diff --git a/.azuredevops/rocm-ci.yml b/.azuredevops/rocm-ci.yml new file mode 100644 index 0000000000000..2be059422043a --- /dev/null +++ b/.azuredevops/rocm-ci.yml @@ -0,0 +1,29 @@ +resources: + repositories: + - repository: pipelines_repo + type: github + endpoint: ROCm + name: ROCm/ROCm + +variables: +- group: common +- template: /.azuredevops/variables-global.yml@pipelines_repo + +trigger: + batch: true + branches: + include: + - amd-staging + - amd-mainline-open + paths: + exclude: + - .ci + - .github + - '*.md' + - '**/*.md' + - LICENSE.TXT + +pr: none + +jobs: + - template: ${{ variables.CI_COMPONENT_PATH }}/llvm-project.yml@pipelines_repo diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 3a0a291ccb24c..3876539652334 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -168,3 +168,8 @@ # libclang/Python bindings /clang/bindings/python @DeinAlptraum + +# AMD-specific projects. +/amd/comgr/ @jlambert_amdeng +/amd/device-libs/ @bsumner_amdeng +/amd/hipcc/ @dsalinas_amdeng diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md new file mode 100644 index 0000000000000..8b137891791fe --- /dev/null +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1 @@ + diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 0000000000000..2ee40d7150c5c --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,27 @@ +version: 2 +updates: + - package-ecosystem: "github-actions" + directory: "/" + schedule: + interval: "monthly" + groups: + github-actions: + patterns: + - "*" + - package-ecosystem: "pip" + directory: "/llvm/docs" + schedule: + interval: "monthly" + groups: + llvm-docs-requirements: + patterns: + - "*" + - package-ecosystem: "pip" # See documentation for possible values + directory: "/amd/hipcc/docs/sphinx" # Location of package manifests + open-pull-requests-limit: 10 + schedule: + interval: "daily" + labels: + - "documentation" + reviewers: + - "samjwu" diff --git a/.github/workflows/PSDB-amd-staging.yml b/.github/workflows/PSDB-amd-staging.yml new file mode 100644 index 0000000000000..e80c4eb39c1ed --- /dev/null +++ b/.github/workflows/PSDB-amd-staging.yml @@ -0,0 +1,107 @@ +name: Compiler CI PSDB trigger on amd-staging branch + +# Controls when the workflow will run +on: + pull_request: + branches: [amd-staging] + types: [opened, reopened, synchronize, ready_for_review] + workflow_dispatch: + +# A workflow run is made up of one or more jobs that can run sequentially or in parallel, below is a single job called invoke jenkins jobs +jobs: + # This workflow contains a single job called "invoke_jenkins_PSDB" + invoke_jenkins_PSDB: + if: github.event.pull_request.draft == false + runs-on: + group: compiler-generic-runners + env: + svc_acc_org_secret: ${{secrets.CI_GITHUB_TOKEN}} + input_sha: ${{ github.event.pull_request.head.sha != '' && github.event.pull_request.head.sha || github.sha }} + input_pr_num: ${{ github.event.pull_request.number != '' && github.event.pull_request.number || 0 }} + input_pr_url: ${{ github.event.pull_request.html_url != '' && github.event.pull_request.html_url || '' }} + input_pr_title: ${{ github.event.pull_request.title != '' && github.event.pull_request.title || '' }} + # set the pipeline name here based on branch name + pipeline_name: ${{secrets.CI_JENKINS_JOB_NAME}} + JENKINS_URL: ${{secrets.CI_JENKINS_URL}} + CONTAINER_IMAGE: ${{ secrets.JENKINS_TRIGGER_DOCKER_IMAGE }} + + # Steps represent a sequence of tasks that will be executed as part of the job + steps: + + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - name: Set environment variable for container image + run: | + echo "CONTAINER_IMAGE=${{ secrets.JENKINS_TRIGGER_DOCKER_IMAGE }}" >> $GITHUB_ENV + echo "CONTAINER_NAME=my_container_${{ github.run_id }}" >> $GITHUB_ENV + + + - name: Pull container image + run: docker pull "${{env.CONTAINER_IMAGE}}" + + + - name: Run container + run: | + docker run -d --name "${{env.CONTAINER_NAME}}" $CONTAINER_IMAGE sleep infinity + #docker exec "${{env.CONTAINER_NAME}}" /bin/bash -c "git clone ${{secrets.CI_UTILS_REPO}} ." + docker exec "${{env.CONTAINER_NAME}}" /bin/bash -c "echo 'Running commands inside the container'" + + - name: Escape pull request title + run: | + import json + import os + import shlex + with open('${{ github.event_path }}') as fh: + event = json.load(fh) + escaped = event['pull_request']['title'] + with open(os.environ['GITHUB_ENV'], 'a') as fh: + print(f'PR_TITLE={escaped}', file=fh) + shell: python3 {0} + + - name: Run Jenkins Cancel Script + env: + JENKINS_URL: ${{secrets.CI_JENKINS_URL}} + JENKINS_USER: ${{secrets.CI_JENKINS_USER}} + JENKINS_API_TOKEN: ${{secrets.CI_JENKINS_TOKEN}} + JENKINS_JOB_NAME: ${{secrets.CI_JENKINS_JOB_NAME}} + PR_NUMBER: ${{ github.event.pull_request.number }} + COMMIT_HASH: ${{ github.event.after }} + run: | + docker exec -e JENKINS_JOB_NAME=${{secrets.CI_JENKINS_JOB_NAME}} -e PR_NUMBER=${{ github.event.pull_request.number }} -e COMMIT_HASH=${{ github.event.after }} -e JENKINS_URL=${{secrets.CI_JENKINS_URL}} -e JENKINS_USER=${{secrets.CI_JENKINS_USER}} -e JENKINS_API_TOKEN=${{secrets.CI_JENKINS_TOKEN}} "${{env.CONTAINER_NAME}}" /bin/bash -c "PYTHONHTTPSVERIFY=0 python3 cancel_previous_build.py" + + + # Runs a set of commands using the runners shell + - name: Getting Event Details + run: | + echo $(pwd) + echo $GITHUB_ENV + echo $GITHUB_REPOSITORY + echo $GITHUB_SERVER_URL + echo "GITHUB_SHA is: $GITHUB_SHA" + echo "GITHUB_WORKFLOW_SHA is: $GITHUB_WORKFLOW_SHA" + echo "GITHUB_BASE_REF is: $GITHUB_BASE_REF" + echo "GITHUB_REF_NAME is: $GITHUB_REF_NAME" + echo "github.event.pull_request.id is: ${{github.event.pull_request.id}}" + echo "github.event.pull_request.html_url is: ${{github.event.pull_request.html_url}}" + echo "github.event.pull_request.number is: ${{github.event.pull_request.number}}" + echo "github.event.pull_request.url is: ${{github.event.pull_request.url}}" + echo "github.event.pull_request.issue_url is: ${{github.event.pull_request.issue_url}}" + echo "github.event.pull_request.head.sha is: ${{github.event.pull_request.head.sha}}" + echo "github.event.pull_request.base.ref is: ${{github.event.pull_request.base.ref}}" + echo "github.event.pull_request.merge_commit_sha is: ${{github.event.pull_request.merge_commit_sha}}" + echo "github.event.pull_request is: ${{github.event.pull_request}}" + + + - name: Trigger Jenkins Pipeline + if: steps.check_changes.outcome != 'failure' + run: | + echo "--Running jenkins_api.py with input sha - $input_sha for pull request - $input_pr_url" + docker exec -e GITHUB_REPOSITORY="$GITHUB_REPOSITORY" -e svc_acc_org_secret="$svc_acc_org_secret" -e input_sha="$input_sha" -e input_pr_url="$input_pr_url" -e pipeline_name="$pipeline_name" \ + -e input_pr_num="$input_pr_num" -e PR_TITLE="$PR_TITLE" -e JENKINS_URL="$JENKINS_URL" -e GITHUB_PAT="$svc_acc_org_secret" "${{env.CONTAINER_NAME}}" \ + /bin/bash -c 'echo \"PR NUM: "$input_pr_num"\" && PYTHONHTTPSVERIFY=0 python3 jenkins_api.py -s \"${JENKINS_URL}\" -jn "$pipeline_name" -ghr "$GITHUB_REPOSITORY" -ghsha "$input_sha" -ghprn "$input_pr_num" -ghpru "$input_pr_url" -ghprt "$PR_TITLE" -ghpat="$svc_acc_org_secret"' + + - name: Stop and remove container + if: always() + run: | + docker stop "${{env.CONTAINER_NAME}}" + docker rm "${{env.CONTAINER_NAME}}" + diff --git a/.github/workflows/buildbot-psdb-trigger.yml b/.github/workflows/buildbot-psdb-trigger.yml new file mode 100644 index 0000000000000..471fd4001ae84 --- /dev/null +++ b/.github/workflows/buildbot-psdb-trigger.yml @@ -0,0 +1,135 @@ +name: Trigger amd-debug Buildbot Build +on: + workflow_dispatch: + pull_request: + branches: [amd-debug] + types: [opened, reopened, synchronize, ready_for_review] + + +jobs: + trigger-build: + if: github.event.pull_request.draft == false + runs-on: + group: compiler-generic-runners + env: + PR_SHA: ${{ github.event.pull_request.head.sha != '' && github.event.pull_request.head.sha || github.sha }} + PR_NUMBER: ${{ github.event.pull_request.number != '' && github.event.pull_request.number || 0 }} + PR_URL: ${{ github.event.pull_request.html_url != '' && github.event.pull_request.html_url || '' }} + PR_TITLE: ${{ github.event.pull_request.title != '' && github.event.pull_request.title || '' }} + BASE_BRANCH: ${{ github.event.pull_request.base.ref != '' && github.event.pull_request.base.ref || '' }} + GITHUB_TOKEN: ${{secrets.CI_GITHUB_TOKEN}} + + steps: + # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it + - name: Set environment variable for container image + run: | + echo "CONTAINER_IMAGE=${{ secrets.BUILDBOT_DOCKER_IMAGE }}" >> $GITHUB_ENV + echo "CONTAINER_NAME=my_container_${{ github.run_id }}" >> $GITHUB_ENV + + - name: Pull container image + run: docker pull "${{env.CONTAINER_IMAGE}}" + + - name: Run container + run: | + docker run -d --name "${{env.CONTAINER_NAME}}" $CONTAINER_IMAGE sleep infinity + docker exec "${{env.CONTAINER_NAME}}" /bin/bash -c "echo 'Running commands inside the container'" + + - name: Escape pull request title + run: | + import json + import os + import shlex + with open('${{ github.event_path }}') as fh: + event = json.load(fh) + escaped = event['pull_request']['title'] + with open(os.environ['GITHUB_ENV'], 'a') as fh: + print(f'PR_TITLE={escaped}', file=fh) + shell: python3 {0} + + - name: Trigger Buildbot Build + run: | + echo "${{ secrets.BUILDBOT_HOST }}:${{ secrets.BUILDBOT_WORKER_PORT }}" + docker exec -e PR_TITLE="$PR_TITLE" "${{env.CONTAINER_NAME}}" /bin/bash -c 'buildbot sendchange -W ${{ secrets.BUILDBOT_USER }} -a ${{secrets.BUILDBOT_USER}}:${{secrets.BUILDBOT_PWD}} --master="${{ secrets.BUILDBOT_HOST }}:${{ secrets.BUILDBOT_WORKER_PORT }}" --branch=${{ env.BASE_BRANCH }} --revision=${{ env.PR_SHA }} -p PR_NUMBER:${{ env.PR_NUMBER }} -p PR_TITLE:"$PR_TITLE" -p PR_URL:${{ env.PR_URL }} -p SHA:${{ env.PR_SHA }}' + + - name: Set Initial Status to Pending + run: | + docker exec -e PR_SHA=$PR_SHA -e GITHUB_TOKEN=$GITHUB_TOKEN "${{env.CONTAINER_NAME}}" /bin/bash -c "python3 -c \" + import os + import requests + GITHUB_TOKEN = os.getenv('GITHUB_TOKEN') + TARGET_SHA = os.getenv('PR_SHA') + print('debug', TARGET_SHA) + api_url = f'https://api.github.com/repos/AMD-Lightning-Internal/llvm-project/statuses/{TARGET_SHA}' + headers = { + 'Authorization': f'token {GITHUB_TOKEN}', + 'Content-Type': 'application/json' + } + payload = { + 'state': 'pending', + 'context': 'buildbot', + 'description': 'Build is in queue' + } + response = requests.post(api_url, json=payload, headers=headers) + if response.status_code == 201: + print('Status set to pending successfully.') + else: + print(f'Failed to set status: {response.status_code} {response.text}') + \"" + + - name: Poll Buildbot build status + run: | + python3 -c " + import os + import time + import requests + GITHUB_TOKEN = os.getenv('GITHUB_TOKEN') + BUILD_URL = 'http://${{ secrets.BUILDBOT_HOST }}:${{ secrets.BUILDBOT_MASTER_PORT }}/api/v2/builds' + TARGET_SHA = os.getenv('PR_SHA') + print('debug', TARGET_SHA) + MAX_RETRIES = 10 + RETRY_INTERVAL = 30 # seconds + + def get_build_properties(build_id): + build_properties_url = f'http://${{ secrets.BUILDBOT_HOST }}:${{ secrets.BUILDBOT_MASTER_PORT }}/api/v2/builds/{build_id}/properties' + response = requests.get(build_properties_url, headers={'Accept': 'application/json', 'Authorization': f'token {GITHUB_TOKEN}'}) + return response.json() + + for i in range(MAX_RETRIES): + response = requests.get(BUILD_URL, headers={'Accept': 'application/json'}) + response_json = response.json() + print(f'Attempt {i + 1}: Buildbot response:', response_json) + + # Check if any build has the target SHA + builds = response_json.get('builds', []) + print (builds) + build_with_sha = None + for build in builds: + build_id = build['buildid'] + properties = get_build_properties(build_id) + #print(properties) + #prop = properties.get('revision', []) + + if 'properties' in properties: + print (properties['properties']) + if 'revision' in properties['properties'][0]: + print(properties['properties'][0]) + if 'revision' in properties['properties'][0] and properties['properties'][0]['revision'] [0] == TARGET_SHA: + build_with_sha = build + break + + if build_with_sha: + print('Build started successfully for SHA:', TARGET_SHA) + break + else: + print('Build for SHA not started yet, retrying in', RETRY_INTERVAL, 'seconds') + time.sleep(RETRY_INTERVAL) + else: + print('Build did not start for SHA:', TARGET_SHA, 'after maximum retries') + exit(1) + " + + - name: Stop and remove container + if: always() + run: | + docker stop "${{env.CONTAINER_NAME}}" + docker rm "${{env.CONTAINER_NAME}}" diff --git a/.github/workflows/compute-rocm-dkmd-afar-trigger.yml b/.github/workflows/compute-rocm-dkmd-afar-trigger.yml new file mode 100644 index 0000000000000..c44027fc3474f --- /dev/null +++ b/.github/workflows/compute-rocm-dkmd-afar-trigger.yml @@ -0,0 +1,79 @@ +name: Trigger compute-rocm-dkms-afar job on push + +on: + push: # This triggers the workflow on push events + branches: + - amd-staging + workflow_dispatch: # This allows manual triggering of the workflow + +jobs: + trigger_jenkins: + runs-on: + group: compiler-generic-runners + + steps: + - name: Set environment variable for container image + run: | + echo "CONTAINER_IMAGE=${{ secrets.JENKINS_TRIGGER_DOCKER_IMAGE }}" >> $GITHUB_ENV + echo "CONTAINER_NAME=my_container_${{ github.run_id }}" >> $GITHUB_ENV + + - name: Pull container image + run: docker pull "${{env.CONTAINER_IMAGE}}" + + - name: Run container + run: | + docker run -d --name "${{env.CONTAINER_NAME}}" $CONTAINER_IMAGE sleep infinity + docker exec "${{env.CONTAINER_NAME}}" /bin/bash -c "echo 'Running commands inside the container'" + + - name: Trigger compute-rocm-dkms-afar job + run: | + docker exec "${{env.CONTAINER_NAME}}" /bin/bash -c "python -c \" + import requests + import time + from requests.auth import HTTPBasicAuth + + jenkins_user = '${{ secrets.CI_JENKINS_USER }}' + jenkins_token = '${{ secrets.ROCM_JENKINS_CI_TOKEN }}' + jenkins_host = '${{ secrets.ROCM_JENKINS_HOST }}' + jenkins_job = '${{ secrets.ROCM_JENKINS_OSDB_JOB }}' + + jenkins_url = f'{jenkins_host}/job/{jenkins_job}/buildWithParameters' + + response = requests.post(jenkins_url, auth=HTTPBasicAuth(jenkins_user, jenkins_token)) + + if response.status_code == 201: + print('Jenkins job triggered successfully!') + queue_url = response.headers.get('Location') + if queue_url: + print(f'Queue URL: {queue_url}') + print(f'Getting build URL(max 5 attempts with 10seconds interval)...') + # Poll the queue item to get the build number, limited to 5 attempts + max_attempts = 5 + attempts = 0 + while attempts < max_attempts: + queue_response = requests.get(queue_url + 'api/json', auth=HTTPBasicAuth(jenkins_user, jenkins_token)) + queue_data = queue_response.json() + if 'executable' in queue_data: + build_number = queue_data['executable']['number'] + build_url = f'{jenkins_host}/job/{jenkins_job}/{build_number}/' + print(f'Build URL: {build_url}') + break + attempts += 1 + time.sleep(10) # Wait for 10 seconds before polling again + else: + print('Exceeded maximum attempts to get the build URL. The trigger happened, so not failing the workflow') + else: + print('Build URL not found in the response headers.') + + elif response.status_code == 200: + print('Request was successful, but check the response content for details.') + print(response.text) + else: + print(f'Failed to trigger Jenkins job. Status code: {response.status_code}') + \"" + + - name: Stop and remove container + if: always() + run: | + docker stop "${{env.CONTAINER_NAME}}" + docker rm "${{env.CONTAINER_NAME}}" diff --git a/README.md b/README.md index a9b29ecbc1a3a..43bf0b8e9f5f4 100644 --- a/README.md +++ b/README.md @@ -1,44 +1,23 @@ -# The LLVM Compiler Infrastructure +# AMD Fork of The LLVM Compiler Infrastructure +# -[![OpenSSF Scorecard](https://api.securityscorecards.dev/projects/github.com/llvm/llvm-project/badge)](https://securityscorecards.dev/viewer/?uri=github.com/llvm/llvm-project) -[![OpenSSF Best Practices](https://www.bestpractices.dev/projects/8273/badge)](https://www.bestpractices.dev/projects/8273) -[![libc++](https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml/badge.svg?branch=main&event=schedule)](https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml?query=event%3Aschedule) +The AMD fork aims to contain all of [upstream LLVM](https://github.com/llvm/llvm-project), and also includes several AMD-specific additions in the `llvm-project/amd` directory: -Welcome to the LLVM project! +- **amd/comgr** - The Code Object Manager API, designed to simplify linking, compiling, and inspecting code objects (code owner: [@lamb-j](https://www.github.com/lamb-j)) +- **amd/device-libs** -The sources and CMake build system for a set of AMD-specific device-side language runtime libraries (code owner: [@b-sumner](https://www.github.com/b-sumner)) +- **amd/hipcc** - A compiler driver utility that wraps clang and passes the appropriate include and library options for the target compiler and HIP infrastructure (code owner: [@david-salinas](https://www.github.com/david-salinas)) -This repository contains the source code for LLVM, a toolkit for the -construction of highly optimized compilers, optimizers, and run-time -environments. +See the README files in respective subdirectories for more information on these AMD-specific projects. While the AMD fork aims to otherwise follow upstream as closely as possible, there are several outstanding differences. -The LLVM project has multiple components. The core of the project is -itself called "LLVM". This contains all of the tools, libraries, and header -files needed to process intermediate representations and convert them into -object files. Tools include an assembler, disassembler, bitcode analyzer, and -bitcode optimizer. +- *OpenMP* - The AMD fork contains several changes: + * Additional optimizations for OpenMP offload + * Host-exec services for printing on-device and doing malloc/free from device + * Improved support for OMPT, the OpenMP tools interface + * Driver improvements for multi-image and Target ID features + * OMPD support, implements OpenMP D interfaces. + * ASAN support for OpenMP. + * MI300A Unified Shared Memory support -C-like languages use the [Clang](https://clang.llvm.org/) frontend. This -component compiles C, C++, Objective-C, and Objective-C++ code into LLVM bitcode --- and from there into object files, using LLVM. - -Other components include: -the [libc++ C++ standard library](https://libcxx.llvm.org), -the [LLD linker](https://lld.llvm.org), and more. - -## Getting the Source Code and Building LLVM - -Consult the -[Getting Started with LLVM](https://llvm.org/docs/GettingStarted.html#getting-the-source-code-and-building-llvm) -page for information on building and running LLVM. - -For information on how to contribute to the LLVM project, please take a look at -the [Contributing to LLVM](https://llvm.org/docs/Contributing.html) guide. - -## Getting in touch - -Join the [LLVM Discourse forums](https://discourse.llvm.org/), [Discord -chat](https://discord.gg/xS7Z362), -[LLVM Office Hours](https://llvm.org/docs/GettingInvolved.html#office-hours) or -[Regular sync-ups](https://llvm.org/docs/GettingInvolved.html#online-sync-ups). - -The LLVM project has adopted a [code of conduct](https://llvm.org/docs/CodeOfConduct.html) for -participants to all modes of communication within the project. +- *Heterogeneous Debugging* - A prototype of debug-info supporting AMDGPU targets, affecting most parts of the compiler, is implemented as documented in `docs/AMDGPULLVMExtensionsForHeterogeneousDebugging.rst` but is an ongoing work-in-progress. Fundamental changes are expected as parts of the design are adapted for upstreaming. +- *Address Sanitizer* - Changes were added to `santizer_common` and `asan` libraries in `compiler-rt` to support AMD GPU address sanitizer error detection and reports. These changes are intended to be upstreamed. The instrumentation pass changes have already been upstreamed. +- *Reverted Patches* - For upstream patches that break internal testing, we may temporarily revert these patches until the testing issues are resolved. We maintain a list of reverted upstream patches in `llvm-project/revert_patches.txt`. diff --git a/amd/README.md b/amd/README.md new file mode 100644 index 0000000000000..6ce5629475359 --- /dev/null +++ b/amd/README.md @@ -0,0 +1,27 @@ +# AMD subprojects + +This directory and its subdirectories contain source code for AMD open-source +projects which are tightly-coupled to LLVM project infrastructure, such that +there is no well-defined interface or versioning guarantees maintained which +make it useful to develop them in separate repositories. + +These projects are either fundamentally unsuitable for direct contribution to +the LLVM project itself, are currently not in a state where the community is +likely to accept them directly, or AMD is not currently prepared to undergo the +upstreaming process for them. In any case, their current home in this distinct +top-level subdirectory is intended to namespace them such that there is no +possibility for conflict with upstream sources, and to leave open a path to +contributing them upstream where possible. + +Most (and at the time of writing, currently all) of these projects were +originally developed in separate repositories. Their history was maintained as +parents of an octopus merge which introduced this subdirectory. A modified +script which was used to perform the merge is retained in the `utils` +subdirectory as `omnibus.sh` for historical interest, and to aid in any +external developer's transition. + +Also available is a more general-purpose script, +`translate-legacy-branch-to-omnibus-monorepo.sh`, which can be used by external +developers to "translate" any branch made against the separate repositories +into a clone of llvm-project. For usage instructions please run the script with +no arguments. diff --git a/amd/comgr/.clang-format b/amd/comgr/.clang-format new file mode 100644 index 0000000000000..5bead5f39dd3c --- /dev/null +++ b/amd/comgr/.clang-format @@ -0,0 +1,2 @@ +BasedOnStyle: LLVM + diff --git a/amd/comgr/.clang-tidy b/amd/comgr/.clang-tidy new file mode 100644 index 0000000000000..08bdff3ecc5ce --- /dev/null +++ b/amd/comgr/.clang-tidy @@ -0,0 +1,17 @@ +Checks: '-*,clang-diagnostic-*,llvm-*,-llvm-header-guard,misc-*,-misc-unused-parameters,-misc-non-private-member-variables-in-classes,readability-identifier-naming,readability-braces-around-statements' +CheckOptions: + - key: readability-identifier-naming.ClassCase + value: CamelCase + - key: readability-identifier-naming.EnumCase + value: CamelCase + - key: readability-identifier-naming.FunctionCase + value: camelBack + - key: readability-identifier-naming.MemberCase + value: CamelCase + - key: readability-identifier-naming.ParameterCase + value: CamelCase + - key: readability-identifier-naming.UnionCase + value: CamelCase + - key: readability-identifier-naming.VariableCase + value: CamelCase + diff --git a/amd/comgr/.git-blame-ignore-revs b/amd/comgr/.git-blame-ignore-revs new file mode 100644 index 0000000000000..d93fa98728657 --- /dev/null +++ b/amd/comgr/.git-blame-ignore-revs @@ -0,0 +1,2 @@ +822a667bf0fc6149513661ee175b187341ef1691 +3cf20b0d3ac4aaaff58116f152b3d15dcca92712 diff --git a/amd/comgr/.gitignore b/amd/comgr/.gitignore new file mode 100644 index 0000000000000..7a43d55bc2759 --- /dev/null +++ b/amd/comgr/.gitignore @@ -0,0 +1,4 @@ +.* +!.gitignore +build +compile_commands.json diff --git a/amd/comgr/CMakeLists.txt b/amd/comgr/CMakeLists.txt new file mode 100644 index 0000000000000..21a544402c48a --- /dev/null +++ b/amd/comgr/CMakeLists.txt @@ -0,0 +1,620 @@ +cmake_minimum_required(VERSION 3.13.4) + +file(READ "VERSION.txt" comgr_ver_file) + +string(REGEX MATCH "#COMGR_VERSION_MAJOR\n([0-9]*)" _ ${comgr_ver_file}) +set (ver_major ${CMAKE_MATCH_1}) +string(REGEX MATCH "#COMGR_VERSION_MINOR\n([0-9]*)" _ ${comgr_ver_file}) +set (ver_minor ${CMAKE_MATCH_1}) + +message("Comgr Version: ${ver_major}.${ver_minor}.0") + +project(amd_comgr VERSION "${ver_major}.${ver_minor}.0" LANGUAGES C CXX) +set(amd_comgr_NAME "${PROJECT_NAME}") + +# Get git branch and commit hash to add to log for easier debugging. +execute_process( + COMMAND git log -1 --format=%h + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + OUTPUT_VARIABLE AMD_COMGR_GIT_COMMIT + OUTPUT_STRIP_TRAILING_WHITESPACE + RESULT_VARIABLE GIT_REV_PARSE_EXITCODE +) + +if (${GIT_REV_PARSE_EXITCODE} EQUAL 0) + execute_process( + COMMAND git log -1 --format=%h + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + OUTPUT_VARIABLE AMD_COMGR_GIT_COMMIT + OUTPUT_STRIP_TRAILING_WHITESPACE + ) + execute_process( + COMMAND git name-rev --name-only HEAD + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + OUTPUT_VARIABLE AMD_COMGR_GIT_BRANCH + OUTPUT_STRIP_TRAILING_WHITESPACE + ) +else() + set(AMD_COMGR_GIT_BRANCH "not-available") + set(AMD_COMGR_GIT_COMMIT "not-available") +endif() + +include(GNUInstallDirs) +include(CMakePackageConfigHelpers) +# Optionally, build Compiler Support with ccache. +set(ROCM_CCACHE_BUILD OFF CACHE BOOL "Set to ON for a ccache enabled build") +if (ROCM_CCACHE_BUILD) + find_program(CCACHE_PROGRAM ccache) + if (CCACHE_PROGRAM) + set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE ${CCACHE_PROGRAM}) + else() + message(WARNING "Unable to find ccache. Falling back to real compiler") + endif() # if (CCACHE_PROGRAM) +endif() # if (ROCM_CCACHE_BUILD) + +# BUILD_SHARED_LIBS is a frustratingly global variable common to all +# projects. LLVM also defines an option for the same varible with the +# opposite default, which will overwrite our default preference +# here. Ignore the regular BUILD_SHARED_LIBS in an embedded llvm +# build. Try to use BUILD_SHARED_LIBS to hint our project specific +# version in a standalone build. +set(build_shared_libs_default ON) +if(NOT DEFINED LLVM_SOURCE_DIR AND DEFINED BUILD_SHARED_LIBS) + set(build_shared_libs_default ${BUILD_SHARED_LIBS}) +endif() + +option(COMGR_BUILD_SHARED_LIBS "Build the shared library" + ${build_shared_libs_default}) + +set(SOURCES + src/comgr-cache.cpp + src/comgr-cache-command.cpp + src/comgr-clang-command.cpp + src/comgr-compiler.cpp + src/comgr.cpp + src/comgr-device-libs.cpp + src/comgr-diagnostic-handler.cpp + src/comgr-disassembly.cpp + src/comgr-env.cpp + src/comgr-metadata.cpp + src/comgr-signal.cpp + src/comgr-spirv-command.cpp + src/comgr-symbol.cpp + src/comgr-symbolizer.cpp + src/comgr-unbundle-command.cpp + src/time-stat/time-stat.cpp) + +if(COMGR_BUILD_SHARED_LIBS) + add_library(amd_comgr SHARED ${SOURCES}) + # Windows doesn't have a strip utility, so CMAKE_STRIP won't be set. + if((CMAKE_BUILD_TYPE STREQUAL "Release") AND NOT ("${CMAKE_STRIP}" STREQUAL "")) + if (APPLE) + # Building on Mac fails unless -x is passed to the strip command + add_custom_command(TARGET amd_comgr POST_BUILD COMMAND ${CMAKE_STRIP} -x $) + else() + add_custom_command(TARGET amd_comgr POST_BUILD COMMAND ${CMAKE_STRIP} $) + endif() + endif() +else() + add_library(amd_comgr STATIC ${SOURCES}) +endif() + +if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) + find_package(AMDDeviceLibs REQUIRED CONFIG) + find_package(Clang REQUIRED CONFIG) + find_package(LLD REQUIRED CONFIG) + + target_include_directories(amd_comgr + PRIVATE + ${LLVM_INCLUDE_DIRS} + ${CLANG_INCLUDE_DIRS} + ${LLD_INCLUDE_DIRS}) +else() + # If building with LLVM_EXTERNAL_PROJECTS, we've already picked up + # the include directories for LLVM, but not clang. + # + if (LLVM_EXTERNAL_CLANG_SOURCE_DIR) + target_include_directories(amd_comgr + PRIVATE + ${LLVM_EXTERNAL_CLANG_SOURCE_DIR}/include + ${LLVM_BINARY_DIR}/tools/clang/include) + endif() + + if (LLVM_EXTERNAL_LLD_SOURCE_DIR) + target_include_directories(amd_comgr + PRIVATE + ${LLVM_EXTERNAL_LLD_SOURCE_DIR}/include + ${LLVM_BINARY_DIR}/tools/lld/include) + endif() + + if (LLVM_EXTERNAL_SPIRV_LLVM_TRANSLATOR_SOURCE_DIR) + target_include_directories(amd_comgr + PRIVATE + ${LLVM_EXTERNAL_SPIRV_LLVM_TRANSLATOR_SOURCE_DIR}/include) + endif() +endif() + +target_include_directories(amd_comgr + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/src) + +message("") +message("------------LLVM_DIR: ${LLVM_DIR}") +message("---LLVM_INCLUDE_DIRS: ${LLVM_INCLUDE_DIRS}") +message("---LLVM_LIBRARY_DIRS: ${LLVM_LIBRARY_DIRS}") +message("-----------Clang_DIR: ${Clang_DIR}") +message("--CLANG_INCLUDE_DIRS: ${CLANG_INCLUDE_DIRS}") +message("----LLD_INCLUDE_DIRS: ${LLD_INCLUDE_DIRS}") +message("---AMDDeviceLibs_DIR: ${AMDDeviceLibs_DIR}") + +list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake") + +if (ADDRESS_SANITIZER) + set(ASAN_LINKER_FLAGS "-fsanitize=address") + set(ASAN_COMPILER_FLAGS "-fno-omit-frame-pointer -fsanitize=address") + + if (NOT CMAKE_COMPILER_IS_GNUCC) + if (COMGR_BUILD_SHARED_LIBS) + set(ASAN_LINKER_FLAGS "${ASAN_LINKER_FLAGS} -shared-libsan") + else() + set(ASAN_LINKER_FLAGS "${ASAN_LINKER_FLAGS} -static-libsan") + endif() + endif() + + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${ASAN_COMPILER_FLAGS}") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${ASAN_COMPILER_FLAGS}") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${ASAN_LINKER_FLAGS} -s") + set(CMAKE_SHARED_LINKER_FLAGS + "${CMAKE_SHARED_LINKER_FLAGS} ${ASAN_LINKER_FLAGS}") +endif() + +set(AMD_COMGR_PRIVATE_COMPILE_OPTIONS) +set(AMD_COMGR_PRIVATE_COMPILE_DEFINITIONS ${LLVM_DEFINITIONS}) +set(AMD_COMGR_PUBLIC_LINKER_OPTIONS) +set(AMD_COMGR_PRIVATE_LINKER_OPTIONS) + +list(APPEND AMD_COMGR_PRIVATE_COMPILE_DEFINITIONS "AMD_COMGR_GIT_COMMIT=${AMD_COMGR_GIT_COMMIT}") +list(APPEND AMD_COMGR_PRIVATE_COMPILE_DEFINITIONS "AMD_COMGR_GIT_BRANCH=${AMD_COMGR_GIT_BRANCH}") +message("----COMGR_GIT_COMMIT: ${AMD_COMGR_GIT_COMMIT}") +message("----COMGR_GIT_BRANCH: ${AMD_COMGR_GIT_BRANCH}") +message("") + +option(COMGR_DISABLE_SPIRV "To disable SPIRV in Comgr" OFF) + +if (NOT COMGR_DISABLE_SPIRV) + # Candidate include paths for LLVMSPIRVLib.h: + # 1. ${LLVM_INCLUDE_DIRS}/LLVMSPIRVLib (standalone build) + # 2. ${LLVM_EXTERNAL_SPIRV_LLVM_TRANSLATOR_SOURCE_DIR}/include (external project) + # 3. ${CMAKE_SOURCE_DIR}/projects/SPIRV-LLVM-Translator/include (usual location) + find_path( + FOUND_SPIRV_INCLUDE_DIR + LLVMSPIRVLib.h + PATHS + "${LLVM_INCLUDE_DIRS}/LLVMSPIRVLib" + "${LLVM_EXTERNAL_SPIRV_LLVM_TRANSLATOR_SOURCE_DIR}/include" + "${CMAKE_SOURCE_DIR}/projects/SPIRV-LLVM-Translator/include" + NO_DEFAULT_PATH + ) + if (NOT EXISTS "${FOUND_SPIRV_INCLUDE_DIR}/LLVMSPIRVLib.h") + message("-- LLVMSPIRVLib/LLVMSPIRVLib.h not found") + set(COMGR_DISABLE_SPIRV ON) + else() + message("-- LLVMSPIRVLib/LLVMSPIRVLib.h found at ${FOUND_SPIRV_INCLUDE_DIR}") + endif() +endif() + +if(${COMGR_DISABLE_SPIRV}) + list(APPEND AMD_COMGR_PRIVATE_COMPILE_DEFINITIONS "COMGR_DISABLE_SPIRV") + message("-- Comgr SPIRV Disabled") +else() + message("-- Comgr SPIRV Enabled") + target_include_directories(amd_comgr + PRIVATE + "${FOUND_SPIRV_INCLUDE_DIR}") +endif() + + +if (UNIX) + list(APPEND AMD_COMGR_PRIVATE_COMPILE_OPTIONS + -fno-rtti -Wall -Wno-attributes -fms-extensions -fvisibility=hidden) + # TODO: Confirm this is actually needed due to LLVM/Clang code + list(APPEND AMD_COMGR_PRIVATE_COMPILE_OPTIONS -fno-strict-aliasing) + list(APPEND AMD_COMGR_PRIVATE_COMPILE_DEFINITIONS + _GNU_SOURCE __STDC_LIMIT_MACROS __STDC_CONSTANT_MACROS AMD_COMGR_BUILD) + list(APPEND AMD_COMGR_PUBLIC_LINKER_OPTIONS -pthread) + if (NOT APPLE AND COMGR_BUILD_SHARED_LIBS) + configure_file( + src/exportmap.in + src/exportmap @ONLY) + list(APPEND AMD_COMGR_PRIVATE_LINKER_OPTIONS + "-Wl,--version-script=${CMAKE_CURRENT_BINARY_DIR}/src/exportmap") + # When building a shared library with -fsanitize=address we can't be + # strict about undefined symbol references, as Clang won't include + # libasan in the link, see + # https://clang.llvm.org/docs/AddressSanitizer.html + if (NOT ADDRESS_SANITIZER) + list(APPEND AMD_COMGR_PRIVATE_LINKER_OPTIONS + -Wl,--no-undefined) + endif() + endif() +elseif (CMAKE_CXX_COMPILER_ID STREQUAL "MSVC") + list(APPEND AMD_COMGR_PRIVATE_COMPILE_OPTIONS + "/wd4244" #[[Suppress 'argument' : conversion from 'type1' to 'type2', possible loss of data]] + "/wd4624" #[[Suppress 'derived class' : destructor could not be generated because a base class destructor is inaccessible]] + "/wd4267" #[[Suppress 'var' : conversion from 'size_t' to 'type', possible loss of data]] + "/wd4291" #[[Suppress 'declaration' : no matching operator delete found; memory will not be freed if initialization throws an exception]] + "/wd4146" #[[Suppress 'unary minus operator applied to unsigned type, result still unsigned]] + "/Zc:preprocessor" #[[Enable standards conforming preprocessor - https://learn.microsoft.com/en-us/cpp/build/reference/zc-preprocessor]]) + list(APPEND AMD_COMGR_PRIVATE_COMPILE_DEFINITIONS _HAS_EXCEPTIONS=0) +endif() + +# Windows is strict about visibility of exports in shared libraries, so we ask +# GCC/Clang to also be strict, and then explicitly mark each exported symbol in +# the shared header. +list(APPEND AMD_COMGR_PRIVATE_COMPILE_DEFINITIONS AMD_COMGR_EXPORT) + +include(bc2h) +include(opencl_header) +include(DeviceLibs) + +# Add major version to the name on windows, including Win64 +if (WIN32) + set_target_properties(amd_comgr PROPERTIES + OUTPUT_NAME "amd_comgr_${amd_comgr_VERSION_MAJOR}") +endif() + +set_target_properties(amd_comgr PROPERTIES + CXX_STANDARD 17 + CXX_STANDARD_REQUIRED Yes + CXX_EXTENSIONS No) +set_target_properties(amd_comgr PROPERTIES + SOVERSION "${amd_comgr_VERSION_MAJOR}" + VERSION "${amd_comgr_VERSION_MAJOR}.${amd_comgr_VERSION_MINOR}.${amd_comgr_VERSION_PATCH}") + +if (NOT COMGR_BUILD_SHARED_LIBS) + set_target_properties(amd_comgr PROPERTIES POSITION_INDEPENDENT_CODE ON) +endif() + +# Overwrite the name on 32-bit Linux and Windows +if (CMAKE_SIZEOF_VOID_P EQUAL 4) + set_target_properties(amd_comgr PROPERTIES OUTPUT_NAME "amd_comgr32") +endif() + +option(LLVM_BUILD_INSTRUMENTED_COVERAGE "Build LLVM and tools with Code Coverage instrumentation" Off) +mark_as_advanced(LLVM_BUILD_INSTRUMENTED_COVERAGE) +if(LLVM_BUILD_INSTRUMENTED_COVERAGE) + if(NOT LLVM_PROFILE_MERGE_POOL_SIZE) + # A pool size of 1-2 is probably sufficient on an SSD. 3-4 should be fine + # for spinning disks. Anything higher may only help on slower mediums. + set(LLVM_PROFILE_MERGE_POOL_SIZE "4") + endif() + if(NOT LLVM_PROFILE_FILE_PATTERN) + if(NOT LLVM_PROFILE_DATA_DIR) + file(TO_NATIVE_PATH "${LLVM_BINARY_DIR}/profiles" LLVM_PROFILE_DATA_DIR) + endif() + file(TO_NATIVE_PATH "${LLVM_PROFILE_DATA_DIR}/%${LLVM_PROFILE_MERGE_POOL_SIZE}m.profraw" LLVM_PROFILE_FILE_PATTERN) + endif() + set(INSTRUMENTED_COVERAGE_FLAGS -O0 -fprofile-instr-generate=${LLVM_PROFILE_FILE_PATTERN} -fcoverage-mapping) + list(APPEND AMD_COMGR_PRIVATE_COMPILE_OPTIONS ${INSTRUMENTED_COVERAGE_FLAGS}) + list(APPEND AMD_COMGR_PUBLIC_COMPILE_OPTIONS ${INSTRUMENTED_COVERAGE_FLAGS}) + list(APPEND AMD_COMGR_PRIVATE_LINKER_OPTIONS ${INSTRUMENTED_COVERAGE_FLAGS} -L${LLVM_LIBRARY_DIRS}) + list(APPEND AMD_COMGR_PUBLIC_LINKER_OPTIONS ${INSTRUMENTED_COVERAGE_FLAGS} -L${LLVM_LIBRARY_DIRS}) +endif() + +target_compile_options(amd_comgr + PRIVATE "${AMD_COMGR_PRIVATE_COMPILE_OPTIONS}") +target_compile_definitions(amd_comgr + PRIVATE "${AMD_COMGR_PRIVATE_COMPILE_DEFINITIONS}") +target_include_directories(amd_comgr + PUBLIC + $ + $) + +configure_file( + include/amd_comgr.h.in + include/amd_comgr.h @ONLY) + +set(AMD_COMGR_CONFIG_NAME amd_comgr-config.cmake) +set(AMD_COMGR_TARGETS_NAME amd_comgr-targets.cmake) +set(AMD_COMGR_VERSION_NAME amd_comgr-config-version.cmake) +set(AMD_COMGR_PACKAGE_PREFIX cmake/amd_comgr) + +# Generate the build-tree package. +set(AMD_COMGR_PREFIX_CODE) +if (NOT COMGR_BUILD_SHARED_LIBS) + string(APPEND AMD_COMGR_PREFIX_CODE "\ninclude(CMakeFindDependencyMacro)\n") + string(APPEND AMD_COMGR_PREFIX_CODE "find_dependency(Clang REQUIRED)\n") + string(APPEND AMD_COMGR_PREFIX_CODE "find_dependency(LLD REQUIRED)\n") +endif() + +set(AMD_COMGR_TARGETS_PATH + "${CMAKE_CURRENT_BINARY_DIR}/lib/${AMD_COMGR_PACKAGE_PREFIX}/${AMD_COMGR_TARGETS_NAME}") +set(AMD_COMGR_VERSION_PATH + "${CMAKE_CURRENT_BINARY_DIR}/lib/${AMD_COMGR_PACKAGE_PREFIX}/${AMD_COMGR_VERSION_NAME}") +export(TARGETS amd_comgr + FILE "lib/${AMD_COMGR_PACKAGE_PREFIX}/${AMD_COMGR_TARGETS_NAME}") +configure_file("cmake/${AMD_COMGR_CONFIG_NAME}.in" + "lib/${AMD_COMGR_PACKAGE_PREFIX}/${AMD_COMGR_CONFIG_NAME}" + @ONLY) +write_basic_package_version_file("${AMD_COMGR_VERSION_PATH}" + VERSION "${amd_comgr_VERSION}" + COMPATIBILITY SameMajorVersion) + +if(ENABLE_ASAN_PACKAGING) + install(TARGETS amd_comgr + EXPORT amd_comgr_export + COMPONENT asan + LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}) +else() + install(TARGETS amd_comgr + EXPORT amd_comgr_export + COMPONENT amd-comgr + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} + LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} + ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) +endif() + +install(FILES + "${CMAKE_CURRENT_BINARY_DIR}/include/amd_comgr.h" + COMPONENT amd-comgr + DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${amd_comgr_NAME}) + +if(ENABLE_ASAN_PACKAGING) + install(FILES + "LICENSE.txt" + COMPONENT asan + DESTINATION ${CMAKE_INSTALL_DOCDIR}-asan) +else() + install(FILES + "README.md" + "LICENSE.txt" + COMPONENT amd-comgr + DESTINATION ${CMAKE_INSTALL_DOCDIR}) +endif() + +# Generate the install-tree package. +set(AMD_COMGR_PREFIX_CODE " +# Derive absolute install prefix from config file path. +get_filename_component(AMD_COMGR_PREFIX \"\${CMAKE_CURRENT_LIST_FILE}\" PATH)") +string(REGEX REPLACE "/" ";" count "${CMAKE_INSTALL_LIBDIR}/${AMD_COMGR_PACKAGE_PREFIX}") +foreach(p ${count}) + set(AMD_COMGR_PREFIX_CODE "${AMD_COMGR_PREFIX_CODE} +get_filename_component(AMD_COMGR_PREFIX \"\${AMD_COMGR_PREFIX}\" PATH)") +endforeach() + +if (NOT COMGR_BUILD_SHARED_LIBS) + string(APPEND AMD_COMGR_PREFIX_CODE "\ninclude(CMakeFindDependencyMacro)\n") + string(APPEND AMD_COMGR_PREFIX_CODE "find_dependency(Clang REQUIRED)\n") + string(APPEND AMD_COMGR_PREFIX_CODE "find_dependency(LLD REQUIRED)\n") +endif() + +set(AMD_COMGR_TARGETS_PATH "\${AMD_COMGR_PREFIX}/${CMAKE_INSTALL_LIBDIR}/${AMD_COMGR_PACKAGE_PREFIX}/${AMD_COMGR_TARGETS_NAME}") +configure_file("cmake/${AMD_COMGR_CONFIG_NAME}.in" + "${AMD_COMGR_CONFIG_NAME}.install" + @ONLY) +install(FILES + "${CMAKE_CURRENT_BINARY_DIR}/${AMD_COMGR_CONFIG_NAME}.install" + COMPONENT amd-comgr + DESTINATION "${CMAKE_INSTALL_LIBDIR}/${AMD_COMGR_PACKAGE_PREFIX}" + RENAME "${AMD_COMGR_CONFIG_NAME}") +install(EXPORT amd_comgr_export + COMPONENT amd-comgr + DESTINATION "${CMAKE_INSTALL_LIBDIR}/${AMD_COMGR_PACKAGE_PREFIX}" + FILE "${AMD_COMGR_TARGETS_NAME}") +install(FILES + "${AMD_COMGR_VERSION_PATH}" + COMPONENT amd-comgr + DESTINATION "${CMAKE_INSTALL_LIBDIR}/${AMD_COMGR_PACKAGE_PREFIX}") + +if(TARGET clangFrontendTool) + set(CLANG_LIBS + clangBasic + clangDriver + clangSerialization + clangFrontend + clangFrontendTool) +else() + set(CLANG_LIBS + clang-cpp) +endif() + +set(LLD_LIBS + lldELF + lldCommon) + +if (${COMGR_DISABLE_SPIRV}) + set(SPIRV_DYNAMIC_LIB "") + set(SPIRV_STATIC_LIB "") +else() + set(SPIRV_DYNAMIC_LIB "LLVMSPIRVAMDLib") + set(SPIRV_STATIC_LIB "SPIRVAMDLib") +endif() + +if (LLVM_LINK_LLVM_DYLIB) + set(LLVM_LIBS LLVM ${SPIRV_DYNAMIC_LIB}) +else() + llvm_map_components_to_libnames(LLVM_LIBS + ${LLVM_TARGETS_TO_BUILD} + BinaryFormat + BitReader + BitWriter + CodeGen + Core + DebugInfoDWARF + Demangle + IRReader + Linker + MC + MCDisassembler + MCParser + Object + Option + Support + Symbolize + TargetParser + ${SPIRV_STATIC_LIB} + ) +endif() + +target_link_options(amd_comgr + PUBLIC + ${AMD_COMGR_PUBLIC_LINKER_OPTIONS} + PRIVATE + ${AMD_COMGR_PRIVATE_LINKER_OPTIONS}) + +target_link_libraries(amd_comgr + PRIVATE + ${LLD_LIBS} + ${LLVM_LIBS} + ${CLANG_LIBS}) + +if (NOT UNIX) + target_link_libraries(amd_comgr + PRIVATE version) +endif() + +find_package(Threads) +target_link_libraries(amd_comgr PRIVATE ${CMAKE_THREAD_LIBS_INIT}) + +find_library(LIBRT rt) +if(LIBRT) + target_link_libraries(amd_comgr PRIVATE ${LIBRT}) +endif() + + +if (NOT WIN32) + target_link_libraries(amd_comgr + PRIVATE + c + ${CMAKE_DL_LIBS}) +endif() + +include(CTest) +if(BUILD_TESTING) + add_custom_target(check-comgr COMMAND ${CMAKE_CTEST_COMMAND} DEPENDS amd_comgr) + if (NOT CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) + set_property(GLOBAL APPEND PROPERTY LLVM_ADDITIONAL_TEST_TARGETS check-comgr) + endif() + add_subdirectory(test) + add_subdirectory(test-lit) +endif() + +if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) + # Add packaging directives for amd_comgr + if(ENABLE_ASAN_PACKAGING) + # Only libraries required for ASAN Package + set(CPACK_COMPONENTS_ALL asan) + set(PKG_DESC_SUMMARY "AddressSanitizer Instrumented Libraries to provide support functions for ROCm code objects.") + elseif(NOT COMGR_BUILD_SHARED_LIBS) + set(CPACK_COMPONENTS_ALL amd-comgr) + set(PKG_DESC_SUMMARY "Static Library to provide support functions for ROCm code objects.") + else() + set(CPACK_COMPONENTS_ALL amd-comgr) + set(PKG_DESC_SUMMARY "Library to provide support functions for ROCm code objects.") + endif() + set(CPACK_PACKAGE_NAME comgr) + set(CPACK_PACKAGE_VENDOR "Advanced Micro Devices, Inc.") + set(CPACK_PACKAGE_DESCRIPTION_SUMMARY ${PKG_DESC_SUMMARY}) + set(CPACK_PACKAGE_DESCRIPTION "This package contains the AMD ${CPACK_PACKAGE_DESCRIPTION_SUMMARY}.") + set(CPACK_PACKAGE_VERSION_MAJOR "${amd_comgr_VERSION_MAJOR}") + set(CPACK_PACKAGE_VERSION_MINOR "${amd_comgr_VERSION_MINOR}") + set(CPACK_PACKAGE_VERSION_PATCH "${amd_comgr_VERSION_PATCH}") + set(CPACK_PACKAGE_CONTACT "ROCm Compiler Support ") + set(CPACK_RESOURCE_FILE_LICENSE "${CMAKE_CURRENT_SOURCE_DIR}/LICENSE.txt") + + # ASAN Specific variables + set(CPACK_DEBIAN_ASAN_PACKAGE_NAME comgr-asan) + set(CPACK_RPM_ASAN_PACKAGE_NAME comgr-asan) + + # Make proper version for appending + set(ROCM_VERSION_FOR_PACKAGE "") + if(DEFINED ENV{ROCM_LIBPATCH_VERSION}) + set(ROCM_VERSION_FOR_PACKAGE $ENV{ROCM_LIBPATCH_VERSION}) + elseif(DEFINED ENV{ROCM_VERSION}) + string(REGEX REPLACE "." "" ROCM_VERSION_FOR_PACKAGE $ENV{ROCM_VERSION}) + else() + # Default Case, set to 99999 + set(ROCM_VERSION_FOR_PACKAGE "99999") + endif() + + # Archive package specific variable + set(CPACK_ARCHIVE_COMPONENT_INSTALL ON) + + # Debian package specific variables + set(CPACK_DEB_COMPONENT_INSTALL ON) + if(COMGR_BUILD_SHARED_LIBS) + set(CPACK_DEBIAN_AMD-COMGR_PACKAGE_NAME comgr) + else() + set(CPACK_DEBIAN_AMD-COMGR_PACKAGE_NAME comgr-static-dev) + endif() + set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/ROCm/llvm-project/tree/amd-staging/amd/comgr") + set(DEBIAN_DEPENDENCIES "libzstd1, zlib1g, libc6, libstdc++6, libgcc-s1 | libgcc1") + if (LLVM_LINK_LLVM_DYLIB) + set(CPACK_DEBIAN_PACKAGE_DEPENDS "libtinfo-dev, rocm-core, rocm-llvm-core, ${DEBIAN_DEPENDENCIES}") + set(CPACK_DEBIAN_ASAN_PACKAGE_DEPENDS "libtinfo-dev, rocm-core-asan, rocm-llvm-core, ${DEBIAN_DEPENDENCIES}") + else() + set(CPACK_DEBIAN_PACKAGE_DEPENDS "libtinfo-dev, rocm-core, ${DEBIAN_DEPENDENCIES}") + set(CPACK_DEBIAN_ASAN_PACKAGE_DEPENDS "libtinfo-dev, rocm-core-asan, ${DEBIAN_DEPENDENCIES}") + endif() + if (DEFINED ENV{CPACK_DEBIAN_PACKAGE_RELEASE}) + set(CPACK_DEBIAN_PACKAGE_RELEASE $ENV{CPACK_DEBIAN_PACKAGE_RELEASE}) + else() + set(CPACK_DEBIAN_PACKAGE_RELEASE "local") + endif() + + # RPM package specific variables + set(CPACK_RPM_COMPONENT_INSTALL ON) + if(COMGR_BUILD_SHARED_LIBS) + set(CPACK_RPM_AMD-COMGR_PACKAGE_NAME comgr) + else() + set(CPACK_RPM_AMD-COMGR_PACKAGE_NAME comgr-static-devel) + endif() + + execute_process(COMMAND rpm --eval %{?dist} + RESULT_VARIABLE PROC_RESULT + OUTPUT_VARIABLE EVAL_RESULT + OUTPUT_STRIP_TRAILING_WHITESPACE) + + if(PROC_RESULT EQUAL "0" AND "${EVAL_RESULT}" STREQUAL ".el7") + # In Centos using parentheses is causing cpack errors. + # Set the dependencies specifically for centos + set(RPM_DEPENDENCIES "zlib, glibc, libstdc++, libgcc") + else() + set(RPM_DEPENDENCIES "(zlib or libz1), (libzstd or libzstd1), glibc, (libstdc++ or libstdc++6), (libgcc or libgcc_s1)") + endif() + + if (LLVM_LINK_LLVM_DYLIB) + set(CPACK_RPM_PACKAGE_REQUIRES "rocm-core, rocm-llvm-core, ${RPM_DEPENDENCIES}") + set(CPACK_RPM_ASAN_PACKAGE_REQUIRES "rocm-core-asan, rocm-llvm-core, ${RPM_DEPENDENCIES}") + else() + set(CPACK_RPM_PACKAGE_REQUIRES "rocm-core, ${RPM_DEPENDENCIES}") + set(CPACK_RPM_ASAN_PACKAGE_REQUIRES "rocm-core-asan, ${RPM_DEPENDENCIES}") + endif() + if(DEFINED ENV{CPACK_RPM_PACKAGE_RELEASE}) + set(CPACK_RPM_PACKAGE_RELEASE $ENV{CPACK_RPM_PACKAGE_RELEASE}) + else() + set(CPACK_RPM_PACKAGE_RELEASE "local") + endif() + set(CPACK_RPM_PACKAGE_LICENSE "NCSA") + + # Get rpm distro + if(CPACK_RPM_PACKAGE_RELEASE) + set(CPACK_RPM_PACKAGE_RELEASE_DIST ON) + endif() + + # Prepare final version for the CPACK use + set(CPACK_PACKAGE_VERSION "${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}.${ROCM_VERSION_FOR_PACKAGE}") + + # Set the names now using CPACK utility + set(CPACK_DEBIAN_FILE_NAME "DEB-DEFAULT") + set(CPACK_RPM_FILE_NAME "RPM-DEFAULT") + # Remove dependency on rocm-core if -DROCM_DEP_ROCMCORE=ON not given to cmake + if(NOT ROCM_DEP_ROCMCORE) + string(REGEX REPLACE ",? ?rocm-core" "" CPACK_RPM_PACKAGE_REQUIRES ${CPACK_RPM_PACKAGE_REQUIRES}) + string(REGEX REPLACE ",? ?rocm-core-asan" "" CPACK_RPM_ASAN_PACKAGE_REQUIRES ${CPACK_RPM_ASAN_PACKAGE_REQUIRES}) + string(REGEX REPLACE ",? ?rocm-core" "" CPACK_DEBIAN_PACKAGE_DEPENDS ${CPACK_DEBIAN_PACKAGE_DEPENDS}) + string(REGEX REPLACE ",? ?rocm-core-asan" "" CPACK_DEBIAN_ASAN_PACKAGE_DEPENDS ${CPACK_DEBIAN_ASAN_PACKAGE_DEPENDS}) + endif() + + include(CPack) +endif() diff --git a/amd/comgr/LICENSE.txt b/amd/comgr/LICENSE.txt new file mode 100644 index 0000000000000..c207e70a8d7cf --- /dev/null +++ b/amd/comgr/LICENSE.txt @@ -0,0 +1,275 @@ +============================================================================== +The Comgr Project is under the Apache License v2.0 with LLVM Exceptions: +============================================================================== + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + +---- LLVM Exceptions to the Apache 2.0 License ---- + +As an exception, if, as a result of your compiling your source code, portions +of this Software are embedded into an Object form of such source code, you +may redistribute such embedded portions in such Object form without complying +with the conditions of Sections 4(a), 4(b) and 4(d) of the License. + +In addition, if you combine or link compiled forms of this Software with +software that is licensed under the GPLv2 ("Combined Software") and if a +court of competent jurisdiction determines that the patent provision (Section +3), the indemnity provision (Section 9) or other Section of the License +conflicts with the conditions of the GPLv2, you may retroactively and +prospectively choose to deem waived or otherwise exclude such Section(s) of +the License, but only in their entirety and only with respect to the Combined +Software. + +============================================================================== +Software from third parties included in the Comgr Project: +============================================================================== +The Comgr Project contains third party software which is under different license +terms. All such code will be identified clearly using at least one of two +mechanisms: +1) It will be in a separate directory tree with its own `LICENSE.txt` or + `LICENSE` file at the top containing the specific license and restrictions + which apply to that software, or +2) It will contain specific license and restriction terms at the top of every + file. + +============================================================================== +Legacy Comgr License +============================================================================== +University of Illinois/NCSA +Open Source License + +Copyright (c) 2018-2025 Advanced Micro Devices, Inc. All Rights Reserved. + +Developed by: + + Advanced Micro Device, Inc. + + https://www.amd.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal with +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +of the Software, and to permit persons to whom the Software is furnished to do +so, subject to the following conditions: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimers. + + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimers in the + documentation and/or other materials provided with the distribution. + + * Neither the names of Advanced Micro Device, Inc. nor the names of its + contributors may be used to endorse or promote products derived from + this Software without specific prior written permission. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE +SOFTWARE. + diff --git a/amd/comgr/README.md b/amd/comgr/README.md new file mode 100644 index 0000000000000..16d962e487552 --- /dev/null +++ b/amd/comgr/README.md @@ -0,0 +1,281 @@ +Code Object Manager (Comgr) +=========================== + +The Comgr library provides APIs for compiling and inspecting AMDGPU code +objects. The API is documented in the [header file](include/amd_comgr.h.in). +The Comgr API is compatible with C99 and C++. + +Building the Code Object Manager +-------------------------------- + +Comgr depends on [LLVM](https://github.com/ROCm/llvm-project) and +[AMDDeviceLibs](https://github.com/ROCm/llvm-project/tree/amd-staging/amd/device-libs). +One way to make these visible to the Comgr build process is by setting the +`CMAKE_PREFIX_PATH` to include either the build directory or install prefix of +each of these components, separated by a semicolon. Both should be built using +either sources with the same ROCm release tag, or from the `amd-staging` +branch. LLVM should be built with at least +`LLVM_ENABLE_PROJECTS='llvm;clang;lld'` and +`LLVM_TARGETS_TO_BUILD='AMDGPU;X86'`. + +An example `bash` session to build Comgr on Linux using GNUMakefiles is: + + $ LLVM_PROJECT=~/llvm-project/build + $ DEVICE_LIBS=~/llvm-project/amd/device-libs/build + $ mkdir -p "$LLVM_PROJECT" + $ cd "$LLVM_PROJECT" + $ cmake \ + -DCMAKE_BUILD_TYPE=Release \ + -DLLVM_ENABLE_PROJECTS="llvm;clang;lld" \ + -DLLVM_TARGETS_TO_BUILD="AMDGPU;X86" \ + ../llvm + $ make + $ mkdir -p "$DEVICE_LIBS" + $ cd "$DEVICE_LIBS" + $ cmake \ + -DCMAKE_BUILD_TYPE=Release \ + -DCMAKE_PREFIX_PATH="$LLVM_PROJECT" \ + .. + $ make + $ cd ~/llvm-project/amd/comgr + $ mkdir -p build; cd build; + $ cmake \ + -DCMAKE_BUILD_TYPE=Release \ + -DCMAKE_PREFIX_PATH="$LLVM_PROJECT;$DEVICE_LIBS" \ + .. + $ make + $ make test + +The equivalent on Windows in `cmd.exe` using Visual Studio project files is: + + > set LLVM_PROJECT="%HOMEPATH%\llvm-project\build" + > set DEVICE_LIBS="%HOMEPATH%\llvm-project\amd\device-libs\build" + > mkdir "%LLVM_PROJECT%" + > cd "%LLVM_PROJECT%" + > cmake ^ + -DLLVM_ENABLE_PROJECTS="llvm;clang;lld" ^ + -DLLVM_TARGETS_TO_BUILD="AMDGPU;X86" ^ + ..\llvm + > msbuild /p:Configuration=Release ALL_BUILD.vcxproj + > mkdir "%DEVICE_LIBS%" + > cd "%DEVICE_LIBS%" + > cmake ^ + -DCMAKE_PREFIX_PATH="%LLVM_PROJECT%" ^ + .. + > msbuild /p:Configuration=Release ALL_BUILD.vcxproj + > cd "%HOMEPATH%\llvm-project\amd\comgr" + > mkdir build + > cd build + > cmake ^ + -DCMAKE_PREFIX_PATH="%LLVM_PROJECT%;%DEVICE_LIBS%" ^ + .. + > msbuild /p:Configuration=Release ALL_BUILD.vcxproj + > msbuild /p:Configuration=Release RUN_TESTS.vcxproj + +**ASAN support:** Optionally, +[AddressSanitizer](https://github.com/google/sanitizers/wiki/AddressSanitizer) +may be enabled during development via `-DADDRESS_SANITIZER=On` during the Comgr +`cmake` step. + +**Static Comgr:** Comgr can be built as a static library by passing +`-DCOMGR_BUILD_SHARED_LIBS=OFF` during the Comgr `cmake` step. + +**SPIRV Support:** To enable SPIRV support, checkout +[SPIRV-LLVM-Translator](https://github.com/ROCm/SPIRV-LLVM-Translator) in +`llvm/projects` or `llvm/tools` and build using the above instructions, with the +exception that the `-DCMAKE_PREFIX_PATH` for llvm-project must be an install +path (specified with `-DCMAKE_INSTALL_PREFIX=/path/to/install/dir` and populated +with `make install`) rather than the build path. + +Comgr SPIRV-related APIs can be disabled by passing +`-DCOMGR_DISABLE_SPIRV=1` during the Comgr `cmake` step. This removes any +dependency on LLVM SPIRV libraries or the llvm-spirv tool. + +**Code Coverage Instrumentation:** Comgr supports source-based [code coverage +via clang](https://clang.llvm.org/docs/SourceBasedCodeCoverage.html), and +leverages the same CMake variables as +[LLVM](https://www.llvm.org/docs/CMake.html#llvm-related-variables) +(LLVM_BUILD_INSTRUMENTED_COVERAGE, etc.). + +Example of insturmenting with covereage, generating profiles, and creating an +HTML for investigation: + + $ cmake -DCMAKE_STRIP="" -DLLVM_PROFILE_DATA_DIR=`pwd`/profiles \ + -DLLVM_BUILD_INSTRUMENTED_COVERAGE=On \ + -DCMAKE_CXX_COMPILER="$LLVM_PROJECT/bin/clang++" \ + -DCMAKE_C_COMPILER="$LLVM_PROJECT/bin/clang" \ + -DCMAKE_BUILD_TYPE=Release \ + -DCMAKE_PREFIX_PATH="$LLVM_PROJECT;$DEVICE_LIBS" .. + $ make -j + $ make test test-lit + $ cd profiles + # Manually aggregate the data and create text report. + $ $LLVM_PROJECT/bin/llvm-profdata merge -sparse *.profraw -o \ + comgr_test.profdata # merge and index data + $ $LLVM_PROJECT/bin/llvm-cov report ../libamd_comgr.so \ + -instr-profile=comgr_test.profdata \ + -ignore-filename-regex="[cl].*/include/*" # show test report without \ + includes + # Or use python script to aggregate the data and create html report. + $ $LLVM_PROJECT/../llvm/utils/prepare-code-coverage-artifact.py \ + --preserve-profiles $LLVM_PROJECT/bin/llvm-profdata \ + $LLVM_PROJECT/bin/llvm-cov . html ../libamd_comgr.so \ + # create html report + +Depending on the Code Object Manager +------------------------------------ + +Comgr exports a CMake package named `amd_comgr` for both the build and install +trees. This package defines a library target named `amd_comgr`. To depend on +this in your CMake project, use `find_package`: + + find_package(amd_comgr REQUIRED CONFIG) + ... + target_link_libraries(your_target amd_comgr) + +If Comgr is not installed to a standard CMake search directory, the path to the +build or install tree can be supplied to CMake via `CMAKE_PREFIX_PATH`: + + cmake -DCMAKE_PREFIX_PATH=path/to/comgr/build/or/install + +Testing +-------------------------------- + +Comgr has both unit tests (older) and LLVM LIT tests (newer). They can be run +from the build directory via: + + make test # unit + make test-lit # lit + +Environment Variables +--------------------- + +Comgr lazily evaluates certain environment variables when their value is first +required. If the value is used, it is read once at the time it is needed, and +then cached. The exact behavior when changing these values during the execution +of a process after Comgr APIs have been invoked is undefined. + +Comgr supports an environment variable to help locate LLVM: + +* `LLVM_PATH`: If set, it is used as an absolute path to the root of the LLVM + installation, which is currently used to locate the clang resource directory + and clang binary path, allowing for additional optimizations. + +### Caching +Comgr utilizes a cache to preserve the results of compilations between executions. +The cache's status (enabled/disabled), storage location for its results, +and eviction policy can be manipulated through specific environment variables. +If an issue arises during cache initialization, the execution will proceed with +the cache turned off. + +By default, the cache is enabled. + +* `AMD_COMGR_CACHE`: When unset or set to a value different than "0", the cache is enabled. + Disabled when set to "0". +* `AMD_COMGR_CACHE_DIR`: If assigned a non-empty value, that value is used as + the path for cache storage. If the variable is unset or set to an empty string `""`, + it is directed to "$XDG_CACHE_HOME/comgr" (which defaults to + "$USER/.cache/comgr" on Linux, and "%LOCALAPPDATA%\cache\comgr" + on Microsoft Windows). +* `AMD_COMGR_CACHE_POLICY`: If assigned a value, the string is interpreted and + applied to the cache pruning policy. The cache is pruned only upon program + termination. The string format aligns with [Clang's ThinLTO cache pruning policy](https://clang.llvm.org/docs/ThinLTO.html#cache-pruning). + The default policy is set as: "prune_interval=1h:prune_expiration=0h:cache_size=75%:cache_size_bytes=30g:cache_size_files=0". + +### Debugging +Comgr supports some environment variables to aid in debugging. These +include: + +* `AMD_COMGR_SAVE_TEMPS`: If this is set, and is not "0", Comgr does not delete + temporary files generated during compilation. These files do not appear in + the current working directory, but are instead left in a platform-specific + temporary directory (typically `/tmp` on Linux and `C:\Temp` or the path + found in the `TEMP` environment variable on Windows). +* `AMD_COMGR_SAVE_LLVM_TEMPS`: If this is set, Comgr forwards `--save-temps=obj` + to Clang Driver invocations. +* `AMD_COMGR_REDIRECT_LOGS`: If this is not set, or is set to "0", logs are + returned to the caller as normal. If this is set to "stdout"/"-" or "stderr", + logs are instead redirected to the standard output or error stream, + respectively. If this is set to any other value, it is interpreted as a + filename which logs should be appended to. +* `AMD_COMGR_EMIT_VERBOSE_LOGS`: If this is set, and is not "0", logs will + include additional Comgr-specific informational messages. +* `AMD_COMGR_TIME_STATISTICS`: If this is set, and is not "0", logs will + include additional Comgr-specific timing information for compilation actions. + +### VFS +Comgr implements support for an in-memory, virtual filesystem (VFS) for storing +temporaries generated during intermediate compilation steps. This is aimed at +improving performance by reducing on-disk file I/O. Currently, VFS is only supported +for the device library link step, but we aim to progressively add support for +more actions. + +By default, VFS is turned on. + +* `AMD_COMGR_USE_VFS`: When set to "0", VFS support is turned off. +* Users may use the API `amd_comgr_action_info_set_vfs` to disable VFS for individual actions + without having to modify system-wide environment variables. +* If `AMD_COMGR_SAVE_TEMPS` is set and not "0", VFS support is turned off irrespective + of `AMD_COMGR_USE_VFS` or the use of `amd_comgr_action_info_set_vfs`. + +Versioning +---------- + +Comgr is versioned according to a `major.minor` number scheme. The version of +the library can be determined dynamically via the `amd_comgr_get_version` +function. The version is not changed due to bug-fixes. The minor version number +is incremented for each backwards-compatible change introduced. The major +version number is incremented, and the minor version is reset to zero, for each +backwards-incompatible change introduced. Information about Comgr changes +can be found in the [release notes](docs/ReleaseNotes.md). + +ISA Metadata and Versioning +--------------------------- + +Comgr supports multiple instruction set architectures (ISA) and APIs to query +metadata associated with an ISA. The queried metadata follows a semantic +versioning scheme e.g. major.minor.patch. The major version changes signifies +backward incompatible changes. + +* `1.0.0` : Support for new target feature syntax introduced at [AMDGPUUsage](https://llvm.org/docs/AMDGPUUsage.html). + Metadata query for a bare ISA string now returns the supported target + features along with other details. A new key for the version is introduced. +* `0.0.x` : Support for querying the metadata for an ISA. The metadata is + supplied in a map format with details of target triple, features and + resource limits associated with registers and memory addressing. The + version key is absent in the Metadata. + +Thread Saftey +------------- + +Comgr strives to be thread-safe when called from multiple threads in the same +process. Because of complications from a shared global state in LLVM, to +accomplish this Comgr internally implements locking mechanisms around LLVM-based +actions. + +Although the locks in Comgr can allow independent actions to be safely executed +in a multithreaded environment, the user-code must still guard against +concurrent method calls which may access any particular Comgr object's state. +A Comgr object shared between threads is only safe to use as long as each thread +carefully locks out access by any other thread while it uses the shared object. + +Coding Standards +---------------- + +Wherever possible, Comgr adheres to the same coding standards as +[LLVM](https://llvm.org/docs/CodingStandards.html). Comgr also includes +configuration files for +[clang-format](https://clang.llvm.org/docs/ClangFormat.html) and +[clang-tidy](https://clang.llvm.org/extra/clang-tidy/), which should be used to +ensure patches conform. + +A script at `utils/tidy-and-format.sh` can be run to help automate the task of +ensuring all sources conform to the coding standards. To support the use of +this script, any exceptions must be annotated in source comments, as described +in the clang-tidy manual. + +Aligning with the purpose of being a stable interface into LLVM functionality, +the core enum values (AMD\_COMGR\_LANGUAGE_\*, AMD\_COMGR\_DATA\_KIND\_\*, +AMD\_COMGR\_ACTION\_\*, etc.) should remain consistent between versions, even if +some enum values are deprecated and removed. This will avoid potential breakages +and binary incompatibilities. diff --git a/amd/comgr/VERSION.txt b/amd/comgr/VERSION.txt new file mode 100644 index 0000000000000..785420ec0eec3 --- /dev/null +++ b/amd/comgr/VERSION.txt @@ -0,0 +1,4 @@ +#COMGR_VERSION_MAJOR +3 +#COMGR_VERSION_MINOR +0 diff --git a/amd/comgr/cmake/DeviceLibs.cmake b/amd/comgr/cmake/DeviceLibs.cmake new file mode 100644 index 0000000000000..3c5654d93dae1 --- /dev/null +++ b/amd/comgr/cmake/DeviceLibs.cmake @@ -0,0 +1,125 @@ +set(INC_DIR ${CMAKE_CURRENT_BINARY_DIR}/include) + +set(GEN_LIBRARY_INC_FILE ${INC_DIR}/libraries.inc) +set(GEN_LIBRARY_DEFS_INC_FILE ${INC_DIR}/libraries_defs.inc) + +# cmake does not provide a way to query targets produced by a project, +# so we have to make one up. Ordinarily, individual library target +# names are usable. In this case, we don't want to have to maintain a +# list of bitcode libraries, since they change (e.g. when a new +# subtarget specific device library is added) +# +# If we found the device libraries through find_package, we were +# already provided a list of targets. If not, we tracked this in a +# global property. This is the same technique used for LLVM_LIBS in +# AddLLVM. + +if(NOT DEFINED AMD_DEVICE_LIBS_TARGETS) + get_property(AMD_DEVICE_LIBS_TARGETS GLOBAL PROPERTY AMD_DEVICE_LIBS) +endif() + +if(NOT AMD_DEVICE_LIBS_TARGETS) + message(FATAL_ERROR "Could not find list of device libraries") +endif() + +set(TARGETS_INCLUDES "") +foreach(AMDGCN_LIB_TARGET ${AMD_DEVICE_LIBS_TARGETS}) + set(header ${AMDGCN_LIB_TARGET}.inc) + + # FIXME: It's very awkward to deal with the device library + # build. Really, they are custom targets that do not nicely fit into + # any of cmake's library concepts. However, they are artificially + # exported as static libraries. The custom target has the + # OUTPUT_NAME property, but imported libraries have the LOCATION + # property. + get_target_property(bc_lib_path ${AMDGCN_LIB_TARGET} LOCATION) + if(NOT bc_lib_path) + get_target_property(bc_lib_path ${AMDGCN_LIB_TARGET} OUTPUT_NAME) + endif() + + if(NOT bc_lib_path) + message(FATAL_ERROR "Could not find path to bitcode library") + endif() + + # Generic targets contain - in the name, but that's not a valid C++ + # identifier so we need to replace - with _. + string(REPLACE "-" "_" AMDGCN_LIB_TARGET_ID ${AMDGCN_LIB_TARGET}) + + add_custom_command(OUTPUT ${INC_DIR}/${header} + COMMAND bc2h ${bc_lib_path} + ${INC_DIR}/${header} + "${AMDGCN_LIB_TARGET_ID}_lib" + DEPENDS bc2h ${AMDGCN_LIB_TARGET} ${bc_lib_path} + COMMENT "Generating ${AMDGCN_LIB_TARGET}.inc" + ) + set_property(DIRECTORY APPEND PROPERTY + ADDITIONAL_MAKE_CLEAN_FILES ${INC_DIR}/${header}) + + add_custom_target(${AMDGCN_LIB_TARGET}_header DEPENDS ${INC_DIR}/${header}) + add_dependencies(amd_comgr ${AMDGCN_LIB_TARGET}_header) + + list(APPEND TARGETS_INCLUDES "#include \"${header}\"") + list(APPEND TARGETS_HEADERS_FILENAME "${header}") + list(APPEND TARGETS_HEADERS_REALPATH "${INC_DIR}/${header}") +endforeach() + +list(JOIN TARGETS_INCLUDES "\n" TARGETS_INCLUDES) +file(GENERATE OUTPUT ${GEN_LIBRARY_INC_FILE} CONTENT "${TARGETS_INCLUDES}") + +add_custom_command(OUTPUT ${INC_DIR}/opencl-c-base.inc + COMMAND bc2h ${OPENCL_C_H} + ${INC_DIR}/opencl-c-base.inc + opencl_c_base + DEPENDS bc2h clang ${OPENCL_C_H} + COMMENT "Generating opencl-c-base.inc" +) +set_property(DIRECTORY APPEND PROPERTY + ADDITIONAL_MAKE_CLEAN_FILES ${INC_DIR}/opencl-c-base.inc) +add_custom_target(opencl-c-base.inc_target DEPENDS ${INC_DIR}/opencl-c-base.inc) +add_dependencies(amd_comgr opencl-c-base.inc_target) + +set(TARGETS_DEFS "") +list(APPEND TARGETS_DEFS "#ifndef AMD_DEVICE_LIBS_TARGET\n#define AMD_DEVICE_LIBS_TARGET(t)\n#endif") +list(APPEND TARGETS_DEFS "#ifndef AMD_DEVICE_LIBS_GFXIP\n#define AMD_DEVICE_LIBS_GFXIP(t, g)\n#endif") +list(APPEND TARGETS_DEFS "#ifndef AMD_DEVICE_LIBS_FUNCTION\n#define AMD_DEVICE_LIBS_FUNCTION(t, f)\n#endif") +list(APPEND TARGETS_DEFS "") +foreach(AMDGCN_LIB_TARGET ${AMD_DEVICE_LIBS_TARGETS}) + # Generic targets contain - in the name, but that's not a valid C++ + # identifier so we need to replace - with _. + string(REPLACE "-" "_" AMDGCN_LIB_TARGET_ID ${AMDGCN_LIB_TARGET}) + + list(APPEND TARGETS_DEFS "AMD_DEVICE_LIBS_TARGET(${AMDGCN_LIB_TARGET_ID})") + # Generate function to select libraries for a given GFXIP number. + if (${AMDGCN_LIB_TARGET} MATCHES "^oclc_isa_version_.+$") + string(REGEX REPLACE "^oclc_isa_version_(.+)$" "\\1" gfxip ${AMDGCN_LIB_TARGET}) + list(APPEND TARGETS_DEFS "AMD_DEVICE_LIBS_GFXIP(${AMDGCN_LIB_TARGET_ID}, \"${gfxip}\")") + endif() + # Generate function to select libraries for given feature. + if (${AMDGCN_LIB_TARGET} MATCHES "^oclc_.*_on$") + string(REGEX REPLACE "^oclc_(.*)_on" "\\1" function ${AMDGCN_LIB_TARGET}) + list(APPEND TARGETS_DEFS "AMD_DEVICE_LIBS_FUNCTION(${AMDGCN_LIB_TARGET}, ${function})") + endif() +endforeach() + +list(APPEND TARGETS_DEFS "") +list(APPEND TARGETS_DEFS "#undef AMD_DEVICE_LIBS_TARGET") +list(APPEND TARGETS_DEFS "#undef AMD_DEVICE_LIBS_GFXIP") +list(APPEND TARGETS_DEFS "#undef AMD_DEVICE_LIBS_FUNCTION") + +list(JOIN TARGETS_DEFS "\n" TARGETS_DEFS) +file(GENERATE OUTPUT ${GEN_LIBRARY_DEFS_INC_FILE} CONTENT "${TARGETS_DEFS}") + +# compute the sha256 of the device libraries to detect changes and pass them to comgr (used by the cache) +find_package(Python3 REQUIRED Interpreter) +set(DEVICE_LIBS_ID_SCRIPT "${CMAKE_CURRENT_SOURCE_DIR}/cmake/device-libs-id.py") +set(DEVICE_LIBS_ID_HEADER ${INC_DIR}/libraries_sha.inc) +add_custom_command(OUTPUT ${DEVICE_LIBS_ID_HEADER} + COMMAND ${Python3_EXECUTABLE} ${DEVICE_LIBS_ID_SCRIPT} --varname DEVICE_LIBS_ID --output ${DEVICE_LIBS_ID_HEADER} --parent-directory ${INC_DIR} ${TARGETS_HEADERS_FILENAME} + DEPENDS ${DEVICE_LIBS_ID_SCRIPT} ${TARGETS_HEADERS_REALPATH} + COMMENT "Generating ${INC_DIR}/libraries_sha.inc" +) +set_property(DIRECTORY APPEND PROPERTY ADDITIONAL_MAKE_CLEAN_FILES ${INC_DIR}/libraries_sha.inc) +add_custom_target(libraries_sha_header DEPENDS ${INC_DIR}/libraries_sha.inc) +add_dependencies(amd_comgr libraries_sha_header) + +include_directories(${INC_DIR}) diff --git a/amd/comgr/cmake/amd_comgr-config.cmake.in b/amd/comgr/cmake/amd_comgr-config.cmake.in new file mode 100644 index 0000000000000..abff41d8f5eb6 --- /dev/null +++ b/amd/comgr/cmake/amd_comgr-config.cmake.in @@ -0,0 +1,3 @@ +@AMD_COMGR_PREFIX_CODE@ + +include("@AMD_COMGR_TARGETS_PATH@") diff --git a/amd/comgr/cmake/bc2h.cmake b/amd/comgr/cmake/bc2h.cmake new file mode 100644 index 0000000000000..9134985e1914f --- /dev/null +++ b/amd/comgr/cmake/bc2h.cmake @@ -0,0 +1,43 @@ +file(GENERATE OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/bc2h.c + CONTENT +"#include +int main(int argc, char **argv){ + FILE *ifp, *ofp; + int c, i, l; + if (argc != 4) return 1; + ifp = fopen(argv[1], \"rb\"); + if (!ifp) return 1; + i = fseek(ifp, 0, SEEK_END); + if (i < 0) return 1; + l = ftell(ifp); + if (l < 0) return 1; + i = fseek(ifp, 0, SEEK_SET); + if (i < 0) return 1; + ofp = fopen(argv[2], \"wb+\"); + if (!ofp) return 1; + fprintf(ofp, \"#define %s_size %d\\n\\n\" + \"#if defined __GNUC__\\n\" + \"__attribute__((aligned (4096)))\\n\" + \"#elif defined _MSC_VER\\n\" + \"__declspec(align(4096))\\n\" + \"#endif\\n\" + \"static const unsigned char %s[%s_size+1] = {\", + argv[3], l, + argv[3], argv[3]); + i = 0; + while ((c = getc(ifp)) != EOF) { + if (0 == (i&7)) fprintf(ofp, \"\\n \"); + fprintf(ofp, \" 0x%02x,\", c); + ++i; + } + fprintf(ofp, \" 0x00\\n};\\n\\n\"); + fclose(ifp); + fclose(ofp); + return 0; +} +") + +add_executable(bc2h ${CMAKE_CURRENT_BINARY_DIR}/bc2h.c) +if (CMAKE_CXX_COMPILER_ID STREQUAL "MSVC") + target_compile_definitions(bc2h PRIVATE -D_CRT_SECURE_NO_WARNINGS) +endif() diff --git a/amd/comgr/cmake/device-libs-id.py b/amd/comgr/cmake/device-libs-id.py new file mode 100644 index 0000000000000..09362fb207ca6 --- /dev/null +++ b/amd/comgr/cmake/device-libs-id.py @@ -0,0 +1,26 @@ +# Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +# amd/comgr/LICENSE.TXT in this repository for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +from argparse import ArgumentParser +from hashlib import sha256 +from os.path import join as join_path + +if __name__ == "__main__": + parser = ArgumentParser(description='Generate id by computing a hash of the generated headers') + parser.add_argument("headers", nargs='+', help='List of headers to generate id from') + # On Windows, we cannot list the realpath for every individual header since we hit cmd.exe's + # maximum command line lenght. As a workaround, we pass the pwd and the headers separately. + parser.add_argument("--parent-directory", help='Parent directory for the headers', required=True) + parser.add_argument("--varname", help='Name of the variable to generate', required=True) + parser.add_argument("--output", help='Name of the header to generate', required=True) + + args = parser.parse_args() + args.headers.sort() + + hash = sha256() + for header in args.headers: + hash.update(open(join_path(args.parent_directory, header), 'rb').read()) + digest_uchar = hash.digest() + digest_elts = ", ".join(map(str, digest_uchar)) + print(f"static const unsigned char {args.varname}[] = {{{digest_elts}, 0}};", file=open(args.output, 'w')) diff --git a/amd/comgr/cmake/opencl_header.cmake b/amd/comgr/cmake/opencl_header.cmake new file mode 100644 index 0000000000000..c64735c56b091 --- /dev/null +++ b/amd/comgr/cmake/opencl_header.cmake @@ -0,0 +1,24 @@ +if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) + find_package(Clang REQUIRED CONFIG) + + # FIXME: CLANG_CMAKE_DIR seems like the most stable way to find this, but + # really there is no way to reliably discover this header. + # + # We effectively back up to the Clang output directory (for the case of a build + # tree) or install prefix (for the case of an installed copy), and then search + # for a file named opencl-c-base.h anywhere below that. We take the first result in + # the case where there are multiple (e.g. if there is an installed copy nested + # in a build directory). This is a bit imprecise, but it covers cases like MSVC + # adding some additional configuration-specific subdirectories to the build + # tree but not to an installed copy. + file(GLOB_RECURSE OPENCL_C_H_LIST "${CLANG_CMAKE_DIR}/../../../*/opencl-c-base.h") + + list(GET OPENCL_C_H_LIST 0 OPENCL_C_H) + + if (NOT EXISTS "${OPENCL_C_H}" OR IS_DIRECTORY "${OPENCL_C_H}") + message(FATAL_ERROR "Unable to locate opencl-c-base.h from the supplied Clang. The path '${CLANG_CMAKE_DIR}/../../../*' was searched.") + endif() +else() + get_target_property(clang_build_header_dir clang-resource-headers RUNTIME_OUTPUT_DIRECTORY) + set(OPENCL_C_H "${clang_build_header_dir}/opencl-c-base.h") +endif() diff --git a/amd/comgr/cpack_project_config.cmake b/amd/comgr/cpack_project_config.cmake new file mode 100644 index 0000000000000..2922e98e9efab --- /dev/null +++ b/amd/comgr/cpack_project_config.cmake @@ -0,0 +1,5 @@ +if (CPACK_GENERATOR MATCHES "DEB") + set(CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}_${CPACK_PACKAGE_VERSION}_amd64") +elseif (CPACK_GENERATOR MATCHES "RPM") + set(CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${CPACK_PACKAGE_VERSION}.x86_64") +endif() diff --git a/amd/comgr/docs/ReleaseNotes.md b/amd/comgr/docs/ReleaseNotes.md new file mode 100644 index 0000000000000..0fbd1edd882aa --- /dev/null +++ b/amd/comgr/docs/ReleaseNotes.md @@ -0,0 +1,88 @@ +Comgr v4.0 (In Progress) Release Notes +======================== + +This document contains the release notes for the Code Object Manager (Comgr), +part of the ROCm Software Stack, release v4.0. Here we describe the status of +Comgr, including major improvements from the previous release and new feature + +These are in-progress notes for the upcoming Comgr v4.0 release. +Release notes for previous releases can be found in +[docs/historical](docs/historical). + +Potentially Breaking Changes +---------------------------- +These changes are ones which we think may surprise users when upgrading to +Comgr v4.0 because of the opportunity they pose for disruption to existing +code bases. + + +New Features +------------ +- Added a Comgr Caching infrastructure, currently covering the following +behaviors: + - caching unbundling of compressed clang offload bundles + - caching SPIR-V to LLVM IR translations + - caching clang driver invocations + More information about the Comgr Caching infrastructure and how to use it can + be found in amd/comgr/README.md. +- Updated the license used for Comgr from Illinois to Apache 2.0 with LLVM +Extensions (the same license used by LLVM). +- Added Image Support to Comgr's handling of ISA metadata. Support for images +can now be queried with Comgr's metadata APIs. +- Added support for linking device library files through the use of a Virtual +File System (VFS). + +Bug Fixes +--------- + +New APIs +-------- +- amd\_comgr\_info\_set\_vfs\_() (v3.1) + - By setting this ActionInfo property, users can explicitly dictate if + device libraries should be linked using the real file system or a + Virtual File System (VFS). + +Deprecated APIs +--------------- + +Removed APIs +------------ +- The following Comgr metadata API has removed support for V2/V3 Code Objects: + - amd\_comgr\_lookup\_code\_object() + This API still supports Code Objects V4 and later. + +New Comgr Actions and Data Types +-------------------------------- + +Deprecated Comgr Actions and Data Types +--------------------------------------- + +Removed Comgr Actions and Data Types +------------------------------------ +- AMD\_COMGR\_ACTION\_DISASSEMBLE\_RELOCATABLE\_TO\_SOURCE +- AMD\_COMGR\_ACTION\_DISASSEMBLE\_EXECUTABLE\_TO\_SOURCE +- AMD\_COMGR\_ACTION\_DISASSEMBLE\_BYTES\_TO\_SOURCE + +Comgr Testing, Debugging, and Logging Updates +--------------------------------------------- +- Removed HIP\_PATH and ROCM\_PATH environment variables. These were used for +now-removed Comgr actions, such as \*COMPILE\_SOURCE\_TO\_FATBIN. +- Added a new Comgr LIT testing infrastructure, which can be found in +amd/comgr/test-lit. This will allow us to write more in-depth and targeted +tests. +- Added support for source-based code coverage. See README.md for more details. + +New Targets +----------- + +Removed Targets +--------------- + +Significant Known Problems +-------------------------- +- Several Comgr actions currently write and read files from the filesystem, +which is a known performance issue. We aim to address this by improving +clang's virtual file system support +- Several Comgr actions currently fork new processes for compilation actions. We +aim to address this by librayizing llvm tools that are currently only useable as +a separate process. diff --git a/amd/comgr/docs/historical/ReleaseNotes-ComgrV3.md b/amd/comgr/docs/historical/ReleaseNotes-ComgrV3.md new file mode 100644 index 0000000000000..d089cd2699f2a --- /dev/null +++ b/amd/comgr/docs/historical/ReleaseNotes-ComgrV3.md @@ -0,0 +1,243 @@ +Comgr v3.0 Release Notes +======================== + +This document contains the release notes for the Code Object Manager (Comgr), +part of the ROCm Software Stack, release v3.0. Here we describe the status of +Comgr, including major improvements from the previous release and new feature + +These are in-progress notes for the upcoming Comgr v3.0 release. +Release notes for previous releases can be found in +[docs/historical](docs/historical). + +Potentially Breaking Changes +---------------------------- +These changes are ones which we think may surprise users when upgrading to +Comgr v3.0 because of the opportunity they pose for disruption to existing +code bases. + +- Removed -h option from comgr-objdump: The -h option (short for -headers) is a +legal comgr-objdump option. However registering this as an LLVM option by Comgr +prevents other LLVM tools or instances from registering a -h option in the same +process, which is an issue because -h is a common short form for -help. +- Updated default code object version used when linking code object specific +device library from v4 to v5 +- Updated shared library name on Windows 64-bit to include Comgr major version +(libamd\_comgr.dll -> libamd\_comgr\_X.dll, where X is the major version) +- oclc\_daz\_opt\_on.bc and oclc\_daz\_opt\_off.bc, and the corresponding + variable \_\_oclc\_daz\_opt are no longer necessary. +- Updated default device library linking behavior for several actions. + Previously, linking was done for some actions and not others, and not + controllable by the user. Now, linking is not done by default, but can + optionally be enabled via the + amd\_comgr\_action\_info\_set\_device\_lib\_linking() API. Users relying + on enabled-by-default behavior should update to use the new API to avoid + changes in behavior. + + Note: This does not apply to the \*COMPILE\_SOURCE\_WITH\_DEVICE\_LIBS\_TO\_BC + action. This action is not affected by the + amd\_comgr\_action\_info\_set\_device\_lib\_linking() API. The new API will + allow us to deprecate and remove this action in favor of the + \*COMPILE\_SOURCE\_TO\_BC action. + +New Features +------------ +- Added support for linking code\_object\_v4/5 device library files. +- Enabled llvm dylib builds. When llvm dylibs are enabled, a new package +rocm-llvm-core will contain the required dylibs for Comgr. +- Moved build to C++17, allowing us to use more modern features in the +implementation and tests. +- Enabled thread-safe execution of Comgr by enclosing primary Comgr actions in +an std::scoped\_lock() +- Added support for bitcode and archive unbundling during linking via the new +llvm OffloadBundler API. +- Added support for code object v6 and generic targets. +- Added mechanism to bypass device library file system writes if Comgr is able +to locate a local device library directory via the clang-resource-dir + +Bug Fixes +--------- +- Fixed symbolizer assertion for non-null terminated file-slice content, +by bypassing null-termination check in llvm::MemoryBuffer +- Fixed bug and add error checking for internal unbundling. Previously internal +unbundler would fail if files weren't already present in filesystem. +- Fixed issue where lookUpCodeObject() would fail if code object ISA strings +weren't listed in order. +- Added support for subdirectories in amd\_comgr\_set\_data\_name(). Previously +names with a "/" would generate a file-not-found error. +- Added amdgpu-internalize-symbols option to bitcode codegen action, which has +significant performance implications +- Fixed an issue where -nogpulib was always included in HIP compilations, which +prevented correct execution of +COMPILE\_SOURCE\_WITH\_DEVICE\_LIBS\_TO\_BC action. +- Fixed a multi-threading bug where programs would hang when calling Comgr APIs +like amd\_comgr\_iterate\_symbols() from multiple threads +- Fixed an issue where providing DataObjects with an empty name to the bitcode +linking action caused errors when AMD\_COMGR\_SAVE\_TEMPS was enabled, or when +linking bitcode bundles. +- Updated to use lld::lldMain() introduced in D110949 instead of the older +lld::elf::link in Comgr's linkWithLLD() +- Added -x assembler option to assembly compilation. Before, if an assembly file +did not end with a .s file extension, it was not handled properly by the Comgr +ASSEMBLE\_SOURCE\_TO\_RELOCATABLE action. +- Switched getline() from C++ to C-style to avoid issues with stdlibc++ and +pytorch +- Added new -relink-builtin-bitcode-postop LLVM option to device library. This +fixes an issue with the \*COMPILE\_SOURCE\_WITH\_DEVICE\_LIBRARIES\_TO\_BC where +OpenCL applications that leveraged AMDGPUSimplifyLibCalls optimizations would +need to re-link bitcodes separately to avoid errors at runtime. +- Correctly set directory to object file path when forwarding -save-temps for +HIP compilations with AMD\_COMGR\_SAVE\_TEMPS set +- Added new ['--skip-line-zero'](https://github.com/llvm/llvm-project/pull/82240) +LLVM option by default in comgr-symbolizer to support symbolization of instructions +having no source correspondence in the debug information. + +New APIs +-------- +- amd\_comgr\_populate\_mangled\_names() (v2.5) +- amd\_comgr\_get\_mangled\_name() (v2.5) + - Support bitcode and executable name lowering. The first call populates a + list of mangled names for a given data object, while the second fetches a + name from a given object and index. +- amd\_comgr\_populate\_name\_expression\_map() (v2.6) +- amd\_comgr\_map\_name\_expression\_to\_symbol\_name() (v2.6) + - Support bitcode and code object name expression mapping. The first call + populates a map of name expressions for a given comgr data object, using + LLVM APIs to traverse the bitcode or code object. The second call returns + a value (mangled symbol name) from the map for a given key (unmangled + name expression). These calls assume that names of interest have been + enclosed the HIP runtime using a stub attribute containg the following + string in the name: "__amdgcn_name_expr". +- amd\_comgr\_map\_elf\_virtual\_address\_to\_code\_object\_offset() (v2.7) + - For a given executable and ELF virtual address, return a code object + offset. This API will benifet the ROCm debugger and profilier +- amd\_comgr\_action\_info\_set\_bundle\_entry\_ids() (v2.8) +- amd\_comgr\_action\_info\_get\_bundle\_entry\_id\_count() (v2.8) +- amd\_comgr\_action\_info\_get\_bundle\_entry\_id() (v2.8) + - A user can provide a set of bundle entry IDs, which are processed when + calling the AMD\_COMGR\_UNBUNDLE action +- amd\_comgr\_action\_info\_set\_device\_lib\_linking() (v2.9) + - By setting this ActionInfo property, a user can explicitly dictate if + device libraries should be linked for a given action. (Previouly, the + action type implicitly determined device library linking). + + +Deprecated APIs +--------------- + +Removed APIs +------------ +- amd\_comgr\_action\_info\_set\_options() (v3.0) +- amd\_comgr\_action\_info\_get\_options() (v3.0) + - Use amd\_comgr\_action\_info\_set\_option\_list(), + amd\_comgr\_action\_info\_get\_option\_list\_count(), and + amd\_comgr\_action\_info\_get\_option\_list\_item() instead + +New Comgr Actions and Data Types +-------------------------------- +- (Action) AMD\_COMGR\_ACTION\_COMPILE\_SOURCE\_TO\_RELOCATABLE + - This action performs compile-to-bitcode, linking device libraries, and +codegen-to-relocatable in a single step. By doing so, clients are able to defer more +of the flag handling to toolchain. Currently only supports HIP. +- (Data Type) AMD\_COMGR\_DATA\_KIND\_BC\_BUNDLE +- (Data Type) AMD\_COMGR\_DATA\_KIND\_AR\_BUNDLE + - These data kinds can now be passed to an AMD\_COMGR\_ACTION\_LINK\_BC\_TO\_BC +action, and Comgr will internally unbundle and link via the OffloadBundler and linkInModule APIs. +- (Language Type) AMD\_COMGR\_LANGUAGE\_LLVM\_IR + - This language can now be passed to AMD\_COMGR\_ACTION\_COMPILE\_\* actions + to enable compilation of LLVM IR (.ll or .bc) files. This is useful for MLIR + contexts. +- (Action) AMD\_COMGR\_ACTION\_COMPILE\_SOURCE\_TO\_EXECUTABLE + - This action allows compilation from source directly to executable, including + linking device libraries. +- (Action) AMD\_COMGR\_ACTION\_UNBUNDLE + - This accepts a set of bitcode bundles, object file bundles, and archive + bundles,and returns set of unbundled bitcode, object files, and archives, + selecting bundles based on the bundle entry IDs provided. +- (Data Type) AMD\_COMGR\_DATA\_KIND\_OBJ\_BUNDLE + - This data kind represents a clang-offload-bundle of object files, and can be + passed when calling the AMD\_COMGR\_ACTION\_UNBUNDLE action +- (Data Type) AMD\_COMGR\_DATA\_KIND\_SPIRV + - This data kind represents a SPIR-V binary file (.spv) +- (Action) AMD\_COMGR\_ACTION\_TRANSLATE\_SPIRV\_TO\_BC + - This accepts a set of SPIR-V (.spv) inputs, and returns a set of translated + bitcode (.bc) outputs + +Deprecated Comgr Actions and Data Types +--------------------------------------- + +Removed Comgr Actions and Data Types +------------------------------------ +- (Action) AMD\_COMGR\_ACTION\_COMPILE\_SOURCE\_TO\_FATBIN + - This workaround has been removed in favor of + \*\_COMPILE\_SOURCE\_(WITH\_DEVICE\_LIBS\_)TO\_BC +- (Action) AMD\_COMGR\_ACTION\_OPTIMIZE\_BC\_TO\_BC + - This is a legacy action that was never implemented +- (Language) AMD\_COMGR\_LANGUAGE\_HC + - This is a legacy language that was never used +- (Action) AMD\_COMGR\_ACTION\_ADD\_DEVICE\_LIBRARIES + - This has been replaced with + AMD\_COMGR\_ACTION\_COMPILE\_SOURCE\_WITH\_DEVICE\_LIBS\_TO\_BC + +Comgr Testing, Debugging, and Logging Updates +--------------------------------------------- +- Added support for C++ tests. Although Comgr APIs are C-compatible, we can now +use C++ features in testing (C++ threading APIs, etc.) +- Clean up test directory by moving sources to subdirectory +- Several tests updated to pass while verbose logs are redirected to stdout +- Log information reported when AMD\_COMGR\_EMIT\_VERBOSE\_LOGS updated to: + - Show both user-facing clang options used (Compilation Args) and internal + driver options (Driver Job Args) + - Show files linked by linkBitcodeToBitcode() +- Remove support for code object v2 compilation in tests and test CMAKE due to +deprecation of code object v2 in LLVM. However, we still test loading and +metadata querys for code object v2 objects. +- Remove support for code object v3 compilation in tests and test CMAKE due to +deprecation of code object v3 in LLVM. However, we still test loading and +metadata querys for code object v3 objects. +- Revamp symbolizer test to fail on errors, among other improvments +- Improve linking and unbundling log to correctly store temporary files in /tmp, +and to output clang-offload-bundler command to allow users to re-create Comgr +unbundling. +- Add git branch and commit hash for Comgr, and commit hash for LLVM to log +output for Comgr actions. This can help us debug issues more quickly in cases +where reporters provide Comgr logs. +- Fix multiple bugs with mangled names test +- Update default arch for test binaries from gfx830 to gfx900 +- Refactor nested kernel behavior into new test, as this behavior is less common +and shouldn't be featured in the baseline tests +- Add metadata parsing tests for code objects with multiple AMDGPU metadata note entries. +- Updated Comgr HIP test to not rely on HIP\_COMPILER being set, or a valid HIP +installation. We can test the functionality of Comgr HIP compilation without +directly relying on HIP +- Added framework for Comgr lit tests. These tests will allow us to easily +validate generated artifacts with command-line tools like llvm-dis, +llvm-objdump, etc. Moving forward, most new Comgr tests should be written as +lit tests, and tests in comgr/test should be transitioned to comgr/test-lit. + +New Targets +----------- + - gfx940 + - gfx941 + - gfx942 + - gfx1036 + - gfx1150 + - gfx1151 + - gfx1152 + - gfx9-generic + - gfx9-4-generic + - gfx10-1-generic + - gfx10-3-generic + - gfx11-generic + - gfx12-generic + +Removed Targets +--------------- + +Significant Known Problems +-------------------------- +- Several Comgr actions currently write and read files from the filesystem, +which is a known performance issue. We aim to address this by improving +clang's virtual file system support +- Several Comgr actions currently fork new processes for compilation actions. We +aim to address this by librayizing llvm tools that are currently only useable as +a separate process. diff --git a/amd/comgr/docs/historical/ReleaseNotes-historical.md b/amd/comgr/docs/historical/ReleaseNotes-historical.md new file mode 100644 index 0000000000000..cd33f4e382e3e --- /dev/null +++ b/amd/comgr/docs/historical/ReleaseNotes-historical.md @@ -0,0 +1,31 @@ +* `2.5`: Introduce `amd_comgr_populate_mangled_names` and + `amd_comgr_get_mangled_name` APIS. +* `2.4`: Introduce `amd_comgr_create_symbolizer_info`, `amd_comgr_symbolize`, + `amd_comgr_destroy_symbolizer_info` APIS. +* `2.3`: Introduce `amd_comgr_set_data_from_file_slice` and + `amd_comgr_lookup_code_object` APIS. +* `2.2`: Introduce `amd_comgr_demangle_symbol_name` API. +* `2.1`: Add `AMD_COMGR_TIME_STATISTICS` environment variable. +* `2.0`: Add support for new target feature syntax introduced at [AMDGPUUsage](https://llvm.org/docs/AMDGPUUsage.html). +* `1.9`: Add gfx1031 +* `1.8`: Implement GNU Symbol Versioning for all exported functions. Rename + some macros exposed in `amd_comgr.h` to avoid conflicts. +* `1.7`: Add `AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC`, a + replacement for `AMD_COMGR_ACTION_ADD_DEVICE_LIBRARIES`, which is now + deprecated. +* `1.6`: Add `AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL` for Code Object V2 + kernel symbols. +* `1.5`: Add `AMD_COMGR_SYMBOL_TYPE_UNKNOWN` for unknown/unsupported ELF symbol + types. This fixes a bug where these symbols were previously reported as + `AMD_COMGR_SYMBOL_TYPE_NOTYPE`. +* `1.4`: Support out-of-process HIP compilation to fat binary. +* `1.3`: Introduce `amd_comgr_action_info_set_option_list`, + `amd_comgr_action_info_get_option_list_count`, and + `amd_comgr_action_info_get_option_list_item` to replace the old option APIs + `amd_comgr_action_info_set_options` and `amd_comgr_action_info_get_options`. + The old APIs do not support arguments with embedded delimiters, and are + replaced with an array-oriented API. The old APIs are deprecated and will be + removed in a future version of the library. +* `1.2`: Introduce `amd_comgr_disassemble_instruction` and associated APIS. +* `1.1`: First versioned release. Versions before this have no guaranteed + compatibility. diff --git a/amd/comgr/include/amd_comgr.h.in b/amd/comgr/include/amd_comgr.h.in new file mode 100644 index 0000000000000..6a91b38e39e98 --- /dev/null +++ b/amd/comgr/include/amd_comgr.h.in @@ -0,0 +1,2665 @@ +//===- amd_comgr.h.in - User-facing APIs ----------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file defines the user-facing Comgr APIs, including compilation, +/// metadata, and disassembly, symbol lookup, and symbolization APIs. +/// +/// It is copied into amd_comgr.h by CMake during the Comgr build. +/// +//===----------------------------------------------------------------------===// + +#ifndef AMD_COMGR_H_ +#define AMD_COMGR_H_ + +#include /* size_t */ +#include + +#ifndef __cplusplus +#include /* bool */ +#endif /* __cplusplus */ + +/* Placeholder for calling convention and import/export macros */ +#ifndef AMD_COMGR_CALL +#define AMD_COMGR_CALL +#endif + +// Add deprecation support for Comgr on Linux +// This can be removed in favor of generic [[deprecated]] in C23, which should +// also allow us to more easily include support on Windows + +#ifndef AMD_COMGR_DEPRECATED +#ifdef AMD_COMGR_BUILD +#define AMD_COMGR_DEPRECATED(msg) // empty +#endif +#endif + +#ifndef AMD_COMGR_DEPRECATED +#if defined __GNUC__ && (__GNUC__ > 5 || defined __clang__) +#define AMD_COMGR_DEPRECATED(msg) __attribute__((deprecated(msg))) +#else // Windows systems, and GCC older than 6.0 +#define AMD_COMGR_DEPRECATED(msg) // empty +#endif +#endif + +#ifndef AMD_COMGR_EXPORT_DECORATOR +#ifdef __GNUC__ +#define AMD_COMGR_EXPORT_DECORATOR __attribute__ ((visibility ("default"))) +#else +#define AMD_COMGR_EXPORT_DECORATOR __declspec(dllexport) +#endif +#endif + +#ifndef AMD_COMGR_IMPORT_DECORATOR +#ifdef __GNUC__ +#define AMD_COMGR_IMPORT_DECORATOR +#else +#define AMD_COMGR_IMPORT_DECORATOR __declspec(dllimport) +#endif +#endif + +#define AMD_COMGR_API_EXPORT AMD_COMGR_EXPORT_DECORATOR AMD_COMGR_CALL +#define AMD_COMGR_API_IMPORT AMD_COMGR_IMPORT_DECORATOR AMD_COMGR_CALL + +#ifndef AMD_COMGR_API +#ifdef AMD_COMGR_EXPORT +#define AMD_COMGR_API AMD_COMGR_API_EXPORT +#else +#define AMD_COMGR_API AMD_COMGR_API_IMPORT +#endif +#endif + +#define AMD_COMGR_INTERFACE_VERSION_MAJOR @amd_comgr_VERSION_MAJOR@ +#define AMD_COMGR_INTERFACE_VERSION_MINOR @amd_comgr_VERSION_MINOR@ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** \defgroup codeobjectmanager Code Object Manager + * @{ + * + * @brief The code object manager is a callable library that provides + * operations for creating and inspecting code objects. + * + * The library provides handles to various objects. Concurrent execution of + * operations is supported provided all objects accessed by each concurrent + * operation are disjoint. For example, the @p amd_comgr_data_set_t handles + * passed to operations must be disjoint, together with all the @p + * amd_comgr_data_t handles that have been added to it. The exception is that + * the default device library data object handles can be non-disjoint as they + * are immutable. + * + * The library supports generating and inspecting code objects that + * contain machine code for a certain set of instruction set + * arhitectures (isa). The set of isa supported and information about + * the properties of the isa can be queried. + * + * The library supports performing an action that can take data + * objects of one kind, and generate new data objects of another kind. + * + * Data objects are referenced using handles using @p + * amd_comgr_data_t. The kinds of data objects are given + * by @p amd_comgr_data_kind_t. + * + * To perform an action, two @p amd_comgr_data_set_t + * objects are created. One is used to hold all the data objects + * needed by an action, and other is updated by the action with all + * the result data objects. In addition, an @p + * amd_comgr_action_info_t is created to hold + * information that controls the action. These are then passed to @p + * amd_comgr_do_action to perform an action specified by + * @p amd_comgr_action_kind_t. + * + * Data objects are reference counted and are destroyed when the + * reference count reaches 0. When a data object is created, its + * reference count is 1, it has 0 bytes of data, it has an empty name, + * and it has no metadata. + * + * Mutating a data object is only permitted before it is used as part of + * the input to an action. A data object which is the result of an action + * must not be mutated. + * + * Some data objects can have associated metadata. There are + * operations for querying this metadata. + * + * The default device library that satisfies the requirements of the + * compiler action can be obtained. + * + * The library inspects some environment variables to aid in debugging. These + * include: + * - @p AMD_COMGR_SAVE_TEMPS: If this is set, and is not "0", the library does + * not delete temporary files generated while executing compilation actions. + * These files do not appear in the current working directory, but are + * instead left in a platform-specific temporary directory (/tmp on Linux and + * C:\Temp or the path found in the TEMP environment variable on Windows). + * - @p AMD_COMGR_SAVE_LLVM_TEMPS: If this is set, and is not "0", Comgr + * forwards "--save-temps=obj" to Clang Driver invocations + * - @p AMD_COMGR_REDIRECT_LOGS: If this is not set, or is set to "0", logs are + * returned to the caller as normal. If this is set to "stdout"/"-" or + * "stderr", logs are instead redirected to the standard output or error + * stream, respectively. If this is set to any other value, it is interpreted + * as a filename which logs should be appended to. Logs may be redirected + * irrespective of whether logging is enabled. + * - @p AMD_COMGR_EMIT_VERBOSE_LOGS: If this is set, and is not "0", logs will + * include additional Comgr-specific informational messages. + */ + +/** \defgroup symbol_versions_group Symbol Versions + * + * The names used for the shared library versioned symbols. + * + * Every function is annotated with one of the version macros defined in this + * section. Each macro specifies a corresponding symbol version string. After + * dynamically loading the shared library with \p dlopen, the address of each + * function can be obtained using \p dlvsym with the name of the function and + * its corresponding symbol version string. An error will be reported by \p + * dlvsym if the installed library does not support the version for the + * function specified in this version of the interface. + * + * @{ + */ + +/** + * The function was introduced in version 1.8 of the interface and has the + * symbol version string of ``"@amd_comgr_NAME@_1.8"``. + */ +#define AMD_COMGR_VERSION_1_8 + +/** + * The function was introduced or changed in version 2.0 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_2.0"``. + */ +#define AMD_COMGR_VERSION_2_0 + +/** + * The function was introduced or changed in version 2.2 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_2.2"``. + */ +#define AMD_COMGR_VERSION_2_2 + +/** + * The function was introduced or changed in version 2.3 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_2.3"``. + */ +#define AMD_COMGR_VERSION_2_3 + +/** + * The function was introduced or changed in version 2.4 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_2.4"``. + */ +#define AMD_COMGR_VERSION_2_4 + +/** + * The function was introduced or changed in version 2.5 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_2.5"``. + */ +#define AMD_COMGR_VERSION_2_5 + +/** + * The function was introduced or changed in version 2.6 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_2.6"``. + */ +#define AMD_COMGR_VERSION_2_6 + +/** + * The function was introduced or changed in version 2.7 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_2.7"``. + */ +#define AMD_COMGR_VERSION_2_7 + +/** + * The function was introduced or changed in version 2.8 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_2.8"``. + */ +#define AMD_COMGR_VERSION_2_8 + +/** + * The function was introduced or changed in version 2.9 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_2.9"``. + */ +#define AMD_COMGR_VERSION_2_9 + +/** + * The function was introduced or changed in version 3.0 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_3.0"``. + */ +#define AMD_COMGR_VERSION_3_0 + +/** + * The function was introduced or changed in version 3.1 of the interface + * and has the symbol version string of ``"@amd_comgr_NAME@_3.1"``. + */ +#define AMD_COMGR_VERSION_3_1 + +/** @} */ + +/** + * @brief Status codes. + */ +typedef enum amd_comgr_status_s { + /** + * The function has been executed successfully. + */ + AMD_COMGR_STATUS_SUCCESS = 0x0, + /** + * A generic error has occurred. + */ + AMD_COMGR_STATUS_ERROR = 0x1, + /** + * One of the actual arguments does not meet a precondition stated + * in the documentation of the corresponding formal argument. This + * includes both invalid Action types, and invalid arguments to + * valid Action types. + */ + AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT = 0x2, + /** + * Failed to allocate the necessary resources. + */ + AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES = 0x3, +} amd_comgr_status_t; + +/** + * @brief The source languages supported by the compiler. + */ +typedef enum amd_comgr_language_s { + /** + * No high level language. + */ + AMD_COMGR_LANGUAGE_NONE = 0x0, + /** + * OpenCL 1.2. + */ + AMD_COMGR_LANGUAGE_OPENCL_1_2 = 0x1, + /** + * OpenCL 2.0. + */ + AMD_COMGR_LANGUAGE_OPENCL_2_0 = 0x2, + /** + * HIP. + */ + AMD_COMGR_LANGUAGE_HIP = 0x3, + /** + * LLVM IR, either textual (.ll) or bitcode (.bc) format. + */ + AMD_COMGR_LANGUAGE_LLVM_IR = 0x4, + /** + * Marker for last valid language. + */ + AMD_COMGR_LANGUAGE_LAST = AMD_COMGR_LANGUAGE_LLVM_IR +} amd_comgr_language_t; + +/** + * @brief Query additional information about a status code. + * + * @param[in] status Status code. + * + * @param[out] status_string A NUL-terminated string that describes + * the error status. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * status is an invalid status code, or @p status_string is NULL. + */ +amd_comgr_status_t AMD_COMGR_API amd_comgr_status_string( + amd_comgr_status_t status, + const char ** status_string) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get the version of the code object manager interface + * supported. + * + * An interface is backwards compatible with an implementation with an + * equal major version, and a greater than or equal minor version. + * + * @param[out] major Major version number. + * + * @param[out] minor Minor version number. + */ +void AMD_COMGR_API amd_comgr_get_version( + size_t *major, + size_t *minor) AMD_COMGR_VERSION_1_8; + +/** + * @brief The kinds of data supported. + */ +typedef enum amd_comgr_data_kind_s { + /** + * No data is available. + */ + AMD_COMGR_DATA_KIND_UNDEF = 0x0, + /** + * The data is a textual main source. + */ + AMD_COMGR_DATA_KIND_SOURCE = 0x1, + /** + * The data is a textual source that is included in the main source + * or other include source. + */ + AMD_COMGR_DATA_KIND_INCLUDE = 0x2, + /** + * The data is a precompiled-header source that is included in the main + * source or other include source. + */ + AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER = 0x3, + /** + * The data is a diagnostic output. + */ + AMD_COMGR_DATA_KIND_DIAGNOSTIC = 0x4, + /** + * The data is a textual log output. + */ + AMD_COMGR_DATA_KIND_LOG = 0x5, + /** + * The data is compiler LLVM IR bit code for a specific isa. + */ + AMD_COMGR_DATA_KIND_BC = 0x6, + /** + * The data is a relocatable machine code object for a specific isa. + */ + AMD_COMGR_DATA_KIND_RELOCATABLE = 0x7, + /** + * The data is an executable machine code object for a specific + * isa. An executable is the kind of code object that can be loaded + * and executed. + */ + AMD_COMGR_DATA_KIND_EXECUTABLE = 0x8, + /** + * The data is a block of bytes. + */ + AMD_COMGR_DATA_KIND_BYTES = 0x9, + /** + * The data is a fat binary (clang-offload-bundler output). + */ + AMD_COMGR_DATA_KIND_FATBIN = 0x10, + /** + * The data is an archive. + */ + AMD_COMGR_DATA_KIND_AR = 0x11, + /** + * The data is a bitcode bundle. + */ + AMD_COMGR_DATA_KIND_BC_BUNDLE = 0x12, + /** + * The data is an archive bundle. + */ + AMD_COMGR_DATA_KIND_AR_BUNDLE = 0x13, + /** + * The data is an object file bundle. + */ + AMD_COMGR_DATA_KIND_OBJ_BUNDLE = 0x14, + /** + * The data is SPIR-V IR + */ + AMD_COMGR_DATA_KIND_SPIRV = 0x15, + /** + * Marker for last valid data kind. + */ + AMD_COMGR_DATA_KIND_LAST = AMD_COMGR_DATA_KIND_SPIRV +} amd_comgr_data_kind_t; + +/** + * @brief A handle to a data object. + * + * Data objects are used to hold the data which is either an input or + * output of a code object manager action. + */ +typedef struct amd_comgr_data_s { + uint64_t handle; +} amd_comgr_data_t; + +/** + * @brief A handle to an action data object. + * + * An action data object holds a set of data objects. These can be + * used as inputs to an action, or produced as the result of an + * action. + */ +typedef struct amd_comgr_data_set_s { + uint64_t handle; +} amd_comgr_data_set_t; + +/** + * @brief A handle to an action information object. + * + * An action information object holds all the necessary information, + * excluding the input data objects, required to perform an action. + */ +typedef struct amd_comgr_action_info_s { + uint64_t handle; +} amd_comgr_action_info_t; + +/** + * @brief A handle to a metadata node. + * + * A metadata node handle is used to traverse the metadata associated + * with a data node. + */ +typedef struct amd_comgr_metadata_node_s { + uint64_t handle; +} amd_comgr_metadata_node_t; + +/** + * @brief A handle to a machine code object symbol. + * + * A symbol handle is used to obtain the properties of symbols of a machine code + * object. A symbol handle is invalidated when the data object containing the + * symbol is destroyed. + */ +typedef struct amd_comgr_symbol_s { + uint64_t handle; +} amd_comgr_symbol_t; + +/** + * @brief A handle to a disassembly information object. + * + * A disassembly information object holds all the necessary information, + * excluding the input data, required to perform disassembly. + */ +typedef struct amd_comgr_disassembly_info_s { + uint64_t handle; +} amd_comgr_disassembly_info_t; + +/** + * @brief A handle to a symbolizer information object. + * + * A symbolizer information object holds all the necessary information + * required to perform symbolization. + */ +typedef struct amd_comgr_symbolizer_info_s { + uint64_t handle; +} amd_comgr_symbolizer_info_t; + +/** + * @brief Return the number of isa names supported by this version of + * the code object manager library. + * + * The isa name specifies the instruction set architecture that should + * be used in the actions that involve machine code generation or + * inspection. + * + * @param[out] count The number of isa names supported. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * count is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update action info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_isa_count( + size_t *count) AMD_COMGR_VERSION_2_0; + +/** + * @brief Return the Nth isa name supported by this version of the + * code object manager library. + * + * @param[in] index The index of the isa name to be returned. The + * first isa name is index 0. + * + * @param[out] isa_name A null terminated string that is the isa name + * being requested. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * index is greater than the number of isa name supported by this + * version of the code object manager library. @p isa_name is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update action info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_isa_name( + size_t index, + const char **isa_name) AMD_COMGR_VERSION_2_0; + + /** + * @brief Get a handle to the metadata of an isa name. + * + * The structure of the returned metadata is isa name specific and versioned + * with details specified in + * https://llvm.org/docs/AMDGPUUsage.html#code-object-metadata. + * It can include information about the + * limits for resources such as registers and memory addressing. + * + * @param[in] isa_name The isa name to query. + * + * @param[out] metadata A handle to the metadata of the isa name. If + * the isa name has no metadata then the returned handle has a kind of + * @p AMD_COMGR_METADATA_KIND_NULL. The handle must be destroyed + * using @c amd_comgr_destroy_metadata. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * name is NULL or is not an isa name supported by this version of the + * code object manager library. @p metadata is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_isa_metadata( + const char *isa_name, + amd_comgr_metadata_node_t *metadata) AMD_COMGR_VERSION_2_0; + +/** + * @brief Create a data object that can hold data of a specified kind. + * + * @param[in] kind The kind of data the object is intended to hold. + * + * @param[out] data A handle to the data object created. Its reference + * count is set to 1. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * kind is an invalid data kind, or @p + * AMD_COMGR_DATA_KIND_UNDEF. @p data is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to create the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_create_data( + amd_comgr_data_kind_t kind, + amd_comgr_data_t *data) AMD_COMGR_VERSION_1_8; + +/** + * @brief Indicate that no longer using a data object handle. + * + * The reference count of the associated data object is + * decremented. If it reaches 0 it is destroyed. + * + * @note Although this may lead to the destruction of a data object, it is not + * considered a mutation for the purposes of the restrictions described in @ref + * codeobjectmanager. + * + * @param[in] data The data object to release. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * data is an invalid data object, or has kind @p + * AMD_COMGR_DATA_KIND_UNDEF. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_release_data( + amd_comgr_data_t data) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get the kind of the data object. + * + * @param[in] data The data object to query. + * + * @param[out] kind The kind of data the object. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * data is an invalid data object. @p kind is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to create the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_data_kind( + amd_comgr_data_t data, + amd_comgr_data_kind_t *kind) AMD_COMGR_VERSION_1_8; + +/** + * @brief Set the data content of a data object to the specified + * bytes. + * + * Any previous value of the data object is overwritten. Any metadata + * associated with the data object is also replaced which invalidates + * all metadata handles to the old metadata. + * + * @warning This function mutates the data object; see @ref codeobjectmanager + * for restrictions. + * + * @param[in] data The data object to update. + * + * @param[in] size The number of bytes in the data specified by @p bytes. + * + * @param[in] bytes The bytes to set the data object to. The bytes are + * copied into the data object and can be freed after the call. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * data is an invalid data object, or has kind @p + * AMD_COMGR_DATA_KIND_UNDEF. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_set_data( + amd_comgr_data_t data, + size_t size, + const char* bytes) AMD_COMGR_VERSION_1_8; + +/** + * @brief For the given open posix file descriptor, map a slice of the + * file into the data object. The slice is specified by @p offset and @p size. + * Internally this API calls amd_comgr_set_data and resets data object's + * current state. + * + * @warning This function mutates the data object; see @ref codeobjectmanager + * for restrictions. + * + * @param[in, out] data The data object to update. + * + * @param[in] file_descriptor The native file descriptor for an open file. + * The @p file_descriptor must not be passed into a system I/O function + * by any other thread while this function is executing. The offset in + * the file descriptor may be updated based on the requested size and + * underlying platform. The @p file_descriptor may be closed immediately + * after this function returns. + * + * @param[in] offset position relative to the start of the file + * specifying the beginning of the slice in @p file_descriptor. + * + * @param[in] size Size in bytes of the slice. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The operation is successful. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data is an invalid or + * the map operation failed. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_set_data_from_file_slice( + amd_comgr_data_t data, + int file_descriptor, + uint64_t offset, + uint64_t size) AMD_COMGR_VERSION_2_3; + +/** + * @brief Set the name associated with a data object. + * + * When compiling, the full name of an include directive is used to + * reference the contents of the include data object with the same + * name. The name may also be used for other data objects in log and + * diagnostic output. + * + * @warning This function mutates the data object; see @ref codeobjectmanager + * for restrictions. + * + * @param[in] data The data object to update. + * + * @param[in] name A null terminated string that specifies the name to + * use for the data object. If NULL then the name is set to the empty + * string. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * data is an invalid data object, or has kind @p + * AMD_COMGR_DATA_KIND_UNDEF. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_set_data_name( + amd_comgr_data_t data, + const char* name) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get the data contents, and/or the size of the data + * associated with a data object. + * + * @param[in] data The data object to query. + * + * @param[in, out] size On entry, the size of @p bytes. On return, if @p bytes + * is NULL, set to the size of the data object contents. + * + * @param[out] bytes If not NULL, then the first @p size bytes of the + * data object contents is copied. If NULL, no data is copied, and + * only @p size is updated (useful in order to find the size of buffer + * required to copy the data). + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * data is an invalid data object, or has kind @p + * AMD_COMGR_DATA_KIND_UNDEF. @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_data( + amd_comgr_data_t data, + size_t *size, + char *bytes) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get the data object name and/or name length. + * + * @param[in] data The data object to query. + * + * @param[in, out] size On entry, the size of @p name. On return, the size of + * the data object name including the terminating null character. + * + * @param[out] name If not NULL, then the first @p size characters of the + * data object name are copied. If @p name is NULL, only @p size is updated + * (useful in order to find the size of buffer required to copy the name). + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * data is an invalid data object, or has kind @p + * AMD_COMGR_DATA_KIND_UNDEF. @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_data_name( + amd_comgr_data_t data, + size_t *size, + char *name) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get the data object isa name and/or isa name length. + * + * @param[in] data The data object to query. + * + * @param[in, out] size On entry, the size of @p isa_name. On return, if @p + * isa_name is NULL, set to the size of the isa name including the terminating + * null character. + * + * @param[out] isa_name If not NULL, then the first @p size characters + * of the isa name are copied. If NULL, no isa name is copied, and + * only @p size is updated (useful in order to find the size of buffer + * required to copy the isa name). + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * data is an invalid data object, has kind @p + * AMD_COMGR_DATA_KIND_UNDEF, or is not an isa specific + * kind. @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_data_isa_name( + amd_comgr_data_t data, + size_t *size, + char *isa_name) AMD_COMGR_VERSION_2_0; + +/** + * @brief Create a symbolizer info object. + * + * @param[in] code_object A data object denoting a code object for which + * symbolization should be performed. The kind of this object must be + * ::AMD_COMGR_DATA_KIND_RELOCATABLE, ::AMD_COMGR_DATA_KIND_EXECUTABLE, + * or ::AMD_COMGR_DATA_KIND_BYTES. + * + * @param[in] print_symbol_callback Function called by a successfull + * symbolize query. @p symbol is a null-terminated string containing the + * symbolization of the address and @p user_data is an arbitary user data. + * The callback does not own @p symbol, and it cannot be referenced once + * the callback returns. + * + * @param[out] symbolizer_info A handle to the symbolizer info object created. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT if @p code_object is + * invalid or @p print_symbol_callback is null. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to create @p symbolizer_info as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_create_symbolizer_info( + amd_comgr_data_t code_object, + void (*print_symbol_callback)( + const char *symbol, + void *user_data), + amd_comgr_symbolizer_info_t *symbolizer_info) AMD_COMGR_VERSION_2_4; + +/** + * @brief Destroy symbolizer info object. + * + * @param[in] symbolizer_info A handle to symbolizer info object to destroy. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS on successful execution. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT if @p + * symbolizer_info is invalid. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_destroy_symbolizer_info( + amd_comgr_symbolizer_info_t symbolizer_info) AMD_COMGR_VERSION_2_4; + +/** + * @brief Symbolize an address. + * + * The @p address is symbolized using the symbol definitions of the + * @p code_object specified when the @p symbolizer_info was created. + * The @p print_symbol_callback callback function specified when the + * @p symbolizer_info was created is called passing the + * symbolization result as @p symbol and @p user_data value. + * + * If symbolization is not possible ::AMD_COMGR_STATUS_SUCCESS is returned and + * the string passed to the @p symbol argument of the @p print_symbol_callback + * specified when the @p symbolizer_info was created contains the text + * "" or "??". This is consistent with `llvm-symbolizer` utility. + * + * @param[in] symbolizer_info A handle to symbolizer info object which should be + * used to symbolize the @p address. + * + * @param[in] address An unrelocated ELF address to which symbolization + * query should be performed. + * + * @param[in] is_code if true, the symbolizer symbolize the address as code + * and the symbolization result contains filename, function name, line number + * and column number, else the symbolizer symbolize the address as data and + * the symbolizaion result contains symbol name, symbol's starting address + * and symbol size. + * + * @param[in] user_data Arbitrary user-data passed to @p print_symbol_callback + * callback as described for @p symbolizer_info argument. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * symbolizer_info is an invalid data object. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_symbolize( + amd_comgr_symbolizer_info_t symbolizer_info, + uint64_t address, + bool is_code, + void *user_data) AMD_COMGR_VERSION_2_4; + + /** + * @brief Get a handle to the metadata of a data object. + * + * @param[in] data The data object to query. + * + * @param[out] metadata A handle to the metadata of the data + * object. If the data object has no metadata then the returned handle + * has a kind of @p AMD_COMGR_METADATA_KIND_NULL. The + * handle must be destroyed using @c amd_comgr_destroy_metadata. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * data is an invalid data object, or has kind @p + * AMD_COMGR_DATA_KIND_UNDEF. @p metadata is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_data_metadata( + amd_comgr_data_t data, + amd_comgr_metadata_node_t *metadata) AMD_COMGR_VERSION_1_8; + +/** + * @brief Destroy a metadata handle. + * + * @param[in] metadata A metadata handle to destroy. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p metadata is an invalid + * metadata handle. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to update metadata + * handle as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_destroy_metadata(amd_comgr_metadata_node_t metadata) AMD_COMGR_VERSION_1_8; + +/** + * @brief Create a data set object. + * + * @param[out] data_set A handle to the data set created. Initially it + * contains no data objects. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data_set is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to create the data + * set object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_create_data_set( + amd_comgr_data_set_t *data_set) AMD_COMGR_VERSION_1_8; + +/** + * @brief Destroy a data set object. + * + * The reference counts of any associated data objects are decremented. Any + * handles to the data set object become invalid. + * + * @param[in] data_set A handle to the data set object to destroy. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data_set is an invalid + * data set object. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to update data set + * object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_destroy_data_set( + amd_comgr_data_set_t data_set) AMD_COMGR_VERSION_1_8; + +/** + * @brief Add a data object to a data set object if it is not already added. + * + * The reference count of the data object is incremented. + * + * @param[in] data_set A handle to the data set object to be updated. + * + * @param[in] data A handle to the data object to be added. If @p data_set + * already has the specified handle present, then it is not added. The order + * that data objects are added is preserved. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data_set is an invalid + * data set object. @p data is an invalid data object; has undef kind; has + * include kind but does not have a name. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to update data set + * object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_data_set_add( + amd_comgr_data_set_t data_set, + amd_comgr_data_t data) AMD_COMGR_VERSION_1_8; + +/** + * @brief Remove all data objects of a specified kind from a data set object. + * + * The reference count of the removed data objects is decremented. + * + * @param[in] data_set A handle to the data set object to be updated. + * + * @param[in] data_kind The data kind of the data objects to be removed. If @p + * AMD_COMGR_DATA_KIND_UNDEF is specified then all data objects are removed. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data_set is an invalid + * data set object. @p data_kind is an invalid data kind. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to update data set + * object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_data_set_remove( + amd_comgr_data_set_t data_set, + amd_comgr_data_kind_t data_kind) AMD_COMGR_VERSION_1_8; + +/** + * @brief Return the number of data objects of a specified data kind that are + * added to a data set object. + * + * @param[in] data_set A handle to the data set object to be queried. + * + * @param[in] data_kind The data kind of the data objects to be counted. + * + * @param[out] count The number of data objects of data kind @p data_kind. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data_set is an invalid + * data set object. @p data_kind is an invalid data kind or @p + * AMD_COMGR_DATA_KIND_UNDEF. @p count is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to query data set + * object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_data_count( + amd_comgr_data_set_t data_set, + amd_comgr_data_kind_t data_kind, + size_t *count) AMD_COMGR_VERSION_1_8; + +/** + * @brief Return the Nth data object of a specified data kind that is added to a + * data set object. + * + * The reference count of the returned data object is incremented. + * + * @param[in] data_set A handle to the data set object to be queried. + * + * @param[in] data_kind The data kind of the data object to be returned. + * + * @param[in] index The index of the data object of data kind @data_kind to be + * returned. The first data object is index 0. The order of data objects matches + * the order that they were added to the data set object. + * + * @param[out] data The data object being requested. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data_set is an invalid + * data set object. @p data_kind is an invalid data kind or @p + * AMD_COMGR_DATA_KIND_UNDEF. @p index is greater than the number of data + * objects of kind @p data_kind. @p data is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to query data set + * object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_data_get_data( + amd_comgr_data_set_t data_set, + amd_comgr_data_kind_t data_kind, + size_t index, + amd_comgr_data_t *data) AMD_COMGR_VERSION_1_8; + +/** + * @brief Create an action info object. + * + * @param[out] action_info A handle to the action info object created. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to create the action info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_create_action_info( + amd_comgr_action_info_t *action_info) AMD_COMGR_VERSION_1_8; + +/** + * @brief Destroy an action info object. + * + * @param[in] action_info A handle to the action info object to destroy. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update action info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_destroy_action_info( + amd_comgr_action_info_t action_info) AMD_COMGR_VERSION_1_8; + +/** + * @brief Set the isa name of an action info object. + * + * When an action info object is created it has no isa name. Some + * actions require that the action info object has an isa name + * defined. + * + * @param[in] action_info A handle to the action info object to be + * updated. + * + * @param[in] isa_name A null terminated string that is the isa name. If NULL + * or the empty string then the isa name is cleared. The isa name is defined as + * the Code Object Target Identification string, described at + * https://llvm.org/docs/AMDGPUUsage.html#code-object-target-identification + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. @p isa_name is not an + * isa name supported by this version of the code object manager + * library. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update action info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_set_isa_name( + amd_comgr_action_info_t action_info, + const char *isa_name) AMD_COMGR_VERSION_2_0; + +/** + * @brief Get the isa name and/or isa name length. + * + * @param[in] action_info The action info object to query. + * + * @param[in, out] size On entry, the size of @p isa_name. On return, if @p + * isa_name is NULL, set to the size of the isa name including the terminating + * null character. + * + * @param[out] isa_name If not NULL, then the first @p size characters of the + * isa name are copied into @p isa_name. If the isa name is not set then an + * empty string is copied into @p isa_name. If NULL, no name is copied, and + * only @p size is updated (useful in order to find the size of buffer required + * to copy the name). + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_get_isa_name( + amd_comgr_action_info_t action_info, + size_t *size, + char *isa_name) AMD_COMGR_VERSION_2_0; + +/** + * @brief Set the source language of an action info object. + * + * When an action info object is created it has no language defined + * which is represented by @p + * AMD_COMGR_LANGUAGE_NONE. Some actions require that + * the action info object has a source language defined. + * + * @param[in] action_info A handle to the action info object to be + * updated. + * + * @param[in] language The language to set. If @p + * AMD_COMGR_LANGUAGE_NONE then the language is cleared. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. @p language is an + * invalid language. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update action info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_set_language( + amd_comgr_action_info_t action_info, + amd_comgr_language_t language) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get the language for an action info object. + * + * @param[in] action_info The action info object to query. + * + * @param[out] language The language of the action info opject. @p + * AMD_COMGR_LANGUAGE_NONE if not defined, + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. @p language is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_get_language( + amd_comgr_action_info_t action_info, + amd_comgr_language_t *language) AMD_COMGR_VERSION_1_8; + +/** + * @brief Set the options array of an action info object. + * + * This overrides any option strings or arrays previously set by calls to this + * function. + * + * An @p action_info object which had its options set with this function can + * only have its option inspected with @p + * amd_comgr_action_info_get_option_list_count and @p + * amd_comgr_action_info_get_option_list_item. + * + * @param[in] action_info A handle to the action info object to be updated. + * + * @param[in] options An array of null terminated strings. May be NULL if @p + * count is zero, which will result in an empty options array. + * + * @param[in] count The number of null terminated strings in @p options. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p action_info is an + * invalid action info object, or @p options is NULL and @p count is non-zero. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to update action + * info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_set_option_list( + amd_comgr_action_info_t action_info, + const char *options[], + size_t count) AMD_COMGR_VERSION_1_8; + +/** + * @brief Return the number of options in the options array. + * + * The @p action_info object must have had its options set with @p + * amd_comgr_action_info_set_option_list. + * + * @param[in] action_info The action info object to query. + * + * @param[out] count The number of options in the options array. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR The options of @p action_info were never + * set, or not set with @p amd_comgr_action_info_set_option_list. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p action_info is an + * invalid action info object, or @p count is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to query the data + * object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_get_option_list_count( + amd_comgr_action_info_t action_info, + size_t *count) AMD_COMGR_VERSION_1_8; + +/** + * @brief Return the Nth option string in the options array and/or that + * option's length. + * + * The @p action_info object must have had its options set with @p + * amd_comgr_action_info_set_option_list. + * + * @param[in] action_info The action info object to query. + * + * @param[in] index The index of the option to be returned. The first option + * index is 0. The order is the same as the options when they were added in @p + * amd_comgr_action_info_set_option_list. + * + * @param[in, out] size On entry, the size of @p option. On return, if @option + * is NULL, set to the size of the Nth option string including the terminating + * null character. + * + * @param[out] option If not NULL, then the first @p size characters of the Nth + * option string are copied into @p option. If NULL, no option string is + * copied, and only @p size is updated (useful in order to find the size of + * buffer required to copy the option string). + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR The options of @p action_info were never + * set, or not set with @p amd_comgr_action_info_set_option_list. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p action_info is an + * invalid action info object, @p index is invalid, or @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to query the data + * object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_get_option_list_item( + amd_comgr_action_info_t action_info, + size_t index, + size_t *size, + char *option) AMD_COMGR_VERSION_1_8; + +/** + * @brief Set the bundle entry IDs of an action info object. + * + * When an action info object is created it has no bundle entry IDs. Some + * actions require that the action info object has bundle entry IDs + * defined. + * + * @param[in] action_info A handle to the action info object to be + * updated. + * + * @param[in] bundle_entry_ids An array of strings containing one or more + * bundle entry ID strings. If NULL then the bundle entry ID strings are + * cleared. These IDs are described at + * https://clang.llvm.org/docs/ClangOffloadBundler.html#bundle-entry-id + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. @p contains an invalid + * bundle ID not supported by this version of the code object manager + * library. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update action info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_set_bundle_entry_ids( + amd_comgr_action_info_t action_info, + const char *bundle_entry_ids[], + size_t count) AMD_COMGR_VERSION_2_8; + +/** + * @brief Get number of bundle entry IDs + * + * @param[in] action_info The action info object to query. + * + * @param[out] count The number of bundle entry IDs availible. This value + * can be used as an upper bound to the Index provided to the corresponding + * amd_comgr_get_bundle_entry_id() call. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_get_bundle_entry_id_count( + amd_comgr_action_info_t action_info, + size_t *count) AMD_COMGR_VERSION_2_8; + +/** + * @brief Fetch the Nth specific bundle entry ID or that ID's length. + * + * @param[in] action_info The action info object to query. + * + * @param[in] index The index of the bundle entry ID to be returned. + * + * @param[in, out] size For out, the size of @p bundle_entry_id. For in, + * if @bundle_entry_id is NULL, set to the size of the Nth ID string including + * the terminating null character. + * + * @param[out] bundle_entry_id If not NULL, then the first @p size characters of + * the Nth bundle entry ID string are copied into @p bundle_entry_id. If NULL, + * no bundle entry ID is copied, and only @p size is updated (useful in order + * to find the size of the buffer requried to copy the bundle_entry_id string). + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_get_bundle_entry_id( + amd_comgr_action_info_t action_info, + size_t index, + size_t *size, + char *bundle_entry_id) AMD_COMGR_VERSION_2_8; + +/** + * @brief Set whether the specified action should use an + * in-memory virtual file system (VFS). + * + * @warning Environment variable @p AMD_COMGR_SAVE_TEMPS may override options + * set by this API and @p AMD_COMGR_USE_VFS. If @p AMD_COMGR_SAVE_TEMPS is set + * to "1", all actions are performed using the real file system irrespective of + * the value of @p should_use_vfs @p AMD_COMGR_USE_VFS; + * + * @warning Environment variable @p AMD_COMGR_USE_VFS may override options + * set by this API. If @p AMD_COMGR_USE_VFS is set to "1", all actions + * are performed using VFS. If @p AMD_COMGR_USE_VFS is set to "0", + * none of the actions are performed using VFS. + * + * If @p AMD_COMGR_USE_VFS is unset, this API can be used to selectively + * turn VFS usage on/off for specified actions. + * + * @param[in] action_info A handle to the action info object to be + * updated. + * + * @param[in] should_use_vfs A boolean that directs the choice to + * use the VFS. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. + * + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_set_vfs( + amd_comgr_action_info_t action_info, + bool should_use_vfs) AMD_COMGR_VERSION_3_1; + +/** + * @brief Set the device library linking behavior of an action info object. + * + * Device library linking can be either enforced or omitted for compilation + * actions. + * + * @param[in] action_info A handle to the action info object to be + * updated. + * + * @param[in] should_link_device_libs A boolean that directs the choice to + * link the device libraries. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_set_device_lib_linking( + amd_comgr_action_info_t action_info, + bool should_link_device_libs) AMD_COMGR_VERSION_2_9; + +/** + * @brief Set the working directory of an action info object. + * + * When an action info object is created it has an empty working + * directory. Some actions use the working directory to resolve + * relative file paths. + * + * @param[in] action_info A handle to the action info object to be + * updated. + * + * @param[in] path A null terminated string that is the working + * directory path. If NULL or the empty string then the working + * directory is cleared. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update action info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_set_working_directory_path( + amd_comgr_action_info_t action_info, + const char *path) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get the working directory path and/or working directory path + * length of an action info object. + * + * @param[in] action_info The action info object to query. + * + * @param[in, out] size On entry, the size of @p path. On return, if @p path is + * NULL, set to the size of the working directory path including the + * terminating null character. + * + * @param[out] path If not NULL, then the first @p size characters of + * the working directory path is copied. If the working directory path + * is not set then an empty string is copied. If NULL, the working + * directory path is not copied, and only @p size is updated (useful + * in order to find the size of buffer required to copy the working + * directory path). + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_get_working_directory_path( + amd_comgr_action_info_t action_info, + size_t *size, + char *path) AMD_COMGR_VERSION_1_8; + +/** + * @brief Set whether logging is enabled for an action info object. + * + * @param[in] action_info A handle to the action info object to be + * updated. + * + * @param[in] logging Whether logging should be enabled or disable. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_set_logging( + amd_comgr_action_info_t action_info, + bool logging) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get whether logging is enabled for an action info object. + * + * @param[in] action_info The action info object to query. + * + * @param[out] logging Whether logging is enabled. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * action_info is an invalid action info object. @p logging is NULL. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_action_info_get_logging( + amd_comgr_action_info_t action_info, + bool *logging) AMD_COMGR_VERSION_1_8; + +/** + * @brief The kinds of actions that can be performed. + */ +typedef enum amd_comgr_action_kind_s { + /** + * Preprocess each source data object in @p input in order. For each + * successful preprocessor invocation, add a source data object to @p result. + * Resolve any include source names using the names of include data objects + * in @p input. Resolve any include relative path names using the working + * directory path in @p info. Preprocess the source for the language in @p + * info. + * + * Return @p AMD_COMGR_STATUS_ERROR if any preprocessing fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if isa name or language is not set in @p info. + */ + AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR = 0x0, + /** + * Copy all existing data objects in @p input to @p output. + * + * Currently the action is a no-op, as the OpenCL pre-compiled headers + * are no longer used. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT if any of the + * input or output are not initialized. + */ + AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS + AMD_COMGR_DEPRECATED("Will be removed in Comgr v4.0. Currently the action\ + is a no-op, as the OpenCL pre-compiled headers are no longer used.") + = 0x1, + /** + * Compile each source data object in @p input in order. For each + * successful compilation add a bc data object to @p result. Resolve + * any include source names using the names of include data objects + * in @p input. Resolve any include relative path names using the + * working directory path in @p info. Produce bc for isa name in @p + * info. Compile the source for the language in @p info. + * + * Return @p AMD_COMGR_STATUS_ERROR if any compilation + * fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if isa name or language is not set in @p info. + */ + AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC = 0x2, + /** + * Link a collection of bitcodes, bundled bitcodes, and bundled bitcode + * archives in @p into a single composite (unbundled) bitcode @p. + * Any device library bc data object must be explicitly added to @p input if + * needed. + * + * Return @p AMD_COMGR_STATUS_ERROR if the link or unbundling fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if IsaName is not set in @p info and does not match the isa name + * of all bc data objects in @p input, or if the Name field is not set for + * any DataObject in the input set. + */ + AMD_COMGR_ACTION_LINK_BC_TO_BC = 0x3, + /** + * Perform code generation for each bc data object in @p input in + * order. For each successful code generation add a relocatable data + * object to @p result. + * + * Return @p AMD_COMGR_STATUS_ERROR if any code + * generation fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if isa name is not set in @p info and does not match the isa name + * of all bc data objects in @p input. + */ + AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE = 0x4, + /** + * Perform code generation for each bc data object in @p input in + * order. For each successful code generation add an assembly source data + * object to @p result. + * + * Return @p AMD_COMGR_STATUS_ERROR if any code + * generation fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if isa name is not set in @p info and does not match the isa name + * of all bc data objects in @p input. + */ + AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY = 0x5, + /** + * Link each relocatable data object in @p input together and add + * the linked relocatable data object to @p result. Any device + * library relocatable data object must be explicitly added to @p + * input if needed. + * + * Return @p AMD_COMGR_STATUS_ERROR if the link fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if isa name is not set in @p info and does not match the isa name + * of all relocatable data objects in @p input. + */ + AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE = 0x6, + /** + * Link each relocatable data object in @p input together and add + * the linked executable data object to @p result. Any device + * library relocatable data object must be explicitly added to @p + * input if needed. + * + * Return @p AMD_COMGR_STATUS_ERROR if the link fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if isa name is not set in @p info and does not match the isa name + * of all relocatable data objects in @p input. + */ + AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE = 0x7, + /** + * Assemble each source data object in @p input in order into machine code. + * For each successful assembly add a relocatable data object to @p result. + * Resolve any include source names using the names of include data objects in + * @p input. Resolve any include relative path names using the working + * directory path in @p info. Produce relocatable for isa name in @p info. + * + * Return @p AMD_COMGR_STATUS_ERROR if any assembly fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT if isa name is not set in + * @p info. + */ + AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE = 0x8, + /** + * @ deprecated + * Return @p AMD_COMGR_STATUS_ERROR_ERROR_INVALID_ARGUMENT + */ + AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE AMD_COMGR_DEPRECATED("This\ + action will return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT") = 0x9, + /** + * @ deprecated + * Return @p AMD_COMGR_STATUS_ERROR_ERROR_INVALID_ARGUMENT + */ + AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE AMD_COMGR_DEPRECATED("This\ + action will return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT") = 0xA, + /** + * @ deprecated + * Return @p AMD_COMGR_STATUS_ERROR_ERROR_INVALID_ARGUMENT + */ + AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE AMD_COMGR_DEPRECATED("This\ + action will return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT") = 0xB, + /** + * Compile each source data object in @p input in order. For each + * successful compilation add a bc data object to @p result. Resolve + * any include source names using the names of include data objects + * in @p input. Resolve any include relative path names using the + * working directory path in @p info. Produce bc for isa name in @p + * info. Compile the source for the language in @p info. Link against + * the device-specific and language-specific bitcode device libraries + * required for compilation. + * + * Return @p AMD_COMGR_STATUS_ERROR if any compilation + * fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if isa name or language is not set in @p info. + */ + AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC = 0xC, + /** + * Compile a single source data object in @p input in order. For each + * successful compilation add a relocatable data object to @p result. + * Resolve any include source names using the names of include data objects + * in @p input. Resolve any include relative path names using the + * working directory path in @p info. Produce relocatable for hip name in @p + * info. Compile the source for the language in @p info. Link against + * the device-specific and language-specific bitcode device libraries + * required for compilation. Currently only supports HIP language. + * + * Return @p AMD_COMGR_STATUS_ERROR if any compilation + * fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if isa name or language is not set in @p info. + */ + AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE = 0xD, + /** + * Compile each source data object in @p input and create a single executabele + * in @p result. Resolve any include source names using the names of include + * data objects in @p input. Resolve any include relative path names using the + * working directory path in @p info. Produce executable for isa name in @p + * info. Compile the source for the language in @p info. Link against + * the device-specific and language-specific bitcode device libraries + * required for compilation. + * + * Return @p AMD_COMGR_STATUS_ERROR if any compilation + * fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if isa name or language is not set in @p info. + */ + AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE = 0xE, + + /** + * Unbundle each source data object in @p input. These objects can be + * bitcode bundles, or an archive containing bitcode bundles. For each + * successful unbundling, add a bc object or archive object to @p result, + * depending on the corresponding input. + * + * Return @p AMD_COMGR_STATUS_ERROR if any unbundling + * fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if isa name or language is not set in @p info. + */ + AMD_COMGR_ACTION_UNBUNDLE = 0xF, + + /** + * Compile each source SPIR-V object in @p input into a relocatable. + * For each successful compilation, add a relocatable object to @p result + * + * We accomplish this by first translating the .spv files to .bc via the + * SPIR-V translator. We then extract any relevant -cc1 flags from the embedded + * @llvm.cmdline variable. Finally, we compile the bitcode to a reloctable, + * appending any extracted flags. + * + * Return @p AMD_COMGR_STATUS_ERROR if any translation, flag extraction, or + * compilation fails. + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if any input is not SPIR-V. + */ + AMD_COMGR_ACTION_COMPILE_SPIRV_TO_RELOCATABLE = 0x10, + + /** + * Translate each source SPIR-V object in @p input into LLVM IR Bitcode. + * For each successful translation, add a bc object to @p result * + * + * Return @p AMD_COMGR_STATUS_ERROR if any translation fails + * + * Return @p AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT + * if any input is not SPIR-V. + */ + AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC = 0x13, + + /** + * Marker for last valid action kind. + */ + AMD_COMGR_ACTION_LAST = AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC +} amd_comgr_action_kind_t; + +/** + * @brief Perform an action. + * + * Each action ignores any data objects in @p input that it does not + * use. If logging is enabled in @info then @p result will have a log + * data object added. Any diagnostic data objects produced by the + * action will be added to @p result. See the description of each + * action in @p amd_comgr_action_kind_t. + * + * @param[in] kind The action to perform. + * + * @param[in] info The action info to use when performing the action. + * + * @param[in] input The input data objects to the @p kind action. + * + * @param[out] result Any data objects are removed before performing + * the action which then adds all data objects produced by the action. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR An error was + * reported when executing the action. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * kind is an invalid action kind. @p input_data or @p result_data are + * invalid action data object handles. See the description of each + * action in @p amd_comgr_action_kind_t for other + * conditions that result in this status. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_do_action( + amd_comgr_action_kind_t kind, + amd_comgr_action_info_t info, + amd_comgr_data_set_t input, + amd_comgr_data_set_t result) AMD_COMGR_VERSION_1_8; + +/** + * @brief The kinds of metadata nodes. + */ +typedef enum amd_comgr_metadata_kind_s { + /** + * The NULL metadata handle. + */ + AMD_COMGR_METADATA_KIND_NULL = 0x0, + /** + * A sting value. + */ + AMD_COMGR_METADATA_KIND_STRING = 0x1, + /** + * A map that consists of a set of key and value pairs. + */ + AMD_COMGR_METADATA_KIND_MAP = 0x2, + /** + * A list that consists of a sequence of values. + */ + AMD_COMGR_METADATA_KIND_LIST = 0x3, + /** + * Marker for last valid metadata kind. + */ + AMD_COMGR_METADATA_KIND_LAST = AMD_COMGR_METADATA_KIND_LIST +} amd_comgr_metadata_kind_t; + +/** + * @brief Get the kind of the metadata node. + * + * @param[in] metadata The metadata node to query. + * + * @param[out] kind The kind of the metadata node. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * metadata is an invalid metadata node. @p kind is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to create the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_metadata_kind( + amd_comgr_metadata_node_t metadata, + amd_comgr_metadata_kind_t *kind) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get the string and/or string length from a metadata string + * node. + * + * @param[in] metadata The metadata node to query. + * + * @param[in, out] size On entry, the size of @p string. On return, if @p + * string is NULL, set to the size of the string including the terminating null + * character. + * + * @param[out] string If not NULL, then the first @p size characters + * of the string are copied. If NULL, no string is copied, and only @p + * size is updated (useful in order to find the size of buffer required + * to copy the string). + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * metadata is an invalid metadata node, or does not have kind @p + * AMD_COMGR_METADATA_KIND_STRING. @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_metadata_string( + amd_comgr_metadata_node_t metadata, + size_t *size, + char *string) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get the map size from a metadata map node. + * + * @param[in] metadata The metadata node to query. + * + * @param[out] size The number of entries in the map. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * metadata is an invalid metadata node, or not of kind @p + * AMD_COMGR_METADATA_KIND_MAP. @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_metadata_map_size( + amd_comgr_metadata_node_t metadata, + size_t *size) AMD_COMGR_VERSION_1_8; + +/** + * @brief Iterate over the elements a metadata map node. + * + * @warning The metadata nodes which are passed to the callback are not owned + * by the callback, and are freed just after the callback returns. The callback + * must not save any references to its parameters between iterations. + * + * @param[in] metadata The metadata node to query. + * + * @param[in] callback The function to call for each entry in the map. The + * entry's key is passed in @p key, the entry's value is passed in @p value, and + * @p user_data is passed as @p user_data. If the function returns with a status + * other than @p AMD_COMGR_STATUS_SUCCESS then iteration is stopped. + * + * @param[in] user_data The value to pass to each invocation of @p + * callback. Allows context to be passed into the call back function. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR An error was + * reported by @p callback. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * metadata is an invalid metadata node, or not of kind @p + * AMD_COMGR_METADATA_KIND_MAP. @p callback is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to iterate the metadata as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_iterate_map_metadata( + amd_comgr_metadata_node_t metadata, + amd_comgr_status_t (*callback)( + amd_comgr_metadata_node_t key, + amd_comgr_metadata_node_t value, + void *user_data), + void *user_data) AMD_COMGR_VERSION_1_8; + +/** + * @brief Use a string key to lookup an element of a metadata map + * node and return the entry value. + * + * @param[in] metadata The metadata node to query. + * + * @param[in] key A null terminated string that is the key to lookup. + * + * @param[out] value The metadata node of the @p key element of the + * @p metadata map metadata node. The handle must be destroyed + * using @c amd_comgr_destroy_metadata. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR The map has no entry + * with a string key with the value @p key. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * metadata is an invalid metadata node, or not of kind @p + * AMD_COMGR_METADATA_KIND_MAP. @p key or @p value is + * NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to lookup metadata as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_metadata_lookup( + amd_comgr_metadata_node_t metadata, + const char *key, + amd_comgr_metadata_node_t *value) AMD_COMGR_VERSION_1_8; + +/** + * @brief Get the list size from a metadata list node. + * + * @param[in] metadata The metadata node to query. + * + * @param[out] size The number of entries in the list. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * metadata is an invalid metadata node, or does nopt have kind @p + * AMD_COMGR_METADATA_KIND_LIST. @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_metadata_list_size( + amd_comgr_metadata_node_t metadata, + size_t *size) AMD_COMGR_VERSION_1_8; + +/** + * @brief Return the Nth metadata node of a list metadata node. + * + * @param[in] metadata The metadata node to query. + * + * @param[in] index The index being requested. The first list element + * is index 0. + * + * @param[out] value The metadata node of the @p index element of the + * @p metadata list metadata node. The handle must be destroyed + * using @c amd_comgr_destroy_metadata. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p + * metadata is an invalid metadata node or not of kind @p + * AMD_COMGR_METADATA_INFO_LIST. @p index is greater + * than the number of list elements. @p value is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to update action data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_index_list_metadata( + amd_comgr_metadata_node_t metadata, + size_t index, + amd_comgr_metadata_node_t *value) AMD_COMGR_VERSION_1_8; + +/** + * @brief Iterate over the symbols of a machine code object. + * + * For a AMD_COMGR_DATA_KIND_RELOCATABLE the symbols in the ELF symtab section + * are iterated. For a AMD_COMGR_DATA_KIND_EXECUTABLE the symbols in the ELF + * dynsymtab are iterated. + * + * @param[in] data The data object to query. + * + * @param[in] callback The function to call for each symbol in the machine code + * data object. The symbol handle is passed in @p symbol and @p user_data is + * passed as @p user_data. If the function returns with a status other than @p + * AMD_COMGR_STATUS_SUCCESS then iteration is stopped. + * + * @param[in] user_data The value to pass to each invocation of @p + * callback. Allows context to be passed into the call back function. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR An error was + * reported by @p callback. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data is an invalid data + * object, or not of kind @p AMD_COMGR_DATA_KIND_RELOCATABLE or + * AMD_COMGR_DATA_KIND_EXECUTABLE. @p callback is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to iterate the data object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_iterate_symbols( + amd_comgr_data_t data, + amd_comgr_status_t (*callback)( + amd_comgr_symbol_t symbol, + void *user_data), + void *user_data) AMD_COMGR_VERSION_1_8; + +/** + * @brief Lookup a symbol in a machine code object by name. + * + * For a AMD_COMGR_DATA_KIND_RELOCATABLE the symbols in the ELF symtab section + * are inspected. For a AMD_COMGR_DATA_KIND_EXECUTABLE the symbols in the ELF + * dynsymtab are inspected. + * + * @param[in] data The data object to query. + * + * @param[in] name A null terminated string that is the symbol name to lookup. + * + * @param[out] symbol The symbol with the @p name. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR The machine code object has no symbol + * with @p name. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data is an invalid data + * object, or not of kind @p AMD_COMGR_DATA_KIND_RELOCATABLE or + * AMD_COMGR_DATA_KIND_EXECUTABLE. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to lookup symbol as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_symbol_lookup( + amd_comgr_data_t data, + const char *name, + amd_comgr_symbol_t *symbol) AMD_COMGR_VERSION_1_8; + +/** + * @brief Machine code object symbol type. + */ +typedef enum amd_comgr_symbol_type_s { + /** + * The symbol's type is unknown. + * + * The user should not infer any specific type for symbols which return + * `AMD_COMGR_SYMBOL_TYPE_UNKNOWN`, and these symbols may return different + * types in future releases. + */ + AMD_COMGR_SYMBOL_TYPE_UNKNOWN = -0x1, + + /** + * The symbol's type is not specified. + */ + AMD_COMGR_SYMBOL_TYPE_NOTYPE = 0x0, + + /** + * The symbol is associated with a data object, such as a variable, an array, + * and so on. + */ + AMD_COMGR_SYMBOL_TYPE_OBJECT = 0x1, + + /** + * The symbol is associated with a function or other executable code. + */ + AMD_COMGR_SYMBOL_TYPE_FUNC = 0x2, + + /** + * The symbol is associated with a section. Symbol table entries of this type + * exist primarily for relocation. + */ + AMD_COMGR_SYMBOL_TYPE_SECTION = 0x3, + + /** + * Conventionally, the symbol's name gives the name of the source file + * associated with the object file. + */ + AMD_COMGR_SYMBOL_TYPE_FILE = 0x4, + + /** + * The symbol labels an uninitialized common block. + */ + AMD_COMGR_SYMBOL_TYPE_COMMON = 0x5, + + /** + * The symbol is associated with an AMDGPU Code Object V2 kernel function. + */ + AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL = 0xa +} amd_comgr_symbol_type_t; + +/** + * @brief Machine code object symbol attributes. + */ +typedef enum amd_comgr_symbol_info_s { + /** + * The length of the symbol name in bytes. Does not include the NUL + * terminator. The type of this attribute is uint64_t. + */ + AMD_COMGR_SYMBOL_INFO_NAME_LENGTH = 0x0, + + /** + * The name of the symbol. The type of this attribute is character array with + * the length equal to the value of the @p AMD_COMGR_SYMBOL_INFO_NAME_LENGTH + * attribute plus 1 for a NUL terminator. + */ + AMD_COMGR_SYMBOL_INFO_NAME = 0x1, + + /** + * The kind of the symbol. The type of this attribute is @p + * amd_comgr_symbol_type_t. + */ + AMD_COMGR_SYMBOL_INFO_TYPE = 0x2, + + /** + * Size of the variable. The value of this attribute is undefined if the + * symbol is not a variable. The type of this attribute is uint64_t. + */ + AMD_COMGR_SYMBOL_INFO_SIZE = 0x3, + + /** + * Indicates whether the symbol is undefined. The type of this attribute is + * bool. + */ + AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED = 0x4, + + /** + * The value of the symbol. The type of this attribute is uint64_t. + */ + AMD_COMGR_SYMBOL_INFO_VALUE = 0x5, + + /** + * Marker for last valid symbol info. + */ + AMD_COMGR_SYMBOL_INFO_LAST = AMD_COMGR_SYMBOL_INFO_VALUE +} amd_comgr_symbol_info_t; + +/** + * @brief Query information about a machine code object symbol. + * + * @param[in] symbol The symbol to query. + * + * @param[in] attribute Attribute to query. + * + * @param[out] value Pointer to an application-allocated buffer where to store + * the value of the attribute. If the buffer passed by the application is not + * large enough to hold the value of attribute, the behavior is undefined. The + * type of value returned is specified by @p amd_comgr_symbol_info_t. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has + * been executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR The @p symbol does not have the requested @p + * attribute. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p symbol is an invalid + * symbol. @p attribute is an invalid value. @p value is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES + * Unable to query symbol as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_symbol_get_info( + amd_comgr_symbol_t symbol, + amd_comgr_symbol_info_t attribute, + void *value) AMD_COMGR_VERSION_1_8; + +/** + * @brief Create a disassembly info object. + * + * @param[in] isa_name A null terminated string that is the isa name of the + * target to disassemble for. The isa name is defined as the Code Object Target + * Identification string, described at + * https://llvm.org/docs/AMDGPUUsage.html#code-object-target-identification + * + * @param[in] read_memory_callback Function called to request @p size bytes + * from the program address space at @p from be read into @p to. The requested + * @p size is never zero. Returns the number of bytes which could be read, with + * the guarantee that no additional bytes will be available in any subsequent + * call. + * + * @param[in] print_instruction_callback Function called after a successful + * disassembly. @p instruction is a null terminated string containing the + * disassembled instruction. The callback does not own @p instruction, and it + * cannot be referenced once the callback returns. + * + * @param[in] print_address_annotation_callback Function called after @c + * print_instruction_callback returns, once for each instruction operand which + * was resolved to an absolute address. @p address is the absolute address in + * the program address space. It is intended to append a symbolic + * form of the address, perhaps as a comment, after the instruction disassembly + * produced by @c print_instruction_callback. + * + * @param[out] disassembly_info A handle to the disassembly info object + * created. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The disassembly info object was created. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p isa_name is NULL or + * invalid; or @p read_memory_callback, @p print_instruction_callback, + * or @p print_address_annotation_callback is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to create the + * disassembly info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_create_disassembly_info( + const char *isa_name, + uint64_t (*read_memory_callback)( + uint64_t from, + char *to, + uint64_t size, + void *user_data), + void (*print_instruction_callback)( + const char *instruction, + void *user_data), + void (*print_address_annotation_callback)( + uint64_t address, + void *user_data), + amd_comgr_disassembly_info_t *disassembly_info) AMD_COMGR_VERSION_2_0; + +/** + * @brief Destroy a disassembly info object. + * + * @param[in] disassembly_info A handle to the disassembly info object to + * destroy. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The disassembly info object was + * destroyed. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p disassembly_info is an + * invalid disassembly info object. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to destroy the + * disassembly info object as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_destroy_disassembly_info( + amd_comgr_disassembly_info_t disassembly_info) AMD_COMGR_VERSION_1_8; + +/** + * @brief Disassemble a single instruction. + * + * @param[in] address The address of the first byte of the instruction in the + * program address space. + * + * @param[in] user_data Arbitrary user-data passed to each callback function + * during disassembly. + * + * @param[out] size The number of bytes consumed to decode the + * instruction, or consumed while failing to decode an invalid instruction. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The disassembly was successful. + * + * @retval ::AMD_COMGR_STATUS_ERROR The disassembly failed. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p disassembly_info is + * invalid or @p size is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Unable to disassemble the + * instruction as out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_disassemble_instruction( + amd_comgr_disassembly_info_t disassembly_info, + uint64_t address, + void *user_data, + uint64_t *size) AMD_COMGR_VERSION_1_8; + +/** + * @brief Demangle a symbol name. + * + * @param[in] mangled_symbol_name A data object of kind @p + * AMD_COMGR_DATA_KIND_BYTES containing the mangled symbol name. + * + * @param[out] demangled_symbol_name A handle to the data object of kind @p + * AMD_COMGR_DATA_KIND_BYTES created and set to contain the demangled symbol + * name in case of successful completion. The handle must be released using + * @c amd_comgr_release_data. @p demangled_symbol_name is not updated for + * an error case. + * + * @note If the @p mangled_symbol_name cannot be demangled, it will be copied + * without changes to the @p demangled_symbol_name and AMD_COMGR_STATUS_SUCCESS + * is returned. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p mangled_symbol_name is + * an invalid data object or not of kind @p AMD_COMGR_DATA_KIND_BYTES or + * @p demangled_symbol_name is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES Out of resources. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_demangle_symbol_name( + amd_comgr_data_t mangled_symbol_name, + amd_comgr_data_t *demangled_symbol_name) AMD_COMGR_VERSION_2_2; + +/** + * @brief Fetch mangled symbol names from a code object. + * + * @param[in] data A data object of kind @p + * AMD_COMGR_DATA_KIND_EXECUTABLE or @p AMD_COMGR_DATA_KIND_BC + * + * @param[out] count The number of mangled names retrieved. This value + * can be used as an upper bound to the Index provided to the corresponding + * amd_comgr_get_mangled_name() call. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data is + * an invalid data object or not of kind @p AMD_COMGR_DATA_KIND_EXECUTABLE or + * @p AMD_COMGR_DATA_KIND_BC. + * + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_populate_mangled_names( + amd_comgr_data_t data, + size_t *count) AMD_COMGR_VERSION_2_5; + +/** + * @brief Fetch the Nth specific mangled name from a set of populated names or + * that name's length. + * + * The @p data must have had its mangled names populated with @p + * amd_comgr_populate_mangled_names. + * + * @param[in] data A data object of kind @p + * AMD_COMGR_DATA_KIND_EXECUTABLE or @p AMD_COMGR_DATA_KIND_BC used to + * identify which set of mangled names to retrive from. + * + * @param[in] index The index of the mangled name to be returned. + * + * @param[in, out] size For out, the size of @p mangled_name. For in, + * if @mangled_name is NULL, set to the size of the Nth option string including + * the terminating null character. + * + * @param[out] mangled_name If not NULL, then the first @p size characters of + * the Nth mangled name string are copied into @p mangled_name. If NULL, no + * mangled name string is copied, and only @p size is updated (useful in order + * to find the size of the buffer requried to copy the mangled_name string). + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR @p data has not been used to + * populate a set of mangled names, or index is greater than the count of + * mangled names for that data object + * + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_get_mangled_name( + amd_comgr_data_t data, + size_t index, + size_t *size, + char *mangled_name) AMD_COMGR_VERSION_2_5; + +/** + * @brief Populate a name expression map from a given code object. + * + * Used to map stub names *__amdgcn_name_expr_* in bitcodes and code + * objects generated by hip runtime to an associated (unmangled) name + * expression and (mangled) symbol name. + * + * @param[in] data A data object of kind @p + * AMD_COMGR_DATA_KIND_EXECUTABLE or @p AMD_COMGR_DATA_KIND_BC + * + * @param[out] count The number of name expressions mapped. This value + * can be used as an upper bound to the Index provided to the corresponding + * amd_comgr_map_name_expression_to_symbol_name() call. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data is + * an invalid data object or not of kind @p AMD_COMGR_DATA_KIND_EXECUTABLE or + * @p AMD_COMGR_DATA_KIND_BC. + * + * @retval ::AMD_COMGR_STATUS_ERROR LLVM API failure, which should be + * accompanied by an LLVM error message to stderr + * + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_populate_name_expression_map( + amd_comgr_data_t data, + size_t *count) AMD_COMGR_VERSION_2_6; + +/** + * @brief Fetch a related symbol name for a given name expression; + * or that name's length. + * + * The @p data must have had its name expression map populated with @p + * amd_comgr_populate_name_expression_map. + * + * @param[in] data A data object of kind @p + * AMD_COMGR_DATA_KIND_EXECUTABLE or @p AMD_COMGR_DATA_KIND_BC used to + * identify which map of name expressions to retrieve from. + * + * @param[in, out] size For out, the size of @p symbol_name. For in, + * if @symbol_name is NULL, set to the size of the Nth option string including + * the terminating null character. + * + * @param[in] name_expression A character array of a name expression. This name + * is used as the key to the name expression map in order to locate the desired + * @symbol_name. + * + * @param[out] symbol_name If not NULL, then the first @p size characters of + * the symbol name string mapped from @name_expression are copied into @p + * symbol_name. If NULL, no symbol name string is copied, and only @p size is + * updated (useful in order to find the size of the buffer required to copy the + * symbol_name string). + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function executed successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR @p data object is not valid (NULL or not of + * type bitcode or code object) + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p name_expression is not + * present in the name expression map. + * + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_map_name_expression_to_symbol_name( + amd_comgr_data_t data, + size_t *size, + const char *name_expression, + char *symbol_name) AMD_COMGR_VERSION_2_6; + +/** + * @brief A data structure for Code object information. + */ +typedef struct code_object_info_s { + /** + * ISA name representing the code object. + */ + const char *isa; + /** + * The size of the code object. + */ + size_t size; + /* + * The location of code object from the beginning + * of code object bundle. + */ + uint64_t offset; +} amd_comgr_code_object_info_t; + +/** + * @ brief Given a bundled code object and list of target id strings, extract + * correponding code object information. + * + * @param[in] data The data object for bundled code object. This should be + * of kind AMD_COMGR_DATA_KIND_FATBIN or AMD_COMGR_DATA_KIND_EXECUTABLE or + * AMD_COMGR_DATA_KIND_BYTES. The API interprets the data object of kind + * AMD_COMGR_DATA_KIND_FATBIN as a clang offload bundle and of kind + * AMD_COMGR_DATA_KIND_EXECUTABLE as an executable shared object. For a data + * object of type AMD_COMGR_DATA_KIND_BYTES the API first inspects the data + * passed to determine if it is a fatbin or an executable and performs + * the lookup. + * + * @param[in, out] info_list A list of code object information structure + * initialized with null terminated target id strings. If the target id + * is matched in the code object bundle the corresponding code object + * information is updated with offset and size of the code object. If the + * target id is not found the offset and size are set to 0. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR The code object bundle header is incorrect + * or reading bundle entries failed. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data is not of + * kind AMD_COMGR_DATA_KIND_FATBIN, or AMD_COMGR_DATA_KIND_BYTES or + * AMD_COMGR_DATA_KIND_EXECUTABLE or either @p info_list is NULL. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT if the @p data has + * invalid data. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_lookup_code_object( + amd_comgr_data_t data, + amd_comgr_code_object_info_t *info_list, + size_t info_list_size) AMD_COMGR_VERSION_2_3; + +/** + * @ brief Given a code object and an ELF virtual address, map the ELF virtual + * address to a code object offset. Also, determine if the ELF virtual address + * maps to an offset in a data region that is defined by the ELF file, but that + * does not occupy bytes in the ELF file. This is typically true of offsets that + * that refer to runtime or heap allocated memory. For ELF files with defined + * sections, these data regions are referred to as NOBITS or .bss sections. + * + * @param[in] data The data object to be inspected for the given ELF virtual + * address. This should be of kind AMD_COMGR_DATA_KIND_EXECUTABLE. + * + * @param[in] elf_virtual_address The address used to calculate the code object + * offset. + * + * @param[out] code_object_offset The code object offset returned to the caller + * based on the given ELF virtual address. + * + * @param[out] slice_size For nobits regions: the size in bytes, starting from + * the provided virtual address up to the end of the segment. In this case, the + * slice size represents the number of contiguous unreadable addresses following + * the provided address. + + * For bits regions: the size in bytes, starting from the provided virtual + * address up to either the end of the segment, or the start of a NOBITS region. + * In this case, slice size represents the number of contiguous readable + * addresses following the provided address. + * + * @param[out] nobits Set to true if the code object offset points to a location + * in a data region that does not occupy bytes in the ELF file, as described + * above. + * + * @retval ::AMD_COMGR_STATUS_SUCCESS The function has been executed + * successfully. + * + * @retval ::AMD_COMGR_STATUS_ERROR The provided code object has an invalid + * header due to a mismatch in magic, class, data, version, abi, type, or + * machine. + * + * @retval ::AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT @p data is not of + * kind AMD_COMGR_DATA_KIND_EXECUTABLE or invalid, or that the provided @p + * elf_virtual_address is not within the ranges covered by the object's + * load-type program headers. + */ +amd_comgr_status_t AMD_COMGR_API +amd_comgr_map_elf_virtual_address_to_code_object_offset( + amd_comgr_data_t data, + uint64_t elf_virtual_address, + uint64_t *code_object_offset, + uint64_t *slice_size, + bool *nobits) AMD_COMGR_VERSION_2_7; + +/** @} */ + +#ifdef __cplusplus +} /* end extern "C" block */ +#endif + +#endif /* header guard */ diff --git a/amd/comgr/src/amdcomgr.def b/amd/comgr/src/amdcomgr.def new file mode 100644 index 0000000000000..27b04dd8270f7 --- /dev/null +++ b/amd/comgr/src/amdcomgr.def @@ -0,0 +1,51 @@ +EXPORTS +amd_comgr_status_string +amd_comgr_get_version +amd_comgr_get_isa_count +amd_comgr_get_isa_name +amd_comgr_get_isa_metadata +amd_comgr_create_data +amd_comgr_release_data +amd_comgr_get_data_kind +amd_comgr_set_data +amd_comgr_get_data +amd_comgr_set_data_name +amd_comgr_get_data_name +amd_comgr_get_data_isa_name +amd_comgr_create_data_set +amd_comgr_destroy_data_set +amd_comgr_data_set_add +amd_comgr_data_set_remove +amd_comgr_action_data_count +amd_comgr_action_data_get_data +amd_comgr_create_action_info +amd_comgr_destroy_action_info +amd_comgr_action_info_set_isa_name +amd_comgr_action_info_get_isa_name +amd_comgr_action_info_set_language +amd_comgr_action_info_get_language +amd_comgr_action_info_set_option_list +amd_comgr_action_info_get_option_list_count +amd_comgr_action_info_get_option_list_item +amd_comgr_action_info_set_working_directory_path +amd_comgr_action_info_get_working_directory_path +amd_comgr_action_info_set_logging +amd_comgr_action_info_get_logging +amd_comgr_do_action +amd_comgr_get_data_metadata +amd_comgr_destroy_metadata +amd_comgr_get_metadata_kind +amd_comgr_get_metadata_string +amd_comgr_get_metadata_map_size +amd_comgr_iterate_map_metadata +amd_comgr_metadata_lookup +amd_comgr_get_metadata_list_size +amd_comgr_index_list_metadata +amd_comgr_iterate_symbols +amd_comgr_symbol_lookup +amd_comgr_symbol_get_info +amd_comgr_action_info_set_bundle_entry_ids +amd_comgr_action_info_get_bundle_entry_id_count +amd_comgr_action_info_get_bundle_entry_id +amd_comgr_action_info_set_device_lib_linking +amd_comgr_action_info_set_vfs diff --git a/amd/comgr/src/comgr-cache-command.cpp b/amd/comgr/src/comgr-cache-command.cpp new file mode 100644 index 0000000000000..1c92016ffe4ab --- /dev/null +++ b/amd/comgr/src/comgr-cache-command.cpp @@ -0,0 +1,175 @@ +//===- comgr-cache-command.cpp - CacheCommand implementation --------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the CachedCommandAdaptor: the interface and common +/// operations for commands that save their execution results in the cache. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-cache-command.h" +#include "comgr-cache.h" +#include "comgr-device-libs.h" +#include "comgr-env.h" +#include "comgr.h" + +#include +#include + +#include + +namespace COMGR { +using namespace llvm; +using namespace clang; + +std::optional +CachedCommandAdaptor::searchComgrTmpModel(StringRef S) { + // Ideally, we would use std::regex_search with the regex + // "comgr-[[:num:]]+-[[:num:]]+-[[:alnum:]]{6}". However, due to a bug in + // stdlibc++ (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85824) we have to + // roll our own search of this regular expression. This bug resulted in a + // crash in luxmarkv3, during the std::regex constructor. + + const StringRef Prefix = "comgr"; + const size_t AlnumCount = 6; + + StringRef Remaining = S; + while (!Remaining.empty()) { + size_t PosInRemaining = Remaining.find(Prefix); + if (PosInRemaining == StringRef::npos) + return std::nullopt; + + size_t PosInS = Remaining.data() + PosInRemaining - S.data(); + + Remaining = Remaining.substr(PosInRemaining + Prefix.size()); + + unsigned Pid; + if (!Remaining.consume_front("-") || + Remaining.consumeInteger(10, Pid)) { + continue; + } + + unsigned Id; + if (!Remaining.consume_front("-") || + Remaining.consumeInteger(10, Id)) { + continue; + } + + if (!Remaining.consume_front("-")) { + continue; + } + + if (Remaining.size() < AlnumCount) { + continue; + } + + // Use llvm::isAlnum and not std::isalnum. The later is locale dependent and + // can have issues depending on the stdlib version and application. + if (!all_of(Remaining.substr(0, AlnumCount), llvm::isAlnum)) { + continue; + } + + // `Remaining` begin is one after the end of the pattern + Remaining = Remaining.drop_front(AlnumCount); + + size_t MatchSize = Remaining.data() - S.data() - PosInS; + + return {{PosInS, MatchSize}}; + } + + return std::nullopt; +} + +void CachedCommandAdaptor::addUInt(CachedCommandAdaptor::HashAlgorithm &H, + uint64_t I) { + uint8_t Bytes[sizeof(I)]; + memcpy(&Bytes, &I, sizeof(I)); + H.update(Bytes); +} + +void CachedCommandAdaptor::addString(CachedCommandAdaptor::HashAlgorithm &H, + StringRef S) { + // hash size + contents to avoid collisions + // for example, we have to ensure that the result of hashing "AA" "BB" is + // different from "A" "ABB" + addUInt(H, S.size()); + H.update(S); +} + +void CachedCommandAdaptor::addFileContents( + CachedCommandAdaptor::HashAlgorithm &H, StringRef Buf) { + // this is a workaround temporary paths getting in the output files of the + // different commands in #line directives in preprocessed files, and the + // ModuleID or source_filename in the bitcode. + while (!Buf.empty()) { + auto ComgrTmpPos = searchComgrTmpModel(Buf); + if (!ComgrTmpPos) { + addString(H, Buf); + break; + } + + StringRef ToHash = Buf.substr(0, ComgrTmpPos->StartPosition); + addString(H, ToHash); + Buf = Buf.substr(ToHash.size() + ComgrTmpPos->MatchSize); + } +} + +Expected +CachedCommandAdaptor::getIdentifier() const { + CachedCommandAdaptor::HashAlgorithm H; + H.update(getClass()); + H.update(env::shouldEmitVerboseLogs()); + addString(H, getClangFullVersion()); + addString(H, getComgrHashIdentifier()); + H.update(getDeviceLibrariesIdentifier()); + + if (Error E = addInputIdentifier(H)) + return E; + + addOptionsIdentifier(H); + + CachedCommandAdaptor::Identifier Id; + toHex(H.final(), true, Id); + return Id; +} + +llvm::Error +CachedCommandAdaptor::writeSingleOutputFile(StringRef OutputFilename, + StringRef CachedBuffer) { + std::error_code EC; + raw_fd_ostream Out(OutputFilename, EC); + if (EC) { + Error E = createStringError(EC, Twine("Failed to open ") + OutputFilename + + " : " + EC.message() + "\n"); + return E; + } + + Out.write(CachedBuffer.data(), CachedBuffer.size()); + Out.close(); + if (Out.has_error()) { + Error E = createStringError(EC, Twine("Failed to write ") + OutputFilename + + " : " + EC.message() + "\n"); + return E; + } + + return Error::success(); +} + +Expected> +CachedCommandAdaptor::readSingleOutputFile(StringRef OutputFilename) { + ErrorOr> MBOrErr = + MemoryBuffer::getFile(OutputFilename); + if (!MBOrErr) { + std::error_code EC = MBOrErr.getError(); + return createStringError(EC, Twine("Failed to open ") + OutputFilename + + " : " + EC.message() + "\n"); + } + + return std::move(*MBOrErr); +} +} // namespace COMGR diff --git a/amd/comgr/src/comgr-cache-command.h b/amd/comgr/src/comgr-cache-command.h new file mode 100644 index 0000000000000..30bed678b967a --- /dev/null +++ b/amd/comgr/src/comgr-cache-command.h @@ -0,0 +1,65 @@ +//===- comgr-cache-command.h - CacheCommand implementation ----------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_CACHE_COMMAND_H +#define COMGR_CACHE_COMMAND_H + +#include "amd_comgr.h" + +#include +#include +#include +#include + +namespace llvm { +class raw_ostream; +} + +namespace COMGR { +class CachedCommandAdaptor { +public: + using ActionClass = + std::underlying_type_t; + using HashAlgorithm = llvm::SHA256; + using Identifier = llvm::SmallString<64>; + + llvm::Expected getIdentifier() const; + + virtual bool canCache() const = 0; + virtual llvm::Error writeExecuteOutput(llvm::StringRef CachedBuffer) = 0; + virtual llvm::Expected readExecuteOutput() = 0; + virtual amd_comgr_status_t execute(llvm::raw_ostream &LogS) = 0; + + virtual ~CachedCommandAdaptor() = default; + + // helper to work around the comgr-xxxxx string appearing in files + static void addFileContents(HashAlgorithm &H, llvm::StringRef Buf); + static void addUInt(HashAlgorithm &H, uint64_t I); + static void addString(HashAlgorithm &H, llvm::StringRef S); + + struct ComgrTmpSearchResult { + size_t StartPosition; + size_t MatchSize; + }; + static std::optional + searchComgrTmpModel(llvm::StringRef S); + + // helper since several command types just write to a single output file + static llvm::Error writeSingleOutputFile(llvm::StringRef OutputFilename, + llvm::StringRef CachedBuffer); + static llvm::Expected> + readSingleOutputFile(llvm::StringRef OutputFilename); + +protected: + virtual ActionClass getClass() const = 0; + virtual void addOptionsIdentifier(HashAlgorithm &) const = 0; + virtual llvm::Error addInputIdentifier(HashAlgorithm &) const = 0; +}; +} // namespace COMGR + +#endif diff --git a/amd/comgr/src/comgr-cache.cpp b/amd/comgr/src/comgr-cache.cpp new file mode 100644 index 0000000000000..c96f6c31cd397 --- /dev/null +++ b/amd/comgr/src/comgr-cache.cpp @@ -0,0 +1,257 @@ +//===- comgr-cache.cpp - Comgr Cache implementation -----------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the CommandCache that is used to store the +/// CachedCommandAdaptor execution results. The implementation relies on LLVM's +/// localCache. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-cache.h" +#include "comgr-cache-command.h" +#include "comgr-env.h" +#include "comgr.h" + +#include +#include +#include + +namespace COMGR { +using namespace llvm; +using namespace clang::driver; + +namespace { + +const unsigned CacheTask = 1; + +void serializeCacheEntry(llvm::raw_ostream &FS, StringRef FileContents, + StringRef Log) { + auto WriteStringRef = [&FS](StringRef Buf) { + uint64_t Size = Buf.size(); + constexpr size_t NSize = sizeof(Size); + char SizeBuf[NSize]; + memcpy(SizeBuf, &Size, NSize); + FS.write(SizeBuf, NSize); + FS.write(Buf.data(), Size); + }; + + for (StringRef *Buf : {&FileContents, &Log}) { + WriteStringRef(*Buf); + } +} + +Error deserializeCacheEntry(const llvm::MemoryBuffer &Buffer, + StringRef &FileContents, StringRef &Log) { + auto ConsumeStringRef = [&](StringRef Buffer, + StringRef &Buf) -> Expected { + uint64_t Size; + constexpr size_t NSize = sizeof(Size); + if (NSize > Buffer.size()) + return createStringError( + "Cache entry file too small: couldn't read buffer size"); + memcpy(&Size, Buffer.data(), NSize); + Buffer = Buffer.substr(NSize); + if (Size > Buffer.size()) + return createStringError( + "Cache entry file too small: couldn't read buffer"); + Buf = Buffer.substr(0, Size); + return Buffer.substr(Size); + }; + + StringRef UnreadBuffer = Buffer.getBuffer(); + for (StringRef *Buf : {&FileContents, &Log}) { + auto ErrOrUnread = ConsumeStringRef(UnreadBuffer, *Buf); + if (!ErrOrUnread) + return ErrOrUnread.takeError(); + UnreadBuffer = *ErrOrUnread; + } + + if (!UnreadBuffer.empty()) + return createStringError( + "Cache entry file too big: extra bytes after the end"); + + return Error::success(); +} + +std::function +getComgrCacheErrorHandler(llvm::raw_ostream &LogS) { + if (!env::shouldEmitVerboseLogs()) { + return [](Error E, const char *) { consumeError(std::move(E)); }; + } + + return [&LogS](Error E, const char *When) { + logAllUnhandledErrors(std::move(E), LogS, + Twine("Comgr cache, ") + When + ": "); + }; +} + +void saveCommandOutput(CachedCommandAdaptor &C, AddStreamFn &AddStream, + StringRef CapturedLogS, raw_ostream &LogS) { + auto ErrorHandler = getComgrCacheErrorHandler(LogS); + + Expected> FileOrErr = + AddStream(CacheTask, ""); + if (!FileOrErr) { + ErrorHandler(FileOrErr.takeError(), "when getting the cached file stream"); + return; + } + + Expected Buffer = C.readExecuteOutput(); + if (!Buffer) { + ErrorHandler(Buffer.takeError(), "when reading command's output"); + return; + } + + CachedFileStream *CFS = FileOrErr->get(); + serializeCacheEntry(*CFS->OS, *Buffer, CapturedLogS); + ErrorHandler(CFS->commit(), "when commiting file stream"); +} + +bool readEntryFromCache(CachedCommandAdaptor &C, MemoryBuffer &CachedBuffer, + raw_ostream &LogS) { + auto ErrorHandler = getComgrCacheErrorHandler(LogS); + + StringRef CachedOutputFile; + StringRef CachedLogS; + if (Error E = + deserializeCacheEntry(CachedBuffer, CachedOutputFile, CachedLogS)) { + ErrorHandler(std::move(E), "when reading the cache entry"); + return false; + } + + if (Error E = C.writeExecuteOutput(CachedOutputFile)) { + ErrorHandler(std::move(E), "when writing the command output"); + return false; + } + + LogS << CachedLogS; + return true; +} +} // namespace + +std::optional +CommandCache::getPolicyFromEnv(llvm::raw_ostream &LogS) { + StringRef PolicyString = COMGR::env::getCachePolicy(); + if (PolicyString.empty()) { + // Default policy: scan at most once per hour, take up at most 75% of + // available disk space or 5GB (whichever is smaller), no limit on number + // or age of files. + + CachePruningPolicy DefaultPolicy; + DefaultPolicy.Interval = std::chrono::hours(1); + DefaultPolicy.Expiration = std::chrono::hours(0); + DefaultPolicy.MaxSizePercentageOfAvailableSpace = 75; + DefaultPolicy.MaxSizeBytes = 5ul << 30; // Gb to byte; + DefaultPolicy.MaxSizeFiles = 0; + return DefaultPolicy; + } + + Expected PolicyOrErr = + parseCachePruningPolicy(PolicyString); + if (!PolicyOrErr) { + auto ErrorHandler = getComgrCacheErrorHandler(LogS); + ErrorHandler(PolicyOrErr.takeError(), "when parsing the cache policy"); + return std::nullopt; + } + return *PolicyOrErr; +} + +void CommandCache::prune() { pruneCache(CacheDir, Policy); } + +std::unique_ptr CommandCache::get(raw_ostream &LogS) { + StringRef CacheDir = env::getCacheDirectory(); + if (CacheDir.empty()) + return nullptr; + + std::optional Policy = + CommandCache::getPolicyFromEnv(LogS); + if (!Policy) + return nullptr; + + return std::unique_ptr(new CommandCache(CacheDir, *Policy)); +} + +CommandCache::CommandCache(StringRef CacheDir, const CachePruningPolicy &Policy) + : CacheDir(CacheDir.str()), Policy(Policy) { + assert(!CacheDir.empty()); +} + +CommandCache::~CommandCache() { prune(); } + +amd_comgr_status_t CommandCache::execute(CachedCommandAdaptor &C, + raw_ostream &LogS) { + + if (!C.canCache()) { + // Do not cache preprocessor commands. + // Handling include directories and constants is hard and this simplifies + // our implementation. Preprocessing is fast. + return C.execute(LogS); + } + + // This lambda will get called when the data is gotten from the cache and + // also after the data was set for a given key. + std::unique_ptr CachedBuffer; + auto AddBuffer = [&CachedBuffer](unsigned Task, const Twine &ModuleName, + std::unique_ptr M) { + CachedBuffer = std::move(M); + }; + + auto ErrorHandler = getComgrCacheErrorHandler(LogS); + + Expected CacheOrErr = + localCache("AMDGPUCompilerCache", "amdgpu-compiler", CacheDir, AddBuffer); + if (!CacheOrErr) { + ErrorHandler(CacheOrErr.takeError(), "when creating cache directory"); + return C.execute(LogS); + } + + auto MaybeId = C.getIdentifier(); + if (!MaybeId) { + ErrorHandler(MaybeId.takeError(), + "when computing the identifier for the command"); + return C.execute(LogS); + } + + FileCache &Cache = *CacheOrErr; + + // If we call the "Cache" function and the data is cached, it will call the + // "AddBuffer" lambda function from the constructor which will in turn take + // ownership of the member buffer that is passed to the callback and put it + // into the CachedBuffer member variable. + Expected AddStreamOrErr = Cache(CacheTask, *MaybeId, ""); + if (!AddStreamOrErr) { + ErrorHandler(AddStreamOrErr.takeError(), + "when building the add stream callback"); + return C.execute(LogS); + } + + // If the "AddStream" is nullptr, then the data was cached and we already + // called the "AddBuffer" lambda. + AddStreamFn &AddStream = *AddStreamOrErr; + if (!AddStream && readEntryFromCache(C, *CachedBuffer, LogS)) { + if (env::shouldEmitVerboseLogs()) + LogS << "Comgr cache: found entry " << *MaybeId << " in cache.\n"; + return AMD_COMGR_STATUS_SUCCESS; + } + + std::string CapturedLogS; + llvm::raw_string_ostream CaptureLogS(CapturedLogS); + amd_comgr_status_t Result = C.execute(CaptureLogS); + CaptureLogS.flush(); + LogS << CapturedLogS; + + if (Result == AMD_COMGR_STATUS_SUCCESS && AddStream) { + if (env::shouldEmitVerboseLogs()) + LogS << "Comgr cache: stored entry " << *MaybeId << " in cache.\n"; + saveCommandOutput(C, AddStream, CapturedLogS, LogS); + } + + return Result; +} +} // namespace COMGR diff --git a/amd/comgr/src/comgr-cache.h b/amd/comgr/src/comgr-cache.h new file mode 100644 index 0000000000000..0c110c58204a1 --- /dev/null +++ b/amd/comgr/src/comgr-cache.h @@ -0,0 +1,50 @@ +//===- comgr-cache.h - Comgr Cache implementation -------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_CACHE_H +#define COMGR_CACHE_H + +#include "amd_comgr.h" +#include "comgr-cache-command.h" + +#include +#include +#include + +#include +#include + +namespace llvm { +class raw_ostream; +} // namespace llvm + +namespace COMGR { +class CommandCache { + std::string CacheDir; + llvm::CachePruningPolicy Policy; + + CommandCache(llvm::StringRef CacheDir, + const llvm::CachePruningPolicy &Policy); + + static std::optional + getPolicyFromEnv(llvm::raw_ostream &LogS); + +public: + static std::unique_ptr get(llvm::raw_ostream &); + + ~CommandCache(); + void prune(); + + /// Checks if the Command C is cached. + /// If it is the case, it replaces its output and logs its error-stream. + /// Otherwise it executes C through the callback Execute + amd_comgr_status_t execute(CachedCommandAdaptor &C, llvm::raw_ostream &LogS); +}; +} // namespace COMGR + +#endif diff --git a/amd/comgr/src/comgr-clang-command.cpp b/amd/comgr/src/comgr-clang-command.cpp new file mode 100644 index 0000000000000..7111dcecace9f --- /dev/null +++ b/amd/comgr/src/comgr-clang-command.cpp @@ -0,0 +1,176 @@ +//===- comgr-clang-command.cpp - ClangCommand implementation --------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the CacheCommandAdaptor interface for +/// clang::driver::Commands that are stored in the cache. These correspond to +/// "clang -cc1" and "lld" invocations. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-clang-command.h" + +#include +#include + +namespace COMGR { +using namespace llvm; +using namespace clang; +namespace { +bool hasDebugOrProfileInfo(ArrayRef Args) { + // These are too difficult to handle since they generate debug info that + // refers to the temporary paths used by comgr. + const StringRef Flags[] = {"-fdebug-info-kind", "-fprofile", "-coverage", + "-ftime-trace"}; + + for (StringRef Arg : Args) { + for (StringRef Flag : Flags) { + if (Arg.starts_with(Flag)) + return true; + } + } + return false; +} + +Error addFile(CachedCommandAdaptor::HashAlgorithm &H, StringRef Path) { + auto BufOrError = MemoryBuffer::getFile(Path); + if (std::error_code EC = BufOrError.getError()) { + return errorCodeToError(EC); + } + StringRef Buf = BufOrError.get()->getBuffer(); + + CachedCommandAdaptor::addFileContents(H, Buf); + + return Error::success(); +} + +template +bool skipProblematicFlag(IteratorTy &It, const IteratorTy &End) { + // Skip include paths, these should have been handled by preprocessing the + // source first. Sadly, these are passed also to the middle-end commands. Skip + // debug related flags (they should be ignored) like -dumpdir (used for + // profiling/coverage/split-dwarf). + // Skip flags related to opencl-c headers or device-libs builtins. + StringRef Arg = *It; + static const StringSet<> FlagsWithPathArg = {"-I", "-dumpdir", "-include", + "-mlink-builtin-bitcode"}; + bool IsFlagWithPathArg = It + 1 != End && FlagsWithPathArg.contains(Arg); + if (IsFlagWithPathArg) { + ++It; + return true; + } + + // Clang always appends the debug compilation dir, + // even without debug info (in comgr it matches the current directory). We + // only consider it if the user specified debug information + const char *FlagsWithEqArg[] = {"-fcoverage-compilation-dir=", + "-fdebug-compilation-dir="}; + bool IsFlagWithSingleArg = any_of( + FlagsWithEqArg, [&](const char *Flag) { return Arg.starts_with(Flag); }); + if (IsFlagWithSingleArg) { + return true; + } + + return false; +} + +SmallVector getInputFiles(driver::Command &Command) { + const auto &CommandInputs = Command.getInputInfos(); + + SmallVector Paths; + Paths.reserve(CommandInputs.size()); + + for (const auto &II : CommandInputs) { + if (!II.isFilename()) + continue; + Paths.push_back(II.getFilename()); + } + + return Paths; +} + +} // namespace +ClangCommand::ClangCommand(driver::Command &Command, + DiagnosticOptions &DiagOpts, + IntrusiveRefCntPtr VFS, + ExecuteFnTy &&ExecuteImpl) + : Command(Command), DiagOpts(DiagOpts), VFS(VFS), + ExecuteImpl(std::move(ExecuteImpl)) {} + +Error ClangCommand::addInputIdentifier(HashAlgorithm &H) const { + auto Inputs(getInputFiles(Command)); + for (StringRef Input : Inputs) { + if (Error E = addFile(H, Input)) { + // call Error's constructor again to silence copy elision warning + return Error(std::move(E)); + } + } + return Error::success(); +} + +void ClangCommand::addOptionsIdentifier(HashAlgorithm &H) const { + auto Inputs(getInputFiles(Command)); + StringRef Output = Command.getOutputFilenames().front(); + ArrayRef Arguments = Command.getArguments(); + for (auto It = Arguments.begin(), End = Arguments.end(); It != End; ++It) { + if (skipProblematicFlag(It, End)) + continue; + + StringRef Arg = *It; + + // input files are considered by their content + // output files should not be considered at all + bool IsIOFile = Output == Arg || is_contained(Inputs, Arg); + if (IsIOFile) + continue; + +#ifndef NDEBUG + bool IsComgrTmpPath = + CachedCommandAdaptor::searchComgrTmpModel(Arg).has_value(); + // On debug builds, fail on /tmp/comgr-xxxx/... paths. + // Implicit dependencies should have been considered before. + // On release builds, add them to the hash to force a cache miss. + assert(!IsComgrTmpPath && + "Unexpected flag and path to comgr temporary directory"); +#endif + + addString(H, Arg); + } +} + +ClangCommand::ActionClass ClangCommand::getClass() const { + return Command.getSource().getKind(); +} + +bool ClangCommand::canCache() const { + bool HasOneOutput = Command.getOutputFilenames().size() == 1; + bool IsPreprocessorCommand = getClass() == driver::Action::PreprocessJobClass; + + return HasOneOutput && !IsPreprocessorCommand && + !hasDebugOrProfileInfo(Command.getArguments()); +} + +Error ClangCommand::writeExecuteOutput(StringRef CachedBuffer) { + StringRef OutputFilename = Command.getOutputFilenames().front(); + return CachedCommandAdaptor::writeSingleOutputFile(OutputFilename, + CachedBuffer); +} + +Expected ClangCommand::readExecuteOutput() { + auto MaybeBuffer = CachedCommandAdaptor::readSingleOutputFile( + Command.getOutputFilenames().front()); + if (!MaybeBuffer) + return MaybeBuffer.takeError(); + Output = std::move(*MaybeBuffer); + return Output->getBuffer(); +} + +amd_comgr_status_t ClangCommand::execute(raw_ostream &LogS) { + return ExecuteImpl(Command, LogS, DiagOpts, VFS); +} +} // namespace COMGR diff --git a/amd/comgr/src/comgr-clang-command.h b/amd/comgr/src/comgr-clang-command.h new file mode 100644 index 0000000000000..31aeee7d9e99c --- /dev/null +++ b/amd/comgr/src/comgr-clang-command.h @@ -0,0 +1,60 @@ +//===- comgr-clang-command.h - ClangCommand implementation ----------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_CLANG_COMMAND_H +#define COMGR_CLANG_COMMAND_H + +#include "comgr-cache-command.h" + +#include + +namespace clang { +class DiagnosticOptions; +namespace driver { +class Command; +} // namespace driver +} // namespace clang + +namespace COMGR { +class ClangCommand final : public CachedCommandAdaptor { +public: + using ExecuteFnTy = std::function)>; + +private: + clang::driver::Command &Command; + clang::DiagnosticOptions &DiagOpts; + llvm::IntrusiveRefCntPtr VFS; + ExecuteFnTy ExecuteImpl; + + // To avoid copies, store the output of execute, such that readExecuteOutput + // can return a reference. + std::unique_ptr Output; + +public: + ClangCommand(clang::driver::Command &Command, + clang::DiagnosticOptions &DiagOpts, + llvm::IntrusiveRefCntPtr VFS, + ExecuteFnTy &&ExecuteImpl); + + bool canCache() const override; + llvm::Error writeExecuteOutput(llvm::StringRef CachedBuffer) override; + llvm::Expected readExecuteOutput() override; + amd_comgr_status_t execute(llvm::raw_ostream &LogS) override; + + ~ClangCommand() override = default; + +protected: + ActionClass getClass() const override; + void addOptionsIdentifier(HashAlgorithm &) const override; + llvm::Error addInputIdentifier(HashAlgorithm &) const override; +}; +} // namespace COMGR + +#endif diff --git a/amd/comgr/src/comgr-compiler.cpp b/amd/comgr/src/comgr-compiler.cpp new file mode 100644 index 0000000000000..2f9126d2f030e --- /dev/null +++ b/amd/comgr/src/comgr-compiler.cpp @@ -0,0 +1,2191 @@ +//===- comgr-compiler.cpp - Comgr compiler Action internals ---------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the compilation and compilation-adjacent +/// AMD_COMGR_ACTIONs. Many of these leverage Comgr's AMDGPUCompiler class. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-compiler.h" +#include "comgr-cache.h" +#include "comgr-clang-command.h" +#include "comgr-device-libs.h" +#include "comgr-diagnostic-handler.h" +#include "comgr-env.h" +#include "comgr-spirv-command.h" +#include "comgr-unbundle-command.h" +#include "lld/Common/CommonLinkerContext.h" +#include "lld/Common/Driver.h" +#include "clang/CodeGen/CodeGenAction.h" +#include "clang/Driver/Compilation.h" +#include "clang/Driver/DriverDiagnostic.h" +#include "clang/Driver/Job.h" +#include "clang/Driver/OffloadBundler.h" +#include "clang/Driver/Options.h" +#include "clang/Driver/Tool.h" +#include "clang/Frontend/CompilerInstance.h" +#include "clang/Frontend/FrontendDiagnostic.h" +#include "clang/Frontend/TextDiagnosticPrinter.h" +#include "clang/FrontendTool/Utils.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/Bitcode/BitcodeWriter.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/Verifier.h" +#include "llvm/IRReader/IRReader.h" +#include "llvm/Linker/Linker.h" +#include "llvm/MC/MCAsmBackend.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCObjectWriter.h" +#include "llvm/MC/MCParser/MCAsmParser.h" +#include "llvm/MC/MCParser/MCTargetAsmParser.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetOptions.h" +#include "llvm/MC/TargetRegistry.h" +#include "llvm/Object/Archive.h" +#include "llvm/Support/Error.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/Path.h" +#include "llvm/Support/Process.h" +#include "llvm/Support/Signals.h" +#include "llvm/Support/VirtualFileSystem.h" +#include "llvm/Support/WithColor.h" +#include "llvm/TargetParser/Host.h" + +#include "time-stat/ts-interface.h" + +#include +#include + +LLD_HAS_DRIVER(elf) + +using namespace llvm; +using namespace llvm::opt; +using namespace llvm::sys; +using namespace clang; +using namespace clang::driver; +using namespace clang::driver::options; +using namespace COMGR::TimeStatistics; + +namespace COMGR { + +namespace { +constexpr llvm::StringLiteral LinkerJobName = "amdgpu::Linker"; + +/// \brief Helper class for representing a single invocation of the assembler. +struct AssemblerInvocation { + /// @name Target Options + /// @{ + + /// The name of the target triple to assemble for. + std::string Triple; + + /// If given, the name of the target CPU to determine which instructions + /// are legal. + std::string CPU; + + /// The list of target specific features to enable or disable -- this should + /// be a list of strings starting with '+' or '-'. + std::vector Features; + + /// The list of symbol definitions. + std::vector SymbolDefs; + + /// @} + /// @name Language Options + /// @{ + + std::vector IncludePaths; + unsigned NoInitialTextSection : 1; + unsigned SaveTemporaryLabels : 1; + unsigned GenDwarfForAssembly : 1; + unsigned RelaxELFRelocations : 1; + unsigned DwarfVersion; + std::string DwarfDebugFlags; + std::string DwarfDebugProducer; + std::string DebugCompilationDir; + llvm::DebugCompressionType CompressDebugSections = + llvm::DebugCompressionType::None; + std::string MainFileName; + + /// @} + /// @name Frontend Options + /// @{ + + std::string InputFile; + std::vector LLVMArgs; + std::string OutputPath; + enum FileType { + FT_Asm, ///< Assembly (.s) output, transliterate mode. + FT_Null, ///< No output, for timing purposes. + FT_Obj ///< Object file output. + }; + FileType OutputType; + unsigned ShowHelp : 1; + unsigned ShowVersion : 1; + + /// @} + /// @name Transliterate Options + /// @{ + + unsigned OutputAsmVariant; + unsigned ShowEncoding : 1; + unsigned ShowInst : 1; + + /// @} + /// @name Assembler Options + /// @{ + + unsigned RelaxAll : 1; + unsigned NoExecStack : 1; + unsigned FatalWarnings : 1; + unsigned IncrementalLinkerCompatible : 1; + + /// The name of the relocation model to use. + std::string RelocationModel; + + /// @} + +public: + AssemblerInvocation() { + Triple = ""; + NoInitialTextSection = 0; + InputFile = "-"; + OutputPath = "-"; + OutputType = FT_Asm; + OutputAsmVariant = 0; + ShowInst = 0; + ShowEncoding = 0; + RelaxAll = 0; + NoExecStack = 0; + FatalWarnings = 0; + IncrementalLinkerCompatible = 0; + DwarfVersion = 0; + } + + static bool createFromArgs(AssemblerInvocation &Res, + ArrayRef Argv, + DiagnosticsEngine &Diags); +}; +} // namespace + +bool AssemblerInvocation::createFromArgs(AssemblerInvocation &Opts, + ArrayRef Argv, + DiagnosticsEngine &Diags) { + bool Success = true; + + // Parse the arguments. + const OptTable &OptTbl = getDriverOptTable(); + + llvm::opt::Visibility VisibilityMask(options::CC1AsOption); + unsigned MissingArgIndex, MissingArgCount; + InputArgList Args = + OptTbl.ParseArgs(Argv, MissingArgIndex, MissingArgCount, VisibilityMask); + + // Check for missing argument error. + if (MissingArgCount) { + Diags.Report(diag::err_drv_missing_argument) + << Args.getArgString(MissingArgIndex) << MissingArgCount; + Success = false; + } + + // Issue errors on unknown arguments. + for (const Arg *A : Args.filtered(OPT_UNKNOWN)) { + auto ArgString = A->getAsString(Args); + std::string Nearest; + if (OptTbl.findNearest(ArgString, Nearest, VisibilityMask) > 1) { + Diags.Report(diag::err_drv_unknown_argument) << ArgString; + } else { + Diags.Report(diag::err_drv_unknown_argument_with_suggestion) + << ArgString << Nearest; + } + Success = false; + } + + // Construct the invocation. + + // Target Options + Opts.Triple = llvm::Triple::normalize(Args.getLastArgValue(OPT_triple)); + Opts.CPU = std::string(Args.getLastArgValue(OPT_target_cpu)); + Opts.Features = Args.getAllArgValues(OPT_target_feature); + + // Use the default target triple if unspecified. + if (Opts.Triple.empty()) { + Opts.Triple = llvm::sys::getDefaultTargetTriple(); + } + + // Language Options + Opts.IncludePaths = Args.getAllArgValues(OPT_I); + Opts.NoInitialTextSection = Args.hasArg(OPT_n); + Opts.SaveTemporaryLabels = Args.hasArg(OPT_msave_temp_labels); + // Any DebugInfoKind implies GenDwarfForAssembly. + Opts.GenDwarfForAssembly = Args.hasArg(OPT_debug_info_kind_EQ); + + if (const Arg *A = Args.getLastArg(OPT_compress_debug_sections, + OPT_compress_debug_sections_EQ)) { + if (A->getOption().getID() == OPT_compress_debug_sections) { + // TODO: be more clever about the compression type auto-detection + Opts.CompressDebugSections = llvm::DebugCompressionType::Zlib; + } else { + Opts.CompressDebugSections = + llvm::StringSwitch(A->getValue()) + .Case("none", llvm::DebugCompressionType::None) + .Case("zlib", llvm::DebugCompressionType::Zlib) + .Default(llvm::DebugCompressionType::None); + } + } + + Opts.RelaxELFRelocations = !Args.hasArg(OPT_mrelax_relocations_no); + Opts.DwarfVersion = getLastArgIntValue(Args, OPT_dwarf_version_EQ, 2, Diags); + Opts.DwarfDebugFlags = + std::string(Args.getLastArgValue(OPT_dwarf_debug_flags)); + Opts.DwarfDebugProducer = + std::string(Args.getLastArgValue(OPT_dwarf_debug_producer)); + Opts.DebugCompilationDir = + std::string(Args.getLastArgValue(OPT_fdebug_compilation_dir)); + Opts.MainFileName = std::string(Args.getLastArgValue(OPT_main_file_name)); + + // Frontend Options + if (Args.hasArg(OPT_INPUT)) { + bool First = true; + for (const Arg *A : Args.filtered(OPT_INPUT)) { + if (First) { + Opts.InputFile = A->getValue(); + First = false; + } else { + Diags.Report(diag::err_drv_unknown_argument) << A->getAsString(Args); + Success = false; + } + } + } + Opts.LLVMArgs = Args.getAllArgValues(OPT_mllvm); + Opts.OutputPath = std::string(Args.getLastArgValue(OPT_o)); + if (Arg *A = Args.getLastArg(OPT_filetype)) { + StringRef Name = A->getValue(); + unsigned OutputType = StringSwitch(Name) + .Case("asm", FT_Asm) + .Case("null", FT_Null) + .Case("obj", FT_Obj) + .Default(~0U); + if (OutputType == ~0U) { + Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Name; + Success = false; + } else { + Opts.OutputType = FileType(OutputType); + } + } + Opts.ShowHelp = Args.hasArg(OPT_help); + Opts.ShowVersion = Args.hasArg(OPT_version); + + // Transliterate Options + Opts.OutputAsmVariant = + getLastArgIntValue(Args, OPT_output_asm_variant, 0, Diags); + Opts.ShowEncoding = Args.hasArg(OPT_show_encoding); + Opts.ShowInst = Args.hasArg(OPT_show_inst); + + // Assemble Options + Opts.RelaxAll = Args.hasArg(OPT_mrelax_all); + Opts.NoExecStack = Args.hasArg(OPT_mno_exec_stack); + Opts.FatalWarnings = Args.hasArg(OPT_massembler_fatal_warnings); + Opts.RelocationModel = + std::string(Args.getLastArgValue(OPT_mrelocation_model, "pic")); + Opts.IncrementalLinkerCompatible = + Args.hasArg(OPT_mincremental_linker_compatible); + Opts.SymbolDefs = Args.getAllArgValues(OPT_defsym); + + return Success; +} + +namespace { +bool needsPreprocessing(DataObject *O) { + if (O->DataKind != AMD_COMGR_DATA_KIND_SOURCE) + return false; + StringRef Ext = path::extension(O->Name); + bool IsPreprocessedSource = Ext == ".i"; + return !IsPreprocessedSource; +} + +std::unique_ptr getOutputStream(AssemblerInvocation &Opts, + DiagnosticsEngine &Diags, + bool Binary) { + if (Opts.OutputPath.empty()) { + Opts.OutputPath = "-"; + } + + // Make sure that the Out file gets unlinked from the disk if we get a + // SIGINT. + if (Opts.OutputPath != "-") { + sys::RemoveFileOnSignal(Opts.OutputPath); + } + + std::error_code EC; + auto Out = std::make_unique( + Opts.OutputPath, EC, (Binary ? sys::fs::OF_None : sys::fs::OF_Text)); + if (EC) { + Diags.Report(diag::err_fe_unable_to_open_output) + << Opts.OutputPath << EC.message(); + return nullptr; + } + + return Out; +} + +// clang/tools/driver/cc1as_main.cpp, ExecuteAssemblerImpl() +bool executeAssemblerImpl(AssemblerInvocation &Opts, DiagnosticsEngine &Diags, + raw_ostream &LogS) { + // Get the target specific parser. + std::string Error; + const Target *TheTarget = TargetRegistry::lookupTarget( + llvm::Triple(Opts.Triple), Error); + if (!TheTarget) { + return Diags.Report(diag::err_target_unknown_triple) << Opts.Triple; + } + + ErrorOr> Buffer = + MemoryBuffer::getFileOrSTDIN(Opts.InputFile); + + if (std::error_code EC = Buffer.getError()) { + Error = EC.message(); + return Diags.Report(diag::err_fe_error_reading) << Opts.InputFile; + } + + SourceMgr SrcMgr; + SrcMgr.setDiagHandler( + [](const SMDiagnostic &SMDiag, void *LogS) { + SMDiag.print("", *(raw_ostream *)LogS, /* ShowColors */ false); + }, + &LogS); + + // Tell SrcMgr about this buffer, which is what the parser will pick up. + SrcMgr.AddNewSourceBuffer(std::move(*Buffer), SMLoc()); + + // Record the location of the include directories so that the lexer can find + // it later. + SrcMgr.setIncludeDirs(Opts.IncludePaths); + + std::unique_ptr MRI(TheTarget->createMCRegInfo( + llvm::Triple(Opts.Triple))); + assert(MRI && "Unable to create target register info!"); + + llvm::MCTargetOptions MCOptions; + MCOptions.X86RelaxRelocations = Opts.RelaxELFRelocations; + MCOptions.CompressDebugSections = Opts.CompressDebugSections; + std::unique_ptr MAI( + TheTarget->createMCAsmInfo(*MRI, llvm::Triple(Opts.Triple), MCOptions)); + assert(MAI && "Unable to create target asm info!"); + + // Ensure MCAsmInfo initialization occurs before any use, otherwise sections + // may be created with a combination of default and explicit settings. + + bool IsBinary = Opts.OutputType == AssemblerInvocation::FT_Obj; + std::unique_ptr FDOS = getOutputStream(Opts, Diags, IsBinary); + if (!FDOS) { + return true; + } + + // Build up the feature string from the target feature list. + std::string FS; + if (!Opts.Features.empty()) { + FS = Opts.Features[0]; + for (unsigned I = 1, E = Opts.Features.size(); I != E; ++I) { + FS += "," + Opts.Features[I]; + } + } + + std::unique_ptr MOFI(new MCObjectFileInfo()); + std::unique_ptr STI( + TheTarget->createMCSubtargetInfo(llvm::Triple(Opts.Triple), Opts.CPU, FS)); + + MCContext Ctx(Triple(Opts.Triple), MAI.get(), MRI.get(), STI.get(), &SrcMgr); + Ctx.setObjectFileInfo(MOFI.get()); + + bool PIC = false; + if (Opts.RelocationModel == "static") { + PIC = false; + } else if (Opts.RelocationModel == "pic") { + PIC = true; + } else { + assert(Opts.RelocationModel == "dynamic-no-pic" && "Invalid PIC model!"); + PIC = false; + } + + MOFI->initMCObjectFileInfo(Ctx, PIC); + if (Opts.GenDwarfForAssembly) { + Ctx.setGenDwarfForAssembly(true); + } + if (!Opts.DwarfDebugFlags.empty()) { + Ctx.setDwarfDebugFlags(StringRef(Opts.DwarfDebugFlags)); + } + if (!Opts.DwarfDebugProducer.empty()) { + Ctx.setDwarfDebugProducer(StringRef(Opts.DwarfDebugProducer)); + } + if (!Opts.DebugCompilationDir.empty()) { + Ctx.setCompilationDir(Opts.DebugCompilationDir); + } + if (!Opts.MainFileName.empty()) { + Ctx.setMainFileName(StringRef(Opts.MainFileName)); + } + Ctx.setDwarfVersion(Opts.DwarfVersion); + + std::unique_ptr Str; + std::unique_ptr MCII(TheTarget->createMCInstrInfo()); + + raw_pwrite_stream *Out = FDOS.get(); + std::unique_ptr BOS; + + // FIXME: There is a bit of code duplication with addPassesToEmitFile. + if (Opts.OutputType == AssemblerInvocation::FT_Asm) { + std::unique_ptr InstructionPrinter( + TheTarget->createMCInstPrinter( + llvm::Triple(Opts.Triple), Opts.OutputAsmVariant, *MAI, *MCII, *MRI)); + std::unique_ptr MCE; + std::unique_ptr MAB; + if (Opts.ShowEncoding) { + MCE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx)); + MCTargetOptions Options; + MAB.reset(TheTarget->createMCAsmBackend(*STI, *MRI, Options)); + } + auto FOut = std::make_unique(*Out); + Str.reset(TheTarget->createAsmStreamer(Ctx, std::move(FOut), std::move(InstructionPrinter), + std::move(MCE), std::move(MAB))); + } else if (Opts.OutputType == AssemblerInvocation::FT_Null) { + Str.reset(createNullStreamer(Ctx)); + } else { + assert(Opts.OutputType == AssemblerInvocation::FT_Obj && + "Invalid file type!"); + if (!FDOS->supportsSeeking()) { + BOS = std::make_unique(*FDOS); + Out = BOS.get(); + } + + MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx); + MCTargetOptions Options; + MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, Options); + Triple T(Opts.Triple); + Str.reset(TheTarget->createMCObjectStreamer( + T, Ctx, std::unique_ptr(MAB), + MAB->createObjectWriter(*Out), std::unique_ptr(CE), + *STI)); + Str.get()->initSections(Opts.NoExecStack, *STI); + } + + bool Failed = false; + + std::unique_ptr Parser( + createMCAsmParser(SrcMgr, Ctx, *Str.get(), *MAI)); + + // FIXME: init MCTargetOptions from sanitizer flags here. + MCTargetOptions Options; + std::unique_ptr TAP( + TheTarget->createMCAsmParser(*STI, *Parser, *MCII, Options)); + if (!TAP) { + Failed = Diags.Report(diag::err_target_unknown_triple) << Opts.Triple; + } + + // Set values for symbols, if any. + for (auto &S : Opts.SymbolDefs) { + auto Pair = StringRef(S).split('='); + auto Sym = Pair.first; + auto Val = Pair.second; + int64_t Value; + // We have already error checked this in the driver. + if (!Val.getAsInteger(0, Value)) { + Ctx.setSymbolValue(Parser->getStreamer(), Sym, Value); + } + } + + if (!Failed) { + Parser->setTargetParser(*TAP.get()); + Failed = Parser->Run(Opts.NoInitialTextSection); + } + + return Failed; +} + +bool executeAssembler(AssemblerInvocation &Opts, DiagnosticsEngine &Diags, + raw_ostream &LogS) { + bool Failed = executeAssemblerImpl(Opts, Diags, LogS); + + // Delete output file if there were errors. + if (Failed && Opts.OutputPath != "-") { + sys::fs::remove(Opts.OutputPath); + } + + return Failed; +} + +SmallString<128> getFilePath(DataObject *Object, StringRef Dir) { + SmallString<128> Path(Dir); + path::append(Path, Object->Name); + + // Create directories specified in the File Path so that the in-process driver + // can successfully execute clang commands that use this file path as an + // output argument + if (fs::create_directories(path::parent_path(Path))) { + return SmallString<128>(); + } + + return Path; +} + +// TODO: Move inputFromFile and outputToFile within AMDGPUCompiler +// +// Currently, we only invoke these two methods in the context of AMDGPUCompiler. +// Moreover, member functions that deal with file I/O should not worry whether +// the underlying filesystem being used is virtual or real. +amd_comgr_status_t inputFromFile(DataObject *Object, StringRef Path) { + ProfilePoint Point("FileIO"); + auto BufOrError = MemoryBuffer::getFile(Path); + if (std::error_code EC = BufOrError.getError()) { + return AMD_COMGR_STATUS_ERROR; + } + Object->setData(BufOrError.get()->getBuffer()); + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t outputToFile(StringRef Data, StringRef Path) { + SmallString<128> DirPath = Path; + path::remove_filename(DirPath); + { + ProfilePoint Point("CreateDir"); + if (fs::create_directories(DirPath)) { + return AMD_COMGR_STATUS_ERROR; + } + } + std::error_code EC; + ProfilePoint Point("FileIO"); + raw_fd_ostream OS(Path, EC, fs::OF_None); + if (EC) { + return AMD_COMGR_STATUS_ERROR; + } + OS << Data; + OS.close(); + if (OS.has_error()) { + return AMD_COMGR_STATUS_ERROR; + } + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t outputToFile(DataObject *Object, StringRef Path) { + return outputToFile(StringRef(Object->Data, Object->Size), Path); +} + +void initializeCommandLineArgs(SmallVectorImpl &Args) { + // Workaround for flawed Driver::BuildCompilation(...) implementation, + // which eliminates 1st argument, cause it actually awaits argv[0]. + Args.clear(); + Args.push_back(""); +} + +// Parse -mllvm options +amd_comgr_status_t parseLLVMOptions(const std::vector &Options) { + std::vector LLVMArgs; + for (auto Option : Options) { + LLVMArgs.push_back(""); + LLVMArgs.push_back(Option.c_str()); + if (!cl::ParseCommandLineOptions(LLVMArgs.size(), &LLVMArgs[0], + "-mllvm options parsing")) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + LLVMArgs.clear(); + } + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t linkWithLLD(llvm::ArrayRef Args, + llvm::raw_ostream &LogS, + llvm::raw_ostream &LogE) { + ArgStringList LLDArgs(llvm::iterator_range::iterator>( + Args.begin(), Args.end())); + LLDArgs.insert(LLDArgs.begin(), "ld.lld"); + LLDArgs.push_back("--threads=1"); + + ArrayRef ArgRefs = llvm::ArrayRef(LLDArgs); + lld::Result LLDRet = + lld::lldMain(ArgRefs, LogS, LogE, {{lld::Gnu, &lld::elf::link}}); + lld::CommonLinkerContext::destroy(); + if (LLDRet.retCode || !LLDRet.canRunAgain) { + return AMD_COMGR_STATUS_ERROR; + } + return AMD_COMGR_STATUS_SUCCESS; +} + +void logArgv(raw_ostream &OS, StringRef ProgramName, + ArrayRef Argv) { + OS << " Driver Job Args: " << ProgramName; + for (size_t I = 0; I < Argv.size(); ++I) { + // Skip the first argument, which we replace with ProgramName, and the last + // argument, which is a null terminator. + if (I && Argv[I]) { + OS << " \"" << Argv[I] << '\"'; + } + } + OS << '\n'; + OS.flush(); +} + +amd_comgr_status_t +executeCommand(const Command &Job, raw_ostream &LogS, + DiagnosticOptions &DiagOpts, + IntrusiveRefCntPtr FS) { + TextDiagnosticPrinter DiagClient(LogS, DiagOpts); + IntrusiveRefCntPtr DiagID(new DiagnosticIDs); + DiagnosticsEngine Diags(DiagID, DiagOpts, &DiagClient, false); + + auto Arguments = Job.getArguments(); + SmallVector Argv; + initializeCommandLineArgs(Argv); + Argv.append(Arguments.begin(), Arguments.end()); + Argv.push_back(nullptr); + + clearLLVMOptions(); + + if (Argv[1] == StringRef("-cc1")) { + if (env::shouldEmitVerboseLogs()) { + logArgv(LogS, "clang", Argv); + } + + std::unique_ptr Clang(new CompilerInstance()); + Clang->setVerboseOutputStream(LogS); + Clang->setVirtualFileSystem(FS); + if (!Argv.back()) { + Argv.pop_back(); + } + + if (!CompilerInvocation::CreateFromArgs(Clang->getInvocation(), Argv, + Diags)) { + return AMD_COMGR_STATUS_ERROR; + } + // Internally this call refers to the invocation created above, so at + // this point the DiagnosticsEngine should accurately reflect all user + // requested configuration from Argv. + Clang->createDiagnostics(&DiagClient, /* ShouldOwnClient */ false); + if (!Clang->hasDiagnostics()) { + return AMD_COMGR_STATUS_ERROR; + } + if (!ExecuteCompilerInvocation(Clang.get())) { + return AMD_COMGR_STATUS_ERROR; + } + } else if (Argv[1] == StringRef("-cc1as")) { + if (env::shouldEmitVerboseLogs()) { + logArgv(LogS, "clang", Argv); + } + Argv.erase(Argv.begin() + 1); + if (!Argv.back()) { + Argv.pop_back(); + } + AssemblerInvocation Asm; + if (!AssemblerInvocation::createFromArgs(Asm, Argv, Diags)) { + return AMD_COMGR_STATUS_ERROR; + } + if (auto Status = parseLLVMOptions(Asm.LLVMArgs)) { + return Status; + } + if (executeAssembler(Asm, Diags, LogS)) { + return AMD_COMGR_STATUS_ERROR; + } + } else if (Job.getCreator().getName() == LinkerJobName) { + if (env::shouldEmitVerboseLogs()) { + logArgv(LogS, "lld", Argv); + } + if (auto Status = linkWithLLD(Arguments, LogS, LogS)) { + return Status; + } + } else { + return AMD_COMGR_STATUS_ERROR; + } + return AMD_COMGR_STATUS_SUCCESS; +} + +std::string getStableCUID(const DataSet *InSet) { + using Hash = CachedCommandAdaptor::HashAlgorithm; + Hash H; + for (const DataObject *Input : InSet->DataObjects) { + CachedCommandAdaptor::addFileContents(H, + StringRef{Input->Data, Input->Size}); + } + return toHex(H.final()); +} +} // namespace + +amd_comgr_status_t +AMDGPUCompiler::executeInProcessDriver(ArrayRef Args) { + // A DiagnosticsEngine is required at several points: + // * By the Driver in order to diagnose option parsing. + // * By the CompilerInvocation in order to diagnose option parsing. + // * By the CompilerInstance in order to diagnose everything else. + // It is a chicken-and-egg problem in that you need some form of diagnostics + // in order to diagnose options which further influence diagnostics. The code + // here is mostly copy-and-pasted from driver.cpp/cc1_main.cpp/various Clang + // tests to try to approximate the same behavior as running the `clang` + // executable. + std::unique_ptr DiagOpts(new DiagnosticOptions); + unsigned MissingArgIndex, MissingArgCount; + InputArgList ArgList = getDriverOptTable().ParseArgs( + Args.slice(1), MissingArgIndex, MissingArgCount); + // We ignore MissingArgCount and the return value of ParseDiagnosticArgs. Any + // errors that would be diagnosed here will also be diagnosed later, when the + // DiagnosticsEngine actually exists. + (void)ParseDiagnosticArgs(*DiagOpts, ArgList); + TextDiagnosticPrinter *DiagClient = + new TextDiagnosticPrinter(LogS, *DiagOpts); + IntrusiveRefCntPtr DiagID(new DiagnosticIDs); + DiagnosticsEngine Diags(DiagID, *DiagOpts, DiagClient); + + ProcessWarningOptions(Diags, *DiagOpts, *OverlayFS, /*ReportDiags=*/false); + + Driver TheDriver((Twine(env::getLLVMPath()) + "/bin/clang").str(), + llvm::sys::getDefaultTargetTriple(), Diags, + "AMDGPU Code Object Manager", OverlayFS); + TheDriver.setCheckInputsExist(false); + + // We do not want the driver to promote -include into -include-pch. + // Otherwise, the driver may pick PCH in the wrong format, without permissions, + // in the process's CWD. + TheDriver.setProbePrecompiled(false); + + // Log arguments used to build compilation + if (env::shouldEmitVerboseLogs()) { + LogS << " Compilation Args: "; + for (size_t I = 1; I < Args.size(); ++I) { + if (Args[I]) { + LogS << " \"" << Args[I] << '\"'; + } + } + LogS << '\n'; + LogS.flush(); + } + + std::unique_ptr C(TheDriver.BuildCompilation(Args)); + if (!C || C->containsError()) { + return AMD_COMGR_STATUS_ERROR; + } + + auto Cache = CommandCache::get(LogS); + for (auto &Job : C->getJobs()) { + ClangCommand C(Job, *DiagOpts, OverlayFS, executeCommand); + if (Cache) { + if (auto Status = Cache->execute(C, LogS)) { + return Status; + } + } else { + if (auto Status = C.execute(LogS)) { + return Status; + } + } + } + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMDGPUCompiler::createTmpDirs() { + static std::atomic Id = 0; + static Process::Pid Pid = Process::getProcessId(); + + std::string TmpDirPrefix("comgr-" + std::to_string(Pid) + "-" + + std::to_string(Id++)); + + ProfilePoint Point("CreateDir"); + if (fs::createUniqueDirectory(TmpDirPrefix, TmpDir)) { + return AMD_COMGR_STATUS_ERROR; + } + + InputDir = TmpDir; + path::append(InputDir, "input"); + if (fs::create_directory(InputDir)) { + return AMD_COMGR_STATUS_ERROR; + } + + OutputDir = TmpDir; + path::append(OutputDir, "output"); + if (fs::create_directory(OutputDir)) { + return AMD_COMGR_STATUS_ERROR; + } + + IncludeDir = TmpDir; + path::append(IncludeDir, "include"); + if (fs::create_directory(IncludeDir)) { + return AMD_COMGR_STATUS_ERROR; + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +// On windows fs::remove_directories takes huge time so use fs::remove. +#ifdef _WIN32 +amd_comgr_status_t removeDirectory(const StringRef DirName) { + std::error_code EC; + for (fs::directory_iterator Dir(DirName, EC), DirEnd; Dir != DirEnd && !EC; + Dir.increment(EC)) { + const StringRef Path = Dir->path(); + + fs::file_status Status; + EC = fs::status(Path, Status); + if (EC) { + return AMD_COMGR_STATUS_ERROR; + } + + switch (Status.type()) { + case fs::file_type::regular_file: + if (fs::remove(Path)) { + return AMD_COMGR_STATUS_ERROR; + } + break; + case fs::file_type::directory_file: + if (removeDirectory(Path)) { + return AMD_COMGR_STATUS_ERROR; + } + + if (fs::remove(Path)) { + return AMD_COMGR_STATUS_ERROR; + } + break; + default: + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + } + + if (fs::remove(DirName)) { + return AMD_COMGR_STATUS_ERROR; + } + + return AMD_COMGR_STATUS_SUCCESS; +} +#endif + +amd_comgr_status_t AMDGPUCompiler::removeTmpDirs() { + if (TmpDir.empty()) { + return AMD_COMGR_STATUS_SUCCESS; + } + ProfilePoint Point("RemoveDir"); +#ifndef _WIN32 + if (fs::remove_directories(TmpDir)) { + return AMD_COMGR_STATUS_ERROR; + } + return AMD_COMGR_STATUS_SUCCESS; +#else + return removeDirectory(TmpDir); +#endif +} + +amd_comgr_status_t AMDGPUCompiler::processFile(DataObject *Input, + const char *InputFilePath, + const char *OutputFilePath) { + SmallVector Argv = Args; + + for (auto &Option : ActionInfo->getOptions()) { + Argv.push_back(Option.c_str()); + if (Option.rfind("--rocm-path", 0) == 0) { + NoGpuLib = false; + } + } + + // The ROCm device library should be provided via --rocm-path. Otherwise + // we can pass -nogpulib to build without the ROCm device library + if (NoGpuLib) { + Argv.push_back("-nogpulib"); + } + + // TODO: Enable this for OpenCL as well (SWDEV-377546) + if (getLanguage() == AMD_COMGR_LANGUAGE_HIP && env::shouldSaveLLVMTemps()) { + Argv.push_back("-save-temps=obj"); + } + + // Add SPIR-V flags + for (auto Flag : Input->SpirvFlags) { + Argv.push_back("-Xclang"); + Argv.push_back(Flag); + } + + // By default clang driver will ask CC1 to leak memory. + Argv.push_back("-Xclang"); + Argv.push_back("-no-disable-free"); + + Argv.push_back(InputFilePath); + + Argv.push_back("-o"); + Argv.push_back(OutputFilePath); + + return executeInProcessDriver(Argv); +} + +amd_comgr_status_t +AMDGPUCompiler::processFiles(amd_comgr_data_kind_t OutputKind, + const char *OutputSuffix) { + return processFiles(OutputKind, OutputSuffix, InSet); +} + +amd_comgr_status_t +AMDGPUCompiler::processFiles(amd_comgr_data_kind_t OutputKind, + const char *OutputSuffix, DataSet *InSet) { + for (auto *Input : InSet->DataObjects) { + if (Input->DataKind != AMD_COMGR_DATA_KIND_INCLUDE) { + continue; + } + auto IncludeFilePath = getFilePath(Input, IncludeDir); + if (auto Status = outputToFile(Input, IncludeFilePath)) { + return Status; + } + } + + for (auto *Input : InSet->DataObjects) { + if (Input->DataKind != AMD_COMGR_DATA_KIND_SOURCE && + Input->DataKind != AMD_COMGR_DATA_KIND_BC && + Input->DataKind != AMD_COMGR_DATA_KIND_RELOCATABLE && + Input->DataKind != AMD_COMGR_DATA_KIND_EXECUTABLE) { + continue; + } + + auto InputFilePath = getFilePath(Input, InputDir); + if (auto Status = outputToFile(Input, InputFilePath)) { + return Status; + } + + amd_comgr_data_t OutputT; + if (auto Status = amd_comgr_create_data(OutputKind, &OutputT)) { + return Status; + } + + // OutputT can be released after addition to the data_set + ScopedDataObjectReleaser SDOR(OutputT); + + DataObject *Output = DataObject::convert(OutputT); + + SmallString<128> OutputName(Input->Name); + sys::path::replace_extension(OutputName, OutputSuffix); + Output->setName(OutputName); + + auto OutputFilePath = getFilePath(Output, OutputDir); + + if (auto Status = + processFile(Input, InputFilePath.c_str(), OutputFilePath.c_str())) { + return Status; + } + + if (auto Status = inputFromFile(Output, OutputFilePath)) { + return Status; + } + + if (auto Status = amd_comgr_data_set_add(OutSetT, OutputT)) { + return Status; + } + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMDGPUCompiler::addIncludeFlags() { + if (none_of(InSet->DataObjects, needsPreprocessing)) + return AMD_COMGR_STATUS_SUCCESS; + + amd_comgr_language_t Language = ActionInfo->Language; + switch (Language) { + case AMD_COMGR_LANGUAGE_OPENCL_1_2: + case AMD_COMGR_LANGUAGE_OPENCL_2_0: { + SmallString<128> OpenCLCBasePath = IncludeDir; + sys::path::append(OpenCLCBasePath, "opencl-c-base.h"); + if (auto Status = + outputToFile(getOpenCLCBaseHeaderContents(), OpenCLCBasePath)) { + return Status; + } + Args.push_back("-include"); + Args.push_back(Saver.save(OpenCLCBasePath.c_str()).data()); + Args.push_back("-Xclang"); + Args.push_back("-fdeclare-opencl-builtins"); + break; + } + default: + break; + } + + if (ActionInfo->Path) { + Args.push_back("-I"); + Args.push_back(ActionInfo->Path); + } + + Args.push_back("-I"); + Args.push_back(IncludeDir.c_str()); + + for (auto *Input : InSet->DataObjects) { + if (Input->DataKind != AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER) { + continue; + } + PrecompiledHeaders.push_back(getFilePath(Input, IncludeDir)); + auto &PrecompiledHeaderPath = PrecompiledHeaders.back(); + if (auto Status = outputToFile(Input, PrecompiledHeaderPath)) { + return Status; + } + Args.push_back("-include-pch"); + Args.push_back(PrecompiledHeaderPath.c_str()); + Args.push_back("-Xclang"); + Args.push_back("-fno-validate-pch"); + } + + bool CacheEnabled = CommandCache::get(LogS) != nullptr; + if (PrecompiledHeaders.empty() && CacheEnabled) { + // The -no-integrated-cpp is used to split the preprocessing stage from the + // rest of the compilation jobs. The cache doesn't handle source-code input, + // but can handle preprocessed input (to avoid dealing with includes). + Args.push_back("-no-integrated-cpp"); + // The -dD option is used to keep the #define directives in the preprocessed + // output. When -fdeclare-opencl-builtins is used, the opencl builtin + // semantic analysis queries the preprocessor for macro definitions that + // signal that an OpenCL feature is enabled. After preprocessing these + // #define are gone, so the semantic analysis during the compilation stage + // fails. This flag is used to keep them such that they are present during + // the compilation stage. + // Additionally, we need to keep the definitions for #pragma directives. + // The preprocessor doesn't expand macro identifiers in #pragmas, and if we + // do not pass -dD the definitions would be missing when clang parses the + // code + Args.push_back("-dD"); + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t +AMDGPUCompiler::addTargetIdentifierFlags(llvm::StringRef IdentStr, + bool CompilingSrc = false) { + TargetIdentifier Ident; + if (auto Status = parseTargetIdentifier(IdentStr, Ident)) { + return Status; + } + + std::string GPUArch = Twine(Ident.Processor).str(); + if (!Ident.Features.empty()) { + GPUArch += ":" + join(Ident.Features, ":"); + } + + if (CompilingSrc && getLanguage() == AMD_COMGR_LANGUAGE_HIP) { + // OffloadArch + Args.push_back(Saver.save(Twine("--offload-arch=") + GPUArch).data()); + } else { + // Triple and CPU + Args.push_back("-target"); + Args.push_back( + Saver.save(Twine(Ident.Arch) + "-" + Ident.Vendor + "-" + Ident.OS) + .data()); + Args.push_back(Saver.save(Twine("-mcpu=") + GPUArch).data()); + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMDGPUCompiler::addCompilationFlags() { + // Default to O3 for all contexts + Args.push_back("-O3"); + + Args.push_back("-x"); + + bool NeedsPreprocessing = any_of(InSet->DataObjects, needsPreprocessing); + + switch (ActionInfo->Language) { + case AMD_COMGR_LANGUAGE_LLVM_IR: + Args.push_back("ir"); + break; + case AMD_COMGR_LANGUAGE_OPENCL_1_2: + Args.push_back(NeedsPreprocessing ? "cl" : "cl-cpp-output"); + Args.push_back("-std=cl1.2"); + Args.push_back("-cl-no-stdinc"); + break; + case AMD_COMGR_LANGUAGE_OPENCL_2_0: + Args.push_back(NeedsPreprocessing ? "cl" : "cl-cpp-output"); + Args.push_back("-std=cl2.0"); + Args.push_back("-cl-no-stdinc"); + break; + case AMD_COMGR_LANGUAGE_HIP: + Args.push_back(NeedsPreprocessing ? "hip" : "hip-cpp-output"); + Args.push_back("--offload-device-only"); + // Pass a cuid that depends on the input files + // Otherwise, a random (which depends on the /tmp/comgr-xxxxx path) cuid is + // generated which causes a cache miss on every run. + Args.push_back(Saver.save("-cuid=" + getStableCUID(InSet)).data()); + break; + default: + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMDGPUCompiler::addDeviceLibraries() { + + NoGpuLib = false; + + SmallString<256> ClangBinaryPath(env::getLLVMPath()); + sys::path::append(ClangBinaryPath, "bin", "clang"); + + std::string ClangResourceDir = Driver::GetResourcesPath(ClangBinaryPath); + + SmallString<256> DeviceLibPath(ClangResourceDir); + sys::path::append(DeviceLibPath, "lib"); + + SmallString<256> DeviceCodeDir(DeviceLibPath); + sys::path::append(DeviceCodeDir, "amdgcn", "bitcode"); + + if (llvm::sys::fs::exists(DeviceCodeDir)) { + Args.push_back(Saver.save(Twine("--rocm-path=") + DeviceLibPath).data()); + } else { + llvm::SmallString<128> FakeRocmDir = TmpDir; + path::append(FakeRocmDir, "rocm"); + llvm::SmallString<128> DeviceLibsDir = FakeRocmDir; + path::append(DeviceLibsDir, "amdgcn", "bitcode"); + if (fs::create_directory(InputDir)) { + return AMD_COMGR_STATUS_ERROR; + } + Args.push_back(Saver.save(Twine("--rocm-path=") + FakeRocmDir).data()); + + for (auto DeviceLib : getDeviceLibraries()) { + llvm::SmallString<128> DeviceLibPath = DeviceLibsDir; + path::append(DeviceLibPath, std::get<0>(DeviceLib)); + // TODO: We should abstract the logic of deciding whether to use the VFS + // or the real file system within inputFromFile and outputToFile. + if (UseVFS) { + if (!InMemoryFS->addFile( + DeviceLibPath, /* ModificationTime */ 0, + llvm::MemoryBuffer::getMemBuffer(std::get<1>(DeviceLib)))) { + return AMD_COMGR_STATUS_ERROR; + } + } else { + if (auto Status = outputToFile(std::get<1>(DeviceLib), DeviceLibPath)) { + return Status; + } + } + } + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMDGPUCompiler::preprocessToSource() { + if (auto Status = createTmpDirs()) { + return Status; + } + + if (ActionInfo->IsaName) { + if (auto Status = addTargetIdentifierFlags(ActionInfo->IsaName, true)) { + return Status; + } + } + + if (auto Status = addIncludeFlags()) { + return Status; + } + + if (auto Status = addCompilationFlags()) { + return Status; + } + + Args.push_back("-E"); + + return processFiles(AMD_COMGR_DATA_KIND_SOURCE, ".i"); +} + +amd_comgr_status_t AMDGPUCompiler::compileToBitcode(bool WithDeviceLibs) { + if (auto Status = createTmpDirs()) { + return Status; + } + + if (ActionInfo->IsaName) { + if (auto Status = addTargetIdentifierFlags(ActionInfo->IsaName, true)) { + return Status; + } + } + + if (auto Status = addIncludeFlags()) { + return Status; + } + + if (auto Status = addCompilationFlags()) { + return Status; + } + + Args.push_back("-c"); + Args.push_back("-emit-llvm"); + +#if _WIN32 + Args.push_back("-fshort-wchar"); +#endif + + // TODO: Deprecate WithDeviceLibs in favor of ActionInfo->ShouldLinkDeviceLibs + if (WithDeviceLibs || ActionInfo->ShouldLinkDeviceLibs) { + if (auto Status = addDeviceLibraries()) { + return Status; + } + + // Currently linking postopt is only needed for OpenCL. If this becomes + // necessary for HIP (for example if HIP adopts the same AMDGPUSimplifyLibs + // strategy that potentially introduces undefined device-library symbols), + // we will need also apply this option in compileToRelocatable(). + Args.push_back("-Xclang"); + Args.push_back("-mlink-builtin-bitcode-postopt"); + } + + return processFiles(AMD_COMGR_DATA_KIND_BC, ".bc"); +} + +amd_comgr_status_t AMDGPUCompiler::compileToExecutable() { + if (auto Status = createTmpDirs()) { + return Status; + } + + if (ActionInfo->IsaName) { + if (auto Status = addTargetIdentifierFlags(ActionInfo->IsaName, true)) { + return Status; + } + } + + if (auto Status = addIncludeFlags()) { + return Status; + } + + if (auto Status = addCompilationFlags()) { + return Status; + } + +#if _WIN32 + Args.push_back("-fshort-wchar"); +#endif + + // TODO: Remove "true" conditional once dependent APIs have included new + // new *_set_device_lib_linking API + if (ActionInfo->ShouldLinkDeviceLibs || true) { + if (auto Status = addDeviceLibraries()) { + return Status; + } + } + + return processFiles(AMD_COMGR_DATA_KIND_EXECUTABLE, ".so"); +} + +amd_comgr_status_t AMDGPUCompiler::compileToRelocatable() { + if (auto Status = createTmpDirs()) { + return Status; + } + + if (ActionInfo->Language != AMD_COMGR_LANGUAGE_HIP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (ActionInfo->IsaName) { + if (auto Status = addTargetIdentifierFlags(ActionInfo->IsaName, true)) { + return Status; + } + } + + Args.push_back("-c"); + Args.push_back("-fhip-emit-relocatable"); + Args.push_back("-mllvm"); + Args.push_back("-amdgpu-internalize-symbols"); + + if (auto Status = addIncludeFlags()) { + return Status; + } + + if (auto Status = addCompilationFlags()) { + return Status; + } + +#if _WIN32 + Args.push_back("-fshort-wchar"); +#endif + + // TODO: Remove "true" conditional once dependent APIs have included new + // new *_set_device_lib_linking API + if (ActionInfo->ShouldLinkDeviceLibs || true) { + if (auto Status = addDeviceLibraries()) { + return Status; + } + } + + return processFiles(AMD_COMGR_DATA_KIND_RELOCATABLE, ".o"); +} + +amd_comgr_status_t AMDGPUCompiler::unbundle() { + if (auto Status = createTmpDirs()) { + return Status; + } + + // Collect bitcode memory buffers from bitcodes, bundles, and archives + auto Cache = CommandCache::get(LogS); + for (auto *Input : InSet->DataObjects) { + + const char *FileExtension; + amd_comgr_data_kind_t UnbundledDataKind; + switch (Input->DataKind) { + case AMD_COMGR_DATA_KIND_BC_BUNDLE: + FileExtension = "bc"; + UnbundledDataKind = AMD_COMGR_DATA_KIND_BC; + break; + case AMD_COMGR_DATA_KIND_AR_BUNDLE: + FileExtension = "a"; + UnbundledDataKind = AMD_COMGR_DATA_KIND_AR; + break; + case AMD_COMGR_DATA_KIND_OBJ_BUNDLE: + FileExtension = "o"; + UnbundledDataKind = AMD_COMGR_DATA_KIND_EXECUTABLE; + break; + default: + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + // Configure Offload Bundler + OffloadBundlerConfig BundlerConfig; + BundlerConfig.AllowMissingBundles = true; + BundlerConfig.FilesType = FileExtension; + BundlerConfig.HipOpenmpCompatible = 1; + BundlerConfig.AllowNoHost = 1; + + // Generate random name if none provided + if (!strcmp(Input->Name, "")) { + const size_t BufSize = sizeof(char) * 30; + char *Buf = (char *)malloc(BufSize); + snprintf(Buf, BufSize, "comgr-bundle-%d.%s", std::rand() % 10000, + FileExtension); + Input->Name = Buf; + } + + // Write input file system so that OffloadBundler API can process + // TODO: Switch write to VFS + SmallString<128> InputFilePath = getFilePath(Input, InputDir); + if (auto Status = outputToFile(Input, InputFilePath)) { + return Status; + } + + // Bundler input name + BundlerConfig.InputFileNames.emplace_back(InputFilePath); + + // Generate prefix for output files + StringRef OutputPrefix = Input->Name; + size_t Index = OutputPrefix.find_last_of("."); + OutputPrefix = OutputPrefix.substr(0, Index); + + // TODO: Log Command (see linkBitcodeToBitcode() unbundling) + if (env::shouldEmitVerboseLogs()) { + LogS << " Extracting Bundle:\n" + << " Input Filename: " << BundlerConfig.InputFileNames[0] << "\n" + << " Unbundled Files Extension: ." << FileExtension << "\n"; + } + + for (StringRef Entry : ActionInfo->BundleEntryIDs) { + // Add an output file for each target + SmallString<128> OutputFilePath = OutputDir; + sys::path::append(OutputFilePath, + OutputPrefix + "-" + Entry + "." + FileExtension); + + BundlerConfig.TargetNames.emplace_back(Entry); + BundlerConfig.OutputFileNames.emplace_back(OutputFilePath); + + if (env::shouldEmitVerboseLogs()) { + LogS << "\tBundle Entry ID: " << Entry << "\n" + << "\tOutput Filename: " << OutputFilePath << "\n"; + LogS.flush(); + } + } + + UnbundleCommand Unbundle(Input->DataKind, BundlerConfig); + if (Cache) { + if (auto Status = Cache->execute(Unbundle, LogS)) { + return Status; + } + } else { + if (auto Status = Unbundle.execute(LogS)) { + return Status; + } + } + + // Add new bitcodes to OutSetT + for (StringRef OutputFilePath : BundlerConfig.OutputFileNames) { + + amd_comgr_data_t ResultT; + + if (auto Status = amd_comgr_create_data(UnbundledDataKind, &ResultT)) + return Status; + + // ResultT can be released after addition to the data_set + ScopedDataObjectReleaser SDOR(ResultT); + + DataObject *Result = DataObject::convert(ResultT); + if (auto Status = inputFromFile(Result, OutputFilePath)) + return Status; + + StringRef OutputFileName = sys::path::filename(OutputFilePath); + Result->setName(OutputFileName); + + if (auto Status = amd_comgr_data_set_add(OutSetT, ResultT)) { + return Status; + } + } + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMDGPUCompiler::linkBitcodeToBitcode() { + if (auto Status = createTmpDirs()) { + return Status; + } + + SMDiagnostic SMDiag; + LLVMContext Context; + Context.setDiagnosticHandler( + std::make_unique(this->LogS), true); + + auto Composite = std::make_unique("llvm-link", Context); + Linker L(*Composite); + unsigned ApplicableFlags = Linker::Flags::None; + + // Collect bitcode memory buffers from bitcodes, bundles, and archives + for (auto *Input : InSet->DataObjects) { + + if (!strcmp(Input->Name, "")) { + // If the calling API doesn't provide a DataObject name, generate a random + // string to assign. This string is used when the DataObject is written + // to the file system via SAVE_TEMPS, or if the object is a bundle which + // also needs a file system write for unpacking + const size_t BufSize = sizeof(char) * 30; + char *Buf = (char *)malloc(BufSize); + snprintf(Buf, BufSize, "comgr-anon-bitcode-%d.bc", std::rand() % 10000); + + Input->Name = Buf; + } + + if (env::shouldSaveTemps()) { + if (auto Status = outputToFile(Input, getFilePath(Input, InputDir))) { + return Status; + } + } + + if (Input->DataKind == AMD_COMGR_DATA_KIND_BC) { + if (env::shouldEmitVerboseLogs()) { + LogS << "\t Linking Bitcode: " << InputDir << path::get_separator() << Input->Name + << "\n"; + } + + // The data in Input outlives Mod, and the linker destructs Mod after + // linking it into composite (i.e. ownership is not transferred to the + // composite) so MemoryBuffer::getMemBuffer is sufficient. + auto Mod = + getLazyIRModule(MemoryBuffer::getMemBuffer( + StringRef(Input->Data, Input->Size), "", false), + SMDiag, Context, true); + + if (!Mod) { + SMDiag.print(Input->Name, LogS, /* ShowColors */ false); + return AMD_COMGR_STATUS_ERROR; + } + if (verifyModule(*Mod, &LogS)) + return AMD_COMGR_STATUS_ERROR; + if (L.linkInModule(std::move(Mod), ApplicableFlags)) + return AMD_COMGR_STATUS_ERROR; + } else if (Input->DataKind == AMD_COMGR_DATA_KIND_BC_BUNDLE) { + if (env::shouldEmitVerboseLogs()) { + LogS << " Linking Bundle: " << InputDir << path::get_separator() << Input->Name + << "\n"; + } + + // Determine desired bundle entry ID + // TODO: Move away from using ActionInfo->IsaName + // Use ActionInfo->BundleEntryIDs instead + if (!ActionInfo->IsaName) + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + + std::string IsaName = ActionInfo->IsaName; + size_t Index = IsaName.find("gfx"); + std::string BundleEntryId = + "hip-amdgcn-amd-amdhsa--gfx" + IsaName.substr(Index + 3); + + // Write data to file system so that Offload Bundler can process, assuming + // we didn't already write due to shouldSaveTemps() conditional above + // TODO: Switch write to VFS + if (!env::shouldSaveTemps()) { + if (auto Status = outputToFile(Input, getFilePath(Input, InputDir))) { + return Status; + } + } + + // Configure Offload Bundler + OffloadBundlerConfig BundlerConfig; + BundlerConfig.AllowMissingBundles = true; + BundlerConfig.FilesType = "bc"; + + BundlerConfig.TargetNames.push_back(BundleEntryId); + std::string InputFilePath = getFilePath(Input, InputDir).str().str(); + BundlerConfig.InputFileNames.push_back(InputFilePath); + + // Generate prefix for output files + std::string OutputPrefix = std::string(Input->Name); + Index = OutputPrefix.find_last_of("."); + OutputPrefix = OutputPrefix.substr(0, Index); + std::string OutputFileName = OutputPrefix + '-' + BundleEntryId + ".bc"; + + // ISA name may contain ':', which is an invalid character in file names + // on Windows. Replace with '_' + std::replace(OutputFileName.begin(), OutputFileName.end(), ':', '_'); + + std::string OutputFilePath = OutputDir.str().str() + path::get_separator().str() + OutputFileName; + BundlerConfig.OutputFileNames.push_back(OutputFilePath); + + OffloadBundler Bundler(BundlerConfig); + + // Execute unbundling + if (env::shouldEmitVerboseLogs()) { + LogS << "Extracting Bitcode Bundle:\n" + << "\t Bundle Entry ID: " << BundlerConfig.TargetNames[0] << "\n" + << "\t Input Filename: " << BundlerConfig.InputFileNames[0] + << "\n" + << "\t Output Filename: " << BundlerConfig.OutputFileNames[0] + << "\n"; + LogS << "\t Command: clang-offload-bundler -unbundle -type=bc" + " -targets=" + << BundleEntryId << " -input=" << InputFilePath + << " -output=" << OutputFilePath << "\n"; + LogS.flush(); + } + + llvm::Error Err = Bundler.UnbundleFiles(); + llvm::logAllUnhandledErrors(std::move(Err), llvm::errs(), + "UnbundleFiles error: "); + + // Read unbundled bitcode from file system in order to pass to linker + amd_comgr_data_t ResultT; + if (auto Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_BC, &ResultT)) + return Status; + + // ResultT can be released after addition to the data_set + ScopedDataObjectReleaser SDOR(ResultT); + + DataObject *Result = DataObject::convert(ResultT); + if (auto Status = inputFromFile(Result, StringRef(OutputFilePath))) + return Status; + + Result->Name = strdup(OutputFileName.c_str()); + + auto Mod = + getLazyIRModule(MemoryBuffer::getMemBuffer( + StringRef(Result->Data, Result->Size), "", false), + SMDiag, Context, true); + + if (!Mod) { + SMDiag.print(Result->Name, LogS, /* ShowColors */ false); + return AMD_COMGR_STATUS_ERROR; + } + if (verifyModule(*Mod, &LogS)) + return AMD_COMGR_STATUS_ERROR; + if (L.linkInModule(std::move(Mod), ApplicableFlags)) + return AMD_COMGR_STATUS_ERROR; + } + // Unbundle bitcode archive + else if (Input->DataKind == AMD_COMGR_DATA_KIND_AR_BUNDLE) { + if (env::shouldEmitVerboseLogs()) { + LogS << "\t Linking Archive: " << InputDir << path::get_separator() << Input->Name + << "\n"; + } + + // Determine desired bundle entry ID + // TODO: Move away from using ActionInfo->IsaName + // Use ActionInfo->BundleEntryIDs instead + if (!ActionInfo->IsaName) + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + + std::string IsaName = ActionInfo->IsaName; + size_t Index = IsaName.find("gfx"); + std::string BundleEntryId = + "hip-amdgcn-amd-amdhsa--gfx" + IsaName.substr(Index + 3); + + // Write data to file system so that Offload Bundler can process, assuming + // we didn't already write due to shouldSaveTemps() conditional above + // TODO: Switch write to VFS + if (!env::shouldSaveTemps()) { + if (auto Status = outputToFile(Input, getFilePath(Input, InputDir))) { + return Status; + } + } + + // Configure Offload Bundler + OffloadBundlerConfig BundlerConfig; + BundlerConfig.AllowMissingBundles = true; + BundlerConfig.FilesType = "a"; + BundlerConfig.HipOpenmpCompatible = 1; + BundlerConfig.AllowNoHost = 1; + + BundlerConfig.TargetNames.push_back(BundleEntryId); + std::string InputFilePath = getFilePath(Input, InputDir).str().str(); + BundlerConfig.InputFileNames.push_back(InputFilePath); + + // Generate prefix for output files + std::string OutputPrefix = std::string(Input->Name); + Index = OutputPrefix.find_last_of("."); + OutputPrefix = OutputPrefix.substr(0, Index); + + std::string OutputFileName = OutputPrefix + '-' + BundleEntryId + ".a"; + + // ISA name may contain ':', which is an invalid character in file names + // on Windows. Replace with '_' + std::replace(OutputFileName.begin(), OutputFileName.end(), ':', '_'); + + std::string OutputFilePath = OutputDir.str().str() + path::get_separator().str() + OutputFileName; + BundlerConfig.OutputFileNames.push_back(OutputFilePath); + + OffloadBundler Bundler(BundlerConfig); + + // Execute unbundling + if (env::shouldEmitVerboseLogs()) { + LogS << " Extracting Bitcode Archive:\n" + << "\t Bundle Entry ID: " << BundlerConfig.TargetNames[0] << "\n" + << "\t Input Filename: " << BundlerConfig.InputFileNames[0] + << "\n" + << "\t Output Filename: " << BundlerConfig.OutputFileNames[0] + << "\n"; + LogS << "\t Command: clang-offload-bundler -unbundle -type=a " + " -targets=" + << BundleEntryId << " -input=" << InputFilePath + << " -output=" << OutputFilePath << "\n"; + LogS.flush(); + } + llvm::Error Err = Bundler.UnbundleArchive(); + llvm::logAllUnhandledErrors(std::move(Err), llvm::errs(), + "UnbundleArchive error: "); + + // Read archive back into Comgr + amd_comgr_data_t ResultT; + if (auto Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_AR, &ResultT)) + return Status; + + // ResultT can be released after addition to the data_set + ScopedDataObjectReleaser SDOR(ResultT); + + DataObject *Result = DataObject::convert(ResultT); + if (auto Status = inputFromFile(Result, StringRef(OutputFilePath))) + return Status; + + // Get memory buffer for each bitcode in archive file + // Modeled after static loadArFile in llvm-link.cpp + std::string ArchiveName = "comgr.ar"; + llvm::StringRef ArchiveBuf = StringRef(Result->Data, Result->Size); + auto ArchiveOrError = + object::Archive::create(MemoryBufferRef(ArchiveBuf, ArchiveName)); + + if (!ArchiveOrError) { + llvm::logAllUnhandledErrors(ArchiveOrError.takeError(), llvm::errs(), + "Unpack Archives error: "); + return AMD_COMGR_STATUS_ERROR; + } + + auto Archive = std::move(ArchiveOrError.get()); + + Err = Error::success(); + for (const object::Archive::Child &C : Archive->children(Err)) { + + // Get child name + Expected Ename = C.getName(); + if (Error E = Ename.takeError()) { + errs() << ": "; + WithColor::error() << " failed to read name of archive member" + << ArchiveName << "'\n"; + return AMD_COMGR_STATUS_ERROR; + } + std::string ChildName = Ename.get().str(); + + // Get memory buffer + SMDiagnostic ParseErr; + Expected MemBuf = C.getMemoryBufferRef(); + if (Error E = MemBuf.takeError()) { + errs() << ": "; + WithColor::error() + << " loading memory for member '" + << "' of archive library failed'" << ArchiveName << "'\n"; + return AMD_COMGR_STATUS_ERROR; + }; + + // Link memory buffer into composite + auto Mod = getLazyIRModule(MemoryBuffer::getMemBuffer(MemBuf.get()), + SMDiag, Context, true); + + if (!Mod) { + SMDiag.print(ChildName.c_str(), LogS, /* ShowColors */ false); + return AMD_COMGR_STATUS_ERROR; + } + if (verifyModule(*Mod, &LogS)) + return AMD_COMGR_STATUS_ERROR; + if (L.linkInModule(std::move(Mod), ApplicableFlags)) + return AMD_COMGR_STATUS_ERROR; + } + + llvm::logAllUnhandledErrors(std::move(Err), llvm::errs(), + "Unpack Archives error: "); + } else + continue; + } + + if (verifyModule(*Composite, &LogS)) { + return AMD_COMGR_STATUS_ERROR; + } + + SmallString<0> OutBuf; + BitcodeWriter Writer(OutBuf); + Writer.writeModule(*Composite, false, nullptr, false, nullptr); + Writer.writeSymtab(); + Writer.writeStrtab(); + + amd_comgr_data_t OutputT; + if (auto Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_BC, &OutputT)) { + return Status; + } + + // OutputT can be released after addition to the data_set + ScopedDataObjectReleaser SDOR(OutputT); + + DataObject *Output = DataObject::convert(OutputT); + Output->setName("linked.bc"); + Output->setData(OutBuf); + + return amd_comgr_data_set_add(OutSetT, OutputT); +} + +amd_comgr_status_t AMDGPUCompiler::codeGenBitcodeToRelocatable() { + if (auto Status = createTmpDirs()) { + return Status; + } + + if (ActionInfo->IsaName) { + if (auto Status = addTargetIdentifierFlags(ActionInfo->IsaName)) { + return Status; + } + } + + if (ActionInfo->ShouldLinkDeviceLibs) { + if (auto Status = addDeviceLibraries()) { + return Status; + } + } + + Args.push_back("-c"); + + Args.push_back("-mllvm"); + Args.push_back("-amdgpu-internalize-symbols"); + + return processFiles(AMD_COMGR_DATA_KIND_RELOCATABLE, ".o"); +} + +amd_comgr_status_t AMDGPUCompiler::codeGenBitcodeToAssembly() { + if (auto Status = createTmpDirs()) { + return Status; + } + + if (ActionInfo->IsaName) { + if (auto Status = addTargetIdentifierFlags(ActionInfo->IsaName)) { + return Status; + } + } + + if (ActionInfo->ShouldLinkDeviceLibs) { + if (auto Status = addDeviceLibraries()) { + return Status; + } + } + + Args.push_back("-S"); + + return processFiles(AMD_COMGR_DATA_KIND_SOURCE, ".s"); +} + +amd_comgr_status_t AMDGPUCompiler::assembleToRelocatable() { + if (auto Status = createTmpDirs()) { + return Status; + } + + if (ActionInfo->IsaName) { + if (auto Status = addTargetIdentifierFlags(ActionInfo->IsaName)) { + return Status; + } + } + + if (auto Status = addIncludeFlags()) { + return Status; + } + + if (ActionInfo->ShouldLinkDeviceLibs) { + if (auto Status = addDeviceLibraries()) { + return Status; + } + } + + Args.push_back("-c"); + Args.push_back("-x"); + Args.push_back("assembler"); + + // -nogpulib option not needed for assembling to relocatable + NoGpuLib = false; + + return processFiles(AMD_COMGR_DATA_KIND_RELOCATABLE, ".o"); +} + +amd_comgr_status_t AMDGPUCompiler::linkToRelocatable() { + if (auto Status = createTmpDirs()) { + return Status; + } + + for (auto &Option : ActionInfo->getOptions()) { + Args.push_back(Option.c_str()); + } + + SmallVector, 128> Inputs; + for (auto *Input : InSet->DataObjects) { + if (Input->DataKind != AMD_COMGR_DATA_KIND_RELOCATABLE) { + continue; + } + + Inputs.push_back(getFilePath(Input, InputDir)); + if (auto Status = outputToFile(Input, Inputs.back())) { + return Status; + } + Args.push_back(Inputs.back().c_str()); + } + + amd_comgr_data_t OutputT; + if (auto Status = + amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &OutputT)) { + return Status; + } + + // OutputT can be released after addition to the data_set + ScopedDataObjectReleaser SDOR(OutputT); + + DataObject *Output = DataObject::convert(OutputT); + Output->setName("a.o"); + auto OutputFilePath = getFilePath(Output, OutputDir); + Args.push_back("-o"); + Args.push_back(OutputFilePath.c_str()); + + Args.push_back("-r"); + + if (auto Status = linkWithLLD(Args, LogS, LogS)) { + return Status; + } + + if (auto Status = inputFromFile(Output, OutputFilePath)) { + return Status; + } + + return amd_comgr_data_set_add(OutSetT, OutputT); +} + +amd_comgr_status_t AMDGPUCompiler::linkToExecutable() { + if (auto Status = createTmpDirs()) { + return Status; + } + + if (ActionInfo->IsaName) { + if (auto Status = addTargetIdentifierFlags(ActionInfo->IsaName)) { + return Status; + } + } + + for (auto &Option : ActionInfo->getOptions()) { + Args.push_back(Option.c_str()); + } + + SmallVector, 128> Inputs; + for (auto *Input : InSet->DataObjects) { + if (Input->DataKind != AMD_COMGR_DATA_KIND_RELOCATABLE) { + continue; + } + + Inputs.push_back(getFilePath(Input, InputDir)); + if (auto Status = outputToFile(Input, Inputs.back())) { + return Status; + } + Args.push_back(Inputs.back().c_str()); + } + + if (ActionInfo->ShouldLinkDeviceLibs) { + if (auto Status = addDeviceLibraries()) { + return Status; + } + } + + amd_comgr_data_t OutputT; + if (auto Status = + amd_comgr_create_data(AMD_COMGR_DATA_KIND_EXECUTABLE, &OutputT)) { + return Status; + } + // OutputT can be released after addition to the data_set + ScopedDataObjectReleaser SDOR(OutputT); + + DataObject *Output = DataObject::convert(OutputT); + Output->setName("a.so"); + auto OutputFilePath = getFilePath(Output, OutputDir); + Args.push_back("-o"); + Args.push_back(OutputFilePath.c_str()); + + if (auto Status = executeInProcessDriver(Args)) { + return Status; + } + + if (auto Status = inputFromFile(Output, OutputFilePath)) { + return Status; + } + + return amd_comgr_data_set_add(OutSetT, OutputT); +} + +// TODO: Generalize this list to include all -cc1 flags and arguments that are +// still valid in a bitcode compilation context +static inline const std::unordered_set ValidSpirvFlags{ + "-fapprox-func", + "-fcolor-diagnostics", + "-fconvergent-functions", + "-fexceptions", + "-ffast-math", + "-ffinite-math-only", + "-ffp-contract=fast", + "-ffp-contract=fast-honor-pragmas", + "-ffp-contract=on", + "-fgpu-rdc", + "-finline-functions", + "-fno-autolink", + "-fno-experimental-relative-c++-abi-vtables", + "-fno-rounding-math", + "-fno-signed-zeros", + "-fno-threadsafe-statics", + "-freciprocal-math", + "-funsafe-math-optimizations", + "-fvisibility=hidden", + "-O0", + "-O1", + "-O2", + "-O3", + "--save-temps"}; + +amd_comgr_status_t AMDGPUCompiler::extractSpirvFlags(DataSet *BcSet) { + + for (auto *Bc : BcSet->DataObjects) { + // Create SPIR-V IR Module from Bitcode Buffer + SMDiagnostic SMDiag; + LLVMContext Context; + Context.setDiagnosticHandler( + std::make_unique(this->LogS), true); + + auto Mod = getLazyIRModule( + MemoryBuffer::getMemBuffer(StringRef(Bc->Data, Bc->Size), "", false), + SMDiag, Context, true); + + if (!Mod) { + SMDiag.print("SPIR-V Bitcode", LogS, /* ShowColors */ false); + return AMD_COMGR_STATUS_ERROR; + } + + if (verifyModule(*Mod, &LogS)) + return AMD_COMGR_STATUS_ERROR; + + // Fetch @llvm.cmdline + GlobalVariable *CmdLine = Mod->getNamedGlobal("llvm.cmdline"); + + // Return if no @llvm.cmdline + if (!CmdLine) + return AMD_COMGR_STATUS_SUCCESS; + + if (ConstantDataSequential *CDS = + dyn_cast(CmdLine->getInitializer())) { + + // Add each valid null-terminated '\0' string to Flags + std::string Tmp; + StringRef CmdLineRaw = CDS->getRawDataValues(); + std::stringstream ss(CmdLineRaw.str()); + while (getline(ss, Tmp, '\0')) { + if (Tmp == "--hipstdpar" || Tmp == "-amdgpu-enable-hipstdpar") { + Bc->SpirvFlags.push_back("-mllvm"); + Bc->SpirvFlags.push_back("-amdgpu-enable-hipstdpar"); + } else if (Tmp == "-amdgpu-spill-cfi-saved-regs") { + Bc->SpirvFlags.push_back("-mllvm"); + Bc->SpirvFlags.push_back("-amdgpu-spill-cfi-saved-regs"); + } else if (ValidSpirvFlags.count(Tmp)) { + Bc->SpirvFlags.push_back(Saver.save(Tmp.c_str()).data()); + } + } + } + + // COV5 required for SPIR-V + Bc->SpirvFlags.push_back("-mcode-object-version=5"); + + if (env::shouldEmitVerboseLogs()) { + LogS << " SPIR-V Flags: " << Bc->Name << "\n"; + for (auto Flag : Bc->SpirvFlags) + LogS << " " << Flag << "\n"; + } + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMDGPUCompiler::translateSpirvToBitcode() { + return translateSpirvToBitcodeImpl(InSet, DataSet::convert(OutSetT)); +} + +amd_comgr_status_t +AMDGPUCompiler::translateSpirvToBitcodeImpl(DataSet *SpirvInSet, + DataSet *BcOutSet) { +#ifdef COMGR_DISABLE_SPIRV + LogS << "Calling AMDGPUCompiler::translateSpirvToBitcodeImpl() not " + << "supported. Comgr is built with -DCOMGR_DISABLE_SPIRV. Re-build LLVM " + << "and Comgr with LLVM-SPIRV-Translator support to continue.\n"; + return AMD_COMGR_STATUS_ERROR; +#else + if (auto Status = createTmpDirs()) { + return Status; + } + + auto Cache = CommandCache::get(LogS); + + for (auto *Input : SpirvInSet->DataObjects) { + + if (env::shouldSaveTemps()) { + if (auto Status = outputToFile(Input, getFilePath(Input, InputDir))) { + return Status; + } + } + + if (Input->DataKind != AMD_COMGR_DATA_KIND_SPIRV) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + SmallString<0> OutBuf; + SPIRVCommand SPIRV(Input, OutBuf); + + amd_comgr_status_t Status; + if (!Cache) { + Status = SPIRV.execute(LogS); + } else { + Status = Cache->execute(SPIRV, LogS); + } + + if (Status) { + return Status; + } + + amd_comgr_data_t OutputT; + if (auto Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_BC, &OutputT)) { + return Status; + } + + // OutputT can be released after addition to the data_set + ScopedDataObjectReleaser SDOR(OutputT); + + DataObject *Output = DataObject::convert(OutputT); + Output->setName(std::string(Input->Name) + std::string(".bc")); + Output->setData(OutBuf); + + if (auto Status = + amd_comgr_data_set_add(DataSet::convert(BcOutSet), OutputT)) { + return Status; + } + + if (env::shouldEmitVerboseLogs()) { + LogS << "SPIR-V Translation: amd-llvm-spirv -r --spirv-target-env=CL2.0 " + << getFilePath(Input, InputDir) << " " + << getFilePath(Output, OutputDir) << " (command line equivalent)\n"; + } + + if (env::shouldSaveTemps()) { + if (auto Status = outputToFile(Output, getFilePath(Output, OutputDir))) { + return Status; + } + } + } + + return AMD_COMGR_STATUS_SUCCESS; +#endif +} + +amd_comgr_status_t AMDGPUCompiler::compileSpirvToRelocatable() { + if (auto Status = createTmpDirs()) { + return Status; + } + + for (auto *Input : InSet->DataObjects) { + if (Input->DataKind != AMD_COMGR_DATA_KIND_SPIRV) + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + // Translate .spv to .bc + amd_comgr_data_set_t TranslatedSpirvT; + if (auto Status = amd_comgr_create_data_set(&TranslatedSpirvT)) + return Status; + DataSet *TranslatedSpirv = DataSet::convert(TranslatedSpirvT); + + if (auto Status = translateSpirvToBitcodeImpl(InSet, TranslatedSpirv)) + return Status; + + // Extract relevant -cc1 flags from @llvm.cmdline + if (auto Status = extractSpirvFlags(TranslatedSpirv)) + return Status; + + // Compile bitcode to relocatable + if (ActionInfo->IsaName) { + if (auto Status = addTargetIdentifierFlags(ActionInfo->IsaName)) { + return Status; + } + } + + if (ActionInfo->ShouldLinkDeviceLibs) { + if (auto Status = addDeviceLibraries()) { + return Status; + } + } + + Args.push_back("-c"); + + Args.push_back("-mllvm"); + Args.push_back("-amdgpu-internalize-symbols"); + + return processFiles(AMD_COMGR_DATA_KIND_RELOCATABLE, ".o", TranslatedSpirv); +} + +AMDGPUCompiler::AMDGPUCompiler(DataAction *ActionInfo, DataSet *InSet, + DataSet *OutSet, raw_ostream &LogS) + : ActionInfo(ActionInfo), InSet(InSet), OutSetT(DataSet::convert(OutSet)), + LogS(LogS) { + initializeCommandLineArgs(Args); + + // Initialize OverlayFS with the real file system which helps redirect + // non-VFS reads and writes. + OverlayFS = new vfs::OverlayFileSystem(vfs::getRealFileSystem()); + + std::optional VFSStatus = env::shouldUseVFS(); + if ((VFSStatus.has_value() && *VFSStatus) || + (!VFSStatus.has_value() && ActionInfo->ShouldUseVFS)) { + if (env::shouldEmitVerboseLogs()) { + LogS << " File System: VFS\n"; + } + UseVFS = true; + InMemoryFS = new vfs::InMemoryFileSystem; + OverlayFS->pushOverlay(InMemoryFS); + } else { + if (env::shouldEmitVerboseLogs()) { + LogS << " File System: Real\n"; + } + } +} + +AMDGPUCompiler::~AMDGPUCompiler() { + if (!env::shouldSaveTemps()) { + removeTmpDirs(); + } +} + +} // namespace COMGR diff --git a/amd/comgr/src/comgr-compiler.h b/amd/comgr/src/comgr-compiler.h new file mode 100644 index 0000000000000..455a179c85050 --- /dev/null +++ b/amd/comgr/src/comgr-compiler.h @@ -0,0 +1,89 @@ +//===- comgr-compiler.h - Comgr compiler Action internals -----------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_COMPILER_H +#define COMGR_COMPILER_H + +#include "comgr.h" +#include "clang/Driver/Driver.h" +#include "llvm/Support/VirtualFileSystem.h" + +namespace COMGR { + +/// Manages executing Compiler-related actions. +/// +/// @warning No more than one public method should be called on a constructed +/// object before it is destructed. +class AMDGPUCompiler { + DataAction *ActionInfo; + DataSet *InSet; + amd_comgr_data_set_t OutSetT; + /// Precompiled header file paths. + llvm::SmallVector, 2> PrecompiledHeaders; + /// Arguments common to all driver invocations in the current action. + llvm::SmallVector Args; + llvm::SmallString<128> TmpDir; + llvm::SmallString<128> InputDir; + llvm::SmallString<128> OutputDir; + llvm::SmallString<128> IncludeDir; + llvm::raw_ostream &LogS; + /// Storage for other dynamic strings we need to include in Argv. + llvm::BumpPtrAllocator Allocator; + llvm::StringSaver Saver = Allocator; + /// Whether we need to disable Clang's device-lib linking. + bool NoGpuLib = true; + bool UseVFS = false; + + llvm::IntrusiveRefCntPtr OverlayFS; + llvm::IntrusiveRefCntPtr InMemoryFS; + + amd_comgr_status_t createTmpDirs(); + amd_comgr_status_t removeTmpDirs(); + amd_comgr_status_t processFile(DataObject *Input, const char *InputFilePath, + const char *OutputFilePath); + /// Process each file in @c InSet individually, placing output in @c OutSet. + amd_comgr_status_t processFiles(amd_comgr_data_kind_t OutputKind, + const char *OutputSuffix); + amd_comgr_status_t processFiles(amd_comgr_data_kind_t OutputKind, + const char *OutputSuffix, DataSet *InSet); + amd_comgr_status_t addIncludeFlags(); + amd_comgr_status_t addTargetIdentifierFlags(llvm::StringRef IdentStr, + bool CompilingSrc); + amd_comgr_status_t addCompilationFlags(); + amd_comgr_status_t addDeviceLibraries(); + amd_comgr_status_t extractSpirvFlags(DataSet *BcSet); + + amd_comgr_status_t executeInProcessDriver(llvm::ArrayRef Args); + + amd_comgr_status_t translateSpirvToBitcodeImpl(DataSet *SpirvInSet, + DataSet *BcOutSet); + +public: + AMDGPUCompiler(DataAction *ActionInfo, DataSet *InSet, DataSet *OutSet, + llvm::raw_ostream &LogS); + ~AMDGPUCompiler(); + + amd_comgr_status_t preprocessToSource(); + amd_comgr_status_t compileToBitcode(bool WithDeviceLibs = false); + amd_comgr_status_t compileToRelocatable(); + amd_comgr_status_t unbundle(); + amd_comgr_status_t linkBitcodeToBitcode(); + amd_comgr_status_t codeGenBitcodeToRelocatable(); + amd_comgr_status_t codeGenBitcodeToAssembly(); + amd_comgr_status_t assembleToRelocatable(); + amd_comgr_status_t linkToRelocatable(); + amd_comgr_status_t linkToExecutable(); + amd_comgr_status_t compileToExecutable(); + amd_comgr_status_t compileSpirvToRelocatable(); + amd_comgr_status_t translateSpirvToBitcode(); + + amd_comgr_language_t getLanguage() const { return ActionInfo->Language; } +}; +} // namespace COMGR + +#endif diff --git a/amd/comgr/src/comgr-device-libs.cpp b/amd/comgr/src/comgr-device-libs.cpp new file mode 100644 index 0000000000000..007f6c70752d6 --- /dev/null +++ b/amd/comgr/src/comgr-device-libs.cpp @@ -0,0 +1,54 @@ +//===- comgr-device-libs.cpp - Handle AMD Device Libraries ----------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the handling of the AMD Device Libraries, which are +/// LLVM IR objects embedded into Comgr via header files. +/// +/// We also handle OpenCL pre-compiled headers, which are similarly embedded in +/// Comgr. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-device-libs.h" +#include "comgr.h" +#include "llvm/ADT/StringSwitch.h" +#include + +using namespace llvm; + +namespace COMGR { + +namespace { +#include "libraries.inc" +#include "libraries_sha.inc" +#include "opencl-c-base.inc" +} // namespace + +ArrayRef getDeviceLibrariesIdentifier() { + return DEVICE_LIBS_ID; +} + +StringRef getOpenCLCBaseHeaderContents() { + return StringRef(reinterpret_cast(opencl_c_base), + opencl_c_base_size); +} + +llvm::ArrayRef> +getDeviceLibraries() { + static std::tuple DeviceLibs[] = { +#define AMD_DEVICE_LIBS_TARGET(target) \ + {#target ".bc", \ + llvm::StringRef(reinterpret_cast(target##_lib), \ + target##_lib_size)}, +#include "libraries_defs.inc" + }; + return DeviceLibs; +} + +} // namespace COMGR diff --git a/amd/comgr/src/comgr-device-libs.h b/amd/comgr/src/comgr-device-libs.h new file mode 100644 index 0000000000000..c24d1ab5069c5 --- /dev/null +++ b/amd/comgr/src/comgr-device-libs.h @@ -0,0 +1,28 @@ +//===- comgr-device-libs.h - Handle AMD Device Libraries ------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_DEVICE_LIBS_H +#define COMGR_DEVICE_LIBS_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/StringRef.h" +#include + +namespace COMGR { + +struct DataAction; +struct DataSet; + +llvm::ArrayRef getDeviceLibrariesIdentifier(); +llvm::StringRef getOpenCLCBaseHeaderContents(); +llvm::ArrayRef> +getDeviceLibraries(); + +} // namespace COMGR + +#endif // COMGR_DEVICE_LIBS_H diff --git a/amd/comgr/src/comgr-diagnostic-handler.cpp b/amd/comgr/src/comgr-diagnostic-handler.cpp new file mode 100644 index 0000000000000..892bf73cb04b2 --- /dev/null +++ b/amd/comgr/src/comgr-diagnostic-handler.cpp @@ -0,0 +1,47 @@ +//===- comgr-diagnostic-handler.cpp - Handle LLVM diagnostics -------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the handling of LLVM diagnonstics, which are generated +/// during LLVM API interactions. We forward these to the Comgr Log to aid in +/// debugging. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-diagnostic-handler.h" + +#include "llvm/IR/DiagnosticPrinter.h" + +namespace COMGR { +using namespace llvm; +bool AMDGPUCompilerDiagnosticHandler::handleDiagnostics( + const DiagnosticInfo &DI) { + unsigned Severity = DI.getSeverity(); + switch (Severity) { + case DS_Error: + LogS << "ERROR: "; + break; + case DS_Warning: + LogS << "WARNING: "; + break; + case DS_Remark: + LogS << "REMARK: "; + break; + case DS_Note: + LogS << "NOTE: "; + break; + default: + LogS << "(Unknown DiagnosticInfo Severity): "; + break; + } + DiagnosticPrinterRawOStream DP(LogS); + DI.print(DP); + LogS << "\n"; + return true; +} +} // namespace COMGR diff --git a/amd/comgr/src/comgr-diagnostic-handler.h b/amd/comgr/src/comgr-diagnostic-handler.h new file mode 100644 index 0000000000000..339d980181109 --- /dev/null +++ b/amd/comgr/src/comgr-diagnostic-handler.h @@ -0,0 +1,24 @@ +//===- comgr-diagnostic-handler.h - Handle LLVM diagnostics ---------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_DIAGNOSTIC_HANDLER_H +#define COMGR_DIAGNOSTIC_HANDLER_H + +#include + +namespace COMGR { +struct AMDGPUCompilerDiagnosticHandler : public llvm::DiagnosticHandler { + llvm::raw_ostream &LogS; + + AMDGPUCompilerDiagnosticHandler(llvm::raw_ostream &LogS) : LogS(LogS) {} + + bool handleDiagnostics(const llvm::DiagnosticInfo &DI) override; +}; +} // namespace COMGR + +#endif diff --git a/amd/comgr/src/comgr-disassembly.cpp b/amd/comgr/src/comgr-disassembly.cpp new file mode 100644 index 0000000000000..f2173164644e7 --- /dev/null +++ b/amd/comgr/src/comgr-disassembly.cpp @@ -0,0 +1,146 @@ +//===- comgr-disassembly.cpp - Disassemble instruction --------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the internals for the amd_comgr_create_disassembly_info +/// and amd_comgr_disassemble_instruction APIs. They leverage the LLVM MC +/// (Machine Code Playground) implementation to disassemble individual +/// instructions. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-disassembly.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/MC/TargetRegistry.h" + +using namespace llvm; +using namespace COMGR; + +amd_comgr_status_t +DisassemblyInfo::create(const TargetIdentifier &Ident, + ReadMemoryCallback ReadMemory, + PrintInstructionCallback PrintInstruction, + PrintAddressAnnotationCallback PrintAddressAnnotation, + amd_comgr_disassembly_info_t *DisassemblyInfoT) { + std::string TT = (Twine(Ident.Arch) + "-" + Ident.Vendor + "-" + Ident.OS + + "-" + Ident.Environ) + .str(); + std::string Isa = TT + Twine("-" + Ident.Processor).str(); + SmallVector FeaturesVec; + + for (auto &Feature : Ident.Features) { + FeaturesVec.push_back( + Twine(Feature.take_back() + Feature.drop_back()).str()); + } + + std::string Features = join(FeaturesVec, ","); + + std::string Error; + llvm::Triple TheTriple(TT); + const Target *TheTarget = TargetRegistry::lookupTarget(TheTriple, Error); + if (!TheTarget) { + return AMD_COMGR_STATUS_ERROR; + } + + std::unique_ptr + MRI(TheTarget->createMCRegInfo(TheTriple)); + if (!MRI) { + return AMD_COMGR_STATUS_ERROR; + } + + llvm::MCTargetOptions MCOptions; + std::unique_ptr MAI( + TheTarget->createMCAsmInfo(*MRI, TheTriple, MCOptions)); + if (!MAI) { + return AMD_COMGR_STATUS_ERROR; + } + + std::unique_ptr MII(TheTarget->createMCInstrInfo()); + if (!MII) { + return AMD_COMGR_STATUS_ERROR; + } + + std::unique_ptr STI( + TheTarget->createMCSubtargetInfo(TheTriple, Ident.Processor, Features)); + if (!STI) { + return AMD_COMGR_STATUS_ERROR; + } + + std::unique_ptr Ctx(new (std::nothrow) MCContext( + Triple(TT), MAI.get(), MRI.get(), STI.get())); + if (!Ctx) { + return AMD_COMGR_STATUS_ERROR; + } + + std::unique_ptr DisAsm( + TheTarget->createMCDisassembler(*STI, *Ctx)); + if (!DisAsm) { + return AMD_COMGR_STATUS_ERROR; + } + + // Optional; currently AMDGPU does not implement this. + std::unique_ptr MIA( + TheTarget->createMCInstrAnalysis(MII.get())); + + std::unique_ptr IP(TheTarget->createMCInstPrinter( + Triple(TT), MAI->getAssemblerDialect(), *MAI, *MII, *MRI)); + if (!IP) { + return AMD_COMGR_STATUS_ERROR; + } + + DisassemblyInfo *DI = new (std::nothrow) DisassemblyInfo( + ReadMemory, PrintInstruction, PrintAddressAnnotation, TheTarget, + std::move(MAI), std::move(MRI), std::move(STI), std::move(MII), + std::move(Ctx), std::move(DisAsm), std::move(MIA), std::move(IP)); + if (!DI) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + *DisassemblyInfoT = DisassemblyInfo::convert(DI); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t DisassemblyInfo::disassembleInstruction(uint64_t Address, + void *UserData, + uint64_t &Size) { + uint64_t ReadSize = MAI->getMaxInstLength(); + SmallVector Buffer(ReadSize); + + uint64_t ActualSize = ReadMemory( + Address, reinterpret_cast(Buffer.data()), ReadSize, UserData); + if (!ActualSize || ActualSize > ReadSize) { + return AMD_COMGR_STATUS_ERROR; + } + + Buffer.resize(ActualSize); + + MCInst Inst; + std::string Annotations; + raw_string_ostream AnnotationsStream(Annotations); + if (DisAsm->getInstruction(Inst, Size, Buffer, Address, AnnotationsStream) != + MCDisassembler::Success) { + return AMD_COMGR_STATUS_ERROR; + } + + std::string InstStr; + raw_string_ostream InstStream(InstStr); + IP->printInst(&Inst, Address, AnnotationsStream.str(), *STI, InstStream); + + PrintInstruction(InstStream.str().c_str(), UserData); + + if (MIA && (MIA->isCall(Inst) || MIA->isUnconditionalBranch(Inst) || + MIA->isConditionalBranch(Inst))) { + uint64_t Target; + if (MIA->evaluateBranch(Inst, Address, Size, Target)) { + PrintAddressAnnotation(Target, UserData); + } + } + + return AMD_COMGR_STATUS_SUCCESS; +} diff --git a/amd/comgr/src/comgr-disassembly.h b/amd/comgr/src/comgr-disassembly.h new file mode 100644 index 0000000000000..299f5a46f8d70 --- /dev/null +++ b/amd/comgr/src/comgr-disassembly.h @@ -0,0 +1,94 @@ +//===- comgr-disassembly.h - Disassemble instruction ----------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_DISASSEMBLY_H +#define COMGR_DISASSEMBLY_H + +#include "comgr.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrAnalysis.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" + +namespace llvm { +class Target; +} // namespace llvm + +namespace COMGR { + +typedef uint64_t (*ReadMemoryCallback)(uint64_t, char *, uint64_t, void *); +typedef void (*PrintInstructionCallback)(const char *, void *); +typedef void (*PrintAddressAnnotationCallback)(uint64_t, void *); + +struct DisassemblyInfo { + DisassemblyInfo(ReadMemoryCallback ReadMemory, + PrintInstructionCallback PrintInstruction, + PrintAddressAnnotationCallback PrintAddressAnnotation, + const llvm::Target *TheTarget, + std::unique_ptr &&MAI, + std::unique_ptr &&MRI, + std::unique_ptr &&STI, + std::unique_ptr &&MII, + std::unique_ptr &&Ctx, + std::unique_ptr &&DisAsm, + std::unique_ptr &&MIA, + std::unique_ptr &&IP) + : ReadMemory(ReadMemory), PrintInstruction(PrintInstruction), + PrintAddressAnnotation(PrintAddressAnnotation), TheTarget(TheTarget), + MAI(std::move(MAI)), MRI(std::move(MRI)), STI(std::move(STI)), + MII(std::move(MII)), Ctx(std::move(Ctx)), DisAsm(std::move(DisAsm)), + MIA(std::move(MIA)), IP(std::move(IP)) {} + + static amd_comgr_disassembly_info_t convert(DisassemblyInfo *DisasmInfo) { + amd_comgr_disassembly_info_t Handle = { + static_cast(reinterpret_cast(DisasmInfo))}; + return Handle; + } + + static const amd_comgr_disassembly_info_t + convert(const DisassemblyInfo *DisasmInfo) { + const amd_comgr_disassembly_info_t Handle = { + static_cast(reinterpret_cast(DisasmInfo))}; + return Handle; + } + + static DisassemblyInfo *convert(amd_comgr_disassembly_info_t DisasmInfo) { + return reinterpret_cast(DisasmInfo.handle); + } + + static amd_comgr_status_t + create(const TargetIdentifier &Ident, ReadMemoryCallback ReadMemory, + PrintInstructionCallback PrintInstruction, + PrintAddressAnnotationCallback PrintAddressAnnotation, + amd_comgr_disassembly_info_t *DisassemblyInfoT); + + amd_comgr_status_t disassembleInstruction(uint64_t Address, void *UserData, + uint64_t &Size); + + ReadMemoryCallback ReadMemory; + PrintInstructionCallback PrintInstruction; + PrintAddressAnnotationCallback PrintAddressAnnotation; + const llvm::Target *TheTarget; + std::unique_ptr MAI; + std::unique_ptr MRI; + std::unique_ptr STI; + std::unique_ptr MII; + std::unique_ptr Ctx; + std::unique_ptr DisAsm; + std::unique_ptr MIA; + std::unique_ptr IP; +}; + +} // namespace COMGR + +#endif // COMGR_DISASSEMBLY_H diff --git a/amd/comgr/src/comgr-env.cpp b/amd/comgr/src/comgr-env.cpp new file mode 100644 index 0000000000000..76f439bd43802 --- /dev/null +++ b/amd/comgr/src/comgr-env.cpp @@ -0,0 +1,102 @@ +//===- comgr-env.cpp - Comgr environment variables ------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the management of Comgr's environment variables. See +/// amd/comgr/README.md for descriptions of these. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-env.h" +#include "llvm/ADT/Twine.h" +#include "llvm/Support/VirtualFileSystem.h" + +using namespace llvm; + +namespace COMGR { +namespace env { + +bool shouldSaveTemps() { + static char *SaveTemps = getenv("AMD_COMGR_SAVE_TEMPS"); + return SaveTemps && StringRef(SaveTemps) != "0"; +} + +bool shouldSaveLLVMTemps() { + static char *SaveTemps = getenv("AMD_COMGR_SAVE_LLVM_TEMPS"); + return SaveTemps && StringRef(SaveTemps) != "0"; +} + +std::optional shouldUseVFS() { + if (shouldSaveTemps()) + return false; + + static char *UseVFS = getenv("AMD_COMGR_USE_VFS"); + if (UseVFS) { + if (StringRef(UseVFS) == "0") + return false; + else if (StringRef(UseVFS) == "1") + return true; + } + + return std::nullopt; +} + +std::optional getRedirectLogs() { + static char *RedirectLogs = getenv("AMD_COMGR_REDIRECT_LOGS"); + if (!RedirectLogs || StringRef(RedirectLogs) == "0") { + return std::nullopt; + } + return StringRef(RedirectLogs); +} + +bool needTimeStatistics() { + static char *TimeStatistics = getenv("AMD_COMGR_TIME_STATISTICS"); + return TimeStatistics && StringRef(TimeStatistics) != "0"; +} + +bool shouldEmitVerboseLogs() { + static char *VerboseLogs = getenv("AMD_COMGR_EMIT_VERBOSE_LOGS"); + return VerboseLogs && StringRef(VerboseLogs) != "0"; +} + +llvm::StringRef getLLVMPath() { + static const char *EnvLLVMPath = std::getenv("LLVM_PATH"); + return EnvLLVMPath; +} + +StringRef getCachePolicy() { + static const char *EnvCachePolicy = std::getenv("AMD_COMGR_CACHE_POLICY"); + return EnvCachePolicy; +} + +StringRef getCacheDirectory() { + // By default the cache is enabled + static const char *Enable = std::getenv("AMD_COMGR_CACHE"); + bool CacheDisabled = StringRef(Enable) == "0"; + if (CacheDisabled) + return ""; + + StringRef EnvCacheDirectory = std::getenv("AMD_COMGR_CACHE_DIR"); + if (!EnvCacheDirectory.empty()) + return EnvCacheDirectory; + + // mark Result as static to keep it cached across calls + static SmallString<256> Result; + if (!Result.empty()) + return Result; + + if (sys::path::cache_directory(Result)) { + sys::path::append(Result, "comgr"); + return Result; + } + + return ""; +} + +} // namespace env +} // namespace COMGR diff --git a/amd/comgr/src/comgr-env.h b/amd/comgr/src/comgr-env.h new file mode 100644 index 0000000000000..b13ca6aa30b91 --- /dev/null +++ b/amd/comgr/src/comgr-env.h @@ -0,0 +1,48 @@ +//===- comgr-env.h - Comgr environment variables --------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_ENV_H +#define COMGR_ENV_H + +#include "llvm/ADT/StringRef.h" + +namespace COMGR { +namespace env { + +/// Return whether the environment requests temps be saved. +bool shouldSaveTemps(); +bool shouldSaveLLVMTemps(); +std::optional shouldUseVFS(); + +/// If the environment requests logs be redirected, return the string identifier +/// of where to redirect. Otherwise return @p None. +std::optional getRedirectLogs(); + +/// Return whether the environment requests verbose logging. +bool shouldEmitVerboseLogs(); + +/// Return whether the environment requests time statistics collection. +bool needTimeStatistics(); + +/// If environment variable LLVM_PATH is set, return the environment variable, +/// otherwise return the default LLVM path. +llvm::StringRef getLLVMPath(); + +/// If environment variable AMD_COMGR_CACHE_POLICY is set, return the +/// environment variable, otherwise return empty +llvm::StringRef getCachePolicy(); + +/// If environment variable AMD_COMGR_CACHE_DIR is set, return the environment +/// variable, otherwise return the default path: On Linux it's typically +/// $HOME/.cache/comgr_cache (depends on XDG_CACHE_HOME) +llvm::StringRef getCacheDirectory(); + +} // namespace env +} // namespace COMGR + +#endif // COMGR_ENV_H diff --git a/amd/comgr/src/comgr-isa-metadata.def b/amd/comgr/src/comgr-isa-metadata.def new file mode 100644 index 0000000000000..16a52f84fa8d2 --- /dev/null +++ b/amd/comgr/src/comgr-isa-metadata.def @@ -0,0 +1,83 @@ +//===- comgr-isa-metadata.def - ISA metadata ------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the HANDLE_ISA macro, which is effectively a table +// with information on ISA features and properties for different AMDGPU +// architectures. +// +//===----------------------------------------------------------------------===// + +#if !(defined HANDLE_ISA) +#error "Missing macro definition of HANDLE_ISA" +#endif + +/* +#define HANDLE_ISA(TARGET_TRIPLE, PROCESSOR, \ + SRAMECC_SUPPORTED, XNACK_SUPPORTED, \ + ELF_MACHINE, TRAP_HANDLER_ENABLED, IMAGE_SUPPORT, \ + LDS_BANK_COUNT, LDS_SIZE, \ + EUS_PER_CU, MAX_WAVES_PER_CU, MAX_FLAT_WORK_GROUP_SIZE, \ + SGPR_ALLOC_GRANULE, TOTAL_NUM_SGPRS, ADDRESSABLE_NUM_SGPRS, \ + VGPR_ALLOC_GRANULE, TOTAL_NUM_VGPRS, ADDRESSABLE_NUM_VGPRS) \ + + ---LDS--- ----CU--- WG ------SGPR----- ------VGPR----- + TARGET_TRIPLE PROCESSOR SRAMECC XNACK ELF_MACHINE TRAP IMAGE Size Bnks EUs Waves Max Alloc Max Addr Alloc Max Addr */ +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx600", false, false, EF_AMDGPU_MACH_AMDGCN_GFX600, true, true, 65536, 32, 4, 40, 1024, 8, 512, 104, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx601", false, false, EF_AMDGPU_MACH_AMDGCN_GFX601, true, true, 65536, 32, 4, 40, 1024, 8, 512, 104, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx602", false, false, EF_AMDGPU_MACH_AMDGCN_GFX602, true, true, 65536, 32, 4, 40, 1024, 8, 512, 104, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx700", false, false, EF_AMDGPU_MACH_AMDGCN_GFX700, true, true, 65536, 32, 4, 40, 1024, 8, 512, 104, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx701", false, false, EF_AMDGPU_MACH_AMDGCN_GFX701, true, true, 65536, 32, 4, 40, 1024, 8, 512, 104, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx702", false, false, EF_AMDGPU_MACH_AMDGCN_GFX702, true, true, 65536, 16, 4, 40, 1024, 8, 512, 104, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx703", false, false, EF_AMDGPU_MACH_AMDGCN_GFX703, true, true, 65536, 16, 4, 40, 1024, 8, 512, 104, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx704", false, false, EF_AMDGPU_MACH_AMDGCN_GFX704, true, true, 65536, 16, 4, 40, 1024, 8, 512, 104, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx705", false, false, EF_AMDGPU_MACH_AMDGCN_GFX705, true, true, 65536, 16, 4, 40, 1024, 8, 512, 104, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx801", false, true, EF_AMDGPU_MACH_AMDGCN_GFX801, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx802", false, false, EF_AMDGPU_MACH_AMDGCN_GFX802, true, true, 65536, 32, 4, 40, 1024, 16, 800, 96, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx803", false, false, EF_AMDGPU_MACH_AMDGCN_GFX803, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx805", false, false, EF_AMDGPU_MACH_AMDGCN_GFX805, true, true, 65536, 32, 4, 40, 1024, 16, 800, 96, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx810", false, true, EF_AMDGPU_MACH_AMDGCN_GFX810, true, true, 65536, 16, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx900", false, true, EF_AMDGPU_MACH_AMDGCN_GFX900, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx902", false, true, EF_AMDGPU_MACH_AMDGCN_GFX902, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx904", false, true, EF_AMDGPU_MACH_AMDGCN_GFX904, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx906", true, true, EF_AMDGPU_MACH_AMDGCN_GFX906, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx908", true, true, EF_AMDGPU_MACH_AMDGCN_GFX908, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx909", false, true, EF_AMDGPU_MACH_AMDGCN_GFX909, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx90a", true, true, EF_AMDGPU_MACH_AMDGCN_GFX90A, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 8, 512, 512) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx90c", false, true, EF_AMDGPU_MACH_AMDGCN_GFX90C, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx942", true, true, EF_AMDGPU_MACH_AMDGCN_GFX942, true, false, 65536, 32, 4, 40, 1024, 16, 800, 102, 8, 512, 512) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx950", true, true, EF_AMDGPU_MACH_AMDGCN_GFX950, true, false, 65536, 32, 4, 40, 1024, 16, 800, 102, 8, 512, 512) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1010", false, true, EF_AMDGPU_MACH_AMDGCN_GFX1010, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1011", false, true, EF_AMDGPU_MACH_AMDGCN_GFX1011, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1012", false, true, EF_AMDGPU_MACH_AMDGCN_GFX1012, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1013", false, true, EF_AMDGPU_MACH_AMDGCN_GFX1013, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1030", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1030, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1031", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1031, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1032", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1032, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1033", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1033, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1034", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1034, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1035", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1035, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1036", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1036, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1100", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1100, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 24, 1536, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1101", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1101, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 24, 1536, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1102", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1102, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 16, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1103", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1103, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 16, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1150", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1150, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 16, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1151", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1151, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 24, 1536, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1152", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1152, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 16, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1153", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1153, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 16, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1200", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1200, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 24, 1536, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx1201", false, false, EF_AMDGPU_MACH_AMDGCN_GFX1201, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 24, 1536, 256) + +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx9-generic", false, true, EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC, true, true, 65536, 32, 4, 40, 1024, 16, 800, 102, 4, 256, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx9-4-generic", true, true, EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERIC, true, false, 65536, 32, 4, 40, 1024, 16, 800, 102, 8, 512, 512) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx10-1-generic", false, true, EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx10-3-generic", false, false, EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 8, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx11-generic", false, false, EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 16, 1024, 256) +HANDLE_ISA("amdgcn-amd-amdhsa-", "gfx12-generic", false, false, EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC, true, true, 65536, 32, 4, 40, 1024, 106, 800, 106, 24, 1536, 256) + +#undef HANDLE_ISA diff --git a/amd/comgr/src/comgr-metadata.cpp b/amd/comgr/src/comgr-metadata.cpp new file mode 100644 index 0000000000000..ac71da8e9b7c8 --- /dev/null +++ b/amd/comgr/src/comgr-metadata.cpp @@ -0,0 +1,724 @@ +//===- comgr-metadata.cpp - Metadata query functions ----------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains functions used to implement the Comgr metadata query +/// APIs, including: +/// amd_comgr_get_isa_count() +/// amd_comgr_get_isa_name() +/// amd_comgr_action_info_set_isa_name() +/// amd_comgr_get_isa_metadata() +/// amd_comgr_lookup_code_object() +/// +//===----------------------------------------------------------------------===// + +#include "comgr-metadata.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/BinaryFormat/MsgPackDocument.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Support/AMDGPUMetadata.h" +#include "llvm/Support/BinaryStreamReader.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Support/raw_ostream.h" +#include +#include + +using namespace llvm; +using namespace llvm::object; + +namespace COMGR { +namespace metadata { + +template using Elf_Note = typename ELFT::Note; + +namespace { +Expected> +getELFObjectFileBase(DataObject *DataP) { + std::unique_ptr Buf = + MemoryBuffer::getMemBuffer(StringRef(DataP->Data, DataP->Size)); + + Expected> ObjOrErr = + ObjectFile::createELFObjectFile(*Buf); + + if (auto Err = ObjOrErr.takeError()) { + return std::move(Err); + } + + return unique_dyn_cast(std::move(*ObjOrErr)); +} + +// PAL currently produces MsgPack metadata in a note with this ID. +// FIXME: Unify with HSA note types? +#define PAL_METADATA_NOTE_TYPE 13 + +// Try to merge "amdhsa.kernels" from DocNode @p From to @p To. +// The merge is allowed only if +// 1. "amdhsa.printf" record is not existing in either of the nodes. +// 2. "amdhsa.version" exists and is same. +// 3. "amdhsa.kernels" exists in both nodes. +// +// If merge is possible the function merges Kernel records +// to @p To and returns @c true. +bool mergeNoteRecords(llvm::msgpack::DocNode &From, llvm::msgpack::DocNode &To, + const StringRef VersionStrKey, + const StringRef PrintfStrKey, + const StringRef KernelStrKey) { + if (!From.isMap()) { + return false; + } + + if (To.isEmpty()) { + To = From; + return true; + } + + assert(To.isMap()); + + if (From.getMap().find(PrintfStrKey) != From.getMap().end()) { + /* Check if both have Printf records */ + if (To.getMap().find(PrintfStrKey) != To.getMap().end()) { + return false; + } + + /* Add Printf record for 'To' */ + To.getMap()[PrintfStrKey] = From.getMap()[PrintfStrKey]; + } + + auto &FromMapNode = From.getMap(); + auto &ToMapNode = To.getMap(); + + auto FromVersionArrayNode = FromMapNode.find(VersionStrKey); + auto ToVersionArrayNode = ToMapNode.find(VersionStrKey); + + if ((FromVersionArrayNode == FromMapNode.end() || + !FromVersionArrayNode->second.isArray()) || + (ToVersionArrayNode == ToMapNode.end() || + !ToVersionArrayNode->second.isArray())) { + return false; + } + + auto FromVersionArray = FromMapNode[VersionStrKey].getArray(); + auto ToVersionArray = ToMapNode[VersionStrKey].getArray(); + + if (FromVersionArray.size() != ToVersionArray.size()) { + return false; + } + + for (size_t I = 0, E = FromVersionArray.size(); I != E; ++I) { + if (FromVersionArray[I] != ToVersionArray[I]) { + return false; + } + } + + auto FromKernelArray = FromMapNode.find(KernelStrKey); + auto ToKernelArray = ToMapNode.find(KernelStrKey); + + if ((FromKernelArray == FromMapNode.end() || + !FromKernelArray->second.isArray()) || + (ToKernelArray == ToMapNode.end() || !ToKernelArray->second.isArray())) { + return false; + } + + auto &ToKernelRecords = ToKernelArray->second.getArray(); + for (auto Kernel : FromKernelArray->second.getArray()) { + ToKernelRecords.push_back(Kernel); + } + + return true; +} + +template +bool processNote(const Elf_Note &Note, DataMeta *MetaP, + llvm::msgpack::DocNode &Root) { + auto DescString = Note.getDescAsStringRef(4); + + if (Note.getName() == "AMD" && Note.getType() == ELF::NT_AMD_HSA_METADATA) { + + if (!Root.isEmpty()) { + return false; + } + + MetaP->MetaDoc->EmitIntegerBooleans = false; + MetaP->MetaDoc->RawDocument.clear(); + if (!MetaP->MetaDoc->Document.fromYAML(DescString)) { + return false; + } + + Root = MetaP->MetaDoc->Document.getRoot(); + return true; + } + if (((Note.getName() == "AMD" || Note.getName() == "AMDGPU") && + Note.getType() == PAL_METADATA_NOTE_TYPE) || + (Note.getName() == "AMDGPU" && + Note.getType() == ELF::NT_AMDGPU_METADATA)) { + if (!Root.isEmpty() && MetaP->MetaDoc->EmitIntegerBooleans != true) { + return false; + } + + MetaP->MetaDoc->EmitIntegerBooleans = true; + MetaP->MetaDoc->RawDocumentList.push_back(std::string(DescString)); + + /* TODO add support for merge using readFromBlob merge function */ + auto &Document = MetaP->MetaDoc->Document; + + Document.clear(); + if (!Document.readFromBlob(MetaP->MetaDoc->RawDocumentList.back(), false)) { + return false; + } + + return mergeNoteRecords(Document.getRoot(), Root, "amdhsa.version", + "amdhsa.printf", "amdhsa.kernels"); + } + return false; +} + +template +amd_comgr_status_t getElfMetadataRoot(const ELFObjectFile *Obj, + DataMeta *MetaP) { + bool Found = false; + llvm::msgpack::DocNode Root; + const ELFFile &ELFFile = Obj->getELFFile(); + + auto ProgramHeadersOrError = ELFFile.program_headers(); + if (errorToBool(ProgramHeadersOrError.takeError())) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + for (const auto &Phdr : *ProgramHeadersOrError) { + if (Phdr.p_type != ELF::PT_NOTE) { + continue; + } + Error Err = Error::success(); + for (const auto &Note : ELFFile.notes(Phdr, Err)) { + if (processNote(Note, MetaP, Root)) { + Found = true; + } + } + + if (errorToBool(std::move(Err))) { + return AMD_COMGR_STATUS_ERROR; + } + } + + if (Found) { + MetaP->MetaDoc->Document.getRoot() = Root; + MetaP->DocNode = MetaP->MetaDoc->Document.getRoot(); + return AMD_COMGR_STATUS_SUCCESS; + } + + auto SectionsOrError = ELFFile.sections(); + if (errorToBool(SectionsOrError.takeError())) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + for (const auto &Shdr : *SectionsOrError) { + if (Shdr.sh_type != ELF::SHT_NOTE) { + continue; + } + Error Err = Error::success(); + for (const auto &Note : ELFFile.notes(Shdr, Err)) { + if (processNote(Note, MetaP, Root)) { + Found = true; + } + } + + if (errorToBool(std::move(Err))) { + return AMD_COMGR_STATUS_ERROR; + } + } + + if (Found) { + MetaP->MetaDoc->Document.getRoot() = Root; + MetaP->DocNode = MetaP->MetaDoc->Document.getRoot(); + return AMD_COMGR_STATUS_SUCCESS; + } + + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; +} +} // namespace + +amd_comgr_status_t getMetadataRoot(DataObject *DataP, DataMeta *MetaP) { + auto ObjOrErr = getELFObjectFileBase(DataP); + if (errorToBool(ObjOrErr.takeError())) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + auto *Obj = ObjOrErr->get(); + + if (auto *ELF32LE = dyn_cast(Obj)) { + return getElfMetadataRoot(ELF32LE, MetaP); + } + if (auto *ELF64LE = dyn_cast(Obj)) { + return getElfMetadataRoot(ELF64LE, MetaP); + } + if (auto *ELF32BE = dyn_cast(Obj)) { + return getElfMetadataRoot(ELF32BE, MetaP); + } + auto *ELF64BE = dyn_cast(Obj); + return getElfMetadataRoot(ELF64BE, MetaP); +} + +struct IsaInfo { + const char *IsaName; + const char *Processor; + bool SrameccSupported; + bool XnackSupported; + unsigned ElfMachine; + bool TrapHandlerEnabled; + bool ImageSupport; + unsigned LDSSize; + unsigned LDSBankCount; + unsigned EUsPerCU; + unsigned MaxWavesPerCU; + unsigned MaxFlatWorkGroupSize; + unsigned SGPRAllocGranule; + unsigned TotalNumSGPRs; + unsigned AddressableNumSGPRs; + unsigned VGPRAllocGranule; + unsigned TotalNumVGPRs; + // TODO: Update this to AvailableNumVGPRs to be more accurate + unsigned AddressableNumVGPRs; +} IsaInfos[] = { +#define HANDLE_ISA(TARGET_TRIPLE, PROCESSOR, SRAMECC_SUPPORTED, \ + XNACK_SUPPORTED, ELF_MACHINE, TRAP_HANDLER_ENABLED, \ + IMAGE_SUPPORT, LDS_SIZE, LDS_BANK_COUNT, EUS_PER_CU, \ + MAX_WAVES_PER_CU, MAX_FLAT_WORK_GROUP_SIZE, \ + SGPR_ALLOC_GRANULE, TOTAL_NUM_SGPRS, ADDRESSABLE_NUM_SGPRS, \ + VGPR_ALLOC_GRANULE, TOTAL_NUM_VGPRS, ADDRESSABLE_NUM_VGPRS) \ + {TARGET_TRIPLE "-" PROCESSOR, \ + PROCESSOR, \ + SRAMECC_SUPPORTED, \ + XNACK_SUPPORTED, \ + ELF::ELF_MACHINE, \ + TRAP_HANDLER_ENABLED, \ + IMAGE_SUPPORT, \ + LDS_SIZE, \ + LDS_BANK_COUNT, \ + EUS_PER_CU, \ + MAX_WAVES_PER_CU, \ + MAX_FLAT_WORK_GROUP_SIZE, \ + SGPR_ALLOC_GRANULE, \ + TOTAL_NUM_SGPRS, \ + ADDRESSABLE_NUM_SGPRS, \ + VGPR_ALLOC_GRANULE, \ + TOTAL_NUM_VGPRS, \ + ADDRESSABLE_NUM_VGPRS}, +#include "comgr-isa-metadata.def" +}; + +size_t getIsaCount() { + return std::distance(std::begin(IsaInfos), std::end(IsaInfos)); +} + +// NOLINTNEXTLINE(readability-identifier-naming) +typedef struct amdgpu_hsa_note_code_object_version_s { + uint32_t major_version; // NOLINT(readability-identifier-naming) + uint32_t minor_version; // NOLINT(readability-identifier-naming) +} amdgpu_hsa_note_code_object_version_t; + +// NOLINTNEXTLINE(readability-identifier-naming) +namespace { +bool getMachInfo(unsigned Mach, std::string &Processor, bool &SrameccSupported, + bool &XnackSupported) { + auto *IsaIterator = std::find_if( + std::begin(IsaInfos), std::end(IsaInfos), + [Mach](const IsaInfo &IsaInfo) { return Mach == IsaInfo.ElfMachine; }); + if (IsaIterator == std::end(IsaInfos)) { + return false; + } + + Processor = IsaIterator->Processor; + SrameccSupported = IsaIterator->SrameccSupported; + XnackSupported = IsaIterator->XnackSupported; + return true; +} + +template +amd_comgr_status_t getElfIsaNameFromElfHeader(const ELFObjectFile *Obj, + std::string &ElfIsaName) { + auto ElfHeader = Obj->getELFFile().getHeader(); + + if (ElfHeader.e_ident[ELF::EI_CLASS] == ELF::ELFCLASS64) + ElfIsaName += "amdgcn"; + + if (ElfHeader.e_machine != ELF::EM_AMDGPU) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + ElfIsaName += "-amd-"; + + if (ElfHeader.e_ident[ELF::EI_OSABI] == ELF::ELFOSABI_AMDGPU_HSA) + ElfIsaName += "amdhsa"; + else + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + + ElfIsaName += "--"; + + std::string Processor; + bool SrameccSupported, XnackSupported; + if (!getMachInfo(ElfHeader.e_flags & ELF::EF_AMDGPU_MACH, Processor, + SrameccSupported, XnackSupported)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + ElfIsaName += Processor; + + switch (ElfHeader.e_ident[ELF::EI_ABIVERSION]) { + case ELF::ELFABIVERSION_AMDGPU_HSA_V4: + case ELF::ELFABIVERSION_AMDGPU_HSA_V5: + case ELF::ELFABIVERSION_AMDGPU_HSA_V6: { + // Note for V6: generic version is not part of the ISA name so + // we don't have to parse it. + switch (ElfHeader.e_flags & ELF::EF_AMDGPU_FEATURE_SRAMECC_V4) { + case ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4: + ElfIsaName += ":sramecc-"; + break; + case ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4: + ElfIsaName += ":sramecc+"; + break; + } + switch (ElfHeader.e_flags & ELF::EF_AMDGPU_FEATURE_XNACK_V4) { + case ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4: + ElfIsaName += ":xnack-"; + break; + case ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4: + ElfIsaName += ":xnack+"; + break; + } + break; + } + + default: + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + return AMD_COMGR_STATUS_SUCCESS; +} +} // namespace + +amd_comgr_status_t getElfIsaName(DataObject *DataP, std::string &IsaName) { + auto ObjOrErr = getELFObjectFileBase(DataP); + if (errorToBool(ObjOrErr.takeError())) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + auto *Obj = ObjOrErr->get(); + + if (auto *ELF64LE = dyn_cast(Obj)) + return getElfIsaNameFromElfHeader(ELF64LE, IsaName); + else + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; +} + +amd_comgr_status_t getIsaIndex(StringRef IsaString, size_t &Index) { + auto IsaName = IsaString.take_until([](char C) { return C == ':'; }); + auto *IsaIterator = std::find_if( + std::begin(IsaInfos), std::end(IsaInfos), + [&](const IsaInfo &IsaInfo) { return IsaName == IsaInfo.IsaName; }); + if (IsaIterator == std::end(IsaInfos)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + Index = std::distance(std::begin(IsaInfos), IsaIterator); + + return AMD_COMGR_STATUS_SUCCESS; +} + +bool isSupportedFeature(size_t IsaIndex, StringRef Feature) { + if (Feature.empty() || + (Feature.take_back() != "+" && Feature.take_back() != "-")) { + return false; + } + + return (Feature.drop_back() == "xnack" && + IsaInfos[IsaIndex].XnackSupported) || + (Feature.drop_back() == "sramecc" && + IsaInfos[IsaIndex].SrameccSupported); +} + +const char *getIsaName(size_t Index) { return IsaInfos[Index].IsaName; } + +amd_comgr_status_t getIsaMetadata(StringRef IsaName, + llvm::msgpack::Document &Doc) { + amd_comgr_status_t Status; + + size_t IsaIndex; + Status = getIsaIndex(IsaName, IsaIndex); + if (Status != AMD_COMGR_STATUS_SUCCESS) { + return Status; + } + + TargetIdentifier Ident; + Status = parseTargetIdentifier(IsaName, Ident); + if (Status != AMD_COMGR_STATUS_SUCCESS) { + return Status; + } + + auto Root = Doc.getRoot().getMap(/*Convert=*/true); + + Root["Name"] = Doc.getNode(IsaName, /*Copy=*/true); + Root["Architecture"] = Doc.getNode(Ident.Arch, /*Copy=*/true); + Root["Vendor"] = Doc.getNode(Ident.Vendor, /*Copy=*/true); + Root["OS"] = Doc.getNode(Ident.OS, /*Copy=*/true); + Root["Environment"] = Doc.getNode(Ident.Environ, /*Copy=*/true); + Root["Processor"] = Doc.getNode(Ident.Processor, /*Copy=*/true); + Root["Version"] = Doc.getNode("1.0.0", /*Copy=*/true); + + auto FeaturesNode = Doc.getMapNode(); + if (IsaInfos[IsaIndex].XnackSupported) { + FeaturesNode["xnack"] = Doc.getNode("any", /*Copy=*/true); + } + if (IsaInfos[IsaIndex].SrameccSupported) { + FeaturesNode["sramecc"] = Doc.getNode("any", /*Copy=*/true); + } + + for (size_t I = 0; I < Ident.Features.size(); ++I) { + if (FeaturesNode.find(Ident.Features[I].drop_back()) == + FeaturesNode.end()) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + auto State = Ident.Features[I].take_back(); + if (State == "+") { + FeaturesNode[Ident.Features[I].drop_back()] = + Doc.getNode("on", /*Copy=*/true); + } else if (State == "-") { + FeaturesNode[Ident.Features[I].drop_back()] = + Doc.getNode("off", /*Copy=*/true); + } else { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + } + + Root["Features"] = FeaturesNode; + + auto Info = IsaInfos[IsaIndex]; + Root["TrapHandlerEnabled"] = + Doc.getNode(std::to_string(Info.TrapHandlerEnabled), /*Copy=*/true); + Root["ImageSupport"] = + Doc.getNode(std::to_string(Info.ImageSupport), /*Copy=*/true); + Root["LocalMemorySize"] = + Doc.getNode(std::to_string(Info.LDSSize), /*Copy=*/true); + Root["EUsPerCU"] = Doc.getNode(std::to_string(Info.EUsPerCU), /*Copy=*/true); + Root["MaxWavesPerCU"] = + Doc.getNode(std::to_string(Info.MaxWavesPerCU), /*Copy=*/true); + Root["MaxFlatWorkGroupSize"] = + Doc.getNode(std::to_string(Info.MaxFlatWorkGroupSize), /*Copy=*/true); + Root["SGPRAllocGranule"] = + Doc.getNode(std::to_string(Info.SGPRAllocGranule), /*Copy=*/true); + Root["TotalNumSGPRs"] = + Doc.getNode(std::to_string(Info.TotalNumSGPRs), /*Copy=*/true); + Root["AddressableNumSGPRs"] = + Doc.getNode(std::to_string(Info.AddressableNumSGPRs), /*Copy=*/true); + Root["VGPRAllocGranule"] = + Doc.getNode(std::to_string(Info.VGPRAllocGranule), /*Copy=*/true); + Root["TotalNumVGPRs"] = + Doc.getNode(std::to_string(Info.TotalNumVGPRs), /*Copy=*/true); + Root["AddressableNumVGPRs"] = + Doc.getNode(std::to_string(Info.AddressableNumVGPRs), /*Copy=*/true); + Root["LDSBankCount"] = + Doc.getNode(std::to_string(Info.LDSBankCount), /*Copy=*/true); + + return AMD_COMGR_STATUS_SUCCESS; +} + +bool isValidIsaName(StringRef IsaString) { + TargetIdentifier Ident; + return parseTargetIdentifier(IsaString, Ident) == AMD_COMGR_STATUS_SUCCESS; +} + +namespace { +size_t constexpr strLiteralLength(char const *Str) { + size_t I = 0; + while (Str[I]) { + ++I; + } + return I; +} + +constexpr const char *OffloadKindHip = "hip"; +constexpr const char *OffloadKindHipV4 = "hipv4"; +constexpr const char *OffloadKindHcc = "hcc"; +constexpr const char *ClangOffloadBundlerMagic = "__CLANG_OFFLOAD_BUNDLE__"; +constexpr size_t OffloadBundleMagicLen = + strLiteralLength(ClangOffloadBundlerMagic); +} // namespace + +bool isCompatibleIsaName(StringRef IsaName, StringRef CodeObjectIsaName) { + if (IsaName == CodeObjectIsaName) { + return true; + } + + TargetIdentifier CodeObjectIdent; + if (parseTargetIdentifier(CodeObjectIsaName, CodeObjectIdent)) { + return false; + } + + TargetIdentifier IsaIdent; + if (parseTargetIdentifier(IsaName, IsaIdent)) { + return false; + } + + if (CodeObjectIdent.Processor != IsaIdent.Processor) { + return false; + } + + char CodeObjectXnack = ' ', CodeObjectSramecc = ' '; + for (auto Feature : CodeObjectIdent.Features) { + if (Feature.drop_back() == "xnack") { + CodeObjectXnack = Feature.take_back()[0]; + } + + if (Feature.drop_back() == "sramecc") { + CodeObjectSramecc = Feature.take_back()[0]; + } + } + + char IsaXnack = ' ', IsaSramecc = ' '; + for (auto Feature : IsaIdent.Features) { + if (Feature.drop_back() == "xnack") { + IsaXnack = Feature.take_back()[0]; + } + if (Feature.drop_back() == "sramecc") { + IsaSramecc = Feature.take_back()[0]; + } + } + + if (CodeObjectXnack != ' ') { + if (CodeObjectXnack != IsaXnack) { + return false; + } + } + + if (CodeObjectSramecc != ' ') { + if (CodeObjectSramecc != IsaSramecc) { + return false; + } + } + return true; +} + +amd_comgr_status_t +lookUpCodeObjectInSharedObject(DataObject *DataP, + amd_comgr_code_object_info_t *QueryList, + size_t QueryListSize) { + for (uint64_t I = 0; I < QueryListSize; I++) { + QueryList[I].offset = 0; + QueryList[I].size = 0; + } + + std::string IsaName; + amd_comgr_status_t Status = getElfIsaName(DataP, IsaName); + if (Status != AMD_COMGR_STATUS_SUCCESS) { + return Status; + } + + for (unsigned J = 0; J < QueryListSize; J++) { + if (isCompatibleIsaName(QueryList[J].isa, IsaName)) { + QueryList[J].offset = 0; + QueryList[J].size = DataP->Size; + break; + } + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t lookUpCodeObject(DataObject *DataP, + amd_comgr_code_object_info_t *QueryList, + size_t QueryListSize) { + + if (DataP->DataKind == AMD_COMGR_DATA_KIND_EXECUTABLE) { + return lookUpCodeObjectInSharedObject(DataP, QueryList, QueryListSize); + } + + int Seen = 0; + BinaryStreamReader Reader(StringRef(DataP->Data, DataP->Size), + llvm::endianness::little); + + StringRef Magic; + if (auto EC = Reader.readFixedString(Magic, OffloadBundleMagicLen)) { + return AMD_COMGR_STATUS_ERROR; + } + + if (Magic != ClangOffloadBundlerMagic) { + if (DataP->DataKind == AMD_COMGR_DATA_KIND_BYTES) { + return lookUpCodeObjectInSharedObject(DataP, QueryList, QueryListSize); + } + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + uint64_t NumOfCodeObjects = 0; + if (auto EC = Reader.readInteger(NumOfCodeObjects)) { + return AMD_COMGR_STATUS_ERROR; + } + + for (uint64_t I = 0; I < QueryListSize; I++) { + QueryList[I].offset = 0; + QueryList[I].size = 0; + } + + // For each code object, extract BundleEntryID information, and check that + // against each ISA in the QueryList + for (uint64_t I = 0; I < NumOfCodeObjects; I++) { + uint64_t BundleEntryCodeObjectSize = 0; + uint64_t BundleEntryCodeObjectOffset = 0; + uint64_t BundleEntryIDSize = 0; + StringRef BundleEntryID; + + if (auto EC = Reader.readInteger(BundleEntryCodeObjectOffset)) { + return AMD_COMGR_STATUS_ERROR; + } + + if (auto Status = Reader.readInteger(BundleEntryCodeObjectSize)) { + return AMD_COMGR_STATUS_ERROR; + } + + if (auto Status = Reader.readInteger(BundleEntryIDSize)) { + return AMD_COMGR_STATUS_ERROR; + } + + if (Reader.readFixedString(BundleEntryID, BundleEntryIDSize)) { + return AMD_COMGR_STATUS_ERROR; + } + + const auto OffloadAndTargetId = BundleEntryID.split('-'); + if (OffloadAndTargetId.first != OffloadKindHip && + OffloadAndTargetId.first != OffloadKindHipV4 && + OffloadAndTargetId.first != OffloadKindHcc) { + continue; + } + + for (unsigned J = 0; J < QueryListSize; J++) { + // If this QueryList item has already been found to be compatible with + // another BundleEntryID, no need to check against the current + // BundleEntryID + if (QueryList[J].size != 0) { + continue; + } + + // If the QueryList Isa is compatible with the BundleEntryID, set the + // QueryList offset/size to this BundleEntryID + if (isCompatibleIsaName(QueryList[J].isa, OffloadAndTargetId.second)) { + QueryList[J].offset = BundleEntryCodeObjectOffset; + QueryList[J].size = BundleEntryCodeObjectSize; + Seen++; + break; + } + } + + // Stop iterating over BundleEntryIDs once we have populated the entire + // QueryList + if (Seen == (int)QueryListSize) { + break; + } + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +} // namespace metadata +} // namespace COMGR diff --git a/amd/comgr/src/comgr-metadata.h b/amd/comgr/src/comgr-metadata.h new file mode 100644 index 0000000000000..7e16d42fa52de --- /dev/null +++ b/amd/comgr/src/comgr-metadata.h @@ -0,0 +1,44 @@ +//===- comgr-metadata.h - Metadata query internals ------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_METADATA_H +#define COMGR_METADATA_H + +#include "comgr.h" +#include "llvm/MC/TargetRegistry.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOptions.h" + +namespace COMGR { +namespace metadata { + +amd_comgr_status_t getMetadataRoot(DataObject *DataP, DataMeta *MetaP); + +size_t getIsaCount(); + +const char *getIsaName(size_t Index); + +amd_comgr_status_t getIsaMetadata(llvm::StringRef IsaName, + llvm::msgpack::Document &MetaP); + +bool isValidIsaName(llvm::StringRef IsaName); + +amd_comgr_status_t getElfIsaName(DataObject *DataP, std::string &IsaName); + +amd_comgr_status_t lookUpCodeObject(DataObject *DataP, + amd_comgr_code_object_info_t *QueryList, + size_t QueryListsize); + +amd_comgr_status_t getIsaIndex(const llvm::StringRef IsaName, size_t &Index); + +bool isSupportedFeature(size_t IsaIndex, llvm::StringRef Feature); + +} // namespace metadata +} // namespace COMGR + +#endif diff --git a/amd/comgr/src/comgr-signal.cpp b/amd/comgr/src/comgr-signal.cpp new file mode 100644 index 0000000000000..43fbc28d60fa7 --- /dev/null +++ b/amd/comgr/src/comgr-signal.cpp @@ -0,0 +1,94 @@ +//===- comgr-signal.cpp - Save and restore signal handlers ----------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the interception, saving, and restoring of OS signals. +/// These are invoked during Comgr Action invocations to avoid conflicts with +/// LLVM-installed signal handlers. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-signal.h" +#include "llvm/ADT/STLExtras.h" +#include + +namespace COMGR { +namespace signal { + +namespace { +#ifndef _MSC_VER +const int Signals[] = {SIGHUP, + SIGINT, + SIGPIPE, + SIGTERM, + SIGUSR1, + SIGUSR2, + SIGILL, + SIGTRAP, + SIGABRT, + SIGFPE, + SIGBUS, + SIGSEGV, + SIGQUIT +#ifdef SIGSYS + , + SIGSYS +#endif +#ifdef SIGXCPU + , + SIGXCPU +#endif +#ifdef SIGXFSZ + , + SIGXFSZ +#endif +#ifdef SIGEMT + , + SIGEMT +#endif +#ifdef SIGINFO + , + SIGINFO +#endif +}; + +const unsigned NumSigs = std::size(Signals); + +struct sigaction SigActions[NumSigs]; +#endif // _MSC_VER + +} // namespace + +amd_comgr_status_t saveHandlers() { +#ifndef _MSC_VER + for (unsigned I = 0; I < NumSigs; ++I) { + int Status = sigaction(Signals[I], nullptr, &SigActions[I]); + + if (Status) { + return AMD_COMGR_STATUS_ERROR; + } + } +#endif + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t restoreHandlers() { +#ifndef _MSC_VER + for (unsigned I = 0; I < NumSigs; ++I) { + int Status = sigaction(Signals[I], &SigActions[I], nullptr); + + if (Status) { + return AMD_COMGR_STATUS_ERROR; + } + } +#endif + return AMD_COMGR_STATUS_SUCCESS; +} + +} // namespace signal +} // namespace COMGR diff --git a/amd/comgr/src/comgr-signal.h b/amd/comgr/src/comgr-signal.h new file mode 100644 index 0000000000000..f041e17f24852 --- /dev/null +++ b/amd/comgr/src/comgr-signal.h @@ -0,0 +1,26 @@ +//===- comgr-signal.h - Save and restore signal handlers ------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_SIGNAL_H +#define COMGR_SIGNAL_H + +#include "comgr.h" + +namespace COMGR { +namespace signal { + +/// Save all signal handlers which are currently registered. +amd_comgr_status_t saveHandlers(); + +/// Restore all saved signal handlers. +amd_comgr_status_t restoreHandlers(); + +} // namespace signal +} // namespace COMGR + +#endif // COMGR_SIGNAL_H diff --git a/amd/comgr/src/comgr-spirv-command.cpp b/amd/comgr/src/comgr-spirv-command.cpp new file mode 100644 index 0000000000000..35ba42d920285 --- /dev/null +++ b/amd/comgr/src/comgr-spirv-command.cpp @@ -0,0 +1,89 @@ +//===- comgr-spirv-command.cpp - SPIRVCommand implementation --------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the CacheCommandAdaptor interface for the SPIRV to LLVM +/// Bitcode conversion. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-spirv-command.h" + +#ifndef COMGR_DISABLE_SPIRV +#include "comgr-diagnostic-handler.h" + +#include +#include +#include + +#include +#endif + +namespace COMGR { +using namespace llvm; +Error SPIRVCommand::writeExecuteOutput(StringRef CachedBuffer) { + assert(OutputBuffer.empty()); + OutputBuffer.reserve(CachedBuffer.size()); + OutputBuffer.insert(OutputBuffer.end(), CachedBuffer.begin(), + CachedBuffer.end()); + return Error::success(); +} + +Expected SPIRVCommand::readExecuteOutput() { + return StringRef(OutputBuffer.data(), OutputBuffer.size()); +} + +amd_comgr_status_t SPIRVCommand::execute(raw_ostream &LogS) { +#ifndef COMGR_DISABLE_SPIRV + LLVMContext Context; + Context.setDiagnosticHandler( + std::make_unique(LogS), true); + + // TODO: With C++23, we should investigate replacing with spanstream + // to avoid memory copies: + // https://en.cppreference.com/w/cpp/io/basic_ispanstream + std::istringstream ISS(std::string(InputBuffer.data(), InputBuffer.size())); + + Module *M; + std::string Err; + + SPIRV::TranslatorOpts Opts; + Opts.enableAllExtensions(); + Opts.setDesiredBIsRepresentation(SPIRV::BIsRepresentation::OpenCL20); + + if (!readSpirv(Context, Opts, ISS, M, Err)) { + LogS << "Failed to load SPIR-V as LLVM Module: " << Err << '\n'; + return AMD_COMGR_STATUS_ERROR; + } + + BitcodeWriter Writer(OutputBuffer); + Writer.writeModule(*M, false, nullptr, false, nullptr); + Writer.writeSymtab(); + Writer.writeStrtab(); + return AMD_COMGR_STATUS_SUCCESS; +#else + return AMD_COMGR_STATUS_ERROR; +#endif +} + +SPIRVCommand::ActionClass SPIRVCommand::getClass() const { + // return an action class that is not allocated to distinguish it from any + // clang action + return clang::driver::Action::ActionClass::JobClassLast + 1; +} + +void SPIRVCommand::addOptionsIdentifier(HashAlgorithm &) const { + // do nothing, there are no options + return; +} + +Error SPIRVCommand::addInputIdentifier(HashAlgorithm &H) const { + addString(H, InputBuffer); + return Error::success(); +} +} // namespace COMGR diff --git a/amd/comgr/src/comgr-spirv-command.h b/amd/comgr/src/comgr-spirv-command.h new file mode 100644 index 0000000000000..17465f3e570f4 --- /dev/null +++ b/amd/comgr/src/comgr-spirv-command.h @@ -0,0 +1,39 @@ +//===- comgr-spirv-command.h - SPIRVCommand implementation ----------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_SPIRV_COMMAND_H +#define COMGR_SPIRV_COMMAND_H + +#include "comgr-cache-command.h" +#include "comgr.h" + +namespace COMGR { +class SPIRVCommand : public CachedCommandAdaptor { +public: + llvm::StringRef InputBuffer; + llvm::SmallVectorImpl &OutputBuffer; + +public: + SPIRVCommand(DataObject *Input, llvm::SmallVectorImpl &OutputBuffer) + : InputBuffer(Input->Data, Input->Size), OutputBuffer(OutputBuffer) {} + + bool canCache() const final { return true; } + llvm::Error writeExecuteOutput(llvm::StringRef CachedBuffer) final; + llvm::Expected readExecuteOutput() final; + amd_comgr_status_t execute(llvm::raw_ostream &LogS) final; + + ~SPIRVCommand() override = default; + +protected: + ActionClass getClass() const override; + void addOptionsIdentifier(HashAlgorithm &) const override; + llvm::Error addInputIdentifier(HashAlgorithm &) const override; +}; +} // namespace COMGR + +#endif diff --git a/amd/comgr/src/comgr-symbol.cpp b/amd/comgr/src/comgr-symbol.cpp new file mode 100644 index 0000000000000..45dbddf1e4af4 --- /dev/null +++ b/amd/comgr/src/comgr-symbol.cpp @@ -0,0 +1,267 @@ +//===- comgr-symbol.cpp - Symbol lookup -----------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements helper functions for the amd_comgr_iterate_symbols() +/// and amd_comgr_symbol_lookup() APIs. +/// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "comgr.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/Object/Archive.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Object/SymbolSize.h" +#include "llvm/Support/raw_ostream.h" +#include + +using namespace llvm; +using namespace llvm::object; +using namespace llvm::support; +using namespace COMGR; + +SymbolContext::SymbolContext() + : Name(nullptr), Type(AMD_COMGR_SYMBOL_TYPE_NOTYPE), Size(0), + Undefined(true), Value(0) {} + +SymbolContext::~SymbolContext() { free(Name); } + +amd_comgr_status_t SymbolContext::setName(llvm::StringRef Name) { + return setCStr(this->Name, Name); +} + +amd_comgr_symbol_type_t +SymbolHelper::mapToComgrSymbolType(uint8_t ELFSymbolType) { + switch (ELFSymbolType) { + case ELF::STT_NOTYPE: + return AMD_COMGR_SYMBOL_TYPE_NOTYPE; + case ELF::STT_OBJECT: + return AMD_COMGR_SYMBOL_TYPE_OBJECT; + case ELF::STT_FUNC: + return AMD_COMGR_SYMBOL_TYPE_FUNC; + case ELF::STT_SECTION: + return AMD_COMGR_SYMBOL_TYPE_SECTION; + case ELF::STT_FILE: + return AMD_COMGR_SYMBOL_TYPE_FILE; + case ELF::STT_COMMON: + return AMD_COMGR_SYMBOL_TYPE_COMMON; + case ELF::STT_AMDGPU_HSA_KERNEL: + return AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL; + default: + return AMD_COMGR_SYMBOL_TYPE_UNKNOWN; + } +} + +// SymbolHelper version of createBinary, contrary to the one in Binary.cpp, +// in_text is textual input, not a filename. +Expected> SymbolHelper::createBinary(StringRef InText) { + ErrorOr> BufOrErr = + MemoryBuffer::getMemBuffer(InText); + if (std::error_code EC = BufOrErr.getError()) { + return errorCodeToError(EC); + } + std::unique_ptr &Buffer = BufOrErr.get(); + + Expected> BinOrErr = + llvm::object::createBinary(Buffer->getMemBufferRef()); + if (!BinOrErr) { + return BinOrErr.takeError(); + } + std::unique_ptr &Bin = BinOrErr.get(); + + return OwningBinary(std::move(Bin), std::move(Buffer)); +} + +SymbolContext *SymbolHelper::createBinary(StringRef Ins, const char *Name, + amd_comgr_data_kind_t Kind) { + StringRef Sname(Name); + + Expected> BinaryOrErr = createBinary(Ins); + if (!BinaryOrErr) { + return NULL; + } + + Binary &Binary = *BinaryOrErr.get().getBinary(); + + if (ObjectFile *Obj = dyn_cast(&Binary)) { + + std::vector SymbolList; + SymbolList.clear(); + + // extract the symbol list from dynsymtab or symtab + if (const auto *E = dyn_cast(Obj)) { + if (Kind == AMD_COMGR_DATA_KIND_EXECUTABLE) { + // executable kind, search dynsymtab + iterator_range Dsyms = + E->getDynamicSymbolIterators(); + for (ELFSymbolRef Dsym : Dsyms) { + SymbolList.push_back(Dsym); + } + + } else if (Kind == AMD_COMGR_DATA_KIND_RELOCATABLE) { + // relocatable kind, search symtab + auto Syms = E->symbols(); + for (ELFSymbolRef Sym : Syms) { + SymbolList.push_back(Sym); + } + } + } + + // Find symbol with specified name + SymbolRef Fsym; + bool Found = false; + for (auto &Symbol : SymbolList) { + Expected SymNameOrErr = Symbol.getName(); + if (!SymNameOrErr) { + return NULL; + } + StringRef SymName = *SymNameOrErr; + if (SymName == Sname) { +#if DEBUG + outs() << "Found! " << sname.data() << "\n"; +#endif + Fsym = Symbol; + Found = true; + break; + } + } + + if (!Found) { + return NULL; + } + + // ATTENTION: Do not attempt to split out the above "find symbol" code + // into a separate function returning a found SymbolRef. For some + // unknown reason, maybe a gcc codegen bug, at the return of the + // SymbolRef, the very beginning code "create_binary" will be called + // again unexpectedly, corrupting memory used by the returned SymbolRef. + // I also suspect it's the OwningBinary of create_binary causing the + // problem, but basically the reason is unknown. + + // Found the specified symbol, fill the SymbolContext values + std::unique_ptr Symp(new (std::nothrow) SymbolContext()); + if (!Symp) { + return NULL; + } + + Symp->setName(Name); + auto ExpectedFsymValue = Fsym.getValue(); + if (!ExpectedFsymValue) { + return NULL; + } + Symp->Value = ExpectedFsymValue.get(); + + DataRefImpl Symb = Fsym.getRawDataRefImpl(); + auto Flags = Fsym.getObject()->getSymbolFlags(Symb); + if (!Flags) { + return NULL; + } + + // symbol size + ELFSymbolRef Esym(Fsym); + Symp->Size = Esym.getSize(); + Symp->Type = mapToComgrSymbolType(Esym.getELFType()); + + // symbol undefined? + if (*Flags & SymbolRef::SF_Undefined) { + Symp->Undefined = true; + } else { + Symp->Undefined = false; + } + + return Symp.release(); + } + + return NULL; +} + +amd_comgr_status_t SymbolHelper::iterateTable( + StringRef Ins, amd_comgr_data_kind_t Kind, + amd_comgr_status_t (*Callback)(amd_comgr_symbol_t, void *), + void *UserData) { + Expected> BinaryOrErr = createBinary(Ins); + if (!BinaryOrErr) { + return AMD_COMGR_STATUS_ERROR; + } + + Binary &Binary = *BinaryOrErr.get().getBinary(); + + if (ObjectFile *Obj = dyn_cast(&Binary)) { + + std::vector SymbolList; + SymbolList.clear(); + + // extract the symbol list from dynsymtab or symtab + if (const auto *E = dyn_cast(Obj)) { + if (Kind == AMD_COMGR_DATA_KIND_EXECUTABLE) { + // executable kind, search dynsymtab + iterator_range Dsyms = + E->getDynamicSymbolIterators(); + for (ELFSymbolRef Dsym : Dsyms) { + SymbolList.push_back(Dsym); + } + + } else if (Kind == AMD_COMGR_DATA_KIND_RELOCATABLE) { + // relocatable kind, search symtab + auto Syms = E->symbols(); + for (ELFSymbolRef Sym : Syms) { + SymbolList.push_back(Sym); + } + } + } + + for (auto &Symbol : SymbolList) { + std::unique_ptr Ctxp(new (std::nothrow) SymbolContext()); + if (!Ctxp) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + Expected SymNameOrErr = Symbol.getName(); + if (!SymNameOrErr) { + return AMD_COMGR_STATUS_ERROR; + } + StringRef SymName = *SymNameOrErr; + Ctxp->setName(SymName); + auto ExpectedSymbolValue = Symbol.getValue(); + if (!ExpectedSymbolValue) { + return AMD_COMGR_STATUS_ERROR; + } + Ctxp->Value = ExpectedSymbolValue.get(); + + Expected TypeOrErr = Symbol.getType(); + if (!TypeOrErr) { + return AMD_COMGR_STATUS_ERROR; + } + DataRefImpl Symb = Symbol.getRawDataRefImpl(); + auto Flags = Symbol.getObject()->getSymbolFlags(Symb); + if (!Flags) { + return AMD_COMGR_STATUS_ERROR; + } + + ELFSymbolRef Esym(Symbol); + Ctxp->Size = Esym.getSize(); + Ctxp->Type = mapToComgrSymbolType(Esym.getELFType()); + + Ctxp->Undefined = (*Flags & SymbolRef::SF_Undefined) ? true : false; + + std::unique_ptr Symp( + new (std::nothrow) COMGR::DataSymbol(Ctxp.release())); + if (!Symp) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + amd_comgr_symbol_t Symt = COMGR::DataSymbol::convert(Symp.get()); + + (*Callback)(Symt, UserData); + } + + return AMD_COMGR_STATUS_SUCCESS; + } // ObjectFile + + return AMD_COMGR_STATUS_ERROR; +} diff --git a/amd/comgr/src/comgr-symbol.h b/amd/comgr/src/comgr-symbol.h new file mode 100644 index 0000000000000..41fb8eff71cd7 --- /dev/null +++ b/amd/comgr/src/comgr-symbol.h @@ -0,0 +1,50 @@ +//===- comgr-symbol.h - Symbol lookup -------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_SYMBOL_H_ +#define COMGR_SYMBOL_H_ + +#include "amd_comgr.h" +#include "llvm/Object/ObjectFile.h" + +namespace COMGR { + +struct SymbolContext { + SymbolContext(); + ~SymbolContext(); + + amd_comgr_status_t setName(llvm::StringRef Name); + + char *Name; + amd_comgr_symbol_type_t Type; + uint64_t Size; + bool Undefined; + uint64_t Value; +}; + +class SymbolHelper { + +public: + amd_comgr_symbol_type_t mapToComgrSymbolType(uint8_t ELFSymbolType); + + llvm::Expected> + createBinary(llvm::StringRef InBuffer); + + SymbolContext *createBinary(llvm::StringRef InBuffer, const char *Name, + amd_comgr_data_kind_t Kind); + + amd_comgr_status_t + iterateTable(llvm::StringRef InBuffer, amd_comgr_data_kind_t Kind, + amd_comgr_status_t (*Callback)(amd_comgr_symbol_t, void *), + void *UserData); + +}; // SymbolHelper + +} // namespace COMGR + +#endif diff --git a/amd/comgr/src/comgr-symbolizer.cpp b/amd/comgr/src/comgr-symbolizer.cpp new file mode 100644 index 0000000000000..2a1bfe4124ecb --- /dev/null +++ b/amd/comgr/src/comgr-symbolizer.cpp @@ -0,0 +1,106 @@ +//===- comgr-symbolizer.cpp - Symbolizer implementation -------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the amd_comgr_symbolize() API, leveraging LLVM's +/// LLVMSymbolizer class and llvm::symbolize namespace. +/// +//===----------------------------------------------------------------------===// + +#include "comgr-symbolizer.h" +#include "llvm/BinaryFormat/Magic.h" +#include "llvm/DebugInfo/Symbolize/SymbolizableObjectFile.h" +#include "llvm/Support/Error.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/raw_ostream.h" +#include + +using namespace COMGR; + +namespace { +// llvm symbolizer with default options +LLVMSymbolizer::Options getDefaultOptions() { + LLVMSymbolizer::Options Opt; + Opt.SkipLineZero = true; + return Opt; +} + +llvm::symbolize::PrinterConfig getDefaultPrinterConfig() { + llvm::symbolize::PrinterConfig Config; + Config.Pretty = true; + Config.Verbose = false; + Config.PrintFunctions = true; + Config.PrintAddress = false; + Config.SourceContextLines = 0; + return Config; +} + +llvm::symbolize::ErrorHandler +symbolizeErrorHandler(llvm::raw_string_ostream &OS) { + return + [&](const llvm::ErrorInfoBase &ErrorInfo, llvm::StringRef ErrorBanner) { + OS << ErrorBanner; + ErrorInfo.log(OS); + OS << '\n'; + }; +} +} // namespace + +Symbolizer::Symbolizer(std::unique_ptr &&CodeObject, + PrintSymbolCallback PrintSymbol) + : CodeObject(std::move(CodeObject)), PrintSymbol(PrintSymbol) { + SymbolizerImpl = std::make_unique(getDefaultOptions()); +} +Symbolizer::~Symbolizer() = default; + +amd_comgr_status_t +Symbolizer::create(DataObject *CodeObjectP, PrintSymbolCallback PrintSymbol, + amd_comgr_symbolizer_info_t *SymbolizeInfo) { + std::unique_ptr Buf = llvm::MemoryBuffer::getMemBuffer( + llvm::StringRef(CodeObjectP->Data, CodeObjectP->Size), "", false); + + if (!Buf) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + auto ObjectOrErr = ObjectFile::createObjectFile(*Buf); + if (errorToBool(ObjectOrErr.takeError())) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + std::unique_ptr ObjFile = std::move(ObjectOrErr.get()); + Symbolizer *SI = + new (std::nothrow) Symbolizer(std::move(ObjFile), PrintSymbol); + if (!SI) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + *SymbolizeInfo = Symbolizer::convert(SI); + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t Symbolizer::symbolize(uint64_t Address, bool IsCode, + void *UserData) { + + std::string Result; + llvm::raw_string_ostream OS(Result); + llvm::symbolize::PrinterConfig Config = getDefaultPrinterConfig(); + llvm::symbolize::Request Request{"", Address, ""}; + auto Printer = std::make_unique( + OS, symbolizeErrorHandler(OS), Config); + if (IsCode) { + auto ResOrErr = SymbolizerImpl->symbolizeInlinedCode( + *CodeObject, {Address, llvm::object::SectionedAddress::UndefSection}); + Printer->print(Request, ResOrErr ? ResOrErr.get() : llvm::DIInliningInfo()); + } else { // data + auto ResOrErr = SymbolizerImpl->symbolizeData( + *CodeObject, {Address, llvm::object::SectionedAddress::UndefSection}); + Printer->print(Request, ResOrErr ? ResOrErr.get() : llvm::DIGlobal()); + } + + PrintSymbol(Result.c_str(), UserData); + return AMD_COMGR_STATUS_SUCCESS; +} diff --git a/amd/comgr/src/comgr-symbolizer.h b/amd/comgr/src/comgr-symbolizer.h new file mode 100644 index 0000000000000..d879593eec904 --- /dev/null +++ b/amd/comgr/src/comgr-symbolizer.h @@ -0,0 +1,59 @@ +//===- comgr-symbolizer.h - Symbolizer implementation ---------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_SYMBOLIZER_H +#define COMGR_SYMBOLIZER_H + +#include "comgr.h" +#include "llvm/DebugInfo/Symbolize/DIPrinter.h" +#include "llvm/DebugInfo/Symbolize/Symbolize.h" +#include "llvm/Object/ELFObjectFile.h" +#include + +using namespace llvm::symbolize; +using namespace llvm::object; + +namespace COMGR { + +typedef void (*PrintSymbolCallback)(const char *, void *); + +struct Symbolizer { + Symbolizer(std::unique_ptr &&CodeObject, + PrintSymbolCallback PrintSymbol); + ~Symbolizer(); + + static amd_comgr_symbolizer_info_t convert(Symbolizer *SymbolizerObj) { + amd_comgr_symbolizer_info_t Handle = { + static_cast(reinterpret_cast(SymbolizerObj))}; + return Handle; + } + + static const amd_comgr_symbolizer_info_t + convert(const Symbolizer *SymbolizerObj) { + const amd_comgr_symbolizer_info_t Handle = { + static_cast(reinterpret_cast(SymbolizerObj))}; + return Handle; + } + + static Symbolizer *convert(amd_comgr_symbolizer_info_t SymbolizerInfo) { + return reinterpret_cast(SymbolizerInfo.handle); + } + + static amd_comgr_status_t create(DataObject *CodeObjectP, + PrintSymbolCallback PrintSymbol, + amd_comgr_symbolizer_info_t *SymbolizeInfo); + + amd_comgr_status_t symbolize(uint64_t Address, bool IsCode, void *UserData); + +private: + std::unique_ptr SymbolizerImpl; + std::unique_ptr CodeObject; + PrintSymbolCallback PrintSymbol; +}; +} // namespace COMGR +#endif diff --git a/amd/comgr/src/comgr-unbundle-command.cpp b/amd/comgr/src/comgr-unbundle-command.cpp new file mode 100644 index 0000000000000..df2ca766217f3 --- /dev/null +++ b/amd/comgr/src/comgr-unbundle-command.cpp @@ -0,0 +1,158 @@ +//===- comgr-unbundle-command.cpp - UnbundleCommand implementation --------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the CacheCommandAdaptor interface for +/// llvm::OffloadBundler::Unbundle() routines that are stored in the cache. +/// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +namespace COMGR { +using namespace llvm; +using namespace clang; + +using SizeFieldType = uint32_t; + +bool UnbundleCommand::canCache() const { + // The header format for AR files is not the same as object files + if (Kind == AMD_COMGR_DATA_KIND_AR_BUNDLE) + return false; + + StringRef InputFilename = Config.InputFileNames.front(); + file_magic Magic; + if (identify_magic(InputFilename, Magic)) + return false; + + // Check the input file magic. Handle only compressed bundles + // It's not worth to cache other types of bundles + return Magic == file_magic::offload_bundle_compressed; +} + +Error UnbundleCommand::writeExecuteOutput(StringRef CachedBuffer) { + for (StringRef OutputFilename : Config.OutputFileNames) { + SizeFieldType OutputFileSize; + if (CachedBuffer.size() < sizeof(OutputFileSize)) + return createStringError(std::errc::invalid_argument, + "Not enough bytes to read output file size"); + memcpy(&OutputFileSize, CachedBuffer.data(), sizeof(OutputFileSize)); + CachedBuffer = CachedBuffer.drop_front(sizeof(OutputFileSize)); + + if (CachedBuffer.size() < OutputFileSize) + return createStringError(std::errc::invalid_argument, + "Not enough bytes to read output file contents"); + + StringRef OutputFileContents = CachedBuffer.substr(0, OutputFileSize); + CachedBuffer = CachedBuffer.drop_front(OutputFileSize); + + if (Error Err = CachedCommandAdaptor::writeSingleOutputFile( + OutputFilename, OutputFileContents)) + return Err; + } + + if (!CachedBuffer.empty()) + return createStringError(std::errc::invalid_argument, + "Bytes in cache entry not used for the output"); + return Error::success(); +} + +Expected UnbundleCommand::readExecuteOutput() { + size_t OutputSize = 0; + for (StringRef OutputFilename : Config.OutputFileNames) { + auto MaybeOneOutput = + CachedCommandAdaptor::readSingleOutputFile(OutputFilename); + if (!MaybeOneOutput) + return MaybeOneOutput.takeError(); + + const MemoryBuffer &OneOutputBuffer = **MaybeOneOutput; + SizeFieldType OneOutputFileSize = OneOutputBuffer.getBufferSize(); + + OutputBuffer.resize_for_overwrite(OutputSize + sizeof(OneOutputFileSize) + + OneOutputFileSize); + + memcpy(OutputBuffer.data() + OutputSize, &OneOutputFileSize, + sizeof(OneOutputFileSize)); + OutputSize += sizeof(OneOutputFileSize); + memcpy(OutputBuffer.data() + OutputSize, OneOutputBuffer.getBufferStart(), + OneOutputFileSize); + OutputSize += OneOutputFileSize; + } + return OutputBuffer; +} + +amd_comgr_status_t UnbundleCommand::execute(raw_ostream &LogS) { + assert(Config.InputFileNames.size() == 1); + + OffloadBundler Bundler(Config); + + switch (Kind) { + case AMD_COMGR_DATA_KIND_BC_BUNDLE: + case AMD_COMGR_DATA_KIND_OBJ_BUNDLE: { + if (Error Err = Bundler.UnbundleFiles()) { + logAllUnhandledErrors(std::move(Err), LogS, "Unbundle Error: "); + return AMD_COMGR_STATUS_ERROR; + } + break; + } + case AMD_COMGR_DATA_KIND_AR_BUNDLE: { + if (Error Err = Bundler.UnbundleArchive()) { + logAllUnhandledErrors(std::move(Err), LogS, "Unbundle Archives Error: "); + return AMD_COMGR_STATUS_ERROR; + } + break; + } + default: + llvm_unreachable("invalid bundle type"); + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +CachedCommandAdaptor::ActionClass UnbundleCommand::getClass() const { + return clang::driver::Action::OffloadUnbundlingJobClass; +} + +void UnbundleCommand::addOptionsIdentifier(HashAlgorithm &H) const { + addUInt(H, Config.TargetNames.size()); + for (StringRef Target : Config.TargetNames) { + CachedCommandAdaptor::addString(H, Target); + } +} + +Error UnbundleCommand::addInputIdentifier(HashAlgorithm &H) const { + StringRef InputFilename = Config.InputFileNames.front(); + + ErrorOr> MaybeInputBuffer = + MemoryBuffer::getFile(InputFilename); + if (!MaybeInputBuffer) { + std::error_code EC = MaybeInputBuffer.getError(); + return createStringError(EC, Twine("Failed to open ") + InputFilename + + " : " + EC.message() + "\n"); + } + + MemoryBuffer &InputBuffer = **MaybeInputBuffer; + + using Header = CompressedOffloadBundle::CompressedBundleHeader; + Expected
MaybeHeader = Header::tryParse(InputBuffer.getBuffer()); + if (!MaybeHeader) + return MaybeHeader.takeError(); + + // The hash represents the contents of the bundle. Extracting the same + // contents should give the same result, regardless of the compression + // algorithm or header version. Since the hash used by the offload bundler is + // not a cryptographic hash, we also add the uncompressed file size. + addUInt(H, MaybeHeader->Hash); + addUInt(H, MaybeHeader->UncompressedFileSize); + return Error::success(); +} + +} // namespace COMGR diff --git a/amd/comgr/src/comgr-unbundle-command.h b/amd/comgr/src/comgr-unbundle-command.h new file mode 100644 index 0000000000000..27f312462fa24 --- /dev/null +++ b/amd/comgr/src/comgr-unbundle-command.h @@ -0,0 +1,47 @@ +//===- comgr-unbundle-command.h - UnbundleCommand implementation ----------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_BUNDLER_COMMAND_H +#define COMGR_BUNDLER_COMMAND_H + +#include + +namespace clang { +class OffloadBundlerConfig; +} // namespace clang + +namespace COMGR { +class UnbundleCommand final : public CachedCommandAdaptor { +private: + amd_comgr_data_kind_t Kind; + const clang::OffloadBundlerConfig &Config; + + // To avoid copies, store the output of execute, such that readExecuteOutput + // can return a reference. + llvm::SmallString<64> OutputBuffer; + +public: + UnbundleCommand(amd_comgr_data_kind_t Kind, + const clang::OffloadBundlerConfig &Config) + : Kind(Kind), Config(Config) {} + + bool canCache() const override; + llvm::Error writeExecuteOutput(llvm::StringRef CachedBuffer) override; + llvm::Expected readExecuteOutput() override; + amd_comgr_status_t execute(llvm::raw_ostream &LogS) override; + + ~UnbundleCommand() override = default; + +protected: + ActionClass getClass() const override; + void addOptionsIdentifier(HashAlgorithm &) const override; + llvm::Error addInputIdentifier(HashAlgorithm &) const override; +}; +} // namespace COMGR + +#endif diff --git a/amd/comgr/src/comgr.cpp b/amd/comgr/src/comgr.cpp new file mode 100644 index 0000000000000..f0ace22833952 --- /dev/null +++ b/amd/comgr/src/comgr.cpp @@ -0,0 +1,2251 @@ +//===- comgr.cpp - User-facing APIs ---------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the core user-facing Comgr APIs, including compilation, +/// metadata, and disassembly, symbol lookup, and symbolization APIs. +/// +//===----------------------------------------------------------------------===// + +#include "comgr.h" +#include "comgr-compiler.h" +#include "comgr-device-libs.h" +#include "comgr-disassembly.h" +#include "comgr-env.h" +#include "comgr-metadata.h" +#include "comgr-signal.h" +#include "comgr-symbol.h" +#include "comgr-symbolizer.h" + +#include "clang/Basic/Version.h" +#include "llvm/Bitcode/BitcodeReader.h" +#include "llvm/Demangle/Demangle.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/Module.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Support/TargetSelect.h" +#include +#include +#include + +#include "time-stat/ts-interface.h" + +#ifndef AMD_NOINLINE +#ifdef __GNUC__ +#define AMD_NOINLINE __attribute__((noinline)) +#else +#define AMD_NOINLINE __declspec(noinline) +#endif +#endif + +// Needed for stringification of macro expansions for git branch/commit macros +#define xstringify(x) stringify(x) +#define stringify(x) #x + +using namespace llvm; +using namespace COMGR; +using namespace COMGR::TimeStatistics; + +namespace { +bool isLanguageValid(amd_comgr_language_t Language) { + return Language >= AMD_COMGR_LANGUAGE_NONE && + Language <= AMD_COMGR_LANGUAGE_LAST; +} + +bool isActionValid(amd_comgr_action_kind_t ActionKind) { + return ActionKind <= AMD_COMGR_ACTION_LAST; +} + +bool isSymbolInfoValid(amd_comgr_symbol_info_t SymbolInfo) { + return SymbolInfo >= AMD_COMGR_SYMBOL_INFO_NAME_LENGTH && + SymbolInfo <= AMD_COMGR_SYMBOL_INFO_LAST; +} + + +amd_comgr_status_t dispatchCompilerAction(amd_comgr_action_kind_t ActionKind, + DataAction *ActionInfo, + DataSet *InputSet, DataSet *ResultSet, + raw_ostream &LogS) { + AMDGPUCompiler Compiler(ActionInfo, InputSet, ResultSet, LogS); + switch (ActionKind) { + case AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR: + return Compiler.preprocessToSource(); + case AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC: + return Compiler.compileToBitcode(); + case AMD_COMGR_ACTION_UNBUNDLE: + return Compiler.unbundle(); + case AMD_COMGR_ACTION_LINK_BC_TO_BC: + return Compiler.linkBitcodeToBitcode(); + case AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE: + return Compiler.codeGenBitcodeToRelocatable(); + case AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY: + return Compiler.codeGenBitcodeToAssembly(); + case AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE: + return Compiler.assembleToRelocatable(); + case AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE: + return Compiler.linkToRelocatable(); + case AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE: + return Compiler.linkToExecutable(); + case AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE: + return Compiler.compileToRelocatable(); + case AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC: + return Compiler.compileToBitcode(true); + case AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE: + return Compiler.compileToExecutable(); + case AMD_COMGR_ACTION_COMPILE_SPIRV_TO_RELOCATABLE: + return Compiler.compileSpirvToRelocatable(); + case AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC: + return Compiler.translateSpirvToBitcode(); + + default: + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } +} + +StringRef getLanguageName(amd_comgr_language_t Language) { + switch (Language) { + case AMD_COMGR_LANGUAGE_NONE: + return "AMD_COMGR_LANGUAGE_NONE"; + case AMD_COMGR_LANGUAGE_OPENCL_1_2: + return "AMD_COMGR_LANGUAGE_OPENCL_1_2"; + case AMD_COMGR_LANGUAGE_OPENCL_2_0: + return "AMD_COMGR_LANGUAGE_OPENCL_2_0"; + case AMD_COMGR_LANGUAGE_HIP: + return "AMD_COMGR_LANGUAGE_HIP"; + case AMD_COMGR_LANGUAGE_LLVM_IR: + return "AMD_COMGR_LANGUAGE_LLVM_IR"; + } + + llvm_unreachable("invalid language"); +} + +StringRef getStatusName(amd_comgr_status_t Status) { + switch (Status) { + case AMD_COMGR_STATUS_SUCCESS: + return "AMD_COMGR_STATUS_SUCCESS"; + case AMD_COMGR_STATUS_ERROR: + return "AMD_COMGR_STATUS_ERROR"; + case AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT: + return "AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT"; + case AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES: + return "AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES"; + } + + llvm_unreachable("invalid status"); +} + +/// Perform a simple quoting of an option to allow separating options with +/// space in debug output. The option is surrounded by double quotes, and +/// any embedded double quotes or backslashes are preceeded by a backslash. +void printQuotedOption(raw_ostream &OS, StringRef Option) { + OS << '"'; + for (const char C : Option) { + if (C == '"' || C == '\\') { + OS << '\\'; + } + OS << C; + } + OS << '"'; +} +} // namespace + +StringRef getActionKindName(amd_comgr_action_kind_t ActionKind) { + switch (ActionKind) { + case AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR: + return "AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR"; + case AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS: + return "AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS"; + case AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC: + return "AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC"; + case AMD_COMGR_ACTION_LINK_BC_TO_BC: + return "AMD_COMGR_ACTION_LINK_BC_TO_BC"; + case AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE: + return "AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE"; + case AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY: + return "AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY"; + case AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE: + return "AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE"; + case AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE: + return "AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE"; + case AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE: + return "AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE"; + case AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE: + return "AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE"; + case AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE: + return "AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE"; + case AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE: + return "AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE"; + case AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE: + return "AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE"; + case AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC: + return "AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC"; + case AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE: + return "AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE"; + case AMD_COMGR_ACTION_UNBUNDLE: + return "AMD_COMGR_ACTION_UNBUNDLE"; + case AMD_COMGR_ACTION_COMPILE_SPIRV_TO_RELOCATABLE: + return "AMD_COMGR_ACTION_COMPILE_SPIRV_TO_RELOCATABLE"; + case AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC: + return "AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC"; + } + + llvm_unreachable("invalid action"); +} + +bool COMGR::isDataKindValid(amd_comgr_data_kind_t DataKind) { + return DataKind > AMD_COMGR_DATA_KIND_UNDEF && + DataKind <= AMD_COMGR_DATA_KIND_LAST; +} + +amd_comgr_status_t COMGR::setCStr(char *&Dest, StringRef Src, size_t *Size) { + free(Dest); + Dest = reinterpret_cast(malloc(Src.size() + 1)); + if (!Dest) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + memcpy(Dest, Src.data(), Src.size()); + Dest[Src.size()] = '\0'; + if (Size) { + *Size = Src.size(); + } + return AMD_COMGR_STATUS_SUCCESS; +} + +StringRef COMGR::getComgrHashIdentifier() { + return xstringify(AMD_COMGR_VERSION_ID); +} + +amd_comgr_status_t COMGR::parseTargetIdentifier(StringRef IdentStr, + TargetIdentifier &Ident) { + SmallVector IsaNameComponents; + IdentStr.split(IsaNameComponents, '-', 4); + if (IsaNameComponents.size() != 5) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + Ident.Arch = IsaNameComponents[0]; + Ident.Vendor = IsaNameComponents[1]; + Ident.OS = IsaNameComponents[2]; + Ident.Environ = IsaNameComponents[3]; + + Ident.Features.clear(); + IsaNameComponents[4].split(Ident.Features, ':'); + + Ident.Processor = Ident.Features[0]; + Ident.Features.erase(Ident.Features.begin()); + + + // TODO: Add a LIT test for this + if (IdentStr == "spirv64-amd-amdhsa--amdgcnspirv" || + IdentStr == "spirv64-amd-amdhsa-unknown-amdgcnspirv") { + // Features not supported for SPIR-V + if (!Ident.Features.empty()) + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + return AMD_COMGR_STATUS_SUCCESS; + } + + size_t IsaIndex; + amd_comgr_status_t Status = metadata::getIsaIndex(IdentStr, IsaIndex); + if (Status != AMD_COMGR_STATUS_SUCCESS) { + return Status; + } + + for (auto Feature : Ident.Features) { + if (!metadata::isSupportedFeature(IsaIndex, Feature)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +void COMGR::ensureLLVMInitialized() { + + // LLVMInitializeAMDGPUTargetInfo calls TargetRegistry.cpp:RegisterTarget() + // This function is not thread safe. There may be thread safety issues + // with the other LLVMInitialize functions as well. For completeness, we + // include all of these initialization functions in mutual exclusion region + // TODO: remove mutex once LLVM multi-threading issues are resolved + static std::mutex LlvmInitMutex; + { + std::scoped_lock LlvmInitLock(LlvmInitMutex); + + static bool LLVMInitialized = false; + if (LLVMInitialized) { + return; + } + LLVMInitializeAMDGPUTarget(); + LLVMInitializeAMDGPUTargetInfo(); + LLVMInitializeAMDGPUTargetMC(); + LLVMInitializeAMDGPUDisassembler(); + LLVMInitializeAMDGPUAsmParser(); + LLVMInitializeAMDGPUAsmPrinter(); + LLVMInitialized = true; + } +} + +void COMGR::clearLLVMOptions() { + cl::ResetAllOptionOccurrences(); + for (auto *SC : cl::getRegisteredSubcommands()) { + for (auto &OM : SC->OptionsMap) { + cl::Option *O = OM.second; + O->setDefault(); + } + } +} + +DataObject::DataObject(amd_comgr_data_kind_t DataKind) + : DataKind(DataKind), Data(nullptr), Name(nullptr), Size(0), RefCount(1), + DataSym(nullptr) {} + +DataObject::~DataObject() { + DataKind = AMD_COMGR_DATA_KIND_UNDEF; + clearData(); + free(Name); + delete DataSym; +} + +DataObject *DataObject::allocate(amd_comgr_data_kind_t DataKind) { + return new (std::nothrow) DataObject(DataKind); +} + +void DataObject::release() { + if (--RefCount == 0) { + delete this; + } +} + +amd_comgr_status_t DataObject::setName(llvm::StringRef Name) { + return setCStr(this->Name, Name); +} + +amd_comgr_status_t DataObject::setData(llvm::StringRef Data) { + clearData(); + return setCStr(this->Data, Data, &Size); +} + +amd_comgr_status_t DataObject::setData(std::unique_ptr MB) { + Buffer = std::move(MB); + Data = const_cast(Buffer->getBufferStart()); + Size = Buffer->getBufferSize(); + MangledNames.clear(); + return AMD_COMGR_STATUS_SUCCESS; +} + +void DataObject::clearData() { + if (Buffer) { + Buffer.reset(); + } else { + free(Data); + } + + Data = nullptr; + Size = 0; + MangledNames.clear(); +} + +DataSet::DataSet() : DataObjects() {} +DataSet::~DataSet() { + for (DataObject *Data : DataObjects) { + Data->release(); + } +} + +DataAction::DataAction() + : IsaName(nullptr), Path(nullptr), Language(AMD_COMGR_LANGUAGE_NONE), + Logging(false) {} + +DataAction::~DataAction() { + free(IsaName); + free(Path); +} + +amd_comgr_status_t DataAction::setIsaName(llvm::StringRef IsaName) { + return setCStr(this->IsaName, IsaName); +} + +amd_comgr_status_t DataAction::setActionPath(llvm::StringRef ActionPath) { + return setCStr(this->Path, ActionPath); +} + +amd_comgr_status_t DataAction::setOptionList(ArrayRef Options) { + ListOptions.clear(); + for (auto &Option : Options) { + ListOptions.push_back(Option); + } + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t DataAction::getOptionListCount(size_t &Size) { + Size = ListOptions.size(); + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t DataAction::getOptionListItem(size_t Index, + StringRef &Option) { + if (Index >= ListOptions.size()) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + auto &Str = ListOptions[Index]; + Option = StringRef(Str.c_str(), Str.size() + 1); + return AMD_COMGR_STATUS_SUCCESS; +} + +ArrayRef DataAction::getOptions() { return ListOptions; } + +amd_comgr_status_t +DataAction::setBundleEntryIDs(ArrayRef EntryIDs) { + BundleEntryIDs.clear(); + for (auto &ID : EntryIDs) { + BundleEntryIDs.push_back(ID); + } + return AMD_COMGR_STATUS_SUCCESS; +} + +ArrayRef DataAction::getBundleEntryIDs() { return BundleEntryIDs; } + +amd_comgr_metadata_kind_t DataMeta::getMetadataKind() { + if (DocNode.isScalar()) { + return AMD_COMGR_METADATA_KIND_STRING; + } + if (DocNode.isArray()) { + return AMD_COMGR_METADATA_KIND_LIST; + } + if (DocNode.isMap()) { + return AMD_COMGR_METADATA_KIND_MAP; + } + // treat as NULL + return AMD_COMGR_METADATA_KIND_NULL; +} + +std::string DataMeta::convertDocNodeToString(msgpack::DocNode DocNode) { + assert(DocNode.isScalar() && "cannot convert non-scalar DocNode to string"); + if (MetaDoc->EmitIntegerBooleans && + DocNode.getKind() == msgpack::Type::Boolean) { + return DocNode.getBool() ? "1" : "0"; + } + return DocNode.toString(); +} + +DataSymbol::DataSymbol(SymbolContext *DataSym) : DataSym(DataSym) {} +DataSymbol::~DataSymbol() { delete DataSym; } + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_status_string + // + (amd_comgr_status_t Status, const char **StatusString) { + if (!StatusString || Status < AMD_COMGR_STATUS_SUCCESS || + Status > AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + switch (Status) { + case AMD_COMGR_STATUS_SUCCESS: + *StatusString = "SUCCESS"; + break; + case AMD_COMGR_STATUS_ERROR: + *StatusString = "ERROR"; + break; + case AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT: + *StatusString = "INVALID_ARGUMENT"; + break; + case AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES: + *StatusString = "OUT_OF_RESOURCES"; + break; + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +void AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_version + // + (size_t *Major, size_t *Minor) { + *Major = AMD_COMGR_INTERFACE_VERSION_MAJOR; + *Minor = AMD_COMGR_INTERFACE_VERSION_MINOR; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_isa_count + // + (size_t *Count) { + if (!Count) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + *Count = metadata::getIsaCount(); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_isa_name + // + (size_t Index, const char **IsaName) { + if (!IsaName || Index >= metadata::getIsaCount()) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + *IsaName = metadata::getIsaName(Index); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_isa_metadata + // + (const char *IsaName, amd_comgr_metadata_node_t *MetadataNode) { + if (!IsaName || !MetadataNode) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + std::unique_ptr MetaP(new (std::nothrow) DataMeta()); + if (!MetaP) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + std::unique_ptr MetaDoc(new (std::nothrow) MetaDocument()); + if (!MetaDoc) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + if (auto Status = metadata::getIsaMetadata(IsaName, MetaDoc->Document)) { + return Status; + } + + MetaP->MetaDoc = std::move(MetaDoc); + MetaP->MetaDoc->EmitIntegerBooleans = true; + MetaP->DocNode = MetaP->MetaDoc->Document.getRoot(); + + *MetadataNode = DataMeta::convert(MetaP.release()); + + return AMD_COMGR_STATUS_SUCCESS; +} + +// API functions on Data Object + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_create_data + // + (amd_comgr_data_kind_t DataKind, amd_comgr_data_t *Data) { + if (!Data || DataKind <= AMD_COMGR_DATA_KIND_UNDEF || + DataKind > AMD_COMGR_DATA_KIND_LAST) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + DataObject *DataP = DataObject::allocate(DataKind); + if (!DataP) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + *Data = DataObject::convert(DataP); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_release_data + // + (amd_comgr_data_t Data) { + DataObject *DataP = DataObject::convert(Data); + + if (!DataP || !DataP->hasValidDataKind()) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + DataP->release(); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_data_kind + // + (amd_comgr_data_t Data, amd_comgr_data_kind_t *DataKind) { + DataObject *DataP = DataObject::convert(Data); + + if (!DataP || !DataP->hasValidDataKind() || !DataKind) { + *DataKind = AMD_COMGR_DATA_KIND_UNDEF; + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + *DataKind = DataP->DataKind; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_set_data + // + (amd_comgr_data_t Data, size_t Size, const char *Bytes) { + DataObject *DataP = DataObject::convert(Data); + + if (!DataP || !DataP->hasValidDataKind() || !Size || !Bytes) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + return DataP->setData(StringRef(Bytes, Size)); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_data + // + (amd_comgr_data_t Data, size_t *Size, char *Bytes) { + DataObject *DataP = DataObject::convert(Data); + + if (!DataP || !DataP->Data || !DataP->hasValidDataKind() || !Size) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (Bytes) { + memcpy(Bytes, DataP->Data, *Size); + } else { + *Size = DataP->Size; + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_set_data_name + // + (amd_comgr_data_t Data, const char *Name) { + DataObject *DataP = DataObject::convert(Data); + + if (!DataP || !DataP->hasValidDataKind()) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + return DataP->setName(Name); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_data_name + // + (amd_comgr_data_t Data, size_t *Size, char *Name) { + DataObject *DataP = DataObject::convert(Data); + + if (!DataP || !DataP->hasValidDataKind() || !Size) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (Name) { + memcpy(Name, DataP->Name, *Size); + } else { + *Size = strlen(DataP->Name) + 1; // include terminating null + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_create_symbolizer_info + // + (amd_comgr_data_t CodeObject, + void (*PrintSymbolCallback)(const char *, void *), + amd_comgr_symbolizer_info_t *SymbolizerInfo) { + + DataObject *CodeObjectP = DataObject::convert(CodeObject); + if (!CodeObjectP || !PrintSymbolCallback || + !(CodeObjectP->DataKind == AMD_COMGR_DATA_KIND_RELOCATABLE || + CodeObjectP->DataKind == AMD_COMGR_DATA_KIND_EXECUTABLE || + CodeObjectP->DataKind == AMD_COMGR_DATA_KIND_BYTES)) + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + + ensureLLVMInitialized(); + + return Symbolizer::create(CodeObjectP, PrintSymbolCallback, SymbolizerInfo); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_destroy_symbolizer_info + // + (amd_comgr_symbolizer_info_t SymbolizerInfo) { + + Symbolizer *SI = Symbolizer::convert(SymbolizerInfo); + if (!SI) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + delete SI; + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_symbolize + // + (amd_comgr_symbolizer_info_t SymbolizeInfo, uint64_t Address, bool IsCode, + void *UserData) { + + Symbolizer *SI = Symbolizer::convert(SymbolizeInfo); + if (!SI || !UserData) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + return SI->symbolize(Address, IsCode, UserData); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_data_isa_name + // + (amd_comgr_data_t Data, size_t *Size, char *IsaName) { + DataObject *DataP = DataObject::convert(Data); + + if (!DataP || !Size || + (DataP->DataKind != AMD_COMGR_DATA_KIND_RELOCATABLE && + DataP->DataKind != AMD_COMGR_DATA_KIND_EXECUTABLE)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + std::string ElfIsaName; + amd_comgr_status_t Status = metadata::getElfIsaName(DataP, ElfIsaName); + + if (Status == AMD_COMGR_STATUS_SUCCESS) { + if (IsaName) { + memcpy(IsaName, ElfIsaName.c_str(), + std::min(*Size, ElfIsaName.size() + 1)); + } + + *Size = ElfIsaName.size() + 1; + } + + return Status; +} + +// API functions on Data Set + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_create_data_set + // + (amd_comgr_data_set_t *Set) { + if (!Set) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + DataSet *SetP = new (std::nothrow) DataSet(); + if (!SetP) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + *Set = DataSet::convert(SetP); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_destroy_data_set + // + (amd_comgr_data_set_t Set) { + DataSet *SetP = DataSet::convert(Set); + + if (!SetP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + delete SetP; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_data_set_add + // + (amd_comgr_data_set_t Set, amd_comgr_data_t Data) { + DataSet *SetP = DataSet::convert(Set); + DataObject *DataP = DataObject::convert(Data); + + if (!SetP || !DataP || !DataP->hasValidDataKind() || !DataP->Name) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + // SmallSetVector: will not add if data was already added + if (SetP->DataObjects.insert(DataP)) { + DataP->RefCount++; + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_data_set_remove + // + (amd_comgr_data_set_t Set, amd_comgr_data_kind_t DataKind) { + DataSet *SetP = DataSet::convert(Set); + + if (!SetP || !isDataKindValid(DataKind)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + SmallVector Tmp = SetP->DataObjects.takeVector(); + + for (DataObject *Data : Tmp) { + if (Data->DataKind == DataKind) { + Data->release(); + } else { + SetP->DataObjects.insert(Data); + } + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_data_count + // + (amd_comgr_data_set_t Set, amd_comgr_data_kind_t DataKind, size_t *Count) { + DataSet *SetP = DataSet::convert(Set); + + if (!SetP || !isDataKindValid(DataKind) || !Count) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + *Count = 0; + for (DataObject *Data : SetP->DataObjects) { + if (Data->DataKind == DataKind) { + *Count += 1; + } + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_data_get_data + // + (amd_comgr_data_set_t Set, amd_comgr_data_kind_t DataKind, size_t Index, + amd_comgr_data_t *Data) { + DataSet *SetP = DataSet::convert(Set); + + if (!SetP || !isDataKindValid(DataKind) || !Data) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + size_t N; + if (auto Status = amd_comgr_action_data_count(Set, DataKind, &N)) { + return Status; + } + if (Index > N) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + N = 0; + for (auto &I : SetP->DataObjects) { + if (I->DataKind == DataKind) { + if (N++ == Index) { + I->RefCount++; + *Data = DataObject::convert(I); + return AMD_COMGR_STATUS_SUCCESS; + } + } + } + + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_create_action_info + // + (amd_comgr_action_info_t *ActionInfo) { + if (!ActionInfo) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + DataAction *ActionP = new (std::nothrow) DataAction(); + if (!ActionP) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + *ActionInfo = DataAction::convert(ActionP); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_destroy_action_info + // + (amd_comgr_action_info_t ActionInfo) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + delete ActionP; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_set_isa_name + // + (amd_comgr_action_info_t ActionInfo, const char *IsaName) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (!IsaName || StringRef(IsaName) == "") { + free(ActionP->IsaName); + ActionP->IsaName = nullptr; + return AMD_COMGR_STATUS_SUCCESS; + } + + if (StringRef(IsaName) == "spir64-amd-amdhsa--amdgcnspirv" || + StringRef(IsaName )== "spir64-amd-amdhsa-unknown-amdgcnspirv") { + return ActionP->setIsaName(IsaName); + } + + if (!metadata::isValidIsaName(IsaName)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + return ActionP->setIsaName(IsaName); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_get_isa_name + // + (amd_comgr_action_info_t ActionInfo, size_t *Size, char *IsaName) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP || !Size) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (IsaName) { + memcpy(IsaName, ActionP->IsaName, *Size); + } else { + *Size = strlen(ActionP->IsaName) + 1; // include terminating null + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_set_language + // + (amd_comgr_action_info_t ActionInfo, amd_comgr_language_t Language) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP || !isLanguageValid(Language)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + ActionP->Language = Language; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_get_language + // + (amd_comgr_action_info_t ActionInfo, amd_comgr_language_t *Language) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP || !Language) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + *Language = ActionP->Language; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_set_option_list + // + (amd_comgr_action_info_t ActionInfo, const char *Options[], size_t Count) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP || (!Options && Count)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + return ActionP->setOptionList(ArrayRef(Options, Count)); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_get_option_list_count + // + (amd_comgr_action_info_t ActionInfo, size_t *Count) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP || !Count) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + return ActionP->getOptionListCount(*Count); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_get_option_list_item + // + (amd_comgr_action_info_t ActionInfo, size_t Index, size_t *Size, + char *Option) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP || !Size) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + StringRef ActionOption; + if (auto Status = ActionP->getOptionListItem(Index, ActionOption)) { + return Status; + } + + if (Option) { + memcpy(Option, ActionOption.data(), *Size); + } else { + *Size = ActionOption.size(); + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_get_bundle_entry_id_count + // + (amd_comgr_action_info_t ActionInfo, size_t *Count) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + *Count = ActionP->getBundleEntryIDs().size(); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_get_bundle_entry_id + // + (amd_comgr_action_info_t ActionInfo, size_t Index, size_t *Size, + char *BundleEntryID) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP || !Size) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + ArrayRef ActionBundleEntryIDs = ActionP->getBundleEntryIDs(); + + if (Index >= ActionBundleEntryIDs.size()) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + // First return the size of the BundleEntryID + if (BundleEntryID == NULL) + *Size = ActionBundleEntryIDs[Index].size() + 1; + + // Now that the calling API has had a chance to allocate memory, copy the + // bundle entry ID at Index to BundleEntryID + else + memcpy(BundleEntryID, ActionBundleEntryIDs[Index].c_str(), *Size); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_set_bundle_entry_ids + // + (amd_comgr_action_info_t ActionInfo, const char *EntryIDs[], size_t Count) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP || (!EntryIDs && Count)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + return ActionP->setBundleEntryIDs(ArrayRef(EntryIDs, Count)); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_set_vfs + // + (amd_comgr_action_info_t ActionInfo, bool ShouldUseVFS) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + ActionP->ShouldUseVFS = ShouldUseVFS; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_set_device_lib_linking + // + (amd_comgr_action_info_t ActionInfo, bool ShouldLinkDeviceLibs) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + ActionP->ShouldLinkDeviceLibs = ShouldLinkDeviceLibs; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_set_working_directory_path + // + (amd_comgr_action_info_t ActionInfo, const char *Path) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + ActionP->setActionPath(Path); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_get_working_directory_path + // + (amd_comgr_action_info_t ActionInfo, size_t *Size, char *Path) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP || !Size) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (Path) { + memcpy(Path, ActionP->Path, *Size); + } else { + *Size = strlen(ActionP->Path) + 1; // include terminating 0 + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_set_logging + // + (amd_comgr_action_info_t ActionInfo, bool Logging) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + ActionP->Logging = Logging; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_action_info_get_logging + // + (amd_comgr_action_info_t ActionInfo, bool *Logging) { + DataAction *ActionP = DataAction::convert(ActionInfo); + + if (!ActionP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + *Logging = ActionP->Logging; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_do_action + // + (amd_comgr_action_kind_t ActionKind, amd_comgr_action_info_t ActionInfo, + amd_comgr_data_set_t InputSet, amd_comgr_data_set_t ResultSet) { + DataAction *ActionInfoP = DataAction::convert(ActionInfo); + DataSet *InputSetP = DataSet::convert(InputSet); + DataSet *ResultSetP = DataSet::convert(ResultSet); + + if (!isActionValid(ActionKind) || !InputSetP || !ResultSetP) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + amd_comgr_status_t ActionStatus; + + // Enclose core Comgr actions in a mutally excusive region to avoid + // multithreading issues stemming from concurrently maintaing multiple + // LLVM instances. + // TODO: Remove the scoped lock once updates to LLVM enable thread saftey + static std::mutex ComgrMutex; + { + std::scoped_lock ComgrLock(ComgrMutex); + + ensureLLVMInitialized(); + + // Save signal handlers so that they can be restored after the action has + // completed. + if (auto Status = signal::saveHandlers()) { + return Status; + } + + // The normal log stream, used to return via a AMD_COMGR_DATA_KIND_LOG + // object. + std::string LogStr; + std::string PerfLog = "PerfStatsLog.txt"; + raw_string_ostream LogS(LogStr); + + // The log stream when redirecting to a file. + std::unique_ptr LogF; + + // Pointer to the currently selected log stream. + raw_ostream *LogP = &LogS; + + if (std::optional RedirectLogs = env::getRedirectLogs()) { + StringRef RedirectLog = *RedirectLogs; + if (RedirectLog == "stdout") { + LogP = &outs(); + } else if (RedirectLog == "stderr") { + LogP = &errs(); + } else { + std::error_code EC; + LogF.reset(new (std::nothrow) raw_fd_ostream( + RedirectLog, EC, sys::fs::OF_Text | sys::fs::OF_Append)); + if (EC) { + LogF.reset(); + *LogP << "Comgr unable to redirect log to file '" << RedirectLog + << "': " << EC.message() << "\n"; + } else { + LogP = LogF.get(); + PerfLog = RedirectLog.str(); + } + } + } + + InitTimeStatistics(PerfLog); + + if (env::shouldEmitVerboseLogs()) { + *LogP << "amd_comgr_do_action:\n" + << "\t ActionKind: " << getActionKindName(ActionKind) << '\n' + << "\t IsaName: " << ActionInfoP->IsaName << '\n' + << "\t Options:"; + for (auto &Option : ActionInfoP->getOptions()) { + *LogP << ' '; + printQuotedOption(*LogP, Option); + } + *LogP << '\n' + << "\t Path: " << ActionInfoP->Path << '\n' + << "\t Language: " << getLanguageName(ActionInfoP->Language) + << '\n' + << " Comgr Branch-Commit: " << xstringify(AMD_COMGR_GIT_BRANCH) + << '-' << xstringify(AMD_COMGR_GIT_COMMIT) << '\n' + << "\t LLVM Commit: " << clang::getLLVMRevision() << '\n'; + (*LogP).flush(); + } + + ProfilePoint ProfileAction(getActionKindName(ActionKind)); + switch (ActionKind) { + case AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR: + case AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC: + case AMD_COMGR_ACTION_UNBUNDLE: + case AMD_COMGR_ACTION_LINK_BC_TO_BC: + case AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE: + case AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY: + case AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE: + case AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE: + case AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE: + case AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE: + case AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC: + case AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE: + case AMD_COMGR_ACTION_COMPILE_SPIRV_TO_RELOCATABLE: + case AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC: + ActionStatus = dispatchCompilerAction(ActionKind, ActionInfoP, InputSetP, + ResultSetP, *LogP); + break; + case AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS: + // Redirect the input to the output. + // Deprecate and remove this action. + for (DataObject *Data : InputSetP->DataObjects) { + Data->RefCount++; + ResultSetP->DataObjects.insert(Data); + } + ActionStatus = AMD_COMGR_STATUS_SUCCESS; + break; + default: + ActionStatus = AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + ProfileAction.finish(); + + // Restore signal handlers. + if (auto Status = signal::restoreHandlers()) { + return Status; + } + + if (env::shouldEmitVerboseLogs()) { + *LogP << "\tReturnStatus: " << getStatusName(ActionStatus) << "\n\n"; + } + + if (ActionInfoP->Logging) { + amd_comgr_data_t LogT; + if (auto Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_LOG, &LogT)) { + return Status; + } + ScopedDataObjectReleaser LogSDOR(LogT); + DataObject *Log = DataObject::convert(LogT); + if (auto Status = Log->setName("comgr.log")) { + return Status; + } + if (auto Status = Log->setData(LogS.str())) { + return Status; + } + if (auto Status = amd_comgr_data_set_add(ResultSet, LogT)) { + return Status; + } + } + } // exit scoped_lock region + + return ActionStatus; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_data_metadata + // + (amd_comgr_data_t Data, amd_comgr_metadata_node_t *MetadataNode) { + DataObject *DataP = DataObject::convert(Data); + + if (!DataP || !DataP->hasValidDataKind() || + DataP->DataKind == AMD_COMGR_DATA_KIND_UNDEF || !MetadataNode) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + std::unique_ptr MetaP(new (std::nothrow) DataMeta()); + if (!MetaP) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + MetaDocument *MetaDoc = new (std::nothrow) MetaDocument(); + if (!MetaDoc) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + MetaP->MetaDoc.reset(MetaDoc); + MetaP->DocNode = MetaP->MetaDoc->Document.getRoot(); + + if (auto Status = metadata::getMetadataRoot(DataP, MetaP.get())) { + return Status; + } + + // if no metadata found in this data object, still return SUCCESS but + // with default NULL kind + + *MetadataNode = DataMeta::convert(MetaP.release()); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_destroy_metadata + // + (amd_comgr_metadata_node_t MetadataNode) { + DataMeta *MetaP = DataMeta::convert(MetadataNode); + delete MetaP; + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_metadata_kind + // + (amd_comgr_metadata_node_t MetadataNode, + amd_comgr_metadata_kind_t *MetadataKind) { + DataMeta *MetaP = DataMeta::convert(MetadataNode); + + if (!MetadataKind) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + *MetadataKind = MetaP->getMetadataKind(); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_metadata_string + // + (amd_comgr_metadata_node_t MetadataNode, size_t *Size, char *String) { + DataMeta *MetaP = DataMeta::convert(MetadataNode); + + if (MetaP->getMetadataKind() != AMD_COMGR_METADATA_KIND_STRING || !Size) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + std::string Str = MetaP->convertDocNodeToString(MetaP->DocNode); + + if (String) { + memcpy(String, Str.c_str(), *Size); + } else { + *Size = Str.size() + 1; + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_metadata_map_size + // + (amd_comgr_metadata_node_t MetadataNode, size_t *Size) { + DataMeta *MetaP = DataMeta::convert(MetadataNode); + + if (MetaP->getMetadataKind() != AMD_COMGR_METADATA_KIND_MAP || !Size) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + *Size = MetaP->DocNode.getMap().size(); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_iterate_map_metadata + // + (amd_comgr_metadata_node_t MetadataNode, + amd_comgr_status_t (*Callback)(amd_comgr_metadata_node_t, + amd_comgr_metadata_node_t, void *), + void *UserData) { + DataMeta *MetaP = DataMeta::convert(MetadataNode); + + if (MetaP->getMetadataKind() != AMD_COMGR_METADATA_KIND_MAP || !Callback) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + auto Map = MetaP->DocNode.getMap(); + + for (auto &KV : Map) { + if (KV.first.isEmpty() || KV.second.isEmpty()) { + return AMD_COMGR_STATUS_ERROR; + } + std::unique_ptr KeyP(new (std::nothrow) DataMeta()); + std::unique_ptr ValueP(new (std::nothrow) DataMeta()); + if (!KeyP || !ValueP) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + KeyP->MetaDoc = MetaP->MetaDoc; + KeyP->DocNode = KV.first; + ValueP->MetaDoc = MetaP->MetaDoc; + ValueP->DocNode = KV.second; + (*Callback)(DataMeta::convert(KeyP.get()), DataMeta::convert(ValueP.get()), + UserData); + } + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_metadata_lookup + // + (amd_comgr_metadata_node_t MetadataNode, const char *Key, + amd_comgr_metadata_node_t *Value) { + DataMeta *MetaP = DataMeta::convert(MetadataNode); + + if (MetaP->getMetadataKind() != AMD_COMGR_METADATA_KIND_MAP || !Key || + !Value) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + for (auto Iter : MetaP->DocNode.getMap()) { + if (!Iter.first.isScalar() || + StringRef(Key) != MetaP->convertDocNodeToString(Iter.first)) { + continue; + } + + DataMeta *NewMetaP = new (std::nothrow) DataMeta(); + if (!NewMetaP) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + NewMetaP->MetaDoc = MetaP->MetaDoc; + NewMetaP->DocNode = Iter.second; + *Value = DataMeta::convert(NewMetaP); + + return AMD_COMGR_STATUS_SUCCESS; + } + + return AMD_COMGR_STATUS_ERROR; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_get_metadata_list_size + // + (amd_comgr_metadata_node_t MetadataNode, size_t *Size) { + DataMeta *MetaP = DataMeta::convert(MetadataNode); + + if (MetaP->getMetadataKind() != AMD_COMGR_METADATA_KIND_LIST || !Size) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + *Size = MetaP->DocNode.getArray().size(); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_index_list_metadata + // + (amd_comgr_metadata_node_t MetadataNode, size_t Index, + amd_comgr_metadata_node_t *Value) { + DataMeta *MetaP = DataMeta::convert(MetadataNode); + + if (MetaP->getMetadataKind() != AMD_COMGR_METADATA_KIND_LIST || !Value) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + auto List = MetaP->DocNode.getArray(); + + if (Index >= List.size()) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + DataMeta *NewMetaP = new (std::nothrow) DataMeta(); + if (!NewMetaP) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + NewMetaP->MetaDoc = MetaP->MetaDoc; + NewMetaP->DocNode = List[Index]; + *Value = DataMeta::convert(NewMetaP); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_iterate_symbols + // + (amd_comgr_data_t Data, + amd_comgr_status_t (*Callback)(amd_comgr_symbol_t, void *), + void *UserData) { + SymbolHelper Helper; + DataObject *DataP = DataObject::convert(Data); + + if (!DataP || !DataP->hasValidDataKind() || + !(DataP->DataKind == AMD_COMGR_DATA_KIND_RELOCATABLE || + DataP->DataKind == AMD_COMGR_DATA_KIND_EXECUTABLE) || + !Callback) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + ensureLLVMInitialized(); + + StringRef Ins(DataP->Data, DataP->Size); + return Helper.iterateTable(Ins, DataP->DataKind, Callback, UserData); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_symbol_lookup + // + (amd_comgr_data_t Data, const char *Name, amd_comgr_symbol_t *Symbol) { + DataObject *DataP = DataObject::convert(Data); + SymbolHelper Helper; + + if (!DataP || !DataP->hasValidDataKind() || + !(DataP->DataKind == AMD_COMGR_DATA_KIND_RELOCATABLE || + DataP->DataKind == AMD_COMGR_DATA_KIND_EXECUTABLE)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + ensureLLVMInitialized(); + + // look through the symbol table for a symbol name based + // on the data object. + + StringRef Ins(DataP->Data, DataP->Size); + SymbolContext *Sym = Helper.createBinary(Ins, Name, DataP->DataKind); + if (!Sym) { + return AMD_COMGR_STATUS_ERROR; + } + + DataSymbol *SymP = new (std::nothrow) DataSymbol(Sym); + if (!SymP) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + *Symbol = DataSymbol::convert(SymP); + + // Update the symbol field in the data object + delete DataP->DataSym; + DataP->DataSym = SymP; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_symbol_get_info + // + (amd_comgr_symbol_t Symbol, amd_comgr_symbol_info_t SymbolInfo, + void *Value) { + DataSymbol *SymP = DataSymbol::convert(Symbol); + + if (!Value || !isSymbolInfoValid(SymbolInfo) || !SymP->DataSym) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + SymbolContext *Sym = SymP->DataSym; + + switch (SymbolInfo) { + case AMD_COMGR_SYMBOL_INFO_NAME_LENGTH: + *(size_t *)Value = strlen(Sym->Name); + return AMD_COMGR_STATUS_SUCCESS; + case AMD_COMGR_SYMBOL_INFO_NAME: + strcpy((char *)Value, Sym->Name); + return AMD_COMGR_STATUS_SUCCESS; + case AMD_COMGR_SYMBOL_INFO_TYPE: + *(amd_comgr_symbol_type_t *)Value = Sym->Type; + return AMD_COMGR_STATUS_SUCCESS; + case AMD_COMGR_SYMBOL_INFO_SIZE: + *(uint64_t *)Value = Sym->Size; + return AMD_COMGR_STATUS_SUCCESS; + case AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED: + *(bool *)Value = Sym->Undefined; + return AMD_COMGR_STATUS_SUCCESS; + case AMD_COMGR_SYMBOL_INFO_VALUE: + *(uint64_t *)Value = Sym->Value; + return AMD_COMGR_STATUS_SUCCESS; + } + + llvm_unreachable("invalid symbol info"); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_create_disassembly_info + // + (const char *IsaName, + uint64_t (*ReadMemoryCallback)(uint64_t, char *, uint64_t, void *), + void (*PrintInstructionCallback)(const char *, void *), + void (*PrintAddressAnnotationCallback)(uint64_t, void *), + amd_comgr_disassembly_info_t *DisasmInfo) { + + if (!IsaName || !metadata::isValidIsaName(IsaName) || !ReadMemoryCallback || + !PrintInstructionCallback || !PrintAddressAnnotationCallback || + !DisasmInfo) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + TargetIdentifier Ident; + if (auto Status = parseTargetIdentifier(IsaName, Ident)) { + return Status; + } + + ensureLLVMInitialized(); + + return DisassemblyInfo::create(Ident, ReadMemoryCallback, + PrintInstructionCallback, + PrintAddressAnnotationCallback, DisasmInfo); +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_destroy_disassembly_info + // + (amd_comgr_disassembly_info_t DisasmInfo) { + + DisassemblyInfo *DI = DisassemblyInfo::convert(DisasmInfo); + + if (!DI) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + delete DI; + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_disassemble_instruction + // + (amd_comgr_disassembly_info_t DisasmInfo, uint64_t Address, void *UserData, + uint64_t *Size) { + + DisassemblyInfo *DI = DisassemblyInfo::convert(DisasmInfo); + if (!DI || !Size) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + return DI->disassembleInstruction(Address, UserData, *Size); +} + +amd_comgr_status_t AMD_COMGR_API +// NOLINTNEXTLINE(readability-identifier-naming) +amd_comgr_demangle_symbol_name(amd_comgr_data_t MangledSymbolName, + amd_comgr_data_t *DemangledSymbolName) { + DataObject *DataP = DataObject::convert(MangledSymbolName); + if (!DataP || !DataP->Data || DataP->DataKind != AMD_COMGR_DATA_KIND_BYTES || + !DemangledSymbolName) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + DataObject *DemangledDataP = DataObject::allocate(AMD_COMGR_DATA_KIND_BYTES); + if (!DemangledDataP) { + return AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES; + } + + DemangledDataP->setData( + llvm::demangle(std::string(DataP->Data, DataP->Size))); + *DemangledSymbolName = DataObject::convert(DemangledDataP); + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API +// NOLINTNEXTLINE(readability-identifier-naming) +amd_comgr_populate_mangled_names(amd_comgr_data_t Data, size_t *Count) { + DataObject *DataP = DataObject::convert(Data); + if (!DataP || !DataP->Data || + (DataP->DataKind != AMD_COMGR_DATA_KIND_BC && + DataP->DataKind != AMD_COMGR_DATA_KIND_EXECUTABLE)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + DataP->MangledNames.clear(); + + LLVMContext Context; + + if (DataP->DataKind == AMD_COMGR_DATA_KIND_BC) { + + MemoryBufferRef BcMemBufRef = MemoryBufferRef( + StringRef(DataP->Data, DataP->Size), StringRef(DataP->Name)); + + auto BcModVecOrErr = getBitcodeModuleList(BcMemBufRef); + if (!BcModVecOrErr) { + llvm::logAllUnhandledErrors(BcModVecOrErr.takeError(), llvm::errs(), + "Bitcode Contents error: "); + return AMD_COMGR_STATUS_ERROR; + } + + std::vector BcModVec = BcModVecOrErr.get(); + for (BitcodeModule BcMod : BcModVec) { + + Expected> ModOrError = + BcMod.getLazyModule(Context, true, true); + if (!ModOrError) { + llvm::logAllUnhandledErrors(ModOrError.takeError(), llvm::errs(), + "Bitcode Contents error: "); + return AMD_COMGR_STATUS_ERROR; + } + + std::unique_ptr M = std::move(ModOrError.get()); + for (llvm::GlobalVariable &GlobalVar : M->globals()) + DataP->MangledNames.push_back(GlobalVar.getName().str()); + for (llvm::Function &Function : M->getFunctionList()) + DataP->MangledNames.push_back(Function.getName().str()); + } + } + + if (DataP->DataKind == AMD_COMGR_DATA_KIND_EXECUTABLE) { + // Callback to iterate_symbols that error checks and appends lowered names + // to "data" + auto Callback = [](amd_comgr_symbol_t Symbol, void *Data) { + size_t Len = 0; + if (auto Res = amd_comgr_symbol_get_info( + Symbol, AMD_COMGR_SYMBOL_INFO_NAME_LENGTH, &Len); + Res != AMD_COMGR_STATUS_SUCCESS) + return Res; + std::string Name(Len, 0); + if (auto Res = amd_comgr_symbol_get_info( + Symbol, AMD_COMGR_SYMBOL_INFO_NAME, &Name[0]); + Res != AMD_COMGR_STATUS_SUCCESS) + return Res; + auto *Rv = reinterpret_cast *>(Data); + Rv->push_back(Name); + return AMD_COMGR_STATUS_SUCCESS; + }; + + if (auto Res = amd_comgr_iterate_symbols( + Data, Callback, reinterpret_cast(&(DataP->MangledNames))); + Res != AMD_COMGR_STATUS_SUCCESS) { + return AMD_COMGR_STATUS_ERROR; + } + } + + *Count = DataP->MangledNames.size(); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API +// NOLINTNEXTLINE(readability-identifier-naming) +amd_comgr_get_mangled_name(amd_comgr_data_t Data, size_t Index, size_t *Size, + char *MangledName) { + DataObject *DataP = DataObject::convert(Data); + if (!DataP || !DataP->Data || + (DataP->DataKind != AMD_COMGR_DATA_KIND_BC && + DataP->DataKind != AMD_COMGR_DATA_KIND_EXECUTABLE)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (Index >= DataP->MangledNames.size()) + return AMD_COMGR_STATUS_ERROR; + + if (MangledName == NULL) + *Size = DataP->MangledNames[Index].size() + 1; + else + memcpy(MangledName, DataP->MangledNames[Index].c_str(), *Size); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API +// NOLINTNEXTLINE(readability-identifier-naming) +amd_comgr_populate_name_expression_map(amd_comgr_data_t Data, size_t *Count) { + + DataObject *DataP = DataObject::convert(Data); + if (!DataP || !DataP->Data || + (DataP->DataKind != AMD_COMGR_DATA_KIND_BC && + DataP->DataKind != AMD_COMGR_DATA_KIND_EXECUTABLE)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + DataP->NameExpressionMap.clear(); + LLVMContext Context; + + // For bitcodes, the name expression and function pointer can be found by + // creating a bitcode module data structure, and searching through the + // initalizers of global variables + if (DataP->DataKind == AMD_COMGR_DATA_KIND_BC) { + + MemoryBufferRef BcMemBufRef = MemoryBufferRef( + StringRef(DataP->Data, DataP->Size), StringRef(DataP->Name)); + + auto BcModVecOrErr = getBitcodeModuleList(BcMemBufRef); + if (!BcModVecOrErr) { + llvm::logAllUnhandledErrors(BcModVecOrErr.takeError(), llvm::errs(), + "Bitcode Contents error: "); + return AMD_COMGR_STATUS_ERROR; + } + + std::vector BcModVec = BcModVecOrErr.get(); + for (BitcodeModule BcMod : BcModVec) { + + Expected> ModOrError = + BcMod.getLazyModule(Context, true, true); + if (!ModOrError) { + llvm::logAllUnhandledErrors(ModOrError.takeError(), llvm::errs(), + "Bitcode Contents error: "); + return AMD_COMGR_STATUS_ERROR; + } + + // Collect initial values of all global variables starting with + // `__amdgcn_name_expr_`. + std::unique_ptr M = std::move(ModOrError.get()); + for (llvm::GlobalVariable &GlobalVar : M->globals()) { + if (GlobalVar.getName().contains("__amdgcn_name_expr_")) { + + std::string MapKey, MapVal; + + // 1. use getInitalizer() to get a pointer to [2xi8*] + auto *Initalizer = GlobalVar.getInitializer(); + + // 2. Get NameExpression map value from second operand name + MapVal = Initalizer->getOperand(1)->getName().str(); + + // 3 Get NameExpression map key from first operand + llvm::Value *V = Initalizer->getOperand(0); + + // Cast initalizer operand 0 to ConstantExpr + if (const ConstantExpr *CE = dyn_cast(V)) { + // Cast ConstantExpr operand 0 to GlobalVaribale + if (llvm::GlobalVariable *GV = + dyn_cast(CE->getOperand(0))) { + // Cast GlobalVariable initializer to ConstantDataSequential + if (ConstantDataSequential *CDS = + dyn_cast(GV->getInitializer())) { + + MapKey = CDS->getAsString().str(); + } + } + } + + MapKey.erase(std::find(MapKey.begin(), MapKey.end(), '\0'), + MapKey.end()); + MapVal.erase(std::find(MapVal.begin(), MapVal.end(), '\0'), + MapVal.end()); + if (env::shouldEmitVerboseLogs()) { + llvm::errs() << " Comgr NameExpressionMap[" << MapKey + << "] = " << MapVal << "\n"; + } + DataP->NameExpressionMap[MapKey] = MapVal; + } + } // end M->globals() loop + } // end BcModVec loop + } // end AMD_COMGR_DATA_KIND_BC conditional + + // For code objects, we can get the needed information by creating an ELF + // object and traversing the .dynsym, .rela.dyn, and .rodata sections. + if (DataP->DataKind == AMD_COMGR_DATA_KIND_EXECUTABLE) { + auto ELFFileOrError = + llvm::object::ELF64LEFile::create(StringRef(DataP->Data, DataP->Size)); + if (!ELFFileOrError) { + llvm::logAllUnhandledErrors(ELFFileOrError.takeError(), llvm::errs(), + "ELFObj creation error: "); + return AMD_COMGR_STATUS_ERROR; + } + auto ELFFile = std::move(ELFFileOrError.get()); + + std::vector NameExpDataVec; + std::map DynsymMap; + + // Collect references for .dynsym, .rela.dyn, and .rodata sections + auto SectionsOrError = ELFFile.sections(); + if (!SectionsOrError) { + llvm::logAllUnhandledErrors(SectionsOrError.takeError(), llvm::errs(), + "Sections creation error: "); + return AMD_COMGR_STATUS_ERROR; + } + auto Sections = std::move(SectionsOrError.get()); + + Elf_Shdr_Impl DynsymShdr, RelaShdr, RodataShdr; + for (auto Shdr : Sections) { + + if (Shdr.sh_type == ELF::SHT_DYNSYM) + DynsymShdr = Shdr; + + // Check sh_info to differentiate .rela.dyn and not .rela + if (Shdr.sh_type == ELF::SHT_RELA && Shdr.sh_info == 0) + RelaShdr = Shdr; + + // We can't uniquely identify the .rodata section using the type and flag + // because other sections may use the exact same flags and type (i.e. + // .interp). For correctness, we can check the name instead + if (Shdr.sh_type == ELF::SHT_PROGBITS && + (Shdr.sh_flags & ELF::SHF_ALLOC)) { + + Expected SecNameOrError = ELFFile.getSectionName(Shdr); + if (!SecNameOrError) { + llvm::logAllUnhandledErrors(SecNameOrError.takeError(), llvm::errs(), + "ELFObj creation error: "); + return AMD_COMGR_STATUS_ERROR; + } + StringRef SecName = std::move(SecNameOrError.get()); + + if (SecName == StringRef(".rodata")) + RodataShdr = Shdr; + } + } + + // .dynsym - Find name expressions with amdgcn_name_expr and store their + // Value fields + Expected StrTabOrError = + ELFFile.getStringTableForSymtab(DynsymShdr); + if (!StrTabOrError) { + llvm::logAllUnhandledErrors(StrTabOrError.takeError(), llvm::errs(), + "StrTab creation error: "); + return AMD_COMGR_STATUS_ERROR; + } + StringRef StrTab = std::move(StrTabOrError.get()); + + // Check each .dynsym entry + for (unsigned int I = 0; I < DynsymShdr.getEntityCount(); ++I) { + + // Get symbol from entry + auto SymbolOrError = ELFFile.getSymbol(&DynsymShdr, I); + if (!SymbolOrError) { + llvm::logAllUnhandledErrors(SymbolOrError.takeError(), llvm::errs(), + "Symbol creation error: "); + return AMD_COMGR_STATUS_ERROR; + } + const auto *Symbol = std::move(SymbolOrError.get()); + + // Get symbol name from symbol + Expected SymbolNameOrError = Symbol->getName(StrTab); + if (!SymbolNameOrError) { + llvm::logAllUnhandledErrors(SymbolNameOrError.takeError(), llvm::errs(), + "SymbolName creation error: "); + return AMD_COMGR_STATUS_ERROR; + } + StringRef SymbolName = std::move(SymbolNameOrError.get()); + + // Process symbol names containing amdgcn_name_expr + if (SymbolName.contains(StringRef("__amdgcn_name_expr_"))) { + struct NameExpressionData *ExpData = new NameExpressionData(); + ExpData->StubName = SymbolName; + ExpData->StubValue = Symbol->getValue(); + NameExpDataVec.push_back(ExpData); + } + + // Store all symbols to later quickly find mangled name + DynsymMap[Symbol->getValue()] = SymbolName; + } // end entry loop + + // .rela.dyn - Use Values collected from .dynsym + // Offset == Value: Store 'Symbol's Name + Addend' + // - needed to get unmangled name from .rodata + // Offset == Value + 8: Store 'Symbol's Name + Addend' + // - needed to get mangled name from .dynsym + auto RelaRangeOrError = ELFFile.relas(RelaShdr); + if (!RelaRangeOrError) { + llvm::logAllUnhandledErrors(RelaRangeOrError.takeError(), llvm::errs(), + "RelaRange creation error: "); + for (auto *Ptr : NameExpDataVec) + delete Ptr; + return AMD_COMGR_STATUS_ERROR; + } + auto RelaRange = std::move(RelaRangeOrError.get()); + + for (auto Rela : RelaRange) { + for (auto *ExpData : NameExpDataVec) { + if (Rela.r_offset == ExpData->StubValue) + ExpData->RodataOffset = Rela.r_addend; + + if (Rela.r_offset == ExpData->StubValue + 8) + ExpData->MangledValue = Rela.r_addend; + } + } + + // rodata - Use the difference between the .rela.dyn Names and .rodata + // offset to collect unmangled strings + auto RodataOrError = ELFFile.getSectionContents(RodataShdr); + if (!RodataOrError) { + llvm::logAllUnhandledErrors(RodataOrError.takeError(), llvm::errs(), + "Rodata creation error: "); + for (auto *Ptr : NameExpDataVec) + delete Ptr; + return AMD_COMGR_STATUS_ERROR; + } + auto Rodata = std::move(RodataOrError.get()); + + // Collect an unmangled name for each name expression + for (auto *ExpData : NameExpDataVec) { + // TODO: If/when an accessor API becomes available to get the starting + // address for the section, switch to that + size_t Offset = ExpData->RodataOffset - RodataShdr.sh_offset; + + // Store from the offset up until the first '\0' + const char *Unmangled = reinterpret_cast(&Rodata[Offset]); + ExpData->UnmangledName = StringRef(Unmangled); + } + + // Populate mangled names now that mangled values are set + for (auto *ExpData : NameExpDataVec) + ExpData->MangledName = DynsymMap[ExpData->MangledValue]; + + // Populate map + for (auto *ExpData : NameExpDataVec) { + DataP->NameExpressionMap[ExpData->UnmangledName.str()] = + ExpData->MangledName.str(); + + if (env::shouldEmitVerboseLogs()) { + llvm::errs() << " Comgr NameExpressionMap[" << ExpData->UnmangledName + << "] = " << ExpData->MangledName << "\n"; + } + } + + for (auto *Ptr : NameExpDataVec) + delete Ptr; + } // end AMD_COMGR_DATA_KIND_EXECUTABLE conditional + + *Count = DataP->NameExpressionMap.size(); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API +// NOLINTNEXTLINE(readability-identifier-naming) +amd_comgr_map_name_expression_to_symbol_name(amd_comgr_data_t Data, + size_t *Size, + const char *NameExpression, + char *SymbolName) { + DataObject *DataP = DataObject::convert(Data); + if (!DataP || !DataP->Data || + (DataP->DataKind != AMD_COMGR_DATA_KIND_BC && + DataP->DataKind != AMD_COMGR_DATA_KIND_EXECUTABLE)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + // Check if the provided NameExpression is in the map + std::string NameExpStr(NameExpression); + if (DataP->NameExpressionMap.find(NameExpStr) == + DataP->NameExpressionMap.end()) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + // First return the size of the SymbolName + if (SymbolName == NULL) + *Size = DataP->NameExpressionMap[NameExpression].size() + 1; + + // Now that the calling API has had a chance to allocate memory, copy the + // symbol name associated with the provided name expression to the provided + // buffer. + else + memcpy(SymbolName, DataP->NameExpressionMap[NameExpression].c_str(), *Size); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_set_data_from_file_slice + // + (amd_comgr_data_t Data, int FD, uint64_t Offset, uint64_t Size) { + DataObject *DataP = DataObject::convert(Data); + if (!DataP || !DataP->hasValidDataKind()) + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + + auto FileHandle = sys::fs::convertFDToNativeFile(FD); + auto BufferOrErr = MemoryBuffer::getOpenFileSlice( + FileHandle, "" /* Name not set */, Size, Offset); + if (BufferOrErr.getError()) { + return AMD_COMGR_STATUS_ERROR; + } + + DataP->setData(std::move(*BufferOrErr)); + + return AMD_COMGR_STATUS_SUCCESS; +} + +amd_comgr_status_t AMD_COMGR_API + // NOLINTNEXTLINE(readability-identifier-naming) + amd_comgr_lookup_code_object + // + (amd_comgr_data_t Data, amd_comgr_code_object_info_t *QueryList, + size_t QueryListSize) { + DataObject *DataP = DataObject::convert(Data); + + if (!DataP || !DataP->hasValidDataKind() || + !(DataP->DataKind == AMD_COMGR_DATA_KIND_FATBIN || + DataP->DataKind == AMD_COMGR_DATA_KIND_BYTES || + DataP->DataKind == AMD_COMGR_DATA_KIND_EXECUTABLE)) + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + + if (!QueryList) + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + + return metadata::lookUpCodeObject(DataP, QueryList, QueryListSize); +} + +amd_comgr_status_t AMD_COMGR_API +// NOLINTNEXTLINE(readability-identifier-naming) +amd_comgr_map_elf_virtual_address_to_code_object_offset( + amd_comgr_data_t Data, uint64_t ElfVirtualAddress, + uint64_t *CodeObjectOffset, uint64_t *SliceSize, bool *Nobits) { + + DataObject *DataP = DataObject::convert(Data); + if (!DataP || !DataP->Data || + (DataP->DataKind != AMD_COMGR_DATA_KIND_EXECUTABLE)) { + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; + } + + // Create ELF Object file + auto ELFFileOrError = + llvm::object::ELF64LEFile::create(StringRef(DataP->Data, DataP->Size)); + if (!ELFFileOrError) { + llvm::logAllUnhandledErrors(ELFFileOrError.takeError(), llvm::errs(), + "ELFObj creation error: "); + return AMD_COMGR_STATUS_ERROR; + } + auto ELFFile = std::move(ELFFileOrError.get()); + + // Error check the ELF file + auto ELFHeader = ELFFile.getHeader(); + if (!ELFHeader.checkMagic()) + return AMD_COMGR_STATUS_ERROR; + + if (ELFHeader.e_ident[llvm::ELF::EI_CLASS] != llvm::ELF::ELFCLASS64 || + ELFHeader.e_ident[llvm::ELF::EI_DATA] != llvm::ELF::ELFDATA2LSB || + ELFHeader.e_ident[llvm::ELF::EI_VERSION] != llvm::ELF::EV_CURRENT || + ELFHeader.e_ident[llvm::ELF::EI_OSABI] != llvm::ELF::ELFOSABI_AMDGPU_HSA) + return AMD_COMGR_STATUS_ERROR; + + unsigned EIdent = ELFHeader.e_ident[llvm::ELF::EI_ABIVERSION]; + if (EIdent != llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4 && + EIdent != llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5 && + EIdent != llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6) + return AMD_COMGR_STATUS_ERROR; + + if (ELFHeader.e_type != llvm::ELF::ET_DYN || + ELFHeader.e_machine != llvm::ELF::EM_AMDGPU || ELFHeader.e_phoff == 0) + return AMD_COMGR_STATUS_ERROR; + + // Access program headers + auto ProgHeadersOrError = ELFFile.program_headers(); + if (!ProgHeadersOrError) { + llvm::logAllUnhandledErrors(ProgHeadersOrError.takeError(), llvm::errs(), + "ProgHeaders creation error: "); + return AMD_COMGR_STATUS_ERROR; + } + auto ProgHeaders = std::move(ProgHeadersOrError.get()); + + for (auto Phdr : ProgHeaders) { + + // Check if ELF virtual address defined in this header + if (Phdr.p_type == llvm::ELF::PT_LOAD && + ElfVirtualAddress >= Phdr.p_vaddr && + ElfVirtualAddress < Phdr.p_vaddr + Phdr.p_memsz) { + + *CodeObjectOffset = ElfVirtualAddress - Phdr.p_vaddr + Phdr.p_offset; + *Nobits = ElfVirtualAddress - Phdr.p_vaddr >= Phdr.p_filesz; + + if (*Nobits) // end of segment to relative address difference + *SliceSize = Phdr.p_filesz - (ElfVirtualAddress - Phdr.p_vaddr); + else // end of valid memory to relative address difference + *SliceSize = Phdr.p_memsz - (ElfVirtualAddress - Phdr.p_vaddr); + + return AMD_COMGR_STATUS_SUCCESS; + } + } + + // If the provided ELF virtual address is not mapped to an offset + return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT; +} diff --git a/amd/comgr/src/comgr.h b/amd/comgr/src/comgr.h new file mode 100644 index 0000000000000..e419a46baf6d5 --- /dev/null +++ b/amd/comgr/src/comgr.h @@ -0,0 +1,299 @@ +//===- comgr.h - User-facing APIs -----------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_DATA_H_ +#define COMGR_DATA_H_ + +#include "amd_comgr.h" +#include "comgr-symbol.h" +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/BinaryFormat/MsgPackDocument.h" +#include "llvm/Object/ObjectFile.h" + +namespace COMGR { +struct DataMeta; +struct DataSymbol; + +/// Update @p Dest to point to a newly allocated C-style (null terminated) +/// string with the contents of @p Src, optionally updating @p Size with the +/// length of the string (not including the null terminator). +/// +/// If @p Dest is non-null, it will first be freed. +/// +/// @p Src may contain null bytes. +amd_comgr_status_t setCStr(char *&Dest, llvm::StringRef Src, + size_t *Size = nullptr); + +/// Components of a "Code Object Target Identification" string. +/// +/// See https://llvm.org/docs/AMDGPUUsage.html#code-object-target-identification +/// for details. +struct TargetIdentifier { + llvm::StringRef Arch; + llvm::StringRef Vendor; + llvm::StringRef OS; + llvm::StringRef Environ; + llvm::StringRef Processor; + llvm::SmallVector Features; +}; + +/// Parse a "Code Object Target Identification" string into it's components. +/// +/// See https://llvm.org/docs/AMDGPUUsage.html#code-object-target-identification +/// for details. +/// +/// @param IdentStr [in] The string to parse. +/// @param Ident [out] The components of the identification string. +amd_comgr_status_t parseTargetIdentifier(llvm::StringRef IdentStr, + TargetIdentifier &Ident); + +/// Ensure all required LLVM initialization functions have been invoked at least +/// once in this process. +void ensureLLVMInitialized(); + +/// Reset all `llvm::cl` options to their default values. +void clearLLVMOptions(); + +/// Return `true` if the kind is valid, or false otherwise. +bool isDataKindValid(amd_comgr_data_kind_t DataKind); + +struct DataObject { + + // Allocate a new DataObject and return a pointer to it. + static DataObject *allocate(amd_comgr_data_kind_t DataKind); + + // Decrement the refcount of this DataObject, and free it when it reaches 0. + void release(); + + static amd_comgr_data_t convert(DataObject *Data) { + amd_comgr_data_t Handle = { + static_cast(reinterpret_cast(Data))}; + return Handle; + } + + static const amd_comgr_data_t convert(const DataObject *Data) { + const amd_comgr_data_t Handle = { + static_cast(reinterpret_cast(Data))}; + return Handle; + } + + static DataObject *convert(amd_comgr_data_t Data) { + return reinterpret_cast(Data.handle); + } + + bool hasValidDataKind() { return isDataKindValid(DataKind); } + + amd_comgr_status_t setName(llvm::StringRef Name); + amd_comgr_status_t setData(llvm::StringRef Data); + amd_comgr_status_t setData(std::unique_ptr Buffer); + + void setMetadata(DataMeta *Metadata); + + amd_comgr_data_kind_t DataKind; + char *Data; + char *Name; + size_t Size; + int RefCount; + DataSymbol *DataSym; + std::vector MangledNames; + std::map NameExpressionMap; + llvm::SmallVector SpirvFlags; + +private: + std::unique_ptr Buffer; + + void clearData(); + // We require this type be allocated via new, specifically through calling + // allocate, because we want to be able to `delete this` in release. To make + // sure the type is not constructed without new, or destructed without + // checking the reference count, we mark the constructor and destructor + // private. + DataObject(amd_comgr_data_kind_t Kind); + ~DataObject(); +}; + +/// Should be used to ensure references to transient data objects are properly +/// released when they go out of scope. +class ScopedDataObjectReleaser { + DataObject *Obj; + +public: + ScopedDataObjectReleaser(DataObject *Obj) : Obj(Obj) {} + + ScopedDataObjectReleaser(amd_comgr_data_t Obj) + : Obj(DataObject::convert(Obj)) {} + + ~ScopedDataObjectReleaser() { Obj->release(); } +}; + +struct DataSet { + + DataSet(); + ~DataSet(); + + static amd_comgr_data_set_t convert(DataSet *Set) { + amd_comgr_data_set_t Handle = { + static_cast(reinterpret_cast(Set))}; + return Handle; + } + + static const amd_comgr_data_set_t convert(const DataSet *Set) { + const amd_comgr_data_set_t Handle = { + static_cast(reinterpret_cast(Set))}; + return Handle; + } + + static DataSet *convert(amd_comgr_data_set_t Set) { + return reinterpret_cast(Set.handle); + } + + llvm::SmallSetVector DataObjects; +}; + +struct DataAction { + // Some actions involving llvm we want to do it only once for the entire + // duration of the COMGR library. Once initialized, they should never be + // reset. + + DataAction(); + ~DataAction(); + + static amd_comgr_action_info_t convert(DataAction *Action) { + amd_comgr_action_info_t Handle = { + static_cast(reinterpret_cast(Action))}; + return Handle; + } + + static const amd_comgr_action_info_t convert(const DataAction *Action) { + const amd_comgr_action_info_t Handle = { + static_cast(reinterpret_cast(Action))}; + return Handle; + } + + static DataAction *convert(amd_comgr_action_info_t Action) { + return reinterpret_cast(Action.handle); + } + + amd_comgr_status_t setIsaName(llvm::StringRef IsaName); + amd_comgr_status_t setActionPath(llvm::StringRef ActionPath); + + // Set the options to be the new list. + amd_comgr_status_t setOptionList(llvm::ArrayRef Options); + // If the options were set via setOptionList, return the length of the list. + amd_comgr_status_t getOptionListCount(size_t &Size); + // If the options were set via setOptionList, return a reference to the + // string at Index in the list (including the null terminator). + amd_comgr_status_t getOptionListItem(size_t Index, llvm::StringRef &Option); + + // Return an array of options. The returned array reference is only valid as + // long as no other option APIs are called. + llvm::ArrayRef getOptions(); + + amd_comgr_status_t setBundleEntryIDs(llvm::ArrayRef EntryIDs); + llvm::ArrayRef getBundleEntryIDs(); + + char *IsaName; + char *Path; + amd_comgr_language_t Language; + bool Logging; + bool ShouldLinkDeviceLibs = false; + bool ShouldUseVFS = true; + + std::vector BundleEntryIDs; + +private: + std::vector ListOptions; +}; + +// Elements common to all DataMeta which refer to the same "document". +struct MetaDocument { + // The MsgPack document, which owns all memory allocated during parsing. + llvm::msgpack::Document Document; + // The MsgPack parser is zero-copy, so we retain a copy of the input buffer. + std::string RawDocument; + std::vector RawDocumentList; + // The old YAML parser would produce the strings "true" and "false" for + // booleans, whereas the old MsgPack parser produced "0" and "1". The new + // universal parser produces "true" and "false", but we need to remain + // backwards compatible, so we set a flag when parsing MsgPack. + bool EmitIntegerBooleans = false; +}; + +struct DataMeta { + static amd_comgr_metadata_node_t convert(DataMeta *Meta) { + amd_comgr_metadata_node_t Handle = { + static_cast(reinterpret_cast(Meta))}; + return Handle; + } + + static const amd_comgr_metadata_node_t convert(const DataMeta *Meta) { + const amd_comgr_metadata_node_t Handle = { + static_cast(reinterpret_cast(Meta))}; + return Handle; + } + + static DataMeta *convert(amd_comgr_metadata_node_t Meta) { + return reinterpret_cast(Meta.handle); + } + + amd_comgr_metadata_kind_t getMetadataKind(); + // Get the canonical string representation of @p DocNode, assuming + // it is a scalar node. + std::string convertDocNodeToString(llvm::msgpack::DocNode DocNode); + + // This DataMeta's "meta document", shared by all instances derived from the + // same metadata. + std::shared_ptr MetaDoc; + // This DataMeta's "view" into the shared llvm::msgpack::Document. + llvm::msgpack::DocNode DocNode; +}; + +struct DataSymbol { + DataSymbol(SymbolContext *DataSym); + ~DataSymbol(); + + static amd_comgr_symbol_t convert(DataSymbol *Sym) { + amd_comgr_symbol_t Handle = { + static_cast(reinterpret_cast(Sym))}; + return Handle; + } + + static const amd_comgr_symbol_t convert(const DataSymbol *Sym) { + const amd_comgr_symbol_t Handle = { + static_cast(reinterpret_cast(Sym))}; + return Handle; + } + + static DataSymbol *convert(amd_comgr_symbol_t Sym) { + return reinterpret_cast(Sym.handle); + } + + SymbolContext *DataSym; +}; + +// Store relevant data used when mapping name expressiosn to symbol names for +// for code objects +struct NameExpressionData { +public: + llvm::StringRef StubName; + llvm::StringRef UnmangledName; + llvm::StringRef MangledName; + long unsigned int StubValue; + long unsigned int MangledValue; + long unsigned int RodataOffset; +}; + +// get a string identifying comgr: this is a combination of comgr's version, +// device-libs contents and opencl-c.h contents. +llvm::StringRef getComgrHashIdentifier(); + +} // namespace COMGR + +#endif // header guard diff --git a/amd/comgr/src/exportmap.in b/amd/comgr/src/exportmap.in new file mode 100644 index 0000000000000..d79760dc96264 --- /dev/null +++ b/amd/comgr/src/exportmap.in @@ -0,0 +1,97 @@ +@amd_comgr_NAME@_1.8 { +global: amd_comgr_action_data_count; + amd_comgr_action_data_get_data; + amd_comgr_action_info_get_language; + amd_comgr_action_info_get_logging; + amd_comgr_action_info_get_option_list_count; + amd_comgr_action_info_get_option_list_item; + amd_comgr_action_info_get_working_directory_path; + amd_comgr_action_info_set_language; + amd_comgr_action_info_set_logging; + amd_comgr_action_info_set_option_list; + amd_comgr_action_info_set_working_directory_path; + amd_comgr_create_action_info; + amd_comgr_create_data_set; + amd_comgr_create_data; + amd_comgr_data_set_add; + amd_comgr_data_set_remove; + amd_comgr_destroy_action_info; + amd_comgr_destroy_data_set; + amd_comgr_destroy_disassembly_info; + amd_comgr_destroy_metadata; + amd_comgr_disassemble_instruction; + amd_comgr_do_action; + amd_comgr_get_data_kind; + amd_comgr_get_data_metadata; + amd_comgr_get_data_name; + amd_comgr_get_data; + amd_comgr_get_metadata_kind; + amd_comgr_get_metadata_list_size; + amd_comgr_get_metadata_map_size; + amd_comgr_get_metadata_string; + amd_comgr_get_version; + amd_comgr_index_list_metadata; + amd_comgr_iterate_map_metadata; + amd_comgr_iterate_symbols; + amd_comgr_metadata_lookup; + amd_comgr_release_data; + amd_comgr_set_data_name; + amd_comgr_set_data; + amd_comgr_status_string; + amd_comgr_symbol_get_info; + amd_comgr_symbol_lookup; +local: *; +}; + +@amd_comgr_NAME@_2.0 { +global: amd_comgr_action_info_get_isa_name; + amd_comgr_action_info_set_isa_name; + amd_comgr_create_disassembly_info; + amd_comgr_get_data_isa_name; + amd_comgr_get_isa_count; + amd_comgr_get_isa_metadata; + amd_comgr_get_isa_name; +} @amd_comgr_NAME@_1.8; + +@amd_comgr_NAME@_2.2 { +global: amd_comgr_demangle_symbol_name; +} @amd_comgr_NAME@_2.0; + +@amd_comgr_NAME@_2.3 { +global: amd_comgr_set_data_from_file_slice; + amd_comgr_lookup_code_object; +} @amd_comgr_NAME@_2.2; + +@amd_comgr_NAME@_2.4 { +global: amd_comgr_create_symbolizer_info; + amd_comgr_destroy_symbolizer_info; + amd_comgr_symbolize; +} @amd_comgr_NAME@_2.3; + +@amd_comgr_NAME@_2.5 { +global: amd_comgr_populate_mangled_names; + amd_comgr_get_mangled_name; +} @amd_comgr_NAME@_2.4; + +@amd_comgr_NAME@_2.6 { +global: amd_comgr_populate_name_expression_map; + amd_comgr_map_name_expression_to_symbol_name; +} @amd_comgr_NAME@_2.5; + +@amd_comgr_NAME@_2.7 { +global: amd_comgr_map_elf_virtual_address_to_code_object_offset; +} @amd_comgr_NAME@_2.6; + +@amd_comgr_NAME@_2.8 { +global: amd_comgr_action_info_set_bundle_entry_ids; + amd_comgr_action_info_get_bundle_entry_id_count; + amd_comgr_action_info_get_bundle_entry_id; +} @amd_comgr_NAME@_2.7; + +@amd_comgr_NAME@_2.9 { +global: amd_comgr_action_info_set_device_lib_linking; +} @amd_comgr_NAME@_2.8; + +@amd_comgr_NAME@3.1 { +global: amd_comgr_action_info_set_vfs; +} @amd_comgr_NAME@_2.9; diff --git a/amd/comgr/src/time-stat/perf-timer.h b/amd/comgr/src/time-stat/perf-timer.h new file mode 100644 index 0000000000000..b1b70ae93075e --- /dev/null +++ b/amd/comgr/src/time-stat/perf-timer.h @@ -0,0 +1,39 @@ +//===- perf-timer.h - Timing statistics -----------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef AMD_COMGR_PERF_TIMER_H +#define AMD_COMGR_PERF_TIMER_H + +namespace COMGR { +namespace TimeStatistics { + +// Timer abstract interface +class PerfTimerImpl { +protected: + long long CounterStart; + double PCFreq; + +public: + PerfTimerImpl() : CounterStart(0), PCFreq(0.0) {}; + virtual ~PerfTimerImpl() = default; + virtual bool Init() = 0; + virtual double getCurrentTime() = 0; +}; + +// Timer client interface class +class PerfTimer { + std::unique_ptr pImpl; + +public: + bool Init(); + double getCurrentTime() { return pImpl->getCurrentTime(); } +}; +} // namespace TimeStatistics +} // namespace COMGR + +#endif // AMD_COMGR_PERF_TIMER_H diff --git a/amd/comgr/src/time-stat/time-stat.cpp b/amd/comgr/src/time-stat/time-stat.cpp new file mode 100644 index 0000000000000..96d8fab8d36e3 --- /dev/null +++ b/amd/comgr/src/time-stat/time-stat.cpp @@ -0,0 +1,181 @@ +//===- time-stat.cpp - Timing statistics ----------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements Comgr's built-in profiler, which can be enabled with +/// the AMD_COMGR_TIME_STATISTICS enviornment variable. +/// +//===----------------------------------------------------------------------===// + +#include +#include +#include +#include +#include + +#include "comgr-env.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/raw_ostream.h" + +#if defined _WIN64 || defined _WIN32 +// Avoid introducing min as a macro from Windows headers. +#define NOMINMAX +#include +#elif defined __linux__ +#include +#endif + +using namespace llvm; +using namespace COMGR; + +#include "time-stat.h" +#include "ts-interface.h" + +namespace COMGR { +namespace TimeStatistics { + +namespace { +std::unique_ptr PS = nullptr; +void dump() { PS->dumpPerfStats(); } +} // namespace + +void getLogFile(std::string &PerfLog) { + if (std::optional RedirectLogs = env::getRedirectLogs()) { + PerfLog = (*RedirectLogs).str(); + return; + } + PerfLog = "PerfStatsLog.txt"; +} + +bool InitTimeStatistics(std::string LogFile) { + if (!PS) { + if (!env::needTimeStatistics()) { + return false; + } + + if (LogFile == "") { + getLogFile(LogFile); + } + + PS = std::make_unique(); + if (!PS || !PS->Init(LogFile)) { + std::cerr << "TimeStatistics failed to initialize\n"; + return false; + } + std::atexit(&dump); + } + return true; +} + +void ProfilePoint::finish() { + if (PS) { + double End = PS->getCurrentTime(); + PS->AddToStats(Name, End - StartTime); + } + + isFinished = true; +} + +ProfilePoint::ProfilePoint(StringRef Tag) : Name(Tag) { + InitTimeStatistics(""); + if (PS) { + StartTime = PS->getCurrentTime(); + } +} + +ProfilePoint::~ProfilePoint() { + if (!isFinished) { + finish(); + } +} + +// Timer implementation +#if defined _WIN64 || defined _WIN32 +class PerfTimerWindows : public PerfTimerImpl { + +public: + PerfTimerWindows() {}; + virtual bool Init() override { + LARGE_INTEGER li; + if (QueryPerformanceCounter(&li)) + CounterStart = li.QuadPart; + else { + std::cerr << "Failed to get performance counter\n"; + return false; + } + + if (!QueryPerformanceFrequency(&li)) { + std::cerr << "Failed to get performance frequency\n"; + return false; + } + // QueryPerformanceFrequency returns counts per second + // If we need milliseconds we divide by 10^3 + // TODO: granularity as env var + PCFreq = li.QuadPart / 1e3; + return true; + } + + virtual double getCurrentTime() override { + LARGE_INTEGER li; + if (QueryPerformanceCounter(&li)) + return double(li.QuadPart) / PCFreq; + else { + std::cerr << "Failed to get performance counter\n"; + return 0.0; + } + } +}; + +#elif defined __linux__ +class PerfTimerLinux : public PerfTimerImpl { +public: + virtual bool Init() override { + struct timespec StartTime; + if (!clock_gettime(CLOCK_MONOTONIC_RAW, &StartTime)) { + CounterStart = StartTime.tv_sec * 1e9 + StartTime.tv_nsec; + } else { + std::cerr << "Failed to get performance counter\n"; + return false; + } + + struct timespec Res; + if (clock_getres(CLOCK_MONOTONIC_RAW, &Res)) { + std::cerr << "Failed to get performance frequency\n"; + return false; + } + // clock_getres returns counts per nanosecond + // If we need milliseconds we multiply by 10^6 + // TODO: granularity as env var + PCFreq = (Res.tv_sec * 1e9 + Res.tv_nsec) * 1e6; + return true; + } + + virtual double getCurrentTime() override { + struct timespec EndTime; + if (!clock_gettime(CLOCK_MONOTONIC_RAW, &EndTime)) { + return (EndTime.tv_sec * 1e9 + EndTime.tv_nsec) / PCFreq; + } + std::cerr << "Failed to get performance counter\n"; + return 0.0; + } +}; +#endif + +bool PerfTimer::Init() { +#if defined _WIN64 || defined _WIN32 + pImpl = std::make_unique(); +#elif defined __linux__ + pImpl = std::make_unique(); +#endif + return pImpl->Init(); +} + +} // namespace TimeStatistics +} // namespace COMGR diff --git a/amd/comgr/src/time-stat/time-stat.h b/amd/comgr/src/time-stat/time-stat.h new file mode 100644 index 0000000000000..8399f95044582 --- /dev/null +++ b/amd/comgr/src/time-stat/time-stat.h @@ -0,0 +1,77 @@ +//===- time-stat.h - Timing statistics ------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef AMD_COMGR_TIME_STAT_H +#define AMD_COMGR_TIME_STAT_H + +#include "perf-timer.h" +#include "llvm/ADT/StringMap.h" + +#include "amd_comgr.h" +#include + +namespace COMGR { +namespace TimeStatistics { + +struct ProfileData { + double TimeTaken; + int Counter; +}; + +class PerfStats { + std::unique_ptr> + pLog; + PerfTimer PT; + + llvm::StringMap ProfileDataMap; + +public: + PerfStats() {} + bool Init(std::string LogFile) { + std::error_code EC; + std::unique_ptr> + LogF(new (std::nothrow) + llvm::raw_fd_ostream(LogFile, EC, llvm::sys::fs::OF_Text), + [](llvm::raw_fd_ostream *fp) { fp->close(); }); + if (EC) { + std::cerr << "Failed to open log file " << LogFile << "for perf stats " + << EC.message() << "\n "; + return false; + } else { + pLog = std::move(LogF); + } + + // Initialize Timer + if (!PT.Init()) + return false; + + return true; + } + + double getCurrentTime() { return PT.getCurrentTime(); } + + void AddToStats(llvm::StringRef Name, double TimeTaken) { + ProfileDataMap[Name].TimeTaken += TimeTaken; + ProfileDataMap[Name].Counter++; + } + + void dumpPerfStats() { + for (const auto &Item : ProfileDataMap) { + *pLog << llvm::format("%-50s", Item.getKey().str().c_str()) + << llvm::format("%6d", Item.getValue().Counter) << " calls" + << llvm::format("%10.4f", Item.getValue().TimeTaken) << " ms\n"; + } + } +}; + +} // namespace TimeStatistics +} // namespace COMGR + +#endif // AMD_COMGR_TIME_STAT_H diff --git a/amd/comgr/src/time-stat/ts-interface.h b/amd/comgr/src/time-stat/ts-interface.h new file mode 100644 index 0000000000000..29a420115f9a9 --- /dev/null +++ b/amd/comgr/src/time-stat/ts-interface.h @@ -0,0 +1,36 @@ +//===- ts-interface.h - Timing statistics ---------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef AMD_COMGR_TS_INTERFACE_H +#define AMD_COMGR_TS_INTERFACE_H + +#include "llvm/ADT/StringRef.h" +// External interface + +namespace COMGR { +namespace TimeStatistics { + +struct ProfilePoint { + ProfilePoint(llvm::StringRef Name); + ~ProfilePoint(); + void finish(); + +private: + std::string Name = ""; + double StartTime = 0.0; + bool isFinished = false; +}; + +bool InitTimeStatistics(std::string LogFile); +void StartAction(amd_comgr_action_kind_t); +void EndAction(); + +} // namespace TimeStatistics +} // namespace COMGR + +#endif // AMD_COMGR_TS_INTERFACE_H diff --git a/amd/comgr/test-lit/CMakeLists.txt b/amd/comgr/test-lit/CMakeLists.txt new file mode 100644 index 0000000000000..b3e478e4002a8 --- /dev/null +++ b/amd/comgr/test-lit/CMakeLists.txt @@ -0,0 +1,51 @@ +function(cannonicalize_cmake_boolean var) + if(${var}) + set(${var} 1 PARENT_SCOPE) + else() + set(${var} 0 PARENT_SCOPE) + endif() +endfunction() + +cannonicalize_cmake_boolean(COMGR_DISABLE_SPIRV) + +configure_file(lit.site.cfg.py.in lit.site.cfg.py @ONLY) + +if (NOT DEFINED LLVM_LIT_PATH) + # Comgr source build + if (EXISTS "${LLVM_TOOLS_BINARY_DIR}/../../bin/llvm-lit") + set(LLVM_LIT_PATH "${LLVM_TOOLS_BINARY_DIR}/../../bin/llvm-lit") + # LLVM external projects build + else() + set(LLVM_LIT_PATH "${LLVM_TOOLS_BINARY_DIR}/llvm-lit") + endif() +endif() +message("-- LLVM_LIT_PATH: ${LLVM_LIT_PATH}") + +add_custom_target(test-lit COMMAND "${LLVM_LIT_PATH}" + "${CMAKE_CURRENT_BINARY_DIR}" -v) + +macro(add_comgr_lit_binary name lang) + add_executable("${name}" "comgr-sources/${name}.${lang}") + if (${lang} STREQUAL "c") + set_target_properties("${name}" PROPERTIES + C_STANDARD 99 + C_STANDARD_REQUIRED Yes + C_EXTENSIONS No) + endif() + target_link_libraries("${name}" amd_comgr) + add_dependencies(check-comgr "${name}") +endmacro() + +set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) + +add_comgr_lit_binary(source-to-bc-with-dev-libs c) +add_comgr_lit_binary(spirv-translator c) +add_comgr_lit_binary(compile-opencl-minimal c) +add_comgr_lit_binary(spirv-to-reloc c) +add_comgr_lit_binary(unbundle c) +add_comgr_lit_binary(get-version c) +add_comgr_lit_binary(status-string c) +add_comgr_lit_binary(data-action c) +add_comgr_lit_binary(lookup-code-object c) + +add_dependencies(check-comgr test-lit) diff --git a/amd/comgr/test-lit/cache-tests/compile-minimal-test-cached-bad-dir.cl b/amd/comgr/test-lit/cache-tests/compile-minimal-test-cached-bad-dir.cl new file mode 100644 index 0000000000000..df6aa7f068f8e --- /dev/null +++ b/amd/comgr/test-lit/cache-tests/compile-minimal-test-cached-bad-dir.cl @@ -0,0 +1,13 @@ +// RUN: export AMD_COMGR_CACHE=1 +// +// COM: fail to create the cache, but still produce something valid +// RUN: rm -f %t.log +// RUN: echo "not a directory" > %t.txt +// RUN: AMD_COMGR_CACHE_DIR=%t.txt \ +// RUN: AMD_COMGR_EMIT_VERBOSE_LOGS=1 \ +// RUN: AMD_COMGR_REDIRECT_LOGS=%t.log \ +// RUN: compile-opencl-minimal %S/../compile-minimal-test.cl %t.bin 1.2 +// RUN: llvm-objdump -d %t.bin | FileCheck %S/../compile-minimal-test.cl +// RUN: FileCheck --check-prefix=BAD %s < %t.log +// BAD: Failed to open cache file +// BAD-SAME: Not a directory diff --git a/amd/comgr/test-lit/cache-tests/compile-minimal-test-cached-bad-policy.cl b/amd/comgr/test-lit/cache-tests/compile-minimal-test-cached-bad-policy.cl new file mode 100644 index 0000000000000..c1f4bf35d5aff --- /dev/null +++ b/amd/comgr/test-lit/cache-tests/compile-minimal-test-cached-bad-policy.cl @@ -0,0 +1,15 @@ +// RUN: export AMD_COMGR_CACHE=1 +// +// COM: fail to create the cache, but still produce something valid +// RUN: rm -f %t_log +// RUN: AMD_COMGR_CACHE_DIR=%t.cache \ +// RUN: AMD_COMGR_CACHE_POLICY="foo=2h" \ +// RUN: AMD_COMGR_EMIT_VERBOSE_LOGS=1 \ +// RUN: AMD_COMGR_REDIRECT_LOGS=%t.log \ +// RUN: compile-opencl-minimal %S/../compile-minimal-test.cl %t.bin 1.2 +// RUN: llvm-objdump -d %t.bin | FileCheck %S/../compile-minimal-test.cl +// RUN: FileCheck --check-prefix=BAD %s < %t.log +// BAD: when parsing the cache policy: Unknown key: 'foo' +// +// COM: the cache has not been created since we couldn't parse the policy +// RUN: [ ! -d %t.cache ] diff --git a/amd/comgr/test-lit/cache-tests/compile-minimal-test-cached.cl b/amd/comgr/test-lit/cache-tests/compile-minimal-test-cached.cl new file mode 100644 index 0000000000000..b19e3aba433ee --- /dev/null +++ b/amd/comgr/test-lit/cache-tests/compile-minimal-test-cached.cl @@ -0,0 +1,51 @@ +// RUN: rm -fr %t.cache +// +// RUN: export AMD_COMGR_EMIT_VERBOSE_LOGS=1 +// RUN: export AMD_COMGR_REDIRECT_LOGS=stdout +// +// +// COM: Check the default behavior of AMD_COMGR_CACHE +// RUN: unset AMD_COMGR_CACHE +// RUN: AMD_COMGR_CACHE_DIR=%t.cache compile-opencl-minimal \ +// RUN: %S/../compile-minimal-test.cl %t.bin 1.2 | FileCheck --check-prefix=STORED %s +// RUN: llvm-objdump -d %t.bin | FileCheck %S/../compile-minimal-test.cl +// RUN: [ -d %t.cache ] +// +// RUN: AMD_COMGR_CACHE_DIR=%t.cache compile-opencl-minimal \ +// RUN: %S/../compile-minimal-test.cl %t.bin 1.2 | FileCheck --check-prefix=FOUND %s +// RUN: llvm-objdump -d %t.bin | FileCheck %S/../compile-minimal-test.cl +// +// RUN: rm -fr %t.cache +// +// RUN: export AMD_COMGR_CACHE=0 +// RUN: AMD_COMGR_CACHE_DIR=%t.cache compile-opencl-minimal \ +// RUN: %S/../compile-minimal-test.cl %t.bin 1.2 +// RUN: llvm-objdump -d %t.bin | FileCheck %S/../compile-minimal-test.cl +// RUN: [ ! -d %t.cache ] +// +// RUN: export AMD_COMGR_CACHE=1 +// +// COM: Run once and check that the cache directory exists and it has more than +// COM 1 element (one for the cache tag, one or more for the cached +// COM: commands) +// RUN: AMD_COMGR_CACHE_DIR=%t.cache compile-opencl-minimal \ +// RUN: %S/../compile-minimal-test.cl %t_a.bin 1.2 | FileCheck --check-prefix=STORED %s +// RUN: llvm-objdump -d %t_a.bin | FileCheck %S/../compile-minimal-test.cl +// RUN: COUNT_BEFORE=$(ls "%t.cache" | wc -l) + +// COM: One element for the tag, one for cli->bc, one for bc->obj another +// COM: for obj->exec. No elements for src->cli since this is not supported. +// RUN: [ 4 -eq $COUNT_BEFORE ] +// +// RUN: AMD_COMGR_CACHE_DIR=%t.cache compile-opencl-minimal \ +// RUN: %S/../compile-minimal-test.cl %t_b.bin 1.2 | FileCheck --check-prefix=FOUND %s +// RUN: llvm-objdump -d %t_b.bin | FileCheck %S/../compile-minimal-test.cl +// RUN: COUNT_AFTER=$(ls "%t.cache" | wc -l) +// RUN: [ $COUNT_AFTER = $COUNT_BEFORE ] +// + +// COM: check that an entry is stored +// STORED: Comgr cache: stored entry + +// COM: check that an entry is found +// FOUND: Comgr cache: found entry diff --git a/amd/comgr/test-lit/cache-tests/spirv-translator-cached.cl b/amd/comgr/test-lit/cache-tests/spirv-translator-cached.cl new file mode 100644 index 0000000000000..b90821f283bb2 --- /dev/null +++ b/amd/comgr/test-lit/cache-tests/spirv-translator-cached.cl @@ -0,0 +1,24 @@ +// REQUIRES: comgr-has-spirv +// COM: Same as spirv-translator but with the cache +// RUN: rm -fr %t.cache + +// COM: Generate a spirv-targeted LLVM IR file from an OpenCL kernel +// RUN: clang -c -emit-llvm --target=spirv64 %S/../spirv-tests/spirv-translator.cl -o %t.bc + +// COM: Translate LLVM IR to SPIRV format +// RUN: amd-llvm-spirv --spirv-target-env=CL2.0 %t.bc -o %t.spv + +// COM: Run Comgr Translator to covert SPIRV back to LLVM IR +// RUN: export AMD_COMGR_CACHE=1 +// RUN: AMD_COMGR_CACHE_DIR=%t.cache spirv-translator %t.spv -o %t.translated.bc +// RUN: COUNT=$(ls "%t.cache" | wc -l) +// RUN: [ 2 -eq $COUNT ] + +// COM: Run again and check that the cache contents haven't changed +// RUN: AMD_COMGR_CACHE_DIR=%t.cache spirv-translator %t.spv -o \ +// RUN: %t.translated.again.bc +// RUN: COUNT=$(ls "%t.cache" | wc -l) +// RUN: [ 2 -eq $COUNT ] + +// COM: Dissasemble LLVM IR bitcode to LLVM IR text +// RUN: llvm-dis %t.translated.bc -o - | FileCheck %S/../spirv-tests/spirv-translator.cl diff --git a/amd/comgr/test-lit/cache-tests/unbundle-test-cached.hip b/amd/comgr/test-lit/cache-tests/unbundle-test-cached.hip new file mode 100644 index 0000000000000..f4fb1510010a3 --- /dev/null +++ b/amd/comgr/test-lit/cache-tests/unbundle-test-cached.hip @@ -0,0 +1,42 @@ +// Create compressed bitcode bundle (add --offload-compress flag) +// RUN: clang -c -x hip --offload-arch=gfx900 --offload-arch=gfx1030 \ +// RUN: -nogpulib -nogpuinc \ +// RUN: --gpu-bundle-output --offload-device-only \ +// RUN: -emit-llvm \ +// RUN: --offload-compress \ +// RUN: %s -o %t.compressed-bundle.bc +// +// Clean the cache +// RUN: rm -fr %t.cache +// +// With the cache enabled, test that we write one file to the cache +// RUN: export AMD_COMGR_CACHE=1 +// RUN: export AMD_COMGR_CACHE_DIR=%t.cache +// RUN: unbundle %t.compressed-bundle.bc hip-amdgcn-amd-amdhsa-unknown-gfx900 \ +// RUN: %t.cache_1.bc +// RUN: llvm-dis %t.cache_1.bc -o - | FileCheck --check-prefixes=BOTH,GFX9 %s +// RUN: COUNT=$(ls "%t.cache" | wc -l) +// RUN: [ 2 -eq $COUNT ] +// +// If there is a re-run, the cache contents remain the same +// RUN: unbundle %t.compressed-bundle.bc hip-amdgcn-amd-amdhsa-unknown-gfx900 \ +// RUN: %t.cache_2.bc +// RUN: llvm-dis %t.cache_2.bc -o - | FileCheck --check-prefixes=BOTH,GFX9 %s +// RUN: COUNT=$(ls "%t.cache" | wc -l) +// RUN: [ 2 -eq $COUNT ] +// +// A run with different input options results in new contents in the cache +// RUN: unbundle %t.compressed-bundle.bc hip-amdgcn-amd-amdhsa-unknown-gfx1030 \ +// RUN: %t.cache_3.bc +// RUN: llvm-dis %t.cache_3.bc -o - | FileCheck --check-prefixes=BOTH,GFX10 %s +// RUN: COUNT=$(ls "%t.cache" | wc -l) +// RUN: [ 3 -eq $COUNT ] + +// BOTH: target triple = "amdgcn-amd-amdhsa" +// GFX9: "target-cpu"="gfx900" +// GFX10: "target-cpu"="gfx1030" + +__attribute__((device)) +void add_value(float* a, float* b, float* res) { + *res = *a + *b; +} diff --git a/amd/comgr/test-lit/comgr-sources/common.h b/amd/comgr/test-lit/comgr-sources/common.h new file mode 100644 index 0000000000000..130d25f685dac --- /dev/null +++ b/amd/comgr/test-lit/comgr-sources/common.h @@ -0,0 +1,115 @@ +//===- common.h -----------------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_TEST_COMMON_H +#define COMGR_TEST_COMMON_H + +#include "amd_comgr.h" +#include +#include +#include +#include +#include + +#if !defined(_WIN32) && !defined(_WIN64) +#include +#include +#include +#include +#else // Windows +#include +#endif +#include +#include + +#define amd_comgr_(call) \ + do { \ + amd_comgr_status_t status = amd_comgr_##call; \ + if (status != AMD_COMGR_STATUS_SUCCESS) { \ + const char *reason = ""; \ + amd_comgr_status_string(status, &reason); \ + fail(#call " failed: %s\n file, line: %s, %d\n", reason, __FILE__, \ + __LINE__); \ + } \ + } while (false) + +#define fail_amd_comgr_(call) \ + do { \ + amd_comgr_status_t status = amd_comgr_##call; \ + if (status == AMD_COMGR_STATUS_SUCCESS) { \ + const char *reason = ""; \ + amd_comgr_status_string(status, &reason); \ + fail(#call " expected fail: %s\n file, line: %s, %d\n", reason, \ + __FILE__, __LINE__); \ + } \ + } while (false) + +static void fail(const char *format, ...) { + va_list ap; + va_start(ap, format); + + printf("FAILED: "); + vprintf(format, ap); + printf("\n"); + + va_end(ap); + + exit(1); +} + +static int setBuf(const char *infile, char **buf) { + FILE *fp; + long size; + + fp = fopen(infile, "rb"); + if (!fp) + fail("fopen : %s", infile); + if (fseek(fp, 0L, SEEK_END) != 0) + fail("fopen"); + size = ftell(fp); + if (size == -1) + fail("ftell"); + if (fseek(fp, 0, SEEK_SET) != 0) + fail("fseek"); + + *buf = (char *)malloc(size + 1); + if (!*buf) + fail("malloc"); + if (fread(*buf, size, 1, fp) != 1) + fail("fread"); + if (fclose(fp) != 0) + fail("fclose"); + (*buf)[size] = 0; // terminating zero + return size; +} + +static void dumpData(amd_comgr_data_t Data, const char *OutFile) { + size_t size; + char *bytes = NULL; + + amd_comgr_(get_data(Data, &size, NULL)); + + bytes = (char *)malloc(size); + if (!bytes) + fail("malloc"); + + amd_comgr_(get_data(Data, &size, bytes)); + + FILE *fp = fopen(OutFile, "wb"); + if (!fp) + fail("fopen : %s", OutFile); + + size_t ret = fwrite(bytes, sizeof(char), size, fp); + if (ret != size) + fail("fwrite"); + + free(bytes); + fclose(fp); +} + +#endif // COMGR_TEST_COMMON_H diff --git a/amd/comgr/test-lit/comgr-sources/compile-opencl-minimal.c b/amd/comgr/test-lit/comgr-sources/compile-opencl-minimal.c new file mode 100644 index 0000000000000..798492b8a784e --- /dev/null +++ b/amd/comgr/test-lit/comgr-sources/compile-opencl-minimal.c @@ -0,0 +1,124 @@ +//===- compile-opencl-minimal.c -------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource; + amd_comgr_data_set_t DataSetIn, DataSetBc, DataSetLinked, DataSetReloc, + DataSetExec; + amd_comgr_action_info_t DataAction; + size_t Count; + const char *CodeGenOptions[] = {"-mllvm", "--color"}; + size_t CodeGenOptionsCount = + sizeof(CodeGenOptions) / sizeof(CodeGenOptions[0]); + + SizeSource = setBuf(argv[1], &BufSource); + + amd_comgr_language_t OpenCLVersion; + if (strcmp(argv[3], "1.2") == 0) { + OpenCLVersion = AMD_COMGR_LANGUAGE_OPENCL_1_2; + } + else if (strcmp(argv[3], "2.0") == 0) { + OpenCLVersion = AMD_COMGR_LANGUAGE_OPENCL_2_0; + } + else + fail("unsupported OCL version: %s", argv[3]); + + amd_comgr_(create_data_set(&DataSetIn)); + amd_comgr_(create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource)); + amd_comgr_(set_data(DataSource, SizeSource, BufSource)); + amd_comgr_(set_data_name(DataSource, "source1.cl")); + amd_comgr_(data_set_add(DataSetIn, DataSource)); + + amd_comgr_(create_action_info(&DataAction)); + amd_comgr_( + action_info_set_language(DataAction, OpenCLVersion)); + amd_comgr_(action_info_set_isa_name(DataAction, "amdgcn-amd-amdhsa--gfx900")); + amd_comgr_(action_info_set_option_list(DataAction, CodeGenOptions, + CodeGenOptionsCount)); + amd_comgr_(create_data_set(&DataSetBc)); + amd_comgr_(do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, DataAction, + DataSetIn, DataSetBc)); + amd_comgr_(action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count)); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + amd_comgr_(create_data_set(&DataSetLinked)); + + amd_comgr_(do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, DataSetBc, + DataSetLinked)); + amd_comgr_(action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, &Count)); + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + amd_comgr_(create_data_set(&DataSetReloc)); + + amd_comgr_(action_info_set_device_lib_linking(DataAction, true)); + + amd_comgr_(do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, DataAction, + DataSetLinked, DataSetReloc)); + + amd_comgr_( + action_data_count(DataSetReloc, AMD_COMGR_DATA_KIND_RELOCATABLE, &Count)); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu source objects (expected 1)\n", + Count); + exit(1); + } + + amd_comgr_(create_data_set(&DataSetExec)); + + amd_comgr_(action_info_set_option_list(DataAction, NULL, 0)); + + amd_comgr_(do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec)); + + amd_comgr_( + action_data_count(DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, &Count)); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + amd_comgr_data_t DataExec; + amd_comgr_(action_data_get_data(DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, + 0, &DataExec)); + dumpData(DataExec, argv[2]); + + amd_comgr_(release_data(DataSource)); + amd_comgr_(release_data(DataExec)); + amd_comgr_(destroy_data_set(DataSetIn)); + amd_comgr_(destroy_data_set(DataSetBc)); + amd_comgr_(destroy_data_set(DataSetLinked)); + amd_comgr_(destroy_data_set(DataSetReloc)); + amd_comgr_(destroy_data_set(DataSetExec)); + amd_comgr_(destroy_action_info(DataAction)); + free(BufSource); + return 0; +} diff --git a/amd/comgr/test-lit/comgr-sources/data-action.c b/amd/comgr/test-lit/comgr-sources/data-action.c new file mode 100644 index 0000000000000..13cb24c65890f --- /dev/null +++ b/amd/comgr/test-lit/comgr-sources/data-action.c @@ -0,0 +1,129 @@ +//===- compile-minimal-test.c ---------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + amd_comgr_action_info_t DataAction; + amd_comgr_(create_action_info(&DataAction)); + + // ---- set_language, get_language + amd_comgr_language_t Language; + amd_comgr_( + action_info_set_language(DataAction, AMD_COMGR_LANGUAGE_NONE)); + amd_comgr_(action_info_get_language(DataAction, &Language)); + if (Language != AMD_COMGR_LANGUAGE_NONE) + fail("AMD_COMGR_LANGUAGE_NONE not returned!"); + + amd_comgr_( + action_info_set_language(DataAction, AMD_COMGR_LANGUAGE_OPENCL_1_2)); + amd_comgr_(action_info_get_language(DataAction, &Language)); + if (Language != AMD_COMGR_LANGUAGE_OPENCL_1_2) + fail("AMD_COMGR_LANGUAGE_OPENCL_1_2 not returned!"); + + amd_comgr_( + action_info_set_language(DataAction, AMD_COMGR_LANGUAGE_OPENCL_2_0)); + amd_comgr_(action_info_get_language(DataAction, &Language)); + if (Language != AMD_COMGR_LANGUAGE_OPENCL_2_0) + fail("AMD_COMGR_LANGUAGE_OPENCL_2_0 not returned!"); + + amd_comgr_( + action_info_set_language(DataAction, AMD_COMGR_LANGUAGE_HIP)); + amd_comgr_(action_info_get_language(DataAction, &Language)); + if (Language != AMD_COMGR_LANGUAGE_HIP) + fail("AMD_COMGR_LANGUAGE_HIP not returned!"); + + amd_comgr_( + action_info_set_language(DataAction, AMD_COMGR_LANGUAGE_LLVM_IR)); + amd_comgr_(action_info_get_language(DataAction, &Language)); + if (Language != AMD_COMGR_LANGUAGE_LLVM_IR) + fail("AMD_COMGR_LANGUAGE_LLVM_IR not returned!"); + + // ---- set_isa_name, get_isa_name + // Tested in comgr/test/get_data_isa_name_test.c + + // ---- set_option_list, get_option_list_count, get_option_list_item + const char *Options[] = {"foo", "bar", "bazqux", "aaaaaaaaaaaaaaaaaaaaa"}; + size_t OptionsCount = sizeof(Options) / sizeof(Options[0]); + + amd_comgr_(action_info_set_option_list(DataAction, Options, OptionsCount)); + + size_t ActualCount; + amd_comgr_(action_info_get_option_list_count(DataAction, &ActualCount)); + + if (OptionsCount != ActualCount) { + fail("incorrect option count: expected %zu, saw %zu", OptionsCount, + ActualCount); + } + + size_t Size; + for (size_t I = 0; I < OptionsCount; ++I) { + amd_comgr_(action_info_get_option_list_item(DataAction, I, &Size, NULL)); + + char *Option = calloc(Size, sizeof(char)); + amd_comgr_(action_info_get_option_list_item(DataAction, I, &Size, Option)); + + if (strcmp(Options[I], Option)) { + fail("incorrect option string: expected '%s', saw '%s'", Options[I], + Option); + } + free(Option); + } + + fail_amd_comgr_(action_info_get_option_list_item(DataAction, OptionsCount, + &Size, NULL)); + fail_amd_comgr_(action_info_get_option_list_count(DataAction, NULL)); + fail_amd_comgr_(action_info_get_option_list_item(DataAction, 0, NULL, NULL)); + + // ---- set_bundle_entry_ids, get_bundle_entry_id_count, get_bundle_entry_id + // Tested in comgr/test/unbundle-hip-test.c + + // ---- set_working_directory_path, get_working_directory_path + const char *Path = "/path/to/my/directory"; + amd_comgr_(action_info_set_working_directory_path(DataAction, Path)); + + amd_comgr_(action_info_get_working_directory_path(DataAction, &Size, + NULL)); + char *GetPath = calloc(Size, sizeof(char)); + amd_comgr_(action_info_get_working_directory_path(DataAction, &Size, + GetPath)); + + if (strcmp(Path, GetPath)) + fail("incorrect path string: expected '%s', saw '%s'", Path, GetPath); + free(GetPath); + + // ---- set_logging, get_logging + amd_comgr_(action_info_set_logging(DataAction, true)); + + bool GetLogging; + amd_comgr_(action_info_get_logging(DataAction, &GetLogging)); + + if (!GetLogging) + fail("incorrect logging boolean: expected 'true', saw 'false'"); + + amd_comgr_(action_info_set_logging(DataAction, false)); + amd_comgr_(action_info_get_logging(DataAction, &GetLogging)); + + if (GetLogging) + fail("incorrect logging boolean: expected 'false', saw 'true'"); + + // ---- set_device_lib_linking + amd_comgr_(action_info_set_device_lib_linking(DataAction, true)); + amd_comgr_(action_info_set_device_lib_linking(DataAction, false)); + + // ---- set_vfs + amd_comgr_(action_info_set_vfs(DataAction, true)); + amd_comgr_(action_info_set_vfs(DataAction, false)); + + amd_comgr_(destroy_action_info(DataAction)); + return 0; +} diff --git a/amd/comgr/test-lit/comgr-sources/get-version.c b/amd/comgr/test-lit/comgr-sources/get-version.c new file mode 100644 index 0000000000000..8df3c0b378429 --- /dev/null +++ b/amd/comgr/test-lit/comgr-sources/get-version.c @@ -0,0 +1,25 @@ +//===- get-version.c ------------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" + +int main(int argc, char *argv[]) { + + size_t *Major = malloc(sizeof(size_t)); + size_t *Minor = malloc(sizeof(size_t)); + + amd_comgr_get_version(Major, Minor); + + if (*Major != 3 || *Minor != 0) + fail("incorrect version: expected 3.0, saw %zu, %zu", *Major, *Minor); + + free(Major); + free(Minor); + return 0; +} diff --git a/amd/comgr/test-lit/comgr-sources/lookup-code-object.c b/amd/comgr/test-lit/comgr-sources/lookup-code-object.c new file mode 100644 index 0000000000000..fab8d4c49ea3a --- /dev/null +++ b/amd/comgr/test-lit/comgr-sources/lookup-code-object.c @@ -0,0 +1,51 @@ +//===- lookup-code-object.c -----------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" + +int main(int argc, char *argv[]) { + amd_comgr_data_kind_t Kind; + switch(atoi(argv[2])) { + case 0: + Kind = AMD_COMGR_DATA_KIND_EXECUTABLE; + break; + case 1: + Kind = AMD_COMGR_DATA_KIND_FATBIN; + } + + char *BufObject; + size_t SizeObject = setBuf(argv[1], &BufObject); + + amd_comgr_data_t DataObject; + amd_comgr_(create_data(Kind, &DataObject)); + amd_comgr_(set_data(DataObject, SizeObject, BufObject)); + + amd_comgr_code_object_info_t ObjectInfo[3]; + ObjectInfo[0].isa = "amdgcn-amd-amdhsa--gfx900"; + ObjectInfo[0].size = 0; + ObjectInfo[0].offset = 0; + + ObjectInfo[1].isa = "amdgcn-amd-amdhsa--gfx942"; + ObjectInfo[1].size = 0; + ObjectInfo[1].offset = 0; + + ObjectInfo[2].isa = "amdgcn-amd-amdhsa--gfx950"; + ObjectInfo[2].size = 0; + ObjectInfo[2].offset = 0; + + amd_comgr_(lookup_code_object(DataObject, ObjectInfo, 3)); + + for (int i = 0; i < 3; ++i) { + printf("ObjectInfo[%d].isa: %s\n", i, ObjectInfo[i].isa); + printf("ObjectInfo[%d].size: %ld\n", i, ObjectInfo[i].size); + printf("ObjectInfo[%d].offset: %ld\n", i, ObjectInfo[i].offset); + } + + return 0; +} diff --git a/amd/comgr/test-lit/comgr-sources/source-to-bc-with-dev-libs.c b/amd/comgr/test-lit/comgr-sources/source-to-bc-with-dev-libs.c new file mode 100644 index 0000000000000..b608817ff8481 --- /dev/null +++ b/amd/comgr/test-lit/comgr-sources/source-to-bc-with-dev-libs.c @@ -0,0 +1,77 @@ +//===- source-to-bc-with-device-libs.c ------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource; + amd_comgr_data_set_t DataSetIn, DataSetBc; + amd_comgr_action_info_t DataAction; + const char *CodeGenOptions[] = {"-mcode-object-version=5", "-mllvm", + "-amdgpu-prelink"}; + size_t CodeGenOptionsCount = + sizeof(CodeGenOptions) / sizeof(CodeGenOptions[0]); + if (argc < 4 || argc > 5) { + fprintf(stderr, "Usage: source-to-bc-with-device-libs file.cl " + "[--vfs|--novfs] -o file.bc\n"); + exit(1); + } + + SizeSource = setBuf(argv[1], &BufSource); + + amd_comgr_(create_data_set(&DataSetIn)); + amd_comgr_(create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource)); + amd_comgr_(set_data(DataSource, SizeSource, BufSource)); + amd_comgr_(set_data_name(DataSource, "device-lib-linking.cl")); + amd_comgr_(data_set_add(DataSetIn, DataSource)); + + amd_comgr_(create_action_info(&DataAction)); + amd_comgr_( + action_info_set_language(DataAction, AMD_COMGR_LANGUAGE_OPENCL_1_2)); + amd_comgr_(action_info_set_isa_name(DataAction, "amdgcn-amd-amdhsa--gfx900")); + + if (!strncmp(argv[2], "--vfs", 5)) { + amd_comgr_(action_info_set_vfs(DataAction, true)); + } else if (!strncmp(argv[2], "--novfs", 7)) { + amd_comgr_(action_info_set_vfs(DataAction, false)); + } + + amd_comgr_(create_data_set(&DataSetBc)); + amd_comgr_(action_info_set_option_list(DataAction, CodeGenOptions, + CodeGenOptionsCount)); + amd_comgr_(do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, + DataAction, DataSetIn, DataSetBc)); + + size_t Count; + amd_comgr_(action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count)); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + amd_comgr_data_t DataBc; + amd_comgr_( + action_data_get_data(DataSetBc, AMD_COMGR_DATA_KIND_BC, 0, &DataBc)); + dumpData(DataBc, argv[argc - 1]); + + amd_comgr_(release_data(DataSource)); + amd_comgr_(release_data(DataBc)); + amd_comgr_(destroy_data_set(DataSetIn)); + amd_comgr_(destroy_data_set(DataSetBc)); + amd_comgr_(destroy_action_info(DataAction)); + free(BufSource); +} diff --git a/amd/comgr/test-lit/comgr-sources/spirv-to-reloc.c b/amd/comgr/test-lit/comgr-sources/spirv-to-reloc.c new file mode 100644 index 0000000000000..17ee953f89793 --- /dev/null +++ b/amd/comgr/test-lit/comgr-sources/spirv-to-reloc.c @@ -0,0 +1,65 @@ +//===- sirpv-to-reloc.c ---------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSpv; + size_t SizeSpv; + amd_comgr_data_t DataSpv; + amd_comgr_data_set_t DataSetSpv, DataSetReloc; + amd_comgr_action_info_t DataAction; + size_t Count; + + if (argc != 3) { + fprintf(stderr, "Usage: spirv-to-reloc file.spv file.o\n"); + exit(1); + } + + SizeSpv = setBuf(argv[1], &BufSpv); + + amd_comgr_(create_data(AMD_COMGR_DATA_KIND_SPIRV, &DataSpv)); + amd_comgr_(set_data(DataSpv, SizeSpv, BufSpv)); + amd_comgr_(set_data_name(DataSpv, "file.spv")); + + amd_comgr_(create_data_set(&DataSetSpv)); + amd_comgr_(data_set_add(DataSetSpv, DataSpv)); + + amd_comgr_(create_action_info(&DataAction)); + amd_comgr_(action_info_set_language(DataAction, AMD_COMGR_LANGUAGE_HIP)); + amd_comgr_(action_info_set_isa_name(DataAction, "amdgcn-amd-amdhsa--gfx900")); + + amd_comgr_(create_data_set(&DataSetReloc)); + amd_comgr_(do_action(AMD_COMGR_ACTION_COMPILE_SPIRV_TO_RELOCATABLE, + DataAction, DataSetSpv, DataSetReloc)); + + amd_comgr_( + action_data_count(DataSetReloc, AMD_COMGR_DATA_KIND_RELOCATABLE, &Count)); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SPIRV_TO_RELOCATABLE Failed: " + "produced %zu RELOCATABLE objects (expected 1)\n", + Count); + exit(1); + } + + amd_comgr_data_t DataReloc; + amd_comgr_(action_data_get_data(DataSetReloc, AMD_COMGR_DATA_KIND_RELOCATABLE, + 0, &DataReloc)); + dumpData(DataReloc, argv[2]); + + amd_comgr_(release_data(DataSpv)); + amd_comgr_(destroy_data_set(DataSetSpv)); + amd_comgr_(destroy_data_set(DataSetReloc)); + amd_comgr_(destroy_action_info(DataAction)); + free(BufSpv); +} diff --git a/amd/comgr/test-lit/comgr-sources/spirv-translator.c b/amd/comgr/test-lit/comgr-sources/spirv-translator.c new file mode 100644 index 0000000000000..d68dca1c915d8 --- /dev/null +++ b/amd/comgr/test-lit/comgr-sources/spirv-translator.c @@ -0,0 +1,67 @@ +//===- spirv-translator.c -------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +// Tests the AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC action +// Accepts one or more .spv files, and returns one or more .bc files + +int main(int argc, char *argv[]) { + char *BufSpirv; + size_t SizeSpirv; + amd_comgr_data_t DataSpirv; + amd_comgr_data_set_t DataSetSpirv, DataSetBc; + amd_comgr_action_info_t DataAction; + size_t Count; + + if (argc != 4) { + fprintf(stderr, "Usage: spirv-translator file.spv -o file.spv.bc\n"); + exit(1); + } + + SizeSpirv = setBuf(argv[1], &BufSpirv); + + amd_comgr_(create_data_set(&DataSetSpirv)); + amd_comgr_(create_data(AMD_COMGR_DATA_KIND_SPIRV, &DataSpirv)); + amd_comgr_(set_data(DataSpirv, SizeSpirv, BufSpirv)); + amd_comgr_(set_data_name(DataSpirv, "source.spv")); + amd_comgr_(data_set_add(DataSetSpirv, DataSpirv)); + + amd_comgr_(create_action_info(&DataAction)); + amd_comgr_(create_data_set(&DataSetBc)); + + amd_comgr_(do_action(AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC, DataAction, + DataSetSpirv, DataSetBc)); + + amd_comgr_(action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count)); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + // Write bitcode to file + amd_comgr_data_t DataSpirvBc; + + amd_comgr_( + action_data_get_data(DataSetBc, AMD_COMGR_DATA_KIND_BC, 0, &DataSpirvBc)); + + dumpData(DataSpirvBc, argv[3]); + + amd_comgr_(release_data(DataSpirv)); + amd_comgr_(destroy_data_set(DataSetSpirv)); + amd_comgr_(destroy_data_set(DataSetBc)); + amd_comgr_(destroy_action_info(DataAction)); + free(BufSpirv); +} diff --git a/amd/comgr/test-lit/comgr-sources/status-string.c b/amd/comgr/test-lit/comgr-sources/status-string.c new file mode 100644 index 0000000000000..fa7eb14bbc4ee --- /dev/null +++ b/amd/comgr/test-lit/comgr-sources/status-string.c @@ -0,0 +1,41 @@ +//===- status-string.c ----------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + const char *StatusString = malloc(sizeof(char) * 100); + amd_comgr_(status_string(AMD_COMGR_STATUS_SUCCESS, &StatusString)); + if (strcmp(StatusString, "SUCCESS")) + fail("incorrect status: expected 'SUCCESS', saw '%s'", StatusString); + + amd_comgr_(status_string(AMD_COMGR_STATUS_ERROR, &StatusString)); + if (strcmp(StatusString, "ERROR")) + fail("incorrect status: expected 'ERROR', saw '%s'", StatusString); + + amd_comgr_(status_string(AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT, + &StatusString)); + if (strcmp(StatusString, "INVALID_ARGUMENT")) { + fail("incorrect status: expected 'INVALID_ARGUMENT', saw '%s'", + StatusString); + } + + amd_comgr_(status_string(AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES, + &StatusString)); + if (strcmp(StatusString, "OUT_OF_RESOURCES")) { + fail("incorrect status: expected 'OUT_OF_RESOURCES', saw '%s'", + StatusString); + } + + fail_amd_comgr_(status_string(-1, &StatusString)); + return 0; +} diff --git a/amd/comgr/test-lit/comgr-sources/unbundle.c b/amd/comgr/test-lit/comgr-sources/unbundle.c new file mode 100644 index 0000000000000..538d8cd5ac3a6 --- /dev/null +++ b/amd/comgr/test-lit/comgr-sources/unbundle.c @@ -0,0 +1,78 @@ +//===- unbundle.c ---------------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" + +int main(int argc, char *argv[]) { + char *BundleData; + size_t BundleSize; + + if (argc < 4) { + printf("Usage: %s \n", argv[0]); + return -1; + } + + const char *BundlePath = argv[1]; + const char *Arch = argv[2]; + const char *BitcodePath = argv[3]; + + amd_comgr_data_t OneBundle; + amd_comgr_data_set_t InputBundles; + + BundleSize = setBuf(BundlePath, &BundleData); + + amd_comgr_(create_data_set(&InputBundles)); + amd_comgr_(create_data(AMD_COMGR_DATA_KIND_BC_BUNDLE, &OneBundle)); + amd_comgr_(set_data(OneBundle, BundleSize, BundleData)); + amd_comgr_(set_data_name(OneBundle, "bundle.bc")); + amd_comgr_(data_set_add(InputBundles, OneBundle)); + + amd_comgr_data_set_t OutputBitcode; + amd_comgr_(create_data_set(&OutputBitcode)); + + amd_comgr_action_info_t DataAction; + amd_comgr_(create_action_info(&DataAction)); + + const char *AllArch[] = {Arch}; + amd_comgr_(action_info_set_bundle_entry_ids(DataAction, AllArch, 1)); + amd_comgr_(do_action(AMD_COMGR_ACTION_UNBUNDLE, DataAction, InputBundles, + OutputBitcode)); + + size_t Count; + amd_comgr_(action_data_count(OutputBitcode, AMD_COMGR_DATA_KIND_BC, &Count)); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + amd_comgr_data_t OneBitcode; + amd_comgr_(action_data_get_data(OutputBitcode, AMD_COMGR_DATA_KIND_BC, 0, + &OneBitcode)); + + size_t BufferSize; + amd_comgr_(get_data(OneBitcode, &BufferSize, 0x0)); + char *Buffer = (char *)malloc(BufferSize); + amd_comgr_(get_data(OneBitcode, &BufferSize, Buffer)); + + FILE *BitcodeFile = fopen(BitcodePath, "wb"); + fwrite(Buffer, 1, BufferSize, BitcodeFile); + fclose(BitcodeFile); + + free(Buffer); + amd_comgr_(release_data(OneBitcode)); + amd_comgr_(release_data(OneBundle)); + amd_comgr_(destroy_action_info(DataAction)); + amd_comgr_(destroy_data_set(OutputBitcode)); + amd_comgr_(destroy_data_set(InputBundles)); + + return 0; +} diff --git a/amd/comgr/test-lit/compile-minimal-test.cl b/amd/comgr/test-lit/compile-minimal-test.cl new file mode 100644 index 0000000000000..3f09758519d48 --- /dev/null +++ b/amd/comgr/test-lit/compile-minimal-test.cl @@ -0,0 +1,12 @@ +// COM: Run Comgr binary to compile OpenCL source into LLVM IR Bitcode, +// COM: and, then generate an executable +// RUN: compile-opencl-minimal %s %t.bin 1.2 + +// COM: Dissasemble +// RUN: llvm-objdump -d %t.bin | FileCheck %s +// CHECK: : +// CHECK: s_endpgm + +void kernel add(__global float *A, __global float *B, __global float *C) { + *C = *A + *B; +} diff --git a/amd/comgr/test-lit/compile-opencl-2.cl b/amd/comgr/test-lit/compile-opencl-2.cl new file mode 100644 index 0000000000000..67d7164f69b4c --- /dev/null +++ b/amd/comgr/test-lit/compile-opencl-2.cl @@ -0,0 +1,12 @@ +// COM: Run Comgr binary to compile OpenCL source into LLVM IR Bitcode, +// COM: and, then generate an executable +// RUN: compile-opencl-minimal %s %t.bin 2.0 + +// COM: Dissasemble +// RUN: llvm-objdump -d %t.bin | FileCheck %s +// CHECK: : +// CHECK: s_endpgm + +void kernel add(__global float *A, __global float *B, __global float *C) { + *C = *A + *B; +} diff --git a/amd/comgr/test-lit/data-action.c b/amd/comgr/test-lit/data-action.c new file mode 100644 index 0000000000000..0df24cc3148ca --- /dev/null +++ b/amd/comgr/test-lit/data-action.c @@ -0,0 +1,2 @@ +// COM: Run Comgr binary test data action APIs +// RUN: data-action diff --git a/amd/comgr/test-lit/device-lib-linking.cl b/amd/comgr/test-lit/device-lib-linking.cl new file mode 100644 index 0000000000000..b8406a9a8b6df --- /dev/null +++ b/amd/comgr/test-lit/device-lib-linking.cl @@ -0,0 +1,48 @@ +// COM: Run Comgr binary to compile OpenCL source into LLVM IR Bitcode, linking +// COM: against the AMD Device Libraries +// RUN: source-to-bc-with-dev-libs %s -o %t-with-dev-libs.bc + +// COM: Dissasemble LLVM IR bitcode to LLVM IR text +// RUN: llvm-dis %t-with-dev-libs.bc -o - | FileCheck %s + +// COM: Verify LLVM IR text file +// CHECK: target triple = "amdgcn-amd-amdhsa" +// CHECK: define internal float @_Z4powrff +// CHECK: define internal float @_Z6sincosfPU3AS5f +// CHECK: define internal float @_Z4cbrtf +// CHECK: define internal float @__ocml_sincos_f32 +// CHECK: define internal float @__ocml_powr_f32 +// CHECK: define internal noundef float @__ocml_exp_f32 +// CHECK: define internal ptr addrspace(1) @__printf_alloc + +extern const __constant bool __oclc_finite_only_opt; +extern const __constant bool __oclc_unsafe_math_opt; +extern const __constant bool __oclc_wavefrontsize64; +extern const __constant int __oclc_ISA_version; +extern const __constant int __oclc_ABI_version; + +void kernel device_libs(__global float *status, float x, float y, float z) { + + if (__oclc_finite_only_opt) status[0] = 1.0; + if (__oclc_unsafe_math_opt) status[1] = 1.0; + if (__oclc_wavefrontsize64) status[2] = 1.0; + if (__oclc_ISA_version) status[3] = 1.0; + if (__oclc_ABI_version) status[4] = 1.0; + + // Math functions to test AMDGPULibCalls Folding optimizations + // fold_sincos() + status[6] = sin(x) + cos(x); + status[7] = cos(x) + sin(x); + + // fold_rootn() + status[8] = rootn(y, 3); + status[9] = rootn(y, -1); + status[10] = rootn(y, -2); + + // fold_pow() + status[11] = pow(z, (float) 0.5); + status[12] = powr(y, (float) 7.23); + + // printf() + printf("testy\n"); +} diff --git a/amd/comgr/test-lit/get-version.c b/amd/comgr/test-lit/get-version.c new file mode 100644 index 0000000000000..d5b3cf63d2fa4 --- /dev/null +++ b/amd/comgr/test-lit/get-version.c @@ -0,0 +1,2 @@ +// COM: Test Comgr get_version() API +// RUN: get-version diff --git a/amd/comgr/test-lit/lit.cfg.py b/amd/comgr/test-lit/lit.cfg.py new file mode 100644 index 0000000000000..242c6448320a1 --- /dev/null +++ b/amd/comgr/test-lit/lit.cfg.py @@ -0,0 +1,20 @@ +import os + +import lit.formats +import lit.util + +config.name = "Comgr" +config.suffixes = {".hip", ".cl", ".c", ".cpp"} +config.test_format = lit.formats.ShTest(True) + +config.excludes = ["comgr-sources"] + +config.test_source_root = os.path.dirname(__file__) +config.test_exec_root = config.my_obj_root + +if not config.comgr_disable_spirv: + config.available_features.add("comgr-has-spirv") + +# By default, disable the cache for the tests. +# Test for the cache must explicitly enable this variable. +config.environment['AMD_COMGR_CACHE'] = "0" diff --git a/amd/comgr/test-lit/lit.site.cfg.py.in b/amd/comgr/test-lit/lit.site.cfg.py.in new file mode 100644 index 0000000000000..ce8874196f946 --- /dev/null +++ b/amd/comgr/test-lit/lit.site.cfg.py.in @@ -0,0 +1,17 @@ +import os + +config.my_src_root = r'@CMAKE_CURRENT_SOURCE_DIR@' +config.my_obj_root = r'@CMAKE_CURRENT_BINARY_DIR@' + +config.comgr_disable_spirv = @COMGR_DISABLE_SPIRV@ + +# Needed for clang, llvm-dis, etc. +config.environment['PATH'] = os.pathsep.join(["@LLVM_TOOLS_BINARY_DIR@", + config.environment['PATH']]) + +# Needed for Comgr binaries +config.environment['PATH'] = os.pathsep.join(["@CMAKE_CURRENT_BINARY_DIR@", + config.environment['PATH']]) + +lit_config.load_config( + config, os.path.join(config.my_src_root, "lit.cfg.py")) diff --git a/amd/comgr/test-lit/lookup-code-object.hip b/amd/comgr/test-lit/lookup-code-object.hip new file mode 100644 index 0000000000000..93ed480a2ce80 --- /dev/null +++ b/amd/comgr/test-lit/lookup-code-object.hip @@ -0,0 +1,37 @@ +// COM: Create fatbin (executable) +// RUN: clang --offload-arch=gfx900 --offload-device-only \ +// RUN: --no-gpu-bundle-output -nogpulib -nogpuinc %s -o %t.so + +// RUN: lookup-code-object %t.so 0 | FileCheck --check-prefixes=EXEC %s + +// EXEC: ObjectInfo[0].isa: amdgcn-amd-amdhsa--gfx900 +// EXEC: ObjectInfo[0].size: {{[1-9][0-9]*}} +// EXEC: ObjectInfo[0].offset: 0 +// EXEC: ObjectInfo[1].isa: amdgcn-amd-amdhsa--gfx942 +// EXEC: ObjectInfo[1].size: 0 +// EXEC: ObjectInfo[1].offset: 0 +// EXEC: ObjectInfo[2].isa: amdgcn-amd-amdhsa--gfx950 +// EXEC: ObjectInfo[2].size: 0 +// EXEC: ObjectInfo[2].offset: 0 + +// COM: Create offload bundle +// RUN: clang --offload-arch=gfx900,gfx942 --offload-device-only \ +// RUN: --gpu-bundle-output -nogpulib -nogpuinc \ +// RUN: %s -o %t.bundle + +// RUN: lookup-code-object %t.bundle 1 | FileCheck --check-prefixes=BUNDLE %s + +// BUNDLE: ObjectInfo[0].isa: amdgcn-amd-amdhsa--gfx900 +// BUNDLE: ObjectInfo[0].size: {{[1-9][0-9]*}} +// BUNDLE: ObjectInfo[0].offset: {{[1-9][0-9]*}} +// BUNDLE: ObjectInfo[1].isa: amdgcn-amd-amdhsa--gfx942 +// BUNDLE: ObjectInfo[1].size: {{[1-9][0-9]*}} +// BUNDLE: ObjectInfo[1].offset: {{[1-9][0-9]*}} +// BUNDLE: ObjectInfo[2].isa: amdgcn-amd-amdhsa--gfx950 +// BUNDLE: ObjectInfo[2].size: 0 +// BUNDLE: ObjectInfo[2].offset: 0 + +__attribute__((device)) +void add_value(float* a, float* b, float* res) { + *res = *a + *b; +} diff --git a/amd/comgr/test-lit/spirv-tests/spirv-to-reloc-debuginfo.hip b/amd/comgr/test-lit/spirv-tests/spirv-to-reloc-debuginfo.hip new file mode 100644 index 0000000000000..4fa7cc4cbe0c6 --- /dev/null +++ b/amd/comgr/test-lit/spirv-tests/spirv-to-reloc-debuginfo.hip @@ -0,0 +1,52 @@ +// REQUIRES: comgr-has-spirv + +// COM: Generate a debuginfo SPIR-V file from a HIP kernel +// RUN: clang -x hip --offload-arch=amdgcnspirv -nogpulib -nogpuinc \ +// RUN: --no-gpu-bundle-output --offload-device-only -O3 %s -o %t.dbg.spv -g + +// COM: Compile debuginfo SPIR-V source to a relocatable +// RUN: AMD_COMGR_EMIT_VERBOSE_LOGS=1 AMD_COMGR_REDIRECT_LOGS=stdout \ +// RUN: spirv-to-reloc %t.dbg.spv %t.dbg.o | FileCheck --dump-input-filter all \ +// RUN: -check-prefix=CHECK-DBG %s + +// COM: Check that debuginfo SPIR-V flags are correctly extracted +// CHECK-DBG: Driver Job Args: {{.*}} "-mllvm" "-amdgpu-spill-cfi-saved-regs" + +#include + +#define __constant__ __attribute__((constant)) +#define __device__ __attribute__((device)) +#define __global__ __attribute__((global)) +#define __host__ __attribute__((host)) +#define __shared__ __attribute__((shared)) +#define __managed__ __attribute__((managed)) +#define __launch_bounds__(...) __attribute__((launch_bounds(__VA_ARGS__))) + +struct dim3 { + unsigned x, y, z; + __host__ __device__ dim3(unsigned x, unsigned y = 1, unsigned z = 1) : x(x), y(y), z(z) {} +}; + +#ifdef __HIP__ +typedef struct hipStream *hipStream_t; +typedef enum hipError {} hipError_t; +int hipConfigureCall(dim3 gridSize, dim3 blockSize, size_t sharedSize = 0, + hipStream_t stream = 0); +extern "C" hipError_t __hipPushCallConfiguration(dim3 gridSize, dim3 blockSize, + size_t sharedSize = 0, + hipStream_t stream = 0); +extern "C" hipError_t hipLaunchKernel(const void *func, dim3 gridDim, + dim3 blockDim, void **args, + size_t sharedMem, + hipStream_t stream); +#endif + +__attribute__((device)) +void clean_value(float* ptr) { *ptr = 0; } + +__attribute__((global)) +void add_value(float* a, float* b, float* res) { + *res = *a + *b; + + clean_value(a); +} diff --git a/amd/comgr/test-lit/spirv-tests/spirv-to-reloc.hip b/amd/comgr/test-lit/spirv-tests/spirv-to-reloc.hip new file mode 100644 index 0000000000000..40bf8fa6e6aca --- /dev/null +++ b/amd/comgr/test-lit/spirv-tests/spirv-to-reloc.hip @@ -0,0 +1,59 @@ +// REQUIRES: comgr-has-spirv + +// COM: Generate a SPIR-V file from a HIP kernel +// RUN: clang -x hip --offload-arch=amdgcnspirv -nogpulib -nogpuinc \ +// RUN: --no-gpu-bundle-output --offload-device-only -O3 %s -o %t.spv \ +// RUN: -fvisibility=hidden -fno-autolink -fexceptions -fcolor-diagnostics + +// COM: Compile SPIR-V source to a relocatable +// RUN: AMD_COMGR_EMIT_VERBOSE_LOGS=1 AMD_COMGR_REDIRECT_LOGS=spirv-flags.txt \ +// RUN: spirv-to-reloc %t.spv %t.o + +// COM: Check that SPIR-V flags are correctly extracted +// RUN: grep '\-fvisibility=hidden' spirv-flags.txt +// RUN: grep '\-fno-autolink' spirv-flags.txt +// RUN: grep '\-fexceptions' spirv-flags.txt +// RUN: grep '\-fcolor-diagnostics' spirv-flags.txt +// RUN: grep '\-O3' spirv-flags.txt +// RUN: grep '\-mcode-object-version=5' spirv-flags.txt + +// RUN: rm spirv-flags.txt + +#include + +#define __constant__ __attribute__((constant)) +#define __device__ __attribute__((device)) +#define __global__ __attribute__((global)) +#define __host__ __attribute__((host)) +#define __shared__ __attribute__((shared)) +#define __managed__ __attribute__((managed)) +#define __launch_bounds__(...) __attribute__((launch_bounds(__VA_ARGS__))) + +struct dim3 { + unsigned x, y, z; + __host__ __device__ dim3(unsigned x, unsigned y = 1, unsigned z = 1) : x(x), y(y), z(z) {} +}; + +#ifdef __HIP__ +typedef struct hipStream *hipStream_t; +typedef enum hipError {} hipError_t; +int hipConfigureCall(dim3 gridSize, dim3 blockSize, size_t sharedSize = 0, + hipStream_t stream = 0); +extern "C" hipError_t __hipPushCallConfiguration(dim3 gridSize, dim3 blockSize, + size_t sharedSize = 0, + hipStream_t stream = 0); +extern "C" hipError_t hipLaunchKernel(const void *func, dim3 gridDim, + dim3 blockDim, void **args, + size_t sharedMem, + hipStream_t stream); +#endif + +__attribute__((device)) +void clean_value(float* ptr) { *ptr = 0; } + +__attribute__((global)) +void add_value(float* a, float* b, float* res) { + *res = *a + *b; + + clean_value(a); +} diff --git a/amd/comgr/test-lit/spirv-tests/spirv-translator.cl b/amd/comgr/test-lit/spirv-tests/spirv-translator.cl new file mode 100644 index 0000000000000..eeba901c722a2 --- /dev/null +++ b/amd/comgr/test-lit/spirv-tests/spirv-translator.cl @@ -0,0 +1,23 @@ +// REQUIRES: comgr-has-spirv +// COM: Enable this test once changes from amdspirv docker land + +// COM: Generate a spirv-targeted LLVM IR file from an OpenCL kernel +// RUN: clang -c -emit-llvm --target=spirv64 %s -o %t.bc + +// COM: Translate LLVM IR to SPIRV format +// RUN: amd-llvm-spirv --spirv-target-env=CL2.0 %t.bc -o %t.spv + +// COM: Run Comgr Translator to covert SPIRV back to LLVM IR +// RUN: spirv-translator %t.spv -o %t.translated.bc + +// COM: Dissasemble LLVM IR bitcode to LLVM IR text +// RUN: llvm-dis %t.translated.bc -o - | FileCheck %s + +// COM: Verify LLVM IR text +// CHECK: target triple = "spir64-unknown-unknown" +// CHECK: define spir_kernel void @source + +void kernel source(__global int *j) { + *j += 2; +} + diff --git a/amd/comgr/test-lit/spirv-tests/spirv-translator.hip b/amd/comgr/test-lit/spirv-tests/spirv-translator.hip new file mode 100644 index 0000000000000..a29e87ed486e0 --- /dev/null +++ b/amd/comgr/test-lit/spirv-tests/spirv-translator.hip @@ -0,0 +1,54 @@ +// REQUIRES: comgr-has-spirv +// COM: Generate a SPIRV file from a HIP kernel +// RUN: clang -x hip --offload-arch=amdgcnspirv -nogpulib -nogpuinc \ +// RUN: --no-gpu-bundle-output --offload-device-only -O3 %s -o %t.spv + +// COM: Run Comgr Translator to covert SPIRV back to LLVM IR +// RUN: spirv-translator %t.spv -o %t.translated.bc + +// COM: Dissasemble LLVM IR bitcode to LLVM IR text +// RUN: llvm-dis %t.translated.bc -o - | FileCheck %s + +// COM: Verify LLVM IR text +// CHECK: target triple = "amdgcn-amd-amdhsa" +// CHECK: define void @_Z11clean_valuePf +// CHECK: define amdgpu_kernel void @_Z9add_valuePfS_S_ + +#include + +#define __constant__ __attribute__((constant)) +#define __device__ __attribute__((device)) +#define __global__ __attribute__((global)) +#define __host__ __attribute__((host)) +#define __shared__ __attribute__((shared)) +#define __managed__ __attribute__((managed)) +#define __launch_bounds__(...) __attribute__((launch_bounds(__VA_ARGS__))) + +struct dim3 { + unsigned x, y, z; + __host__ __device__ dim3(unsigned x, unsigned y = 1, unsigned z = 1) : x(x), y(y), z(z) {} +}; + +#ifdef __HIP__ +typedef struct hipStream *hipStream_t; +typedef enum hipError {} hipError_t; +int hipConfigureCall(dim3 gridSize, dim3 blockSize, size_t sharedSize = 0, + hipStream_t stream = 0); +extern "C" hipError_t __hipPushCallConfiguration(dim3 gridSize, dim3 blockSize, + size_t sharedSize = 0, + hipStream_t stream = 0); +extern "C" hipError_t hipLaunchKernel(const void *func, dim3 gridDim, + dim3 blockDim, void **args, + size_t sharedMem, + hipStream_t stream); +#endif + +__attribute__((device)) +void clean_value(float* ptr) { *ptr = 0; } + +__attribute__((global)) +void add_value(float* a, float* b, float* res) { + *res = *a + *b; + + clean_value(a); +} diff --git a/amd/comgr/test-lit/status-string.c b/amd/comgr/test-lit/status-string.c new file mode 100644 index 0000000000000..6e04df4d8ca10 --- /dev/null +++ b/amd/comgr/test-lit/status-string.c @@ -0,0 +1,2 @@ +// COM: Check the Comgr status string API +// RUN: status-string diff --git a/amd/comgr/test-lit/time-statistics.cl b/amd/comgr/test-lit/time-statistics.cl new file mode 100644 index 0000000000000..2e546b2c434e4 --- /dev/null +++ b/amd/comgr/test-lit/time-statistics.cl @@ -0,0 +1,7 @@ +// COM: Check for any runtime errors with the Comgr Profilier +// RUN: AMD_COMGR_TIME_STATISTICS=1 compile-opencl-minimal %s %t.bin 1.2 +// RUN: test -f PerfStatsLog.txt + +void kernel add(__global float *A, __global float *B, __global float *C) { + *C = *A + *B; +} diff --git a/amd/comgr/test-lit/unbundle-test.hip b/amd/comgr/test-lit/unbundle-test.hip new file mode 100644 index 0000000000000..3ef312b50c834 --- /dev/null +++ b/amd/comgr/test-lit/unbundle-test.hip @@ -0,0 +1,28 @@ +// Create bitcode bundle +// RUN: clang -c -x hip --offload-arch=gfx900 --offload-arch=gfx1030 \ +// RUN: -nogpulib -nogpuinc -emit-llvm \ +// RUN: --gpu-bundle-output --offload-device-only \ +// RUN: %s -o %t.bundle.bc +// +// Create compressed bitcode bundle (add --offload-compress flag) +// RUN: clang -c -x hip --offload-arch=gfx900 --offload-arch=gfx1030 \ +// RUN: -nogpulib -nogpuinc -emit-llvm \ +// RUN: --gpu-bundle-output --offload-device-only \ +// RUN: --offload-compress \ +// RUN: %s -o %t.compressed-bundle.bc +// +// Extract using Comgr +// RUN: unbundle %t.bundle.bc hip-amdgcn-amd-amdhsa-unknown-gfx900 %t.gfx900.bc +// RUN: llvm-dis %t.gfx900.bc -o - | FileCheck --check-prefixes=BOTH,GFX9 %s +// +// RUN: unbundle %t.compressed-bundle.bc hip-amdgcn-amd-amdhsa-unknown-gfx1030 %t.compressed.gfx1030.bc +// RUN: llvm-dis %t.compressed.gfx1030.bc -o - | FileCheck --check-prefixes=BOTH,GFX10 %s +// +// BOTH: target triple = "amdgcn-amd-amdhsa" +// GFX9: "target-cpu"="gfx900" +// GFX10: "target-cpu"="gfx1030" + +__attribute__((device)) +void add_value(float* a, float* b, float* res) { + *res = *a + *b; +} diff --git a/amd/comgr/test-lit/vfs-tests/lit.local.cfg b/amd/comgr/test-lit/vfs-tests/lit.local.cfg new file mode 100644 index 0000000000000..78283bc64f747 --- /dev/null +++ b/amd/comgr/test-lit/vfs-tests/lit.local.cfg @@ -0,0 +1,2 @@ +config.environment['AMD_COMGR_EMIT_VERBOSE_LOGS'] = "1" +config.environment['AMD_COMGR_REDIRECT_LOGS'] = "stdout" diff --git a/amd/comgr/test-lit/vfs-tests/vfs-tests.cl b/amd/comgr/test-lit/vfs-tests/vfs-tests.cl new file mode 100644 index 0000000000000..3b5a7679041ce --- /dev/null +++ b/amd/comgr/test-lit/vfs-tests/vfs-tests.cl @@ -0,0 +1,72 @@ +// COM: Prefixes follow pattern (AMD_COMGR_SAVETEMPS)-(AMD_COMGR_USE_VFS)-(DataAction API) + +// COM: Default behavior right now is to use the real file system +// RUN: source-to-bc-with-dev-libs %s -o %t-with-dev-libs.bc | FileCheck --check-prefixes=STATUS,OUT-NA-NA-NA %s + +// COM: AMD_COMGR_USE_VFS=1 should force the compiler to use VFS, irrespective of the option provided via the DataAction API +// RUN: env AMD_COMGR_USE_VFS=1 source-to-bc-with-dev-libs %s --novfs -o %t-with-dev-libs.bc | FileCheck --check-prefixes=STATUS,OUT-NA-VFS-NOVFS %s +// RUN: env AMD_COMGR_USE_VFS=1 source-to-bc-with-dev-libs %s -o %t-with-dev-libs.bc | FileCheck --check-prefixes=STATUS,OUT-NA-VFS-NA %s + +// COM: AMD_COMGR_USE_VFS=0 should force the compiler to not use VFS, irrespective of the option provided via the DataAction API +// RUN: env AMD_COMGR_USE_VFS=0 source-to-bc-with-dev-libs %s --vfs -o %t-with-dev-libs.bc | FileCheck --check-prefixes=STATUS,OUT-NA-NOVFS-VFS %s +// RUN: env AMD_COMGR_USE_VFS=0 source-to-bc-with-dev-libs %s -o %t-with-dev-libs.bc | FileCheck --check-prefixes=STATUS,OUT-NA-NOVFS-NA %s + +// COM: No value for AMD_COMGR_USE_VFS should respect option provided via the DataAction API +// RUN: source-to-bc-with-dev-libs %s --vfs -o %t-with-dev-libs.bc | FileCheck --check-prefixes=STATUS,OUT-NA-NA-VFS %s +// RUN: source-to-bc-with-dev-libs %s --novfs -o %t-with-dev-libs.bc | FileCheck --check-prefixes=STATUS,OUT-NA-NA-NOVFS %s + +// COM: AMD_COMGR_SAVE_TEMPS=1 should override all options and always use the real file system +// RUN: env AMD_COMGR_SAVE_TEMPS=1 source-to-bc-with-dev-libs %s --vfs -o %t-with-dev-libs.bc | FileCheck --check-prefixes=STATUS,OUT-SAVETEMPS-NA-VFS %s +// RUN: env AMD_COMGR_SAVE_TEMPS=1 AMD_COMGR_USE_VFS=1 source-to-bc-with-dev-libs %s -o %t-with-dev-libs.bc | FileCheck --check-prefixes=STATUS,OUT-SAVETEMPS-VFS-NA %s +// RUN: env AMD_COMGR_SAVE_TEMPS=1 AMD_COMGR_USE_VFS=1 source-to-bc-with-dev-libs %s --vfs -o %t-with-dev-libs.bc | FileCheck --check-prefixes=STATUS,OUT-SAVETEMPS-VFS-VFS %s + +// OUT-NA-NA-NA: File System: VFS +// OUT-NA-VFS-NOVFS: File System: VFS +// OUT-NA-VFS-NA: File System: VFS +// OUT-NA-NOVFS-VFS: File System: Real +// OUT-NA-NOVFS-NA: File System: Real +// OUT-NA-NA-VFS: File System: VFS +// OUT-NA-NA-NOVFS: File System: Real +// OUT-SAVETEMPS-NA-VFS: File System: Real +// OUT-SAVETEMPS-VFS-VFS: File System: Real +// OUT-SAVETEMPS-VFS-NA: File System: Real + +// COM: Verify success of compilation for all scenarios +// STATUS: ReturnStatus: AMD_COMGR_STATUS_SUCCESS + +extern const __constant bool __oclc_finite_only_opt; +extern const __constant bool __oclc_unsafe_math_opt; +extern const __constant bool __oclc_correctly_rounded_sqrt32; +extern const __constant bool __oclc_wavefrontsize64; +extern const __constant int __oclc_ISA_version; +extern const __constant int __oclc_ABI_version; + +void kernel device_libs(__global float *status) { + + if (__oclc_finite_only_opt) status[0] = 1.0; + if (__oclc_unsafe_math_opt) status[1] = 1.0; + if (__oclc_correctly_rounded_sqrt32) status[3] = 1.0; + if (__oclc_wavefrontsize64) status[4] = 1.0; + if (__oclc_ISA_version) status[5] = 1.0; + if (__oclc_ABI_version) status[6] = 1.0; + + // Math functions to test AMDGPULibCalls Folding optimizations + // fold_sincos() + float x = 0.25; + status[7] = sin(x) + cos(x); + status[8] = cos(x) + sin(x); + + // fold_rootn() + float y = 725.0; + status[9] = rootn(y, 3); + status[10] = rootn(y, -1); + status[11] = rootn(y, -2); + + // fold_pow() + float z = 12.16; + status[12] = pow(z, (float) 0.5); + status[13] = powr(y, (float) 7.23); + + // printf() + printf("testy\n"); +} diff --git a/amd/comgr/test/CMakeLists.txt b/amd/comgr/test/CMakeLists.txt new file mode 100644 index 0000000000000..7cdcd0202affc --- /dev/null +++ b/amd/comgr/test/CMakeLists.txt @@ -0,0 +1,240 @@ +set(TEST_INPUT_BINARIES) +set(TEST_INPUT_BITCODES) +set(TEST_INPUT_BUNDLES) +set(TEST_INPUT_ARCHIVES) +set(TEST_INPUT_LINKED_OBJS) + +# Create target ${name} which depends on a clang command to compile ${input} to +# ${output}, with any additional arguments from ${ARGN}, and add it to the +# TEST_INPUT_BINARIES target list. +macro(add_test_input_binary name input output) + add_custom_command( + OUTPUT "${output}" + COMMAND "$" --target=amdgcn-amd-amdhsa -mcpu=gfx900 -nogpulib -nogpuinc + ${ARGN} "${CMAKE_CURRENT_SOURCE_DIR}/${input}" -o "${output}" + VERBATIM + DEPENDS clang lld "${input}") + add_custom_target("${name}" + DEPENDS "${output}" + SOURCES "${input}") + list(APPEND TEST_INPUT_BINARIES "${name}") +endmacro() + +# Creates target ${name} which depends on a clang command to compile ${input} to +# ${output}, with any additional arguments from ${ARGN}, and add it to the +# TEST_INPUT_BITCODES target list. +macro(add_test_input_bitcode name input output) + add_custom_command( + OUTPUT "${output}" + COMMAND "$" -c -emit-llvm -target amdgcn-amd-amdhsa + -mcpu=gfx900 -nogpulib -nogpuinc + ${ARGN} "${CMAKE_CURRENT_SOURCE_DIR}/${input}" + -o "${output}" + VERBATIM + DEPENDS clang lld "${input}") + add_custom_target("${name}" + DEPENDS "${output}" + SOURCES "${input}") + list(APPEND TEST_INPUT_BITCODES "${name}") +endmacro() + +# Creates target ${name} which depends on a clang command to compile ${input} to +# ${output}, with any additional arguments from ${ARGN}, and add it to the +# TEST_INPUT_BUNDLES target list. +macro(add_test_input_bitcode_bundle name input output) + add_custom_command( + OUTPUT "${output}" + COMMAND "$" -c --offload-arch=gfx900 -emit-llvm + --gpu-bundle-output ${ARGN} "${CMAKE_CURRENT_SOURCE_DIR}/${input}" -nogpulib -nogpuinc + --offload-device-only -o "${output}" + VERBATIM + DEPENDS clang lld "${input}") + add_custom_target("${name}" + DEPENDS "${output}" + SOURCES "${input}") + list(APPEND TEST_INPUT_BUNDLES "${name}") +endmacro() + +# Creates target ${name} which depends on a clang command to compile ${input} to +# ${output}, with any additional arguments from ${ARGN}, and add it to the +# TEST_INPUT_BUNDLES target list. +macro(add_test_input_object_file_bundle name input output) + add_custom_command( + OUTPUT "${output}" + COMMAND "$" -c --offload-arch=gfx900 --gpu-bundle-output + --offload-device-only ${ARGN} "${CMAKE_CURRENT_SOURCE_DIR}/${input}" -nogpulib -nogpuinc + -o "${output}" + VERBATIM + DEPENDS clang lld "${input}") + add_custom_target("${name}" + DEPENDS "${output}" + SOURCES "${input}") + list(APPEND TEST_INPUT_BUNDLES "${name}") +endmacro() + +# Creates target ${name} and output ${output} by archiving a file. +# ${target} should refer to the a target created in the above +# add_test_input_bitcode() macro, and ${input} should refer +# to the associated bitcode file built by the same macro. +macro(add_test_archive name target input output) + add_custom_command( + OUTPUT "${output}" + COMMAND "$" rc "${output}" "${input}" + VERBATIM + DEPENDS clang lld ${target}) + add_custom_target("${name}" + DEPENDS "${output}" + SOURCES "${input}") + list(APPEND TEST_INPUT_ARCHIVES "${name}") +endmacro() + +# Creates target ${name} which depends on 2 clang commands to compile +# ${input0} and ${input1} and then links them to create ${output} +# with any additional arguments from ${ARGN}, and add it to the +# TEST_INPUT_LINKED_OBJS target list. +macro(add_test_input_linked name input0 input1 output) + add_custom_command( + OUTPUT "${output}" + COMMAND "$" -flavor gnu ${ARGN} "${input0}" + "${input1}" -o "${output}" + VERBATIM + DEPENDS lld "${input0}" "${input1}") + add_custom_target("${name}" + DEPENDS "${output}" + SOURCES "${input0}" "${input1}") + list(APPEND TEST_INPUT_LINKED_OBJS "${name}") +endmacro() + +add_test_input_binary(reloc1 source/reloc1.cl source/reloc1.o -c -mcode-object-version=4) +add_test_input_binary(reloc2 source/reloc2.cl source/reloc2.o -c -mcode-object-version=4) +add_test_input_binary(reloc-asm source/reloc-asm.s source/reloc-asm.o -c -mcode-object-version=4) +add_test_input_binary(shared source/shared.cl source/shared.so -mcode-object-version=4) +add_test_input_binary(symbolize-debug source/symbolize.cl source/symbolize-debug.so -c -g -O3 -mcode-object-version=4) +add_test_input_bitcode(source1 source/source1.cl source/source1.bc) + +add_test_input_binary(linking-kernel0 source/linking/kernel0.cl source/linking/kernel0.o -c -mcode-object-version=4) +add_test_input_binary(linking-kernel1 source/linking/kernel1.cl source/linking/kernel1.o -c -mcode-object-version=4) +add_test_input_binary(linking-empty source/linking/empty.cl source/linking/empty.o -c -mcode-object-version=4) + +add_test_input_linked(multiple-note-records source/linking/kernel0.o source/linking/kernel1.o source/multiple-note-records.out -w) +add_test_input_linked(multiple-note-records-one-kernel source/linking/kernel0.o source/linking/empty.o source/multiple-note-records-one-kernel.out -w) + +add_test_input_bitcode_bundle(square source/square.hip source/square.bc) +add_test_input_object_file_bundle(double source/double.hip source/double.o) + +add_test_input_bitcode_bundle(cube source/cube.hip source/cube.bc) +add_test_archive(cube_archive cube source/cube.bc source/cube.a) + +configure_file("source/linking/kernel0.cl" "source/linking/kernel0.cl" COPYONLY) +configure_file("source/linking/kernel1.cl" "source/linking/kernel1.cl" COPYONLY) +configure_file("source/linking/empty.cl" "source/linking/empty.cl" COPYONLY) +configure_file("source/source1.cl" "source/source1.cl" COPYONLY) +configure_file("source/source2.cl" "source/source2.cl" COPYONLY) +configure_file("source/nested-kernel1.cl" "source/nested-kernel1.cl" COPYONLY) +configure_file("source/nested-kernel2.cl" "source/nested-kernel2.cl" COPYONLY) +configure_file("source/shared.cl" "source/shared.cl" COPYONLY) +configure_file("source/symbolize.cl" "source/symbolize.cl" COPYONLY) +configure_file("source/device_libs.cl" "source/device_libs.cl" COPYONLY) +configure_file("source/include-macro.h" "source/include-macro.h" COPYONLY) +configure_file("source/include-nested.h" "source/include-nested.h" COPYONLY) +configure_file("source/source1.s" "source/source1.s" COPYONLY) +configure_file("source/source1.hip" "source/source1.hip" COPYONLY) +configure_file("source/name-expression.hip" "source/name-expression.hip" COPYONLY) +configure_file("source/rocm56slice.b" "source/rocm56slice.b" COPYONLY) +configure_file("source/rocm57slice.b" "source/rocm57slice.b" COPYONLY) + +configure_file("source/square.hip" "source/square.hip" COPYONLY) +configure_file("source/double.hip" "source/double.hip" COPYONLY) +configure_file("source/cube.hip" "source/cube.hip" COPYONLY) + +# We no longer support emission of code object v2/v3. The runtime however +# can still load them so we need to test them using prebuilt binaries. +configure_file("source/legacy/shared-v2.so" "source/shared-v2.so" COPYONLY) +configure_file("source/legacy/shared12-v2.so" "source/shared12-v2.so" COPYONLY) +configure_file("source/legacy/shared14-v2.so" "source/shared14-v2.so" COPYONLY) +configure_file("source/legacy/shared23-v2.so" "source/shared23-v2.so" COPYONLY) +configure_file("source/legacy/source1-v2.o" "source/source1-v2.o" COPYONLY) +configure_file("source/legacy/source2-v2.o" "source/source2-v2.o" COPYONLY) +configure_file("source/legacy/source3-v2.o" "source/source3-v2.o" COPYONLY) +configure_file("source/legacy/source4-v2.o" "source/source4-v2.o" COPYONLY) + +configure_file("source/legacy/shared-v3.so" "source/shared-v3.so" COPYONLY) +configure_file("source/legacy/shared12-v3.so" "source/shared12-v3.so" COPYONLY) +configure_file("source/legacy/shared14-v3.so" "source/shared14-v3.so" COPYONLY) +configure_file("source/legacy/shared23-v3.so" "source/shared23-v3.so" COPYONLY) +configure_file("source/legacy/source1-v3.o" "source/source1-v3.o" COPYONLY) +configure_file("source/legacy/source2-v3.o" "source/source2-v3.o" COPYONLY) +configure_file("source/legacy/source3-v3.o" "source/source3-v3.o" COPYONLY) +configure_file("source/legacy/source4-v3.o" "source/source4-v3.o" COPYONLY) + +# Creates executable ${name} and accompanying test ${name} built from +# test/${name}.cl +macro(add_comgr_test name lang) + set(test_name "comgr_${name}") + add_executable("${name}" "${name}.${lang}") + set_target_properties("${name}" PROPERTIES + C_STANDARD 99 + C_STANDARD_REQUIRED Yes + C_EXTENSIONS No) + target_compile_definitions("${name}" + PRIVATE -DTEST_OBJ_DIR=\"${CMAKE_CURRENT_BINARY_DIR}/source\") +if (CMAKE_CXX_COMPILER_ID STREQUAL "MSVC") + target_compile_definitions("${name}" + PRIVATE -D_CRT_SECURE_NO_WARNINGS) +endif() + + target_link_libraries("${name}" + amd_comgr) + add_dependencies("${name}" + ${TEST_INPUT_BINARIES};${TEST_INPUT_BITCODES};${TEST_INPUT_BUNDLES}; + ${TEST_INPUT_ARCHIVES};${TEST_INPUT_LINKED_OBJS}) + add_test(NAME ${test_name} + COMMAND "${name}") + add_dependencies(check-comgr ${name}) + # Windows binaries have no equivalent to RPATH, so we must set their PATH to + # include the .lib/.dll directory. + if (UNIX) + set_tests_properties(${test_name} + PROPERTIES ENVIRONMENT "AMD_COMGR_CACHE=0;") + else() + set_tests_properties(${test_name} + PROPERTIES ENVIRONMENT "PATH=$;AMD_COMGR_CACHE=0;") + endif() +endmacro() + +find_package(hip CONFIG PATHS ${ROCM_INSTALL_PATH}/hip QUIET) + +add_comgr_test(data_test c) +add_comgr_test(disasm_instr_test c) +add_comgr_test(metadata_tp_test c) +add_comgr_test(metadata_yaml_test c) +add_comgr_test(metadata_msgpack_test c) +add_comgr_test(metadata_multiple_msgpacks_test c) +add_comgr_test(metadata_merge_test c) +add_comgr_test(symbols_test c) +add_comgr_test(symbols_iterate_test c) +add_comgr_test(compile_test c) +add_comgr_test(compile_minimal_test c) +add_comgr_test(compile_log_test c) +add_comgr_test(compile_log_remarks_test c) +add_comgr_test(compile_source_with_device_libs_to_bc_test c) +add_comgr_test(compile_source_with_device_libs_to_bc_with_vfs_test c) +add_comgr_test(assemble_test c) +add_comgr_test(link_test c) +add_comgr_test(isa_name_parsing_test c) +add_comgr_test(get_data_isa_name_test c) +add_comgr_test(include_subdirectory_test c) +add_comgr_test(demangle_test c) +add_comgr_test(fail_to_build_driver c) +add_comgr_test(file_map c) +add_comgr_test(symbolize_test c) +add_comgr_test(mangled_names_test c) +add_comgr_test(multithread_test cpp) +add_comgr_test(nested_kernel_test c) +add_comgr_test(map_elf_virtual_address_test c) +add_comgr_test(compile_source_to_executable c) +add_comgr_test(name_expression_map_test c) +add_comgr_test(compile_hip_test c) +add_comgr_test(compile_hip_to_relocatable c) +add_comgr_test(mangled_names_hip_test c) +#add_comgr_test(unbundle_hip_test c) diff --git a/amd/comgr/test/assemble_test.c b/amd/comgr/test/assemble_test.c new file mode 100644 index 0000000000000..9b73c368cff10 --- /dev/null +++ b/amd/comgr/test/assemble_test.c @@ -0,0 +1,95 @@ +//===- assemble_test.c ----------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + size_t Size1; + char *Buf1; + amd_comgr_data_t DataIn1; + amd_comgr_data_set_t DataSetIn, DataSetOut; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + + // Read input file + Size1 = setBuf(TEST_OBJ_DIR "/source1.s", &Buf1); + + // Create data object + { + printf("Test create input data set\n"); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_cogmr_create_data_set"); + + // File 1 + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataIn1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataIn1, Size1, Buf1); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataIn1, "source1_no_extension"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataIn1); + checkError(Status, "amd_cogmr_data_set_add"); + } + + { + printf("Test create empty output data set\n"); + + Status = amd_comgr_create_data_set(&DataSetOut); + checkError(Status, "amd_cogmr_create_data_set"); + } + + { + printf("Test action assemble\n"); + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + amd_comgr_action_info_set_isa_name(DataAction, "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + Status = + amd_comgr_do_action(AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE, + DataAction, DataSetIn, DataSetOut); + checkError(Status, "amd_comgr_do_action"); + } + + { + printf("Test action outputs\n"); + // There should be two output data object + size_t Count; + Status = amd_comgr_action_data_count( + DataSetOut, AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + if (Count == 1) { + printf("Passed, output 1 relocatable object\n"); + } else { + printf("Failed, output %zd relocatable objects (should output 1)\n", + Count); + exit(1); + } + } + + { + printf("Cleanup ...\n"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetOut); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + Status = amd_comgr_release_data(DataIn1); + checkError(Status, "amd_comgr_release_data"); + free(Buf1); + } + + return 0; +} diff --git a/amd/comgr/test/common.h b/amd/comgr/test/common.h new file mode 100644 index 0000000000000..cdbf4431f69a3 --- /dev/null +++ b/amd/comgr/test/common.h @@ -0,0 +1,334 @@ +//===- common.h -----------------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef COMGR_TEST_COMMON_H +#define COMGR_TEST_COMMON_H + +#include "amd_comgr.h" +#include +#include +#include +#include +#include + +#if !defined(_WIN32) && !defined(_WIN64) +#include +#include +#include +#else // Windows +#include +#endif +#include +#include + +#if defined(_WIN64) +typedef __int64 ssize_t; +#elif defined(_WIN32) +typedef long ssize_t; +#endif + +void fail(const char *format, ...) { + va_list ap; + va_start(ap, format); + + printf("FAILED: "); + vprintf(format, ap); + printf("\n"); + + va_end(ap); + + exit(1); +} + +int setBuf(const char *infile, char **buf) { + FILE *fp; + long size; + + fp = fopen(infile, "rb"); + if (!fp) + fail("fopen : %s", infile); + if (fseek(fp, 0L, SEEK_END) != 0) + fail("fopen"); + size = ftell(fp); + if (size == -1) + fail("ftell"); + if (fseek(fp, 0, SEEK_SET) != 0) + fail("fseek"); + + *buf = (char *)malloc(size + 1); + if (!*buf) + fail("malloc"); + if (fread(*buf, size, 1, fp) != 1) + fail("fread"); + if (fclose(fp) != 0) + fail("fclose"); + (*buf)[size] = 0; // terminating zero + return size; +} + +void checkStatus(amd_comgr_status_t status, amd_comgr_status_t expected, + const char *str) { + if (status != expected) { + const char *statusStr; + printf("FAILED: %s\n", str); + status = amd_comgr_status_string(status, &statusStr); + if (status == AMD_COMGR_STATUS_SUCCESS) + printf(" REASON: %s\n", statusStr); + exit(1); + } +} + +void checkError(amd_comgr_status_t status, const char *str) { + checkStatus(status, AMD_COMGR_STATUS_SUCCESS, str); +} + +void dumpData(amd_comgr_data_t Data, const char *OutFile) { + size_t size; + char *bytes = NULL; + amd_comgr_status_t status; + + status = amd_comgr_get_data(Data, &size, NULL); + checkError(status, "amd_comgr_get_data"); + + bytes = (char *)malloc(size); + if (!bytes) + fail("malloc"); + + status = amd_comgr_get_data(Data, &size, bytes); + checkError(status, "amd_comgr_get_data"); + + FILE *fp = fopen(OutFile, "wb"); + if (!fp) + fail("fopen : %s", OutFile); + + size_t ret = fwrite(bytes, sizeof(char), size, fp); + if (ret != size) + fail("fwrite"); + + free(bytes); + fclose(fp); +} + +amd_comgr_status_t printSymbol(amd_comgr_symbol_t symbol, void *userData) { + amd_comgr_status_t status; + if (userData == NULL) + return AMD_COMGR_STATUS_ERROR; + + size_t nlen; + status = amd_comgr_symbol_get_info(symbol, AMD_COMGR_SYMBOL_INFO_NAME_LENGTH, + (void *)&nlen); + checkError(status, "amd_comgr_symbol_get_info_1"); + + char *name = (char *)malloc(nlen + 1); + status = amd_comgr_symbol_get_info(symbol, AMD_COMGR_SYMBOL_INFO_NAME, + (void *)name); + checkError(status, "amd_comgr_symbol_get_info_2"); + + amd_comgr_symbol_type_t type; + status = amd_comgr_symbol_get_info(symbol, AMD_COMGR_SYMBOL_INFO_TYPE, + (void *)&type); + checkError(status, "amd_comgr_symbol_get_info_3"); + + uint64_t size; + status = amd_comgr_symbol_get_info(symbol, AMD_COMGR_SYMBOL_INFO_SIZE, + (void *)&size); + checkError(status, "amd_comgr_symbol_get_info_4"); + + bool undefined; + status = amd_comgr_symbol_get_info(symbol, AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED, + (void *)&undefined); + checkError(status, "amd_comgr_symbol_get_info_5"); + + uint64_t value; + status = amd_comgr_symbol_get_info(symbol, AMD_COMGR_SYMBOL_INFO_VALUE, + (void *)&value); + checkError(status, "amd_comgr_symbol_get_info_6"); + + printf("%d: name=%s, type=%d, size=%" PRIu64 ", undef:%d, value:%" PRIu64 + "I64u\n", + *(int *)userData, name, type, size, undefined ? 1 : 0, value); + *(int *)userData += 1; + + free(name); + + return status; +} + +amd_comgr_status_t printEntry(amd_comgr_metadata_node_t key, + amd_comgr_metadata_node_t value, void *data) { + amd_comgr_metadata_kind_t kind; + amd_comgr_metadata_node_t son; + amd_comgr_status_t status; + size_t size; + char *keybuf; + char *valbuf; + int *indent = (int *)data; + + // assume key to be string in this test function + status = amd_comgr_get_metadata_kind(key, &kind); + checkError(status, "amd_comgr_get_metadata_kind"); + if (kind != AMD_COMGR_METADATA_KIND_STRING) + return AMD_COMGR_STATUS_ERROR; + status = amd_comgr_get_metadata_string(key, &size, NULL); + checkError(status, "amd_comgr_get_metadata_string"); + keybuf = (char *)calloc(size, sizeof(char)); + if (!keybuf) + fail("calloc"); + status = amd_comgr_get_metadata_string(key, &size, keybuf); + checkError(status, "amd_comgr_get_metadata_string"); + + status = amd_comgr_get_metadata_kind(value, &kind); + checkError(status, "amd_comgr_get_metadata_kind"); + for (int i = 0; i < *indent; i++) + printf(" "); + + switch (kind) { + case AMD_COMGR_METADATA_KIND_STRING: { + printf("%s : ", size ? keybuf : ""); + status = amd_comgr_get_metadata_string(value, &size, NULL); + checkError(status, "amd_comgr_get_metadata_string"); + valbuf = (char *)calloc(size, sizeof(char)); + if (!valbuf) + fail("calloc"); + status = amd_comgr_get_metadata_string(value, &size, valbuf); + checkError(status, "amd_comgr_get_metadata_string"); + printf(" %s\n", valbuf); + free(valbuf); + break; + } + case AMD_COMGR_METADATA_KIND_LIST: { + *indent += 1; + status = amd_comgr_get_metadata_list_size(value, &size); + checkError(status, "amd_comgr_get_metadata_list_size"); + printf("LIST %s %zd entries = \n", keybuf, size); + for (size_t i = 0; i < size; i++) { + status = amd_comgr_index_list_metadata(value, i, &son); + checkError(status, "amd_comgr_index_list_metadata"); + status = printEntry(key, son, data); + checkError(status, "printEntry"); + status = amd_comgr_destroy_metadata(son); + checkError(status, "amd_comgr_destroy_metadata"); + } + *indent = *indent > 0 ? *indent - 1 : 0; + break; + } + case AMD_COMGR_METADATA_KIND_MAP: { + *indent += 1; + status = amd_comgr_get_metadata_map_size(value, &size); + checkError(status, "amd_comgr_get_metadata_map_size"); + printf("MAP %zd entries = \n", size); + status = amd_comgr_iterate_map_metadata(value, printEntry, data); + checkError(status, "amd_comgr_iterate_map_metadata"); + *indent = *indent > 0 ? *indent - 1 : 0; + break; + } + default: + free(keybuf); + return AMD_COMGR_STATUS_ERROR; + } // switch + + free(keybuf); + return AMD_COMGR_STATUS_SUCCESS; +} + +void checkLogs(const char *id, amd_comgr_data_set_t dataSet, + const char *expected) { + amd_comgr_status_t status; + + size_t count; + status = + amd_comgr_action_data_count(dataSet, AMD_COMGR_DATA_KIND_LOG, &count); + checkError(status, "amd_comgr_action_data_count"); + + for (size_t i = 0; i < count; i++) { + amd_comgr_data_t data; + status = amd_comgr_action_data_get_data(dataSet, AMD_COMGR_DATA_KIND_LOG, i, + &data); + checkError(status, "amd_comgr_action_data_get_data"); + + size_t size; + status = amd_comgr_get_data(data, &size, NULL); + checkError(status, "amd_comgr_get_data"); + + char *bytes = (char *)malloc(size + 1); + if (!bytes) + fail("malloc"); + status = amd_comgr_get_data(data, &size, bytes); + checkError(status, "amd_comgr_get_data"); + bytes[size] = '\0'; + + if (!strstr(bytes, expected)) { + printf("%s failed: expected substring \"%s\" not found in log:\n%s", id, + expected, bytes); + exit(1); + } + + free(bytes); + + status = amd_comgr_release_data(data); + checkError(status, "amd_comgr_release_data"); + } +} + +// FIXME: This should probably be defined by Comgr +const char *dataKindString(amd_comgr_data_kind_t dataKind) { + static const char *strings[AMD_COMGR_DATA_KIND_FATBIN + 1] = { + "AMD_COMGR_DATA_KIND_UNDEF", + "AMD_COMGR_DATA_KIND_SOURCE", + "AMD_COMGR_DATA_KIND_INCLUDE", + "AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER", + "AMD_COMGR_DATA_KIND_DIAGNOSTIC", + "AMD_COMGR_DATA_KIND_LOG", + "AMD_COMGR_DATA_KIND_BC", + "AMD_COMGR_DATA_KIND_RELOCATABLE", + "AMD_COMGR_DATA_KIND_EXECUTABLE", + "AMD_COMGR_DATA_KIND_BYTES", + "AMD_COMGR_DATA_KIND_FATBIN", + }; + return strings[dataKind]; +} + +void checkCount(const char *id, amd_comgr_data_set_t dataSet, + amd_comgr_data_kind_t dataKind, size_t expected) { + amd_comgr_status_t status; + + size_t count; + status = amd_comgr_action_data_count(dataSet, dataKind, &count); + checkError(status, "checkCount:amd_comgr_action_data_count"); + + if (count != expected) + fail("%s failed: produced %zu %s objects (expected %zu)\n", id, count, + dataKindString(dataKind), expected); +} + +size_t WriteFileCustom(int FD, const char *Buffer, size_t Size) { + size_t BytesWritten = 0; + + while (BytesWritten < Size) { +#if defined(_WIN32) || defined(_WIN64) + ssize_t Ret = + _write(FD, Buffer + BytesWritten, (unsigned int)(Size - BytesWritten)); +#else + ssize_t Ret = write(FD, Buffer + BytesWritten, Size - BytesWritten); +#endif + if (Ret == 0) { + break; + } else if (Ret < 0) { + if (errno != EAGAIN && errno != EWOULDBLOCK && errno != EINTR) { + break; + } + printf("Write failed with errno %d\n", errno); + } else { + BytesWritten += Ret; + } + } + + return BytesWritten; +} + +#endif // COMGR_TEST_COMMON_H diff --git a/amd/comgr/test/compile_hip_test.c b/amd/comgr/test/compile_hip_test.c new file mode 100644 index 0000000000000..e83580c671812 --- /dev/null +++ b/amd/comgr/test/compile_hip_test.c @@ -0,0 +1,101 @@ +//===- compile_hip_test.c -------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int Argc, char *Argv[]) { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSrc; + amd_comgr_data_set_t DataSetSrc, DataSetBc, DataSetLinkedBc, DataSetAsm, + DataSetReloc, DataSetExec; + amd_comgr_action_info_t ActionInfo; + amd_comgr_status_t Status; + const char *CompileOptions[] = {"-nogpulib", "-nogpuinc"}; + size_t CompileOptionsCount = + sizeof(CompileOptions) / sizeof(CompileOptions[0]); + + SizeSource = setBuf(TEST_OBJ_DIR "/source1.hip", &BufSource); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSrc); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSrc, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSrc, "source1.hip"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_create_data_set(&DataSetSrc); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_data_set_add(DataSetSrc, DataSrc); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&ActionInfo); + checkError(Status, "amd_comgr_create_action_info"); + Status = + amd_comgr_action_info_set_language(ActionInfo, AMD_COMGR_LANGUAGE_HIP); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(ActionInfo, + "amdgcn-amd-amdhsa--gfx906"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + Status = amd_comgr_action_info_set_option_list(ActionInfo, CompileOptions, + CompileOptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action( + AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, ActionInfo, + DataSetSrc, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_create_data_set(&DataSetLinkedBc); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, ActionInfo, + DataSetBc, DataSetLinkedBc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_create_data_set(&DataSetAsm); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY, + ActionInfo, DataSetLinkedBc, DataSetAsm); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + ActionInfo, DataSetLinkedBc, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + ActionInfo, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_destroy_action_info(ActionInfo); + checkError(Status, "amd_comgr_destroy_action_info"); + Status = amd_comgr_destroy_data_set(DataSetSrc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinkedBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetAsm); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_release_data(DataSrc); + checkError(Status, "amd_comgr_release_data"); + + free(BufSource); +} diff --git a/amd/comgr/test/compile_hip_to_relocatable.c b/amd/comgr/test/compile_hip_to_relocatable.c new file mode 100644 index 0000000000000..d682244efc8f0 --- /dev/null +++ b/amd/comgr/test/compile_hip_to_relocatable.c @@ -0,0 +1,106 @@ +//===- compile_hip_to_relocatable.c ---------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource1; + amd_comgr_data_set_t DataSetIn, DataSetReloc, DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + const char *CompileOptions[] = {"-fno-slp-vectorize", "-nogpulib", + "-nogpuinc"}; + size_t CompileOptionsCount = + sizeof(CompileOptions) / sizeof(CompileOptions[0]); + + SizeSource = setBuf(TEST_OBJ_DIR "/source1.hip", &BufSource); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource1, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource1, "source1.hip"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource1); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = + amd_comgr_action_info_set_language(DataAction, AMD_COMGR_LANGUAGE_HIP); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx906"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + + Status = amd_comgr_action_info_set_option_list(DataAction, CompileOptions, + CompileOptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE, + DataAction, DataSetIn, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + size_t Count; + Status = amd_comgr_action_data_count(DataSetReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_RELOCATABLE " + "Failed: " + "produced %zu RELOC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_release_data(DataSource1); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource); +} diff --git a/amd/comgr/test/compile_log_remarks_test.c b/amd/comgr/test/compile_log_remarks_test.c new file mode 100644 index 0000000000000..ab13ea435ab2d --- /dev/null +++ b/amd/comgr/test/compile_log_remarks_test.c @@ -0,0 +1,101 @@ +//===- compile_log_remarks_test.c -----------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +#undef unsetenv +#ifdef _WIN32 +#define unsetenv(name) _putenv_s(name, "") +#else +#if !HAVE_DECL_UNSETENV +#if VOID_UNSETENV +extern void unsetenv(const char *); +#else +extern int unsetenv(const char *); +#endif +#endif +#endif + +int main(int argc, char *argv[]) { + + // For this test to pass when redirecting logs to stdout, + // we need to temporarily undo the redirect + if (getenv("AMD_COMGR_REDIRECT_LOGS") && + (!strcmp("stdout", getenv("AMD_COMGR_REDIRECT_LOGS")) || + !strcmp("stderr", getenv("AMD_COMGR_REDIRECT_LOGS")))) + unsetenv("AMD_COMGR_REDIRECT_LOGS"); + + amd_comgr_data_t DataCl; + amd_comgr_data_set_t DataSetCl, DataSetBc, DataSetAsm; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + + const char *Buf = "kernel void f() { volatile int x = 0; }"; + size_t Size = strlen(Buf); + + Status = amd_comgr_create_data_set(&DataSetCl); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataCl); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataCl, Size, Buf); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataCl, "empty.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetCl, DataCl); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + Status = amd_comgr_action_info_set_logging(DataAction, true); + checkError(Status, "amd_comgr_action_info_set_logging"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, + DataAction, DataSetCl, DataSetBc); + checkError(Status, "AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC"); + checkCount("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC", DataSetBc, + AMD_COMGR_DATA_KIND_BC, 1); + + Status = amd_comgr_create_data_set(&DataSetAsm); + checkError(Status, "amd_comgr_create_data_set"); + const char *Options[] = {"-Rpass-analysis=prolog"}; + size_t Count = sizeof(Options) / sizeof(Options[0]); + Status = amd_comgr_action_info_set_option_list(DataAction, Options, Count); + checkError(Status, "amd_comgr_action_info_set_option_list"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY, + DataAction, DataSetBc, DataSetAsm); + checkError(Status, "AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY"); + checkCount("AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY", DataSetAsm, + AMD_COMGR_DATA_KIND_SOURCE, 1); + + checkLogs("AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY", DataSetAsm, + "remark: :0:0: 8 stack bytes in function 'f' " + "[-Rpass-analysis=prologepilog]"); + + Status = amd_comgr_destroy_data_set(DataSetCl); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetAsm); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + Status = amd_comgr_release_data(DataCl); + checkError(Status, "amd_comgr_release_data"); +} diff --git a/amd/comgr/test/compile_log_test.c b/amd/comgr/test/compile_log_test.c new file mode 100644 index 0000000000000..424319936436f --- /dev/null +++ b/amd/comgr/test/compile_log_test.c @@ -0,0 +1,240 @@ +//===- compile_log_test.c -------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +#undef unsetenv +#ifdef _WIN32 +#define unsetenv(name) _putenv_s(name, "") +#else +#if !HAVE_DECL_UNSETENV +#if VOID_UNSETENV +extern void unsetenv(const char *); +#else +extern int unsetenv(const char *); +#endif +#endif +#endif + +int main(int argc, char *argv[]) { + + // For this test to pass when redirecting logs to stdout, + // we need to temporarily undo the redirect + if (getenv("AMD_COMGR_REDIRECT_LOGS") && + (!strcmp("stdout", getenv("AMD_COMGR_REDIRECT_LOGS")) || + !strcmp("stderr", getenv("AMD_COMGR_REDIRECT_LOGS")))) + unsetenv("AMD_COMGR_REDIRECT_LOGS"); + + amd_comgr_data_t DataCl, DataAsm, DataBc, DataReloc; + amd_comgr_data_set_t DataSetOut, DataSetCl, DataSetAsm, DataSetBc, + DataSetReloc; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + + size_t Count; + const char *Buf = "invalid"; + size_t Size = strlen(Buf); + + Status = amd_comgr_create_data_set(&DataSetCl); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataCl); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataCl, Size, Buf); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataCl, "invalid.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetCl, DataCl); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data_set(&DataSetAsm); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataAsm); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataAsm, Size, Buf); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataAsm, "invalid.s"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetAsm, DataAsm); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_BC, &DataBc); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataBc, Size, Buf); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataBc, "invalid.bc"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetBc, DataBc); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &DataReloc); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataReloc, Size, Buf); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataReloc, "invalid.o"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetReloc, DataReloc); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + Status = amd_comgr_action_info_set_logging(DataAction, true); + checkError(Status, "amd_comgr_action_info_set_logging"); + + // AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC + + Status = amd_comgr_create_data_set(&DataSetOut); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, + DataAction, DataSetCl, DataSetOut); + checkLogs("COMPILE_SOURCE_TO_BC", DataSetOut, + "error: unknown type name 'invalid'"); + checkLogs("COMPILE_SOURCE_TO_BC", DataSetOut, "2 errors generated."); + + Status = + amd_comgr_action_data_count(DataSetOut, AMD_COMGR_DATA_KIND_LOG, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu LOG objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_destroy_data_set(DataSetOut); + checkError(Status, "amd_comgr_destroy_data_set"); + + // AMD_COMGR_ACTION_LINK_BC_TO_BC + + Status = amd_comgr_create_data_set(&DataSetOut); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetOut); + checkLogs("LINK_BC_TO_BC", DataSetOut, "error: expected top-level entity"); + + Status = + amd_comgr_action_data_count(DataSetOut, AMD_COMGR_DATA_KIND_LOG, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu LOG objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_destroy_data_set(DataSetOut); + checkError(Status, "amd_comgr_destroy_data_set"); + + // AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE + + Status = amd_comgr_create_data_set(&DataSetOut); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE, + DataAction, DataSetAsm, DataSetOut); + checkLogs("ASSEMBLE_SOURCE_TO_RELOCATABLE", DataSetOut, + "error: invalid instruction"); + + Status = + amd_comgr_action_data_count(DataSetOut, AMD_COMGR_DATA_KIND_LOG, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu LOG objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_destroy_data_set(DataSetOut); + checkError(Status, "amd_comgr_destroy_data_set"); + + // AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE + + Status = amd_comgr_create_data_set(&DataSetOut); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + DataAction, DataSetBc, DataSetOut); + checkLogs("CODEGEN_BC_TO_RELOCATABLE", DataSetOut, + "error: expected top-level entity"); + checkLogs("CODEGEN_BC_TO_RELOCATABLE", DataSetOut, "1 error generated."); + + Status = + amd_comgr_action_data_count(DataSetOut, AMD_COMGR_DATA_KIND_LOG, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu LOG objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_destroy_data_set(DataSetOut); + checkError(Status, "amd_comgr_destroy_data_set"); + + // AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE + + Status = amd_comgr_create_data_set(&DataSetOut); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetOut); + checkLogs("LINK_RELOCATABLE_TO_EXECUTABLE", DataSetOut, "unknown directive"); + + Status = + amd_comgr_action_data_count(DataSetOut, AMD_COMGR_DATA_KIND_LOG, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu LOG objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_destroy_data_set(DataSetOut); + checkError(Status, "amd_comgr_destroy_data_set"); + + Status = amd_comgr_release_data(DataCl); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataAsm); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataBc); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataReloc); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetCl); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetAsm); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); +} diff --git a/amd/comgr/test/compile_minimal_test.c b/amd/comgr/test/compile_minimal_test.c new file mode 100644 index 0000000000000..ea6eaf2bae7ef --- /dev/null +++ b/amd/comgr/test/compile_minimal_test.c @@ -0,0 +1,173 @@ +//===- compile_minimal_test.c ---------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource1, *BufSource2, *BufInclude; + size_t SizeSource1, SizeSource2, SizeInclude; + amd_comgr_data_t DataSource1, DataSource2, DataInclude; + amd_comgr_data_set_t DataSetIn, DataSetBc, DataSetLinked, DataSetReloc, + DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + size_t Count; + const char *CodeGenOptions[] = {"-mllvm", "--color"}; + size_t CodeGenOptionsCount = + sizeof(CodeGenOptions) / sizeof(CodeGenOptions[0]); + + SizeSource1 = setBuf(TEST_OBJ_DIR "/source1.cl", &BufSource1); + SizeSource2 = setBuf(TEST_OBJ_DIR "/source2.cl", &BufSource2); + SizeInclude = setBuf(TEST_OBJ_DIR "/include-macro.h", &BufInclude); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource1, SizeSource1, BufSource1); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource1, "source1.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource1); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource2); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource2, SizeSource2, BufSource2); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource2, "source2.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource2); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_INCLUDE, &DataInclude); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataInclude, SizeInclude, BufInclude); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataInclude, "include-macro.h"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataInclude); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + Status = amd_comgr_action_info_set_option_list(DataAction, CodeGenOptions, + CodeGenOptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, + DataAction, DataSetIn, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + Status = + amd_comgr_action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 2) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu BC objects (expected 2)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_device_lib_linking(DataAction, true); + checkError(Status, "amd_comgr_action_info_set_device_lib_linking"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + DataAction, DataSetLinked, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu source objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_release_data(DataSource1); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataSource2); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataInclude); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource1); + free(BufSource2); + free(BufInclude); +} diff --git a/amd/comgr/test/compile_source_to_executable.c b/amd/comgr/test/compile_source_to_executable.c new file mode 100644 index 0000000000000..5b465aa2ccc71 --- /dev/null +++ b/amd/comgr/test/compile_source_to_executable.c @@ -0,0 +1,224 @@ +//===- compile_source_to_executable.c -------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + + // OpenCL + { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource; + amd_comgr_data_set_t DataSetIn, DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + + // Create OpenCL source data set + SizeSource = setBuf(TEST_OBJ_DIR "/source1.cl", &BufSource); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource, "source1.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource); + checkError(Status, "amd_comgr_data_set_add"); + + // Set up ActionInfo + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + + // Compile source to executable + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE, + DataAction, DataSetIn, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + size_t Count; + Status = amd_comgr_action_data_count( + DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE Failed: " + "produced %zu executable objects from source (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_release_data(DataSource); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource); + } + + // Re-enable post https://github.com/llvm/llvm-project/pull/85672 +#if 0 + // HIP + { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource; + amd_comgr_data_set_t DataSetIn, DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + + // Create HIP source data set + SizeSource = setBuf(TEST_OBJ_DIR "/source1.hip", &BufSource); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource, "source1.hip"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource); + checkError(Status, "amd_comgr_data_set_add"); + + // Set up ActionInfo + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_HIP); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + + // Compile source to executable + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE, + DataAction, DataSetIn, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + size_t Count; + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE Failed: " + "produced %zu executable objects from source (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_release_data(DataSource); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource); + } +#endif + + // Bitcode + { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource; + amd_comgr_data_set_t DataSetIn, DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + + // Create Bitcode source data set + SizeSource = setBuf(TEST_OBJ_DIR "/source1.bc", &BufSource); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_BC, &DataSource); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource, "source1.bc"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource); + checkError(Status, "amd_comgr_data_set_add"); + + // Set up ActionInfo + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_LLVM_IR); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + + // Compile source to executable + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE, + DataAction, DataSetIn, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + size_t Count; + Status = amd_comgr_action_data_count( + DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE Failed: " + "produced %zu executable objects from bitcode (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_release_data(DataSource); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource); + } // end Bitcode +} diff --git a/amd/comgr/test/compile_source_with_device_libs_to_bc_test.c b/amd/comgr/test/compile_source_with_device_libs_to_bc_test.c new file mode 100644 index 0000000000000..802d726cb95b3 --- /dev/null +++ b/amd/comgr/test/compile_source_with_device_libs_to_bc_test.c @@ -0,0 +1,147 @@ +//===- compile_source_with_device_libs_to_bc_test.c -----------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource; + amd_comgr_data_set_t DataSetIn, DataSetBc, DataSetLinked, DataSetReloc, + DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + const char *CodeGenOptions[] = {"-mcode-object-version=5", "-mllvm", + "-amdgpu-prelink"}; + size_t CodeGenOptionsCount = + sizeof(CodeGenOptions) / sizeof(CodeGenOptions[0]); + + SizeSource = setBuf(TEST_OBJ_DIR "/device_libs.cl", &BufSource); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource, "device_libs.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, CodeGenOptions, + CodeGenOptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action( + AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, DataAction, + DataSetIn, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + size_t Count; + Status = + amd_comgr_action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + DataAction, DataSetLinked, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu relocatable objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_release_data(DataSource); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource); +} diff --git a/amd/comgr/test/compile_source_with_device_libs_to_bc_with_vfs_test.c b/amd/comgr/test/compile_source_with_device_libs_to_bc_with_vfs_test.c new file mode 100644 index 0000000000000..1c98243f63050 --- /dev/null +++ b/amd/comgr/test/compile_source_with_device_libs_to_bc_with_vfs_test.c @@ -0,0 +1,150 @@ +//===- compile_source_with_device_libs_to_bc_with_vfs_test.c --------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource; + amd_comgr_data_set_t DataSetIn, DataSetBc, DataSetLinked, DataSetReloc, + DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + const char *CodeGenOptions[] = {"-mcode-object-version=5", "-mllvm", + "-amdgpu-prelink"}; + size_t CodeGenOptionsCount = + sizeof(CodeGenOptions) / sizeof(CodeGenOptions[0]); + + SizeSource = setBuf(TEST_OBJ_DIR "/device_libs.cl", &BufSource); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource, "device_libs.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + // Set VFS knob to true + Status = amd_comgr_action_info_set_vfs(DataAction, true); + checkError(Status, "amd_comgr_action_info_set_vfs"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, CodeGenOptions, + CodeGenOptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action( + AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, DataAction, + DataSetIn, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + size_t Count; + Status = + amd_comgr_action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + DataAction, DataSetLinked, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu relocatable objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_release_data(DataSource); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource); +} diff --git a/amd/comgr/test/compile_test.c b/amd/comgr/test/compile_test.c new file mode 100644 index 0000000000000..c6175ed288652 --- /dev/null +++ b/amd/comgr/test/compile_test.c @@ -0,0 +1,210 @@ +//===- compile_test.c -----------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource1, *BufSource2, *BufInclude; + size_t SizeSource1, SizeSource2, SizeInclude; + amd_comgr_data_t DataSource1, DataSource2, DataInclude; + amd_comgr_data_set_t DataSetIn, DataSetPreproc, DataSetBc, DataSetLinked, + DataSetAsm, DataSetReloc, DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + size_t Count; + const char *CodeGenOptions[] = {"-mllvm", "--color"}; + size_t CodeGenOptionsCount = + sizeof(CodeGenOptions) / sizeof(CodeGenOptions[0]); + + SizeSource1 = setBuf(TEST_OBJ_DIR "/source1.cl", &BufSource1); + SizeSource2 = setBuf(TEST_OBJ_DIR "/source2.cl", &BufSource2); + SizeInclude = setBuf(TEST_OBJ_DIR "/include-macro.h", &BufInclude); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource1, SizeSource1, BufSource1); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource1, "source1.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource1); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource2); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource2, SizeSource2, BufSource2); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource2, "source2.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource2); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_INCLUDE, &DataInclude); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataInclude, SizeInclude, BufInclude); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataInclude, "include-macro.h"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataInclude); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + Status = amd_comgr_action_info_set_option_list(DataAction, CodeGenOptions, + CodeGenOptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_create_data_set(&DataSetPreproc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR, + DataAction, DataSetIn, DataSetPreproc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetPreproc, + AMD_COMGR_DATA_KIND_SOURCE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 2) { + printf("AMD_COMGR_ACTION_PREPROCESS_SOURCE_TO_SOURCE Failed: " + "produced %zu source objects (expected 2)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, + DataAction, DataSetPreproc, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + Status = + amd_comgr_action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 2) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu BC objects (expected 2)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetAsm); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY, + DataAction, DataSetLinked, DataSetAsm); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetAsm, AMD_COMGR_DATA_KIND_SOURCE, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY Failed: " + "produced %zu source objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE, + DataAction, DataSetAsm, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE Failed: " + "produced %zu relocatable objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_release_data(DataSource1); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataSource2); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataInclude); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetPreproc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetAsm); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource1); + free(BufSource2); + free(BufInclude); +} diff --git a/amd/comgr/test/data_test.c b/amd/comgr/test/data_test.c new file mode 100644 index 0000000000000..31e5dff075cf2 --- /dev/null +++ b/amd/comgr/test/data_test.c @@ -0,0 +1,182 @@ +//===- data_test.c --------------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + long Size1; + char *Buf; + amd_comgr_data_t DataObject, DataObject2, DataObject3; + amd_comgr_data_set_t DataSet; + amd_comgr_status_t Status; + size_t Count; + + // Read input file + Size1 = setBuf(TEST_OBJ_DIR "/shared.so", &Buf); + + // Create data object + { + printf("Test 1 ...\n"); + + Status = + amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &DataObject); + checkError(Status, "amd_comgr_create_data"); + + Status = amd_comgr_set_data(DataObject, Size1, Buf); + checkError(Status, "amd_comgr_set_data"); + } + + { + printf("Test 2 ...\n"); + Status = amd_comgr_set_data_name(DataObject, "DO1"); + checkError(Status, "amd_comgr_set_data_name"); + + size_t Size; + char Name[10]; + Status = amd_comgr_get_data_name(DataObject, &Size, NULL); + checkError(Status, "amd_comgr_get_data_name"); + if (Size != strlen("DO1") + 1) { + printf("FAILED_2a:\n"); + printf(" amd_comgr_get_data_name size = %zd\n", Size); + printf(" expected size = %zd\n", strlen("DO1")); + } + Status = amd_comgr_get_data_name(DataObject, &Size, &Name[0]); + checkError(Status, "amd_comgr_get_data_name"); + if (strcmp(Name, "DO1")) { + printf("FAILED_2b:\n"); + printf(" amd_comgr_get_data_name name = %s\n", &Name[0]); + printf(" expected name = DO1\n"); + } + } + + { + printf("Test 3 ...\n"); + + // Add data object 1 + Status = amd_comgr_create_data_set(&DataSet); + checkError(Status, "amd_cogmr_create_data_set"); + + // Add data object + Status = amd_comgr_data_set_add(DataSet, DataObject); + checkError(Status, "amd_cogmr_data_set_add"); + + // Add data object 2 + Status = + amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &DataObject2); + checkError(Status, "amd_comgr_create_data_2"); + Status = amd_comgr_set_data(DataObject2, Size1, Buf); // Use the same data + checkError(Status, "amd_comgr_set_data_2"); + Status = amd_comgr_set_data_name(DataObject2, "DO2"); + checkError(Status, "amd_comgr_set_data_name_2"); + Status = amd_comgr_data_set_add(DataSet, DataObject2); + checkError(Status, "amd_cogmr_data_set_add_2"); + + // Add data object 3 + Status = + amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &DataObject3); + checkError(Status, "amd_comgr_create_data_3"); + Status = amd_comgr_set_data(DataObject3, Size1, Buf); // Use the same data + checkError(Status, "amd_comgr_set_data_3"); + Status = amd_comgr_set_data_name(DataObject3, "DO3"); + checkError(Status, "amd_comgr_set_data_name_3"); + Status = amd_comgr_data_set_add(DataSet, DataObject3); + checkError(Status, "amd_cogmr_data_set_add_3"); + + Status = amd_comgr_action_data_count( + DataSet, AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + if (Count != 3) { + printf("FAILED_3a:\n"); + printf(" amd_comgr_action_data_count = %zd\n", Count); + printf(" expected count = 3\n"); + } + + amd_comgr_data_t Data2; + Status = amd_comgr_action_data_get_data( + DataSet, AMD_COMGR_DATA_KIND_RELOCATABLE, 2, &Data2); + checkError(Status, "amd_comgr_action_data_get_data"); + size_t Size2; + char Name2[10]; + Status = amd_comgr_get_data_name(Data2, &Size2, NULL); + checkError(Status, "amd_comgr_get_data_name"); + Status = amd_comgr_get_data_name(Data2, &Size2, &Name2[0]); + if (strcmp(Name2, "DO3")) { + printf("FAILED_3b:\n"); + printf(" amd_comgr_get_data_name name_2 = %s\n", &Name2[0]); + printf(" expected name = DO2\n"); + } + + // dataObject1, dataObject2 has refcount = 2, dataObject3 has refcount = 3. + amd_comgr_release_data(Data2); + // dataObject1, dataObject2 has refcount = 2, dataObject3 has refcount = 2. + } + + { + printf("Test 4 ...\n"); + + // Remove data object. + Status = amd_comgr_data_set_remove(DataSet, AMD_COMGR_DATA_KIND_EXECUTABLE); + checkError(Status, "amd_cogmr_data_set_remove"); // nothing to remove + Status = amd_comgr_action_data_count( + DataSet, AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + if (Count != 3) { + printf("FAILED_4a:\n"); + printf(" amd_comgr_action_data_count = %zd\n", Count); + printf(" expected count = 3\n"); + } + + Status = + amd_comgr_data_set_remove(DataSet, AMD_COMGR_DATA_KIND_RELOCATABLE); + checkError(Status, "amd_cogmr_data_set_remove_2"); + Status = amd_comgr_action_data_count( + DataSet, AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + if (Count != 0) { + printf("FAILED_4b:\n"); + printf(" amd_comgr_action_data_count = %zd\n", Count); + printf(" expected count = 1\n"); + } + + // dataObject1, dataObject2 has refcount = 1, dataObject3 has refcount = 1. + + amd_comgr_data_kind_t Kind2; + Status = amd_comgr_get_data_kind(DataObject, &Kind2); + checkError(Status, "amd_cogmr_get_data_kind"); + if (Kind2 != AMD_COMGR_DATA_KIND_RELOCATABLE) { + printf("FAILED_4c:\n"); + printf(" amd_comgr_get_data_kind kind = %d\n", Kind2); + } + + // insert 3 items back into set + Status = amd_comgr_data_set_add(DataSet, DataObject); + Status = amd_comgr_data_set_add(DataSet, DataObject2); + Status = amd_comgr_data_set_add(DataSet, DataObject3); + + // Destroy data set, amd_comgr_release_data to be called also + Status = amd_comgr_destroy_data_set(DataSet); + checkError(Status, "amd_comgr_destroy_data_set"); + } + + { + printf("Cleanup ...\n"); + Status = amd_comgr_release_data(DataObject); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataObject2); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataObject3); + checkError(Status, "amd_comgr_release_data"); + free(Buf); + } + + return 0; +} diff --git a/amd/comgr/test/demangle_test.c b/amd/comgr/test/demangle_test.c new file mode 100644 index 0000000000000..5dd2f0d5547e6 --- /dev/null +++ b/amd/comgr/test/demangle_test.c @@ -0,0 +1,116 @@ +//===- demangle_test.c ----------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" + +int test(const char *MangledName, const char *ExpectedString) { + amd_comgr_data_t MangledData; + amd_comgr_data_t DemangledData; + amd_comgr_status_t Status; + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_BYTES, &MangledData); + checkError(Status, "amd_comgr_create_data"); + + size_t Size = strlen(MangledName); + Status = amd_comgr_set_data(MangledData, Size, MangledName); + checkError(Status, "amd_comgr_set_data"); + + Status = amd_comgr_demangle_symbol_name(MangledData, &DemangledData); + checkError(Status, "amd_comgr_demangle_symbol_name"); + + size_t DemangledSize = 0; + Status = amd_comgr_get_data(DemangledData, &DemangledSize, NULL); + checkError(Status, "amd_comgr_get_data"); + + if (DemangledSize != strlen(ExpectedString)) { + fail("DemangledSize (%zu) does not match ExpectedString size(%zu)\n", + DemangledSize, ExpectedString); + } + + char *DemangledName = (char *)calloc(DemangledSize, sizeof(char)); + if (DemangledName == NULL) { + fail("calloc failed\n"); + } + + Status = amd_comgr_get_data(DemangledData, &DemangledSize, DemangledName); + checkError(Status, "amd_comgr_get_data"); + + if (strncmp(DemangledName, ExpectedString, DemangledSize) != 0) { + fail(">> expected %s \n >> got %s\n", ExpectedString, DemangledName); + } + + free(DemangledName); + + Status = amd_comgr_release_data(MangledData); + checkError(Status, "amd_comgr_release_data"); + + Status = amd_comgr_release_data(DemangledData); + checkError(Status, "amd_comgr_release_data"); + + return 0; +} + +int main(int argc, char *argv[]) { + // Tests from llvm/unittests/Demangle/DemangleTest.cpp + test("_", "_"); + test("_Z3fooi", "foo(int)"); + test("__Z3fooi", "foo(int)"); + test("___Z3fooi_block_invoke", "invocation function for block in foo(int)"); + test("____Z3fooi_block_invoke", "invocation function for block in foo(int)"); + test("?foo@@YAXH@Z", "void __cdecl foo(int)"); + test("foo", "foo"); + test("_RNvC3foo3bar", "foo::bar"); + test("_Z3fooILi79EEbU7_ExtIntIXT_EEi", "bool foo<79>(int _ExtInt<79>)"); + + // Some additional test cases. + test("_Znwm", "operator new(unsigned long)"); + test("_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSERKS4_", + "std::__cxx11::basic_string, " + "std::allocator>::operator=(std::__cxx11::basic_string, std::allocator> const&)"); + test("_ZSt29_Rb_tree_insert_and_rebalancebPSt18_Rb_tree_node_baseS0_RS_", + "std::_Rb_tree_insert_and_rebalance(bool, std::_Rb_tree_node_base*, " + "std::_Rb_tree_node_base*, std::_Rb_tree_node_base&)"); + test("_ZSt17__throw_bad_allocv", "std::__throw_bad_alloc()"); + test("_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev", + "std::__cxx11::basic_string, " + "std::allocator>::~basic_string()"); + test("_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED1Ev", + "std::__cxx11::basic_string, " + "std::allocator>::~basic_string()"); + test("_ZSt18_Rb_tree_incrementPSt18_Rb_tree_node_base", + "std::_Rb_tree_increment(std::_Rb_tree_node_base*)"); + test("_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2Ev", + "std::__cxx11::basic_string, " + "std::allocator>::basic_string()"); + test("_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__" + "cxx1112basic_stringIS4_S5_T1_EE", + "std::basic_ostream>& std::operator<<" + ", std::allocator" + ">(std::basic_ostream>&, " + "std::__cxx11::basic_string, " + "std::allocator> const&)"); + test("_ZdlPv", "operator delete(void*)"); + test("_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc", + "std::basic_ostream>& std::operator<<" + ">(std::basic_ostream>&, char const*)"); + test("_ZdlPvm", "operator delete(void*, unsigned long)"); + test("_ZSt18_Rb_tree_decrementPSt18_Rb_tree_node_base", + "std::_Rb_tree_decrement(std::_Rb_tree_node_base*)"); + test("_ZNSaIcED1Ev", "std::allocator::~allocator()"); + test("_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EPKcRKS3_", + "std::__cxx11::basic_string, " + "std::allocator>::basic_string(char const*, std::allocator " + "const&)"); + test("_ZNSt8ios_base4InitC1Ev", "std::ios_base::Init::Init()"); + test("_ZNSolsEi", "std::ostream::operator<<(int)"); + test("_ZNSaIcEC1Ev", "std::allocator::allocator()"); + return 0; +} diff --git a/amd/comgr/test/disasm_instr_test.c b/amd/comgr/test/disasm_instr_test.c new file mode 100644 index 0000000000000..9613bd8424337 --- /dev/null +++ b/amd/comgr/test/disasm_instr_test.c @@ -0,0 +1,139 @@ +//===- disasm_instr_test.c ------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include +#include +#include + +const int ExpectedUserData; + +void checkUserData(void *UserData) { + if (UserData != (void *)&ExpectedUserData) { + fail("user_data changed"); + } +} + +const char *skipspace(const char *S) { + while (isspace(*S)) { + ++S; + } + return S; +} + +size_t strlenWithoutTrailingWhitespace(const char *S) { + size_t I = strlen(S); + while (I && isspace(S[--I])) { + ; + } + return I + 1; +} + +const char Program[] = { + '\x02', '\x00', '\x06', '\xC0', '\x00', '\x00', '\x00', '\x00', '\x7f', + '\xC0', '\x8c', '\xbf', '\x00', '\x80', '\x12', '\xbf', '\x05', '\x00', + '\x85', '\xbf', '\x00', '\x02', '\x00', '\x7e', '\xc0', '\x02', '\x04', + '\x7e', '\x01', '\x02', '\x02', '\x7e', '\x00', '\x80', '\x70', '\xdc', + '\x00', '\x02', '\x7f', '\x00', '\x00', '\x00', '\x81', '\xbf', +}; + +const char *Instructions[] = { + "s_load_dwordx2 s[0:1], s[4:5], 0x0", + "s_waitcnt lgkmcnt(0)", + "s_cmp_eq_u64 s[0:1], 0", + "s_cbranch_scc1 5", + "v_mov_b32_e32 v0, s0", + "v_mov_b32_e32 v2, 64", + "v_mov_b32_e32 v1, s1", + "global_store_dword v[0:1], v2, off", + "s_endpgm", +}; +const size_t InstructionsLen = sizeof(Instructions) / sizeof(*Instructions); +size_t InstructionsIdx = 0; +const size_t BrInstructionIdx = 3; +const size_t BrInstructionAddr = 40; + +uint64_t readMemoryCallback(uint64_t From, char *To, uint64_t Size, + void *UserData) { + checkUserData(UserData); + if (From >= sizeof(Program)) { + return 0; + } + if (From + Size > sizeof(Program)) { + Size = sizeof(Program) - From; + } + memcpy(To, Program + From, Size); + return Size; +} + +void printInstructionCallback(const char *Instruction, void *UserData) { + checkUserData(UserData); + if (InstructionsIdx == InstructionsLen) { + fail("too many instructions"); + } + const char *Expected = skipspace(Instructions[InstructionsIdx++]); + const char *Actual = skipspace(Instruction); + if (strncmp(Expected, Actual, strlenWithoutTrailingWhitespace(Actual))) { + fail("incorrect instruction: expected '%s', actual '%s'", Expected, Actual); + } +} + +void printAddressCallback(uint64_t Address, void *UserData) { + checkUserData(UserData); + size_t ActualIdx = InstructionsIdx - 1; + if (ActualIdx != BrInstructionIdx) { + fail("absolute address resolved for instruction index %zu, expected index " + "%zu", + InstructionsIdx, BrInstructionIdx); + } + if (Address != BrInstructionAddr) { + fail("incorrect absolute address %llu resolved for instruction index %zu, " + "expected %llu", + Address, ActualIdx, BrInstructionAddr); + } +} + +int main(int argc, char *argv[]) { + amd_comgr_status_t Status; + + amd_comgr_disassembly_info_t DisassemblyInfo; + + Status = amd_comgr_create_disassembly_info( + "amdgcn-amd-amdhsa--gfx900", &readMemoryCallback, + &printInstructionCallback, &printAddressCallback, &DisassemblyInfo); + checkError(Status, "amd_comgr_create_disassembly_info"); + + uint64_t Addr = 0; + uint64_t Size = 0; + while (Status == AMD_COMGR_STATUS_SUCCESS && Addr < sizeof(Program)) { + Status = amd_comgr_disassemble_instruction( + DisassemblyInfo, Addr, (void *)&ExpectedUserData, &Size); + checkError(Status, "amd_comgr_disassemble_instruction"); + Addr += Size; + } + + if (InstructionsIdx != InstructionsLen) { + fail("too few instructions\n"); + } + + Addr = sizeof(Program) - 1; + Size = 0; + Status = amd_comgr_disassemble_instruction(DisassemblyInfo, Addr, + (void *)&ExpectedUserData, &Size); + if (Status != AMD_COMGR_STATUS_ERROR) { + fail("successfully disassembled invalid instruction encoding"); + } + + Status = amd_comgr_destroy_disassembly_info(DisassemblyInfo); + checkError(Status, "amd_comgr_destroy_disassembly_info"); + + return EXIT_SUCCESS; +} diff --git a/amd/comgr/test/fail_to_build_driver.c b/amd/comgr/test/fail_to_build_driver.c new file mode 100644 index 0000000000000..84826fb3ba153 --- /dev/null +++ b/amd/comgr/test/fail_to_build_driver.c @@ -0,0 +1,69 @@ +//===- fail_to_build_driver.c ---------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource1; + size_t SizeSource1; + amd_comgr_data_t DataSource1, DataSource2, DataInclude; + amd_comgr_data_set_t DataSetIn, DataSetBc; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + size_t Count; + const char *CodeGenOptions[] = {"-this-is-a-non-existent-flag"}; + size_t CodeGenOptionsCount = + sizeof(CodeGenOptions) / sizeof(CodeGenOptions[0]); + + SizeSource1 = setBuf(TEST_OBJ_DIR "/source1.cl", &BufSource1); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource1, SizeSource1, BufSource1); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource1, "source1.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource1); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + Status = amd_comgr_action_info_set_option_list(DataAction, CodeGenOptions, + CodeGenOptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, + DataAction, DataSetIn, DataSetBc); + checkStatus(Status, AMD_COMGR_STATUS_ERROR, "amd_comgr_do_action"); + + Status = amd_comgr_release_data(DataSource1); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource1); +} diff --git a/amd/comgr/test/file_map.c b/amd/comgr/test/file_map.c new file mode 100644 index 0000000000000..de3ccf3f25e7f --- /dev/null +++ b/amd/comgr/test/file_map.c @@ -0,0 +1,74 @@ +//===- file_map.c ---------------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" + +int main(int argc, char *argv[]) { + int Ret; + amd_comgr_status_t Status; + + const char *FileName = "comgr_map_test_file.txt"; + + // Remove any stray file that may exist from before. + remove(FileName); + +#if defined(_WIN32) || defined(_WIN64) + int FD = _open(FileName, _O_CREAT | _O_RDWR); +#else + int FD = open(FileName, O_CREAT | O_RDWR, 0755); +#endif + if (FD < 0) { + fail("open failed for %s with errno %d", FileName, errno); + } + + const char *Buffer = "abcdefghi"; + size_t Length = strlen(Buffer); + size_t Bytes = WriteFileCustom(FD, Buffer, Length); + if (Bytes != Length) { + fail("Write failed with ret %zu", Bytes); + } + + amd_comgr_data_t DataObject; + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &DataObject); + checkError(Status, "amd_comgr_create_data"); + + uint64_t Offset = 2; + Status = amd_comgr_set_data_from_file_slice(DataObject, FD, Offset, Length); + checkError(Status, "amd_comgr_get_file_slice"); + + char Slice[10]; + size_t SliceLength = Length - 2; + Status = amd_comgr_get_data(DataObject, &SliceLength, Slice); + checkError(Status, "amd_comgr_get_data"); + + if (SliceLength != Length - Offset) { + fail("File Slice Length incorrect"); + } + + if (!strncmp(Slice, Buffer, Length - Offset)) { + fail("File Slice read failed"); + } + +#if defined(_WIN32) || defined(_WIN64) + _close(FD); +#else + close(FD); +#endif + + if ((Ret = remove(FileName)) != 0) { +#if defined(_WIN32) || defined(_WIN64) + if ((Ret = remove(FileName)) != 0) { + fail("remove failed"); + } +#else + fail("remove failed"); +#endif + } + return 0; +} diff --git a/amd/comgr/test/get_data_isa_name_test.c b/amd/comgr/test/get_data_isa_name_test.c new file mode 100644 index 0000000000000..655e0d5ae8ff5 --- /dev/null +++ b/amd/comgr/test/get_data_isa_name_test.c @@ -0,0 +1,370 @@ +//===- get_data_is_name_test.c --------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +#define MAX_ISA_NAME_SIZE 1024 + +typedef enum { + none, + off, + on, + any +} feature_mode_t; + +typedef struct { + const char *IsaName; + bool SrameccSupported; + bool XnackSupported; + bool NeedsCOV6; +} isa_features_t; + +/* Features supported based on https://llvm.org/docs/AMDGPUUsage.html . */ +static isa_features_t IsaFeatures[] = { + // clang-format off + // ISA Name SRAMECC XNACK NeedsCOV7 + {"amdgcn-amd-amdhsa--gfx600", false, false, false}, + {"amdgcn-amd-amdhsa--gfx601", false, false, false}, + {"amdgcn-amd-amdhsa--gfx602", false, false, false}, + {"amdgcn-amd-amdhsa--gfx700", false, false, false}, + {"amdgcn-amd-amdhsa--gfx701", false, false, false}, + {"amdgcn-amd-amdhsa--gfx702", false, false, false}, + {"amdgcn-amd-amdhsa--gfx703", false, false, false}, + {"amdgcn-amd-amdhsa--gfx704", false, false, false}, + {"amdgcn-amd-amdhsa--gfx705", false, false, false}, + {"amdgcn-amd-amdhsa--gfx801", false, true, false}, + {"amdgcn-amd-amdhsa--gfx802", false, false, false}, + {"amdgcn-amd-amdhsa--gfx803", false, false, false}, + {"amdgcn-amd-amdhsa--gfx805", false, false, false}, + {"amdgcn-amd-amdhsa--gfx810", false, true, false}, + {"amdgcn-amd-amdhsa--gfx900", false, true, false}, + {"amdgcn-amd-amdhsa--gfx902", false, true, false}, + {"amdgcn-amd-amdhsa--gfx904", false, true, false}, + {"amdgcn-amd-amdhsa--gfx906", true, true, false}, + {"amdgcn-amd-amdhsa--gfx908", true, true, false}, + {"amdgcn-amd-amdhsa--gfx909", false, true, false}, + {"amdgcn-amd-amdhsa--gfx90a", true, true, false}, + {"amdgcn-amd-amdhsa--gfx90c", false, true, false}, + {"amdgcn-amd-amdhsa--gfx942", true, true, false}, + {"amdgcn-amd-amdhsa--gfx950", true, true, false}, + {"amdgcn-amd-amdhsa--gfx1010", false, true, false}, + {"amdgcn-amd-amdhsa--gfx1011", false, true, false}, + {"amdgcn-amd-amdhsa--gfx1012", false, true, false}, + {"amdgcn-amd-amdhsa--gfx1013", false, true, false}, + {"amdgcn-amd-amdhsa--gfx1030", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1031", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1032", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1033", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1034", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1035", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1036", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1100", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1101", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1102", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1103", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1150", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1151", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1152", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1153", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1200", false, false, false}, + {"amdgcn-amd-amdhsa--gfx1201", false, false, false}, + + {"amdgcn-amd-amdhsa--gfx9-generic", false, true, true}, + {"amdgcn-amd-amdhsa--gfx9-4-generic", true, true, true}, + {"amdgcn-amd-amdhsa--gfx10-1-generic", false, true, true}, + {"amdgcn-amd-amdhsa--gfx10-3-generic", false, false, true}, + {"amdgcn-amd-amdhsa--gfx11-generic", false, false, true}, + {"amdgcn-amd-amdhsa--gfx12-generic", false, false, true}, + // clang-format on +}; + +static size_t IsaFeaturesSize = sizeof(IsaFeatures) / sizeof(IsaFeatures[0]); + +bool hasSubString(const char *String, const char *Sub) { + return !strncmp(String, Sub, strlen(Sub)); +} + +bool getExpectedIsaName(unsigned CodeObjectVersion, const char *IsaName, + char *ExpectedIsaName, bool *NeedsCoV6) { + char TokenizedIsaName[MAX_ISA_NAME_SIZE]; + + strncpy(TokenizedIsaName, IsaName, MAX_ISA_NAME_SIZE); + + char *Token = strtok(TokenizedIsaName, ":"); + isa_features_t *Isa = NULL; + for (size_t I = 0; I < IsaFeaturesSize; I++) { + if (strncmp(Token, IsaFeatures[I].IsaName, MAX_ISA_NAME_SIZE) == 0) { + Isa = &IsaFeatures[I]; + break; + } + } + if (!Isa) { + printf("The %s target is not supported by the test (update the " + "isa_features table)\n", + Token); + exit(1); + } + + *NeedsCoV6 = Isa->NeedsCOV6; + strncpy(ExpectedIsaName, Isa->IsaName, MAX_ISA_NAME_SIZE); + + feature_mode_t Sramecc = any; + feature_mode_t Xnack = any; + + Token = strtok(NULL, ":"); + while (Token != NULL) { + if (strncmp(Token, "sramecc", strlen("sramecc")) == 0 && + Isa->SrameccSupported) { + switch (Token[strlen("sramecc")]) { + case '-': + Sramecc = off; + break; + case '+': + Sramecc = on; + break; + } + } + + if (strncmp(Token, "xnack", strlen("xnack")) == 0 && Isa->XnackSupported) { + switch (Token[strlen("xnack")]) { + case '-': + Xnack = off; + break; + case '+': + Xnack = on; + break; + } + } + + Token = strtok(NULL, ":"); + } + + switch (CodeObjectVersion) { + case 4: + case 5: + case 6: + // All ISA strings are valid. + return true; + + default: + printf("Code object V%u is not supported by the test (update the " + "get_expected_isa_name)\n", + CodeObjectVersion); + exit(1); + } + + strncpy(ExpectedIsaName, Isa->IsaName, MAX_ISA_NAME_SIZE); + + if (Isa->SrameccSupported && Sramecc != any) { + strncat(ExpectedIsaName, Sramecc == on ? ":sramecc+" : ":sramecc-", + MAX_ISA_NAME_SIZE - strlen(ExpectedIsaName)); + } + + if (Isa->XnackSupported && Xnack != any) { + strncat(ExpectedIsaName, Xnack == on ? ":xnack+" : ":xnack-", + MAX_ISA_NAME_SIZE - strlen(ExpectedIsaName)); + } + + return true; +} + +void checkIsaName(amd_comgr_data_t Data, const char *InputIsaName, + const char *ExpectedIsaName) { + size_t Size; + char *IsaName = NULL; + amd_comgr_status_t Status; + + Status = amd_comgr_get_data_isa_name(Data, &Size, IsaName); + checkError(Status, "amd_comgr_get_data_isa_name"); + + IsaName = malloc(Size); + if (!IsaName) { + printf("cannot allocate %zu bytes for isa_name\n", Size); + exit(1); + } + + Status = amd_comgr_get_data_isa_name(Data, &Size, IsaName); + checkError(Status, "amd_comgr_get_data_isa_name"); + + if (strcmp(IsaName, ExpectedIsaName)) { + printf( + "ISA name match failed: input '%s', expected '%s' but produced '%s'\n", + InputIsaName, ExpectedIsaName, IsaName); + exit(1); + } + + free(IsaName); +} + +void compileAndTestIsaName(const char *IsaName, const char *ExpectedIsaName, + const char *Options[], size_t OptionsCount) { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource, DataReloc, DataExec; + amd_comgr_status_t Status; + amd_comgr_data_set_t DataSetIn, DataSetBc, DataSetLinked, DataSetReloc, + DataSetExec; + amd_comgr_action_info_t DataAction; + + SizeSource = setBuf(TEST_OBJ_DIR "/shared.cl", &BufSource); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource, "shared.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, IsaName); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + Status = + amd_comgr_action_info_set_option_list(DataAction, Options, OptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, + DataAction, DataSetIn, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + DataAction, DataSetLinked, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_get_data( + DataSetReloc, AMD_COMGR_DATA_KIND_RELOCATABLE, 0, &DataReloc); + checkError(Status, "amd_comgr_action_data_get_data"); + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_get_data( + DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, 0, &DataExec); + checkError(Status, "amd_comgr_action_data_get_data"); + + checkIsaName(DataReloc, IsaName, ExpectedIsaName); + checkIsaName(DataExec, IsaName, ExpectedIsaName); + printf("ISA name matched %s -> %s\n", IsaName, ExpectedIsaName); + + Status = amd_comgr_release_data(DataSource); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataReloc); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataExec); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource); +} + +void testIsaName(char *Name, const char *Features) { + char IsaName[MAX_ISA_NAME_SIZE]; + char ExpectedIsaName[MAX_ISA_NAME_SIZE]; + + strncpy(IsaName, Name, MAX_ISA_NAME_SIZE); + strncat(IsaName, Features, MAX_ISA_NAME_SIZE - 1); + + const char *V4Options[] = {"-mcode-object-version=4"}; + size_t V4OptionsCount = sizeof(V4Options) / sizeof(V4Options[0]); + + const char *V6Options[] = {"-mcode-object-version=6"}; + size_t V6OptionsCount = sizeof(V6Options) / sizeof(V6Options[0]); + + // Test object code v6 so generic targets are available. + bool NeedsCOV6; + if (getExpectedIsaName(6, IsaName, ExpectedIsaName, &NeedsCOV6)) { + if (NeedsCOV6) { + printf("V6 : "); + compileAndTestIsaName(IsaName, IsaName, V6Options, V6OptionsCount); + } else { + printf("V4 : "); + compileAndTestIsaName(IsaName, IsaName, V4Options, V4OptionsCount); + } + } +} + +int main(int argc, char *argv[]) { + size_t IsaCount; + amd_comgr_status_t Status; + + Status = amd_comgr_get_isa_count(&IsaCount); + checkError(Status, "amd_comgr_get_isa_count"); + + for (size_t I = 0; I < IsaCount; I++) { + const char *Name; + char IsaName[MAX_ISA_NAME_SIZE]; + + Status = amd_comgr_get_isa_name(I, &Name); + checkError(Status, "amd_comgr_get_isa_name"); + + strncpy(IsaName, Name, MAX_ISA_NAME_SIZE); + + testIsaName(IsaName, ""); + + for (size_t I = 0; I < IsaFeaturesSize; I++) { + if (strncmp(IsaName, IsaFeatures[I].IsaName, MAX_ISA_NAME_SIZE) == 0) { + + if (IsaFeatures[I].SrameccSupported) { + testIsaName(IsaName, ":sramecc+"); + testIsaName(IsaName, ":sramecc-"); + } + + if (IsaFeatures[I].XnackSupported) { + testIsaName(IsaName, ":xnack+"); + testIsaName(IsaName, ":xnack-"); + } + + if (IsaFeatures[I].SrameccSupported && IsaFeatures[I].XnackSupported) { + testIsaName(IsaName, ":sramecc+:xnack+"); + testIsaName(IsaName, ":sramecc+:xnack-"); + testIsaName(IsaName, ":sramecc-:xnack+"); + testIsaName(IsaName, ":sramecc-:xnack-"); + } + + break; + } + } + } + + return 0; +} diff --git a/amd/comgr/test/include_subdirectory_test.c b/amd/comgr/test/include_subdirectory_test.c new file mode 100644 index 0000000000000..411d6b0c0dc20 --- /dev/null +++ b/amd/comgr/test/include_subdirectory_test.c @@ -0,0 +1,101 @@ +//===- include_subdirectory_test.c ----------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + const char *BufInclude1 = "int x = 1;"; + size_t SizeInclude1 = strlen(BufInclude1); + const char *BufInclude2 = "int y = 1;"; + size_t SizeInclude2 = strlen(BufInclude2); + const char *BufInclude3 = "int z = 1;"; + size_t SizeInclude3 = strlen(BufInclude3); + const char *BufSource = + "#include \"subdir/header1.h\"\n#include \"sub/dir/header2.h\"\n#include " + "\"sub/dir/header3.h\""; + size_t SizeSource = strlen(BufSource); + + amd_comgr_data_t DataSource, DataInclude1, DataInclude2, DataInclude3; + amd_comgr_data_set_t DataSetIn, DataSetPreproc; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource, "source.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_INCLUDE, &DataInclude1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataInclude1, SizeInclude1, BufInclude1); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataInclude1, "subdir/header1.h"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataInclude1); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_INCLUDE, &DataInclude2); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataInclude2, SizeInclude2, BufInclude2); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataInclude2, "sub/dir/header2.h"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataInclude2); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_INCLUDE, &DataInclude3); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataInclude3, SizeInclude3, BufInclude3); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataInclude3, "sub/dir/header3.h"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataInclude3); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + + Status = amd_comgr_create_data_set(&DataSetPreproc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR, + DataAction, DataSetIn, DataSetPreproc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_destroy_data_set(DataSetPreproc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + Status = amd_comgr_release_data(DataInclude3); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataInclude2); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataInclude1); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataSource); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); +} diff --git a/amd/comgr/test/isa_name_parsing_test.c b/amd/comgr/test/isa_name_parsing_test.c new file mode 100644 index 0000000000000..b0de72b6a9b84 --- /dev/null +++ b/amd/comgr/test/isa_name_parsing_test.c @@ -0,0 +1,69 @@ +//===- isa_name_parsing_test.c --------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +void parseIsaName(amd_comgr_action_info_t DataAction, const char *IsaName, + amd_comgr_status_t ExpectedStatus) { + amd_comgr_status_t TrueStatus = + amd_comgr_action_info_set_isa_name(DataAction, IsaName); + if (TrueStatus != ExpectedStatus) { + amd_comgr_status_t Status; + const char *TrueStatusString, *ExpectedStatusString; + Status = amd_comgr_status_string(TrueStatus, &TrueStatusString); + checkError(Status, "amd_comgr_status_string"); + Status = amd_comgr_status_string(ExpectedStatus, &ExpectedStatusString); + checkError(Status, "amd_comgr_status_string"); + printf("Parsing \"%s\" resulted in \"%s\"; expected \"%s\"\n", IsaName, + TrueStatusString, ExpectedStatusString); + exit(1); + } +} + +int main(int argc, char *argv[]) { + amd_comgr_status_t Status; + amd_comgr_action_info_t dataAction; + + Status = amd_comgr_create_action_info(&dataAction); + checkError(Status, "amd_comgr_create_action_info"); + +#define PARSE_VALID_ISA_NAME(name) \ + parseIsaName(dataAction, name, AMD_COMGR_STATUS_SUCCESS) +#define PARSE_INVALID_ISA_NAME(name) \ + parseIsaName(dataAction, name, AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT) + + PARSE_VALID_ISA_NAME("amdgcn-amd-amdhsa--gfx803"); + PARSE_VALID_ISA_NAME("amdgcn-amd-amdhsa--gfx801:xnack+"); + PARSE_VALID_ISA_NAME("amdgcn-amd-amdhsa--gfx801:xnack-"); + PARSE_VALID_ISA_NAME("amdgcn-amd-amdhsa--gfx908:sramecc+"); + PARSE_VALID_ISA_NAME("amdgcn-amd-amdhsa--gfx908:sramecc-"); + PARSE_VALID_ISA_NAME("amdgcn-amd-amdhsa--gfx908:xnack+:sramecc+"); + PARSE_VALID_ISA_NAME("amdgcn-amd-amdhsa--gfx908:xnack-:sramecc+"); + PARSE_VALID_ISA_NAME("amdgcn-amd-amdhsa--gfx908:xnack-:sramecc-"); + + PARSE_VALID_ISA_NAME("amdgcn-amd-amdhsa--gfx1010:xnack+"); + PARSE_VALID_ISA_NAME(""); + PARSE_VALID_ISA_NAME(NULL); + + PARSE_INVALID_ISA_NAME("amdgcn-amd-amdhsa--gfx801:xnack+:sramecc+"); + PARSE_INVALID_ISA_NAME("amdgcn-amd-amdhsa--gfx803:::"); + PARSE_INVALID_ISA_NAME("amdgcn-amd-amdhsa-opencl-gfx803"); + PARSE_INVALID_ISA_NAME("amdgcn-amd-amdhsa-gfx803"); + PARSE_INVALID_ISA_NAME("gfx803"); + PARSE_INVALID_ISA_NAME(" amdgcn-amd-amdhsa--gfx803"); + PARSE_INVALID_ISA_NAME(" amdgcn-amd-amdhsa--gfx803 "); + PARSE_INVALID_ISA_NAME("amdgcn-amd-amdhsa--gfx803 "); + PARSE_INVALID_ISA_NAME(" amdgcn-amd-amdhsa--gfx803 "); + + Status = amd_comgr_destroy_action_info(dataAction); + checkError(Status, "amd_comgr_destroy_action_info"); +} diff --git a/amd/comgr/test/link_test.c b/amd/comgr/test/link_test.c new file mode 100644 index 0000000000000..06a18dc7d3c8d --- /dev/null +++ b/amd/comgr/test/link_test.c @@ -0,0 +1,103 @@ +//===- link_test.c --------------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + size_t Size1, Size2; + char *Buf1, *Buf2; + size_t Count; + amd_comgr_data_t DataIn1, DataIn2; + amd_comgr_data_set_t DataSetIn, DataSetOutReloc, DataSetOutExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + + // Read input file + Size1 = setBuf(TEST_OBJ_DIR "/reloc1.o", &Buf1); + Size2 = setBuf(TEST_OBJ_DIR "/reloc2.o", &Buf2); + + // Create data object + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_cogmr_create_data_set"); + + // File 1 + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &DataIn1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataIn1, Size1, Buf1); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataIn1, "DO_IN1"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataIn1); + checkError(Status, "amd_cogmr_data_set_add"); + + // File 2 + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &DataIn2); + checkError(Status, "amd_comgr_create_data_2"); + Status = amd_comgr_set_data(DataIn2, Size2, Buf2); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataIn2, "DO_IN2"); + checkError(Status, "amd_comgr_set_data_name_2"); + Status = amd_comgr_data_set_add(DataSetIn, DataIn2); + checkError(Status, "amd_cogmr_data_set_add_2"); + + Status = amd_comgr_create_data_set(&DataSetOutReloc); + checkError(Status, "amd_cogmr_create_data_set"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + amd_comgr_action_info_set_isa_name(DataAction, "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_language"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE, + DataAction, DataSetIn, DataSetOutReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetOutReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + if (Count != 1) { + printf("Failed, output %zd relocatable objects (should output 1)\n", Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetOutExec); + checkError(Status, "amd_cogmr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetIn, DataSetOutExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetOutExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + if (Count != 1) { + printf("Failed, output %zd executable objects (should output 1)\n", Count); + exit(1); + } + + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetOutReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetOutExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + Status = amd_comgr_release_data(DataIn1); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataIn2); + checkError(Status, "amd_comgr_release_data"); + free(Buf1); + free(Buf2); + + return 0; +} diff --git a/amd/comgr/test/mangled_names_hip_test.c b/amd/comgr/test/mangled_names_hip_test.c new file mode 100644 index 0000000000000..d98ac14b6ec69 --- /dev/null +++ b/amd/comgr/test/mangled_names_hip_test.c @@ -0,0 +1,239 @@ +//===- mangled_names_hip_test.c -------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource; + amd_comgr_data_set_t DataSetIn, DataSetBc, DataSetLinked, DataSetReloc, + DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + size_t Count; + const char *CompileOptions[] = {"-nogpulib", "-nogpuinc"}; + size_t CompileOptionsCount = + sizeof(CompileOptions) / sizeof(CompileOptions[0]); + + SizeSource = setBuf(TEST_OBJ_DIR "/source1.hip", &BufSource); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource, "source1.hip"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = + amd_comgr_action_info_set_language(DataAction, AMD_COMGR_LANGUAGE_HIP); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + Status = amd_comgr_action_info_set_option_list(DataAction, CompileOptions, + CompileOptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action( + AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, DataAction, + DataSetIn, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + Status = + amd_comgr_action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + // Get bitcode mangled names + amd_comgr_data_t DataBc; + + Status = amd_comgr_action_data_get_data(DataSetBc, AMD_COMGR_DATA_KIND_BC, 0, + &DataBc); + checkError(Status, "amd_comgr_action_data_get_data"); + +#if 1 + // write bitcode + { + size_t BytesSize = 0; + char *Bytes = NULL; + + Status = amd_comgr_get_data(DataBc, &BytesSize, Bytes); + checkError(Status, "amd_comgr_get_data"); + + Bytes = (char *)malloc(BytesSize); + + Status = amd_comgr_get_data(DataBc, &BytesSize, Bytes); + checkError(Status, "amd_comgr_get_data"); + + const char *BitcodeFile = "comgr_mangled.bc"; + FILE *File = fopen(BitcodeFile, "wb"); + + if (File) + fwrite(Bytes, BytesSize, 1, File); + else + return AMD_COMGR_STATUS_ERROR; + + fclose(File); + free(Bytes); + } +#endif + + size_t NumNames; + Status = amd_comgr_populate_mangled_names(DataBc, &NumNames); + checkError(Status, "amd_comgr_populate_mangled_names"); + + char *MangledSubstr = "__hip_cuid_"; + bool BcFound = false; + + for (size_t I = 0; I < NumNames; ++I) { + size_t Size; + Status = amd_comgr_get_mangled_name(DataBc, I, &Size, NULL); + checkError(Status, "amd_comgr_get_mangled_name"); + + char *MName = calloc(Size, sizeof(char)); + Status = amd_comgr_get_mangled_name(DataBc, I, &Size, MName); + checkError(Status, "amd_comgr_get_mangled_name"); + + if (strstr(MName, MangledSubstr)) { + BcFound = true; + } + + free(MName); + } + + if (!BcFound) { + printf("amd_get_mangled_name from bc Failed: " + "(expected '%s*')\n", + MangledSubstr); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + DataAction, DataSetLinked, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu source objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + // Get Mangled Names + amd_comgr_data_t DataExec; + + Status = amd_comgr_action_data_get_data( + DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, 0, &DataExec); + + Status = amd_comgr_populate_mangled_names(DataExec, &NumNames); + + bool ExecFound = false; + + for (size_t I = 0; I < NumNames; ++I) { + size_t Size; + Status = amd_comgr_get_mangled_name(DataExec, I, &Size, NULL); + checkError(Status, "amd_comgr_get_mangled_name"); + + char *MName = calloc(Size, sizeof(char)); + Status = amd_comgr_get_mangled_name(DataExec, I, &Size, MName); + checkError(Status, "amd_comgr_get_mangled_name"); + + if (strstr(MName, MangledSubstr)) { + ExecFound = true; + } + + free(MName); + } + + if (!ExecFound) { + printf("amd_get_mangled_name from exec Failed: " + "(expected '%s*')\n", + MangledSubstr); + exit(1); + } + + Status = amd_comgr_release_data(DataSource); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataBc); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataExec); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource); +} diff --git a/amd/comgr/test/mangled_names_test.c b/amd/comgr/test/mangled_names_test.c new file mode 100644 index 0000000000000..45ac29a972736 --- /dev/null +++ b/amd/comgr/test/mangled_names_test.c @@ -0,0 +1,282 @@ +//===- mangled_names_test.c -----------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource1, *BufSource2, *BufInclude; + size_t SizeSource1, SizeSource2, SizeInclude; + amd_comgr_data_t DataSource1, DataSource2, DataInclude; + amd_comgr_data_set_t DataSetIn, DataSetBc, DataSetLinked, DataSetReloc, + DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + size_t Count; + + SizeSource1 = setBuf(TEST_OBJ_DIR "/source1.cl", &BufSource1); + SizeSource2 = setBuf(TEST_OBJ_DIR "/source2.cl", &BufSource2); + SizeInclude = setBuf(TEST_OBJ_DIR "/include-macro.h", &BufInclude); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource1, SizeSource1, BufSource1); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource1, "source1.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource1); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource2); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource2, SizeSource2, BufSource2); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource2, "source2.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource2); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_INCLUDE, &DataInclude); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataInclude, SizeInclude, BufInclude); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataInclude, "include-macro.h"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataInclude); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, + DataAction, DataSetIn, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + Status = + amd_comgr_action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 2) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu BC objects (expected 2)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + // Get bitcode mangled names + amd_comgr_data_t DataBc; + + Status = amd_comgr_action_data_get_data(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + 0, &DataBc); + checkError(Status, "amd_comgr_action_data_get_data"); + +#if 0 + // write bitcode + { + size_t bytes_size = 0; + char *bytes = NULL; + + Status = amd_comgr_get_data(DataBc, &bytes_size, bytes); + checkError(Status, "amd_comgr_get_data"); + + bytes = (char *) malloc(bytes_size); + + Status = amd_comgr_get_data(DataBc, &bytes_size, bytes); + checkError(Status, "amd_comgr_get_data"); + + const char *bitcode_file = "comgr_mangled.bc"; + FILE *file = fopen(bitcode_file, "wb"); + + if (file) + fwrite(bytes, bytes_size, 1, file); + else + return AMD_COMGR_STATUS_ERROR; + + fclose(file); + free(bytes); + } +#endif + + size_t NumNames; + Status = amd_comgr_populate_mangled_names(DataBc, &NumNames); + checkError(Status, "amd_comgr_populate_mangled_names"); + + if (NumNames != 4) { + printf("amd_populate_mangled_names Failed: " + "produced %zu bitcode names (expected 4)\n", + NumNames); + exit(1); + } + + const char *BcNames[] = {"source1", "__clang_ocl_kern_imp_source1", "source2", "__clang_ocl_kern_imp_source2"}; + + for (size_t I = 0; I < NumNames; ++I) { + size_t Size; + Status = amd_comgr_get_mangled_name(DataBc, I, &Size, NULL); + checkError(Status, "amd_comgr_get_mangled_name"); + + char *MName = calloc(Size, sizeof(char)); + Status = amd_comgr_get_mangled_name(DataBc, I, &Size, MName); + checkError(Status, "amd_comgr_get_mangled_name"); + + if (!BcNames[I]) { + printf("Failed, bcNames[%ld] NULL\n", I); + return 1; + } + + if (strcmp(MName, BcNames[I])) { + printf("amd_get_mangled_name from bc Failed: " + "produced '%s' (expected '%s')\n", + MName, BcNames[I]); + exit(1); + } + + free(MName); + } + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + DataAction, DataSetLinked, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu source objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + // Get Mangled Names + amd_comgr_data_t DataExec; + + Status = amd_comgr_action_data_get_data( + DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, 0, &DataExec); + checkError(Status, "amd_comgr_action_data_get_data"); + + Status = amd_comgr_populate_mangled_names(DataExec, &NumNames); + checkError(Status, "amd_comgr_populate_mangled_names"); + + if (NumNames != 6) { + printf("amd_populate_mangled_names Failed: " + "produced %zu executable names (expected 6)\n", + NumNames); + exit(1); + } + + const char *ExecNames[] = {"source1", "source1.kd", "__clang_ocl_kern_imp_source1", "source2", "source2.kd", "__clang_ocl_kern_imp_source2"}; + + for (size_t I = 0; I < NumNames; ++I) { + size_t Size; + Status = amd_comgr_get_mangled_name(DataExec, I, &Size, NULL); + checkError(Status, "amd_comgr_get_mangled_name"); + + char *MName = calloc(Size, sizeof(char)); + Status = amd_comgr_get_mangled_name(DataExec, I, &Size, MName); + checkError(Status, "amd_comgr_get_mangled_name"); + + if (!ExecNames[I]) { + printf("Failed, execNames[%ld] NULL\n", I); + return 1; + } + + if (strcmp(MName, ExecNames[I])) { + printf("amd_get_mangled_name from executable Failed: " + "produced '%s' (expected '%s')\n", + MName, ExecNames[I]); + exit(1); + } + + free(MName); + } + + Status = amd_comgr_release_data(DataSource1); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataSource2); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataInclude); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataBc); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataExec); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource1); + free(BufSource2); + free(BufInclude); +} diff --git a/amd/comgr/test/map_elf_virtual_address_test.c b/amd/comgr/test/map_elf_virtual_address_test.c new file mode 100644 index 0000000000000..8e0491b47cc0c --- /dev/null +++ b/amd/comgr/test/map_elf_virtual_address_test.c @@ -0,0 +1,245 @@ +//===- map_elf_virtual_address_test.c -------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource1, *BufSource2; + size_t SizeSource1, SizeSource2; + amd_comgr_data_t DataSource1, DataSource2; + amd_comgr_data_set_t DataSetExec; + amd_comgr_status_t Status; + + // TODO: We need to add the source code for these objects to the + // repository. We should also update them to include some headers + // in a nobits segment + SizeSource1 = setBuf(TEST_OBJ_DIR "/rocm56slice.b", &BufSource1); + SizeSource2 = setBuf(TEST_OBJ_DIR "/rocm57slice.b", &BufSource2); + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_EXECUTABLE, &DataSource1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource1, SizeSource1, BufSource1); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource1, "rocm56slice.b"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetExec, DataSource1); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_EXECUTABLE, &DataSource2); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource2, SizeSource2, BufSource2); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource2, "rocm57slice.b"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetExec, DataSource2); + checkError(Status, "amd_comgr_data_set_add"); + + size_t Count; + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 2) { + printf("Creating executable data set failed: " + "produced %zu executable objects (expected 2)\n", + Count); + exit(1); + } + + // Test rocm 5.6 elf virtual address mapping + amd_comgr_data_t DataExec; + Status = amd_comgr_action_data_get_data( + DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, 0, &DataExec); + bool Nobits; + uint64_t ElfVirtualAddress = 0x60; + uint64_t CodeObjectOffset = -1; + uint64_t SliceSize = -1; + + // phdr.p_vaddr: 0 + // phdr.p_vaddr + phdr.p_memsz: 0x8c0 + // phdr.p_offset: 0 + // phdr.p_filesz: 0x8c0 + // phdr.p_memsz: 0x8c0 + // codeObjectOffset == elfVirtualAddress - phdr.p_vaddr + phdr.p_offset + // nobits = phdr.p_vaddr >= phdr.p_filesz + // slizesize = phdr.p_memsz - (elfVirtualAddress - phdr.p_vaddr); + Status = amd_comgr_map_elf_virtual_address_to_code_object_offset( + DataExec, ElfVirtualAddress, &CodeObjectOffset, &SliceSize, &Nobits); + checkError(Status, "amd_comgr_map_elf_virtual_address_to_code_object_offset"); + + if (CodeObjectOffset != 0x60 || Nobits != 0 || SliceSize != 0x860) { + printf("elf virtual address map failed for address %#6" PRIx64 "\n" + " Expected: codeObjectOffset = 0x60, nobits = 0, slice = 0x\n" + " Actual: codeObjectOffset = %#6" PRIx64 + ", nobits = %d, slice = %#6" PRIx64 "\n", + ElfVirtualAddress, CodeObjectOffset, Nobits, SliceSize); + exit(1); + } + + ElfVirtualAddress = 0x1400; + CodeObjectOffset = -1; + // phdr.p_vaddr: 0x1000 + // phdr.p_vaddr + phdr.p_memsz: 0x1580 + // phdr.p_offset: 0x1000 + // phdr.p_filesz: 0x580 + // phdr.p_memsz: 0x580 + // codeObjectOffset == elfVirtualAddress - phdr.p_vaddr + phdr.p_offset + // nobits = phdr.p_vaddr >= phdr.p_filesz + // slizesize = phdr.p_memsz - (elfVirtualAddress - phdr.p_vaddr); + Status = amd_comgr_map_elf_virtual_address_to_code_object_offset( + DataExec, ElfVirtualAddress, &CodeObjectOffset, &SliceSize, &Nobits); + checkError(Status, "amd_comgr_map_elf_virtual_address_to_code_object_offset"); + + if (CodeObjectOffset != 0x1400 || Nobits != 0 || SliceSize != 0x180) { + printf("elf virtual address map failed for address %#6" PRIx64 "\n" + " Expected: codeObjectOffset = 0x1400, nobits = 0, slice = 0x180\n" + " Actual: codeObjectOffset = %#6" PRIx64 + ", nobits = %d, slice = %#6" PRIx64 "\n", + ElfVirtualAddress, CodeObjectOffset, Nobits, SliceSize); + exit(1); + } + + ElfVirtualAddress = 0x2035; + CodeObjectOffset = -1; + // phdr.p_vaddr: 0x2000 + // phdr.p_vaddr + phdr.p_memsz: 0x2070 + // phdr.p_offset: 0x2000 + // phdr.p_filesz: 0x70 + // phdr.p_memsz: 0x70 + // codeObjectOffset == elfVirtualAddress - phdr.p_vaddr + phdr.p_offset + // nobits = phdr.p_vaddr >= phdr.p_filesz + // slizesize = phdr.p_memsz - (elfVirtualAddress - phdr.p_vaddr); + Status = amd_comgr_map_elf_virtual_address_to_code_object_offset( + DataExec, ElfVirtualAddress, &CodeObjectOffset, &SliceSize, &Nobits); + checkError(Status, "amd_comgr_map_elf_virtual_address_to_code_object_offset"); + + if (CodeObjectOffset != 0x2035 || Nobits != 0 || SliceSize != 0x3b) { + printf("elf virtual address map failed for address %#6" PRIx64 "\n" + " Expected: codeObjectOffset = 0x2035, nobits = 0, slice = 0x3b\n" + " Actual: codeObjectOffset = %#6" PRIx64 + ", nobits = %d, slice = %#6" PRIx64 "\n", + ElfVirtualAddress, CodeObjectOffset, Nobits, SliceSize); + exit(1); + } + + ElfVirtualAddress = 0x9000; + CodeObjectOffset = -1; + // invalid elf virtual address + Status = amd_comgr_map_elf_virtual_address_to_code_object_offset( + DataExec, ElfVirtualAddress, &CodeObjectOffset, &SliceSize, &Nobits); + if (Status != AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT) { + printf("elf virtual address map succeded on invalid address:\n" + " Address = %#6" PRIx64 "\n" + " codeObjectOffset = %#6" PRIx64 "\n", + ElfVirtualAddress, CodeObjectOffset); + exit(1); + } + + // Test rocm 5.7 elf virtual address mapping + Status = amd_comgr_action_data_get_data( + DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, 1, &DataExec); + ElfVirtualAddress = 0x60; + CodeObjectOffset = -1; + // phdr.p_vaddr: 0 + // phdr.p_vaddr + phdr.p_memsz: 0x8c0 + // phdr.p_offset: 0 + // phdr.p_filesz: 0x8c0 + // phdr.p_memsz: 0x8c0 + // codeObjectOffset == elfVirtualAddress - phdr.p_vaddr + phdr.p_offset + // nobits = phdr.p_vaddr >= phdr.p_filesz + // slizesize = phdr.p_memsz - (elfVirtualAddress - phdr.p_vaddr); + Status = amd_comgr_map_elf_virtual_address_to_code_object_offset( + DataExec, ElfVirtualAddress, &CodeObjectOffset, &SliceSize, &Nobits); + checkError(Status, "amd_comgr_map_elf_virtual_address_to_code_object_offset"); + + if (CodeObjectOffset != 0x60 || Nobits != 0 || SliceSize != 0x860) { + printf("elf virtual address map failed for address %#6" PRIx64 "\n" + " Expected: codeObjectOffset = 0x60, nobits = 0, slice = 0x860\n" + " Actual: codeObjectOffset = %#6" PRIx64 + ", nobits = %d, slice = %#6" PRIx64 "\n", + ElfVirtualAddress, CodeObjectOffset, Nobits, SliceSize); + exit(1); + } + + ElfVirtualAddress = 0x1a00; + CodeObjectOffset = -1; + // phdr.p_vaddr: 0x1900 + // phdr.p_vaddr + phdr.p_memsz: 0x1e80 + // phdr.p_offset: 0x900 + // phdr.p_filesz: 0x580 + // phdr.p_memsz: 0x580 + // codeObjectOffset == elfVirtualAddress - phdr.p_vaddr + phdr.p_offset + // nobits = phdr.p_vaddr >= phdr.p_filesz + // slizesize = phdr.p_memsz - (elfVirtualAddress - phdr.p_vaddr); + Status = amd_comgr_map_elf_virtual_address_to_code_object_offset( + DataExec, ElfVirtualAddress, &CodeObjectOffset, &SliceSize, &Nobits); + checkError(Status, "amd_comgr_map_elf_virtual_address_to_code_object_offset"); + + if (CodeObjectOffset != 0xa00 || Nobits != 0 || SliceSize != 0x480) { + printf("elf virtual address map failed for address %#6" PRIx64 "\n" + " Expected: codeObjectOffset = 0xa00, nobits = 0, slice = 0x480\n" + " Actual: codeObjectOffset = %#6" PRIx64 + ", nobits = %d, slice = %#6" PRIx64 "\n", + ElfVirtualAddress, CodeObjectOffset, Nobits, SliceSize); + exit(1); + } + + ElfVirtualAddress = 0x2e90; + CodeObjectOffset = -1; + // phdr.p_vaddr: 0x2e80 + // phdr.p_vaddr + phdr.p_memsz: 0x2ef0 + // phdr.p_offset: 0xe80 + // phdr.p_filesz: 0x70 + // phdr.p_memsz: 0x70 + // codeObjectOffset == elfVirtualAddress - phdr.p_vaddr + phdr.p_offset + // nobits = phdr.p_vaddr >= phdr.p_filesz + // slizesize = phdr.p_memsz - (elfVirtualAddress - phdr.p_vaddr); + Status = amd_comgr_map_elf_virtual_address_to_code_object_offset( + DataExec, ElfVirtualAddress, &CodeObjectOffset, &SliceSize, &Nobits); + checkError(Status, "amd_comgr_map_elf_virtual_address_to_code_object_offset"); + + if (CodeObjectOffset != 0xe90 || Nobits != 0 || SliceSize != 0x60) { + printf("elf virtual address map failed for address %#6" PRIx64 "\n" + " Expected: codeObjectOffset = 0x2035, nobits = 0, slice = 0x60\n" + " Actual: codeObjectOffset = %#6" PRIx64 + ", nobits = %d, slice = %#6" PRIx64 "\n", + ElfVirtualAddress, CodeObjectOffset, Nobits, SliceSize); + exit(1); + } + + ElfVirtualAddress = 0x9000; + CodeObjectOffset = -1; + // invalid elf virtual address + Status = amd_comgr_map_elf_virtual_address_to_code_object_offset( + DataExec, ElfVirtualAddress, &CodeObjectOffset, &SliceSize, &Nobits); + if (Status != AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT) { + printf("elf virtual address map succeded on invalid address:\n" + " Address = %#6" PRIx64 "\n" + " codeObjectOffset = %#6" PRIx64 "\n", + ElfVirtualAddress, CodeObjectOffset); + exit(1); + } + + Status = amd_comgr_release_data(DataSource1); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataSource2); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataExec); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + free(BufSource1); + free(BufSource2); +} diff --git a/amd/comgr/test/metadata_merge_test.c b/amd/comgr/test/metadata_merge_test.c new file mode 100644 index 0000000000000..ba2fae4b715ee --- /dev/null +++ b/amd/comgr/test/metadata_merge_test.c @@ -0,0 +1,176 @@ +//===- metadata_merge_test.c ----------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +void metadataTest1(void); + +typedef struct TestMetaDataS { + char *Buf; + amd_comgr_data_t Data; + amd_comgr_metadata_node_t Root; +} test_meta_data_t; + +void read_metadata(test_meta_data_t *MetaData, const char *File, + bool ErrorExpected, bool Display) { + long Size; + amd_comgr_status_t Status; + amd_comgr_metadata_kind_t Mkind = AMD_COMGR_METADATA_KIND_NULL; + + // Read input file + char Buffer[1024]; + snprintf(Buffer, 1024, "%s/%s", TEST_OBJ_DIR, File); + Size = setBuf(Buffer, &MetaData->Buf); + + Status = + amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &MetaData->Data); + checkError(Status, "amd_comgr_create_data"); + + Status = amd_comgr_set_data(MetaData->Data, Size, MetaData->Buf); + checkError(Status, "amd_comgr_set_data"); + + Status = amd_comgr_set_data_name(MetaData->Data, NULL); + checkError(Status, "amd_comgr_set_data_name"); + + // Get metadata from data object + if (Display) { + printf("Get metadata from %s\n", File); + } + + Status = amd_comgr_get_data_metadata(MetaData->Data, &MetaData->Root); + if (!ErrorExpected && Status) { + printf("Unexpected error from amd_comgr_get_data_metadata\n"); + exit(1); + } else { + return; + } + + checkError(Status, "amd_comgr_get_data_metadata"); + + // the root must be map + Status = amd_comgr_get_metadata_kind(MetaData->Root, &Mkind); + checkError(Status, "amd_comgr_get_metadata_kind"); + if (Mkind != AMD_COMGR_METADATA_KIND_MAP) { + printf("Root is not map\n"); + exit(1); + } + + if (Display) { + // print code object metadata + int Indent = 0; + printf("Metadata for file %s : start\n", File); + Status = amd_comgr_iterate_map_metadata(MetaData->Root, printEntry, + (void *)&Indent); + checkError(Status, "amd_comgr_iterate_map_metadata"); + printf("Metadata for file %s : end\n\n", File); + } +} + +void lookup_meta_data(test_meta_data_t *MetaData, const char *Key, + amd_comgr_metadata_kind_t Kind, void *Data, + bool ErrorExpected) { + amd_comgr_status_t Status; + amd_comgr_metadata_node_t LookupNode; + amd_comgr_metadata_kind_t LookupKind; + + Status = amd_comgr_metadata_lookup(MetaData->Root, Key, &LookupNode); + checkError(Status, "amd_comgr_metadata_lookup"); + + Status = amd_comgr_get_metadata_kind(LookupNode, &LookupKind); + if (!ErrorExpected && Status) { + printf("Unexpected error from amd_comgr_get_metadata_kind\n"); + exit(1); + } else { + Status = amd_comgr_destroy_metadata(LookupNode); + checkError(Status, "amd_comgr_destroy_metadata"); + return; + } + + checkError(Status, "amd_comgr_get_metadata_kind"); + if (LookupKind != Kind) { + printf("Metadata kind mismatch in lookup\n"); + exit(1); + } + + switch (Kind) { + case AMD_COMGR_METADATA_KIND_LIST: { + size_t Size = 0; + size_t Nentries = *((size_t *)Data); + + Status = amd_comgr_get_metadata_list_size(LookupNode, &Size); + checkError(Status, "amd_comgr_get_metadata_list_size"); + if (Size != Nentries) { + printf("List node size mismatch : expected %zu got %zu\n", Nentries, + Size); + exit(1); + } + } break; + + default: + printf("Unknown kind\n"); + exit(1); + } + + Status = amd_comgr_destroy_metadata(LookupNode); + checkError(Status, "amd_comgr_destroy_metadata"); +} + +void close_meta_data(test_meta_data_t *MetaData) { + amd_comgr_status_t Status; + + Status = amd_comgr_destroy_metadata(MetaData->Root); + checkError(Status, "amd_comgr_destroy_metadata"); + + Status = amd_comgr_release_data(MetaData->Data); + checkError(Status, "amd_comgr_release_data"); + free(MetaData->Buf); + + memset(MetaData, 0, sizeof(test_meta_data_t)); +} + +int main(int argc, char *argv[]) { + test_meta_data_t MetaData; + + memset(&MetaData, 0, sizeof(test_meta_data_t)); + +#define READ_METADATA(meta, file, is_error, display) \ + do { \ + read_metadata(&meta, file, is_error, display); \ + close_meta_data(&meta); \ + } while (0) + +#define LOOKUP_LIST_METADATA(meta, file, key, size, is_error) \ + do { \ + size_t n = size; \ + read_metadata(&meta, file, is_error, false); \ + lookup_meta_data(&meta, key, AMD_COMGR_METADATA_KIND_LIST, &n, is_error); \ + close_meta_data(&meta); \ + } while (0) + + READ_METADATA(MetaData, "source1-v2.o", false, true); + READ_METADATA(MetaData, "source2-v2.o", false, true); + READ_METADATA(MetaData, "source1-v3.o", false, true); + READ_METADATA(MetaData, "source2-v3.o", false, true); + + READ_METADATA(MetaData, "shared12-v2.so", true, true); + + LOOKUP_LIST_METADATA(MetaData, "shared12-v3.so", "amdhsa.printf", 1, false); + LOOKUP_LIST_METADATA(MetaData, "shared12-v3.so", "amdhsa.kernels", 2, false); + LOOKUP_LIST_METADATA(MetaData, "shared12-v3.so", "amdhsa.version", 2, false); + + LOOKUP_LIST_METADATA(MetaData, "shared14-v3.so", "amdhsa.version", 2, true); + LOOKUP_LIST_METADATA(MetaData, "shared23-v3.so", "amdhsa.kernels", 2, true); + + printf("Metadata merge tests : passed\n"); + + return 0; +} diff --git a/amd/comgr/test/metadata_msgpack_test.c b/amd/comgr/test/metadata_msgpack_test.c new file mode 100644 index 0000000000000..17fed81e4f98d --- /dev/null +++ b/amd/comgr/test/metadata_msgpack_test.c @@ -0,0 +1,86 @@ +//===- metadata_msgpack_test.c --------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *Arg = NULL; + long Size1; + char *Buf; + amd_comgr_data_t DataIn; + amd_comgr_status_t Status; + amd_comgr_metadata_kind_t Mkind = AMD_COMGR_METADATA_KIND_NULL; + + // Read input file + Size1 = setBuf(TEST_OBJ_DIR "/shared-v3.so", &Buf); + + // Create data object + { + printf("Test create input data object\n"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &DataIn); + checkError(Status, "amd_comgr_create_data"); + + Status = amd_comgr_set_data(DataIn, Size1, Buf); + checkError(Status, "amd_comgr_set_data"); + + Status = amd_comgr_set_data_name(DataIn, Arg); + checkError(Status, "amd_comgr_set_data_name"); + } + + // Get metadata from data object + { + printf("Get metadata from shared.so\n"); + + amd_comgr_metadata_node_t Meta; + Status = amd_comgr_get_data_metadata(DataIn, &Meta); + checkError(Status, "amd_comgr_get_data_metadata"); + + // the root must be map + Status = amd_comgr_get_metadata_kind(Meta, &Mkind); + checkError(Status, "amd_comgr_get_metadata_kind"); + if (Mkind != AMD_COMGR_METADATA_KIND_MAP) { + printf("Root is not map\n"); + exit(1); + } + + amd_comgr_metadata_node_t MetaLookup; + amd_comgr_metadata_kind_t MkindLookup; + Status = amd_comgr_metadata_lookup(Meta, "amdhsa.version", &MetaLookup); + checkError(Status, "amd_comgr_metadata_lookup"); + Status = amd_comgr_get_metadata_kind(MetaLookup, &MkindLookup); + checkError(Status, "amd_comgr_get_metadata_kind"); + if (MkindLookup != AMD_COMGR_METADATA_KIND_LIST) { + printf("Lookup of Version should return a list\n"); + exit(1); + } + Status = amd_comgr_destroy_metadata(MetaLookup); + checkError(Status, "amd_comgr_destroy_metadata"); + + // print code object metadata + int Indent = 0; + Status = amd_comgr_iterate_map_metadata(Meta, printEntry, (void *)&Indent); + checkError(Status, "amd_comgr_iterate_map_metadata"); + + Status = amd_comgr_destroy_metadata(Meta); + checkError(Status, "amd_comgr_destroy_metadata"); + } + + { + printf("Cleanup ...\n"); + Status = amd_comgr_release_data(DataIn); + checkError(Status, "amd_comgr_release_data"); + free(Buf); + } + + return 0; +} diff --git a/amd/comgr/test/metadata_multiple_msgpacks_test.c b/amd/comgr/test/metadata_multiple_msgpacks_test.c new file mode 100644 index 0000000000000..bd0b86f1742c1 --- /dev/null +++ b/amd/comgr/test/metadata_multiple_msgpacks_test.c @@ -0,0 +1,100 @@ +//===- metadata_multiple_msgpacks_test.c ----------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +typedef struct TestMetaDataS { + char *Buf; + amd_comgr_data_t Data; + amd_comgr_metadata_node_t Root; +} test_meta_data_t; + +void read_metadata(test_meta_data_t *MetaData, const char *File, bool IsErr) { + long Size; + amd_comgr_status_t Status; + amd_comgr_metadata_kind_t Mkind = AMD_COMGR_METADATA_KIND_NULL; + + // Read input file + char Buffer[1024]; + snprintf(Buffer, 1024, "%s/%s", TEST_OBJ_DIR, File); + Size = setBuf(Buffer, &MetaData->Buf); + + Status = + amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &MetaData->Data); + checkError(Status, "amd_comgr_create_data"); + + Status = amd_comgr_set_data(MetaData->Data, Size, MetaData->Buf); + checkError(Status, "amd_comgr_set_data"); + + Status = amd_comgr_set_data_name(MetaData->Data, NULL); + checkError(Status, "amd_comgr_set_data_name"); + + // Get metadata from data object + printf("Get metadata from %s\n", File); + + Status = amd_comgr_get_data_metadata(MetaData->Data, &MetaData->Root); + checkError(Status, "amd_comgr_get_data_metadata"); + + // the root must be map + Status = amd_comgr_get_metadata_kind(MetaData->Root, &Mkind); + checkError(Status, "amd_comgr_get_metadata_kind"); + if (Mkind != AMD_COMGR_METADATA_KIND_MAP) { + printf("Root is not map\n"); + exit(1); + } + + // iterate code object metadata + int Indent = 0; + printf("Metadata for file %s : start\n", File); + Status = amd_comgr_iterate_map_metadata(MetaData->Root, printEntry, + (void *)&Indent); + if (Status) { + if (IsErr) + return; + checkError(Status, "amd_comgr_iterate_map_metadata"); + } else if (IsErr) { + printf("Unexpected success from amd_comgr_iterate_map_metadata\n"); + exit(1); + } + printf("Metadata for file %s : end\n\n", File); +} + +void close_meta_data(test_meta_data_t *MetaData) { + amd_comgr_status_t Status; + + Status = amd_comgr_destroy_metadata(MetaData->Root); + checkError(Status, "amd_comgr_destroy_metadata"); + + Status = amd_comgr_release_data(MetaData->Data); + checkError(Status, "amd_comgr_release_data"); + free(MetaData->Buf); + + memset(MetaData, 0, sizeof(test_meta_data_t)); +} + +int main(int argc, char *argv[]) { + test_meta_data_t MetaData; + + memset(&MetaData, 0, sizeof(test_meta_data_t)); + +#define READ_METADATA(meta, file, is_error) \ + do { \ + read_metadata(&meta, file, is_error); \ + close_meta_data(&meta); \ + } while (0) + + READ_METADATA(MetaData, "multiple-note-records.out", false); + READ_METADATA(MetaData, "multiple-note-records-one-kernel.out", false); + + printf("Metadata Multiple MsgPacks tests : passed\n"); + return 0; +} diff --git a/amd/comgr/test/metadata_tp_test.c b/amd/comgr/test/metadata_tp_test.c new file mode 100644 index 0000000000000..10cb4458bd290 --- /dev/null +++ b/amd/comgr/test/metadata_tp_test.c @@ -0,0 +1,42 @@ +//===- metadata_tp_test.c -------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + amd_comgr_status_t Status; + + // how many isa_names do we support? + size_t IsaCounts; + Status = amd_comgr_get_isa_count(&IsaCounts); + checkError(Status, "amd_comgr_get_isa_count"); + printf("isa count = %zu\n\n", IsaCounts); + + // print the list + printf("*** List of ISA names supported:\n"); + for (size_t I = 0; I < IsaCounts; I++) { + const char *Name; + Status = amd_comgr_get_isa_name(I, &Name); + checkError(Status, "amd_comgr_get_isa_name"); + printf("%zu: %s\n", I, Name); + amd_comgr_metadata_node_t Meta; + Status = amd_comgr_get_isa_metadata(Name, &Meta); + checkError(Status, "amd_comgr_get_isa_metadata"); + int Indent = 1; + Status = amd_comgr_iterate_map_metadata(Meta, printEntry, (void *)&Indent); + checkError(Status, "amd_comgr_iterate_map_metadata"); + Status = amd_comgr_destroy_metadata(Meta); + checkError(Status, "amd_comgr_destroy_metadata"); + } + + return 0; +} diff --git a/amd/comgr/test/metadata_yaml_test.c b/amd/comgr/test/metadata_yaml_test.c new file mode 100644 index 0000000000000..d4b5bba442ffd --- /dev/null +++ b/amd/comgr/test/metadata_yaml_test.c @@ -0,0 +1,86 @@ +//===- metadata_yaml_test.c -----------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *Arg = NULL; + long Size1; + char *Buf; + amd_comgr_data_t DataIn; + amd_comgr_status_t Status; + amd_comgr_metadata_kind_t Mkind = AMD_COMGR_METADATA_KIND_NULL; + + // Read input file + Size1 = setBuf(TEST_OBJ_DIR "/shared-v2.so", &Buf); + + // Create data object + { + printf("Test create input data object\n"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_RELOCATABLE, &DataIn); + checkError(Status, "amd_comgr_create_data"); + + Status = amd_comgr_set_data(DataIn, Size1, Buf); + checkError(Status, "amd_comgr_set_data"); + + Status = amd_comgr_set_data_name(DataIn, Arg); + checkError(Status, "amd_comgr_set_data_name"); + } + + // Get metadata from data object + { + printf("Get metadata from shared-v2.so\n"); + + amd_comgr_metadata_node_t Meta; + Status = amd_comgr_get_data_metadata(DataIn, &Meta); + checkError(Status, "amd_comgr_get_data_metadata"); + + // the root must be map + Status = amd_comgr_get_metadata_kind(Meta, &Mkind); + checkError(Status, "amd_comgr_get_metadata_kind"); + if (Mkind != AMD_COMGR_METADATA_KIND_MAP) { + printf("Root is not map\n"); + exit(1); + } + + amd_comgr_metadata_node_t MetaLookup; + amd_comgr_metadata_kind_t MkindLookup; + Status = amd_comgr_metadata_lookup(Meta, "Version", &MetaLookup); + checkError(Status, "amd_comgr_metadata_lookup"); + Status = amd_comgr_get_metadata_kind(MetaLookup, &MkindLookup); + checkError(Status, "amd_comgr_get_metadata_kind"); + if (MkindLookup != AMD_COMGR_METADATA_KIND_LIST) { + printf("Lookup of Version should return a list\n"); + exit(1); + } + Status = amd_comgr_destroy_metadata(MetaLookup); + checkError(Status, "amd_comgr_destroy_metadata"); + + // print code object metadata + int Indent = 0; + Status = amd_comgr_iterate_map_metadata(Meta, printEntry, (void *)&Indent); + checkError(Status, "amd_comgr_iterate_map_metadata"); + + Status = amd_comgr_destroy_metadata(Meta); + checkError(Status, "amd_comgr_destroy_metadata"); + } + + { + printf("Cleanup ...\n"); + Status = amd_comgr_release_data(DataIn); + checkError(Status, "amd_comgr_release_data"); + free(Buf); + } + + return 0; +} diff --git a/amd/comgr/test/multithread_test.cpp b/amd/comgr/test/multithread_test.cpp new file mode 100644 index 0000000000000..7e9c916369df0 --- /dev/null +++ b/amd/comgr/test/multithread_test.cpp @@ -0,0 +1,181 @@ +//===- multithread_test.cpp -----------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include +#include +#include +#include + +int compileMin(int Index) { + + char *BufSource1, *BufSource2, *BufInclude; + size_t SizeSource1, SizeSource2, SizeInclude; + amd_comgr_data_t DataSource1, DataSource2, DataInclude; + amd_comgr_data_set_t DataSetIn, DataSetBc, DataSetLinked, DataSetReloc, + DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + size_t Count; + + SizeSource1 = setBuf(TEST_OBJ_DIR "/source1.cl", &BufSource1); + SizeSource2 = setBuf(TEST_OBJ_DIR "/source2.cl", &BufSource2); + SizeInclude = setBuf(TEST_OBJ_DIR "/include-macro.h", &BufInclude); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource1, SizeSource1, BufSource1); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource1, "source1.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource1); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource2); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource2, SizeSource2, BufSource2); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource2, "source2.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource2); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_INCLUDE, &DataInclude); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataInclude, SizeInclude, BufInclude); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataInclude, "include-macro.h"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataInclude); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, + DataAction, DataSetIn, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + Status = + amd_comgr_action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 2) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu BC objects (expected 2)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + DataAction, DataSetLinked, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu source objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_release_data(DataSource1); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataSource2); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataInclude); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource1); + free(BufSource2); + free(BufInclude); + + return 0; +} + +int main(int argc, char *argv[]) { + + std::vector CompileThreads; + + for (int I = 0; I < 30; I++) + CompileThreads.push_back(std::thread(compileMin, I)); + + for (auto &Thread : CompileThreads) + Thread.join(); +} diff --git a/amd/comgr/test/name_expression_map_test.c b/amd/comgr/test/name_expression_map_test.c new file mode 100644 index 0000000000000..33dd1d70e1273 --- /dev/null +++ b/amd/comgr/test/name_expression_map_test.c @@ -0,0 +1,396 @@ +//===- name_expression_map_test.c -----------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource; + size_t SizeSource; + amd_comgr_data_t DataSource; + amd_comgr_data_set_t DataSetIn, DataSetBc, DataSetLinked, DataSetReloc, + DataSetExec, DataSetReloc2, DataSetExec2; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + size_t Count; + const char *CompileOptions[] = {"-nogpulib", "-nogpuinc"}; + size_t CompileOptionsCount = + sizeof(CompileOptions) / sizeof(CompileOptions[0]); + + SizeSource = setBuf(TEST_OBJ_DIR "/name-expression.hip", &BufSource); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource, SizeSource, BufSource); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource, "name-expression.hip"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = + amd_comgr_action_info_set_language(DataAction, AMD_COMGR_LANGUAGE_HIP); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx900"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + Status = amd_comgr_action_info_set_option_list(DataAction, CompileOptions, + CompileOptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action( + AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, DataAction, + DataSetIn, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + // Check name_expression_map for Bitcodes + amd_comgr_data_t DataBc; + + Status = amd_comgr_action_data_get_data(DataSetBc, AMD_COMGR_DATA_KIND_BC, 0, + &DataBc); + checkError(Status, "amd_comgr_action_data_get_data"); + +#if 0 + // write bitcode + { + size_t bytes_size = 0; + char *bytes = NULL; + + Status = amd_comgr_get_data(DataBc, &bytes_size, bytes); + checkError(Status, "amd_comgr_get_data"); + + bytes = (char *) malloc(bytes_size); + + Status = amd_comgr_get_data(DataBc, &bytes_size, bytes); + checkError(Status, "amd_comgr_get_data"); + + const char *bitcode_file = "comgr_name_expression.bc"; + FILE *file = fopen(bitcode_file, "wb"); + + if (file) + fwrite(bytes, bytes_size, 1, file); + else + return AMD_COMGR_STATUS_ERROR; + + fclose(file); + free(bytes); + } +#endif + + size_t NumNames; + Status = amd_comgr_populate_name_expression_map(DataBc, &NumNames); + checkError(Status, "amd_comgr_populate_name_expression_map"); + + if (NumNames != 2) { + printf("amd_populate_name_expression_map Failed: " + "produced %zu bitcode names (expected 2)\n", + NumNames); + exit(1); + } + + const char *NameExpressions[] = { + "my_kernel_BOO(2+1),float >", + "my_kernel_FOO(2+1),float >"}; + const char *SymbolNames[] = {"_Z13my_kernel_BOOILi3EfEvPT0_", + "_Z13my_kernel_FOOILi3EfEvPT0_"}; + + for (size_t I = 0; I < NumNames; ++I) { + size_t Size; + Status = amd_comgr_map_name_expression_to_symbol_name( + DataBc, &Size, NameExpressions[I], NULL); + checkError(Status, "amd_map_name_expression_to_symbol_name"); + + char *SymbolName = calloc(Size, sizeof(char)); + Status = amd_comgr_map_name_expression_to_symbol_name( + DataBc, &Size, NameExpressions[I], SymbolName); + checkError(Status, "amd_map_name_expression_to_symbol_name"); + + if (!SymbolNames[I]) { + printf("Failed, symbolNames[%ld] NULL\n", I); + return 1; + } + + if (strcmp(SymbolName, SymbolNames[I])) { + printf("amd_comgr_map_name_expression_to_symbol_name from bc Failed: " + "produced '%s' (expected '%s')\n", + SymbolName, SymbolNames[I]); + exit(1); + } + + free(SymbolName); + } + + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + DataAction, DataSetLinked, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu source objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + // Check name_expression_map for Code Objects + amd_comgr_data_t DataExec; + + Status = amd_comgr_action_data_get_data( + DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, 0, &DataExec); +#if 0 + // write code object + { + size_t bytes_size = 0; + char *bytes = NULL; + + Status = amd_comgr_get_data(DataExec, &bytes_size, bytes); + checkError(Status, "amd_comgr_get_data"); + + bytes = (char *) malloc(bytes_size); + + Status = amd_comgr_get_data(DataExec, &bytes_size, bytes); + checkError(Status, "amd_comgr_get_data"); + + const char *code_object_file = "comgr_name_expression.o"; + FILE *file = fopen(code_object_file, "wb"); + + if (file) + fwrite(bytes, bytes_size, 1, file); + else + return AMD_COMGR_STATUS_ERROR; + + fclose(file); + free(bytes); + } +#endif + + Status = amd_comgr_populate_name_expression_map(DataExec, &NumNames); + checkError(Status, "amd_comgr_populate_name_expression_map"); + + if (NumNames != 2) { + printf("amd_populate_name_expression_map Failed: " + "produced %zu code object names (expected 2)\n", + NumNames); + exit(1); + } + + for (size_t I = 0; I < NumNames; ++I) { + size_t Size; + Status = amd_comgr_map_name_expression_to_symbol_name( + DataExec, &Size, NameExpressions[I], NULL); + checkError(Status, "amd_map_name_expression_to_symbol_name"); + + char *SymbolName = calloc(Size, sizeof(char)); + Status = amd_comgr_map_name_expression_to_symbol_name( + DataExec, &Size, NameExpressions[I], SymbolName); + checkError(Status, "amd_map_name_expression_to_symbol_name"); + + if (!SymbolNames[I]) { + printf("Failed, symbolNames[%ld] NULL\n", I); + return 1; + } + + if (strcmp(SymbolName, SymbolNames[I])) { + printf("amd_comgr_map_name_expression_to_symbol_name from exec Failed: " + "produced '%s' (expected '%s')\n", + SymbolName, SymbolNames[I]); + exit(1); + } + + free(SymbolName); + } + + // + // Test AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE + // + Status = amd_comgr_create_data_set(&DataSetReloc2); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, CompileOptions, + CompileOptionsCount); + checkError(Status, "amd_comgr_action_info_set_option_list"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE, + DataAction, DataSetIn, DataSetReloc2); + checkError(Status, "amd_comgr_do_action"); + + // Check name_expression_map for Bitcodes + amd_comgr_data_t DataReloc2; + + Status = amd_comgr_action_data_get_data( + DataSetReloc2, AMD_COMGR_DATA_KIND_RELOCATABLE, 0, &DataReloc2); + checkError(Status, "amd_comgr_action_data_get_data"); + + Status = amd_comgr_create_data_set(&DataSetExec2); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc2, DataSetExec2); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec2, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + // Check name_expression_map for Code Objects + amd_comgr_data_t DataExec2; + + Status = amd_comgr_action_data_get_data( + DataSetExec2, AMD_COMGR_DATA_KIND_EXECUTABLE, 0, &DataExec2); +#if 0 + // write code object + { + size_t bytes_size = 0; + char *bytes = NULL; + + Status = amd_comgr_get_data(DataExec2, &bytes_size, bytes); + checkError(Status, "amd_comgr_get_data"); + + bytes = (char *) malloc(bytes_size); + + Status = amd_comgr_get_data(DataExec2, &bytes_size, bytes); + checkError(Status, "amd_comgr_get_data"); + + const char *code_object_file = "comgr_name_expression.o"; + FILE *file = fopen(code_object_file, "wb"); + + if (file) + fwrite(bytes, bytes_size, 1, file); + else + return AMD_COMGR_STATUS_ERROR; + + fclose(file); + free(bytes); + } +#endif + + Status = amd_comgr_populate_name_expression_map(DataExec2, &NumNames); + checkError(Status, "amd_comgr_populate_name_expression_map"); + + if (NumNames != 2) { + printf("amd_populate_name_expression_map Failed: " + "produced %zu code object names (expected 2)\n", + NumNames); + exit(1); + } + + for (size_t I = 0; I < NumNames; ++I) { + size_t Size; + Status = amd_comgr_map_name_expression_to_symbol_name( + DataExec2, &Size, NameExpressions[I], NULL); + checkError(Status, "amd_map_name_expression_to_symbol_name"); + + char *SymbolName = calloc(Size, sizeof(char)); + Status = amd_comgr_map_name_expression_to_symbol_name( + DataExec2, &Size, NameExpressions[I], SymbolName); + checkError(Status, "amd_map_name_expression_to_symbol_name"); + + if (!SymbolNames[I]) { + printf("Failed, symbolNames[%ld] NULL\n", I); + return 1; + } + + if (strcmp(SymbolName, SymbolNames[I])) { + printf("amd_comgr_map_name_expression_to_symbol_name from exec Failed: " + "produced '%s' (expected '%s')\n", + SymbolName, SymbolNames[I]); + exit(1); + } + + free(SymbolName); + } + + Status = amd_comgr_release_data(DataSource); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataBc); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataExec); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc2); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec2); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource); +} diff --git a/amd/comgr/test/nested_kernel_test.c b/amd/comgr/test/nested_kernel_test.c new file mode 100644 index 0000000000000..bf2b07062d8f1 --- /dev/null +++ b/amd/comgr/test/nested_kernel_test.c @@ -0,0 +1,164 @@ +//===- nested_kernel_test.c -----------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + char *BufSource1, *BufSource2, *BufInclude; + size_t SizeSource1, SizeSource2, SizeInclude; + amd_comgr_data_t DataSource1, DataSource2, DataInclude; + amd_comgr_data_set_t DataSetIn, DataSetBc, DataSetLinked, DataSetReloc, + DataSetExec; + amd_comgr_action_info_t DataAction; + amd_comgr_status_t Status; + size_t Count; + + SizeSource1 = setBuf(TEST_OBJ_DIR "/nested-kernel1.cl", &BufSource1); + SizeSource2 = setBuf(TEST_OBJ_DIR "/nested-kernel2.cl", &BufSource2); + SizeInclude = setBuf(TEST_OBJ_DIR "/include-nested.h", &BufInclude); + + Status = amd_comgr_create_data_set(&DataSetIn); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource1); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource1, SizeSource1, BufSource1); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource1, "nested-kernel1.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource1); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_SOURCE, &DataSource2); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataSource2, SizeSource2, BufSource2); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataSource2, "nested-kernel2.cl"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataSource2); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_INCLUDE, &DataInclude); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataInclude, SizeInclude, BufInclude); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataInclude, "include-nested.h"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetIn, DataInclude); + checkError(Status, "amd_comgr_data_set_add"); + + Status = amd_comgr_create_action_info(&DataAction); + checkError(Status, "amd_comgr_create_action_info"); + Status = amd_comgr_action_info_set_language(DataAction, + AMD_COMGR_LANGUAGE_OPENCL_1_2); + checkError(Status, "amd_comgr_action_info_set_language"); + Status = amd_comgr_action_info_set_isa_name(DataAction, + "amdgcn-amd-amdhsa--gfx803"); + checkError(Status, "amd_comgr_action_info_set_isa_name"); + + Status = amd_comgr_create_data_set(&DataSetBc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, + DataAction, DataSetIn, DataSetBc); + checkError(Status, "amd_comgr_do_action"); + + Status = + amd_comgr_action_data_count(DataSetBc, AMD_COMGR_DATA_KIND_BC, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 2) { + printf("AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC Failed: " + "produced %zu BC objects (expected 2)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, DataAction, + DataSetBc, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_BC_TO_BC Failed: " + "produced %zu BC objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + DataAction, DataSetLinked, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetReloc, + AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu source objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_action_info_set_option_list(DataAction, NULL, 0); + checkError(Status, "amd_comgr_action_info_set_option_list"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + DataAction, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count(DataSetExec, + AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + + Status = amd_comgr_release_data(DataSource1); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataSource2); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataInclude); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_destroy_data_set(DataSetIn); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetBc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_action_info(DataAction); + checkError(Status, "amd_comgr_destroy_action_info"); + free(BufSource1); + free(BufSource2); + free(BufInclude); +} diff --git a/amd/comgr/test/source/cube.hip b/amd/comgr/test/source/cube.hip new file mode 100644 index 0000000000000..8766aa2613a19 --- /dev/null +++ b/amd/comgr/test/source/cube.hip @@ -0,0 +1,3 @@ +void cube(int *j) { + *j = *j * *j * *j; +} diff --git a/amd/comgr/test/source/device_libs.cl b/amd/comgr/test/source/device_libs.cl new file mode 100644 index 0000000000000..b1983d854d0cf --- /dev/null +++ b/amd/comgr/test/source/device_libs.cl @@ -0,0 +1,39 @@ +extern const __constant bool __oclc_finite_only_opt; +extern const __constant bool __oclc_unsafe_math_opt; +extern const __constant bool __oclc_wavefrontsize64; +extern const __constant int __oclc_ISA_version; +extern const __constant int __oclc_ABI_version; + +void kernel device_libs(__global float *status) { + + if (__oclc_finite_only_opt) + status[0] = 1.0; + if (__oclc_unsafe_math_opt) + status[1] = 1.0; + if (__oclc_wavefrontsize64) + status[4] = 1.0; + if (__oclc_ISA_version) + status[5] = 1.0; + if (__oclc_ABI_version) + status[6] = 1.0; + + // Math functions to test AMDGPULibCalls Folding optimizations + // fold_sincos() + float x = 0.25; + status[7] = sin(x) + cos(x); + status[8] = cos(x) + sin(x); + + // fold_rootn() + float y = 725.0; + status[9] = rootn(y, 3); + status[10] = rootn(y, -1); + status[11] = rootn(y, -2); + + // fold_pow() + float z = 12.16; + status[12] = pow(z, (float)0.5); + status[13] = powr(y, (float)7.23); + + // printf() + printf("testy\n"); +} diff --git a/amd/comgr/test/source/double.hip b/amd/comgr/test/source/double.hip new file mode 100644 index 0000000000000..2c0aa20e30683 --- /dev/null +++ b/amd/comgr/test/source/double.hip @@ -0,0 +1,3 @@ +void doubles(int *j) { + *j = *j * 2; +} diff --git a/amd/comgr/test/source/include-macro.h b/amd/comgr/test/source/include-macro.h new file mode 100644 index 0000000000000..8523d58b330cc --- /dev/null +++ b/amd/comgr/test/source/include-macro.h @@ -0,0 +1 @@ +#define FOO 1 diff --git a/amd/comgr/test/source/include-nested.h b/amd/comgr/test/source/include-nested.h new file mode 100644 index 0000000000000..7482dc3071bba --- /dev/null +++ b/amd/comgr/test/source/include-nested.h @@ -0,0 +1,4 @@ +#define FOO 1 + +void kernel nested1(__global int *j); +void kernel nested2(__global int *j); diff --git a/amd/comgr/test/source/legacy/shared-v2.so b/amd/comgr/test/source/legacy/shared-v2.so new file mode 100755 index 0000000000000..629abb8f29ff4 Binary files /dev/null and b/amd/comgr/test/source/legacy/shared-v2.so differ diff --git a/amd/comgr/test/source/legacy/shared-v3.so b/amd/comgr/test/source/legacy/shared-v3.so new file mode 100755 index 0000000000000..da6d2781c6bad Binary files /dev/null and b/amd/comgr/test/source/legacy/shared-v3.so differ diff --git a/amd/comgr/test/source/legacy/shared12-v2.so b/amd/comgr/test/source/legacy/shared12-v2.so new file mode 100755 index 0000000000000..99162643153ee Binary files /dev/null and b/amd/comgr/test/source/legacy/shared12-v2.so differ diff --git a/amd/comgr/test/source/legacy/shared12-v3.so b/amd/comgr/test/source/legacy/shared12-v3.so new file mode 100755 index 0000000000000..7c4f9da00ebe5 Binary files /dev/null and b/amd/comgr/test/source/legacy/shared12-v3.so differ diff --git a/amd/comgr/test/source/legacy/shared14-v2.so b/amd/comgr/test/source/legacy/shared14-v2.so new file mode 100755 index 0000000000000..08c8592d7d2da Binary files /dev/null and b/amd/comgr/test/source/legacy/shared14-v2.so differ diff --git a/amd/comgr/test/source/legacy/shared14-v3.so b/amd/comgr/test/source/legacy/shared14-v3.so new file mode 100755 index 0000000000000..d7b50d2e516a6 Binary files /dev/null and b/amd/comgr/test/source/legacy/shared14-v3.so differ diff --git a/amd/comgr/test/source/legacy/shared23-v2.so b/amd/comgr/test/source/legacy/shared23-v2.so new file mode 100755 index 0000000000000..75be7105ceb47 Binary files /dev/null and b/amd/comgr/test/source/legacy/shared23-v2.so differ diff --git a/amd/comgr/test/source/legacy/shared23-v3.so b/amd/comgr/test/source/legacy/shared23-v3.so new file mode 100755 index 0000000000000..2227a06e264bb Binary files /dev/null and b/amd/comgr/test/source/legacy/shared23-v3.so differ diff --git a/amd/comgr/test/source/legacy/source1-v2.o b/amd/comgr/test/source/legacy/source1-v2.o new file mode 100644 index 0000000000000..34cabf54591b0 Binary files /dev/null and b/amd/comgr/test/source/legacy/source1-v2.o differ diff --git a/amd/comgr/test/source/legacy/source1-v2.s b/amd/comgr/test/source/legacy/source1-v2.s new file mode 100644 index 0000000000000..b8e9daecbed2e --- /dev/null +++ b/amd/comgr/test/source/legacy/source1-v2.s @@ -0,0 +1,163 @@ +; Empty Kernel test1_v2 code-object-v2 source + .text + .hsa_code_object_version 2,1 + .hsa_code_object_isa 8,0,3,"AMD","AMDGPU" + .protected test1_v2 ; -- Begin function test1_v2 + .globl test1_v2 + .p2align 8 + .type test1_v2,@function + .amdgpu_hsa_kernel test1_v2 +test1_v2: ; @test1_v2 +test1_v2$local: + .amd_kernel_code_t + amd_code_version_major = 1 + amd_code_version_minor = 2 + amd_machine_kind = 1 + amd_machine_version_major = 8 + amd_machine_version_minor = 0 + amd_machine_version_stepping = 3 + kernel_code_entry_byte_offset = 256 + kernel_code_prefetch_byte_size = 0 + granulated_workitem_vgpr_count = 0 + granulated_wavefront_sgpr_count = 4 + priority = 0 + float_mode = 192 + priv = 0 + enable_dx10_clamp = 1 + debug_mode = 0 + enable_ieee_mode = 1 + enable_wgp_mode = 0 + enable_mem_ordered = 0 + enable_fwd_progress = 0 + enable_sgpr_private_segment_wave_byte_offset = 0 + user_sgpr_count = 4 + enable_trap_handler = 0 + enable_sgpr_workgroup_id_x = 1 + enable_sgpr_workgroup_id_y = 0 + enable_sgpr_workgroup_id_z = 0 + enable_sgpr_workgroup_info = 0 + enable_vgpr_workitem_id = 0 + enable_exception_msb = 0 + granulated_lds_size = 0 + enable_exception = 0 + enable_sgpr_private_segment_buffer = 1 + enable_sgpr_dispatch_ptr = 0 + enable_sgpr_queue_ptr = 0 + enable_sgpr_kernarg_segment_ptr = 0 + enable_sgpr_dispatch_id = 0 + enable_sgpr_flat_scratch_init = 0 + enable_sgpr_private_segment_size = 0 + enable_sgpr_grid_workgroup_count_x = 0 + enable_sgpr_grid_workgroup_count_y = 0 + enable_sgpr_grid_workgroup_count_z = 0 + enable_wavefront_size32 = 0 + enable_ordered_append_gds = 0 + private_element_size = 1 + is_ptr64 = 1 + is_dynamic_callstack = 0 + is_debug_enabled = 0 + is_xnack_enabled = 0 + workitem_private_segment_byte_size = 0 + workgroup_group_segment_byte_size = 0 + gds_segment_byte_size = 0 + kernarg_segment_byte_size = 56 + workgroup_fbarrier_count = 0 + wavefront_sgpr_count = 34 + workitem_vgpr_count = 0 + reserved_vgpr_first = 0 + reserved_vgpr_count = 0 + reserved_sgpr_first = 0 + reserved_sgpr_count = 0 + debug_wavefront_private_segment_offset_sgpr = 0 + debug_private_segment_buffer_sgpr = 0 + kernarg_segment_alignment = 4 + group_segment_alignment = 4 + private_segment_alignment = 4 + wavefront_size = 6 + call_convention = -1 + runtime_loader_kernel_symbol = 0 + .end_amd_kernel_code_t +; %bb.0: ; %entry + s_mov_b32 s33, 0 + s_endpgm +.Lfunc_end0: + .size test1_v2, .Lfunc_end0-test1_v2 + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 8 +; NumSgprs: 34 +; NumVgprs: 0 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 192 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 4 +; VGPRBlocks: 0 +; NumSGPRsForWavesPerEU: 34 +; NumVGPRsForWavesPerEU: 1 +; Occupancy: 10 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 4 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .ident "clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20629ca949cddde9f7e41a4b9e8539a970615feb)" + .section ".note.GNU-stack" + .addrsig + .amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx803" + .amd_amdgpu_hsa_metadata +--- +Version: [ 1, 0 ] +Kernels: + - Name: test1_v2 + SymbolName: 'test1_v2@kd' + Language: OpenCL C + LanguageVersion: [ 2, 0 ] + Args: + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetX + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetY + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetZ + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenNone + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenNone + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenNone + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenMultiGridSyncArg + ValueType: I8 + AddrSpaceQual: Global + CodeProps: + KernargSegmentSize: 56 + GroupSegmentFixedSize: 0 + PrivateSegmentFixedSize: 0 + KernargSegmentAlign: 4 + WavefrontSize: 64 + NumSGPRs: 34 + MaxFlatWorkGroupSize: 256 +... + + .end_amd_amdgpu_hsa_metadata diff --git a/amd/comgr/test/source/legacy/source1-v3.o b/amd/comgr/test/source/legacy/source1-v3.o new file mode 100644 index 0000000000000..fb3e22551e0a5 Binary files /dev/null and b/amd/comgr/test/source/legacy/source1-v3.o differ diff --git a/amd/comgr/test/source/legacy/source1-v3.s b/amd/comgr/test/source/legacy/source1-v3.s new file mode 100644 index 0000000000000..ba1d97c23403a --- /dev/null +++ b/amd/comgr/test/source/legacy/source1-v3.s @@ -0,0 +1,135 @@ +; Empty Kernel test1_v3 code-object-v3 source + .text + .amdgcn_target "amdgcn-amd-amdhsa--gfx803" + .protected test1_v3 ; -- Begin function test1_v3 + .globl test1_v3 + .p2align 8 + .type test1_v3,@function +test1_v3: ; @test1_v3 +test1_v3$local: +; %bb.0: ; %entry + s_mov_b32 s33, 0 + s_endpgm + .section .rodata,#alloc + .p2align 6 + .amdhsa_kernel test1_v3 + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_user_sgpr_private_segment_buffer 1 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 0 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_flat_scratch_init 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_system_sgpr_private_segment_wavefront_offset 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 1 + .amdhsa_next_free_sgpr 34 + .amdhsa_reserve_vcc 0 + .amdhsa_reserve_flat_scratch 0 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 0 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .text +.Lfunc_end0: + .size test1_v3, .Lfunc_end0-test1_v3 + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 8 +; NumSgprs: 34 +; NumVgprs: 0 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 192 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 4 +; VGPRBlocks: 0 +; NumSGPRsForWavesPerEU: 34 +; NumVGPRsForWavesPerEU: 1 +; Occupancy: 10 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 4 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .ident "clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20629ca949cddde9f7e41a4b9e8539a970615feb)" + .section ".note.GNU-stack" + .addrsig + .amdgpu_metadata +--- +amdhsa.kernels: + - .args: + - .offset: 0 + .size: 8 + .value_kind: hidden_global_offset_x + .value_type: i64 + - .offset: 8 + .size: 8 + .value_kind: hidden_global_offset_y + .value_type: i64 + - .offset: 16 + .size: 8 + .value_kind: hidden_global_offset_z + .value_type: i64 + - .address_space: global + .offset: 24 + .size: 8 + .value_kind: hidden_none + .value_type: i8 + - .address_space: global + .offset: 32 + .size: 8 + .value_kind: hidden_none + .value_type: i8 + - .address_space: global + .offset: 40 + .size: 8 + .value_kind: hidden_none + .value_type: i8 + - .address_space: global + .offset: 48 + .size: 8 + .value_kind: hidden_multigrid_sync_arg + .value_type: i8 + .group_segment_fixed_size: 0 + .kernarg_segment_align: 4 + .kernarg_segment_size: 56 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 256 + .name: test1_v3 + .private_segment_fixed_size: 0 + .sgpr_count: 34 + .sgpr_spill_count: 0 + .symbol: test1_v3.kd + .vgpr_count: 0 + .vgpr_spill_count: 0 + .wavefront_size: 64 +amdhsa.version: + - 1 + - 0 +... + + .end_amdgpu_metadata diff --git a/amd/comgr/test/source/legacy/source2-v2.o b/amd/comgr/test/source/legacy/source2-v2.o new file mode 100644 index 0000000000000..14ba47579d698 Binary files /dev/null and b/amd/comgr/test/source/legacy/source2-v2.o differ diff --git a/amd/comgr/test/source/legacy/source2-v2.s b/amd/comgr/test/source/legacy/source2-v2.s new file mode 100644 index 0000000000000..4dc3e692add0a --- /dev/null +++ b/amd/comgr/test/source/legacy/source2-v2.s @@ -0,0 +1,187 @@ +; Kernel test2_v2 wth printf, code-object-v2 source + .text + .hsa_code_object_version 2,1 + .hsa_code_object_isa 8,0,3,"AMD","AMDGPU" + .protected test2_v2 ; -- Begin function test2_v2 + .globl test2_v2 + .p2align 8 + .type test2_v2,@function + .amdgpu_hsa_kernel test2_v2 +test2_v2: ; @test2_v2 +test2_v2$local: + .amd_kernel_code_t + amd_code_version_major = 1 + amd_code_version_minor = 2 + amd_machine_kind = 1 + amd_machine_version_major = 8 + amd_machine_version_minor = 0 + amd_machine_version_stepping = 3 + kernel_code_entry_byte_offset = 256 + kernel_code_prefetch_byte_size = 0 + granulated_workitem_vgpr_count = 5 + granulated_wavefront_sgpr_count = 5 + priority = 0 + float_mode = 192 + priv = 0 + enable_dx10_clamp = 1 + debug_mode = 0 + enable_ieee_mode = 1 + enable_wgp_mode = 0 + enable_mem_ordered = 0 + enable_fwd_progress = 0 + enable_sgpr_private_segment_wave_byte_offset = 1 + user_sgpr_count = 6 + enable_trap_handler = 0 + enable_sgpr_workgroup_id_x = 1 + enable_sgpr_workgroup_id_y = 0 + enable_sgpr_workgroup_id_z = 0 + enable_sgpr_workgroup_info = 0 + enable_vgpr_workitem_id = 0 + enable_exception_msb = 0 + granulated_lds_size = 0 + enable_exception = 0 + enable_sgpr_private_segment_buffer = 1 + enable_sgpr_dispatch_ptr = 0 + enable_sgpr_queue_ptr = 0 + enable_sgpr_kernarg_segment_ptr = 0 + enable_sgpr_dispatch_id = 0 + enable_sgpr_flat_scratch_init = 1 + enable_sgpr_private_segment_size = 0 + enable_sgpr_grid_workgroup_count_x = 0 + enable_sgpr_grid_workgroup_count_y = 0 + enable_sgpr_grid_workgroup_count_z = 0 + enable_wavefront_size32 = 0 + enable_ordered_append_gds = 0 + private_element_size = 1 + is_ptr64 = 1 + is_dynamic_callstack = 1 + is_debug_enabled = 0 + is_xnack_enabled = 0 + workitem_private_segment_byte_size = 16384 + workgroup_group_segment_byte_size = 0 + gds_segment_byte_size = 0 + kernarg_segment_byte_size = 56 + workgroup_fbarrier_count = 0 + wavefront_sgpr_count = 48 + workitem_vgpr_count = 24 + reserved_vgpr_first = 0 + reserved_vgpr_count = 0 + reserved_sgpr_first = 0 + reserved_sgpr_count = 0 + debug_wavefront_private_segment_offset_sgpr = 0 + debug_private_segment_buffer_sgpr = 0 + kernarg_segment_alignment = 4 + group_segment_alignment = 4 + private_segment_alignment = 4 + wavefront_size = 6 + call_convention = -1 + runtime_loader_kernel_symbol = 0 + .end_amd_kernel_code_t +; %bb.0: ; %entry + s_add_u32 s4, s4, s7 + s_lshr_b32 flat_scratch_hi, s4, 8 + s_add_u32 s0, s0, s7 + s_addc_u32 s1, s1, 0 + s_mov_b32 flat_scratch_lo, s5 + s_getpc_b64 s[4:5] + s_add_u32 s4, s4, __printf_alloc@gotpcrel32@lo+4 + s_addc_u32 s5, s5, __printf_alloc@gotpcrel32@hi+4 + s_load_dwordx2 s[4:5], s[4:5], 0x0 + v_mov_b32_e32 v0, 4 + s_mov_b32 s32, 0 + s_mov_b32 s33, 0 + s_waitcnt lgkmcnt(0) + s_swappc_b64 s[30:31], s[4:5] + v_cmp_ne_u64_e32 vcc, 0, v[0:1] + s_and_saveexec_b64 s[4:5], vcc + s_cbranch_execz BB0_2 +; %bb.1: + v_mov_b32_e32 v2, 1 + flat_store_dword v[0:1], v2 +BB0_2: + s_endpgm +.Lfunc_end0: + .size test2_v2, .Lfunc_end0-test2_v2 + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 96 +; NumSgprs: 48 +; NumVgprs: 24 +; ScratchSize: 16384 +; MemoryBound: 0 +; FloatMode: 192 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 5 +; VGPRBlocks: 5 +; NumSGPRsForWavesPerEU: 48 +; NumVGPRsForWavesPerEU: 24 +; Occupancy: 10 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .ident "clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20629ca949cddde9f7e41a4b9e8539a970615feb)" + .section ".note.GNU-stack" + .addrsig + .amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx803" + .amd_amdgpu_hsa_metadata +--- +Version: [ 1, 0 ] +Printf: + - '1:0:foo' +Kernels: + - Name: test2_v2 + SymbolName: 'test2_v2@kd' + Language: OpenCL C + LanguageVersion: [ 2, 0 ] + Args: + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetX + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetY + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetZ + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenPrintfBuffer + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenNone + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenNone + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenMultiGridSyncArg + ValueType: I8 + AddrSpaceQual: Global + CodeProps: + KernargSegmentSize: 56 + GroupSegmentFixedSize: 0 + PrivateSegmentFixedSize: 16384 + KernargSegmentAlign: 4 + WavefrontSize: 64 + NumSGPRs: 48 + NumVGPRs: 24 + MaxFlatWorkGroupSize: 256 + IsDynamicCallStack: true +... + + .end_amd_amdgpu_hsa_metadata diff --git a/amd/comgr/test/source/legacy/source2-v3.o b/amd/comgr/test/source/legacy/source2-v3.o new file mode 100644 index 0000000000000..0d9302fb4ee6b Binary files /dev/null and b/amd/comgr/test/source/legacy/source2-v3.o differ diff --git a/amd/comgr/test/source/legacy/source2-v3.s b/amd/comgr/test/source/legacy/source2-v3.s new file mode 100644 index 0000000000000..aed7911e25767 --- /dev/null +++ b/amd/comgr/test/source/legacy/source2-v3.s @@ -0,0 +1,155 @@ +; Kernel test2_v3 wth printf, code-object-v3 source + .text + .amdgcn_target "amdgcn-amd-amdhsa--gfx803" + .protected test2_v3 ; -- Begin function test2_v3 + .globl test2_v3 + .p2align 8 + .type test2_v3,@function +test2_v3: ; @test2_v3 +test2_v3$local: +; %bb.0: ; %entry + s_add_u32 s4, s4, s7 + s_lshr_b32 flat_scratch_hi, s4, 8 + s_add_u32 s0, s0, s7 + s_addc_u32 s1, s1, 0 + s_mov_b32 flat_scratch_lo, s5 + s_getpc_b64 s[4:5] + s_add_u32 s4, s4, __printf_alloc@gotpcrel32@lo+4 + s_addc_u32 s5, s5, __printf_alloc@gotpcrel32@hi+4 + s_load_dwordx2 s[4:5], s[4:5], 0x0 + v_mov_b32_e32 v0, 4 + s_mov_b32 s32, 0 + s_mov_b32 s33, 0 + s_waitcnt lgkmcnt(0) + s_swappc_b64 s[30:31], s[4:5] + v_cmp_ne_u64_e32 vcc, 0, v[0:1] + s_and_saveexec_b64 s[4:5], vcc + s_cbranch_execz BB0_2 +; %bb.1: + v_mov_b32_e32 v2, 1 + flat_store_dword v[0:1], v2 +BB0_2: + s_endpgm + .section .rodata,#alloc + .p2align 6 + .amdhsa_kernel test2_v3 + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 16384 + .amdhsa_user_sgpr_private_segment_buffer 1 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 0 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_flat_scratch_init 1 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_system_sgpr_private_segment_wavefront_offset 1 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 24 + .amdhsa_next_free_sgpr 42 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 0 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .text +.Lfunc_end0: + .size test2_v3, .Lfunc_end0-test2_v3 + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 96 +; NumSgprs: 48 +; NumVgprs: 24 +; ScratchSize: 16384 +; MemoryBound: 0 +; FloatMode: 192 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 5 +; VGPRBlocks: 5 +; NumSGPRsForWavesPerEU: 48 +; NumVGPRsForWavesPerEU: 24 +; Occupancy: 10 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .ident "clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20629ca949cddde9f7e41a4b9e8539a970615feb)" + .section ".note.GNU-stack" + .addrsig + .amdgpu_metadata +--- +amdhsa.kernels: + - .args: + - .offset: 0 + .size: 8 + .value_kind: hidden_global_offset_x + .value_type: i64 + - .offset: 8 + .size: 8 + .value_kind: hidden_global_offset_y + .value_type: i64 + - .offset: 16 + .size: 8 + .value_kind: hidden_global_offset_z + .value_type: i64 + - .address_space: global + .offset: 24 + .size: 8 + .value_kind: hidden_printf_buffer + .value_type: i8 + - .address_space: global + .offset: 32 + .size: 8 + .value_kind: hidden_none + .value_type: i8 + - .address_space: global + .offset: 40 + .size: 8 + .value_kind: hidden_none + .value_type: i8 + - .address_space: global + .offset: 48 + .size: 8 + .value_kind: hidden_multigrid_sync_arg + .value_type: i8 + .group_segment_fixed_size: 0 + .kernarg_segment_align: 4 + .kernarg_segment_size: 56 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 256 + .name: test2_v3 + .private_segment_fixed_size: 16384 + .sgpr_count: 48 + .sgpr_spill_count: 0 + .symbol: test2_v3.kd + .vgpr_count: 24 + .vgpr_spill_count: 0 + .wavefront_size: 64 +amdhsa.printf: + - '1:0:foo' +amdhsa.version: + - 1 + - 0 +... + + .end_amdgpu_metadata diff --git a/amd/comgr/test/source/legacy/source3-v2.o b/amd/comgr/test/source/legacy/source3-v2.o new file mode 100644 index 0000000000000..cb8c7a2414d3d Binary files /dev/null and b/amd/comgr/test/source/legacy/source3-v2.o differ diff --git a/amd/comgr/test/source/legacy/source3-v2.s b/amd/comgr/test/source/legacy/source3-v2.s new file mode 100644 index 0000000000000..8c66603a41cf0 --- /dev/null +++ b/amd/comgr/test/source/legacy/source3-v2.s @@ -0,0 +1,187 @@ +; Kernel test3_v2 wth printf, code-object-v2 source + .text + .hsa_code_object_version 2,1 + .hsa_code_object_isa 8,0,3,"AMD","AMDGPU" + .protected test3_v2 ; -- Begin function test3_v2 + .globl test3_v2 + .p2align 8 + .type test3_v2,@function + .amdgpu_hsa_kernel test3_v2 +test3_v2: ; @test3_v2 +test3_v2$local: + .amd_kernel_code_t + amd_code_version_major = 1 + amd_code_version_minor = 2 + amd_machine_kind = 1 + amd_machine_version_major = 8 + amd_machine_version_minor = 0 + amd_machine_version_stepping = 3 + kernel_code_entry_byte_offset = 256 + kernel_code_prefetch_byte_size = 0 + granulated_workitem_vgpr_count = 5 + granulated_wavefront_sgpr_count = 5 + priority = 0 + float_mode = 192 + priv = 0 + enable_dx10_clamp = 1 + debug_mode = 0 + enable_ieee_mode = 1 + enable_wgp_mode = 0 + enable_mem_ordered = 0 + enable_fwd_progress = 0 + enable_sgpr_private_segment_wave_byte_offset = 1 + user_sgpr_count = 6 + enable_trap_handler = 0 + enable_sgpr_workgroup_id_x = 1 + enable_sgpr_workgroup_id_y = 0 + enable_sgpr_workgroup_id_z = 0 + enable_sgpr_workgroup_info = 0 + enable_vgpr_workitem_id = 0 + enable_exception_msb = 0 + granulated_lds_size = 0 + enable_exception = 0 + enable_sgpr_private_segment_buffer = 1 + enable_sgpr_dispatch_ptr = 0 + enable_sgpr_queue_ptr = 0 + enable_sgpr_kernarg_segment_ptr = 0 + enable_sgpr_dispatch_id = 0 + enable_sgpr_flat_scratch_init = 1 + enable_sgpr_private_segment_size = 0 + enable_sgpr_grid_workgroup_count_x = 0 + enable_sgpr_grid_workgroup_count_y = 0 + enable_sgpr_grid_workgroup_count_z = 0 + enable_wavefront_size32 = 0 + enable_ordered_append_gds = 0 + private_element_size = 1 + is_ptr64 = 1 + is_dynamic_callstack = 1 + is_debug_enabled = 0 + is_xnack_enabled = 0 + workitem_private_segment_byte_size = 16384 + workgroup_group_segment_byte_size = 0 + gds_segment_byte_size = 0 + kernarg_segment_byte_size = 56 + workgroup_fbarrier_count = 0 + wavefront_sgpr_count = 48 + workitem_vgpr_count = 24 + reserved_vgpr_first = 0 + reserved_vgpr_count = 0 + reserved_sgpr_first = 0 + reserved_sgpr_count = 0 + debug_wavefront_private_segment_offset_sgpr = 0 + debug_private_segment_buffer_sgpr = 0 + kernarg_segment_alignment = 4 + group_segment_alignment = 4 + private_segment_alignment = 4 + wavefront_size = 6 + call_convention = -1 + runtime_loader_kernel_symbol = 0 + .end_amd_kernel_code_t +; %bb.0: ; %entry + s_add_u32 s4, s4, s7 + s_lshr_b32 flat_scratch_hi, s4, 8 + s_add_u32 s0, s0, s7 + s_addc_u32 s1, s1, 0 + s_mov_b32 flat_scratch_lo, s5 + s_getpc_b64 s[4:5] + s_add_u32 s4, s4, __printf_alloc@gotpcrel32@lo+4 + s_addc_u32 s5, s5, __printf_alloc@gotpcrel32@hi+4 + s_load_dwordx2 s[4:5], s[4:5], 0x0 + v_mov_b32_e32 v0, 4 + s_mov_b32 s32, 0 + s_mov_b32 s33, 0 + s_waitcnt lgkmcnt(0) + s_swappc_b64 s[30:31], s[4:5] + v_cmp_ne_u64_e32 vcc, 0, v[0:1] + s_and_saveexec_b64 s[4:5], vcc + s_cbranch_execz BB0_2 +; %bb.1: + v_mov_b32_e32 v2, 1 + flat_store_dword v[0:1], v2 +BB0_2: + s_endpgm +.Lfunc_end0: + .size test3_v2, .Lfunc_end0-test3_v2 + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 96 +; NumSgprs: 48 +; NumVgprs: 24 +; ScratchSize: 16384 +; MemoryBound: 0 +; FloatMode: 192 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 5 +; VGPRBlocks: 5 +; NumSGPRsForWavesPerEU: 48 +; NumVGPRsForWavesPerEU: 24 +; Occupancy: 10 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .ident "clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20629ca949cddde9f7e41a4b9e8539a970615feb)" + .section ".note.GNU-stack" + .addrsig + .amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx803" + .amd_amdgpu_hsa_metadata +--- +Version: [ 1, 0 ] +Printf: + - '1:0:foo' +Kernels: + - Name: test3_v2 + SymbolName: 'test3_v2@kd' + Language: OpenCL C + LanguageVersion: [ 2, 0 ] + Args: + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetX + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetY + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetZ + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenPrintfBuffer + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenNone + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenNone + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenMultiGridSyncArg + ValueType: I8 + AddrSpaceQual: Global + CodeProps: + KernargSegmentSize: 56 + GroupSegmentFixedSize: 0 + PrivateSegmentFixedSize: 16384 + KernargSegmentAlign: 4 + WavefrontSize: 64 + NumSGPRs: 48 + NumVGPRs: 24 + MaxFlatWorkGroupSize: 256 + IsDynamicCallStack: true +... + + .end_amd_amdgpu_hsa_metadata diff --git a/amd/comgr/test/source/legacy/source3-v3.o b/amd/comgr/test/source/legacy/source3-v3.o new file mode 100644 index 0000000000000..76999923b3b5d Binary files /dev/null and b/amd/comgr/test/source/legacy/source3-v3.o differ diff --git a/amd/comgr/test/source/legacy/source3-v3.s b/amd/comgr/test/source/legacy/source3-v3.s new file mode 100644 index 0000000000000..b3316c6b28912 --- /dev/null +++ b/amd/comgr/test/source/legacy/source3-v3.s @@ -0,0 +1,155 @@ +; Kernel test3_v3 wth printf, code-object-v3 source + .text + .amdgcn_target "amdgcn-amd-amdhsa--gfx803" + .protected test3_v3 ; -- Begin function test3_v3 + .globl test3_v3 + .p2align 8 + .type test3_v3,@function +test3_v3: ; @test3_v3 +test3_v3$local: +; %bb.0: ; %entry + s_add_u32 s4, s4, s7 + s_lshr_b32 flat_scratch_hi, s4, 8 + s_add_u32 s0, s0, s7 + s_addc_u32 s1, s1, 0 + s_mov_b32 flat_scratch_lo, s5 + s_getpc_b64 s[4:5] + s_add_u32 s4, s4, __printf_alloc@gotpcrel32@lo+4 + s_addc_u32 s5, s5, __printf_alloc@gotpcrel32@hi+4 + s_load_dwordx2 s[4:5], s[4:5], 0x0 + v_mov_b32_e32 v0, 4 + s_mov_b32 s32, 0 + s_mov_b32 s33, 0 + s_waitcnt lgkmcnt(0) + s_swappc_b64 s[30:31], s[4:5] + v_cmp_ne_u64_e32 vcc, 0, v[0:1] + s_and_saveexec_b64 s[4:5], vcc + s_cbranch_execz BB0_2 +; %bb.1: + v_mov_b32_e32 v2, 1 + flat_store_dword v[0:1], v2 +BB0_2: + s_endpgm + .section .rodata,#alloc + .p2align 6 + .amdhsa_kernel test3_v3 + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 16384 + .amdhsa_user_sgpr_private_segment_buffer 1 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 0 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_flat_scratch_init 1 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_system_sgpr_private_segment_wavefront_offset 1 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 24 + .amdhsa_next_free_sgpr 42 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 0 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .text +.Lfunc_end0: + .size test3_v3, .Lfunc_end0-test3_v3 + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 96 +; NumSgprs: 48 +; NumVgprs: 24 +; ScratchSize: 16384 +; MemoryBound: 0 +; FloatMode: 192 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 5 +; VGPRBlocks: 5 +; NumSGPRsForWavesPerEU: 48 +; NumVGPRsForWavesPerEU: 24 +; Occupancy: 10 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .ident "clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20629ca949cddde9f7e41a4b9e8539a970615feb)" + .section ".note.GNU-stack" + .addrsig + .amdgpu_metadata +--- +amdhsa.kernels: + - .args: + - .offset: 0 + .size: 8 + .value_kind: hidden_global_offset_x + .value_type: i64 + - .offset: 8 + .size: 8 + .value_kind: hidden_global_offset_y + .value_type: i64 + - .offset: 16 + .size: 8 + .value_kind: hidden_global_offset_z + .value_type: i64 + - .address_space: global + .offset: 24 + .size: 8 + .value_kind: hidden_printf_buffer + .value_type: i8 + - .address_space: global + .offset: 32 + .size: 8 + .value_kind: hidden_none + .value_type: i8 + - .address_space: global + .offset: 40 + .size: 8 + .value_kind: hidden_none + .value_type: i8 + - .address_space: global + .offset: 48 + .size: 8 + .value_kind: hidden_multigrid_sync_arg + .value_type: i8 + .group_segment_fixed_size: 0 + .kernarg_segment_align: 4 + .kernarg_segment_size: 56 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 256 + .name: test3_v3 + .private_segment_fixed_size: 16384 + .sgpr_count: 48 + .sgpr_spill_count: 0 + .symbol: test3_v3.kd + .vgpr_count: 24 + .vgpr_spill_count: 0 + .wavefront_size: 64 +amdhsa.printf: + - '1:0:foo' +amdhsa.version: + - 1 + - 0 +... + + .end_amdgpu_metadata diff --git a/amd/comgr/test/source/legacy/source4-v1.s b/amd/comgr/test/source/legacy/source4-v1.s new file mode 100644 index 0000000000000..2991147ed2979 --- /dev/null +++ b/amd/comgr/test/source/legacy/source4-v1.s @@ -0,0 +1,155 @@ +; Kernel test4_v3 wth printf, version manually changed, code-object-v3 source + .text + .amdgcn_target "amdgcn-amd-amdhsa--gfx803" + .protected test4_v3 ; -- Begin function test4_v3 + .globl test4_v3 + .p2align 8 + .type test4_v3,@function +test4_v3: ; @test4_v3 +test4_v3$local: +; %bb.0: ; %entry + s_add_u32 s4, s4, s7 + s_lshr_b32 flat_scratch_hi, s4, 8 + s_add_u32 s0, s0, s7 + s_addc_u32 s1, s1, 0 + s_mov_b32 flat_scratch_lo, s5 + s_getpc_b64 s[4:5] + s_add_u32 s4, s4, __printf_alloc@gotpcrel32@lo+4 + s_addc_u32 s5, s5, __printf_alloc@gotpcrel32@hi+4 + s_load_dwordx2 s[4:5], s[4:5], 0x0 + v_mov_b32_e32 v0, 4 + s_mov_b32 s32, 0 + s_mov_b32 s33, 0 + s_waitcnt lgkmcnt(0) + s_swappc_b64 s[30:31], s[4:5] + v_cmp_ne_u64_e32 vcc, 0, v[0:1] + s_and_saveexec_b64 s[4:5], vcc + s_cbranch_execz BB0_2 +; %bb.1: + v_mov_b32_e32 v2, 1 + flat_store_dword v[0:1], v2 +BB0_2: + s_endpgm + .section .rodata,#alloc + .p2align 6 + .amdhsa_kernel test4_v3 + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 16384 + .amdhsa_user_sgpr_private_segment_buffer 1 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 0 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_flat_scratch_init 1 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_system_sgpr_private_segment_wavefront_offset 1 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 24 + .amdhsa_next_free_sgpr 42 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 0 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .text +.Lfunc_end0: + .size test4_v3, .Lfunc_end0-test4_v3 + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 96 +; NumSgprs: 48 +; NumVgprs: 24 +; ScratchSize: 16384 +; MemoryBound: 0 +; FloatMode: 192 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 5 +; VGPRBlocks: 5 +; NumSGPRsForWavesPerEU: 48 +; NumVGPRsForWavesPerEU: 24 +; Occupancy: 10 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .ident "clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20629ca949cddde9f7e41a4b9e8539a970615feb)" + .section ".note.GNU-stack" + .addrsig + .amdgpu_metadata +--- +amdhsa.kernels: + - .args: + - .offset: 0 + .size: 8 + .value_kind: hidden_global_offset_x + .value_type: i64 + - .offset: 8 + .size: 8 + .value_kind: hidden_global_offset_y + .value_type: i64 + - .offset: 16 + .size: 8 + .value_kind: hidden_global_offset_z + .value_type: i64 + - .address_space: global + .offset: 24 + .size: 8 + .value_kind: hidden_printf_buffer + .value_type: i8 + - .address_space: global + .offset: 32 + .size: 8 + .value_kind: hidden_none + .value_type: i8 + - .address_space: global + .offset: 40 + .size: 8 + .value_kind: hidden_none + .value_type: i8 + - .address_space: global + .offset: 48 + .size: 8 + .value_kind: hidden_multigrid_sync_arg + .value_type: i8 + .group_segment_fixed_size: 0 + .kernarg_segment_align: 4 + .kernarg_segment_size: 56 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 256 + .name: test4_v3 + .private_segment_fixed_size: 16384 + .sgpr_count: 48 + .sgpr_spill_count: 0 + .symbol: test4_v3.kd + .vgpr_count: 24 + .vgpr_spill_count: 0 + .wavefront_size: 64 +amdhsa.printf: + - '1:0:foo' +amdhsa.version: + - 2 + - 0 +... + + .end_amdgpu_metadata diff --git a/amd/comgr/test/source/legacy/source4-v2.o b/amd/comgr/test/source/legacy/source4-v2.o new file mode 100644 index 0000000000000..ce71ac2d0466d Binary files /dev/null and b/amd/comgr/test/source/legacy/source4-v2.o differ diff --git a/amd/comgr/test/source/legacy/source4-v2.s b/amd/comgr/test/source/legacy/source4-v2.s new file mode 100644 index 0000000000000..f67e0566bddf6 --- /dev/null +++ b/amd/comgr/test/source/legacy/source4-v2.s @@ -0,0 +1,187 @@ +; Kernel test4_v2 wth printf, version manually changed, code-object-v2 source + .text + .hsa_code_object_version 2,1 + .hsa_code_object_isa 8,0,3,"AMD","AMDGPU" + .protected test4_v2 ; -- Begin function test4_v2 + .globl test4_v2 + .p2align 8 + .type test4_v2,@function + .amdgpu_hsa_kernel test4_v2 +test4_v2: ; @test4_v2 +test4_v2$local: + .amd_kernel_code_t + amd_code_version_major = 1 + amd_code_version_minor = 2 + amd_machine_kind = 1 + amd_machine_version_major = 8 + amd_machine_version_minor = 0 + amd_machine_version_stepping = 3 + kernel_code_entry_byte_offset = 256 + kernel_code_prefetch_byte_size = 0 + granulated_workitem_vgpr_count = 5 + granulated_wavefront_sgpr_count = 5 + priority = 0 + float_mode = 192 + priv = 0 + enable_dx10_clamp = 1 + debug_mode = 0 + enable_ieee_mode = 1 + enable_wgp_mode = 0 + enable_mem_ordered = 0 + enable_fwd_progress = 0 + enable_sgpr_private_segment_wave_byte_offset = 1 + user_sgpr_count = 6 + enable_trap_handler = 0 + enable_sgpr_workgroup_id_x = 1 + enable_sgpr_workgroup_id_y = 0 + enable_sgpr_workgroup_id_z = 0 + enable_sgpr_workgroup_info = 0 + enable_vgpr_workitem_id = 0 + enable_exception_msb = 0 + granulated_lds_size = 0 + enable_exception = 0 + enable_sgpr_private_segment_buffer = 1 + enable_sgpr_dispatch_ptr = 0 + enable_sgpr_queue_ptr = 0 + enable_sgpr_kernarg_segment_ptr = 0 + enable_sgpr_dispatch_id = 0 + enable_sgpr_flat_scratch_init = 1 + enable_sgpr_private_segment_size = 0 + enable_sgpr_grid_workgroup_count_x = 0 + enable_sgpr_grid_workgroup_count_y = 0 + enable_sgpr_grid_workgroup_count_z = 0 + enable_wavefront_size32 = 0 + enable_ordered_append_gds = 0 + private_element_size = 1 + is_ptr64 = 1 + is_dynamic_callstack = 1 + is_debug_enabled = 0 + is_xnack_enabled = 0 + workitem_private_segment_byte_size = 16384 + workgroup_group_segment_byte_size = 0 + gds_segment_byte_size = 0 + kernarg_segment_byte_size = 56 + workgroup_fbarrier_count = 0 + wavefront_sgpr_count = 48 + workitem_vgpr_count = 24 + reserved_vgpr_first = 0 + reserved_vgpr_count = 0 + reserved_sgpr_first = 0 + reserved_sgpr_count = 0 + debug_wavefront_private_segment_offset_sgpr = 0 + debug_private_segment_buffer_sgpr = 0 + kernarg_segment_alignment = 4 + group_segment_alignment = 4 + private_segment_alignment = 4 + wavefront_size = 6 + call_convention = -1 + runtime_loader_kernel_symbol = 0 + .end_amd_kernel_code_t +; %bb.0: ; %entry + s_add_u32 s4, s4, s7 + s_lshr_b32 flat_scratch_hi, s4, 8 + s_add_u32 s0, s0, s7 + s_addc_u32 s1, s1, 0 + s_mov_b32 flat_scratch_lo, s5 + s_getpc_b64 s[4:5] + s_add_u32 s4, s4, __printf_alloc@gotpcrel32@lo+4 + s_addc_u32 s5, s5, __printf_alloc@gotpcrel32@hi+4 + s_load_dwordx2 s[4:5], s[4:5], 0x0 + v_mov_b32_e32 v0, 4 + s_mov_b32 s32, 0 + s_mov_b32 s33, 0 + s_waitcnt lgkmcnt(0) + s_swappc_b64 s[30:31], s[4:5] + v_cmp_ne_u64_e32 vcc, 0, v[0:1] + s_and_saveexec_b64 s[4:5], vcc + s_cbranch_execz BB0_2 +; %bb.1: + v_mov_b32_e32 v2, 1 + flat_store_dword v[0:1], v2 +BB0_2: + s_endpgm +.Lfunc_end0: + .size test4_v2, .Lfunc_end0-test4_v2 + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 96 +; NumSgprs: 48 +; NumVgprs: 24 +; ScratchSize: 16384 +; MemoryBound: 0 +; FloatMode: 192 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 5 +; VGPRBlocks: 5 +; NumSGPRsForWavesPerEU: 48 +; NumVGPRsForWavesPerEU: 24 +; Occupancy: 10 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .ident "clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20629ca949cddde9f7e41a4b9e8539a970615feb)" + .section ".note.GNU-stack" + .addrsig + .amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx803" + .amd_amdgpu_hsa_metadata +--- +Version: [ 2, 0 ] +Printf: + - '1:0:foo' +Kernels: + - Name: test4_v2 + SymbolName: 'test4_v2@kd' + Language: OpenCL C + LanguageVersion: [ 2, 0 ] + Args: + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetX + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetY + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenGlobalOffsetZ + ValueType: I64 + - Size: 8 + Align: 8 + ValueKind: HiddenPrintfBuffer + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenNone + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenNone + ValueType: I8 + AddrSpaceQual: Global + - Size: 8 + Align: 8 + ValueKind: HiddenMultiGridSyncArg + ValueType: I8 + AddrSpaceQual: Global + CodeProps: + KernargSegmentSize: 56 + GroupSegmentFixedSize: 0 + PrivateSegmentFixedSize: 16384 + KernargSegmentAlign: 4 + WavefrontSize: 64 + NumSGPRs: 48 + NumVGPRs: 24 + MaxFlatWorkGroupSize: 256 + IsDynamicCallStack: true +... + + .end_amd_amdgpu_hsa_metadata diff --git a/amd/comgr/test/source/legacy/source4-v3.o b/amd/comgr/test/source/legacy/source4-v3.o new file mode 100644 index 0000000000000..9bb64800fe536 Binary files /dev/null and b/amd/comgr/test/source/legacy/source4-v3.o differ diff --git a/amd/comgr/test/source/linking/empty.cl b/amd/comgr/test/source/linking/empty.cl new file mode 100644 index 0000000000000..85e6cd8c3909a --- /dev/null +++ b/amd/comgr/test/source/linking/empty.cl @@ -0,0 +1 @@ +void foo() {} diff --git a/amd/comgr/test/source/linking/kernel0.cl b/amd/comgr/test/source/linking/kernel0.cl new file mode 100644 index 0000000000000..5feef42f2c997 --- /dev/null +++ b/amd/comgr/test/source/linking/kernel0.cl @@ -0,0 +1 @@ +void kernel kernel0(__global int *j) { *j += 2; } diff --git a/amd/comgr/test/source/linking/kernel1.cl b/amd/comgr/test/source/linking/kernel1.cl new file mode 100644 index 0000000000000..5dbb78c1caf8b --- /dev/null +++ b/amd/comgr/test/source/linking/kernel1.cl @@ -0,0 +1 @@ +void kernel kernel1(__global int *j) { *j += 2; } diff --git a/amd/comgr/test/source/multiple-note-records-one-kernel.s b/amd/comgr/test/source/multiple-note-records-one-kernel.s new file mode 100644 index 0000000000000..48ba0e5a1683e --- /dev/null +++ b/amd/comgr/test/source/multiple-note-records-one-kernel.s @@ -0,0 +1,212 @@ + .text + .amdgcn_target "amdgcn-amd-amdhsa--gfx1030" + .protected _Z3fooPtS_ ; -- Begin function _Z3fooPtS_ + .globl _Z3fooPtS_ + .p2align 8 + .type _Z3fooPtS_,@function +_Z3fooPtS_: ; @_Z3fooPtS_ +; %bb.0: + s_clause 0x1 + s_load_dword s7, s[4:5], 0x1c + s_load_dwordx4 s[0:3], s[4:5], 0x0 + s_waitcnt lgkmcnt(0) + s_and_b32 s4, s7, 0xffff + v_mad_u64_u32 v[0:1], null, s6, s4, v[0:1] + v_mov_b32_e32 v1, 0 + v_lshlrev_b64 v[0:1], 1, v[0:1] + v_add_co_u32 v2, vcc_lo, s0, v0 + v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo + v_add_co_u32 v0, vcc_lo, s2, v0 + v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo + global_load_ushort v2, v[2:3], off + s_waitcnt vmcnt(0) + global_store_short v[0:1], v2, off + s_endpgm + .section .rodata,#alloc + .p2align 6, 0x0 + .amdhsa_kernel _Z3fooPtS_ + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 272 + .amdhsa_user_sgpr_count 6 + .amdhsa_user_sgpr_private_segment_buffer 1 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_flat_scratch_init 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_wavefront_size32 1 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_system_sgpr_private_segment_wavefront_offset 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 4 + .amdhsa_next_free_sgpr 8 + .amdhsa_reserve_flat_scratch 0 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_workgroup_processor_mode 1 + .amdhsa_memory_ordered 1 + .amdhsa_forward_progress 0 + .amdhsa_shared_vgpr_count 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .text +.Lfunc_end0: + .size _Z3fooPtS_, .Lfunc_end0-_Z3fooPtS_ + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 112 +; NumSgprs: 10 +; NumVgprs: 4 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 1 +; VGPRBlocks: 0 +; NumSGPRsForWavesPerEU: 10 +; NumVGPRsForWavesPerEU: 4 +; Occupancy: 16 +; WaveLimiterHint : 1 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .text + .p2alignl 6, 3214868480 + .fill 48, 4, 3214868480 + .protected _ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE ; @_ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE + .type _ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE,@object + .section .rodata._ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE,#alloc + .weak _ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE +_ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE: + .zero 1 + .size _ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE, 1 + + .protected _ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE ; @_ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE + .type _ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE,@object + .section .rodata._ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE,#alloc + .weak _ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE +_ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE: + .zero 1 + .size _ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE, 1 + + .protected _ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE ; @_ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE + .type _ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE,@object + .section .rodata._ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE,#alloc + .weak _ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE +_ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE: + .zero 1 + .size _ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE, 1 + + .ident "AMD clang version 17.0.0 (https://github.com/ROCm/llvm-project roc-6.0.0 23483 7208e8d15fbf218deb74483ea8c549c67ca4985e)" + .section ".note.GNU-stack" + .addrsig + .amdgpu_metadata +--- +amdhsa.kernels: [] +amdhsa.target: amdgcn-amd-amdhsa--gfx1030 +amdhsa.version: + - 1 + - 2 +... + + .end_amdgpu_metadata + .amdgpu_metadata +--- +amdhsa.kernels: + - .args: + - .address_space: global + .offset: 0 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 8 + .size: 8 + .value_kind: global_buffer + - .offset: 16 + .size: 4 + .value_kind: hidden_block_count_x + - .offset: 20 + .size: 4 + .value_kind: hidden_block_count_y + - .offset: 24 + .size: 4 + .value_kind: hidden_block_count_z + - .offset: 28 + .size: 2 + .value_kind: hidden_group_size_x + - .offset: 30 + .size: 2 + .value_kind: hidden_group_size_y + - .offset: 32 + .size: 2 + .value_kind: hidden_group_size_z + - .offset: 34 + .size: 2 + .value_kind: hidden_remainder_x + - .offset: 36 + .size: 2 + .value_kind: hidden_remainder_y + - .offset: 38 + .size: 2 + .value_kind: hidden_remainder_z + - .offset: 56 + .size: 8 + .value_kind: hidden_global_offset_x + - .offset: 64 + .size: 8 + .value_kind: hidden_global_offset_y + - .offset: 72 + .size: 8 + .value_kind: hidden_global_offset_z + - .offset: 80 + .size: 2 + .value_kind: hidden_grid_dims + .group_segment_fixed_size: 0 + .kernarg_segment_align: 8 + .kernarg_segment_size: 272 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 1024 + .name: _Z3fooPtS_ + .private_segment_fixed_size: 0 + .sgpr_count: 10 + .sgpr_spill_count: 0 + .symbol: _Z3fooPtS_.kd + .uniform_work_group_size: 1 + .uses_dynamic_stack: false + .vgpr_count: 4 + .vgpr_spill_count: 0 + .wavefront_size: 32 + .workgroup_processor_mode: 1 +amdhsa.target: amdgcn-amd-amdhsa--gfx1030 +amdhsa.version: + - 1 + - 2 +... + + .end_amdgpu_metadata diff --git a/amd/comgr/test/source/multiple-note-records.s b/amd/comgr/test/source/multiple-note-records.s new file mode 100644 index 0000000000000..ee268bd9b39f2 --- /dev/null +++ b/amd/comgr/test/source/multiple-note-records.s @@ -0,0 +1,385 @@ + .text + .amdgcn_target "amdgcn-amd-amdhsa--gfx1030" + .protected _Z3fooPtS_ ; -- Begin function _Z3fooPtS_ + .globl _Z3fooPtS_ + .p2align 8 + .type _Z3fooPtS_,@function +_Z3fooPtS_: ; @_Z3fooPtS_ +; %bb.0: + s_clause 0x1 + s_load_dword s7, s[4:5], 0x1c + s_load_dwordx4 s[0:3], s[4:5], 0x0 + s_waitcnt lgkmcnt(0) + s_and_b32 s4, s7, 0xffff + v_mad_u64_u32 v[0:1], null, s6, s4, v[0:1] + v_mov_b32_e32 v1, 0 + v_lshlrev_b64 v[0:1], 1, v[0:1] + v_add_co_u32 v2, vcc_lo, s0, v0 + v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo + v_add_co_u32 v0, vcc_lo, s2, v0 + v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo + global_load_ushort v2, v[2:3], off + s_waitcnt vmcnt(0) + global_store_short v[0:1], v2, off + s_endpgm + .section .rodata,#alloc + .p2align 6, 0x0 + .amdhsa_kernel _Z3fooPtS_ + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 272 + .amdhsa_user_sgpr_count 6 + .amdhsa_user_sgpr_private_segment_buffer 1 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_flat_scratch_init 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_wavefront_size32 1 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_system_sgpr_private_segment_wavefront_offset 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 4 + .amdhsa_next_free_sgpr 8 + .amdhsa_reserve_flat_scratch 0 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_workgroup_processor_mode 1 + .amdhsa_memory_ordered 1 + .amdhsa_forward_progress 0 + .amdhsa_shared_vgpr_count 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .text +.Lfunc_end0: + .size _Z3fooPtS_, .Lfunc_end0-_Z3fooPtS_ + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 112 +; NumSgprs: 10 +; NumVgprs: 4 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 1 +; VGPRBlocks: 0 +; NumSGPRsForWavesPerEU: 10 +; NumVGPRsForWavesPerEU: 4 +; Occupancy: 16 +; WaveLimiterHint : 1 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .text + .p2alignl 6, 3214868480 + .fill 48, 4, 3214868480 + .protected _Z3barPmS_ ; -- Begin function _Z3barPmS_ + .globl _Z3barPmS_ + .p2align 8 + .type _Z3barPmS_,@function +_Z3barPmS_: ; @_Z3barPmS_ +; %bb.0: + s_clause 0x1 + s_load_dword s7, s[4:5], 0x1c + s_load_dwordx4 s[0:3], s[4:5], 0x0 + s_waitcnt lgkmcnt(0) + s_and_b32 s4, s7, 0xffff + v_mad_u64_u32 v[0:1], null, s6, s4, v[0:1] + v_mov_b32_e32 v1, 0 + v_lshlrev_b64 v[0:1], 3, v[0:1] + v_add_co_u32 v2, vcc_lo, s0, v0 + v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo + v_add_co_u32 v0, vcc_lo, s2, v0 + v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo + global_load_dwordx2 v[2:3], v[2:3], off + s_waitcnt vmcnt(0) + global_store_dwordx2 v[0:1], v[2:3], off + s_endpgm + .section .rodata,#alloc + .p2align 6, 0x0 + .amdhsa_kernel _Z3barPmS_ + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 272 + .amdhsa_user_sgpr_count 6 + .amdhsa_user_sgpr_private_segment_buffer 1 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_flat_scratch_init 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_wavefront_size32 1 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_system_sgpr_private_segment_wavefront_offset 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 4 + .amdhsa_next_free_sgpr 8 + .amdhsa_reserve_flat_scratch 0 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_workgroup_processor_mode 1 + .amdhsa_memory_ordered 1 + .amdhsa_forward_progress 0 + .amdhsa_shared_vgpr_count 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .text +.Lfunc_end1: + .size _Z3barPmS_, .Lfunc_end1-_Z3barPmS_ + ; -- End function + .section .AMDGPU.csdata +; Kernel info: +; codeLenInByte = 112 +; NumSgprs: 10 +; NumVgprs: 4 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 1 +; VGPRBlocks: 0 +; NumSGPRsForWavesPerEU: 10 +; NumVGPRsForWavesPerEU: 4 +; Occupancy: 16 +; WaveLimiterHint : 1 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 + .text + .p2alignl 6, 3214868480 + .fill 48, 4, 3214868480 + .protected _ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE ; @_ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE + .type _ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE,@object + .section .rodata._ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE,#alloc + .weak _ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE +_ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE: + .zero 1 + .size _ZN17__HIP_CoordinatesI15__HIP_ThreadIdxE1xE, 1 + + .protected _ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE ; @_ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE + .type _ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE,@object + .section .rodata._ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE,#alloc + .weak _ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE +_ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE: + .zero 1 + .size _ZN17__HIP_CoordinatesI14__HIP_BlockIdxE1xE, 1 + + .protected _ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE ; @_ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE + .type _ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE,@object + .section .rodata._ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE,#alloc + .weak _ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE +_ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE: + .zero 1 + .size _ZN17__HIP_CoordinatesI14__HIP_BlockDimE1xE, 1 + + .ident "AMD clang version 17.0.0 (https://github.com/ROCm/llvm-project roc-6.0.0 23483 7208e8d15fbf218deb74483ea8c549c67ca4985e)" + .section ".note.GNU-stack" + .addrsig + .amdgpu_metadata +--- +amdhsa.kernels: + - .args: + - .address_space: global + .offset: 0 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 8 + .size: 8 + .value_kind: global_buffer + - .offset: 16 + .size: 4 + .value_kind: hidden_block_count_x + - .offset: 20 + .size: 4 + .value_kind: hidden_block_count_y + - .offset: 24 + .size: 4 + .value_kind: hidden_block_count_z + - .offset: 28 + .size: 2 + .value_kind: hidden_group_size_x + - .offset: 30 + .size: 2 + .value_kind: hidden_group_size_y + - .offset: 32 + .size: 2 + .value_kind: hidden_group_size_z + - .offset: 34 + .size: 2 + .value_kind: hidden_remainder_x + - .offset: 36 + .size: 2 + .value_kind: hidden_remainder_y + - .offset: 38 + .size: 2 + .value_kind: hidden_remainder_z + - .offset: 56 + .size: 8 + .value_kind: hidden_global_offset_x + - .offset: 64 + .size: 8 + .value_kind: hidden_global_offset_y + - .offset: 72 + .size: 8 + .value_kind: hidden_global_offset_z + - .offset: 80 + .size: 2 + .value_kind: hidden_grid_dims + .group_segment_fixed_size: 0 + .kernarg_segment_align: 8 + .kernarg_segment_size: 272 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 1024 + .name: _Z3barPmS_ + .private_segment_fixed_size: 0 + .sgpr_count: 10 + .sgpr_spill_count: 0 + .symbol: _Z3barPmS_.kd + .uniform_work_group_size: 1 + .uses_dynamic_stack: false + .vgpr_count: 4 + .vgpr_spill_count: 0 + .wavefront_size: 32 + .workgroup_processor_mode: 1 +amdhsa.target: amdgcn-amd-amdhsa--gfx1030 +amdhsa.version: + - 1 + - 2 +... + + .end_amdgpu_metadata + .amdgpu_metadata +--- +amdhsa.kernels: + - .args: + - .address_space: global + .offset: 0 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 8 + .size: 8 + .value_kind: global_buffer + - .offset: 16 + .size: 4 + .value_kind: hidden_block_count_x + - .offset: 20 + .size: 4 + .value_kind: hidden_block_count_y + - .offset: 24 + .size: 4 + .value_kind: hidden_block_count_z + - .offset: 28 + .size: 2 + .value_kind: hidden_group_size_x + - .offset: 30 + .size: 2 + .value_kind: hidden_group_size_y + - .offset: 32 + .size: 2 + .value_kind: hidden_group_size_z + - .offset: 34 + .size: 2 + .value_kind: hidden_remainder_x + - .offset: 36 + .size: 2 + .value_kind: hidden_remainder_y + - .offset: 38 + .size: 2 + .value_kind: hidden_remainder_z + - .offset: 56 + .size: 8 + .value_kind: hidden_global_offset_x + - .offset: 64 + .size: 8 + .value_kind: hidden_global_offset_y + - .offset: 72 + .size: 8 + .value_kind: hidden_global_offset_z + - .offset: 80 + .size: 2 + .value_kind: hidden_grid_dims + .group_segment_fixed_size: 0 + .kernarg_segment_align: 8 + .kernarg_segment_size: 272 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 1024 + .name: _Z3fooPtS_ + .private_segment_fixed_size: 0 + .sgpr_count: 10 + .sgpr_spill_count: 0 + .symbol: _Z3fooPtS_.kd + .uniform_work_group_size: 1 + .uses_dynamic_stack: false + .vgpr_count: 4 + .vgpr_spill_count: 0 + .wavefront_size: 32 + .workgroup_processor_mode: 1 +amdhsa.target: amdgcn-amd-amdhsa--gfx1030 +amdhsa.version: + - 1 + - 2 +... + + .end_amdgpu_metadata + .amdgpu_metadata +--- +amdhsa.kernels: [] +amdhsa.target: amdgcn-amd-amdhsa--gfx1030 +amdhsa.version: + - 1 + - 2 +... + + .end_amdgpu_metadata diff --git a/amd/comgr/test/source/name-expression.hip b/amd/comgr/test/source/name-expression.hip new file mode 100644 index 0000000000000..0bb7562b99a76 --- /dev/null +++ b/amd/comgr/test/source/name-expression.hip @@ -0,0 +1,21 @@ +template +__attribute__((global)) void my_kernel_FOO(T* array) { + array[0] = N; +} +static __attribute__((device)) const void* __amdgcn_name_expr_ABC[] = { + "my_kernel_FOO(2+1),float >", + (void*)&my_kernel_FOO(2+1),float > + }; + +static auto __amdgcn_name_expr_stub_ABC = __amdgcn_name_expr_ABC; + +template +__attribute__((global)) void my_kernel_BOO(T* array) { + array[0] = N; +} +static __attribute__((device)) const void* __amdgcn_name_expr_XYZ[] = { + "my_kernel_BOO(2+1),float >", + (void*)&my_kernel_BOO(2+1),float > + }; + +static auto __amdgcn_name_expr_stub_XYZ= __amdgcn_name_expr_XYZ; diff --git a/amd/comgr/test/source/nested-kernel1.cl b/amd/comgr/test/source/nested-kernel1.cl new file mode 100644 index 0000000000000..db6f34f558ba9 --- /dev/null +++ b/amd/comgr/test/source/nested-kernel1.cl @@ -0,0 +1,6 @@ +#include "include-nested.h" + +void kernel nested1(__global int *j) { + *j += 2; + nested2(j); +} diff --git a/amd/comgr/test/source/nested-kernel2.cl b/amd/comgr/test/source/nested-kernel2.cl new file mode 100644 index 0000000000000..2e4b8df2109ab --- /dev/null +++ b/amd/comgr/test/source/nested-kernel2.cl @@ -0,0 +1,3 @@ +#include "include-nested.h" + +void kernel nested2(__global int *j) { *j = FOO; } diff --git a/amd/comgr/test/source/reloc-asm.s b/amd/comgr/test/source/reloc-asm.s new file mode 100644 index 0000000000000..9a5fd68c96541 --- /dev/null +++ b/amd/comgr/test/source/reloc-asm.s @@ -0,0 +1,19 @@ + .text + .file "reloc-asm.c" + .globl foo + .p2align 4, 0x90 + .type foo,@function +foo: + s_load_dwordx2 s[0:1], s[4:5], 0x0 // 000000000000: C0060002 00000000 + v_mov_b32_e32 v2, 42 // 000000000008: 7E0402AA + s_waitcnt lgkmcnt(0) // 00000000000C: BF8C007F + v_mov_b32_e32 v0, s0 // 000000000010: 7E000200 + v_mov_b32_e32 v1, s1 // 000000000014: 7E020201 + flat_store_dword v[0:1], v2 // 000000000018: DC700000 00000200 + s_endpgm +.Lfunc_end0: + .size foo, .Lfunc_end0-foo + + .ident "clang" + .section ".note.GNU-stack","",@progbits + .addrsig diff --git a/amd/comgr/test/source/reloc1.cl b/amd/comgr/test/source/reloc1.cl new file mode 100644 index 0000000000000..1b7f028b1833f --- /dev/null +++ b/amd/comgr/test/source/reloc1.cl @@ -0,0 +1,3 @@ +// clang bytes1.cl --target=amdgcn-amdhsa-opencl -mcpu=gfx803 -c -o bytes1.o + +void kernel foo(global int *a) { *a = 42; } diff --git a/amd/comgr/test/source/reloc2.cl b/amd/comgr/test/source/reloc2.cl new file mode 100644 index 0000000000000..4a6db6d0e7e9a --- /dev/null +++ b/amd/comgr/test/source/reloc2.cl @@ -0,0 +1,3 @@ +// clang bytes2.cl --target=amdgcn-amdhsa-opencl -mcpu=gfx900 -c -o bytes2.o + +void kernel bar(global int *a) { *a = 43; } diff --git a/amd/comgr/test/source/rocm56slice.b b/amd/comgr/test/source/rocm56slice.b new file mode 100644 index 0000000000000..cd14c633413db Binary files /dev/null and b/amd/comgr/test/source/rocm56slice.b differ diff --git a/amd/comgr/test/source/rocm57slice.b b/amd/comgr/test/source/rocm57slice.b new file mode 100644 index 0000000000000..3c78cfb4bc2f6 Binary files /dev/null and b/amd/comgr/test/source/rocm57slice.b differ diff --git a/amd/comgr/test/source/shared.cl b/amd/comgr/test/source/shared.cl new file mode 100644 index 0000000000000..0857ddfd81fd7 --- /dev/null +++ b/amd/comgr/test/source/shared.cl @@ -0,0 +1,9 @@ +// Standard +// clang shared.cl --target=amdgcn-amd-amdhsa -mcpu=gfx900 -O3 -o shared.so + +__attribute__((visibility("default"))) constant int foo = 0; + +void kernel bazzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz( + global int *a, const global int *b) { + *a = *b; +} diff --git a/amd/comgr/test/source/source1.cl b/amd/comgr/test/source/source1.cl new file mode 100644 index 0000000000000..63049e5538375 --- /dev/null +++ b/amd/comgr/test/source/source1.cl @@ -0,0 +1 @@ +void kernel source1(__global int *j) { *j += 2; } diff --git a/amd/comgr/test/source/source1.hip b/amd/comgr/test/source/source1.hip new file mode 100644 index 0000000000000..dc2d7a662cfeb --- /dev/null +++ b/amd/comgr/test/source/source1.hip @@ -0,0 +1,3 @@ +void source1(int *j) { + *j += 2; +} diff --git a/amd/comgr/test/source/source1.s b/amd/comgr/test/source/source1.s new file mode 100644 index 0000000000000..479ad1606fe48 --- /dev/null +++ b/amd/comgr/test/source/source1.s @@ -0,0 +1,8 @@ +baz: + s_load_dwordx2 s[0:1], s[4:5], 0x0 // 000000001100: C0060002 00000000 + v_mov_b32_e32 v2, 44 // 000000001108: 7E0402AC + s_waitcnt lgkmcnt(0) // 00000000110C: BF8C007F + v_mov_b32_e32 v0, s0 // 000000001110: 7E000200 + v_mov_b32_e32 v1, s1 // 000000001114: 7E020201 + flat_store_dword v[0:1], v2 // 000000001118: DC700000 00000200 + s_endpgm // 000000001120: BF810000 diff --git a/amd/comgr/test/source/source2.cl b/amd/comgr/test/source/source2.cl new file mode 100644 index 0000000000000..1a06cc182133b --- /dev/null +++ b/amd/comgr/test/source/source2.cl @@ -0,0 +1,3 @@ +#include "include-macro.h" + +void kernel source2(__global int *j) { *j = FOO; } diff --git a/amd/comgr/test/source/square.hip b/amd/comgr/test/source/square.hip new file mode 100644 index 0000000000000..eef9c3025cf90 --- /dev/null +++ b/amd/comgr/test/source/square.hip @@ -0,0 +1,3 @@ +void square(int *j) { + *j = *j * *j; +} diff --git a/amd/comgr/test/source/symbolize.cl b/amd/comgr/test/source/symbolize.cl new file mode 100644 index 0000000000000..f6eb67ce23443 --- /dev/null +++ b/amd/comgr/test/source/symbolize.cl @@ -0,0 +1,15 @@ +// Debug +// clang -c -O3 -g -target=amdgcn-amd-amdhsa -mcpu=gfx900 symbolize.cl -o +// symbolize-debug.so + +__attribute__((visibility("default"))) constant int foo = 1234; + +int offset(int x) { return x + foo + 5678; } + +void kernel bazzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz( + global int *a, const global int *b) { + if (offset(foo) < offset(*b)) + *a = *b; + else + *a = foo; +} diff --git a/amd/comgr/test/symbolize_test.c b/amd/comgr/test/symbolize_test.c new file mode 100644 index 0000000000000..f03dc79a00955 --- /dev/null +++ b/amd/comgr/test/symbolize_test.c @@ -0,0 +1,134 @@ +//===- symbolize_test.c ---------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +#define CHECK(ptr, ...) \ + do { \ + if ((ptr) == NULL) { \ + fprintf(stderr, "Error: "); \ + fprintf(stderr, __VA_ARGS__); \ + fprintf(stderr, " at %s:%d\n", __FILE__, __LINE__); \ + exit(EXIT_FAILURE); \ + } \ + } while (0) + +typedef struct Container { + char *Data; + int Sz; +} container_t; + +void collectSymbolizedString(const char *Input, void *Data) { + int Sz = strlen(Input); + container_t *Ptr = (container_t *)Data; + Ptr->Data = (char *)malloc(Sz + 1); + Ptr->Data[Sz] = '\0'; + Ptr->Sz = Sz; + memcpy(Ptr->Data, Input, Sz); +} + +void testSymbolizedString(container_t *SymbolContainer) { + + char *SymbolStr = SymbolContainer->Data; + CHECK(SymbolStr, "Failed, symbol_str is NULL.\n"); + + char *SpacePos = strchr(SymbolStr, ' '); + CHECK(SpacePos, "Expected spaces in %s\n", SymbolStr); + + char *LineColPos = strchr(SymbolStr, ':'); + CHECK(LineColPos, "Expected line:column information in %s\n", SymbolStr); + + char *NewlinePos = strchr(SymbolStr, '\n'); + CHECK(NewlinePos, "Expected '\\n' in %s", SymbolStr); + + size_t FuncNameSize = SpacePos - SymbolStr; + char *FuncName = (char *)malloc(sizeof(char) * (FuncNameSize + 1)); + + strncpy(FuncName, SymbolStr, FuncNameSize); + FuncName[FuncNameSize] = '\0'; + + size_t LineColSize = NewlinePos - LineColPos; + char *LineCol = (char *)malloc(sizeof(char) * (LineColSize)); + + strncpy(LineCol, LineColPos + 1, LineColSize); + LineCol[LineColSize - 1] = '\0'; + + if (strcmp(FuncName, + "bazzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz") && + strcmp(LineCol, "46:7 (approximate)")) { + printf("mismatch:\n"); + printf("expected symbolized function name: " + "'bazzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz'\n"); + printf("actual symbolized function name: '%s'\n", FuncName); + printf("expected symbolized line:column output: '46:7 (approximate)'\n"); + printf("actual symbolized line:column output: '%s'\n", LineCol); + exit(0); + } + + printf("symbolized string is %s", SymbolStr); + free(FuncName); + free(LineCol); + free(SymbolStr); + + return; +} + +int main(int argc, char *argv[]) { + size_t Size; + char *Buf; + amd_comgr_data_t DataIn; + amd_comgr_status_t Status; + amd_comgr_symbolizer_info_t Symbolizer; + container_t UserData; + + // Read input file + Size = setBuf(TEST_OBJ_DIR "/symbolize-debug.so", &Buf); + + // Create data object + { + printf("Test create input data set\n"); + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_EXECUTABLE, &DataIn); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataIn, Size, Buf); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataIn, "symbolize-debug.so"); + checkError(Status, "amd_comgr_set_data_name"); + } + + // Create symbolizer info and symbolize + { + printf("Test create symbolizer info\n"); + Status = amd_comgr_create_symbolizer_info(DataIn, &collectSymbolizedString, + &Symbolizer); + checkError(Status, "amd_comgr_create_symbolizer_info"); + // Use this command to get valid address + // llvm-objdump --triple=amdgcn-amd-amdhsa -l --mcpu=gfx900 --disassemble + // --source symbolize-debug.so + uint64_t Address = 0x128; + Status = amd_comgr_symbolize(Symbolizer, Address, 1, (void *)&UserData); + checkError(Status, "amd_comgr_symbolize"); + + testSymbolizedString(&UserData); + } + + // Destroy symbolizer info + { + printf("Test destroy symbolizer info\n"); + Status = amd_comgr_destroy_symbolizer_info(Symbolizer); + checkError(Status, "amd_comgr_destroy_symbolizer_info"); + Status = amd_comgr_release_data(DataIn); + checkError(Status, "amd_comgr_release_data"); + free(Buf); + } + + return 0; +} diff --git a/amd/comgr/test/symbols_iterate_test.c b/amd/comgr/test/symbols_iterate_test.c new file mode 100644 index 0000000000000..9ee7ea96b4172 --- /dev/null +++ b/amd/comgr/test/symbols_iterate_test.c @@ -0,0 +1,38 @@ +//===- symbols_iterate_test.c ---------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int argc, char *argv[]) { + long Size; + char *Buf; + amd_comgr_data_t DataObject; + amd_comgr_status_t Status; + int Count = 1; + + Size = setBuf(TEST_OBJ_DIR "/shared.so", &Buf); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_EXECUTABLE, &DataObject); + checkError(Status, "amd_comgr_create_data"); + + Status = amd_comgr_set_data(DataObject, Size, Buf); + checkError(Status, "amd_comgr_set_data"); + + Status = amd_comgr_iterate_symbols(DataObject, printSymbol, &Count); + checkError(Status, "amd_comgr_iterate_symbols"); + + Status = amd_comgr_release_data(DataObject); + checkError(Status, "amd_comgr_release_data"); + free(Buf); + + return 0; +} diff --git a/amd/comgr/test/symbols_test.c b/amd/comgr/test/symbols_test.c new file mode 100644 index 0000000000000..a8b578acad30a --- /dev/null +++ b/amd/comgr/test/symbols_test.c @@ -0,0 +1,61 @@ +//===- symbols_test.c -----------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +void expectSymbol(const char *ObjectFilename, const char *SymbolName, + amd_comgr_symbol_type_t ExpectedType) { + long Size; + char *Buf; + amd_comgr_data_t DataObject; + amd_comgr_symbol_t Symbol; + amd_comgr_status_t Status; + + Size = setBuf(ObjectFilename, &Buf); + + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_EXECUTABLE, &DataObject); + checkError(Status, "amd_comgr_create_data"); + + Status = amd_comgr_set_data(DataObject, Size, Buf); + checkError(Status, "amd_comgr_set_data"); + + Status = amd_comgr_symbol_lookup(DataObject, SymbolName, &Symbol); + checkError(Status, "amd_comgr_symbol_lookup"); + + amd_comgr_symbol_type_t Type; + Status = amd_comgr_symbol_get_info(Symbol, AMD_COMGR_SYMBOL_INFO_TYPE, + (void *)&Type); + checkError(Status, "amd_comgr_symbol_get_info"); + + if (Type != ExpectedType) { + fail("unexpected symbol type for symbol %s: expected %d, saw %d\n", + SymbolName, ExpectedType, Type); + } + + Status = amd_comgr_release_data(DataObject); + checkError(Status, "amd_comgr_release_data"); + free(Buf); +} + +int main(int argc, char *argv[]) { + expectSymbol(TEST_OBJ_DIR "/shared-v2.so", + "bazzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz", + AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL); + expectSymbol(TEST_OBJ_DIR "/shared-v3.so", + "bazzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz", + AMD_COMGR_SYMBOL_TYPE_FUNC); + expectSymbol(TEST_OBJ_DIR "/shared-v2.so", "foo", + AMD_COMGR_SYMBOL_TYPE_OBJECT); + expectSymbol(TEST_OBJ_DIR "/shared-v3.so", "foo", + AMD_COMGR_SYMBOL_TYPE_OBJECT); + return 0; +} diff --git a/amd/comgr/test/unbundle_hip_test.c b/amd/comgr/test/unbundle_hip_test.c new file mode 100644 index 0000000000000..fe5276c52372e --- /dev/null +++ b/amd/comgr/test/unbundle_hip_test.c @@ -0,0 +1,451 @@ +//===- unbundle_hip_test.c ------------------------------------------------===// +// +// Part of Comgr, under the Apache License v2.0 with LLVM Exceptions. See +// amd/comgr/LICENSE.TXT in this repository for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +/// ------- +// Manual recreation of Comgr bundle linking +// +// // Create bitcode bundles +// clang -c --offload-arch=gfx900 -emit-llvm -fgpu-rdc \ +// --gpu-bundle-output square.hip cube.hip +// +// // Create object file bundles +// clang -c --offload-arch=gfx900 --gpu-bundle-output \ +// double.hip +// +// // Create archive bundle +// llvm-ar rc cube.a cube.bc +// +// // Manually unbundle bitcode bundle +// clang-offload-bundler -type=bc \ +// -targets=hip-amdgcn-amd-amdhsa-unknown-gfx900 \ +// -input=square.bc -output=square-gfx900.bc \ +// -unbundle -allow-missing-bundles +// +// // Manually unbundle object file bundle +// clang-offload-bundler -type=o \ +// -targets=hip-amdgcn-amd-amdhsa-unknown-gfx900 \ +// -input=double.o -output=double-gfx900.o \ +// -unbundle -allow-missing-bundles +// +// // Manually unbundle archive bundle +// clang-offload-bundler -type=a \ +// -targets=hip-amdgcn-amd-amdhsa-unknown-gfx900 \ +// -input=cube.a -output=cube-gfx900.a \ +// -unbundle -allow-missing-bundles \ +// -hip-openmp-compatible + +#include "amd_comgr.h" +#include "common.h" +#include +#include +#include + +int main(int Argc, char *Argv[]) { + char *BufBitcode, *BufObjectFile, *BufArchive; + size_t SizeBitcode, SizeObjectFile, SizeArchive; + amd_comgr_data_t DataBitcode, DataObjectFile, DataArchive; + amd_comgr_data_set_t DataSetBundled, DataSetUnbundled, DataSetLinked, + DataSetReloc, DataSetExec; + amd_comgr_action_info_t ActionInfoUnbundle, ActionInfoLink; + amd_comgr_status_t Status; + + SizeBitcode = setBuf("./source/square.bc", &BufBitcode); + SizeObjectFile = setBuf("./source/double.o", &BufObjectFile); + SizeArchive = setBuf("./source/cube.a", &BufArchive); + + // Create Bundled dataset + Status = amd_comgr_create_data_set(&DataSetBundled); + checkError(Status, "amd_comgr_create_data_set"); + + // Bitcode + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_BC_BUNDLE, &DataBitcode); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataBitcode, SizeBitcode, BufBitcode); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataBitcode, "square"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetBundled, DataBitcode); + checkError(Status, "amd_comgr_data_set_add"); + + // ObjectFile + Status = + amd_comgr_create_data(AMD_COMGR_DATA_KIND_OBJ_BUNDLE, &DataObjectFile); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataObjectFile, SizeObjectFile, BufObjectFile); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataObjectFile, "double"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetBundled, DataObjectFile); + checkError(Status, "amd_comgr_data_set_add"); + + // Archive + Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_AR_BUNDLE, &DataArchive); + checkError(Status, "amd_comgr_create_data"); + Status = amd_comgr_set_data(DataArchive, SizeArchive, BufArchive); + checkError(Status, "amd_comgr_set_data"); + Status = amd_comgr_set_data_name(DataArchive, "cube"); + checkError(Status, "amd_comgr_set_data_name"); + Status = amd_comgr_data_set_add(DataSetBundled, DataArchive); + checkError(Status, "amd_comgr_data_set_add"); + + // Unbundle explicitly via UNBUNDLE action + { + // Set up ActionInfo + Status = amd_comgr_create_action_info(&ActionInfoUnbundle); + checkError(Status, "amd_comgr_create_action_info"); + + Status = amd_comgr_action_info_set_language(ActionInfoUnbundle, + AMD_COMGR_LANGUAGE_HIP); + checkError(Status, "amd_comgr_action_info_set_language"); + + const char *BundleEntryIDs[] = {"host-x86_64-unknown-linux-gnu", + "hip-amdgcn-amd-amdhsa-unknown-gfx900"}; + size_t BundleEntryIDsCount = + sizeof(BundleEntryIDs) / sizeof(BundleEntryIDs[0]); + Status = amd_comgr_action_info_set_bundle_entry_ids( + ActionInfoUnbundle, BundleEntryIDs, BundleEntryIDsCount); + + // Unbundle + Status = amd_comgr_create_data_set(&DataSetUnbundled); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_UNBUNDLE, ActionInfoUnbundle, + DataSetBundled, DataSetUnbundled); + checkError(Status, "amd_comgr_do_action"); + + // -------- + // Check Bitcode count, element names, and element sizes + size_t Count; + Status = amd_comgr_action_data_count(DataSetUnbundled, + AMD_COMGR_DATA_KIND_BC, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 2) { + printf("Unbundle: produced %zu bitcodes (expected 2)\n", Count); + exit(1); + } + + amd_comgr_data_t DataElement; + + // bitcode host element (empty) + Status = amd_comgr_action_data_get_data( + DataSetUnbundled, AMD_COMGR_DATA_KIND_BC, 0, &DataElement); + checkError(Status, "amd_comgr_action_data_get_data"); + + size_t NameSize; + char Name[100]; + Status = amd_comgr_get_data_name(DataElement, &NameSize, NULL); + checkError(Status, "amd_comgr_get_data_name"); + Status = amd_comgr_get_data_name(DataElement, &NameSize, &Name[0]); + checkError(Status, "amd_comgr_get_data_name"); + + const char *ExpectedName = "square-host-x86_64-unknown-linux-gnu.bc"; + if (strcmp(Name, ExpectedName)) { + printf("Bitcode host element name mismatch: %s (expected %s)\n", Name, + ExpectedName); + } + + size_t BytesSize = 0; + Status = amd_comgr_get_data(DataElement, &BytesSize, NULL); + checkError(Status, "amd_comgr_get_data"); + Status = amd_comgr_release_data(DataElement); + checkError(Status, "amd_comgr_release_data"); + + if (!BytesSize) { + printf("Bitcode host empty (expected non-empty)\n"); + exit(1); + } + + // bitcode hip-gfx900 element (non-empty) + Status = amd_comgr_action_data_get_data( + DataSetUnbundled, AMD_COMGR_DATA_KIND_BC, 1, &DataElement); + checkError(Status, "amd_comgr_action_data_get_data"); + + Status = amd_comgr_get_data_name(DataElement, &NameSize, NULL); + checkError(Status, "amd_comgr_get_data_name"); + Status = amd_comgr_get_data_name(DataElement, &NameSize, &Name[0]); + checkError(Status, "amd_comgr_get_data_name"); + + ExpectedName = "square-hip-amdgcn-amd-amdhsa-unknown-gfx900.bc"; + if (strcmp(Name, ExpectedName)) { + printf("Bitcode hip-gfx900 element name mismatch: %s (expected %s)\n", + Name, ExpectedName); + } + + BytesSize = 0; + Status = amd_comgr_get_data(DataElement, &BytesSize, NULL); + checkError(Status, "amd_comgr_get_data"); + Status = amd_comgr_release_data(DataElement); + checkError(Status, "amd_comgr_release_data"); + + if (BytesSize == 0) { + printf("Bitcode hip-gfx900 empty (expected non-empty)\n"); + exit(1); + } + + // -------- + // Check ObjectFile count, element names, and element sizes + Status = amd_comgr_action_data_count( + DataSetUnbundled, AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 2) { + printf("Unbundle: produced %zu object files (expected 2)\n", Count); + exit(1); + } + + // object host element (empty) + Status = amd_comgr_action_data_get_data( + DataSetUnbundled, AMD_COMGR_DATA_KIND_EXECUTABLE, 0, &DataElement); + checkError(Status, "amd_comgr_action_data_get_data"); + + Status = amd_comgr_get_data_name(DataElement, &NameSize, NULL); + checkError(Status, "amd_comgr_get_data_name"); + Status = amd_comgr_get_data_name(DataElement, &NameSize, &Name[0]); + checkError(Status, "amd_comgr_get_data_name"); + + ExpectedName = "double-host-x86_64-unknown-linux-gnu.o"; + if (strcmp(Name, ExpectedName)) { + printf("Object host element name mismatch: %s (expected %s)\n", Name, + ExpectedName); + } + + BytesSize = 0; + Status = amd_comgr_get_data(DataElement, &BytesSize, NULL); + checkError(Status, "amd_comgr_get_data"); + Status = amd_comgr_release_data(DataElement); + checkError(Status, "amd_comgr_release_data"); + + if (BytesSize) { + printf("Object host element size: %ld (expected empty)\n", BytesSize); + exit(1); + } + + // object hip-gfx900 element (non-empty) + Status = amd_comgr_action_data_get_data( + DataSetUnbundled, AMD_COMGR_DATA_KIND_EXECUTABLE, 1, &DataElement); + checkError(Status, "amd_comgr_action_data_get_data"); + + Status = amd_comgr_get_data_name(DataElement, &NameSize, NULL); + checkError(Status, "amd_comgr_get_data_name"); + Status = amd_comgr_get_data_name(DataElement, &NameSize, &Name[0]); + checkError(Status, "amd_comgr_get_data_name"); + + ExpectedName = "double-hip-amdgcn-amd-amdhsa-unknown-gfx900.o"; + if (strcmp(Name, ExpectedName)) { + printf("Object hip-gfx900 element name mismatch: %s (expected %s)\n", + Name, ExpectedName); + } + + BytesSize = 0; + Status = amd_comgr_get_data(DataElement, &BytesSize, NULL); + checkError(Status, "amd_comgr_get_data"); + Status = amd_comgr_release_data(DataElement); + checkError(Status, "amd_comgr_release_data"); + + if (BytesSize == 0) { + printf("Object hip-gfx900 empty (expected non-empty)\n"); + exit(1); + } + + // -------- + // Check Archive count, element names, and element sizes + Status = amd_comgr_action_data_count(DataSetUnbundled, + AMD_COMGR_DATA_KIND_AR, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 2) { + printf("Unbundle: produced %zu archives (expected 2)\n", Count); + exit(1); + } + + // archive host element (empty, size 8) + Status = amd_comgr_action_data_get_data( + DataSetUnbundled, AMD_COMGR_DATA_KIND_AR, 0, &DataElement); + checkError(Status, "amd_comgr_action_data_get_data"); + + Status = amd_comgr_get_data_name(DataElement, &NameSize, NULL); + checkError(Status, "amd_comgr_get_data_name"); + Status = amd_comgr_get_data_name(DataElement, &NameSize, &Name[0]); + checkError(Status, "amd_comgr_get_data_name"); + + ExpectedName = "cube-host-x86_64-unknown-linux-gnu.a"; + if (strcmp(Name, ExpectedName)) { + printf("Archive host element name mismatch: %s (expected %s)\n", Name, + ExpectedName); + } + + BytesSize = 0; + Status = amd_comgr_get_data(DataElement, &BytesSize, NULL); + checkError(Status, "amd_comgr_get_data"); + Status = amd_comgr_release_data(DataElement); + checkError(Status, "amd_comgr_release_data"); + + if (!BytesSize) { + printf("Arvhive host empty (expected non-empty)\n"); + exit(1); + } + + // archive hip-gfx900 element (non-empty) + Status = amd_comgr_action_data_get_data( + DataSetUnbundled, AMD_COMGR_DATA_KIND_AR, 1, &DataElement); + checkError(Status, "amd_comgr_action_data_get_data"); + + Status = amd_comgr_get_data_name(DataElement, &NameSize, NULL); + checkError(Status, "amd_comgr_get_data_name"); + Status = amd_comgr_get_data_name(DataElement, &NameSize, &Name[0]); + checkError(Status, "amd_comgr_get_data_name"); + + ExpectedName = "cube-hip-amdgcn-amd-amdhsa-unknown-gfx900.a"; + if (strcmp(Name, ExpectedName)) { + printf("Archive hip-gfx900 bundle name mismatch: %s (expected %s)\n", + Name, ExpectedName); + } + + BytesSize = 0; + Status = amd_comgr_get_data(DataElement, &BytesSize, NULL); + checkError(Status, "amd_comgr_get_data"); + Status = amd_comgr_release_data(DataElement); + checkError(Status, "amd_comgr_release_data"); + + if (BytesSize < 9) { + printf("Archive hip-gfx900 element size: %ld (expected > 9)\n", + BytesSize); + exit(1); + } + + // -------- + // Check Bundle Entry IDs + size_t BundleCount; + Status = amd_comgr_action_info_get_bundle_entry_id_count(ActionInfoUnbundle, + &BundleCount); + checkError(Status, "amd_comgr_action_info_get_bundle_entry_id_count"); + + for (size_t I = 0; I < BundleCount; I++) { + + size_t Size; + Status = amd_comgr_action_info_get_bundle_entry_id(ActionInfoUnbundle, I, + &Size, NULL); + checkError(Status, "amd_comgr_action_info_get_bundle_entry_id"); + + char *BundleID = calloc(Size, sizeof(char)); + Status = amd_comgr_action_info_get_bundle_entry_id(ActionInfoUnbundle, I, + &Size, BundleID); + checkError(Status, "amd_comgr_action_info_get_bundle_entry_id"); + + if (strcmp(BundleID, BundleEntryIDs[I])) { + printf("BundleEntryID mismatch. Expected \"%s\", returned \"%s\"\n", + BundleEntryIDs[I], BundleID); + checkError(AMD_COMGR_STATUS_ERROR, + "amd_comgr_action_info_get_bundle_entry_id"); + } + + free(BundleID); + } + } + + // Unbundle silently via LINK action + { + // Set up ActionInfo + Status = amd_comgr_create_action_info(&ActionInfoLink); + checkError(Status, "amd_comgr_create_action_info"); + + Status = amd_comgr_action_info_set_language(ActionInfoLink, + AMD_COMGR_LANGUAGE_HIP); + checkError(Status, "amd_comgr_action_info_set_language"); + + const char *IsaName = "amdgcn-amd-amdhsa--gfx900"; + Status = amd_comgr_action_info_set_isa_name(ActionInfoLink, IsaName); + + // Unbundle + Status = amd_comgr_create_data_set(&DataSetLinked); + checkError(Status, "amd_comgr_create_data_set"); + Status = amd_comgr_do_action(AMD_COMGR_ACTION_LINK_BC_TO_BC, ActionInfoLink, + DataSetBundled, DataSetLinked); + checkError(Status, "amd_comgr_do_action"); + + // Check Linked bitcode count + size_t Count; + Status = amd_comgr_action_data_count(DataSetLinked, AMD_COMGR_DATA_KIND_BC, + &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("Bundled bitcode linking: " + "produced %zu bitcodes (expected 1)\n", + Count); + exit(1); + } + + // Compile to relocatable + Status = amd_comgr_create_data_set(&DataSetReloc); + checkError(Status, "amd_comgr_create_data_set"); + + Status = amd_comgr_do_action(AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, + ActionInfoLink, DataSetLinked, DataSetReloc); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count( + DataSetReloc, AMD_COMGR_DATA_KIND_RELOCATABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE Failed: " + "produced %zu source objects (expected 1)\n", + Count); + exit(1); + } + + // Compile to executable + Status = amd_comgr_create_data_set(&DataSetExec); + checkError(Status, "amd_comgr_create_data_set"); + + Status = + amd_comgr_do_action(AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, + ActionInfoLink, DataSetReloc, DataSetExec); + checkError(Status, "amd_comgr_do_action"); + + Status = amd_comgr_action_data_count( + DataSetExec, AMD_COMGR_DATA_KIND_EXECUTABLE, &Count); + checkError(Status, "amd_comgr_action_data_count"); + + if (Count != 1) { + printf("AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE Failed: " + "produced %zu executable objects (expected 1)\n", + Count); + exit(1); + } + } + + // Cleanup + Status = amd_comgr_destroy_action_info(ActionInfoUnbundle); + checkError(Status, "amd_comgr_destroy_action_info"); + Status = amd_comgr_destroy_action_info(ActionInfoLink); + checkError(Status, "amd_comgr_destroy_action_info"); + Status = amd_comgr_destroy_data_set(DataSetBundled); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetUnbundled); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetLinked); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetReloc); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_destroy_data_set(DataSetExec); + checkError(Status, "amd_comgr_destroy_data_set"); + Status = amd_comgr_release_data(DataBitcode); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataObjectFile); + checkError(Status, "amd_comgr_release_data"); + Status = amd_comgr_release_data(DataArchive); + checkError(Status, "amd_comgr_release_data"); + + free(BufBitcode); + free(BufObjectFile); + free(BufArchive); + + return 0; +} diff --git a/amd/comgr/utils/tidy-and-format.sh b/amd/comgr/utils/tidy-and-format.sh new file mode 100755 index 0000000000000..537a187185090 --- /dev/null +++ b/amd/comgr/utils/tidy-and-format.sh @@ -0,0 +1,24 @@ +#/bin/bash + +set -euo pipefail + +if ! test -f ../../../build/bin/clang-format; then + printf "error: could not find clang-format in llvm-project/build/bin directory\n" >&2 + exit 1 +fi + +cd "$(git rev-parse --show-toplevel)/amd/comgr" + +if [ ! -e compile_commands.json ]; then + printf "error: compile_commands.json database missing\n" >&2 + printf " hint: enable with -DCMAKE_EXPORT_COMPILE_COMMANDS=On and then symlink into the amd/comgr directory:\n" >&2 + printf " amd/comgr/build$ cmake ... -DCMAKE_EXPORT_COMPILE_COMMANDS=On ... && make && cd ..\n" >&2 + printf " amd/comgr$ ln -s build/compile_commands.json .\n" >&2 + exit 1 +fi + +../../clang-tools-extra/clang-tidy/tool/run-clang-tidy.py -fix -checks=-*,readability-identifier-naming,llvm-else-after-return,llvm-qualified-auto,llvm-namespace-comment,misc-unused-using-decls,misc-use-anonymous-namespace 2>&1 | grep -Ev 'Suppressed|header-filter|warnings generated|clang-tidy|^$' + +# FIXME: Drive this off of compile_commands.json +find src/ test/ -type f -regex '.*\.\(c\|cpp\|h\|hpp\|cl\)$' -print0 \ + | xargs -0 ../../build/bin/clang-format -i diff --git a/amd/device-libs/.clang-format b/amd/device-libs/.clang-format new file mode 100644 index 0000000000000..de830ec83978c --- /dev/null +++ b/amd/device-libs/.clang-format @@ -0,0 +1,6 @@ +AlwaysBreakAfterReturnType: All +BraceWrapping: + AfterFunction: true +BreakBeforeBraces: Custom +IndentWidth: 4 +PenaltyBreakBeforeFirstCallParameter: 300 diff --git a/amd/device-libs/.gitignore b/amd/device-libs/.gitignore new file mode 100644 index 0000000000000..796b96d1c4023 --- /dev/null +++ b/amd/device-libs/.gitignore @@ -0,0 +1 @@ +/build diff --git a/amd/device-libs/AMDDeviceLibsConfig.cmake.in b/amd/device-libs/AMDDeviceLibsConfig.cmake.in new file mode 100644 index 0000000000000..3a86012f40617 --- /dev/null +++ b/amd/device-libs/AMDDeviceLibsConfig.cmake.in @@ -0,0 +1,17 @@ +if(COMMAND include_guard) + include_guard(DIRECTORY) +else() +string(MAKE_C_IDENTIFIER "${CMAKE_CURRENT_LIST_FILE}" _PACKAGE_ID) +if(DEFINED ${_GUARD_FILE_${_PACKAGE_ID}}) + return() +endif() +set(${_GUARD_FILE_${_PACKAGE_ID}} On) +endif() + +@AMD_DEVICE_LIBS_PREFIX_CODE@ +@AMD_DEVICE_LIBS_TARGET_CODE@ + +set_property(GLOBAL PROPERTY AMD_DEVICE_LIBS "@AMDGCN_LIB_LIST@") + +# List of exported target names. +set(AMD_DEVICE_LIBS_TARGETS "@AMDGCN_LIB_LIST@") diff --git a/amd/device-libs/CMakeLists.txt b/amd/device-libs/CMakeLists.txt new file mode 100644 index 0000000000000..0de5222a4a282 --- /dev/null +++ b/amd/device-libs/CMakeLists.txt @@ -0,0 +1,158 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +cmake_minimum_required(VERSION 3.13.4) + +project(rocm-device-libs VERSION "1.0.0") +cmake_policy(SET CMP0011 NEW) + +if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) + include(CMakePackageConfigHelpers) + include(GNUInstallDirs) + + find_package(ROCmCMakeBuildTools) + if (ROCM_FOUND) + include(ROCMSetupVersion) + rocm_setup_version(VERSION "${PROJECT_VERSION}") + endif() +endif() + +list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake") + +add_custom_target(rocm-device-libs) + +# Optionally, build Device Libs with ccache. +set(ROCM_CCACHE_BUILD OFF CACHE BOOL "Set to ON for a ccache enabled build") +if (ROCM_CCACHE_BUILD) + find_program(CCACHE_PROGRAM ccache) + if (CCACHE_PROGRAM) + set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE ${CCACHE_PROGRAM}) + else() + message(WARNING "Unable to find ccache. Falling back to real compiler") + endif() # if (CCACHE_PROGRAM) +endif() # if (ROCM_CCACHE_BUILD) + +if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) + find_package(LLVM REQUIRED) + find_package(Clang HINTS ${LLVM_DIR}/../clang) + + list(APPEND CMAKE_MODULE_PATH ${LLVM_DIR}) + + if(CMAKE_INSTALL_PREFIX_INITIALIZED_TO_DEFAULT) + set(CMAKE_INSTALL_PREFIX ${CMAKE_BINARY_DIR}/dist CACHE INTERNAL "Prefix prepended to install directories") + endif() + + set(ROCM_DEVICELIB_STANDALONE_BUILD ON) +endif(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) + + +if (NOT DEFINED AMDGPU_TARGET_TRIPLE) + set(AMDGPU_TARGET_TRIPLE "amdgcn-amd-amdhsa") +endif() + +if (NOT PREPARE_BUILTINS) + add_subdirectory(utils/prepare-builtins) + set (PREPARE_BUILTINS $) +endif() + +# Following variables are required for ROCM backwards compatibility, +# and should be removed in ROCM 7.0 release. +set(ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_NEW "" CACHE STRING "New bitcode install location relative to CMAKE_INSTALL_PREFIX") +set(ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_OLD "" CACHE STRING "Old bitcode install location relative to CMAKE_INSTALL_PREFIX") + +include(OCL) + +if (NOT ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_NEW STREQUAL "" AND + NOT ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_OLD STREQUAL "") + set(ROCM_DEVICE_LIBS_WRAPPER_DIR ${CMAKE_CURRENT_BINARY_DIR}/wrapper_dir) + file(MAKE_DIRECTORY ${ROCM_DEVICE_LIBS_WRAPPER_DIR}) + add_custom_target( + FILE_REORG_ROCM_6_0 ALL + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + COMMAND ${CMAKE_COMMAND} -E create_symlink + ${ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_NEW} + ${ROCM_DEVICE_LIBS_WRAPPER_DIR}/${ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_OLD}) + install( + FILES ${ROCM_DEVICE_LIBS_WRAPPER_DIR}/${ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_OLD} + DESTINATION .) +endif() + +set(AMDGCN_LIB_LIST) +set(AMDGCN_DEP_LIST) +add_subdirectory(oclc) +add_subdirectory(ocml) +add_subdirectory(ockl) +add_subdirectory(opencl) +add_subdirectory(hip) +add_subdirectory(asanrtl) + +enable_testing() +add_subdirectory(test/compile) + +include(Packages) + +if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) + ## CPack standard variables + set ( CPACK_PACKAGE_NAME "rocm-device-libs" ) + set ( CPACK_PACKAGE_VERSION_MAJOR "${PROJECT_VERSION_MAJOR}" ) + set ( CPACK_PACKAGE_VERSION_MINOR "${PROJECT_VERSION_MINOR}" ) + set ( CPACK_PACKAGE_VERSION_PATCH "${PROJECT_VERSION_PATCH}" ) + set ( CPACK_PACKAGE_VERSION "${PROJECT_VERSION}" ) + set ( CPACK_PACKAGE_CONTACT "Advanced Micro Devices Inc." ) + set ( CPACK_PACKAGE_DESCRIPTION_SUMMARY "Radeon Open Compute - device libraries" ) + set ( CPACK_PACKAGE_DESCRIPTION "This package includes LLVM bitcode libraries." ) + set ( CPACK_RESOURCE_FILE_LICENSE "${CMAKE_CURRENT_SOURCE_DIR}/LICENSE.TXT" ) + set ( CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/ROCm/llvm-project/tree/amd-staging/amd/device-libs" ) + + # Install License file + install ( FILES "${CPACK_RESOURCE_FILE_LICENSE}" + DESTINATION ${CMAKE_INSTALL_DATADIR}/doc/${CPACK_PACKAGE_NAME}) + + set ( CPACK_GENERATOR "DEB;RPM" CACHE STRING "Default packaging generators." ) + + ## ROCM version updates as per naming convention + set ( ROCM_VERSION_FOR_PACKAGE "99999" ) + if( DEFINED ENV{ROCM_LIBPATCH_VERSION} ) + set ( ROCM_VERSION_FOR_PACKAGE $ENV{ROCM_LIBPATCH_VERSION} ) + endif() + ## Debian package values + set ( CPACK_DEBIAN_PACKAGE_MAINTAINER "ROCm Compiler Support " ) + + set ( CPACK_DEBIAN_PACKAGE_RELEASE "local" ) + if( DEFINED ENV{CPACK_DEBIAN_PACKAGE_RELEASE} ) + set ( CPACK_DEBIAN_PACKAGE_RELEASE $ENV{CPACK_DEBIAN_PACKAGE_RELEASE} ) + endif() + ## RPM package variables + set ( CPACK_RPM_PACKAGE_RELEASE "local" ) + if( DEFINED ENV{CPACK_RPM_PACKAGE_RELEASE} ) + set ( CPACK_RPM_PACKAGE_RELEASE $ENV{CPACK_RPM_PACKAGE_RELEASE} ) + endif() + ## get distro for RPM package using dist + message("device-libs CPACK_RPM_PACKAGE_RELEASE now is ${CPACK_RPM_PACKAGE_RELEASE}") + set( CPACK_RPM_PACKAGE_LICENSE "NCSA" ) + + execute_process( COMMAND rpm --eval %{?dist} + RESULT_VARIABLE _result_var + OUTPUT_VARIABLE _output_var + OUTPUT_STRIP_TRAILING_WHITESPACE ) + if( _result_var EQUAL "0" AND NOT _output_var STREQUAL "" ) + string (APPEND CPACK_RPM_PACKAGE_RELEASE ${_output_var}) + endif() + # set package name as per standard + set ( CPACK_PACKAGE_VERSION "${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}.${ROCM_VERSION_FOR_PACKAGE}" ) + + set ( CPACK_RPM_FILE_NAME "RPM-DEFAULT" ) + set ( CPACK_RPM_PACKAGE_REQUIRES "rocm-core" ) + set ( CPACK_DEBIAN_FILE_NAME "DEB-DEFAULT" ) + set ( CPACK_DEBIAN_PACKAGE_DEPENDS "rocm-core" ) + # Remove dependency on rocm-core if -DROCM_DEP_ROCMCORE=ON not given to cmake + if(NOT ROCM_DEP_ROCMCORE) + string(REGEX REPLACE ",? ?rocm-core" "" CPACK_RPM_PACKAGE_REQUIRES ${CPACK_RPM_PACKAGE_REQUIRES}) + string(REGEX REPLACE ",? ?rocm-core" "" CPACK_DEBIAN_PACKAGE_DEPENDS ${CPACK_DEBIAN_PACKAGE_DEPENDS}) + endif() + include( CPack ) +endif() diff --git a/amd/device-libs/LICENSE.TXT b/amd/device-libs/LICENSE.TXT new file mode 100644 index 0000000000000..bcfb226f486b6 --- /dev/null +++ b/amd/device-libs/LICENSE.TXT @@ -0,0 +1,43 @@ +============================================================================== +ROCm-Device-Libs Release License +============================================================================== +University of Illinois/NCSA +Open Source License + +Copyright (c) 2014-2016, Advanced Micro Devices, Inc. +All rights reserved. + +Developed by: + + AMD Research and AMD HSA Software Development + + Advanced Micro Devices, Inc. + + www.amd.com + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal with +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +of the Software, and to permit persons to whom the Software is furnished to do +so, subject to the following conditions: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimers. + + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimers in the + documentation and/or other materials provided with the distribution. + + * Neither the names of the LLVM Team, University of Illinois at + Urbana-Champaign, nor the names of its contributors may be used to + endorse or promote products derived from this Software without specific + prior written permission. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE +SOFTWARE. diff --git a/amd/device-libs/README.md b/amd/device-libs/README.md new file mode 100644 index 0000000000000..83c393e94352f --- /dev/null +++ b/amd/device-libs/README.md @@ -0,0 +1,107 @@ +## OVERVIEW + +ROCm Device libraries. + +This subdirectory contains the sources and CMake build system for a +set of AMD specific device-side language runtime libraries. Specifically: + +| **Name** | **Comments** | **Dependencies** | +| --- | --- | --- | +| oclc* | Open Compute library controls ([documentation](doc/OCML.md#controls)) | | +| ocml | Open Compute Math library ([documentation](doc/OCML.md)) | oclc* | +| ockl | Open Compute Kernel library ([documentation](doc/OCKL.md)) | oclc* | +| opencl | OpenCL built-in library | ocml, ockl, oclc* | +| hip | HIP built-in library | ocml, ockl, oclc* | +| hc | Heterogeneous Compute built-in library | ocml, ockl, oclc* | + +Refer to [LICENSE.TXT](LICENSE.TXT) for license information. + +## BUILDING + +The build requires clang and several llvm development tools. These tools can +be built using the amd-staging branch of https://github.com/ROCm/llvm-project +where this subdirectory now lives. Using dev tools build from upstream +llvm-project ( https://github.com/llvm/llvm-project/ ) should also work. + +There are two different methods to build the device libraries: as a +standalone project or as an llvm external subproject. + +For a standalone build, this will find preexisting clang and llvm +tools using the standard cmake search mechanisms. If you wish to use a +specific build, you can specify this with the CMAKE_PREFIX_PATH +variable: + + git clone https://github.com/ROCm/llvm-project.git -b amd-staging + cd llvm-project/amd/device-libs + +Then run the following commands: + + mkdir -p build + cd build + export LLVM_BUILD=... (path to LLVM build directory created previously) + cmake -DCMAKE_PREFIX_PATH=$LLVM_BUILD .. + make + +To build as an llvm external project: + + LLVM_PROJECT_ROOT=llvm-project-rocm + git clone https://github.com/ROCm/llvm-project.git -b amd-staging ${LLVM_PROJECT_ROOT} + cd ${LLVM_PROJECT_ROOT} + mkdir -p build + cd build + + cmake ${LLVM_PROJECT_ROOT}/llvm -DCMAKE_BUILD_TYPE=Release \ + -DLLVM_ENABLE_PROJECTS="clang;lld" \ + -DLLVM_EXTERNAL_PROJECTS="device-libs" \ + -DLLVM_EXTERNAL_DEVICE_LIBS_SOURCE_DIR=/path/to/ROCm-Device-Libs + +Testing requires the amdhsacod utility from ROCm Runtime. + +To install artifacts: + make install + +To create packages for the library: + make package + +## USING BITCODE LIBRARIES + +The ROCm compilers and runtimes automatically link the +required bitcode files invoked during the process of creating a code +object. clang will search for these libraries by default when +targeting amdhsa, in the default ROCm install location. To specify a +specific set of libraries, the --rocm-path argument can point to the +root directory where the bitcode libraries are installed, which is the +recommended way to link the libraries. + + $LLVM_BUILD/bin/clang -x cl -Xclang -finclude-default-header \ + -target amdgcn-amd-amdhsa -mcpu=gfx900 \ + --rocm-path=/srv/git/ROCm-Device-Libs/build/dist + +These can be manually linked, but is generally not recommended. The +set of libraries linked should be in sync with the corresponding +compiler flags and target options. The default library linking can be +disabled with -nogpulib, and a manual linking invocation might look +like as follows: + + $LLVM_BUILD/bin/clang -x cl -Xclang -finclude-default-header \ + -nogpulib -target amdgcn-amd-amdhsa -mcpu=gfx900 \ + -Xclang -mlink-bitcode-file -Xclang /srv/git/ROCm-Device-Libs/build/dist/amdgcn/bitcode/opencl/opencl.bc \ + -Xclang -mlink-bitcode-file -Xclang /srv/git/ROCm-Device-Libs/build/dist/amdgcn/bitcode/ocml/ocml.bc \ + -Xclang -mlink-bitcode-file -Xclang /srv/git/ROCm-Device-Libs/build/dist/amdgcn/bitcode/ockl/ockl.bc \ + -Xclang -mlink-bitcode-file -Xclang /srv/git/ROCm-Device-Libs/build/dist/amdgcn/bitcode/oclc/oclc_correctly_rounded_sqrt_off.bc \ + -Xclang -mlink-bitcode-file -Xclang /srv/git/ROCm-Device-Libs/build/dist/amdgcn/bitcode/oclc/oclc_finite_only_off.bc \ + -Xclang -mlink-bitcode-file -Xclang /srv/git/ROCm-Device-Libs/build/dist/amdgcn/bitcode/oclc/oclc_unsafe_math_off.bc \ + -Xclang -mlink-bitcode-file -Xclang /srv/git/ROCm-Device-Libs/build/dist/amdgcn/bitcode/oclc/oclc_wavefrontsize64_on.bc \ + -Xclang -mlink-bitcode-file -Xclang /srv/git/ROCm-Device-Libs/build/dist/amdgcn/bitcode/oclc/oclc_isa_version_900.bc \ + test.cl -o test.so + +### USING FROM CMAKE + +The bitcode libraries are exported as CMake targets, organized in a CMake +package. You can depend on this package using +`find_package(AMDDeviceLibs REQUIRED CONFIG)` after ensuring the +`CMAKE_PREFIX_PATH` includes either the build directory or install prefix of +the bitcode libraries. The package defines a variable +`AMD_DEVICE_LIBS_TARGETS` containing a list of the exported CMake +targets. + diff --git a/amd/device-libs/asanrtl/CMakeLists.txt b/amd/device-libs/asanrtl/CMakeLists.txt new file mode 100644 index 0000000000000..f1ed0205348f4 --- /dev/null +++ b/amd/device-libs/asanrtl/CMakeLists.txt @@ -0,0 +1,18 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +file(GLOB sources + ${CMAKE_CURRENT_SOURCE_DIR}/src/*.cl +) + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../irif/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../oclc/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../ockl/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/src) + +opencl_bc_lib(NAME asanrtl SOURCES ${sources}) diff --git a/amd/device-libs/asanrtl/inc/asan_util.h b/amd/device-libs/asanrtl/inc/asan_util.h new file mode 100644 index 0000000000000..7f6627af01dce --- /dev/null +++ b/amd/device-libs/asanrtl/inc/asan_util.h @@ -0,0 +1,63 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma once +#include "ockl.h" + +typedef ulong uptr; +typedef unsigned char u8; +typedef signed char s8; +typedef unsigned short u16; +typedef short s16; +typedef unsigned long u64; + +#define ASAN_SHADOW 3 + +#define SHADOW_GRANULARITY (1ULL << ASAN_SHADOW) + +#define CALL_BYTES 4 +#define GET_CALLER_PC() ((uptr)__builtin_return_address(0) - CALL_BYTES) + +#define WORKGROUP_ID(dim) __builtin_amdgcn_workgroup_id_##dim() + +#define USED __attribute__((used)) + +#define NO_INLINE __attribute__((noinline)) + +#define NO_SANITIZE_ADDR __attribute__((no_sanitize("address"))) + +#define REPORT_IMPL(caller_pc, addr, is_write, size, no_abort) \ + uptr read = is_write; \ + if (no_abort) \ + read |= 0xFFFFFFFF00000000; \ + \ + __ockl_sanitizer_report(addr, caller_pc, WORKGROUP_ID(x), WORKGROUP_ID(y), \ + WORKGROUP_ID(z), __ockl_get_local_linear_id(), \ + read, size); + +NO_SANITIZE_ADDR +static bool +is_aligned_by_granularity(uptr addr) +{ + return (addr & (SHADOW_GRANULARITY - 1)) == 0; +} + +// round up size to the nearest multiple of boundary. +NO_SANITIZE_ADDR +static uptr +round_upto(uptr size, uptr boundary) +{ + return (size + boundary - 1) & ~(boundary - 1); +} + +// round down size to the nearest multiple of boundary. +NO_SANITIZE_ADDR +static uptr +round_downto(uptr size, uptr boundary) +{ + return size & ~(boundary - 1); +} diff --git a/amd/device-libs/asanrtl/inc/globals.h b/amd/device-libs/asanrtl/inc/globals.h new file mode 100644 index 0000000000000..8130b07d50147 --- /dev/null +++ b/amd/device-libs/asanrtl/inc/globals.h @@ -0,0 +1,37 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma once +#include "asan_util.h" + +// The strucutures semantics and layout must match the host instrumented +// global variable as defined in +// llvm-project/compiler-rt/lib/asan/asan_interface_internal.h + +// This structure used to describe the source location of a place +// where global was defined. +struct global_source_location { + const char *filename; + int line_no; + int column_no; +}; + +// This structure describes an instrumented global variable. +struct device_global { + uptr beg; // The address of the global. + uptr size; // The original size of the global. + uptr size_with_redzone; // The size with the redzone. + const char *name; // Name as a C string. + const char *module_name; // Module name as a C string. This pointer is a + // unique identifier of a module. + uptr has_dynamic_init; // Non-zero if the global has dynamic initializer. + struct global_source_location *location; // Source location of a global, + // or NULL if it is unknown. + uptr odr_indicator; // The address of the ODR indicator symbol. +}; + +static const __constant s8 kAsanGlobalRedzoneMagic = 0xf9; diff --git a/amd/device-libs/asanrtl/inc/shadow_mapping.h b/amd/device-libs/asanrtl/inc/shadow_mapping.h new file mode 100644 index 0000000000000..67fe4e98e5d94 --- /dev/null +++ b/amd/device-libs/asanrtl/inc/shadow_mapping.h @@ -0,0 +1,35 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma once +#include "asan_util.h" + +//offset from llvm/compiler-rt/lib/asan/asan_mapping.h +static const u64 kh_Linux64bit_ShadowOffset = + 0x7FFFFFFF & (~0xFFFULL << ASAN_SHADOW); + +#define MEM_TO_SHADOW(mem_addr) (((mem_addr) >> ASAN_SHADOW) + kh_Linux64bit_ShadowOffset) + +// Addresses are atleast SHADOW_GRANULARITY aligned. +// True, when given byte is accessible false otherwise. +NO_SANITIZE_ADDR +static bool +is_address_poisoned(uptr addr) +{ + uptr shadow_addr = MEM_TO_SHADOW(addr); + s8 shadow_value = *(__global s8 *)shadow_addr; + if (shadow_value) { + //compute index of the given address within 8-byte range + return (s8)(addr & (SHADOW_GRANULARITY - 1)) >= shadow_value; + } + return false; +} + +USED +NO_SANITIZE_ADDR +uptr +__asan_region_is_poisoned(uptr beg, uptr size); diff --git a/amd/device-libs/asanrtl/src/cxxa.cl b/amd/device-libs/asanrtl/src/cxxa.cl new file mode 100644 index 0000000000000..9e650244332c6 --- /dev/null +++ b/amd/device-libs/asanrtl/src/cxxa.cl @@ -0,0 +1,35 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "asan_util.h" +#include "shadow_mapping.h" + +static const __constant u8 kAsanArrayCookieMagic = (u8)0xac; +static const __constant u8 kAsanHeapFreeMagic = (u8)0xfd; + +USED NO_SANITIZE_ADDR +void +__asan_poison_cxx_array_cookie(uptr a) { + __global u8 *sa = (__global u8 *)MEM_TO_SHADOW(a); + *sa = kAsanArrayCookieMagic; +} + +USED NO_INLINE NO_SANITIZE_ADDR +uptr +__asan_load_cxx_array_cookie(uptr a) { + uptr pc = GET_CALLER_PC(); + __global u8 *sa = (__global u8 *)MEM_TO_SHADOW(a); + u8 sv = *sa; + if (sv == kAsanArrayCookieMagic) + return *(__global uptr *)a; + if (sv == kAsanHeapFreeMagic) { + REPORT_IMPL(pc, a, 0, 1, false); + return 0; + } + return *(__global uptr *)a; +} + diff --git a/amd/device-libs/asanrtl/src/dm.cl b/amd/device-libs/asanrtl/src/dm.cl new file mode 100644 index 0000000000000..5cf226588023e --- /dev/null +++ b/amd/device-libs/asanrtl/src/dm.cl @@ -0,0 +1,674 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "asan_util.h" +#include "shadow_mapping.h" + +#define OPTNONE __attribute__((optnone)) + +static const __constant uchar kAsanHeapLeftRedzoneMagic = (uchar)0xfa; +static const __constant uint kAsanHeapLeftRedzoneMagicx4 = 0xfafafafaU; +static const __constant ulong kAsanHeapLeftRedzoneMagicx8 = 0xfafafafafafafafaUL; +static const __constant uchar kAsanHeapFreeMagic = (uchar)0xfd; +static const __constant uchar kAsanArrayCookieMagic = (uchar)0xac; + +extern ulong __ockl_devmem_request(ulong addr, ulong size); + +// Whether we track non-slab allocations +#define NON_SLAB_TRACKING 1 + +// Whether we add ID to slabs +#define SLAB_IDENTITY 1 + +// Magic at beginning of allocation +#define ALLOC_MAGIC 0xfedcba1ee1abcdefUL + +#define AS(P,V) __opencl_atomic_store(P, V, memory_order_relaxed, memory_scope_device) +#define AL(P) __opencl_atomic_load(P, memory_order_relaxed, memory_scope_device) +#define AA(P,V) __opencl_atomic_fetch_add(P, V, memory_order_relaxed, memory_scope_device) +#define AN(P,V) __opencl_atomic_fetch_and(P, V, memory_order_relaxed, memory_scope_device) +#define AO(P,V) __opencl_atomic_fetch_or(P, V, memory_order_relaxed, memory_scope_device) +#define ACE(P,E,V) __opencl_atomic_compare_exchange_strong(P, E, V, memory_order_relaxed, memory_order_relaxed, memory_scope_device) +#define RF() __builtin_amdgcn_fence(__ATOMIC_RELEASE, "agent", "global") +#define ARF() __builtin_amdgcn_fence(__ATOMIC_ACQ_REL, "agent", "global") + +// An allocation +#define ALLOC_HEADER_BYTES 32 +typedef struct alloc_struct { + ulong magic; // Assist with memory scan for header + ulong sp; // slab pointer, 0 if non-slab allocation + ulong pc; // We can only collect PC currently, callstack ID later + uint asz; // Total number of bytes including header, redzone, and round, multiple of 16 + uint usz; // user specificed size + ulong ret[]; // Address returned by malloc, always 16-byte aligned +} alloc_t; + +// Assumes 4096 byte minimum alignment of slab +#define SLAB_ALIGN 4096 +#define SLAB_BUSY ((__global slab_t *)1UL) +#define SLAB_TICKS 100000 +#define SLAB_BYTES (1UL << 21) +#define SLAB_THRESHOLD (SLAB_BYTES / 64) +#define SLAB_HEADER_BYTES 32 + +// Assume SLAB_ALIGN so low 12 bits are already clear +#define SLAB_SHIFT 6 +#define SLAB_CTR_MASK ((1UL << (SLAB_SHIFT+12)) - 1UL) + +#define LINE 128 +#define PAD(N,M) ulong pad##N[LINE/8 - M]; + +#define F_POISON_NEEDED 0x01 +#define F_POISON_PENDING 0x02 +#define F_UNREADY 0x04 +#define F_MASK (F_POISON_NEEDED | F_POISON_PENDING | F_UNREADY) + +// A slab of memory used to provide malloc returned blocks +typedef struct slab_s { + atomic_ulong next; // link to next slab on queue chain, must be first + atomic_ulong ap; // Pointer to next allocation and flags + atomic_uint rb; // returned bytes + uint pad; + atomic_ulong sid; // slab ID + ulong space[(SLAB_BYTES-SLAB_HEADER_BYTES)/8]; // Space for allocations. Must be aligned 16 +} slab_t; + +// A LIFO for storing available slabs +typedef struct lifo_s { + atomic_ulong top; + PAD(0,1); +} lifo_t; + +// Number of LIFO we use, need to size to keep heap_s under 128K +// Current initialization must change if this exceeds 256 +#define NLA 256 +#define LP(H,I) (H->la + (I) % NLA) + +// State for mechanism +typedef struct heap_s { + atomic_ulong cs; // current slab pointer + PAD(0,1); + atomic_ulong atime; // Time most recent allocation started + PAD(1,1); + atomic_ulong rid; // Next read index + PAD(2,1); + atomic_ulong wid; // Next write index + PAD(3,1); + atomic_ulong initial_slabs; // pointer to next preallocated slab + ulong initial_slabs_end; // pointer to end of preallocated slabs + PAD(4,2); +#if defined NON_SLAB_TRACKING + atomic_ulong num_nonslab_allocations; // Count of number of non-slab allocations that have not been freed + PAD(5,1); +#endif +#if defined SLAB_IDENTITY + atomic_ulong num_slab_allocations; // Count of total slabs allocated + PAD(6,1); +#endif + lifo_t la[NLA]; // Storage for available slabs +} heap_t; + +// Overloads to broadcast the value held by the first active lane +// The result is known to be wave-uniform +static __attribute__((overloadable)) uint +first(uint v) +{ + return __builtin_amdgcn_readfirstlane(v); +} + +static __attribute__((overloadable)) ulong +first(ulong v) +{ + uint2 v2 = __builtin_astype(v, uint2); + uint2 w2; + w2.x = __builtin_amdgcn_readfirstlane(v2.x); + w2.y = __builtin_amdgcn_readfirstlane(v2.y); + return __builtin_astype(w2, ulong); +} + +static __attribute__((overloadable)) __global void * +first(__global void * v) +{ + uint2 v2 = __builtin_astype(v, uint2); + uint2 w2; + w2.x = __builtin_amdgcn_readfirstlane(v2.x); + w2.y = __builtin_amdgcn_readfirstlane(v2.y); + return __builtin_astype(w2, __global void *); +} + +// The number of active lanes at this point +static uint +active_lane_count(void) +{ + return __builtin_popcountl(__builtin_amdgcn_ballot_w64(true)); +} + +static ulong +round_16(ulong n) +{ + return ((n + 15) >> 4) << 4; +} + +static ulong +addcnt(ulong p, ulong c) +{ + return (p << SLAB_SHIFT) | ((c + 1UL) & SLAB_CTR_MASK); +} + +static __global slab_t * +slabptr(ulong p) +{ + return (__global slab_t *)((p & ~SLAB_CTR_MASK) >> SLAB_SHIFT); +} + +NO_SANITIZE_ADDR +static __global heap_t * +get_heap_ptr(void) { + if (__oclc_ABI_version < 500) { + static __attribute__((aligned(4096))) __global heap_t heap; + return &heap; + } else { + return (__global heap_t *)((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[12]; + } +} + +// Size of additional left redzone, roughly assumes 32 byte header, multiple of 16 +static uint +added_redzone(uint sz) +{ + return sz < 128 ? 0 : + sz < 512 ? 96 : + sz < 2048 ? 224 : + sz < 8192 ? 992 : 2016; +} + +// Called by a single workitem +static void +slab_pause(void) +{ + __builtin_amdgcn_s_sleep(9); +} + + +// Intended to be called from only one lane of a wave +OPTNONE +NO_SANITIZE_ADDR +static void +put_free_slab(__global heap_t *hp, __global slab_t *sp) +{ + __global lifo_t *lp = LP(hp, AA(&hp->wid, 1UL)); + + for (;;) { + ulong top = AL(&lp->top); + AS(&sp->next, (ulong)slabptr(top)); + if (ACE(&lp->top, &top, addcnt((ulong)sp, top))) { + return; + } + slab_pause(); + } +} + +// Intended to be called from only one lane of a wave +NO_SANITIZE_ADDR +static __global slab_t * +get_free_slab(__global heap_t *hp) +{ + if (AL(&hp->rid) >= AL(&hp->wid)) + return 0; + + __global lifo_t *lp = LP(hp, AA(&hp->rid, 1UL)); + + for (;;) { + ulong top = AL(&lp->top); + __global slab_t *sp = slabptr(top); + if (sp) { + ulong next = AL(&sp->next); + if (ACE(&lp->top, &top, addcnt(next, top))) + return sp; + } else { + return 0; + } + slab_pause(); + } + +} + +NO_SANITIZE_ADDR +static void +ready_slab(__global slab_t *sp) +{ + AS(&sp->rb, 0U); + if (!(AL(&sp->ap) & (ulong)(F_POISON_PENDING | F_POISON_NEEDED))) { + AS(&sp->ap, (ulong)sp + SLAB_HEADER_BYTES); + } else { + AN(&sp->ap, ~(ulong)F_UNREADY); + } +} + +NO_SANITIZE_ADDR +static void +unpublish_allocation(__global alloc_t *ap, ulong pc) +{ + uint arz = ap->asz - ALLOC_HEADER_BYTES - round_16(ap->usz); + __global uchar *s = (__global uchar *)MEM_TO_SHADOW((ulong)ap - arz); + __builtin_memset(s, kAsanHeapFreeMagic, ap->asz / SHADOW_GRANULARITY); + ap->pc = pc; +} + +// Free a slab based allocation +NO_SANITIZE_ADDR +static void +slab_free(__global alloc_t *ap, ulong pc) +{ + unpublish_allocation(ap, pc); + __global heap_t *hp = get_heap_ptr(); + __global slab_t *sp = (__global slab_t *)ap->sp; + + int go = 1; + do { + if (go) { + if (sp == first(sp)) { + uint sz = __ockl_alisa_u32(ap->asz); + uint aid = __ockl_activelane_u32(); + if (aid == 0) { + uint rb = AA(&sp->rb, sz) + sz; + if (rb == SLAB_BYTES - SLAB_HEADER_BYTES) { + put_free_slab(hp, sp); + } + } + go = 0; + } + } + } while (__ockl_wfany_i32(go)); +} + +// Free a non-slab allocation +NO_SANITIZE_ADDR +static void +non_slab_free(__global alloc_t *ap, ulong pc) +{ + ap->pc = pc; + __ockl_devmem_request((ulong)ap, 0); + +#if defined NON_SLAB_TRACKING + uint aid = __ockl_activelane_u32(); + uint nactive = active_lane_count(); + + if (aid == 0) { + __global heap_t *hp = get_heap_ptr(); + AA(&hp->num_nonslab_allocations, -nactive); + } +#endif +} + +// free +USED +NO_INLINE +NO_SANITIZE_ADDR +void +__asan_free_impl(ulong aa, ulong pc) +{ + if (!aa) + return; + + pc -= CALL_BYTES; + + ARF(); + + uptr sa = MEM_TO_SHADOW(aa); + s8 sb = *(__global s8*) sa; + if (sb != 0 && sb != (s8)kAsanArrayCookieMagic && ((s8)(aa & (SHADOW_GRANULARITY-1)) >= sb)) { + REPORT_IMPL(pc, aa, 1, 1, false); + } + + __global alloc_t *ap = (__global alloc_t *)(aa - ALLOC_HEADER_BYTES); + if (ap->sp) + slab_free(ap, pc); + else + non_slab_free(ap, pc); + + ARF(); +} + +// Non-slab based allocation (when size is above threshold) +NO_SANITIZE_ADDR +static ulong +non_slab_malloc(ulong sz, ulong pc) +{ + ulong ret = __ockl_devmem_request(0UL, sz + ALLOC_HEADER_BYTES); + if (ret) { +#if defined NON_SLAB_TRACKING + uint aid = __ockl_activelane_u32(); + uint nactive = active_lane_count(); + + if (aid == 0) { + __global heap_t *hp = get_heap_ptr(); + AA(&hp->num_nonslab_allocations, nactive); + } +#endif + +#if SLAB_HEADER_BYTES == 32 + __global uint *asp = (__global uint *)MEM_TO_SHADOW(ret); + *asp = kAsanHeapLeftRedzoneMagicx4; +#else +#error unimplemented poisoning +#endif + + __global alloc_t *ap = (__global alloc_t *)ret; + ap->magic = ALLOC_MAGIC; + ap->sp = 0UL; + ap->pc = pc; + ap->asz = (uint)(sz + ALLOC_HEADER_BYTES); + ap->usz = (uint)sz; + ret += ALLOC_HEADER_BYTES; + } + return ret; +} + +// Called by a single workitem +NO_SANITIZE_ADDR +static __global slab_t * +obtain_new_slab(__global heap_t *hp) +{ + ulong ret = 0; + + ulong is = AL(&hp->initial_slabs); + ulong se = hp->initial_slabs_end; + if (is < se) { + is = AA(&hp->initial_slabs, SLAB_BYTES); + if (is < se) + ret = is; + } else { + ret = __ockl_devmem_request(0, SLAB_BYTES); + } + + return (__global slab_t *)ret; +} + +// Called by a single workitem +NO_SANITIZE_ADDR +static __global slab_t * +try_new_slab(__global heap_t *hp) +{ + ulong atime = AL(&hp->atime); + ulong now = __ockl_steadyctr_u64(); + ulong dt = now - atime; + if (dt < SLAB_TICKS || !ACE(&hp->atime, &atime, now)) + return SLAB_BUSY; + + __global slab_t *sp = obtain_new_slab(hp); + if (sp) { + AS(&sp->next, 0UL); + AS(&sp->rb, 0U); + AS(&sp->ap, (ulong)sp + (ulong)SLAB_HEADER_BYTES + (ulong)(F_UNREADY | F_POISON_PENDING | F_POISON_NEEDED)); +#if defined SLAB_IDENTITY + AS(&sp->sid, AA(&hp->num_slab_allocations, 1UL)); +#else + AS(&sp->sid, 0UL); +#endif + } + return sp; +} + +// Called by a single workitem +NO_SANITIZE_ADDR +static void +new_slab_wait(__global heap_t *hp) +{ + ulong atime = AL(&hp->atime); + ulong now = __ockl_steadyctr_u64(); + ulong dt = now - atime; + if (dt < SLAB_TICKS) + __ockl_rtcwait_u32(SLAB_TICKS - (uint)dt); +} + +// Called by a single workitem +OPTNONE +NO_SANITIZE_ADDR +static __global slab_t * +get_current_slab(__global heap_t *hp) +{ + for (;;) { + ulong cs = AL(&hp->cs); + if (cs) + return (__global slab_t *)cs; + + slab_pause(); + + cs = AL(&hp->cs); + if (cs) + return (__global slab_t *)cs; + + slab_pause(); + + cs = AL(&hp->cs); + if (cs) + return (__global slab_t *)cs; + + __global slab_t *fs = get_free_slab(hp); + if (fs) { + if (ACE(&hp->cs, &cs, (ulong)fs)) { + ready_slab(fs); + return fs; + } + put_free_slab(hp, fs); + continue; + } + + __global slab_t *ns = try_new_slab(hp); + if ((ulong)ns > (ulong)SLAB_BUSY) { + if (ACE(&hp->cs, &cs, (ulong)ns)) { + AN(&ns->ap, ~(ulong)F_UNREADY); + return ns; + } + put_free_slab(hp, ns); + continue; + } + + if (!ns) + return 0; + + new_slab_wait(hp); + } +} + +NO_SANITIZE_ADDR +static void +poison_slab(__global slab_t *sp, int aid, int na) +{ + __global ulong *ssp = (__global ulong *)MEM_TO_SHADOW((ulong)sp); + + for (int i=aid; i < SLAB_BYTES / SHADOW_GRANULARITY / sizeof(ulong); i += na) + ssp[i] = kAsanHeapLeftRedzoneMagicx8; + RF(); + + if (!aid) + AN(&sp->ap, ~(ulong)F_POISON_PENDING); +} + +NO_SANITIZE_ADDR +static ulong +publish_allocation(ulong ap, ulong sp, ulong pc, uint asz, uint arz, uint usz) +{ + __global uchar *s = (__global uchar *)MEM_TO_SHADOW(ap); + + __builtin_memset(s, kAsanHeapLeftRedzoneMagic, (arz + ALLOC_HEADER_BYTES) / SHADOW_GRANULARITY); + + s += (arz + ALLOC_HEADER_BYTES) / SHADOW_GRANULARITY; + __builtin_memset(s, 0, usz / SHADOW_GRANULARITY); + if (usz % SHADOW_GRANULARITY) + s[usz / SHADOW_GRANULARITY] = (uchar)(usz % SHADOW_GRANULARITY); + + __global alloc_t *a = (__global alloc_t *)(ap + arz); + a->magic = ALLOC_MAGIC; + a->sp = sp; + a->pc = pc; + a->asz = asz; + a->usz = usz; + + return ap + arz + ALLOC_HEADER_BYTES; +} + +// slab based malloc +NO_SANITIZE_ADDR +static ulong +slab_malloc(ulong lsz, ulong pc) +{ + __global heap_t *hp = get_heap_ptr(); + uint usz = (uint)lsz; + uint arz = added_redzone(usz); + uint asz = arz + ALLOC_HEADER_BYTES + round_16(usz); + ulong ret = 0; + + int go = 1; + do { + if (go) { + uint aid = __ockl_activelane_u32(); + + __global slab_t *cs = (__global slab_t *)0; + if (!aid) + cs = get_current_slab(hp); + cs = first(cs); + + if (!cs) { + go = 0; + continue; + } + + ulong o = (ulong)__ockl_alisa_u32(asz); + + ulong ap = 0; + if (!aid) + ap = AL(&cs->ap); + ap = first(ap); + + if (ap & (ulong)F_MASK) { + ulong p = 0; + if (!aid) + p = AN(&cs->ap, ~(ulong)F_POISON_NEEDED); + p = first(p); + + if (p & (ulong)F_POISON_NEEDED) + poison_slab(cs, aid, active_lane_count()); + else + slab_pause(); + } else { + ulong p = 0; + if (!aid) + p = AA(&cs->ap, o); + p = first(p); + + if (!(p & (ulong)F_MASK)) { + if (p + o <= (ulong)cs + SLAB_BYTES) { + ret = publish_allocation(p + o - asz, (ulong)cs, pc, asz, arz, usz); + go = 0; + } else { + if (!__ockl_activelane_u32()) { + ulong e = (ulong)cs; + ACE(&hp->cs, &e, 0UL); + AO(&cs->ap, (ulong)F_UNREADY); + } + if (p + o - asz < (ulong)cs + SLAB_BYTES) { + uint unused = (uint)((ulong)cs + SLAB_BYTES - (p + o - asz)); + uint rb = AA(&cs->rb, unused) + unused; + if (rb == SLAB_BYTES - SLAB_HEADER_BYTES) { + put_free_slab(hp, cs); + } + } + } + } else + slab_pause(); + } + } + } while (__ockl_wfany_i32(go)); + + + return ret; +} + +// malloc +USED +NO_INLINE +NO_SANITIZE_ADDR +ulong +__asan_malloc_impl(ulong sz, ulong pc) +{ + pc -= CALL_BYTES; + + ARF(); + + ulong ret; + if (sz > SLAB_THRESHOLD) + ret = non_slab_malloc(sz, pc); + else + ret = slab_malloc(sz, pc); + + ARF(); + + return ret; +} + +// This initialization assumes a one-workgroup grid with 256 work items, +// exacty like the non-ASAN version +NO_SANITIZE_ADDR +void +__ockl_dm_init_v1(ulong ha, ulong sa, uint hb, uint nis) +{ + uint lid = __ockl_get_local_id(0); + + __global ulong *hs = (__global ulong *)MEM_TO_SHADOW(ha); + hs[lid+0*256] = kAsanHeapLeftRedzoneMagicx8; + hs[lid+1*256] = kAsanHeapLeftRedzoneMagicx8; + hs[lid+2*256] = kAsanHeapLeftRedzoneMagicx8; + hs[lid+3*256] = kAsanHeapLeftRedzoneMagicx8; + hs[lid+4*256] = kAsanHeapLeftRedzoneMagicx8; + hs[lid+5*256] = kAsanHeapLeftRedzoneMagicx8; + hs[lid+6*256] = kAsanHeapLeftRedzoneMagicx8; + hs[lid+7*256] = kAsanHeapLeftRedzoneMagicx8; + + __global heap_t *hp = (__global heap_t *)ha; + + if (!lid) { + AS(&hp->cs, 0UL); + AS(&hp->atime, 0UL); + AS(&hp->rid, 0UL); + AS(&hp->wid, 0UL); + AS(&hp->initial_slabs, sa); + hp->initial_slabs_end = sa + ((ulong)nis << 21); +#if defined NON_SLAB_TRACKING + AS(&hp->num_nonslab_allocations, 0UL); +#endif +#if defined SLAB_IDENTITY + AS(&hp->num_slab_allocations, 0UL); +#endif + } + + if (lid < NLA) { + __global lifo_t *lp = LP(hp, lid); + AS(&lp->top, 0UL); + } +} + +NO_SANITIZE_ADDR +void +__ockl_dm_trim(int *mem) +{ +} + +#if defined NON_SLAB_TRACKING +// return a snapshot of the current number of nonslab allocations +// which haven't been deallocated +NO_SANITIZE_ADDR +ulong +__ockl_dm_nna(void) +{ + __global heap_t *hp = get_heap_ptr(); + return AL(&hp->num_nonslab_allocations); +} +#endif + diff --git a/amd/device-libs/asanrtl/src/globals.cl b/amd/device-libs/asanrtl/src/globals.cl new file mode 100644 index 0000000000000..18409a45e1f3b --- /dev/null +++ b/amd/device-libs/asanrtl/src/globals.cl @@ -0,0 +1,113 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "asan_util.h" +#include "globals.h" +#include "shadow_mapping.h" + +// fill shadow bytes of range [aligned_beg, aligned_beg+aligned_size) +// with value. +NO_SANITIZE_ADDR +static void +fill_shadowof(uptr aligned_beg, uptr aligned_size, s8 value) { + u64 nbytes = aligned_size / SHADOW_GRANULARITY; + __global s8 *shadow_beg = (__global s8*)MEM_TO_SHADOW(aligned_beg); + for (; nbytes; nbytes--, shadow_beg++) + *shadow_beg = value; +} + +// poison the redzones around the global only if global is shadow granularity aligned. +NO_SANITIZE_ADDR +static void +poison_redzones(__global const struct device_global *g) { + if (!is_aligned_by_granularity(g->beg)) + return; + if (!is_aligned_by_granularity(g->size_with_redzone)) + return; + + uptr aligned_size = round_upto(g->size, SHADOW_GRANULARITY); + uptr redzone_beg = g->beg + aligned_size; + uptr redzone_size = g->size_with_redzone - aligned_size; + fill_shadowof(redzone_beg, redzone_size, kAsanGlobalRedzoneMagic); + + // poison partial redzones if any. + // since SHADOW_GRANULARITY is 8 bytes we require only one shadow byte + // to keep partially addressable bytes information. + if (g->size != aligned_size) { + uptr aligned_addr = g->beg + round_downto(g->size, SHADOW_GRANULARITY); + __global s8 *shadow_addr = (__global s8*)MEM_TO_SHADOW(aligned_addr); + *shadow_addr = (s8) (g->size % SHADOW_GRANULARITY); + } +} + +// unpoison global and redzones around it only if global is shadow granularity aligned. +NO_SANITIZE_ADDR +static void +unpoison_redzones(__global const struct device_global *g) { + if (!is_aligned_by_granularity(g->beg)) + return; + if (!is_aligned_by_granularity(g->size_with_redzone)) + return; + fill_shadowof(g->beg, g->size_with_redzone, 0); +} + +// This function is called by one-workitem constructor kernel. +USED NO_INLINE NO_SANITIZE_ADDR +void +__asan_register_globals(uptr globals, uptr n) { + __global struct device_global *dglobals = (__global struct device_global*) globals; + for (uptr i = 0; i < n; i++) + poison_redzones(&dglobals[i]); +} + +// This function is called by one-workitem destructor kernel. +USED NO_INLINE NO_SANITIZE_ADDR +void +__asan_unregister_globals(uptr globals, uptr n) { + __global struct device_global* dglobals = (__global struct device_global*) globals; + for (uptr i = 0; i < n; i++) + unpoison_redzones(&dglobals[i]); +} + +USED NO_INLINE NO_SANITIZE_ADDR +void +__asan_register_elf_globals(uptr flag, uptr start, uptr stop) +{ + if (!start) + return; + + __global uptr *f = (__global uptr *)flag; + if (*f) + return; + + __global struct device_global *b = (__global struct device_global *)start; + __global struct device_global *e = (__global struct device_global *)stop; + + __asan_register_globals(start, e - b); + + *f = 1; +} + +USED NO_INLINE NO_SANITIZE_ADDR +void +__asan_unregister_elf_globals(uptr flag, uptr start, uptr stop) +{ + if (!start) + return; + + __global uptr *f = (__global uptr *)flag; + if (!*f) + return; + + __global struct device_global *b = (__global struct device_global *)start; + __global struct device_global *e = (__global struct device_global *)stop; + + __asan_unregister_globals(start, e - b); + + *f = 0; +} + diff --git a/amd/device-libs/asanrtl/src/memintrinsics.cl b/amd/device-libs/asanrtl/src/memintrinsics.cl new file mode 100644 index 0000000000000..794e8e72d1445 --- /dev/null +++ b/amd/device-libs/asanrtl/src/memintrinsics.cl @@ -0,0 +1,72 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "asan_util.h" +#include "shadow_mapping.h" + +NO_SANITIZE_ADDR +static void +check_memory_range_accessible(const void* dst, const void* src, uptr size, uptr pc) +{ + if (size == 0) + return; + + if (!__ockl_is_private_addr(src) && !__ockl_is_local_addr(src)) { + uptr invalid_addr = __asan_region_is_poisoned((uptr)src, size); + if (invalid_addr) { + REPORT_IMPL(pc, invalid_addr, false, size, false) + } + } + + if (!__ockl_is_private_addr(dst) && !__ockl_is_local_addr(dst)) { + uptr invalid_addr = __asan_region_is_poisoned((uptr)dst, size); + if (invalid_addr) { + REPORT_IMPL(pc, invalid_addr, true, size, false) + } + } +} + +USED +NO_INLINE +NO_SANITIZE_ADDR +void* +__asan_memcpy(void* to, const void* from, uptr size) +{ + uptr pc = GET_CALLER_PC(); + check_memory_range_accessible(to, from, size, pc); + return __builtin_memcpy(to, from, size); +} + +USED +NO_INLINE +NO_SANITIZE_ADDR +void* +__asan_memmove(void* to, const void* from, uptr size) +{ + uptr pc = GET_CALLER_PC(); + check_memory_range_accessible(to, from, size, pc); + return __builtin_memmove(to, from, size); +} + +USED +NO_INLINE +NO_SANITIZE_ADDR +void* +__asan_memset(void* s, int c, uptr n) +{ + uptr pc = GET_CALLER_PC(); + + if (!__ockl_is_private_addr(s) && !__ockl_is_local_addr(s)) { + uptr invalid_addr = __asan_region_is_poisoned((uptr)s, n); + if (invalid_addr) { + REPORT_IMPL(pc, invalid_addr, true, n, false) + } + } + + return __builtin_memset(s, c, n); +} + diff --git a/amd/device-libs/asanrtl/src/report.cl b/amd/device-libs/asanrtl/src/report.cl new file mode 100644 index 0000000000000..5846b00a3a312 --- /dev/null +++ b/amd/device-libs/asanrtl/src/report.cl @@ -0,0 +1,106 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "asan_util.h" +#include "shadow_mapping.h" + +#define ASAN_REPORT_ERROR(type, size, is_write) \ +USED NO_INLINE NO_SANITIZE_ADDR \ +void __asan_report_ ## type ## size(uptr addr) { \ + REPORT_IMPL(GET_CALLER_PC(), addr, is_write, size, false) \ +} \ +USED NO_INLINE NO_SANITIZE_ADDR \ +void __asan_report_ ## type ## size ## _noabort(uptr addr) { \ + REPORT_IMPL(GET_CALLER_PC(), addr, is_write, size, true) \ +} \ + +ASAN_REPORT_ERROR(load, 1, 0) +ASAN_REPORT_ERROR(load, 2, 0) +ASAN_REPORT_ERROR(load, 4, 0) +ASAN_REPORT_ERROR(load, 8, 0) +ASAN_REPORT_ERROR(load, 16,0) + +ASAN_REPORT_ERROR(store, 1, 1) +ASAN_REPORT_ERROR(store, 2, 1) +ASAN_REPORT_ERROR(store, 4, 1) +ASAN_REPORT_ERROR(store, 8, 1) +ASAN_REPORT_ERROR(store, 16,1) + +#define ASAN_REPORT_ERROR_N(type, is_write) \ +USED NO_INLINE NO_SANITIZE_ADDR \ +void __asan_report_ ## type ## _n(uptr addr, uptr size) { \ + REPORT_IMPL(GET_CALLER_PC(), addr, is_write, size, false) \ +} \ +USED NO_INLINE NO_SANITIZE_ADDR \ +void __asan_report_ ## type ## _n_noabort(uptr addr, uptr size) { \ + REPORT_IMPL(GET_CALLER_PC(), addr, is_write, size, true) \ +} \ + +ASAN_REPORT_ERROR_N(store,1) +ASAN_REPORT_ERROR_N(load,0) + +NO_SANITIZE_ADDR +static bool +is_invalid_access(uptr addr, uptr size) +{ + uptr shadow_addr = MEM_TO_SHADOW(addr); + if (size <= SHADOW_GRANULARITY) { + s8 shadow_value = *(__global s8*) shadow_addr; + return shadow_value != 0 && ((s8)((addr & (SHADOW_GRANULARITY-1)) + size - 1) >= shadow_value); + } + else { + s16 shadow_value = *(__global s16*) shadow_addr; + return shadow_value != 0; + } +} + +#define ASAN_ERROR(type, size, is_write) \ +USED NO_INLINE NO_SANITIZE_ADDR \ +void __asan_ ## type ## size(uptr addr) { \ + uptr caller_pc = GET_CALLER_PC(); \ + if (is_invalid_access(addr, size)) { \ + REPORT_IMPL(caller_pc, addr, is_write, size, false) \ + } \ +} \ +USED NO_INLINE NO_SANITIZE_ADDR \ +void __asan_ ## type ## size ## _noabort(uptr addr) { \ + uptr caller_pc = GET_CALLER_PC(); \ + if (is_invalid_access(addr, size)) { \ + REPORT_IMPL(caller_pc, addr, is_write, size, true) \ + } \ +} \ + +ASAN_ERROR(load, 1, 0) +ASAN_ERROR(load, 2, 0) +ASAN_ERROR(load, 4, 0) +ASAN_ERROR(load, 8, 0) +ASAN_ERROR(load, 16,0) + +ASAN_ERROR(store, 1, 1) +ASAN_ERROR(store, 2, 1) +ASAN_ERROR(store, 4, 1) +ASAN_ERROR(store, 8, 1) +ASAN_ERROR(store, 16,1) + +#define ASAN_ERROR_N(type, is_write) \ +USED NO_INLINE NO_SANITIZE_ADDR \ +void __asan_ ## type ## N(uptr addr, uptr size) { \ + uptr caller_pc = GET_CALLER_PC(); \ + if (__asan_region_is_poisoned(addr, size)) { \ + REPORT_IMPL(caller_pc, addr, is_write, size, false) \ + } \ +} \ +USED NO_INLINE NO_SANITIZE_ADDR \ +void __asan_ ## type ## N_noabort(uptr addr, uptr size) { \ + uptr caller_pc = GET_CALLER_PC(); \ + if (__asan_region_is_poisoned(addr, size)) { \ + REPORT_IMPL(caller_pc, addr, is_write, size, true) \ + } \ +} \ + +ASAN_ERROR_N(store, 1) +ASAN_ERROR_N(load, 0) diff --git a/amd/device-libs/asanrtl/src/shadow_mapping.cl b/amd/device-libs/asanrtl/src/shadow_mapping.cl new file mode 100644 index 0000000000000..d768e1e459d98 --- /dev/null +++ b/amd/device-libs/asanrtl/src/shadow_mapping.cl @@ -0,0 +1,71 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "shadow_mapping.h" + +static const __constant u8 kAsanHeapLeftRedzoneMagic = (u8)0xfa; + +NO_SANITIZE_ADDR +static uptr +range_check(uptr beg, uptr end) { + uptr aligned_beg = round_downto(beg, SHADOW_GRANULARITY); + uptr aligned_end = round_downto(end, SHADOW_GRANULARITY); + uptr shadow_beg = MEM_TO_SHADOW(aligned_beg); + uptr shadow_end = MEM_TO_SHADOW(aligned_end); + uptr nbytes = (shadow_end - shadow_beg)+1; + uptr shadow_byte_count = 0; + while (shadow_beg <= shadow_end) { + s8 shadow_value = *(__global s8 *)shadow_beg; + if (shadow_value) + break; + shadow_byte_count++; + shadow_beg++; + } + if (shadow_byte_count == nbytes) + return 0; + uptr start_addr = round_downto(beg + (shadow_byte_count*SHADOW_GRANULARITY), SHADOW_GRANULARITY); + return start_addr; +} + +//check all application bytes in [beg,beg+size) range are accessible +USED NO_INLINE NO_SANITIZE_ADDR +uptr +__asan_region_is_poisoned(uptr beg, uptr size) +{ + uptr end = beg + size - 1; + uptr start_addr = range_check(beg, end); + if (start_addr != 0) { + // loop through the range to find accessible address. + for (uptr addr = start_addr; addr <= end; ++addr) { + if (is_address_poisoned(addr)) + return addr; + } + } + return 0; +} + +USED NO_INLINE NO_SANITIZE_ADDR +void +__asan_poison_region(ulong beg, ulong size) +{ + // Handle intial bytes if not aligned. + if (!is_aligned_by_granularity(beg)) { + ulong beg_round_downto = round_downto(beg, SHADOW_GRANULARITY); + __global s8 *shadow_ptr = (__global s8 *)MEM_TO_SHADOW(beg_round_downto); + s8 shadow_value = (s8) (beg - beg_round_downto); + *shadow_ptr = shadow_value; + } + + // Handle aligned bytes. + ulong end = round_downto(beg + size, SHADOW_GRANULARITY); + ulong beg_round_upto = round_upto(beg, SHADOW_GRANULARITY); + if (end > beg_round_upto) { + u64 shadow_size = (end - beg_round_upto) / SHADOW_GRANULARITY; + __global s8 *shadow_ptr = (__global s8 *)MEM_TO_SHADOW(beg_round_upto); + __builtin_memset(shadow_ptr, kAsanHeapLeftRedzoneMagic, shadow_size); + } +} diff --git a/amd/device-libs/asanrtl/src/stubs.cl b/amd/device-libs/asanrtl/src/stubs.cl new file mode 100644 index 0000000000000..683fc3974228f --- /dev/null +++ b/amd/device-libs/asanrtl/src/stubs.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "asan_util.h" + +USED NO_SANITIZE_ADDR void __asan_handle_no_return(void) {} + +USED NO_SANITIZE_ADDR void __sanitizer_ptr_cmp(uptr a, uptr b) {} + +USED NO_SANITIZE_ADDR void __sanitizer_ptr_sub(uptr a, uptr b) {} + +USED NO_SANITIZE_ADDR void __asan_before_dynamic_init(uptr addr) {} + +USED NO_SANITIZE_ADDR void __asan_after_dynamic_init(void) {} + +USED NO_SANITIZE_ADDR void __asan_register_image_globals(uptr flag) {} + +USED NO_SANITIZE_ADDR void __asan_unregister_image_globals(uptr flag) {} + +USED NO_SANITIZE_ADDR void __asan_init(void) {} + +USED NO_SANITIZE_ADDR void __asan_version_mismatch_check_v8(void) {} + diff --git a/amd/device-libs/cmake/OCL.cmake b/amd/device-libs/cmake/OCL.cmake new file mode 100644 index 0000000000000..f0d5441d79739 --- /dev/null +++ b/amd/device-libs/cmake/OCL.cmake @@ -0,0 +1,227 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +# Required because we need to generate response files on windows for long +# command-lines, but the only way to do this as part of the dependency graph is +# configure_file and we are included from multiple places. To get around this +# we `file(WRITE)` a file with an @variable reference and `configure_file` it. +# FIXME: CMP0053 is removed in CMake 4; refine code relying on this policy. +if(${CMAKE_VERSION} VERSION_LESS "4.0.0") + cmake_policy(SET CMP0053 OLD) +endif() + +if(${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.20.0") + # The policy change was for handling of relative paths for + # DEPFILE. We only use absolute paths but cmake still feels the need + # to complain without setting this. + cmake_policy(SET CMP0116 NEW) +endif() + + +if (WIN32) + set(EXE_SUFFIX ".exe") +else() + set(EXE_SUFFIX) +endif() + +# -Wno-error=atomic-alignment was added to workaround build problems due to +# potential mis-aligned atomic ops detected by clang +set(CLANG_OCL_FLAGS -fcolor-diagnostics -Werror -Wno-error=atomic-alignment -x cl -Xclang + -cl-std=CL2.0 -target "${AMDGPU_TARGET_TRIPLE}" -fvisibility=hidden -fomit-frame-pointer + -Xclang -finclude-default-header -Xclang -fexperimental-strict-floating-point + -Xclang -fdenormal-fp-math=dynamic + -nogpulib -cl-no-stdinc "${CLANG_OPTIONS_APPEND}") + +# For compatibility with the MSVC headers we use a 32-bit wchar. Users linking +# against us must also use a short wchar. +if (WIN32) + set(CLANG_OCL_FLAGS ${CLANG_OCL_FLAGS} -fshort-wchar) +endif() + +# Disable code object version module flag. +set(CLANG_OCL_FLAGS ${CLANG_OCL_FLAGS} -Xclang -mcode-object-version=none) + +set (BC_EXT .bc) +set (LIB_SUFFIX ".lib${BC_EXT}") +set (STRIP_SUFFIX ".strip${BC_EXT}") +set (FINAL_SUFFIX "${BC_EXT}") +set (INSTALL_ROOT_SUFFIX "amdgcn/bitcode") + +if (NOT ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_NEW STREQUAL "") + set(INSTALL_ROOT_SUFFIX "${ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_NEW}/bitcode") +endif() + +# Set `inc_options` to contain Clang command-line for include directories for +# current source directory. +macro(set_inc_options) + get_property(inc_dirs + DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" + PROPERTY INCLUDE_DIRECTORIES) + set(inc_options) + foreach(inc_dir ${inc_dirs}) + list(APPEND inc_options "-I${inc_dir}") + endforeach() +endmacro() + +# called with NAME: library name +# SOURCES: .cl and .ll source files +# INTERNAL_LINK_LIBS: Extra .lls to be linked and internalized into final library +macro(opencl_bc_lib) + set(parse_options) + set(one_value_args NAME) + set(multi_value_args SOURCES INTERNAL_LINK_LIBS) + + cmake_parse_arguments(OPENCL_BC_LIB "${parse_options}" "${one_value_args}" + "${multi_value_args}" ${ARGN}) + + set(name ${OPENCL_BC_LIB_NAME}) + set(sources ${OPENCL_BC_LIB_SOURCES}) + set(internal_link_libs ${OPENCL_BC_LIB_INTERNAL_LINK_LIBS}) + + # Mirror the install layout structure. + set(OUTPUT_DIR ${PROJECT_BINARY_DIR}/${INSTALL_ROOT_SUFFIX}) + file(MAKE_DIRECTORY ${OUTPUT_DIR}) + + set(OUT_NAME ${name}) + set(OUTPUT_BC_LIB ${OUTPUT_DIR}/${name}${FINAL_SUFFIX}) + + set(clean_files) + + list(APPEND AMDGCN_LIB_LIST ${name}) + set(AMDGCN_LIB_LIST ${AMDGCN_LIB_LIST} PARENT_SCOPE) + + list(APPEND AMDGCN_DEP_LIST ${name}) + set(AMDGCN_DEP_LIST ${AMDGCN_DEP_LIST} PARENT_SCOPE) + + set_inc_options() + set(deps) + foreach(file ${OPENCL_BC_LIB_SOURCES}) + get_filename_component(fname "${file}" NAME) + get_filename_component(fname_we "${file}" NAME_WE) + get_filename_component(fext "${file}" EXT) + if (fext STREQUAL ".cl") + set(output "${CMAKE_CURRENT_BINARY_DIR}/${fname_we}${BC_EXT}") + set(depfile "${CMAKE_CURRENT_BINARY_DIR}/${fname}.d") + + get_property(file_specific_flags SOURCE "${file}" PROPERTY COMPILE_FLAGS) + + add_custom_command(OUTPUT "${output}" + COMMAND $ ${inc_options} ${CLANG_OCL_FLAGS} + ${file_specific_flags} + -emit-llvm -c "${file}" -o "${output}" + -MD -MF ${depfile} + MAIN_DEPENDENCY "${file}" + DEPENDS "$" + DEPFILE ${depfile}) + list(APPEND deps "${output}") + list(APPEND clean_files "${output}") + endif() + if (fext STREQUAL ".ll") + list(APPEND deps "${file}") + endif() + endforeach() + + # The llvm-link command-lines can get long enough to trigger strange behavior + # on Windows. LLVM tools support "response files" which can work around this: + # http://llvm.org/docs/CommandLine.html#response-files + set(RESPONSE_COMMAND_LINE) + foreach(dep ${deps}) + set(RESPONSE_COMMAND_LINE "${RESPONSE_COMMAND_LINE} ${dep}") + endforeach() + file(WRITE "${CMAKE_CURRENT_BINARY_DIR}/response.in" "@RESPONSE_COMMAND_LINE@") + configure_file("${CMAKE_CURRENT_BINARY_DIR}/response.in" + "${CMAKE_CURRENT_BINARY_DIR}/${OUT_NAME}_response" @ONLY) + + add_custom_command(OUTPUT ${OUTPUT_BC_LIB} + # Link regular library dependencies + COMMAND $ + -o "${OUT_NAME}.link0${LIB_SUFFIX}" "@${OUT_NAME}_response" + # Extra link step with internalize + COMMAND $ -internalize -only-needed "${name}.link0${LIB_SUFFIX}" + -o "${OUT_NAME}${LIB_SUFFIX}" ${internal_link_libs} + COMMAND $ + -o "${OUT_NAME}${STRIP_SUFFIX}" "${OUT_NAME}${LIB_SUFFIX}" + COMMAND "${PREPARE_BUILTINS}" + -o ${OUTPUT_BC_LIB} "${OUT_NAME}${STRIP_SUFFIX}" + DEPENDS "${deps}" "${CMAKE_CURRENT_BINARY_DIR}/${OUT_NAME}_response" "${PREPARE_BUILTINS}" ${internal_link_libs}) + + add_custom_target("${name}" ALL + DEPENDS "${OUTPUT_DIR}/${OUT_NAME}${FINAL_SUFFIX}" + SOURCES ${OPENCL_BC_LIB_SOURCES}) + add_dependencies(rocm-device-libs "${name}") + set_target_properties(${name} PROPERTIES + OUTPUT_NAME "${OUTPUT_DIR}/${OUT_NAME}${FINAL_SUFFIX}" + ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_BINARY_DIR}" + ARCHIVE_OUTPUT_NAME "${name}" + PREFIX "" SUFFIX ${FINAL_SUFFIX}) + + list(APPEND clean_files + "${OUT_NAME}${LIB_SUFFIX}" "${OUT_NAME}${STRIP_SUFFIX}") + + set_property(GLOBAL APPEND PROPERTY AMD_DEVICE_LIBS ${name}) + + if(NOT ROCM_DEVICELIB_STANDALONE_BUILD) + add_dependencies("${name}" llvm-link clang opt llvm-objdump) + endif() + + if (TARGET prepare-builtins) + add_dependencies("${name}" prepare-builtins) + endif() + + set_directory_properties(PROPERTIES + ADDITIONAL_MAKE_CLEAN_FILES "${clean_files}") + + install(FILES ${OUTPUT_BC_LIB} + DESTINATION ${INSTALL_ROOT_SUFFIX} + COMPONENT device-libs) +endmacro() + +function(clang_opencl_code name dir) + set(TEST_TGT "${name}_code") + set(OUT_NAME "${CMAKE_CURRENT_BINARY_DIR}/${name}") + set(mlink_flags) + foreach (lib ${ARGN}) + get_target_property(lib_path "${lib}" OUTPUT_NAME) + list(APPEND mlink_flags + -Xclang -mlink-bitcode-file + -Xclang "${lib_path}") + endforeach() + set_inc_options() + add_custom_command(OUTPUT "${OUT_NAME}.co" + COMMAND "$" ${inc_options} ${CLANG_OCL_FLAGS} + -mcpu=fiji ${mlink_flags} -o "${OUT_NAME}.co" -c "${dir}/${name}.cl" + DEPENDS "${dir}/${name}.cl") + add_custom_target("${TEST_TGT}" ALL + DEPENDS "${OUT_NAME}.co" + SOURCES "${dir}/${name}.cl") + set_target_properties(${TEST_TGT} PROPERTIES + OUTPUT_NAME "${OUT_NAME}.co") + foreach (lib ${ARGN}) + add_dependencies(${TEST_TGT} ${lib}) + endforeach() +endfunction() + +set(OCLC_DEFAULT_LIBS + oclc_correctly_rounded_sqrt_off + oclc_daz_opt_off + oclc_finite_only_off + oclc_isa_version_803 + oclc_unsafe_math_off) + +macro(clang_opencl_test name dir) + clang_opencl_code(${name} ${dir} hip opencl ocml ockl ${OCLC_DEFAULT_LIBS}) + add_test( + NAME ${name}:llvm-objdump + COMMAND $ -disassemble -mcpu=fiji "${name}.co" + ) +endmacro() + +macro(clang_opencl_test_file dir fname) + get_filename_component(name ${fname} NAME_WE) + get_filename_component(fdir ${fname} DIRECTORY) + clang_opencl_test(${name} ${dir}/${fdir}) +endmacro() diff --git a/amd/device-libs/cmake/Packages.cmake b/amd/device-libs/cmake/Packages.cmake new file mode 100644 index 0000000000000..7406d31e6fad6 --- /dev/null +++ b/amd/device-libs/cmake/Packages.cmake @@ -0,0 +1,46 @@ +set(PACKAGE_PREFIX ${CMAKE_INSTALL_LIBDIR}/cmake/AMDDeviceLibs) + +# Generate the build-tree package. +# We know the absolute path to the build tree, so we leave +# AMD_DEVICE_LIBS_PREFIX_CODE blank and include absolute paths in the target +# imports in AMD_DEVICE_LIBS_TARGET_CODE. +foreach(target ${AMDGCN_LIB_LIST}) + get_target_property(target_path ${target} OUTPUT_NAME) + set(AMD_DEVICE_LIBS_TARGET_CODE "${AMD_DEVICE_LIBS_TARGET_CODE} +add_library(${target} STATIC IMPORTED) +set_target_properties(${target} PROPERTIES + IMPORTED_LOCATION \"${target_path}\")") +endforeach() +configure_file(AMDDeviceLibsConfig.cmake.in + ${PACKAGE_PREFIX}/AMDDeviceLibsConfig.cmake + @ONLY) + +# Generate the install-tree package. +# We do not know the absolute path to the intall tree until we are installed, +# so we calculate it dynamically in AMD_DEVICE_LIBS_PREFIX_CODE and use +# relative paths in the target imports in AMD_DEVICE_LIBS_TARGET_CODE. +set(AMD_DEVICE_LIBS_PREFIX_CODE " +# Derive absolute install prefix from config file path. +get_filename_component(AMD_DEVICE_LIBS_PREFIX \"\${CMAKE_CURRENT_LIST_FILE}\" PATH)") +string(REGEX REPLACE "/" ";" count "${PACKAGE_PREFIX}") +foreach(p ${count}) + set(AMD_DEVICE_LIBS_PREFIX_CODE "${AMD_DEVICE_LIBS_PREFIX_CODE} +get_filename_component(AMD_DEVICE_LIBS_PREFIX \"\${AMD_DEVICE_LIBS_PREFIX}\" PATH)") +endforeach() +set(AMD_DEVICE_LIBS_TARGET_CODE) +foreach(target ${AMDGCN_LIB_LIST}) + get_target_property(target_name ${target} ARCHIVE_OUTPUT_NAME) + get_target_property(target_prefix ${target} PREFIX) + get_target_property(target_suffix ${target} SUFFIX) + set(AMD_DEVICE_LIBS_TARGET_CODE "${AMD_DEVICE_LIBS_TARGET_CODE} +add_library(${target} STATIC IMPORTED) +set_target_properties(${target} PROPERTIES + IMPORTED_LOCATION \"\${AMD_DEVICE_LIBS_PREFIX}/${INSTALL_ROOT_SUFFIX}/${target_prefix}${target_name}${target_suffix}\")") +endforeach() +configure_file(AMDDeviceLibsConfig.cmake.in + ${CMAKE_CURRENT_BINARY_DIR}/AMDDeviceLibsConfig.cmake.install + @ONLY) +install(FILES ${CMAKE_CURRENT_BINARY_DIR}/AMDDeviceLibsConfig.cmake.install + DESTINATION ${PACKAGE_PREFIX} + COMPONENT device-libs + RENAME AMDDeviceLibsConfig.cmake) diff --git a/amd/device-libs/cuda2gcn/CMakeLists.txt b/amd/device-libs/cuda2gcn/CMakeLists.txt new file mode 100644 index 0000000000000..27872c165b75a --- /dev/null +++ b/amd/device-libs/cuda2gcn/CMakeLists.txt @@ -0,0 +1,18 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +file(GLOB cl_sources + ${CMAKE_CURRENT_SOURCE_DIR}/src/*.cl +) + +file(GLOB sources ${cl_sources}) + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../ocml/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../ockl/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../irif/inc) +opencl_bc_lib(NAME cuda2gcn + SOURCES ${sources}) diff --git a/amd/device-libs/cuda2gcn/src/bitsbytes.cl b/amd/device-libs/cuda2gcn/src/bitsbytes.cl new file mode 100644 index 0000000000000..19caa9e86a9a4 --- /dev/null +++ b/amd/device-libs/cuda2gcn/src/bitsbytes.cl @@ -0,0 +1,46 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" +#include "irif.h" + +#define ATTR __attribute__((const)) + +//-------- T __nv_brev +ATTR int __nv_brev(int x) { return __builtin_bitreverse32(x); } + +//-------- T __nv_brevll +ATTR long __nv_brevll(long x) { return __builitn_bitreverse64(x); } + +//-------- T __nv_clz +ATTR int __nv_clz(int x) +{ + return (int)__ockl_clz_u32((uint)x); +} + +//-------- T __nv_clzll +ATTR int __nv_clzll(long x) +{ + uint xlo = (uint)x; + uint xhi = (uint)(x >> 32); + uint zlo = __ockl_clz_u32(xlo) + 32u; + uint zhi = __ockl_clz_u32(xhi); + return (int)(xhi == 0 ? zlo : zhi); +} + +//-------- T __nv_ffs +ATTR int __nv_ffs(int x) { return (32 - __nv_clz(x&(-x))); } + +//-------- T __nv_ffsll +ATTR int __nv_ffsll(long x) { return (int)(64 - __nv_clzll(x&(-x))); } + +//-------- T __nv_popc +ATTR int __nv_popc(int x) { return __llvm_ctpop_i32(x); } + +//-------- T __nv_popcll +ATTR int __nv_popcll(long x) { return (int)__llvm_ctpop_i64(x); } + diff --git a/amd/device-libs/cuda2gcn/src/convert.cl b/amd/device-libs/cuda2gcn/src/convert.cl new file mode 100644 index 0000000000000..b79ab0c24372f --- /dev/null +++ b/amd/device-libs/cuda2gcn/src/convert.cl @@ -0,0 +1,150 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((const)) + +#define CONVERTM(A,B,m,n) ATTR B __nv_##A##2##B##_##m(A x) \ + { return convert_##B##_##n(x); } + +#define CONVERT(A,B) \ + CONVERTM(A, B, rd, rtn) \ + CONVERTM(A, B, rn, rte) \ + CONVERTM(A, B, ru, rtp) \ + CONVERTM(A, B, rz, rtz) + +//-------- T __nv_double2float_rd +//-------- T __nv_double2float_rn +//-------- T __nv_double2float_ru +//-------- T __nv_double2float_rz +CONVERT(double, float) + +//-------- T __nv_double2int_rd +//-------- T __nv_double2int_rn +//-------- T __nv_double2int_ru +//-------- T __nv_double2int_rz +CONVERT(double, int) + +//-------- T __nv_float2int_rd +//-------- T __nv_float2int_rn +//-------- T __nv_float2int_ru +//-------- T __nv_float2int_rz +CONVERT(float, int) + +//-------- T __nv_int2float_rd +//-------- T __nv_int2float_rn +//-------- T __nv_int2float_ru +//-------- T __nv_int2float_rz +CONVERT(int, float) + +//-------- T __nv_double2uint_rd +//-------- T __nv_double2uint_rn +//-------- T __nv_double2uint_ru +//-------- T __nv_double2uint_rz +CONVERT(double, uint) + +//-------- T __nv_float2uint_rd +//-------- T __nv_float2uint_rn +//-------- T __nv_float2uint_ru +//-------- T __nv_float2uint_rz +CONVERT(float, uint) + +//-------- T __nv_uint2double_rd +//-------- T __nv_uint2double_rn +//-------- T __nv_uint2double_ru +//-------- T __nv_uint2double_rz +CONVERT(uint, double) + +//-------- T __nv_uint2float_rd +//-------- T __nv_uint2float_rn +//-------- T __nv_uint2float_ru +//-------- T __nv_uint2float_rz +CONVERT(uint, float) + +#define CONVERT2LLM(A,B,m,n) ATTR long __nv_##A##2ll_##m(A x) \ + { return convert_long_##n(x); } + +#define CONVERT2LL(A) \ + CONVERT2LLM(A, long, rd, rtn) \ + CONVERT2LLM(A, long, rn, rte) \ + CONVERT2LLM(A, long, ru, rtp) \ + CONVERT2LLM(A, long, rz, rtz) + +//-------- T __nv_double2ll_rd +//-------- T __nv_double2ll_rn +//-------- T __nv_double2ll_ru +//-------- T __nv_double2ll_rz +CONVERT2LL(double) + +//-------- T __nv_float2ll_rd +//-------- T __nv_float2ll_rn +//-------- T __nv_float2ll_ru +//-------- T __nv_float2ll_rz +CONVERT2LL(float) + +#define CONVERT2ULLM(A,B,m,n) ATTR ulong __nv_##A##2ull_##m(A x) \ + { return convert_ulong_##n(x); } + +#define CONVERT2ULL(A) \ + CONVERT2ULLM(A, ulong, rd, rtn) \ + CONVERT2ULLM(A, ulong, rn, rte) \ + CONVERT2ULLM(A, ulong, ru, rtp) \ + CONVERT2ULLM(A, ulong, rz, rtz) + +//-------- T __nv_double2ull_rd +//-------- T __nv_double2ull_rn +//-------- T __nv_double2ull_ru +//-------- T __nv_double2ull_rz +CONVERT2ULL(double) + +//-------- T __nv_float2ull_rd +//-------- T __nv_float2ull_rn +//-------- T __nv_float2ull_ru +//-------- T __nv_float2ull_rz +CONVERT2ULL(float) + +#define CONVERT4LLM(A,B,m,n) ATTR B __nv_ll2##B##_##m(long x) \ + { return convert_##B##_##n(x); } + +#define CONVERT4LL(B) \ + CONVERT4LLM(long, B, rd, rtn) \ + CONVERT4LLM(long, B, rn, rte) \ + CONVERT4LLM(long, B, ru, rtp) \ + CONVERT4LLM(long, B, rz, rtz) + +//-------- T __nv_ll2double_rd +//-------- T __nv_ll2double_rn +//-------- T __nv_ll2double_ru +//-------- T __nv_ll2double_rz +CONVERT4LL(double) + +//-------- T __nv_ll2float_rd +//-------- T __nv_ll2float_rn +//-------- T __nv_ll2float_ru +//-------- T __nv_ll2float_rz +CONVERT4LL(float) + +#define CONVERT4ULLM(A,B,m,n) ATTR B __nv_ull2##B##_##m(ulong x) \ + { return convert_##B##_##n(x); } + +#define CONVERT4ULL(B) \ + CONVERT4ULLM(ulong, B, rd, rtn) \ + CONVERT4ULLM(ulong, B, rn, rte) \ + CONVERT4ULLM(ulong, B, ru, rtp) \ + CONVERT4ULLM(ulong, B, rz, rtz) + +//-------- T __nv_ull2double_rd +//-------- T __nv_ull2double_rn +//-------- T __nv_ull2double_ru +//-------- T __nv_ull2double_rz +CONVERT4ULL(double) + +//-------- T __nv_ull2float_rd +//-------- T __nv_ull2float_rn +//-------- T __nv_ull2float_ru +//-------- T __nv_ull2float_rz +CONVERT4ULL(float) + diff --git a/amd/device-libs/cuda2gcn/src/float.cl b/amd/device-libs/cuda2gcn/src/float.cl new file mode 100644 index 0000000000000..7c0ed2fa56a1e --- /dev/null +++ b/amd/device-libs/cuda2gcn/src/float.cl @@ -0,0 +1,33 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((const)) + +//-------- T __nv_finitef +ATTR int __nv_finitef(float x) { return isfinite(x); } + +//-------- T __nv_isfinited +ATTR int __nv_isfinited(double x) { return isfinite(x); } + +//-------- T __nv_isinfd +ATTR int __nv_isinfd(double x) { return isinf(x); } + +//-------- T __nv_isinff +ATTR int __nv_isinff(float x) { return isinf(x); } + +//-------- T __nv_isnand +ATTR int __nv_isnand(double x) { return isnan(x); } + +//-------- T __nv_isnanf +ATTR int __nv_isnanf(float x) { return isnan(x); } + +//-------- T __nv_nan +ATTR double __nv_nan(char *tagp) { return __builtin_nan(tagp); } + +//-------- T __nv_nanf +ATTR float __nv_nanf(char *tagp) { return __builtin_nan(tagp); } + diff --git a/amd/device-libs/cuda2gcn/src/generic.cl b/amd/device-libs/cuda2gcn/src/generic.cl new file mode 100644 index 0000000000000..3ac519aec7b2a --- /dev/null +++ b/amd/device-libs/cuda2gcn/src/generic.cl @@ -0,0 +1,54 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((const)) + +#define MAX(x, y) (((x) > (y)) ? (x) : (y)) +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) + +//-------- T __nv_abs +ATTR int __nv_abs(int x) { return abs(x); } + +//-------- T __nv_llabs +ATTR long __nv_llabs(long x) { return abs(x); } + +//-------- T __nv_max +ATTR int __nv_max(int a, int b) { return MAX(a,b); } + +//-------- T __nv_llmax +ATTR long __nv_llmax(long a, long b) { return MAX(a,b); } + +//-------- T __nv_ullmax +ATTR ulong __nv_ullmax(ulong a, ulong b) { return MAX(a,b); } + +//-------- T __nv_umax +ATTR uint __nv_umax(uint a, uint b) { return MAX(a,b); } + +//-------- T __nv_min +ATTR int __nv_min(int a, int b) { return MIN(a,b); } + +//-------- T __nv_llmin +ATTR long __nv_llmin(long a, long b) { return MIN(a,b); } + +//-------- T __nv_ullmin +ATTR ulong __nv_ullmin(ulong a, ulong b) { return MIN(a,b); } + +//-------- T __nv_umin +ATTR uint __nv_umin(uint a, uint b) { return MIN(a,b); } + +//-------- T __nv_sad +ATTR uint __nv_sad(int x, int y, uint z) +{ + return (z+abs(x-y)); +} + +//-------- T __nv_usad +ATTR uint __nv_usad(uint x, uint y, uint z) +{ + return (z+abs(x-y)); +} + diff --git a/amd/device-libs/cuda2gcn/src/half.cl b/amd/device-libs/cuda2gcn/src/half.cl new file mode 100644 index 0000000000000..517cebb560dce --- /dev/null +++ b/amd/device-libs/cuda2gcn/src/half.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ATTR __attribute__((const)) + +//-------- T __nv_float2half_rn +half __nv_float2half_rn(float x) +{ + return (half)x; +} + +//-------- T __nv_half2float +float __nv_half2float(half x) +{ + return (float)x; +} + diff --git a/amd/device-libs/cuda2gcn/src/integer.cl b/amd/device-libs/cuda2gcn/src/integer.cl new file mode 100644 index 0000000000000..58b8bf5a3303b --- /dev/null +++ b/amd/device-libs/cuda2gcn/src/integer.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((always_inline, const)) + +//-------- T __nv_mul24 +ATTR int __nv_mul24(int x, int y) { return __ockl_mul24_i32(x, y); } + +//-------- T __nv_umul24 +ATTR uint __nv_umul24(uint x, uint y) { return __ockl_mul24_u32(x, y); } + +//-------- T __nv_mul64hi +ATTR long __nv_mul64hi(long x, long y) { return __ockl_mul_hi_i64(x,y); } + +//-------- T __nv_mulhi +ATTR int __nv_mulhi(int x, int y) { return __ockl_mul_hi_i32(x,y); } + +//-------- T __nv_umul64hi +ATTR ulong __nv_umul64hi(ulong x, ulong y) { return __ockl_mul_hi_u64(x,y); } + +//-------- T __nv_umulhi +ATTR uint __nv_umulhi(uint x, uint y) { return __ockl_mul_hi_u32(x,y); } + diff --git a/amd/device-libs/cuda2gcn/src/math.cl b/amd/device-libs/cuda2gcn/src/math.cl new file mode 100644 index 0000000000000..2c4eaf551bb12 --- /dev/null +++ b/amd/device-libs/cuda2gcn/src/math.cl @@ -0,0 +1,354 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#define ATTR __attribute__((always_inline)) + +#define FUNC1D(root) \ + ATTR double __nv_##root(double x) { return __ocml_##root##_f64(x); } +#define FUNC1F(root) \ + ATTR float __nv_##root##f(float x) { return __ocml_##root##_f32(x); } +#define FUNC1(root) FUNC1D(root) FUNC1F(root) + +#define FUNC2D(root) \ + ATTR double __nv_##root(double x, double y) { return __ocml_##root##_f64(x, y); } +#define FUNC2F(root) \ + ATTR float __nv_##root##f(float x, float y) { return __ocml_##root##_f32(x, y); } +#define FUNC2(root) FUNC2D(root) FUNC2F(root) + +#define FUNC3D(root) \ + ATTR double __nv_##root(double x, double y, double z) { return __ocml_##root##_f64(x, y, z); } +#define FUNC3F(root) \ + ATTR float __nv_##root##f(float x, float y, float z) { return __ocml_##root##_f32(x, y, z); } +#define FUNC3(root) FUNC3D(root) FUNC3F(root) + +//-------- T __nv_acos +//-------- T __nv_acosf +FUNC1(acos) + +//-------- T __nv_acosh +//-------- T __nv_acoshf +FUNC1(acosh) + +//-------- T __nv_asin +//-------- T __nv_asinf +FUNC1(asin) + +//-------- T __nv_asinh +//-------- T __nv_asinhf +FUNC1(asinh) + +//-------- T __nv_atan +//-------- T __nv_atanf +FUNC1(atan) + +//-------- T __nv_atan2 +//-------- T __nv_atan2f +FUNC2(atan2) + +//-------- T __nv_atanh +//-------- T __nv_atanhf +FUNC1(atanh) + +//-------- T __nv_cbrt +//-------- T __nv_cbrtf +FUNC1(cbrt) + +//-------- T __nv_ceil +//-------- T __nv_ceilf +FUNC1(ceil) + +//-------- T __nv_copysign +//-------- T __nv_copysignf +FUNC2(copysign) + +//-------- T __nv_cos +//-------- T __nv_cosf +FUNC1(cos) + +//-------- T __nv_cosh +//-------- T __nv_coshf +FUNC1(cosh) + +//-------- T __nv_cospi +//-------- T __nv_cospif +FUNC1(cospi) + +//-------- T __nv_erf +//-------- T __nv_erff +FUNC1(erf) + +//-------- T __nv_erfc +//-------- T __nv_erfcf +FUNC1(erfc) + +//-------- T __nv_erfcinv +//-------- T __nv_erfcinvf +FUNC1(erfcinv) + +//-------- T __nv_erfcx +//-------- T __nv_erfcxf +FUNC1(erfcx) + +//-------- T __nv_erfinv +//-------- T __nv_erfinvf +FUNC1(erfinv) + +//-------- T __nv_exp +//-------- T __nv_expf +FUNC1(exp) + +//-------- T __nv_exp10 +//-------- T __nv_exp10f +FUNC1(exp10) + +//-------- T __nv_exp2 +//-------- T __nv_exp2f +FUNC1(exp2) + +//-------- T __nv_expm1 +//-------- T __nv_expm1f +FUNC1(expm1) + +//-------- T __nv_fabs +//-------- T __nv_fabsf +FUNC1(fabs) + +//-------- T __nv_fdim +//-------- T __nv_fdimf +FUNC2(fdim) + +//-------- T __nv_floor +//-------- T __nv_floorf +FUNC1(floor) + +//-------- T __nv_fma +//-------- T __nv_fmaf +FUNC3(fma) + +//-------- T __nv_fmax +//-------- T __nv_fmaxf +FUNC2(fmax) + +//-------- T __nv_fmin +//-------- T __nv_fminf +FUNC2(fmin) + +//-------- T __nv_fmod +//-------- T __nv_fmodf +FUNC2(fmod) + +//-------- T __nv_hypot +//-------- T __nv_hypotf +FUNC2(hypot) + +//-------- T __nv_j0 +//-------- T __nv_j0f +FUNC1(j0) + +//-------- T __nv_j1 +//-------- T __nv_j1f +FUNC1(j1) + +//-------- T __nv_lgamma +//-------- T __nv_lgammaf +FUNC1(lgamma) + +//-------- T __nv_log +//-------- T __nv_logf +FUNC1(log) + +//-------- T __nv_log10 +//-------- T __nv_log10f +FUNC1(log10) + +//-------- T __nv_log1p +//-------- T __nv_log1pf +FUNC1(log1p) + +//-------- T __nv_log2 +//-------- T __nv_log2f +FUNC1(log2) + +//-------- T __nv_logb +//-------- T __nv_logbf +FUNC1(logb) + +//-------- T __nv_pow +//-------- T __nv_powf +FUNC2(pow) + +//-------- T __nv_rcbrt +//-------- T __nv_rcbrtf +FUNC1(rcbrt) + +//-------- T __nv_remainder +//-------- T __nv_remainderf +FUNC2(remainder) + +//-------- T __nv_rhypot +//-------- T __nv_rhypotf +FUNC2(rhypot) + +//-------- T __nv_nearbyint +//-------- T __nv_nearbyintf +FUNC1(nearbyint) + +//-------- T __nv_nextafter +//-------- T __nv_nextafterf +FUNC2(nextafter) + +//-------- T __nv_rint +//-------- T __nv_rintf +FUNC1(rint) + +//-------- T __nv_round +//-------- T __nv_roundf +FUNC1(round) + +//-------- T __nv_rsqrt +//-------- T __nv_rsqrtf +FUNC1(rsqrt) + +//-------- T __nv_scalbn +//-------- T __nv_scalbnf +FUNC2(scalbn) + +//-------- T __nv_sin +//-------- T __nv_sinf +FUNC1(sin) + +//-------- T __nv_sinh +//-------- T __nv_sinhf +FUNC1(sinh) + +//-------- T __nv_sinpi +//-------- T __nv_sinpif +FUNC1(sinpi) + +//-------- T __nv_sqrt +//-------- T __nv_sqrtf +FUNC1(sqrt) + +//-------- T __nv_tan +//-------- T __nv_tanf +FUNC1(tan) + +//-------- T __nv_tanh +//-------- T __nv_tanhf +FUNC1(tanh) + +//-------- T __nv_tgamma +//-------- T __nv_tgammaf +FUNC1(tgamma) + +//-------- T __nv_trunc +//-------- T __nv_truncf +FUNC1(trunc) + +//-------- T __nv_y0 +//-------- T __nv_y0f +FUNC1(y0) + +//-------- T __nv_y1 +//-------- T __nv_y1f +FUNC1(y1) + +//-------- T __nv_cyl_bessel_i0 +ATTR double __nv_cyl_bessel_i0(double x) { return __ocml_i0_f64(x); } + +//-------- T __nv_cyl_bessel_i0f +ATTR float __nv_cyl_bessel_i0f(float x) { return __ocml_i0_f32(x); } + +//-------- T __nv_cyl_bessel_i1 +ATTR double __nv_cyl_bessel_i1(double x) { return __ocml_i1_f64(x); } + +//-------- T __nv_cyl_bessel_i1f +ATTR float __nv_cyl_bessel_i1f(float x) { return __ocml_i1_f32(x); } + +//-------- T __nv_frexp +ATTR double __nv_frexp(double x, __private int *ptr) { return __ocml_frexp_f64(x, ptr); } + +//-------- T __nv_frexpf +ATTR float __nv_frexpf(float x, __private int *ptr) { return __ocml_frexp_f32(x, ptr); } + +//-------- T __nv_ilogb +ATTR int __nv_ilogb(double x) { return __ocml_ilogb_f64(x); } + +//-------- T __nv_ilogbf +ATTR int __nv_ilogbf(float x) { return __ocml_ilogb_f32(x); } + +//-------- T __nv_ldexp +ATTR double __nv_ldexp(double x, int i) { return __ocml_ldexp_f64(x, i); } + +//-------- T __nv_ldexpf +ATTR float __nv_ldexpf(float x, int i) { return __ocml_ldexp_f32(x, i); } + +//-------- T __nv_modf +ATTR double __nv_modf(double x, __private double *ptr) { return __ocml_modf_f64(x, ptr); } + +//-------- T __nv_modff +ATTR float __nv_modff(float x, __private float *ptr) { return __ocml_modf_f32(x, ptr); } + +//-------- T __nv_norm3d +ATTR double __nv_norm3d(double x, double y, double z) { return __ocml_len3_f64(x,y,z); } + +//-------- T __nv_norm3df +ATTR float __nv_norm3df(float x, float y, float z) { return __ocml_len3_f32(x,y,z); } + +//-------- T __nv_norm4d +ATTR double __nv_norm4d(double a, double b, double c, double d) { return __ocml_len4_f64(a,b,c,d); } + +//-------- T __nv_norm4df +ATTR float __nv_norm4df(float a, float b, float c, float d) { return __ocml_len4_f32(a,b,c,d); } + +//-------- T __nv_normcdf +ATTR double __nv_normcdf(double x) { return __ocml_ncdf_f64(x); } + +//-------- T __nv_normcdff +ATTR float __nv_normcdff(float x) { return __ocml_ncdf_f32(x); } + +//-------- T __nv_normcdfinv +ATTR double __nv_normcdfinv(double x) { return __ocml_ncdfinv_f64(x); } + +//-------- T __nv_normcdfinvf +ATTR float __nv_normcdfinvf(float x) { return __ocml_ncdfinv_f32(x); } + +//-------- T __nv_powi +ATTR double __nv_powi(double x, int n) { return __ocml_pown_f64(x, n); } + +//-------- T __nv_powi +ATTR float __nv_powif(float x, int n) { return __ocml_pown_f32(x, n); } + +//-------- T __nv_remquo +ATTR double __nv_remquo(double x, double y, __private int *ptr) { return __ocml_remquo_f64(x, y, ptr); } + +//-------- T __nv_remquof +ATTR float __nv_remquof(float x, float y, __private int *ptr) { return __ocml_remquo_f32(x, y, ptr); } + +//-------- T __nv_saturatef +ATTR float __nv_saturatef(float x) { return __ocml_min_f32(__ocml_max_f32(x, 0.0f), 1.0f); } + +//-------- T __nv_signbitd +ATTR int __nv_signbitd(double x) { return __ocml_signbit_f64(x); } + +//-------- T __nv_signbitf +ATTR int __nv_signbitf(float x) { return __ocml_signbit_f32(x); } + +//-------- T __nv_sincos +ATTR void __nv_sincos(double x, __private double * sptr, __private double *cptr) { (*sptr)=__ocml_sincos_f64(x, cptr); } + +//-------- T __nv_sincosf +ATTR void __nv_sincosf(float x, __private float * sptr, __private float *cptr) { (*sptr)=__ocml_sincos_f32(x, cptr); } + +//-------- T __nv_sincospi +ATTR void __nv_sincospi(double x, __private double * sptr, __private double *cptr) { (*sptr)=__ocml_sincospi_f64(x, cptr); } + +//-------- T __nv_sincospif +ATTR void __nv_sincosfpif(float x, __private float * sptr, __private float *cptr) { (*sptr)=__ocml_sincospi_f32(x, cptr); } + diff --git a/amd/device-libs/cuda2gcn/src/precision.cl b/amd/device-libs/cuda2gcn/src/precision.cl new file mode 100644 index 0000000000000..19c9b60755a70 --- /dev/null +++ b/amd/device-libs/cuda2gcn/src/precision.cl @@ -0,0 +1,56 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#define ATTR + +#define FUNC1F(root) \ + ATTR float __nv_fast_##root##f(float x) { return __ocml_##root##_f32(x); } +#define FUNC1(root) FUNC1F(root) + +#define FUNC2F(root) \ + ATTR float __nv_fast_##root##f(float x, float y) { return __ocml_##root##_f32(x, y); } +#define FUNC2(root) FUNC2F(root) + +#define FUNC3F(root) \ + ATTR float __nv_fast_##root##f(float x, float y, float z) { return __ocml_##root##_f32(x, y, z); } +#define FUNC3(root) FUNC3F(root) + +//-------- T __nv_fast_cosf +FUNC1(cos) + +//-------- T __nv_fast_exp10f +FUNC1(exp10) + +//-------- T __nv_fast_expf +FUNC1(exp) + +//-------- T __nv_fast_log10f +FUNC1(log10) + +//-------- T __nv_fast_log2f +FUNC1(log2) + +//-------- T __nv_fast_logf +FUNC1(log) + +//-------- T __nv_fast_powf +FUNC2(pow) + +//-------- T __nv_fast_sinf +FUNC1(sin) + +//-------- T __nv_fast_tanf +FUNC1(tan) + +//-------- T __nv_fast_fdividef +ATTR float __nv_fast_fdividef(float x, float y) { return native_divide(x, y); } + +//-------- T __nv_fast_sincosf +ATTR void __nv_fast_sincosf(float x, __private float * sptr, __private float *cptr) { (*sptr)=__ocml_sincos_f32(x, cptr); } + diff --git a/amd/device-libs/cuda2gcn/src/reinterpret.cl b/amd/device-libs/cuda2gcn/src/reinterpret.cl new file mode 100644 index 0000000000000..0d55cdedeeac9 --- /dev/null +++ b/amd/device-libs/cuda2gcn/src/reinterpret.cl @@ -0,0 +1,63 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((always_inline, const)) + +//-------- T __nv_double_as_longlong +ATTR long __nv_double_as_longlong(double x) +{ + return as_long(x); +} + +//-------- T __nv_float_as_int +ATTR int __nv_float_as_int(float x) +{ + return as_int(x); +} + +//-------- T __nv_float_as_uint +ATTR unsigned int __nv_float_as_uint(float x) +{ + return as_uint(x); +} + +//-------- T __nv_int_as_float +ATTR float __nv_int_as_float(int x) +{ + return as_float(x); +} + +//-------- T __nv_longlong_as_double +ATTR double __nv_longlong_as_double(long x) +{ + return as_double(x); +} + +//-------- T __nv_uint_as_float +ATTR float __nv_uint_as_float(unsigned int x) +{ + return as_float(x); +} + +//-------- T __nv_double2hiint +int __nv_double2hiint(double x) +{ + return (int) as_long(x) >> 32; +} + +//-------- T __nv_double2loint +int __nv_double2loint(double x) +{ + return (int) as_long(x); +} + +//-------- T __nv_hiloint2double +double __nv_hiloint2double(int x, int y) +{ + return as_double((long)x << 32 | y); +} + diff --git a/amd/device-libs/cuda2gcn/src/rounding.cl b/amd/device-libs/cuda2gcn/src/rounding.cl new file mode 100644 index 0000000000000..036282184d0da --- /dev/null +++ b/amd/device-libs/cuda2gcn/src/rounding.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#define ATTR __attribute__((const)) + +//-------- T __nv_llrint +ATTR long __nv_llrint(double x) { return (long)__ocml_rint_f64(x); } + +//-------- T __nv_llrintf +ATTR long __nv_llrintf(float x) { return (long)__ocml_rint_f32(x); } + +//-------- T __nv_llround +ATTR long __nv_llround(double x) { return (long)__ocml_round_f64(x); } + +//-------- T __nv_llroundf +ATTR long __nv_llroundf(float x) { return (long)__ocml_round_f32(x); } + diff --git a/amd/device-libs/doc/OCKL.md b/amd/device-libs/doc/OCKL.md new file mode 100644 index 0000000000000..62fc71d0ca8dc --- /dev/null +++ b/amd/device-libs/doc/OCKL.md @@ -0,0 +1,415 @@ +# OCKL User Guide + +* [Introduction](#introduction) + * [What Is OCKL](#what-is-ockl) +* [Using OCKL](#using-ocml) + * [Standard Usage](#standard-usage) + * [Controls](#controls) +* [Versioning](#versioning) +* [Naming convention](#naming-convention) +* [Supported functions](#supported-functions) + + +## Introduction +### What Is OCKL + +OCKL is an LLVM-IR bitcode library designed to provide access to certain hardware +and compiler capabilities needed by language runtimes. It should rarely be necessary +to call any of these functions directly from application code. Consider this library +a "detail" layer. + +## Using OCKL +### Standard Usage + +OCKL is expected to be used in a standard LLVM compilation flow as follows: + * Compile source modules to LLVM-IR bitcode (clang) + * Link together program bitcode with library bitcode including OCKL and OCLC. + * Run generic optimizations (opt) + * Code generation (llc) + +### Controls + +OCKL supports a number of controls that are provided by linking in specifically named inline +functions. These functions are inlined at optimization time and result in specific paths +taken with no control flow overhead. These functions all have the form (in C) + + __attribute__((always_inline, const)) int + __oclc_control(void) + { return 1; } // or 0 to disable + +The currently supported control are + * `finite_only_opt` - floating point Inf and NaN are never expected to be consumed or produced + * `unsafe_math_opt` - lower accuracy results may be produced with higher performance + * `ISA_version` - an integer representation of the ISA version of the target device + * `daz_opt` - unused and deprecated. Will be removed in the future. + * `correctly_rounded_sqrt32` - unused and deprecated. Will be removed in the future. + +### Versioning + +OCKL usually ships as a single LLVM-IR bitcode file named + + ocml-{LLVM rev}-{OCKL rev}.bc + +where `{LLVM rev}` is the version of LLVM used to create the file, of the +form X.Y, e.g. 3.8, and `{OCKL rev}` is the OCKL library version of the form X.Y, currently 0.9. + +### Naming convention + +OCKL functions follow a simple naming convention: + + __ockl_{function}_{type suffix} + +where {type suffix} generally indicates the type of the arguments and/or returned result using a type letter, +e.g. "u" for unsigned integer, and a bit width, e.g. 32. + +### Supported functions + +The following table lists the available functions along with a brief description of each: + +| **function** | **Brief Description** | +| :--- | :--- | +| `uchar __ockl_clz_u8(uchar);` | Count leading zeroes | +| `ushort __ockl_clz_u16(ushort);` | | +| `uint __ockl_clz_u32(uint);` | | +| `ulong __ockl_clz_u64(ulong);` | | +| - | | +| `uchar __ockl_ctz_u8(uchar);` | Count trailing zeroes | +| `ushort __ockl_ctz_u16(ushort);` | | +| `uint __ockl_ctz_u32(uint);` | | +| `ulong __ockl_ctz_u64(ulong);` | | +| - | | +| `uint __ockl_popcount_u32(uint);` | Count nonzero bits | +| `ulong __ockl_popcount_u64(ulong);` | | +| - | | +| `int __ockl_add_sat_i32(int,int);` | Add with saturation | +| `uint __ockl_add_sat_u32(uint,uint);` | | +| `long __ockl_add_sat_i64(long,long);` | | +| `ulong __ockl_add_sat_u64(ulong,ulong);` | | +| - | | +| `int __ockl_sub_sat_i32(int,int);` | Subtract with saturation | +| `uint __ockl_sub_sat_u32(uint,uint);` | | +| `long __ockl_sub_sat_i64(long,long);` | | +| `ulong __ockl_sub_sat_u64(ulong,ulong);` | | +| - | | +| `int __ockl_mul_hi_i32(int,int);` | High part of multiplication | +| `uint __ockl_mul_hi_u32(uint,uint);` | | +| `long __ockl_mul_hi_i64(long,long);` | | +| `ulong __ockl_mul_hi_u64(ulong,ulong);` | | +| - | | +| `int __ockl_mul24_i32(int,int);` | Multiply assuming operands fit in 24 bits | +| `uint __ockl_mul24_u32(uint,uint);` | | +| - | | +| `ulong __ockl_cyclectr_u64(void);` | Current value of free running 64-bit clock counter | +| `ulong __ockl_steadyctr_u64(void);` | Current value of constant speed 64-bit clock counter | +| - | | +| `uint __ockl_activelane_u32(void);` | Index of currently lane counting only active lanes in wavefront | +| - | | +| `half __ockl_wfred_add_f16(half x);` | ADD reduction across wavefront | +| `float __ockl_wfred_add_f32(float x);` | | +| `double __ockl_wfred_add_f64(double x);` | | +| `int __ockl_wfred_add_i32(int x);` | | +| `long __ockl_wfred_add_i64(long x);` | | +| `uint __ockl_wfred_add_u32(uint x);` | | +| `ulong __ockl_wfred_add_u64(ulong x);` | AND reduction across wavefront | +| `int __ockl_wfred_and_i32(int x);` | | +| `long __ockl_wfred_and_i64(long x);` | | +| `uint __ockl_wfred_and_u32(uint x);` | | +| `ulong __ockl_wfred_and_u64(ulong x);` | | +| `half __ockl_wfred_max_f16(half x);` | MAX reduction across wavefront | +| `float __ockl_wfred_max_f32(float x);` | | +| `double __ockl_wfred_max_f64(double x);` | | +| `int __ockl_wfred_max_i32(int x);` | | +| `long __ockl_wfred_max_i64(long x);` | | +| `uint __ockl_wfred_max_u32(uint x);` | | +| `ulong __ockl_wfred_max_u64(ulong x);` | | +| `half __ockl_wfred_min_f16(half x);` | MIN reduction across wavefront | +| `float __ockl_wfred_min_f32(float x);` | | +| `double __ockl_wfred_min_f64(double x);` | | +| `int __ockl_wfred_min_i32(int x);` | | +| `long __ockl_wfred_min_i64(long x);` | | +| `uint __ockl_wfred_min_u32(uint x);` | | +| `ulong __ockl_wfred_min_u64(ulong x);` | | +| `int __ockl_wfred_or_i32(int x);` | OR reduction across wavefront | +| `long __ockl_wfred_or_i64(long x);` | | +| `uint __ockl_wfred_or_u32(uint x);` | | +| `ulong __ockl_wfred_or_u64(ulong x);` | | +| `int __ockl_wfred_xor_i32(int x);` | XOR reduction across wavefront | +| `long __ockl_wfred_xor_i64(long x);` | | +| `uint __ockl_wfred_xor_u32(uint x);` | | +| `ulong __ockl_wfred_xor_u64(ulong x);` | | +| `half __ockl_wfscan_add_f16(half x, bool inclusive);` | ADD scan across wavefront | +| `float __ockl_wfscan_add_f32(float x, bool inclusive);` | | +| `double __ockl_wfscan_add_f64(double x, bool inclusive);` | | +| `int __ockl_wfscan_add_i32(int x, bool inclusive);` | | +| `long __ockl_wfscan_add_i64(long x, bool inclusive);` | | +| `uint __ockl_wfscan_add_u32(uint x, bool inclusive);` | | +| `ulong __ockl_wfscan_add_u64(ulong x, bool inclusive);` | | +| `int __ockl_wfscan_and_i32(int x, bool inclusive);` | AND scan across wavefront | +| `long __ockl_wfscan_and_i64(long x, bool inclusive);` | | +| `uint __ockl_wfscan_and_u32(uint x, bool inclusive);` | | +| `ulong __ockl_wfscan_and_u64(ulong x, bool inclusive);` | | +| `half __ockl_wfscan_max_f16(half x, bool inclusive);` | MAX scan across wavefront | +| `float __ockl_wfscan_max_f32(float x, bool inclusive);` | | +| `double __ockl_wfscan_max_f64(double x, bool inclusive);` | | +| `int __ockl_wfscan_max_i32(int x, bool inclusive);` | | +| `long __ockl_wfscan_max_i64(long x, bool inclusive);` | | +| `uint __ockl_wfscan_max_u32(uint x, bool inclusive);` | | +| `ulong __ockl_wfscan_max_u64(ulong x, bool inclusive);` | | +| `half __ockl_wfscan_min_f16(half x, bool inclusive);` | MIN scan across wavefront | +| `float __ockl_wfscan_min_f32(float x, bool inclusive);` | | +| `double __ockl_wfscan_min_f64(double x, bool inclusive);` | | +| `int __ockl_wfscan_min_i32(int x, bool inclusive);` | | +| `long __ockl_wfscan_min_i64(long x, bool inclusive);` | | +| `uint __ockl_wfscan_min_u32(uint x, bool inclusive);` | | +| `ulong __ockl_wfscan_min_u64(ulong x, bool inclusive);` | | +| `int __ockl_wfscan_or_i32(int x, bool inclusive);` | OR scan across wavefront | +| `long __ockl_wfscan_or_i64(long x, bool inclusive);` | | +| `uint __ockl_wfscan_or_u32(uint x, bool inclusive);` | | +| `ulong __ockl_wfscan_or_u64(ulong x, bool inclusive);` | | +| `int __ockl_wfscan_xor_i32(int x, bool inclusive);` | XOR scan across wavefront | +| `long __ockl_wfscan_xor_i64(long x, bool inclusive);` | | +| `uint __ockl_wfscan_xor_u32(uint x, bool inclusive);` | | +| `ulong __ockl_wfscan_xor_u64(ulong x, bool inclusive);` | | +| `uint __ockl_wfbcast_u32(uint x, uint i);` | Broadcast to wavefront | +| `ulong __ockl_wfbcast_u64(ulong x, uint i);` | | +| - | | +| `bool __ockl_wfany_i32(int e);` | Detect any nonzero across wavefront | +| `bool __ockl_wfall_i32(int e);` | Detect all nozero across wavefront | +| `bool __ockl_wfsame_i32(int e);` | Detect same across wavefront | +| - | | +| `uint __ockl_bfm_u32(uint,uint);` | Bit field mask | +| `int __ockl_bfe_i32(int, uint, uint);` | Bit field extract | +| `uint __ockl_bfe_u32(uint,uint,uint);` | | +| `uint __ockl_bitalign_u32(uint,uint,uint);` | Align on bit boundary | +| `uint __ockl_bytealign_u32(uint,uint,uint);` | Align on byte boundary | +| `uint __ockl_lerp_u32(uint,uint,uint);` | Add each byte with prescribed carry | +| `float __ockl_max3_f32(float,float,float);` | Max of 3 | +| `half __ockl_max3_f16(half,half,half);` | | +| `int __ockl_max3_i32(int,int,int);` | | +| `uint __ockl_max3_u32(uint,uint,uint);` | | +| `float __ockl_median3_f32(float,float,float);` | Median of 3 | +| `half __ockl_median3_f16(half,half,half);` | | +| `int __ockl_median3_i32(int,int,int);` | | +| `uint __ockl_median3_u32(uint,uint,uint);` | | +| `float __ockl_min3_f32(float,float,float);` | Min of 3 | +| `half __ockl_min3_f16(half,half,half);` | | +| `int __ockl_min3_i32(int,int,int);` | | +| `uint __ockl_min3_u32(uint,uint,uint);` | | +| `ulong __ockl_mqsad_u64(ulong, uint, ulong);` | Masked rolling SAD | +| `uint __ockl_pack_u32(float4);` | Pack vector to bytes | +| `ulong __ockl_qsad_u64(ulong, uint, ulong);` | Rolling SAD | +| `uint __ockl_msad_u32(uint,uint,uint);` | Masked SAD | +| `uint __ockl_sad_u32(uint,uint,uint);` | SAD | +| `uint __ockl_sadd_u32(uint,uint,uint);` | 32-bit SAD | +| `uint __ockl_sadhi_u32(uint,uint,uint);` | SAD accululating to high half | +| `uint __ockl_sadw_u32(uint,uint,uint);` | 16-bit SAD | +| `float __ockl_unpack0_f32(uint);` | Extract byte and convert to float | +| `float __ockl_unpack1_f32(uint);` | | +| `float __ockl_unpack2_f32(uint);` | | +| `float __ockl_unpack3_f32(uint);` | | +| - | | +| `float4 __ockl_image_load_1D(TSHARP i, int c);` | Load from 1D image | +| `float4 __ockl_image_load_1Da(TSHARP i, int2 c);` | Load from 1D image array | +| `float4 __ockl_image_load_1Db(TSHARP i, int c);` | Load from 1D buffered image | +| `float4 __ockl_image_load_2D(TSHARP i, int2 c);` | Load from 2D image | +| `float4 __ockl_image_load_2Da(TSHARP i, int4 c);` | Load from 2D image array | +| `float __ockl_image_load_2Dad(TSHARP i, int4 c);` | Load from 2D depth image array | +| `float __ockl_image_load_2Dd(TSHARP i, int2 c);` | Load from 2D depth image | +| `float4 __ockl_image_load_3D(TSHARP i, int4 c);` | Load from 3D image | +| `float4 __ockl_image_load_CM(TSHARP i, int2 c, int f);` | Load from cubemap | +| `float4 __ockl_image_load_CMa(TSHARP i, int4 c, int f);` | Load from cubemap array | +| - | | +| `float4 __ockl_image_load_mip_1D(TSHARP i, int c, int l);` | Load from mipmapped image | +| `float4 __ockl_image_load_mip_1Da(TSHARP i, int2 c, int l);` | | +| `float4 __ockl_image_load_mip_2D(TSHARP i, int2 c, int l);` | | +| `float4 __ockl_image_load_mip_2Da(TSHARP i, int4 c, int l);` | | +| `float __ockl_image_load_mip_2Dad(TSHARP i, int4 c, int l);` | | +| `float __ockl_image_load_mip_2Dd(TSHARP i, int2 c, int l);` | | +| `float4 __ockl_image_load_mip_3D(TSHARP i, int4 c, int l);` | | +| `float4 __ockl_image_load_mip_CM(TSHARP i, int2 c, int f, int l);` | | +| `float4 __ockl_image_load_mip_CMa(TSHARP i, int4 c, int f, int l);` | | +| - | | +| `half4 __ockl_image_loadh_1D(TSHARP i, int c);` | Load from image returning half precision | +| `half4 __ockl_image_loadh_1Da(TSHARP i, int2 c);` | | +| `half4 __ockl_image_loadh_1Db(TSHARP i, int c);` | | +| `half4 __ockl_image_loadh_2D(TSHARP i, int2 c);` | | +| `half4 __ockl_image_loadh_2Da(TSHARP i, int4 c);` | | +| `half4 __ockl_image_loadh_3D(TSHARP i, int4 c);` | | +| `half4 __ockl_image_loadh_CM(TSHARP i, int2 c, int f);` | | +| `half4 __ockl_image_loadh_CMa(TSHARP i, int4 c, int f);` | | +| `half4 __ockl_image_loadh_mip_1D(TSHARP i, int c, int l);` | | +| `half4 __ockl_image_loadh_mip_1Da(TSHARP i, int2 c, int l);` | | +| `half4 __ockl_image_loadh_mip_2D(TSHARP i, int2 c, int l);` | | +| `half4 __ockl_image_loadh_mip_2Da(TSHARP i, int4 c, int l);` | | +| `half4 __ockl_image_loadh_mip_3D(TSHARP i, int4 c, int l);` | | +| `half4 __ockl_image_loadh_mip_CM(TSHARP i, int2 c, int f, int l);` | | +| `half4 __ockl_image_loadh_mip_CMa(TSHARP i, int4 c, int f, int l);` | | +| - | | +| `void __ockl_image_store_1D(TSHARP i, int c, float4 p);` | Store to image | +| `void __ockl_image_store_1Da(TSHARP i, int2 c, float4 p);` | | +| `void __ockl_image_store_1Db(TSHARP i, int c, float4 p);` | | +| `void __ockl_image_store_2D(TSHARP i, int2 c, float4 p);` | | +| `void __ockl_image_store_2Da(TSHARP i, int4 c, float4 p);` | | +| `void __ockl_image_store_2Dad(TSHARP i, int4 c, float p);` | | +| `void __ockl_image_store_2Dd(TSHARP i, int2 c, float p);` | | +| `void __ockl_image_store_3D(TSHARP i, int4 c, float4 p);` | | +| `void __ockl_image_store_CM(TSHARP i, int2 c, int f, float4 p);` | | +| `void __ockl_image_store_CMa(TSHARP i, int4 c, int f, float4 p);` | | +| `void __ockl_image_store_lod_1D(TSHARP i, int c, int l, float4 p);` | Store to level of mipmapped image | +| - | | +| `void __ockl_image_store_lod_1Da(TSHARP i, int2 c, int l, float4 p);` | | +| `void __ockl_image_store_lod_2D(TSHARP i, int2 c, int l, float4 p);` | | +| `void __ockl_image_store_lod_2Da(TSHARP i, int4 c, int l, float4 p);` | | +| `void __ockl_image_store_lod_2Dad(TSHARP i, int4 c, int l, float p);` | | +| `void __ockl_image_store_lod_2Dd(TSHARP i, int2 c, int l, float p);` | | +| `void __ockl_image_store_lod_3D(TSHARP i, int4 c, int l, float4 p);` | | +| `void __ockl_image_store_lod_CM(TSHARP i, int2 c, int f, int l, float4 p);` | | +| `void __ockl_image_store_lod_CMa(TSHARP i, int4 c, int f, int l, float4 p);` | | +| - | | +| `void __ockl_image_storeh_1D(TSHARP i, int c, half4 p);` | Store half precision pixel to image| +| `void __ockl_image_storeh_1Da(TSHARP i, int2 c, half4 p);` | | +| `void __ockl_image_storeh_1Db(TSHARP i, int c, half4 p);` | | +| `void __ockl_image_storeh_2D(TSHARP i, int2 c, half4 p);` | | +| `void __ockl_image_storeh_2Da(TSHARP i, int4 c, half4 p);` | | +| `void __ockl_image_storeh_3D(TSHARP i, int4 c, half4 p);` | | +| `void __ockl_image_storeh_CM(TSHARP i, int2 c, int f, half4 p);` | | +| `void __ockl_image_storeh_CMa(TSHARP i, int4 c, int f, half4 p);` | | +| - | | +| `void __ockl_image_storeh_lod_1D(TSHARP i, int c, int l, half4 p);` | Store half precision pixel to level of mipmapped image | +| `void __ockl_image_storeh_lod_1Da(TSHARP i, int2 c, int l, half4 p);` | | +| `void __ockl_image_storeh_lod_2D(TSHARP i, int2 c, int l, half4 p);` | | +| `void __ockl_image_storeh_lod_2Da(TSHARP i, int4 c, int l, half4 p);` | | +| `void __ockl_image_storeh_lod_3D(TSHARP i, int4 c, int l, half4 p);` | | +| `void __ockl_image_storeh_lod_CM(TSHARP i, int2 c, int f, int l, half4 p);` | | +| `void __ockl_image_storeh_lod_CMa(TSHARP i, int4 c, int f, int l, half4 p);` | | +| - | | +| `float4 __ockl_image_sample_1D(TSHARP i, SSHARP s, float c);` | Sample image | +| `float4 __ockl_image_sample_1Da(TSHARP i, SSHARP s, float2 c);` | | +| `float4 __ockl_image_sample_2D(TSHARP i, SSHARP s, float2 c);` | | +| `float4 __ockl_image_sample_2Da(TSHARP i, SSHARP s, float4 c);` | | +| `float __ockl_image_sample_2Dad(TSHARP i, SSHARP s, float4 c);` | | +| `float __ockl_image_sample_2Dd(TSHARP i, SSHARP s, float2 c);` | | +| `float4 __ockl_image_sample_3D(TSHARP i, SSHARP s, float4 c);` | | +| `float4 __ockl_image_sample_CM(TSHARP i, SSHARP s, float4 c);` | | +| `float4 __ockl_image_sample_CMa(TSHARP i, SSHARP s, float4 c);` | | +| - | | +| `float4 __ockl_image_sample_grad_1D(TSHARP i, SSHARP s, float c, float dx, float dy);` | Sample mipmapped image using gradient | +| `float4 __ockl_image_sample_grad_1Da(TSHARP i, SSHARP s, float2 c, float dx, float dy);` | | +| `float4 __ockl_image_sample_grad_2D(TSHARP i, SSHARP s, float2 c, float2 dx, float2 dy);` | | +| `float4 __ockl_image_sample_grad_2Da(TSHARP i, SSHARP s, float4 c, float2 dx, float2 dy);` | | +| `float __ockl_image_sample_grad_2Dad(TSHARP i, SSHARP s, float4 c, float2 dx, float2 dy);` | | +| `float __ockl_image_sample_grad_2Dd(TSHARP i, SSHARP s, float2 c, float2 dx, float2 dy);` | | +| `float4 __ockl_image_sample_grad_3D(TSHARP i, SSHARP s, float4 c, float4 dx, float4 dy);` | | +| - | | +| `float4 __ockl_image_sample_lod_1D(TSHARP i, SSHARP s, float c, float l);` | Sample mipmapped image using LOD | +| `float4 __ockl_image_sample_lod_1Da(TSHARP i, SSHARP s, float2 c, float l);` | | +| `float4 __ockl_image_sample_lod_2D(TSHARP i, SSHARP s, float2 c, float l);` | | +| `float4 __ockl_image_sample_lod_2Da(TSHARP i, SSHARP s, float4 c, float l);` | | +| `float __ockl_image_sample_lod_2Dad(TSHARP i, SSHARP s, float4 c, float l);` | | +| `float __ockl_image_sample_lod_2Dd(TSHARP i, SSHARP s, float2 c, float l);` | | +| `float4 __ockl_image_sample_lod_3D(TSHARP i, SSHARP s, float4 c, float l);` | | +| `float4 __ockl_image_sample_lod_CM(TSHARP i, SSHARP s, float4 c, float l);` | | +| `float4 __ockl_image_sample_lod_CMa(TSHARP i, SSHARP s, float4 c, float l);` | | +| - | | +| `half4 __ockl_image_sampleh_1D(TSHARP i, SSHARP s, float c);` | Sample image returning half precision | +| `half4 __ockl_image_sampleh_1Da(TSHARP i, SSHARP s, float2 c);` | | +| `half4 __ockl_image_sampleh_2D(TSHARP i, SSHARP s, float2 c);` | | +| `half4 __ockl_image_sampleh_2Da(TSHARP i, SSHARP s, float4 c);` | | +| `half4 __ockl_image_sampleh_3D(TSHARP i, SSHARP s, float4 c);` | | +| `half4 __ockl_image_sampleh_CM(TSHARP i, SSHARP s, float4 c);` | | +| `half4 __ockl_image_sampleh_CMa(TSHARP i, SSHARP s, float4 c);` | | +| - | | +| `half4 __ockl_image_sampleh_grad_1D(TSHARP i, SSHARP s, float c, float dx, float dy);` | Sample mipmapped image using gradient returning half precision | +| `half4 __ockl_image_sampleh_grad_1Da(TSHARP i, SSHARP s, float2 c, float dx, float dy);` | | +| `half4 __ockl_image_sampleh_grad_2D(TSHARP i, SSHARP s, float2 c, float2 dx, float2 dy);` | | +| `half4 __ockl_image_sampleh_grad_2Da(TSHARP i, SSHARP s, float4 c, float2 dx, float2 dy);` | | +| `half4 __ockl_image_sampleh_grad_3D(TSHARP i, SSHARP s, float4 c, float4 dx, float4 dy);` | | +| - | | +| `half4 __ockl_image_sampleh_lod_1D(TSHARP i, SSHARP s, float c, float l);` | Sample mipmapped image using LOD returning half precision | +| `half4 __ockl_image_sampleh_lod_1Da(TSHARP i, SSHARP s, float2 c, float l);` | | +| `half4 __ockl_image_sampleh_lod_2D(TSHARP i, SSHARP s, float2 c, float l);` | | +| `half4 __ockl_image_sampleh_lod_2Da(TSHARP i, SSHARP s, float4 c, float l);` | | +| `half4 __ockl_image_sampleh_lod_3D(TSHARP i, SSHARP s, float4 c, float l);` | | +| `half4 __ockl_image_sampleh_lod_CM(TSHARP i, SSHARP s, float4 c, float l);` | | +| `half4 __ockl_image_sampleh_lod_CMa(TSHARP i, SSHARP s, float4 c, float l);` | | +| - | | +| `float4 __ockl_image_gather4r_2D(TSHARP i, SSHARP s, float2 c);` | Gather 2x2 channel from image | +| `float4 __ockl_image_gather4g_2D(TSHARP i, SSHARP s, float2 c);` | | +| `float4 __ockl_image_gather4b_2D(TSHARP i, SSHARP s, float2 c);` | | +| `float4 __ockl_image_gather4a_2D(TSHARP i, SSHARP s, float2 c);` | | +| - | | +| `int __ockl_image_array_size_1Da(TSHARP i);` | Get image array size | +| `int __ockl_image_array_size_2Da(TSHARP i);` | | +| `int __ockl_image_array_size_2Dad(TSHARP i);` | | +| `int __ockl_image_array_size_CMa(TSHARP i);` | | +| - | | +| `int __ockl_image_channel_data_type_1D(TSHARP i);` | Get image channel data type | +| `int __ockl_image_channel_data_type_1Da(TSHARP i);` | | +| `int __ockl_image_channel_data_type_1Db(TSHARP i);` | | +| `int __ockl_image_channel_data_type_2D(TSHARP i);` | | +| `int __ockl_image_channel_data_type_2Da(TSHARP i);` | | +| `int __ockl_image_channel_data_type_2Dad(TSHARP i);` | | +| `int __ockl_image_channel_data_type_2Dd(TSHARP i);` | | +| `int __ockl_image_channel_data_type_3D(TSHARP i);` | | +| `int __ockl_image_channel_data_type_CM(TSHARP i);` | | +| `int __ockl_image_channel_data_type_CMa(TSHARP i);` | | +| - | | +| `int __ockl_image_channel_order_1D(TSHARP i);` | Get image channel order | +| `int __ockl_image_channel_order_1Da(TSHARP i);` | | +| `int __ockl_image_channel_order_1Db(TSHARP i);` | | +| `int __ockl_image_channel_order_2D(TSHARP i);` | | +| `int __ockl_image_channel_order_2Da(TSHARP i);` | | +| `int __ockl_image_channel_order_2Dad(TSHARP i);` | | +| `int __ockl_image_channel_order_2Dd(TSHARP i);` | | +| `int __ockl_image_channel_order_3D(TSHARP i);` | | +| `int __ockl_image_channel_order_CM(TSHARP i);` | | +| `int __ockl_image_channel_order_CMa(TSHARP i);` | | +| - | | +| `int __ockl_image_depth_3D(TSHARP i);` | Get 3D image depth | +| - | | +| `int __ockl_image_height_2D(TSHARP i);` | Get image height | +| `int __ockl_image_height_2Da(TSHARP i);` | | +| `int __ockl_image_height_2Dad(TSHARP i);` | | +| `int __ockl_image_height_2Dd(TSHARP i);` | | +| `int __ockl_image_height_3D(TSHARP i);` | | +| `int __ockl_image_height_CM(TSHARP i);` | | +| `int __ockl_image_height_CMa(TSHARP i);` | | +| - | | +| `int __ockl_image_num_mip_levels_1D(TSHARP i);` | Get number of levels in mipmapped image | +| `int __ockl_image_num_mip_levels_1Da(TSHARP i);` | | +| `int __ockl_image_num_mip_levels_2D(TSHARP i);` | | +| `int __ockl_image_num_mip_levels_2Da(TSHARP i);` | | +| `int __ockl_image_num_mip_levels_2Dad(TSHARP i);` | | +| `int __ockl_image_num_mip_levels_2Dd(TSHARP i);` | | +| `int __ockl_image_num_mip_levels_3D(TSHARP i);` | | +| `int __ockl_image_num_mip_levels_CM(TSHARP i);` | | +| `int __ockl_image_num_mip_levels_CMa(TSHARP i);` | | +| - | | +| `int __ockl_image_width_1D(TSHARP i);` | Get image width | +| `int __ockl_image_width_1Da(TSHARP i);` | | +| `int __ockl_image_width_1Db(TSHARP i);` | | +| `int __ockl_image_width_2D(TSHARP i);` | | +| `int __ockl_image_width_2Da(TSHARP i);` | | +| `int __ockl_image_width_2Dad(TSHARP i);` | | +| `int __ockl_image_width_2Dd(TSHARP i);` | | +| `int __ockl_image_width_3D(TSHARP i);` | | +| `int __ockl_image_width_CM(TSHARP i);` | | +| `int __ockl_image_width_CMa(TSHARP i);` | | +| - | | +| `size_t __ockl_get_global_offset(uint);` | Get grid global offset (OpenCL) of dimension | +| `size_t __ockl_get_global_id(uint);` | Get workitem global ID of dimension | +| `size_t __ockl_get_local_id(uint);` | Get workitem local ID of dimension | +| `size_t __ockl_get_group_id(uint);` | Get ID of group workitem resides in of dimension | +| `size_t __ockl_get_global_size(uint);` | Get global size of dimension | +| `size_t __ockl_get_local_size(uint);` | Get local size of dimension | +| `size_t __ockl_get_num_groups(uint);` | Get number of groups in dimension | +| `uint __ockl_get_work_dim(void);` | Get grid number of dimensions | +| `size_t __ockl_get_enqueued_local_size(uint);` | Get enqueued local size of dimension | +| `size_t __ockl_get_global_linear_id(void);` | Get global linear ID of workitem| +| `size_t __ockl_get_local_linear_id(void);` | Get local linear ID of workitem | +| - | | +| `bool __ockl_is_local_addr(const void *);` | Test if generic address is local | +| `bool __ockl_is_private_addr(const void *);` | Test if generic address is private | +| `__global void * __ockl_to_global(void *);` | Convert generic address to global address | +| `__local void * __ockl_to_local(void *);` | Convert generic address to local address | +| `__private void * __ockl_to_private(void *);` | Convert generic address to private address | diff --git a/amd/device-libs/doc/OCML.md b/amd/device-libs/doc/OCML.md new file mode 100644 index 0000000000000..99c56cc11185a --- /dev/null +++ b/amd/device-libs/doc/OCML.md @@ -0,0 +1,203 @@ +# OCML User Guide + +* [Introduction](#introduction) + * [What Is OCML](#what-is-ocml) +* [Using OCML](#using-ocml) + * [Standard Usage](#standard-usage) + * [Controls](#controls) +* [Versioning](#versioning) +* [Tables](#tables) +* [Naming convention](#naming-convention) +* [Supported functions](#supported-functions) + + +## Introduction +### What Is OCML + +OCML is an LLVM-IR bitcode library designed to relieve language compiler and runtime implementers of the burden of implementing efficient and accurate mathematical functions. It is essentially a “libm” in intermediate representation with a fixed, simple API that can be linked in to supply the implementations of most standard low-level mathematical functions provided by the language. + +## Using OCML +### Standard Usage + +OCML is expected to be used in a standard LLVM compilation flow as follows: + * Compile source modules to LLVM-IR bitcode (clang) + * Link program bitcode, “wrapper” bitcode, OCML bitcode, other device library bitcode, and OCML control functions (llvm-link) + * Generic optimizations (opt) + * Code generation (llc) + +Here, “wrapper” bitcode denotes a thin library responsible for mapping language specific mangled built-in function calls as produced by clang to the OCML API. An example for handling "sqrt" might look like + + extern "C" __attribute__((const)) float __ocml_sqrt_f32(float); + float sqrt(float x) { return __ocml_sqrt_f32(x); } + +The next section describes OCML controls and how to use them. + +### Controls + +OCML (and a few other device libraries) requires a number of control variables definitions to be provided. These definitions may be provided by linking in specific OCLC libraries which define one specifically named variable or via other runtime specific means. These variables are known at optimization time and optimizations will result in specific paths taken with no control flow overhead. These variables all have the form (in C) + +`__constant const int __oclc_ = N;` + + +The currently supported control ``s and values `N` are + * `finite_only_opt` - floating point Inf and NaN are never expected to be consumed or produced. `N` may be 1 (on/true/enabled), or 0 (off/false/disabled). + * `unsafe_math_opt` - lower accuracy results may be produced with higher performance. `N` may be 1 (on/true/enabled) or 0 (off/false/disabled). + * `daz_opt` - subnormal values consumed and produced may be flushed to zero. `N`may be 1 (on/true/enabled) or 0 (off/false/disabled). + * `wavefrontsize64` - the wave front size is 64. `N` may be 1 (on/true/enabled) or 0 (off/false/disabled). Very few current devices support a value of 0. + * `ISA_version` - an integer representation of the ISA version of the target device + +The language runtime can link a specific set of OCLC control libraries to properly configure OCML and other device libraries which also use the controls. If linking OCLC libraries is used to define the control variables, then the runtime must link in: + +- Exactly one of `oclc_daz_opt_on.amdgcn.bc` or `oclc_daz_opt_off.amdgcn.bc` depending on the kernel's requirements +- Exactly one of `oclc_finite_only_on.amdgcn.bc` or `oclc_finite_only_off.amdgcn.bc` depending on the kernel's requirements +- Exactly one of `oclc_unsafe_math_on.amdgcn.bc` or `oclc_unsafe_math_off.amdgcn.bc` depending on the kernel's requirements +- Exactly one of `oclc_wavefrontsize64_on.amdgcn.bc` or `oclc_wavefrontsize64_off.amdgcn.bc` depending on the kernel's requirements +- Exactly one of `oclc_isa_version_XYZ.amdgcn.bc` where XYZ is the suffix of the `gfxXYZ` target name the kernel is being compiled for. + +If these rules are not followed, link time or execution time errors may result. + +### Versioning + +OCML ships within the larger release as a single LLVM-IR bitcode file named + + ocml.amdgcn.bc + +Bitcode linking errors are possible if the library is not in-sync with the compiler shipped with the same release. + +### Tables + +Some OCML functions require access to tables of constants. These tables are currently named +with the prefix `__ocmltbl_` and are placed in LLVM address space 2. + +### Naming convention + +OCML functions follow a simple naming convention: + + __ocml_{function}_{type suffix} + +where `{function}` is generally the familiar libm name of the function, and `{type suffix}` indicates the type of the floating point arguments or results, and is one of + * `f16` – 16 bit floating point (half precision) + * `f32` – 32 bit floating point (single precision) + * `f64` – 64 bit floating point (double precision) + +For example, `__ocml_sqrt_f32` is the name of the OCML single precision square root function. + +OCML does not currently support higher precision than double precision due to the lack of hardware support for such precisions. + +### Supported functions + +The following table contains a list of {function} currently supported by OCML, a brief description of each, and the maximum relative error in ULPs for each floating point type. A “c” in the last 3 columns indicates that the function is required to be correctly rounded. + +| **{function}** | **Description** | **f32 max err** | **f64 max err** | **f16 max err** | +| --- | --- | --- | --- | --- | +| acos | arc cosine | 4 | 4 | 2 | +| acosh | arc hyperbolic cosine | 4 | 4 | 2 | +| acospi | arc cosine / π | 5 | 5 | 2 | +| add_{rm} | add with specific rounding mode | c | c | c | +| asin | arc sine | 4 | 4 | 2 | +| asinh | arc hyperbolic sin | 4 | 4 | 2 | +| asinpi | arc sine / pi | 5 | 5 | 2 | +| atan2 | two argument arc tangent | 6 | 6 | 2 | +| atan2pi | two argument arc tangent / pi | 6 | 6 | 2 | +| atan | single argument arc tangent | 5 | 5 | 2 | +| atanh | arc hyperbolic tangent | 5 | 5 | 2 | +| atanpi | single argument arc tangent / pi | 5 | 5 | 2 | +| cbrt | cube root | 2 | 2 | 2 | +| ceil | round upwards to integer | c | c | c | +| copysign | copy sign of second argument to absolute value of first | 0 | 0 | 0 | +| cos | cosine | 4 | 4 | 2 | +| cosh | hyperbolic cosine | 4 | 4 | 2 | +| cospi | cosine of argument times pi | 4 | 4 | 2 | +| div_{rm} | correctly rounded division with specific rounding mode | c | c | c | +| erf | error function | 16 | 16 | 4 | +| erfc | complementary error function | 16 | 16 | 4 | +| erfcinv | inverse complementary error function | 7 | 8 | 3 | +| erfcx | scaled error function | 6 | 6 | 2 | +| erfinv | inverse error function | 3 | 8 | 2 | +| exp10 | 10x | 3 | 3 | 2 | +| exp2 | 2x | 3 | 3 | 2 | +| exp | ex | 3 | 3 | 2 | +| expm1 | ex - 1, accurate at 0 | 3 | 3 | 2 | +| fabs | absolute value | 0 | 0 | 0 | +| fdim | positive difference | c | c | c | +| floor | round downwards to integer | c | c | c | +| fma[_{rm}] | fused (i.e. singly rounded) multiply-add, with optional specific rounding | c | c | c | +| fmax | maximum, avoids NaN | 0 | 0 | 0 | +| fmin | minimum, avoids NaN | 0 | 0 | 0 | +| fmod | floating point remainder | 0 | 0 | 0 | +| fpclassify | classify floating point | - | - | - | +| fract | fractional part | c | c | c | +| frexp | extract significand and exponent | 0 | 0 | 0 | +| hypot | length, with overflow control | 4 | 4 | 2 | +| i0 | modified Bessel function of the first kind, order 0, I0 | 6 | 6 | 2 | +| i1 | modified Bessel function of the first kind, order 1, I1 | 6 | 6 | 2 | +| ilogb | extract exponent | 0 | 0 | 0 | +| isfinite | tests finiteness | - | - | - | +| isinf | test for Inf | - | - | - | +| isnan | test for NaN | - | - | - | +| isnormal | test for normal | - | - | - | +| j0 | Bessel function of the first kind, order 0, J0 | 6 (<12) | 6 (<12) | 2 (<12) | +| j1 | Bessel function of the first kind, order 1, J1 | 6 (<12) | 6 (<12) | 2 (<12) | +| ldexp | multiply by 2 raised to an integral power | c | c | c | +| len3 | three argument hypot | 2 | 2 | 2| +| len4 | four argument hypot | 2 | 2 | 2| +| lgamma | log Γ function | 6(>0) | 4(>0) | 3(>0) | +| lgamma_r | log Γ function with sign | 6(>0) | 4(>0) | 3(>0) | +| log10 | log base 10 | 3 | 3 | 2 | +| log1p | log base e accurate near 1 | 2 | 2 | 2 | +| log2 | log base 2 | 3 | 3 | 2 | +| log | log base e | 3 | 3 | 2 | +| logb | extract exponent | 0 | 0 | 0 | +| mad | multiply-add, implementation defined if fused | c | c | c | +| max | maximum without special NaN handling | 0 | 0 | 0 | +| maxmag | maximum magnitude | 0 | 0 | 0 | +| min | minimum without special NaN handling | 0 | 0 | 0 | +| minmag | minimum magnitude | 0 | 0 | 0 | +| modf | extract integer and fraction | 0 | 0 | 0 | +| mul_{rm} | multiply with specific rounding mode | c | c | c | +| nan | produce a NaN with a specific payload | 0 | 0 | 0 | +| ncdf | standard normal cumulative distribution function | 16 | 16 | 4 | +| ncdfinv | inverse standard normal cumulative distribution function | 16 | 16 | 4 | +| nearbyint | round to nearest integer (see also rint) | 0 | 0 | 0 | +| nextafter | next closest value above or below | 0 | 0 | 0 | +| pow | general power | 16 | 16 | 4 | +| pown | power with integral exponent | 16 | 16 | 4 | +| powr | power with positive floating point exponent | 16 | 16 | 4 | +| pred | predecessor | c | c | c | +| rcbrt | reciprocal cube root | 2 | 2 | 2 | +| remainder | floating point remainder | 0 | 0 | 0 | +| remquo | floating point remainder and lowest integral quotient bits | 0 | 0 | 0 | +| rhypot | reciprocal hypot | 2 | 2 | 2 | +| rint | round to nearest integer | c | c | c | +| rlen3 | reciprocal len3 | 2 | 2 | 2 | +| rlen4 | reciprocal len4 | 2 | 2 | 2 | +| rootn | nth root | 16 | 16 | 4 | +| round | round to integer, always away from 0 | c | c | c | +| rsqrt | reciprocal square root | 2 | 2 | 1 | +| scalb | multiply by 2 raised to a power | c | c | c | +| scalbn | multiply by 2 raised to an integral power (see also ldexp) | c | c | c | +| signbit | nonzero if argument has sign bit set | - | - | - | +| sin | sine function | 4 | 4 | 2 | +| sincos | simultaneous sine and cosine evaluation | 4 | 4 | 2 | +| sincospi | sincos function of argument times pi | 4 | 4 | 2 | +| sinh | hyperbolic sin | 4 | 4 | 2 | +| sinpi | sine of argument times pi | 4 | 4 | 2 | +| sqrt | square root | 3/c | 3/c | c | +| sub_{rm} | subtract with specific rounding mode | c | c | c | +| succ | successor | c | c | c | +| tan | tangent | 5 | 5 | 2 | +| tanh | hyperbolic tangent | 5 | 5 | 2 | +| tanpi | tangent of argument times pi | 6 | 6 | 2 | +| tgamma | true Γ function | 16 | 16 | 4 | +| trunc | round to integer, towards zero | c | c | c | +| y0 | Bessel function of the second kind, order 0, Y0 | 2 (<12) | 6 (<12) | 6 (<12) | +| y1 | Bessel function of the second kind, order 1, Y1 | 2 (<12) | 6 (<12) | 6 (<12) | + +For the functions supporting specific roundings, the rounding mode {rm} can be one of + * `rte` – round towards nearest even + * `rtp` – round towards positive infinity + * `rtn` – round towards negative infinity + * `rtz` – round towards zero + +Note that these functions are not currently available. + diff --git a/amd/device-libs/hip/CMakeLists.txt b/amd/device-libs/hip/CMakeLists.txt new file mode 100644 index 0000000000000..cba6179c0331f --- /dev/null +++ b/amd/device-libs/hip/CMakeLists.txt @@ -0,0 +1,21 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +file(GLOB cl_sources + ${CMAKE_CURRENT_SOURCE_DIR}/src/*.cl +) + +file(GLOB ll_sources + ${CMAKE_CURRENT_SOURCE_DIR}/src/*.ll +) + +file(GLOB sources ${cl_sources} ${ll_sources}) + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../ocml/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../ockl/inc) +opencl_bc_lib(NAME hip + SOURCES ${sources}) diff --git a/amd/device-libs/hip/src/empty.cl b/amd/device-libs/hip/src/empty.cl new file mode 100644 index 0000000000000..b01cb0359ecf3 --- /dev/null +++ b/amd/device-libs/hip/src/empty.cl @@ -0,0 +1 @@ +// Placeholder until clang stops trying to link hip.bc diff --git a/amd/device-libs/irif/inc/irif.h b/amd/device-libs/irif/inc/irif.h new file mode 100644 index 0000000000000..9297175ce8047 --- /dev/null +++ b/amd/device-libs/irif/inc/irif.h @@ -0,0 +1,24 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#ifndef IRIF_H +#define IRIF_H + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define BUILTIN_CLZ_U8(x) (uchar)(x == 0u ? 8 : __builtin_clz(x) - 24) +#define BUILTIN_CLZ_U16(x) (ushort)(x == 0u ? 16 : __builtin_clzs(x)) +#define BUILTIN_CLZ_U32(x) (uint)(x == 0u ? 32 : __builtin_clz(x)) +#define BUILTIN_CLZ_U64(x) (ulong)(x == 0u ? 64 : __builtin_clzl(x)) + +#define BUILTIN_CTZ_U8(x) (uchar)(x == 0u ? (uchar)8 : __builtin_ctz((uint)x)) +#define BUILTIN_CTZ_U16(x) (ushort)(x == 0u ? 16 : __builtin_ctzs(x)) +#define BUILTIN_CTZ_U32(x) (uint)(x == 0u ? 32 : __builtin_ctz(x)) +#define BUILTIN_CTZ_U64(x) (ulong)(x == 0u ? 64 : __builtin_ctzl(x)) + +#pragma OPENCL EXTENSION cl_khr_fp16 : disable +#endif // IRIF_H diff --git a/amd/device-libs/ockl/CMakeLists.txt b/amd/device-libs/ockl/CMakeLists.txt new file mode 100644 index 0000000000000..79846e3e8c049 --- /dev/null +++ b/amd/device-libs/ockl/CMakeLists.txt @@ -0,0 +1,21 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +file(GLOB sources + ${CMAKE_CURRENT_SOURCE_DIR}/src/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/*.ll +) + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../irif/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../oclc/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/inc) + +set_source_files_properties( + ${CMAKE_CURRENT_SOURCE_DIR}/src/gaaf.cl + PROPERTIES COMPILE_FLAGS "-munsafe-fp-atomics") + +opencl_bc_lib(NAME ockl SOURCES ${sources}) diff --git a/amd/device-libs/ockl/inc/amd_hsa_common.h b/amd/device-libs/ockl/inc/amd_hsa_common.h new file mode 100644 index 0000000000000..11efd6e02dedb --- /dev/null +++ b/amd/device-libs/ockl/inc/amd_hsa_common.h @@ -0,0 +1,93 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// The University of Illinois/NCSA +// Open Source License (NCSA) +// +// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved. +// +// Developed by: +// +// AMD Research and AMD HSA Software Development +// +// Advanced Micro Devices, Inc. +// +// www.amd.com +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to +// deal with the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimers. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimers in +// the documentation and/or other materials provided with the distribution. +// - Neither the names of Advanced Micro Devices, Inc, +// nor the names of its contributors may be used to endorse or promote +// products derived from this Software without specific prior written +// permission. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS WITH THE SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +// The following set of header files provides definitions for AMD GPU +// Architecture: +// - amd_hsa_common.h +// - amd_hsa_elf.h +// - amd_hsa_kernel_code.h +// - amd_hsa_queue.h +// - amd_hsa_signal.h +// +// Refer to "HSA Application Binary Interface: AMD GPU Architecture" for more +// information. + +#ifndef AMD_HSA_COMMON_H +#define AMD_HSA_COMMON_H + +#ifndef DEVICE_COMPILER +#include +#include +#endif + +// Descriptive version of the HSA Application Binary Interface. +#define AMD_HSA_ABI_VERSION "AMD GPU Architecture v0.35 (June 25, 2015)" + +// Alignment attribute that specifies a minimum alignment (in bytes) for +// variables of the specified type. +#if defined(__GNUC__) || defined(DEVICE_COMPILER) +# define __ALIGNED__(x) __attribute__((aligned(x))) +#elif defined(_MSC_VER) +# define __ALIGNED__(x) __declspec(align(x)) +#elif defined(RC_INVOKED) +# define __ALIGNED__(x) +#else +# error +#endif + +// Creates enumeration entries for packed types. Enumeration entries include +// bit shift amount, bit width, and bit mask. +#define AMD_HSA_BITS_CREATE_ENUM_ENTRIES(name, shift, width) \ + name ## _SHIFT = (shift), \ + name ## _WIDTH = (width), \ + name = (((1 << (width)) - 1) << (shift)) \ + +// Gets bits for specified mask from specified src packed instance. +#define AMD_HSA_BITS_GET(src, mask) \ + ((src & mask) >> mask ## _SHIFT) \ + +// Sets val bits for specified mask in specified dst packed instance. +#define AMD_HSA_BITS_SET(dst, mask, val) \ + dst &= (~(1 << mask ## _SHIFT) & ~mask); \ + dst |= (((val) << mask ## _SHIFT) & mask) \ + +#endif // AMD_HSA_COMMON_H diff --git a/amd/device-libs/ockl/inc/amd_hsa_elf.h b/amd/device-libs/ockl/inc/amd_hsa_elf.h new file mode 100644 index 0000000000000..95f89c63541af --- /dev/null +++ b/amd/device-libs/ockl/inc/amd_hsa_elf.h @@ -0,0 +1,295 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// The University of Illinois/NCSA +// Open Source License (NCSA) +// +// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved. +// +// Developed by: +// +// AMD Research and AMD HSA Software Development +// +// Advanced Micro Devices, Inc. +// +// www.amd.com +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to +// deal with the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimers. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimers in +// the documentation and/or other materials provided with the distribution. +// - Neither the names of Advanced Micro Devices, Inc, +// nor the names of its contributors may be used to endorse or promote +// products derived from this Software without specific prior written +// permission. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS WITH THE SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +#ifndef AMD_HSA_ELF_H +#define AMD_HSA_ELF_H + +#include "amd_hsa_common.h" + +// ELF Header Enumeration Values. +#define EM_AMDGPU 224 +#define ELFOSABI_AMDGPU_HSA 64 +#define ELFABIVERSION_AMDGPU_HSA 0 +#define EF_AMDGPU_XNACK 0x00000001 +#define EF_AMDGPU_TRAP_HANDLER 0x00000002 + +// ELF Section Header Flag Enumeration Values. +#define SHF_AMDGPU_HSA_GLOBAL (0x00100000 & SHF_MASKOS) +#define SHF_AMDGPU_HSA_READONLY (0x00200000 & SHF_MASKOS) +#define SHF_AMDGPU_HSA_CODE (0x00400000 & SHF_MASKOS) +#define SHF_AMDGPU_HSA_AGENT (0x00800000 & SHF_MASKOS) + +// +typedef enum { + AMDGPU_HSA_SEGMENT_GLOBAL_PROGRAM = 0, + AMDGPU_HSA_SEGMENT_GLOBAL_AGENT = 1, + AMDGPU_HSA_SEGMENT_READONLY_AGENT = 2, + AMDGPU_HSA_SEGMENT_CODE_AGENT = 3, + AMDGPU_HSA_SEGMENT_LAST, +} amdgpu_hsa_elf_segment_t; + +// ELF Program Header Type Enumeration Values. +#define PT_AMDGPU_HSA_LOAD_GLOBAL_PROGRAM (PT_LOOS + AMDGPU_HSA_SEGMENT_GLOBAL_PROGRAM) +#define PT_AMDGPU_HSA_LOAD_GLOBAL_AGENT (PT_LOOS + AMDGPU_HSA_SEGMENT_GLOBAL_AGENT) +#define PT_AMDGPU_HSA_LOAD_READONLY_AGENT (PT_LOOS + AMDGPU_HSA_SEGMENT_READONLY_AGENT) +#define PT_AMDGPU_HSA_LOAD_CODE_AGENT (PT_LOOS + AMDGPU_HSA_SEGMENT_CODE_AGENT) + +// ELF Symbol Type Enumeration Values. +#define STT_AMDGPU_HSA_KERNEL (STT_LOOS + 0) +#define STT_AMDGPU_HSA_INDIRECT_FUNCTION (STT_LOOS + 1) +#define STT_AMDGPU_HSA_METADATA (STT_LOOS + 2) + +// ELF Symbol Binding Enumeration Values. +#define STB_AMDGPU_HSA_EXTERNAL (STB_LOOS + 0) + +// ELF Symbol Other Information Creation/Retrieval. +#define ELF64_ST_AMDGPU_ALLOCATION(o) (((o) >> 2) & 0x3) +#define ELF64_ST_AMDGPU_FLAGS(o) ((o) >> 4) +#define ELF64_ST_AMDGPU_OTHER(f, a, v) (((f) << 4) + (((a) & 0x3) << 2) + ((v) & 0x3)) + +typedef enum { + AMDGPU_HSA_SYMBOL_ALLOCATION_DEFAULT = 0, + AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_PROGRAM = 1, + AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_AGENT = 2, + AMDGPU_HSA_SYMBOL_ALLOCATION_READONLY_AGENT = 3, + AMDGPU_HSA_SYMBOL_ALLOCATION_LAST, +} amdgpu_hsa_symbol_allocation_t; + +// ELF Symbol Allocation Enumeration Values. +#define STA_AMDGPU_HSA_DEFAULT AMDGPU_HSA_SYMBOL_ALLOCATION_DEFAULT +#define STA_AMDGPU_HSA_GLOBAL_PROGRAM AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_PROGRAM +#define STA_AMDGPU_HSA_GLOBAL_AGENT AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_AGENT +#define STA_AMDGPU_HSA_READONLY_AGENT AMDGPU_HSA_SYMBOL_ALLOCATION_READONLY_AGENT + +typedef enum { + AMDGPU_HSA_SYMBOL_FLAG_DEFAULT = 0, + AMDGPU_HSA_SYMBOL_FLAG_CONST = 1, + AMDGPU_HSA_SYMBOL_FLAG_LAST, +} amdgpu_hsa_symbol_flag_t; + +// ELF Symbol Flag Enumeration Values. +#define STF_AMDGPU_HSA_CONST AMDGPU_HSA_SYMBOL_FLAG_CONST + +// AMD GPU Relocation Type Enumeration Values. +#define R_AMDGPU_NONE 0 +#define R_AMDGPU_32_LOW 1 +#define R_AMDGPU_32_HIGH 2 +#define R_AMDGPU_64 3 +#define R_AMDGPU_INIT_SAMPLER 4 +#define R_AMDGPU_INIT_IMAGE 5 + +// AMD GPU Note Type Enumeration Values. +#define NT_AMDGPU_HSA_CODE_OBJECT_VERSION 1 +#define NT_AMDGPU_HSA_HSAIL 2 +#define NT_AMDGPU_HSA_ISA 3 +#define NT_AMDGPU_HSA_PRODUCER 4 +#define NT_AMDGPU_HSA_PRODUCER_OPTIONS 5 +#define NT_AMDGPU_HSA_EXTENSION 6 +#define NT_AMDGPU_HSA_HLDEBUG_DEBUG 101 +#define NT_AMDGPU_HSA_HLDEBUG_TARGET 102 + +// AMD GPU Metadata Kind Enumeration Values. +typedef uint16_t amdgpu_hsa_metadata_kind16_t; +typedef enum { + AMDGPU_HSA_METADATA_KIND_NONE = 0, + AMDGPU_HSA_METADATA_KIND_INIT_SAMP = 1, + AMDGPU_HSA_METADATA_KIND_INIT_ROIMG = 2, + AMDGPU_HSA_METADATA_KIND_INIT_WOIMG = 3, + AMDGPU_HSA_METADATA_KIND_INIT_RWIMG = 4 +} amdgpu_hsa_metadata_kind_t; + +// AMD GPU Sampler Coordinate Normalization Enumeration Values. +typedef uint8_t amdgpu_hsa_sampler_coord8_t; +typedef enum { + AMDGPU_HSA_SAMPLER_COORD_UNNORMALIZED = 0, + AMDGPU_HSA_SAMPLER_COORD_NORMALIZED = 1 +} amdgpu_hsa_sampler_coord_t; + +// AMD GPU Sampler Filter Enumeration Values. +typedef uint8_t amdgpu_hsa_sampler_filter8_t; +typedef enum { + AMDGPU_HSA_SAMPLER_FILTER_NEAREST = 0, + AMDGPU_HSA_SAMPLER_FILTER_LINEAR = 1 +} amdgpu_hsa_sampler_filter_t; + +// AMD GPU Sampler Addressing Enumeration Values. +typedef uint8_t amdgpu_hsa_sampler_addressing8_t; +typedef enum { + AMDGPU_HSA_SAMPLER_ADDRESSING_UNDEFINED = 0, + AMDGPU_HSA_SAMPLER_ADDRESSING_CLAMP_TO_EDGE = 1, + AMDGPU_HSA_SAMPLER_ADDRESSING_CLAMP_TO_BORDER = 2, + AMDGPU_HSA_SAMPLER_ADDRESSING_REPEAT = 3, + AMDGPU_HSA_SAMPLER_ADDRESSING_MIRRORED_REPEAT = 4 +} amdgpu_hsa_sampler_addressing_t; + +// AMD GPU Sampler Descriptor. +typedef struct amdgpu_hsa_sampler_descriptor_s { + uint16_t size; + amdgpu_hsa_metadata_kind16_t kind; + amdgpu_hsa_sampler_coord8_t coord; + amdgpu_hsa_sampler_filter8_t filter; + amdgpu_hsa_sampler_addressing8_t addressing; + uint8_t reserved1; +} amdgpu_hsa_sampler_descriptor_t; + +// AMD GPU Image Geometry Enumeration Values. +typedef uint8_t amdgpu_hsa_image_geometry8_t; +typedef enum { + AMDGPU_HSA_IMAGE_GEOMETRY_1D = 0, + AMDGPU_HSA_IMAGE_GEOMETRY_2D = 1, + AMDGPU_HSA_IMAGE_GEOMETRY_3D = 2, + AMDGPU_HSA_IMAGE_GEOMETRY_1DA = 3, + AMDGPU_HSA_IMAGE_GEOMETRY_2DA = 4, + AMDGPU_HSA_IMAGE_GEOMETRY_1DB = 5, + AMDGPU_HSA_IMAGE_GEOMETRY_2DDEPTH = 6, + AMDGPU_HSA_IMAGE_GEOMETRY_2DADEPTH = 7 +} amdgpu_hsa_image_geometry_t; + +// AMD GPU Image Channel Order Enumeration Values. +typedef uint8_t amdgpu_hsa_image_channel_order8_t; +typedef enum { + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_A = 0, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_R = 1, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RX = 2, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RG = 3, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGX = 4, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RA = 5, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGB = 6, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGBX = 7, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGBA = 8, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_BGRA = 9, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_ARGB = 10, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_ABGR = 11, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SRGB = 12, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SRGBX = 13, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SRGBA = 14, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SBGRA = 15, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_INTENSITY = 16, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_LUMINANCE = 17, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_DEPTH = 18, + AMDGPU_HSA_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL = 19 +} amdgpu_hsa_image_channel_order_t; + +// AMD GPU Image Channel Type Enumeration Values. +typedef uint8_t amdgpu_hsa_image_channel_type8_t; +typedef enum { + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SNORM_INT8 = 0, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SNORM_INT16 = 1, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNORM_INT8 = 2, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNORM_INT16 = 3, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNORM_INT24 = 4, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SHORT_555 = 5, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SHORT_565 = 6, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_INT_101010 = 7, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SIGNED_INT8 = 8, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SIGNED_INT16 = 9, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SIGNED_INT32 = 10, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8 = 11, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16 = 12, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32 = 13, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_HALF_FLOAT = 14, + AMDGPU_HSA_IMAGE_CHANNEL_TYPE_FLOAT = 15 +} amdgpu_hsa_image_channel_type_t; + +// AMD GPU Image Descriptor. +typedef struct amdgpu_hsa_image_descriptor_s { + uint16_t size; + amdgpu_hsa_metadata_kind16_t kind; + amdgpu_hsa_image_geometry8_t geometry; + amdgpu_hsa_image_channel_order8_t channel_order; + amdgpu_hsa_image_channel_type8_t channel_type; + uint8_t reserved1; + uint64_t width; + uint64_t height; + uint64_t depth; + uint64_t array; +} amdgpu_hsa_image_descriptor_t; + +typedef struct amdgpu_hsa_note_code_object_version_s { + uint32_t major_version; + uint32_t minor_version; +} amdgpu_hsa_note_code_object_version_t; + +typedef struct amdgpu_hsa_note_hsail_s { + uint32_t hsail_major_version; + uint32_t hsail_minor_version; + uint8_t profile; + uint8_t machine_model; + uint8_t default_float_round; +} amdgpu_hsa_note_hsail_t; + +typedef struct amdgpu_hsa_note_isa_s { + uint16_t vendor_name_size; + uint16_t architecture_name_size; + uint32_t major; + uint32_t minor; + uint32_t stepping; + char vendor_and_architecture_name[1]; +} amdgpu_hsa_note_isa_t; + +typedef struct amdgpu_hsa_note_producer_s { + uint16_t producer_name_size; + uint16_t reserved; + uint32_t producer_major_version; + uint32_t producer_minor_version; + char producer_name[1]; +} amdgpu_hsa_note_producer_t; + +typedef struct amdgpu_hsa_note_producer_options_s { + uint16_t producer_options_size; + char producer_options[1]; +} amdgpu_hsa_note_producer_options_t; + +typedef enum { + AMDGPU_HSA_RODATA_GLOBAL_PROGRAM = 0, + AMDGPU_HSA_RODATA_GLOBAL_AGENT, + AMDGPU_HSA_RODATA_READONLY_AGENT, + AMDGPU_HSA_DATA_GLOBAL_PROGRAM, + AMDGPU_HSA_DATA_GLOBAL_AGENT, + AMDGPU_HSA_DATA_READONLY_AGENT, + AMDGPU_HSA_BSS_GLOBAL_PROGRAM, + AMDGPU_HSA_BSS_GLOBAL_AGENT, + AMDGPU_HSA_BSS_READONLY_AGENT, + AMDGPU_HSA_SECTION_LAST, +} amdgpu_hsa_elf_section_t; + +#endif // AMD_HSA_ELF_H diff --git a/amd/device-libs/ockl/inc/amd_hsa_kernel_code.h b/amd/device-libs/ockl/inc/amd_hsa_kernel_code.h new file mode 100644 index 0000000000000..6c2742a68a3d4 --- /dev/null +++ b/amd/device-libs/ockl/inc/amd_hsa_kernel_code.h @@ -0,0 +1,269 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// The University of Illinois/NCSA +// Open Source License (NCSA) +// +// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved. +// +// Developed by: +// +// AMD Research and AMD HSA Software Development +// +// Advanced Micro Devices, Inc. +// +// www.amd.com +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to +// deal with the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimers. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimers in +// the documentation and/or other materials provided with the distribution. +// - Neither the names of Advanced Micro Devices, Inc, +// nor the names of its contributors may be used to endorse or promote +// products derived from this Software without specific prior written +// permission. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS WITH THE SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +#ifndef AMD_HSA_KERNEL_CODE_H +#define AMD_HSA_KERNEL_CODE_H + +#include "amd_hsa_common.h" +#include "hsa.h" + +// AMD Kernel Code Version Enumeration Values. +typedef uint32_t amd_kernel_code_version32_t; +enum amd_kernel_code_version_t { + AMD_KERNEL_CODE_VERSION_MAJOR = 1, + AMD_KERNEL_CODE_VERSION_MINOR = 1 +}; + +// AMD Machine Kind Enumeration Values. +typedef uint16_t amd_machine_kind16_t; +enum amd_machine_kind_t { + AMD_MACHINE_KIND_UNDEFINED = 0, + AMD_MACHINE_KIND_AMDGPU = 1 +}; + +// AMD Machine Version. +typedef uint16_t amd_machine_version16_t; + +// AMD Float Round Mode Enumeration Values. +enum amd_float_round_mode_t { + AMD_FLOAT_ROUND_MODE_NEAREST_EVEN = 0, + AMD_FLOAT_ROUND_MODE_PLUS_INFINITY = 1, + AMD_FLOAT_ROUND_MODE_MINUS_INFINITY = 2, + AMD_FLOAT_ROUND_MODE_ZERO = 3 +}; + +// AMD Float Denorm Mode Enumeration Values. +enum amd_float_denorm_mode_t { + AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE_OUTPUT = 0, + AMD_FLOAT_DENORM_MODE_FLUSH_OUTPUT = 1, + AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE = 2, + AMD_FLOAT_DENORM_MODE_NO_FLUSH = 3 +}; + +// AMD Compute Program Resource Register One. +typedef uint32_t amd_compute_pgm_rsrc_one32_t; +enum amd_compute_pgm_rsrc_one_t { + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT, 6, 4), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY, 10, 2), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32, 12, 2), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64, 14, 2), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32, 16, 2), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64, 18, 2), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_PRIV, 20, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP, 21, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE, 22, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE, 23, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_BULKY, 24, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER, 25, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1, 26, 6) +}; + +// AMD System VGPR Workitem ID Enumeration Values. +enum amd_system_vgpr_workitem_id_t { + AMD_SYSTEM_VGPR_WORKITEM_ID_X = 0, + AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y = 1, + AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2, + AMD_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3 +}; + +// AMD Compute Program Resource Register Two. +typedef uint32_t amd_compute_pgm_rsrc_two32_t; +enum amd_compute_pgm_rsrc_two_t { + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET, 0, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT, 1, 5), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER, 6, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X, 7, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y, 8, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z, 9, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO, 10, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID, 11, 2), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH, 13, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION, 14, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE, 15, 9), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, 24, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE, 25, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, 26, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW, 27, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW, 28, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT, 29, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO, 30, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1, 31, 1) +}; + +// AMD Element Byte Size Enumeration Values. +enum amd_element_byte_size_t { + AMD_ELEMENT_BYTE_SIZE_2 = 0, + AMD_ELEMENT_BYTE_SIZE_4 = 1, + AMD_ELEMENT_BYTE_SIZE_8 = 2, + AMD_ELEMENT_BYTE_SIZE_16 = 3 +}; + +// AMD Kernel Code Properties. +typedef uint32_t amd_kernel_code_properties32_t; +enum amd_kernel_code_properties_t { + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR, 1, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR, 2, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR, 3, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID, 4, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT, 5, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE, 6, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X, 7, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y, 8, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z, 9, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_RESERVED1, 10, 6), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS, 16, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE, 17, 2), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_IS_PTR64, 19, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK, 20, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED, 21, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED, 22, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_RESERVED2, 23, 9) +}; + +// AMD Power Of Two Enumeration Values. +typedef uint8_t amd_powertwo8_t; +enum amd_powertwo_t { + AMD_POWERTWO_1 = 0, + AMD_POWERTWO_2 = 1, + AMD_POWERTWO_4 = 2, + AMD_POWERTWO_8 = 3, + AMD_POWERTWO_16 = 4, + AMD_POWERTWO_32 = 5, + AMD_POWERTWO_64 = 6, + AMD_POWERTWO_128 = 7, + AMD_POWERTWO_256 = 8 +}; + +// AMD Enabled Control Directive Enumeration Values. +typedef uint64_t amd_enabled_control_directive64_t; +enum amd_enabled_control_directive_t { + AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_BREAK_EXCEPTIONS = 1, + AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_DETECT_EXCEPTIONS = 2, + AMD_ENABLED_CONTROL_DIRECTIVE_MAX_DYNAMIC_GROUP_SIZE = 4, + AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_GRID_SIZE = 8, + AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_WORKGROUP_SIZE = 16, + AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_DIM = 32, + AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_GRID_SIZE = 64, + AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_WORKGROUP_SIZE = 128, + AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRE_NO_PARTIAL_WORKGROUPS = 256 +}; + +// AMD Exception Kind Enumeration Values. +typedef uint16_t amd_exception_kind16_t; +enum amd_exception_kind_t { + AMD_EXCEPTION_KIND_INVALID_OPERATION = 1, + AMD_EXCEPTION_KIND_DIVISION_BY_ZERO = 2, + AMD_EXCEPTION_KIND_OVERFLOW = 4, + AMD_EXCEPTION_KIND_UNDERFLOW = 8, + AMD_EXCEPTION_KIND_INEXACT = 16 +}; + +// AMD Control Directives. +#define AMD_CONTROL_DIRECTIVES_ALIGN_BYTES 64 +#define AMD_CONTROL_DIRECTIVES_ALIGN __ALIGNED__(AMD_CONTROL_DIRECTIVES_ALIGN_BYTES) +typedef AMD_CONTROL_DIRECTIVES_ALIGN struct amd_control_directives_s { + amd_enabled_control_directive64_t enabled_control_directives; + uint16_t enable_break_exceptions; + uint16_t enable_detect_exceptions; + uint32_t max_dynamic_group_size; + uint64_t max_flat_grid_size; + uint32_t max_flat_workgroup_size; + uint8_t required_dim; + uint8_t reserved1[3]; + uint64_t required_grid_size[3]; + uint32_t required_workgroup_size[3]; + uint8_t reserved2[60]; +} amd_control_directives_t; + +// AMD Kernel Code. +#define AMD_ISA_ALIGN_BYTES 256 +#define AMD_KERNEL_CODE_ALIGN_BYTES 64 +#define AMD_KERNEL_CODE_ALIGN __ALIGNED__(AMD_KERNEL_CODE_ALIGN_BYTES) +typedef AMD_KERNEL_CODE_ALIGN struct amd_kernel_code_s { + amd_kernel_code_version32_t amd_kernel_code_version_major; + amd_kernel_code_version32_t amd_kernel_code_version_minor; + amd_machine_kind16_t amd_machine_kind; + amd_machine_version16_t amd_machine_version_major; + amd_machine_version16_t amd_machine_version_minor; + amd_machine_version16_t amd_machine_version_stepping; + int64_t kernel_code_entry_byte_offset; + int64_t kernel_code_prefetch_byte_offset; + uint64_t kernel_code_prefetch_byte_size; + uint64_t max_scratch_backing_memory_byte_size; + amd_compute_pgm_rsrc_one32_t compute_pgm_rsrc1; + amd_compute_pgm_rsrc_two32_t compute_pgm_rsrc2; + amd_kernel_code_properties32_t kernel_code_properties; + uint32_t workitem_private_segment_byte_size; + uint32_t workgroup_group_segment_byte_size; + uint32_t gds_segment_byte_size; + uint64_t kernarg_segment_byte_size; + uint32_t workgroup_fbarrier_count; + uint16_t wavefront_sgpr_count; + uint16_t workitem_vgpr_count; + uint16_t reserved_vgpr_first; + uint16_t reserved_vgpr_count; + uint16_t reserved_sgpr_first; + uint16_t reserved_sgpr_count; + uint16_t debug_wavefront_private_segment_offset_sgpr; + uint16_t debug_private_segment_buffer_sgpr; + amd_powertwo8_t kernarg_segment_alignment; + amd_powertwo8_t group_segment_alignment; + amd_powertwo8_t private_segment_alignment; + amd_powertwo8_t wavefront_size; + int32_t call_convention; + uint8_t reserved1[12]; + uint64_t runtime_loader_kernel_symbol; + amd_control_directives_t control_directives; +} amd_kernel_code_t; + +// TODO: this struct should be completely gone once debugger designs/implements +// Debugger APIs. +typedef struct amd_runtime_loader_debug_info_s { + const void* elf_raw; + size_t elf_size; + const char *kernel_name; + const void *owning_segment; +} amd_runtime_loader_debug_info_t; + +#endif // AMD_HSA_KERNEL_CODE_H diff --git a/amd/device-libs/ockl/inc/amd_hsa_queue.h b/amd/device-libs/ockl/inc/amd_hsa_queue.h new file mode 100644 index 0000000000000..60e4c079ccd27 --- /dev/null +++ b/amd/device-libs/ockl/inc/amd_hsa_queue.h @@ -0,0 +1,86 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// The University of Illinois/NCSA +// Open Source License (NCSA) +// +// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved. +// +// Developed by: +// +// AMD Research and AMD HSA Software Development +// +// Advanced Micro Devices, Inc. +// +// www.amd.com +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to +// deal with the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimers. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimers in +// the documentation and/or other materials provided with the distribution. +// - Neither the names of Advanced Micro Devices, Inc, +// nor the names of its contributors may be used to endorse or promote +// products derived from this Software without specific prior written +// permission. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS WITH THE SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +#ifndef AMD_HSA_QUEUE_H +#define AMD_HSA_QUEUE_H + +#include "amd_hsa_common.h" +#include "hsa.h" + +// AMD Queue Properties. +typedef uint32_t amd_queue_properties32_t; +enum amd_queue_properties_t { + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER, 0, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_IS_PTR64, 1, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS, 2, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_ENABLE_PROFILING, 3, 1), + AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_PROPERTIES_RESERVED1, 4, 28) +}; + +// AMD Queue. +#define AMD_QUEUE_ALIGN_BYTES 64 +#define AMD_QUEUE_ALIGN __ALIGNED__(AMD_QUEUE_ALIGN_BYTES) +typedef struct AMD_QUEUE_ALIGN amd_queue_s { + hsa_queue_t hsa_queue; + uint32_t reserved1[4]; + volatile uint64_t write_dispatch_id; + uint32_t group_segment_aperture_base_hi; + uint32_t private_segment_aperture_base_hi; + uint32_t max_cu_id; + uint32_t max_wave_id; + volatile uint64_t max_legacy_doorbell_dispatch_id_plus_1; + volatile uint32_t legacy_doorbell_lock; + uint32_t reserved2[9]; + volatile uint64_t read_dispatch_id; + uint32_t read_dispatch_id_field_base_byte_offset; + uint32_t compute_tmpring_size; + uint32_t scratch_resource_descriptor[4]; + uint64_t scratch_backing_memory_location; + uint64_t scratch_backing_memory_byte_size; + uint32_t scratch_workitem_byte_size; + amd_queue_properties32_t queue_properties; + uint32_t reserved3[2]; + hsa_signal_t queue_inactive_signal; + uint32_t reserved4[14]; +} amd_queue_t; + +#endif // AMD_HSA_QUEUE_H diff --git a/amd/device-libs/ockl/inc/amd_hsa_signal.h b/amd/device-libs/ockl/inc/amd_hsa_signal.h new file mode 100644 index 0000000000000..ea6f3da4542a2 --- /dev/null +++ b/amd/device-libs/ockl/inc/amd_hsa_signal.h @@ -0,0 +1,89 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// The University of Illinois/NCSA +// Open Source License (NCSA) +// +// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved. +// +// Developed by: +// +// AMD Research and AMD HSA Software Development +// +// Advanced Micro Devices, Inc. +// +// www.amd.com +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to +// deal with the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimers. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimers in +// the documentation and/or other materials provided with the distribution. +// - Neither the names of Advanced Micro Devices, Inc, +// nor the names of its contributors may be used to endorse or promote +// products derived from this Software without specific prior written +// permission. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS WITH THE SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +#ifndef AMD_HSA_SIGNAL_H +#define AMD_HSA_SIGNAL_H + +#include "amd_hsa_common.h" +#include "amd_hsa_queue.h" + +// AMD Signal Kind Enumeration Values. +typedef int64_t amd_signal_kind64_t; +enum amd_signal_kind_t { + AMD_SIGNAL_KIND_INVALID = 0, + AMD_SIGNAL_KIND_USER = 1, + AMD_SIGNAL_KIND_DOORBELL = -1, + AMD_SIGNAL_KIND_LEGACY_DOORBELL = -2 +}; + +// AMD Signal. +#define AMD_SIGNAL_ALIGN_BYTES 64 +#define AMD_SIGNAL_ALIGN __ALIGNED__(AMD_SIGNAL_ALIGN_BYTES) +typedef struct AMD_SIGNAL_ALIGN amd_signal_s { + amd_signal_kind64_t kind; + union { + volatile int64_t value; +#ifdef DEVICE_COMPILER + __global +#endif + volatile uint32_t* legacy_hardware_doorbell_ptr; +#ifdef DEVICE_COMPILER + __global +#endif + volatile uint64_t* hardware_doorbell_ptr; + }; + uint64_t event_mailbox_ptr; + uint32_t event_id; + uint32_t reserved1; + uint64_t start_ts; + uint64_t end_ts; + union { +#ifdef DEVICE_COMPILER + __global +#endif + amd_queue_t* queue_ptr; + uint64_t reserved2; + }; + uint32_t reserved3[2]; +} amd_signal_t; + +#endif // AMD_HSA_SIGNAL_H diff --git a/amd/device-libs/ockl/inc/device_amd_hsa.h b/amd/device-libs/ockl/inc/device_amd_hsa.h new file mode 100644 index 0000000000000..3fb3b296d2950 --- /dev/null +++ b/amd/device-libs/ockl/inc/device_amd_hsa.h @@ -0,0 +1,30 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#ifndef DEVICE_AMD_HSA_H +#define DEVICE_AMD_HSA_H + +typedef char int8_t; +typedef unsigned char uint8_t; +typedef short int16_t; +typedef unsigned short uint16_t; +typedef int int32_t; +typedef unsigned int uint32_t; +typedef long int64_t; +typedef unsigned long uint64_t; + +#define DEVICE_COMPILER +#define LITTLEENDIAN_CPU +#include "hsa.h" +#include "amd_hsa_common.h" +#include "amd_hsa_elf.h" +#include "amd_hsa_kernel_code.h" +#include "amd_hsa_queue.h" +#include "amd_hsa_signal.h" +#undef DEVICE_COMPILER + +#endif // DEVICE_AMD_HSA_H diff --git a/amd/device-libs/ockl/inc/hsa.h b/amd/device-libs/ockl/inc/hsa.h new file mode 100644 index 0000000000000..fe3b021a589e9 --- /dev/null +++ b/amd/device-libs/ockl/inc/hsa.h @@ -0,0 +1,3967 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// The University of Illinois/NCSA +// Open Source License (NCSA) +// +// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved. +// +// Developed by: +// +// AMD Research and AMD HSA Software Development +// +// Advanced Micro Devices, Inc. +// +// www.amd.com +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to +// deal with the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimers. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimers in +// the documentation and/or other materials provided with the distribution. +// - Neither the names of Advanced Micro Devices, Inc, +// nor the names of its contributors may be used to endorse or promote +// products derived from this Software without specific prior written +// permission. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS WITH THE SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +#ifndef HSA_RUNTIME_INC_HSA_H_ +#define HSA_RUNTIME_INC_HSA_H_ + +#ifndef DEVICE_COMPILER +#include /* size_t */ +#include /* uintXX_t */ +#ifndef __cplusplus +#include +#endif /* __cplusplus */ +#endif + +// Placeholder for calling convention and import/export macros +#ifndef HSA_CALL +#define HSA_CALL +#endif + +#ifndef HSA_EXPORT_DECORATOR +#ifdef __GNUC__ +#define HSA_EXPORT_DECORATOR __attribute__ ((visibility ("default"))) +#else +#define HSA_EXPORT_DECORATOR +#endif +#endif + +#define HSA_API_EXPORT HSA_EXPORT_DECORATOR HSA_CALL +#define HSA_API_IMPORT HSA_CALL + +#if !defined(HSA_API) && defined(HSA_EXPORT) +#define HSA_API HSA_API_EXPORT +#else +#define HSA_API HSA_API_IMPORT +#endif + +// Detect and set large model builds. +#undef HSA_LARGE_MODEL +#if defined(__LP64__) || defined(_M_X64) +#define HSA_LARGE_MODEL +#endif + +// Try to detect CPU endianness +#if !defined(LITTLEENDIAN_CPU) && !defined(BIGENDIAN_CPU) +#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || \ + defined(_M_X64) +#define LITTLEENDIAN_CPU +#endif +#endif + +#undef HSA_LITTLE_ENDIAN +#if defined(LITTLEENDIAN_CPU) +#define HSA_LITTLE_ENDIAN +#elif defined(BIGENDIAN_CPU) +#else +#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" +#endif + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** \defgroup status Runtime Notifications + * @{ + */ + +/** + * @brief Status codes. + */ +typedef enum { + /** + * The function has been executed successfully. + */ + HSA_STATUS_SUCCESS = 0x0, + /** + * A traversal over a list of elements has been interrupted by the + * application before completing. + */ + HSA_STATUS_INFO_BREAK = 0x1, + /** + * A generic error has occurred. + */ + HSA_STATUS_ERROR = 0x1000, + /** + * One of the actual arguments does not meet a precondition stated in the + * documentation of the corresponding formal argument. + */ + HSA_STATUS_ERROR_INVALID_ARGUMENT = 0x1001, + /** + * The requested queue creation is not valid. + */ + HSA_STATUS_ERROR_INVALID_QUEUE_CREATION = 0x1002, + /** + * The requested allocation is not valid. + */ + HSA_STATUS_ERROR_INVALID_ALLOCATION = 0x1003, + /** + * The agent is invalid. + */ + HSA_STATUS_ERROR_INVALID_AGENT = 0x1004, + /** + * The memory region is invalid. + */ + HSA_STATUS_ERROR_INVALID_REGION = 0x1005, + /** + * The signal is invalid. + */ + HSA_STATUS_ERROR_INVALID_SIGNAL = 0x1006, + /** + * The queue is invalid. + */ + HSA_STATUS_ERROR_INVALID_QUEUE = 0x1007, + /** + * The HSA runtime failed to allocate the necessary resources. This error + * may also occur when the HSA runtime needs to spawn threads or create + * internal OS-specific events. + */ + HSA_STATUS_ERROR_OUT_OF_RESOURCES = 0x1008, + /** + * The AQL packet is malformed. + */ + HSA_STATUS_ERROR_INVALID_PACKET_FORMAT = 0x1009, + /** + * An error has been detected while releasing a resource. + */ + HSA_STATUS_ERROR_RESOURCE_FREE = 0x100A, + /** + * An API other than ::hsa_init has been invoked while the reference count + * of the HSA runtime is 0. + */ + HSA_STATUS_ERROR_NOT_INITIALIZED = 0x100B, + /** + * The maximum reference count for the object has been reached. + */ + HSA_STATUS_ERROR_REFCOUNT_OVERFLOW = 0x100C, + /** + * The arguments passed to a functions are not compatible. + */ + HSA_STATUS_ERROR_INCOMPATIBLE_ARGUMENTS = 0x100D, + /** + * The index is invalid. + */ + HSA_STATUS_ERROR_INVALID_INDEX = 0x100E, + /** + * The instruction set architecture is invalid. + */ + HSA_STATUS_ERROR_INVALID_ISA = 0x100F, + /** + * The instruction set architecture name is invalid. + */ + HSA_STATUS_ERROR_INVALID_ISA_NAME = 0x1017, + /** + * The code object is invalid. + */ + HSA_STATUS_ERROR_INVALID_CODE_OBJECT = 0x1010, + /** + * The executable is invalid. + */ + HSA_STATUS_ERROR_INVALID_EXECUTABLE = 0x1011, + /** + * The executable is frozen. + */ + HSA_STATUS_ERROR_FROZEN_EXECUTABLE = 0x1012, + /** + * There is no symbol with the given name. + */ + HSA_STATUS_ERROR_INVALID_SYMBOL_NAME = 0x1013, + /** + * The variable is already defined. + */ + HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED = 0x1014, + /** + * The variable is undefined. + */ + HSA_STATUS_ERROR_VARIABLE_UNDEFINED = 0x1015, + /** + * An HSAIL operation resulted on a hardware exception. + */ + HSA_STATUS_ERROR_EXCEPTION = 0x1016 +} hsa_status_t; + +/** + * @brief Query additional information about a status code. + * + * @param[in] status Status code. + * + * @param[out] status_string A NUL-terminated string that describes the error + * status. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p status is an invalid + * status code, or @p status_string is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API + hsa_status_string(hsa_status_t status, const char **status_string); +#endif + +/** @} */ + +/** \defgroup common Common Definitions + * @{ + */ + +/** + * @brief Three-dimensional coordinate. + */ +typedef struct hsa_dim3_s { + /** + * X dimension. + */ + uint32_t x; + + /** + * Y dimension. + */ + uint32_t y; + + /** + * Z dimension. + */ + uint32_t z; +} hsa_dim3_t; + +/** + * @brief Access permissions. + */ +typedef enum { + /** + * Read-only access. + */ + HSA_ACCESS_PERMISSION_RO = 1, + /** + * Write-only access. + */ + HSA_ACCESS_PERMISSION_WO = 2, + /** + * Read and write access. + */ + HSA_ACCESS_PERMISSION_RW = 3 +} hsa_access_permission_t; + +/** @} **/ + +/** \defgroup initshutdown Initialization and Shut Down + * @{ + */ + +/** + * @brief Initialize the HSA runtime. + * + * @details Initializes the HSA runtime if it is not already initialized, and + * increases the reference counter associated with the HSA runtime for the + * current process. Invocation of any HSA function other than ::hsa_init results + * in undefined behavior if the current HSA runtime reference counter is less + * than one. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is failure to allocate + * the resources required by the implementation. + * + * @retval ::HSA_STATUS_ERROR_REFCOUNT_OVERFLOW The HSA runtime reference + * count reaches INT32_MAX. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_init(); +#endif + +/** + * @brief Shut down the HSA runtime. + * + * @details Decreases the reference count of the HSA runtime instance. When the + * reference count reaches 0, the HSA runtime is no longer considered valid + * but the application might call ::hsa_init to initialize the HSA runtime + * again. + * + * Once the reference count of the HSA runtime reaches 0, all the resources + * associated with it (queues, signals, agent information, etc.) are + * considered invalid and any attempt to reference them in subsequent API calls + * results in undefined behavior. When the reference count reaches 0, the HSA + * runtime may release resources associated with it. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_shut_down(); +#endif + +/** @} **/ + +/** \defgroup agentinfo System and Agent Information + * @{ + */ + +/** + * @brief Endianness. A convention used to interpret the bytes making up a data + * word. + */ +typedef enum { + /** + * The least significant byte is stored in the smallest address. + */ + HSA_ENDIANNESS_LITTLE = 0, + /** + * The most significant byte is stored in the smallest address. + */ + HSA_ENDIANNESS_BIG = 1 +} hsa_endianness_t; + +/** + * @brief Machine model. A machine model determines the size of certain data + * types in HSA runtime and an agent. + */ +typedef enum { + /** + * Small machine model. Addresses use 32 bits. + */ + HSA_MACHINE_MODEL_SMALL = 0, + /** + * Large machine model. Addresses use 64 bits. + */ + HSA_MACHINE_MODEL_LARGE = 1 +} hsa_machine_model_t; + +/** + * @brief Profile. A profile indicates a particular level of feature + * support. For example, in the base profile the application must use the HSA + * runtime allocator to reserve Shared Virtual Memory, while in the full profile + * any host pointer can be shared across all the agents. + */ +typedef enum { + /** + * Base profile. + */ + HSA_PROFILE_BASE = 0, + /** + * Full profile. + */ + HSA_PROFILE_FULL = 1 +} hsa_profile_t; + +/** + * @brief System attributes. + */ +typedef enum { + /** + * Major version of the HSA runtime specification supported by the + * implementation. The type of this attribute is uint16_t. + */ + HSA_SYSTEM_INFO_VERSION_MAJOR = 0, + /** + * Minor version of the HSA runtime specification supported by the + * implementation. The type of this attribute is uint16_t. + */ + HSA_SYSTEM_INFO_VERSION_MINOR = 1, + /** + * Current timestamp. The value of this attribute monotonically increases at a + * constant rate. The type of this attribute is uint64_t. + */ + HSA_SYSTEM_INFO_TIMESTAMP = 2, + /** + * Timestamp value increase rate, in Hz. The timestamp (clock) frequency is + * in the range 1-400MHz. The type of this attribute is uint64_t. + */ + HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY = 3, + /** + * Maximum duration of a signal wait operation. Expressed as a count based on + * the timestamp frequency. The type of this attribute is uint64_t. + */ + HSA_SYSTEM_INFO_SIGNAL_MAX_WAIT = 4, + /** + * Endianness of the system. The type of this attribute us ::hsa_endianness_t. + */ + HSA_SYSTEM_INFO_ENDIANNESS = 5, + /** + * Machine model supported by the HSA runtime. The type of this attribute is + * ::hsa_machine_model_t. + */ + HSA_SYSTEM_INFO_MACHINE_MODEL = 6, + /** + * Bit-mask indicating which extensions are supported by the + * implementation. An extension with an ID of @p i is supported if the bit at + * position @p i is set. The type of this attribute is uint8_t[128]. + */ + HSA_SYSTEM_INFO_EXTENSIONS = 7, + /** + * Returns true if XNACK is enabled on this system. The type of + * this attribute is bool. + */ + HSA_AMD_SYSTEM_INFO_XNACK_ENABLED = 0x206 +} hsa_system_info_t; + +/** + * @brief Get the current value of a system attribute. + * + * @param[in] attribute Attribute to query. + * + * @param[out] value Pointer to an application-allocated buffer where to store + * the value of the attribute. If the buffer passed by the application is not + * large enough to hold the value of @p attribute, the behavior is undefined. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p attribute is an invalid + * system attribute, or @p value is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API + hsa_system_get_info(hsa_system_info_t attribute, void *value); +#endif + +/** + * @brief HSA extensions. + */ +typedef enum { + /** + * Finalizer extension. + */ + HSA_EXTENSION_FINALIZER = 0, + /** + * Images extension. + */ + HSA_EXTENSION_IMAGES = 1, + /** + * Profiler extension. + */ + HSA_EXTENSION_AMD_PROFILER = 2, + /** + * Loaded code object extension. + */ + HSA_EXTENSION_AMD_LOADED_CODE_OBJECT = 3 +} hsa_extension_t; + +/** + * @brief Query if a given version of an extension is supported by the HSA + * implementation. + * + * @param[in] extension Extension identifier. + * + * @param[in] version_major Major version number. + * + * @param[in] version_minor Minor version number. + * + * @param[out] result Pointer to a memory location where the HSA runtime stores + * the result of the check. The result is true if the specified version of the + * extension is supported, and false otherwise. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p extension is not a valid + * extension, or @p result is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API + hsa_system_extension_supported(uint16_t extension, uint16_t version_major, + uint16_t version_minor, bool *result); +#endif + +/** + * @brief Retrieve the function pointers corresponding to a given version of an + * extension. Portable applications are expected to invoke the extension API + * using the returned function pointers + * + * @details The application is responsible for verifying that the given version + * of the extension is supported by the HSA implementation (see + * ::hsa_system_extension_supported). If the given combination of extension, + * major version, and minor version is not supported by the implementation, the + * behavior is undefined. + * + * @param[in] extension Extension identifier. + * + * @param[in] version_major Major version number for which to retrieve the + * function pointer table. + * + * @param[in] version_minor Minor version number for which to retrieve the + * function pointer table. + * + * @param[out] table Pointer to an application-allocated function pointer table + * that is populated by the HSA runtime. Must not be NULL. The memory associated + * with table can be reused or freed after the function returns. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p extension is not a valid + * extension, or @p table is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API + hsa_system_get_extension_table(uint16_t extension, uint16_t version_major, + uint16_t version_minor, void *table); +#endif + +/** + * @brief Opaque handle representing an agent, a device that participates in + * the HSA memory model. An agent can submit AQL packets for execution, and + * may also accept AQL packets for execution (agent dispatch packets or kernel + * dispatch packets launching HSAIL-derived binaries). + */ +typedef struct hsa_agent_s { + /** + * Opaque handle. + */ + uint64_t handle; +} hsa_agent_t; + +/** + * @brief Agent features. + */ +typedef enum { + /** + * The agent supports AQL packets of kernel dispatch type. If this + * feature is enabled, the agent is also a kernel agent. + */ + HSA_AGENT_FEATURE_KERNEL_DISPATCH = 1, + /** + * The agent supports AQL packets of agent dispatch type. + */ + HSA_AGENT_FEATURE_AGENT_DISPATCH = 2 +} hsa_agent_feature_t; + +/** + * @brief Hardware device type. + */ +typedef enum { + /** + * CPU device. + */ + HSA_DEVICE_TYPE_CPU = 0, + /** + * GPU device. + */ + HSA_DEVICE_TYPE_GPU = 1, + /** + * DSP device. + */ + HSA_DEVICE_TYPE_DSP = 2 +} hsa_device_type_t; + +/** + * @brief Default floating-point rounding mode. + */ +typedef enum { + /** + * Use a default floating-point rounding mode specified elsewhere. + */ + HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT = 0, + /** + * Operations that specify the default floating-point mode are rounded to zero + * by default. + */ + HSA_DEFAULT_FLOAT_ROUNDING_MODE_ZERO = 1, + /** + * Operations that specify the default floating-point mode are rounded to the + * nearest representable number and that ties should be broken by selecting + * the value with an even least significant bit. + */ + HSA_DEFAULT_FLOAT_ROUNDING_MODE_NEAR = 2 +} hsa_default_float_rounding_mode_t; + +/** + * @brief Agent attributes. + */ +typedef enum { + /** + * Agent name. The type of this attribute is a NUL-terminated char[64]. If + * the name of the agent uses less than 63 characters, the rest of the + * array must be filled with NULs. + */ + HSA_AGENT_INFO_NAME = 0, + /** + * Name of vendor. The type of this attribute is a NUL-terminated char[64]. If + * the name of the vendor uses less than 63 characters, the rest of the array + * must be filled with NULs. + */ + HSA_AGENT_INFO_VENDOR_NAME = 1, + /** + * Agent capability. The type of this attribute is ::hsa_agent_feature_t. + */ + HSA_AGENT_INFO_FEATURE = 2, + /** + * Machine model supported by the agent. The type of this attribute is + * ::hsa_machine_model_t. + */ + HSA_AGENT_INFO_MACHINE_MODEL = 3, + /** + * Profile supported by the agent. The type of this attribute is + * ::hsa_profile_t. + */ + HSA_AGENT_INFO_PROFILE = 4, + /** + * Default floating-point rounding mode. The type of this attribute is + * ::hsa_default_float_rounding_mode_t, but the value + * ::HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT is not allowed. + */ + HSA_AGENT_INFO_DEFAULT_FLOAT_ROUNDING_MODE = 5, + /** + * Default floating-point rounding modes supported by the agent in the Base + * profile. The type of this attribute is a mask of + * ::hsa_default_float_rounding_mode_t. The default floating-point rounding + * mode (::HSA_AGENT_INFO_DEFAULT_FLOAT_ROUNDING_MODE) bit must not be set. + */ + HSA_AGENT_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES = 23, + /** + * Flag indicating that the f16 HSAIL operation is at least as fast as the + * f32 operation in the current agent. The value of this attribute is + * undefined if the agent is not a kernel agent. The type of this + * attribute is bool. + */ + HSA_AGENT_INFO_FAST_F16_OPERATION = 24, + /** + * Number of work-items in a wavefront. Must be a power of 2 in the range + * [1,256]. The value of this attribute is undefined if the agent is not + * a kernel agent. The type of this attribute is uint32_t. + */ + HSA_AGENT_INFO_WAVEFRONT_SIZE = 6, + /** + * Maximum number of work-items of each dimension of a work-group. Each + * maximum must be greater than 0. No maximum can exceed the value of + * ::HSA_AGENT_INFO_WORKGROUP_MAX_SIZE. The value of this attribute is + * undefined if the agent is not a kernel agent. The type of this + * attribute is uint16_t[3]. + */ + HSA_AGENT_INFO_WORKGROUP_MAX_DIM = 7, + /** + * Maximum total number of work-items in a work-group. The value of this + * attribute is undefined if the agent is not a kernel agent. The type + * of this attribute is uint32_t. + */ + HSA_AGENT_INFO_WORKGROUP_MAX_SIZE = 8, + /** + * Maximum number of work-items of each dimension of a grid. Each maximum must + * be greater than 0, and must not be smaller than the corresponding value in + * ::HSA_AGENT_INFO_WORKGROUP_MAX_DIM. No maximum can exceed the value of + * ::HSA_AGENT_INFO_GRID_MAX_SIZE. The value of this attribute is undefined if + * the agent is not a kernel agent. The type of this attribute is + * ::hsa_dim3_t. + */ + HSA_AGENT_INFO_GRID_MAX_DIM = 9, + /** + * Maximum total number of work-items in a grid. The value of this attribute + * is undefined if the agent is not a kernel agent. The type of this + * attribute is uint32_t. + */ + HSA_AGENT_INFO_GRID_MAX_SIZE = 10, + /** + * Maximum number of fbarriers per work-group. Must be at least 32. The value + * of this attribute is undefined if the agent is not a kernel agent. The + * type of this attribute is uint32_t. + */ + HSA_AGENT_INFO_FBARRIER_MAX_SIZE = 11, + /** + * Maximum number of queues that can be active (created but not destroyed) at + * one time in the agent. The type of this attribute is uint32_t. + */ + HSA_AGENT_INFO_QUEUES_MAX = 12, + /** + * Minimum number of packets that a queue created in the agent + * can hold. Must be a power of 2 greater than 0. Must not exceed + * the value of ::HSA_AGENT_INFO_QUEUE_MAX_SIZE. The type of this + * attribute is uint32_t. + */ + HSA_AGENT_INFO_QUEUE_MIN_SIZE = 13, + /** + * Maximum number of packets that a queue created in the agent can + * hold. Must be a power of 2 greater than 0. The type of this attribute + * is uint32_t. + */ + HSA_AGENT_INFO_QUEUE_MAX_SIZE = 14, + /** + * Type of a queue created in the agent. The type of this attribute is + * ::hsa_queue_type_t. + */ + HSA_AGENT_INFO_QUEUE_TYPE = 15, + /** + * Identifier of the NUMA node associated with the agent. The type of this + * attribute is uint32_t. + */ + HSA_AGENT_INFO_NODE = 16, + /** + * Type of hardware device associated with the agent. The type of this + * attribute is ::hsa_device_type_t. + */ + HSA_AGENT_INFO_DEVICE = 17, + /** + * Array of data cache sizes (L1..L4). Each size is expressed in bytes. A size + * of 0 for a particular level indicates that there is no cache information + * for that level. The type of this attribute is uint32_t[4]. + */ + HSA_AGENT_INFO_CACHE_SIZE = 18, + /** + * Instruction set architecture of the agent. The type of this attribute + * is ::hsa_isa_t. + */ + HSA_AGENT_INFO_ISA = 19, + /** + * Bit-mask indicating which extensions are supported by the agent. An + * extension with an ID of @p i is supported if the bit at position @p i is + * set. The type of this attribute is uint8_t[128]. + */ + HSA_AGENT_INFO_EXTENSIONS = 20, + /** + * Major version of the HSA runtime specification supported by the + * agent. The type of this attribute is uint16_t. + */ + HSA_AGENT_INFO_VERSION_MAJOR = 21, + /** + * Minor version of the HSA runtime specification supported by the + * agent. The type of this attribute is uint16_t. + */ + HSA_AGENT_INFO_VERSION_MINOR = 22 +} hsa_agent_info_t; + +/** + * @brief Get the current value of an attribute for a given agent. + * + * @param[in] agent A valid agent. + * + * @param[in] attribute Attribute to query. + * + * @param[out] value Pointer to an application-allocated buffer where to store + * the value of the attribute. If the buffer passed by the application is not + * large enough to hold the value of @p attribute, the behavior is undefined. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_AGENT The agent is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p attribute is an invalid + * agent attribute, or @p value is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_agent_get_info(hsa_agent_t agent, + hsa_agent_info_t attribute, + void *value); +#endif + +/** + * @brief Iterate over the available agents, and invoke an + * application-defined callback on every iteration. + * + * @param[in] callback Callback to be invoked once per agent. The HSA + * runtime passes two arguments to the callback, the agent and the + * application data. If @p callback returns a status other than + * ::HSA_STATUS_SUCCESS for a particular iteration, the traversal stops and + * ::hsa_iterate_agents returns that status value. + * + * @param[in] data Application data that is passed to @p callback on every + * iteration. May be NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p callback is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API + hsa_iterate_agents(hsa_status_t (*callback)(hsa_agent_t agent, void *data), + void *data); +#endif + +/* + +// If we do not know the size of an attribute, we need to query it first +// Note: this API will not be in the spec unless needed +hsa_status_t HSA_API hsa_agent_get_info_size( + hsa_agent_t agent, + hsa_agent_info_t attribute, + size_t* size); + +// Set the value of an agents attribute +// Note: this API will not be in the spec unless needed +hsa_status_t HSA_API hsa_agent_set_info( + hsa_agent_t agent, + hsa_agent_info_t attribute, + void* value); + +*/ + +/** + * @brief Exception policies applied in the presence of hardware exceptions. + */ +typedef enum { + /** + * If a hardware exception is detected, a work-item signals an exception. + */ + HSA_EXCEPTION_POLICY_BREAK = 1, + /** + * If a hardware exception is detected, a hardware status bit is set. + */ + HSA_EXCEPTION_POLICY_DETECT = 2 +} hsa_exception_policy_t; + +/** + * @brief Retrieve the exception policy support for a given combination of + * agent and profile + * + * @param[in] agent Agent. + * + * @param[in] profile Profile. + * + * @param[out] mask Pointer to a memory location where the HSA runtime stores a + * mask of ::hsa_exception_policy_t values. Must not be NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_AGENT The agent is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p profile is not a valid + * profile, or @p mask is NULL. + * + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_agent_get_exception_policies(hsa_agent_t agent, + hsa_profile_t profile, + uint16_t *mask); +#endif + +/** + * @brief Query if a given version of an extension is supported by an agent + * + * @param[in] extension Extension identifier. + * + * @param[in] agent Agent. + * + * @param[in] version_major Major version number. + * + * @param[in] version_minor Minor version number. + * + * @param[out] result Pointer to a memory location where the HSA runtime stores + * the result of the check. The result is true if the specified version of the + * extension is supported, and false otherwise. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_AGENT The agent is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p extension is not a valid + * extension, or @p result is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API + hsa_agent_extension_supported(uint16_t extension, hsa_agent_t agent, + uint16_t version_major, + uint16_t version_minor, bool *result); +#endif + +/** @} */ + +/** \defgroup signals Signals + * @{ + */ + +/** + * @brief Signal handle. + */ +typedef struct hsa_signal_s { + /** + * Opaque handle. The value 0 is reserved. + */ + uint64_t handle; +} hsa_signal_t; + +/** + * @brief Signal value. The value occupies 32 bits in small machine mode, and 64 + * bits in large machine mode. + */ +#ifdef HSA_LARGE_MODEL +typedef int64_t hsa_signal_value_t; +#else +typedef int32_t hsa_signal_value_t; +#endif + +/** + * @brief Create a signal. + * + * @param[in] initial_value Initial value of the signal. + * + * @param[in] num_consumers Size of @p consumers. A value of 0 indicates that + * any agent might wait on the signal. + * + * @param[in] consumers List of agents that might consume (wait on) the + * signal. If @p num_consumers is 0, this argument is ignored; otherwise, the + * HSA runtime might use the list to optimize the handling of the signal + * object. If an agent not listed in @p consumers waits on the returned + * signal, the behavior is undefined. The memory associated with @p consumers + * can be reused or freed after the function returns. + * + * @param[out] signal Pointer to a memory location where the HSA runtime will + * store the newly created signal handle. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is failure to allocate the + * resources required by the implementation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p signal is NULL, @p + * num_consumers is greater than 0 but @p consumers is NULL, or @p consumers + * contains duplicates. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API + hsa_signal_create(hsa_signal_value_t initial_value, uint32_t num_consumers, + const hsa_agent_t *consumers, hsa_signal_t *signal); +#endif + +/** + * @brief Destroy a signal previous created by ::hsa_signal_create. + * + * @param[in] signal Signal. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_SIGNAL @p signal is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT The handle in @p signal is 0. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_signal_destroy(hsa_signal_t signal); +#endif + +/** + * @brief Atomically read the current value of a signal. + * + * @param[in] signal Signal. + * + * @return Value of the signal. + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API hsa_signal_load_acquire(hsa_signal_t signal); +#endif + +/** + * @copydoc hsa_signal_load_acquire + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API hsa_signal_load_relaxed(hsa_signal_t signal); +#endif + +/** + * @brief Atomically set the value of a signal. + * + * @details If the value of the signal is changed, all the agents waiting + * on @p signal for which @p value satisfies their wait condition are awakened. + * + * @param[in] signal Signal. + * + * @param[in] value New signal value. + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_store_relaxed(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_store_relaxed + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_store_release(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @brief Atomically set the value of a signal and return its previous value. + * + * @details If the value of the signal is changed, all the agents waiting + * on @p signal for which @p value satisfies their wait condition are awakened. + * + * @param[in] signal Signal. If @p signal is a queue doorbell signal, the + * behavior is undefined. + * + * @param[in] value New value. + * + * @return Value of the signal prior to the exchange. + * + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API + hsa_signal_exchange_acq_rel(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_exchange_acq_rel + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API + hsa_signal_exchange_acquire(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_exchange_acq_rel + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API + hsa_signal_exchange_relaxed(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_exchange_acq_rel + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API + hsa_signal_exchange_release(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @brief Atomically set the value of a signal if the observed value is equal to + * the expected value. The observed value is returned regardless of whether the + * replacement was done. + * + * @details If the value of the signal is changed, all the agents waiting + * on @p signal for which @p value satisfies their wait condition are awakened. + * + * @param[in] signal Signal. If @p signal is a queue + * doorbell signal, the behavior is undefined. + * + * @param[in] expected Value to compare with. + * + * @param[in] value New value. + * + * @return Observed value of the signal. + * + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API hsa_signal_cas_acq_rel(hsa_signal_t signal, + hsa_signal_value_t expected, + hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_cas_acq_rel + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API hsa_signal_cas_acquire(hsa_signal_t signal, + hsa_signal_value_t expected, + hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_cas_acq_rel + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API hsa_signal_cas_relaxed(hsa_signal_t signal, + hsa_signal_value_t expected, + hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_cas_acq_rel + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API hsa_signal_cas_release(hsa_signal_t signal, + hsa_signal_value_t expected, + hsa_signal_value_t value); +#endif + +/** + * @brief Atomically increment the value of a signal by a given amount. + * + * @details If the value of the signal is changed, all the agents waiting on + * @p signal for which @p value satisfies their wait condition are awakened. + * + * @param[in] signal Signal. If @p signal is a queue doorbell signal, the + * behavior is undefined. + * + * @param[in] value Value to add to the value of the signal. + * + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_add_acq_rel(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_add_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_add_acquire(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_add_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_add_relaxed(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_add_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_add_release(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @brief Atomically decrement the value of a signal by a given amount. + * + * @details If the value of the signal is changed, all the agents waiting on + * @p signal for which @p value satisfies their wait condition are awakened. + * + * @param[in] signal Signal. If @p signal is a queue doorbell signal, the + * behavior is undefined. + * + * @param[in] value Value to subtract from the value of the signal. + * + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_subtract_acq_rel(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_subtract_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_subtract_acquire(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_subtract_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_subtract_relaxed(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_subtract_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_subtract_release(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @brief Atomically perform a bitwise AND operation between the value of a + * signal and a given value. + * + * @details If the value of the signal is changed, all the agents waiting on + * @p signal for which @p value satisfies their wait condition are awakened. + * + * @param[in] signal Signal. If @p signal is a queue doorbell signal, the + * behavior is undefined. + * + * @param[in] value Value to AND with the value of the signal. + * + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_and_acq_rel(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_and_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_and_acquire(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_and_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_and_relaxed(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_and_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_and_release(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @brief Atomically perform a bitwise OR operation between the value of a + * signal and a given value. + * + * @details If the value of the signal is changed, all the agents waiting on + * @p signal for which @p value satisfies their wait condition are awakened. + * + * @param[in] signal Signal. If @p signal is a queue doorbell signal, the + * behavior is undefined. + * + * @param[in] value Value to OR with the value of the signal. + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_or_acq_rel(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_or_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_or_acquire(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_or_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_or_relaxed(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_or_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_or_release(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @brief Atomically perform a bitwise XOR operation between the value of a + * signal and a given value. + * + * @details If the value of the signal is changed, all the agents waiting on + * @p signal for which @p value satisfies their wait condition are awakened. + * + * @param[in] signal Signal. If @p signal is a queue doorbell signal, the + * behavior is undefined. + * + * @param[in] value Value to XOR with the value of the signal. + * + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_xor_acq_rel(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_xor_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_xor_acquire(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_xor_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_xor_relaxed(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @copydoc hsa_signal_xor_acq_rel + */ +#ifndef DEVICE_COMPILER +void HSA_API + hsa_signal_xor_release(hsa_signal_t signal, hsa_signal_value_t value); +#endif + +/** + * @brief Wait condition operator. + */ +typedef enum { + /** + * The two operands are equal. + */ + HSA_SIGNAL_CONDITION_EQ = 0, + /** + * The two operands are not equal. + */ + HSA_SIGNAL_CONDITION_NE = 1, + /** + * The first operand is less than the second operand. + */ + HSA_SIGNAL_CONDITION_LT = 2, + /** + * The first operand is greater than or equal to the second operand. + */ + HSA_SIGNAL_CONDITION_GTE = 3 +} hsa_signal_condition_t; + +/** + * @brief State of the application thread during a signal wait. + */ +typedef enum { + /** + * The application thread may be rescheduled while waiting on the signal. + */ + HSA_WAIT_STATE_BLOCKED = 0, + /** + * The application thread stays active while waiting on a signal. + */ + HSA_WAIT_STATE_ACTIVE = 1 +} hsa_wait_state_t; + +/** + * @brief Wait until a signal value satisfies a specified condition, or a + * certain amount of time has elapsed. + * + * @details A wait operation can spuriously resume at any time sooner than the + * timeout (for example, due to system or other external factors) even when the + * condition has not been met. + * + * The function is guaranteed to return if the signal value satisfies the + * condition at some point in time during the wait, but the value returned to + * the application might not satisfy the condition. The application must ensure + * that signals are used in such way that wait wakeup conditions are not + * invalidated before dependent threads have woken up. + * + * When the wait operation internally loads the value of the passed signal, it + * uses the memory order indicated in the function name. + * + * @param[in] signal Signal. + * + * @param[in] condition Condition used to compare the signal value with @p + * compare_value. + * + * @param[in] compare_value Value to compare with. + * + * @param[in] timeout_hint Maximum duration of the wait. Specified in the same + * unit as the system timestamp. The operation might block for a shorter or + * longer time even if the condition is not met. A value of UINT64_MAX indicates + * no maximum. + * + * @param[in] wait_state_hint Hint used by the application to indicate the + * preferred waiting state. The actual waiting state is ultimately decided by + * HSA runtime and may not match the provided hint. A value of + * ::HSA_WAIT_STATE_ACTIVE may improve the latency of response to a signal + * update by avoiding rescheduling overhead. + * + * @return Observed value of the signal, which might not satisfy the specified + * condition. + * + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API + hsa_signal_wait_acquire(hsa_signal_t signal, + hsa_signal_condition_t condition, + hsa_signal_value_t compare_value, + uint64_t timeout_hint, + hsa_wait_state_t wait_state_hint); +#endif + +/** + * @copydoc hsa_signal_wait_acquire + */ +#ifndef DEVICE_COMPILER +hsa_signal_value_t HSA_API + hsa_signal_wait_relaxed(hsa_signal_t signal, + hsa_signal_condition_t condition, + hsa_signal_value_t compare_value, + uint64_t timeout_hint, + hsa_wait_state_t wait_state_hint); +#endif + +/** @} */ + +/** \defgroup memory Memory + * @{ + */ + +/** + * @brief A memory region represents a block of virtual memory with certain + * properties. For example, the HSA runtime represents fine-grained memory in + * the global segment using a region. A region might be associated with more + * than one agent. + */ +typedef struct hsa_region_s { + /** + * Opaque handle. + */ + uint64_t handle; +} hsa_region_t; + +/** @} */ + +/** \defgroup queue Queues + * @{ + */ + +/** + * @brief Queue type. Intended to be used for dynamic queue protocol + * determination. + */ +typedef enum { + /** + * Queue supports multiple producers. + */ + HSA_QUEUE_TYPE_MULTI = 0, + /** + * Queue only supports a single producer. + */ + HSA_QUEUE_TYPE_SINGLE = 1 +} hsa_queue_type_t; + +/** + * @brief Queue features. + */ +typedef enum { + /** + * Queue supports kernel dispatch packets. + */ + HSA_QUEUE_FEATURE_KERNEL_DISPATCH = 1, + + /** + * Queue supports agent dispatch packets. + */ + HSA_QUEUE_FEATURE_AGENT_DISPATCH = 2 +} hsa_queue_feature_t; + +/** + * @brief User mode queue. + * + * @details The queue structure is read-only and allocated by the HSA runtime, + * but agents can directly modify the contents of the buffer pointed by @a + * base_address, or use HSA runtime APIs to access the doorbell signal. + * + */ +typedef struct hsa_queue_s { + /** + * Queue type. + */ + hsa_queue_type_t type; + + /** + * Queue features mask. This is a bit-field of ::hsa_queue_feature_t + * values. Applications should ignore any unknown set bits. + */ + uint32_t features; + +#ifdef HSA_LARGE_MODEL +#ifdef DEVICE_COMPILER + __global +#endif + void *base_address; +#elif defined HSA_LITTLE_ENDIAN + /** + * Starting address of the HSA runtime-allocated buffer used to store the AQL + * packets. Must be aligned to the size of an AQL packet. + */ +#ifdef DEVICE_COMPILER + __global +#endif + void *base_address; + /** + * Reserved. Must be 0. + */ + uint32_t reserved0; +#else + uint32_t reserved0; +#ifdef DEVICE_COMPILER + __global +#endif + void *base_address; +#endif + + /** + * Signal object used by the application to indicate the ID of a packet that + * is ready to be processed. The HSA runtime manages the doorbell signal. If + * the application tries to replace or destroy this signal, the behavior is + * undefined. + * + * If @a type is ::HSA_QUEUE_TYPE_SINGLE the doorbell signal value must be + * updated in a monotonically increasing fashion. If @a type is + * ::HSA_QUEUE_TYPE_MULTI, the doorbell signal value can be updated with any + * value. + */ + hsa_signal_t doorbell_signal; + + /** + * Maximum number of packets the queue can hold. Must be a power of 2. + */ + uint32_t size; + /** + * Reserved. Must be 0. + */ + uint32_t reserved1; + /** + * Queue identifier, which is unique over the lifetime of the application. + */ + uint64_t id; + +} hsa_queue_t; + +/** + * @brief Create a user mode queue. + * + * @details The HSA runtime creates the queue structure, the underlying packet + * buffer, the completion signal, and the write and read indexes. The initial + * value of the write and read indexes is 0. The type of every packet in the + * buffer is initialized to ::HSA_PACKET_TYPE_INVALID. + * + * The application should only rely on the error code returned to determine if + * the queue is valid. + * + * @param[in] agent Agent where to create the queue. + * + * @param[in] size Number of packets the queue is expected to + * hold. Must be a power of 2 between 1 and the value of + * ::HSA_AGENT_INFO_QUEUE_MAX_SIZE in @p agent. The size of the newly + * created queue is the maximum of @p size and the value of + * ::HSA_AGENT_INFO_QUEUE_MIN_SIZE in @p agent. + * + * @param[in] type Type of the queue. If the value of + * ::HSA_AGENT_INFO_QUEUE_TYPE in @p agent is ::HSA_QUEUE_TYPE_SINGLE, then @p + * type must also be ::HSA_QUEUE_TYPE_SINGLE. + * + * @param[in] callback Callback invoked by the HSA runtime for every + * asynchronous event related to the newly created queue. May be NULL. The HSA + * runtime passes three arguments to the callback: a code identifying the event + * that triggered the invocation, a pointer to the queue where the event + * originated, and the application data. + * + * @param[in] data Application data that is passed to @p callback on every + * iteration. May be NULL. + * + * @param[in] private_segment_size Hint indicating the maximum + * expected private segment usage per work-item, in bytes. There may + * be performance degradation if the application places a kernel + * dispatch packet in the queue and the corresponding private segment + * usage exceeds @p private_segment_size. If the application does not + * want to specify any particular value for this argument, @p + * private_segment_size must be UINT32_MAX. If the queue does not + * support kernel dispatch packets, this argument is ignored. + * + * @param[in] group_segment_size Hint indicating the maximum expected + * group segment usage per work-group, in bytes. There may be + * performance degradation if the application places a kernel dispatch + * packet in the queue and the corresponding group segment usage + * exceeds @p group_segment_size. If the application does not want to + * specify any particular value for this argument, @p + * group_segment_size must be UINT32_MAX. If the queue does not + * support kernel dispatch packets, this argument is ignored. + * + * @param[out] queue Memory location where the HSA runtime stores a pointer to + * the newly created queue. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is failure to allocate + * the resources required by the implementation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_AGENT The agent is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_QUEUE_CREATION @p agent does not + * support queues of the given type. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p size is not a power of two, + * @p size is 0, @p type is an invalid queue type, or @p queue is NULL. + * + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API + hsa_queue_create(hsa_agent_t agent, uint32_t size, hsa_queue_type_t type, + void (*callback)(hsa_status_t status, hsa_queue_t *source, + void *data), + void *data, uint32_t private_segment_size, + uint32_t group_segment_size, hsa_queue_t **queue); +#endif + +/** + * @brief Create a queue for which the application or a kernel is responsible + * for processing the AQL packets. + * + * @details The application can use this function to create queues where AQL + * packets are not parsed by the packet processor associated with an agent, + * but rather by a unit of execution running on that agent (for example, a + * thread in the host application). + * + * The application is responsible for ensuring that all the producers and + * consumers of the resulting queue can access the provided doorbell signal + * and memory region. The application is also responsible for ensuring that the + * unit of execution processing the queue packets supports the indicated + * features (AQL packet types). + * + * When the queue is created, the HSA runtime allocates the packet buffer using + * @p region, and the write and read indexes. The initial value of the write and + * read indexes is 0, and the type of every packet in the buffer is initialized + * to ::HSA_PACKET_TYPE_INVALID. The value of the @e size, @e type, @e features, + * and @e doorbell_signal fields in the returned queue match the values passed + * by the application. + * + * @param[in] region Memory region that the HSA runtime should use to allocate + * the AQL packet buffer and any other queue metadata. + * + * @param[in] size Number of packets the queue is expected to hold. Must be a + * power of 2 greater than 0. + * + * @param[in] type Queue type. + * + * @param[in] features Supported queue features. This is a bit-field of + * ::hsa_queue_feature_t values. + * + * @param[in] doorbell_signal Doorbell signal that the HSA runtime must + * associate with the returned queue. The signal handle must not be 0. + * + * @param[out] queue Memory location where the HSA runtime stores a pointer to + * the newly created queue. The application should not rely on the value + * returned for this argument but only in the status code to determine if the + * queue is valid. Must not be NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is failure to allocate + * the resources required by the implementation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p size is not a power of two, @p + * size is 0, @p type is an invalid queue type, the doorbell signal handle is + * 0, or @p queue is NULL. + * + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API + hsa_soft_queue_create(hsa_region_t region, uint32_t size, + hsa_queue_type_t type, uint32_t features, + hsa_signal_t doorbell_signal, hsa_queue_t **queue); +#endif + +/** + * @brief Destroy a user mode queue. + * + * @details When a queue is destroyed, the state of the AQL packets that have + * not been yet fully processed (their completion phase has not finished) + * becomes undefined. It is the responsibility of the application to ensure that + * all pending queue operations are finished if their results are required. + * + * The resources allocated by the HSA runtime during queue creation (queue + * structure, ring buffer, doorbell signal) are released. The queue should not + * be accessed after being destroyed. + * + * @param[in] queue Pointer to a queue created using ::hsa_queue_create. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_QUEUE The queue is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p queue is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_queue_destroy(hsa_queue_t *queue); +#endif + +/** + * @brief Inactivate a queue. + * + * @details Inactivating the queue aborts any pending executions and prevent any + * new packets from being processed. Any more packets written to the queue once + * it is inactivated will be ignored by the packet processor. + * + * @param[in] queue Pointer to a queue. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_QUEUE The queue is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p queue is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_queue_inactivate(hsa_queue_t *queue); +#endif + +/** + * @brief Atomically load the read index of a queue. + * + * @param[in] queue Pointer to a queue. + * + * @return Read index of the queue pointed by @p queue. + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API hsa_queue_load_read_index_acquire(const hsa_queue_t *queue); +#endif + +/** + * @copydoc hsa_queue_load_read_index_acquire + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API hsa_queue_load_read_index_relaxed(const hsa_queue_t *queue); +#endif + +/** + * @brief Atomically load the write index of a queue. + * + * @param[in] queue Pointer to a queue. + * + * @return Write index of the queue pointed by @p queue. + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API hsa_queue_load_write_index_acquire(const hsa_queue_t *queue); +#endif + +/** + * @copydoc hsa_queue_load_write_index_acquire + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API hsa_queue_load_write_index_relaxed(const hsa_queue_t *queue); +#endif + +/** + * @brief Atomically set the write index of a queue. + * + * @param[in] queue Pointer to a queue. + * + * @param[in] value Value to assign to the write index. + * + */ +#ifndef DEVICE_COMPILER +void HSA_API hsa_queue_store_write_index_relaxed(const hsa_queue_t *queue, + uint64_t value); +#endif + +/** + * @copydoc hsa_queue_store_write_index_relaxed + */ +#ifndef DEVICE_COMPILER +void HSA_API hsa_queue_store_write_index_release(const hsa_queue_t *queue, + uint64_t value); +#endif + +/** + * @brief Atomically set the write index of a queue if the observed value is + * equal to the expected value. The application can inspect the returned value + * to determine if the replacement was done. + * + * @param[in] queue Pointer to a queue. + * + * @param[in] expected Expected value. + * + * @param[in] value Value to assign to the write index if @p expected matches + * the observed write index. Must be greater than @p expected. + * + * @return Previous value of the write index. + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API hsa_queue_cas_write_index_acq_rel(const hsa_queue_t *queue, + uint64_t expected, + uint64_t value); +#endif + +/** + * @copydoc hsa_queue_cas_write_index_acq_rel + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API hsa_queue_cas_write_index_acquire(const hsa_queue_t *queue, + uint64_t expected, + uint64_t value); +#endif + +/** + * @copydoc hsa_queue_cas_write_index_acq_rel + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API hsa_queue_cas_write_index_relaxed(const hsa_queue_t *queue, + uint64_t expected, + uint64_t value); +#endif + +/** + * @copydoc hsa_queue_cas_write_index_acq_rel + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API hsa_queue_cas_write_index_release(const hsa_queue_t *queue, + uint64_t expected, + uint64_t value); +#endif + +/** + * @brief Atomically increment the write index of a queue by an offset. + * + * @param[in] queue Pointer to a queue. + * + * @param[in] value Value to add to the write index. + * + * @return Previous value of the write index. + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API + hsa_queue_add_write_index_acq_rel(const hsa_queue_t *queue, uint64_t value); +#endif + +/** + * @copydoc hsa_queue_add_write_index_acq_rel + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API + hsa_queue_add_write_index_acquire(const hsa_queue_t *queue, uint64_t value); +#endif + +/** + * @copydoc hsa_queue_add_write_index_acq_rel + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API + hsa_queue_add_write_index_relaxed(const hsa_queue_t *queue, uint64_t value); +#endif + +/** + * @copydoc hsa_queue_add_write_index_acq_rel + */ +#ifndef DEVICE_COMPILER +uint64_t HSA_API + hsa_queue_add_write_index_release(const hsa_queue_t *queue, uint64_t value); +#endif + +/** + * @brief Atomically set the read index of a queue. + * + * @details Modifications of the read index are not allowed and result in + * undefined behavior if the queue is associated with an agent for which + * only the corresponding packet processor is permitted to update the read + * index. + * + * @param[in] queue Pointer to a queue. + * + * @param[in] value Value to assign to the read index. + * + */ +#ifndef DEVICE_COMPILER +void HSA_API hsa_queue_store_read_index_relaxed(const hsa_queue_t *queue, + uint64_t value); +#endif + +/** + * @copydoc hsa_queue_store_read_index_relaxed + */ +#ifndef DEVICE_COMPILER +void HSA_API hsa_queue_store_read_index_release(const hsa_queue_t *queue, + uint64_t value); +#endif +/** @} */ + +/** \defgroup aql Architected Queuing Language + * @{ + */ + +/** + * @brief Packet type. + */ +typedef enum { + /** + * Vendor-specific packet. + */ + HSA_PACKET_TYPE_VENDOR_SPECIFIC = 0, + /** + * The packet has been processed in the past, but has not been reassigned to + * the packet processor. A packet processor must not process a packet of this + * type. All queues support this packet type. + */ + HSA_PACKET_TYPE_INVALID = 1, + /** + * Packet used by agents for dispatching jobs to kernel agents. Not all + * queues support packets of this type (see ::hsa_queue_feature_t). + */ + HSA_PACKET_TYPE_KERNEL_DISPATCH = 2, + /** + * Packet used by agents to delay processing of subsequent packets, and to + * express complex dependencies between multiple packets. All queues support + * this packet type. + */ + HSA_PACKET_TYPE_BARRIER_AND = 3, + /** + * Packet used by agents for dispatching jobs to agents. Not all + * queues support packets of this type (see ::hsa_queue_feature_t). + */ + HSA_PACKET_TYPE_AGENT_DISPATCH = 4, + /** + * Packet used by agents to delay processing of subsequent packets, and to + * express complex dependencies between multiple packets. All queues support + * this packet type. + */ + HSA_PACKET_TYPE_BARRIER_OR = 5 +} hsa_packet_type_t; + +/** + * @brief Scope of the memory fence operation associated with a packet. + */ +typedef enum { + /** + * No scope (no fence is applied). The packet relies on external fences to + * ensure visibility of memory updates. + */ + HSA_FENCE_SCOPE_NONE = 0, + /** + * The fence is applied with agent scope for the global segment. + */ + HSA_FENCE_SCOPE_AGENT = 1, + /** + * The fence is applied across both agent and system scope for the global + * segment. + */ + HSA_FENCE_SCOPE_SYSTEM = 2 +} hsa_fence_scope_t; + +/** + * @brief Sub-fields of the @a header field that is present in any AQL + * packet. The offset (with respect to the address of @a header) of a sub-field + * is identical to its enumeration constant. The width of each sub-field is + * determined by the corresponding value in ::hsa_packet_header_width_t. The + * offset and the width are expressed in bits. + */ +typedef enum { + /** + * Packet type. The value of this sub-field must be one of + * ::hsa_packet_type_t. If the type is ::HSA_PACKET_TYPE_VENDOR_SPECIFIC, the + * packet layout is vendor-specific. + */ + HSA_PACKET_HEADER_TYPE = 0, + /** + * Barrier bit. If the barrier bit is set, the processing of the current + * packet only launches when all preceding packets (within the same queue) are + * complete. + */ + HSA_PACKET_HEADER_BARRIER = 8, + /** + * Acquire fence scope. The value of this sub-field determines the scope and + * type of the memory fence operation applied before the packet enters the + * active phase. An acquire fence ensures that any subsequent global segment + * or image loads by any unit of execution that belongs to a dispatch that has + * not yet entered the active phase on any queue of the same kernel agent, + * sees any data previously released at the scopes specified by the acquire + * fence. The value of this sub-field must be one of ::hsa_fence_scope_t. + */ + HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE = 9, + /** + * Release fence scope, The value of this sub-field determines the scope and + * type of the memory fence operation applied after kernel completion but + * before the packet is completed. A release fence makes any global segment or + * image data that was stored by any unit of execution that belonged to a + * dispatch that has completed the active phase on any queue of the same + * kernel agent visible in all the scopes specified by the release fence. The + * value of this sub-field must be one of ::hsa_fence_scope_t. + */ + HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE = 11 +} hsa_packet_header_t; + +/** + * @brief Width (in bits) of the sub-fields in ::hsa_packet_header_t. + */ +typedef enum { + HSA_PACKET_HEADER_WIDTH_TYPE = 8, + HSA_PACKET_HEADER_WIDTH_BARRIER = 1, + HSA_PACKET_HEADER_WIDTH_ACQUIRE_FENCE_SCOPE = 2, + HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE = 2 +} hsa_packet_header_width_t; + +/** + * @brief Sub-fields of the kernel dispatch packet @a setup field. The offset + * (with respect to the address of @a setup) of a sub-field is identical to its + * enumeration constant. The width of each sub-field is determined by the + * corresponding value in ::hsa_kernel_dispatch_packet_setup_width_t. The + * offset and the width are expressed in bits. + */ +typedef enum { + /** + * Number of dimensions of the grid. Valid values are 1, 2, or 3. + * + */ + HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS = 0 +} hsa_kernel_dispatch_packet_setup_t; + +/** + * @brief Width (in bits) of the sub-fields in + * ::hsa_kernel_dispatch_packet_setup_t. + */ +typedef enum { + HSA_KERNEL_DISPATCH_PACKET_SETUP_WIDTH_DIMENSIONS = 2 +} hsa_kernel_dispatch_packet_setup_width_t; + +/** + * @brief AQL kernel dispatch packet + */ +typedef struct hsa_kernel_dispatch_packet_s { + /** + * Packet header. Used to configure multiple packet parameters such as the + * packet type. The parameters are described by ::hsa_packet_header_t. + */ + uint16_t header; + + /** + * Dispatch setup parameters. Used to configure kernel dispatch parameters + * such as the number of dimensions in the grid. The parameters are described + * by ::hsa_kernel_dispatch_packet_setup_t. + */ + uint16_t setup; + + /** + * X dimension of work-group, in work-items. Must be greater than 0. + */ + uint16_t workgroup_size_x; + + /** + * Y dimension of work-group, in work-items. Must be greater than + * 0. If the grid has 1 dimension, the only valid value is 1. + */ + uint16_t workgroup_size_y; + + /** + * Z dimension of work-group, in work-items. Must be greater than + * 0. If the grid has 1 or 2 dimensions, the only valid value is 1. + */ + uint16_t workgroup_size_z; + + /** + * Reserved. Must be 0. + */ + uint16_t reserved0; + + /** + * X dimension of grid, in work-items. Must be greater than 0. Must + * not be smaller than @a workgroup_size_x. + */ + uint32_t grid_size_x; + + /** + * Y dimension of grid, in work-items. Must be greater than 0. If the grid has + * 1 dimension, the only valid value is 1. Must not be smaller than @a + * workgroup_size_y. + */ + uint32_t grid_size_y; + + /** + * Z dimension of grid, in work-items. Must be greater than 0. If the grid has + * 1 or 2 dimensions, the only valid value is 1. Must not be smaller than @a + * workgroup_size_z. + */ + uint32_t grid_size_z; + + /** + * Size in bytes of private memory allocation request (per work-item). + */ + uint32_t private_segment_size; + + /** + * Size in bytes of group memory allocation request (per work-group). Must not + * be less than the sum of the group memory used by the kernel (and the + * functions it calls directly or indirectly) and the dynamically allocated + * group segment variables. + */ + uint32_t group_segment_size; + + /** + * Opaque handle to a code object that includes an implementation-defined + * executable code for the kernel. + */ + union { +#ifdef DEVICE_COMPILER + __global +#endif + void *kernel_object; + uint64_t kernel_object_padding; + }; + +#ifdef HSA_LARGE_MODEL +#ifdef DEVICE_COMPILER + __global +#endif + void *kernarg_address; +#elif defined HSA_LITTLE_ENDIAN + /** + * Pointer to a buffer containing the kernel arguments. May be NULL. + * + * The buffer must be allocated using ::hsa_memory_allocate, and must not be + * modified once the kernel dispatch packet is enqueued until the dispatch has + * completed execution. + */ +#ifdef DEVICE_COMPILER + __global +#endif + void *kernarg_address; + /** + * Reserved. Must be 0. + */ + uint32_t reserved1; +#else + uint32_t reserved1; +#ifdef DEVICE_COMPILER + __global +#endif + void *kernarg_address; +#endif + + /** + * Reserved. Must be 0. + */ + uint64_t reserved2; + + /** + * Signal used to indicate completion of the job. The application can use the + * special signal handle 0 to indicate that no signal is used. + */ + hsa_signal_t completion_signal; + +} hsa_kernel_dispatch_packet_t; + +/** + * @brief Agent dispatch packet. + */ +typedef struct hsa_agent_dispatch_packet_s { + /** + * Packet header. Used to configure multiple packet parameters such as the + * packet type. The parameters are described by ::hsa_packet_header_t. + */ + uint16_t header; + + /** + * Application-defined function to be performed by the destination agent. + */ + uint16_t type; + + /** + * Reserved. Must be 0. + */ + uint32_t reserved0; + +#ifdef HSA_LARGE_MODEL +#ifdef DEVICE_COMPILER + __constant +#endif + void *return_address; +#elif defined HSA_LITTLE_ENDIAN + /** + * Address where to store the function return values, if any. + */ +#ifdef DEVICE_COMPILER + __constant +#endif + void *return_address; + /** + * Reserved. Must be 0. + */ + uint32_t reserved1; +#else + uint32_t reserved1; +#ifdef DEVICE_COMPILER + __constant +#endif + void *return_address; +#endif + + /** + * Function arguments. + */ + uint64_t arg[4]; + + /** + * Reserved. Must be 0. + */ + uint64_t reserved2; + + /** + * Signal used to indicate completion of the job. The application can use the + * special signal handle 0 to indicate that no signal is used. + */ + hsa_signal_t completion_signal; + +} hsa_agent_dispatch_packet_t; + +/** + * @brief Barrier-AND packet. + */ +typedef struct hsa_barrier_and_packet_s { + /** + * Packet header. Used to configure multiple packet parameters such as the + * packet type. The parameters are described by ::hsa_packet_header_t. + */ + uint16_t header; + + /** + * Reserved. Must be 0. + */ + uint16_t reserved0; + + /** + * Reserved. Must be 0. + */ + uint32_t reserved1; + + /** + * Array of dependent signal objects. Signals with a handle value of 0 are + * allowed and are interpreted by the packet processor as satisfied + * dependencies. + */ + hsa_signal_t dep_signal[5]; + + /** + * Reserved. Must be 0. + */ + uint64_t reserved2; + + /** + * Signal used to indicate completion of the job. The application can use the + * special signal handle 0 to indicate that no signal is used. + */ + hsa_signal_t completion_signal; + +} hsa_barrier_and_packet_t; + +/** + * @brief Barrier-OR packet. + */ +typedef struct hsa_barrier_or_packet_s { + /** + * Packet header. Used to configure multiple packet parameters such as the + * packet type. The parameters are described by ::hsa_packet_header_t. + */ + uint16_t header; + + /** + * Reserved. Must be 0. + */ + uint16_t reserved0; + + /** + * Reserved. Must be 0. + */ + uint32_t reserved1; + + /** + * Array of dependent signal objects. Signals with a handle value of 0 are + * allowed and are interpreted by the packet processor as dependencies not + * satisfied. + */ + hsa_signal_t dep_signal[5]; + + /** + * Reserved. Must be 0. + */ + uint64_t reserved2; + + /** + * Signal used to indicate completion of the job. The application can use the + * special signal handle 0 to indicate that no signal is used. + */ + hsa_signal_t completion_signal; + +} hsa_barrier_or_packet_t; + +/** @} */ + +/** \addtogroup memory Memory + * @{ + */ + +/** + * @brief Memory segments associated with a region. + */ +typedef enum { + /** + * Global segment. Used to hold data that is shared by all agents. + */ + HSA_REGION_SEGMENT_GLOBAL = 0, + /** + * Read-only segment. Used to hold data that remains constant during the + * execution of a kernel. + */ + HSA_REGION_SEGMENT_READONLY = 1, + /** + * Private segment. Used to hold data that is local to a single work-item. + */ + HSA_REGION_SEGMENT_PRIVATE = 2, + /** + * Group segment. Used to hold data that is shared by the work-items of a + * work-group. + */ + HSA_REGION_SEGMENT_GROUP = 3 +} hsa_region_segment_t; + +/** + * @brief Global region flags. + */ +typedef enum { + /** + * The application can use memory in the region to store kernel arguments, and + * provide the values for the kernarg segment of a kernel dispatch. If this + * flag is set, then ::HSA_REGION_GLOBAL_FLAG_FINE_GRAINED must be set. + */ + HSA_REGION_GLOBAL_FLAG_KERNARG = 1, + /** + * Updates to memory in this region are immediately visible to all the + * agents under the terms of the HSA memory model. If this + * flag is set, then ::HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED must not be set. + */ + HSA_REGION_GLOBAL_FLAG_FINE_GRAINED = 2, + /** + * Updates to memory in this region can be performed by a single agent at + * a time. If a different agent in the system is allowed to access the + * region, the application must explicitely invoke ::hsa_memory_assign_agent + * in order to transfer ownership to that agent for a particular buffer. + */ + HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED = 4 +} hsa_region_global_flag_t; + +/** + * @brief Attributes of a memory region. + */ +typedef enum { + /** + * Segment where memory in the region can be used. The type of this + * attribute is ::hsa_region_segment_t. + */ + HSA_REGION_INFO_SEGMENT = 0, + /** + * Flag mask. The value of this attribute is undefined if the value of + * ::HSA_REGION_INFO_SEGMENT is not ::HSA_REGION_SEGMENT_GLOBAL. The type of + * this attribute is uint32_t, a bit-field of ::hsa_region_global_flag_t + * values. + */ + HSA_REGION_INFO_GLOBAL_FLAGS = 1, + /** + * Size of this region, in bytes. The type of this attribute is size_t. + */ + HSA_REGION_INFO_SIZE = 2, + /** + * Maximum allocation size in this region, in bytes. Must not exceed the value + * of ::HSA_REGION_INFO_SIZE. The type of this attribute is size_t. + * + * If the region is in the global or readonly segments, this is the maximum + * size that the application can pass to ::hsa_memory_allocate. If the region + * is in the group segment, this is the maximum size (per work-group) that can + * be requested for a given kernel dispatch. If the region is in the private + * segment, this is the maximum size (per work-item) that can be request for a + * specific kernel dispatch. + */ + HSA_REGION_INFO_ALLOC_MAX_SIZE = 4, + /** + * Indicates whether memory in this region can be allocated using + * ::hsa_memory_allocate. The type of this attribute is bool. + * + * The value of this flag is always false for regions in the group and private + * segments. + */ + HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED = 5, + /** + * Allocation granularity of buffers allocated by ::hsa_memory_allocate in + * this region. The size of a buffer allocated in this region is a multiple of + * the value of this attribute. The value of this attribute is only defined if + * ::HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED is true for this region. The type + * of this attribute is size_t. + */ + HSA_REGION_INFO_RUNTIME_ALLOC_GRANULE = 6, + /** + * Alignment of buffers allocated by ::hsa_memory_allocate in this region. The + * value of this attribute is only defined if + * ::HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED is true for this region, and must + * be a power of 2. The type of this attribute is size_t. + */ + HSA_REGION_INFO_RUNTIME_ALLOC_ALIGNMENT = 7 +} hsa_region_info_t; + +/** + * @brief Get the current value of an attribute of a region. + * + * @param[in] region A valid region. + * + * @param[in] attribute Attribute to query. + * + * @param[out] value Pointer to a application-allocated buffer where to store + * the value of the attribute. If the buffer passed by the application is not + * large enough to hold the value of @p attribute, the behavior is undefined. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_REGION The region is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p attribute is an invalid + * region attribute, or @p value is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_region_get_info(hsa_region_t region, + hsa_region_info_t attribute, + void *value); +#endif + +/** + * @brief Iterate over the memory regions associated with a given agent, and + * invoke an application-defined callback on every iteration. + * + * @param[in] agent A valid agent. + * + * @param[in] callback Callback to be invoked once per region that is + * accessible from the agent. The HSA runtime passes two arguments to the + * callback, the region and the application data. If @p callback returns a + * status other than ::HSA_STATUS_SUCCESS for a particular iteration, the + * traversal stops and ::hsa_agent_iterate_regions returns that status value. + * + * @param[in] data Application data that is passed to @p callback on every + * iteration. May be NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_AGENT The agent is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p callback is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_agent_iterate_regions( + hsa_agent_t agent, + hsa_status_t (*callback)(hsa_region_t region, void *data), void *data); +#endif + +/** + * @brief Allocate a block of memory in a given region. + * + * @param[in] region Region where to allocate memory from. The region must have + * the ::HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED flag set. + * + * @param[in] size Allocation size, in bytes. Must not be zero. This value is + * rounded up to the nearest multiple of ::HSA_REGION_INFO_RUNTIME_ALLOC_GRANULE + * in @p region. + * + * @param[out] ptr Pointer to the location where to store the base address of + * the allocated block. The returned base address is aligned to the value of + * ::HSA_REGION_INFO_RUNTIME_ALLOC_ALIGNMENT in @p region. If the allocation + * fails, the returned value is undefined. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES No memory is available. + * + * @retval ::HSA_STATUS_ERROR_INVALID_REGION The region is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ALLOCATION The host is not allowed to + * allocate memory in @p region, or @p size is greater than the value of + * HSA_REGION_INFO_ALLOC_MAX_SIZE in @p region. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p ptr is NULL, or @p size is 0. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API + hsa_memory_allocate(hsa_region_t region, size_t size, void **ptr); +#endif + +/** + * @brief Deallocate a block of memory previously allocated using + * ::hsa_memory_allocate. + * + * @param[in] ptr Pointer to a memory block. If @p ptr does not match a value + * previously returned by ::hsa_memory_allocate, the behavior is undefined. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_memory_free(void *ptr); +#endif + +/** + * @brief Copy a block of memory. + * + * @param[out] dst Buffer where the content is to be copied. + * + * @param[in] src A valid pointer to the source of data to be copied. + * + * @param[in] size Number of bytes to copy. If @p size is 0, no copy is + * performed and the function returns success. Copying a number of bytes larger + * than the size of the buffers pointed by @p dst or @p src results in undefined + * behavior. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT The source or destination + * pointers are NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_memory_copy(void *dst, const void *src, size_t size); +#endif + +/** + * @brief Change the ownership of a global, coarse-grained buffer. + * + * @details The contents of a coarse-grained buffer are visible to an agent + * only after ownership has been explicitely transferred to that agent. Once the + * operation completes, the previous owner cannot longer access the data in the + * buffer. + * + * An implementation of the HSA runtime is allowed, but not required, to change + * the physical location of the buffer when ownership is transferred to a + * different agent. In general the application must not assume this + * behavior. The virtual location (address) of the passed buffer is never + * modified. + * + * @param[in] ptr Base address of a global buffer. The pointer should match an + * address previously returned by ::hsa_memory_allocate. The size of the buffer + * affected by the ownership change is identical to the size of that previous + * allocation. If @p ptr points to a fine-grained global buffer, no operation is + * performed and the function returns success. If @p ptr does not point to + * global memory, the behavior is undefined. + * + * @param[in] agent Agent that becomes the owner of the buffer. The + * application is responsible for ensuring that @p agent has access to the + * region that contains the buffer. It is allowed to change ownership to an + * agent that is already the owner of the buffer, with the same or different + * access permissions. + * + * @param[in] access Access permissions requested for the new owner. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_AGENT The agent is invalid. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES The HSA runtime is unable to + * acquire the resources required by the operation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p ptr is NULL, or @p access is + * not a valid access value. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_memory_assign_agent(void *ptr, hsa_agent_t agent, + hsa_access_permission_t access); +#endif + +/** + * + * @brief Register a global, fine-grained buffer. + * + * @details Registering a buffer serves as an indication to the HSA runtime that + * the memory might be accessed from a kernel agent other than the + * host. Registration is a performance hint that allows the HSA runtime + * implementation to know which buffers will be accessed by some of the kernel + * agents ahead of time. + * + * Registration is only recommended for buffers in the global segment that have + * not been allocated using the HSA allocator (::hsa_memory_allocate), but an OS + * allocator instead. + * + * Registrations should not overlap. + * + * @param[in] ptr A buffer in global memory. If a NULL pointer is passed, no + * operation is performed. + * + * @param[in] size Requested registration size in bytes. A size of 0 is + * only allowed if @p ptr is NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is a failure in + * allocating the necessary resources. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p size is 0 but @p ptr + * is not NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_memory_register(void *ptr, size_t size); +#endif + +/** + * + * @brief Deregister memory previously registered using ::hsa_memory_register. + * + * @details If the memory interval being deregistered does not match a previous + * registration (start and end addresses), the behavior is undefined. + * + * @param[in] ptr A pointer to the base of the buffer to be deregistered. If + * a NULL pointer is passed, no operation is performed. + * + * @param[in] size Size of the buffer to be deregistered. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_memory_deregister(void *ptr, size_t size); +#endif + +/** @} */ + +/** \defgroup symbol-attributes Symbol Attributes + * @{ + */ + +/** + * @brief Symbol type. + */ +typedef enum { + /** + * Variable. + */ + HSA_SYMBOL_KIND_VARIABLE = 0, + /** + * Kernel. + */ + HSA_SYMBOL_KIND_KERNEL = 1, + /** + * Indirect function. + */ + HSA_SYMBOL_KIND_INDIRECT_FUNCTION = 2 +} hsa_symbol_kind_t; + +/** + * @brief Allocation type of a variable. + */ +typedef enum { + /** + * Agent allocation. + */ + HSA_VARIABLE_ALLOCATION_AGENT = 0, + /** + * Program allocation. + */ + HSA_VARIABLE_ALLOCATION_PROGRAM = 1 +} hsa_variable_allocation_t; + +/** + * @brief Linkage type of a symbol. + */ +typedef enum { + /** + * Module linkage. + */ + HSA_SYMBOL_LINKAGE_MODULE = 0, + /** + * Program linkage. + */ + HSA_SYMBOL_LINKAGE_PROGRAM = 1 +} hsa_symbol_linkage_t; + +/** + * @brief Memory segment associated with a variable. + */ +typedef enum { + /** + * Global memory segment. + */ + HSA_VARIABLE_SEGMENT_GLOBAL = 0, + /** + * Readonly memory segment. + */ + HSA_VARIABLE_SEGMENT_READONLY = 1 +} hsa_variable_segment_t; + +/** @} */ + +/** \defgroup code-object Code Object + * @{ + */ + +/** + * @brief Instruction set architecture. + */ +typedef struct hsa_isa_s { + /** + * Opaque handle. + */ + uint64_t handle; +} hsa_isa_t; + +/** + * @brief Retrieve a reference to an ISA handle out of a symbolic name. + * + * @param[in] name Vendor-specific name associated with a particular instruction + * set architecture. Must be a NUL-terminated string. + * + * @param[out] isa Memory location where the HSA runtime stores the ISA handle + * corresponding to the given name. Must not be NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p name is NULL, or @p isa is + * NULL. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ISA_NAME The given name does not + * correspond to any instruction set architecture. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_isa_from_name( + const char* name, + hsa_isa_t* isa); +#endif + +/** + * @brief Instruction set architecture attributes. + */ +typedef enum { + /** + * The length of the ISA name. The type of this attribute is uint32_t. + */ + HSA_ISA_INFO_NAME_LENGTH = 0, + /** + * Human-readable description. The type of this attribute is character array + * with the length equal to the value of ::HSA_ISA_INFO_NAME_LENGTH attribute. + */ + HSA_ISA_INFO_NAME = 1, + /** + * Number of call conventions supported by the instruction set architecture. + * The type of this attribute is uint32_t. + */ + HSA_ISA_INFO_CALL_CONVENTION_COUNT = 2, + /** + * Number of work-items in a wavefront for a given call convention. Must be a + * power of 2 in the range [1,256]. The type of this attribute is uint32_t. + */ + HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONT_SIZE = 3, + /** + * Number of wavefronts per compute unit for a given call convention. In + * practice, other factors (for example, the amount of group memory used by a + * work-group) may further limit the number of wavefronts per compute + * unit. The type of this attribute is uint32_t. + */ + HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONTS_PER_COMPUTE_UNIT = 4 +} hsa_isa_info_t; + +/** + * @brief Get the current value of an attribute for a given instruction set + * architecture (ISA). + * + * @param[in] isa A valid instruction set architecture. + * + * @param[in] attribute Attribute to query. + * + * @param[in] index Call convention index. Used only for call convention + * attributes, otherwise ignored. Must have a value between 0 (inclusive) and + * the value of the attribute ::HSA_ISA_INFO_CALL_CONVENTION_COUNT (not + * inclusive) in @p isa. + * + * @param[out] value Pointer to an application-allocated buffer where to store + * the value of the attribute. If the buffer passed by the application is not + * large enough to hold the value of @p attribute, the behavior is undefined. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ISA The instruction set architecture is + * invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_INDEX @p index out of range. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p attribute is an invalid + * instruction set architecture attribute, or @p value is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_isa_get_info( + hsa_isa_t isa, + hsa_isa_info_t attribute, + uint32_t index, + void* value); +#endif + +/** + * @brief Check if the instruction set architecture of a code object can be + * executed on an agent associated with another architecture. + * + * @param[in] code_object_isa Instruction set architecture associated with a + * code object. + * + * @param[in] agent_isa Instruction set architecture associated with an agent. + * + * @param[out] result Pointer to a memory location where the HSA runtime stores + * the result of the check. If the two architectures are compatible, the result + * is true; if they are incompatible, the result is false. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ISA @p code_object_isa or @p agent_isa are + * invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p result is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_isa_compatible( + hsa_isa_t code_object_isa, + hsa_isa_t agent_isa, + bool* result); +#endif + +/** + * @brief An opaque handle to a code object, which contains ISA for finalized + * kernels and indirect functions together with information about the + * global/readonly segment variables they reference. + */ +typedef struct hsa_code_object_s { + /** + * Opaque handle. + */ + uint64_t handle; +} hsa_code_object_t; + +/** + * @brief Opaque handle to application data that is passed to the serialization + * and deserialization functions. + */ +typedef struct hsa_callback_data_s { + /** + * Opaque handle. + */ + uint64_t handle; +} hsa_callback_data_t; + +/** + * @brief Serialize a code object. Can be used for offline finalization, + * install-time finalization, disk code caching, etc. + * + * @param[in] code_object Code object. + * + * @param[in] alloc_callback Callback function for memory allocation. Must not + * be NULL. The HSA runtime passes three arguments to the callback: the + * allocation size, the application data, and a pointer to a memory location + * where the application stores the allocation result. The HSA runtime invokes + * @p alloc_callback once to allocate a buffer that contains the serialized + * version of @p code_object. If the callback returns a status code other than + * ::HSA_STATUS_SUCCESS, this function returns the same code. + * + * @param[in] callback_data Application data that is passed to @p + * alloc_callback. May be NULL. + * + * @param[in] options Vendor-specific options. May be NULL. + * + * @param[out] serialized_code_object Memory location where the HSA runtime + * stores a pointer to the serialized code object. Must not be NULL. + * + * @param[out] serialized_code_object_size Memory location where the HSA runtime + * stores the size (in bytes) of @p serialized_code_object. The returned value + * matches the allocation size passed by the HSA runtime to @p + * alloc_callback. Must not be NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is a failure to allocate + * resources required for the operation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_CODE_OBJECT @p code_object is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p alloc_callback, @p + * serialized_code_object, or @p serialized_code_object_size are NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_code_object_serialize( + hsa_code_object_t code_object, + hsa_status_t (*alloc_callback)(size_t size, hsa_callback_data_t data, void **address), + hsa_callback_data_t callback_data, + const char *options, + void **serialized_code_object, + size_t *serialized_code_object_size); +#endif + +/** + * @brief Deserialize a code object. + * + * @param[in] serialized_code_object A serialized code object. Must not be NULL. + * + * @param[in] serialized_code_object_size The size (in bytes) of @p + * serialized_code_object. Must not be 0. + * + * @param[in] options Vendor-specific options. May be NULL. + * + * @param[out] code_object Memory location where the HSA runtime stores the + * deserialized code object. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is a failure to allocate + * resources required for the operation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p serialized_code_object, or @p + * code_object are NULL. @p serialized_code_object_size is 0. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_code_object_deserialize( + void *serialized_code_object, + size_t serialized_code_object_size, + const char *options, + hsa_code_object_t *code_object); +#endif + +/** + * @brief Destroy a code object. + * + * @details The lifetime of a code object must exceed that of any executable + * where it has been loaded. If an executable that loaded @p code_object has not + * been destroyed, the behavior is undefined. + * + * @param[in] code_object Code object. The handle becomes invalid after it has + * been destroyed. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_CODE_OBJECT @p code_object is invalid. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_code_object_destroy( + hsa_code_object_t code_object); +#endif + +/** + * @brief Code object type. + */ +typedef enum { + /** + * Produces code object that contains ISA for all kernels and indirect + * functions in HSA source. + */ + HSA_CODE_OBJECT_TYPE_PROGRAM = 0 +} hsa_code_object_type_t; + +/** + * @brief Code object attributes. + */ +typedef enum { + /** + * The version of the code object. The type of this attribute is a + * NUL-terminated char[64]. If the version of the code object uses less than + * 63 characters, the rest of the array must be filled with NULs. + */ + HSA_CODE_OBJECT_INFO_VERSION = 0, + /** + * Type of code object. The type of this attribute is + * ::hsa_code_object_type_t. + */ + HSA_CODE_OBJECT_INFO_TYPE = 1, + /** + * Instruction set architecture this code object is produced for. The type of + * this attribute is ::hsa_isa_t. + */ + HSA_CODE_OBJECT_INFO_ISA = 2, + /** + * Machine model this code object is produced for. The type of this attribute + * is ::hsa_machine_model_t. + */ + HSA_CODE_OBJECT_INFO_MACHINE_MODEL = 3, + /** + * Profile this code object is produced for. The type of this attribute is + * ::hsa_profile_t. + */ + HSA_CODE_OBJECT_INFO_PROFILE = 4, + /** + * Default floating-point rounding mode used when the code object is + * produced. The type of this attribute is + * ::hsa_default_float_rounding_mode_t. + */ + HSA_CODE_OBJECT_INFO_DEFAULT_FLOAT_ROUNDING_MODE = 5 +} hsa_code_object_info_t; + +/** + * @brief Get the current value of an attribute for a given code object. + * + * @param[in] code_object Code object. + * + * @param[in] attribute Attribute to query. + * + * @param[out] value Pointer to an application-allocated buffer where to store + * the value of the attribute. If the buffer passed by the application is not + * large enough to hold the value of @p attribute, the behavior is undefined. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p attribute is an invalid + * code object attribute, or @p value is NULL. + * + * @retval ::HSA_STATUS_ERROR_INVALID_CODE_OBJECT @p code_object is invalid. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_code_object_get_info( + hsa_code_object_t code_object, + hsa_code_object_info_t attribute, + void *value); +#endif + +/** + * @brief Code object symbol. + */ +typedef struct hsa_code_symbol_s { + /** + * Opaque handle. + */ + uint64_t handle; +} hsa_code_symbol_t; + +/** + * @brief Get the symbol handle within a code object for a given a symbol name. + * + * @param[in] code_object Code object. + * + * @param[in] symbol_name Symbol name. + * + * @param[out] symbol Memory location where the HSA runtime stores the symbol + * handle. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_CODE_OBJECT @p code_object is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_SYMBOL_NAME There is no symbol with a name + * that matches @p symbol_name. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p symbol_name is NULL, or + * @p symbol is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_code_object_get_symbol( + hsa_code_object_t code_object, + const char *symbol_name, + hsa_code_symbol_t *symbol); +#endif + +/** + * @brief Code object symbol attributes. + */ +typedef enum { + /** + * The type of the symbol. The type of this attribute is ::hsa_symbol_kind_t. + */ + HSA_CODE_SYMBOL_INFO_TYPE = 0, + /** + * The length of the symbol name. The type of this attribute is uint32_t. + */ + HSA_CODE_SYMBOL_INFO_NAME_LENGTH = 1, + /** + * The name of the symbol. The type of this attribute is character array with + * the length equal to the value of ::HSA_CODE_SYMBOL_INFO_NAME_LENGTH + * attribute + */ + HSA_CODE_SYMBOL_INFO_NAME = 2, + /** + * The length of the module name to which this symbol belongs if this symbol + * has module linkage, otherwise 0 is returned. The type of this attribute is + * uint32_t. + */ + HSA_CODE_SYMBOL_INFO_MODULE_NAME_LENGTH = 3, + /** + * The module name to which this symbol belongs if this symbol has module + * linkage, otherwise empty string is returned. The type of this attribute is + * character array with the length equal to the value of + * ::HSA_CODE_SYMBOL_INFO_MODULE_NAME_LENGTH attribute. + */ + HSA_CODE_SYMBOL_INFO_MODULE_NAME = 4, + /** + * The linkage kind of the symbol. The type of this attribute is + * ::hsa_symbol_linkage_t. + */ + HSA_CODE_SYMBOL_INFO_LINKAGE = 5, + /** + * Indicates whether the symbol corresponds to a definition. The type of this + * attribute is bool. + */ + HSA_CODE_SYMBOL_INFO_IS_DEFINITION = 17, + /** + * The allocation kind of the variable. The value of this attribute is + * undefined if the symbol is not a variable. The type of this attribute is + * ::hsa_variable_allocation_t. + */ + HSA_CODE_SYMBOL_INFO_VARIABLE_ALLOCATION = 6, + /** + * The segment kind of the variable. The value of this attribute is + * undefined if the symbol is not a variable. The type of this attribute is + * ::hsa_variable_segment_t. + */ + HSA_CODE_SYMBOL_INFO_VARIABLE_SEGMENT = 7, + /** + * Alignment of the variable. The value of this attribute is undefined if the + * symbol is not a variable. The type of this attribute is uint32_t. + */ + HSA_CODE_SYMBOL_INFO_VARIABLE_ALIGNMENT = 8, + /** + * Size of the variable. The value of this attribute is undefined if the + * symbol is not a variable. The type of this attribute is uint32_t. + * + * A size of 0 is returned if the variable is an external variable and has an + * unknown dimension. + */ + HSA_CODE_SYMBOL_INFO_VARIABLE_SIZE = 9, + /** + * Indicates whether the variable is constant. The value of this attribute is + * undefined if the symbol is not a variable. The type of this attribute is + * bool. + */ + HSA_CODE_SYMBOL_INFO_VARIABLE_IS_CONST = 10, + /** + * Size of kernarg segment memory that is required to hold the values of the + * kernel arguments, in bytes. The value of this attribute is undefined if the + * symbol is not a kernel. The type of this attribute is uint32_t. + */ + HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE = 11, + /** + * Alignment (in bytes) of the buffer used to pass arguments to the kernel, + * which is the maximum of 16 and the maximum alignment of any of the kernel + * arguments. The value of this attribute is undefined if the symbol is not a + * kernel. The type of this attribute is uint32_t. + */ + HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT = 12, + /** + * Size of static group segment memory required by the kernel (per + * work-group), in bytes. The value of this attribute is undefined + * if the symbol is not a kernel. The type of this attribute is uint32_t. + * + * The reported amount does not include any dynamically allocated group + * segment memory that may be requested by the application when a kernel is + * dispatched. + */ + HSA_CODE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE = 13, + /** + * Size of static private, spill, and arg segment memory required by + * this kernel (per work-item), in bytes. The value of this attribute is + * undefined if the symbol is not a kernel. The type of this attribute is + * uint32_t. + * + * If the value of ::HSA_CODE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK is true, + * the kernel may use more private memory than the reported value, and the + * application must add the dynamic call stack usage to @a + * private_segment_size when populating a kernel dispatch packet. + */ + HSA_CODE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE = 14, + /** + * Dynamic callstack flag. The value of this attribute is undefined if the + * symbol is not a kernel. The type of this attribute is bool. + * + * If this flag is set (the value is true), the kernel uses a dynamically + * sized call stack. This can happen if recursive calls, calls to indirect + * functions, or the HSAIL alloca instruction are present in the kernel. + */ + HSA_CODE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK = 15, + /** + * Call convention of the indirect function. The value of this attribute is + * undefined if the symbol is not an indirect function. The type of this + * attribute is uint32_t. + */ + HSA_CODE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION = 16 +} hsa_code_symbol_info_t; + +/** + * @brief Get the current value of an attribute for a given code symbol. + * + * @param[in] code_symbol Code symbol. + * + * @param[in] attribute Attribute to query. + * + * @param[out] value Pointer to an application-allocated buffer where to store + * the value of the attribute. If the buffer passed by the application is not + * large enough to hold the value of @p attribute, the behavior is undefined. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p attribute is an invalid + * code symbol attribute, or @p value is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_code_symbol_get_info( + hsa_code_symbol_t code_symbol, + hsa_code_symbol_info_t attribute, + void *value); +#endif + +/** + * @brief Iterate over the symbols in a code object, and invoke an + * application-defined callback on every iteration. + * + * @param[in] code_object Code object. + * + * @param[in] callback Callback to be invoked once per code object symbol. The + * HSA runtime passes three arguments to the callback: the code object, a + * symbol, and the application data. If @p callback returns a status other than + * ::HSA_STATUS_SUCCESS for a particular iteration, the traversal stops and + * ::hsa_code_object_iterate_symbols returns that status value. + * + * @param[in] data Application data that is passed to @p callback on every + * iteration. May be NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_CODE_OBJECT @p code_object is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p callback is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_code_object_iterate_symbols( + hsa_code_object_t code_object, + hsa_status_t (*callback)(hsa_code_object_t code_object, hsa_code_symbol_t symbol, void* data), + void* data); +#endif + +/** @} */ + +/** \defgroup executable Executable + * @{ + */ + +/** + * @brief An opaque handle to an executable, which contains ISA for finalized + * kernels and indirect functions together with the allocated global/readonly + * segment variables they reference. + */ +typedef struct hsa_executable_s { + /** + * Opaque handle. + */ + uint64_t handle; +} hsa_executable_t; + +/** + * @brief Executable state. + */ +typedef enum { + /** + * Executable state, which allows the user to load code objects and define + * external variables. Variable addresses, kernel code handles, and + * indirect function code handles are not available in query operations until + * the executable is frozen (zero always returned). + */ + HSA_EXECUTABLE_STATE_UNFROZEN = 0, + /** + * Executable state, which allows the user to query variable addresses, + * kernel code handles, and indirect function code handles using query + * operation. Loading new code objects, as well as defining external variables + * is not allowed in this state. + */ + HSA_EXECUTABLE_STATE_FROZEN = 1 +} hsa_executable_state_t; + +/** + * @brief Create an empty executable. + * + * @param[in] profile Profile used in the executable. + * + * @param[in] executable_state Executable state. If the state is + * ::HSA_EXECUTABLE_STATE_FROZEN, the resulting executable is useless because no + * code objects can be loaded, and no variables can be defined. + * + * @param[in] options Vendor-specific options. May be NULL. + * + * @param[out] executable Memory location where the HSA runtime stores newly + * created executable handle. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is a failure to allocate + * resources required for the operation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p profile is invalid, or + * @p executable is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_create( + hsa_profile_t profile, + hsa_executable_state_t executable_state, + const char *options, + hsa_executable_t *executable); +#endif + +/** + * @brief Destroy an executable. + * + * @details Executable handle becomes invalid after the executable has been + * destroyed. Code object handles that were loaded into this executable are + * still valid after the executable has been destroyed, and can be used as + * intended. Resources allocated outside and associated with this executable + * (such as external global/readonly variables) can be released after the + * executable has been destroyed. + * + * Executable should not be destroyed while kernels are in flight. + * + * @param[in] executable Executable. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_EXECUTABLE The executable is invalid. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_destroy( + hsa_executable_t executable); +#endif + +/** + * @brief Load code object into the executable. + * + * @details Every global/readonly variable that is external must be defined + * using define set of operations before loading code objects. Internal + * global/readonly variable is allocated once the code object, that is being + * loaded, references this variable and this variable is not allocated. + * + * Any module linkage declaration must have been defined either by a define + * variable or by loading a code object that has a symbol with module linkage + * definition. + * + * @param[in] executable Executable. + * + * @param[in] agent Agent to load code object for. The agent must support the + * default floating-point rounding mode used by @p code_object. + * + * @param[in] code_object Code object to load. The lifetime of the code object + * must exceed that of the executable: if @p code_object is destroyed before @p + * executable, the behavior is undefined. + * + * @param[in] options Vendor-specific options. May be NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is a failure to allocate + * resources required for the operation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_EXECUTABLE The executable is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_AGENT The agent is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_CODE_OBJECT @p code_object is invalid. + * + * @retval ::HSA_STATUS_ERROR_INCOMPATIBLE_ARGUMENTS @p agent is not compatible + * with @p code_object (for example, @p agent does not support the default + * floating-point rounding mode specified by @p code_object), or @p code_object + * is not compatible with @p executable (for example, @p code_object and @p + * executable have different machine models or profiles). + * + * @retval ::HSA_STATUS_ERROR_FROZEN_EXECUTABLE @p executable is frozen. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_load_code_object( + hsa_executable_t executable, + hsa_agent_t agent, + hsa_code_object_t code_object, + const char *options); +#endif + +/** + * @brief Freeze the executable. + * + * @details No modifications to executable can be made after freezing: no + * code objects can be loaded to the executable, no external variables can + * be defined. Freezing the executable does not prevent querying executable's + * attributes. + * + * @param[in] executable Executable. + * + * @param[in] options Vendor-specific options. May be NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_EXECUTABLE The executable is invalid. + * + * @retval ::HSA_STATUS_ERROR_VARIABLE_UNDEFINED One or more variable is + * undefined in the executable. + * + * @retval ::HSA_STATUS_ERROR_FROZEN_EXECUTABLE @p executable is already frozen. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_freeze( + hsa_executable_t executable, + const char *options); +#endif + +/** + * @brief Executable attributes. + */ +typedef enum { + /** + * Profile this executable is created for. The type of this attribute is + * ::hsa_profile_t. + */ + HSA_EXECUTABLE_INFO_PROFILE = 1, + /** + * Executable state. The type of this attribute is ::hsa_executable_state_t. + */ + HSA_EXECUTABLE_INFO_STATE = 2 +} hsa_executable_info_t; + +/** + * @brief Get the current value of an attribute for a given executable. + * + * @param[in] executable Executable. + * + * @param[in] attribute Attribute to query. + * + * @param[out] value Pointer to an application-allocated buffer where to store + * the value of the attribute. If the buffer passed by the application is not + * large enough to hold the value of @p attribute, the behavior is undefined. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_EXECUTABLE The executable is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p attribute is an invalid + * executable attribute, or @p value is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_get_info( + hsa_executable_t executable, + hsa_executable_info_t attribute, + void *value); +#endif + +/** + * @brief Define an external global variable with program allocation. + * + * @details This function allows the application to provide the definition + * of a variable in the global segment memory with program allocation. The + * variable must be defined before loading a code object into an executable. + * In addition, code objects loaded must not define the variable. + * + * @param[in] executable Executable. + * + * @param[in] variable_name Name of the variable. + * + * @param[in] address Address where the variable is defined. The buffer pointed + * by @p address is owned by the application, and cannot be deallocated before + * @p executable is destroyed. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is a failure to allocate + * resources required for the operation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p variable_name is NULL. + * + * @retval ::HSA_STATUS_ERROR_INVALID_EXECUTABLE The executable is invalid. + * + * @retval ::HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED The variable is + * already defined. + * + * @retval ::HSA_STATUS_ERROR_INVALID_SYMBOL_NAME There is no variable with the + * @p variable_name. + * + * @retval ::HSA_STATUS_ERROR_FROZEN_EXECUTABLE @p executable is frozen. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_global_variable_define( + hsa_executable_t executable, + const char *variable_name, + void *address); +#endif + +/** + * @brief Define an external global variable with agent allocation. + * + * @details This function allows the application to provide the definition + * of a variable in the global segment memory with agent allocation. The + * variable must be defined before loading a code object into an executable. + * In addition, code objects loaded must not define the variable. + * + * @param[in] executable Executable. + * + * @param[in] agent Agent for which the variable is being defined. + * + * @param[in] variable_name Name of the variable. + * + * @param[in] address Address where the variable is defined. The buffer pointed + * by @p address is owned by the application, and cannot be deallocated before + * @p executable is destroyed. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is a failure to allocate + * resources required for the operation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p variable_name is NULL. + * + * @retval ::HSA_STATUS_ERROR_INVALID_EXECUTABLE The executable is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_AGENT @p agent is invalid. + * + * @retval ::HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED The variable is + * already defined. + * + * @retval ::HSA_STATUS_ERROR_INVALID_SYMBOL_NAME There is no variable with the + * @p variable_name. + * + * @retval ::HSA_STATUS_ERROR_FROZEN_EXECUTABLE @p executable is frozen. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_agent_global_variable_define( + hsa_executable_t executable, + hsa_agent_t agent, + const char *variable_name, + void *address); +#endif + +/** + * @brief Define an external readonly variable. + * + * @details This function allows the application to provide the definition + * of a variable in the readonly segment memory. The variable must be defined + * before loading a code object into an executable. In addition, code objects + * loaded must not define the variable. + * + * @param[in] executable Executable. + * + * @param[in] agent Agent for which the variable is being defined. + * + * @param[in] variable_name Name of the variable. + * + * @param[in] address Address where the variable is defined. The buffer pointed + * by @p address is owned by the application, and cannot be deallocated before + * @p executable is destroyed. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_OUT_OF_RESOURCES There is a failure to allocate + * resources required for the operation. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p variable_name is NULL. + * + * @retval ::HSA_STATUS_ERROR_INVALID_EXECUTABLE Executable is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_AGENT @p agent is invalid. + * + * @retval ::HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED The variable is + * already defined. + * + * @retval ::HSA_STATUS_ERROR_INVALID_SYMBOL_NAME There is no variable with the + * @p variable_name. + * + * @retval ::HSA_STATUS_ERROR_FROZEN_EXECUTABLE @p executable is frozen. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_readonly_variable_define( + hsa_executable_t executable, + hsa_agent_t agent, + const char *variable_name, + void *address); +#endif + +/** + * @brief Validate executable. Checks that all code objects have matching + * machine model, profile, and default floating-point rounding mode. Checks that + * all declarations have definitions. Checks declaration-definition + * compatibility (see HSA Programming Reference Manual for compatibility rules). + * + * @param[in] executable Executable. + * + * @param[out] result Memory location where the HSA runtime stores the + * validation result. If the executable is valid, the result is 0. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_EXECUTABLE @p executable is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p result is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_validate( + hsa_executable_t executable, + uint32_t* result); +#endif + +/** + * @brief Executable symbol. + */ +typedef struct hsa_executable_symbol_s { + /** + * Opaque handle. + */ + uint64_t handle; +} hsa_executable_symbol_t; + +/** + * @brief Get the symbol handle for a given a symbol name. + * + * @param[in] executable Executable. + * + * @param[in] module_name Module name. Must be NULL if the symbol has + * program linkage. + * + * @param[in] symbol_name Symbol name. + * + * @param[in] agent Agent associated with the symbol. If the symbol is + * independent of any agent (for example, a variable with program + * allocation), this argument is ignored. + * + * @param[in] call_convention Call convention associated with the symbol. If the + * symbol does not correspond to an indirect function, this argument is ignored. + * + * @param[out] symbol Memory location where the HSA runtime stores the symbol + * handle. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_EXECUTABLE The executable is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_SYMBOL_NAME There is no symbol with a name + * that matches @p symbol_name. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p symbol_name is NULL, or + * @p symbol is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_get_symbol( + hsa_executable_t executable, + const char *module_name, + const char *symbol_name, + hsa_agent_t agent, + int32_t call_convention, + hsa_executable_symbol_t *symbol); +#endif + +/** + * @brief Executable symbol attributes. + */ +typedef enum { + /** + * The kind of the symbol. The type of this attribute is ::hsa_symbol_kind_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_TYPE = 0, + /** + * The length of the symbol name. The type of this attribute is uint32_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_NAME_LENGTH = 1, + /** + * The name of the symbol. The type of this attribute is character array with + * the length equal to the value of ::HSA_EXECUTABLE_SYMBOL_INFO_NAME_LENGTH + * attribute + */ + HSA_EXECUTABLE_SYMBOL_INFO_NAME = 2, + /** + * The length of the module name to which this symbol belongs if this symbol + * has module linkage, otherwise 0 is returned. The type of this attribute is + * uint32_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME_LENGTH = 3, + /** + * The module name to which this symbol belongs if this symbol has module + * linkage, otherwise empty string is returned. The type of this attribute is + * character array with the length equal to the value of + * ::HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME_LENGTH attribute. + */ + HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME = 4, + /** + * Agent associated with this symbol. If the symbol is a variable, the + * value of this attribute is only defined if + * ::HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALLOCATION is + * ::HSA_VARIABLE_ALLOCATION_AGENT. The type of this attribute is hsa_agent_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_AGENT = 20, + /** + * The address of the variable. The value of this attribute is undefined if + * the symbol is not a variable. The type of this attribute is uint64_t. + * + * If executable's state is ::HSA_EXECUTABLE_STATE_UNFROZEN, then 0 is + * returned. + */ + HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ADDRESS = 21, + /** + * The linkage kind of the symbol. The type of this attribute is + * ::hsa_symbol_linkage_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_LINKAGE = 5, + /** + * Indicates whether the symbol corresponds to a definition. The type of this + * attribute is bool. + */ + HSA_EXECUTABLE_SYMBOL_INFO_IS_DEFINITION = 17, + /** + * The allocation kind of the variable. The value of this attribute is + * undefined if the symbol is not a variable. The type of this attribute is + * ::hsa_variable_allocation_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALLOCATION = 6, + /** + * The segment kind of the variable. The value of this attribute is undefined + * if the symbol is not a variable. The type of this attribute is + * ::hsa_variable_segment_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SEGMENT = 7, + /** + * Alignment of the variable. The value of this attribute is undefined if + * the symbol is not a variable. The type of this attribute is uint32_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALIGNMENT = 8, + /** + * Size of the variable. The value of this attribute is undefined if + * the symbol is not a variable. The type of this attribute is uint32_t. + * + * A value of 0 is returned if the variable is an external variable and has an + * unknown dimension. + */ + HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SIZE = 9, + /** + * Indicates whether the variable is constant. The value of this attribute is + * undefined if the symbol is not a variable. The type of this attribute is + * bool. + */ + HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_IS_CONST = 10, + /** + * Kernel object handle, used in the kernel dispatch packet. The value of this + * attribute is undefined if the symbol is not a kernel. The type of this + * attribute is uint64_t. + * + * If the state of the executable is ::HSA_EXECUTABLE_STATE_UNFROZEN, then 0 + * is returned. + */ + HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT = 22, + /** + * Size of kernarg segment memory that is required to hold the values of the + * kernel arguments, in bytes. The value of this attribute is undefined if the + * symbol is not a kernel. The type of this attribute is uint32_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE = 11, + /** + * Alignment (in bytes) of the buffer used to pass arguments to the kernel, + * which is the maximum of 16 and the maximum alignment of any of the kernel + * arguments. The value of this attribute is undefined if the symbol is not a + * kernel. The type of this attribute is uint32_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT = 12, + /** + * Size of static group segment memory required by the kernel (per + * work-group), in bytes. The value of this attribute is undefined + * if the symbol is not a kernel. The type of this attribute is uint32_t. + * + * The reported amount does not include any dynamically allocated group + * segment memory that may be requested by the application when a kernel is + * dispatched. + */ + HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE = 13, + /** + * Size of static private, spill, and arg segment memory required by + * this kernel (per work-item), in bytes. The value of this attribute is + * undefined if the symbol is not a kernel. The type of this attribute is + * uint32_t. + * + * If the value of ::HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK is + * true, the kernel may use more private memory than the reported value, and + * the application must add the dynamic call stack usage to @a + * private_segment_size when populating a kernel dispatch packet. + */ + HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE = 14, + /** + * Dynamic callstack flag. The value of this attribute is undefined if the + * symbol is not a kernel. The type of this attribute is bool. + * + * If this flag is set (the value is true), the kernel uses a dynamically + * sized call stack. This can happen if recursive calls, calls to indirect + * functions, or the HSAIL alloca instruction are present in the kernel. + */ + HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK = 15, + /** + * Indirect function object handle. The value of this attribute is undefined + * if the symbol is not an indirect function, or the associated agent does + * not support the Full Profile. The type of this attribute depends on the + * machine model: if machine model is small, then the type is uint32_t, if + * machine model is large, then the type is uint64_t. + * + * If the state of the executable is ::HSA_EXECUTABLE_STATE_UNFROZEN, then 0 + * is returned. + */ + HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_OBJECT = 23, + /** + * Call convention of the indirect function. The value of this attribute is + * undefined if the symbol is not an indirect function, or the associated + * agent does not support the Full Profile. The type of this attribute is + * uint32_t. + */ + HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION = 16 +} hsa_executable_symbol_info_t; + +/** + * @brief Get the current value of an attribute for a given executable symbol. + * + * @param[in] executable_symbol Executable symbol. + * + * @param[in] attribute Attribute to query. + * + * @param[out] value Pointer to an application-allocated buffer where to store + * the value of the attribute. If the buffer passed by the application is not + * large enough to hold the value of @p attribute, the behavior is undefined. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p attribute is an invalid + * executable symbol attribute, or @p value is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_symbol_get_info( + hsa_executable_symbol_t executable_symbol, + hsa_executable_symbol_info_t attribute, + void *value); +#endif + +/** + * @brief Iterate over the symbols in a executable, and invoke an + * application-defined callback on every iteration. + * + * @param[in] executable Executable. + * + * @param[in] callback Callback to be invoked once per executable symbol. The + * HSA runtime passes three arguments to the callback: the executable, a symbol, + * and the application data. If @p callback returns a status other than + * ::HSA_STATUS_SUCCESS for a particular iteration, the traversal stops and + * ::hsa_executable_iterate_symbols returns that status value. + * + * @param[in] data Application data that is passed to @p callback on every + * iteration. May be NULL. + * + * @retval ::HSA_STATUS_SUCCESS The function has been executed successfully. + * + * @retval ::HSA_STATUS_ERROR_NOT_INITIALIZED The HSA runtime has not been + * initialized. + * + * @retval ::HSA_STATUS_ERROR_INVALID_EXECUTABLE Th executable is invalid. + * + * @retval ::HSA_STATUS_ERROR_INVALID_ARGUMENT @p callback is NULL. + */ +#ifndef DEVICE_COMPILER +hsa_status_t HSA_API hsa_executable_iterate_symbols( + hsa_executable_t executable, + hsa_status_t (*callback)(hsa_executable_t executable, hsa_executable_symbol_t symbol, void* data), + void* data); +#endif + +/** @} */ + +#ifdef __cplusplus +} // end extern "C" block +#endif + +#endif // header guard diff --git a/amd/device-libs/ockl/inc/ockl.h b/amd/device-libs/ockl/inc/ockl.h new file mode 100644 index 0000000000000..b96eaae358bbf --- /dev/null +++ b/amd/device-libs/ockl/inc/ockl.h @@ -0,0 +1,464 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#ifndef OCKL_H +#define OCKL_H + +// This C header declares the functions provided by the OCKL library +// Aspects of this library's behavior can be controlled via the +// oclc library. See the oclc header for further information + +#define OCKL_DEPRECATED __attribute__((deprecated)) + +#define _MANGLE3x(P,N,S) P##_##N##S +#define MANGLE3x(P,N,S) _MANGLE3x(P,N,S) +#define _MANGLE3(P,N,S) P##_##N##_##S +#define MANGLE3(P,N,S) _MANGLE3(P,N,S) +#define OCKL_MANGLE_T(N,T) MANGLE3(__ockl, N, T) +#define OCKL_MANGLE_Tx(N,T) MANGLE3x(__ockl, N, T) +#define OCKL_MANGLE_I32(N) OCKL_MANGLE_T(N, i32) +#define OCKL_MANGLE_U32(N) OCKL_MANGLE_T(N, u32) +#define OCKL_MANGLE_F32(N) OCKL_MANGLE_T(N, f32) +#define OCKL_MANGLE_F16(N) OCKL_MANGLE_T(N, f16) +#define OCKL_MANGLE_I64(N) OCKL_MANGLE_T(N, i64) +#define OCKL_MANGLE_U64(N) OCKL_MANGLE_T(N, u64) + +#define DECL_OCKL_NULLARY_U32(N) extern uint OCKL_MANGLE_U32(N)(void); +#define _DECL_X_OCKL_NULLARY_U32(A,N) extern __attribute__((A)) uint OCKL_MANGLE_U32(N)(void); +#define DECL_PURE_OCKL_NULLARY_U32(N) _DECL_X_OCKL_NULLARY_U32(pure, N) +#define DECL_CONST_OCKL_NULLARY_U32(N) _DECL_X_OCKL_NULLARY_U32(const, N) + +#define DECL_OCKL_NULLARY_U64(N) extern ulong OCKL_MANGLE_U64(N)(void); +#define _DECL_X_OCKL_NULLARY_U64(A,N) extern __attribute__((A)) ulong OCKL_MANGLE_U64(N)(void); +#define DECL_PURE_OCKL_NULLARY_U64(N) _DECL_X_OCKL_NULLARY_U64(pure, N) +#define DECL_CONST_OCKL_NULLARY_U64(N) _DECL_X_OCKL_NULLARY_U64(const, N) + +#define DECL_OCKL_UNARY_I32(N) extern int OCKL_MANGLE_I32(N)(int); +#define _DECL_X_OCKL_UNARY_I32(A,N) extern __attribute__((A)) int OCKL_MANGLE_I32(N)(int); +#define DECL_PURE_OCKL_UNARY_I32(N) _DECL_X_OCKL_UNARY_I32(pure, N) +#define DECL_CONST_OCKL_UNARY_I32(N) _DECL_X_OCKL_UNARY_I32(const, N) + +#define DECL_OCKL_UNARY_I64(N) extern long OCKL_MANGLE_I64(N)(long); +#define _DECL_X_OCKL_UNARY_I64(A,N) extern __attribute__((A)) long OCKL_MANGLE_I64(N)(long); +#define DECL_PURE_OCKL_UNARY_I64(N) _DECL_X_OCKL_UNARY_I64(pure, N) +#define DECL_CONST_OCKL_UNARY_I64(N) _DECL_X_OCKL_UNARY_I64(const, N) + +#define DECL_OCKL_UNARY_U32(N) extern uint OCKL_MANGLE_U32(N)(uint); +#define _DECL_X_OCKL_UNARY_U32(A,N) extern __attribute__((A)) uint OCKL_MANGLE_U32(N)(uint); +#define DECL_PURE_OCKL_UNARY_U32(N) _DECL_X_OCKL_UNARY_U32(pure, N) +#define DECL_CONST_OCKL_UNARY_U32(N) _DECL_X_OCKL_UNARY_U32(const, N) + +#define DECL_OCKL_UNARY_U64(N) extern ulong OCKL_MANGLE_U64(N)(ulong); +#define _DECL_X_OCKL_UNARY_U64(A,N) extern __attribute__((A)) ulong OCKL_MANGLE_U64(N)(ulong); +#define DECL_PURE_OCKL_UNARY_U64(N) _DECL_X_OCKL_UNARY_U64(pure, N) +#define DECL_CONST_OCKL_UNARY_U64(N) _DECL_X_OCKL_UNARY_U64(const, N) + +#define DECL_OCKL_BINARY_I32(N) extern int OCKL_MANGLE_I32(N)(int,int); +#define _DECL_X_OCKL_BINARY_I32(A,N) extern __attribute__((A)) int OCKL_MANGLE_I32(N)(int,int); +#define DECL_PURE_OCKL_BINARY_I32(N) _DECL_X_OCKL_BINARY_I32(pure, N) +#define DECL_CONST_OCKL_BINARY_I32(N) _DECL_X_OCKL_BINARY_I32(const, N) + +#define DECL_OCKL_BINARY_I64(N) extern long OCKL_MANGLE_I64(N)(long,long); +#define _DECL_X_OCKL_BINARY_I64(A,N) extern __attribute__((A)) long OCKL_MANGLE_I64(N)(long,long); +#define DECL_PURE_OCKL_BINARY_I64(N) _DECL_X_OCKL_BINARY_I64(pure, N) +#define DECL_CONST_OCKL_BINARY_I64(N) _DECL_X_OCKL_BINARY_I64(const, N) + +#define DECL_OCKL_BINARY_U32(N) extern uint OCKL_MANGLE_U32(N)(uint,uint); +#define _DECL_X_OCKL_BINARY_U32(A,N) extern __attribute__((A)) uint OCKL_MANGLE_U32(N)(uint,uint); +#define DECL_PURE_OCKL_BINARY_U32(N) _DECL_X_OCKL_BINARY_U32(pure, N) +#define DECL_CONST_OCKL_BINARY_U32(N) _DECL_X_OCKL_BINARY_U32(const, N) + +#define DECL_OCKL_BINARY_U64(N) extern ulong OCKL_MANGLE_U64(N)(ulong,ulong); +#define _DECL_X_OCKL_BINARY_U64(A,N) extern __attribute__((A)) ulong OCKL_MANGLE_U64(N)(ulong,ulong); +#define DECL_PURE_OCKL_BINARY_U64(N) _DECL_X_OCKL_BINARY_U64(pure, N) +#define DECL_CONST_OCKL_BINARY_U64(N) _DECL_X_OCKL_BINARY_U64(const, N) + +#define DECL_OCKL_TERNARY_I32(N) extern int OCKL_MANGLE_I32(N)(int,int,int); +#define _DECL_X_OCKL_TERNARY_I32(A,N) extern __attribute__((A)) int OCKL_MANGLE_I32(N)(int,int,int); +#define DECL_PURE_OCKL_TERNARY_I32(N) _DECL_X_OCKL_TERNARY_I32(pure, N) +#define DECL_CONST_OCKL_TERNARY_I32(N) _DECL_X_OCKL_TERNARY_I32(const, N) + +#define DECL_OCKL_TERNARY_F32(N) extern float OCKL_MANGLE_F32(N)(float,float,float); +#define _DECL_X_OCKL_TERNARY_F32(A,N) extern __attribute__((A)) float OCKL_MANGLE_F32(N)(float,float,float); +#define DECL_PURE_OCKL_TERNARY_F32(N) _DECL_X_OCKL_TERNARY_F32(pure, N) +#define DECL_CONST_OCKL_TERNARY_F32(N) _DECL_X_OCKL_TERNARY_F32(const, N) + +#define DECL_OCKL_TERNARY_F16(N) extern half OCKL_MANGLE_F16(N)(half,half,half); +#define _DECL_X_OCKL_TERNARY_F16(A,N) extern __attribute__((A)) half OCKL_MANGLE_F16(N)(half,half,half); +#define DECL_PURE_OCKL_TERNARY_F16(N) _DECL_X_OCKL_TERNARY_F16(pure, N) +#define DECL_CONST_OCKL_TERNARY_F16(N) _DECL_X_OCKL_TERNARY_F16(const, N) + +#define DECL_OCKL_TERNARY_I64(N) extern long OCKL_MANGLE_I64(N)(long,long,long); +#define _DECL_X_OCKL_TERNARY_I64(A,N) extern __attribute__((A)) long OCKL_MANGLE_I64(N)(long,long,long); +#define DECL_PURE_OCKL_TERNARY_I64(N) _DECL_X_OCKL_TERNARY_I64(pure, N) +#define DECL_CONST_OCKL_TERNARY_I64(N) _DECL_X_OCKL_TERNARY_I64(const, N) + +#define DECL_OCKL_TERNARY_U32(N) extern uint OCKL_MANGLE_U32(N)(uint,uint,uint); +#define _DECL_X_OCKL_TERNARY_U32(A,N) extern __attribute__((A)) uint OCKL_MANGLE_U32(N)(uint,uint,uint); +#define DECL_PURE_OCKL_TERNARY_U32(N) _DECL_X_OCKL_TERNARY_U32(pure, N) +#define DECL_CONST_OCKL_TERNARY_U32(N) _DECL_X_OCKL_TERNARY_U32(const, N) + +#define DECL_OCKL_TERNARY_U64(N) extern ulong OCKL_MANGLE_U64(N)(ulong,ulong,ulong); +#define _DECL_X_OCKL_TERNARY_U64(A,N) extern __attribute__((A)) ulong OCKL_MANGLE_U64(N)(ulong,ulong,ulong); +#define DECL_PURE_OCKL_TERNARY_U64(N) _DECL_X_OCKL_TERNARY_U64(pure, N) +#define DECL_CONST_OCKL_TERNARY_U64(N) _DECL_X_OCKL_TERNARY_U64(const, N) + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +extern __attribute__((const)) uchar OCKL_MANGLE_T(clz,u8)(uchar); +extern __attribute__((const)) ushort OCKL_MANGLE_T(clz,u16)(ushort); +DECL_CONST_OCKL_UNARY_U32(clz) +DECL_CONST_OCKL_UNARY_U64(clz) + +extern __attribute__((const)) uchar OCKL_MANGLE_T(ctz,u8)(uchar); +extern __attribute__((const)) ushort OCKL_MANGLE_T(ctz,u16)(ushort); +DECL_CONST_OCKL_UNARY_U32(ctz) +DECL_CONST_OCKL_UNARY_U64(ctz) + +DECL_CONST_OCKL_UNARY_U32(popcount) +DECL_CONST_OCKL_UNARY_U64(popcount) + +DECL_CONST_OCKL_BINARY_I32(add_sat) +DECL_CONST_OCKL_BINARY_U32(add_sat) +DECL_CONST_OCKL_BINARY_I64(add_sat) +DECL_CONST_OCKL_BINARY_U64(add_sat) + +DECL_CONST_OCKL_BINARY_I32(sub_sat) +DECL_CONST_OCKL_BINARY_U32(sub_sat) +DECL_CONST_OCKL_BINARY_I64(sub_sat) +DECL_CONST_OCKL_BINARY_U64(sub_sat) + +DECL_CONST_OCKL_BINARY_I32(mul_hi) +DECL_CONST_OCKL_BINARY_U32(mul_hi) +DECL_CONST_OCKL_BINARY_I64(mul_hi) +DECL_CONST_OCKL_BINARY_U64(mul_hi) + +DECL_CONST_OCKL_BINARY_I32(mul24) +DECL_CONST_OCKL_BINARY_U32(mul24) + +DECL_OCKL_NULLARY_U32(lane) +DECL_OCKL_NULLARY_U32(activelane) + +DECL_OCKL_NULLARY_U64(cyclectr) +DECL_OCKL_NULLARY_U64(steadyctr) + + +extern half OCKL_MANGLE_T(wfred_add,f16)(half x); +extern float OCKL_MANGLE_T(wfred_add,f32)(float x); +extern double OCKL_MANGLE_T(wfred_add,f64)(double x); +extern int OCKL_MANGLE_T(wfred_add,i32)(int x); +extern long OCKL_MANGLE_T(wfred_add,i64)(long x); +extern uint OCKL_MANGLE_T(wfred_add,u32)(uint x); +extern ulong OCKL_MANGLE_T(wfred_add,u64)(ulong x); +extern int OCKL_MANGLE_T(wfred_and,i32)(int x); +extern long OCKL_MANGLE_T(wfred_and,i64)(long x); +extern uint OCKL_MANGLE_T(wfred_and,u32)(uint x); +extern ulong OCKL_MANGLE_T(wfred_and,u64)(ulong x); +extern half OCKL_MANGLE_T(wfred_max,f16)(half x); +extern float OCKL_MANGLE_T(wfred_max,f32)(float x); +extern double OCKL_MANGLE_T(wfred_max,f64)(double x); +extern int OCKL_MANGLE_T(wfred_max,i32)(int x); +extern long OCKL_MANGLE_T(wfred_max,i64)(long x); +extern uint OCKL_MANGLE_T(wfred_max,u32)(uint x); +extern ulong OCKL_MANGLE_T(wfred_max,u64)(ulong x); +extern half OCKL_MANGLE_T(wfred_min,f16)(half x); +extern float OCKL_MANGLE_T(wfred_min,f32)(float x); +extern double OCKL_MANGLE_T(wfred_min,f64)(double x); +extern int OCKL_MANGLE_T(wfred_min,i32)(int x); +extern long OCKL_MANGLE_T(wfred_min,i64)(long x); +extern uint OCKL_MANGLE_T(wfred_min,u32)(uint x); +extern ulong OCKL_MANGLE_T(wfred_min,u64)(ulong x); +extern int OCKL_MANGLE_T(wfred_or,i32)(int x); +extern long OCKL_MANGLE_T(wfred_or,i64)(long x); +extern uint OCKL_MANGLE_T(wfred_or,u32)(uint x); +extern ulong OCKL_MANGLE_T(wfred_or,u64)(ulong x); +extern int OCKL_MANGLE_T(wfred_xor,i32)(int x); +extern long OCKL_MANGLE_T(wfred_xor,i64)(long x); +extern uint OCKL_MANGLE_T(wfred_xor,u32)(uint x); +extern ulong OCKL_MANGLE_T(wfred_xor,u64)(ulong x); +extern half OCKL_MANGLE_T(wfscan_add,f16)(half x, bool inclusive); +extern float OCKL_MANGLE_T(wfscan_add,f32)(float x, bool inclusive); +extern double OCKL_MANGLE_T(wfscan_add,f64)(double x, bool inclusive); +extern int OCKL_MANGLE_T(wfscan_add,i32)(int x, bool inclusive); +extern long OCKL_MANGLE_T(wfscan_add,i64)(long x, bool inclusive); +extern uint OCKL_MANGLE_T(wfscan_add,u32)(uint x, bool inclusive); +extern ulong OCKL_MANGLE_T(wfscan_add,u64)(ulong x, bool inclusive); +extern int OCKL_MANGLE_T(wfscan_and,i32)(int x, bool inclusive); +extern long OCKL_MANGLE_T(wfscan_and,i64)(long x, bool inclusive); +extern uint OCKL_MANGLE_T(wfscan_and,u32)(uint x, bool inclusive); +extern ulong OCKL_MANGLE_T(wfscan_and,u64)(ulong x, bool inclusive); +extern half OCKL_MANGLE_T(wfscan_max,f16)(half x, bool inclusive); +extern float OCKL_MANGLE_T(wfscan_max,f32)(float x, bool inclusive); +extern double OCKL_MANGLE_T(wfscan_max,f64)(double x, bool inclusive); +extern int OCKL_MANGLE_T(wfscan_max,i32)(int x, bool inclusive); +extern long OCKL_MANGLE_T(wfscan_max,i64)(long x, bool inclusive); +extern uint OCKL_MANGLE_T(wfscan_max,u32)(uint x, bool inclusive); +extern ulong OCKL_MANGLE_T(wfscan_max,u64)(ulong x, bool inclusive); +extern half OCKL_MANGLE_T(wfscan_min,f16)(half x, bool inclusive); +extern float OCKL_MANGLE_T(wfscan_min,f32)(float x, bool inclusive); +extern double OCKL_MANGLE_T(wfscan_min,f64)(double x, bool inclusive); +extern int OCKL_MANGLE_T(wfscan_min,i32)(int x, bool inclusive); +extern long OCKL_MANGLE_T(wfscan_min,i64)(long x, bool inclusive); +extern uint OCKL_MANGLE_T(wfscan_min,u32)(uint x, bool inclusive); +extern ulong OCKL_MANGLE_T(wfscan_min,u64)(ulong x, bool inclusive); +extern int OCKL_MANGLE_T(wfscan_or,i32)(int x, bool inclusive); +extern long OCKL_MANGLE_T(wfscan_or,i64)(long x, bool inclusive); +extern uint OCKL_MANGLE_T(wfscan_or,u32)(uint x, bool inclusive); +extern ulong OCKL_MANGLE_T(wfscan_or,u64)(ulong x, bool inclusive); +extern int OCKL_MANGLE_T(wfscan_xor,i32)(int x, bool inclusive); +extern long OCKL_MANGLE_T(wfscan_xor,i64)(long x, bool inclusive); +extern uint OCKL_MANGLE_T(wfscan_xor,u32)(uint x, bool inclusive); +extern ulong OCKL_MANGLE_T(wfscan_xor,u64)(ulong x, bool inclusive); +extern uint OCKL_MANGLE_U32(wfbcast)(uint x, uint i); +extern ulong OCKL_MANGLE_U64(wfbcast)(ulong x, uint i); + +extern bool OCKL_MANGLE_I32(wfany)(int e); +extern bool OCKL_MANGLE_I32(wfall)(int e); +extern bool OCKL_MANGLE_I32(wfsame)(int e); + +DECL_CONST_OCKL_BINARY_U32(bfm) +extern __attribute__((const)) int OCKL_MANGLE_I32(bfe)(int, uint, uint); +DECL_CONST_OCKL_TERNARY_U32(bfe) +DECL_CONST_OCKL_TERNARY_U32(bitalign) +DECL_CONST_OCKL_TERNARY_U32(bytealign) +DECL_CONST_OCKL_TERNARY_U32(lerp) +DECL_CONST_OCKL_TERNARY_F32(max3) +DECL_CONST_OCKL_TERNARY_F32(median3) +DECL_CONST_OCKL_TERNARY_F32(min3) +DECL_CONST_OCKL_TERNARY_F16(max3) +DECL_CONST_OCKL_TERNARY_F16(median3) +DECL_CONST_OCKL_TERNARY_F16(min3) +DECL_CONST_OCKL_TERNARY_I32(max3) +DECL_CONST_OCKL_TERNARY_I32(median3) +DECL_CONST_OCKL_TERNARY_I32(min3) +DECL_CONST_OCKL_TERNARY_U32(max3) +DECL_CONST_OCKL_TERNARY_U32(median3) +DECL_CONST_OCKL_TERNARY_U32(min3) +extern __attribute__((const)) ulong OCKL_MANGLE_U64(mqsad)(ulong, uint, ulong); +extern __attribute__((const)) uint OCKL_MANGLE_U32(pack)(float4); +extern __attribute__((const)) ulong OCKL_MANGLE_U64(qsad)(ulong, uint, ulong); +DECL_CONST_OCKL_TERNARY_U32(msad) +DECL_CONST_OCKL_TERNARY_U32(sad) +DECL_CONST_OCKL_TERNARY_U32(sadd) +DECL_CONST_OCKL_TERNARY_U32(sadhi) +DECL_CONST_OCKL_TERNARY_U32(sadw) +extern __attribute__((const)) float OCKL_MANGLE_F32(unpack0)(uint); +extern __attribute__((const)) float OCKL_MANGLE_F32(unpack1)(uint); +extern __attribute__((const)) float OCKL_MANGLE_F32(unpack2)(uint); +extern __attribute__((const)) float OCKL_MANGLE_F32(unpack3)(uint); + + +#define SSHARP __constant uint * +#define TSHARP __constant uint * + +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load,1D)(TSHARP i, int c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load,1Da)(TSHARP i, int2 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load,1Db)(TSHARP i, int c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load,2D)(TSHARP i, int2 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load,2Da)(TSHARP i, int4 c); +extern __attribute__((pure)) float OCKL_MANGLE_T(image_load,2Dad)(TSHARP i, int4 c); +extern __attribute__((pure)) float OCKL_MANGLE_T(image_load,2Dd)(TSHARP i, int2 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load,3D)(TSHARP i, int4 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load,CM)(TSHARP i, int2 c, int f); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load,CMa)(TSHARP i, int4 c, int f); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load_mip,1D)(TSHARP i, int c, int l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load_mip,1Da)(TSHARP i, int2 c, int l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load_mip,2D)(TSHARP i, int2 c, int l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load_mip,2Da)(TSHARP i, int4 c, int l); +extern __attribute__((pure)) float OCKL_MANGLE_T(image_load_mip,2Dad)(TSHARP i, int4 c, int l); +extern __attribute__((pure)) float OCKL_MANGLE_T(image_load_mip,2Dd)(TSHARP i, int2 c, int l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load_mip,3D)(TSHARP i, int4 c, int l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load_mip,CM)(TSHARP i, int2 c, int f, int l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_load_mip,CMa)(TSHARP i, int4 c, int f, int l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh,1D)(TSHARP i, int c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh,1Da)(TSHARP i, int2 c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh,1Db)(TSHARP i, int c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh,2D)(TSHARP i, int2 c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh,2Da)(TSHARP i, int4 c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh,3D)(TSHARP i, int4 c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh,CM)(TSHARP i, int2 c, int f); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh,CMa)(TSHARP i, int4 c, int f); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh_mip,1D)(TSHARP i, int c, int l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh_mip,1Da)(TSHARP i, int2 c, int l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh_mip,2D)(TSHARP i, int2 c, int l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh_mip,2Da)(TSHARP i, int4 c, int l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh_mip,3D)(TSHARP i, int4 c, int l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh_mip,CM)(TSHARP i, int2 c, int f, int l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_loadh_mip,CMa)(TSHARP i, int4 c, int f, int l); + +extern void OCKL_MANGLE_T(image_store,1D)(TSHARP i, int c, float4 p); +extern void OCKL_MANGLE_T(image_store,1Da)(TSHARP i, int2 c, float4 p); +extern void OCKL_MANGLE_T(image_store,1Db)(TSHARP i, int c, float4 p); +extern void OCKL_MANGLE_T(image_store,2D)(TSHARP i, int2 c, float4 p); +extern void OCKL_MANGLE_T(image_store,2Da)(TSHARP i, int4 c, float4 p); +extern void OCKL_MANGLE_T(image_store,2Dad)(TSHARP i, int4 c, float p); +extern void OCKL_MANGLE_T(image_store,2Dd)(TSHARP i, int2 c, float p); +extern void OCKL_MANGLE_T(image_store,3D)(TSHARP i, int4 c, float4 p); +extern void OCKL_MANGLE_T(image_store,CM)(TSHARP i, int2 c, int f, float4 p); +extern void OCKL_MANGLE_T(image_store,CMa)(TSHARP i, int4 c, int f, float4 p); +extern void OCKL_MANGLE_T(image_store_lod,1D)(TSHARP i, int c, int l, float4 p); +extern void OCKL_MANGLE_T(image_store_lod,1Da)(TSHARP i, int2 c, int l, float4 p); +extern void OCKL_MANGLE_T(image_store_lod,2D)(TSHARP i, int2 c, int l, float4 p); +extern void OCKL_MANGLE_T(image_store_lod,2Da)(TSHARP i, int4 c, int l, float4 p); +extern void OCKL_MANGLE_T(image_store_lod,2Dad)(TSHARP i, int4 c, int l, float p); +extern void OCKL_MANGLE_T(image_store_lod,2Dd)(TSHARP i, int2 c, int l, float p); +extern void OCKL_MANGLE_T(image_store_lod,3D)(TSHARP i, int4 c, int l, float4 p); +extern void OCKL_MANGLE_T(image_store_lod,CM)(TSHARP i, int2 c, int f, int l, float4 p); +extern void OCKL_MANGLE_T(image_store_lod,CMa)(TSHARP i, int4 c, int f, int l, float4 p); +extern void OCKL_MANGLE_T(image_storeh,1D)(TSHARP i, int c, half4 p); +extern void OCKL_MANGLE_T(image_storeh,1Da)(TSHARP i, int2 c, half4 p); +extern void OCKL_MANGLE_T(image_storeh,1Db)(TSHARP i, int c, half4 p); +extern void OCKL_MANGLE_T(image_storeh,2D)(TSHARP i, int2 c, half4 p); +extern void OCKL_MANGLE_T(image_storeh,2Da)(TSHARP i, int4 c, half4 p); +extern void OCKL_MANGLE_T(image_storeh,3D)(TSHARP i, int4 c, half4 p); +extern void OCKL_MANGLE_T(image_storeh,CM)(TSHARP i, int2 c, int f, half4 p); +extern void OCKL_MANGLE_T(image_storeh,CMa)(TSHARP i, int4 c, int f, half4 p); +extern void OCKL_MANGLE_T(image_storeh_lod,1D)(TSHARP i, int c, int l, half4 p); +extern void OCKL_MANGLE_T(image_storeh_lod,1Da)(TSHARP i, int2 c, int l, half4 p); +extern void OCKL_MANGLE_T(image_storeh_lod,2D)(TSHARP i, int2 c, int l, half4 p); +extern void OCKL_MANGLE_T(image_storeh_lod,2Da)(TSHARP i, int4 c, int l, half4 p); +extern void OCKL_MANGLE_T(image_storeh_lod,3D)(TSHARP i, int4 c, int l, half4 p); +extern void OCKL_MANGLE_T(image_storeh_lod,CM)(TSHARP i, int2 c, int f, int l, half4 p); +extern void OCKL_MANGLE_T(image_storeh_lod,CMa)(TSHARP i, int4 c, int f, int l, half4 p); + +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample,1D)(TSHARP i, SSHARP s, float c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample,1Da)(TSHARP i, SSHARP s, float2 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample,2D)(TSHARP i, SSHARP s, float2 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample,2Da)(TSHARP i, SSHARP s, float4 c); +extern __attribute__((pure)) float OCKL_MANGLE_T(image_sample,2Dad)(TSHARP i, SSHARP s, float4 c); +extern __attribute__((pure)) float OCKL_MANGLE_T(image_sample,2Dd)(TSHARP i, SSHARP s, float2 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample,3D)(TSHARP i, SSHARP s, float4 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample,CM)(TSHARP i, SSHARP s, float4 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample,CMa)(TSHARP i, SSHARP s, float4 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_grad,1D)(TSHARP i, SSHARP s, float c, float dx, float dy); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_grad,1Da)(TSHARP i, SSHARP s, float2 c, float dx, float dy); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_grad,2D)(TSHARP i, SSHARP s, float2 c, float2 dx, float2 dy); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_grad,2Da)(TSHARP i, SSHARP s, float4 c, float2 dx, float2 dy); +extern __attribute__((pure)) float OCKL_MANGLE_T(image_sample_grad,2Dad)(TSHARP i, SSHARP s, float4 c, float2 dx, float2 dy); +extern __attribute__((pure)) float OCKL_MANGLE_T(image_sample_grad,2Dd)(TSHARP i, SSHARP s, float2 c, float2 dx, float2 dy); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_grad,3D)(TSHARP i, SSHARP s, float4 c, float4 dx, float4 dy); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_lod,1D)(TSHARP i, SSHARP s, float c, float l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_lod,1Da)(TSHARP i, SSHARP s, float2 c, float l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_lod,2D)(TSHARP i, SSHARP s, float2 c, float l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_lod,2Da)(TSHARP i, SSHARP s, float4 c, float l); +extern __attribute__((pure)) float OCKL_MANGLE_T(image_sample_lod,2Dad)(TSHARP i, SSHARP s, float4 c, float l); +extern __attribute__((pure)) float OCKL_MANGLE_T(image_sample_lod,2Dd)(TSHARP i, SSHARP s, float2 c, float l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_lod,3D)(TSHARP i, SSHARP s, float4 c, float l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_lod,CM)(TSHARP i, SSHARP s, float4 c, float l); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_sample_lod,CMa)(TSHARP i, SSHARP s, float4 c, float l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh,1D)(TSHARP i, SSHARP s, float c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh,1Da)(TSHARP i, SSHARP s, float2 c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh,2D)(TSHARP i, SSHARP s, float2 c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh,2Da)(TSHARP i, SSHARP s, float4 c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh,3D)(TSHARP i, SSHARP s, float4 c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh,CM)(TSHARP i, SSHARP s, float4 c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh,CMa)(TSHARP i, SSHARP s, float4 c); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_grad,1D)(TSHARP i, SSHARP s, float c, float dx, float dy); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_grad,1Da)(TSHARP i, SSHARP s, float2 c, float dx, float dy); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_grad,2D)(TSHARP i, SSHARP s, float2 c, float2 dx, float2 dy); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_grad,2Da)(TSHARP i, SSHARP s, float4 c, float2 dx, float2 dy); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_grad,3D)(TSHARP i, SSHARP s, float4 c, float4 dx, float4 dy); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_lod,1D)(TSHARP i, SSHARP s, float c, float l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_lod,1Da)(TSHARP i, SSHARP s, float2 c, float l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_lod,2D)(TSHARP i, SSHARP s, float2 c, float l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_lod,2Da)(TSHARP i, SSHARP s, float4 c, float l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_lod,3D)(TSHARP i, SSHARP s, float4 c, float l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_lod,CM)(TSHARP i, SSHARP s, float4 c, float l); +extern __attribute__((pure)) half4 OCKL_MANGLE_T(image_sampleh_lod,CMa)(TSHARP i, SSHARP s, float4 c, float l); + +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_gather4r,2D)(TSHARP i, SSHARP s, float2 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_gather4g,2D)(TSHARP i, SSHARP s, float2 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_gather4b,2D)(TSHARP i, SSHARP s, float2 c); +extern __attribute__((pure)) float4 OCKL_MANGLE_T(image_gather4a,2D)(TSHARP i, SSHARP s, float2 c); + +extern __attribute__((const)) int OCKL_MANGLE_T(image_array_size,1Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_array_size,2Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_array_size,2Dad)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_array_size,CMa)(TSHARP i); + +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_data_type,1D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_data_type,1Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_data_type,1Db)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_data_type,2D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_data_type,2Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_data_type,2Dad)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_data_type,2Dd)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_data_type,3D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_data_type,CM)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_data_type,CMa)(TSHARP i); + +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_order,1D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_order,1Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_order,1Db)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_order,2D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_order,2Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_order,2Dad)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_order,2Dd)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_order,3D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_order,CM)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_channel_order,CMa)(TSHARP i); + +extern __attribute__((const)) int OCKL_MANGLE_T(image_depth,3D)(TSHARP i); + +extern __attribute__((const)) int OCKL_MANGLE_T(image_height,2D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_height,2Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_height,2Dad)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_height,2Dd)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_height,3D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_height,CM)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_height,CMa)(TSHARP i); + +extern __attribute__((const)) int OCKL_MANGLE_T(image_num_mip_levels,1D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_num_mip_levels,1Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_num_mip_levels,2D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_num_mip_levels,2Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_num_mip_levels,2Dad)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_num_mip_levels,2Dd)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_num_mip_levels,3D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_num_mip_levels,CM)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_num_mip_levels,CMa)(TSHARP i); + +extern __attribute__((const)) int OCKL_MANGLE_T(image_width,1D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_width,1Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_width,1Db)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_width,2D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_width,2Da)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_width,2Dad)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_width,2Dd)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_width,3D)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_width,CM)(TSHARP i); +extern __attribute__((const)) int OCKL_MANGLE_T(image_width,CMa)(TSHARP i); + +extern __attribute__((const)) size_t __ockl_get_global_offset(uint); +extern __attribute__((const)) size_t __ockl_get_global_id(uint); +extern __attribute__((const)) size_t __ockl_get_local_id(uint); +extern __attribute__((const)) size_t __ockl_get_group_id(uint); +extern __attribute__((const)) size_t __ockl_get_global_size(uint); +extern __attribute__((const)) size_t __ockl_get_local_size(uint); +extern __attribute__((const)) size_t __ockl_get_num_groups(uint); +extern __attribute__((const)) uint __ockl_get_work_dim(void); +extern __attribute__((const)) size_t __ockl_get_enqueued_local_size(uint); +extern __attribute__((const)) size_t __ockl_get_global_linear_id(void); +extern __attribute__((const)) size_t __ockl_get_local_linear_id(void); +extern __attribute__((const)) int __ockl_readuplane_i32(int, int); +extern __attribute__((const)) long __ockl_readuplane_i64(long, int); + +extern __attribute__((const)) bool OCKL_MANGLE_T(is_local,addr)(const void *); +extern __attribute__((const)) bool OCKL_MANGLE_T(is_private,addr)(const void *); +extern __attribute__((const)) __global void * OCKL_MANGLE_T(to,global)(void *); +extern __attribute__((const)) __local void * OCKL_MANGLE_T(to,local)(void *); +extern __attribute__((const)) __private void * OCKL_MANGLE_T(to,private)(void *); + +extern void OCKL_MANGLE_T(rtcwait,u32)(uint); +extern void __ockl_sanitizer_report(ulong, ulong, ulong, ulong, ulong, ulong, ulong, ulong); + +extern uint OCKL_MANGLE_U32(alisa)(uint); + +#pragma OPENCL EXTENSION cl_khr_fp16 : disable + +#endif // OCKL_H + diff --git a/amd/device-libs/ockl/inc/ockl_hsa.h b/amd/device-libs/ockl/inc/ockl_hsa.h new file mode 100644 index 0000000000000..ab97077eb11aa --- /dev/null +++ b/amd/device-libs/ockl/inc/ockl_hsa.h @@ -0,0 +1,39 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#ifndef OCKL_HSA_H +#define OCKL_HSA_H + +#include "ockl.h" +#include "device_amd_hsa.h" + +typedef enum __ockl_memory_order_e { + __ockl_memory_order_relaxed = __ATOMIC_RELAXED, + __ockl_memory_order_acquire = __ATOMIC_ACQUIRE, + __ockl_memory_order_release = __ATOMIC_RELEASE, + __ockl_memory_order_acq_rel = __ATOMIC_ACQ_REL, + __ockl_memory_order_seq_cst = __ATOMIC_SEQ_CST, +} __ockl_memory_order; + +extern ulong OCKL_MANGLE_T(hsa_queue,load_read_index)(const __global hsa_queue_t *queue, __ockl_memory_order mem_order); + +extern ulong OCKL_MANGLE_T(hsa_queue,load_write_index)(const __global hsa_queue_t *queue, __ockl_memory_order mem_order); +extern ulong OCKL_MANGLE_T(hsa_queue,add_write_index)(__global hsa_queue_t *queue, ulong value, __ockl_memory_order mem_order); +extern ulong OCKL_MANGLE_T(hsa_queue,cas_write_index)(__global hsa_queue_t *queue, ulong expected, ulong value, __ockl_memory_order mem_order); +extern void OCKL_MANGLE_T(hsa_queue,store_write_index)(__global hsa_queue_t *queue, ulong value, __ockl_memory_order mem_order); + +extern long OCKL_MANGLE_T(hsa_signal,load)(const hsa_signal_t sig, __ockl_memory_order mem_order); +extern void OCKL_MANGLE_T(hsa_signal,add)(hsa_signal_t sig, long value, __ockl_memory_order mem_order); +extern void OCKL_MANGLE_T(hsa_signal,and)(hsa_signal_t sig, long value, __ockl_memory_order mem_order); +extern void OCKL_MANGLE_T(hsa_signal,or)(hsa_signal_t sig, long value, __ockl_memory_order mem_order); +extern void OCKL_MANGLE_T(hsa_signal,xor)(hsa_signal_t sig, long value, __ockl_memory_order mem_order); +extern long OCKL_MANGLE_T(hsa_signal,exchange)(hsa_signal_t sig, long value, __ockl_memory_order mem_order); +extern void OCKL_MANGLE_T(hsa_signal,subtract)(hsa_signal_t sig, long value, __ockl_memory_order mem_order); +extern long OCKL_MANGLE_T(hsa_signal,cas)(hsa_signal_t sig, long expected, long value, __ockl_memory_order mem_order); +extern void OCKL_MANGLE_T(hsa_signal,store)(hsa_signal_t sig, long value, __ockl_memory_order mem_order); + +#endif // OCKL_HSA_H diff --git a/amd/device-libs/ockl/inc/wgscratch.h b/amd/device-libs/ockl/inc/wgscratch.h new file mode 100644 index 0000000000000..42e0b031afc48 --- /dev/null +++ b/amd/device-libs/ockl/inc/wgscratch.h @@ -0,0 +1,9 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +extern __attribute__((const)) __local ulong *__get_scratch_lds(void); + diff --git a/amd/device-libs/ockl/src/activelane.cl b/amd/device-libs/ockl/src/activelane.cl new file mode 100644 index 0000000000000..0d164318851e1 --- /dev/null +++ b/amd/device-libs/ockl/src/activelane.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "ockl.h" + +uint +OCKL_MANGLE_U32(activelane)(void) +{ + return __builtin_amdgcn_mbcnt_hi(__builtin_amdgcn_read_exec_hi(), + __builtin_amdgcn_mbcnt_lo(__builtin_amdgcn_read_exec_lo(), 0u)); +} + diff --git a/amd/device-libs/ockl/src/add_sat.cl b/amd/device-libs/ockl/src/add_sat.cl new file mode 100644 index 0000000000000..1f5e5d89604f5 --- /dev/null +++ b/amd/device-libs/ockl/src/add_sat.cl @@ -0,0 +1,41 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +int +OCKL_MANGLE_I32(add_sat)(int x, int y) +{ + int s; + bool c = __builtin_sadd_overflow(x, y, &s); + return c ? (x < 0 ? INT_MIN : INT_MAX) : s; +} + +uint +OCKL_MANGLE_U32(add_sat)(uint x, uint y) +{ + uint s; + bool c = __builtin_uadd_overflow(x, y, &s); + return c ? UINT_MAX : s; +} + +long +OCKL_MANGLE_I64(add_sat)(long x, long y) +{ + long s; + bool c = __builtin_saddl_overflow(x, y, &s); + return c ? (x < 0 ? LONG_MIN : LONG_MAX) : s; +} + +ulong +OCKL_MANGLE_U64(add_sat)(ulong x, ulong y) +{ + ulong s; + bool c = __builtin_uaddl_overflow(x, y, &s); + return c ? ULONG_MAX : s; +} + diff --git a/amd/device-libs/ockl/src/alrs.cl b/amd/device-libs/ockl/src/alrs.cl new file mode 100644 index 0000000000000..656365e876594 --- /dev/null +++ b/amd/device-libs/ockl/src/alrs.cl @@ -0,0 +1,139 @@ + +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "ockl.h" + +static uint +bpermute_u32(uint l, uint v) +{ + return __builtin_amdgcn_ds_bpermute(l << 2, v); +} + +uint +OCKL_MANGLE_U32(alisa)(uint n) +{ + uint l = __ockl_lane_u32(); + uint ret = n; + + if (__oclc_wavefrontsize64) { + // Step 1 + ulong smask = __builtin_amdgcn_read_exec() & ~((0x2UL << l) - 0x1UL); + int slid = (int)__ockl_ctz_u64(smask); + uint t = bpermute_u32(slid, n); + ret += slid < 64 ? t : 0; + + smask &= smask - 1UL; + + // Step 2 + slid = (int)__ockl_ctz_u64(smask); + t = bpermute_u32(slid, ret); + ret += slid < 64 ? t : 0; + + smask &= smask - 1UL; + smask &= smask - 1UL; + + // Step 3 + slid = __ockl_ctz_u64(smask); + t = bpermute_u32(slid, ret); + ret += slid < 64 ? t : 0; + + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + + // Step 4 + slid = __ockl_ctz_u64(smask); + t = bpermute_u32(slid, ret); + ret += slid < 64 ? t : 0; + + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + + // Step 5 + slid = __ockl_ctz_u64(smask); + t = bpermute_u32(slid, ret); + ret += slid < 64 ? t : 0; + + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + smask &= smask - 1UL; + + // Step 6 + slid = __ockl_ctz_u64(smask); + t = bpermute_u32(slid, ret); + ret += slid < 64 ? t : 0; + } else { + // Step 1 + uint smask = __builtin_amdgcn_read_exec_lo() & ~((0x2U << l) - 0x1U); + int slid = (int)__ockl_ctz_u32(smask); + uint t = bpermute_u32(slid, n); + ret += slid < 32 ? t : 0; + + smask &= smask - 1U; + + // Step 2 + slid = (int)__ockl_ctz_u32(smask); + t = bpermute_u32(slid, ret); + ret += slid < 32 ? t : 0; + + smask &= smask - 1U; + smask &= smask - 1U; + + // Step 3 + slid = __ockl_ctz_u32(smask); + t = bpermute_u32(slid, ret); + ret += slid < 32 ? t : 0; + + smask &= smask - 1U; + smask &= smask - 1U; + smask &= smask - 1U; + smask &= smask - 1U; + + // Step 4 + slid = __ockl_ctz_u32(smask); + t = bpermute_u32(slid, ret); + ret += slid < 32 ? t : 0; + + smask &= smask - 1U; + smask &= smask - 1U; + smask &= smask - 1U; + smask &= smask - 1U; + smask &= smask - 1U; + smask &= smask - 1U; + smask &= smask - 1U; + smask &= smask - 1U; + + // Step 5 + slid = __ockl_ctz_u32(smask); + t = bpermute_u32(slid, ret); + ret += slid < 32 ? t : 0; + } + + return ret; +} diff --git a/amd/device-libs/ockl/src/base-image-intrinsics.ll b/amd/device-libs/ockl/src/base-image-intrinsics.ll new file mode 100644 index 0000000000000..50b6e4b47f627 --- /dev/null +++ b/amd/device-libs/ockl/src/base-image-intrinsics.ll @@ -0,0 +1,707 @@ +target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" +target triple = "amdgcn-amd-amdhsa" + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_1d_v4f32_i32(i32 %arg1, <8 x i32> %arg2) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 noundef 15, i32 %arg1, <8 x i32> %arg2, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_2d_v4f32_i32(i32 %arg1, i32 %arg2, <8 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, <8 x i32> %arg3, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_3d_v4f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_cube_v4f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_1darray_v4f32_i32(i32 %arg1, i32 %arg2, <8 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, <8 x i32> %arg3, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_2darray_v4f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_mip_1d_v4f32_i32(i32 %arg1, i32 %arg2, <8 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, <8 x i32> %arg3, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_mip_2d_v4f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_mip_3d_v4f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_mip_cube_v4f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_mip_1darray_v4f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_load_mip_2darray_v4f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_1d_v4f16_i32(i32 %arg1, <8 x i32> %arg2) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i32(i32 noundef 15, i32 %arg1, <8 x i32> %arg2, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_2d_v4f16_i32(i32 %arg1, i32 %arg2, <8 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, <8 x i32> %arg3, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_3d_v4f16_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_cube_v4f16_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.cube.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.cube.v4f16.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_1darray_v4f16_i32(i32 %arg1, i32 %arg2, <8 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.1darray.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, <8 x i32> %arg3, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.1darray.v4f16.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_2darray_v4f16_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.2darray.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.2darray.v4f16.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_mip_1d_v4f16_i32(i32 %arg1, i32 %arg2, <8 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.mip.1d.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, <8 x i32> %arg3, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.mip.1d.v4f16.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_mip_2d_v4f16_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.mip.2d.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.mip.2d.v4f16.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_mip_3d_v4f16_i32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.mip.3d.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.mip.3d.v4f16.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_mip_cube_v4f16_i32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.mip.cube.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.mip.cube.v4f16.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_mip_1darray_v4f16_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.mip.1darray.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.mip.1darray.v4f16.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_load_mip_2darray_v4f16_i32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.load.mip.2darray.v4f16.i32(i32 noundef 15, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.load.mip.2darray.v4f16.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_load_2d_f32_i32(i32 %arg1, i32 %arg2, <8 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.load.2d.f32.i32(i32 noundef 1, i32 %arg1, i32 %arg2, <8 x i32> %arg3, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.load.2d.f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_load_2darray_f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.load.2darray.f32.i32(i32 noundef 1, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.load.2darray.f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_load_mip_2d_f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.load.mip.2d.f32.i32(i32 noundef 1, i32 %arg1, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.load.mip.2d.f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_load_mip_2darray_f32_i32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.load.mip.2darray.f32.i32(i32 noundef 1, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.load.mip.2darray.f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_1d_v4f32_i32(<4 x float> %arg, i32 %arg2, <8 x i32> %arg3) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, <8 x i32> %arg3, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float>, i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_2d_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_3d_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.3d.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.3d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_cube_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.cube.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.cube.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_1darray_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.1darray.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.1darray.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_2darray_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.2darray.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.2darray.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_1d_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_2d_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.2d.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_3d_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.3d.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.3d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_cube_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.cube.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.cube.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_1darray_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_2darray_v4f32_i32(<4 x float> %arg, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float>, i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_1d_v4f16_i32(<4 x half> %arg, i32 %arg2, <8 x i32> %arg3) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.1d.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, <8 x i32> %arg3, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.1d.v4f16.i32(<4 x half>, i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_2d_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_3d_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.3d.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.3d.v4f16.i32(<4 x half>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_cube_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.cube.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.cube.v4f16.i32(<4 x half>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_1darray_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.1darray.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.1darray.v4f16.i32(<4 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_2darray_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.2darray.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.2darray.v4f16.i32(<4 x half>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_1d_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.1d.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.1d.v4f16.i32(<4 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_2d_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.2d.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.2d.v4f16.i32(<4 x half>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_3d_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.3d.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.3d.v4f16.i32(<4 x half>, i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_cube_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.cube.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.cube.v4f16.i32(<4 x half>, i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_1darray_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.1darray.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.1darray.v4f16.i32(<4 x half>, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_2darray_v4f16_i32(<4 x half> %arg, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.2darray.v4f16.i32(<4 x half> %arg, i32 noundef 15, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.2darray.v4f16.i32(<4 x half>, i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_2d_f32_i32(float %arg, i32 %arg2, i32 %arg3, <8 x i32> %arg4) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.2d.f32.i32(float %arg, i32 noundef 15, i32 %arg2, i32 %arg3, <8 x i32> %arg4, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.2d.f32.i32(float, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_2darray_f32_i32(float %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.2darray.f32.i32(float %arg, i32 noundef 1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.2darray.f32.i32(float, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_2d_f32_i32(float %arg, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.2d.f32.i32(float %arg, i32 noundef 1, i32 %arg2, i32 %arg3, i32 %arg4, <8 x i32> %arg5, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.2d.f32.i32(float, i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(write) +define protected void @__llvm_amdgcn_image_store_mip_2darray_f32_i32(float %arg, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6) local_unnamed_addr #2 { +bb: + tail call void @llvm.amdgcn.image.store.mip.2darray.f32.i32(float %arg, i32 noundef 1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, <8 x i32> %arg6, i32 noundef 0, i32 noundef 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.image.store.mip.2darray.f32.i32(float, i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_1d_v4f32_f32(float %arg1, <8 x i32> %arg2, <4 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 noundef 15, float %arg1, <8 x i32> %arg2, <4 x i32> %arg3, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 immarg, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_2d_v4f32_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_3d_v4f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_cube_v4f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_1darray_v4f32_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_2darray_v4f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_1d_v4f16_f32(float %arg1, <8 x i32> %arg2, <4 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.1d.v4f16.f32(i32 noundef 15, float %arg1, <8 x i32> %arg2, <4 x i32> %arg3, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.1d.v4f16.f32(i32 immarg, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_2d_v4f16_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.2d.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.2d.v4f16.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_3d_v4f16_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.3d.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.3d.v4f16.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_cube_v4f16_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.cube.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.cube.v4f16.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_1darray_v4f16_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.1darray.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.1darray.v4f16.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_2darray_v4f16_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.2darray.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.2darray.v4f16.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_sample_2d_f32_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 noundef 1, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.sample.2d.f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_sample_2darray_f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.sample.2darray.f32.f32(i32 noundef 1, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.sample.2darray.f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +attributes #0 = { nofree norecurse nosync nounwind willreturn memory(read) } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } +attributes #2 = { nofree norecurse nosync nounwind willreturn memory(write) } +attributes #3 = { nocallback nofree nosync nounwind willreturn memory(write) } diff --git a/amd/device-libs/ockl/src/buffer-intrinsics.ll b/amd/device-libs/ockl/src/buffer-intrinsics.ll new file mode 100644 index 0000000000000..19bf8b07dfad3 --- /dev/null +++ b/amd/device-libs/ockl/src/buffer-intrinsics.ll @@ -0,0 +1,31 @@ +target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" +target triple = "amdgcn-amd-amdhsa" + +declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg) #1 +declare void @llvm.amdgcn.struct.buffer.store.format.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32 immarg) #1 + + +define <4 x float> @__llvm_amdgcn_struct_buffer_load_format_v4f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) #0 { + %1 = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) + ret <4 x float> %1 +} + +define <4 x half> @__llvm_amdgcn_struct_buffer_load_format_v4f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) #0 { + %1 = call <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) + ret <4 x half> %1 +} + +define void @__llvm_amdgcn_struct_buffer_store_format_v4f32(<4 x float> %vdata, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) #1 { + call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %vdata, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) + ret void +} + +define void @__llvm_amdgcn_struct_buffer_store_format_v4f16(<4 x half> %vdata, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) #1 { + call void @llvm.amdgcn.struct.buffer.store.format.v4f16(<4 x half> %vdata, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) + ret void +} + +attributes #0 = { nocallback nofree nosync nounwind willreturn memory(read) } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } diff --git a/amd/device-libs/ockl/src/cg.cl b/amd/device-libs/ockl/src/cg.cl new file mode 100644 index 0000000000000..4ebb5632ec02f --- /dev/null +++ b/amd/device-libs/ockl/src/cg.cl @@ -0,0 +1,239 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "ockl.h" + +#define AL(P,S) __opencl_atomic_load((__global atomic_uint *)P, memory_order_relaxed, S) +#define AA(P,V,S) __opencl_atomic_fetch_add((__global atomic_uint *)P, V, memory_order_relaxed, S) + +#define AVOID_GWS() (__oclc_ISA_version == 9402 || __oclc_ISA_version == 9500 || __oclc_ISA_version >= 11000) + +// XXX do not change these two structs without changing the language runtime +struct mg_sync { + uint w0; + uint w1; +}; + +struct mg_info { + __global struct mg_sync *mgs; + uint grid_id; + uint num_grids; + ulong prev_sum; + ulong all_sum; + + struct mg_sync sgs; + uint num_wg; +}; + +static inline size_t +get_mg_info_arg(void) +{ + if (__oclc_ABI_version < 500) { + return ((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[6]; + } else { + return ((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[11]; + } +} + +static inline bool +choose_one_workgroup_workitem(void) +{ + return (__builtin_amdgcn_workitem_id_x() | __builtin_amdgcn_workitem_id_y() | __builtin_amdgcn_workitem_id_z()) == 0; +} + +static inline bool +choose_one_grid_workitem(void) +{ + return (__builtin_amdgcn_workitem_id_x() | __builtin_amdgcn_workgroup_id_x() | + __builtin_amdgcn_workitem_id_y() | __builtin_amdgcn_workgroup_id_y() | + __builtin_amdgcn_workitem_id_z() | __builtin_amdgcn_workgroup_id_z()) == 0; +} + +static inline uint +single_grid_arrive(__global struct mg_sync *s, uint members) +{ + // Assumes 65535 or fewer workgroups in the grid + uint v = AA(&s->w0, 1U, memory_scope_device); + if ((v & 0xffff) == members-1) + AA(&s->w0, 0x10000 - members, memory_scope_device); + return v & ~0xffff; +} + +static inline void +single_grid_wait(__global struct mg_sync *s, uint t) +{ + while ((AL(&s->w0, memory_scope_device) & ~0xffff) == t) + __builtin_amdgcn_s_sleep(1); +} + + +static inline void +single_grid_sync(__global struct mg_sync *s, uint members) +{ + single_grid_wait(s, single_grid_arrive(s, members)); +} + +static inline void +multi_grid_sync(__global struct mg_sync *s, uint members) +{ + // Assumes 255 or fewer GPUs in the multi grid + uint v = AA(&s->w0, 1U, memory_scope_all_svm_devices); + if ((v & 0xff) == members-1) { + AA(&s->w0, 0x100 - members, memory_scope_all_svm_devices); + } else { + v &= ~0xff; + do { + __builtin_amdgcn_s_sleep(2); + } while ((AL(&s->w0, memory_scope_all_svm_devices) & ~0xff) == v); + } +} + +__attribute__((target("gws"))) void +__ockl_gws_init(uint nwm1, uint rid) +{ + __builtin_amdgcn_ds_gws_init(nwm1, rid); +} + +__attribute__((target("gws"))) void +__ockl_gws_barrier(uint nwm1, uint rid) +{ + __builtin_amdgcn_ds_gws_barrier(nwm1, rid); +} + +__attribute__((const)) int +__ockl_grid_is_valid(void) +{ + return get_mg_info_arg() != 0UL; +} + +uint +__ockl_grid_bar_arrive(void) +{ + __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup"); + __builtin_amdgcn_s_barrier(); + uint ret = 0; + if (choose_one_workgroup_workitem()) { + __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup"); + __builtin_amdgcn_fence(__ATOMIC_RELEASE, "agent"); + __global struct mg_info *mi = (__global struct mg_info *)get_mg_info_arg(); + ret = single_grid_arrive(&mi->sgs, mi->num_wg); + } + return ret; +} + +void +__ockl_grid_bar_wait(uint t) +{ + if (choose_one_workgroup_workitem()) { + __global struct mg_info *mi = (__global struct mg_info *)get_mg_info_arg(); + single_grid_wait(&mi->sgs, t); + __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "agent"); + __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup"); + } + __builtin_amdgcn_s_barrier(); + __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup"); +} + +void +__ockl_grid_sync(void) +{ + __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup"); + __builtin_amdgcn_s_barrier(); + + if (choose_one_workgroup_workitem()) { + __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup"); + __builtin_amdgcn_fence(__ATOMIC_RELEASE, "agent"); + + if (AVOID_GWS()) { + __global struct mg_info *mi = (__global struct mg_info *)get_mg_info_arg(); + single_grid_sync(&mi->sgs, mi->num_wg); + } else { + uint nwm1 = (uint)__ockl_get_num_groups(0) * (uint)__ockl_get_num_groups(1) * (uint)__ockl_get_num_groups(2) - 1; + __ockl_gws_barrier(nwm1, 0); + } + + __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "agent"); + __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup"); + } + + __builtin_amdgcn_s_barrier(); + __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup"); +} + +__attribute__((const)) uint +__ockl_multi_grid_num_grids(void) +{ + return ((__constant struct mg_info *)get_mg_info_arg())->num_grids; +} + +__attribute__((const)) uint +__ockl_multi_grid_grid_rank(void) +{ + return ((__constant struct mg_info *)get_mg_info_arg())->grid_id; +} + +__attribute__((const)) uint +__ockl_multi_grid_size(void) +{ + return ((__constant struct mg_info *)get_mg_info_arg())->all_sum; +} + +__attribute__((const)) uint +__ockl_multi_grid_thread_rank(void) +{ + size_t r = ((__constant struct mg_info *)get_mg_info_arg())->prev_sum; + r += __ockl_get_global_linear_id(); + return r; +} + +__attribute__((const)) int +__ockl_multi_grid_is_valid(void) +{ + if (AVOID_GWS()) { + __constant struct mg_info *mi = (__constant struct mg_info *)get_mg_info_arg(); + return mi && mi->num_grids > 0; + } else { + return get_mg_info_arg() > 1; + } +} + +void +__ockl_multi_grid_sync(void) +{ + __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, ""); + __builtin_amdgcn_s_barrier(); + + bool cwwi = choose_one_workgroup_workitem(); + uint nwm1 = (uint)__ockl_get_num_groups(0) * (uint)__ockl_get_num_groups(1) * (uint)__ockl_get_num_groups(2) - 1; + __global struct mg_info *mi = (global struct mg_info *)get_mg_info_arg(); + uint nwg = mi->num_wg; + __global struct mg_sync *sgs = &mi->sgs; + + if (cwwi) { + if (AVOID_GWS()) { + single_grid_sync(sgs, nwg); + } else { + __ockl_gws_barrier(nwm1, 0); + } + } + + if (choose_one_grid_workitem()) { + multi_grid_sync(mi->mgs, mi->num_grids); + } + + if (cwwi) { + if (AVOID_GWS()) { + single_grid_sync(sgs, nwg); + } else { + __ockl_gws_barrier(nwm1, 0); + } + } + + __builtin_amdgcn_s_barrier(); +} + diff --git a/amd/device-libs/ockl/src/clz.cl b/amd/device-libs/ockl/src/clz.cl new file mode 100644 index 0000000000000..a3f5db17d79d1 --- /dev/null +++ b/amd/device-libs/ockl/src/clz.cl @@ -0,0 +1,34 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "irif.h" +#include "ockl.h" + +__attribute__((always_inline, const)) uchar +OCKL_MANGLE_T(clz,u8)(uchar i) +{ + return BUILTIN_CLZ_U8(i); +} + +__attribute__((always_inline, const)) ushort +OCKL_MANGLE_T(clz,u16)(ushort i) +{ + return BUILTIN_CLZ_U16(i); +} + +__attribute__((always_inline, const)) uint +OCKL_MANGLE_U32(clz)(uint i) +{ + return BUILTIN_CLZ_U32(i); +} + +__attribute__((always_inline, const)) ulong +OCKL_MANGLE_U64(clz)(ulong i) +{ + return BUILTIN_CLZ_U64(i); +} + diff --git a/amd/device-libs/ockl/src/cprintf.cl b/amd/device-libs/ockl/src/cprintf.cl new file mode 100644 index 0000000000000..51416c647f5db --- /dev/null +++ b/amd/device-libs/ockl/src/cprintf.cl @@ -0,0 +1,38 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +#define AL(P, O) __opencl_atomic_load(P, O, memory_scope_device) +#define ACE(P, E, V, O) __opencl_atomic_compare_exchange_strong(P, E, V, O, O, memory_scope_device) + +#define OFFSET 8 + +// Atomically reserves space to the printf data buffer and returns a pointer to it +__global char * +__printf_alloc(uint bytes) +{ + __global char *ptr; + if (__oclc_ABI_version < 500) { + ptr = (__global char *)((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[3]; + } else { + ptr = (__global char *)((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[9]; + } + + uint size = ((__global uint *)ptr)[1]; + uint offset = AL((__global atomic_uint *)ptr, memory_order_relaxed); + + for (;;) { + if (OFFSET + offset + bytes > size) + return NULL; + + if (ACE((__global atomic_uint *)ptr, &offset, offset+bytes, memory_order_relaxed)) + break; + } + + return ptr + OFFSET + offset; +} diff --git a/amd/device-libs/ockl/src/ctz.cl b/amd/device-libs/ockl/src/ctz.cl new file mode 100644 index 0000000000000..22f05a8bf7e7a --- /dev/null +++ b/amd/device-libs/ockl/src/ctz.cl @@ -0,0 +1,34 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "irif.h" +#include "ockl.h" + +__attribute__((always_inline, const)) uchar +OCKL_MANGLE_T(ctz,u8)(uchar i) +{ + return BUILTIN_CTZ_U8(i); +} + +__attribute__((always_inline, const)) ushort +OCKL_MANGLE_T(ctz,u16)(ushort i) +{ + return BUILTIN_CTZ_U16(i); +} + +__attribute__((always_inline, const)) uint +OCKL_MANGLE_U32(ctz)(uint i) +{ + return BUILTIN_CTZ_U32(i); +} + +__attribute__((always_inline, const)) ulong +OCKL_MANGLE_U64(ctz)(ulong i) +{ + return BUILTIN_CTZ_U64(i); +} + diff --git a/amd/device-libs/ockl/src/dm.cl b/amd/device-libs/ockl/src/dm.cl new file mode 100644 index 0000000000000..9a5970249ad10 --- /dev/null +++ b/amd/device-libs/ockl/src/dm.cl @@ -0,0 +1,1192 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "ockl.h" + +#pragma OPENCL EXTENSION cl_khr_int64_base_atomics : enable +#pragma OPENCL EXTENSION cl_khr_int64_extended_atomics : enable + +extern ulong __ockl_devmem_request(ulong addr, ulong size); + +// Define this to track user requested non-slab (i.e. "large") in-use +// allocations. This adds the definition of a query function nna() that +// returns a snapshot of the current value. +#define NON_SLAB_TRACKING 1 + +// The number of kinds of blocks. Do not change. +#define NUM_KINDS 16 + +// The size where we switch the large & slow mechanism. Do not change. +#define ALLOC_THRESHOLD 3072 + +// This controls the size of the heap, and also how often +// we need to expand the capacity of the array that tracks +// the allocations that have been made. +// +// With the definition below, 256, one level can hold 256 +// slabs (512 MiB), and two levels can hold (256+1)*256 = 65792 +// slabs (131585 MiB) +#define SDATA_SHIFT 8 +#define NUM_SDATA (1 << SDATA_SHIFT) +#define SDATA_MASK (NUM_SDATA - 1) +#define MAX_RECORDABLE_SLABS ((NUM_SDATA + 1) * NUM_SDATA) + +// Type of variable use to hold a kind +typedef uint kind_t; + +// Type of variable used to hold a sdata index +typedef uint sid_t; + +// Various info about a given kind of block +struct kind_info_s { + uint num_blocks; + uint num_usable_blocks; + uint skip_threshold; + uint block_offset; + uint first_unusable; + uint gap_unusable; + uint pattern_unusable; +}; + +static const __constant struct kind_info_s kinfo[NUM_KINDS] = { + { /* 0: 16 */ 130054, 129546, 110114, 16288, 6, 256, 0x00000000 }, + { /* 1: 24 */ 86927, 86758, 73744, 10904, 399, 512, 0x00000000 }, + { /* 2: 32 */ 65280, 64770, 55054, 8192, 0, 128, 0x00000000 }, + { /* 3: 48 */ 43576, 43406, 36895, 5504, 56, 256, 0x00000000 }, + { /* 4: 64 */ 32703, 32193, 27364, 4160, 63, 64, 0x00000000 }, + { /* 5: 96 */ 21816, 21646, 18399, 2816, 56, 128, 0x00000000 }, + { /* 6: 128 */ 16367, 15856, 13477, 2176, 15, 32, 0x00008000 }, + { /* 7: 192 */ 10915, 10745, 9133, 1472, 35, 64, 0x00000000 }, + { /* 8: 256 */ 8187, 7676, 6524, 1280, 11, 16, 0x08000800 }, + { /* 9: 384 */ 5459, 5289, 4495, 896, 19, 32, 0x00080000 }, + { /* 10: 512 */ 4094, 3583, 3045, 1024, 6, 8, 0x40404040 }, + { /* 11: 768 */ 2730, 2560, 2176, 512, 10, 16, 0x04000400 }, + { /* 12: 1024 */ 2047, 1536, 1305, 1024, 3, 4, 0x88888888 }, + { /* 13: 1536 */ 1365, 1195, 1015, 512, 5, 8, 0x20202020 }, + { /* 14: 2048 */ 1023, 512, 435, 2048, 1, 2, 0xaaaaaaaa }, + { /* 15: 3072 */ 682, 512, 435, 2048, 2, 4, 0x44444444 }, +}; + +// A slab is a chunk of memory used to provide "block"s whose addresses are +// returned by malloc. The slab tracks which blocks are in use using a bit +// array "bits". The blocks themselves start at offset "block_offset". +typedef struct slab_s { + kind_t k; // The kind of the blocks + sid_t i; // The index of the slab in the heap + atomic_uint start; // Used to guide the search for unused blocks + uint pad; + atomic_uint in_use[2*1024*1024 / 4 - 4]; // An array of per-block bits, followed by the blocks +} slab_t; + +// The minimum number of ticks each slab allocation must be separated by +#define SLAB_TICKS 20000 + +// This struct captures a little more information about a given slab +// such as its address and its number of used blocks. There is another +// member used to increase the number of slabs that can be recorded in +// the heap +typedef struct sdata_s { + atomic_ulong array; // Address of an array of sdata_t + atomic_ulong saddr; // Slab address is really a __global slab_t * + atomic_uint num_used_blocks; +} sdata_t; + +// The number of ulong that cover an sdata_t +#define ULONG_PER_SDATA 3 + +// The length of a CAS loop sleep +#define CAS_SLEEP 2 + +// This is used to communicate that a result is +// not currently available due to a limit on how +// fast we are allowed to create new slabs +#define SDATA_BUSY (__global sdata_t *)1 + +// Possible results when trying to increase the number of recordable slabs +#define GROW_SUCCESS 0 +#define GROW_BUSY 1 +#define GROW_FAILURE 2 + +// The minimum number of ticks each grow must be separated by +#define GROW_TICKS 30000 + +// The number of ulong per cache line used to separate atomics +#define ULONG_PER_CACHE_LINE 16 +#define ATOMIC_PAD (ULONG_PER_CACHE_LINE-1) + +// Type used to hold a search start index +typedef struct start_s { + atomic_uint value; +#if ATOMIC_PAD > 0 + ulong pad[ATOMIC_PAD]; +#endif +} start_t; + +// Type used to hold the number of allocated slabs +typedef struct nallocated_s { + atomic_uint value; +#if ATOMIC_PAD > 0 + ulong pad[ATOMIC_PAD]; +#endif +} nallocated_t; + +// Type used to hold the number of recordable slabs +typedef struct nrecordable_s { + atomic_uint value; +#if ATOMIC_PAD > 0 + ulong pad[ATOMIC_PAD]; +#endif +} nrecordable_t; + +// Type used to hold a real-time clock sample +typedef struct rtcsample_s { + atomic_ulong value; +#if ATOMIC_PAD > 0 + ulong pad[ATOMIC_PAD]; +#endif +} rtcsample_t; + +// The management structure +// All bits 0 is an acceptable state, and the expected initial state +typedef struct heap_s { + start_t start[NUM_KINDS]; // Used to guide the search for a slab to allocate from + nallocated_t num_allocated_slabs[NUM_KINDS]; // The number of allocated slabs of a given kind + nrecordable_t num_recordable_slabs[NUM_KINDS]; // The number of slabs that can be recorded (a multiple of NUM_SDATA) + rtcsample_t salloc_time[NUM_KINDS]; // The time the most recent slab allocation was started + rtcsample_t grow_time[NUM_KINDS]; // The time the most recent grow recordable was started + sdata_t sdata[NUM_KINDS][NUM_SDATA]; // Information about all allocated slabs + atomic_ulong initial_slabs; // Next initial slab to deliver + ulong initial_slabs_end; // End of inititial slabs + ulong initial_slabs_start; // Start of initial slabs +#if defined NON_SLAB_TRACKING +#if ATOMIC_PAD > 1 + ulong pad[ATOMIC_PAD-1]; +#endif + atomic_ulong num_nonslab_allocations; // Count of number of non-slab allocations that have not been freed +#endif +} heap_t; + +// Atomics wrappers +#define AL(P, O) __opencl_atomic_load(P, O, memory_scope_device) +#define AS(P, V, O) __opencl_atomic_store(P, V, O, memory_scope_device) +#define AFA(P, V, O) __opencl_atomic_fetch_add(P, V, O, memory_scope_device) +#define AFS(P, V, O) __opencl_atomic_fetch_sub(P, V, O, memory_scope_device) +#define AFN(P, V, O) __opencl_atomic_fetch_and(P, V, O, memory_scope_device) +#define AFO(P, V, O) __opencl_atomic_fetch_or (P, V, O, memory_scope_device) +#define ACE(P, E, V, O) __opencl_atomic_compare_exchange_strong(P, E, V, O, O, memory_scope_device) + +#define NEED_RELEASE __oclc_ISA_version >= 9402 && __oclc_ISA_version < 10000 + +// get the heap pointer +static __global heap_t * +get_heap_ptr(void) { + if (__oclc_ABI_version < 500) { + static __global heap_t heap; + return &heap; + } else { + return (__global heap_t *)((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[12]; + } +} + +// The actual number of blocks in a slab with blocks of kind k +static uint +num_blocks(kind_t k) +{ + return kinfo[k].num_blocks; +} + +// The usable number of blocks in a slab with blocks of kind k +static uint +num_usable_blocks(kind_t k) +{ + return kinfo[k].num_usable_blocks; +} + +// The number of used blocks in a slab of kind k triggering skipping while searching +static uint +skip_threshold(kind_t k) +{ + return kinfo[k].skip_threshold; +} + +// The offset to the first block in a slab of kind k +static uint +block_offset(kind_t k) +{ + return kinfo[k].block_offset; +} + +// The index of the first unusable block in a slab of kind k +static uint +first_unusable(kind_t k) +{ + return kinfo[k].first_unusable; +} + +// The gap or distance between indices of unusable blocks in a slab of kind k +static uint +gap_unusable(kind_t k) +{ + return kinfo[k].gap_unusable; +} + +// The pattern of unusable bits when the gap is less than 32 +static uint +pattern_unusable(kind_t k) +{ + return kinfo[k].pattern_unusable; +} + +// The number of active lanes at this point +static uint +active_lane_count(void) +{ + if (__oclc_wavefrontsize64) { + return __builtin_popcountl(__builtin_amdgcn_read_exec()); + } else { + return __builtin_popcount(__builtin_amdgcn_read_exec_lo()); + } +} + +// Overloads to broadcast the value held by the first active lane +// The result is known to be wave-uniform +static __attribute__((overloadable)) uint +first(uint v) +{ + return __builtin_amdgcn_readfirstlane(v); +} + +static __attribute__((overloadable)) ulong +first(ulong v) +{ + uint2 v2 = __builtin_astype(v, uint2); + uint2 w2; + w2.x = __builtin_amdgcn_readfirstlane(v2.x); + w2.y = __builtin_amdgcn_readfirstlane(v2.y); + return __builtin_astype(w2, ulong); +} + +static __attribute__((overloadable)) __global void * +first(__global void * v) +{ + uint2 v2 = __builtin_astype(v, uint2); + uint2 w2; + w2.x = __builtin_amdgcn_readfirstlane(v2.x); + w2.y = __builtin_amdgcn_readfirstlane(v2.y); + return __builtin_astype(w2, __global void *); +} + +// Read val from one active lane whose predicate is one. +// If no lanes have the predicate set, return none +// This is like first, except that first may not have its predicate set +static uint +elect_uint(int pred, uint val, uint none) +{ + // Pretend wave32 doesn't exist. The wave64 ballot works, and the high half + // will fold out as 0. + uint ret = none; + + ulong mask = __builtin_amdgcn_ballot_w64(pred != 0); + if (mask != 0UL) { + uint l = __ockl_ctz_u64(mask); + ret = __builtin_amdgcn_ds_bpermute(l << 2, val); + } + + return ret; +} + +// Count the number of nonzero arguments across the wave +static uint +votes(bool b) +{ + ulong mask = __builtin_amdgcn_ballot_w64(b); + return __builtin_popcountl(mask); +} + +// The kind of the smallest block that can hold sz bytes +static uint +size_to_kind(uint sz) +{ + sz = sz < 16 ? 16 : sz; + uint b = 31 - OCKL_MANGLE_U32(clz)(sz); + uint v = 1 << b; + return ((b - 4) << 1) + (sz > v) + (sz > (v | (v >> 1))); +} + +// The size of a block of kind k +// Alternatively we could place this in kinfo +static uint +kind_to_size(kind_t k) +{ + uint s = 1 << ((k >> 1) + 4); + return s + ((k & 1) != 0 ? (s >> 1) : 0); +} + +// Get the sdata pointer corresponding to kind k and index i +// Assumes only 2 levels +static __global sdata_t * +sdata_for(__global heap_t *hp, kind_t k, sid_t i) +{ + if (i >= NUM_SDATA) { + i -= NUM_SDATA; + __global sdata_t *sdp = &hp->sdata[k][i >> SDATA_SHIFT]; + ulong array = AL(&sdp->array, memory_order_relaxed); + __global sdata_t *sda = (__global sdata_t *)array; + return &sda[i & SDATA_MASK]; + } else { + return &hp->sdata[k][i]; + } +} + +// Get the sdata parent pointer corresponding to kind k and index i +// Also assumes only 2 levels, and i must be >= NUM_SDATA +static __global sdata_t * +sdata_parent_for(__global heap_t *hp, kind_t k, sid_t i) +{ + return &hp->sdata[k][(i - NUM_SDATA) >> SDATA_SHIFT]; +} + +// Free a non-slab allocation +static void +non_slab_free(ulong addr) +{ + __ockl_devmem_request(addr, 0); + +#if defined NON_SLAB_TRACKING + uint aid = __ockl_activelane_u32(); + uint nactive = active_lane_count(); + + if (aid == 0) { + __global heap_t *hp = get_heap_ptr(); + AFS(&hp->num_nonslab_allocations, nactive, memory_order_relaxed); + } +#endif +} + +// public dealloc() entrypoint +__attribute__((cold)) void +__ockl_dm_dealloc(ulong addr) +{ + if ((addr & 0xfffUL) == 0UL) { + if (addr) + non_slab_free(addr); + + return; + } + + if (NEED_RELEASE) { + __builtin_amdgcn_fence(__ATOMIC_RELEASE, "agent", "global"); + } + + // Find a slab block + ulong saddr = addr & ~(ulong)0x1fffffUL; + __global slab_t *sptr = (__global slab_t *)saddr; + kind_t my_k = sptr->k; + sid_t my_i = sptr->i; + + __global heap_t *hp = get_heap_ptr(); + int go = 1; + do { + if (go) { + kind_t first_k = first(my_k); + sid_t first_i = first(my_i); + if (my_k == first_k && my_i == first_i) { + uint aid = __ockl_activelane_u32(); + uint nactive = active_lane_count(); + + __global sdata_t *sdp = 0; + if (aid == 0) + sdp = sdata_for(hp, first_k, first_i); + sdp = first(sdp); + + uint b = (uint)(addr - (saddr + block_offset(first_k))) / kind_to_size(first_k); + uint mask = ~(1 << (b & 0x1f)); + AFN(&sptr->in_use[b >> 5], mask, memory_order_relaxed); + + if (aid == 0) + AFS(&sdp->num_used_blocks, nactive, memory_order_relaxed); + + go = 0; + } + } + } while (__ockl_wfany_i32(go)); +} + +// The is the malloc implementation for sizes greater +// than ALLOC_THRESHOLD +static __global void * +non_slab_malloc(size_t sz) +{ + ulong addr = __ockl_devmem_request(0, sz); + +#if defined NON_SLAB_TRACKING + if (addr != 0) { + uint aid = __ockl_activelane_u32(); + uint nactive = active_lane_count(); + + if (aid == 0) { + __global heap_t *hp = get_heap_ptr(); + AFA(&hp->num_nonslab_allocations, nactive, memory_order_relaxed); + } + } +#endif + + return (__global void *)addr; +} + +// Wait for a while to let a new slab of kind k to appear +static void +new_slab_wait(__global heap_t *hp, kind_t k) +{ + uint aid = __ockl_activelane_u32(); + if (aid == 0) { + ulong expected = AL(&hp->salloc_time[k].value, memory_order_relaxed); + ulong now = __ockl_steadyctr_u64(); + ulong dt = now - expected; + if (dt < SLAB_TICKS) + __ockl_rtcwait_u32(SLAB_TICKS - (uint)dt); + } +} + +// Wait for a while to let the number of recordable slabs of kind k to grow +static void +grow_recordable_wait(__global heap_t *hp, kind_t k) +{ + uint aid = __ockl_activelane_u32(); + if (aid == 0) { + ulong expected = AL(&hp->grow_time[k].value, memory_order_relaxed); + ulong now = __ockl_steadyctr_u64(); + ulong dt = now - expected; + if (dt < GROW_TICKS) + __ockl_rtcwait_u32(GROW_TICKS - (uint)dt); + } +} + +// Wait to let a CAS failure clear +static void +cas_wait(void) +{ + __builtin_amdgcn_s_sleep(CAS_SLEEP); +} + +// Obtain a new sdata array +// Expect only one active lane here +static ulong +obtain_new_array(void) +{ + return __ockl_devmem_request(0, sizeof(sdata_t) * NUM_SDATA); +} + +// Clear an array of sdata +static void +clear_array(ulong a) +{ + uint aid = __ockl_activelane_u32(); + uint nactive = active_lane_count(); + __global ulong *p = (__global ulong *)a; + + for (uint i = aid; i < NUM_SDATA*ULONG_PER_SDATA; i += nactive) + p[i] = 0UL; +} + +// Release an array +// Expect only one active lane here +static void +release_array(ulong a) +{ + __ockl_devmem_request(a, 0); +} + +// Try to grow the number of recordable slabs +// The arguments and result are uniform +static uint +try_grow_num_recordable_slabs(__global heap_t *hp, kind_t k) +{ + uint aid = __ockl_activelane_u32(); + uint nrs = 0; + if (aid == 0) + nrs = AL(&hp->num_recordable_slabs[k].value, memory_order_relaxed); + nrs = first(nrs); + + if (nrs == MAX_RECORDABLE_SLABS) + return GROW_FAILURE; + + uint ret = GROW_BUSY; + if (aid == 0) { + ulong expected = AL(&hp->grow_time[k].value, memory_order_relaxed); + ulong now = __ockl_steadyctr_u64(); + if (now - expected >= GROW_TICKS && + ACE(&hp->grow_time[k].value, &expected, now, memory_order_relaxed)) + ret = GROW_FAILURE; + } + ret = first(ret); + + if (ret == GROW_BUSY) + return ret; + + ulong sa = 0; + if (aid == 0) + sa = obtain_new_array(); + sa = first(sa); + + if (!sa) + return ret; + + clear_array(sa); + + + for (;;) { + if (aid == 0) + nrs = AL(&hp->num_recordable_slabs[k].value, memory_order_relaxed); + nrs = first(nrs); + + if (nrs == MAX_RECORDABLE_SLABS) { + if (aid == 0) + release_array(sa); + return ret; + } + + if (aid == 0) { + __global sdata_t *sdp = sdata_parent_for(hp, k, nrs); + + ulong expected = 0UL; + bool done = ACE(&sdp->array, &expected, sa, memory_order_relaxed); + ret = done ? GROW_SUCCESS : ret; + if (done) + AFA(&hp->num_recordable_slabs[k].value, NUM_SDATA, memory_order_release); + } + ret = first(ret); + + if (ret == GROW_SUCCESS) + return ret; + + cas_wait(); + } +} + +// Obtain a new slab +// Only expect one lane active here +static ulong +obtain_new_slab(__global heap_t *hp) +{ + ulong is = AL(&hp->initial_slabs, memory_order_relaxed); + ulong se = hp->initial_slabs_end; + if (is < se) { + is = AFA(&hp->initial_slabs, 1UL << 21, memory_order_relaxed); + if (is < se) + return is; + } + ulong ret = __ockl_devmem_request(0, 1UL << 21); + return ret; +} + +// Initialize a slab +// Rely on the caller to release the changes +static void +initialize_slab(__global slab_t *s, kind_t k) +{ + uint aid = __ockl_activelane_u32(); + uint nactive = active_lane_count(); + uint g = gap_unusable(k); + uint m = num_blocks(k); + uint n = (m + 31) >> 5; + + __global uint *p = (__global uint *)&s->in_use; + if (g > 32) { + for (uint i = aid; i < n; i += nactive) + p[i] = 0; + + uint di = g * nactive; + for (uint i = first_unusable(k) + aid*g; i < m; i += di) + p[i >> 5] = 1 << (i & 0x1f); + } else { + uint v = pattern_unusable(k); + for (uint i = aid; i < n; i += nactive) + p[i] = v; + } + + if (aid == 0) { + uint l = m & 0x1f; + if (l != 0) + p[n-1] |= ~0 << l; + + *((__global uint4 *)s) = (uint4)(k, 0, 0, 0); + } +} + +// Release a slab +// Only expect one lane active here +static void +release_slab(ulong saddr) +{ + __ockl_devmem_request(saddr, 0); +} + +// Try to allocate a new slab of kind k +static __global sdata_t * +try_allocate_new_slab(__global heap_t *hp, kind_t k) +{ + uint aid = __ockl_activelane_u32(); + + for (;;) { + uint nas = 0; + uint nrs = 0;; + + if (aid == 0) + nas = AL(&hp->num_allocated_slabs[k].value, memory_order_relaxed); + nas = first(nas); + + if (nas == MAX_RECORDABLE_SLABS) + return (__global sdata_t *)0; + + if (aid == 0) { + uint expected = 0; + bool s = ACE(&hp->num_recordable_slabs[k].value, &expected, NUM_SDATA, memory_order_relaxed); + nrs = s ? NUM_SDATA : expected; + } + nrs = first(nrs); + + if (nas == nrs) { + uint result = try_grow_num_recordable_slabs(hp, k); + if (result != GROW_SUCCESS) { + grow_recordable_wait(hp, k); + return result == GROW_FAILURE ? (__global sdata_t *)0 : SDATA_BUSY; + } + } + + __global sdata_t *ret = SDATA_BUSY; + + if (aid == 0) { + ulong expected = AL(&hp->salloc_time[k].value, memory_order_relaxed); + ulong now = __ockl_steadyctr_u64(); + if (now - expected >= SLAB_TICKS && + ACE(&hp->salloc_time[k].value, &expected, now, memory_order_relaxed)) + ret = (__global sdata_t *)0; + } + ret = first(ret); + + if (ret) + return ret; + + ulong saddr = 0; + if (aid == 0) + saddr = obtain_new_slab(hp); + saddr = first(saddr); + + if (!saddr) + return (__global sdata_t *)0; + + initialize_slab((__global slab_t *)saddr, k); + + for (;;) { + if (aid == 0) + nas = AL(&hp->num_allocated_slabs[k].value, memory_order_relaxed); + nas = first(nas); + + if (nas == MAX_RECORDABLE_SLABS) + return (__global sdata_t *)0; + + if (aid == 0) + nrs = AL(&hp->num_recordable_slabs[k].value, memory_order_relaxed); + nrs = first(nrs); + + if (nas == nrs) { + if (aid == 0) + release_slab(saddr); + break; + } + + if (aid == 0) { + ret = sdata_for(hp, k, nas); + ((__global slab_t *)saddr)->i = nas; + ulong expected = 0; + bool done = ACE(&ret->saddr, &expected, saddr, memory_order_relaxed); + ret = done ? ret : (__global sdata_t *)0; + if (done) + AFA(&hp->num_allocated_slabs[k].value, 1, memory_order_release); + } + ret = first(ret); + + if (ret) + return ret; + + cas_wait(); + } + } +} + +// Find a slab of kind k that can be searched for blocks using +// the "normal" approach. The arguments and results are uniform +static __global sdata_t * +normal_slab_find(__global heap_t *hp, kind_t k, uint nas) +{ + __global sdata_t *ret = (__global sdata_t *)0; + uint aid = __ockl_activelane_u32(); + uint nactive = active_lane_count(); + + for (;;) { + if (nas > 0) { + int nleft = nas; + + uint i = 0; + if (aid == 0) + i = AL(&hp->start[k].value, memory_order_relaxed); + i = (first(i) + aid) % nas; + + do { + __global sdata_t *sdp = sdata_for(hp, k, i); + uint nub = AL(&sdp->num_used_blocks, memory_order_relaxed); + + uint besti = first(elect_uint(nub < skip_threshold(k), i, ~0)); + + if (besti != ~0) + return sdata_for(hp, k, besti); + + i = (i + nactive) % nas; + if (aid == 0) + AS(&hp->start[k].value, i, memory_order_relaxed); + nleft -= nactive; + } while (nleft > 0); + } + + __global sdata_t *sdp = try_allocate_new_slab(hp, k); + if (sdp != SDATA_BUSY) + return sdp; + + new_slab_wait(hp, k); + if (aid == 0) + nas = AL(&hp->num_allocated_slabs[k].value, memory_order_relaxed); + nas = first(nas); + } +} + +// Find a slab of kind k that can be searched for blocks using +// the "final" approach. The arguments and results are uniform +static __global sdata_t * +final_slab_find(__global heap_t *hp, kind_t k0) +{ + __global sdata_t *ret = (__global sdata_t *)0; + uint aid = __ockl_activelane_u32(); + uint nactive = active_lane_count(); + + for (kind_t k = k0;;) { + __global sdata_t *sda = hp->sdata[k]; + int nleft = MAX_RECORDABLE_SLABS; + + uint i = 0; + if (aid == 0) + i = AL(&hp->start[k].value, memory_order_relaxed); + i = (first(i) + aid) % MAX_RECORDABLE_SLABS; + + do { + __global sdata_t *sdp = sdata_for(hp, k, i); + uint nub = AL(&sdp->num_used_blocks, memory_order_relaxed); + + uint besti = first(elect_uint(nub < num_usable_blocks(k), i, ~0)); + + if (besti != ~0) + return sdata_for(hp, k, besti); + + i = (i + nactive) % MAX_RECORDABLE_SLABS; + if (aid == 0) + AS(&hp->start[k].value, i, memory_order_relaxed); + + nleft -= nactive; + } while (nleft > 0); + + uint nextk = k + 2 - (k & 1); + + if (k != k0 || nextk >= NUM_KINDS) + return (__global sdata_t *)0; + + uint nas = 0; + if (aid == 0) + nas = AL(&hp->num_allocated_slabs[nextk].value, memory_order_relaxed); + nas = first(nas); + + if (nas < MAX_RECORDABLE_SLABS) + return normal_slab_find(hp, nextk, nas); + + k = nextk; + } +} + +// Find a slab of kind k that can be searched for blocks +// The arguments and results are uniform +static __global sdata_t * +slab_find(__global heap_t *hp, kind_t k) +{ + uint aid = __ockl_activelane_u32(); + + uint nas = 0; + if (aid == 0) + nas = AL(&hp->num_allocated_slabs[k].value, memory_order_relaxed); + nas = first(nas); + + if (nas < MAX_RECORDABLE_SLABS) + return normal_slab_find(hp, k, nas); + else + return final_slab_find(hp, k); +} + +// Find an empty block in a specific slab +// The argument is uniform, the result is not +static __global void * +block_find(__global sdata_t *sdp) +{ + uint aid = __ockl_activelane_u32(); + uint nactive = active_lane_count(); + __global slab_t *sp = (__global slab_t *)AL(&sdp->saddr, memory_order_relaxed); + kind_t k = sp->k; + + uint i = 0; + if (aid == 0) + i = AFA(&sp->start, nactive, memory_order_relaxed); + i = (((first(i) + aid) << 5) % num_blocks(k)) >> 5; + + uint n = (num_blocks(k) + 31) >> 5; + + __global void *ret = (__global void *)0; + + for (uint j=0; jin_use + i; + uint m = AL(p, memory_order_relaxed); + if (m != ~0) { + uint b = __ockl_ctz_u32(~m); + uint mm = AFO(p, 1 << b, memory_order_relaxed); + if ((mm & (1 << b)) == 0) { + uint ii = (i << 5) + b; + ret = (__global void *)((__global char *)sp + block_offset(k) + kind_to_size(k)*ii); + break; + } + } + i = (i + 1) % n; + } + + uint done = votes(ret != (__global void *)0); + if (aid == 0) + AFA(&sdp->num_used_blocks, done, memory_order_relaxed); + + return ret; +} + +// This is the malloc implementation for sizes that fit in some kind of block +static __global void * +slab_malloc(int sz) +{ + kind_t my_k = size_to_kind(sz); + __global void *ret = (__global void *)0; + __global heap_t *hp = get_heap_ptr(); + + int k_go = 1; + do { + if (k_go) { + kind_t first_k = first(my_k); + if (first_k == my_k) { + int s_go = 1; + do { + if (s_go) { + __global sdata_t *sdp = first(slab_find(hp, first_k)); + if (sdp != (__global sdata_t *)0) { + ret = block_find(sdp); + if (ret != (__global void *)0) { + k_go = 0; + s_go = 0; + } + } else { + k_go = 0; + s_go = 0; + } + } + } while (__ockl_wfany_i32(s_go)); + } + } + } while (__ockl_wfany_i32(k_go)); + + return ret; +} + +// public alloc() entrypoint +__attribute__((cold)) __global void * +__ockl_dm_alloc(ulong sz) +{ + if (sz == 0) + return (__global void *)0; + + if (sz > ALLOC_THRESHOLD) + return non_slab_malloc(sz); + + return slab_malloc(sz); +} + +// Initialize the heap +// This is intended to be called by a kernel launched by the language runtime +// at device initialization time. The launched NDrange must have one workgroup +// consisting of 256 workitems. +__attribute__((weak)) void +__ockl_dm_init_v1(ulong hp, ulong sp, uint hb, uint nis) +{ + uint lid = __ockl_get_local_id(0); + + // 0 is used to indicate no clearing needed + if (hb) { + __global int4 *p = (__global int4 *)(hp + lid*16); + for (int i=0; i<131072/16/256; ++i) { + *p = (int4)0; + p += 256; + } + } + + __builtin_amdgcn_fence(__ATOMIC_RELEASE, "agent", "global"); + __builtin_amdgcn_s_barrier(); + + if (lid == 0) { + __global heap_t *thp = (__global heap_t *)hp; + AS(&thp->initial_slabs, sp, memory_order_relaxed); + thp->initial_slabs_end = sp + ((ulong)nis << 21); + thp->initial_slabs_start = sp; + } +} + +// reverse local array, n <= wavesize +// Expect this to be called by one full wave +// TODO make this work on devices which can't permute full wave +static void __attribute__((target("gfx8-insts"))) +reverse_la(__local uint *x, uint i, uint n) +{ + if (i < n) { + uint j = n - 1 - i; + x[i] = __builtin_amdgcn_ds_bpermute(j << 2, x[i]); + } +} + +// Shift wavesize consecutive elements downward by n +static void +shift_la(__local uint *a, uint i, uint n) +{ + a[i] = a[i+n]; +} + +// Find and record destination location for trim +static uint +dst_scan(__global heap_t *hp, kind_t k, ulong iss, ulong ise, uint l, uint i, uint n, uint c0, __local uint *d) +{ + bool b = false; + + if (l+i < n) { + __global sdata_t *sdp = sdata_for(hp, k, l+i); + uint nub = AL(&sdp->num_used_blocks, memory_order_relaxed); + ulong saddr = AL(&sdp->saddr, memory_order_relaxed); + + b = nub == 0 && saddr && (saddr < iss || saddr >= ise); + if (b) { + release_slab(saddr); + AS(&sdp->saddr, 0UL, memory_order_relaxed); + AS(&sdp->num_used_blocks, 0U, memory_order_relaxed); + d[c0+__ockl_activelane_u32()] = l+i; + } + } + + return c0 + votes(b); +} + +// Find and record source location for trim +static uint +src_scan(__global heap_t *hp, kind_t k, ulong iss, ulong ise, uint r, uint i, uint n, uint c0, __local uint *s) +{ + bool b = false; + + if (r+i < n) { + __global sdata_t *sdp = sdata_for(hp, k, r+i); + ulong saddr = AL(&sdp->saddr, memory_order_relaxed); + uint nub = AL(&sdp->num_used_blocks, memory_order_relaxed); + + b = nub > 0 || (saddr >= iss && saddr < ise); + if (b) { + s[c0+__ockl_activelane_u32()] = r+i; + } else if (saddr) { + release_slab(saddr); + AS(&sdp->saddr, 0UL, memory_order_relaxed); + AS(&sdp->num_used_blocks, 0U, memory_order_relaxed); + } + } + + uint c = votes(b); + reverse_la(s + c0, i, c); + return c0 + c; +} + +// Count available slabs +static uint +end_scan(__global heap_t *hp, kind_t k, uint l, uint i, uint n, int c0) +{ + bool b = false; + + if (l+i < n) { + __global sdata_t *sdp = sdata_for(hp, k, l+i); + ulong saddr = AL(&sdp->saddr, memory_order_relaxed); + b = saddr != 0; + } + + return c0 + votes(b); +} + +// Move up to n slabs (n <= wavesize) from index in s[] to index in d[] +// and return the number moved +static uint +move_slabs(__global heap_t *hp, kind_t k, uint i, uint n, __local uint *d, __local uint *s) +{ + bool b = i < n && d[i] < s[i]; + if (b) { + __global sdata_t *dsdp = sdata_for(hp, k, d[i]); + + __global sdata_t *ssdp = sdata_for(hp, k, s[i]); + ulong ssaddr = AL(&ssdp->saddr, memory_order_relaxed); + ((__global slab_t *)ssaddr)->i = d[i]; + + AS(&dsdp->saddr, ssaddr, memory_order_relaxed); + AS(&dsdp->num_used_blocks, AL(&ssdp->num_used_blocks, memory_order_relaxed), memory_order_relaxed); + + AS(&ssdp->saddr, 0UL, memory_order_relaxed); + AS(&ssdp->num_used_blocks, 0UL, memory_order_relaxed); + } + + return votes(b); +} + +// "Trim" slabs of kind k +// Expecting an exactly one-full-wave caller +static uint +trim_kind(__global heap_t *hp, kind_t k, ulong iss, ulong ise, uint i, uint n, __local uint *srcs, __local uint *dsts) +{ + uint l = 0; + uint lm = 0; + uint nd = 0; + const uint wsz = __oclc_wavefrontsize64 ? 64 : 32; + + uint r = (n - 1) / wsz * wsz; + uint ns = 0; + + for (;;) { + while (l < n && nd < wsz) { + nd = dst_scan(hp, k, iss, ise, l, i, n, nd, dsts); + l += wsz; + } + + if (nd == 0) + break; + + while (r < n && ns < wsz) { + ns = src_scan(hp, k, iss, ise, r, i, n, ns, srcs); + r -= wsz; + } + + if (ns == 0) + break; + + uint m = nd < ns ? nd : ns; + m = wsz < m ? wsz : m; + + uint mm = move_slabs(hp, k, i, m, dsts, srcs); + + if (mm) + lm = dsts[mm-1]; + + if (l >= n || mm != m) + break; + + shift_la(dsts, i, m); + shift_la(srcs, i, m); + nd -= m; + ns -= m; + } + + lm = lm / wsz * wsz; + l = lm; + uint nn = lm; + do { + nn = end_scan(hp, k, l, i, n, nn); + l += wsz; + } while (l == nn); + + return nn; +} + +// "Trim" non-initial empty slabs of all kinds +// +// This function must be called from a 1D 1-full-wave kernel that only +// calls this function. When that kernel runs, no other kernel on the +// device using dm_[de]alloc may be running. +// +// The calling kernel must pass in a generic pointer to a __local int array with 4*wavesize elements +// +// TODO consider a design which allows trimming concurrent with other use +// +__attribute__((weak, cold)) void +__ockl_dm_trim(int *mem) +{ + __local uint *dsts = (__local uint *)mem; + __local uint *srcs = dsts + (__oclc_wavefrontsize64 ? 2*64 : 2*32); + __global heap_t *hp = get_heap_ptr(); + ulong iss = hp->initial_slabs_start; + ulong ise = hp->initial_slabs_end; + uint i = __ockl_lane_u32(); + + for (kind_t k=0; knum_allocated_slabs[k].value, memory_order_relaxed); + nas = first(nas); + if (nas) { + uint tnas = trim_kind(hp, k, iss, ise, i, nas, srcs, dsts); + if (i == 0) + AS(&hp->num_allocated_slabs[k].value, tnas, memory_order_relaxed); + } + } +} + +// Grab some info about the current state of the heap +// Expecting the caller to limit the number of threads executing here to 1 +__attribute__((cold)) void +__ockl_dm_hinfo(ulong *rp) +{ + __global heap_t *hp = get_heap_ptr(); + + *rp++ = NUM_KINDS; + for (kind_t k=0; knum_allocated_slabs[k].value, memory_order_relaxed); + *rp++ = (ulong)nas; + ulong nubs = 0; + for (uint i = 0; inum_used_blocks, memory_order_relaxed); + nubs += nub; + } + *rp++ = nubs; + *rp++ = (ulong)nas * num_usable_blocks(k); + } +#if defined NON_SLAB_TRACKING + *rp++ = AL(&hp->num_nonslab_allocations, memory_order_relaxed); +#else + *rp++ = 0; +#endif +} + +// + +#if defined NON_SLAB_TRACKING +// return a snapshot of the current number of nonslab allocations +// which haven't been deallocated +__attribute__((cold)) ulong +__ockl_dm_nna(void) +{ + __global heap_t *hp = get_heap_ptr(); + return AL(&hp->num_nonslab_allocations, memory_order_relaxed); +} +#endif + diff --git a/amd/device-libs/ockl/src/dots.cl b/amd/device-libs/ockl/src/dots.cl new file mode 100644 index 0000000000000..480941b5bbaad --- /dev/null +++ b/amd/device-libs/ockl/src/dots.cl @@ -0,0 +1,193 @@ + +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "ockl.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +__attribute__((target("dot10-insts"), const)) static float amdgcn_fdot2(half2 a, half2 b, float c, bool s) +{ if (s) return __builtin_amdgcn_fdot2(a, b, c, true); + else return __builtin_amdgcn_fdot2(a, b, c, false); } + +__attribute__((target("dot2-insts"), const)) static int amdgcn_sdot2(short2 a, short2 b, int c, bool s) +{ if (s) return __builtin_amdgcn_sdot2(a, b, c, true); + else return __builtin_amdgcn_sdot2(a, b, c, false); } + +__attribute__((target("dot2-insts"), const)) static uint amdgcn_udot2(ushort2 a, ushort2 b, uint c, bool s) +{ if (s) return __builtin_amdgcn_udot2(a, b, c, true); + else return __builtin_amdgcn_udot2(a, b, c, false); } + +__attribute__((target("dot1-insts"), const)) static int amdgcn_sdot4(int a, int b, int c, bool s) +{ if (s) return __builtin_amdgcn_sdot4(a, b, c, true); + else return __builtin_amdgcn_sdot4(a, b, c, false); } + +__attribute__((target("dot7-insts"), const)) static uint amdgcn_udot4(uint a, uint b, uint c, bool s) +{ if (s) return __builtin_amdgcn_udot4(a, b, c, true); + else return __builtin_amdgcn_udot4(a, b, c, false); } + +__attribute__((target("dot1-insts"), const)) static int amdgcn_sdot8(int a, int b, int c, bool s) +{ if (s) return __builtin_amdgcn_sdot8(a, b, c, true); + else return __builtin_amdgcn_sdot8(a, b, c, false); } + +__attribute__((target("dot7-insts"), const)) static uint amdgcn_udot8(uint a, uint b, uint c, bool s) +{ if (s) return __builtin_amdgcn_udot8(a, b, c, true); + else return __builtin_amdgcn_udot8(a, b, c, false); } + + +__attribute__((target("dot8-insts"), const)) static uint amdgcn_sudot4(bool as, uint a, bool bs, uint b, uint c, bool s) +{ + if (!as && !bs && !s) return __builtin_amdgcn_sudot4(false, a, false, b, c, false); + if (!as && !bs && s) return __builtin_amdgcn_sudot4(false, a, false, b, c, true ); + if (!as && bs && !s) return __builtin_amdgcn_sudot4(false, a, true , b, c, false); + if (!as && bs && s) return __builtin_amdgcn_sudot4(false, a, true , b, c, true ); + if ( as && !bs && !s) return __builtin_amdgcn_sudot4(true , a, false, b, c, false); + if ( as && !bs && s) return __builtin_amdgcn_sudot4(true , a, false, b, c, true ); + if ( as && bs && !s) return __builtin_amdgcn_sudot4(true , a, true , b, c, false); + return __builtin_amdgcn_sudot4(true , a, true , b, c, true ); +} + +__attribute__((target("dot8-insts"), const)) static uint amdgcn_sudot8(bool as, uint a, bool bs, uint b, uint c, bool s) +{ + if (!as && !bs && !s) return __builtin_amdgcn_sudot8(false, a, false, b, c, false); + if (!as && !bs && s) return __builtin_amdgcn_sudot8(false, a, false, b, c, true ); + if (!as && bs && !s) return __builtin_amdgcn_sudot8(false, a, true , b, c, false); + if (!as && bs && s) return __builtin_amdgcn_sudot8(false, a, true , b, c, true ); + if ( as && !bs && !s) return __builtin_amdgcn_sudot8(true , a, false, b, c, false); + if ( as && !bs && s) return __builtin_amdgcn_sudot8(true , a, false, b, c, true ); + if ( as && bs && !s) return __builtin_amdgcn_sudot8(true , a, true , b, c, false); + return __builtin_amdgcn_sudot8(true , a, true , b, c, true ); +} + +#define SWDOT __oclc_ISA_version < 9006 || __oclc_ISA_version == 9009 || __oclc_ISA_version == 10100 +#define SWIDOT2 __oclc_ISA_version < 9006 || __oclc_ISA_version == 9009 || __oclc_ISA_version == 10100 || __oclc_ISA_version >= 11000 +#define SUDOT __oclc_ISA_version >= 11000 + +#define AS_INT(X) __builtin_astype(X, int) +#define AS_UINT(X) __builtin_astype(X, uint) +#define ATTR __attribute__((const)) + +ATTR static float +fmuladd(float a, float b, float c) +{ + #pragma OPENCL FP_CONTRACT ON + return a * b + c; +} + +ATTR float +__ockl_fdot2(half2 a, half2 b, float c, bool s) +{ + if (SWDOT) + return fmuladd((float)a.s1, (float)b.s1, fmuladd((float)a.s0, (float)b.s0, c)); + else + return amdgcn_fdot2(a, b, c, true); +} + +ATTR int +__ockl_sdot2(short2 a, short2 b, int c, bool s) +{ + if (SWIDOT2) { + int p0 = (int)a.s0 * (int)b.s0; + int p1 = (int)a.s1 * (int)b.s1; + long r = (long)c + (long)p0 + (long)p1; + + if (s) + return r < -2147483648L ? -2147483648 : + (r > 2147483647L ? 2147483647 : (int)r); + else + return (int)r; + } else { + return amdgcn_sdot2(a, b, c, s); + } +} + +ATTR uint +__ockl_udot2(ushort2 a, ushort2 b, uint c, bool s) +{ + if (SWIDOT2) { + uint p0 = (uint)a.s0 * (uint)b.s0; + uint p1 = (uint)a.s1 * (uint)b.s1; + ulong r = (ulong)c + (ulong)p0 + (ulong)p1; + return (s & (r > (ulong)0xffffffff)) ? 0xffffffff : (uint)r; + } else { + return amdgcn_udot2(a, b, c, s); + } +} + + +ATTR int +__ockl_sdot4(char4 a, char4 b, int c, bool s) +{ + if (SWDOT) { + int t = + (int)a.s0 * (int)b.s0 + + (int)a.s1 * (int)b.s1 + + (int)a.s2 * (int)b.s2 + + (int)a.s3 * (int)b.s3; + return s ? __ockl_add_sat_i32(t, c) : (t + c); + } else { + if (SUDOT) return amdgcn_sudot4(true, AS_INT(a), true, AS_INT(b), c, s); + else return amdgcn_sdot4(AS_INT(a), AS_INT(b), c, s); + } +} + +ATTR uint +__ockl_udot4(uchar4 a, uchar4 b, uint c, bool s) +{ + if (SWDOT) { + uint t = + (uint)a.s0 * (uint)b.s0 + + (uint)a.s1 * (uint)b.s1 + + (uint)a.s2 * (uint)b.s2 + + (uint)a.s3 * (uint)b.s3; + return s ? __ockl_add_sat_u32(t, c) : (t + c); + } else { + return amdgcn_udot4(AS_UINT(a), AS_UINT(b), c, s); + } +} + + +ATTR int +__ockl_sdot8(int a, int b, int c, bool s) +{ + if (SWDOT) { + int t = + ((a << 28) >> 28) * ((b << 28) >> 28) + + ((a << 24) >> 28) * ((b << 24) >> 28) + + ((a << 20) >> 28) * ((b << 20) >> 28) + + ((a << 16) >> 28) * ((b << 16) >> 28) + + ((a << 12) >> 28) * ((b << 12) >> 28) + + ((a << 8) >> 28) * ((b << 8) >> 28) + + ((a << 4) >> 28) * ((b << 4) >> 28) + + ( a >> 28) * ( b >> 28); + return s ? __ockl_add_sat_i32(t, c) : (t + c); + } else { + if (SUDOT) return amdgcn_sudot8(true, a, true, b, c, s); + else return amdgcn_sdot8(a, b, c, s); + } +} + +ATTR uint +__ockl_udot8(uint a, uint b, uint c, bool s) +{ + if (SWDOT) { + uint t = + ( a & 0xf) * ( b & 0xf) + + ((a >> 4) & 0xf) * ((b >> 4) & 0xf) + + ((a >> 8) & 0xf) * ((b >> 8) & 0xf) + + ((a >> 12) & 0xf) * ((b >> 12) & 0xf) + + ((a >> 16) & 0xf) * ((b >> 16) & 0xf) + + ((a >> 20) & 0xf) * ((b >> 20) & 0xf) + + ((a >> 24) & 0xf) * ((b >> 24) & 0xf) + + ((a >> 28) ) * ((b >> 28) ); + return s ? __ockl_add_sat_u32(t, c) : (t + c); + } else { + return amdgcn_udot8(a, b, c, s); + } +} + diff --git a/amd/device-libs/ockl/src/extended-image-intrinsics.ll b/amd/device-libs/ockl/src/extended-image-intrinsics.ll new file mode 100644 index 0000000000000..bf8a9f389bfa4 --- /dev/null +++ b/amd/device-libs/ockl/src/extended-image-intrinsics.ll @@ -0,0 +1,436 @@ +target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" +target triple = "amdgcn-amd-amdhsa" + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_lz_1d_v4f32_f32(float %arg1, <8 x i32> %arg2, <4 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f32(i32 noundef 15, float %arg1, <8 x i32> %arg2, <4 x i32> %arg3, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f32(i32 immarg, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_l_1d_v4f32_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_d_1d_v4f32_f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_lz_2d_v4f32_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_l_2d_v4f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_d_2d_v4f32_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, <8 x i32> %arg7, <4 x i32> %arg8) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, <8 x i32> %arg7, <4 x i32> %arg8, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 immarg, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_lz_3d_v4f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.lz.3d.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.lz.3d.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_l_3d_v4f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.l.3d.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.l.3d.v4f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_d_3d_v4f32_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, <8 x i32> %arg10, <4 x i32> %arg11) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, <8 x i32> %arg10, <4 x i32> %arg11, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f32(i32 immarg, float, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_lz_cube_v4f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.lz.cube.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.lz.cube.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_l_cube_v4f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.l.cube.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.l.cube.v4f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_lz_1darray_v4f32_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.lz.1darray.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.lz.1darray.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_l_1darray_v4f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.l.1darray.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.l.1darray.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_d_1darray_v4f32_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.d.1darray.v4f32.f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.d.1darray.v4f32.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_lz_2darray_v4f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.lz.2darray.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.lz.2darray.v4f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_l_2darray_v4f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.l.2darray.v4f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.l.2darray.v4f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_sample_d_2darray_v4f32_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, <8 x i32> %arg8, <4 x i32> %arg9) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.sample.d.2darray.v4f32.f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, <8 x i32> %arg8, <4 x i32> %arg9, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.sample.d.2darray.v4f32.f32.f32(i32 immarg, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_lz_1d_v4f16_f32(float %arg1, <8 x i32> %arg2, <4 x i32> %arg3) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.lz.1d.v4f16.f32(i32 noundef 15, float %arg1, <8 x i32> %arg2, <4 x i32> %arg3, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.lz.1d.v4f16.f32(i32 immarg, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_l_1d_v4f16_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.l.1d.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.l.1d.v4f16.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_d_1d_v4f16_f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.d.1d.v4f16.f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.d.1d.v4f16.f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_lz_2d_v4f16_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.lz.2d.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.lz.2d.v4f16.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_l_2d_v4f16_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.l.2d.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.l.2d.v4f16.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_d_2d_v4f16_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, <8 x i32> %arg7, <4 x i32> %arg8) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.d.2d.v4f16.f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, <8 x i32> %arg7, <4 x i32> %arg8, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.d.2d.v4f16.f32.f32(i32 immarg, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_lz_3d_v4f16_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.lz.3d.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.lz.3d.v4f16.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_l_3d_v4f16_f32(float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.l.3d.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.l.3d.v4f16.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_d_3d_v4f16_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, <8 x i32> %arg10, <4 x i32> %arg11, i32 %arg13, i32 %arg14) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.d.3d.v4f16.f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, <8 x i32> %arg10, <4 x i32> %arg11, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.d.3d.v4f16.f32.f32(i32 immarg, float, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_lz_cube_v4f16_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.lz.cube.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.lz.cube.v4f16.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_l_cube_v4f16_f32(float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.l.cube.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.l.cube.v4f16.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_lz_1darray_v4f16_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.lz.1darray.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.lz.1darray.v4f16.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_l_1darray_v4f16_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.l.1darray.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.l.1darray.v4f16.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_d_1darray_v4f16_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.d.1darray.v4f16.f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.d.1darray.v4f16.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_lz_2darray_v4f16_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.lz.2darray.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.lz.2darray.v4f16.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_l_2darray_v4f16_f32(float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.l.2darray.v4f16.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.l.2darray.v4f16.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x half> @__llvm_amdgcn_image_sample_d_2darray_v4f16_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, <8 x i32> %arg8, <4 x i32> %arg9) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.d.2darray.v4f16.f32.f32(i32 noundef 15, float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, <8 x i32> %arg8, <4 x i32> %arg9, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x half> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x half> @llvm.amdgcn.image.sample.d.2darray.v4f16.f32.f32(i32 immarg, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_sample_lz_2d_f32_f32(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 noundef 1, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_sample_l_2d_f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.sample.l.2d.f32.f32(i32 noundef 1, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.sample.l.2d.f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_sample_d_2d_f32_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, <8 x i32> %arg7, <4 x i32> %arg8) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.sample.d.2d.f32.f32.f32(i32 noundef 1, float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, <8 x i32> %arg7, <4 x i32> %arg8, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.sample.d.2d.f32.f32.f32(i32 immarg, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_sample_lz_2darray_f32_f32(float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.sample.lz.2darray.f32.f32(i32 noundef 1, float %arg1, float %arg2, float %arg3, <8 x i32> %arg4, <4 x i32> %arg5, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.sample.lz.2darray.f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_sample_l_2darray_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 noundef 1, float %arg1, float %arg2, float %arg3, float %arg4, <8 x i32> %arg5, <4 x i32> %arg6, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected float @__llvm_amdgcn_image_sample_d_2darray_f32_f32_f32(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, <8 x i32> %arg8, <4 x i32> %arg9, i32 %arg11, i32 %arg12) local_unnamed_addr #0 { +bb: + %tmp = tail call float @llvm.amdgcn.image.sample.d.2darray.f32.f32.f32(i32 noundef 1, float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, <8 x i32> %arg8, <4 x i32> %arg9, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret float %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare float @llvm.amdgcn.image.sample.d.2darray.f32.f32.f32(i32 immarg, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_r(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 noundef 1, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_g(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 noundef 2, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_b(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 noundef 4, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nofree norecurse nosync nounwind willreturn memory(read) +define protected <4 x float> @__llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_a(float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4) local_unnamed_addr #0 { +bb: + %tmp = tail call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 noundef 8, float %arg1, float %arg2, <8 x i32> %arg3, <4 x i32> %arg4, i1 noundef false, i32 noundef 0, i32 noundef 0) + ret <4 x float> %tmp +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 + +attributes #0 = { nofree norecurse nosync nounwind willreturn memory(read) "target-features"="+extended-image-insts" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } diff --git a/amd/device-libs/ockl/src/gaaf.cl b/amd/device-libs/ockl/src/gaaf.cl new file mode 100644 index 0000000000000..6509173b3eab9 --- /dev/null +++ b/amd/device-libs/ockl/src/gaaf.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +void +__ockl_atomic_add_noret_f32(float *p, float v) +{ + __opencl_atomic_fetch_add((atomic_float *)p, v, memory_order_relaxed, memory_scope_device); +} + diff --git a/amd/device-libs/ockl/src/hostcall.cl b/amd/device-libs/ockl/src/hostcall.cl new file mode 100644 index 0000000000000..5021d9ea159a5 --- /dev/null +++ b/amd/device-libs/ockl/src/hostcall.cl @@ -0,0 +1,57 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +/** \brief Internal implementation of hostcall. + * + * *** INTERNAL USE ONLY *** + * Internal function, not safe for direct use in user + * code. Application kernels must only use __ockl_hostcall_preview() + * defined below. + */ +__attribute__((cold)) +extern long2 +__ockl_hostcall_internal(void *buffer, uint service_id, + ulong arg0, ulong arg1, ulong arg2, ulong arg3, + ulong arg4, ulong arg5, ulong arg6, ulong arg7); + +/** \brief Submit a wave-wide hostcall packet. + * \param service_id The service to be invoked on the host. + * \param arg0 Up to eight parameters (arg0..arg7) + * \return Two 64-bit values. + * + * The hostcall is executed for all active threads in the + * wave. #service_id must be uniform across the active threads, + * otherwise behaviour is undefined. The service parameters may be + * different for each active thread, and correspondingly, the + * returned values are also different. + * + * The contents of the input parameters and the return values are + * defined by the service being invoked. + * + * *** PREVIEW FEATURE *** + * This is a feature preview and considered alpha quality only; + * behaviour may vary between ROCm releases. Device code that invokes + * hostcall can be launched only on the ROCm release that it was + * compiled for, otherwise behaviour is undefined. + */ +long2 +__ockl_hostcall_preview(uint service_id, + ulong arg0, ulong arg1, ulong arg2, ulong arg3, + ulong arg4, ulong arg5, ulong arg6, ulong arg7) +{ + void *buffer; + if (__oclc_ABI_version < 500) { + buffer = (__global void *)((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[3]; + } else { + buffer = (__global void *)((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[10]; + } + + return __ockl_hostcall_internal(buffer, service_id, arg0, arg1, arg2, arg3, + arg4, arg5, arg6, arg7); +} diff --git a/amd/device-libs/ockl/src/hostcall_impl.cl b/amd/device-libs/ockl/src/hostcall_impl.cl new file mode 100644 index 0000000000000..325ee8e45c414 --- /dev/null +++ b/amd/device-libs/ockl/src/hostcall_impl.cl @@ -0,0 +1,299 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl_hsa.h" + +#pragma OPENCL EXTENSION cl_khr_int64_base_atomics : enable +#pragma OPENCL EXTENSION cl_khr_int64_extended_atomics : enable + +#define AC(P, E, V, O, R, S) \ + __opencl_atomic_compare_exchange_strong(P, E, V, O, R, S) +#define AL(P, O, S) __opencl_atomic_load(P, O, S) +#define AF(K, P, V, O, S) __opencl_atomic_fetch_##K(P, V, O, S) + +typedef enum { STATUS_SUCCESS, STATUS_BUSY } status_t; + +typedef enum { + CONTROL_OFFSET_READY_FLAG = 0, + CONTROL_OFFSET_RESERVED0 = 1, +} control_offset_t; + +typedef enum { + CONTROL_WIDTH_READY_FLAG = 1, + CONTROL_WIDTH_RESERVED0 = 31, +} control_width_t; + +typedef struct { + ulong next; + ulong activemask; + uint service; + uint control; +} header_t; + +typedef struct { + // 64 slots of 8 ulongs each + ulong slots[64][8]; +} payload_t; + +// Note: Hostcall buffer struct defined here is not an exact +// match of runtime buffer layout but matches its prefix that +// this code tries to access. +typedef struct { + __global header_t *headers; + __global payload_t *payloads; + hsa_signal_t doorbell; + ulong free_stack; + ulong ready_stack; + ulong index_mask; +} buffer_t; + +static void +send_signal(hsa_signal_t signal) +{ + __ockl_hsa_signal_add(signal, 1, __ockl_memory_order_release); +} + +static __global header_t * +get_header(__global buffer_t *buffer, ulong ptr) +{ + return buffer->headers + (ptr & buffer->index_mask); +} + +static __global payload_t * +get_payload(__global buffer_t *buffer, ulong ptr) +{ + return buffer->payloads + (ptr & buffer->index_mask); +} + +static uint +get_control_field(uint control, uint offset, uint width) +{ + return (control >> offset) & ((1 << width) - 1); +} + +static uint +get_ready_flag(uint control) +{ + return get_control_field(control, CONTROL_OFFSET_READY_FLAG, + CONTROL_WIDTH_READY_FLAG); +} + +static uint +set_control_field(uint control, uint offset, uint width, uint value) +{ + uint mask = ~(((1 << width) - 1) << offset); + return (control & mask) | (value << offset); +} + +static uint +set_ready_flag(uint control) +{ + return set_control_field(control, CONTROL_OFFSET_READY_FLAG, + CONTROL_WIDTH_READY_FLAG, 1); +} + +static ulong +pop(__global ulong *top, __global buffer_t *buffer) +{ + ulong F = AL((__global atomic_ulong *)top, memory_order_acquire, + memory_scope_all_svm_devices); + // F is guaranteed to be non-zero, since there are at least as + // many packets as there are waves, and each wave can hold at most + // one packet. + while (true) { + __global header_t *P = get_header(buffer, F); + ulong N = AL((__global atomic_ulong *)&P->next, memory_order_relaxed, + memory_scope_all_svm_devices); + if (AC((__global atomic_ulong *)top, &F, N, memory_order_acquire, + memory_order_relaxed, memory_scope_all_svm_devices)) { + break; + } + __builtin_amdgcn_s_sleep(1); + } + + return F; +} + +/** \brief Use the first active lane to get a free packet and + * broadcast to the whole wave. + */ +static ulong +pop_free_stack(__global buffer_t *buffer, uint me, uint low) +{ + ulong packet_ptr = 0; + if (me == low) { + packet_ptr = pop(&buffer->free_stack, buffer); + } + + uint ptr_lo = packet_ptr; + uint ptr_hi = packet_ptr >> 32; + ptr_lo = __builtin_amdgcn_readfirstlane(ptr_lo); + ptr_hi = __builtin_amdgcn_readfirstlane(ptr_hi); + + return ((ulong)ptr_hi << 32) | ptr_lo; +} + +static void +push(__global ulong *top, ulong ptr, __global buffer_t *buffer) +{ + ulong F = AL((__global const atomic_ulong *)top, memory_order_relaxed, + memory_scope_all_svm_devices); + __global header_t *P = get_header(buffer, ptr); + + while (true) { + P->next = F; + if (AC((__global atomic_ulong *)top, &F, ptr, memory_order_release, + memory_order_relaxed, memory_scope_all_svm_devices)) + break; + __builtin_amdgcn_s_sleep(1); + } +} + +/** \brief Use the first active lane in a wave to submit a ready + * packet and signal the host. + */ +static void +push_ready_stack(__global buffer_t *buffer, ulong ptr, uint me, uint low) +{ + if (me == low) { + push(&buffer->ready_stack, ptr, buffer); + send_signal(buffer->doorbell); + } +} + +static ulong +inc_ptr_tag(ulong ptr, ulong index_mask) +{ + // Unit step for the tag. + ulong inc = index_mask + 1; + ptr += inc; + // When the tag for index 0 wraps, increment the tag. + return ptr == 0 ? inc : ptr; +} + +/** \brief Return the packet after incrementing the ABA tag + */ +static void +return_free_packet(__global buffer_t *buffer, ulong ptr, uint me, uint low) +{ + if (me == low) { + ptr = inc_ptr_tag(ptr, buffer->index_mask); + push(&buffer->free_stack, ptr, buffer); + } +} + +static void +fill_packet(__global header_t *header, __global payload_t *payload, + uint service_id, ulong arg0, ulong arg1, ulong arg2, ulong arg3, + ulong arg4, ulong arg5, ulong arg6, ulong arg7, uint me, uint low) +{ + ulong active = __builtin_amdgcn_read_exec(); + if (me == low) { + header->service = service_id; + header->activemask = active; + uint control = set_ready_flag(0); + header->control = control; + } + + __global ulong *ptr = payload->slots[me]; + ptr[0] = arg0; + ptr[1] = arg1; + ptr[2] = arg2; + ptr[3] = arg3; + ptr[4] = arg4; + ptr[5] = arg5; + ptr[6] = arg6; + ptr[7] = arg7; +} + +/** \brief Wait for the host response and return the first two ulong + * entries per workitem. + * + * After the packet is submitted in READY state, the wave spins until + * the host changes the state to DONE. Each workitem reads the first + * two ulong elements in its slot and returns this. + */ +static long2 +get_return_value(__global header_t *header, __global payload_t *payload, + uint me, uint low) +{ + // The while loop needs to be executed by all active + // lanes. Otherwise, later reads from ptr are performed only by + // the first thread, while other threads reuse a value cached from + // previous operations. The use of readfirstlane in the while loop + // prevents this reordering. + // + // In the absence of the readfirstlane, only one thread has a + // sequenced-before relation from the atomic load on + // header->control to the ordinary loads on ptr. As a result, the + // compiler is free to reorder operations in such a way that the + // ordinary loads are performed only by the first thread. The use + // of readfirstlane provides a stronger code-motion barrier, and + // it effectively "spreads out" the sequenced-before relation to + // the ordinary stores in other threads too. + while (true) { + uint ready_flag = 1; + if (me == low) { + uint control = + AL((__global const atomic_uint *)&header->control, + memory_order_acquire, memory_scope_all_svm_devices); + ready_flag = get_ready_flag(control); + } + ready_flag = __builtin_amdgcn_readfirstlane(ready_flag); + if (ready_flag == 0) + break; + __builtin_amdgcn_s_sleep(1); + } + + __global ulong *ptr = (__global ulong *)(payload->slots + me); + ulong value0 = *ptr++; + ulong value1 = *ptr; + + long2 retval = {value0, value1}; + return retval; +} + +/** \brief The implementation that should be hidden behind an ABI + * + * The transaction is a wave-wide operation, where the service_id + * must be uniform, but the parameters are different for each + * workitem. Parameters from all active lanes are written into a + * hostcall packet. The hostcall blocks until the host processes the + * request, and returns the response it receiveds. + * + * TODO: This function and everything above it should eventually move + * to a separate library that is loaded by the language runtime. The + * function itself will be exposed as an orindary function symbol to + * be linked into kernel objects that are loaded after this library. + * + * *** INTERNAL USE ONLY *** + * Internal function, not safe for direct use in user + * code. Application kernels must only use __ockl_hostcall_preview() + * defined elsewhere. + * + */ +long2 +__ockl_hostcall_internal(void *_buffer, uint service_id, ulong arg0, ulong arg1, + ulong arg2, ulong arg3, ulong arg4, ulong arg5, + ulong arg6, ulong arg7) +{ + uint me = __ockl_lane_u32(); + uint low = __builtin_amdgcn_readfirstlane(me); + + __global buffer_t *buffer = (__global buffer_t *)_buffer; + ulong packet_ptr = pop_free_stack(buffer, me, low); + __global header_t *header = get_header(buffer, packet_ptr); + __global payload_t *payload = get_payload(buffer, packet_ptr); + + fill_packet(header, payload, service_id, arg0, arg1, arg2, arg3, arg4, arg5, + arg6, arg7, me, low); + push_ready_stack(buffer, packet_ptr, me, low); + + long2 retval = get_return_value(header, payload, me, low); + return_free_packet(buffer, packet_ptr, me, low); + return retval; +} diff --git a/amd/device-libs/ockl/src/hsaqs.cl b/amd/device-libs/ockl/src/hsaqs.cl new file mode 100644 index 0000000000000..f98ef33a4f79b --- /dev/null +++ b/amd/device-libs/ockl/src/hsaqs.cl @@ -0,0 +1,186 @@ + +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "ockl_hsa.h" + +#pragma OPENCL EXTENSION cl_khr_int64_base_atomics : enable +#pragma OPENCL EXTENSION cl_khr_int64_extended_atomics : enable + +#define ATTR + +#define AL(T,P,O,S) __opencl_atomic_load(P,O,S) +#define AS(P,V,O,S) __opencl_atomic_store(P,V,O,S) +#define AF(T,K,P,V,O,S) __opencl_atomic_fetch_##K(P,V,O,S) +#define AX(T,P,V,O,S) __opencl_atomic_exchange(P,V,O,S) +#define AC(P,E,V,O,R,S) __opencl_atomic_compare_exchange_strong(P,E,V,O,R,S) + +// +// HSA queue ops +// + +ATTR ulong +OCKL_MANGLE_T(hsa_queue,load_read_index)(const __global hsa_queue_t *queue, __ockl_memory_order mem_order) +{ + const __global amd_queue_t *q = (const __global amd_queue_t *)queue; + return AL(ulong, (__global atomic_ulong *)&q->read_dispatch_id, mem_order, memory_scope_all_svm_devices); +} + +ATTR ulong +OCKL_MANGLE_T(hsa_queue,load_write_index)(const __global hsa_queue_t *queue, __ockl_memory_order mem_order) +{ + const __global amd_queue_t *q = (const __global amd_queue_t *)queue; + return AL(ulong, (__global atomic_ulong *)&q->write_dispatch_id, mem_order, memory_scope_all_svm_devices); +} + +ATTR ulong +OCKL_MANGLE_T(hsa_queue,add_write_index)(__global hsa_queue_t *queue, ulong value, __ockl_memory_order mem_order) +{ + __global amd_queue_t *q = (__global amd_queue_t *)queue; + return AF(ulong, add, (__global atomic_ulong *)&q->write_dispatch_id, value, mem_order, memory_scope_all_svm_devices); +} + +ATTR ulong +OCKL_MANGLE_T(hsa_queue,cas_write_index)(__global hsa_queue_t *queue, ulong expected, ulong value, __ockl_memory_order mem_order) +{ + __global amd_queue_t *q = (__global amd_queue_t *)queue; + ulong e = expected; + AC((__global atomic_ulong *)&q->write_dispatch_id, &e, value, mem_order, memory_order_relaxed, memory_scope_all_svm_devices); + return e; +} + +ATTR void +OCKL_MANGLE_T(hsa_queue,store_write_index)(__global hsa_queue_t *queue, ulong value, __ockl_memory_order mem_order) +{ + __global amd_queue_t *q = (__global amd_queue_t *)queue; + AS((__global atomic_ulong *)&q->write_dispatch_id, value, mem_order, memory_scope_all_svm_devices); +} + +// +// HSA signal ops +// + +static ATTR void +update_mbox(const __global amd_signal_t *sig) +{ + __global atomic_ulong *mb = (__global atomic_ulong *)sig->event_mailbox_ptr; + if (mb) { + uint id = sig->event_id; + AS(mb, id, memory_order_release, memory_scope_all_svm_devices); + uint mid = id & + (__oclc_ISA_version < 9000 ? 0xff : + (__oclc_ISA_version < 10000 ? 0xffffff : + (__oclc_ISA_version < 11000 ? 0x7fffff : 0xffffff))); + __builtin_amdgcn_s_sendmsg(1 | (0 << 4), __builtin_amdgcn_readfirstlane(mid)); + } +} + +ATTR long +OCKL_MANGLE_T(hsa_signal,load)(const hsa_signal_t sig, __ockl_memory_order mem_order) +{ + const __global amd_signal_t *s = (const __global amd_signal_t *)sig.handle; + return AL(long, (__global atomic_long *)&s->value, mem_order, memory_scope_all_svm_devices); +} + +ATTR void +OCKL_MANGLE_T(hsa_signal,add)(hsa_signal_t sig, long value, __ockl_memory_order mem_order) +{ + __global amd_signal_t *s = (__global amd_signal_t *)sig.handle; + AF(long, add, (__global atomic_long *)&s->value, value, mem_order, memory_scope_all_svm_devices); + update_mbox(s); +} + +ATTR void +OCKL_MANGLE_T(hsa_signal,and)(hsa_signal_t sig, long value, __ockl_memory_order mem_order) +{ + __global amd_signal_t *s = (__global amd_signal_t *)sig.handle; + AF(long, and, (__global atomic_long *)&s->value, value, mem_order, memory_scope_all_svm_devices); + update_mbox(s); +} + +ATTR void +OCKL_MANGLE_T(hsa_signal,or)(hsa_signal_t sig, long value, __ockl_memory_order mem_order) +{ + __global amd_signal_t *s = (__global amd_signal_t *)sig.handle; + AF(long, or, (__global atomic_long *)&s->value, value, mem_order, memory_scope_all_svm_devices); + update_mbox(s); +} + +ATTR void +OCKL_MANGLE_T(hsa_signal,xor)(hsa_signal_t sig, long value, __ockl_memory_order mem_order) +{ + __global amd_signal_t *s = (__global amd_signal_t *)sig.handle; + AF(long, xor, (__global atomic_long *)&s->value, value, mem_order, memory_scope_all_svm_devices); + update_mbox(s); +} + +ATTR long +OCKL_MANGLE_T(hsa_signal,exchange)(hsa_signal_t sig, long value, __ockl_memory_order mem_order) +{ + __global amd_signal_t *s = (__global amd_signal_t *)sig.handle; + long ret = AX(long, (__global atomic_long *)&s->value, value, mem_order, memory_scope_all_svm_devices); + update_mbox(s); + return ret; +} + +ATTR void +OCKL_MANGLE_T(hsa_signal,subtract)(hsa_signal_t sig, long value, __ockl_memory_order mem_order) +{ + __global amd_signal_t *s = (__global amd_signal_t *)sig.handle; + AF(long, sub, (__global atomic_long *)&s->value, value, mem_order, memory_scope_all_svm_devices); + update_mbox(s); +} + +ATTR long +OCKL_MANGLE_T(hsa_signal,cas)(hsa_signal_t sig, long expected, long value, __ockl_memory_order mem_order) +{ + __global amd_signal_t *s = (__global amd_signal_t *)sig.handle; + long e = expected; + if (AC((__global atomic_long *)&s->value, &e, value, mem_order, memory_order_relaxed, memory_scope_all_svm_devices)) + update_mbox(s); + return e; +} + +ATTR void +OCKL_MANGLE_T(hsa_signal,store)(hsa_signal_t sig, long value, __ockl_memory_order mem_order) +{ + __global amd_signal_t *s = (__global amd_signal_t *)sig.handle; + if (s->kind == AMD_SIGNAL_KIND_USER) { + AS((__global atomic_long *)&s->value, value, mem_order, memory_scope_all_svm_devices); + update_mbox(s); + } else if (__oclc_ISA_version >= 9000) { + // Hardware doorbell supports AQL semantics. + AS((__global atomic_ulong *)s->hardware_doorbell_ptr, (ulong)value, memory_order_release, memory_scope_all_svm_devices); + } else { + + { + __global amd_queue_t * q = s->queue_ptr; + __global atomic_uint *lp = (__global atomic_uint *)&q->legacy_doorbell_lock; + uint e = 0; + while (!AC(lp, &e, (uint)1, memory_order_acquire, memory_order_relaxed, memory_scope_all_svm_devices)) { + __builtin_amdgcn_s_sleep(1); + e = 0; + } + + ulong legacy_dispatch_id = value + 1; + + if (legacy_dispatch_id > q->max_legacy_doorbell_dispatch_id_plus_1) { + AS((__global atomic_ulong *)&q->max_legacy_doorbell_dispatch_id_plus_1, legacy_dispatch_id, memory_order_relaxed, memory_scope_all_svm_devices); + + if (__oclc_ISA_version < 8000) { + legacy_dispatch_id = (ulong)(((uint)legacy_dispatch_id & ((q->hsa_queue.size << 1) - 1)) * 16); + } + + *s->legacy_hardware_doorbell_ptr = (uint)legacy_dispatch_id; + } + + AS(lp, 0, memory_order_release, memory_scope_all_svm_devices); + } + } +} + diff --git a/amd/device-libs/ockl/src/image.cl b/amd/device-libs/ockl/src/image.cl new file mode 100644 index 0000000000000..ca30656da8773 --- /dev/null +++ b/amd/device-libs/ockl/src/image.cl @@ -0,0 +1,1339 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" +#include "oclc.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define EII() __oclc_ISA_version != 9010 + +#define RATTR __attribute__((pure)) +#define ERATTR __attribute__((pure, target("extended-image-insts"))) +#define WATTR +#define GATTR __attribute__((const)) + + +// Buffer Load/Store +// Cache policy is dropped since it's unused and isn't enforced to be a constant +// FIXME: Really should have builtins for these. +extern __attribute__((pure)) float4 __llvm_amdgcn_struct_buffer_load_format_v4f32(uint4 rsrc, uint vindex, uint voffset, uint soffset); +extern __attribute__((pure)) half4 __llvm_amdgcn_struct_buffer_load_format_v4f16(uint4 rsrc, uint vindex, uint voffset, uint soffset); +extern void __llvm_amdgcn_struct_buffer_store_format_v4f32(float4 vdata, uint4 rsrc, uint vindex, uint voffset, uint soffset); +extern void __llvm_amdgcn_struct_buffer_store_format_v4f16( half4 vdata, uint4 rsrc, uint vindex, uint voffset, uint soffset); + +// Image load, store, sample, gather +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_1d_v4f32_i32(uint ix, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_2d_v4f32_i32(uint ix, uint iy, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_3d_v4f32_i32(uint ix, uint iy, uint iz, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_cube_v4f32_i32(uint ix, uint iy, uint iface, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_1darray_v4f32_i32(uint ix, uint islice, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_2darray_v4f32_i32(uint ix, uint iy, uint islice, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_mip_1d_v4f32_i32(uint ix, uint imip, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_mip_2d_v4f32_i32(uint ix, uint iy, uint imip, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_mip_3d_v4f32_i32(uint ix, uint iy, uint iz, uint imip, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_mip_cube_v4f32_i32(uint ix, uint iy, uint iface, uint imip, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_mip_1darray_v4f32_i32(uint ix, uint islice, uint imip, uint8 t); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_load_mip_2darray_v4f32_i32(uint ix, uint iy, uint islice, uint imip, uint8 t); + +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_1d_v4f16_i32(uint ix, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_2d_v4f16_i32(uint ix, uint iy, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_3d_v4f16_i32(uint ix, uint iy, uint iz, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_cube_v4f16_i32(uint ix, uint iy, uint iface, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_1darray_v4f16_i32(uint ix, uint islice, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_2darray_v4f16_i32(uint ix, uint iy, uint islice, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_mip_1d_v4f16_i32(uint ix, uint imip, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_mip_2d_v4f16_i32(uint ix, uint iy, uint imip, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_mip_3d_v4f16_i32(uint ix, uint iy, uint iz, uint imip, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_mip_cube_v4f16_i32(uint ix, uint iy, uint iface, uint imip, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_mip_1darray_v4f16_i32(uint ix, uint islice, uint imip, uint8 t); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_load_mip_2darray_v4f16_i32(uint ix, uint iy, uint islice, uint imip, uint8 t); + +extern __attribute__((pure)) float __llvm_amdgcn_image_load_2d_f32_i32(uint ix, uint iy, uint8 t); +extern __attribute__((pure)) float __llvm_amdgcn_image_load_2darray_f32_i32(uint ix, uint iy, uint islice, uint8 t); +extern __attribute__((pure)) float __llvm_amdgcn_image_load_mip_2d_f32_i32(uint ix, uint iy, uint imip, uint8 t); +extern __attribute__((pure)) float __llvm_amdgcn_image_load_mip_2darray_f32_i32(uint ix, uint iy, uint islice, uint imip, uint8 t); + +extern void __llvm_amdgcn_image_store_1d_v4f32_i32(float4 pix, uint ix, uint8 t); +extern void __llvm_amdgcn_image_store_2d_v4f32_i32(float4 pix, uint ix, uint iy, uint8 t); +extern void __llvm_amdgcn_image_store_3d_v4f32_i32(float4 pix, uint ix, uint iy, uint iz, uint8 t); +extern void __llvm_amdgcn_image_store_cube_v4f32_i32(float4 pix, uint ix, uint iy, uint iface, uint8 t); +extern void __llvm_amdgcn_image_store_1darray_v4f32_i32(float4 pix, uint ix, uint islice, uint8 t); +extern void __llvm_amdgcn_image_store_2darray_v4f32_i32(float4 pix, uint ix, uint iy, uint islice, uint8 t); +extern void __llvm_amdgcn_image_store_mip_1d_v4f32_i32(float4 pix, uint ix, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_2d_v4f32_i32(float4 pix, uint ix, uint iy, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_3d_v4f32_i32(float4 pix, uint ix, uint iy, uint iz, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_cube_v4f32_i32(float4 pix, uint ix, uint iy, uint iface, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_1darray_v4f32_i32(float4 pix, uint ix, uint islice, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_2darray_v4f32_i32(float4 pix, uint ix, uint iy, uint islice, uint imip, uint8 t); + +extern void __llvm_amdgcn_image_store_1d_v4f16_i32(half4 pix, uint ix, uint8 t); +extern void __llvm_amdgcn_image_store_2d_v4f16_i32(half4 pix, uint ix, uint iy, uint8 t); +extern void __llvm_amdgcn_image_store_3d_v4f16_i32(half4 pix, uint ix, uint iy, uint iz, uint8 t); +extern void __llvm_amdgcn_image_store_cube_v4f16_i32(half4 pix, uint ix, uint iy, uint iface, uint8 t); +extern void __llvm_amdgcn_image_store_1darray_v4f16_i32(half4 pix, uint ix, uint islice, uint8 t); +extern void __llvm_amdgcn_image_store_2darray_v4f16_i32(half4 pix, uint ix, uint iy, uint islice, uint8 t); +extern void __llvm_amdgcn_image_store_mip_1d_v4f16_i32(half4 pix, uint ix, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_2d_v4f16_i32(half4 pix, uint ix, uint iy, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_3d_v4f16_i32(half4 pix, uint ix, uint iy, uint iz, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_cube_v4f16_i32(half4 pix, uint ix, uint iy, uint iface, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_1darray_v4f16_i32(half4 pix, uint ix, uint islice, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_2darray_v4f16_i32(half4 pix, uint ix, uint iy, uint islice, uint imip, uint8 t); + +extern void __llvm_amdgcn_image_store_2d_f32_i32(float pix, uint ix, uint iy, uint8 t); +extern void __llvm_amdgcn_image_store_2darray_f32_i32(float pix, uint ix, uint iy, uint islice, uint8 t); +extern void __llvm_amdgcn_image_store_mip_2d_f32_i32(float pix, uint ix, uint iy, uint imip, uint8 t); +extern void __llvm_amdgcn_image_store_mip_2darray_f32_i32(float pix, uint ix, uint iy, uint islice, uint imip, uint8 t); + +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_1d_v4f32_f32(float x, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_lz_1d_v4f32_f32(float x, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_l_1d_v4f32_f32(float x, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_d_1d_v4f32_f32_f32(float dxdh, float dxdv, float x, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_2d_v4f32_f32(float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_lz_2d_v4f32_f32(float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_l_2d_v4f32_f32(float x, float y, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_d_2d_v4f32_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_3d_v4f32_f32(float x, float y, float z, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_lz_3d_v4f32_f32(float x, float y, float z, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_l_3d_v4f32_f32(float x, float y, float z, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_d_3d_v4f32_f32_f32(float dxdh, float dydh, float dzdh, float dxdv, float dydv, float dzdv, float x, float y, float z, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_cube_v4f32_f32(float x, float y, float face, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_lz_cube_v4f32_f32(float x, float y, float face, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_l_cube_v4f32_f32(float x, float y, float face, float lod, uint8 t, uint4 s); + +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_1darray_v4f32_f32(float x, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_lz_1darray_v4f32_f32(float x, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_l_1darray_v4f32_f32(float x, float slice, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_d_1darray_v4f32_f32_f32(float dxdh, float dxdv, float x, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_2darray_v4f32_f32(float x, float y, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_lz_2darray_v4f32_f32(float x, float y, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_l_2darray_v4f32_f32(float x, float y, float slice, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_sample_d_2darray_v4f32_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, float slice, uint8 t, uint4 s); + +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_1d_v4f16_f32(float x, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_lz_1d_v4f16_f32(float x, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_l_1d_v4f16_f32(float x, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_d_1d_v4f16_f32_f32(float dxdh, float dxdv, float x, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_2d_v4f16_f32(float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_lz_2d_v4f16_f32(float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_l_2d_v4f16_f32(float x, float y, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_d_2d_v4f16_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_3d_v4f16_f32(float x, float y, float z, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_lz_3d_v4f16_f32(float x, float y, float z, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_l_3d_v4f16_f32(float x, float y, float z, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_d_3d_v4f16_f32_f32(float dxdh, float dydh, float dzdh, float dxdv, float dydv, float dzdv, float x, float y, float z, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_cube_v4f16_f32(float x, float y, float face, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_lz_cube_v4f16_f32(float x, float y, float face, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_l_cube_v4f16_f32(float x, float y, float face, float lod, uint8 t, uint4 s); + +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_1darray_v4f16_f32(float x, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_lz_1darray_v4f16_f32(float x, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_l_1darray_v4f16_f32(float x, float slice, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_d_1darray_v4f16_f32_f32(float dxdh, float dxdv, float x, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_2darray_v4f16_f32(float x, float y, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_lz_2darray_v4f16_f32(float x, float y, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_l_2darray_v4f16_f32(float x, float y, float slice, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) half4 __llvm_amdgcn_image_sample_d_2darray_v4f16_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, float slice, uint8 t, uint4 s); + +extern __attribute__((pure)) float __llvm_amdgcn_image_sample_2d_f32_f32(float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) float __llvm_amdgcn_image_sample_lz_2d_f32_f32(float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) float __llvm_amdgcn_image_sample_l_2d_f32_f32(float x, float y, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) float __llvm_amdgcn_image_sample_d_2d_f32_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) float __llvm_amdgcn_image_sample_2darray_f32_f32(float x, float y, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) float __llvm_amdgcn_image_sample_lz_2darray_f32_f32(float x, float y, float slice, uint8 t, uint4 s); +extern __attribute__((pure)) float __llvm_amdgcn_image_sample_l_2darray_f32_f32(float x, float y, float slice, float lod, uint8 t, uint4 s); +extern __attribute__((pure)) float __llvm_amdgcn_image_sample_d_2darray_f32_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, float slice, uint8 t, uint4 s); + +extern __attribute__((pure)) float4 __llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_r(float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_g(float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_b(float x, float y, uint8 t, uint4 s); +extern __attribute__((pure)) float4 __llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_a(float x, float y, uint8 t, uint4 s); + + +// TSHARP/SSHARP access +#define FIELD(P,B,W) ((P[B >> 5] >> (B & 0x1f)) & ((1 << W) - 1)) +#define WORD(P,I) P[I] +#define LOAD_TSHARP(I) *(__constant uint8 *)I +#define LOAD_VSHARP(I) *(__constant uint4 *)I +#define LOAD_SSHARP(S) *(__constant uint4 *)S + +// Adjustments for hardware precision limits +#define ADJUST_X(C,I,S) do { \ + float _w = (float)WORD(I,10); \ + float _p = FIELD(S,15,1) ? 1.0f : _w; \ + float _x = __builtin_floorf(C * _p) * __builtin_amdgcn_rcpf(_p); \ + C = FIELD(S,84,1) ? C : _x; \ +} while (0) + +#define ADJUST_XY(C,I,S) do { \ + float _w = (float)WORD(I,10); \ + float _h = (float)(FIELD(I,78,14) + 1U); \ + bool _f = FIELD(S,15,1); \ + float _p = _f ? 1.0f : _w; \ + float _q = _f ? 1.0f : _h; \ + float _x = __builtin_floorf(C.x * _p) * __builtin_amdgcn_rcpf(_p); \ + float _y = __builtin_floorf(C.y * _q) * __builtin_amdgcn_rcpf(_q); \ + bool _m = FIELD(S,84,1); \ + C.x = _m ? C.x : _x; \ + C.y = _m ? C.y : _y; \ +} while (0) + +#define ADJUST_XYZ(C,I,S) do { \ + float _w = (float)WORD(I,10); \ + float _h = (float)(FIELD(I,78,14) + 1U); \ + float _d = (float)(FIELD(I, 128, 13) + 1U); \ + bool _f = FIELD(S,15,1); \ + float _p = _f ? 1.0f : _w; \ + float _q = _f ? 1.0f : _h; \ + float _r = _f ? 1.0f : _d; \ + float _x = __builtin_floorf(C.x * _p) * __builtin_amdgcn_rcpf(_p); \ + float _y = __builtin_floorf(C.y * _q) * __builtin_amdgcn_rcpf(_q); \ + float _z = __builtin_floorf(C.z * _r) * __builtin_amdgcn_rcpf(_r); \ + bool _m = FIELD(S,84,1); \ + C.x = _m ? C.x : _x; \ + C.y = _m ? C.y : _y; \ + C.z = _m ? C.z : _z; \ +} while (0) + +GATTR +static float fmuladd_f32(float a, float b, float c) +{ + #pragma OPENCL FP_CONTRACT ON + return a * b + c; +} + +#define LS_ARRAY_FACE(I,F) (6 * (((I) << 8) >> 8) + (F)) +#define SAMPLE_ARRAY_FACE(I, F) fmuladd_f32(__builtin_rintf(I), 8.0f, F) + +#define CUBE_PREP(C) do { \ + float _vx = C.x; \ + float _vy = C.y; \ + float _vz = C.z; \ + float _rl = __builtin_amdgcn_rcpf(__builtin_amdgcn_cubema(_vx, _vy, _vz)); \ + C.x = fmuladd_f32(__builtin_amdgcn_cubesc(_vx, _vy, _vz), _rl, 0.5f); \ + C.y = fmuladd_f32(__builtin_amdgcn_cubetc(_vx, _vy, _vz), _rl, 0.5f); \ + C.z = __builtin_amdgcn_cubeid(_vx, _vy, _vz); \ +} while (0) + +RATTR static float4 my_image_load_1d_v4f32_i32(uint ix, uint8 t) +{ return __llvm_amdgcn_image_load_1d_v4f32_i32(ix, t); } +RATTR static float4 my_image_load_2d_v4f32_i32(uint ix, uint iy, uint8 t) +{ return __llvm_amdgcn_image_load_2d_v4f32_i32(ix, iy, t); } +RATTR static float4 my_image_load_3d_v4f32_i32(uint ix, uint iy, uint iz, uint8 t) +{ return __llvm_amdgcn_image_load_3d_v4f32_i32(ix, iy, iz, t); } +RATTR static float4 my_image_load_cube_v4f32_i32(uint ix, uint iy, uint iface, uint8 t) +{ return __llvm_amdgcn_image_load_cube_v4f32_i32(ix, iy, iface, t); } +RATTR static float4 my_image_load_1darray_v4f32_i32(uint ix, uint islice, uint8 t) +{ return __llvm_amdgcn_image_load_1darray_v4f32_i32(ix, islice, t); } +RATTR static float4 my_image_load_2darray_v4f32_i32(uint ix, uint iy, uint islice, uint8 t) +{ return __llvm_amdgcn_image_load_2darray_v4f32_i32(ix, iy, islice, t); } +RATTR static float4 my_image_load_mip_1d_v4f32_i32(uint ix, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_1d_v4f32_i32(ix, imip, t); } +RATTR static float4 my_image_load_mip_2d_v4f32_i32(uint ix, uint iy, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_2d_v4f32_i32(ix, iy, imip, t); } +RATTR static float4 my_image_load_mip_3d_v4f32_i32(uint ix, uint iy, uint iz, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_3d_v4f32_i32(ix, iy, iz, imip, t); } +RATTR static float4 my_image_load_mip_cube_v4f32_i32(uint ix, uint iy, uint iface, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_cube_v4f32_i32(ix, iy, iface, imip, t); } +RATTR static float4 my_image_load_mip_1darray_v4f32_i32(uint ix, uint islice, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_1darray_v4f32_i32(ix, islice, imip, t); } +RATTR static float4 my_image_load_mip_2darray_v4f32_i32(uint ix, uint iy, uint islice, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_2darray_v4f32_i32(ix, iy, islice, imip, t); } + +RATTR static half4 my_image_load_1d_v4f16_i32(uint ix, uint8 t) +{ return __llvm_amdgcn_image_load_1d_v4f16_i32(ix, t); } +RATTR static half4 my_image_load_2d_v4f16_i32(uint ix, uint iy, uint8 t) +{ return __llvm_amdgcn_image_load_2d_v4f16_i32(ix, iy, t); } +RATTR static half4 my_image_load_3d_v4f16_i32(uint ix, uint iy, uint iz, uint8 t) +{ return __llvm_amdgcn_image_load_3d_v4f16_i32(ix, iy, iz, t); } +RATTR static half4 my_image_load_cube_v4f16_i32(uint ix, uint iy, uint iface, uint8 t) +{ return __llvm_amdgcn_image_load_cube_v4f16_i32(ix, iy, iface, t); } +RATTR static half4 my_image_load_1darray_v4f16_i32(uint ix, uint islice, uint8 t) +{ return __llvm_amdgcn_image_load_1darray_v4f16_i32(ix, islice, t); } +RATTR static half4 my_image_load_2darray_v4f16_i32(uint ix, uint iy, uint islice, uint8 t) +{ return __llvm_amdgcn_image_load_2darray_v4f16_i32(ix, iy, islice, t); } +RATTR static half4 my_image_load_mip_1d_v4f16_i32(uint ix, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_1d_v4f16_i32(ix, imip, t); } +RATTR static half4 my_image_load_mip_2d_v4f16_i32(uint ix, uint iy, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_2d_v4f16_i32(ix, iy, imip, t); } +RATTR static half4 my_image_load_mip_3d_v4f16_i32(uint ix, uint iy, uint iz, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_3d_v4f16_i32(ix, iy, iz, imip, t); } +RATTR static half4 my_image_load_mip_cube_v4f16_i32(uint ix, uint iy, uint iface, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_cube_v4f16_i32(ix, iy, iface, imip, t); } +RATTR static half4 my_image_load_mip_1darray_v4f16_i32(uint ix, uint islice, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_1darray_v4f16_i32(ix, islice, imip, t); } +RATTR static half4 my_image_load_mip_2darray_v4f16_i32(uint ix, uint iy, uint islice, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_2darray_v4f16_i32(ix, iy, islice, imip, t); } + +RATTR static float my_image_load_2d_f32_i32(uint ix, uint iy, uint8 t) +{ return __llvm_amdgcn_image_load_2d_f32_i32(ix, iy, t); } +RATTR static float my_image_load_2darray_f32_i32(uint ix, uint iy, uint islice, uint8 t) +{ return __llvm_amdgcn_image_load_2darray_f32_i32(ix, iy, islice, t); } +RATTR static float my_image_load_mip_2d_f32_i32(uint ix, uint iy, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_2d_f32_i32(ix, iy, imip, t); } +RATTR static float my_image_load_mip_2darray_f32_i32(uint ix, uint iy, uint islice, uint imip, uint8 t) +{ return __llvm_amdgcn_image_load_mip_2darray_f32_i32(ix, iy, islice, imip, t); } + +WATTR static void my_image_store_1d_v4f32_i32(float4 pix, uint ix, uint8 t) +{ __llvm_amdgcn_image_store_1d_v4f32_i32(pix, ix, t); } +WATTR static void my_image_store_2d_v4f32_i32(float4 pix, uint ix, uint iy, uint8 t) +{ __llvm_amdgcn_image_store_2d_v4f32_i32(pix, ix, iy, t); } +WATTR static void my_image_store_3d_v4f32_i32(float4 pix, uint ix, uint iy, uint iz, uint8 t) +{ __llvm_amdgcn_image_store_3d_v4f32_i32(pix, ix, iy, iz, t); } +WATTR static void my_image_store_cube_v4f32_i32(float4 pix, uint ix, uint iy, uint iface, uint8 t) +{ __llvm_amdgcn_image_store_cube_v4f32_i32(pix, ix, iy, iface, t); } +WATTR static void my_image_store_1darray_v4f32_i32(float4 pix, uint ix, uint islice, uint8 t) +{ __llvm_amdgcn_image_store_1darray_v4f32_i32(pix, ix, islice, t); } +WATTR static void my_image_store_2darray_v4f32_i32(float4 pix, uint ix, uint iy, uint islice, uint8 t) +{ __llvm_amdgcn_image_store_2darray_v4f32_i32(pix, ix, iy, islice, t); } +WATTR static void my_image_store_mip_1d_v4f32_i32(float4 pix, uint ix, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_1d_v4f32_i32(pix, ix, imip, t); } +WATTR static void my_image_store_mip_2d_v4f32_i32(float4 pix, uint ix, uint iy, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_2d_v4f32_i32(pix, ix, iy, imip, t); } +WATTR static void my_image_store_mip_3d_v4f32_i32(float4 pix, uint ix, uint iy, uint iz, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_3d_v4f32_i32(pix, ix, iy, iz, imip, t); } +WATTR static void my_image_store_mip_cube_v4f32_i32(float4 pix, uint ix, uint iy, uint iface, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_cube_v4f32_i32(pix, ix, iy, iface, imip, t); } +WATTR static void my_image_store_mip_1darray_v4f32_i32(float4 pix, uint ix, uint islice, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_1darray_v4f32_i32(pix, ix, islice, imip, t); } +WATTR static void my_image_store_mip_2darray_v4f32_i32(float4 pix, uint ix, uint iy, uint islice, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_2darray_v4f32_i32(pix, ix, iy, islice, imip, t); } + +WATTR static void my_image_store_1d_v4f16_i32(half4 pix, uint ix, uint8 t) +{ __llvm_amdgcn_image_store_1d_v4f16_i32(pix, ix, t); } +WATTR static void my_image_store_2d_v4f16_i32(half4 pix, uint ix, uint iy, uint8 t) +{ __llvm_amdgcn_image_store_2d_v4f16_i32(pix, ix, iy, t); } +WATTR static void my_image_store_3d_v4f16_i32(half4 pix, uint ix, uint iy, uint iz, uint8 t) +{ __llvm_amdgcn_image_store_3d_v4f16_i32(pix, ix, iy, iz, t); } +WATTR static void my_image_store_cube_v4f16_i32(half4 pix, uint ix, uint iy, uint iface, uint8 t) +{ __llvm_amdgcn_image_store_cube_v4f16_i32(pix, ix, iy, iface, t); } +WATTR static void my_image_store_1darray_v4f16_i32(half4 pix, uint ix, uint islice, uint8 t) +{ __llvm_amdgcn_image_store_1darray_v4f16_i32(pix, ix, islice, t); } +WATTR static void my_image_store_2darray_v4f16_i32(half4 pix, uint ix, uint iy, uint islice, uint8 t) +{ __llvm_amdgcn_image_store_2darray_v4f16_i32(pix, ix, iy, islice, t); } +WATTR static void my_image_store_mip_1d_v4f16_i32(half4 pix, uint ix, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_1d_v4f16_i32(pix, ix, imip, t); } +WATTR static void my_image_store_mip_2d_v4f16_i32(half4 pix, uint ix, uint iy, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_2d_v4f16_i32(pix, ix, iy, imip, t); } +WATTR static void my_image_store_mip_3d_v4f16_i32(half4 pix, uint ix, uint iy, uint iz, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_3d_v4f16_i32(pix, ix, iy, iz, imip, t); } +WATTR static void my_image_store_mip_cube_v4f16_i32(half4 pix, uint ix, uint iy, uint iface, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_cube_v4f16_i32(pix, ix, iy, iface, imip, t); } +WATTR static void my_image_store_mip_1darray_v4f16_i32(half4 pix, uint ix, uint islice, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_1darray_v4f16_i32(pix, ix, islice, imip, t); } +WATTR static void my_image_store_mip_2darray_v4f16_i32(half4 pix, uint ix, uint iy, uint islice, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_2darray_v4f16_i32(pix, ix, iy, islice, imip, t); } + + +WATTR static void my_image_store_2d_f32_i32(float pix, uint ix, uint iy, uint8 t) +{ __llvm_amdgcn_image_store_2d_f32_i32(pix, ix, iy, t); } +WATTR static void my_image_store_2darray_f32_i32(float pix, uint ix, uint iy, uint islice, uint8 t) +{ __llvm_amdgcn_image_store_2darray_f32_i32(pix, ix, iy, islice, t); } +WATTR static void my_image_store_mip_2d_f32_i32(float pix, uint ix, uint iy, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_2d_f32_i32(pix, ix, iy, imip, t); } +WATTR static void my_image_store_mip_2darray_f32_i32(float pix, uint ix, uint iy, uint islice, uint imip, uint8 t) +{ __llvm_amdgcn_image_store_mip_2darray_f32_i32(pix, ix, iy, islice, imip, t); } + + +RATTR static float4 my_image_sample_1d_v4f32_f32(float x, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_1d_v4f32_f32(x, t, s); } +ERATTR static float4 my_image_sample_lz_1d_v4f32_f32(float x, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_1d_v4f32_f32(x, t, s); } +ERATTR static float4 my_image_sample_l_1d_v4f32_f32(float x, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_1d_v4f32_f32(x, lod, t, s); } +ERATTR static float4 my_image_sample_d_1d_v4f32_f32_f32(float dxdh, float dxdv, float x, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_1d_v4f32_f32_f32(dxdh, dxdv, x, t, s); } +RATTR static float4 my_image_sample_2d_v4f32_f32(float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_2d_v4f32_f32(x, y, t, s); } +ERATTR static float4 my_image_sample_lz_2d_v4f32_f32(float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_2d_v4f32_f32(x, y, t, s); } +ERATTR static float4 my_image_sample_l_2d_v4f32_f32(float x, float y, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_2d_v4f32_f32(x, y, lod, t, s); } +ERATTR static float4 my_image_sample_d_2d_v4f32_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_2d_v4f32_f32_f32(dxdh, dydh, dxdv, dydv, x, y, t, s); } +RATTR static float4 my_image_sample_3d_v4f32_f32(float x, float y, float z, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_3d_v4f32_f32(x, y, z, t, s); } +ERATTR static float4 my_image_sample_lz_3d_v4f32_f32(float x, float y, float z, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_3d_v4f32_f32(x, y, z, t, s); } +ERATTR static float4 my_image_sample_l_3d_v4f32_f32(float x, float y, float z, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_3d_v4f32_f32(x, y, z, lod, t, s); } +ERATTR static float4 my_image_sample_d_3d_v4f32_f32_f32(float dxdh, float dydh, float dzdh, float dxdv, float dydv, float dzdv, float x, float y, float z, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_3d_v4f32_f32_f32(dxdh, dydh, dzdh, dxdv, dydv, dzdv, x, y, z, t, s); } +RATTR static float4 my_image_sample_cube_v4f32_f32(float x, float y, float face, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_cube_v4f32_f32(x, y, face, t, s); } +ERATTR static float4 my_image_sample_lz_cube_v4f32_f32(float x, float y, float face, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_cube_v4f32_f32(x, y, face, t, s); } +ERATTR static float4 my_image_sample_l_cube_v4f32_f32(float x, float y, float face, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_cube_v4f32_f32(x, y, face, lod, t, s); } + +RATTR static float4 my_image_sample_1darray_v4f32_f32(float x, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_1darray_v4f32_f32(x, slice, t, s); } +ERATTR static float4 my_image_sample_lz_1darray_v4f32_f32(float x, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_1darray_v4f32_f32(x, slice, t, s); } +ERATTR static float4 my_image_sample_l_1darray_v4f32_f32(float x, float slice, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_1darray_v4f32_f32(x, slice, lod, t, s); } +ERATTR static float4 my_image_sample_d_1darray_v4f32_f32_f32(float dxdh, float dxdv, float x, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_1darray_v4f32_f32_f32(dxdh, dxdv, x, slice, t, s); } +RATTR static float4 my_image_sample_2darray_v4f32_f32(float x, float y, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_2darray_v4f32_f32(x, y, slice, t, s); } +ERATTR static float4 my_image_sample_lz_2darray_v4f32_f32(float x, float y, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_2darray_v4f32_f32(x, y, slice, t, s); } +ERATTR static float4 my_image_sample_l_2darray_v4f32_f32(float x, float y, float slice, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_2darray_v4f32_f32(x, y, slice, lod, t, s); } +ERATTR static float4 my_image_sample_d_2darray_v4f32_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_2darray_v4f32_f32_f32(dxdh, dydh, dxdv, dydv, x, y, slice, t, s); } + +RATTR static half4 my_image_sample_1d_v4f16_f32(float x, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_1d_v4f16_f32(x, t, s); } +ERATTR static half4 my_image_sample_lz_1d_v4f16_f32(float x, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_1d_v4f16_f32(x, t, s); } +ERATTR static half4 my_image_sample_l_1d_v4f16_f32(float x, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_1d_v4f16_f32(x, lod, t, s); } +ERATTR static half4 my_image_sample_d_1d_v4f16_f32_f32(float dxdh, float dxdv, float x, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_1d_v4f16_f32_f32(dxdh, dxdv, x, t, s); } +RATTR static half4 my_image_sample_2d_v4f16_f32(float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_2d_v4f16_f32(x, y, t, s); } +ERATTR static half4 my_image_sample_lz_2d_v4f16_f32(float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_2d_v4f16_f32(x, y, t, s); } +ERATTR static half4 my_image_sample_l_2d_v4f16_f32(float x, float y, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_2d_v4f16_f32(x, y, lod, t, s); } +ERATTR static half4 my_image_sample_d_2d_v4f16_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_2d_v4f16_f32_f32(dxdh, dydh, dxdv, dydv, x, y, t, s); } +RATTR static half4 my_image_sample_3d_v4f16_f32(float x, float y, float z, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_3d_v4f16_f32(x, y, z, t, s); } +ERATTR static half4 my_image_sample_lz_3d_v4f16_f32(float x, float y, float z, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_3d_v4f16_f32(x, y, z, t, s); } +ERATTR static half4 my_image_sample_l_3d_v4f16_f32(float x, float y, float z, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_3d_v4f16_f32(x, y, z, lod, t, s); } +ERATTR static half4 my_image_sample_d_3d_v4f16_f32_f32(float dxdh, float dydh, float dzdh, float dxdv, float dydv, float dzdv, float x, float y, float z, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_3d_v4f16_f32_f32(dxdh, dydh, dzdh, dxdv, dydv, dzdv, x, y, z, t, s); } +RATTR static half4 my_image_sample_cube_v4f16_f32(float x, float y, float face, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_cube_v4f16_f32(x, y, face, t, s); } +ERATTR static half4 my_image_sample_lz_cube_v4f16_f32(float x, float y, float face, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_cube_v4f16_f32(x, y, face, t, s); } +ERATTR static half4 my_image_sample_l_cube_v4f16_f32(float x, float y, float face, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_cube_v4f16_f32(x, y, face, lod, t, s); } + +RATTR static half4 my_image_sample_1darray_v4f16_f32(float x, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_1darray_v4f16_f32(x, slice, t, s); } +ERATTR static half4 my_image_sample_lz_1darray_v4f16_f32(float x, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_1darray_v4f16_f32(x, slice, t, s); } +ERATTR static half4 my_image_sample_l_1darray_v4f16_f32(float x, float slice, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_1darray_v4f16_f32(x, slice, lod, t, s); } +ERATTR static half4 my_image_sample_d_1darray_v4f16_f32_f32(float dxdh, float dxdv, float x, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_1darray_v4f16_f32_f32(dxdh, dxdv, x, slice, t, s); } +RATTR static half4 my_image_sample_2darray_v4f16_f32(float x, float y, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_2darray_v4f16_f32(x, y, slice, t, s); } +ERATTR static half4 my_image_sample_lz_2darray_v4f16_f32(float x, float y, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_2darray_v4f16_f32(x, y, slice, t, s); } +ERATTR static half4 my_image_sample_l_2darray_v4f16_f32(float x, float y, float slice, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_2darray_v4f16_f32(x, y, slice, lod, t, s); } +ERATTR static half4 my_image_sample_d_2darray_v4f16_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_2darray_v4f16_f32_f32(dxdh, dydh, dxdv, dydv, x, y, slice, t, s); } + +RATTR static float my_image_sample_2d_f32_f32(float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_2d_f32_f32(x, y, t, s); } +ERATTR static float my_image_sample_lz_2d_f32_f32(float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_2d_f32_f32(x, y, t, s); } +ERATTR static float my_image_sample_l_2d_f32_f32(float x, float y, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_2d_f32_f32(x, y, lod, t, s); } +ERATTR static float my_image_sample_d_2d_f32_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_2d_f32_f32_f32(dxdh, dydh, dxdv, dydv, x, y, t, s); } +RATTR static float my_image_sample_2darray_f32_f32(float x, float y, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_2darray_f32_f32(x, y, slice, t, s); } +ERATTR static float my_image_sample_lz_2darray_f32_f32(float x, float y, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_lz_2darray_f32_f32(x, y, slice, t, s); } +ERATTR static float my_image_sample_l_2darray_f32_f32(float x, float y, float slice, float lod, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_l_2darray_f32_f32(x, y, slice, lod, t, s); } +ERATTR static float my_image_sample_d_2darray_f32_f32_f32(float dxdh, float dydh, float dxdv, float dydv, float x, float y, float slice, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_sample_d_2darray_f32_f32_f32(dxdh, dydh, dxdv, dydv, x, y, slice, t, s); } + +ERATTR static float4 my_image_gather4_lz_2d_v4f32_f32_r(float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_r(x, y, t, s); } +ERATTR static float4 my_image_gather4_lz_2d_v4f32_f32_g(float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_g(x, y, t, s); } +ERATTR static float4 my_image_gather4_lz_2d_v4f32_f32_b(float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_b(x, y, t, s); } +ERATTR static float4 my_image_gather4_lz_2d_v4f32_f32_a(float x, float y, uint8 t, uint4 s) +{ return __llvm_amdgcn_image_gather4_lz_2d_v4f32_f32_a(x, y, t, s); } + + +RATTR float4 +OCKL_MANGLE_T(image_load,1D)(TSHARP i, int c) +{ + return my_image_load_1d_v4f32_i32(c, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load,1Da)(TSHARP i, int2 c) +{ + return my_image_load_1darray_v4f32_i32(c.x, c.y, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load,1Db)(TSHARP i, int c) +{ + return __llvm_amdgcn_struct_buffer_load_format_v4f32(LOAD_VSHARP(i), c, 0, 0); +} + +RATTR float4 +OCKL_MANGLE_T(image_load,2D)(TSHARP i, int2 c) +{ + return my_image_load_2d_v4f32_i32(c.x, c.y, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load,2Da)(TSHARP i, int4 c) +{ + return my_image_load_2darray_v4f32_i32(c.x, c.y, c.z, LOAD_TSHARP(i)); +} + +RATTR float +OCKL_MANGLE_T(image_load,2Dad)(TSHARP i, int4 c) +{ + return my_image_load_2darray_f32_i32(c.x, c.y, c.z, LOAD_TSHARP(i)); +} + +RATTR float +OCKL_MANGLE_T(image_load,2Dd)(TSHARP i, int2 c) +{ + return my_image_load_2d_f32_i32(c.x, c.y, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load,3D)(TSHARP i, int4 c) +{ + return my_image_load_3d_v4f32_i32(c.x, c.y, c.z, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load,CM)(TSHARP i, int2 c, int f) +{ + return my_image_load_cube_v4f32_i32(c.x, c.y, f, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load,CMa)(TSHARP i, int4 c, int f) +{ + f = LS_ARRAY_FACE(c.z, f); + return my_image_load_cube_v4f32_i32(c.x, c.y, f, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load_lod,1D)(TSHARP i, int c, int l) +{ + return my_image_load_mip_1d_v4f32_i32(c, l, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load_lod,1Da)(TSHARP i, int2 c, int l) +{ + return my_image_load_mip_1darray_v4f32_i32(c.x, c.y, l, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load_lod,2D)(TSHARP i, int2 c, int l) +{ + return my_image_load_mip_2d_v4f32_i32(c.x, c.y, l, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load_lod,2Da)(TSHARP i, int4 c, int l) +{ + return my_image_load_mip_2darray_v4f32_i32(c.x, c.y, c.z, l, LOAD_TSHARP(i)); +} + +RATTR float +OCKL_MANGLE_T(image_load_lod,2Dad)(TSHARP i, int4 c, int l) +{ + return my_image_load_mip_2darray_f32_i32(c.x, c.y, c.z, l, LOAD_TSHARP(i)); +} + +RATTR float +OCKL_MANGLE_T(image_load_lod,2Dd)(TSHARP i, int2 c, int l) +{ + return my_image_load_mip_2d_f32_i32(c.x, c.y, l, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load_lod,3D)(TSHARP i, int4 c, int l) +{ + return my_image_load_mip_3d_v4f32_i32(c.x, c.y, c.z, l, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load_lod,CM)(TSHARP i, int2 c, int f, int l) +{ + return my_image_load_mip_cube_v4f32_i32(c.x, c.y, f, l, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_load_lod,CMa)(TSHARP i, int4 c, int f, int l) +{ + f = LS_ARRAY_FACE(c.z, f); + return my_image_load_mip_cube_v4f32_i32(c.x, c.y, f, l, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh,1D)(TSHARP i, int c) +{ + return my_image_load_1d_v4f16_i32(c, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh,1Da)(TSHARP i, int2 c) +{ + return my_image_load_1darray_v4f16_i32(c.x, c.y, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh,1Db)(TSHARP i, int c) +{ + return __llvm_amdgcn_struct_buffer_load_format_v4f16(LOAD_VSHARP(i), c, 0, 0); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh,2D)(TSHARP i, int2 c) +{ + return my_image_load_2d_v4f16_i32(c.x, c.y, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh,2Da)(TSHARP i, int4 c) +{ + return my_image_load_2darray_v4f16_i32(c.x, c.y, c.z, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh,3D)(TSHARP i, int4 c) +{ + return my_image_load_3d_v4f16_i32(c.x, c.y, c.z, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh,CM)(TSHARP i, int2 c, int f) +{ + return my_image_load_cube_v4f16_i32(c.x, c.y, f, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh,CMa)(TSHARP i, int4 c, int f) +{ + f = LS_ARRAY_FACE(c.z, f); + return my_image_load_cube_v4f16_i32(c.x, c.y, f, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh_lod,1D)(TSHARP i, int c, int l) +{ + return my_image_load_mip_1d_v4f16_i32(c, l, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh_lod,1Da)(TSHARP i, int2 c, int l) +{ + return my_image_load_mip_1darray_v4f16_i32(c.x, c.y, l, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh_lod,2D)(TSHARP i, int2 c, int l) +{ + return my_image_load_mip_2d_v4f16_i32(c.x, c.y, l, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh_lod,2Da)(TSHARP i, int4 c, int l) +{ + return my_image_load_mip_2darray_v4f16_i32(c.x, c.y, c.z, l, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh_lod,3D)(TSHARP i, int4 c, int l) +{ + return my_image_load_mip_3d_v4f16_i32(c.x, c.y, c.z, l, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh_lod,CM)(TSHARP i, int2 c, int f, int l) +{ + return my_image_load_mip_cube_v4f16_i32(c.x, c.y, f, l, LOAD_TSHARP(i)); +} + +RATTR half4 +OCKL_MANGLE_T(image_loadh_lod,CMa)(TSHARP i, int4 c, int f, int l) +{ + f = LS_ARRAY_FACE(c.z, f); + return my_image_load_mip_cube_v4f16_i32(c.x, c.y, f, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store,1D)(TSHARP i, int c, float4 p) +{ + my_image_store_1d_v4f32_i32(p, c, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store,1Da)(TSHARP i, int2 c, float4 p) +{ + my_image_store_1darray_v4f32_i32(p, c.x, c.y, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store,1Db)(TSHARP i, int c, float4 p) +{ + __llvm_amdgcn_struct_buffer_store_format_v4f32(p, LOAD_VSHARP(i), c, 0, 0); +} + +WATTR void +OCKL_MANGLE_T(image_store,2D)(TSHARP i, int2 c, float4 p) +{ + my_image_store_2d_v4f32_i32(p, c.x, c.y, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store,2Da)(TSHARP i, int4 c, float4 p) +{ + my_image_store_2darray_v4f32_i32(p, c.x, c.y, c.z, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store,2Dad)(TSHARP i, int4 c, float p) +{ + my_image_store_2darray_f32_i32(p, c.x, c.y, c.z, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store,2Dd)(TSHARP i, int2 c, float p) +{ + my_image_store_2d_f32_i32(p, c.x, c.y, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store,3D)(TSHARP i, int4 c, float4 p) +{ + my_image_store_3d_v4f32_i32(p, c.x, c.y, c.z, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store,CM)(TSHARP i, int2 c, int f, float4 p) +{ + my_image_store_cube_v4f32_i32(p, c.x, c.y, f, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store,CMa)(TSHARP i, int4 c, int f, float4 p) +{ + f = LS_ARRAY_FACE(c.z, f); + my_image_store_cube_v4f32_i32(p, c.x, c.y, f, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store_lod,1D)(TSHARP i, int c, int l, float4 p) +{ + my_image_store_mip_1d_v4f32_i32(p, c, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store_lod,1Da)(TSHARP i, int2 c, int l, float4 p) +{ + my_image_store_mip_1darray_v4f32_i32(p, c.x, c.y, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store_lod,2D)(TSHARP i, int2 c, int l, float4 p) +{ + my_image_store_mip_2d_v4f32_i32(p, c.x, c.y, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store_lod,2Da)(TSHARP i, int4 c, int l, float4 p) +{ + my_image_store_mip_2darray_v4f32_i32(p, c.x, c.y, c.z, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store_lod,2Dad)(TSHARP i, int4 c, int l, float p) +{ + my_image_store_mip_2darray_f32_i32(p, c.x, c.y, c.z, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store_lod,2Dd)(TSHARP i, int2 c, int l, float p) +{ + my_image_store_mip_2d_f32_i32(p, c.x, c.y, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store_lod,3D)(TSHARP i, int4 c, int l, float4 p) +{ + my_image_store_mip_3d_v4f32_i32(p, c.x, c.y, c.z, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store_lod,CM)(TSHARP i, int2 c, int f, int l, float4 p) +{ + my_image_store_mip_cube_v4f32_i32(p, c.x, c.y, f, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_store_lod,CMa)(TSHARP i, int4 c, int f, int l, float4 p) +{ + f = LS_ARRAY_FACE(c.z, f); + my_image_store_mip_cube_v4f32_i32(p, c.x, c.y, f, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh,1D)(TSHARP i, int c, half4 p) +{ + my_image_store_1d_v4f16_i32(p, c, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh,1Da)(TSHARP i, int2 c, half4 p) +{ + my_image_store_1darray_v4f16_i32(p, c.x, c.y, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh,1Db)(TSHARP i, int c, half4 p) +{ + __llvm_amdgcn_struct_buffer_store_format_v4f16(p, LOAD_VSHARP(i), c, 0, 0); +} + +WATTR void +OCKL_MANGLE_T(image_storeh,2D)(TSHARP i, int2 c, half4 p) +{ + my_image_store_2d_v4f16_i32(p, c.x, c.y, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh,2Da)(TSHARP i, int4 c, half4 p) +{ + my_image_store_2darray_v4f16_i32(p, c.x, c.y, c.z, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh,3D)(TSHARP i, int4 c, half4 p) +{ + my_image_store_3d_v4f16_i32(p, c.x, c.y, c.z, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh,CM)(TSHARP i, int2 c, int f, half4 p) +{ + my_image_store_cube_v4f16_i32(p, c.x, c.y, f, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh,CMa)(TSHARP i, int4 c, int f, half4 p) +{ + f = LS_ARRAY_FACE(c.z, f); + my_image_store_cube_v4f16_i32(p, c.x, c.y, f, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh_lod,1D)(TSHARP i, int c, int l, half4 p) +{ + my_image_store_mip_1d_v4f16_i32(p, c, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh_lod,1Da)(TSHARP i, int2 c, int l, half4 p) +{ + my_image_store_mip_1darray_v4f16_i32(p, c.x, c.y, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh_lod,2D)(TSHARP i, int2 c, int l, half4 p) +{ + my_image_store_mip_2d_v4f16_i32(p, c.x, c.y, l, LOAD_TSHARP(i)); +} +WATTR void +OCKL_MANGLE_T(image_storeh_lod,2Da)(TSHARP i, int4 c, int l, half4 p) +{ + my_image_store_mip_2darray_v4f16_i32(p, c.x, c.y, c.z, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh_lod,3D)(TSHARP i, int4 c, int l, half4 p) +{ + my_image_store_mip_3d_v4f16_i32(p, c.x, c.y, c.z, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh_lod,CM)(TSHARP i, int2 c, int f, int l, half4 p) +{ + my_image_store_mip_cube_v4f16_i32(p, c.x, c.y, f, l, LOAD_TSHARP(i)); +} + +WATTR void +OCKL_MANGLE_T(image_storeh_lod,CMa)(TSHARP i, int4 c, int f, int l, half4 p) +{ + f = LS_ARRAY_FACE(c.z, f); + my_image_store_mip_cube_v4f16_i32(p, c.x, c.y, f, l, LOAD_TSHARP(i)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample,1D)(TSHARP i, SSHARP s, float c) +{ + ADJUST_X(c, i, s); + if (EII()) + return my_image_sample_lz_1d_v4f32_f32(c, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_1d_v4f32_f32(c, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample,1Da)(TSHARP i, SSHARP s, float2 c) +{ + ADJUST_X(c.x, i, s); + c.y = __builtin_rintf(c.y); + if (EII()) + return my_image_sample_lz_1darray_v4f32_f32(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_1darray_v4f32_f32(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample,2D)(TSHARP i, SSHARP s, float2 c) +{ + ADJUST_XY(c, i, s); + if (EII()) + return my_image_sample_lz_2d_v4f32_f32(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_2d_v4f32_f32(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample,2Da)(TSHARP i, SSHARP s, float4 c) +{ + ADJUST_XY(c, i, s); + c.z = __builtin_rintf(c.z); + if (EII()) + return my_image_sample_lz_2darray_v4f32_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_2darray_v4f32_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float +OCKL_MANGLE_T(image_sample,2Dad)(TSHARP i, SSHARP s, float4 c) +{ + ADJUST_XY(c, i, s); + c.z = __builtin_rintf(c.z); + if (EII()) + return my_image_sample_lz_2darray_f32_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_2darray_f32_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float +OCKL_MANGLE_T(image_sample,2Dd)(TSHARP i, SSHARP s, float2 c) +{ + ADJUST_XY(c, i, s); + if (EII()) + return my_image_sample_lz_2d_f32_f32(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_2d_f32_f32(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample,3D)(TSHARP i, SSHARP s, float4 c) +{ + ADJUST_XYZ(c, i, s); + if (EII()) + return my_image_sample_lz_3d_v4f32_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_3d_v4f32_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample,CM)(TSHARP i, SSHARP s, float4 c) +{ + CUBE_PREP(c); + if (EII()) + return my_image_sample_lz_cube_v4f32_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_cube_v4f32_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample,CMa)(TSHARP i, SSHARP s, float4 c) +{ + CUBE_PREP(c); + c.z = SAMPLE_ARRAY_FACE(c.w, c.z); + if (EII()) + return my_image_sample_lz_cube_v4f32_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_cube_v4f32_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_grad,1D)(TSHARP i, SSHARP s, float c, float dx, float dy) +{ + ADJUST_X(c, i, s); + return my_image_sample_d_1d_v4f32_f32_f32(dx, dy, c, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_grad,1Da)(TSHARP i, SSHARP s, float2 c, float dx, float dy) +{ + ADJUST_X(c.x, i, s); + c.y = __builtin_rintf(c.y); + return my_image_sample_d_1darray_v4f32_f32_f32(dx, dy, c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_grad,2D)(TSHARP i, SSHARP s, float2 c, float2 dx, float2 dy) +{ + ADJUST_XY(c, i, s); + return my_image_sample_d_2d_v4f32_f32_f32(dx.x, dx.y, dy.x, dy.y, c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_grad,2Da)(TSHARP i, SSHARP s, float4 c, float2 dx, float2 dy) +{ + ADJUST_XY(c, i, s); + c.z = __builtin_rintf(c.z); + return my_image_sample_d_2darray_v4f32_f32_f32(dx.x, dx.y, dy.x, dy.y, c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float +OCKL_MANGLE_T(image_sample_grad,2Dad)(TSHARP i, SSHARP s, float4 c, float2 dx, float2 dy) +{ + ADJUST_XY(c, i, s); + c.z = __builtin_rintf(c.z); + return my_image_sample_d_2darray_f32_f32_f32(dx.x, dx.y, dy.x, dy.y, c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float +OCKL_MANGLE_T(image_sample_grad,2Dd)(TSHARP i, SSHARP s, float2 c, float2 dx, float2 dy) +{ + ADJUST_XY(c, i, s); + return my_image_sample_d_2d_f32_f32_f32(dx.x, dx.y, dy.x, dy.y, c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_grad,3D)(TSHARP i, SSHARP s, float4 c, float4 dx, float4 dy) +{ + ADJUST_XYZ(c, i, s); + return my_image_sample_d_3d_v4f32_f32_f32(dx.x, dx.y, dx.z, dy.x, dy.y, dy.z, c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_lod,1D)(TSHARP i, SSHARP s, float c, float l) +{ + return my_image_sample_l_1d_v4f32_f32(c, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_lod,1Da)(TSHARP i, SSHARP s, float2 c, float l) +{ + c.y = __builtin_rintf(c.y); + return my_image_sample_l_1darray_v4f32_f32(c.x, c.y, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_lod,2D)(TSHARP i, SSHARP s, float2 c, float l) +{ + return my_image_sample_l_2d_v4f32_f32(c.x, c.y, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_lod,2Da)(TSHARP i, SSHARP s, float4 c, float l) +{ + c.z = __builtin_rintf(c.z); + return my_image_sample_l_2darray_v4f32_f32(c.x, c.y, c.z, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float +OCKL_MANGLE_T(image_sample_lod,2Dad)(TSHARP i, SSHARP s, float4 c, float l) +{ + c.z = __builtin_rintf(c.z); + return my_image_sample_l_2darray_f32_f32(c.x, c.y, c.z, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float +OCKL_MANGLE_T(image_sample_lod,2Dd)(TSHARP i, SSHARP s, float2 c, float l) +{ + return my_image_sample_l_2d_f32_f32(c.x, c.y, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_lod,3D)(TSHARP i, SSHARP s, float4 c, float l) +{ + return my_image_sample_l_3d_v4f32_f32(c.x, c.y, c.z, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_lod,CM)(TSHARP i, SSHARP s, float4 c, float l) +{ + CUBE_PREP(c); + return my_image_sample_l_cube_v4f32_f32(c.x, c.y, c.z, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_sample_lod,CMa)(TSHARP i, SSHARP s, float4 c, float l) +{ + CUBE_PREP(c); + c.z = SAMPLE_ARRAY_FACE(c.w, c.z); + return my_image_sample_l_cube_v4f32_f32(c.x, c.y, c.z, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh,1D)(TSHARP i, SSHARP s, float c) +{ + ADJUST_X(c, i, s); + if (EII()) + return my_image_sample_lz_1d_v4f16_f32(c, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_1d_v4f16_f32(c, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh,1Da)(TSHARP i, SSHARP s, float2 c) +{ + ADJUST_X(c.x, i, s); + c.y = __builtin_rintf(c.y); + if (EII()) + return my_image_sample_lz_1darray_v4f16_f32(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_1darray_v4f16_f32(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh,2D)(TSHARP i, SSHARP s, float2 c) +{ + ADJUST_XY(c, i, s); + if (EII()) + return my_image_sample_lz_2d_v4f16_f32(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_2d_v4f16_f32(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh,2Da)(TSHARP i, SSHARP s, float4 c) +{ + ADJUST_XY(c, i, s); + c.z = __builtin_rintf(c.z); + if (EII()) + return my_image_sample_lz_2darray_v4f16_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_2darray_v4f16_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh,3D)(TSHARP i, SSHARP s, float4 c) +{ + ADJUST_XYZ(c, i, s); + if (EII()) + return my_image_sample_lz_3d_v4f16_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_3d_v4f16_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh,CM)(TSHARP i, SSHARP s, float4 c) +{ + CUBE_PREP(c); + if (EII()) + return my_image_sample_lz_cube_v4f16_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_cube_v4f16_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh,CMa)(TSHARP i, SSHARP s, float4 c) +{ + CUBE_PREP(c); + c.z = SAMPLE_ARRAY_FACE(c.w, c.z); + if (EII()) + return my_image_sample_lz_cube_v4f16_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); + else + return my_image_sample_cube_v4f16_f32(c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_grad,1D)(TSHARP i, SSHARP s, float c, float dx, float dy) +{ + ADJUST_X(c, i, s); + return my_image_sample_d_1d_v4f16_f32_f32(dx, dy, c, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_grad,1Da)(TSHARP i, SSHARP s, float2 c, float dx, float dy) +{ + ADJUST_X(c.x, i, s); + c.y = __builtin_rintf(c.y); + return my_image_sample_d_1darray_v4f16_f32_f32(dx, dy, c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_grad,2D)(TSHARP i, SSHARP s, float2 c, float2 dx, float2 dy) +{ + ADJUST_XY(c, i, s); + return my_image_sample_d_2d_v4f16_f32_f32(dx.x, dx.y, dy.x, dy.y, c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_grad,2Da)(TSHARP i, SSHARP s, float4 c, float2 dx, float2 dy) +{ + ADJUST_XY(c, i, s); + c.z = __builtin_rintf(c.z); + return my_image_sample_d_2darray_v4f16_f32_f32(dx.x, dx.y, dy.x, dy.y, c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_grad,3D)(TSHARP i, SSHARP s, float4 c, float4 dx, float4 dy) +{ + ADJUST_XYZ(c, i, s); + return my_image_sample_d_3d_v4f16_f32_f32(dx.x, dx.y, dx.z, dy.x, dy.y, dy.z, c.x, c.y, c.z, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_lod,1D)(TSHARP i, SSHARP s, float c, float l) +{ + return my_image_sample_l_1d_v4f16_f32(c, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_lod,1Da)(TSHARP i, SSHARP s, float2 c, float l) +{ + c.y = __builtin_rintf(c.y); + return my_image_sample_l_1darray_v4f16_f32(c.x, c.y, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_lod,2D)(TSHARP i, SSHARP s, float2 c, float l) +{ + return my_image_sample_l_2d_v4f16_f32(c.x, c.y, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_lod,2Da)(TSHARP i, SSHARP s, float4 c, float l) +{ + c.z = __builtin_rintf(c.z); + return my_image_sample_l_2darray_v4f16_f32(c.x, c.y, c.z, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_lod,3D)(TSHARP i, SSHARP s, float4 c, float l) +{ + return my_image_sample_l_3d_v4f16_f32(c.x, c.y, c.z, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_lod,CM)(TSHARP i, SSHARP s, float4 c, float l) +{ + CUBE_PREP(c); + return my_image_sample_l_cube_v4f16_f32(c.x, c.y, c.z, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR half4 +OCKL_MANGLE_T(image_sampleh_lod,CMa)(TSHARP i, SSHARP s, float4 c, float l) +{ + CUBE_PREP(c); + c.z = SAMPLE_ARRAY_FACE(c.w, c.z); + return my_image_sample_l_cube_v4f16_f32(c.x, c.y, c.z, l, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_gather4r,2D)(TSHARP i, SSHARP s, float2 c) +{ + ADJUST_XY(c, i, s); + return my_image_gather4_lz_2d_v4f32_f32_r(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_gather4g,2D)(TSHARP i, SSHARP s, float2 c) +{ + ADJUST_XY(c, i, s); + return my_image_gather4_lz_2d_v4f32_f32_g(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_gather4b,2D)(TSHARP i, SSHARP s, float2 c) +{ + ADJUST_XY(c, i, s); + return my_image_gather4_lz_2d_v4f32_f32_b(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +RATTR float4 +OCKL_MANGLE_T(image_gather4a,2D)(TSHARP i, SSHARP s, float2 c) +{ + ADJUST_XY(c, i, s); + return my_image_gather4_lz_2d_v4f32_f32_a(c.x, c.y, LOAD_TSHARP(i), LOAD_SSHARP(s)); +} + +// We rely on the fact that the runtime allocates 12 words for the T# or V# +// and fills words 8, 9, and 10 with the data we need to answer all of the queries + +#define ARRAY_SIZE(I) \ + if (__oclc_ISA_version < 9000) { \ + return FIELD(I, 173, 13) + 1U; \ + } else { \ + return FIELD(I, 128, 13) + 1U; \ + } + +GATTR int OCKL_MANGLE_T(image_array_size,1Da)(TSHARP i) { ARRAY_SIZE(i) } +GATTR int OCKL_MANGLE_T(image_array_size,2Da)(TSHARP i) { ARRAY_SIZE(i) } +GATTR int OCKL_MANGLE_T(image_array_size,2Dad)(TSHARP i) { ARRAY_SIZE(i) } +GATTR int OCKL_MANGLE_T(image_array_size,CMa)(TSHARP i) { ARRAY_SIZE(i) } + +GATTR int OCKL_MANGLE_T(image_channel_data_type,1D)(TSHARP i) { return WORD(i, 8); } +GATTR int OCKL_MANGLE_T(image_channel_data_type,1Da)(TSHARP i) { return WORD(i, 8); } +GATTR int OCKL_MANGLE_T(image_channel_data_type,1Db)(TSHARP i) { return WORD(i, 8); } +GATTR int OCKL_MANGLE_T(image_channel_data_type,2D)(TSHARP i) { return WORD(i, 8); } +GATTR int OCKL_MANGLE_T(image_channel_data_type,2Da)(TSHARP i) { return WORD(i, 8); } +GATTR int OCKL_MANGLE_T(image_channel_data_type,2Dad)(TSHARP i) { return WORD(i, 8); } +GATTR int OCKL_MANGLE_T(image_channel_data_type,2Dd)(TSHARP i) { return WORD(i, 8); } +GATTR int OCKL_MANGLE_T(image_channel_data_type,3D)(TSHARP i) { return WORD(i, 8); } +GATTR int OCKL_MANGLE_T(image_channel_data_type,CM)(TSHARP i) { return WORD(i, 8); } +GATTR int OCKL_MANGLE_T(image_channel_data_type,CMa)(TSHARP i) { return WORD(i, 8); } + +GATTR int OCKL_MANGLE_T(image_channel_order,1D)(TSHARP i) { return WORD(i, 9); } +GATTR int OCKL_MANGLE_T(image_channel_order,1Da)(TSHARP i) { return WORD(i, 9); } +GATTR int OCKL_MANGLE_T(image_channel_order,1Db)(TSHARP i) { return WORD(i, 9); } +GATTR int OCKL_MANGLE_T(image_channel_order,2D)(TSHARP i) { return WORD(i, 9); } +GATTR int OCKL_MANGLE_T(image_channel_order,2Da)(TSHARP i) { return WORD(i, 9); } +GATTR int OCKL_MANGLE_T(image_channel_order,2Dad)(TSHARP i) { return WORD(i, 9); } +GATTR int OCKL_MANGLE_T(image_channel_order,2Dd)(TSHARP i) { return WORD(i, 9); } +GATTR int OCKL_MANGLE_T(image_channel_order,3D)(TSHARP i) { return WORD(i, 9); } +GATTR int OCKL_MANGLE_T(image_channel_order,CM)(TSHARP i) { return WORD(i, 9); } +GATTR int OCKL_MANGLE_T(image_channel_order,CMa)(TSHARP i) { return WORD(i, 9); } + +GATTR int OCKL_MANGLE_T(image_depth,3D)(TSHARP i) { return FIELD(i, 128, 13) + 1U; } + +GATTR int OCKL_MANGLE_T(image_height,2D)(TSHARP i) { return FIELD(i, 78, 14) + 1U; } +GATTR int OCKL_MANGLE_T(image_height,2Da)(TSHARP i) { return FIELD(i, 78, 14) + 1U; } +GATTR int OCKL_MANGLE_T(image_height,2Dad)(TSHARP i) { return FIELD(i, 78, 14) + 1U; } +GATTR int OCKL_MANGLE_T(image_height,2Dd)(TSHARP i) { return FIELD(i, 78, 14) + 1U; } +GATTR int OCKL_MANGLE_T(image_height,3D)(TSHARP i) { return FIELD(i, 78, 14) + 1U; } +GATTR int OCKL_MANGLE_T(image_height,CM)(TSHARP i) { return FIELD(i, 78, 14) + 1U; } +GATTR int OCKL_MANGLE_T(image_height,CMa)(TSHARP i) { return FIELD(i, 78, 14) + 1U; } + +GATTR int OCKL_MANGLE_T(image_num_mip_levels,1D)(TSHARP i) { return FIELD(i, 112, 4); } +GATTR int OCKL_MANGLE_T(image_num_mip_levels,1Da)(TSHARP i) { return FIELD(i, 112, 4); } +GATTR int OCKL_MANGLE_T(image_num_mip_levels,2D)(TSHARP i) { return FIELD(i, 112, 4); } +GATTR int OCKL_MANGLE_T(image_num_mip_levels,2Da)(TSHARP i) { return FIELD(i, 112, 4); } +GATTR int OCKL_MANGLE_T(image_num_mip_levels,2Dad)(TSHARP i) { return FIELD(i, 112, 4); } +GATTR int OCKL_MANGLE_T(image_num_mip_levels,2Dd)(TSHARP i) { return FIELD(i, 112, 4); } +GATTR int OCKL_MANGLE_T(image_num_mip_levels,3D)(TSHARP i) { return FIELD(i, 112, 4); } +GATTR int OCKL_MANGLE_T(image_num_mip_levels,CM)(TSHARP i) { return FIELD(i, 112, 4); } +GATTR int OCKL_MANGLE_T(image_num_mip_levels,CMa)(TSHARP i) { return FIELD(i, 112, 4); } + +// In FIELD(i, 64, 14) but also copied into word 11 of the 12 that are allocated +GATTR int OCKL_MANGLE_T(image_width,1D)(TSHARP i) { return WORD(i, 10); } +GATTR int OCKL_MANGLE_T(image_width,1Da)(TSHARP i) { return WORD(i, 10); } +GATTR int OCKL_MANGLE_T(image_width,2D)(TSHARP i) { return WORD(i, 10); } +GATTR int OCKL_MANGLE_T(image_width,2Da)(TSHARP i) { return WORD(i, 10); } +GATTR int OCKL_MANGLE_T(image_width,2Dad)(TSHARP i) { return WORD(i, 10); } +GATTR int OCKL_MANGLE_T(image_width,2Dd)(TSHARP i) { return WORD(i, 10); } +GATTR int OCKL_MANGLE_T(image_width,3D)(TSHARP i) { return WORD(i, 10); } +GATTR int OCKL_MANGLE_T(image_width,CM)(TSHARP i) { return WORD(i, 10); } +GATTR int OCKL_MANGLE_T(image_width,CMa)(TSHARP i) { return WORD(i, 10); } +// This would be a bit trickier since we actually have a V# here and need to look at const_num_records and const_stride +GATTR int OCKL_MANGLE_T(image_width,1Db)(TSHARP i) { return WORD(i, 10); } diff --git a/amd/device-libs/ockl/src/lane.cl b/amd/device-libs/ockl/src/lane.cl new file mode 100644 index 0000000000000..3b95e745939ef --- /dev/null +++ b/amd/device-libs/ockl/src/lane.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +__attribute__((always_inline)) uint +OCKL_MANGLE_U32(lane)(void) +{ + + return __builtin_amdgcn_mbcnt_hi(~0u, __builtin_amdgcn_mbcnt_lo(~0u, 0u)); +} + diff --git a/amd/device-libs/ockl/src/media.cl b/amd/device-libs/ockl/src/media.cl new file mode 100644 index 0000000000000..6bdb12b3562d9 --- /dev/null +++ b/amd/device-libs/ockl/src/media.cl @@ -0,0 +1,216 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" +#include "oclc.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define CATTR __attribute__((const)) +#define AS_UCHAR4(X) __builtin_astype(X, uchar4) + +CATTR uint +OCKL_MANGLE_U32(bfm)(uint w, uint s) +{ + // TODO check that this results in v_bfm_b32 + return ((1U << w) - 1U) << s; +} + +CATTR int +OCKL_MANGLE_I32(bfe)(int a, uint s, uint w) +{ + return __builtin_amdgcn_sbfe(a, s, w); +} + +CATTR uint +OCKL_MANGLE_U32(bfe)(uint a, uint s, uint w) +{ + return __builtin_amdgcn_ubfe(a, s, w); +} + +CATTR uint +OCKL_MANGLE_U32(bitalign)(uint a, uint b, uint c) +{ + return __builtin_amdgcn_alignbit(a, b, c); +} + +CATTR uint +OCKL_MANGLE_U32(bytealign)(uint a, uint b, uint c) +{ + return __builtin_amdgcn_alignbyte(a, b, c); +} + +CATTR uint +OCKL_MANGLE_U32(lerp)(uint a, uint b, uint c) +{ + return __builtin_amdgcn_lerp(a, b, c); +} + +CATTR float +OCKL_MANGLE_F32(max3)(float a, float b, float c) +{ + return __builtin_fmaxf(__builtin_fmaxf(a, b), c); +} + +CATTR float +OCKL_MANGLE_F32(median3)(float a, float b, float c) +{ + return __builtin_amdgcn_fmed3f(a, b, c); +} + +CATTR float +OCKL_MANGLE_F32(min3)(float a, float b, float c) +{ + return __builtin_fminf(__builtin_fminf(a, b), c); +} + +CATTR half +OCKL_MANGLE_F16(max3)(half a, half b, half c) +{ + return __builtin_fmaxf16(__builtin_fmaxf16(a, b), c); +} + +CATTR half +OCKL_MANGLE_F16(median3)(half a, half b, half c) +{ + // The optimizer can turn this back into an f16 fmed3 on supported + // targets. + return (half)__builtin_amdgcn_fmed3f((float)a, (float)b, (float)c); +} + +CATTR half +OCKL_MANGLE_F16(min3)(half a, half b, half c) +{ + return __builtin_fminf16(__builtin_fminf16(a, b), c); +} + +CATTR int +OCKL_MANGLE_I32(max3)(int a, int b, int c) +{ + int a1 = a > b ? a : b; + return a1 > c ? a1 : c; +} + +CATTR int +OCKL_MANGLE_I32(median3)(int a, int b, int c) +{ + int a1 = a < b ? a : b; + int b1 = a > b ? a : b; + int c1 = a1 > c ? a1 : c; + return b1 < c1 ? b1 : c1; +} + +CATTR int +OCKL_MANGLE_I32(min3)(int a, int b, int c) +{ + int a1 = a < b ? a : b; + return a1 < c ? a1 : c; +} + +CATTR uint +OCKL_MANGLE_U32(max3)(uint a, uint b, uint c) +{ + uint a1 = a > b ? a : b; + return a1 > c ? a1 : c; +} + +CATTR uint +OCKL_MANGLE_U32(median3)(uint a, uint b, uint c) +{ + uint a1 = a < b ? a : b; + uint b1 = a > b ? a : b; + uint c1 = a1 > c ? a1 : c; + return b1 < c1 ? b1 : c1; +} + +CATTR uint +OCKL_MANGLE_U32(min3)(uint a, uint b, uint c) +{ + uint a1 = a < b ? a : b; + return a1 < c ? a1 : c; +} + +CATTR uint +OCKL_MANGLE_U32(msad)(uint a, uint b, uint c) +{ + return __builtin_amdgcn_msad_u8(a, b, c); +} + +CATTR ulong +OCKL_MANGLE_U64(mqsad)(ulong a, uint b, ulong c) +{ + return __builtin_amdgcn_mqsad_pk_u16_u8(a, b, c); +} + +CATTR uint +OCKL_MANGLE_U32(pack)(float4 a) +{ + return __builtin_amdgcn_cvt_pk_u8_f32(a.s3, 3, + __builtin_amdgcn_cvt_pk_u8_f32(a.s2, 2, + __builtin_amdgcn_cvt_pk_u8_f32(a.s1, 1, + __builtin_amdgcn_cvt_pk_u8_f32(a.s0, 0, 0)))); +} + +CATTR ulong +OCKL_MANGLE_U64(qsad)(ulong a, uint b, ulong c) +{ + return __builtin_amdgcn_qsad_pk_u16_u8(a, b, c); +} + +CATTR uint +OCKL_MANGLE_U32(sad)(uint a, uint b, uint c) +{ + return __builtin_amdgcn_sad_u8(a, b, c); +} + +CATTR uint +OCKL_MANGLE_U32(sadd)(uint a, uint b, uint c) +{ + // TODO check that this results in v_sad_u32 + return (a > b ? a : b) - (a < b ? a : b) + c; +} + +CATTR uint +OCKL_MANGLE_U32(sadhi)(uint a, uint b, uint c) +{ + return __builtin_amdgcn_sad_hi_u8(a, b, c); +} + +CATTR uint +OCKL_MANGLE_U32(sadw)(uint a, uint b, uint c) +{ + return __builtin_amdgcn_sad_u16(a, b, c); +} + +CATTR float +OCKL_MANGLE_F32(unpack0)(uint a) +{ + uchar4 v = AS_UCHAR4(a); + return (float)v.s0; +} + +CATTR float +OCKL_MANGLE_F32(unpack1)(uint a) +{ + uchar4 v = AS_UCHAR4(a); + return (float)v.s1; +} + +CATTR float +OCKL_MANGLE_F32(unpack2)(uint a) +{ + uchar4 v = AS_UCHAR4(a); + return (float)v.s2; +} + +CATTR float +OCKL_MANGLE_F32(unpack3)(uint a) +{ + uchar4 v = AS_UCHAR4(a); + return (float)v.s3; +} + diff --git a/amd/device-libs/ockl/src/mtime.cl b/amd/device-libs/ockl/src/mtime.cl new file mode 100644 index 0000000000000..b0d7734805e90 --- /dev/null +++ b/amd/device-libs/ockl/src/mtime.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +ulong +OCKL_MANGLE_U64(cyclectr)(void) +{ + return __builtin_readcyclecounter(); +} + +ulong +OCKL_MANGLE_U64(steadyctr)(void) +{ + return __builtin_readsteadycounter(); +} + diff --git a/amd/device-libs/ockl/src/mul24.cl b/amd/device-libs/ockl/src/mul24.cl new file mode 100644 index 0000000000000..9ebb38b5699e8 --- /dev/null +++ b/amd/device-libs/ockl/src/mul24.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +__attribute__((const)) int +OCKL_MANGLE_I32(mul24)(int x, int y) +{ + return ((x << 8) >> 8) * ((y << 8) >> 8); +} + +__attribute__((const)) uint +OCKL_MANGLE_U32(mul24)(uint x, uint y) +{ + return ((x << 8) >> 8) * ((y << 8) >> 8); +} + diff --git a/amd/device-libs/ockl/src/mul_hi.cl b/amd/device-libs/ockl/src/mul_hi.cl new file mode 100644 index 0000000000000..b1a001e41ab10 --- /dev/null +++ b/amd/device-libs/ockl/src/mul_hi.cl @@ -0,0 +1,51 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +__attribute__((const)) int +OCKL_MANGLE_I32(mul_hi)(int x, int y) +{ + return (int)(((long)x * (long)y) >> 32); +} + +__attribute__((const)) uint +OCKL_MANGLE_U32(mul_hi)(uint x, uint y) +{ + return (uint)(((ulong)x * (ulong)y) >> 32); +} + +__attribute__((const)) long +OCKL_MANGLE_I64(mul_hi)(long x, long y) +{ + ulong x0 = (ulong)x & 0xffffffffUL; + long x1 = x >> 32; + ulong y0 = (ulong)y & 0xffffffffUL; + long y1 = y >> 32; + ulong z0 = x0*y0; + long t = x1*y0 + (z0 >> 32); + long z1 = t & 0xffffffffL; + long z2 = t >> 32; + z1 = x0*y1 + z1; + return x1*y1 + z2 + (z1 >> 32); +} + +__attribute__((const)) ulong +OCKL_MANGLE_U64(mul_hi)(ulong x, ulong y) +{ + ulong x0 = x & 0xffffffffUL; + ulong x1 = x >> 32; + ulong y0 = y & 0xffffffffUL; + ulong y1 = y >> 32; + ulong z0 = x0*y0; + ulong t = x1*y0 + (z0 >> 32); + ulong z1 = t & 0xffffffffUL; + ulong z2 = t >> 32; + z1 = x0*y1 + z1; + return x1*y1 + z2 + (z1 >> 32); +} + diff --git a/amd/device-libs/ockl/src/popcount.cl b/amd/device-libs/ockl/src/popcount.cl new file mode 100644 index 0000000000000..9f9ab7c476c14 --- /dev/null +++ b/amd/device-libs/ockl/src/popcount.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +__attribute__((always_inline, const)) uint +OCKL_MANGLE_U32(popcount)(uint i) +{ + return (uint)__builtin_popcount(i); +} + +__attribute__((always_inline, const)) ulong +OCKL_MANGLE_U64(popcount)(ulong i) +{ + return (ulong)__builtin_popcountl(i); +} + diff --git a/amd/device-libs/ockl/src/readuplane.cl b/amd/device-libs/ockl/src/readuplane.cl new file mode 100644 index 0000000000000..9e8451571e4ae --- /dev/null +++ b/amd/device-libs/ockl/src/readuplane.cl @@ -0,0 +1,43 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define WAVESIZE 64 + + +// Function to exchange data between different lanes +// var: value to return if the index is outside the bounds of the wave +// offset: To be added to the lane id to obtain final index +// return a int value correspoding to the lane + +int +__ockl_readuplane_i32(int var, int offset) +{ + + uint lane_id = __ockl_lane_u32(); + int index = lane_id + offset; + index = (uint)((lane_id & (WAVESIZE - 1)) + offset) >= WAVESIZE ? lane_id : index; + return __builtin_amdgcn_ds_bpermute(index << 2, var); + } + + +// Function to exchange data between different lanes +// var: value to return if the index is outside the bounds of the wave +// offset: To be added to the lane id to obtain final index +// return a long value correspoding to the lane + +long +__ockl_readuplane_i64(long var, int offset) { + int lane_id = __ockl_lane_u32(); + int index = lane_id + offset; + index = (uint)((lane_id & (WAVESIZE - 1)) + offset) >= WAVESIZE ? lane_id : index; + int2 var_64= __builtin_astype(var, int2); + var_64.x = __builtin_amdgcn_ds_bpermute(index << 2, var_64.x); + var_64.y = __builtin_amdgcn_ds_bpermute(index << 2, var_64.y); + return __builtin_astype(var_64, long); +} diff --git a/amd/device-libs/ockl/src/services.cl b/amd/device-libs/ockl/src/services.cl new file mode 100644 index 0000000000000..176aecf8bde3a --- /dev/null +++ b/amd/device-libs/ockl/src/services.cl @@ -0,0 +1,410 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define WEAK_ATTR __attribute__((weak)) + +// This must match the enumeration defined by the runtime in +// ROCclr/device/devhcmessages.hpp +typedef enum { + SERVICE_RESERVED = 0, + SERVICE_FUNCTION_CALL = 1, + SERVICE_PRINTF = 2, + SERVICE_FPRINTF = SERVICE_PRINTF, + SERVICE_DEVMEM = 3, + SERVICE_SANITIZER = 4 +} service_id_t; + +extern long2 +__ockl_hostcall_preview(uint service_id, ulong arg0, ulong arg1, ulong arg2, + ulong arg3, ulong arg4, ulong arg5, ulong arg6, + ulong arg7); + +/*===--- FUNCTION CALL -----------------------------------------------------*/ + +long2 +__ockl_call_host_function(ulong fptr, ulong arg0, ulong arg1, ulong arg2, + ulong arg3, ulong arg4, ulong arg5, ulong arg6) +{ + return __ockl_hostcall_preview(SERVICE_FUNCTION_CALL, fptr, arg0, arg1, + arg2, arg3, arg4, arg5, arg6); +} + +/*===--- MESSAGES ----------------------------------------------------------*/ + +/** \brief Concatenating hostcalls into a message + * + * A message is a stream of 64-bit integers transmitted as a series + * of hostcall invocations by the device code. Although the hostcall + * is "warp-wide", the message for each workitem is distinct. + * + * Of the eight uint64_t arguments in hostcall, the first argument is + * used as the message descriptor, while the rest are used for + * message contents. The descriptor consists of the following fields: + * + * - Bit 0 is the BEGIN flag. + * - Bit 1 is the END flag. + * - Bits 2-4 are reserved and must be zero. + * - Bits 5-7 indicate the number of elements being transmitted. + * - Bits 8-63 contain a 56-bit message ID. + * + * A hostcall with the BEGIN flag set in the descriptor indicates the + * start of a new message. A hostcall with the END flag set indicates + * the end of a message. A single hostcall can have both flags set if + * the message fits in the payload of a single hostcall. Each + * hostcall indicates the number of uint64_t elements in the payload + * that contain data to be appended to the message. + * + * When the accumulator receives a hostcall with the BEGIN flag set, + * it allocates a new message ID, which is transmitted to the device + * via the first return value in the hostcall. Every subsequent + * hostcall containing the same message ID appends its payload to + * that message. The message is said to be "active" until a + * corresponding END hostcall is received. + * + * When the accumulator receives a hostcall with the END flag set, it + * invokes the corresponding message handler on the contents of the + * accumulated message, and then discards the message. The handler + * may return up to two uint64_t values, that are transmitted to the + * device via the return value of the last hostcall. + * + * Behaviour is undefined in each of the following cases: + * - An END packet is received with a non-existent message ID, or with + * the ID of a message that has previously been END'ed. + * - No END packet is received for an active message. + * - Any of the reserved bits are non-zero. + * - Different hostcalls indicate the same active message ID but a + * different service. + */ + +/** Enums that describe the message descriptor fields. + */ +typedef enum { + DESCRIPTOR_OFFSET_FLAG_BEGIN = 0, + DESCRIPTOR_OFFSET_FLAG_END = 1, + DESCRIPTOR_OFFSET_RESERVED0 = 2, + DESCRIPTOR_OFFSET_LEN = 5, + DESCRIPTOR_OFFSET_ID = 8 +} descriptor_offset_t; + +typedef enum { + DESCRIPTOR_WIDTH_FLAG_BEGIN = 1, + DESCRIPTOR_WIDTH_FLAG_END = 1, + DESCRIPTOR_WIDTH_RESERVED0 = 3, + DESCRIPTOR_WIDTH_LEN = 3, + DESCRIPTOR_WIDTH_ID = 56 +} descriptor_width_t; + +static ulong +msg_set_len(ulong pd, uint len) +{ + ulong reset_mask = + ~(((1UL << DESCRIPTOR_WIDTH_LEN) - 1) << DESCRIPTOR_OFFSET_LEN); + return (pd & reset_mask) | ((ulong)len << DESCRIPTOR_OFFSET_LEN); +} + +static ulong +msg_set_begin_flag(ulong pd) +{ + return pd | (1UL << DESCRIPTOR_OFFSET_FLAG_BEGIN); +} + +static ulong +msg_reset_begin_flag(ulong pd) +{ + return pd & (~(1UL << DESCRIPTOR_OFFSET_FLAG_BEGIN)); +} + +static ulong +msg_get_end_flag(ulong pd) +{ + return pd & (1UL << DESCRIPTOR_OFFSET_FLAG_END); +} + +static ulong +msg_reset_end_flag(ulong pd) +{ + return pd & (~(1UL << DESCRIPTOR_OFFSET_FLAG_END)); +} + +static ulong +msg_set_end_flag(ulong pd) +{ + return pd | (1UL << DESCRIPTOR_OFFSET_FLAG_END); +} + +static long2 +append_bytes(uint service_id, ulong msg_desc, const uchar *data, uint len) +{ + msg_desc = msg_set_len(msg_desc, (len + 7) / 8); + +#define PACK_ULONG(ARG) \ + ulong ARG = 0; \ + if (len >= 8) { \ + ARG = (ulong)data[0] | ((ulong)data[1] << 8) | \ + ((ulong)data[2] << 16) | ((ulong)data[3] << 24) | \ + ((ulong)data[4] << 32) | ((ulong)data[5] << 40) | \ + ((ulong)data[6] << 48) | ((ulong)data[7] << 56); \ + len -= 8; \ + data += 8; \ + } else { \ + for (uint ii = 0; ii != len; ++ii) { \ + ARG |= (ulong)data[ii] << (ii * 8); \ + } \ + len = 0; \ + } + + PACK_ULONG(arg1); + PACK_ULONG(arg2); + PACK_ULONG(arg3); + PACK_ULONG(arg4); + PACK_ULONG(arg5); + PACK_ULONG(arg6); + PACK_ULONG(arg7); + + return __ockl_hostcall_preview(service_id, msg_desc, arg1, arg2, arg3, arg4, + arg5, arg6, arg7); +} + +/** \brief Append an array of bytes to a message. + * \param service_id Identifier for the target host-side service. + * \param msg_desc Message descriptor for a new or existing message. + * \param data Pointer to an array of bytes. + * \param len Length of the array. + * \return Values depend on the state of the message. + * + * The function can transmit a byte array of arbitrary length, but + * during transmission, the array is padded with zeroes until the + * length is a multiple of eight bytes. Only the array contents are + * transmitted, and not the length. + * + * If the END flag is set, the function returns two long values + * received from the host message handler. Otherwise, the first + * return value is the message descriptor to be used for a subsequent + * message call, while the second return value is not defined. + */ +static long2 +message_append_bytes(uint service_id, ulong msg_desc, const uchar *data, + ulong len) +{ + ulong end_flag = msg_get_end_flag(msg_desc); + long2 retval = {0, 0}; + retval.x = msg_reset_end_flag(msg_desc); + + do { + uint plen = len; + if (len > 56) { + plen = 56; + } else { + retval.x |= end_flag; + } + retval = append_bytes(service_id, retval.x, data, plen); + len -= plen; + data += plen; + } while (len != 0); + + return retval; +} + +/** \brief Append up to seven ulong values to a message. + * \param service_id Identifier for the target host-side service. + * \param msg_desc Message descriptor for a new or existing message. + * \param num_args Number of arguments to be appended (maximum seven). + * \param arg[0..6] Arguments to be appended. + * \return Values depend on the state of the message. + * + * Only the first #num_args arguments are appended to the + * message. The remaining arguments are ignored. Behaviour is + * undefined if #num_args is greater then seven. + * + * If the END flag is set, the function returns two uint64_t values + * received from the host message handler. Otherwise, the first + * return value is the message descriptor to be used for a subsequent + * message call, while the second return value is not defined. + */ +static long2 +message_append_args(uint service_id, ulong msg_desc, uint num_args, ulong arg0, + ulong arg1, ulong arg2, ulong arg3, ulong arg4, ulong arg5, + ulong arg6) +{ + msg_desc = msg_set_len(msg_desc, num_args); + + return __ockl_hostcall_preview(service_id, msg_desc, arg0, arg1, arg2, arg3, + arg4, arg5, arg6); +} + +/*===--- FPRINTF -----------------------------------------------------------*/ + +typedef enum { + FPRINTF_CTRL_STDOUT = 0, + FPRINTF_CTRL_STDERR = 1 +} fprintf_ctrl_t; + +static inline ulong +begin_fprintf(fprintf_ctrl_t flags) +{ + // The two standard output streams stderr and stdout are indicated + // using the lowest bits in the control qword. For now, all other + // bits are required to be zero. + const ulong msg_desc = msg_set_begin_flag(0); + ulong control = (ulong)flags; + + long2 retval = + message_append_args(SERVICE_FPRINTF, msg_desc, + /* num_args = */ 1, control, 0, 0, 0, 0, 0, 0); + return retval.x; +} + +/** \brief Begin a new fprintf message for stdout. + * \return Message descriptor for a new printf invocation. + */ +ulong +__ockl_fprintf_stdout_begin() +{ + return begin_fprintf(FPRINTF_CTRL_STDOUT); +} + +/** \brief Begin a new fprintf message for stderr. + * \return Message descriptor for a new printf invocation. + */ +ulong +__ockl_fprintf_stderr_begin() +{ + return begin_fprintf(FPRINTF_CTRL_STDERR); +} + +/** \brief Append up to seven arguments to the fprintf message. + * \param msg_desc Message descriptor for the current fprintf. + * \param num_args Number of arguments to be appended (maximum seven). + * \param value0... The argument values to be appended. + * \param is_last If non-zero, this causes the fprintf to be completed. + * \return Value depends on #is_last. + * + * Only the first #num_args arguments are appended to the + * message. The remaining arguments are ignored. Behaviour is + * undefined if #num_args is greater then seven. + * + * If #is_last is zero, the function returns a message desciptor that + * must be used by a subsequent call to any __ockl_fprintf* + * function. If #is_last is non-zero, the function causes the current + * fprintf to be completed on the host-side, and returns the value + * returned by that fprintf. + */ +ulong +__ockl_fprintf_append_args(ulong msg_desc, uint num_args, ulong value0, + ulong value1, ulong value2, ulong value3, + ulong value4, ulong value5, ulong value6, + uint is_last) +{ + if (is_last) { + msg_desc = msg_set_end_flag(msg_desc); + } + + long2 retval = + message_append_args(SERVICE_FPRINTF, msg_desc, num_args, value0, value1, + value2, value3, value4, value5, value6); + return retval.x; +} + +/** \brief Append a null-terminated string to the fprintf message. + * \param msg_desc Message descriptor for the current fprintf. + * \param data Pointer to the string. + * \param length Number of bytes, including the null terminator. + * \param is_last If non-zero, this causes the fprintf to be completed. + * \return Value depends on #is_last. + * + * The function appends a single null-terminated string to a current + * fprintf message, including the final null character. The host-side + * can use the bytes as a null-terminated string in place, without + * having to first copy the string and then append the null + * terminator. + * + * #length itself is not transmitted. Behaviour is undefined if + * #length does not include the final null character. #data may + * be a null pointer, in which case, #length is ignored and a single + * zero is transmitted. This makes the nullptr indistinguishable from + * an empty string to the host-side receiver. + * + * The call to message_append_args() ensures that during + * transmission, the string is null-padded to a multiple of eight. + * + * If #is_last is zero, the function returns a message desciptor that + * must be used by a subsequent call to any __ockl_fprintf* + * function. If #is_last is non-zero, the function causes the current + * fprintf to be completed on the host-side, and returns the value + * returned by that fprintf. + */ +ulong +__ockl_fprintf_append_string_n(ulong msg_desc, const char *data, ulong length, + uint is_last) +{ + long2 retval = {0, 0}; + + if (is_last) { + msg_desc = msg_set_end_flag(msg_desc); + } + + if (!data) { + retval = message_append_args(SERVICE_FPRINTF, msg_desc, 1, 0, 0, 0, 0, 0, + 0, 0); + return retval.x; + } + + retval = message_append_bytes(SERVICE_FPRINTF, msg_desc, (const uchar *)data, + length); + return retval.x; +} + +/*===--- PRINTF ------------------------------------------------------------*/ +/* DEPRECATED. Wrappers that should be removed eventually. */ + +ulong +__ockl_printf_begin(ulong ignored /* used to be version */) +{ + return __ockl_fprintf_stdout_begin(); +} + +ulong +__ockl_printf_append_args(ulong msg_desc, uint num_args, ulong value0, + ulong value1, ulong value2, ulong value3, + ulong value4, ulong value5, ulong value6, + uint is_last) +{ + return __ockl_fprintf_append_args(msg_desc, num_args, value0, value1, + value2, value3, value4, value5, value6, + is_last); +} + +ulong +__ockl_printf_append_string_n(ulong msg_desc, const char *data, ulong length, + uint is_last) +{ + return __ockl_fprintf_append_string_n(msg_desc, data, length, is_last); +} + + +/*---------------- SANITIZER SERVICE ---------------------------------*/ + +WEAK_ATTR void +__ockl_sanitizer_report(ulong addr, ulong pc, ulong wgidx, ulong wgidy, + ulong wgidz, ulong wave_id, ulong is_read, ulong access_size) +{ + long2 value = __ockl_hostcall_preview(SERVICE_SANITIZER, addr, pc, + wgidx, wgidy, wgidz, wave_id, is_read, access_size); + (void)value; +} + +/*===--- DEVMEM ----------------------------------------------------------*/ + +WEAK_ATTR ulong +__ockl_devmem_request(ulong addr, ulong size) +{ + long2 result = __ockl_hostcall_preview(SERVICE_DEVMEM, addr, size, 0, 0, 0, 0, 0, 0); + return (ulong)result.x; +} + diff --git a/amd/device-libs/ockl/src/sub_sat.cl b/amd/device-libs/ockl/src/sub_sat.cl new file mode 100644 index 0000000000000..5498ceb781625 --- /dev/null +++ b/amd/device-libs/ockl/src/sub_sat.cl @@ -0,0 +1,41 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +__attribute__((const)) int +OCKL_MANGLE_I32(sub_sat)(int x, int y) +{ + int s; + bool c = __builtin_ssub_overflow(x, y, &s); + return c ? (x < 0 ? INT_MIN : INT_MAX) : s; +} + +__attribute__((const)) uint +OCKL_MANGLE_U32(sub_sat)(uint x, uint y) +{ + uint s; + bool c = __builtin_usub_overflow(x, y, &s); + return c ? 0U : s; +} + +__attribute__((const)) long +OCKL_MANGLE_I64(sub_sat)(long x, long y) +{ + long s; + bool c = __builtin_ssubl_overflow(x, y, &s); + return c ? (x < 0 ? LONG_MIN : LONG_MAX) : s; +} + +__attribute__((const)) ulong +OCKL_MANGLE_U64(sub_sat)(ulong x, ulong y) +{ + ulong s; + bool c = __builtin_usubl_overflow(x, y, &s); + return c ? 0UL : s; +} + diff --git a/amd/device-libs/ockl/src/toas.cl b/amd/device-libs/ockl/src/toas.cl new file mode 100644 index 0000000000000..a121c1c2adcdc --- /dev/null +++ b/amd/device-libs/ockl/src/toas.cl @@ -0,0 +1,44 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" +__attribute__((const)) +bool +OCKL_MANGLE_T(is_local,addr)(const void *a) +{ + return __builtin_amdgcn_is_shared(a); +} + +__attribute__((const)) +bool +OCKL_MANGLE_T(is_private,addr)(const void *a) +{ + return __builtin_amdgcn_is_private(a); +} + +__attribute__((const)) __global void * +OCKL_MANGLE_T(to,global)(void *a) +{ + return (OCKL_MANGLE_T(is_local,addr)(a) | + OCKL_MANGLE_T(is_private,addr)(a)) ? + (__global void *)0 : (__global void*)a; +} + +__attribute__((const)) __local void * +OCKL_MANGLE_T(to,local)(void *a) +{ + return OCKL_MANGLE_T(is_local,addr)(a) ? + (__local void *)a : (__local void *)0; +} + +__attribute__((const)) __private void * +OCKL_MANGLE_T(to,private)(void *a) +{ + return OCKL_MANGLE_T(is_private,addr)(a) ? + (__private void *)a : (__private void *)0; +} + diff --git a/amd/device-libs/ockl/src/wait.cl b/amd/device-libs/ockl/src/wait.cl new file mode 100644 index 0000000000000..2bd720a187a50 --- /dev/null +++ b/amd/device-libs/ockl/src/wait.cl @@ -0,0 +1,55 @@ + +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" +#include "oclc.h" + +void +OCKL_MANGLE_T(rtcwait,u32)(uint ticks) +{ + ulong now = __ockl_steadyctr_u64(); + ulong end = now + __builtin_amdgcn_readfirstlane(ticks); + + if (__oclc_ISA_version >= 9000) { + while (end > now + 1625) { + __builtin_amdgcn_s_sleep(127); + now = __ockl_steadyctr_u64(); + } + + while (end > now + 806) { + __builtin_amdgcn_s_sleep(63); + now = __ockl_steadyctr_u64(); + } + + while (end > now + 396) { + __builtin_amdgcn_s_sleep(31); + now = __ockl_steadyctr_u64(); + } + } + + while (end > now + 192) { + __builtin_amdgcn_s_sleep(15); + now = __ockl_steadyctr_u64(); + } + + while (end > now + 89) { + __builtin_amdgcn_s_sleep(7); + now = __ockl_steadyctr_u64(); + } + + while (end > now + 38) { + __builtin_amdgcn_s_sleep(3); + now = __ockl_steadyctr_u64(); + } + + while (end > now) { + __builtin_amdgcn_s_sleep(1); + now = __ockl_steadyctr_u64(); + } +} + diff --git a/amd/device-libs/ockl/src/wfaas.cl b/amd/device-libs/ockl/src/wfaas.cl new file mode 100644 index 0000000000000..342a8a312efac --- /dev/null +++ b/amd/device-libs/ockl/src/wfaas.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "ockl.h" + +#define ATTR __attribute__((always_inline)) + +ATTR bool +OCKL_MANGLE_I32(wfany)(int e) +{ + return __builtin_amdgcn_ballot_w64(e) != 0; +} + +ATTR bool +OCKL_MANGLE_I32(wfall)(int e) +{ + return __builtin_amdgcn_ballot_w64(e) == __builtin_amdgcn_read_exec(); +} + +ATTR bool +OCKL_MANGLE_I32(wfsame)(int e) +{ + ulong u = __builtin_amdgcn_ballot_w64(e); + return (u == 0UL) | (u == __builtin_amdgcn_read_exec()); +} + diff --git a/amd/device-libs/ockl/src/wfbc.cl b/amd/device-libs/ockl/src/wfbc.cl new file mode 100644 index 0000000000000..d3bbe2d9e7a5b --- /dev/null +++ b/amd/device-libs/ockl/src/wfbc.cl @@ -0,0 +1,21 @@ + +#include "ockl.h" + + +uint +OCKL_MANGLE_U32(wfbcast)(uint a, uint i) +{ + uint j = __builtin_amdgcn_readfirstlane(i); + return __builtin_amdgcn_readlane(a, j); +} + +ulong +OCKL_MANGLE_U64(wfbcast)(ulong a, uint i) +{ + uint j = __builtin_amdgcn_readfirstlane(i); + uint2 aa = __builtin_astype(a, uint2); + aa.x = __builtin_amdgcn_readlane(aa.x, j); + aa.y = __builtin_amdgcn_readlane(aa.y, j); + return __builtin_astype(aa, ulong); +} + diff --git a/amd/device-libs/ockl/src/wfredscan.cl b/amd/device-libs/ockl/src/wfredscan.cl new file mode 100644 index 0000000000000..4da63029e4a04 --- /dev/null +++ b/amd/device-libs/ockl/src/wfredscan.cl @@ -0,0 +1,605 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" +#include "oclc.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define AS_USHORT(X) __builtin_astype(X, ushort) +#define AS_INT(X) __builtin_astype(X, int) +#define AS_UINT(X) __builtin_astype(X, uint) +#define AS_UINT2(X) __builtin_astype(X, uint2) +#define AS_LONG(X) __builtin_astype(X, long) +#define AS_ULONG(X) __builtin_astype(X, ulong) +#define AS_DOUBLE(X) __builtin_astype(X, double) +#define AS_FLOAT(X) __builtin_astype(X, float) +#define AS_HALF(X) __builtin_astype(X, half) + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +// Swizzle offset macros +#define SWIZZLE_QUAD_PERM(S0,S1,S2,S3) (uint)(0x8000 | (S3 << 6) | (S2 << 4) | (S1 << 2) | S0) +#define SWIZZLE_32_LIMITED(ANDM,ORM,XORM) (uint)((XORM << 10) | (ORM << 5) | ANDM) + +// DPP 9 bit control macros +#define DPP_QUAD_PERM(S0,S1,S2,S3) (uint)((S3 << 6) | (S2 << 4) | (S1 << 2) | S0) +#define DPP_ROW_SL(N) (uint)(0x100 | N) +#define DPP_ROW_SR(N) (uint)(0x110 | N) +#define DPP_ROW_RR(N) (uint)(0x120 | N) +#define DPP_WF_SL1 (uint)0x130 +#define DPP_WF_RL1 (uint)0x134 +#define DPP_WF_SR1 (uint)0x138 +#define DPP_WF_RR1 (uint)0x13c +#define DPP_ROW_MIRROR (uint)0x140 +#define DPP_ROW_HALF_MIRROR (uint)0x141 +#define DPP_ROW_BCAST15 (uint)0x142 +#define DPP_ROW_BCAST31 (uint)0x143 +#define DPP_ROW_SHARE(N) (uint)(0x150 | N) +#define DPP_ROW_XMASK(N) (uint)(0x160 | N) + +// Swizzle +#define uint_swizzle(X,Y) __builtin_amdgcn_ds_swizzle(X, Y) +#define ulong_swizzle(X,Y) ({ \ + uint2 __x = AS_UINT2(X); \ + uint2 __r; \ + __r.lo = uint_swizzle(__x.lo, Y); \ + __r.hi = uint_swizzle(__x.hi, Y); \ + AS_ULONG(__r); \ +}) +#define int_swizzle(X,Y) AS_INT(uint_swizzle(AS_UINT(X),Y)) +#define long_swizzle(X,Y) AS_LONG(ulong_swizzle(AS_ULONG(X),Y)) +#define float_swizzle(X,Y) AS_FLOAT(uint_swizzle(AS_UINT(X),Y)) +#define double_swizzle(X,Y) AS_DOUBLE(ulong_swizzle(AS_ULONG(X),Y)) +#define half_swizzle(X,Y) AS_HALF((ushort)uint_swizzle((uint)AS_USHORT(X),Y)) + +// DPP16 +#define uint_dpp(ID,X,C,R,B,W) __builtin_amdgcn_update_dpp(ID,X,C,R,B,W) +#define ulong_dpp(ID,X,C,R,B,W) __builtin_amdgcn_update_dpp(ID,X,C,R,B,W) +#define int_dpp(ID,X,C,R,B,W) __builtin_amdgcn_update_dpp(ID,X,C,R,B,W) +#define long_dpp(ID,X,C,R,B,W) __builtin_amdgcn_update_dpp(ID,X,C,R,B,W) +#define float_dpp(ID,X,C,R,B,W) __builtin_amdgcn_update_dpp(ID,X,C,R,B,W) +#define double_dpp(ID,X,C,R,B,W) __builtin_amdgcn_update_dpp(ID,X,C,R,B,W) +#define half_dpp(ID,X,C,R,B,W) __builtin_amdgcn_update_dpp(ID,X,C,R,B,W) + +// DPP8 +#define uint_dpp8(X,S) __builtin_amdgcn_mov_dpp8(X,S) +#define ulong_dpp8(X,S) __builtin_amdgcn_mov_dpp8(X,S) +#define int_dpp8(X,S) __builtin_amdgcn_mov_dpp8(X,S) +#define long_dpp8(X,S) __builtin_amdgcn_mov_dpp8(X,S) +#define float_dpp8(X,S) __builtin_amdgcn_mov_dpp8(X,S) +#define double_dpp8(X,S) __builtin_amdgcn_mov_dpp8(X,S) +#define half_dpp8(X,S) __builtin_amdgcn_mov_dpp8(X,S) + +// permlane16 +#define uint_permlane16(ID,X,S0,S1,W) __builtin_amdgcn_permlane16(ID,X,S0,S1,false,W) +#define ulong_permlane16(ID,X,S0,S1,W) ({ \ + uint2 __x = AS_UINT2(X); \ + uint2 __r; \ + __r.lo = uint_permlane16((uint)ID,__x.lo,S0,S1,W); \ + __r.hi = uint_permlane16((uint)(ID>>32),__x.hi,S0,S1,W); \ + AS_ULONG(__r); \ +}) +#define int_permlane16(ID,X,S0,S1,W) AS_INT(uint_permlane16(AS_UINT(ID),AS_UINT(X),S0,S1,W)) +#define long_permlane16(ID,X,S0,S1,W) AS_LONG(ulong_permlane16(AS_ULONG(ID),AS_ULONG(X),S0,S1,W)) +#define float_permlane16(ID, X,S0,S1,W) AS_FLOAT(uint_permlane16(AS_UINT(ID),AS_UINT(X),S0,S1,W)) +#define double_permlane16(ID, X,S0,S1,W) AS_DOUBLE(ulong_permlane16(AS_ULONG(ID),AS_ULONG(X),S0,S1,W)) +#define half_permlane16(ID,X,S0,S1,W) AS_HALF((ushort)uint_permlane16((uint)AS_USHORT(ID),(uint)AS_USHORT(X),S0,S1,W)) + +// permlanex16 +#define uint_permlanex16(ID,X,S0,S1,W) __builtin_amdgcn_permlanex16(ID,X,S0,S1,false,W) +#define ulong_permlanex16(ID,X,S0,S1,W) ({ \ + uint2 __x = AS_UINT2(X); \ + uint2 __r; \ + __r.lo = uint_permlanex16((uint)ID,__x.lo,S0,S1,W); \ + __r.hi = uint_permlanex16((uint)(ID>>32),__x.hi,S0,S1,W); \ + AS_ULONG(__r); \ +}) +#define int_permlanex16(ID,X,S0,S1,W) AS_INT(uint_permlanex16(AS_UINT(ID),AS_UINT(X),S0,S1,W)) +#define long_permlanex16(ID,X,S0,S1,W) AS_LONG(ulong_permlanex16(AS_ULONG(ID),AS_ULONG(X),S0,S1,W)) +#define float_permlanex16(ID, X,S0,S1,W) AS_FLOAT(uint_permlanex16(AS_UINT(ID),AS_UINT(X),S0,S1,W)) +#define double_permlanex16(ID, X,S0,S1,W) AS_DOUBLE(ulong_permlanex16(AS_ULONG(ID),AS_ULONG(X),S0,S1,W)) +#define half_permlanex16(ID,X,S0,S1,W) AS_HALF((ushort)uint_permlanex16((uint)AS_USHORT(ID),(uint)AS_USHORT(X),S0,S1,W)) + +// readlane +#define uint_readlane(X,L) __builtin_amdgcn_readlane(X,L) +#define ulong_readlane(X,L) ({ \ + uint2 __x = AS_UINT2(X); \ + uint2 __r; \ + __r.lo = uint_readlane(__x.lo, L); \ + __r.hi = uint_readlane(__x.hi, L); \ + AS_ULONG(__r); \ +}) +#define int_readlane(X,L) AS_INT(uint_readlane(AS_UINT(X),L)) +#define long_readlane(X,L) AS_LONG(ulong_readlane(AS_ULONG(X),L)) +#define float_readlane(X,L) AS_FLOAT(uint_readlane(AS_UINT(X),L)) +#define double_readlane(X,L) AS_DOUBLE(ulong_readlane(AS_ULONG(X),L)) +#define half_readlane(X,L) AS_HALF((ushort)uint_readlane((uint)AS_USHORT(X),L)) + +// Select +#define uint_sel(C,B,A) ({ \ + uint __c = C; \ + (__c & B) | (~__c & A); \ +}) +#define ulong_sel(C,B,A) ({ \ + uint __c = C; \ + uint2 __b = AS_UINT2(B); \ + uint2 __a = AS_UINT2(A); \ + uint2 __r; \ + __r.lo = (__c & __b.lo) | (~__c & __a.lo); \ + __r.hi = (__c & __b.hi) | (~__c & __a.hi); \ + AS_ULONG(__r); \ +}) +#define int_sel(C,B,A) AS_INT(uint_sel(C, AS_UINT(B), AS_UINT(A))) +#define long_sel(C,B,A) AS_LONG(ulong_sel(C, AS_ULONG(B), AS_ULONG(A))) +#define float_sel(C,B,A) AS_FLOAT(uint_sel(C, AS_UINT(B), AS_UINT(A))) +#define double_sel(C,B,A) AS_DOUBLE(ulong_sel(C, AS_ULONG(B), AS_ULONG(A))) +#define half_sel(C,B,A) AS_HALF((ushort)uint_sel(C, (uint)AS_USHORT(B), (uint)AS_USHORT(A))) + +#define uint_suf _u32 +#define int_suf _i32 +#define ulong_suf _u64 +#define long_suf _i64 +#define float_suf _f32 +#define double_suf _f64 +#define half_suf _f16 + +#define CATTR __attribute__((const)) +#define IATTR + +#define GENMIN(T) CATTR static T T##_min(T a, T b) { return a < b ? a : b; } +GENMIN(int) +GENMIN(uint) +GENMIN(long) +GENMIN(ulong) +#define float_min(A,B) __builtin_fminf(A,B) +#define double_min(A,B) __builtin_fmin(A,B) +#define half_min(A,B) __builtin_fminf16(A,B) + +#define GENMAX(T) CATTR static T T##_max(T a, T b) { return a < b ? b : a; } +GENMAX(int) +GENMAX(uint) +GENMAX(long) +GENMAX(ulong) +#define float_max(A,B) __builtin_fmaxf(A,B) +#define double_max(A,B) __builtin_fmax(A,B) +#define half_max(A,B) __builtin_fmaxf16(A,B) + +#define ADD(X,Y) (X + Y) +#define uint_add(X,Y) ADD(X,Y) +#define int_add(X,Y) ADD(X,Y) +#define ulong_add(X,Y) ADD(X,Y) +#define long_add(X,Y) ADD(X,Y) +#define float_add(X,Y) ADD(X,Y) +#define double_add(X,Y) ADD(X,Y) +#define half_add(X,Y) ADD(X,Y) + +#define OR(X,Y) (X | Y) +#define uint_or(X,Y) OR(X,Y) +#define int_or(X,Y) OR(X,Y) +#define ulong_or(X,Y) OR(X,Y) +#define long_or(X,Y) OR(X,Y) + +#define AND(X,Y) (X & Y) +#define uint_and(X,Y) AND(X,Y) +#define int_and(X,Y) AND(X,Y) +#define ulong_and(X,Y) AND(X,Y) +#define long_and(X,Y) AND(X,Y) + +#define XOR(X,Y) (X ^ Y) +#define uint_xor(X,Y) XOR(X,Y) +#define int_xor(X,Y) XOR(X,Y) +#define ulong_xor(X,Y) XOR(X,Y) +#define long_xor(X,Y) XOR(X,Y) + + +#define GENRED7_FULL(T,OP,ID,IDZ) \ +static T \ +red7_full_##T##_##OP(T x) \ +{ \ + T v, r; \ + \ + v = T##_swizzle(x, SWIZZLE_QUAD_PERM(0x1,0x0,0x3,0x2)); \ + r = T##_##OP(x, v); \ + \ + v = T##_swizzle(r, SWIZZLE_QUAD_PERM(0x2,0x3,0x0,0x1)); \ + r = T##_##OP(r, v); \ + \ + v = T##_swizzle(r, SWIZZLE_32_LIMITED(0x1f,0x00,0x04)); \ + r = T##_##OP(r, v); \ + \ + v = T##_swizzle(r, SWIZZLE_32_LIMITED(0x1f,0x00,0x08)); \ + r = T##_##OP(r, v); \ + \ + v = T##_swizzle(r, SWIZZLE_32_LIMITED(0x1f,0x00,0x10)); \ + r = T##_##OP(r, v); \ + \ + r = T##_##OP(T##_readlane(r,0), T##_readlane(r,32)); \ + \ + return r; \ +} + +#define GENRED7_PART(T,OP,ID,IDZ) \ +static T \ +red7_part_##T##_##OP(T x) \ +{ \ + T r; \ + if (IDZ) { \ + T v; \ + \ + v = T##_swizzle(x, SWIZZLE_QUAD_PERM(0x1,0x0,0x3,0x2)); \ + r = T##_##OP(x, v); \ + \ + v = T##_swizzle(r, SWIZZLE_QUAD_PERM(0x2,0x3,0x0,0x1)); \ + r = T##_##OP(r, v); \ + \ + v = T##_swizzle(r, SWIZZLE_32_LIMITED(0x1f,0x00,0x04)); \ + r = T##_##OP(r, v); \ + \ + v = T##_swizzle(r, SWIZZLE_32_LIMITED(0x1f,0x00,0x08)); \ + r = T##_##OP(r, v); \ + \ + v = T##_swizzle(r, SWIZZLE_32_LIMITED(0x1f,0x00,0x10)); \ + r = T##_##OP(r, v); \ + \ + v = T##_readlane(r, 32); \ + v = (__builtin_amdgcn_read_exec_hi() & 1) ? v : ID; \ + r = T##_##OP(T##_readlane(r, 0), v); \ + } else { \ + uint e; \ + T v, t; \ + \ + t = T##_swizzle(x, SWIZZLE_QUAD_PERM(0x1,0x0,0x3,0x2)); \ + e = uint_swizzle(~0u, SWIZZLE_QUAD_PERM(0x1,0x0,0x3,0x2)); \ + v = T##_sel(e, t, ID); \ + r = T##_##OP(x, v); \ + \ + t = T##_swizzle(r, SWIZZLE_QUAD_PERM(0x2,0x3,0x0,0x1)); \ + e = uint_swizzle(~0u, SWIZZLE_QUAD_PERM(0x2,0x3,0x0,0x1)); \ + v = T##_sel(e, t, ID); \ + r = T##_##OP(r, v); \ + \ + t = T##_swizzle(r, SWIZZLE_32_LIMITED(0x1f,0x00,0x04)); \ + e = uint_swizzle(~0u, SWIZZLE_32_LIMITED(0x1f,0x00,0x04)); \ + v = T##_sel(e, t, ID); \ + r = T##_##OP(r, v); \ + \ + t = T##_swizzle(r, SWIZZLE_32_LIMITED(0x1f,0x00,0x08)); \ + e = uint_swizzle(~0u, SWIZZLE_32_LIMITED(0x1f,0x00,0x08)); \ + v = T##_sel(e, t, ID); \ + r = T##_##OP(r, v); \ + \ + t = T##_swizzle(r, SWIZZLE_32_LIMITED(0x1f,0x00,0x10)); \ + e = uint_swizzle(~0u, SWIZZLE_32_LIMITED(0x1f,0x00,0x10)); \ + v = T##_sel(e, t, ID); \ + r = T##_##OP(r, v); \ + \ + t = T##_readlane(r, 32); \ + v = (__builtin_amdgcn_read_exec_hi() & 1) ? t : ID; \ + r = T##_##OP(T##_readlane(r, 0), v); \ + } \ + \ + return r; \ +} + +#define GENRED7(T,OP,ID,IDZ) \ + GENRED7_FULL(T,OP,ID,IDZ) \ + GENRED7_PART(T,OP,ID,IDZ) + +#define GENRED89(T,OP,ID,IDZ) \ +__attribute__((target("dpp"))) static T \ +red89_##T##_##OP(T x) \ +{ \ + T r, v; \ + \ + v = T##_dpp(ID, x, DPP_ROW_SL(1), 0xf, 0xf, IDZ); \ + r = T##_##OP(x, v); \ + \ + v = T##_dpp(ID, r, DPP_ROW_SL(2), 0xf, 0xf, IDZ); \ + r = T##_##OP(r, v); \ + \ + v = T##_dpp(ID, r, DPP_ROW_SL(4), 0xf, 0xf, IDZ); \ + r = T##_##OP(r, v); \ + \ + v = T##_dpp(ID, r, DPP_ROW_SL(8), 0xf, 0xf, IDZ); \ + r = T##_##OP(r, v); \ + \ + v = T##_dpp(ID, r, DPP_WF_SL1, 0xf, 0xf, IDZ); \ + v = T##_dpp(ID, v, DPP_ROW_MIRROR, 0xf, 0xf, IDZ); \ + r = T##_##OP(r, v); \ + \ + v = T##_readlane(r, 32); \ + v = (__builtin_amdgcn_read_exec_hi() & 1) ? v : ID; \ + r = T##_##OP(T##_readlane(r, 0), v); \ + \ + return r; \ +} + +#define GENRED10(T,OP,ID,IDZ) \ +__attribute__((target("dpp,gfx10-insts"))) static T \ +red10_##T##_##OP(T x) \ +{ \ + T r, v; \ + \ + v = T##_dpp(ID, x, DPP_ROW_SL(1), 0xf, 0xf, IDZ); \ + r = T##_##OP(x, v); \ + \ + v = T##_dpp(ID, r, DPP_ROW_SL(2), 0xf, 0xf, IDZ); \ + r = T##_##OP(r, v); \ + \ + v = T##_dpp(ID, r, DPP_ROW_SL(4), 0xf, 0xf, IDZ); \ + r = T##_##OP(r, v); \ + \ + v = T##_dpp(ID, r, DPP_ROW_SL(8), 0xf, 0xf, IDZ); \ + r = T##_##OP(r, v); \ + \ + r = T##_dpp(ID, r, DPP_ROW_SHARE(0), 0xf, 0xf, IDZ); \ + \ + v = T##_permlanex16(ID, r, 0, 0, IDZ); \ + r = T##_##OP(r, v); \ + \ + if (__oclc_wavefrontsize64) { \ + T v = T##_readlane(r, 32); \ + v = (__builtin_amdgcn_read_exec_hi() & 1) ? v : ID; \ + r = T##_##OP(T##_readlane(r, 0), v); \ + } \ + \ + return r; \ +} + +#define GENISCAN7(T,OP,ID,IDZ) \ +static T \ +iscan7_##T##_##OP(T x, uint l) \ +{ \ + T s, v; \ + \ + v = T##_swizzle(x, SWIZZLE_32_LIMITED(0x1e,0x00,0x00)); \ + v = (l & 1) ? v : ID; \ + s = T##_##OP(x, v); \ + \ + v = T##_swizzle(s, SWIZZLE_32_LIMITED(0x1c,0x01,0x00)); \ + v = (l & 2) ? v : ID; \ + s = T##_##OP(s, v); \ + \ + v = T##_swizzle(s, SWIZZLE_32_LIMITED(0x18,0x03,0x00)); \ + v = (l & 4) ? v : ID; \ + s = T##_##OP(s, v); \ + \ + v = T##_swizzle(s, SWIZZLE_32_LIMITED(0x10,0x07,0x00)); \ + v = (l & 8) ? v : ID; \ + s = T##_##OP(s, v); \ + \ + v = T##_swizzle(s, SWIZZLE_32_LIMITED(0x00,0x0f,0x00)); \ + v = (l & 16) ? v : ID; \ + s = T##_##OP(s, v); \ + \ + v = T##_readlane(s, 31); \ + v = l > 31 ? v : ID; \ + s = T##_##OP(s, v); \ + \ + return s; \ +} + +#define GENISCAN89(T,OP,ID,IDZ) \ +__attribute__((target("dpp"))) static T \ +iscan89_##T##_##OP(T x, uint l) \ +{ \ + T s, v; \ + \ + v = T##_dpp(ID, x, DPP_ROW_SR(1), 0xf, 0xf, IDZ); \ + s = T##_##OP(x, v); \ + \ + v = T##_dpp(ID, s, DPP_ROW_SR(2), 0xf, 0xf, IDZ); \ + s = T##_##OP(s, v); \ + \ + v = T##_dpp(ID, s, DPP_ROW_SR(4), 0xf, 0xf, IDZ); \ + s = T##_##OP(s, v); \ + \ + v = T##_dpp(ID, s, DPP_ROW_SR(8), 0xf, 0xf, IDZ); \ + s = T##_##OP(s, v); \ + \ + v = T##_dpp(ID, s, DPP_ROW_BCAST15, 0xa, 0xf, false); \ + s = T##_##OP(s, v); \ + \ + v = T##_dpp(ID, s, DPP_ROW_BCAST31, 0xc, 0xf, false); \ + s = T##_##OP(s, v); \ + \ + return s; \ +} + +#define GENISCAN10(T,OP,ID,IDZ) \ +__attribute__((target("dpp,gfx10-insts"))) static T \ +iscan10_##T##_##OP(T x, uint l) \ +{ \ + T s, v; \ + \ + v = T##_dpp(ID, x, DPP_ROW_SR(1), 0xf, 0xf, IDZ); \ + s = T##_##OP(x, v); \ + \ + v = T##_dpp(ID, s, DPP_ROW_SR(2), 0xf, 0xf, IDZ); \ + s = T##_##OP(s, v); \ + \ + v = T##_dpp(ID, s, DPP_ROW_SR(4), 0xf, 0xf, IDZ); \ + s = T##_##OP(s, v); \ + \ + v = T##_dpp(ID, s, DPP_ROW_SR(8), 0xf, 0xf, IDZ); \ + s = T##_##OP(s, v); \ + \ + v = T##_permlanex16(ID, s, 0xffffffff, 0xffffffff, IDZ); \ + v = (l & 0x10) ? v : ID; \ + s = T##_##OP(s, v); \ + \ + if (__oclc_wavefrontsize64) { \ + v = T##_readlane(s, 31); \ + v = l > 31 ? v : ID; \ + s = T##_##OP(s, v); \ + } \ + \ + return s; \ +} + +#define GENSR1_7(T,OP,ID,IDZ) \ +static T \ +sr1_7_##T##_##OP(T s, uint l) \ +{ \ + T v; \ + T t = s; \ + \ + s = T##_swizzle(t, SWIZZLE_QUAD_PERM(0x0,0x0,0x1,0x2)); \ + \ + v = T##_swizzle(t, SWIZZLE_32_LIMITED(0x18, 0x03, 0x00)); \ + s = (l & 0x7) == 0x4 ? v : s; \ + \ + v = T##_swizzle(t, SWIZZLE_32_LIMITED(0x10, 0x07, 0x00)); \ + s = (l & 0xf) == 0x8 ? v : s; \ + \ + v = T##_swizzle(t, SWIZZLE_32_LIMITED(0x00, 0x0f, 0x00)); \ + s = (l & 0x1f) == 0x10 ? v : s; \ + \ + v = T##_readlane(t, 31); \ + s = l == 32 ? v : s; \ + \ + s = l == 0 ? ID : s; \ + \ + return s; \ +} + + +#define GENSR1_89(T,OP,ID,IDZ) \ +__attribute__((target("dpp"))) static T \ +sr1_89_##T##_##OP(T s, uint l) \ +{ \ + return T##_dpp(ID, s, DPP_WF_SR1, 0xf, 0xf, IDZ); \ +} + +#define GENSR1_10(T,OP,ID,IDZ) \ +__attribute((target("dpp,gfx10-insts"))) static T \ +sr1_10_##T##_##OP(T s, uint l) \ +{ \ + T t = T##_dpp(ID, s, DPP_ROW_SR(1), 0xf, 0xf, IDZ); \ + T v = T##_permlanex16(ID, s, 0xffffffff, 0xffffffff, IDZ); \ + if (__oclc_wavefrontsize64) { \ + T w = T##_readlane(s, 31); \ + v = l == 32 ? w : v; \ + s = ((l == 32) | ((l & 0x1f) == 0x10)) ? v : t; \ + } else {\ + s = l == 16 ? v : t; \ + } \ + \ + return s; \ +} + +IATTR static bool +fullwave(void) +{ + if (__oclc_wavefrontsize64) { + return __builtin_popcountl(__builtin_amdgcn_read_exec()) == 64; + } else { + return __builtin_popcount(__builtin_amdgcn_read_exec_lo()) == 32; + } +} + +#define GENRED(T,OP,ID,IDZ) \ +GENRED7(T,OP,ID,IDZ) \ +GENRED89(T,OP,ID,IDZ) \ +GENRED10(T,OP,ID,IDZ) \ +IATTR T \ +C(__ockl_wfred_,C(OP,T##_suf))(T x) \ +{ \ + T r; \ + if (__oclc_ISA_version < 8000) { \ + if (fullwave()) { \ + r = red7_full_##T##_##OP(x); \ + } else { \ + r = red7_part_##T##_##OP(x); \ + } \ + } else if (__oclc_ISA_version < 10000) { \ + r = red89_##T##_##OP(x); \ + } else { \ + r = red10_##T##_##OP(x); \ + } \ + return r; \ +} + +#define GENSCAN(T,OP,ID,IDZ) \ +GENISCAN7(T,OP,ID,IDZ) \ +GENISCAN89(T,OP,ID,IDZ) \ +GENISCAN10(T,OP,ID,IDZ) \ +GENSR1_7(T,OP,ID,IDZ) \ +GENSR1_89(T,OP,ID,IDZ) \ +GENSR1_10(T,OP,ID,IDZ) \ +IATTR T \ +C(__ockl_wfscan_,C(OP,T##_suf))(T x, bool inclusive) \ +{ \ + T s; \ + uint l = __ockl_lane_u32(); \ + \ + if (__oclc_ISA_version < 8000) { \ + s = iscan7_##T##_##OP(x, l); \ + } else if (__oclc_ISA_version < 10000) { \ + s = iscan89_##T##_##OP(x, l); \ + } else { \ + s = iscan10_##T##_##OP(x, l); \ + } \ + \ + if (!inclusive) { \ + if (__oclc_ISA_version < 8000) { \ + s = sr1_7_##T##_##OP(s, l); \ + } else if (__oclc_ISA_version < 10000) { \ + s = sr1_89_##T##_##OP(s, l); \ + } else { \ + s = sr1_10_##T##_##OP(s, l); \ + } \ + } \ + \ + return s; \ +} + +#define GEN(T,OP,ID,IDZ) \ + GENRED(T,OP,ID,IDZ) \ + GENSCAN(T,OP,ID,IDZ) + +GEN(int,add,0,1) +GEN(uint,add,0u,1) +GEN(long,add,0L,1) +GEN(ulong,add,0UL,1) +GEN(float,add,0.0f,1) +GEN(double,add,0.0,1) +GEN(half,add,0.0h,1) + +GEN(int,min,INT_MAX,0) +GEN(uint,min,UINT_MAX,0) +GEN(long,min,LONG_MAX,0) +GEN(ulong,min,ULONG_MAX,0) +GEN(float,min,INFINITY,0) +GEN(double,min,(double)INFINITY,0) +GEN(half,min,(half)INFINITY,0) + +GEN(int,max,INT_MIN,0) +GEN(uint,max,0u,1) +GEN(long,max,LONG_MIN,0) +GEN(ulong,max,0UL,1) +GEN(float,max,-INFINITY,0) +GEN(double,max,-(double)INFINITY,0) +GEN(half,max,-(half)INFINITY,0) + +GEN(int,and,~0,0) +GEN(uint,and,~0u,0) +GEN(long,and,~0L,0) +GEN(ulong,and,~0UL,0) + +GEN(int,or,0,1) +GEN(uint,or,0u,1) +GEN(long,or,0L,1) +GEN(ulong,or,0UL,1) + +GEN(int,xor,0,1) +GEN(uint,xor,0u,1) +GEN(long,xor,0L,1) +GEN(ulong,xor,0UL,1) + diff --git a/amd/device-libs/ockl/src/wgred.cl b/amd/device-libs/ockl/src/wgred.cl new file mode 100644 index 0000000000000..8d507107b96e4 --- /dev/null +++ b/amd/device-libs/ockl/src/wgred.cl @@ -0,0 +1,71 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "ockl.h" +#include "wgscratch.h" + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define reduce_add __opencl_atomic_fetch_add +#define reduce_and __opencl_atomic_fetch_and +#define reduce_or __opencl_atomic_fetch_or + +#define int_suf _i32 + +static uint +my_num_sub_groups(void) +{ + uint wgs = __ockl_mul24_i32((uint)__ockl_get_local_size(2), + __ockl_mul24_i32((uint)__ockl_get_local_size(1), + (uint)__ockl_get_local_size(0))); + return (wgs + OCLC_WAVEFRONT_SIZE - 1) >> __oclc_wavefrontsize_log2; +} + +static uint +my_sub_group_id(void) +{ + return (uint)__ockl_get_local_linear_id() >> __oclc_wavefrontsize_log2; +} + +static void +my_barrier(void) +{ + __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup"); + __builtin_amdgcn_s_barrier(); + __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup"); +} + +#define AGEN(T,OP) \ +T \ +C(__ockl_wgred_,C(OP,T##_suf))(int a) \ +{ \ + uint n = my_num_sub_groups(); \ + a = C(__ockl_wfred_##OP,T##_suf)(a); \ + if (n == 1) \ + return a; \ + \ + __local atomic_##T *p = (__local atomic_##T *)__get_scratch_lds(); \ + uint l = __ockl_lane_u32(); \ + uint i = my_sub_group_id(); \ + \ + if ((i == 0) & (l == 0)) \ + __opencl_atomic_store(p, a, memory_order_relaxed, memory_scope_work_group); \ + \ + my_barrier(); \ + if ((i != 0) & (l == 0)) \ + reduce_##OP(p, a, memory_order_relaxed, memory_scope_work_group); \ + my_barrier(); \ + a = __opencl_atomic_load(p, memory_order_relaxed, memory_scope_work_group); \ + my_barrier(); \ + return a; \ +} + +AGEN(int,add) +AGEN(int,and) +AGEN(int,or) diff --git a/amd/device-libs/ockl/src/wgscratch.ll b/amd/device-libs/ockl/src/wgscratch.ll new file mode 100644 index 0000000000000..50442ea63605f --- /dev/null +++ b/amd/device-libs/ockl/src/wgscratch.ll @@ -0,0 +1,11 @@ +target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" +target triple = "amdgcn-amd-amdhsa" + +; 1024 work-items means up to 32 work groups +@__scratch_lds = linkonce_odr hidden addrspace(3) global [32 x i64] poison, align 8 + +define protected noundef align 8 dereferenceable(256) ptr addrspace(3) @__get_scratch_lds() #0 { + ret ptr addrspace(3) @__scratch_lds +} + +attributes #0 = { alwaysinline mustprogress nofree norecurse nosync nounwind speculatable willreturn memory(none) } diff --git a/amd/device-libs/ockl/src/workitem.cl b/amd/device-libs/ockl/src/workitem.cl new file mode 100644 index 0000000000000..95612e1215f05 --- /dev/null +++ b/amd/device-libs/ockl/src/workitem.cl @@ -0,0 +1,476 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "device_amd_hsa.h" + +#define ATTR __attribute__((const)) +#define OLD_ABI __oclc_ABI_version < 500 + +#define IMPLICITARG(T) ((__constant T *)__builtin_amdgcn_implicitarg_ptr()) + +ATTR static size_t +get_global_offset_x(void) +{ + if (OLD_ABI) { + return IMPLICITARG(ulong)[0]; + } else { + return IMPLICITARG(ulong)[5]; + } +} + +ATTR static size_t +get_global_offset_y(void) +{ + if (OLD_ABI) { + return IMPLICITARG(ulong)[1]; + } else { + return IMPLICITARG(ulong)[6]; + } +} + +ATTR static size_t +get_global_offset_z(void) +{ + if (OLD_ABI) { + return IMPLICITARG(ulong)[2]; + } else { + return IMPLICITARG(ulong)[7]; + } +} + +ATTR static size_t +get_global_size_x(void) +{ + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + return p->grid_size_x; + } else { + return IMPLICITARG(uint)[0]*IMPLICITARG(ushort)[6] + IMPLICITARG(ushort)[9]; + return 0; + } +} + +ATTR static size_t +get_global_size_y(void) +{ + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + return p->grid_size_y; + } else { + return IMPLICITARG(uint)[1]*IMPLICITARG(ushort)[7] + IMPLICITARG(ushort)[10]; + } +} + +ATTR static size_t +get_global_size_z(void) +{ + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + return p->grid_size_z; + } else { + return IMPLICITARG(uint)[2]*IMPLICITARG(ushort)[8] + IMPLICITARG(ushort)[11]; + return 0; + } +} + +ATTR static size_t +get_global_id_x(void) +{ + uint l = __builtin_amdgcn_workitem_id_x(); + uint g = __builtin_amdgcn_workgroup_id_x(); + uint s; + if (OLD_ABI) { + s = __builtin_amdgcn_workgroup_size_x(); + } else { + s = IMPLICITARG(ushort)[6]; + } + return (g*s + l) + get_global_offset_x(); +} + +ATTR static size_t +get_global_id_y(void) +{ + uint l = __builtin_amdgcn_workitem_id_y(); + uint g = __builtin_amdgcn_workgroup_id_y(); + uint s; + if (OLD_ABI) { + s = __builtin_amdgcn_workgroup_size_y(); + } else { + s = IMPLICITARG(ushort)[7]; + } + return (g*s + l) + get_global_offset_y(); +} + +ATTR static size_t +get_global_id_z(void) +{ + uint l = __builtin_amdgcn_workitem_id_z(); + uint g = __builtin_amdgcn_workgroup_id_z(); + uint s; + if (OLD_ABI) { + s = __builtin_amdgcn_workgroup_size_z(); + } else { + s = IMPLICITARG(ushort)[8]; + } + return (g*s + l) + get_global_offset_z(); +} + +ATTR static size_t +get_local_size_x(void) +{ + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + uint group_id = __builtin_amdgcn_workgroup_id_x(); + uint group_size = __builtin_amdgcn_workgroup_size_x(); + uint grid_size = p->grid_size_x; + uint r = grid_size - group_id * group_size; + return (r < group_size) ? r : group_size; + } else { + return __builtin_amdgcn_workgroup_id_x() < IMPLICITARG(uint)[0] ? IMPLICITARG(ushort)[6] : IMPLICITARG(ushort)[9]; + } +} + +ATTR static size_t +get_local_size_y(void) +{ + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + uint group_id = __builtin_amdgcn_workgroup_id_y(); + uint group_size = __builtin_amdgcn_workgroup_size_y(); + uint grid_size = p->grid_size_y; + uint r = grid_size - group_id * group_size; + return (r < group_size) ? r : group_size; + } else { + return __builtin_amdgcn_workgroup_id_y() < IMPLICITARG(uint)[1] ? IMPLICITARG(ushort)[7] : IMPLICITARG(ushort)[10]; + } +} + +ATTR static size_t +get_local_size_z(void) +{ + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + uint group_id = __builtin_amdgcn_workgroup_id_z(); + uint group_size = __builtin_amdgcn_workgroup_size_z(); + uint grid_size = p->grid_size_z; + uint r = grid_size - group_id * group_size; + return (r < group_size) ? r : group_size; + } else { + return __builtin_amdgcn_workgroup_id_z() < IMPLICITARG(uint)[2] ? IMPLICITARG(ushort)[8] : IMPLICITARG(ushort)[11]; + } +} + +ATTR static size_t +get_enqueued_local_size_x(void) +{ + if (OLD_ABI) { + return __builtin_amdgcn_workgroup_size_x(); + } else { + return IMPLICITARG(ushort)[6]; + } +} + +ATTR static size_t +get_enqueued_local_size_y(void) +{ + if (OLD_ABI) { + return __builtin_amdgcn_workgroup_size_y(); + } else { + return IMPLICITARG(ushort)[7]; + } +} + +ATTR static size_t +get_enqueued_local_size_z(void) +{ + if (OLD_ABI) { + return __builtin_amdgcn_workgroup_size_z(); + } else { + return IMPLICITARG(ushort)[8]; + } +} + +ATTR static size_t +get_num_groups_x(void) +{ + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + uint n = p->grid_size_x; + uint d = __builtin_amdgcn_workgroup_size_x(); + uint q = n / d; + return q + (n > q*d); + } else { + return IMPLICITARG(uint)[0] + (IMPLICITARG(ushort)[9] > 0); + } +} + +ATTR static size_t +get_num_groups_y(void) +{ + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + uint n = p->grid_size_y; + uint d = __builtin_amdgcn_workgroup_size_y(); + uint q = n / d; + return q + (n > q*d); + } else { + return IMPLICITARG(uint)[1] + (IMPLICITARG(ushort)[10] > 0); + } +} + +ATTR static size_t +get_num_groups_z(void) +{ + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + uint n = p->grid_size_z; + uint d = __builtin_amdgcn_workgroup_size_z(); + uint q = n / d; + return q + (n > q*d); + } else { + return IMPLICITARG(uint)[2] + (IMPLICITARG(ushort)[11] > 0); + } +} + +ATTR static uint +get_work_dim_(void) +{ + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + return p->setup; + } else { + return IMPLICITARG(ushort)[32]; + } +} + +ATTR static size_t +get_global_linear_id_x(void) +{ + uint l0 = __builtin_amdgcn_workitem_id_x(); + uint g0 = __builtin_amdgcn_workgroup_id_x(); + uint s0; + if (OLD_ABI) { + s0 = __builtin_amdgcn_workgroup_size_x(); + } else { + s0 = IMPLICITARG(ushort)[6]; + } + return g0*s0 + l0; +} + +ATTR static size_t +get_global_linear_id_y(void) +{ + uint l0 = __builtin_amdgcn_workitem_id_x(); + uint l1 = __builtin_amdgcn_workitem_id_y(); + uint g0 = __builtin_amdgcn_workgroup_id_x(); + uint g1 = __builtin_amdgcn_workgroup_id_y(); + uint s0, s1; + uint n0; + + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + s0 = __builtin_amdgcn_workgroup_size_x(); + s1 = __builtin_amdgcn_workgroup_size_y(); + n0 = p->grid_size_x; + } else { + s0 = IMPLICITARG(ushort)[6]; + s1 = IMPLICITARG(ushort)[7]; + n0 = IMPLICITARG(uint)[0]*s0 + IMPLICITARG(ushort)[9]; + } + uint i0 = g0*s0 + l0; + uint i1 = g1*s1 + l1; + return (size_t)i1 * (size_t)n0 + i0; +} + +ATTR static size_t +get_global_linear_id_z(void) +{ + uint l0 = __builtin_amdgcn_workitem_id_x(); + uint l1 = __builtin_amdgcn_workitem_id_y(); + uint l2 = __builtin_amdgcn_workitem_id_z(); + uint g0 = __builtin_amdgcn_workgroup_id_x(); + uint g1 = __builtin_amdgcn_workgroup_id_y(); + uint g2 = __builtin_amdgcn_workgroup_id_z(); + uint s0, s1, s2; + uint n0, n1; + + if (OLD_ABI) { + __constant hsa_kernel_dispatch_packet_t *p = __builtin_amdgcn_dispatch_ptr(); + s0 = __builtin_amdgcn_workgroup_size_x(); + s1 = __builtin_amdgcn_workgroup_size_y(); + s2 = __builtin_amdgcn_workgroup_size_z(); + n0 = p->grid_size_x; + n1 = p->grid_size_y; + } else { + s0 = IMPLICITARG(ushort)[6]; + s1 = IMPLICITARG(ushort)[7]; + s2 = IMPLICITARG(ushort)[8]; + n0 = IMPLICITARG(uint)[0]*s0 + IMPLICITARG(ushort)[9]; + n1 = IMPLICITARG(uint)[1]*s1 + IMPLICITARG(ushort)[10]; + } + uint i0 = g0*s0 + l0; + uint i1 = g1*s1 + l1; + uint i2 = g2*s2 + l2; + return ((size_t)i2 * (size_t)n1 + (size_t)i1) * (size_t)n0 + i0; +} + +ATTR static size_t +get_local_linear_id_(void) +{ + return (__builtin_amdgcn_workitem_id_z() * (uint)get_local_size_y() + + __builtin_amdgcn_workitem_id_y()) * (uint)get_local_size_x() + + __builtin_amdgcn_workitem_id_x(); +} + +ATTR size_t +__ockl_get_global_offset(uint dim) +{ + switch(dim) { + case 0: + return get_global_offset_x(); + case 1: + return get_global_offset_y(); + case 2: + return get_global_offset_z(); + default: + return 0; + } +} + +ATTR size_t +__ockl_get_global_id(uint dim) +{ + switch(dim) { + case 0: + return get_global_id_x(); + case 1: + return get_global_id_y(); + case 2: + return get_global_id_z(); + default: + return 0; + } +} + +ATTR size_t +__ockl_get_local_id(uint dim) +{ + switch(dim) { + case 0: + return __builtin_amdgcn_workitem_id_x(); + case 1: + return __builtin_amdgcn_workitem_id_y(); + case 2: + return __builtin_amdgcn_workitem_id_z(); + default: + return 0; + } +} + +ATTR size_t +__ockl_get_group_id(uint dim) +{ + switch(dim) { + case 0: + return __builtin_amdgcn_workgroup_id_x(); + case 1: + return __builtin_amdgcn_workgroup_id_y(); + case 2: + return __builtin_amdgcn_workgroup_id_z(); + default: + return 0; + } +} + +ATTR size_t +__ockl_get_global_size(uint dim) +{ + switch(dim) { + case 0: + return get_global_size_x(); + case 1: + return get_global_size_y(); + case 2: + return get_global_size_z(); + default: + return 1; + } +} + +ATTR size_t +__ockl_get_local_size(uint dim) +{ + switch(dim) { + case 0: + return get_local_size_x(); + case 1: + return get_local_size_y(); + case 2: + return get_local_size_z(); + default: + return 1; + } +} + +ATTR size_t +__ockl_get_num_groups(uint dim) +{ + switch(dim) { + case 0: + return get_num_groups_x(); + case 1: + return get_num_groups_y(); + case 2: + return get_num_groups_z(); + default: + return 1; + } +} + +ATTR uint +__ockl_get_work_dim(void) +{ + return get_work_dim_(); +} + +ATTR size_t +__ockl_get_enqueued_local_size(uint dim) +{ + switch(dim) { + case 0: + return get_enqueued_local_size_x(); + case 1: + return get_enqueued_local_size_y(); + case 2: + return get_enqueued_local_size_z(); + default: + return 1; + } +} + +ATTR size_t +__ockl_get_global_linear_id(void) +{ + switch (get_work_dim_()) { + case 1: + return get_global_linear_id_x(); + case 2: + return get_global_linear_id_y(); + case 3: + return get_global_linear_id_z(); + default: + return 0; + } +} + +ATTR size_t +__ockl_get_local_linear_id(void) +{ + return get_local_linear_id_(); +} + diff --git a/amd/device-libs/oclc/CMakeLists.txt b/amd/device-libs/oclc/CMakeLists.txt new file mode 100644 index 0000000000000..8ffbc071d3f3c --- /dev/null +++ b/amd/device-libs/oclc/CMakeLists.txt @@ -0,0 +1,19 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +file(GLOB sources + ${CMAKE_CURRENT_SOURCE_DIR}/src/*.cl +) + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/inc) + +foreach (file ${sources}) + get_filename_component(dir ${file} DIRECTORY) + get_filename_component(name ${file} NAME_WE) + get_filename_component(ext ${file} EXT) + opencl_bc_lib(NAME oclc_${name} SOURCES ${file}) +endforeach() diff --git a/amd/device-libs/oclc/inc/oclc.h b/amd/device-libs/oclc/inc/oclc.h new file mode 100644 index 0000000000000..dae41738c3fc5 --- /dev/null +++ b/amd/device-libs/oclc/inc/oclc.h @@ -0,0 +1,48 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#ifndef OCLC_H +#define OCLC_H + +// These constants are used to control behavior of the libraries which +// check them. +// +// The current list of controls is as follows: +// +// __constant bool __oclc_finite_only_opt +// - the application will only pass finite arguments and expects only finite results +// +// __constant bool __oclc_unsafe_math_opt +// - the application accepts optimizations that may lower the accuracy of the results +// +// __constant bool __oclc_wavefrontsize64 +// - the application is being compiled for a wavefront size of 64 +// +// __constant int __oclc_ISA_version +// - the ISA version of the target device +// +// __constant int __oclc_ABI_version +// - the ABI version the application is being compiled for +// +// it is expected that the implementation provides these as if declared from the following +// C code: +// +// const bool int __oclc_... = 0; // Or 1 +// +// allowing them and any control flow associated with them to be optimized away + +extern const __constant bool __oclc_finite_only_opt; +extern const __constant bool __oclc_unsafe_math_opt; +extern const __constant bool __oclc_wavefrontsize64; +extern const __constant uint __oclc_wavefrontsize_log2; +extern const __constant int __oclc_ISA_version; +extern const __constant int __oclc_ABI_version; + +#define OCLC_WAVEFRONT_SIZE (1u << __oclc_wavefrontsize_log2) + + +#endif // OCLC_H diff --git a/amd/device-libs/oclc/src/abi_version_400.cl b/amd/device-libs/oclc/src/abi_version_400.cl new file mode 100644 index 0000000000000..3d9f6c3f03b6d --- /dev/null +++ b/amd/device-libs/oclc/src/abi_version_400.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ABI_version = 400; + diff --git a/amd/device-libs/oclc/src/abi_version_500.cl b/amd/device-libs/oclc/src/abi_version_500.cl new file mode 100644 index 0000000000000..0a09ea20810a3 --- /dev/null +++ b/amd/device-libs/oclc/src/abi_version_500.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ABI_version = 500; + diff --git a/amd/device-libs/oclc/src/abi_version_600.cl b/amd/device-libs/oclc/src/abi_version_600.cl new file mode 100644 index 0000000000000..6227c1dcfc354 --- /dev/null +++ b/amd/device-libs/oclc/src/abi_version_600.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ABI_version = 600; diff --git a/amd/device-libs/oclc/src/correctly_rounded_sqrt_off.cl b/amd/device-libs/oclc/src/correctly_rounded_sqrt_off.cl new file mode 100644 index 0000000000000..d5bc07c0c4238 --- /dev/null +++ b/amd/device-libs/oclc/src/correctly_rounded_sqrt_off.cl @@ -0,0 +1 @@ +// Placeholder until clang stops trying to link this diff --git a/amd/device-libs/oclc/src/correctly_rounded_sqrt_on.cl b/amd/device-libs/oclc/src/correctly_rounded_sqrt_on.cl new file mode 100644 index 0000000000000..d5bc07c0c4238 --- /dev/null +++ b/amd/device-libs/oclc/src/correctly_rounded_sqrt_on.cl @@ -0,0 +1 @@ +// Placeholder until clang stops trying to link this diff --git a/amd/device-libs/oclc/src/daz_opt_off.cl b/amd/device-libs/oclc/src/daz_opt_off.cl new file mode 100644 index 0000000000000..91529c697578d --- /dev/null +++ b/amd/device-libs/oclc/src/daz_opt_off.cl @@ -0,0 +1,8 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +// Placeholder until clang stops looking for this library diff --git a/amd/device-libs/oclc/src/daz_opt_on.cl b/amd/device-libs/oclc/src/daz_opt_on.cl new file mode 100644 index 0000000000000..3ac37ed982741 --- /dev/null +++ b/amd/device-libs/oclc/src/daz_opt_on.cl @@ -0,0 +1,9 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +// Placeholder until clang stops looking for this library + diff --git a/amd/device-libs/oclc/src/finite_only_off.cl b/amd/device-libs/oclc/src/finite_only_off.cl new file mode 100644 index 0000000000000..37e296805b7f6 --- /dev/null +++ b/amd/device-libs/oclc/src/finite_only_off.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant bool __oclc_finite_only_opt = 0; + diff --git a/amd/device-libs/oclc/src/finite_only_on.cl b/amd/device-libs/oclc/src/finite_only_on.cl new file mode 100644 index 0000000000000..f0098c1a924f1 --- /dev/null +++ b/amd/device-libs/oclc/src/finite_only_on.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant bool __oclc_finite_only_opt = 1; + diff --git a/amd/device-libs/oclc/src/isa_version_10-1-generic.cl b/amd/device-libs/oclc/src/isa_version_10-1-generic.cl new file mode 100644 index 0000000000000..3c89cdb3f4f4d --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_10-1-generic.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +// gfx10-1-generic is identical to gfx1010. +const __constant int __oclc_ISA_version = 10100; diff --git a/amd/device-libs/oclc/src/isa_version_10-3-generic.cl b/amd/device-libs/oclc/src/isa_version_10-3-generic.cl new file mode 100644 index 0000000000000..2a66d3b03ae08 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_10-3-generic.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +// gfx10-3-generic is identical to gfx1030-36. +const __constant int __oclc_ISA_version = 10300; diff --git a/amd/device-libs/oclc/src/isa_version_1010.cl b/amd/device-libs/oclc/src/isa_version_1010.cl new file mode 100644 index 0000000000000..59ba3e143f480 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1010.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10100; + diff --git a/amd/device-libs/oclc/src/isa_version_1011.cl b/amd/device-libs/oclc/src/isa_version_1011.cl new file mode 100644 index 0000000000000..6556655db49f4 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1011.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10101; + diff --git a/amd/device-libs/oclc/src/isa_version_1012.cl b/amd/device-libs/oclc/src/isa_version_1012.cl new file mode 100644 index 0000000000000..4b001550f569c --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1012.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10102; + diff --git a/amd/device-libs/oclc/src/isa_version_1013.cl b/amd/device-libs/oclc/src/isa_version_1013.cl new file mode 100644 index 0000000000000..7ec0694a95670 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1013.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10103; + diff --git a/amd/device-libs/oclc/src/isa_version_1030.cl b/amd/device-libs/oclc/src/isa_version_1030.cl new file mode 100644 index 0000000000000..117645f6d36ec --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1030.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10300; + diff --git a/amd/device-libs/oclc/src/isa_version_1031.cl b/amd/device-libs/oclc/src/isa_version_1031.cl new file mode 100644 index 0000000000000..4dc1b887c878e --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1031.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10301; + diff --git a/amd/device-libs/oclc/src/isa_version_1032.cl b/amd/device-libs/oclc/src/isa_version_1032.cl new file mode 100644 index 0000000000000..151efd534a996 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1032.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10302; + diff --git a/amd/device-libs/oclc/src/isa_version_1033.cl b/amd/device-libs/oclc/src/isa_version_1033.cl new file mode 100644 index 0000000000000..9a07a2c745f60 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1033.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10303; + diff --git a/amd/device-libs/oclc/src/isa_version_1034.cl b/amd/device-libs/oclc/src/isa_version_1034.cl new file mode 100644 index 0000000000000..ee693ff67ecce --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1034.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10304; + diff --git a/amd/device-libs/oclc/src/isa_version_1035.cl b/amd/device-libs/oclc/src/isa_version_1035.cl new file mode 100644 index 0000000000000..cc96890f47c1f --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1035.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10305; + diff --git a/amd/device-libs/oclc/src/isa_version_1036.cl b/amd/device-libs/oclc/src/isa_version_1036.cl new file mode 100644 index 0000000000000..3559b9a751faa --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1036.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 10306; diff --git a/amd/device-libs/oclc/src/isa_version_11-generic.cl b/amd/device-libs/oclc/src/isa_version_11-generic.cl new file mode 100644 index 0000000000000..075b559c9c12a --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_11-generic.cl @@ -0,0 +1,12 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +// gfx11-generic is identical to gfx1103 from the device-lib perspective. +// NOTE: gfx1103 does not have the HW workarounds that gfx11-generic has. +const __constant int __oclc_ISA_version = 11003; diff --git a/amd/device-libs/oclc/src/isa_version_1100.cl b/amd/device-libs/oclc/src/isa_version_1100.cl new file mode 100644 index 0000000000000..291f110174d6a --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1100.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 11000; + diff --git a/amd/device-libs/oclc/src/isa_version_1101.cl b/amd/device-libs/oclc/src/isa_version_1101.cl new file mode 100644 index 0000000000000..4e5d98f06eb8f --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1101.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 11001; diff --git a/amd/device-libs/oclc/src/isa_version_1102.cl b/amd/device-libs/oclc/src/isa_version_1102.cl new file mode 100644 index 0000000000000..806c9ac378066 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1102.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 11002; diff --git a/amd/device-libs/oclc/src/isa_version_1103.cl b/amd/device-libs/oclc/src/isa_version_1103.cl new file mode 100644 index 0000000000000..4fd148a01f8da --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1103.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 11003; diff --git a/amd/device-libs/oclc/src/isa_version_1150.cl b/amd/device-libs/oclc/src/isa_version_1150.cl new file mode 100644 index 0000000000000..f6506a8b82dde --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1150.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 11500; diff --git a/amd/device-libs/oclc/src/isa_version_1151.cl b/amd/device-libs/oclc/src/isa_version_1151.cl new file mode 100644 index 0000000000000..fe9204252adf4 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1151.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 11501; diff --git a/amd/device-libs/oclc/src/isa_version_1152.cl b/amd/device-libs/oclc/src/isa_version_1152.cl new file mode 100644 index 0000000000000..e3bf439a162e6 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1152.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 11502; diff --git a/amd/device-libs/oclc/src/isa_version_1153.cl b/amd/device-libs/oclc/src/isa_version_1153.cl new file mode 100644 index 0000000000000..713137c8905d2 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1153.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 11503; diff --git a/amd/device-libs/oclc/src/isa_version_12-generic.cl b/amd/device-libs/oclc/src/isa_version_12-generic.cl new file mode 100644 index 0000000000000..d64c294d5fdcc --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_12-generic.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +// gfx12-generic is identical to gfx1200 and gfx1201. +const __constant int __oclc_ISA_version = 12000; diff --git a/amd/device-libs/oclc/src/isa_version_1200.cl b/amd/device-libs/oclc/src/isa_version_1200.cl new file mode 100644 index 0000000000000..351c0f14fc819 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1200.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 12000; diff --git a/amd/device-libs/oclc/src/isa_version_1201.cl b/amd/device-libs/oclc/src/isa_version_1201.cl new file mode 100644 index 0000000000000..db984fddebdc8 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_1201.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 12001; diff --git a/amd/device-libs/oclc/src/isa_version_600.cl b/amd/device-libs/oclc/src/isa_version_600.cl new file mode 100644 index 0000000000000..f22f1aa6a6ce9 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_600.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 6000; + diff --git a/amd/device-libs/oclc/src/isa_version_601.cl b/amd/device-libs/oclc/src/isa_version_601.cl new file mode 100644 index 0000000000000..6e3f623342f28 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_601.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 6001; + diff --git a/amd/device-libs/oclc/src/isa_version_602.cl b/amd/device-libs/oclc/src/isa_version_602.cl new file mode 100644 index 0000000000000..c65747755a01b --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_602.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 6002; + diff --git a/amd/device-libs/oclc/src/isa_version_700.cl b/amd/device-libs/oclc/src/isa_version_700.cl new file mode 100644 index 0000000000000..e4767ec6c16a3 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_700.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 7000; + diff --git a/amd/device-libs/oclc/src/isa_version_701.cl b/amd/device-libs/oclc/src/isa_version_701.cl new file mode 100644 index 0000000000000..4375ddefc6a72 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_701.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 7001; + diff --git a/amd/device-libs/oclc/src/isa_version_702.cl b/amd/device-libs/oclc/src/isa_version_702.cl new file mode 100644 index 0000000000000..bd110f198b56e --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_702.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 7002; + diff --git a/amd/device-libs/oclc/src/isa_version_703.cl b/amd/device-libs/oclc/src/isa_version_703.cl new file mode 100644 index 0000000000000..a4b4d781f8706 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_703.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 7003; + diff --git a/amd/device-libs/oclc/src/isa_version_704.cl b/amd/device-libs/oclc/src/isa_version_704.cl new file mode 100644 index 0000000000000..fd437e6136e1d --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_704.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 7004; + diff --git a/amd/device-libs/oclc/src/isa_version_705.cl b/amd/device-libs/oclc/src/isa_version_705.cl new file mode 100644 index 0000000000000..78b9ef7c506a8 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_705.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 7005; + diff --git a/amd/device-libs/oclc/src/isa_version_801.cl b/amd/device-libs/oclc/src/isa_version_801.cl new file mode 100644 index 0000000000000..9d416bffcec09 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_801.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 8001; + diff --git a/amd/device-libs/oclc/src/isa_version_802.cl b/amd/device-libs/oclc/src/isa_version_802.cl new file mode 100644 index 0000000000000..45ed5cb2968cb --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_802.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 8002; + diff --git a/amd/device-libs/oclc/src/isa_version_803.cl b/amd/device-libs/oclc/src/isa_version_803.cl new file mode 100644 index 0000000000000..b62ec0ffaebd9 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_803.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 8003; + diff --git a/amd/device-libs/oclc/src/isa_version_805.cl b/amd/device-libs/oclc/src/isa_version_805.cl new file mode 100644 index 0000000000000..18e8084d705f6 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_805.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 8005; + diff --git a/amd/device-libs/oclc/src/isa_version_810.cl b/amd/device-libs/oclc/src/isa_version_810.cl new file mode 100644 index 0000000000000..ae086b5739232 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_810.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 8100; + diff --git a/amd/device-libs/oclc/src/isa_version_9-4-generic.cl b/amd/device-libs/oclc/src/isa_version_9-4-generic.cl new file mode 100644 index 0000000000000..ba8f51c4c58a1 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_9-4-generic.cl @@ -0,0 +1,13 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +// gfx9-4-generic matches gfx942 from the device-lib perspective. +// NOTE: gfx942 has fp8 instructions, fp8 conversion instructions, and support +// for xf32 format, while the gfx9-4-generic doesn't. +const __constant int __oclc_ISA_version = 9402; diff --git a/amd/device-libs/oclc/src/isa_version_9-generic.cl b/amd/device-libs/oclc/src/isa_version_9-generic.cl new file mode 100644 index 0000000000000..39705203653fe --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_9-generic.cl @@ -0,0 +1,12 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +// gfx9-generic matches gfx900 from the device-lib perspective. +// NOTE: gfx900 has mad-mix while gfx9-generic does NOT. +const __constant int __oclc_ISA_version = 9000; diff --git a/amd/device-libs/oclc/src/isa_version_900.cl b/amd/device-libs/oclc/src/isa_version_900.cl new file mode 100644 index 0000000000000..4fc2d78d53046 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_900.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 9000; + diff --git a/amd/device-libs/oclc/src/isa_version_902.cl b/amd/device-libs/oclc/src/isa_version_902.cl new file mode 100644 index 0000000000000..c39e9b035380f --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_902.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 9002; + diff --git a/amd/device-libs/oclc/src/isa_version_904.cl b/amd/device-libs/oclc/src/isa_version_904.cl new file mode 100644 index 0000000000000..4327d65c228a8 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_904.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 9004; + diff --git a/amd/device-libs/oclc/src/isa_version_906.cl b/amd/device-libs/oclc/src/isa_version_906.cl new file mode 100644 index 0000000000000..07b81e912b37b --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_906.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 9006; + diff --git a/amd/device-libs/oclc/src/isa_version_908.cl b/amd/device-libs/oclc/src/isa_version_908.cl new file mode 100644 index 0000000000000..29779948d30c7 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_908.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 9008; diff --git a/amd/device-libs/oclc/src/isa_version_909.cl b/amd/device-libs/oclc/src/isa_version_909.cl new file mode 100644 index 0000000000000..4503d37e139fd --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_909.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 9009; diff --git a/amd/device-libs/oclc/src/isa_version_90a.cl b/amd/device-libs/oclc/src/isa_version_90a.cl new file mode 100644 index 0000000000000..142ce1e690ad2 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_90a.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 9010; diff --git a/amd/device-libs/oclc/src/isa_version_90c.cl b/amd/device-libs/oclc/src/isa_version_90c.cl new file mode 100644 index 0000000000000..935753ab620e0 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_90c.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 9012; diff --git a/amd/device-libs/oclc/src/isa_version_942.cl b/amd/device-libs/oclc/src/isa_version_942.cl new file mode 100644 index 0000000000000..4d9f1d119821e --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_942.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 9402; diff --git a/amd/device-libs/oclc/src/isa_version_950.cl b/amd/device-libs/oclc/src/isa_version_950.cl new file mode 100644 index 0000000000000..672ec4bc67548 --- /dev/null +++ b/amd/device-libs/oclc/src/isa_version_950.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant int __oclc_ISA_version = 9500; diff --git a/amd/device-libs/oclc/src/unsafe_math_off.cl b/amd/device-libs/oclc/src/unsafe_math_off.cl new file mode 100644 index 0000000000000..55a82942cb471 --- /dev/null +++ b/amd/device-libs/oclc/src/unsafe_math_off.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant bool __oclc_unsafe_math_opt = 0; + diff --git a/amd/device-libs/oclc/src/unsafe_math_on.cl b/amd/device-libs/oclc/src/unsafe_math_on.cl new file mode 100644 index 0000000000000..33a63325d0607 --- /dev/null +++ b/amd/device-libs/oclc/src/unsafe_math_on.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant bool __oclc_unsafe_math_opt = 1; + diff --git a/amd/device-libs/oclc/src/wavefrontsize64_off.cl b/amd/device-libs/oclc/src/wavefrontsize64_off.cl new file mode 100644 index 0000000000000..4efa215023540 --- /dev/null +++ b/amd/device-libs/oclc/src/wavefrontsize64_off.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant bool __oclc_wavefrontsize64 = 0; +const __constant uint __oclc_wavefrontsize_log2 = 5; diff --git a/amd/device-libs/oclc/src/wavefrontsize64_on.cl b/amd/device-libs/oclc/src/wavefrontsize64_on.cl new file mode 100644 index 0000000000000..ccb248094f5fa --- /dev/null +++ b/amd/device-libs/oclc/src/wavefrontsize64_on.cl @@ -0,0 +1,11 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +const __constant bool __oclc_wavefrontsize64 = 1; +const __constant uint __oclc_wavefrontsize_log2 = 6; diff --git a/amd/device-libs/ocml/CMakeLists.txt b/amd/device-libs/ocml/CMakeLists.txt new file mode 100644 index 0000000000000..7957d694319eb --- /dev/null +++ b/amd/device-libs/ocml/CMakeLists.txt @@ -0,0 +1,31 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +file(GLOB sources + ${CMAKE_CURRENT_SOURCE_DIR}/src/*.cl + ) + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../irif/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../oclc/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/src) + +set(native_func_flags -fapprox-func) + +set_source_files_properties( + ${CMAKE_CURRENT_SOURCE_DIR}/src/native_logF.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/native_expF.cl + PROPERTIES COMPILE_FLAGS "${native_func_flags}") + + +# This implementation of sqrt will not be used through opencl, openmp, +# or hip. Compile to be correctly rounded just in case +set_source_files_properties( + ${CMAKE_CURRENT_SOURCE_DIR}/src/sqrtF.cl + PROPERTIES COMPILE_FLAGS -cl-fp32-correctly-rounded-divide-sqrt) + +opencl_bc_lib(NAME ocml SOURCES ${sources}) diff --git a/amd/device-libs/ocml/inc/ocml.h b/amd/device-libs/ocml/inc/ocml.h new file mode 100644 index 0000000000000..ce0ad8e358054 --- /dev/null +++ b/amd/device-libs/ocml/inc/ocml.h @@ -0,0 +1,804 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#ifndef OCML_H +#define OCML_H + +// This C header declares the functions provided by the OCML library +// Aspects of this library's behavior can be controlled via the +// oclc library. See the oclc header for further information + +// Define here the return values from fpclassify +// These match most host definitions +#define FP_NAN 0 +#define FP_INFINITE 1 +#define FP_ZERO 2 +#define FP_SUBNORMAL 3 +#define FP_NORMAL 4 + +#define OCML_DEPRECATED(X, Replacement) __attribute__((deprecated("use "#Replacement " instead", Replacement))) + +#define _MANGLE3(P,N,S) P##_##N##_##S +#define MANGLE3(P,N,S) _MANGLE3(P,N,S) +#define OCML_MANGLE_F32(N) MANGLE3(__ocml, N, f32) +#define OCML_MANGLE_2F32(N) MANGLE3(__ocml, N, 2f32) +#define OCML_MANGLE_F64(N) MANGLE3(__ocml, N, f64) +#define OCML_MANGLE_F16(N) MANGLE3(__ocml, N, f16) +#define OCML_MANGLE_2F16(N) MANGLE3(__ocml, N, 2f16) +#define OCML_MANGLE_S32(N) MANGLE3(__ocml, N, s32) +#define OCML_MANGLE_U32(N) MANGLE3(__ocml, N, u32) +#define OCML_MANGLE_S64(N) MANGLE3(__ocml, N, s64) +#define OCML_MANGLE_U64(N) MANGLE3(__ocml, N, u64) + + +#define DECL_OCML_UNARY_F32(N) extern float OCML_MANGLE_F32(N)(float); +#define _DECL_X_OCML_UNARY_F32(A,N) extern __attribute__((A)) float OCML_MANGLE_F32(N)(float); +#define DECL_PURE_OCML_UNARY_F32(N) _DECL_X_OCML_UNARY_F32(pure, N) +#define DECL_CONST_OCML_UNARY_F32(N) _DECL_X_OCML_UNARY_F32(const, N) + +#define DECL_CONST_OCML_UNARYPRED_F32(N) extern __attribute__((const)) int OCML_MANGLE_F32(N)(float); + +#define DECL_OCML_BINARY_F32(N) extern float OCML_MANGLE_F32(N)(float, float); +#define _DECL_X_OCML_BINARY_F32(A,N) extern __attribute__((A)) float OCML_MANGLE_F32(N)(float, float); +#define DECL_PURE_OCML_BINARY_F32(N) _DECL_X_OCML_BINARY_F32(pure, N) +#define DECL_CONST_OCML_BINARY_F32(N) _DECL_X_OCML_BINARY_F32(const, N) + +#define DECL_CONST_OCML_BINARYPRED_F32(N) extern __attribute__((const)) int OCML_MANGLE_F32(N)(float, float); + +#define _DECL_X_OCML_TERNARY_F32(A,N) extern __attribute__((A)) float OCML_MANGLE_F32(N)(float, float, float); +#define DECL_PURE_OCML_TERNARY_F32(N) _DECL_X_OCML_TERNARY_F32(pure, N) +#define DECL_CONST_OCML_TERNARY_F32(N) _DECL_X_OCML_TERNARY_F32(const, N) + +#define _DECL_X_OCML_TERNARY_2F32(A,N) extern __attribute__((A)) float2 OCML_MANGLE_2F32(N)(float2, float2, float2); +#define DECL_PURE_OCML_TERNARY_2F32(N) _DECL_X_OCML_TERNARY_2F32(pure, N) +#define DECL_CONST_OCML_TERNARY_2F32(N) _DECL_X_OCML_TERNARY_2F32(const, N) + +#define DECL_OCML_UNARY_F64(N) extern double OCML_MANGLE_F64(N)(double); +#define _DECL_X_OCML_UNARY_F64(A,N) extern __attribute__((A)) double OCML_MANGLE_F64(N)(double); +#define DECL_PURE_OCML_UNARY_F64(N) _DECL_X_OCML_UNARY_F64(pure, N) +#define DECL_CONST_OCML_UNARY_F64(N) _DECL_X_OCML_UNARY_F64(const, N) + +#define DECL_CONST_OCML_UNARYPRED_F64(N) extern __attribute__((const)) int OCML_MANGLE_F64(N)(double); + +#define DECL_OCML_BINARY_F64(N) extern double OCML_MANGLE_F64(N)(double, double); +#define _DECL_X_OCML_BINARY_F64(A,N) extern __attribute__((A)) double OCML_MANGLE_F64(N)(double, double); +#define DECL_PURE_OCML_BINARY_F64(N) _DECL_X_OCML_BINARY_F64(pure, N) +#define DECL_CONST_OCML_BINARY_F64(N) _DECL_X_OCML_BINARY_F64(const, N) + +#define DECL_CONST_OCML_BINARYPRED_F64(N) extern __attribute__((const)) int OCML_MANGLE_F64(N)(double, double); + +#define _DECL_X_OCML_TERNARY_F64(A,N) extern __attribute__((A)) double OCML_MANGLE_F64(N)(double, double, double); +#define DECL_PURE_OCML_TERNARY_F64(N) _DECL_X_OCML_TERNARY_F64(pure, N) +#define DECL_CONST_OCML_TERNARY_F64(N) _DECL_X_OCML_TERNARY_F64(const, N) + +#define DECL_OCML_UNARY_F16(N) extern half OCML_MANGLE_F16(N)(half); +#define _DECL_X_OCML_UNARY_F16(A,N) extern __attribute__((A)) half OCML_MANGLE_F16(N)(half); +#define DECL_PURE_OCML_UNARY_F16(N) _DECL_X_OCML_UNARY_F16(pure, N) +#define DECL_CONST_OCML_UNARY_F16(N) _DECL_X_OCML_UNARY_F16(const, N) + +#define DECL_CONST_OCML_UNARYPRED_F16(N) extern __attribute__((const)) int OCML_MANGLE_F16(N)(half); + +#define DECL_OCML_BINARY_F16(N) extern half OCML_MANGLE_F16(N)(half, half); +#define _DECL_X_OCML_BINARY_F16(A,N) extern __attribute__((A)) half OCML_MANGLE_F16(N)(half, half); +#define DECL_PURE_OCML_BINARY_F16(N) _DECL_X_OCML_BINARY_F16(pure, N) +#define DECL_CONST_OCML_BINARY_F16(N) _DECL_X_OCML_BINARY_F16(const, N) + +#define DECL_CONST_OCML_BINARYPRED_F16(N) extern __attribute__((const)) int OCML_MANGLE_F16(N)(half, half); + +#define _DECL_X_OCML_TERNARY_F16(A,N) extern __attribute__((A)) half OCML_MANGLE_F16(N)(half, half, half); +#define DECL_PURE_OCML_TERNARY_F16(N) _DECL_X_OCML_TERNARY_F16(pure, N) +#define DECL_CONST_OCML_TERNARY_F16(N) _DECL_X_OCML_TERNARY_F16(const, N) + +#define DECL_OCML_UNARY_2F16(N) extern half2 OCML_MANGLE_2F16(N)(half2); +#define _DECL_X_OCML_UNARY_2F16(A,N) extern __attribute__((A)) half2 OCML_MANGLE_2F16(N)(half2); +#define DECL_PURE_OCML_UNARY_2F16(N) _DECL_X_OCML_UNARY_2F16(pure, N) +#define DECL_CONST_OCML_UNARY_2F16(N) _DECL_X_OCML_UNARY_2F16(const, N) + +#define DECL_CONST_OCML_UNARYPRED_2F16(N) extern __attribute__((const)) short2 OCML_MANGLE_2F16(N)(half2); + +#define DECL_OCML_BINARY_2F16(N) extern half2 OCML_MANGLE_2F16(N)(half2, half2); +#define _DECL_X_OCML_BINARY_2F16(A,N) extern __attribute__((A)) half2 OCML_MANGLE_2F16(N)(half2, half2); +#define DECL_PURE_OCML_BINARY_2F16(N) _DECL_X_OCML_BINARY_2F16(pure, N) +#define DECL_CONST_OCML_BINARY_2F16(N) _DECL_X_OCML_BINARY_2F16(const, N) + +#define DECL_CONST_OCML_BINARYPRED_2F16(N) extern __attribute__((const)) short2 OCML_MANGLE_2F16(N)(half2, half2); + +#define _DECL_X_OCML_TERNARY_2F16(A,N) extern __attribute__((A)) half2 OCML_MANGLE_2F16(N)(half2, half2, half2); +#define DECL_PURE_OCML_TERNARY_2F16(N) _DECL_X_OCML_TERNARY_2F16(pure, N) +#define DECL_CONST_OCML_TERNARY_2F16(N) _DECL_X_OCML_TERNARY_2F16(const, N) + +DECL_CONST_OCML_UNARY_F32(acos) +DECL_CONST_OCML_UNARY_F32(acospi) +DECL_CONST_OCML_UNARY_F32(acosh) +DECL_CONST_OCML_UNARY_F32(asin) +DECL_CONST_OCML_UNARY_F32(asinpi) +DECL_CONST_OCML_UNARY_F32(asinh) +DECL_CONST_OCML_BINARY_F32(atan2) +DECL_CONST_OCML_BINARY_F32(atan2pi) +DECL_CONST_OCML_UNARY_F32(atan) +DECL_CONST_OCML_UNARY_F32(atanh) +DECL_CONST_OCML_UNARY_F32(atanpi) +DECL_CONST_OCML_UNARY_F32(cbrt) +DECL_CONST_OCML_UNARY_F32(ceil) +DECL_OCML_UNARY_F32(cos) +DECL_CONST_OCML_UNARY_F32(cosh) +DECL_OCML_UNARY_F32(cospi) +DECL_CONST_OCML_BINARY_F32(copysign) +DECL_CONST_OCML_UNARY_F32(erf) +DECL_CONST_OCML_UNARY_F32(erfc) +DECL_CONST_OCML_UNARY_F32(erfinv) +DECL_CONST_OCML_UNARY_F32(erfcinv) +DECL_CONST_OCML_UNARY_F32(erfcx) +DECL_CONST_OCML_UNARY_F32(exp) +DECL_CONST_OCML_UNARY_F32(exp2) +DECL_CONST_OCML_UNARY_F32(exp10) +DECL_CONST_OCML_UNARY_F32(expm1) +DECL_CONST_OCML_UNARY_F32(fabs) +DECL_CONST_OCML_BINARY_F32(fdim) +DECL_CONST_OCML_UNARY_F32(floor) +DECL_CONST_OCML_TERNARY_F32(fma) +DECL_CONST_OCML_TERNARY_2F32(fma) +DECL_CONST_OCML_TERNARY_F32(fmuladd) +DECL_CONST_OCML_TERNARY_2F32(fmuladd) +DECL_CONST_OCML_BINARY_F32(fmax) +DECL_CONST_OCML_BINARY_F32(fmin) +DECL_CONST_OCML_BINARY_F32(fmod) +DECL_CONST_OCML_UNARYPRED_F32(fpclassify) +extern float OCML_MANGLE_F32(fract)(float, __private float *); +extern float OCML_MANGLE_F32(frexp)(float, __private int *); +DECL_CONST_OCML_BINARY_F32(hypot) +DECL_CONST_OCML_UNARYPRED_F32(ilogb) +DECL_CONST_OCML_UNARYPRED_F32(isfinite) +DECL_CONST_OCML_UNARYPRED_F32(isinf) +DECL_CONST_OCML_UNARYPRED_F32(isnan) +DECL_CONST_OCML_UNARYPRED_F32(isnormal) +DECL_CONST_OCML_UNARY_F32(i0) +DECL_CONST_OCML_UNARY_F32(i1) +DECL_CONST_OCML_UNARY_F32(j0) +DECL_CONST_OCML_UNARY_F32(j1) +extern __attribute__((const)) float OCML_MANGLE_F32(ldexp)(float, int); +DECL_CONST_OCML_TERNARY_F32(len3) +extern __attribute__((const)) float OCML_MANGLE_F32(len4)(float, float, float, float); +DECL_CONST_OCML_UNARY_F32(lgamma) +extern float OCML_MANGLE_F32(lgamma_r)(float, __private int *); +DECL_CONST_OCML_UNARY_F32(log) +DECL_CONST_OCML_UNARY_F32(log2) +DECL_CONST_OCML_UNARY_F32(log10) +DECL_CONST_OCML_UNARY_F32(log1p) +DECL_CONST_OCML_UNARY_F32(logb) +DECL_CONST_OCML_TERNARY_F32(mad) +DECL_CONST_OCML_TERNARY_2F32(mad) +DECL_CONST_OCML_BINARY_F32(max) +DECL_CONST_OCML_BINARY_F32(min) +DECL_CONST_OCML_BINARY_F32(maxmag) +DECL_CONST_OCML_BINARY_F32(minmag) +extern float OCML_MANGLE_F32(modf)(float, __private float *); +extern __attribute__((const)) float OCML_MANGLE_F32(nan)(uint); +DECL_CONST_OCML_UNARY_F32(ncdf) +DECL_CONST_OCML_UNARY_F32(ncdfinv) +DECL_CONST_OCML_UNARY_F32(nearbyint) +DECL_CONST_OCML_BINARY_F32(nextafter) +DECL_CONST_OCML_BINARY_F32(pow) +DECL_CONST_OCML_BINARY_F32(powr) +extern __attribute__((pure)) float OCML_MANGLE_F32(pown)(float, int); +extern __attribute__((pure)) float OCML_MANGLE_F32(rootn)(float, int); +DECL_CONST_OCML_UNARY_F32(pred) +DECL_CONST_OCML_BINARY_F32(remainder) + +typedef struct __ocml_remquo_f32_result { + float rem; + int quo; +} __ocml_remquo_f32_result; + +extern __ocml_remquo_f32_result OCML_MANGLE_F32(remquo2)(float, float); + +OCML_DEPRECATED(OCML_MANGLE_F32(remquo), "__ocml_remquo2_f32") +extern float OCML_MANGLE_F32(remquo)(float, float, __private int *); +DECL_CONST_OCML_BINARY_F32(rhypot) +DECL_CONST_OCML_UNARY_F32(rint) +DECL_CONST_OCML_TERNARY_F32(rlen3) +extern __attribute__((const)) float OCML_MANGLE_F32(rlen4)(float, float, float, float); +DECL_CONST_OCML_UNARY_F32(round) +DECL_CONST_OCML_UNARY_F32(rcbrt) +DECL_CONST_OCML_UNARY_F32(rsqrt) +DECL_CONST_OCML_BINARY_F32(scalb) +extern __attribute__((const)) float OCML_MANGLE_F32(scalbn)(float, int); +DECL_CONST_OCML_UNARYPRED_F32(signbit) +DECL_CONST_OCML_UNARY_F32(sin) +DECL_CONST_OCML_UNARY_F32(sinh) +DECL_CONST_OCML_UNARY_F32(sinpi) +extern float OCML_MANGLE_F32(sincos)(float, __private float *); +extern float OCML_MANGLE_F32(sincospi)(float, __private float *); +DECL_CONST_OCML_UNARY_F32(sqrt) +DECL_CONST_OCML_UNARY_F32(succ) +DECL_OCML_UNARY_F32(tan) +DECL_CONST_OCML_UNARY_F32(tanpi) +DECL_CONST_OCML_UNARY_F32(tanh) +DECL_CONST_OCML_UNARY_F32(tgamma) +DECL_CONST_OCML_UNARY_F32(trunc) +DECL_CONST_OCML_UNARY_F32(y0) +DECL_CONST_OCML_UNARY_F32(y1) + +DECL_CONST_OCML_BINARY_F32(add_rte) +DECL_CONST_OCML_BINARY_F32(add_rtp) +DECL_CONST_OCML_BINARY_F32(add_rtn) +DECL_CONST_OCML_BINARY_F32(add_rtz) + +DECL_CONST_OCML_BINARY_F32(div_rte) +DECL_CONST_OCML_BINARY_F32(div_rtp) +DECL_CONST_OCML_BINARY_F32(div_rtn) +DECL_CONST_OCML_BINARY_F32(div_rtz) + +DECL_CONST_OCML_TERNARY_F32(fma_rte) +DECL_CONST_OCML_TERNARY_F32(fma_rtp) +DECL_CONST_OCML_TERNARY_F32(fma_rtn) +DECL_CONST_OCML_TERNARY_F32(fma_rtz) + +DECL_CONST_OCML_BINARY_F32(mul_rte) +DECL_CONST_OCML_BINARY_F32(mul_rtp) +DECL_CONST_OCML_BINARY_F32(mul_rtn) +DECL_CONST_OCML_BINARY_F32(mul_rtz) + +DECL_CONST_OCML_UNARY_F32(sqrt_rte) +DECL_CONST_OCML_UNARY_F32(sqrt_rtp) +DECL_CONST_OCML_UNARY_F32(sqrt_rtn) +DECL_CONST_OCML_UNARY_F32(sqrt_rtz) + +DECL_CONST_OCML_BINARY_F32(sub_rte) +DECL_CONST_OCML_BINARY_F32(sub_rtp) +DECL_CONST_OCML_BINARY_F32(sub_rtn) +DECL_CONST_OCML_BINARY_F32(sub_rtz) + + +DECL_CONST_OCML_UNARY_F64(acos) +DECL_CONST_OCML_UNARY_F64(acosh) +DECL_CONST_OCML_UNARY_F64(acospi) +DECL_CONST_OCML_UNARY_F64(asin) +DECL_CONST_OCML_UNARY_F64(asinh) +DECL_CONST_OCML_UNARY_F64(asinpi) +DECL_CONST_OCML_UNARY_F64(atan) +DECL_CONST_OCML_UNARY_F64(atanh) +DECL_CONST_OCML_UNARY_F64(atanpi) +DECL_CONST_OCML_BINARY_F64(atan2) +DECL_CONST_OCML_BINARY_F64(atan2pi) +DECL_CONST_OCML_UNARY_F64(cbrt) +DECL_CONST_OCML_UNARY_F64(ceil) +DECL_CONST_OCML_BINARY_F64(copysign) +DECL_CONST_OCML_UNARY_F64(cos) +DECL_CONST_OCML_UNARY_F64(cosh) +DECL_CONST_OCML_UNARY_F64(cospi) +DECL_CONST_OCML_UNARY_F64(erf) +DECL_CONST_OCML_UNARY_F64(erfc) +DECL_CONST_OCML_UNARY_F64(erfinv) +DECL_CONST_OCML_UNARY_F64(erfcinv) +DECL_CONST_OCML_UNARY_F64(erfcx) +DECL_CONST_OCML_UNARY_F64(exp) +DECL_CONST_OCML_UNARY_F64(exp2) +DECL_CONST_OCML_UNARY_F64(exp10) +DECL_CONST_OCML_UNARY_F64(expm1) +DECL_CONST_OCML_UNARY_F64(fabs) +DECL_CONST_OCML_BINARY_F64(fdim) +DECL_CONST_OCML_UNARY_F64(floor) +DECL_CONST_OCML_TERNARY_F64(fma) +DECL_CONST_OCML_TERNARY_F64(fmuladd) +DECL_CONST_OCML_BINARY_F64(fmax) +DECL_CONST_OCML_BINARY_F64(fmin) +DECL_CONST_OCML_BINARY_F64(fmod) +DECL_CONST_OCML_UNARYPRED_F64(fpclassify) +extern double OCML_MANGLE_F64(fract)(double, __private double *); +extern double OCML_MANGLE_F64(frexp)(double, __private int *); +DECL_CONST_OCML_BINARY_F64(hypot) +DECL_CONST_OCML_UNARYPRED_F64(ilogb) +DECL_CONST_OCML_UNARYPRED_F64(isfinite) +DECL_CONST_OCML_UNARYPRED_F64(isinf) +DECL_CONST_OCML_UNARYPRED_F64(isnan) +DECL_CONST_OCML_UNARYPRED_F64(isnormal) +DECL_CONST_OCML_UNARY_F64(i0) +DECL_CONST_OCML_UNARY_F64(i1) +DECL_CONST_OCML_UNARY_F64(j0) +DECL_CONST_OCML_UNARY_F64(j1) +extern __attribute__((const)) double OCML_MANGLE_F64(ldexp)(double, int); +DECL_CONST_OCML_TERNARY_F64(len3) +extern __attribute__((const)) double OCML_MANGLE_F64(len4)(double, double, double, double); +DECL_CONST_OCML_UNARY_F64(lgamma) +extern double OCML_MANGLE_F64(lgamma_r)(double, __private int *); +DECL_CONST_OCML_UNARY_F64(log) +DECL_CONST_OCML_UNARY_F64(log2) +DECL_CONST_OCML_UNARY_F64(log10) +DECL_CONST_OCML_UNARY_F64(log1p) +DECL_CONST_OCML_UNARY_F64(logb) +DECL_CONST_OCML_TERNARY_F64(mad) +DECL_CONST_OCML_BINARY_F64(max) +DECL_CONST_OCML_BINARY_F64(min) +DECL_CONST_OCML_BINARY_F64(maxmag) +DECL_CONST_OCML_BINARY_F64(minmag) +extern double OCML_MANGLE_F64(modf)(double, __private double *); +extern __attribute__((const)) double OCML_MANGLE_F64(nan)(ulong); +DECL_CONST_OCML_UNARY_F64(ncdf) +DECL_CONST_OCML_UNARY_F64(ncdfinv) +DECL_CONST_OCML_UNARY_F64(nearbyint) +DECL_CONST_OCML_BINARY_F64(nextafter) +DECL_CONST_OCML_BINARY_F64(pow) +DECL_CONST_OCML_BINARY_F64(powr) +extern __attribute__((pure)) double OCML_MANGLE_F64(pown)(double, int); +extern __attribute__((pure)) double OCML_MANGLE_F64(rootn)(double, int); +DECL_CONST_OCML_UNARY_F64(pred) +DECL_CONST_OCML_BINARY_F64(remainder) + + +typedef struct __ocml_remquo_f64_result { + double rem; + int quo; +} __ocml_remquo_f64_result; + +extern __ocml_remquo_f64_result OCML_MANGLE_F64(remquo2)(double, double); + +OCML_DEPRECATED(OCML_MANGLE_F64(remquo), "__ocml_remquo2_f64") +extern double OCML_MANGLE_F64(remquo)(double, double, __private int *); +DECL_CONST_OCML_BINARY_F64(rhypot) +DECL_CONST_OCML_UNARY_F64(rint) +DECL_CONST_OCML_TERNARY_F64(rlen3) +extern __attribute__((const)) double OCML_MANGLE_F64(rlen4)(double, double, double, double); +DECL_CONST_OCML_UNARY_F64(round) +DECL_CONST_OCML_UNARY_F64(rcbrt) +DECL_CONST_OCML_UNARY_F64(rsqrt) +DECL_CONST_OCML_BINARY_F64(scalb) +extern __attribute__((const)) double OCML_MANGLE_F64(scalbn)(double, int); +DECL_CONST_OCML_UNARYPRED_F64(signbit) +DECL_CONST_OCML_UNARY_F64(sin) +extern double OCML_MANGLE_F64(sincos)(double, __private double *); +extern double OCML_MANGLE_F64(sincospi)(double, __private double *); +DECL_CONST_OCML_UNARY_F64(sinh) +DECL_CONST_OCML_UNARY_F64(sinpi) +DECL_CONST_OCML_UNARY_F64(sqrt) +DECL_CONST_OCML_UNARY_F64(succ) +DECL_CONST_OCML_UNARY_F64(tan) +DECL_CONST_OCML_UNARY_F64(tanh) +DECL_CONST_OCML_UNARY_F64(tanpi) +DECL_CONST_OCML_UNARY_F64(tgamma) +DECL_CONST_OCML_UNARY_F64(trunc) +DECL_CONST_OCML_UNARY_F64(y0) +DECL_CONST_OCML_UNARY_F64(y1) + +DECL_CONST_OCML_BINARY_F64(add_rte) +DECL_CONST_OCML_BINARY_F64(add_rtp) +DECL_CONST_OCML_BINARY_F64(add_rtn) +DECL_CONST_OCML_BINARY_F64(add_rtz) + +DECL_CONST_OCML_BINARY_F64(div_rte) +DECL_CONST_OCML_BINARY_F64(div_rtp) +DECL_CONST_OCML_BINARY_F64(div_rtn) +DECL_CONST_OCML_BINARY_F64(div_rtz) + +DECL_CONST_OCML_TERNARY_F64(fma_rte) +DECL_CONST_OCML_TERNARY_F64(fma_rtp) +DECL_CONST_OCML_TERNARY_F64(fma_rtn) +DECL_CONST_OCML_TERNARY_F64(fma_rtz) + +DECL_CONST_OCML_BINARY_F64(mul_rte) +DECL_CONST_OCML_BINARY_F64(mul_rtp) +DECL_CONST_OCML_BINARY_F64(mul_rtn) +DECL_CONST_OCML_BINARY_F64(mul_rtz) + +DECL_CONST_OCML_UNARY_F64(sqrt_rte) +DECL_CONST_OCML_UNARY_F64(sqrt_rtp) +DECL_CONST_OCML_UNARY_F64(sqrt_rtn) +DECL_CONST_OCML_UNARY_F64(sqrt_rtz) + +DECL_CONST_OCML_BINARY_F64(sub_rte) +DECL_CONST_OCML_BINARY_F64(sub_rtp) +DECL_CONST_OCML_BINARY_F64(sub_rtn) +DECL_CONST_OCML_BINARY_F64(sub_rtz) + + +DECL_CONST_OCML_UNARY_F32(native_recip) +DECL_CONST_OCML_UNARY_F64(native_recip) + +DECL_CONST_OCML_UNARY_F32(native_sqrt) +DECL_CONST_OCML_UNARY_F64(native_sqrt) + +DECL_CONST_OCML_UNARY_F32(native_rsqrt) +DECL_CONST_OCML_UNARY_F64(native_rsqrt) + +DECL_CONST_OCML_UNARY_F32(native_sin) + +DECL_CONST_OCML_UNARY_F32(native_cos) + +DECL_CONST_OCML_UNARY_F32(native_exp) + +DECL_CONST_OCML_UNARY_F32(native_exp2) + +DECL_CONST_OCML_UNARY_F32(native_exp10) + +DECL_CONST_OCML_UNARY_F32(native_log) + +DECL_CONST_OCML_UNARY_F32(native_log2) + +DECL_CONST_OCML_UNARY_F32(native_log10) + + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +DECL_CONST_OCML_UNARY_F16(acos) +DECL_CONST_OCML_UNARY_F16(acosh) +DECL_CONST_OCML_UNARY_F16(acospi) +DECL_CONST_OCML_UNARY_F16(asin) +DECL_CONST_OCML_UNARY_F16(asinh) +DECL_CONST_OCML_UNARY_F16(asinpi) +DECL_CONST_OCML_UNARY_F16(atan) +DECL_CONST_OCML_UNARY_F16(atanh) +DECL_CONST_OCML_UNARY_F16(atanpi) +DECL_CONST_OCML_BINARY_F16(atan2) +DECL_CONST_OCML_BINARY_F16(atan2pi) +DECL_CONST_OCML_UNARY_F16(cbrt) +DECL_CONST_OCML_UNARY_F16(ceil) +DECL_CONST_OCML_BINARY_F16(copysign) +DECL_CONST_OCML_UNARY_F16(cos) +DECL_CONST_OCML_UNARY_F16(cosh) +DECL_CONST_OCML_UNARY_F16(cospi) +DECL_CONST_OCML_UNARY_F16(erf) +DECL_CONST_OCML_UNARY_F16(erfc) +DECL_CONST_OCML_UNARY_F16(erfinv) +DECL_CONST_OCML_UNARY_F16(erfcinv) +DECL_CONST_OCML_UNARY_F16(erfcx) +DECL_CONST_OCML_UNARY_F16(exp) +DECL_CONST_OCML_UNARY_F16(exp2) +DECL_CONST_OCML_UNARY_F16(exp10) +DECL_CONST_OCML_UNARY_F16(expm1) +DECL_CONST_OCML_UNARY_F16(fabs) +DECL_CONST_OCML_BINARY_F16(fdim) +DECL_CONST_OCML_UNARY_F16(floor) +DECL_CONST_OCML_TERNARY_F16(fma) +DECL_CONST_OCML_TERNARY_F16(fmuladd) +DECL_CONST_OCML_TERNARY_F16(fma_rte) +DECL_CONST_OCML_TERNARY_F16(fma_rtp) +DECL_CONST_OCML_TERNARY_F16(fma_rtn) +DECL_CONST_OCML_TERNARY_F16(fma_rtz) +DECL_CONST_OCML_BINARY_F16(fmax) +DECL_CONST_OCML_BINARY_F16(fmin) +DECL_CONST_OCML_BINARY_F16(fmod) +DECL_CONST_OCML_UNARYPRED_F16(fpclassify) +extern half OCML_MANGLE_F16(fract)(half, __private half *); +extern half OCML_MANGLE_F16(frexp)(half, __private int *); +DECL_CONST_OCML_BINARY_F16(hypot) +DECL_CONST_OCML_UNARYPRED_F16(ilogb) +DECL_CONST_OCML_UNARYPRED_F16(isfinite) +DECL_CONST_OCML_UNARYPRED_F16(isinf) +DECL_CONST_OCML_UNARYPRED_F16(isnan) +DECL_CONST_OCML_UNARYPRED_F16(isnormal) +DECL_CONST_OCML_UNARY_F16(i0) +DECL_CONST_OCML_UNARY_F16(i1) +DECL_CONST_OCML_UNARY_F16(j0) +DECL_CONST_OCML_UNARY_F16(j1) +extern __attribute__((const)) half OCML_MANGLE_F16(ldexp)(half, int); +DECL_CONST_OCML_TERNARY_F16(len3) +extern __attribute__((const)) half OCML_MANGLE_F16(len4)(half, half, half, half); +DECL_CONST_OCML_UNARY_F16(lgamma) +extern half OCML_MANGLE_F16(lgamma_r)(half, __private int *); +DECL_CONST_OCML_UNARY_F16(log) +DECL_CONST_OCML_UNARY_F16(logb) +DECL_CONST_OCML_UNARY_F16(log2) +DECL_CONST_OCML_UNARY_F16(log10) +DECL_CONST_OCML_UNARY_F16(log1p) +DECL_CONST_OCML_TERNARY_F16(mad) +DECL_CONST_OCML_BINARY_F16(max) +DECL_CONST_OCML_BINARY_F16(min) +DECL_CONST_OCML_BINARY_F16(maxmag) +DECL_CONST_OCML_BINARY_F16(minmag) +extern half OCML_MANGLE_F16(modf)(half, __private half *); +extern __attribute__((const)) half OCML_MANGLE_F16(nan)(ushort); +DECL_CONST_OCML_UNARY_F16(ncdf) +DECL_CONST_OCML_UNARY_F16(ncdfinv) +DECL_CONST_OCML_UNARY_F16(nearbyint) +DECL_CONST_OCML_BINARY_F16(nextafter) +DECL_CONST_OCML_BINARY_F16(pow) +DECL_CONST_OCML_BINARY_F16(powr) +extern __attribute__((pure)) half OCML_MANGLE_F16(pown)(half, int); +extern __attribute__((pure)) half OCML_MANGLE_F16(rootn)(half, int); +DECL_CONST_OCML_UNARY_F16(pred) +DECL_CONST_OCML_UNARY_F16(rcbrt) +DECL_CONST_OCML_BINARY_F16(remainder) + +typedef struct __ocml_remquo_f16_result { + half rem; + int quo; +} __ocml_remquo_f16_result; + +extern __ocml_remquo_f16_result OCML_MANGLE_F16(remquo2)(half, half); + +OCML_DEPRECATED(OCML_MANGLE_F16(remquo), "__ocml_remquo2_f16") +extern half OCML_MANGLE_F16(remquo)(half, half, __private int *); + +DECL_CONST_OCML_BINARY_F16(rhypot) +DECL_CONST_OCML_UNARY_F16(rint) +DECL_CONST_OCML_TERNARY_F16(rlen3) +extern __attribute__((const)) half OCML_MANGLE_F16(rlen4)(half, half, half, half); +DECL_CONST_OCML_UNARY_F16(round) +DECL_CONST_OCML_UNARY_F16(rsqrt) +DECL_CONST_OCML_BINARY_F16(scalb) +extern __attribute__((const)) half OCML_MANGLE_F16(scalbn)(half, int); +DECL_CONST_OCML_UNARYPRED_F16(signbit) +DECL_CONST_OCML_UNARY_F16(sin) +DECL_CONST_OCML_UNARY_F16(sinh) +DECL_CONST_OCML_UNARY_F16(sinpi) +extern half OCML_MANGLE_F16(sincos)(half, __private half *); +extern half OCML_MANGLE_F16(sincospi)(half, __private half *); +DECL_CONST_OCML_UNARY_F16(sqrt) +DECL_CONST_OCML_UNARY_F16(sqrt_rte) +DECL_CONST_OCML_UNARY_F16(sqrt_rtp) +DECL_CONST_OCML_UNARY_F16(sqrt_rtn) +DECL_CONST_OCML_UNARY_F16(sqrt_rtz) +DECL_CONST_OCML_UNARY_F16(succ) +DECL_CONST_OCML_UNARY_F16(tan) +DECL_CONST_OCML_UNARY_F16(tanpi) +DECL_CONST_OCML_UNARY_F16(tanh) +DECL_CONST_OCML_UNARY_F16(tgamma) +DECL_CONST_OCML_UNARY_F16(trunc) +DECL_CONST_OCML_UNARY_F16(y0) +DECL_CONST_OCML_UNARY_F16(y1) + +DECL_CONST_OCML_BINARY_F16(add_rte) +DECL_CONST_OCML_BINARY_F16(add_rtp) +DECL_CONST_OCML_BINARY_F16(add_rtn) +DECL_CONST_OCML_BINARY_F16(add_rtz) + +DECL_CONST_OCML_BINARY_F16(div_rte) +DECL_CONST_OCML_BINARY_F16(div_rtp) +DECL_CONST_OCML_BINARY_F16(div_rtn) +DECL_CONST_OCML_BINARY_F16(div_rtz) + +DECL_CONST_OCML_TERNARY_F16(fma_rte) +DECL_CONST_OCML_TERNARY_F16(fma_rtp) +DECL_CONST_OCML_TERNARY_F16(fma_rtn) +DECL_CONST_OCML_TERNARY_F16(fma_rtz) + +DECL_CONST_OCML_BINARY_F16(mul_rte) +DECL_CONST_OCML_BINARY_F16(mul_rtp) +DECL_CONST_OCML_BINARY_F16(mul_rtn) +DECL_CONST_OCML_BINARY_F16(mul_rtz) + +DECL_CONST_OCML_UNARY_F16(sqrt_rte) +DECL_CONST_OCML_UNARY_F16(sqrt_rtp) +DECL_CONST_OCML_UNARY_F16(sqrt_rtn) +DECL_CONST_OCML_UNARY_F16(sqrt_rtz) + +DECL_CONST_OCML_BINARY_F16(sub_rte) +DECL_CONST_OCML_BINARY_F16(sub_rtp) +DECL_CONST_OCML_BINARY_F16(sub_rtn) +DECL_CONST_OCML_BINARY_F16(sub_rtz) + +// 2-vector functions +DECL_CONST_OCML_UNARY_2F16(acos) +DECL_CONST_OCML_UNARY_2F16(acosh) +DECL_CONST_OCML_UNARY_2F16(acospi) +DECL_CONST_OCML_UNARY_2F16(asin) +DECL_CONST_OCML_UNARY_2F16(asinh) +DECL_CONST_OCML_UNARY_2F16(asinpi) +DECL_CONST_OCML_UNARY_2F16(atan) +DECL_CONST_OCML_UNARY_2F16(atanh) +DECL_CONST_OCML_UNARY_2F16(atanpi) +DECL_CONST_OCML_BINARY_2F16(atan2) +DECL_CONST_OCML_BINARY_2F16(atan2pi) +DECL_CONST_OCML_UNARY_2F16(cbrt) +DECL_CONST_OCML_UNARY_2F16(ceil) +DECL_CONST_OCML_BINARY_2F16(copysign) +DECL_CONST_OCML_UNARY_2F16(cos) +DECL_CONST_OCML_UNARY_2F16(cosh) +DECL_CONST_OCML_UNARY_2F16(cospi) +DECL_CONST_OCML_UNARY_2F16(erf) +DECL_CONST_OCML_UNARY_2F16(erfc) +DECL_CONST_OCML_UNARY_2F16(erfinv) +DECL_CONST_OCML_UNARY_2F16(erfcinv) +DECL_CONST_OCML_UNARY_2F16(erfcx) +DECL_CONST_OCML_UNARY_2F16(exp) +DECL_CONST_OCML_UNARY_2F16(exp2) +DECL_CONST_OCML_UNARY_2F16(exp10) +DECL_CONST_OCML_UNARY_2F16(expm1) +DECL_CONST_OCML_UNARY_2F16(fabs) +DECL_CONST_OCML_BINARY_2F16(fdim) +DECL_CONST_OCML_UNARY_2F16(floor) +DECL_CONST_OCML_TERNARY_2F16(fma) +DECL_CONST_OCML_TERNARY_2F16(fmuladd) +DECL_CONST_OCML_TERNARY_2F16(fma_rte) +DECL_CONST_OCML_TERNARY_2F16(fma_rtp) +DECL_CONST_OCML_TERNARY_2F16(fma_rtn) +DECL_CONST_OCML_TERNARY_2F16(fma_rtz) +DECL_CONST_OCML_BINARY_2F16(fmax) +DECL_CONST_OCML_BINARY_2F16(fmin) +DECL_CONST_OCML_BINARY_2F16(fmod) +DECL_CONST_OCML_UNARYPRED_2F16(fpclassify) +extern half2 OCML_MANGLE_2F16(fract)(half2, __private half2 *); +extern half2 OCML_MANGLE_2F16(frexp)(half2, __private int2 *); +DECL_CONST_OCML_BINARY_2F16(hypot) +extern __attribute__((const)) int2 OCML_MANGLE_2F16(ilogb)(half2); +DECL_CONST_OCML_UNARYPRED_2F16(isfinite) +DECL_CONST_OCML_UNARYPRED_2F16(isinf) +DECL_CONST_OCML_UNARYPRED_2F16(isnan) +DECL_CONST_OCML_UNARYPRED_2F16(isnormal) +DECL_CONST_OCML_UNARY_2F16(i0) +DECL_CONST_OCML_UNARY_2F16(i1) +DECL_CONST_OCML_UNARY_2F16(j0) +DECL_CONST_OCML_UNARY_2F16(j1) +extern __attribute__((const)) half2 OCML_MANGLE_2F16(ldexp)(half2, int2); +DECL_CONST_OCML_UNARY_2F16(lgamma) +extern half2 OCML_MANGLE_2F16(lgamma_r)(half2, __private int2 *); +DECL_CONST_OCML_UNARY_2F16(log) +DECL_CONST_OCML_UNARY_2F16(logb) +DECL_CONST_OCML_UNARY_2F16(log2) +DECL_CONST_OCML_UNARY_2F16(log10) +DECL_CONST_OCML_UNARY_2F16(log1p) +DECL_CONST_OCML_TERNARY_2F16(mad) +DECL_CONST_OCML_BINARY_2F16(max) +DECL_CONST_OCML_BINARY_2F16(min) +DECL_CONST_OCML_BINARY_2F16(maxmag) +DECL_CONST_OCML_BINARY_2F16(minmag) +extern half2 OCML_MANGLE_2F16(modf)(half2, __private half2 *); +extern __attribute__((const)) half2 OCML_MANGLE_2F16(nan)(ushort2); +DECL_CONST_OCML_UNARY_2F16(ncdf) +DECL_CONST_OCML_UNARY_2F16(ncdfinv) +DECL_CONST_OCML_UNARY_2F16(nearbyint) +DECL_CONST_OCML_BINARY_2F16(nextafter) +DECL_CONST_OCML_BINARY_2F16(pow) +DECL_CONST_OCML_BINARY_2F16(powr) +extern __attribute__((pure)) half2 OCML_MANGLE_2F16(pown)(half2, int2); +extern __attribute__((pure)) half2 OCML_MANGLE_2F16(rootn)(half2, int2); +DECL_CONST_OCML_UNARY_2F16(rcbrt) +DECL_CONST_OCML_BINARY_2F16(remainder) + +typedef struct __ocml_remquo_2f16_result { + half2 rem; + int2 quo; +} __ocml_remquo_2f16_result; + +extern __ocml_remquo_2f16_result OCML_MANGLE_2F16(remquo2)(half2, half2); + +OCML_DEPRECATED(OCML_MANGLE_F16(remquo), "__ocml_remquo2_2f16") +extern half2 OCML_MANGLE_2F16(remquo)(half2, half2, __private int2 *); +DECL_CONST_OCML_UNARY_2F16(rint) +DECL_CONST_OCML_UNARY_2F16(round) +DECL_CONST_OCML_UNARY_2F16(rsqrt) +DECL_CONST_OCML_BINARY_2F16(scalb) +extern __attribute__((const)) half2 OCML_MANGLE_2F16(scalbn)(half2, int2); +DECL_CONST_OCML_UNARYPRED_2F16(signbit) +DECL_CONST_OCML_UNARY_2F16(sin) +DECL_CONST_OCML_UNARY_2F16(sinh) +DECL_CONST_OCML_UNARY_2F16(sinpi) +extern half2 OCML_MANGLE_2F16(sincos)(half2, __private half2 *); +extern half2 OCML_MANGLE_2F16(sincospi)(half2, __private half2 *); +DECL_CONST_OCML_UNARY_2F16(sqrt) +DECL_CONST_OCML_UNARY_2F16(sqrt_rte) +DECL_CONST_OCML_UNARY_2F16(sqrt_rtp) +DECL_CONST_OCML_UNARY_2F16(sqrt_rtn) +DECL_CONST_OCML_UNARY_2F16(sqrt_rtz) +DECL_CONST_OCML_UNARY_2F16(tan) +DECL_CONST_OCML_UNARY_2F16(tanpi) +DECL_CONST_OCML_UNARY_2F16(tanh) +DECL_CONST_OCML_UNARY_2F16(tgamma) +DECL_CONST_OCML_UNARY_2F16(trunc) +DECL_CONST_OCML_UNARY_2F16(y0) +DECL_CONST_OCML_UNARY_2F16(y1) + +DECL_CONST_OCML_BINARY_2F16(add_rte) +DECL_CONST_OCML_BINARY_2F16(add_rtp) +DECL_CONST_OCML_BINARY_2F16(add_rtn) +DECL_CONST_OCML_BINARY_2F16(add_rtz) + +DECL_CONST_OCML_BINARY_2F16(div_rte) +DECL_CONST_OCML_BINARY_2F16(div_rtp) +DECL_CONST_OCML_BINARY_2F16(div_rtn) +DECL_CONST_OCML_BINARY_2F16(div_rtz) + +DECL_CONST_OCML_TERNARY_2F16(fma_rte) +DECL_CONST_OCML_TERNARY_2F16(fma_rtp) +DECL_CONST_OCML_TERNARY_2F16(fma_rtn) +DECL_CONST_OCML_TERNARY_2F16(fma_rtz) + +DECL_CONST_OCML_BINARY_2F16(mul_rte) +DECL_CONST_OCML_BINARY_2F16(mul_rtp) +DECL_CONST_OCML_BINARY_2F16(mul_rtn) +DECL_CONST_OCML_BINARY_2F16(mul_rtz) + +DECL_CONST_OCML_UNARY_2F16(sqrt_rte) +DECL_CONST_OCML_UNARY_2F16(sqrt_rtp) +DECL_CONST_OCML_UNARY_2F16(sqrt_rtn) +DECL_CONST_OCML_UNARY_2F16(sqrt_rtz) + +DECL_CONST_OCML_BINARY_2F16(sub_rte) +DECL_CONST_OCML_BINARY_2F16(sub_rtp) +DECL_CONST_OCML_BINARY_2F16(sub_rtn) +DECL_CONST_OCML_BINARY_2F16(sub_rtz) + +DECL_CONST_OCML_UNARY_F16(native_recip) +DECL_CONST_OCML_UNARY_F16(native_sqrt) +DECL_CONST_OCML_UNARY_F16(native_rsqrt) +DECL_CONST_OCML_UNARY_F16(native_sin) +DECL_CONST_OCML_UNARY_F16(native_cos) +DECL_CONST_OCML_UNARY_F16(native_exp2) +DECL_CONST_OCML_UNARY_F16(native_log2) + +extern __attribute__((const)) float OCML_MANGLE_F32(cabs)(float2); +extern __attribute__((const)) double OCML_MANGLE_F64(cabs)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(cacos)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(cacos)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(cacosh)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(cacosh)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(casin)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(casin)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(casinh)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(casinh)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(catan)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(catan)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(catanh)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(catanh)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(cexp)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(cexp)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(clog)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(clog)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(ccos)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(ccos)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(ccosh)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(ccosh)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(csin)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(csin)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(csinh)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(csinh)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(ctan)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(ctan)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(ctanh)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(ctanh)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(csqrt)(float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(csqrt)(double2); + +extern __attribute__((const)) float2 OCML_MANGLE_F32(cdiv)(float2, float2); +extern __attribute__((const)) double2 OCML_MANGLE_F64(cdiv)(double2, double2); + +extern __attribute__((const)) half OCML_MANGLE_F32(cvtrtn_f16)(float a); +extern __attribute__((const)) half OCML_MANGLE_F32(cvtrtp_f16)(float a); +extern __attribute__((const)) half OCML_MANGLE_F32(cvtrtz_f16)(float a); +extern __attribute__((const)) half OCML_MANGLE_F64(cvtrte_f16)(double a); +extern __attribute__((const)) half OCML_MANGLE_F64(cvtrtn_f16)(double a); +extern __attribute__((const)) half OCML_MANGLE_F64(cvtrtp_f16)(double a); +extern __attribute__((const)) half OCML_MANGLE_F64(cvtrtz_f16)(double a); +extern __attribute__((const)) float OCML_MANGLE_F64(cvtrtn_f32)(double a); +extern __attribute__((const)) float OCML_MANGLE_F64(cvtrtp_f32)(double a); +extern __attribute__((const)) float OCML_MANGLE_F64(cvtrtz_f32)(double a); +extern __attribute__((const)) float OCML_MANGLE_S32(cvtrtn_f32)(int); +extern __attribute__((const)) float OCML_MANGLE_S32(cvtrtp_f32)(int); +extern __attribute__((const)) float OCML_MANGLE_S32(cvtrtz_f32)(int); +extern __attribute__((const)) float OCML_MANGLE_U32(cvtrtn_f32)(uint); +extern __attribute__((const)) float OCML_MANGLE_U32(cvtrtp_f32)(uint); +extern __attribute__((const)) float OCML_MANGLE_U32(cvtrtz_f32)(uint); +extern __attribute__((const)) float OCML_MANGLE_S64(cvtrtn_f32)(long); +extern __attribute__((const)) float OCML_MANGLE_S64(cvtrtp_f32)(long); +extern __attribute__((const)) float OCML_MANGLE_S64(cvtrtz_f32)(long); +extern __attribute__((const)) float OCML_MANGLE_U64(cvtrtn_f32)(ulong); +extern __attribute__((const)) float OCML_MANGLE_U64(cvtrtp_f32)(ulong); +extern __attribute__((const)) float OCML_MANGLE_U64(cvtrtz_f32)(ulong); +extern __attribute__((const)) double OCML_MANGLE_S64(cvtrtn_f64)(long); +extern __attribute__((const)) double OCML_MANGLE_S64(cvtrtp_f64)(long); +extern __attribute__((const)) double OCML_MANGLE_S64(cvtrtz_f64)(long); +extern __attribute__((const)) double OCML_MANGLE_U64(cvtrtn_f64)(ulong); +extern __attribute__((const)) double OCML_MANGLE_U64(cvtrtp_f64)(ulong); +extern __attribute__((const)) double OCML_MANGLE_U64(cvtrtz_f64)(ulong); + +#pragma OPENCL EXTENSION cl_khr_fp16 : disable + +#endif // OCML_H diff --git a/amd/device-libs/ocml/src/acosD.cl b/amd/device-libs/ocml/src/acosD.cl new file mode 100644 index 0000000000000..f50dcd61a9ef5 --- /dev/null +++ b/amd/device-libs/ocml/src/acosD.cl @@ -0,0 +1,57 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double +MATH_MANGLE(acos)(double x) +{ + // Computes arccos(x). + // The argument is first reduced by noting that arccos(x) + // is invalid for abs(x) > 1. For denormal and small + // arguments arccos(x) = pi/2 to machine accuracy. + // Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arccos(x) = pi/2 - arcsin(x) + // = pi/2 - (x + x^3*R(x^2)) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arccos(x) = pi - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + double y = BUILTIN_ABS_F64(x); + bool transform = y >= 0.5; + + double rt = MATH_MAD(y, -0.5, 0.5); + double y2 = y * y; + double r = transform ? rt : y2; + + double u = r * MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + 0x1.059859fea6a70p-5, -0x1.0a5a378a05eafp-6), 0x1.4052137024d6ap-6), 0x1.ab3a098a70509p-8), + 0x1.8ed60a300c8d2p-7), 0x1.c6fa84b77012bp-7), 0x1.1c6c111dccb70p-6), 0x1.6e89f0a0adacfp-6), + 0x1.f1c72c668963fp-6), 0x1.6db6db41ce4bdp-5), 0x1.333333336fd5bp-4), 0x1.5555555555380p-3); + + double z = MATH_MAD(0x1.dd9ad336a0500p-1, 0x1.af154eeb562d6p+0, -MATH_MAD(x, u, x)); + if (transform) { + double2 s = root2(r); + double zm = MATH_MAD(0x1.dd9ad336a0500p+0, 0x1.af154eeb562d6p+0, -2.0*MATH_MAD(s.hi, u, s.hi)); + double zp = 2.0 * (s.hi + MATH_MAD(s.hi, u, s.lo)); + z = x < 0.0 ? zm : zp; + z = x == -1.0 ? 0x1.921fb54442d18p+1 : z; + z = x == 1.0 ? 0.0 : z; + } + + return z; +} + diff --git a/amd/device-libs/ocml/src/acosF.cl b/amd/device-libs/ocml/src/acosF.cl new file mode 100644 index 0000000000000..1ab7289a68ad2 --- /dev/null +++ b/amd/device-libs/ocml/src/acosF.cl @@ -0,0 +1,48 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(acos)(float x) +{ + // Computes arccos(x). + // The argument is first reduced by noting that arccos(x) + // is invalid for abs(x) > 1 and arccos(-x) = arccos(x). + // For denormal and small arguments arccos(x) = pi/2 to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arccos(x) = pi/2 - arcsin(x) + // = pi/2 - (x + x^3*R(x^2)) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arccos(x) = pi - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + float ax = BUILTIN_ABS_F32(x); + + float rt = MATH_MAD(-0.5f, ax, 0.5f); + float x2 = ax * ax; + float r = ax > 0.5f ? rt : x2; + + float u = r * MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, + 0x1.38434ep-5f, 0x1.bf8bb4p-7f), 0x1.069878p-5f), 0x1.6c8362p-5f), + 0x1.33379p-4f), 0x1.555558p-3f); + + float s = MATH_FAST_SQRT(r); + float ztp = 2.0f * MATH_MAD(s, u, s); + float ztn = MATH_MAD(0x1.ddcb02p+0f, 0x1.aee9d6p+0f, -ztp); + float zt = x < 0.0f ? ztn : ztp; + float z = MATH_MAD(0x1.ddcb02p-1f, 0x1.aee9d6p+0f, -MATH_MAD(x, u, x)); + z = ax > 0.5f ? zt : z; + + return z; +} + diff --git a/amd/device-libs/ocml/src/acosH.cl b/amd/device-libs/ocml/src/acosH.cl new file mode 100644 index 0000000000000..511f6f7030486 --- /dev/null +++ b/amd/device-libs/ocml/src/acosH.cl @@ -0,0 +1,47 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(acos) + +CONSTATTR half +MATH_MANGLE(acos)(half x) +{ + // Computes arccos(x). + // The argument is first reduced by noting that arccos(x) + // is invalid for abs(x) > 1 and arccos(-x) = arccos(x). + // For denormal and small arguments arccos(x) = pi/2 to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arccos(x) = pi/2 - arcsin(x) + // = pi/2 - (x + x^3*R(x^2)) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arccos(x) = pi - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + half ax = BUILTIN_ABS_F16(x); + + half rt = MATH_MAD(-0.5h, ax, 0.5h); + half x2 = ax * ax; + half r = ax > 0.5h ? rt : x2; + + half u = r * MATH_MAD(r, 0x1.828p-4h, 0x1.52p-3h); + + half s = MATH_FAST_SQRT(r); + half ztp = 2.0h * MATH_MAD(s, u, s); + half ztn = MATH_MAD(0x1.ea8p+0h, 0x1.a3cp+0h, -ztp); + half zt = x < 0.0h ? ztn : ztp; + half z = MATH_MAD(0x1.ea8p-1h, 0x1.a3cp+0h, -MATH_MAD(x, u, x)); + z = ax > 0.5h ? zt : z; + + return z; +} + diff --git a/amd/device-libs/ocml/src/acoshD.cl b/amd/device-libs/ocml/src/acoshD.cl new file mode 100644 index 0000000000000..54f812ad5fe1f --- /dev/null +++ b/amd/device-libs/ocml/src/acoshD.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double MATH_PRIVATE(lnep)(double2 a, int ea); + +CONSTATTR double +MATH_MANGLE(acosh)(double x) +{ + bool b = x >= 0x1.0p+512; + double s = b ? 0x1.0p-512 : 1.0; + double sx = x * s; + double2 a = add(sx, root2(sub(sqr(sx), s*s))); + double z = MATH_PRIVATE(lnep)(a, b ? 512 : 0); + + if (!FINITE_ONLY_OPT()) { + z = x == PINF_F64 ? x : z; + z = x < 1.0 ? QNAN_F64 : z; + } + + return z; +} + diff --git a/amd/device-libs/ocml/src/acoshF.cl b/amd/device-libs/ocml/src/acoshF.cl new file mode 100644 index 0000000000000..89ecc79639b7d --- /dev/null +++ b/amd/device-libs/ocml/src/acoshF.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float MATH_PRIVATE(lnep)(float2 a, int ea); + +CONSTATTR float +MATH_MANGLE(acosh)(float x) +{ + bool b = x >= 0x1.0p+64f; + float s = b ? 0x1.0p-64f : 1.0f; + float sx = x * s; + float2 a = add(sx, root2(sub(sqr(sx), s*s))); + float z = MATH_PRIVATE(lnep)(a, b ? 64 : 0); + + if (!FINITE_ONLY_OPT()) { + z = x == PINF_F32 ? x : z; + z = x < 1.0f ? QNAN_F32 : z; + } + + return z; +} + diff --git a/amd/device-libs/ocml/src/acoshH.cl b/amd/device-libs/ocml/src/acoshH.cl new file mode 100644 index 0000000000000..bd0c2d4116277 --- /dev/null +++ b/amd/device-libs/ocml/src/acoshH.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(acosh) + +CONSTATTR half +MATH_MANGLE(acosh)(half hx) +{ + half ret; + float x = (float)hx; + float t = x + BUILTIN_AMDGPU_SQRT_F32(BUILTIN_MAD_F32(x, x, -1.0f)); + ret = (half)(BUILTIN_AMDGPU_LOG2_F32(t) * 0x1.62e430p-1f); + + if (!FINITE_ONLY_OPT()) { + ret = hx < 1.0h ? QNAN_F16 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/acospiD.cl b/amd/device-libs/ocml/src/acospiD.cl new file mode 100644 index 0000000000000..20894f10fcfc0 --- /dev/null +++ b/amd/device-libs/ocml/src/acospiD.cl @@ -0,0 +1,59 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double +MATH_MANGLE(acospi)(double x) +{ + // Computes arccos(x). + // The argument is first reduced by noting that arccos(x) + // is invalid for abs(x) > 1. For denormal and small + // arguments arccos(x) = pi/2 to machine accuracy. + // Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arccos(x) = pi/2 - arcsin(x) + // = pi/2 - (x + x^3*R(x^2)) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arccos(x) = pi - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + + double y = BUILTIN_ABS_F64(x); + bool transform = y >= 0.5; + + double rt = MATH_MAD(y, -0.5, 0.5); + double y2 = y * y; + double r = transform ? rt : y2; + + double u = r * MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + 0x1.547a51d41fb0bp-7, -0x1.6a3fb0718a8f7p-8), 0x1.a7b91f7177ee8p-8), 0x1.035d3435b8ad8p-9), + 0x1.ff0549b4e0449p-9), 0x1.21604ae288f96p-8), 0x1.6a2b36f9aec49p-8), 0x1.d2b076c914f04p-8), + 0x1.3ce53861f8f1fp-7), 0x1.d1a4529a30a69p-7), 0x1.8723a1d61d2e9p-6), 0x1.b2995e7b7af0fp-5); + + const double piinv = 0x1.45f306dc9c883p-2; + double z = 0.5 - MATH_MAD(x, u, piinv*x); + if (transform) { + double2 s = ldx(root2(r), 1); + double zm = 1.0 - MATH_MAD(s.hi, u, piinv*s.hi); + double2 zp = fadd(mul(piinv, s), mul(s, u)); + z = x < 0.0 ? zm : zp.hi; + z = x == -1.0 ? 1.0 : z; + z = x == 1.0 ? 0.0 : z; + } + + return z; +} + diff --git a/amd/device-libs/ocml/src/acospiF.cl b/amd/device-libs/ocml/src/acospiF.cl new file mode 100644 index 0000000000000..ef6424605f61f --- /dev/null +++ b/amd/device-libs/ocml/src/acospiF.cl @@ -0,0 +1,35 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(acospi)(float x) +{ + const float piinv = 0x1.45f306p-2f; + + float ax = BUILTIN_ABS_F32(x); + + float rt = MATH_MAD(-0.5f, ax, 0.5f); + float x2 = ax * ax; + float r = ax > 0.5f ? rt : x2; + + float u = r * MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, + -0x1.3f1c6cp-8f, 0x1.2ac560p-6f), 0x1.80aab4p-8f), 0x1.e53378p-7f), + 0x1.86680ap-6f), 0x1.b29c5ap-5f); + + float s = MATH_FAST_SQRT(r); + float ztp = 2.0f * MATH_MAD(s, u, piinv*s); + float ztn = 1.0f - ztp; + float zt = x < 0.0f ? ztn : ztp; + float z = 0.5f - MATH_MAD(x, u, piinv*x); + z = ax > 0.5f ? zt : z; + + return z; +} + diff --git a/amd/device-libs/ocml/src/acospiH.cl b/amd/device-libs/ocml/src/acospiH.cl new file mode 100644 index 0000000000000..9cea6b5f99054 --- /dev/null +++ b/amd/device-libs/ocml/src/acospiH.cl @@ -0,0 +1,49 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(acospi) + +CONSTATTR half +MATH_MANGLE(acospi)(half x) +{ + // Computes arccos(x). + // The argument is first reduced by noting that arccos(x) + // is invalid for abs(x) > 1 and arccos(-x) = arccos(x). + // For denormal and small arguments arccos(x) = pi/2 to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arccos(x) = pi/2 - arcsin(x) + // = pi/2 - (x + x^3*R(x^2)) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arccos(x) = pi - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + const half piinv = 0x1.46p-2h; + + half ax = BUILTIN_ABS_F16(x); + + half rt = MATH_MAD(-0.5h, ax, 0.5h); + half x2 = ax * ax; + half r = ax > 0.5h ? rt : x2; + + half u = r * MATH_MAD(r, 0x1.0b8p-5h, 0x1.a7cp-5h); + + half s = MATH_FAST_SQRT(r); + half ztp = 2.0h * MATH_MAD(s, u, piinv*s); + half ztn = 1.0h - ztp; + half zt = x < 0.0h ? ztn : ztp; + half z = 0.5h - MATH_MAD(x, u, piinv*x); + z = ax > 0.5h ? zt : z; + + return z; +} + diff --git a/amd/device-libs/ocml/src/addD.cl b/amd/device-libs/ocml/src/addD.cl new file mode 100644 index 0000000000000..9fe2747c12f0a --- /dev/null +++ b/amd/device-libs/ocml/src/addD.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(add_rte)(double x, double y) +{ + return x + y; +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR double \ +MATH_MANGLE(LN)(double x, double y) \ +{ \ + BUILTIN_SETROUND_F16F64(RM); \ + double ret = x + y; \ + BUILTIN_SETROUND_F16F64(ROUND_RTE); \ + return ret; \ +} + +GEN(add_rtn, ROUND_RTN) +GEN(add_rtp, ROUND_RTP) +GEN(add_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/addF.cl b/amd/device-libs/ocml/src/addF.cl new file mode 100644 index 0000000000000..1e8d9696f5121 --- /dev/null +++ b/amd/device-libs/ocml/src/addF.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(add_rte)(float x, float y) +{ + return x + y; +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR float \ +MATH_MANGLE(LN)(float x, float y) \ +{ \ + BUILTIN_SETROUND_F32(RM); \ + float ret = x + y; \ + BUILTIN_SETROUND_F32(ROUND_RTE); \ + return ret; \ +} + +GEN(add_rtn, ROUND_RTN) +GEN(add_rtp, ROUND_RTP) +GEN(add_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/addH.cl b/amd/device-libs/ocml/src/addH.cl new file mode 100644 index 0000000000000..4ff04df4edca0 --- /dev/null +++ b/amd/device-libs/ocml/src/addH.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_MANGLE(add_rte)(half x, half y) +{ + return x + y; +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR half \ +MATH_MANGLE(LN)(half x, half y) \ +{ \ + BUILTIN_SETROUND_F16F64(RM); \ + half ret = x + y; \ + BUILTIN_SETROUND_F16F64(ROUND_RTE); \ + return ret; \ +} + +GEN(add_rtn, ROUND_RTN) +GEN(add_rtp, ROUND_RTP) +GEN(add_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/asinD.cl b/amd/device-libs/ocml/src/asinD.cl new file mode 100644 index 0000000000000..97762412b966f --- /dev/null +++ b/amd/device-libs/ocml/src/asinD.cl @@ -0,0 +1,55 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double +MATH_MANGLE(asin)(double x) +{ + // Computes arcsin(x). + // The argument is first reduced by noting that arcsin(x) + // is invalid for abs(x) > 1 and arcsin(-x) = -arcsin(x). + // For denormal and small arguments arcsin(x) = x to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arcsin(x) = x + x^3*R(x^2) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arcsin(x) = pi/2 - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + + double y = BUILTIN_ABS_F64(x); + bool transform = y >= 0.5; + + double rt = MATH_MAD(y, -0.5, 0.5); + double y2 = y * y; + double r = transform ? rt : y2; + + double u = r * MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + 0x1.059859fea6a70p-5, -0x1.0a5a378a05eafp-6), 0x1.4052137024d6ap-6), 0x1.ab3a098a70509p-8), + 0x1.8ed60a300c8d2p-7), 0x1.c6fa84b77012bp-7), 0x1.1c6c111dccb70p-6), 0x1.6e89f0a0adacfp-6), + 0x1.f1c72c668963fp-6), 0x1.6db6db41ce4bdp-5), 0x1.333333336fd5bp-4), 0x1.5555555555380p-3); + + double v = MATH_MAD(y, u, y); + if (transform) { + double2 s = root2(r); + double2 ve = fsub(con(0x1.921fb54442d18p-1, 0x1.1a62633145c07p-55), fadd(s, mul(s, u))); + v = ve.hi + ve.hi; + v = y == 1.0 ? 0x1.921fb54442d18p+0 : v; + } + + return BUILTIN_COPYSIGN_F64(v, x); +} + diff --git a/amd/device-libs/ocml/src/asinF.cl b/amd/device-libs/ocml/src/asinF.cl new file mode 100644 index 0000000000000..4c32c4207ea7d --- /dev/null +++ b/amd/device-libs/ocml/src/asinF.cl @@ -0,0 +1,45 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(asin)(float x) +{ + // Computes arcsin(x). + // The argument is first reduced by noting that arcsin(x) + // is invalid for abs(x) > 1 and arcsin(-x) = -arcsin(x). + // For denormal and small arguments arcsin(x) = x to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arcsin(x) = x + x^3*R(x^2) + // where R(x^2) is a polynomial minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arcsin(x) = pi/2 - 2*arcsin(sqrt(1-x)/2) + // together with the above polynomial approximation, and + // reconstruct the terms carefully. + + float ax = BUILTIN_ABS_F32(x); + float tx = MATH_MAD(ax, -0.5f, 0.5f); + float x2 = x*x; + float r = ax >= 0.5f ? tx : x2; + + float u = r * MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, + 0x1.38434ep-5f, 0x1.bf8bb4p-7f), 0x1.069878p-5f), 0x1.6c8362p-5f), + 0x1.33379p-4f), 0x1.555558p-3f); + + float s = MATH_FAST_SQRT(r); + float ret = MATH_MAD(0x1.ddcb02p-1f, 0x1.aee9d6p+0f, -2.0f*MATH_MAD(s, u, s)); + + float xux = MATH_MAD(ax, u, ax); + ret = ax < 0.5f ? xux : ret; + + return BUILTIN_COPYSIGN_F32(ret, x); +} + diff --git a/amd/device-libs/ocml/src/asinH.cl b/amd/device-libs/ocml/src/asinH.cl new file mode 100644 index 0000000000000..ae14dc497031b --- /dev/null +++ b/amd/device-libs/ocml/src/asinH.cl @@ -0,0 +1,45 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(asin) + +CONSTATTR half +MATH_MANGLE(asin)(half x) +{ + // Computes arcsin(x). + // The argument is first reduced by noting that arcsin(x) + // is invalid for abs(x) > 1 and arcsin(-x) = -arcsin(x). + // For denormal and small arguments arcsin(x) = x to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arcsin(x) = x + x^3*R(x^2) + // where R(x^2) is a polynomial minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arcsin(x) = pi/2 - 2*arcsin(sqrt(1-x)/2) + // together with the above polynomial approximation, and + // reconstruct the terms carefully. + + half ax = BUILTIN_ABS_F16(x); + half r; + + if (ax <= 0.5h) { + half s = x * x; + half p = s * MATH_MAD(s, 0x1.828p-4h, 0x1.52p-3h); + r = MATH_MAD(ax, p, ax); + } else { + float s = BUILTIN_MAD_F32((float)ax, -0.5f, 0.5f); + float t = BUILTIN_AMDGPU_SQRT_F32(s); + float p = BUILTIN_MAD_F32(t, BUILTIN_MAD_F32(s, -0x1.82675ap-2f, -0x1.ff9f6p+0f), 0x1.921fb6p+0f); + r = (half)p; + } + + return BUILTIN_COPYSIGN_F16(r, x); +} + diff --git a/amd/device-libs/ocml/src/asinhD.cl b/amd/device-libs/ocml/src/asinhD.cl new file mode 100644 index 0000000000000..c9552ae00912a --- /dev/null +++ b/amd/device-libs/ocml/src/asinhD.cl @@ -0,0 +1,33 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double MATH_PRIVATE(lnep)(double2 a, int ea); + + +CONSTATTR double +MATH_MANGLE(asinh)(double x) +{ + double y = BUILTIN_ABS_F64(x); + bool b = y >= 0x1.0p+512; + double s = b ? 0x1.0p-512 : 1.0; + double sy = y * s; + double2 a = add(sy, root2(add(sqr(sy), s*s))); + double z = MATH_PRIVATE(lnep)(a, b ? 512 : 0); + z = y < 0x1.0p-27 ? y : z; + + if (!FINITE_ONLY_OPT()) { + z = y == PINF_F64 ? y : z; + } + + return BUILTIN_COPYSIGN_F64(z, x); +} + diff --git a/amd/device-libs/ocml/src/asinhF.cl b/amd/device-libs/ocml/src/asinhF.cl new file mode 100644 index 0000000000000..0f9ae149281fc --- /dev/null +++ b/amd/device-libs/ocml/src/asinhF.cl @@ -0,0 +1,33 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float MATH_PRIVATE(lnep)(float2 a, int ea); + +CONSTATTR float +MATH_MANGLE(asinh)(float x) +{ + float y = BUILTIN_ABS_F32(x); + bool b = y >= 0x1.0p+64f; + float s = b ? 0x1.0p-64f : 1.0f; + float sy = y * s; + float2 a = add(sy, root2(add(sqr(sy), s*s))); + float z = MATH_PRIVATE(lnep)(a, b ? 64 : 0); + + z = y < 0x1.0p-12f ? y : z; + + if (!FINITE_ONLY_OPT()) { + z = y == PINF_F32 ? y : z; + } + + return BUILTIN_COPYSIGN_F32(z, x); +} + diff --git a/amd/device-libs/ocml/src/asinhH.cl b/amd/device-libs/ocml/src/asinhH.cl new file mode 100644 index 0000000000000..25be0b0fb53a3 --- /dev/null +++ b/amd/device-libs/ocml/src/asinhH.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(asinh) + +CONSTATTR half +MATH_MANGLE(asinh)(half hx) +{ + half ret; + float x = (float)BUILTIN_ABS_F16(hx); + float t = x + BUILTIN_AMDGPU_SQRT_F32(BUILTIN_MAD_F32(x, x, 1.0f)); + ret = BUILTIN_COPYSIGN_F16((half)(BUILTIN_AMDGPU_LOG2_F32(t) * 0x1.62e430p-1f), hx); + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_ISFINITE_F16(hx) ? ret : hx; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/asinpiD.cl b/amd/device-libs/ocml/src/asinpiD.cl new file mode 100644 index 0000000000000..bda0a3cd5c4e1 --- /dev/null +++ b/amd/device-libs/ocml/src/asinpiD.cl @@ -0,0 +1,55 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double +MATH_MANGLE(asinpi)(double x) +{ + // Computes arcsin(x). + // The argument is first reduced by noting that arcsin(x) + // is invalid for abs(x) > 1 and arcsin(-x) = -arcsin(x). + // For denormal and small arguments arcsin(x) = x to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arcsin(x) = x + x^3*R(x^2) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arcsin(x) = pi/2 - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + double y = BUILTIN_ABS_F64(x); + bool transform = y >= 0.5; + + double rt = MATH_MAD(y, -0.5, 0.5); + double y2 = y * y; + double r = transform ? rt : y2; + + double u = r * MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + 0x1.547a51d41fb0bp-7, -0x1.6a3fb0718a8f7p-8), 0x1.a7b91f7177ee8p-8), 0x1.035d3435b8ad8p-9), + 0x1.ff0549b4e0449p-9), 0x1.21604ae288f96p-8), 0x1.6a2b36f9aec49p-8), 0x1.d2b076c914f04p-8), + 0x1.3ce53861f8f1fp-7), 0x1.d1a4529a30a69p-7), 0x1.8723a1d61d2e9p-6), 0x1.b2995e7b7af0fp-5); + + const double piinv = 0x1.45f306dc9c883p-2; + double v = MATH_MAD(y, piinv, y*u); + if (transform) { + double2 s = ldx(root2(r), 1); + double2 ve = fsub(0.5, fadd(mul(piinv, s), mul(s, u))); + v = ve.hi; + v = y == 1.0 ? 0.5 : v; + } + + return BUILTIN_COPYSIGN_F64(v, x); +} + diff --git a/amd/device-libs/ocml/src/asinpiF.cl b/amd/device-libs/ocml/src/asinpiF.cl new file mode 100644 index 0000000000000..02311389da029 --- /dev/null +++ b/amd/device-libs/ocml/src/asinpiF.cl @@ -0,0 +1,47 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(asinpi)(float x) +{ + // Computes arcsin(x). + // The argument is first reduced by noting that arcsin(x) + // is invalid for abs(x) > 1 and arcsin(-x) = -arcsin(x). + // For denormal and small arguments arcsin(x) = x to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arcsin(x) = x + x^3*R(x^2) + // where R(x^2) is a polynomial minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arcsin(x) = pi/2 - 2*arcsin(sqrt(1-x)/2) + // together with the above polynomial approximation, and + // reconstruct the terms carefully. + + const float piinv = 0x1.45f306p-2f; + + float ax = BUILTIN_ABS_F32(x); + + float tx = MATH_MAD(ax, -0.5f, 0.5f); + float x2 = ax * ax; + float r = ax >= 0.5f ? tx : x2; + + float u = r * MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, MATH_MAD(r, + MATH_MAD(r, + -0x1.3f1c6cp-8f, 0x1.2ac560p-6f), 0x1.80aab4p-8f), 0x1.e53378p-7f), + 0x1.86680ap-6f), 0x1.b29c5ap-5f); + + float s = MATH_FAST_SQRT(r); + float ret = MATH_MAD(-2.0f, MATH_MAD(s, u, piinv*s), 0.5f); + float xux = MATH_MAD(piinv, ax, ax*u); + ret = ax >= 0.5f ? ret : xux; + + return BUILTIN_COPYSIGN_F32(ret, x); +} + diff --git a/amd/device-libs/ocml/src/asinpiH.cl b/amd/device-libs/ocml/src/asinpiH.cl new file mode 100644 index 0000000000000..9c24ac5c1b515 --- /dev/null +++ b/amd/device-libs/ocml/src/asinpiH.cl @@ -0,0 +1,47 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(asinpi) + +CONSTATTR half +MATH_MANGLE(asinpi)(half x) +{ + // Computes arcsin(x). + // The argument is first reduced by noting that arcsin(x) + // is invalid for abs(x) > 1 and arcsin(-x) = -arcsin(x). + // For denormal and small arguments arcsin(x) = x to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arcsin(x) = x + x^3*R(x^2) + // where R(x^2) is a polynomial minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arcsin(x) = pi/2 - 2*arcsin(sqrt(1-x)/2) + // together with the above polynomial approximation, and + // reconstruct the terms carefully. + + const half piinv = 0x1.45f306p-2h; + + half ax = BUILTIN_ABS_F16(x); + + half r; + if (ax <= 0.5h) { + half s = x * x; + r = ax * MATH_MAD(s, MATH_MAD(s, 0x1.0b8p-5h, 0x1.a7cp-5h), 0x1.46p-2h); + } else { + float s = BUILTIN_MAD_F32((float)ax, -0.5f, 0.5f); + float t = BUILTIN_AMDGPU_SQRT_F32(s); + float p = BUILTIN_MAD_F32(t, BUILTIN_MAD_F32(s, BUILTIN_MAD_F32(s, + -0x1.f4b736p-5f, -0x1.ad0826p-4f), -0x1.45f5a8p-1f), 0.5f); + r = (half)p; + } + + return BUILTIN_COPYSIGN_F16(r, x); +} + diff --git a/amd/device-libs/ocml/src/atan2D.cl b/amd/device-libs/ocml/src/atan2D.cl new file mode 100644 index 0000000000000..5c5e76bbbe253 --- /dev/null +++ b/amd/device-libs/ocml/src/atan2D.cl @@ -0,0 +1,48 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +extern CONSTATTR double MATH_PRIVATE(atanred)(double); + +CONSTATTR double +MATH_MANGLE(atan2)(double y, double x) +{ + const double pi = 0x1.921fb54442d18p+1; + const double piby2 = 0x1.921fb54442d18p+0; + const double piby4 = 0x1.921fb54442d18p-1; + const double threepiby4 = 0x1.2d97c7f3321d2p+1; + + double ay = BUILTIN_ABS_F64(y); + double ax = BUILTIN_ABS_F64(x); + double u = BUILTIN_MAX_F64(ax, ay); + double v = BUILTIN_MIN_F64(ax, ay); + double vbyu = MATH_DIV(v, u); + + double a = MATH_PRIVATE(atanred)(vbyu); + + bool xneg = AS_INT2(x).y < 0; + + double t = piby2 - a; + a = ax < ay ? t : a; + t = pi - a; + a = xneg ? t : a; + + t = xneg ? pi : 0.0; + a = y == 0.0 ? t : a; + + if (!FINITE_ONLY_OPT()) { + t = xneg ? threepiby4 : piby4; + t = BUILTIN_COPYSIGN_F64(t, y); + a = (BUILTIN_ISINF_F64(x) & BUILTIN_ISINF_F64(y)) ? t : a; + + a = BUILTIN_ISUNORDERED_F64(x, y) ? QNAN_F64 : a; + } + + return BUILTIN_COPYSIGN_F64(a, y); +} + diff --git a/amd/device-libs/ocml/src/atan2F.cl b/amd/device-libs/ocml/src/atan2F.cl new file mode 100644 index 0000000000000..78db7fae0e4ae --- /dev/null +++ b/amd/device-libs/ocml/src/atan2F.cl @@ -0,0 +1,54 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +extern CONSTATTR float MATH_PRIVATE(atanred)(float); + +CONSTATTR float +MATH_MANGLE(atan2)(float y, float x) +{ + const float pi = 0x1.921fb6p+1f; + const float piby2 = 0x1.921fb6p+0f; + const float piby4 = 0x1.921fb6p-1f; + const float threepiby4 = 0x1.2d97c8p+1f; + + float ax = BUILTIN_ABS_F32(x); + float ay = BUILTIN_ABS_F32(y); + float v = BUILTIN_MIN_F32(ax, ay); + float u = BUILTIN_MAX_F32(ax, ay); + + float vbyu; + if (DAZ_OPT()) { + float s = u > 0x1.0p+96f ? 0x1.0p-32f : 1.0f; + vbyu = s * MATH_FAST_DIV(v, s*u); + } else { + vbyu = MATH_DIV(v, u); + } + + float a = MATH_PRIVATE(atanred)(vbyu); + + float t = piby2 - a; + a = ay > ax ? t : a; + t = pi - a; + a = x < 0.0f ? t : a; + + t = AS_INT(x) < 0 ? pi : 0.0f; + a = y == 0.0f ? t : a; + + if (!FINITE_ONLY_OPT()) { + // x and y are +- Inf + t = x < 0.0f ? threepiby4 : piby4; + a = (BUILTIN_ISINF_F32(x) & BUILTIN_ISINF_F32(y)) ? t : a; + + // x or y is NaN + a = BUILTIN_ISUNORDERED_F32(x, y) ? QNAN_F32 : a; + } + + return BUILTIN_COPYSIGN_F32(a, y); +} + diff --git a/amd/device-libs/ocml/src/atan2H.cl b/amd/device-libs/ocml/src/atan2H.cl new file mode 100644 index 0000000000000..b032fc2c64c6d --- /dev/null +++ b/amd/device-libs/ocml/src/atan2H.cl @@ -0,0 +1,51 @@ + +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +extern CONSTATTR half MATH_PRIVATE(atanred)(half); + +CONSTATTR BGEN(atan2) + +CONSTATTR half +MATH_MANGLE(atan2)(half y, half x) +{ + const half pi = 0x1.921fb6p+1h; + const half piby2 = 0x1.921fb6p+0h; + const half piby4 = 0x1.921fb6p-1h; + const half threepiby4 = 0x1.2d97c8p+1h; + + half ax = BUILTIN_ABS_F16(x); + half ay = BUILTIN_ABS_F16(y); + half v = BUILTIN_MIN_F16(ax, ay); + half u = BUILTIN_MAX_F16(ax, ay); + + half vbyu = MATH_DIV(v, u); + + half a = MATH_PRIVATE(atanred)(vbyu); + + half t = piby2 - a; + a = ay > ax ? t : a; + t = pi - a; + a = x < 0.0h ? t : a; + + t = AS_SHORT(x) < 0 ? pi : 0.0h; + a = y == 0.0h ? t : a; + + if (!FINITE_ONLY_OPT()) { + // x and y are +- Inf + t = x < 0.0h ? threepiby4 : piby4; + a = (BUILTIN_ISINF_F16(x) & BUILTIN_ISINF_F16(y)) ? t : a; + + // x or y is NaN + a = BUILTIN_ISUNORDERED_F16(x, y) ? QNAN_F16 : a; + } + + return BUILTIN_COPYSIGN_F16(a, y); +} + diff --git a/amd/device-libs/ocml/src/atan2piD.cl b/amd/device-libs/ocml/src/atan2piD.cl new file mode 100644 index 0000000000000..f04680cb9f999 --- /dev/null +++ b/amd/device-libs/ocml/src/atan2piD.cl @@ -0,0 +1,45 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +extern CONSTATTR double MATH_PRIVATE(atanpired)(double); + +CONSTATTR double +MATH_MANGLE(atan2pi)(double y, double x) +{ + const double pi = 0x1.921fb54442d18p+1; + + double ay = BUILTIN_ABS_F64(y); + double ax = BUILTIN_ABS_F64(x); + double u = BUILTIN_MAX_F64(ax, ay); + double v = BUILTIN_MIN_F64(ax, ay); + double vbyu = MATH_DIV(v, u); + + double a = MATH_PRIVATE(atanpired)(vbyu); + + bool xneg = AS_INT2(x).y < 0; + + double t = 0.5 - a; + a = ax < ay ? t : a; + t = 1.0 - a; + a = xneg ? t : a; + + t = xneg ? 1.0 : 0.0; + a = y == 0.0 ? t : a; + + if (!FINITE_ONLY_OPT()) { + t = xneg ? 0.75 : 0.25; + t = BUILTIN_COPYSIGN_F64(t, y); + a = (BUILTIN_ISINF_F64(x) & BUILTIN_ISINF_F64(y)) ? t : a; + + a = BUILTIN_ISUNORDERED_F64(x, y) ? QNAN_F64 : a; + } + + return BUILTIN_COPYSIGN_F64(a, y); +} + diff --git a/amd/device-libs/ocml/src/atan2piF.cl b/amd/device-libs/ocml/src/atan2piF.cl new file mode 100644 index 0000000000000..d55c845cb14f2 --- /dev/null +++ b/amd/device-libs/ocml/src/atan2piF.cl @@ -0,0 +1,50 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +extern CONSTATTR float MATH_PRIVATE(atanpired)(float); + +CONSTATTR float +MATH_MANGLE(atan2pi)(float y, float x) +{ + const float pi = 0x1.921fb6p+1f; + + float ax = BUILTIN_ABS_F32(x); + float ay = BUILTIN_ABS_F32(y); + float v = BUILTIN_MIN_F32(ax, ay); + float u = BUILTIN_MAX_F32(ax, ay); + + float vbyu; + if (DAZ_OPT()) { + float s = u > 0x1.0p+96f ? 0x1.0p-32f : 1.0f; + vbyu = s * MATH_FAST_DIV(v, s*u); + } else { + vbyu = MATH_DIV(v, u); + } + + float a = MATH_PRIVATE(atanpired)(vbyu); + + float at = 0.5f - a; + a = ay > ax ? at : a; + at = 1.0f - a; + a = x < 0.0f ? at : a; + + at = AS_INT(x) < 0 ? 1.0f : 0.0f; + a = y == 0.0f ? at : a; + + if (!FINITE_ONLY_OPT()) { + // x and y are +- Inf + at = x < 0.0f ? 0.75f : 0.25f; + a = (BUILTIN_ISINF_F32(x) & BUILTIN_ISINF_F32(y)) ? at : a; + + // x or y is NaN + a = BUILTIN_ISUNORDERED_F32(x, y) ? QNAN_F32 : a; + } + + return BUILTIN_COPYSIGN_F32(a, y); +} diff --git a/amd/device-libs/ocml/src/atan2piH.cl b/amd/device-libs/ocml/src/atan2piH.cl new file mode 100644 index 0000000000000..dde92a6c24ccf --- /dev/null +++ b/amd/device-libs/ocml/src/atan2piH.cl @@ -0,0 +1,47 @@ + +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +extern CONSTATTR half MATH_PRIVATE(atanpired)(half); + +CONSTATTR BGEN(atan2pi) + + +CONSTATTR half +MATH_MANGLE(atan2pi)(half y, half x) +{ + half ax = BUILTIN_ABS_F16(x); + half ay = BUILTIN_ABS_F16(y); + half v = BUILTIN_MIN_F16(ax, ay); + half u = BUILTIN_MAX_F16(ax, ay); + + half vbyu = MATH_DIV(v, u); + + half a = MATH_PRIVATE(atanpired)(vbyu); + + half at = 0.5h - a; + a = ay > ax ? at : a; + at = 1.0h - a; + a = x < 0.0h ? at : a; + + at = AS_SHORT(x) < 0 ? 1.0h : 0.0h; + a = y == 0.0h ? at : a; + + if (!FINITE_ONLY_OPT()) { + // x and y are +- Inf + at = x < 0.0h ? 0.75h : 0.25h; + a = (BUILTIN_ISINF_F16(x) & BUILTIN_ISINF_F16(y)) ? + at : a; + + // x or y is NaN + a = BUILTIN_ISUNORDERED_F16(x, y) ? QNAN_F16 : a; + } + + return BUILTIN_COPYSIGN_F16(a, y); +} diff --git a/amd/device-libs/ocml/src/atanD.cl b/amd/device-libs/ocml/src/atanD.cl new file mode 100644 index 0000000000000..29b5d9ccaba1d --- /dev/null +++ b/amd/device-libs/ocml/src/atanD.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +extern CONSTATTR double MATH_PRIVATE(atanred)(double); + +CONSTATTR double +MATH_MANGLE(atan)(double x) +{ + double v = BUILTIN_ABS_F64(x); + bool g = v > 1.0; + + if (g) { + v = MATH_RCP(v); + } + + double a = MATH_PRIVATE(atanred)(v); + + double y = BUILTIN_FMA_F64(0x1.dd9ad336a0500p-1, 0x1.af154eeb562d6p+0, -a); + a = g ? y : a; + + return BUILTIN_COPYSIGN_F64(a, x); +} + diff --git a/amd/device-libs/ocml/src/atanF.cl b/amd/device-libs/ocml/src/atanF.cl new file mode 100644 index 0000000000000..08a7b1b10335c --- /dev/null +++ b/amd/device-libs/ocml/src/atanF.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +extern CONSTATTR float MATH_PRIVATE(atanred)(float); + +CONSTATTR float +MATH_MANGLE(atan)(float x) +{ + float v = BUILTIN_ABS_F32(x); + bool g = v > 1.0f; + + float vi = MATH_FAST_RCP(v); + v = g ? vi : v; + + float a = MATH_PRIVATE(atanred)(v); + + float y = MATH_MAD(0x1.ddcb02p-1f, 0x1.aee9d6p+0f, -a); + a = g ? y : a; + + return BUILTIN_COPYSIGN_F32(a, x); +} + diff --git a/amd/device-libs/ocml/src/atanH.cl b/amd/device-libs/ocml/src/atanH.cl new file mode 100644 index 0000000000000..42ba68988a16e --- /dev/null +++ b/amd/device-libs/ocml/src/atanH.cl @@ -0,0 +1,30 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +extern CONSTATTR half MATH_PRIVATE(atanred)(half); + +CONSTATTR UGEN(atan) + +CONSTATTR half +MATH_MANGLE(atan)(half x) +{ + half v = BUILTIN_ABS_F16(x); + bool g = v > 1.0h; + + half vi = MATH_FAST_RCP(v); + v = g ? vi : v; + + half a = MATH_PRIVATE(atanred)(v); + + half y = MATH_MAD(0x1.ea8p-1h, 0x1.a3cp+0h, -a); + a = g ? y : a; + + return BUILTIN_COPYSIGN_F16(a, x); +} + diff --git a/amd/device-libs/ocml/src/atanhD.cl b/amd/device-libs/ocml/src/atanhD.cl new file mode 100644 index 0000000000000..990f18991680c --- /dev/null +++ b/amd/device-libs/ocml/src/atanhD.cl @@ -0,0 +1,30 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double MATH_PRIVATE(lnep)(double2 a, int ea); + +CONSTATTR double +MATH_MANGLE(atanh)(double x) +{ + double y = BUILTIN_ABS_F64(x); + double2 a = fdiv(fadd(1.0, y), fsub(1.0, y)); + double z = 0.5 * MATH_PRIVATE(lnep)(a, 0); + z = y < 0x1.0p-27 ? y : z; + + if (!FINITE_ONLY_OPT()) { + z = y > 1.0 ? QNAN_F64 : z; + z = y == 1.0 ? PINF_F64 : z; + } + + return BUILTIN_COPYSIGN_F64(z, x); +} + diff --git a/amd/device-libs/ocml/src/atanhF.cl b/amd/device-libs/ocml/src/atanhF.cl new file mode 100644 index 0000000000000..c0e0ce011a525 --- /dev/null +++ b/amd/device-libs/ocml/src/atanhF.cl @@ -0,0 +1,30 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float MATH_PRIVATE(lnep)(float2 a, int ea); + +CONSTATTR float +MATH_MANGLE(atanh)(float x) +{ + float y = BUILTIN_ABS_F32(x); + float2 a = fdiv(fadd(1.0f, y), fsub(1.0f, y)); + float z = 0.5f * MATH_PRIVATE(lnep)(a, 0); + z = y < 0x1.0p-12f ? y : z; + + if (!FINITE_ONLY_OPT()) { + z = y > 1.0f ? QNAN_F32 : z; + z = y == 1.0f ? PINF_F32 : z; + } + + return BUILTIN_COPYSIGN_F32(z, x); +} + diff --git a/amd/device-libs/ocml/src/atanhH.cl b/amd/device-libs/ocml/src/atanhH.cl new file mode 100644 index 0000000000000..cf496edd0816f --- /dev/null +++ b/amd/device-libs/ocml/src/atanhH.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(atanh) + +CONSTATTR half +MATH_MANGLE(atanh)(half hx) +{ + half ret; + float x = (float)BUILTIN_ABS_F16(hx); + float t = (1.0f + x) * BUILTIN_AMDGPU_RCP_F32(1.0f - x); + ret = (half)(BUILTIN_AMDGPU_LOG2_F32(t) * 0x1.62e430p-2f); + ret = x < 0x1.0p-7f ? x : ret; + + if (!FINITE_ONLY_OPT()) { + ret = x == 1.0f ? PINF_F16 : ret; + ret = (x > 1.0f) | BUILTIN_ISNAN_F32(x) ? QNAN_F16 : ret; + } + + return BUILTIN_COPYSIGN_F16(ret, hx); +} + diff --git a/amd/device-libs/ocml/src/atanpiD.cl b/amd/device-libs/ocml/src/atanpiD.cl new file mode 100644 index 0000000000000..c79e1250f09e1 --- /dev/null +++ b/amd/device-libs/ocml/src/atanpiD.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +extern CONSTATTR double MATH_PRIVATE(atanpired)(double); + +CONSTATTR double +MATH_MANGLE(atanpi)(double x) +{ + double v = BUILTIN_ABS_F64(x); + bool g = v > 1.0; + + if (g) { + v = MATH_RCP(v); + } + + double a = MATH_PRIVATE(atanpired)(v); + + double y = 0.5 - a; + a = g ? y : a; + + return BUILTIN_COPYSIGN_F64(a, x); +} + diff --git a/amd/device-libs/ocml/src/atanpiF.cl b/amd/device-libs/ocml/src/atanpiF.cl new file mode 100644 index 0000000000000..1c46c155b0bff --- /dev/null +++ b/amd/device-libs/ocml/src/atanpiF.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +extern CONSTATTR float MATH_PRIVATE(atanpired)(float); + +CONSTATTR float +MATH_MANGLE(atanpi)(float x) +{ + float v = BUILTIN_ABS_F32(x); + bool g = v > 1.0f; + + float vi = MATH_FAST_RCP(v); + v = g ? vi : v; + + float a = MATH_PRIVATE(atanpired)(v); + + float y = 0.5f - a; + a = g ? y : a; + + return BUILTIN_COPYSIGN_F32(a, x); +} + + diff --git a/amd/device-libs/ocml/src/atanpiH.cl b/amd/device-libs/ocml/src/atanpiH.cl new file mode 100644 index 0000000000000..44cb201ca77a9 --- /dev/null +++ b/amd/device-libs/ocml/src/atanpiH.cl @@ -0,0 +1,32 @@ + +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +extern CONSTATTR half MATH_PRIVATE(atanpired)(half); + +CONSTATTR UGEN(atanpi) + +CONSTATTR half +MATH_MANGLE(atanpi)(half x) +{ + half v = BUILTIN_ABS_F16(x); + bool g = v > 1.0h; + + half vi = MATH_FAST_RCP(v); + v = g ? vi : v; + + half a = MATH_PRIVATE(atanpired)(v); + + half y = 0.5h - a; + a = g ? y : a; + + return BUILTIN_COPYSIGN_F16(a, x); +} + + diff --git a/amd/device-libs/ocml/src/atanpiredD.cl b/amd/device-libs/ocml/src/atanpiredD.cl new file mode 100644 index 0000000000000..f18eaef184d27 --- /dev/null +++ b/amd/device-libs/ocml/src/atanpiredD.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_PRIVATE(atanpired)(double v) +{ + double t = v * v; + double z = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.39e58b43320d2p-18, -0x1.be9e52f5df14fp-15), 0x1.2d7a6cad8e9dbp-12), -0x1.024ebcc10f8a6p-10), + 0x1.3df92946a87d8p-9), -0x1.2f04271b6cd94p-8), 0x1.d91b9a6908690p-8), -0x1.3e1c18f5ea692p-7), + 0x1.8253e53662be6p-7), -0x1.ba3db7e462112p-7), 0x1.ed7188505388cp-7), -0x1.121f707a5851bp-6), + 0x1.32b737d7f904ap-6), -0x1.5bac13378ea68p-6), 0x1.912af944c4411p-6), -0x1.da1babd44fccfp-6), + 0x1.21bb945aacd29p-5), -0x1.7483758f7040fp-5), 0x1.04c26be3b5934p-4), -0x1.b2995e7b7b74dp-4), + 0x1.45f306dc9c883p-2); + return v * z; +} + diff --git a/amd/device-libs/ocml/src/atanpiredF.cl b/amd/device-libs/ocml/src/atanpiredF.cl new file mode 100644 index 0000000000000..63af0f76d128a --- /dev/null +++ b/amd/device-libs/ocml/src/atanpiredF.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_PRIVATE(atanpired)(float v) +{ + float t = v * v; + float z = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.ccf836p-11f, -0x1.4761e4p-8f), 0x1.b6662ep-7f), -0x1.8423b4p-6f), + 0x1.149cb4p-5f), -0x1.721cccp-5f), 0x1.04a466p-4f), -0x1.b2981cp-4f), + 0x1.45f306p-2f); + return v * z; +} + diff --git a/amd/device-libs/ocml/src/atanpiredH.cl b/amd/device-libs/ocml/src/atanpiredH.cl new file mode 100644 index 0000000000000..61dcf5c4b0e89 --- /dev/null +++ b/amd/device-libs/ocml/src/atanpiredH.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_PRIVATE(atanpired)(half v) +{ + const half ch = 0x1.45cp-2h; + const half cl = 0x1.85cp-13h; + half t = v * v; + half y = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, 0x1.f04p-8h, -0x1.dfp-6h), 0x1.e3p-5h), -0x1.b08p-4h); + half ph = v * ch; + half pl = MATH_MAD(v, ch, -ph); + half r = MATH_MAD(v, MATH_MAD(t, y, cl), pl) + ph; + return r; +} + diff --git a/amd/device-libs/ocml/src/atanredD.cl b/amd/device-libs/ocml/src/atanredD.cl new file mode 100644 index 0000000000000..d0d3eabcdef58 --- /dev/null +++ b/amd/device-libs/ocml/src/atanredD.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_PRIVATE(atanred)(double v) +{ + double t = v * v; + double z = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.ba404b5e68a13p-17, -0x1.3e260bd3237f4p-13), 0x1.b2bb069efb384p-11), -0x1.7952daf56de9bp-9), + 0x1.d6d43a595c56fp-8), -0x1.c6ea4a57d9582p-7), 0x1.67e295f08b19fp-6), -0x1.e9ae6fc27006ap-6), + 0x1.2c15b5711927ap-5), -0x1.59976e82d3ff0p-5), 0x1.82d5d6ef28734p-5), -0x1.ae5ce6a214619p-5), + 0x1.e1bb48427b883p-5), -0x1.110e48b207f05p-4), 0x1.3b13657b87036p-4), -0x1.745d119378e4fp-4), + 0x1.c71c717e1913cp-4), -0x1.2492492376b7dp-3), 0x1.99999999952ccp-3), -0x1.5555555555523p-2); + z = MATH_MAD(v, t*z, v); + return z; +} + diff --git a/amd/device-libs/ocml/src/atanredF.cl b/amd/device-libs/ocml/src/atanredF.cl new file mode 100644 index 0000000000000..a089592868d39 --- /dev/null +++ b/amd/device-libs/ocml/src/atanredF.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_PRIVATE(atanred)(float v) +{ + float t = v * v; + float z = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.5a54bp-9f, -0x1.f4b218p-7f), 0x1.53f67ep-5f), -0x1.2fa9aep-4f), + 0x1.b26364p-4f), -0x1.22c1ccp-3f), 0x1.99717ep-3f), -0x1.5554c4p-2f); + + z = MATH_MAD(v, t*z, v); + return z; +} + diff --git a/amd/device-libs/ocml/src/atanredH.cl b/amd/device-libs/ocml/src/atanredH.cl new file mode 100644 index 0000000000000..1553df78e28e0 --- /dev/null +++ b/amd/device-libs/ocml/src/atanredH.cl @@ -0,0 +1,18 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_PRIVATE(atanred)(half v) +{ + half t = v * v; + half z = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, 0x1.938p-6h, -0x1.7f4p-4h), 0x1.7dcp-3h), -0x1.54p-2); + z = MATH_MAD(t, v*z, v); + return z; +} + diff --git a/amd/device-libs/ocml/src/ba0D.cl b/amd/device-libs/ocml/src/ba0D.cl new file mode 100644 index 0000000000000..e87226bc045e5 --- /dev/null +++ b/amd/device-libs/ocml/src/ba0D.cl @@ -0,0 +1,20 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_PRIVATE(ba0)(double t) +{ + return + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.44395cd7ac32cp+20, -0x1.25bf3abbee803p+16), 0x1.55a4a78625b0fp+11), -0x1.a826c7ea56321p+6), + 0x1.763253bbf53b6p+2), -0x1.15efaff948953p-1), 0x1.a7ffff967a1d4p-4), -0x1.fffffffff2868p-5), + 0x1.0000000000000p+0); +} + diff --git a/amd/device-libs/ocml/src/ba0F.cl b/amd/device-libs/ocml/src/ba0F.cl new file mode 100644 index 0000000000000..309ad26732193 --- /dev/null +++ b/amd/device-libs/ocml/src/ba0F.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_PRIVATE(ba0)(float t) +{ + return + MATH_MAD(t, MATH_MAD(t, + 0x1.92aeccp-4f, -0x1.ffe472p-5f), 0x1.000000p+0f); +} + diff --git a/amd/device-libs/ocml/src/ba1D.cl b/amd/device-libs/ocml/src/ba1D.cl new file mode 100644 index 0000000000000..d4453e003f982 --- /dev/null +++ b/amd/device-libs/ocml/src/ba1D.cl @@ -0,0 +1,20 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_PRIVATE(ba1)(double t) +{ + return + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.7940a06621145p+20, 0x1.591fb68428bafp+16), -0x1.996552a8bafb0p+11), 0x1.0795578cd8c93p+7), + -0x1.ef38364596b5ap+2), 0x1.9c4fa465744c7p-1), -0x1.8bffffc3937c1p-3), 0x1.7ffffffffc240p-3), + 0x1.0000000000000p+0); +} + diff --git a/amd/device-libs/ocml/src/ba1F.cl b/amd/device-libs/ocml/src/ba1F.cl new file mode 100644 index 0000000000000..5dd1ea96b8376 --- /dev/null +++ b/amd/device-libs/ocml/src/ba1F.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_PRIVATE(ba1)(float t) +{ + return + MATH_MAD(t, MATH_MAD(t, + -0x1.7c0d46p-3f, 0x1.7ff5aap-3f), 0x1.000000p+0f); +} + diff --git a/amd/device-libs/ocml/src/besselD_table.h b/amd/device-libs/ocml/src/besselD_table.h new file mode 100644 index 0000000000000..e3cca79098ec9 --- /dev/null +++ b/amd/device-libs/ocml/src/besselD_table.h @@ -0,0 +1,848 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +DECLARE_TABLE(double, M64_J0, 8*15) + 1.0, + -0.14269328868608038e-15, + -0.24999999999999378, + -0.10717704790389966e-12, + 0.015625000000966751, + -0.52511567891715885e-11, + -0.00043402775917084975, + -0.45154263377571991e-10, + 0.6781761279002329e-5, + -0.94524619593582299e-10, + -0.67734011417068302e-7, + -0.51276965587306847e-10, + 0.49259222901902222e-9, + -0.57479109221671054e-11, + -0.16331521876245402e-11, + + 0.0, + -0.51914749728946679, + 0.10793870175492009, + 0.056601774437946192, + -0.0086576695933049068, + -0.0021942003590150295, + 0.00026437703675251415, + 0.43729192716923728e-4, + -0.43388262868833412e-5, + -0.53049137594784273e-6, + 0.44700551042149104e-7, + 0.43264003773432392e-8, + -0.31664470012675611e-9, + -0.25122835305798086e-10, + 0.16215931083463106e-11, + + -0.40275939570255297, + -0.52181326018778115e-18, + 0.20137969785127645, + -0.017518715285659044, + -0.013352611033180267, + 0.0010359438491269923, + 0.00037218755651442075, + -0.24952041524263142e-4, + -0.57760876091040014e-5, + 0.33742922699801002e-6, + 0.57277913211048927e-7, + -0.29528827354673038e-8, + -0.39441693779923091e-9, + 0.18022594969949103e-10, + 0.18857204715831148e-11, + + 0.0, + 0.34026480655836815, + -0.030820651425593648, + -0.052988552867604362, + 0.0046310421459076305, + 0.0022574402290271133, + -0.00017518572899406692, + -0.46521090692503814e-4, + 0.31997869075739445e-5, + 0.57164888846826257e-6, + -0.35115366797673734e-7, + -0.46830399346222682e-8, + 0.25923658333924528e-9, + 0.27115172723816524e-10, + -0.13884165974276054e-11, + + 0.30011575252613256, + 0.2057050400962928e-17, + -0.15005787626306626, + 0.0071297376031137401, + 0.011742619737434781, + -0.00062605834520753437, + -0.00035093119053508375, + 0.17929701348313658e-4, + 0.56239343808321796e-5, + -0.26684224520542096e-6, + -0.56652615547124157e-7, + 0.24792586052774415e-8, + 0.39325985931918323e-9, + -0.15724313427150255e-10, + -0.19341803571391105e-11, + + 0.0, + -0.27145229992838192, + 0.015684124960953883, + 0.044033774963411685, + -0.0025093022272106884, + -0.0020603351551222082, + 0.00011243486789352708, + 0.44823035412848692e-4, + -0.22883910078014302e-5, + -0.56793781722802321e-6, + 0.26941566442661998e-7, + 0.47365215013159892e-8, + -0.20866089859212072e-9, + -0.27761981412381772e-10, + 0.11411583417182674e-11, + + -0.2497048770578432, + -0.21909546936929062e-17, + 0.12485243852892159, + -0.0040907858517003804, + -0.010102792347697843, + 0.00038536375944999447, + 0.0003185971148934128, + -0.12373899203877618e-4, + -0.53013953324799306e-5, + 0.20010876457654013e-6, + 0.54715979534900829e-7, + -0.19711317018282613e-8, + -0.38584018939012558e-9, + 0.13028557538648307e-10, + 0.19387251405422158e-11, + + 0.0, + 0.23245983136472478, + -0.0098570645138257917, + -0.03818600911162297, + 0.0016073972920896773, + 0.0018420433388659426, + -0.75813584809846931e-4, + -0.41592845395702554e-4, + 0.16506463478622605e-5, + 0.54254505636478441e-6, + -0.20558027910130633e-7, + -0.46196044646920421e-8, + 0.16630784845680672e-9, + 0.27483865275708142e-10, + -0.93846646239935553e-12, +END_TABLE() + + +DECLARE_TABLE(double, M64_J1, 8*15) + 0.0, + 0.5, + -0.12970309732986903e-17, + -0.062499999999999923, + -0.17942214325033243e-14, + 0.0026041666666885299, + -0.15964519165155314e-12, + -0.54253471466663886e-4, + -0.242857790709361e-11, + 0.67817384698301118e-6, + -0.86070068625189802e-11, + -0.56418387778447458e-8, + -0.73192849689297935e-11, + 0.37319822951004815e-10, + -0.11001445955275011e-11, + + 0.58186522428159638, + -0.56159765491837453e-17, + -0.20511071214777315, + 0.006058948324603733, + 0.013801769807954829, + -0.00037231709715965684, + -0.00039495907353545311, + 0.92029498173768214e-5, + 0.62672896236849497e-5, + -0.1267857801249798e-6, + -0.63255257619028979e-7, + 0.11251771403253868e-8, + 0.44176005585408683e-9, + -0.69798300547918846e-11, + -0.21578026548615529e-11, + + 0.0, + -0.402759395702553, + 0.052556145856977239, + 0.053410444132727687, + -0.0051797192456383855, + -0.0022331253392001435, + 0.00017466429070665996, + 0.46208701653337802e-4, + -0.30368632238776932e-5, + -0.57278166634453134e-6, + 0.32482189325657561e-7, + 0.47369084764612076e-8, + -0.23499460493506461e-9, + -0.28705938354850318e-10, + 0.44693128781201312e-12, + + -0.34612620185379152, + -0.17631593012980777e-17, + 0.16697453550109302, + -0.0096782685428780814, + -0.012099225779141488, + 0.00066540090064072656, + 0.00035413890079260022, + -0.17427203124603725e-4, + -0.56552935762375831e-5, + 0.24842942396474063e-6, + 0.57098949030140281e-7, + -0.22536110266152491e-8, + -0.39802896432910825e-9, + 0.14090328151677641e-10, + 0.19636717850506288e-11, + + 0.0, + 0.30011575252613256, + -0.021389212809341581, + -0.04697047894974129, + 0.0031302917260480798, + 0.0021055871432437381, + -0.00012550790955127199, + -0.44991475264757161e-4, + 0.24015807952585114e-5, + 0.56652684843934755e-6, + -0.27273424894801725e-7, + -0.47201704013422051e-8, + 0.20653028510455782e-9, + 0.27690106438474044e-10, + -0.11154568938183541e-11, + + 0.27329994163319985, + 0.2232142433641675e-17, + -0.13477468037992365, + 0.0051163403464879163, + 0.010631861751984214, + -0.00044874368373337155, + -0.00032680001851823873, + 0.13382555960237626e-4, + 0.53631771344886529e-5, + -0.20647195244065982e-6, + -0.54999812559703342e-7, + 0.19736935833650958e-8, + 0.38691574660208312e-9, + -0.12790599536440081e-10, + -0.19364854538966976e-11, + + 0.0, + -0.24970487705784317, + 0.012272357555101521, + 0.040411169390789711, + -0.001926818797260396, + -0.0019115826893325857, + 0.86617294531543399e-4, + 0.42411162505820529e-4, + -0.18009793753942718e-5, + -0.5471594365997978e-6, + 0.21683657796392875e-7, + 0.46297313740491134e-8, + -0.17085932625435942e-9, + -0.27035506268991826e-10, + 0.73146488801751189e-12, + + -0.23330441717143407, + -0.22662118296062933e-17, + 0.11580092244607786, + -0.0032489977328225844, + -0.0093725272060512657, + 0.00030361382116634888, + 0.00029804555532176523, + -0.98138185687649243e-5, + -0.50242299853933591e-5, + 0.16136260748150418e-6, + 0.5251960653430569e-7, + -0.16180019977389104e-8, + -0.37446742393781688e-9, + 0.10863405480283854e-10, + 0.19078934776878301e-11, +END_TABLE() + +DECLARE_TABLE(double, M64_Y0, 18*15) + -0.073804295108687225, + 0.17760601686906714, + -0.016073968025938426, + 0.00053860266686165496, + -0.94950052052215465e-5, + 0.10358476033628097e-6, + -0.76930799009029319e-9, + 0.41435657365127098e-11, + -0.1693271517935695e-13, + 0.54310606578547998e-16, + -0.14038708139145726e-18, + 0.29871591749670351e-21, + -0.53238579320936109e-24, + 0.80636887083404931e-27, + -0.10479788308161506e-29, + + -0.77912935353834307, + 2.2110954318911016, + -3.1481880142409648, + 6.7631541766023146, + -16.558846016561116, + 42.556164402735613, + -113.65090971911888, + 311.92221820936423, + -872.50902177512439, + 2461.0565691666882, + -6829.049205644454, + 17617.540310147784, + -38115.181270412403, + 58513.491703205172, + -45741.69055512617, + + -0.54179079742759428, + 1.64879305137253, + -1.6134395171403224, + 2.3901721546248332, + -4.2770404998133958, + 7.8857581113382368, + -15.060011460820601, + 29.549657999172217, + -59.136402510594911, + 119.95202976931475, + -243.64086705143111, + 478.7020767792245, + -836.74741023460869, + 1104.0427235801185, + -779.71306204835432, + + -0.35708307020027898, + 1.3315403043553127, + -1.0050498465490202, + 1.0750491956121098, + -1.5469100036757135, + 2.235635072477068, + -3.324194198035296, + 5.0776635871010325, + -7.9096546309462989, + 12.50166753906456, + -19.905699415239301, + 31.245221424718389, + -45.309925774701995, + 52.094004174782553, + -33.533831674941474, + + -0.2045648213118789, + 1.120816812372814, + -0.71285708925156112, + 0.55404402904516822, + -0.68086349391521071, + 0.81641946964915076, + -0.99376659920171963, + 1.2431212752135579, + -1.5855777667632761, + 2.0522491911004844, + -2.6819002952055626, + 3.4877724825589845, + -4.2917811335732653, + 4.3478499271457812, + -2.5645514824451464, + + 0.0, + 0.87942080249719477, + -0.49207893426297755, + 0.22055282848170949, + -0.22612171354423224, + 0.21894842697129336, + -0.20487719776562028, + 0.19733568623230481, + -0.1939501765143562, + 0.19337292001268456, + -0.19504328259403041, + 0.1989415973717781, + -0.20633673974538298, + 0.20488487879343473, + -0.12698771588648888, + + 0.088256964215676958, + 0.7812128213002887, + -0.43473489275797808, + 0.14491163091871858, + -0.1375568838608908, + 0.12453666860389533, + -0.10402567514600134, + 0.089474169159502648, + -0.078647603970442897, + 0.070036305115760506, + -0.062684214895833727, + 0.054972325513095258, + -0.043964628503220077, + 0.027371209537030947, + -0.0093703929219555162, + + 0.25821685159454078, + 0.58436403661500803, + -0.36285404044324346, + 0.061699235252148297, + -0.045739306782895844, + 0.040702353485939169, + -0.027255526573770462, + 0.018591111730641299, + -0.013104420664549169, + 0.0093397328068473626, + -0.0066469721051120698, + 0.0045586325249059059, + -0.0027647918918092109, + 0.0012569316613639002, + -0.00030394891460079893, + + 0.42891756089319696, + 0.33169442327191864, + -0.31651860299180319, + 0.030579837257061538, + -0.0047471912131737328, + 0.01054712074005649, + -0.0058778174555227628, + 0.0029188053177132331, + -0.0015824799060393402, + 0.00087461459619324866, + -0.00048386068841997002, + 0.00026310045468230596, + -0.00013160965333042817, + 0.51894745655900052e-4, + -0.11391844004684635e-4, + + 0.52078641240226751, + -0.20584037223089673e-17, + -0.2603932062011338, + 0.039504848583033348, + 0.0082143493513316977, + 0.00095956233382919533, + -0.001237092222826762, + 0.00037074882687906914, + -0.00013335661481505372, + 0.56621847806301764e-4, + -0.23586337096205168e-4, + 0.98050240371430491e-5, + -0.4128688513318286e-5, + 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+ 0.55865297153285871e-6, + -0.24419231590119171e-7, + -0.46840491648468389e-8, + 0.18834793161094204e-9, + 0.27682023845401218e-10, + -0.10382770024573064e-11, + + 0.25091253627781262, + 0.20958312999524093e-17, + -0.12423210535891706, + 0.0040099743760130122, + 0.0099565661817092748, + -0.00036590017033001253, + -0.0003122461086376193, + 0.11455332592119589e-4, + 0.51972538301279162e-5, + -0.18290468581196801e-6, + -0.53824305862244231e-7, + 0.1793715153149277e-8, + 0.38104401282521395e-9, + -0.11833239178630346e-10, + -0.19174467220108448e-11, + + 0.0, + -0.23246176601703874, + 0.0098927016182840341, + 0.037901635052955098, + -0.001577119502209961, + -0.0018169820021341525, + 0.72805910540142751e-4, + 0.40899999683340315e-4, + -0.15593759383351302e-5, + -0.53369324013028829e-6, + 0.1923660656790709e-7, + 0.45548312775946846e-8, + -0.15488624419048933e-9, + -0.27169020291555582e-10, + 0.87150492645533502e-12, +END_TABLE() + diff --git a/amd/device-libs/ocml/src/besselF_table.h b/amd/device-libs/ocml/src/besselF_table.h new file mode 100644 index 0000000000000..437568ab48a7a --- /dev/null +++ b/amd/device-libs/ocml/src/besselF_table.h @@ -0,0 +1,535 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +DECLARE_TABLE(float, M32_J0, 8*9) + 1.0f, + 0.44869526e-7f, + -0.250000678f, + 0.394978156e-5f, + 0.0156135085f, + 0.186404843e-4f, + -0.000451465494f, + 0.906744475e-5f, + 0.462022483e-5f, + + 0.0f, + -0.519147497f, + 0.107938702f, + 0.0566017522f, + -0.00865766565f, + -0.00219399941f, + 0.000264347633f, + 0.431469054e-4f, + -0.427168323e-5f, + + -0.402759396f, + -0.133988793e-8f, + 0.201379688f, + -0.0175186868f, + -0.0133525141f, + 0.00103577016f, + 0.000371882642f, + -0.245406847e-4f, + -0.544857844e-5f, + + 0.0f, + 0.340264805f, + -0.0308206513f, + -0.0529884948f, + 0.00463103756f, + 0.00225704943f, + -0.00017515902f, + -0.45676898e-4f, + 0.314800819e-5f, + + 0.300115752f, + 0.142140419e-8f, + -0.150057871f, + 0.00712970835f, + 0.0117425671f, + -0.00062589107f, + -0.00035076219f, + 0.175677152e-4f, + 0.542756342e-5f, + + 0.0f, + -0.271452299f, + 0.0156841249f, + 0.0440337286f, + -0.00250929967f, + -0.0020600007f, + 0.000112417278f, + 0.440465451e-4f, + -0.224955545e-5f, + + -0.249704877f, + -0.114020252e-8f, + 0.124852435f, + -0.00409076252f, + -0.0101027605f, + 0.000385232178f, + 0.000318490142f, + -0.120950437e-4f, + -0.516322204e-5f, + + 0.0f, + 0.232459831f, + -0.00985706448f, + -0.0381859695f, + 0.00160739566f, + 0.00184174666f, + -0.758016756e-4f, + -0.408780042e-4f, + 0.162275495e-5f, +END_TABLE() + +DECLARE_TABLE(float, M32_J1, 8*9) + 0.0f, + 0.5f, + 0.462571126e-8f, + -0.0625000886f, + 0.646901306e-6f, + 0.00260184106f, + 0.455472757e-5f, + -0.592206849e-4f, + 0.284771796e-5f, + + 0.581865224f, + -0.432727717e-10f, + -0.205110698f, + 0.00605894703f, + 0.0138016513f, + -0.000372288399f, + -0.000394630783f, + 0.908655709e-5f, + 0.594411649e-5f, + + 0.0f, + -0.402759391f, + 0.0525561452f, + 0.0534102785f, + -0.00517971268f, + -0.00223227521f, + 0.000174696729f, + 0.448728749e-4f, + -0.312619124e-5f, + + -0.346126202f, + -0.135982554e-8f, + 0.166974529f, + -0.00967824094f, + -0.0120991661f, + 0.000665244429f, + 0.000353951297f, + -0.170900235e-4f, + -0.544345571e-5f, + + 0.0f, + 0.300115751f, + -0.0213892127f, + -0.0469704276f, + 0.00313028838f, + 0.00210522941f, + -0.000125486758f, + -0.441893462e-4f, + 0.235877085e-5f, + + 0.273299942f, + 0.123871464e-8f, + -0.134774676f, + 0.00511631544f, + 0.0106318216f, + -0.000448605206f, + -0.000326670201f, + 0.130923618e-4f, + 0.520545213e-5f, + + 0.0f, + -0.249704872f, + 0.0122723573f, + 0.04041102f, + -0.00192680868f, + -0.00191084766f, + 0.865574383e-4f, + 0.412630035e-4f, + -0.171042992e-5f, + + -0.233304417f, + -0.101355681e-8f, + 0.11580092f, + -0.00324897742f, + -0.00937250256f, + 0.000303501923f, + 0.000297960941f, + -0.958268173e-5f, + -0.490863176e-5f, +END_TABLE() + +DECLARE_TABLE(float, M32_Y0, 18*9) + -0.0738042951f, + 0.177606017f, + -0.016073968f, + 0.000538602667f, + -0.949500521e-5f, + 0.10358476e-6f, + -0.769307974e-9f, + 0.414351772e-11f, + -0.168538199e-13f, + + -0.779129354f, + 2.21109539f, + -3.14817837f, + 6.76234763f, + -16.5245871f, + 41.721874f, + -101.297948f, + 197.994167f, + -213.204578f, + + -0.541790797f, + 1.64879305f, + -1.61343882f, + 2.39011447f, + -4.27463147f, + 7.8283496f, + -14.2356687f, + 22.309494f, + -20.7850723f, + + -0.35708307f, + 1.3315403f, + -1.00504975f, + 1.07504147f, + -1.54659225f, + 2.2281907f, + -3.21955386f, + 4.18656836f, + -3.43559538f, + + -0.204564821f, + 1.12081681f, + -0.712857069f, + 0.554042423f, + -0.680799155f, + 0.814950073f, + -0.973649903f, + 1.07700623f, + -0.787302821f, + + 0.0f, + 0.879420802f, + -0.492078934f, + 0.220553062f, + -0.226122006f, + 0.218871042f, + -0.204734177f, + 0.205007038f, + -0.209851389f, + + 0.0882569642f, + 0.781212821f, + -0.434734855f, + 0.144909902f, + -0.137517504f, + 0.124034055f, + -0.100221697f, + 0.072159059f, + -0.0322405804f, + + 0.258216852f, + 0.584364035f, + -0.362853954f, + 0.0616967017f, + -0.0457019916f, + 0.0403914876f, + -0.0257050488f, + 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-0.556989234e-5f, + + 0.0f, + 0.300097614f, + -0.0211752365f, + -0.0480240177f, + 0.00331834481f, + 0.00217561974f, + -0.000140580184f, + -0.451359559e-4f, + 0.265455576e-5f, + + 0.271459877f, + 0.139172743e-8f, + -0.135729934f, + 0.00526326684f, + 0.0108515634f, + -0.000483436056f, + -0.000335109802f, + 0.145606732e-4f, + 0.530954251e-5f, + + 0.0f, + -0.249701237f, + 0.0122135007f, + 0.0408203043f, + -0.00197714145f, + -0.00194569725f, + 0.914230753e-4f, + 0.425102172e-4f, + -0.190386676e-5f, + + -0.232461766f, + -0.985286365e-9f, + 0.11623088f, + -0.00329754703f, + -0.00947537951f, + 0.000315310068f, + 0.000302731128f, + -0.101595111e-4f, + -0.49823498e-5f, +END_TABLE() + +DECLARE_TABLE(float, M32_Y1, 18*9) + -0.196057091f, + 0.0543486882f, + -0.00295530534f, + 0.716426875e-4f, + -0.992674062e-6f, + 0.893187962e-8f, + -0.564802451e-10f, + 0.264946691e-12f, + -0.956040552e-15f, + + -1.47147239f, + 2.49842603f, + -4.705631f, + 9.97554229f, + -20.1713128f, + 40.1878477f, + -76.6812412f, + 123.027773f, + -115.903802f, + + -1.2171501f, + 1.6698932f, + -2.28529116f, + 4.02725834f, + -6.58555591f, + 10.5423814f, + -16.4151681f, + 22.3415253f, + -18.8343596f, + + -1.03759455f, + 1.24628662f, + -1.23436566f, + 1.89920078f, + -2.63550437f, + 3.50388357f, + -4.46415376f, + 4.77962593f, + -3.00258761f, + + -0.837397335f, + 0.930919184f, + -0.554175938f, + 0.733648813f, + -0.859400875f, + 0.908155864f, + -0.904818857f, + 0.731425234f, + -0.332223767f, + + -0.607228956f, + 0.737838338f, + -0.203493924f, + 0.210066093f, + -0.230917988f, + 0.188616636f, + -0.14625808f, + 0.0958024404f, + -0.0364996384f, + + -0.391867956f, + 0.650927429f, + -0.100177392f, + 0.0422373453f, + -0.07235139f, + 0.0493095772f, + -0.0299278561f, + 0.0165691516f, + -0.00564529733f, + + -0.197513707f, + 0.593769812f, + -0.0913166067f, + -0.013725346f, + -0.0252004653f, + 0.0176426751f, + -0.00832470911f, + 0.00410178601f, + -0.00142662074f, + + 0.0f, + 0.520786412f, + -0.118514546f, + -0.0328573972f, + -0.00479781174f, + 0.00742247989f, + -0.00259521656f, + 0.00107430961f, + -0.000512579875f, + + 0.0584489381f, + 0.492108098f, + -0.130161305f, + -0.0341572041f, + -0.000981824109f, + 0.00587622283f, + -0.00185575707f, + 0.000582281731f, + -0.000148343917f, + + 0.240364643f, + 0.364553919f, + -0.170769591f, + -0.0276077249f, + 0.00766230439f, + 0.00273966927f, + -0.000828295737f, + 0.000137588785f, + -0.305187593e-4f, + + 0.416729928f, + -0.258296385e-9f, + -0.193004092f, + 0.0146874353f, + 0.0120957914f, + -0.000525144004f, + -0.000426716299f, + 0.352388331e-4f, + 0.877397631e-6f, + + 0.367444533f, + -0.182322102f, + -0.151633779f, + 0.0373228744f, + 0.00917855673f, + -0.00164468944f, + -0.000284979934f, + 0.451783718e-4f, + 0.198340769e-5f, + + 0.0f, + -0.340318045f, + 0.0313386774f, + 0.0509479111f, + -0.00416011363f, + -0.00216575933f, + 0.000146604317f, + 0.458142122e-4f, + -0.282657316e-5f, + + -0.30317374f, + -0.139307478e-8f, + 0.148440893f, + -0.00682601599f, + -0.0113866644f, + 0.000555890828f, + 0.000340287228f, + -0.150871178e-4f, + -0.536125411e-5f, + + 0.0f, + 0.271459876f, + -0.0157898843f, + -0.0434063812f, + 0.00241795425f, + 0.00201116367f, + -0.000104184764f, + -0.430443521e-4f, + 0.204582146e-5f, + + 0.250912536f, + 0.109595535e-8f, + -0.124232101f, + 0.00400995233f, + 0.009956529f, + -0.000365777587f, + -0.000312125102f, + 0.111983746e-4f, + 0.504825687e-5f, + + 0.0f, + -0.232461765f, + 0.00989270158f, + 0.037901591f, + -0.0015771177f, + -0.00181666561f, + 0.72793478e-4f, + 0.40167952e-4f, + -0.153180005e-5f, +END_TABLE() + diff --git a/amd/device-libs/ocml/src/bp0D.cl b/amd/device-libs/ocml/src/bp0D.cl new file mode 100644 index 0000000000000..9014ae9e23c54 --- /dev/null +++ b/amd/device-libs/ocml/src/bp0D.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_PRIVATE(bp0)(double t) +{ + return + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + -0x1.91f780a4a989bp+28, 0x1.52a41923b70a7p+24), -0x1.40a5e31612a8dp+19), 0x1.0c9a0cbe3b3b8p+14), + -0x1.0af76167fe583p+9), 0x1.778ea61b94139p+4), -0x1.a3581d1a82662p+0), 0x1.ad33330a1daf2p-3), + -0x1.0aaaaaaaa7909p-4), 0x1.0000000000000p-3); +} + diff --git a/amd/device-libs/ocml/src/bp0F.cl b/amd/device-libs/ocml/src/bp0F.cl new file mode 100644 index 0000000000000..c0c27a1f066fe --- /dev/null +++ b/amd/device-libs/ocml/src/bp0F.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_PRIVATE(bp0)(float t) +{ + return + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.5ec5e6p+0f, 0x1.aafb08p-3f), -0x1.0aa926p-4f), 0x1.000000p-3f); +} + diff --git a/amd/device-libs/ocml/src/bp1D.cl b/amd/device-libs/ocml/src/bp1D.cl new file mode 100644 index 0000000000000..c9239c9594d6a --- /dev/null +++ b/amd/device-libs/ocml/src/bp1D.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_PRIVATE(bp1)(double t) +{ + return + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + 0x1.c22f653d3a76ep+28, -0x1.80a4d95ed3e8ep+24), 0x1.72f1d1f8cdd76p+19), -0x1.3ea4e96460ad7p+14), + 0x1.488dd98d9ab3ap+9), -0x1.e9ed612fa3b38p+4), 0x1.2f484fcab9ddap+1), -0x1.7bccccad443c0p-2), + 0x1.4ffffffffcbfap-3), -0x1.8000000000000p-2); +} + diff --git a/amd/device-libs/ocml/src/bp1F.cl b/amd/device-libs/ocml/src/bp1F.cl new file mode 100644 index 0000000000000..18569cb6f32e9 --- /dev/null +++ b/amd/device-libs/ocml/src/bp1F.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_PRIVATE(bp1)(float t) +{ + return + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.0214cep+1f, -0x1.7a54cap-2f), 0x1.4ffefep-3f), -0x1.800000p-2f); +} + diff --git a/amd/device-libs/ocml/src/builtins.h b/amd/device-libs/ocml/src/builtins.h new file mode 100644 index 0000000000000..c5f4ca94ab9dc --- /dev/null +++ b/amd/device-libs/ocml/src/builtins.h @@ -0,0 +1,317 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +// Bitcasting + +#define AS_SHORT(X) __builtin_astype(X, short) +#define AS_SHORT2(X) __builtin_astype(X, short2) +#define AS_USHORT(X) __builtin_astype(X, ushort) +#define AS_USHORT2(X) __builtin_astype(X, ushort2) +#define AS_INT(X) __builtin_astype(X, int) +#define AS_INT2(X) __builtin_astype(X, int2) +#define AS_UINT(X) __builtin_astype(X, uint) +#define AS_UINT2(X) __builtin_astype(X, uint2) +#define AS_LONG(X) __builtin_astype(X, long) +#define AS_ULONG(X) __builtin_astype(X, ulong) +#define AS_DOUBLE(X) __builtin_astype(X, double) +#define AS_FLOAT(X) __builtin_astype(X, float) +#define AS_HALF(X) __builtin_astype(X, half) +#define AS_HALF2(X) __builtin_astype(X, half2) + +// Class mask bits +#define CLASS_SNAN __FPCLASS_SNAN +#define CLASS_QNAN __FPCLASS_QNAN +#define CLASS_NINF __FPCLASS_NEGINF +#define CLASS_NNOR __FPCLASS_NEGNORMAL +#define CLASS_NSUB __FPCLASS_NEGSUBNORMAL +#define CLASS_NZER __FPCLASS_NEGZERO +#define CLASS_PZER __FPCLASS_POSZERO +#define CLASS_PSUB __FPCLASS_POSSUBNORMAL +#define CLASS_PNOR __FPCLASS_POSNORMAL +#define CLASS_PINF __FPCLASS_POSINF + +#include "irif.h" + +#define BUILTIN_ABS_F32 __builtin_fabsf +#define BUILTIN_ABS_F64 __builtin_fabs +#define BUILTIN_ABS_F16 __builtin_fabsf16 +#define BUILTIN_ABS_2F16 __builtin_elementwise_abs + +#define BUILTIN_BITALIGN_B32 __builtin_amdgcn_alignbit + +#define BUILTIN_CEIL_F32 __builtin_ceilf +#define BUILTIN_CEIL_F64 __builtin_ceil +#define BUILTIN_CEIL_F16 __builtin_ceilf16 +#define BUILTIN_CEIL_2F16 __builtin_elementwise_ceil + +#define BUILTIN_CLASS_F32 __builtin_isfpclass +#define BUILTIN_CLASS_F64 __builtin_isfpclass +#define BUILTIN_CLASS_F16 __builtin_isfpclass + +#define BUILTIN_ISNAN_F32(x) __builtin_isnan(x) +#define BUILTIN_ISNAN_F64(x) __builtin_isnan(x) +#define BUILTIN_ISNAN_F16(x) __builtin_isnan(x) + +#define BUILTIN_ISUNORDERED_F32(x, y) __builtin_isunordered(x, y) +#define BUILTIN_ISUNORDERED_F64(x, y) __builtin_isunordered(x, y) +#define BUILTIN_ISUNORDERED_F16(x, y) __builtin_isunordered(x, y) + +#define BUILTIN_ISINF_F32(x) __builtin_isinf(x) +#define BUILTIN_ISINF_F64(x) __builtin_isinf(x) +#define BUILTIN_ISINF_F16(x) __builtin_isinf(x) + +#define BUILTIN_ISFINITE_F32(x) __builtin_isfinite(x) +#define BUILTIN_ISFINITE_F64(x) __builtin_isfinite(x) +#define BUILTIN_ISFINITE_F16(x) __builtin_isfinite(x) + +#define BUILTIN_ISSUBNORMAL_F32(x) __builtin_isfpclass(x, CLASS_NSUB|CLASS_PSUB) +#define BUILTIN_ISSUBNORMAL_F64(x) __builtin_isfpclass(x, CLASS_NSUB|CLASS_PSUB) +#define BUILTIN_ISSUBNORMAL_F16(x) __builtin_isfpclass(x, CLASS_NSUB|CLASS_PSUB) + +#define BUILTIN_ISZERO_F32(x) __builtin_isfpclass(x, CLASS_NZER|CLASS_PZER) +#define BUILTIN_ISZERO_F64(x) __builtin_isfpclass(x, CLASS_NZER|CLASS_PZER) +#define BUILTIN_ISZERO_F16(x) __builtin_isfpclass(x, CLASS_NZER|CLASS_PZER) + +#define BUILTIN_ISNORMAL_F32(x) __builtin_isnormal(x) +#define BUILTIN_ISNORMAL_F64(x) __builtin_isnormal(x) +#define BUILTIN_ISNORMAL_F16(x) __builtin_isnormal(x) + +#define BUILTIN_COPYSIGN_F32 __builtin_copysignf +#define BUILTIN_COPYSIGN_F64 __builtin_copysign +#define BUILTIN_COPYSIGN_F16 __builtin_copysignf16 +#define BUILTIN_COPYSIGN_2F16 __builtin_elementwise_copysign + +#define BUILTIN_FLOOR_F32 __builtin_floorf +#define BUILTIN_FLOOR_F64 __builtin_floor +#define BUILTIN_FLOOR_F16 __builtin_floorf16 +#define BUILTIN_FLOOR_2F16 __builtin_elementwise_floor + +// These will codegen to v_fract_{f16|f32|f64} as appropriate. +#define BUILTIN_FRACTION_F32(X) ({ \ + const float _x = X; \ + const float _floor_x = BUILTIN_FLOOR_F32(_x); \ + float _f = BUILTIN_MIN_F32(_x - _floor_x, 0x1.fffffep-1f); \ + if (!FINITE_ONLY_OPT()) { \ + _f = BUILTIN_ISNAN_F32(_x) ? _x : _f; \ + _f = BUILTIN_ISINF_F32(_x) ? 0.0f : _f; \ + } \ + _f; \ +}) + +#define BUILTIN_FRACTION_F64(X) ({ \ + const double _x = X; \ + const double _floor_x = BUILTIN_FLOOR_F64(_x); \ + double _f = BUILTIN_MIN_F64(_x - _floor_x, 0x1.fffffffffffffp-1); \ + if (!FINITE_ONLY_OPT()) { \ + _f = BUILTIN_ISNAN_F64(_x) ? _x : _f; \ + _f = BUILTIN_ISINF_F64(_x) ? 0.0 : _f; \ + } \ + _f; \ +}) + +#define BUILTIN_FRACTION_F16(X) ({ \ + const half _x = X; \ + const half _floor_x = BUILTIN_FLOOR_F16(_x); \ + half _f = BUILTIN_MIN_F16(_x - _floor_x, 0x1.ffcp-1h); \ + if (!FINITE_ONLY_OPT()) { \ + _f = BUILTIN_ISNAN_F16(_x) ? _x : _f; \ + _f = BUILTIN_ISINF_F16(_x) ? 0.0h : _f; \ + } \ + _f; \ +}) + +#define BUILTIN_MAD_U32(A,B,C) ((A)*(B)+(C)) + +#define BUILTIN_MAX_F32 __builtin_fmaxf +#define BUILTIN_MAX_F64 __builtin_fmax +#define BUILTIN_MAX_F16 __builtin_fmaxf16 +#define BUILTIN_MAX_2F16 __builtin_elementwise_max + +#define BUILTIN_MAX_S32(A,B) ((A) < (B) ? (B) : (A)) +#define BUILTIN_MAX_U32(A,B) ((A) < (B) ? (B) : (A)) + +#define BUILTIN_MIN_F32 __builtin_fminf +#define BUILTIN_MIN_F64 __builtin_fmin +#define BUILTIN_MIN_F16 __builtin_fminf16 +#define BUILTIN_MIN_2F16 __builtin_elementwise_min + +#define BUILTIN_MIN_S32(A,B) ((A) < (B) ? (A) : (B)) +#define BUILTIN_MIN_U32(A,B) ((A) < (B) ? (A) : (B)) + +#define BUILTIN_CANONICALIZE_F32(X) __builtin_canonicalizef(X) +#define BUILTIN_CANONICALIZE_F64(X) __builtin_canonicalize(X) +#define BUILTIN_CANONICALIZE_F16(X) __builtin_canonicalizef16(X) + +#define BUILTIN_MULHI_U32(A,B) (((ulong)(A) * (ulong)(B)) >> 32) + +#define BUILTIN_AMDGPU_COS_F32 __builtin_amdgcn_cosf + +#define BUILTIN_AMDGPU_EXP2_F32 __builtin_amdgcn_exp2f +#define BUILTIN_EXP2_F32 __builtin_exp2f +#define BUILTIN_EXP2_F16 __builtin_exp2f16 + +#define BUILTIN_EXP_F32 __builtin_expf + +#define BUILTIN_AMDGPU_LOG2_F32 __builtin_amdgcn_logf +#define BUILTIN_LOG2_F32 __builtin_log2f +#define BUILTIN_LOG2_F16 __builtin_log2f16 + +#define BUILTIN_LOG_F32 __builtin_logf +#define BUILTIN_LOG10_F32 __builtin_log10f + +#define BUILTIN_AMDGPU_RCP_F32 __builtin_amdgcn_rcpf +#define BUILTIN_AMDGPU_RCP_F64 __builtin_amdgcn_rcp +#define BUILTIN_RCP_F16(X) (1.0h / (X)) + +#define BUILTIN_AMDGPU_RSQRT_F32 __builtin_amdgcn_rsqf +#define BUILTIN_AMDGPU_RSQRT_F64 __builtin_amdgcn_rsq + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +static inline half __ocml_priv_rsqrt_f16(half x) { + #pragma clang fp contract(fast) + return 1.0h / __builtin_sqrtf16(x); +} +#pragma OPENCL EXTENSION cl_khr_fp16 : disable + +#define BUILTIN_RSQRT_F16(X) __ocml_priv_rsqrt_f16(X) + +#define BUILTIN_AMDGPU_SIN_F32 __builtin_amdgcn_sinf + +#define BUILTIN_RINT_F32 __builtin_rintf +#define BUILTIN_RINT_F64 __builtin_rint +#define BUILTIN_RINT_F16 __builtin_rintf16 +#define BUILTIN_RINT_2F16 __builtin_elementwise_rint + +#define BUILTIN_SQRT_F32(X) __builtin_sqrtf(X) +#define BUILTIN_SQRT_F64(X) __builtin_sqrt(X) +#define BUILTIN_SQRT_F16(X) __builtin_sqrtf16(X) + +#define BUILTIN_AMDGPU_SQRT_F32(X) __builtin_amdgcn_sqrtf(X) + +#define BUILTIN_TRUNC_F32 __builtin_truncf +#define BUILTIN_TRUNC_F64 __builtin_trunc +#define BUILTIN_TRUNC_F16 __builtin_truncf16 +#define BUILTIN_TRUNC_2F16 __builtin_elementwise_trunc + +#define BUILTIN_ROUND_F32 __builtin_roundf +#define BUILTIN_ROUND_F64 __builtin_round +#define BUILTIN_ROUND_F16 __builtin_roundf16 +#define BUILTIN_ROUND_2F16 __builtin_elementwise_round + +#define BUILTIN_DIV_F32(X,Y) ({ \ + float _div_x = X; \ + float _div_y = Y; \ + float _div_ret = _div_x / _div_y; \ + _div_ret; \ +}) + +#define BUILTIN_DIV_F64(X,Y) ({ \ + double _div_x = X; \ + double _div_y = Y; \ + double _div_ret = _div_x / _div_y; \ + _div_ret; \ +}) + +#define BUILTIN_DIV_F16(X,Y) ({ \ + half _div_x = X; \ + half _div_y = Y; \ + half _div_ret = _div_x / _div_y; \ + _div_ret; \ +}) + +#define BUILTIN_FMA_F32 __builtin_fmaf +#define BUILTIN_FMA_2F32 __builtin_elementwise_fma +#define BUILTIN_FMA_F64 __builtin_fma +#define BUILTIN_FMA_F16 __builtin_fmaf16 +#define BUILTIN_FMA_2F16 __builtin_elementwise_fma + +#define BUILTIN_FLDEXP_F32 __builtin_ldexpf +#define BUILTIN_FLDEXP_F64 __builtin_ldexp +#define BUILTIN_FLDEXP_F16 __builtin_ldexpf16 + +#define BUILTIN_FREXP_F32 __builtin_frexpf +#define BUILTIN_FREXP_F64 __builtin_frexp +#define BUILTIN_FREXP_F16 __builtin_frexpf16 + +#define BUILTIN_FREXP_EXP_F32(X) \ + ({ \ + int _exp; \ + __builtin_frexp(X, &_exp); \ + _exp; \ + }) + +#define BUILTIN_FREXP_EXP_F64(X) \ + ({ \ + int _exp; \ + __builtin_frexp(X, &_exp); \ + _exp; \ + }) + +#define BUILTIN_FREXP_EXP_F16(X) \ + ({ \ + int _exp; \ + __builtin_frexpf16(X, &_exp); \ + _exp; \ + }) + +#define BUILTIN_FREXP_MANT_F32(X) \ + ({ \ + int _exp; \ + __builtin_frexpf(X, &_exp); \ + }) + +#define BUILTIN_FREXP_MANT_F64(X) \ + ({ \ + int _exp; \ + __builtin_frexp(X, &_exp); \ + }) + +#define BUILTIN_FREXP_MANT_F16(X) \ + ({ \ + int _exp; \ + __builtin_frexpf16(X, &_exp); \ + }) + +#define BUILTIN_CMAX_F32 __builtin_fmaxf +#define BUILTIN_CMAX_F64 __builtin_fmax +#define BUILTIN_CMAX_F16 __builtin_fmaxf16 +#define BUILTIN_CMAX_2F16 __builtin_elementwise_max + +#define BUILTIN_CMIN_F32 __builtin_fminf +#define BUILTIN_CMIN_F64 __builtin_fmin +#define BUILTIN_CMIN_F16 __builtin_fminf16 +#define BUILTIN_CMIN_2F16 __builtin_elementwise_min + +#define BUILTIN_AMDGPU_TRIG_PREOP_F64 __builtin_amdgcn_trig_preop + +#define BUILTIN_MAD_F32 __ocml_fmuladd_f32 +#define BUILTIN_MAD_2F32 __ocml_fmuladd_2f32 +#define BUILTIN_MAD_F64 __ocml_fmuladd_f64 +#define BUILTIN_MAD_F16 __ocml_fmuladd_f16 +#define BUILTIN_MAD_2F16 __ocml_fmuladd_2f16 + +// HW has ISA for max3, median3, and min3, median3 can be used to clamp +#define BUILTIN_CLAMP_S32(X,L,H) ({ \ + int _clamp_x = X; \ + int _clamp_l = L; \ + int _clamp_h = H; \ + int _clamp_r = _clamp_x > _clamp_l ? _clamp_x : _clamp_l; \ + _clamp_r = _clamp_r < _clamp_h ? _clamp_r : _clamp_h; \ + _clamp_r; \ +}) + +#define BUILTIN_CLAMP_F32(X,L,H) __builtin_amdgcn_fmed3f(X,L,H) + +#define ROUND_RTE 0 +#define ROUND_RTP 1 +#define ROUND_RTN 2 +#define ROUND_RTZ 3 + +#define BUILTIN_GETROUND_F32() __builtin_amdgcn_s_getreg((1 << 0) | (0 << 6) | ((2-1) << 11)) +#define BUILTIN_SETROUND_F32(X) __builtin_amdgcn_s_setreg((1 << 0) | (0 << 6) | ((2-1) << 11), X) +#define BUILTIN_GETROUND_F16F64() __builtin_amdgcn_s_getreg((1 << 0) | (2 << 6) | ((2-1) << 11)) +#define BUILTIN_SETROUND_F16F64(X) __builtin_amdgcn_s_setreg((1 << 0) | (2 << 6) | ((2-1) << 11), X) diff --git a/amd/device-libs/ocml/src/cabsD.cl b/amd/device-libs/ocml/src/cabsD.cl new file mode 100644 index 0000000000000..9a6965cbe4979 --- /dev/null +++ b/amd/device-libs/ocml/src/cabsD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(cabs)(double2 x) +{ + return MATH_MANGLE(hypot)(x.s0, x.s1); +} + diff --git a/amd/device-libs/ocml/src/cabsF.cl b/amd/device-libs/ocml/src/cabsF.cl new file mode 100644 index 0000000000000..62e8bf911f365 --- /dev/null +++ b/amd/device-libs/ocml/src/cabsF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(cabs)(float2 x) +{ + return MATH_MANGLE(hypot)(x.s0, x.s1); +} + diff --git a/amd/device-libs/ocml/src/cacosD.cl b/amd/device-libs/ocml/src/cacosD.cl new file mode 100644 index 0000000000000..ac468011bd038 --- /dev/null +++ b/amd/device-libs/ocml/src/cacosD.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double2 +MATH_MANGLE(cacos)(double2 z) +{ + double2 a = MATH_MANGLE(cacosh)(z); + bool b = AS_INT2(z.y).hi < 0; + return (double2)(b ? -a.y : a.y, b ? a.x : -a.x); +} + diff --git a/amd/device-libs/ocml/src/cacosF.cl b/amd/device-libs/ocml/src/cacosF.cl new file mode 100644 index 0000000000000..e20b7d90e0167 --- /dev/null +++ b/amd/device-libs/ocml/src/cacosF.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE(cacos)(float2 z) +{ + float2 a = MATH_MANGLE(cacosh)(z); + bool b = AS_INT(z.y) < 0; + return (float2)(b ? -a.y : a.y, b ? a.x : -a.x); +} + diff --git a/amd/device-libs/ocml/src/cacoshD.cl b/amd/device-libs/ocml/src/cacoshD.cl new file mode 100644 index 0000000000000..8300169d67e79 --- /dev/null +++ b/amd/device-libs/ocml/src/cacoshD.cl @@ -0,0 +1,64 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double4 MATH_PRIVATE(epcsqrtep)(double4 z); +extern CONSTATTR double MATH_PRIVATE(lnep)(double2 a, int ea); + +CONSTATTR double2 +MATH_MANGLE(cacosh)(double2 z) +{ + double x = BUILTIN_ABS_F64(z.x); + double y = BUILTIN_ABS_F64(z.y); + + double2 l2, t; + int e = 0; + bool b = true; + + if (x < 0x1.0p+54 && y < 0x1.0p+54) { + if (x >= 1.0 || y >= 0x1.0p-53 || y > (1.0 - x)*0x1.0p-26) { + double4 z2p1 = (double4)(add(mul(add(y,x), sub(y,x)), 1.0), mul(y,x)*2.0); + double4 rz2m1 = MATH_PRIVATE(epcsqrtep)(z2p1); + rz2m1 = (double4)(csgn(rz2m1.hi, (double2)z.x), csgn(rz2m1.lo, (double2)z.y)); + double4 s = (double4)(add(rz2m1.lo, z.x), add(rz2m1.hi, z.y)); + l2 = add(sqr(s.lo), sqr(s.hi)); + t = (double2)(s.s1, z.y == 0.0 ? z.y : s.s3); + } else { + b = false; + double r = MATH_FAST_SQRT(BUILTIN_FMA_F64(-x, x, 1.0)); + l2 = con(MATH_DIV(y, r), 0.0); + t = (double2)(z.x, BUILTIN_COPYSIGN_F64(r, z.y)); + } + } else { + e = BUILTIN_FREXP_EXP_F64(BUILTIN_MAX_F64(x,y)); + x = BUILTIN_FLDEXP_F64(x, -e); + y = BUILTIN_FLDEXP_F64(y, -e); + l2 = add(sqr(x), sqr(y)); + e = 2*e + 2; + t = z; + } + + double rr; + if (b) { + rr = 0.5 * MATH_PRIVATE(lnep)(l2, e); + } else { + rr = l2.hi; + } + + double ri = MATH_MANGLE(atan2)(t.y, t.x); + + if (!FINITE_ONLY_OPT()) { + rr = (BUILTIN_ISINF_F64(z.x) | BUILTIN_ISINF_F64(z.y)) ? PINF_F64 : rr; + } + + return (double2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/cacoshF.cl b/amd/device-libs/ocml/src/cacoshF.cl new file mode 100644 index 0000000000000..429f58a8b93fc --- /dev/null +++ b/amd/device-libs/ocml/src/cacoshF.cl @@ -0,0 +1,64 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float4 MATH_PRIVATE(epcsqrtep)(float4 z); +extern CONSTATTR float MATH_PRIVATE(lnep)(float2 a, int ea); + +CONSTATTR float2 +MATH_MANGLE(cacosh)(float2 z) +{ + float x = BUILTIN_ABS_F32(z.x); + float y = BUILTIN_ABS_F32(z.y); + + float2 l2, t; + int e = 0; + bool b = true; + + if (x < 0x1.0p+25f && y < 0x1.0p+25f) { + if (x >= 1.0f || y >= 0x1.0p-24f || y > (1.0f - x)*0x1.0p-12f) { + float4 z2p1 = (float4)(add(mul(add(y,x), sub(y,x)), 1.0f), mul(y,x)*2.0f); + float4 rz2m1 = MATH_PRIVATE(epcsqrtep)(z2p1); + rz2m1 = (float4)(csgn(rz2m1.hi, (float2)z.x), csgn(rz2m1.lo, (float2)z.y)); + float4 s = (float4)(add(rz2m1.lo, z.x), add(rz2m1.hi, z.y)); + l2 = add(sqr(s.lo), sqr(s.hi)); + t = (float2)(s.s1, z.y == 0.0f ? z.y : s.s3); + } else { + b = false; + float r = MATH_SQRT(BUILTIN_FMA_F32(-x, x, 1.0f)); + l2 = con(MATH_DIV(y, r), 0.0f); + t = (float2)(z.x, BUILTIN_COPYSIGN_F32(r, z.y)); + } + } else { + e = BUILTIN_FREXP_EXP_F32(AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(x), AS_UINT(y)))); + x = BUILTIN_FLDEXP_F32(x, -e); + y = BUILTIN_FLDEXP_F32(y, -e); + l2 = add(sqr(x), sqr(y)); + e = 2*e + 2; + t = z; + } + + float rr; + if (b) { + rr = 0.5f * MATH_PRIVATE(lnep)(l2, e); + } else { + rr = l2.hi; + } + + float ri = MATH_MANGLE(atan2)(t.y, t.x); + + if (!FINITE_ONLY_OPT()) { + rr = (BUILTIN_ISINF_F32(z.x) | BUILTIN_ISINF_F32(z.y)) ? PINF_F32 : rr; + } + + return (float2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/casinD.cl b/amd/device-libs/ocml/src/casinD.cl new file mode 100644 index 0000000000000..d0bafe12b17a0 --- /dev/null +++ b/amd/device-libs/ocml/src/casinD.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double2 +MATH_MANGLE(casin)(double2 z) +{ + double2 a = MATH_MANGLE(casinh)((double2)(-z.y, z.x)); + return (double2)(a.y, -a.x); +} + diff --git a/amd/device-libs/ocml/src/casinF.cl b/amd/device-libs/ocml/src/casinF.cl new file mode 100644 index 0000000000000..1189c59956e93 --- /dev/null +++ b/amd/device-libs/ocml/src/casinF.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE(casin)(float2 z) +{ + float2 a = MATH_MANGLE(casinh)((float2)(-z.y, z.x)); + return (float2)(a.y, -a.x); +} + diff --git a/amd/device-libs/ocml/src/casinhD.cl b/amd/device-libs/ocml/src/casinhD.cl new file mode 100644 index 0000000000000..b90b3ee7a5adf --- /dev/null +++ b/amd/device-libs/ocml/src/casinhD.cl @@ -0,0 +1,65 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double4 MATH_PRIVATE(epcsqrtep)(double4 z); +extern CONSTATTR double MATH_PRIVATE(lnep)(double2 a, int ea); + +CONSTATTR double2 +MATH_MANGLE(casinh)(double2 z) +{ + double x = BUILTIN_ABS_F64(z.x); + double y = BUILTIN_ABS_F64(z.y); + + double2 l2, t; + int e = 0; + bool b = true; + + if (x < 0x1.0p+54 && y < 0x1.0p+54) { + if (y >= 1.0 || x >= 0x1.0p-53 || x > (1.0 - y)*0x1.0p-26f) { + double4 z2p1 = (double4)(add(mul(add(x,y), sub(x,y)), 1.0), mul(y,x)*2.0); + double4 rz2p1 = MATH_PRIVATE(epcsqrtep)(z2p1); + double4 s = (double4)(add(rz2p1.lo, x), add(rz2p1.hi, y)); + l2 = add(sqr(s.lo), sqr(s.hi)); + t = (double2)(s.s1, s.s3); + } else { + b = false; + double r = MATH_SQRT(BUILTIN_FMA_F64(-y, y, 1.0)); + l2 = con(MATH_DIV(x, r), 0.0); + t = (double2)(r, y); + } + } else { + t = (double2)(x, y); + e = BUILTIN_FREXP_EXP_F64(BUILTIN_MAX_F64(x, y)); + x = BUILTIN_FLDEXP_F64(x, -e); + y = BUILTIN_FLDEXP_F64(y, -e); + l2 = add(sqr(x), sqr(y)); + e = 2*e + 2; + } + + double rr; + if (b) { + rr = 0.5 * MATH_PRIVATE(lnep)(l2, e); + } else { + rr = l2.hi; + } + + rr = BUILTIN_COPYSIGN_F64(rr, z.x); + double ri = BUILTIN_COPYSIGN_F64(MATH_MANGLE(atan2)(t.y, t.x), z.y); + + if (!FINITE_ONLY_OPT()) { + double i = BUILTIN_COPYSIGN_F64(PINF_F64, z.x); + rr = (BUILTIN_ISINF_F64(z.x) | BUILTIN_ISINF_F64(z.y)) ? i : rr; + } + + return (double2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/casinhF.cl b/amd/device-libs/ocml/src/casinhF.cl new file mode 100644 index 0000000000000..71d8dddd14c2b --- /dev/null +++ b/amd/device-libs/ocml/src/casinhF.cl @@ -0,0 +1,65 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float4 MATH_PRIVATE(epcsqrtep)(float4 z); +extern CONSTATTR float MATH_PRIVATE(lnep)(float2 a, int ea); + +CONSTATTR float2 +MATH_MANGLE(casinh)(float2 z) +{ + float x = BUILTIN_ABS_F32(z.x); + float y = BUILTIN_ABS_F32(z.y); + + float2 l2, t; + int e = 0; + bool b = true; + + if (x < 0x1.0p+25f && y < 0x1.0p+25f) { + if (y >= 1.0f || x >= 0x1.0p-24f || x > (1.0f - y)*0x1.0p-12f) { + float4 z2p1 = (float4)(add(mul(add(x,y), sub(x,y)), 1.0f), mul(y,x)*2.0f); + float4 rz2p1 = MATH_PRIVATE(epcsqrtep)(z2p1); + float4 s = (float4)(add(rz2p1.lo, x), add(rz2p1.hi, y)); + l2 = add(sqr(s.lo), sqr(s.hi)); + t = (float2)(s.s1, s.s3); + } else { + b = false; + float r = MATH_SQRT(BUILTIN_FMA_F32(-y, y, 1.0f)); + l2 = con(MATH_DIV(x, r), 0.0f); + t = (float2)(r, y); + } + } else { + t = (float2)(x, y); + e = BUILTIN_FREXP_EXP_F32(AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(x), AS_UINT(y)))); + x = BUILTIN_FLDEXP_F32(x, -e); + y = BUILTIN_FLDEXP_F32(y, -e); + l2 = add(sqr(x), sqr(y)); + e = 2*e + 2; + } + + float rr; + if (b) { + rr = 0.5f * MATH_PRIVATE(lnep)(l2, e); + } else { + rr = l2.hi; + } + + rr = BUILTIN_COPYSIGN_F32(rr, z.x); + float ri = BUILTIN_COPYSIGN_F32(MATH_MANGLE(atan2)(t.y, t.x), z.y); + + if (!FINITE_ONLY_OPT()) { + float i = BUILTIN_COPYSIGN_F32(PINF_F32, z.x); + rr = (BUILTIN_ISINF_F32(z.x) | BUILTIN_ISINF_F32(z.y)) ? i : rr; + } + + return (float2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/catanD.cl b/amd/device-libs/ocml/src/catanD.cl new file mode 100644 index 0000000000000..0c3cf43c63723 --- /dev/null +++ b/amd/device-libs/ocml/src/catanD.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double2 +MATH_MANGLE(catan)(double2 z) +{ + double2 a = MATH_MANGLE(catanh)((double2)(-z.y, z.x)); + return (double2)(a.y, -a.x); +} + diff --git a/amd/device-libs/ocml/src/catanF.cl b/amd/device-libs/ocml/src/catanF.cl new file mode 100644 index 0000000000000..55715a5917972 --- /dev/null +++ b/amd/device-libs/ocml/src/catanF.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE(catan)(float2 z) +{ + float2 a = MATH_MANGLE(catanh)((float2)(-z.y, z.x)); + return (float2)(a.y, -a.x); +} + diff --git a/amd/device-libs/ocml/src/catanhD.cl b/amd/device-libs/ocml/src/catanhD.cl new file mode 100644 index 0000000000000..c168040954c59 --- /dev/null +++ b/amd/device-libs/ocml/src/catanhD.cl @@ -0,0 +1,59 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double MATH_PRIVATE(lnep)(double2 a, int ea); + +CONSTATTR double2 +MATH_MANGLE(catanh)(double2 z) +{ + double x = BUILTIN_ABS_F64(z.x); + double y = BUILTIN_ABS_F64(z.y); + double rr, ri; + + if (x < 0x1.0p+54 && y < 0x1.0p+54) { + double2 omx = sub(1.0, x); + double2 opx = add(1.0, x); + double2 y2 = sqr(y); + double2 b = sub(mul(omx, opx), y2); + ri = 0.5 * MATH_MANGLE(atan2)(2.0 * y, b.hi); + + double2 a; + double2 d = add(sqr(opx), y2); + if (x < 0x1.0p-3 * d.hi) { + a = fsub(1.0, div(4.0*x, d)); + } else { + a = div(add(sqr(omx), y2), d); + } + rr = -0.25 * MATH_PRIVATE(lnep)(a, 0); + } else { + int e = BUILTIN_FREXP_EXP_F64(BUILTIN_MAX_F64(x, y)); + x = BUILTIN_FLDEXP_F64(x, -e); + y = BUILTIN_FLDEXP_F64(y, -e); + rr = BUILTIN_FLDEXP_F64(MATH_DIV(x, MATH_MAD(x, x, y*y)), -e); + ri = 0x1.921fb54442d18p+0; + } + + if (!FINITE_ONLY_OPT()) { + rr = ((x == 1.0) & (y == 0.0)) ? PINF_F64 : rr; + rr = x == 0.0 ? 0.0 : rr; + rr = BUILTIN_ISINF_F64(x) ? 0.0 : rr; + rr = (BUILTIN_ISNAN_F64(x) & BUILTIN_ISINF_F64(y)) ? 0.0 : rr; + ri = (BUILTIN_ISNAN_F64(x) & BUILTIN_ISFINITE_F64(y)) ? QNAN_F64 : ri; + ri = BUILTIN_ISNAN_F64(y) ? y : ri; + } + + rr = BUILTIN_COPYSIGN_F64(rr, z.x); + ri = BUILTIN_COPYSIGN_F64(ri, z.y); + + return (double2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/catanhF.cl b/amd/device-libs/ocml/src/catanhF.cl new file mode 100644 index 0000000000000..62947fc6df599 --- /dev/null +++ b/amd/device-libs/ocml/src/catanhF.cl @@ -0,0 +1,59 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float MATH_PRIVATE(lnep)(float2 a, int ea); + +CONSTATTR float2 +MATH_MANGLE(catanh)(float2 z) +{ + float x = BUILTIN_ABS_F32(z.x); + float y = BUILTIN_ABS_F32(z.y); + float rr, ri; + + if (x < 0x1.0p+25f && y < 0x1.0p+25f) { + float2 omx = sub(1.0f, x); + float2 opx = add(1.0f, x); + float2 y2 = sqr(y); + float2 b = sub(mul(omx, opx), y2); + ri = 0.5f * MATH_MANGLE(atan2)(2.0f * y, b.hi); + + float2 a; + float2 d = add(sqr(opx), y2); + if (x < 0x1.0p-3f * d.hi) { + a = fsub(1.0f, div(4.0f*x, d)); + } else { + a = div(add(sqr(omx), y2), d); + } + rr = -0.25f * MATH_PRIVATE(lnep)(a, 0); + } else { + int e = BUILTIN_FREXP_EXP_F32(AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(x), AS_UINT(y)))); + x = BUILTIN_FLDEXP_F32(x, -e); + y = BUILTIN_FLDEXP_F32(y, -e); + rr = BUILTIN_FLDEXP_F32(MATH_DIV(x, MATH_MAD(x, x, y*y)), -e); + ri = 0x1.921fb6p+0f; + } + + if (!FINITE_ONLY_OPT()) { + rr = ((x == 1.0f) & (y == 0.0f)) ? PINF_F32 : rr; + rr = x == 0.0f ? 0.0f : rr; + rr = BUILTIN_ISINF_F32(x) ? 0.0f : rr; + rr = (BUILTIN_ISNAN_F32(x) & BUILTIN_ISINF_F32(y)) ? 0.0f : rr; + ri = (BUILTIN_ISNAN_F32(x) & BUILTIN_ISFINITE_F32(y)) ? QNAN_F32 : ri; + ri = BUILTIN_ISNAN_F32(y) ? y : ri; + } + + rr = BUILTIN_COPYSIGN_F32(rr, z.x); + ri = BUILTIN_COPYSIGN_F32(ri, z.y); + + return (float2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/cbrtD.cl b/amd/device-libs/ocml/src/cbrtD.cl new file mode 100644 index 0000000000000..34e2a7d8c9807 --- /dev/null +++ b/amd/device-libs/ocml/src/cbrtD.cl @@ -0,0 +1,24 @@ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(cbrt)(double x) +{ + double a = BUILTIN_ABS_F64(x); + int e3 = BUILTIN_FREXP_EXP_F64(a); + int e = (int)BUILTIN_RINT_F32(0x1.555556p-2f * (float)e3); + a = BUILTIN_FLDEXP_F64(a, -3*e); + + double c = (double)BUILTIN_AMDGPU_EXP2_F32(0x1.555556p-2f * BUILTIN_AMDGPU_LOG2_F32((float)a)); + double c2 = c * c; + c = MATH_MAD(c, MATH_FAST_DIV(MATH_MAD(-c, c2, a), MATH_MAD(c+c, c2, a)), c); + + c = BUILTIN_FLDEXP_F64(c, e); + + if (!FINITE_ONLY_OPT()) { + // Is normal or subnormal. + c = ((x != 0.0) & BUILTIN_ISFINITE_F64(x)) ? c : x; + } + + return BUILTIN_COPYSIGN_F64(c, x); +} diff --git a/amd/device-libs/ocml/src/cbrtF.cl b/amd/device-libs/ocml/src/cbrtF.cl new file mode 100644 index 0000000000000..75f6651d345de --- /dev/null +++ b/amd/device-libs/ocml/src/cbrtF.cl @@ -0,0 +1,37 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(cbrt)(float x) +{ + if (DAZ_OPT()) { + x = BUILTIN_CANONICALIZE_F32(x); + } + + float ax = BUILTIN_ABS_F32(x); + bool denorm_or_zero = ax < 0x1p-126f; + + if (!DAZ_OPT()) { + ax = denorm_or_zero ? + BUILTIN_FLDEXP_F32(ax, 24) : ax; + } + + float z = BUILTIN_AMDGPU_EXP2_F32(0x1.555556p-2f * BUILTIN_AMDGPU_LOG2_F32(ax)); + z = MATH_MAD(MATH_MAD(MATH_FAST_RCP(z*z), -ax, z), -0x1.555556p-2f, z); + + if (!DAZ_OPT()) { + z = denorm_or_zero ? + BUILTIN_FLDEXP_F32(z, -8) : z; + } + + // Is normal or subnormal. + z = ((x != 0.0f) & BUILTIN_ISFINITE_F32(x)) ? z : x; + return BUILTIN_COPYSIGN_F32(z, x); +} + diff --git a/amd/device-libs/ocml/src/cbrtH.cl b/amd/device-libs/ocml/src/cbrtH.cl new file mode 100644 index 0000000000000..17fd336403917 --- /dev/null +++ b/amd/device-libs/ocml/src/cbrtH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(cbrt) + +CONSTATTR half +MATH_MANGLE(cbrt)(half x) +{ + half ret = (half)BUILTIN_AMDGPU_EXP2_F32(0x1.555556p-2f * BUILTIN_AMDGPU_LOG2_F32((float)BUILTIN_ABS_F16(x))); + ret = BUILTIN_COPYSIGN_F16(ret, x); + + // Is normal or subnormal. + return ((x != 0.0h) & BUILTIN_ISFINITE_F16(x)) ? ret : x; +} + diff --git a/amd/device-libs/ocml/src/ccosD.cl b/amd/device-libs/ocml/src/ccosD.cl new file mode 100644 index 0000000000000..539c560488d82 --- /dev/null +++ b/amd/device-libs/ocml/src/ccosD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double2 +MATH_MANGLE(ccos)(double2 z) +{ + return MATH_MANGLE(ccosh)((double2)(-z.y, z.x)); +} + diff --git a/amd/device-libs/ocml/src/ccosF.cl b/amd/device-libs/ocml/src/ccosF.cl new file mode 100644 index 0000000000000..9747d01f932d8 --- /dev/null +++ b/amd/device-libs/ocml/src/ccosF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE(ccos)(float2 z) +{ + return MATH_MANGLE(ccosh)((float2)(-z.y, z.x)); +} + diff --git a/amd/device-libs/ocml/src/ccoshD.cl b/amd/device-libs/ocml/src/ccoshD.cl new file mode 100644 index 0000000000000..def3dd01cd321 --- /dev/null +++ b/amd/device-libs/ocml/src/ccoshD.cl @@ -0,0 +1,49 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double2 MATH_PRIVATE(epexpep)(double2 z); + +CONSTATTR double2 +MATH_MANGLE(ccosh)(double2 z) +{ + double x = BUILTIN_ABS_F64(z.x); + double2 e = MATH_PRIVATE(epexpep)(sub(x, con(0x1.62e42fefa39efp+0,0x1.abc9e3b39803fp-55))); + double2 er = rcp(e); + er = ldx(er, -4); + double2 cx = fadd(e, er); + double2 sx = fsub(e, er); + double cy; + double sy = MATH_MANGLE(sincos)(z.y, &cy); + + double cxhi, sxhi; + if (FINITE_ONLY_OPT()) { + cxhi = cx.hi; + sxhi = sx.hi; + } else { + bool b = x >= 0x1.6395a2079b70cp+9; + cxhi = b ? PINF_F64 : cx.hi; + sxhi = b ? PINF_F64 : sx.hi; + } + + double rr = BUILTIN_FLDEXP_F64(cxhi * cy, 1); + bool s = x >= 0x1.0p-27; + double ri = BUILTIN_FLDEXP_F64(BUILTIN_COPYSIGN_F64(s ? sxhi : x, z.x) * sy, s); + + if (!FINITE_ONLY_OPT()) { + ri = ((x == 0.0) | (z.y == 0.0)) ? BUILTIN_COPYSIGN_F64(0.0, z.y) : ri; + rr = (BUILTIN_ISINF_F64(x) & + BUILTIN_CLASS_F64(z.y, CLASS_PINF|CLASS_NINF|CLASS_PZER|CLASS_NZER|CLASS_QNAN|CLASS_SNAN)) ? x : rr; + } + + return (double2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/ccoshF.cl b/amd/device-libs/ocml/src/ccoshF.cl new file mode 100644 index 0000000000000..a2d6ae3d93de7 --- /dev/null +++ b/amd/device-libs/ocml/src/ccoshF.cl @@ -0,0 +1,49 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float2 MATH_PRIVATE(epexpep)(float2 z); + +CONSTATTR float2 +MATH_MANGLE(ccosh)(float2 z) +{ + float x = BUILTIN_ABS_F32(z.x); + float2 e = MATH_PRIVATE(epexpep)(sub(x, con(0x1.62e430p+0, -0x1.05c610p-28f))); + float2 er = rcp(e); + er = ldx(er, -4); + float2 cx = fadd(e, er); + float2 sx = fsub(e, er); + float cy; + float sy = MATH_MANGLE(sincos)(z.y, &cy); + + float cxhi, sxhi; + if (FINITE_ONLY_OPT()) { + cxhi = cx.hi; + sxhi = sx.hi; + } else { + bool b = x >= 0x1.686fc0p+6f; + cxhi = b ? PINF_F32 : cx.hi; + sxhi = b ? PINF_F32 : sx.hi; + } + + float rr = BUILTIN_FLDEXP_F32(cxhi * cy, 1); + bool s = x >= 0x1.0p-12f; + float ri = BUILTIN_FLDEXP_F32(BUILTIN_COPYSIGN_F32(s ? sxhi : x, z.x) * sy, s); + + if (!FINITE_ONLY_OPT()) { + ri = ((x == 0.0f) | (z.y == 0.0f)) ? BUILTIN_COPYSIGN_F32(0.0f, z.y) : ri; + rr = (BUILTIN_ISINF_F32(x) & + BUILTIN_CLASS_F32(z.y, CLASS_PINF|CLASS_NINF|CLASS_PZER|CLASS_NZER|CLASS_QNAN|CLASS_SNAN)) ? x : rr; + } + + return (float2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/cdivD.cl b/amd/device-libs/ocml/src/cdivD.cl new file mode 100644 index 0000000000000..77750750b57a0 --- /dev/null +++ b/amd/device-libs/ocml/src/cdivD.cl @@ -0,0 +1,72 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define CP(A,B,C,D) ({ \ + double _a = A; \ + double _b = B; \ + double _c = C; \ + double _d = D; \ + double _bd = _b * _d; \ + double _e = BUILTIN_FMA_F64(_b, _d, -_bd); \ + double _f = BUILTIN_FMA_F64(_a, _c, _bd); \ + _f + _e; \ +}) + + +CONSTATTR double2 +MATH_MANGLE(cdiv)(double2 zn, double2 zd) +{ + double zdx = zd.x; + double zdy = zd.y; + bool g = BUILTIN_ABS_F64(zdx) > BUILTIN_ABS_F64(zdy); + int ed = BUILTIN_FREXP_EXP_F64(g ? zdx : zdy); + int en = BUILTIN_FREXP_EXP_F64(BUILTIN_MAX_F64(BUILTIN_ABS_F64(zn.x), BUILTIN_ABS_F64(zn.y))); + int es1 = 1022 - ed; + int es2 = 1022 - ed - ed; + int es3 = 1022 - ed - en; + int es = BUILTIN_MIN_S32(BUILTIN_MIN_S32(es1, es2), es3) >> 1; + + zdx = BUILTIN_FLDEXP_F64(zdx, es); + zdy = BUILTIN_FLDEXP_F64(zdy, es); + double u = g ? zdx : zdy; + double v = g ? zdy : zdx; + double d2 = BUILTIN_FMA_F64(u, u, v*v); + + zdx = BUILTIN_FLDEXP_F64(zdx, es); + zdy = BUILTIN_FLDEXP_F64(zdy, es); + double tr = CP(zn.x, zn.y, zdx, zdy); + double ti = CP(zn.y, -zn.x, zdx, zdy); + double rr = MATH_DIV(tr, d2); + double ri = MATH_DIV(ti, d2); + + if (!FINITE_ONLY_OPT()) { + if (BUILTIN_ISNAN_F64(rr) && BUILTIN_ISNAN_F64(ri)) { + if (d2 == 0.0 && (!BUILTIN_ISNAN_F64(zn.x) || !BUILTIN_ISNAN_F64(zn.y))) { + double i = BUILTIN_COPYSIGN_F64(PINF_F64, zd.x); + rr = i * zn.x; + ri = i * zn.y; + } else if ((BUILTIN_ISINF_F64(zn.x) || BUILTIN_ISINF_F64(zn.y)) && + (BUILTIN_ISFINITE_F64(zd.x) && BUILTIN_ISFINITE_F64(zd.y))) { + double znx = BUILTIN_COPYSIGN_F64(BUILTIN_ISINF_F64(zn.x) ? 1.0 : 0.0, zn.x); + double zny = BUILTIN_COPYSIGN_F64(BUILTIN_ISINF_F64(zn.y) ? 1.0 : 0.0, zn.y); + rr = PINF_F64 * MATH_MAD(znx, zd.x, zny * zd.y); + ri = PINF_F64 * MATH_MAD(zny, zd.x, -znx * zd.y); + } else if ((BUILTIN_ISINF_F64(zd.x) || BUILTIN_ISINF_F64(zd.y)) && + (BUILTIN_ISFINITE_F64(zn.x) && BUILTIN_ISFINITE_F64(zn.y))) { + zdx = BUILTIN_COPYSIGN_F64(BUILTIN_ISINF_F64(zd.x) ? 1.0 : 0.0, zd.x); + zdy = BUILTIN_COPYSIGN_F64(BUILTIN_ISINF_F64(zd.y) ? 1.0 : 0.0, zd.y); + rr = 0.0 * MATH_MAD(zn.x, zdx, zn.y * zdy); + ri = 0.0 * MATH_MAD(zn.y, zdx, -zn.x * zdy); + } + } + } + + return (double2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/cdivF.cl b/amd/device-libs/ocml/src/cdivF.cl new file mode 100644 index 0000000000000..739d2767f05e6 --- /dev/null +++ b/amd/device-libs/ocml/src/cdivF.cl @@ -0,0 +1,72 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define CP(A,B,C,D) ({ \ + float _a = A; \ + float _b = B; \ + float _c = C; \ + float _d = D; \ + float _bd = _b * _d; \ + float _e = BUILTIN_FMA_F32(_b, _d, -_bd); \ + float _f = BUILTIN_FMA_F32(_a, _c, _bd); \ + _f + _e; \ +}) + + +CONSTATTR float2 +MATH_MANGLE(cdiv)(float2 zn, float2 zd) +{ + float zdx = zd.x; + float zdy = zd.y; + bool g = BUILTIN_ABS_F32(zdx) > BUILTIN_ABS_F32(zdy); + int ed = BUILTIN_FREXP_EXP_F32(g ? zdx : zdy); + int en = BUILTIN_FREXP_EXP_F32(BUILTIN_MAX_F32(BUILTIN_ABS_F32(zn.x), BUILTIN_ABS_F32(zn.y))); + int es1 = 126 - ed; + int es2 = 126 - ed - ed; + int es3 = 126 - ed - en; + int es = BUILTIN_MIN_S32(BUILTIN_MIN_S32(es1, es2), es3) >> 1; + + zdx = BUILTIN_FLDEXP_F32(zdx, es); + zdy = BUILTIN_FLDEXP_F32(zdy, es); + float u = g ? zdx : zdy; + float v = g ? zdy : zdx; + float d2 = BUILTIN_FMA_F32(u, u, v*v); + + zdx = BUILTIN_FLDEXP_F32(zdx, es); + zdy = BUILTIN_FLDEXP_F32(zdy, es); + float tr = CP(zn.x, zn.y, zdx, zdy); + float ti = CP(zn.y, -zn.x, zdx, zdy); + float rr = MATH_DIV(tr, d2); + float ri = MATH_DIV(ti, d2); + + if (!FINITE_ONLY_OPT()) { + if (BUILTIN_ISNAN_F32(rr) && BUILTIN_ISNAN_F32(ri)) { + if (d2 == 0.0f && (!BUILTIN_ISNAN_F32(zn.x) || !BUILTIN_ISNAN_F32(zn.y))) { + float i = BUILTIN_COPYSIGN_F32(PINF_F32, zd.x); + rr = i * zn.x; + ri = i * zn.y; + } else if ((BUILTIN_ISINF_F32(zn.x) || BUILTIN_ISINF_F32(zn.y)) && + (BUILTIN_ISFINITE_F32(zd.x) && BUILTIN_ISFINITE_F32(zd.y))) { + float znx = BUILTIN_COPYSIGN_F32(BUILTIN_ISINF_F32(zn.x) ? 1.0f : 0.0f, zn.x); + float zny = BUILTIN_COPYSIGN_F32(BUILTIN_ISINF_F32(zn.y) ? 1.0f : 0.0f, zn.y); + rr = PINF_F32 * MATH_MAD(znx, zd.x, zny * zd.y); + ri = PINF_F32 * MATH_MAD(zny, zd.x, -znx * zd.y); + } else if ((BUILTIN_ISINF_F32(zd.x) || BUILTIN_ISINF_F32(zd.y)) && + (BUILTIN_ISFINITE_F32(zn.x) && BUILTIN_ISFINITE_F32(zn.y))) { + zdx = BUILTIN_COPYSIGN_F32(BUILTIN_ISINF_F32(zd.x) ? 1.0f : 0.0f, zd.x); + zdy = BUILTIN_COPYSIGN_F32(BUILTIN_ISINF_F32(zd.y) ? 1.0f : 0.0f, zd.y); + rr = 0.0f * MATH_MAD(zn.x, zdx, zn.y * zdy); + ri = 0.0f * MATH_MAD(zn.y, zdx, -zn.x * zdy); + } + } + } + + return (float2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/ceilD.cl b/amd/device-libs/ocml/src/ceilD.cl new file mode 100644 index 0000000000000..654226ccdd62e --- /dev/null +++ b/amd/device-libs/ocml/src/ceilD.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(ceil)(double x) +{ + return BUILTIN_CEIL_F64(x); +} diff --git a/amd/device-libs/ocml/src/ceilF.cl b/amd/device-libs/ocml/src/ceilF.cl new file mode 100644 index 0000000000000..8b1600c8796db --- /dev/null +++ b/amd/device-libs/ocml/src/ceilF.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(ceil)(float x) +{ + return BUILTIN_CEIL_F32(x); +} diff --git a/amd/device-libs/ocml/src/ceilH.cl b/amd/device-libs/ocml/src/ceilH.cl new file mode 100644 index 0000000000000..5b9804cb6d930 --- /dev/null +++ b/amd/device-libs/ocml/src/ceilH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(ceil)(half2 x) +{ + return BUILTIN_CEIL_2F16(x); +} + +CONSTATTR half +MATH_MANGLE(ceil)(half x) +{ + return BUILTIN_CEIL_F16(x); +} + diff --git a/amd/device-libs/ocml/src/cexpD.cl b/amd/device-libs/ocml/src/cexpD.cl new file mode 100644 index 0000000000000..e293f1adf5ee6 --- /dev/null +++ b/amd/device-libs/ocml/src/cexpD.cl @@ -0,0 +1,41 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double2 +MATH_MANGLE(cexp)(double2 z) +{ + double x = z.s0; + double y = z.s1; + double cy; + double sy = MATH_MANGLE(sincos)(y, &cy); + bool g = x > 709.0; + double ex = MATH_MANGLE(exp)(x - (g ? 1.0f : 0.0f)); + const double e1 = 0x1.5bf0a8b145769p+1; + cy *= g ? e1 : 1.0; + sy *= g ? e1 : 1.0; + double rr = ex * cy; + double ri = ex * sy; + + if (!FINITE_ONLY_OPT()) { + bool isfinite = BUILTIN_ISFINITE_F64(y); + if (x == NINF_F64) { + rr = 0.0; + ri = isfinite ? ri : 0.0; + } + if (x == PINF_F64) { + rr = isfinite ? rr : PINF_F64; + ri = isfinite ? ri : QNAN_F64; + ri = y == 0.0 ? y : ri; + } + ri = (BUILTIN_ISNAN_F64(x) & (y == 0.0)) ? y : ri; + } + + return (double2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/cexpF.cl b/amd/device-libs/ocml/src/cexpF.cl new file mode 100644 index 0000000000000..922061c4a9ed4 --- /dev/null +++ b/amd/device-libs/ocml/src/cexpF.cl @@ -0,0 +1,41 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE(cexp)(float2 z) +{ + float x = z.s0; + float y = z.s1; + float cy; + float sy = MATH_MANGLE(sincos)(y, &cy); + bool g = x > 88.0f; + float ex = MATH_MANGLE(exp)(x - (g ? 1.0f : 0.0f)); + const float e1 = 0x1.5bf0a8p+1f; + cy *= g ? e1 : 1.0f; + sy *= g ? e1 : 1.0f; + float rr = ex * cy; + float ri = ex * sy; + + if (!FINITE_ONLY_OPT()) { + bool finite = BUILTIN_ISFINITE_F32(y); + if (x == NINF_F32) { + rr = 0.0f; + ri = finite ? ri : 0.0f; + } + if (x == PINF_F32) { + rr = finite ? rr : PINF_F32; + ri = finite ? ri : QNAN_F32; + ri = y == 0.0f ? y : ri; + } + ri = (BUILTIN_ISNAN_F32(x) & (y == 0.0f)) ? y : ri; + } + + return (float2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/clogD.cl b/amd/device-libs/ocml/src/clogD.cl new file mode 100644 index 0000000000000..f47a1082b4e6a --- /dev/null +++ b/amd/device-libs/ocml/src/clogD.cl @@ -0,0 +1,37 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double MATH_PRIVATE(lnep)(double2 a, int ea); + +CONSTATTR double2 +MATH_MANGLE(clog)(double2 z) +{ + double x = z.s0; + double y = z.s1; + double a = BUILTIN_ABS_F64(x); + double b = BUILTIN_ABS_F64(y); + double t = BUILTIN_MAX_F64(a, b); + int e = BUILTIN_FREXP_EXP_F64(t) ; + a = BUILTIN_FLDEXP_F64(a, -e); + b = BUILTIN_FLDEXP_F64(b, -e); + double rr = 0.5 * MATH_PRIVATE(lnep)(add(sqr(a), sqr(b)), 2*e); + double ri = MATH_MANGLE(atan2)(y, x); + + + if (!FINITE_ONLY_OPT()) { + rr = ((x == 0.0) & (y == 0.0)) ? NINF_F64 : rr; + rr = (BUILTIN_ISINF_F64(x) | BUILTIN_ISINF_F64(y)) ? PINF_F64 : rr; + } + + return (double2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/clogF.cl b/amd/device-libs/ocml/src/clogF.cl new file mode 100644 index 0000000000000..2cf791b191f0a --- /dev/null +++ b/amd/device-libs/ocml/src/clogF.cl @@ -0,0 +1,37 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float MATH_PRIVATE(lnep)(float2 a, int ea); + +CONSTATTR float2 +MATH_MANGLE(clog)(float2 z) +{ + float x = z.s0; + float y = z.s1; + float a = BUILTIN_ABS_F32(x); + float b = BUILTIN_ABS_F32(y); + float t = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(a), AS_UINT(b))); + int e = BUILTIN_FREXP_EXP_F32(t) ; + a = BUILTIN_FLDEXP_F32(a, -e); + b = BUILTIN_FLDEXP_F32(b, -e); + float rr = 0.5f * MATH_PRIVATE(lnep)(add(sqr(a), sqr(b)), 2*e); + float ri = MATH_MANGLE(atan2)(y, x); + + + if (!FINITE_ONLY_OPT()) { + rr = ((x == 0.0f) & (y == 0.0f)) ? NINF_F32 : rr; + rr = (BUILTIN_ISINF_F32(x) | BUILTIN_ISINF_F32(y)) ? PINF_F32 : rr; + } + + return (float2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/convert.cl b/amd/device-libs/ocml/src/convert.cl new file mode 100644 index 0000000000000..b2e43a03d6812 --- /dev/null +++ b/amd/device-libs/ocml/src/convert.cl @@ -0,0 +1,481 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" +#include "builtins.h" +#include "opts.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#define ATTR __attribute__((const)) +#define AATTR(S) __attribute__((const, alias(S))) +#undef AVOID_FP + +ATTR half +OCML_MANGLE_F32(cvtrtn_f16)(float a) +{ +#if defined AVOID_FP + uint u = as_uint(a); + uint um = u & 0x7fffffU; + int e = (int)((u >> 23) & 0xff) - 127 + 15; + int ds = BUILTIN_CLAMP_S32(1-e, 0, 19); + uint t = (um | (e > -112 ? 0x800000 : 0)) << (19 - ds); + uint s = (u >> 16) & 0x8000; + uint m = (u >> 13) & 0x3ff; + uint i = 0x7c00 | m | (um ? 0x0200 : 0); + uint n = ((uint)e << 10) | m; + uint d = (0x400 | m) >> ds; + uint v = e < 1 ? d : n; + v += (s >> 15) & (t > 0U); + uint j = 0x7bff + (s >> 15); + v = e > 30 ? j : v; + v = e == 143 ? i : v; + return AS_HALF((ushort)(s | v)); +#else + half r = (half)a; + half p = OCML_MANGLE_F16(pred)(r); + return (float)r > a ? p : r; +#endif +} + +ATTR half +OCML_MANGLE_F32(cvtrtp_f16)(float a) +{ +#if defined AVOID_FP + uint u = as_uint(a); + uint um = u & 0x7fffffU; + int e = (int)((u >> 23) & 0xff) - 127 + 15; + int ds = BUILTIN_CLAMP_S32(1-e, 0, 19); + uint t = (um | (e > -112 ? 0x800000 : 0)) << (19 - ds); + uint s = (u >> 16) & 0x8000; + uint m = (u >> 13) & 0x3ff; + uint i = 0x7c00 | m | (um ? 0x0200 : 0); + uint n = ((uint)e << 10) | m; + uint d = (0x400 | m) >> ds; + uint v = e < 1 ? d : n; + v += ~(s >> 15) & (t > 0U); + uint j = 0x7c00 - (s >> 15); + v = e > 30 ? j : v; + v = e == 143 ? i : v; + return AS_HALF((ushort)(s | v)); +#else + half r = (half)a; + half s = OCML_MANGLE_F16(succ)(r); + return (float)r < a ? s : r; +#endif +} + +ATTR half +OCML_MANGLE_F32(cvtrtz_f16)(float a) +{ +#if defined AVOID_FP + uint u = as_uint(a); + uint um = u & 0x7fffffU; + int e = (int)((u >> 23) & 0xff) - 127 + 15; + uint s = (u >> 16) & 0x8000; + uint m = (u >> 13) & 0x3ff; + uint i = 0x7c00 | m | (um ? 0x0200 : 0); + uint n = ((uint)e << 10) | m; + uint d = (0x400 | m) >> (1 - e); + uint v = e > 30 ? 0x7bff : n; + v = e == 143 ? i : v; + v = e < 1 ? d : v; + v = e < -10 ? 0 : v; + return AS_HALF((ushort)(s | v)); +#else + float aa = BUILTIN_ABS_F32(a); + half r = (half)a; + half ar = BUILTIN_ABS_F16(r); + half z = OCML_MANGLE_F16(nextafter)(r, 0.0h); + return aa < (float)ar ? z : r; +#endif +} + +ATTR half +OCML_MANGLE_F64(cvtrte_f16)(double a) +{ + ulong u = as_ulong(a); + uint uh = u >> 32; + int e = (int)((uh >> 20) & 0x7ff) - 1023 + 15; + uint m = ((uh >> 8) & 0xffe) | (((uh & 0x1ff) | (uint)u) != 0); + uint i = 0x7c00 | (m != 0 ? 0x0200 : 0); + uint n = ((uint)e << 12) | m; + uint s = (uh >> 16) & 0x8000; + int b = BUILTIN_CLAMP_S32(1-e, 0, 13); + uint d = (0x1000 | m) >> b; + d |= (d << b) != (0x1000 | m); + uint v = e < 1 ? d : n; + v = (v >> 2) + ((v & 0x7) == 3 | (v & 0x7) > 5); + v = e > 30 ? 0x7c00 : v; + v = e == 1039 ? i : v; + return AS_HALF((ushort)(s | v)); +} + +ATTR half +OCML_MANGLE_F64(cvtrtn_f16)(double a) +{ + ulong u = as_ulong(a); + uint uh = u >> 32; + int e = (int)((uh >> 20) & 0x7ff) - 1023 + 15; + uint m = ((uh >> 9) & 0x7fe) | (((uh & 0x3ff) | (uint)u) != 0); + uint i = 0x7c00 | (m != 0 ? 0x0200 : 0); + uint n = ((uint)e << 11) | m; + uint s = (uh >> 16) & 0x8000; + uint vp = 0x7bff + (s >> 15); + int b = BUILTIN_CLAMP_S32(1-e, 0, 12); + uint d = (0x800 | m) >> b; + d |= (d << b) != (0x800 | m); + uint v = e < 1 ? d : n; + v = (v >> 1) + (v & 1 & (s >> 15)); + v = e > 30 ? vp : v; + v = e == 1039 ? i : v; + v = (e == -1008 & m == 0) ? 0 : v; + return AS_HALF((ushort)(s | v)); +} + +ATTR half +OCML_MANGLE_F64(cvtrtp_f16)(double a) +{ + ulong u = as_ulong(a); + uint uh = u >> 32; + int e = (int)((uh >> 20) & 0x7ff) - 1023 + 15; + uint m = ((uh >> 9) & 0x7fe) | (((uh & 0x3ff) | (uint)u) != 0); + uint i = 0x7c00 | (m != 0 ? 0x0200 : 0); + uint n = ((uint)e << 11) | m; + uint s = (uh >> 16) & 0x8000; + uint vp = 0x7c00 - (s >> 15); + int b = BUILTIN_CLAMP_S32(1-e, 0, 12); + uint d = (0x800 | m) >> b; + d |= (d << b) != (0x800 | m); + uint v = e < 1 ? d : n; + v = (v >> 1) + (v & 1 & ((s >> 15) ^ 1)); + v = e > 30 ? vp : v; + v = e == 1039 ? i : v; + v = (e == -1008 & m == 0) ? 0 : v; + return AS_HALF((ushort)(s | v)); +} + +ATTR half +OCML_MANGLE_F64(cvtrtz_f16)(double a) +{ + ulong u = as_ulong(a); + uint uh = u >> 32; + uint m = ((uh >> 9) & 0x7fe) | (((uh & 0x3ff) | (uint)u) != 0); + int e = (int)((uh >> 20) & 0x7ff) - 1023 + 15; + uint i = 0x7c00 | (m != 0 ? 0x0200 : 0); + m >>= 1; + uint d = (0x400 | m) >> (1 - e); + uint n = ((uint)e << 10) | m; + uint v = e > 30 ? 0x7bff : n; + v = e == 1039 ? i : v; + v = e < 1 ? d : v; + v = e < -10 ? 0 : v; + return AS_HALF((ushort)(((uh >> 16) & 0x8000) | v)); +} + +ATTR float +OCML_MANGLE_F64(cvtrtn_f32)(double a) +{ +#if defined AVOID_FP + ulong u = as_ulong(a); + ulong um = u & 0xfffffffffffffUL; + int e = (int)((u >> 52) & 0x7ff) - 1023 + 127; + int ds = BUILTIN_CLAMP_S32(1-e, 0, 31); + ulong t = (um | (e > -896 ? 0x0010000000000000UL : 0UL)) << (35 - ds); + uint s = (uint)(u >> 32) & 0x80000000; + uint m = (uint)(u >> 29) & 0x7fffff; + uint i = 0x7f800000 | m | (um ? 0x00400000 : 0U); + uint n = ((uint)(e << 23)) | m; + uint d = (0x800000 | m) >> ds; + uint v = e < 1 ? d : n; + v += (s >> 31) & (t > 0UL); + uint j = 0x7f7fffff + (s >> 31); + v = e > 254 ? j : v; + v = e == 1151 ? i : v; + return as_float(s | v); +#else + float r = (float)a; + float p = OCML_MANGLE_F32(pred)(r); + r = (double)r > a ? p : r; + if (DAZ_OPT()) { + float z = AS_FLOAT(AS_INT2(a).hi & 0x80000000); + r = a >= -0x1.fffffcp-127 && a < 0x1.0p-126 ? z : r; + } + return r; +#endif +} + +ATTR float +OCML_MANGLE_F64(cvtrtp_f32)(double a) +{ +#if defined AVOID_FP + ulong u = as_ulong(a); + ulong um = u & 0xfffffffffffffUL; + int e = (int)((u >> 52) & 0x7ff) - 1023 + 127; + int ds = BUILTIN_CLAMP_S32(1-e, 0, 31); + ulong t = (um | (e > -896 ? 0x0010000000000000UL : 0UL)) << (35 - ds); + uint s = (uint)(u >> 32) & 0x80000000; + uint m = (uint)(u >> 29) & 0x7fffff; + uint i = 0x7f800000 | m | (um ? 0x00400000 : 0U); + uint n = ((uint)(e << 23)) | m; + uint d = (0x800000 | m) >> ds; + uint v = e < 1 ? d : n; + v += ~(s >> 31) & (t > 0UL); + uint j = 0x7f800000 - (s >> 31); + v = e > 254 ? j : v; + v = e == 1151 ? i : v; + return as_float(s | v); +#else + float r = (float)a; + float s = OCML_MANGLE_F32(succ)(r); + r = (double)r < a ? s : r; + if (DAZ_OPT()) { + float z = AS_FLOAT(AS_INT2(a).hi & 0x80000000); + r = a <= 0x1.fffffcp-127 && a > -0x1.0p-126 ? z : r; + } + return r; +#endif +} + +ATTR float +OCML_MANGLE_F64(cvtrtz_f32)(double a) +{ +#if defined AVOID_FP + ulong u = as_ulong(a); + ulong um = u & 0xfffffffffffffUL; + int e = (int)((u >> 52) & 0x7ff) - 1023 + 127; + uint s = (uint)(u >> 32) & 0x80000000; + uint m = (uint)(u >> 29) & 0x7fffff; + uint i = 0x7f800000 | m | (um ? 0x00400000 : 0U); + uint n = ((uint)(e << 23)) | m; + uint d = (0x800000 | m) >> (1 - e); + uint v = e > 254 ? 0x7f7fffff : n; + v = e == 1151 ? i : v; + v = e < 1 ? d : v; + v = e < -23 ? 0 : v; + return as_float(s | v); +#else + double aa = BUILTIN_ABS_F64(a); + float r = (float)a; + float ar = BUILTIN_ABS_F32(r); + float z = OCML_MANGLE_F32(nextafter)(r, 0.0f); + return aa < (double)ar ? z : r; +#endif +} + +ATTR float +OCML_MANGLE_S32(cvtrtn_f32)(int i) +{ +#if defined AVOID_FP + int s = i >> 31; + uint u = AS_UINT((i + s) ^ s); + uint lz = BUILTIN_CLZ_U32(u); + uint e = 127U + 31U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffU; + uint t = u & 0xffU; + u = (e << 23) | (u >> 8); + return AS_FLOAT((u + ((s & t) > 0)) | (s & 0x80000000)); +#else + float r = (float)BUILTIN_MIN_S32(i, 0x7fffffbf); + float p = OCML_MANGLE_F32(pred)(r); + return (int)r > i ? p : r; +#endif +} + +ATTR float +OCML_MANGLE_S32(cvtrtp_f32)(int i) +{ +#if defined AVOID_FP + int s = i >> 31; + uint u = AS_UINT((i + s) ^ s); + uint lz = BUILTIN_CLZ_U32(u); + uint e = 127U + 31U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffU; + uint t = u & 0xffU; + u = (e << 23) | (u >> 8); + return AS_FLOAT((u + ((~s & t) > 0)) | (s & 0x80000000)); +#else + float r = (float)BUILTIN_MIN_S32(i, 0x7fffffbf); + float s = OCML_MANGLE_F32(succ)(r); + return (int)r < i ? s : r; +#endif +} + +ATTR float +OCML_MANGLE_S32(cvtrtz_f32)(int i) +{ + int s = i >> 31; + uint u = AS_UINT((i + s) ^ s); + uint lz = BUILTIN_CLZ_U32(u); + uint e = 127U + 31U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffU; + u = (e << 23) | (u >> 8); + return AS_FLOAT(u | (s & 0x80000000)); +} + +ATTR static float +cvt1f4_zu4(uint u) +{ + uint lz = BUILTIN_CLZ_U32(u); + uint e = 127U + 31U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffU; + return AS_FLOAT((e << 23) | (u >> 8)); +} +extern AATTR("cvt1f4_zu4") float OCML_MANGLE_U32(cvtrtn_f32)(uint); +extern AATTR("cvt1f4_zu4") float OCML_MANGLE_U32(cvtrtz_f32)(uint); + +ATTR float +OCML_MANGLE_U32(cvtrtp_f32)(uint u) +{ +#if defined AVOID_FP + uint lz = BUILTIN_CLZ_U32(u); + uint e = 127U + 31U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffU; + uint t = u & 0xffU; + u = (e << 23) | (u >> 8); + return AS_FLOAT(u + (t > 0)); +#else + float r = (float)BUILTIN_MIN_S32(u, 0xffffff7fU); + float s = OCML_MANGLE_F32(succ)(r); + return (uint)r < u ? s : r; +#endif +} + +ATTR float +OCML_MANGLE_S64(cvtrtn_f32)(long l) +{ + long s = l >> 63; + ulong u = AS_ULONG((l + s) ^ s); + uint lz = BUILTIN_CLZ_U64(u); + uint e = 127U + 63U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffffffffffUL; + ulong t = u & 0xffffffffffUL; + uint v = (e << 23) | (uint)(u >> 40); + return AS_FLOAT((v + ((s & t) > 0)) | ((uint)s & 0x80000000)); +} + +ATTR float +OCML_MANGLE_S64(cvtrtp_f32)(long l) +{ + long s = l >> 63; + ulong u = AS_ULONG((l + s) ^ s); + uint lz = BUILTIN_CLZ_U64(u); + uint e = 127U + 63U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffffffffffUL; + ulong t = u & 0xffffffffffUL; + uint v = (e << 23) | (uint)(u >> 40); + return AS_FLOAT((v + ((~s & t) > 0)) | ((uint)s & 0x80000000)); +} + +ATTR float +OCML_MANGLE_S64(cvtrtz_f32)(long l) +{ + long s = l >> 63; + ulong u = AS_ULONG((l + s) ^ s); + uint lz = BUILTIN_CLZ_U64(u); + uint e = 127U + 63U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffffffffffUL; + uint v = (e << 23) | (uint)(u >> 40); + return AS_FLOAT(v | ((uint)s & 0x80000000)); +} + +ATTR static float +cvt1f4_zu8(ulong u) +{ + uint lz = BUILTIN_CLZ_U64(u); + uint e = 127U + 63U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffffffffffUL; + return AS_FLOAT((e << 23) | (uint)(u >> 40)); +} +extern AATTR("cvt1f4_zu8") float OCML_MANGLE_U64(cvtrtn_f32)(ulong); +extern AATTR("cvt1f4_zu8") float OCML_MANGLE_U64(cvtrtz_f32)(ulong); + +ATTR float +OCML_MANGLE_U64(cvtrtp_f32)(ulong u) +{ + uint lz = BUILTIN_CLZ_U64(u); + uint e = 127U + 63U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffffffffffUL; + ulong t = u & 0xffffffffffUL; + uint v = (e << 23) | (uint)(u >> 40); + return AS_FLOAT(v + (t > 0)); +} + +ATTR double +OCML_MANGLE_S64(cvtrtn_f64)(long l) +{ + long s = l >> 63; + ulong u = AS_ULONG((l + s) ^ s); + uint lz = BUILTIN_CLZ_U64(u); + uint e = 1023U + 63U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffffffffffUL; + ulong t = u & 0x7ffUL; + u = ((ulong)e << 52) | (u >> 11); + return AS_DOUBLE((u + ((s & t) > 0)) | ((ulong)s & 0x8000000000000000UL)); +} + +ATTR double +OCML_MANGLE_S64(cvtrtp_f64)(long l) +{ + long s = l >> 63; + ulong u = AS_ULONG((l + s) ^ s); + uint lz = BUILTIN_CLZ_U64(u); + uint e = 1023U + 63U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffffffffffUL; + ulong t = u & 0x7ffUL; + u = ((ulong)e << 52) | (u >> 11); + return AS_DOUBLE((u + ((~s & t) > 0)) | ((ulong)s & 0x8000000000000000UL)); +} + +ATTR double +OCML_MANGLE_S64(cvtrtz_f64)(long l) +{ + long s = l >> 63; + ulong u = AS_ULONG((l + s) ^ s); + uint lz = BUILTIN_CLZ_U64(u); + uint e = 1023U + 63U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffffffffffUL; + u = ((ulong)e << 52) | (u >> 11); + return AS_DOUBLE(u | ((ulong)s & 0x8000000000000000UL)); +} + +ATTR static double +cvt1f8_zu8(ulong u) +{ + uint lz = BUILTIN_CLZ_U64(u); + uint e = 1023U + 63U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffffffffffUL; + return AS_DOUBLE(((ulong)e << 52) | (u >> 11)); +} +AATTR("cvt1f8_zu8") double OCML_MANGLE_U64(cvtrtn_f64)(ulong); +AATTR("cvt1f8_zu8") double OCML_MANGLE_U64(cvtrtz_f64)(ulong); + +ATTR double +OCML_MANGLE_U64(cvtrtp_f64)(ulong u) +{ + uint lz = BUILTIN_CLZ_U64(u); + uint e = 1023U + 63U - lz; + e = u ? e : 0; + u = (u << lz) & 0x7fffffffffffffffUL; + ulong t = u & 0x7ffUL; + u = ((ulong)e << 52) | (u >> 11); + return AS_DOUBLE(u + (t > 0UL)); +} + diff --git a/amd/device-libs/ocml/src/copysignD.cl b/amd/device-libs/ocml/src/copysignD.cl new file mode 100644 index 0000000000000..b239b79300ae6 --- /dev/null +++ b/amd/device-libs/ocml/src/copysignD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(copysign)(double x, double y) +{ + return BUILTIN_COPYSIGN_F64(x, y); +} + diff --git a/amd/device-libs/ocml/src/copysignF.cl b/amd/device-libs/ocml/src/copysignF.cl new file mode 100644 index 0000000000000..f2fac4ab69ca8 --- /dev/null +++ b/amd/device-libs/ocml/src/copysignF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(copysign)(float x, float y) +{ + return BUILTIN_COPYSIGN_F32(x, y); +} + diff --git a/amd/device-libs/ocml/src/copysignH.cl b/amd/device-libs/ocml/src/copysignH.cl new file mode 100644 index 0000000000000..7897b1e36f13a --- /dev/null +++ b/amd/device-libs/ocml/src/copysignH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(copysign)(half2 x, half2 y) +{ + return BUILTIN_COPYSIGN_2F16(x, y); +} + +CONSTATTR half +MATH_MANGLE(copysign)(half x, half y) +{ + return BUILTIN_COPYSIGN_F16(x, y); +} + diff --git a/amd/device-libs/ocml/src/cosD.cl b/amd/device-libs/ocml/src/cosD.cl new file mode 100644 index 0000000000000..801753a48bad5 --- /dev/null +++ b/amd/device-libs/ocml/src/cosD.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +double +MATH_MANGLE(cos)(double x) +{ + double ax = BUILTIN_ABS_F64(x); + struct redret r = MATH_PRIVATE(trigred)(ax); + struct scret sc = MATH_PRIVATE(sincosred2)(r.hi, r.lo); + sc.s = -sc.s; + + int2 c = AS_INT2((r.i & 1) != 0 ? sc.s : sc.c); + c.hi ^= r.i > 1 ? (int)0x80000000 : 0; + + if (!FINITE_ONLY_OPT()) { + c = BUILTIN_ISFINITE_F64(ax) ? c : AS_INT2(QNANBITPATT_DP64); + } + + return AS_DOUBLE(c); +} + diff --git a/amd/device-libs/ocml/src/cosF.cl b/amd/device-libs/ocml/src/cosF.cl new file mode 100644 index 0000000000000..638e56eeb27dd --- /dev/null +++ b/amd/device-libs/ocml/src/cosF.cl @@ -0,0 +1,34 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +float +MATH_MANGLE(cos)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + + struct redret r = MATH_PRIVATE(trigred)(AS_FLOAT(ax)); + +#if defined EXTRA_PRECISION + struct scret sc = MATH_PRIVATE(sincosred2)(r.hi, r.lo); +#else + struct scret sc = MATH_PRIVATE(sincosred)(r.hi); +#endif + sc.s = -sc.s; + + float c = (r.i & 1) != 0 ? sc.s : sc.c; + c = AS_FLOAT(AS_INT(c) ^ (r.i > 1 ? 0x80000000 : 0)); + + if (!FINITE_ONLY_OPT()) { + c = BUILTIN_ISFINITE_F32(ax) ? c : QNAN_F32; + } + + return c; +} + diff --git a/amd/device-libs/ocml/src/cosH.cl b/amd/device-libs/ocml/src/cosH.cl new file mode 100644 index 0000000000000..182d12febfca2 --- /dev/null +++ b/amd/device-libs/ocml/src/cosH.cl @@ -0,0 +1,30 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigredH.h" + +UGEN(cos) + +half +MATH_MANGLE(cos)(half x) +{ + half ax = BUILTIN_ABS_F16(x); + struct redret r = MATH_PRIVATE(trigred)(ax); + struct scret sc = MATH_PRIVATE(sincosred)(r.hi); + sc.s = -sc.s; + + short c = AS_SHORT((r.i & 1) == (short)0 ? sc.c : sc.s); + c ^= r.i > 1 ? (short)0x8000 : (short)0; + + if (!FINITE_ONLY_OPT()) { + c = BUILTIN_ISFINITE_F16(ax) ? c : (short)QNANBITPATT_HP16; + } + + return AS_HALF(c); +} + diff --git a/amd/device-libs/ocml/src/cosbD.cl b/amd/device-libs/ocml/src/cosbD.cl new file mode 100644 index 0000000000000..0838b61851864 --- /dev/null +++ b/amd/device-libs/ocml/src/cosbD.cl @@ -0,0 +1,55 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +#define FSUM2(A, B, H, L) \ + do { \ + double __s = A + B; \ + double __t = B - (__s - A); \ + H = __s; \ + L = __t; \ + } while (0) + +#define FDIF2(A, B, H, L) \ + do { \ + double __d = A - B; \ + double __e = (A - __d) - B; \ + H = __d; \ + L = __e; \ + } while (0) + +double +MATH_PRIVATE(cosb)(double x, int n, double p) +{ + struct redret r = MATH_PRIVATE(trigred)(x); + bool b = r.hi < p; + r.i = (r.i - b - n) & 3; + + // This is a properly signed extra precise pi/4 + double ph = AS_DOUBLE((uint2)(0x54442d18, 0xbfe921fb ^ (b ? 0x80000000 : 0))); + double pl = AS_DOUBLE((uint2)(0x33145c07, 0xbc81a626 ^ (b ? 0x80000000 : 0))); + + double sh, sl; + FDIF2(ph, p, ph, sl); + pl += sl; + FSUM2(ph, pl, ph, pl); + + FSUM2(ph, r.hi, sh, sl); + sl += pl + r.lo; + FSUM2(sh, sl, sh, sl); + + struct scret sc = MATH_PRIVATE(sincosred2)(sh, sl); + sc.s = -sc.s; + + int2 c = AS_INT2((r.i & 1) != 0 ? sc.s : sc.c); + c.hi ^= r.i > 1 ? 0x80000000 : 0; + + return AS_DOUBLE(c); +} + diff --git a/amd/device-libs/ocml/src/cosbF.cl b/amd/device-libs/ocml/src/cosbF.cl new file mode 100644 index 0000000000000..60e1f415e9173 --- /dev/null +++ b/amd/device-libs/ocml/src/cosbF.cl @@ -0,0 +1,60 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +#define FSUM2(A, B, H, L) \ + do { \ + float __s = A + B; \ + float __t = B - (__s - A); \ + H = __s; \ + L = __t; \ + } while (0) + +#define FDIF2(A, B, H, L) \ + do { \ + float __d = A - B; \ + float __e = (A - __d) - B; \ + H = __d; \ + L = __e; \ + } while (0) + +float +MATH_PRIVATE(cosb)(float x, int n, float p) +{ + struct redret r = MATH_PRIVATE(trigred)(x); + bool b = r.hi < p; + r.i = (r.i - b - n) & 3; + +#if defined EXTRA_PRECISION + float ph = AS_FLOAT(0xbf490fdb ^ (b ? 0x80000000 : 0)); + float pl = AS_FLOAT(0x32bbbd2e ^ (b ? 0x80000000 : 0)); + + float sh, sl; + + FDIF2(ph, p, ph, sl); + pl += sl; + FSUM2(ph, pl, ph, pl); + + FSUM2(ph, r.hi, sh, sl); + sl += pl + r.lo; + FSUM2(sh, sl, sh, sl); + + struct scret sc = MATH_PRIVATE(sincosred2)(sh, sl); +#else + r.hi = r.hi - p + AS_FLOAT(0xbf490fdb ^ (b ? 0x80000000 : 0)); + + struct scret sc = MATH_PRIVATE(sincosred)(r.hi); +#endif + sc.s = -sc.s; + + float c = (r.i & 1) != 0 ? sc.s : sc.c; + c = AS_FLOAT(AS_INT(c) ^ (r.i > 1 ? 0x80000000 : 0)); + return c; +} + diff --git a/amd/device-libs/ocml/src/coshD.cl b/amd/device-libs/ocml/src/coshD.cl new file mode 100644 index 0000000000000..dcef7ecc07c69 --- /dev/null +++ b/amd/device-libs/ocml/src/coshD.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double2 MATH_PRIVATE(epexpep)(double2 x); + +CONSTATTR double +MATH_MANGLE(cosh)(double x) +{ + x = BUILTIN_ABS_F64(x); + double2 e = MATH_PRIVATE(epexpep)(sub(x, con(0x1.62e42fefa39efp-1,0x1.abc9e3b39803fp-56))); + double2 c = fadd(e, ldx(rcp(e), -2)); + double z = c.hi; + + if (!FINITE_ONLY_OPT()) { + z = x >= 0x1.633ce8fb9f87ep+9 ? PINF_F64 : z; + } + + return z; +} + diff --git a/amd/device-libs/ocml/src/coshF.cl b/amd/device-libs/ocml/src/coshF.cl new file mode 100644 index 0000000000000..a0d0a199fd18d --- /dev/null +++ b/amd/device-libs/ocml/src/coshF.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float2 MATH_PRIVATE(epexpep)(float2 x); + +CONSTATTR float +MATH_MANGLE(cosh)(float x) +{ + x = BUILTIN_ABS_F32(x); + float2 e = MATH_PRIVATE(epexpep)(sub(x, con(0x1.62e430p-1f, -0x1.05c610p-29f))); + float2 c = fadd(e, ldx(rcp(e), -2)); + float z = c.hi; + + if (!FINITE_ONLY_OPT()) { + z = x > 0x1.65a9f8p+6f ? PINF_F32 : z; + } + + return z; +} + diff --git a/amd/device-libs/ocml/src/coshH.cl b/amd/device-libs/ocml/src/coshH.cl new file mode 100644 index 0000000000000..c513a8b9bdb86 --- /dev/null +++ b/amd/device-libs/ocml/src/coshH.cl @@ -0,0 +1,18 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(cosh) + +CONSTATTR half +MATH_MANGLE(cosh)(half hx) +{ + float x = (float)hx * 0x1.715476p+0f; + return (half)(0.5f * (BUILTIN_AMDGPU_EXP2_F32(x) + BUILTIN_AMDGPU_EXP2_F32(-x))); +} + diff --git a/amd/device-libs/ocml/src/cospiD.cl b/amd/device-libs/ocml/src/cospiD.cl new file mode 100644 index 0000000000000..111c0e5bfbcd8 --- /dev/null +++ b/amd/device-libs/ocml/src/cospiD.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigpiredD.h" + +double +MATH_MANGLE(cospi)(double x) +{ + double ax = BUILTIN_ABS_F64(x); + struct redret r = MATH_PRIVATE(trigpired)(ax); + struct scret sc = MATH_PRIVATE(sincospired)(r.hi); + sc.s = -sc.s; + + double c = (r.i & 1) == 0 ? sc.c : sc.s; + c = r.i > 1 ? -c : c; + + if (!FINITE_ONLY_OPT() && !BUILTIN_ISFINITE_F64(ax)) { + c = QNAN_F64; + } + + return c; +} + diff --git a/amd/device-libs/ocml/src/cospiF.cl b/amd/device-libs/ocml/src/cospiF.cl new file mode 100644 index 0000000000000..ed7433711f28d --- /dev/null +++ b/amd/device-libs/ocml/src/cospiF.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigpiredF.h" + +CONSTATTR float +MATH_MANGLE(cospi)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + struct redret r = MATH_PRIVATE(trigpired)(ax); + struct scret sc = MATH_PRIVATE(sincospired)(r.hi); + sc.s = -sc.s; + + float c = (r.i & 1) != 0 ? sc.s : sc.c; + c = r.i > 1 ? -c : c; + + if (!FINITE_ONLY_OPT() && !BUILTIN_ISFINITE_F32(ax)) { + c = QNAN_F32; + } + + return c; +} + diff --git a/amd/device-libs/ocml/src/cospiH.cl b/amd/device-libs/ocml/src/cospiH.cl new file mode 100644 index 0000000000000..e581c78156fe4 --- /dev/null +++ b/amd/device-libs/ocml/src/cospiH.cl @@ -0,0 +1,30 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigpiredH.h" + +UGEN(cospi) + +half +MATH_MANGLE(cospi)(half x) +{ + half ax = BUILTIN_ABS_F16(x); + struct redret r = MATH_PRIVATE(trigpired)(ax); + struct scret sc = MATH_PRIVATE(sincospired)(r.hi); + sc.s = -sc.s; + + half c = (r.i & (short)1) == (short)0 ? sc.c : sc.s; + c = r.i > (short)1 ? -c : c; + + if (!FINITE_ONLY_OPT() && !BUILTIN_ISFINITE_F16(ax)) { + c = QNAN_F16; + } + + return c; +} + diff --git a/amd/device-libs/ocml/src/csinD.cl b/amd/device-libs/ocml/src/csinD.cl new file mode 100644 index 0000000000000..57d8e5e15359c --- /dev/null +++ b/amd/device-libs/ocml/src/csinD.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double2 +MATH_MANGLE(csin)(double2 z) +{ + double2 r = MATH_MANGLE(csinh)((double2)(-z.y, z.x)); + return (double2)(r.y, -r.x); +} + diff --git a/amd/device-libs/ocml/src/csinF.cl b/amd/device-libs/ocml/src/csinF.cl new file mode 100644 index 0000000000000..f6df862c2dd44 --- /dev/null +++ b/amd/device-libs/ocml/src/csinF.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE(csin)(float2 z) +{ + float2 r = MATH_MANGLE(csinh)((float2)(-z.y, z.x)); + return (float2)(r.y, -r.x); +} + diff --git a/amd/device-libs/ocml/src/csinhD.cl b/amd/device-libs/ocml/src/csinhD.cl new file mode 100644 index 0000000000000..c0cbbc5b02b95 --- /dev/null +++ b/amd/device-libs/ocml/src/csinhD.cl @@ -0,0 +1,48 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double2 MATH_PRIVATE(epexpep)(double2 z); + +CONSTATTR double2 +MATH_MANGLE(csinh)(double2 z) +{ + double x = BUILTIN_ABS_F64(z.x); + double2 e = MATH_PRIVATE(epexpep)(sub(x, con(0x1.62e42fefa39efp+0,0x1.abc9e3b39803fp-55))); + double2 er = rcp(e); + er = ldx(er, -4); + double2 cx = fadd(e, er); + double2 sx = fsub(e, er); + double cy; + double sy = MATH_MANGLE(sincos)(z.y, &cy); + + double cxhi = cx.hi; + double sxhi = sx.hi; + + if (!FINITE_ONLY_OPT()) { + bool b = x >= 0x1.6395a2079b70cp+9; + cxhi = b ? PINF_F64 : cxhi; + sxhi = b ? PINF_F64 : sxhi; + } + + bool s = x >= 0x1.0p-27; + double rr = BUILTIN_FLDEXP_F64(BUILTIN_COPYSIGN_F64(s ? sxhi : x, z.x) * cy, s); + double ri = BUILTIN_FLDEXP_F64(cxhi * sy, 1); + + if (!FINITE_ONLY_OPT()) { + rr = (!BUILTIN_CLASS_F64(x, CLASS_PZER|CLASS_NZER|CLASS_PINF|CLASS_NINF) | + BUILTIN_ISFINITE_F64(z.y)) ? rr : z.x; + ri = (BUILTIN_ISFINITE_F64(x) | (z.y != 0.0)) ? ri : z.y; + } + + return (double2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/csinhF.cl b/amd/device-libs/ocml/src/csinhF.cl new file mode 100644 index 0000000000000..622c58f025b3d --- /dev/null +++ b/amd/device-libs/ocml/src/csinhF.cl @@ -0,0 +1,48 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float2 MATH_PRIVATE(epexpep)(float2 z); + +CONSTATTR float2 +MATH_MANGLE(csinh)(float2 z) +{ + float x = BUILTIN_ABS_F32(z.x); + float2 e = MATH_PRIVATE(epexpep)(sub(x, con(0x1.62e430p+0, -0x1.05c610p-28f))); + float2 er = rcp(e); + er = ldx(er, -4); + float2 cx = fadd(e, er); + float2 sx = fsub(e, er); + float cy; + float sy = MATH_MANGLE(sincos)(z.y, &cy); + + float cxhi = cx.hi; + float sxhi = sx.hi; + + if (!FINITE_ONLY_OPT()) { + bool b = x >= 0x1.686fc0p+6f; + cxhi = b ? PINF_F32 : cxhi; + sxhi = b ? PINF_F32 : sxhi; + } + + bool s = x >= 0x1.0p-12f; + float rr = BUILTIN_FLDEXP_F32(BUILTIN_COPYSIGN_F32(s ? sxhi : x, z.x) * cy, s); + float ri = BUILTIN_FLDEXP_F32(cxhi * sy, 1); + + if (!FINITE_ONLY_OPT()) { + rr = (!BUILTIN_CLASS_F32(x, CLASS_PZER|CLASS_NZER|CLASS_PINF|CLASS_NINF) | + BUILTIN_ISFINITE_F32(z.y)) ? rr : z.x; + ri = (BUILTIN_ISFINITE_F32(x) | (z.y != 0.0f)) ? ri : z.y; + } + + return (float2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/csqrtD.cl b/amd/device-libs/ocml/src/csqrtD.cl new file mode 100644 index 0000000000000..8614c8250be0a --- /dev/null +++ b/amd/device-libs/ocml/src/csqrtD.cl @@ -0,0 +1,47 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double2 +MATH_MANGLE(csqrt)(double2 z) +{ + double a = BUILTIN_ABS_F64(z.x); + double b = BUILTIN_ABS_F64(z.y); + double t = BUILTIN_MAX_F64(a, b); + + if (!FINITE_ONLY_OPT()) { + t = BUILTIN_ISUNORDERED_F64(a, b) ? QNAN_F64 : t; + } + + int e = BUILTIN_FREXP_EXP_F64(t); + double as = BUILTIN_FLDEXP_F64(a, -e); + double bs = BUILTIN_FLDEXP_F64(b, -e); + bool o = BUILTIN_CLASS_F64(t, CLASS_NZER|CLASS_PZER|CLASS_NINF|CLASS_PINF|CLASS_QNAN|CLASS_SNAN); + double p = MATH_FAST_SQRT(MATH_MAD(as, as, bs*bs)); + p = o ? t : p; + int k = (e & 1) ^ 1; + p = BUILTIN_FLDEXP_F64(p + as, k); + p = BUILTIN_FLDEXP_F64(MATH_FAST_SQRT(p), (e >> 1) - k); + p = o ? t : p; + double q = BUILTIN_FLDEXP_F64(MATH_DIV(b, p), -1); + q = t == 0.0 ? t : q; + bool l = z.x < 0.0; + double rr = l ? q : p; + double ri = l ? p : q; + + if (!FINITE_ONLY_OPT()) { + bool i = BUILTIN_ISINF_F64(b); + rr = i ? b : rr; + ri = i ? b : ri; + ri = z.x == NINF_F64 ? a : ri; + rr = z.x == PINF_F64 ? a : rr; + } + + return (double2)(rr, BUILTIN_COPYSIGN_F64(ri, z.y)); +} + diff --git a/amd/device-libs/ocml/src/csqrtF.cl b/amd/device-libs/ocml/src/csqrtF.cl new file mode 100644 index 0000000000000..a4479a2a1374b --- /dev/null +++ b/amd/device-libs/ocml/src/csqrtF.cl @@ -0,0 +1,38 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE(csqrt)(float2 z) +{ + float a = BUILTIN_ABS_F32(z.x); + float b = BUILTIN_ABS_F32(z.y); + int e = BUILTIN_FREXP_EXP_F32(BUILTIN_MAX_F32(a, b)); + float as = BUILTIN_FLDEXP_F32(a, -e); + float bs = BUILTIN_FLDEXP_F32(b, -e); + float p = MATH_FAST_SQRT(MATH_MAD(as, as, bs*bs)); + int k = (e & 1) ^ 1; + p = BUILTIN_FLDEXP_F32(p + as, k); + p = BUILTIN_FLDEXP_F32(MATH_FAST_SQRT(p), (e >> 1) - k); + float q = BUILTIN_FLDEXP_F32(MATH_DIV(b, p), -1); + q = p == 0.0f ? p : q; + bool l = z.x < 0.0f; + float rr = l ? q : p; + float ri = l ? p : q; + + if (!FINITE_ONLY_OPT()) { + bool i = BUILTIN_ISINF_F32(b); + rr = i ? b : rr; + ri = i ? b : ri; + ri = z.x == NINF_F32 ? a : ri; + rr = z.x == PINF_F32 ? a : rr; + } + + return (float2)(rr, BUILTIN_COPYSIGN_F32(ri, z.y)); +} + diff --git a/amd/device-libs/ocml/src/ctanD.cl b/amd/device-libs/ocml/src/ctanD.cl new file mode 100644 index 0000000000000..68c0fd70834e5 --- /dev/null +++ b/amd/device-libs/ocml/src/ctanD.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double2 +MATH_MANGLE(ctan)(double2 z) +{ + double2 r = MATH_MANGLE(ctanh)((double2)(-z.y, z.x)); + return (double2)(r.y, -r.x); +} + diff --git a/amd/device-libs/ocml/src/ctanF.cl b/amd/device-libs/ocml/src/ctanF.cl new file mode 100644 index 0000000000000..f90ebaf02ebff --- /dev/null +++ b/amd/device-libs/ocml/src/ctanF.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE(ctan)(float2 z) +{ + float2 r = MATH_MANGLE(ctanh)((float2)(-z.y, z.x)); + return (float2)(r.y, -r.x); +} + diff --git a/amd/device-libs/ocml/src/ctanhD.cl b/amd/device-libs/ocml/src/ctanhD.cl new file mode 100644 index 0000000000000..54ec6583add4b --- /dev/null +++ b/amd/device-libs/ocml/src/ctanhD.cl @@ -0,0 +1,54 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double2 MATH_PRIVATE(epexpep)(double2 z); + +CONSTATTR double2 +MATH_MANGLE(ctanh)(double2 z) +{ + double cy; + double sy = MATH_MANGLE(sincos)(z.y, &cy); + double cysy = cy*sy; + double x = BUILTIN_ABS_F64(z.x); + + double rr, ri; + if (x < 0x1.419ecb712c481p+4) { + double2 e = MATH_PRIVATE(epexpep)(sub(x, con(0x1.62e42fefa39efp-1,0x1.abc9e3b39803fp-56))); + double2 er = rcp(e); + er = ldx(er, -2); + double2 cx = fadd(e, er); + double2 sx = fsub(e, er); + + double cxhi = cx.hi; + double sxhi = x < 0x1.0p-27 ? x : sx.hi; + + double d = MATH_MAD(cy, cy, sxhi*sxhi); + rr = BUILTIN_COPYSIGN_F64(MATH_DIV(cxhi*sxhi, d), z.x); + ri = MATH_DIV(cysy, d); + } else { + rr = BUILTIN_COPYSIGN_F64(1.0, z.x); + ri = 4.0 * cysy * MATH_MANGLE(exp)(-2.0 * x); + } + + if (!FINITE_ONLY_OPT()) { + bool xn = BUILTIN_ISNAN_F64(x); + bool yin = !BUILTIN_ISFINITE_F64(z.y); + bool ni = BUILTIN_CLASS_F64(x, CLASS_PZER|CLASS_PSUB|CLASS_PNOR) & yin; + rr = (ni | xn) ? QNAN_F64 : rr; + ri = ni ? QNAN_F64 : ri; + ri = (BUILTIN_ISINF_F64(x) & yin) ? 0.0 : ri; + ri = (xn & (z.y == 0.0)) ? z.y : ri; + } + + return (double2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/ctanhF.cl b/amd/device-libs/ocml/src/ctanhF.cl new file mode 100644 index 0000000000000..f9a6a7209caf3 --- /dev/null +++ b/amd/device-libs/ocml/src/ctanhF.cl @@ -0,0 +1,54 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float2 MATH_PRIVATE(epexpep)(float2 z); + +CONSTATTR float2 +MATH_MANGLE(ctanh)(float2 z) +{ + float cy; + float sy = MATH_MANGLE(sincos)(z.y, &cy); + float cysy = cy*sy; + float x = BUILTIN_ABS_F32(z.x); + + float rr, ri; + if (x < 0x1.3687aap+3f) { + float2 e = MATH_PRIVATE(epexpep)(sub(x, con(0x1.62e430p-1, -0x1.05c610p-29f))); + float2 er = rcp(e); + er = ldx(er, -2); + float2 cx = fadd(e, er); + float2 sx = fsub(e, er); + + float cxhi = cx.hi; + float sxhi = x < 0x1.0p-12f ? x : sx.hi; + + float d = MATH_MAD(cy, cy, sxhi*sxhi); + rr = BUILTIN_COPYSIGN_F32(MATH_DIV(cxhi*sxhi, d), z.x); + ri = MATH_DIV(cysy, d); + } else { + rr = BUILTIN_COPYSIGN_F32(1.0f, z.x); + ri = 4.0f * cysy * MATH_MANGLE(exp)(-2.0f * x); + } + + if (!FINITE_ONLY_OPT()) { + bool xn = BUILTIN_ISNAN_F32(x); + bool yin = !BUILTIN_ISFINITE_F32(z.y); + bool ni = BUILTIN_CLASS_F32(x, CLASS_PZER|CLASS_PSUB|CLASS_PNOR) & yin; + rr = (ni | xn) ? QNAN_F32 : rr; + ri = ni ? QNAN_F32 : ri; + ri = (BUILTIN_ISINF_F32(x) & yin) ? 0.0f : ri; + ri = (xn & (z.y == 0.0f)) ? z.y : ri; + } + + return (float2)(rr, ri); +} + diff --git a/amd/device-libs/ocml/src/divD.cl b/amd/device-libs/ocml/src/divD.cl new file mode 100644 index 0000000000000..1e4bd00218902 --- /dev/null +++ b/amd/device-libs/ocml/src/divD.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define GEN(LN,UN) \ +CONSTATTR double \ +MATH_MANGLE(LN)(double x, double y) \ +{ \ + return BUILTIN_##UN##_F64(x, y); \ +} + +// GEN(div_rte,DIV_RTE) +// GEN(div_rtn,DIV_RTN) +// GEN(div_rtp,DIV_RTP) +// GEN(div_rtz,DIV_RTZ) + diff --git a/amd/device-libs/ocml/src/divF.cl b/amd/device-libs/ocml/src/divF.cl new file mode 100644 index 0000000000000..173b7f00caeeb --- /dev/null +++ b/amd/device-libs/ocml/src/divF.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define GEN(LN,UN) \ +CONSTATTR float \ +MATH_MANGLE(LN)(float x, float y) \ +{ \ + return BUILTIN_##UN##_F32(x, y); \ +} + +// GEN(div_rte,DIV_RTE) +// GEN(div_rtn,DIV_RTN) +// GEN(div_rtp,DIV_RTP) +// GEN(div_rtz,DIV_RTZ) + diff --git a/amd/device-libs/ocml/src/divH.cl b/amd/device-libs/ocml/src/divH.cl new file mode 100644 index 0000000000000..011d1f9436b64 --- /dev/null +++ b/amd/device-libs/ocml/src/divH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +#define GEN(LN,UN) \ +CONSTATTR half \ +MATH_MANGLE(LN)(half x, half y) \ +{ \ + return BUILTIN_##UN##_F16(x, y); \ +} + +// GEN(div_rte,DIV_RTE) +// GEN(div_rtn,DIV_RTN) +// GEN(div_rtp,DIV_RTP) +// GEN(div_rtz,DIV_RTZ) + diff --git a/amd/device-libs/ocml/src/ep.h b/amd/device-libs/ocml/src/ep.h new file mode 100644 index 0000000000000..81110624161e7 --- /dev/null +++ b/amd/device-libs/ocml/src/ep.h @@ -0,0 +1,462 @@ + +#define ATTR __attribute__((const, overloadable)) + +#if defined FLOAT_SPECIALIZATION +#define T float +#define T2 float2 +#define FMA BUILTIN_FMA_F32 +#define RCP MATH_FAST_RCP +#define DIV(X,Y) MATH_FAST_DIV(X,Y) +#define LDEXP BUILTIN_FLDEXP_F32 +#define SQRT MATH_FAST_SQRT +#define ISINF(X) BUILTIN_ISINF_F32(X) +#define USE_FMA HAVE_FAST_FMA32() +#define HIGH(X) AS_FLOAT(AS_UINT(X) & 0xfffff000U) +#define SIGNBIT(X) (AS_INT(X) < 0) +#define SAMESIGN(X,Y) ((AS_INT(X)& 0x80000000) == (AS_INT(Y) & 0x80000000)) +#endif + +#if defined DOUBLE_SPECIALIZATION +#define T double +#define T2 double2 +#define FMA BUILTIN_FMA_F64 +#define RCP MATH_FAST_RCP +#define DIV(X,Y) MATH_FAST_DIV(X,Y) +#define LDEXP BUILTIN_FLDEXP_F64 +#define SQRT MATH_FAST_SQRT +#define ISINF(X) BUILTIN_ISINF_F64(X) +#define USE_FMA true +#define HIGH(X) AS_DOUBLE(AS_ULONG(X) & 0xfffffffff8000000UL) +#define SIGNBIT(X) (AS_INT2(X).hi < 0) +#define SAMESIGN(X,Y) ((AS_INT2(X).hi & 0x80000000) == (AS_INT2(Y).hi & 0x80000000)) +#endif + +#if defined HALF_SPECIALIZATION +#define T half +#define T2 half2 +#define FMA BUILTIN_FMA_F16 +#define RCP MATH_FAST_RCP +#define DIV(X,Y) MATH_FAST_DIV(X,Y) +#define LDEXP BUILTIN_FLDEXP_F16 +#define SQRT MATH_FAST_SQRT +#define ISINF(X) BUILTIN_ISINF_F16(X) +#define USE_FMA true +#define HIGH(X) AS_HALF(AS_USHORT(X) & (ushort)0xffc0U) +#define SIGNBIT(X) (AS_SHORT(X) < (short)0) +#define SAMESIGN(X,Y) ((AS_USHORT(X) & (ushort)0x8000) == (AS_USHORT(Y) & (ushort)0x8000)) +#endif + +static ATTR T2 +absv(T2 a) +{ + return SIGNBIT(a.hi) ? -a : a; +} + +static ATTR T2 +csgn(T2 a, T2 b) +{ + return SAMESIGN(a.hi, b.hi) ? a : -a; +} + +static ATTR T2 +con(T a, T b) +{ + return (T2)(b, a); +} + +static ATTR T2 +fadd(T a, T b) +{ + T s = a + b; + return con(s, b - (s - a)); +} + +static ATTR T2 +nrm(T2 a) +{ + return fadd(a.hi, a.lo); +} + +static ATTR T2 +onrm(T2 a) +{ + T s = a.hi + a.lo; + T t = a.lo - (s - a.hi); + s = ISINF(a.hi) ? a.hi : s; + return con(s, ISINF(s) ? (T)0 : t); +} + +static ATTR T2 +fsub(T a, T b) +{ + T d = a - b; + return con(d, (a - d) - b); +} + +static ATTR T2 +add(T a, T b) +{ + T s = a + b; + T d = s - a; + return con(s, (a - (s - d)) + (b - d)); +} + +static ATTR T2 +sub(T a, T b) +{ + T d = a - b; + T e = d - a; + return con(d, (a - (d - e)) - (b + e)); +} + +static ATTR T2 +mul(T a, T b) +{ + T p = a * b; + if (USE_FMA) { + return con(p, FMA(a, b, -p)); + } else { + T ah = HIGH(a); + T al = a - ah; + T bh = HIGH(b); + T bl = b - bh; + T p = a * b; + return con(p, ((ah*bh - p) + ah*bl + al*bh) + al*bl); + } +} + +static ATTR T2 +sqr(T a) +{ + T p = a * a; + if (USE_FMA) { + return con(p, FMA(a, a, -p)); + } else { + T ah = HIGH(a); + T al = a - ah; + return con(p, ((ah*ah - p) + 2.0f*ah*al) + al*al); + } +} + +static ATTR T2 +add(T2 a, T b) +{ + T2 s = add(a.hi, b); + s.lo += a.lo; + return nrm(s); +} + +static ATTR T2 +fadd(T2 a, T b) +{ + T2 s = fadd(a.hi, b); + s.lo += a.lo; + return nrm(s); +} + +static ATTR T2 +add(T a, T2 b) +{ + T2 s = add(a, b.hi); + s.lo += b.lo; + return nrm(s); +} + +static ATTR T2 +fadd(T a, T2 b) +{ + T2 s = fadd(a, b.hi); + s.lo += b.lo; + return nrm(s); +} + +static ATTR T2 +add(T2 a, T2 b) +{ + T2 s = add(a.hi, b.hi); + T2 t = add(a.lo, b.lo); + s.lo += t.hi; + s = nrm(s); + s.lo += t.lo; + return nrm(s); +} + +static ATTR T2 +fadd(T2 a, T2 b) +{ + T2 s = fadd(a.hi, b.hi); + s.lo += a.lo + b.lo; + return nrm(s); +} + +static ATTR T2 +sub(T2 a, T b) +{ + T2 d = sub(a.hi, b); + d.lo += a.lo; + return nrm(d); +} + +static ATTR T2 +fsub(T2 a, T b) +{ + T2 d = fsub(a.hi, b); + d.lo += a.lo; + return nrm(d); +} + +static ATTR T2 +sub(T a, T2 b) +{ + T2 d = sub(a, b.hi); + d.lo -= b.lo; + return nrm(d); +} + +static ATTR T2 +fsub(T a, T2 b) +{ + T2 d = fsub(a, b.hi); + d.lo -= b.lo; + return nrm(d); +} + +static ATTR T2 +sub(T2 a, T2 b) +{ + T2 d = sub(a.hi, b.hi); + T2 e = sub(a.lo, b.lo); + d.lo += e.hi; + d = nrm(d); + d.lo += e.lo; + return nrm(d); +} + +static ATTR T2 +fsub(T2 a, T2 b) +{ + T2 d = fsub(a.hi, b.hi); + d.lo = d.lo + a.lo - b.lo; + return nrm(d); +} + +static ATTR T2 +ldx(T2 a, int e) +{ + return con(LDEXP(a.hi, e), LDEXP(a.lo, e)); +} + +static ATTR T2 +mul(T2 a, T b) +{ + T2 p = mul(a.hi, b); + if (USE_FMA) { + p.lo = FMA(a.lo, b, p.lo); + } else { + p.lo += a.lo * b; + } + return nrm(p); +} + +static ATTR T2 +omul(T2 a, T b) +{ + T2 p = mul(a.hi, b); + if (USE_FMA) { + p.lo = FMA(a.lo, b, p.lo); + } else { + p.lo += a.lo * b; + } + return onrm(p); +} + +static ATTR T2 +mul(T a, T2 b) +{ + T2 p = mul(a, b.hi); + if (USE_FMA) { + p.lo = FMA(a, b.lo, p.lo); + } else { + p.lo += a * b.lo; + } + return nrm(p); +} + +static ATTR T2 +omul(T a, T2 b) +{ + T2 p = mul(a, b.hi); + if (USE_FMA) { + p.lo = FMA(a, b.lo, p.lo); + } else { + p.lo += a * b.lo; + } + return onrm(p); +} + +static ATTR T2 +mul(T2 a, T2 b) +{ + T2 p = mul(a.hi, b.hi); + if (USE_FMA) { + p.lo = FMA(a.lo, b.hi, FMA(a.hi, b.lo, p.lo)); + } else { + p.lo += a.hi*b.lo + a.lo*b.hi; + } + return nrm(p); +} + +static ATTR T2 +omul(T2 a, T2 b) +{ + T2 p = mul(a.hi, b.hi); + if (USE_FMA) { + p.lo += FMA(a.hi, b.lo, a.lo*b.hi); + } else { + p.lo += a.hi*b.lo + a.lo*b.hi; + } + return onrm(p); +} + +static ATTR T2 +div(T a, T b) +{ + T r = RCP(b); + T qhi = a * r; + T2 p = mul(qhi, b); + T2 d = fsub(a, p.hi); + d.lo -= p.lo; + T qlo = (d.hi + d.lo) * r; + return fadd(qhi, qlo); +} + +static ATTR T2 +div(T2 a, T b) +{ + T r = RCP(b); + T qhi = a.hi * r; + T2 p = mul(qhi, b); + T2 d = fsub(a.hi, p.hi); + d.lo = d.lo + a.lo - p.lo; + T qlo = (d.hi + d.lo) * r; + return fadd(qhi, qlo); +} + +static ATTR T2 +div(T a, T2 b) +{ + T r = RCP(b.hi); + T qhi = a * r; + T2 p = mul(qhi, b); + T2 d = fsub(a, p.hi); + d.lo -= p.lo; + T qlo = (d.hi + d.lo) * r; + return fadd(qhi, qlo); +} + +static ATTR T2 +fdiv(T2 a, T2 b) +{ + T r = RCP(b.hi); + T qhi = a.hi * r; + T2 p = mul(qhi, b); + T2 d = fsub(a.hi, p.hi); + d.lo = d.lo - p.lo + a.lo; + T qlo = (d.hi + d.lo) * r; + return fadd(qhi, qlo); +} + +static ATTR T2 +div(T2 a, T2 b) +{ + T y = RCP(b.hi); + T qhi = a.hi * y; + T2 r = fsub(a, mul(qhi, b)); + T qmi = r.hi * y; + r = fsub(r, mul(qmi, b)); + T qlo = r.hi * y; + T2 q = fadd(qhi, qmi); + q.lo += qlo; + return nrm(q); +} + +static ATTR T2 +rcp(T b) +{ + T qhi = RCP(b); + T2 p = mul(qhi, b); + T2 d = fsub((T)1, p.hi); + d.lo -= p.lo; + T qlo = (d.hi + d.lo) * qhi; + return fadd(qhi, qlo); +} + +static ATTR T2 +frcp(T2 b) +{ + T qhi = RCP(b.hi); + T2 p = mul(qhi, b); + T2 d = fsub((T)1, p.hi); + d.lo -= p.lo; + T qlo = (d.hi + d.lo) * qhi; + return fadd(qhi, qlo); +} + +static ATTR T2 +rcp(T2 b) +{ + T qhi = RCP(b.hi); + T2 r = fsub((T)1, mul(qhi, b)); + T qmi = r.hi * qhi; + r = fsub(r, mul(qmi, b)); + T qlo = r.hi * qhi; + T2 q = fadd(qhi, qmi); + q.lo += qlo; + return nrm(q); +} + +static ATTR T2 +sqr(T2 a) +{ + T2 p = sqr(a.hi); + if (USE_FMA) { + p.lo = FMA(a.hi, (T)2 * a.lo, p.lo); + } else { + p.lo = p.lo + (T)2 * a.lo * a.hi; + } + return nrm(p); +} + +static ATTR T2 +root2(T a) +{ + T shi = SQRT(a); + T2 e = fsub(a, sqr(shi)); + T slo = DIV(e.hi, (T)2 * shi); + return fadd(shi, a == (T)0 ? (T)0 : slo); +} + +static ATTR T2 +root2(T2 a) +{ + T shi = SQRT(a.hi); + T2 e = fsub(a, sqr(shi)); + T slo = DIV(e.hi, (T)2 * shi); + return fadd(shi, a.hi == (T)0 ? (T)0 : slo); +} + +#undef ATTR +#undef T +#undef T2 +#undef FMA +#undef RCP +#undef DIV +#undef LDEXP +#undef SQRT +#undef ISINF +#undef USE_FMA +#undef HIGH +#undef COPYSIGN +#undef SIGNBIT +#undef SAMESIGN + diff --git a/amd/device-libs/ocml/src/epcsqrtepD.cl b/amd/device-libs/ocml/src/epcsqrtepD.cl new file mode 100644 index 0000000000000..ce95a7f9328a9 --- /dev/null +++ b/amd/device-libs/ocml/src/epcsqrtepD.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double4 +MATH_PRIVATE(epcsqrtep)(double4 z) +{ + double2 x = z.lo; + double2 y = z.hi; + double2 u = root2(fadd(root2(add(sqr(x), sqr(y))), absv(x)) * 0.5); + double2 v = absv(fdiv(y, u) * 0.5); + v = ((y.hi == 0.0) & (u.hi == 0.0)) ? y : v; + bool b = x.hi >= 0.0; + double2 s = b ? u : v; + double2 t = csgn(b ? v : u, y); + return (double4)(s, t); +} + diff --git a/amd/device-libs/ocml/src/epcsqrtepF.cl b/amd/device-libs/ocml/src/epcsqrtepF.cl new file mode 100644 index 0000000000000..d8dcbd351d76d --- /dev/null +++ b/amd/device-libs/ocml/src/epcsqrtepF.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +CONSTATTR float4 +MATH_PRIVATE(epcsqrtep)(float4 z) +{ + float2 x = z.lo; + float2 y = z.hi; + float2 u = root2(fadd(root2(add(sqr(x), sqr(y))), absv(x)) * 0.5f); + float2 v = absv(fdiv(y, u) * 0.5f); + v = ((y.hi == 0.0f) & (u.hi == 0.0f)) ? y : v; + bool b = x.hi >= 0.0f; + float2 s = b ? u : v; + float2 t = csgn(b ? v : u, y); + return (float4)(s, t); +} + diff --git a/amd/device-libs/ocml/src/epexpepD.cl b/amd/device-libs/ocml/src/epexpepD.cl new file mode 100644 index 0000000000000..f6340e15bf1e8 --- /dev/null +++ b/amd/device-libs/ocml/src/epexpepD.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double2 +MATH_PRIVATE(epexpep)(double2 x) +{ + double dn = BUILTIN_RINT_F64(x.hi * 0x1.71547652b82fep+0); + double2 t = fsub(fsub(fadd(MATH_MAD(dn, -0x1.62e42fefa3000p-1, x.hi), x.lo), dn*0x1.3de6af278e000p-42), dn*0x1.9cc01f97b57a0p-83); + + double th = t.hi; + double p = MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, + MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, + MATH_MAD(th, + 0x1.ade156a5dcb37p-26, 0x1.28af3fca7ab0cp-22), 0x1.71dee623fde64p-19), 0x1.a01997c89e6b0p-16), + 0x1.a01a014761f6ep-13), 0x1.6c16c1852b7b0p-10), 0x1.1111111122322p-7), 0x1.55555555502a1p-5), + 0x1.5555555555511p-3), 0x1.000000000000bp-1); + + double2 r = fadd(1.0, fadd(t, mul(sqr(t), p))); + + return ldx(r, (int)dn); +} + diff --git a/amd/device-libs/ocml/src/epexpepF.cl b/amd/device-libs/ocml/src/epexpepF.cl new file mode 100644 index 0000000000000..1ba48e10cad9b --- /dev/null +++ b/amd/device-libs/ocml/src/epexpepF.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +CONSTATTR float2 +MATH_PRIVATE(epexpep)(float2 x) +{ + float fn = BUILTIN_RINT_F32(x.hi * 0x1.715476p+0f); + float2 t = fsub(fsub(fadd(MATH_MAD(fn, -0x1.62e400p-1f, x.hi), x.lo), fn*0x1.7f7800p-20f), fn*0x1.473de6p-34f); + + float th = t.hi; + float p = MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, + 0x1.6850e4p-10f, 0x1.123bccp-7f), 0x1.555b98p-5f), 0x1.55548ep-3f), + 0x1.fffff8p-2f); + + float2 r = fadd(1.0f, fadd(t, mul(sqr(t), p))); + + return ldx(r, (int)fn); +} + diff --git a/amd/device-libs/ocml/src/eplnD.cl b/amd/device-libs/ocml/src/eplnD.cl new file mode 100644 index 0000000000000..c69847778d957 --- /dev/null +++ b/amd/device-libs/ocml/src/eplnD.cl @@ -0,0 +1,39 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double2 +MATH_PRIVATE(epln)(double a) +{ + double m = BUILTIN_FREXP_MANT_F64(a); + int b = m < (2.0/3.0); + m = BUILTIN_FLDEXP_F64(m, b); + int e = BUILTIN_FREXP_EXP_F64(a) - b; + + double2 x = div(m - 1.0, fadd(1.0, m)); + double2 s = sqr(x); + double t = s.hi; + double p = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.dee674222de17p-4, 0x1.a6564968915a9p-4), 0x1.e25e43abe935ap-4), 0x1.110ef47e6c9c2p-3), + 0x1.3b13bcfa74449p-3), 0x1.745d171bf3c30p-3), 0x1.c71c71c7792cep-3), 0x1.24924924920dap-2), + 0x1.999999999999cp-2); + + // ln(2)*e + 2*x + x^3(c3 + x^2*p) + double2 r = add(mul(con(0x1.62e42fefa39efp-1, 0x1.abc9e3b39803fp-56), (double)e), + fadd(ldx(x,1), + mul(mul(s, x), + fadd(con(0x1.5555555555555p-1,0x1.543b0d5df274dp-55), + mul(s, p))))); + + return r; +} + diff --git a/amd/device-libs/ocml/src/eplnF.cl b/amd/device-libs/ocml/src/eplnF.cl new file mode 100644 index 0000000000000..3c2bc177ff3ef --- /dev/null +++ b/amd/device-libs/ocml/src/eplnF.cl @@ -0,0 +1,35 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +CONSTATTR float2 +MATH_PRIVATE(epln)(float a) +{ + float m = BUILTIN_FREXP_MANT_F32(a); + int b = m < (2.0f/3.0f); + m = BUILTIN_FLDEXP_F32(m, b); + int e = BUILTIN_FREXP_EXP_F32(a) - b; + + float2 x = div(m - 1.0f, fadd(1.0f, m)); + float2 s = sqr(x); + float t = s.hi; + float p = MATH_MAD(t, MATH_MAD(t, 0x1.ed89c2p-3f, 0x1.23e988p-2f), 0x1.999bdep-2f); + + // ln(2)*e + 2*x + x^3(c3 + x^2*p) + float2 r = add(mul(con(0x1.62e430p-1f, -0x1.05c610p-29f), (float)e), + fadd(ldx(x,1), + mul(mul(s, x), + fadd(con(0x1.555554p-1f,0x1.e72020p-29f), + mul(s, p))))); + + return r; +} + diff --git a/amd/device-libs/ocml/src/erfD.cl b/amd/device-libs/ocml/src/erfD.cl new file mode 100644 index 0000000000000..e88f4ab8082c1 --- /dev/null +++ b/amd/device-libs/ocml/src/erfD.cl @@ -0,0 +1,54 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(erf)(double x) +{ + double ax = BUILTIN_ABS_F64(x); + double ret; + + if (ax < 1.0) { + double t = ax * ax; + double p = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.ab15c51d2ebebp-31, 0x1.d6e3ddfeb1f49p-27), + -0x1.5bfe76384472p-23), 0x1.b97e44280cfb9p-20), + -0x1.f4ca204c771c5p-17), 0x1.f9a2b75531772p-14), + -0x1.c02db0149d904p-11), 0x1.565bccf7e2856p-8), + -0x1.b82ce311ee09bp-6), 0x1.ce2f21a0408d1p-4), + -0x1.812746b0379b2p-2), 0x1.06eba8214db68p-3); + ret = MATH_MAD(ax, p, ax); + } else { + double p = MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + MATH_MAD(ax, MATH_MAD(ax, + 0x1.98d37c14b24bep-58, -0x1.145a3502a41cdp-51), + 0x1.62deed735f9ecp-46), -0x1.1ffe55552ca22p-41), + 0x1.4b9ba7074b644p-37), -0x1.20345a78ce24p-33), + 0x1.88b7a0cefddd8p-30), -0x1.aded48c94b617p-27), + 0x1.803aa312306dp-24), -0x1.1b0106f4c5a9bp-21), + 0x1.58c0e7cfd79aep-19), -0x1.59e386410fdf7p-17), + 0x1.192fc1f9b1786p-15), -0x1.62cf3f4634b2ep-14), + 0x1.314dfb42f7e4bp-13), -0x1.2cb68c047288ap-14), + -0x1.038ff7bbcce25p-11), 0x1.a9466ae1babaep-10), + -0x1.58be1e65a6063p-13), -0x1.39bc16738ee3ap-6), + 0x1.a4fbc28146b69p-4), 0x1.45f2da69750c4p-1), + 0x1.06ebb919fcca8p-3); + p = MATH_MAD(ax, p, ax); + ret = 1.0 - MATH_MANGLE(exp)(-p); + } + + ret = BUILTIN_COPYSIGN_F64(ret, x); + return ret; +} + diff --git a/amd/device-libs/ocml/src/erfF.cl b/amd/device-libs/ocml/src/erfF.cl new file mode 100644 index 0000000000000..9358a7d670516 --- /dev/null +++ b/amd/device-libs/ocml/src/erfF.cl @@ -0,0 +1,35 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(erf)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + float ret; + + if (ax < 1.0f) { + float t = ax*ax; + float p = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + -0x1.268bc2p-11f, 0x1.420828p-8f), -0x1.b5937p-6f), 0x1.ce077cp-4f), + -0x1.81266p-2f), 0x1.06eba0p-3f); + ret = BUILTIN_FMA_F32(ax, p, ax); + } else { + float p = MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + MATH_MAD(ax, MATH_MAD(ax, + 0x1.1d3156p-16f, -0x1.8d129p-12f), 0x1.f9a6d2p-9f), -0x1.8c3164p-6f), + 0x1.b4e9c8p-4f), 0x1.4515fap-1f), 0x1.078e50p-3f); + p = BUILTIN_FMA_F32(ax, p, ax); + ret = 1.0f - MATH_MANGLE(exp)(-p); + } + + ret = BUILTIN_COPYSIGN_F32(ret, x); + return ret; +} + diff --git a/amd/device-libs/ocml/src/erfH.cl b/amd/device-libs/ocml/src/erfH.cl new file mode 100644 index 0000000000000..b9af4e0ee4a0f --- /dev/null +++ b/amd/device-libs/ocml/src/erfH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(erf) + +CONSTATTR half +MATH_MANGLE(erf)(half x) +{ + return (half)MATH_UPMANGLE(erf)((float)x); +} + diff --git a/amd/device-libs/ocml/src/erfcD.cl b/amd/device-libs/ocml/src/erfcD.cl new file mode 100644 index 0000000000000..d5fceb18ef92b --- /dev/null +++ b/amd/device-libs/ocml/src/erfcD.cl @@ -0,0 +1,263 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#if !defined EXTRA_ACCURACY +CONSTATTR extern double MATH_PRIVATE(erfcx)(double); + +CONSTATTR double +MATH_MANGLE(erfc)(double x) +{ + double ax = BUILTIN_ABS_F64(x); + double x2h = -x*x; + double x2l = MATH_MAD(-x, x, -x2h); + double e = MATH_MANGLE(exp)(x2h); + e = MATH_MAD(e, x2l, e); + double ret = e * MATH_PRIVATE(erfcx)(ax); + ret = ax > 0x1.b39dc41e48bfcp+4 ? 0.0f : ret; + double nret = 2.0 - ret; + return x < 0.0 ? nret : ret; +} + +#else + +// Partially based on ideas from the Sun implementation +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunPro, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + */ + +/* double erf(double x) + * double erfc(double x) + * x + * 2 |\ + * erf(x) = --------- | exp(-t*t)dt + * sqrt(pi) \| + * 0 + * + * erfc(x) = 1-erf(x) + * Note that + * erf(-x) = -erf(x) + * erfc(-x) = 2 - erfc(x) + * + * Method: + * 1. For |x| in [0, 0.84375] + * erf(x) = x + x*R(x^2) + * erfc(x) = 1 - erf(x) if x in [-.84375,0.25] + * = 0.5 + ((0.5-x)-x*R) if x in [0.25,0.84375] + * where R = P/Q where P is an odd poly of degree 8 and + * Q is an odd poly of degree 10. + * -57.90 + * | R - (erf(x)-x)/x | <= 2 + * + * + * Remark. The formula is derived by noting + * erf(x) = (2/sqrt(pi))*(x - x^3/3 + x^5/10 - x^7/42 + ....) + * and that + * 2/sqrt(pi) = 1.128379167095512573896158903121545171688 + * is close to one. The interval is chosen because the fix + * point of erf(x) is near 0.6174 (i.e., erf(x)=x when x is + * near 0.6174), and by some experiment, 0.84375 is chosen to + * guarantee the error is less than one ulp for erf. + * + * 2. For |x| in [0.84375,1.25], let s = |x| - 1, and + * c = 0.84506291151 rounded to single (24 bits) + * erf(x) = sign(x) * (c + P1(s)/Q1(s)) + * erfc(x) = (1-c) - P1(s)/Q1(s) if x > 0 + * 1+(c+P1(s)/Q1(s)) if x < 0 + * |P1/Q1 - (erf(|x|)-c)| <= 2**-59.06 + * Remark: here we use the taylor series expansion at x=1. + * erf(1+s) = erf(1) + s*Poly(s) + * = 0.845.. + P1(s)/Q1(s) + * That is, we use rational approximation to approximate + * erf(1+s) - (c = (single)0.84506291151) + * Note that |P1/Q1|< 0.078 for x in [0.84375,1.25] + * where + * P1(s) = degree 6 poly in s + * Q1(s) = degree 6 poly in s + * + * 3. For x in [1.25,1/0.35(~2.857143)], + * erfc(x) = (1/x)*exp(-x*x-0.5625+R1/S1) + * erf(x) = 1 - erfc(x) + * where + * R1(z) = degree 7 poly in z, (z=1/x^2) + * S1(z) = degree 8 poly in z + * + * 4. For x in [1/0.35,28] + * erfc(x) = (1/x)*exp(-x*x-0.5625+R2/S2) if x > 0 + * = 2.0 - (1/x)*exp(-x*x-0.5625+R2/S2) if -6 x >= 28 + * erf(x) = sign(x) *(1 - tiny) (raise inexact) + * erfc(x) = tiny*tiny (raise underflow) if x > 0 + * = 2 - tiny if x<0 + * + * 7. Special case: + * erf(0) = 0, erf(inf) = 1, erf(-inf) = -1, + * erfc(0) = 1, erfc(inf) = 0, erfc(-inf) = 2, + * erfc/erf(NaN) is NaN + */ + +CONSTATTR double +MATH_MANGLE(erfc)(double x) +{ + double ret; + + if (x < 0x1.e861fbb24c00ap-2) { + if (x > -1.0) { + double t = x * x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.abae491c443a9p-31, 0x1.d71b0f1b10a64p-27), -0x1.5c0726f04dcfbp-23), 0x1.b97fd3d992938p-20), + -0x1.f4ca4d6f3e30fp-17), 0x1.f9a2baa8fedd2p-14), -0x1.c02db03dd71d4p-11), 0x1.565bccf92b2f9p-8), + -0x1.b82ce311fa93ep-6), 0x1.ce2f21a040d16p-4), -0x1.812746b0379bdp-2), 0x1.20dd750429b6dp+0); + ret = MATH_MAD(-x, ret, 1.0); + } else if (x > -1.75) { + double t = -x - 1.0; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.6c922ed03eb9dp-17, 0x1.97d42571bbb38p-14), -0x1.41761e0138c87p-12), 0x1.7f635425509dep-13), + 0x1.30fe6b148c32fp-10), -0x1.e682366d34981p-10), -0x1.39b7dcc1aeec8p-8), 0x1.f0ab5db978c52p-7), + 0x1.2e3e92d3304b4p-8), -0x1.1b613d8e18405p-4), 0x1.1b614a01845b4p-4), 0x1.1b614b15ab5c1p-3), + -0x1.a911f0970fc8dp-2), 0x1.a911f096fbf43p-2), 0x1.d7bb3d3a08445p+0); + } else if (x > -2.5) { + double t = -x - 1.75; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.1f145e2e90ae8p-18, -0x1.04595429d0b58p-15), 0x1.566284cadc629p-14), -0x1.daefe4f2fa8e2p-17), + -0x1.cbee5eda62503p-12), 0x1.d416c2aa2275ap-11), 0x1.7eeb86b197684p-11), -0x1.8d11b66138741p-8), + 0x1.25b37e361d1c9p-7), 0x1.b22258f45515dp-8), -0x1.8a0da54b7e9dep-5), 0x1.7148c3d5d2293p-4), + -0x1.7a4a8a2bdfeb2p-4), 0x1.b05530322115bp-5), 0x1.fc9683bfc6ab7p+0); + } else if (x > -4.0) { + double t = -x - 2.5; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.708f6d0e65c33p-32, 0x1.dbd0618847c60p-28), -0x1.c3001cf83cd69p-26), -0x1.4dca746dfe625p-22), + 0x1.a8e79a95d6f67p-20), 0x1.8d8d7711fc864p-16), -0x1.99fe2d9d9b69bp-13), -0x1.b3b1f1e28669cp-12), + 0x1.01d3d83753fb1p-7), -0x1.e842cf8341e6ap-10), -0x1.a49bb4ab1d7d9p-3), 0x1.3a50e1b16e339p-1); + ret = ret*ret; + ret = ret*ret; + ret = ret*ret; + ret = MATH_MAD(-ret, ret, 2.0); + } else if (x > -5.9375) { + double t = -x - 4.0; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + 0x1.5b22d2cd54932p-26, -0x1.3e056a1040a29p-24), -0x1.2d8f6bf8af04ap-19), 0x1.4c20d337a4541p-16), + 0x1.d9d0971c8f96dp-16), -0x1.0a33e01adb0ddp-10), 0x1.63716fb40eab9p-9), 0x1.7d6f6bbcfc7e0p-6), + -0x1.5687476feec74p-3), 0x1.4cb2bacd30820p-2); + ret = ret*ret; + ret = ret*ret; + ret = ret*ret; + ret = MATH_MAD(-ret, ret, 2.0); + } else { + ret = 2.0; + } + } else { + if (x < 1.0) { + double t = x - 0.75; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.57d59f658aba7p-16, 0x1.362e0b222318ep-14), 0x1.bc4dcd34fdd6dp-14), -0x1.470d403e0efe6p-11), + -0x1.86196ce26e31fp-13), 0x1.0410341ee1473p-8), -0x1.2db338db4ad88p-9), -0x1.2e0afac283b7fp-6), + 0x1.b847796a479d8p-6), 0x1.b42a1890465d3p-5), -0x1.349b5eaa155b6p-3), -0x1.b6e8591f65270p-6), + 0x1.edc5644353c2dp-2), -0x1.492e42d78d2c5p-1), 0x1.27c6d14c5e341p-2); + } else if (x < 1.5) { + double t = x - 1.25; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.9c25dae26e5a8p-18, 0x1.692456873fac4p-19), -0x1.d3ef7e77785bap-15), 0x1.baaa993d5590fp-15), + 0x1.53b075bbc5b61p-12), -0x1.a00787b6af397p-11), -0x1.cc224fab0d8a4p-11), 0x1.75672d1e80999p-8), + -0x1.db43c97b37ceap-9), -0x1.5d0003afa1e92p-6), 0x1.8281ce0b36c0dp-5), 0x1.93a9a7bb80513p-8), + -0x1.571d01c5c56c8p-3), 0x1.2ebf3dcc9f22fp-2), -0x1.e4652fadcb6b2p-3), 0x1.3bcd133aa0ffcp-4); + } else if (x < 1.75) { + double t = x - 1.625; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.02ad00dd8cbb4p-13, 0x1.70ffb4c1c5cbfp-12), -0x1.71c6788c68de8p-10), 0x1.2e4d6f91e46c7p-11), + 0x1.954aa9df71457p-8), -0x1.d857f3fbcac79p-7), 0x1.17d430d63aaf5p-9), 0x1.974c0368aecfcp-5), + -0x1.d6631e1a2977fp-4), 0x1.0bcfca219477bp-3), -0x1.499d478bca733p-4), 0x1.612d893085125p-6); + } else if (x < 27.21875) { + double t = MATH_RCP(x*x); + + if (x < 2.75) + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.ee796b0cccbebp+11, -0x1.f287322c462d4p+13), 0x1.d9e0700d3d82dp+14), -0x1.1a96768b6b29fp+15), + 0x1.dafa2508a60dcp+14), -0x1.2bbd8e3460b89p+14), 0x1.27fd8cab24e6ep+13), -0x1.d7a7a4e4c3b93p+11), + 0x1.37a4a4d018456p+10), -0x1.60173b9f73257p+8), 0x1.6253e7ca4b16fp+6), -0x1.51d02c514c31cp+4), + 0x1.4e9a1546b2716p+2), -0x1.86ed776e3a5e5p+0), 0x1.3fb9e1ef8c40ap-1), -0x1.fffcb9ff22596p-2), + -0x1.43424dfcdbdcep-7); + else + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.bba05f5648454p+38, -0x1.401ff919f9865p+39), 0x1.b23350c3b39a1p+38), -0x1.70d6cf6eca08ep+37), + 0x1.b9e665656eee6p+35), -0x1.8f73b118a9b93p+33), 0x1.1da829fcea796p+31), -0x1.5090992846e0ep+28), + 0x1.548adac0440f5p+25), -0x1.3694e9079941ep+22), 0x1.0e5ce4af6bb84p+19), -0x1.dda4fee0ea545p+15), + 0x1.c3f3a46f6fac8p+12), -0x1.dc5f4d89f0ae7p+9), 0x1.1f825da9dcbacp+7), -0x1.98193f7900492p+4), + 0x1.60fffd6b1743dp+2), -0x1.8aaaaa9e2e8dep+0), 0x1.3fffffffedba9p-1), -0x1.fffffffffff1fp-2), + -0x1.4341239e86f47p-7); + + double xh = AS_DOUBLE(AS_LONG(x) & 0xffffffff00000000L); + ret = MATH_DIV(MATH_MANGLE(exp)(MATH_MAD(x - xh, -(x + xh), ret)), x) * + MATH_MANGLE(exp)(MATH_MAD(xh, -xh, -0.5625)); + } else { + ret = BUILTIN_ISNAN_F64(x) ? x : 0.0; + } + } + + return ret; +} + +#endif diff --git a/amd/device-libs/ocml/src/erfcF.cl b/amd/device-libs/ocml/src/erfcF.cl new file mode 100644 index 0000000000000..00379aad0a4f9 --- /dev/null +++ b/amd/device-libs/ocml/src/erfcF.cl @@ -0,0 +1,117 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#if !defined EXTRA_ACCURACY +CONSTATTR extern float MATH_PRIVATE(erfcx)(float); + +CONSTATTR float +MATH_MANGLE(erfc)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + float x2h = -x*x; + float x2l = BUILTIN_FMA_F32(-x, x, -x2h); + float e = MATH_MANGLE(exp)(x2h); + e = BUILTIN_FMA_F32(e, x2l, e); + float ret = e * MATH_PRIVATE(erfcx)(ax); + ret = ax > 0x1.41bbf8p+3f ? 0.0f : ret; + float nret = 2.0f - ret; + return x < 0.0f ? nret : ret; +} + +#else + +// Some of this implementation is based on ideas from Sun LLVM +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunPro, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + */ + +CONSTATTR float +MATH_MANGLE(erfc)(float x) +{ + float ret; + + if (x < 0x1.e861fcp-2f) { + if (x > -1.0f) { + float t = x * x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.496a32p-14f, -0x1.a3f700p-11f), 0x1.5405b2p-8f), -0x1.b7f90ep-6f), + 0x1.ce2cf8p-4f), -0x1.81273ep-2f), 0x1.20dd74p+0f), + ret = MATH_MAD(-x, ret, 1.0f); + } else if (x > -2.0f) { + float t = -x - 1.0f; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.e72c84p-9f, 0x1.fe43a0p-6f), -0x1.6c8eecp-4f), 0x1.3db6cep-4f), + 0x1.1760e0p-3f), -0x1.a8d6d0p-2f), 0x1.a90f56p-2f), 0x1.d7bb3ep+0f); + } else if (x > -3.74609375f) { + float t = -x - 2.0f; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + -0x1.19665ap-13f, -0x1.d8e18ap-14f), 0x1.13b7c0p-7f), -0x1.cf36a8p-7f), + -0x1.9460fap-3f), 0x1.6e23c8p-1f); + ret = ret*ret; + ret = ret*ret; + ret = ret*ret; + ret = MATH_MAD(-ret, ret, 2.0f); + } else { + return 2.0f; + } + } else { + if (x < 1.0f) { + float t = x - 0.75f; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.b3ca9ap-6f, 0x1.a27606p-5f), -0x1.3489bcp-3f), -0x1.b5b5f0p-6f), + 0x1.edc50cp-2f), -0x1.492e58p-1f), 0x1.27c6d2p-2f); + } else if (x < 1.5f) { + float t = x - 1.25f; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.558b4ep-6f, 0x1.7f4316p-5f), 0x1.9362c6p-8f), -0x1.5716acp-3f), + 0x1.2ebf30p-2f), -0x1.e4653cp-3f), 0x1.3bcd14p-4f); + } else if (x < 1.75f) { + float t = x - 1.625f; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.d1cd9cp-7f, 0x1.2d8f6cp-9f), 0x1.9742c6p-5f), -0x1.d66472p-4f), + 0x1.0bcfcep-3f), -0x1.499d46p-4f), 0x1.612d8ap-6f); + } else if (x < 10.0234375f) { + float t = MATH_FAST_RCP(x*x); + + if (x < 2.75f) + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.ecf46ap-1f, -0x1.d8a006p+0f), 0x1.ab72d8p+0f), -0x1.05ed12p+0f), + 0x1.2691fep-1f), -0x1.fd0ddcp-2f), -0x1.45b16ep-7f); + else + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.107a4cp+4f, -0x1.7fa404p+3f), 0x1.22b8c8p+2f), -0x1.7faf0cp+0f), + 0x1.3f746ep-1f), -0x1.fffc90p-2f), -0x1.4341a6p-7f); + + float xh = AS_FLOAT(AS_INT(x) & 0xffffe000); + ret = MATH_FAST_DIV(MATH_MANGLE(exp)(MATH_MAD(xh - x, xh + x, ret)), x) * + MATH_MANGLE(exp)(MATH_MAD(xh, -xh, -0.5625f)); + } else { + ret = BUILTIN_ISNAN_F32(x) ? x : 0.0f; + } + } + + return ret; +} +#endif + diff --git a/amd/device-libs/ocml/src/erfcH.cl b/amd/device-libs/ocml/src/erfcH.cl new file mode 100644 index 0000000000000..15f8348be350d --- /dev/null +++ b/amd/device-libs/ocml/src/erfcH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(erfc) + +CONSTATTR half +MATH_MANGLE(erfc)(half x) +{ + return (half)MATH_UPMANGLE(erfc)((float)x); +} + diff --git a/amd/device-libs/ocml/src/erfcinvD.cl b/amd/device-libs/ocml/src/erfcinvD.cl new file mode 100644 index 0000000000000..0fc466b7ac16b --- /dev/null +++ b/amd/device-libs/ocml/src/erfcinvD.cl @@ -0,0 +1,96 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(erfcinv)(double y) +{ + double ret; + + if (y > 0.625) { + ret = MATH_MANGLE(erfinv)(1.0 - y); + } else if (y > 0x1.0p-10) { + double t = -MATH_MANGLE(log)(y * (2.0 - y)) - 3.125; + + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.1267a785a1166p-69, -0x1.a6581051dd484p-63), 0x1.2b2956fc047a4p-60), 0x1.ad835aed5cc07p-57), + -0x1.25e0612eae68fp-53), 0x1.a0cab63f02a91p-57), 0x1.d9227af501adbp-48), -0x1.6c3ad559a9b4ep-45), + -0x1.6cafa36036318p-44), 0x1.72879641e158fp-39), -0x1.c89d755f7fff8p-37), -0x1.dc51171ddae3ap-35), + 0x1.20f512744ae65p-30), -0x1.1a9e5f4bcfcd8p-28), -0x1.f36ce926b83e8p-26), 0x1.c6b4f6c7cfa1ep-22), + -0x1.6e8a53e0c2026p-20), -0x1.d1d1f7bf4570bp-17), 0x1.879c2a20cc3e2p-13), -0x1.8457694844d14p-11), + -0x1.8b6c33114edadp-8), 0x1.ebd80d9b13e14p-3), 0x1.a755e7c99ae86p+0); + ret = BUILTIN_FMA_F64(-y, ret, ret); + } else { + double s = MATH_SQRT(-MATH_MANGLE(log)(y)); + double t = MATH_RCP(s); + + if (y > 0x1.0p-19) { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.8b3cfc98a5212p+4, -0x1.907bcdab54a4ep+6), 0x1.7659cf8216d7dp+7), -0x1.ac222777f664dp+7), + 0x1.4f2f8e33151acp+7), -0x1.7d7d1eb301c4cp+6), 0x1.48e630c1c77e7p+5), -0x1.c63e7d0e327f6p+3), + 0x1.225b286aeb0dfp+2), -0x1.82a4acc22b05dp+0), -0x1.0a88271680e57p-5), 0x1.001f6acebb122p+0); + } else if (y > 0x1.0p-40) { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.0fdcb40bf066dp+9, -0x1.870ddeaa832dbp+10), 0x1.035c39e0428c4p+11), -0x1.a4d3c54a3ec14p+10), + 0x1.d382aee6efae8p+9), -0x1.79f9e26565bc1p+8), 0x1.d00e058ce9abap+6), -0x1.c7d1e01821eb3p+4), + 0x1.9d930ba7a3111p+2), -0x1.af47941dd2baap+0), -0x1.787ecc823998bp-6), 0x1.000fae5fb73e3p+0); + } else if (y > 0x1.0p-82) { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.c9e5b8e31c18ep+13, -0x1.c866153b1bce6p+14), 0x1.a386b3b4fb25cp+14), -0x1.d7bf378e7b5fbp+13), + 0x1.6b416de0a7a75p+12), -0x1.9757c1cf44e90p+10), 0x1.5b56ededbaa8cp+8), -0x1.da79924b4d155p+5), + 0x1.2ba25315d612bp+3), -0x1.de5808fbd786dp+0), -0x1.04e014b9fc507p-6), 0x1.000788df1c89fp+0); + } else if (y > 0x1.0p-200) { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.ff518aae00301p+18, -0x1.5781ef98c6aa9p+19), 0x1.a9511b21c7715p+18), -0x1.41d8f1455b21ep+17), + 0x1.4d4a3d4025a4cp+15), -0x1.f640fe7077996p+12), 0x1.1faf674f42181p+10), -0x1.080c5cd81d791p+7), + 0x1.c0ae370098ef4p+3), -0x1.08ebd67dc005ap+1), -0x1.5cf3329e72289p-7), 0x1.00035e75f27e2p+0); + } else if (y > 0x1.0p-400) { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.d554f00bf9d81p+20, 0x1.8456711ff3627p+20), -0x1.26c90acc5daafp+19), 0x1.106501cdef815p+17), + -0x1.57a4c95601c04p+14), 0x1.3ca627cbaede6p+11), -0x1.c716e091922fbp+7), 0x1.292f8f6e8bc75p+4), + -0x1.1b469c212bd5fp+1), -0x1.04977fb6d0462p-7), 0x1.0001dc9f52f8ap+0); + } else if (y > 0x1.0p-900) { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.21913925f3a73p+25, 0x1.4aa2fba282b9bp+24), -0x1.5a2a3f9742896p+22), 0x1.b8ee3895772e8p+19), + -0x1.7f2ce0b036be4p+16), 0x1.e62ab1bcbb738p+12), -0x1.e0ed2965d2a06p+8), 0x1.b0c16705263e5p+4), + -0x1.334f9a732ecc7p+1), -0x1.65f60412f9578p-8), 0x1.0000e0bda43b5p+0); + } else { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.e3d70f1fdc7bep+11, 0x1.28d9acd5b9596p+10), -0x1.554c1ce591414p+7), 0x1.15b1e5a1fe7f5p+4), + -0x1.1aa8e6f616c69p+1), -0x1.f6803b3b4d6ccp-8), 0x1.00019ac5bed2ap+0); + } + ret = s * ret; + } + + if (!FINITE_ONLY_OPT()) { + ret = ((y < 0.0) | (y > 2.0)) ? QNAN_F64 : ret; + ret = y == 0.0 ? PINF_F64 : ret; + ret = y == 2.0 ? NINF_F64 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/erfcinvF.cl b/amd/device-libs/ocml/src/erfcinvF.cl new file mode 100644 index 0000000000000..2a953a5b05eac --- /dev/null +++ b/amd/device-libs/ocml/src/erfcinvF.cl @@ -0,0 +1,52 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(erfcinv)(float y) +{ + float ret; + + if (y > 0.625f) { + ret = MATH_MANGLE(erfinv)(1.0f - y); + } else if (y > 0x1.0p-10f) { + float t = -MATH_MANGLE(log)(y * (2.0f - y)) - 3.125f; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.7ee662p-31f, -0x1.3f5a80p-28f), -0x1.b638f0p-26f), 0x1.c9ccc6p-22f), + -0x1.72f8aep-20f), -0x1.d21aa6p-17f), 0x1.87aebcp-13f), -0x1.8455d4p-11f), + -0x1.8b6ca4p-8f), 0x1.ebd80cp-3f), 0x1.a755e8p+0f); + ret = MATH_MAD(-y, ret, ret); + } else { + float s = MATH_FAST_SQRT(-MATH_MANGLE(log)(y)); + float t = MATH_FAST_RCP(s); + + if (y > 0x1.0p-42f) { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.57221ep+0f, 0x1.7f6144p+1f), -0x1.98dd40p+1f), 0x1.2c9066p+1f), + -0x1.3a07eap+0f), -0x1.ba546cp-5f), 0x1.004e66p+0f); + } else { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.649c6ap+4f, 0x1.8fa8fap+4f), -0x1.a112d8p+3f), 0x1.309d98p+2f), + -0x1.919488p+0f), -0x1.c084ecp-6f), 0x1.00143ep+0f); + } + ret = s * ret; + } + + if (!FINITE_ONLY_OPT()) { + ret = ((y < 0.0f) | (y > 2.0f)) ? QNAN_F32 : ret; + ret = y == 0.0f ? PINF_F32 : ret; + ret = y == 2.0f ? NINF_F32 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/erfcinvH.cl b/amd/device-libs/ocml/src/erfcinvH.cl new file mode 100644 index 0000000000000..858f7fc2b7c9b --- /dev/null +++ b/amd/device-libs/ocml/src/erfcinvH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(erfcinv) + +CONSTATTR half +MATH_MANGLE(erfcinv)(half x) +{ + return (half)MATH_UPMANGLE(erfcinv)((float)x); +} + diff --git a/amd/device-libs/ocml/src/erfcxD.cl b/amd/device-libs/ocml/src/erfcxD.cl new file mode 100644 index 0000000000000..ab463d63c3fd5 --- /dev/null +++ b/amd/device-libs/ocml/src/erfcxD.cl @@ -0,0 +1,142 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_PRIVATE(erfcx)(double x) +{ + double n = x - 4.0; + double d = x + 4.0; + double r = MATH_FAST_RCP(d); + double q = n * r; + double e = MATH_MAD(-q, x, MATH_MAD(q + 1.0, -4.0, x)); + q = BUILTIN_FMA_F64(r, e, q); + + double p = MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, + MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, + MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, + MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, + MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, + MATH_MAD(q, + -0x1.1f39d54df3c0ep-27, -0x1.1166337cfa789p-27), + 0x1.b45f1d9802b82p-24), 0x1.d90488a03dcdbp-25), + -0x1.b87b02eba62d8p-21), 0x1.5104ba56e15f1p-22), + 0x1.7f29f71c907dep-18), -0x1.78f5c2cd770fbp-17), + -0x1.995fb76d0a51ap-16), 0x1.3be2ec022d0edp-13), + -0x1.a1deb2fdbf62ep-13), -0x1.8d4ac3689fc43p-11), + 0x1.49c67192d909bp-8), -0x1.09623852ff07p-6), + 0x1.3079edfadea8fp-5), -0x1.0fb06dff6591p-4), + 0x1.7fee004de8f32p-4), -0x1.9ddb23c3dbeb3p-4), + 0x1.16ecefcfa693p-4), 0x1.f7f5df66fb8a3p-7), + -0x1.1df1ad154a2a8p-3), 0x1.dd2c8b74febf8p-3); + + double tx = x + x; + d = 1.0 + tx; + r = MATH_FAST_RCP(d); + q = MATH_MAD(p, r, r); + e = MATH_MAD(-q, tx, 1.0) + (p - q); + q = MATH_MAD(r, e, q); + return q; +} + +#if !defined EXTRA_ACCURACY + +CONSTATTR double +MATH_MANGLE(erfcx)(double x) +{ + double ax = BUILTIN_ABS_F64(x); + double ret; + + if (ax < 0x1.b39dc41e48bfcp+4) { + ret = MATH_PRIVATE(erfcx)(ax); + } else { + double r = MATH_RCP(ax); + double t = r*r; + double p = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -29.53125, 6.5625), -1.875), 0.75), -0.5), 1.0); + ret = 0x1.20dd750429b6dp-1 * r * p; + } + + if (x < 0.0) { + double x2h = x*x; + double x2l = MATH_MAD(x, x, -x2h); + double e = MATH_MANGLE(exp)(x2h); + ret = MATH_MAD(2.0, MATH_MAD(e, x2l, e), -ret); + ret = x < -0x1.aa0f4d2e063cep+4 ? PINF_F64 : ret; + } + + return ret; +} + +#else + +CONSTATTR double +MATH_MANGLE(erfcx)(double x) +{ + double ax = BUILTIN_ABS_F64(x); + double ret; + + if (ax < 1.0) { + ret = MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + 0x1.997339112da12p-29, -0x1.9a1485b7ae337p-27), + 0x1.9548ab4c5bb56p-26), -0x1.2f88b47e02dc3p-24), + 0x1.282114351c39ap-22), -0x1.e533a426aadd7p-21), + 0x1.723131b8ef11ep-19), -0x1.188f6b08d66b9p-17), + 0x1.a00995a561233p-16), -0x1.2aeb04681fed5p-14), + 0x1.a01b9d82bcaa5p-13), -0x1.182d3bb1ac2c8p-11), + 0x1.6c16a932f49d1p-10), -0x1.c74aef6905182p-9), + 0x1.111111f403407p-7), -0x1.390379458257cp-6), + 0x1.5555554b34536p-5), -0x1.6023e8de7793p-4), + 0x1.5555555597342p-3), -0x1.341f6bc020c17p-2), + 0x1.fffffffffe5aep-2), -0x1.812746b037cadp-1), + 0x1.000000000001dp0), -0x1.20dd750429b6ap0), + 0x1.0p0); + } else if (ax < 5120.0) { + double t = MATH_DIV(ax - 4.0, ax + 4.0); + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0.14981549849751462e-8, -0.69954933359042387e-8), + -0.15965692247743744e-7), 0.92967132363414431e-7), + 0.70214215034531004e-7), -0.80204958740421079e-6), + 0.29923810132862422e-6), 0.56895739871851154e-5), + -0.11226090578381133e-4), -0.2438781785281914e-4), + 0.00015062360829881126), -0.00019926094025574419), + -0.00075777387606136804), 0.0050319709983606006), + -0.016197733946788412), 0.037167515387099868), + -0.066330365824435124), 0.093732835010698844), + -0.10103906603561565), 0.068097054254223675), + 0.015379652102604634), -0.13962111684055725), + 1.2329951186255526); + ret = MATH_DIV(ret, MATH_MAD(ax, 2.0, 1.0)); + } else { + const double one_over_sqrtpi = 0x1.20dd750429b6dp-1; + double z = MATH_RCP(x * x); + ret = MATH_DIV(one_over_sqrtpi, x) * MATH_MAD(z, MATH_MAD(z, 0.375, -0.5), 1.0); + } + + if (x <= -1.0) { + double x2h = ax * ax; + double x2l = BUILTIN_FMA_F64(ax, ax, -x2h); + ret = MATH_MANGLE(exp)(x2h) * MATH_MANGLE(exp)(x2l) * 2.0 - ret; + ret = x < -27.0 ? PINF_F64 : ret; + } + + return ret; +} + +#endif + diff --git a/amd/device-libs/ocml/src/erfcxF.cl b/amd/device-libs/ocml/src/erfcxF.cl new file mode 100644 index 0000000000000..eafcdad527e91 --- /dev/null +++ b/amd/device-libs/ocml/src/erfcxF.cl @@ -0,0 +1,117 @@ + +#include "mathF.h" + +CONSTATTR float +MATH_PRIVATE(erfcx)(float x) +{ + float n = x - 2.0f; + float d = x + 2.0f; + float r = MATH_FAST_RCP(d); + float q = n * r; + float e = BUILTIN_FMA_F32(-q, x, BUILTIN_FMA_F32(q + 1.0f, -2.0f, x)); + q = BUILTIN_FMA_F32(r, e, q); + + float p = MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, + MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, MATH_MAD(q, + MATH_MAD(q, + -0x1.adf188p-12f, -0x1.45aea6p-10f), + 0x1.5a5f68p-10f), 0x1.1b44cep-7f), + -0x1.082b62p-7f), -0x1.bc143p-5f), + 0x1.4ffc54p-3f), -0x1.5407fap-3f), + -0x1.7bf616p-4f), 0x1.1ba038p-2); + float tx = x + x; + d = 1.0f + tx; + r = MATH_FAST_RCP(d); + q = BUILTIN_FMA_F32(p, r, r); + e = BUILTIN_FMA_F32(-q, tx, 1.0f) + (p - q); + q = BUILTIN_FMA_F32(r, e, q); + return q; +} + +#if !defined EXTRA_ACCURACY + +CONSTATTR float +MATH_MANGLE(erfcx)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + float ret; + + if (ax < 0x1.41bbf8p+3f) { + ret = MATH_PRIVATE(erfcx)(ax); + } else { + float r = MATH_FAST_RCP(0x1.0p-2f * ax); + float t = r*r * 0x1.0p-4f; + float p = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 6.5625f, -1.875f), 0.75f), -0.5f), 1.0f); + ret = 0x1.20dd76p-3f * r * p; + } + + if (x < 0.0f) { + float x2h = x*x; + float x2l = BUILTIN_FMA_F32(x, x, -x2h); + float e = MATH_MANGLE(exp)(x2h); + ret = BUILTIN_FMA_F32(2.0f, BUILTIN_FMA_F32(e, x2l, e), -ret); + ret = x < -0x1.2d6abcp+3f ? PINF_F32 : ret; + } + + return ret; +} + +#else + +CONSTATTR float +MATH_MANGLE(erfcx)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + float ret; + + if (ax < 1.0f) { + ret = MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, + -0x1.77d64p-11f, 0x1.269372p-9f), + -0x1.c27dd4p-9f), 0x1.d3d3c4p-8f), + -0x1.35d6cap-6f), 0x1.5bb082p-5f), + -0x1.60e46ep-4f), 0x1.54d3e4p-3f), + -0x1.340edap-2f), 0x1.00049ap-1f), + -0x1.81286p-1f), 0x1.ffffcap-1f), + -0x1.20dd7p+0f), 0x1.0p+0f); + } else if (ax < 32.0f) { + float t = MATH_DIV(ax - 4.0f, ax + 4.0f); + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + 0.00416076401f, -0.0167250745f), + 0.0378070959f), -0.0661972834f), + 0.0935599947f), -0.101052745f), + 0.0681148962f), 0.0153801711f), + -0.139621619f), 1.23299511f); + + ret = MATH_DIV(ret, MATH_MAD(ax, 2.0f, 1.0f)); + } else { + const float one_over_sqrtpi = 0x1.20dd76p-1f; + float z = MATH_RCP(x * x); + ret = MATH_DIV(one_over_sqrtpi, x) * MATH_MAD(z, MATH_MAD(z, 0.375f, -0.5f), 1.0f); + } + + if (x <= -1.0f) { + float x2h, x2l; + if (HAVE_FAST_FMA32()) { + x2h = ax * ax; + x2l = BUILTIN_FMA_F32(ax, ax, -x2h); + } else { + float xh = AS_FLOAT(AS_UINT(ax) & 0xfffff000U); + float xl = ax - xh; + x2h = xh*xh; + x2l = (ax + xh)*xl; + } + + ret = MATH_MANGLE(exp)(x2h) * MATH_MANGLE(exp)(x2l) * 2.0f - ret; + ret = x < -10.0f ? PINF_F32 : ret; + } + + return ret; +} + +#endif diff --git a/amd/device-libs/ocml/src/erfcxH.cl b/amd/device-libs/ocml/src/erfcxH.cl new file mode 100644 index 0000000000000..4a56bde126914 --- /dev/null +++ b/amd/device-libs/ocml/src/erfcxH.cl @@ -0,0 +1,11 @@ + +#include "mathH.h" + +CONSTATTR UGEN(erfcx) + +CONSTATTR half +MATH_MANGLE(erfcx)(half x) +{ + return (half)MATH_UPMANGLE(erfcx)((float)x); +} + diff --git a/amd/device-libs/ocml/src/erfinvD.cl b/amd/device-libs/ocml/src/erfinvD.cl new file mode 100644 index 0000000000000..24da7560b75f5 --- /dev/null +++ b/amd/device-libs/ocml/src/erfinvD.cl @@ -0,0 +1,99 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(erfinv)(double x) +{ + double ax = BUILTIN_ABS_F64(x); + double ret; + + if (ax < 0.375) { + double t = ax*ax; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.c5ec06cd8002bp-2, -0x1.bb7dd47aef0d6p-1), 0x1.d189992eccdb6p-1), -0x1.10ec180cde957p-1), + 0x1.05cce379dd66fp-2), -0x1.6b9067e3dae74p-5), 0x1.5f7f0487c11a3p-5), 0x1.e0fbf22b2350cp-6), + 0x1.2ce26322b7f90p-5), 0x1.5ebeeee81dd31p-5), 0x1.a7cacb897f0d4p-5), 0x1.0a130d62cba32p-4), + 0x1.62847c8653359p-4), 0x1.053c2c0a5e083p-3), 0x1.db29fb2feec72p-3), 0x1.c5bf891b4ef6ap-1); + ret = ax * ret; + } else if (ax < 0x1.fffep-1) { + double w = -MATH_MANGLE(log)(BUILTIN_FMA_F64(-ax, ax, 1.0)); + + if (w < 6.25) { + w = w - 3.125; + ret = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, + -0x1.135d2e746e627p-68, -0x1.8ddf93324d327p-63), 0x1.7b83eef0b7c9fp-60), 0x1.9ba72cd589b91p-57), + -0x1.33689090a6b96p-53), 0x1.82e11898132e0p-56), 0x1.de4acfd9e26bap-48), -0x1.6d33eed66c487p-45), + -0x1.6f2167040d8e2p-44), 0x1.72a22c2d77e20p-39), -0x1.c8859c4e5c0afp-37), -0x1.dc583d118a561p-35), + 0x1.20f47ccf46b3cp-30), -0x1.1a9e38dc84d60p-28), -0x1.f36cd6d3d46a9p-26), 0x1.c6b4f5d03b787p-22), + -0x1.6e8a5434ae8a2p-20), -0x1.d1d1f7b8736f6p-17), 0x1.879c2a212f024p-13), -0x1.845769484fca8p-11), + -0x1.8b6c33114f909p-8), 0x1.ebd80d9b13e28p-3), 0x1.a755e7c99ae86p+0); + } else if (w < 16.0) { + w = MATH_SQRT(w) - 3.25; + ret = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, + 0x1.3040f87dbd932p-29, 0x1.85cbe52878635p-24), -0x1.2777453dd3955p-22), 0x1.395abcd554c6cp-26), + 0x1.936388a3790adp-20), -0x1.0d5db812b5083p-18), 0x1.8860cd5d652f6p-19), 0x1.a29a0cacdfb23p-17), + -0x1.8cef1f80281f2p-15), 0x1.1e684d0b9188ap-14), 0x1.932cd54c8a222p-16), -0x1.7448a89ef8aa3p-12), + 0x1.f3cc55ad40c25p-11), -0x1.ba924132f38b1p-10), 0x1.468eeca533cf8p-9), -0x1.ebadabb891bbdp-9), + 0x1.5ffcfe5b76afcp-8), 0x1.0158a6d641d39p+0), 0x1.8abcc380d5a48p+1); + } else { + w = MATH_SQRT(w) - 5.0; + ret = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + -0x1.dcec3a7785389p-36, -0x1.18feec0e38727p-32), 0x1.9e6bf2dda45e3p-30), -0x1.0468fb24e2f5fp-28), + 0x1.05ac6a8fba182p-27), -0x1.0102e495fb9c0p-26), 0x1.f4c20e1334af8p-26), -0x1.22d220fdf9c3ep-24), + 0x1.ebc8bb824cb54p-23), -0x1.0a8d40ea372ccp-20), 0x1.2fbd29d093d2bp-18), -0x1.4a3497e1e0facp-16), + 0x1.3ebf4eb00938fp-14), -0x1.c2f36a8fc5d53p-13), -0x1.22ea5df04047cp-13), 0x1.02a30d1fba0dcp+0), + 0x1.3664ddd1ad7fbp+2); + } + ret = ax * ret; + } else { + double s = MATH_SQRT(-MATH_MANGLE(log)(1.0 - ax)); + double t = MATH_RCP(s); + + if (ax < 0x1.fffffffep-1) { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.c4bd831a51669p+7, -0x1.66af45b757c26p+9), 0x1.061b293ee1671p+10), -0x1.d4aa0fd7248e9p+9), + 0x1.1eebb0088748dp+9), -0x1.ff4cb6c165efep+7), 0x1.59c379a609255p+6), -0x1.762b2677680c6p+4), + 0x1.7626132cf7c5ap+2), -0x1.a298cc231a949p+0), -0x1.9fa2d429b22cap-6), 0x1.00131c4b15d15p+0); + } else { + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + 0x1.e1f462cc8e58ap+7, -0x1.dd260d25bee8dp+8), 0x1.af7dab6c206e6p+8), -0x1.d97c75a0f5809p+7), + 0x1.632c20bf45d30p+6), -0x1.8e4908179a727p+4), 0x1.89538a73a2c3cp+2), -0x1.aad8569b3607dp+0), + -0x1.80d1bec4b54cbp-6), 0x1.001006f90ea2cp+0); + } + + ret = s * ret; + } + + if (!FINITE_ONLY_OPT()) { + ret = ax > 1.0 ? QNAN_F64 : ret; + ret = ax == 1.0 ? PINF_F64 : ret; + } + + return BUILTIN_COPYSIGN_F64(ret, x); +} + diff --git a/amd/device-libs/ocml/src/erfinvF.cl b/amd/device-libs/ocml/src/erfinvF.cl new file mode 100644 index 0000000000000..8dc9e95326f77 --- /dev/null +++ b/amd/device-libs/ocml/src/erfinvF.cl @@ -0,0 +1,57 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(erfinv)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + float p; + + if (ax < 0.375f) { + float t = ax*ax; + p = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.48b6cap-3f, -0x1.a2930ap-6f), 0x1.65b0b4p-4f), 0x1.5581aep-4f), + 0x1.05aa56p-3f), 0x1.db2748p-3f), 0x1.c5bf8ap-1f); + } else { + float w; + if (HAVE_FAST_FMA32()) { + w = BUILTIN_FMA_F32(-ax, ax, 1.0f); + } else { + w = (1.0f - ax) * (1.0f + ax); + } + w = -MATH_MANGLE(log)(w); + + if (w < 5.0f) { + w = w - 2.5f; + p = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + 0x1.e2cb10p-26f, 0x1.70966cp-22f), -0x1.d8e6aep-19f), -0x1.26b582p-18f), + 0x1.ca65b6p-13f), -0x1.48a810p-10f), -0x1.11c9dep-8f), 0x1.f91ec6p-3f), + 0x1.805c5ep+0f); + } else { + w = MATH_SQRT(w) - 3.0f; + p = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, + -0x1.a3e136p-13f, 0x1.a76ad6p-14f), 0x1.61b8e4p-10f), -0x1.e17bcep-9f), + 0x1.7824f6p-8f), -0x1.f38baep-8f), 0x1.354afcp-7f), 0x1.006db6p+0f), + 0x1.6a9efcp+1f); + } + } + + float ret = p*ax; + + if (!FINITE_ONLY_OPT()) { + ret = ax > 1.0f ? QNAN_F32 : ret; + ret = ax == 1.0f ? PINF_F32 : ret; + } + + return BUILTIN_COPYSIGN_F32(ret, x); +} + diff --git a/amd/device-libs/ocml/src/erfinvH.cl b/amd/device-libs/ocml/src/erfinvH.cl new file mode 100644 index 0000000000000..b9a1b3f1cd619 --- /dev/null +++ b/amd/device-libs/ocml/src/erfinvH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(erfinv) + +CONSTATTR half +MATH_MANGLE(erfinv)(half x) +{ + return (half)MATH_UPMANGLE(erfinv)((float)x); +} + diff --git a/amd/device-libs/ocml/src/exp10D.cl b/amd/device-libs/ocml/src/exp10D.cl new file mode 100644 index 0000000000000..54d5103e8bdeb --- /dev/null +++ b/amd/device-libs/ocml/src/exp10D.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_EXP10 +#include "expD_base.h" + diff --git a/amd/device-libs/ocml/src/exp10F.cl b/amd/device-libs/ocml/src/exp10F.cl new file mode 100644 index 0000000000000..1acbb865ffee4 --- /dev/null +++ b/amd/device-libs/ocml/src/exp10F.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_EXP10 +#include "expF_base.h" + diff --git a/amd/device-libs/ocml/src/exp10H.cl b/amd/device-libs/ocml/src/exp10H.cl new file mode 100644 index 0000000000000..ec645473371b1 --- /dev/null +++ b/amd/device-libs/ocml/src/exp10H.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(exp10) + +CONSTATTR half +MATH_MANGLE(exp10)(half x) +{ + return (half)BUILTIN_AMDGPU_EXP2_F32((float)x * 0x1.a934f0p+1f); +} + diff --git a/amd/device-libs/ocml/src/exp2D.cl b/amd/device-libs/ocml/src/exp2D.cl new file mode 100644 index 0000000000000..8175feb396e5a --- /dev/null +++ b/amd/device-libs/ocml/src/exp2D.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_EXP2 +#include "expD_base.h" + diff --git a/amd/device-libs/ocml/src/exp2F.cl b/amd/device-libs/ocml/src/exp2F.cl new file mode 100644 index 0000000000000..e0e717bc824bc --- /dev/null +++ b/amd/device-libs/ocml/src/exp2F.cl @@ -0,0 +1,13 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(exp2)(float x) { + return BUILTIN_EXP2_F32(x); +} diff --git a/amd/device-libs/ocml/src/exp2H.cl b/amd/device-libs/ocml/src/exp2H.cl new file mode 100644 index 0000000000000..3e8ad62aa835c --- /dev/null +++ b/amd/device-libs/ocml/src/exp2H.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(exp2) + +CONSTATTR half +MATH_MANGLE(exp2)(half x) +{ + return BUILTIN_EXP2_F16(x); +} + diff --git a/amd/device-libs/ocml/src/expD.cl b/amd/device-libs/ocml/src/expD.cl new file mode 100644 index 0000000000000..5cbd8d08eb60a --- /dev/null +++ b/amd/device-libs/ocml/src/expD.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_EXP +#include "expD_base.h" + diff --git a/amd/device-libs/ocml/src/expD_base.h b/amd/device-libs/ocml/src/expD_base.h new file mode 100644 index 0000000000000..b98ec8411bea0 --- /dev/null +++ b/amd/device-libs/ocml/src/expD_base.h @@ -0,0 +1,50 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +#if defined COMPILING_EXP2 +MATH_MANGLE(exp2)(double x) +#elif defined COMPILING_EXP10 +MATH_MANGLE(exp10)(double x) +#else +MATH_MANGLE(exp)(double x) +#endif +{ +#if defined(COMPILING_EXP2) + double dn = BUILTIN_RINT_F64(x); + double f = x - dn; + double t = MATH_MAD(f, 0x1.62e42fefa39efp-1, f * 0x1.abc9e3b39803fp-56); +#elif defined(COMPILING_EXP10) + double dn = BUILTIN_RINT_F64(x * 0x1.a934f0979a371p+1); + double f = MATH_MAD(-dn, -0x1.9dc1da994fd21p-59, MATH_MAD(-dn, 0x1.34413509f79ffp-2, x)); + double t = MATH_MAD(f, 0x1.26bb1bbb55516p+1, f * -0x1.f48ad494ea3e9p-53); +#else + double dn = BUILTIN_RINT_F64(x * 0x1.71547652b82fep+0); + double t = MATH_MAD(-dn, 0x1.abc9e3b39803fp-56, MATH_MAD(-dn, 0x1.62e42fefa39efp-1, x)); +#endif + + double p = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.ade156a5dcb37p-26, 0x1.28af3fca7ab0cp-22), 0x1.71dee623fde64p-19), 0x1.a01997c89e6b0p-16), + 0x1.a01a014761f6ep-13), 0x1.6c16c1852b7b0p-10), 0x1.1111111122322p-7), 0x1.55555555502a1p-5), + 0x1.5555555555511p-3), 0x1.000000000000bp-1), 1.0), 1.0); + + + double z = BUILTIN_FLDEXP_F64(p, (int)dn); + + if (!FINITE_ONLY_OPT()) { + z = x > 1024.0 ? PINF_F64 : z; + } + + z = x < -1075.0 ? 0.0 : z; + + return z; +} + diff --git a/amd/device-libs/ocml/src/expF.cl b/amd/device-libs/ocml/src/expF.cl new file mode 100644 index 0000000000000..7703fe6159048 --- /dev/null +++ b/amd/device-libs/ocml/src/expF.cl @@ -0,0 +1,13 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(exp)(float x) { + return BUILTIN_EXP_F32(x); +} diff --git a/amd/device-libs/ocml/src/expF_base.h b/amd/device-libs/ocml/src/expF_base.h new file mode 100644 index 0000000000000..c423d2657f77a --- /dev/null +++ b/amd/device-libs/ocml/src/expF_base.h @@ -0,0 +1,100 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +// Algorithm: +// +// e^x = 2^(x/ln(2)) = 2^(x*(64/ln(2))/64) +// +// x*(64/ln(2)) = n + f, |f| <= 0.5, n is integer +// n = 64*m + j, 0 <= j < 64 +// +// e^x = 2^((64*m + j + f)/64) +// = (2^m) * (2^(j/64)) * 2^(f/64) +// = (2^m) * (2^(j/64)) * e^(f*(ln(2)/64)) +// +// f = x*(64/ln(2)) - n +// r = f*(ln(2)/64) = x - n*(ln(2)/64) +// +// e^x = (2^m) * (2^(j/64)) * e^r +// +// (2^(j/64)) is precomputed +// +// e^r = 1 + r + (r^2)/2! + (r^3)/3! + (r^4)/4! + (r^5)/5! +// e^r = 1 + q +// +// q = r + (r^2)/2! + (r^3)/3! + (r^4)/4! + (r^5)/5! +// +// e^x = (2^m) * ( (2^(j/64)) + q*(2^(j/64)) ) + +CONSTATTR float +MATH_MANGLE(exp10)(float x) +{ + if (DAZ_OPT()) { + if (UNSAFE_MATH_OPT()) { + return BUILTIN_AMDGPU_EXP2_F32(x * 0x1.a92000p+1f) * BUILTIN_AMDGPU_EXP2_F32(x * 0x1.4f0978p-11f); + } else { + float ph, pl; + + if (HAVE_FAST_FMA32()) { + const float c = 0x1.a934f0p+1f; + const float cc = 0x1.2f346ep-24f; + ph = x * c; + pl = BUILTIN_FMA_F32(x, cc, BUILTIN_FMA_F32(x, c, -ph)); + } else { + const float ch = 0x1.a92000p+1f; + const float cl = 0x1.4f0978p-11f; + float xh = AS_FLOAT(AS_INT(x) & 0xfffff000); + float xl = x - xh; + ph = xh * ch; + pl = MATH_MAD(xh, cl, MATH_MAD(xl, ch, xl*cl)); + } + + float e = BUILTIN_RINT_F32(ph); + float a = ph - e + pl; + float r = BUILTIN_FLDEXP_F32(BUILTIN_AMDGPU_EXP2_F32(a), (int)e); + + r = x < -0x1.2f7030p+5f ? 0.0f : r; + r = x > 0x1.344136p+5f ? PINF_F32 : r; + return r; + } + } else { + if (UNSAFE_MATH_OPT()) { + bool s = x < -0x1.2f7030p+5f; + x += s ? 0x1.0p+5f : 0.0f; + return BUILTIN_AMDGPU_EXP2_F32(x * 0x1.a92000p+1f) * + BUILTIN_AMDGPU_EXP2_F32(x * 0x1.4f0978p-11f) * + (s ? 0x1.9f623ep-107f : 1.0f); + } else { + float ph, pl; + + if (HAVE_FAST_FMA32()) { + const float c = 0x1.a934f0p+1f; + const float cc = 0x1.2f346ep-24f; + ph = x * c; + pl = BUILTIN_FMA_F32(x, cc, BUILTIN_FMA_F32(x, c, -ph)); + } else { + const float ch = 0x1.a92000p+1f; + const float cl = 0x1.4f0978p-11f; + float xh = AS_FLOAT(AS_INT(x) & 0xfffff000); + float xl = x - xh; + ph = xh * ch; + pl = MATH_MAD(xh, cl, MATH_MAD(xl, ch, xl*cl)); + } + + float e = BUILTIN_RINT_F32(ph); + float a = ph - e + pl; + float r = BUILTIN_FLDEXP_F32(BUILTIN_AMDGPU_EXP2_F32(a), (int)e); + + r = x < -0x1.66d3e8p+5f ? 0.0f : r; + r = x > 0x1.344136p+5f ? PINF_F32 : r; + return r; + } + } +} + diff --git a/amd/device-libs/ocml/src/expH.cl b/amd/device-libs/ocml/src/expH.cl new file mode 100644 index 0000000000000..b8757a2087b3f --- /dev/null +++ b/amd/device-libs/ocml/src/expH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(exp) + +CONSTATTR half +MATH_MANGLE(exp)(half x) +{ + return (half)BUILTIN_AMDGPU_EXP2_F32((float)x * 0x1.715476p+0f); +} + diff --git a/amd/device-libs/ocml/src/expepD.cl b/amd/device-libs/ocml/src/expepD.cl new file mode 100644 index 0000000000000..75230030135f1 --- /dev/null +++ b/amd/device-libs/ocml/src/expepD.cl @@ -0,0 +1,43 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double +MATH_PRIVATE(expep)(double2 x) +{ +#if defined EXTRA_ACCURACY + double dn = BUILTIN_RINT_F64(x.hi * 0x1.71547652b82fep+0); + double2 t = fsub(fsub(sub(x, dn*0x1.62e42fefa3000p-1), dn*0x1.3de6af278e000p-42), dn*0x1.9cc01f97b57a0p-83); + + double th = t.hi; + double p = MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, + MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, + MATH_MAD(th, + 0x1.ade156a5dcb37p-26, 0x1.28af3fca7ab0cp-22), 0x1.71dee623fde64p-19), 0x1.a01997c89e6b0p-16), + 0x1.a01a014761f6ep-13), 0x1.6c16c1852b7b0p-10), 0x1.1111111122322p-7), 0x1.55555555502a1p-5), + 0x1.5555555555511p-3), 0x1.000000000000bp-1); + + double2 r = fadd(t, mul(sqr(t), p)); + double z = 1.0 + r.hi; + + z = BUILTIN_FLDEXP_F64(z, (int)dn); + + z = x.hi > 710.0 ? PINF_F64 : z; + z = x.hi < -745.0 ? 0.0 : z; +#else + double z = MATH_MANGLE(exp)(x.hi); + double zz = MATH_MAD(z, x.lo, z); + z = BUILTIN_ISINF_F64(z)? z : zz; +#endif + + return z; +} + diff --git a/amd/device-libs/ocml/src/expepF.cl b/amd/device-libs/ocml/src/expepF.cl new file mode 100644 index 0000000000000..3a675626f7763 --- /dev/null +++ b/amd/device-libs/ocml/src/expepF.cl @@ -0,0 +1,43 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +CONSTATTR float +MATH_PRIVATE(expep)(float2 x) +{ +#if defined EXTRA_ACCURACY + float fn = BUILTIN_RINT_F32(x.hi * 0x1.715476p+0f); + float2 t = fsub(fsub(sub(x, fn*0x1.62e400p-1f), fn*0x1.7f7800p-20f), fn*0x1.473de6p-34f); + + float th = t.hi; + float p = MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, MATH_MAD(th, + 0x1.6850e4p-10f, 0x1.123bccp-7f), 0x1.555b98p-5f), 0x1.55548ep-3f), + 0x1.fffff8p-2f); + + float2 r = fadd(t, mul(sqr(t), p)); + float z = 1.0f + r.hi; + + z = BUILTIN_FLDEXP_F32(z, (int)fn); + + z = x.hi > 89.0f ? PINF_F32 : z; + z = x.hi < -104.0f ? 0.0f : z; +#else + float d = x.hi == 0x1.62e430p+6f ? 0x1.0p-17f : 0.0f; + x.hi -= d; + x.lo += d; + float z = MATH_MANGLE(exp)(x.hi); + float zz = BUILTIN_FMA_F32(z, x.lo, z); + z = BUILTIN_ISINF_F32(z) ? z : zz; +#endif + + return z; +} + diff --git a/amd/device-libs/ocml/src/expm1D.cl b/amd/device-libs/ocml/src/expm1D.cl new file mode 100644 index 0000000000000..17376f1b890d2 --- /dev/null +++ b/amd/device-libs/ocml/src/expm1D.cl @@ -0,0 +1,50 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double2 MATH_PRIVATE(epexpep)(double2 x); + +CONSTATTR double +MATH_MANGLE(expm1)(double x) +{ +#if defined EXTRA_ACCURACY + double2 e = sub(MATH_PRIVATE(epexpep)(con(x, 0.0)), 1.0); + double z = e.hi; +#else + double dn = BUILTIN_RINT_F64(x * 0x1.71547652b82fep+0); + double t = MATH_MAD(-dn, 0x1.abc9e3b39803fp-56, MATH_MAD(-dn, 0x1.62e42fefa39efp-1, x)); + + double p = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.1f32ea9d67f34p-29, 0x1.af4eb2a1b768bp-26), + 0x1.27e500e0ac05bp-22), 0x1.71de01b889c29p-19), + 0x1.a01a0197bcfd8p-16), 0x1.a01a01ac1a723p-13), + 0x1.6c16c16c18931p-10), 0x1.1111111110056p-7), + 0x1.5555555555552p-5), 0x1.5555555555557p-3), + 0x1.0000000000000p-1); + + p = MATH_MAD(t, t*p, t); + int e = dn == 1024.0 ? 1023 : (int)dn; + double s = BUILTIN_FLDEXP_F64(1.0, e); + double z = MATH_MAD(s, p, s - 1.0); + z = dn == 1024.0 ? 2.0*z : z; +#endif + + if (!FINITE_ONLY_OPT()) { + z = x > 0x1.62e42fefa39efp+9 ? PINF_F64 : z; + } + + z = x < -37.0 ? -1.0 : z; + + return z; +} + diff --git a/amd/device-libs/ocml/src/expm1F.cl b/amd/device-libs/ocml/src/expm1F.cl new file mode 100644 index 0000000000000..75df38f942bcb --- /dev/null +++ b/amd/device-libs/ocml/src/expm1F.cl @@ -0,0 +1,42 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float2 MATH_PRIVATE(epexpep)(float2 x); + +CONSTATTR float +MATH_MANGLE(expm1)(float x) +{ +#if defined EXTRA_ACCURACY + float2 e = sub(MATH_PRIVATE(epexpep)(con(x, 0.0f)), 1.0f); + float z = e.hi; +#else + float fn = BUILTIN_RINT_F32(x * 0x1.715476p+0f); + float t = BUILTIN_FMA_F32(-fn, -0x1.05c610p-29f, BUILTIN_FMA_F32(-fn, 0x1.62e430p-1f, x)); + float p = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.a26762p-13f, 0x1.6d2e00p-10f), 0x1.110ff2p-7f), 0x1.555502p-5f), + 0x1.555556p-3f), 0x1.000000p-1f); + p = BUILTIN_FMA_F32(t, t*p, t); + int e = fn == 128.0f ? 127 : (int)fn; + float s = BUILTIN_FLDEXP_F32(1.0f, e); + float z = BUILTIN_FMA_F32(s, p, s - 1.0f); + z = fn == 128.0 ? 2.0f*z : z; +#endif + + if (!FINITE_ONLY_OPT()) { + z = x > 0x1.62e42ep+6f ? PINF_F32 : z; + } + + z = x < -17.0f ? -1.0f : z; + + return z; +} + diff --git a/amd/device-libs/ocml/src/expm1H.cl b/amd/device-libs/ocml/src/expm1H.cl new file mode 100644 index 0000000000000..b9de01b93ad6a --- /dev/null +++ b/amd/device-libs/ocml/src/expm1H.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(expm1) + +CONSTATTR half +MATH_MANGLE(expm1)(half x) +{ + half ret; + ret = (half)(BUILTIN_AMDGPU_EXP2_F32((float)x * 0x1.715476p+0f) - 1.0f); + half p = BUILTIN_FMA_F16(x, x*BUILTIN_FMA_F16(x, 0x1.555556p-3h, 0.5h), x); + ret = BUILTIN_ABS_F16(x) < 0x1.0p-6h ? p : ret; + return ret; +} + diff --git a/amd/device-libs/ocml/src/fabsD.cl b/amd/device-libs/ocml/src/fabsD.cl new file mode 100644 index 0000000000000..9052cd0170421 --- /dev/null +++ b/amd/device-libs/ocml/src/fabsD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(fabs)(double x) +{ + return BUILTIN_ABS_F64(x); +} + diff --git a/amd/device-libs/ocml/src/fabsF.cl b/amd/device-libs/ocml/src/fabsF.cl new file mode 100644 index 0000000000000..957cb79fd8c67 --- /dev/null +++ b/amd/device-libs/ocml/src/fabsF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(fabs)(float x) +{ + return BUILTIN_ABS_F32(x); +} + diff --git a/amd/device-libs/ocml/src/fabsH.cl b/amd/device-libs/ocml/src/fabsH.cl new file mode 100644 index 0000000000000..1504bb6a3bcc6 --- /dev/null +++ b/amd/device-libs/ocml/src/fabsH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(fabs)(half2 x) +{ + return BUILTIN_ABS_2F16(x); +} + +CONSTATTR half +MATH_MANGLE(fabs)(half x) +{ + return BUILTIN_ABS_F16(x); +} + diff --git a/amd/device-libs/ocml/src/fdimD.cl b/amd/device-libs/ocml/src/fdimD.cl new file mode 100644 index 0000000000000..b90e4f557b69d --- /dev/null +++ b/amd/device-libs/ocml/src/fdimD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(fdim)(double x, double y) +{ + return (x <= y && !BUILTIN_ISUNORDERED_F64(x, y)) ? 0.0 : (x - y); +} + diff --git a/amd/device-libs/ocml/src/fdimF.cl b/amd/device-libs/ocml/src/fdimF.cl new file mode 100644 index 0000000000000..9d2d6dc7e39f8 --- /dev/null +++ b/amd/device-libs/ocml/src/fdimF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(fdim)(float x, float y) +{ + return (x <= y && !BUILTIN_ISUNORDERED_F32(x, y)) ? 0.0f : (x - y); +} + diff --git a/amd/device-libs/ocml/src/fdimH.cl b/amd/device-libs/ocml/src/fdimH.cl new file mode 100644 index 0000000000000..387d903465b9f --- /dev/null +++ b/amd/device-libs/ocml/src/fdimH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(fdim) + +CONSTATTR half +MATH_MANGLE(fdim)(half x, half y) +{ + return (x <= y && !BUILTIN_ISUNORDERED_F16(x, y)) ? 0.0h : (x - y); +} + diff --git a/amd/device-libs/ocml/src/floorD.cl b/amd/device-libs/ocml/src/floorD.cl new file mode 100644 index 0000000000000..2fc2375d7cad5 --- /dev/null +++ b/amd/device-libs/ocml/src/floorD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(floor)(double x) +{ + return BUILTIN_FLOOR_F64(x); +} + diff --git a/amd/device-libs/ocml/src/floorF.cl b/amd/device-libs/ocml/src/floorF.cl new file mode 100644 index 0000000000000..e8b6d3eff6680 --- /dev/null +++ b/amd/device-libs/ocml/src/floorF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(floor)(float x) +{ + return BUILTIN_FLOOR_F32(x); +} + diff --git a/amd/device-libs/ocml/src/floorH.cl b/amd/device-libs/ocml/src/floorH.cl new file mode 100644 index 0000000000000..f563e6488d1d8 --- /dev/null +++ b/amd/device-libs/ocml/src/floorH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(floor)(half2 x) +{ + return BUILTIN_FLOOR_2F16(x); +} + +CONSTATTR half +MATH_MANGLE(floor)(half x) +{ + return BUILTIN_FLOOR_F16(x); +} + diff --git a/amd/device-libs/ocml/src/fmaD.cl b/amd/device-libs/ocml/src/fmaD.cl new file mode 100644 index 0000000000000..cf84176186e28 --- /dev/null +++ b/amd/device-libs/ocml/src/fmaD.cl @@ -0,0 +1,37 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(fma)(double a, double b, double c) +{ + return BUILTIN_FMA_F64(a, b, c); +} + +CONSTATTR double +MATH_MANGLE(fma_rte)(double a, double b, double c) +{ + return BUILTIN_FMA_F64(a, b, c); +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR double \ +MATH_MANGLE(LN)(double a, double b, double c) \ +{ \ + BUILTIN_SETROUND_F16F64(RM); \ + double ret = BUILTIN_FMA_F64(a, b, c); \ + BUILTIN_SETROUND_F16F64(ROUND_RTE); \ + return ret; \ +} + +GEN(fma_rtn, ROUND_RTN) +GEN(fma_rtp, ROUND_RTP) +GEN(fma_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/fmaF.cl b/amd/device-libs/ocml/src/fmaF.cl new file mode 100644 index 0000000000000..3192447c13fac --- /dev/null +++ b/amd/device-libs/ocml/src/fmaF.cl @@ -0,0 +1,43 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE2(fma)(float2 a, float2 b, float2 c) +{ + return BUILTIN_FMA_2F32(a, b, c); +} + +CONSTATTR float +MATH_MANGLE(fma)(float a, float b, float c) +{ + return BUILTIN_FMA_F32(a, b, c); +} + +CONSTATTR float +MATH_MANGLE(fma_rte)(float a, float b, float c) +{ + return BUILTIN_FMA_F32(a, b, c); +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR float \ +MATH_MANGLE(LN)(float a, float b, float c) \ +{ \ + BUILTIN_SETROUND_F32(RM); \ + float ret = BUILTIN_FMA_F32(a, b, c); \ + BUILTIN_SETROUND_F32(ROUND_RTE); \ + return ret; \ +} + +GEN(fma_rtn, ROUND_RTN) +GEN(fma_rtp, ROUND_RTP) +GEN(fma_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/fmaH.cl b/amd/device-libs/ocml/src/fmaH.cl new file mode 100644 index 0000000000000..be764218e7baf --- /dev/null +++ b/amd/device-libs/ocml/src/fmaH.cl @@ -0,0 +1,43 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(fma)(half2 a, half2 b, half2 c) +{ + return BUILTIN_FMA_2F16(a, b, c); +} + +CONSTATTR half +MATH_MANGLE(fma)(half a, half b, half c) +{ + return BUILTIN_FMA_F16(a, b, c); +} + +CONSTATTR half +MATH_MANGLE(fma_rte)(half a, half b, half c) +{ + return BUILTIN_FMA_F16(a, b, c); +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR half \ +MATH_MANGLE(LN)(half a, half b, half c) \ +{ \ + BUILTIN_SETROUND_F16F64(RM); \ + half ret = BUILTIN_FMA_F16(a, b, c); \ + BUILTIN_SETROUND_F16F64(ROUND_RTE); \ + return ret; \ +} + +GEN(fma_rtn, ROUND_RTN) +GEN(fma_rtp, ROUND_RTP) +GEN(fma_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/fmaxD.cl b/amd/device-libs/ocml/src/fmaxD.cl new file mode 100644 index 0000000000000..06c5517d0964e --- /dev/null +++ b/amd/device-libs/ocml/src/fmaxD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(fmax)(double x, double y) +{ + return BUILTIN_MAX_F64(x, y); +} + diff --git a/amd/device-libs/ocml/src/fmaxF.cl b/amd/device-libs/ocml/src/fmaxF.cl new file mode 100644 index 0000000000000..da00090af9abf --- /dev/null +++ b/amd/device-libs/ocml/src/fmaxF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(fmax)(float x, float y) +{ + return BUILTIN_MAX_F32(x, y); +} + diff --git a/amd/device-libs/ocml/src/fmaxH.cl b/amd/device-libs/ocml/src/fmaxH.cl new file mode 100644 index 0000000000000..1d4f3f50352b5 --- /dev/null +++ b/amd/device-libs/ocml/src/fmaxH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(fmax)(half2 x, half2 y) +{ + return BUILTIN_MAX_2F16(x, y); +} + +CONSTATTR half +MATH_MANGLE(fmax)(half x, half y) +{ + return BUILTIN_MAX_F16(x, y); +} + diff --git a/amd/device-libs/ocml/src/fminD.cl b/amd/device-libs/ocml/src/fminD.cl new file mode 100644 index 0000000000000..7bf2b21c8beaa --- /dev/null +++ b/amd/device-libs/ocml/src/fminD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(fmin)(double x, double y) +{ + return BUILTIN_MIN_F64(x, y); +} + diff --git a/amd/device-libs/ocml/src/fminF.cl b/amd/device-libs/ocml/src/fminF.cl new file mode 100644 index 0000000000000..a0fc6d1bf5cac --- /dev/null +++ b/amd/device-libs/ocml/src/fminF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(fmin)(float x, float y) +{ + return BUILTIN_MIN_F32(x, y); +} + diff --git a/amd/device-libs/ocml/src/fminH.cl b/amd/device-libs/ocml/src/fminH.cl new file mode 100644 index 0000000000000..7f12d077e5794 --- /dev/null +++ b/amd/device-libs/ocml/src/fminH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(fmin)(half2 x, half2 y) +{ + return BUILTIN_MIN_2F16(x, y); +} + +CONSTATTR half +MATH_MANGLE(fmin)(half x, half y) +{ + return BUILTIN_MIN_F16(x, y); +} + diff --git a/amd/device-libs/ocml/src/fmodD.cl b/amd/device-libs/ocml/src/fmodD.cl new file mode 100644 index 0000000000000..f8fc5fb28245d --- /dev/null +++ b/amd/device-libs/ocml/src/fmodD.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_FMOD +#include "remainderD_base.h" + diff --git a/amd/device-libs/ocml/src/fmodF.cl b/amd/device-libs/ocml/src/fmodF.cl new file mode 100644 index 0000000000000..ca6fa09ea080a --- /dev/null +++ b/amd/device-libs/ocml/src/fmodF.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_FMOD +#include "remainderF_base.h" + diff --git a/amd/device-libs/ocml/src/fmodH.cl b/amd/device-libs/ocml/src/fmodH.cl new file mode 100644 index 0000000000000..9f5802e66f6b8 --- /dev/null +++ b/amd/device-libs/ocml/src/fmodH.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(fmod) + +#define COMPILING_FMOD +#include "remainderH_base.h" + diff --git a/amd/device-libs/ocml/src/fmuladdD.cl b/amd/device-libs/ocml/src/fmuladdD.cl new file mode 100644 index 0000000000000..97be92ffe7faa --- /dev/null +++ b/amd/device-libs/ocml/src/fmuladdD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(fmuladd)(double a, double b, double c) +{ + #pragma OPENCL FP_CONTRACT ON + return a * b + c; +} diff --git a/amd/device-libs/ocml/src/fmuladdF.cl b/amd/device-libs/ocml/src/fmuladdF.cl new file mode 100644 index 0000000000000..b8f12a12c6be3 --- /dev/null +++ b/amd/device-libs/ocml/src/fmuladdF.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE2(fmuladd)(float2 a, float2 b, float2 c) +{ + #pragma OPENCL FP_CONTRACT ON + return a * b + c; +} + +CONSTATTR float +MATH_MANGLE(fmuladd)(float a, float b, float c) +{ + #pragma OPENCL FP_CONTRACT ON + return a * b + c; +} + diff --git a/amd/device-libs/ocml/src/fmuladdH.cl b/amd/device-libs/ocml/src/fmuladdH.cl new file mode 100644 index 0000000000000..ff744dfcecfb9 --- /dev/null +++ b/amd/device-libs/ocml/src/fmuladdH.cl @@ -0,0 +1,24 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(fmuladd)(half2 a, half2 b, half2 c) +{ + #pragma OPENCL FP_CONTRACT ON + return a * b + c; +} + + +CONSTATTR half +MATH_MANGLE(fmuladd)(half a, half b, half c) +{ + #pragma OPENCL FP_CONTRACT ON + return a * b + c; +} + diff --git a/amd/device-libs/ocml/src/fpclassifyD.cl b/amd/device-libs/ocml/src/fpclassifyD.cl new file mode 100644 index 0000000000000..10ab2d48844f2 --- /dev/null +++ b/amd/device-libs/ocml/src/fpclassifyD.cl @@ -0,0 +1,19 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR int +MATH_MANGLE(fpclassify)(double x) +{ + int ret = BUILTIN_ISINF_F64(x) ? FP_INFINITE : FP_NAN; + ret = BUILTIN_ISZERO_F64(x) ? FP_ZERO : ret; + ret = BUILTIN_ISSUBNORMAL_F64(x) ? FP_SUBNORMAL : ret; + ret = BUILTIN_ISNORMAL_F64(x) ? FP_NORMAL : ret; + return ret; +} + diff --git a/amd/device-libs/ocml/src/fpclassifyF.cl b/amd/device-libs/ocml/src/fpclassifyF.cl new file mode 100644 index 0000000000000..3cb92a8333e27 --- /dev/null +++ b/amd/device-libs/ocml/src/fpclassifyF.cl @@ -0,0 +1,19 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR int +MATH_MANGLE(fpclassify)(float x) +{ + int ret = BUILTIN_ISINF_F32(x) ? FP_INFINITE : FP_NAN; + ret = BUILTIN_ISZERO_F32(x) ? FP_ZERO : ret; + ret = BUILTIN_ISSUBNORMAL_F32(x) ? FP_SUBNORMAL : ret; + ret = BUILTIN_ISNORMAL_F32(x) ? FP_NORMAL : ret; + return ret; +} + diff --git a/amd/device-libs/ocml/src/fpclassifyH.cl b/amd/device-libs/ocml/src/fpclassifyH.cl new file mode 100644 index 0000000000000..8847eb6d6d598 --- /dev/null +++ b/amd/device-libs/ocml/src/fpclassifyH.cl @@ -0,0 +1,19 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR int +MATH_MANGLE(fpclassify)(half x) +{ + int ret = BUILTIN_ISINF_F16(x) ? FP_INFINITE : FP_NAN; + ret = BUILTIN_ISZERO_F16(x) ? FP_ZERO : ret; + ret = BUILTIN_ISSUBNORMAL_F16(x) ? FP_SUBNORMAL : ret; + ret = BUILTIN_ISNORMAL_F16(x) ? FP_NORMAL : ret; + return ret; +} + diff --git a/amd/device-libs/ocml/src/fractD.cl b/amd/device-libs/ocml/src/fractD.cl new file mode 100644 index 0000000000000..8bf8c945651c0 --- /dev/null +++ b/amd/device-libs/ocml/src/fractD.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +double +MATH_MANGLE(fract)(double x, __private double *ip) +{ + *ip = BUILTIN_FLOOR_F64(x); + return BUILTIN_FRACTION_F64(x); +} + diff --git a/amd/device-libs/ocml/src/fractF.cl b/amd/device-libs/ocml/src/fractF.cl new file mode 100644 index 0000000000000..a34b39705c187 --- /dev/null +++ b/amd/device-libs/ocml/src/fractF.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +float +MATH_MANGLE(fract)(float x, __private float *ip) +{ + *ip = BUILTIN_FLOOR_F32(x); + return BUILTIN_FRACTION_F32(x); +} + diff --git a/amd/device-libs/ocml/src/fractH.cl b/amd/device-libs/ocml/src/fractH.cl new file mode 100644 index 0000000000000..2cda3a5c67e98 --- /dev/null +++ b/amd/device-libs/ocml/src/fractH.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +half2 +MATH_MANGLE2(fract)(half2 x, __private half2 *ip) +{ + *ip = BUILTIN_FLOOR_2F16(x); + return (half2)(BUILTIN_FRACTION_F16(x.lo), BUILTIN_FRACTION_F16(x.hi)); +} + +half +MATH_MANGLE(fract)(half x, __private half *ip) +{ + *ip = BUILTIN_FLOOR_F16(x); + return BUILTIN_FRACTION_F16(x); +} + diff --git a/amd/device-libs/ocml/src/frexpD.cl b/amd/device-libs/ocml/src/frexpD.cl new file mode 100644 index 0000000000000..66f5ad6c118d1 --- /dev/null +++ b/amd/device-libs/ocml/src/frexpD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +double +MATH_MANGLE(frexp)(double x, __private int *ep) +{ + return BUILTIN_FREXP_F64(x, ep); +} + diff --git a/amd/device-libs/ocml/src/frexpF.cl b/amd/device-libs/ocml/src/frexpF.cl new file mode 100644 index 0000000000000..a0cfd1cf97a7b --- /dev/null +++ b/amd/device-libs/ocml/src/frexpF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +float +MATH_MANGLE(frexp)(float x, __private int *ep) +{ + return BUILTIN_FREXP_F32(x, ep); +} + diff --git a/amd/device-libs/ocml/src/frexpH.cl b/amd/device-libs/ocml/src/frexpH.cl new file mode 100644 index 0000000000000..9867b0d4a8c2f --- /dev/null +++ b/amd/device-libs/ocml/src/frexpH.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +half2 +MATH_MANGLE2(frexp)(half2 x, __private int2 *ep) +{ + int elo, ehi; + half2 r; + r.lo = MATH_MANGLE(frexp)(x.lo, &elo); + r.hi = MATH_MANGLE(frexp)(x.hi, &ehi); + *ep = (int2)(elo, ehi); + return r; +} + +half +MATH_MANGLE(frexp)(half x, __private int *ep) +{ + return BUILTIN_FREXP_F16(x, ep); +} + diff --git a/amd/device-libs/ocml/src/hypotD.cl b/amd/device-libs/ocml/src/hypotD.cl new file mode 100644 index 0000000000000..efcca4db7faf9 --- /dev/null +++ b/amd/device-libs/ocml/src/hypotD.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(hypot)(double x, double y) +{ + double a = BUILTIN_ABS_F64(x); + double b = BUILTIN_ABS_F64(y); + double t = BUILTIN_MAX_F64(a, b); + int e = BUILTIN_FREXP_EXP_F64(t); + a = BUILTIN_FLDEXP_F64(a, -e); + b = BUILTIN_FLDEXP_F64(b, -e); + double ret = BUILTIN_FLDEXP_F64(MATH_FAST_SQRT(MATH_MAD(a, a, b*b)), e); + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_ISUNORDERED_F64(x, y) ? QNAN_F64 : ret; + + ret = (BUILTIN_ISINF_F64(x) | BUILTIN_ISINF_F64(y)) ? PINF_F64 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/hypotF.cl b/amd/device-libs/ocml/src/hypotF.cl new file mode 100644 index 0000000000000..0be18ae962187 --- /dev/null +++ b/amd/device-libs/ocml/src/hypotF.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(hypot)(float x, float y) +{ + float a = BUILTIN_ABS_F32(x); + float b = BUILTIN_ABS_F32(y); + float t = BUILTIN_MAX_F32(a, b); + int e = BUILTIN_FREXP_EXP_F32(t) ; + a = BUILTIN_FLDEXP_F32(a, -e); + b = BUILTIN_FLDEXP_F32(b, -e); + float ret = BUILTIN_FLDEXP_F32(MATH_FAST_SQRT(MATH_MAD(a, a, b*b)), e); + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_ISINF_F32(t) ? PINF_F32 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/hypotH.cl b/amd/device-libs/ocml/src/hypotH.cl new file mode 100644 index 0000000000000..ea4ee963beb96 --- /dev/null +++ b/amd/device-libs/ocml/src/hypotH.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(hypot) + +CONSTATTR half +MATH_MANGLE(hypot)(half x, half y) +{ + float fx = (float)x; + float fy = (float)y; + float d2 = BUILTIN_MAD_F32(fx, fx, fy*fy); + + half ret = (half)BUILTIN_AMDGPU_SQRT_F32(d2); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F16(x) | BUILTIN_ISINF_F16(y)) ? PINF_F16 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/i0D.cl b/amd/device-libs/ocml/src/i0D.cl new file mode 100644 index 0000000000000..d88243c17e0f6 --- /dev/null +++ b/amd/device-libs/ocml/src/i0D.cl @@ -0,0 +1,55 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +double +MATH_MANGLE(i0)(double x) +{ + x = BUILTIN_ABS_F64(x); + + double ret; + + if (x < 8.0) { + double t = 0.25 * x * x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.dd78750ff79b2p-97, 0x1.4394559531e65p-89), 0x1.6f7123f151c79p-81), 0x1.3d9e7c5528048p-73), + 0x1.e736f323a0cabp-66), 0x1.4196ce3b298c5p-58), 0x1.69caac7bf9255p-51), 0x1.5601878c06ac8p-44), + 0x1.0b313291f5e48p-37), 0x1.522a43f5dcb54p-31), 0x1.522a43f659634p-25), 0x1.02e85c0898945p-19), + 0x1.23456789abcf3p-14), 0x1.c71c71c71c71cp-10), 0x1.c71c71c71c71cp-6), 0x1.0000000000000p-2), + 0x1.0000000000000p+0), + ret = MATH_MAD(t, ret, 1.0f); + } else { + double t = MATH_RCP(x); + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + 0x1.cc967bacb549dp+49, -0x1.5ba7722975981p+50), 0x1.df0f836763276p+49), -0x1.9042a430f3f43p+48), + 0x1.c630541c4f568p+46), -0x1.7366be5a9784fp+44), 0x1.c5669a48f574ep+41), -0x1.a664cac47f0eap+38), + 0x1.308250566988cp+35), -0x1.56874c2ddb061p+31), 0x1.2da58968da2aap+27), -0x1.9faaa33f0d6bcp+22), + 0x1.be0a8f2bc76ddp+17), -0x1.7123c68c3cb02p+12), 0x1.d402150cc72aap+6), -0x1.7a8ae85359520p+0), + 0x1.bd7e0b6a753cdp-4), 0x1.6d6ce3774506dp-5), 0x1.debdd3d2f7cf9p-6), 0x1.cb94db8d452d5p-6), + 0x1.9884533daea3dp-5), 0x1.9884533d4362fp-2); + double xs = x - 709.0; + double e1 = MATH_MANGLE(exp)(x > 709.0 ? xs : x); + double e2 = x > 709.0 ? 0x1.d422d2be5dc9bp+1022 : 1.0; + ret = e1 * MATH_MANGLE(rsqrt)(x) * ret * e2; + } + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_CLASS_F64(x, CLASS_PINF|CLASS_QNAN|CLASS_SNAN) ? x : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/i0F.cl b/amd/device-libs/ocml/src/i0F.cl new file mode 100644 index 0000000000000..b4b75b95eebb9 --- /dev/null +++ b/amd/device-libs/ocml/src/i0F.cl @@ -0,0 +1,44 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +float +MATH_MANGLE(i0)(float x) +{ + x = BUILTIN_ABS_F32(x); + + float ret; + + if (x < 8.0f) { + float t = 0.25f * x * x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + 0x1.38d760p-43f, 0x1.7fd5c6p-38f), 0x1.66ffc8p-31f), 0x1.4ecb6ep-25f), + 0x1.033c70p-19f), 0x1.233bb2p-14f), 0x1.c71db2p-10f), 0x1.c71c5ep-6f), + 0x1.000000p-2f), 0x1.000000p+0f); + ret = MATH_MAD(t, ret, 1.0f); + } else { + float t = MATH_FAST_RCP(x); + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + 0x1.c49916p-2f, -0x1.110f5ep-5f), 0x1.2a130ap-5f), 0x1.c68702p-6f), + 0x1.9890aep-5f), 0x1.988450p-2f); + float xs = x - 88.0f; + float e1 = MATH_MANGLE(exp)(x > 88.0f ? xs : x); + float e2 = x > 88.0f ? 0x1.f1056ep+126f : 1.0f; + ret = e1 * BUILTIN_AMDGPU_RSQRT_F32(x) * ret * e2; + } + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_CLASS_F32(x, CLASS_PINF|CLASS_QNAN|CLASS_SNAN) ? x : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/i0H.cl b/amd/device-libs/ocml/src/i0H.cl new file mode 100644 index 0000000000000..913942f53918c --- /dev/null +++ b/amd/device-libs/ocml/src/i0H.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +UGEN(i0) + +half +MATH_MANGLE(i0)(half x) +{ + return (half)MATH_UPMANGLE(i0)((float)x); +} + diff --git a/amd/device-libs/ocml/src/i1D.cl b/amd/device-libs/ocml/src/i1D.cl new file mode 100644 index 0000000000000..56bfab559e158 --- /dev/null +++ b/amd/device-libs/ocml/src/i1D.cl @@ -0,0 +1,56 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +double +MATH_MANGLE(i1)(double x) +{ + double a = BUILTIN_ABS_F64(x); + + double ret; + + if (a < 8.0) { + a *= 0.5; + double t = a * a; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.fc892c836e80ap-93, 0x1.432352d94a857p-85), 0x1.588ae4f7b7a4ap-77), 0x1.15e96e9231b49p-69), + 0x1.8bdcb5f2184d1p-62), 0x1.e26237a1e02fep-55), 0x1.f176aca1a831fp-48), 0x1.ab81e97c83e75p-41), + 0x1.2c9758e3649ffp-34), 0x1.522a43f5ed306p-28), 0x1.27e4fb778d591p-22), 0x1.845c8a0ce4edap-17), + 0x1.6c16c16c16c26p-12), 0x1.c71c71c71c71cp-8), 0x1.5555555555555p-4), 0x1.0000000000000p-1); + ret = MATH_MAD(t, a*ret, a); + } else { + double t = MATH_RCP(a); + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + -0x1.c9d8d43214423p+49, 0x1.5c072e12fb4bap+50), -0x1.e26cff438b6f6p+49), 0x1.952224c61a221p+48), + -0x1.cdc7c873cf435p+46), 0x1.7b1e32a15fb86p+44), -0x1.d07dbd6696f1cp+41), 0x1.b227934f2ced2p+38), + -0x1.39f23e6685444p+35), 0x1.6229383f6f890p+31), -0x1.38bf1ceeee865p+27), 0x1.b01a348b749b8p+22), + -0x1.d0e043ef0916ap+17), 0x1.81b06f82cfbacp+12), -0x1.ea879b2a6508bp+6), 0x1.85cffc8d54f52p+0), + -0x1.09f107ee0f7e2p-3), -0x1.d61631539fb0dp-5), -0x1.4f1e01d904ebap-5), -0x1.7efc0ced79c58p-5), + -0x1.32633e6e0f07ap-3), 0x1.9884533d43674p-2); + + double xs = x - 709.0; + double e1 = MATH_MANGLE(exp)(x > 709.0 ? xs : x); + double e2 = x > 709.0 ? 0x1.d422d2be5dc9bp+1022 : 1.0; + ret = e1 * MATH_MANGLE(rsqrt)(x) * ret * e2; + } + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_CLASS_F64(a, CLASS_PINF|CLASS_QNAN|CLASS_SNAN) ? a : ret; + } + + return BUILTIN_COPYSIGN_F64(ret, x); +} + diff --git a/amd/device-libs/ocml/src/i1F.cl b/amd/device-libs/ocml/src/i1F.cl new file mode 100644 index 0000000000000..08732057a30e7 --- /dev/null +++ b/amd/device-libs/ocml/src/i1F.cl @@ -0,0 +1,45 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +float +MATH_MANGLE(i1)(float x) +{ + float a = BUILTIN_ABS_F32(x); + + float ret; + + if (a < 8.0f) { + a *= 0.5f; + float t = a * a; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.882dd2p-40f, 0x1.af97f6p-35f), 0x1.66a3eap-28f), 0x1.251b32p-22f), + 0x1.84cbb6p-17f), 0x1.6c0d4ap-12f), 0x1.c71d3ap-8f), 0x1.555550p-4f), + 0x1.000000p-1f); + ret = MATH_MAD(t, a*ret, a); + } else { + float t = MATH_FAST_RCP(a); + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + -0x1.06de32p-1f, 0x1.043b22p-5f), -0x1.925276p-5f), -0x1.7c15c8p-5f), + -0x1.3266ccp-3f), 0x1.988456p-2f); + + float as = a - 88.0f; + float e1 = MATH_MANGLE(exp)(a > 88.0f ? as : a); + float e2 = a > 88.0f ? 0x1.f1056ep+126f : 1.0f; + ret = e1 * BUILTIN_AMDGPU_RSQRT_F32(a) * ret * e2; + } + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_CLASS_F32(a, CLASS_PINF|CLASS_QNAN|CLASS_SNAN) ? a : ret; + } + + return BUILTIN_COPYSIGN_F32(ret, x); +} + diff --git a/amd/device-libs/ocml/src/i1H.cl b/amd/device-libs/ocml/src/i1H.cl new file mode 100644 index 0000000000000..d778626be29ca --- /dev/null +++ b/amd/device-libs/ocml/src/i1H.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +UGEN(i1) + +half +MATH_MANGLE(i1)(half x) +{ + return (half)MATH_UPMANGLE(i1)((float)x); +} + diff --git a/amd/device-libs/ocml/src/ilogbD.cl b/amd/device-libs/ocml/src/ilogbD.cl new file mode 100644 index 0000000000000..b74b23aa0cb0d --- /dev/null +++ b/amd/device-libs/ocml/src/ilogbD.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR int +MATH_MANGLE(ilogb)(double x) +{ + int r = BUILTIN_FREXP_EXP_F64(x) - 1; + + if (!FINITE_ONLY_OPT()) { + r = BUILTIN_ISNAN_F64(x) ? FP_ILOGBNAN : r; + r = BUILTIN_ISINF_F64(x) ? INT_MAX : r; + } + + r = x == 0.0 ? FP_ILOGB0 : r; + return r; +} + diff --git a/amd/device-libs/ocml/src/ilogbF.cl b/amd/device-libs/ocml/src/ilogbF.cl new file mode 100644 index 0000000000000..7e3bf77a21d71 --- /dev/null +++ b/amd/device-libs/ocml/src/ilogbF.cl @@ -0,0 +1,24 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR int +MATH_MANGLE(ilogb)(float x) +{ + int r = BUILTIN_FREXP_EXP_F32(x) - 1; + + if (!FINITE_ONLY_OPT()) { + r = BUILTIN_ISNAN_F32(x) ? FP_ILOGBNAN : r; + r = BUILTIN_ISINF_F32(x) ? INT_MAX : r; + } + + r = x == 0.0f ? FP_ILOGB0 : r; + + return r; +} + diff --git a/amd/device-libs/ocml/src/ilogbH.cl b/amd/device-libs/ocml/src/ilogbH.cl new file mode 100644 index 0000000000000..2d25c77ef9351 --- /dev/null +++ b/amd/device-libs/ocml/src/ilogbH.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR int2 +MATH_MANGLE2(ilogb)(half2 x) +{ + return (int2)(MATH_MANGLE(ilogb)(x.lo), MATH_MANGLE(ilogb)(x.hi)); +} + +CONSTATTR int +MATH_MANGLE(ilogb)(half x) +{ + int r = (int)BUILTIN_FREXP_EXP_F16(x) - 1; + + if (!FINITE_ONLY_OPT()) { + r = BUILTIN_ISNAN_F16(x) ? FP_ILOGBNAN : r; + r = BUILTIN_ISINF_F16(x) ? INT_MAX : r; + } + + r = x == 0.0h ? FP_ILOGB0 : r; + return r; +} + diff --git a/amd/device-libs/ocml/src/isfiniteD.cl b/amd/device-libs/ocml/src/isfiniteD.cl new file mode 100644 index 0000000000000..69257f63fe401 --- /dev/null +++ b/amd/device-libs/ocml/src/isfiniteD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR int +MATH_MANGLE(isfinite)(double x) +{ + return BUILTIN_ISFINITE_F64(x); +} + diff --git a/amd/device-libs/ocml/src/isfiniteF.cl b/amd/device-libs/ocml/src/isfiniteF.cl new file mode 100644 index 0000000000000..92b38c52a355c --- /dev/null +++ b/amd/device-libs/ocml/src/isfiniteF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR int +MATH_MANGLE(isfinite)(float x) +{ + return BUILTIN_ISFINITE_F32(x); +} + diff --git a/amd/device-libs/ocml/src/isfiniteH.cl b/amd/device-libs/ocml/src/isfiniteH.cl new file mode 100644 index 0000000000000..d7b886d7bbe97 --- /dev/null +++ b/amd/device-libs/ocml/src/isfiniteH.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR short2 +MATH_MANGLE2(isfinite)(half2 x) +{ + return (short2) + (BUILTIN_ISFINITE_F16(x.lo) ? (short)-1 : (short)0, + BUILTIN_ISFINITE_F16(x.hi) ? (short)-1 : (short)0); +} + +CONSTATTR int +MATH_MANGLE(isfinite)(half x) +{ + return BUILTIN_ISFINITE_F16(x); +} + diff --git a/amd/device-libs/ocml/src/isinfD.cl b/amd/device-libs/ocml/src/isinfD.cl new file mode 100644 index 0000000000000..a3820a3e62764 --- /dev/null +++ b/amd/device-libs/ocml/src/isinfD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR int +MATH_MANGLE(isinf)(double x) +{ + return BUILTIN_ISINF_F64(x); +} + diff --git a/amd/device-libs/ocml/src/isinfF.cl b/amd/device-libs/ocml/src/isinfF.cl new file mode 100644 index 0000000000000..5a0b176a550dd --- /dev/null +++ b/amd/device-libs/ocml/src/isinfF.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR int +MATH_MANGLE(isinf)(float x) +{ + return BUILTIN_ISINF_F32(x); +} diff --git a/amd/device-libs/ocml/src/isinfH.cl b/amd/device-libs/ocml/src/isinfH.cl new file mode 100644 index 0000000000000..6d176733d1a11 --- /dev/null +++ b/amd/device-libs/ocml/src/isinfH.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR short2 +MATH_MANGLE2(isinf)(half2 x) +{ + return (short2) + (BUILTIN_ISINF_F16(x.lo) ? (short)-1 : (short)0, + BUILTIN_ISINF_F16(x.hi) ? (short)-1 : (short)0); +} + +CONSTATTR int +MATH_MANGLE(isinf)(half x) +{ + return BUILTIN_ISINF_F16(x); +} + diff --git a/amd/device-libs/ocml/src/isnanD.cl b/amd/device-libs/ocml/src/isnanD.cl new file mode 100644 index 0000000000000..932e0c24b97fb --- /dev/null +++ b/amd/device-libs/ocml/src/isnanD.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR int +MATH_MANGLE(isnan)(double x) +{ + return BUILTIN_ISNAN_F64(x); +} diff --git a/amd/device-libs/ocml/src/isnanF.cl b/amd/device-libs/ocml/src/isnanF.cl new file mode 100644 index 0000000000000..aa73088f2b6bf --- /dev/null +++ b/amd/device-libs/ocml/src/isnanF.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR int +MATH_MANGLE(isnan)(float x) +{ + return BUILTIN_ISNAN_F32(x); +} diff --git a/amd/device-libs/ocml/src/isnanH.cl b/amd/device-libs/ocml/src/isnanH.cl new file mode 100644 index 0000000000000..c4fbcc7f0d991 --- /dev/null +++ b/amd/device-libs/ocml/src/isnanH.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR short2 +MATH_MANGLE2(isnan)(half2 x) +{ + return (short2) + (BUILTIN_ISNAN_F16(x.lo) ? (short)-1 : (short)0, + BUILTIN_ISNAN_F16(x.hi) ? (short)-1 : (short)0); +} + +CONSTATTR int +MATH_MANGLE(isnan)(half x) +{ + return BUILTIN_ISNAN_F16(x); +} + diff --git a/amd/device-libs/ocml/src/isnormalD.cl b/amd/device-libs/ocml/src/isnormalD.cl new file mode 100644 index 0000000000000..69fbc280c30d5 --- /dev/null +++ b/amd/device-libs/ocml/src/isnormalD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR int +MATH_MANGLE(isnormal)(double x) +{ + return BUILTIN_ISNORMAL_F64(x); +} + diff --git a/amd/device-libs/ocml/src/isnormalF.cl b/amd/device-libs/ocml/src/isnormalF.cl new file mode 100644 index 0000000000000..c8704c07b029d --- /dev/null +++ b/amd/device-libs/ocml/src/isnormalF.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR int +MATH_MANGLE(isnormal)(float x) +{ + return BUILTIN_ISNORMAL_F32(x); +} diff --git a/amd/device-libs/ocml/src/isnormalH.cl b/amd/device-libs/ocml/src/isnormalH.cl new file mode 100644 index 0000000000000..25f9abd60bc8d --- /dev/null +++ b/amd/device-libs/ocml/src/isnormalH.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR short2 +MATH_MANGLE2(isnormal)(half2 x) +{ + return (short2) + (BUILTIN_ISNORMAL_F16(x.lo) ? (short)-1 : (short)0, + BUILTIN_ISNORMAL_F16(x.hi) ? (short)-1 : (short)0); +} + +CONSTATTR int +MATH_MANGLE(isnormal)(half x) +{ + return BUILTIN_ISNORMAL_F16(x); +} + diff --git a/amd/device-libs/ocml/src/j0D.cl b/amd/device-libs/ocml/src/j0D.cl new file mode 100644 index 0000000000000..df4ee9cfee1a7 --- /dev/null +++ b/amd/device-libs/ocml/src/j0D.cl @@ -0,0 +1,93 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +extern double MATH_PRIVATE(cosb)(double, int, double); +extern CONSTATTR double MATH_PRIVATE(bp0)(double); +extern CONSTATTR double MATH_PRIVATE(ba0)(double); + +double +MATH_MANGLE(j0)(double x) +{ + x = BUILTIN_ABS_F64(x); + + const double b0 = 1.65625; + const double b1 = 3.125; + const double b2 = 4.6875; + const double b3 = 6.265625; + const double b4 = 7.84375; + const double b5 = 9.421875; + const double b6 = 10.984375; + const double b7 = 12.578125; + + double ret; + + if (x <= b7) { + // Ty to maintain relative accuracy here + + USE_TABLE(double, p, M64_J0); + double ch, cl; + + if (x <= b3) { + if (x <= b0) { + ch = 0.0; + cl = 0.0; + } else if (x <= b1) { + ch = 0x1.33d152e971b40p+1; + cl = -0x1.0f539d7da258ep-53; + p += 1*15; + } else if (x <= b2) { + ch = 0x1.ea75575af6f09p+1; + cl = -0x1.60155a9d1b256p-53; + p += 2*15; + } else { + ch = 0x1.6148f5b2c2e45p+2; + cl = 0x1.75054cd60a517p-54; + p += 3*15; + } + } else { + if (x <= b4) { + ch = 0x1.c0ff5f3b47250p+2; + cl = -0x1.b226d9d243827p-54; + p += 4*15; + } else if (x <= b5) { + ch = 0x1.14eb56cccdecap+3; + cl = -0x1.51970714c7c25p-52; + p += 5*15; + } else if (x <= b6) { + ch = 0x1.458d0d0bdfc29p+3; + cl = 0x1.02610a51562b6p-51; + p += 6*15; + } else { + ch = 0x1.79544008272b6p+3; + cl = 0x1.444fd5821d5b1p-52; + p += 7*15; + } + } + + x = x - ch - cl; + ret = MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, + p[14], p[13]), p[12]), + p[11]), p[10]), p[9]), p[8]), + p[7]), p[6]), p[5]), p[4]), + p[3]), p[2]), p[1]), p[0]); + + } else { + double r = MATH_RCP(x); + double r2 = r*r; + double p = MATH_PRIVATE(bp0)(r2) * r; + ret = 0x1.9884533d43651p-1 * MATH_FAST_SQRT(r) * MATH_PRIVATE(ba0)(r2) * MATH_PRIVATE(cosb)(x, 0, p); + ret = x == PINF_F64 ? 0.0 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/j0F.cl b/amd/device-libs/ocml/src/j0F.cl new file mode 100644 index 0000000000000..f569390d875a8 --- /dev/null +++ b/amd/device-libs/ocml/src/j0F.cl @@ -0,0 +1,88 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +extern float MATH_PRIVATE(cosb)(float, int, float); +extern CONSTATTR float MATH_PRIVATE(bp0)(float); +extern CONSTATTR float MATH_PRIVATE(ba0)(float); + +float +MATH_MANGLE(j0)(float x) +{ + x = BUILTIN_ABS_F32(x); + + const float b0 = 1.65625f; + const float b1 = 3.125f; + const float b2 = 4.6875f; + const float b3 = 6.265625f; + const float b4 = 7.84375f; + const float b5 = 9.421875f; + const float b6 = 10.984375f; + const float b7 = 12.578125f; + + float ret; + + if (x <= b7) { + // Ty to maintain relative accuracy here + + USE_TABLE(float, p, M32_J0); + float ch, cl; + + if (x <= b3) { + if (x <= b0) { + ch = 0x0.000000p+0f; + cl = 0x0.000000p+0f; + } else if (x <= b1) { + ch = 0x1.33d152p+1f; + cl = 0x1.d2e368p-24f; + p += 1*9; + } else if (x <= b2) { + ch = 0x1.ea7558p+1f; + cl = -0x1.4a121ep-24f; + p += 2*9; + } else { + ch = 0x1.6148f6p+2f; + cl = -0x1.34f46ep-24f; + p += 3*9; + } + } else { + if (x <= b4) { + ch = 0x1.c0ff60p+2f; + cl = -0x1.8971b6p-23f; + p += 4*9; + } else if (x <= b5) { + ch = 0x1.14eb56p+3f; + cl = 0x1.999bdap-22f; + p += 5*9; + } else if (x <= b6) { + ch = 0x1.458d0ep+3f; + cl = -0x1.e8407ap-22f; + p += 6*9; + } else { + ch = 0x1.795440p+3f; + cl = 0x1.04e56cp-26f; + p += 7*9; + } + } + + x = x - ch - cl; + ret = MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + p[8], p[7]), p[6]), p[5]), p[4]), + p[3]), p[2]), p[1]), p[0]); + } else { + float r = MATH_RCP(x); + float r2 = r*r; + float p = MATH_PRIVATE(bp0)(r2) * r; + ret = 0x1.988454p-1f * BUILTIN_AMDGPU_RSQRT_F32(x) * MATH_PRIVATE(ba0)(r2) * MATH_PRIVATE(cosb)(x, 0, p); + ret = x == PINF_F32 ? 0.0f : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/j0H.cl b/amd/device-libs/ocml/src/j0H.cl new file mode 100644 index 0000000000000..83feff6f04470 --- /dev/null +++ b/amd/device-libs/ocml/src/j0H.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +UGEN(j0) + +half +MATH_MANGLE(j0)(half x) +{ + return (half)MATH_UPMANGLE(j0)((float)x); +} + diff --git a/amd/device-libs/ocml/src/j1D.cl b/amd/device-libs/ocml/src/j1D.cl new file mode 100644 index 0000000000000..1884b4dc9d7d4 --- /dev/null +++ b/amd/device-libs/ocml/src/j1D.cl @@ -0,0 +1,96 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +extern double MATH_PRIVATE(cosb)(double, int, double); +extern CONSTATTR double MATH_PRIVATE(bp1)(double); +extern CONSTATTR double MATH_PRIVATE(ba1)(double); + + +double +MATH_MANGLE(j1)(double x) +{ + const double b0 = 1.09375; + const double b1 = 2.84375; + const double b2 = 4.578125; + const double b3 = 6.171875; + const double b4 = 7.78125; + const double b5 = 9.359375; + const double b6 = 10.953125; + const double b7 = 12.515625; + + double ax = BUILTIN_ABS_F64(x); + double ret; + + if (ax <= b7) { + // Ty to maintain relative accuracy here + + USE_TABLE(double, p, M64_J1); + double ch, cl; + + if (ax <= b3) { + if (ax <= b0) { + ch = 0.0; + cl = 0.0; + } else if (ax <= b1) { + ch = 0x1.d757d1fec8a3ap+0; + cl = 0x1.616d820cfdaebp-58; + p += 1*15; + } else if (ax <= b2) { + ch = 0x1.ea75575af6f09p+1; + cl = -0x1.60155a9d1b256p-53; + p += 2*15; + } else { + ch = 0x1.55365bc032467p+2; + cl = 0x1.5c646a75d7539p-53; + p += 3*15; + } + } else { + if (ax <= b4) { + ch = 0x1.c0ff5f3b47250p+2; + cl = -0x1.b226d9d243827p-54; + p += 4*15; + } else if (ax <= b5) { + ch = 0x1.112980f0b88a1p+3; + cl = -0x1.63e17ec20a31dp-53; + p += 5*15; + } else if (ax <= b6) { + ch = 0x1.458d0d0bdfc29p+3; + cl = 0x1.02610a51562b6p-51; + p += 6*15; + } else { + ch = 0x1.76979797ee5acp+3; + cl = 0x1.9a84d3a5fedc2p-51; + p += 7*15; + } + } + + ax = ax - ch - cl; + + ret = MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + MATH_MAD(ax, MATH_MAD(ax, + p[14], p[13]), p[12]), + p[11]), p[10]), p[9]), p[8]), + p[7]), p[6]), p[5]), p[4]), + p[3]), p[2]), p[1]), p[0]); + } else { + double r = MATH_RCP(ax); + double r2 = r*r; + double p = MATH_PRIVATE(bp1)(r2) * r; + ret = 0x1.9884533d43651p-1 * MATH_FAST_SQRT(r) * MATH_PRIVATE(ba1)(r2) * MATH_PRIVATE(cosb)(ax, 1, p); + ret = ax == PINF_F64 ? 0.0 : ret; + } + + if (x < 0.0) + ret = -ret; + + return ret; +} + diff --git a/amd/device-libs/ocml/src/j1F.cl b/amd/device-libs/ocml/src/j1F.cl new file mode 100644 index 0000000000000..dc510701faf99 --- /dev/null +++ b/amd/device-libs/ocml/src/j1F.cl @@ -0,0 +1,90 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +extern float MATH_PRIVATE(cosb)(float, int, float); +extern CONSTATTR float MATH_PRIVATE(bp1)(float); +extern CONSTATTR float MATH_PRIVATE(ba1)(float); + +float +MATH_MANGLE(j1)(float x) +{ + const float b0 = 1.09375f; + const float b1 = 2.84375f; + const float b2 = 4.578125f; + const float b3 = 6.171875f; + const float b4 = 7.78125f; + const float b5 = 9.359375f; + const float b6 = 10.953125f; + const float b7 = 12.515625f; + + float ax = BUILTIN_ABS_F32(x); + float ret; + + if (ax <= b7) { + // Ty to maintain relative accuracy here + + USE_TABLE(float, p, M32_J1); + float ch, cl; + + if (ax <= b3) { + if (ax <= b0) { + ch = 0.0f; + cl = 0.0f; + } else if (ax <= b1) { + ch = 0x1.d757d2p+0f; + cl = -0x1.375c60p-32f; + p += 1*9; + } else if (ax <= b2) { + ch = 0x1.ea7558p+1f; + cl = -0x1.4a121ep-24f; + p += 2*9; + } else { + ch = 0x1.55365cp+2f; + cl = -0x1.fe6dccp-25f; + p += 3*9; + } + } else { + if (ax <= b4) { + ch = 0x1.c0ff60p+2f; + cl = -0x1.8971b6p-23f; + p += 4*9; + } else if (ax <= b5) { + ch = 0x1.112980p+3f; + cl = 0x1.e17114p-22f; + p += 5*9; + } else if (ax <= b6) { + ch = 0x1.458d0ep+3f; + cl = -0x1.e8407ap-22f; + p += 6*9; + } else { + ch = 0x1.769798p+3f; + cl = -0x1.a04694p-23f; + p += 7*9; + } + } + + ax = ax - ch - cl; + ret = MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, + p[8], p[7]), p[6]), p[5]), p[4]), + p[3]), p[2]), p[1]), p[0]); + } else { + float r = MATH_RCP(ax); + float r2 = r*r; + float p = MATH_PRIVATE(bp1)(r2) * r; + ret = 0x1.988454p-1f * BUILTIN_AMDGPU_RSQRT_F32(ax) * MATH_PRIVATE(ba1)(r2) * MATH_PRIVATE(cosb)(ax, 1, p); + ret = ax == PINF_F32 ? 0.0f : ret; + } + + if (x < 0.0f) + ret = -ret; + + return ret; +} + diff --git a/amd/device-libs/ocml/src/j1H.cl b/amd/device-libs/ocml/src/j1H.cl new file mode 100644 index 0000000000000..557038f213d14 --- /dev/null +++ b/amd/device-libs/ocml/src/j1H.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +UGEN(j1) + +half +MATH_MANGLE(j1)(half x) +{ + return (half)MATH_UPMANGLE(j1)((float)x); +} + diff --git a/amd/device-libs/ocml/src/ldexpD.cl b/amd/device-libs/ocml/src/ldexpD.cl new file mode 100644 index 0000000000000..7ba482853fb95 --- /dev/null +++ b/amd/device-libs/ocml/src/ldexpD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(ldexp)(double x, int n) +{ + return BUILTIN_FLDEXP_F64(x, n); +} + diff --git a/amd/device-libs/ocml/src/ldexpF.cl b/amd/device-libs/ocml/src/ldexpF.cl new file mode 100644 index 0000000000000..29a1da2852346 --- /dev/null +++ b/amd/device-libs/ocml/src/ldexpF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(ldexp)(float x, int n) +{ + return BUILTIN_FLDEXP_F32(x, n); +} + diff --git a/amd/device-libs/ocml/src/ldexpH.cl b/amd/device-libs/ocml/src/ldexpH.cl new file mode 100644 index 0000000000000..59c43bf98b1c9 --- /dev/null +++ b/amd/device-libs/ocml/src/ldexpH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(ldexp)(half2 x, int2 n) +{ + return (half2)(MATH_MANGLE(ldexp)(x.lo, n.lo), MATH_MANGLE(ldexp)(x.hi, n.hi)); +} + +CONSTATTR half +MATH_MANGLE(ldexp)(half x, int n) +{ + return BUILTIN_FLDEXP_F16(x, n); +} + diff --git a/amd/device-libs/ocml/src/len3D.cl b/amd/device-libs/ocml/src/len3D.cl new file mode 100644 index 0000000000000..7884ccc82e78b --- /dev/null +++ b/amd/device-libs/ocml/src/len3D.cl @@ -0,0 +1,44 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(len3)(double x, double y, double z) +{ + double a = BUILTIN_ABS_F64(x); + double b = BUILTIN_ABS_F64(y); + double c = BUILTIN_ABS_F64(z); + + double a1 = BUILTIN_MAX_F64(a, b); + double b1 = BUILTIN_MIN_F64(a, b); + + a = BUILTIN_MAX_F64(a1, c); + double c1 = BUILTIN_MIN_F64(a1, c); + + b = BUILTIN_MAX_F64(b1, c1); + c = BUILTIN_MIN_F64(b1, c1); + + int e = BUILTIN_FREXP_EXP_F64(a); + a = BUILTIN_FLDEXP_F64(a, -e); + b = BUILTIN_FLDEXP_F64(b, -e); + c = BUILTIN_FLDEXP_F64(c, -e); + + double ret = BUILTIN_FLDEXP_F64(MATH_FAST_SQRT(MATH_MAD(a, a, MATH_MAD(b, b, c*c))), e); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISNAN_F64(x) | + BUILTIN_ISNAN_F64(y) | + BUILTIN_ISNAN_F64(z)) ? QNAN_F64 : ret; + ret = (BUILTIN_ISINF_F64(x) | + BUILTIN_ISINF_F64(y) | + BUILTIN_ISINF_F64(z)) ? PINF_F64 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/len3F.cl b/amd/device-libs/ocml/src/len3F.cl new file mode 100644 index 0000000000000..cee0e377e2dc6 --- /dev/null +++ b/amd/device-libs/ocml/src/len3F.cl @@ -0,0 +1,41 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(len3)(float x, float y, float z) +{ + float a = BUILTIN_ABS_F32(x); + float b = BUILTIN_ABS_F32(y); + float c = BUILTIN_ABS_F32(z); + + float a1 = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(a), AS_UINT(b))); + float b1 = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(a), AS_UINT(b))); + + a = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(a1), AS_UINT(c))); + float c1 = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(a1), AS_UINT(c))); + + b = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(b1), AS_UINT(c1))); + c = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(b1), AS_UINT(c1))); + + int e = BUILTIN_FREXP_EXP_F32(a); + a = BUILTIN_FLDEXP_F32(a, -e); + b = BUILTIN_FLDEXP_F32(b, -e); + c = BUILTIN_FLDEXP_F32(c, -e); + + float ret = BUILTIN_FLDEXP_F32(MATH_FAST_SQRT(MATH_MAD(a, a, MATH_MAD(b, b, c*c))), e); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F32(x) | + BUILTIN_ISINF_F32(y) | + BUILTIN_ISINF_F32(z)) ? PINF_F32 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/len3H.cl b/amd/device-libs/ocml/src/len3H.cl new file mode 100644 index 0000000000000..8f3777637c6d2 --- /dev/null +++ b/amd/device-libs/ocml/src/len3H.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_MANGLE(len3)(half x, half y, half z) +{ + float fx = (float)x; + float fy = (float)y; + float fz = (float)z; + + float d2 = MATH_MAD(fx, fx, MATH_MAD(fy, fy, fz*fz)); + + half ret = (half)BUILTIN_AMDGPU_SQRT_F32(d2); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F16(x) | + BUILTIN_ISINF_F16(y) | + BUILTIN_ISINF_F16(z)) ? PINF_F16 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/len4D.cl b/amd/device-libs/ocml/src/len4D.cl new file mode 100644 index 0000000000000..334a4cebf3c61 --- /dev/null +++ b/amd/device-libs/ocml/src/len4D.cl @@ -0,0 +1,52 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(len4)(double x, double y, double z, double w) +{ + double a = BUILTIN_ABS_F64(x); + double b = BUILTIN_ABS_F64(y); + double c = BUILTIN_ABS_F64(z); + double d = BUILTIN_ABS_F64(w); + + double a1 = BUILTIN_MAX_F64(a, b); + double b1 = BUILTIN_MIN_F64(a, b); + + double c1 = BUILTIN_MAX_F64(c, d); + double d1 = BUILTIN_MIN_F64(c, d); + + a = BUILTIN_MAX_F64(a1, c1); + double c2 = BUILTIN_MIN_F64(a1, c1); + + double b2 = BUILTIN_MAX_F64(b1, d1); + d = BUILTIN_MIN_F64(b1, d1); + + b = BUILTIN_MAX_F64(b2, c2); + c = BUILTIN_MIN_F64(b2, c2); + + int e = BUILTIN_FREXP_EXP_F64(a); + a = BUILTIN_FLDEXP_F64(a, -e); + b = BUILTIN_FLDEXP_F64(b, -e); + c = BUILTIN_FLDEXP_F64(c, -e); + d = BUILTIN_FLDEXP_F64(d, -e); + + double ret = BUILTIN_FLDEXP_F64(MATH_FAST_SQRT(MATH_MAD(a, a, MATH_MAD(b, b, MATH_MAD(c, c, d*d)))), e); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISUNORDERED_F64(x, y) | + BUILTIN_ISUNORDERED_F64(z, w)) ? QNAN_F64 : ret; + ret = (BUILTIN_ISINF_F64(x) | + BUILTIN_ISINF_F64(y) | + BUILTIN_ISINF_F64(z) | + BUILTIN_ISINF_F64(w)) ? PINF_F64 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/len4F.cl b/amd/device-libs/ocml/src/len4F.cl new file mode 100644 index 0000000000000..d0a352f41dc8e --- /dev/null +++ b/amd/device-libs/ocml/src/len4F.cl @@ -0,0 +1,50 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(len4)(float x, float y, float z, float w) +{ + float a = BUILTIN_ABS_F32(x); + float b = BUILTIN_ABS_F32(y); + float c = BUILTIN_ABS_F32(z); + float d = BUILTIN_ABS_F32(w); + + float a1 = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(a), AS_UINT(b))); + float b1 = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(a), AS_UINT(b))); + + float c1 = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(c), AS_UINT(d))); + float d1 = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(c), AS_UINT(d))); + + a = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(a1), AS_UINT(c1))); + float c2 = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(a1), AS_UINT(c1))); + + float b2 = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(b1), AS_UINT(d1))); + d = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(b1), AS_UINT(d1))); + + b = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(b2), AS_UINT(c2))); + c = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(b2), AS_UINT(c2))); + + int e = BUILTIN_FREXP_EXP_F32(a); + a = BUILTIN_FLDEXP_F32(a, -e); + b = BUILTIN_FLDEXP_F32(b, -e); + c = BUILTIN_FLDEXP_F32(c, -e); + d = BUILTIN_FLDEXP_F32(d, -e); + + float ret = BUILTIN_FLDEXP_F32(MATH_FAST_SQRT(MATH_MAD(a, a, MATH_MAD(b, b, MATH_MAD(c, c, d*d)))), e); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F32(x) | + BUILTIN_ISINF_F32(y) | + BUILTIN_ISINF_F32(z) | + BUILTIN_ISINF_F32(w)) ? PINF_F32 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/len4H.cl b/amd/device-libs/ocml/src/len4H.cl new file mode 100644 index 0000000000000..80178e7920bc2 --- /dev/null +++ b/amd/device-libs/ocml/src/len4H.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_MANGLE(len4)(half x, half y, half z, half w) +{ + float fx = (float)x; + float fy = (float)y; + float fz = (float)z; + float fw = (float)w; + + float d2 = MATH_MAD(fx, fx, MATH_MAD(fy, fy, MATH_MAD(fz, fz, fw*fw))); + + half ret = (half)BUILTIN_AMDGPU_SQRT_F32(d2); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F16(x) | + BUILTIN_ISINF_F16(y) | + BUILTIN_ISINF_F16(z) | + BUILTIN_ISINF_F16(w)) ? PINF_F16 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/lgammaD.cl b/amd/device-libs/ocml/src/lgammaD.cl new file mode 100644 index 0000000000000..69e502585499a --- /dev/null +++ b/amd/device-libs/ocml/src/lgammaD.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +double +MATH_MANGLE(lgamma)(double x) +{ + int s; + return MATH_MANGLE(lgamma_r)(x, &s); +} + diff --git a/amd/device-libs/ocml/src/lgammaF.cl b/amd/device-libs/ocml/src/lgammaF.cl new file mode 100644 index 0000000000000..4a113c1de0ce3 --- /dev/null +++ b/amd/device-libs/ocml/src/lgammaF.cl @@ -0,0 +1,16 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +float +MATH_MANGLE(lgamma)(float x) +{ + int s; + return MATH_MANGLE(lgamma_r)(x, &s); +} + diff --git a/amd/device-libs/ocml/src/lgammaH.cl b/amd/device-libs/ocml/src/lgammaH.cl new file mode 100644 index 0000000000000..81a0fcec96897 --- /dev/null +++ b/amd/device-libs/ocml/src/lgammaH.cl @@ -0,0 +1,18 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +UGEN(lgamma) + +half +MATH_MANGLE(lgamma)(half x) +{ + int s; + return MATH_MANGLE(lgamma_r)(x, &s); +} + diff --git a/amd/device-libs/ocml/src/lgamma_rD.cl b/amd/device-libs/ocml/src/lgamma_rD.cl new file mode 100644 index 0000000000000..c7514120e9888 --- /dev/null +++ b/amd/device-libs/ocml/src/lgamma_rD.cl @@ -0,0 +1,306 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +// This lgamma routine began with Sun's lgamma code from netlib. +// Their original copyright notice follows. +/* @(#)e_lgamma_r.c 1.3 95/01/18 */ +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunSoft, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + * + */ + +/* __ieee754_lgamma_r(x, signgamp) + * Reentrant version of the logarithm of the Gamma function + * with user provide pointer for the sign of Gamma(x). + * + * Method: + * 1. Argument Reduction for 0 < x <= 8 + * Since gamma(1+s)=s*gamma(s), for x in [0,8], we may + * reduce x to a number in [1.5,2.5] by + * lgamma(1+s) = log(s) + lgamma(s) + * for example, + * lgamma(7.3) = log(6.3) + lgamma(6.3) + * = log(6.3*5.3) + lgamma(5.3) + * = log(6.3*5.3*4.3*3.3*2.3) + lgamma(2.3) + * 2. Polynomial approximation of lgamma around its + * minimun ymin=1.461632144968362245 to maintain monotonicity. + * On [ymin-0.23, ymin+0.27] (i.e., [1.23164,1.73163]), use + * Let z = x-ymin; + * lgamma(x) = -1.214862905358496078218 + z^2*poly(z) + * where + * poly(z) is a 14 degree polynomial. + * 2. Rational approximation in the primary interval [2,3] + * We use the following approximation: + * s = x-2.0; + * lgamma(x) = 0.5*s + s*P(s)/Q(s) + * with accuracy + * |P/Q - (lgamma(x)-0.5s)| < 2**-61.71 + * Our algorithms are based on the following observation + * + * zeta(2)-1 2 zeta(3)-1 3 + * lgamma(2+s) = s*(1-Euler) + --------- * s - --------- * s + ... + * 2 3 + * + * where Euler = 0.5771... is the Euler constant, which is very + * close to 0.5. + * + * 3. For x>=8, we have + * lgamma(x)~(x-0.5)log(x)-x+0.5*log(2pi)+1/(12x)-1/(360x**3)+.... + * (better formula: + * lgamma(x)~(x-0.5)*(log(x)-1)-.5*(log(2pi)-1) + ...) + * Let z = 1/x, then we approximation + * f(z) = lgamma(x) - (x-0.5)(log(x)-1) + * by + * 3 5 11 + * w = w0 + w1*z + w2*z + w3*z + ... + w6*z + * where + * |w - f(z)| < 2**-58.74 + * + * 4. For negative x, since (G is gamma function) + * -x*G(-x)*G(x) = pi/sin(pi*x), + * we have + * G(x) = pi/(sin(pi*x)*(-x)*G(-x)) + * since G(-x) is positive, sign(G(x)) = sign(sin(pi*x)) for x<0 + * Hence, for x<0, signgam = sign(sin(pi*x)) and + * lgamma(x) = log(|Gamma(x)|) + * = log(pi/(|x*sin(pi*x)|)) - lgamma(-x); + * Note: one should avoid compute pi*(-x) directly in the + * computation of sin(pi*(-x)). + * + * 5. Special Cases + * lgamma(2+s) ~ s*(1-Euler) for tiny s + * lgamma(1)=lgamma(2)=0 + * lgamma(x) ~ -log(x) for tiny x + * lgamma(0) = lgamma(inf) = inf + * lgamma(-integer) = +-inf + * + */ + + +struct ret_t { + double result; + int signp; +}; + +static struct ret_t +MATH_MANGLE(lgamma_r_impl)(double x) +{ + const double two52= 4.50359962737049600000e+15; + const double pi = 3.14159265358979311600e+00; + const double a0 = 7.72156649015328655494e-02; + const double a1 = 3.22467033424113591611e-01; + const double a2 = 6.73523010531292681824e-02; + const double a3 = 2.05808084325167332806e-02; + const double a4 = 7.38555086081402883957e-03; + const double a5 = 2.89051383673415629091e-03; + const double a6 = 1.19270763183362067845e-03; + const double a7 = 5.10069792153511336608e-04; + const double a8 = 2.20862790713908385557e-04; + const double a9 = 1.08011567247583939954e-04; + const double a10 = 2.52144565451257326939e-05; + const double a11 = 4.48640949618915160150e-05; + const double tc = 1.46163214496836224576e+00; + const double tf = -1.21486290535849611461e-01; + const double tt = -3.63867699703950536541e-18; + const double t0 = 4.83836122723810047042e-01; + const double t1 = -1.47587722994593911752e-01; + const double t2 = 6.46249402391333854778e-02; + const double t3 = -3.27885410759859649565e-02; + const double t4 = 1.79706750811820387126e-02; + const double t5 = -1.03142241298341437450e-02; + const double t6 = 6.10053870246291332635e-03; + const double t7 = -3.68452016781138256760e-03; + const double t8 = 2.25964780900612472250e-03; + const double t9 = -1.40346469989232843813e-03; + const double t10 = 8.81081882437654011382e-04; + const double t11 = -5.38595305356740546715e-04; + const double t12 = 3.15632070903625950361e-04; + const double t13 = -3.12754168375120860518e-04; + const double t14 = 3.35529192635519073543e-04; + const double u0 = -7.72156649015328655494e-02; + const double u1 = 6.32827064025093366517e-01; + const double u2 = 1.45492250137234768737e+00; + const double u3 = 9.77717527963372745603e-01; + const double u4 = 2.28963728064692451092e-01; + const double u5 = 1.33810918536787660377e-02; + const double v1 = 2.45597793713041134822e+00; + const double v2 = 2.12848976379893395361e+00; + const double v3 = 7.69285150456672783825e-01; + const double v4 = 1.04222645593369134254e-01; + const double v5 = 3.21709242282423911810e-03; + const double s0 = -7.72156649015328655494e-02; + const double s1 = 2.14982415960608852501e-01; + const double s2 = 3.25778796408930981787e-01; + const double s3 = 1.46350472652464452805e-01; + const double s4 = 2.66422703033638609560e-02; + const double s5 = 1.84028451407337715652e-03; + const double s6 = 3.19475326584100867617e-05; + const double r1 = 1.39200533467621045958e+00; + const double r2 = 7.21935547567138069525e-01; + const double r3 = 1.71933865632803078993e-01; + const double r4 = 1.86459191715652901344e-02; + const double r5 = 7.77942496381893596434e-04; + const double r6 = 7.32668430744625636189e-06; + const double w0 = 4.18938533204672725052e-01; + const double w1 = 8.33333333333329678849e-02; + const double w2 = -2.77777777728775536470e-03; + const double w3 = 7.93650558643019558500e-04; + const double w4 = -5.95187557450339963135e-04; + const double w5 = 8.36339918996282139126e-04; + const double w6 = -1.63092934096575273989e-03; + const double z1 = -0x1.2788cfc6fb619p-1; + const double z2 = 0x1.a51a6625307d3p-1; + const double z3 = -0x1.9a4d55beab2d7p-2; + const double z4 = 0x1.151322ac7d848p-2; + const double z5 = -0x1.a8b9c17aa6149p-3; + + double ax = BUILTIN_ABS_F64(x); + uint hax = AS_UINT2(ax).hi; + double ret; + + if (hax < 0x3f700000) { + // ax < 0x1.0p-8 + ret = MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, z5, z4), z3), z2), z1), + -MATH_MANGLE(log)(ax)); + } else if (hax < 0x40000000) { + // ax < 2.0 + int i; + bool c; + double y, t; + if (hax <= 0x3feccccc) { // |x| < 0.9 : lgamma(x) = lgamma(x+1)-log(x) + ret = -MATH_MANGLE(log)(ax); + + y = 1.0 - ax; + i = 0; + + c = hax < 0x3FE76944; // x < 0.7316 + t = ax - (tc - 1.0); + y = c ? t : y; + i = c ? 1 : i; + + c = hax < 0x3FCDA661; // x < .2316 + y = c ? ax : y; + i = c ? 2 : i; + } else { + ret = 0.0; + + y = 2.0 - ax; + i = 0; + + c = hax < 0x3FFBB4C3; // x < 1.7316 + t = ax - tc; + y = c ? t : y; + i = c ? 1 : i; + + c = hax < 0x3FF3B4C4; // x < 1.2316 + t = ax - 1.0; + y = c ? t : y; + i = c ? 2 : i; + } + + double w, z, p, p1, p2, p3; + switch(i) { + case 0: + z = y*y; + p1 = MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, a10, a8), a6), a4), a2), a0); + p2 = z * MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, a11, a9), a7), a5), a3), a1); + p = MATH_MAD(y, p1, p2); + ret += MATH_MAD(y, -0.5, p); + break; + case 1: + z = y*y; + w = z*y; + p1 = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, t12, t9), t6), t3), t0); + p2 = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, t13, t10), t7), t4), t1); + p3 = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, t14, t11), t8), t5), t2); + p = MATH_MAD(z, p1, -MATH_MAD(w, -MATH_MAD(y, p3,p2), tt)); + ret += tf + p; + break; + case 2: + p1 = y * MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, u5, u4), u3), u2), u1), u0); + p2 = MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, v5, v4), v3), v2), v1), 1.0); + ret += MATH_MAD(y, -0.5, MATH_DIV(p1, p2)); + break; + } + } else if (hax < 0x40200000) { // 2 < ax < 8 + int i = (int)ax; + double y = ax - (double)i; + double p = y * MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, s6, s5), s4), s3), s2), s1), s0); + double q = MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, r6, r5), r4), r3), r2), r1), 1.0); + ret = MATH_MAD(y, 0.5, MATH_DIV(p, q)); + + double y2 = y + 2.0; + double y3 = y + 3.0; + double y4 = y + 4.0; + double y5 = y + 5.0; + double y6 = y + 6.0; + + double z = 1.0; + z *= i > 2 ? y2 : 1.0; + z *= i > 3 ? y3 : 1.0; + z *= i > 4 ? y4 : 1.0; + z *= i > 5 ? y5 : 1.0; + z *= i > 6 ? y6 : 1.0; + + ret += MATH_MANGLE(log)(z); + } else if (hax < 0x43900000) { // 8 <= ax < 2^58 + double z = MATH_RCP(ax); + double y = z*z; + double w = MATH_MAD(z, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, w6, w5), w4), w3), w2), w1), w0); + ret = MATH_MAD(ax - 0.5, MATH_MANGLE(log)(ax) - 1.0, w); + } else { // 2^58 <= ax <= Inf + ret = MATH_MAD(ax, MATH_MANGLE(log)(ax), -ax); + } + + + int s = 0; + if (x >= 0.0) { + ret = (x == 1.0 | x == 2.0) ? 0.0 : ret; + s = x == 0.0 ? 0 : 1; + } else if (hax < 0x43300000) { // x > -0x1.0p+52 + if (hax > 0x3cd00000) { // x < -0x1.0p-50 + double t = MATH_MANGLE(sinpi)(x); + double negadj = MATH_MANGLE(log)(MATH_DIV(pi, BUILTIN_ABS_F64(t * x))); + ret = negadj - ret; + bool z = BUILTIN_FRACTION_F64(x) == 0.0; + ret = z ? PINF_F64 : ret; + s = t < 0.0 ? -1 : 1; + s = z ? 0 : s; + } else { + s = -1; + } + } + + if (!FINITE_ONLY_OPT()) { + // Handle negative integer, Inf, NaN + ret = BUILTIN_CLASS_F64(ax, CLASS_NZER|CLASS_PZER|CLASS_PINF) | (x < 0.0f & hax >= 0x43300000) ? PINF_F64 : ret; + ret = BUILTIN_ISNAN_F64(x) ? x : ret; + } + + struct ret_t result; + result.result = ret; + result.signp = s; + return result; +} + + +double +MATH_MANGLE(lgamma_r)(double x, __private int *signp) +{ + struct ret_t ret = MATH_MANGLE(lgamma_r_impl)(x); + *signp = ret.signp; + return ret.result; +} diff --git a/amd/device-libs/ocml/src/lgamma_rF.cl b/amd/device-libs/ocml/src/lgamma_rF.cl new file mode 100644 index 0000000000000..c822b66c6b488 --- /dev/null +++ b/amd/device-libs/ocml/src/lgamma_rF.cl @@ -0,0 +1,298 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +// This lgamma routine began with Sun's lgamma code from netlib. +// Their original copyright notice follows. +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunSoft, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + * + */ + +/* Reentrant version of the logarithm of the Gamma function + * with user provide pointer for the sign of Gamma(x). + * + * Method: + * 1. Argument Reduction for 0 < x <= 8 + * Since gamma(1+s)=s*gamma(s), for x in [0,8], we may + * reduce x to a number in [1.5,2.5] by + * lgamma(1+s) = log(s) + lgamma(s) + * for example, + * lgamma(7.3) = log(6.3) + lgamma(6.3) + * = log(6.3*5.3) + lgamma(5.3) + * = log(6.3*5.3*4.3*3.3*2.3) + lgamma(2.3) + * 2. Polynomial approximation of lgamma around its + * minimun ymin=1.461632144968362245 to maintain monotonicity. + * On [ymin-0.23, ymin+0.27] (i.e., [1.23164,1.73163]), use + * Let z = x-ymin; + * lgamma(x) = -1.214862905358496078218 + z^2*poly(z) + * where + * poly(z) is a 14 degree polynomial. + * 2. Rational approximation in the primary interval [2,3] + * We use the following approximation: + * s = x-2.0; + * lgamma(x) = 0.5*s + s*P(s)/Q(s) + * with accuracy + * |P/Q - (lgamma(x)-0.5s)| < 2**-61.71 + * Our algorithms are based on the following observation + * + * zeta(2)-1 2 zeta(3)-1 3 + * lgamma(2+s) = s*(1-Euler) + --------- * s - --------- * s + ... + * 2 3 + * + * where Euler = 0.5771... is the Euler constant, which is very + * close to 0.5. + * + * 3. For x>=8, we have + * lgamma(x)~(x-0.5)log(x)-x+0.5*log(2pi)+1/(12x)-1/(360x**3)+.... + * (better formula: + * lgamma(x)~(x-0.5)*(log(x)-1)-.5*(log(2pi)-1) + ...) + * Let z = 1/x, then we approximation + * f(z) = lgamma(x) - (x-0.5)(log(x)-1) + * by + * 3 5 11 + * w = w0 + w1*z + w2*z + w3*z + ... + w6*z + * where + * |w - f(z)| < 2**-58.74 + * + * 4. For negative x, since (G is gamma function) + * -x*G(-x)*G(x) = pi/sin(pi*x), + * we have + * G(x) = pi/(sin(pi*x)*(-x)*G(-x)) + * since G(-x) is positive, sign(G(x)) = sign(sin(pi*x)) for x<0 + * Hence, for x<0, signgam = sign(sin(pi*x)) and + * lgamma(x) = log(|Gamma(x)|) + * = log(pi/(|x*sin(pi*x)|)) - lgamma(-x); + * Note: one should avoid compute pi*(-x) directly in the + * computation of sin(pi*(-x)). + * + * 5. Special Cases + * lgamma(2+s) ~ s*(1-Euler) for tiny s + * lgamma(1)=lgamma(2)=0 + * lgamma(x) ~ -log(x) for tiny x + * lgamma(0) = lgamma(inf) = inf + * lgamma(-integer) = +-inf + * + */ + +struct ret_t { + float result; + int signp; +}; + +static struct ret_t +MATH_MANGLE(lgamma_r_impl)(float x) +{ + const float two52 = 4.50359962737049600000e+15f; + const float pi = 3.14159265358979311600e+00f; + const float a0 = 7.72156649015328655494e-02f; + const float a1 = 3.22467033424113591611e-01f; + const float a2 = 6.73523010531292681824e-02f; + const float a3 = 2.05808084325167332806e-02f; + const float a4 = 7.38555086081402883957e-03f; + const float a5 = 2.89051383673415629091e-03f; + const float a6 = 1.19270763183362067845e-03f; + const float a7 = 5.10069792153511336608e-04f; + const float a8 = 2.20862790713908385557e-04f; + const float a9 = 1.08011567247583939954e-04f; + const float a10 = 2.52144565451257326939e-05f; + const float a11 = 4.48640949618915160150e-05f; + const float tc = 1.46163214496836224576e+00f; + const float tf = -1.21486290535849611461e-01f; + const float tt = -3.63867699703950536541e-18f; + const float t0 = 4.83836122723810047042e-01f; + const float t1 = -1.47587722994593911752e-01f; + const float t2 = 6.46249402391333854778e-02f; + const float t3 = -3.27885410759859649565e-02f; + const float t4 = 1.79706750811820387126e-02f; + const float t5 = -1.03142241298341437450e-02f; + const float t6 = 6.10053870246291332635e-03f; + const float t7 = -3.68452016781138256760e-03f; + const float t8 = 2.25964780900612472250e-03f; + const float t9 = -1.40346469989232843813e-03f; + const float t10 = 8.81081882437654011382e-04f; + const float t11 = -5.38595305356740546715e-04f; + const float t12 = 3.15632070903625950361e-04f; + const float t13 = -3.12754168375120860518e-04f; + const float t14 = 3.35529192635519073543e-04f; + const float u0 = -7.72156649015328655494e-02f; + const float u1 = 6.32827064025093366517e-01f; + const float u2 = 1.45492250137234768737e+00f; + const float u3 = 9.77717527963372745603e-01f; + const float u4 = 2.28963728064692451092e-01f; + const float u5 = 1.33810918536787660377e-02f; + const float v1 = 2.45597793713041134822e+00f; + const float v2 = 2.12848976379893395361e+00f; + const float v3 = 7.69285150456672783825e-01f; + const float v4 = 1.04222645593369134254e-01f; + const float v5 = 3.21709242282423911810e-03f; + const float s0 = -7.72156649015328655494e-02f; + const float s1 = 2.14982415960608852501e-01f; + const float s2 = 3.25778796408930981787e-01f; + const float s3 = 1.46350472652464452805e-01f; + const float s4 = 2.66422703033638609560e-02f; + const float s5 = 1.84028451407337715652e-03f; + const float s6 = 3.19475326584100867617e-05f; + const float r1 = 1.39200533467621045958e+00f; + const float r2 = 7.21935547567138069525e-01f; + const float r3 = 1.71933865632803078993e-01f; + const float r4 = 1.86459191715652901344e-02f; + const float r5 = 7.77942496381893596434e-04f; + const float r6 = 7.32668430744625636189e-06f; + const float w0 = 4.18938533204672725052e-01f; + const float w1 = 8.33333333333329678849e-02f; + const float w2 = -2.77777777728775536470e-03f; + const float w3 = 7.93650558643019558500e-04f; + const float w4 = -5.95187557450339963135e-04f; + const float w5 = 8.36339918996282139126e-04f; + const float w6 = -1.63092934096575273989e-03f; + const float z1 = -0x1.2788d0p-1f; + const float z2 = 0x1.a51a66p-1f; + const float z3 = -0x1.9a4d56p-2f; + const float z4 = 0x1.151322p-2f; + + float ax = BUILTIN_ABS_F32(x); + float ret; + + if (ax < 0x1.0p-6f) { + ret = MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, MATH_MAD(ax, z4, z3), z2), z1), + -MATH_MANGLE(log)(ax)); + } else if (ax < 2.0f) { + int i; + bool c; + float y, t; + if( ax <= 0.9f) { // lgamma(x) = lgamma(x+1)-log(x) + ret = -MATH_MANGLE(log)(ax); + y = 1.0f - ax; + i = 0; + + c = ax < 0.7316f; + t = ax - (tc - 1.0f); + y = c ? t : y; + i = c ? 1 : i; + + c = ax < 0.23164f; + y = c ? ax : y; + i = c ? 2 : i; + } else { + ret = 0.0f; + y = 2.0f - ax; + i = 0; + + c = ax < 1.7316f; + t = ax - tc; + y = c ? t : y; + i = c ? 1 : y; + + c = ax < 1.23f; + t = ax - 1.0f; + y = c ? t : y; + i = c ? 2 : i; + } + + float z, w, p1, p2, p3, p; + switch(i) { + case 0: + z = y * y; + p1 = MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, a10, a8), a6), a4), a2), a0); + p2 = z * MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, MATH_MAD(z, a11, a9), a7), a5), a3), a1); + p = MATH_MAD(y, p1, p2); + ret += MATH_MAD(y, -0.5f, p); + break; + case 1: + z = y * y; + w = z * y; + p1 = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, t12, t9), t6), t3), t0); + p2 = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, t13, t10), t7), t4), t1); + p3 = MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, MATH_MAD(w, t14, t11), t8), t5), t2); + p = MATH_MAD(z, p1, -MATH_MAD(w, -MATH_MAD(y, p3, p2), tt)); + ret += tf + p; + break; + case 2: + p1 = y * MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, u5, u4), u3), u2), u1), u0); + p2 = MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, v5, v4), v3), v2), v1), 1.0f); + ret += MATH_MAD(y, -0.5f, MATH_FAST_DIV(p1, p2)); + break; + } + } else if (ax < 8.0f) { // 2 < |x| < 8 + int i = (int)ax; + float y = ax - (float) i; + float p = y * MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, s6, s5), s4), s3), s2), s1), s0); + float q = MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, r6, r5), r4), r3), r2), r1), 1.0f); + ret = MATH_MAD(y, 0.5f, MATH_FAST_DIV(p, q)); + + float y2 = y + 2.0f; + float y3 = y + 3.0f; + float y4 = y + 4.0f; + float y5 = y + 5.0f; + float y6 = y + 6.0f; + + float z = 1.0f; + z *= i > 2 ? y2 : 1.0f; + z *= i > 3 ? y3 : 1.0f; + z *= i > 4 ? y4 : 1.0f; + z *= i > 5 ? y5 : 1.0f; + z *= i > 6 ? y6 : 1.0f; + + ret += MATH_MANGLE(log)(z); + } else if (ax < 0x1.0p+58f) { // 8 <= |x| < 2^58 + float z = MATH_FAST_RCP(ax); + float y = z * z; + float w = MATH_MAD(z, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, w6, w5), w4), w3), w2), w1), w0); + ret = MATH_MAD(ax - 0.5f, MATH_MANGLE(log)(ax) - 1.0f, w); + } else { + // 2^58 <= |x| <= Inf + ret = MATH_MAD(ax, MATH_MANGLE(log)(ax), -ax); + } + + int s = 0; + if (x >= 0.0f) { + ret = ((x == 1.0f) | (x == 2.0f)) ? 0.0f : ret; + s = x == 0.0f ? 0 : 1; + } else if (ax < 0x1.0p+23f) { // x > -0x1.0p+23 + if (ax > 0x1.0p-21f) { + float t = MATH_MANGLE(sinpi)(x); + float negadj = MATH_MANGLE(log)(MATH_DIV(pi, BUILTIN_ABS_F32(t * x))); + ret = negadj - ret; + bool z = BUILTIN_FRACTION_F32(x) == 0.0f; + ret = z ? PINF_F32 : ret; + s = t < 0.0f ? -1 : 1; + s = z ? 0 : s; + } else { + s = -1; + } + } + + if (!FINITE_ONLY_OPT()) { + ret = ((ax != 0.0f) && !BUILTIN_ISINF_F32(ax) && + ((x >= 0.0f) || (ax < 0x1.0p+23f))) ? ret : PINF_F32; + + ret = BUILTIN_ISNAN_F32(x) ? x : ret; + } + + struct ret_t result; + result.result = ret; + result.signp = s; + + return result; +} + +float +MATH_MANGLE(lgamma_r)(float x, __private int *signp) +{ + struct ret_t ret = MATH_MANGLE(lgamma_r_impl)(x); + *signp = ret.signp; + return ret.result; +} diff --git a/amd/device-libs/ocml/src/lgamma_rH.cl b/amd/device-libs/ocml/src/lgamma_rH.cl new file mode 100644 index 0000000000000..b1f6d4854424f --- /dev/null +++ b/amd/device-libs/ocml/src/lgamma_rH.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +half2 +MATH_MANGLE2(lgamma_r)(half2 x, __private int2 *signp) +{ + int slo, shi; + half2 r; + r.lo = MATH_MANGLE(lgamma_r)(x.lo, &slo); + r.hi = MATH_MANGLE(lgamma_r)(x.hi, &shi); + *signp = (int2)(slo, shi); + return r; +} + +half +MATH_MANGLE(lgamma_r)(half x, __private int *signp) +{ + return (half)MATH_UPMANGLE(lgamma_r)((float)x, signp); +} + diff --git a/amd/device-libs/ocml/src/lnepD.cl b/amd/device-libs/ocml/src/lnepD.cl new file mode 100644 index 0000000000000..449cb7f3ebdc8 --- /dev/null +++ b/amd/device-libs/ocml/src/lnepD.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double +MATH_PRIVATE(lnep)(double2 a, int ea) +{ + int b = BUILTIN_FREXP_MANT_F64(a.hi) < (2.0/3.0); + int e = BUILTIN_FREXP_EXP_F64(a.hi) - b; + double2 m = ldx(a, -e); + double2 x = div(fadd(-1.0, m), fadd(1.0, m)); + double s = x.hi * x.hi; + double p = MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, + MATH_MAD(s, MATH_MAD(s, + 0x1.3ab76bf559e2bp-3, 0x1.385386b47b09ap-3), 0x1.7474dd7f4df2ep-3), 0x1.c71c016291751p-3), + 0x1.249249b27acf1p-2), 0x1.99999998ef7b6p-2), 0x1.5555555555780p-1); + double2 r = add(mul(con(0x1.62e42fefa39efp-1, 0x1.abc9e3b39803fp-56), (double)(e + ea)), + fadd(ldx(x,1), s * x.hi * p)); + return r.hi; +} + diff --git a/amd/device-libs/ocml/src/lnepF.cl b/amd/device-libs/ocml/src/lnepF.cl new file mode 100644 index 0000000000000..4cc43621ff7cf --- /dev/null +++ b/amd/device-libs/ocml/src/lnepF.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +CONSTATTR float +MATH_PRIVATE(lnep)(float2 a, int ea) +{ + int b = BUILTIN_FREXP_MANT_F32(a.hi) < (2.0f/3.0f); + int e = BUILTIN_FREXP_EXP_F32(a.hi) - b; + float2 m = ldx(a, -e); + float2 x = div(fadd(-1.0f, m), fadd(1.0f, m)); + float s = x.hi * x.hi; + float p = MATH_MAD(s, MATH_MAD(s, 0x1.36db58p-2f, 0x1.992b46p-2f), 0x1.5555b4p-1f); + float2 r = add(mul(con(0x1.62e430p-1f, -0x1.05c610p-29f), (float)(e + ea)), + fadd(ldx(x,1), s * x.hi * p)); + return r.hi; +} + diff --git a/amd/device-libs/ocml/src/log10D.cl b/amd/device-libs/ocml/src/log10D.cl new file mode 100644 index 0000000000000..6e2c52fcf8e5d --- /dev/null +++ b/amd/device-libs/ocml/src/log10D.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_LOG10 +#include "logD_base.h" + diff --git a/amd/device-libs/ocml/src/log10F.cl b/amd/device-libs/ocml/src/log10F.cl new file mode 100644 index 0000000000000..634affc99b6b8 --- /dev/null +++ b/amd/device-libs/ocml/src/log10F.cl @@ -0,0 +1,13 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(log10)(float x) { + return BUILTIN_LOG10_F32(x); +} diff --git a/amd/device-libs/ocml/src/log10H.cl b/amd/device-libs/ocml/src/log10H.cl new file mode 100644 index 0000000000000..e0807bf03502d --- /dev/null +++ b/amd/device-libs/ocml/src/log10H.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(log10) + +CONSTATTR half +MATH_MANGLE(log10)(half x) +{ + return (half)(BUILTIN_AMDGPU_LOG2_F32((float)x) * 0x1.344136p-2f); +} + diff --git a/amd/device-libs/ocml/src/log1pD.cl b/amd/device-libs/ocml/src/log1pD.cl new file mode 100644 index 0000000000000..12a9b45cdfca4 --- /dev/null +++ b/amd/device-libs/ocml/src/log1pD.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +extern CONSTATTR double MATH_PRIVATE(lnep)(double2 a, int ea); + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double +MATH_MANGLE(log1p)(double x) +{ + double z = MATH_PRIVATE(lnep)(add(1.0, x), 0); + + if (!FINITE_ONLY_OPT()) { + z = x == PINF_F64 ? x : z; + z = x < -1.0 ? QNAN_F64 : z; + z = x == -1.0 ? NINF_F64 : z; + } + + return z; +} + diff --git a/amd/device-libs/ocml/src/log1pF.cl b/amd/device-libs/ocml/src/log1pF.cl new file mode 100644 index 0000000000000..53a33096f05f5 --- /dev/null +++ b/amd/device-libs/ocml/src/log1pF.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float MATH_PRIVATE(lnep)(float2 a, int ea); + +CONSTATTR float +MATH_MANGLE(log1p)(float x) +{ + float z = MATH_PRIVATE(lnep)(add(1.0f, x), 0); + + if (!FINITE_ONLY_OPT()) { + z = x == PINF_F32 ? x : z; + z = x < -1.0f ? QNAN_F32 : z; + z = x == -1.0f ? NINF_F32 : z; + } + + return BUILTIN_ABS_F32(x) < 0x1.0p-24f ? x : z; +} + diff --git a/amd/device-libs/ocml/src/log1pH.cl b/amd/device-libs/ocml/src/log1pH.cl new file mode 100644 index 0000000000000..69e7eda79ab8a --- /dev/null +++ b/amd/device-libs/ocml/src/log1pH.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(log1p) + +CONSTATTR half +MATH_MANGLE(log1p)(half x) +{ + half ret; + ret = (half)(BUILTIN_AMDGPU_LOG2_F32((float)x + 1.0f) * 0x1.62e430p-1f); + half p = MATH_MAD(x, x*MATH_MAD(x, 0x1.555556p-2h, -0.5h), x); + ret = BUILTIN_ABS_F16(x) < 0x1.0p-6h ? p : ret; + + return ret; +} + diff --git a/amd/device-libs/ocml/src/log2D.cl b/amd/device-libs/ocml/src/log2D.cl new file mode 100644 index 0000000000000..099ac40aabe15 --- /dev/null +++ b/amd/device-libs/ocml/src/log2D.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_LOG2 +#include "logD_base.h" + diff --git a/amd/device-libs/ocml/src/log2F.cl b/amd/device-libs/ocml/src/log2F.cl new file mode 100644 index 0000000000000..5489ac5152ad3 --- /dev/null +++ b/amd/device-libs/ocml/src/log2F.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(log2)(float x) { + return BUILTIN_LOG2_F32(x); +} + diff --git a/amd/device-libs/ocml/src/log2H.cl b/amd/device-libs/ocml/src/log2H.cl new file mode 100644 index 0000000000000..e115e1011d4bd --- /dev/null +++ b/amd/device-libs/ocml/src/log2H.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(log2) + +CONSTATTR half +MATH_MANGLE(log2)(half x) +{ + return BUILTIN_LOG2_F16(x); +} + diff --git a/amd/device-libs/ocml/src/logD.cl b/amd/device-libs/ocml/src/logD.cl new file mode 100644 index 0000000000000..9d60ed58d7447 --- /dev/null +++ b/amd/device-libs/ocml/src/logD.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_LOG +#include "logD_base.h" + diff --git a/amd/device-libs/ocml/src/logD_base.h b/amd/device-libs/ocml/src/logD_base.h new file mode 100644 index 0000000000000..ff5b916da15d9 --- /dev/null +++ b/amd/device-libs/ocml/src/logD_base.h @@ -0,0 +1,54 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +CONSTATTR double +#if defined(COMPILING_LOG2) +MATH_MANGLE(log2)(double a) +#elif defined(COMPILING_LOG10) +MATH_MANGLE(log10)(double a) +#else +MATH_MANGLE(log)(double a) +#endif +{ + double m = BUILTIN_FREXP_MANT_F64(a); + int b = m < (2.0/3.0); + m = BUILTIN_FLDEXP_F64(m, b); + int e = BUILTIN_FREXP_EXP_F64(a) - b; + + double2 x = div(m - 1.0, fadd(1.0, m)); + double s = x.hi * x.hi; + double p = MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, + MATH_MAD(s, MATH_MAD(s, + 0x1.3ab76bf559e2bp-3, 0x1.385386b47b09ap-3), 0x1.7474dd7f4df2ep-3), 0x1.c71c016291751p-3), + 0x1.249249b27acf1p-2), 0x1.99999998ef7b6p-2), 0x1.5555555555780p-1); + double2 r = fadd(ldx(x,1), s*x.hi*p); + +#if defined COMPILING_LOG2 + r = add((double)e, mul(con(0x1.71547652b82fep+0,0x1.777d0ffda0d24p-56), r)); +#elif defined COMPILING_LOG10 + r = add(mul(con(0x1.34413509f79ffp-2, -0x1.9dc1da994fd21p-59), (double)e), + mul(con(0x1.bcb7b1526e50ep-2, 0x1.95355baaafad3p-57), r)); +#else + r = add(mul(con(0x1.62e42fefa39efp-1, 0x1.abc9e3b39803fp-56), (double)e), r); +#endif + + double ret = r.hi; + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_ISINF_F64(a) ? a : ret; + ret = a < 0.0 ? QNAN_F64 : ret; + ret = a == 0.0 ? NINF_F64 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/logF.cl b/amd/device-libs/ocml/src/logF.cl new file mode 100644 index 0000000000000..a335d37be3802 --- /dev/null +++ b/amd/device-libs/ocml/src/logF.cl @@ -0,0 +1,13 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(log)(float x) { + return BUILTIN_LOG_F32(x); +} diff --git a/amd/device-libs/ocml/src/logH.cl b/amd/device-libs/ocml/src/logH.cl new file mode 100644 index 0000000000000..73cd6cd1ee3f1 --- /dev/null +++ b/amd/device-libs/ocml/src/logH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(log) + +CONSTATTR half +MATH_MANGLE(log)(half x) +{ + return (half)(BUILTIN_AMDGPU_LOG2_F32((float)x) * 0x1.62e430p-1f); +} + diff --git a/amd/device-libs/ocml/src/logbD.cl b/amd/device-libs/ocml/src/logbD.cl new file mode 100644 index 0000000000000..e5eb431f41ac8 --- /dev/null +++ b/amd/device-libs/ocml/src/logbD.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(logb)(double x) +{ + double ret = (double)(BUILTIN_FREXP_EXP_F64(x) - 1); + + if (!FINITE_ONLY_OPT()) { + double ax = BUILTIN_ABS_F64(x); + ret = BUILTIN_ISFINITE_F64(ax) ? ret : ax; + ret = x == 0.0 ? NINF_F64 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/logbF.cl b/amd/device-libs/ocml/src/logbF.cl new file mode 100644 index 0000000000000..d8a424255d932 --- /dev/null +++ b/amd/device-libs/ocml/src/logbF.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(logb)(float x) +{ + float ret = (float)(BUILTIN_FREXP_EXP_F32(x) - 1); + + if (!FINITE_ONLY_OPT()) { + float ax = BUILTIN_ABS_F32(x); + ret = BUILTIN_ISFINITE_F32(ax) ? ret : ax; + ret = x == 0.0f ? NINF_F32 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/logbH.cl b/amd/device-libs/ocml/src/logbH.cl new file mode 100644 index 0000000000000..1e32ec4a096f7 --- /dev/null +++ b/amd/device-libs/ocml/src/logbH.cl @@ -0,0 +1,25 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(logb) + +CONSTATTR half +MATH_MANGLE(logb)(half x) +{ + half ret = (half)(BUILTIN_FREXP_EXP_F16(x) - (short)1); + + if (!FINITE_ONLY_OPT()) { + half ax = BUILTIN_ABS_F16(x); + ret = BUILTIN_ISFINITE_F16(ax) ? ret : ax; + ret = x == 0.0h ? NINF_F16 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/madD.cl b/amd/device-libs/ocml/src/madD.cl new file mode 100644 index 0000000000000..293e3fceb8960 --- /dev/null +++ b/amd/device-libs/ocml/src/madD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(mad)(double a, double b, double c) +{ + return MATH_MAD(a, b, c); +} + diff --git a/amd/device-libs/ocml/src/madF.cl b/amd/device-libs/ocml/src/madF.cl new file mode 100644 index 0000000000000..2d8a16759ae0d --- /dev/null +++ b/amd/device-libs/ocml/src/madF.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float2 +MATH_MANGLE2(mad)(float2 a, float2 b, float2 c) +{ + return MATH_MAD2(a, b, c); +} + +CONSTATTR float +MATH_MANGLE(mad)(float a, float b, float c) +{ + return MATH_MAD(a, b, c); +} + diff --git a/amd/device-libs/ocml/src/madH.cl b/amd/device-libs/ocml/src/madH.cl new file mode 100644 index 0000000000000..4f3d393f86bcf --- /dev/null +++ b/amd/device-libs/ocml/src/madH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(mad)(half2 a, half2 b, half2 c) +{ + return MATH_MAD2(a, b, c); +} + +CONSTATTR half +MATH_MANGLE(mad)(half a, half b, half c) +{ + return MATH_MAD(a, b, c); +} + diff --git a/amd/device-libs/ocml/src/mathD.h b/amd/device-libs/ocml/src/mathD.h new file mode 100644 index 0000000000000..b0c3441819a4e --- /dev/null +++ b/amd/device-libs/ocml/src/mathD.h @@ -0,0 +1,56 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +// OCML prototypes +#include "ocml.h" + +// Tables +#include "tables.h" + +// Builtins +#include "builtins.h" + +// Mangling +#define MATH_MANGLE(N) OCML_MANGLE_F64(N) +#define MATH_PRIVATE(N) MANGLE3(__ocmlpriv,N,f64) + +// Optimization Controls +#include "opts.h" + +// Attributes +#define PUREATTR __attribute__((pure)) +#define CONSTATTR __attribute__((const)) + +// Math controls +#include "privD.h" + +// Bit patterns +#define SIGNBIT_DP64 0x8000000000000000L +#define EXSIGNBIT_DP64 0x7fffffffffffffffL +#define EXPBITS_DP64 0x7ff0000000000000L +#define MANTBITS_DP64 0x000fffffffffffffL +#define ONEEXPBITS_DP64 0x3ff0000000000000L +#define TWOEXPBITS_DP64 0x4000000000000000L +#define HALFEXPBITS_DP64 0x3fe0000000000000L +#define IMPBIT_DP64 0x0010000000000000L +#define QNANBITPATT_DP64 0x7ff8000000000000L +#define INDEFBITPATT_DP64 0xfff8000000000000L +#define PINFBITPATT_DP64 0x7ff0000000000000L +#define NINFBITPATT_DP64 0xfff0000000000000L +#define EXPBIAS_DP64 1023 +#define EXPSHIFTBITS_DP64 52 +#define BIASEDEMIN_DP64 1 +#define EMIN_DP64 -1022 +#define BIASEDEMAX_DP64 2046 +#define EMAX_DP64 1023 +#define LAMBDA_DP64 1.0e300 +#define MANTLENGTH_DP64 53 +#define BASEDIGITS_DP64 15 + +#define QNAN_F64 __builtin_nan("") +#define PINF_F64 __builtin_inf() +#define NINF_F64 (-__builtin_inf()) diff --git a/amd/device-libs/ocml/src/mathF.h b/amd/device-libs/ocml/src/mathF.h new file mode 100644 index 0000000000000..70d3f94f31e12 --- /dev/null +++ b/amd/device-libs/ocml/src/mathF.h @@ -0,0 +1,55 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +// OCML prototypes +#include "ocml.h" + +// Tables +#include "tables.h" + +// Builtins +#include "builtins.h" + +// Mangling +#define MATH_MANGLE(N) OCML_MANGLE_F32(N) +#define MATH_MANGLE2(N) OCML_MANGLE_2F32(N) +#define MATH_PRIVATE(N) MANGLE3(__ocmlpriv,N,f32) + +// Optimization Controls +#include "opts.h" + +// Attributes +#define PUREATTR __attribute__((pure)) +#define CONSTATTR __attribute__((const)) + +// Math controls +#include "privF.h" + +// Floating point patterns +#define SIGNBIT_SP32 (int)0x80000000 +#define EXSIGNBIT_SP32 0x7fffffff +#define EXPBITS_SP32 0x7f800000 +#define MANTBITS_SP32 0x007fffff +#define ONEEXPBITS_SP32 0x3f800000 +#define TWOEXPBITS_SP32 0x40000000 +#define HALFEXPBITS_SP32 0x3f000000 +#define IMPBIT_SP32 0x00800000 +#define QNANBITPATT_SP32 0x7fc00000 +#define PINFBITPATT_SP32 0x7f800000 +#define NINFBITPATT_SP32 (int)0xff800000 +#define EXPBIAS_SP32 127 +#define EXPSHIFTBITS_SP32 23 +#define BIASEDEMIN_SP32 1 +#define EMIN_SP32 -126 +#define BIASEDEMAX_SP32 254 +#define EMAX_SP32 127 +#define MANTLENGTH_SP32 24 +#define BASEDIGITS_SP32 7 + +#define QNAN_F32 __builtin_nanf("") +#define PINF_F32 __builtin_inff() +#define NINF_F32 (-__builtin_inff()) diff --git a/amd/device-libs/ocml/src/mathH.h b/amd/device-libs/ocml/src/mathH.h new file mode 100644 index 0000000000000..4a3ccadffa7bd --- /dev/null +++ b/amd/device-libs/ocml/src/mathH.h @@ -0,0 +1,71 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +// OCML prototypes +#include "ocml.h" + +// Tables +#include "tables.h" + +// Builtins +#include "builtins.h" + +// Mangling +#define MATH_MANGLE(N) OCML_MANGLE_F16(N) +#define MATH_MANGLE2(N) OCML_MANGLE_2F16(N) +#define MATH_PRIVATE(N) MANGLE3(__ocmlpriv,N,f16) +#define MATH_UPMANGLE(N) OCML_MANGLE_F32(N) + +// Optimization Controls +#include "opts.h" + +// Attributes +#define PUREATTR __attribute__((pure)) +#define CONSTATTR __attribute__((const)) + +// Math controls +#include "privH.h" + +// Floating point patterns +#define SIGNBIT_HP16 0x8000 +#define EXSIGNBIT_HP16 0x7fff +#define EXPBITS_HP16 0x7c00 +#define MANTBITS_HP16 0x03ff +#define ONEEXPBITS_HP16 0x3c00 +#define TWOEXPBITS_HP16 0x4000 +#define HALFEXPBITS_HP16 0x3800 +#define IMPBIT_HP16 0x0400 +#define QNANBITPATT_HP16 0x7e00 +#define PINFBITPATT_HP16 0x7c00 +#define NINFBITPATT_HP16 0xfc00 +#define EXPBIAS_HP16 15 +#define EXPSHIFTBITS_HP16 10 +#define BIASEDEMIN_HP16 1 +#define EMIN_HP16 -14 +#define BIASEDEMAX_HP16 30 +#define EMAX_HP16 15 +#define MANTLENGTH_HP16 11 +#define BASEDIGITS_HP16 5 + +#define QNAN_F16 __builtin_nanf16("") +#define PINF_F16 __builtin_inff16() +#define NINF_F16 (-__builtin_inff16()) + +#define UGEN(N) \ +half2 MATH_MANGLE2(N)(half2 x) \ +{ \ + return (half2)(MATH_MANGLE(N)(x.lo), MATH_MANGLE(N)(x.hi)); \ +} + +#define BGEN(N) \ +half2 MATH_MANGLE2(N)(half2 x, half2 y) \ +{ \ + return (half2)(MATH_MANGLE(N)(x.lo, y.lo), MATH_MANGLE(N)(x.hi, y.hi)); \ +} + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + diff --git a/amd/device-libs/ocml/src/maxD.cl b/amd/device-libs/ocml/src/maxD.cl new file mode 100644 index 0000000000000..7c6664b0f504d --- /dev/null +++ b/amd/device-libs/ocml/src/maxD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(max)(double x, double y) +{ + return BUILTIN_CMAX_F64(x, y); +} + diff --git a/amd/device-libs/ocml/src/maxF.cl b/amd/device-libs/ocml/src/maxF.cl new file mode 100644 index 0000000000000..4cd0bfa97ee96 --- /dev/null +++ b/amd/device-libs/ocml/src/maxF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(max)(float x, float y) +{ + return BUILTIN_CMAX_F32(x, y); +} + diff --git a/amd/device-libs/ocml/src/maxH.cl b/amd/device-libs/ocml/src/maxH.cl new file mode 100644 index 0000000000000..01479c8a52a33 --- /dev/null +++ b/amd/device-libs/ocml/src/maxH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(max)(half2 x, half2 y) +{ + return BUILTIN_CMAX_2F16(x, y); +} + +CONSTATTR half +MATH_MANGLE(max)(half x, half y) +{ + return BUILTIN_CMAX_F16(x, y); +} + diff --git a/amd/device-libs/ocml/src/maxmagD.cl b/amd/device-libs/ocml/src/maxmagD.cl new file mode 100644 index 0000000000000..42799ac29ccfa --- /dev/null +++ b/amd/device-libs/ocml/src/maxmagD.cl @@ -0,0 +1,20 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(maxmag)(double x, double y) +{ + double ret = BUILTIN_MAX_F64(x, y); + double ax = BUILTIN_ABS_F64(x); + double ay = BUILTIN_ABS_F64(y); + ret = ax > ay ? x : ret; + ret = ay > ax ? y : ret; + return ret; +} + diff --git a/amd/device-libs/ocml/src/maxmagF.cl b/amd/device-libs/ocml/src/maxmagF.cl new file mode 100644 index 0000000000000..b8ef3b5c263fc --- /dev/null +++ b/amd/device-libs/ocml/src/maxmagF.cl @@ -0,0 +1,20 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(maxmag)(float x, float y) +{ + float ret = BUILTIN_MAX_F32(x, y); + float ax = BUILTIN_ABS_F32(x); + float ay = BUILTIN_ABS_F32(y); + ret = ax > ay ? x : ret; + ret = ay > ax ? y : ret; + return ret; +} + diff --git a/amd/device-libs/ocml/src/maxmagH.cl b/amd/device-libs/ocml/src/maxmagH.cl new file mode 100644 index 0000000000000..9bd188d2a94c7 --- /dev/null +++ b/amd/device-libs/ocml/src/maxmagH.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(maxmag) + +CONSTATTR half +MATH_MANGLE(maxmag)(half x, half y) +{ + half ret = BUILTIN_MAX_F16(x, y); + half ax = BUILTIN_ABS_F16(x); + half ay = BUILTIN_ABS_F16(y); + ret = ax > ay ? x : ret; + ret = ay > ax ? y : ret; + return ret; +} + diff --git a/amd/device-libs/ocml/src/minD.cl b/amd/device-libs/ocml/src/minD.cl new file mode 100644 index 0000000000000..151178c236d94 --- /dev/null +++ b/amd/device-libs/ocml/src/minD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(min)(double x, double y) +{ + return BUILTIN_CMIN_F64(x, y); +} + diff --git a/amd/device-libs/ocml/src/minF.cl b/amd/device-libs/ocml/src/minF.cl new file mode 100644 index 0000000000000..eb38af709ca10 --- /dev/null +++ b/amd/device-libs/ocml/src/minF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(min)(float x, float y) +{ + return BUILTIN_CMIN_F32(x, y); +} + diff --git a/amd/device-libs/ocml/src/minH.cl b/amd/device-libs/ocml/src/minH.cl new file mode 100644 index 0000000000000..2f2eb4d758cc3 --- /dev/null +++ b/amd/device-libs/ocml/src/minH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(min)(half2 x, half2 y) +{ + return BUILTIN_CMIN_2F16(x, y); +} + +CONSTATTR half +MATH_MANGLE(min)(half x, half y) +{ + return BUILTIN_CMIN_F16(x, y); +} + diff --git a/amd/device-libs/ocml/src/minmagD.cl b/amd/device-libs/ocml/src/minmagD.cl new file mode 100644 index 0000000000000..902e6becd2a90 --- /dev/null +++ b/amd/device-libs/ocml/src/minmagD.cl @@ -0,0 +1,20 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(minmag)(double x, double y) +{ + double ret = BUILTIN_MIN_F64(x, y); + double ax = BUILTIN_ABS_F64(x); + double ay = BUILTIN_ABS_F64(y); + ret = ax < ay ? x : ret; + ret = ay < ax ? y : ret; + return ret; +} + diff --git a/amd/device-libs/ocml/src/minmagF.cl b/amd/device-libs/ocml/src/minmagF.cl new file mode 100644 index 0000000000000..83fff262f20cb --- /dev/null +++ b/amd/device-libs/ocml/src/minmagF.cl @@ -0,0 +1,20 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(minmag)(float x, float y) +{ + float ret = BUILTIN_MIN_F32(x, y); + float ax = BUILTIN_ABS_F32(x); + float ay = BUILTIN_ABS_F32(y); + ret = ax < ay ? x : ret; + ret = ay < ax ? y : ret; + return ret; +} + diff --git a/amd/device-libs/ocml/src/minmagH.cl b/amd/device-libs/ocml/src/minmagH.cl new file mode 100644 index 0000000000000..eaf84c7d32e0d --- /dev/null +++ b/amd/device-libs/ocml/src/minmagH.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(minmag) + +CONSTATTR half +MATH_MANGLE(minmag)(half x, half y) +{ + half ret = BUILTIN_MIN_F16(x, y); + half ax = BUILTIN_ABS_F16(x); + half ay = BUILTIN_ABS_F16(y); + ret = ax < ay ? x : ret; + ret = ay < ax ? y : ret; + return ret; +} + diff --git a/amd/device-libs/ocml/src/modfD.cl b/amd/device-libs/ocml/src/modfD.cl new file mode 100644 index 0000000000000..d20a0a89189b5 --- /dev/null +++ b/amd/device-libs/ocml/src/modfD.cl @@ -0,0 +1,19 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +double +MATH_MANGLE(modf)(double x, __private double *iptr) +{ + double tx = BUILTIN_TRUNC_F64(x); + double ret = x - tx; + ret = BUILTIN_ISINF_F64(x) ? 0.0 : ret; + *iptr = tx; + return BUILTIN_COPYSIGN_F64(ret, x); +} + diff --git a/amd/device-libs/ocml/src/modfF.cl b/amd/device-libs/ocml/src/modfF.cl new file mode 100644 index 0000000000000..a99b7ce288106 --- /dev/null +++ b/amd/device-libs/ocml/src/modfF.cl @@ -0,0 +1,19 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +float +MATH_MANGLE(modf)(float x, __private float *iptr) +{ + float tx = BUILTIN_TRUNC_F32(x); + float ret = x - tx; + ret = BUILTIN_ISINF_F32(x) ? 0.0f : ret; + *iptr = tx; + return BUILTIN_COPYSIGN_F32(ret, x); +} + diff --git a/amd/device-libs/ocml/src/modfH.cl b/amd/device-libs/ocml/src/modfH.cl new file mode 100644 index 0000000000000..a3ce26817aa0b --- /dev/null +++ b/amd/device-libs/ocml/src/modfH.cl @@ -0,0 +1,30 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +half2 +MATH_MANGLE2(modf)(half2 x, __private half2 *iptr) +{ + half2 tx = BUILTIN_TRUNC_2F16(x); + half2 ret = x - tx; + ret.lo = BUILTIN_ISINF_F16(x.lo) ? 0.0h : ret.lo; + ret.hi = BUILTIN_ISINF_F16(x.hi) ? 0.0h : ret.hi; + *iptr = tx; + return BUILTIN_COPYSIGN_2F16(ret, x); +} + +half +MATH_MANGLE(modf)(half x, __private half *iptr) +{ + half tx = BUILTIN_TRUNC_F16(x); + half ret = x - tx; + ret = BUILTIN_ISINF_F16(x) ? 0.0h : ret; + *iptr = tx; + return BUILTIN_COPYSIGN_F16(ret, x); +} + diff --git a/amd/device-libs/ocml/src/mulD.cl b/amd/device-libs/ocml/src/mulD.cl new file mode 100644 index 0000000000000..1308014825a67 --- /dev/null +++ b/amd/device-libs/ocml/src/mulD.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(mul_rte)(double x, double y) +{ + return x * y; +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR double \ +MATH_MANGLE(LN)(double x, double y) \ +{ \ + BUILTIN_SETROUND_F16F64(RM); \ + double ret = x * y; \ + BUILTIN_SETROUND_F16F64(ROUND_RTE); \ + return ret; \ +} + +GEN(mul_rtn, ROUND_RTN) +GEN(mul_rtp, ROUND_RTP) +GEN(mul_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/mulF.cl b/amd/device-libs/ocml/src/mulF.cl new file mode 100644 index 0000000000000..fd96271a12770 --- /dev/null +++ b/amd/device-libs/ocml/src/mulF.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(mul_rte)(float x, float y) +{ + return x * y; +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR float \ +MATH_MANGLE(LN)(float x, float y) \ +{ \ + BUILTIN_SETROUND_F32(RM); \ + float ret = x * y; \ + BUILTIN_SETROUND_F32(ROUND_RTE); \ + return ret; \ +} + +GEN(mul_rtn, ROUND_RTN) +GEN(mul_rtp, ROUND_RTP) +GEN(mul_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/mulH.cl b/amd/device-libs/ocml/src/mulH.cl new file mode 100644 index 0000000000000..c753e1dcab668 --- /dev/null +++ b/amd/device-libs/ocml/src/mulH.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_MANGLE(mul_rte)(half x, half y) +{ + return x * y; +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR half \ +MATH_MANGLE(LN)(half x, half y) \ +{ \ + BUILTIN_SETROUND_F16F64(RM); \ + half ret = x * y; \ + BUILTIN_SETROUND_F16F64(ROUND_RTE); \ + return ret; \ +} + +GEN(mul_rtn, ROUND_RTN) +GEN(mul_rtp, ROUND_RTP) +GEN(mul_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/nanD.cl b/amd/device-libs/ocml/src/nanD.cl new file mode 100644 index 0000000000000..762365bc54280 --- /dev/null +++ b/amd/device-libs/ocml/src/nanD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(nan)(ulong nancode) +{ + return AS_DOUBLE((nancode & MANTBITS_DP64) | QNANBITPATT_DP64); +} + diff --git a/amd/device-libs/ocml/src/nanF.cl b/amd/device-libs/ocml/src/nanF.cl new file mode 100644 index 0000000000000..aeb5e530f294b --- /dev/null +++ b/amd/device-libs/ocml/src/nanF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(nan)(uint nancode) +{ + return AS_FLOAT(QNANBITPATT_SP32 | (nancode & 0xfffff)); +} + diff --git a/amd/device-libs/ocml/src/nanH.cl b/amd/device-libs/ocml/src/nanH.cl new file mode 100644 index 0000000000000..b53e48e8bfd2f --- /dev/null +++ b/amd/device-libs/ocml/src/nanH.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(nan)(ushort2 nancode) +{ + ushort2 h = (ushort2)QNANBITPATT_HP16 | (nancode & (ushort2)0x01ff); + return AS_HALF2(h); +} + +CONSTATTR half +MATH_MANGLE(nan)(ushort nancode) +{ + ushort h = (ushort)QNANBITPATT_HP16 | (nancode & (ushort)0x01ff); + return AS_HALF(h); +} + diff --git a/amd/device-libs/ocml/src/nativeD.cl b/amd/device-libs/ocml/src/nativeD.cl new file mode 100644 index 0000000000000..43b7d0c01c8f7 --- /dev/null +++ b/amd/device-libs/ocml/src/nativeD.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + + +CONSTATTR double +MATH_MANGLE(native_recip)(double x) +{ + // FIXME: Should use IR fdiv with arcp set. + return __builtin_amdgcn_rcp(x); +} + +CONSTATTR double +MATH_MANGLE(native_sqrt)(double x) +{ + return __builtin_sqrt(x); +} + +CONSTATTR double +MATH_MANGLE(native_rsqrt)(double x) +{ + return __builtin_amdgcn_rsq(x); +} + diff --git a/amd/device-libs/ocml/src/nativeF.cl b/amd/device-libs/ocml/src/nativeF.cl new file mode 100644 index 0000000000000..7d0f16d02f7e4 --- /dev/null +++ b/amd/device-libs/ocml/src/nativeF.cl @@ -0,0 +1,40 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + + +CONSTATTR float +MATH_MANGLE(native_recip)(float x) +{ + #pragma clang fp reciprocal(on) + return 1.0f / x; +} + +CONSTATTR float +MATH_MANGLE(native_sqrt)(float x) +{ + return __builtin_sqrtf(x); +} + +CONSTATTR float +MATH_MANGLE(native_rsqrt)(float x) +{ + #pragma clang fp contract(fast) + return 1.0f / __builtin_sqrtf(x); +} + +CONSTATTR float +MATH_MANGLE(native_sin)(float x) { + return __builtin_sinf(x); +} + +CONSTATTR float +MATH_MANGLE(native_cos)(float x) +{ + return __builtin_cosf(x); +} diff --git a/amd/device-libs/ocml/src/nativeH.cl b/amd/device-libs/ocml/src/nativeH.cl new file mode 100644 index 0000000000000..432597e090a8d --- /dev/null +++ b/amd/device-libs/ocml/src/nativeH.cl @@ -0,0 +1,57 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_MANGLE(native_sqrt)(half x) +{ + return __builtin_sqrtf16(x); +} + +CONSTATTR half +MATH_MANGLE(native_sin)(half x) +{ + return __builtin_sinf16(x); +} + +CONSTATTR half +MATH_MANGLE(native_cos)(half x) +{ + return __builtin_cosf16(x); +} + +CONSTATTR half +MATH_MANGLE(native_exp)(half x) +{ + return __builtin_expf16(x); +} + +CONSTATTR half +MATH_MANGLE(native_exp2)(half x) +{ + return __builtin_exp2f16(x); +} + +CONSTATTR half +MATH_MANGLE(native_log)(half x) +{ + return __builtin_logf16(x); +} + +CONSTATTR half +MATH_MANGLE(native_log2)(half x) +{ + return __builtin_log2f16(x); +} + +CONSTATTR half +MATH_MANGLE(native_log10)(half x) +{ + return __builtin_log10f16(x); + +} diff --git a/amd/device-libs/ocml/src/native_expF.cl b/amd/device-libs/ocml/src/native_expF.cl new file mode 100644 index 0000000000000..2af44201f38d9 --- /dev/null +++ b/amd/device-libs/ocml/src/native_expF.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +// Value of log2(10) +#define M_LOG2_10_F 0x1.a934f0p+1f + +CONSTATTR float +MATH_MANGLE(native_exp2)(float x) +{ + // The approximate function expansion of generic exp2 has to + // handle denormals without DAZ, this does not. + return __builtin_amdgcn_exp2f(x); +} + +CONSTATTR float +MATH_MANGLE(native_exp)(float x) +{ + return MATH_MANGLE(native_exp2)(M_LOG2E_F * x); +} + +CONSTATTR float +MATH_MANGLE(native_exp10)(float x) +{ + return MATH_MANGLE(native_exp2)(M_LOG2_10_F * x); +} diff --git a/amd/device-libs/ocml/src/native_logF.cl b/amd/device-libs/ocml/src/native_logF.cl new file mode 100644 index 0000000000000..65221ce3d6eba --- /dev/null +++ b/amd/device-libs/ocml/src/native_logF.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(native_log)(float x) +{ + return __builtin_logf(x); +} + +CONSTATTR float +MATH_MANGLE(native_log2)(float x) +{ + return __builtin_log2f(x); +} + +CONSTATTR float +MATH_MANGLE(native_log10)(float x) +{ + return __builtin_log10f(x); +} diff --git a/amd/device-libs/ocml/src/native_rcpH.cl b/amd/device-libs/ocml/src/native_rcpH.cl new file mode 100644 index 0000000000000..85d112bf26f8d --- /dev/null +++ b/amd/device-libs/ocml/src/native_rcpH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +// File should be compiled with -freciprocal-math and accuracy flags +// sufficient to select v_rcp_f16. +CONSTATTR half +MATH_MANGLE(native_rcp)(half x) +{ + #pragma clang fp reciprocal(on) + return 1.0h / x; +} diff --git a/amd/device-libs/ocml/src/native_rsqrtH.cl b/amd/device-libs/ocml/src/native_rsqrtH.cl new file mode 100644 index 0000000000000..94c67c964702a --- /dev/null +++ b/amd/device-libs/ocml/src/native_rsqrtH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +// File should be compiled with -freciprocal-math and accuracy flags +// sufficient to select v_rsq_f16. +CONSTATTR half +MATH_MANGLE(native_rsqrt)(half x) +{ + #pragma clang fp contract(fast) + return 1.0h / __builtin_sqrtf16(x); +} diff --git a/amd/device-libs/ocml/src/ncdfD.cl b/amd/device-libs/ocml/src/ncdfD.cl new file mode 100644 index 0000000000000..e8ee06d6a06c2 --- /dev/null +++ b/amd/device-libs/ocml/src/ncdfD.cl @@ -0,0 +1,151 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#if !defined EXTRA_ACCURACY + +CONSTATTR double +MATH_MANGLE(ncdf)(double x) +{ + const double chi = -0x1.6a09e667f3bcdp-1; + const double clo = 0x1.bdd3413b26456p-55; + const double b = 0x1.34d4edce2b7d6p+5; + x = BUILTIN_ABS_F64(x) > b ? BUILTIN_COPYSIGN_F64(b, x) : x; + double thi = chi * x; + double tlo = MATH_MAD(clo, x, MATH_MAD(chi, x, -thi)); + double yhi = thi + tlo; + double ylo = tlo - (yhi - thi); + double r = MATH_MANGLE(erfc)(yhi); + double dr = -2.0 * yhi * r; + dr = x >= -1.0 ? 0.0f : dr; + r = MATH_MAD(ylo, dr, r); + return 0.5 * r; +} + +#else + +CONSTATTR double +MATH_MANGLE(ncdf)(double x) +{ + double ret; + + if (x > -0x1.5956b87528a49p-1) { + if (x < 1.0) { + double t = x * x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + -0x1.8cb754014e0b3p-34, 0x1.320d075b1fdefp-29), -0x1.61ab7dd43f8c3p-25), 0x1.6584e2ae1c515p-21), + -0x1.3ce8d5eca373fp-17), 0x1.e42b0c16331c9p-14), -0x1.37403f689501bp-10), 0x1.46d0429761749p-7), + -0x1.1058377e2ce69p-4), 0x1.9884533d43650p-2); + ret = MATH_MAD(x, ret, 0.5); + } else if (x < 2.5) { + double t = x - 1.0; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.060edab4a19d2p-29, -0x1.53a0eb739ccefp-25), 0x1.4c8f542ea757fp-22), -0x1.1c15387d5063ap-20), + 0x1.fadb9735a0803p-22), 0x1.a2bae693176d3p-18), -0x1.cd9e9b6a563dbp-21), -0x1.73fccf7f7f32cp-14), + 0x1.f8d0e4a86cde5p-14), 0x1.92ac8d4045877p-11), -0x1.084ad98cd25bfp-9), -0x1.084c041e359abp-8), + 0x1.4a5ee6ad39afcp-6), -0x1.c16ac04dad985p-35), -0x1.ef8e58e30ef67p-4), 0x1.ef8e58e331308p-3), + 0x1.aec4bd120d37ep-1); + } else if (x < 4.0) { + double t = x - 2.5; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.5f0f31da8eb78p-33, -0x1.51820cdbd28e7p-32), 0x1.af16a4a50d960p-26), -0x1.b5b829c3676fep-23), + 0x1.6a839ce113434p-21), -0x1.efa0b32917d76p-24), -0x1.c2eaad7a58467p-18), 0x1.2c1fa77adea62p-16), + 0x1.c789d533e599bp-16), -0x1.13874be6da82dp-12), 0x1.0d3cf7e102cccp-11), 0x1.5d67fa3a182e7p-11), + -0x1.84e50141ef284p-8), 0x1.f6924953c9cbbp-7), -0x1.66fac6add3b42p-6), 0x1.1f2f0557f4ab9p-6), + 0x1.fcd21635036c6p-1); + } else if (x < 8.2109375) { + double t = x - 4.0; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.49dae5934aa9ep-37, 0x1.a0a9b27e4276cp-33), -0x1.40ae395c9950bp-32), -0x1.6d7df112c9529p-26), + 0x1.f76261921be9dp-25), 0x1.a70ffb3533144p-19), -0x1.9e462dbfa92d9p-16), -0x1.5db0c27784edap-13), + 0x1.3c5a964f22d79p-9), 0x1.5cadd35757947p-9), -0x1.1b11634e869afp-3), 0x1.0bf46d4a7c1dap-1); + ret = ret * ret; + ret = ret * ret; + ret = ret * ret; + ret = MATH_MAD(-ret, ret, 1.0); + } else { + ret = 1.0; + } + } else { + if (x > -1.5) { + double t = -1.5 - x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.87f6d8bacfe4dp-24, -0x1.48dcea6d816e1p-23), 0x1.a32c40a47a30ep-20), 0x1.bd22f42e45845p-21), + -0x1.40839ec0fb6a8p-16), 0x1.a659159d48d42p-16), 0x1.6f322a8af7fa6p-13), -0x1.2466b5cb3347ep-11), + -0x1.58d37df0dc6c4p-11), 0x1.809d8fed7b759p-8), -0x1.8de0c7fed2ce4p-8), -0x1.ba1633b5691dfp-6), + 0x1.8de0c823b3adcp-4), -0x1.0940856d21e73p-3), 0x1.11a46d89647efp-4); + } else if (x > -2.25) { + double t = -2.25 - x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.34778becb8778p-25, -0x1.48b485e383089p-24), -0x1.bd48bc73889cap-21), 0x1.b73b6859639c8p-20), + 0x1.3582af30190aap-18), -0x1.1ac5d5e34ec1bp-15), 0x1.0cc99e25a5373p-15), 0x1.14835909e7060p-12), + -0x1.03e8ee71d051cp-10), 0x1.e44553637b8cap-12), 0x1.9234723301c22p-8), -0x1.601939c453937p-6), + 0x1.24833bce57500p-5), -0x1.0402dfd3dc1adp-5), 0x1.90924f21d3612p-7); + } else if (x > -2.75) { + double t = -2.75 - x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + 0x1.b9337a6a3734cp-24, -0x1.6590be46da1cep-23), -0x1.267a1aba29190p-20), 0x1.5254da7def6c3p-18), + -0x1.502fd581f8723p-19), -0x1.9d5f911317093p-15), 0x1.7a91271378f92p-13), -0x1.f4331ea1149bdp-14), + -0x1.2654aaf562b70p-10), 0x1.378ebd4d4cb5bp-8), -0x1.45e9ccb8cbc85p-7), 0x1.99b83490879c6p-7), + -0x1.29fa54c6341e5p-7), 0x1.86904349ec803p-9); + } else if (x > -38.46875) { + double t = MATH_RCP(x * x); + + if (x > -4.0) + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.088bebb0c7bfcp+25, -0x1.964e1d51045b9p+25), 0x1.255cf223ca4ddp+25), -0x1.093e30bdaaf0ap+24), + 0x1.51dabf56ccafap+22), -0x1.440d8ce218330p+20), 0x1.eaab175120c83p+17), -0x1.31cd405f6ece6p+15), + 0x1.4949b45c18bffp+12), -0x1.476ca2d47ed6dp+9), 0x1.4b5c83b73de92p+6), -0x1.86317d1686e59p+3), + 0x1.3fab4df0327b3p+1), -0x1.fffc093fa2eedp-1), -0x1.3f9112da61104p-8); + else + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.668af6ed742f7p+59, -0x1.e8a3ea3ebba9fp+58), 0x1.39149210574c4p+57), -0x1.f6e7aed1dc814p+54), + 0x1.1d2c1545c3a31p+52), -0x1.e8eb69ce384f2p+48), 0x1.4c8445a6d688bp+45), -0x1.7638c79bb1508p+41), + 0x1.6c05288dd5cfbp+37), -0x1.41fe50b8d5f0fp+33), 0x1.12af999e7acfap+29), -0x1.e02f34f68433ep+24), + 0x1.c4864e8ef2105p+20), -0x1.dc7852ceec4e8p+16), 0x1.1f83f2164bb6fp+13), -0x1.9819642b134dbp+9), + 0x1.60fffe9105243p+6), -0x1.8aaaaaa42b3fdp+3), 0x1.3ffffffff70fdp+1), -0x1.fffffffffff98p-1), + -0x1.3f8e4325f5a57p-8); + + double xh = AS_DOUBLE(AS_LONG(x) & 0xffffffff00000000L); + ret = MATH_DIV(MATH_MANGLE(exp)(MATH_MAD(x - xh, -0.5*(x + xh), ret)), -x) * + MATH_MANGLE(exp)(MATH_MAD(xh, -0.5*xh, -0.9140625)); + } else { + ret = BUILTIN_ISNAN_F64(x) ? x : 0.0; + } + } + + return ret; +} + +#endif diff --git a/amd/device-libs/ocml/src/ncdfF.cl b/amd/device-libs/ocml/src/ncdfF.cl new file mode 100644 index 0000000000000..086554aa44a9d --- /dev/null +++ b/amd/device-libs/ocml/src/ncdfF.cl @@ -0,0 +1,115 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#if !defined EXTRA_ACCURACY +CONSTATTR float +MATH_MANGLE(ncdf)(float x) +{ + const float chi = -0x1.6a09e6p-1f; + const float clo = -0x1.9fcef4p-27f; + const float b = 0x1.c57228p+3f; + x = BUILTIN_ABS_F32(x) > b ? BUILTIN_COPYSIGN_F32(b, x) : x; + float thi = chi * x; + float tlo = BUILTIN_FMA_F32(clo, x, BUILTIN_FMA_F32(chi, x, -thi)); + float yhi = thi + tlo; + float ylo = tlo - (yhi - thi); + float r = MATH_MANGLE(erfc)(yhi); + float dr = -2.0f * yhi * r; + dr = x >= -1.0f ? 0.0f : dr; + r = BUILTIN_FMA_F32(ylo, dr, r); + return 0.5f * r; +} + +#else +CONSTATTR float +MATH_MANGLE(ncdf)(float x) +{ + float ret; + + // cut at -0x1.5956b8p-1f + + if (x > -0x1.5956b8p-1f) { + if (x < 1.0f) { + float t = x*x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.20379ep-21f, -0x1.3727aep-17f), 0x1.e3af2ep-14f), -0x1.373d8cp-10f), + 0x1.46d034p-7f), -0x1.105838p-4f), 0x1.988454p-2f); + ret = MATH_MAD(x, ret, 0.5f); + } else if (x < 2.5f) { + float t = x - 1.0f; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.53eaecp-13f, 0x1.3458b4p-10f), -0x1.306adcp-9f), -0x1.01ae44p-8f), + 0x1.4a7e5ep-6f), -0x1.fe4012p-17f), -0x1.ef8a62p-4f), 0x1.ef8e32p-3f), + 0x1.aec4bep-1f); + } else if (x < 4.0f) { + float t = x - 2.5f; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.4ca664p-13f, 0x1.990fd2p-10f), -0x1.b0d706p-8f), 0x1.ffa500p-7f), + -0x1.67e84cp-6f), 0x1.1f419cp-6f), 0x1.fcd214p-1f); + } else if (x < 5.296875f) { + float t = x - 4.0f; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.eae60ap-10f, 0x1.9b6438p-9f), -0x1.1b57a8p-3f), 0x1.0bf538p-1f); + ret = ret * ret; + ret = ret * ret; + ret = ret * ret; + ret = MATH_MAD(-ret, ret, 1.0f); + } else { + ret = 1.0f; + } + } else { + if (x > -1.5f) { + float t = -1.5f - x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.a29ef2p-11f, -0x1.a25e42p-11f), 0x1.7eaaaap-8f), -0x1.8d95e2p-8f), + -0x1.ba093ap-6f), 0x1.8de146p-4f), -0x1.094082p-3f), 0x1.11a46ep-4f); + } else if (x > -2.5f) { + float t = -2.5f - x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.aef5d0p-14f, 0x1.0b8148p-11f), -0x1.232788p-12f), -0x1.1afa4cp-11f), + 0x1.877322p-8f), -0x1.f65b2ep-7f), 0x1.66fd08p-6f), -0x1.1f2ef4p-6f), + 0x1.96f4e6p-8f); + } else if (x > -3.25f) { + float t = -3.25f - x; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + -0x1.8963dep-15f, -0x1.2e81a4p-17f), 0x1.7477b2p-13f), -0x1.c8841ap-11f), + 0x1.1036c6p-9f), -0x1.a7e084p-9f), 0x1.b02b86p-9f), -0x1.09f390p-9f), + 0x1.2e86fep-11f); + } else if (x > -14.125f) { + float t = MATH_FAST_RCP(x * x); + + if (x > -5.0f) + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.f9b114p+7f, -0x1.32f4b4p+7f), 0x1.723550p+5f), -0x1.4b98dcp+3f), + 0x1.3821cep+1f), -0x1.ff6d7cp-1f), -0x1.4023a6p-8f); + else + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + 0x1.f31adep+10f, -0x1.030fd6p+9f), 0x1.41d2c6p+6f), -0x1.86b97ap+3f), + 0x1.3fdb64p+1f), -0x1.ffff50p-1f), -0x1.3f8e6cp-8f); + + float xh = AS_FLOAT(AS_INT(x) & 0xffffe000); + ret = MATH_FAST_DIV(MATH_MANGLE(exp)(MATH_MAD(x - xh, -0.5f*(x + xh), ret)), -x) * + MATH_MANGLE(exp)(MATH_MAD(xh, -0.5f*xh, -0.9140625f)); + } else { + ret = BUILTIN_ISNAN_F32(x) ? x : 0.0f; + } + } + + return ret; +} +#endif + diff --git a/amd/device-libs/ocml/src/ncdfH.cl b/amd/device-libs/ocml/src/ncdfH.cl new file mode 100644 index 0000000000000..bd7dc77e0934a --- /dev/null +++ b/amd/device-libs/ocml/src/ncdfH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(ncdf) + +CONSTATTR half +MATH_MANGLE(ncdf)(half x) +{ + return (half)MATH_UPMANGLE(ncdf)((float)x); +} + diff --git a/amd/device-libs/ocml/src/ncdfinvD.cl b/amd/device-libs/ocml/src/ncdfinvD.cl new file mode 100644 index 0000000000000..62103ae02bb3c --- /dev/null +++ b/amd/device-libs/ocml/src/ncdfinvD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(ncdfinv)(double x) +{ + return -0x1.6a09e667f3bcdp+0 * MATH_MANGLE(erfcinv)(x + x); +} + diff --git a/amd/device-libs/ocml/src/ncdfinvF.cl b/amd/device-libs/ocml/src/ncdfinvF.cl new file mode 100644 index 0000000000000..d8fc5fe6a9b57 --- /dev/null +++ b/amd/device-libs/ocml/src/ncdfinvF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(ncdfinv)(float x) +{ + return -0x1.6a09e6p+0f * MATH_MANGLE(erfcinv)(x + x); +} + diff --git a/amd/device-libs/ocml/src/ncdfinvH.cl b/amd/device-libs/ocml/src/ncdfinvH.cl new file mode 100644 index 0000000000000..1f4e96e18c792 --- /dev/null +++ b/amd/device-libs/ocml/src/ncdfinvH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(ncdfinv) + +CONSTATTR half +MATH_MANGLE(ncdfinv)(half x) +{ + return (half)MATH_UPMANGLE(ncdfinv)((float)x); +} + diff --git a/amd/device-libs/ocml/src/nearbyintD.cl b/amd/device-libs/ocml/src/nearbyintD.cl new file mode 100644 index 0000000000000..a222532f58815 --- /dev/null +++ b/amd/device-libs/ocml/src/nearbyintD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(nearbyint)(double x) +{ + return BUILTIN_RINT_F64(x); +} + diff --git a/amd/device-libs/ocml/src/nearbyintF.cl b/amd/device-libs/ocml/src/nearbyintF.cl new file mode 100644 index 0000000000000..44be24813f4c9 --- /dev/null +++ b/amd/device-libs/ocml/src/nearbyintF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(nearbyint)(float x) +{ + return BUILTIN_RINT_F32(x); +} + diff --git a/amd/device-libs/ocml/src/nearbyintH.cl b/amd/device-libs/ocml/src/nearbyintH.cl new file mode 100644 index 0000000000000..92c0fa3b17d05 --- /dev/null +++ b/amd/device-libs/ocml/src/nearbyintH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(nearbyint)(half2 x) +{ + return BUILTIN_RINT_2F16(x); +} + +CONSTATTR half +MATH_MANGLE(nearbyint)(half x) +{ + return BUILTIN_RINT_F16(x); +} + diff --git a/amd/device-libs/ocml/src/nextafterD.cl b/amd/device-libs/ocml/src/nextafterD.cl new file mode 100644 index 0000000000000..35d2e8610f367 --- /dev/null +++ b/amd/device-libs/ocml/src/nextafterD.cl @@ -0,0 +1,32 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(nextafter)(double x, double y) +{ + long ix = AS_LONG(x); + long mx = SIGNBIT_DP64 - ix; + mx = ix < 0 ? mx : ix; + long iy = AS_LONG(y); + long my = SIGNBIT_DP64 - iy; + my = iy < 0 ? my : iy; + long t = mx + (mx < my ? 1 : -1); + long r = SIGNBIT_DP64 - t; + r = t < 0 ? r : t; + r = (mx == -1L && mx < my) ? SIGNBIT_DP64 : r; + + if (!FINITE_ONLY_OPT()) { + r = BUILTIN_ISNAN_F64(x) ? ix : r; + r = BUILTIN_ISNAN_F64(y) ? iy : r; + } + + r = (ix == iy || (AS_LONG(BUILTIN_ABS_F64(x)) | AS_LONG(BUILTIN_ABS_F64(y))) == 0L) ? iy : r; + return AS_DOUBLE(r); +} + diff --git a/amd/device-libs/ocml/src/nextafterF.cl b/amd/device-libs/ocml/src/nextafterF.cl new file mode 100644 index 0000000000000..df5e4aa396942 --- /dev/null +++ b/amd/device-libs/ocml/src/nextafterF.cl @@ -0,0 +1,32 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(nextafter)(float x, float y) +{ + int ix = AS_INT(x); + int mx = SIGNBIT_SP32 - ix; + mx = ix < 0 ? mx : ix; + int iy = AS_INT(y); + int my = SIGNBIT_SP32 - iy; + my = iy < 0 ? my : iy; + int t = mx + (mx < my ? 1 : -1); + int r = SIGNBIT_SP32 - t; + r = t < 0 ? r : t; + r = (mx == -1 && mx < my) ? SIGNBIT_SP32 : r; + + if (!FINITE_ONLY_OPT()) { + r = BUILTIN_ISNAN_F32(x) ? ix : r; + r = BUILTIN_ISNAN_F32(y) ? iy : r; + } + + r = (ix == iy || (AS_INT(BUILTIN_ABS_F32(x)) | AS_INT(BUILTIN_ABS_F32(y))) == 0) ? iy : r; + return AS_FLOAT(r); +} + diff --git a/amd/device-libs/ocml/src/nextafterH.cl b/amd/device-libs/ocml/src/nextafterH.cl new file mode 100644 index 0000000000000..d84bf2a3d1259 --- /dev/null +++ b/amd/device-libs/ocml/src/nextafterH.cl @@ -0,0 +1,34 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(nextafter) + +CONSTATTR half +MATH_MANGLE(nextafter)(half x, half y) +{ + short ix = AS_SHORT(x); + short mx = (short)SIGNBIT_HP16 - ix; + mx = ix < (short)0 ? mx : ix; + short iy = AS_SHORT(y); + short my = (short)SIGNBIT_HP16 - iy; + my = iy < (short)0 ? my : iy; + short t = mx + (mx < my ? (short)1 : (short)-1); + short r = (short)SIGNBIT_HP16 - t; + r = t < (short)0 ? r : t; + r = (mx == (short)-1 && mx < my) ? (short)SIGNBIT_HP16 : r; + + if (!FINITE_ONLY_OPT()) { + r = BUILTIN_ISNAN_F16(x) ? ix : r; + r = BUILTIN_ISNAN_F16(y) ? iy : r; + } + + r = (ix == iy || (AS_SHORT(BUILTIN_ABS_F16(x)) | AS_SHORT(BUILTIN_ABS_F16(y))) == (short)0) ? iy : r; + return AS_HALF(r); +} + diff --git a/amd/device-libs/ocml/src/opts.h b/amd/device-libs/ocml/src/opts.h new file mode 100644 index 0000000000000..2d9a24b3a14e6 --- /dev/null +++ b/amd/device-libs/ocml/src/opts.h @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +#define HAVE_FAST_FMA32() (__oclc_ISA_version == 7001 || __oclc_ISA_version == 8001 || __oclc_ISA_version >= 9000) +#define FINITE_ONLY_OPT() __oclc_finite_only_opt +#define UNSAFE_MATH_OPT() __oclc_unsafe_math_opt + +#define DAZ_OPT() __builtin_isfpclass(__builtin_canonicalizef(0x1p-149f), __FPCLASS_POSZERO) diff --git a/amd/device-libs/ocml/src/powD.cl b/amd/device-libs/ocml/src/powD.cl new file mode 100644 index 0000000000000..0776406e816b4 --- /dev/null +++ b/amd/device-libs/ocml/src/powD.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_POW +#include "powD_base.h" + diff --git a/amd/device-libs/ocml/src/powD_base.h b/amd/device-libs/ocml/src/powD_base.h new file mode 100644 index 0000000000000..fe6855a6868ee --- /dev/null +++ b/amd/device-libs/ocml/src/powD_base.h @@ -0,0 +1,155 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +extern CONSTATTR double2 MATH_PRIVATE(epln)(double); +extern CONSTATTR double MATH_PRIVATE(expep)(double2); + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +static bool is_integer(double ay) +{ + return BUILTIN_TRUNC_F64(ay) == ay; +} + +static bool is_even_integer(double ay) { + // Even integers are still integers after division by 2. + return is_integer(0.5 * ay); +} + +static bool is_odd_integer(double ay) { + return is_integer(ay) && !is_even_integer(ay); +} + +#if defined(COMPILING_POW) + +CONSTATTR double +MATH_MANGLE(pow)(double x, double y) +{ + if (x == 1.0) + y = 1.0; + if (y == 0.0) + x = 1.0; + + double ax = BUILTIN_ABS_F64(x); + double expylnx = MATH_PRIVATE(expep)(omul(y, MATH_PRIVATE(epln)(ax))); + + bool is_odd_y = is_odd_integer(y); + + double ret = BUILTIN_COPYSIGN_F64(expylnx, is_odd_y ? x : 1.0); + + // Now all the edge cases + if (x < 0.0 && !is_integer(y)) + ret = QNAN_F64; + + double ay = BUILTIN_ABS_F64(y); + if (BUILTIN_ISINF_F64(ay)) { + // FIXME: Missing backend optimization to save on + // materialization cost of mixed sign constant infinities. + bool y_is_neg_inf = y != ay; + ret = ax == 1.0 ? ax : ((ax < 1.0) ^ y_is_neg_inf ? 0.0 : ay); + } + + if (BUILTIN_ISINF_F64(ax) || x == 0.0) + ret = BUILTIN_COPYSIGN_F64((x == 0.0) ^ (y < 0.0) ? 0.0 : PINF_F64, + is_odd_y ? x : 0.0); + + if (BUILTIN_ISUNORDERED_F64(x, y)) + ret = QNAN_F64; + + return ret; +} + + +#elif defined(COMPILING_POWR) + +CONSTATTR double +MATH_MANGLE(powr)(double x, double y) +{ + if (x < 0.0) + x = QNAN_F64; + + double ret = MATH_PRIVATE(expep)(omul(y, MATH_PRIVATE(epln)(x))); + + // Now all the edge cases + double iz = y < 0.0 ? PINF_F64 : 0.0; + double zi = y < 0.0 ? 0.0 : PINF_F64; + + if (x == 0.0) + ret = y == 0.0 ? QNAN_F64 : iz; + + if (x == PINF_F64 && y != 0.0) + ret = zi; + + if (BUILTIN_ISINF_F64(y) && x != 1.0) + ret = x < 1.0 ? iz : zi; + + if (y == 0.0) + ret = x == 0.0 || BUILTIN_ISINF_F64(x) ? QNAN_F64 : 1.0; + + if (BUILTIN_ISUNORDERED_F64(x, y)) + ret = QNAN_F64; + + return ret; +} + +#elif defined(COMPILING_POWN) + +CONSTATTR double +MATH_MANGLE(pown)(double x, int ny) +{ + if (ny == 0) + x = 1.0; + + double y = (double) ny; + + double ax = BUILTIN_ABS_F64(x); + double expylnx = MATH_PRIVATE(expep)(omul(y, MATH_PRIVATE(epln)(ax))); + + bool is_odd_y = ny & 1; + + double ret = BUILTIN_COPYSIGN_F64(expylnx, is_odd_y ? x : 1.0); + + // Now all the edge cases + if (BUILTIN_ISINF_F64(ax) || x == 0.0) + ret = BUILTIN_COPYSIGN_F64((x == 0.0) ^ (ny < 0) ? 0.0 : PINF_F64, + is_odd_y ? x : 0.0); + + return ret; +} + +#elif defined(COMPILING_ROOTN) + +CONSTATTR double +MATH_MANGLE(rootn)(double x, int ny) +{ + double2 y = rcp((double)ny); + + double ax = BUILTIN_ABS_F64(x); + double expylnx = MATH_PRIVATE(expep)(omul(y, MATH_PRIVATE(epln)(ax))); + + bool is_odd_y = ny & 1; + + double ret = BUILTIN_COPYSIGN_F64(expylnx, is_odd_y ? x : 1.0); + + // Now all the edge cases + if (BUILTIN_ISINF_F64(ax) || x == 0.0) + ret = BUILTIN_COPYSIGN_F64((x == 0.0) ^ (ny < 0) ? 0.0 : PINF_F64, + is_odd_y ? x : 0.0); + + if ((x < 0.0 && !is_odd_y) || ny == 0) + ret = QNAN_F64; + + return ret; +} + +#else +#error missing function macro +#endif + diff --git a/amd/device-libs/ocml/src/powF.cl b/amd/device-libs/ocml/src/powF.cl new file mode 100644 index 0000000000000..97fe9a2015599 --- /dev/null +++ b/amd/device-libs/ocml/src/powF.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_POW +#include "powF_base.h" + diff --git a/amd/device-libs/ocml/src/powF_base.h b/amd/device-libs/ocml/src/powF_base.h new file mode 100644 index 0000000000000..dd96e4546c11a --- /dev/null +++ b/amd/device-libs/ocml/src/powF_base.h @@ -0,0 +1,182 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float2 MATH_PRIVATE(epln)(float); +extern CONSTATTR float MATH_PRIVATE(expep)(float2); + +static float fast_expylnx(float ax, float y) +{ + return BUILTIN_EXP2_F32(y * BUILTIN_LOG2_F32(ax)); +} + +static float compute_expylnx_int(float ax, int ny) +{ + if (UNSAFE_MATH_OPT()) + return fast_expylnx(ax, (float)ny); + + int nyh = ny & 0xffff0000; + float2 y = fadd((float)nyh, (float)(ny - nyh)); + return MATH_PRIVATE(expep)(omul(y, MATH_PRIVATE(epln)(ax))); +} + +// root version of compute_expylnx_int +static float compute_exp_inverse_y_lnx_int(float ax, int ny) +{ + if (UNSAFE_MATH_OPT()) { + float y = MATH_FAST_RCP((float)ny); + return fast_expylnx(ax, y); + } + + int nyh = ny & 0xffff0000; + float2 y = fadd((float)nyh, (float)(ny - nyh)); + y = rcp(y); + return MATH_PRIVATE(expep)(omul(y, MATH_PRIVATE(epln)(ax))); +} + +static float compute_expylnx_float(float ax, float y) +{ + if (UNSAFE_MATH_OPT()) + return fast_expylnx(ax, y); + return MATH_PRIVATE(expep)(omul(y, MATH_PRIVATE(epln)(ax))); +} + +static bool is_integer(float ay) +{ + return BUILTIN_TRUNC_F32(ay) == ay; +} + +static bool is_even_integer(float ay) { + // Even integers are still integers after division by 2. + return is_integer(0.5f * ay); +} + +static bool is_odd_integer(float ay) { + return is_integer(ay) && !is_even_integer(ay); +} + +#if defined(COMPILING_POW) + +CONSTATTR float +MATH_MANGLE(pow)(float x, float y) +{ + if (x == 1.0f) + y = 1.0f; + if (y == 0.0f) + x = 1.0f; + + float ax = BUILTIN_ABS_F32(x); + float expylnx = compute_expylnx_float(ax, y); + + bool is_odd_y = is_odd_integer(y); + + float ret = BUILTIN_COPYSIGN_F32(expylnx, is_odd_y ? x : 1.0f); + + // Now all the edge cases + if (x < 0.0f && !is_integer(y)) + ret = QNAN_F32; + + float ay = BUILTIN_ABS_F32(y); + if (BUILTIN_ISINF_F32(ay)) { + // FIXME: Missing backend optimization to save on + // materialization cost of mixed sign constant infinities. + bool y_is_neg_inf = y != ay; + ret = ax == 1.0f ? ax : ((ax < 1.0f) ^ y_is_neg_inf ? 0.0f : ay); + } + + if (BUILTIN_ISINF_F32(ax) || x == 0.0f) + ret = BUILTIN_COPYSIGN_F32((x == 0.0f) ^ (y < 0.0f) ? 0.0f : PINF_F32, + is_odd_y ? x : 0.0f); + + if (BUILTIN_ISUNORDERED_F32(x, y)) + ret = QNAN_F32; + + return ret; +} + +#elif defined(COMPILING_POWR) + +CONSTATTR float +MATH_MANGLE(powr)(float x, float y) +{ + if (x < 0.0f) + x = QNAN_F32; + + float ret = compute_expylnx_float(x, y); + + // Now all the edge cases + float iz = y < 0.0f ? PINF_F32 : 0.0f; + float zi = y < 0.0f ? 0.0f : PINF_F32; + + if (x == 0.0f) + ret = y == 0.0f ? QNAN_F32 : iz; + + if (x == PINF_F32 && y != 0.0f) + ret = zi; + + if (BUILTIN_ISINF_F32(y) && x != 1.0f) + ret = x < 1.0f ? iz : zi; + + if (BUILTIN_ISUNORDERED_F32(x, y)) + ret = QNAN_F32; + + return ret; +} + +#elif defined(COMPILING_POWN) + +CONSTATTR float +MATH_MANGLE(pown)(float x, int ny) +{ + if (ny == 0) + x = 1.0f; + + float ax = BUILTIN_ABS_F32(x); + float expylnx = compute_expylnx_int(ax, ny); + + bool is_odd_y = ny & 1; + + float ret = BUILTIN_COPYSIGN_F32(expylnx, is_odd_y ? x : 1.0f); + + // Now all the edge cases + if (BUILTIN_ISINF_F32(ax) || x == 0.0f) + ret = BUILTIN_COPYSIGN_F32((x == 0.0f) ^ (ny < 0) ? 0.0f : PINF_F32, + is_odd_y ? x : 0.0f); + return ret; +} + +#elif defined(COMPILING_ROOTN) + +CONSTATTR float +MATH_MANGLE(rootn)(float x, int ny) +{ + float ax = BUILTIN_ABS_F32(x); + float expylnx = compute_exp_inverse_y_lnx_int(ax, ny); + + bool is_odd_y = ny & 1; + + float ret = BUILTIN_COPYSIGN_F32(expylnx, is_odd_y ? x : 1.0f); + + // Now all the edge cases + if (BUILTIN_ISINF_F32(ax) || x == 0.0f) + ret = BUILTIN_COPYSIGN_F32((x == 0.0f) ^ (ny < 0) ? 0.0f : PINF_F32, + is_odd_y ? x : 0.0f); + + if ((x < 0.0f && !is_odd_y) || ny == 0) + ret = QNAN_F32; + + return ret; +} + +#else +#error missing function macro +#endif + diff --git a/amd/device-libs/ocml/src/powH.cl b/amd/device-libs/ocml/src/powH.cl new file mode 100644 index 0000000000000..26c76c54b5c00 --- /dev/null +++ b/amd/device-libs/ocml/src/powH.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(pow) + +#define COMPILING_POW +#include "powH_base.h" + diff --git a/amd/device-libs/ocml/src/powH_base.h b/amd/device-libs/ocml/src/powH_base.h new file mode 100644 index 0000000000000..7eb1ef8d08f55 --- /dev/null +++ b/amd/device-libs/ocml/src/powH_base.h @@ -0,0 +1,150 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +static float compute_expylnx_f16(half ax, half y) +{ + return BUILTIN_AMDGPU_EXP2_F32((float)y * BUILTIN_AMDGPU_LOG2_F32((float)ax)); +} + +static bool is_integer(half ay) +{ + return BUILTIN_TRUNC_F16(ay) == ay; +} + +static bool is_even_integer(half ay) { + // Even integers are still integers after division by 2. + return is_integer(0.5h * ay); +} + +static bool is_odd_integer(half ay) { + return is_integer(ay) && !is_even_integer(ay); +} + +#if defined(COMPILING_POW) + +CONSTATTR half +MATH_MANGLE(pow)(half x, half y) +{ + if (x == 1.0h) + y = 1.0h; + if (y == 0.0h) + x = 1.0h; + + half ax = BUILTIN_ABS_F16(x); + float p = compute_expylnx_f16(ax, y); + + bool is_odd_y = is_odd_integer(y); + half ret = BUILTIN_COPYSIGN_F16((half)p, is_odd_y ? x : 1.0f); + + // Now all the edge cases + if (x < 0.0h && !is_integer(y)) + ret = QNAN_F16; + + half ay = BUILTIN_ABS_F16(y); + if (BUILTIN_ISINF_F16(ay)) { + // FIXME: Missing backend optimization to save on + // materialization cost of mixed sign constant infinities. + bool y_is_neg_inf = y != ay; + ret = ax == 1.0h ? ax : ((ax < 1.0h) ^ y_is_neg_inf ? 0.0h : ay); + } + + if (BUILTIN_ISINF_F16(ax) || x == 0.0h) { + ret = BUILTIN_COPYSIGN_F16((x == 0.0h) ^ (y < 0.0h) ? 0.0h : PINF_F16, + is_odd_y ? x : 0.0h); + } + + if (BUILTIN_ISUNORDERED_F16(x, y)) + ret = QNAN_F16; + + return ret; +} + +#elif defined(COMPILING_POWR) + +CONSTATTR half +MATH_MANGLE(powr)(half x, half y) +{ + if (x < 0.0h) + x = QNAN_F16; + + half ret = (half)compute_expylnx_f16(x, y); + + // Now all the edge cases + half iz = y < 0.0h ? PINF_F16 : 0.0h; + half zi = y < 0.0h ? 0.0h : PINF_F16; + + if (x == 0.0h) + ret = y == 0.0h ? QNAN_F16 : iz; + + if (x == PINF_F16 && y != 0.0h) + ret = zi; + + if (BUILTIN_ISINF_F16(y) && x != 1.0h) + ret = x < 1.0h ? iz : zi; + + if (BUILTIN_ISUNORDERED_F16(x, y)) + ret = QNAN_F16; + + return ret; +} + + +#elif defined(COMPILING_POWN) + +CONSTATTR half +MATH_MANGLE(pown)(half x, int ny) +{ + if (ny == 0) + x = 1.0h; + + half ax = BUILTIN_ABS_F16(x); + + float fy = (float)ny; + + float p = BUILTIN_AMDGPU_EXP2_F32(fy * BUILTIN_AMDGPU_LOG2_F32((float)ax)); + + bool is_odd_y = ny & 1; + + half ret = BUILTIN_COPYSIGN_F16((half)p, is_odd_y ? x : 1.0f); + + // Now all the edge cases + if (BUILTIN_ISINF_F16(ax) || x == 0.0h) + ret = BUILTIN_COPYSIGN_F16((x == 0.0h) ^ (ny < 0) ? 0.0h : PINF_F16, + is_odd_y ? x : 0.0h); + + return ret; +} + +#elif defined(COMPILING_ROOTN) + +CONSTATTR half +MATH_MANGLE(rootn)(half x, int ny) +{ + half ax = BUILTIN_ABS_F16(x); + + float fy = BUILTIN_AMDGPU_RCP_F32((float)ny); + + float p = BUILTIN_AMDGPU_EXP2_F32(fy * BUILTIN_AMDGPU_LOG2_F32((float)ax)); + + bool is_odd_y = ny & 1; + + half ret = BUILTIN_COPYSIGN_F16((half)p, is_odd_y ? x : 1.0f); + + // Now all the edge cases + if (BUILTIN_ISINF_F16(ax) || x == 0.0h) + ret = BUILTIN_COPYSIGN_F16((x == 0.0h) ^ (ny < 0) ? 0.0h : PINF_F16, + is_odd_y ? x : 0.0h); + + if ((x < 0.0h && !is_odd_y) || ny == 0) + ret = QNAN_F16; + + return ret; +} + +#else +#error missing function macro +#endif diff --git a/amd/device-libs/ocml/src/pownD.cl b/amd/device-libs/ocml/src/pownD.cl new file mode 100644 index 0000000000000..95cd95cac1e53 --- /dev/null +++ b/amd/device-libs/ocml/src/pownD.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_POWN +#include "powD_base.h" + diff --git a/amd/device-libs/ocml/src/pownF.cl b/amd/device-libs/ocml/src/pownF.cl new file mode 100644 index 0000000000000..1eab4f188021e --- /dev/null +++ b/amd/device-libs/ocml/src/pownF.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_POWN +#include "powF_base.h" + diff --git a/amd/device-libs/ocml/src/pownH.cl b/amd/device-libs/ocml/src/pownH.cl new file mode 100644 index 0000000000000..1812e1bd68716 --- /dev/null +++ b/amd/device-libs/ocml/src/pownH.cl @@ -0,0 +1,18 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(pown)(half2 x, int2 ny) +{ + return (half2)(MATH_MANGLE(pown)(x.lo, ny.lo), MATH_MANGLE(pown)(x.hi, ny.hi)); +} + +#define COMPILING_POWN +#include "powH_base.h" + diff --git a/amd/device-libs/ocml/src/powrD.cl b/amd/device-libs/ocml/src/powrD.cl new file mode 100644 index 0000000000000..0c9e77c334faa --- /dev/null +++ b/amd/device-libs/ocml/src/powrD.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_POWR +#include "powD_base.h" + diff --git a/amd/device-libs/ocml/src/powrF.cl b/amd/device-libs/ocml/src/powrF.cl new file mode 100644 index 0000000000000..cb8d2f0692947 --- /dev/null +++ b/amd/device-libs/ocml/src/powrF.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_POWR +#include "powF_base.h" + diff --git a/amd/device-libs/ocml/src/powrH.cl b/amd/device-libs/ocml/src/powrH.cl new file mode 100644 index 0000000000000..5c9b6dad5c12f --- /dev/null +++ b/amd/device-libs/ocml/src/powrH.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(powr) + +#define COMPILING_POWR +#include "powH_base.h" + diff --git a/amd/device-libs/ocml/src/predD.cl b/amd/device-libs/ocml/src/predD.cl new file mode 100644 index 0000000000000..72c865f0f2384 --- /dev/null +++ b/amd/device-libs/ocml/src/predD.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(pred)(double x) +{ + long ix = AS_LONG(x); + long mx = SIGNBIT_DP64 - ix; + mx = ix < 0 ? mx : ix; + long t = mx - (x != NINF_F64 && !BUILTIN_ISNAN_F64(x)); + long r = SIGNBIT_DP64 - t; + r = t < 0 ? r : t; + return AS_DOUBLE(r); +} + diff --git a/amd/device-libs/ocml/src/predF.cl b/amd/device-libs/ocml/src/predF.cl new file mode 100644 index 0000000000000..3432838736953 --- /dev/null +++ b/amd/device-libs/ocml/src/predF.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(pred)(float x) +{ + int ix = AS_INT(x); + int mx = SIGNBIT_SP32 - ix; + mx = ix < 0 ? mx : ix; + int t = mx - (x != NINF_F32 && !BUILTIN_ISNAN_F32(x)); + int r = SIGNBIT_SP32 - t; + r = t < 0 ? r : t; + return AS_FLOAT(r); +} + diff --git a/amd/device-libs/ocml/src/predH.cl b/amd/device-libs/ocml/src/predH.cl new file mode 100644 index 0000000000000..29d5345a7676f --- /dev/null +++ b/amd/device-libs/ocml/src/predH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_MANGLE(pred)(half x) +{ + short ix = AS_SHORT(x); + short mx = (short)SIGNBIT_HP16 - ix; + mx = ix < (short)0 ? mx : ix; + short t = mx - (short)(x != NINF_F16 && !BUILTIN_ISNAN_F16(x)); + short r = (short)SIGNBIT_HP16 - t; + r = t < (short)0 ? r : t; + return AS_HALF(r); +} + diff --git a/amd/device-libs/ocml/src/privD.h b/amd/device-libs/ocml/src/privD.h new file mode 100644 index 0000000000000..54469be24ecdf --- /dev/null +++ b/amd/device-libs/ocml/src/privD.h @@ -0,0 +1,47 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define MATH_MAD(A,B,C) BUILTIN_FMA_F64(A, B, C) + +#define MATH_FAST_RCP(X) ({ \ + double _frcp_x = X; \ + double _frcp_ret; \ + _frcp_ret = BUILTIN_AMDGPU_RCP_F64(_frcp_x); \ + _frcp_ret = BUILTIN_FMA_F64(BUILTIN_FMA_F64(-_frcp_x, _frcp_ret, 1.0), _frcp_ret, _frcp_ret); \ + _frcp_ret = BUILTIN_FMA_F64(BUILTIN_FMA_F64(-_frcp_x, _frcp_ret, 1.0), _frcp_ret, _frcp_ret); \ + _frcp_ret; \ +}) +#define MATH_RCP(X) BUILTIN_DIV_F64(1.0, X) + +#define MATH_FAST_DIV(X, Y) ({ \ + double _fdiv_x = X; \ + double _fdiv_y = Y; \ + double _fdiv_ret; \ + double _fdiv_r = BUILTIN_AMDGPU_RCP_F64(_fdiv_y); \ + _fdiv_r = BUILTIN_FMA_F64(BUILTIN_FMA_F64(-_fdiv_y, _fdiv_r, 1.0), _fdiv_r, _fdiv_r); \ + _fdiv_r = BUILTIN_FMA_F64(BUILTIN_FMA_F64(-_fdiv_y, _fdiv_r, 1.0), _fdiv_r, _fdiv_r); \ + _fdiv_ret = _fdiv_x * _fdiv_r; \ + _fdiv_ret = BUILTIN_FMA_F64(BUILTIN_FMA_F64(-_fdiv_y, _fdiv_ret, _fdiv_x), _fdiv_r, _fdiv_ret); \ + _fdiv_ret; \ +}) +#define MATH_DIV(X,Y) BUILTIN_DIV_F64(X, Y) + +#define MATH_FAST_SQRT(X) ({ \ + double _fsqrt_x = X; \ + double _fsqrt_y = BUILTIN_AMDGPU_RSQRT_F64(_fsqrt_x); \ + double _fsqrt_s0 = _fsqrt_x * _fsqrt_y; \ + double _fsqrt_h0 = 0.5 * _fsqrt_y; \ + double _fsqrt_r0 = BUILTIN_FMA_F64(-_fsqrt_h0, _fsqrt_s0, 0.5); \ + double _fsqrt_h1 = BUILTIN_FMA_F64(_fsqrt_h0, _fsqrt_r0, _fsqrt_h0); \ + double _fsqrt_s1 = BUILTIN_FMA_F64(_fsqrt_s0, _fsqrt_r0, _fsqrt_s0); \ + double _fsqrt_d0 = BUILTIN_FMA_F64(-_fsqrt_s1, _fsqrt_s1, _fsqrt_x); \ + double _fsqrt_ret = BUILTIN_FMA_F64(_fsqrt_d0, _fsqrt_h1, _fsqrt_s1); \ + _fsqrt_ret = _fsqrt_x == 0.0 ? _fsqrt_x : _fsqrt_ret; \ + _fsqrt_ret; \ +}) + +#define MATH_SQRT(X) BUILTIN_SQRT_F64(X) diff --git a/amd/device-libs/ocml/src/privF.h b/amd/device-libs/ocml/src/privF.h new file mode 100644 index 0000000000000..5cb8b44b8130a --- /dev/null +++ b/amd/device-libs/ocml/src/privF.h @@ -0,0 +1,50 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define MATH_MAD(A,B,C) BUILTIN_MAD_F32(A, B, C) +#define MATH_MAD2(A,B,C) BUILTIN_MAD_2F32(A, B, C) + +#define MATH_FAST_RCP(X) BUILTIN_AMDGPU_RCP_F32(X) +#define MATH_RCP(X) BUILTIN_DIV_F32(1.0f, X) + +#define MATH_FAST_DIV(X, Y) ({ \ + float _fdiv_x = X; \ + float _fdiv_y = Y; \ + float _fdiv_ret = _fdiv_x * BUILTIN_AMDGPU_RCP_F32(_fdiv_y); \ + _fdiv_ret; \ +}) +#define MATH_DIV(X,Y) BUILTIN_DIV_F32(X, Y) + +#define MATH_FAST_SQRT(X) BUILTIN_AMDGPU_SQRT_F32(X) + +#define MATH_SQRT(X) ({ \ + float _sqrt_x = X; \ + bool _sqrt_b = _sqrt_x < 0x1.0p-96f; \ + _sqrt_x *= _sqrt_b ? 0x1.0p+32f : 1.0f; \ + float _sqrt_s; \ + if (!DAZ_OPT()) { \ + _sqrt_s = BUILTIN_AMDGPU_SQRT_F32(_sqrt_x); \ + float _sqrt_sp = AS_FLOAT(AS_INT(_sqrt_s) - 1); \ + float _sqrt_ss = AS_FLOAT(AS_INT(_sqrt_s) + 1); \ + float _sqrt_vp = BUILTIN_FMA_F32(-_sqrt_sp, _sqrt_s, _sqrt_x); \ + float _sqrt_vs = BUILTIN_FMA_F32(-_sqrt_ss, _sqrt_s, _sqrt_x); \ + _sqrt_s = _sqrt_vp <= 0.0f ? _sqrt_sp : _sqrt_s; \ + _sqrt_s = _sqrt_vs > 0.0f ? _sqrt_ss : _sqrt_s; \ + } else { \ + float _sqrt_r = BUILTIN_AMDGPU_RSQRT_F32(_sqrt_x); \ + _sqrt_s = _sqrt_x * _sqrt_r; \ + float _sqrt_h = 0.5f * _sqrt_r; \ + float _sqrt_e = BUILTIN_FMA_F32(-_sqrt_h, _sqrt_s, 0.5f); \ + _sqrt_h = BUILTIN_FMA_F32(_sqrt_h, _sqrt_e, _sqrt_h); \ + _sqrt_s = BUILTIN_FMA_F32(_sqrt_s, _sqrt_e, _sqrt_s); \ + float _sqrt_d = BUILTIN_FMA_F32(-_sqrt_s, _sqrt_s, _sqrt_x); \ + _sqrt_s = BUILTIN_FMA_F32(_sqrt_d, _sqrt_h, _sqrt_s); \ + } \ + _sqrt_s *= _sqrt_b ? 0x1.0p-16f : 1.0f; \ + _sqrt_s = BUILTIN_CLASS_F32(_sqrt_x, CLASS_PZER|CLASS_NZER|CLASS_PINF) ? _sqrt_x : _sqrt_s; \ + _sqrt_s; \ +}) diff --git a/amd/device-libs/ocml/src/privH.h b/amd/device-libs/ocml/src/privH.h new file mode 100644 index 0000000000000..b05ab2c8876cc --- /dev/null +++ b/amd/device-libs/ocml/src/privH.h @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define MATH_MAD(A,B,C) BUILTIN_FMA_F16(A, B, C) +#define MATH_MAD2(A,B,C) BUILTIN_FMA_2F16(A, B, C) + +#define MATH_FAST_RCP(X) BUILTIN_RCP_F16(X) +#define MATH_RCP(X) BUILTIN_DIV_F16(1.0h, X) + +#define MATH_FAST_DIV(X, Y) ({ \ + half _fdiv_x = X; \ + half _fdiv_y = Y; \ + half _fdiv_ret = _fdiv_x * BUILTIN_RCP_F16(_fdiv_y); \ + _fdiv_ret; \ +}) +#define MATH_DIV(X,Y) BUILTIN_DIV_F16(X, Y) + +#define MATH_FAST_SQRT(X) BUILTIN_SQRT_F16(X) +#define MATH_SQRT(X) ((half)BUILTIN_AMDGPU_SQRT_F32((float)(X))) diff --git a/amd/device-libs/ocml/src/rcbrtD.cl b/amd/device-libs/ocml/src/rcbrtD.cl new file mode 100644 index 0000000000000..96bbcb88334fa --- /dev/null +++ b/amd/device-libs/ocml/src/rcbrtD.cl @@ -0,0 +1,37 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(rcbrt)(double x) +{ + double a = BUILTIN_ABS_F64(x); + int e3 = BUILTIN_FREXP_EXP_F64(a); + int e = (int)BUILTIN_RINT_F32(0x1.555556p-2f * (float)e3); + a = BUILTIN_FLDEXP_F64(a, -3*e); + + double c = (double)BUILTIN_AMDGPU_EXP2_F32(-0x1.555556p-2f * BUILTIN_AMDGPU_LOG2_F32((float)a)); + + // Correction is c + c*(1 - a c^3)/(1 + 2 a c^3) + // = c + c*t/(3 - 2t) where t = 1 - a c^3 + // use t/(3 - 2t) ~ t/3 + 2 t^2 / 9 + 4 t^3 / 27 ... + // compute t with extra precision for better accuracy + double c3 = c * c * c; + double t = MATH_MAD(-a, c3, 1.0); + c = MATH_MAD(c, t*MATH_MAD(t, 0x1.c71c71c71c8b2p-3, 0x1.5555555555685p-2), c); + + c = BUILTIN_FLDEXP_F64(c, -e); + + if (!FINITE_ONLY_OPT()) { + c = a == PINF_F64 ? 0.0 : c; + c = x == 0.0 ? PINF_F64 : c; + } + + return BUILTIN_COPYSIGN_F64(c, x); +} + diff --git a/amd/device-libs/ocml/src/rcbrtF.cl b/amd/device-libs/ocml/src/rcbrtF.cl new file mode 100644 index 0000000000000..ebf1f06b105d3 --- /dev/null +++ b/amd/device-libs/ocml/src/rcbrtF.cl @@ -0,0 +1,41 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +// Subnormal or zero. +#define IS_LT_SMALLEST_NORMAL(x) (x < 0x1p-126f) + +CONSTATTR float +MATH_MANGLE(rcbrt)(float x) +{ + if (DAZ_OPT()) { + x = BUILTIN_CANONICALIZE_F32(x); + } + + float ax = BUILTIN_ABS_F32(x); + bool do_scale = IS_LT_SMALLEST_NORMAL(ax); + + if (!DAZ_OPT()) { + ax = do_scale ? BUILTIN_FLDEXP_F32(ax, 24) : ax; + } + + float z = BUILTIN_AMDGPU_EXP2_F32(-0x1.555556p-2f * BUILTIN_AMDGPU_LOG2_F32(ax)); + z = MATH_MAD(MATH_MAD(z*z, -z*ax, 1.0f), 0x1.555556p-2f*z, z); + + if (!DAZ_OPT()) { + z = do_scale ? BUILTIN_FLDEXP_F32(z, 8) : z; + } + + float xi = MATH_FAST_RCP(x); + + // Is normal or subnormal + z = ((x != 0.0f) & BUILTIN_ISFINITE_F32(x)) ? z : xi; + + return BUILTIN_COPYSIGN_F32(z, x); +} + diff --git a/amd/device-libs/ocml/src/rcbrtH.cl b/amd/device-libs/ocml/src/rcbrtH.cl new file mode 100644 index 0000000000000..f0dcb22db5432 --- /dev/null +++ b/amd/device-libs/ocml/src/rcbrtH.cl @@ -0,0 +1,24 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(rcbrt) + +CONSTATTR half +MATH_MANGLE(rcbrt)(half x) +{ + half ret = (half)BUILTIN_AMDGPU_EXP2_F32(-0x1.555556p-2f * BUILTIN_AMDGPU_LOG2_F32((float)BUILTIN_ABS_F16(x))); + + half xi = MATH_FAST_RCP(x); + + // Is normal or subnormal + ret = ((x != 0.0h) & BUILTIN_ISFINITE_F16(x)) ? ret : xi; + + return BUILTIN_COPYSIGN_F16(ret, x); +} + diff --git a/amd/device-libs/ocml/src/remainderD.cl b/amd/device-libs/ocml/src/remainderD.cl new file mode 100644 index 0000000000000..9ea176f09cac0 --- /dev/null +++ b/amd/device-libs/ocml/src/remainderD.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_REMAINDER +#include "remainderD_base.h" + diff --git a/amd/device-libs/ocml/src/remainderD_base.h b/amd/device-libs/ocml/src/remainderD_base.h new file mode 100644 index 0000000000000..c3ef77a168ef9 --- /dev/null +++ b/amd/device-libs/ocml/src/remainderD_base.h @@ -0,0 +1,151 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR static double +fnma(double a, double b, double c) +{ + return BUILTIN_FMA_F64(-a, b, c); +} + +#if defined(COMPILING_FMOD) +CONSTATTR double +MATH_MANGLE(fmod)(double x, double y) +#elif defined(COMPILING_REMQUO) +__ocml_remquo_f64_result +MATH_MANGLE(remquo2)(double x, double y) +#else +CONSTATTR double +MATH_MANGLE(remainder)(double x, double y) +#endif +{ + // How many bits of the quotient per iteration + const int bits = 26; + + double ax = BUILTIN_ABS_F64(x); + double ay = BUILTIN_ABS_F64(y); + double ret; +#if defined(COMPILING_REMQUO) + int q7; +#endif + + if (ax > ay) { + int ex, ey; + + ex = BUILTIN_FREXP_EXP_F64(ax) - 1; + ax = BUILTIN_FLDEXP_F64(BUILTIN_FREXP_MANT_F64(ax), bits); + ey = BUILTIN_FREXP_EXP_F64(ay) - 1; + ay = BUILTIN_FLDEXP_F64(BUILTIN_FREXP_MANT_F64(ay), 1); + + int nb = ex - ey; + double ayinv = MATH_RCP(ay); + +#if !defined(COMPILING_FMOD) + int qacc = 0; +#endif + + while (nb > bits) { + double q = BUILTIN_RINT_F64(ax * ayinv); + ax = fnma(q, ay, ax); + int clt = ax < 0.0; + double axp = ax + ay; + ax = clt ? axp : ax; +#if defined(COMPILING_REMQUO) + int iq = (int)q; + iq -= clt; + qacc = (qacc << bits) | iq; +#endif + ax = BUILTIN_FLDEXP_F64(ax, bits); + nb -= bits; + } + + ax = BUILTIN_FLDEXP_F64(ax, nb - bits + 1); + + // Final iteration + { + double q = BUILTIN_RINT_F64(ax * ayinv); + ax = fnma(q, ay, ax); + int clt = ax < 0.0; + double axp = ax + ay; + ax = clt ? axp : ax; +#if !defined(COMPILING_FMOD) + int iq = (int)q; + iq -= clt; +#if defined(COMPILING_REMQUO) + qacc = (qacc << (nb+1)) | iq; +#else + qacc = iq; +#endif +#endif + } + +#if !defined(COMPILING_FMOD) + // Adjust ax so that it is the range (-y/2, y/2] + // We need to choose the even integer when x/y is midway between two integers + int aq = (2.0*ax > ay) | ((qacc & 0x1) & (2.0f*ax == ay)); + ax = ax - (aq ? ay : 0.0f); +#if defined(COMPILING_REMQUO) + qacc += aq; + int qneg = (AS_INT2(x).hi ^ AS_INT2(y).hi) >> 31; + q7 = ((qacc & 0x7f) ^ qneg) - qneg; +#endif +#endif + + ax = BUILTIN_FLDEXP_F64(ax, ey); + ret = AS_DOUBLE((AS_ULONG(x) & SIGNBIT_DP64) ^ AS_ULONG(ax)); + } else { + ret = x; +#if defined(COMPILING_REMQUO) + q7 = 0; +#endif + +#if !defined(COMPILING_FMOD) + int c = (ay < 0x1.0p+1023 & 2.0*ax > ay) | (ax > 0.5*ay); + + int qsgn = 1 + (((AS_INT2(x).hi ^ AS_INT2(y).hi) >> 31) << 1); + double t = MATH_MAD(y, -(double)qsgn, x); + ret = c ? t : ret; +#if defined(COMPILING_REMQUO) + q7 = c ? qsgn : q7; +#endif +#endif + ret = ax == ay ? BUILTIN_COPYSIGN_F64(0.0, x) : ret; +#if defined(COMPILING_REMQUO) + q7 = ax == ay ? qsgn : q7; +#endif + } + + if (!FINITE_ONLY_OPT()) { + ret = y == 0.0 ? QNAN_F64 : ret; +#if defined(COMPILING_REMQUO) + q7 = y == 0.0 ? 0 : q7; +#endif + + bool c = !BUILTIN_ISNAN_F64(y) && BUILTIN_ISFINITE_F64(x); + ret = c ? ret : QNAN_F64; +#if defined(COMPILING_REMQUO) + q7 = c ? q7 : 0; +#endif + } + +#if defined(COMPILING_REMQUO) + __ocml_remquo_f64_result result = { ret, q7 }; + return result; +#else + return ret; +#endif +} + +#if defined(COMPILING_REMQUO) +double +MATH_MANGLE(remquo)(double x, double y, __private int *q7p) { + __ocml_remquo_f64_result result = MATH_MANGLE(remquo2)(x, y); + *q7p = result.quo; + return result.rem; +} +#endif diff --git a/amd/device-libs/ocml/src/remainderF.cl b/amd/device-libs/ocml/src/remainderF.cl new file mode 100644 index 0000000000000..48a3640b53390 --- /dev/null +++ b/amd/device-libs/ocml/src/remainderF.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_REMAINDER +#include "remainderF_base.h" + diff --git a/amd/device-libs/ocml/src/remainderF_base.h b/amd/device-libs/ocml/src/remainderF_base.h new file mode 100644 index 0000000000000..af2b45e52369a --- /dev/null +++ b/amd/device-libs/ocml/src/remainderF_base.h @@ -0,0 +1,173 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +// The arguments must only be variable names +#define FULL_MUL(A, B, CHI, CLO) \ + do { \ + float __ha = AS_FLOAT(AS_UINT(A) & 0xfffff000U); \ + float __ta = A - __ha; \ + float __hb = AS_FLOAT(AS_UINT(B) & 0xfffff000U); \ + float __tb = B - __hb; \ + CHI = A * B; \ + CLO = MATH_MAD(__ta, __tb, MATH_MAD(__ta, __hb, MATH_MAD(__ha, __tb, MATH_MAD(__ha, __hb, -CHI)))); \ + } while (0) + +CONSTATTR static float +fnma(float a, float b, float c) +{ + float d; + if (HAVE_FAST_FMA32()) { + d = BUILTIN_FMA_F32(-a, b, c); + } else { + float h, t; + FULL_MUL(a, b, h, t); + d = c - h; + d = (((c - d) - h) - t) + d; + } + return d; +} + +#if defined(COMPILING_FMOD) +CONSTATTR float +MATH_MANGLE(fmod)(float x, float y) +#elif defined(COMPILING_REMQUO) +__ocml_remquo_f32_result +MATH_MANGLE(remquo2)(float x, float y) +#else +CONSTATTR float +MATH_MANGLE(remainder)(float x, float y) +#endif +{ + // How many bits of the quotient per iteration + const int bits = 12; + float ax = BUILTIN_ABS_F32(x); + float ay = BUILTIN_ABS_F32(y); + + float ret; +#if defined(COMPILING_REMQUO) + int q7; +#endif + + if (ax > ay) { + int ex, ey; + + ex = BUILTIN_FREXP_EXP_F32(ax) - 1; + ax = BUILTIN_FLDEXP_F32(BUILTIN_FREXP_MANT_F32(ax), bits); + ey = BUILTIN_FREXP_EXP_F32(ay) - 1; + ay = BUILTIN_FLDEXP_F32(BUILTIN_FREXP_MANT_F32(ay), 1); + + int nb = ex - ey; + float ayinv = MATH_FAST_RCP(ay); + +#if !defined(COMPILING_FMOD) + int qacc = 0; +#endif + + while (nb > bits) { + float q = BUILTIN_RINT_F32(ax * ayinv); + ax = fnma(q, ay, ax); + int clt = ax < 0.0f; + float axp = ax + ay; + ax = clt ? axp : ax; +#if defined(COMPILING_REMQUO) + int iq = (int)q; + iq -= clt; + qacc = (qacc << bits) | iq; +#endif + ax = BUILTIN_FLDEXP_F32(ax, bits); + nb -= bits; + } + + ax = BUILTIN_FLDEXP_F32(ax, nb - bits + 1); + + // Final iteration + { + float q = BUILTIN_RINT_F32(ax * ayinv); + ax = fnma(q, ay, ax); + int clt = ax < 0.0f; + float axp = ax + ay; + ax = clt ? axp : ax; +#if !defined(COMPILING_FMOD) + int iq = (int)q; + iq -= clt; +#if defined(COMPILING_REMQUO) + qacc = (qacc << (nb+1)) | iq; +#else + qacc = iq; +#endif +#endif + } + +#if !defined(COMPILING_FMOD) + // Adjust ax so that it is the range (-y/2, y/2] + // We need to choose the even integer when x/y is midway between two integers + int aq = (2.0f*ax > ay) | ((qacc & 0x1) & (2.0f*ax == ay)); + ax = ax - (aq ? ay : 0.0f); +#if defined(COMPILING_REMQUO) + qacc += aq; + int qneg = (AS_INT(x) ^ AS_INT(y)) >> 31; + q7 = ((qacc & 0x7f) ^ qneg) - qneg; +#endif +#endif + + ax = BUILTIN_FLDEXP_F32(ax, ey); + ret = AS_FLOAT((AS_INT(x) & SIGNBIT_SP32) ^ AS_INT(ax)); + } else { + ret = x; +#if defined(COMPILING_REMQUO) + q7 = 0; +#endif + +#if !defined(COMPILING_FMOD) + bool c = (ay < 0x1.0p+127f & 2.0f*ax > ay) | (ax > 0.5f*ay); + + int qsgn = 1 + (((AS_INT(x) ^ AS_INT(y)) >> 31) << 1); + float t = MATH_MAD(y, -(float)qsgn, x); + ret = c ? t : (DAZ_OPT() ? BUILTIN_CANONICALIZE_F32(x) : x); +#if defined(COMPILING_REMQUO) + q7 = c ? qsgn : q7; +#endif +#endif + + ret = ax == ay ? BUILTIN_COPYSIGN_F32(0.0f, x) : ret; +#if defined(COMPILING_REMQUO) + q7 = ax == ay ? qsgn : q7; +#endif + } + + if (!FINITE_ONLY_OPT()) { + ret = y == 0.0f ? QNAN_F32 : ret; +#if defined(COMPILING_REMQUO) + q7 = y == 0.0f ? 0 : q7; +#endif + + bool c = !BUILTIN_ISNAN_F32(y) && BUILTIN_ISFINITE_F32(x); + ret = c ? ret : QNAN_F32; +#if defined(COMPILING_REMQUO) + q7 = c ? q7 : 0; +#endif + } + +#if defined(COMPILING_REMQUO) + __ocml_remquo_f32_result result = { ret, q7 }; + return result; +#else + return ret; +#endif + +} + +#if defined(COMPILING_REMQUO) +float +MATH_MANGLE(remquo)(float x, float y, __private int *q7p) { + __ocml_remquo_f32_result result = MATH_MANGLE(remquo2)(x, y); + *q7p = result.quo; + return result.rem; +} +#endif diff --git a/amd/device-libs/ocml/src/remainderH.cl b/amd/device-libs/ocml/src/remainderH.cl new file mode 100644 index 0000000000000..986c20d738d87 --- /dev/null +++ b/amd/device-libs/ocml/src/remainderH.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(remainder) + +#define COMPILING_REMAINDER +#include "remainderH_base.h" + diff --git a/amd/device-libs/ocml/src/remainderH_base.h b/amd/device-libs/ocml/src/remainderH_base.h new file mode 100644 index 0000000000000..918f37e211c44 --- /dev/null +++ b/amd/device-libs/ocml/src/remainderH_base.h @@ -0,0 +1,152 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +CONSTATTR static bool +samesign(half x, half y) +{ + return (AS_USHORT(x) & (ushort)SIGNBIT_HP16) == (AS_USHORT(y) & (ushort)SIGNBIT_HP16); +} + +#if defined(COMPILING_FMOD) +CONSTATTR half +MATH_MANGLE(fmod)(half x, half y) +#elif defined(COMPILING_REMQUO) +__ocml_remquo_f16_result +MATH_MANGLE(remquo2)(half x, half y) +#else +CONSTATTR half +MATH_MANGLE(remainder)(half x, half y) +#endif +{ + // How many bits of the quotient per iteration + const int bits = 11; + float ax = (float)BUILTIN_ABS_F16(x); + float ay = (float)BUILTIN_ABS_F16(y); + + float ret; +#if defined(COMPILING_REMQUO) + int q7; +#endif + + if (ax > ay) { + int ex, ey; + + ex = BUILTIN_FREXP_EXP_F32(ax) - 1; + ax = BUILTIN_FLDEXP_F32(BUILTIN_FREXP_MANT_F32(ax), bits); + ey = BUILTIN_FREXP_EXP_F32(ay) - 1; + ay = BUILTIN_FLDEXP_F32(BUILTIN_FREXP_MANT_F32(ay), 1); + + int nb = ex - ey; + + float ayinv = BUILTIN_AMDGPU_RCP_F32(ay); + +#if !defined(COMPILING_FMOD) + int qacc = 0; +#endif + + while (nb > bits) { + float q = BUILTIN_RINT_F32(ax * ayinv); + ax = BUILTIN_MAD_F32(-q, ay, ax); + int clt = ax < 0.0f; + float axp = ax + ay; + ax = clt ? axp : ax; +#if defined(COMPILING_REMQUO) + int iq = (int)q; + iq -= clt; + qacc = (qacc << bits) | iq; +#endif + ax = BUILTIN_FLDEXP_F32(ax, bits); + nb -= bits; + } + + ax = BUILTIN_FLDEXP_F32(ax, nb - bits + 1); + + // Final iteration + { + float q = BUILTIN_RINT_F32(ax * ayinv); + ax = BUILTIN_MAD_F32(-q, ay, ax); + int clt = ax < 0.0f; + float axp = ax + ay; + ax = clt ? axp : ax; +#if !defined(COMPILING_FMOD) + int iq = (int)q; + iq -= clt; +#if defined(COMPILING_REMQUO) + qacc = (qacc << (nb+1)) | iq; +#else + qacc = iq; +#endif +#endif + } + +#if !defined(COMPILING_FMOD) + // Adjust ax so that it is the range (-y/2, y/2] + // We need to choose the even integer when x/y is midway between two integers + int aq = (2.0f*ax > ay) | ((qacc & 0x1) & (2.0f*ax == ay)); + ax = ax - (aq ? ay : 0.0f); +#if defined(COMPILING_REMQUO) + qacc += aq; + int qneg = samesign(x, y) ? 0 : -1; + q7 = ((qacc & 0x7f) ^ qneg) - qneg; +#endif +#endif + + ax = BUILTIN_FLDEXP_F32(ax, ey); + short ir = AS_SHORT((half)ax); + ir ^= AS_SHORT(x) & (short)SIGNBIT_HP16; + ret = AS_HALF(ir); + } else { + ret = x; +#if defined(COMPILING_REMQUO) + q7 = 0; +#endif + +#if !defined(COMPILING_FMOD) + bool c = ax > 0.5f*ay; + + int qsgn = samesign(x,y) ? 1 : -1; + half t = MATH_MAD(y, -(half)qsgn, x); + ret = c ? t : ret; +#if defined(COMPILING_REMQUO) + q7 = c ? qsgn : q7; +#endif +#endif + + ret = ax == ay ? BUILTIN_COPYSIGN_F16(0.0h, x) : ret; +#if defined(COMPILING_REMQUO) + q7 = ax == ay ? qsgn : q7; +#endif + } + + if (!FINITE_ONLY_OPT()) { + ret = y == 0.0h ? QNAN_F16 : ret; +#if defined(COMPILING_REMQUO) + q7 = y == 0.0h ? 0 : q7; +#endif + + bool c = !BUILTIN_ISNAN_F16(y) && BUILTIN_ISFINITE_F16(x); + ret = c ? ret : QNAN_F16; +#if defined(COMPILING_REMQUO) + q7 = c ? q7 : 0; +#endif + } + +#if defined(COMPILING_REMQUO) + __ocml_remquo_f16_result result = { ret, q7 }; + return result; +#else + return ret; +#endif +} + +#if defined(COMPILING_REMQUO) +half MATH_MANGLE(remquo)(half x, half y, __private int *q7p) { + __ocml_remquo_f16_result result = MATH_MANGLE(remquo2)(x, y); + *q7p = result.quo; + return result.rem; +} +#endif diff --git a/amd/device-libs/ocml/src/remquoD.cl b/amd/device-libs/ocml/src/remquoD.cl new file mode 100644 index 0000000000000..fb7206c0cc03e --- /dev/null +++ b/amd/device-libs/ocml/src/remquoD.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_REMQUO +#include "remainderD_base.h" + diff --git a/amd/device-libs/ocml/src/remquoF.cl b/amd/device-libs/ocml/src/remquoF.cl new file mode 100644 index 0000000000000..96717c3e9500a --- /dev/null +++ b/amd/device-libs/ocml/src/remquoF.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_REMQUO +#include "remainderF_base.h" + diff --git a/amd/device-libs/ocml/src/remquoH.cl b/amd/device-libs/ocml/src/remquoH.cl new file mode 100644 index 0000000000000..0e5197e5fd3fb --- /dev/null +++ b/amd/device-libs/ocml/src/remquoH.cl @@ -0,0 +1,33 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +half2 +MATH_MANGLE2(remquo)(half2 x, half2 y, __private int2 *q7p) +{ + int qlo, qhi; + half2 r; + r.lo = MATH_MANGLE(remquo)(x.lo, y.lo, &qlo); + r.hi = MATH_MANGLE(remquo)(x.hi, y.hi, &qhi); + *q7p = (int2)(qlo, qhi); + return r; +} + +__ocml_remquo_2f16_result +MATH_MANGLE2(remquo2)(half2 x, half2 y) +{ + __ocml_remquo_f16_result lo = MATH_MANGLE(remquo2)(x.lo, y.lo); + __ocml_remquo_f16_result hi = MATH_MANGLE(remquo2)(x.hi, y.hi); + __ocml_remquo_2f16_result result = { (half2)(lo.rem, hi.rem), + (int2)(lo.quo, hi.quo) }; + return result; +} + +#define COMPILING_REMQUO +#include "remainderH_base.h" + diff --git a/amd/device-libs/ocml/src/rhypotD.cl b/amd/device-libs/ocml/src/rhypotD.cl new file mode 100644 index 0000000000000..90bb39569a86a --- /dev/null +++ b/amd/device-libs/ocml/src/rhypotD.cl @@ -0,0 +1,35 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(rhypot)(double x, double y) +{ + double a = BUILTIN_ABS_F64(x); + double b = BUILTIN_ABS_F64(y); + double t = BUILTIN_MAX_F64(a, b); + int e = BUILTIN_FREXP_EXP_F64(t); + a = BUILTIN_FLDEXP_F64(a, -e); + b = BUILTIN_FLDEXP_F64(b, -e); + double d2 = MATH_MAD(a, a, b*b); + double z = BUILTIN_AMDGPU_RSQRT_F64(d2); + double u = MATH_MAD(-d2*z, z, 1.0); + z = MATH_MAD(z*u, MATH_MAD(u, 0.375, 0.5), z); + double ret = BUILTIN_FLDEXP_F64(z, -e); + + if (!FINITE_ONLY_OPT()) { + ret = t == 0.0 ? PINF_F64 : ret; + + ret = BUILTIN_ISUNORDERED_F64(x, y) ? QNAN_F64 : ret; + + ret = (BUILTIN_ISINF_F64(x) | BUILTIN_ISINF_F64(y)) ? 0.0 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/rhypotF.cl b/amd/device-libs/ocml/src/rhypotF.cl new file mode 100644 index 0000000000000..9d5cf349d169a --- /dev/null +++ b/amd/device-libs/ocml/src/rhypotF.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(rhypot)(float x, float y) +{ + float a = BUILTIN_ABS_F32(x); + float b = BUILTIN_ABS_F32(y); + float t = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(a), AS_UINT(b))); + int e = BUILTIN_FREXP_EXP_F32(t); + a = BUILTIN_FLDEXP_F32(a, -e); + b = BUILTIN_FLDEXP_F32(b, -e); + float ret = BUILTIN_FLDEXP_F32(BUILTIN_AMDGPU_RSQRT_F32(MATH_MAD(a, a, b*b)), -e); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F32(x) | + BUILTIN_ISINF_F32(y)) ? + 0.0f : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/rhypotH.cl b/amd/device-libs/ocml/src/rhypotH.cl new file mode 100644 index 0000000000000..057219d248e03 --- /dev/null +++ b/amd/device-libs/ocml/src/rhypotH.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(rhypot) + +CONSTATTR half +MATH_MANGLE(rhypot)(half x, half y) +{ + float fx = (float)x; + float fy = (float)y; + + float d2 = BUILTIN_MAD_F32(fx, fx, fy*fy); + + half ret = (half)BUILTIN_AMDGPU_RSQRT_F32(d2); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F16(x) | BUILTIN_ISINF_F16(y)) ? + 0.0h : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/rintD.cl b/amd/device-libs/ocml/src/rintD.cl new file mode 100644 index 0000000000000..7c3bb107650dd --- /dev/null +++ b/amd/device-libs/ocml/src/rintD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(rint)(double x) +{ + return BUILTIN_RINT_F64(x); +} + diff --git a/amd/device-libs/ocml/src/rintF.cl b/amd/device-libs/ocml/src/rintF.cl new file mode 100644 index 0000000000000..1725493376d01 --- /dev/null +++ b/amd/device-libs/ocml/src/rintF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(rint)(float x) +{ + return BUILTIN_RINT_F32(x); +} + diff --git a/amd/device-libs/ocml/src/rintH.cl b/amd/device-libs/ocml/src/rintH.cl new file mode 100644 index 0000000000000..f2ffd3c101d6b --- /dev/null +++ b/amd/device-libs/ocml/src/rintH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(rint)(half2 x) +{ + return BUILTIN_RINT_2F16(x); +} + +CONSTATTR half +MATH_MANGLE(rint)(half x) +{ + return BUILTIN_RINT_F16(x); +} + diff --git a/amd/device-libs/ocml/src/rlen3D.cl b/amd/device-libs/ocml/src/rlen3D.cl new file mode 100644 index 0000000000000..d6be46cb5cc03 --- /dev/null +++ b/amd/device-libs/ocml/src/rlen3D.cl @@ -0,0 +1,51 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(rlen3)(double x, double y, double z) +{ + double a = BUILTIN_ABS_F64(x); + double b = BUILTIN_ABS_F64(y); + double c = BUILTIN_ABS_F64(z); + + double a1 = BUILTIN_MAX_F64(a, b); + double b1 = BUILTIN_MIN_F64(a, b); + + a = BUILTIN_MAX_F64(a1, c); + double c1 = BUILTIN_MIN_F64(a1, c); + + b = BUILTIN_MAX_F64(b1, c1); + c = BUILTIN_MIN_F64(b1, c1); + + int e = BUILTIN_FREXP_EXP_F64(a); + a = BUILTIN_FLDEXP_F64(a, -e); + b = BUILTIN_FLDEXP_F64(b, -e); + c = BUILTIN_FLDEXP_F64(c, -e); + + double d2 = MATH_MAD(a, a, MATH_MAD(b, b, c*c)); + double v = BUILTIN_AMDGPU_RSQRT_F64(d2); + double u = MATH_MAD(-d2*v, v, 1.0); + v = MATH_MAD(v*u, MATH_MAD(u, 0.375, 0.5), v); + double ret = BUILTIN_FLDEXP_F64(v, -e); + + if (!FINITE_ONLY_OPT()) { + ret = a == 0.0 ? PINF_F64 : ret; + + ret = (BUILTIN_ISNAN_F64(x) | + BUILTIN_ISNAN_F64(y) | + BUILTIN_ISNAN_F64(z)) ? QNAN_F64 : ret; + + ret = (BUILTIN_ISINF_F64(x) | + BUILTIN_ISINF_F64(y) | + BUILTIN_ISINF_F64(z)) ? 0.0 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/rlen3F.cl b/amd/device-libs/ocml/src/rlen3F.cl new file mode 100644 index 0000000000000..37ca76c13ece1 --- /dev/null +++ b/amd/device-libs/ocml/src/rlen3F.cl @@ -0,0 +1,42 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(rlen3)(float x, float y, float z) +{ + float a = BUILTIN_ABS_F32(x); + float b = BUILTIN_ABS_F32(y); + float c = BUILTIN_ABS_F32(z); + + float a1 = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(a), AS_UINT(b))); + float b1 = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(a), AS_UINT(b))); + + a = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(a1), AS_UINT(c))); + float c1 = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(a1), AS_UINT(c))); + + b = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(b1), AS_UINT(c1))); + c = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(b1), AS_UINT(c1))); + + int e = BUILTIN_FREXP_EXP_F32(a); + a = BUILTIN_FLDEXP_F32(a, -e); + b = BUILTIN_FLDEXP_F32(b, -e); + c = BUILTIN_FLDEXP_F32(c, -e); + + float ret = BUILTIN_AMDGPU_RSQRT_F32(MATH_MAD(a, a, MATH_MAD(b, b, c*c))); + ret = BUILTIN_FLDEXP_F32(ret, -e); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F32(x) | + BUILTIN_ISINF_F32(y) | + BUILTIN_ISINF_F32(z)) ? 0.0f : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/rlen3H.cl b/amd/device-libs/ocml/src/rlen3H.cl new file mode 100644 index 0000000000000..0b9074ef91acc --- /dev/null +++ b/amd/device-libs/ocml/src/rlen3H.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_MANGLE(rlen3)(half x, half y, half z) +{ + float fx = (float)x; + float fy = (float)y; + float fz = (float)z; + + float d2 = BUILTIN_MAD_F32(fx, fx, BUILTIN_MAD_F32(fy, fy, fz*fz)); + + half ret = (half)BUILTIN_AMDGPU_RSQRT_F32(d2); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F16(x) | + BUILTIN_ISINF_F16(y) | + BUILTIN_ISINF_F16(z)) ? 0.0h : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/rlen4D.cl b/amd/device-libs/ocml/src/rlen4D.cl new file mode 100644 index 0000000000000..36940042031de --- /dev/null +++ b/amd/device-libs/ocml/src/rlen4D.cl @@ -0,0 +1,61 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(rlen4)(double x, double y, double z, double w) +{ + double a = BUILTIN_ABS_F64(x); + double b = BUILTIN_ABS_F64(y); + double c = BUILTIN_ABS_F64(z); + double d = BUILTIN_ABS_F64(w); + + double a1 = BUILTIN_MAX_F64(a, b); + double b1 = BUILTIN_MIN_F64(a, b); + + double c1 = BUILTIN_MAX_F64(c, d); + double d1 = BUILTIN_MIN_F64(c, d); + + a = BUILTIN_MAX_F64(a1, c1); + double c2 = BUILTIN_MIN_F64(a1, c1); + + double b2 = BUILTIN_MAX_F64(b1, d1); + d = BUILTIN_MIN_F64(b1, d1); + + b = BUILTIN_MAX_F64(b2, c2); + c = BUILTIN_MIN_F64(b2, c2); + + int e = BUILTIN_FREXP_EXP_F64(a); + a = BUILTIN_FLDEXP_F64(a, -e); + b = BUILTIN_FLDEXP_F64(b, -e); + c = BUILTIN_FLDEXP_F64(c, -e); + d = BUILTIN_FLDEXP_F64(d, -e); + + double l2 = MATH_MAD(a, a, MATH_MAD(b, b, MATH_MAD(c, c, d*d))); + double v = BUILTIN_AMDGPU_RSQRT_F64(l2); + double u = MATH_MAD(-l2*v, v, 1.0); + v = MATH_MAD(v*u, MATH_MAD(u, 0.375, 0.5), v); + double ret = BUILTIN_FLDEXP_F64(v, -e); + + if (!FINITE_ONLY_OPT()) { + ret = a == 0.0 ? PINF_F64 : ret; + + ret = (BUILTIN_ISNAN_F64(x) | + BUILTIN_ISNAN_F64(y) | + BUILTIN_ISNAN_F64(z) | + BUILTIN_ISNAN_F64(w)) ? QNAN_F64 : ret; + + ret = (BUILTIN_ISINF_F64(x) | + BUILTIN_ISINF_F64(y) | + BUILTIN_ISINF_F64(z) | + BUILTIN_ISINF_F64(w)) ? 0.0 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/rlen4F.cl b/amd/device-libs/ocml/src/rlen4F.cl new file mode 100644 index 0000000000000..0a2cd99521e3d --- /dev/null +++ b/amd/device-libs/ocml/src/rlen4F.cl @@ -0,0 +1,50 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(rlen4)(float x, float y, float z, float w) +{ + float a = BUILTIN_ABS_F32(x); + float b = BUILTIN_ABS_F32(y); + float c = BUILTIN_ABS_F32(z); + float d = BUILTIN_ABS_F32(w); + + float a1 = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(a), AS_UINT(b))); + float b1 = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(a), AS_UINT(b))); + + float c1 = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(c), AS_UINT(d))); + float d1 = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(c), AS_UINT(d))); + + a = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(a1), AS_UINT(c1))); + float c2 = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(a1), AS_UINT(c1))); + + float b2 = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(b1), AS_UINT(d1))); + d = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(b1), AS_UINT(d1))); + + b = AS_FLOAT(BUILTIN_MAX_U32(AS_UINT(b2), AS_UINT(c2))); + c = AS_FLOAT(BUILTIN_MIN_U32(AS_UINT(b2), AS_UINT(c2))); + + int e = BUILTIN_FREXP_EXP_F32(a); + a = BUILTIN_FLDEXP_F32(a, -e); + b = BUILTIN_FLDEXP_F32(b, -e); + c = BUILTIN_FLDEXP_F32(c, -e); + d = BUILTIN_FLDEXP_F32(d, -e); + + float ret = BUILTIN_FLDEXP_F32(BUILTIN_AMDGPU_RSQRT_F32(MATH_MAD(a, a, MATH_MAD(b, b, MATH_MAD(c, c, d*d)))), -e); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F32(x) | + BUILTIN_ISINF_F32(y) | + BUILTIN_ISINF_F32(z) | + BUILTIN_ISINF_F32(w)) ? 0.0f : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/rlen4H.cl b/amd/device-libs/ocml/src/rlen4H.cl new file mode 100644 index 0000000000000..ebf08811b32d3 --- /dev/null +++ b/amd/device-libs/ocml/src/rlen4H.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_MANGLE(rlen4)(half x, half y, half z, half w) +{ + float fx = (float)x; + float fy = (float)y; + float fz = (float)z; + float fw = (float)w; + + float d2 = BUILTIN_MAD_F32(fx, fx, BUILTIN_MAD_F32(fy, fy, BUILTIN_MAD_F32(fz, fz, fw*fw))); + + half ret = (half)BUILTIN_AMDGPU_RSQRT_F32(d2); + + if (!FINITE_ONLY_OPT()) { + ret = (BUILTIN_ISINF_F16(x) | + BUILTIN_ISINF_F16(y) | + BUILTIN_ISINF_F16(z) | + BUILTIN_ISINF_F16(w)) ? 0.0h : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/rootnD.cl b/amd/device-libs/ocml/src/rootnD.cl new file mode 100644 index 0000000000000..ecfea931aa1e4 --- /dev/null +++ b/amd/device-libs/ocml/src/rootnD.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_ROOTN +#include "powD_base.h" + diff --git a/amd/device-libs/ocml/src/rootnF.cl b/amd/device-libs/ocml/src/rootnF.cl new file mode 100644 index 0000000000000..77f87f1d3ef39 --- /dev/null +++ b/amd/device-libs/ocml/src/rootnF.cl @@ -0,0 +1,10 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define COMPILING_ROOTN +#include "powF_base.h" + diff --git a/amd/device-libs/ocml/src/rootnH.cl b/amd/device-libs/ocml/src/rootnH.cl new file mode 100644 index 0000000000000..e55405e75e161 --- /dev/null +++ b/amd/device-libs/ocml/src/rootnH.cl @@ -0,0 +1,18 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(rootn)(half2 x, int2 ny) +{ + return (half2)(MATH_MANGLE(rootn)(x.lo, ny.lo), MATH_MANGLE(rootn)(x.hi, ny.hi)); +} + +#define COMPILING_ROOTN +#include "powH_base.h" + diff --git a/amd/device-libs/ocml/src/roundD.cl b/amd/device-libs/ocml/src/roundD.cl new file mode 100644 index 0000000000000..63c89ca2b0322 --- /dev/null +++ b/amd/device-libs/ocml/src/roundD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(round)(double x) +{ + return BUILTIN_ROUND_F64(x); +} + diff --git a/amd/device-libs/ocml/src/roundF.cl b/amd/device-libs/ocml/src/roundF.cl new file mode 100644 index 0000000000000..5543b4f4f22c5 --- /dev/null +++ b/amd/device-libs/ocml/src/roundF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(round)(float x) +{ + return BUILTIN_ROUND_F32(x); +} + diff --git a/amd/device-libs/ocml/src/roundH.cl b/amd/device-libs/ocml/src/roundH.cl new file mode 100644 index 0000000000000..6f616560d9a45 --- /dev/null +++ b/amd/device-libs/ocml/src/roundH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(round)(half2 x) +{ + return BUILTIN_ROUND_2F16(x); +} + +CONSTATTR half +MATH_MANGLE(round)(half x) +{ + return BUILTIN_ROUND_F16(x); +} + diff --git a/amd/device-libs/ocml/src/rsqrtD.cl b/amd/device-libs/ocml/src/rsqrtD.cl new file mode 100644 index 0000000000000..0430645e542e4 --- /dev/null +++ b/amd/device-libs/ocml/src/rsqrtD.cl @@ -0,0 +1,18 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(rsqrt)(double x) +{ + double y0 = BUILTIN_AMDGPU_RSQRT_F64(x); + double e = MATH_MAD(-x*y0, y0, 1.0); + double y1 = MATH_MAD(y0*e, MATH_MAD(e, 0.375, 0.5), y0); + return BUILTIN_CLASS_F64(y0, CLASS_PSUB|CLASS_PNOR) ? y1 : y0; +} + diff --git a/amd/device-libs/ocml/src/rsqrtF.cl b/amd/device-libs/ocml/src/rsqrtF.cl new file mode 100644 index 0000000000000..437498fcb3eb4 --- /dev/null +++ b/amd/device-libs/ocml/src/rsqrtF.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(rsqrt)(float x) +{ + if (DAZ_OPT()) { + return BUILTIN_AMDGPU_RSQRT_F32(x); + } else { + bool need_scale = x < 0x1p-126f; + float scaled_input = need_scale ? 0x1.0p+24f * x : x; + float result = BUILTIN_AMDGPU_RSQRT_F32(scaled_input); + return need_scale ? result * 0x1.0p+12f : result; + } +} + diff --git a/amd/device-libs/ocml/src/rsqrtH.cl b/amd/device-libs/ocml/src/rsqrtH.cl new file mode 100644 index 0000000000000..ab42880e86328 --- /dev/null +++ b/amd/device-libs/ocml/src/rsqrtH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(rsqrt) + +CONSTATTR half +MATH_MANGLE(rsqrt)(half x) +{ + return BUILTIN_RSQRT_F16(x); +} + diff --git a/amd/device-libs/ocml/src/scalbD.cl b/amd/device-libs/ocml/src/scalbD.cl new file mode 100644 index 0000000000000..9fc0b3266a6d5 --- /dev/null +++ b/amd/device-libs/ocml/src/scalbD.cl @@ -0,0 +1,24 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(scalb)(double x, double y) +{ + double t = BUILTIN_MIN_F64(BUILTIN_MAX_F64(y, -0x1.0p+20), 0x1.0p+20); + double ret = MATH_MANGLE(ldexp)(x, (int)BUILTIN_RINT_F64(t)); + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_ISUNORDERED_F64(x, y) ? QNAN_F64 : ret; + ret = ((x == 0.0) & (y == PINF_F64)) ? QNAN_F64 : ret; + ret = (BUILTIN_ISINF_F64(x) & (y == NINF_F64)) ? QNAN_F64 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/scalbF.cl b/amd/device-libs/ocml/src/scalbF.cl new file mode 100644 index 0000000000000..dbdbebe06b27d --- /dev/null +++ b/amd/device-libs/ocml/src/scalbF.cl @@ -0,0 +1,24 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(scalb)(float x, float y) +{ + float t = BUILTIN_CLAMP_F32(y, -0x1.0p+20f, 0x1.0p+20f); + float ret = MATH_MANGLE(ldexp)(x, (int)BUILTIN_RINT_F32(t)); + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_ISUNORDERED_F32(x, y) ? QNAN_F32 : ret; + ret = (BUILTIN_ISINF_F32(x) & (y == PINF_F32)) ? QNAN_F32 : ret; + ret = (BUILTIN_ISINF_F32(x) & (y == NINF_F32)) ? QNAN_F32 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/scalbH.cl b/amd/device-libs/ocml/src/scalbH.cl new file mode 100644 index 0000000000000..e3cd0d02216f2 --- /dev/null +++ b/amd/device-libs/ocml/src/scalbH.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR BGEN(scalb) + +CONSTATTR half +MATH_MANGLE(scalb)(half x, half y) +{ + half t = BUILTIN_MIN_F16(BUILTIN_MAX_F16(y, -0x1.0p+6h), 0x1.0p+6h); + half ret = MATH_MANGLE(ldexp)(x, (int)BUILTIN_RINT_F16(t)); + + if (!FINITE_ONLY_OPT()) { + ret = BUILTIN_ISUNORDERED_F16(x, y) ? QNAN_F16 : ret; + ret = ((x == 0.0h) & (y == PINF_F16)) ? QNAN_F16 : ret; + ret = (BUILTIN_ISINF_F16(x) & (y == NINF_F16)) ? QNAN_F16 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/scalbnD.cl b/amd/device-libs/ocml/src/scalbnD.cl new file mode 100644 index 0000000000000..07ecd54108382 --- /dev/null +++ b/amd/device-libs/ocml/src/scalbnD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(scalbn)(double x, int n) +{ + return MATH_MANGLE(ldexp)(x, n); +} + diff --git a/amd/device-libs/ocml/src/scalbnF.cl b/amd/device-libs/ocml/src/scalbnF.cl new file mode 100644 index 0000000000000..b0adcc1a38f09 --- /dev/null +++ b/amd/device-libs/ocml/src/scalbnF.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(scalbn)(float x, int n) +{ + return MATH_MANGLE(ldexp)(x, n); +} + diff --git a/amd/device-libs/ocml/src/scalbnH.cl b/amd/device-libs/ocml/src/scalbnH.cl new file mode 100644 index 0000000000000..f9be702ea3100 --- /dev/null +++ b/amd/device-libs/ocml/src/scalbnH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(scalbn)(half2 x, int2 n) +{ + return (half2)(MATH_MANGLE(ldexp)(x.lo, n.lo), MATH_MANGLE(ldexp)(x.hi, n.hi)); +} + +CONSTATTR half +MATH_MANGLE(scalbn)(half x, int n) +{ + return MATH_MANGLE(ldexp)(x, n); +} + diff --git a/amd/device-libs/ocml/src/signbitD.cl b/amd/device-libs/ocml/src/signbitD.cl new file mode 100644 index 0000000000000..98681e5d5656e --- /dev/null +++ b/amd/device-libs/ocml/src/signbitD.cl @@ -0,0 +1,15 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR int +MATH_MANGLE(signbit)(double x) +{ + return AS_INT2(x).hi < 0; +} + diff --git a/amd/device-libs/ocml/src/signbitF.cl b/amd/device-libs/ocml/src/signbitF.cl new file mode 100644 index 0000000000000..e944a72bfaff4 --- /dev/null +++ b/amd/device-libs/ocml/src/signbitF.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR int +MATH_MANGLE(signbit)(float x) +{ + return AS_INT(x) < 0; +} diff --git a/amd/device-libs/ocml/src/signbitH.cl b/amd/device-libs/ocml/src/signbitH.cl new file mode 100644 index 0000000000000..b5d991705700f --- /dev/null +++ b/amd/device-libs/ocml/src/signbitH.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR short2 +MATH_MANGLE2(signbit)(half2 x) +{ + return (short2) + (AS_SHORT(x.lo) < 0 ? (short)-1 : (short)0, + AS_SHORT(x.hi) < 0 ? (short)-1 : (short)0); +} + +CONSTATTR int +MATH_MANGLE(signbit)(half x) +{ + return AS_SHORT(x) < 0; +} diff --git a/amd/device-libs/ocml/src/sinD.cl b/amd/device-libs/ocml/src/sinD.cl new file mode 100644 index 0000000000000..1c54fb2ac2c18 --- /dev/null +++ b/amd/device-libs/ocml/src/sinD.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +CONSTATTR double +MATH_MANGLE(sin)(double x) +{ + double ax = BUILTIN_ABS_F64(x); + struct redret r = MATH_PRIVATE(trigred)(ax); + struct scret sc = MATH_PRIVATE(sincosred2)(r.hi, r.lo); + + int2 s = AS_INT2((r.i & 1) == 0 ? sc.s : sc.c); + s.hi ^= (r.i > 1 ? 0x80000000 : 0) ^ (AS_INT2(x).hi & 0x80000000); + + if (!FINITE_ONLY_OPT()) { + s = BUILTIN_ISFINITE_F64(ax) ? s : AS_INT2(QNANBITPATT_DP64); + } + + return AS_DOUBLE(s); +} + diff --git a/amd/device-libs/ocml/src/sinF.cl b/amd/device-libs/ocml/src/sinF.cl new file mode 100644 index 0000000000000..d7ddef47af15d --- /dev/null +++ b/amd/device-libs/ocml/src/sinF.cl @@ -0,0 +1,34 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +float +MATH_MANGLE(sin)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + + struct redret r = MATH_PRIVATE(trigred)(ax); + +#if defined EXTRA_PRECISION + struct scret sc = MATH_PRIVATE(sincosred2)(r.hi, r.lo); +#else + struct scret sc = MATH_PRIVATE(sincosred)(r.hi); +#endif + + float s = (r.i & 1) != 0 ? sc.c : sc.s; + s = AS_FLOAT(AS_INT(s) ^ (r.i > 1 ? 0x80000000 : 0) ^ + (AS_INT(x) ^ AS_INT(ax))); + + if (!FINITE_ONLY_OPT()) { + s = BUILTIN_ISFINITE_F32(ax) ? s : QNAN_F32; + } + + return s; +} + diff --git a/amd/device-libs/ocml/src/sinH.cl b/amd/device-libs/ocml/src/sinH.cl new file mode 100644 index 0000000000000..d4d2a40bc8e24 --- /dev/null +++ b/amd/device-libs/ocml/src/sinH.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigredH.h" + +UGEN(sin) + +half +MATH_MANGLE(sin)(half x) +{ + half ax = BUILTIN_ABS_F16(x); + struct redret r = MATH_PRIVATE(trigred)(ax); + struct scret sc = MATH_PRIVATE(sincosred)(r.hi); + + short s = AS_SHORT((r.i & (short)1) == (short)0 ? sc.s : sc.c); + s ^= (r.i > (short)1 ? (short)0x8000 : (short)0) ^ (AS_SHORT(x) & (short)0x8000); + + if (!FINITE_ONLY_OPT()) { + s = BUILTIN_ISFINITE_F16(ax) ? s : (short)QNANBITPATT_HP16; + } + + return AS_HALF(s); +} + diff --git a/amd/device-libs/ocml/src/sinbD.cl b/amd/device-libs/ocml/src/sinbD.cl new file mode 100644 index 0000000000000..c98a8fa2abac9 --- /dev/null +++ b/amd/device-libs/ocml/src/sinbD.cl @@ -0,0 +1,55 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +#define FSUM2(A, B, H, L) \ + do { \ + double __s = A + B; \ + double __t = B - (__s - A); \ + H = __s; \ + L = __t; \ + } while (0) + +#define FDIF2(A, B, H, L) \ + do { \ + double __d = A - B; \ + double __e = (A - __d) - B; \ + H = __d; \ + L = __e; \ + } while (0) + +double +MATH_PRIVATE(sinb)(double x, int n, double p) +{ + struct redret r = MATH_PRIVATE(trigred)(x); + bool b = r.hi < p; + r.i = (r.i - b - n) & 3; + + // This is a properly signed extra precise pi/4 + double ph = AS_DOUBLE((uint2)(0x54442d18, 0xbfe921fb ^ (b ? 0x80000000 : 0))); + double pl = AS_DOUBLE((uint2)(0x33145c07, 0xbc81a626 ^ (b ? 0x80000000 : 0))); + + double sh, sl; + + FDIF2(ph, p, ph, sl); + pl += sl; + FSUM2(ph, pl, ph, pl); + + FSUM2(ph, r.hi, sh, sl); + sl += pl + r.lo; + FSUM2(sh, sl, sh, sl); + + struct scret sc = MATH_PRIVATE(sincosred2)(sh, sl); + + int2 s = AS_INT2((r.i & 1) == 0 ? sc.s : sc.c); + s.hi ^= r.i > 1 ? 0x80000000 : 0; + + return AS_DOUBLE(s); +} + diff --git a/amd/device-libs/ocml/src/sinbF.cl b/amd/device-libs/ocml/src/sinbF.cl new file mode 100644 index 0000000000000..cdc139be8a11b --- /dev/null +++ b/amd/device-libs/ocml/src/sinbF.cl @@ -0,0 +1,59 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +#define FSUM2(A, B, H, L) \ + do { \ + float __s = A + B; \ + float __t = B - (__s - A); \ + H = __s; \ + L = __t; \ + } while (0) + +#define FDIF2(A, B, H, L) \ + do { \ + float __d = A - B; \ + float __e = (A - __d) - B; \ + H = __d; \ + L = __e; \ + } while (0) + +float +MATH_PRIVATE(sinb)(float x, int n, float p) +{ + struct redret r = MATH_PRIVATE(trigred)(x); + bool b = r.hi < p; + r.i = (r.i - b - n) & 3; + +#if defined EXTRA_PRECISION + float ph = AS_FLOAT(0xbf490fdb ^ (b ? 0x80000000 : 0)); + float pl = AS_FLOAT(0x32bbbd2e ^ (b ? 0x80000000 : 0)); + + float sh, sl; + + FDIF2(ph, p, ph, sl); + pl += sl; + FSUM2(ph, pl, ph, pl); + + FSUM2(ph, r.hi, sh, sl); + sl += pl + r.lo; + FSUM2(sh, sl, sh, sl); + + struct scret sc = MATH_PRIVATE(sincosred2)(sh, sl); +#else + r.hi = r.hi - p + AS_FLOAT(0xbf490fdb ^ (b ? 0x80000000 : 0)); + + struct scret sc = MATH_PRIVATE(sincosred)(r.hi); +#endif + + float s = (r.i & 1) != 0 ? sc.c : sc.s; + s = AS_FLOAT(AS_INT(s) ^ (r.i > 1 ? 0x80000000 : 0)); + return s; +} + diff --git a/amd/device-libs/ocml/src/sincosD.cl b/amd/device-libs/ocml/src/sincosD.cl new file mode 100644 index 0000000000000..be03e97711c8b --- /dev/null +++ b/amd/device-libs/ocml/src/sincosD.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +double +MATH_MANGLE(sincos)(double x, __private double * cp) +{ + double ax = BUILTIN_ABS_F64(x); + struct redret r = MATH_PRIVATE(trigred)(ax); + struct scret sc = MATH_PRIVATE(sincosred2)(r.hi, r.lo); + + int flip = r.i > 1 ? (int)0x80000000 : 0; + bool odd = (r.i & 1) != 0; + + int2 s = AS_INT2(odd ? sc.c : sc.s); + s.hi ^= flip ^ (AS_INT2(x).hi &(int)0x80000000); + sc.s = -sc.s; + int2 c = AS_INT2(odd ? sc.s : sc.c); + c.hi ^= flip; + + if (!FINITE_ONLY_OPT()) { + bool finite = BUILTIN_ISFINITE_F64(x); + s = finite ? s : AS_INT2(QNANBITPATT_DP64); + c = finite ? c : AS_INT2(QNANBITPATT_DP64); + } + + *cp = AS_DOUBLE(c); + return AS_DOUBLE(s); +} + diff --git a/amd/device-libs/ocml/src/sincosF.cl b/amd/device-libs/ocml/src/sincosF.cl new file mode 100644 index 0000000000000..8971061883f6d --- /dev/null +++ b/amd/device-libs/ocml/src/sincosF.cl @@ -0,0 +1,41 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +float +MATH_MANGLE(sincos)(float x, __private float *cp) +{ + float ax = BUILTIN_ABS_F32(x); + + struct redret r = MATH_PRIVATE(trigred)(ax); + +#if defined EXTRA_PRECISION + struct scret sc = MATH_PRIVATE(sincosred2)(r.hi, r.lo); +#else + struct scret sc = MATH_PRIVATE(sincosred)(r.hi); +#endif + + int flip = r.i > 1 ? 0x80000000 : 0; + bool odd = (r.i & 1) != 0; + float s = odd ? sc.c : sc.s; + s = AS_FLOAT(AS_INT(s) ^ flip ^ (AS_INT(ax) ^ AS_INT(x))); + sc.s = -sc.s; + float c = odd ? sc.s : sc.c; + c = AS_FLOAT(AS_INT(c) ^ flip); + + if (!FINITE_ONLY_OPT()) { + bool finite = BUILTIN_ISFINITE_F32(ax); + c = finite ? c : QNAN_F32; + s = finite ? s : QNAN_F32; + } + + *cp = c; + return s; +} + diff --git a/amd/device-libs/ocml/src/sincosH.cl b/amd/device-libs/ocml/src/sincosH.cl new file mode 100644 index 0000000000000..5fd693e6c8dea --- /dev/null +++ b/amd/device-libs/ocml/src/sincosH.cl @@ -0,0 +1,46 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigredH.h" + +half2 +MATH_MANGLE2(sincos)(half2 x, __private half2 *cp) +{ + half2 s; + half clo, chi; + s.lo = MATH_MANGLE(sincos)(x.lo, &clo); + s.hi = MATH_MANGLE(sincos)(x.hi, &chi); + *cp = (half2)(clo, chi); + return s; +} + +CONSTATTR half +MATH_MANGLE(sincos)(half x, __private half *cp) +{ + half ax = BUILTIN_ABS_F16(x); + struct redret r = MATH_PRIVATE(trigred)(ax); + struct scret sc = MATH_PRIVATE(sincosred)(r.hi); + + short flip = r.i > (short)1 ? (short)0x8000 : (short)0; + bool odd = (r.i & (short)1) != (short)0; + short s = AS_SHORT(odd ? sc.c : sc.s); + s ^= flip ^ (AS_SHORT(x) & (short)0x8000); + sc.s = -sc.s; + short c = AS_SHORT(odd ? sc.s : sc.c); + c ^= flip; + + if (!FINITE_ONLY_OPT()) { + bool finite = BUILTIN_ISFINITE_F16(ax); + c = finite ? c : (short)QNANBITPATT_HP16; + s = finite ? s : (short)QNANBITPATT_HP16; + } + + *cp = AS_HALF(c); + return AS_HALF(s); +} + diff --git a/amd/device-libs/ocml/src/sincospiD.cl b/amd/device-libs/ocml/src/sincospiD.cl new file mode 100644 index 0000000000000..4bb2db0ab272b --- /dev/null +++ b/amd/device-libs/ocml/src/sincospiD.cl @@ -0,0 +1,35 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigpiredD.h" + +double +MATH_MANGLE(sincospi)(double x, __private double * cp) +{ + struct redret r = MATH_PRIVATE(trigpired)(BUILTIN_ABS_F64(x)); + struct scret sc = MATH_PRIVATE(sincospired)(r.hi); + + int flip = r.i > 1 ? (int)0x80000000 : 0; + bool odd = (r.i & 1) != 0; + + int2 s = AS_INT2(odd ? sc.c : sc.s); + s.hi ^= flip ^ (AS_INT2(x).hi & 0x80000000); + sc.s = -sc.s; + int2 c = AS_INT2(odd ? sc.s : sc.c); + c.hi ^= flip; + + if (!FINITE_ONLY_OPT()) { + bool finite = BUILTIN_ISFINITE_F64(x); + s = finite ? s : AS_INT2(QNANBITPATT_DP64); + c = finite ? c : AS_INT2(QNANBITPATT_DP64); + } + + *cp = AS_DOUBLE(c); + return AS_DOUBLE(s); +} + diff --git a/amd/device-libs/ocml/src/sincospiF.cl b/amd/device-libs/ocml/src/sincospiF.cl new file mode 100644 index 0000000000000..9be5c85ad76f2 --- /dev/null +++ b/amd/device-libs/ocml/src/sincospiF.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigpiredF.h" + +float +MATH_MANGLE(sincospi)(float x, __private float *cp) +{ + float ax = BUILTIN_ABS_F32(x); + + struct redret r = MATH_PRIVATE(trigpired)(ax); + struct scret sc = MATH_PRIVATE(sincospired)(r.hi); + + int flip = r.i > 1 ? 0x80000000 : 0; + bool odd = (r.i & 1) != 0; + float s = odd ? sc.c : sc.s; + s = AS_FLOAT(AS_INT(s) ^ flip ^ (AS_INT(ax) ^ AS_INT(x))); + sc.s = -sc.s; + float c = odd ? sc.s : sc.c; + c = AS_FLOAT(AS_INT(c) ^ flip); + + if (!FINITE_ONLY_OPT()) { + bool finite = BUILTIN_ISFINITE_F32(ax); + c = finite ? c : QNAN_F32; + s = finite ? s : QNAN_F32; + } + + *cp = c; + return s; +} + diff --git a/amd/device-libs/ocml/src/sincospiH.cl b/amd/device-libs/ocml/src/sincospiH.cl new file mode 100644 index 0000000000000..8fa211a297209 --- /dev/null +++ b/amd/device-libs/ocml/src/sincospiH.cl @@ -0,0 +1,46 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigpiredH.h" + +half2 +MATH_MANGLE2(sincospi)(half2 x, __private half2 *cp) +{ + half2 s; + half clo, chi; + + s.lo = MATH_MANGLE(sincospi)(x.lo, &clo); + s.hi = MATH_MANGLE(sincospi)(x.hi, &chi); + *cp = (half2)(clo, chi); + return s; +} + +half +MATH_MANGLE(sincospi)(half x, __private half *cp) +{ + struct redret r = MATH_PRIVATE(trigpired)(BUILTIN_ABS_F16(x)); + struct scret sc = MATH_PRIVATE(sincospired)(r.hi); + + short flip = r.i > (short)1 ? (short)0x8000 : (short)0; + bool odd = (r.i & (short)1) != (short)0; + short s = AS_SHORT(odd ? sc.c : sc.s); + s ^= flip ^ (AS_SHORT(x) & (short)0x8000); + sc.s = -sc.s; + short c = AS_SHORT(odd ? sc.s : sc.c); + c ^= flip; + + if (!FINITE_ONLY_OPT()) { + bool finite = BUILTIN_ISFINITE_F16(x); + c = finite ? c : (short)QNANBITPATT_HP16; + s = finite ? s : (short)QNANBITPATT_HP16; + } + + *cp = AS_HALF(c); + return AS_HALF(s); +} + diff --git a/amd/device-libs/ocml/src/sincospiredD.cl b/amd/device-libs/ocml/src/sincospiredD.cl new file mode 100644 index 0000000000000..aae84504861e8 --- /dev/null +++ b/amd/device-libs/ocml/src/sincospiredD.cl @@ -0,0 +1,34 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigpiredD.h" + +CONSTATTR struct scret +MATH_PRIVATE(sincospired)(double x) +{ + double t = x * x; + + double sx = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, + 0x1.e357ef99eb0bbp-12, -0x1.e2fe76fdffd2bp-8), 0x1.50782d5f14825p-4), -0x1.32d2ccdfe9424p-1), + 0x1.466bc67754fffp+1), -0x1.4abbce625be09p+2); + sx = x * t * sx; + sx = MATH_MAD(x, 0x1.921fb54442d18p+1, sx); + + double cx = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + -0x1.b167302e21c33p-14, 0x1.f9c89ca1d4f33p-10), -0x1.a6d1e7294bff9p-6), 0x1.e1f5067b90b37p-3), + -0x1.55d3c7e3c325bp+0), 0x1.03c1f081b5a67p+2), -0x1.3bd3cc9be45dep+2); + cx = MATH_MAD(t, cx, 1.0); + + struct scret ret; + ret.c = cx; + ret.s = sx; + return ret; +} + diff --git a/amd/device-libs/ocml/src/sincospiredF.cl b/amd/device-libs/ocml/src/sincospiredF.cl new file mode 100644 index 0000000000000..ac164a1772bb3 --- /dev/null +++ b/amd/device-libs/ocml/src/sincospiredF.cl @@ -0,0 +1,32 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +CONSTATTR struct scret +MATH_PRIVATE(sincospired)(float x) +{ + + float t = x * x; + + float sx = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.eb5482p-3f, -0x1.3e497cp-1f), 0x1.468e6cp+1f), -0x1.4abc1cp+2f); + sx = x * t * sx; + sx = MATH_MAD(x, 0x1.921fb6p+1f, sx); + + float cx = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.97ca88p-5f, 0x1.c85d3ap-3f), -0x1.55a3b4p+0f), 0x1.03c1a6p+2f), + -0x1.3bd3ccp+2f); + cx = MATH_MAD(t, cx, 1.0f); + + struct scret ret; + ret.c = cx; + ret.s = sx; + return ret; +} + diff --git a/amd/device-libs/ocml/src/sincospiredH.cl b/amd/device-libs/ocml/src/sincospiredH.cl new file mode 100644 index 0000000000000..33a13ab00d88c --- /dev/null +++ b/amd/device-libs/ocml/src/sincospiredH.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigpiredH.h" + +CONSTATTR struct scret +MATH_PRIVATE(sincospired)(half x) +{ + half t = x * x; + + half sx = MATH_MAD(t, 0x1.b84p+0h, -0x1.46cp+2h); + sx = x * t * sx; + sx = MATH_MAD(x, 0x1.92p+1h, sx); + + half cx = MATH_MAD(t, 0x1.fbp+1h, -0x1.3bcp+2h); + cx = MATH_MAD(t, cx, 1.0h); + + struct scret ret; + ret.c = cx; + ret.s = sx; + return ret; +} + diff --git a/amd/device-libs/ocml/src/sincosred2D.cl b/amd/device-libs/ocml/src/sincosred2D.cl new file mode 100644 index 0000000000000..3d8c487dbd042 --- /dev/null +++ b/amd/device-libs/ocml/src/sincosred2D.cl @@ -0,0 +1,44 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +CONSTATTR struct scret +MATH_PRIVATE(sincosred2)(double x, double y) +{ + const double S0 = -0x1.5555555555555p-3; + const double S1 = 0x1.1111111110bb3p-7; + const double S2 = -0x1.a01a019e83e5cp-13; + const double S3 = 0x1.71de3796cde01p-19; + const double S4 = -0x1.ae600b42fdfa7p-26; + const double S5 = 0x1.5e0b2f9a43bb8p-33; + + const double C0 = 0x1.5555555555555p-5; + const double C1 = -0x1.6c16c16c16967p-10; + const double C2 = 0x1.a01a019f4ec90p-16; + const double C3 = -0x1.27e4fa17f65f6p-22; + const double C4 = 0x1.1eeb69037ab78p-29; + const double C5 = -0x1.907db46cc5e42p-37; + + double x2 = x*x; + double x3 = x * x2; + double r = 0.5 * x2; + double t = 1.0 - r; + double u = 1.0 - t; + double v = u - r; + + double cxy = t + MATH_MAD(x2*x2, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, C5, C4), C3), C2), C1), C0), MATH_MAD(x, -y, v)); + double sxy = MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, S5, S4), S3), S2), S1); + sxy = x - MATH_MAD(-x3, S0, MATH_MAD(x2, MATH_MAD(-x3, sxy, 0.5*y), -y)); + + struct scret ret; + ret.c = cxy; + ret.s = sxy; + return ret; +} + diff --git a/amd/device-libs/ocml/src/sincosred2F.cl b/amd/device-libs/ocml/src/sincosred2F.cl new file mode 100644 index 0000000000000..16cd8fdeb1526 --- /dev/null +++ b/amd/device-libs/ocml/src/sincosred2F.cl @@ -0,0 +1,41 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +CONSTATTR struct scret +MATH_PRIVATE(sincosred2)(float x, float y) +{ + const float c0 = 0x1.555556p-5f; + const float c1 = -0x1.6c16b2p-10f; + const float c2 = 0x1.a00e98p-16f; + const float c3 = -0x1.23c5e0p-22f; + + const float s0 = -0x1.555556p-3f; + const float s1 = 0x1.11110ep-7f; + const float s2 = -0x1.a0139ep-13f; + const float s3 = 0x1.6dbc3ap-19f; + + float x2 = x*x; + float x3 = x * x2; + float r = 0.5f * x2; + float t = 1.0f - r; + float u = 1.0f - t; + float v = u - r; + + float cxy = t + MATH_MAD(x2*x2, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, c3, c2), c1), c0), MATH_MAD(x, -y, v)); + + float sxy = MATH_MAD(x2, MATH_MAD(x2, s3, s2), s1); + sxy = x - MATH_MAD(-x3, s0, MATH_MAD(x2, MATH_MAD(-x3, sxy, 0.5f*y), -y)); + + struct scret ret; + ret.c = cxy; + ret.s = sxy; + return ret; +} + diff --git a/amd/device-libs/ocml/src/sincosredD.cl b/amd/device-libs/ocml/src/sincosredD.cl new file mode 100644 index 0000000000000..4418d62391197 --- /dev/null +++ b/amd/device-libs/ocml/src/sincosredD.cl @@ -0,0 +1,42 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +CONSTATTR struct scret +MATH_PRIVATE(sincosred)(double x) +{ + const double S0 = -0x1.5555555555555p-3; + const double S1 = 0x1.1111111110bb3p-7; + const double S2 = -0x1.a01a019e83e5cp-13; + const double S3 = 0x1.71de3796cde01p-19; + const double S4 = -0x1.ae600b42fdfa7p-26; + const double S5 = 0x1.5e0b2f9a43bb8p-33; + + const double C0 = 0x1.5555555555555p-5; + const double C1 = -0x1.6c16c16c16967p-10; + const double C2 = 0x1.a01a019f4ec90p-16; + const double C3 = -0x1.27e4fa17f65f6p-22; + const double C4 = 0x1.1eeb69037ab78p-29; + const double C5 = -0x1.907db46cc5e42p-37; + + double x2 = x*x; + double r = 0.5 * x2; + double t = 1.0 - r; + double u = 1.0 - t; + double v = u - r; + + double cx = t + MATH_MAD(x2*x2, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, C5, C4), C3), C2), C1), C0), v); + double sx = MATH_MAD(x2*x, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, MATH_MAD(x2, S5, S4), S3), S2), S1), S0), x); + + struct scret ret; + ret.c = cx; + ret.s = sx; + return ret; +} + diff --git a/amd/device-libs/ocml/src/sincosredF.cl b/amd/device-libs/ocml/src/sincosredF.cl new file mode 100644 index 0000000000000..9f28c062579db --- /dev/null +++ b/amd/device-libs/ocml/src/sincosredF.cl @@ -0,0 +1,25 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +CONSTATTR struct scret +MATH_PRIVATE(sincosred)(float x) +{ + float t = x * x; + + float s = MATH_MAD(x, t*MATH_MAD(t, MATH_MAD(t, -0x1.983304p-13f, 0x1.110388p-7f), -0x1.55553ap-3f), x); + float c = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + 0x1.aea668p-16f, -0x1.6c9e76p-10f), 0x1.5557eep-5f), -0x1.000008p-1f), 1.0f); + + struct scret ret; + ret.c = c; + ret.s = s; + return ret; +} + diff --git a/amd/device-libs/ocml/src/sincosredH.cl b/amd/device-libs/ocml/src/sincosredH.cl new file mode 100644 index 0000000000000..0dd4b17d3cf3e --- /dev/null +++ b/amd/device-libs/ocml/src/sincosredH.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigredH.h" + +CONSTATTR struct scret +MATH_PRIVATE(sincosred)(half x) +{ + half t = x * x; + half s = MATH_MAD(x, t*MATH_MAD(t, 0x1.0bp-7h, -0x1.554p-3h), x); + half c = MATH_MAD(t, MATH_MAD(t, 0x1.4b4p-5h, -0x1.ffcp-2h), 1.0h); + + struct scret ret; + ret.c = c; + ret.s = s; + return ret; +} + diff --git a/amd/device-libs/ocml/src/sinhD.cl b/amd/device-libs/ocml/src/sinhD.cl new file mode 100644 index 0000000000000..83e87611af76f --- /dev/null +++ b/amd/device-libs/ocml/src/sinhD.cl @@ -0,0 +1,30 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double2 MATH_PRIVATE(epexpep)(double2 x); + +CONSTATTR double +MATH_MANGLE(sinh)(double x) +{ + double y = BUILTIN_ABS_F64(x); + double2 e = MATH_PRIVATE(epexpep)(sub(y, con(0x1.62e42fefa39efp-1,0x1.abc9e3b39803fp-56))); + double2 s = fsub(e, ldx(rcp(e), -2)); + double z = s.hi; + + if (!FINITE_ONLY_OPT()) { + z = y >= 0x1.633ce8fb9f87ep+9 ? PINF_F64 : z; + } + + z = y < 0x1.0p-27 ? y : z; + return BUILTIN_COPYSIGN_F64(z, x); +} + diff --git a/amd/device-libs/ocml/src/sinhF.cl b/amd/device-libs/ocml/src/sinhF.cl new file mode 100644 index 0000000000000..e2174103d7c7b --- /dev/null +++ b/amd/device-libs/ocml/src/sinhF.cl @@ -0,0 +1,30 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float2 MATH_PRIVATE(epexpep)(float2 x); + +CONSTATTR float +MATH_MANGLE(sinh)(float x) +{ + float y = BUILTIN_ABS_F32(x); + float2 e = MATH_PRIVATE(epexpep)(sub(y, con(0x1.62e430p-1f, -0x1.05c610p-29f))); + float2 s = fsub(e, ldx(rcp(e), -2)); + float z = s.hi; + + if (!FINITE_ONLY_OPT()) { + z = y > 0x1.65a9f8p+6f ? PINF_F32 : z; + } + + z = y < 0x1.0p-12f ? y : z; + return BUILTIN_COPYSIGN_F32(z, x); +} + diff --git a/amd/device-libs/ocml/src/sinhH.cl b/amd/device-libs/ocml/src/sinhH.cl new file mode 100644 index 0000000000000..1ee9e927f5eb7 --- /dev/null +++ b/amd/device-libs/ocml/src/sinhH.cl @@ -0,0 +1,18 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(sinh) + +CONSTATTR half +MATH_MANGLE(sinh)(half hx) +{ + float x = (float)hx * 0x1.715476p+0f; + return (half)(0.5f * (BUILTIN_AMDGPU_EXP2_F32(x) - BUILTIN_AMDGPU_EXP2_F32(-x))); +} + diff --git a/amd/device-libs/ocml/src/sinpiD.cl b/amd/device-libs/ocml/src/sinpiD.cl new file mode 100644 index 0000000000000..9fd4445c6b61a --- /dev/null +++ b/amd/device-libs/ocml/src/sinpiD.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigpiredD.h" + +double +MATH_MANGLE(sinpi)(double x) +{ + struct redret r = MATH_PRIVATE(trigpired)(BUILTIN_ABS_F64(x)); + struct scret sc = MATH_PRIVATE(sincospired)(r.hi); + + int2 s = AS_INT2((r.i & 1) == 0 ? sc.s : sc.c); + s.hi ^= (r.i > 1 ? 0x80000000 : 0) ^ (AS_INT2(x).hi & 0x80000000); + + if (!FINITE_ONLY_OPT()) { + s = BUILTIN_ISFINITE_F64(x) ? s : AS_INT2(QNANBITPATT_DP64); + } + + return AS_DOUBLE(s); +} + diff --git a/amd/device-libs/ocml/src/sinpiF.cl b/amd/device-libs/ocml/src/sinpiF.cl new file mode 100644 index 0000000000000..c2149e483ac4b --- /dev/null +++ b/amd/device-libs/ocml/src/sinpiF.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigpiredF.h" + +CONSTATTR float +MATH_MANGLE(sinpi)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + struct redret r = MATH_PRIVATE(trigpired)(ax); + struct scret sc = MATH_PRIVATE(sincospired)(r.hi); + + float s = (r.i & 1) == 0 ? sc.s : sc.c; + s = AS_FLOAT(AS_INT(s) ^ (r.i > 1 ? 0x80000000 : 0) ^ (AS_INT(x) ^ AS_INT(ax))); + + if (!FINITE_ONLY_OPT()) { + s = BUILTIN_ISFINITE_F32(ax) ? s : QNAN_F32; + } + + return s; +} + diff --git a/amd/device-libs/ocml/src/sinpiH.cl b/amd/device-libs/ocml/src/sinpiH.cl new file mode 100644 index 0000000000000..dec23a736b6e5 --- /dev/null +++ b/amd/device-libs/ocml/src/sinpiH.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigpiredH.h" + +UGEN(sinpi) + +half +MATH_MANGLE(sinpi)(half x) +{ + struct redret r = MATH_PRIVATE(trigpired)(BUILTIN_ABS_F16(x)); + struct scret sc = MATH_PRIVATE(sincospired)(r.hi); + + short s = AS_SHORT((r.i & (short)1) == (short)0 ? sc.s : sc.c); + s ^= (r.i > (short)1 ? (short)0x8000 : (short)0) ^ (AS_SHORT(x) & (short)0x8000); + + if (!FINITE_ONLY_OPT()) { + s = BUILTIN_ISFINITE_F16(x) ? s : (short)QNANBITPATT_HP16; + } + + return AS_HALF(s); +} + diff --git a/amd/device-libs/ocml/src/sqrtD.cl b/amd/device-libs/ocml/src/sqrtD.cl new file mode 100644 index 0000000000000..0423e5a87526d --- /dev/null +++ b/amd/device-libs/ocml/src/sqrtD.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(sqrt)(double x) +{ + return MATH_SQRT(x); +} + +#define GEN(LN,UN) \ +CONSTATTR double \ +MATH_MANGLE(LN)(double x) \ +{ \ + return BUILTIN_##UN##_F64(x); \ +} + +// GEN(sqrt_rte,SQRT_RTE) +// GEN(sqrt_rtn,SQRT_RTN) +// GEN(sqrt_rtp,SQRT_RTP) +// GEN(sqrt_rtz,SQRT_RTZ) + diff --git a/amd/device-libs/ocml/src/sqrtF.cl b/amd/device-libs/ocml/src/sqrtF.cl new file mode 100644 index 0000000000000..0f3bf02acdfa2 --- /dev/null +++ b/amd/device-libs/ocml/src/sqrtF.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(sqrt)(float x) +{ + return __builtin_elementwise_sqrt(x); +} + +#define GEN(LN,UN) \ +CONSTATTR float \ +MATH_MANGLE(LN)(float x) \ +{ \ + return __builtin_elementwise_sqrt(x); \ +} + +// GEN(sqrt_rte,SQRT_RTE) +// GEN(sqrt_rtn,SQRT_RTN) +// GEN(sqrt_rtp,SQRT_RTP) +// GEN(sqrt_rtz,SQRT_RTZ) + diff --git a/amd/device-libs/ocml/src/sqrtH.cl b/amd/device-libs/ocml/src/sqrtH.cl new file mode 100644 index 0000000000000..aa73ccb6f6fb2 --- /dev/null +++ b/amd/device-libs/ocml/src/sqrtH.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(sqrt) + +CONSTATTR half +MATH_MANGLE(sqrt)(half x) +{ + return BUILTIN_SQRT_F16(x); +} + +#define GEN(LN,UN) \ +CONSTATTR half \ +MATH_MANGLE(LN)(half x) \ +{ \ + return BUILTIN_##UN##_F16(x); \ +} + +// GEN(sqrt_rte,SQRT_RTE) +// GEN(sqrt_rtp,SQRT_RTN) +// GEN(sqrt_rtn,SQRT_RTP) +// GEN(sqrt_rtz,SQRT_RTZ) + diff --git a/amd/device-libs/ocml/src/subD.cl b/amd/device-libs/ocml/src/subD.cl new file mode 100644 index 0000000000000..9efd9e440f593 --- /dev/null +++ b/amd/device-libs/ocml/src/subD.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(sub_rte)(double x, double y) +{ + return x - y; +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR double \ +MATH_MANGLE(LN)(double x, double y) \ +{ \ + BUILTIN_SETROUND_F16F64(RM); \ + double ret = x - y; \ + BUILTIN_SETROUND_F16F64(ROUND_RTE); \ + return ret; \ +} + +GEN(sub_rtn, ROUND_RTN) +GEN(sub_rtp, ROUND_RTP) +GEN(sub_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/subF.cl b/amd/device-libs/ocml/src/subF.cl new file mode 100644 index 0000000000000..148b8c39af3d8 --- /dev/null +++ b/amd/device-libs/ocml/src/subF.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(sub_rte)(float x, float y) +{ + return x - y; +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR float \ +MATH_MANGLE(LN)(float x, float y) \ +{ \ + BUILTIN_SETROUND_F32(RM); \ + float ret = x - y; \ + BUILTIN_SETROUND_F32(ROUND_RTE); \ + return ret; \ +} + +GEN(sub_rtn, ROUND_RTN) +GEN(sub_rtp, ROUND_RTP) +GEN(sub_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/subH.cl b/amd/device-libs/ocml/src/subH.cl new file mode 100644 index 0000000000000..35963af63105f --- /dev/null +++ b/amd/device-libs/ocml/src/subH.cl @@ -0,0 +1,31 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_MANGLE(sub_rte)(half x, half y) +{ + return x - y; +} + +#pragma STDC FENV_ACCESS ON + +#define GEN(LN,RM) \ +CONSTATTR half \ +MATH_MANGLE(LN)(half x, half y) \ +{ \ + BUILTIN_SETROUND_F16F64(RM); \ + half ret = x - y; \ + BUILTIN_SETROUND_F16F64(ROUND_RTE); \ + return ret; \ +} + +GEN(sub_rtn, ROUND_RTN) +GEN(sub_rtp, ROUND_RTP) +GEN(sub_rtz, ROUND_RTZ) + diff --git a/amd/device-libs/ocml/src/succD.cl b/amd/device-libs/ocml/src/succD.cl new file mode 100644 index 0000000000000..387e914adb7cb --- /dev/null +++ b/amd/device-libs/ocml/src/succD.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(succ)(double x) +{ + long ix = AS_LONG(x); + long mx = SIGNBIT_DP64 - ix; + mx = ix < 0 ? mx : ix; + long t = mx + (x != PINF_F64 && !BUILTIN_ISNAN_F64(x)); + long r = SIGNBIT_DP64 - t; + r = t < 0 ? r : t; + r = mx == -1L ? SIGNBIT_DP64 : r; + return AS_DOUBLE(r); +} + diff --git a/amd/device-libs/ocml/src/succF.cl b/amd/device-libs/ocml/src/succF.cl new file mode 100644 index 0000000000000..61ab84ad03878 --- /dev/null +++ b/amd/device-libs/ocml/src/succF.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(succ)(float x) +{ + int ix = AS_INT(x); + int mx = SIGNBIT_SP32 - ix; + mx = ix < 0 ? mx : ix; + int t = mx + (x != PINF_F32 && !BUILTIN_ISNAN_F32(x)); + int r = SIGNBIT_SP32 - t; + r = t < 0 ? r : t; + r = mx == -1 ? SIGNBIT_SP32 : r; + return AS_FLOAT(r); +} + diff --git a/amd/device-libs/ocml/src/succH.cl b/amd/device-libs/ocml/src/succH.cl new file mode 100644 index 0000000000000..fe36e08ee1c4d --- /dev/null +++ b/amd/device-libs/ocml/src/succH.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half +MATH_MANGLE(succ)(half x) +{ + short ix = AS_SHORT(x); + short mx = (short)SIGNBIT_HP16 - ix; + mx = ix < (short)0 ? mx : ix; + short t = mx + (short)(x != PINF_F16 && !BUILTIN_ISNAN_F16(x)); + short r = (short)SIGNBIT_HP16 - t; + r = t < (short)0 ? r : t; + r = mx == (short)-1 ? (short)SIGNBIT_HP16 : r; + return AS_HALF(r); +} + diff --git a/amd/device-libs/ocml/src/tables.cl b/amd/device-libs/ocml/src/tables.cl new file mode 100644 index 0000000000000..342a3882afbd4 --- /dev/null +++ b/amd/device-libs/ocml/src/tables.cl @@ -0,0 +1,34 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" +#include "tables.h" + +#ifdef USE_TABLESTRUCT + +#define DECLARE_TABLE(TYPE,NAME,LENGTH) { + +#define END_TABLE() }, + +__constant struct __tbl_mem_s __tbl_mem = { + +#else + +#define DECLARE_TABLE(TYPE,NAME,LENGTH) \ +__constant TYPE TABLE_MANGLE(NAME) [ LENGTH ] = { + +#define END_TABLE() }; + +#endif + +#include "besselF_table.h" +#include "besselD_table.h" + +#ifdef USE_TABLESTRUCT +}; +#endif + diff --git a/amd/device-libs/ocml/src/tables.h b/amd/device-libs/ocml/src/tables.h new file mode 100644 index 0000000000000..9f47204ec2bf9 --- /dev/null +++ b/amd/device-libs/ocml/src/tables.h @@ -0,0 +1,47 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +// Table stuff + +#undef USE_TABLESTRUCT + +#ifdef USE_TABLESTRUCT + +struct __tbl_mem_s { + float M32_J0[72]; + float M32_J1[72]; + float M32_Y0[162] + float M32_Y1[162] + double M64_J0[120]; + double M64_J1[120]; + double M64_Y0[270]; + double M64_Y1[270]; +}; + +extern __constant struct __tbl_mem_s __tbl_mem; + +#define USE_TABLE(TYPE,PTR,NAME) \ + __constant TYPE * PTR = __ocmltbl_mem . NAME + +#else + +#define TABLE_MANGLE(NAME) __ocmltbl_##NAME + +extern __constant float TABLE_MANGLE(M32_J0)[]; +extern __constant float TABLE_MANGLE(M32_J1)[]; +extern __constant float TABLE_MANGLE(M32_Y0)[]; +extern __constant float TABLE_MANGLE(M32_Y1)[]; +extern __constant double TABLE_MANGLE(M64_J0)[]; +extern __constant double TABLE_MANGLE(M64_J1)[]; +extern __constant double TABLE_MANGLE(M64_Y0)[]; +extern __constant double TABLE_MANGLE(M64_Y1)[]; + +#define USE_TABLE(TYPE,PTR,NAME) \ + __constant TYPE * PTR = TABLE_MANGLE(NAME) + +#endif + diff --git a/amd/device-libs/ocml/src/tanD.cl b/amd/device-libs/ocml/src/tanD.cl new file mode 100644 index 0000000000000..f33b9c392b63f --- /dev/null +++ b/amd/device-libs/ocml/src/tanD.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +CONSTATTR double +MATH_MANGLE(tan)(double x) +{ + double ax = BUILTIN_ABS_F64(x); + struct redret r = MATH_PRIVATE(trigred)(ax); + + int2 t = AS_INT2(MATH_PRIVATE(tanred2)(r.hi, r.lo, r.i & 1)); + t.hi ^= AS_INT2(x).hi & (int)0x80000000; + + if (!FINITE_ONLY_OPT()) { + t = BUILTIN_ISFINITE_F64(ax) ? t : AS_INT2(QNANBITPATT_DP64); + } + + return AS_DOUBLE(t); +} + diff --git a/amd/device-libs/ocml/src/tanF.cl b/amd/device-libs/ocml/src/tanF.cl new file mode 100644 index 0000000000000..57517252b2010 --- /dev/null +++ b/amd/device-libs/ocml/src/tanF.cl @@ -0,0 +1,32 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +float +MATH_MANGLE(tan)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + + struct redret r = MATH_PRIVATE(trigred)(AS_FLOAT(ax)); + +#if defined EXTRA_PRECISION + float t = MATH_PRIVATE(tanred)(r.hi + r.lo, r.i & 1); +#else + float t = MATH_PRIVATE(tanred)(r.hi, r.i & 1); +#endif + + t = AS_FLOAT(AS_INT(t) ^ (AS_INT(x) ^ AS_INT(ax))); + + if (!FINITE_ONLY_OPT()) { + t = BUILTIN_ISFINITE_F32(ax) ? t : QNAN_F32; + } + + return t; +} + diff --git a/amd/device-libs/ocml/src/tanH.cl b/amd/device-libs/ocml/src/tanH.cl new file mode 100644 index 0000000000000..3be7bbe1e5143 --- /dev/null +++ b/amd/device-libs/ocml/src/tanH.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigredH.h" + +UGEN(tan) + +half +MATH_MANGLE(tan)(half x) +{ + half ax = BUILTIN_ABS_F16(x); + struct redret r = MATH_PRIVATE(trigred)(ax); + short t = AS_SHORT(MATH_PRIVATE(tanred)(r.hi, r.i & (short)1)); + t ^= AS_SHORT(x) & (short)0x8000; + + if (!FINITE_ONLY_OPT()) { + t = BUILTIN_ISFINITE_F16(ax) ? t : (short)QNANBITPATT_HP16; + } + + return AS_HALF(t); +} + diff --git a/amd/device-libs/ocml/src/tanhD.cl b/amd/device-libs/ocml/src/tanhD.cl new file mode 100644 index 0000000000000..6494e38fb1abf --- /dev/null +++ b/amd/device-libs/ocml/src/tanhD.cl @@ -0,0 +1,29 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR double2 MATH_PRIVATE(epexpep)(double2 x); + +CONSTATTR double +MATH_MANGLE(tanh)(double x) +{ + double y = BUILTIN_ABS_F64(x); + double2 e = MATH_PRIVATE(epexpep)(con(y, 0.0)); + double2 ei = rcp(e); + double2 t = fdiv(fsub(e, ei), fadd(e, ei)); + double z = t.hi; + + z = y > 19.0625 ? 1.0 : z; + z = y < 0x1.0p-27 ? y : z; + + return BUILTIN_COPYSIGN_F64(z, x); +} + diff --git a/amd/device-libs/ocml/src/tanhF.cl b/amd/device-libs/ocml/src/tanhF.cl new file mode 100644 index 0000000000000..e49e6d3ab19e4 --- /dev/null +++ b/amd/device-libs/ocml/src/tanhF.cl @@ -0,0 +1,46 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +#if defined EXTRA_ACCURACY +#define FLOAT_SPECIALIZATION +#include "ep.h" + +extern CONSTATTR float2 MATH_PRIVATE(epexpep)(float2 x); +#endif + +CONSTATTR float +MATH_MANGLE(tanh)(float x) +{ + float y = BUILTIN_ABS_F32(x); + +#if defined EXTRA_ACCURACY + float2 e = MATH_PRIVATE(epexpep)(con(y, 0.0f)); + float2 ei = rcp(e); + float2 t = fdiv(fsub(e, ei), fadd(e, ei)); + float z = t.hi; + + z = y > 9.0f ? 1.0f : z; + z = y < 0x1.0p-13f ? y : z; +#else + float z; + if (y < 0.625f) { + float y2 = y*y; + float p = MATH_MAD(y2, MATH_MAD(y2, MATH_MAD(y2, MATH_MAD(y2, + -0x1.758e7ap-8f, 0x1.521192p-6f), -0x1.b8389cp-5f), + 0x1.110704p-3f), -0x1.555532p-2f); + z = MATH_MAD(y2, y*p, y); + } else { + float t = MATH_MANGLE(exp)(2.0f * y); + z = MATH_MAD(-2.0f, MATH_FAST_RCP(t + 1.0f), 1.0f); + } +#endif + + return BUILTIN_COPYSIGN_F32(z, x); +} + diff --git a/amd/device-libs/ocml/src/tanhH.cl b/amd/device-libs/ocml/src/tanhH.cl new file mode 100644 index 0000000000000..41eba1796ca15 --- /dev/null +++ b/amd/device-libs/ocml/src/tanhH.cl @@ -0,0 +1,22 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR UGEN(tanh) + +CONSTATTR half +MATH_MANGLE(tanh)(half hx) +{ + float x = (float)hx * 0x1.715476p+0f; + float a = BUILTIN_AMDGPU_EXP2_F32(x); + float b = BUILTIN_AMDGPU_EXP2_F32(-x); + half one = BUILTIN_COPYSIGN_F16(1.0h, hx); + half ret = (half)((a - b) * BUILTIN_AMDGPU_RCP_F32(a + b)); + return BUILTIN_ABS_F16(hx) > 4.5h ? one : ret; +} + diff --git a/amd/device-libs/ocml/src/tanpiD.cl b/amd/device-libs/ocml/src/tanpiD.cl new file mode 100644 index 0000000000000..ab58aa90c77df --- /dev/null +++ b/amd/device-libs/ocml/src/tanpiD.cl @@ -0,0 +1,25 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigpiredD.h" + +CONSTATTR double +MATH_MANGLE(tanpi)(double x) +{ + struct redret r = MATH_PRIVATE(trigpired)(BUILTIN_ABS_F64(x)); + int2 t = AS_INT2(MATH_PRIVATE(tanpired)(r.hi, r.i & 1)); + t.hi ^= (((r.i == 1) | (r.i == 2)) & (r.hi == 0.0)) ? 0x80000000 : 0; + t.hi ^= AS_INT2(x).hi & (int)0x80000000; + + if (!FINITE_ONLY_OPT()) { + t = BUILTIN_ISFINITE_F64(x) ? t : AS_INT2(QNANBITPATT_DP64); + } + + return AS_DOUBLE(t); +} + diff --git a/amd/device-libs/ocml/src/tanpiF.cl b/amd/device-libs/ocml/src/tanpiF.cl new file mode 100644 index 0000000000000..49cb478e7aa79 --- /dev/null +++ b/amd/device-libs/ocml/src/tanpiF.cl @@ -0,0 +1,25 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigpiredF.h" + +CONSTATTR float +MATH_MANGLE(tanpi)(float x) +{ + struct redret r = MATH_PRIVATE(trigpired)(BUILTIN_ABS_F32(x)); + int t = AS_INT(MATH_PRIVATE(tanpired)(r.hi, r.i & 1)); + t ^= (((r.i == 1) | (r.i == 2)) & (r.hi == 0.0f)) ? (int)0x80000000 : 0; + t ^= AS_INT(x) & (int)0x80000000; + + if (!FINITE_ONLY_OPT()) { + t = BUILTIN_ISFINITE_F32(x) ? t : QNANBITPATT_SP32; + } + + return AS_FLOAT(t); +} + diff --git a/amd/device-libs/ocml/src/tanpiH.cl b/amd/device-libs/ocml/src/tanpiH.cl new file mode 100644 index 0000000000000..a5fbd8fab1752 --- /dev/null +++ b/amd/device-libs/ocml/src/tanpiH.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigpiredH.h" + +CONSTATTR UGEN(tanpi) + +CONSTATTR half +MATH_MANGLE(tanpi)(half x) +{ + struct redret r = MATH_PRIVATE(trigpired)(BUILTIN_ABS_F16(x)); + short t = AS_SHORT(MATH_PRIVATE(tanpired)(r.hi, r.i & (short)1)); + t ^= (((r.i == (short)1) | (r.i == (short)2)) & (r.hi == 0.0h)) ? (short)0x8000 : (short)0; + t ^= AS_SHORT(x) & (short)0x8000; + + if (!FINITE_ONLY_OPT()) { + t = BUILTIN_ISFINITE_F16(x) ? t : (short)QNANBITPATT_HP16; + } + + return AS_HALF(t); +} + diff --git a/amd/device-libs/ocml/src/tanpiredD.cl b/amd/device-libs/ocml/src/tanpiredD.cl new file mode 100644 index 0000000000000..ecedafd222b75 --- /dev/null +++ b/amd/device-libs/ocml/src/tanpiredD.cl @@ -0,0 +1,30 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigpiredD.h" + +CONSTATTR double +MATH_PRIVATE(tanpired)(double x, int i) +{ + double s = x * x; + double t = MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, + MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, + MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, + MATH_MAD(s, + 0x1.3fad0a71ea6d1p+32, -0x1.11a76ac97377bp+30), 0x1.ba2bcaca6da1bp+27), -0x1.79e8e2d7aaf57p+22), + 0x1.c1c1102e46eccp+21), 0x1.31291bbcb5588p+19), 0x1.486b2d6bb3db2p+17), 0x1.45be1b46ff156p+15), + 0x1.45f61b419c746p+13), 0x1.45f311045a4ffp+11), 0x1.45f4739a998c7p+9), 0x1.45fff9b243050p+7), + 0x1.466bc6775cf74p+5), 0x1.4abbce625be8bp+3); + t = x * s * t; + t = MATH_MAD(x, 0x1.921fb54442d18p+1, t); + + double tr = -MATH_RCP(t); + + return i ? tr : t; +} + diff --git a/amd/device-libs/ocml/src/tanpiredF.cl b/amd/device-libs/ocml/src/tanpiredF.cl new file mode 100644 index 0000000000000..96e63ad2856da --- /dev/null +++ b/amd/device-libs/ocml/src/tanpiredF.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigpiredF.h" + +CONSTATTR float +MATH_PRIVATE(tanpired)(float x, int i) +{ + float s = x * x; + + float t = MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, + MATH_MAD(s, MATH_MAD(s, + 0x1.7d2bd4p+16f, 0x1.a4d306p+12f), 0x1.435004p+11f), 0x1.4b6926p+9f), + 0x1.451e22p+7f), 0x1.467a9cp+5f), 0x1.4abb6ap+3f); + + t = x * s * t; + t = MATH_MAD(x, 0x1.921fb6p+1f, t); + + float tr = -MATH_RCP(t); + + return i ? tr : t; +} + diff --git a/amd/device-libs/ocml/src/tanpiredH.cl b/amd/device-libs/ocml/src/tanpiredH.cl new file mode 100644 index 0000000000000..645f58a5e76d1 --- /dev/null +++ b/amd/device-libs/ocml/src/tanpiredH.cl @@ -0,0 +1,25 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigpiredH.h" + +CONSTATTR half +MATH_PRIVATE(tanpired)(half x, short i) +{ + half s = x * x; + + half t = MATH_MAD(s, MATH_MAD(s, 0x1.3d8p+8h, 0x1.fe4p+4h), 0x1.508p+3h); + + t = x * s * t; + t = MATH_MAD(x, 0x1.92p+1h, t); + + half tr = -MATH_RCP(t); + + return i ? tr : t; +} + diff --git a/amd/device-libs/ocml/src/tanred2D.cl b/amd/device-libs/ocml/src/tanred2D.cl new file mode 100644 index 0000000000000..39c686424c0ae --- /dev/null +++ b/amd/device-libs/ocml/src/tanred2D.cl @@ -0,0 +1,92 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +#define DOUBLE_SPECIALIZATION +#include "ep.h" + +#define NOCFLOW + +CONSTATTR double +MATH_PRIVATE(tanred2)(double x, double xx, int sel) +{ +#if defined NOCFLOW + double s = sqr(con(x,xx)).hi; + double p = s * MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, + MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, + MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, + MATH_MAD(s, + 0x1.5e089c751c08cp-16, -0x1.78809a9a29f71p-15), + 0x1.7746f90a8aaep-14), -0x1.bb44da6fbf144p-16), + 0x1.1e634a7943acfp-13), 0x1.d250fdeb68febp-13), + 0x1.37fd9b58c4d95p-11), 0x1.7d5af15120e2cp-10), + 0x1.d6d93e09491dfp-9), 0x1.226e12033784dp-7), + 0x1.664f49ac36ae2p-6), 0x1.ba1ba1b451c21p-5), + 0x1.11111111185b7p-3), 0x1.55555555554eep-2); + double2 t = fadd(con(x,xx), mul(x, p)); + double2 tr = frcp(t); + return sel ? -tr.hi : t.hi; +#else + const double piby4_lead = 0x1.921fb54442d18p-1; + const double piby4_tail = 0x1.1a62633145c06p-55; + + // In order to maintain relative precision transform using the identity: + // tan(pi/4-x) = (1-tan(x))/(1+tan(x)) for arguments close to pi/4. + // Similarly use tan(x-pi/4) = (tan(x)-1)/(tan(x)+1) close to -pi/4. + + bool ca = x > 0.68; + bool cb = x < -0.68; + double transform = ca ? 1.0 : 0.0; + transform = cb ? -1.0 : transform; + + double tx = MATH_MAD(-transform, x, piby4_lead) + MATH_MAD(-transform, xx, piby4_tail); + + bool c = ca | cb; + x = c ? tx : x; + xx = c ? 0.0 : xx; + + // Core Remez [2,3] approximation to tan(x+xx) on the interval [0,0.68]. + double t1 = x; + double r = MATH_MAD(x*xx, 2.0, x*x); + + double a = MATH_MAD(r, + MATH_MAD(r, 0x1.d5daf289c385ap-13, -0x1.77c24c7569abbp-6), + 0x1.7d50f6638564ap-2); + + double b = MATH_MAD(r, + MATH_MAD(r, + MATH_MAD(r, -0x1.e7517ef6d98f8p-13, 0x1.ab0f4f80a0acfp-6), + -0x1.08046499eb90fp-1), + 0x1.1dfcb8caa40b8p+0); + + double t2 = MATH_MAD(MATH_FAST_DIV(a, b), x*r, xx); + + double tp = t1 + t2; + double ret; + + if (c) { + if (sel) + ret = transform * (MATH_FAST_DIV(2.0*tp, tp - 1.0) - 1.0); + else + ret = transform * (1.0 - MATH_FAST_DIV(2.0*tp, 1.0 + tp)); + } else { + if (sel) { + // Compute -1.0/(t1 + t2) accurately + double tq = t2 - (tp - t1); + double tr = -MATH_FAST_RCP(tp); + double e = MATH_MAD(tr, tq, MATH_MAD(tr, tp, 1.0)); + ret = MATH_MAD(e, tr, tr); + } else { + ret = tp; + } + } + + return ret; +#endif +} + diff --git a/amd/device-libs/ocml/src/tanredF.cl b/amd/device-libs/ocml/src/tanredF.cl new file mode 100644 index 0000000000000..70fcbd2314c45 --- /dev/null +++ b/amd/device-libs/ocml/src/tanredF.cl @@ -0,0 +1,40 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +CONSTATTR float +MATH_PRIVATE(tanred)(float x, int i) +{ + float s = x * x; + +#if defined MORE_ACCURACY + float p = s * MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, MATH_MAD(s, + MATH_MAD(s, + 0x1.33d5e6p-7f, 0x1.9697f8p-9f), 0x1.907be2p-6f), 0x1.b581ap-5f), + 0x1.112e2p-3f), 0x1.5554dcp-2f); +#else + float a = MATH_MAD(s, -0x1.19dba6p-6f, 0x1.8a8b0ep-2f); + float b = MATH_MAD(s, MATH_MAD(s, 0x1.2e2900p-6f, -0x1.07266ep-1f), 0x1.27e84ap+0f); + float p = s * MATH_FAST_DIV(a,b); +#endif + +#if defined LESS_ACCURACY + float t = MATH_MAD(p, x, x); + float tr = -MATH_FAST_RCP(t); +#else + float t = BUILTIN_FMA_F32(p, x, x); + float tt = BUILTIN_FMA_F32(p, x, -(t - x)); + float tr = -MATH_FAST_RCP(t); + float e = BUILTIN_FMA_F32(tt, tr, BUILTIN_FMA_F32(t, tr, 1.0f)); + tr = BUILTIN_FMA_F32(e, tr, tr); +#endif + + return i ? tr : t; +} + diff --git a/amd/device-libs/ocml/src/tanredH.cl b/amd/device-libs/ocml/src/tanredH.cl new file mode 100644 index 0000000000000..b11844f2b06b4 --- /dev/null +++ b/amd/device-libs/ocml/src/tanredH.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigredH.h" + +CONSTATTR half +MATH_PRIVATE(tanred)(half x, short i) +{ + half s = x * x; + + half t = MATH_MAD(s, MATH_MAD(s, 0x1.794p-4h, 0x1.e3cp-4h), 0x1.57p-2h); + t = MATH_MAD(x, s*t, x); + + half tr = -MATH_RCP(t); + + return i ? tr : t; +} + diff --git a/amd/device-libs/ocml/src/tgammaD.cl b/amd/device-libs/ocml/src/tgammaD.cl new file mode 100644 index 0000000000000..bc8fa7d9d9d8e --- /dev/null +++ b/amd/device-libs/ocml/src/tgammaD.cl @@ -0,0 +1,97 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(tgamma)(double x) +{ + double ax = BUILTIN_ABS_F64(x); + double ret; + + if (ax < 16.0) { + double n, d; + double y = x; + if (x > 0.0) { + n = 1.0; + while (y > 2.5) { + n = MATH_MAD(n, y, -n); + y = y - 1.0; + n = MATH_MAD(n, y, -n); + y = y - 1.0; + } + if (y > 1.5) { + n = MATH_MAD(n, y, -n); + y = y - 1.0; + } + if (x >= 0.5) + y = y - 1.0; + d = x < 0.5 ? x : 1.0; + } else { + d = x; + while (y < -1.5) { + d = MATH_MAD(d, y, d); + y = y + 1.0; + d = MATH_MAD(d, y, d); + y = y + 1.0; + } + if (y < -0.5) { + d = MATH_MAD(d, y, d); + y = y + 1.0; + } + n = 1.0; + } + double qt = MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, + MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, + MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, + MATH_MAD(y, + -0x1.aed75feec7b9ap-23, 0x1.31854a0be3cd3p-20), + -0x1.5037d6a97a8b7p-20), -0x1.51d67f2cdbcfbp-16), + 0x1.0c8ab2ac5112dp-13), -0x1.c364ce9b5e149p-13), + -0x1.317113a39f929p-10), 0x1.d919c501178a3p-8), + -0x1.3b4af282da690p-7), -0x1.59af103bf2cd0p-5), + 0x1.5512320b432ccp-3), -0x1.5815e8fa28886p-5), + -0x1.4fcf4026afa24p-1), 0x1.2788cfc6fb61cp-1); + + ret = MATH_DIV(n, MATH_MAD(d, y*qt, d)); + ret = x == 0.0 ? BUILTIN_COPYSIGN_F64(PINF_F64, x) : ret; + ret = x < 0.0 && BUILTIN_FRACTION_F64(x) == 0.0 ? QNAN_F64 : ret; + } else { + const double sqrt2pi = 0x1.40d931ff62706p+1; + const double sqrtpiby2 = 0x1.40d931ff62706p+0; + + double t1 = MATH_MANGLE(powr)(ax, MATH_MAD(ax, 0.5, -0.25)); + double t2 = MATH_MANGLE(exp)(-ax); + double xr = MATH_FAST_RCP(ax); + double pt = MATH_MAD(xr, MATH_MAD(xr, MATH_MAD(xr, MATH_MAD(xr, + MATH_MAD(xr, MATH_MAD(xr, + -0x1.2b04c5ea74bbfp-11, 0x1.14869344f1d9bp-14), + 0x1.9b3457156ffefp-11), -0x1.e1427e86ee097p-13), + -0x1.5f7266f67c4e0p-9), 0x1.c71c71c0f96adp-9), + 0x1.5555555555a28p-4); + + if (x > 0.0) { + double gt = sqrt2pi*t2*t1*t1; + double g = MATH_MAD(gt, xr*pt, gt); + ret = x > 0x1.573fae561f646p+7 ? PINF_F64 : g; + } else { + double s = -x * MATH_MANGLE(sinpi)(x); + if (x > -170.5) { + double d = s*t2*t1*t1; + ret = MATH_DIV(sqrtpiby2, MATH_MAD(d, xr*pt, d)); + } else if (x > -184.0) { + double d = t2*t1; + ret = MATH_DIV(MATH_DIV(sqrtpiby2, MATH_MAD(d, xr*pt, d)), s*t1); + } else + ret = BUILTIN_COPYSIGN_F64(0.0, s); + ret = BUILTIN_FRACTION_F64(x) == 0.0 || BUILTIN_ISNAN_F64(x) ? QNAN_F64 : ret; + } + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/tgammaF.cl b/amd/device-libs/ocml/src/tgammaF.cl new file mode 100644 index 0000000000000..623d255dc7f77 --- /dev/null +++ b/amd/device-libs/ocml/src/tgammaF.cl @@ -0,0 +1,80 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(tgamma)(float x) +{ + float ax = BUILTIN_ABS_F32(x); + float ret; + + if (ax < 16.0f) { + float n, d; + float y = x; + if (x > 0.0f) { + n = 1.0f; + while (y > 2.5f) { + n = MATH_MAD(n, y, -n); + y = y - 1.0f; + n = MATH_MAD(n, y, -n); + y = y - 1.0f; + } + if (y > 1.5f) { + n = MATH_MAD(n, y, -n); + y = y - 1.0f; + } + if (x >= 0.5f) + y = y - 1.0f; + d = x < 0.5f ? x : 1.0f; + } else { + d = x; + while (y < -1.5f) { + d = MATH_MAD(d, y, d); + y = y + 1.0f; + d = MATH_MAD(d, y, d); + y = y + 1.0f; + } + if (y < -0.5f) { + d = MATH_MAD(d, y, d); + y = y + 1.0f; + } + n = 1.0f; + } + float qt = MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, MATH_MAD(y, + MATH_MAD(y, MATH_MAD(y, + 0x1.d5a56ep-8f, -0x1.4dcb00p-7f), -0x1.59c03ap-5f), 0x1.55405ap-3f), + -0x1.5810f2p-5f), -0x1.4fcfd6p-1f), 0x1.2788ccp-1f); + ret = MATH_DIV(n, MATH_MAD(d, y*qt, d)); + ret = x == 0.0f ? BUILTIN_COPYSIGN_F32(PINF_F32, x) : ret; + ret = x < 0.0f && BUILTIN_FRACTION_F32(x) == 0.0f ? QNAN_F32 : ret; + } else { + const float sqrt2pi = 0x1.40d932p+1f; + const float sqrtpiby2 = 0x1.40d932p+0f; + + float t1 = MATH_MANGLE(powr)(ax, MATH_MAD(ax, 0.5f, -0.25f)); + float t2 = MATH_MANGLE(exp)(-ax); + float xr = MATH_FAST_RCP(ax); + float p = MATH_MAD(xr, MATH_MAD(xr, 0x1.96d7e4p-9f, 0x1.556652p-4f), 0x1.fffff8p-1f); + if (x > 0.0f) { + float g = sqrt2pi*t2*t1*t1*p; + ret = x > 0x1.18521ep+5f ? PINF_F32 : g; + } else { + float s = -x * MATH_MANGLE(sinpi)(x); + if (x > -30.0f) + ret = MATH_DIV(sqrtpiby2, s*t2*t1*t1*p); + else if (x > -41.0f) + ret = MATH_DIV(MATH_DIV(sqrtpiby2, t2*t1*p), s*t1); + else + ret = BUILTIN_COPYSIGN_F32(0.0f, s); + ret = BUILTIN_FRACTION_F32(x) == 0.0f || BUILTIN_ISNAN_F32(x) ? QNAN_F32 : ret; + } + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/tgammaH.cl b/amd/device-libs/ocml/src/tgammaH.cl new file mode 100644 index 0000000000000..a69bd83a8eb19 --- /dev/null +++ b/amd/device-libs/ocml/src/tgammaH.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +UGEN(tgamma) + +CONSTATTR half +MATH_MANGLE(tgamma)(half x) +{ + return (half)MATH_UPMANGLE(tgamma)((float)x); +} + diff --git a/amd/device-libs/ocml/src/trigpiredD.cl b/amd/device-libs/ocml/src/trigpiredD.cl new file mode 100644 index 0000000000000..7bea3077802c6 --- /dev/null +++ b/amd/device-libs/ocml/src/trigpiredD.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigpiredD.h" + +CONSTATTR struct redret +MATH_PRIVATE(trigpired)(double x) +{ + double t = 2.0 * BUILTIN_FRACTION_F64(0.5 * x); + x = x > 1.0 ? t : x; + t = BUILTIN_RINT_F64(2.0 * x); + + struct redret ret; + ret.hi = MATH_MAD(t, -0.5, x); + ret.i = (int)t & 0x3; + return ret; +} + diff --git a/amd/device-libs/ocml/src/trigpiredD.h b/amd/device-libs/ocml/src/trigpiredD.h new file mode 100644 index 0000000000000..3d82c947b505f --- /dev/null +++ b/amd/device-libs/ocml/src/trigpiredD.h @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +struct redret { + double hi; + int i; +}; + +struct scret { + double c; + double s; +}; + +extern CONSTATTR struct redret MATH_PRIVATE(trigpired)(double x); +extern CONSTATTR struct scret MATH_PRIVATE(sincospired)(double x); +extern CONSTATTR double MATH_PRIVATE(tanpired)(double x, int i); + diff --git a/amd/device-libs/ocml/src/trigpiredF.cl b/amd/device-libs/ocml/src/trigpiredF.cl new file mode 100644 index 0000000000000..bcdc572795f22 --- /dev/null +++ b/amd/device-libs/ocml/src/trigpiredF.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigpiredF.h" + +CONSTATTR struct redret +MATH_PRIVATE(trigpired)(float x) +{ + float t = 2.0f * BUILTIN_FRACTION_F32(0.5f * x); + x = x > 1.0f ? t : x; + t = BUILTIN_RINT_F32(2.0f * x); + + struct redret ret; + ret.hi = MATH_MAD(t, -0.5f, x); + ret.i = (int)t & 0x3; + return ret; +} + diff --git a/amd/device-libs/ocml/src/trigpiredF.h b/amd/device-libs/ocml/src/trigpiredF.h new file mode 100644 index 0000000000000..f6727b5b48d52 --- /dev/null +++ b/amd/device-libs/ocml/src/trigpiredF.h @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +struct redret { + float hi; + int i; +}; + +struct scret { + float s; + float c; +}; + +extern CONSTATTR struct redret MATH_PRIVATE(trigpired)(float x); +extern CONSTATTR struct scret MATH_PRIVATE(sincospired)(float x); +extern CONSTATTR float MATH_PRIVATE(tanpired)(float x, int i); + diff --git a/amd/device-libs/ocml/src/trigpiredH.cl b/amd/device-libs/ocml/src/trigpiredH.cl new file mode 100644 index 0000000000000..7615528f48f56 --- /dev/null +++ b/amd/device-libs/ocml/src/trigpiredH.cl @@ -0,0 +1,23 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigpiredH.h" + +CONSTATTR struct redret +MATH_PRIVATE(trigpired)(half x) +{ + half t = 2.0h * BUILTIN_FRACTION_F16(0.5h * x); + x = x > 1.0h ? t : x; + t = BUILTIN_RINT_F16(2.0h * x); + + struct redret ret; + ret.hi = MATH_MAD(t, -0.5h, x); + ret.i = (short)t & (short)0x3; + return ret; +} + diff --git a/amd/device-libs/ocml/src/trigpiredH.h b/amd/device-libs/ocml/src/trigpiredH.h new file mode 100644 index 0000000000000..b2d240f51412d --- /dev/null +++ b/amd/device-libs/ocml/src/trigpiredH.h @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +struct redret { + half hi; + short i; +}; + +struct scret { + half s; + half c; +}; + +extern CONSTATTR struct redret MATH_PRIVATE(trigpired)(half x); +extern CONSTATTR struct scret MATH_PRIVATE(sincospired)(half x); +extern CONSTATTR half MATH_PRIVATE(tanpired)(half x, short i); + diff --git a/amd/device-libs/ocml/src/trigredD.cl b/amd/device-libs/ocml/src/trigredD.cl new file mode 100644 index 0000000000000..5826f15b4e07a --- /dev/null +++ b/amd/device-libs/ocml/src/trigredD.cl @@ -0,0 +1,19 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +CONSTATTR struct redret +MATH_PRIVATE(trigred)(double x) +{ + if (x < 0x1.0p+30) + return MATH_PRIVATE(trigredsmall)(x); + else + return MATH_PRIVATE(trigredlarge)(x); +} + diff --git a/amd/device-libs/ocml/src/trigredD.h b/amd/device-libs/ocml/src/trigredD.h new file mode 100644 index 0000000000000..26a9599db56e8 --- /dev/null +++ b/amd/device-libs/ocml/src/trigredD.h @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +struct redret { + double lo; + double hi; + int i; +}; + +struct scret { + double s; + double c; +}; + +extern CONSTATTR struct redret MATH_PRIVATE(trigredsmall)(double x); +extern CONSTATTR struct redret MATH_PRIVATE(trigredlarge)(double x); +extern CONSTATTR struct redret MATH_PRIVATE(trigred)(double x); + +extern CONSTATTR struct scret MATH_PRIVATE(sincosred)(double x); +extern CONSTATTR struct scret MATH_PRIVATE(sincosred2)(double x, double y); + +extern CONSTATTR double MATH_PRIVATE(tanred2)(double x, double xx, int sel); + diff --git a/amd/device-libs/ocml/src/trigredF.cl b/amd/device-libs/ocml/src/trigredF.cl new file mode 100644 index 0000000000000..20cbd39b42b73 --- /dev/null +++ b/amd/device-libs/ocml/src/trigredF.cl @@ -0,0 +1,19 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +CONSTATTR struct redret +MATH_PRIVATE(trigred)(float x) +{ + if (x < SMALL_BOUND) + return MATH_PRIVATE(trigredsmall)(x); + else + return MATH_PRIVATE(trigredlarge)(x); +} + diff --git a/amd/device-libs/ocml/src/trigredF.h b/amd/device-libs/ocml/src/trigredF.h new file mode 100644 index 0000000000000..e0e50c93635b2 --- /dev/null +++ b/amd/device-libs/ocml/src/trigredF.h @@ -0,0 +1,40 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define SMALL_BOUND 0x1.0p+17f + +#if defined EXTRA_PRECISION +struct redret { + float hi; + float lo; + int i; +}; +#else +struct redret { + float hi; + int i; +}; +#endif + +struct scret { + float s; + float c; +}; + +extern CONSTATTR struct redret MATH_PRIVATE(trigredsmall)(float x); +extern CONSTATTR struct redret MATH_PRIVATE(trigredlarge)(float x); +extern CONSTATTR struct redret MATH_PRIVATE(trigred)(float x); + + +#if defined EXTRA_PRECISION +extern CONSTATTR struct scret MATH_PRIVATE(sincosred2)(float x, float y); +#else +extern CONSTATTR struct scret MATH_PRIVATE(sincosred)(float x); +#endif + +extern CONSTATTR float MATH_PRIVATE(tanred)(float x, int regn); + diff --git a/amd/device-libs/ocml/src/trigredH.cl b/amd/device-libs/ocml/src/trigredH.cl new file mode 100644 index 0000000000000..ac75d51aac892 --- /dev/null +++ b/amd/device-libs/ocml/src/trigredH.cl @@ -0,0 +1,27 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" +#include "trigredH.h" + +CONSTATTR struct redret +MATH_PRIVATE(trigred)(half hx) +{ + const float twobypi = 0x1.45f306p-1f; + const float pb2_a = 0x1.92p+0f; + const float pb2_b = 0x1.fap-12f; + const float pb2_c = 0x1.54442ep-20f; + + float x = (float)hx; + float fn = BUILTIN_RINT_F32(x * twobypi); + + struct redret ret; + ret.hi = (half)BUILTIN_MAD_F32(fn, -pb2_c, BUILTIN_MAD_F32(fn, -pb2_b, BUILTIN_MAD_F32(fn, -pb2_a, x))); + ret.i = (int)fn & 0x3; + return ret; +} + diff --git a/amd/device-libs/ocml/src/trigredH.h b/amd/device-libs/ocml/src/trigredH.h new file mode 100644 index 0000000000000..2f02b42a295a2 --- /dev/null +++ b/amd/device-libs/ocml/src/trigredH.h @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +struct redret { + half hi; + short i; +}; + +struct scret { + half s; + half c; +}; + +extern CONSTATTR struct redret MATH_PRIVATE(trigred)(half x); +extern CONSTATTR struct scret MATH_PRIVATE(sincosred)(half x); +extern CONSTATTR half MATH_PRIVATE(tanred)(half x, short i); + diff --git a/amd/device-libs/ocml/src/trigredlargeD.cl b/amd/device-libs/ocml/src/trigredlargeD.cl new file mode 100644 index 0000000000000..b0d2e1abb9ef1 --- /dev/null +++ b/amd/device-libs/ocml/src/trigredlargeD.cl @@ -0,0 +1,105 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +// Allow H,L to be the same as A,B +#define FSUM2(A, B, H, L) \ + do { \ + double __s = A + B; \ + double __t = B - (__s - A); \ + H = __s; \ + L = __t; \ + } while (0) + +#define SUM2(A, B, H, L) \ + do { \ + double __s = A + B; \ + double __aa = __s - B; \ + double __bb = __s - __aa; \ + double __da = A - __aa; \ + double __db = B - __bb; \ + double __t = __da + __db; \ + H = __s; \ + L = __t; \ + } while (0) + +#define PROD2(A, B, H, L) \ + do { \ + double __p = A * B; \ + double __q = BUILTIN_FMA_F64(A, B, -__p); \ + H = __p; \ + L = __q; \ + } while (0) + +#define EVALUATE(A, B2, B1, B0, F2, F1, F0) \ + do { \ + double __p2h, __p2l, __p1h, __p1l, __p0h, __p0l; \ + double __v1h, __v1l, __v2h, __v2l, __w2h, __w2l; \ + double __e0, __e1, __e2, __e3; \ + PROD2(B0, A, __p0h, __p0l); \ + PROD2(B1, A, __p1h, __p1l); \ + PROD2(B2, A, __p2h, __p2l); \ + SUM2(__p2l, __p1h, __v2h, __v2l); \ + SUM2(__p1l, __p0h, __v1h, __v1l); \ + SUM2(__v2l, __v1h, __w2h, __w2l); \ + __e3 = __p2h; \ + __e2 = __v2h; \ + __e1 = __w2h; \ + __e0 = __w2l + __v1l + __p0l; \ + FSUM2(__e3, __e2, __e3, __e2); \ + FSUM2(__e2, __e1, __e2, __e1); \ + FSUM2(__e1, __e0, __e1, __e0); \ + F2 = __e3; \ + F1 = __e2; \ + F0 = __e1; \ + } while(0) + +CONSTATTR struct redret +MATH_PRIVATE(trigredlarge)(double x) +{ + // Scale x by relevant part of 2/pi + double p2 = BUILTIN_AMDGPU_TRIG_PREOP_F64(x, 0); + double p1 = BUILTIN_AMDGPU_TRIG_PREOP_F64(x, 1); + double p0 = BUILTIN_AMDGPU_TRIG_PREOP_F64(x, 2); + + x = x >= 0x1.0p+945 ? BUILTIN_FLDEXP_F64(x, -128) : x; + + double f2, f1, f0; + EVALUATE(x, p2, p1, p0, f2, f1, f0); + + f2 = BUILTIN_FLDEXP_F64(BUILTIN_FRACTION_F64(BUILTIN_FLDEXP_F64(f2, -2)), 2); + f2 += f2+f1 < 0.0 ? 4.0 : 0.0; + + int i = (int)(f2 + f1); + f2 -= (double)i; + + FSUM2(f2, f1, f2, f1); + FSUM2(f1, f0, f1, f0); + + int g = f2 >= 0.5; + i += g; + f2 -= g ? 1.0 : 0.0; + + FSUM2(f2, f1, f2, f1); + + const double pio2h = 0x1.921fb54442d18p+0; + const double pio2t = 0x1.1a62633145c07p-54; + + double rh = f2 * pio2h; + double rt = BUILTIN_FMA_F64(f1, pio2h, BUILTIN_FMA_F64(f2, pio2t, BUILTIN_FMA_F64(f2, pio2h, -rh))); + + FSUM2(rh, rt, rh, rt); + + struct redret ret; + ret.hi = rh; + ret.lo = rt; + ret.i = i & 0x3; + return ret; +} + diff --git a/amd/device-libs/ocml/src/trigredlargeF.cl b/amd/device-libs/ocml/src/trigredlargeF.cl new file mode 100644 index 0000000000000..4fc23a2ef307f --- /dev/null +++ b/amd/device-libs/ocml/src/trigredlargeF.cl @@ -0,0 +1,148 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + + +CONSTATTR struct redret +MATH_PRIVATE(trigredlarge)(float x) +{ + int xe = (int)(AS_UINT(x) >> 23) - 127; + uint xm = 0x00800000U | (AS_UINT(x) & 0x7fffffU); + + // 224 bits of 2/PI: . A2F9836E 4E441529 FC2757D1 F534DDC0 DB629599 3C439041 FE5163AB + const uint b6 = 0xA2F9836EU; + const uint b5 = 0x4E441529U; + const uint b4 = 0xFC2757D1U; + const uint b3 = 0xF534DDC0U; + const uint b2 = 0xDB629599U; + const uint b1 = 0x3C439041U; + const uint b0 = 0xFE5163ABU; + + uint p0, p1, p2, p3, p4, p5, p6, p7; + ulong a; + + a = (ulong)xm * (ulong)b0; p0 = a; a >>= 32; + a = (ulong)xm * (ulong)b1 + a; p1 = a; a >>= 32; + a = (ulong)xm * (ulong)b2 + a; p2 = a; a >>= 32; + a = (ulong)xm * (ulong)b3 + a; p3 = a; a >>= 32; + a = (ulong)xm * (ulong)b4 + a; p4 = a; a >>= 32; + a = (ulong)xm * (ulong)b5 + a; p5 = a; a >>= 32; + a = (ulong)xm * (ulong)b6 + a; p6 = a; p7 = a >> 32; + + uint fbits = 224 + 23 - xe; + + // shift amount to get 2 lsb of integer part at top 2 bits + // min: 25 (xe=18) max: 134 (xe=127) + uint shift = 256U - 2 - fbits; + + // Shift by up to 134/32 = 4 words + int c = shift > 63; + p7 = c ? p5 : p7; + p6 = c ? p4 : p6; + p5 = c ? p3 : p5; + p4 = c ? p2 : p4; + p3 = c ? p1 : p3; + p2 = c ? p0 : p2; + shift -= (-c) & 64; + + c = shift > 31; + p7 = c ? p6 : p7; + p6 = c ? p5 : p6; + p5 = c ? p4 : p5; + p4 = c ? p3 : p4; + p3 = c ? p2 : p3; + shift -= (-c) & 32; + + c = shift > 31; + p7 = c ? p6 : p7; + p6 = c ? p5 : p6; + p5 = c ? p4 : p5; + p4 = c ? p3 : p4; + shift -= (-c) & 32; + + // BUILTIN_BITALIGN_B32 cannot handle a shift of 32 + c = shift > 0; + shift = 32 - shift; + uint t7 = BUILTIN_BITALIGN_B32(p7, p6, shift); + uint t6 = BUILTIN_BITALIGN_B32(p6, p5, shift); + uint t5 = BUILTIN_BITALIGN_B32(p5, p4, shift); + p7 = c ? t7 : p7; + p6 = c ? t6 : p6; + p5 = c ? t5 : p5; + + // Get 2 lsb of int part and msb of fraction + int i = p7 >> 29; + + // Scoot up 2 more bits so only fraction remains + p7 = BUILTIN_BITALIGN_B32(p7, p6, 30); + p6 = BUILTIN_BITALIGN_B32(p6, p5, 30); + p5 = BUILTIN_BITALIGN_B32(p5, p4, 30); + + // Subtract 1 if msb of fraction is 1, i.e. fraction >= 0.5 + uint flip = i & 1 ? 0xffffffffU : 0U; + uint sign = i & 1 ? 0x80000000U : 0U; + p7 = p7 ^ flip; + p6 = p6 ^ flip; + p5 = p5 ^ flip; + + // Find exponent and shift away leading zeroes and hidden bit + xe = BUILTIN_CLZ_U32(p7) + 1; + shift = 32 - xe; + p7 = BUILTIN_BITALIGN_B32(p7, p6, shift); + p6 = BUILTIN_BITALIGN_B32(p6, p5, shift); + + // Most significant part of fraction + float q1 = AS_FLOAT(sign | ((127 - xe) << 23) | (p7 >> 9)); + + // Shift out bits we captured on q1 + p7 = BUILTIN_BITALIGN_B32(p7, p6, 32-23); + + // Get 24 more bits of fraction in another float, there are not long strings of zeroes here + int xxe = BUILTIN_CLZ_U32(p7) + 1; + p7 = BUILTIN_BITALIGN_B32(p7, p6, 32-xxe); + float q0 = AS_FLOAT(sign | ((127 - (xe + 23 + xxe)) << 23) | (p7 >> 9)); + + // At this point, the fraction q1 + q0 is correct to at least 48 bits + // Now we need to multiply the fraction by pi/2 + // This loses us about 4 bits + // pi/2 = C90 FDA A22 168 C23 4C4 + + const float pio2h = (float)0xc90fda / 0x1.0p+23f; + const float pio2hh = (float)0xc90 / 0x1.0p+11f; + const float pio2ht = (float)0xfda / 0x1.0p+23f; + const float pio2t = (float)0xa22168 / 0x1.0p+47f; + + float rh, rt; + + if (HAVE_FAST_FMA32() || !DAZ_OPT()) { + rh = q1 * pio2h; + rt = BUILTIN_FMA_F32(q0, pio2h, BUILTIN_FMA_F32(q1, pio2t, BUILTIN_FMA_F32(q1, pio2h, -rh))); + } else { + float q1h = AS_FLOAT(AS_UINT(q1) & 0xfffff000); + float q1t = q1 - q1h; + rh = q1 * pio2h; + rt = MATH_MAD(q1t, pio2ht, MATH_MAD(q1t, pio2hh, MATH_MAD(q1h, pio2ht, MATH_MAD(q1h, pio2hh, -rh)))) + + MATH_MAD(q0, pio2h, q1*pio2t); + } + + struct redret ret; +#if defined EXTRA_PRECISION + float t = rh + rt; + rt = rt - (t - rh); + + ret.hi = t; + ret.lo = rt; +#else + ret.hi = rh + rt; +#endif + + ret.i = ((i >> 1) + (i & 1)) & 0x3; + return ret; +} + diff --git a/amd/device-libs/ocml/src/trigredsmallD.cl b/amd/device-libs/ocml/src/trigredsmallD.cl new file mode 100644 index 0000000000000..0cac73ef36ce1 --- /dev/null +++ b/amd/device-libs/ocml/src/trigredsmallD.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" +#include "trigredD.h" + +CONSTATTR struct redret +MATH_PRIVATE(trigredsmall)(double x) +{ + const double twobypi = 0x1.45f306dc9c883p-1; + const double piby2_h = 0x1.921fb54442d18p+0; + const double piby2_m = 0x1.1a62633145c00p-54; + const double piby2_t = 0x1.b839a252049c0p-104; + + double dn = BUILTIN_RINT_F64(x * twobypi); + double xt = BUILTIN_FMA_F64(dn, -piby2_h, x); + double yh = BUILTIN_FMA_F64(dn, -piby2_m, xt); + double ph = dn * piby2_m; + double pt = BUILTIN_FMA_F64(dn, piby2_m, -ph); + double th = xt - ph; + double tt = (xt - th) - ph; + double yt = BUILTIN_FMA_F64(dn, -piby2_t, ((th - yh) + tt) - pt); + double rh = yh + yt; + double rt = yt - (rh - yh); + + struct redret ret; + ret.hi = rh; + ret.lo = rt; + ret.i = (int)dn & 0x3; + return ret; +} + diff --git a/amd/device-libs/ocml/src/trigredsmallF.cl b/amd/device-libs/ocml/src/trigredsmallF.cl new file mode 100644 index 0000000000000..c93a27610d4fa --- /dev/null +++ b/amd/device-libs/ocml/src/trigredsmallF.cl @@ -0,0 +1,103 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" +#include "trigredF.h" + +#define FMUL(A, AHI, ALO, B, BHI, BLO, CHI, CLO) \ + do { \ + CHI = A * B; \ + CLO = MATH_MAD(ALO, BLO, MATH_MAD(ALO, BHI, MATH_MAD(AHI, BLO, MATH_MAD(AHI, BHI, -CHI)))); \ + } while(0) + +#define FNMA(A, AHI, ALO, B, BHI, BLO, C, D) \ + do { \ + float __ph, __pt; \ + FMUL(A, AHI, ALO, B, BHI, BLO, __ph, __pt); \ + float __t = C - __ph; \ + D = __t + (((C - __t) - __ph) - __pt); \ + } while(0) + +static inline struct redret +mad_reduce(float x) +{ +#if defined EXTRA_PRECISION +#error Not implemented +#else + const float twobypi = 0x1.45f306p-1f; + + const float piby2_h = 0x1.921fb4p+0f; + const float piby2_hh = 0x1.92p+0f; + const float piby2_hl = 0x1.fb4p-12f; + + const float piby2_m = 0x1.4442d0p-24f; + const float piby2_mh = 0x1.444p-24f; + const float piby2_ml = 0x1.680p-39f; + + const float piby2_l = 0x1.846988p-48f; + const float piby2_lh = 0x1.846p-48f; + const float piby2_ll = 0x1.310p-61f; + + + float fn = BUILTIN_RINT_F32(x * twobypi); + float fnh = AS_FLOAT(AS_UINT(fn) & 0xfffff000U); + float fnl = fn - fnh; + + float r; + FNMA(fn, fnh, fnl, piby2_h, piby2_hh, piby2_hl, x, r); + FNMA(fn, fnh, fnl, piby2_m, piby2_mh, piby2_ml, r, r); + + struct redret ret; + ret.hi = MATH_MAD(-piby2_l, fn, r); + ret.i = (int)fn & 0x3; + return ret; +#endif +} + +static inline struct redret +fma_reduce(float x) +{ + const float twobypi = 0x1.45f306p-1f; + const float piby2_h = 0x1.921fb4p+0f; + const float piby2_m = 0x1.4442d0p-24f; + const float piby2_l = 0x1.846988p-48f; + + float fn = BUILTIN_RINT_F32(x * twobypi); + + struct redret ret; + +#if defined EXTRA_PRECISION + float xt = BUILTIN_FMA_F32(fn, -piby2_h, x); + float yh = BUILTIN_FMA_F32(fn, -piby2_m, xt); + float ph = fn * piby2_m; + float pt = BUILTIN_FMA_F32(fn, piby2_m, -ph); + float th = xt - ph; + float tt = (xt - th) - ph; + float yt = BUILTIN_FMA_F32(fn, -piby2_l, ((th - yh) + tt) - pt); + float rh = yh + yt; + float rt = yt - (rh - yh); + ret.hi = rh; + ret.lo = rt; +#else + float r = BUILTIN_FMA_F32(fn, -piby2_l, BUILTIN_FMA_F32(fn, -piby2_m, BUILTIN_FMA_F32(fn, -piby2_h, x))); + ret.hi = r; +#endif + + ret.i =(int)fn & 0x3; + return ret; +} + +CONSTATTR struct redret +MATH_PRIVATE(trigredsmall)(float x) +{ + if (HAVE_FAST_FMA32()) { + return fma_reduce(x); + } else { + return mad_reduce(x); + } +} + diff --git a/amd/device-libs/ocml/src/truncD.cl b/amd/device-libs/ocml/src/truncD.cl new file mode 100644 index 0000000000000..b1ae04174cfd6 --- /dev/null +++ b/amd/device-libs/ocml/src/truncD.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +CONSTATTR double +MATH_MANGLE(trunc)(double x) +{ + return BUILTIN_TRUNC_F64(x); +} diff --git a/amd/device-libs/ocml/src/truncF.cl b/amd/device-libs/ocml/src/truncF.cl new file mode 100644 index 0000000000000..3d2793634f0ca --- /dev/null +++ b/amd/device-libs/ocml/src/truncF.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +CONSTATTR float +MATH_MANGLE(trunc)(float x) +{ + return BUILTIN_TRUNC_F32(x); +} diff --git a/amd/device-libs/ocml/src/truncH.cl b/amd/device-libs/ocml/src/truncH.cl new file mode 100644 index 0000000000000..6787af800b77e --- /dev/null +++ b/amd/device-libs/ocml/src/truncH.cl @@ -0,0 +1,21 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +CONSTATTR half2 +MATH_MANGLE2(trunc)(half2 x) +{ + return BUILTIN_TRUNC_2F16(x); +} + +CONSTATTR half +MATH_MANGLE(trunc)(half x) +{ + return BUILTIN_TRUNC_F16(x); +} + diff --git a/amd/device-libs/ocml/src/y0D.cl b/amd/device-libs/ocml/src/y0D.cl new file mode 100644 index 0000000000000..b296c0548da3e --- /dev/null +++ b/amd/device-libs/ocml/src/y0D.cl @@ -0,0 +1,154 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +extern double MATH_PRIVATE(sinb)(double, int, double); +extern CONSTATTR double MATH_PRIVATE(bp0)(double); +extern CONSTATTR double MATH_PRIVATE(ba0)(double); + +CONSTATTR double +MATH_MANGLE(y0)(double x) +{ + const double b0 = 0.3125; + const double b1 = 0.4375; + const double b2 = 0.5625; + const double b3 = 0.6875; + const double b4 = 0.8125; + const double b5 = 1.0; + const double b6 = 1.25; + const double b7 = 1.625; + const double b8 = 2.0; + const double b9 = 2.53125; + const double b10 = 3.0; + const double b11 = 3.484375; + const double b12 = 4.703125; + const double b13 = 6.265625; + const double b14 = 7.84375; + const double b15 = 9.421875; + const double b16 = 10.984375; + const double b17 = 12.546875; + double ret; + + if (x <= b17) { + // Ty to maintain relative accuracy here + + USE_TABLE(double, p, M64_Y0); + double ch, cl; + + if (x < b8) { + if (x < b4) { + if (x < b0) { + ch = 0.0; + cl = 0.0; + } else if (x < b1) { + ch = 0x1.4p-2; + cl = 0.0; + p += 1*15; + } else if (x < b2) { + ch = 0x1.cp-2; + cl = 0.0; + p += 2*15; + } else if (x < b3) { + ch = 0x1.2p-1; + cl = 0.0; + p += 3*15; + } else { + ch = 0x1.6p-1; + cl = 0.0; + p += 4*15; + } + } else { + if (x < b5) { + ch = 0x1.c982eb8d417eap-1; + cl = 0x1.ea9d270347f83p-56; + p += 5*15; + } else if (x < b6) { + ch = 0x1.p+0; + cl = 0.0; + p += 6*15; + } else if (x < b7) { + ch = 0x1.4p+0; + cl = 0.0; + p += 7*15; + } else { + ch = 0x1.ap+0; + cl = 0.0; + p += 8*15; + } + } + } else { + if (x < b13) { + if (x < b9) { + ch = 0x1.193bed4dff243p+1; + cl = -0x1.bd1e50d219bfdp-55; + p += 9*15; + } else if (x < b10) { + ch = 0x1.44p+1; + cl = 0.0; + p += 10*15; + } else if (x < b11) { + ch = 0x1.8p+1; + cl = 0.0; + p += 11*15; + } else if (x < b12) { + ch = 0x1.fa9534d98569cp+1; + cl = -0x1.f06ae7804384ep-54; + p += 12*15; + } else { + ch = 0x1.5b7fe4e87b02ep+2; + cl = 0x1.dfe7bac228e8cp-52; + p += 13*15; + } + } else { + if (x < b14) { + ch = 0x1.c581dc4e72103p+2; + cl = -0x1.9774a495f56cfp-54; + p += 14*15; + } else if (x < b15) { + ch = 0x1.13127ae6169b4p+3; + cl = 0x1.479cc068d9046p-52; + p += 15*15; + } else if (x < b16) { + ch = 0x1.471d735a47d58p+3; + cl = -0x1.cb49ff791c495p-51; + p += 16*15; + } else { + ch = 0x1.77f9138d43206p+3; + cl = 0x1.0fc786ce0608p-55; + p += 17*15; + } + } + } + + ret = 0.0; + if (x < b0) { + ret = 0x1.45f306dc9c883p-1 * MATH_MANGLE(j0)(x) * MATH_MANGLE(log)(x); + x = x*x; + } + + x = x - ch - cl; + ret += MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, + p[14], p[13]), p[12]), + p[11]), p[10]), p[9]), p[8]), + p[7]), p[6]), p[5]), p[4]), + p[3]), p[2]), p[1]), p[0]); + + } else { + double r = MATH_RCP(x); + double r2 = r*r; + double p = MATH_PRIVATE(bp0)(r2) * r; + ret = 0x1.9884533d43651p-1 * MATH_FAST_SQRT(r) * MATH_PRIVATE(ba0)(r2) * MATH_PRIVATE(sinb)(x, 0, p); + ret = x == PINF_F64 ? 0.0 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/y0F.cl b/amd/device-libs/ocml/src/y0F.cl new file mode 100644 index 0000000000000..44392de8a3011 --- /dev/null +++ b/amd/device-libs/ocml/src/y0F.cl @@ -0,0 +1,150 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +extern float MATH_PRIVATE(sinb)(float, int, float); +extern CONSTATTR float MATH_PRIVATE(bp0)(float); +extern CONSTATTR float MATH_PRIVATE(ba0)(float); + +CONSTATTR float +MATH_MANGLE(y0)(float x) +{ + const float b0 = 0.3125f; + const float b1 = 0.4375f; + const float b2 = 0.5625f; + const float b3 = 0.6875f; + const float b4 = 0.8125f; + const float b5 = 1.0f; + const float b6 = 1.25f; + const float b7 = 1.625f; + const float b8 = 2.0f; + const float b9 = 2.53125f; + const float b10 = 3.0f; + const float b11 = 3.484375f; + const float b12 = 4.703125f; + const float b13 = 6.265625f; + const float b14 = 7.84375f; + const float b15 = 9.421875f; + const float b16 = 10.984375f; + const float b17 = 12.546875f; + + float ret; + + if (x <= b17) { + // Ty to maintain relative accuracy here + + USE_TABLE(float, p, M32_Y0); + float ch, cl; + + if (x < b8) { + if (x < b4) { + if (x < b0) { + ch = 0.0f; + cl = 0.0f; + } else if (x < b1) { + ch = 0x1.4p-2f; + cl = 0.0f; + p += 1*9; + } else if (x < b2) { + ch = 0x1.cp-2f; + cl = 0.0f; + p += 2*9; + } else if (x < b3) { + ch = 0x1.2p-1f; + cl = 0.0f; + p += 3*9; + } else { + ch = 0x1.6p-1f; + cl = 0.0f; + p += 4*9; + } + } else { + if (x < b5) { + ch = 0x1.c982ecp-1f; + cl = -0x1.cafa06p-27f; + p += 5*9; + } else if (x < b6) { + ch = 0x1.p+0f; + cl = 0.0f; + p += 6*9; + } else if (x < b7) { + ch = 0x1.4p+0f; + cl = 0.0f; + p += 7*9; + } else { + ch = 0x1.ap+0f; + cl = 0.0f; + p += 8*9; + } + } + } else { + if (x < b13) { + if (x < b9) { + ch = 0x1.193beep+1f; + cl = -0x1.6401b8p-24f; + p += 9*9; + } else if (x < b10) { + ch = 0x1.44p+1f; + cl = 0.0f; + p += 10*9; + } else if (x < b11) { + ch = 0x1.8p+1f; + cl = 0.0f; + p += 11*9; + } else if (x < b12) { + ch = 0x1.fa9534p+1f; + cl = 0x1.b30ad4p-24f; + p += 12*9; + } else { + ch = 0x1.5b7fe4p+2f; + cl = 0x1.d0f606p-23f; + p += 13*9; + } + } else { + if (x < b14) { + ch = 0x1.c581dcp+2f; + cl = 0x1.39c84p-24f; + p += 14*9; + } else if (x < b15) { + ch = 0x1.13127ap+3f; + cl = 0x1.cc2d36p-22f; + p += 15*9; + } else if (x < b16) { + ch = 0x1.471d74p+3f; + cl = -0x1.4b7056p-22f; + p += 16*9; + } else { + ch = 0x1.77f914p+3f; + cl = -0x1.caf37ep-23f; + p += 17*9; + } + } + } + + ret = 0.0f; + if (x < b0) { + ret = 0x1.45f306p-1f * MATH_MANGLE(j0)(x) * MATH_MANGLE(log)(x); + x = x*x; + } + + x = x - ch - cl; + ret += MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, MATH_MAD(x, + p[8], p[7]), p[6]), p[5]), p[4]), + p[3]), p[2]), p[1]), p[0]); + } else { + float r = MATH_RCP(x); + float r2 = r*r; + float p = MATH_PRIVATE(bp0)(r2) * r; + ret = 0x1.988454p-1f * BUILTIN_AMDGPU_RSQRT_F32(x) * MATH_PRIVATE(ba0)(r2) * MATH_PRIVATE(sinb)(x, 0, p); + ret = x == PINF_F32 ? 0.0f : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/y0H.cl b/amd/device-libs/ocml/src/y0H.cl new file mode 100644 index 0000000000000..7efb0af427190 --- /dev/null +++ b/amd/device-libs/ocml/src/y0H.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +UGEN(y0) + +CONSTATTR half +MATH_MANGLE(y0)(half x) +{ + return (half)MATH_UPMANGLE(y0)((float)x); +} + diff --git a/amd/device-libs/ocml/src/y1D.cl b/amd/device-libs/ocml/src/y1D.cl new file mode 100644 index 0000000000000..0665a3e3d44c4 --- /dev/null +++ b/amd/device-libs/ocml/src/y1D.cl @@ -0,0 +1,160 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathD.h" + +extern double MATH_PRIVATE(sinb)(double, int, double); +extern CONSTATTR double MATH_PRIVATE(bp1)(double); +extern CONSTATTR double MATH_PRIVATE(ba1)(double); + +CONSTATTR double +MATH_MANGLE(y1)(double x) +{ + const double b0 = 0.5; + const double b1 = 0.625; + const double b2 = 0.75; + const double b3 = 0.9375; + const double b4 = 1.21875; + const double b5 = 1.53125; + const double b6 = 1.84375; + const double b7 = 2.078125; + const double b8 = 2.3125; + const double b9 = 2.734375; + const double b10 = 3.15625; + const double b11 = 4.203125; + const double b12 = 4.6875; + const double b13 = 6.1875; + const double b14 = 7.76953125; + const double b15 = 9.359375; + const double b16 = 10.9375; + const double b17 = 12.5625; + + double ret; + + if (x <= b17) { + // Ty to maintain relative accuracy here + + USE_TABLE(double, p, M64_Y1); + double ch, cl; + + if (x < b8) { + if (x < b4) { + if (x < b0) { + ch = 0.0; + cl = 0.0; + p += 0*15; + } else if (x < b1) { + ch = 0x1.0p-1; + cl = 0.0; + p += 1*15; + } else if (x < b2) { + ch = 0x1.4p-1; + cl = 0.0; + p += 2*15; + } else if (x < b3) { + ch = 0x1.8p-1; + cl = 0.0; + p += 3*15; + } else { + ch = 0x1.ep-1; + cl = 0.0; + p += 4*15; + } + } else { + if (x < b5) { + ch = 0x1.38p+0; + cl = 0.0; + p += 5*15; + } else if (x < b6) { + ch = 0x1.88p+0; + cl = 0.0; + p += 6*15; + } else if (x < b7) { + ch = 0x1.d8p+0; + cl = 0.0; + p += 7*15; + } else { + ch = 0x1.193bed4dff243p+1; + cl = -0x1.bd1e50d219bfdp-55; + p += 8*15; + } + } + } else { + if (x < b13) { + if (x < b9) { + ch = 0x1.28p+1; + cl = 0.0; + p += 9*15; + } else if (x < b10) { + ch = 0x1.5ep+1; + cl = 0.0; + p += 10*15; + } else if (x < b11) { + ch = 0x1.d76d4affba175p+1; + cl = 0x1.3bac0714e4129p-58; + p += 11*15; + } else if (x < b12) { + ch = 0x1.0dp+2; + cl = 0.0; + p += 12*15; + } else { + ch = 0x1.5b7fe4e87b02ep+2; + cl = 0x1.dfe7bac228e8cp-52; + p += 13*15; + } + } else { + if (x < b14) { + ch = 0x1.bc41890588553p+2; + cl = 0x1.7960b6b1c46acp-53; + p += 14*15; + } else if (x < b15) { + ch = 0x1.13127ae6169b4p+3; + cl = 0x1.479cc068d9046p-52; + p += 15*15; + } else if (x < b16) { + ch = 0x1.43f2ee51e8c7ep+3; + cl = 0x1.8f4ba5d68e44p-51; + p += 16*15; + } else { + ch = 0x1.77f9138d43206p+3; + cl = 0x1.0fc786ce0608p-55; + p += 17*15; + } + } + } + + double x2 = x*x; + double xs = x - ch - cl; + double t = x < b0 ? x2 : xs; + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, + p[14], p[13]), p[12]), + p[11]), p[10]), p[9]), p[8]), + p[7]), p[6]), p[5]), p[4]), + p[3]), p[2]), p[1]), p[0]); + + if (x < b0) { + const double twobypi = 0x1.45f306dc9c883p-1; + if (x < 0x1.0p-33) + ret = MATH_DIV(-twobypi, BUILTIN_ABS_F64(x)); + else + ret = MATH_MAD(ret, x, twobypi*(MATH_MANGLE(j1)(x) * MATH_MANGLE(log)(x) - MATH_RCP(x))); + ret = x < 0.0 ? QNAN_F64 : ret; + } + } else { + double r = MATH_RCP(x); + double r2 = r*r; + double p = MATH_PRIVATE(bp1)(r2) * r; + ret = 0x1.9884533d43651p-1 * MATH_FAST_SQRT(r) * MATH_PRIVATE(ba1)(r2) * MATH_PRIVATE(sinb)(x, 1, p); + ret = x == PINF_F64 ? 0.0 : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/y1F.cl b/amd/device-libs/ocml/src/y1F.cl new file mode 100644 index 0000000000000..2261b0163d72b --- /dev/null +++ b/amd/device-libs/ocml/src/y1F.cl @@ -0,0 +1,157 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathF.h" + +extern float MATH_PRIVATE(sinb)(float, int, float); +extern CONSTATTR float MATH_PRIVATE(bp1)(float); +extern CONSTATTR float MATH_PRIVATE(ba1)(float); + +CONSTATTR float +MATH_MANGLE(y1)(float x) +{ + const float b0 = 0.5f; + const float b1 = 0.625f; + const float b2 = 0.75f; + const float b3 = 0.9375f; + const float b4 = 1.21875f; + const float b5 = 1.53125f; + const float b6 = 1.84375f; + const float b7 = 2.078125f; + const float b8 = 2.3125f; + const float b9 = 2.734375f; + const float b10 = 3.15625f; + const float b11 = 4.203125f; + const float b12 = 4.6875f; + const float b13 = 6.1875f; + const float b14 = 7.76953125f; + const float b15 = 9.359375f; + const float b16 = 10.9375f; + const float b17 = 12.5625f; + + float ret; + + if (x <= b17) { + // Ty to maintain relative accuracy here + + USE_TABLE(float, p, M32_Y1); + float ch, cl; + + if (x < b8) { + if (x < b4) { + if (x < b0) { + ch = 0.0f; + cl = 0.0f; + p += 0*9; + } else if (x < b1) { + ch = 0x1.0p-1f; + cl = 0.0f; + p += 1*9; + } else if (x < b2) { + ch = 0x1.4p-1f; + cl = 0.0f; + p += 2*9; + } else if (x < b3) { + ch = 0x1.8p-1f; + cl = 0.0f; + p += 3*9; + } else { + ch = 0x1.ep-1f; + cl = 0.0f; + p += 4*9; + } + } else { + if (x < b5) { + ch = 0x1.38p+0f; + cl = 0.0f; + p += 5*9; + } else if (x < b6) { + ch = 0x1.88p+0f; + cl = 0.0f; + p += 6*9; + } else if (x < b7) { + ch = 0x1.d8p+0f; + cl = 0.0f; + p += 7*9; + } else { + ch = 0x1.193beep+1f; + cl = -0x1.6401b8p-24f; + p += 8*9; + } + } + } else { + if (x < b13) { + if (x < b9) { + ch = 0x1.28p+1f; + cl = 0.0f; + p += 9*9; + } else if (x < b10) { + ch = 0x1.5ep+1f; + cl = 0.0f; + p += 10*9; + } else if (x < b11) { + ch = 0x1.d76d4ap+1f; + cl = 0x1.ff742ep-24f; + p += 11*9; + } else if (x < b12) { + ch = 0x1.0dp+2f; + cl = 0.0f; + p += 12*9; + } else { + ch = 0x1.5b7fe4p+2f; + cl = 0x1.d0f606p-23f; + p += 13*9; + } + } else { + if (x < b14) { + ch = 0x1.bc418ap+2f; + cl = -0x1.f4ef56p-23f; + p += 14*9; + } else if (x < b15) { + ch = 0x1.13127ap+3f; + cl = 0x1.cc2d36p-22f; + p += 15*9; + } else if (x < b16) { + ch = 0x1.43f2eep+3f; + cl = 0x1.47a32p-23f; + p += 16*9; + } else { + ch = 0x1.77f914p+3f; + cl = -0x1.caf37ep-23f; + p += 17*9; + } + } + } + + float x2 = x*x; + float xs = x - ch - cl; + float t = x < b0 ? x2 : xs; + + ret = MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, MATH_MAD(t, + p[8], p[7]), p[6]), p[5]), p[4]), + p[3]), p[2]), p[1]), p[0]); + + if (x < b0) { + const float twobypi = 0x1.45f306p-1f; + if (x < 0x1.0p-20f) + ret = MATH_DIV(-twobypi, BUILTIN_ABS_F32(x)); + else + ret = MATH_MAD(ret, x, twobypi*(MATH_MANGLE(j1)(x) * MATH_MANGLE(log)(x) - MATH_RCP(x))); + ret = x < 0.0f ? QNAN_F32 : ret; + } + } else { + float r = MATH_RCP(x); + float r2 = r*r; + float p = MATH_PRIVATE(bp1)(r2) * r; + ret = 0x1.988454p-1f * BUILTIN_AMDGPU_RSQRT_F32(x) * MATH_PRIVATE(ba1)(r2) * MATH_PRIVATE(sinb)(x, 1, p); + ret = x == PINF_F32 ? 0.0f : ret; + } + + return ret; +} + diff --git a/amd/device-libs/ocml/src/y1H.cl b/amd/device-libs/ocml/src/y1H.cl new file mode 100644 index 0000000000000..a09ad9efb5be5 --- /dev/null +++ b/amd/device-libs/ocml/src/y1H.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "mathH.h" + +UGEN(y1) + +half +MATH_MANGLE(y1)(half x) +{ + return (half)MATH_UPMANGLE(y1)((float)x); +} + diff --git a/amd/device-libs/opencl/CMakeLists.txt b/amd/device-libs/opencl/CMakeLists.txt new file mode 100644 index 0000000000000..f39278d0bf2f9 --- /dev/null +++ b/amd/device-libs/opencl/CMakeLists.txt @@ -0,0 +1,33 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +file(GLOB cl_sources + ${CMAKE_CURRENT_SOURCE_DIR}/src/async/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/common/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/devenq/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/geometric/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/image/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/integer/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/math/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/media/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/misc/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/pipes/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/relational/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/subgroup/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/vldst/*.cl + ${CMAKE_CURRENT_SOURCE_DIR}/src/workgroup/*.cl + ) + +file(GLOB sources ${cl_sources}) + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/src/integer) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/src/workgroup) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../ocml/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../ockl/inc) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../oclc/inc) + +opencl_bc_lib(NAME opencl SOURCES ${sources}) diff --git a/amd/device-libs/opencl/src/async/awgcpy.cl b/amd/device-libs/opencl/src/async/awgcpy.cl new file mode 100644 index 0000000000000..bc12c51e3f277 --- /dev/null +++ b/amd/device-libs/opencl/src/async/awgcpy.cl @@ -0,0 +1,107 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _S(X) #X +#define S(X) _S(X) + +#define ATTR __attribute__((overloadable)) +#define IATTR +#define AATTR(A) __attribute__((overloadable, alias(A))) + +#define BODY(D,S) \ + size_t i; \ + size_t d = mul24(mul24((int)get_local_size(0), (int)get_local_size(1)), (int)get_local_size(2)); \ + for (i = get_local_linear_id(); istate is done and then start processing + // WAIT_WORK_GROUP currently == WAIT_PARENT + uint command_id; //!< [LWO/SRO] The unique command ID + uint child_counter; //!< [LRW/SRW] Counter that determine the launches of child kernels. + // It's incremented on the + // start and decremented on the finish. The parent kernel can be considered as + // done when the value is 0 and the state is DONE + + //!< [LWO/SRO] CL event for the current execution (clk_event_t) + union { + __global struct _AmdEvent *completion; + ulong completion_padding; + }; + + //!< [LWO/SRO] Pointer to the parent AQL wrapper (AmdAqlWrap*) + union { + __global struct _AmdAqlWrap *parent_wrap; + ulong parent_padding; + }; + + union { + __global size_t *wait_list; //!< [LRO/SRO] Pointer to an array of clk_event_t objects (64 bytes default) + ulong wait_list_padding; + }; + + uint wait_num; //!< [LWO/SRO] The number of cl_event_wait objects + uint reserved[5]; //!< For the future usage + hsa_kernel_dispatch_packet_t aql; //!< [LWO/SRO] AQL packet - 64 bytes AQL packet +} AmdAqlWrap; + +typedef struct _AmdEvent { + uint state; //!< [LRO/SRW] Event state: START, END, COMPLETE + uint counter; //!< [LRW] Event retain/release counter. 0 means the event is free + ulong timer[3]; //!< [LRO/SWO] Timer values for profiling for each state + ulong capture_info; //!< [LRW/SRO] Profiling capture info for CLK_PROFILING_COMMAND_EXEC_TIME +} AmdEvent; + +// XXX this needs to match workgroup/wg.h MAX_WAVES_PER_SIMD +#define CL_DEVICE_MAX_WORK_GROUP_SIZE 256 + +// ABI has implicit trailing arguments +#define NUM_IMPLICIT_ARGS (__oclc_ABI_version < 500 ? 7 : 32) + +static inline __global void * +get_printf_ptr(void) +{ + if (__oclc_ABI_version < 500) { + return (__global void *)(((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[3]); + } else { + return (__global void *)(((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[9]); + } +} + +static inline __global AmdVQueueHeader * +get_vqueue(void) +{ + if (__oclc_ABI_version < 500) { + return (__global AmdVQueueHeader *)(((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[4]); + } else { + return (__global AmdVQueueHeader *)(((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[13]); + } +} + +static inline __global AmdAqlWrap * +get_aql_wrap(void) +{ + if (__oclc_ABI_version < 500) { + return (__global AmdAqlWrap *)(((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[5]); + } else { + return (__global AmdAqlWrap *)(((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[14]); + } +} + +static inline size_t +get_bases(void) +{ + return ((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[24]; +} + +static inline size_t +get_hsa_queue(void) +{ + return ((__constant size_t *)__builtin_amdgcn_implicitarg_ptr())[25]; +} + +// reserve a slot in a bitmask controlled resource +// n is the number of slots +static inline int +reserve_slot(__global uint * restrict mask, uint n, uint mask_groups) +{ + n >>= 5; + uint j, k, v, vv, z; + + // Spread the starting points + k = (get_local_linear_id() * mask_groups) % n; + + // Make only one pass + for (j=0;j> 5)); + uint v, vv; + + v = atomic_load_explicit(p, memory_order_relaxed, memory_scope_device); + for (;;) { + vv = v & b; + if (atomic_compare_exchange_strong_explicit(p, &v, vv, memory_order_relaxed, memory_order_relaxed, memory_scope_device)) + break; + } +} + +static inline uint +align_up(uint start, uint align) +{ + return (start + align - 1U) & -align; +} + diff --git a/amd/device-libs/opencl/src/devenq/enqueue.cl b/amd/device-libs/opencl/src/devenq/enqueue.cl new file mode 100644 index 0000000000000..756f98d29b488 --- /dev/null +++ b/amd/device-libs/opencl/src/devenq/enqueue.cl @@ -0,0 +1,542 @@ + +#include "devenq.h" + +#define LSIZE_LIMIT 65536U +#define LOCAL_ALIGN 16 + +struct rtinfo { + __global char* kernel_object; + uint private_segment_size; + uint group_segment_size; +}; + +static inline void +copy_captured_context(__global void * restrict d, void * restrict s, uint size, uint align) +{ + if (align == 8) { + __global ulong * restrict d8 = (__global ulong * restrict)d; + ulong * restrict s8 = (ulong * restrict)s; + uint n = size / align; + uint r = size % align; + for (uint i=0; i 3) { + *(__global uint * restrict)dd = *(uint * restrict)ss; + dd += 4; + ss += 4; + r -= 4; + } + if (r > 1) { + *(__global ushort * restrict)dd = *(ushort * restrict)ss; + dd += 2; + ss += 2; + r -= 2; + } + if (r > 0) { + *dd = *ss; + } + } + } else if (align >= 16) { + __global uint4 * restrict d16 = (__global uint4 * restrict)d; + uint4 * restrict s16 = (uint4 * restrict)s; + uint n = size / 16; + uint r = size % 16; + for (uint i=0; i 7) { + *(__global ulong * restrict)dd = *(ulong * restrict)ss; + dd += 8; + ss += 8; + r -= 8; + } + if (r > 3) { + *(__global uint * restrict)dd = *(uint * restrict)ss; + dd += 4; + ss += 4; + r -= 4; + } + if (r > 1) { + *(__global ushort * restrict)dd = *(ushort * restrict)ss; + dd += 2; + ss += 2; + r -= 2; + } + if (r > 0) { + *dd = *ss; + } + } + } else if (align == 4) { + __global uint * restrict d4 = (__global uint * restrict)d; + uint * restrict s4 = (uint * restrict)s; + uint n = size / align; + uint r = size % align; + for (uint i=0; i 1) { + *(__global ushort * restrict)dd = *(ushort * restrict)ss; + dd += 2; + ss += 2; + r -= 2; + } + if (r > 0) { + *dd = *ss; + } + } + } else { + __global char * restrict d1 = (__global char * restrict)d; + char * restrict s1 = (char * restrict)s; + for (uint i=0; icounter, (uint)1, memory_order_relaxed, memory_scope_device); + dst[i] = src[i]; + } +} + +__attribute__((overloadable, always_inline, const)) queue_t +get_default_queue(void) +{ + return __builtin_astype(get_vqueue(), queue_t); +} + +__attribute__((overloadable)) int +enqueue_marker(queue_t q, uint nwl, const clk_event_t *wl, clk_event_t *ce) +{ + __global AmdVQueueHeader *vq = __builtin_astype(q, __global AmdVQueueHeader *); + if (nwl > vq->wait_size) + return CLK_ENQUEUE_FAILURE; + + // Get a wrap slot + __global uint *amask = (__global uint *)vq->aql_slot_mask; + int ai = reserve_slot(amask, vq->aql_slot_num, vq->mask_groups); + if (ai < 0) + return CLK_ENQUEUE_FAILURE; + + // Get a return event slot + __global uint *emask = (__global uint *)vq->event_slot_mask; + int ei = reserve_slot(emask, vq->event_slot_num, 1); + if (ei < 0) { + release_slot(amask, ai); + return CLK_ENQUEUE_FAILURE; + } + + // Initialize return event + __global AmdEvent *ev = (__global AmdEvent *)vq->event_slots + ei; + ev->state = CL_SUBMITTED; + ev->counter = 2; + ev->capture_info = 0; + + // Initialize wrap + __global AmdAqlWrap *me = get_aql_wrap(); + __global AmdAqlWrap *aw = (__global AmdAqlWrap *)(vq + 1) + ai; + + aw->enqueue_flags = CLK_ENQUEUE_FLAGS_NO_WAIT; + aw->command_id = atomic_fetch_add_explicit((__global atomic_uint *)&vq->command_counter, (uint)1, memory_order_relaxed, memory_scope_device); + aw->child_counter = 0; + aw->completion = ev; + aw->parent_wrap = me; + + if (nwl > 0) + copy_retain_waitlist((__global size_t *)aw->wait_list, (const size_t *)wl, nwl); + + aw->wait_num = nwl; + + // A marker is never enqueued so ignore displatch packet + + // Tell the scheduler + atomic_fetch_add_explicit((__global atomic_uint *)&me->child_counter, (uint)1, memory_order_relaxed, memory_scope_device); + atomic_store_explicit((__global atomic_uint *)&aw->state, AQL_WRAP_MARKER, memory_order_release, memory_scope_device); + + *ce = __builtin_astype(ev, clk_event_t); + return 0; +} + +int +__enqueue_kernel_basic(queue_t q, kernel_enqueue_flags_t f, const ndrange_t r, void *block, void *capture) +{ + uint csize = ((uint *)capture)[0]; + uint calign = ((uint *)capture)[1]; + __global AmdVQueueHeader *vq = __builtin_astype(q, __global AmdVQueueHeader *); + + if (align_up(csize, sizeof(size_t)) + NUM_IMPLICIT_ARGS*sizeof(size_t) > vq->arg_size || + mul24(mul24((uint)r.localWorkSize[0], (uint)r.localWorkSize[1]), (uint)r.localWorkSize[2]) > CL_DEVICE_MAX_WORK_GROUP_SIZE) + return CLK_ENQUEUE_FAILURE; + + // Get a queue slot + __global uint *amask = (__global uint *)vq->aql_slot_mask; + int ai = reserve_slot(amask, vq->aql_slot_num, vq->mask_groups); + if (ai < 0) + return CLK_ENQUEUE_FAILURE; + + __global AmdAqlWrap *aw = (__global AmdAqlWrap *)(vq + 1) + ai; + + // Set up kernarg + copy_captured_context(aw->aql.kernarg_address, capture, csize, calign); + __global size_t *implicit = (__global size_t *)((__global char *)aw->aql.kernarg_address + align_up(csize, sizeof(size_t))); + if (__oclc_ABI_version < 500) { + implicit[0] = r.globalWorkOffset[0]; + implicit[1] = r.globalWorkOffset[1]; + implicit[2] = r.globalWorkOffset[2]; + implicit[3] = (size_t)get_printf_ptr(); + implicit[4] = (size_t)get_vqueue(); + implicit[5] = (size_t)aw; + } else { + implicit[0] = ((size_t)((uint)r.globalWorkSize[0] / (ushort)r.localWorkSize[0])) | + ((size_t)((uint)r.globalWorkSize[1] / (ushort)r.localWorkSize[1]) << 32); + implicit[1] = ((size_t)((uint)r.globalWorkSize[2] / (ushort)r.localWorkSize[2])) | + ((size_t)(ushort)r.localWorkSize[0] << 32) | + ((size_t)(ushort)r.localWorkSize[1] << 48); + implicit[2] = ((size_t)(ushort)r.localWorkSize[2]) | + ((size_t)((uint)r.globalWorkSize[0] % (ushort)r.localWorkSize[0]) << 16) | + ((size_t)((uint)r.globalWorkSize[1] % (ushort)r.localWorkSize[1]) << 32) | + ((size_t)((uint)r.globalWorkSize[2] % (ushort)r.localWorkSize[2]) << 48); + implicit[5] = r.globalWorkOffset[0]; + implicit[6] = r.globalWorkOffset[1]; + implicit[7] = r.globalWorkOffset[2]; + implicit[8] = (size_t)(ushort)r.workDimension; + implicit[9] = (size_t)get_printf_ptr(); + implicit[13] = (size_t)get_vqueue(); + implicit[14] = (size_t)aw; + implicit[24] = get_bases(); + implicit[25] = get_hsa_queue(); + } + + const __global struct rtinfo *rti = (const __global struct rtinfo *)block; + + __global AmdAqlWrap *me = get_aql_wrap(); + + aw->enqueue_flags = f; + aw->command_id = atomic_fetch_add_explicit((__global atomic_uint *)&vq->command_counter, (uint)1, memory_order_relaxed, memory_scope_device); + aw->completion = 0UL; + aw->parent_wrap = me; + aw->wait_num = 0; + aw->aql.header = (0x1 << 11) | (0x1 << 9) |(0x0 << 8) | (0x2 << 0); + aw->aql.setup = r.workDimension; + aw->aql.workgroup_size_x = (ushort)r.localWorkSize[0]; + aw->aql.workgroup_size_y = (ushort)r.localWorkSize[1]; + aw->aql.workgroup_size_z = (ushort)r.localWorkSize[2]; + aw->aql.grid_size_x = (uint)r.globalWorkSize[0]; + aw->aql.grid_size_y = (uint)r.globalWorkSize[1]; + aw->aql.grid_size_z = (uint)r.globalWorkSize[2]; + aw->aql.private_segment_size = rti->private_segment_size; + aw->aql.group_segment_size = rti->group_segment_size; + aw->aql.kernel_object = rti->kernel_object; + aw->aql.completion_signal.handle = 0; + + atomic_fetch_add_explicit((__global atomic_uint *)&me->child_counter, (uint)1, memory_order_relaxed, memory_scope_device); + atomic_store_explicit((__global atomic_uint *)&aw->state, AQL_WRAP_READY, memory_order_release, memory_scope_device); + return 0; +} + +int +__enqueue_kernel_basic_events(queue_t q, kernel_enqueue_flags_t f, const ndrange_t r, uint nwl, const clk_event_t *wl, clk_event_t *ce, void *block, void *capture) +{ + uint csize = ((uint *)capture)[0]; + uint calign = ((uint *)capture)[1]; + __global AmdVQueueHeader *vq = __builtin_astype(q, __global AmdVQueueHeader *); + + if (align_up(csize, sizeof(size_t)) + NUM_IMPLICIT_ARGS*sizeof(size_t) > vq->arg_size || + nwl > vq->wait_size || + mul24(mul24((uint)r.localWorkSize[0], (uint)r.localWorkSize[1]), (uint)r.localWorkSize[2]) > CL_DEVICE_MAX_WORK_GROUP_SIZE) + return CLK_ENQUEUE_FAILURE; + + __global uint *amask = (__global uint *)vq->aql_slot_mask; + int ai = reserve_slot(amask, vq->aql_slot_num, vq->mask_groups); + if (ai < 0) + return CLK_ENQUEUE_FAILURE; + + __global AmdEvent *ev = (__global AmdEvent *)NULL; + if (ce) { + // Get a completion event slot + __global uint *emask = (__global uint *)vq->event_slot_mask; + int ei = reserve_slot(emask, vq->event_slot_num, 1); + if (ei < 0) { + release_slot(amask, ai); + return CLK_ENQUEUE_FAILURE; + } + + // Initialize completion event + ev = (__global AmdEvent *)vq->event_slots + ei; + ev->state = CL_SUBMITTED; + ev->counter = 2; + ev->capture_info = 0; + *ce = __builtin_astype(ev, clk_event_t); + } + + __global AmdAqlWrap *aw = (__global AmdAqlWrap *)(vq + 1) + ai; + + // Set up kernarg + copy_captured_context(aw->aql.kernarg_address, capture, csize, calign); + __global size_t *implicit = (__global size_t *)((__global char *)aw->aql.kernarg_address + align_up(csize, sizeof(size_t))); + if (__oclc_ABI_version < 500) { + implicit[0] = r.globalWorkOffset[0]; + implicit[1] = r.globalWorkOffset[1]; + implicit[2] = r.globalWorkOffset[2]; + implicit[3] = (size_t)get_printf_ptr(); + implicit[4] = (size_t)get_vqueue(); + implicit[5] = (size_t)aw; + } else { + implicit[0] = ((size_t)((uint)r.globalWorkSize[0] / (ushort)r.localWorkSize[0])) | + ((size_t)((uint)r.globalWorkSize[1] / (ushort)r.localWorkSize[1]) << 32); + implicit[1] = ((size_t)((uint)r.globalWorkSize[2] / (ushort)r.localWorkSize[2])) | + ((size_t)(ushort)r.localWorkSize[0] << 32) | + ((size_t)(ushort)r.localWorkSize[1] << 48); + implicit[2] = ((size_t)(ushort)r.localWorkSize[2]) | + ((size_t)((uint)r.globalWorkSize[0] % (ushort)r.localWorkSize[0]) << 16) | + ((size_t)((uint)r.globalWorkSize[1] % (ushort)r.localWorkSize[1]) << 32) | + ((size_t)((uint)r.globalWorkSize[2] % (ushort)r.localWorkSize[2]) << 48); + implicit[5] = r.globalWorkOffset[0]; + implicit[6] = r.globalWorkOffset[1]; + implicit[7] = r.globalWorkOffset[2]; + implicit[8] = (size_t)(ushort)r.workDimension; + implicit[9] = (size_t)get_printf_ptr(); + implicit[13] = (size_t)get_vqueue(); + implicit[14] = (size_t)aw; + implicit[24] = get_bases(); + implicit[25] = get_hsa_queue(); + } + + const __global struct rtinfo *rti = (const __global struct rtinfo *)block; + + __global AmdAqlWrap *me = get_aql_wrap(); + + aw->enqueue_flags = f; + aw->command_id = atomic_fetch_add_explicit((__global atomic_uint *)&vq->command_counter, (uint)1, memory_order_relaxed, memory_scope_device); + aw->completion = ev; + aw->parent_wrap = me; + if (nwl > 0) + copy_retain_waitlist(aw->wait_list, (const size_t *)wl, nwl); + aw->wait_num = nwl; + aw->aql.header = (ushort)((0x1 << 11) | (0x1 << 9) |(0x0 << 8) | (0x2 << 0)); + aw->aql.setup = (ushort)r.workDimension; + aw->aql.workgroup_size_x = (ushort)r.localWorkSize[0]; + aw->aql.workgroup_size_y = (ushort)r.localWorkSize[1]; + aw->aql.workgroup_size_z = (ushort)r.localWorkSize[2]; + aw->aql.grid_size_x = (uint)r.globalWorkSize[0]; + aw->aql.grid_size_y = (uint)r.globalWorkSize[1]; + aw->aql.grid_size_z = (uint)r.globalWorkSize[2]; + aw->aql.private_segment_size = rti->private_segment_size; + aw->aql.group_segment_size = rti->group_segment_size; + aw->aql.kernel_object = rti->kernel_object; + aw->aql.completion_signal.handle = 0; + + atomic_fetch_add_explicit((__global atomic_uint *)&me->child_counter, (uint)1, memory_order_relaxed, memory_scope_device); + atomic_store_explicit((__global atomic_uint *)&aw->state, AQL_WRAP_READY, memory_order_release, memory_scope_device); + return 0; +} + +int +__enqueue_kernel_varargs(queue_t q, kernel_enqueue_flags_t f, const ndrange_t r, void *block, void *capture, uint nl, __private size_t *ll) +{ + uint csize = ((uint *)capture)[0]; + uint calign = ((uint *)capture)[1]; + + const __global struct rtinfo *rti = (const __global struct rtinfo *)block; + uint lo = rti->group_segment_size; + for (uint il=0; il LSIZE_LIMIT || + align_up(align_up(csize, sizeof(uint)) + nl*sizeof(uint), sizeof(size_t)) + NUM_IMPLICIT_ARGS*sizeof(size_t) > vq->arg_size || + mul24(mul24((uint)r.localWorkSize[0], (uint)r.localWorkSize[1]), (uint)r.localWorkSize[2]) > CL_DEVICE_MAX_WORK_GROUP_SIZE) + return CLK_ENQUEUE_FAILURE; + + // Get a queue slot + __global uint *amask = (__global uint *)vq->aql_slot_mask; + int ai = reserve_slot(amask, vq->aql_slot_num, vq->mask_groups); + if (ai < 0) + return CLK_ENQUEUE_FAILURE; + + __global AmdAqlWrap *aw = (__global AmdAqlWrap *)(vq + 1) + ai; + + // Set up kernarg + copy_captured_context(aw->aql.kernarg_address, capture, csize, calign); + + __global uint *la = (__global uint *)((__global char *)aw->aql.kernarg_address + align_up(csize, sizeof(uint))); + lo = rti->group_segment_size; + for (uint il=0; ilaql.kernarg_address + + align_up(align_up(csize, sizeof(uint)) + nl*sizeof(uint), sizeof(size_t))); + if (__oclc_ABI_version < 500) { + implicit[0] = r.globalWorkOffset[0]; + implicit[1] = r.globalWorkOffset[1]; + implicit[2] = r.globalWorkOffset[2]; + implicit[3] = (size_t)get_printf_ptr(); + implicit[4] = (size_t)get_vqueue(); + implicit[5] = (size_t)aw; + } else { + implicit[0] = ((size_t)((uint)r.globalWorkSize[0] / (ushort)r.localWorkSize[0])) | + ((size_t)((uint)r.globalWorkSize[1] / (ushort)r.localWorkSize[1]) << 32); + implicit[1] = ((size_t)((uint)r.globalWorkSize[2] / (ushort)r.localWorkSize[2])) | + ((size_t)(ushort)r.localWorkSize[0] << 32) | + ((size_t)(ushort)r.localWorkSize[1] << 48); + implicit[2] = ((size_t)(ushort)r.localWorkSize[2]) | + ((size_t)((uint)r.globalWorkSize[0] % (ushort)r.localWorkSize[0]) << 16) | + ((size_t)((uint)r.globalWorkSize[1] % (ushort)r.localWorkSize[1]) << 32) | + ((size_t)((uint)r.globalWorkSize[2] % (ushort)r.localWorkSize[2]) << 48); + implicit[5] = r.globalWorkOffset[0]; + implicit[6] = r.globalWorkOffset[1]; + implicit[7] = r.globalWorkOffset[2]; + implicit[8] = (size_t)(ushort)r.workDimension; + implicit[9] = (size_t)get_printf_ptr(); + implicit[13] = (size_t)get_vqueue(); + implicit[14] = (size_t)aw; + implicit[24] = get_bases(); + implicit[25] = get_hsa_queue(); + } + + __global AmdAqlWrap *me = get_aql_wrap(); + + aw->enqueue_flags = f; + aw->command_id = atomic_fetch_add_explicit((__global atomic_uint *)&vq->command_counter, (uint)1, memory_order_relaxed, memory_scope_device); + aw->completion = 0UL; + aw->parent_wrap = me; + aw->wait_num = 0; + aw->aql.header = (0x1 << 11) | (0x1 << 9) |(0x0 << 8) | (0x2 << 0); + aw->aql.setup = r.workDimension; + aw->aql.workgroup_size_x = (ushort)r.localWorkSize[0]; + aw->aql.workgroup_size_y = (ushort)r.localWorkSize[1]; + aw->aql.workgroup_size_z = (ushort)r.localWorkSize[2]; + aw->aql.grid_size_x = (uint)r.globalWorkSize[0]; + aw->aql.grid_size_y = (uint)r.globalWorkSize[1]; + aw->aql.grid_size_z = (uint)r.globalWorkSize[2]; + aw->aql.private_segment_size = rti->private_segment_size; + aw->aql.group_segment_size = lo; + aw->aql.kernel_object = rti->kernel_object; + aw->aql.completion_signal.handle = 0; + + atomic_fetch_add_explicit((__global atomic_uint *)&me->child_counter, (uint)1, memory_order_relaxed, memory_scope_device); + atomic_store_explicit((__global atomic_uint *)&aw->state, AQL_WRAP_READY, memory_order_release, memory_scope_device); + return 0; +} + + +int +__enqueue_kernel_events_varargs(queue_t q, kernel_enqueue_flags_t f, const ndrange_t r, int nwl, const clk_event_t *wl, clk_event_t *ce, void *block, void *capture, uint nl, __private size_t *ll) +{ + uint csize = ((uint *)capture)[0]; + uint calign = ((uint *)capture)[1]; + + const __global struct rtinfo *rti = (const __global struct rtinfo *)block; + uint lo = rti->group_segment_size; + for (uint il=0; il LSIZE_LIMIT || + nwl > vq->wait_size || + align_up(align_up(csize, sizeof(uint)) + nl*sizeof(uint), sizeof(size_t)) + NUM_IMPLICIT_ARGS*sizeof(size_t) > vq->arg_size || + mul24(mul24((uint)r.localWorkSize[0], (uint)r.localWorkSize[1]), (uint)r.localWorkSize[2]) > CL_DEVICE_MAX_WORK_GROUP_SIZE) + return CLK_ENQUEUE_FAILURE; + + // Get a queue slot + __global uint *amask = (__global uint *)vq->aql_slot_mask; + int ai = reserve_slot(amask, vq->aql_slot_num, vq->mask_groups); + if (ai < 0) + return CLK_ENQUEUE_FAILURE; + + __global AmdEvent *ev = (__global AmdEvent *)NULL; + if (ce) { + // Get a completion event slot + __global uint *emask = (__global uint *)vq->event_slot_mask; + int ei = reserve_slot(emask, vq->event_slot_num, 1); + if (ei < 0) { + release_slot(amask, ai); + return CLK_ENQUEUE_FAILURE; + } + + // Initialize completion event + ev = (__global AmdEvent *)vq->event_slots + ei; + ev->state = CL_SUBMITTED; + ev->counter = 2; + ev->capture_info = 0; + *ce = __builtin_astype(ev, clk_event_t); + } + + __global AmdAqlWrap *aw = (__global AmdAqlWrap *)(vq + 1) + ai; + + // Set up kernarg + copy_captured_context(aw->aql.kernarg_address, capture, csize, calign); + + __global uint *la = (__global uint *)((__global char *)aw->aql.kernarg_address + align_up(csize, sizeof(uint))); + lo = rti->group_segment_size; + for (uint il=0; ilaql.kernarg_address + + align_up(align_up(csize, sizeof(uint)) + nl*sizeof(uint), sizeof(size_t))); + if (__oclc_ABI_version < 500) { + implicit[0] = r.globalWorkOffset[0]; + implicit[1] = r.globalWorkOffset[1]; + implicit[2] = r.globalWorkOffset[2]; + implicit[3] = (size_t)get_printf_ptr(); + implicit[4] = (size_t)get_vqueue(); + implicit[5] = (size_t)aw; + } else { + implicit[0] = ((size_t)((uint)r.globalWorkSize[0] / (ushort)r.localWorkSize[0])) | + ((size_t)((uint)r.globalWorkSize[1] / (ushort)r.localWorkSize[1]) << 32); + implicit[1] = ((size_t)((uint)r.globalWorkSize[2] / (ushort)r.localWorkSize[2])) | + ((size_t)(ushort)r.localWorkSize[0] << 32) | + ((size_t)(ushort)r.localWorkSize[1] << 48); + implicit[2] = ((size_t)(ushort)r.localWorkSize[2]) | + ((size_t)((uint)r.globalWorkSize[0] % (ushort)r.localWorkSize[0]) << 16) | + ((size_t)((uint)r.globalWorkSize[1] % (ushort)r.localWorkSize[1]) << 32) | + ((size_t)((uint)r.globalWorkSize[2] % (ushort)r.localWorkSize[2]) << 48); + implicit[5] = r.globalWorkOffset[0]; + implicit[6] = r.globalWorkOffset[1]; + implicit[7] = r.globalWorkOffset[2]; + implicit[8] = (size_t)(ushort)r.workDimension; + implicit[9] = (size_t)get_printf_ptr(); + implicit[13] = (size_t)get_vqueue(); + implicit[14] = (size_t)aw; + } + + __global AmdAqlWrap *me = get_aql_wrap(); + + aw->enqueue_flags = f; + aw->command_id = atomic_fetch_add_explicit((__global atomic_uint *)&vq->command_counter, (uint)1, memory_order_relaxed, memory_scope_device); + aw->completion = ev; + aw->parent_wrap = me; + if (nwl > 0) + copy_retain_waitlist((__global size_t *)aw->wait_list, (const size_t *)wl, nwl); + aw->wait_num = nwl; + aw->aql.header = (0x1 << 11) | (0x1 << 9) |(0x0 << 8) | (0x2 << 0); + aw->aql.setup = r.workDimension; + aw->aql.workgroup_size_x = (ushort)r.localWorkSize[0]; + aw->aql.workgroup_size_y = (ushort)r.localWorkSize[1]; + aw->aql.workgroup_size_z = (ushort)r.localWorkSize[2]; + aw->aql.grid_size_x = (uint)r.globalWorkSize[0]; + aw->aql.grid_size_y = (uint)r.globalWorkSize[1]; + aw->aql.grid_size_z = (uint)r.globalWorkSize[2]; + aw->aql.private_segment_size = rti->private_segment_size; + aw->aql.group_segment_size = lo; + aw->aql.kernel_object = rti->kernel_object; + aw->aql.completion_signal.handle = 0; + + atomic_fetch_add_explicit((__global atomic_uint *)&me->child_counter, (uint)1, memory_order_relaxed, memory_scope_device); + atomic_store_explicit((__global atomic_uint *)&aw->state, AQL_WRAP_READY, memory_order_release, memory_scope_device); + return 0; +} + diff --git a/amd/device-libs/opencl/src/devenq/events.cl b/amd/device-libs/opencl/src/devenq/events.cl new file mode 100644 index 0000000000000..98e87e1ee0aec --- /dev/null +++ b/amd/device-libs/opencl/src/devenq/events.cl @@ -0,0 +1,73 @@ + +#include "devenq.h" + +#define ATTR __attribute__((overloadable, always_inline)) + +ATTR void +retain_event(clk_event_t e) +{ + __global AmdEvent *ev = __builtin_astype(e, __global AmdEvent *); + atomic_fetch_add_explicit((__global atomic_uint *)&ev->counter, (uint)1, memory_order_relaxed, memory_scope_device); +} + +ATTR void +release_event(clk_event_t e) +{ + __global AmdEvent *ev = __builtin_astype(e, __global AmdEvent *); + uint c = atomic_fetch_sub_explicit((__global atomic_uint *)&ev->counter, (uint)1, memory_order_relaxed, memory_scope_device); + if (c == 1U) { + __global AmdVQueueHeader *vq = get_vqueue(); + __global uint *emask = (__global uint *)vq->event_slot_mask; + __global AmdEvent *eb = (__global AmdEvent *)vq->event_slots; + uint i = ev - eb; + release_slot(emask, i); + } +} + +ATTR clk_event_t +create_user_event(void) +{ + __global AmdVQueueHeader *vq = get_vqueue(); + __global uint *emask = (__global uint *)vq->event_slot_mask; + int i = reserve_slot(emask, vq->event_slot_num, 1); + + if (i >= 0) { + __global AmdEvent *ev = (__global AmdEvent *)vq->event_slots + i; + ev->state = CL_SUBMITTED; + ev->counter = 1; + ev->capture_info = 0; + return __builtin_astype(ev, clk_event_t); + } else + return __builtin_astype((ulong)0, clk_event_t); +} + +ATTR bool +is_valid_event(clk_event_t e) +{ + return __builtin_astype(e, ulong) != (ulong)0; +} + +ATTR void +set_user_event_status(clk_event_t e, int s) +{ + __global AmdEvent *ev = __builtin_astype(e, __global AmdEvent *); + atomic_store_explicit((__global atomic_uint *)&ev->state, (uint)s, memory_order_release, memory_scope_device); +} + +ATTR void +capture_event_profiling_info(clk_event_t e, clk_profiling_info n, __global void *p) +{ + // Currently the second argument must be CLK_PROFILING_COMMAND_EXEC_TIME + __global AmdEvent *ev = __builtin_astype(e, __global AmdEvent *); + + // Set the pointer now in case we're racing with the scheduler + atomic_store_explicit((__global atomic_ulong *)&ev->capture_info, (ulong)p, memory_order_relaxed, memory_scope_device); + + uint state = atomic_load_explicit((__global atomic_uint *)&ev->state, memory_order_acquire, memory_scope_device); + if (state == CL_COMPLETE) { + __global ulong *t = (__global ulong *)ev->timer; + ((__global ulong *)p)[0] = t[PROFILING_COMMAND_END] - t[PROFILING_COMMAND_START]; + ((__global ulong *)p)[1] = t[PROFILING_COMMAND_COMPLETE] - t[PROFILING_COMMAND_START]; + } +} + diff --git a/amd/device-libs/opencl/src/devenq/getkern.cl b/amd/device-libs/opencl/src/devenq/getkern.cl new file mode 100644 index 0000000000000..95427f13078f1 --- /dev/null +++ b/amd/device-libs/opencl/src/devenq/getkern.cl @@ -0,0 +1,20 @@ + +#include "devenq.h" + +__attribute__((always_inline, const)) uint +__get_kernel_work_group_size_impl(void *b, void *c) +{ + return (uint)CL_DEVICE_MAX_WORK_GROUP_SIZE; +} + +__attribute__((always_inline, const)) uint +__get_kernel_preferred_work_group_size_multiple_impl(void *b, void *c) +{ + return 64U; +} + +// 2.1 Reference card mentions +// uint get_kernel_sub_group_count_for_ndrange(ndrange_t, block); +// --> __get_kernel_sub_group_count_for_ndrange_impl(ndrange_t, void *, void *); +// uint get_kernel_max_sub_group_size_for_ndrange(ndrange_t, block); +// --> __get_kernel_max_sub_group_size_for_ndrange_impl(ndrange_t, void *, void *); diff --git a/amd/device-libs/opencl/src/devenq/ndrange.cl b/amd/device-libs/opencl/src/devenq/ndrange.cl new file mode 100644 index 0000000000000..bd2ed46fe2cea --- /dev/null +++ b/amd/device-libs/opencl/src/devenq/ndrange.cl @@ -0,0 +1,165 @@ + + +#include "devenq.h" + +#define ATTR __attribute__((overloadable, always_inline, const)) + +// 1D variants + +ATTR ndrange_t +ndrange_1D(size_t gws) +{ + ndrange_t ret; + ret.workDimension = 1; + ret.globalWorkOffset[0] = 0; + ret.globalWorkOffset[1] = 0; + ret.globalWorkOffset[2] = 0; + ret.globalWorkSize[0] = gws; + ret.globalWorkSize[1] = 1; + ret.globalWorkSize[2] = 1; + ret.localWorkSize[0] = min(gws, (size_t)64); + ret.localWorkSize[1] = 1; + ret.localWorkSize[2] = 1; + return ret; +} + +ATTR ndrange_t +ndrange_1D(size_t gws, size_t lws) +{ + ndrange_t ret; + ret.workDimension = 1; + ret.globalWorkOffset[0] = 0; + ret.globalWorkOffset[1] = 0; + ret.globalWorkOffset[2] = 0; + ret.globalWorkSize[0] = gws; + ret.globalWorkSize[1] = 1; + ret.globalWorkSize[2] = 1; + ret.localWorkSize[0] = lws; + ret.localWorkSize[1] = 1; + ret.localWorkSize[2] = 1; + return ret; +} + +ATTR ndrange_t +ndrange_1D(size_t goff, size_t gws, size_t lws) +{ + ndrange_t ret; + ret.workDimension = 1; + ret.globalWorkOffset[0] = goff; + ret.globalWorkOffset[1] = 0; + ret.globalWorkOffset[2] = 0; + ret.globalWorkSize[0] = gws; + ret.globalWorkSize[1] = 1; + ret.globalWorkSize[2] = 1; + ret.localWorkSize[0] = lws; + ret.localWorkSize[1] = 1; + ret.localWorkSize[2] = 1; + return ret; +} + +// 2D variants + +ATTR ndrange_t +ndrange_2D(const size_t gws[2]) +{ + ndrange_t ret; + ret.workDimension = 2; + ret.globalWorkOffset[0] = 0; + ret.globalWorkOffset[1] = 0; + ret.globalWorkOffset[2] = 0; + ret.globalWorkSize[0] = gws[0]; + ret.globalWorkSize[1] = gws[1]; + ret.globalWorkSize[2] = 1; + ret.localWorkSize[0] = min(gws[0], (size_t)8); + ret.localWorkSize[1] = min(gws[1], (size_t)8); + ret.localWorkSize[2] = 1; + return ret; +} + +ATTR ndrange_t +ndrange_2D(const size_t gws[2], const size_t lws[2]) +{ + ndrange_t ret; + ret.workDimension = 2; + ret.globalWorkOffset[0] = 0; + ret.globalWorkOffset[1] = 0; + ret.globalWorkOffset[2] = 0; + ret.globalWorkSize[0] = gws[0]; + ret.globalWorkSize[1] = gws[1]; + ret.globalWorkSize[2] = 1; + ret.localWorkSize[0] = lws[0]; + ret.localWorkSize[1] = lws[1]; + ret.localWorkSize[2] = 1; + return ret; +} + +ATTR ndrange_t +ndrange_2D(const size_t goff[2], const size_t gws[2], const size_t lws[2]) +{ + ndrange_t ret; + ret.workDimension = 2; + ret.globalWorkOffset[0] = goff[0]; + ret.globalWorkOffset[1] = goff[1]; + ret.globalWorkOffset[2] = 0; + ret.globalWorkSize[0] = gws[0]; + ret.globalWorkSize[1] = gws[1]; + ret.globalWorkSize[2] = 1; + ret.localWorkSize[0] = lws[0]; + ret.localWorkSize[1] = lws[1]; + ret.localWorkSize[2] = 1; + return ret; +} + +// 3D variants + +ATTR ndrange_t +ndrange_3D(const size_t gws[3]) +{ + ndrange_t ret; + ret.workDimension = 3; + ret.globalWorkOffset[0] = 0; + ret.globalWorkOffset[1] = 0; + ret.globalWorkOffset[2] = 0; + ret.globalWorkSize[0] = gws[0]; + ret.globalWorkSize[1] = gws[1]; + ret.globalWorkSize[2] = gws[2]; + ret.localWorkSize[0] = min(gws[0], (size_t)4); + ret.localWorkSize[1] = min(gws[1], (size_t)4); + ret.localWorkSize[2] = min(gws[2], (size_t)4); + return ret; +} + +ATTR ndrange_t +ndrange_3D(const size_t gws[3], const size_t lws[3]) +{ + ndrange_t ret; + ret.workDimension = 3; + ret.globalWorkOffset[0] = 0; + ret.globalWorkOffset[1] = 0; + ret.globalWorkOffset[2] = 0; + ret.globalWorkSize[0] = gws[0]; + ret.globalWorkSize[1] = gws[1]; + ret.globalWorkSize[2] = gws[2]; + ret.localWorkSize[0] = lws[0]; + ret.localWorkSize[1] = lws[1]; + ret.localWorkSize[2] = lws[2]; + return ret; +} + +ATTR ndrange_t +ndrange_3D(const size_t goff[3], const size_t gws[3], const size_t lws[3]) +{ + ndrange_t ret; + ret.workDimension = 3; + ret.globalWorkOffset[0] = goff[0]; + ret.globalWorkOffset[1] = goff[1]; + ret.globalWorkOffset[2] = goff[2]; + ret.globalWorkSize[0] = gws[0]; + ret.globalWorkSize[1] = gws[1]; + ret.globalWorkSize[2] = gws[2]; + ret.localWorkSize[0] = lws[0]; + ret.localWorkSize[1] = lws[1]; + ret.localWorkSize[2] = lws[2]; + return ret; +} + diff --git a/amd/device-libs/opencl/src/devenq/schedule_pal.cl b/amd/device-libs/opencl/src/devenq/schedule_pal.cl new file mode 100644 index 0000000000000..dcbd9aea89590 --- /dev/null +++ b/amd/device-libs/opencl/src/devenq/schedule_pal.cl @@ -0,0 +1,230 @@ + +#include "devenq.h" + +typedef struct _SchedulerParam { + uint signal; //!< Signal to stop the child queue + uint eng_clk; //!< Engine clock in Mhz + ulong hw_queue; //!< Address to HW queue + ulong hsa_queue; //!< Address to HSA dummy queue + uint useATC; //!< GPU access to shader program by ATC. + uint scratchSize; //!< Scratch buffer size + ulong scratch; //!< GPU address to the scratch buffer + uint numMaxWaves; //!< Num max waves on the asic + uint releaseHostCP; //!< Releases CP on the host queue + union { + __global AmdAqlWrap* parentAQL; //!< Host parent AmdAqlWrap packet + ulong pad_parentAQL; + }; + uint dedicatedQueue; //!< Scheduler uses a dedicated queue + uint scratchOffset; //!< Scratch buffer offset + uint ringGran64Dw ; //!< WAVESIZE unit is 64 dwords instead of 256 + uint reserved[1]; //!< Processed mask groups by one thread +} SchedulerParam; + +static inline int +checkWaitEvents(__global AmdEvent** events, uint numEvents) +{ + for (uint i = 0; i < numEvents; ++i) { + int status = atomic_load_explicit((__global atomic_uint*)(&events[i]->state), memory_order_relaxed, memory_scope_device); + if (status != CL_COMPLETE) + return status < 0 ? -1 : 0; + } + return 1; +} + +static inline void +releaseEvent(__global AmdEvent* ev, __global uint* emask, __global AmdEvent* eb) +{ + uint c = atomic_fetch_sub_explicit((__global atomic_uint *)&ev->counter, 1U, memory_order_relaxed, memory_scope_device); + if (c == 1U) { + uint i = ev - eb; + release_slot(emask, i); + } +} + +static inline void +releaseWaitEvents(__global AmdEvent** events, uint numEvents, __global uint* emask, __global AmdEvent* eb) +{ + for (uint i = 0; i < numEvents; ++i) { + releaseEvent(events[i], emask, eb); + } +} + +static inline uint +min_command(uint slot_num, __global AmdAqlWrap* wraps) +{ + uint minCommand = 0xffffffff; + for (uint idx = 0; idx < slot_num; ++idx) { + __global AmdAqlWrap* disp = (__global AmdAqlWrap*)&wraps[idx]; + uint slotState = atomic_load_explicit((__global atomic_uint*)(&disp->state), memory_order_relaxed, memory_scope_device); + if ((slotState != AQL_WRAP_FREE) && (slotState != AQL_WRAP_RESERVED)) { + minCommand = min(disp->command_id, minCommand); + } + } + return minCommand; +} + +extern uint GetCmdTemplateHeaderSize(void); +extern uint GetCmdTemplateDispatchSize(void); +extern void EmptyCmdTemplateDispatch(ulong cmdBuf); +extern void RunCmdTemplateDispatch( + ulong cmdBuf, + __global hsa_kernel_dispatch_packet_t* aqlPkt, + ulong scratch, + ulong hsaQueue, + uint scratchSize, + uint scratchOffset, + uint numMaxWaves, + uint useATC, + uint ringGran64Dw); + +void +__amd_scheduler_pal( + __global AmdVQueueHeader* queue, + __global SchedulerParam* params, + uint paramIdx) +{ + __global SchedulerParam* param = ¶ms[paramIdx]; + ulong hwDisp = param->hw_queue + GetCmdTemplateHeaderSize(); + __global AmdAqlWrap* hostParent = param->parentAQL; + __global uint* counter = (__global uint*)(&hostParent->child_counter); + __global uint* signal = (__global uint*)(¶m->signal); + __global AmdAqlWrap* wraps = (__global AmdAqlWrap*)&queue[1]; + __global uint* amask = (__global uint *)queue->aql_slot_mask; + + //! @todo This is an unexplained behavior. + //! The scheduler can be launched one more time after termination. + if (1 == atomic_load_explicit((__global atomic_uint*)¶m->releaseHostCP, + memory_order_acquire, memory_scope_device)) { + return; + } + + int launch = 0; + int grpId = get_group_id(0); + hwDisp += GetCmdTemplateDispatchSize() * grpId; + uint mskGrp = queue->mask_groups; + + for (uint m = 0; m < mskGrp && launch == 0; ++m) { + uint maskId = grpId * mskGrp + m; + uint mask = atomic_load_explicit((__global atomic_uint*)(&amask[maskId]), memory_order_relaxed, memory_scope_device); + + int baseIdx = maskId << 5; + while (mask != 0) { + uint sIdx = ctz(mask); + uint idx = baseIdx + sIdx; + mask &= ~(1 << sIdx); + __global AmdAqlWrap* disp = (__global AmdAqlWrap*)&wraps[idx]; + uint slotState = atomic_load_explicit((__global atomic_uint*)(&disp->state), memory_order_acquire, memory_scope_device); + __global AmdAqlWrap* parent = (__global AmdAqlWrap*)(disp->parent_wrap); + __global AmdEvent* event = (__global AmdEvent*)(disp->completion); + + // Check if the current slot is ready for processing + if (slotState == AQL_WRAP_READY) { + if (launch == 0) { + // Attempt to find a new dispatch if nothing was launched yet + uint parentState = atomic_load_explicit((__global atomic_uint*)(&parent->state), memory_order_relaxed, memory_scope_device); + uint enqueueFlags = atomic_load_explicit((__global atomic_uint*)(&disp->enqueue_flags), memory_order_relaxed, memory_scope_device); + + // Check the launch flags + if (((enqueueFlags == CLK_ENQUEUE_FLAGS_WAIT_KERNEL) || + (enqueueFlags == CLK_ENQUEUE_FLAGS_WAIT_WORK_GROUP)) && + (parentState != AQL_WRAP_DONE)) { + continue; + } + + // Check if the wait list is COMPLETE + launch = checkWaitEvents((__global AmdEvent**)(disp->wait_list), disp->wait_num); + + if (launch != 0) { + if (event != 0) { + event->timer[PROFILING_COMMAND_START] = ((ulong)__builtin_readcyclecounter() * (ulong)param->eng_clk) >> 10; + } + if (launch > 0) { + // Launch child kernel .... + RunCmdTemplateDispatch(hwDisp, &disp->aql, param->scratch, param->hsa_queue, + param->scratchSize, param->scratchOffset, param->numMaxWaves, param->useATC, param->ringGran64Dw); + } else if (event != 0) { + event->state = -1; + } + atomic_store_explicit((__global atomic_uint*)&disp->state, AQL_WRAP_BUSY, memory_order_relaxed, memory_scope_device); + releaseWaitEvents((__global AmdEvent**)(disp->wait_list), disp->wait_num, (__global uint*)queue->event_slot_mask, + (__global AmdEvent*)queue->event_slots); + break; + } + } + } else if (slotState == AQL_WRAP_MARKER) { + bool complete = false; + if (disp->wait_num == 0) { + uint minCommand = min_command(queue->aql_slot_num, wraps); + complete = disp->command_id == minCommand; + } else { + int status = checkWaitEvents((__global AmdEvent**)(disp->wait_list), disp->wait_num); + // Check if the wait list is COMPLETE + if (status != 0) { + complete = true; + releaseWaitEvents((__global AmdEvent**)(disp->wait_list), disp->wait_num, (__global uint*)queue->event_slot_mask, + (__global AmdEvent*)queue->event_slots); + if (status < 0) + event->state = -1; + } + } + if (complete) { + // Decrement the child execution counter on the parent + atomic_fetch_sub_explicit((__global atomic_uint*)&parent->child_counter, 1, memory_order_relaxed, memory_scope_device); + if (event->state >= 0) + event->state = CL_COMPLETE; + atomic_store_explicit((__global atomic_uint*)&disp->state, AQL_WRAP_FREE, memory_order_relaxed, memory_scope_device); + release_slot(amask, idx); + releaseEvent(event, (__global uint*)queue->event_slot_mask, (__global AmdEvent*)queue->event_slots); + } + } else if ((slotState == AQL_WRAP_BUSY) || (slotState == AQL_WRAP_DONE)) { + if (slotState == AQL_WRAP_BUSY) { + atomic_store_explicit((__global atomic_uint*)&disp->state, AQL_WRAP_DONE, memory_order_relaxed, memory_scope_device); + if (event != 0) { + event->timer[PROFILING_COMMAND_END] = ((ulong)__builtin_readcyclecounter() * (ulong)param->eng_clk) >> 10; + } + } + // Was CL_EVENT requested? + if (event != 0) { + // The current dispatch doesn't have any outstanding children + if (disp->child_counter == 0) { + event->timer[PROFILING_COMMAND_COMPLETE] = ((ulong)__builtin_readcyclecounter() * (ulong)param->eng_clk) >> 10; + if (event->state >= 0) { + event->state = CL_COMPLETE; + } + if (event->capture_info != 0) { + __global ulong* values = (__global ulong*)event->capture_info; + values[0] = event->timer[PROFILING_COMMAND_END] - event->timer[PROFILING_COMMAND_START]; + values[1] = event->timer[PROFILING_COMMAND_COMPLETE] - event->timer[PROFILING_COMMAND_START]; + } + releaseEvent(event, (__global uint *)queue->event_slot_mask, (__global AmdEvent *)queue->event_slots); + } + } + // The current dispatch doesn't have any outstanding children + if (disp->child_counter == 0) { + // Decrement the child execution counter on the parent + atomic_fetch_sub_explicit((__global atomic_uint*)&parent->child_counter, 1, memory_order_relaxed, memory_scope_device); + atomic_store_explicit((__global atomic_uint*)&disp->state, AQL_WRAP_FREE, memory_order_relaxed, memory_scope_device); + release_slot(amask, idx); + } + } + } + } + + if (launch <= 0) { + EmptyCmdTemplateDispatch(hwDisp); + } + + __global atomic_uint *againptr = param->dedicatedQueue ? (__global atomic_uint*)¶m->signal : (__global atomic_uint*)&hostParent->child_counter; + + uint again = atomic_load_explicit(againptr, memory_order_relaxed, memory_scope_device); + + if (!again) { + //! \todo Write deadcode to the template, but somehow + //! the scheduler will be launched one more time. + atomic_store_explicit((__global atomic_uint*)hwDisp, 0xdeadc0de, memory_order_relaxed, memory_scope_device); + atomic_store_explicit((__global atomic_uint*)¶m->signal, 0, memory_order_relaxed, memory_scope_device); + atomic_store_explicit((__global atomic_uint*)¶m->releaseHostCP, 1, memory_order_relaxed, memory_scope_device); + } +} + diff --git a/amd/device-libs/opencl/src/devenq/schedule_rocm.cl b/amd/device-libs/opencl/src/devenq/schedule_rocm.cl new file mode 100644 index 0000000000000..209eebeebc02f --- /dev/null +++ b/amd/device-libs/opencl/src/devenq/schedule_rocm.cl @@ -0,0 +1,240 @@ + +#include "ockl_hsa.h" +#include "devenq.h" + +typedef struct _SchedulerParam { + ulong kernarg_address; //!< set to the VM address of SchedulerParam + ulong hidden_global_offset_x; //!< set to 0 before queuing the scheduler + ulong hidden_global_offset_y; //!< set to 0 before queuing the scheduler + ulong hidden_global_offset_z; //!< set to 0 before queuing the scheduler + ulong thread_counter; //!< set to 0 before queuing the scheduler + __global hsa_queue_t* child_queue; //!< set to the device queue the child kernels will be queued to + hsa_kernel_dispatch_packet_t scheduler_aql; //!< Dispatch packet used to relaunch the scheduler + hsa_signal_t complete_signal; //!< Notify the host queue to continue processing + __global AmdVQueueHeader* vqueue_header; //!< The vqueue + uint signal; //!< Signal to stop the child queue + uint eng_clk; //!< Engine clock in Mhz + __global AmdAqlWrap* parentAQL; //!< Host parent AmdAqlWrap packet + ulong write_index; //!< Write Index to the child queue +} SchedulerParam; + +static inline int +checkWaitEvents(__global AmdEvent** events, uint numEvents) +{ + for (uint i = 0; i < numEvents; ++i) { + int status = atomic_load_explicit((__global atomic_uint*)(&events[i]->state), memory_order_relaxed, memory_scope_device); + if (status != CL_COMPLETE) + return status < 0 ? -1 : 0; + } + return 1; +} + +static inline void +releaseEvent(__global AmdEvent* ev, __global uint* emask, __global AmdEvent* eb) +{ + uint c = atomic_fetch_sub_explicit((__global atomic_uint *)&ev->counter, 1U, memory_order_relaxed, memory_scope_device); + if (c == 1U) { + uint i = ev - eb; + release_slot(emask, i); + } +} + +static inline void +releaseWaitEvents(__global AmdEvent** events, uint numEvents, __global uint* emask, __global AmdEvent* eb) +{ + for (uint i = 0; i < numEvents; ++i) { + releaseEvent(events[i], emask, eb); + } +} + +static inline uint +min_command(uint slot_num, __global AmdAqlWrap* wraps) +{ + uint minCommand = 0xffffffff; + for (uint idx = 0; idx < slot_num; ++idx) { + __global AmdAqlWrap* disp = (__global AmdAqlWrap*)&wraps[idx]; + uint slotState = atomic_load_explicit((__global atomic_uint*)(&disp->state), memory_order_relaxed, memory_scope_device); + if ((slotState != AQL_WRAP_FREE) && (slotState != AQL_WRAP_RESERVED)) { + minCommand = min(disp->command_id, minCommand); + } + } + return minCommand; +} + +static inline bool +check_pcie_support(__global SchedulerParam* param) { + #define kInvalidWriteIndex (ulong)(-1) + return (param->write_index == kInvalidWriteIndex) ? true : false; +} + +static inline void +EnqueueDispatch(__global hsa_kernel_dispatch_packet_t* aqlPkt, __global SchedulerParam* param) +{ + __global hsa_queue_t* child_queue = param->child_queue; + + ulong index; + if (check_pcie_support(param)) { + index = __ockl_hsa_queue_add_write_index(child_queue, 1, __ockl_memory_order_relaxed); + } else { + index = atomic_fetch_add_explicit((__global atomic_ulong*)¶m->write_index, (ulong)1, memory_order_relaxed, memory_scope_device); + } + + const ulong queueMask = child_queue->size - 1; + __global hsa_kernel_dispatch_packet_t* dispatch_packet = &(((__global hsa_kernel_dispatch_packet_t*)(child_queue->base_address))[index & queueMask]); + *dispatch_packet = *aqlPkt; +} + +static inline void +EnqueueScheduler(__global SchedulerParam* param) +{ + __global hsa_queue_t* child_queue = param->child_queue; + + ulong index; + if (check_pcie_support(param)) { + index = __ockl_hsa_queue_add_write_index(child_queue, 1, __ockl_memory_order_relaxed); + } else { + index = atomic_fetch_add_explicit((__global atomic_ulong*)¶m->write_index, (ulong)1, memory_order_relaxed, memory_scope_device); + } + + const ulong queueMask = child_queue->size - 1; + __global hsa_kernel_dispatch_packet_t* dispatch_packet = &(((__global hsa_kernel_dispatch_packet_t*)(child_queue->base_address))[index & queueMask]); + *dispatch_packet = param->scheduler_aql; + + if (!check_pcie_support(param)) { + __ockl_hsa_queue_store_write_index(child_queue, index + 1, __ockl_memory_order_relaxed); + } + + __ockl_hsa_signal_store(child_queue->doorbell_signal, index, __ockl_memory_order_release); +} + +void +__amd_scheduler_rocm(__global SchedulerParam* param) +{ + __global AmdVQueueHeader* queue = (__global AmdVQueueHeader*)(param->vqueue_header); + __global AmdAqlWrap* wraps = (__global AmdAqlWrap*)&queue[1]; + __global uint* amask = (__global uint *)queue->aql_slot_mask; + + int launch = 0; + int grpId = get_group_id(0); + uint mskGrp = queue->mask_groups; + + for (uint m = 0; m < mskGrp && launch == 0; ++m) { + uint maskId = grpId * mskGrp + m; + uint mask = atomic_load_explicit((__global atomic_uint*)(&amask[maskId]), memory_order_relaxed, memory_scope_device); + + int baseIdx = maskId << 5; + while (mask != 0) { + uint sIdx = ctz(mask); + uint idx = baseIdx + sIdx; + mask &= ~(1 << sIdx); + __global AmdAqlWrap* disp = (__global AmdAqlWrap*)&wraps[idx]; + uint slotState = atomic_load_explicit((__global atomic_uint*)(&disp->state), memory_order_acquire, memory_scope_device); + __global AmdAqlWrap* parent = (__global AmdAqlWrap*)(disp->parent_wrap); + __global AmdEvent* event = (__global AmdEvent*)(disp->completion); + + // Check if the current slot is ready for processing + if (slotState == AQL_WRAP_READY) { + if (launch == 0) { + // Attempt to find a new dispatch if nothing was launched yet + uint parentState = atomic_load_explicit((__global atomic_uint*)(&parent->state), memory_order_relaxed, memory_scope_device); + uint enqueueFlags = atomic_load_explicit( (__global atomic_uint*)(&disp->enqueue_flags), memory_order_relaxed, memory_scope_device); + + // Check the launch flags + if (((enqueueFlags == CLK_ENQUEUE_FLAGS_WAIT_KERNEL) || + (enqueueFlags == CLK_ENQUEUE_FLAGS_WAIT_WORK_GROUP)) && + (parentState != AQL_WRAP_DONE)) { + continue; + } + + // Check if the wait list is COMPLETE + launch = checkWaitEvents((__global AmdEvent**)(disp->wait_list), disp->wait_num); + + if (launch != 0) { + if (event != 0) { + event->timer[PROFILING_COMMAND_START] = ((ulong)__builtin_readcyclecounter() * (ulong)param->eng_clk) >> 10; + } + if (launch > 0) { + // Launch child kernel .... + EnqueueDispatch(&disp->aql, param); + } else if (event != 0) { + event->state = -1; + } + atomic_store_explicit((__global atomic_uint*)&disp->state, AQL_WRAP_BUSY, memory_order_relaxed, memory_scope_device); + releaseWaitEvents((__global AmdEvent**)(disp->wait_list), disp->wait_num, (__global uint*)queue->event_slot_mask, + (__global AmdEvent*)queue->event_slots); + break; + } + } + } else if (slotState == AQL_WRAP_MARKER) { + bool complete = false; + if (disp->wait_num == 0) { + uint minCommand = min_command(queue->aql_slot_num, wraps); + complete = disp->command_id == minCommand; + } else { + int status = checkWaitEvents((__global AmdEvent**)(disp->wait_list), disp->wait_num); + // Check if the wait list is COMPLETE + if (status != 0) { + complete = true; + releaseWaitEvents((__global AmdEvent**)(disp->wait_list), disp->wait_num, (__global uint*)queue->event_slot_mask, + (__global AmdEvent*)queue->event_slots); + if (status < 0) + event->state = -1; + } + } + if (complete) { + // Decrement the child execution counter on the parent + atomic_fetch_sub_explicit((__global atomic_uint*)&parent->child_counter, 1, memory_order_relaxed, memory_scope_device); + if (event->state >= 0) + event->state = CL_COMPLETE; + atomic_store_explicit((__global atomic_uint*)&disp->state, AQL_WRAP_FREE, memory_order_relaxed, memory_scope_device); + release_slot(amask, idx); + releaseEvent(event, (__global uint*)queue->event_slot_mask, (__global AmdEvent*)queue->event_slots); + } + } else if ((slotState == AQL_WRAP_BUSY) || (slotState == AQL_WRAP_DONE)) { + if (slotState == AQL_WRAP_BUSY) { + atomic_store_explicit((__global atomic_uint*)&disp->state, AQL_WRAP_DONE, memory_order_relaxed, memory_scope_device); + if (event != 0) { + event->timer[PROFILING_COMMAND_END] = ((ulong)__builtin_readcyclecounter() * (ulong)param->eng_clk) >> 10; + } + } + // Was CL_EVENT requested? + if (event != 0) { + // The current dispatch doesn't have any outstanding children + if (disp->child_counter == 0) { + event->timer[PROFILING_COMMAND_COMPLETE] = ((ulong)__builtin_readcyclecounter() * (ulong)param->eng_clk) >> 10; + if (event->state >= 0) { + event->state = CL_COMPLETE; + } + if (event->capture_info != 0) { + __global ulong* values = (__global ulong*)event->capture_info; + values[0] = event->timer[PROFILING_COMMAND_END] - event->timer[PROFILING_COMMAND_START]; + values[1] = event->timer[PROFILING_COMMAND_COMPLETE] - event->timer[PROFILING_COMMAND_START]; + } + releaseEvent(event, (__global uint *)queue->event_slot_mask, (__global AmdEvent *)queue->event_slots); + } + } + // The current dispatch doesn't have any outstanding children + if (disp->child_counter == 0) { + // Decrement the child execution counter on the parent + atomic_fetch_sub_explicit((__global atomic_uint*)&parent->child_counter, 1, memory_order_relaxed, memory_scope_device); + atomic_store_explicit((__global atomic_uint*)&disp->state, AQL_WRAP_FREE, memory_order_relaxed, memory_scope_device); + release_slot(amask, idx); + } + } + } + } + + ulong threads_done = atomic_fetch_add_explicit((__global atomic_ulong*)¶m->thread_counter, (ulong)1, memory_order_relaxed, memory_scope_device); + if (threads_done >= (get_global_size(0) - 1)) { + // The last thread finishes the processing + __global AmdAqlWrap* hostParent = param->parentAQL; + bool complete = atomic_load_explicit((__global atomic_uint*)&hostParent->child_counter, memory_order_relaxed, memory_scope_device) == 0; + if (complete) { + __ockl_hsa_signal_store(param->complete_signal, 0, __ockl_memory_order_relaxed); + } else { + param->thread_counter = 0; + EnqueueScheduler(param); + } + } +} + diff --git a/amd/device-libs/opencl/src/geometric/cross.cl b/amd/device-libs/opencl/src/geometric/cross.cl new file mode 100644 index 0000000000000..2e39cf67c4dd3 --- /dev/null +++ b/amd/device-libs/opencl/src/geometric/cross.cl @@ -0,0 +1,32 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ATTR __attribute__((overloadable, const)) + +#define GEN(T) \ +ATTR T##3 \ +cross(T##3 p0, T##3 p1) \ +{ \ + return (T##3)(mad(p0.y, p1.z, -p0.z*p1.y), \ + mad(p0.z, p1.x, -p0.x*p1.z), \ + mad(p0.x, p1.y, -p0.y*p1.x)); \ +} \ + \ +ATTR T##4 \ +cross(T##4 p0, T##4 p1) \ +{ \ + return (T##4)(mad(p0.y, p1.z, -p0.z*p1.y), \ + mad(p0.z, p1.x, -p0.x*p1.z), \ + mad(p0.x, p1.y, -p0.y*p1.x), \ + (T)0); \ +} + +GEN(float) +GEN(double) +GEN(half) diff --git a/amd/device-libs/opencl/src/geometric/distance.cl b/amd/device-libs/opencl/src/geometric/distance.cl new file mode 100644 index 0000000000000..783f1f6d52371 --- /dev/null +++ b/amd/device-libs/opencl/src/geometric/distance.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ATTR __attribute__((overloadable, const)) + +#define GENN(N,T) \ +ATTR T \ +distance(T##N p0, T##N p1) \ +{ \ + return length(p0 - p1); \ +} + +#define GEN(T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GENN(,T) + +GEN(float) +GEN(double) +GEN(half) + diff --git a/amd/device-libs/opencl/src/geometric/dot.cl b/amd/device-libs/opencl/src/geometric/dot.cl new file mode 100644 index 0000000000000..3521f3bd2cc60 --- /dev/null +++ b/amd/device-libs/opencl/src/geometric/dot.cl @@ -0,0 +1,37 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ATTR __attribute__((overloadable, const)) + +#define GEN(T) \ +ATTR T \ +dot(T p0, T p1) \ +{ \ + return p0 * p1; \ +} \ +ATTR T \ +dot(T##2 p0, T##2 p1) \ +{ \ + return mad(p0.y, p1.y, p0.x*p1.x); \ +} \ +ATTR T \ +dot(T##3 p0, T##3 p1) \ +{ \ + return mad(p0.z, p1.z, mad(p0.y, p1.y, p0.x*p1.x)); \ +} \ +ATTR T \ +dot(T##4 p0, T##4 p1) \ +{ \ + return mad(p0.w, p1.w, mad(p0.z, p1.z, mad(p0.y, p1.y, p0.x*p1.x))); \ +} + +GEN(float) +GEN(double) +GEN(half) + diff --git a/amd/device-libs/opencl/src/geometric/fast_distance.cl b/amd/device-libs/opencl/src/geometric/fast_distance.cl new file mode 100644 index 0000000000000..a8d1e5002356c --- /dev/null +++ b/amd/device-libs/opencl/src/geometric/fast_distance.cl @@ -0,0 +1,24 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define GENN(N,T) \ +ATTR T \ +fast_distance(T##N p0, T##N p1) \ +{ \ + return fast_length(p0 - p1); \ +} + +#define GEN(T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GENN(,T) + +GEN(float) + diff --git a/amd/device-libs/opencl/src/geometric/fast_length.cl b/amd/device-libs/opencl/src/geometric/fast_length.cl new file mode 100644 index 0000000000000..efc5847dd28ec --- /dev/null +++ b/amd/device-libs/opencl/src/geometric/fast_length.cl @@ -0,0 +1,33 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +ATTR float +fast_length(float p) +{ + return fabs(p); +} + +ATTR float +fast_length(float2 p) +{ + return half_sqrt(dot(p, p)); +} + +ATTR float +fast_length(float3 p) +{ + return half_sqrt(dot(p, p)); +} + +ATTR float +fast_length(float4 p) +{ + return half_sqrt(dot(p, p)); +} + diff --git a/amd/device-libs/opencl/src/geometric/fast_normalize.cl b/amd/device-libs/opencl/src/geometric/fast_normalize.cl new file mode 100644 index 0000000000000..8d6f6bad67d73 --- /dev/null +++ b/amd/device-libs/opencl/src/geometric/fast_normalize.cl @@ -0,0 +1,28 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define GEN(N) \ +ATTR float##N \ +fast_normalize(float##N p) \ +{ \ + float l2 = dot(p, p); \ + float##N n = p * half_rsqrt(l2); \ + return l2 == 0.0f ? p : n; \ +} + +GEN(4) +GEN(3) +GEN(2) + +ATTR float +fast_normalize(float p) +{ + return sign(p); +} + diff --git a/amd/device-libs/opencl/src/geometric/length.cl b/amd/device-libs/opencl/src/geometric/length.cl new file mode 100644 index 0000000000000..1fe9b5a099b71 --- /dev/null +++ b/amd/device-libs/opencl/src/geometric/length.cl @@ -0,0 +1,191 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ATTR __attribute__((overloadable, const)) + +ATTR float +length(float p) +{ + return fabs(p); +} + +ATTR float +length(float2 p) +{ + float l2 = dot(p, p); + float r; + + if (l2 < FLT_MIN) { + p *= 0x1.0p+86f; + r = sqrt(dot(p, p)) * 0x1.0p-86f; + } else if (l2 == INFINITY) { + p *= 0x1.0p-65f; + r = sqrt(dot(p, p)) * 0x1.0p+65f; + } else + r = sqrt(l2); + + return r; +} + +ATTR float +length(float3 p) +{ + float l2 = dot(p, p); + float r; + + if (l2 < FLT_MIN) { + p *= 0x1.0p+86f; + r = sqrt(dot(p, p)) * 0x1.0p-86f; + } else if (l2 == INFINITY) { + p *= 0x1.0p-66f; + r = sqrt(dot(p, p)) * 0x1.0p+66f; + } else + r = sqrt(l2); + + return r; +} + +ATTR float +length(float4 p) +{ + float l2 = dot(p, p); + float r; + + if (l2 < FLT_MIN) { + p *= 0x1.0p+86f; + r = sqrt(dot(p, p)) * 0x1.0p-86f; + } else if (l2 == INFINITY) { + p *= 0x1.0p-66f; + r = sqrt(dot(p, p)) * 0x1.0p+66f; + } else + r = sqrt(l2); + + return r; +} + +ATTR double +length(double p) +{ + return fabs(p); +} + +ATTR double +length(double2 p) +{ + double l2 = dot(p, p); + double r; + + if (l2 < DBL_MIN) { + p *= 0x1.0p+563; + r = sqrt(dot(p, p)) * 0x1.0p-563; + } else if (l2 == INFINITY) { + p *= 0x1.0p-513; + r = sqrt(dot(p, p)) * 0x1.0p+513; + } else + r = sqrt(l2); + + return r; +} + +ATTR double +length(double3 p) +{ + double l2 = dot(p, p); + double r; + + if (l2 < DBL_MIN) { + p *= 0x1.0p+563; + r = sqrt(dot(p, p)) * 0x1.0p-563; + } else if (l2 == INFINITY) { + p *= 0x1.0p-514; + r = sqrt(dot(p, p)) * 0x1.0p+514; + } else + r = sqrt(l2); + + return r; +} + +ATTR double +length(double4 p) +{ + double l2 = dot(p, p); + double r; + + if (l2 < DBL_MIN) { + p *= 0x1.0p+563; + r = sqrt(dot(p, p)) * 0x1.0p-563; + } else if (l2 == INFINITY) { + p *= 0x1.0p-514; + r = sqrt(dot(p, p)) * 0x1.0p+514; + } else + r = sqrt(l2); + + return r; +} + +ATTR half +length(half p) +{ + return fabs(p); +} + +ATTR half +length(half2 p) +{ + half l2 = dot(p, p); + half r; + + if (l2 < HALF_MIN) { + p = p * 0x1.0p+10h * 0x1.0p+7h; + r = sqrt(dot(p, p)) * 0x1.0p-17h; + } else if (l2 == (half)INFINITY) { + p *= 0x1.0p-9h; + r = sqrt(dot(p, p)) * 0x1.0p+9h; + } else + r = sqrt(l2); + + return r; +} + +ATTR half +length(half3 p) +{ + half l2 = dot(p, p); + half r; + + if (l2 < HALF_MIN) { + p = p * 0x1.0p+10h * 0x1.0p+7h; + r = sqrt(dot(p, p)) * 0x1.0p-17h; + } else if (l2 == (half)INFINITY) { + p *= 0x1.0p-10h; + r = sqrt(dot(p, p)) * 0x1.0p+10h; + } else + r = sqrt(l2); + + return r; +} + +ATTR half +length(half4 p) +{ + half l2 = dot(p, p); + half r; + + if (l2 < HALF_MIN) { + p = p * 0x1.0p+10h * 0x1.0p+7h; + r = sqrt(dot(p, p)) * 0x1.0p-17h; + } else if (l2 == (half)INFINITY) { + p *= 0x1.0p-10h; + r = sqrt(dot(p, p)) * 0x1.0p+10h; + } else + r = sqrt(l2); + + return r; +} + diff --git a/amd/device-libs/opencl/src/geometric/normalize.cl b/amd/device-libs/opencl/src/geometric/normalize.cl new file mode 100644 index 0000000000000..327521bf9253f --- /dev/null +++ b/amd/device-libs/opencl/src/geometric/normalize.cl @@ -0,0 +1,227 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ATTR __attribute__((overloadable, const)) + +ATTR float +normalize(float p) +{ + return sign(p); +} + +ATTR float2 +normalize(float2 p) +{ + if (all(p == (float2)0.0F)) + return p; + + float l2 = dot(p, p); + + if (l2 < FLT_MIN) { + p *= 0x1.0p+86F; + l2 = dot(p, p); + } else if (l2 == INFINITY) { + p *= 0x1.0p-65f; + l2 = dot(p, p); + if (l2 == INFINITY) { + p = copysign(select((float2)0.0F, (float2)1.0F, isinf(p)), p); + l2 = dot(p, p); + } + } + return p * rsqrt(l2); +} + +ATTR float3 +normalize(float3 p) +{ + if (all(p == (float3)0.0F)) + return p; + + float l2 = dot(p, p); + + if (l2 < FLT_MIN) { + p *= 0x1.0p+86F; + l2 = dot(p, p); + } else if (l2 == INFINITY) { + p *= 0x1.0p-66f; + l2 = dot(p, p); + if (l2 == INFINITY) { + p = copysign(select((float3)0.0F, (float3)1.0F, isinf(p)), p); + l2 = dot(p, p); + } + } + return p * rsqrt(l2); +} + +ATTR float4 +normalize(float4 p) +{ + if (all(p == (float4)0.0F)) + return p; + + float l2 = dot(p, p); + + if (l2 < FLT_MIN) { + p *= 0x1.0p+86F; + l2 = dot(p, p); + } else if (l2 == INFINITY) { + p *= 0x1.0p-66f; + l2 = dot(p, p); + if (l2 == INFINITY) { + p = copysign(select((float4)0.0F, (float4)1.0F, isinf(p)), p); + l2 = dot(p, p); + } + } + return p * rsqrt(l2); +} + +ATTR double +normalize(double p) +{ + return sign(p); +} + +ATTR double2 +normalize(double2 p) +{ + if (all(p == (double2)0.0)) + return p; + + double l2 = dot(p, p); + + if (l2 < DBL_MIN) { + p *= 0x1.0p+563; + l2 = dot(p, p); + } else if (l2 == INFINITY) { + p *= 0x1.0p-513; + l2 = dot(p, p); + if (l2 == INFINITY) { + p = copysign(select((double2)0.0, (double2)1.0, isinf(p)), p); + l2 = dot(p, p); + } + } + return p * rsqrt(l2); +} + +ATTR double3 +normalize(double3 p) +{ + if (all(p == (double3)0.0)) + return p; + + double l2 = dot(p, p); + + if (l2 < DBL_MIN) { + p *= 0x1.0p+563; + l2 = dot(p, p); + } else if (l2 == INFINITY) { + p *= 0x1.0p-514; + l2 = dot(p, p); + if (l2 == INFINITY) { + p = copysign(select((double3)0.0, (double3)1.0, isinf(p)), p); + l2 = dot(p, p); + } + } + return p * rsqrt(l2); +} + +ATTR double4 +normalize(double4 p) +{ + if (all(p == (double4)0.0)) + return p; + + double l2 = dot(p, p); + + if (l2 < DBL_MIN) { + p *= 0x1.0p+563; + l2 = dot(p, p); + } else if (l2 == INFINITY) { + p *= 0x1.0p-514; + l2 = dot(p, p); + if (l2 == INFINITY) { + p = copysign(select((double4)0.0, (double4)1.0, isinf(p)), p); + l2 = dot(p, p); + } + } + return p * rsqrt(l2); +} + +ATTR half +normalize(half p) +{ + return sign(p); +} + +ATTR half2 +normalize(half2 p) +{ + if (all(p == (half2)0.0)) + return p; + + half l2 = dot(p, p); + + if (l2 < HALF_MIN) { + p = p * 0x1.0p+10h * 0x1.0p+7h; + l2 = dot(p, p); + } else if (l2 == (half)INFINITY) { + p *= 0x1.0p-9h; + l2 = dot(p, p); + if (l2 == (half)INFINITY) { + p = copysign(select((half2)0.0, (half2)1.0, isinf(p)), p); + l2 = dot(p, p); + } + } + return p * rsqrt(l2); +} + +ATTR half3 +normalize(half3 p) +{ + if (all(p == (half3)0.0)) + return p; + + half l2 = dot(p, p); + + if (l2 < HALF_MIN) { + p = p * 0x1.0p+10h * 0x1.0p+7h; + l2 = dot(p, p); + } else if (l2 == (half)INFINITY) { + p *= 0x1.0p-10h; + l2 = dot(p, p); + if (l2 == (half)INFINITY) { + p = copysign(select((half3)0.0, (half3)1.0, isinf(p)), p); + l2 = dot(p, p); + } + } + return p * rsqrt(l2); +} + +ATTR half4 +normalize(half4 p) +{ + if (all(p == (half4)0.0)) + return p; + + half l2 = dot(p, p); + + if (l2 < HALF_MIN) { + p = p * 0x1.0p+10h * 0x1.0p+7h; + l2 = dot(p, p); + } else if (l2 == (half)INFINITY) { + p *= 0x1.0p-10h; + l2 = dot(p, p); + if (l2 == INFINITY) { + p = copysign(select((half4)0.0, (half4)1.0, isinf(p)), p); + l2 = dot(p, p); + } + } + return p * rsqrt(l2); +} + diff --git a/amd/device-libs/opencl/src/image/imwrap.cl b/amd/device-libs/opencl/src/image/imwrap.cl new file mode 100644 index 0000000000000..0e8bb7207d795 --- /dev/null +++ b/amd/device-libs/opencl/src/image/imwrap.cl @@ -0,0 +1,707 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" +#include "oclc.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_mipmap_image : enable + +static __constant int channel_order_map[32] = { + CLK_A, + CLK_R, + CLK_Rx, + CLK_RG, + CLK_RGx, + CLK_RA, + CLK_RGB, + CLK_RGBx, + CLK_RGBA, + CLK_BGRA, + CLK_ARGB, + 666, // XXX CLK_ABGR, + CLK_sRGB, + CLK_sRGBx, + CLK_sRGBA, + CLK_sBGRA, + CLK_INTENSITY, + CLK_LUMINANCE, + CLK_DEPTH, + CLK_DEPTH_STENCIL +}; + +static __constant int channel_data_type_map[32] = { + CLK_SNORM_INT8, + CLK_SNORM_INT16, + CLK_UNORM_INT8, + CLK_UNORM_INT16, + CLK_UNORM_INT24, + CLK_UNORM_SHORT_555, + CLK_UNORM_SHORT_565, + CLK_UNORM_INT_101010, + CLK_SIGNED_INT8, + CLK_SIGNED_INT16, + CLK_SIGNED_INT32, + CLK_UNSIGNED_INT8, + CLK_UNSIGNED_INT16, + CLK_UNSIGNED_INT32, + CLK_HALF_FLOAT, + CLK_FLOAT +}; + + +#define LOWER_sampler(S) __builtin_astype(S, SSHARP) + +#define LOWER_ro_1D(I) __builtin_astype(I, TSHARP) +#define LOWER_ro_1Da(I) __builtin_astype(I, TSHARP) +#define LOWER_ro_1Db(I) __builtin_astype(I, TSHARP) +#define LOWER_ro_2D(I) __builtin_astype(I, TSHARP) +#define LOWER_ro_2Da(I) __builtin_astype(I, TSHARP) +#define LOWER_ro_2Dd(I) __builtin_astype(I, TSHARP) +#define LOWER_ro_2Dad(I) __builtin_astype(I, TSHARP) +#define LOWER_ro_3D(I) __builtin_astype(I, TSHARP) + +#define LOWER_wo_1D(I) __builtin_astype(I, TSHARP) +#define LOWER_wo_1Da(I) __builtin_astype(I, TSHARP) +#define LOWER_wo_1Db(I) __builtin_astype(I, TSHARP) +#define LOWER_wo_2D(I) __builtin_astype(I, TSHARP) +#define LOWER_wo_2Da(I) __builtin_astype(I, TSHARP) +#define LOWER_wo_2Dd(I) __builtin_astype(I, TSHARP) +#define LOWER_wo_2Dad(I) __builtin_astype(I, TSHARP) +#define LOWER_wo_3D(I) __builtin_astype(I, TSHARP) + +#define LOWER_rw_1D(I) __builtin_astype(I, TSHARP) +#define LOWER_rw_1Da(I) __builtin_astype(I, TSHARP) +#define LOWER_rw_1Db(I) __builtin_astype(I, TSHARP) +#define LOWER_rw_2D(I) __builtin_astype(I, TSHARP) +#define LOWER_rw_2Da(I) __builtin_astype(I, TSHARP) +#define LOWER_rw_2Dd(I) __builtin_astype(I, TSHARP) +#define LOWER_rw_2Dad(I) __builtin_astype(I, TSHARP) +#define LOWER_rw_3D(I) __builtin_astype(I, TSHARP) + +#define _C(X,Y) X ## Y +#define C(X,Y) _C(X,Y) + +#define PFX __ockl_image_ + +#define i32_fsuf i +#define u32_fsuf ui +#define f32_fsuf f +#define f16_fsuf h + +#define i32_ksuf +#define u32_ksuf +#define f32_ksuf +#define f16_ksuf h + +#define i32_rcast as_int4 +#define u32_rcast as_uint4 +#define f32_rcast +#define f16_rcast + +#define _1D_ity image1d_t +#define _1Da_ity image1d_array_t +#define _1Db_ity image1d_buffer_t +#define _2D_ity image2d_t +#define _2Da_ity image2d_array_t +#define _2Dd_ity image2d_depth_t +#define _2Dad_ity image2d_array_depth_t +#define _3D_ity image3d_t + +#define _1D_f32_pty float4 +#define _1D_f16_pty half4 +#define _1D_i32_pty int4 +#define _1D_u32_pty uint4 + +#define _1Da_f32_pty float4 +#define _1Da_f16_pty half4 +#define _1Da_i32_pty int4 +#define _1Da_u32_pty uint4 + +#define _1Db_f32_pty float4 +#define _1Db_f16_pty half4 +#define _1Db_i32_pty int4 +#define _1Db_u32_pty uint4 + +#define _2D_f32_pty float4 +#define _2D_f16_pty half4 +#define _2D_i32_pty int4 +#define _2D_u32_pty uint4 + +#define _2Da_f32_pty float4 +#define _2Da_f16_pty half4 +#define _2Da_i32_pty int4 +#define _2Da_u32_pty uint4 + +#define _2Dd_f32_pty float + +#define _2Dad_f32_pty float + +#define _3D_f32_pty float4 +#define _3D_f16_pty half4 +#define _3D_i32_pty int4 +#define _3D_u32_pty uint4 + +#define _1D_f32_parg p +#define _1D_f16_parg p +#define _1D_i32_parg as_float4(p) +#define _1D_u32_parg as_float4(p) + +#define _1Da_f32_parg p +#define _1Da_f16_parg p +#define _1Da_i32_parg as_float4(p) +#define _1Da_u32_parg as_float4(p) + +#define _1Db_f32_parg p +#define _1Db_f16_parg p +#define _1Db_i32_parg as_float4(p) +#define _1Db_u32_parg as_float4(p) + +#define _2D_f32_parg p +#define _2D_f16_parg p +#define _2D_i32_parg as_float4(p) +#define _2D_u32_parg as_float4(p) + +#define _2Da_f32_parg p +#define _2Da_f16_parg p +#define _2Da_i32_parg as_float4(p) +#define _2Da_u32_parg as_float4(p) + +#define _2Dd_f32_parg p + +#define _2Dad_f32_parg p + +#define _3D_f32_parg p +#define _3D_f16_parg p +#define _3D_i32_parg as_float4(p) +#define _3D_u32_parg as_float4(p) + +#define _1D_i32_cty int +#define _1D_f32_cty float + +#define _1Da_i32_cty int2 +#define _1Da_f32_cty float2 + +#define _1Db_i32_cty int + +#define _2D_i32_cty int2 +#define _2D_f32_cty float2 + +#define _2Da_i32_cty int4 +#define _2Da_f32_cty float4 + +#define _2Dd_i32_cty int2 +#define _2Dd_f32_cty float2 + +#define _2Dad_i32_cty int4 +#define _2Dad_f32_cty float4 + +#define _3D_i32_cty int4 +#define _3D_f32_cty float4 + +#define _1D_i32_carg convert_float(c) +#define _1D_f32_carg c + +#define _1Da_i32_carg convert_float2(c) +#define _1Da_f32_carg c + +#define _1Db_i32_carg c + +#define _2D_i32_carg convert_float2(c) +#define _2D_f32_carg c + +#define _2Da_i32_carg convert_float4(c) +#define _2Da_f32_carg c + +#define _2Dd_i32_carg convert_float2(c) +#define _2Dd_f32_carg c + +#define _2Dad_i32_carg convert_float4(c) +#define _2Dad_f32_carg c + +#define _3D_i32_carg convert_float4(c) +#define _3D_f32_carg c + +#define _1D_gpars float dx, float dy +#define _1Da_gpars float dx, float dy +#define _2D_gpars float2 dx, float2 dy +#define _2Da_gpars float2 dx, float2 dy +#define _2Dd_gpars float2 dx, float2 dy +#define _2Dad_gpars float2 dx, float2 dy +#define _3D_gpars float4 dx, float4 dy + +#define RATTR __attribute__((overloadable, pure)) +#define WATTR __attribute__((overloadable)) +#define GATTR __attribute__((overloadable, const)) +#define FATTR __attribute__((pure)) + +#define SGEN(IT,PT,CT) \ +RATTR IT##_##PT##_pty \ +C(read_image,PT##_fsuf)(read_only IT##_ity i, sampler_t s, IT##_##CT##_cty c) \ +{ \ + return PT##_rcast(C(PFX,C(sample,C(PT##_ksuf,IT)))(LOWER_ro##IT(i), LOWER_sampler(s), IT##_##CT##_carg)); \ +} + +#define SGENL(IT,PT,CT) \ +RATTR IT##_##PT##_pty \ +C(read_image,PT##_fsuf)(read_only IT##_ity i, sampler_t s, IT##_##CT##_cty c, float l) \ +{ \ + return PT##_rcast(C(PFX,C(sample,C(PT##_ksuf,C(_lod,IT))))(LOWER_ro##IT(i), LOWER_sampler(s), IT##_##CT##_carg, l)); \ +} + +#define SGENG(IT,PT,CT) \ +RATTR IT##_##PT##_pty \ +C(read_image,PT##_fsuf)(read_only IT##_ity i, sampler_t s, IT##_##CT##_cty c, IT##_gpars) \ +{ \ + return PT##_rcast(C(PFX,C(sample,C(PT##_ksuf,C(_grad,IT))))(LOWER_ro##IT(i), LOWER_sampler(s), IT##_##CT##_carg, dx, dy)); \ +} + +#define SGENX(IT,PT,CT) \ + SGEN(IT,PT,CT) \ + SGENL(IT,PT,CT) \ + SGENG(IT,PT,CT) + +#define RGEN(IT,PT,CT) \ +RATTR IT##_##PT##_pty \ +C(read_image,PT##_fsuf)(read_only IT##_ity i, IT##_##CT##_cty c) \ +{ \ + return PT##_rcast(C(PFX,C(load,C(PT##_ksuf,IT)))(LOWER_ro##IT(i), c)); \ +} \ + \ +RATTR IT##_##PT##_pty \ +C(read_image,PT##_fsuf)(read_write IT##_ity i, IT##_##CT##_cty c) \ +{ \ + return PT##_rcast(C(PFX,C(load,C(PT##_ksuf,IT)))(LOWER_rw##IT(i), c)); \ +} + +#define WGEN(IT,PT,CT) \ +WATTR void \ +C(write_image,PT##_fsuf)(write_only IT##_ity i, IT##_##CT##_cty c, IT##_##PT##_pty p) \ +{ \ + C(PFX,C(store,C(PT##_ksuf,IT)))(LOWER_wo##IT(i), c, IT##_##PT##_parg); \ +} \ + \ +WATTR void \ +C(write_image,PT##_fsuf)(read_write IT##_ity i, IT##_##CT##_cty c, IT##_##PT##_pty p) \ +{ \ + C(PFX,C(store,C(PT##_ksuf,IT)))(LOWER_rw##IT(i), c, IT##_##PT##_parg); \ +} + +#define WGENL(IT,PT,CT) \ +WATTR void \ +C(write_image,PT##_fsuf)(write_only IT##_ity i, IT##_##CT##_cty c, int l, IT##_##PT##_pty p) \ +{ \ + C(PFX,C(store,C(PT##_ksuf,C(_lod,IT))))(LOWER_wo##IT(i), c, l, IT##_##PT##_parg); \ +} \ + \ +WATTR void \ +C(write_image,PT##_fsuf)(read_write IT##_ity i, IT##_##CT##_cty c, int l, IT##_##PT##_pty p) \ +{ \ + C(PFX,C(store,C(PT##_ksuf,C(_lod,IT))))(LOWER_rw##IT(i), c, l, IT##_##PT##_parg); \ +} + +#define WGENX(IT,PT,CT) \ + WGEN(IT,PT,CT) \ + WGENL(IT,PT,CT) + +SGEN(_2D,f32,i32) +SGENX(_2D,f32,f32) +SGEN(_2D,f16,i32) +SGENX(_2D,f16,f32) +SGEN(_2D,i32,i32) +SGENX(_2D,i32,f32) +SGEN(_2D,u32,i32) +SGENX(_2D,u32,f32) + +SGEN(_3D,f32,i32) +SGENX(_3D,f32,f32) +SGEN(_3D,f16,i32) +SGENX(_3D,f16,f32) +SGEN(_3D,i32,i32) +SGENX(_3D,i32,f32) +SGEN(_3D,u32,i32) +SGENX(_3D,u32,f32) + +SGEN(_2Da,f32,i32) +SGENX(_2Da,f32,f32) +SGEN(_2Da,f16,i32) +SGENX(_2Da,f16,f32) +SGEN(_2Da,i32,i32) +SGENX(_2Da,i32,f32) +SGEN(_2Da,u32,i32) +SGENX(_2Da,u32,f32) + +SGEN(_1D,f32,i32) +SGENX(_1D,f32,f32) +SGEN(_1D,f16,i32) +SGENX(_1D,f16,f32) +SGEN(_1D,i32,i32) +SGENX(_1D,i32,f32) +SGEN(_1D,u32,i32) +SGENX(_1D,u32,f32) + +SGEN(_1Da,f32,i32) +SGENX(_1Da,f32,f32) +SGEN(_1Da,f16,i32) +SGENX(_1Da,f16,f32) +SGEN(_1Da,i32,i32) +SGENX(_1Da,i32,f32) +SGEN(_1Da,u32,i32) +SGENX(_1Da,u32,f32) + +SGEN(_2Dd,f32,i32) +SGENX(_2Dd,f32,f32) + +SGEN(_2Dad,f32,i32) +SGENX(_2Dad,f32,f32) + +RGEN(_2D,f32,i32) +RGEN(_2D,f16,i32) +RGEN(_2D,i32,i32) +RGEN(_2D,u32,i32) + +RGEN(_3D,f32,i32) +RGEN(_3D,f16,i32) +RGEN(_3D,i32,i32) +RGEN(_3D,u32,i32) + +RGEN(_2Da,f32,i32) +RGEN(_2Da,f16,i32) +RGEN(_2Da,i32,i32) +RGEN(_2Da,u32,i32) + +RGEN(_1D,f32,i32) +RGEN(_1D,f16,i32) +RGEN(_1D,i32,i32) +RGEN(_1D,u32,i32) + +RGEN(_1Db,f32,i32) +RGEN(_1Db,f16,i32) +RGEN(_1Db,i32,i32) +RGEN(_1Db,u32,i32) + +RGEN(_1Da,f32,i32) +RGEN(_1Da,f16,i32) +RGEN(_1Da,i32,i32) +RGEN(_1Da,u32,i32) + +RGEN(_2Dd,f32,i32) + +RGEN(_2Dad,f32,i32) + +WGENX(_2D,f32,i32) +WGENX(_2D,f16,i32) +WGENX(_2D,i32,i32) +WGENX(_2D,u32,i32) + +WGENX(_2Da,f32,i32) +WGENX(_2Da,f16,i32) +WGENX(_2Da,i32,i32) +WGENX(_2Da,u32,i32) + +WGENX(_1D,f32,i32) +WGENX(_1D,f16,i32) +WGENX(_1D,i32,i32) +WGENX(_1D,u32,i32) + +WGEN(_1Db,f32,i32) +WGEN(_1Db,f16,i32) +WGEN(_1Db,i32,i32) +WGEN(_1Db,u32,i32) + +WGENX(_1Da,f32,i32) +WGENX(_1Da,f16,i32) +WGENX(_1Da,i32,i32) +WGENX(_1Da,u32,i32) + +WGENX(_2Dd,f32,i32) + +WGENX(_2Dad,f32,i32) + +WGENX(_3D,f32,i32) +WGENX(_3D,f16,i32) +WGENX(_3D,i32,i32) +WGENX(_3D,u32,i32) + + +#define ro_qual read_only +#define wo_qual write_only +#define rw_qual read_write + +#define GD3GEN(Q) \ +GATTR int4 \ +get_image_dim(Q##_qual image3d_t i) \ +{ \ + return (int4)(get_image_width(i), get_image_height(i), get_image_depth(i), 0); \ +} + +GD3GEN(ro) +GD3GEN(wo) +GD3GEN(rw) + +#define GD2GENQ(Q,T) \ +GATTR int2 \ +get_image_dim(Q##_qual T##_ity i) \ +{ \ + return (int2)(get_image_width(i), get_image_height(i)); \ +} + +#define GD2GEN(T) \ + GD2GENQ(ro,T) \ + GD2GENQ(wo,T) \ + GD2GENQ(rw,T) + +GD2GEN(_2D) +GD2GEN(_2Da) +GD2GEN(_2Dd) +GD2GEN(_2Dad) + +#define GGENQT(Q,N,T) \ +GATTR int \ +get_image_##N(Q##_qual T##_ity i) { \ + return C(PFX,C(N,T))(LOWER_##Q##T(i)); \ +} + +#define GGENT(N,T) \ + GGENQT(ro,N,T) \ + GGENQT(wo,N,T) \ + GGENQT(rw,N,T) + +#define GGENX(N) \ + GGENT(N,_1D) \ + GGENT(N,_1Da) \ + GGENT(N,_2D) \ + GGENT(N,_2Da) \ + GGENT(N,_2Dd) \ + GGENT(N,_2Dad) \ + GGENT(N,_3D) + +#define GGEN(N) \ + GGENX(N) \ + GGENT(N,_1Db) \ + +GGEN(width) +GGENX(num_mip_levels) + +// int get depth _3D +#define GNZGEN(Q) \ +GATTR int \ +get_image_depth(Q##_qual image3d_t i) \ +{ \ + return C(PFX,depth_3D)(LOWER_##Q##_3D(i)); \ +} + +GNZGEN(ro) +GNZGEN(wo) +GNZGEN(rw) + +// size_t get image_array_size _1Da, _2Da, _2Dad +#define GASGENQ(Q,T) \ +GATTR size_t \ +get_image_array_size(Q##_qual T##_ity i) \ +{ \ + return C(PFX,C(array_size,T))(LOWER_##Q##T(i)); \ +} + +#define GASGEN(T) \ + GASGENQ(ro,T) \ + GASGENQ(wo,T) \ + GASGENQ(rw,T) + +GASGEN(_1Da) +GASGEN(_2Da) +GASGEN(_2Dad) + +#define GCOGENQ(Q,T) \ +GATTR int \ +get_image_channel_order(Q##_qual T##_ity i) { \ + return channel_order_map[C(PFX,C(channel_order,T))(LOWER_##Q##T(i))]; \ +} + +#define GCOGEN(T) \ + GCOGENQ(ro,T) \ + GCOGENQ(wo,T) \ + GCOGENQ(rw,T) + +GCOGEN(_1D) +GCOGEN(_1Da) +GCOGEN(_1Db) +GCOGEN(_2D) +GCOGEN(_2Da) +GCOGEN(_2Dd) +GCOGEN(_2Dad) +GCOGEN(_3D) + +#define GDTGENQ(Q,T) \ +GATTR int \ +get_image_channel_data_type(Q##_qual T##_ity i) { \ + return channel_data_type_map[C(PFX,C(channel_data_type,T))(LOWER_##Q##T(i))]; \ +} + +#define GDTGEN(T) \ + GDTGENQ(ro,T) \ + GDTGENQ(wo,T) \ + GDTGENQ(rw,T) + +GDTGEN(_1D) +GDTGEN(_1Da) +GDTGEN(_1Db) +GDTGEN(_2D) +GDTGEN(_2Da) +GDTGEN(_2Dd) +GDTGEN(_2Dad) +GDTGEN(_3D) + +#define GNYGENQ(Q,T) \ +GATTR int \ +get_image_height(Q##_qual T##_ity i) { \ + return C(PFX,C(height,T))(LOWER_##Q##T(i)); \ +} + +#define GNYGEN(T) \ + GNYGENQ(ro,T) \ + GNYGENQ(wo,T) \ + GNYGENQ(rw,T) + +GNYGEN(_2D) +GNYGEN(_2Da) +GNYGEN(_2Dd) +GNYGEN(_2Dad) +GNYGEN(_3D) + +FATTR float4 +amd_fetch4_ff(read_only image2d_t im, float2 coord, int comp) +{ + sampler_t s = CLK_NORMALIZED_COORDS_FALSE | CLK_FILTER_NEAREST | CLK_ADDRESS_NONE; + switch (comp) { + case 1: return __ockl_image_gather4g_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord); + case 2: return __ockl_image_gather4b_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord); + case 3: return __ockl_image_gather4a_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord); + default: return __ockl_image_gather4r_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord); + } +} + +FATTR float4 +amd_fetch4_fsf(read_only image2d_t im, sampler_t s, float2 coord, int comp) +{ + switch (comp) { + case 1: return __ockl_image_gather4g_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord); + case 2: return __ockl_image_gather4b_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord); + case 3: return __ockl_image_gather4a_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord); + default: return __ockl_image_gather4r_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord); + } +} + +FATTR float4 +amd_fetch4_fi(read_only image2d_t im, int2 coord, int comp) +{ + sampler_t s = CLK_NORMALIZED_COORDS_FALSE | CLK_FILTER_NEAREST | CLK_ADDRESS_NONE; + float2 fcoord = convert_float2(coord); + switch (comp) { + case 1: return __ockl_image_gather4g_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord); + case 2: return __ockl_image_gather4b_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord); + case 3: return __ockl_image_gather4a_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord); + default: return __ockl_image_gather4r_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord); + } +} + +FATTR float4 +amd_fetch4_fsi(read_only image2d_t im, sampler_t s, int2 coord, int comp) +{ + float2 fcoord = convert_float2(coord); + switch (comp) { + case 1: return __ockl_image_gather4g_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord); + case 2: return __ockl_image_gather4b_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord); + case 3: return __ockl_image_gather4a_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord); + default: return __ockl_image_gather4r_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord); + } +} + +FATTR int4 +amd_fetch4_if(read_only image2d_t im, float2 coord, int comp) +{ + sampler_t s = CLK_NORMALIZED_COORDS_FALSE | CLK_FILTER_NEAREST | CLK_ADDRESS_NONE; + if (__oclc_ISA_version < 9000) { + coord -= 0.5f; + } + switch (comp) { + case 1: return as_int4(__ockl_image_gather4g_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord)); + case 2: return as_int4(__ockl_image_gather4b_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord)); + case 3: return as_int4(__ockl_image_gather4a_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord)); + default: return as_int4(__ockl_image_gather4r_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord)); + } +} + +FATTR int4 +amd_fetch4_isf(read_only image2d_t im, sampler_t s, float2 coord, int comp) +{ + if (__oclc_ISA_version < 9000) { + coord -= 0.5f; + } + switch (comp) { + case 1: return as_int4(__ockl_image_gather4g_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord)); + case 2: return as_int4(__ockl_image_gather4b_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord)); + case 3: return as_int4(__ockl_image_gather4a_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord)); + default: return as_int4(__ockl_image_gather4r_2D(LOWER_ro_2D(im), LOWER_sampler(s), coord)); + } +} + +FATTR int4 +amd_fetch4_ii(read_only image2d_t im, int2 coord, int comp) +{ + sampler_t s = CLK_NORMALIZED_COORDS_FALSE | CLK_FILTER_NEAREST | CLK_ADDRESS_NONE; + float2 fcoord = convert_float2(coord); + if (__oclc_ISA_version < 9000) { + fcoord -= 0.5f; + } + switch (comp) { + case 1: return as_int4(__ockl_image_gather4g_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord)); + case 2: return as_int4(__ockl_image_gather4b_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord)); + case 3: return as_int4(__ockl_image_gather4a_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord)); + default: return as_int4(__ockl_image_gather4r_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord)); + } +} + +FATTR int4 +amd_fetch4_isi(read_only image2d_t im, sampler_t s, int2 coord, int comp) +{ + float2 fcoord = convert_float2(coord); + if (__oclc_ISA_version < 9000) { + fcoord -= 0.5f; + } + switch (comp) { + case 1: return as_int4(__ockl_image_gather4g_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord)); + case 2: return as_int4(__ockl_image_gather4b_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord)); + case 3: return as_int4(__ockl_image_gather4a_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord)); + default: return as_int4(__ockl_image_gather4r_2D(LOWER_ro_2D(im), LOWER_sampler(s), fcoord)); + } +} + +FATTR uint4 +amd_fetch4_uf(read_only image2d_t im, float2 coord, int comp) +{ + return as_uint4(amd_fetch4_if(im, coord, comp)); +} + +FATTR uint4 +amd_fetch4_usf(read_only image2d_t im, sampler_t s, float2 coord, int comp) +{ + return as_uint4(amd_fetch4_isf(im, s, coord, comp)); +} + +FATTR uint4 +amd_fetch4_ui(read_only image2d_t im, int2 coord, int comp) +{ + return as_uint4(amd_fetch4_ii(im, coord, comp)); +} + +FATTR uint4 +amd_fetch4_usi(read_only image2d_t im, sampler_t s, int2 coord, int comp) +{ + return as_uint4(amd_fetch4_isi(im, s, coord, comp)); +} + diff --git a/amd/device-libs/opencl/src/image/isamp.cl b/amd/device-libs/opencl/src/image/isamp.cl new file mode 100644 index 0000000000000..b0990d0d5565a --- /dev/null +++ b/amd/device-libs/opencl/src/image/isamp.cl @@ -0,0 +1,141 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" + +static __constant uint SI_samplers[] = { + 0x1000b1b6, 0x00fff000, 0x00000000, 0x00000000, // 0x10 + 0x100031b6, 0x00fff000, 0x00000000, 0x00000000, // 0x11 + 0x1000b092, 0x00fff000, 0x00000000, 0x00000000, // 0x12 + 0x10003092, 0x00fff000, 0x00000000, 0x00000000, // 0x13 + 0x1000b1b6, 0x00fff000, 0x00000000, 0x00000000, // 0x14 + 0x100031b6, 0x00fff000, 0x00000000, 0x00000000, // 0x15 + 0x1000b000, 0x00fff000, 0x00000000, 0x00000000, // 0x16 + 0x10003000, 0x00fff000, 0x00000000, 0x00000000, // 0x17 + 0x1000b049, 0x00fff000, 0x00000000, 0x00000000, // 0x18 + 0x10003049, 0x00fff000, 0x00000000, 0x00000000, // 0x19 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1a + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1b + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1c + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1d + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1e + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1f + 0x1000b1b6, 0x00fff000, 0x00500000, 0x00000000, // 0x20 + 0x100031b6, 0x00fff000, 0x00500000, 0x00000000, // 0x21 + 0x1000b092, 0x00fff000, 0x00500000, 0x00000000, // 0x22 + 0x10003092, 0x00fff000, 0x00500000, 0x00000000, // 0x23 + 0x1000b1b6, 0x00fff000, 0x00500000, 0x00000000, // 0x24 + 0x100031b6, 0x00fff000, 0x00500000, 0x00000000, // 0x25 + 0x1000b000, 0x00fff000, 0x00500000, 0x00000000, // 0x26 + 0x10003000, 0x00fff000, 0x00500000, 0x00000000, // 0x27 + 0x1000b049, 0x00fff000, 0x00500000, 0x00000000, // 0x28 + 0x10003049, 0x00fff000, 0x00500000, 0x00000000, // 0x29 +}; + +static __constant uint GFX9_samplers[] = { + 0x1000b1b6, 0x00fff000, 0x80000000, 0x00000000, // 0x10 + 0x100031b6, 0x00fff000, 0x80000000, 0x00000000, // 0x11 + 0x1000b092, 0x00fff000, 0x80000000, 0x00000000, // 0x12 + 0x10003092, 0x00fff000, 0x80000000, 0x00000000, // 0x13 + 0x1000b1b6, 0x00fff000, 0x80000000, 0x00000000, // 0x14 + 0x100031b6, 0x00fff000, 0x80000000, 0x00000000, // 0x15 + 0x1000b000, 0x00fff000, 0x80000000, 0x00000000, // 0x16 + 0x10003000, 0x00fff000, 0x80000000, 0x00000000, // 0x17 + 0x1000b049, 0x00fff000, 0x80000000, 0x00000000, // 0x18 + 0x10003049, 0x00fff000, 0x80000000, 0x00000000, // 0x19 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1a + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1b + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1c + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1d + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1e + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1f + 0x1000b1b6, 0x00fff000, 0x80500000, 0x00000000, // 0x20 + 0x100031b6, 0x00fff000, 0x80500000, 0x00000000, // 0x21 + 0x1000b092, 0x00fff000, 0x80500000, 0x00000000, // 0x22 + 0x10003092, 0x00fff000, 0x80500000, 0x00000000, // 0x23 + 0x1000b1b6, 0x00fff000, 0x80500000, 0x00000000, // 0x24 + 0x100031b6, 0x00fff000, 0x80500000, 0x00000000, // 0x25 + 0x1000b000, 0x00fff000, 0x80500000, 0x00000000, // 0x26 + 0x10003000, 0x00fff000, 0x80500000, 0x00000000, // 0x27 + 0x1000b049, 0x00fff000, 0x80500000, 0x00000000, // 0x28 + 0x10003049, 0x00fff000, 0x80500000, 0x00000000, // 0x29 +}; + +static __constant uint GFX10_samplers[] = { + 0x1000b1b6, 0x00fff000, 0x20000000, 0x00000000, // 0x10 + 0x100031b6, 0x00fff000, 0x20000000, 0x00000000, // 0x11 + 0x1000b092, 0x00fff000, 0x20000000, 0x00000000, // 0x12 + 0x10003092, 0x00fff000, 0x20000000, 0x00000000, // 0x13 + 0x1000b1b6, 0x00fff000, 0x20000000, 0x00000000, // 0x14 + 0x100031b6, 0x00fff000, 0x20000000, 0x00000000, // 0x15 + 0x1000b000, 0x00fff000, 0x20000000, 0x00000000, // 0x16 + 0x10003000, 0x00fff000, 0x20000000, 0x00000000, // 0x17 + 0x1000b049, 0x00fff000, 0x20000000, 0x00000000, // 0x18 + 0x10003049, 0x00fff000, 0x20000000, 0x00000000, // 0x19 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1a + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1b + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1c + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1d + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1e + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1f + 0x1000b1b6, 0x00fff000, 0x20500000, 0x00000000, // 0x20 + 0x100031b6, 0x00fff000, 0x20500000, 0x00000000, // 0x21 + 0x1000b092, 0x00fff000, 0x20500000, 0x00000000, // 0x22 + 0x10003092, 0x00fff000, 0x20500000, 0x00000000, // 0x23 + 0x1000b1b6, 0x00fff000, 0x20500000, 0x00000000, // 0x24 + 0x100031b6, 0x00fff000, 0x20500000, 0x00000000, // 0x25 + 0x1000b000, 0x00fff000, 0x20500000, 0x00000000, // 0x26 + 0x10003000, 0x00fff000, 0x20500000, 0x00000000, // 0x27 + 0x1000b049, 0x00fff000, 0x20500000, 0x00000000, // 0x28 + 0x10003049, 0x00fff000, 0x20500000, 0x00000000, // 0x29 +}; + +static __constant uint GFX12_samplers[] = { + 0x1000b1b6, 0x01ffe000, 0x20000000, 0x00000000, // 0x10 + 0x100031b6, 0x01ffe000, 0x20000000, 0x00000000, // 0x11 + 0x1000b092, 0x01ffe000, 0x20000000, 0x00000000, // 0x12 + 0x10003092, 0x01ffe000, 0x20000000, 0x00000000, // 0x13 + 0x1000b1b6, 0x01ffe000, 0x20000000, 0x00000000, // 0x14 + 0x100031b6, 0x01ffe000, 0x20000000, 0x00000000, // 0x15 + 0x1000b000, 0x01ffe000, 0x20000000, 0x00000000, // 0x16 + 0x10003000, 0x01ffe000, 0x20000000, 0x00000000, // 0x17 + 0x1000b049, 0x01ffe000, 0x20000000, 0x00000000, // 0x18 + 0x10003049, 0x01ffe000, 0x20000000, 0x00000000, // 0x19 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1a + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1b + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1c + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1d + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1e + 0x00000000, 0x00000000, 0x00000000, 0x00000000, // 0x1f + 0x1000b1b6, 0x01ffe000, 0x20500000, 0x00000000, // 0x20 + 0x100031b6, 0x01ffe000, 0x20500000, 0x00000000, // 0x21 + 0x1000b092, 0x01ffe000, 0x20500000, 0x00000000, // 0x22 + 0x10003092, 0x01ffe000, 0x20500000, 0x00000000, // 0x23 + 0x1000b1b6, 0x01ffe000, 0x20500000, 0x00000000, // 0x24 + 0x100031b6, 0x01ffe000, 0x20500000, 0x00000000, // 0x25 + 0x1000b000, 0x01ffe000, 0x20500000, 0x00000000, // 0x26 + 0x10003000, 0x01ffe000, 0x20500000, 0x00000000, // 0x27 + 0x1000b049, 0x01ffe000, 0x20500000, 0x00000000, // 0x28 + 0x10003049, 0x01ffe000, 0x20500000, 0x00000000, // 0x29 +}; + +typedef struct { int x, y, z, w; } __sampler_t; + +__attribute__((const)) __constant __sampler_t * +__translate_sampler_initializer(int i) +{ + if (__oclc_ISA_version < 9000) { + return (__constant __sampler_t *)&SI_samplers[(i - 16) << 2]; + } else if (__oclc_ISA_version < 10000) { + return (__constant __sampler_t *)&GFX9_samplers[(i - 16) << 2]; + } else if (__oclc_ISA_version < 12000) { + return (__constant __sampler_t *)&GFX10_samplers[(i - 16) << 2]; + } else { + return (__constant __sampler_t *)&GFX12_samplers[(i - 16) << 2]; + } +} + diff --git a/amd/device-libs/opencl/src/integer/abs.cl b/amd/device-libs/opencl/src/integer/abs.cl new file mode 100644 index 0000000000000..040524eec6cd9 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/abs.cl @@ -0,0 +1,73 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define GENN(N,T) \ +ATTR u##T##N \ +abs(T##N x) \ +{ \ + int##N px = convert_int##N(x); \ + int##N nx = -px; \ + return convert_u##T##N(max(px,nx)); \ +} \ + \ +ATTR u##T##N \ +abs(u##T##N x) \ +{ \ + return x; \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GENN(,T) + +GEN(char) +GEN(short) + +#define LGENN(N,T) \ +ATTR u##T##N \ +abs(T##N x) \ +{ \ + return convert_u##T##N(select(-x, x, x > (T)0)); \ +} \ + \ +ATTR u##T##N \ +abs(u##T##N x) \ +{ \ + return x; \ +} + +#define LGEN1(T) \ +ATTR u##T \ +abs(T x) \ +{ \ + T mx = -x; \ + return as_u##T(x > (T)0 ? x : mx); \ +} \ + \ +ATTR u##T \ +abs(u##T x) \ +{ \ + return x; \ +} + +#define LGEN(T) \ + LGENN(16,T) \ + LGENN(8,T) \ + LGENN(4,T) \ + LGENN(3,T) \ + LGENN(2,T) \ + LGEN1(T) + +LGEN(int) +LGEN(long) + diff --git a/amd/device-libs/opencl/src/integer/abs_diff.cl b/amd/device-libs/opencl/src/integer/abs_diff.cl new file mode 100644 index 0000000000000..65cda0ddfa453 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/abs_diff.cl @@ -0,0 +1,72 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define GENN(N,T) \ +ATTR u##T##N \ +abs_diff(T##N x, T##N y) \ +{ \ + int##N xx = convert_int##N(x); \ + int##N yy = convert_int##N(y); \ + int##N d = max(xx,yy) - min(xx,yy); \ + return convert_u##T##N(d); \ +} \ + \ +ATTR u##T##N \ +abs_diff(u##T##N x, u##T##N y) \ +{ \ + uint##N xx = convert_uint##N(x); \ + uint##N yy = convert_uint##N(y); \ + uint##N d = max(xx,yy) - min(xx,yy); \ + return convert_u##T##N(d); \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GENN(,T) + +GEN(char) +GEN(short) + +// On the signed implementation, we intentionally use unsigned integers to +// avoid signed integer overflows, which result in undefined-behaviour +#define LGENN(N,T) \ +ATTR u##T##N \ +abs_diff(T##N x, T##N y) \ +{ \ + T##N c = x > y; \ + u##T##N xx = convert_u##T##N(x); \ + u##T##N yy = convert_u##T##N(y); \ + u##T##N xmy = xx - yy; \ + u##T##N ymx = yy - xx; \ + return select(ymx, xmy, c); \ +} \ + \ +ATTR u##T##N \ +abs_diff(u##T##N x, u##T##N y) \ +{ \ + T##N c = x > y; \ + u##T##N xmy = x - y; \ + u##T##N ymx = y - x; \ + return select(ymx, xmy, c); \ +} + +#define LGEN(T) \ + LGENN(16,T) \ + LGENN(8,T) \ + LGENN(4,T) \ + LGENN(3,T) \ + LGENN(2,T) \ + LGENN(,T) + +LGEN(int) +LGEN(long) diff --git a/amd/device-libs/opencl/src/integer/add_sat.cl b/amd/device-libs/opencl/src/integer/add_sat.cl new file mode 100644 index 0000000000000..f140ba7dc6dd9 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/add_sat.cl @@ -0,0 +1,73 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "int.h" + +#define ATTR __attribute__((overloadable, const)) + +#define char_min CHAR_MIN +#define char_max CHAR_MAX +#define short_min SHRT_MIN +#define short_max SHRT_MAX + +#define uchar_max UCHAR_MAX +#define ushort_max USHRT_MAX + +#define GENN(T) \ + ATTR T \ + add_sat(T x, T y) \ + { \ + T s; \ + bool c = __builtin_add_overflow(x, y, &s); \ + return c ? (x < 0 ? T##_min : T##_max) : s; \ + } \ + \ + ATTR u##T \ + add_sat(u##T x, u##T y) \ + { \ + u##T s; \ + bool c = __builtin_add_overflow(x, y, &s); \ + return c ? u##T##_max : s; \ + } + +GENN(char) +GENN(short) + +#define BEXPATTR __attribute__((overloadable)) +BEXP(char,add_sat) +BEXP(uchar,add_sat) +BEXP(short,add_sat) +BEXP(ushort,add_sat) +BEXP(int,add_sat) +BEXP(uint,add_sat) +BEXP(long,add_sat) +BEXP(ulong,add_sat) + +BEXPATTR int +add_sat(int x, int y) +{ + return __ockl_add_sat_i32(x, y); +} + +BEXPATTR uint +add_sat(uint x, uint y) +{ + return __ockl_add_sat_u32(x, y); +} + +BEXPATTR long +add_sat(long x, long y) +{ + return __ockl_add_sat_i64(x, y); +} + +BEXPATTR ulong +add_sat(ulong x, ulong y) +{ + return __ockl_add_sat_u64(x, y); +} + diff --git a/amd/device-libs/opencl/src/integer/clz.cl b/amd/device-libs/opencl/src/integer/clz.cl new file mode 100644 index 0000000000000..310d33728cf29 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/clz.cl @@ -0,0 +1,67 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "int.h" + +#define UEXPATTR __attribute__((overloadable, const)) +UEXP(char,clz) +UEXP(uchar,clz) +UEXP(short,clz) +UEXP(ushort,clz) +UEXP(int,clz) +UEXP(uint,clz) +UEXP(long,clz) +UEXP(ulong,clz) + +UEXPATTR char +clz(char x) +{ + return (char)OCKL_MANGLE_T(clz,u8)((uchar)x); +} + +UEXPATTR uchar +clz(uchar x) +{ + return OCKL_MANGLE_T(clz,u8)(x); +} + +UEXPATTR short +clz(short x) +{ + return (short)OCKL_MANGLE_T(clz,u16)((ushort)x); +} + +UEXPATTR ushort +clz(ushort x) +{ + return OCKL_MANGLE_T(clz,u16)(x); +} + +UEXPATTR int +clz(int x) +{ + return (int)OCKL_MANGLE_U32(clz)((uint)x); +} + +UEXPATTR uint +clz(uint x) +{ + return OCKL_MANGLE_U32(clz)(x); +} + +UEXPATTR long +clz(long x) +{ + return (long)OCKL_MANGLE_U64(clz)((ulong)x); +} + +UEXPATTR ulong +clz(ulong x) +{ + return OCKL_MANGLE_U64(clz)(x); +} + diff --git a/amd/device-libs/opencl/src/integer/ctz.cl b/amd/device-libs/opencl/src/integer/ctz.cl new file mode 100644 index 0000000000000..c978e220c2130 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/ctz.cl @@ -0,0 +1,67 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "int.h" + +#define UEXPATTR __attribute__((overloadable, const)) +UEXP(char,ctz) +UEXP(uchar,ctz) +UEXP(short,ctz) +UEXP(ushort,ctz) +UEXP(int,ctz) +UEXP(uint,ctz) +UEXP(long,ctz) +UEXP(ulong,ctz) + +UEXPATTR char +ctz(char x) +{ + return (char)OCKL_MANGLE_T(ctz,u8)((uchar)x); +} + +UEXPATTR uchar +ctz(uchar x) +{ + return OCKL_MANGLE_T(ctz,u8)(x); +} + +UEXPATTR short +ctz(short x) +{ + return (short)OCKL_MANGLE_T(ctz,u16)((ushort)x); +} + +UEXPATTR ushort +ctz(ushort x) +{ + return OCKL_MANGLE_T(ctz,u16)(x); +} + +UEXPATTR int +ctz(int x) +{ + return (uint)OCKL_MANGLE_U32(ctz)((uint)x); +} + +UEXPATTR uint +ctz(uint x) +{ + return OCKL_MANGLE_U32(ctz)(x); +} + +UEXPATTR long +ctz(long x) +{ + return (long)OCKL_MANGLE_U64(ctz)((ulong)x); +} + +UEXPATTR ulong +ctz(ulong x) +{ + return OCKL_MANGLE_U64(ctz)(x); +} + diff --git a/amd/device-libs/opencl/src/integer/hadd.cl b/amd/device-libs/opencl/src/integer/hadd.cl new file mode 100644 index 0000000000000..cf3775422f984 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/hadd.cl @@ -0,0 +1,54 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define GENN(N,T) \ +ATTR T##N \ +hadd(T##N x, T##N y) \ +{ \ + return convert_##T##N((convert_int##N(x) + convert_int##N(y)) >> 1); \ +} \ + \ +ATTR u##T##N \ +hadd(u##T##N x, u##T##N y) \ +{ \ + return convert_u##T##N((convert_uint##N(x) + convert_uint##N(y)) >> 1); \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GENN(,T) + +GEN(char) +GEN(short) + +#define LGENN(N,T) \ +ATTR T##N \ +hadd(T##N x, T##N y) \ +{ \ + T##N c = (x & (T)1) & y; \ + return (x >> 1) + (y >> 1) + c; \ +} + +#define LGEN(T) \ + LGENN(16,T) \ + LGENN(8,T) \ + LGENN(4,T) \ + LGENN(3,T) \ + LGENN(2,T) \ + LGENN(,T) + +LGEN(int) +LGEN(uint) +LGEN(long) +LGEN(ulong) + diff --git a/amd/device-libs/opencl/src/integer/iclamp.cl b/amd/device-libs/opencl/src/integer/iclamp.cl new file mode 100644 index 0000000000000..468204716f721 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/iclamp.cl @@ -0,0 +1,46 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define GENN(N,T) \ +ATTR T##N \ +clamp(T##N x, T lo, T hi) \ +{ \ + return min(max(x, lo), hi); \ +} \ + \ +ATTR T##N \ +clamp(T##N x, T##N lo, T##N hi) \ +{ \ + return min(max(x, lo), hi); \ +} + +#define GEN1(T) \ +ATTR T \ +clamp(T x, T lo, T hi) \ +{ \ + return min(max(x, lo), hi); \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GEN1(T) + +GEN(char) +GEN(uchar) +GEN(short) +GEN(ushort) +GEN(int) +GEN(uint) +GEN(long) +GEN(ulong) + diff --git a/amd/device-libs/opencl/src/integer/int.h b/amd/device-libs/opencl/src/integer/int.h new file mode 100644 index 0000000000000..8315358fee747 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/int.h @@ -0,0 +1,99 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ULIST2(F) F(x.s0), F(x.s1) +#define ULIST3(F) F(x.s0), F(x.s1), F(x.s2) +#define ULIST4(F) ULIST2(F), F(x.s2), F(x.s3) +#define ULIST8(F) ULIST4(F), F(x.s4), F(x.s5), F(x.s6), F(x.s7) +#define ULIST16(F) ULIST8(F), F(x.s8), F(x.s9), F(x.sa), F(x.sb), F(x.sc), F(x.sd), F(x.se), F(x.sf) + +#define UEXPN(N,T,F) \ +UEXPATTR T##N \ +F(T##N x) \ +{ \ + return (T##N) ( ULIST##N(F) ); \ +} + +#define UEXP(T,F) \ + UEXPN(16,T,F) \ + UEXPN(8,T,F) \ + UEXPN(4,T,F) \ + UEXPN(3,T,F) \ + UEXPN(2,T,F) + +#define BLIST2(F) F(x.s0, y.s0), F(x.s1, y.s1) +#define BLIST3(F) F(x.s0, y.s0), F(x.s1, y.s1), F(x.s2, y.s2) +#define BLIST4(F) BLIST2(F), F(x.s2, y.s2), F(x.s3, y.s3) +#define BLIST8(F) BLIST4(F), F(x.s4, y.s4), F(x.s5, y.s5), F(x.s6, y.s6), F(x.s7, y.s7) +#define BLIST16(F) BLIST8(F), F(x.s8, y.s8), F(x.s9, y.s9), F(x.sa, y.sa), F(x.sb, y.sb), F(x.sc, y.sc), F(x.sd, y.sd), F(x.se, y.se), F(x.sf, y.sf) + +#define BEXPN(N,T,F) \ +BEXPATTR T##N \ +F(T##N x, T##N y) \ +{ \ + return (T##N) ( BLIST##N(F) ); \ +} + +#define BEXP(T,F) \ + BEXPN(16,T,F) \ + BEXPN(8,T,F) \ + BEXPN(4,T,F) \ + BEXPN(3,T,F) \ + BEXPN(2,T,F) + +#define TLIST2(F) F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define TLIST3(F) F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1), F(a.s2, b.s2, c.s2) +#define TLIST4(F) TLIST2(F), F(a.s2, b.s2, c.s2), F(a.s3, b.s3, c.s3) +#define TLIST8(F) TLIST4(F), F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define TLIST16(F) TLIST8(F), F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + +#define TEXPN(N,T,F) \ +TEXPATTR T##N \ +F(T##N a, T##N b, T##N c) \ +{ \ + return (T##N) ( TLIST##N(F) ); \ +} + +#define TEXP(T,F) \ + TEXPN(16,T,F) \ + TEXPN(8,T,F) \ + TEXPN(4,T,F) \ + TEXPN(3,T,F) \ + TEXPN(2,T,F) + +static inline long +_gpu_mul_hi_i64(long x, long y) +{ + ulong x0 = (ulong)x & 0xffffffffUL; + long x1 = x >> 32; + ulong y0 = (ulong)y & 0xffffffffUL; + long y1 = y >> 32; + ulong z0 = x0*y0; + long t = x1*y0 + (z0 >> 32); + long z1 = t & 0xffffffffL; + long z2 = t >> 32; + z1 = x0*y1 + z1; + return x1*y1 + z2 + (z1 >> 32); +} + +static inline ulong +_gpu_mul_hi_u64(ulong x, ulong y) +{ + ulong x0 = x & 0xffffffffUL; + ulong x1 = x >> 32; + ulong y0 = y & 0xffffffffUL; + ulong y1 = y >> 32; + ulong z0 = x0*y0; + ulong t = x1*y0 + (z0 >> 32); + ulong z1 = t & 0xffffffffUL; + ulong z2 = t >> 32; + z1 = x0*y1 + z1; + return x1*y1 + z2 + (z1 >> 32); +} + diff --git a/amd/device-libs/opencl/src/integer/mad24.cl b/amd/device-libs/opencl/src/integer/mad24.cl new file mode 100644 index 0000000000000..9ee91a754f4a0 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/mad24.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "int.h" + +#define TEXPATTR __attribute__((overloadable, const)) + +TEXP(int,mad24) +TEXP(uint,mad24) + +TEXPATTR int +mad24(int a, int b, int c) +{ + return ((a << 8) >> 8) * ((b << 8) >> 8) + c; +} + +TEXPATTR uint +mad24(uint a, uint b, uint c) +{ + return ((a << 8) >> 8) * ((b << 8) >> 8) + c; +} + diff --git a/amd/device-libs/opencl/src/integer/mad_hi.cl b/amd/device-libs/opencl/src/integer/mad_hi.cl new file mode 100644 index 0000000000000..9116090e4d901 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/mad_hi.cl @@ -0,0 +1,33 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define GENN(N,T) \ +ATTR T##N \ +mad_hi(T##N a, T##N b, T##N c) \ +{ \ + return mul_hi(a, b) + c; \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GENN(,T) + +GEN(char) +GEN(uchar) +GEN(short) +GEN(ushort) +GEN(int) +GEN(uint) +GEN(long) +GEN(ulong) + diff --git a/amd/device-libs/opencl/src/integer/mad_sat.cl b/amd/device-libs/opencl/src/integer/mad_sat.cl new file mode 100644 index 0000000000000..8852cbf430645 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/mad_sat.cl @@ -0,0 +1,105 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "int.h" + +#define TEXPATTR __attribute__((overloadable, const)) + +TEXP(char,mad_sat) +TEXP(uchar,mad_sat) +TEXP(short,mad_sat) +TEXP(ushort,mad_sat) +TEXP(int,mad_sat) +TEXP(uint,mad_sat) +TEXP(long,mad_sat) +TEXP(ulong,mad_sat) + +TEXPATTR char +mad_sat(char a, char b, char c) +{ + return (char)clamp(mad24((int)a, (int)b, (int)c), CHAR_MIN, CHAR_MAX); +} + +TEXPATTR uchar +mad_sat(uchar a, uchar b, uchar c) +{ + return (uchar)min(mad24((uint)a, (uint)b, (uint)c), (uint)UCHAR_MAX); +} + +TEXPATTR short +mad_sat(short a, short b, short c) +{ + return (short)clamp(mad24((int)a, (int)b, (int)c), SHRT_MIN, SHRT_MAX); +} + +TEXPATTR ushort +mad_sat(ushort a, ushort b, ushort c) +{ + return (ushort)min(mad24((uint)a, (uint)b, (uint)c), (uint)USHRT_MAX); +} + +TEXPATTR int +mad_sat(int a, int b, int c) +{ + long d = as_long((int2)(a * b, mul_hi(a, b))) + (long)c; + return (int)clamp(d, (long)INT_MIN, (long)INT_MAX); +} + +TEXPATTR uint +mad_sat(uint a, uint b, uint c) +{ + ulong d = as_ulong((uint2)(a * b, mul_hi(a, b))) + (ulong)c; + return (uint)min(d, (ulong)UINT_MAX); +} + +TEXPATTR long +mad_sat(long a, long b, long c) +{ + ulong a0 = (ulong)a & 0xffffffffUL; + long a1 = a >> 32; + ulong b0 = (ulong)b & 0xffffffffUL; + long b1 = b >> 32; + ulong s0 = a0*b0; + long t = a1*b0 + (s0 >> 32); + long s1 = a0*b1 + (t & 0xffffffffL); + long s2 = t >> 32; + long lo = (s1 << 32) | (s0 & 0xffffffffL); + long hi = a1*b1 + s2 + (s1 >> 32); + + t = lo + c; + hi += ((ulong)0xffffffffffffffffUL - (ulong)c < (ulong)lo); + lo = t; + hi -= c < 0L; + + lo = (hi < 0L) & ((hi != -1L) | (lo >= 0L)) ? 0x8000000000000000L : lo; + lo = (hi >= 0L) & ((hi > 0L) | (lo < 0L)) ? 0x7fffffffffffffffL : lo; + + return lo; +} + +TEXPATTR ulong +mad_sat(ulong a, ulong b, ulong c) +{ + ulong a0 = a & 0xffffffffUL; + ulong a1 = a >> 32; + ulong b0 = b & 0xffffffffUL; + ulong b1 = b >> 32; + ulong s0 = a0*b0; + ulong t = a1*b0 + (s0 >> 32); + ulong s1 = t & 0xffffffffUL; + ulong s2 = t >> 32; + s1 = a0*b1 + s1; + ulong lo = (s1 << 32) | (s0 & 0xffffffffUL); + ulong hi = a1*b1 + s2 + (s1 >> 32); + + t = lo + c; + hi += 0xffffffffffffffffUL - c < lo; + lo = t; + + return hi > 0UL ? 0xffffffffffffffffUL : lo; +} + diff --git a/amd/device-libs/opencl/src/integer/max.cl b/amd/device-libs/opencl/src/integer/max.cl new file mode 100644 index 0000000000000..44dd09b1a6148 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/max.cl @@ -0,0 +1,47 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define GENN(N,T) \ +ATTR T##N \ +max(T##N x, T y) \ +{ \ + T##N vy = (T##N)y; \ + return select(x, vy, x < vy); \ +} \ + \ +ATTR T##N \ +max(T##N x, T##N y) \ +{ \ + return select(x, y, x < y); \ +} + +#define GEN1(T) \ +ATTR T \ +max(T x, T y) \ +{ \ + return x < y ? y : x; \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GEN1(T) + +GEN(char) +GEN(uchar) +GEN(short) +GEN(ushort) +GEN(int) +GEN(uint) +GEN(long) +GEN(ulong) + diff --git a/amd/device-libs/opencl/src/integer/min.cl b/amd/device-libs/opencl/src/integer/min.cl new file mode 100644 index 0000000000000..8fdadde5c1b07 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/min.cl @@ -0,0 +1,47 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define GENN(N,T) \ +ATTR T##N \ +min(T##N x, T y) \ +{ \ + T##N yv = (T##N)y; \ + return select(x, yv, yv < x); \ +} \ + \ +ATTR T##N \ +min(T##N x, T##N y) \ +{ \ + return select(x, y, y < x); \ +} + +#define GEN1(T) \ +ATTR T \ +min(T x, T y) \ +{ \ + return y < x ? y : x; \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GEN1(T) + +GEN(char) +GEN(uchar) +GEN(short) +GEN(ushort) +GEN(int) +GEN(uint) +GEN(long) +GEN(ulong) + diff --git a/amd/device-libs/opencl/src/integer/mul24.cl b/amd/device-libs/opencl/src/integer/mul24.cl new file mode 100644 index 0000000000000..faff767c7b033 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/mul24.cl @@ -0,0 +1,26 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "int.h" + +#define BEXPATTR __attribute__((overloadable, const)) + +BEXP(int,mul24) +BEXP(uint,mul24) + +BEXPATTR int +mul24(int x, int y) +{ + return __ockl_mul24_i32(x, y); +} + +BEXPATTR uint +mul24(uint x, uint y) +{ + return __ockl_mul24_u32(x, y); +} + diff --git a/amd/device-libs/opencl/src/integer/mul_hi.cl b/amd/device-libs/opencl/src/integer/mul_hi.cl new file mode 100644 index 0000000000000..98e503844f065 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/mul_hi.cl @@ -0,0 +1,68 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "int.h" + +#define ATTR __attribute__((overloadable, const)) + +#define char_shift 8 +#define short_shift 16 + +#define GENN(N,T) \ +ATTR T##N \ +mul_hi(T##N x, T##N y) \ +{ \ + return convert_##T##N(mul24(convert_int##N(x), convert_int##N(y)) >> T##_shift); \ +} \ + \ +ATTR u##T##N \ +mul_hi(u##T##N x, u##T##N y) \ +{ \ + return convert_u##T##N(mul24(convert_uint##N(x), convert_uint##N(y)) >> T##_shift); \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GENN(,T) + +GEN(char) +GEN(short) + +#define BEXPATTR ATTR +BEXP(int,mul_hi) +BEXP(uint,mul_hi) +BEXP(long,mul_hi) +BEXP(ulong,mul_hi) + +BEXPATTR int +mul_hi(int x, int y) +{ + return __ockl_mul_hi_i32(x, y); +} + +BEXPATTR uint +mul_hi(uint x, uint y) +{ + return __ockl_mul_hi_u32(x, y); +} + +BEXPATTR long +mul_hi(long x, long y) +{ + return __ockl_mul_hi_i64(x, y); +} + +BEXPATTR ulong +mul_hi(ulong x, ulong y) +{ + return __ockl_mul_hi_u64(x, y); +} + diff --git a/amd/device-libs/opencl/src/integer/popcount.cl b/amd/device-libs/opencl/src/integer/popcount.cl new file mode 100644 index 0000000000000..029ad12bbdc31 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/popcount.cl @@ -0,0 +1,68 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "int.h" + +#define UEXPATTR __attribute__((overloadable, const)) + +UEXP(char,popcount) +UEXP(uchar,popcount) +UEXP(short,popcount) +UEXP(ushort,popcount) +UEXP(int,popcount) +UEXP(uint,popcount) +UEXP(long,popcount) +UEXP(ulong,popcount) + +UEXPATTR char +popcount(char x) +{ + return (char)__ockl_popcount_u32((uint)(uchar)x); +} + +UEXPATTR uchar +popcount(uchar x) +{ + return (uchar)__ockl_popcount_u32((uint)x); +} + +UEXPATTR short +popcount(short x) +{ + return (short)__ockl_popcount_u32((uint)(ushort)x); +} + +UEXPATTR ushort +popcount(ushort x) +{ + return (ushort)__ockl_popcount_u32((uint)x); +} + +UEXPATTR int +popcount(int x) +{ + return (int)__ockl_popcount_u32((uint)x); +} + +UEXPATTR uint +popcount(uint x) +{ + return __ockl_popcount_u32(x); +} + +UEXPATTR long +popcount(long x) +{ + return (long)__ockl_popcount_u64((ulong)x); +} + +UEXPATTR ulong +popcount(ulong x) +{ + return __ockl_popcount_u64(x); +} + diff --git a/amd/device-libs/opencl/src/integer/rhadd.cl b/amd/device-libs/opencl/src/integer/rhadd.cl new file mode 100644 index 0000000000000..b6bd677b475f4 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/rhadd.cl @@ -0,0 +1,54 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define GENN(N,T) \ +ATTR T##N \ +rhadd(T##N x, T##N y) \ +{ \ + return convert_##T##N((convert_int##N(x) + convert_int##N(y) + 1) >> 1); \ +} \ + \ +ATTR u##T##N \ +rhadd(u##T##N x, u##T##N y) \ +{ \ + return convert_u##T##N((convert_uint##N(x) + convert_uint##N(y) + 1U) >> 1); \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GENN(,T) + +GEN(char) +GEN(short) + +#define LGENN(N,T) \ +ATTR T##N \ +rhadd(T##N x, T##N y) \ +{ \ + T##N c = (x | y) & (T)1; \ + return (x >> 1) + (y >> 1) + c; \ +} + +#define LGEN(T) \ + LGENN(16,T) \ + LGENN(8,T) \ + LGENN(4,T) \ + LGENN(3,T) \ + LGENN(2,T) \ + LGENN(,T) + +LGEN(int) +LGEN(uint) +LGEN(long) +LGEN(ulong) + diff --git a/amd/device-libs/opencl/src/integer/rotate.cl b/amd/device-libs/opencl/src/integer/rotate.cl new file mode 100644 index 0000000000000..8fb101a3b2a2d --- /dev/null +++ b/amd/device-libs/opencl/src/integer/rotate.cl @@ -0,0 +1,71 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "int.h" + +#define ATTR __attribute__((overloadable, const)) + +#define char_bits 8 +#define short_bits 16 +#define int_bits 32 +#define long_bits 64 + +#define GENN(N,T) \ +ATTR T##N \ +rotate(T##N x, T##N y) \ +{ \ + uint##N s = convert_uint##N(as_u##T##N(y)) & (uint)(T##_bits - 1); \ + uint##N v = convert_uint##N(as_u##T##N(x)); \ + return convert_##T##N((v << s) | (v >> (T##_bits - s))); \ +} \ + \ +ATTR u##T##N \ +rotate(u##T##N x, u##T##N y) \ +{ \ + uint##N s = convert_uint##N(y) & (uint)(T##_bits - 1); \ + uint##N v = convert_uint##N(x); \ + return convert_u##T##N((v << s) | (v >> ((uint)T##_bits - s))); \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GENN(,T) + +GEN(char) +GEN(short) + +#define LGENN(N,T) \ +ATTR T##N \ +rotate(T##N x, T##N y) \ +{ \ + u##T##N s = as_u##T##N(y) & (u##T)(T##_bits - 1); \ + u##T##N v = as_u##T##N(x); \ + return as_##T##N((v << s) | (v >> ((u##T)T##_bits - s))); \ +} \ + \ +ATTR u##T##N \ +rotate(u##T##N x, u##T##N y) \ +{ \ + y &= (u##T)(T##_bits - 1); \ + return (x << y) | (x >> ((u##T)T##_bits - y)); \ +} + +#define LGEN(T) \ + LGENN(16,T) \ + LGENN(8,T) \ + LGENN(4,T) \ + LGENN(3,T) \ + LGENN(2,T) \ + LGENN(,T) + +LGEN(int) +LGEN(long) + diff --git a/amd/device-libs/opencl/src/integer/sub_sat.cl b/amd/device-libs/opencl/src/integer/sub_sat.cl new file mode 100644 index 0000000000000..1ff127a97a801 --- /dev/null +++ b/amd/device-libs/opencl/src/integer/sub_sat.cl @@ -0,0 +1,73 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "int.h" + +#define ATTR __attribute__((overloadable, const)) + +#define char_min CHAR_MIN +#define char_max CHAR_MAX +#define short_min SHRT_MIN +#define short_max SHRT_MAX + +#define uchar_max UCHAR_MAX +#define ushort_max USHRT_MAX + +#define GENN(T) \ + ATTR T \ + sub_sat(T x, T y) \ + { \ + T s; \ + bool c = __builtin_sub_overflow(x, y, &s); \ + return c ? (x < 0 ? T##_min : T##_max) : s; \ + } \ + \ + ATTR u##T \ + sub_sat(u##T x, u##T y) \ + { \ + u##T s; \ + bool c = __builtin_sub_overflow(x, y, &s); \ + return c ? 0 : s; \ + } + +GENN(char) +GENN(short) + +#define BEXPATTR __attribute__((overloadable)) +BEXP(char,sub_sat) +BEXP(uchar,sub_sat) +BEXP(short,sub_sat) +BEXP(ushort,sub_sat) +BEXP(int,sub_sat) +BEXP(uint,sub_sat) +BEXP(long,sub_sat) +BEXP(ulong,sub_sat) + +BEXPATTR int +sub_sat(int x, int y) +{ + return __ockl_sub_sat_i32(x, y); +} + +BEXPATTR uint +sub_sat(uint x, uint y) +{ + return __ockl_sub_sat_u32(x, y); +} + +BEXPATTR long +sub_sat(long x, long y) +{ + return __ockl_sub_sat_i64(x, y); +} + +BEXPATTR ulong +sub_sat(ulong x, ulong y) +{ + return __ockl_sub_sat_u64(x, y); +} + diff --git a/amd/device-libs/opencl/src/integer/upsample.cl b/amd/device-libs/opencl/src/integer/upsample.cl new file mode 100644 index 0000000000000..a6970133f14ce --- /dev/null +++ b/amd/device-libs/opencl/src/integer/upsample.cl @@ -0,0 +1,62 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define ATTR __attribute__((overloadable, const)) + +#define char_shift 8 +#define short_shift 16 + +#define char_up short +#define short_up int + +#define GENN(N,T) \ +ATTR C(T##_up,N) \ +upsample(T##N hi, u##T##N lo) \ +{ \ + return C(convert_,C(T##_up,N))((convert_uint##N(as_u##T##N(hi)) << T##_shift) | convert_uint##N(lo)); \ +} \ + \ +ATTR C(u,C(T##_up,N)) \ +upsample(u##T##N hi, u##T##N lo) \ +{ \ + return C(convert_u,C(T##_up,N))((convert_uint##N(hi) << T##_shift) | convert_uint##N(lo)); \ +} + +#define GEN(T) \ + GENN(16,T) \ + GENN(8,T) \ + GENN(4,T) \ + GENN(3,T) \ + GENN(2,T) \ + GENN(,T) + +GEN(char) +GEN(short) + +#define LGEN(N) \ +ATTR long##N \ +upsample(int##N hi, uint##N lo) \ +{ \ + return as_long##N((convert_ulong##N(as_uint##N(hi)) << 32) | convert_ulong##N(lo)); \ +} \ + \ +ATTR ulong##N \ +upsample(uint##N hi, uint##N lo) \ +{ \ + return (convert_ulong##N(hi) << 32) | convert_ulong##N(lo); \ +} + +LGEN(16) +LGEN(8) +LGEN(4) +LGEN(3) +LGEN(2) +LGEN() + diff --git a/amd/device-libs/opencl/src/math/halfmath.cl b/amd/device-libs/opencl/src/math/halfmath.cl new file mode 100644 index 0000000000000..46d1f4940b130 --- /dev/null +++ b/amd/device-libs/opencl/src/math/halfmath.cl @@ -0,0 +1,212 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +struct redret { + int i; + float r; +}; + +// For trigs +extern struct redret __half_red(float); +extern float2 __half_scr(float); +extern float __half_tr(float, int); + +#define IATTR __attribute__((overloadable)) +#define CATTR __attribute__((overloadable, const)) + +#if !defined USE_CLP +#define LISTU2(F) F(x.s0), F(x.s1) +#define LISTU3(F) F(x.s0), F(x.s1), F(x.s2) +#define LISTU4(F) LISTU2(F), F(x.s2), F(x.s3) +#define LISTU8(F) LISTU4(F), F(x.s4), F(x.s5), F(x.s6), F(x.s7) +#define LISTU16(F) LISTU8(F), F(x.s8), F(x.s9), F(x.sa), F(x.sb), \ + F(x.sc), F(x.sd), F(x.se), F(x.sf) + +#define EXPUN(N,F) \ +IATTR float##N \ +F(float##N x) \ +{ \ + return (float##N) ( LISTU##N(F) ); \ +} + +#define EXPU(F) \ + EXPUN(16,F) \ + EXPUN(8,F) \ + EXPUN(4,F) \ + EXPUN(3,F) \ + EXPUN(2,F) + +#define LISTB2(F) F(x.s0,y.s0), F(x.s1,y.s1) +#define LISTB3(F) F(x.s0,y.s0), F(x.s1,y.s1), F(x.s2,y.s2) +#define LISTB4(F) LISTB2(F), F(x.s2,y.s2), F(x.s3,y.s3) +#define LISTB8(F) LISTB4(F), F(x.s4,y.s4), F(x.s5,y.s5), F(x.s6,y.s6), F(x.s7,y.s7) +#define LISTB16(F) LISTB8(F), F(x.s8,y.s8), F(x.s9,y.s9), F(x.sa,y.sa), F(x.sb,y.sb), \ + F(x.sc,y.sc), F(x.sd,y.sd), F(x.se,y.se), F(x.sf,y.sf) + +#define EXPBN(N,F) \ +IATTR float##N \ +F(float##N x, float##N y) \ +{ \ + return (float##N) ( LISTB##N(F) ); \ +} + +#define EXPB(F) \ + EXPBN(16,F) \ + EXPBN(8,F) \ + EXPBN(4,F) \ + EXPBN(3,F) \ + EXPBN(2,F) + +EXPB(half_divide) +EXPB(half_powr) +EXPU(half_cos) +EXPU(half_exp2) +EXPU(half_exp) +EXPU(half_exp10) +EXPU(half_log2) +EXPU(half_log) +EXPU(half_log10) +EXPU(half_recip) +EXPU(half_rsqrt) +EXPU(half_sin) +EXPU(half_sqrt) +EXPU(half_tan) +#endif // !USE_CLP + +CATTR float +half_divide(float x, float y) +{ + return x / y; +} + +IATTR float +half_powr(float x, float y) +{ + return powr(x, y); +} + +IATTR float +half_cos(float x) +{ + float dx = fabs(x); + int ax = as_int(dx); + + + struct redret red =__half_red(dx); + float r0 = red.r; + int regn = red.i; + + float2 scr = __half_scr(r0); + float cc = scr.y; + float ss = -scr.x; + + float c = (regn & 1) != 0 ? ss : cc; + c = as_float(as_int(c) ^ ((regn > 1) << 31)); + + c = ax > 0x47800000 ? 1.0f : c; + c = ax >= 0x7f800000 ? as_float(0x7fc00000) : c; + return c; +} + +CATTR float +half_exp2(float x) +{ + return native_exp2(x); +} + +CATTR float +half_exp(float x) +{ + return native_exp(x); +} + +CATTR float +half_exp10(float x) +{ + return native_exp10(x); +} + +CATTR float +half_log2(float x) +{ + return native_log2(x); +} + +CATTR float +half_log(float x) +{ + return native_log(x); +} + +CATTR float +half_log10(float x) +{ + return native_log10(x); +} + +CATTR float +half_recip(float x) +{ + return native_recip(x); +} + +CATTR float +half_rsqrt(float x) +{ + return native_rsqrt(x); +} + +IATTR float +half_sin(float x) +{ + int ix = as_int(x); + float dx = fabs(x); + int ax = as_int(dx); + + struct redret red = __half_red(dx); + float r0 = red.r; + int regn = red.i; + + float2 scr = __half_scr(r0); + float ss = scr.x; + float cc = scr.y; + + float s = (regn & 1) != 0 ? cc : ss; + s = as_float(as_int(s) ^ ((regn > 1) << 31)); + + s = ax > 0x47800000 ? 1.0f : s; + s = as_float(as_int(s) ^ (ix ^ ax)); + s = x == 0.0f ? x : s; + s = ax >= 0x7f800000 ? as_float(0x7fc00000) : s; + return s; +} + +CATTR float +half_sqrt(float x) +{ + return native_sqrt(x); +} + +IATTR float +half_tan(float x) +{ + int ix = as_int(x); + float dx = fabs(x); + int ax = as_int(dx); + + struct redret red = __half_red(dx); + float r0 = red.r; + int regn = red.i; + float t = __half_tr(r0, regn); + + t = as_float(as_int(t) ^ (ix ^ ax)); + t = x == 0.0f ? x : t; + t = ax > 0x47800000 ? 0.0f : t; + t = ax >= 0x7f800000 ? as_float(0x7fc00000) : t; + return t; +} + diff --git a/amd/device-libs/opencl/src/math/halfred.cl b/amd/device-libs/opencl/src/math/halfred.cl new file mode 100644 index 0000000000000..ddcf07f6c1894 --- /dev/null +++ b/amd/device-libs/opencl/src/math/halfred.cl @@ -0,0 +1,39 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +// Trigonometric reduction for half_cos,sin,tan + +struct redret { + int i; + float r; +}; + +struct redret +__half_red(float x) +{ + const float twobypi = 0x1.45f306p-1f; + const float pb2_a = 0x1.92p+0f; + const float pb2_b = 0x1.fap-12f; + const float pb2_c = 0x1.54p-20f; + const float pb2_d = 0x1.10p-30f; + const float pb2_e = 0x1.68p-39f; + const float pb2_f = 0x1.846988p-48f; + + float fn = rint(x * twobypi); + + struct redret ret; + ret.i = (int)fn & 0x3; + ret.r = mad(fn, -pb2_f, + mad(fn, -pb2_e, + mad(fn, -pb2_d, + mad(fn, -pb2_c, + mad(fn, -pb2_b, + mad(fn, -pb2_a, x)))))); + + return ret; +} + diff --git a/amd/device-libs/opencl/src/math/halfscr.cl b/amd/device-libs/opencl/src/math/halfscr.cl new file mode 100644 index 0000000000000..b8ff43c1feb04 --- /dev/null +++ b/amd/device-libs/opencl/src/math/halfscr.cl @@ -0,0 +1,17 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +float2 +__half_scr(float x) +{ + float y = x * 0x1.45f306p-3f; + float s = __builtin_amdgcn_sinf(y); + float result = fabs(x) < 0x1.0p-20f ? x : s; + + return (float2)(result, __builtin_amdgcn_cosf(y) ); +} + diff --git a/amd/device-libs/opencl/src/math/halftr.cl b/amd/device-libs/opencl/src/math/halftr.cl new file mode 100644 index 0000000000000..7c6773d92a57c --- /dev/null +++ b/amd/device-libs/opencl/src/math/halftr.cl @@ -0,0 +1,24 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +__attribute__((const)) float +__half_tr(float x, int regn) +{ + float r = x * x; + + float a = mad(r, -0.0172032480471481694693109f, 0.385296071263995406715129f); + + float b = mad(r, + mad(r, 0.01844239256901656082986661f, -0.51396505478854532132342f), + 1.15588821434688393452299f); + + float t = mad(x*r, a * __builtin_amdgcn_rcpf(b), x); + float tr = -__builtin_amdgcn_rcpf(t); + + return regn & 1 ? tr : t; +} + diff --git a/amd/device-libs/opencl/src/math/native.cl b/amd/device-libs/opencl/src/math/native.cl new file mode 100644 index 0000000000000..706d91273b105 --- /dev/null +++ b/amd/device-libs/opencl/src/math/native.cl @@ -0,0 +1,151 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#define ATTR __attribute__((overloadable, const)) + +#if !defined USE_CLP +#define LISTU2(F) F(x.s0), F(x.s1) +#define LISTU3(F) F(x.s0), F(x.s1), F(x.s2) +#define LISTU4(F) LISTU2(F), F(x.s2), F(x.s3) +#define LISTU8(F) LISTU4(F), F(x.s4), F(x.s5), F(x.s6), F(x.s7) +#define LISTU16(F) LISTU8(F), F(x.s8), F(x.s9), F(x.sa), F(x.sb), \ + F(x.sc), F(x.sd), F(x.se), F(x.sf) + +#define EXPUN(N,F) \ +ATTR float##N \ +F(float##N x) \ +{ \ + return (float##N) ( LISTU##N(F) ); \ +} + +#define EXPU(F) \ + EXPUN(16,F) \ + EXPUN(8,F) \ + EXPUN(4,F) \ + EXPUN(3,F) \ + EXPUN(2,F) + +#define LISTB2(F) F(x.s0,y.s0), F(x.s1,y.s1) +#define LISTB3(F) F(x.s0,y.s0), F(x.s1,y.s1), F(x.s2,y.s2) +#define LISTB4(F) LISTB2(F), F(x.s2,y.s2), F(x.s3,y.s3) +#define LISTB8(F) LISTB4(F), F(x.s4,y.s4), F(x.s5,y.s5), F(x.s6,y.s6), F(x.s7,y.s7) +#define LISTB16(F) LISTB8(F), F(x.s8,y.s8), F(x.s9,y.s9), F(x.sa,y.sa), F(x.sb,y.sb), \ + F(x.sc,y.sc), F(x.sd,y.sd), F(x.se,y.se), F(x.sf,y.sf) + +#define EXPBN(N,F) \ +ATTR float##N \ +F(float##N x, float##N y) \ +{ \ + return (float##N) ( LISTB##N(F) ); \ +} + +#define EXPB(F) \ + EXPBN(16,F) \ + EXPBN(8,F) \ + EXPBN(4,F) \ + EXPBN(3,F) \ + EXPBN(2,F) + + +EXPB(native_divide) +EXPB(native_powr) +EXPU(native_tan) +EXPU(native_cos) +EXPU(native_exp) +EXPU(native_exp2) +EXPU(native_exp10) +EXPU(native_log) +EXPU(native_log2) +EXPU(native_log10) +EXPU(native_recip) +EXPU(native_rsqrt) +EXPU(native_sin) +EXPU(native_sqrt) +#endif // !USE_CLP + +ATTR float +native_divide(float x, float y) +{ + return x * native_recip(y); +} + +ATTR float +native_powr(float x, float y) +{ + return native_exp2(native_log2(x)*y); +} + +ATTR float +native_tan(float x) +{ + x *= 0x1.45f306p-3f; + return native_sin(x) * native_recip(native_cos(x)); +} + +ATTR float +native_cos(float x) +{ + return __ocml_native_cos_f32(x); +} + +ATTR float +native_exp2(float x) +{ + return __ocml_native_exp2_f32(x); +} + +ATTR float +native_exp(float f) { + return __ocml_native_exp_f32(f); +} + +ATTR float +native_exp10(float f) +{ + return __ocml_native_exp10_f32(f); +} + +ATTR float +native_log2(float x) { + return __ocml_native_log2_f32(x); +} + +ATTR float +native_log(float f) +{ + return __ocml_native_log_f32(f); +} + +ATTR float +native_log10(float f) +{ + return __ocml_native_log10_f32(f); +} + +ATTR float +native_recip(float x) { + return __ocml_native_recip_f32(x); +} + +ATTR float +native_rsqrt(float x) +{ + return __ocml_native_rsqrt_f32(x); +} + +ATTR float +native_sin(float x) { + return __ocml_native_sin_f32(x); +} + +ATTR float +native_sqrt(float x) { + return __ocml_native_sqrt_f32(x); +} + diff --git a/amd/device-libs/opencl/src/math/wrapb.cl b/amd/device-libs/opencl/src/math/wrapb.cl new file mode 100644 index 0000000000000..fc54779353d28 --- /dev/null +++ b/amd/device-libs/opencl/src/math/wrapb.cl @@ -0,0 +1,106 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define ATTR __attribute__((overloadable)) + +#define float_ssuf _f32 +#define double_ssuf _f64 +#define half_ssuf _f16 +#define half_psuf _2f16 + +#define SNAME(F,T) C(__ocml_,C(F,T##_ssuf)) +#define PNAME(F,T) C(__ocml_,C(F,T##_psuf)) + +#define SLST2(F,T) SNAME(F,T)(x.s0,y.s0), SNAME(F,T)(x.s1,y.s1) +#define SLST3(F,T) SNAME(F,T)(x.s0,y.s0), SNAME(F,T)(x.s1,y.s1), SNAME(F,T)(x.s2,y.s2) +#define SLST4(F,T) SLST2(F,T), SNAME(F,T)(x.s2,y.s2), SNAME(F,T)(x.s3,y.s3) +#define SLST8(F,T) SLST4(F,T), SNAME(F,T)(x.s4,y.s4), SNAME(F,T)(x.s5,y.s5), SNAME(F,T)(x.s6,y.s6), SNAME(F,T)(x.s7,y.s7) +#define SLST16(F,T) SLST8(F,T), SNAME(F,T)(x.s8,y.s8), SNAME(F,T)(x.s9,y.s9), SNAME(F,T)(x.sa,y.sa), SNAME(F,T)(x.sb,y.sb), \ + SNAME(F,T)(x.sc,y.sc), SNAME(F,T)(x.sd,y.sd), SNAME(F,T)(x.se,y.se), SNAME(F,T)(x.sf,y.sf) + +#define PLST3(F,T) PNAME(F,T)(x.s01,y.s01), SNAME(F,T)(x.s2,y.s2) +#define PLST4(F,T) PNAME(F,T)(x.s01,y.s01), PNAME(F,T)(x.s23,y.s23) +#define PLST8(F,T) PLST4(F,T), PNAME(F,T)(x.s45,y.s45),PNAME(F,T)(x.s67,y.s67) +#define PLST16(F,T) PLST8(F,T), PNAME(F,T)(x.s89,y.s89),PNAME(F,T)(x.sab,y.sab), PNAME(F,T)(x.scd,y.scd),PNAME(F,T)(x.sef,y.sef) + +#define SWRAPNT(N,F,T) \ +ATTR T##N \ +F(T##N x, T##N y) \ +{ \ + return (T##N) ( SLST##N(F,T) ); \ +} + +#define PWRAPNT(N,F,T) \ +ATTR T##N \ +F(T##N x, T##N y) \ +{ \ + return (T##N) ( PLST##N(F,T) ); \ +} + +#define WRAP1T(F,T) \ +ATTR T \ +F(T x, T y) \ +{ \ + return SNAME(F,T)(x, y); \ +} + +#define WRAP2T(F,T) \ +ATTR T##2 \ +F(T##2 x, T##2 y) \ +{ \ + return PNAME(F,T)(x, y); \ +} + +#define SWRAPT(F,T) \ + SWRAPNT(16,F,T) \ + SWRAPNT(8,F,T) \ + SWRAPNT(4,F,T) \ + SWRAPNT(3,F,T) \ + SWRAPNT(2,F,T) \ + WRAP1T(F,T) + +#define PWRAPT(F,T) \ + PWRAPNT(16,F,T) \ + PWRAPNT(8,F,T) \ + PWRAPNT(4,F,T) \ + PWRAPNT(3,F,T) \ + WRAP2T(F,T) \ + WRAP1T(F,T) + +#if !defined USE_CLP +#define WRAP(F) \ + SWRAPT(F,float) \ + SWRAPT(F,double) \ + PWRAPT(F,half) +#else +#define WRAP(F) \ + WRAP1T(F,float) \ + WRAP1T(F,double) \ + WRAP1T(F,half) \ + WRAP2T(F,half) +#endif + +WRAP(atan2) +WRAP(atan2pi) +WRAP(copysign) +WRAP(fdim) +WRAP(fmod) +WRAP(hypot) +WRAP(maxmag) +WRAP(minmag) +WRAP(nextafter) +WRAP(pow) +WRAP(powr) +WRAP(remainder) + diff --git a/amd/device-libs/opencl/src/math/wrapbp.cl b/amd/device-libs/opencl/src/math/wrapbp.cl new file mode 100644 index 0000000000000..7facd94c8dba9 --- /dev/null +++ b/amd/device-libs/opencl/src/math/wrapbp.cl @@ -0,0 +1,140 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define ATTR __attribute__((overloadable)) + +#define float_ssuf _f32 +#define double_ssuf _f64 +#define half_ssuf _f16 +#define half_psuf _2f16 + +#define SNAME(F,T) C(__ocml_,C(F,T##_ssuf)) +#define PNAME(F,T) C(__ocml_,C(F,T##_psuf)) + +#define SEVN(N,F,T,P) \ + P v##N; \ + T r##N = SNAME(F,T)(x.s##N, &v##N) + +#define PEVN(N,F,T,P) \ + P##2 v##N; \ + T##2 r##N = PNAME(F,T)(x.s##N, &v##N) + +#define SEVAL2(F,T,P) SEVN(0,F,T,P); SEVN(1,F,T,P) +#define SEVAL3(F,T,P) SEVAL2(F,T,P); SEVN(2,F,T,P) +#define SEVAL4(F,T,P) SEVAL2(F,T,P); SEVN(2,F,T,P); SEVN(3,F,T,P) +#define SEVAL8(F,T,P) SEVAL4(F,T,P); SEVN(4,F,T,P); SEVN(5,F,T,P); SEVN(6,F,T,P); SEVN(7,F,T,P) +#define SEVAL16(F,T,P) SEVAL8(F,T,P); SEVN(8,F,T,P); SEVN(9,F,T,P); SEVN(a,F,T,P); SEVN(b,F,T,P); SEVN(c,F,T,P); SEVN(d,F,T,P); SEVN(e,F,T,P); SEVN(f,F,T,P) + +#define PEVAL3(F,T,P) PEVN(01,F,T,P); SEVN(2,F,T,P) +#define PEVAL4(F,T,P) PEVN(01,F,T,P); PEVN(23,F,T,P) +#define PEVAL8(F,T,P) PEVAL4(F,T,P); PEVN(45,F,T,P); PEVN(67,F,T,P) +#define PEVAL16(F,T,P) PEVAL8(F,T,P); PEVN(89,F,T,P); PEVN(ab,F,T,P); PEVN(cd,F,T,P); PEVN(ef,F,T,P) + +#define SLST2(V) V##0, V##1 +#define SLST3(V) SLST2(V), V##2 +#define SLST4(V) SLST2(V), V##2, V##3 +#define SLST8(V) SLST4(V), V##4, V##5, V##6, V##7 +#define SLST16(V) SLST8(V), V##8, V##9, V##a, V##b, V##c, V##d, V##e, V##f + +#define PLST3(V) V##01, V##2 +#define PLST4(V) V##01, V##23 +#define PLST8(V) PLST4(V), V##45, V##67 +#define PLST16(V) PLST8(V), V##89, V##ab, V##cd, V##ef + +#define SWRAPNTAP(N,F,T,A,P) \ +ATTR T##N \ +F(T##N x, A P##N * v) \ +{ \ + SEVAL##N(F,T,P); \ + *v = (P##N)( SLST##N(v) ); \ + return (T##N) ( SLST##N(r) ); \ +} + +#define PWRAPNTAP(N,F,T,A,P) \ +ATTR T##N \ +F(T##N x, A P##N * v) \ +{ \ + PEVAL##N(F,T,P); \ + *v = (P##N)( PLST##N(v) ); \ + return (T##N) ( PLST##N(r) ); \ +} + +#define WRAP1TAP(F,T,A,P) \ +ATTR T \ +F(T x, A P * v) \ +{ \ + P v0; \ + T r0 = SNAME(F,T)(x, &v0); \ + *v = v0; \ + return r0; \ +} + +#define WRAP2TAP(F,T,A,P) \ +ATTR T##2 \ +F(T##2 x, A P##2 * v) \ +{ \ + P##2 v01; \ + T##2 r01 = PNAME(F,T)(x, &v01); \ + *v = v01; \ + return r01; \ +} + +#define SWRAPTAP(F,T,A,P) \ + SWRAPNTAP(16,F,T,A,P) \ + SWRAPNTAP(8,F,T,A,P) \ + SWRAPNTAP(4,F,T,A,P) \ + SWRAPNTAP(3,F,T,A,P) \ + SWRAPNTAP(2,F,T,A,P) \ + WRAP1TAP(F,T,A,P) + +#define PWRAPTAP(F,T,A,P) \ + PWRAPNTAP(16,F,T,A,P) \ + PWRAPNTAP(8,F,T,A,P) \ + PWRAPNTAP(4,F,T,A,P) \ + PWRAPNTAP(3,F,T,A,P) \ + WRAP2TAP(F,T,A,P) \ + WRAP1TAP(F,T,A,P) + +#define SWRAPTP(F,T,P) \ + SWRAPTAP(F,T,__private,P) \ + SWRAPTAP(F,T,__local,P) \ + SWRAPTAP(F,T,__global,P) \ + SWRAPTAP(F,T,,P) + +#define PWRAPTP(F,T,P) \ + PWRAPTAP(F,T,__private,P) \ + PWRAPTAP(F,T,__local,P) \ + PWRAPTAP(F,T,__global,P) \ + PWRAPTAP(F,T,,P) + +SWRAPTP(fract,float,float) +SWRAPTP(fract,double,double) +PWRAPTP(fract,half,half) + +SWRAPTP(frexp,float,int) +SWRAPTP(frexp,double,int) +PWRAPTP(frexp,half,int) + +SWRAPTP(lgamma_r,float,int) +SWRAPTP(lgamma_r,double,int) +PWRAPTP(lgamma_r,half,int) + +SWRAPTP(modf,float,float) +SWRAPTP(modf,double,double) +PWRAPTP(modf,half,half) + +SWRAPTP(sincos,float,float) +SWRAPTP(sincos,double,double) +PWRAPTP(sincos,half,half) + diff --git a/amd/device-libs/opencl/src/math/wrapbs.cl b/amd/device-libs/opencl/src/math/wrapbs.cl new file mode 100644 index 0000000000000..b88be6f241381 --- /dev/null +++ b/amd/device-libs/opencl/src/math/wrapbs.cl @@ -0,0 +1,168 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define ATTR __attribute__((overloadable)) + +#define float_ssuf _f32 +#define double_ssuf _f64 +#define half_ssuf _f16 +#define half_psuf _2f16 + +#define SNAME(F,T) C(__ocml_,C(F,T##_ssuf)) +#define PNAME(F,T) C(__ocml_,C(F,T##_psuf)) + +#define SLST2(F,T) SNAME(F,T)(x.s0,y.s0), SNAME(F,T)(x.s1,y.s1) +#define SLST3(F,T) SNAME(F,T)(x.s0,y.s0), SNAME(F,T)(x.s1,y.s1), SNAME(F,T)(x.s2,y.s2) +#define SLST4(F,T) SLST2(F,T), SNAME(F,T)(x.s2,y.s2), SNAME(F,T)(x.s3,y.s3) +#define SLST8(F,T) SLST4(F,T), SNAME(F,T)(x.s4,y.s4), SNAME(F,T)(x.s5,y.s5), SNAME(F,T)(x.s6,y.s6), SNAME(F,T)(x.s7,y.s7) +#define SLST16(F,T) SLST8(F,T), SNAME(F,T)(x.s8,y.s8), SNAME(F,T)(x.s9,y.s9), SNAME(F,T)(x.sa,y.sa), SNAME(F,T)(x.sb,y.sb), \ + SNAME(F,T)(x.sc,y.sc), SNAME(F,T)(x.sd,y.sd), SNAME(F,T)(x.se,y.se), SNAME(F,T)(x.sf,y.sf) + +#define SLST2S(F,T) SNAME(F,T)(x.s0,y), SNAME(F,T)(x.s1,y) +#define SLST3S(F,T) SNAME(F,T)(x.s0,y), SNAME(F,T)(x.s1,y), SNAME(F,T)(x.s2,y) +#define SLST4S(F,T) SLST2S(F,T), SNAME(F,T)(x.s2,y), SNAME(F,T)(x.s3,y) +#define SLST8S(F,T) SLST4S(F,T), SNAME(F,T)(x.s4,y), SNAME(F,T)(x.s5,y), SNAME(F,T)(x.s6,y), SNAME(F,T)(x.s7,y) +#define SLST16S(F,T) SLST8S(F,T), SNAME(F,T)(x.s8,y), SNAME(F,T)(x.s9,y), SNAME(F,T)(x.sa,y), SNAME(F,T)(x.sb,y), \ + SNAME(F,T)(x.sc,y), SNAME(F,T)(x.sd,y), SNAME(F,T)(x.se,y), SNAME(F,T)(x.sf,y) + +#define PLST3(F,T) PNAME(F,T)(x.s01,y.s01), SNAME(F,T)(x.s2,y.s2) +#define PLST4(F,T) PNAME(F,T)(x.s01,y.s01), PNAME(F,T)(x.s23,y.s23) +#define PLST8(F,T) PLST4(F,T), PNAME(F,T)(x.s45,y.s45), PNAME(F,T)(x.s67,y.s67) +#define PLST16(F,T) PLST8(F,T), PNAME(F,T)(x.s89,y.s89), PNAME(F,T)(x.sab,y.sab), PNAME(F,T)(x.scd,y.scd), PNAME(F,T)(x.sef,y.sef) + +#define PLST3S(F,T) PNAME(F,T)(x.s01,yy), SNAME(F,T)(x.s2,y) +#define PLST4S(F,T) PNAME(F,T)(x.s01,yy), PNAME(F,T)(x.s23,yy) +#define PLST8S(F,T) PLST4S(F,T), PNAME(F,T)(x.s45,yy), PNAME(F,T)(x.s67,yy) +#define PLST16S(F,T) PLST8S(F,T), PNAME(F,T)(x.s89,yy), PNAME(F,T)(x.sab,yy), PNAME(F,T)(x.scd,yy), PNAME(F,T)(x.sef,yy) + +#define SWRAPTN(N,F,TX,TY) \ +ATTR TX##N \ +F(TX##N x, TY##N y) \ +{ \ + return (TX##N) ( SLST##N(F,TX) ); \ +} + +#define SWRAPSTN(N,F,TX,TY) \ +ATTR TX##N \ +F(TX##N x, TY y) \ +{ \ + return (TX##N) ( SLST##N##S(F,TX) ); \ +} + +#define PWRAPTN(N,F,TX,TY) \ +ATTR TX##N \ +F(TX##N x, TY##N y) \ +{ \ + return (TX##N) ( PLST##N(F,TX) ); \ +} + +#define PWRAPSTN(N,F,TX,TY) \ +ATTR TX##N \ +F(TX##N x, TY y) \ +{ \ + TY##2 yy = (TY##2)y; \ + return (TX##N) ( PLST##N##S(F,TX) ); \ +} + +#define WRAPT1(F,TX,TY) \ +ATTR TX \ +F(TX x, TY y) \ +{ \ + return SNAME(F,TX)(x, y); \ +} + +#define WRAPT2(F,TX,TY) \ +ATTR TX##2 \ +F(TX##2 x, TY##2 y) \ +{ \ + return PNAME(F,TX)(x, y); \ +} + +#define WRAPT2S(F,TX,TY) \ +ATTR TX##2 \ +F(TX##2 x, TY y) \ +{ \ + return PNAME(F,TX)(x, (TY##2)y); \ +} + +#define SWRAPT(F,TX,TY) \ + SWRAPTN(16,F,TX,TY) \ + SWRAPTN(8,F,TX,TY) \ + SWRAPTN(4,F,TX,TY) \ + SWRAPTN(3,F,TX,TY) \ + SWRAPTN(2,F,TX,TY) \ + WRAPT1(F,TX,TY) + +#define SWRAPST(F,TX,TY) \ + SWRAPTN(16,F,TX,TY) \ + SWRAPSTN(16,F,TX,TY) \ + SWRAPTN(8,F,TX,TY) \ + SWRAPSTN(8,F,TX,TY) \ + SWRAPTN(4,F,TX,TY) \ + SWRAPSTN(4,F,TX,TY) \ + SWRAPTN(3,F,TX,TY) \ + SWRAPSTN(3,F,TX,TY) \ + SWRAPTN(2,F,TX,TY) \ + SWRAPSTN(2,F,TX,TY) \ + WRAPT1(F,TX,TY) + +#define PWRAPT(F,TX,TY) \ + PWRAPTN(16,F,TX,TY) \ + PWRAPTN(8,F,TX,TY) \ + PWRAPTN(4,F,TX,TY) \ + PWRAPTN(3,F,TX,TY) \ + WRAPT2(F,TX,TY) \ + WRAPT1(F,TX,TY) + +#define PWRAPST(F,TX,TY) \ + PWRAPTN(16,F,TX,TY) \ + PWRAPSTN(16,F,TX,TY) \ + PWRAPTN(8,F,TX,TY) \ + PWRAPSTN(8,F,TX,TY) \ + PWRAPTN(4,F,TX,TY) \ + PWRAPSTN(4,F,TX,TY) \ + PWRAPTN(3,F,TX,TY) \ + PWRAPSTN(3,F,TX,TY) \ + WRAPT2(F,TX,TY) \ + WRAPT2S(F,TX,TY) \ + WRAPT1(F,TX,TY) + +SWRAPST(fmax,float,float) +SWRAPST(fmax,double,double) +PWRAPST(fmax,half,half) + +SWRAPST(fmin,float,float) +SWRAPST(fmin,double,double) +PWRAPST(fmin,half,half) + +SWRAPST(ldexp,float,int) +SWRAPST(ldexp,double,int) +PWRAPST(ldexp,half,int) + +SWRAPST(max,float,float) +SWRAPST(max,double,double) +PWRAPST(max,half,half) + +SWRAPST(min,float,float) +SWRAPST(min,double,double) +PWRAPST(min,half,half) + +SWRAPT(pown,float,int) +SWRAPT(pown,double,int) +PWRAPT(pown,half,int) + +SWRAPT(rootn,float,int) +SWRAPT(rootn,double,int) +PWRAPT(rootn,half,int) + diff --git a/amd/device-libs/opencl/src/math/wrapt.cl b/amd/device-libs/opencl/src/math/wrapt.cl new file mode 100644 index 0000000000000..b7414682be71b --- /dev/null +++ b/amd/device-libs/opencl/src/math/wrapt.cl @@ -0,0 +1,101 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define ATTR __attribute__((overloadable)) + +#define float_ssuf _f32 +#define float_psuf _2f32 +#define double_ssuf _f64 +#define half_ssuf _f16 +#define half_psuf _2f16 + +#define SNAME(F,T) C(__ocml_,C(F,T##_ssuf)) +#define PNAME(F,T) C(__ocml_,C(F,T##_psuf)) + +#define SLST2(F,T) SNAME(F,T)(a.s0,b.s0,c.s0), SNAME(F,T)(a.s1,b.s1,c.s1) +#define SLST3(F,T) SNAME(F,T)(a.s0,b.s0,c.s0), SNAME(F,T)(a.s1,b.s1,c.s1), SNAME(F,T)(a.s2,b.s2,c.s2) +#define SLST4(F,T) SLST2(F,T), SNAME(F,T)(a.s2,b.s2,c.s2), SNAME(F,T)(a.s3,b.s3,c.s3) +#define SLST8(F,T) SLST4(F,T), SNAME(F,T)(a.s4,b.s4,c.s4), SNAME(F,T)(a.s5,b.s5,c.s5), \ + SNAME(F,T)(a.s6,b.s6,c.s6), SNAME(F,T)(a.s7,b.s7,c.s7) +#define SLST16(F,T) SLST8(F,T), SNAME(F,T)(a.s8,b.s8,c.s8), SNAME(F,T)(a.s9,b.s9,c.s9), \ + SNAME(F,T)(a.sa,b.sa,c.sa), SNAME(F,T)(a.sb,b.sb,c.sb), \ + SNAME(F,T)(a.sc,b.sc,c.sc), SNAME(F,T)(a.sd,b.sd,c.sd), \ + SNAME(F,T)(a.se,b.se,c.se), SNAME(F,T)(a.sf,b.sf,c.sf) + +#define PLST3(F,T) PNAME(F,T)(a.s01,b.s01,c.s01), SNAME(F,T)(a.s2,b.s2,c.s2) +#define PLST4(F,T) PNAME(F,T)(a.s01,b.s01,c.s01), PNAME(F,T)(a.s23,b.s23,c.s23) +#define PLST8(F,T) PLST4(F,T), PNAME(F,T)(a.s45,b.s45,c.s45), PNAME(F,T)(a.s67,b.s67,c.s67) +#define PLST16(F,T) PLST8(F,T), PNAME(F,T)(a.s89,b.s89,c.s89), PNAME(F,T)(a.sab,b.sab,c.sab), \ + PNAME(F,T)(a.scd,b.scd,c.scd), PNAME(F,T)(a.sef,b.sef,c.sef) + +#define SWRAPNT(N,F,T) \ +ATTR T##N \ +F(T##N a, T##N b, T##N c) \ +{ \ + return (T##N) ( SLST##N(F,T) ); \ +} + +#define PWRAPNT(N,F,T) \ +ATTR T##N \ +F(T##N a, T##N b, T##N c) \ +{ \ + return (T##N) ( PLST##N(F,T) ); \ +} + +#define WRAP1T(F,T) \ +ATTR T \ +F(T a, T b, T c) \ +{ \ + return SNAME(F,T)(a, b, c); \ +} + +#define WRAP2T(F,T) \ +ATTR T##2 \ +F(T##2 a, T##2 b, T##2 c) \ +{ \ + return PNAME(F,T)(a, b, c); \ +} + +#define SWRAPT(F,T) \ + SWRAPNT(16,F,T) \ + SWRAPNT(8,F,T) \ + SWRAPNT(4,F,T) \ + SWRAPNT(3,F,T) \ + SWRAPNT(2,F,T) \ + WRAP1T(F,T) + +#define PWRAPT(F,T) \ + PWRAPNT(16,F,T) \ + PWRAPNT(8,F,T) \ + PWRAPNT(4,F,T) \ + PWRAPNT(3,F,T) \ + WRAP2T(F,T) \ + WRAP1T(F,T) + +#if !defined USE_CLP +#define WRAP(F) \ + PWRAPT(F,float) \ + SWRAPT(F,double) \ + PWRAPT(F,half) +#else +#define WRAP(F) \ + WRAP1T(F,float) \ + WRAP1T(F,double) \ + WRAP1T(F,half) \ + WRAP2T(F,half) +#endif + +WRAP(fma) +WRAP(mad) + diff --git a/amd/device-libs/opencl/src/math/wraptp.cl b/amd/device-libs/opencl/src/math/wraptp.cl new file mode 100644 index 0000000000000..7a4bc63a805c8 --- /dev/null +++ b/amd/device-libs/opencl/src/math/wraptp.cl @@ -0,0 +1,128 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define ATTR __attribute__((overloadable)) + +#define float_ssuf _f32 +#define double_ssuf _f64 +#define half_ssuf _f16 +#define half_psuf _2f16 + +#define SNAME(F,T) C(__ocml_,C(F,T##_ssuf)) +#define PNAME(F,T) C(__ocml_,C(F,T##_psuf)) + +#define SEVN(N,F,T,P) \ + P v##N; \ + T r##N = SNAME(F,T)(x.s##N, y.s##N, &v##N) + +#define PEVN(N,F,T,P) \ + P##2 v##N; \ + T##2 r##N = PNAME(F,T)(x.s##N, y.s##N, &v##N) + +#define SEVAL2(F,T,P) SEVN(0,F,T,P); SEVN(1,F,T,P) +#define SEVAL3(F,T,P) SEVAL2(F,T,P); SEVN(2,F,T,P) +#define SEVAL4(F,T,P) SEVAL2(F,T,P); SEVN(2,F,T,P); SEVN(3,F,T,P) +#define SEVAL8(F,T,P) SEVAL4(F,T,P); SEVN(4,F,T,P); SEVN(5,F,T,P); SEVN(6,F,T,P); SEVN(7,F,T,P) +#define SEVAL16(F,T,P) SEVAL8(F,T,P); SEVN(8,F,T,P); SEVN(9,F,T,P); SEVN(a,F,T,P); SEVN(b,F,T,P); SEVN(c,F,T,P); SEVN(d,F,T,P); SEVN(e,F,T,P); SEVN(f,F,T,P) + +#define PEVAL3(F,T,P) PEVN(01,F,T,P); SEVN(2,F,T,P) +#define PEVAL4(F,T,P) PEVN(01,F,T,P); PEVN(23,F,T,P) +#define PEVAL8(F,T,P) PEVAL4(F,T,P); PEVN(45,F,T,P); PEVN(67,F,T,P) +#define PEVAL16(F,T,P) PEVAL8(F,T,P); PEVN(89,F,T,P); PEVN(ab,F,T,P); PEVN(cd,F,T,P); PEVN(ef,F,T,P) + +#define SLST2(V) V##0, V##1 +#define SLST3(V) SLST2(V), V##2 +#define SLST4(V) SLST2(V), V##2, V##3 +#define SLST8(V) SLST4(V), V##4, V##5, V##6, V##7 +#define SLST16(V) SLST8(V), V##8, V##9, V##a, V##b, V##c, V##d, V##e, V##f + +#define PLST3(V) V##01, V##2 +#define PLST4(V) V##01, V##23 +#define PLST8(V) PLST4(V), V##45, V##67 +#define PLST16(V) PLST8(V), V##89, V##ab, V##cd, V##ef + +#define SWRAPNTAP(N,F,T,A,P) \ +ATTR T##N \ +F(T##N x, T##N y, A P##N * v) \ +{ \ + SEVAL##N(F,T,P); \ + *v = (P##N)( SLST##N(v) ); \ + return (T##N) ( SLST##N(r) ); \ +} + +#define PWRAPNTAP(N,F,T,A,P) \ +ATTR T##N \ +F(T##N x, T##N y, A P##N * v) \ +{ \ + PEVAL##N(F,T,P); \ + *v = (P##N)( PLST##N(v) ); \ + return (T##N) ( PLST##N(r) ); \ +} + +#define WRAP1TAP(F,T,A,P) \ +ATTR T \ +F(T x, T y, A P * v) \ +{ \ + P v0; \ + T r0 = SNAME(F,T)(x, y, &v0); \ + *v = v0; \ + return r0; \ +} + +#define WRAP2TAP(F,T,A,P) \ +ATTR T##2 \ +F(T##2 x, T##2 y, A P##2 * v) \ +{ \ + P##2 v01; \ + T##2 r01 = PNAME(F,T)(x, y, &v01); \ + *v = v01; \ + return r01; \ +} + +#define SWRAPTAP(F,T,A,P) \ + SWRAPNTAP(16,F,T,A,P) \ + SWRAPNTAP(8,F,T,A,P) \ + SWRAPNTAP(4,F,T,A,P) \ + SWRAPNTAP(3,F,T,A,P) \ + SWRAPNTAP(2,F,T,A,P) \ + WRAP1TAP(F,T,A,P) + +#define PWRAPTAP(F,T,A,P) \ + PWRAPNTAP(16,F,T,A,P) \ + PWRAPNTAP(8,F,T,A,P) \ + PWRAPNTAP(4,F,T,A,P) \ + PWRAPNTAP(3,F,T,A,P) \ + WRAP2TAP(F,T,A,P) \ + WRAP1TAP(F,T,A,P) + +#define SWRAPTP(F,T,P) \ + SWRAPTAP(F,T,__private,P) \ + SWRAPTAP(F,T,__local,P) \ + SWRAPTAP(F,T,__global,P) \ + SWRAPTAP(F,T,,P) + +#define PWRAPTP(F,T,P) \ + PWRAPTAP(F,T,__private,P) \ + PWRAPTAP(F,T,__local,P) \ + PWRAPTAP(F,T,__global,P) \ + PWRAPTAP(F,T,,P) + +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wdeprecated" + +SWRAPTP(remquo,float,int) +SWRAPTP(remquo,double,int) +PWRAPTP(remquo,half,int) + +#pragma clang diagnostic pop diff --git a/amd/device-libs/opencl/src/math/wrapu.cl b/amd/device-libs/opencl/src/math/wrapu.cl new file mode 100644 index 0000000000000..25238b18362b7 --- /dev/null +++ b/amd/device-libs/opencl/src/math/wrapu.cl @@ -0,0 +1,134 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define ATTR __attribute__((overloadable)) + +#define float_ssuf _f32 +#define double_ssuf _f64 +#define half_ssuf _f16 +#define half_psuf _2f16 + +#define SNAME(F,T) C(__ocml_,C(F,T##_ssuf)) +#define PNAME(F,T) C(__ocml_,C(F,T##_psuf)) + +#define SLST2(F,T) SNAME(F,T)(x.s0), SNAME(F,T)(x.s1) +#define SLST3(F,T) SLST2(F,T), SNAME(F,T)(x.s2) +#define SLST4(F,T) SLST2(F,T), SNAME(F,T)(x.s2), SNAME(F,T)(x.s3) +#define SLST8(F,T) SLST4(F,T), SNAME(F,T)(x.s4), SNAME(F,T)(x.s5), SNAME(F,T)(x.s6), SNAME(F,T)(x.s7) +#define SLST16(F,T) SLST8(F,T), SNAME(F,T)(x.s8), SNAME(F,T)(x.s9), SNAME(F,T)(x.sa), SNAME(F,T)(x.sb), \ + SNAME(F,T)(x.sc), SNAME(F,T)(x.sd), SNAME(F,T)(x.se), SNAME(F,T)(x.sf) + +#define PLST3(F,T) PNAME(F,T)(x.s01), SNAME(F,T)(x.s2) +#define PLST4(F,T) PNAME(F,T)(x.s01), PNAME(F,T)(x.s23) +#define PLST8(F,T) PLST4(F,T), PNAME(F,T)(x.s45), PNAME(F,T)(x.s67) +#define PLST16(F,T) PLST8(F,T), PNAME(F,T)(x.s89), PNAME(F,T)(x.sab), PNAME(F,T)(x.scd), PNAME(F,T)(x.sef) + +#define SWRAPNT(N,F,T) \ +ATTR T##N \ +F(T##N x) \ +{ \ + return (T##N) ( SLST##N(F,T) ); \ +} + +#define PWRAPNT(N,F,T) \ +ATTR T##N \ +F(T##N x) \ +{ \ + return (T##N) ( PLST##N(F,T) ); \ +} + +#define WRAP1T(F,T) \ +ATTR T \ +F(T x) \ +{ \ + return SNAME(F,T)(x); \ +} + +#define WRAP2T(F,T) \ +ATTR T##2 \ +F(T##2 x) \ +{ \ + return PNAME(F,T)(x); \ +} + +#define SWRAPT(F,T) \ + SWRAPNT(16,F,T) \ + SWRAPNT(8,F,T) \ + SWRAPNT(4,F,T) \ + SWRAPNT(3,F,T) \ + SWRAPNT(2,F,T) \ + WRAP1T(F,T) + +#define PWRAPT(F,T) \ + PWRAPNT(16,F,T) \ + PWRAPNT(8,F,T) \ + PWRAPNT(4,F,T) \ + PWRAPNT(3,F,T) \ + WRAP2T(F,T) \ + WRAP1T(F,T) + +#if !defined USE_CLP +#define WRAP(F) \ + SWRAPT(F,float) \ + SWRAPT(F,double) \ + PWRAPT(F,half) +#else +#define WRAP(F) \ + WRAP1T(F,float) \ + WRAP1T(F,double) \ + WRAP1T(F,half) \ + WRAP2T(F,half) +#endif + +WRAP(acos) +WRAP(acosh) +WRAP(acospi) +WRAP(asin) +WRAP(asinh) +WRAP(asinpi) +WRAP(atan) +WRAP(atanh) +WRAP(atanpi) +WRAP(cbrt) +WRAP(ceil) +WRAP(cos) +WRAP(cosh) +WRAP(cospi) +WRAP(erfc) +WRAP(erf) +WRAP(exp) +WRAP(exp2) +WRAP(exp10) +WRAP(expm1) +WRAP(fabs) +WRAP(floor) +WRAP(lgamma) +WRAP(log) +WRAP(log2) +WRAP(log10) +WRAP(log1p) +WRAP(logb) +WRAP(rint) +WRAP(round) +WRAP(rsqrt) +WRAP(sin) +WRAP(sinh) +WRAP(sinpi) +WRAP(sqrt) +WRAP(tan) +WRAP(tanh) +WRAP(tanpi) +WRAP(tgamma) +WRAP(trunc) + diff --git a/amd/device-libs/opencl/src/math/wrapu2.cl b/amd/device-libs/opencl/src/math/wrapu2.cl new file mode 100644 index 0000000000000..168c1903b63b0 --- /dev/null +++ b/amd/device-libs/opencl/src/math/wrapu2.cl @@ -0,0 +1,88 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define ATTR __attribute__((overloadable)) + +#define float_ssuf _f32 +#define double_ssuf _f64 +#define half_ssuf _f16 +#define half_psuf _2f16 + +#define SNAME(F,T) C(__ocml_,C(F,T##_ssuf)) +#define PNAME(F,T) C(__ocml_,C(F,T##_psuf)) + +#define SLST2(F,T) SNAME(F,T)(x.s0), SNAME(F,T)(x.s1) +#define SLST3(F,T) SNAME(F,T)(x.s0), SNAME(F,T)(x.s1), SNAME(F,T)(x.s2) +#define SLST4(F,T) SLST2(F,T), SNAME(F,T)(x.s2), SNAME(F,T)(x.s3) +#define SLST8(F,T) SLST4(F,T), SNAME(F,T)(x.s4), SNAME(F,T)(x.s5), SNAME(F,T)(x.s6), SNAME(F,T)(x.s7) +#define SLST16(F,T) SLST8(F,T), SNAME(F,T)(x.s8), SNAME(F,T)(x.s9), SNAME(F,T)(x.sa), SNAME(F,T)(x.sb), \ + SNAME(F,T)(x.sc), SNAME(F,T)(x.sd), SNAME(F,T)(x.se), SNAME(F,T)(x.sf) + +#define PLST3(F,T) PNAME(F,T)(x.s01), SNAME(F,T)(x.s2) +#define PLST4(F,T) PNAME(F,T)(x.s01), PNAME(F,T)(x.s23) +#define PLST8(F,T) PLST4(F,T), PNAME(F,T)(x.s45), PNAME(F,T)(x.s67) +#define PLST16(F,T) PLST8(F,T), PNAME(F,T)(x.s89), PNAME(F,T)(x.sab), PNAME(F,T)(x.scd), PNAME(F,T)(x.sef) + +#define SWRAPN(N,F,OT,IT,ST) \ +ATTR OT##N \ +F(IT##N x) \ +{ \ + return (OT##N) ( SLST##N(F,ST) ); \ +} + +#define PWRAPN(N,F,OT,IT,ST) \ +ATTR OT##N \ +F(IT##N x) \ +{ \ + return (OT##N) ( PLST##N(F,ST) ); \ +} + +#define WRAP1(F,OT,IT,ST) \ +ATTR OT \ +F(IT x) \ +{ \ + return SNAME(F,ST)(x); \ +} + +#define WRAP2(F,OT,IT,ST) \ +ATTR OT##2 \ +F(IT##2 x) \ +{ \ + return PNAME(F,ST)(x); \ +} + +#define SWRAP(F,OT,IT,ST) \ + SWRAPN(16,F,OT,IT,ST) \ + SWRAPN(8,F,OT,IT,ST) \ + SWRAPN(4,F,OT,IT,ST) \ + SWRAPN(3,F,OT,IT,ST) \ + SWRAPN(2,F,OT,IT,ST) \ + WRAP1(F,OT,IT,ST) + +#define PWRAP(F,OT,IT,ST) \ + PWRAPN(16,F,OT,IT,ST) \ + PWRAPN(8,F,OT,IT,ST) \ + PWRAPN(4,F,OT,IT,ST) \ + PWRAPN(3,F,OT,IT,ST) \ + WRAP2(F,OT,IT,ST) \ + WRAP1(F,OT,IT,ST) + +SWRAP(ilogb,int,float,float) +SWRAP(ilogb,int,double,double) +PWRAP(ilogb,int,half,half) + +SWRAP(nan,float,uint,float) +SWRAP(nan,double,ulong,double) +PWRAP(nan,half,ushort,half) + diff --git a/amd/device-libs/opencl/src/media/bfm.cl b/amd/device-libs/opencl/src/media/bfm.cl new file mode 100644 index 0000000000000..af5675dee10b0 --- /dev/null +++ b/amd/device-libs/opencl/src/media/bfm.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(bfm) + +#define L2 F(a.s0, b.s0), F(a.s1, b.s1) +#define L3 L2, F(a.s2, b.s2) +#define L4 L3, F(a.s3, b.s3) +#define L8 L4, F(a.s4, b.s4), F(a.s5, b.s5), F(a.s6, b.s6), F(a.s7, b.s7) +#define L16 L8, F(a.s8, b.s8), F(a.s9, b.s9), F(a.sa, b.sa), F(a.sb, b.sb), \ + F(a.sc, b.sc), F(a.sd, b.sd), F(a.se, b.se), F(a.sf, b.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_bfm(uint##N a, uint##N b) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_bfm(uint a, uint b) { return F(a, b); } + diff --git a/amd/device-libs/opencl/src/media/bitalign.cl b/amd/device-libs/opencl/src/media/bitalign.cl new file mode 100644 index 0000000000000..f74bb7d7515d0 --- /dev/null +++ b/amd/device-libs/opencl/src/media/bitalign.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(bitalign) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_bitalign(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_bitalign(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/bytealign.cl b/amd/device-libs/opencl/src/media/bytealign.cl new file mode 100644 index 0000000000000..b9522f2d5ae0e --- /dev/null +++ b/amd/device-libs/opencl/src/media/bytealign.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(bytealign) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_bytealign(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_bytealign(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/fmax3.cl b/amd/device-libs/opencl/src/media/fmax3.cl new file mode 100644 index 0000000000000..3d1f51ce6efe8 --- /dev/null +++ b/amd/device-libs/opencl/src/media/fmax3.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_F32(max3) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR float##N \ +amd_max3(float##N a, float##N b, float##N c) \ +{ \ + return (float##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR float amd_max3(float a, float b, float c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/fmed3.cl b/amd/device-libs/opencl/src/media/fmed3.cl new file mode 100644 index 0000000000000..0bf2ed3a40de1 --- /dev/null +++ b/amd/device-libs/opencl/src/media/fmed3.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_F32(median3) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR float##N \ +amd_median3(float##N a, float##N b, float##N c) \ +{ \ + return (float##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR float amd_median3(float a, float b, float c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/fmin3.cl b/amd/device-libs/opencl/src/media/fmin3.cl new file mode 100644 index 0000000000000..49cffb3202e52 --- /dev/null +++ b/amd/device-libs/opencl/src/media/fmin3.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_F32(min3) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR float##N \ +amd_min3(float##N a, float##N b, float##N c) \ +{ \ + return (float##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR float amd_min3(float a, float b, float c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/ibfe.cl b/amd/device-libs/opencl/src/media/ibfe.cl new file mode 100644 index 0000000000000..06d6604eb2400 --- /dev/null +++ b/amd/device-libs/opencl/src/media/ibfe.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_I32(bfe) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR int##N \ +amd_bfe(int##N a, uint##N b, uint##N c) \ +{ \ + return (int##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR int amd_bfe(int a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/imax3.cl b/amd/device-libs/opencl/src/media/imax3.cl new file mode 100644 index 0000000000000..4b7a2023afd86 --- /dev/null +++ b/amd/device-libs/opencl/src/media/imax3.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_I32(max3) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR int##N \ +amd_max3(int##N a, int##N b, int##N c) \ +{ \ + return (int##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR int amd_max3(int a, int b, int c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/imed3.cl b/amd/device-libs/opencl/src/media/imed3.cl new file mode 100644 index 0000000000000..953ee5f2b6a59 --- /dev/null +++ b/amd/device-libs/opencl/src/media/imed3.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_I32(median3) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR int##N \ +amd_median3(int##N a, int##N b, int##N c) \ +{ \ + return (int##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR int amd_median3(int a, int b, int c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/imin3.cl b/amd/device-libs/opencl/src/media/imin3.cl new file mode 100644 index 0000000000000..fb8c0c9fedadc --- /dev/null +++ b/amd/device-libs/opencl/src/media/imin3.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_I32(min3) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR int##N \ +amd_min3(int##N a, int##N b, int##N c) \ +{ \ + return (int##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR int amd_min3(int a, int b, int c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/lerp.cl b/amd/device-libs/opencl/src/media/lerp.cl new file mode 100644 index 0000000000000..ea9b45601a510 --- /dev/null +++ b/amd/device-libs/opencl/src/media/lerp.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(lerp) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_lerp(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_lerp(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/mqsad.cl b/amd/device-libs/opencl/src/media/mqsad.cl new file mode 100644 index 0000000000000..7e5b546011e48 --- /dev/null +++ b/amd/device-libs/opencl/src/media/mqsad.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U64(mqsad) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR ulong##N \ +amd_mqsad(ulong##N a, uint##N b, ulong##N c) \ +{ \ + return (ulong##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR ulong amd_mqsad(ulong a, uint b, ulong c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/msad.cl b/amd/device-libs/opencl/src/media/msad.cl new file mode 100644 index 0000000000000..98b5c4d662699 --- /dev/null +++ b/amd/device-libs/opencl/src/media/msad.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(msad) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_msad(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_msad(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/pack.cl b/amd/device-libs/opencl/src/media/pack.cl new file mode 100644 index 0000000000000..d0e7905aa85de --- /dev/null +++ b/amd/device-libs/opencl/src/media/pack.cl @@ -0,0 +1,13 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +ATTR uint amd_pack(float4 v) { return OCKL_MANGLE_U32(pack)(v); } + diff --git a/amd/device-libs/opencl/src/media/qsad.cl b/amd/device-libs/opencl/src/media/qsad.cl new file mode 100644 index 0000000000000..5692f51326393 --- /dev/null +++ b/amd/device-libs/opencl/src/media/qsad.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U64(qsad) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR ulong##N \ +amd_qsad(ulong##N a, uint##N b, ulong##N c) \ +{ \ + return (ulong##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR ulong amd_qsad(ulong a, uint b, ulong c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/sad.cl b/amd/device-libs/opencl/src/media/sad.cl new file mode 100644 index 0000000000000..d076f281bce3b --- /dev/null +++ b/amd/device-libs/opencl/src/media/sad.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(sad) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_sad(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_sad(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/sad4.cl b/amd/device-libs/opencl/src/media/sad4.cl new file mode 100644 index 0000000000000..a2d9f84087700 --- /dev/null +++ b/amd/device-libs/opencl/src/media/sad4.cl @@ -0,0 +1,19 @@ + +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +__attribute__((overloadable, const)) uint +amd_sad4(uint4 x, uint4 y, uint z) +{ + uint a = OCKL_MANGLE_U32(sad)(x.s0,y.s0,z); + a = OCKL_MANGLE_U32(sad)(x.s1,y.s1,a); + a = OCKL_MANGLE_U32(sad)(x.s2,y.s2,a); + return OCKL_MANGLE_U32(sad)(x.s3,y.s3,a); +} + diff --git a/amd/device-libs/opencl/src/media/sadd.cl b/amd/device-libs/opencl/src/media/sadd.cl new file mode 100644 index 0000000000000..0618921f23fcd --- /dev/null +++ b/amd/device-libs/opencl/src/media/sadd.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(sadd) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_sadd(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_sadd(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/sadhi.cl b/amd/device-libs/opencl/src/media/sadhi.cl new file mode 100644 index 0000000000000..fdab49fac171f --- /dev/null +++ b/amd/device-libs/opencl/src/media/sadhi.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(sadhi) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_sadhi(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_sadhi(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/sadw.cl b/amd/device-libs/opencl/src/media/sadw.cl new file mode 100644 index 0000000000000..9cc84f13f2aeb --- /dev/null +++ b/amd/device-libs/opencl/src/media/sadw.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(sadw) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_sadw(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_sadw(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/ubfe.cl b/amd/device-libs/opencl/src/media/ubfe.cl new file mode 100644 index 0000000000000..04666c9d938d4 --- /dev/null +++ b/amd/device-libs/opencl/src/media/ubfe.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(bfe) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_bfe(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_bfe(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/umax3.cl b/amd/device-libs/opencl/src/media/umax3.cl new file mode 100644 index 0000000000000..e637ad9bfb49d --- /dev/null +++ b/amd/device-libs/opencl/src/media/umax3.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(max3) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_max3(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_max3(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/umed3.cl b/amd/device-libs/opencl/src/media/umed3.cl new file mode 100644 index 0000000000000..e3694aacbd569 --- /dev/null +++ b/amd/device-libs/opencl/src/media/umed3.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(median3) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_median3(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_median3(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/umin3.cl b/amd/device-libs/opencl/src/media/umin3.cl new file mode 100644 index 0000000000000..4de74871fa2d9 --- /dev/null +++ b/amd/device-libs/opencl/src/media/umin3.cl @@ -0,0 +1,36 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define F OCKL_MANGLE_U32(min3) + +#define L2 F(a.s0, b.s0, c.s0), F(a.s1, b.s1, c.s1) +#define L3 L2, F(a.s2, b.s2, c.s2) +#define L4 L3, F(a.s3, b.s3, c.s3) +#define L8 L4, F(a.s4, b.s4, c.s4), F(a.s5, b.s5, c.s5), F(a.s6, b.s6, c.s6), F(a.s7, b.s7, c.s7) +#define L16 L8, F(a.s8, b.s8, c.s8), F(a.s9, b.s9, c.s9), F(a.sa, b.sa, c.sa), F(a.sb, b.sb, c.sb), \ + F(a.sc, b.sc, c.sc), F(a.sd, b.sd, c.sd), F(a.se, b.se, c.se), F(a.sf, b.sf, c.sf) + + +#define GEN(N) \ +ATTR uint##N \ +amd_min3(uint##N a, uint##N b, uint##N c) \ +{ \ + return (uint##N)( L##N ); \ +} + +GEN(16) +GEN(8) +GEN(4) +GEN(3) +GEN(2) + +ATTR uint amd_min3(uint a, uint b, uint c) { return F(a, b, c); } + diff --git a/amd/device-libs/opencl/src/media/unpack.cl b/amd/device-libs/opencl/src/media/unpack.cl new file mode 100644 index 0000000000000..973efb8248a04 --- /dev/null +++ b/amd/device-libs/opencl/src/media/unpack.cl @@ -0,0 +1,44 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +#define _F(N) __ockl_unpack##N##_f32 +#define F(N) _F(N) + +#define L2(N) F(N)(a.s0), F(N)(a.s1) +#define L3(N) L2(N), F(N)(a.s2) +#define L4(N) L3(N), F(N)(a.s3) +#define L8(N) L4(N), F(N)(a.s4), F(N)(a.s5), F(N)(a.s6), F(N)(a.s7) +#define L16(N) L8(N), F(N)(a.s8), F(N)(a.s9), F(N)(a.sa), F(N)(a.sb), F(N)(a.sc), F(N)(a.sd), F(N)(a.se), F(N)(a.sf) + +#define GENN(N,B) \ +ATTR float##N \ +amd_unpack##B(uint##N a) \ +{ \ + return (float##N)( L##N(B) ); \ +} + +#define GEN(B) \ + GENN(16,B) \ + GENN(8,B) \ + GENN(4,B) \ + GENN(3,B) \ + GENN(2,B) + +GEN(0) +GEN(1) +GEN(2) +GEN(3) + +ATTR float amd_unpack0(uint a) { return F(0)(a); } +ATTR float amd_unpack1(uint a) { return F(1)(a); } +ATTR float amd_unpack2(uint a) { return F(2)(a); } +ATTR float amd_unpack3(uint a) { return F(3)(a); } + diff --git a/amd/device-libs/opencl/src/misc/amdblit.cl b/amd/device-libs/opencl/src/misc/amdblit.cl new file mode 100644 index 0000000000000..5828a6b97572b --- /dev/null +++ b/amd/device-libs/opencl/src/misc/amdblit.cl @@ -0,0 +1,832 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#if !defined NO_BLIT + +#pragma OPENCL EXTENSION cl_khr_int64_base_atomics : enable +#pragma OPENCL EXTENSION cl_khr_int64_extended_atomics : enable + +typedef enum BatchMemOpType { + STREAM_WAIT_VALUE_32 = 0x1, + STREAM_WRITE_VALUE_32 = 0x2, + STREAM_WAIT_VALUE_64 = 0x4, + STREAM_WRITE_VALUE_64 = 0x5, + STREAM_MEM_OP_BARRIER = 0x6, // Currently not supported + STREAM_MEM_OP_FLUSH_REMOTE_WRITES = 0x3 // Currently not supported +} BatchMemOpType; + +typedef union streamBatchMemOpParams_union { + BatchMemOpType operation; + struct streamMemOpWaitValueParams_t{ + BatchMemOpType operation; + atomic_ulong* address; + union { + uint value; + ulong value64; + }; + uint flags; + atomic_ulong* alias; // Not valid for AMD backend + } waitValue; + struct streamMemOpWriteValueParams_t{ + BatchMemOpType operation; + atomic_ulong* address; + union { + uint value; + ulong value64; + }; + uint flags; + atomic_ulong* alias; // Not valid for AMD backend + } writeValue; + struct streamMemOpFlushRemoteWritesParams_t{ // Currently not supported + BatchMemOpType operation; + uint flags; + } flushRemoteWrites; + struct streamMemOpMemoryBarrierParams_t{ // Currently not supported + BatchMemOpType operation; + uint flags; + } memoryBarrier; + ulong pad[6]; +} BatchMemOpParams; + + +static const uint SplitCount = 3; + +__attribute__((always_inline)) void +__amd_copyBufferToImage( + __global uint *src, + __write_only image2d_array_t dst, + ulong4 srcOrigin, + int4 dstOrigin, + int4 size, + uint4 format, + ulong4 pitch) +{ + ulong idxSrc; + int4 coordsDst; + uint4 pixel; + __global uint* srcUInt = src; + __global ushort* srcUShort = (__global ushort*)src; + __global uchar* srcUChar = (__global uchar*)src; + ushort tmpUShort; + uint tmpUInt; + + coordsDst.x = get_global_id(0); + coordsDst.y = get_global_id(1); + coordsDst.z = get_global_id(2); + coordsDst.w = 0; + + if ((coordsDst.x >= size.x) || + (coordsDst.y >= size.y) || + (coordsDst.z >= size.z)) { + return; + } + + idxSrc = (coordsDst.z * pitch.y + + coordsDst.y * pitch.x + coordsDst.x) * + format.z + srcOrigin.x; + + coordsDst.x += dstOrigin.x; + coordsDst.y += dstOrigin.y; + coordsDst.z += dstOrigin.z; + + // Check components + switch (format.x) { + case 1: + // Check size + if (format.y == 1) { + pixel.x = (uint)srcUChar[idxSrc]; + } + else if (format.y == 2) { + pixel.x = (uint)srcUShort[idxSrc]; + } + else { + pixel.x = srcUInt[idxSrc]; + } + break; + case 2: + // Check size + if (format.y == 1) { + tmpUShort = srcUShort[idxSrc]; + pixel.x = (uint)(tmpUShort & 0xff); + pixel.y = (uint)(tmpUShort >> 8); + } + else if (format.y == 2) { + tmpUInt = srcUInt[idxSrc]; + pixel.x = (tmpUInt & 0xffff); + pixel.y = (tmpUInt >> 16); + } + else { + pixel.x = srcUInt[idxSrc++]; + pixel.y = srcUInt[idxSrc]; + } + break; + case 4: + // Check size + if (format.y == 1) { + tmpUInt = srcUInt[idxSrc]; + pixel.x = tmpUInt & 0xff; + pixel.y = (tmpUInt >> 8) & 0xff; + pixel.z = (tmpUInt >> 16) & 0xff; + pixel.w = (tmpUInt >> 24) & 0xff; + } + else if (format.y == 2) { + tmpUInt = srcUInt[idxSrc++]; + pixel.x = tmpUInt & 0xffff; + pixel.y = (tmpUInt >> 16); + tmpUInt = srcUInt[idxSrc]; + pixel.z = tmpUInt & 0xffff; + pixel.w = (tmpUInt >> 16); + } + else { + pixel.x = srcUInt[idxSrc++]; + pixel.y = srcUInt[idxSrc++]; + pixel.z = srcUInt[idxSrc++]; + pixel.w = srcUInt[idxSrc]; + } + break; + } + // Write the final pixel + write_imageui(dst, coordsDst, pixel); +} + +__attribute__((always_inline)) void +__amd_copyImageToBuffer( + __read_only image2d_array_t src, + __global uint* dstUInt, + __global ushort* dstUShort, + __global uchar* dstUChar, + int4 srcOrigin, + ulong4 dstOrigin, + int4 size, + uint4 format, + ulong4 pitch) +{ + ulong idxDst; + int4 coordsSrc; + uint4 texel; + + coordsSrc.x = get_global_id(0); + coordsSrc.y = get_global_id(1); + coordsSrc.z = get_global_id(2); + coordsSrc.w = 0; + + if ((coordsSrc.x >= size.x) || + (coordsSrc.y >= size.y) || + (coordsSrc.z >= size.z)) { + return; + } + + idxDst = (coordsSrc.z * pitch.y + coordsSrc.y * pitch.x + + coordsSrc.x) * format.z + dstOrigin.x; + + coordsSrc.x += srcOrigin.x; + coordsSrc.y += srcOrigin.y; + coordsSrc.z += srcOrigin.z; + + texel = read_imageui(src, coordsSrc); + + // Check components + switch (format.x) { + case 1: + // Check size + switch (format.y) { + case 1: + dstUChar[idxDst] = (uchar)texel.x; + break; + case 2: + dstUShort[idxDst] = (ushort)texel.x; + break; + case 4: + dstUInt[idxDst] = texel.x; + break; + } + break; + case 2: + // Check size + switch (format.y) { + case 1: + dstUShort[idxDst] = (ushort)texel.x | + ((ushort)texel.y << 8); + break; + case 2: + dstUInt[idxDst] = texel.x | (texel.y << 16); + break; + case 4: + dstUInt[idxDst++] = texel.x; + dstUInt[idxDst] = texel.y; + break; + } + break; + case 4: + // Check size + switch (format.y) { + case 1: + dstUInt[idxDst] = (uint)texel.x | + (texel.y << 8) | + (texel.z << 16) | + (texel.w << 24); + break; + case 2: + dstUInt[idxDst++] = texel.x | (texel.y << 16); + dstUInt[idxDst] = texel.z | (texel.w << 16); + break; + case 4: + dstUInt[idxDst++] = texel.x; + dstUInt[idxDst++] = texel.y; + dstUInt[idxDst++] = texel.z; + dstUInt[idxDst] = texel.w; + break; + } + break; + } +} + +__attribute__((always_inline)) void +__amd_copyImage( + __read_only image2d_array_t src, + __write_only image2d_array_t dst, + int4 srcOrigin, + int4 dstOrigin, + int4 size) +{ + int4 coordsDst; + int4 coordsSrc; + + coordsDst.x = get_global_id(0); + coordsDst.y = get_global_id(1); + coordsDst.z = get_global_id(2); + coordsDst.w = 0; + + if ((coordsDst.x >= size.x) || + (coordsDst.y >= size.y) || + (coordsDst.z >= size.z)) { + return; + } + + coordsSrc = srcOrigin + coordsDst; + coordsDst += dstOrigin; + + uint4 texel; + texel = read_imageui(src, coordsSrc); + write_imageui(dst, coordsDst, texel); +} + +__attribute__((always_inline)) void +__amd_copyImage1DA( + __read_only image2d_array_t src, + __write_only image2d_array_t dst, + int4 srcOrigin, + int4 dstOrigin, + int4 size) +{ + int4 coordsDst; + int4 coordsSrc; + + coordsDst.x = get_global_id(0); + coordsDst.y = get_global_id(1); + coordsDst.z = get_global_id(2); + coordsDst.w = 0; + + if ((coordsDst.x >= size.x) || + (coordsDst.y >= size.y) || + (coordsDst.z >= size.z)) { + return; + } + + coordsSrc = srcOrigin + coordsDst; + coordsDst += dstOrigin; + if (srcOrigin.w != 0) { + coordsSrc.z = coordsSrc.y; + coordsSrc.y = 0; + } + if (dstOrigin.w != 0) { + coordsDst.z = coordsDst.y; + coordsDst.y = 0; + } + + uint4 texel; + texel = read_imageui(src, coordsSrc); + write_imageui(dst, coordsDst, texel); +} + +__attribute__((always_inline)) void +__amd_copyBufferRect( + __global uchar* src, + __global uchar* dst, + ulong4 srcRect, + ulong4 dstRect, + ulong4 size) +{ + ulong x = get_global_id(0); + ulong y = get_global_id(1); + ulong z = get_global_id(2); + + if ((x >= size.x) || + (y >= size.y) || + (z >= size.z)) { + return; + } + + ulong offsSrc = srcRect.z + x + y * srcRect.x + z * srcRect.y; + ulong offsDst = dstRect.z + x + y * dstRect.x + z * dstRect.y; + + dst[offsDst] = src[offsSrc]; +} + +__attribute__((always_inline)) void +__amd_copyBufferRectAligned( + __global uint* src, + __global uint* dst, + ulong4 srcRect, + ulong4 dstRect, + ulong4 size) +{ + ulong x = get_global_id(0); + ulong y = get_global_id(1); + ulong z = get_global_id(2); + + if ((x >= size.x) || + (y >= size.y) || + (z >= size.z)) { + return; + } + + ulong offsSrc = srcRect.z + x + y * srcRect.x + z * srcRect.y; + ulong offsDst = dstRect.z + x + y * dstRect.x + z * dstRect.y; + + if (size.w == 16) { + __global uint4* src4 = (__global uint4*)src; + __global uint4* dst4 = (__global uint4*)dst; + dst4[offsDst] = src4[offsSrc]; + } + else { + dst[offsDst] = src[offsSrc]; + } +} + +__attribute__((always_inline)) void +__amd_copyBuffer( + __global uchar* srcI, + __global uchar* dstI, + ulong srcOrigin, + ulong dstOrigin, + ulong size, + uint remain) +{ + ulong id = get_global_id(0); + + if (id >= size) { + return; + } + + __global uchar* src = srcI + srcOrigin; + __global uchar* dst = dstI + dstOrigin; + + if (remain == 8) { + dst[id] = src[id]; + } + else { + if (id < (size - 1)) { + __global uint* srcD = (__global uint*)(src); + __global uint* dstD = (__global uint*)(dst); + dstD[id] = srcD[id]; + } + else { + for (uint i = 0; i < remain; ++i) { + dst[id * 4 + i] = src[id * 4 + i]; + } + } + } +} + +__attribute__((always_inline)) void +__amd_copyBufferAligned( + __global uint* src, + __global uint* dst, + ulong srcOrigin, + ulong dstOrigin, + ulong size, + uint alignment) +{ + ulong id = get_global_id(0); + + if (id >= size) { + return; + } + + ulong offsSrc = id + srcOrigin; + ulong offsDst = id + dstOrigin; + + if (alignment == 16) { + __global uint4* src4 = (__global uint4*)src; + __global uint4* dst4 = (__global uint4*)dst; + dst4[offsDst] = src4[offsSrc]; + } + else { + dst[offsDst] = src[offsSrc]; + } +} + +__attribute__((always_inline)) void +__amd_copyBufferExt( + __global uchar* srcI, + __global uchar* dstI, + ulong srcOrigin, + ulong dstOrigin, + ulong size, + uint remainder, + uint aligned_size, + ulong end_ptr, + uint next_chunk) { + ulong id = get_global_id(0); + ulong id_remainder = id; + + __global uchar* src = srcI + srcOrigin; + __global uchar* dst = dstI + dstOrigin; + + if (aligned_size == sizeof(ulong2)) { + __global ulong2* srcD = (__global ulong2*)(src); + __global ulong2* dstD = (__global ulong2*)(dst); + while ((ulong)(&dstD[id]) < end_ptr) { + dstD[id] = srcD[id]; + id += next_chunk; + } + } else { + __global uint* srcD = (__global uint*)(src); + __global uint* dstD = (__global uint*)(dst); + while ((ulong)(&dstD[id]) < end_ptr) { + dstD[id] = srcD[id]; + id += next_chunk; + } + } + if ((remainder != 0) && (id_remainder == 0)) { + for (ulong i = size - remainder; i < size; ++i) { + dst[i] = src[i]; + } + } +} + +__attribute__((always_inline)) void +__amd_fillBuffer( + __global uchar* bufUChar, + __global uint* bufUInt, + __constant uchar* pattern, + uint patternSize, + ulong offset, + ulong size) +{ + ulong id = get_global_id(0); + + if (id >= size) { + return; + } + + if (bufUInt) { + __global uint* element = &bufUInt[offset + id * patternSize]; + __constant uint* pt = (__constant uint*)pattern; + + for (uint i = 0; i < patternSize; ++i) { + element[i] = pt[i]; + } + } + else { + __global uchar* element = &bufUChar[offset + id * patternSize]; + + for (uint i = 0; i < patternSize; ++i) { + element[i] = pattern[i]; + } + } +} + +__attribute__((always_inline)) void +__amd_fillBufferAligned( + __global uchar* bufUChar, + __global ushort* bufUShort, + __global uint* bufUInt, + __global ulong* bufULong, + __constant uchar* pattern, + uint patternSize, + ulong offset, + ulong size) +{ + ulong id = get_global_id(0); + + if (id >= size) { + return; + } + + if (bufULong) { + __global ulong* element = &bufULong[offset + id * patternSize]; + __constant ulong* pt = (__constant ulong*)pattern; + + for (uint i = 0; i < patternSize; ++i) { + element[i] = pt[i]; + } + } + else if (bufUInt) { + __global uint* element = &bufUInt[offset + id * patternSize]; + __constant uint* pt = (__constant uint*)pattern; + + for (uint i = 0; i < patternSize; ++i) { + element[i] = pt[i]; + } + } + else if (bufUShort) { + __global ushort* element = &bufUShort[offset + id * patternSize]; + __constant ushort* pt = (__constant ushort*)pattern; + + for (uint i = 0; i < patternSize; ++i) { + element[i] = pt[i]; + } + } + else { + __global uchar* element = &bufUChar[offset + id * patternSize]; + + for (uint i = 0; i < patternSize; ++i) { + element[i] = pattern[i]; + } + } +} + +__attribute__((always_inline)) void + __amd_fillBufferAlignedExt( + __global uchar* bufUChar, + __global ushort* bufUShort, + __global uint* bufUInt, + __global ulong* bufULong, + __global ulong2* bufULong2, + __constant uchar* pattern, + uint pattern_size, + ulong offset, + ulong end_ptr, + uint next_chunk) +{ + int id = get_global_id(0); + long cur_id = offset + id * pattern_size; + if (bufULong2) { + __global ulong2* element = &bufULong2[cur_id]; + __constant ulong2* pt = (__constant ulong2*)pattern; + while ((ulong)element < end_ptr) { + for (uint i = 0; i < pattern_size; ++i) { + element[i] = pt[i]; + } + element += next_chunk; + } + } else if (bufULong) { + __global ulong* element = &bufULong[cur_id]; + __constant ulong* pt = (__constant ulong*)pattern; + while ((ulong)element < end_ptr) { + for (uint i = 0; i < pattern_size; ++i) { + element[i] = pt[i]; + } + element += next_chunk; + } + } else if (bufUInt) { + __global uint* element = &bufUInt[cur_id]; + __constant uint* pt = (__constant uint*)pattern; + while ((ulong)element < end_ptr) { + for (uint i = 0; i < pattern_size; ++i) { + element[i] = pt[i]; + } + element += next_chunk; + } + } else if (bufUShort) { + __global ushort* element = &bufUShort[cur_id]; + __constant ushort* pt = (__constant ushort*)pattern; + while ((ulong)element < end_ptr) { + for (uint i = 0; i < pattern_size; ++i) { + element[i] = pt[i]; + } + element += next_chunk; + } + } else { + __global uchar* element = &bufUChar[cur_id]; + while ((ulong)element < end_ptr) { + for (uint i = 0; i < pattern_size; ++i) { + element[i] = pattern[i]; + } + element += next_chunk; + } + } +} + +__attribute__((always_inline)) void +__amd_fillBufferAligned2D(__global uchar* bufUChar, + __global ushort* bufUShort, + __global uint* bufUInt, + __global ulong* bufULong, + __constant uchar* pattern, + uint patternSize, + ulong origin, + ulong width, + ulong height, + ulong pitch) +{ + ulong tid_x = get_global_id(0); + ulong tid_y = get_global_id(1); + + if (tid_x >= width || tid_y >= height) { + return; + } + + ulong offset = (tid_y * pitch + tid_x); + + if (bufULong) { + __global ulong* element = &bufULong[origin + offset]; + __constant ulong* pt = (__constant ulong*)pattern; + for (uint i = 0; i < patternSize; ++i) { + element[i] = pt[i]; + } + } else if (bufUInt) { + __global uint* element = &bufUInt[origin + offset]; + __constant uint* pt = (__constant uint*)pattern; + for (uint i = 0; i < patternSize; ++i) { + element[i] = pt[i]; + } + } else if (bufUShort) { + __global ushort* element = &bufUShort[origin + offset]; + __constant ushort* pt = (__constant ushort*)pattern; + for (uint i = 0; i < patternSize; ++i) { + element[i] = pt[i]; + } + } else if (bufUChar) { + __global uchar* element = &bufUChar[origin + offset]; + __constant uchar* pt = (__constant uchar*)pattern; + for (uint i = 0; i < patternSize; ++i) { + element[i] = pt[i]; + } + } +} + +__attribute__((always_inline)) void +__amd_fillImage( + __write_only image2d_array_t image, + float4 patternFLOAT4, + int4 patternINT4, + uint4 patternUINT4, + int4 origin, + int4 size, + uint type) +{ + int4 coords; + + coords.x = get_global_id(0); + coords.y = get_global_id(1); + coords.z = get_global_id(2); + coords.w = 0; + + if ((coords.x >= size.x) || + (coords.y >= size.y) || + (coords.z >= size.z)) { + return; + } + + coords += origin; + + int SizeX = get_global_size(0); + int AdjustedSizeX = size.x + origin.x; + + for (uint i = 0; i < SplitCount; ++i) { + // Check components + switch (type) { + case 0: + write_imagef(image, coords, patternFLOAT4); + break; + case 1: + write_imagei(image, coords, patternINT4); + break; + case 2: + write_imageui(image, coords, patternUINT4); + break; + } + coords.x += SizeX; + if (coords.x >= AdjustedSizeX) return; + } +} + + +__attribute__((always_inline)) void +__amd_streamOpsWrite( + __global atomic_uint* ptrUint, + __global atomic_ulong* ptrUlong, + ulong value) { + + // The launch parameters for this shader is a 1 grid work-item + + // 32-bit write + if (ptrUint) { + atomic_store_explicit(ptrUint, (uint)value, memory_order_relaxed, memory_scope_all_svm_devices); + } + // 64-bit write + else { + atomic_store_explicit(ptrUlong, value, memory_order_relaxed, memory_scope_all_svm_devices); + } +} + + +__attribute__((always_inline)) void +__amd_streamOpsWait( + __global atomic_uint* ptrUint, + __global atomic_ulong* ptrUlong, + ulong value, ulong compareOp, ulong mask) { + + // The launch parameters for this shader is a 1 grid work-item + + switch (compareOp) { + case 0: //GEQ + if (ptrUint) { + while ((int)(atomic_load_explicit(ptrUint, memory_order_relaxed, + memory_scope_all_svm_devices) & (uint)mask) < (uint)value) { + __builtin_amdgcn_s_sleep(1); + } + } + else { + while ((long)(atomic_load_explicit(ptrUlong, memory_order_relaxed, + memory_scope_all_svm_devices) & mask) < value) { + __builtin_amdgcn_s_sleep(1); + } + } + break; + + case 1: // EQ + if (ptrUint) { + while ((atomic_load_explicit(ptrUint, memory_order_relaxed, + memory_scope_all_svm_devices) & (uint)mask) != (uint)value) { + __builtin_amdgcn_s_sleep(1); + } + } + else { + while ((atomic_load_explicit(ptrUlong, memory_order_relaxed, + memory_scope_all_svm_devices) & mask) != value) { + __builtin_amdgcn_s_sleep(1); + } + } + break; + + case 2: //AND + if (ptrUint) { + while (!((atomic_load_explicit(ptrUint, memory_order_relaxed, + memory_scope_all_svm_devices) & (uint)mask) & (uint)value)) { + __builtin_amdgcn_s_sleep(1); + } + } + else { + while (!((atomic_load_explicit(ptrUlong, memory_order_relaxed, + memory_scope_all_svm_devices) & mask) & value)) { + __builtin_amdgcn_s_sleep(1); + } + } + break; + + case 3: //NOR + if (ptrUint) { + while (((atomic_load_explicit(ptrUint, memory_order_relaxed, + memory_scope_all_svm_devices) | (uint)value) & (uint)mask) == (uint)mask) { + __builtin_amdgcn_s_sleep(1); + } + } + else { + while (((atomic_load_explicit(ptrUlong, memory_order_relaxed, + memory_scope_all_svm_devices) | value) & mask) == mask) { + __builtin_amdgcn_s_sleep(1); + } + } + break; + } +} + +// The kernel calling this function must be launched with 'count' workgroups each of size 1 +__attribute__((always_inline)) void +__amd_batchMemOp(__global BatchMemOpParams* param, + uint count) { + + ulong id = get_global_id(0); + + switch (param[id].operation) { + case STREAM_WAIT_VALUE_32: + __amd_streamOpsWait((__global atomic_uint*)param[id].waitValue.address, NULL, + (uint)param[id].waitValue.value, (uint)param[id].waitValue.flags, + (ulong)~0UL); + break; + case STREAM_WRITE_VALUE_32: + __amd_streamOpsWrite((__global atomic_uint*)param[id].writeValue.address, NULL, + (uint)param[id].writeValue.value); + break; + case STREAM_WAIT_VALUE_64: + __amd_streamOpsWait(NULL, (__global atomic_ulong*)param[id].waitValue.address, + (ulong)param[id].waitValue.value64, (uint)param[id].waitValue.flags, + (ulong)~0UL); + break; + case STREAM_WRITE_VALUE_64: + __amd_streamOpsWrite(NULL, (__global atomic_ulong*)param[id].writeValue.address, + (ulong)param[id].writeValue.value64); + break; + default: + break; + } +} +#endif diff --git a/amd/device-libs/opencl/src/misc/asqf.cl b/amd/device-libs/opencl/src/misc/asqf.cl new file mode 100644 index 0000000000000..d6a05968de60a --- /dev/null +++ b/amd/device-libs/opencl/src/misc/asqf.cl @@ -0,0 +1,39 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +__attribute__((overloadable, always_inline, const)) cl_mem_fence_flags +get_fence(void *a) +{ + return OCKL_MANGLE_T(is_local,addr)(a) ? CLK_LOCAL_MEM_FENCE : CLK_GLOBAL_MEM_FENCE; +} + +__attribute__((overloadable, always_inline, const)) cl_mem_fence_flags +get_fence(const void *a) +{ + return OCKL_MANGLE_T(is_local,addr)(a) ? CLK_LOCAL_MEM_FENCE : CLK_GLOBAL_MEM_FENCE; +} + +__attribute__((always_inline, const)) __global void * +__to_global(void *a) +{ + return OCKL_MANGLE_T(to,global)(a); +} + +__attribute__((always_inline, const)) __local void * +__to_local(void *a) +{ + return OCKL_MANGLE_T(to,local)(a); +} + +__attribute__((always_inline, const)) __private void * +__to_private(void *a) +{ + return OCKL_MANGLE_T(to,private)(a); +} + diff --git a/amd/device-libs/opencl/src/misc/atom.cl b/amd/device-libs/opencl/src/misc/atom.cl new file mode 100644 index 0000000000000..950e4f3d869d8 --- /dev/null +++ b/amd/device-libs/opencl/src/misc/atom.cl @@ -0,0 +1,446 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_int64_base_atomics : enable +#pragma OPENCL EXTENSION cl_khr_int64_extended_atomics : enable + +#define ATTR __attribute__((overloadable)) + +// Cast away volatile before calling clang builtin +#define VOLATILE + +#define AC_int(X) X +#define AC_uint(X) X +#define AC_long(X) X +#define AC_ulong(X) X +#define AC_intptr_t(X) X +#define AC_uintptr_t(X) X +#define AC_size_t(X) X +#define AC_ptrdiff_t(X) X +#define AC_float(X) as_int(X) +#define AC_double(X) as_long(X) + +#define RC_int(X) X +#define RC_uint(X) X +#define RC_long(X) X +#define RC_ulong(X) X +#define RC_intptr_t(X) X +#define RC_uintptr_t(X) X +#define RC_size_t(X) X +#define RC_ptrdiff_t(X) X +#define RC_float(X) as_float(X) +#define RC_double(X) as_double(X) + +#define AT_int atomic_int +#define AT_uint atomic_uint +#define AT_long atomic_long +#define AT_ulong atomic_ulong +#define AT_intptr_t atomic_intptr_t +#define AT_uintptr_t atomic_uintptr_t +#define AT_size_t atomic_size_t +#define AT_ptrdiff_t atomic_ptrdiff_t +#define AT_float atomic_int +#define AT_double atomic_long + +#define ET_int int +#define ET_uint uint +#define ET_long long +#define ET_ulong ulong +#define ET_intptr_t intptr_t +#define ET_uintptr_t uintptr_t +#define ET_size_t size_t +#define ET_ptrdiff_t ptrdiff_t +#define ET_float int +#define ET_double long + +#define OCL12_MEMORY_ORDER memory_order_relaxed +#define OCL12_MEMORY_SCOPE memory_scope_device + +#define F_inc __opencl_atomic_fetch_add +#define F_dec __opencl_atomic_fetch_sub + +// extension and 1.2 functions +#define GEN1(T,A,O) \ +ATTR T \ +atom_##O(volatile A T *p, T v) \ +{ \ + return __opencl_atomic_fetch_##O((VOLATILE A atomic_##T *)p, v, OCL12_MEMORY_ORDER, OCL12_MEMORY_SCOPE); \ +} + +#define GEN2(T,A,O) \ +ATTR T \ +atomic_##O(volatile A T *p, T v) \ +{ \ + return __opencl_atomic_fetch_##O((VOLATILE A atomic_##T *)p, v, OCL12_MEMORY_ORDER, OCL12_MEMORY_SCOPE); \ +} + +#define OPSA(F,T,A) \ + F(T,A,add) \ + F(T,A,sub) \ + F(T,A,max) \ + F(T,A,min) \ + F(T,A,and) \ + F(T,A,or) \ + F(T,A,xor) + +#define OPS(F,T) \ + OPSA(F,T,__local) \ + OPSA(F,T,__global) \ + OPSA(F,T,) + +#define ALL() \ + OPS(GEN1,int) \ + OPS(GEN2,int) \ + OPS(GEN1,uint) \ + OPS(GEN2,uint) \ + OPS(GEN1,long) \ + OPS(GEN1,ulong) + +ALL() + +// Handle inc and dec +#undef GEN1 +#undef GEN2 +#undef OPSA + +#define OPSA(F,T,A) \ + F(T,A,inc) \ + F(T,A,dec) + + +#define GEN1(T,A,O) \ +ATTR T \ +atom_##O(volatile A T *p) \ +{ \ + return F_##O((VOLATILE A atomic_##T *)p, (T)1, OCL12_MEMORY_ORDER, OCL12_MEMORY_SCOPE); \ +} + +#define GEN2(T,A,O) \ +ATTR T \ +atomic_##O(volatile A T *p) \ +{ \ + return F_##O((VOLATILE A atomic_##T *)p, (T)1, OCL12_MEMORY_ORDER, OCL12_MEMORY_SCOPE); \ +} + +ALL() + +// Handle xchg +#undef GEN1 +#undef GEN2 +#undef OPSA +#undef OPS + +#define GEN1(T,A) \ +ATTR T \ +atom_xchg(volatile A T *p, T v) \ +{ \ + return __opencl_atomic_exchange((VOLATILE A atomic_##T *)p, v, OCL12_MEMORY_ORDER, OCL12_MEMORY_SCOPE); \ +} + +#define GEN2(T,A) \ +ATTR T \ +atomic_xchg(volatile A T *p, T v) \ +{ \ + return __opencl_atomic_exchange((VOLATILE A atomic_##T *)p, v, OCL12_MEMORY_ORDER, OCL12_MEMORY_SCOPE); \ +} + +#define OPS(F,T) \ + F(T,__local) \ + F(T,__global) \ + F(T,) \ + +ALL() + +#define G(A) \ +ATTR float \ +atomic_xchg(volatile A float *p, float v) \ +{ \ + return as_float(__opencl_atomic_exchange((VOLATILE A atomic_int *)p, as_int(v), OCL12_MEMORY_ORDER, OCL12_MEMORY_SCOPE)); \ +} + +G(__local) +G(__global) +G() + +// Handle cmpxchg +#undef GEN1 +#undef GEN2 +#undef G + +#define GEN1(T,A) \ +ATTR T \ +atom_cmpxchg(volatile A T *p, T e, T d) \ +{ \ + __opencl_atomic_compare_exchange_strong((VOLATILE A atomic_##T *)p, &e, d, OCL12_MEMORY_ORDER, OCL12_MEMORY_ORDER, OCL12_MEMORY_SCOPE); \ + return e; \ +} + +#define GEN2(T,A) \ +ATTR T \ +atomic_cmpxchg(volatile A T *p, T e, T d) \ +{ \ + __opencl_atomic_compare_exchange_strong((VOLATILE A atomic_##T *)p, &e, d, OCL12_MEMORY_ORDER, OCL12_MEMORY_ORDER, OCL12_MEMORY_SCOPE); \ + return e; \ +} + +ALL() +#undef GEN1 +#undef GEN2 +#undef ALL + +// 2.0 functions +#undef EXPLICIT_ASPACES + +#define GENIA(A,T) \ +ATTR void \ +atomic_init(volatile A atomic_##T *p, T v) \ +{ \ + __opencl_atomic_init((VOLATILE A atomic_##T *)p, v); \ +} + +#define GENSA(A,T) \ +ATTR void \ +atomic_store(volatile A atomic_##T *p, T v) \ +{ \ + __opencl_atomic_store((VOLATILE A atomic_##T *)p, v, memory_order_seq_cst, memory_scope_device); \ +} \ + \ +ATTR void \ +atomic_store_explicit(volatile A atomic_##T *p, T v, memory_order o) \ +{ \ + __opencl_atomic_store((VOLATILE A atomic_##T *)p, v, o, memory_scope_device); \ +} \ + \ +ATTR void \ +atomic_store_explicit(volatile A atomic_##T *p, T v, memory_order o, memory_scope s) \ +{ \ + __opencl_atomic_store((VOLATILE A atomic_##T *)p, v, o, s); \ +} + +#define GENLA(A,T) \ +ATTR T \ +atomic_load(volatile A atomic_##T *p) \ +{ \ + return __opencl_atomic_load((VOLATILE A atomic_##T *)p, memory_order_seq_cst, memory_scope_device); \ +} \ + \ +ATTR T \ +atomic_load_explicit(volatile A atomic_##T *p, memory_order o) \ +{ \ + return __opencl_atomic_load((VOLATILE A atomic_##T *)p, o, memory_scope_device); \ +} \ + \ +ATTR T \ +atomic_load_explicit(volatile A atomic_##T *p, memory_order o, memory_scope s) \ +{ \ + return __opencl_atomic_load((VOLATILE A atomic_##T *)p, o, s); \ +} + +#define GENXA(A,T) \ +ATTR T \ +atomic_exchange(volatile A atomic_##T *p, T v) \ +{ \ + return RC_##T(__opencl_atomic_exchange((VOLATILE A AT_##T *)p, AC_##T(v), memory_order_seq_cst, memory_scope_device)); \ +} \ + \ +ATTR T \ +atomic_exchange_explicit(volatile A atomic_##T *p, T v, memory_order o) \ +{ \ + return RC_##T(__opencl_atomic_exchange((VOLATILE A AT_##T *)p, AC_##T(v), o, memory_scope_device)); \ +} \ + \ +ATTR T \ +atomic_exchange_explicit(volatile A atomic_##T *p, T v, memory_order o, memory_scope s) \ +{ \ + return RC_##T(__opencl_atomic_exchange((VOLATILE A AT_##T *)p, AC_##T(v), o, s)); \ +} + +#define GENCXAA(AP,AE,T,K) \ +ATTR bool \ +atomic_compare_exchange_##K(volatile AP atomic_##T *p, AE T *e, T d) \ +{ \ + return __opencl_atomic_compare_exchange_##K((VOLATILE AP AT_##T *) p, (AE ET_##T *) e, AC_##T(d), memory_order_seq_cst, memory_order_seq_cst, memory_scope_device); \ +} \ + \ +ATTR bool \ +atomic_compare_exchange_##K##_explicit(volatile AP atomic_##T *p, AE T *e, T d, memory_order os, memory_order of) \ +{ \ + return __opencl_atomic_compare_exchange_##K((VOLATILE AP AT_##T *)p, (AE ET_##T *)e, AC_##T(d), os, of, memory_scope_device); \ +} \ + \ +ATTR bool \ +atomic_compare_exchange_##K##_explicit(volatile AP atomic_##T *p, AE T *e, T d, memory_order os, memory_order of, memory_scope s) \ +{ \ + return __opencl_atomic_compare_exchange_##K((VOLATILE AP AT_##T *) p, (AE ET_##T *)e, AC_##T(d), os, of, s); \ +} + +#if defined EXPLICIT_ASPACES +#define GENCXA(A,T,K) \ + GENCXAA(A,__global,T,K) \ + GENCXAA(A,__local,T,K) \ + GENCXAA(A,__private,T,K) \ + GENCXAA(A,,T,K) +#else +#define GENCXA(A,T,K) GENCXAA(A,,T,K) +#endif + +#define GENFOA(A,T,O) \ +ATTR T \ +atomic_fetch_##O(volatile A atomic_##T *p, T v) \ +{ \ + return RC_##T(__opencl_atomic_fetch_##O((VOLATILE A AT_##T *)p, AC_##T(v), memory_order_seq_cst, memory_scope_device)); \ +} \ + \ +ATTR T \ +atomic_fetch_##O##_explicit(volatile A atomic_##T *p, T v, memory_order o) \ +{ \ + return RC_##T(__opencl_atomic_fetch_##O((VOLATILE A AT_##T *)p, AC_##T(v), o, memory_scope_device)); \ +} \ + \ +ATTR T \ +atomic_fetch_##O##_explicit(volatile A atomic_##T *p, T v, memory_order o, memory_scope s) \ +{ \ + return RC_##T(__opencl_atomic_fetch_##O((VOLATILE A AT_##T *) p, AC_##T(v), o, s)); \ +} + +#define CXA(A,T) \ + GENCXA(A,T,strong) \ + GENCXA(A,T,weak) + +#define FOA(A,T) \ + GENFOA(A,T,add) \ + GENFOA(A,T,sub) \ + GENFOA(A,T,or) \ + GENFOA(A,T,xor) \ + GENFOA(A,T,and) \ + GENFOA(A,T,min) \ + GENFOA(A,T,max) \ + +#define ALLIA(A,F) \ + F(A,int) \ + F(A,uint) \ + F(A,long) \ + F(A,ulong) + +#define ALLA(A,F) \ + ALLIA(A,F) \ + F(A,float) \ + F(A,double) + +#if defined EXPLICIT_ASPACES +#define ALLI(F) \ + ALLIA(__global, F) \ + ALLIA(__local, F) \ + ALLIA(, F) +#else +#define ALLI(F) ALLIA(, F) +#endif + +#if defined EXPLICIT_ASPACES +#define ALL(F) \ + ALLA(__global,F) \ + ALLA(__local, F) \ + ALLA(, F) +#else +#define ALL(F) ALLA(, F) +#endif + +ALL(GENIA) +ALL(GENLA) +ALL(GENSA) +ALL(GENXA) +ALL(CXA) +ALLI(FOA) + +// These are needed for uintptr_t +#define UIP(A) \ +ATTR ulong \ +atomic_fetch_add(volatile A atomic_ulong *p, long v) \ +{ \ + return __opencl_atomic_fetch_add((VOLATILE A atomic_ulong *)p, (ulong)v, memory_order_seq_cst, memory_scope_device); \ +} \ + \ +ATTR ulong \ +atomic_fetch_add_explicit(volatile A atomic_ulong *p, long v, memory_order o) \ +{ \ + return __opencl_atomic_fetch_add((VOLATILE A atomic_ulong *)p, (ulong)v, o, memory_scope_device); \ +} \ + \ +ATTR ulong \ +atomic_fetch_add_explicit(volatile A atomic_ulong *p, long v, memory_order o, memory_scope s) \ +{ \ + return __opencl_atomic_fetch_add((VOLATILE A atomic_ulong *)p, (ulong)v, o, s); \ +} \ + \ +ATTR ulong \ +atomic_fetch_sub(volatile A atomic_ulong *p, long v) \ +{ \ + return __opencl_atomic_fetch_sub((VOLATILE A atomic_ulong *)p, (ulong)v, memory_order_seq_cst, memory_scope_device); \ +} \ + \ +ATTR ulong \ +atomic_fetch_sub_explicit(volatile A atomic_ulong *p, long v, memory_order o) \ +{ \ + return __opencl_atomic_fetch_sub((VOLATILE A atomic_ulong *)p, (ulong)v, o, memory_scope_device); \ +} \ + \ +ATTR ulong \ +atomic_fetch_sub_explicit(volatile A atomic_ulong *p, long v, memory_order o, memory_scope s) \ +{ \ + return __opencl_atomic_fetch_sub((VOLATILE A atomic_ulong *)p, (ulong)v, o, s); \ +} + +#if defined EXPLICIT_ASPACES +UIP(__global) +UIP(__local) +#endif +UIP() + +// flag functions +#define FLG(A) \ +ATTR bool \ +atomic_flag_test_and_set(volatile A atomic_flag *p) \ +{ \ + return __opencl_atomic_exchange((VOLATILE A atomic_int *)p, 1, memory_order_seq_cst, memory_scope_device); \ +} \ + \ +ATTR bool \ +atomic_flag_test_and_set_explicit(volatile A atomic_flag *p, memory_order o) \ +{ \ + return __opencl_atomic_exchange((VOLATILE A atomic_int *)p, 1, o, memory_scope_device); \ +} \ + \ +ATTR bool \ +atomic_flag_test_and_set_explicit(volatile A atomic_flag *p, memory_order o, memory_scope s) \ +{ \ + return __opencl_atomic_exchange((VOLATILE A atomic_int *)p, 1, o, s); \ +} \ + \ +ATTR void \ +atomic_flag_clear(volatile A atomic_flag *p) \ +{ \ + __opencl_atomic_store((VOLATILE A atomic_int *)p, 0, memory_order_seq_cst, memory_scope_device); \ +} \ + \ +ATTR void \ +atomic_flag_clear_explicit(volatile A atomic_flag *p, memory_order o) \ +{ \ + __opencl_atomic_store((VOLATILE A atomic_int *)p, 0, o, memory_scope_device); \ +} \ + \ +ATTR void \ +atomic_flag_clear_explicit(volatile A atomic_flag *p, memory_order o, memory_scope s) \ +{ \ + __opencl_atomic_store((VOLATILE A atomic_int *)p, 0, o, s); \ +} \ + +#if defined EXPLICIT_ASPACES +FLG(__global) +FLG(__local) +#endif +FLG() + diff --git a/amd/device-libs/opencl/src/misc/awif.cl b/amd/device-libs/opencl/src/misc/awif.cl new file mode 100644 index 0000000000000..69b30031f1adb --- /dev/null +++ b/amd/device-libs/opencl/src/misc/awif.cl @@ -0,0 +1,98 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_subgroups : enable + +__attribute__((overloadable)) void +mem_fence(cl_mem_fence_flags flags) +{ + atomic_work_item_fence(flags, memory_order_acq_rel, memory_scope_work_group); +} + +__attribute__((overloadable)) void +read_mem_fence(cl_mem_fence_flags flags) +{ + atomic_work_item_fence(flags, memory_order_acquire, memory_scope_work_group); +} + +__attribute__((overloadable)) void +write_mem_fence(cl_mem_fence_flags flags) +{ + atomic_work_item_fence(flags, memory_order_release, memory_scope_work_group); +} + +#define IMPL_ATOMIC_WORK_ITEM_FENCE(...) \ + if (order != memory_order_relaxed) { \ + switch (scope) { \ + case memory_scope_work_item: \ + break; \ + case memory_scope_sub_group: \ + switch (order) { \ + case memory_order_relaxed: break; \ + case memory_order_acquire: __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "wavefront" __VA_ARGS__); break;\ + case memory_order_release: __builtin_amdgcn_fence(__ATOMIC_RELEASE, "wavefront" __VA_ARGS__); break;\ + case memory_order_acq_rel: __builtin_amdgcn_fence(__ATOMIC_ACQ_REL, "wavefront" __VA_ARGS__); break;\ + case memory_order_seq_cst: __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "wavefront" __VA_ARGS__); break;\ + } \ + break; \ + case memory_scope_work_group: \ + switch (order) { \ + case memory_order_relaxed: break; \ + case memory_order_acquire: __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup" __VA_ARGS__); break;\ + case memory_order_release: __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup" __VA_ARGS__); break;\ + case memory_order_acq_rel: __builtin_amdgcn_fence(__ATOMIC_ACQ_REL, "workgroup" __VA_ARGS__); break;\ + case memory_order_seq_cst: __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup" __VA_ARGS__); break;\ + } \ + break; \ + case memory_scope_device: \ + switch (order) { \ + case memory_order_relaxed: break; \ + case memory_order_acquire: __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "agent" __VA_ARGS__); break; \ + case memory_order_release: __builtin_amdgcn_fence(__ATOMIC_RELEASE, "agent" __VA_ARGS__); break; \ + case memory_order_acq_rel: __builtin_amdgcn_fence(__ATOMIC_ACQ_REL, "agent" __VA_ARGS__); break; \ + case memory_order_seq_cst: __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "agent" __VA_ARGS__); break; \ + } \ + break; \ + case memory_scope_all_svm_devices: \ + switch (order) { \ + case memory_order_relaxed: break; \ + case memory_order_acquire: __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "" __VA_ARGS__); break; \ + case memory_order_release: __builtin_amdgcn_fence(__ATOMIC_RELEASE, "" __VA_ARGS__); break; \ + case memory_order_acq_rel: __builtin_amdgcn_fence(__ATOMIC_ACQ_REL, "" __VA_ARGS__); break; \ + case memory_order_seq_cst: __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "" __VA_ARGS__); break; \ + } \ + break; \ + } \ + } + +__attribute__((overloadable)) void +atomic_work_item_fence(cl_mem_fence_flags flags, memory_order order, memory_scope scope) +{ + // The AS to fence (if only global or local is needed) is encoded in + // metadata attached to the fence instruction by the builtin. + // That metadata may be dropped in some cases, if that happens then + // we are tying global-happens-before and local-happens-before together + // as does HSA + + if (flags) { + // global or image is set, but not local -> fence only global memory. + if ((flags & CLK_LOCAL_MEM_FENCE) == 0) { + IMPL_ATOMIC_WORK_ITEM_FENCE(, "global"); + return; + } + + // only local is set + if (flags == CLK_LOCAL_MEM_FENCE) { + IMPL_ATOMIC_WORK_ITEM_FENCE(, "local"); + return; + } + + // all flags are set, same as if none are set -> fence all. + } + + IMPL_ATOMIC_WORK_ITEM_FENCE(); +} diff --git a/amd/device-libs/opencl/src/misc/conversions.cl b/amd/device-libs/opencl/src/misc/conversions.cl new file mode 100644 index 0000000000000..9e4cdaf2fef22 --- /dev/null +++ b/amd/device-libs/opencl/src/misc/conversions.cl @@ -0,0 +1,1856 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ATTR __attribute__((overloadable, const)) +#define IATTR __attribute__((const)) +#define AATTR(S) __attribute__((overloadable, const, alias(S))) + +#define _C(A,B) A##B +#define C(A,B) _C(A,B) + + +#if !defined USE_CLP +#define NOPN(N,TO,TI,S,R) ATTR TO##N convert_##TO##N##S##R(TO##N x) { return x; } + +#define NOP(TO,TI,S,R) \ + NOPN(16,TO,TI,S,R) \ + NOPN(8,TO,TI,S,R) \ + NOPN(4,TO,TI,S,R) \ + NOPN(3,TO,TI,S,R) \ + NOPN(2,TO,TI,S,R) \ + NOPN(,TO,TI,S,R) + +#define XLIST x +#define XLIST2 x.s0, x.s1 +#define XLIST3 XLIST2, x.s2 +#define XLIST4 XLIST3, x.s3 +#define XLIST8 XLIST4, x.s4, x.s5, x.s6, x.s7 +#define XLIST16 XLIST8, x.s8, x.s9, x.sa, x.sb, x.sc, x.sd, x.se, x.sf + +#define YLIST y +#define YLIST2 y.s0, y.s1 +#define YLIST3 YLIST2, y.s2 +#define YLIST4 YLIST3, y.s3 +#define YLIST8 YLIST4, y.s4, y.s5, y.s6, y.s7 +#define YLIST16 YLIST8, y.s8, y.s9, y.sa, y.sb, y.sc, y.sd, y.se, y.sf + +#define CASTN(N,TO,TI,S,R) ATTR TO##N convert_##TO##N##S##R(TI##N x) { return (TO##N)(XLIST##N); } + +#define CAST(TO,TI,S,R) \ + CASTN(16,TO,TI,S,R) \ + CASTN(8,TO,TI,S,R) \ + CASTN(4,TO,TI,S,R) \ + CASTN(3,TO,TI,S,R) \ + CASTN(2,TO,TI,S,R) \ + CASTN(,TO,TI,S,R) +#else +#define NOP(TO,TI,S,R) +#define CAST(TO,TI,S,R) +#endif + +#define char_short_lb CHAR_MIN +#define char_short_ub CHAR_MAX +#define char_int_lb CHAR_MIN +#define char_int_ub CHAR_MAX +#define char_long_lb CHAR_MIN +#define char_long_ub CHAR_MAX +#define char_float_lb CHAR_MIN +#define char_float_ub CHAR_MAX +#define char_double_lb CHAR_MIN +#define char_double_ub CHAR_MAX +#define char_half_lb CHAR_MIN +#define char_half_ub CHAR_MAX + +#define uchar_short_lb 0 +#define uchar_short_ub UCHAR_MAX +#define uchar_int_lb 0 +#define uchar_int_ub UCHAR_MAX +#define uchar_long_lb 0 +#define uchar_long_ub UCHAR_MAX +#define uchar_float_lb 0 +#define uchar_float_ub UCHAR_MAX +#define uchar_double_lb 0 +#define uchar_double_ub UCHAR_MAX +#define uchar_half_lb 0 +#define uchar_half_ub UCHAR_MAX + +#define short_int_lb SHRT_MIN +#define short_int_ub SHRT_MAX +#define short_long_lb SHRT_MIN +#define short_long_ub SHRT_MAX +#define short_float_lb SHRT_MIN +#define short_float_ub SHRT_MAX +#define short_double_lb SHRT_MIN +#define short_double_ub SHRT_MAX +#define short_half_lb -HALF_MAX +#define short_half_ub HALF_MAX + +#define ushort_int_lb 0 +#define ushort_int_ub USHRT_MAX +#define ushort_long_lb 0 +#define ushort_long_ub USHRT_MAX +#define ushort_float_lb 0 +#define ushort_float_ub USHRT_MAX +#define ushort_double_lb 0 +#define ushort_double_ub USHRT_MAX +#define ushort_half_lb 0 +#define ushort_half_ub HALF_MAX + +#define int_long_lb INT_MIN +#define int_long_ub INT_MAX +#define int_float_lb INT_MIN +#define int_float_ub 0x7fffff80 +#define int_double_lb INT_MIN +#define int_double_ub INT_MAX +#define int_half_lb -HALF_MAX +#define int_half_ub HALF_MAX + +#define uint_long_lb 0 +#define uint_long_ub UINT_MAX +#define uint_float_lb 0 +#define uint_float_ub 0xffffff00U +#define uint_double_lb 0 +#define uint_double_ub UINT_MAX +#define uint_half_lb 0 +#define uint_half_ub HALF_MAX + +#define long_float_lb LONG_MIN +#define long_float_ub 0x7fffff8000000000L +#define long_double_lb LONG_MIN +#define long_double_ub 0x7ffffffffffffc00L +#define long_half_lb -HALF_MAX +#define long_half_ub HALF_MAX + +#define ulong_float_lb 0 +#define ulong_float_ub 0xffffff0000000000UL +#define ulong_double_lb 0 +#define ulong_double_ub 0xfffffffffffff800UL +#define ulong_half_lb 0 +#define ulong_half_ub HALF_MAX + +#define char_minbnd CHAR_MAX +#define uchar_minbnd UCHAR_MAX +#define short_minbnd SHRT_MAX +#define ushort_minbnd USHRT_MAX +#define int_minbnd INT_MAX +#define uint_minbnd UINT_MAX +#define long_minbnd LONG_MAX +#define ulong_minbnd ULONG_MAX + +#define char_maxbnd CHAR_MIN +#define uchar_maxbnd 0 +#define short_maxbnd SHRT_MIN +#define ushort_maxbnd 0 +#define int_maxbnd INT_MIN +#define uint_maxbnd 0 +#define long_maxbnd LONG_MIN +#define ulong_maxbnd 0 + +#define HALFBND 65535 + +#define MMN(F,N,TO,TI,S,R) \ +ATTR TO##N \ +convert_##TO##N##S##R(TI##N x) \ +{ \ + return convert_##TO##N(F(x, (TI##N) TO##_##F##bnd)); \ +} + +#define MIN(TO,TI,S,R) \ + MMN(min,16,TO,TI,S,R) \ + MMN(min,8,TO,TI,S,R) \ + MMN(min,4,TO,TI,S,R) \ + MMN(min,3,TO,TI,S,R) \ + MMN(min,2,TO,TI,S,R) \ + MMN(min,,TO,TI,S,R) + +#define MAX(TO,TI,S,R) \ + MMN(max,16,TO,TI,S,R) \ + MMN(max,8,TO,TI,S,R) \ + MMN(max,4,TO,TI,S,R) \ + MMN(max,3,TO,TI,S,R) \ + MMN(max,2,TO,TI,S,R) \ + MMN(max,,TO,TI,S,R) + +#define CLAMPN(N,TO,TI,S,R) \ +ATTR TO##N \ +convert_##TO##N##S##R(TI##N x) \ +{ \ + return convert_##TO##N(min(max(x, (TI##N) TO##_##TI##_lb), (TI##N) TO##_##TI##_ub)); \ +} + +#define CLAMP(TO,TI,S,R) \ + CLAMPN(16,TO,TI,S,R) \ + CLAMPN(8,TO,TI,S,R) \ + CLAMPN(4,TO,TI,S,R) \ + CLAMPN(3,TO,TI,S,R) \ + CLAMPN(2,TO,TI,S,R) \ + CLAMPN(,TO,TI,S,R) + +#define F2IEN(E,N,TO,TI,S,R) \ +ATTR TO##N \ +convert_##TO##N##S##R(TI##N x) \ +{ \ + return convert_##TO##N##_sat##E(x); \ +} + +#define F2IE(E,TO,TI,S,R) \ + F2IEN(E,16,TO,TI,S,R) \ + F2IEN(E,8,TO,TI,S,R) \ + F2IEN(E,4,TO,TI,S,R) \ + F2IEN(E,3,TO,TI,S,R) \ + F2IEN(E,2,TO,TI,S,R) \ + F2IEN(E,,TO,TI,S,R) + +#define EF2I(TO,TI,S,R) F2IE(_rte,TO,TI,S,R) +#define NF2I(TO,TI,S,R) F2IE(_rtn,TO,TI,S,R) +#define PF2I(TO,TI,S,R) F2IE(_rtp,TO,TI,S,R) +#define ZF2I(TO,TI,S,R) F2IE(_rtz,TO,TI,S,R) + +#define CLAMPFN(F,N,TO,TI,S,R) \ +ATTR TO##N \ +convert_##TO##N##S##R(TI##N x) \ +{ \ + x = min(max(F(x), (TI##N) TO##_##TI##_lb), (TI##N) TO##_##TI##_ub); \ + return (TO##N)(XLIST##N); \ +} + +#define CLAMPF(F,TO,TI,S,R) \ + CLAMPFN(F,16,TO,TI,S,R) \ + CLAMPFN(F,8,TO,TI,S,R) \ + CLAMPFN(F,4,TO,TI,S,R) \ + CLAMPFN(F,3,TO,TI,S,R) \ + CLAMPFN(F,2,TO,TI,S,R) \ + CLAMPFN(F,,TO,TI,S,R) + +#define ECLAMP(TO,TI,S,R) CLAMPF(rint,TO,TI,S,R) +#define NCLAMP(TO,TI,S,R) CLAMPF(floor,TO,TI,S,R) +#define PCLAMP(TO,TI,S,R) CLAMPF(ceil,TO,TI,S,R) +#define ZCLAMP(TO,TI,S,R) CLAMPF(,TO,TI,S,R) + +#define SEL_(A,B,C) C ? B : A +#define SEL_2(A,B,C) select(A,B,C) +#define SEL_3(A,B,C) select(A,B,C) +#define SEL_4(A,B,C) select(A,B,C) +#define SEL_8(A,B,C) select(A,B,C) +#define SEL_16(A,B,C) select(A,B,C) + +#define nou_short short +#define nou_ushort short +#define nou_int int +#define nou_uint int +#define nou_long long +#define nou_ulong long + +#define CMP(N,TO,TI,X,OP,B) \ + C(convert_,C(nou_##TO, N))(X OP (TI##N) TO##_##TI##_##B) + +#define CMP_(TO,TI,X,OP,B) (X OP (TI) TO##_##TI##_##B) +#define CMP_2(TO,TI,X,OP,B) CMP(2,TO,TI,X,OP,B) +#define CMP_3(TO,TI,X,OP,B) CMP(3,TO,TI,X,OP,B) +#define CMP_4(TO,TI,X,OP,B) CMP(4,TO,TI,X,OP,B) +#define CMP_8(TO,TI,X,OP,B) CMP(8,TO,TI,X,OP,B) +#define CMP_16(TO,TI,X,OP,B) CMP(16,TO,TI,X,OP,B) + +#define CLAMP2FN(F,N,TO,TI,S,R) \ +ATTR TO##N \ +convert_##TO##N##S##R(TI##N x) \ +{ \ + TI##N y = min(max(F(x), (TI##N) TO##_##TI##_lb), (TI##N) TO##_##TI##_ub); \ + TO##N z = (TO##N)(YLIST##N); \ + z = SEL_##N(z, (TO##N) TO##_minbnd, CMP_##N(TO,TI,x,>,ub)); \ + return SEL_##N(z, (TO##N) TO##_maxbnd, CMP_##N(TO,TI,x,<,lb)); \ +} + +#define CLAMP2F(F,TO,TI,S,R) \ + CLAMP2FN(F,16,TO,TI,S,R) \ + CLAMP2FN(F,8,TO,TI,S,R) \ + CLAMP2FN(F,4,TO,TI,S,R) \ + CLAMP2FN(F,3,TO,TI,S,R) \ + CLAMP2FN(F,2,TO,TI,S,R) \ + CLAMP2FN(F,,TO,TI,S,R) + +#define ECLAMP2(TO,TI,S,R) CLAMP2F(rint,TO,TI,S,R) +#define NCLAMP2(TO,TI,S,R) CLAMP2F(floor,TO,TI,S,R) +#define PCLAMP2(TO,TI,S,R) CLAMP2F(ceil,TO,TI,S,R) +#define ZCLAMP2(TO,TI,S,R) CLAMP2F(,TO,TI,S,R) + +#define EXPAND2(TO,TI,S,R) \ +ATTR TO##2 \ +convert_##TO##2##S##R(TI##2 x) \ +{ \ + return (TO##2)(convert_##TO##S##R(x.lo), \ + convert_##TO##S##R(x.hi)); \ +} + +#define EXPAND3(TO,TI,S,R) \ +ATTR TO##3 \ +convert_##TO##3##S##R(TI##3 x) \ +{ \ + return (TO##3)(convert_##TO##2##S##R(x.s01), \ + convert_##TO##S##R(x.s2)); \ +} + +#define EXPAND4(TO,TI,S,R) \ +ATTR TO##4 \ +convert_##TO##4##S##R(TI##4 x) \ +{ \ + return (TO##4)(convert_##TO##2##S##R(x.lo), \ + convert_##TO##2##S##R(x.hi)); \ +} + +#define EXPAND8(TO,TI,S,R) \ +ATTR TO##8 \ +convert_##TO##8##S##R(TI##8 x) \ +{ \ + return (TO##8)(convert_##TO##4##S##R(x.lo), \ + convert_##TO##4##S##R(x.hi)); \ +} + +#define EXPAND16(TO,TI,S,R) \ +ATTR TO##16 \ +convert_##TO##16##S##R(TI##16 x) \ +{ \ + return (TO##16)(convert_##TO##8##S##R(x.lo), \ + convert_##TO##8##S##R(x.hi)); \ +} + +#define EXPAND(TO,TI,S,R) \ + EXPAND16(TO,TI,S,R) \ + EXPAND8(TO,TI,S,R) \ + EXPAND4(TO,TI,S,R) \ + EXPAND3(TO,TI,S,R) \ + EXPAND2(TO,TI,S,R) + +#define G_char_char(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_char_sat_char(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_char_sat_rte_char(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_char_sat_rtn_char(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_char_sat_rtp_char(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_char_sat_rtz_char(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_char_rte_char(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_char_rtn_char(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_char_rtp_char(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_char_rtz_char(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_char_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_sat_uchar(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rte_uchar(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtn_uchar(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtp_uchar(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtz_uchar(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_sat_short(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rte_short(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rtn_short(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rtp_short(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rtz_short(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_sat_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rte_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtn_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtp_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtz_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_sat_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rte_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rtn_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rtp_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rtz_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtn_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtp_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtz_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_sat_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rte_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtn_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtp_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtz_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtn_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtp_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtz_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_sat_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rte_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rtn_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rtp_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_sat_rtz_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_char_rte_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtn_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtp_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtz_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_sat_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rte_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtn_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtp_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_sat_rtz_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_char_rte_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtn_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtp_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_rtz_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_char_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_char_sat_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_char_sat_rte_float(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_char_sat_rtn_float(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_char_sat_rtp_float(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_char_sat_rtz_float(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_char_rte_float(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_char_rtn_float(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_char_rtp_float(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_char_rtz_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_char_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_char_sat_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_char_sat_rte_double(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_char_sat_rtn_double(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_char_sat_rtp_double(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_char_sat_rtz_double(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_char_rte_double(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_char_rtn_double(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_char_rtp_double(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_char_rtz_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_char_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_char_sat_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_char_sat_rte_half(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_char_sat_rtn_half(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_char_sat_rtp_half(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_char_sat_rtz_half(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_char_rte_half(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_char_rtn_half(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_char_rtp_half(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_char_rtz_half(TO,TI,S,R) ZF2I(TO,TI,S,R) + +#define G_uchar_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_sat_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uchar_sat_rte_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uchar_sat_rtn_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uchar_sat_rtp_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uchar_sat_rtz_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uchar_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_uchar(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uchar_sat_uchar(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uchar_sat_rte_uchar(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uchar_sat_rtn_uchar(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uchar_sat_rtp_uchar(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uchar_sat_rtz_uchar(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uchar_rte_uchar(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uchar_rtn_uchar(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uchar_rtp_uchar(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uchar_rtz_uchar(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uchar_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_sat_short(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rte_short(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rtn_short(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rtp_short(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rtz_short(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_sat_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rte_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rtn_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rtp_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rtz_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_sat_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rte_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rtn_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rtp_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rtz_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtn_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtp_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtz_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_sat_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rte_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rtn_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rtp_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rtz_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtn_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtp_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtz_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_sat_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rte_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rtn_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rtp_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_sat_rtz_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uchar_rte_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtn_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtp_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtz_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_sat_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rte_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rtn_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rtp_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_sat_rtz_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uchar_rte_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtn_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtp_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_rtz_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uchar_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uchar_sat_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uchar_sat_rte_float(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_uchar_sat_rtn_float(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_uchar_sat_rtp_float(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_uchar_sat_rtz_float(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_uchar_rte_float(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_uchar_rtn_float(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_uchar_rtp_float(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_uchar_rtz_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uchar_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uchar_sat_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uchar_sat_rte_double(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_uchar_sat_rtn_double(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_uchar_sat_rtp_double(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_uchar_sat_rtz_double(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_uchar_rte_double(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_uchar_rtn_double(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_uchar_rtp_double(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_uchar_rtz_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uchar_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uchar_sat_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uchar_sat_rte_half(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_uchar_sat_rtn_half(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_uchar_sat_rtp_half(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_uchar_sat_rtz_half(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_uchar_rte_half(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_uchar_rtn_half(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_uchar_rtp_half(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_uchar_rtz_half(TO,TI,S,R) ZF2I(TO,TI,S,R) + +#define G_short_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_short(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_short_sat_short(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_short_sat_rte_short(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_short_sat_rtn_short(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_short_sat_rtp_short(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_short_sat_rtz_short(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_short_rte_short(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_short_rtn_short(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_short_rtp_short(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_short_rtz_short(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_short_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rte_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rtn_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rtp_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rtz_ushort(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_short_sat_rte_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_short_sat_rtn_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_short_sat_rtp_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_short_sat_rtz_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_short_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtn_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtp_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtz_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rte_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rtn_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rtp_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rtz_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtn_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtp_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtz_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_short_sat_rte_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_short_sat_rtn_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_short_sat_rtp_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_short_sat_rtz_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_short_rte_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtn_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtp_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtz_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_sat_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rte_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rtn_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rtp_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_sat_rtz_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_short_rte_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtn_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtp_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_rtz_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_short_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_short_sat_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_short_sat_rte_float(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_short_sat_rtn_float(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_short_sat_rtp_float(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_short_sat_rtz_float(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_short_rte_float(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_short_rtn_float(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_short_rtp_float(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_short_rtz_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_short_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_short_sat_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_short_sat_rte_double(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_short_sat_rtn_double(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_short_sat_rtp_double(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_short_sat_rtz_double(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_short_rte_double(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_short_rtn_double(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_short_rtp_double(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_short_rtz_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_short_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_short_sat_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_short_sat_rte_half(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_short_sat_rtn_half(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_short_sat_rtp_half(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_short_sat_rtz_half(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_short_rte_half(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_short_rtn_half(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_short_rtp_half(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_short_rtz_half(TO,TI,S,R) ZF2I(TO,TI,S,R) + +#define G_ushort_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ushort_sat_rte_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ushort_sat_rtn_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ushort_sat_rtp_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ushort_sat_rtz_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ushort_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ushort_sat_rte_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ushort_sat_rtn_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ushort_sat_rtp_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ushort_sat_rtz_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ushort_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_ushort(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ushort_sat_ushort(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ushort_sat_rte_ushort(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ushort_sat_rtn_ushort(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ushort_sat_rtp_ushort(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ushort_sat_rtz_ushort(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ushort_rte_ushort(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ushort_rtn_ushort(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ushort_rtp_ushort(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ushort_rtz_ushort(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ushort_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_ushort_sat_rte_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_ushort_sat_rtn_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_ushort_sat_rtp_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_ushort_sat_rtz_int(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_ushort_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtn_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtp_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtz_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_ushort_sat_rte_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_ushort_sat_rtn_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_ushort_sat_rtp_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_ushort_sat_rtz_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_ushort_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtn_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtp_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtz_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_ushort_sat_rte_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_ushort_sat_rtn_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_ushort_sat_rtp_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_ushort_sat_rtz_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_ushort_rte_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtn_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtp_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtz_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_sat_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_ushort_sat_rte_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_ushort_sat_rtn_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_ushort_sat_rtp_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_ushort_sat_rtz_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_ushort_rte_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtn_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtp_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_rtz_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ushort_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ushort_sat_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ushort_sat_rte_float(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_ushort_sat_rtn_float(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_ushort_sat_rtp_float(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_ushort_sat_rtz_float(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_ushort_rte_float(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_ushort_rtn_float(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_ushort_rtp_float(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_ushort_rtz_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ushort_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ushort_sat_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ushort_sat_rte_double(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_ushort_sat_rtn_double(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_ushort_sat_rtp_double(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_ushort_sat_rtz_double(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_ushort_rte_double(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_ushort_rtn_double(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_ushort_rtp_double(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_ushort_rtz_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ushort_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ushort_sat_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ushort_sat_rte_half(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_ushort_sat_rtn_half(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_ushort_sat_rtp_half(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_ushort_sat_rtz_half(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_ushort_rte_half(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_ushort_rtn_half(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_ushort_rtp_half(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_ushort_rtz_half(TO,TI,S,R) ZF2I(TO,TI,S,R) + +#define G_int_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_int(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_int_sat_int(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_int_sat_rte_int(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_int_sat_rtn_int(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_int_sat_rtp_int(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_int_sat_rtz_int(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_int_rte_int(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_int_rtn_int(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_int_rtp_int(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_int_rtz_int(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_int_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_int_sat_rte_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_int_sat_rtn_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_int_sat_rtp_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_int_sat_rtz_uint(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_int_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtn_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtp_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtz_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_int_sat_rte_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_int_sat_rtn_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_int_sat_rtp_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_int_sat_rtz_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_int_rte_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtn_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtp_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtz_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_sat_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_int_sat_rte_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_int_sat_rtn_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_int_sat_rtp_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_int_sat_rtz_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_int_rte_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtn_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtp_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_rtz_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_int_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_int_sat_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_int_sat_rte_float(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_int_sat_rtn_float(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_int_sat_rtp_float(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_int_sat_rtz_float(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_int_rte_float(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_int_rtn_float(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_int_rtp_float(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_int_rtz_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_int_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_int_sat_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_int_sat_rte_double(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_int_sat_rtn_double(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_int_sat_rtp_double(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_int_sat_rtz_double(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_int_rte_double(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_int_rtn_double(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_int_rtp_double(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_int_rtz_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_int_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_int_sat_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_int_sat_rte_half(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_int_sat_rtn_half(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_int_sat_rtp_half(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_int_sat_rtz_half(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_int_rte_half(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_int_rtn_half(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_int_rtp_half(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_int_rtz_half(TO,TI,S,R) ZF2I(TO,TI,S,R) + +#define G_uint_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rte_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rtn_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rtp_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rtz_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rte_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rtn_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rtp_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rtz_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_int(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rte_int(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rtn_int(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rtp_int(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_sat_rtz_int(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_uint_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtn_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtp_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtz_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_uint(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uint_sat_uint(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uint_sat_rte_uint(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uint_sat_rtn_uint(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uint_sat_rtp_uint(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uint_sat_rtz_uint(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uint_rte_uint(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uint_rtn_uint(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uint_rtp_uint(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uint_rtz_uint(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_uint_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uint_sat_rte_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uint_sat_rtn_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uint_sat_rtp_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uint_sat_rtz_long(TO,TI,S,R) CLAMP(TO,TI,S,R) +#define G_uint_rte_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtn_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtp_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtz_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_sat_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uint_sat_rte_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uint_sat_rtn_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uint_sat_rtp_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uint_sat_rtz_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_uint_rte_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtn_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtp_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_rtz_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_uint_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uint_sat_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uint_sat_rte_float(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_uint_sat_rtn_float(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_uint_sat_rtp_float(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_uint_sat_rtz_float(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_uint_rte_float(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_uint_rtn_float(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_uint_rtp_float(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_uint_rtz_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uint_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uint_sat_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uint_sat_rte_double(TO,TI,S,R) ECLAMP(TO,TI,S,R) +#define G_uint_sat_rtn_double(TO,TI,S,R) NCLAMP(TO,TI,S,R) +#define G_uint_sat_rtp_double(TO,TI,S,R) PCLAMP(TO,TI,S,R) +#define G_uint_sat_rtz_double(TO,TI,S,R) ZCLAMP(TO,TI,S,R) +#define G_uint_rte_double(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_uint_rtn_double(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_uint_rtp_double(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_uint_rtz_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uint_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uint_sat_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_uint_sat_rte_half(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_uint_sat_rtn_half(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_uint_sat_rtp_half(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_uint_sat_rtz_half(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_uint_rte_half(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_uint_rtn_half(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_uint_rtp_half(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_uint_rtz_half(TO,TI,S,R) ZF2I(TO,TI,S,R) + +#define G_long_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtn_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtp_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtz_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtn_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtp_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtz_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtn_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtp_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_rtz_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtn_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtp_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtz_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_long(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_long_sat_long(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_long_sat_rte_long(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_long_sat_rtn_long(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_long_sat_rtp_long(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_long_sat_rtz_long(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_long_rte_long(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_long_rtn_long(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_long_rtp_long(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_long_rtz_long(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_long_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_sat_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_long_sat_rte_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_long_sat_rtn_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_long_sat_rtp_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_long_sat_rtz_ulong(TO,TI,S,R) MIN(TO,TI,S,R) +#define G_long_rte_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtn_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtp_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_rtz_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_long_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_long_sat_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_long_sat_rte_float(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_long_sat_rtn_float(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_long_sat_rtp_float(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_long_sat_rtz_float(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_long_rte_float(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_long_rtn_float(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_long_rtp_float(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_long_rtz_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_long_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_long_sat_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_long_sat_rte_double(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_long_sat_rtn_double(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_long_sat_rtp_double(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_long_sat_rtz_double(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_long_rte_double(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_long_rtn_double(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_long_rtp_double(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_long_rtz_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_long_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_long_sat_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_long_sat_rte_half(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_long_sat_rtn_half(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_long_sat_rtp_half(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_long_sat_rtz_half(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_long_rte_half(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_long_rtn_half(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_long_rtp_half(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_long_rtz_half(TO,TI,S,R) ZF2I(TO,TI,S,R) + +#define G_ulong_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rte_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtn_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtp_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtz_char(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rte_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtn_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtp_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtz_short(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_int(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rte_int(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtn_int(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtp_int(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtz_int(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtn_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtp_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtz_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rtn_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rtp_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_rtz_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtn_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtp_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtz_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_sat_long(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rte_long(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtn_long(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtp_long(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_sat_rtz_long(TO,TI,S,R) MAX(TO,TI,S,R) +#define G_ulong_rte_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtn_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtp_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_rtz_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_ulong_ulong(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ulong_sat_ulong(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ulong_sat_rte_ulong(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ulong_sat_rtn_ulong(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ulong_sat_rtp_ulong(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ulong_sat_rtz_ulong(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ulong_rte_ulong(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ulong_rtn_ulong(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ulong_rtp_ulong(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ulong_rtz_ulong(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_ulong_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ulong_sat_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ulong_sat_rte_float(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_ulong_sat_rtn_float(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_ulong_sat_rtp_float(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_ulong_sat_rtz_float(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_ulong_rte_float(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_ulong_rtn_float(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_ulong_rtp_float(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_ulong_rtz_float(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ulong_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ulong_sat_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ulong_sat_rte_double(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_ulong_sat_rtn_double(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_ulong_sat_rtp_double(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_ulong_sat_rtz_double(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_ulong_rte_double(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_ulong_rtn_double(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_ulong_rtp_double(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_ulong_rtz_double(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ulong_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ulong_sat_half(TO,TI,S,R) ZF2I(TO,TI,S,R) +#define G_ulong_sat_rte_half(TO,TI,S,R) ECLAMP2(TO,TI,S,R) +#define G_ulong_sat_rtn_half(TO,TI,S,R) NCLAMP2(TO,TI,S,R) +#define G_ulong_sat_rtp_half(TO,TI,S,R) PCLAMP2(TO,TI,S,R) +#define G_ulong_sat_rtz_half(TO,TI,S,R) ZCLAMP2(TO,TI,S,R) +#define G_ulong_rte_half(TO,TI,S,R) EF2I(TO,TI,S,R) +#define G_ulong_rtn_half(TO,TI,S,R) NF2I(TO,TI,S,R) +#define G_ulong_rtp_half(TO,TI,S,R) PF2I(TO,TI,S,R) +#define G_ulong_rtz_half(TO,TI,S,R) ZF2I(TO,TI,S,R) + +#define G_float_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_sat_char(TO,TI,S,R) +#define G_float_sat_rte_char(TO,TI,S,R) +#define G_float_sat_rtn_char(TO,TI,S,R) +#define G_float_sat_rtp_char(TO,TI,S,R) +#define G_float_sat_rtz_char(TO,TI,S,R) +#define G_float_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_sat_uchar(TO,TI,S,R) +#define G_float_sat_rte_uchar(TO,TI,S,R) +#define G_float_sat_rtn_uchar(TO,TI,S,R) +#define G_float_sat_rtp_uchar(TO,TI,S,R) +#define G_float_sat_rtz_uchar(TO,TI,S,R) +#define G_float_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_sat_short(TO,TI,S,R) +#define G_float_sat_rte_short(TO,TI,S,R) +#define G_float_sat_rtn_short(TO,TI,S,R) +#define G_float_sat_rtp_short(TO,TI,S,R) +#define G_float_sat_rtz_short(TO,TI,S,R) +#define G_float_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_sat_ushort(TO,TI,S,R) +#define G_float_sat_rte_ushort(TO,TI,S,R) +#define G_float_sat_rtn_ushort(TO,TI,S,R) +#define G_float_sat_rtp_ushort(TO,TI,S,R) +#define G_float_sat_rtz_ushort(TO,TI,S,R) +#define G_float_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_sat_int(TO,TI,S,R) +#define G_float_sat_rte_int(TO,TI,S,R) +#define G_float_sat_rtn_int(TO,TI,S,R) +#define G_float_sat_rtp_int(TO,TI,S,R) +#define G_float_sat_rtz_int(TO,TI,S,R) +#define G_float_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtn_int(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_rtp_int(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_rtz_int(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_sat_uint(TO,TI,S,R) +#define G_float_sat_rte_uint(TO,TI,S,R) +#define G_float_sat_rtn_uint(TO,TI,S,R) +#define G_float_sat_rtp_uint(TO,TI,S,R) +#define G_float_sat_rtz_uint(TO,TI,S,R) +#define G_float_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtn_uint(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_rtp_uint(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_rtz_uint(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_sat_long(TO,TI,S,R) +#define G_float_sat_rte_long(TO,TI,S,R) +#define G_float_sat_rtn_long(TO,TI,S,R) +#define G_float_sat_rtp_long(TO,TI,S,R) +#define G_float_sat_rtz_long(TO,TI,S,R) +#define G_float_rte_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtn_long(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_rtp_long(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_rtz_long(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_sat_ulong(TO,TI,S,R) +#define G_float_sat_rte_ulong(TO,TI,S,R) +#define G_float_sat_rtn_ulong(TO,TI,S,R) +#define G_float_sat_rtp_ulong(TO,TI,S,R) +#define G_float_sat_rtz_ulong(TO,TI,S,R) +#define G_float_rte_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtn_ulong(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_rtp_ulong(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_rtz_ulong(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_float(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_float_sat_float(TO,TI,S,R) +#define G_float_sat_rte_float(TO,TI,S,R) +#define G_float_sat_rtn_float(TO,TI,S,R) +#define G_float_sat_rtp_float(TO,TI,S,R) +#define G_float_sat_rtz_float(TO,TI,S,R) +#define G_float_rte_float(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_float_rtn_float(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_float_rtp_float(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_float_rtz_float(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_float_double(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_sat_double(TO,TI,S,R) +#define G_float_sat_rte_double(TO,TI,S,R) +#define G_float_sat_rtn_double(TO,TI,S,R) +#define G_float_sat_rtp_double(TO,TI,S,R) +#define G_float_sat_rtz_double(TO,TI,S,R) +#define G_float_rte_double(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtn_double(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_rtp_double(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_rtz_double(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_float_half(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_sat_half(TO,TI,S,R) +#define G_float_sat_rte_half(TO,TI,S,R) +#define G_float_sat_rtn_half(TO,TI,S,R) +#define G_float_sat_rtp_half(TO,TI,S,R) +#define G_float_sat_rtz_half(TO,TI,S,R) +#define G_float_rte_half(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtn_half(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtp_half(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_float_rtz_half(TO,TI,S,R) CAST(TO,TI,S,R) + +#define G_double_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_sat_char(TO,TI,S,R) +#define G_double_sat_rte_char(TO,TI,S,R) +#define G_double_sat_rtn_char(TO,TI,S,R) +#define G_double_sat_rtp_char(TO,TI,S,R) +#define G_double_sat_rtz_char(TO,TI,S,R) +#define G_double_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_sat_uchar(TO,TI,S,R) +#define G_double_sat_rte_uchar(TO,TI,S,R) +#define G_double_sat_rtn_uchar(TO,TI,S,R) +#define G_double_sat_rtp_uchar(TO,TI,S,R) +#define G_double_sat_rtz_uchar(TO,TI,S,R) +#define G_double_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_sat_short(TO,TI,S,R) +#define G_double_sat_rte_short(TO,TI,S,R) +#define G_double_sat_rtn_short(TO,TI,S,R) +#define G_double_sat_rtp_short(TO,TI,S,R) +#define G_double_sat_rtz_short(TO,TI,S,R) +#define G_double_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtn_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtp_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtz_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_sat_ushort(TO,TI,S,R) +#define G_double_sat_rte_ushort(TO,TI,S,R) +#define G_double_sat_rtn_ushort(TO,TI,S,R) +#define G_double_sat_rtp_ushort(TO,TI,S,R) +#define G_double_sat_rtz_ushort(TO,TI,S,R) +#define G_double_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtn_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtp_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtz_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_sat_int(TO,TI,S,R) +#define G_double_sat_rte_int(TO,TI,S,R) +#define G_double_sat_rtn_int(TO,TI,S,R) +#define G_double_sat_rtp_int(TO,TI,S,R) +#define G_double_sat_rtz_int(TO,TI,S,R) +#define G_double_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtn_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtp_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtz_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_sat_uint(TO,TI,S,R) +#define G_double_sat_rte_uint(TO,TI,S,R) +#define G_double_sat_rtn_uint(TO,TI,S,R) +#define G_double_sat_rtp_uint(TO,TI,S,R) +#define G_double_sat_rtz_uint(TO,TI,S,R) +#define G_double_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtn_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtp_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtz_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_sat_long(TO,TI,S,R) +#define G_double_sat_rte_long(TO,TI,S,R) +#define G_double_sat_rtn_long(TO,TI,S,R) +#define G_double_sat_rtp_long(TO,TI,S,R) +#define G_double_sat_rtz_long(TO,TI,S,R) +#define G_double_rte_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtn_long(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_double_rtp_long(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_double_rtz_long(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_double_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_sat_ulong(TO,TI,S,R) +#define G_double_sat_rte_ulong(TO,TI,S,R) +#define G_double_sat_rtn_ulong(TO,TI,S,R) +#define G_double_sat_rtp_ulong(TO,TI,S,R) +#define G_double_sat_rtz_ulong(TO,TI,S,R) +#define G_double_rte_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtn_ulong(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_double_rtp_ulong(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_double_rtz_ulong(TO,TI,S,R) EXPAND(TO,TI,S,R) +#define G_double_float(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_sat_float(TO,TI,S,R) +#define G_double_sat_rte_float(TO,TI,S,R) +#define G_double_sat_rtn_float(TO,TI,S,R) +#define G_double_sat_rtp_float(TO,TI,S,R) +#define G_double_sat_rtz_float(TO,TI,S,R) +#define G_double_rte_float(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtn_float(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtp_float(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtz_float(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_double(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_double_sat_double(TO,TI,S,R) +#define G_double_sat_rte_double(TO,TI,S,R) +#define G_double_sat_rtn_double(TO,TI,S,R) +#define G_double_sat_rtp_double(TO,TI,S,R) +#define G_double_sat_rtz_double(TO,TI,S,R) +#define G_double_rte_double(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_double_rtn_double(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_double_rtp_double(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_double_rtz_double(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_double_half(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_sat_half(TO,TI,S,R) +#define G_double_sat_rte_half(TO,TI,S,R) +#define G_double_sat_rtn_half(TO,TI,S,R) +#define G_double_sat_rtp_half(TO,TI,S,R) +#define G_double_sat_rtz_half(TO,TI,S,R) +#define G_double_rte_half(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtn_half(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtp_half(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_double_rtz_half(TO,TI,S,R) CAST(TO,TI,S,R) + +#define G_half_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_sat_char(TO,TI,S,R) +#define G_half_sat_rte_char(TO,TI,S,R) +#define G_half_sat_rtn_char(TO,TI,S,R) +#define G_half_sat_rtp_char(TO,TI,S,R) +#define G_half_sat_rtz_char(TO,TI,S,R) +#define G_half_rte_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtn_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtp_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtz_char(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_sat_uchar(TO,TI,S,R) +#define G_half_sat_rte_uchar(TO,TI,S,R) +#define G_half_sat_rtn_uchar(TO,TI,S,R) +#define G_half_sat_rtp_uchar(TO,TI,S,R) +#define G_half_sat_rtz_uchar(TO,TI,S,R) +#define G_half_rte_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtn_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtp_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtz_uchar(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_sat_short(TO,TI,S,R) +#define G_half_sat_rte_short(TO,TI,S,R) +#define G_half_sat_rtn_short(TO,TI,S,R) +#define G_half_sat_rtp_short(TO,TI,S,R) +#define G_half_sat_rtz_short(TO,TI,S,R) +#define G_half_rte_short(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtn_short(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtp_short(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtz_short(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_sat_ushort(TO,TI,S,R) +#define G_half_sat_rte_ushort(TO,TI,S,R) +#define G_half_sat_rtn_ushort(TO,TI,S,R) +#define G_half_sat_rtp_ushort(TO,TI,S,R) +#define G_half_sat_rtz_ushort(TO,TI,S,R) +#define G_half_rte_ushort(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtn_ushort(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtp_ushort(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtz_ushort(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_sat_int(TO,TI,S,R) +#define G_half_sat_rte_int(TO,TI,S,R) +#define G_half_sat_rtn_int(TO,TI,S,R) +#define G_half_sat_rtp_int(TO,TI,S,R) +#define G_half_sat_rtz_int(TO,TI,S,R) +#define G_half_rte_int(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtn_int(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtp_int(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtz_int(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_sat_uint(TO,TI,S,R) +#define G_half_sat_rte_uint(TO,TI,S,R) +#define G_half_sat_rtn_uint(TO,TI,S,R) +#define G_half_sat_rtp_uint(TO,TI,S,R) +#define G_half_sat_rtz_uint(TO,TI,S,R) +#define G_half_rte_uint(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtn_uint(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtp_uint(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtz_uint(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_sat_long(TO,TI,S,R) +#define G_half_sat_rte_long(TO,TI,S,R) +#define G_half_sat_rtn_long(TO,TI,S,R) +#define G_half_sat_rtp_long(TO,TI,S,R) +#define G_half_sat_rtz_long(TO,TI,S,R) +#define G_half_rte_long(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtn_long(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtp_long(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtz_long(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_sat_ulong(TO,TI,S,R) +#define G_half_sat_rte_ulong(TO,TI,S,R) +#define G_half_sat_rtn_ulong(TO,TI,S,R) +#define G_half_sat_rtp_ulong(TO,TI,S,R) +#define G_half_sat_rtz_ulong(TO,TI,S,R) +#define G_half_rte_ulong(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtn_ulong(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtp_ulong(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtz_ulong(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_float(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_sat_float(TO,TI,S,R) +#define G_half_sat_rte_float(TO,TI,S,R) +#define G_half_sat_rtn_float(TO,TI,S,R) +#define G_half_sat_rtp_float(TO,TI,S,R) +#define G_half_sat_rtz_float(TO,TI,S,R) +#define G_half_rte_float(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtn_float(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtp_float(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtz_float(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_double(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_sat_double(TO,TI,S,R) +#define G_half_sat_rte_double(TO,TI,S,R) +#define G_half_sat_rtn_double(TO,TI,S,R) +#define G_half_sat_rtp_double(TO,TI,S,R) +#define G_half_sat_rtz_double(TO,TI,S,R) +#define G_half_rte_double(TO,TI,S,R) CAST(TO,TI,S,R) +#define G_half_rtn_double(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtp_double(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_rtz_double(TO,TI,S,R) EXPAND(TO,TI,R,S) +#define G_half_half(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_half_sat_half(TO,TI,S,R) +#define G_half_sat_rte_half(TO,TI,S,R) +#define G_half_sat_rtn_half(TO,TI,S,R) +#define G_half_sat_rtp_half(TO,TI,S,R) +#define G_half_sat_rtz_half(TO,TI,S,R) +#define G_half_rte_half(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_half_rtn_half(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_half_rtp_half(TO,TI,S,R) NOP(TO,TI,S,R) +#define G_half_rtz_half(TO,TI,S,R) NOP(TO,TI,S,R) + +#define GEN2(TO,TI) \ + C(G_,C(TO,C(_,TI)))(TO,TI,,) \ + C(G_,C(TO,C(_sat_,TI)))(TO,TI,_sat,) \ + C(G_,C(TO,C(_sat_rte_,TI)))(TO,TI,_sat,_rte) \ + C(G_,C(TO,C(_sat_rtn_,TI)))(TO,TI,_sat,_rtn) \ + C(G_,C(TO,C(_sat_rtp_,TI)))(TO,TI,_sat,_rtp) \ + C(G_,C(TO,C(_sat_rtz_,TI)))(TO,TI,_sat,_rtz) \ + C(G_,C(TO,C(_rte_,TI)))(TO,TI,,_rte) \ + C(G_,C(TO,C(_rtn_,TI)))(TO,TI,,_rtn) \ + C(G_,C(TO,C(_rtp_,TI)))(TO,TI,,_rtp) \ + C(G_,C(TO,C(_rtz_,TI)))(TO,TI,,_rtz) + +#define GEN(T) \ + GEN2(T,char) \ + GEN2(T,uchar) \ + GEN2(T,short) \ + GEN2(T,ushort) \ + GEN2(T,int) \ + GEN2(T,uint) \ + GEN2(T,long) \ + GEN2(T,ulong) \ + GEN2(T,float) \ + GEN2(T,double) \ + GEN2(T,half) + +GEN(char) +GEN(uchar) +GEN(short) +GEN(ushort) +GEN(int) +GEN(uint) +GEN(long) +GEN(ulong) +GEN(float) +GEN(double) +GEN(half) + +ATTR float +convert_float_rtn(int i) +{ + return __ocml_cvtrtn_f32_s32(i); +} + +ATTR float +convert_float_rtp(int i) +{ + return __ocml_cvtrtp_f32_s32(i); +} + +ATTR float +convert_float_rtz(int i) +{ + return __ocml_cvtrtz_f32_s32(i); +} + +ATTR float +convert_float_rtn(uint i) +{ + return __ocml_cvtrtn_f32_u32(i); +} + +ATTR float +convert_float_rtp(uint i) +{ + return __ocml_cvtrtp_f32_u32(i); +} + +ATTR float +convert_float_rtz(uint i) +{ + return __ocml_cvtrtz_f32_u32(i); +} + +ATTR float +convert_float_rtn(long l) +{ + return __ocml_cvtrtn_f32_s64(l); +} + +ATTR float +convert_float_rtp(long l) +{ + return __ocml_cvtrtp_f32_s64(l); +} + +ATTR float +convert_float_rtz(long l) +{ + return __ocml_cvtrtz_f32_s64(l); +} + +ATTR float +convert_float_rtn(ulong l) +{ + return __ocml_cvtrtn_f32_u64(l); +} + +ATTR float +convert_float_rtp(ulong l) +{ + return __ocml_cvtrtp_f32_u64(l); +} + +ATTR float +convert_float_rtz(ulong l) +{ + return __ocml_cvtrtz_f32_u64(l); +} + +ATTR float +convert_float_rtn(double a) +{ + return __ocml_cvtrtn_f32_f64(a); +} + +ATTR float +convert_float_rtp(double a) +{ + return __ocml_cvtrtp_f32_f64(a); +} + +ATTR float +convert_float_rtz(double a) +{ + return __ocml_cvtrtz_f32_f64(a); +} + +ATTR double +convert_double_rtn(long l) +{ + return __ocml_cvtrtn_f64_s64(l); +} + +ATTR double +convert_double_rtp(long l) +{ + return __ocml_cvtrtp_f64_s64(l); +} + +ATTR double +convert_double_rtz(long l) +{ + return __ocml_cvtrtz_f64_s64(l); +} + +ATTR double +convert_double_rtn(ulong l) +{ + return __ocml_cvtrtn_f64_u64(l); +} + +ATTR double +convert_double_rtp(ulong l) +{ + return __ocml_cvtrtp_f64_u64(l); +} + +ATTR double +convert_double_rtz(ulong l) +{ + return __ocml_cvtrtz_f64_u64(l); +} + +ATTR half +convert_half_rtn(short s) +{ + return __ocml_cvtrtn_f16_f32((float)s); +} + +ATTR half +convert_half_rtp(short s) +{ + return __ocml_cvtrtp_f16_f32((float)s); +} + +ATTR half +convert_half_rtz(short s) +{ + return __ocml_cvtrtz_f16_f32((float)s); +} + +IATTR static half +cvt1f2_zu2(ushort u) +{ + return __ocml_cvtrtz_f16_f32((float)u); +} +AATTR("cvt1f2_zu2") half convert_half_rtn(ushort); +AATTR("cvt1f2_zu2") half convert_half_rtz(ushort); + +ATTR half +convert_half_rtp(ushort u) +{ + return __ocml_cvtrtp_f16_f32((float)u); +} + +ATTR half +convert_half_rtn(int i) +{ + i = clamp(i, -HALFBND, HALFBND); + return __ocml_cvtrtn_f16_f32((float)i); +} + +ATTR half +convert_half_rtp(int i) +{ + i = clamp(i, -HALFBND, HALFBND); + return __ocml_cvtrtp_f16_f32((float)i); +} + +ATTR half +convert_half_rtz(int i) +{ + i = clamp(i, -HALFBND, HALFBND); + return __ocml_cvtrtz_f16_f32((float)i); +} + +IATTR static half +cvt1f2_zu4(uint u) +{ + u = min(u, (uint)USHRT_MAX); + return __ocml_cvtrtz_f16_f32((float)u); +} +AATTR("cvt1f2_zu4") half convert_half_rtn(uint); +AATTR("cvt1f2_zu4") half convert_half_rtz(uint); + +ATTR half +convert_half_rtp(uint u) +{ + u = min(u, (uint)USHRT_MAX); + return __ocml_cvtrtp_f16_f32((float)u); +} + +ATTR half +convert_half_rtn(long l) +{ + int i = (int)clamp(l, -(long)HALFBND, (long)HALFBND); + return __ocml_cvtrtn_f16_f32((float)i); +} + +ATTR half +convert_half_rtp(long l) +{ + int i = (int)clamp(l, -(long)HALFBND, (long)HALFBND); + return __ocml_cvtrtp_f16_f32((float)i); +} + +ATTR half +convert_half_rtz(long l) +{ + int i = (int)clamp(l, -(long)HALFBND, (long)HALFBND); + return __ocml_cvtrtz_f16_f32((float)i); +} + +IATTR static half +cvt1f2_zu8(ulong ul) +{ + uint u = (uint)min(ul, (ulong)USHRT_MAX); + return __ocml_cvtrtz_f16_f32((float)u); +} +AATTR("cvt1f2_zu8") half convert_half_rtn(ulong); +AATTR("cvt1f2_zu8") half convert_half_rtz(ulong); + +ATTR half +convert_half_rtp(ulong ul) +{ + uint u = (uint)min(ul, (ulong)USHRT_MAX); + return __ocml_cvtrtp_f16_f32((float)u); +} + +ATTR half +convert_half_rtp(float a) +{ + return __ocml_cvtrtp_f16_f32(a); +} + +ATTR half +convert_half_rtn(float a) +{ + return __ocml_cvtrtn_f16_f32(a); +} + +ATTR half +convert_half_rtz(float a) +{ + return __ocml_cvtrtz_f16_f32(a); +} + +ATTR half +convert_half_rtp(double a) +{ + return __ocml_cvtrtp_f16_f64(a); +} + +ATTR half +convert_half_rtn(double a) +{ + return __ocml_cvtrtn_f16_f64(a); +} + +ATTR half +convert_half_rtz(double a) +{ + return __ocml_cvtrtz_f16_f64(a); +} diff --git a/amd/device-libs/opencl/src/misc/shuffle.cl b/amd/device-libs/opencl/src/misc/shuffle.cl new file mode 100644 index 0000000000000..1735b14a255ee --- /dev/null +++ b/amd/device-libs/opencl/src/misc/shuffle.cl @@ -0,0 +1,109 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _S(X) #X +#define S(X) _S(X) + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define char_utype uchar +#define short_utype ushort +#define int_utype uint +#define long_utype ulong +#define float_utype uint +#define double_utype ulong +#define half_utype ushort + +#define ATTR __attribute__((overloadable, const)) +#define IATTR __attribute__((const)) +#define AATTR(A) __attribute__((overloadable, const, alias(A))) + +#define LIST2 t[m.s0], t[m.s1] +#define LIST4 LIST2, t[m.s2], t[m.s3] +#define LIST8 LIST4, t[m.s4], t[m.s5], t[m.s6], t[m.s7] +#define LIST16 LIST8, t[m.s8], t[m.s9], t[m.sa], t[m.sb], t[m.sc], t[m.sd], t[m.se], t[m.sf] + +#define GENIMN(M,N,T) \ +IATTR T##N \ +sh_##N##T##M(T##M x, C(T##_utype,N) m) \ +{ \ + __attribute__((aligned(sizeof(T##M)))) T t[M]; \ + *(__private T##M *)t = x; \ + m &= (C(T##_utype,N))(M-1); \ + return (T##N) ( LIST##N ); \ +} \ +extern AATTR(S(sh_##N##T##M)) T##N shuffle(T##M, C(T##_utype,N)); \ +extern AATTR(S(sh_##N##T##M)) u##T##N shuffle(u##T##M, C(T##_utype,N)); \ + \ +IATTR T##N \ +sh2_##N##T##M(T##M x, T##M y, C(T##_utype,N) m) \ +{ \ + __attribute__((aligned(sizeof(T##M)))) T t[2*M]; \ + *(__private T##M *)t = x; \ + *(__private T##M *)(t + M) = y; \ + m &= (C(T##_utype,N))(2*M-1); \ + return (T##N) ( LIST##N ); \ +} \ +extern AATTR(S(sh2_##N##T##M)) T##N shuffle2(T##M, T##M, C(T##_utype,N)); \ +extern AATTR(S(sh2_##N##T##M)) u##T##N shuffle2(u##T##M, u##T##M, C(T##_utype,N)); + +#define GENIN(N,T) \ + GENIMN(16,N,T) \ + GENIMN(8,N,T) \ + GENIMN(4,N,T) \ + GENIMN(2,N,T) + +#define GENI(T) \ + GENIN(16,T) \ + GENIN(8,T) \ + GENIN(4,T) \ + GENIN(2,T) + +GENI(char) +GENI(short) +GENI(int) +GENI(long) + +#define GENFMN(M,N,T) \ +ATTR T##N \ +shuffle(T##M x, C(T##_utype,N) m) \ +{ \ + __attribute__((aligned(sizeof(T##M)))) T t[M]; \ + *(__private T##M *)t = x; \ + m &= (C(T##_utype,N))(M-1); \ + return (T##N) ( LIST##N ); \ +} \ + \ +ATTR T##N \ +shuffle2(T##M x, T##M y, C(T##_utype,N) m) \ +{ \ + __attribute__((aligned(sizeof(T##M)))) T t[2*M]; \ + *(__private T##M *)t = x; \ + *(__private T##M *)(t + M) = y; \ + m &= (C(T##_utype,N))(2*M-1); \ + return (T##N) ( LIST##N ); \ +} + +#define GENFN(N,T) \ + GENFMN(16,N,T) \ + GENFMN(8,N,T) \ + GENFMN(4,N,T) \ + GENFMN(2,N,T) + +#define GENF(T) \ + GENFN(16,T) \ + GENFN(8,T) \ + GENFN(4,T) \ + GENFN(2,T) + +GENF(float) +GENF(double) +GENF(half) + diff --git a/amd/device-libs/opencl/src/misc/workitem.cl b/amd/device-libs/opencl/src/misc/workitem.cl new file mode 100644 index 0000000000000..66f3d7435f83c --- /dev/null +++ b/amd/device-libs/opencl/src/misc/workitem.cl @@ -0,0 +1,77 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#define ATTR __attribute__((overloadable, const)) + +ATTR size_t +get_global_offset(uint dim) +{ + return __ockl_get_global_offset(dim); +} + +ATTR size_t +get_global_id(uint dim) +{ + return __ockl_get_global_id(dim); +} + +ATTR size_t +get_local_id(uint dim) +{ + return __ockl_get_local_id(dim); +} + +ATTR size_t +get_group_id(uint dim) +{ + return __ockl_get_group_id(dim); +} + +ATTR size_t +get_global_size(uint dim) +{ + return __ockl_get_global_size(dim); +} + +ATTR size_t +get_local_size(uint dim) +{ + return __ockl_get_local_size(dim); +} + +ATTR size_t +get_num_groups(uint dim) +{ + return __ockl_get_num_groups(dim); +} + +ATTR uint +get_work_dim(void) +{ + return __ockl_get_work_dim(); +} + +ATTR size_t +get_enqueued_local_size(uint dim) +{ + return __ockl_get_enqueued_local_size(dim); +} + +ATTR size_t +get_global_linear_id(void) +{ + return __ockl_get_global_linear_id(); +} + +ATTR size_t +get_local_linear_id(void) +{ + return __ockl_get_local_linear_id(); +} + diff --git a/amd/device-libs/opencl/src/pipes/commitp.cl b/amd/device-libs/opencl/src/pipes/commitp.cl new file mode 100644 index 0000000000000..51528cb8d25fc --- /dev/null +++ b/amd/device-libs/opencl/src/pipes/commitp.cl @@ -0,0 +1,93 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "pipes.h" + +#define ATTR __attribute__((always_inline)) + +#define COMMIT_READ_PIPE_SIZE(SIZE, STYPE) \ +ATTR void \ +__commit_read_pipe_##SIZE(__global struct pipeimp* p, size_t rid) \ +{ \ +} + +// DO_PIPE_SIZE(COMMIT_READ_PIPE_SIZE) + +ATTR void +__commit_read_pipe(__global struct pipeimp* p, size_t rid, uint size, uint align) +{ +} + +#define COMMIT_WRITE_PIPE_SIZE(SIZE, STYPE) \ +ATTR void \ +__commit_write_pipe_##SIZE(__global struct pipeimp* p, size_t rid) \ +{ \ +} + +// DO_PIPE_SIZE(COMMIT_WRITE_PIPE_SIZE) + +ATTR void +__commit_write_pipe(__global struct pipeimp* p, size_t rid, uint size, uint align) +{ +} + +// Work group functions + +#define WORK_GROUP_COMMIT_READ_PIPE_SIZE(SIZE, STYPE) \ +ATTR void \ +__work_group_commit_read_pipe_##SIZE(__global struct pipeimp* p, size_t rid) \ +{ \ +} + +// DO_PIPE_SIZE(WORK_GROUP_COMMIT_READ_PIPE_SIZE) + +ATTR void +__work_group_commit_read_pipe(__global struct pipeimp* p, size_t rid, uint size, uint align) +{ +} + +#define WORK_GROUP_COMMIT_WRITE_PIPE_SIZE(SIZE, STYPE) \ +ATTR void \ +__work_group_commit_write_pipe_##SIZE(__global struct pipeimp* p, size_t rid) \ +{ \ +} + +// DO_PIPE_SIZE(WORK_GROUP_COMMIT_WRITE_PIPE_SIZE) + +ATTR void +__work_group_commit_write_pipe(__global struct pipeimp* p, size_t rid, uint size, uint align) +{ +} + +// sub group functions + +#define SUB_GROUP_COMMIT_READ_PIPE_SIZE(SIZE, STYPE) \ +ATTR void \ +__sub_group_commit_read_pipe_##SIZE(__global struct pipeimp* p, size_t rid) \ +{ \ +} + +// DO_PIPE_SIZE(SUB_GROUP_COMMIT_READ_PIPE_SIZE) + +ATTR void +__sub_group_commit_read_pipe(__global struct pipeimp* p, size_t rid, uint size, uint align) +{ +} + +#define SUB_GROUP_COMMIT_WRITE_PIPE_SIZE(SIZE, STYPE) \ +ATTR void \ +__sub_group_commit_write_pipe_##SIZE(__global struct pipeimp* p, size_t rid) \ +{ \ +} + +// DO_PIPE_SIZE(SUB_GROUP_COMMIT_WRITE_PIPE_SIZE) + +ATTR void +__sub_group_commit_write_pipe(__global struct pipeimp* p, size_t rid, uint size, uint align) +{ +} + diff --git a/amd/device-libs/opencl/src/pipes/getp.cl b/amd/device-libs/opencl/src/pipes/getp.cl new file mode 100644 index 0000000000000..a412637a9d27f --- /dev/null +++ b/amd/device-libs/opencl/src/pipes/getp.cl @@ -0,0 +1,43 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "pipes.h" + +#define ATTR __attribute__((always_inline, pure)) + +static ATTR uint +num_packets(__global struct pipeimp* p) +{ + size_t ri = __opencl_atomic_load(&p->read_idx, memory_order_relaxed, memory_scope_device); + size_t wi = __opencl_atomic_load(&p->write_idx, memory_order_relaxed, memory_scope_device); + return (uint)(wi - ri); +} + +ATTR uint +__get_pipe_num_packets_ro(__global struct pipeimp* p, uint size, uint align) +{ + return num_packets(p); +} + +ATTR uint +__get_pipe_num_packets_wo(__global struct pipeimp* p, uint size, uint align) +{ + return num_packets(p); +} + +ATTR uint +__get_pipe_max_packets_ro(__global struct pipeimp* p, uint size, uint align) +{ + return (uint)p->end_idx; +} + +ATTR uint +__get_pipe_max_packets_wo(__global struct pipeimp* p, uint size, uint align) +{ + return (uint)p->end_idx; +} + diff --git a/amd/device-libs/opencl/src/pipes/pipes.h b/amd/device-libs/opencl/src/pipes/pipes.h new file mode 100644 index 0000000000000..7d3f9d1bff05e --- /dev/null +++ b/amd/device-libs/opencl/src/pipes/pipes.h @@ -0,0 +1,111 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#pragma OPENCL EXTENSION cl_khr_int64_base_atomics : enable +#pragma OPENCL EXTENSION cl_khr_int64_extended_atomics : enable + +extern size_t __amd_wresvn(volatile __global atomic_size_t *pidx, size_t lim, size_t n); + +#define DO_PIPE_SIZE(F) \ +F(1,uchar) \ +F(2,ushort) \ +F(4,uint) \ +F(8,ulong) \ +F(16,ulong2) \ +F(32,ulong4) \ +F(64,ulong8) \ +F(128,ulong16) + +// Assume that ptr is aligned by at least align bytes. In contrast to +// __builtin_assume_aligned, this allows a non-constant alignment operand. +#define ASSUME_ALIGNED(ptr, align) \ + __builtin_assume(__builtin_is_aligned(ptr, align)) + +struct pipeimp { + atomic_size_t read_idx; + atomic_size_t write_idx; + size_t end_idx; + uchar pad[128 - 3*sizeof(size_t)]; + uchar packets[1]; +}; + +static __attribute__((always_inline)) size_t +reserve(volatile __global atomic_size_t *pi, size_t lim, size_t n) +{ + size_t i = __opencl_atomic_load(pi, memory_order_relaxed, memory_scope_device); + + for (;;) { + if (i + n > lim) + return ~(size_t)0; + + if (__opencl_atomic_compare_exchange_strong(pi, &i, i + n, memory_order_relaxed, memory_order_relaxed, memory_scope_device)) + break; + } + + return i; +} + +static inline size_t +wave_reserve_1(volatile __global atomic_size_t *pi, size_t lim) +{ + ulong n = __builtin_popcountl(__builtin_amdgcn_read_exec()); + uint l = __builtin_amdgcn_mbcnt_hi(__builtin_amdgcn_read_exec_hi(), + __builtin_amdgcn_mbcnt_lo(__builtin_amdgcn_read_exec_lo(), 0u)); + size_t i = 0; + + if (l == 0) { + i = __opencl_atomic_load(pi, memory_order_relaxed, memory_scope_device); + + for (;;) { + if (i + n > lim) { + i = ~(size_t)0; + break; + } + + if (__opencl_atomic_compare_exchange_strong(pi, &i, i + n, memory_order_relaxed, memory_order_relaxed, memory_scope_device)) + break; + } + } + + __builtin_amdgcn_wave_barrier(); + + // Broadcast the result; the ctz tells us which lane has active lane id 0 + uint k = (uint)OCKL_MANGLE_U64(ctz)(__builtin_amdgcn_read_exec()); + i = ((size_t)__builtin_amdgcn_readlane((uint)(i >> 32), k) << 32) | + (size_t)__builtin_amdgcn_readlane((uint)i, k); + + __builtin_amdgcn_wave_barrier(); + + if (i != ~(size_t)0) + i += l; + else { + // The entire group didn't fit, have to handle one by one + i = reserve(pi, lim, (size_t)1); + } + + return i; +} + +static inline size_t +wrap(size_t i, size_t n) +{ + // Assume end_i < 2^32 + size_t ret; + if (as_uint2(i).y == 0U) { + uint j = (uint)i; + uint m = (uint)n; + if (j < m) + ret = i; + else + ret = (ulong)(j % m); + } else + ret = i % n; + return ret; +} + diff --git a/amd/device-libs/opencl/src/pipes/readp.cl b/amd/device-libs/opencl/src/pipes/readp.cl new file mode 100644 index 0000000000000..759b53bac12ad --- /dev/null +++ b/amd/device-libs/opencl/src/pipes/readp.cl @@ -0,0 +1,81 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "pipes.h" + +#define ATTR __attribute__((always_inline)) + +#define READ_PIPE_SIZE(SIZE, STYPE) \ +ATTR int \ +__read_pipe_2_##SIZE(__global struct pipeimp* p, STYPE* ptr) \ +{ \ + size_t wi = __opencl_atomic_load(&p->write_idx, memory_order_relaxed, memory_scope_device); \ + size_t ri = wave_reserve_1(&p->read_idx, wi); \ + if (ri == ~(size_t)0) \ + return -1; \ + \ + size_t pi = wrap(ri, p->end_idx); \ + *ptr = ((__global STYPE *)p->packets)[pi]; \ + \ + if (ri == wi-1) { \ + __opencl_atomic_store(&p->write_idx, 0, memory_order_relaxed, memory_scope_device); \ + __opencl_atomic_store(&p->read_idx, 0, memory_order_relaxed, memory_scope_device); \ + }\ +\ + return 0; \ +} + +DO_PIPE_SIZE(READ_PIPE_SIZE) + +ATTR int +__read_pipe_2(__global struct pipeimp* p, void* ptr, uint size, uint align) +{ + size_t wi = __opencl_atomic_load(&p->write_idx, memory_order_relaxed, memory_scope_device); + size_t ri = wave_reserve_1(&p->read_idx, wi); + if (ri == ~(size_t)0) + return -1; + + size_t pi = wrap(ri, p->end_idx); + void *pipe_ptr = p->packets + pi * size; + ASSUME_ALIGNED(ptr, align); + ASSUME_ALIGNED(pipe_ptr, align); + __builtin_memcpy(ptr, pipe_ptr, size); + + if (ri == wi-1) { + __opencl_atomic_store(&p->write_idx, 0, memory_order_relaxed, memory_scope_device); + __opencl_atomic_store(&p->read_idx, 0, memory_order_relaxed, memory_scope_device); + } + + return 0; +} + +#define READ_PIPE_RESERVED_SIZE(SIZE, STYPE) \ +ATTR int \ +__read_pipe_4_##SIZE(__global struct pipeimp* p, reserve_id_t rid, uint i, STYPE* ptr) \ +{ \ + size_t rin = __builtin_astype(rid, size_t) + i; \ + size_t pi = wrap(rin, p->end_idx); \ + *ptr = ((__global STYPE *)p->packets)[pi]; \ + \ + return 0; \ +} + +DO_PIPE_SIZE(READ_PIPE_RESERVED_SIZE) + +ATTR int +__read_pipe_4(__global struct pipeimp* p, reserve_id_t rid, uint i, void *ptr, uint size, uint align) +{ + size_t rin = __builtin_astype(rid, size_t) + i; \ + size_t pi = wrap(rin, p->end_idx); + void *pipe_ptr = p->packets + pi * size; + ASSUME_ALIGNED(ptr, align); + ASSUME_ALIGNED(pipe_ptr, align); + __builtin_memcpy(ptr, pipe_ptr, size); + + return 0; +} + diff --git a/amd/device-libs/opencl/src/pipes/reservep.cl b/amd/device-libs/opencl/src/pipes/reservep.cl new file mode 100644 index 0000000000000..91dbb3443e9e4 --- /dev/null +++ b/amd/device-libs/opencl/src/pipes/reservep.cl @@ -0,0 +1,220 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#include "pipes.h" +#include "wgscratch.h" + +#define ATTR __attribute__((always_inline)) + +#define RESERVE_READ_PIPE_SIZE(SIZE, STYPE) \ +ATTR reserve_id_t \ +__reserve_read_pipe_##SIZE(__global struct pipeimp *p, uint num_packets) \ +{ \ + size_t wi = __opencl_atomic_load(&p->write_idx, memory_order_relaxed, memory_scope_device); \ + size_t rid = __amd_wresvn(&p->read_idx, wi, num_packets); \ + \ + if (rid + num_packets == wi) { \ + __opencl_atomic_store(&p->write_idx, 0, memory_order_relaxed, memory_scope_device); \ + __opencl_atomic_store(&p->read_idx, 0, memory_order_relaxed, memory_scope_device); \ + } \ + \ + return __builtin_astype(rid, reserve_id_t); \ +} + +// DO_PIPE_SIZE(RESERVE_READ_PIPE_SIZE) + +ATTR reserve_id_t +__reserve_read_pipe(__global struct pipeimp *p, uint num_packets, uint size, uint align) +{ + size_t wi = __opencl_atomic_load(&p->write_idx, memory_order_relaxed, memory_scope_device); + size_t rid = __amd_wresvn(&p->read_idx, wi, num_packets); + + if (rid + num_packets == wi) { + __opencl_atomic_store(&p->write_idx, 0, memory_order_relaxed, memory_scope_device); + __opencl_atomic_store(&p->read_idx, 0, memory_order_relaxed, memory_scope_device); + } + + return __builtin_astype(rid, reserve_id_t); +} + +#define RESERVE_WRITE_PIPE_SIZE(SIZE, STYPE) \ +ATTR reserve_id_t \ +__reserve_write_pipe_##SIZE(__global struct pipeimp *p, uint num_packets) \ +{ \ + size_t ri = __opencl_atomic_load(&p->read_idx, memory_order_relaxed, memory_scope_device); \ + size_t ei = p->end_idx; \ + return __amd_wresvn(&p->write_idx, ri + ei, num_packets); \ +} + +// DO_PIPE_SIZE(RESERVE_WRITE_PIPE_SIZE) + +ATTR reserve_id_t +__reserve_write_pipe(__global struct pipeimp *p, uint num_packets, uint size, uint align) +{ + size_t ri = __opencl_atomic_load(&p->read_idx, memory_order_relaxed, memory_scope_device); + size_t ei = p->end_idx; + size_t rid = __amd_wresvn(&p->write_idx, ri + ei, num_packets); + return __builtin_astype(rid, reserve_id_t); +} + +// Work group functions + +#define WORK_GROUP_RESERVE_READ_PIPE_SIZE(SIZE, STYPE) \ +ATTR reserve_id_t \ +__work_group_reserve_read_pipe_##SIZE(__global struct pipeimp *p, uint num_packets) \ +{ \ + __local size_t *t = (__local size_t *)__get_scratch_lds(); \ + \ + if ((int)get_local_linear_id() == 0) { \ + size_t wi = __opencl_atomic_load(&p->write_idx, memory_order_relaxed, memory_scope_device); \ + size_t rid = reserve(&p->read_idx, wi, num_packets); \ + \ + if (rid + num_packets == wi) { \ + __opencl_atomic_store(&p->write_idx, 0, memory_order_relaxed, memory_scope_device); \ + __opencl_atomic_store(&p->read_idx, 0, memory_order_relaxed, memory_scope_device); \ + } \ + \ + *t = rid; \ + } \ + \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + \ + return __builtin_astype(*t, reserve_id_t); \ +} + +// DO_PIPE_SIZE(WORK_GROUP_RESERVE_READ_PIPE_SIZE) + +ATTR reserve_id_t +__work_group_reserve_read_pipe(__global struct pipeimp *p, uint num_packets, uint size, uint align) +{ + __local size_t *t = (__local size_t *)__get_scratch_lds(); + + if ((int)get_local_linear_id() == 0) { + size_t wi = __opencl_atomic_load(&p->write_idx, memory_order_relaxed, memory_scope_device); + size_t rid = reserve(&p->read_idx, wi, num_packets); + + if (rid + num_packets == wi) { + __opencl_atomic_store(&p->write_idx, 0, memory_order_relaxed, memory_scope_device); + __opencl_atomic_store(&p->read_idx, 0, memory_order_relaxed, memory_scope_device); + } + + *t = rid; + } + + work_group_barrier(CLK_LOCAL_MEM_FENCE); + + return __builtin_astype(*t, reserve_id_t); +} + +#define WORK_GROUP_RESERVE_WRITE_PIPE_SIZE(SIZE, STYPE) \ +ATTR reserve_id_t \ +__work_group_reserve_write_pipe_##SIZE(__global struct pipeimp *p, uint num_packets) \ +{ \ + __local size_t *t = (__local size_t *)__get_scratch_lds(); \ + \ + if ((int)get_local_linear_id() == 0) { \ + size_t ri = __opencl_atomic_load(&p->read_idx, memory_order_relaxed, memory_scope_device); \ + size_t ei = p->end_idx; \ + *t = reserve(&p->write_idx, ri + ei, num_packets); \ + } \ + \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + \ + return __builtin_astype(*t, reserve_id_t); \ +} + +// DO_PIPE_SIZE(WORK_GROUP_RESERVE_WRITE_PIPE_SIZE) + +ATTR reserve_id_t +__work_group_reserve_write_pipe(__global struct pipeimp *p, uint num_packets, uint size, uint align) +{ + __local size_t *t = (__local size_t *)__get_scratch_lds(); + + if ((int)get_local_linear_id() == 0) { + size_t ri = __opencl_atomic_load(&p->read_idx, memory_order_relaxed, memory_scope_device); + size_t ei = p->end_idx; + *t = reserve(&p->write_idx, ri + ei, num_packets); + } + + work_group_barrier(CLK_LOCAL_MEM_FENCE); + + return __builtin_astype(*t, reserve_id_t); +} + +// sub group functions + +#define SUB_GROUP_RESERVE_READ_PIPE_SIZE(SIZE, STYPE) \ +ATTR reserve_id_t \ +__sub_group_reserve_read_pipe_##SIZE(__global struct pipeimp *p, uint num_packets) \ +{ \ + size_t rid = ~(size_t)0; \ + \ + if (get_sub_group_local_id() == 0) { \ + size_t wi = __opencl_atomic_load(&p->write_idx, memory_order_relaxed, memory_scope_device); \ + rid = reserve(&p->read_idx, wi, num_packets); \ + \ + if (rid + num_packets == wi) { \ + __opencl_atomic_store(&p->write_idx, 0, memory_order_relaxed, memory_scope_device); \ + __opencl_atomic_store(&p->read_idx, 0, memory_order_relaxed, memory_scope_device); \ + } \ + } \ + \ + return __builtin_astype(sub_group_broadcast(rid, 0), reserve_id_t); \ +} + +// DO_PIPE_SIZE(SUB_GROUP_RESERVE_READ_PIPE_SIZE) + +ATTR reserve_id_t +__sub_group_reserve_read_pipe(__global struct pipeimp *p, uint num_packets, uint size, uint align) +{ + size_t rid = ~(size_t)0; + + if (get_sub_group_local_id() == 0) { + size_t wi = __opencl_atomic_load(&p->write_idx, memory_order_relaxed, memory_scope_device); + rid = reserve(&p->read_idx, wi, num_packets); + + if (rid + num_packets == wi) { + __opencl_atomic_store(&p->write_idx, 0, memory_order_relaxed, memory_scope_device); + __opencl_atomic_store(&p->read_idx, 0, memory_order_relaxed, memory_scope_device); + } + } + + return __builtin_astype(sub_group_broadcast(rid, 0), reserve_id_t); +} + +#define SUB_GROUP_RESERVE_WRITE_PIPE_SIZE(SIZE, STYPE) \ +ATTR reserve_id_t \ +__sub_group_reserve_write_pipe_##SIZE(__global struct pipeimp *p, uint num_packets) \ +{ \ + size_t rid = ~(size_t)0; \ + \ + if (get_sub_group_local_id() == 0) { \ + size_t ri = __opencl_atomic_load(&p->read_idx, memory_order_relaxed, memory_scope_device); \ + size_t ei = p->end_idx; \ + rid = reserve(&p->write_idx, ri + ei, num_packets); \ + } \ + \ + return __builtin_astype(sub_group_broadcast(rid, 0), reserve_id_t); \ +} + +// DO_PIPE_SIZE(SUB_GROUP_RESERVE_WRITE_PIPE_SIZE) + +ATTR reserve_id_t +__sub_group_reserve_write_pipe(__global struct pipeimp *p, uint num_packets, uint size, uint align) +{ + size_t rid = ~(size_t)0; + + if (get_sub_group_local_id() == 0) { + size_t ri = __opencl_atomic_load(&p->read_idx, memory_order_relaxed, memory_scope_device); + size_t ei = p->end_idx; + rid = reserve(&p->write_idx, ri + ei, num_packets); + } + + return __builtin_astype(sub_group_broadcast(rid, 0), reserve_id_t); +} + diff --git a/amd/device-libs/opencl/src/pipes/validp.cl b/amd/device-libs/opencl/src/pipes/validp.cl new file mode 100644 index 0000000000000..5397dfce0bfa3 --- /dev/null +++ b/amd/device-libs/opencl/src/pipes/validp.cl @@ -0,0 +1,14 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + + +__attribute__((overloadable, always_inline)) bool +is_valid_reserve_id(reserve_id_t rid) +{ + return as_ulong(rid) != ~(size_t)0; +} + diff --git a/amd/device-libs/opencl/src/pipes/wresvnp.cl b/amd/device-libs/opencl/src/pipes/wresvnp.cl new file mode 100644 index 0000000000000..421f16d59e994 --- /dev/null +++ b/amd/device-libs/opencl/src/pipes/wresvnp.cl @@ -0,0 +1,58 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "oclc.h" +#include "ockl.h" +#include "pipes.h" + +static uint +active_lane_count(void) +{ + return __builtin_popcountl(__builtin_amdgcn_ballot_w64(true)); +} + +size_t +__amd_wresvn(volatile __global atomic_size_t *pidx, size_t lim, size_t n) +{ + uint alc = active_lane_count(); + uint l = __ockl_lane_u32(); + size_t rid; + + if (__builtin_amdgcn_read_exec() == (1UL << alc) - 1UL) { + // Handle fully active subgroup + uint sum = sub_group_scan_inclusive_add((uint)n); + size_t idx = 0; + if (l == alc-1) { + idx = reserve(pidx, lim, (size_t)sum); + } + idx = sub_group_broadcast(idx, alc-1); + rid = idx + (size_t)(sum - (uint)n); + rid = idx != ~(size_t)0 ? rid : idx; + } else { + uint sum = __ockl_alisa_u32((uint)n); + uint al = __ockl_activelane_u32(); + + size_t idx = 0; + if (al == 0) { + idx = reserve(pidx, lim, (size_t)sum); + } + __builtin_amdgcn_wave_barrier(); + idx = ((size_t)__builtin_amdgcn_readfirstlane((uint)(idx >> 32)) << 32) | + (size_t)__builtin_amdgcn_readfirstlane((uint)idx); + + rid = idx + (size_t)(sum - (uint)n); + rid = idx != ~(size_t)0 ? rid : idx; + } + + if (rid == ~(size_t)0) { + // Try again one at a time + rid = reserve(pidx, lim, n); + } + + return rid; +} + diff --git a/amd/device-libs/opencl/src/pipes/writep.cl b/amd/device-libs/opencl/src/pipes/writep.cl new file mode 100644 index 0000000000000..2508f1fa7c3ae --- /dev/null +++ b/amd/device-libs/opencl/src/pipes/writep.cl @@ -0,0 +1,71 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "pipes.h" + +#define ATTR __attribute__((always_inline)) + +#define WRITE_PIPE_SIZE(SIZE, STYPE) \ +ATTR int \ +__write_pipe_2_##SIZE(__global struct pipeimp* p, const STYPE* ptr) \ +{ \ + size_t ri = atomic_load_explicit(&p->read_idx, memory_order_relaxed, memory_scope_device); \ + size_t ei = p->end_idx; \ + size_t wi = wave_reserve_1(&p->write_idx, ri+ei); \ + if (wi == ~(size_t)0) \ + return -1; \ + \ + size_t pi = wrap(wi, ei); \ + ((__global STYPE *)p->packets)[pi] = *ptr; \ + return 0; \ +} + +DO_PIPE_SIZE(WRITE_PIPE_SIZE) + +ATTR int +__write_pipe_2(__global struct pipeimp* p, const void* ptr, uint size, uint align) +{ + size_t ri = atomic_load_explicit(&p->read_idx, memory_order_relaxed, memory_scope_device); + size_t ei = p->end_idx; + size_t wi = wave_reserve_1(&p->write_idx, ri+ei); + if (wi == ~(size_t)0) + return -1; + + size_t pi = wrap(wi, ei); + void *pipe_ptr = p->packets + pi * size; + ASSUME_ALIGNED(pipe_ptr, align); + ASSUME_ALIGNED(ptr, align); + __builtin_memcpy(pipe_ptr, ptr, size); + + return 0; +} + +#define WRITE_PIPE_RESERVED_SIZE(SIZE, STYPE) \ +ATTR int \ +__write_pipe_4_##SIZE(__global struct pipeimp* p, reserve_id_t rid, uint i, const STYPE* ptr) \ +{ \ + size_t rin = __builtin_astype(rid, size_t) + i; \ + size_t pi = wrap(rin, p->end_idx); \ + ((__global STYPE *)p->packets)[pi] = *ptr; \ + return 0; \ +} + +DO_PIPE_SIZE(WRITE_PIPE_RESERVED_SIZE) + +ATTR int +__write_pipe_4(__global struct pipeimp* p, reserve_id_t rid, uint i, const void *ptr, uint size, uint align) +{ + size_t rin = __builtin_astype(rid, size_t) + i; \ + size_t pi = wrap(rin, p->end_idx); + void *pipe_ptr = p->packets + pi * size; + ASSUME_ALIGNED(pipe_ptr, align); + ASSUME_ALIGNED(ptr, align); + __builtin_memcpy(pipe_ptr, ptr, size); + + return 0; +} + diff --git a/amd/device-libs/opencl/src/relational/anyall.cl b/amd/device-libs/opencl/src/relational/anyall.cl new file mode 100644 index 0000000000000..787260b0f8ea5 --- /dev/null +++ b/amd/device-libs/opencl/src/relational/anyall.cl @@ -0,0 +1,63 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define ATTR __attribute__((overloadable, const)) + +#define char_mask ((char)1 << 7) +#define short_mask ((short)1 << 15) +#define int_mask ((int)1 << 31) +#define long_mask ((long)1 << 63) + +#define any_op | +#define all_op & + +#define RED(T,O) + +#define RED2(T,O) \ + T a = a2.lo O a2.hi + +#define RED3(T,O) \ + T a = a3.s0 O a3.s1 O a3.s2 + +#define RED4(T,O) \ + T##2 a2 = a4.hi O a4.lo; \ + RED2(T,O) + +#define RED8(T,O) \ + T##4 a4 = a8.hi O a8.lo; \ + RED4(T,O) + +#define RED16(T,O) \ + T##8 a8 = a16.hi O a16.lo; \ + RED8(T,O) + +#define RET(T) return (a & T##_mask) != (T)0 + +#define GENNT(F,N,T) \ +ATTR int \ +F(T##N a##N) \ +{ \ + RED##N(T,F##_op); \ + RET(T); \ +} + +#define GENT(F,T) \ + GENNT(F,16,T) \ + GENNT(F,8,T) \ + GENNT(F,4,T) \ + GENNT(F,3,T) \ + GENNT(F,2,T) \ + GENNT(F,,T) + +#define GEN(F) \ + GENT(F,char) \ + GENT(F,short) \ + GENT(F,int) \ + GENT(F,long) + +GEN(any) +GEN(all) diff --git a/amd/device-libs/opencl/src/relational/bselect.cl b/amd/device-libs/opencl/src/relational/bselect.cl new file mode 100644 index 0000000000000..34e20ded8df52 --- /dev/null +++ b/amd/device-libs/opencl/src/relational/bselect.cl @@ -0,0 +1,71 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#define _S(X) #X +#define S(X) _S(X) + +#define _C(A,B) A##B +#define C(A,B) _C(A,B) + +#define ATTR __attribute__((overloadable, const)) +#define IATTR __attribute__((const)) +#define AATTR(S) __attribute__((overloadable, const, alias(S))) + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define char_utype uchar +#define short_utype ushort +#define int_utype uint +#define long_utype ulong +#define float_itype int +#define float_utype uint +#define double_itype long +#define double_utype ulong +#define half_itype short +#define half_utype ushort + +#define FGENN(N,T) \ +ATTR T##N \ +bitselect(T##N a, T##N b, T##N c) \ +{ \ + return as_##T##N(bitselect(C(as_,C(T##_itype,N))(a), C(as_,C(T##_itype,N))(b), C(as_,C(T##_itype,N))(c))); \ +} \ + +#define FGEN(T) \ + FGENN(16,T) \ + FGENN(8,T) \ + FGENN(4,T) \ + FGENN(3,T) \ + FGENN(2,T) \ + FGENN(,T) + +FGEN(float) +FGEN(double) +FGEN(half) + +#define IGENN(N,T) \ +IATTR static T##N \ +bsel_##T##N(T##N a, T##N b, T##N c) \ +{ \ + return a ^ ((a ^ b) & c); \ +} \ +extern AATTR(S(bsel_##T##N)) T##N bitselect(T##N, T##N, T##N); \ +extern AATTR(S(bsel_##T##N)) C(T##_utype,N) bitselect(C(T##_utype,N), C(T##_utype,N), C(T##_utype,N)); + +#define IGEN(T) \ + IGENN(16,T) \ + IGENN(8,T) \ + IGENN(4,T) \ + IGENN(3,T) \ + IGENN(2,T) \ + IGENN(,T) + +IGEN(char) +IGEN(short) +IGEN(int) +IGEN(long) + diff --git a/amd/device-libs/opencl/src/relational/predicates.cl b/amd/device-libs/opencl/src/relational/predicates.cl new file mode 100644 index 0000000000000..db756b2744bca --- /dev/null +++ b/amd/device-libs/opencl/src/relational/predicates.cl @@ -0,0 +1,132 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ocml.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ATTR __attribute__((overloadable, const)) + +#define _C(A,B) A##B +#define C(A,B) _C(A,B) + +#define float_ssuf _f32 +#define double_ssuf _f64 +#define half_ssuf _f16 +#define half_psuf _2f16 + +#define float_rtype int +#define double_rtype long +#define half_rtype short + +#define SNAME(F,T) C(__ocml_,C(F,T##_ssuf)) +#define PNAME(F,T) C(__ocml_,C(F,T##_psuf)) + +#define USLST2(F,T) -SNAME(F,T)(x.s0), -SNAME(F,T)(x.s1) +#define USLST3(F,T) USLST2(F,T), -SNAME(F,T)(x.s2) +#define USLST4(F,T) USLST2(F,T), -SNAME(F,T)(x.s2), -SNAME(F,T)(x.s3) +#define USLST8(F,T) USLST4(F,T), -SNAME(F,T)(x.s4), -SNAME(F,T)(x.s5), -SNAME(F,T)(x.s6), -SNAME(F,T)(x.s7) +#define USLST16(F,T) USLST8(F,T), -SNAME(F,T)(x.s8), -SNAME(F,T)(x.s9), -SNAME(F,T)(x.sa), -SNAME(F,T)(x.sb), -SNAME(F,T)(x.sc), -SNAME(F,T)(x.sd), -SNAME(F,T)(x.se), -SNAME(F,T)(x.sf) + +#define UPLST3(F,T) PNAME(F,T)(x.s01), -SNAME(F,T)(x.s2) +#define UPLST4(F,T) PNAME(F,T)(x.s01), PNAME(F,T)(x.s23) +#define UPLST8(F,T) UPLST4(F,T), PNAME(F,T)(x.s45), PNAME(F,T)(x.s67) +#define UPLST16(F,T) UPLST8(F,T), PNAME(F,T)(x.s89), PNAME(F,T)(x.sab), PNAME(F,T)(x.scd), PNAME(F,T)(x.sef) + +#define USGENTN(N,F,T) \ +ATTR C(T##_rtype,N) \ +F(T##N x) \ +{ \ + return (C(T##_rtype,N)) ( USLST##N(F,T) ); \ +} + +#define UPGENTN(N,F,T) \ +ATTR C(T##_rtype,N) \ +F(T##N x) \ +{ \ + return (C(T##_rtype,N)) ( UPLST##N(F,T) ); \ +} + +#define UGENT1(F,T) \ +ATTR int \ +F(T x) \ +{ \ + return SNAME(F,T)(x); \ +} + +#define UGENT2(F,T) \ +ATTR C(T##_rtype,2) \ +F(T##2 x) \ +{ \ + return PNAME(F,T)(x); \ +} + +#define USGENT(F,T) \ + USGENTN(16,F,T) \ + USGENTN(8,F,T) \ + USGENTN(4,F,T) \ + USGENTN(3,F,T) \ + USGENTN(2,F,T) \ + UGENT1(F,T) + +#define UPGENT(F,T) \ + UPGENTN(16,F,T) \ + UPGENTN(8,F,T) \ + UPGENTN(4,F,T) \ + UPGENTN(3,F,T) \ + UGENT2(F,T) \ + UGENT1(F,T) + +#define UGEN(F) \ + USGENT(F,float) \ + USGENT(F,double) \ + UPGENT(F,half) + +UGEN(isfinite) +UGEN(isinf) +UGEN(isnan) +UGEN(isnormal) +UGEN(signbit) + +#define BGENTN(N,F,T,E) \ +ATTR C(T##_rtype,N) \ +F(T##N x, T##N y) \ +{ \ + return E; \ +} + +#define BGENT1(F,T,E) \ +ATTR int \ +F(T x, T y) \ +{ \ + return E; \ +} + +#define BGENT(F,T,E) \ + BGENTN(16,F,T,E) \ + BGENTN(8,F,T,E) \ + BGENTN(4,F,T,E) \ + BGENTN(3,F,T,E) \ + BGENTN(2,F,T,E) \ + BGENT1(F,T,E) + +#define BGEN(F,E) \ + BGENT(F,float,E) \ + BGENT(F,double,E) \ + BGENT(F,half,E) + +BGEN(isequal,x==y) +BGEN(isnotequal,x!=y) +BGEN(isgreater,x>y) +BGEN(isgreaterequal,x>=y) +BGEN(isless,x> __oclc_wavefrontsize_log2; +} + +CATTR uint +get_enqueued_num_sub_groups(void) +{ + uint wgs = mul24((uint)get_enqueued_local_size(2), mul24((uint)get_enqueued_local_size(1), (uint)get_enqueued_local_size(0))); + return (wgs + OCLC_WAVEFRONT_SIZE - 1) >> __oclc_wavefrontsize_log2; +} + +CATTR uint +get_sub_group_id(void) +{ + + return (uint)get_local_linear_id() >> __oclc_wavefrontsize_log2; +} + +CATTR uint +get_sub_group_local_id(void) +{ + return __ockl_lane_u32(); +} + diff --git a/amd/device-libs/opencl/src/subgroup/subredscan.cl b/amd/device-libs/opencl/src/subgroup/subredscan.cl new file mode 100644 index 0000000000000..a05e6371c797a --- /dev/null +++ b/amd/device-libs/opencl/src/subgroup/subredscan.cl @@ -0,0 +1,75 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "ockl.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _C(X,Y) X ## Y +#define C(X,Y) _C(X,Y) + +#define red_full reduce +#define scan_full scan + +#define PFX __ockl_wf +#define ATTR __attribute__((overloadable)) + +#define i32_tn int +#define u32_tn uint +#define i64_tn long +#define u64_tn ulong +#define f32_tn float +#define f64_tn double +#define f16_tn half + +#define true_inc inclusive_ +#define false_inc exclusive_ + +#define GENROT(O,T) \ +ATTR T##_tn \ +C(sub_group_reduce_,O)(T##_tn x) \ +{ \ + return C(PFX,C(red_,C(O,C(_,T))))(x); \ +} + +#define GENRO(O) \ + GENROT(O,i32) \ + GENROT(O,u32) \ + GENROT(O,i64) \ + GENROT(O,u64) \ + GENROT(O,f32) \ + GENROT(O,f64) \ + GENROT(O,f16) + +GENRO(add) +GENRO(max) +GENRO(min) + +#define GENSOTI(O, T, I) \ +ATTR T##_tn \ +C(sub_group_scan_,C(I##_inc,O))(T##_tn x) \ +{ \ + return C(PFX,C(scan_,C(O,C(_,T))))(x, I); \ +} + +#define GENSOT(O,T) \ + GENSOTI(O,T,false) \ + GENSOTI(O,T,true) + +#define GENSO(O) \ + GENSOT(O,i32) \ + GENSOT(O,u32) \ + GENSOT(O,i64) \ + GENSOT(O,u64) \ + GENSOT(O,f32) \ + GENSOT(O,f64) \ + GENSOT(O,f16) + +GENSO(add) +GENSO(max) +GENSO(min) + diff --git a/amd/device-libs/opencl/src/vldst/vldst_gen.cl b/amd/device-libs/opencl/src/vldst/vldst_gen.cl new file mode 100644 index 0000000000000..e396a4e0ebc33 --- /dev/null +++ b/amd/device-libs/opencl/src/vldst/vldst_gen.cl @@ -0,0 +1,117 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define _C(X,Y) X##Y +#define C(X,Y) _C(X,Y) + +#define _S(X) #X +#define S(X) _S(X) + +#define LATTR __attribute__((overloadable, pure)) +#define SATTR __attribute__((overloadable)) + +#define char_align 1 +#define uchar_align 1 +#define short_align 2 +#define ushort_align 2 +#define int_align 4 +#define uint_align 4 +#define long_align 8 +#define ulong_align 8 +#define float_align 4 +#define double_align 8 +#define half_align 2 + +#define LGENAN(N,A,T) \ +LATTR T##N \ +vload##N(size_t i, const A T *p) \ +{ \ + typedef T __attribute__((ext_vector_type(N), aligned(T##_align))) vt; \ + p += i * N; \ + return *(const A vt *)p; \ +} + +#define LGENA3(A,T) \ +LATTR T##3 \ +vload3(size_t i, const A T *p) \ +{ \ + p += i * 3; \ + return (T##3) ( p[0], p[1], p[2] ); \ +} + +#define LGENA(A,T) \ + LGENAN(16,A,T) \ + LGENAN(8,A,T) \ + LGENAN(4,A,T) \ + LGENA3(A,T) \ + LGENAN(2,A,T) + +#define LGEN(T) \ + LGENA(__constant,T) \ + LGENA(__private,T) \ + LGENA(__local,T) \ + LGENA(__global,T) \ + LGENA(,T) + +LGEN(char) +LGEN(uchar) +LGEN(short) +LGEN(ushort) +LGEN(int) +LGEN(uint) +LGEN(long) +LGEN(ulong) +LGEN(float) +LGEN(double) +LGEN(half) + +#define SGENAN(N,A,T) \ +SATTR void \ +vstore##N(T##N v, size_t i, A T *p) \ +{ \ + typedef T __attribute__((ext_vector_type(N), aligned(T##_align))) vt; \ + p += i * N; \ + *(A vt *)p = v; \ +} + +#define SGENA3(A,T) \ +SATTR void \ +vstore3(T##3 v, size_t i, A T *p) \ +{ \ + p += i * 3; \ + p[0] = v.s0; \ + p[1] = v.s1; \ + p[2] = v.s2; \ +} + +#define SGENA(A,T) \ + SGENAN(16,A,T) \ + SGENAN(8,A,T) \ + SGENAN(4,A,T) \ + SGENA3(A,T) \ + SGENAN(2,A,T) + +#define SGEN(T) \ + SGENA(__private,T) \ + SGENA(__local,T) \ + SGENA(__global,T) \ + SGENA(,T) + +SGEN(char) +SGEN(uchar) +SGEN(short) +SGEN(ushort) +SGEN(int) +SGEN(uint) +SGEN(long) +SGEN(ulong) +SGEN(float) +SGEN(double) +SGEN(half) + diff --git a/amd/device-libs/opencl/src/vldst/vldst_half.cl b/amd/device-libs/opencl/src/vldst/vldst_half.cl new file mode 100644 index 0000000000000..063b1cbe37448 --- /dev/null +++ b/amd/device-libs/opencl/src/vldst/vldst_half.cl @@ -0,0 +1,160 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#define LATTR __attribute__((overloadable, pure)) +#define SATTR __attribute__((overloadable)) + +#define LGENAN(N,A) \ +LATTR float##N \ +vload_half##N(size_t i, const A half *p) \ +{ \ + return convert_float##N(vload##N(i, p)); \ +} + +#define LGENA1(A) \ +LATTR float \ +vload_half(size_t i, const A half *p) \ +{ \ + return convert_float(p[i]); \ +} + +#define LGENA(A) \ + LGENAN(16,A) \ + LGENAN(8,A) \ + LGENAN(4,A) \ + LGENAN(3,A) \ + LGENAN(2,A) \ + LGENA1(A) + +LGENA(__constant) +LGENA(__global) +LGENA(__local) +LGENA(__private) +LGENA() + +#define LAGENAN(N,A) \ +LATTR float##N \ +vloada_half##N(size_t i, const A half *p) \ +{ \ + return convert_float##N(*(const A half##N *)(p + i*N)); \ +} + +#define LAGENA3(A) \ +LATTR float3 \ +vloada_half3(size_t i, const A half *p) \ +{ \ + half4 v = *(const A half4 *)(p + i*4); \ + return convert_float3(v.s012); \ +} + +#define LAGENA1(A) \ +LATTR float \ +vloada_half(size_t i, const A half *p) \ +{ \ + return convert_float(p[i]); \ +} + +#define LAGENA(A) \ + LAGENAN(16,A) \ + LAGENAN(8,A) \ + LAGENAN(4,A) \ + LAGENA3(A) \ + LAGENAN(2,A) \ + LAGENA1(A) + +LAGENA(__constant) +LAGENA(__global) +LAGENA(__local) +LAGENA(__private) +LAGENA() + +#define SGENTARN(N,T,A,R) \ +SATTR void \ +vstore_half##N##R(T##N v, size_t i, A half *p) \ +{ \ + vstore##N(convert_half##N##R(v), i, p); \ +} + +#define SGENTAR1(T,A,R) \ +SATTR void \ +vstore_half##R(T v, size_t i, A half *p) \ +{ \ + p[i] = convert_half##R(v); \ +} + +#define SGENTAR(T,A,R) \ + SGENTARN(16,T,A,R) \ + SGENTARN(8,T,A,R) \ + SGENTARN(4,T,A,R) \ + SGENTARN(3,T,A,R) \ + SGENTARN(2,T,A,R) \ + SGENTAR1(T,A,R) + +#define SGENTA(T,A) \ + SGENTAR(T,A,) \ + SGENTAR(T,A,_rte) \ + SGENTAR(T,A,_rtn) \ + SGENTAR(T,A,_rtp) \ + SGENTAR(T,A,_rtz) + +#define SGENT(T) \ + SGENTA(T,__global) \ + SGENTA(T,__local) \ + SGENTA(T,__private) \ + SGENTA(T,) + +SGENT(float) +SGENT(double) + +#define SAGENTARN(N,T,A,R) \ +SATTR void \ +vstorea_half##N##R(T##N v, size_t i, A half *p) \ +{ \ + *(A half##N *)(p + i*N) = convert_half##N##R(v); \ +} + +#define SAGENTAR3(T,A,R) \ +SATTR void \ +vstorea_half3##R(T##3 v, size_t i, A half *p) \ +{ \ + half4 h; \ + h.s012 = convert_half3##R(v); \ + *(A half4 *)(p + i*4) = h; \ +} + +#define SAGENTAR1(T,A,R) \ +SATTR void \ +vstorea_half##R(T v, size_t i, A half *p) \ +{ \ + p[i] = convert_half##R(v); \ +} + +#define SAGENTAR(T,A,R) \ + SAGENTARN(16,T,A,R) \ + SAGENTARN(8,T,A,R) \ + SAGENTARN(4,T,A,R) \ + SAGENTAR3(T,A,R) \ + SAGENTARN(2,T,A,R) \ + SAGENTAR1(T,A,R) + +#define SAGENTA(T,A) \ + SAGENTAR(T,A,) \ + SAGENTAR(T,A,_rte) \ + SAGENTAR(T,A,_rtn) \ + SAGENTAR(T,A,_rtp) \ + SAGENTAR(T,A,_rtz) + +#define SAGENT(T) \ + SAGENTA(T,__global) \ + SAGENTA(T,__local) \ + SAGENTA(T,__private) \ + SAGENTA(T,) + +SAGENT(float) +SAGENT(double) + diff --git a/amd/device-libs/opencl/src/workgroup/wganyall.cl b/amd/device-libs/opencl/src/workgroup/wganyall.cl new file mode 100644 index 0000000000000..71b845bfaca25 --- /dev/null +++ b/amd/device-libs/opencl/src/workgroup/wganyall.cl @@ -0,0 +1,41 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "wgscratch.h" + +#define update_any atomic_fetch_or_explicit +#define update_all atomic_fetch_and_explicit + +#define GEN_AA(SUF,ID) \ +__attribute__((overloadable, always_inline)) int \ +work_group_##SUF(int predicate) \ +{ \ + uint n = get_num_sub_groups(); \ + int a = sub_group_##SUF(predicate); \ + if (n == 1) \ + return a; \ + \ + __local atomic_uint *p = (__local atomic_uint *)__get_scratch_lds(); \ + uint l = get_sub_group_local_id(); \ + uint i = get_sub_group_id(); \ + \ + if ((i == 0) & (l == 0)) \ + atomic_store_explicit(p, a, memory_order_relaxed, memory_scope_work_group); \ + \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + if ((i != 0) & (l == 0)) \ + update_##SUF(p, a, memory_order_relaxed, memory_scope_work_group); \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + a = atomic_load_explicit(p, memory_order_relaxed, memory_scope_work_group); \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + \ + return a; \ +} + +GEN_AA(all, 1U) +GEN_AA(any, 0U); + diff --git a/amd/device-libs/opencl/src/workgroup/wgbarrier.cl b/amd/device-libs/opencl/src/workgroup/wgbarrier.cl new file mode 100644 index 0000000000000..5f02529034188 --- /dev/null +++ b/amd/device-libs/opencl/src/workgroup/wgbarrier.cl @@ -0,0 +1,39 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +__attribute__((overloadable)) void +barrier(cl_mem_fence_flags flags) +{ + work_group_barrier(flags); +} + +__attribute__((overloadable)) void +work_group_barrier(cl_mem_fence_flags flags) +{ + work_group_barrier(flags, memory_scope_work_group); +} + +__attribute__((overloadable)) void +work_group_barrier(cl_mem_fence_flags flags, memory_scope scope) +{ + if (flags) { + atomic_work_item_fence(flags, + flags == (CLK_GLOBAL_MEM_FENCE|CLK_LOCAL_MEM_FENCE) ? + memory_order_seq_cst : memory_order_release, + scope); + + __builtin_amdgcn_s_barrier(); + + atomic_work_item_fence(flags, + flags == (CLK_GLOBAL_MEM_FENCE|CLK_LOCAL_MEM_FENCE) ? + memory_order_seq_cst : memory_order_acquire, + scope); + } else { + __builtin_amdgcn_s_barrier(); + } +} + diff --git a/amd/device-libs/opencl/src/workgroup/wgbcast.cl b/amd/device-libs/opencl/src/workgroup/wgbcast.cl new file mode 100644 index 0000000000000..0d2972c443ba0 --- /dev/null +++ b/amd/device-libs/opencl/src/workgroup/wgbcast.cl @@ -0,0 +1,60 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "wgscratch.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + + +#define GEN_BROADCAST(T) \ +__attribute__((overloadable, always_inline)) T \ +work_group_broadcast(T a, size_t local_id_x) \ +{ \ + if (get_num_sub_groups() == 1) \ + return sub_group_broadcast(a, local_id_x); \ + \ + __local T *p = (__local T *)__get_scratch_lds(); \ + if (get_local_id(0) == local_id_x) \ + *p = a; \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + a = *p; \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + return a; \ +} \ +\ +__attribute__((overloadable, always_inline)) T \ +work_group_broadcast(T a, size_t local_id_x, size_t local_id_y) \ +{ \ + __local T *p = (__local T *)__get_scratch_lds(); \ + if (get_local_id(0) == local_id_x && get_local_id(1) == local_id_y) \ + *p = a; \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + a = *p; \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + return a; \ +} \ +\ +__attribute__((overloadable, always_inline)) T \ +work_group_broadcast(T a, size_t local_id_x, size_t local_id_y, size_t local_id_z) \ +{ \ + __local T *p = (__local T *)__get_scratch_lds(); \ + if (get_local_id(0) == local_id_x && get_local_id(1) == local_id_y && get_local_id(2) == local_id_z) \ + *p = a; \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + a = *p; \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + return a; \ +} + +GEN_BROADCAST(uint) +GEN_BROADCAST(int) +GEN_BROADCAST(ulong) +GEN_BROADCAST(long) +GEN_BROADCAST(float) +GEN_BROADCAST(double) +GEN_BROADCAST(half) + diff --git a/amd/device-libs/opencl/src/workgroup/wgreduce.cl b/amd/device-libs/opencl/src/workgroup/wgreduce.cl new file mode 100644 index 0000000000000..2279166c3d3c9 --- /dev/null +++ b/amd/device-libs/opencl/src/workgroup/wgreduce.cl @@ -0,0 +1,107 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "wgscratch.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#pragma OPENCL EXTENSION cl_khr_int64_base_atomics : enable +#pragma OPENCL EXTENSION cl_khr_int64_extended_atomics : enable + +#define reduce_add atomic_fetch_add_explicit +#define reduce_min atomic_fetch_min_explicit +#define reduce_max atomic_fetch_max_explicit + +#define AGEN(T,OP) \ +__attribute__((overloadable)) T \ +work_group_reduce_##OP(T a) \ +{ \ + uint n = get_num_sub_groups(); \ + a = sub_group_reduce_##OP(a); \ + if (n == 1) \ + return a; \ + \ + __local atomic_##T *p = (__local atomic_##T *)__get_scratch_lds(); \ + uint l = get_sub_group_local_id(); \ + uint i = get_sub_group_id(); \ + \ + if ((i == 0) & (l == 0)) \ + atomic_store_explicit(p, a, memory_order_relaxed, memory_scope_work_group); \ + \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + if ((i != 0) & (l == 0)) \ + reduce_##OP(p, a, memory_order_relaxed, memory_scope_work_group); \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + a = atomic_load_explicit(p, memory_order_relaxed, memory_scope_work_group); \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + return a; \ +} + +AGEN(int,add) +AGEN(int,max) +AGEN(int,min) + +AGEN(uint,add) +AGEN(uint,max) +AGEN(uint,min) + +AGEN(long,add) +AGEN(long,max) +AGEN(long,min) + +AGEN(ulong,add) +AGEN(ulong,max) +AGEN(ulong,min) + +// TODO implement floating point reduction using LDS atomics as above +// (note that ds_add_f32 is not available on GFX7) + +// TODO Use a special reduce for per-sub-group results since there +// are fewer of them than work-items in a sub group + +#define add(X,Y) (X + Y) + +#define SGEN(T,OP,ID) \ +__attribute__((overloadable)) T \ +work_group_reduce_##OP(T a) \ +{ \ + uint n = get_num_sub_groups(); \ + a = sub_group_reduce_##OP(a); \ + if (n == 1) \ + return a; \ + \ + __local T *p = (__local T *)__get_scratch_lds(); \ + uint l = get_sub_group_local_id(); \ + uint i = get_sub_group_id(); \ + \ + if (l == 0) \ + p[i] = a; \ + \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + if (i == 0) { \ + T t = l < n ? p[l] : ID; \ + t = sub_group_reduce_##OP(t); \ + if (l == 0) \ + p[0] = t; \ + } \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + T ret = p[0]; \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + return ret; \ +} + +SGEN(float,add,0.0f) +SGEN(float,max,-INFINITY) +SGEN(float,min,INFINITY) + +SGEN(double,add,0.0) +SGEN(double,max,-(double)INFINITY) +SGEN(double,min,(double)INFINITY) + +SGEN(half,add,0.0h) +SGEN(half,max,-(half)INFINITY) +SGEN(half,min,(half)INFINITY) + diff --git a/amd/device-libs/opencl/src/workgroup/wgscan.cl b/amd/device-libs/opencl/src/workgroup/wgscan.cl new file mode 100644 index 0000000000000..eb9e9395e2bc4 --- /dev/null +++ b/amd/device-libs/opencl/src/workgroup/wgscan.cl @@ -0,0 +1,130 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#include "wgscratch.h" + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +// TODO Use a special scan for per-sub-group results since there +// are fewer of them than work-items in a sub group + +#define add(X,Y) (X + Y) + +#define GENI(TYPE,OP,ID) \ +__attribute__((overloadable)) TYPE \ +work_group_scan_inclusive_##OP(TYPE a) \ +{ \ + uint n = get_num_sub_groups(); \ + a = sub_group_scan_inclusive_##OP(a); \ + if (n == 1) \ + return a; \ + \ + __local TYPE *p = (__local TYPE *)__get_scratch_lds(); \ + uint l = get_sub_group_local_id(); \ + uint i = get_sub_group_id(); \ + \ + if (l == get_sub_group_size() - 1U) \ + p[i] = a; \ + \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + if (i == 0) { \ + TYPE t = l < n ? p[l] : ID; \ + t = sub_group_scan_inclusive_##OP(t); \ + if (l < n) \ + p[l] = t; \ + } \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + TYPE ret = i == 0 ? a : OP(a, p[i-1]); \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + return ret; \ +} + +GENI(int,add,0) +GENI(int,max,INT_MIN) +GENI(int,min,INT_MAX) + +GENI(uint,add,0U) +GENI(uint,max,0U) +GENI(uint,min,UINT_MAX) + +GENI(long,add,0L) +GENI(long,max,LONG_MIN) +GENI(long,min,LONG_MAX) + +GENI(ulong,add,0UL) +GENI(ulong,max,0UL) +GENI(ulong,min,ULONG_MAX) + +GENI(float,add,0.0f) +GENI(float,max,-INFINITY) +GENI(float,min,INFINITY) + +GENI(double,add,0.0) +GENI(double,max,-(double)INFINITY) +GENI(double,min,(double)INFINITY) + +GENI(half,add,0.0h) +GENI(half,max,-(half)INFINITY) +GENI(half,min,(half)INFINITY) + +#define GENE(TYPE,OP,ID) \ +__attribute__((overloadable)) TYPE \ +work_group_scan_exclusive_##OP(TYPE a) \ +{ \ + uint n = get_num_sub_groups(); \ + TYPE t = sub_group_scan_exclusive_##OP(a); \ + if (n == 1) \ + return t; \ + \ + __local TYPE *p = (__local TYPE *)__get_scratch_lds(); \ + uint l = get_sub_group_local_id(); \ + uint i = get_sub_group_id(); \ + \ + if (l == get_sub_group_size() - 1U) \ + p[i] = OP(a, t); \ + \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + if (i == 0) { \ + TYPE s = l < n ? p[l] : ID; \ + s = sub_group_scan_inclusive_##OP(s); \ + if (l < n) \ + p[l] = s; \ + } \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + TYPE ret = i == 0 ? t : OP(t, p[i-1]); \ + work_group_barrier(CLK_LOCAL_MEM_FENCE); \ + return ret; \ +} + +GENE(int,add,0) +GENE(int,max,INT_MIN) +GENE(int,min,INT_MAX) + +GENE(uint,add,0U) +GENE(uint,max,0U) +GENE(uint,min,UINT_MAX) + +GENE(long,add,0L) +GENE(long,max,LONG_MIN) +GENE(long,min,LONG_MAX) + +GENE(ulong,add,0UL) +GENE(ulong,max,0UL) +GENE(ulong,min,ULONG_MAX) + +GENE(float,add,0.0f) +GENE(float,max,-INFINITY) +GENE(float,min,INFINITY) + +GENE(double,add,0.0) +GENE(double,max,-(double)INFINITY) +GENE(double,min,(double)INFINITY) + +GENE(half,add,0.0h) +GENE(half,max,-(half)INFINITY) +GENE(half,min,(half)INFINITY) + diff --git a/amd/device-libs/test/compile/CMakeLists.txt b/amd/device-libs/test/compile/CMakeLists.txt new file mode 100644 index 0000000000000..86acf3ad33d22 --- /dev/null +++ b/amd/device-libs/test/compile/CMakeLists.txt @@ -0,0 +1,109 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +if(TARGET FileCheck) + set(FILECHECK_BIN $) +else() + # FIXME: Is there a better way to get the binary directory? + # FileCheck is also not normally installed, so it only really works + # well with build directories by default. + find_program(FILECHECK_BIN FileCheck + HINTS ${LLVM_DIR}/../../../bin) +endif() + +if(NOT FILECHECK_BIN) + message(STATUS "FileCheck not found, not adding constant fold tests") + return() +endif() + +message(STATUS "Running constant fold tests") + +function(add_compile_test test_name func_name) + set(parse_options) + set(one_value_args TEST_CPU FILE_NAME SCRIPT EXTRA_CHECK_PREFIXES) + set(multi_value_args COMPILE_FLAGS) + + cmake_parse_arguments(COMPILE_TEST "${parse_options}" "${one_value_args}" + "${multi_value_args}" ${ARGN}) + + set(test_cpu ${COMPILE_TEST_TEST_CPU}) + set(file_name ${COMPILE_TEST_FILE_NAME}) + + add_test(NAME ${test_name}__${test_cpu} + COMMAND ${CMAKE_COMMAND} + -DCLANG_BIN=$ + -DBINARY_DIR=${PROJECT_BINARY_DIR} + -DFILECHECK_BIN=${FILECHECK_BIN} + -DOUTPUT_FILE=output.${test_name}.${test_cpu}.s + -DINPUT_FILE=${file_name} + -DTEST_CPU=${test_cpu} + -DCOMPILE_FLAGS=${COMPILE_TEST_COMPILE_FLAGS} + -DEXTRA_CHECK_PREFIX=${COMPILE_TEST_EXTRA_CHECK_PREFIXES} + -P ${COMPILE_TEST_SCRIPT}) +endfunction() + + +# Add constant folding tests +function(add_constant_fold_test name test_cpu) + add_compile_test(constant_fold_${name} ${name} + FILE_NAME ${CMAKE_CURRENT_SOURCE_DIR}/${name}.cl + SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/RunConstantFoldTest.cmake + TEST_CPU ${test_cpu} + EXTRA_CHECK_PREFIXES CHECK + ${ARGN}) +endfunction() + +# Add full to ISA compile tests +function(add_isa_test name test_cpu) + string(TOUPPER ${test_cpu} check_prefix) + add_compile_test(compile_${name} ${name} + FILE_NAME ${CMAKE_CURRENT_SOURCE_DIR}/${name}.cl + SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/RunCompileTest.cmake + TEST_CPU ${test_cpu} + EXTRA_CHECK_PREFIXES "${check_prefix},GCN" + ${ARGN}) +endfunction() + + +foreach(gpu gfx900 gfx1030) + add_constant_fold_test(lgamma_r ${gpu}) +endforeach() + +foreach(gpu gfx803) + add_isa_test(asin ${gpu}) + add_isa_test(atan2 ${gpu}) + add_isa_test(atan2pi ${gpu}) +endforeach() + +foreach(gpu gfx600) + add_isa_test(frexp ${gpu}) +endforeach() + +foreach(gpu gfx900) + # Test with default denormal enabled target + add_isa_test(rsqrt ${gpu} + EXTRA_CHECK_PREFIXES IEEE) + add_isa_test(rsqrt_daz ${gpu} + FILE_NAME ${CMAKE_CURRENT_SOURCE_DIR}/rsqrt.cl + COMPILE_FLAGS -cl-denorms-are-zero + EXTRA_CHECK_PREFIXES DAZ) +endforeach() + + +foreach(gpu gfx600 gfx700 gfx803) + add_isa_test(fract ${gpu}) + add_isa_test(native_rcp ${gpu}) + add_isa_test(native_rsqrt ${gpu}) + add_isa_test(native_log ${gpu}) + add_isa_test(native_exp ${gpu}) +endforeach() + +foreach(gpu gfx803 gfx900 gfx90a gfx1030 gfx1100 gfx1200) + add_isa_test(atomic_work_item_fence ${gpu} + FILE_NAME ${CMAKE_CURRENT_SOURCE_DIR}/atomic_work_item_fence.cl + COMPILE_FLAGS -emit-llvm) +endforeach() diff --git a/amd/device-libs/test/compile/RunCompileTest.cmake b/amd/device-libs/test/compile/RunCompileTest.cmake new file mode 100644 index 0000000000000..02feccb6a7faa --- /dev/null +++ b/amd/device-libs/test/compile/RunCompileTest.cmake @@ -0,0 +1,38 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +# Test execution is wrapped here because add_test only allows running +# one command at a time. + +# FIXME: It would be better to use llvm-lit and parse RUN lines from +# individual tests. + +execute_process(COMMAND + ${CLANG_BIN} -O3 -S -cl-std=CL2.0 + -target amdgcn-amd-amdhsa -mcpu=${TEST_CPU} + -Xclang -finclude-default-header + --rocm-path=${BINARY_DIR} + -mllvm -amdgpu-simplify-libcall=0 + ${COMPILE_FLAGS} + -o ${OUTPUT_FILE} ${INPUT_FILE} + RESULT_VARIABLE CLANG_RESULT + ERROR_VARIABLE CLANG_ERR) +if(CLANG_RESULT) + message(FATAL_ERROR "Error compiling test: ${CLANG_ERR}") +endif() + +execute_process(COMMAND ${FILECHECK_BIN} -v --enable-var-scope + --allow-unused-prefixes + --dump-input=fail + --dump-input-filter=all + ${INPUT_FILE} --input-file ${OUTPUT_FILE} + --check-prefixes=CHECK,${EXTRA_CHECK_PREFIX} + RESULT_VARIABLE FILECHECK_RESULT + ERROR_VARIABLE FILECHECK_ERROR) +if(FILECHECK_RESULT) + message(FATAL_ERROR "Error in test output: ${FILECHECK_ERROR}") +endif() diff --git a/amd/device-libs/test/compile/RunConstantFoldTest.cmake b/amd/device-libs/test/compile/RunConstantFoldTest.cmake new file mode 100644 index 0000000000000..54246900887d4 --- /dev/null +++ b/amd/device-libs/test/compile/RunConstantFoldTest.cmake @@ -0,0 +1,34 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +# Test execution is wrapped here because add_test only allows running +# one command at a time. + +# FIXME: It would be better to use llvm-lit and parse RUN lines from +# individual tests. + +execute_process(COMMAND + ${CLANG_BIN} -O3 -S -emit-llvm -cl-std=CL2.0 + -target amdgcn-amd-amdhsa -mcpu=${TEST_CPU} + -Xclang -finclude-default-header + --rocm-path=${BINARY_DIR} + -mllvm -amdgpu-simplify-libcall=0 + -o ${OUTPUT_FILE} ${INPUT_FILE} + RESULT_VARIABLE CLANG_RESULT + ERROR_VARIABLE CLANG_ERR) +if(CLANG_RESULT) + message(FATAL_ERROR "Error compiling test: ${CLANG_ERR}") +endif() + +execute_process(COMMAND ${FILECHECK_BIN} -v --enable-var-scope + ${INPUT_FILE} --input-file ${OUTPUT_FILE} + --check-prefix=CONSTANTFOLD + RESULT_VARIABLE FILECHECK_RESULT + ERROR_VARIABLE FILECHECK_ERROR) +if(FILECHECK_RESULT) + message(FATAL_ERROR "Error in test output: ${FILECHECK_ERROR}") +endif() diff --git a/amd/device-libs/test/compile/asin.cl b/amd/device-libs/test/compile/asin.cl new file mode 100644 index 0000000000000..3bce227448b40 --- /dev/null +++ b/amd/device-libs/test/compile/asin.cl @@ -0,0 +1,21 @@ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +// GCN: {{^}}test_asin_f16: +// GFX700: v_cvt_f32_f16{{(_e32)?}} [[CVT:v[0-9]+]] +// GFX700: v_cmp_le_f32{{(_e64)?}} s{{\[[0-9]+:[0-9]+\]}}, |[[CVT]]|, 0.5 +// GFX700: v_mul_f32 +// GFX700: v_mad_f32 +// GFX700: v_sqrt_f32 +// GFX700: v_bfi_b32 +// GFX700: v_cvt_f16_f32 + + +// GFX803: v_cmp_le_f16{{(_e64)?}} s{{\[[0-9]+:[0-9]+\]}}, |{{v[0-9]+}}|, 0.5 +// GFX803: v_mad_f32 +// GFX803: v_sqrt_f32 +// GFX803: v_bfi_b32 +kernel void test_asin_f16(global half* restrict out, global half* restrict in) { + int id = get_local_id(0); + out[id] = asin(in[id]); +} diff --git a/amd/device-libs/test/compile/atan2.cl b/amd/device-libs/test/compile/atan2.cl new file mode 100644 index 0000000000000..58e38456243ef --- /dev/null +++ b/amd/device-libs/test/compile/atan2.cl @@ -0,0 +1,23 @@ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +// GCN: {{^}}test_atan2_f16: +// GFX700: v_cvt_f32_f16 +// GFX700: v_mul_f32 +// GFX700: v_div_scale_f32 +// GFX700: v_div_scale_f32 +// GFX700: v_cmp_class_f32 +// GFX700: v_cmp_class_f32 +// GFX700: v_div_fixup_f32 +// GFX700: v_bfi_b32 + +// GFX803: v_max_f16 +// GFX803: v_rcp_f32 +// GFX803: v_mul_f32 +// GFX803: v_fma_f16 +// GFX803: v_cmp_o_f16 +// GFX803: v_bfi_b32 +kernel void test_atan2_f16(global half* restrict out, global half* restrict in0, global half* restrict in1) { + int id = get_local_id(0); + out[id] = atan2(in0[id], in1[id]); +} diff --git a/amd/device-libs/test/compile/atan2pi.cl b/amd/device-libs/test/compile/atan2pi.cl new file mode 100644 index 0000000000000..4488ec7968605 --- /dev/null +++ b/amd/device-libs/test/compile/atan2pi.cl @@ -0,0 +1,23 @@ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +// GCN: {{^}}test_atan2pi_f16: +// GFX700: v_cvt_f32_f16 +// GFX700: v_mul_f32 +// GFX700: v_div_scale_f32 +// GFX700: v_div_scale_f32 +// GFX700: v_cmp_class_f32 +// GFX700: v_cmp_class_f32 +// GFX700: v_div_fixup_f32 +// GFX700: v_bfi_b32 + +// GFX803: v_max_f16 +// GFX803: v_rcp_f32 +// GFX803: v_mul_f32 +// GFX803: v_fma_f16 +// GFX803: v_cmp_o_f16 +// GFX803: v_bfi_b32 +kernel void test_atan2pi_f16(global half* restrict out, global half* restrict in0, global half* restrict in1) { + int id = get_local_id(0); + out[id] = atan2pi(in0[id], in1[id]); +} diff --git a/amd/device-libs/test/compile/atomic_work_item_fence.cl b/amd/device-libs/test/compile/atomic_work_item_fence.cl new file mode 100644 index 0000000000000..dde77f9e8bba1 --- /dev/null +++ b/amd/device-libs/test/compile/atomic_work_item_fence.cl @@ -0,0 +1,52 @@ +// Check that the cl_mem_fence_flags is honored. + +// GCN: @test_local() +// GCN-NEXT: entry: +// GCN-NEXT: fence syncscope("agent") acq_rel, !mmra ![[LOCAL_MMRA:[0-9]+]] +// GCN-NEXT: ret void +kernel void test_local() { + atomic_work_item_fence(CLK_LOCAL_MEM_FENCE, memory_order_acq_rel, memory_scope_device); +} + +// GCN: @test_image() +// GCN-NEXT: entry: +// GCN-NEXT: fence syncscope("agent") acq_rel, !mmra ![[GLOBAL_MMRA:[0-9]+]] +// GCN-NEXT: ret void +kernel void test_image() { + atomic_work_item_fence(CLK_IMAGE_MEM_FENCE, memory_order_acq_rel, memory_scope_device); +} + +// GCN: @test_global() +// GCN-NEXT: entry: +// GCN-NEXT: fence syncscope("agent") acq_rel, !mmra ![[GLOBAL_MMRA:[0-9]+]] +// GCN-NEXT: ret void +kernel void test_global() { + atomic_work_item_fence(CLK_GLOBAL_MEM_FENCE, memory_order_acq_rel, memory_scope_device); +} + +// GCN: @test_local_global() +// GCN-NEXT: entry: +// GCN-NEXT: fence syncscope("agent") acq_rel{{$}} +// GCN-NEXT: ret void +kernel void test_local_global() { + atomic_work_item_fence(CLK_GLOBAL_MEM_FENCE | CLK_LOCAL_MEM_FENCE, memory_order_acq_rel, memory_scope_device); +} + +// GCN: @test_all() +// GCN-NEXT: entry: +// GCN-NEXT: fence syncscope("agent") acq_rel{{$}} +// GCN-NEXT: ret void +kernel void test_all() { + atomic_work_item_fence(CLK_IMAGE_MEM_FENCE | CLK_GLOBAL_MEM_FENCE | CLK_LOCAL_MEM_FENCE, memory_order_acq_rel, memory_scope_device); +} + +// GCN: @test_invalid() +// GCN-NEXT: entry: +// GCN-NEXT: fence syncscope("agent") acq_rel{{$}} +// GCN-NEXT: ret void +kernel void test_invalid() { + atomic_work_item_fence(0, memory_order_acq_rel, memory_scope_device); +} + +// GCN: ![[LOCAL_MMRA]] = !{!"amdgpu-as", !"local"} +// GCN: ![[GLOBAL_MMRA]] = !{!"amdgpu-as", !"global"} diff --git a/amd/device-libs/test/compile/fract.cl b/amd/device-libs/test/compile/fract.cl new file mode 100644 index 0000000000000..0b56b2fa5484e --- /dev/null +++ b/amd/device-libs/test/compile/fract.cl @@ -0,0 +1,119 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +// CHECK-LABEL: test_fract_f16 +// GFX600-DAG: s_add_u32 +// GFX600-DAG: s_addc_u32 +// GFX600: buffer_load_ushort +// GFX600-DAG: v_lshlrev_b32 +// GFX600-DAG: v_mov_b32 +// GFX600-DAG: s_mov_b32 +// GFX600-DAG: s_mov_b32 +// GFX600: s_waitcnt +// GFX600: buffer_store_short + + +// TODO: Could promote the f16 pattern to f32 +// GFX700-DAG: s_add_i32 +// GFX700-DAG: s_lshr_b32 +// GFX700-DAG: s_add_u32 +// GFX700-DAG: s_addc_u32 +// GFX700: buffer_load_ushort +// GFX700-DAG: s_load_dwordx2 +// GFX700-DAG: v_lshlrev_b32 +// GFX700-DAG: s_mov_b32 +// GFX700-DAG: s_waitcnt +// GFX700-DAG: v_mov_b32 +// GFX700-DAG: v_add_i32 +// GFX700-DAG: v_addc_u32 +// GFX700: s_waitcnt +// GFX700: flat_store_short + + +// GFX803: flat_load_ushort [[VAL:v[0-9]+]] +// GFX803-DAG: v_floor_f16_e32 [[FLOOR:v[0-9]+]], [[VAL]] +// GFX803-DAG: v_fract_f16_e32 [[FRACT:v[0-9]+]], [[VAL]] +// GFX803-DAG: s_movk_i32 [[INF:s[0-9]+]], 0x7c00 +// GFX803: v_cmp_neq_f16_e64 [[FINITE:(vcc)?(s\[[[[0-9]+:[0-9]+\]]])?]], |[[VAL]]|, [[INF]] +// GFX803: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 0, [[FRACT]] +// GFX803: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[FLOOR]] +// GFX803: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[SELECT]] +kernel void test_fract_f16(global half* restrict out0, + global half* restrict out1, + global half* restrict in) { + int id = get_local_id(0); + out0[id] = fract(in[id], &out1[id]); +} + +// CHECK-LABEL: test_fract_f32 +// GFX600-DAG: v_floor_f32 +// GFX600-DAG: v_sub_f32 +// GFX600-DAG: v_min_f32_e32 v{{[0-9]+}}, 0x3f7fffff, +// GFX600-DAG: v_cmp_u_f32 +// GFX600-DAG: v_cndmask_b32 +// GFX600-DAG: v_cmp_neq_f32 +// GFX600-DAG: v_cndmask_b32 + + +// GFX803: flat_load_dword [[VAL:v[0-9]+]] +// GFX803-DAG: v_floor_f32_e32 [[FLOOR:v[0-9]+]], [[VAL]] +// GFX803-DAG: v_fract_f32_e32 [[FRACT:v[0-9]+]], [[VAL]] +// GFX803-DAG: s_mov_b32 [[INF:s[0-9]+]], 0x7f800000 +// GFX803: v_cmp_neq_f32_e64 [[FINITE:(vcc)?(s\[[[[0-9]+:[0-9]+\]]])?]], |[[VAL]]|, [[INF]] +// GFX803: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], 0, [[FRACT]] +// GFX803: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FLOOR]] +// GFX803: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[SELECT]] +kernel void test_fract_f32(global float* restrict out0, + global float* restrict out1, + global float* restrict in) { + int id = get_local_id(0); + out0[id] = fract(in[id], &out1[id]); +} + +// CHECK-LABEL: test_fract_f64 + +// Fract is used in floor expansion, not directly for fract +// GFX600: v_fract_f64_e32 +// GFX600: v_cmp_class_f64_e64 +// GFX600: v_min_f64 +// GFX600: v_cndmask_b32 +// GFX600: v_cndmask_b32 +// GFX600: v_add_f64 +// GFX600: v_cmp_u_f64 +// GFX600: v_add_f64 +// GFX600: v_min_f64 +// GFX600: v_cmp_neq_f64 + + +// GFX700: flat_load_dwordx2 [[VAL:v[[0-9]+:[0-9]+]]] +// GFX700-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[VAL]] + +// GFX700-DAG: v_fract_f64_e32 v{{\[}}[[FRACT_LO:[0-9]+]]:[[FRACT_HI:[0-9]+]]{{\]}}, [[VAL]] + +// GFX700-DAG: s_mov_b32 s[[INF_HI:[0-9]+]], 0x7ff00000 +// GFX700-DAG: s_mov_b32 s[[INF_LO:[0-9]+]], 0{{$}} +// GFX700-DAG: v_cmp_neq_f64_e64 [[FINITE:(vcc)?(s\[[[[0-9]+:[0-9]+\]]])?]], |[[VAL]]|, s{{\[}}[[INF_LO]]:[[INF_HI]]{{\]}} + +// GFX700-DAG: v_cndmask_b32_e32 v[[SELECT0:[0-9]+]], 0, v[[FRACT_LO]] +// GFX700-DAG: v_cndmask_b32_e32 v[[SELECT1:[0-9]+]], 0, v[[FRACT_HI]] +// GFX700: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[FLOOR]] +// GFX700: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SELECT0]]:[[SELECT1]]{{\]}} + + +// GFX803: flat_load_dwordx2 [[VAL:v[[0-9]+:[0-9]+]]] +// GFX803-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[VAL]] +// GFX803-DAG: v_fract_f64_e32 v{{\[}}[[FRACT_LO:[0-9]+]]:[[FRACT_HI:[0-9]+]]{{\]}}, [[VAL]] + +// GFX803-DAG: s_mov_b32 s[[INF_HI:[0-9]+]], 0x7ff00000 +// GFX803-DAG: s_mov_b32 s[[INF_LO:[0-9]+]], 0{{$}} +// GFX803-DAG: v_cmp_neq_f64_e64 [[FINITE:(vcc)?(s\[[[[0-9]+:[0-9]+\]]])?]], |[[VAL]]|, s{{\[}}[[INF_LO]]:[[INF_HI]]{{\]}} + +// GFX803-DAG: v_cndmask_b32_e32 v[[SELECT0:[0-9]+]], 0, v[[FRACT_LO]] +// GFX803-DAG: v_cndmask_b32_e32 v[[SELECT1:[0-9]+]], 0, v[[FRACT_HI]] +// GFX803: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[FLOOR]] +// GFX803: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SELECT0]]:[[SELECT1]]{{\]}} +kernel void test_fract_f64(global double* restrict out0, + global double* restrict out1, + global double* restrict in) { + int id = get_local_id(0); + out0[id] = fract(in[id], &out1[id]); +} diff --git a/amd/device-libs/test/compile/frexp.cl b/amd/device-libs/test/compile/frexp.cl new file mode 100644 index 0000000000000..b89c6b7b559b5 --- /dev/null +++ b/amd/device-libs/test/compile/frexp.cl @@ -0,0 +1,53 @@ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +// Test that a hardware bug is worked around for gfx6, not applied +// later. + +// GCN-LABEL: {{^}}test_frexp_f32: + +// GFX600-DAG: s_movk_i32 [[INF:s[0-9]+]], 0x1f8 +// GFX600-DAG: v_frexp_mant_f32{{(_e32)?}} [[MANT:v[0-9]+]], [[SRC:v[0-9]+]] +// GFX600-DAG: v_cmp_class_f32{{(_e64)?}} [[CMP:(vcc|s{{\[[0-9]+:[0-9]+\]}})]], [[SRC]], [[INF]] +// GFX600-DAG: v_frexp_exp_i32_f32{{(_e32)?}} [[EXP:v[0-9]+]], [[SRC]] +// GFX600-DAG: v_cndmask_b32{{(_e32)?|(e64)?}} v{{[0-9]+}}, [[SRC]], [[MANT]], [[CMP]] +// GFX600-DAG: v_cndmask_b32{{(_e32)?|(e64)?}} v{{[0-9]+}}, 0, [[EXP]], [[CMP]] + +// GFX700-NOT: v_cmp_class +// GFX700-DAG: v_frexp_mant_f32{{(_e32)?}} [[MANT:v[0-9]+]], [[SRC:v[0-9]+]] +// GFX700-DAG: v_frexp_exp_i32_f32{{(_e32)?}} [[EXP:v[0-9]+]], [[SRC:v[0-9]+]] +// GFX700-NOT: v_cmp_class +kernel void test_frexp_f32(global float* restrict out0, + global int* restrict out1, + global float* restrict in) { + int id = get_local_id(0); + + int exponent; + out0[id] = frexp(in[id], &exponent); + out1[id] = exponent; +} + +// GCN-LABEL: {{^}}test_frexp_f64: +// GFX600: s_mov_b32 s{{[0-9]+}}, 0{{$}} + +// GFX600-DAG: s_movk_i32 [[INF:s[0-9]+]], 0x1f8 +// GFX600-DAG: v_frexp_mant_f64{{(_e32)?}} v{{\[}}[[MANT_LO:[0-9]+]]:[[MANT_HI:[0-9]+]]{{\]}}, [[SRC:v\[[0-9]+:[0-9]+\]]] +// GFX600-DAG: v_cmp_class_f64{{(_e64)?}} [[CMP:(vcc|s{{\[[0-9]+:[0-9]+\]}})]], [[SRC]], [[INF]] +// GFX600-DAG: v_frexp_exp_i32_f64{{(_e32)?}} [[EXP:v[0-9]+]], [[SRC]] +// GFX600-DAG: v_cndmask_b32{{(_e32)?|(e64)?}} v{{[0-9]+}}, v{{[0-9]+}}, v[[MANT_HI]], [[CMP]] +// GFX600-DAG: v_cndmask_b32{{(_e32)?|(e64)?}} v{{[0-9]+}}, v{{[0-9]+}}, v[[MANT_LO]], [[CMP]] +// GFX600-DAG: v_cndmask_b32{{(_e32)?|(e64)?}} v{{[0-9]+}}, 0, [[EXP]], [[CMP]] + +// GFX700-NOT: v_cmp_class +// GFX700-DAG: v_frexp_mant_f64 +// GFX700-DAG: v_frexp_exp_i32_f64 +// GFX700-NOT: v_cmp_class +kernel void test_frexp_f64(global double* restrict out0, + global int* restrict out1, + global double* restrict in) { + int id = get_local_id(0); + + int exponent; + out0[id] = frexp(in[id], &exponent); + out1[id] = exponent; +} diff --git a/amd/device-libs/test/compile/lgamma_r.cl b/amd/device-libs/test/compile/lgamma_r.cl new file mode 100644 index 0000000000000..56d1ba15f761f --- /dev/null +++ b/amd/device-libs/test/compile/lgamma_r.cl @@ -0,0 +1,103 @@ +// Verify lgamma_r function constant folds to correct values. +// Run with filecheck from test cmake + +__attribute__((always_inline)) +static float test_lgamma_r(float val, volatile global int* sign_out) { + int tmp; + float result = lgamma_r(val, &tmp); + *sign_out = tmp; + return result; +} + +// CHECK-LABEL: {{^}}constant_fold_lgamma_r_f32: +// CONSTANTFOLD-LABEL: @constant_fold_lgamma_r_f32( +kernel void constant_fold_lgamma_r_f32(volatile global float* out, + volatile global int* sign_out) { + // CONSTANTFOLD: store volatile i32 0, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF0000000000000 + out[0] = test_lgamma_r(0.0f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 0, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF0000000000000 + out[0] = test_lgamma_r(-0.0f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 0, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF8000000000000, + out[0] = test_lgamma_r(__builtin_nanf(""), sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 0, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF4000000000000, + out[0] = test_lgamma_r(__builtin_nansf(""), sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF0000000000000, + out[0] = test_lgamma_r(__builtin_inff(), sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 0, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF0000000000000, + out[0] = test_lgamma_r(-__builtin_inff(), sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0x419DE28020000000, + out[0] = test_lgamma_r(0x1.0p+23f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 0, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF0000000000000, + out[0] = test_lgamma_r(-0x1.0p+23f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0.000000e+00, + out[0] = test_lgamma_r(1.0f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0.000000e+00, + out[0] = test_lgamma_r(2.0f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0x3FE62E4300000000, + out[0] = test_lgamma_r(3.0f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0x3FE250D040000000, + out[0] = test_lgamma_r(0.5f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0x405601E680000000, + out[0] = test_lgamma_r(0x1.0p-127f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0x419DE28060000000, + out[0] = test_lgamma_r(nextafter(0x1.0p+23f, __builtin_inff()), sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0x419DE28000000000, + out[0] = test_lgamma_r(nextafter(0x1.0p+23f, -__builtin_inff()), sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0xC19DE28040000000, + out[0] = test_lgamma_r(nextafter(-0x1.0p+23f, __builtin_inff()), sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 0, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF0000000000000, + out[0] = test_lgamma_r(nextafter(-0x1.0p+23f, -__builtin_inff()), sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 0, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF0000000000000, + out[0] = test_lgamma_r(-1.0f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 0, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF0000000000000, + out[0] = test_lgamma_r(-2.0f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 0, + // CONSTANTFOLD-NEXT: store volatile float 0x7FF0000000000000, + out[0] = test_lgamma_r(-3.0f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0xBFF4F1B100000000, + out[0] = test_lgamma_r(-3.5f, sign_out); + + // CONSTANTFOLD-NEXT: store volatile i32 1, + // CONSTANTFOLD-NEXT: store volatile float 0xC19DE28040000000, + out[0] = test_lgamma_r(as_float(0xcaffffff), sign_out); +} diff --git a/amd/device-libs/test/compile/native_exp.cl b/amd/device-libs/test/compile/native_exp.cl new file mode 100644 index 0000000000000..91262ef00213c --- /dev/null +++ b/amd/device-libs/test/compile/native_exp.cl @@ -0,0 +1,26 @@ + +// GCN: {{^}}test_native_exp2_f32: +// GCN-NOT: v0 +// GCN: v_exp_f32{{(_e32)?}} v0, v0 +// GCN-NOT: v0 +float test_native_exp2_f32(float arg) { + return native_exp2(arg); +} + +// GCN: {{^}}test_native_exp_f32: +// GCN-NOT: v0 +// GCN: v_mul_f32{{(_e32)?}} v0, 0x3fb8aa3b, v0 +// GCN-NEXT: v_exp_f32{{(_e32)?}} v0, v0 +// GCN-NOT: v0 +float test_native_exp_f32(float arg) { + return native_exp(arg); +} + +// GCN: {{^}}test_native_exp10_f32: +// GCN-NOT: v0 +// GCN: v_mul_f32{{(_e32)?}} v0, 0x40549a78, v0 +// GCN-NEXT: v_exp_f32{{(_e32)?}} v0, v0 +// GCN-NOT: v0 +float test_native_exp10_f32(float arg) { + return native_exp10(arg); +} diff --git a/amd/device-libs/test/compile/native_log.cl b/amd/device-libs/test/compile/native_log.cl new file mode 100644 index 0000000000000..c83c52d0fc8aa --- /dev/null +++ b/amd/device-libs/test/compile/native_log.cl @@ -0,0 +1,27 @@ + +// GCN: {{^}}test_native_log_f32: +// GCN-NOT: v0 +// GCN: v_log_f32{{(_e32)?}} v0, v0 +// GCN-NEXT: v_mul_f32{{(_e32)?}} v0, 0x3f317218, v0 +// GCN-NOT: v0 +float test_native_log_f32(float arg) { + return native_log(arg); +} + +// GCN: {{^}}test_native_log2_f32: +// GCN-NOT: v0 +// GCN: v_log_f32{{(_e32)?}} v0, v0 +// GCN-NOT: v0 +float test_native_log2_f32(float arg) { + return native_log2(arg); +} + +// GCN: {{^}}test_native_log10_f32: +// GCN-NOT: v0 +// GCN: v_log_f32{{(_e32)?}} v0, v0 +// GCN-NEXT: v_mul_f32{{(_e32)?}} v0, 0x3e9a209b, v0 + +// GCN-NOT: v0 +float test_native_log10_f32(float arg) { + return native_log10(arg); +} diff --git a/amd/device-libs/test/compile/native_rcp.cl b/amd/device-libs/test/compile/native_rcp.cl new file mode 100644 index 0000000000000..50777d4e65369 --- /dev/null +++ b/amd/device-libs/test/compile/native_rcp.cl @@ -0,0 +1,35 @@ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +// FIXME: OpenCL's native_recip doesn't seem wired up to the ocml +// functions for f16/f64 + +half __ocml_native_rcp_f16(half); + +// GCN: {{^}}test_native_recip_f16: +// GFX600: v_rcp_f32 +// GFX700: v_rcp_f32 + + +// GFX803: {{(flat|global|buffer)}}_load_{{(ushort|b16)}} [[VAL:v[0-9+]]], +// GFX803-NOT: [[VAL]] +// GFX803: v_rcp_f16{{(_e32)?}} [[RESULT:v[0-9]+]], [[VAL]] +// GFX803-NOT: [[RESULT]] +// GFX803: [[RESULT]] +// GFX803-NOT: [[RESULT]] +kernel void test_native_recip_f16(global half* restrict out, global half* restrict in) { + int id = get_local_id(0); + out[id] = __ocml_native_rcp_f16(in[id]); +} + +// GCN: {{^}}test_native_recip_f32: +// GCN: {{(flat|global|buffer)}}_load_{{(dword|b32)}} [[VAL:v[0-9+]]], +// GCN-NOT: [[VAL]] +// GCN: v_rcp_f32{{(_e32)?}} [[RESULT:v[0-9]+]], [[VAL]] +// GCN-NOT: [[RESULT]] +// GCN: [[RESULT]] +// GCN-NOT: [[RESULT]] +kernel void test_native_recip_f32(global float* restrict out, global float* restrict in) { + int id = get_local_id(0); + out[id] = native_recip(in[id]); +} diff --git a/amd/device-libs/test/compile/native_rsqrt.cl b/amd/device-libs/test/compile/native_rsqrt.cl new file mode 100644 index 0000000000000..ae33d2d3d4b9c --- /dev/null +++ b/amd/device-libs/test/compile/native_rsqrt.cl @@ -0,0 +1,38 @@ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +// FIXME: OpenCL's native_rsqrt doesn't seem wired up to the ocml +// functions for f16/f64 + +half __ocml_native_rsqrt_f16(half); + +// FIXME: Promoted case using full expansion +// GCN-LABEL: {{^}}test_native_rsqrt_f16: +// GFX600: v_sqrt_f32 +// GFX600: v_rcp_f32 + +// GFX700: v_sqrt_f32 +// GFX700: v_rcp_f32 + +// GFX803: {{(flat|global|buffer)}}_load_{{(ushort|b16)}} [[VAL:v[0-9+]]], +// GFX803-NOT: [[VAL]] +// GFX803: v_rsq_f16{{(_e32)?}} [[RESULT:v[0-9]+]], [[VAL]] +// GFX803-NOT: [[RESULT]] +// GFX803: [[RESULT]] +// GFX803-NOT: [[RESULT]] +kernel void test_native_rsqrt_f16(global half* restrict out, global half* restrict in) { + int id = get_local_id(0); + out[id] = __ocml_native_rsqrt_f16(in[id]); +} + +// GCN-LABEL: {{^}}test_native_rsqrt_f32: +// GCN: {{(flat|global|buffer)}}_load_{{(dword|b32)}} [[VAL:v[0-9+]]], +// GCN-NOT: [[VAL]] +// GCN: v_rsq_f32{{(_e32)?}} [[RESULT:v[0-9]+]], [[VAL]] +// GCN-NOT: [[RESULT]] +// GCN: [[RESULT]] +// GCN-NOT: [[RESULT]] +kernel void test_native_rsqrt_f32(global float* restrict out, global float* restrict in) { + int id = get_local_id(0); + out[id] = native_rsqrt(in[id]); +} diff --git a/amd/device-libs/test/compile/rsqrt.cl b/amd/device-libs/test/compile/rsqrt.cl new file mode 100644 index 0000000000000..1a44c1ad539ab --- /dev/null +++ b/amd/device-libs/test/compile/rsqrt.cl @@ -0,0 +1,38 @@ + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +// CHECK-LABEL: {{^}}test_rsqrt_f16: +// CHECK: s_waitcnt +// CHECK-NEXT: v_rsq_f16{{(_e32)?}} v0, v0 +// CHECK-NEXT: s_setpc_b64 +half test_rsqrt_f16(half x) { + return rsqrt(x); +} + +// CHECK-LABEL: {{^}}test_rsqrt_f32: +// IEEE: v_mul_f32 +// IEEE: v_cmp_gt_f32 +// IEEE: v_cndmask_b32 +// IEEE: v_rsq_f32 +// IEEE: v_mul_f32 +// IEEE: v_cndmask_b32 + +// DAZ: s_waitcnt +// DAZ-NEXT: v_rsq_f32{{(_e32)?}} v0, v0 +// DAZ-NEXT: s_setpc_b64 +float test_rsqrt_f32(float x) { + return rsqrt(x); +} + +// CHECK-LABEL: {{^}}test_rsqrt_f64: +// CHECK: v_rsq_f64 +// CHECK: v_mul_f64 +// CHECK: v_fma_f64 +// CHECK: v_mul_f64 +// CHECK: v_fma_f64 +// CHECK: v_fma_f64 +// CHECK: v_cndmask_b32 +// CHECK: v_cndmask_b32 +double test_rsqrt_f64(double x) { + return rsqrt(x); +} diff --git a/amd/device-libs/utils/prepare-builtins/CMakeLists.txt b/amd/device-libs/utils/prepare-builtins/CMakeLists.txt new file mode 100644 index 0000000000000..03a33222fe314 --- /dev/null +++ b/amd/device-libs/utils/prepare-builtins/CMakeLists.txt @@ -0,0 +1,36 @@ +##===-------------------------------------------------------------------------- +## ROCm Device Libraries +## +## This file is distributed under the University of Illinois Open Source +## License. See LICENSE.TXT for details. +##===-------------------------------------------------------------------------- + +cmake_minimum_required(VERSION 3.13.4) + +include(AddLLVM) + +if (ROCM_DEVICELIB_STANDALONE_BUILD) + add_definitions(${LLVM_DEFINITIONS}) + include_directories(${LLVM_INCLUDE_DIR}) + include_directories(${LLVM_CONFIG_INCLUDE_DIR}) + include_directories(${LLVM_MAIN_INCLUDE_DIR}) + + include_directories(${LLVM_INCLUDE_DIRS}) + add_definitions(${LLVM_DEFINITIONS}) + link_directories("${LLVM_LIBRARY_DIR}") +endif() + +add_executable(prepare-builtins prepare-builtins.cpp) +set_target_properties(prepare-builtins PROPERTIES + CXX_STANDARD 17 + CXX_STANDARD_REQUIRED Yes + CXX_EXTENSIONS No) +llvm_update_compile_flags(prepare-builtins) + +if (LLVM_LINK_LLVM_DYLIB) + set(llvm_libs LLVM) +else() + llvm_map_components_to_libnames(llvm_libs support core bitreader bitwriter) +endif() + +target_link_libraries(prepare-builtins ${llvm_libs}) diff --git a/amd/device-libs/utils/prepare-builtins/prepare-builtins.cpp b/amd/device-libs/utils/prepare-builtins/prepare-builtins.cpp new file mode 100644 index 0000000000000..7fc9d06dab7d6 --- /dev/null +++ b/amd/device-libs/utils/prepare-builtins/prepare-builtins.cpp @@ -0,0 +1,117 @@ +/*===-------------------------------------------------------------------------- + * ROCm Device Libraries + * + * This file is distributed under the University of Illinois Open Source + * License. See LICENSE.TXT for details. + *===------------------------------------------------------------------------*/ + +#if !defined(__STDC_LIMIT_MACROS) +# define __STDC_LIMIT_MACROS +#endif +#if !defined(__STDC_CONSTANT_MACROS) +# define __STDC_CONSTANT_MACROS +#endif + +#include "llvm/Bitcode/BitcodeReader.h" +#include "llvm/Bitcode/BitcodeWriter.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/IR/Module.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/ManagedStatic.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Support/ErrorOr.h" +#include "llvm/Support/ToolOutputFile.h" +#include "llvm/Config/llvm-config.h" + +#include + +using namespace llvm; + +static cl::opt +InputFilename(cl::Positional, cl::desc(""), cl::init("-")); + +static cl::opt +OutputFilename("o", cl::desc("Output filename"), + cl::value_desc("filename")); + +int main(int argc, char **argv) { + LLVMContext Context; + llvm_shutdown_obj Y; // Call llvm_shutdown() on exit. + + cl::ParseCommandLineOptions(argc, argv, "bitcode library builtin preparation tool\n"); + + std::string ErrorMessage; + Module *M = nullptr; + + { + ErrorOr> BufferOrErr = + MemoryBuffer::getFile(InputFilename); + if (std::error_code ec = BufferOrErr.getError()) + ErrorMessage = ec.message(); + else { + std::unique_ptr &BufferPtr = BufferOrErr.get(); + Expected> ModuleOrErr = + parseBitcodeFile(BufferPtr.get()->getMemBufferRef(), Context); + if (Error Err = ModuleOrErr.takeError()) { + ErrorMessage = toString(std::move(Err)); + } + else + M = ModuleOrErr.get().release(); + } + } + + if (!M) { + errs() << argv[0] << ": "; + if (ErrorMessage.size()) + errs() << ErrorMessage << "\n"; + else + errs() << "bitcode didn't read correctly.\n"; + return 1; + } + + // Set linkage of every external definition to linkonce_odr. + for (Module::iterator i = M->begin(), e = M->end(); i != e; ++i) { + if (!i->isDeclaration() && i->getLinkage() == GlobalValue::ExternalLinkage) { + i->setLinkage(GlobalValue::LinkOnceODRLinkage); + } + } + + for (Module::global_iterator i = M->global_begin(), e = M->global_end(); + i != e; ++i) { + if (!i->isDeclaration() && i->getLinkage() == GlobalValue::ExternalLinkage) { + i->setLinkage(GlobalValue::LinkOnceODRLinkage); + } + } + + for (Module::alias_iterator i = M->alias_begin(), e = M->alias_end(); + i != e; ++i) { + if (!i->isDeclaration() && i->getLinkage() == GlobalValue::ExternalLinkage) { + i->setLinkage(GlobalValue::LinkOnceODRLinkage); + } + } + + + if (OutputFilename.empty()) { + errs() << "no output file\n"; + return 1; + } + + std::error_code EC; + std::unique_ptr Out + (new ToolOutputFile(OutputFilename, EC, sys::fs::OF_None)); + if (EC) { + errs() << EC.message() << '\n'; + exit(1); + } + + WriteBitcodeToFile(*M, Out->os()); + + // Declare success. + Out->keep(); + return 0; +} + diff --git a/amd/git-hooks/install-merge-hooks b/amd/git-hooks/install-merge-hooks new file mode 100755 index 0000000000000..8254356d0309c --- /dev/null +++ b/amd/git-hooks/install-merge-hooks @@ -0,0 +1,24 @@ +#!/bin/bash + +pushd() { + command pushd "$@" > /dev/null +} + +popd() { + command popd "$@" > /dev/null +} + +GIT_DIR=$(git rev-parse --git-dir) +ROOT_DIR=$(git rev-parse --show-toplevel) + +pushd ${GIT_DIR}/hooks + +rm --force post-merge +rm --force pre-commit +rm --force llvm-main-revision + +ln --relative --symbolic ${ROOT_DIR}/amd/git-hooks/post-merge post-merge +ln --relative --symbolic ${ROOT_DIR}/amd/git-hooks/pre-commit pre-commit +ln --relative --symbolic ${ROOT_DIR}/amd/git-hooks/llvm-main-revision llvm-main-revision + +popd diff --git a/amd/git-hooks/llvm-main-revision b/amd/git-hooks/llvm-main-revision new file mode 100755 index 0000000000000..f1d5b7de2d48c --- /dev/null +++ b/amd/git-hooks/llvm-main-revision @@ -0,0 +1,34 @@ +#!/bin/sh + +ACTION_TYPE=$1 +if test -z "$ACTION_TYPE"; then + exit 0 +fi + +if test "$ACTION_TYPE" = "pre-commit"; then + MERGE=$(git rev-parse --quiet --verify MERGE_HEAD) + if test -z "$MERGE"; then + exit 0 + fi + FETCH=$(git rev-parse --quiet --verify FETCH_HEAD) + if test "$MERGE" != "$FETCH"; then + exit 0 + fi +fi + +#disable automatic llvm-config.h.cmake LLVM_MAIN_REVISION update +exit 0 + +LLVM_CONFIG_H_CMAKE_PATH="llvm/include/llvm/Config/llvm-config.h.cmake" + +FETCH_HASH=$(git log --oneline --format='%h' --max-count=1 FETCH_HEAD) +COMMIT_REVISION=$(git rev-list --count $(git merge-base HEAD ${FETCH_HASH})) + +sed --in-place 's/^#define LLVM_MAIN_REVISION .*$/#define LLVM_MAIN_REVISION '${COMMIT_REVISION}'/' ${LLVM_CONFIG_H_CMAKE_PATH} +git add ${LLVM_CONFIG_H_CMAKE_PATH} +if test "$ACTION_TYPE" = "post-merge"; then + GIT_DIR=$(git rev-parse --git-dir) + rm --force ${GIT_DIR}/MERGE_HEAD + + git commit --amend --no-edit +fi diff --git a/amd/git-hooks/post-merge b/amd/git-hooks/post-merge new file mode 100755 index 0000000000000..a80e4d2886bb6 --- /dev/null +++ b/amd/git-hooks/post-merge @@ -0,0 +1,6 @@ +#!/bin/sh + +. git-sh-setup +test -x "$GIT_DIR/hooks/llvm-main-revision" && + exec "$GIT_DIR/hooks/llvm-main-revision" "post-merge" +: diff --git a/amd/git-hooks/pre-commit b/amd/git-hooks/pre-commit new file mode 100755 index 0000000000000..ba6e574951ae9 --- /dev/null +++ b/amd/git-hooks/pre-commit @@ -0,0 +1,6 @@ +#!/bin/sh + +. git-sh-setup +test -x "$GIT_DIR/hooks/llvm-main-revision" && + exec "$GIT_DIR/hooks/llvm-main-revision" "pre-commit" +: diff --git a/amd/hipcc/.gitignore b/amd/hipcc/.gitignore new file mode 100644 index 0000000000000..3c2e3103578a1 --- /dev/null +++ b/amd/hipcc/.gitignore @@ -0,0 +1,17 @@ +# Merge files created by git. +*.orig +# Reject files created by patch. +*.rej + +# Nested build directory. +/build* + +# documentation artifacts +build/ +_build/ +_images/ +_static/ +_templates/ +_toc.yml +docBin/ +_doxygen/ diff --git a/amd/hipcc/.readthedocs.yaml b/amd/hipcc/.readthedocs.yaml new file mode 100644 index 0000000000000..523980fe04cd0 --- /dev/null +++ b/amd/hipcc/.readthedocs.yaml @@ -0,0 +1,31 @@ +# Read the Docs configuration file +# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details + +version: 2 + +sphinx: + configuration: amd/hipcc/docs/conf.py + +formats: [htmlzip, pdf, epub] + +python: + install: + - requirements: amd/hipcc/docs/sphinx/requirements.txt + +build: + os: ubuntu-22.04 + tools: + python: "3.10" + jobs: + post_checkout: + # Cancel building pull requests when there aren't changed in the docs directory or YAML file. + # You can add any other files or directories that you'd like here as well, + # like your docs requirements file, or other files that will change your docs build. + # + # If there are no changes (git diff exits with 0) we force the command to return with 183. + # This is a special exit code on Read the Docs that will cancel the build immediately. + - | + if [ "$READTHEDOCS_VERSION_TYPE" = "external" ] && git diff --quiet origin/amd-staging -- docs/ .readthedocs.yaml; + then + exit 183; + fi diff --git a/amd/hipcc/CMakeLists.txt b/amd/hipcc/CMakeLists.txt new file mode 100755 index 0000000000000..ca09a04538c61 --- /dev/null +++ b/amd/hipcc/CMakeLists.txt @@ -0,0 +1,215 @@ +cmake_minimum_required(VERSION 3.13.4) +if(POLICY CMP0177) + cmake_policy(SET CMP0177 NEW) +endif() + +project(hipcc VERSION "1.1.1" LANGUAGES C CXX) + +include(CMakePackageConfigHelpers) +include(GNUInstallDirs) + +# Generate static package, when BUILD_SHARED_LIBS is set to OFF. +# Default to ON +option(BUILD_SHARED_LIBS "Build using shared libraries" ON) + +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_CXX_STANDARD_REQUIRED True) + +set(ADDITIONAL_SHARED_LIBRARIES_TO_LINK + libstdc++fs.so) + +set(HIPCC_BIN + hipcc) +set(HIPCC_SOURCES + src/hipcc.cpp + src/utils.cpp +) + +set(HIPCONFIG_BIN + hipconfig) +set(HIPCONFIG_SOURCES + src/hipconfig.cpp + src/utils.cpp +) + +add_executable(${HIPCC_BIN} ${HIPCC_SOURCES}) +if(NOT WIN32) + # C++17 does not require std lib linking. + target_link_libraries(${HIPCC_BIN} ${ADDITIONAL_SHARED_LIBRARIES_TO_LINK}) +endif() + +add_executable(${HIPCONFIG_BIN} ${HIPCONFIG_SOURCES}) +if(NOT WIN32) + # C++17 does not require std lib linking. + target_link_libraries(${HIPCONFIG_BIN} ${ADDITIONAL_SHARED_LIBRARIES_TO_LINK}) +endif() + +# Copy scripts and batch files to build directory. +file(COPY ${PROJECT_SOURCE_DIR}/bin/ DESTINATION ${PROJECT_BINARY_DIR}) + +# Packaging: +set(CPACK_RPM_COMPONENT_INSTALL ON) +set(CPACK_ARCHIVE_COMPONENT_INSTALL ON) +set(CPACK_COMPONENTS_ALL AMD NVIDIA) +set(CPACK_GENERATOR "DEB;RPM;ZIP" CACHE STRING "Default packaging generators") +set(CPACK_PACKAGE_CONTACT "ROCm Compiler Support ") +set(CPACK_PACKAGE_DESCRIPTION "HIP Compiler Driver") +set(CPACK_PACKAGE_NAME "${PROJECT_NAME}") +set(CPACK_PACKAGE_VENDOR "Advanced Micro Devices, Inc.") +set(CPACK_PACKAGE_VERSION_MAJOR "${hipcc_VERSION_MAJOR}") +set(CPACK_PACKAGE_VERSION_MINOR "${hipcc_VERSION_MINOR}") +set(CPACK_PACKAGE_VERSION_PATCH "${hipcc_VERSION_PATCH}") +set(CPACK_RESOURCE_FILE_LICENSE "${CMAKE_CURRENT_SOURCE_DIR}/LICENSE.txt") + +# Debian specific packaging variables. +set(CPACK_DEBIAN_ENABLE_COMPONENT_DEPENDS ON) +set(CPACK_DEB_COMPONENT_INSTALL ON) +set(CPACK_DEBIAN_FILE_NAME "DEB-DEFAULT") +set(CPACK_DEBIAN_PACKAGE_DEPENDS "rocm-core") +set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/ROCm/llvm-project/tree/amd-staging/amd/hipcc") +if(DEFINED ENV{CPACK_DEBIAN_PACKAGE_RELEASE}) + set(CPACK_DEBIAN_PACKAGE_RELEASE $ENV{CPACK_DEBIAN_PACKAGE_RELEASE}) +else() + set(CPACK_DEBIAN_PACKAGE_RELEASE "local") +endif() + +# AMD specific Debian packaging varibles. +set(CPACK_DEBIAN_AMD_PACKAGE_NAME "hipcc") +set(CPACK_DEBIAN_AMD_PACKAGE_DEPENDS "rocm-core, rocm-llvm") + +# NVIDIA specific Debian packaging variables. +set(CPACK_DEBIAN_NVIDIA_PACKAGE_NAME "hipcc-nvidia") +set(CPACK_DEBIAN_NVIDIA_PACKAGE_DEPENDS "rocm-core") # for NVIDIA we don't need to add rocm-llvm as a dependency + + +# RPM specific packaging variables. +set(CPACK_RPM_FILE_NAME "RPM-DEFAULT") +set(CPACK_RPM_PACKAGE_LICENSE "MIT") +set(CPACK_RPM_PACKAGE_REQUIRES "rocm-core") +set(CPACK_RPM_PACKAGE_AUTOREQPROV 0) +if(DEFINED ENV{CPACK_RPM_PACKAGE_RELEASE}) + set(CPACK_RPM_PACKAGE_RELEASE $ENV{CPACK_RPM_PACKAGE_RELEASE}) +else() + set(CPACK_RPM_PACKAGE_RELEASE "local") +endif() +if(CPACK_RPM_PACKAGE_RELEASE) + set(CPACK_RPM_PACKAGE_RELEASE_DIST ON) +endif() + +# AMD specific RPM packaging varibables. +set(CPACK_RPM_AMD_PACKAGE_NAME "hipcc") +set(CPACK_RPM_AMD_PACKAGE_REQUIRES "rocm-core, rocm-llvm") + +# NVIDIA specific RPM packaging variables. +set(CPACK_RPM_NVIDIA_PACKAGE_NAME "hipcc-nvidia") +set(CPACK_RPM_NVIDIA_PACKAGE_REQUIRES "rocm-core") # for NVIDIA we don't need to add rocm-llvm as a dependency + +# ROCM versioning. +set(ROCM_VERSION_FOR_PACKAGE "") +if(DEFINED ENV{ROCM_LIBPATCH_VERSION}) + set(ROCM_VERSION_FOR_PACKAGE $ENV{ROCM_LIBPATCH_VERSION}) +elseif(DEFINED ENV{ROCM_VERSION}) + string(REGEX REPLACE "." "" ROCM_VERSION_FOR_PACKAGE $ENV{ROCM_VERSION}) +else() + set(ROCM_VERSION_FOR_PACKAGE "99999") +endif() +set(CPACK_PACKAGE_VERSION "${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}.${ROCM_VERSION_FOR_PACKAGE}") + +# Exclude Windows specific BAT scripts from install/packaging for Linux. +if (NOT WIN32) + # AMD specific. + file(GLOB install_bin_files "${CMAKE_CURRENT_SOURCE_DIR}/bin/*") + foreach(ITEM ${install_bin_files}) + # Exclude *.bat files + if(NOT "${ITEM}" MATCHES ".bat$") + # For *.pm files not require binary permissions + if("${ITEM}" MATCHES ".pm$") + LIST( APPEND gen_files "${ITEM}" ) + else() + LIST( APPEND bin_files "${ITEM}" ) + endif() + endif() + endforeach() + # Install with right type and Permissions + install(PROGRAMS ${bin_files} + DESTINATION ./bin + COMPONENT AMD) + install(FILES ${gen_files} + DESTINATION ./bin + COMPONENT AMD) + + # NVIDIA specific. + install(PROGRAMS ${bin_files} + DESTINATION ./bin + COMPONENT NVIDIA) + install(FILES ${gen_files} + DESTINATION ./bin + COMPONENT NVIDIA) +else () + # AMD specific. + install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/bin + DESTINATION . + USE_SOURCE_PERMISSIONS + DIRECTORY_PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE + COMPONENT AMD) + + # NVIDIA specific. + install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/bin + DESTINATION . + USE_SOURCE_PERMISSIONS + DIRECTORY_PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE + COMPONENT NVIDIA) +endif() + +# AMD specific. +install(FILES + "LICENSE.txt" + "README.md" + COMPONENT AMD + DESTINATION ${CMAKE_INSTALL_DOCDIR}) +install(TARGETS ${HIPCC_BIN} + COMPONENT AMD + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) +install(TARGETS ${HIPCONFIG_BIN} + COMPONENT AMD + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) + +# NVIDIA specific. +install(FILES + "LICENSE.txt" + "README.md" + COMPONENT NVIDIA + DESTINATION ${CMAKE_INSTALL_DOCDIR}) +install(TARGETS ${HIPCC_BIN} + COMPONENT NVIDIA + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) +install(TARGETS ${HIPCONFIG_BIN} + COMPONENT NVIDIA + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) + +# TODO: WIN32 check need to be removed if backward +# compatibility is required for WIN32. +option(HIPCC_BACKWARD_COMPATIBILITY "Enable HIPCC backward compatibility" ON) +if(NOT WIN32) + if(HIPCC_BACKWARD_COMPATIBILITY) + include(hipcc-backward-compat.cmake) + endif() +endif() + +if(NOT ROCM_DEP_ROCMCORE) + string(REGEX REPLACE ",? ?rocm-core" "" CPACK_DEBIAN_PACKAGE_DEPENDS ${CPACK_DEBIAN_PACKAGE_DEPENDS}) + string(REGEX REPLACE ",? ?rocm-core" "" CPACK_DEBIAN_AMD_PACKAGE_DEPENDS ${CPACK_DEBIAN_AMD_PACKAGE_DEPENDS}) + string(REGEX REPLACE ",? ?rocm-core" "" CPACK_DEBIAN_NVIDIA_PACKAGE_DEPENDS ${CPACK_DEBIAN_NVIDIA_PACKAGE_DEPENDS}) + string(REGEX REPLACE ",? ?rocm-core" "" CPACK_RPM_PACKAGE_REQUIRES ${CPACK_RPM_PACKAGE_REQUIRES}) + string(REGEX REPLACE ",? ?rocm-core" "" CPACK_RPM_AMD_PACKAGE_REQUIRES ${CPACK_RPM_AMD_PACKAGE_REQUIRES}) + string(REGEX REPLACE ",? ?rocm-core" "" CPACK_RPM_NVIDIA_PACKAGE_REQUIRES ${CPACK_RPM_NVIDIA_PACKAGE_REQUIRES}) +endif() + +# Static packaging +if(NOT BUILD_SHARED_LIBS) + # For static builds change the pakage name + set(CPACK_DEBIAN_AMD_PACKAGE_NAME "hipcc-static-dev") + set(CPACK_RPM_AMD_PACKAGE_NAME "hipcc-static-devel") +endif() + +include(CPack) diff --git a/amd/hipcc/LICENSE.txt b/amd/hipcc/LICENSE.txt new file mode 100644 index 0000000000000..a8d7060d447c6 --- /dev/null +++ b/amd/hipcc/LICENSE.txt @@ -0,0 +1,19 @@ +Copyright (c) 2008 - 2025 Advanced Micro Devices, Inc. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/amd/hipcc/README.md b/amd/hipcc/README.md new file mode 100644 index 0000000000000..6231739a13c6f --- /dev/null +++ b/amd/hipcc/README.md @@ -0,0 +1,80 @@ +# HIP compiler driver (hipcc) + +## Table of Contents + + + +- [hipcc](#hipcc) + - [Documentation](#documentation) + - [Environment Variables](#envVar) + - [Usage](#usage) + - [Building](#building) + - [Testing](#testing) + + + +## hipcc + +`hipcc` is a compiler driver utility that will call clang or nvcc, depending on target, and pass the appropriate include and library options for the target compiler and HIP infrastructure. + +`hipcc` will pass-through options to the target compiler. The tools calling hipcc must ensure the compiler options are appropriate for the target compiler. + +### Building + +Building on Linux: + +```bash +mkdir build +cd build + +cmake .. + +make -j4 +``` + +The hipcc and hipconfig executables are created in the current build folder. +You may also create installable packages with : +```bash +make package +``` + +## Documentation + +The published documentation is available at [HIPCC](https://rocm.docs.amd.com/projects/HIPCC/en/latest/index.html) in an organized, easy-to-read format, with search and a table of contents. The documentation source files reside in the `amd/HIPCC/docs` folder of this repository. As with all ROCm projects, the documentation is open source. For more information on contributing to the documentation, see [Contribute to ROCm documentation](https://rocm.docs.amd.com/en/latest/contribute/contributing.html). + +Run the steps below to build documentation locally. + +```shell +cd docs + +pip3 install -r sphinx/requirements.txt + +python3 -m sphinx -T -E -b html -d _build/doctrees -D language=en . _build/html +``` + +### Environment Variables + +The environment variable HIP_PLATFORM may be used to specify amd/nvidia: + +- HIP_PLATFORM='amd' or HIP_PLATFORM='nvidia'. +- If HIP_PLATFORM is not set, then hipcc will attempt to auto-detect based on if nvcc is found. + +Other environment variable controls: + +- CUDA_PATH : Path to CUDA SDK (default /usr/local/cuda). Used on NVIDIA platforms only. + +### Usage + +The built executables can be used the same way as the hipcc/hipconfig perl scripts. +To use the newly built executables from the build folder use ./ in front of the executable name - +Example: +```shell +./hipconfig --help +./hipcc --help +./hipcc --version +./hipconfig --full +``` + +### hipcc: testing + +Currently hipcc/hipconfig executables are tested by building and executing HIP tests: https://github.com/ROCm/hip-tests diff --git a/amd/hipcc/bin/hipcc.bat b/amd/hipcc/bin/hipcc.bat new file mode 100755 index 0000000000000..cfce96a308ab9 --- /dev/null +++ b/amd/hipcc/bin/hipcc.bat @@ -0,0 +1,2 @@ +@set HIPCC="%~dp0hipcc" +%HIPCC% %* diff --git a/amd/hipcc/bin/hipconfig.bat b/amd/hipcc/bin/hipconfig.bat new file mode 100755 index 0000000000000..de76095e31cae --- /dev/null +++ b/amd/hipcc/bin/hipconfig.bat @@ -0,0 +1,2 @@ +@set HIPCONFIG="%~dp0hipconfig" +%HIPCONFIG% %* diff --git a/amd/hipcc/docs/build.rst b/amd/hipcc/docs/build.rst new file mode 100644 index 0000000000000..4cdd7d5f7f36c --- /dev/null +++ b/amd/hipcc/docs/build.rst @@ -0,0 +1,28 @@ +.. meta:: + :description: Building HIPCC from source files + :keywords: HIPCC, ROCm, HIP tools, HIP compiler + +.. _hipcc_build: + +****************************************** +Building and testing HIPCC +****************************************** + +To build the ``hipcc`` and ``hipconfig`` executables, use the following commands. + +.. code-block:: bash + + mkdir build + cd build + + cmake .. + + make -j + +.. note:: + The tools are created in the current build folder, and will need to be copied to ``/opt/rocm/hip/bin`` folder location. + +Testing HIPCC +============= + +Currently ``hipcc`` and ``hipconfig`` tools are tested by building and running test samples that can be found at `HIP-tests `_. diff --git a/amd/hipcc/docs/conf.py b/amd/hipcc/docs/conf.py new file mode 100644 index 0000000000000..181f77c3d9414 --- /dev/null +++ b/amd/hipcc/docs/conf.py @@ -0,0 +1,31 @@ +# Configuration file for the Sphinx documentation builder. +# +# This file only contains a selection of the most common options. For a full +# list see the documentation: +# https://www.sphinx-doc.org/en/master/usage/configuration.html + +import re + +from rocm_docs import ROCmDocs + +with open('../CMakeLists.txt', encoding='utf-8') as f: + match = re.search(r'.*\bproject\(hipcc VERSION\s+\"?([0-9.]+)[^0-9.]+', f.read()) + if not match: + raise ValueError("VERSION not found!") + version_number = match[1] +left_nav_title = f"HIPCC {version_number} Documentation" + +# for PDF output on Read the Docs +project = "HIPCC Documentation" +author = "Advanced Micro Devices, Inc." +copyright = "Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved." +version = version_number +release = version_number + +external_toc_path = "./sphinx/_toc.yml" + +docs_core = ROCmDocs(left_nav_title) +docs_core.setup() + +for sphinx_var in ROCmDocs.SPHINX_VARS: + globals()[sphinx_var] = getattr(docs_core, sphinx_var) diff --git a/amd/hipcc/docs/env.rst b/amd/hipcc/docs/env.rst new file mode 100644 index 0000000000000..92c5b17fe86e2 --- /dev/null +++ b/amd/hipcc/docs/env.rst @@ -0,0 +1,65 @@ +.. meta:: + :description: HIPCC environment variables + :keywords: HIPCC, ROCm, HIP tools, HIP compiler + +.. _hipcc_vars: + +****************************************** +HIPCC environment variables +****************************************** + +This topic provides descriptions of the HIPCC environment +variables. For more information about other ROCm environment variables, see +`HIP environment variables `_. + +.. list-table:: + :header-rows: 1 + :widths: 50,50 + + * - Environment variable + - Value + + * - | ``HIP_PLATFORM`` + | The platform targeted by HIP. If ``HIP_PLATFORM`` isn't set, then :doc:`HIPCC ` attempts to auto-detect the platform based on whether the ``nvcc`` tool is found. + - ``amd``, ``nvidia`` + + * - | ``HIP_PATH`` + | The path of the HIP SDK on Microsoft Windows for AMD platforms. + - Default: ``C:/hip`` + + * - | ``ROCM_PATH`` + | The path of the installed ROCm software stack on Linux for AMD platforms. + - Default: ``/opt/rocm`` + + * - | ``CUDA_PATH`` + | Path to the CUDA SDK, which is only used for NVIDIA platforms. + - Default: ``/usr/local/cuda`` + + * - | ``HIP_CLANG_PATH`` + | Path to the clang, which is only used for AMD platforms. + - Default: ``ROCM_PATH/llvm/bin`` or ``HIP_PATH/../llvm/bin"`` + + * - | ``HIP_LIB_PATH`` + | The HIP device library installation path. + - Default: ``HIP_PATH/lib`` + + * - | ``HIP_DEVICE_LIB_PATH`` + | The HIP device library installation path. + - + + * - | ``HIPCC_COMPILE_FLAGS_APPEND`` + | Append extra flags as compilation options to ``hipcc``. + - + + * - | ``HIPCC_LINK_FLAGS_APPEND`` + | Append extra flags as compilation options to ``hipcc``. + - + + * - | ``HIPCC_VERBOSE`` + | Outputs detailed information on subcommands executed during compilation. + - | 1: Displays the command to ``clang++`` or ``nvcc`` with all options (``hipcc-cmd``). + | 2: Displays all relevant environment variables and their values. + | 4: Displays only the arguments passed to the ``hipcc`` command (``hipcc_args``). + | 5: Displays both the command to ``clang++`` or ``nvcc`` and ``hipcc`` arguments (``hipcc-cmd`` and ``hipcc-args``). + | 6: Displays all relevant environment variables and their values, along with the arguments to the ``hipcc`` command. + | 7: Displays all of the above: ``hipcc-cmd``, ``hipcc-args``, and environment variables. diff --git a/amd/hipcc/docs/index.rst b/amd/hipcc/docs/index.rst new file mode 100644 index 0000000000000..642e501cd82a0 --- /dev/null +++ b/amd/hipcc/docs/index.rst @@ -0,0 +1,36 @@ +.. meta:: + :description: HIPCC command + :keywords: HIPCC, ROCm, HIP tools, HIP compiler + +.. _hipcc-docs: + +****************************************** +HIPCC documentation +****************************************** + +.. note:: + ROCm provides and supports multiple compilers as described in `ROCm compiler reference `_. + +``hipcc`` is a compiler driver utility that will call ``clang`` or ``nvcc``, depending on target, and pass the appropriate include and library options for the target compiler and HIP infrastructure. C++ executable versions of ``hipcc`` and ``hipconfig`` compiler driver utilities are provided. + +The HIPCC public repository is located at `https://github.com/ROCm/llvm-project/tree/amd-staging/amd/hipcc `_ + +The documentation is structured as follows: + +.. grid:: 2 + :gutter: 3 + + .. grid-item-card:: Installation + + * :ref:`hipcc_build` + * :ref:`hipcc_vars` + + .. grid-item-card:: How to + + * :ref:`hipcc_use` + +To contribute to the documentation, refer to +`Contributing to ROCm `_. + +You can find licensing information on the +`Licensing `_ page. diff --git a/amd/hipcc/docs/license.md b/amd/hipcc/docs/license.md new file mode 100644 index 0000000000000..bfc65acd0326f --- /dev/null +++ b/amd/hipcc/docs/license.md @@ -0,0 +1,4 @@ +# License + +```{include} ../LICENSE.txt +``` diff --git a/amd/hipcc/docs/sphinx/_toc.yml.in b/amd/hipcc/docs/sphinx/_toc.yml.in new file mode 100644 index 0000000000000..35c421540c687 --- /dev/null +++ b/amd/hipcc/docs/sphinx/_toc.yml.in @@ -0,0 +1,20 @@ +# Anywhere {branch} is used, the branch name will be substituted. +# These comments will also be removed. +defaults: + numbered: False + maxdepth: 6 +root: index +subtrees: + +- caption: Install + entries: + - file: build + - file: env + +- caption: How to + entries: + - file: usage + +- caption: About + entries: + - file: license.md diff --git a/amd/hipcc/docs/sphinx/requirements.in b/amd/hipcc/docs/sphinx/requirements.in new file mode 100644 index 0000000000000..189f0449162a8 --- /dev/null +++ b/amd/hipcc/docs/sphinx/requirements.in @@ -0,0 +1 @@ +rocm-docs-core==1.4.0 diff --git a/amd/hipcc/docs/sphinx/requirements.txt b/amd/hipcc/docs/sphinx/requirements.txt new file mode 100644 index 0000000000000..ee6e29278d724 --- /dev/null +++ b/amd/hipcc/docs/sphinx/requirements.txt @@ -0,0 +1,147 @@ +# +# This file is autogenerated by pip-compile with Python 3.10 +# by the following command: +# +# pip-compile requirements.in +# +accessible-pygments==0.0.5 + # via pydata-sphinx-theme +alabaster==0.7.16 + # via sphinx +babel==2.15.0 + # via + # pydata-sphinx-theme + # sphinx +beautifulsoup4==4.12.3 + # via pydata-sphinx-theme +breathe==4.35.0 + # via rocm-docs-core +certifi==2024.6.2 + # via requests +cffi==1.16.0 + # via + # cryptography + # pynacl +charset-normalizer==3.3.2 + # via requests +click==8.1.7 + # via sphinx-external-toc +cryptography==42.0.8 + # via pyjwt +deprecated==1.2.14 + # via pygithub +docutils==0.21.2 + # via + # breathe + # myst-parser + # pydata-sphinx-theme + # sphinx +fastjsonschema==2.19.1 + # via rocm-docs-core +gitdb==4.0.11 + # via gitpython +gitpython==3.1.43 + # via rocm-docs-core +idna==3.7 + # via requests +imagesize==1.4.1 + # via sphinx +jinja2==3.1.4 + # via + # myst-parser + # sphinx +markdown-it-py==3.0.0 + # via + # mdit-py-plugins + # myst-parser +markupsafe==2.1.5 + # via jinja2 +mdit-py-plugins==0.4.1 + # via myst-parser +mdurl==0.1.2 + # via markdown-it-py +myst-parser==3.0.1 + # via rocm-docs-core +packaging==24.1 + # via + # pydata-sphinx-theme + # sphinx +pycparser==2.22 + # via cffi +pydata-sphinx-theme==0.15.3 + # via + # rocm-docs-core + # sphinx-book-theme +pygithub==2.3.0 + # via rocm-docs-core +pygments==2.18.0 + # via + # accessible-pygments + # pydata-sphinx-theme + # sphinx +pyjwt[crypto]==2.8.0 + # via pygithub +pynacl==1.5.0 + # via pygithub +pyyaml==6.0.1 + # via + # myst-parser + # rocm-docs-core + # sphinx-external-toc +requests==2.32.3 + # via + # pygithub + # sphinx +rocm-docs-core==1.4.0 + # via -r requirements.in +smmap==5.0.1 + # via gitdb +snowballstemmer==2.2.0 + # via sphinx +soupsieve==2.5 + # via beautifulsoup4 +sphinx==7.3.7 + # via + # breathe + # myst-parser + # pydata-sphinx-theme + # rocm-docs-core + # sphinx-book-theme + # sphinx-copybutton + # sphinx-design + # sphinx-external-toc + # sphinx-notfound-page +sphinx-book-theme==1.1.3 + # via rocm-docs-core +sphinx-copybutton==0.5.2 + # via rocm-docs-core +sphinx-design==0.6.0 + # via rocm-docs-core +sphinx-external-toc==1.0.1 + # via rocm-docs-core +sphinx-notfound-page==1.0.2 + # via rocm-docs-core +sphinxcontrib-applehelp==1.0.8 + # via sphinx +sphinxcontrib-devhelp==1.0.6 + # via sphinx +sphinxcontrib-htmlhelp==2.0.5 + # via sphinx +sphinxcontrib-jsmath==1.0.1 + # via sphinx +sphinxcontrib-qthelp==1.0.7 + # via sphinx +sphinxcontrib-serializinghtml==1.1.10 + # via sphinx +tomli==2.0.1 + # via sphinx +typing-extensions==4.12.2 + # via + # pydata-sphinx-theme + # pygithub +urllib3==2.2.1 + # via + # pygithub + # requests +wrapt==1.16.0 + # via deprecated diff --git a/amd/hipcc/docs/usage.rst b/amd/hipcc/docs/usage.rst new file mode 100644 index 0000000000000..7b1c5ed845fe0 --- /dev/null +++ b/amd/hipcc/docs/usage.rst @@ -0,0 +1,19 @@ +.. meta:: + :description: HIPCC usage description + :keywords: HIPCC, ROCm, HIP tools, HIP compiler + +.. _hipcc_use: + +****************************************** +Using HIPCC +****************************************** + +To use the newly built ``hipcc`` and ``hipconfig`` executables from the build folder use ``./`` in front of the executable name. +For example: + +.. code-block:: shell + + ./hipconfig --help + ./hipcc --help + ./hipcc --version + ./hipconfig --full diff --git a/amd/hipcc/hipcc-backward-compat.cmake b/amd/hipcc/hipcc-backward-compat.cmake new file mode 100644 index 0000000000000..468f54d176e15 --- /dev/null +++ b/amd/hipcc/hipcc-backward-compat.cmake @@ -0,0 +1,49 @@ +# Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +cmake_minimum_required(VERSION 3.16.8) + +set(HIPCC_WRAPPER_BIN_DIR ${CMAKE_CURRENT_BINARY_DIR}/wrapper_dir/bin) +set(HIPCC_SRC_BIN_DIR ${CMAKE_CURRENT_SOURCE_DIR}/bin) + +#function to create symlink to binaries +function(create_binary_symlink) + file(MAKE_DIRECTORY ${HIPCC_WRAPPER_BIN_DIR}) + #get all binaries + file(GLOB binary_files ${HIPCC_SRC_BIN_DIR}/*) + foreach(binary_file ${binary_files}) + get_filename_component(file_name ${binary_file} NAME) + add_custom_target(link_${file_name} ALL + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + COMMAND ${CMAKE_COMMAND} -E create_symlink + ../../${CMAKE_INSTALL_BINDIR}/${file_name} ${HIPCC_WRAPPER_BIN_DIR}/${file_name}) + endforeach() +endfunction() + +# Create symlink to binaries +create_binary_symlink() +# TODO: Following has to modified if component based installation is required +if (NOT WIN32) + install(DIRECTORY ${HIPCC_WRAPPER_BIN_DIR} DESTINATION hip) +else() + install(DIRECTORY ${HIPCC_WRAPPER_BIN_DIR} DESTINATION hip + FILES_MATCHING + PATTERN "*" + PATTERN "*.bat" EXCLUDE ) +endif() diff --git a/amd/hipcc/src/filesystem.h b/amd/hipcc/src/filesystem.h new file mode 100644 index 0000000000000..0318efce09531 --- /dev/null +++ b/amd/hipcc/src/filesystem.h @@ -0,0 +1,69 @@ +#ifndef SRC_HIP_FILESYSTEM_H_ +#define SRC_HIP_FILESYSTEM_H_ + +// We haven't checked which filesystem to include yet +#ifndef INCLUDE_STD_FILESYSTEM_EXPERIMENTAL +// Check for feature test macro for +#if defined(__cpp_lib_filesystem) +#define INCLUDE_STD_FILESYSTEM_EXPERIMENTAL 0 +// Check for feature test macro for +#elif defined(__cpp_lib_experimental_filesystem) +#define INCLUDE_STD_FILESYSTEM_EXPERIMENTAL 1 +// We can't check if headers exist... +// Let's assume experimental to be safe +#elif !defined(__has_include) +#define INCLUDE_STD_FILESYSTEM_EXPERIMENTAL 1 +// Check if the header "" exists +#elif __has_include() +// If we're compiling on Visual Studio and are not compiling with C++17, +// we need to use experimental +#ifdef _MSC_VER +// Check and include header that defines "_HAS_CXX17" +#if __has_include() +#include + +// Check for enabled C++17 support +#if defined(_HAS_CXX17) && _HAS_CXX17 +// We're using C++17, so let's use the normal version +#define INCLUDE_STD_FILESYSTEM_EXPERIMENTAL 0 +#endif + +#endif + +// If the marco isn't defined yet, that means any of the other +// VS specific checks failed, so we need to use experimental +#ifndef INCLUDE_STD_FILESYSTEM_EXPERIMENTAL +#define INCLUDE_STD_FILESYSTEM_EXPERIMENTAL 1 +#endif + +// Not on Visual Studio. Let's use the normal version +#else // #ifdef _MSC_VER +#define INCLUDE_STD_FILESYSTEM_EXPERIMENTAL 0 +#endif + +// Check if the header "" exists +#elif __has_include() +#define INCLUDE_STD_FILESYSTEM_EXPERIMENTAL 1 + +// Fail if neither header is available with a nice error message +#else +#error Could not find system header "" || +"" +#endif + +// We priously determined that we need the exprimental version +#if INCLUDE_STD_FILESYSTEM_EXPERIMENTAL +// Include it +#include +// We need the alias from std::experimental::filesystem to std::filesystem +namespace fs = std::experimental::filesystem; +// We have a decent compiler and can use the normal version +#else +// Include it +#include +namespace fs = std::filesystem; +#endif + +#endif // #ifndef INCLUDE_STD_FILESYSTEM_EXPERIMENTAL + +#endif diff --git a/amd/hipcc/src/hipBin.h b/amd/hipcc/src/hipBin.h new file mode 100644 index 0000000000000..8c32a7a5b70ae --- /dev/null +++ b/amd/hipcc/src/hipBin.h @@ -0,0 +1,88 @@ +/* +Copyright (c) 2021 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#include "hipBin_util.h" +#include "hipBin_amd.h" +#include "hipBin_nvidia.h" +#include +#include +#include + +class HipBinUtil; +class HipBinBase; +class HipBinAmd; +class HipBinNvidia; +class HipBin; + + +class HipBin { + private: + HipBinUtil* hipBinUtilPtr_; + vector hipBinBasePtrs_; + HipBinBase* hipBinNVPtr_; + HipBinBase* hipBinAMDPtr_; + + public: + HipBin(); + ~HipBin(); + vector &getHipBinPtrs(); +}; + + +// Implementation ================================================ +//=========================================================================== + +HipBin::HipBin() { + hipBinUtilPtr_ = hipBinUtilPtr_->getInstance(); + hipBinNVPtr_ = new HipBinNvidia(); + hipBinAMDPtr_ = new HipBinAmd(); + bool platformDetected = false; + if (hipBinAMDPtr_->detectPlatform()) { + // populates the struct with AMD info + hipBinBasePtrs_.push_back(hipBinAMDPtr_); + platformDetected = true; + } else if (hipBinNVPtr_->detectPlatform()) { + // populates the struct with Nvidia info + hipBinBasePtrs_.push_back(hipBinNVPtr_); + platformDetected = true; + } + // if no device is detected, then it is defaulted to AMD + if (!platformDetected) { + std::cerr << "Device not supported - Defaulting to AMD" << endl; + // populates the struct with AMD info + hipBinBasePtrs_.push_back(hipBinAMDPtr_); + } +} + +HipBin::~HipBin() { + delete hipBinNVPtr_; + delete hipBinAMDPtr_; + // clearing the vector so no one accesses the pointers + hipBinBasePtrs_.clear(); + delete hipBinUtilPtr_; +} + +vector& HipBin::getHipBinPtrs() { + return hipBinBasePtrs_; // Return the populated device pointers. +} + + diff --git a/amd/hipcc/src/hipBin_amd.h b/amd/hipcc/src/hipBin_amd.h new file mode 100644 index 0000000000000..e845139080c4c --- /dev/null +++ b/amd/hipcc/src/hipBin_amd.h @@ -0,0 +1,941 @@ +/* +Copyright (c) 2021 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#ifndef SRC_HIPBIN_AMD_H_ +#define SRC_HIPBIN_AMD_H_ + +#include "hipBin_base.h" +#include "hipBin_util.h" +#include +#include +#include +#include +#include + + +// Use (void) to silent unused warnings. +#define assertm(exp, msg) assert(((void)msg, exp)) + +// Known Features + std::unordered_set + knownFeatures = { "sramecc-" , "sramecc+", + "xnack-", "xnack+" }; + +class HipBinAmd : public HipBinBase { + private: + string hipClangPath_ = ""; + string roccmPathEnv_, hipRocclrPathEnv_, hsaPathEnv_; + PlatformInfo platformInfoAMD_; + string hipCFlags_, hipCXXFlags_, hipLdFlags_; + void constructRocclrHomePath(); + void constructHsaPath(); + + public: + HipBinAmd(); + ~HipBinAmd() override = default; + virtual bool detectPlatform(); + virtual void constructCompilerPath(); + virtual const string& getCompilerPath() const; + virtual const PlatformInfo& getPlatformInfo() const; + virtual string getCppConfig(); + virtual void printFull(); + virtual void printCompilerInfo() const; + virtual string getCompilerVersion(); + virtual void checkHipconfig(); + virtual string getDeviceLibPath() const; + virtual string getHipLibPath() const; + virtual string getHipCC() const; + virtual string getHipInclude() const; + virtual void initializeHipCXXFlags(); + virtual void initializeHipCFlags(); + virtual void initializeHipLdFlags(); + virtual const string& getHipCXXFlags() const; + virtual const string& getHipCFlags() const; + virtual const string& getHipLdFlags() const; + virtual void executeHipCCCmd(vector argv); + // non virtual functions + const string& getHsaPath() const; + const string& getRocclrHomePath() const; + const bool isWindows() const; +}; + +HipBinAmd::HipBinAmd() { + PlatformInfo platformInfo; + platformInfo.os = getOSInfo(); + platformInfo.platform = amd; + platformInfo.runtime = rocclr; + platformInfo.compiler = clang; + platformInfoAMD_ = platformInfo; + + // Base class calls readEnvVariables, but we need to make sure we set rocm_path and hip_path, so that we can set hipClangPath + constructHipPath(); + constructRoccmPath(); + constructCompilerPath(); + readHipVersion(); +} + +// returns the Rocclr Home path +void HipBinAmd::constructRocclrHomePath() { + fs::path full_path(fs::current_path()); + fs::path hipvars_dir = full_path; + fs::path bitcode = hipvars_dir; + string rocclrHomePath = getEnvVariables().hipRocclrPathEnv_; + if (rocclrHomePath.empty()) { + bitcode /= "../lib/bitcode"; + if (!fs::exists(bitcode)) { + rocclrHomePath = getHipPath(); + } else { + hipvars_dir /= ".."; + rocclrHomePath = hipvars_dir.string(); + } + } + hipRocclrPathEnv_ = rocclrHomePath; +} + + +// construct hsa Path +void HipBinAmd::constructHsaPath() { + fs::path hsaPathfs; + string hsaPath = getEnvVariables().hsaPathEnv_; + if (hsaPath.empty()) { + hsaPath = getRoccmPath(); + hsaPathfs = hsaPath; + hsaPathfs /= "hsa"; + hsaPath = hsaPathfs.string(); + hsaPathEnv_ = hsaPath; + } else { + hsaPathEnv_ = hsaPath; + } +} + +// returns the Rocclr Home path +const string& HipBinAmd::getRocclrHomePath() const { + return hipRocclrPathEnv_; +} + +// returns hsa Path +const string& HipBinAmd::getHsaPath() const { + // return variables_.hsaPathEnv_; + return hsaPathEnv_; +} + + +const string& HipBinAmd::getHipCFlags() const { + return hipCFlags_; +} + + +const string& HipBinAmd::getHipLdFlags() const { + return hipLdFlags_; +} + + +void HipBinAmd::initializeHipLdFlags() { + string hipLdFlags; + const string& hipClangPath = getCompilerPath(); + // If $HIPCC clang++ is not compiled, use clang instead + string hipCC = "\"" + hipClangPath + "/clang++"; + if (!fs::exists(hipCC)) { + hipLdFlags = "--driver-mode=g++"; + } + hipLdFlags_ = hipLdFlags; +} + +void HipBinAmd::initializeHipCFlags() { +} + +const string& HipBinAmd::getHipCXXFlags() const { + return hipCXXFlags_; +} + + +string HipBinAmd::getHipInclude() const { + const string& rocclrHomePath = getRocclrHomePath(); + fs::path hipIncludefs = rocclrHomePath; + hipIncludefs /= "include"; + if (hipIncludefs.string().empty()) { + const string& hipPath = getHipPath(); + hipIncludefs = hipPath; + hipIncludefs /= "include"; + } + string hipInclude = hipIncludefs.string(); + return hipInclude; +} + + +void HipBinAmd::initializeHipCXXFlags() { + string hipCXXFlags; + const OsType& os = getOSInfo(); + const EnvVariables& var = getEnvVariables(); + // Allow __fp16 as function parameter and return type. + if (var.hipClangHccCompactModeEnv_.compare("1") == 0) { + hipCXXFlags += + " -Xclang -fallow-half-arguments-and-returns -D__HIP_HCC_COMPAT_MODE__=1"; + } + + hipCXXFlags_ = hipCXXFlags; +} + +// populates clang path. +void HipBinAmd::constructCompilerPath() { + string compilerPath; + const EnvVariables& envVariables = getEnvVariables(); + if (envVariables.hipClangPathEnv_.empty()) { + fs::path hipClangPath; + if (isWindows()) { + compilerPath = getHipPath(); + hipClangPath = compilerPath; + hipClangPath /= "bin"; + } else { + compilerPath = getRoccmPath(); + hipClangPath = compilerPath; + hipClangPath /= "lib/llvm/bin"; + } + + compilerPath = hipClangPath.string(); + } else { + compilerPath = envVariables.hipClangPathEnv_; + } + hipClangPath_ = compilerPath; +} + +// returns clang path. +const string& HipBinAmd::getCompilerPath() const { + return hipClangPath_; +} + +void HipBinAmd::printCompilerInfo() const { + const string& hipClangPath = getCompilerPath(); + const string& hipPath = getHipPath(); + if (isWindows()) { + string cmd = hipClangPath + "/clang++ --version"; + system(cmd.c_str()); // hipclang version + cout << "llc-version :" << endl; + cmd = hipClangPath + "/llc --version"; + system(cmd.c_str()); // llc version + cout << "hip-clang-cxxflags :" << endl; + cmd = hipPath + "/bin/hipcc --cxxflags"; + system(cmd.c_str()); // cxx flags + cout << endl << "hip-clang-ldflags :" << endl; + cmd = hipPath + "/bin/hipcc --ldflags"; + system(cmd.c_str()); // ld flags + cout << endl; + } else { + string cmd = hipClangPath + "/clang++ --version"; + system(cmd.c_str()); // hipclang version + cmd = hipClangPath + "/llc --version"; + system(cmd.c_str()); // llc version + cout << "hip-clang-cxxflags :" << endl; + cmd = hipPath + "/bin/hipcc --cxxflags"; + system(cmd.c_str()); // cxx flags + cout << endl << "hip-clang-ldflags :" << endl; + cmd = hipPath + "/bin/hipcc --ldflags"; + system(cmd.c_str()); // ldflags version + cout << endl; + } +} + +string HipBinAmd::getCompilerVersion() { + string out, compilerVersion; + const string& hipClangPath = getCompilerPath(); + fs::path cmdAmd = hipClangPath; + cmdAmd /= "clang++"; + if (canRunCompiler(cmdAmd.string(), out) || canRunCompiler("amdclang++", out)) { + regex regexp("([0-9.]+)"); + smatch m; + if (regex_search(out, m, regexp)) { + if (m.size() > 1) { + // get the index =1 match, 0=whole match we ignore + std::ssub_match sub_match = m[1]; + compilerVersion = sub_match.str(); + } + } + } else { + std::cerr << "Hip Clang Compiler not found" << endl; + } + return compilerVersion; +} + + + +const PlatformInfo& HipBinAmd::getPlatformInfo() const { + return platformInfoAMD_; +} + + +string HipBinAmd::getCppConfig() { + string cppConfig = " -D__HIP_PLATFORM_HCC__= -D__HIP_PLATFORM_AMD__="; + + string compilerVersion; + compilerVersion = getCompilerVersion(); + + fs::path hipPathInclude, cppConfigFs; + const string& hipPath = getHipPath(); + hipPathInclude = hipPath; + hipPathInclude /= "include"; + if (isWindows()) { + cppConfig += " -I" + hipPathInclude.string(); + cppConfigFs = cppConfig; + cppConfigFs /= "/"; + } else { + const string& hsaPath = getHsaPath(); + cppConfig += " -I" + hipPathInclude.string() + + " -I" + hsaPath; + cppConfigFs = cppConfig; + cppConfigFs /= "include"; + cppConfig = cppConfigFs.string(); + } + return cppConfig; +} + +string HipBinAmd::getDeviceLibPath() const { + const EnvVariables& var = getEnvVariables(); + const string& rocclrHomePath = getRocclrHomePath(); + const string& roccmPath = getRoccmPath(); + fs::path bitCodePath = rocclrHomePath; + bitCodePath /= "lib/bitcode"; + string deviceLibPath = var.deviceLibPathEnv_; + if (deviceLibPath.empty() && fs::exists(bitCodePath)) { + deviceLibPath = bitCodePath.string(); + } + + if (deviceLibPath.empty()) { + fs::path amdgcnBitcode = roccmPath; + amdgcnBitcode /= "amdgcn/bitcode"; + if (fs::exists(amdgcnBitcode)) { + deviceLibPath = amdgcnBitcode.string(); + } else { + // This path is to support an older build of the device library + // TODO(hipcc): To be removed in the future. + fs::path lib = roccmPath; + lib /= "lib"; + deviceLibPath = lib.string(); + } + } + return deviceLibPath; +} + + +bool HipBinAmd::detectPlatform() { + string out; + constructCompilerPath(); + const string& hipClangPath = getCompilerPath(); + fs::path cmdAmd = hipClangPath; + cmdAmd /= "clang++"; + const EnvVariables& var = getEnvVariables(); + bool detected = false; + if (var.hipPlatformEnv_.empty()) { + string cmd = cmdAmd.string(); + if (getOSInfo() == windows) { + cmd = "\"" + cmd + "\""; + } + + if (canRunCompiler(cmd, out)){ + detected = true; + } + } else { + if (var.hipPlatformEnv_ == "amd" || + var.hipPlatformEnv_ == "hcc") { + detected = true; + if (var.hipPlatformEnv_ == "hcc") + std::cerr << + "Warning: HIP_PLATFORM=hcc is deprecated."<< + "Please use HIP_PLATFORM=amd." << endl; + } + } + return detected; +} + +string HipBinAmd::getHipLibPath() const { + string hipLibPath; + const EnvVariables& env = getEnvVariables(); + if (!env.hipLibPathEnv_.empty()) { + hipLibPath = env.hipLibPathEnv_; + } + else if (!env.hipPathEnv_.empty()) { + fs::path p = env.hipLibPathEnv_; + p /= "lib"; + hipLibPath = p.string(); + } + return hipLibPath; +} + +string HipBinAmd::getHipCC() const { + string hipCC; + const string& hipClangPath = getCompilerPath(); + fs::path compiler = hipClangPath; + if (isWindows()) + compiler /= "clang.exe"; + else + compiler /= "clang++"; + + if (!fs::exists(compiler)) { + fs::path compiler = hipClangPath; + compiler /= "clang"; + } + hipCC = compiler.string(); + + if (isWindows()) // wrap hipcc (clang) command in escaped double quotes. + hipCC = "\"" + hipCC + "\" "; + return hipCC; +} + +void HipBinAmd::checkHipconfig() { + printFull(); + cout << endl << "Check system installation: " << endl; + cout << "check hipconfig in PATH..." << endl; + if (system("which hipconfig > /dev/null 2>&1") != 0) { + std::cerr << "FAIL " << endl; + } else { + cout << "good" << endl; + } + string ldLibraryPath; + const EnvVariables& env = getEnvVariables(); + ldLibraryPath = env.ldLibraryPathEnv_; + const string& hsaPath = getHsaPath(); + cout << "check LD_LIBRARY_PATH (" << ldLibraryPath << + ") contains HSA_PATH (" << hsaPath << ")..." << endl; + if (ldLibraryPath.find(hsaPath) == string::npos) { + std::cerr << "FAIL" << endl; + } else { + cout << "good" << endl; + } +} + +void HipBinAmd::printFull() { + const string& hipVersion = getHipVersion(); + const string& hipPath = getHipPath(); + const string& roccmPath = getRoccmPath(); + const PlatformInfo& platformInfo = getPlatformInfo(); + const string& ccpConfig = getCppConfig(); + const string& hsaPath = getHsaPath(); + const string& hipClangPath = getCompilerPath(); + + cout << "HIP version: " << hipVersion << endl; + cout << endl << "==hipconfig" << endl; + cout << "HIP_PATH :" << hipPath << endl; + cout << "ROCM_PATH :" << roccmPath << endl; + cout << "HIP_COMPILER :" << CompilerTypeStr( + platformInfo.compiler) << endl; + cout << "HIP_PLATFORM :" << PlatformTypeStr( + platformInfo.platform) << endl; + cout << "HIP_RUNTIME :" << RuntimeTypeStr( + platformInfo.runtime) << endl; + cout << "CPP_CONFIG :" << ccpConfig << endl; + + cout << endl << "==hip-clang" << endl; + cout << "HIP_CLANG_PATH :" << hipClangPath << endl; + printCompilerInfo(); + cout << endl << "== Environment Variables" << endl; + printEnvironmentVariables(); + getSystemInfo(); + if (fs::exists("/usr/bin/lsb_release")) + system("/usr/bin/lsb_release -a"); + cout << endl; +} + +const bool HipBinAmd::isWindows() const { + const OsType& osInfo = getOSInfo(); + return (osInfo == windows); +} + +void HipBinAmd::executeHipCCCmd(vector argv) { + if (argv.size() < 2) { + cout<< "No Arguments passed, exiting ...\n"; + exit(EXIT_SUCCESS); + } + const EnvVariables& var = getEnvVariables(); + int verbose = 0; + if (!var.verboseEnv_.empty()) + verbose = stoi(var.verboseEnv_); + + // Verbose: 0x1=commands, 0x2=paths, 0x4=hipcc args + // set if user explicitly requests -stdlib=libc++ + // (else we default to libstdc++ for better interop with g++) + bool setStdLib = 0; + bool default_amdgpu_target = 1; + bool compileOnly = 0; + bool needCXXFLAGS = 0; // need to add CXX flags to compile step + bool needCFLAGS = 0; // need to add C flags to compile step + bool needLDFLAGS = 1; // need to add LDFLAGS to compile step. + bool fileTypeFlag = 0; // to see if -x flag is mentioned + bool hasOMPTargets = 0; // If OMP targets is mentioned + bool hasC = 0; // options contain a c-style file + // options contain a cpp-style file (NVCC must force recognition as GPU file) + bool hasCXX = 0; + // options contain a hip-style file (HIP-Clang must pass offloading options) + bool hasHIP = 0; + bool printHipVersion = 0; // print HIP version + bool printCXXFlags = 0; // print HIPCXXFLAGS + bool printLDFlags = 0; // print HIPLDFLAGS + bool runCmd = 1; + bool buildDeps = 0; + string hsacoVersion; + bool funcSupp = 1; // enable function support + bool rdc = 0; // whether -fgpu-rdc is on + + string prevArg; // previous argument + // TODO(hipcc): convert toolArgs to an array rather than a string + string toolArgs; // arguments to pass to the clang or nvcc tool + string optArg; // -O args + vector options, inputs; + + // TODO(hipcc): hipcc uses --amdgpu-target for historical reasons. + // It should be replaced + // by clang option --offload-arch. + vector targetOpts = {"--offload-arch=", "--amdgpu-target="}; + string targetsStr; + // file followed by -o should not contibute in picking compiler flags + bool skipOutputFile = false; + + const OsType& os = getOSInfo(); + string hip_compile_cxx_as_hip; + if (var.hipCompileCxxAsHipEnv_.empty()) { + hip_compile_cxx_as_hip = "1"; + } else { + hip_compile_cxx_as_hip = var.hipCompileCxxAsHipEnv_; + } + + string HIPLDARCHFLAGS; + string HIPCXXFLAGS, HIPCFLAGS, HIPLDFLAGS; + + // ARGV Processing Loop + // TODO(hipcc): create a proper Options Processing function/routine + for (unsigned int argcount = 1; argcount < argv.size(); argcount++) { + // Save $arg, it can get changed in the loop. + string arg = argv.at(argcount); + // TODO(hipcc): figure out why this space removal is wanted. + // TODO(hipcc): If someone has gone to the effort of + // quoting the spaces to the shell + // TODO(hipcc): why are we removing it here? + regex toRemove("\\s+"); + // Remove whitespace + string trimarg = hipBinUtilPtr_->replaceRegex(arg, toRemove, ""); + bool swallowArg = false; + bool escapeArg = true; + if (arg == "-c" || arg == "--genco" || arg == "-E") { + compileOnly = true; + needLDFLAGS = false; + } + + if (skipOutputFile) { + // TODO(hipcc): handle filename with shell metacharacters + toolArgs += " \"" + arg +"\""; + prevArg = arg; + skipOutputFile = 0; + continue; + } + + if (arg == "-o") { + needLDFLAGS = 1; + skipOutputFile = 1; + } + + if ((trimarg == "-stdlib=libc++") && (setStdLib == 0)) { + HIPCXXFLAGS += " -stdlib=libc++"; + setStdLib = 1; + } + + // Process --rocm-path option + const string& rocmPathOption = "--rocm-path="; + if (arg.compare(0,rocmPathOption.length(),rocmPathOption) == 0) + rocm_pathOption_ = arg.substr(rocmPathOption.length()); + // Process --hip-path option + const string& hipPathOption = "--hip-path="; + if (arg.compare(0,hipPathOption.length(),hipPathOption) == 0) + hip_pathOption_ = arg.substr(hipPathOption.length()); + + // Check target selection option: --offload-arch= and --amdgpu-target=... + for (unsigned int i = 0; i stringRegexMatch(arg, pattern)) { + if (targetOpt == "--amdgpu-target=") { + std::cerr << "Warning: The --amdgpu-target option has been deprecated and will be removed in the future." + << " Use --offload-arch instead.\n"; + } + // If targets string is not empty, + // add a comma before adding new target option value. + targetsStr.size() >0 ? targetsStr += ",": targetsStr += ""; + targetsStr += arg.substr(targetOpt.size()); // argument of targetOpts + default_amdgpu_target = 0; + // Collect the GPU arch options and pass them to clang later. + swallowArg = 1; + } + } // end of for targetOpts for loop + + if (hipBinUtilPtr_->substringPresent(arg, "--genco")) { + arg = "--cuda-device-only"; + } + + if (trimarg == "--version") { + printHipVersion = 1; + } + if (trimarg == "--short-version") { + printHipVersion = 1; + runCmd = 0; + } + if (trimarg == "--cxxflags") { + printCXXFlags = 1; + runCmd = 0; + } + if (trimarg == "--ldflags") { + printLDFlags = 1; + runCmd = 0; + } + if (trimarg == "-M") { + compileOnly = 1; + buildDeps = 1; + } + if ((trimarg == "-use-staticlib")) { + std::cerr << "Warning: The -use-staticlib option has been deprecated and is no longer needed.\n"; + swallowArg = true; + } + if ((trimarg == "-use-sharedlib")) { + std::cerr << "Warning: The -use-sharedlib option has been deprecated and is no longer needed.\n"; + swallowArg = true; + } + if (hipBinUtilPtr_->stringRegexMatch(arg, "^-O.*")) { + optArg = arg; + } + if (hipBinUtilPtr_->substringPresent( + arg, "--amdhsa-code-object-version=")) { + std::cerr << "Warning: The --amdhsa-code-object-version option has been " + "deprecated and will be removed in the future." + << " Use -mcode-object-version instead.\n"; + arg = hipBinUtilPtr_->replaceStr( + arg, "--amdhsa-code-object-version=", ""); + hsacoVersion = arg; + swallowArg = 1; + } + + if (arg == "-x") { + fileTypeFlag = 1; + } else if ((arg == "c" && prevArg == "-x") || (arg == "-xc")) { + fileTypeFlag = 1; + hasC = 1; + hasCXX = 0; + hasHIP = 0; + } else if ((arg == "c++" && prevArg == "-x") || (arg == "-xc++")) { + fileTypeFlag = 1; + hasC = 0; + hasCXX = 1; + hasHIP = 0; + } else if ((arg == "hip" && prevArg == "-x") || (arg == "-xhip")) { + fileTypeFlag = 1; + hasC = 0; + hasCXX = 0; + hasHIP = 1; + } else if (hipBinUtilPtr_->substringPresent(arg, "-fopenmp-targets=")) { + hasOMPTargets = 1; + // options start with - + } else if (hipBinUtilPtr_->stringRegexMatch(arg, "^-.*")) { + if (arg == "-fgpu-rdc") { + rdc = 1; + } else if (arg == "-fno-gpu-rdc") { + rdc = 0; + } + //# Process HIPCC options here: + if (hipBinUtilPtr_->stringRegexMatch(arg, "^--hipcc.*")) { + swallowArg = 1; + if (arg == "--hipcc-func-supp") { + std::cerr << "Warning: The --hipcc-func-supp option has been deprecated and will be removed in the future.\n"; + funcSupp = 1; + } else if (arg == "--hipcc-no-func-supp") { + std::cerr << "Warning: The --hipcc-no-func-supp option has been deprecated and will be removed in the future.\n"; + funcSupp = 0; + } + } else { + options.push_back(arg); + } + // print "O: <$arg>\n"; + } else if (prevArg != "-o") { + // input files and libraries + // Skip guessing if `-x {c|c++|hip}` is already specified. + // Add proper file extension before each file type + // File Extension -> Flag + // .c -> -x c + // .cpp/.cxx/.cc/.cu/.cuh/.hip -> -x hip + + if (fileTypeFlag == 0) { + if (hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.c$")) { + hasC = 1; + needCFLAGS = 1; + toolArgs += " -x c"; + } else if ((hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.cpp$")) || + (hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.cxx$")) || + (hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.cc$")) || + (hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.C$"))) { + needCXXFLAGS = 1; + if (hip_compile_cxx_as_hip == "0" || hasOMPTargets == 1) { + hasCXX = 1; + } else { + hasHIP = 1; + toolArgs += " -x hip"; + } + } else if (((hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.cu$") || + hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.cuh$")) && + hip_compile_cxx_as_hip != "0") || + (hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.hip$"))) { + needCXXFLAGS = 1; + hasHIP = 1; + toolArgs += " -x hip"; + } + } + if (hasC) { + needCFLAGS = 1; + } else if (hasCXX || hasHIP) { + needCXXFLAGS = 1; + } + if (isWindows()) + arg = "\"" + arg + "\""; + + inputs.push_back(arg); + // print "I: <$arg>\n"; + } + // Produce a version of $arg where characters significant to the shell are + // quoted. One could quote everything of course but don't bother for + // common characters such as alphanumerics. + // Do the quoting here because sometimes the $arg is changed in the loop + // Important to have all of '-Xlinker' in the set of unquoted characters. + // Windows needs different quoting, ignore for now + if (!isWindows() && escapeArg) { + regex reg("[^-a-zA-Z0-9_=+,.\\/]"); + arg = regex_replace(arg, reg, "\\$&"); + } + if (!swallowArg) + toolArgs += " " + arg; + prevArg = arg; + } // end of ARGV Processing Loop + + // now construct Paths ... + constructHipPath(); // constructs HIP Path + constructRoccmPath(); // constructs Roccm Path + readHipVersion(); // stores the hip version + constructCompilerPath(); + constructRocclrHomePath(); + constructHsaPath(); + + initializeHipCXXFlags(); + initializeHipCFlags(); + initializeHipLdFlags(); + HIPCFLAGS = getHipCFlags(); + HIPCXXFLAGS = getHipCXXFlags(); + HIPLDFLAGS = getHipLdFlags(); + + string hipLibPath; + string hipIncludePath, deviceLibPath; + hipLibPath = getHipLibPath(); + const string& roccmPath = getRoccmPath(); + const string& hipPath = getHipPath(); + const PlatformInfo& platformInfo = getPlatformInfo(); + const string& rocclrHomePath = getRocclrHomePath(); + const string& hipClangPath = getCompilerPath(); + hipIncludePath = getHipInclude(); + deviceLibPath = getDeviceLibPath(); + const string& hipVersion = getHipVersion(); + if (verbose & 0x2) { + cout << "HIP_PATH=" << hipPath << endl; + cout << "HIP_PLATFORM=" << PlatformTypeStr(platformInfo.platform) <exec(targetsStr.c_str()); + regex toReplace("\n+"); + targetsStr = hipBinUtilPtr_->replaceRegex(sysOut.out, toReplace, ","); + } + default_amdgpu_target = 0; + } + // Parse the targets collected in targetStr + // and set corresponding compiler options. + vector targets = hipcc::utils::splitStr(targetsStr, ','); + string GPU_ARCH_OPT = " --offload-arch="; + + for (auto &val : targets) { + // Ignore 'gfx000' target reported by rocm_agent_enumerator. + if (val != "gfx000") { + vector procAndFeatures = hipcc::utils::splitStr(val, ':'); + size_t len = procAndFeatures.size(); + // proc and features + assertm(procAndFeatures.size() >= 1, "Pass the correct device/feature"); + for (size_t i = 1; i < len; i++) { + // fixme: currently it checks only for validity of the feature string. + // does not check if the device supports the feature or not + // e.g. vega10 does not support sramecc + if (knownFeatures.find(procAndFeatures.at(i)) == knownFeatures.end()) { + std::cerr << "Warning: The Feature: "<< procAndFeatures.at(i) << + " is unknown. Correct compilation is not guaranteed.\n"; + } + } + string GPU_ARCH_ARG; + GPU_ARCH_ARG = GPU_ARCH_OPT + val; + + HIPLDARCHFLAGS += GPU_ARCH_ARG; + if (hasHIP) { + HIPCXXFLAGS += GPU_ARCH_ARG; + } + } // end of val != "gfx000" + } // end of targets for loop + if (hsacoVersion.size() > 0) { + if (compileOnly == 0) { + HIPLDFLAGS += " -mcode-object-version=" + hsacoVersion; + } else { + HIPCXXFLAGS += " -mcode-object-version=" + hsacoVersion; + } + } + + // rocm_agent_enumerator failed! Throw an error and die if linking is required + if (default_amdgpu_target == 1 && compileOnly == 0) { + // TODO(agunashe) exit from function + std::cerr << "No valid AMD GPU target was either specified or found." + << "Please specify a valid target using --offload-arch=.\n"; + } + + if (buildDeps) { + HIPCXXFLAGS += " --cuda-host-only"; + } + + // hipcc currrently requires separate compilation of source files, + // ie it is not possible to pass + // CPP files combined with .O files + // Reason is that NVCC uses the file extension to determine + // whether to compile in CUDA mode or + // pass-through CPP mode. + // Set default optimization level to -O3 for hip-clang. + if (optArg.empty()) { + HIPCXXFLAGS += " -O3"; + HIPCFLAGS += " -O3"; + HIPLDFLAGS += " -O3"; + } + + if (!funcSupp && optArg != "-O0" && hasHIP) { + HIPCXXFLAGS += + " -mllvm -amdgpu-early-inline-all=true -mllvm -amdgpu-function-calls=false"; + if (needLDFLAGS && !needCXXFLAGS) { + HIPLDFLAGS += + " -mllvm -amdgpu-early-inline-all=true" + " -mllvm -amdgpu-function-calls=false"; + } + } + + // to avoid using dk linker or MSVC linker + if (isWindows()) { + HIPLDFLAGS += " -fuse-ld=lld --ld-path=\"" + hipClangPath + "/lld-link.exe\""; + } + + if (!compileOnly) { + string hip_path = getHipLibPath(); + if (!hip_path.empty()) { + HIPLDFLAGS += " -L" + hip_path; + } + HIPLDFLAGS += " --hip-link"; + if (rdc) { + HIPLDFLAGS += HIPLDARCHFLAGS; + } + if (!windows) { + HIPLDFLAGS += " --rtlib=compiler-rt -unwindlib=libgcc"; + } + } + + // TODO(hipcc): convert CMD to an array rather than a string + string compiler; + compiler = getHipCC(); + string CMD = compiler; + if (needCFLAGS) { + CMD += " " + HIPCFLAGS; + } + + if (needCXXFLAGS) { + CMD += " " + HIPCXXFLAGS; + } + + if (needLDFLAGS && !compileOnly) { + CMD += " " + HIPLDFLAGS; + } + + CMD += " " + toolArgs; + if ((needCFLAGS || needCXXFLAGS) && + !var.hipccCompileFlagsAppendEnv_.empty()) { + CMD.append(" "); + CMD.append(var.hipccCompileFlagsAppendEnv_); + } + if (needLDFLAGS && !compileOnly && !var.hipccLinkFlagsAppendEnv_.empty()) { + CMD.append(" "); + CMD.append(var.hipccLinkFlagsAppendEnv_); + } + if (verbose & 0x1) { + cout << "hipcc-cmd: " << CMD << "\n"; + } + + if (printHipVersion) { + if (runCmd) { + cout << "HIP version: "; + } + cout << hipVersion << endl; + } + if (printCXXFlags) { + cout << HIPCXXFLAGS; + } + if (printLDFlags) { + cout << HIPLDFLAGS; + } + if (runCmd) { + if (isWindows()) + CMD = "\"" + CMD + "\""; + + SystemCmdOut sysOut; + sysOut = hipBinUtilPtr_->exec(CMD.c_str(), true); + string cmdOut = sysOut.out; + int CMD_EXIT_CODE = sysOut.exitCode; + if (CMD_EXIT_CODE !=0) { + std::cerr << "failed to execute:" << CMD << std::endl; + } + exit(CMD_EXIT_CODE); + } // end of runCmd section +} // end of function + +#endif // SRC_HIPBIN_AMD_H_ diff --git a/amd/hipcc/src/hipBin_base.h b/amd/hipcc/src/hipBin_base.h new file mode 100644 index 0000000000000..0f7ba2699682a --- /dev/null +++ b/amd/hipcc/src/hipBin_base.h @@ -0,0 +1,532 @@ +/* +Copyright (c) 2021 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ +#ifndef SRC_HIPBIN_BASE_H_ +#define SRC_HIPBIN_BASE_H_ + + +#include "hipBin_util.h" +#include +#include +#include + +// All envirnoment variables used in the code +# define PATH "PATH" +# define HIP_ROCCLR_HOME "HIP_ROCCLR_HOME" +# define HIP_PATH "HIP_PATH" +# define ROCM_PATH "ROCM_PATH" +# define CUDA_PATH "CUDA_PATH" +# define HSA_PATH "HSA_PATH" +# define HIP_CLANG_PATH "HIP_CLANG_PATH" +# define HIP_PLATFORM "HIP_PLATFORM" +# define HIP_COMPILER "HIP_COMPILER" +# define HIP_RUNTIME "HIP_RUNTIME" +# define LD_LIBRARY_PATH "LD_LIBRARY_PATH" + +// hipcc +# define HIPCC_COMPILE_FLAGS_APPEND "HIPCC_COMPILE_FLAGS_APPEND" +# define HIPCC_LINK_FLAGS_APPEND "HIPCC_LINK_FLAGS_APPEND" +# define HIP_LIB_PATH "HIP_LIB_PATH" +# define DEVICE_LIB_PATH "DEVICE_LIB_PATH" +# define HIP_CLANG_HCC_COMPAT_MODE "HIP_CLANG_HCC_COMPAT_MODE" +# define HIP_COMPILE_CXX_AS_HIP "HIP_COMPILE_CXX_AS_HIP" +# define HIPCC_VERBOSE "HIPCC_VERBOSE" +# define HCC_AMDGPU_TARGET "HCC_AMDGPU_TARGET" + +# define HIP_BASE_VERSION_DEFAULT "9999" + +enum PlatformType { + amd = 0, + nvidia, + // add new platform types to be added here +}; + +string PlatformTypeStr(PlatformType platform) { + switch (platform) { + case amd: + return "amd"; + case nvidia: + return "nvidia"; + // add new platform types to be added here + default: + return "invalid platform"; + } +} + +enum CompilerType { + clang = 0, + nvcc + // add new compiler types to be added here +}; + + +string CompilerTypeStr(CompilerType compiler) { + switch (compiler) { + case clang: + return "clang"; + case nvcc: + return "nvcc"; + // add new compiler types to be added here + default: + return "invalid CompilerType"; + } +} + + +enum RuntimeType { + rocclr = 0, + cuda + // add new runtime types to be added here +}; + +string RuntimeTypeStr(RuntimeType runtime) { + switch (runtime) { + case rocclr: + return "rocclr"; + case cuda: + return "cuda"; + // add new runtime types to be added here + default: + return "invalid RuntimeType"; + } +} + +enum OsType { + lnx = 0, + windows + // add new OS types to be added here +}; + +string OsTypeStr(OsType os) { + switch (os) { + case lnx: + return "linux"; + case windows: + return "windows"; + // add new OS types to be added here + default: + return "invalid OsType"; + } +} + +struct PlatformInfo { + PlatformType platform; + CompilerType compiler; + RuntimeType runtime; + OsType os; +}; + +struct EnvVariables { + string path_ = ""; + string hipPathEnv_ = ""; + string hipRocclrPathEnv_ = ""; + string roccmPathEnv_ = ""; + string cudaPathEnv_ = ""; + string hsaPathEnv_ = ""; + string hipClangPathEnv_ = ""; + string hipPlatformEnv_ = ""; + string hipCompilerEnv_ = ""; + string hipRuntimeEnv_ = ""; + string ldLibraryPathEnv_ = ""; + string verboseEnv_ = ""; + string hipccCompileFlagsAppendEnv_ = ""; + string hipccLinkFlagsAppendEnv_ = ""; + string hipLibPathEnv_ = ""; + string deviceLibPathEnv_ = ""; + string hipClangHccCompactModeEnv_ = ""; + string hipCompileCxxAsHipEnv_ = ""; + string hccAmdGpuTargetEnv_ = ""; + friend std::ostream& operator <<(std::ostream& os, const EnvVariables& var) { + os << "Path: " << var.path_ << endl; + os << "Hip Path: " << var.hipPathEnv_ << endl; + os << "Hip Rocclr Path: " << var.hipRocclrPathEnv_ << endl; + os << "Roccm Path: " << var.roccmPathEnv_ << endl; + os << "Cuda Path: " << var.cudaPathEnv_ << endl; + os << "Hsa Path: " << var.hsaPathEnv_ << endl; + os << "Hip Clang Path: " << var.hipClangPathEnv_ << endl; + os << "Hip Platform: " << var.hipPlatformEnv_ << endl; + os << "Hip Compiler: " << var.hipCompilerEnv_ << endl; + os << "Hip Runtime: " << var.hipRuntimeEnv_ << endl; + os << "LD Library Path: " << var.ldLibraryPathEnv_ << endl; + os << "Verbose: " << var.verboseEnv_ << endl; + os << "Hipcc Compile Flags Append: " << + var.hipccCompileFlagsAppendEnv_ << endl; + os << "Hipcc Link Flags Append: " << + var.hipccLinkFlagsAppendEnv_ << endl; + os << "Hip lib Path: " << var.hipLibPathEnv_ << endl; + os << "Device lib Path: " << var.deviceLibPathEnv_ << endl; + os << "Hip Clang HCC Compact mode: " << + var.hipClangHccCompactModeEnv_ << endl; + os << "Hip Compile Cxx as Hip: " << + var.hipCompileCxxAsHipEnv_ << endl; + os << "Hcc Amd Gpu Target: " << var.hccAmdGpuTargetEnv_ << endl; + return os; + } +}; + +enum HipBinCommand { + unknown = -1, + path, + roccmpath, + cpp_config, + compiler, + platform, + runtime, + hipclangpath, + full, + version, + check, + newline, + help, +}; + + + +class HipBinBase { + public: + HipBinBase(); + virtual ~HipBinBase() = default; + // Interface functions + virtual void constructCompilerPath() = 0; + virtual void printFull() = 0; + virtual bool detectPlatform() = 0; + virtual const string& getCompilerPath() const = 0; + virtual void printCompilerInfo() const = 0; + virtual string getCompilerVersion() = 0; + virtual const PlatformInfo& getPlatformInfo() const = 0; + virtual string getCppConfig() = 0; + virtual void checkHipconfig() = 0; + virtual string getDeviceLibPath() const = 0; + virtual string getHipLibPath() const = 0; + virtual string getHipCC() const = 0; + virtual string getHipInclude() const = 0; + virtual void initializeHipCXXFlags() = 0; + virtual void initializeHipCFlags() = 0; + virtual void initializeHipLdFlags() = 0; + virtual const string& getHipCXXFlags() const = 0; + virtual const string& getHipCFlags() const = 0; + virtual const string& getHipLdFlags() const = 0; + virtual void executeHipCCCmd(vector argv) = 0; + // Common functions used by all platforms + void getSystemInfo() const; + void printEnvironmentVariables() const; + const EnvVariables& getEnvVariables() const; + const OsType& getOSInfo() const; + const string& getHipPath() const; + const string& getRoccmPath() const; + const string& getHipVersion() const; + void printUsage() const; + bool canRunCompiler(string exeName, string& cmdOut); + HipBinCommand gethipconfigCmd(string argument); + const string& getrocm_pathOption() const; + const string& gethip_pathOption() const; + + protected: + // hipBinUtilPtr used by derived platforms + // so therefore its protected + HipBinUtil* hipBinUtilPtr_; + string rocm_pathOption_ = ""; + string hip_pathOption_ = ""; + void readOSInfo(); + void readEnvVariables(); + void constructHipPath(); + void constructRoccmPath(); + void readHipVersion(); + + private: + EnvVariables envVariables_, variables_; + OsType osInfo_; + string hipVersion_; + +}; + +HipBinBase::HipBinBase() { + hipBinUtilPtr_ = hipBinUtilPtr_->getInstance(); + readOSInfo(); // detects if windows or linux + readEnvVariables(); // reads the environment variables +} + +// detects the OS information +void HipBinBase::readOSInfo() { +#if defined _WIN32 || defined _WIN64 + osInfo_ = windows; +#elif defined __unix || defined __linux__ + osInfo_ = lnx; +#endif +} + + +// reads envirnoment variables +void HipBinBase::readEnvVariables() { + if (const char* path = std::getenv(PATH)) + envVariables_.path_ = path; + if (const char* hip = std::getenv(HIP_PATH)) + envVariables_.hipPathEnv_ = hip; + if (const char* hip_rocclr = std::getenv(HIP_ROCCLR_HOME)) + envVariables_.hipRocclrPathEnv_ = hip_rocclr; + if (const char* roccm = std::getenv(ROCM_PATH)) + envVariables_.roccmPathEnv_ = roccm; + if (const char* cuda = std::getenv(CUDA_PATH)) + envVariables_.cudaPathEnv_ = cuda; + if (const char* hsa = std::getenv(HSA_PATH)) + envVariables_.hsaPathEnv_ = hsa; + if (const char* hipClang = std::getenv(HIP_CLANG_PATH)) + envVariables_.hipClangPathEnv_ = hipClang; + if (const char* hipPlatform = std::getenv(HIP_PLATFORM)) + envVariables_.hipPlatformEnv_ = hipPlatform; + if (const char* hipCompiler = std::getenv(HIP_COMPILER)) + envVariables_.hipCompilerEnv_ = hipCompiler; + if (const char* hipRuntime = std::getenv(HIP_RUNTIME)) + envVariables_.hipRuntimeEnv_ = hipRuntime; + if (const char* ldLibaryPath = std::getenv(LD_LIBRARY_PATH)) + envVariables_.ldLibraryPathEnv_ = ldLibaryPath; + if (const char* hccAmdGpuTarget = std::getenv(HCC_AMDGPU_TARGET)) + envVariables_.hccAmdGpuTargetEnv_ = hccAmdGpuTarget; + if (const char* verbose = std::getenv(HIPCC_VERBOSE)) + envVariables_.verboseEnv_ = verbose; + if (const char* hipccCompileFlagsAppend = + std::getenv(HIPCC_COMPILE_FLAGS_APPEND)) + envVariables_.hipccCompileFlagsAppendEnv_ = hipccCompileFlagsAppend; + if (const char* hipccLinkFlagsAppend = std::getenv(HIPCC_LINK_FLAGS_APPEND)) + envVariables_.hipccLinkFlagsAppendEnv_ = hipccLinkFlagsAppend; + if (const char* hipLibPath = std::getenv(HIP_LIB_PATH)) + envVariables_.hipLibPathEnv_ = hipLibPath; + if (const char* deviceLibPath = std::getenv(DEVICE_LIB_PATH)) + envVariables_.deviceLibPathEnv_ = deviceLibPath; + if (const char* hipClangHccCompactMode = + std::getenv(HIP_CLANG_HCC_COMPAT_MODE)) + envVariables_.hipClangHccCompactModeEnv_ = hipClangHccCompactMode; + if (const char* hipCompileCxxAsHip = std::getenv(HIP_COMPILE_CXX_AS_HIP)) + envVariables_.hipCompileCxxAsHipEnv_ = hipCompileCxxAsHip; +} + +// constructs the HIP path +void HipBinBase::constructHipPath() { + // we need to use --hip-path option + string hip_path_name = gethip_pathOption(); + if (!hip_path_name.empty()) { + variables_.hipPathEnv_ = hip_path_name; + } else if (envVariables_.hipPathEnv_.empty()) { + fs::path full_path(hipcc::utils::getSelfPath()); + variables_.hipPathEnv_ = (full_path.parent_path()).string(); + } else { + variables_.hipPathEnv_ = envVariables_.hipPathEnv_; + } +} + + +// constructs the ROCM path +void HipBinBase::constructRoccmPath() { + // we need to use --rocm-path option + string rocm_path_name = getrocm_pathOption(); + + // chose the --rocm-path option first, if specified. + if (!rocm_path_name.empty()) + variables_.roccmPathEnv_ = rocm_path_name; + else if (envVariables_.roccmPathEnv_.empty()) { + variables_.roccmPathEnv_ = getHipPath(); + } else { + variables_.roccmPathEnv_ = envVariables_.roccmPathEnv_;} +} + +// reads the Hip Version +void HipBinBase::readHipVersion() { + string hipVersion; + const string& hipPath = getHipPath(); + fs::path hipVersionPath = hipPath; + const OsType& os = getOSInfo(); + if (os == windows) + hipVersionPath /= "bin/.hipVersion"; + else + hipVersionPath /= "share/hip/version"; + map hipVersionMap; + hipVersionMap = hipBinUtilPtr_->parseConfigFile(hipVersionPath); + + if (hipVersionMap.empty()) { + std::cerr << "Warning: HIP version file: " << hipVersionPath << " not found. Cannot give HIP version information." << endl; + return; + } else { + string hip_version_major, hip_version_minor, + hip_version_patch, hip_version_githash; + hip_version_major = hipBinUtilPtr_->readConfigMap( + hipVersionMap, "HIP_VERSION_MAJOR", + HIP_BASE_VERSION_DEFAULT); + hip_version_minor = hipBinUtilPtr_->readConfigMap( + hipVersionMap, "HIP_VERSION_MINOR", + HIP_BASE_VERSION_DEFAULT); + hip_version_patch = hipBinUtilPtr_->readConfigMap( + hipVersionMap, "HIP_VERSION_PATCH", + HIP_BASE_VERSION_DEFAULT); + hip_version_githash = hipBinUtilPtr_->readConfigMap( + hipVersionMap, "HIP_VERSION_GITHASH", + HIP_BASE_VERSION_DEFAULT); + hipVersion = hip_version_major + "." + hip_version_minor + + "." + hip_version_patch + "-" + hip_version_githash; + hipVersion_ = hipVersion; + } +} + +// prints system information +void HipBinBase::getSystemInfo() const { + const OsType& os = getOSInfo(); + if (os == windows) { + cout << endl << "== Windows Display Drivers" << endl; + cout << "Hostname :"; + system("hostname"); + system("powershell -c \"Get-CIMInstance -query 'SELECT * FROM win32_VideoController' | " + "ft AdapterCompatibility,InstalledDisplayDrivers,Name | " + "Out-String -Width 1000 | findstr /B /C:'Advanced Micro Devices'\""); + } else { + assert(os == lnx); + cout << endl << "== Linux Kernel" << endl; + cout << "Hostname :" << endl; + system("hostname"); + system("uname -a"); + } +} + +// prints the envirnoment variables +void HipBinBase::printEnvironmentVariables() const { + const OsType& os = getOSInfo(); + if (os == windows) { + cout << "PATH=" << envVariables_.path_ << "\n" << endl; + system("set | findstr" + " /B /C:\"HIP\" /C:\"HSA\" /C:\"CUDA\" /C:\"LD_LIBRARY_PATH\""); + } else { + string cmd = "echo PATH ="; + cmd += envVariables_.path_; + system(cmd.c_str()); + system("env | egrep '^HIP|^HSA|^CUDA|^LD_LIBRARY_PATH'"); + } +} + +// returns envirnoment variables +const EnvVariables& HipBinBase::getEnvVariables() const { + return envVariables_; +} + + +// returns the os information +const OsType& HipBinBase::getOSInfo() const { + return osInfo_; +} + +// returns the HIP path +const string& HipBinBase::getHipPath() const { + return variables_.hipPathEnv_; +} + +// returns the Roccm path +const string& HipBinBase::getRoccmPath() const { + return variables_.roccmPathEnv_; +} + +// returns the Hip Version +const string& HipBinBase::getHipVersion() const { + return hipVersion_; +} + +// prints the help text +void HipBinBase::printUsage() const { + cout << "usage: hipconfig [OPTIONS]\n"; + cout << " --path, -p :" + " print HIP_PATH (use env var if set, else determine from hipconfig path)\n"; + cout << " --rocmpath, -R :" + " print ROCM_PATH (use env var if set," + " else determine from hip path or /opt/rocm)\n"; + cout << " --cpp_config, -C : print C++ compiler options\n"; + cout << " --compiler, -c : print compiler (clang or nvcc)\n"; + cout << " --platform, -P : print platform (amd or nvidia)\n"; + cout << " --runtime, -r : print runtime (rocclr or cuda)\n"; + cout << " --hipclangpath, -l : print HIP_CLANG_PATH\n"; + cout << " --full, -f : print full config\n"; + cout << " --version, -v : print hip version\n"; + cout << " --check : check configuration\n"; + cout << " --newline, -n : print newline\n"; + cout << " --help, -h : print help message\n"; +} + + + +// compiler canRun or not +bool HipBinBase::canRunCompiler(string exeName, string& cmdOut) { + bool executable = false; + SystemCmdOut sysOut = hipBinUtilPtr_->exec((exeName + " --version").c_str()); + if (sysOut.exitCode != 0) { + executable = false; + } else { + executable = true; + cmdOut += sysOut.out; + } + return executable; +} + +HipBinCommand HipBinBase::gethipconfigCmd(string argument) { + vector pathStrs = { "-p", "--path", "-path", "--p" }; + if (hipBinUtilPtr_->checkCmd(pathStrs, argument)) + return path; + vector rocmPathStrs = { "-R", "--rocmpath", "-rocmpath", "--R" }; + if (hipBinUtilPtr_->checkCmd(rocmPathStrs, argument)) + return roccmpath; + vector cppConfigStrs = { "-C", "--cpp_config", + "-cpp_config", "--C", }; + if (hipBinUtilPtr_->checkCmd(cppConfigStrs, argument)) + return cpp_config; + vector CompilerStrs = { "-c", "--compiler", "-compiler", "--c" }; + if (hipBinUtilPtr_->checkCmd(CompilerStrs, argument)) + return compiler; + vector platformStrs = { "-P", "--platform", "-platform", "--P" }; + if (hipBinUtilPtr_->checkCmd(platformStrs, argument)) + return platform; + vector runtimeStrs = { "-r", "--runtime", "-runtime", "--r" }; + if (hipBinUtilPtr_->checkCmd(runtimeStrs, argument)) + return runtime; + vector hipClangPathStrs = { "-l", "--hipclangpath", + "-hipclangpath", "--l" }; + if (hipBinUtilPtr_->checkCmd(hipClangPathStrs, argument)) + return hipclangpath; + vector fullStrs = { "-f", "--full", "-full", "--f" }; + if (hipBinUtilPtr_->checkCmd(fullStrs, argument)) + return full; + vector versionStrs = { "-v", "--version", "-version", "--v" }; + if (hipBinUtilPtr_->checkCmd(versionStrs, argument)) + return version; + vector checkStrs = { "--check", "-check" }; + if (hipBinUtilPtr_->checkCmd(checkStrs, argument)) + return check; + vector newlineStrs = { "--n", "-n", "--newline", "-newline" }; + if (hipBinUtilPtr_->checkCmd(newlineStrs, argument)) + return newline; + vector helpStrs = { "-h", "--help", "-help", "--h" }; + if (hipBinUtilPtr_->checkCmd(helpStrs, argument)) + return help; + return full; // default is full. return full if no commands are matched +} + +const string& HipBinBase::getrocm_pathOption() const { + return rocm_pathOption_; +} + +const string& HipBinBase::gethip_pathOption() const { + return hip_pathOption_; +} + +#endif // SRC_HIPBIN_BASE_H_ diff --git a/amd/hipcc/src/hipBin_nvidia.h b/amd/hipcc/src/hipBin_nvidia.h new file mode 100644 index 0000000000000..a1b1fecb848bb --- /dev/null +++ b/amd/hipcc/src/hipBin_nvidia.h @@ -0,0 +1,631 @@ +/* +Copyright (c) 2021 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#ifndef SRC_HIPBIN_NVIDIA_H_ +#define SRC_HIPBIN_NVIDIA_H_ + +#include "hipBin_base.h" +#include "hipBin_util.h" +#include +#include +#include + +class HipBinNvidia : public HipBinBase { + private: + string cudaPath_ = ""; + PlatformInfo platformInfoNV_; + string hipCFlags_, hipCXXFlags_, hipLdFlags_; + + public: + HipBinNvidia(); + ~HipBinNvidia() override = default; + virtual bool detectPlatform(); + virtual void constructCompilerPath(); + virtual const string& getCompilerPath() const; + virtual const PlatformInfo& getPlatformInfo() const; + virtual string getCppConfig(); + virtual void printFull(); + virtual void printCompilerInfo() const; + virtual string getCompilerVersion(); + virtual void checkHipconfig(); + virtual string getDeviceLibPath() const; + virtual string getHipLibPath() const; + virtual string getHipCC() const; + virtual string getCompilerIncludePath(); + virtual string getHipInclude() const; + virtual void initializeHipCXXFlags(); + virtual void initializeHipCFlags(); + virtual void initializeHipLdFlags(); + virtual const string& getHipCXXFlags() const; + virtual const string& getHipCFlags() const; + virtual const string& getHipLdFlags() const; + virtual void executeHipCCCmd(vector argv); +}; + +HipBinNvidia::HipBinNvidia() { + PlatformInfo platformInfo; + platformInfo.os = getOSInfo(); + platformInfo.platform = nvidia; + platformInfo.runtime = cuda; + platformInfo.compiler = nvcc; + platformInfoNV_ = platformInfo; + constructHipPath(); + constructRoccmPath(); + constructCompilerPath(); + readHipVersion(); +} + +// detects if cuda is installed +bool HipBinNvidia::detectPlatform() { + string out; + const string& nvccPath = getCompilerPath(); + fs::path cmdNv = nvccPath; + cmdNv /= "bin/nvcc"; + const OsType& os = getOSInfo(); + const EnvVariables& var = getEnvVariables(); + bool detected = false; + if (var.hipPlatformEnv_.empty()) { + if (canRunCompiler(cmdNv.string(), out) || (canRunCompiler("nvcc", out))) { + detected = true; + } + } else { + if (var.hipPlatformEnv_ == "nvidia" || var.hipPlatformEnv_ == "nvcc") { + detected = true; + if (var.hipPlatformEnv_ == "nvcc") + std::cerr << "Warning: HIP_PLATFORM=nvcc is deprecated." + << "Please use HIP_PLATFORM=nvidia." << endl; + } + } + return detected; +} + + + +// returns device lib path +string HipBinNvidia::getDeviceLibPath() const { + cout << "TODO Not required for now" << endl; + return ""; +} + +// returns compiler path +string HipBinNvidia::getHipCC() const { + string hipCC; + const string& cudaPath = getCompilerPath(); + fs::path hipCCPath; + hipCCPath = cudaPath; + hipCCPath /= "bin/nvcc"; + hipCC = hipCCPath.string(); + if (getOSInfo() == windows) + hipCC = "\"" + hipCC + "\""; + return hipCC; +} + +// returns compiler include path +string HipBinNvidia::getCompilerIncludePath() { + cout << "TODO Not required for now" << endl; + return ""; +} + + +// checks Hipconfig +void HipBinNvidia::checkHipconfig() { + cout << endl << "Check system installation: " << endl; + cout << "check hipconfig in PATH..." << endl; + if (system("which hipconfig > /dev/null 2>&1") != 0) { + std::cerr << "FAIL " << endl; + } else { + cout << "good" << endl; + } +} + +// prints full +void HipBinNvidia::printFull() { + const string& hipVersion = getHipVersion(); + const string& hipPath = getHipPath(); + const string& roccmPath = getRoccmPath(); + const PlatformInfo& platformInfo = getPlatformInfo(); + const string& ccpConfig = getCppConfig(); + const string& cudaPath = getCompilerPath(); + cout << "HIP version: " << hipVersion << endl; + cout << endl << "==hipconfig" << endl; + cout << "HIP_PATH :" << hipPath << endl; + cout << "ROCM_PATH :" << roccmPath << endl; + cout << "HIP_COMPILER :" << CompilerTypeStr( + platformInfo.compiler) << endl; + cout << "HIP_PLATFORM :" << PlatformTypeStr( + platformInfo.platform) << endl; + cout << "HIP_RUNTIME :" << RuntimeTypeStr( + platformInfo.runtime) << endl; + cout << "CPP_CONFIG :" << ccpConfig << endl; + cout << endl << "== nvcc" << endl; + cout << "CUDA_PATH :" << cudaPath < argv) { + if (argv.size() < 2) { + cout<< "No Arguments passed, exiting ...\n"; + exit(EXIT_SUCCESS); + } + const EnvVariables& var = getEnvVariables(); + int verbose = 0; + if (!var.verboseEnv_.empty()) + verbose = stoi(var.verboseEnv_); + // Verbose: 0x1=commands, 0x2=paths, 0x4=hipcc args + // set if user explicitly requests -stdlib=libc++. + // (else we default to libstdc++ for better interop with g++): + bool setStdLib = 0; + bool default_amdgpu_target = 1; + bool compileOnly = 0; + bool needCXXFLAGS = 0; // need to add CXX flags to compile step + bool needCFLAGS = 0; // need to add C flags to compile step + bool needLDFLAGS = 1; // need to add LDFLAGS to compile step. + bool fileTypeFlag = 0; // to see if -x flag is mentioned + bool hasOMPTargets = 0; // If OMP targets is mentioned + bool hasC = 0; // options contain a c-style file + // options contain a cpp-style file (NVCC must force recognition as GPU file) + bool hasCXX = 0; + // options contain a cu-style file (HCC must force recognition as GPU file) + bool hasCU = 0; + // options contain a hip-style file (HIP-Clang must pass offloading options) + bool hasHIP = 0; + bool printHipVersion = 0; // print HIP version + bool printCXXFlags = 0; // print HIPCXXFLAGS + bool printLDFlags = 0; // print HIPLDFLAGS + bool runCmd = 1; + bool buildDeps = 0; + bool linkType = 1; + bool setLinkType = 0; + string hsacoVersion; + bool funcSupp = 0; // enable function support + bool rdc = 0; // whether -fgpu-rdc is on + string prevArg; + // TODO(hipcc): convert toolArgs to an array rather than a string + string toolArgs; + string optArg; + vector options, inputs; + // TODO(hipcc): hipcc uses --amdgpu-target for historical reasons. + // It should be replaced by clang option --offload-arch. + vector targetOpts = {"--offload-arch=", "--amdgpu-target="}; + string targetsStr; + bool skipOutputFile = false; + const OsType& os = getOSInfo(); + string hip_compile_cxx_as_hip; + if (var.hipCompileCxxAsHipEnv_.empty()) { + hip_compile_cxx_as_hip = "1"; + } else { + hip_compile_cxx_as_hip = var.hipCompileCxxAsHipEnv_; + } + string HIPLDARCHFLAGS; + initializeHipCXXFlags(); + initializeHipCFlags(); + initializeHipLdFlags(); + string HIPCXXFLAGS, HIPCFLAGS, HIPLDFLAGS; + HIPCFLAGS = getHipCFlags(); + HIPCXXFLAGS = getHipCXXFlags(); + HIPLDFLAGS = getHipLdFlags(); + string hipPath; + hipPath = getHipPath(); + const PlatformInfo& platformInfo = getPlatformInfo(); + const string& nvccPath = getCompilerPath(); + const string& hipVersion = getHipVersion(); + if (verbose & 0x2) { + cout << "HIP_PATH=" << hipPath << endl; + cout << "HIP_PLATFORM=" << PlatformTypeStr(platformInfo.platform) <substringPresent(isaarg,"--rocm-path=") || + hipBinUtilPtr_->substringPresent(isaarg,"--hip-path=")) { + ISACMD += "-I" + hipcc::utils::splitStr(isaarg, '=')[1] + "/include"; + } else { + ISACMD += isaarg; + } + } + if (verbose & 0x1) { + cout<< "hipcc-cmd: " << ISACMD << "\n"; + } + system(ISACMD.c_str()); + exit(EXIT_SUCCESS); + } + for (unsigned int argcount = 1; argcount < argv.size(); argcount++) { + // Save $arg, it can get changed in the loop. + string arg = argv.at(argcount); + regex toRemove("\\s+"); + // TODO(hipcc): figure out why this space removal is wanted. + // TODO(hipcc): If someone has gone to the effort of quoting + // the spaces to the shell + // TODO(hipcc): why are we removing it here? + string trimarg = hipBinUtilPtr_->replaceRegex(arg, toRemove, ""); + bool swallowArg = false; + bool escapeArg = true; + // do not pass amd paths to nvcc + if (hipBinUtilPtr_->substringPresent(arg,"--rocm-path=") || + hipBinUtilPtr_->substringPresent(arg,"--hip-path=")) { + continue; + } + + if (arg == "-c" || arg == "--genco" || arg == "-E") { + compileOnly = true; + needLDFLAGS = false; + } + if (skipOutputFile) { + // TODO(hipcc): handle filename with shell metacharacters + toolArgs += " \"" + arg +"\""; + prevArg = arg; + skipOutputFile = 0; + continue; + } + if (arg == "-o") { + needLDFLAGS = 1; + skipOutputFile = 1; + } + if ((trimarg == "-stdlib=libc++") && (setStdLib == 0)) { + HIPCXXFLAGS += " -stdlib=libc++"; + setStdLib = 1; + } + // Check target selection option: --offload-arch= and --amdgpu-target=... + for (unsigned int i = 0; i stringRegexMatch(arg, pattern)) { + // If targets string is not empty, add a comma before + // adding new target option value. + targetsStr.size() >0 ? targetsStr += ",": targetsStr += ""; + targetsStr += arg.substr(targetOpt.size()); + default_amdgpu_target = 0; + } + } + if (trimarg == "--version") { + printHipVersion = 1; + } + if (trimarg == "--short-version") { + printHipVersion = 1; + runCmd = 0; + } + if (trimarg == "--cxxflags") { + printCXXFlags = 1; + runCmd = 0; + } + if (trimarg == "--ldflags") { + printLDFlags = 1; + runCmd = 0; + } + if (trimarg == "-M") { + compileOnly = 1; + buildDeps = 1; + } + if (trimarg == "-use_fast_math") { + HIPCXXFLAGS += " -DHIP_FAST_MATH "; + HIPCFLAGS += " -DHIP_FAST_MATH "; + } + if ((trimarg == "-use-staticlib") && (setLinkType == 0)) { + linkType = 0; + setLinkType = 1; + swallowArg = 1; + } + if ((trimarg == "-use-sharedlib") && (setLinkType == 0)) { + linkType = 1; + setLinkType = 1; + } + if (hipBinUtilPtr_->stringRegexMatch(arg, "^-O.*")) { + optArg = arg; + } + if (hipBinUtilPtr_->substringPresent( + arg, "--amdhsa-code-object-version=")) { + arg = hipBinUtilPtr_->replaceStr( + arg, "--amdhsa-code-object-version=", ""); + hsacoVersion = arg; + swallowArg = 1; + } + // nvcc does not handle standard compiler options properly + // This can prevent hipcc being used as standard CXX/C Compiler + // To fix this we need to pass -Xcompiler for options + if (arg == "-fPIC" || hipBinUtilPtr_->substringPresent(arg, "-Wl,")) { + HIPCXXFLAGS += " -Xcompiler "+ arg; + swallowArg = 1; + } + if (arg == "-x") { + fileTypeFlag = 1; + } else if ((arg == "c" && prevArg == "-x") || (arg == "-xc")) { + fileTypeFlag = 1; + hasC = 1; + hasCXX = 0; + hasHIP = 0; + } else if ((arg == "c++" && prevArg == "-x") || (arg == "-xc++")) { + fileTypeFlag = 1; + hasC = 0; + hasCXX = 1; + hasHIP = 0; + } else if ((arg == "hip" && prevArg == "-x") || (arg == "-xhip")) { + fileTypeFlag = 1; + hasC = 0; + hasCXX = 0; + hasHIP = 1; + } else if (hipBinUtilPtr_->substringPresent(arg, "-fopenmp-targets=")) { + hasOMPTargets = 1; + } else if (hipBinUtilPtr_->stringRegexMatch(arg, "^-.*")) { + if (arg == "-fgpu-rdc") { + rdc = 1; + } else if (arg == "-fno-gpu-rdc") { + rdc = 0; + } + if (hipBinUtilPtr_->stringRegexMatch(arg, "^--hipcc.*")) { + swallowArg = 1; + if (arg == "--hipcc-func-supp") { + funcSupp = 1; + } else if (arg == "--hipcc-no-func-supp") { + funcSupp = 0; + } + } else { + options.push_back(arg); + } + } else if (prevArg != "-o") { + if (fileTypeFlag == 0) { + if (hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.c$")) { + hasC = 1; + needCFLAGS = 1; + toolArgs += " -x c"; + } else if ((hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.cpp$")) || + (hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.cxx$")) || + (hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.cc$")) || + (hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.C$"))) { + needCXXFLAGS = 1; + hasCXX = 1; + } else if (((hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.cu$") || + hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.cuh$")) && + hip_compile_cxx_as_hip != "0") || + (hipBinUtilPtr_->stringRegexMatch(arg, ".*\\.hip$"))) { + needCXXFLAGS = 1; + hasCU = 1; + } + } + if (hasC) { + needCFLAGS = 1; + } else if (hasCXX || hasHIP) { + needCXXFLAGS = 1; + } + inputs.push_back(arg); + } + // Windows needs different quoting, ignore for now + if (os != windows && escapeArg) { + regex reg("[^-a-zA-Z0-9_=+,.\\/]"); + arg = regex_replace(arg, reg, "\\$&"); + } + if (!swallowArg) + toolArgs += " " + arg; + prevArg = arg; + } // end of for loop + if (hasCXX) { + HIPCXXFLAGS += " -x cu"; + } + if (buildDeps) { + HIPCXXFLAGS += " -M -D__CUDACC__"; + HIPCFLAGS += " -M -D__CUDACC__"; + } + string compiler; + compiler = getHipCC(); + string CMD = compiler; + if (needCFLAGS) { + CMD += " " + HIPCFLAGS; + } + if (needCXXFLAGS) { + CMD += " " + HIPCXXFLAGS; + } + if (needLDFLAGS && !compileOnly) { + CMD += " " + HIPLDFLAGS; + } + CMD += " " + toolArgs; + if ((needCFLAGS || needCXXFLAGS) && + !var.hipccCompileFlagsAppendEnv_.empty()) { + CMD.append("\" "); + CMD.append(var.hipccCompileFlagsAppendEnv_); + CMD.append("\" "); + } + if (needLDFLAGS && !compileOnly && !var.hipccLinkFlagsAppendEnv_.empty()) { + CMD.append("\" "); + CMD.append(var.hipccLinkFlagsAppendEnv_); + CMD.append("\" "); + } + if (verbose & 0x1) { + cout << "hipcc-cmd: " << CMD << "\n"; + } + if (printHipVersion) { + if (runCmd) { + cout << "HIP version: "; + } + cout << hipVersion << endl; + } + if (printCXXFlags) { + cout << HIPCXXFLAGS; + } + if (printLDFlags) { + cout << HIPLDFLAGS; + } + if (runCmd) { + SystemCmdOut sysOut; + if (os == windows) + CMD = "\"" + CMD + "\""; + + sysOut = hipBinUtilPtr_->exec(CMD.c_str(), true); + string cmdOut = sysOut.out; + int CMD_EXIT_CODE = sysOut.exitCode; + if (CMD_EXIT_CODE !=0) { + cout << "failed to execute:" << CMD << std::endl; + } + exit(CMD_EXIT_CODE); + } +} // end of function + + +#endif // SRC_HIPBIN_NVIDIA_H_ diff --git a/amd/hipcc/src/hipBin_util.h b/amd/hipcc/src/hipBin_util.h new file mode 100644 index 0000000000000..6cefbe0787cf5 --- /dev/null +++ b/amd/hipcc/src/hipBin_util.h @@ -0,0 +1,268 @@ +/* +Copyright (c) 2021 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#ifndef SRC_HIPBIN_UTIL_H_ +#define SRC_HIPBIN_UTIL_H_ + +#include "filesystem.h" + +#include "utils.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#if defined(_WIN32) || defined(_WIN64) +#include +#include +#include +#ifdef _UNICODE + typedef wchar_t TCHAR; + typedef std::wstring TSTR; + typedef std::wstring::size_type TSIZE; +#define ENDLINE L"/\\" +#else + typedef char TCHAR; + typedef std::string TSTR; + typedef std::string::size_type TSIZE; +#define ENDLINE "/\\" +#endif +#else +#include +#endif + +using std::cout; +using std::endl; +using std::vector; +using std::string; +using std::ifstream; +using std::ofstream; +using std::regex; +using std::regex_match; +using std::regex_search; +using std::regex_replace; +using std::map; +using std::smatch; +using std::stringstream; + + +struct SystemCmdOut { + string out; + int exitCode = 0; +}; + +class HipBinUtil { + public: + static HipBinUtil* getInstance() { + if (!instance) + instance = new HipBinUtil; + return instance; + } + virtual ~HipBinUtil(); + // Common helper functions + string replaceStr(const string& s, const string& toReplace, + const string& replaceWith) const; + string replaceRegex(const string& s, regex toReplace, + string replaceWith) const; + SystemCmdOut exec(const char* cmd, bool printConsole) const; + string getTempDir(); + void deleteTempFiles(); + string mktempFile(string name); + string readConfigMap(map hipVersionMap, + string keyName, string defaultValue) const; + map parseConfigFile(fs::path configPath) const; + bool substringPresent(string fullString, string subString) const; + bool stringRegexMatch(string fullString, string pattern) const; + bool checkCmd(const vector& commands, const string& argument); + + private: + HipBinUtil() {} + vector tmpFiles_; + static HipBinUtil *instance; +}; + +HipBinUtil *HipBinUtil::instance = 0; + +// deleting temp files created +HipBinUtil::~HipBinUtil() { + deleteTempFiles(); +} + +// create temp file with the template name +string HipBinUtil::mktempFile(string name) { + string fileName; +#if defined(_WIN32) || defined(_WIN64) + fileName = _mktemp(&name[0]); +#else + fileName = mkstemp(&name[0]); +#endif + tmpFiles_.push_back(fileName); + return fileName; +} + +// matches the pattern in the string +bool HipBinUtil::stringRegexMatch(string fullString, string pattern) const { + return regex_match(fullString, regex(pattern)); +} + +// subtring is present in string +bool HipBinUtil::substringPresent(string fullString, string subString) const { + return fullString.find(subString) != string::npos; +} + +// replaces the toReplace string with replaceWith string. Returns the new string +string HipBinUtil::replaceStr(const string& s, const string& toReplace, + const string& replaceWith) const { + string out = s; + std::size_t pos = out.find(toReplace); + if (pos == string::npos) return out; + return out.replace(pos, toReplace.length(), replaceWith); +} + +// replaces the toReplace regex pattern with replaceWith string. +// Returns the new string +string HipBinUtil::replaceRegex(const string& s, regex toReplace, + string replaceWith) const { + string out = s; + while (regex_search(out, toReplace)) { + out = regex_replace(out, toReplace, replaceWith); + } + return out; +} + +// reads the config file and stores it in a map for access +map HipBinUtil::parseConfigFile(fs::path configPath) const { + map configMap; + ifstream isFile(configPath.string()); + string line; + if (isFile.is_open()) { + while (std::getline(isFile, line)) { + std::istringstream is_line(line); + string key; + if (std::getline(is_line, key, '=')) { + string value; + if (std::getline(is_line, value)) { + configMap.insert({ key, value }); + } + } + } + isFile.close(); + } + return configMap; +} + +// Delete all created temporary files +void HipBinUtil::deleteTempFiles() { + // Deleting temp files vs the temp directory + for (unsigned int i = 0; i < tmpFiles_.size(); i++) { + try { + if (!fs::remove(tmpFiles_.at(i))) + std::cerr << "Error deleting temp name: "<< tmpFiles_.at(i) < hipVersionMap, + string keyName, string defaultValue) const { + auto it = hipVersionMap.find(keyName); + if (it != hipVersionMap.end()) { + return it->second; + } + return defaultValue; +} + + + +bool HipBinUtil::checkCmd(const vector& commands, + const string& argument) { + bool found = false; + for (unsigned int i = 0; i < commands.size(); i++) { + if (argument.compare(commands.at(i)) == 0) { + found = true; + break; + } + } + return found; +} + + + +#endif // SRC_HIPBIN_UTIL_H_ diff --git a/amd/hipcc/src/hipcc.cpp b/amd/hipcc/src/hipcc.cpp new file mode 100644 index 0000000000000..58a90fa3f77d5 --- /dev/null +++ b/amd/hipcc/src/hipcc.cpp @@ -0,0 +1,35 @@ +/* +Copyright (c) 2021 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#include "hipBin.h" + +int main(int argc, char* argv[]){ + HipBin hipbin; + vector& platformPtrs = hipbin.getHipBinPtrs(); + vector argvcc; + for (int i = 0; i < argc; i++) { + argvcc.push_back(argv[i]); + } + // 0th index points to the first platform detected. + // In the near future this vector will contain mulitple devices + platformPtrs.at(0)->executeHipCCCmd(argvcc); +} diff --git a/amd/hipcc/src/hipconfig.cpp b/amd/hipcc/src/hipconfig.cpp new file mode 100644 index 0000000000000..69bd664e81a3b --- /dev/null +++ b/amd/hipcc/src/hipconfig.cpp @@ -0,0 +1,69 @@ +/* +Copyright (c) 2021 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#include "hipBin.h" + +int main(int argc, char* argv[]){ + HipBin hipbin; + vector& platformPtrs = hipbin.getHipBinPtrs(); + for (unsigned int j = 0; j < platformPtrs.size(); j++) { + if (argc == 1) { + platformPtrs.at(j)->printFull(); + } + for (int i = 1; i < argc; ++i) { + HipBinCommand cmd; + cmd = platformPtrs.at(j)->gethipconfigCmd(argv[i]); + switch (cmd) { + case help: platformPtrs.at(j)->printUsage(); + break; + case path: cout << platformPtrs.at(j)->getHipPath(); + break; + case roccmpath: cout << platformPtrs.at(j)->getRoccmPath(); + break; + case cpp_config: cout << platformPtrs.at(j)->getCppConfig(); + break; + case compiler: cout << CompilerTypeStr(( + platformPtrs.at(j)->getPlatformInfo()).compiler); + break; + case platform: cout << PlatformTypeStr(( + platformPtrs.at(j)->getPlatformInfo()).platform); + break; + case runtime: cout << RuntimeTypeStr(( + platformPtrs.at(j)->getPlatformInfo()).runtime); + break; + case hipclangpath: cout << platformPtrs.at(j)->getCompilerPath(); + break; + case full: platformPtrs.at(j)->printFull(); + break; + case version: cout << platformPtrs.at(j)->getHipVersion(); + break; + case check: platformPtrs.at(j)->checkHipconfig(); + break; + case newline: cout << endl; + break; + default: + platformPtrs.at(j)->printUsage(); + break; + } + } + } +} diff --git a/amd/hipcc/src/utils.cpp b/amd/hipcc/src/utils.cpp new file mode 100644 index 0000000000000..cc088ae997d33 --- /dev/null +++ b/amd/hipcc/src/utils.cpp @@ -0,0 +1,61 @@ +#include "utils.h" +#include "filesystem.h" + +#if defined(_WIN32) || defined(_WIN64) +#include +#include +#include +#ifdef _UNICODE +typedef wchar_t TCHAR; +typedef std::wstring TSTR; +typedef std::wstring::size_type TSIZE; +#define ENDLINE L"/\\" +#else +typedef char TCHAR; +typedef std::string TSTR; +typedef std::string::size_type TSIZE; +#define ENDLINE "/\\" +#endif +#else +#include +#endif + +#include +#include + +std::string hipcc::utils::getSelfPath() { + constexpr size_t MAX_PATH_CHAR = 1024; + std::string path; +#if defined(_WIN32) || defined(_WIN64) + TCHAR buffer[MAX_PATH] = {0}; + GetModuleFileName(NULL, buffer, MAX_PATH_CHAR); + TSIZE pos = TSTR(buffer).find_last_of(ENDLINE); + TSTR wide = TSTR(buffer).substr(0, pos); + path = std::string(wide.begin(), wide.end()); +#else + char buff[MAX_PATH_CHAR]; + ssize_t len = ::readlink("/proc/self/exe", buff, sizeof(buff) - 1); + if (len > 0) { + buff[len] = '\0'; + path = std::string(buff); + fs::path exePath(path); + path = exePath.parent_path().string(); + } else { + std::cerr << "readlink: Error reading the exe path" << std::endl; + perror("readlink"); + exit(-1); + } +#endif + return path; +} + +std::vector hipcc::utils::splitStr(std::string const &fullStr, + char delimiter) { + std::vector tokens; + std::stringstream check1(fullStr); + std::string intermediate; + while (std::getline(check1, intermediate, delimiter)) { + tokens.emplace_back(std::move(intermediate)); + } + return tokens; +} \ No newline at end of file diff --git a/amd/hipcc/src/utils.h b/amd/hipcc/src/utils.h new file mode 100644 index 0000000000000..426a09e431008 --- /dev/null +++ b/amd/hipcc/src/utils.h @@ -0,0 +1,18 @@ +#ifndef HIP_UTILS_H +#define HIP_UTILS_H + +#include +#include + +namespace hipcc { +namespace utils { +// gets the path of the executable name +std::string getSelfPath(); + +// splits the string with the delimiter +std::vector splitStr(std::string const &fullStr, char delimiter); + +} // namespace utils +} // namespace hipcc + +#endif diff --git a/clang-tools-extra/CMakeLists.txt b/clang-tools-extra/CMakeLists.txt index 87050db4e0e75..f3d01811aa813 100644 --- a/clang-tools-extra/CMakeLists.txt +++ b/clang-tools-extra/CMakeLists.txt @@ -6,7 +6,7 @@ include(GNUInstallDirs) option(CLANG_TIDY_ENABLE_STATIC_ANALYZER "Include static analyzer checks in clang-tidy" ON) option(CLANG_TIDY_ENABLE_QUERY_BASED_CUSTOM_CHECKS - "Enable query-based custom checks in clang-tidy" ON) + "Enable query-based custom checks in clang-tidy" OFF) if(CLANG_INCLUDE_TESTS) umbrella_lit_testsuite_begin(check-clang-tools) @@ -31,6 +31,12 @@ add_subdirectory(include-cleaner) add_subdirectory(pp-trace) add_subdirectory(tool-template) +# Add the common testsuite after all the tools. +if(CLANG_INCLUDE_TESTS) +add_subdirectory(test) +add_subdirectory(unittests) +endif() + option(CLANG_TOOLS_EXTRA_INCLUDE_DOCS "Generate build targets for the Clang Extra Tools docs." ${LLVM_INCLUDE_DOCS}) if( CLANG_TOOLS_EXTRA_INCLUDE_DOCS ) @@ -43,10 +49,3 @@ CMAKE_DEPENDENT_OPTION(CLANG_ENABLE_CLANGD "Build clangd language server" ON if (CLANG_ENABLE_CLANGD) add_subdirectory(clangd) endif() - -# Add the common testsuite after all the tools. -if(CLANG_INCLUDE_TESTS) - add_subdirectory(test) - add_subdirectory(unittests) - umbrella_lit_testsuite_end(check-clang-tools) -endif() diff --git a/clang-tools-extra/clang-tidy/llvm/CMakeLists.txt b/clang-tools-extra/clang-tidy/llvm/CMakeLists.txt index 78ef0444305ff..a77417153eeff 100644 --- a/clang-tools-extra/clang-tidy/llvm/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/llvm/CMakeLists.txt @@ -18,6 +18,7 @@ add_clang_library(clangTidyLLVMModule STATIC clangTidy clangTidyReadabilityModule clangTidyUtils + clangTransformer DEPENDS omp_gen diff --git a/clang-tools-extra/docs/conf.py b/clang-tools-extra/docs/conf.py index feb7a1da63643..52155d3a38f9e 100644 --- a/clang-tools-extra/docs/conf.py +++ b/clang-tools-extra/docs/conf.py @@ -78,10 +78,17 @@ # A list of ignored prefixes for module index sorting. # modindex_common_prefix = [] -in_progress_title = "(In-Progress) " if tags.has("PreRelease") else "" +# TODO: Temporary workaround for configuration error to get man pages built +# Error: "There is a syntax error in your configuration file: invalid syntax (conf.py, line 91)" -rst_epilog = f""" -.. |ReleaseNotesTitle| replace:: {in_progress_title} Release Notes +# in_progress_title = "(In-Progress) " if tags.has("PreRelease") else "" + +# rst_epilog = f""" +# .. |ReleaseNotesTitle| replace:: {in_progress_title} Release Notes +# """ + +rst_epilog = """ +.. |ReleaseNotesTitle| replace:: Release Notes """ # -- Options for HTML output --------------------------------------------------- diff --git a/clang/CMakeLists.txt b/clang/CMakeLists.txt index e4cb1a359620d..a5db73b11daf9 100644 --- a/clang/CMakeLists.txt +++ b/clang/CMakeLists.txt @@ -288,6 +288,31 @@ set(CLANG_DEFAULT_OBJCOPY "objcopy" CACHE STRING set(CLANG_DEFAULT_OPENMP_RUNTIME "libomp" CACHE STRING "Default OpenMP runtime used by -fopenmp.") +# OpenMP offloading requires at least sm_35 because we use shuffle instructions +# to generate efficient code for reductions and the atomicMax instruction on +# 64-bit integers in the implementation of conditional lastprivate. +set(CUDA_ARCH_FLAGS "sm_35") + +# Try to find the highest Nvidia GPU architecture the system supports +if (NOT DEFINED CLANG_OPENMP_NVPTX_DEFAULT_ARCH) + find_package(CUDA QUIET) + if (CUDA_FOUND) + cuda_select_nvcc_arch_flags(CUDA_ARCH_FLAGS) + endif() +else() + set(CUDA_ARCH_FLAGS ${CLANG_OPENMP_NVPTX_DEFAULT_ARCH}) +endif() + +string(REGEX MATCH "sm_([0-9]+)" CUDA_ARCH_MATCH ${CUDA_ARCH_FLAGS}) +if (NOT DEFINED CUDA_ARCH_MATCH OR "${CMAKE_MATCH_1}" LESS 35) + set(CLANG_OPENMP_NVPTX_DEFAULT_ARCH "sm_35" CACHE STRING + "Default architecture for OpenMP offloading to Nvidia GPUs." FORCE) + message(WARNING "Resetting default architecture for OpenMP offloading to Nvidia GPUs to sm_35") +else() + set(CLANG_OPENMP_NVPTX_DEFAULT_ARCH ${CUDA_ARCH_MATCH} CACHE STRING + "Default architecture for OpenMP offloading to Nvidia GPUs.") +endif() + set(CLANG_SYSTEMZ_DEFAULT_ARCH "z10" CACHE STRING "SystemZ Default Arch") set(CLANG_VENDOR ${PACKAGE_VENDOR} CACHE STRING diff --git a/clang/docs/ClangOffloadWrapper.rst b/clang/docs/ClangOffloadWrapper.rst new file mode 100644 index 0000000000000..be75894baf097 --- /dev/null +++ b/clang/docs/ClangOffloadWrapper.rst @@ -0,0 +1,271 @@ +===================== +Clang Offload Wrapper +===================== + +.. contents:: + :local: + +.. _clang-offload-wrapper: + +Introduction +============ + +This tool is used in OpenMP offloading toolchain to embed device code objects +(usually ELF) into a wrapper host llvm IR (bitcode) file. The wrapper host IR +is then assembled and linked with host code objects to generate the executable +binary. See :ref:`multi-image-binary-embedding-execution` for more details. + +Usage +===== + +This tool can be used as follows: + +.. code-block:: console + + $ clang-offload-wrapper -help + OVERVIEW: A tool to create a wrapper bitcode for offload target binaries. + Takes offload target binaries as input and produces bitcode file containing + target binaries packaged as data and initialization code which registers + target binaries in offload runtime. + + USAGE: clang-offload-wrapper [options] + + OPTIONS: + + Generic Options: + + --help - Display available options (--help-hidden for more) + --help-list - Display list of available options (--help-list-hidden for more) + --version - Display the version of this program + + clang-offload-wrapper options: + -o - Output filename + --target= - Target triple for the output module + +Example +======= + +.. code-block:: console + + clang-offload-wrapper -target host-triple -o host-wrapper.bc --offload-arch=gfx906 gfx906-binary.out --offload-arch=gfx90a gfx90a-binary.out + + +.. _openmp-device-binary_embedding: + +OpenMP Device Binary Embedding +============================== + +Various structures and functions used in the wrapper host IR form the interface +between the executable binary and the OpenMP runtime. + +Enum Types +---------- + +:ref:`table-offloading-declare-target-flags` lists different flag for +offloading entries. + + .. table:: Offloading Declare Target Flags Enum + :name: table-offloading-declare-target-flags + + +-------------------------+-------+------------------------------------------------------------------+ + | Name | Value | Description | + +=========================+=======+==================================================================+ + | OMP_DECLARE_TARGET_LINK | 0x01 | Mark the entry as having a 'link' attribute (w.r.t. link clause) | + +-------------------------+-------+------------------------------------------------------------------+ + | OMP_DECLARE_TARGET_CTOR | 0x02 | Mark the entry as being a global constructor | + +-------------------------+-------+------------------------------------------------------------------+ + | OMP_DECLARE_TARGET_DTOR | 0x04 | Mark the entry as being a global destructor | + +-------------------------+-------+------------------------------------------------------------------+ + + +Structure Types +--------------- + +:ref:`table-tgt_offload_entry`, :ref:`table-tgt_device_image`, +:ref:`table-tgt_bin_desc`, and :ref:`table-tgt_image_info` are the structures +used in the wrapper host IR. + + .. table:: __tgt_offload_entry structure + :name: table-tgt_offload_entry + + +---------+------------+------------------------------------------------------------------------------------+ + | Type | Identifier | Description | + +=========+============+====================================================================================+ + | void* | addr | Address of global symbol within device image (function or global) | + +---------+------------+------------------------------------------------------------------------------------+ + | char* | name | Name of the symbol | + +---------+------------+------------------------------------------------------------------------------------+ + | size_t | size | Size of the entry info (0 if it is a function) | + +---------+------------+------------------------------------------------------------------------------------+ + | int32_t | flags | Flags associated with the entry (see :ref:`table-offloading-declare-target-flags`) | + +---------+------------+------------------------------------------------------------------------------------+ + | int32_t | reserved | Reserved, to be used by the runtime library. | + +---------+------------+------------------------------------------------------------------------------------+ + + .. table:: __tgt_device_image structure + :name: table-tgt_device_image + + +----------------------+--------------+----------------------------------------+ + | Type | Identifier | Description | + +======================+==============+========================================+ + | void* | ImageStart | Pointer to the target code start | + +----------------------+--------------+----------------------------------------+ + | void* | ImageEnd | Pointer to the target code end | + +----------------------+--------------+----------------------------------------+ + | __tgt_offload_entry* | EntriesBegin | Begin of table with all target entries | + +----------------------+--------------+----------------------------------------+ + | __tgt_offload_entry* | EntriesEnd | End of table (non inclusive) | + +----------------------+--------------+----------------------------------------+ + + .. table:: __tgt_bin_desc structure + :name: table-tgt_bin_desc + + +----------------------+------------------+------------------------------------------+ + | Type | Identifier | Description | + +======================+==================+==========================================+ + | int32_t | NumDeviceImages | Number of device types supported | + +----------------------+------------------+------------------------------------------+ + | __tgt_device_image* | DeviceImages | Array of device images (1 per dev. type) | + +----------------------+------------------+------------------------------------------+ + | __tgt_offload_entry* | HostEntriesBegin | Begin of table with all host entries | + +----------------------+------------------+------------------------------------------+ + | __tgt_offload_entry* | HostEntriesEnd | End of table (non inclusive) | + +----------------------+------------------+------------------------------------------+ + + .. table:: __tgt_image_info structure + :name: table-tgt_image_info + + +---------+---------------+-----------------------------------------------+ + | Type | Identifier | Description | + +=========+===============+===============================================+ + | int32_t | version | The version of this struct | + +---------+---------------+-----------------------------------------------+ + | int32_t | image_number | Image number in image library starting from 0 | + +---------+---------------+-----------------------------------------------+ + | int32_t | number_images | Number of images, used for initial allocation | + +---------+---------------+-----------------------------------------------+ + | char* | offload_arch | Target ID for which this image was compiled | + +---------+---------------+-----------------------------------------------+ + | char* | compile_opts | reserved for future use | + +---------+---------------+-----------------------------------------------+ + +Global Variables +---------------- + +:ref:`table-global-variables` lists various global variables, along with their +type and their explicit ELF sections, which are used to store device images and +related symbols. + + .. table:: Global Variables + :name: table-global-variables + + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | Variable | Type | ELF Section | Description | + +================================+=====================+=========================+===================================================+ + | __start_omp_offloading_entries | __tgt_offload_entry | .omp_offloading_entries | Begin symbol for the offload entries table. | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | __stop_omp_offloading_entries | __tgt_offload_entry | .omp_offloading_entries | End symbol for the offload entries table. | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | __dummy.omp_offloading.entry | __tgt_offload_entry | .omp_offloading_entries | Dummy zero-sized object in the offload entries | + | | | | section to force linker to define begin/end | + | | | | symbols defined above. | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | .omp_offloading.device_image | __tgt_device_image | .omp_offloading_entries | ELF device code object of the first image. | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | .omp_offloading.device_image.N | __tgt_device_image | .omp_offloading_entries | ELF device code object of the (N+1)th image. | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | .omp_offloading.device_images | __tgt_device_image | .omp_offloading_entries | Array of images. | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | .omp_offloading.descriptor | __tgt_bin_desc | .omp_offloading_entries | Binary descriptor object (see details below). | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | __offload_arch | string | .offload_arch_list | Target ID string of the first image. | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | .offload_image_info | __tgt_image_info | .omp_offloading_entries | Object containing target ID of the first image. | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | __offload_arch.N | string | .offload_arch_list | Target ID string of the (N+1)th image. | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + | .offload_image_info.N | __tgt_image_info | .omp_offloading_entries | Object containing target ID of the (N+1)th image. | + +--------------------------------+---------------------+-------------------------+---------------------------------------------------+ + +Binary Descriptor for Device Images +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This object is passed to the offloading runtime at program startup and it +describes all device images available in the executable or shared library. It +is defined as follows: + +.. code-block:: console + + __attribute__((visibility("hidden"))) + extern __tgt_offload_entry *__start_omp_offloading_entries; + __attribute__((visibility("hidden"))) + extern __tgt_offload_entry *__stop_omp_offloading_entries; + + static const char Image0[] = { }; + ... + static const char ImageN[] = { }; + + static const __tgt_device_image Images[] = { + { + Image0, /*ImageStart*/ + Image0 + sizeof(Image0), /*ImageEnd*/ + __start_omp_offloading_entries, /*EntriesBegin*/ + __stop_omp_offloading_entries /*EntriesEnd*/ + }, + ... + { + ImageN, /*ImageStart*/ + ImageN + sizeof(ImageN), /*ImageEnd*/ + __start_omp_offloading_entries, /*EntriesBegin*/ + __stop_omp_offloading_entries /*EntriesEnd*/ + } + }; + + static const __tgt_bin_desc BinDesc = { + sizeof(Images) / sizeof(Images[0]), /*NumDeviceImages*/ + Images, /*DeviceImages*/ + __start_omp_offloading_entries, /*HostEntriesBegin*/ + __stop_omp_offloading_entries /*HostEntriesEnd*/ + }; + +Global Constructor and Destructor +--------------------------------- + +Global constructor (``.omp_offloading.descriptor_reg()``) registers the library +of images with the runtime by calling ``__tgt_register_lib()`` function. The +cunstructor is explicitly defined in ``.text.startup`` section. It calls +``__tgt_register_image_info()`` function for each ``.offload_image_info.N`` +before calling registration function. Similarly, global destructor +(``.omp_offloading.descriptor_unreg()``) calls ``__tgt_unregister_lib()`` for +the unregistration and is also defined in ``.text.startup`` section. + +.. _multi-image-binary-embedding-execution: + +Multi-image Binary Embedding and Execution for OpenMP +===================================================== +For each offloading target, device ELF code objects are generated by ``clang``, +``opt``, ``llc``, and ``lld`` pipeline. These code objects along with the +target id of the offloading target devices are passed to the +``clang-offload-wrapper``. + + * At compile time, the ``clang-offload-wrapper`` tool takes the following + actions: + + * It embeds the ELF code objects for the device into the host code (see + :ref:`openmp-device-binary_embedding`). + * It creates internal labels to these embedded device code objects + (``.offload_image_info.N``). + * It creates a global constructor to get the address of the embedded device + code through ``.offload_image_info.N`` structure and to register the + device code. + * It also creates a new ELF section ``.offload_arch_list`` with an array of + null-terminated strings where each string (``__offload_arch.N``) provides + the target ID of an image. + + * At execution time: + + * The global constructor gets run and it registers the device image. + * The runtime looks for an image that is compatible with the offload + environment. It uses the ``offload-arch`` library to obtain underlying + system's environment. It's the target ID for AMDGPU and the processor + name for other offloading targets. diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 495f2ab3926ce..cabc193de91f2 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -68,9 +68,6 @@ It can be used like this: ``__has_builtin`` should not be used to detect support for a builtin macro; use ``#ifdef`` instead. - When compiling with target offloading, ``__has_builtin`` only considers the - currently active target. - ``__has_constexpr_builtin`` --------------------------- @@ -5197,6 +5194,119 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __builtin_amdgcn_is_invocable +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +``__builtin_amdgcn_processor_is`` and ``__builtin_amdgcn_is_invocable`` provide +a functional mechanism for programatically querying: + +* the identity of the current target processor; +* the capability of the current target processor to invoke a particular builtin. + +**Syntax**: + +.. code-block:: c + + __amdgpu_feature_predicate_t __builtin_amdgcn_processor_is(const char*); + __amdgpu_feature_predicate_t __builtin_amdgcn_is_invocable(builtin_name); + +**Example of use**: + +.. code-block:: c++ + + if (__builtin_amdgcn_processor_is("gfx1201") || + __builtin_amdgcn_is_invocable(__builtin_amdgcn_s_sleep_var)) + __builtin_amdgcn_s_sleep_var(x); + + if (!__builtin_amdgcn_processor_is("gfx906")) + __builtin_amdgcn_s_wait_event_export_ready(); + else if (__builtin_amdgcn_processor_is("gfx1010") || + __builtin_amdgcn_processor_is("gfx1101")) + __builtin_amdgcn_s_ttracedata_imm(1); + + while (__builtin_amdgcn_processor_is("gfx1101")) *p += x; + + do { + break; + } while (__builtin_amdgcn_processor_is("gfx1010")); + + for (; __builtin_amdgcn_processor_is("gfx1201"); ++*p) break; + + if (__builtin_amdgcn_is_invocable(__builtin_amdgcn_s_wait_event_export_ready)) + __builtin_amdgcn_s_wait_event_export_ready(); + else if (__builtin_amdgcn_is_invocable(__builtin_amdgcn_s_ttracedata_imm)) + __builtin_amdgcn_s_ttracedata_imm(1); + + do { + break; + } while ( + __builtin_amdgcn_is_invocable(__builtin_amdgcn_global_load_tr_b64_i32)); + + for (; __builtin_amdgcn_is_invocable(__builtin_amdgcn_permlane64); ++*p) + break; + +**Description**: + +The builtins return a value of type ``__amdgpu_feature_predicate_t``, which is a +target specific type that behaves as if its C++ definition was the following: + +.. code-block:: c++ + + struct __amdgpu_feature_predicate_t { + __amdgpu_feature_predicate_t() = delete; + __amdgpu_feature_predicate_t(const __amdgpu_feature_predicate_t&) = delete; + __amdgpu_feature_predicate_t(__amdgpu_feature_predicate_t&&) = delete; + + explicit + operator bool() const noexcept; + }; + +The builtins can be used in C as well, wherein the +``__amdgpu_feature_predicate_t`` type behaves as an opaque, forward declared +type with conditional automated conversion to ``_Bool`` when used as the +predicate argument to a control structure: + +.. code-block:: c + + struct __amdgpu_feature_predicate_t ret(); // Error + void arg(struct __amdgpu_feature_predicate_t); // Error + void local() { + struct __amdgpu_feature_predicate_t x; // Error + struct __amdgpu_feature_predicate_t y = + __builtin_amdgcn_processor_is("gfx900"); // Error + } + void valid_use() { + _Bool x = (_Bool)__builtin_amdgcn_processor_is("gfx900"); // OK + if (__builtin_amdgcn_processor_is("gfx900")) // Implicit cast to _Bool + return; + for (; __builtin_amdgcn_processor_is("gfx900");) // Implicit cast to _Bool + break; + while (__builtin_amdgcn_processor_is("gfx900")) // Implicit cast to _Bool + break; + do { + break; + } while (__builtin_amdgcn_processor_is("gfx900")); // Implicit cast to _Bool + + __builtin_amdgcn_processor_is("gfx900") ? x : !x; + } + +The boolean interpretation of the predicate values returned by the builtins: + +* indicates whether the current target matches the argument; the argument MUST + be a string literal and a valid AMDGPU target +* indicates whether the builtin function passed as the argument can be invoked + by the current target; the argument MUST be either a generic or AMDGPU + specific builtin name + +When invoked while compiling for a concrete target, the builtins are evaluated +early by Clang, and never produce any CodeGen effects / have no observable ++side-effects in IR. Conversely, when compiling for AMDGCN flavoured SPIR-v, ++which is an abstract target, a series of predicate values are implicitly ++created. These predicates get resolved when finalizing the compilation process ++for a concrete target, and shall reflect the latter's identity and features. ++Thus, it is possible to author high-level code, in e.g. HIP, that is target ++adaptive in a dynamic fashion, contrary to macro based mechanisms. + __builtin_amdgcn_ballot_w{32,64} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -5215,6 +5325,53 @@ returns the bit at the position of the current lane. It is almost equivalent to ``(mask & (1 << lane_id)) != 0``, except that its behavior is only defined if the given mask has the same value for all active lanes of the current wave. + +__builtin_amdgcn_global_load_b128 and __builtin_amdgcn_global_store_b128 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Signature: + +.. code-block:: c + + typedef __attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int v4u; + typedef v4u __attribute__((address_space(1))) *global_ptr_to_v4u; + + v4u __builtin_amdgcn_global_load_b128( + v4u __attribute__((address_space(1))) *src, + const char *scope); + + void __builtin_amdgcn_global_store_b128( + v4u __attribute__((address_space(1))) *dst, + v4u data, + const char *scope); + +Load or store a vector of 4 unsigned integers from or to global memory with +cache behavior specified by `scope` which must be a string literal. + +Valid values for `scope` are: + +===================== ========================================================== +scope architecture name +===================== ========================================================== +``"wavefront"`` wave + +``"workgroup"`` group + +``"agent"`` device + +``""`` (empty string) system +===================== ========================================================== + +These builtins are only supported on gfx942 and gfx950 devices. + +For semantics on gfx942, see Tables 47 and 48 in section 9.1.10 "Memory Scope +and Temporal Controls" of the "AMD Instinct MI300" Instruction Set Architecture +Reference. + +For semantics on gfx950, see Tables 49 and 50 in section 9.1.10 "Memory Scope +and Temporal Controls" of the CDNA4 Instruction Set Architecture Reference. + + ARM/AArch64 Language Extensions ------------------------------- diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index e6e33e7a9a280..190da055c3afc 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -317,6 +317,254 @@ Attribute Changes in Clang Improvements to Clang's diagnostics ----------------------------------- + +- Improve the diagnostics for deleted default constructor errors for C++ class + initializer lists that don't explicitly list a class member and thus attempt + to implicitly default construct that member. +- The ``-Wunique-object-duplication`` warning has been added to warn about objects + which are supposed to only exist once per program, but may get duplicated when + built into a shared library. +- Fixed a bug where Clang's Analysis did not correctly model the destructor behavior of ``union`` members (#GH119415). +- A statement attribute applied to a ``case`` label no longer suppresses + 'bypassing variable initialization' diagnostics (#84072). +- The ``-Wunsafe-buffer-usage`` warning has been updated to warn + about unsafe libc function calls. Those new warnings are emitted + under the subgroup ``-Wunsafe-buffer-usage-in-libc-call``. +- Diagnostics on chained comparisons (``a < b < c``) are now an error by default. This can be disabled with + ``-Wno-error=parentheses``. +- Similarly, fold expressions over a comparison operator are now an error by default. +- Clang now better preserves the sugared types of pointers to member. +- Clang now better preserves the presence of the template keyword with dependent + prefixes. +- Clang now in more cases avoids printing 'type-parameter-X-X' instead of the name of + the template parameter. +- Clang now respects the current language mode when printing expressions in + diagnostics. This fixes a bunch of `bool` being printed as `_Bool`, and also + a bunch of HLSL types being printed as their C++ equivalents. +- Clang now consistently quotes expressions in diagnostics. +- When printing types for diagnostics, clang now doesn't suppress the scopes of + template arguments contained within nested names. +- The ``-Wshift-bool`` warning has been added to warn about shifting a boolean. (#GH28334) +- Fixed diagnostics adding a trailing ``::`` when printing some source code + constructs, like base classes. +- The :doc:`ThreadSafetyAnalysis` now supports ``-Wthread-safety-pointer``, + which enables warning on passing or returning pointers to guarded variables + as function arguments or return value respectively. Note that + :doc:`ThreadSafetyAnalysis` still does not perform alias analysis. The + feature will be default-enabled with ``-Wthread-safety`` in a future release. +- The :doc:`ThreadSafetyAnalysis` now supports reentrant capabilities. +- Clang will now do a better job producing common nested names, when producing + common types for ternary operator, template argument deduction and multiple return auto deduction. +- The ``-Wsign-compare`` warning now treats expressions with bitwise not(~) and minus(-) as signed integers + except for the case where the operand is an unsigned integer + and throws warning if they are compared with unsigned integers (##18878). +- The ``-Wunnecessary-virtual-specifier`` warning (included in ``-Wextra``) has + been added to warn about methods which are marked as virtual inside a + ``final`` class, and hence can never be overridden. + +- Improve the diagnostics for chained comparisons to report actual expressions and operators (#GH129069). + +- Improve the diagnostics for shadows template parameter to report correct location (#GH129060). + +- Improve the ``-Wundefined-func-template`` warning when a function template is not instantiated due to being unreachable in modules. + +- When diagnosing an unused return value of a type declared ``[[nodiscard]]``, the type + itself is now included in the diagnostic. + +- Clang will now prefer the ``[[nodiscard]]`` declaration on function declarations over ``[[nodiscard]]`` + declaration on the return type of a function. Previously, when both have a ``[[nodiscard]]`` declaration attached, + the one on the return type would be preferred. This may affect the generated warning message: + + .. code-block:: c++ + + struct [[nodiscard("Reason 1")]] S {}; + [[nodiscard("Reason 2")]] S getS(); + void use() + { + getS(); // Now diagnoses "Reason 2", previously diagnoses "Reason 1" + } + +- Fixed an assertion when referencing an out-of-bounds parameter via a function + attribute whose argument list refers to parameters by index and the function + is variadic. e.g., + + .. code-block:: c + + __attribute__ ((__format_arg__(2))) void test (int i, ...) { } + + Fixes #GH61635 + +- Split diagnosing base class qualifiers from the ``-Wignored-Qualifiers`` diagnostic group into a new ``-Wignored-base-class-qualifiers`` diagnostic group (which is grouped under ``-Wignored-qualifiers``). Fixes #GH131935. + +- ``-Wc++98-compat`` no longer diagnoses use of ``__auto_type`` or + ``decltype(auto)`` as though it was the extension for ``auto``. (#GH47900) +- Clang now issues a warning for missing return in ``main`` in C89 mode. (#GH21650) + +- Now correctly diagnose a tentative definition of an array with static + storage duration in pedantic mode in C. (#GH50661) +- No longer diagnosing idiomatic function pointer casts on Windows under + ``-Wcast-function-type-mismatch`` (which is enabled by ``-Wextra``). Clang + would previously warn on this construct, but will no longer do so on Windows: + + .. code-block:: c + + typedef void (WINAPI *PGNSI)(LPSYSTEM_INFO); + HMODULE Lib = LoadLibrary("kernel32"); + PGNSI FnPtr = (PGNSI)GetProcAddress(Lib, "GetNativeSystemInfo"); + + +- An error is now emitted when a ``musttail`` call is made to a function marked with the ``not_tail_called`` attribute. (#GH133509). + +- ``-Whigher-precision-for-complex-divison`` warns when: + + - The divisor is complex. + - When the complex division happens in a higher precision type due to arithmetic promotion. + - When using the divide and assign operator (``/=``). + + Fixes #GH131127 + +- ``-Wuninitialized`` now diagnoses when a class does not declare any + constructors to initialize their non-modifiable members. The diagnostic is + not new; being controlled via a warning group is what's new. Fixes #GH41104 + +- Analysis-based diagnostics (like ``-Wconsumed`` or ``-Wunreachable-code``) + can now be correctly controlled by ``#pragma clang diagnostic``. #GH42199 + +- Improved Clang's error recovery for invalid function calls. + +- Improved bit-field diagnostics to consider the type specified by the + ``preferred_type`` attribute. These diagnostics are controlled by the flags + ``-Wpreferred-type-bitfield-enum-conversion`` and + ``-Wpreferred-type-bitfield-width``. These warnings are on by default as they + they're only triggered if the authors are already making the choice to use + ``preferred_type`` attribute. + +- ``-Winitializer-overrides`` and ``-Wreorder-init-list`` are now grouped under + the ``-Wc99-designator`` diagnostic group, as they also are about the + behavior of the C99 feature as it was introduced into C++20. Fixes #GH47037 +- ``-Wreserved-identifier`` now fires on reserved parameter names in a function + declaration which is not a definition. +- Clang now prints the namespace for an attribute, if any, + when emitting an unknown attribute diagnostic. + +- ``-Wvolatile`` now warns about volatile-qualified class return types + as well as volatile-qualified scalar return types. Fixes #GH133380 + +- Several compatibility diagnostics that were incorrectly being grouped under + ``-Wpre-c++20-compat`` are now part of ``-Wc++20-compat``. (#GH138775) + +- Improved the ``-Wtautological-overlap-compare`` diagnostics to warn about overlapping and non-overlapping ranges involving character literals and floating-point literals. + The warning message for non-overlapping cases has also been improved (#GH13473). + +- Fixed a duplicate diagnostic when performing typo correction on function template + calls with explicit template arguments. (#GH139226) + +- Explanatory note is printed when ``assert`` fails during evaluation of a + constant expression. Prior to this, the error inaccurately implied that assert + could not be used at all in a constant expression (#GH130458) + +- A new off-by-default warning ``-Wms-bitfield-padding`` has been added to alert to cases where bit-field + packing may differ under the MS struct ABI (#GH117428). + +- ``-Watomic-access`` no longer fires on unreachable code. e.g., + + .. code-block:: c + + _Atomic struct S { int a; } s; + void func(void) { + if (0) + s.a = 12; // Previously diagnosed with -Watomic-access, now silenced + s.a = 12; // Still diagnosed with -Watomic-access + return; + s.a = 12; // Previously diagnosed, now silenced + } + + +- A new ``-Wcharacter-conversion`` warns where comparing or implicitly converting + between different Unicode character types (``char8_t``, ``char16_t``, ``char32_t``). + This warning only triggers in C++ as these types are aliases in C. (#GH138526) + +- Fixed a crash when checking a ``__thread``-specified variable declaration + with a dependent type in C++. (#GH140509) + +- Clang now suggests corrections for unknown attribute names. + +- ``-Wswitch`` will now diagnose unhandled enumerators in switches also when + the enumerator is deprecated. Warnings about using deprecated enumerators in + switch cases have moved behind a new ``-Wdeprecated-declarations-switch-case`` + flag. + + For example: + + .. code-block:: c + + enum E { + Red, + Green, + Blue [[deprecated]] + }; + void example(enum E e) { + switch (e) { + case Red: // stuff... + case Green: // stuff... + } + } + + will result in a warning about ``Blue`` not being handled in the switch. + + The warning can be fixed either by adding a ``default:``, or by adding + ``case Blue:``. Since the enumerator is deprecated, the latter approach will + trigger a ``'Blue' is deprecated`` warning, which can be turned off with + ``-Wno-deprecated-declarations-switch-case``. + +- Split diagnosis of implicit integer comparison on negation to a new + diagnostic group ``-Wimplicit-int-comparison-on-negation``, grouped under + ``-Wimplicit-int-conversion``, so user can turn it off independently. + +- Improved the FixIts for unused lambda captures. + +- Delayed typo correction was removed from the compiler; immediate typo + correction behavior remains the same. Delayed typo correction facilities were + fragile and unmaintained, and the removal closed the following issues: + #GH142457, #GH139913, #GH138850, #GH137867, #GH137860, #GH107840, #GH93308, + #GH69470, #GH59391, #GH58172, #GH46215, #GH45915, #GH45891, #GH44490, + #GH36703, #GH32903, #GH23312, #GH69874. + +- Clang no longer emits a spurious -Wdangling-gsl warning in C++23 when + iterating over an element of a temporary container in a range-based + for loop.(#GH109793, #GH145164) + +- Fixed false positives in ``-Wformat-truncation`` and ``-Wformat-overflow`` + diagnostics when floating-point numbers had both width field and plus or space + prefix specified. (#GH143951) + +- A warning is now emitted when ``main`` is attached to a named module, + which can be turned off with ``-Wno-main-attached-to-named-module``. (#GH146247) + +- Clang now avoids issuing `-Wreturn-type` warnings in some cases where + the final statement of a non-void function is a `throw` expression, or + a call to a function that is trivially known to always throw (i.e., its + body consists solely of a `throw` statement). This avoids certain + false positives in exception-heavy code, though only simple patterns + are currently recognized. + +- Clang now accepts ``@tparam`` comments on variable template partial + specializations. (#GH144775) + +- Fixed a bug that caused diagnostic line wrapping to not function correctly on + some systems. (#GH139499) + +- Clang now tries to avoid printing file paths that contain ``..``, instead preferring + the canonical file path if it ends up being shorter. + +- Improve the diagnostics for placement new expression when const-qualified + object was passed as the storage argument. (#GH143708) + +- Clang now does not issue a warning about returning from a function declared with + the ``[[noreturn]]`` attribute when the function body is ended with a call via + pointer, provided it can be proven that the pointer only points to + ``[[noreturn]]`` functions. + - Diagnostics messages now refer to ``structured binding`` instead of ``decomposition``, to align with `P0615R0 `_ changing the term. (#GH157880) - Added a separate diagnostic group ``-Wfunction-effect-redeclarations``, for the more pedantic @@ -518,6 +766,12 @@ Target Specific Changes AMDGPU Support ^^^^^^^^^^^^^^ +- Bump the default code object version to 6. ROCm 6.3 is required to run any program compiled with COV6. +- Introduced a new target specific builtin ``__builtin_amdgcn_processor_is``, + a late / deferred query for the current target processor +- Introduced a new target specific builtin ``__builtin_amdgcn_is_invocable``, + which enables fine-grained, per-builtin, feature availability + NVPTX Support ^^^^^^^^^^^^^^ diff --git a/clang/docs/conf.py b/clang/docs/conf.py index 4cee382a718fa..6918e6d804680 100644 --- a/clang/docs/conf.py +++ b/clang/docs/conf.py @@ -88,10 +88,19 @@ # The name of the Pygments (syntax highlighting) style to use. pygments_style = "friendly" -in_progress_title = "(In-Progress) " if tags.has("PreRelease") else "" +# A list of ignored prefixes for module index sorting. +#modindex_common_prefix = [] -rst_epilog = f""" -.. |ReleaseNotesTitle| replace:: {in_progress_title} Release Notes +# TODO: Temporary workaround for configuration error to get man pages built + +# in_progress_title = "(In-Progress) " if tags.has("PreRelease") else "" + +# rst_epilog = f""" +# .. |ReleaseNotesTitle| replace:: {in_progress_title} Release Notes +# """ + +rst_epilog = """ +.. |ReleaseNotesTitle| replace:: Release Notes """ # -- Options for HTML output --------------------------------------------------- diff --git a/clang/docs/index.rst b/clang/docs/index.rst index 272ae54bd9278..258316759fccf 100644 --- a/clang/docs/index.rst +++ b/clang/docs/index.rst @@ -100,8 +100,10 @@ Using Clang Tools ClangFormat ClangFormatStyleOptions ClangLinkerWrapper - ClangNVLinkWrapper + ClangNvlinkWrapper + ClangOffloadWrapper ClangOffloadBundler + ClangOffloadWrapper ClangRepl ClangSYCLLinker diff --git a/clang/include/clang/AST/MangleNumberingContext.h b/clang/include/clang/AST/MangleNumberingContext.h index 1313c94eb1224..0064ef4d4e408 100644 --- a/clang/include/clang/AST/MangleNumberingContext.h +++ b/clang/include/clang/AST/MangleNumberingContext.h @@ -16,6 +16,7 @@ #include "clang/Basic/LLVM.h" #include "llvm/ADT/IntrusiveRefCntPtr.h" +#include "llvm/Support/ErrorHandling.h" namespace clang { diff --git a/clang/include/clang/Analysis/Analyses/UninitializedValues.h b/clang/include/clang/Analysis/Analyses/UninitializedValues.h index a9b9caf38e518..b151bc3f58321 100644 --- a/clang/include/clang/Analysis/Analyses/UninitializedValues.h +++ b/clang/include/clang/Analysis/Analyses/UninitializedValues.h @@ -50,9 +50,6 @@ class UninitUse { /// Is this use a const reference to this variable? bool ConstRefUse = false; - /// Is this use a const pointer to this variable? - bool ConstPtrUse = false; - /// This use is always uninitialized if it occurs after any of these branches /// is taken. SmallVector UninitBranches; @@ -68,14 +65,11 @@ class UninitUse { void setUninitAfterCall() { UninitAfterCall = true; } void setUninitAfterDecl() { UninitAfterDecl = true; } void setConstRefUse() { ConstRefUse = true; } - void setConstPtrUse() { ConstPtrUse = true; } /// Get the expression containing the uninitialized use. const Expr *getUser() const { return User; } bool isConstRefUse() const { return ConstRefUse; } - bool isConstPtrUse() const { return ConstPtrUse; } - bool isConstRefOrPtrUse() const { return ConstRefUse || ConstPtrUse; } /// The kind of uninitialized use. enum Kind { diff --git a/clang/include/clang/Basic/AMDGPUTypes.def b/clang/include/clang/Basic/AMDGPUTypes.def index 089a72b5c102e..8065393413d5e 100644 --- a/clang/include/clang/Basic/AMDGPUTypes.def +++ b/clang/include/clang/Basic/AMDGPUTypes.def @@ -20,11 +20,19 @@ AMDGPU_TYPE(Name, Id, SingletonId, Width, Align) #endif +#ifndef AMDGPU_FEATURE_PREDICATE_TYPE +#define AMDGPU_FEATURE_PREDICATE_TYPE(Name, Id, SingletonId, Width, Align) \ + AMDGPU_TYPE(Name, Id, SingletonId, Width, Align) +#endif + AMDGPU_OPAQUE_PTR_TYPE("__amdgpu_buffer_rsrc_t", AMDGPUBufferRsrc, AMDGPUBufferRsrcTy, 128, 128, 8) AMDGPU_OPAQUE_PTR_TYPE("__amdgpu_texture_t", AMDGPUTexture, AMDGPUTextureTy, 256, 256, 0) AMDGPU_NAMED_BARRIER_TYPE("__amdgpu_named_workgroup_barrier_t", AMDGPUNamedWorkgroupBarrier, AMDGPUNamedWorkgroupBarrierTy, 128, 32, 0) +AMDGPU_FEATURE_PREDICATE_TYPE("__amdgpu_feature_predicate_t", AMDGPUFeaturePredicate, AMDGPUFeaturePredicateTy, 1, 1) + #undef AMDGPU_TYPE #undef AMDGPU_OPAQUE_PTR_TYPE #undef AMDGPU_NAMED_BARRIER_TYPE +#undef AMDGPU_FEATURE_PREDICATE_TYPE diff --git a/clang/include/clang/Basic/Builtins.def b/clang/include/clang/Basic/Builtins.def index b856ad145824d..0e94b0bba4e32 100644 --- a/clang/include/clang/Basic/Builtins.def +++ b/clang/include/clang/Basic/Builtins.def @@ -34,6 +34,7 @@ // Q -> target builtin type, followed by a character to distinguish the builtin type // Qa -> AArch64 svcount_t builtin type. // Qb -> AMDGPU __amdgpu_buffer_rsrc_t builtin type. +// Qc -> AMDGPU __amdgpu_feature_predicate_t builtin type. // Qt -> AMDGPU __amdgpu_texture_t builtin type. // E -> ext_vector, followed by the number of elements and the base type. // X -> _Complex, followed by the base type. diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def b/clang/include/clang/Basic/BuiltinsAMDGPU.def index f265d82efee75..8c71668415aad 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.def +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def @@ -190,6 +190,9 @@ TARGET_BUILTIN(__builtin_amdgcn_raw_ptr_buffer_atomic_fmax_f64, "ddQbiiIi", "", TARGET_BUILTIN(__builtin_amdgcn_raw_ptr_buffer_load_lds, "vQbv*3IUiiiIiIi", "t", "vmem-to-lds-load-insts") TARGET_BUILTIN(__builtin_amdgcn_struct_ptr_buffer_load_lds, "vQbv*3IUiiiiIiIi", "t", "vmem-to-lds-load-insts") +TARGET_BUILTIN(__builtin_amdgcn_global_load_b128, "V4UiV4Ui*1cC*", "n", "gfx940-insts") +TARGET_BUILTIN(__builtin_amdgcn_global_store_b128, "vV4Ui*1V4UicC*", "n", "gfx940-insts") + //===----------------------------------------------------------------------===// // Ballot builtins. //===----------------------------------------------------------------------===// @@ -378,6 +381,11 @@ BUILTIN(__builtin_amdgcn_endpgm, "v", "nr") BUILTIN(__builtin_amdgcn_get_fpenv, "WUi", "n") BUILTIN(__builtin_amdgcn_set_fpenv, "vWUi", "n") +// These are special FE only builtins intended for forwarding the requirements +// to the ME. +BUILTIN(__builtin_amdgcn_processor_is, "QccC*", "nctu") +BUILTIN(__builtin_amdgcn_is_invocable, "Qc", "nctu") + //===----------------------------------------------------------------------===// // Wave Reduction builtins. diff --git a/clang/include/clang/Basic/CodeGenOptions.h b/clang/include/clang/Basic/CodeGenOptions.h index 5d5cf250b56b9..65d47c5e8b31d 100644 --- a/clang/include/clang/Basic/CodeGenOptions.h +++ b/clang/include/clang/Basic/CodeGenOptions.h @@ -192,6 +192,14 @@ class CodeGenOptions : public CodeGenOptionsBase { Never, // No loop is assumed to be finite. }; + enum class HeterogeneousDwarfOpts { + Disabled, //< Do not emit any heterogeneous dwarf metadata. + DIExpression, //< Enable DIExpression-based metadata. + }; + bool isHeterogeneousDwarfEnabled() const { + return getHeterogeneousDwarfMode() != HeterogeneousDwarfOpts::Disabled; + } + enum AssignmentTrackingOpts { Disabled, Enabled, diff --git a/clang/include/clang/Basic/DebugOptions.def b/clang/include/clang/Basic/DebugOptions.def index a768b12fa4e0d..9f8b30d1e7ea4 100644 --- a/clang/include/clang/Basic/DebugOptions.def +++ b/clang/include/clang/Basic/DebugOptions.def @@ -53,6 +53,10 @@ DEBUGOPT(DebugStrictDwarf, 1, 1, Compatible) ///< Whether or not to use strict D DEBUGOPT(DebugOmitUnreferencedMethods, 1, 0, Compatible) ///< Omit unreferenced member ///< functions in type debug info. +/// Control DWARF extensions for heterogeneous debugging enablement and approach. +ENUM_DEBUGOPT(HeterogeneousDwarfMode, HeterogeneousDwarfOpts, 2, + HeterogeneousDwarfOpts::Disabled, Benign) + /// Control the Assignment Tracking debug info feature. ENUM_DEBUGOPT(AssignmentTrackingMode, AssignmentTrackingOpts, 2, AssignmentTrackingOpts::Disabled, Benign) diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index 83980e3ac35b7..4ced9204effdf 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -71,6 +71,9 @@ def err_drv_no_rocm_device_lib : Error< "%select{|, which requires ROCm %3 or higher}2}0; provide its path via " "'--rocm-path' or '--rocm-device-lib-path', or pass '-nogpulib' to build " "without ROCm device library">; +def err_drv_no_asan_rt_lib : Error< + "AMDGPU address sanitizer runtime library (asanrtl) not found. " + "Please install ROCm device library which supports address sanitizer">; def err_drv_no_hip_runtime : Error< "cannot find HIP runtime; provide its path via '--rocm-path', or pass " "'-nogpuinc' to build without HIP runtime">; @@ -148,9 +151,9 @@ def warn_drv_unsupported_option_for_processor : Warning< def warn_drv_unsupported_openmp_library : Warning< "the library '%0=%1' is not supported, OpenMP will not be enabled">, InGroup; -def warn_openmp_incomplete : Warning< - "OpenMP support for version %0 in flang is still incomplete">, - InGroup; + +def warn_openacc_experimental : Warning< +"OpenACC is NOT supported for AMDGPU">; def err_drv_invalid_thread_model_for_target : Error< "invalid thread model '%0' in '%1' for this target">; @@ -158,6 +161,10 @@ def err_drv_invalid_linker_name : Error< "invalid linker name in argument '%0'">; def err_drv_invalid_rtlib_name : Error< "invalid runtime library name in argument '%0'">; +def err_drv_invalid_allocatable_mode : Error< + "invalid semantic mode for assignments to allocatables in argument '%0'">; +def err_drv_unsupported_fixed_line_length : Error< + "unsupported fixed-format line length in argument '%0'">; def err_drv_unsupported_rtlib_for_platform : Error< "unsupported runtime library '%0' for platform '%1'">; def err_drv_invalid_unwindlib_name : Error< @@ -193,6 +200,12 @@ def err_drv_invalid_diagnotics_misexpect_tolerance : Error< "invalid argument in '%0', only integers are supported">; def err_drv_missing_argument : Error< "argument to '%0' is missing (expected %1 value%s1)">; +def err_drv_missing_Xopenmptarget_or_march: Error< + "option -fopenmp-targets= requires additional options -Xopenmp-target= and -march=">, + DefaultFatal; +def warn_drv_missing_flang_exec : Warning< + "%0 not found, 'openmp-extras' package from ROCm may be missing">, + InGroup; def err_drv_invalid_Xarch_argument_with_args : Error< "invalid Xarch argument: '%0', options requiring arguments are unsupported">; def err_drv_Xopenmp_target_missing_triple : Error< @@ -368,7 +381,7 @@ def err_drv_omp_host_target_not_supported : Error< "target '%0' is not a supported OpenMP host target">; def err_drv_expecting_fopenmp_with_fopenmp_targets : Error< "'-fopenmp-targets' must be used in conjunction with a '-fopenmp' option " - "compatible with offloading; e.g., '-fopenmp=libomp' or '-fopenmp=libiomp5'">; + "compatible with offloading; e.g., '-fopenmp=libomp' or '-fopenmp=libiomp5' or '-fopenmp=libbolt'">; def err_drv_failed_to_deduce_target_from_arch : Error< "failed to deduce triple for target architecture '%0'; specify the triple " "using '-fopenmp-targets' and '-Xopenmp-target' instead">; @@ -705,6 +718,14 @@ def warn_drv_global_isel_incomplete_opt : Warning< "-fglobal-isel support is incomplete for this architecture at the current optimization level">, InGroup; +def warn_drv_amd_opt_removed : Warning< + "[AMD] proprietary optimization compiler has been removed">, + InGroup; + +def warn_drv_amd_opt_not_found : Warning< + "[AMD] proprietary optimization compiler installation was not found">, + InGroup; + def warn_drv_moutline_unsupported_opt : Warning< "'%0' does not support '-moutline'; flag ignored">, InGroup; diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td index 8aa3489a2a62b..4ac82da179fd5 100644 --- a/clang/include/clang/Basic/DiagnosticGroups.td +++ b/clang/include/clang/Basic/DiagnosticGroups.td @@ -962,11 +962,9 @@ def UninitializedMaybe : DiagGroup<"conditional-uninitialized">; def UninitializedSometimes : DiagGroup<"sometimes-uninitialized">; def UninitializedStaticSelfInit : DiagGroup<"static-self-init">; def UninitializedConstReference : DiagGroup<"uninitialized-const-reference">; -def UninitializedConstPointer : DiagGroup<"uninitialized-const-pointer">; def Uninitialized : DiagGroup<"uninitialized", [UninitializedSometimes, UninitializedStaticSelfInit, - UninitializedConstReference, - UninitializedConstPointer]>; + UninitializedConstReference]>; def IgnoredPragmaIntrinsic : DiagGroup<"ignored-pragma-intrinsic">; // #pragma optimize is often used to avoid to work around MSVC codegen bugs or // to disable inlining. It's not completely clear what alternative to suggest @@ -1766,6 +1764,3 @@ def ExtractAPIMisuse : DiagGroup<"extractapi-misuse">; // Warnings about using the non-standard extension having an explicit specialization // with a storage class specifier. def ExplicitSpecializationStorageClass : DiagGroup<"explicit-specialization-storage-class">; - -// A warning for options that enable a feature that is not yet complete -def ExperimentalOption : DiagGroup<"experimental-option">; diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 4e369be0bbb92..dac93db247f12 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -2564,10 +2564,6 @@ def warn_uninit_const_reference : Warning< "variable %0 is uninitialized when passed as a const reference argument " "here">, InGroup, DefaultIgnore; -def warn_uninit_const_pointer : Warning< - "variable %0 is uninitialized when passed as a const pointer argument here">, - InGroup, DefaultIgnore; - def warn_unsequenced_mod_mod : Warning< "multiple unsequenced modifications to %0">, InGroup; def warn_unsequenced_mod_use : Warning< @@ -12205,6 +12201,10 @@ def err_omp_inscan_reduction_expected : Error< "expected 'reduction' clause with the 'inscan' modifier">; def note_omp_previous_inscan_reduction : Note< "'reduction' clause with 'inscan' modifier is used here">; +def err_omp_multivar_xteam_scan_unsupported : Error< + "multiple list items are not yet supported with the 'inclusive' or the 'exclusive' clauses that appear with the 'scan' directive">; +def err_omp_xteam_scan_prohibited : Error< + "'scan' directive is not supported inside target regions. Use flag '-fopenmp-target-xteam-scan' to enable it">; def err_omp_expected_predefined_allocator : Error< "expected one of the predefined allocators for the variables with the static " "storage: 'omp_default_mem_alloc', 'omp_large_cap_mem_alloc', " @@ -13688,6 +13688,27 @@ def note_acc_reduction_combiner_forming // AMDGCN builtins diagnostics def err_amdgcn_load_lds_size_invalid_value : Error<"invalid size value">; def note_amdgcn_load_lds_size_valid_value : Note<"size must be %select{1, 2, or 4|1, 2, 4, 12 or 16}0">; +def err_amdgcn_processor_is_arg_not_literal + : Error<"the argument to __builtin_amdgcn_processor_is must be a string " + "literal">; +def err_amdgcn_processor_is_arg_invalid_value + : Error<"the argument to __builtin_amdgcn_processor_is must be a valid " + "AMDGCN processor identifier; '%0' is not valid">; +def note_amdgcn_processor_is_valid_options + : Note<"valid AMDGCN processor identifiers are: %0">; +def err_amdgcn_is_invocable_arg_invalid_value + : Error<"the argument to __builtin_amdgcn_is_invocable must be either a " + "target agnostic builtin or an AMDGCN target specific builtin; `%0`" + " is not valid">; +def err_amdgcn_predicate_type_is_not_constructible + : Error<"%0 has type __amdgpu_feature_predicate_t, which is not" + " constructible">; +def err_amdgcn_predicate_type_needs_explicit_bool_cast + : Error<"%0 must be explicitly cast to %1; however, please note that this " + "is almost always an error and that it prevents the effective " + "guarding of target dependent code, and thus should be avoided">; +def note_amdgcn_protected_by_predicate : Note<"jump enters statement controlled" + " by AMDGPU feature predicate">; def err_amdgcn_coop_atomic_invalid_as : Error<"cooperative atomic requires a global or generic pointer">; } // end of sema component. diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index 8d6b8a14740ce..74eee0761bac4 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -216,6 +216,7 @@ LANGOPT(OpenCLGenericAddressSpace, 1, 0, NotCompatible, "OpenCL generic keyword" LANGOPT(OpenCLPipes , 1, 0, NotCompatible, "OpenCL pipes language constructs and built-ins") LANGOPT(NativeHalfType , 1, 0, NotCompatible, "Native half type support") LANGOPT(NativeHalfArgsAndReturns, 1, 0, NotCompatible, "Native half args and returns") +LANGOPT(HalfArgsAndReturns, 1, 0, NotCompatible, "half args and returns") LANGOPT(CUDA , 1, 0, NotCompatible, "CUDA") LANGOPT(HIP , 1, 0, NotCompatible, "HIP") LANGOPT(OpenMP , 32, 0, NotCompatible, "OpenMP support and version of OpenMP (31, 40 or 45)") @@ -228,7 +229,19 @@ LANGOPT(OpenMPIRBuilder , 1, 0, NotCompatible, "Use the experimental OpenMP-IR LANGOPT(OpenMPCUDANumSMs , 32, 0, NotCompatible, "Number of SMs for CUDA devices.") LANGOPT(OpenMPCUDABlocksPerSM , 32, 0, NotCompatible, "Number of blocks per SM for CUDA devices.") LANGOPT(OpenMPCUDAReductionBufNum , 32, 1024, NotCompatible, "Number of the reduction records in the intermediate reduction buffer used for the teams reductions.") +LANGOPT(OpenMPGPUThreadsPerTeam, 32, 256, NotCompatible, "Number of threads per team for GPUs.") +LANGOPT(OpenMPTargetXteamReductionBlockSize, 32, 512, NotCompatible, "Number of threads in a block used by cross-team reduction.") LANGOPT(OpenMPTargetDebug , 32, 0, NotCompatible, "Enable debugging in the OpenMP offloading device RTL") +LANGOPT(OpenMPTargetIgnoreEnvVars , 1, 0, NotCompatible, "Generate code assuming that device related environment variables can be ignored.") +LANGOPT(OpenMPTargetBigJumpLoop , 1, 1, NotCompatible, "Use big jump loop code generation technique.") +LANGOPT(OpenMPTargetNoLoop , 1, 1, NotCompatible, "Use no-loop code generation technique.") +LANGOPT(OpenMPTargetXteamReduction , 1, 1, NotCompatible, "Use cross-team code generation technique.") +LANGOPT(OpenMPTargetFastReduction , 1, 0, NotCompatible, "Use fast reduction code generation technique.") +LANGOPT(OpenMPTargetMultiDevice , 1, 0, NotCompatible, "Offload the iteration space of a single target region across multiple GPU devices.") + +// The flag '-fopenmp-target-xteam-scan' triggers the 'Segmented Cross Team Scan' variant by default. To use the no-loop variant, please use the flag '-fopenmp-target-no-loop-scan' instead. +LANGOPT(OpenMPTargetXteamScan , 1, 0, NotCompatible, "Use the cross-team specialized kernel code generation for 'scan' directive.") +LANGOPT(OpenMPTargetXteamNoLoopScan , 1, 0, NotCompatible, "Use the no-loop variant of the cross-team specialized kernel code generation for 'scan' directive.") LANGOPT(OpenMPOptimisticCollapse , 1, 0, NotCompatible, "Use at most 32 bits to represent the collapsed loop nest counter.") LANGOPT(OpenMPThreadSubscription , 1, 0, NotCompatible, "Assume work-shared loops do not have more iterations than participating threads.") LANGOPT(OpenMPTeamSubscription , 1, 0, NotCompatible, "Assume distributed loops do not have more iterations than participating teams.") @@ -236,6 +249,8 @@ LANGOPT(OpenMPNoThreadState , 1, 0, NotCompatible, "Assume that no thread in a LANGOPT(OpenMPNoNestedParallelism , 1, 0, NotCompatible, "Assume that no thread in a parallel region will encounter a parallel region") LANGOPT(OpenMPOffloadMandatory , 1, 0, NotCompatible, "Assert that offloading is mandatory and do not create a host fallback.") LANGOPT(OpenMPForceUSM , 1, 0, NotCompatible, "Enable OpenMP unified shared memory mode via compiler.") +LANGOPT(OpenMPKernelIO , 1, 1, NotCompatible, "Enable OpenMP host-exec Device IO.") + LANGOPT(NoGPULib , 1, 0, NotCompatible, "Indicate a build without the standard GPU libraries.") LANGOPT(HLSL, 1, 0, NotCompatible, "HLSL") diff --git a/clang/include/clang/Basic/SyncScope.h b/clang/include/clang/Basic/SyncScope.h index 7776c3d83a77d..27a31b491a508 100644 --- a/clang/include/clang/Basic/SyncScope.h +++ b/clang/include/clang/Basic/SyncScope.h @@ -131,7 +131,7 @@ class AtomicScopeOpenCLModel : public AtomicScopeModel { public: /// The enum values match the pre-defined macros /// __OPENCL_MEMORY_SCOPE_*, which are used to define memory_scope_* - /// enums in opencl-c-base.h. + /// enums in opencl-c.h. enum ID { WorkGroup = 1, Device = 2, diff --git a/clang/include/clang/Config/config.h.cmake b/clang/include/clang/Config/config.h.cmake index 00c352b458c34..eee93bdc83bb8 100644 --- a/clang/include/clang/Config/config.h.cmake +++ b/clang/include/clang/Config/config.h.cmake @@ -29,6 +29,9 @@ /* Default OpenMP runtime used by -fopenmp. */ #define CLANG_DEFAULT_OPENMP_RUNTIME "${CLANG_DEFAULT_OPENMP_RUNTIME}" +/* Default architecture for OpenMP offloading to Nvidia GPUs. */ +#define CLANG_OPENMP_NVPTX_DEFAULT_ARCH "${CLANG_OPENMP_NVPTX_DEFAULT_ARCH}" + /* Default architecture for SystemZ. */ #define CLANG_SYSTEMZ_DEFAULT_ARCH "${CLANG_SYSTEMZ_DEFAULT_ARCH}" diff --git a/clang/include/clang/Driver/Action.h b/clang/include/clang/Driver/Action.h index dbf1187da4db9..354e0a6b5bf20 100644 --- a/clang/include/clang/Driver/Action.h +++ b/clang/include/clang/Driver/Action.h @@ -61,6 +61,7 @@ class Action { ExtractAPIJobClass, AnalyzeJobClass, CompileJobClass, + FortranFrontendJobClass, BackendJobClass, AssembleJobClass, LinkJobClass, @@ -472,6 +473,17 @@ class CompileJobAction : public JobAction { } }; +class FortranFrontendJobAction : public JobAction { + void anchor() override; + +public: + FortranFrontendJobAction(Action *Input, types::ID OutputType); + + static bool classof(const Action *A) { + return A->getKind() == FortranFrontendJobClass; + } +}; + class BackendJobAction : public JobAction { void anchor() override; diff --git a/clang/include/clang/Driver/CommonArgs.h b/clang/include/clang/Driver/CommonArgs.h index ac17d6211d882..56c2a65ce8c7b 100644 --- a/clang/include/clang/Driver/CommonArgs.h +++ b/clang/include/clang/Driver/CommonArgs.h @@ -24,6 +24,8 @@ namespace clang { namespace driver { namespace tools { +bool needFortranLibs(const Driver &D, const llvm::opt::ArgList &Args); + void addPathIfExists(const Driver &D, const Twine &Path, ToolChain::path_list &Paths); @@ -56,18 +58,29 @@ void AddRunTimeLibs(const ToolChain &TC, const Driver &D, llvm::opt::ArgStringList &CmdArgs, const llvm::opt::ArgList &Args); +void AddStaticDeviceLibsLinking( + Compilation &C, const Tool &T, const JobAction &JA, + const InputInfoList &Inputs, const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CmdArgs, StringRef Arch, StringRef TargetID, + bool isBitCodeSDL, bool postClangLink, bool unpackage); void AddStaticDeviceLibsLinking(Compilation &C, const Tool &T, const JobAction &JA, const InputInfoList &Inputs, const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CmdArgs, - StringRef Arch, StringRef Target, - bool isBitCodeSDL); + StringRef Arch, StringRef TargetID, + bool isBitCodeSDL, bool postClangLink); +void AddStaticDeviceLibsPostLinking(const Driver &D, + const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CmdArgs, + StringRef Arch, StringRef TargetID, + bool isBitCodeSDL, bool postClangLink); void AddStaticDeviceLibs(Compilation *C, const Tool *T, const JobAction *JA, const InputInfoList *Inputs, const Driver &D, const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CmdArgs, StringRef Arch, - StringRef Target, bool isBitCodeSDL); + StringRef TargetID, bool isBitCodeSDL, + bool postClangLink, bool unpackage = false); const char *SplitDebugName(const JobAction &JA, const llvm::opt::ArgList &Args, const InputInfo &Input, const InputInfo &Output); @@ -122,6 +135,9 @@ void AddAssemblerKPIC(const ToolChain &ToolChain, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs); +void addOpenMPRuntimeSpecificRPath(const ToolChain &TC, + const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs); void addArchSpecificRPath(const ToolChain &TC, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs); void addOpenMPRuntimeLibraryPath(const ToolChain &TC, @@ -181,7 +197,8 @@ std::string getCPUName(const Driver &D, const llvm::opt::ArgList &Args, void getTargetFeatures(const Driver &D, const llvm::Triple &Triple, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs, bool ForAS, - bool IsAux = false); + bool IsAux = false, + const StringRef TcTargetID = StringRef()); /// Iterate \p Args and convert -mxxx to +xxx and -mno-xxx to -xxx and /// append it to \p Features. @@ -211,6 +228,10 @@ void addX86AlignBranchArgs(const Driver &D, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs, bool IsLTO, const StringRef PluginOptPrefix = ""); +unsigned getOrCheckAMDGPUCodeObjectVersion(const Driver &D, + const llvm::opt::ArgList &Args, + bool Diagnose = false); + void checkAMDGPUCodeObjectVersion(const Driver &D, const llvm::opt::ArgList &Args); diff --git a/clang/include/clang/Driver/Driver.h b/clang/include/clang/Driver/Driver.h index b9b187ada8add..419089731569b 100644 --- a/clang/include/clang/Driver/Driver.h +++ b/clang/include/clang/Driver/Driver.h @@ -162,7 +162,10 @@ class Driver { /// The legacy name for the LLVM OpenMP runtime from when it was the Intel /// OpenMP runtime. We support this mode for users with existing /// dependencies on this runtime library name. - OMPRT_IOMP5 + OMPRT_IOMP5, + + /// The LLVM BOLT OpenMP runtime. See https://github.com/pmodels/bolt + OMPRT_BOLT }; // Diag - Forwarding function for diagnostics. @@ -374,6 +377,9 @@ class Driver { /// stored in it, and will clean them up when torn down. mutable llvm::StringMap> ToolChains; + /// Number of parallel jobs. + unsigned NumParallelJobs; + private: /// TranslateInputArgs - Create a new derived argument list from the input /// arguments, after applying the standard argument translations. @@ -453,6 +459,11 @@ class Driver { return ClangExecutable.c_str(); } + /// Get the path to where the clang executable was installed. + const char *getInstalledDir() const { + return Dir.c_str(); + } + StringRef getPreferredLinker() const { return PreferredLinker; } void setPreferredLinker(std::string Value) { PreferredLinker = std::move(Value); @@ -763,6 +774,12 @@ class Driver { /// Get the specific kind of offload LTO being performed. LTOKind getOffloadLTOMode() const { return OffloadLTOMode; } + /// Get the number of parallel jobs. + unsigned getNumberOfParallelJobs() const { return NumParallelJobs; } + + /// Set the number of parallel jobs. + void setNumberOfParallelJobs(unsigned N) { NumParallelJobs = N; } + /// Get the CUID option. const CUIDOptions &getCUIDOpts() const { return CUIDOpts; } diff --git a/clang/include/clang/Driver/Job.h b/clang/include/clang/Driver/Job.h index 561866197b780..5ce5e4ef73607 100644 --- a/clang/include/clang/Driver/Job.h +++ b/clang/include/clang/Driver/Job.h @@ -144,6 +144,9 @@ class Command { /// See Command::setEnvironment std::vector Environment; + /// Dependent actions + llvm::SmallVector DependentActions; + /// Optional redirection for stdin, stdout, stderr. std::vector> RedirectFiles; @@ -223,6 +226,9 @@ class Command { const llvm::opt::ArgStringList &getArguments() const { return Arguments; } + const llvm::SmallVector &getDependentActions() const { + return DependentActions; + } const std::vector &getInputInfos() const { return InputInfoList; } const std::vector &getOutputFilenames() const { diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 8784c9d7d206d..7bdd21c82982d 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -852,6 +852,8 @@ def P : Flag<["-"], "P">, Group, HelpText<"Disable linemarker output in -E mode">, MarshallingInfoNegativeFlag>; +def parallel_jobs_EQ : Joined<["-"], "parallel-jobs=">, Flags<[NoXarchOption]>, + HelpText<"Number of parallel jobs">; def Qy : Flag<["-"], "Qy">, Visibility<[ClangOption, CC1Option]>, HelpText<"Emit metadata containing compiler name and version">; def Qn : Flag<["-"], "Qn">, Visibility<[ClangOption, CC1Option]>, @@ -1002,6 +1004,9 @@ def Xoffload_linker : JoinedAndSeparate<["-"], "Xoffload-linker">, Visibility<[ClangOption, FlangOption]>, HelpText<"Pass to the offload linkers or the ones identified by -">, MetaVarName<" ">, Group; +def Xopaque_offload_opt : Separate<["-"], "Xopaque-offload-opt">, + HelpText<"Pass to the opaque offload optimizer">, + MetaVarName<"">, Visibility<[ClangOption, FlangOption]>; def Xpreprocessor : Separate<["-"], "Xpreprocessor">, Group, HelpText<"Pass to the preprocessor">, MetaVarName<"">; def X_Flag : Flag<["-"], "X">, Group; @@ -1590,11 +1595,15 @@ defm xl_pragma_pack : BoolFOption<"xl-pragma-pack", "Enable IBM XL #pragma pack handling">, NegFlag>; def shared_libsan : Flag<["-"], "shared-libsan">, + Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Dynamically link the sanitizer runtime">; def static_libsan : Flag<["-"], "static-libsan">, + Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Statically link the sanitizer runtime (Not supported for ASan, TSan or UBSan on darwin)">; -def : Flag<["-"], "shared-libasan">, Alias; -def : Flag<["-"], "static-libasan">, Alias; +def : Flag<["-"], "shared-libasan">, Alias, + Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>; +def : Flag<["-"], "static-libasan">, Alias, + Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>; def fasm : Flag<["-"], "fasm">, Group; defm assume_unique_vtables : BoolFOption<"assume-unique-vtables", @@ -2377,7 +2386,7 @@ def fmemory_profile_use_EQ : Joined<["-"], "fmemory-profile-use=">, // Begin sanitizer flags. These should all be core options exposed in all driver // modes. -let Visibility = [ClangOption, CC1Option, CLOption] in { +let Visibility = [ClangOption, CC1Option, CLOption, FlangOption, FC1Option] in { def fsanitize_EQ : CommaJoined<["-"], "fsanitize=">, Group, MetaVarName<"">, @@ -3744,6 +3753,9 @@ defm disable_block_signature_string : BoolFOption<"disable-block-signature-strin NegFlag, BothFlags<[], [CC1Option], " block signature string)">>; +def ffast_amd_memory_allocator : Flag<["-"], "ffast-amd-memory-allocator">, Group, + Flags<[HelpHidden]>, Visibility<[FlangOption,FC1Option]>, + HelpText<"Enable optimized memory allocator for AMD Instinct(tm) APUs (experimental)">; def fomit_frame_pointer : Flag<["-"], "fomit-frame-pointer">, Group, Visibility<[ClangOption, FlangOption]>, HelpText<"Omit the frame pointer from functions that don't need it. " @@ -3813,6 +3825,93 @@ def fopenmp_cuda_blocks_per_sm_EQ : Joined<["-"], "fopenmp-cuda-blocks-per-sm="> def fopenmp_cuda_teams_reduction_recs_num_EQ : Joined<["-"], "fopenmp-cuda-teams-reduction-recs-num=">, Group, Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option]>; +// AMD OpenMP +def fno_openmp_allow_kernel_io : Flag<["-"], "fno-openmp-allow-kernel-io">, Group, + Flags<[NoArgumentUnused]>, Visibility<[ClangOption, CC1Option]>, + HelpText<"Disable OpenMP host-exec device I/O">, + MarshallingInfoFlag>; +def fopenmp_allow_kernel_io : Flag<["-"], "fopenmp-allow-kernel-io">, Group, + Flags<[NoArgumentUnused]>, Visibility<[ClangOption, CC1Option]>, + HelpText<"Enable OpenMP host-exec device I/O">, + MarshallingInfoFlag>; +def fenable_host_devmem : Flag<["-"], "fenable-host-devmem">, Group, + HelpText<"Enable host-assisted dynamic device memory management (Default)">; +def fdisable_host_devmem : Flag<["-"], "fdisable-host-devmem">, Group, + HelpText<"Disable host-assisted dynamic device memory management">; +def fopenmp_runtimelib_EQ : Joined<["-"], "fopenmp-runtimelib=">, Group, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, Flags<[NoArgumentUnused]>, + HelpText<"Select lib, lib-perf, or lib-debug openmp runtime" + " must be: lib, lib-perf or lib-debug.">; +def fopenmp_gpu_threads_per_team_EQ : Joined<["-"], "fopenmp-gpu-threads-per-team=">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option]>; +def fopenmp_target_xteam_reduction_blocksize_EQ : Joined<["-"], "fopenmp-target-xteam-reduction-blocksize=">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>; +def fopenmp_target_fast : Flag<["-"], "fopenmp-target-fast">, Group, Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>; +def fno_openmp_target_fast : Flag<["-"], "fno-openmp-target-fast">, Group, Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>; +def fopenmp_target_ignore_env_vars : Flag<["-"], "fopenmp-target-ignore-env-vars">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Assert that device related environment variables can be ignored while generating code">, + MarshallingInfoFlag>; +def fno_openmp_target_ignore_env_vars : Flag<["-"], "fno-openmp-target-ignore-env-vars">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Assert that device related environment variables cannot be ignored while generating code">, + MarshallingInfoFlag>; +def fopenmp_target_big_jump_loop : Flag<["-"], "fopenmp-target-big-jump-loop">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Use the big-jump-loop code generation technique if possible">, + MarshallingInfoFlag>; +def fno_openmp_target_big_jump_loop : Flag<["-"], "fno-openmp-target-big-jump-loop">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Do not use the big-jump-loop code generation technique">, + MarshallingInfoFlag>; +def fopenmp_target_no_loop : Flag<["-"], "fopenmp-target-no-loop">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Use the no-loop code generation technique if possible">, + MarshallingInfoFlag>; +def fno_openmp_target_no_loop : Flag<["-"], "fno-openmp-target-no-loop">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Do not use the no-loop code generation technique">, + MarshallingInfoFlag>; +def fopenmp_target_xteam_reduction : Flag<["-"], "fopenmp-target-xteam-reduction">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Use the cross-team code generation technique if possible">, + MarshallingInfoFlag>; +def fno_openmp_target_xteam_reduction : Flag<["-"], "fno-openmp-target-xteam-reduction">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Do not use the cross-team reduction code generation technique">, + MarshallingInfoFlag>; +def fopenmp_target_fast_reduction : Flag<["-"], "fopenmp-target-fast-reduction">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Use the fast reduction code generation technique if possible">, + MarshallingInfoFlag>; +def fno_openmp_target_fast_reduction : Flag<["-"], "fno-openmp-target-fast-reduction">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Do not use the fast reduction code generation technique">, + MarshallingInfoFlag>; +def fopenmp_target_xteam_scan : Flag<["-"], "fopenmp-target-xteam-scan">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option]>, + HelpText<"Use the cross-team specialized kernel code generation for 'scan' directive.">, + MarshallingInfoFlag>; +def fno_openmp_target_xteam_scan : Flag<["-"], "fno-openmp-target-xteam-scan">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option]>, + HelpText<"Do not use the cross-team specialized kernel code generation for 'scan' directive.">, + MarshallingInfoFlag>; +def fopenmp_target_xteam_no_loop_scan : Flag<["-"], "fopenmp-target-xteam-no-loop-scan">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option]>, + HelpText<"Use the no-loop variant of the cross-team specialized kernel code generation for 'scan' directive.">, + MarshallingInfoFlag>; +def fno_openmp_target_xteam_no_loop_scan : Flag<["-"], "fno-openmp-target-xteam-no-loop-scan">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option]>, + HelpText<"Do not use the no-loop variant of the cross-team specialized kernel code generation for 'scan' directive.">, + MarshallingInfoFlag>; +def fopenmp_target_multi_device : Flag<["-"], "fopenmp-target-multi-device">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option, FlangOption]>, + HelpText<"Enable code generation to emit support for multi device target region execution">, + MarshallingInfoFlag>; +def fno_openmp_target_multi_device : Flag<["-"], "fno-openmp-target-multi-device">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option,FlangOption]>, + HelpText<"Do not use code generation to emit support for multi target offloading">, + MarshallingInfoFlag>; + //===----------------------------------------------------------------------===// // Shared cc1 + fc1 OpenMP Target Options //===----------------------------------------------------------------------===// @@ -3832,10 +3931,11 @@ def fno_openmp_target_debug : Flag<["-"], "fno-openmp-target-debug">; //===----------------------------------------------------------------------===// // FlangOption + FC1 + ClangOption + CC1Option //===----------------------------------------------------------------------===// +// Unsupported on AMD downstream let Visibility = [FC1Option, FlangOption, CC1Option, ClangOption] in { -def fopenacc : Flag<["-"], "fopenacc">, Group, +def fopenacc : Flag<["-"], "fopenacc">, Group, Visibility<[]>, HelpText<"Enable OpenACC">; -} // let Visibility = [FC1Option, FlangOption, CC1Option, ClangOption] +} //===----------------------------------------------------------------------===// // Optimisation remark options @@ -3883,19 +3983,27 @@ def fno_openmp_assume_teams_oversubscription : Flag<["-"], "fno-openmp-assume-te HelpText<"Do not assume teams oversubscription.">; def fno_openmp_assume_threads_oversubscription : Flag<["-"], "fno-openmp-assume-threads-oversubscription">, HelpText<"Do not assume threads oversubscription.">; +def fno_openmp_assume_no_thread_state : Flag<["-"], "fno-openmp-assume-no-thread-state">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option]>, + HelpText<"Assert that a thread in a parallel region may modify an ICV">, + MarshallingInfoFlag>; def fopenmp_assume_no_thread_state : Flag<["-"], "fopenmp-assume-no-thread-state">, HelpText<"Assert no thread in a parallel region modifies an ICV">, MarshallingInfoFlag>; def fopenmp_assume_no_nested_parallelism : Flag<["-"], "fopenmp-assume-no-nested-parallelism">, HelpText<"Assert no nested parallel regions in the GPU">, MarshallingInfoFlag>; +def fno_openmp_assume_no_nested_parallelism : Flag<["-"], "fno-openmp-assume-no-nested-parallelism">, Group, + Flags<[NoArgumentUnused, HelpHidden]>, Visibility<[ClangOption, CC1Option]>, + HelpText<"Assert that a nested parallel region may be used in the GPU">, + MarshallingInfoFlag>; } // let Group = f_Group } // let Visibility = [ClangOption, CC1Option, FC1Option] } // let Flags = [NoArgumentUnused, HelpHidden] def fopenmp_offload_mandatory : Flag<["-"], "fopenmp-offload-mandatory">, Group, - Flags<[NoArgumentUnused]>, Visibility<[ClangOption, CC1Option]>, + Flags<[NoArgumentUnused]>, Visibility<[ClangOption, CC1Option, FlangOption]>, HelpText<"Do not create a host fallback if offloading to the device fails.">, MarshallingInfoFlag>; def fopenmp_force_usm : Flag<["-"], "fopenmp-force-usm">, Group, @@ -3918,6 +4026,17 @@ defm openmp_optimistic_collapse : BoolFOption<"openmp-optimistic-collapse", NegFlag, BothFlags<[NoArgumentUnused, HelpHidden], []>>; def static_openmp: Flag<["-"], "static-openmp">, HelpText<"Use the static host OpenMP runtime while linking.">; +def opaque_offload_linker + : Flag<["--"], "opaque-offload-linker">, + Visibility<[ClangOption, FlangOption]>, + Group, + HelpText<"Build/link omp offload binary, construct opaque cmd list " + "instead of single clang-linker-wrapper cmd.">; +def no_opaque_offload_linker : Flag<["--"], "no-opaque-offload-linker">, + Visibility<[ClangOption, FlangOption]>, + Group, + HelpText<"Build/link omp offload binary, using " + "single clang-linker-wrapper cmd.">; def fopenmp_new_driver : Flag<["-"], "fopenmp-new-driver">, Flags<[HelpHidden]>, HelpText<"Use the new driver for OpenMP offloading.">; def fno_openmp_new_driver : Flag<["-"], "fno-openmp-new-driver">, @@ -4756,6 +4875,23 @@ def gdwarf32 : Flag<["-"], "gdwarf32">, Group, Visibility<[ClangOption, CC1Option, CC1AsOption]>, HelpText<"Enables DWARF32 format for ELF binaries, if debug information emission is enabled.">; +def gheterogeneous_dwarf_EQ : Joined<["-"], "gheterogeneous-dwarf=">, + Group, Visibility<[ClangOption, CC1Option]>, + HelpText<"Control DWARF extensions for heterogeneous debugging">, + Values<"disabled,diexpression">, + NormalizedValuesScope<"CodeGenOptions::HeterogeneousDwarfOpts">, + NormalizedValues<["Disabled","DIExpression"]>, + MarshallingInfoEnum, "Disabled">; +def gheterogeneous_dwarf : Flag<["-"], "gheterogeneous-dwarf">, Group, + Visibility<[ClangOption, CC1Option]>, + HelpText<"Enable DIExpression-based DWARF extensions for heterogeneous debugging">, + Alias, AliasArgs<["diexpression"]>; +def gno_heterogeneous_dwarf : Flag<["-"], "gno-heterogeneous-dwarf">, + Visibility<[ClangOption, CC1Option]>, + Group, + HelpText<"Disable DWARF extensions for heterogeneous debugging">, + Alias, AliasArgs<["disabled"]>; + def gcodeview : Flag<["-"], "gcodeview">, HelpText<"Generate CodeView debug information">, Visibility<[ClangOption, CC1Option, CC1AsOption, CLOption, DXCOption]>, @@ -4841,8 +4977,10 @@ def gmodules : Flag <["-"], "gmodules">, Group, " or precompiled headers">; def gno_modules : Flag <["-"], "gno-modules">, Group; def gz_EQ : Joined<["-"], "gz=">, Group, + Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"DWARF debug sections compression type">; -def gz : Flag<["-"], "gz">, Alias, AliasArgs<["zlib"]>, Group; +def gz : Flag<["-"], "gz">, Alias, AliasArgs<["zlib"]>, Group, + Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>; def gembed_source : Flag<["-"], "gembed-source">, Group, Visibility<[ClangOption, CC1Option]>, HelpText<"Embed source text in DWARF debug sections">, @@ -5485,6 +5623,8 @@ def mcode_object_version_EQ : Joined<["-"], "mcode-object-version=">, Group; +defm sram_ecc_legacy : SimpleMFlag<"sram-ecc", "", "", + "Legacy option to specify SRAM ECC mode (AMDGPU only)">; defm tgsplit : SimpleMFlag<"tgsplit", "Enable", "Disable", " threadgroup split execution mode (AMDGPU only)", m_amdgpu_Features_Group>; defm wavefrontsize64 : SimpleMFlag<"wavefrontsize64", @@ -5499,6 +5639,11 @@ def munsafe_fp_atomics : Flag<["-"], "munsafe-fp-atomics">, def mno_unsafe_fp_atomics : Flag<["-"], "mno-unsafe-fp-atomics">, Visibility<[ClangOption, FlangOption]>, Alias; +// TODO: Remove during upstreaming target id. +def mxnack : Flag<["-"], "mxnack">, Group, + HelpText<"Legacy option to specify XNACK mode (AMDGPU only)">; +def mno_xnack : Flag<["-"], "mno-xnack">, Group; + def faltivec : Flag<["-"], "faltivec">, Group; def fno_altivec : Flag<["-"], "fno-altivec">, Group; let Flags = [TargetSpecific] in { @@ -6162,6 +6307,13 @@ def no_offload_add_rpath: Flag<["--"], "no-offload-add-rpath">, Alias; def r : Flag<["-"], "r">, Flags<[LinkerInput, NoArgumentUnused]>, Group; +defm openmp_implicit_rpath: BoolFOption<"openmp-implicit-rpath", + LangOpts<"OpenMP">, + DefaultTrue, + PosFlag, + NegFlag, + BothFlags<[NoArgumentUnused]>>; def regcall4 : Flag<["-"], "regcall4">, Group, Visibility<[ClangOption, CC1Option]>, HelpText<"Set __regcall4 as a default calling convention to respect __regcall ABI v.4">, @@ -7137,6 +7289,22 @@ defm second_underscore : BooleanFFlag<"second-underscore">, Group, Group; defm whole_file : BooleanFFlag<"whole-file">, Group; +//Suspicious fortran entries +def flang_rt_Group : OptionGroup<"Flang runtime library Group">; +def pgi_fortran_Group : OptionGroup<"PGI Fortran compatibility Group">, + Visibility<[FlangOption]>; +def mp: Flag<["-"], "mp">, Group, + HelpText<"Enable OpenMP">; +def nomp: Flag<["-"], "nomp">, Group, + HelpText<"Do not link with OpenMP library libomp">; +def staticFlangLibs: Flag<["-"], "static-flang-libs">, Group, + HelpText<"Link using static Flang libraries">; +def noFlangLibs: Flag<["-"], "no-flang-libs">, Group, + HelpText<"Do not link against Flang libraries">; +def Mnomain: Flag<["-"], "Mnomain">, Group, + HelpText<"Don't link in Fortran main">; +// end suspicious + // -W options unsupported by the flang compiler // If any of these options are passed into flang's compiler driver, // a warning will be raised and the argument will be claimed @@ -7275,6 +7443,7 @@ defm logical_abbreviations : OptInFC1FFlag<"logical-abbreviations", "Enable logi defm implicit_none : OptInFC1FFlag<"implicit-none", "No implicit typing allowed unless overridden by IMPLICIT statements">; defm implicit_none_ext : OptInFC1FFlag<"implicit-none-ext", "No implicit externals allowed">; defm underscoring : OptInFC1FFlag<"underscoring", "Appends one trailing underscore to external names">; +defm offload_global_filtering : OptInFC1FFlag<"offload-global-filtering", "Enable/disable OpenMP global filtering pass">; defm ppc_native_vec_elem_order: BoolOptionWithoutMarshalling<"f", "ppc-native-vector-element-order", PosFlag, NegFlag>; @@ -7364,6 +7533,15 @@ def fhermetic_module_files : Flag<["-"], "fhermetic-module-files">, Group, Values<"none, host, device">; + +def fdefer_desc_map : Flag<["-"], "fdefer-desc-map">, Group, + HelpText<"Enable deferred descriptor mapping, which puts off top-level descriptor " + "mapping until target regions, this is the default behaviour">; + +def fno_defer_desc_map : Flag<["-"], "fno-defer-desc-map">, Group, + HelpText<"Disable deferred deferred descriptor mapping, which puts off top-level " + " descriptor mapping till target regions">; + } // let Visibility = [FC1Option, FlangOption] def J : JoinedOrSeparate<["-"], "J">, @@ -8636,6 +8814,10 @@ def fnative_half_arguments_and_returns : Flag<["-"], "fnative-half-arguments-and HelpText<"Use the native __fp16 type for arguments and returns (and skip ABI-specific lowering)">, MarshallingInfoFlag>, ImpliedByAnyOf<[open_cl.KeyPath, hlsl.KeyPath, hip.KeyPath]>; +def fallow_half_arguments_and_returns : Flag<["-"], "fallow-half-arguments-and-returns">, + HelpText<"Allow function arguments and returns of type half">, + MarshallingInfoFlag>, + ImpliedByAnyOf<[open_cl.KeyPath, hlsl.KeyPath, hip.KeyPath]>; def fdefault_calling_conv_EQ : Joined<["-"], "fdefault-calling-conv=">, HelpText<"Set default calling convention">, Values<"cdecl,fastcall,stdcall,vectorcall,regcall,rtdcall">, @@ -8763,7 +8945,7 @@ def source_date_epoch : Separate<["-"], "source-date-epoch">, // CUDA Options //===----------------------------------------------------------------------===// -let Visibility = [CC1Option] in { +let Visibility = [CC1Option, FC1Option] in { def fcuda_is_device : Flag<["-"], "fcuda-is-device">, HelpText<"Generate code for CUDA device">, @@ -9468,6 +9650,117 @@ def _SLASH_Zg : CLFlag<"Zg">; def _SLASH_ZI : CLFlag<"ZI">; def _SLASH_ZW : CLJoined<"ZW">; + + +//===----------------------------------------------------------------------===// +// AOCC Optimization Options +//===----------------------------------------------------------------------===// + +let Visibility = [ClangOption, CLOption, FlangOption] in { +def famd_opt : Flag<["-"], "famd-opt">, Group, + HelpText<"Enable \"All\" [AMD] proprietary Optimizations">; +def fno_amd_opt : Flag<["-"], "fno-amd-opt">, Group; +} +def famd_allow_threadprivate_equivalence : Flag<["-"], "famd-allow-threadprivate-equivalence">, + Flags<[HelpHidden]>, Group, Visibility<[FlangOption, FC1Option]>, + HelpText<"Allow to use veriables in EQUIVALENCE statements with THREADPRIVATE">; +let Visibility = [ClangOption, CLOption] in { +def floop_unswitch_aggressive : Flag<["-"], "floop-unswitch-aggressive">, Group, + HelpText<"Aggressively unswitch loops.">; +def fno_loop_unswitch_aggressive: Flag<["-"], "fno-loop-unswitch-aggressive">, Group; +def fsimplify_pow : Flag<["-"], "fsimplify-pow">, Group, + HelpText<"Enable SimplifyPowLibCalls pass">; +def fno_simplify_pow : Flag<["-"], "fno-simplify-pow">, Group; + +def fitodcalls : Flag<["-"], "fitodcalls">, Group, + HelpText<"Enable indirect to direct call promotion">; +def fno_itodcalls : Flag<["-"], "fno-itodcalls">, Group; +def fitodcallsbyclone : Flag<["-"], "fitodcallsbyclone">, Group, + HelpText<"Enable indirect to direct call promotion by funnction cloning">; +def fno_itodcallsbyclone : Flag<["-"], "fno-itodcallsbyclone">, Group; + +def fproactive_loop_fusion : Flag<["-"], "fproactive-loop-fusion">, Group, + HelpText<"Enable the loop fusion passes">; +def fno_proactive_loop_fusion : Flag<["-"], "fno-proactive-loop-fusion">, Group; +def fproactive_loop_fusion_analysis : Flag<["-"], "fproactive-loop-fusion-analysis">, Group, + HelpText<"Enable the loop fusion analysis passes">; +def fno_proactive_loop_fusion_analysis : Flag<["-"], "fno-proactive-loop-fusion analysis">, Group; + +def finline_aggressive : Flag<["-"], "finline-aggressive">, Group, + HelpText<"Enable aggresive Inlining during LTO">; +def fno_inline_aggressive : Flag<["-"], "fno-inline-aggressive">, Group; + +def floop_splitting : Flag<["-"], "floop-splitting">, Group, + HelpText<"Enable the inter procedural loop splitting pass">; +def fno_loop_splitting : Flag<["-"], "fno-loop-splitting">, Group; + +def fremove_unused_array_ops : Flag<["-"], "fremove-unused-array-ops">, Group, + HelpText<"Enable the Dead Array op elimination passes">; +def fnoremove_unused_array_ops : Flag<["-"], "fno-remove-unused-array-ops">, Group; + +def finline_recursion_EQ : Joined<["-"], "finline-recursion=">, Group, + HelpText<"Enable the Inline Recursive Pass">; + +def fno_branch_combine : Flag<["-"], "fno-branch-combine">, Group, + HelpText<"Disable Branch Combine pass">; + +def flv_function_specialization : Flag<["-"], "flv-function-specialization">, Group, + HelpText<"Enable Function Specialization For Vectorization">; +def fno_lv_function_specialization : Flag<["-"], "fno-lv-function-specialization">, Group; + +def farray_remap : Flag<["-"], "fremap-arrays">, Group, + HelpText<"Enable the Array Remapping passes">; +def fno_array_remap : Flag<["-"], "fno-remap-arrays">, Group; + +def fstruct_layout_EQ : Joined<["-"], "fstruct-layout=">, Group, + HelpText<"Enable the Structure Peeling passes">; + +def fstruct_peel_ptr_size_EQ : Joined<["-"], "fstruct-peel-ptr-size=">, Group, + Flags<[HelpHidden]>, + HelpText<"Enable aggresive self referential pointer compression during structure-peeling">; + +def fstruct_peel_mem_block_size_EQ : Joined<["-"], "fstruct-peel-mem-block-size=">, Group, + Flags<[HelpHidden]>, + HelpText<"Enable to change unit memory block size used by structure peeling">; + +def fnt_store_EQ : Joined<["-"], "fnt-store=">, Visibility<[CC1Option]>, Group, + HelpText<"Enable Nontemporal store instruction generation. Options: never, auto, aggressive.">, Values<"never,auto,aggressive">; + +def fnt_store : Flag<["-"], "fnt-store">, Group, Visibility<[CC1Option]>, + Alias, AliasArgs<["auto"]>, + HelpText<"Enable Nontemporal store instruction generation">; + +} + + +def inline_aggressive : Flag<["-"], "inline-aggressive">, + HelpText<"Enable aggresive Inlining during LTO">; +def array_remap : Flag<["-"], "remap-arrays">, + HelpText<"Run the Array Remapping passes">; +def struct_layout_EQ : Joined<["-"], "struct-layout=">, + HelpText<"Run the Structure Peeling passes">; +def struct_peel_ptr_size_EQ : Joined<["-"], "struct-peel-ptr-size=">, + HelpText<"Enable aggresive self referential pointer compression during structure-peeling">; +def struct_peel_mem_block_size_EQ : Joined<["-"], "struct-peel-mem-block-size=">, + HelpText<"Enable to change unit memory block size used by structure peeling">; +def remove_unused_array_ops : Flag<["-"], "remove-unused-array-ops">, + HelpText<"Enable the Dead Array op elimination passes">; +def inline_recursion_EQ : Joined<["-"], "inline-recursion=">, + HelpText<"Run the Inline Recursion Pass">; +def lv_function_specialization : Flag<["-"], "lv-function-specialization">, + HelpText<"Enable Function Specialization For Vectorization">; +def simplify_pow : Flag<["-"], "simplify-pow">, + HelpText<"Enable SimplifyPowLibCalls pass">; +def itodcalls : Flag<["-"], "itodcalls">, + HelpText<"Enable indirect to direct call promotion">; +def no_itodcalls : Flag<["-"], "disable-itodcalls">, + HelpText<"Disable indirect to direct call promotion">; +def itodcallsbyclone : Flag<["-"], "itodcallsbyclone">, + HelpText<"Enable indirect to direct call promotion by function cloning">; +def no_itodcallsbyclone : Flag<["-"], "disable-itodcallsbyclone">, + HelpText<"Disable indirect to direct call promotion by function cloning">; +// AOCC END + //===----------------------------------------------------------------------===// // clang-dxc Options //===----------------------------------------------------------------------===// diff --git a/clang/include/clang/Driver/Phases.h b/clang/include/clang/Driver/Phases.h index 9003c58573513..f8cac9548d02f 100644 --- a/clang/include/clang/Driver/Phases.h +++ b/clang/include/clang/Driver/Phases.h @@ -17,6 +17,7 @@ namespace phases { enum ID { Preprocess, Precompile, + FortranFrontend, Compile, Backend, Assemble, diff --git a/clang/include/clang/Driver/ToolChain.h b/clang/include/clang/Driver/ToolChain.h index 1425714d34110..1bf81be7ffd3d 100644 --- a/clang/include/clang/Driver/ToolChain.h +++ b/clang/include/clang/Driver/ToolChain.h @@ -14,6 +14,7 @@ #include "clang/Basic/Sanitizers.h" #include "clang/Driver/Action.h" #include "clang/Driver/Multilib.h" +#include "clang/Driver/Tool.h" #include "clang/Driver/Types.h" #include "llvm/ADT/APFloat.h" #include "llvm/ADT/ArrayRef.h" @@ -54,10 +55,10 @@ class ObjCRuntime; namespace driver { +class Compilation; class Driver; class InputInfo; class SanitizerArgs; -class Tool; class XRayArgs; /// Helper structure used to pass information extracted from clang executable @@ -196,6 +197,8 @@ class ToolChain { mutable std::optional unwindLibType; protected: + // OpenMP creates a toolchain for each target arch. eg - gfx908 + std::string TargetID; MultilibSet Multilibs; llvm::SmallVector SelectedMultilibs; @@ -289,6 +292,8 @@ class ToolChain { return !EffectiveTriple.getTriple().empty(); } + StringRef getTargetID() const { return TargetID; } + path_list &getLibraryPaths() { return LibraryPaths; } const path_list &getLibraryPaths() const { return LibraryPaths; } @@ -692,6 +697,22 @@ class ToolChain { AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const; + /// \brief Add the flang arguments for system include paths. + /// + /// This routine is responsible for adding the -stdinc argument to + /// include headers and module files from standard system header directories. + virtual void + AddFlangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &Flang1Args) const {} + + /// Add options that need to be passed to cc1 for this target that could add + /// commands to the compilation to transform an input. + virtual void + addActionsFromClangTargetOptions(const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args, + const JobAction &JA, Compilation &C, + const InputInfoList &Inputs) const; + /// Add options that need to be passed to cc1 for this target. virtual void addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, diff --git a/clang/include/clang/Driver/Types.def b/clang/include/clang/Driver/Types.def index 76944ec656917..4daea1e08a1cb 100644 --- a/clang/include/clang/Driver/Types.def +++ b/clang/include/clang/Driver/Types.def @@ -92,6 +92,9 @@ TYPE("f95", Fortran, PP_Fortran, nullptr, phases TYPE("f95-cpp-input", PP_Fortran, PP_Fortran, "i", phases::Preprocess, phases::Compile, phases::Backend, phases::Assemble, phases::Link) TYPE("java", Java, INVALID, nullptr, phases::Compile, phases::Backend, phases::Assemble, phases::Link) +TYPE("f77", PP_F_FixedForm, INVALID, "fi", phases::Compile, phases::Backend, phases::Assemble, phases::Link) +TYPE("f77-cpp-input", F_FixedForm, PP_F_FixedForm, "fi", phases::Preprocess, phases::Compile, phases::Backend, phases::Assemble, phases::Link) + // LLVM IR/LTO types. We define separate types for IR and LTO because LTO // outputs should use the standard suffixes. TYPE("ir", LLVM_IR, INVALID, "ll", phases::Compile, phases::Backend, phases::Assemble, phases::Link) diff --git a/clang/include/clang/Driver/Types.h b/clang/include/clang/Driver/Types.h index 121b58a6b477d..a9da705c6d350 100644 --- a/clang/include/clang/Driver/Types.h +++ b/clang/include/clang/Driver/Types.h @@ -127,6 +127,12 @@ namespace types { /// source file type (used for clang-cl emulation of \Yc). ID lookupHeaderTypeForSourceType(ID Id); + /// isFreeFormFortran -- is it a free form layout Fortran input + bool isFreeFormFortran(ID Id); + + /// isFixedFormFortran -- is it a fixed form layout Fortran input + bool isFixedFormFortran(ID Id); + } // end namespace types } // end namespace driver } // end namespace clang diff --git a/clang/include/clang/Sema/SemaAMDGPU.h b/clang/include/clang/Sema/SemaAMDGPU.h index bac812a9d4fcf..41e950ccc0800 100644 --- a/clang/include/clang/Sema/SemaAMDGPU.h +++ b/clang/include/clang/Sema/SemaAMDGPU.h @@ -15,12 +15,16 @@ #include "clang/AST/ASTFwd.h" #include "clang/Sema/SemaBase.h" +#include "llvm/ADT/SmallPtrSet.h" namespace clang { class AttributeCommonInfo; +class Expr; class ParsedAttr; class SemaAMDGPU : public SemaBase { + llvm::SmallPtrSet ExpandedPredicates; + public: SemaAMDGPU(Sema &S); @@ -28,6 +32,8 @@ class SemaAMDGPU : public SemaBase { bool checkCoopAtomicFunctionCall(CallExpr *TheCall, bool IsStore); + bool checkScopedMemAccessFunctionCall(CallExpr *TheCall); + bool checkMovDPPFunctionCall(CallExpr *TheCall, unsigned NumArgs, unsigned NumDataArgs); @@ -66,6 +72,11 @@ class SemaAMDGPU : public SemaBase { void handleAMDGPUNumVGPRAttr(Decl *D, const ParsedAttr &AL); void handleAMDGPUMaxNumWorkGroupsAttr(Decl *D, const ParsedAttr &AL); void handleAMDGPUFlatWorkGroupSizeAttr(Decl *D, const ParsedAttr &AL); + + /// Expand a valid use of the feature identification builtins into its + /// corresponding sequence of instructions. + Expr *ExpandAMDGPUPredicateBI(CallExpr *CE); + bool IsPredicate(Expr *E) const; }; } // namespace clang diff --git a/clang/include/clang/Serialization/ASTBitCodes.h b/clang/include/clang/Serialization/ASTBitCodes.h index 5d09d5536e5ab..c18f158525e85 100644 --- a/clang/include/clang/Serialization/ASTBitCodes.h +++ b/clang/include/clang/Serialization/ASTBitCodes.h @@ -1160,7 +1160,7 @@ enum PredefinedTypeIDs { /// /// Type IDs for non-predefined types will start at /// NUM_PREDEF_TYPE_IDs. -const unsigned NUM_PREDEF_TYPE_IDS = 514; +const unsigned NUM_PREDEF_TYPE_IDS = 515; // Ensure we do not overrun the predefined types we reserved // in the enum PredefinedTypeIDs above. diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 687cd46773f43..aafeb35a801fa 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -1389,7 +1389,12 @@ void ASTContext::InitBuiltinTypes(const TargetInfo &Target, } if (Target.getTriple().isAMDGPU() || - (AuxTarget && AuxTarget->getTriple().isAMDGPU())) { + (Target.getTriple().isSPIRV() && + Target.getTriple().getVendor() == llvm::Triple::AMD) || + (AuxTarget && + (AuxTarget->getTriple().isAMDGPU() || + ((AuxTarget->getTriple().isSPIRV() && + AuxTarget->getTriple().getVendor() == llvm::Triple::AMD))))) { #define AMDGPU_TYPE(Name, Id, SingletonId, Width, Align) \ InitBuiltinType(SingletonId, BuiltinType::Id); #include "clang/Basic/AMDGPUTypes.def" @@ -12531,6 +12536,10 @@ static QualType DecodeTypeFromStr(const char *&Str, const ASTContext &Context, Type = Context.AMDGPUBufferRsrcTy; break; } + case 'c': { + Type = Context.AMDGPUFeaturePredicateTy; + break; + } case 't': { Type = Context.AMDGPUTextureTy; break; diff --git a/clang/lib/AST/MicrosoftCXXABI.cpp b/clang/lib/AST/MicrosoftCXXABI.cpp index 1c020c3ad4ad5..3ec3900ee56e6 100644 --- a/clang/lib/AST/MicrosoftCXXABI.cpp +++ b/clang/lib/AST/MicrosoftCXXABI.cpp @@ -24,6 +24,138 @@ using namespace clang; +// Before revising the interface, clone of `ItaniumNumberingContext` from +// `lib/AST/ItaniumCXXABI.cpp`. +// {{{ BEGIN CLONE +namespace { + +/// According to Itanium C++ ABI 5.1.2: +/// the name of an anonymous union is considered to be +/// the name of the first named data member found by a pre-order, +/// depth-first, declaration-order walk of the data members of +/// the anonymous union. +/// If there is no such data member (i.e., if all of the data members +/// in the union are unnamed), then there is no way for a program to +/// refer to the anonymous union, and there is therefore no need to mangle its name. +/// +/// Returns the name of anonymous union VarDecl or nullptr if it is not found. +static const IdentifierInfo *findAnonymousUnionVarDeclName(const VarDecl& VD) { + const RecordType *RT = VD.getType()->getAs(); + assert(RT && "type of VarDecl is expected to be RecordType."); + assert(RT->getOriginalDecl()->isUnion() && "RecordType is expected to be a union."); + if (const FieldDecl *FD = RT->getOriginalDecl()->findFirstNamedDataMember()) { + return FD->getIdentifier(); + } + + return nullptr; +} + +/// The name of a decomposition declaration. +struct DecompositionDeclName { + using BindingArray = ArrayRef; + + /// Representative example of a set of bindings with these names. + BindingArray Bindings; + + /// Iterators over the sequence of identifiers in the name. + struct Iterator + : llvm::iterator_adaptor_base { + Iterator(BindingArray::const_iterator It) : iterator_adaptor_base(It) {} + const IdentifierInfo *operator*() const { + return (*this->I)->getIdentifier(); + } + }; + Iterator begin() const { return Iterator(Bindings.begin()); } + Iterator end() const { return Iterator(Bindings.end()); } +}; +} + +namespace llvm { +template<> +struct DenseMapInfo { + using ArrayInfo = llvm::DenseMapInfo>; + using IdentInfo = llvm::DenseMapInfo; + static DecompositionDeclName getEmptyKey() { + return {ArrayInfo::getEmptyKey()}; + } + static DecompositionDeclName getTombstoneKey() { + return {ArrayInfo::getTombstoneKey()}; + } + static unsigned getHashValue(DecompositionDeclName Key) { + assert(!isEqual(Key, getEmptyKey()) && !isEqual(Key, getTombstoneKey())); + return llvm::hash_combine_range(Key.begin(), Key.end()); + } + static bool isEqual(DecompositionDeclName LHS, DecompositionDeclName RHS) { + if (ArrayInfo::isEqual(LHS.Bindings, ArrayInfo::getEmptyKey())) + return ArrayInfo::isEqual(RHS.Bindings, ArrayInfo::getEmptyKey()); + if (ArrayInfo::isEqual(LHS.Bindings, ArrayInfo::getTombstoneKey())) + return ArrayInfo::isEqual(RHS.Bindings, ArrayInfo::getTombstoneKey()); + return LHS.Bindings.size() == RHS.Bindings.size() && + std::equal(LHS.begin(), LHS.end(), RHS.begin()); + } +}; +} + +namespace { + +/// Keeps track of the mangled names of lambda expressions and block +/// literals within a particular context. +class ItaniumNumberingContext : public MangleNumberingContext { + llvm::DenseMap ManglingNumbers; + llvm::DenseMap VarManglingNumbers; + llvm::DenseMap TagManglingNumbers; + llvm::DenseMap + DecompsitionDeclManglingNumbers; + +public: + unsigned getManglingNumber(const CXXMethodDecl *CallOperator) override { + const FunctionProtoType *Proto = + CallOperator->getType()->getAs(); + ASTContext &Context = CallOperator->getASTContext(); + + FunctionProtoType::ExtProtoInfo EPI; + EPI.Variadic = Proto->isVariadic(); + QualType Key = + Context.getFunctionType(Context.VoidTy, Proto->getParamTypes(), EPI); + Key = Context.getCanonicalType(Key); + return ++ManglingNumbers[Key->castAs()]; + } + + unsigned getManglingNumber(const BlockDecl *BD) override { + const Type *Ty = nullptr; + return ++ManglingNumbers[Ty]; + } + + unsigned getStaticLocalNumber(const VarDecl *VD) override { + return 0; + } + + /// Variable decls are numbered by identifier. + unsigned getManglingNumber(const VarDecl *VD, unsigned) override { + if (auto *DD = dyn_cast(VD)) { + DecompositionDeclName Name{DD->bindings()}; + return ++DecompsitionDeclManglingNumbers[Name]; + } + + const IdentifierInfo *Identifier = VD->getIdentifier(); + if (!Identifier) { + // VarDecl without an identifier represents an anonymous union + // declaration. + Identifier = findAnonymousUnionVarDeclName(*VD); + } + return ++VarManglingNumbers[Identifier]; + } + + unsigned getManglingNumber(const TagDecl *TD, unsigned) override { + return ++TagManglingNumbers[TD->getIdentifier()]; + } +}; + +} // End anonymous namesapce +// END CLONE }}} + namespace { /// Numbers things which need to correspond across multiple TUs. diff --git a/clang/lib/AST/StmtOpenMP.cpp b/clang/lib/AST/StmtOpenMP.cpp index a5b0cd3786a28..59ac3b25a0bc6 100644 --- a/clang/lib/AST/StmtOpenMP.cpp +++ b/clang/lib/AST/StmtOpenMP.cpp @@ -2535,10 +2535,6 @@ OMPTeamsGenericLoopDirective *OMPTeamsGenericLoopDirective::Create( Dir->setNextLowerBound(Exprs.NLB); Dir->setNextUpperBound(Exprs.NUB); Dir->setNumIterations(Exprs.NumIterations); - Dir->setPrevLowerBoundVariable(Exprs.PrevLB); - Dir->setPrevUpperBoundVariable(Exprs.PrevUB); - Dir->setDistInc(Exprs.DistInc); - Dir->setPrevEnsureUpperBound(Exprs.PrevEUB); Dir->setCounters(Exprs.Counters); Dir->setPrivateCounters(Exprs.PrivateCounters); Dir->setInits(Exprs.Inits); @@ -2548,15 +2544,6 @@ OMPTeamsGenericLoopDirective *OMPTeamsGenericLoopDirective::Create( Dir->setDependentInits(Exprs.DependentInits); Dir->setFinalsConditions(Exprs.FinalsConditions); Dir->setPreInits(Exprs.PreInits); - Dir->setCombinedLowerBoundVariable(Exprs.DistCombinedFields.LB); - Dir->setCombinedUpperBoundVariable(Exprs.DistCombinedFields.UB); - Dir->setCombinedEnsureUpperBound(Exprs.DistCombinedFields.EUB); - Dir->setCombinedInit(Exprs.DistCombinedFields.Init); - Dir->setCombinedCond(Exprs.DistCombinedFields.Cond); - Dir->setCombinedNextLowerBound(Exprs.DistCombinedFields.NLB); - Dir->setCombinedNextUpperBound(Exprs.DistCombinedFields.NUB); - Dir->setCombinedDistCond(Exprs.DistCombinedFields.DistCond); - Dir->setCombinedParForInDistCond(Exprs.DistCombinedFields.ParForInDistCond); return Dir; } @@ -2575,8 +2562,8 @@ OMPTargetTeamsGenericLoopDirective *OMPTargetTeamsGenericLoopDirective::Create( const HelperExprs &Exprs, bool CanBeParallelFor) { auto *Dir = createDirective( C, Clauses, AssociatedStmt, - numLoopChildren(CollapsedNum, OMPD_target_teams_loop), StartLoc, EndLoc, - CollapsedNum); + numLoopChildren(CollapsedNum, OMPD_target_teams_loop), StartLoc, + EndLoc, CollapsedNum); Dir->setIterationVariable(Exprs.IterationVarRef); Dir->setLastIteration(Exprs.LastIteration); Dir->setCalcLastIteration(Exprs.CalcLastIteration); diff --git a/clang/lib/Analysis/UninitializedValues.cpp b/clang/lib/Analysis/UninitializedValues.cpp index f6b1c67ab20c3..8c9cf8dac79ed 100644 --- a/clang/lib/Analysis/UninitializedValues.cpp +++ b/clang/lib/Analysis/UninitializedValues.cpp @@ -276,7 +276,13 @@ namespace { /// escaped the analysis and will be treated as an initialization. class ClassifyRefs : public StmtVisitor { public: - enum Class { Init, Use, SelfInit, ConstRefUse, ConstPtrUse, Ignore }; + enum Class { + Init, + Use, + SelfInit, + ConstRefUse, + Ignore + }; private: const DeclContext *DC; @@ -445,7 +451,8 @@ void ClassifyRefs::VisitCallExpr(CallExpr *CE) { const Expr *Ex = stripCasts(DC->getParentASTContext(), *I); const auto *UO = dyn_cast(Ex); if (UO && UO->getOpcode() == UO_AddrOf) - classify(UO->getSubExpr(), isTrivialBody ? Ignore : ConstPtrUse); + Ex = UO->getSubExpr(); + classify(Ex, Ignore); } } } @@ -489,7 +496,6 @@ class TransferFunctions : public StmtVisitor { void reportUse(const Expr *ex, const VarDecl *vd); void reportConstRefUse(const Expr *ex, const VarDecl *vd); - void reportConstPtrUse(const Expr *ex, const VarDecl *vd); void VisitBinaryOperator(BinaryOperator *bo); void VisitBlockExpr(BlockExpr *be); @@ -676,15 +682,6 @@ void TransferFunctions::reportConstRefUse(const Expr *ex, const VarDecl *vd) { } } -void TransferFunctions::reportConstPtrUse(const Expr *ex, const VarDecl *vd) { - Value v = vals[vd]; - if (isAlwaysUninit(v)) { - auto use = getUninitUse(ex, vd, v); - use.setConstPtrUse(); - handler.handleUseOfUninitVariable(vd, use); - } -} - void TransferFunctions::VisitObjCForCollectionStmt(ObjCForCollectionStmt *FS) { // This represents an initialization of the 'element' value. if (const auto *DS = dyn_cast(FS->getElement())) { @@ -757,9 +754,6 @@ void TransferFunctions::VisitDeclRefExpr(DeclRefExpr *dr) { case ClassifyRefs::ConstRefUse: reportConstRefUse(dr, cast(dr->getDecl())); break; - case ClassifyRefs::ConstPtrUse: - reportConstPtrUse(dr, cast(dr->getDecl())); - break; } } diff --git a/clang/lib/Basic/OpenMPKinds.cpp b/clang/lib/Basic/OpenMPKinds.cpp index 64b2bff063340..769d92007d0c0 100644 --- a/clang/lib/Basic/OpenMPKinds.cpp +++ b/clang/lib/Basic/OpenMPKinds.cpp @@ -748,7 +748,7 @@ bool clang::isOpenMPLoopBoundSharingDirective(OpenMPDirectiveKind Kind) { Kind == OMPD_teams_distribute_parallel_for || Kind == OMPD_target_teams_distribute_parallel_for || Kind == OMPD_target_teams_distribute_parallel_for_simd || - Kind == OMPD_teams_loop || Kind == OMPD_target_teams_loop; + Kind == OMPD_target_teams_loop; } bool clang::isOpenMPCanonicalLoopNestTransformationDirective( @@ -852,6 +852,15 @@ void clang::getOpenMPCaptureRegions( assert(unsigned(DKind) < llvm::omp::Directive_enumSize); assert(isOpenMPCapturingDirective(DKind) && "Expecting capturing directive"); + auto IsTeamsLoop = [&]() { + // Assume the current leaf is OMPD_loop, check if the CaptureRegions + // contains only OMPD_teams. + // Upstream OMPD_teams_loop has two regions: OMPD_teams, OMPD_parallel. + // Downstream, it has only one: OMPD_teams. Avoid adding the parallel + // region in this specific case. + return CaptureRegions.size() == 1 && CaptureRegions[0] == OMPD_teams; + }; + auto GetRegionsForLeaf = [&](OpenMPDirectiveKind LKind) { assert(isLeafConstruct(LKind) && "Epecting leaf directive"); // Whether a leaf would require OMPD_unknown if it occured on its own. @@ -887,7 +896,8 @@ void clang::getOpenMPCaptureRegions( // If any of the directives that push regions here are parents of 'loop', // assume 'parallel'. Otherwise do nothing. if (!CaptureRegions.empty() && - !llvm::is_contained(CaptureRegions, OMPD_parallel)) + !llvm::is_contained(CaptureRegions, OMPD_parallel) && + !IsTeamsLoop()) CaptureRegions.push_back(OMPD_parallel); else return true; @@ -927,7 +937,7 @@ void clang::getOpenMPCaptureRegions( // constructs were present. Push a single OMPD_unknown as the capture /// region. if (CaptureRegions.empty() && MayNeedUnknownRegion) - CaptureRegions.push_back(OMPD_unknown); + CaptureRegions.push_back(OMPD_unknown); // OMPD_unknown is only expected as the only region. If other regions // are present OMPD_unknown should not be present. diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp index 2336fb3ef0495..19f160e279b21 100644 --- a/clang/lib/Basic/Targets/SPIR.cpp +++ b/clang/lib/Basic/Targets/SPIR.cpp @@ -181,3 +181,12 @@ void SPIRV64AMDGCNTargetInfo::setAuxTarget(const TargetInfo *Aux) { Float128Format = DoubleFormat; } } + +bool SPIRV64AMDGCNTargetInfo::isValidCPUName(StringRef CPU) const { + return AMDGPUTI.isValidCPUName(CPU); +} + +void SPIRV64AMDGCNTargetInfo::fillValidCPUList( + SmallVectorImpl &Values) const { + return AMDGPUTI.fillValidCPUList(Values); +} diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h index 22b2799518dd0..141f1bf364e5b 100644 --- a/clang/lib/Basic/Targets/SPIR.h +++ b/clang/lib/Basic/Targets/SPIR.h @@ -467,6 +467,11 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64AMDGCNTargetInfo final } bool hasInt128Type() const override { return TargetInfo::hasInt128Type(); } + + // This is only needed for validating arguments passed to + // __builtin_amdgcn_processor_is + bool isValidCPUName(StringRef Name) const override; + void fillValidCPUList(SmallVectorImpl &Values) const override; }; class LLVM_LIBRARY_VISIBILITY SPIRV64IntelTargetInfo final diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index fd14cd6926fe2..772cb245b7cd7 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -6313,18 +6313,16 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } case Builtin::BI__builtin_printf: case Builtin::BIprintf: - if (getTarget().getTriple().isNVPTX() || - getTarget().getTriple().isAMDGCN() || - (getTarget().getTriple().isSPIRV() && - getTarget().getTriple().getVendor() == Triple::VendorType::AMD)) { - if (getTarget().getTriple().isNVPTX()) - return EmitNVPTXDevicePrintfCallExpr(E); + if (getTarget().getTriple().isNVPTX()) + return EmitNVPTXDevicePrintfCallExpr(E, ReturnValue); + if (getTarget().getTriple().isAMDGCN() || + (getTarget().getTriple().isSPIRV() && + getTarget().getTriple().getVendor() == Triple::VendorType::AMD)) { if ((getTarget().getTriple().isAMDGCN() || getTarget().getTriple().isSPIRV()) && - getLangOpts().HIP) - return EmitAMDGPUDevicePrintfCallExpr(E); + getLangOpts().HIP) + return EmitAMDGPUDevicePrintfCallExpr(E, ReturnValue); } - break; case Builtin::BI__builtin_canonicalize: case Builtin::BI__builtin_canonicalizef: diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index 465f3f4e670c2..d2b8bf5497d26 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -832,7 +832,8 @@ const CGFunctionInfo &CodeGenTypes::arrangeLLVMFunctionInfo( FunctionType::ExtInfo info, ArrayRef paramInfos, RequiredArgs required) { - assert(llvm::all_of(argTypes, + if (!getContext().getLangOpts().OpenMP) + assert(llvm::all_of(argTypes, [](CanQualType T) { return T.isCanonicalAsParam(); })); // Lookup or create unique function info. @@ -3175,6 +3176,9 @@ void CodeGenFunction::EmitFunctionProlog(const CGFunctionInfo &FI, if (ArgI.getInAllocaIndirect()) V = Address(Builder.CreateLoad(V), ConvertTypeForMem(Ty), getContext().getTypeAlignInChars(Ty)); + // FIXME: It seems like we would want to represent inalloca via + // ParamValue more directly, so the debug information can reflect it + // directly. ArgVals.push_back(ParamValue::forIndirect(V)); break; } @@ -3375,8 +3379,10 @@ void CodeGenFunction::EmitFunctionProlog(const CGFunctionInfo &FI, llvm::StructType *STy = dyn_cast(ArgI.getCoerceToType()); + + RawAddress DebugAddr = Address::invalid(); Address Alloca = - CreateMemTemp(Ty, getContext().getDeclAlign(Arg), Arg->getName()); + CreateMemTemp(Ty, getContext().getDeclAlign(Arg), Arg->getName(), &DebugAddr); // Pointer to store into. Address Ptr = emitAddressAtOffset(*this, Alloca, ArgI); @@ -3451,15 +3457,17 @@ void CodeGenFunction::EmitFunctionProlog(const CGFunctionInfo &FI, V = emitArgumentDemotion(*this, Arg, V); ArgVals.push_back(ParamValue::forDirect(V)); } else { - ArgVals.push_back(ParamValue::forIndirect(Alloca)); + ArgVals.push_back(ParamValue::forIndirect(Alloca, DebugAddr)); } break; } case ABIArgInfo::CoerceAndExpand: { // Reconstruct into a temporary. - Address alloca = CreateMemTemp(Ty, getContext().getDeclAlign(Arg)); - ArgVals.push_back(ParamValue::forIndirect(alloca)); + RawAddress DebugAddr = Address::invalid(); + RawAddress alloca = + CreateMemTemp(Ty, getContext().getDeclAlign(Arg), "tmp", &DebugAddr); + ArgVals.push_back(ParamValue::forIndirect(alloca, DebugAddr)); auto coercionType = ArgI.getCoerceAndExpandType(); auto unpaddedCoercionType = ArgI.getUnpaddedCoerceAndExpandType(); @@ -3499,9 +3507,11 @@ void CodeGenFunction::EmitFunctionProlog(const CGFunctionInfo &FI, // If this structure was expanded into multiple arguments then // we need to create a temporary and reconstruct it from the // arguments. - Address Alloca = CreateMemTemp(Ty, getContext().getDeclAlign(Arg)); + RawAddress DebugAddr = Address::invalid(); + RawAddress Alloca = + CreateMemTemp(Ty, getContext().getDeclAlign(Arg), "tmp", &DebugAddr); LValue LV = MakeAddrLValue(Alloca, Ty); - ArgVals.push_back(ParamValue::forIndirect(Alloca)); + ArgVals.push_back(ParamValue::forIndirect(Alloca, DebugAddr)); auto FnArgIter = Fn->arg_begin() + FirstIRArg; ExpandTypeFromArgs(Ty, LV, FnArgIter); @@ -3536,7 +3546,9 @@ void CodeGenFunction::EmitFunctionProlog(const CGFunctionInfo &FI, assert(NumIRArgs == 0); // Initialize the local variable appropriately. if (!hasScalarEvaluationKind(Ty)) { - ArgVals.push_back(ParamValue::forIndirect(CreateMemTemp(Ty))); + RawAddress DebugAddr = Address::invalid(); + RawAddress Alloca = CreateMemTemp(Ty, "tmp", &DebugAddr); + ArgVals.push_back(ParamValue::forIndirect(Alloca, DebugAddr)); } else { llvm::Value *U = llvm::UndefValue::get(ConvertType(Arg->getType())); ArgVals.push_back(ParamValue::forDirect(U)); diff --git a/clang/lib/CodeGen/CGClass.cpp b/clang/lib/CodeGen/CGClass.cpp index f782b0cd17da4..62f5d2f789326 100644 --- a/clang/lib/CodeGen/CGClass.cpp +++ b/clang/lib/CodeGen/CGClass.cpp @@ -2199,6 +2199,10 @@ void CodeGenFunction::EmitCXXConstructorCall(const CXXConstructorDecl *D, llvm::Value *ThisPtr = getAsNaturalPointerTo(This, D->getThisType()->getPointeeType()); + if (CGM.getLangOpts().OpenMPIsTargetDevice && + getContext().getTargetInfo().getTriple().isAMDGCN() && + (SlotAS == LangAS::Default)) + SlotAS = LangAS::cuda_device; if (SlotAS != ThisAS) { unsigned TargetThisAS = getContext().getTargetAddressSpace(ThisAS); llvm::Type *NewType = diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp index 6af806686a3b9..c84f2cc85094b 100644 --- a/clang/lib/CodeGen/CGDebugInfo.cpp +++ b/clang/lib/CodeGen/CGDebugInfo.cpp @@ -371,6 +371,56 @@ void CGDebugInfo::setLocation(SourceLocation Loc) { } } +static llvm::dwarf::MemorySpace getDWARFMemorySpace(LangAS AS) { + using namespace llvm::dwarf; + const MemorySpace + LangASToMS[static_cast(LangAS::FirstTargetAddressSpace)] = { + DW_MSPACE_LLVM_none, // Default + DW_MSPACE_LLVM_global, // opencl_global + DW_MSPACE_LLVM_group, // opencl_local + DW_MSPACE_LLVM_constant, // opencl_constant + DW_MSPACE_LLVM_private, // opencl_private + DW_MSPACE_LLVM_none, // opencl_generic + DW_MSPACE_LLVM_global, // opencl_global_device + DW_MSPACE_LLVM_global, // opencl_global_host + DW_MSPACE_LLVM_global, // cuda_device + DW_MSPACE_LLVM_constant, // cuda_constant + DW_MSPACE_LLVM_group, // cuda_shared + DW_MSPACE_LLVM_global, // sycl_global + DW_MSPACE_LLVM_global, // sycl_global_device + DW_MSPACE_LLVM_global, // sycl_global_host + DW_MSPACE_LLVM_group, // sycl_local + DW_MSPACE_LLVM_private, // sycl_private + DW_MSPACE_LLVM_none, // ptr32_sptr + DW_MSPACE_LLVM_none, // ptr32_uptr + DW_MSPACE_LLVM_none, // ptr64 + DW_MSPACE_LLVM_none, // hlsl_groupshared + }; + const auto i = static_cast>(AS); + if (i < std::size(LangASToMS)) + return LangASToMS[i]; + + // LangAS coming from OpenMP can be out-of-bounds. + // This happened in the test CodeGen/OpenMP/target_parallel_debug_codegen.cpp + return DW_MSPACE_LLVM_none; +} + +static llvm::dwarf::MemorySpace getDWARFMemorySpace(const QualType &QT) { + return getDWARFMemorySpace(QT.getAddressSpace()); +} + +static llvm::dwarf::MemorySpace getDWARFMemorySpace(const ValueDecl *D) { + // When parsing HIP/Cuda, the address space is not attached to the type. + // Instead, create a new QualType + if (D->hasAttr()) + return getDWARFMemorySpace(LangAS::cuda_shared); + if (D->hasAttr()) + return getDWARFMemorySpace(LangAS::cuda_constant); + if (D->hasAttr()) + return getDWARFMemorySpace(LangAS::cuda_device); + return getDWARFMemorySpace(D->getType()); +} + llvm::DIScope *CGDebugInfo::getDeclContextDescriptor(const Decl *D) { llvm::DIScope *Mod = getParentModuleOrNull(D); return getContextDescriptor(cast(D->getDeclContext()), @@ -1089,6 +1139,13 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType *BT) { DBuilder.createBasicType(Name, Width, llvm::dwarf::DW_ATE_unsigned); \ return SingletonId; \ } +#define AMDGPU_FEATURE_PREDICATE_TYPE(Name, Id, SingletonId, Width, Align) \ + case BuiltinType::Id: { \ + if (!SingletonId) \ + SingletonId = \ + DBuilder.createBasicType(Name, Width, llvm::dwarf::DW_ATE_boolean); \ + return SingletonId; \ + } #include "clang/Basic/AMDGPUTypes.def" case BuiltinType::UChar: case BuiltinType::Char_U: @@ -1470,6 +1527,7 @@ llvm::DIType *CGDebugInfo::CreatePointerLikeType(llvm::dwarf::Tag Tag, std::optional DWARFAddressSpace = CGM.getTarget().getDWARFAddressSpace( CGM.getTypes().getTargetAddressSpace(PointeeTy)); + llvm::dwarf::MemorySpace MS = getDWARFMemorySpace(PointeeTy); const BTFTagAttributedType *BTFAttrTy; if (auto *Atomic = PointeeTy->getAs()) @@ -1496,10 +1554,10 @@ llvm::DIType *CGDebugInfo::CreatePointerLikeType(llvm::dwarf::Tag Tag, if (Tag == llvm::dwarf::DW_TAG_reference_type || Tag == llvm::dwarf::DW_TAG_rvalue_reference_type) return DBuilder.createReferenceType(Tag, getOrCreateType(PointeeTy, Unit), - Size, Align, DWARFAddressSpace); + Size, Align, DWARFAddressSpace, MS); else return DBuilder.createPointerType(getOrCreateType(PointeeTy, Unit), Size, - Align, DWARFAddressSpace, StringRef(), + Align, DWARFAddressSpace, MS, StringRef(), Annotations); } @@ -2750,7 +2808,8 @@ llvm::DIType *CGDebugInfo::getOrCreateVTablePtrType(llvm::DIFile *Unit) { CGM.getTarget().getDWARFAddressSpace(VtblPtrAddressSpace); llvm::DIType *vtbl_ptr_type = DBuilder.createPointerType( - SubTy, Size, 0, DWARFAddressSpace, "__vtbl_ptr_type"); + SubTy, Size, 0, DWARFAddressSpace, llvm::dwarf::DW_MSPACE_LLVM_none, + "__vtbl_ptr_type"); VTablePtrType = DBuilder.createPointerType(vtbl_ptr_type, Size); return VTablePtrType; } @@ -2818,7 +2877,7 @@ void CGDebugInfo::emitVTableSymbol(llvm::GlobalVariable *VTable, TheCU, SymbolName, VTable->getName(), Unit, /*LineNo=*/0, getOrCreateType(VoidPtr, Unit), VTable->hasLocalLinkage(), /*isDefined=*/true, nullptr, DT, /*TemplateParameters=*/nullptr, - PAlign); + llvm::dwarf::DW_MSPACE_LLVM_none, PAlign); VTable->addDebugInfo(GVE); } @@ -2910,7 +2969,8 @@ void CGDebugInfo::CollectVTableInfo(const CXXRecordDecl *RD, llvm::DIFile *Unit, // Create a very wide void* type and insert it directly in the element list. llvm::DIType *VTableType = DBuilder.createPointerType( - nullptr, VTableWidth, 0, DWARFAddressSpace, "__vtbl_ptr_type"); + nullptr, VTableWidth, 0, DWARFAddressSpace, + llvm::dwarf::DW_MSPACE_LLVM_none, "__vtbl_ptr_type"); EltTys.push_back(VTableType); // The vptr is a pointer to this special vtable type. @@ -4552,7 +4612,8 @@ CGDebugInfo::getGlobalVariableForwardDeclaration(const VarDecl *VD) { auto Align = getDeclAlignIfRequired(VD, CGM.getContext()); auto *GV = DBuilder.createTempGlobalVariableFwdDecl( DContext, Name, LinkageName, Unit, Line, getOrCreateType(T, Unit), - !VD->isExternallyVisible(), nullptr, TemplateParameters, Align); + !VD->isExternallyVisible(), nullptr, TemplateParameters, + getDWARFMemorySpace(VD), Align); FwdDeclReplaceMap.emplace_back( std::piecewise_construct, std::make_tuple(cast(VD->getCanonicalDecl())), @@ -4939,9 +5000,10 @@ void CGDebugInfo::EmitFunctionDecl(GlobalDecl GD, SourceLocation Loc, unsigned ArgNo = 1; for (ParmVarDecl *PD : FD->parameters()) { llvm::DINodeArray ParamAnnotations = CollectBTFDeclTagAnnotations(PD); + llvm::dwarf::MemorySpace MS = getDWARFMemorySpace(PD); DBuilder.createParameterVariable( SP, PD->getName(), ArgNo, Unit, LineNo, ParamTypes[ArgNo], true, - llvm::DINode::FlagZero, ParamAnnotations); + llvm::DINode::FlagZero, MS, ParamAnnotations); ++ArgNo; } } @@ -5154,6 +5216,10 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const VarDecl *VD, std::optional ArgNo, CGBuilderTy &Builder, const bool UsePointerValue) { + if (CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()) + return EmitDeclareForHeterogeneousDwarf(VD, Storage, ArgNo, Builder, + UsePointerValue); + assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); assert(!LexicalBlockStack.empty() && "Region stack mismatch, stack empty!"); if (VD->hasAttr()) @@ -5176,6 +5242,8 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const VarDecl *VD, if (!Ty) return nullptr; + llvm::dwarf::MemorySpace MS = getDWARFMemorySpace(VD); + // Get location information. unsigned Line = 0; unsigned Column = 0; @@ -5257,7 +5325,7 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const VarDecl *VD, auto *D = DBuilder.createAutoVariable( Scope, FieldName, Unit, Line, FieldTy, CGM.getCodeGenOpts().OptimizationLevel != 0, - Flags | llvm::DINode::FlagArtificial, FieldAlign); + Flags | llvm::DINode::FlagArtificial, MS, FieldAlign); // Insert an llvm.dbg.declare into the current block. DBuilder.insertDeclare(Storage, D, DBuilder.createExpression(Expr), @@ -5284,7 +5352,7 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const VarDecl *VD, llvm::DINodeArray Annotations = CollectBTFDeclTagAnnotations(VD); D = DBuilder.createParameterVariable( Scope, Name, *ArgNo, Unit, Line, Ty, - CGM.getCodeGenOpts().OptimizationLevel != 0, Flags, Annotations); + CGM.getCodeGenOpts().OptimizationLevel != 0, Flags, MS, Annotations); } else { // For normal local variable, we will try to find out whether 'VD' is the // copy parameter of coroutine. @@ -5327,7 +5395,7 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const VarDecl *VD, if (!D) D = DBuilder.createAutoVariable( Scope, Name, Unit, Line, Ty, - CGM.getCodeGenOpts().OptimizationLevel != 0, Flags, Align); + CGM.getCodeGenOpts().OptimizationLevel != 0, Flags, MS, Align); } // Insert an llvm.dbg.declare into the current block. DBuilder.insertDeclare(Storage, D, DBuilder.createExpression(Expr), @@ -5338,11 +5406,296 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const VarDecl *VD, return D; } +llvm::DILocalVariable *CGDebugInfo::EmitDeclareForHeterogeneousDwarf( + const BindingDecl *BD, llvm::Value *Storage, std::optional ArgNo, + CGBuilderTy &Builder, const bool UsePointerValue) { + assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); + assert(!LexicalBlockStack.empty() && "Region stack mismatch, stack empty!"); + if (BD->hasAttr()) + return nullptr; + + // Skip the tuple like case, we don't handle that here + if (isa(BD->getBinding())) + return nullptr; + + llvm::DIFile *Unit = getOrCreateFile(BD->getLocation()); + llvm::DIType *Ty = getOrCreateType(BD->getType(), Unit); + if (!Ty) + return nullptr; + + auto Align = getDeclAlignIfRequired(BD, CGM.getContext()); + + llvm::Type *ValueTy = CGM.getTypes().ConvertTypeForMem(BD->getType()); + llvm::Type *DecomposedTy = + CGM.getTypes().ConvertTypeForMem(BD->getDecomposedDecl()->getType()); + + llvm::DIExprBuilder ExprBuilder(CGM.getLLVMContext()); + ExprBuilder.append(0u, Storage->getType()); + ExprBuilder.append(DecomposedTy); + + if (UsePointerValue) { + llvm::Type *PointeeTy = CGM.getTypes().ConvertTypeForMem( + BD->getDecomposedDecl()->getType()->getPointeeType()); + ExprBuilder.append(PointeeTy); + } + + unsigned Line = getLineNumber(BD->getLocation()); + unsigned Column = getColumnNumber(BD->getLocation()); + StringRef Name = BD->getName(); + auto *Scope = cast(LexicalBlockStack.back()); + // Create the descriptor for the variable. + llvm::DILocalVariable *D = DBuilder.createAutoVariable( + Scope, Name, Unit, Line, Ty, CGM.getCodeGenOpts().OptimizationLevel != 0, + llvm::DINode::FlagZero, getDWARFMemorySpace(BD), Align); + + if (const MemberExpr *ME = dyn_cast(BD->getBinding())) { + if (const FieldDecl *FD = dyn_cast(ME->getMemberDecl())) { + const unsigned fieldIndex = FD->getFieldIndex(); + const clang::CXXRecordDecl *parent = + (const CXXRecordDecl *)FD->getParent(); + const ASTRecordLayout &layout = + CGM.getContext().getASTRecordLayout(parent); + const uint64_t fieldOffset = layout.getFieldOffset(fieldIndex); + + if (fieldOffset % CGM.getContext().getCharWidth() != 0) + return nullptr; + + auto *I32 = llvm::Type::getInt32Ty(CGM.getLLVMContext()); + auto *Offset = llvm::ConstantInt::get(I32, fieldOffset); + ExprBuilder.append(Offset); + ExprBuilder.append(ValueTy); + } + } else if (const ArraySubscriptExpr *ASE = + dyn_cast(BD->getBinding())) { + if (const IntegerLiteral *IL = dyn_cast(ASE->getIdx())) { + const uint64_t value = IL->getValue().getZExtValue(); + const uint64_t typeSize = CGM.getContext().getTypeSize(BD->getType()); + const uint64_t index = + CGM.getContext().toCharUnitsFromBits(value * typeSize).getQuantity(); + auto *I32 = llvm::Type::getInt32Ty(CGM.getLLVMContext()); + auto *Index = llvm::ConstantInt::get(I32, index); + ExprBuilder.append(Index); + ExprBuilder.append(ValueTy); + } + } + + DBuilder.insertDeclare(Storage, D, ExprBuilder.intoExpression(), + llvm::DILocation::get(CGM.getLLVMContext(), Line, + Column, Scope, CurInlinedAt), + Builder.GetInsertBlock()); + return D; +} + +llvm::DILocalVariable *CGDebugInfo::EmitDeclareForHeterogeneousDwarf( + const VarDecl *VD, llvm::Value *Storage, std::optional ArgNo, + CGBuilderTy &Builder, const bool UsePointerValue) { + assert(CGM.getCodeGenOpts().hasReducedDebugInfo() && + "Call to EmitDef below ReducedDebugInfo"); + assert(CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled() && + "Call to EmitDef without HeterogeneousDwarf enabled"); + assert(!LexicalBlockStack.empty() && "Region stack mismatch, stack empty!"); + if (VD->hasAttr()) + return nullptr; + + // Debug intrinsics expect to take an alloca directly, not an addrspace cast + // thereof. + Storage = Storage->stripPointerCasts(); + + bool Unwritten = + VD->isImplicit() || (isa(VD->getDeclContext()) && + cast(VD->getDeclContext())->isImplicit()); + llvm::DIFile *Unit = nullptr; + unsigned Line = 0; + unsigned Column = 0; + if (!Unwritten) { + Unit = getOrCreateFile(VD->getLocation()); + // Get location information. + Line = getLineNumber(VD->getLocation()); + Column = getColumnNumber(VD->getLocation()); + } + llvm::DIType *Ty; + uint64_t XOffset = 0; + if (VD->hasAttr()) + Ty = EmitTypeForVarWithBlocksAttr(VD, &XOffset).WrappedType; + else + Ty = getOrCreateType(VD->getType(), Unit); + + // If there is no debug info for this type then do not emit debug info + // for this variable. + if (!Ty) + return nullptr; + + llvm::dwarf::MemorySpace MS = getDWARFMemorySpace(VD); + + // FIXME: This was previously hard-coded, but we should be deriving this from + // the blocks somehow. Can this differ between the referrer alloca block ref + // and the block ref pointed to by __forwarding? + LangAS BlockAddressSpace = LangAS::Default; + + llvm::DINode::DIFlags Flags = llvm::DINode::FlagZero; + if (Unwritten) + Flags |= llvm::DINode::FlagArtificial; + + auto Align = getDeclAlignIfRequired(VD, CGM.getContext()); + StringRef Name = VD->getName(); + + llvm::Type *VDMemTy = CGM.getTypes().ConvertTypeForMem(VD->getType()); + llvm::Type *BlockPtrTy = llvm::PointerType::getUnqual( + CGM.getLLVMContext()); + + llvm::DIExprBuilder ExprBuilder(CGM.getLLVMContext()); + ExprBuilder.append(0u, Storage->getType()); + llvm::Type *ReferrerPointeeTy = + (!Name.empty() && VD->isEscapingByref()) ? BlockPtrTy : VDMemTy; + if (UsePointerValue) + ExprBuilder.append(Storage->getType()); + else + ExprBuilder.append(ReferrerPointeeTy); + + // If this is implicit parameter of CXXThis or ObjCSelf kind, then give it an + // object pointer flag. + if (const auto *IPD = dyn_cast(VD)) { + if (IPD->getParameterKind() == ImplicitParamKind::CXXThis || + IPD->getParameterKind() == ImplicitParamKind::ObjCSelf) + Flags |= llvm::DINode::FlagObjectPointer; + } + + auto *Scope = cast(LexicalBlockStack.back()); + if (!Name.empty()) { + // __block vars are stored on the heap if they are captured by a block that + // can escape the local scope. + if (VD->isEscapingByref()) { + auto ToChars = [&](uint64_t BitSize) { + return CGM.getContext().toCharUnitsFromBits(BitSize).getQuantity(); + }; + auto *Int64Ty = llvm::Type::getInt64Ty(CGM.getLLVMContext()); + // offset to __forwarding field + ExprBuilder.append(llvm::ConstantInt::get( + Int64Ty, + ToChars(CGM.getTarget().getPointerWidth(BlockAddressSpace)))); + ExprBuilder.append(BlockPtrTy); + // follow __forwarding field + ExprBuilder.append(BlockPtrTy); + // offset of x field + ExprBuilder.append( + llvm::ConstantInt::get(Int64Ty, ToChars(XOffset))); + ExprBuilder.append(VDMemTy); + } + } else if (const auto *RT = dyn_cast(VD->getType())) { + // If VD is an anonymous union then Storage represents value for + // all union fields. + const RecordDecl *RD = RT->getOriginalDecl()->getDefinitionOrSelf(); + if (RD->isUnion() && RD->isAnonymousStructOrUnion()) { + llvm::DIExprBuilder UnionExprBuilder{ExprBuilder}; + llvm::DIExpression *UnionDIExpression = UnionExprBuilder.intoExpression(); + + // GDB has trouble finding local variables in anonymous unions, so we emit + // artificial local variables for each of the members. + // + // FIXME: Remove this code as soon as GDB supports this. + // The debug info verifier in LLVM operates based on the assumption that a + // variable has the same size as its storage and we had to disable the + // check for artificial variables. + for (const auto *Field : RD->fields()) { + llvm::DIType *FieldTy = getOrCreateType(Field->getType(), Unit); + StringRef FieldName = Field->getName(); + + // Ignore unnamed fields. Do not ignore unnamed records. + if (FieldName.empty() && !isa(Field->getType())) + continue; + + // Use VarDecl's Tag, Scope and Line number. + auto FieldAlign = getDeclAlignIfRequired(Field, CGM.getContext()); + auto *D = DBuilder.createAutoVariable( + Scope, FieldName, Unit, Line, FieldTy, /*AlwaysPreserve=*/true, + Flags | llvm::DINode::FlagArtificial, MS, FieldAlign); + + // Insert an intrinsic into the current block. + DBuilder.insertDeclare(Storage, D, UnionDIExpression, + llvm::DILocation::get(CGM.getLLVMContext(), Line, + Column, Scope, + CurInlinedAt), + Builder.GetInsertBlock()); + } + } + } + + // Clang stores the sret pointer provided by the caller in a static alloca. + // Use DW_OP_deref to tell the debugger to load the pointer and treat it as + // the address of the variable. + if (UsePointerValue) + ExprBuilder.append(VDMemTy); + + llvm::DILocalVariable *D = nullptr; + if (ArgNo) { + D = DBuilder.createParameterVariable(Scope, Name, *ArgNo, Unit, Line, Ty, + /*AlwaysPreserve=*/true, Flags, MS); + } else { + // For normal local variable, we will try to find out whether 'VD' is the + // copy parameter of coroutine. + // If yes, we are going to use DIVariable of the origin parameter instead + // of creating the new one. + // If no, it might be a normal alloc, we just create a new one for it. + + // Check whether the VD is move parameters. + auto RemapCoroArgToLocalVar = [&]() -> llvm::DILocalVariable * { + // The scope of parameter and move-parameter should be distinct + // DISubprogram. + if (!isa(Scope) || !Scope->isDistinct()) + return nullptr; + + auto Iter = llvm::find_if(CoroutineParameterMappings, [&](auto &Pair) { + Stmt *StmtPtr = const_cast(Pair.second); + if (DeclStmt *DeclStmtPtr = dyn_cast(StmtPtr)) { + DeclGroupRef DeclGroup = DeclStmtPtr->getDeclGroup(); + Decl *Decl = DeclGroup.getSingleDecl(); + if (VD == dyn_cast_or_null(Decl)) + return true; + } + return false; + }); + + if (Iter != CoroutineParameterMappings.end()) { + ParmVarDecl *PD = const_cast(Iter->first); + auto Iter2 = llvm::find_if(ParamDbgMappings, [&](auto &DbgPair) { + return DbgPair.first == PD && DbgPair.second->getScope() == Scope; + }); + if (Iter2 != ParamDbgMappings.end()) + return const_cast(Iter2->second); + } + return nullptr; + }; + + // If we couldn't find a move param DIVariable, create a new one. + D = RemapCoroArgToLocalVar(); + // Or we will create a new DIVariable for this Decl if D dose not exists. + if (!D) + D = DBuilder.createAutoVariable(Scope, Name, Unit, Line, Ty, + /*AlwaysPreserve=*/true, Flags, MS, + Align); + } + // Insert an intrinsic into the current block. + DBuilder.insertDeclare(Storage, D, ExprBuilder.intoExpression(), + llvm::DILocation::get(CGM.getLLVMContext(), Line, + Column, Scope, CurInlinedAt), + Builder.GetInsertBlock()); + + llvm::Function *Parent = Builder.GetInsertBlock()->getParent(); + assert(Parent->getSubprogram() && "expected DISubprogram"); + + return D; +} + llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const BindingDecl *BD, llvm::Value *Storage, std::optional ArgNo, CGBuilderTy &Builder, const bool UsePointerValue) { + + if (CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()) + return EmitDeclareForHeterogeneousDwarf(BD, Storage, ArgNo, Builder, + UsePointerValue); + assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); assert(!LexicalBlockStack.empty() && "Region stack mismatch, stack empty!"); if (BD->hasAttr()) @@ -5382,7 +5735,7 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const BindingDecl *BD, // Create the descriptor for the variable. llvm::DILocalVariable *D = DBuilder.createAutoVariable( Scope, Name, Unit, Line, Ty, CGM.getCodeGenOpts().OptimizationLevel != 0, - llvm::DINode::FlagZero, Align); + llvm::DINode::FlagZero, getDWARFMemorySpace(BD), Align); if (const MemberExpr *ME = dyn_cast(BD->getBinding())) { if (const FieldDecl *FD = dyn_cast(ME->getMemberDecl())) { @@ -5502,6 +5855,9 @@ llvm::DIType *CGDebugInfo::CreateSelfType(const QualType &QualTy, void CGDebugInfo::EmitDeclareOfBlockDeclRefVariable( const VarDecl *VD, llvm::Value *Storage, CGBuilderTy &Builder, const CGBlockInfo &blockInfo, llvm::Instruction *InsertPoint) { + // FIXME: Workaround to prevent crash when using with -gheterogeneous-dwarf + if (CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()) + return; assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); assert(!LexicalBlockStack.empty() && "Region stack mismatch, stack empty!"); @@ -5520,6 +5876,8 @@ void CGDebugInfo::EmitDeclareOfBlockDeclRefVariable( else Ty = getOrCreateType(VD->getType(), Unit); + llvm::dwarf::MemorySpace MS = getDWARFMemorySpace(VD); + // Self is passed along as an implicit non-arg variable in a // block. Mark it as the object pointer. if (const auto *IPD = dyn_cast(VD)) @@ -5559,7 +5917,7 @@ void CGDebugInfo::EmitDeclareOfBlockDeclRefVariable( auto Align = getDeclAlignIfRequired(VD, CGM.getContext()); auto *D = DBuilder.createAutoVariable( cast(LexicalBlockStack.back()), VD->getName(), Unit, - Line, Ty, false, llvm::DINode::FlagZero, Align); + Line, Ty, false, llvm::DINode::FlagZero, MS, Align); // Insert an llvm.dbg.declare into the current block. auto DL = llvm::DILocation::get(CGM.getLLVMContext(), Line, Column, @@ -5632,6 +5990,9 @@ void CGDebugInfo::EmitDeclareOfBlockLiteralArgVariable(const CGBlockInfo &block, unsigned ArgNo, llvm::AllocaInst *Alloca, CGBuilderTy &Builder) { + // FIXME: Workaround to prevent crash when using with -gheterogeneous-dwarf + if (CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()) + return; assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); ASTContext &C = CGM.getContext(); const BlockDecl *blockDecl = block.getBlockDecl(); @@ -5775,7 +6136,8 @@ CGDebugInfo::getOrCreateStaticDataMemberDeclarationOrNull(const VarDecl *D) { llvm::DIGlobalVariableExpression *CGDebugInfo::CollectAnonRecordDecls( const RecordDecl *RD, llvm::DIFile *Unit, unsigned LineNo, - StringRef LinkageName, llvm::GlobalVariable *Var, llvm::DIScope *DContext) { + StringRef LinkageName, llvm::dwarf::MemorySpace MS, + llvm::GlobalVariable *Var, llvm::DIScope *DContext) { llvm::DIGlobalVariableExpression *GVE = nullptr; for (const auto *Field : RD->fields()) { @@ -5786,13 +6148,43 @@ llvm::DIGlobalVariableExpression *CGDebugInfo::CollectAnonRecordDecls( if (FieldName.empty()) { if (const auto *RT = dyn_cast(Field->getType())) GVE = CollectAnonRecordDecls(RT->getDecl()->getDefinitionOrSelf(), Unit, - LineNo, LinkageName, Var, DContext); + LineNo, LinkageName, MS, Var, DContext); + continue; + } + // Use VarDecl's Tag, Scope and Line number. + GVE = DBuilder.createGlobalVariableExpression( + DContext, FieldName, LinkageName, Unit, LineNo, FieldTy, + Var->hasLocalLinkage(), true, nullptr, nullptr, nullptr, MS); + Var->addDebugInfo(GVE); + } + return GVE; +} + +llvm::DIGlobalVariableExpression * +CGDebugInfo::CollectAnonRecordDeclsForHeterogeneousDwarf( + const RecordDecl *RD, llvm::DIFile *Unit, unsigned LineNo, + StringRef LinkageName, llvm::dwarf::MemorySpace MS, + llvm::GlobalVariable *Var, llvm::DIScope *DContext) { + assert(CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()); + + llvm::DIGlobalVariableExpression *GVE = nullptr; + + for (const auto *Field : RD->fields()) { + llvm::DIType *FieldTy = getOrCreateType(Field->getType(), Unit); + StringRef FieldName = Field->getName(); + + // Ignore unnamed fields, but recurse into anonymous records. + if (FieldName.empty()) { + if (const auto *RT = dyn_cast(Field->getType())) + GVE = CollectAnonRecordDeclsForHeterogeneousDwarf( + RT->getOriginalDecl()->getDefinitionOrSelf(), Unit, LineNo, + LinkageName, MS, Var, DContext); continue; } // Use VarDecl's Tag, Scope and Line number. GVE = DBuilder.createGlobalVariableExpression( DContext, FieldName, LinkageName, Unit, LineNo, FieldTy, - Var->hasLocalLinkage()); + Var->hasLocalLinkage(), true, nullptr, nullptr, nullptr, MS); Var->addDebugInfo(GVE); } return GVE; @@ -6035,6 +6427,9 @@ std::string CGDebugInfo::GetName(const Decl *D, bool Qualified) const { void CGDebugInfo::EmitGlobalVariable(llvm::GlobalVariable *Var, const VarDecl *D) { + if (CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()) + return EmitGlobalVariableForHeterogeneousDwarf(Var, D); + assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); if (D->hasAttr()) return; @@ -6067,11 +6462,13 @@ void CGDebugInfo::EmitGlobalVariable(llvm::GlobalVariable *Var, // If this is an anonymous union then we'll want to emit a global // variable for each member of the anonymous union so that it's possible // to find the name of any field in the union. + llvm::dwarf::MemorySpace MS = getDWARFMemorySpace(D); if (T->isUnionType() && DeclName.empty()) { const auto *RD = T->castAsRecordDecl(); assert(RD->isAnonymousStructOrUnion() && "unnamed non-anonymous struct or union?"); - GVE = CollectAnonRecordDecls(RD, Unit, LineNo, LinkageName, Var, DContext); + GVE = CollectAnonRecordDecls(RD, Unit, LineNo, LinkageName, MS, Var, + DContext); } else { auto Align = getDeclAlignIfRequired(D, CGM.getContext()); @@ -6092,7 +6489,79 @@ void CGDebugInfo::EmitGlobalVariable(llvm::GlobalVariable *Var, DContext, DeclName, LinkageName, Unit, LineNo, getOrCreateType(T, Unit), Var->hasLocalLinkage(), true, Expr.empty() ? nullptr : DBuilder.createExpression(Expr), - getOrCreateStaticDataMemberDeclarationOrNull(D), TemplateParameters, + getOrCreateStaticDataMemberDeclarationOrNull(D), TemplateParameters, MS, + Align, Annotations); + Var->addDebugInfo(GVE); + } + DeclCache[D->getCanonicalDecl()].reset(GVE); +} + +void CGDebugInfo::EmitGlobalVariableForHeterogeneousDwarf( + llvm::GlobalVariable *Var, const VarDecl *D) { + assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); + assert(CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()); + if (D->hasAttr()) + return; + + llvm::TimeTraceScope TimeScope("DebugGlobalVariable", [&]() { + std::string Name; + llvm::raw_string_ostream OS(Name); + D->getNameForDiagnostic(OS, getPrintingPolicy(), + /*Qualified=*/true); + return Name; + }); + + // FIXME: Need to handle cases like the NOADDROF lines in + // clang/test/CodeGen/debug-info-global-constant-heterogeneous-dwarf.c where + // we should conceptually produce both a memory location description *and* an + // implicit location description because of optimizations along the lines of + // really-early constant folding. Maybe this is an example of why we need to + // support multiple computed lifetime segments for global variables? For now + // just do what existing LLVM does and prefer the implicit location. + auto &GV = DeclCache[D->getCanonicalDecl()]; + if (GV) + return; + + // Create global variable debug descriptor. + llvm::DIFile *Unit = nullptr; + llvm::DIScope *DContext = nullptr; + unsigned LineNo; + StringRef DeclName, LinkageName; + QualType T; + llvm::MDTuple *TemplateParameters = nullptr; + collectVarDeclProps(D, Unit, LineNo, T, DeclName, LinkageName, + TemplateParameters, DContext); + + // Attempt to store one global variable for the declaration - even if we + // emit a lot of fields. + llvm::DIGlobalVariableExpression *GVE = nullptr; + + // If this is an anonymous union then we'll want to emit a global + // variable for each member of the anonymous union so that it's possible + // to find the name of any field in the union. + llvm::dwarf::MemorySpace MS = getDWARFMemorySpace(D); + if (T->isUnionType() && DeclName.empty()) { + const RecordDecl *RD = + T->castAs()->getOriginalDecl()->getDefinitionOrSelf(); + assert(RD->isAnonymousStructOrUnion() && + "unnamed non-anonymous struct or union?"); + // FIXME(KZHURAVL): No tests for this path. + GVE = CollectAnonRecordDeclsForHeterogeneousDwarf( + RD, Unit, LineNo, LinkageName, MS, Var, DContext); + } else { + auto Align = getDeclAlignIfRequired(D, CGM.getContext()); + + // Create DIExpr. + llvm::DIExprBuilder ExprBuilder(CGM.getLLVMContext()); + ExprBuilder.append(0u, Var->getType()); + ExprBuilder.append(Var->getValueType()); + + llvm::DINodeArray Annotations = CollectBTFDeclTagAnnotations(D); + + GVE = DBuilder.createGlobalVariableExpression( + DContext, DeclName, LinkageName, Unit, LineNo, getOrCreateType(T, Unit), + Var->hasLocalLinkage(), true, ExprBuilder.intoExpression(), + getOrCreateStaticDataMemberDeclarationOrNull(D), TemplateParameters, MS, Align, Annotations); Var->addDebugInfo(GVE); } @@ -6100,6 +6569,9 @@ void CGDebugInfo::EmitGlobalVariable(llvm::GlobalVariable *Var, } void CGDebugInfo::EmitGlobalVariable(const ValueDecl *VD, const APValue &Init) { + if (CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()) + return EmitGlobalVariableForHeterogeneousDwarf(VD, Init); + assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); if (VD->hasAttr()) return; @@ -6112,6 +6584,7 @@ void CGDebugInfo::EmitGlobalVariable(const ValueDecl *VD, const APValue &Init) { llvm::DIFile *Unit = getOrCreateFile(VD->getLocation()); StringRef Name = VD->getName(); llvm::DIType *Ty = getOrCreateType(VD->getType(), Unit); + llvm::dwarf::MemorySpace MS = getDWARFMemorySpace(VD); if (const auto *ECD = dyn_cast(VD)) { const auto *ED = cast(ECD->getDeclContext()); @@ -6169,11 +6642,103 @@ void CGDebugInfo::EmitGlobalVariable(const ValueDecl *VD, const APValue &Init) { GV.reset(DBuilder.createGlobalVariableExpression( DContext, Name, StringRef(), Unit, getLineNumber(VD->getLocation()), Ty, true, true, InitExpr, getOrCreateStaticDataMemberDeclarationOrNull(VarD), - TemplateParameters, Align)); + TemplateParameters, MS, Align)); +} + +void CGDebugInfo::EmitGlobalVariableForHeterogeneousDwarf( + const ValueDecl *VD, const APValue &Init) { + assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); + if (VD->hasAttr()) + return; + llvm::TimeTraceScope TimeScope("DebugConstGlobalVariable", [&]() { + return GetName(VD, true); + }); + + auto Align = getDeclAlignIfRequired(VD, CGM.getContext()); + // Create the descriptor for the variable. + llvm::DIFile *Unit = getOrCreateFile(VD->getLocation()); + StringRef Name = VD->getName(); + llvm::DIType *Ty = getOrCreateType(VD->getType(), Unit); + llvm::dwarf::MemorySpace MS = getDWARFMemorySpace(VD); + + if (const auto *ECD = dyn_cast(VD)) { + const auto *ED = cast(ECD->getDeclContext()); + + if (CGM.getCodeGenOpts().EmitCodeView) { + // If CodeView, emit enums as global variables, unless they are defined + // inside a class. We do this because MSVC doesn't emit S_CONSTANTs for + // enums in classes, and because it is difficult to attach this scope + // information to the global variable. + if (isa(ED->getDeclContext())) + return; + } else { + // If not CodeView, emit DW_TAG_enumeration_type if necessary. For + // example: for "enum { ZERO };", a DW_TAG_enumeration_type is created the + // first time `ZERO` is referenced in a function. + CanQualType T = CGM.getContext().getCanonicalTagType(ED); + [[maybe_unused]] llvm::DIType *EDTy = getOrCreateType(T, Unit); + assert(EDTy->getTag() == llvm::dwarf::DW_TAG_enumeration_type); + return; + } + } + + // Do not emit separate definitions for function local consts. + if (isa(VD->getDeclContext())) + return; + + VD = cast(VD->getCanonicalDecl()); + auto *VarD = dyn_cast(VD); + if (VarD && VarD->isStaticDataMember()) { + auto *RD = cast(VarD->getDeclContext()); + getDeclContextDescriptor(VarD); + // Ensure that the type is retained even though it's otherwise unreferenced. + // + // FIXME: This is probably unnecessary, since Ty should reference RD + // through its scope. + RetainedTypes.push_back( + CGM.getContext().getCanonicalTagType(RD).getAsOpaquePtr()); + + return; + } + llvm::DIScope *DContext = getDeclContextDescriptor(VD); + + auto &GV = DeclCache[VD]; + if (GV) + return; + + llvm::MDTuple *TemplateParameters = nullptr; + + if (isa(VD)) + if (VarD) { + llvm::DINodeArray parameterNodes = CollectVarTemplateParams(VarD, &*Unit); + TemplateParameters = parameterNodes.get(); + } + + llvm::DIExprBuilder ExprBuilder(CGM.getLLVMContext()); + // FIXME: There isn't general support for getting a Constant from an APValue, + // but we should be able to support all possibilities here. + if (Init.isInt()) + ExprBuilder.append( + llvm::ConstantInt::get(CGM.getLLVMContext(), Init.getInt())); + else if (Init.isFloat()) + ExprBuilder.append( + llvm::ConstantFP::get(CGM.getLLVMContext(), Init.getFloat())); + + GV.reset(DBuilder.createGlobalVariableExpression( + DContext, Name, StringRef(), Unit, getLineNumber(VD->getLocation()), Ty, + true, true, ExprBuilder.intoExpression(), + getOrCreateStaticDataMemberDeclarationOrNull(VarD), TemplateParameters, + MS, Align)); } void CGDebugInfo::EmitExternalVariable(llvm::GlobalVariable *Var, const VarDecl *D) { + // FIXME: Workaround to prevent crash when using with -gheterogeneous-dwarf + // NOTE: Only currently reachable for BPF target, but check added for + // completeness and in case this changes. + if (CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()) + return; + assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); if (D->hasAttr()) return; @@ -6182,17 +6747,22 @@ void CGDebugInfo::EmitExternalVariable(llvm::GlobalVariable *Var, llvm::DIFile *Unit = getOrCreateFile(D->getLocation()); StringRef Name = D->getName(); llvm::DIType *Ty = getOrCreateType(D->getType(), Unit); + llvm::dwarf::MemorySpace MS = getDWARFMemorySpace(D); llvm::DIScope *DContext = getDeclContextDescriptor(D); llvm::DIGlobalVariableExpression *GVE = DBuilder.createGlobalVariableExpression( DContext, Name, StringRef(), Unit, getLineNumber(D->getLocation()), - Ty, false, false, nullptr, nullptr, nullptr, Align); + Ty, false, false, nullptr, nullptr, nullptr, MS, Align); Var->addDebugInfo(GVE); } void CGDebugInfo::EmitPseudoVariable(CGBuilderTy &Builder, llvm::Instruction *Value, QualType Ty) { + // FIXME: Workaround to prevent crash when using with -gheterogeneous-dwarf + if (CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()) + return; + // Only when -g2 or above is specified, debug info for variables will be // generated. if (CGM.getCodeGenOpts().getDebugInfo() <= @@ -6275,6 +6845,10 @@ void CGDebugInfo::EmitGlobalAlias(const llvm::GlobalValue *GV, void CGDebugInfo::AddStringLiteralDebugInfo(llvm::GlobalVariable *GV, const StringLiteral *S) { + // FIXME: Implement for heterogeneous debug info + if (CGM.getCodeGenOpts().isHeterogeneousDwarfEnabled()) + return; + SourceLocation Loc = S->getStrTokenLoc(0); PresumedLoc PLoc = CGM.getContext().getSourceManager().getPresumedLoc(Loc); if (!PLoc.isValid()) diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h index 78c3eb9c5792e..6ea825f9693c0 100644 --- a/clang/lib/CodeGen/CGDebugInfo.h +++ b/clang/lib/CodeGen/CGDebugInfo.h @@ -558,9 +558,17 @@ class CGDebugInfo { /// Emit information about a global variable. void EmitGlobalVariable(llvm::GlobalVariable *GV, const VarDecl *Decl); + /// Emit information about a global variable (-gheterogeneous-dwarf). + void EmitGlobalVariableForHeterogeneousDwarf(llvm::GlobalVariable *GV, + const VarDecl *Decl); + /// Emit a constant global variable's debug info. void EmitGlobalVariable(const ValueDecl *VD, const APValue &Init); + /// Emit a constant global variable's debug info (-gheterogeneous-dwarf). + void EmitGlobalVariableForHeterogeneousDwarf(const ValueDecl *VD, + const APValue &Init); + /// Emit information about an external variable. void EmitExternalVariable(llvm::GlobalVariable *GV, const VarDecl *Decl); @@ -694,6 +702,20 @@ class CGDebugInfo { CGBuilderTy &Builder, const bool UsePointerValue = false); + /// Emit call to llvm.dbg.declare for a variable definition. + /// Returns a pointer to the DILocalVariable associated with the + /// llvm.dbg.def, or nullptr otherwise. + llvm::DILocalVariable *EmitDeclareForHeterogeneousDwarf( + const VarDecl *decl, llvm::Value *AI, std::optional ArgNo, + CGBuilderTy &Builder, const bool UsePointerValue = false); + + /// Emit call to llvm.dbg.declare for a structured binding definition. + /// Returns a pointer to the DILocalVariable associated with the + /// llvm.dbg.def, or nullptr otherwise. + llvm::DILocalVariable *EmitDeclareForHeterogeneousDwarf( + const BindingDecl *decl, llvm::Value *AI, std::optional ArgNo, + CGBuilderTy &Builder, const bool UsePointerValue = false); + /// Emit call to llvm.dbg.declare for a binding declaration. /// Returns a pointer to the DILocalVariable associated with the /// llvm.dbg.declare, or nullptr otherwise. @@ -702,6 +724,8 @@ class CGDebugInfo { CGBuilderTy &Builder, const bool UsePointerValue = false); + // FIXME: EmitDef(const BindingDecl *... + struct BlockByRefType { /// The wrapper struct used inside the __block_literal struct. llvm::DIType *BlockByRefWrapper; @@ -825,8 +849,20 @@ class CGDebugInfo { llvm::DIGlobalVariableExpression * CollectAnonRecordDecls(const RecordDecl *RD, llvm::DIFile *Unit, unsigned LineNo, StringRef LinkageName, - llvm::GlobalVariable *Var, llvm::DIScope *DContext); + llvm::dwarf::MemorySpace MS, llvm::GlobalVariable *Var, + llvm::DIScope *DContext); + /// Return a global variable that represents one of the collection of global + /// variables created for an anonmyous union (-gheterogeneous-dwarf). + /// + /// Recursively collect all of the member fields of a global + /// anonymous decl and create static variables for them. The first + /// time this is called it needs to be on a union and then from + /// there we can have additional unnamed fields. + llvm::DIGlobalVariableExpression *CollectAnonRecordDeclsForHeterogeneousDwarf( + const RecordDecl *RD, llvm::DIFile *Unit, unsigned LineNo, + StringRef LinkageName, llvm::dwarf::MemorySpace MS, + llvm::GlobalVariable *Var, llvm::DIScope *DContext); /// Return flags which enable debug info emission for call sites, provided /// that it is supported and enabled. diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp index 8b1cd83af2396..079c490fe4d8f 100644 --- a/clang/lib/CodeGen/CGDecl.cpp +++ b/clang/lib/CodeGen/CGDecl.cpp @@ -437,6 +437,12 @@ void CodeGenFunction::EmitStaticVarDecl(const VarDecl &D, ApplyAtomGroup Grp(getDebugInfo()); var = AddInitializerToStaticVarDecl(D, var); } + // amdgcn does not support initializers in LDS + if ((var->getType()->getAddressSpace() == + CGM.getContext().getTargetAddressSpace(LangAS::cuda_shared)) && + (CGM.getContext().getTargetInfo().getTriple().isAMDGCN())) + var->setInitializer( + llvm::UndefValue::get(var->getValueType())); var->setAlignment(alignment.getAsAlign()); @@ -1704,16 +1710,29 @@ CodeGenFunction::EmitAutoVarAlloca(const VarDecl &D) { // Emit debug info for local var declaration. if (EmitDebugInfo && HaveInsertPoint()) { - Address DebugAddr = address; - bool UsePointerValue = NRVO && ReturnValuePointer.isValid(); DI->setLocation(D.getLocation()); - // If NRVO, use a pointer to the return address. + // Even for NRVO, we may not have ReturnValuePointer if the sret parameter + // is also byval. + bool UsePointerValue = NRVO && ReturnValuePointer.isValid(); + Address DebugAddr = Address::invalid(); if (UsePointerValue) { DebugAddr = ReturnValuePointer; - AllocaAddr = ReturnValuePointer; + } else { + // We are either in an alloca, and AllocaAddr is valid, or we are in: + // * An sret+byval NRVO return parameter. + // * A runtime-managed OpenMP allocation. + // FIXME: The assert condition here is overly broad. + // FIXME: Can the cases where OpenMP requires this be eliminated? + assert(AllocaAddr.isValid() || NRVO || + getLangOpts().OpenMP && + "Expected either an alloca, sret+byval NRVO parameter, or " + "OpenMP runtime allocation."); + RawAddress rawAddress = RawAddress(address.emitRawPointer(*this), + address.getElementType(), address.getAlignment()); + DebugAddr = AllocaAddr.isValid() ? AllocaAddr : rawAddress; } - (void)DI->EmitDeclareOfAutoVariable(&D, AllocaAddr.getPointer(), Builder, + (void)DI->EmitDeclareOfAutoVariable(&D, DebugAddr.emitRawPointer(*this), Builder, UsePointerValue); } @@ -2682,6 +2701,7 @@ void CodeGenFunction::EmitParmDecl(const VarDecl &D, ParamValue Arg, } Address DeclPtr = Address::invalid(); + RawAddress DebugPtr = Address::invalid(); RawAddress AllocaPtr = Address::invalid(); bool DoStore = false; bool IsScalar = hasScalarEvaluationKind(Ty); @@ -2690,6 +2710,10 @@ void CodeGenFunction::EmitParmDecl(const VarDecl &D, ParamValue Arg, // If we already have a pointer to the argument, reuse the input pointer. if (Arg.isIndirect()) { DeclPtr = Arg.getIndirectAddress(); + if (auto DebugAddr = Arg.getDebugAddr()) + DebugPtr = *DebugAddr; + else + DebugPtr = DeclPtr; DeclPtr = DeclPtr.withElementType(ConvertTypeForMem(Ty)); // Indirect argument is in alloca address space, which may be different // from the default address space. @@ -2704,9 +2728,10 @@ void CodeGenFunction::EmitParmDecl(const VarDecl &D, ParamValue Arg, UseIndirectDebugAddress = !ArgInfo.getIndirectByVal(); if (UseIndirectDebugAddress) { auto PtrTy = getContext().getPointerType(Ty); - AllocaPtr = CreateMemTemp(PtrTy, getContext().getTypeAlignInChars(PtrTy), - D.getName() + ".indirect_addr"); - EmitStoreOfScalar(V, AllocaPtr, /* Volatile */ false, PtrTy); + Address StackHomedPtr = + CreateMemTemp(PtrTy, getContext().getTypeAlignInChars(PtrTy), + D.getName() + ".indirect_addr", &DebugPtr); + EmitStoreOfScalar(V, StackHomedPtr, /* Volatile */ false, PtrTy); } auto SrcLangAS = getLangOpts().OpenCL ? LangAS::opencl_private : AllocaAS; @@ -2744,12 +2769,11 @@ void CodeGenFunction::EmitParmDecl(const VarDecl &D, ParamValue Arg, ? CGM.getOpenMPRuntime().getAddressOfLocalVariable(*this, &D) : Address::invalid(); if (getLangOpts().OpenMP && OpenMPLocalAddr.isValid()) { - DeclPtr = OpenMPLocalAddr; - AllocaPtr = DeclPtr; + DeclPtr = DebugPtr = OpenMPLocalAddr; } else { // Otherwise, create a temporary to hold the value. DeclPtr = CreateMemTemp(Ty, getContext().getDeclAlign(&D), - D.getName() + ".addr", &AllocaPtr); + D.getName() + ".addr", &DebugPtr); } DoStore = true; } @@ -2838,7 +2862,7 @@ void CodeGenFunction::EmitParmDecl(const VarDecl &D, ParamValue Arg, if (CGM.getCodeGenOpts().hasReducedDebugInfo() && !CurFuncIsThunk && !NoDebugInfo) { llvm::DILocalVariable *DILocalVar = DI->EmitDeclareOfArgVariable( - &D, AllocaPtr.getPointer(), ArgNo, Builder, UseIndirectDebugAddress); + &D, DebugPtr.getPointer(), ArgNo, Builder, UseIndirectDebugAddress); if (const auto *Var = dyn_cast_or_null(&D)) DI->getParamDbgMappings().insert({Var, DILocalVar}); } diff --git a/clang/lib/CodeGen/CGEmitEmissaryExec.cpp b/clang/lib/CodeGen/CGEmitEmissaryExec.cpp new file mode 100644 index 0000000000000..11245ad28caaf --- /dev/null +++ b/clang/lib/CodeGen/CGEmitEmissaryExec.cpp @@ -0,0 +1,387 @@ +//===------- CGEmitEmissaryExec.cpp - Codegen for _emissary_exec --==------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Emits device code for an encountered call to vargs functions _emissary_exec +// The emitted code has three parts: +// 1 call __llvm_omp_emissary_prealloc for memory buffer to contain all args +// 2. Store each arg into the buffer. +// 3. call to __llvm_omp_emissary_rpc function. +//===----------------------------------------------------------------------===// + +#include "../../openmp/device/include/EmissaryIds.h" +#include "CodeGenFunction.h" +#include "clang/Basic/Builtins.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/Instruction.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Transforms/Utils/AMDGPUEmitPrintf.h" + +using namespace clang; +using namespace CodeGen; + +// EmitEmissaryExec: +// +// When a device call to the varadic function _emissary_exec is encountered +// (in CGExpr.cpp) EmitEmissaryExec does these steps: +// +// 1. If string lens are runtime dependent, Emit code to determine runtime len. +// 2. Emits call to allocate memory __llvm_omp_emissary_premalloc, +// 3. Emit stores of each arg into arg buffer, +// 4. Emits call to function __llvm_omp_emissary_rpc. +// +// The arg buffer is a struct that contains the length, number of args, an +// array of 4-byte keys that represent the type of of each arg, an array of +// aligned "data" values for each arg, and finally the runtime string values. +// If an arg is a string the data value is the runtime length of the string. +// Each 4-byte key contains the llvm type ID and the number of bits for the +// type. encoded by the macro _PACK_TY_BITLEN(x,y) ((uint32_t)x << 16) | +// ((uint32_t)y) +// +// TODO: Add example of call to _emissary_exec() and the corresponding struct + +// These static helper functions support EmitEmissaryExec. +static llvm::Function *GetOmpStrlenDeclaration(CodeGenModule &CGM) { + auto &M = CGM.getModule(); + // Args are pointer to char and maxstringlen + llvm::Type *ArgTypes[] = {CGM.Int8PtrTy, CGM.Int32Ty}; + llvm::FunctionType *OmpStrlenFTy = + llvm::FunctionType::get(CGM.Int32Ty, ArgTypes, false); + if (auto *F = M.getFunction("__strlen_max")) { + assert(F->getFunctionType() == OmpStrlenFTy); + return F; + } + llvm::Function *FN = llvm::Function::Create( + OmpStrlenFTy, llvm::GlobalVariable::ExternalLinkage, "__strlen_max", &M); + return FN; +} + +// Deterimines if an expression is a string with variable lenth +static bool isVarString(const clang::Expr *argX, const clang::Type *argXTy, + const llvm::Value *Arg) { + if ((argXTy->isPointerType() || argXTy->isConstantArrayType()) && + argXTy->getPointeeOrArrayElementType()->isCharType() && !argX->isLValue()) + return true; + // Ensure the VarDecl has an inititalizer + if (const auto *DRE = dyn_cast(argX)) + if (const auto *VD = dyn_cast(DRE->getDecl())) + if (!VD->getInit() || + !llvm::isa(VD->getInit()->IgnoreImplicit())) + return true; + return false; +} + +// Deterimines if an argument is a string +static bool isString(const clang::Type *argXTy) { + if ((argXTy->isPointerType() || argXTy->isConstantArrayType()) && + argXTy->getPointeeOrArrayElementType()->isCharType()) + return true; + else + return false; +} + +// Gets a string literal to write into the transfer buffer +static const StringLiteral *getSL(const clang::Expr *argX, + const clang::Type *argXTy) { + // String in argX has known constant length + if (!argXTy->isConstantArrayType()) { + // Allow constant string to be a declared variable, + // But it must be constant and initialized. + const DeclRefExpr *DRE = cast(argX); + const VarDecl *VarD = cast(DRE->getDecl()); + argX = VarD->getInit()->IgnoreImplicit(); + } + const StringLiteral *SL = cast(argX); + return SL; +} + +// Returns a function pointer to __llvm_omp_emissary_premalloc +static llvm::Function *GetEmissaryAllocDeclaration(CodeGenModule &CGM) { + auto &M = CGM.getModule(); + const char *_executeName = "__llvm_omp_emissary_premalloc"; + llvm::Type *ArgTypes[] = {CGM.Int32Ty}; + llvm::Function *FN; + llvm::FunctionType *VargsFnAllocFuncType = llvm::FunctionType::get( + llvm::PointerType::getUnqual(CGM.Int8Ty), ArgTypes, false); + + if (!(FN = M.getFunction(_executeName))) + FN = llvm::Function::Create(VargsFnAllocFuncType, + llvm::GlobalVariable::ExternalLinkage, + _executeName, &M); + assert(FN->getFunctionType() == VargsFnAllocFuncType); + return FN; +} + +// Returns a function pointer to __llvm_omp_emissary_rpc +static llvm::Function *GetEmissaryExecDeclaration(CodeGenModule &CGM) { + const char *_executeName = "__llvm_omp_emissary_rpc"; + auto &M = CGM.getModule(); + llvm::Type *ArgTypes[] = {CGM.Int64Ty, + llvm::PointerType::getUnqual(CGM.Int8Ty)}; + llvm::Function *FN; + llvm::FunctionType *VarfnFuncType = + llvm::FunctionType::get(CGM.Int64Ty, ArgTypes, false); + if (!(FN = M.getFunction(_executeName))) + FN = llvm::Function::Create( + VarfnFuncType, llvm::GlobalVariable::ExternalLinkage, _executeName, &M); + assert(FN->getFunctionType() == VarfnFuncType); + return FN; +} + +// A macro to pack the llvm type ID and numbits into 4-byte key +#define _PACK_TY_BITLEN(x, y) ((uint32_t)x << 16) | ((uint32_t)y) + +// ----- External function EmitEmissaryExec called from CGExpr.cpp ----- +RValue CodeGenFunction::EmitEmissaryExec(const CallExpr *E) { + assert(getTarget().getTriple().isAMDGCN() || + getTarget().getTriple().isNVPTX()); + assert(E->getNumArgs() >= 1); // _emissary_exec always has at least one arg. + + const llvm::DataLayout &DL = CGM.getDataLayout(); + + CallArgList Args; + + // --- Insert 1st emisid arg if emiting fprintf or printf. + unsigned int AOE = 0; + if (E->getDirectCallee()->getNameAsString() == "fprintf") { + constexpr unsigned long long emisid = + ((unsigned long long)EMIS_ID_PRINT << 32) | + (unsigned long long)_fprintf_idx; + Args.add( + RValue::get(llvm::ConstantInt::get(Int64Ty, emisid)), + getContext().getIntTypeForBitwidth(/*DestWidth=*/64, /*Signed=*/false)); + AOE = 1; // Arg# offset to E->arguments to use with E->getArg(I-AOE) + } + if (E->getDirectCallee()->getNameAsString() == "printf") { + constexpr unsigned long long emisid = + ((unsigned long long)EMIS_ID_PRINT << 32) | + (unsigned long long)_printf_idx; + Args.add( + RValue::get(llvm::ConstantInt::get(Int64Ty, emisid)), + getContext().getIntTypeForBitwidth(/*DestWidth=*/64, /*Signed=*/false)); + AOE = 1; // Arg# offset to E->arguments to use with E->getArg(I-AOE) + } + + EmitCallArgs(Args, + E->getDirectCallee()->getType()->getAs(), + E->arguments(), E->getDirectCallee(), + /* ParamsToSkip = */ 0); + + // We don't know how to emit non-scalar varargs. + if (std::any_of(Args.begin() + 1, Args.end(), [&](const CallArg &A) { + return !A.getRValue(*this).isScalar(); + })) { + CGM.ErrorUnsupported(E, "non-scalar arg in GPU vargs function"); + return RValue::get(llvm::ConstantInt::get(IntTy, 0)); + } + + // NumArgs always includes emisid, but E->getNumArgs() could be 1 less if + // inserted it above. + unsigned NumArgs = (unsigned)Args.size(); + llvm::SmallVector ArgTypes; + llvm::SmallVector VarStrLengths; + llvm::Value *TotalVarStrsLength = llvm::ConstantInt::get(Int32Ty, 0); + bool hasVarStrings = false; + ArgTypes.push_back( + Int32Ty); // First field in struct will be total DataLen FIXME + ArgTypes.push_back(Int32Ty); // 2nd field in struct will be num args + // An array of 4-byte keys that describe the arg type + for (unsigned I = 0; I < NumArgs; ++I) + ArgTypes.push_back(Int32Ty); + + // Track the size of the numeric data length and string length + unsigned DataLen_CT = + (unsigned)(DL.getTypeAllocSize(Int32Ty)) * (NumArgs + 2); + unsigned AllStringsLen_CT = 0; + + // --- 1st Pass over Args to create ArgTypes and count size --- + size_t structOffset = 4 * (NumArgs + 2); + for (unsigned I = 0; I < NumArgs; I++) { + llvm::Value *Arg = Args[I].getRValue(*this).getScalarVal(); + llvm::Type *ArgType = Arg->getType(); + // Skip string processing on arg0 which may not be in E->getArg(0) + if (I != 0) { + const Expr *argX = E->getArg(I - AOE)->IgnoreParenCasts(); + auto *argXTy = argX->getType().getTypePtr(); + if (isString(argXTy)) { + if (isVarString(argX, argXTy, Arg)) { + hasVarStrings = true; + if (auto *PtrTy = dyn_cast(ArgType)) + if (PtrTy->getPointerAddressSpace()) { + Arg = Builder.CreateAddrSpaceCast(Arg, CGM.Int8PtrTy); + ArgType = Arg->getType(); + } + llvm::Value *VarStrLen = + Builder.CreateCall(GetOmpStrlenDeclaration(CGM), + {Arg, llvm::ConstantInt::get(Int32Ty, 1024)}); + VarStrLengths.push_back(VarStrLen); + TotalVarStrsLength = Builder.CreateAdd(TotalVarStrsLength, VarStrLen, + "sum_of_var_strings_length"); + ArgType = Int32Ty; + } else { + const StringLiteral *SL = getSL(argX, argXTy); + StringRef ArgString = SL->getString(); + AllStringsLen_CT += ((int)ArgString.size() + 1); + // change ArgType from char ptr to int to contain string length + ArgType = Int32Ty; + } + } // end of processing string argument + } // End of skip 1st arg + // if ArgTypeSize is >4 bytes we need to insert dummy align + // values in the struct so all stores can be aligned . + // These dummy fields must be inserted before the arg. + // + // In the pass below where the stores are generated careful + // tracking of the index into the struct is necessary. + size_t needsPadding = (structOffset % (size_t)DL.getTypeAllocSize(ArgType)); + if (needsPadding) { + DataLen_CT += (unsigned)needsPadding; + structOffset += needsPadding; + ArgTypes.push_back(Int32Ty); // could assert that needsPadding == 4 here + } + + ArgTypes.push_back(ArgType); + DataLen_CT += ((int)DL.getTypeAllocSize(ArgType)); + structOffset += (size_t)DL.getTypeAllocSize(ArgType); + } + + // --- Generate call to __llvm_omp_emissary_premalloc to get data pointer + if (hasVarStrings) + TotalVarStrsLength = Builder.CreateAdd( + TotalVarStrsLength, + llvm::ConstantInt::get(Int32Ty, AllStringsLen_CT + DataLen_CT), + "total_buffer_size"); + llvm::Value *BufferLen = + hasVarStrings + ? TotalVarStrsLength + : llvm::ConstantInt::get(Int32Ty, AllStringsLen_CT + DataLen_CT); + llvm::Value *DataStructPtr = + Builder.CreateCall(GetEmissaryAllocDeclaration(CGM), {BufferLen}); + + // --- Cast the generic return pointer to be a struct in device global memory + llvm::StructType *DataStructTy = + llvm::StructType::create(ArgTypes, "varfn_args_store"); + unsigned AS = getContext().getTargetAddressSpace(LangAS::cuda_device); + llvm::Value *BufferPtr = Builder.CreatePointerCast( + DataStructPtr, llvm::PointerType::get(DataStructTy, AS), + "varfn_args_store_casted"); + + // --- Header of struct contains length and NumArgs --- + llvm::Value *DataLenField = llvm::ConstantInt::get(Int32Ty, DataLen_CT); + llvm::Value *P = Builder.CreateStructGEP(DataStructTy, BufferPtr, 0); + Builder.CreateAlignedStore(DataLenField, P, + DL.getPrefTypeAlign(DataLenField->getType())); + llvm::Value *NumArgsField = llvm::ConstantInt::get(Int32Ty, NumArgs); + P = Builder.CreateStructGEP(DataStructTy, BufferPtr, 1); + Builder.CreateAlignedStore(NumArgsField, P, + DL.getPrefTypeAlign(NumArgsField->getType())); + + // --- 2nd Pass: create array of 4-byte keys to describe each arg + for (unsigned I = 0; I < NumArgs; I++) { + llvm::Type *ty = Args[I].getRValue(*this).getScalarVal()->getType(); + llvm::Type::TypeID argtypeid = + Args[I].getRValue(*this).getScalarVal()->getType()->getTypeID(); + + // Get type size in bits. Usually 64 or 32. + uint32_t numbits = 0; + if (I > 0 && + isString( + E->getArg(I - AOE)->IgnoreParenCasts()->getType().getTypePtr())) + // The llvm typeID for string is pointer. Since pointer numbits is 0, + // we set numbits to 1 to distinguish pointer type ID as string pointer. + numbits = 1; + else + numbits = ty->getScalarSizeInBits(); + // Create a key that combines llvm typeID and size + llvm::Value *Key = + llvm::ConstantInt::get(Int32Ty, _PACK_TY_BITLEN(argtypeid, numbits)); + P = Builder.CreateStructGEP(DataStructTy, BufferPtr, I + 2); + Builder.CreateAlignedStore(Key, P, DL.getPrefTypeAlign(Key->getType())); + } + + // --- 3rd Pass: Store data values for each arg --- + unsigned varstring_index = 0; + unsigned structIndex = 2 + NumArgs; + structOffset = 4 * structIndex; + for (unsigned I = 0; I < NumArgs; I++) { + llvm::Value *Arg; + if (I == 0) { + Arg = Args[I].getKnownRValue().getScalarVal(); + } else { + const Expr *argX = E->getArg(I - AOE)->IgnoreParenCasts(); + auto *argXTy = argX->getType().getTypePtr(); + if (isString(argXTy)) { + if (isVarString(argX, argXTy, Arg)) { + Arg = VarStrLengths[varstring_index]; + varstring_index++; + } else { + const StringLiteral *SL = getSL(argX, argXTy); + StringRef ArgString = SL->getString(); + int ArgStrLen = (int)ArgString.size() + 1; + // Change Arg from a char pointer to the integer string length + Arg = llvm::ConstantInt::get(Int32Ty, ArgStrLen); + } + } else { + Arg = Args[I].getKnownRValue().getScalarVal(); + } + } + size_t structElementSize = (size_t)DL.getTypeAllocSize(Arg->getType()); + size_t needsPadding = (structOffset % structElementSize); + if (needsPadding) { + // Skip over dummy fields in struct to align + structOffset += needsPadding; // should assert needsPadding == 4 + structIndex++; + } + P = Builder.CreateStructGEP(DataStructTy, BufferPtr, structIndex); + Builder.CreateAlignedStore(Arg, P, DL.getPrefTypeAlign(Arg->getType())); + structOffset += structElementSize; + structIndex++; + } + + // --- 4th Pass: memcpy all strings after the data values --- + // bitcast the struct in device global memory as a char buffer + Address BufferPtrByteAddr = Address( + Builder.CreatePointerCast(BufferPtr, llvm::PointerType::get(Int8Ty, AS)), + Int8Ty, CharUnits::fromQuantity(1)); + // BufferPtrByteAddr is a pointer to where we want to write the next string + BufferPtrByteAddr = Builder.CreateConstInBoundsByteGEP( + BufferPtrByteAddr, CharUnits::fromQuantity(DataLen_CT)); + varstring_index = 0; + // Skip string processing on arg0 which may not be in E->getArg(0) + for (unsigned I = 1; I < NumArgs; ++I) { + llvm::Value *Arg = Args[I].getKnownRValue().getScalarVal(); + const Expr *argX = E->getArg(I - AOE)->IgnoreParenCasts(); + auto *argXTy = argX->getType().getTypePtr(); + if (isString(argXTy)) { + if (isVarString(argX, argXTy, Arg)) { + llvm::Value *varStrLength = VarStrLengths[varstring_index]; + varstring_index++; + Address SrcAddr = Address(Arg, Int8Ty, CharUnits::fromQuantity(1)); + Builder.CreateMemCpy(BufferPtrByteAddr, SrcAddr, varStrLength); + // update BufferPtrByteAddr for next string memcpy + llvm::Value *PtrAsInt = BufferPtrByteAddr.emitRawPointer(*this); + BufferPtrByteAddr = + Address(Builder.CreateGEP(Int8Ty, PtrAsInt, + ArrayRef(varStrLength)), + Int8Ty, CharUnits::fromQuantity(1)); + } else { + const StringLiteral *SL = getSL(argX, argXTy); + StringRef ArgString = SL->getString(); + int ArgStrLen = (int)ArgString.size() + 1; + Address SrcAddr = CGM.GetAddrOfConstantStringFromLiteral(SL); + Builder.CreateMemCpy(BufferPtrByteAddr, SrcAddr, ArgStrLen); + // update BufferPtrByteAddr for next memcpy + BufferPtrByteAddr = Builder.CreateConstInBoundsByteGEP( + BufferPtrByteAddr, CharUnits::fromQuantity(ArgStrLen)); + } + } + } + // --- Generate call to __llvm_omp_emissary_rpc and return RValue + llvm::Value *EmisIds = Args[0].getRValue(*this).getScalarVal(); + return RValue::get(Builder.CreateCall( + GetEmissaryExecDeclaration(CGM), {EmisIds, DataStructPtr})); +} diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 301d5770cf78f..866a0e6cad209 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -6596,6 +6596,21 @@ RValue CodeGenFunction::EmitCall(QualType CalleeType, StaticOperator = true; } + // Emit __llvm_omp_emissary_rpc for stubs of emissary APIs. + if ((CGM.getTriple().isAMDGCN() || CGM.getTriple().isNVPTX()) && FnType && + dyn_cast(FnType) && + dyn_cast(FnType)->isVariadic()) { + // This is a variadic function in a device compile + // if (emissary_exec || (openmp && (fprintf || printf)) + if ((E->getDirectCallee()->getNameAsString() == "_emissary_exec") || + // FIXME: do not call for fprintf or printf if device libc is active + (CGM.getLangOpts().OpenMP && + ((E->getDirectCallee()->getNameAsString() == "fprintf") || + (E->getDirectCallee()->getNameAsString() == "printf")))) { + return EmitEmissaryExec(E); + } + } + auto Arguments = E->arguments(); if (StaticOperator) { // If we're calling a static operator, we need to emit the object argument diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 714192db1b15c..334951251c634 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -990,6 +990,10 @@ Value *ScalarExprEmitter::EmitConversionToBool(Value *Src, QualType SrcType) { if (const MemberPointerType *MPT = dyn_cast(SrcType)) return CGF.CGM.getCXXABI().EmitMemberPointerIsNotNull(CGF, Src, MPT); + // The conversion is a NOP, and will be done when CodeGening the builtin. + if (SrcType == CGF.getContext().AMDGPUFeaturePredicateTy) + return Src; + assert((SrcType->isIntegerType() || isa(Src->getType())) && "Unknown scalar type to convert"); diff --git a/clang/lib/CodeGen/CGGPUBuiltin.cpp b/clang/lib/CodeGen/CGGPUBuiltin.cpp index c133b5f3c0293..5bbf22f39c785 100644 --- a/clang/lib/CodeGen/CGGPUBuiltin.cpp +++ b/clang/lib/CodeGen/CGGPUBuiltin.cpp @@ -149,13 +149,16 @@ RValue EmitDevicePrintfCallExpr(const CallExpr *E, CodeGenFunction *CGF, } } // namespace -RValue CodeGenFunction::EmitNVPTXDevicePrintfCallExpr(const CallExpr *E) { +RValue CodeGenFunction::EmitNVPTXDevicePrintfCallExpr(const CallExpr *E, + ReturnValueSlot ReturnValu) { assert(getTarget().getTriple().isNVPTX()); return EmitDevicePrintfCallExpr( E, this, GetVprintfDeclaration(CGM.getModule()), false); } -RValue CodeGenFunction::EmitAMDGPUDevicePrintfCallExpr(const CallExpr *E) { +RValue +CodeGenFunction::EmitAMDGPUDevicePrintfCallExpr(const CallExpr *E, + ReturnValueSlot ReturnValue) { assert(getTarget().getTriple().isAMDGCN() || (getTarget().getTriple().isSPIRV() && getTarget().getTriple().getVendor() == llvm::Triple::AMD)); diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index 66fea920812c2..a044168205d67 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -46,6 +46,7 @@ using namespace clang; using namespace CodeGen; using namespace llvm::omp; +using namespace llvm::omp::xteam_red; namespace { /// Base class for handling code generation inside OpenMP regions. @@ -551,6 +552,26 @@ enum OpenMPSchedType { OMP_sch_modifier_nonmonotonic = (1 << 30), }; +/// Hint enum values for atomic and critical constructs (these enumerators are +/// taken from the enum omp_sync_hint_t in omp.h). +enum OpenMPSyncHintExpr { + OMP_sync_hint_none = 0, + OMP_lock_hint_none = OMP_sync_hint_none, + OMP_sync_hint_uncontended = 1, + OMP_lock_hint_uncontended = OMP_sync_hint_uncontended, + OMP_sync_hint_contended = (1 << 1), + OMP_lock_hint_contended = OMP_sync_hint_contended, + OMP_sync_hint_nonspeculative = (1 << 2), + OMP_lock_hint_nonspeculative = OMP_sync_hint_nonspeculative, + OMP_sync_hint_speculative = (1 << 3), + OMP_lock_hint_speculative = OMP_sync_hint_speculative, + kmp_lock_hint_hle = (1 << 16), + kmp_lock_hint_rtm = (1 << 17), + kmp_lock_hint_adaptive = (1 << 18), + AMD_fast_fp_atomics = (1 << 19), + AMD_safe_fp_atomics = (1 << 20) +}; + /// A basic class for pre|post-action for advanced codegen sequence for OpenMP /// region. class CleanupTy final : public EHScopeStack::Cleanup { @@ -1049,7 +1070,8 @@ CGOpenMPRuntime::CGOpenMPRuntime(CodeGenModule &CGM) // The user forces the compiler to behave as if omp requires // unified_shared_memory was given. - if (CGM.getLangOpts().OpenMPForceUSM) { + if (CGM.getLangOpts().OpenMPForceUSM || + CGM.getLangOpts().OpenMPTargetMultiDevice) { HasRequiresUnifiedSharedMemory = true; OMPBuilder.Config.setHasRequiresUnifiedSharedMemory(true); } @@ -1211,7 +1233,8 @@ struct PushAndPopStackRAII { static llvm::Function *emitParallelOrTeamsOutlinedFunction( CodeGenModule &CGM, const OMPExecutableDirective &D, const CapturedStmt *CS, const VarDecl *ThreadIDVar, OpenMPDirectiveKind InnermostKind, - const StringRef OutlinedHelperName, const RegionCodeGenTy &CodeGen) { + const StringRef OutlinedHelperName, const RegionCodeGenTy &CodeGen, + bool EmittingOutlinedTeams) { assert(ThreadIDVar->getType()->isPointerType() && "thread id variable must be of type kmp_int32 *"); CodeGenFunction CGF(CGM, true); @@ -1242,7 +1265,8 @@ static llvm::Function *emitParallelOrTeamsOutlinedFunction( CGOpenMPOutlinedRegionInfo CGInfo(*CS, ThreadIDVar, CodeGen, InnermostKind, HasCancel, OutlinedHelperName); CodeGenFunction::CGCapturedStmtRAII CapInfoRAII(CGF, &CGInfo); - return CGF.GenerateOpenMPCapturedStmtFunction(*CS, D); + return CGF.GenerateOpenMPCapturedStmtFunction(*CS, D, + EmittingOutlinedTeams, false); } std::string CGOpenMPRuntime::getOutlinedHelperName(StringRef Name) const { @@ -1266,7 +1290,7 @@ llvm::Function *CGOpenMPRuntime::emitParallelOutlinedFunction( const CapturedStmt *CS = D.getCapturedStmt(OMPD_parallel); return emitParallelOrTeamsOutlinedFunction( CGM, D, CS, ThreadIDVar, InnermostKind, getOutlinedHelperName(CGF), - CodeGen); + CodeGen, /*EmittingOutlinedTeams*/ false); } llvm::Function *CGOpenMPRuntime::emitTeamsOutlinedFunction( @@ -1276,7 +1300,7 @@ llvm::Function *CGOpenMPRuntime::emitTeamsOutlinedFunction( const CapturedStmt *CS = D.getCapturedStmt(OMPD_teams); return emitParallelOrTeamsOutlinedFunction( CGM, D, CS, ThreadIDVar, InnermostKind, getOutlinedHelperName(CGF), - CodeGen); + CodeGen, /*EmittingOutlinedTeams*/ true); } llvm::Function *CGOpenMPRuntime::emitTaskOutlinedFunction( @@ -2581,19 +2605,38 @@ static void emitForStaticInitCall( Schedule == OMP_dist_sch_static_chunked) && "expected static chunked schedule"); } - llvm::Value *Args[] = { - UpdateLocation, - ThreadId, - CGF.Builder.getInt32(addMonoNonMonoModifier(CGF.CGM, Schedule, M1, - M2)), // Schedule type - Values.IL.emitRawPointer(CGF), // &isLastIter - Values.LB.emitRawPointer(CGF), // &LB - Values.UB.emitRawPointer(CGF), // &UB - Values.ST.emitRawPointer(CGF), // &Stride - CGF.Builder.getIntN(Values.IVSize, 1), // Incr - Chunk // Chunk - }; - CGF.EmitRuntimeCall(ForStaticInitFunction, Args); + + if (Values.IsMultiDevice) { + llvm::Value *Args[] = { + UpdateLocation, + ThreadId, + CGF.Builder.getInt32(addMonoNonMonoModifier(CGF.CGM, Schedule, M1, + M2)), // Schedule type + Values.IL.emitRawPointer(CGF), // &isLastIter + Values.MultiDeviceLB.emitRawPointer(CGF), // &MultiDeviceLB + Values.MultiDeviceUB.emitRawPointer(CGF), // &MultiDeviceUB + Values.LB.emitRawPointer(CGF), // &LB + Values.UB.emitRawPointer(CGF), // &UB + Values.ST.emitRawPointer(CGF), // &Stride + CGF.Builder.getIntN(Values.IVSize, 1), // Incr + Chunk // Chunk + }; + CGF.EmitRuntimeCall(ForStaticInitFunction, Args); + } else { + llvm::Value *Args[] = { + UpdateLocation, + ThreadId, + CGF.Builder.getInt32(addMonoNonMonoModifier(CGF.CGM, Schedule, M1, + M2)), // Schedule type + Values.IL.emitRawPointer(CGF), // &isLastIter + Values.LB.emitRawPointer(CGF), // &LB + Values.UB.emitRawPointer(CGF), // &UB + Values.ST.emitRawPointer(CGF), // &Stride + CGF.Builder.getIntN(Values.IVSize, 1), // Incr + Chunk // Chunk + }; + CGF.EmitRuntimeCall(ForStaticInitFunction, Args); + } } void CGOpenMPRuntime::emitForStaticInit(CodeGenFunction &CGF, @@ -2621,7 +2664,7 @@ void CGOpenMPRuntime::emitForStaticInit(CodeGenFunction &CGF, void CGOpenMPRuntime::emitDistributeStaticInit( CodeGenFunction &CGF, SourceLocation Loc, OpenMPDistScheduleClauseKind SchedKind, - const CGOpenMPRuntime::StaticRTInput &Values) { + const CGOpenMPRuntime::StaticRTInput &Values, bool IsMultiDeviceKernel) { OpenMPSchedType ScheduleNum = getRuntimeSchedule(SchedKind, Values.Chunk != nullptr); llvm::Value *UpdatedLocation = @@ -2630,9 +2673,13 @@ void CGOpenMPRuntime::emitDistributeStaticInit( llvm::FunctionCallee StaticInitFunction; bool isGPUDistribute = CGM.getLangOpts().OpenMPIsTargetDevice && CGM.getTriple().isGPU(); - StaticInitFunction = OMPBuilder.createForStaticInitFunction( - Values.IVSize, Values.IVSigned, isGPUDistribute); - + if (IsMultiDeviceKernel && isGPUDistribute) { + StaticInitFunction = OMPBuilder.createMDDistributeForStaticInitFunction( + Values.IVSize, Values.IVSigned); + } else { + StaticInitFunction = OMPBuilder.createForStaticInitFunction( + Values.IVSize, Values.IVSigned, isGPUDistribute); + } emitForStaticInitCall(CGF, UpdatedLocation, ThreadId, StaticInitFunction, ScheduleNum, OMPC_SCHEDULE_MODIFIER_unknown, OMPC_SCHEDULE_MODIFIER_unknown, Values); @@ -6223,7 +6270,9 @@ void CGOpenMPRuntime::emitTargetOutlinedFunctionHelper( CGOpenMPTargetRegionInfo CGInfo(CS, CodeGen, EntryFnName); CodeGenFunction::CGCapturedStmtRAII CapInfoRAII(CGF, &CGInfo); - return CGF.GenerateOpenMPCapturedStmtFunction(CS, D); + return CGF.GenerateOpenMPCapturedStmtFunction( + CS, D, + /*CanHaveMultiDeviceArgs*/ true, /*IsTopKernel*/ true); }; cantFail(OMPBuilder.emitTargetRegionFunction( @@ -9964,6 +10013,33 @@ llvm::Value *CGOpenMPRuntime::emitTargetNumIterationsCall( return llvm::ConstantInt::get(CGF.Int64Ty, 0); } +void addXTeamReductionComponentHelper( + CodeGenFunction &CGF, MappableExprsHandler::MapCombinedInfoTy &CombinedInfo, + llvm::Value *InfoComponent) { + MappableExprsHandler::MapCombinedInfoTy CurInfo; + CurInfo.Exprs.push_back(nullptr); + CurInfo.BasePointers.push_back(InfoComponent); + CurInfo.Pointers.push_back(InfoComponent); + CurInfo.Sizes.push_back(CGF.Builder.CreateIntCast( + CGF.getTypeSize(CGF.getContext().VoidPtrTy), CGF.Int64Ty, + /*isSigned=*/true)); + + // Copy to the device as an argument. No need to retrieve it. + CurInfo.Types.push_back(OpenMPOffloadMappingFlags::OMP_MAP_LITERAL | + OpenMPOffloadMappingFlags::OMP_MAP_TARGET_PARAM); + CurInfo.Mappers.push_back(nullptr); + + assert(CurInfo.BasePointers.size() == CurInfo.Pointers.size() && + CurInfo.BasePointers.size() == CurInfo.Sizes.size() && + CurInfo.BasePointers.size() == CurInfo.Types.size() && + CurInfo.BasePointers.size() == CurInfo.Mappers.size() && + "Inconsistent map information sizes!"); + + // We need to append the results of this capture to what we already + // have. + CombinedInfo.append(CurInfo); +} + static void emitTargetCallFallback(CGOpenMPRuntime *OMPRuntime, llvm::Function *OutlinedFn, const OMPExecutableDirective &D, @@ -9975,7 +10051,8 @@ emitTargetCallFallback(CGOpenMPRuntime *OMPRuntime, llvm::Function *OutlinedFn, } else { if (RequiresOuterTask) { CapturedVars.clear(); - CGF.GenerateOpenMPCapturedVars(CS, CapturedVars); + CGF.GenerateOpenMPCapturedVars(CS, CapturedVars, + CGF.CGM.getOptKernelKey(D)); } OMPRuntime->emitOutlinedFunctionCall(CGF, D.getBeginLoc(), OutlinedFn, CapturedVars); @@ -10016,16 +10093,54 @@ static llvm::Value *emitDynCGGroupMem(const OMPExecutableDirective &D, static void genMapInfoForCaptures( MappableExprsHandler &MEHandler, CodeGenFunction &CGF, const CapturedStmt &CS, llvm::SmallVectorImpl &CapturedVars, + llvm::SmallVectorImpl &MultiTargetVars, llvm::OpenMPIRBuilder &OMPBuilder, llvm::DenseSet> &MappedVarSet, + uint32_t &CapturedCount, MappableExprsHandler::MapCombinedInfoTy &CombinedInfo) { - llvm::DenseMap LambdaPointers; + + // If a for statement is present and the compiler flag for multi-device + // targets is enabled then it means we have 2 variables at the start which + // represent the lower and upper bounds of the loop: + // TODO: add compiler flag condition + for (auto *MTV = MultiTargetVars.begin(); MTV != MultiTargetVars.end(); + ++MTV) { + // This should always be null because the any used variable (if one exists) + // will be included when capturing the actual variables (not the + // multi-target ones). + MappedVarSet.insert(nullptr); + + MappableExprsHandler::MapCombinedInfoTy CurInfo; + CurInfo.Exprs.push_back(nullptr); + CurInfo.BasePointers.push_back(*MTV); + CurInfo.Pointers.push_back(*MTV); + CurInfo.Sizes.push_back(llvm::ConstantInt::get(CGF.Int64Ty, 4)); + + // Copy to the device as an argument. No need to retrieve it. + CurInfo.Types.push_back(OpenMPOffloadMappingFlags::OMP_MAP_LITERAL | + OpenMPOffloadMappingFlags::OMP_MAP_TARGET_PARAM | + OpenMPOffloadMappingFlags::OMP_MAP_IMPLICIT); + CurInfo.Mappers.push_back(nullptr); + + assert(CurInfo.BasePointers.size() == CurInfo.Pointers.size() && + CurInfo.BasePointers.size() == CurInfo.Sizes.size() && + CurInfo.BasePointers.size() == CurInfo.Types.size() && + CurInfo.BasePointers.size() == CurInfo.Mappers.size() && + "Inconsistent map information sizes!"); + + // We need to append the results of this capture to what we already + // have. + CombinedInfo.append(CurInfo); + } + auto RI = CS.getCapturedRecordDecl()->field_begin(); auto *CV = CapturedVars.begin(); + CapturedCount = 0; for (CapturedStmt::const_capture_iterator CI = CS.capture_begin(), CE = CS.capture_end(); CI != CE; ++CI, ++RI, ++CV) { + ++CapturedCount; MappableExprsHandler::MapCombinedInfoTy CurInfo; // VLA sizes are passed to the outlined region by copy and do not have map @@ -10090,6 +10205,7 @@ genMapInfo(MappableExprsHandler &MEHandler, CodeGenFunction &CGF, llvm::DenseSet>()) { CodeGenModule &CGM = CGF.CGM; + // Map any list items in a map clause that were not captures because they // weren't referenced within the construct. MEHandler.generateAllInfo(CombinedInfo, OMPBuilder, SkippedVarSet); @@ -10108,14 +10224,16 @@ genMapInfo(MappableExprsHandler &MEHandler, CodeGenFunction &CGF, static void genMapInfo(const OMPExecutableDirective &D, CodeGenFunction &CGF, const CapturedStmt &CS, llvm::SmallVectorImpl &CapturedVars, + llvm::SmallVectorImpl &MultiTargetVars, llvm::OpenMPIRBuilder &OMPBuilder, + uint32_t &CapturedCount, MappableExprsHandler::MapCombinedInfoTy &CombinedInfo) { // Get mappable expression information. MappableExprsHandler MEHandler(D, CGF); llvm::DenseSet> MappedVarSet; - genMapInfoForCaptures(MEHandler, CGF, CS, CapturedVars, OMPBuilder, - MappedVarSet, CombinedInfo); + genMapInfoForCaptures(MEHandler, CGF, CS, CapturedVars, MultiTargetVars, + OMPBuilder, MappedVarSet, CapturedCount, CombinedInfo); genMapInfo(MEHandler, CGF, CombinedInfo, OMPBuilder, MappedVarSet); } @@ -10138,8 +10256,9 @@ emitClauseForBareTargetDirective(CodeGenFunction &CGF, static void emitTargetCallKernelLaunch( CGOpenMPRuntime *OMPRuntime, llvm::Function *OutlinedFn, const OMPExecutableDirective &D, - llvm::SmallVectorImpl &CapturedVars, bool RequiresOuterTask, - const CapturedStmt &CS, bool OffloadingMandatory, + llvm::SmallVectorImpl &CapturedVars, + llvm::SmallVectorImpl &MultiTargetVars, + bool RequiresOuterTask, const CapturedStmt &CS, bool OffloadingMandatory, llvm::PointerIntPair Device, llvm::Value *OutlinedFnID, CodeGenFunction::OMPTargetDataInfo &InputInfo, llvm::Value *&MapTypesArray, llvm::Value *&MapNamesArray, @@ -10151,9 +10270,300 @@ static void emitTargetCallKernelLaunch( // Fill up the arrays with all the captured variables. MappableExprsHandler::MapCombinedInfoTy CombinedInfo; - CGOpenMPRuntime::TargetDataInfo Info; - genMapInfo(D, CGF, CS, CapturedVars, OMPBuilder, CombinedInfo); + uint32_t CapturedCount; + genMapInfo(D, CGF, CS, CapturedVars, MultiTargetVars, OMPBuilder, + CapturedCount, CombinedInfo); + + // Array to hold to allocated XTeam reduction variables: + llvm::SmallVector ReductionVars; + + // TODO Use device id from device clause, if any. + llvm::CallInst *DevIdVal = nullptr; + llvm::CallInst *TeamProcsInst = nullptr; + llvm::CallInst *InitialDevInst = nullptr; + // If doing Xteam reduction, add the corresponding vars to Info + const ForStmt *FStmt = CGF.CGM.getSingleForStmt(CGF.CGM.getOptKernelKey(D)); + bool HasXTeamReduction = FStmt && CGF.CGM.isXteamRedKernel(FStmt); + if (HasXTeamReduction) { + CodeGenModule::XteamRedVarMap &XteamRVM = CGF.CGM.getXteamRedVarMap(FStmt); + auto &XteamOrdVars = CGF.CGM.getXteamOrderedRedVar(FStmt); + + // Note Regarding the ExpectedNumArgs: + // 1. The Xteam Reduction kernels require two helper variables - `team_vals` + // array and `teams_done_ptr`. + // 2. The Xteam Scan Reduction kernels require a third helper variable - + // `scan_storage` array. + // a. The segmented scan variant(the default) requires a fourth helper + // variable - `segmented_vals` + size_t ExpectedNumArgs = + CGF.CGM.isXteamScanKernel() + ? (CGF.CGM.isXteamSegmentedScanKernel() ? 4 : 3) + : 2; + assert((CapturedVars.size() == + CapturedCount + ExpectedNumArgs * XteamRVM.size()) && + "Unexpected number of captured vars"); + + // Needed for processing the xteam reduction var pairs: + llvm::Value *Int32Zero = llvm::ConstantInt::get(CGF.Int32Ty, 0); + + llvm::Value *XteamRedNumTeamsFromClauseVal = nullptr; + llvm::Value *XteamRedNumTeamsFromOccupancy = nullptr; + bool IsXteamRedFast = CGF.CGM.isXteamRedFast(FStmt); + // We don't need to allocate/initialize metadata in the fast version. + // TODO: This will not work for multi-target if we need to allocate + // data for each used device. Ensure conditions guard against that. + if (!IsXteamRedFast) { + // TODO Use device id from device clause, if any. + DevIdVal = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGF.CGM.getModule(), + OMPRTL_omp_get_default_device), + "default_dev"); + + // If num_teams clause is found, compute NumTeamsFromClause + int64_t XteamRedNumTeamsFromClause = + CGF.CGM.getXteamRedNumTeamsFromClause(D); + if (XteamRedNumTeamsFromClause > 0) { + XteamRedNumTeamsFromClauseVal = + llvm::ConstantInt::get(CGF.Int64Ty, XteamRedNumTeamsFromClause); + } + if (XteamRedNumTeamsFromClauseVal == nullptr) { + // team_procs = ompx_get_team_procs(devid) + TeamProcsInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGF.CGM.getModule(), + OMPRTL_ompx_get_team_procs), + DevIdVal, "team_procs"); + + // Given the currently determined blocksize, compute the scaling + // factor for number of teams in terms of the number of CUs. This + // computation must stay in sync with the runtime. + uint32_t CUMultiplier = llvm::omp::xteam_red::getXteamRedCUMultiplier( + CGF.CGM.getXteamRedBlockSize(D)); + + llvm::Value *Int64CUMultiplier = + llvm::ConstantInt::get(CGF.Int64Ty, CUMultiplier); + // NumTeamsFromOccupancy = CUMultiplier * NumCUs + XteamRedNumTeamsFromOccupancy = CGF.Builder.CreateMul( + Int64CUMultiplier, + CGF.Builder.CreateIntCast(TeamProcsInst, CGF.Int64Ty, false)); + } + + // initial_devid = omp_get_initial_device() + InitialDevInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGF.CGM.getModule(), + OMPRTL_omp_get_initial_device), + "initial_devid"); + } + + // Allocate reduction variables. The loop goes over these variables in + // pairs. Each xteam reduction variable leads to the use of 2 extra + // variables in the generated code. + // TODO: change the magic number 2 into a variable. + // Always generate Xteam metadata in the same order as user-specified + // reduction variables. + size_t ArgPos = 0; + size_t RedVarCount = 0; + if (CGF.CGM.isXteamScanKernel() && !CGF.CGM.isXteamScanPhaseOne) { + // For the Phase 2 of the Xteam Scan codegen, fresh memory allocation for + // reduction helper data structures is not needed. The helpers generated + // during the Phase 1 will be re-used here. + assert(CGF.CGM.ReductionVars.size() == ExpectedNumArgs && + "Insufficient number of helper variables for Xteam Scan reduction " + "code-generation"); + addXTeamReductionComponentHelper( + CGF, CombinedInfo, CGF.CGM.ReductionVars[0]); // team_vals + addXTeamReductionComponentHelper( + CGF, CombinedInfo, CGF.CGM.ReductionVars[1]); // teams_done_ptr + addXTeamReductionComponentHelper( + CGF, CombinedInfo, CGF.CGM.ReductionVars[2]); // scan_storage + if (CGF.CGM.isXteamSegmentedScanKernel()) + addXTeamReductionComponentHelper( + CGF, CombinedInfo, CGF.CGM.ReductionVars[3]); // segment_vals + } else { + for (; CapturedCount + ArgPos < CapturedVars.size();) { + // Process the pair of captured variables: + llvm::Value *DTeamValsInst = nullptr; + llvm::Value *DScanStorageInst = nullptr; + llvm::Value *DSegmentValsInst = nullptr; + + assert(CapturedCount + ArgPos < CapturedVars.size() && + "Xteam reduction argument position out of bounds"); + assert(RedVarCount < XteamOrdVars.size() && + "Reduction variable count out of bounds"); + const VarDecl *UserRedVar = XteamOrdVars[RedVarCount]; + assert(XteamRVM.find(UserRedVar) != XteamRVM.end() && + "Reduction variable not found in metadata"); + auto RedVarQualType = + XteamRVM.find(UserRedVar)->second.RedVarExpr->getType(); + llvm::Type *RedVarType = CGF.ConvertTypeForMem(RedVarQualType); + + const ASTContext &Context = CGM.getContext(); + if (IsXteamRedFast) { + // Placeholder for d_team_vals initialized to nullptr + DTeamValsInst = + CGF.Builder.CreateAlloca(RedVarType, nullptr, "d_team_vals"); + Address DTeamValsAddr(DTeamValsInst, RedVarType, + Context.getTypeAlignInChars(RedVarQualType)); + llvm::Value *NullPtrDTeamVals = llvm::ConstantPointerNull::get( + llvm::PointerType::get(CGF.getLLVMContext(), /*AddressSpace=*/0)); + CGF.Builder.CreateStore(NullPtrDTeamVals, DTeamValsAddr); + } else { + // dteam_vals = omp_target_alloc(sizeof(red-type) * num_teams, devid) + llvm::Value *RedVarTySz = llvm::ConstantInt::get( + CGF.Int64Ty, + CGF.CGM.getDataLayout().getTypeSizeInBits(RedVarType) / 8); + assert((XteamRedNumTeamsFromClauseVal != nullptr || + XteamRedNumTeamsFromOccupancy != nullptr) && + "Number of teams cannot be null"); + llvm::Value *DTeamValsSz = CGF.Builder.CreateMul( + RedVarTySz, + XteamRedNumTeamsFromClauseVal ? XteamRedNumTeamsFromClauseVal + : XteamRedNumTeamsFromOccupancy, + "d_team_vals_sz"); + llvm::Value *TgtAllocArgs[] = {DTeamValsSz, DevIdVal}; + DTeamValsInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGF.CGM.getModule(), + OMPRTL_omp_target_alloc), + TgtAllocArgs, "d_team_vals"); + + if (CGF.CGM.isXteamScanKernel()) { + // d_scan_storage = omp_target_alloc(sizeof(red-type) * (2*num_teams*num_threads + 1), devid) + llvm::Value *TotalNumThreads = CGF.Builder.CreateMul( + XteamRedNumTeamsFromClauseVal ? XteamRedNumTeamsFromClauseVal + : XteamRedNumTeamsFromOccupancy, + CGF.Builder.CreateIntCast( + CGF.Builder.getInt32(CGF.CGM.getXteamRedBlockSize(D)), + CGF.Int64Ty, false), + "total_num_threads"); + llvm::Value *StorageSize = CGF.Builder.CreateAdd( + CGF.Builder.CreateMul(TotalNumThreads, + llvm::ConstantInt::get(CGF.Int64Ty, 2)), + llvm::ConstantInt::get(CGF.Int64Ty, 1), "storage_size"); + llvm::Value *DScanStorageSz = CGF.Builder.CreateMul( + RedVarTySz, StorageSize, "d_scan_storage_sz"); + llvm::Value *TgtAllocArgsScan[] = {DScanStorageSz, DevIdVal}; + DScanStorageInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGF.CGM.getModule(), + OMPRTL_omp_target_alloc), + TgtAllocArgsScan, "d_scan_storage"); + if (CGF.CGM.isXteamSegmentedScanKernel()) { + // Emit the lower and upper bounds + const auto *LBDecl = cast( + cast( + cast(D).getLowerBoundVariable()) + ->getDecl()); + CGF.EmitVarDecl(*LBDecl); + + const auto *UBDecl = cast( + cast( + cast(D).getUpperBoundVariable()) + ->getDecl()); + CGF.EmitVarDecl(*UBDecl); + const auto UBLValue = CGF.EmitLValue(cast( + cast(D).getUpperBoundVariable())); + const auto LBLValue = CGF.EmitLValue(cast( + cast(D).getLowerBoundVariable())); + // Emit SegmentValsSize = UBLValue - LBLValue + 1 + llvm::Value *SegmentValsSize = CGF.Builder.CreateAdd( + CGF.Builder.CreateSub( + CGF.Builder.CreateLoad(UBLValue.getAddress()), + CGF.Builder.CreateLoad(LBLValue.getAddress())), + llvm::ConstantInt::get(CGF.Int32Ty, 1), "segment_vals_size"); + + llvm::Value *DSegmentValsSz = CGF.Builder.CreateMul( + RedVarTySz, + CGF.Builder.CreateIntCast(SegmentValsSize, CGF.Int64Ty, + /*isSigned*/ false), + "d_segment_vals_sz"); + llvm::Value *TgtAllocArgsScan[] = {DSegmentValsSz, DevIdVal}; + DSegmentValsInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGF.CGM.getModule(), OMPRTL_omp_target_alloc), + TgtAllocArgsScan, "d_segment_vals"); + } + } + } + CGF.CGM.ReductionVars.push_back(DTeamValsInst); + addXTeamReductionComponentHelper(CGF, CombinedInfo, DTeamValsInst); + + // Advance to the next reduction variable in the pair: + ++ArgPos; + + llvm::Value *DTeamsDonePtrInst = nullptr; + if (IsXteamRedFast) { + // Placeholder for d_teams_done_ptr initialized to nullptr + DTeamsDonePtrInst = CGF.Builder.CreateAlloca(CGF.Int32Ty, nullptr, + "d_teams_done_ptr"); + Address DTeamsDoneAddr( + DTeamsDonePtrInst, CGF.Int32Ty, + Context.getTypeAlignInChars(Context.UnsignedIntTy)); + llvm::Value *NullPtrDTeamsDone = llvm::ConstantPointerNull::get( + llvm::PointerType::get(CGF.getLLVMContext(), /*AddressSpace=*/0)); + CGF.Builder.CreateStore(NullPtrDTeamsDone, DTeamsDoneAddr); + } else { + // uint32 teams_done = 0 + Address TeamsDoneAddr( + CapturedVars[CapturedCount + ArgPos], CGF.Int32Ty, + CGF.getContext().getTypeAlignInChars(CGF.getContext().IntTy)); + CGF.Builder.CreateStore(Int32Zero, TeamsDoneAddr); + + // d_teams_done_ptr = omp_target_alloc(4, devid) + llvm::Value *IntTySz = llvm::ConstantInt::get(CGF.Int64Ty, 4); + llvm::Value *DTeamsDonePtrArgs[] = {IntTySz, DevIdVal}; + DTeamsDonePtrInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGF.CGM.getModule(), + OMPRTL_omp_target_alloc), + DTeamsDonePtrArgs, "d_teams_done_ptr"); + + // omp_target_memcpy(d_teams_done_ptr, &teams_done, 4 /*sizeof(uint32_t) + // */, 0 /* offset */, 0 /* offset */, devid, initial_devid) + llvm::Value *DTeamsDoneMemcpyArgs[] = { + DTeamsDonePtrInst, + TeamsDoneAddr.emitRawPointer(CGF), + /*sizeof(uint32_t)=*/llvm::ConstantInt::get(CGF.Int64Ty, 4), + /*dst_offset=*/llvm::ConstantInt::get(CGF.Int64Ty, 0), + /*src_offset=*/llvm::ConstantInt::get(CGF.Int64Ty, 0), + DevIdVal, + InitialDevInst}; + CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGF.CGM.getModule(), + OMPRTL_omp_target_memcpy), + DTeamsDoneMemcpyArgs); + } + CGF.CGM.ReductionVars.push_back(DTeamsDonePtrInst); + addXTeamReductionComponentHelper(CGF, CombinedInfo, DTeamsDonePtrInst); + + if (CGF.CGM.isXteamScanKernel()) { + // Advance to the next reduction variable in the pair: + ++ArgPos; + CGF.CGM.ReductionVars.push_back(DScanStorageInst); + addXTeamReductionComponentHelper(CGF, CombinedInfo, DScanStorageInst); + if (CGF.CGM.isXteamSegmentedScanKernel()) { + ++ArgPos; + CGF.CGM.ReductionVars.push_back(DSegmentValsInst); + addXTeamReductionComponentHelper(CGF, CombinedInfo, + DSegmentValsInst); + } + } + // Advance to the next reduction variable in the pair: + ++ArgPos; + + ++RedVarCount; + } + } + // Process debug info. + if (CGF.CGM.getCodeGenOpts().getDebugInfo() != + llvm::codegenoptions::NoDebugInfo) { + auto FillInfoMap = [&](MappableExprsHandler::MappingExprInfo &MapExpr) { + return emitMappingInformation(CGF, OMPBuilder, MapExpr); + }; + CombinedInfo.Names.resize(CombinedInfo.Exprs.size()); + llvm::transform(CombinedInfo.Exprs, CombinedInfo.Names.begin(), + FillInfoMap); + } + } + + CGOpenMPRuntime::TargetDataInfo Info; emitOffloadingArraysAndArgs(CGF, CombinedInfo, Info, OMPBuilder, /*IsNonContiguous=*/true, /*ForEndCall=*/false); @@ -10176,6 +10586,9 @@ static void emitTargetCallKernelLaunch( bool IsReverseOffloading = Device.getInt() == OMPC_DEVICE_ancestor; if (IsReverseOffloading) { + assert( + !CGF.CGM.getLangOpts().OpenMPTargetMultiDevice && + "Cannot enable multi-device targets when doing reverse offloading"); // Reverse offloading is not supported, so just execute on the host. // FIXME: This fallback solution is incorrect since it ignores the // OMP_TARGET_OFFLOAD environment variable. Instead it would be better to @@ -10240,10 +10653,27 @@ static void emitTargetCallKernelLaunch( CGF.Builder.restoreIP(AfterIP); }; - if (RequiresOuterTask) + if (RequiresOuterTask) { + assert(!CGM.getLangOpts().OpenMPTargetMultiDevice && + "Cannot yet enable multi-device targets for situations in which an " + "outer task is required"); CGF.EmitOMPTargetTaskBasedDirective(D, ThenGen, InputInfo); - else + } else OMPRuntime->emitInlinedDirective(CGF, D.getDirectiveKind(), ThenGen); + + if (HasXTeamReduction) { + if (!CGF.CGM.isXteamRedFast(FStmt) && + !(CGF.CGM.isXteamScanKernel() && CGF.CGM.isXteamScanPhaseOne)) { + // Deallocate XTeam reduction variables: + for (uint32_t I = 0; I < CGF.CGM.ReductionVars.size(); ++I) { + llvm::Value *FreeArgs[] = {CGF.CGM.ReductionVars[I], DevIdVal}; + CGF.EmitRuntimeCall(OMPBuilder.getOrCreateRuntimeFunction( + CGF.CGM.getModule(), OMPRTL_omp_target_free), + FreeArgs); + } + CGF.CGM.ReductionVars.clear(); + } + } } static void @@ -10292,10 +10722,12 @@ void CGOpenMPRuntime::emitTargetCall( needsTaskBasedThreadLimit(D.getDirectiveKind()) && D.hasClausesOfKind()); llvm::SmallVector CapturedVars; + llvm::SmallVector MultiTargetVars; const CapturedStmt &CS = *D.getCapturedStmt(OMPD_target); - auto &&ArgsCodegen = [&CS, &CapturedVars](CodeGenFunction &CGF, - PrePostActionTy &) { - CGF.GenerateOpenMPCapturedVars(CS, CapturedVars); + auto &&ArgsCodegen = [&CS, &D, &CapturedVars, &MultiTargetVars]( + CodeGenFunction &CGF, PrePostActionTy &) { + CGF.GenerateOpenMPCapturedVarsDevice(CS, CapturedVars, MultiTargetVars, + CGF.CGM.getOptKernelKey(D)); }; emitInlinedDirective(CGF, OMPD_unknown, ArgsCodegen); @@ -10303,15 +10735,15 @@ void CGOpenMPRuntime::emitTargetCall( llvm::Value *MapTypesArray = nullptr; llvm::Value *MapNamesArray = nullptr; - auto &&TargetThenGen = [this, OutlinedFn, &D, &CapturedVars, + auto &&TargetThenGen = [this, OutlinedFn, &D, &CapturedVars, &MultiTargetVars, RequiresOuterTask, &CS, OffloadingMandatory, Device, OutlinedFnID, &InputInfo, &MapTypesArray, &MapNamesArray, SizeEmitter](CodeGenFunction &CGF, PrePostActionTy &) { - emitTargetCallKernelLaunch(this, OutlinedFn, D, CapturedVars, - RequiresOuterTask, CS, OffloadingMandatory, - Device, OutlinedFnID, InputInfo, MapTypesArray, - MapNamesArray, SizeEmitter, CGF, CGM); + emitTargetCallKernelLaunch( + this, OutlinedFn, D, CapturedVars, MultiTargetVars, RequiresOuterTask, + CS, OffloadingMandatory, Device, OutlinedFnID, InputInfo, MapTypesArray, + MapNamesArray, SizeEmitter, CGF, CGM); }; auto &&TargetElseGen = @@ -10397,6 +10829,10 @@ void CGOpenMPRuntime::scanForTargetRegionsFunctions(const Stmt *S, CodeGenFunction::EmitOMPTargetTeamsDistributeParallelForDeviceFunction( CGM, ParentName, cast(E)); + if (CGM.isXteamScanKernel() && !CGM.isXteamScanPhaseOne) + CodeGenFunction::EmitOMPTargetTeamsDistributeParallelForDeviceFunction( + CGM, ParentName, + cast(E)); break; case OMPD_target_teams_distribute_parallel_for_simd: CodeGenFunction:: @@ -10657,7 +11093,9 @@ void CGOpenMPRuntime::adjustTargetSpecificDataForLambdas( void CGOpenMPRuntime::processRequiresDirective(const OMPRequiresDecl *D) { for (const OMPClause *Clause : D->clauselists()) { - if (Clause->getClauseKind() == OMPC_unified_shared_memory) { + // default unified_address to the same semantics as unified_shared_memory + if (Clause->getClauseKind() == OMPC_unified_shared_memory || + Clause->getClauseKind() == OMPC_unified_address) { HasRequiresUnifiedSharedMemory = true; OMPBuilder.Config.setHasRequiresUnifiedSharedMemory(true); } else if (const auto *AC = @@ -12623,7 +13061,8 @@ void CGOpenMPSIMDRuntime::emitForStaticInit( void CGOpenMPSIMDRuntime::emitDistributeStaticInit( CodeGenFunction &CGF, SourceLocation Loc, - OpenMPDistScheduleClauseKind SchedKind, const StaticRTInput &Values) { + OpenMPDistScheduleClauseKind SchedKind, const StaticRTInput &Values, + bool IsMultiDeviceKernel) { llvm_unreachable("Not supported in SIMD-only mode"); } diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.h b/clang/lib/CodeGen/CGOpenMPRuntime.h index 6bfd7d6a590b9..105e6b65a6491 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.h +++ b/clang/lib/CodeGen/CGOpenMPRuntime.h @@ -1,3 +1,4 @@ + //===----- CGOpenMPRuntime.h - Interface to OpenMP Runtimes -----*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. @@ -955,11 +956,17 @@ class CGOpenMPRuntime { bool IVSigned = false; /// true if loop is ordered, false otherwise. bool Ordered = false; - /// Address of the output variable in which the flag of the last iteration - /// is returned. + /// true if kernel is multi-device + bool IsMultiDevice = false; Address IL = Address::invalid(); /// Address of the output variable in which the lower iteration number is /// returned. + Address MultiDeviceLB = Address::invalid(); + /// Address of the output variable in which the upper iteration number is + /// returned. + Address MultiDeviceUB = Address::invalid(); + /// Address of the output variable in which the lower iteration number is + /// returned. Address LB = Address::invalid(); /// Address of the output variable in which the upper iteration number is /// returned. @@ -975,6 +982,11 @@ class CGOpenMPRuntime { llvm::Value *Chunk = nullptr) : IVSize(IVSize), IVSigned(IVSigned), Ordered(Ordered), IL(IL), LB(LB), UB(UB), ST(ST), Chunk(Chunk) {} + void setMultiDeviceLBUB(Address LB, Address UB) { + MultiDeviceLB = LB; + MultiDeviceUB = UB; + IsMultiDevice = true; + } }; /// Call the appropriate runtime routine to initialize it before start /// of loop. @@ -1005,7 +1017,8 @@ class CGOpenMPRuntime { virtual void emitDistributeStaticInit(CodeGenFunction &CGF, SourceLocation Loc, OpenMPDistScheduleClauseKind SchedKind, - const StaticRTInput &Values); + const StaticRTInput &Values, + bool IsMultiDeviceKernel); /// Call the appropriate runtime routine to notify that we finished /// iteration of the ordered loop with the dynamic scheduling. @@ -1695,6 +1708,30 @@ class CGOpenMPRuntime { /// Returns true if the variable is a local variable in untied task. bool isLocalVarInUntiedTask(CodeGenFunction &CGF, const VarDecl *VD) const; + + // Returns whether the hint expressions for an architecture should be + // evaluated to decide which kind of atomic ops should be generated. + virtual bool needsHintsForFastFPAtomics() { return false; } + + /// Returns whether the current architecture supports fast FP atomics + virtual bool supportFastFPAtomics() { return false; } + + /// Used for AMDGPU architectures where certain fast FP atomics are defined as + /// instrinsic functions. + virtual std::pair emitFastFPAtomicCall(CodeGenFunction &CGF, + LValue X, RValue Update, + BinaryOperatorKind BO, + bool IsXBinopExpr) { + return std::make_pair(false, RValue::get(nullptr)); + } + + /// Used for AMDGPU architectures where certain atomics must be lowered + /// to a CAS loop. + virtual std::pair emitAtomicCASLoop(CodeGenFunction &CGF, + LValue X, RValue Update, + BinaryOperatorKind BO) { + return std::make_pair(false, RValue::get(nullptr)); + } }; /// Class supports emissionof SIMD-only code. @@ -1903,7 +1940,8 @@ class CGOpenMPSIMDRuntime final : public CGOpenMPRuntime { /// void emitDistributeStaticInit(CodeGenFunction &CGF, SourceLocation Loc, OpenMPDistScheduleClauseKind SchedKind, - const StaticRTInput &Values) override; + const StaticRTInput &Values, + bool IsMultiDeviceKernel) override; /// Call the appropriate runtime routine to notify that we finished /// iteration of the ordered loop with the dynamic scheduling. @@ -2335,6 +2373,29 @@ class CGOpenMPSIMDRuntime final : public CGOpenMPRuntime { } }; +class HintClause { +public: + /// Hint enum values for atomic and critical constructs (these enumerators are + /// taken from the enum omp_sync_hint_t in omp.h). + enum OpenMPSyncHintExpr { + OMP_sync_hint_none = 0, + OMP_lock_hint_none = OMP_sync_hint_none, + OMP_sync_hint_uncontended = 1, + OMP_lock_hint_uncontended = OMP_sync_hint_uncontended, + OMP_sync_hint_contended = (1 << 1), + OMP_lock_hint_contended = OMP_sync_hint_contended, + OMP_sync_hint_nonspeculative = (1 << 2), + OMP_lock_hint_nonspeculative = OMP_sync_hint_nonspeculative, + OMP_sync_hint_speculative = (1 << 3), + OMP_lock_hint_speculative = OMP_sync_hint_speculative, + kmp_lock_hint_hle = (1 << 16), + kmp_lock_hint_rtm = (1 << 17), + kmp_lock_hint_adaptive = (1 << 18), + AMD_fast_fp_atomics = (1 << 19), + AMD_safe_fp_atomics = (1 << 20) + }; +}; + } // namespace CodeGen // Utility for openmp doacross clause kind namespace { diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp index fddeba98adccc..3ce13edcddfd6 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp @@ -21,8 +21,12 @@ #include "clang/AST/StmtVisitor.h" #include "clang/Basic/Cuda.h" #include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/Frontend/OpenMP/OMPDeviceConstants.h" #include "llvm/Frontend/OpenMP/OMPGridValues.h" +#include "llvm/IR/IntrinsicsAMDGPU.h" +#include "llvm/IR/Metadata.h" +#include "llvm/Support/Debug.h" using namespace clang; using namespace CodeGen; @@ -541,7 +545,7 @@ static bool hasNestedSPMDDirective(ASTContext &Ctx, } return false; case OMPD_target_teams: - return isOpenMPParallelDirective(DKind); + return isOpenMPParallelDirective(DKind) || (DKind == OMPD_loop); case OMPD_target_simd: case OMPD_target_parallel: case OMPD_target_parallel_for: @@ -614,8 +618,9 @@ static bool hasNestedSPMDDirective(ASTContext &Ctx, return false; } -static bool supportsSPMDExecutionMode(ASTContext &Ctx, +static bool supportsSPMDExecutionMode(CodeGenModule &CGM, const OMPExecutableDirective &D) { + ASTContext &Ctx = CGM.getContext(); OpenMPDirectiveKind DirectiveKind = D.getDirectiveKind(); switch (DirectiveKind) { case OMPD_target: @@ -701,6 +706,117 @@ static bool supportsSPMDExecutionMode(ASTContext &Ctx, "Unknown programming model for OpenMP directive on NVPTX target."); } +// Create a unique global variable to indicate the flat-work-group-size +// for this region. Values are [1..1024]. +static void setPropertyWorkGroupSize(CodeGenModule &CGM, StringRef Name, + int WGSize) { + auto *GVMode = new llvm::GlobalVariable( + CGM.getModule(), CGM.Int16Ty, + /*isConstant=*/true, llvm::GlobalValue::WeakAnyLinkage, + llvm::ConstantInt::get(CGM.Int16Ty, WGSize), Twine(Name, "_wg_size")); + + CGM.addCompilerUsedGlobal(GVMode); +} + +// Create a unique global variable to indicate if the kernel is multi-device. +static void setMultiDeviceStatus(CodeGenModule &CGM, StringRef Name, + int IsMultiDevice) { + auto *GVMode = new llvm::GlobalVariable( + CGM.getModule(), CGM.Int8Ty, + /*isConstant=*/true, llvm::GlobalValue::WeakAnyLinkage, + llvm::ConstantInt::get(CGM.Int8Ty, IsMultiDevice), + Twine(Name, "_multi_device")); + + CGM.addCompilerUsedGlobal(GVMode); +} + +// Compute the correct number of threads in a team +// to accommodate for a master thread. +// Keep aligned with amdgpu plugin code located in function getLaunchVals +static int ComputeGenericWorkgroupSize(CodeGenModule &CGM, int WorkgroupSize) { + assert(WorkgroupSize >= 0); + int MaxWorkGroupSz = CGM.getTarget().getGridValue().GV_Max_WG_Size; + int WorkgroupSizeWithMaster = -1; + + // Add master thread in additional warp for GENERIC mode + // Only one additional thread is started, not an entire warp + + if (WorkgroupSize >= MaxWorkGroupSz) + // Do not exceed max number of threads: sacrifice last warp for + // the thread master + WorkgroupSizeWithMaster = + MaxWorkGroupSz - CGM.getTarget().getGridValue().GV_Warp_Size + 1; + else if ((unsigned int)WorkgroupSize < + CGM.getTarget().getGridValue().GV_Warp_Size) + // Cap threadsPerGroup at WarpSize level as we need a master + WorkgroupSizeWithMaster = CGM.getTarget().getGridValue().GV_Warp_Size + 1; + else + WorkgroupSizeWithMaster = + CGM.getTarget().getGridValue().GV_Warp_Size * + (WorkgroupSize / CGM.getTarget().getGridValue().GV_Warp_Size) + + 1; + return WorkgroupSizeWithMaster; +} + +void CGOpenMPRuntimeGPU::GenerateMetaData(CodeGenModule &CGM, + const OMPExecutableDirective &D, + llvm::Function *&OutlinedFn, + bool IsGeneric) { + if (!CGM.getTriple().isAMDGCN()) + return; + + int FlatAttr = 0; + bool flatAttrEmitted = false; + unsigned compileTimeThreadLimit = + CGM.getTarget().getGridValue().GV_Default_WG_Size; + bool isXteamRedKernel = CGM.isXteamRedKernel(D); + bool isBigJumpLoopKernel = CGM.isBigJumpLoopKernel(D); + bool isNoLoopKernel = CGM.isNoLoopKernel(D); + // If constant ThreadLimit(), set reqd_work_group_size metadata + if (isOpenMPTeamsDirective(D.getDirectiveKind()) || + isOpenMPParallelDirective(D.getDirectiveKind()) || isXteamRedKernel || + isBigJumpLoopKernel || isNoLoopKernel) { + // Call the work group size calculation based on kernel type. + if (isXteamRedKernel) + compileTimeThreadLimit = CGM.getXteamRedBlockSize(D); + else if (isBigJumpLoopKernel) + compileTimeThreadLimit = CGM.getBigJumpLoopBlockSize(D); + else if (isNoLoopKernel) + compileTimeThreadLimit = CGM.getNoLoopBlockSize(D); + else + compileTimeThreadLimit = CGM.getWorkGroupSizeSPMDHelper(D); + + // Add kernel metadata if ThreadLimit Clause is compile time constant > 0 + if (compileTimeThreadLimit > 0) { + if (IsGeneric) + compileTimeThreadLimit = + ComputeGenericWorkgroupSize(CGM, compileTimeThreadLimit); + FlatAttr = compileTimeThreadLimit; + OutlinedFn->addFnAttr("amdgpu-flat-work-group-size", + "1," + llvm::utostr(compileTimeThreadLimit)); + flatAttrEmitted = true; + } // end > 0 + } // end of amdgcn teams or parallel directive + + // emit amdgpu-flat-work-group-size if not emitted already. + if (!flatAttrEmitted) { + // When outermost construct does not have teams or parallel + // workgroup size is still based on mode + int GenericModeWorkgroupSize = compileTimeThreadLimit; + if (IsGeneric) + GenericModeWorkgroupSize = + ComputeGenericWorkgroupSize(CGM, compileTimeThreadLimit); + FlatAttr = GenericModeWorkgroupSize; + OutlinedFn->addFnAttr("amdgpu-flat-work-group-size", + "1," + llvm::utostr(GenericModeWorkgroupSize)); + } + // Emit a kernel descriptor for runtime. + setPropertyWorkGroupSize(CGM, OutlinedFn->getName(), FlatAttr); + + // Emit multi-device flag for this kernel. + setMultiDeviceStatus(CGM, OutlinedFn->getName(), CGM.isMultiDeviceKernel(D)); +} + void CGOpenMPRuntimeGPU::emitNonSPMDKernel(const OMPExecutableDirective &D, StringRef ParentName, llvm::Function *&OutlinedFn, @@ -740,6 +856,7 @@ void CGOpenMPRuntimeGPU::emitNonSPMDKernel(const OMPExecutableDirective &D, emitTargetOutlinedFunctionHelper(D, ParentName, OutlinedFn, OutlinedFnID, IsOffloadEntry, CodeGen); IsInTTDRegion = false; + GenerateMetaData(CGM, D, OutlinedFn, /*Generic*/ true); } void CGOpenMPRuntimeGPU::emitKernelInit(const OMPExecutableDirective &D, @@ -841,6 +958,54 @@ void CGOpenMPRuntimeGPU::emitSPMDKernel(const OMPExecutableDirective &D, emitTargetOutlinedFunctionHelper(D, ParentName, OutlinedFn, OutlinedFnID, IsOffloadEntry, CodeGen); IsInTTDRegion = false; + + GenerateMetaData(CGM, D, OutlinedFn, /*SPMD*/ false); +} + +// Create a unique global variable to indicate the execution mode of this target +// region. The execution mode is either 'generic', or 'spmd' depending on the +// target directive. This variable is picked up by the offload library to setup +// the device appropriately before kernel launch. If the execution mode is +// 'generic', the runtime reserves one warp for the master, otherwise, all +// warps participate in parallel work. +static void setPropertyExecutionMode(CodeGenModule &CGM, StringRef Name, + OMPTgtExecModeFlags Mode) { + auto *GVMode = new llvm::GlobalVariable( + CGM.getModule(), CGM.Int8Ty, /*isConstant=*/true, + llvm::GlobalValue::WeakAnyLinkage, + llvm::ConstantInt::get(CGM.Int8Ty, Mode), Twine(Name, "_exec_mode")); + CGM.addCompilerUsedGlobal(GVMode); +} + +// Create a global variable to indicate whether fast reduction is enabled for +// this file. This variable is read by the runtime while determining the launch +// bounds. +static void setIsFastReduction(CodeGenModule &CGM) { + auto *GVFastReduction = new llvm::GlobalVariable( + CGM.getModule(), CGM.Int8Ty, /*isConstant=*/true, + llvm::GlobalValue::WeakAnyLinkage, + llvm::ConstantInt::get(CGM.Int8Ty, + CGM.getLangOpts().OpenMPTargetFastReduction), + Twine("__omp_plugin_enable_fast_reduction")); + CGM.addCompilerUsedGlobal(GVFastReduction); +} + +static OMPTgtExecModeFlags +computeExecutionMode(bool Mode, const Stmt *DirectiveStmt, CodeGenModule &CGM) { + if (!Mode) + return OMP_TGT_EXEC_MODE_GENERIC; + if (DirectiveStmt) { + const Stmt *KernelForStmt = CGM.getSingleForStmt(DirectiveStmt); + if (KernelForStmt) { + if (CGM.isNoLoopKernel(KernelForStmt)) + return OMP_TGT_EXEC_MODE_SPMD_NO_LOOP; + if (CGM.isBigJumpLoopKernel(KernelForStmt)) + return OMP_TGT_EXEC_MODE_SPMD_BIG_JUMP_LOOP; + if (CGM.isXteamRedKernel(KernelForStmt)) + return OMP_TGT_EXEC_MODE_XTEAM_RED; + } + } + return OMP_TGT_EXEC_MODE_SPMD; } void CGOpenMPRuntimeGPU::emitTargetOutlinedFunction( @@ -852,14 +1017,48 @@ void CGOpenMPRuntimeGPU::emitTargetOutlinedFunction( assert(!ParentName.empty() && "Invalid target region parent name!"); - bool Mode = supportsSPMDExecutionMode(CGM.getContext(), D); + const Stmt *DirectiveStmt = CGM.getOptKernelKey(D); + bool Mode = supportsSPMDExecutionMode(CGM, D); + // Used by emitParallelCall + CGM.setIsSPMDExecutionMode(Mode); + if (Mode) { + // For AMDGPU, check if a no-loop or a Xteam reduction kernel should + // be generated and if so, set metadata that can be used by codegen. + // This check is done regardless of host or device codegen since the + // signature of the offloading routine has to match across host and device. + if (CGM.getTriple().isAMDGCN()) { + assert(CGM.getLangOpts().OpenMPIsTargetDevice && "Unexpected host path"); + CodeGenModule::NoLoopXteamErr NxStatus = CGM.checkAndSetNoLoopKernel(D); + DEBUG_WITH_TYPE(NO_LOOP_XTEAM_RED, + CGM.emitNxResult("[No-Loop/Big-Jump-Loop]", D, NxStatus)); + if (NxStatus != CodeGenModule::NxSuccess) { + NxStatus = CGM.checkAndSetXteamRedKernel(D); + DEBUG_WITH_TYPE(NO_LOOP_XTEAM_RED, + CGM.emitNxResult("[Xteam]", D, NxStatus)); + } + } + } bool IsBareKernel = D.getSingleClause(); if (Mode || IsBareKernel) emitSPMDKernel(D, ParentName, OutlinedFn, OutlinedFnID, IsOffloadEntry, CodeGen); - else + else { emitNonSPMDKernel(D, ParentName, OutlinedFn, OutlinedFnID, IsOffloadEntry, CodeGen); + DEBUG_WITH_TYPE(NO_LOOP_XTEAM_RED, + CGM.emitNxResult("[No-Loop/Big-Jump-Loop/Xteam]", D, + CodeGenModule::NxNonSPMD)); + } + setPropertyExecutionMode( + CGM, OutlinedFn->getName(), + IsBareKernel ? OMP_TGT_EXEC_MODE_BARE + : computeExecutionMode(Mode, DirectiveStmt, CGM)); + + if (Mode && DirectiveStmt) + CGM.resetOptKernelMetadata(DirectiveStmt); + + // Reset cached mode + CGM.setIsSPMDExecutionMode(false); } CGOpenMPRuntimeGPU::CGOpenMPRuntimeGPU(CodeGenModule &CGM) @@ -879,6 +1078,11 @@ CGOpenMPRuntimeGPU::CGOpenMPRuntimeGPU(CodeGenModule &CGM) if (CGM.getLangOpts().OpenMPCUDAMode) CurrentDataSharingMode = CGOpenMPRuntimeGPU::DS_CUDA; + // Write a global variable indicating whether fast reduction is enabled. + // This is done regardless of -nogpulib + if (!CGM.getLangOpts().OMPHostIRFile.empty()) + setIsFastReduction(CGM); + llvm::OpenMPIRBuilder &OMPBuilder = getOMPBuilder(); if (CGM.getLangOpts().NoGPULib || CGM.getLangOpts().OMPHostIRFile.empty()) return; @@ -1058,6 +1262,7 @@ llvm::Function *CGOpenMPRuntimeGPU::emitTeamsOutlinedFunction( } } Action(Loc, GlobalizedRD, MappedDeclsFields); CodeGen.setAction(Action); + llvm::Function *OutlinedFun = CGOpenMPRuntime::emitTeamsOutlinedFunction( CGF, D, ThreadIDVar, InnermostKind, CodeGen); @@ -1224,6 +1429,20 @@ void CGOpenMPRuntimeGPU::emitTeamsCall(CodeGenFunction &CGF, else OutlinedFnArgs.push_back(emitThreadIDAddress(CGF, Loc).emitRawPointer(CGF)); OutlinedFnArgs.push_back(ZeroAddr.getPointer()); + + // If this is a kernel we can run on multiple devices then we need to add + // the arguments for multi-device targets. This is needed for the case when + // we emit an outlined teams function which needs to be passed the multi + // device LB and UB. + if (CGM.isMultiDeviceKernel(D)) { + Address LBAddr = + CGF.GetAddrOfLocalVar(CGM.getMultiDeviceLBArg(D, CGF.CurFn)); + OutlinedFnArgs.push_back(CGF.Builder.CreateLoad(LBAddr)); + Address UBAddr = + CGF.GetAddrOfLocalVar(CGM.getMultiDeviceUBArg(D, CGF.CurFn)); + OutlinedFnArgs.push_back(CGF.Builder.CreateLoad(UBAddr)); + } + OutlinedFnArgs.append(CapturedVars.begin(), CapturedVars.end()); emitOutlinedFunctionCall(CGF, Loc, OutlinedFn, OutlinedFnArgs); } @@ -1712,7 +1931,7 @@ void CGOpenMPRuntimeGPU::emitReduction( const RecordDecl *ReductionRec = ::buildRecordForGlobalizedVars( CGM.getContext(), PrivatesReductions, {}, VarFieldMap, 1); - if (TeamsReduction) + if (!ParallelReduction) TeamsReductions.push_back(ReductionRec); // Source location for the ident struct @@ -1914,6 +2133,7 @@ llvm::Function *CGOpenMPRuntimeGPU::createParallelDataSharingWrapper( CGM.SetInternalFunctionAttributes(GlobalDecl(), Fn, CGFI); Fn->setLinkage(llvm::GlobalValue::InternalLinkage); + Fn->setDoesNotRecurse(); CodeGenFunction CGF(CGM, /*suppressNewContext=*/true); @@ -2257,8 +2477,16 @@ bool CGOpenMPRuntimeGPU::hasAllocateAttributeForGlobalVar(const VarDecl *VD, // Get current OffloadArch and ignore any unknown values static OffloadArch getOffloadArch(CodeGenModule &CGM) { - if (!CGM.getTarget().hasFeature("ptx")) + if (!CGM.getTarget().hasFeature("ptx") && + (CGM.getTriple().getArch() != llvm::Triple::amdgcn)) return OffloadArch::UNKNOWN; + if (CGM.getTriple().isAMDGCN()) + return StringToOffloadArch(CGM.getTarget().getTargetOpts().CPU); + // FIXME: Can we always just return StringToOffloadArch(...CPU) here? + llvm::StringMap Features; + CGM.getTarget().initFeatureMap(Features, CGM.getDiags(), + CGM.getTarget().getTargetOpts().CPU, + CGM.getTarget().getTargetOpts().Features); for (const auto &Feature : CGM.getTarget().getTargetOpts().FeatureMap) { if (Feature.getValue()) { OffloadArch Arch = StringToOffloadArch(Feature.getKey()); @@ -2273,7 +2501,8 @@ static OffloadArch getOffloadArch(CodeGenModule &CGM) { /// a restriction for OpenMP requires clause "unified_shared_memory". void CGOpenMPRuntimeGPU::processRequiresDirective(const OMPRequiresDecl *D) { for (const OMPClause *Clause : D->clauselists()) { - if (Clause->getClauseKind() == OMPC_unified_shared_memory) { + if (Clause->getClauseKind() == OMPC_unified_shared_memory || + Clause->getClauseKind() == OMPC_unified_address) { OffloadArch Arch = getOffloadArch(CGM); switch (Arch) { case OffloadArch::SM_20: @@ -2402,3 +2631,1104 @@ llvm::Value *CGOpenMPRuntimeGPU::getGPUThreadID(CodeGenFunction &CGF) { CGM.getModule(), OMPRTL___kmpc_get_hardware_thread_id_in_block), Args); } +llvm::Value *CGOpenMPRuntimeGPU::getGPUBlockID(CodeGenFunction &CGF) { + CGBuilderTy &Bld = CGF.Builder; + llvm::Function *F = + CGF.CGM.getIntrinsic(llvm::Intrinsic::amdgcn_workgroup_id_x); + return Bld.CreateCall(F, std::nullopt, "gpu_block_id"); +} + +llvm::Value *CGOpenMPRuntimeGPU::getGPUNumBlocks(CodeGenFunction &CGF) { + return CGF.EmitRuntimeCall(OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_get_hardware_num_blocks)); +} + +llvm::Value *CGOpenMPRuntimeGPU::initSpecializedKernel(CodeGenFunction &CGF) { + return CGF.EmitRuntimeCall(OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_specialized_kernel_init)); +} + +std::pair +CGOpenMPRuntimeGPU::getXteamRedFunctionPtrs( + CodeGenFunction &CGF, llvm::Type *RedVarType, + CodeGenModule::XteamRedOpKind Opcode) { + if (RedVarType->isIntegerTy()) { + if (RedVarType->getPrimitiveSizeInBits() == 16) { + switch (Opcode) { + case CodeGenModule::XR_OP_unknown: + llvm_unreachable("Xteam reduction opcode cannot be unknown"); + case CodeGenModule::XR_OP_add: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_s) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_lds_s) + .getCallee()); + case CodeGenModule::XR_OP_min: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_s) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_lds_s) + .getCallee()); + case CodeGenModule::XR_OP_max: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_s) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_lds_s) + .getCallee()); + } + } + if (RedVarType->getPrimitiveSizeInBits() == 32) { + switch (Opcode) { + case CodeGenModule::XR_OP_unknown: + llvm_unreachable("Xteam reduction opcode cannot be unknown"); + case CodeGenModule::XR_OP_add: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_i) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_lds_i) + .getCallee()); + case CodeGenModule::XR_OP_min: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_i) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_lds_i) + .getCallee()); + case CodeGenModule::XR_OP_max: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_i) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_lds_i) + .getCallee()); + } + } + if (RedVarType->getPrimitiveSizeInBits() == 64) { + switch (Opcode) { + case CodeGenModule::XR_OP_unknown: + llvm_unreachable("Xteam reduction opcode cannot be unknown"); + case CodeGenModule::XR_OP_add: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_l) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_lds_l) + .getCallee()); + case CodeGenModule::XR_OP_min: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_l) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_lds_l) + .getCallee()); + case CodeGenModule::XR_OP_max: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_l) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_lds_l) + .getCallee()); + } + } + } + + if (RedVarType->isFloatTy()) { + switch (Opcode) { + case CodeGenModule::XR_OP_unknown: + llvm_unreachable("Xteam reduction opcode cannot be unknown"); + case CodeGenModule::XR_OP_add: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_f) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_lds_f) + .getCallee()); + case CodeGenModule::XR_OP_min: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_f) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_lds_f) + .getCallee()); + case CodeGenModule::XR_OP_max: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_f) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_lds_f) + .getCallee()); + } + } + + if (RedVarType->isDoubleTy()) { + switch (Opcode) { + case CodeGenModule::XR_OP_unknown: + llvm_unreachable("Xteam reduction opcode cannot be unknown"); + case CodeGenModule::XR_OP_add: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_d) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_lds_d) + .getCallee()); + case CodeGenModule::XR_OP_min: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_d) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_lds_d) + .getCallee()); + case CodeGenModule::XR_OP_max: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_d) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_lds_d) + .getCallee()); + } + } + + if (RedVarType->isHalfTy()) { + switch (Opcode) { + case CodeGenModule::XR_OP_unknown: + llvm_unreachable("Xteam reduction opcode cannot be unknown"); + case CodeGenModule::XR_OP_add: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_h) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_lds_h) + .getCallee()); + case CodeGenModule::XR_OP_min: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_h) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_lds_h) + .getCallee()); + case CodeGenModule::XR_OP_max: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_h) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_lds_h) + .getCallee()); + } + } + + if (RedVarType->isBFloatTy()) { + switch (Opcode) { + case CodeGenModule::XR_OP_unknown: + llvm_unreachable("Xteam reduction opcode cannot be unknown"); + case CodeGenModule::XR_OP_add: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_bf) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_sum_lds_bf) + .getCallee()); + case CodeGenModule::XR_OP_min: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_bf) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_min_lds_bf) + .getCallee()); + case CodeGenModule::XR_OP_max: + return std::make_pair( + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_bf) + .getCallee(), + OMPBuilder + .getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_rfun_max_lds_bf) + .getCallee()); + } + } + llvm_unreachable("No support for other types currently."); +} + +llvm::Value *CGOpenMPRuntimeGPU::getXteamRedOperation( + CodeGenFunction &CGF, llvm::Value *Val, llvm::Value *OrigVarPtr, + llvm::Value *DTeamVals, llvm::Value *DTeamsDonePtr, + llvm::Value *ThreadStartIndex, llvm::Value *NumTeams, int BlockSize, + CodeGenModule::XteamRedOpKind Opcode, bool IsFast) { + // TODO handle more types + llvm::Type *RedVarType = Val->getType(); + assert((RedVarType->isFloatTy() || RedVarType->isDoubleTy() || + RedVarType->isHalfTy() || RedVarType->isBFloatTy() || + (RedVarType->isIntegerTy() && + (RedVarType->getPrimitiveSizeInBits() == 16 || + RedVarType->getPrimitiveSizeInBits() == 32 || + RedVarType->getPrimitiveSizeInBits() == 64))) && + "Unhandled type"); + assert((Opcode == CodeGenModule::XR_OP_add || + Opcode == CodeGenModule::XR_OP_min || + Opcode == CodeGenModule::XR_OP_max) && + "Unexpected Xteam reduction operator"); + std::pair RfunPair = + getXteamRedFunctionPtrs(CGF, RedVarType, Opcode); + // The initial value (referred to as the sentinel value) of the local + // reduction variable depends on the opcode. + llvm::Value *SentinelVal = CGF.getXteamRedSentinel(RedVarType, Opcode); + + llvm::Value *Args[] = { + Val, + OrigVarPtr, + DTeamVals, + DTeamsDonePtr, + RfunPair.first, + RfunPair.second, + SentinelVal, + ThreadStartIndex, + NumTeams, + CGF.CGM.getLangOpts().OpenMPTargetMultiDevice + ? llvm::ConstantInt::get(CGF.CGM.Int32Ty, + 0) /* __MEMORY_SCOPE_SYSTEM */ + : llvm::ConstantInt::get(CGF.CGM.Int32Ty, + 1) /* __MEMORY_SCOPE_DEVICE */}; + + unsigned WarpSize = CGF.getTarget().getGridValue().GV_Warp_Size; + assert(WarpSize == 32 || WarpSize == 64); + + assert(BlockSize > 0 && BlockSize <= llvm::omp::xteam_red::MaxBlockSize && + "XTeam Reduction blocksize outside expected range"); + assert(((BlockSize & (BlockSize - 1)) == 0) && + "XTeam Reduction blocksize must be a power of two"); + + // Prior analysis ensures that Xteam min/max reduction is not initiated if + // fast reduction is requested by the user. + if (IsFast) + assert(Opcode == CodeGenModule::XR_OP_add && + "Fast reduction is not enabled for min and max"); + + if (RedVarType->isIntegerTy()) { + if (RedVarType->getPrimitiveSizeInBits() == 16) { + if (WarpSize == 32) { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_s_32x32_fast_sum + : OMPRTL___kmpc_xteamr_s_32x32), + Args); + } else { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_s_16x64_fast_sum + : OMPRTL___kmpc_xteamr_s_16x64), + Args); + } + } + if (RedVarType->getPrimitiveSizeInBits() == 32) { + if (WarpSize == 32) { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_i_32x32_fast_sum + : OMPRTL___kmpc_xteamr_i_32x32), + Args); + } else { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_i_16x64_fast_sum + : OMPRTL___kmpc_xteamr_i_16x64), + Args); + } + } + if (RedVarType->getPrimitiveSizeInBits() == 64) { + if (WarpSize == 32) { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_l_32x32_fast_sum + : OMPRTL___kmpc_xteamr_l_32x32), + Args); + } else { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_l_16x64_fast_sum + : OMPRTL___kmpc_xteamr_l_16x64), + Args); + } + } + } + if (RedVarType->isFloatTy()) { + if (WarpSize == 32) { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_f_32x32_fast_sum + : OMPRTL___kmpc_xteamr_f_32x32), + Args); + } else { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_f_16x64_fast_sum + : OMPRTL___kmpc_xteamr_f_16x64), + Args); + } + } + if (RedVarType->isDoubleTy()) { + if (WarpSize == 32) { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_d_32x32_fast_sum + : OMPRTL___kmpc_xteamr_d_32x32), + Args); + } else { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_d_16x64_fast_sum + : OMPRTL___kmpc_xteamr_d_16x64), + Args); + } + } + if (RedVarType->isHalfTy()) { + if (WarpSize == 32) { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_h_32x32_fast_sum + : OMPRTL___kmpc_xteamr_h_32x32), + Args); + } else { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_h_16x64_fast_sum + : OMPRTL___kmpc_xteamr_h_16x64), + Args); + } + } + if (RedVarType->isBFloatTy()) { + if (WarpSize == 32) { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_bf_32x32_fast_sum + : OMPRTL___kmpc_xteamr_bf_32x32), + Args); + } else { + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), IsFast ? OMPRTL___kmpc_xteamr_bf_16x64_fast_sum + : OMPRTL___kmpc_xteamr_bf_16x64), + Args); + } + } + llvm_unreachable("No support for other types currently."); +} + +llvm::Value *CGOpenMPRuntimeGPU::getXteamScanSum( + CodeGenFunction &CGF, llvm::Value *Val, llvm::Value *SumPtr, + llvm::Value *DTeamVals, llvm::Value *DTeamsDonePtr, + llvm::Value *DScanStorage, llvm::Value *ThreadStartIndex, + llvm::Value *NumTeams, int BlockSize, bool IsFast) { + // TODO handle more types + llvm::Type *SumType = Val->getType(); + assert( + (SumType->isFloatTy() || SumType->isDoubleTy() || + (SumType->isIntegerTy() && (SumType->getPrimitiveSizeInBits() == 32 || + SumType->getPrimitiveSizeInBits() == 64))) && + "Unhandled type"); + + llvm::Type *Int32Ty = llvm::Type::getInt32Ty(CGM.getLLVMContext()); + llvm::Type *Int64Ty = llvm::Type::getInt64Ty(CGM.getLLVMContext()); + + std::pair RfunPair = + getXteamRedFunctionPtrs(CGF, SumType, CodeGenModule::XR_OP_add); + llvm::Value *ZeroVal = (SumType->isFloatTy() || SumType->isDoubleTy()) + ? llvm::ConstantFP::getZero(SumType) + : SumType->getPrimitiveSizeInBits() == 32 + ? llvm::ConstantInt::get(Int32Ty, 0) + : llvm::ConstantInt::get(Int64Ty, 0); + + // TODO: The argument 'SumPtr' is useless for Xteam Scan. Plan to get rid of + // it in the future from both here and the DeviceRTL implementation. + llvm::Value *Args[] = {Val, + DScanStorage, + SumPtr, + DTeamVals, + DTeamsDonePtr, + RfunPair.first, + RfunPair.second, + ZeroVal, + ThreadStartIndex, + NumTeams}; + + unsigned WarpSize = CGF.getTarget().getGridValue().GV_Warp_Size; + assert(WarpSize == 32 || WarpSize == 64); + + assert(BlockSize > 0 && BlockSize <= llvm::omp::xteam_red::MaxBlockSize && + "XTeam Reduction blocksize outside expected range"); + assert(((BlockSize & (BlockSize - 1)) == 0) && + "XTeam Reduction blocksize must be a power of two"); + + if (SumType->isIntegerTy()) { + if (SumType->getPrimitiveSizeInBits() == 64) { + if (WarpSize == 64) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_l_16x64), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_l_8x64), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_l_4x64), + Args); + else + llvm_unreachable("Block size unsupported."); + } else if (WarpSize == 32) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_l_32x32), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_l_16x32), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_l_8x32), + Args); + else + llvm_unreachable("Block size unsupported."); + } else + llvm_unreachable("Warp size should be 32 or 64."); + } else if (SumType->getPrimitiveSizeInBits() == 32) { + if (WarpSize == 64) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_i_16x64), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_i_8x64), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_i_4x64), + Args); + else + llvm_unreachable("Block size unsupported."); + } else if (WarpSize == 32) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_i_32x32), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_i_16x32), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_i_8x32), + Args); + else + llvm_unreachable("Block size unsupported."); + } else + llvm_unreachable("Warp size should be 32 or 64."); + } + } + if (SumType->isDoubleTy()) { + if (WarpSize == 64) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_d_16x64), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_d_8x64), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_d_4x64), + Args); + else + llvm_unreachable("Block size unsupported."); + } else if (WarpSize == 32) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_d_32x32), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_d_16x32), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_d_8x32), + Args); + else + llvm_unreachable("Block size unsupported."); + } else + llvm_unreachable("Warp size should be 32 or 64."); + } + if (SumType->isFloatTy()) { + // FIXME: The Xteam Scan Implementation exhibits unpredictable behavior for + // 'float' datatype when number of elements to be scanned goes beyond 1 + // million. This issue requires further debugging. + if (WarpSize == 64) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_f_16x64), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_f_8x64), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_f_4x64), + Args); + else + llvm_unreachable("BBlock size unsupported."); + } else if (WarpSize == 32) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_f_32x32), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_f_16x32), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction(CGM.getModule(), + OMPRTL___kmpc_xteams_f_8x32), + Args); + else + llvm_unreachable("Block size unsupported."); + } else + llvm_unreachable("Warp size should be 32 or 64."); + } + llvm_unreachable("No support for other types currently."); +} + +llvm::Value *CGOpenMPRuntimeGPU::getXteamScanPhaseTwo( + CodeGenFunction &CGF, llvm::Value *Val, llvm::Value *SegmentSize, + llvm::Value *DTeamVals, llvm::Value *DScanStorage, + llvm::Value *DSegmentVals, llvm::Value *ThreadStartIndex, int BlockSize, + bool IsInclusiveScan) { + // TODO handle more types + llvm::Type *SumType = Val->getType(); + assert( + (SumType->isFloatTy() || SumType->isDoubleTy() || + (SumType->isIntegerTy() && (SumType->getPrimitiveSizeInBits() == 32 || + SumType->getPrimitiveSizeInBits() == 64))) && + "Unhandled type"); + + llvm::Type *Int32Ty = llvm::Type::getInt32Ty(CGM.getLLVMContext()); + llvm::Type *Int64Ty = llvm::Type::getInt64Ty(CGM.getLLVMContext()); + + std::pair RfunPair = + getXteamRedFunctionPtrs(CGF, SumType, CodeGenModule::XR_OP_add); + llvm::Value *ZeroVal = (SumType->isFloatTy() || SumType->isDoubleTy()) + ? llvm::ConstantFP::getZero(SumType) + : SumType->getPrimitiveSizeInBits() == 32 + ? llvm::ConstantInt::get(Int32Ty, 0) + : llvm::ConstantInt::get(Int64Ty, 0); + + llvm::Value *IsInclusiveScanVal = + llvm::ConstantInt::get(Int32Ty, IsInclusiveScan); + llvm::Value *Args[] = {DScanStorage, SegmentSize, DTeamVals, + DSegmentVals, RfunPair.first, ZeroVal, + ThreadStartIndex, IsInclusiveScanVal}; + + unsigned WarpSize = CGF.getTarget().getGridValue().GV_Warp_Size; + assert(WarpSize == 32 || WarpSize == 64); + + assert(BlockSize > 0 && BlockSize <= llvm::omp::xteam_red::MaxBlockSize && + "XTeam Reduction blocksize outside expected range"); + assert(((BlockSize & (BlockSize - 1)) == 0) && + "XTeam Reduction blocksize must be a power of two"); + + if (SumType->isIntegerTy()) { + if (SumType->getPrimitiveSizeInBits() == 64) { + if (WarpSize == 64) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_l_16x64), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_l_8x64), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_l_4x64), + Args); + else + llvm_unreachable("Block size unsupported."); + } else if (WarpSize == 32) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_l_32x32), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_l_16x32), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_l_8x32), + Args); + else + llvm_unreachable("Block size unsupported."); + } else + llvm_unreachable("Warp size should be 32 or 64."); + } else if (SumType->getPrimitiveSizeInBits() == 32) { + if (WarpSize == 64) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_i_16x64), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_i_8x64), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_i_4x64), + Args); + else + llvm_unreachable("Block size unsupported."); + } else if (WarpSize == 32) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_i_32x32), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_i_16x32), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_i_8x32), + Args); + else + llvm_unreachable("Block size unsupported."); + } else + llvm_unreachable("Warp size should be 32 or 64."); + } + } + if (SumType->isDoubleTy()) { + if (WarpSize == 64) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_d_16x64), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_d_8x64), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_d_4x64), + Args); + else + llvm_unreachable("Block size unsupported."); + } else if (WarpSize == 32) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_d_32x32), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_d_16x32), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_d_8x32), + Args); + else + llvm_unreachable("Block size unsupported."); + } else + llvm_unreachable("Warp size should be 32 or 64."); + } + if (SumType->isFloatTy()) { + if (WarpSize == 64) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_f_16x64), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_f_8x64), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_f_4x64), + Args); + else + llvm_unreachable("BBlock size unsupported."); + } else if (WarpSize == 32) { + if (BlockSize == 1024) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_f_32x32), + Args); + else if (BlockSize == 512) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_f_16x32), + Args); + else if (BlockSize == 256) + return CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_xteams_phase2_f_8x32), + Args); + else + llvm_unreachable("Block size unsupported."); + } else + llvm_unreachable("Warp size should be 32 or 64."); + } + llvm_unreachable("No support for other types currently."); +} + +bool CGOpenMPRuntimeGPU::needsHintsForFastFPAtomics() { + return getOffloadArch(CGM) == OffloadArch::GFX90a; +} + +bool CGOpenMPRuntimeGPU::supportFastFPAtomics() { + OffloadArch Arch = getOffloadArch(CGM); + switch (Arch) { + case OffloadArch::GFX90a: + case OffloadArch::GFX942: + return true; + default: + break; + } + return false; +} + +std::pair +CGOpenMPRuntimeGPU::emitFastFPAtomicCall(CodeGenFunction &CGF, LValue X, + RValue Update, BinaryOperatorKind BO, + bool IsXBinopExpr) { + CGBuilderTy &Bld = CGF.Builder; + llvm::AtomicRMWInst::BinOp Kind = llvm::AtomicRMWInst::FAdd; + switch (BO) { + case BO_Sub: + Kind = llvm::AtomicRMWInst::FSub; + break; + case BO_Add: + Kind = llvm::AtomicRMWInst::FAdd; + break; + case BO_LT: + Kind = IsXBinopExpr ? llvm::AtomicRMWInst::FMax : llvm::AtomicRMWInst::FMin; + break; + case BO_GT: + Kind = IsXBinopExpr ? llvm::AtomicRMWInst::FMin : llvm::AtomicRMWInst::FMax; + break; + default: + // remaining operations are not supported yet + return std::make_pair(false, RValue::get(nullptr)); + } + + llvm::Value *UpdateVal = Update.getScalarVal(); + + // The scope of the atomic, currently set to 'agent'. By default, if this + // scope is not specified the scope will be 'system' scope. + llvm::SyncScope::ID SSID = + CGM.getLLVMContext().getOrInsertSyncScopeID("agent"); + llvm::AtomicRMWInst *CallInst = Bld.CreateAtomicRMW( + Kind, X.getAddress(), UpdateVal, llvm::AtomicOrdering::Monotonic, SSID); + + // The following settings are used to get the atomicrmw instruction to + // be closer in spirit to the previous use of the intrinsic. + // Setting of amdgpu.no.fine.grained.memory property + llvm::MDTuple *EmptyMD = llvm::MDNode::get(CGM.getLLVMContext(), {}); + CallInst->setMetadata("amdgpu.no.fine.grained.memory", EmptyMD); + + // Setting of amdgpu.ignore.denormal.mode + if (Kind == llvm::AtomicRMWInst::FAdd && UpdateVal->getType()->isFloatTy()) + CallInst->setMetadata("amdgpu.ignore.denormal.mode", EmptyMD); + + // Note: breaks fp_atomics test so volatile cannot be used + // CallInst->setVolatile(true); + + return std::make_pair(true, RValue::get(CallInst)); +} + +void CGOpenMPRuntimeGPU::emitFlush(CodeGenFunction &CGF, ArrayRef, + SourceLocation Loc, + llvm::AtomicOrdering AO) { + if (CGF.CGM.getLangOpts().OpenMPIRBuilder) { + OMPBuilder.createFlush(CGF.Builder); + } else { + if (!CGF.HaveInsertPoint()) + return; + // Build call void __kmpc_flush(ident_t *loc) and variants + //__kmpc_flush_acquire, __kmpc_flush_release, __kmpc_flush_acqrel + if (AO == llvm::AtomicOrdering::NotAtomic || + AO == llvm::AtomicOrdering::SequentiallyConsistent) + CGF.EmitRuntimeCall(OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_flush), + emitUpdateLocation(CGF, Loc)); + else + switch (AO) { + case llvm::AtomicOrdering::Acquire: + CGF.EmitRuntimeCall(OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_flush_acquire), + emitUpdateLocation(CGF, Loc)); + return; + case llvm::AtomicOrdering::Release: + CGF.EmitRuntimeCall(OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_flush_release), + emitUpdateLocation(CGF, Loc)); + return; + case llvm::AtomicOrdering::AcquireRelease: + CGF.EmitRuntimeCall(OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_flush_acqrel), + emitUpdateLocation(CGF, Loc)); + return; + default: + llvm_unreachable("Unexpected atomic ordering for flush directive."); + } + } +} + +std::pair +CGOpenMPRuntimeGPU::emitAtomicCASLoop(CodeGenFunction &CGF, LValue X, + RValue Update, BinaryOperatorKind BO) { + ASTContext &Context = CGF.getContext(); + SmallVector CASLoopArgs; + CASLoopArgs.reserve(2); + CASLoopArgs.push_back(X.getPointer(CGF)); + CASLoopArgs.push_back(Update.getScalarVal()); + llvm::Value *CallInst = nullptr; + switch (BO) { + case BO_LT: { // unavailable for both float, double, and integer types (32 and + // 64 bits) + if (Update.getScalarVal()->getType()->isIntegerTy() && + !(Context.getTypeSize(X.getType()) == 32 || + Context.getTypeSize(X.getType()) == 64)) + llvm_unreachable("Atomic Min types available for CAS loop conversion is " + "double, float, int (32 and 64 bits)"); + + if (Update.getScalarVal()->getType()->isDoubleTy()) + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_atomicCASLoopMin_double), + CASLoopArgs); + else if (Update.getScalarVal()->getType()->isFloatTy()) + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_atomicCASLoopMin_float), + CASLoopArgs); + + else if (Update.getScalarVal()->getType()->isIntegerTy()) { + if (Context.getTypeSize(X.getType()) == 32) { + if (X.getType()->hasSignedIntegerRepresentation()) { + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_atomicCASLoopMin_int32_t), + CASLoopArgs); + } else { + const llvm::StringRef FunNameStr = "__kmpc_atomicCASLoopMin_uint32_t"; + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.unsignedGetOrCreateAtomicCASRuntimeFunction( + CGM.getModule(), FunNameStr, + /*RetType=*/CGF.Builder.getVoidTy(), + X.getPointer(CGF)->getType(), + Update.getScalarVal()->getType()), + CASLoopArgs); + } + } else if (Context.getTypeSize(X.getType()) == 64) { + if (X.getType()->hasSignedIntegerRepresentation()) { + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_atomicCASLoopMin_int64_t), + CASLoopArgs); + } else { + const llvm::StringRef FunNameStr = "__kmpc_atomicCASLoopMin_uint64_t"; + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.unsignedGetOrCreateAtomicCASRuntimeFunction( + CGM.getModule(), FunNameStr, + /*RetType=*/CGF.Builder.getVoidTy(), + X.getPointer(CGF)->getType(), + Update.getScalarVal()->getType()), + CASLoopArgs); + } + } + } + // other types (e.g., int8_t) are handled by backend directly + return std::make_pair(true, RValue::get(CallInst)); + } + case BO_GT: { // unavailable for both float, double, and integer types (32 and + // 664 bits) + if (Update.getScalarVal()->getType()->isIntegerTy() && + !(Context.getTypeSize(X.getType()) == 32 || + Context.getTypeSize(X.getType()) == 64)) + llvm_unreachable("Atomic Max types available for CAS loop conversion is " + "double, float, int (32 and 64 bits)"); + + if (Update.getScalarVal()->getType()->isDoubleTy()) + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_atomicCASLoopMax_double), + CASLoopArgs); + else if (Update.getScalarVal()->getType()->isFloatTy()) + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_atomicCASLoopMax_float), + CASLoopArgs); + + else if (Update.getScalarVal()->getType()->isIntegerTy()) { + if (Context.getTypeSize(X.getType()) == 32) { + if (X.getType()->hasSignedIntegerRepresentation()) { + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_atomicCASLoopMax_int32_t), + CASLoopArgs); + } else { + const llvm::StringRef FunNameStr = "__kmpc_atomicCASLoopMax_uint32_t"; + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.unsignedGetOrCreateAtomicCASRuntimeFunction( + CGM.getModule(), FunNameStr, + /*RetType=*/CGF.Builder.getVoidTy(), + X.getPointer(CGF)->getType(), + Update.getScalarVal()->getType()), + CASLoopArgs); + } + } else if (Context.getTypeSize(X.getType()) == 64) { + if (X.getType()->hasSignedIntegerRepresentation()) { + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.getOrCreateRuntimeFunction( + CGM.getModule(), OMPRTL___kmpc_atomicCASLoopMax_int64_t), + CASLoopArgs); + } else { + const llvm::StringRef FunNameStr = "__kmpc_atomicCASLoopMax_uint64_t"; + CallInst = CGF.EmitRuntimeCall( + OMPBuilder.unsignedGetOrCreateAtomicCASRuntimeFunction( + CGM.getModule(), FunNameStr, + /*RetType=*/CGF.Builder.getVoidTy(), + X.getPointer(CGF)->getType(), + Update.getScalarVal()->getType()), + CASLoopArgs); + } + } + } + return std::make_pair(true, RValue::get(CallInst)); + } + case BO_Add: + case BO_Sub: + case BO_And: + case BO_Or: + case BO_Xor: + llvm_unreachable("Atomic operation must be generated via clang atomic " + "support and not via OpenMP runtime"); + break; + default: + llvm_unreachable( + "Operation is not supported by kmpc_atomicCASLoop functions"); + break; + } + return std::make_pair(false, RValue::get(nullptr)); +} diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h index 3a7ee5456a9d2..2011a1add4953 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h +++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h @@ -67,6 +67,9 @@ class CGOpenMPRuntimeGPU : public CGOpenMPRuntime { void emitKernelDeinit(CodeGenFunction &CGF, EntryFunctionState &EST, bool IsSPMD); + void GenerateMetaData(CodeGenModule &CGM, const OMPExecutableDirective &D, + llvm::Function *&OutlinedFn, bool isSPMD); + /// Helper for generic variables globalization prolog. void emitGenericVarsProlog(CodeGenFunction &CGF, SourceLocation Loc); @@ -156,6 +159,62 @@ class CGOpenMPRuntimeGPU : public CGOpenMPRuntime { /// Get the maximum number of threads in a block of the GPU. llvm::Value *getGPUNumThreads(CodeGenFunction &CGF); + /// Get the block id of the current thread on the GPU + llvm::Value *getGPUBlockID(CodeGenFunction &CGF); + + /// Get the number of blocks on the GPU + llvm::Value *getGPUNumBlocks(CodeGenFunction &CGF); + + /// Initialization for a specialized kernel. + llvm::Value *initSpecializedKernel(CodeGenFunction &CGF); + + std::pair + getXteamRedFunctionPtrs(CodeGenFunction &CGF, llvm::Type *RedVarType, + CodeGenModule::XteamRedOpKind Opcode); + + /// Generate a call to cross-team operation. + llvm::Value *getXteamRedOperation(CodeGenFunction &CGF, llvm::Value *Val, + llvm::Value *OrigVarPtr, + llvm::Value *DTeamVals, + llvm::Value *DTeamsDonePtr, + llvm::Value *ThreadStartIndex, + llvm::Value *NumTeams, int BlockSize, + CodeGenModule::XteamRedOpKind, bool IsFast); + + /// Emit call to Cross-team scan entry points + llvm::Value * + getXteamScanSum(CodeGenFunction &CGF, llvm::Value *Val, llvm::Value *SumPtr, + llvm::Value *DTeamVals, llvm::Value *DTeamsDonePtr, + llvm::Value *DScanStorage, llvm::Value *ThreadStartIndex, + llvm::Value *NumTeams, int BlockSize, bool IsFast); + + /// Emit calls to Cross-team scan Phase 2 entry points + llvm::Value *getXteamScanPhaseTwo(CodeGenFunction &CGF, llvm::Value *Val, + llvm::Value *SegmentSize, + llvm::Value *DTeamVals, + llvm::Value *DScanStorage, + llvm::Value *DSegmentVals, + llvm::Value *ThreadStartIndex, + int BlockSize, bool IsInclusiveScan); + + // Returns whether the hint expressions for an architecture should be + // evaluated to decide which kind of atomic ops should be generated. + bool needsHintsForFastFPAtomics() override final; + + /// Returns whether the current architecture supports fast FP atomics + bool supportFastFPAtomics() override; + + // Emit call to fast FP intrinsics + std::pair emitFastFPAtomicCall(CodeGenFunction &CGF, LValue X, + RValue Update, + BinaryOperatorKind BO, + bool IsXBinopExpr) override; + + // Emit call to CAS loop + std::pair emitAtomicCASLoop(CodeGenFunction &CGF, LValue X, + RValue Update, + BinaryOperatorKind BO) override; + /// Emit call to void __kmpc_push_proc_bind(ident_t *loc, kmp_int32 /// global_tid, int proc_bind) to generate code for 'proc_bind' clause. void emitProcBindClause(CodeGenFunction &CGF, @@ -358,6 +417,11 @@ class CGOpenMPRuntimeGPU : public CGOpenMPRuntime { /// space. bool hasAllocateAttributeForGlobalVar(const VarDecl *VD, LangAS &AS) override; + /// Emit flush of the variables specified in 'omp flush' directive. + /// \param Vars List of variables to flush. + void emitFlush(CodeGenFunction &CGF, ArrayRef Vars, + SourceLocation Loc, llvm::AtomicOrdering AO) override; + private: /// Track the execution mode when codegening directives within a target /// region. The appropriate mode (SPMD/NON-SPMD) is set on entry to the diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp index fdc1a11f6c55c..6a24cc37539e4 100644 --- a/clang/lib/CodeGen/CGStmt.cpp +++ b/clang/lib/CodeGen/CGStmt.cpp @@ -12,6 +12,7 @@ #include "CGDebugInfo.h" #include "CGOpenMPRuntime.h" +#include "CGOpenMPRuntimeGPU.h" #include "CodeGenFunction.h" #include "CodeGenModule.h" #include "CodeGenPGO.h" @@ -58,6 +59,1081 @@ void CodeGenFunction::EmitStopPoint(const Stmt *S) { } } +llvm::Value *CodeGenFunction::applyNoLoopInc(const Expr *Inc, + const VarDecl *IVDecl, + llvm::Value *CurrVal) { + // If we reach here, it must be a unary increment or a binary + // step expression. For a binary expression, generate myid = step * myid + const Expr *StepExpr = CGM.getBinaryExprStep(Inc, IVDecl); + if (StepExpr == nullptr) + return CurrVal; // nothing to do + llvm::Value *StepVal = EmitScalarExpr(StepExpr); + return Builder.CreateMul( + Builder.CreateIntCast(CurrVal, ConvertTypeForMem(StepExpr->getType()), + false), + StepVal); +} + +std::pair +CodeGenFunction::EmitBigJumpLoopStartingIndex(const ForStmt &FStmt, + const FunctionArgList *Args) { + const CodeGenModule::OptKernelNestDirectives &Directives = + CGM.isXteamRedKernel(&FStmt) ? CGM.getXteamRedNestDirs(&FStmt) + : CGM.getBigJumpLoopNestDirs(&FStmt); + assert(Directives.size() > 0 && isa(Directives.back()) && + "Appropriate directive not found"); + const OMPLoopDirective &LD = *(cast(Directives.back())); + std::pair IVPair = EmitNoLoopIV(LD, Args); + const VarDecl *LoopVD = IVPair.first; + Address IvAddr = IVPair.second; + + // Generate idx = workgroup_id * workgroup_size + workitem_id + auto &RT = static_cast(CGM.getOpenMPRuntime()); + + // workitem_id + llvm::Value *GpuThreadId = RT.getGPUThreadID(*this); + + // workgroup_size + llvm::Value *WorkGroupSize = RT.getGPUNumThreads(*this); + + // workgroup_id + llvm::Value *WorkGroupId = RT.getGPUBlockID(*this); + + llvm::Value *WorkGroup = Builder.CreateMul(WorkGroupId, WorkGroupSize); + llvm::Value *GlobalGpuThreadId = Builder.CreateAdd(WorkGroup, GpuThreadId); + + // Check the loop increment + assert(CGM.checkLoopStep(LD.getInc(), LoopVD) && "Loop incr check failed"); + + // Handle stride + GlobalGpuThreadId = applyNoLoopInc(LD.getInc(), LoopVD, GlobalGpuThreadId); + + // Generate my_index = my_index + myid. Note that my_index was already + // initialized + llvm::Value *Gtid = + Builder.CreateIntCast(GlobalGpuThreadId, IvAddr.getElementType(), false); + + llvm::Value *Iv = nullptr; + if (CGM.isMultiDeviceKernel(&FStmt)) { + Iv = Builder.CreateAdd( + Gtid, + Builder.CreateIntCast(Builder.CreateLoad(GetAddrOfLocalVar((*Args)[1])), + IvAddr.getElementType(), false)); + } else { + Iv = Builder.CreateAdd(Gtid, Builder.CreateLoad(IvAddr)); + } + + if (CGM.isXteamRedKernel(&FStmt)) { + // Cache the thread specific initial loop iteration value and the number of + // teams + llvm::Value *NumTeams = RT.getGPUNumBlocks(*this); + CGM.updateXteamRedKernel(&FStmt, Builder.CreateIntCast(Iv, Int64Ty, false), + NumTeams); + } + // Set the initial value of the loop iteration + Builder.CreateStore(Iv, IvAddr); + + return std::make_pair(LoopVD, IvAddr); +} + +void CodeGenFunction::EmitBigJumpLoopUpdates(const ForStmt &FStmt) { + const CodeGenModule::OptKernelNestDirectives &Directives = + CGM.isXteamRedKernel(&FStmt) ? CGM.getXteamRedNestDirs(&FStmt) + : CGM.getBigJumpLoopNestDirs(&FStmt); + assert(Directives.size() > 0 && isa(Directives.back()) && + "Appropriate directive not found"); + const OMPLoopDirective &LD = *(cast(Directives.back())); + // Emit updates of the original loop indices + for (const Expr *UE : LD.updates()) + EmitIgnoredExpr(UE); +} + +void CodeGenFunction::EmitBigJumpLoopInc(const ForStmt &FStmt, + const VarDecl *LoopVD, + const Address &NoLoopIvAddr) { + const CodeGenModule::OptKernelNestDirectives &Directives = + CGM.isXteamRedKernel(&FStmt) ? CGM.getXteamRedNestDirs(&FStmt) + : CGM.getBigJumpLoopNestDirs(&FStmt); + assert(Directives.size() > 0 && isa(Directives.back()) && + "Appropriate directive not found"); + const OMPLoopDirective &LD = *(cast(Directives.back())); + + auto &RT = static_cast(CGM.getOpenMPRuntime()); + llvm::Value *BlockSize = RT.getGPUNumThreads(*this); + llvm::Value *NumBlocks = CGM.isXteamRedKernel(&FStmt) + ? CGM.getXteamRedNumTeams(&FStmt) + : RT.getGPUNumBlocks(*this); + assert(NumBlocks && "Number of blocks cannot be null"); + // prod = block_size * num_blocks + llvm::Value *Prod = Builder.CreateMul(BlockSize, NumBlocks); + + // Check the loop increment + assert(CGM.checkLoopStep(LD.getInc(), LoopVD) && "Loop incr check failed"); + + // Handle stride + Prod = applyNoLoopInc(LD.getInc(), LoopVD, Prod); + + // *iv = *iv + prod + llvm::Value *ProdRes = + Builder.CreateIntCast(Prod, NoLoopIvAddr.getElementType(), false); + llvm::Value *NoLoopInc = + Builder.CreateAdd(ProdRes, Builder.CreateLoad(NoLoopIvAddr)); + Builder.CreateStore(NoLoopInc, NoLoopIvAddr); +} + +std::pair +CodeGenFunction::EmitNoLoopIV(const OMPLoopDirective &LD, + const FunctionArgList *Args) { + // Emit the original loop indices + for (const Expr *CE : LD.counters()) { + const auto *CEDecl = cast(cast(CE)->getDecl()); + if (!hasAddrOfLocalVar(CEDecl)) { + if (CEDecl->hasLocalStorage()) + EmitVarDecl(*CEDecl); + else { + llvm::Type *CEDeclType = ConvertTypeForMem(CEDecl->getType()); + llvm::AllocaInst *LocalForGlobal = + Builder.CreateAlloca(CEDeclType, nullptr, "lglobal"); + setAddrOfLocalVar(CEDecl, Address(LocalForGlobal, CEDeclType, + getContext().getTypeAlignInChars( + CEDecl->getType()))); + } + } + } + + // Emit the preinits + const DeclStmt *PreInits = cast_or_null(LD.getPreInits()); + if (PreInits) { + for (const auto *I : PreInits->decls()) { + EmitVarDecl(cast(*I)); + } + } + + // Emit the inits of original loop indices + for (const Expr *CIE : LD.inits()) { + EmitIgnoredExpr(CIE); + } + + // Emit the lower and upper bounds + const auto *LBDecl = + cast(cast(LD.getLowerBoundVariable())->getDecl()); + EmitVarDecl(*LBDecl); + + const auto *UBDecl = + cast(cast(LD.getUpperBoundVariable())->getDecl()); + EmitVarDecl(*UBDecl); + + // Emit the iteration variable of the loop + const auto *IVDecl = + cast(cast(LD.getIterationVariable())->getDecl()); + EmitVarDecl(*IVDecl); + + // Emit init of the iteration variable + EmitIgnoredExpr(LD.getInit()); + + // If multi-device targets are enabled, overwrite the LB and UB + // initialization with the values passed in as arguments in positions 1 and 2 + // respectively: + if (CGM.isMultiDeviceKernel(LD)) { + llvm::Value *LBMultiTarget = Builder.CreateIntCast( + Builder.CreateLoad(GetAddrOfLocalVar((*Args)[1])), + GetAddrOfLocalVar(IVDecl).getElementType(), false); + Builder.CreateStore(LBMultiTarget, GetAddrOfLocalVar(LBDecl)); + Builder.CreateStore(LBMultiTarget, GetAddrOfLocalVar(IVDecl)); + llvm::Value *UBMultiTarget = Builder.CreateIntCast( + Builder.CreateLoad(GetAddrOfLocalVar((*Args)[2])), + GetAddrOfLocalVar(IVDecl).getElementType(), false); + Builder.CreateStore(UBMultiTarget, GetAddrOfLocalVar(UBDecl)); + } + + return std::make_pair(IVDecl, GetAddrOfLocalVar(IVDecl)); +} + +const CodeGenModule::OptKernelNestDirectives & +CodeGenModule::getOptKernelDirectives( + const ForStmt *CapturedForStmt, + llvm::omp::OMPTgtExecModeFlags OptKernelMode) { + assert(OptKernelMode == + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP || + OptKernelMode == llvm::omp::OMPTgtExecModeFlags:: + OMP_TGT_EXEC_MODE_SPMD_BIG_JUMP_LOOP || + OptKernelMode == + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_XTEAM_RED); + if (OptKernelMode == + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP) + return getNoLoopNestDirs(CapturedForStmt); + if (OptKernelMode == + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_BIG_JUMP_LOOP) + return getBigJumpLoopNestDirs(CapturedForStmt); + return getXteamRedNestDirs(CapturedForStmt); +} + +void CodeGenFunction::EmitOptKernel( + const OMPExecutableDirective &D, const ForStmt *CapturedForStmt, + llvm::omp::OMPTgtExecModeFlags OptKernelMode, SourceLocation Loc, + const FunctionArgList *Args) { + if (!HaveInsertPoint()) + EnsureInsertPoint(); + + assert(CapturedForStmt && "Cannot generate kernel for null captured stmt"); + const CodeGenModule::OptKernelNestDirectives &NestDirs = + CGM.getOptKernelDirectives(CapturedForStmt, OptKernelMode); + + // We support at most 3 levels of nesting. + assert((NestDirs.size() > 0 && NestDirs.size() < 4) && + "Unexpected number of nested directives for optimized kernel codegen"); + + // No private scope must be destroyed before the kernel codegen is done. + if (NestDirs.size() == 1) { + OMPPrivateScope PrivateScope(*this); + EmitOMPFirstprivateClause(*NestDirs[0], PrivateScope); + EmitOMPPrivateClause(*NestDirs[0], PrivateScope); + (void)PrivateScope.Privatize(); + + EmitOptKernelCode(*NestDirs[0], CapturedForStmt, OptKernelMode, Loc, Args); + } else if (NestDirs.size() == 2) { + OMPPrivateScope PrivateScopeZero(*this); + EmitOMPFirstprivateClause(*NestDirs[0], PrivateScopeZero); + EmitOMPPrivateClause(*NestDirs[0], PrivateScopeZero); + (void)PrivateScopeZero.Privatize(); + + OMPPrivateScope PrivateScopeOne(*this); + EmitOMPFirstprivateClause(*NestDirs[1], PrivateScopeOne); + EmitOMPPrivateClause(*NestDirs[1], PrivateScopeOne); + (void)PrivateScopeOne.Privatize(); + + EmitOptKernelCode(*NestDirs[1], CapturedForStmt, OptKernelMode, Loc, Args); + } else { + OMPPrivateScope PrivateScopeZero(*this); + EmitOMPFirstprivateClause(*NestDirs[0], PrivateScopeZero); + EmitOMPPrivateClause(*NestDirs[0], PrivateScopeZero); + (void)PrivateScopeZero.Privatize(); + + OMPPrivateScope PrivateScopeOne(*this); + EmitOMPFirstprivateClause(*NestDirs[1], PrivateScopeOne); + EmitOMPPrivateClause(*NestDirs[1], PrivateScopeOne); + (void)PrivateScopeOne.Privatize(); + + OMPPrivateScope PrivateScopeTwo(*this); + EmitOMPFirstprivateClause(*NestDirs[2], PrivateScopeTwo); + EmitOMPPrivateClause(*NestDirs[2], PrivateScopeTwo); + (void)PrivateScopeTwo.Privatize(); + + EmitOptKernelCode(*NestDirs[2], CapturedForStmt, OptKernelMode, Loc, Args); + } +} + +void CodeGenFunction::EmitOptKernelCode( + const OMPExecutableDirective &D, const ForStmt *CapturedForStmt, + llvm::omp::OMPTgtExecModeFlags OptKernelMode, SourceLocation Loc, + const FunctionArgList *Args) { + assert(OptKernelMode == + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP || + OptKernelMode == llvm::omp::OMPTgtExecModeFlags:: + OMP_TGT_EXEC_MODE_SPMD_BIG_JUMP_LOOP || + OptKernelMode == + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_XTEAM_RED); + if (OptKernelMode == + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP) + EmitNoLoopCode(D, CapturedForStmt, Loc, Args); + else if (OptKernelMode == + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_BIG_JUMP_LOOP) + EmitBigJumpLoopCode(D, CapturedForStmt, Loc, Args); + else + EmitXteamRedCode(D, CapturedForStmt, Loc, Args); +} + +void CodeGenFunction::EmitNoLoopCode(const OMPExecutableDirective &D, + const ForStmt *CapturedForStmt, + SourceLocation Loc, + const FunctionArgList *Args) { + assert(isa(D) && "Unexpected directive"); + + const OMPLoopDirective &LD = cast(D); + auto &RT = static_cast(CGM.getOpenMPRuntime()); + + // Initialize a specialized kernel. + RT.initSpecializedKernel(*this); + + auto IVPair = EmitNoLoopIV(LD, Args); + const VarDecl *IVDecl = IVPair.first; + Address IvAddr = IVPair.second; + + // Generate myid = workgroup_id * workgroup_size + workitem_id + // workitem_id + llvm::Value *GpuThreadId = RT.getGPUThreadID(*this); + + // workgroup_size + assert(CGM.isNoLoopKernel(D) && "Unexpected optimized kernel type"); + llvm::Value *WorkGroupSize = RT.getGPUNumThreads(*this); + + // workgroup_id + llvm::Value *WorkGroupId = RT.getGPUBlockID(*this); + + llvm::Value *WorkGroup = Builder.CreateMul(WorkGroupId, WorkGroupSize); + llvm::Value *GlobalGpuThreadId = Builder.CreateAdd(WorkGroup, GpuThreadId); + + // Check the loop increment + assert(CGM.checkLoopStep(LD.getInc(), IVDecl) && "Loop incr check failed"); + + // Handle stride + GlobalGpuThreadId = applyNoLoopInc(LD.getInc(), IVDecl, GlobalGpuThreadId); + + // Generate my_index = my_index + myid. Note that my_index was already + // initialized + llvm::Value *Gtid = + Builder.CreateIntCast(GlobalGpuThreadId, IvAddr.getElementType(), false); + if (CGM.isMultiDeviceKernel(D)) { + llvm::Value *Iv = Builder.CreateAdd( + Gtid, + Builder.CreateIntCast(Builder.CreateLoad(GetAddrOfLocalVar((*Args)[1])), + IvAddr.getElementType(), false)); + Builder.CreateStore(Iv, IvAddr); + } else { + llvm::Value *Iv = Builder.CreateAdd(Gtid, Builder.CreateLoad(IvAddr)); + Builder.CreateStore(Iv, IvAddr); + } + + // Emit updates of the original loop indices + for (const Expr *UE : LD.updates()) + EmitIgnoredExpr(UE); + + // Branch to end if original loop condition not satisfied + llvm::Value *IvCmp = EvaluateExprAsBool(LD.getCond()); + + llvm::BasicBlock *ExecBB = createBasicBlock("omp.kernel.body"); + llvm::BasicBlock *DoneBB = createBasicBlock("omp.kernel.done"); + + Builder.CreateCondBr(IvCmp, ExecBB, DoneBB); + + // On a continue in the body, jump to the end. + // A break is not allowed in this scope but it would be the end anyways + JumpDest Continue = getJumpDestInCurrentScope(DoneBB); + BreakContinueStack.push_back(BreakContinue(cast(*CapturedForStmt), Continue, Continue)); + + EmitBlock(ExecBB); + + for (const Expr *E : LD.finals_conditions()) { + if (!E) + continue; + // Check that loop counter in non-rectangular nest fits into the iteration + // space. + llvm::BasicBlock *NextBB = createBasicBlock("omp.body.next"); + EmitBranchOnBoolExpr(E, NextBB, Continue.getBlock(), + getProfileCount(LD.getBody())); + EmitBlock(NextBB); + } + + // Emit the kernel body block + EmitOMPNoLoopBody(LD); + EmitBranch(DoneBB); + + EmitBlock(DoneBB); + Builder.CreateRetVoid(); + Builder.ClearInsertionPoint(); + BreakContinueStack.pop_back(); +} + +/// Emit the GlobalGpuThreadId and loop iteration variables using RTL calls and +/// update the Xteam Scan Kernel info +void CodeGenFunction::EmitNoLoopXteamScanInit(const OMPLoopDirective &LD, + const ForStmt *CapturedForStmt, + const FunctionArgList *Args, + llvm::Value *&GpuThreadId, + llvm::Value *&GlobalGpuThreadId, + llvm::Value *&WorkGroupId, + llvm::Value *&TotalNumThreads) { + auto IVPair = EmitNoLoopIV(LD, Args); + Address OMPIterationVarAddr = IVPair.second; + + // Generate: + // GlobalGpuThreadId = (WorkGroupId * WorkGroupSize) + GpuThreadId + auto &RT = static_cast(CGM.getOpenMPRuntime()); + GpuThreadId = RT.getGPUThreadID(*this); + llvm::Value *WorkGroupSize = RT.getGPUNumThreads(*this); + WorkGroupId = RT.getGPUBlockID(*this); + llvm::Value *WorkGroup = Builder.CreateMul(WorkGroupId, WorkGroupSize); + GlobalGpuThreadId = Builder.CreateAdd(WorkGroup, GpuThreadId); + + // Generate: + // omp.iteration.var = omp.iteration.var + GlobalGpuThreadId + // (Note that the omp.iteration.var had been initialized with the lower bound + // of iteration space) + llvm::Value *CastedGlobalGpuThreadId = Builder.CreateIntCast( + GlobalGpuThreadId, OMPIterationVarAddr.getElementType(), false); + llvm::Value *OMPIterationVar = Builder.CreateAdd( + CastedGlobalGpuThreadId, Builder.CreateLoad(OMPIterationVarAddr)); + + // Cache the thread specific initial loop iteration value and the number of + // teams + llvm::Value *NumTeams = RT.getGPUNumBlocks(*this); + CGM.updateXteamRedKernel( + CapturedForStmt, Builder.CreateIntCast(OMPIterationVar, Int64Ty, false), + NumTeams); + TotalNumThreads = + Builder.CreateMul(NumTeams, WorkGroupSize, "total_num_threads"); + Builder.CreateStore(OMPIterationVar, OMPIterationVarAddr); + + // Emit updates of the original loop indices + for (const Expr *UE : LD.updates()) + EmitIgnoredExpr(UE); +} + +/// Emit a NoLoop body for the PhaseOne of Xteam Scan Kernel. This computes +/// the BeforeScanBlock and then generates a call to the DeviceRTL APIs +/// kmpc_xteams* which eventually executes the parallelized cross-team scan +/// algorithm on the GPU. +void CodeGenFunction::EmitNoLoopXteamScanPhaseOneCode( + const OMPExecutableDirective &D, const ForStmt *CapturedForStmt, + SourceLocation Loc, const FunctionArgList *Args) { + assert(isa(D) && "Unexpected directive"); + const OMPLoopDirective &LD = cast(D); + + llvm::Value *GpuThreadId = nullptr; + llvm::Value *GlobalGpuThreadId = nullptr; + llvm::Value *WorkGroupId = nullptr; + llvm::Value *TotalNumThreads = nullptr; + EmitNoLoopXteamScanInit(LD, CapturedForStmt, Args, GpuThreadId, + GlobalGpuThreadId, WorkGroupId, TotalNumThreads); + + // Branch to end if original loop condition not satisfied + llvm::Value *IvCmp = EvaluateExprAsBool(LD.getCond()); + + llvm::BasicBlock *ExecBB = createBasicBlock("omp.kernel.body"); + llvm::BasicBlock *DoneBB = createBasicBlock("omp.kernel.done"); + + Builder.CreateCondBr(IvCmp, ExecBB, DoneBB); + + // On a continue in the body, jump to the end. + // A break is not allowed in this scope but it would be the end anyways + JumpDest Continue = getJumpDestInCurrentScope(DoneBB); + BreakContinueStack.push_back(BreakContinue(cast(*CapturedForStmt), Continue, Continue)); + + // Emit the kernel body block + EmitBlock(ExecBB); + + // Generate the BeforeScanBlock + CodeGenFunction::ParentLoopDirectiveForScanRegion ScanRegion(*this, LD); + { + OMPFirstScanLoop = true; + CodeGenFunction::OMPLocalDeclMapRAII Scope(*this); + EmitOMPXteamScanNoLoopBody(LD); + } + + // Generate call to the DeviceRTL calls kmpc_xteams_* + EmitXteamScanSum(CapturedForStmt, *Args, CGM.getXteamRedBlockSize(D)); + + EmitBranch(DoneBB); + + EmitBlock(DoneBB); + Builder.CreateRetVoid(); + Builder.ClearInsertionPoint(); + BreakContinueStack.pop_back(); +} + +/// Emit a NoLoop body for the PhaseTwo of the Xteam Scan Kernel. This +/// computes the final 'scanned' values for every team using the intermediate +/// results computed by the PhaseOne kernel. These results are stored in the +/// data structures TeamVals[] and Storage[]. +void CodeGenFunction::EmitNoLoopXteamScanPhaseTwoCode( + const OMPExecutableDirective &D, const ForStmt *CapturedForStmt, + SourceLocation Loc, const FunctionArgList *Args) { + assert(isa(D) && "Unexpected directive"); + const OMPLoopDirective &LD = cast(D); + + llvm::Value *GpuThreadId = nullptr; + llvm::Value *GlobalGpuThreadId = nullptr; + llvm::Value *WorkGroupId = nullptr; + llvm::Value *TotalNumThreads = nullptr; + EmitNoLoopXteamScanInit(LD, CapturedForStmt, Args, GpuThreadId, + GlobalGpuThreadId, WorkGroupId, TotalNumThreads); + + const CodeGenModule::XteamRedVarMap &RedVarMap = + CGM.getXteamRedVarMap(CapturedForStmt); + for (auto XteamVD : CGM.getXteamOrderedRedVar(CapturedForStmt)) { + auto Itr = RedVarMap.find(XteamVD); + assert(Itr != RedVarMap.end() && "Metadata not found"); + + const CodeGenModule::XteamRedVarInfo &RVI = Itr->second; + llvm::Type *RedVarType = ConvertTypeForMem(XteamVD->getType()); + + assert(RVI.ArgPos + 1 < Args->size() && "Arg position beyond bounds"); + + Address XteamRedSumArg1 = GetAddrOfLocalVar((*Args)[RVI.ArgPos]); + llvm::Value *DTeamVals = Builder.CreateLoad(XteamRedSumArg1); + (void)DTeamVals; + + Address XteamRedSumArg3 = GetAddrOfLocalVar((*Args)[RVI.ArgPos + 2]); + llvm::Value *DScanStorage = Builder.CreateLoad(XteamRedSumArg3); + + EmitXteamScanPhaseTwo( + CapturedForStmt, /*SegmentSize=*/Builder.getInt32(1), *Args, + CGM.getXteamRedBlockSize(D), + CGM.OMPPresentScanDirective->hasClausesOfKind()); + + // Emit: RedVar = Storage[Offset + GlobalTID] + // The offset is calculated to index into the second half of the Storage[] + // data structure. + llvm::Value *StorageOffset = + Builder.CreateAdd(GlobalGpuThreadId, TotalNumThreads); + Address ScanStorageValGEP = Address( + Builder.CreateGEP(RedVarType, DScanStorage, StorageOffset), RedVarType, + getContext().getTypeAlignInChars( + XteamVD->getType())); // Storage[Offset + GlobalTID] + Builder.CreateStore(Builder.CreateLoad(ScanStorageValGEP), RVI.RedVarAddr); + } + + // After the 'scanned' results are put in the respective private copies, the + // AfterScanBlock can be generated which will consume these results. + CodeGenFunction::ParentLoopDirectiveForScanRegion ScanRegion(*this, LD); + OMPFirstScanLoop = false; + EmitOMPXteamScanNoLoopBody(LD); + CGM.OMPPresentScanDirective = nullptr; +} + +void CodeGenFunction::EmitBigJumpLoopCode(const OMPExecutableDirective &D, + const ForStmt *CapturedForStmt, + SourceLocation Loc, + const FunctionArgList *Args) { + auto &RT = static_cast(CGM.getOpenMPRuntime()); + // Initialize a specialized kernel. + RT.initSpecializedKernel(*this); + + // Add pre-processing code from start of EmitStmt function so that the + // code path is identical. + assert(CapturedForStmt && "Null statement?"); + PGO->setCurrentStmt(CapturedForStmt); + + // These statements have their own debug info handling. + if (EmitSimpleStmt(CapturedForStmt, nullptr)) + return; + + // Check if we are generating unreachable code. + if (!HaveInsertPoint()) { + if (!ContainsLabel(CapturedForStmt)) + return; + + // Otherwise, make a new block to hold the code. + EnsureInsertPoint(); + } + + // Generate a stoppoint if we are emitting debug info. + EmitStopPoint(CapturedForStmt); + + // Ignore all OpenMP directives except for simd if OpenMP with Simd is + // enabled. + if (getLangOpts().OpenMP && getLangOpts().OpenMPSimd) { + if (const auto *D = dyn_cast(CapturedForStmt)) { + EmitSimpleOMPExecutableDirective(*D); + return; + } + } + + // Call variant with Args: + EmitForStmtWithArgs(cast(*CapturedForStmt), Args); +} + +void CodeGenFunction::EmitXteamRedCode(const OMPExecutableDirective &D, + const ForStmt *CapturedForStmt, + SourceLocation Loc, + const FunctionArgList *Args) { + // This is the top level ForStmt for which Xteam reduction code is being + // generated + CGM.setCurrentXteamRedStmt(CapturedForStmt); + + auto &RT = static_cast(CGM.getOpenMPRuntime()); + + // Initialize a specialized kernel. + RT.initSpecializedKernel(*this); + + EmitXteamLocalAggregator(CapturedForStmt); + + if (CGM.isXteamScanKernel()) { + // Note about the two Xteam Scan Kernel variants: + // + // 1. Segmented Scan Kernel: This is the default Xteam Scan kernel that will + // be generated. + // + // 2. NoLoop Scan Kernel: This is a special case when the number of + // iterations in the captured 'For' Stmt(i.e. total number of elements in + // the input array that has to be scanned) is smaller than or equal to + // the total number of parallel work-items available during the kernel + // execution. This will generate a more time and space efficient kernel + // for this case. + // + if (CGM.isXteamSegmentedScanKernel()) { + // Follow the Xteam Segmented Scan Kernel Codegen + EmitForStmtWithArgs(cast(*CapturedForStmt), Args); + // Toggle the Phase number(1 or 2) after emitting any of the phases + CGM.isXteamScanPhaseOne = !CGM.isXteamScanPhaseOne; + } else if (CGM.isXteamScanPhaseOne) { + // Follow the Xteam NoLoop Scan Kernel Codegen - Phase 1 + EmitNoLoopXteamScanPhaseOneCode(D, CapturedForStmt, Loc, Args); + CGM.isXteamScanPhaseOne = false; + } else { + // Follow the Xteam NoLoop Scan Kernel Codegen - Phase 2 + EmitNoLoopXteamScanPhaseTwoCode(D, CapturedForStmt, Loc, Args); + CGM.isXteamScanPhaseOne = true; + } + } else { + // Now emit the modified loop. If there is a statement in the loop with a + // reduction, the reduction variable will be replaced with the local + // aggregator variable. + EmitForStmtWithArgs(cast(*CapturedForStmt), Args); + // EmitStmt(CapturedForStmt); + + // Now emit the calls to xteam_sum, one for each reduction variable + EmitXteamRedOperation(CapturedForStmt, *Args, CGM.getXteamRedBlockSize(D)); + } + + // Xteam codegen done + CGM.setCurrentXteamRedStmt(nullptr); +} + +/// If the provided For Stmt has metadata for reduction variables, emit +/// an initializer for each of them +void CodeGenFunction::EmitXteamLocalAggregator(const ForStmt *FStmt) { + const CodeGenModule::XteamRedVarMap &RedVarMap = CGM.getXteamRedVarMap(FStmt); + auto XteamOrdVars = CGM.getXteamOrderedRedVar(FStmt); + // Always emit thread-local reduction variables in the same order as + // user-specified reduction variables. + for (auto XteamVD : XteamOrdVars) { + auto Itr = RedVarMap.find(XteamVD); + assert(Itr != RedVarMap.end() && "Metadata not found"); + const Expr *RedVarExpr = Itr->second.RedVarExpr; + llvm::Type *RedVarType = ConvertTypeForMem(RedVarExpr->getType()); + assert((RedVarType->isFloatTy() || RedVarType->isDoubleTy() || + RedVarType->isHalfTy() || RedVarType->isBFloatTy() || + RedVarType->isIntegerTy()) && + "Unhandled type"); + llvm::AllocaInst *XteamRedInst = Builder.CreateAlloca(RedVarType); + // The initial value (referred to as the sentinel value) of the local + // reduction variable depends on the opcode. + llvm::Value *InitVal = getXteamRedSentinel(RedVarType, Itr->second.Opcode); + Address XteamRedVarAddr( + XteamRedInst, RedVarType, + getContext().getTypeAlignInChars(RedVarExpr->getType())); + Builder.CreateStore(InitVal, XteamRedVarAddr); + + // Update the map with the local aggregator address + // TODO update only the address, the expression is already there + // TODO don't do a lookup again, use the element avail here + CGM.updateXteamRedVarMap(FStmt, XteamVD, RedVarExpr, XteamRedVarAddr); + } +} + +llvm::Value * +CodeGenFunction::getXteamRedSentinel(llvm::Type *RedVarType, + CodeGenModule::XteamRedOpKind Opcode) { + assert((RedVarType->isFloatTy() || RedVarType->isDoubleTy() || + RedVarType->isHalfTy() || RedVarType->isBFloatTy() || + RedVarType->isIntegerTy()) && + "Unhandled type"); + assert(Opcode != CodeGenModule::XR_OP_unknown && + "Unexpected Xteam reduction opcode"); + if (RedVarType->isFloatTy() || RedVarType->isDoubleTy() || + RedVarType->isHalfTy() || RedVarType->isBFloatTy()) { + if (Opcode == CodeGenModule::XR_OP_add) + return llvm::ConstantFP::getZero(RedVarType); + else if (Opcode == CodeGenModule::XR_OP_min) + return llvm::ConstantFP::getInfinity(RedVarType); + else // max operator + return llvm::ConstantFP::getInfinity(RedVarType, /*Negative=*/true); + } else { + // Integer type + if (RedVarType->getPrimitiveSizeInBits() == 16) + return llvm::ConstantInt::get(Int16Ty, + Opcode == CodeGenModule::XR_OP_add ? 0 + : Opcode == CodeGenModule::XR_OP_min + ? std::numeric_limits::max() + : std::numeric_limits::min()); + else if (RedVarType->getPrimitiveSizeInBits() == 32) + return llvm::ConstantInt::get(Int32Ty, + Opcode == CodeGenModule::XR_OP_add ? 0 + : Opcode == CodeGenModule::XR_OP_min + ? std::numeric_limits::max() + : std::numeric_limits::min()); + else { + assert(RedVarType->getPrimitiveSizeInBits() == 64 && + "Expected a 64-bit integer"); + return llvm::ConstantInt::get(Int64Ty, + Opcode == CodeGenModule::XR_OP_add ? 0 + : Opcode == CodeGenModule::XR_OP_min + ? std::numeric_limits::max() + : std::numeric_limits::min()); + } + } + llvm_unreachable( + "Unexpected type or opcode in Xteam reduction sentinel generation"); +} + +// Emit a call to the DeviceRTL Xteam reduction function for each reduction +// variable in the helper map for the given For Stmt. +void CodeGenFunction::EmitXteamRedOperation(const ForStmt *FStmt, + const FunctionArgList &Args, + int BlockSize) { + auto &RT = static_cast(CGM.getOpenMPRuntime()); + const CodeGenModule::XteamRedVarMap &RedVarMap = CGM.getXteamRedVarMap(FStmt); + + llvm::Value *ThreadStartIdx = CGM.getXteamRedThreadStartIndex(FStmt); + assert(ThreadStartIdx && "Thread start index cannot be null"); + llvm::Value *NumTeams = CGM.getXteamRedNumTeams(FStmt); + assert(NumTeams && "Number of teams cannot be null"); + + bool IsFast = CGM.isXteamRedFast(FStmt); + auto XteamOrdVars = CGM.getXteamOrderedRedVar(FStmt); + // Always emit calls to Xteam device functions in the same order as + // user-specified reduction variables. + for (auto XteamVD : XteamOrdVars) { + auto Itr = RedVarMap.find(XteamVD); + assert(Itr != RedVarMap.end() && "Metadata not found"); + + const CodeGenModule::XteamRedVarInfo &RVI = Itr->second; + + assert(RVI.ArgPos + 1 < Args.size() && "Arg position beyond bounds"); + + Address XteamRedSumArg1 = GetAddrOfLocalVar(Args[RVI.ArgPos]); + llvm::Value *DTeamVals = Builder.CreateLoad(XteamRedSumArg1); + + Address XteamRedSumArg2 = GetAddrOfLocalVar(Args[RVI.ArgPos + 1]); + llvm::Value *DTeamsDonePtr = Builder.CreateLoad(XteamRedSumArg2); + + const Expr *OrigRedVarExpr = RVI.RedVarExpr; + const DeclRefExpr *DRE = cast(OrigRedVarExpr); + Address OrigRedVarAddr = EmitLValue(DRE).getAddress(); + // Note that fast Xteam reduction is available only for sum operator. + RT.getXteamRedOperation(*this, Builder.CreateLoad(RVI.RedVarAddr), + OrigRedVarAddr.emitRawPointer(*this), DTeamVals, + DTeamsDonePtr, ThreadStartIdx, NumTeams, BlockSize, + RVI.Opcode, + IsFast && RVI.Opcode == CodeGenModule::XR_OP_add); + } +} + +void CodeGenFunction::EmitXteamScanSum(const ForStmt *FStmt, + const FunctionArgList &Args, + int BlockSize) { + auto &RT = static_cast(CGM.getOpenMPRuntime()); + const CodeGenModule::XteamRedVarMap &RedVarMap = CGM.getXteamRedVarMap(FStmt); + + llvm::Value *ThreadStartIdx = CGM.getXteamRedThreadStartIndex(FStmt); + assert(ThreadStartIdx && "Thread start index cannot be null"); + llvm::Value *NumTeams = CGM.getXteamRedNumTeams(FStmt); + assert(NumTeams && "Number of teams cannot be null"); + + bool IsFast = CGM.isXteamRedFast(FStmt); + auto XteamOrdVars = CGM.getXteamOrderedRedVar(FStmt); + // Always emit calls to Xteam device functions in the same order as + // user-specified reduction variables. + for (auto XteamVD : XteamOrdVars) { + auto Itr = RedVarMap.find(XteamVD); + assert(Itr != RedVarMap.end() && "Metadata not found"); + + const CodeGenModule::XteamRedVarInfo &RVI = Itr->second; + + assert(RVI.ArgPos + 1 < Args.size() && "Arg position beyond bounds"); + + Address XteamRedSumArg1 = GetAddrOfLocalVar(Args[RVI.ArgPos]); + llvm::Value *DTeamVals = Builder.CreateLoad(XteamRedSumArg1); + + Address XteamRedSumArg2 = GetAddrOfLocalVar(Args[RVI.ArgPos + 1]); + llvm::Value *DTeamsDonePtr = Builder.CreateLoad(XteamRedSumArg2); + + Address XteamRedSumArg3 = GetAddrOfLocalVar(Args[RVI.ArgPos + 2]); + llvm::Value *DScanStorage = Builder.CreateLoad(XteamRedSumArg3); + + const Expr *OrigRedVarExpr = RVI.RedVarExpr; + const DeclRefExpr *DRE = cast(OrigRedVarExpr); + Address OrigRedVarAddr = EmitLValue(DRE).getAddress(); + RT.getXteamScanSum(*this, Builder.CreateLoad(RVI.RedVarAddr), + OrigRedVarAddr.emitRawPointer(*this), DTeamVals, + DTeamsDonePtr, DScanStorage, ThreadStartIdx, NumTeams, + BlockSize, IsFast); + } +} + +/// Emit calls to the DeviceRTL implementations(__kmpc_xteams_phase2_*) for +/// computing the phase two of segmented Xteam scan. +void CodeGenFunction::EmitXteamScanPhaseTwo(const ForStmt *FStmt, + llvm::Value *SegmentSize, + const FunctionArgList &Args, + int BlockSize, + bool IsInclusiveScan) { + auto &RT = static_cast(CGM.getOpenMPRuntime()); + const CodeGenModule::XteamRedVarMap &RedVarMap = CGM.getXteamRedVarMap(FStmt); + + llvm::Value *ThreadStartIdx = CGM.getXteamRedThreadStartIndex(FStmt); + assert(ThreadStartIdx && "Thread start index cannot be null"); + + auto XteamOrdVars = CGM.getXteamOrderedRedVar(FStmt); + // Always emit calls to Xteam device functions in the same order as + // user-specified reduction variables. + for (auto XteamVD : XteamOrdVars) { + auto Itr = RedVarMap.find(XteamVD); + assert(Itr != RedVarMap.end() && "Metadata not found"); + + const CodeGenModule::XteamRedVarInfo &RVI = Itr->second; + + assert(RVI.ArgPos + 1 < Args.size() && "Arg position beyond bounds"); + + Address XteamRedSumArg1 = GetAddrOfLocalVar(Args[RVI.ArgPos]); + llvm::Value *DTeamVals = Builder.CreateLoad(XteamRedSumArg1); + + Address XteamRedSumArg2 = GetAddrOfLocalVar(Args[RVI.ArgPos + 2]); + llvm::Value *DScanStorage = Builder.CreateLoad(XteamRedSumArg2); + + llvm::Value *DSegmentVals = nullptr; + if (CGM.isXteamSegmentedScanKernel()) { + Address XteamRedSumArg3 = GetAddrOfLocalVar(Args[RVI.ArgPos + 3]); + DSegmentVals = Builder.CreateLoad(XteamRedSumArg3); + } else { + // For No-Loop Scan, the SegmentVals[] is not required and therefore was + // not created in the first place. Here we want to use the same + // kmpc_xteams_phase2* API to compute Phase 2 of scan, therefore we're + // passing the pointer of Storage[] as a dummy ptr. + DSegmentVals = DScanStorage; + } + + RT.getXteamScanPhaseTwo(*this, Builder.CreateLoad(RVI.RedVarAddr), + SegmentSize, DTeamVals, DScanStorage, DSegmentVals, + ThreadStartIdx, BlockSize, IsInclusiveScan); + } +} + +bool CodeGenFunction::EmitXteamRedStmt(const Stmt *S) { + if (CGM.getCurrentXteamRedStmt() == nullptr) + return false; + if (!isa(S) && !isa(S)) + return false; + + auto getLocalRedVarPointer = + [this](const Expr *E, + const CodeGenModule::XteamRedVarMap &RVM) -> llvm::Value * { + if (!isa(E)) + return nullptr; + const ValueDecl *ValDecl = cast(E)->getDecl(); + if (!isa(ValDecl)) + return nullptr; + const VarDecl *VD = cast(ValDecl); + if (RVM.find(VD) == RVM.end()) + return nullptr; + return RVM.find(VD)->second.RedVarAddr.emitRawPointer(*this); + }; + + const CodeGenModule::XteamRedVarMap &RedVarMap = + CGM.getXteamRedVarMap(CGM.getCurrentXteamRedStmt()); + + // Currently, there is limited support in Xteam reduction for calls with + // reduction variables in arguments. Either the call has to be at the + // statement level or it has to be a call to a builtin function (e.g. min/max) + // on the rhs of an assignment statement. Handle call at the statement level. + if (isa(S)) { + const CallExpr *CE = cast(S); + assert(CE && "Unexpected null call expression"); + + // First check if the call references any reduction variable. Otherwise, + // let the caller handle it. + bool FoundRedVar = false; + for (unsigned ArgIndex = 0; ArgIndex < CE->getNumArgs(); ++ArgIndex) + if (CGM.hasXteamRedVar(CE->getArg(ArgIndex), RedVarMap)) { + FoundRedVar = true; + break; + } + if (!FoundRedVar) + return false; // Let the caller handle the call expression. + + // Generate the call with the reduction variable reference replaced by a + // reference to the corresponding local variable. + CallArgList CallArgs; + for (unsigned ArgIndex = 0; ArgIndex < CE->getNumArgs(); ++ArgIndex) { + const Expr *Arg = CE->getArg(ArgIndex); + llvm::Value *LocalRedVar = getLocalRedVarPointer(Arg, RedVarMap); + if (LocalRedVar != nullptr) { + // Add any required cast for the reduction variable. + llvm::Value *LRV = Builder.CreatePointerBitCastOrAddrSpaceCast( + LocalRedVar, CGM.getTypes().ConvertTypeForMem( + getContext().getPointerType(Arg->getType()))); + CallArgs.add(RValue::get(LRV), + getContext().getPointerType(Arg->getType())); + } else { + assert(hasScalarEvaluationKind(Arg->getType()) && + "Expected scalar type in call arg"); + CallArgs.add(RValue::get(EmitScalarExpr(Arg)), Arg->getType()); + } + } + const CGFunctionInfo &FI = + CGM.getTypes().arrangeBuiltinFunctionCall(CE->getType(), CallArgs); + // The earlier analysis ensures there is no use of return value. + EmitCall(FI, EmitCallee(CE->getCallee()), ReturnValueSlot(), CallArgs); + return true; + } // End of call expression handling. + + const BinaryOperator *RedBO = cast(S); + // Is a reduction variable the lhs? + const VarDecl *RedVarDecl = + CGM.getXteamRedVarDecl(RedBO->getLHS()->IgnoreImpCasts(), RedVarMap); + if (RedVarDecl == nullptr) { + if (CGM.isXteamScanKernel() && !CGM.isXteamScanPhaseOne) { + // For Xteam Scan: check if the RHS has any xteam reduction variable + // access + const VarDecl *RHSRedVarDecl = + CGM.getXteamRedVarDecl(RedBO->getRHS()->IgnoreImpCasts(), RedVarMap); + if (RHSRedVarDecl == nullptr) + return false; // neither RHS nor LHS has reduction vars + assert(RedBO->getOpcode() == BO_Assign && + "Unexpected operator during Xteam Scan CodeGen"); + auto LHSCodegen = EmitLValue(RedBO->getLHS()); + Address RHSXteamRedLocalAddr = + RedVarMap.find(RHSRedVarDecl)->second.RedVarAddr; + Builder.CreateStore(Builder.CreateLoad(RHSXteamRedLocalAddr), + LHSCodegen.getAddress()); + // Emit: lhs_expr = *xteam_local_red_var_addr + return true; + } + // The analysis made sure that the statement did not access the reduction + // variable, so there is nothing to do. + return false; + } + + // For now, we handle only sum reduction + assert( + (RedBO->getOpcode() == BO_AddAssign || RedBO->getOpcode() == BO_Assign) && + "Unexpected operator during Xteam CodeGen"); + + // Extract the rhs for the reduction. + const Expr *RedRHSExpr = nullptr; + auto OpcRedBO = RedBO->getOpcode(); + if (OpcRedBO == BO_AddAssign) { + RedRHSExpr = RedBO->getRHS()->IgnoreImpCasts(); + } else { + const Expr *L1RhsExpr = RedBO->getRHS()->IgnoreImpCasts(); + assert((isa(L1RhsExpr) || isa(L1RhsExpr) || + isa(L1RhsExpr)) && + "Expected rhs to be a binary operator"); + if (isa(L1RhsExpr)) { + const BinaryOperator *L2BO = cast(L1RhsExpr); + auto OpcL2BO = L2BO->getOpcode(); + assert(OpcL2BO == BO_Add && "Unexpected operator"); + // If the redvar is lhs, use the rhs in the generated reduction statement + // and vice-versa. + if (CGM.isXteamRedVarExpr(L2BO->getLHS()->IgnoreImpCasts(), RedVarDecl)) + RedRHSExpr = L2BO->getRHS(); + else if (CGM.isXteamRedVarExpr(L2BO->getRHS()->IgnoreImpCasts(), + RedVarDecl)) + RedRHSExpr = L2BO->getLHS(); + else + llvm_unreachable("Unhandled add expression during xteam reduction"); + } else if (isa(L1RhsExpr)) { + const CallExpr *Call = cast(L1RhsExpr); + assert(CGM.getStatusOptKernelBuiltin(Call) == CodeGenModule::NxSuccess && + "Expected a call to an Xteam supported builtin"); + EmitXteamRedStmtForBuiltinCall(Call, RedVarDecl, RedVarMap); + return true; + } else { + assert(isa(L1RhsExpr) && "Expected a PseudoObjectExpr"); + auto [Status, ReturnExpr] = CGM.getStatusXteamSupportedPseudoObject( + cast(L1RhsExpr)); + assert(Status == CodeGenModule::NxSuccess && + "Expected call expression from analysis of PseudoObjectExpr"); + const CallExpr *Call = cast(ReturnExpr); + assert(CGM.getStatusOptKernelBuiltin(Call) == CodeGenModule::NxSuccess && + "Expected a call to an Xteam supported builtin"); + EmitXteamRedStmtForBuiltinCall(Call, RedVarDecl, RedVarMap); + return true; + } + } + assert(RedRHSExpr != nullptr && "Did not find a valid reduction rhs"); + + EmitLocalReductionStmt(RedRHSExpr, RedVarDecl, RedVarMap, + CodeGenModule::XR_OP_add); + return true; +} + +void CodeGenFunction::EmitLocalReductionStmt( + const Expr *E, const VarDecl *RedVarDecl, + const CodeGenModule::XteamRedVarMap &RedVarMap, + CodeGenModule::XteamRedOpKind OpKind) { + // For add, generate *xteam_local = *xteam_local + rhs_value + // For min/max, generate *xteam_local = min/max(*xteam_local, other_operand) + + // First, generate the other operand. + llvm::Value *RHSValue = EmitScalarExpr(E); + // Now handle the local reduction variable accesses. + auto It = RedVarMap.find(RedVarDecl); + assert(It != RedVarMap.end() && "Variable must be found in reduction map"); + Address XteamRedLocalAddr = It->second.RedVarAddr; + llvm::Type *RedVarType = ConvertTypeForMem(It->second.RedVarExpr->getType()); + llvm::Value *Op1 = Builder.CreateLoad(XteamRedLocalAddr); + llvm::Value *RedRHS = nullptr; + if (RedVarType->isFloatTy() || RedVarType->isDoubleTy() || + RedVarType->isHalfTy() || RedVarType->isBFloatTy()) { + auto Op2 = RHSValue->getType()->isIntegerTy() + ? Builder.CreateSIToFP(RHSValue, RedVarType) + : Builder.CreateFPCast(RHSValue, RedVarType); + if (OpKind == CodeGenModule::XR_OP_add) + RedRHS = Builder.CreateFAdd(Op1, Op2); + else if (OpKind == CodeGenModule::XR_OP_min) + RedRHS = + Builder.CreateMinNum(Op1, Op2, /*FMFSource=*/nullptr, "xteam.min"); + else if (OpKind == CodeGenModule::XR_OP_max) + RedRHS = + Builder.CreateMaxNum(Op1, Op2, /*FMFSource=*/nullptr, "xteam.max"); + else + llvm_unreachable("Unexpected reduction kind"); + } else if (RedVarType->isIntegerTy()) { + auto Op2 = RHSValue->getType()->isIntegerTy() + ? Builder.CreateIntCast(RHSValue, RedVarType, false) + : Builder.CreateFPToSI(RHSValue, RedVarType); + if (OpKind == CodeGenModule::XR_OP_add) + RedRHS = Builder.CreateAdd(Op1, Op2); + else if (OpKind == CodeGenModule::XR_OP_min) + // TODO Fix when unsigned + RedRHS = Builder.CreateBinaryIntrinsic(llvm::Intrinsic::smin, Op1, Op2, + nullptr, "xteam.min"); + else if (OpKind == CodeGenModule::XR_OP_max) + // TODO fix when unsigned + RedRHS = Builder.CreateBinaryIntrinsic(llvm::Intrinsic::smax, Op1, Op2, + nullptr, "xteam.max"); + else + llvm_unreachable("Unexpected reduction kind"); + } else + llvm_unreachable("Unhandled type"); + assert(RedRHS && "Right hand side of statement cannot be null"); + Builder.CreateStore(RedRHS, XteamRedLocalAddr); +} + +std::pair +CodeGenFunction::ExtractXteamRedRhsExpr(const CallExpr *Call, + const VarDecl *RedVarDecl) { + // Traverse arguments, identifying and ignoring the reduction variable, and + // then extracting the other argument. + CodeGenModule::XteamRedOpKind Opcode; + std::string CallName = Call->getDirectCallee()->getNameInfo().getAsString(); + if (CGM.isOptKernelAMDGCNMax(Call)) + Opcode = CodeGenModule::XR_OP_max; + else if (CGM.isOptKernelAMDGCNMin(Call)) + Opcode = CodeGenModule::XR_OP_min; + else + llvm_unreachable("Epecting either min or max"); + + for (unsigned ArgIndex = 0; ArgIndex < Call->getNumArgs(); ++ArgIndex) { + const Expr *Arg = Call->getArg(ArgIndex); + while (isa(Arg)) + Arg = cast(Arg)->getSubExpr(); + if (CGM.isXteamRedVarExpr(Arg, RedVarDecl)) + continue; + return std::make_pair(Call->getArg(ArgIndex), Opcode); + } + llvm_unreachable("Could not extract expected arg of min/max"); +} + +void CodeGenFunction::EmitXteamRedStmtForBuiltinCall( + const CallExpr *Call, const VarDecl *RedVarDecl, + const CodeGenModule::XteamRedVarMap &RedVarMap) { + auto [RhsExpr, Opcode] = ExtractXteamRedRhsExpr(Call, RedVarDecl); + EmitLocalReductionStmt(RhsExpr, RedVarDecl, RedVarMap, Opcode); +} + void CodeGenFunction::EmitStmt(const Stmt *S, ArrayRef Attrs) { assert(S && "Null statement?"); PGO->setCurrentStmt(S); @@ -128,7 +1204,8 @@ void CodeGenFunction::EmitStmt(const Stmt *S, ArrayRef Attrs) { llvm::BasicBlock *incoming = Builder.GetInsertBlock(); assert(incoming && "expression emission must have an insertion point"); - EmitIgnoredExpr(cast(S)); + if (!EmitXteamRedStmt(S)) + EmitIgnoredExpr(cast(S)); llvm::BasicBlock *outgoing = Builder.GetInsertBlock(); assert(outgoing && "expression emission cleared block!"); @@ -1290,17 +2367,122 @@ void CodeGenFunction::EmitDoStmt(const DoStmt &S, ConvergenceTokenStack.pop_back(); } -void CodeGenFunction::EmitForStmt(const ForStmt &S, - ArrayRef ForAttrs) { +void CodeGenFunction::EmitForStmtWithArgs(const ForStmt &S, + const FunctionArgList *Args, + ArrayRef ForAttrs) { JumpDest LoopExit = getJumpDestInCurrentScope("for.end"); std::optional ForScope; if (getLangOpts().C99 || getLangOpts().CPlusPlus) ForScope.emplace(*this, S.getSourceRange()); - // Evaluate the first part before the loop. - if (S.getInit()) - EmitStmt(S.getInit()); + Address BigJumpLoopIvAddr = Address::invalid(); + const VarDecl *LoopVar = nullptr; + const OMPLoopDirective *BigJumpLoopLD = nullptr; + if (CGM.getLangOpts().OpenMPIsTargetDevice && + (CGM.isXteamRedKernel(&S) || CGM.isBigJumpLoopKernel(&S))) { + const CodeGenModule::OptKernelNestDirectives &Directives = + CGM.isXteamRedKernel(&S) ? CGM.getXteamRedNestDirs(&S) + : CGM.getBigJumpLoopNestDirs(&S); + assert(Directives.size() > 0 && isa(Directives.back()) && + "Appropriate directive not found"); + BigJumpLoopLD = cast(Directives.back()); + + std::pair LoopVarInfo = + EmitBigJumpLoopStartingIndex(S, Args); + LoopVar = LoopVarInfo.first; + BigJumpLoopIvAddr = LoopVarInfo.second; + } else { + // Evaluate the first part before the loop. + if (S.getInit()) + EmitStmt(S.getInit()); + } + + llvm::Value *SegmentLoopUB = nullptr; + llvm::Value *DSegmentVals = nullptr; + llvm::Value *GlobalUpperBound = nullptr; + const Address *RedVarAddr = nullptr; + llvm::BasicBlock *ExecBB = nullptr; + llvm::BasicBlock *DoneBB = nullptr; + const clang::VarDecl *XteamVD; + llvm::Type *RedVarType; + if (getLangOpts().OpenMPIsTargetDevice && CGM.isXteamSegmentedScanKernel()) { + // Compute Loop trip-count (N) = GlobalUB - GlobalLB + 1 + const auto UBLValue = EmitLValue( + cast(BigJumpLoopLD->getUpperBoundVariable())); // GlobalUB + const auto LBLValue = EmitLValue( + cast(BigJumpLoopLD->getLowerBoundVariable())); // GlobalLB + GlobalUpperBound = + Builder.CreateLoad(UBLValue.getAddress(), "global_upper_bound"); + auto InputSize = Builder.CreateAdd( + Builder.CreateSub(GlobalUpperBound, + Builder.CreateLoad(LBLValue.getAddress())), + llvm::ConstantInt::get(Int32Ty, 1)); // GlobalUB - GlobalLB + 1 + auto &RT = static_cast(CGM.getOpenMPRuntime()); + + // Compute Global thread ID (GlobalTID) = (WorkGroupID * WorkGroupSize) + + // GpuThreadId + llvm::Value *GpuThreadId = RT.getGPUThreadID(*this); + llvm::Value *WorkGroupSize = RT.getGPUNumThreads(*this); + llvm::Value *WorkGroupId = RT.getGPUBlockID(*this); + llvm::Value *WorkGroup = Builder.CreateMul(WorkGroupId, WorkGroupSize); + llvm::Value *GlobalGpuThreadId = Builder.CreateAdd(WorkGroup, GpuThreadId); + + // Compute Grid Size (Total number of threads T) = WorkGroupSize * NumTeams + llvm::Value *NumTeams = RT.getGPUNumBlocks(*this); + auto TotalNumThreads = Builder.CreateMul(WorkGroupSize, NumTeams); + + // Create a conditional break to the end of the kernel if the iteration + // variable(iv) exceeds total number of threads in the entire Grid. Note + // that `iv` was initialized with the GlobalTID of a thread. + llvm::Value *ThreadCondVal = + Builder.CreateICmpULT(Builder.CreateLoad(BigJumpLoopIvAddr), + TotalNumThreads); // iv < TotalNumThreads + ExecBB = createBasicBlock("omp.kernel.body"); + DoneBB = createBasicBlock("omp.kernel.done"); + Builder.CreateCondBr(ThreadCondVal, ExecBB, DoneBB); + EmitBlock(ExecBB); + + // Compute Segment size required for a work-item to loop through + llvm::Value *SegmentSizeForScan = + Builder.CreateAdd(Builder.CreateUDiv(InputSize, TotalNumThreads), + llvm::ConstantInt::get(Int32Ty, 1), + "padded_segment_size"); // Seg_Size = ceil(N / T) + + if (!CGM.isXteamScanPhaseOne) // Emit call to DeviceRTL to compute segmented + // scanned values + EmitXteamScanPhaseTwo( + &S, SegmentSizeForScan, *Args, + CGM.getXteamRedBlockSize(*BigJumpLoopLD), + CGM.OMPPresentScanDirective->hasClausesOfKind()); + + // Every thread starts looping from the lower bound: GlobalTID * Seg_Size + Builder.CreateStore( + Builder.CreateMul(SegmentSizeForScan, GlobalGpuThreadId), + BigJumpLoopIvAddr); // *iv = GlobalTID * Seg_Size + + // Every thread loops till just before the SegmentLoopUB: + // SegmentLoopUB = (GlobaTID + 1) * Seg_Size + SegmentLoopUB = Builder.CreateMul( + SegmentSizeForScan, + Builder.CreateAdd(GlobalGpuThreadId, + llvm::ConstantInt::get(Int32Ty, 1))); + + XteamVD = *(CGM.getXteamOrderedRedVar(&S).begin()); + RedVarType = ConvertTypeForMem(XteamVD->getType()); + const CodeGenModule::XteamRedVarMap &RedVarMap = CGM.getXteamRedVarMap(&S); + const CodeGenModule::XteamRedVarInfo &RVI = + (RedVarMap.find(XteamVD))->second; + RedVarAddr = &(RVI.RedVarAddr); + + // SegmentValsAddr points to the SegmentVals array which will store the + // intermediate scan results computed per segment by a single thread + // sequentially. + Address SegmentValsAddr = GetAddrOfLocalVar((*Args)[RVI.ArgPos + 3]); + DSegmentVals = Builder.CreateLoad(SegmentValsAddr); + } + + const Expr *CondExpr = BigJumpLoopLD ? BigJumpLoopLD->getCond() : S.getCond(); // Start the loop with a block that tests the condition. // If there's an increment, the continue scope will be overwritten @@ -1335,7 +2517,7 @@ void CodeGenFunction::EmitForStmt(const ForStmt &S, Continue = getJumpDestInCurrentScope("for.inc"); BreakContinueStack.push_back(BreakContinue(S, LoopExit, Continue)); - if (S.getCond()) { + if (CondExpr) { // If the for statement has a condition scope, emit the local variable // declaration. if (S.getConditionVariable()) { @@ -1361,26 +2543,40 @@ void CodeGenFunction::EmitForStmt(const ForStmt &S, // As long as the condition is true, iterate the loop. llvm::BasicBlock *ForBody = createBasicBlock("for.body"); - // C99 6.8.5p2/p4: The first substatement is executed if the expression - // compares unequal to 0. The condition must be a scalar type. - llvm::Value *BoolCondVal = EvaluateExprAsBool(S.getCond()); + if (getLangOpts().OpenMPIsTargetDevice && + CGM.isXteamSegmentedScanKernel()) { + // Emit the Segment loop breaking condition + + llvm::Value *loopIterationVar = Builder.CreateLoad(BigJumpLoopIvAddr); + llvm::Value *isWithinSegmentBounds = Builder.CreateICmpULT( + loopIterationVar, SegmentLoopUB); // iv < SegmentLoopUB + llvm::Value *isWithinGlobalBounds = Builder.CreateICmpULE( + loopIterationVar, GlobalUpperBound); // iv <= GlobalUB + llvm::Value *BoolCondVal = Builder.CreateAnd( + isWithinGlobalBounds, + isWithinSegmentBounds); // (iv < SegmentLoopUB) && (iv <= GlobalUB) + llvm::MDNode *Weights = + createProfileWeightsForLoop(CondExpr, getProfileCount(S.getBody())); + if (!Weights && CGM.getCodeGenOpts().OptimizationLevel) + BoolCondVal = emitCondLikelihoodViaExpectIntrinsic( + BoolCondVal, Stmt::getLikelihood(S.getBody())); + + Builder.CreateCondBr(BoolCondVal, ForBody, ExitBlock, Weights); + } else { + // C99 6.8.5p2/p4: The first substatement is executed if the expression + // compares unequal to 0. The condition must be a scalar type. + llvm::Value *BoolCondVal = EvaluateExprAsBool(CondExpr); - MaybeEmitDeferredVarDeclInit(S.getConditionVariable()); + MaybeEmitDeferredVarDeclInit(S.getConditionVariable()); - llvm::MDNode *Weights = - createProfileWeightsForLoop(S.getCond(), getProfileCount(S.getBody())); - if (!Weights && CGM.getCodeGenOpts().OptimizationLevel) - BoolCondVal = emitCondLikelihoodViaExpectIntrinsic( - BoolCondVal, Stmt::getLikelihood(S.getBody())); + llvm::MDNode *Weights = + createProfileWeightsForLoop(CondExpr, getProfileCount(S.getBody())); + if (!Weights && CGM.getCodeGenOpts().OptimizationLevel) + BoolCondVal = emitCondLikelihoodViaExpectIntrinsic( + BoolCondVal, Stmt::getLikelihood(S.getBody())); - auto *I = Builder.CreateCondBr(BoolCondVal, ForBody, ExitBlock, Weights); - // Key Instructions: Emit the condition and branch as separate atoms to - // match existing loop stepping behaviour. FIXME: We could have the branch - // as the backup location for the condition, which would probably be a - // better experience (no jumping to the brace). - if (auto *CondI = dyn_cast(BoolCondVal)) - addInstToNewSourceAtom(CondI, nullptr); - addInstToNewSourceAtom(I, nullptr); + Builder.CreateCondBr(BoolCondVal, ForBody, ExitBlock, Weights); + } if (ExitBlock != LoopExit.getBlock()) { EmitBlock(ExitBlock); @@ -1402,19 +2598,80 @@ void CodeGenFunction::EmitForStmt(const ForStmt &S, // Create a separate cleanup scope for the body, in case it is not // a compound statement. RunCleanupsScope BodyScope(*this); - EmitStmt(S.getBody()); - } - // The last block in the loop's body (which unconditionally branches to the - // `inc` block if there is one). - auto *FinalBodyBB = Builder.GetInsertBlock(); + if (CGM.getLangOpts().OpenMPIsTargetDevice && + (CGM.isXteamRedKernel(&S) || CGM.isBigJumpLoopKernel(&S))) { + EmitBigJumpLoopUpdates(S); + for (auto C : BigJumpLoopLD->finals_conditions()) { + if (!C) + continue; + // Check that loop counter in non-rectangular nest fits into the + // iteration space. + llvm::BasicBlock *NextBB = createBasicBlock("omp.body.next"); + EmitBranchOnBoolExpr(C, NextBB, Continue.getBlock(), + getProfileCount(BigJumpLoopLD->getBody())); + EmitBlock(NextBB); + } + if (CGM.isXteamSegmentedScanKernel()) { + if (!CGM.isXteamScanPhaseOne) { + // SegmentVals contains the final scanned results computed for every + // element in a segment. + Address SegmentValsGEP = + Address(Builder.CreateGEP(RedVarType, DSegmentVals, + Builder.CreateLoad(BigJumpLoopIvAddr)), + RedVarType, + getContext().getTypeAlignInChars( + XteamVD->getType())); // SegmentVals[*iv] + // emit redvar = SegmentVals[omp.iv] + Builder.CreateStore(Builder.CreateLoad(SegmentValsGEP), *RedVarAddr); + } + CodeGenFunction::ParentLoopDirectiveForScanRegion ScanRegion( + *this, *BigJumpLoopLD); + { + OMPFirstScanLoop = CGM.isXteamScanPhaseOne; + CodeGenFunction::OMPLocalDeclMapRAII Scope(*this); + EmitOMPXteamScanNoLoopBody(*BigJumpLoopLD); + } + if (!CGM.isXteamScanPhaseOne) + CGM.OMPPresentScanDirective = nullptr; + } else + EmitOMPNoLoopBody(*BigJumpLoopLD); + } else { + EmitStmt(S.getBody()); + } + } - // If there is an increment, emit it next. - if (S.getInc()) { - EmitBlock(Continue.getBlock()); - EmitStmt(S.getInc()); - if (llvm::EnableSingleByteCoverage) - incrementProfileCounter(S.getInc()); + if (CGM.getLangOpts().OpenMPIsTargetDevice && + (CGM.isXteamRedKernel(&S) || CGM.isBigJumpLoopKernel(&S))) { + if (CGM.isXteamSegmentedScanKernel()) { + EmitBlock(Continue.getBlock()); + Address SegmentValsGEP = + Address(Builder.CreateGEP(RedVarType, DSegmentVals, + Builder.CreateLoad(BigJumpLoopIvAddr)), + RedVarType, + getContext().getTypeAlignInChars( + XteamVD->getType())); // Segment_Vals[*iv] + Builder.CreateStore(Builder.CreateLoad(*RedVarAddr), + SegmentValsGEP); // Segment_Vals[*iv] = red_var + llvm::Value *SegmentScanLoopInc = + Builder.CreateAdd(llvm::ConstantInt::get(Int32Ty, 1), + Builder.CreateLoad(BigJumpLoopIvAddr)); + Builder.CreateStore(SegmentScanLoopInc, + BigJumpLoopIvAddr); // *iv = *iv + 1 + } else { + EmitBlock(Continue.getBlock()); + EmitBigJumpLoopInc( + S, LoopVar, + BigJumpLoopIvAddr); // *iv = *iv + num_teams * num_threads + } + } else { + // If there is an increment, emit it next. + if (S.getInc()) { + EmitBlock(Continue.getBlock()); + EmitStmt(S.getInc()); + if (llvm::EnableSingleByteCoverage) + incrementProfileCounter(S.getInc()); + } } BreakContinueStack.pop_back(); @@ -1432,6 +2689,13 @@ void CodeGenFunction::EmitForStmt(const ForStmt &S, // Emit the fall-through block. EmitBlock(LoopExit.getBlock(), true); + if (CGM.getLangOpts().OpenMPIsTargetDevice && + CGM.isXteamSegmentedScanKernel()) { + if (CGM.isXteamScanPhaseOne) + EmitXteamScanSum(&S, *Args, CGM.getXteamRedBlockSize(*BigJumpLoopLD)); + EmitBranch(DoneBB); + EmitBlock(DoneBB); + } // When single byte coverage mode is enabled, add a counter to continuation // block. if (llvm::EnableSingleByteCoverage) @@ -1440,11 +2704,11 @@ void CodeGenFunction::EmitForStmt(const ForStmt &S, if (CGM.shouldEmitConvergenceTokens()) ConvergenceTokenStack.pop_back(); - if (FinalBodyBB) { - // Key Instructions: We want the for closing brace to be step-able on to - // match existing behaviour. - addInstToNewSourceAtom(FinalBodyBB->getTerminator(), nullptr); - } +} + +void CodeGenFunction::EmitForStmt(const ForStmt &S, + ArrayRef ForAttrs) { + CodeGenFunction::EmitForStmtWithArgs(S, nullptr, ForAttrs); } void diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp index efc06a276267a..dd9a4b3fa076a 100644 --- a/clang/lib/CodeGen/CGStmtOpenMP.cpp +++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp @@ -401,8 +401,74 @@ llvm::Value *CodeGenFunction::getTypeSize(QualType Ty) { return CGM.getSize(SizeInChars); } +void CodeGenFunction::InitializeXteamRedCapturedVars( + SmallVectorImpl &CapturedVars, QualType RedVarQualType) { + llvm::Type *RedVarType = ConvertTypeForMem(RedVarQualType); + assert((RedVarType->isFloatTy() || RedVarType->isDoubleTy() || + RedVarType->isHalfTy() || RedVarType->isBFloatTy() || + RedVarType->isIntegerTy()) && + "Unhandled type"); + + const ASTContext &Context = CGM.getContext(); + llvm::Type *Int32Ty = llvm::Type::getInt32Ty(CGM.getLLVMContext()); + + // Placeholder for d_team_vals initialized to nullptr + llvm::Value *DTeamValsInst = + Builder.CreateAlloca(RedVarType, nullptr, "d_team_vals"); + Address DTeamValsAddr(DTeamValsInst, RedVarType, + Context.getTypeAlignInChars(RedVarQualType)); + llvm::Value *NullPtrDTeamVals = llvm::ConstantPointerNull::get( + llvm::PointerType::get(getLLVMContext(), /*AddressSpace=*/0)); + Builder.CreateStore(NullPtrDTeamVals, DTeamValsAddr); + + // Placeholder for d_teams_done_ptr initialized to nullptr + llvm::Value *DTeamsDonePtrInst = + Builder.CreateAlloca(Int32Ty, nullptr, "d_teams_done_ptr"); + Address DTeamsDoneAddr(DTeamsDonePtrInst, Int32Ty, + Context.getTypeAlignInChars(Context.UnsignedIntTy)); + llvm::Value *NullPtrDTeamsDone = llvm::ConstantPointerNull::get( + llvm::PointerType::get(getLLVMContext(), /*AddressSpace=*/0)); + Builder.CreateStore(NullPtrDTeamsDone, DTeamsDoneAddr); + + assert(DTeamValsInst && "Device team vals pointer cannot be null"); + CapturedVars.push_back(DTeamValsInst); + + assert(DTeamsDonePtrInst && "Device team done pointer cannot be null"); + CapturedVars.push_back(DTeamsDonePtrInst); + + if (CGM.isXteamScanKernel()) { + // Placeholder for d_scan_storage initialized to nullptr + llvm::Value *DScanStorageInst = + Builder.CreateAlloca(RedVarType, nullptr, "d_scan_storage"); + Address DScanStorageAddr( + DScanStorageInst, RedVarType, + Context.getTypeAlignInChars(Context.UnsignedIntTy)); + llvm::Value *NullPtrDScanStorage = llvm::ConstantPointerNull::get( + llvm::PointerType::get(getLLVMContext(), /*AddressSpace=*/0)); + Builder.CreateStore(NullPtrDScanStorage, DScanStorageAddr); + + assert(DScanStorageInst && "Device scan storage pointer cannot be null"); + CapturedVars.push_back(DScanStorageInst); + if (CGM.isXteamSegmentedScanKernel()) { + // Placeholder for d_segment_vals initialized to nullptr + llvm::Value *DSegmentValsInst = + Builder.CreateAlloca(RedVarType, nullptr, "d_segment_vals"); + Address DSegmentValsAddr( + DSegmentValsInst, RedVarType, + Context.getTypeAlignInChars(Context.UnsignedIntTy)); + llvm::Value *NullPtrDSegmentVals = llvm::ConstantPointerNull::get( + llvm::PointerType::get(getLLVMContext(), /*AddressSpace=*/0)); + Builder.CreateStore(NullPtrDSegmentVals, DSegmentValsAddr); + + assert(DSegmentValsInst && "Segment Vals Array pointer cannot be null"); + CapturedVars.push_back(DSegmentValsInst); + } + } +} + void CodeGenFunction::GenerateOpenMPCapturedVars( - const CapturedStmt &S, SmallVectorImpl &CapturedVars) { + const CapturedStmt &S, SmallVectorImpl &CapturedVars, + const Stmt *XteamRedNestKey) { const RecordDecl *RD = S.getCapturedRecordDecl(); auto CurField = RD->field_begin(); auto CurCap = S.captures().begin(); @@ -446,6 +512,56 @@ void CodeGenFunction::GenerateOpenMPCapturedVars( CapturedVars.push_back(EmitLValue(*I).getAddress().emitRawPointer(*this)); } } + + // The Xteam reduction variable capture must happen after all other captures. + const ForStmt *FStmt = CGM.getSingleForStmt(XteamRedNestKey); + if (FStmt && CGM.isXteamRedKernel(FStmt)) { + assert(!CGM.getLangOpts().OpenMPIsTargetDevice && "Expecting host CG"); + CodeGenModule::XteamRedVarMap &XteamRVM = CGM.getXteamRedVarMap(FStmt); + auto XteamOrdVars = CGM.getXteamOrderedRedVar(FStmt); + // Always generate Xteam metadata in the same order as user-specified + // reduction variables. + for (auto XteamVD : XteamOrdVars) { + auto Itr = XteamRVM.find(XteamVD); + assert(Itr != XteamRVM.end() && "Metadata not found"); + InitializeXteamRedCapturedVars(CapturedVars, + Itr->second.RedVarExpr->getType()); + } + } +} + +// This function should be called on the host when preparing to emit the +// code that launches the kernel on the device. +void CodeGenFunction::GenerateOpenMPCapturedVarsDevice( + const CapturedStmt &S, SmallVectorImpl &CapturedVars, + SmallVectorImpl &MultiTargetVars, + const Stmt *XteamRedNestKey) { + ASTContext &Ctx = getContext(); + + // If a for loop exists then it means we can use multi-target split on + // this target region. + if (CGM.getLangOpts().OpenMPTargetMultiDevice) { + assert(!CGM.getLangOpts().OpenMPIsTargetDevice && + "This should only happen on host CG"); + + // Add LB placeholder: + Address CastedLBMultiAddr = + CreateMemTemp(Ctx.getUIntPtrType(), "LB.multi.addr"); + LValue CastedLBMultiLV = + MakeAddrLValue(CastedLBMultiAddr, Ctx.getUIntPtrType()); + llvm::Value *LBValue = EmitLoadOfScalar(CastedLBMultiLV, S.getBeginLoc()); + MultiTargetVars.push_back(LBValue); + + // Add UB placeholder: + Address CastedUBMultiAddr = + CreateMemTemp(Ctx.getUIntPtrType(), "UB.multi.addr"); + LValue CastedUBMultiLV = + MakeAddrLValue(CastedUBMultiAddr, Ctx.getUIntPtrType()); + llvm::Value *UBValue = EmitLoadOfScalar(CastedUBMultiLV, S.getBeginLoc()); + MultiTargetVars.push_back(UBValue); + } + + GenerateOpenMPCapturedVars(S, CapturedVars, XteamRedNestKey); } static Address castValueFromUintptr(CodeGenFunction &CGF, SourceLocation Loc, @@ -453,6 +569,15 @@ static Address castValueFromUintptr(CodeGenFunction &CGF, SourceLocation Loc, LValue AddrLV) { ASTContext &Ctx = CGF.getContext(); + Address Addr = AddrLV.getAddress(); + if (Ctx.getTargetInfo().getTriple().isAMDGCN() && + CGF.CGM.getLangOpts().OpenMPIsTargetDevice) { + auto *Ty = CGF.ConvertType(Ctx.getPointerType(DstType)); + auto *PTy = dyn_cast(Ty); + // For device path, add addrspacecast if needed before emitscalar conversion + if (PTy && PTy->getAddressSpace() != Addr.getAddressSpace()) + Addr = CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(Addr, Ty, PTy); + } llvm::Value *CastedPtr = CGF.EmitScalarConversion( AddrLV.getAddress().emitRawPointer(CGF), Ctx.getUIntPtrType(), Ctx.getPointerType(DstType), Loc); @@ -504,12 +629,15 @@ struct FunctionOptions { } // namespace static llvm::Function *emitOutlinedFunctionPrologue( - CodeGenFunction &CGF, FunctionArgList &Args, + CodeGenFunction &CGF, const OMPExecutableDirective &D, + FunctionArgList &Args, llvm::MapVector> &LocalAddrs, llvm::DenseMap> &VLASizes, - llvm::Value *&CXXThisValue, const FunctionOptions &FO) { + llvm::Value *&CXXThisValue, const FunctionOptions &FO, + bool argsNeedAddrSpace, bool isXteamKernel, bool AddMultiDeviceArgs, + bool AddArgsToTopKernelOnly) { const CapturedDecl *CD = FO.S->getCapturedDecl(); const RecordDecl *RD = FO.S->getCapturedRecordDecl(); assert(CD->hasBody() && "missing CapturedDecl body"); @@ -524,6 +652,47 @@ static llvm::Function *emitOutlinedFunctionPrologue( TargetArgs.append( CD->param_begin(), std::next(CD->param_begin(), CD->getContextParamPosition())); + + // Add arguments for multi-device targets if enabled and if there is a an + // iteration space associated with the directive containing the target + // directive. + unsigned ContextArgsMultiDeviceOffset = 0; + VarDecl *LBDeclVD = nullptr; + VarDecl *UBDeclVD = nullptr; + + // Determine if two extra arguments should be added. The args should always + // be added to the top kernel when in multi-device mode and on the device. + bool AddedExtraMDArgs = false; + if (AddArgsToTopKernelOnly) { + AddedExtraMDArgs = true; + } else if (AddMultiDeviceArgs) { + assert(CGM.getOptKernelKey(D) && + "Mapping key for Xteam reduction statement not found"); + const ForStmt *FStmt = CGM.getSingleForStmt(CGM.getOptKernelKey(D)); + assert(FStmt && "For statement for directive not found"); + + // If we have a valid for statement for this target region then we can + // emit a multi-device target for it. Add the two arguments that hold the + // lower and upper bound for the loop: + if (FStmt) { + AddedExtraMDArgs = true; + } + } + + if (AddedExtraMDArgs) { + QualType Int64Ty = + Ctx.getIntTypeForBitwidth(/*DestWidth=*/64, /*Signed=*/1); + LBDeclVD = ImplicitParamDecl::Create(Ctx, Int64Ty, + ImplicitParamKind::CapturedContext); + Args.emplace_back(LBDeclVD); + TargetArgs.emplace_back(LBDeclVD); + UBDeclVD = ImplicitParamDecl::Create(Ctx, Int64Ty, + ImplicitParamKind::CapturedContext); + Args.emplace_back(UBDeclVD); + TargetArgs.emplace_back(UBDeclVD); + ContextArgsMultiDeviceOffset = 2; + } + auto I = FO.S->captures().begin(); FunctionDecl *DebugFunctionDecl = nullptr; if (!FO.UIntPtrCastRequired) { @@ -562,6 +731,19 @@ static llvm::Function *emitOutlinedFunctionPrologue( } if (ArgType->isVariablyModifiedType()) ArgType = getCanonicalParamType(Ctx, ArgType); + + // Set the IPD QualType for kernel args to be in device AS (1) + if (CapVar && CGM.getLangOpts().OpenMPIsTargetDevice && argsNeedAddrSpace && + (Ctx.getTargetInfo().getTriple().isAMDGCN())) { + const clang::Type *ty = ArgType.getTypePtr(); + if (ty->isAnyPointerType() || ty->isReferenceType()) { + clang::LangAS LLVM_AS = CapVar->getType().getAddressSpace(); + if (LLVM_AS == LangAS::Default) + LLVM_AS = LangAS::cuda_device; + ArgType = Ctx.getAddrSpaceQualType(ArgType, LLVM_AS); + } + } + VarDecl *Arg; if (CapVar && (CapVar->getTLSKind() != clang::VarDecl::TLS_None)) { Arg = ImplicitParamDecl::Create(Ctx, /*DC=*/nullptr, FD->getLocation(), @@ -591,8 +773,69 @@ static llvm::Function *emitOutlinedFunctionPrologue( std::next(CD->param_begin(), CD->getContextParamPosition() + 1), CD->param_end()); + // If Xteam, add the new args here to the signature. + if (isXteamKernel) { + assert(CGM.getOptKernelKey(D) && + "Mapping key for Xteam reduction statement not found"); + const ForStmt *FStmt = CGM.getSingleForStmt(CGM.getOptKernelKey(D)); + assert(FStmt && "For statement for directive not found"); + CodeGenModule::XteamRedVarMap &XteamRVM = CGM.getXteamRedVarMap(FStmt); + auto XteamOrdVars = CGM.getXteamOrderedRedVar(FStmt); + // Always add Xteam arguments to the signature in the same order as + // user-specified reduction variables. + for (auto XteamVD : XteamOrdVars) { + auto Itr = XteamRVM.find(XteamVD); + assert(Itr != XteamRVM.end() && "Metadata not found"); + + // Cached argument positions are used for device codegen alone + if (CGM.getLangOpts().OpenMPIsTargetDevice) + CGM.updateXteamRedVarArgPos(&Itr->second, Args.size()); + VarDecl *DTeamValsVD = ImplicitParamDecl::Create( + Ctx, Ctx.VoidPtrTy, ImplicitParamKind::CapturedContext); + Args.emplace_back(DTeamValsVD); + TargetArgs.emplace_back(DTeamValsVD); + VarDecl *DTeamsDoneVD = ImplicitParamDecl::Create( + Ctx, Ctx.VoidPtrTy, ImplicitParamKind::CapturedContext); + Args.emplace_back(DTeamsDoneVD); + TargetArgs.emplace_back(DTeamsDoneVD); + if (CGM.isXteamScanKernel()) { + VarDecl *DScanStorageVD = ImplicitParamDecl::Create( + Ctx, Ctx.VoidPtrTy, ImplicitParamKind::CapturedContext); + Args.emplace_back(DScanStorageVD); + TargetArgs.emplace_back(DScanStorageVD); + if (CGM.isXteamSegmentedScanKernel()) { + VarDecl *DSegmentValsVD = ImplicitParamDecl::Create( + Ctx, Ctx.VoidPtrTy, ImplicitParamKind::CapturedContext); + Args.emplace_back(DSegmentValsVD); + TargetArgs.emplace_back(DSegmentValsVD); + } + } + } + } + + SmallVector argCanQualTypes; + if (CGM.getLangOpts().OpenMPIsTargetDevice && argsNeedAddrSpace && + (Ctx.getTargetInfo().getTriple().isAMDGCN())) { + // We need Canonical Param Types WITH addrspace qualifier + for (const auto &Arg : TargetArgs) { + clang::LangAS address_space = Arg->getType().getAddressSpace(); + if (address_space != LangAS::Default) + argCanQualTypes.push_back( + CanQualType::CreateUnsafe(Ctx.getAddrSpaceQualType( + Ctx.getCanonicalParamType(Arg->getType()), address_space))); + else + argCanQualTypes.push_back(Ctx.getCanonicalParamType(Arg->getType())); + } + } + // Create the function declaration. const CGFunctionInfo &FuncInfo = + (CGM.getLangOpts().OpenMPIsTargetDevice && argsNeedAddrSpace && + (Ctx.getTargetInfo().getTriple().isAMDGCN())) + ? CGM.getTypes().arrangeLLVMFunctionInfo( + Ctx.VoidTy, FnInfoOpts::None, argCanQualTypes, + FunctionType::ExtInfo(), {}, RequiredArgs::All) + : FO.IsDeviceKernel ? CGM.getTypes().arrangeDeviceKernelCallerDeclaration(Ctx.VoidTy, TargetArgs) @@ -619,7 +862,12 @@ static llvm::Function *emitOutlinedFunctionPrologue( FO.UIntPtrCastRequired ? FO.Loc : FO.S->getBeginLoc(), FO.UIntPtrCastRequired ? FO.Loc : CD->getBody()->getBeginLoc()); - unsigned Cnt = CD->getContextParamPosition(); + + // When multi-device targets are enabled and applicable to this kernel then + // we need to add an offset of 2 to the regular offset since now the + // context variables start in position 3 instead of 1. The loop below will + // iterate over any variables captured from the user context. + unsigned Cnt = ContextArgsMultiDeviceOffset + CD->getContextParamPosition(); I = FO.S->captures().begin(); for (const FieldDecl *FD : RD->fields()) { // Do not map arguments if we emit function with non-original types. @@ -688,19 +936,28 @@ static llvm::Function *emitOutlinedFunctionPrologue( ++I; } + if (AddMultiDeviceArgs) { + const ForStmt *FStmt = CGM.getSingleForStmt(CGM.getOptKernelKey(D)); + if (FStmt) { + // Save these emitted arguments to use them later on if we need to emit an + // outlined function in the generic case. + CGM.saveMultiDeviceArgs(D, F, LBDeclVD, UBDeclVD); + } + } + return F; } llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunction( - const CapturedStmt &S, const OMPExecutableDirective &D) { + const CapturedStmt &S, const OMPExecutableDirective &D, + bool CanHaveMultiDeviceArgs, bool IsTopKernel) { SourceLocation Loc = D.getBeginLoc(); assert( CapturedStmtInfo && "CapturedStmtInfo should be set when generating the captured function"); const CapturedDecl *CD = S.getCapturedDecl(); + // Build the argument list. - bool NeedWrapperFunction = - getDebugInfo() && CGM.getCodeGenOpts().hasReducedDebugInfo(); FunctionArgList Args, WrapperArgs; llvm::MapVector> LocalAddrs, WrapperLocalAddrs; @@ -709,10 +966,56 @@ llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunction( SmallString<256> Buffer; llvm::raw_svector_ostream Out(Buffer); Out << CapturedStmtInfo->getHelperName(); + + bool isKernel = (Out.str().find("__omp_offloading_") != std::string::npos); + + // For host codegen, we need to determine now whether Xteam reduction is used + // for this statement. For device codegen, it is already determined and hence + // retrieved from the cache. This boolean will determine the signature of the + // offloading function, both on the host and device. + const ForStmt *FStmt = nullptr; + const Stmt *OptKernelKey = CGM.getOptKernelKey(D); + if (OptKernelKey) + FStmt = CGM.getSingleForStmt(OptKernelKey); + bool isXteamKernel = false; + if (CGM.getLangOpts().OpenMPIsTargetDevice) + isXteamKernel = FStmt && CGM.isXteamRedKernel(FStmt); + else { + // If Xteam found, use it. Otherwise, query again. This is required to make + // sure that the outlined routines have the correct signature. + if (FStmt) { + if (!CGM.isXteamRedKernel(FStmt)) { + CodeGenModule::NoLoopXteamErr NxStatus = + CGM.checkAndSetXteamRedKernel(D); + DEBUG_WITH_TYPE(NO_LOOP_XTEAM_RED, + CGM.emitNxResult("[Xteam-host]", D, NxStatus)); + isXteamKernel = (NxStatus == CodeGenModule::NxSuccess); + } else + isXteamKernel = true; + } else { + CodeGenModule::NoLoopXteamErr NxStatus = CGM.checkAndSetXteamRedKernel(D); + DEBUG_WITH_TYPE(NO_LOOP_XTEAM_RED, + CGM.emitNxResult("[Xteam-host]", D, NxStatus)); + isXteamKernel = (NxStatus == CodeGenModule::NxSuccess); + } + } + + // AMDGCN does not generate wrapper kernels properly, fails to launch kernel. + // Xteam reduction does not use wrapper kernels. + bool NeedWrapperFunction = + !CGM.getTriple().isAMDGCN() && !isXteamKernel && + (getDebugInfo() && CGM.getCodeGenOpts().hasReducedDebugInfo()); + + // Determine if the kernel is multi-device. The check and set function will + // verify if the value has been set before, if it has been set then return it. + bool IsMultiDeviceKernel = + CGM.checkAndSetMultiDeviceKernel(D, CanHaveMultiDeviceArgs); + OpenMPDirectiveKind EKind = getEffectiveDirectiveKind(D); bool IsDeviceKernel = CGM.getOpenMPRuntime().isGPU() && isOpenMPTargetExecutionDirective(EKind) && D.getCapturedStmt(OMPD_target) == &S; + CodeGenFunction WrapperCGF(CGM, /*suppressNewContext=*/true); llvm::Function *WrapperF = nullptr; if (NeedWrapperFunction) { @@ -723,15 +1026,31 @@ llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunction( CapturedStmtInfo->getHelperName(), Loc, IsDeviceKernel); WrapperCGF.CapturedStmtInfo = CapturedStmtInfo; - WrapperF = - emitOutlinedFunctionPrologue(WrapperCGF, Args, LocalAddrs, VLASizes, - WrapperCGF.CXXThisValue, WrapperFO); + // TODO: Determine if the wrapper function needs to pass in multi-device + // args in the meantime it is always false. + WrapperF = emitOutlinedFunctionPrologue( + WrapperCGF, D, Args, LocalAddrs, VLASizes, WrapperCGF.CXXThisValue, + WrapperFO, isKernel, isXteamKernel, /*AddMultiDeviceArgs*/ false, + /*AddArgsToTopKernelOnly*/ false); Out << "_debug__"; } FunctionOptions FO(&S, !NeedWrapperFunction, /*RegisterCastedArgsOnly=*/false, Out.str(), Loc, !NeedWrapperFunction && IsDeviceKernel); + + // Add multi-device args only if this is the team level or higher. For + // outlined parallel level we should never emit multi device arguments even if + // this is deemed to be a multi device kernel. The team level, when outlined, + // will correctly pass the LB and UB values to the outlined parallel region as + // prev.UB and prev.LB arguments. + bool ShouldEmitMultiDevicePrologue = + IsMultiDeviceKernel && CanHaveMultiDeviceArgs; + bool AddArgsToTopKernelOnly = IsTopKernel && !ShouldEmitMultiDevicePrologue && + getLangOpts().OpenMPTargetMultiDevice && + getLangOpts().OpenMPIsTargetDevice; llvm::Function *F = emitOutlinedFunctionPrologue( - *this, WrapperArgs, WrapperLocalAddrs, WrapperVLASizes, CXXThisValue, FO); + *this, D, WrapperArgs, WrapperLocalAddrs, WrapperVLASizes, CXXThisValue, + FO, isKernel, isXteamKernel, ShouldEmitMultiDevicePrologue, + AddArgsToTopKernelOnly); CodeGenFunction::OMPPrivateScope LocalScope(*this); for (const auto &LocalAddrPair : WrapperLocalAddrs) { if (LocalAddrPair.second.first) { @@ -743,7 +1062,41 @@ llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunction( for (const auto &VLASizePair : WrapperVLASizes) VLASizeMap[VLASizePair.second.first] = VLASizePair.second.second; PGO->assignRegionCounters(GlobalDecl(CD), F); - CapturedStmtInfo->EmitBody(*this, CD->getBody()); + + // Generate specialized kernels for device only + if (CGM.getLangOpts().OpenMPIsTargetDevice && D.hasAssociatedStmt() && + ((FStmt && CGM.isNoLoopKernel(FStmt)) || + (FStmt && CGM.isBigJumpLoopKernel(FStmt)))) { + if (CGM.isNoLoopKernel(FStmt)) + EmitOptKernel( + D, FStmt, + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP, Loc, + &WrapperArgs); + else + EmitOptKernel( + D, FStmt, + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_BIG_JUMP_LOOP, + Loc, &WrapperArgs); + } else if (CGM.getLangOpts().OpenMPIsTargetDevice && isXteamKernel) { + EmitOptKernel(D, FStmt, + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_XTEAM_RED, + Loc, &WrapperArgs); + } else { + // TODO: for multi-device targets handle this case + if (!(CGM.isXteamScanKernel() && !CGM.isXteamScanPhaseOne)) + // This condition prevents any codegen for the host fallback function of + // the PhaseTwo kernel of Xteam Scan. + // Explanation: The fallback function for PhaseOne kernel is the 'true' + // fallback that computes parallel scan on the host using the existing + // implementation of scan. Whereas, the fallback function for PhaseTwo + // kernel is a 'dummy' one, that is, it doesn't do any computation. The + // two kernels are necessary to enforce synchronization between the two + // phases of Xteam Scan. At the same time, fallback generation is + // mandatory for every kernel although we don't need the host fallback + // generation for the PhaseTwo kernel. + CapturedStmtInfo->EmitBody(*this, CD->getBody()); + } + LocalScope.ForceCleanup(); FinishFunction(CD->getBodyRBrace()); if (!NeedWrapperFunction) @@ -752,7 +1105,6 @@ llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunction( // Reverse the order. WrapperF->removeFromParent(); F->getParent()->getFunctionList().insertAfter(F->getIterator(), WrapperF); - llvm::SmallVector CallArgs; auto *PI = F->arg_begin(); for (const auto *Arg : Args) { @@ -1690,7 +2042,7 @@ static void emitCommonOMPParallelDirective( // The following lambda takes care of appending the lower and upper bound // parameters when necessary CodeGenBoundParameters(CGF, S, CapturedVars); - CGF.GenerateOpenMPCapturedVars(*CS, CapturedVars); + CGF.GenerateOpenMPCapturedVars(*CS, CapturedVars, CGF.CGM.getOptKernelKey(S)); CGF.CGM.getOpenMPRuntime().emitParallelCall(CGF, S.getBeginLoc(), OutlinedFn, CapturedVars, IfCond, NumThreads, Modifier, Severity, Message); @@ -2079,6 +2431,56 @@ void CodeGenFunction::EmitOMPLoopBody(const OMPLoopDirective &D, BreakContinueStack.pop_back(); } +void CodeGenFunction::EmitOMPNoLoopBody(const OMPLoopDirective &D) { + const Stmt *Body = + D.getInnermostCapturedStmt()->getCapturedStmt()->IgnoreContainers(); + // Emit loop body. + emitBody(*this, Body, + OMPLoopBasedDirective::tryToFindNextInnerLoop( + Body, /*TryImperfectlyNestedLoops=*/true), + D.getLoopsNumber()); +} + +void CodeGenFunction::EmitOMPXteamScanNoLoopBody(const OMPLoopDirective &D) { + RunCleanupsScope BodyScope(*this); + JumpDest Continue = getJumpDestInCurrentScope("omp.body.continue"); + JumpDest LoopExit = getJumpDestInCurrentScope("omp.loop.exit"); + const Stmt *BodyL = + D.getInnermostCapturedStmt()->getCapturedStmt()->IgnoreContainers(); + BreakContinueStack.push_back(BreakContinue(cast(*BodyL), LoopExit, Continue)); + OMPPrivateScope InscanScope(*this); + EmitOMPReductionClauseInit(D, InscanScope, /*ForInscan=*/true); + + // Need to remember the block before and after scan directive + // to dispatch them correctly depending on the clause used in + // this directive, inclusive or exclusive. For inclusive scan the natural + // order of the blocks is used, for exclusive clause the blocks must be + // executed in reverse order. + OMPBeforeScanBlock = createBasicBlock("omp.before.scan.bb"); + OMPAfterScanBlock = createBasicBlock("omp.after.scan.bb"); + // No need to allocate inscan exit block, in simd mode it is selected in the + // codegen for the scan directive. + if (D.getDirectiveKind() != OMPD_simd && !getLangOpts().OpenMPSimd) + OMPScanExitBlock = createBasicBlock("omp.exit.inscan.bb"); + OMPScanDispatch = createBasicBlock("omp.inscan.dispatch"); + EmitBranch(OMPScanDispatch); + EmitBlock(OMPBeforeScanBlock); + + // Emit loop variables for C++ range loops. + const Stmt *Body = + D.getInnermostCapturedStmt()->getCapturedStmt()->IgnoreContainers(); + // Emit loop body. + emitBody(*this, Body, + OMPLoopBasedDirective::tryToFindNextInnerLoop( + Body, /*TryImperfectlyNestedLoops=*/true), + D.getLoopsNumber()); + + // Jump to the dispatcher at the end of the loop body. + EmitBranch(OMPScanExitBlock); + EmitBlock(Continue.getBlock()); + BreakContinueStack.pop_back(); +} + using EmittedClosureTy = std::pair; /// Emit a captured statement and return the function as well as its captured @@ -2245,7 +2647,6 @@ void CodeGenFunction::EmitOMPInnerLoop( ExitBlock = createBasicBlock("omp.inner.for.cond.cleanup"); llvm::BasicBlock *LoopBody = createBasicBlock("omp.inner.for.body"); - // Emit condition. EmitBranchOnBoolExpr(LoopCond, LoopBody, ExitBlock, getProfileCount(&S)); if (ExitBlock != LoopExit.getBlock()) { @@ -2273,6 +2674,78 @@ void CodeGenFunction::EmitOMPInnerLoop( EmitBlock(LoopExit.getBlock()); } +void CodeGenFunction::EmitOMPMultiDeviceInnerLoop( + const OMPExecutableDirective &S, bool RequiresCleanup, const Expr *LoopCond, + const Expr *IncExpr, const VarDecl *IVDecl, + const llvm::function_ref BodyGen, + const llvm::function_ref PostIncGen) { + // If this is not a multi-device kernel, call the previous method. + if (!CGM.isMultiDeviceKernel(S)) + return EmitOMPInnerLoop(S, RequiresCleanup, LoopCond, IncExpr, BodyGen, + PostIncGen); + + auto LoopExit = getJumpDestInCurrentScope("omp.inner.for.end"); + + // Start the loop with a block that tests the condition. + auto CondBlock = createBasicBlock("omp.inner.for.cond"); + EmitBlock(CondBlock); + const SourceRange R = S.getSourceRange(); + + // If attributes are attached, push to the basic block with them. + const auto &OMPED = cast(S); + const CapturedStmt *ICS = OMPED.getInnermostCapturedStmt(); + const Stmt *SS = ICS->getCapturedStmt(); + const AttributedStmt *AS = dyn_cast_or_null(SS); + OMPLoopNestStack.clear(); + if (AS) + LoopStack.push(CondBlock, CGM.getContext(), CGM.getCodeGenOpts(), + AS->getAttrs(), SourceLocToDebugLoc(R.getBegin()), + SourceLocToDebugLoc(R.getEnd())); + else + LoopStack.push(CondBlock, SourceLocToDebugLoc(R.getBegin()), + SourceLocToDebugLoc(R.getEnd())); + + // If there are any cleanups between here and the loop-exit scope, + // create a block to stage a loop exit along. + llvm::BasicBlock *ExitBlock = LoopExit.getBlock(); + if (RequiresCleanup) + ExitBlock = createBasicBlock("omp.inner.for.cond.cleanup"); + + llvm::BasicBlock *LoopBody = createBasicBlock("omp.inner.for.body"); + // Emit condition bearing in mind that the condition should be compared + // against MultiDeviceUB not the original loop UB. + llvm::Value *IV = Builder.CreateLoad(GetAddrOfLocalVar(IVDecl)); + llvm::Value *IVCast = Builder.CreateIntCast(IV, Int64Ty, /*isSigned=*/true); + Address MultiDeviceUBAddr = + GetAddrOfLocalVar(CGM.getMultiDeviceUBArg(S, CurFn)); + llvm::Value *MultiDeviceUB = Builder.CreateLoad(MultiDeviceUBAddr); + llvm::Value *CmpI = Builder.CreateICmpSLE(IVCast, MultiDeviceUB); + Builder.CreateCondBr(CmpI, LoopBody, ExitBlock); + if (ExitBlock != LoopExit.getBlock()) { + EmitBlock(ExitBlock); + EmitBranchThroughCleanup(LoopExit); + } + + EmitBlock(LoopBody); + incrementProfileCounter(&S); + + // Create a block for the increment. + JumpDest Continue = getJumpDestInCurrentScope("omp.inner.for.inc"); + BreakContinueStack.push_back(BreakContinue(*SS, LoopExit, Continue)); + + BodyGen(*this); + + // Emit "IV = IV + 1" and a back-edge to the condition block. + EmitBlock(Continue.getBlock()); + EmitIgnoredExpr(IncExpr); + PostIncGen(*this); + BreakContinueStack.pop_back(); + EmitBranch(CondBlock); + LoopStack.pop(); + // Emit the fall-through block. + EmitBlock(LoopExit.getBlock()); +} + bool CodeGenFunction::EmitOMPLinearClauseInit(const OMPLoopDirective &D) { if (!HaveInsertPoint()) return false; @@ -3274,9 +3747,11 @@ void CodeGenFunction::EmitOMPForOuterLoop( OuterLoopArgs.DKind = LoopArgs.DKind; EmitOMPOuterLoop(DynamicOrOrdered, IsMonotonic, S, LoopScope, OuterLoopArgs, emitOMPLoopBodyWithStopPoint, CodeGenOrdered); +#ifndef _WIN32 if (DynamicOrOrdered) { RT.emitForDispatchDeinit(*this, S.getBeginLoc()); } +#endif } static void emitEmptyOrdered(CodeGenFunction &, SourceLocation Loc, @@ -3302,7 +3777,13 @@ void CodeGenFunction::EmitOMPDistributeOuterLoop( CGOpenMPRuntime::StaticRTInput StaticInit( IVSize, IVSigned, /* Ordered = */ false, LoopArgs.IL, LoopArgs.LB, LoopArgs.UB, LoopArgs.ST, LoopArgs.Chunk); - RT.emitDistributeStaticInit(*this, S.getBeginLoc(), ScheduleKind, StaticInit); + bool IsMultiDeviceKernel = CGM.isMultiDeviceKernel(S); + if (IsMultiDeviceKernel) + StaticInit.setMultiDeviceLBUB( + GetAddrOfLocalVar(CGM.getMultiDeviceLBArg(S, CurFn)), + GetAddrOfLocalVar(CGM.getMultiDeviceUBArg(S, CurFn))); + RT.emitDistributeStaticInit(*this, S.getBeginLoc(), ScheduleKind, StaticInit, + IsMultiDeviceKernel); // for combined 'distribute' and 'for' the increment expression of distribute // is stored in DistInc. For 'distribute' alone, it is in Inc. @@ -3421,6 +3902,8 @@ static void emitDistributeParallelForDistributeInnerBoundParams( CGF.Builder.CreateLoad(UB.getAddress()), CGF.SizeTy, /*isSigned=*/false); CapturedVars.push_back(UBCast); } +static bool emitWorksharingDirective(CodeGenFunction &CGF, + const OMPLoopDirective &S, bool HasCancel); static void emitInnerParallelForWhenCombined(CodeGenFunction &CGF, @@ -3440,10 +3923,15 @@ emitInnerParallelForWhenCombined(CodeGenFunction &CGF, dyn_cast(&S)) HasCancel = D->hasCancel(); } - CodeGenFunction::OMPCancelStackRAII CancelRegion(CGF, EKind, HasCancel); - CGF.EmitOMPWorksharingLoop(S, S.getPrevEnsureUpperBound(), - emitDistributeParallelForInnerBounds, - emitDistributeParallelForDispatchBounds); + if (CGF.CGM.isXteamScanKernel()) { + emitOMPCopyinClause(CGF, S); + (void)emitWorksharingDirective(CGF, S, HasCancel); + } else { + CodeGenFunction::OMPCancelStackRAII CancelRegion(CGF, EKind, HasCancel); + CGF.EmitOMPWorksharingLoop(S, S.getPrevEnsureUpperBound(), + emitDistributeParallelForInnerBounds, + emitDistributeParallelForDispatchBounds); + } }; emitCommonOMPParallelDirective( @@ -3830,7 +4318,28 @@ static void emitScanBasedDirectiveDecls( ->getSizeExpr()), RValue::get(OMPScanNumIterations)); // Emit temp buffer. - CGF.EmitVarDecl(*cast(cast(*ITA)->getDecl())); + auto TempVarDecl = cast(cast(*ITA)->getDecl()); + if (CGF.CGM.isXteamScanKernel() && + !CGF.CGM.getLangOpts().OpenMPIsTargetDevice && + CGF.hasAddrOfLocalVar(TempVarDecl)) { + // While generating the Host Fallback function for the Xteam Scan + // Kernels, emit the stack allocation pointer for the VLA(Variable + // Length Array) of size (i.e. OMPScanNumIterations) - a helper + // variable required for host scan. In a previous allocation for this + // VarDecl, only a dummy VLA allocation of size 0 was emitted just so + // that there is an entry in the LocalDeclMap at the CGF level. However, + // this is the place where the actual allocation happens and the new + // alloca's pointer is now stored at the address of older alloca's + // pointer. + auto TempVLAInst = CGF.Builder.CreateAlloca( + CGF.Int32Ty, OMPScanNumIterations, "tmp.vla"); + Address TempVDAddr = CGF.GetAddrOfLocalVar(TempVarDecl); + auto TempVDAddrLValue = + CGF.MakeAddrLValue(TempVDAddr, TempVarDecl->getType()); + CGF.EmitStoreOfScalar(TempVLAInst, TempVDAddrLValue, + /* isInitialization */ false); + } else + CGF.EmitVarDecl(*TempVarDecl); ++ITA; ++Count; } @@ -5686,9 +6195,21 @@ void CodeGenFunction::EmitOMPTaskgroupDirective( } void CodeGenFunction::EmitOMPFlushDirective(const OMPFlushDirective &S) { - llvm::AtomicOrdering AO = S.getSingleClause() - ? llvm::AtomicOrdering::NotAtomic - : llvm::AtomicOrdering::AcquireRelease; + // assume implicit FlushClause is used and change to AcquireRelease if not + // used + llvm::AtomicOrdering AO = llvm::AtomicOrdering::NotAtomic; + if (!S.getSingleClause()) { + AO = llvm::AtomicOrdering::AcquireRelease; + if (S.getSingleClause()) + AO = llvm::AtomicOrdering::SequentiallyConsistent; + else if (S.getSingleClause()) + AO = llvm::AtomicOrdering::AcquireRelease; + else if (S.getSingleClause()) + AO = llvm::AtomicOrdering::Acquire; + else if (S.getSingleClause()) + AO = llvm::AtomicOrdering::Release; + } + CGM.getOpenMPRuntime().emitFlush( *this, [&S]() -> ArrayRef { @@ -5728,6 +6249,7 @@ void CodeGenFunction::EmitOMPDepobjDirective(const OMPDepobjDirective &S) { void CodeGenFunction::EmitOMPScanDirective(const OMPScanDirective &S) { if (!OMPParentLoopDirectiveForScan) return; + CGM.OMPPresentScanDirective = &S; const OMPExecutableDirective &ParentDir = *OMPParentLoopDirectiveForScan; bool IsInclusive = S.hasClausesOfKind(); SmallVector Shareds; @@ -5869,12 +6391,20 @@ void CodeGenFunction::EmitOMPScanDirective(const OMPScanDirective &S) { cast( cast(CopyArrayElem)->getIdx()), RValue::get(IdxVal)); - LValue DestLVal = EmitLValue(CopyArrayElem); - LValue SrcLVal = EmitLValue(OrigExpr); - EmitOMPCopy( - PrivateExpr->getType(), DestLVal.getAddress(), SrcLVal.getAddress(), - cast(cast(LHSs[I])->getDecl()), - cast(cast(RHSs[I])->getDecl()), CopyOps[I]); + + // Omit the codegen of `CopyArrayElem[Index] = Red_Var (aka OrigExpr)` + // while generating code for the Xteam Scan kernel function because the + // Red_Var will be eventually consumed by the Device codegen machinery + // implemented for Xteam Scan + if (!(CGM.getLangOpts().OpenMPIsTargetDevice && + CGM.isXteamRedKernel(ParentDir) && CGM.isXteamScanKernel())) { + LValue DestLVal = EmitLValue(CopyArrayElem); + LValue SrcLVal = EmitLValue(OrigExpr); + EmitOMPCopy( + PrivateExpr->getType(), DestLVal.getAddress(), SrcLVal.getAddress(), + cast(cast(LHSs[I])->getDecl()), + cast(cast(RHSs[I])->getDecl()), CopyOps[I]); + } } } EmitBranch(BreakContinueStack.back().ContinueBlock.getBlock()); @@ -5912,10 +6442,26 @@ void CodeGenFunction::EmitOMPScanDirective(const OMPScanDirective &S) { RValue::get(IdxVal)); LValue SrcLVal = EmitLValue(CopyArrayElem); LValue DestLVal = EmitLValue(OrigExpr); - EmitOMPCopy( - PrivateExpr->getType(), DestLVal.getAddress(), SrcLVal.getAddress(), - cast(cast(LHSs[I])->getDecl()), - cast(cast(RHSs[I])->getDecl()), CopyOps[I]); + + if (CGM.getLangOpts().OpenMPIsTargetDevice && + CGM.isXteamRedKernel(ParentDir) && CGM.isXteamScanKernel()) { + // Store the updated value of reduction variable(in the second phase of + // Xteam scan) to the OrigExpr(aka Red_Var). This will be consumed by + // the AfterScanBlock later on. + const CodeGenModule::XteamRedVarMap &RedVarMap = + CGM.getXteamRedVarMap(CGM.getCurrentXteamRedStmt()); + const VarDecl *RedVarDecl = + cast(cast(OrigExpr)->getDecl()); + Address XteamRedLocalAddr = + RedVarMap.find(RedVarDecl)->second.RedVarAddr; + Builder.CreateStore(Builder.CreateLoad(XteamRedLocalAddr), + DestLVal.getAddress()); + } else { + EmitOMPCopy( + PrivateExpr->getType(), DestLVal.getAddress(), SrcLVal.getAddress(), + cast(cast(LHSs[I])->getDecl()), + cast(cast(RHSs[I])->getDecl()), CopyOps[I]); + } } if (!IsInclusive) { EmitBlock(ExclusiveExitBB); @@ -5952,6 +6498,7 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S, // Skip the entire loop if we don't meet the precondition. // If the condition constant folds and can be elided, avoid emitting the // whole loop. + bool CondConstant; llvm::BasicBlock *ContBlock = nullptr; if (ConstantFoldsToSimpleInteger(S.getPreCond(), CondConstant)) { @@ -5970,7 +6517,6 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S, // Emit 'then' code. { // Emit helper vars inits. - LValue LB = EmitOMPHelperVar( *this, cast( (isOpenMPLoopBoundSharingDirective(S.getDirectiveKind()) @@ -6036,6 +6582,7 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S, bool StaticChunked = RT.isStaticChunked(ScheduleKind, /* Chunked */ Chunk != nullptr) && isOpenMPLoopBoundSharingDirective(S.getDirectiveKind()); + bool IsMultiDeviceKernel = CGM.isMultiDeviceKernel(S); if (RT.isStaticNonchunked(ScheduleKind, /* Chunked */ Chunk != nullptr) || StaticChunked) { @@ -6043,14 +6590,60 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S, IVSize, IVSigned, /* Ordered = */ false, IL.getAddress(), LB.getAddress(), UB.getAddress(), ST.getAddress(), StaticChunked ? Chunk : nullptr); + // If the current emission is part of multi-device kernel then we need + // to invoke a special method. + if (IsMultiDeviceKernel) + StaticInit.setMultiDeviceLBUB( + GetAddrOfLocalVar(CGM.getMultiDeviceLBArg(S, CurFn)), + GetAddrOfLocalVar(CGM.getMultiDeviceUBArg(S, CurFn))); RT.emitDistributeStaticInit(*this, S.getBeginLoc(), ScheduleKind, - StaticInit); + StaticInit, IsMultiDeviceKernel); JumpDest LoopExit = getJumpDestInCurrentScope(createBasicBlock("omp.loop.exit")); - // UB = min(UB, GlobalUB); - EmitIgnoredExpr(isOpenMPLoopBoundSharingDirective(S.getDirectiveKind()) - ? S.getCombinedEnsureUpperBound() - : S.getEnsureUpperBound()); + + // For multi device kernels we have to compare against the MultiDeviceUB + // instead of the GlobalUB. + if (CGM.isMultiDeviceKernel(S)) { + // UB = min(UB, MultiDeviceUB); + // Step 1: load UB variable which was just passed and modified by the + // distribute static init runtime function. + llvm::Value *UBVal = Builder.CreateLoad(UB.getAddress()); + + // Step 2: Get the address of the Multi Device UB and load it: + Address MultiDeviceUBAddr = + GetAddrOfLocalVar(CGM.getMultiDeviceUBArg(S, CurFn)); + llvm::Value *MultiDeviceUB = Builder.CreateLoad(MultiDeviceUBAddr); + + // Step 3: Make sure the compared values have the same type: + llvm::Value *UBValCasted = + Builder.CreateIntCast(UBVal, Int64Ty, /*isSigned=*/true); + + // Step 4: Compare the values: if current UB is > MultiDeviceUB then + // ensure that we do not go beyond the MultiDeviceUB. + llvm::Value *CmpI = Builder.CreateICmpSGT(UBValCasted, MultiDeviceUB); + auto MDCheckTrue = createBasicBlock("omp.md.check.true"); + auto MDCheckEnd = createBasicBlock("omp.md.check.end"); + + // Step 5: Emit the comparison: + Builder.CreateCondBr(CmpI, MDCheckTrue, MDCheckEnd); + + // Step 6: Emit the true block which will store the upper bound. + EmitBlock(MDCheckTrue); + llvm::Value *MultiDeviceUBCasted = Builder.CreateIntCast( + MultiDeviceUB, UBVal->getType(), /*isSigned=*/true); + Builder.CreateStore(MultiDeviceUBCasted, UB.getAddress()); + EmitBranch(MDCheckEnd); + + // Step 7: emit condition end block + EmitBlock(MDCheckEnd); + } else { + // UB = min(UB, GlobalUB); + EmitIgnoredExpr( + isOpenMPLoopBoundSharingDirective(S.getDirectiveKind()) + ? S.getCombinedEnsureUpperBound() + : S.getEnsureUpperBound()); + } + // IV = LB; EmitIgnoredExpr(isOpenMPLoopBoundSharingDirective(S.getDirectiveKind()) ? S.getCombinedInit() @@ -6094,18 +6687,67 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S, if (isOpenMPSimdDirective(S.getDirectiveKind())) CGF.EmitOMPSimdInit(S); }, - [&S, &LoopScope, Cond, IncExpr, LoopExit, &CodeGenLoop, - StaticChunked](CodeGenFunction &CGF, PrePostActionTy &) { - CGF.EmitOMPInnerLoop( - S, LoopScope.requiresCleanups(), Cond, IncExpr, + [&S, &LoopScope, Cond, IncExpr, IVDecl, LoopExit, &CodeGenLoop, + StaticChunked, UB](CodeGenFunction &CGF, PrePostActionTy &) { + CGF.EmitOMPMultiDeviceInnerLoop( + S, LoopScope.requiresCleanups(), Cond, IncExpr, IVDecl, [&S, LoopExit, &CodeGenLoop](CodeGenFunction &CGF) { CodeGenLoop(CGF, S, LoopExit); }, - [&S, StaticChunked](CodeGenFunction &CGF) { + [&S, StaticChunked, UB](CodeGenFunction &CGF) { if (StaticChunked) { CGF.EmitIgnoredExpr(S.getCombinedNextLowerBound()); CGF.EmitIgnoredExpr(S.getCombinedNextUpperBound()); - CGF.EmitIgnoredExpr(S.getCombinedEnsureUpperBound()); + // TODO: emit UB = min(UB, MutliDeviceUB) + if (CGF.CGM.isMultiDeviceKernel(S)) { + // UB = min(UB, MultiDeviceUB); + // Step 1: load UB variable which was just passed and + // modified by the distribute static init runtime + // function. + llvm::Value *UBVal = + CGF.Builder.CreateLoad(UB.getAddress()); + + // Step 2: Get the address of the Multi Device UB and + // load it: + Address MultiDeviceUBAddr = CGF.GetAddrOfLocalVar( + CGF.CGM.getMultiDeviceUBArg(S, CGF.CurFn)); + llvm::Value *MultiDeviceUB = + CGF.Builder.CreateLoad(MultiDeviceUBAddr); + + // Step 3: Make sure the compared values have the same + // type: + llvm::Value *UBValCasted = CGF.Builder.CreateIntCast( + UBVal, CGF.Int64Ty, /*isSigned=*/true); + + // Step 4: Compare the values: if current UB is > + // MultiDeviceUB then ensure that we do not go beyond + // the MultiDeviceUB. + llvm::Value *CmpI = CGF.Builder.CreateICmpSGT( + UBValCasted, MultiDeviceUB); + auto MDCheckTrue = + CGF.createBasicBlock("omp.md.check.true"); + auto MDCheckEnd = + CGF.createBasicBlock("omp.md.check.end"); + + // Step 5: Emit the comparison: + CGF.Builder.CreateCondBr(CmpI, MDCheckTrue, MDCheckEnd); + + // Step 6: Emit the true block which will store the + // upper bound. + CGF.EmitBlock(MDCheckTrue); + llvm::Value *MultiDeviceUBCasted = + CGF.Builder.CreateIntCast(MultiDeviceUB, + UBVal->getType(), + /*isSigned=*/true); + CGF.Builder.CreateStore(MultiDeviceUBCasted, + UB.getAddress()); + CGF.EmitBranch(MDCheckEnd); + + // Step 7: emit condition end block + CGF.EmitBlock(MDCheckEnd); + } else { + CGF.EmitIgnoredExpr(S.getCombinedEnsureUpperBound()); + } CGF.EmitIgnoredExpr(S.getCombinedInit()); } }); @@ -6116,6 +6758,7 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S, } else { // Emit the outer loop, which requests its work chunk [LB..UB] from // runtime and runs the inner loop to process it. + // TODO: handle this case for Multi-Device Kernels. const OMPLoopArguments LoopArguments = { LB.getAddress(), UB.getAddress(), ST.getAddress(), IL.getAddress(), Chunk}; @@ -6178,7 +6821,10 @@ emitOutlinedOrderedFunction(CodeGenModule &CGM, const CapturedStmt *S, CodeGenFunction CGF(CGM, /*suppressNewContext=*/true); CodeGenFunction::CGCapturedStmtInfo CapStmtInfo; CGF.CapturedStmtInfo = &CapStmtInfo; - llvm::Function *Fn = CGF.GenerateOpenMPCapturedStmtFunction(*S, D); + llvm::Function *Fn = + CGF.GenerateOpenMPCapturedStmtFunction(*S, D, + /*CanHaveMultiDeviceArgs*/ false, + /*IsTopKernel*/ false); Fn->setDoesNotRecurse(); return Fn; } @@ -6242,8 +6888,9 @@ void CodeGenFunction::EmitOMPOrderedDirective(const OMPOrderedDirective &S) { llvm::BasicBlock *FiniBB = splitBBWithSuffix( Builder, /*CreateBranch=*/false, ".ordered.after"); llvm::SmallVector CapturedVars; - GenerateOpenMPCapturedVars(*CS, CapturedVars); - llvm::Function *OutlinedFn = emitOutlinedOrderedFunction(CGM, CS, S); + GenerateOpenMPCapturedVars(*CS, CapturedVars, CGM.getOptKernelKey(S)); + llvm::Function *OutlinedFn = + emitOutlinedOrderedFunction(CGM, CS, S); assert(S.getBeginLoc().isValid() && "Outlined function call location must be valid."); ApplyDebugLocation::CreateDefaultArtificial(*this, S.getBeginLoc()); @@ -6284,8 +6931,10 @@ void CodeGenFunction::EmitOMPOrderedDirective(const OMPOrderedDirective &S) { const CapturedStmt *CS = S.getInnermostCapturedStmt(); if (C) { llvm::SmallVector CapturedVars; - CGF.GenerateOpenMPCapturedVars(*CS, CapturedVars); - llvm::Function *OutlinedFn = emitOutlinedOrderedFunction(CGM, CS, S); + CGF.GenerateOpenMPCapturedVars(*CS, CapturedVars, CGM.getOptKernelKey(S)); + llvm::Function *OutlinedFn = + emitOutlinedOrderedFunction(CGM, CS, S); + CGM.getOpenMPRuntime().emitOutlinedFunctionCall(CGF, S.getBeginLoc(), OutlinedFn, CapturedVars); } else { @@ -6430,12 +7079,107 @@ static void emitOMPAtomicWriteExpr(CodeGenFunction &CGF, } } -static std::pair emitOMPAtomicRMW(CodeGenFunction &CGF, LValue X, - RValue Update, - BinaryOperatorKind BO, - llvm::AtomicOrdering AO, - bool IsXLHSInRHSPart) { +static bool canUseAMDGPUFastFPAtomics(CodeGenFunction &CGF, LValue X, + RValue Update, BinaryOperatorKind BO, + const Expr *Hint, SourceLocation Loc) { + + if (!Update.isScalar()) + return false; + + if (!X.isSimple()) + return false; + + ASTContext &Context = CGF.getContext(); + + // Handle fast FP atomics for AMDGPU target (call intrinsic) + // Flag\Hint| None | Fast | Safe | + //---------------------------------- + // | | | | + // Fast | Fast | Fast | Safe | + // (unsafe) | | | | + //---------------------------------- + // | | | | + // Safe | Safe | Fast | Safe | + //(no-unsafe)| | | | + //---------------------------------- + + bool userRequestsAMDGPUFastFPAtomics = true; + + if (CGF.CGM.getOpenMPRuntime().needsHintsForFastFPAtomics()) { + + userRequestsAMDGPUFastFPAtomics = + CGF.CGM.getLangOpts().AtomicIgnoreDenormalMode; + + if (Hint) { + if (Hint->getIntegerConstantExpr(Context).value() == + HintClause::OpenMPSyncHintExpr::AMD_fast_fp_atomics) + userRequestsAMDGPUFastFPAtomics = true; + else if (Hint->getIntegerConstantExpr(Context).value() == + HintClause::OpenMPSyncHintExpr::AMD_safe_fp_atomics) + userRequestsAMDGPUFastFPAtomics = false; + } + } + + bool supportsFastFPAtomics = + Context.getTargetInfo().getTriple().isAMDGCN() && + CGF.CGM.getOpenMPRuntime().supportFastFPAtomics() && + CGF.CGM.getLangOpts().OpenMPIsTargetDevice && + userRequestsAMDGPUFastFPAtomics; + + bool addOpHasAMDGPUFastVersion = + BO == BO_Add && (Update.getScalarVal()->getType()->isDoubleTy() || + Update.getScalarVal()->getType()->isFloatTy()); + + bool minMaxOpHasAMDGPUFastVersion = + (BO == BO_LT || BO == BO_GT) && + Update.getScalarVal()->getType()->isDoubleTy(); + + if (!supportsFastFPAtomics || + (!addOpHasAMDGPUFastVersion && !minMaxOpHasAMDGPUFastVersion)) + return false; + + llvm::Type *UpdateType = Update.getScalarVal()->getType(); + llvm::Type *XType = X.getAddress().getElementType(); + + bool isUpdateLosslesslyCastableToX = + UpdateType->canLosslesslyBitCastTo(XType); + + if (!isUpdateLosslesslyCastableToX) { + + auto getTypeNameAsString = [](llvm::Type* T) -> std::string { + std::string TypeNameStr; + llvm::raw_string_ostream OutputStream(TypeNameStr); + T->print(OutputStream); + return TypeNameStr; + }; + + unsigned DiagID = CGF.CGM.getDiags().getCustomDiagID( + DiagnosticsEngine::Warning, + "Can't emit fast FP atomic call due to type mismatch. The operation " + "tries to assign %0 to %1. A fallback atomic operation is " + "emitted which ignores the type conflict. Result may be incorrect!"); + clang::DiagnosticBuilder DB = CGF.CGM.getDiags().Report(Loc, DiagID); + DB.AddString(getTypeNameAsString(UpdateType)); + DB.AddString(getTypeNameAsString(XType)); + } + + return isUpdateLosslesslyCastableToX; +} + +static std::pair +emitOMPAtomicRMW(CodeGenFunction &CGF, LValue X, RValue Update, + BinaryOperatorKind BO, llvm::AtomicOrdering AO, + bool IsXLHSInRHSPart, const Expr *Hint, SourceLocation Loc) { ASTContext &Context = CGF.getContext(); + + bool useFPAtomics = canUseAMDGPUFastFPAtomics(CGF, X, Update, BO, Hint, Loc); + if (useFPAtomics) { + auto Ret = CGF.CGM.getOpenMPRuntime().emitFastFPAtomicCall( + CGF, X, Update, BO, IsXLHSInRHSPart); + if (Ret.first) + return Ret; + } + // Allow atomicrmw only if 'x' and 'update' are integer values, lvalue for 'x' // expression is simple and atomic is allowed for the given type for the // target platform. @@ -6551,14 +7295,14 @@ static std::pair emitOMPAtomicRMW(CodeGenFunction &CGF, LValue X, std::pair CodeGenFunction::EmitOMPAtomicSimpleUpdateExpr( LValue X, RValue E, BinaryOperatorKind BO, bool IsXLHSInRHSPart, llvm::AtomicOrdering AO, SourceLocation Loc, - const llvm::function_ref CommonGen) { + const llvm::function_ref CommonGen, const Expr *Hint) { // Update expressions are allowed to have the following forms: // x binop= expr; -> xrval + expr; // x++, ++x -> xrval + 1; // x--, --x -> xrval - 1; // x = x binop expr; -> xrval binop expr // x = expr Op x; - > expr binop xrval; - auto Res = emitOMPAtomicRMW(*this, X, E, BO, AO, IsXLHSInRHSPart); + auto Res = emitOMPAtomicRMW(*this, X, E, BO, AO, IsXLHSInRHSPart, Hint, Loc); if (!Res.first) { if (X.isGlobalReg()) { // Emit an update expression: 'xrval' binop 'expr' or 'expr' binop @@ -6575,7 +7319,8 @@ std::pair CodeGenFunction::EmitOMPAtomicSimpleUpdateExpr( static void emitOMPAtomicUpdateExpr(CodeGenFunction &CGF, llvm::AtomicOrdering AO, const Expr *X, const Expr *E, const Expr *UE, - bool IsXLHSInRHSPart, SourceLocation Loc) { + bool IsXLHSInRHSPart, SourceLocation Loc, + const Expr *Hint) { assert(isa(UE->IgnoreImpCasts()) && "Update expr in 'atomic update' must be a binary operator."); const auto *BOUE = cast(UE->IgnoreImpCasts()); @@ -6597,8 +7342,9 @@ static void emitOMPAtomicUpdateExpr(CodeGenFunction &CGF, CodeGenFunction::OpaqueValueMapping MapX(CGF, XRValExpr, XRValue); return CGF.EmitAnyExpr(UE); }; - (void)CGF.EmitOMPAtomicSimpleUpdateExpr( - XLValue, ExprRValue, BOUE->getOpcode(), IsXLHSInRHSPart, AO, Loc, Gen); + (void)CGF.EmitOMPAtomicSimpleUpdateExpr(XLValue, ExprRValue, + BOUE->getOpcode(), IsXLHSInRHSPart, + AO, Loc, Gen, Hint); CGF.CGM.getOpenMPRuntime().checkAndEmitLastprivateConditional(CGF, X); // OpenMP, 2.17.7, atomic Construct // If the write, update, or capture clause is specified and the release, @@ -6748,7 +7494,7 @@ static void emitOMPAtomicCompareExpr( CodeGenFunction &CGF, llvm::AtomicOrdering AO, llvm::AtomicOrdering FailAO, const Expr *X, const Expr *V, const Expr *R, const Expr *E, const Expr *D, const Expr *CE, bool IsXBinopExpr, bool IsPostfixUpdate, bool IsFailOnly, - SourceLocation Loc) { + const Expr *Hint, SourceLocation Loc) { llvm::OpenMPIRBuilder &OMPBuilder = CGF.CGM.getOpenMPRuntime().getOMPBuilder(); @@ -6782,6 +7528,18 @@ static void emitOMPAtomicCompareExpr( }; llvm::Value *EVal = EmitRValueWithCastIfNeeded(X, E); + + // Check if fast AMDGPU FP atomics can be used for the current operation: + bool canUseFastAtomics = canUseAMDGPUFastFPAtomics( + CGF, XLVal, RValue::get(EVal), cast(CE)->getOpcode(), + Hint, Loc); + if (canUseFastAtomics) { + CGF.CGM.getOpenMPRuntime().emitFastFPAtomicCall( + CGF, XLVal, RValue::get(EVal), cast(CE)->getOpcode(), + IsXBinopExpr); + return; + } + llvm::Value *DVal = D ? EmitRValueWithCastIfNeeded(X, D) : nullptr; if (auto *CI = dyn_cast(EVal)) EVal = CGF.Builder.CreateIntCast( @@ -6831,7 +7589,8 @@ static void emitOMPAtomicExpr(CodeGenFunction &CGF, OpenMPClauseKind Kind, const Expr *X, const Expr *V, const Expr *R, const Expr *E, const Expr *UE, const Expr *D, const Expr *CE, bool IsXLHSInRHSPart, - bool IsFailOnly, SourceLocation Loc) { + bool IsFailOnly, SourceLocation Loc, + const Expr *Hint) { switch (Kind) { case OMPC_read: emitOMPAtomicReadExpr(CGF, AO, X, V, Loc); @@ -6841,7 +7600,7 @@ static void emitOMPAtomicExpr(CodeGenFunction &CGF, OpenMPClauseKind Kind, break; case OMPC_unknown: case OMPC_update: - emitOMPAtomicUpdateExpr(CGF, AO, X, E, UE, IsXLHSInRHSPart, Loc); + emitOMPAtomicUpdateExpr(CGF, AO, X, E, UE, IsXLHSInRHSPart, Loc, Hint); break; case OMPC_capture: emitOMPAtomicCaptureExpr(CGF, AO, IsPostfixUpdate, V, X, E, UE, @@ -6849,7 +7608,11 @@ static void emitOMPAtomicExpr(CodeGenFunction &CGF, OpenMPClauseKind Kind, break; case OMPC_compare: { emitOMPAtomicCompareExpr(CGF, AO, FailAO, X, V, R, E, D, CE, - IsXLHSInRHSPart, IsPostfixUpdate, IsFailOnly, Loc); + IsXLHSInRHSPart, IsPostfixUpdate, IsFailOnly, Hint, Loc); + break; + } + case OMPC_fail: { + //TODO break; } default: @@ -6916,6 +7679,9 @@ void CodeGenFunction::EmitOMPAtomicDirective(const OMPAtomicDirective &S) { } } } + const Expr *Hint = nullptr; + if (const auto *HintClause = S.getSingleClause()) + Hint = HintClause->getHint(); if (KindsEncountered.contains(OMPC_compare) && KindsEncountered.contains(OMPC_fail)) { @@ -6937,7 +7703,7 @@ void CodeGenFunction::EmitOMPAtomicDirective(const OMPAtomicDirective &S) { emitOMPAtomicExpr(*this, Kind, AO, FailAO, S.isPostfixUpdate(), S.getX(), S.getV(), S.getR(), S.getExpr(), S.getUpdateExpr(), S.getD(), S.getCondExpr(), S.isXLHSInRHSPart(), - S.isFailOnly(), S.getBeginLoc()); + S.isFailOnly(), S.getBeginLoc(), Hint); } static void emitCommonOMPTargetDirective(CodeGenFunction &CGF, @@ -6988,6 +7754,18 @@ static void emitCommonOMPTargetDirective(CodeGenFunction &CGF, if (CGM.getLangOpts().OMPTargetTriples.empty()) IsOffloadEntry = false; + // Check if this is an XTeam reduction kernel when the offload + // mandatory flag is on. + const ForStmt *FStmt = nullptr; + const Stmt *OptKernelKey = CGM.getOptKernelKey(S); + if (OptKernelKey) + FStmt = CGM.getSingleForStmt(OptKernelKey); + if (FStmt && CGM.getLangOpts().OpenMPOffloadMandatory) { + CodeGenModule::NoLoopXteamErr NxStatus = CGM.checkAndSetXteamRedKernel(S); + DEBUG_WITH_TYPE(NO_LOOP_XTEAM_RED, + CGM.emitNxResult("[Xteam-host]", S, NxStatus)); + } + if (CGM.getLangOpts().OpenMPOffloadMandatory && !IsOffloadEntry) { unsigned DiagID = CGM.getDiags().getCustomDiagID( DiagnosticsEngine::Error, @@ -7024,6 +7802,8 @@ static void emitCommonOMPTargetDirective(CodeGenFunction &CGF, } return nullptr; }; + // Fn passed in here is passed in to emit the case in which the offloading + // fails and the execution of the target region occurs on the host. CGM.getOpenMPRuntime().emitTargetCall(CGF, S, Fn, FnID, IfCond, Device, SizeEmitter); } @@ -7085,7 +7865,7 @@ static void emitCommonOMPTeamsDirective(CodeGenFunction &CGF, OMPTeamsScope Scope(CGF, S); llvm::SmallVector CapturedVars; - CGF.GenerateOpenMPCapturedVars(*CS, CapturedVars); + CGF.GenerateOpenMPCapturedVars(*CS, CapturedVars, CGF.CGM.getOptKernelKey(S)); CGF.CGM.getOpenMPRuntime().emitTeamsCall(CGF, S, S.getBeginLoc(), OutlinedFn, CapturedVars); } @@ -7426,8 +8206,19 @@ static void emitTargetTeamsDistributeParallelForRegion( CGF.EmitOMPReductionClauseFinal(S, /*ReductionKind=*/OMPD_teams); }; + auto &&NumIteratorsGen = [&S](CodeGenFunction &CGF) { + CodeGenFunction::OMPLocalDeclMapRAII Scope(CGF); + OMPLoopScope LoopScope(CGF, S); + return CGF.EmitScalarExpr(S.getNumIterations()); + }; + + if (CGF.CGM.isXteamScanKernel()) + emitScanBasedDirectiveDecls(CGF, S, NumIteratorsGen); emitCommonOMPTeamsDirective(CGF, S, OMPD_distribute_parallel_for, CodeGenTeams); + if (CGF.CGM.isXteamScanKernel()) + emitScanBasedDirectiveFinals(CGF, S, NumIteratorsGen); + emitPostUpdateForReductionClause(CGF, S, [](CodeGenFunction &) { return nullptr; }); } @@ -7440,6 +8231,7 @@ void CodeGenFunction::EmitOMPTargetTeamsDistributeParallelForDeviceFunction( auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &Action) { emitTargetTeamsDistributeParallelForRegion(CGF, S, Action); }; + llvm::Function *Fn; llvm::Constant *Addr; // Emit target region as a standalone region. @@ -7453,7 +8245,36 @@ void CodeGenFunction::EmitOMPTargetTeamsDistributeParallelForDirective( auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &Action) { emitTargetTeamsDistributeParallelForRegion(CGF, S, Action); }; - emitCommonOMPTargetDirective(*this, S, CodeGen); + { + const auto &&NumIteratorsGen = [&S](CodeGenFunction &CGF) { + CodeGenFunction::OMPLocalDeclMapRAII Scope(CGF); + CGCapturedStmtInfo CGSI(CR_OpenMP); + CodeGenFunction::CGCapturedStmtRAII CapInfoRAII(CGF, &CGSI); + OMPLoopScope LoopScope(CGF, S); + // Emit the size 0 to emit a dummy alloca just so that the LocalDeclMap + // contains the respective VarDecl. We later emit the actual alloca during + // host fallback generation for Xteam Scan kernels. + return CGF.Builder.getInt32(0); + }; + bool IsInscan = + llvm::any_of(S.getClausesOfKind(), + [](const OMPReductionClause *C) { + return C->getModifier() == OMPC_REDUCTION_inscan; + }); + if (IsInscan) + emitScanBasedDirectiveDecls(*this, S, NumIteratorsGen); + auto LPCRegion = + CGOpenMPRuntime::LastprivateConditionalRAII::disable(*this, S); + emitCommonOMPTargetDirective(*this, S, CodeGen); + this->CGM.isXteamScanPhaseOne = false; + if (this->CGM.isXteamScanKernel()) { + emitCommonOMPTargetDirective(*this, S, CodeGen); + this->CGM.isXteamScanPhaseOne = true; + } + + if (IsInscan) + emitScanBasedDirectiveFinals(*this, S, NumIteratorsGen); + } } static void emitTargetTeamsDistributeParallelForSimdRegion( @@ -7492,6 +8313,7 @@ void CodeGenFunction::EmitOMPTargetTeamsDistributeParallelForSimdDeviceFunction( auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &Action) { emitTargetTeamsDistributeParallelForSimdRegion(CGF, S, Action); }; + llvm::Function *Fn; llvm::Constant *Addr; // Emit target region as a standalone region. @@ -8270,8 +9092,13 @@ void CodeGenFunction::EmitOMPTargetUpdateDirective( CGM.getOpenMPRuntime().emitTargetDataStandAloneCall(*this, S, IfCond, Device); } +/// A 'loop' construct is supposed to be a work distribution construct by +/// default unless its binding region is the innermost enclosing parallel +/// region, in which case it is a worksharing region. Because we currently +/// have no way to know if this is true at compile time, for now emit them +/// as inlined loops. void CodeGenFunction::EmitOMPGenericLoopDirective( - const OMPGenericLoopDirective &S) { + const OMPLoopDirective &S) { // Always expect a bind clause on the loop directive. It it wasn't // in the source, it should have been added in sema. @@ -8462,8 +9289,8 @@ void CodeGenFunction::EmitOMPTargetTeamsGenericLoopDeviceFunction( } static void emitTargetParallelGenericLoopRegion( - CodeGenFunction &CGF, const OMPTargetParallelGenericLoopDirective &S, - PrePostActionTy &Action) { + CodeGenFunction &CGF, const OMPTargetParallelGenericLoopDirective &S, + PrePostActionTy &Action) { Action.Enter(CGF); // Emit as 'parallel for'. auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &Action) { diff --git a/clang/lib/CodeGen/CMakeLists.txt b/clang/lib/CodeGen/CMakeLists.txt index ad9ef91c781a8..c41d5c1574ea5 100644 --- a/clang/lib/CodeGen/CMakeLists.txt +++ b/clang/lib/CodeGen/CMakeLists.txt @@ -61,6 +61,7 @@ add_clang_library(clangCodeGen CGAtomic.cpp CGBlocks.cpp CGBuiltin.cpp + CGEmitEmissaryExec.cpp CGCUDANV.cpp CGCUDARuntime.cpp CGCXX.cpp diff --git a/clang/lib/CodeGen/CodeGenAction.cpp b/clang/lib/CodeGen/CodeGenAction.cpp index 60d6b7fa009e7..c395a1fa24cd6 100644 --- a/clang/lib/CodeGen/CodeGenAction.cpp +++ b/clang/lib/CodeGen/CodeGenAction.cpp @@ -44,6 +44,7 @@ #include "llvm/IRReader/IRReader.h" #include "llvm/LTO/LTOBackend.h" #include "llvm/Linker/Linker.h" +#include "llvm/Object/Archive.h" #include "llvm/Pass.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" @@ -963,10 +964,81 @@ CodeGenAction::CreateASTConsumer(CompilerInstance &CI, StringRef InFile) { if (BA != Backend_EmitNothing && !OS) return nullptr; - // Load bitcode modules to link with, if we need to. if (loadLinkModules(CI)) return nullptr; + // Load bitcode modules to link with, if we need to. + if (LinkModules.empty()) + for (const CodeGenOptions::BitcodeFileToLink &F : + CI.getCodeGenOpts().LinkBitcodeFiles) { + auto BCBuf = CI.getFileManager().getBufferForFile(F.Filename); + if (!BCBuf) { + CI.getDiagnostics().Report(diag::err_cannot_open_file) + << F.Filename << BCBuf.getError().message(); + LinkModules.clear(); + return nullptr; + } + + if (StringRef(F.Filename).ends_with(".a")) { + // Handle Archive file + Error Err = Error::success(); + llvm::object::Archive Archive(BCBuf.get()->getMemBufferRef(), Err); + llvm::object::Archive *ArchivePtr = &Archive; + + if (Err) { + auto EC = errorToErrorCode(std::move(Err)); + CI.getDiagnostics().Report(diag::err_cannot_open_file) + << F.Filename << EC.message(); + LinkModules.clear(); + return nullptr; + } + for (auto &C : ArchivePtr->children(Err)) { + Expected MemBufRef = C.getMemoryBufferRef(); + if (MemBufRef.takeError()) { + CI.getDiagnostics().Report(diag::err_cannot_open_file) + << F.Filename; + LinkModules.clear(); + return nullptr; + } + + auto ChildBuf = llvm::MemoryBuffer::getMemBufferCopy( + MemBufRef.get().getBuffer(), + MemBufRef.get().getBufferIdentifier()); + Expected> ModuleOrErr = + getOwningLazyBitcodeModule(std::move(ChildBuf), *VMContext); + if (!ModuleOrErr) { + handleAllErrors(ModuleOrErr.takeError(), [&](ErrorInfoBase &EIB) { + CI.getDiagnostics().Report(diag::err_cannot_open_file) + << F.Filename << EIB.message(); + }); + LinkModules.clear(); + return nullptr; + } + LinkModules.push_back({std::move(ModuleOrErr.get()), F.PropagateAttrs, + F.Internalize, F.LinkFlags}); + } // end for each child + + if (std::move(Err)) { + CI.getDiagnostics().Report(diag::err_cannot_open_file) << F.Filename; + LinkModules.clear(); + return nullptr; + } + } else { + // Single .bc file + Expected> ModuleOrErr = + getOwningLazyBitcodeModule(std::move(*BCBuf), *VMContext); + if (!ModuleOrErr) { + handleAllErrors(ModuleOrErr.takeError(), [&](ErrorInfoBase &EIB) { + CI.getDiagnostics().Report(diag::err_cannot_open_file) + << F.Filename << EIB.message(); + }); + LinkModules.clear(); + return nullptr; + } + LinkModules.push_back({std::move(ModuleOrErr.get()), F.PropagateAttrs, + F.Internalize, F.LinkFlags}); + } + } CoverageSourceInfo *CoverageInfo = nullptr; // Add the preprocessor callback only when the coverage mapping is generated. if (CI.getCodeGenOpts().CoverageMapping) diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 8c4c1c8c2dc95..90ced670d33e1 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -45,6 +45,8 @@ #include "llvm/Transforms/Utils/SanitizerStats.h" #include +#define NO_LOOP_XTEAM_RED "no-loop-xteam-red" + namespace llvm { class BasicBlock; class ConvergenceControlInst; @@ -3030,6 +3032,10 @@ class CodeGenFunction : public CodeGenTypeCache { AggValueSlot::Overlap_t MayOverlap, bool isVolatile = false); + bool hasAddrOfLocalVar(const VarDecl *VD) { + return LocalDeclMap.find(VD) != LocalDeclMap.end(); + } + /// GetAddrOfLocalVar - Return the address of a local variable. Address GetAddrOfLocalVar(const VarDecl *VD) { auto it = LocalDeclMap.find(VD); @@ -3514,11 +3520,13 @@ class CodeGenFunction : public CodeGenTypeCache { static ParamValue forDirect(llvm::Value *value) { return ParamValue(value); } - static ParamValue forIndirect(Address addr) { + static ParamValue forIndirect(Address addr, + std::optional
DebugAddr = std::nullopt) { assert(!addr.getAlignment().isZero()); return ParamValue(addr); } + std::optional
DebugAddr; bool isIndirect() const { return IsIndirect; } llvm::Value *getAnyValue() const { if (!isIndirect()) @@ -3536,6 +3544,8 @@ class CodeGenFunction : public CodeGenTypeCache { assert(isIndirect()); return Addr; } + + std::optional
getDebugAddr() const { return DebugAddr; } }; /// EmitParmDecl - Emit a ParmVarDecl or an ImplicitParamDecl. @@ -3586,6 +3596,61 @@ class CodeGenFunction : public CodeGenTypeCache { /// calling EmitBlock, EmitBranch, or EmitStmt. void EmitStmt(const Stmt *S, ArrayRef Attrs = {}); + /// EmitOptKernel - For an OpenMP target directive, emit the optimized + /// kernel code assuming that related runtime environment variables + /// can be ignored. This function should be called after ensuring that + /// legality conditions for a no-loop kernel are met. There are 3 kinds of + /// optimized kernels that may be generated: No-Loop, Big-Jump-Loop, and Xteam + /// reduction. + void EmitOptKernel(const OMPExecutableDirective &D, + const ForStmt *CapturedForStmt, + llvm::omp::OMPTgtExecModeFlags OptKernelMode, + SourceLocation Loc, const FunctionArgList *Args); + + void EmitOptKernelCode(const OMPExecutableDirective &D, + const ForStmt *CapturedForStmt, + llvm::omp::OMPTgtExecModeFlags OptKernelMode, + SourceLocation Loc, const FunctionArgList *Args); + + void EmitNoLoopCode(const OMPExecutableDirective &D, + const ForStmt *CapturedForStmt, SourceLocation Loc, + const FunctionArgList *Args); + + void EmitBigJumpLoopCode(const OMPExecutableDirective &D, + const ForStmt *CapturedForStmt, SourceLocation Loc, + const FunctionArgList *Args); + + void EmitXteamRedCode(const OMPExecutableDirective &D, + const ForStmt *CapturedForStmt, SourceLocation Loc, + const FunctionArgList *Args); + + void EmitNoLoopXteamScanInit(const OMPLoopDirective &D, + const ForStmt *CapturedForStmt, + const FunctionArgList *Args, + llvm::Value *&GpuThreadId, + llvm::Value *&GlobalGpuThreadId, + llvm::Value *&WorkGroupId, + llvm::Value *&TotalNumThreads); + + void EmitNoLoopXteamScanPhaseOneCode(const OMPExecutableDirective &D, + const ForStmt *CapturedForStmt, + SourceLocation Loc, + const FunctionArgList *Args); + + void EmitNoLoopXteamScanPhaseTwoCode(const OMPExecutableDirective &D, + const ForStmt *CapturedForStmt, + SourceLocation Loc, + const FunctionArgList *Args); + + /// Used in No-Loop and Xteam codegen to emit the loop iteration and the + /// associated variables. Returns the loop iteration variable and its address. + std::pair EmitNoLoopIV(const OMPLoopDirective &LD, + const FunctionArgList *Args); + + /// Emit updates of the original loop indices. Used by both + /// BigJumpLoop and Xteam reduction kernel codegen. + void EmitBigJumpLoopUpdates(const ForStmt &FStmt); + /// EmitSimpleStmt - Try to emit a "simple" statement which does not /// necessarily require an insertion point or debug information; typically /// because the statement amounts to a jump or a container of other @@ -3613,6 +3678,8 @@ class CodeGenFunction : public CodeGenTypeCache { void EmitWhileStmt(const WhileStmt &S, ArrayRef Attrs = {}); void EmitDoStmt(const DoStmt &S, ArrayRef Attrs = {}); void EmitForStmt(const ForStmt &S, ArrayRef Attrs = {}); + void EmitForStmtWithArgs(const ForStmt &S, const FunctionArgList *Args, + ArrayRef Attrs = {}); void EmitReturnStmt(const ReturnStmt &S); void EmitDeclStmt(const DeclStmt &S); void EmitBreakStmt(const BreakStmt &S); @@ -3709,11 +3776,23 @@ class CodeGenFunction : public CodeGenTypeCache { llvm::Function *EmitCapturedStmt(const CapturedStmt &S, CapturedRegionKind K); llvm::Function *GenerateCapturedStmtFunction(const CapturedStmt &S); Address GenerateCapturedStmtArgument(const CapturedStmt &S); - llvm::Function * - GenerateOpenMPCapturedStmtFunction(const CapturedStmt &S, - const OMPExecutableDirective &D); + llvm::Function *GenerateOpenMPCapturedStmtFunction( + const CapturedStmt &S, const OMPExecutableDirective &D, + bool TopLevel, bool IsTopKernel); void GenerateOpenMPCapturedVars(const CapturedStmt &S, - SmallVectorImpl &CapturedVars); + SmallVectorImpl &CapturedVars, + const Stmt *XteamRedNestKey); + void GenerateOpenMPCapturedVarsDevice( + const CapturedStmt &S, SmallVectorImpl &CapturedVars, + SmallVectorImpl &MultiTargetVars, + const Stmt *XteamRedNestKey); + void + InitializeXteamRedCapturedVars(SmallVectorImpl &CapturedVars, + QualType RedVarQualType); + /// Generate the sentinel (referred to as the reduction null value in + /// DeviceRTL) based on the reduction opcode. + llvm::Value *getXteamRedSentinel(llvm::Type *RedVarType, + CodeGenModule::XteamRedOpKind Opcode); void emitOMPSimpleStore(LValue LVal, RValue RVal, QualType RValTy, SourceLocation Loc); /// Perform element by element copying of arrays with type \a @@ -3753,12 +3832,14 @@ class CodeGenFunction : public CodeGenTypeCache { /// \param AO Atomic ordering of the generated atomic instructions. /// \param CommonGen Code generator for complex expressions that cannot be /// expressed through atomicrmw instruction. + /// \param Hint OpenMP atomic hint expression /// \returns if simple 'atomicrmw' instruction was /// generated, otherwise. std::pair EmitOMPAtomicSimpleUpdateExpr( LValue X, RValue E, BinaryOperatorKind BO, bool IsXLHSInRHSPart, llvm::AtomicOrdering AO, SourceLocation Loc, - const llvm::function_ref CommonGen); + const llvm::function_ref CommonGen, + const Expr *Hint = nullptr); bool EmitOMPFirstprivateClause(const OMPExecutableDirective &D, OMPPrivateScope &PrivateScope); void EmitOMPPrivateClause(const OMPExecutableDirective &D, @@ -3955,8 +4036,9 @@ class CodeGenFunction : public CodeGenTypeCache { const OMPTargetTeamsDistributeParallelForSimdDirective &S); void EmitOMPTargetTeamsDistributeSimdDirective( const OMPTargetTeamsDistributeSimdDirective &S); - void EmitOMPGenericLoopDirective(const OMPGenericLoopDirective &S); - void EmitOMPParallelGenericLoopDirective(const OMPLoopDirective &S); + void EmitOMPGenericLoopDirective(const OMPLoopDirective &S); + void EmitOMPParallelGenericLoopDirective( + const OMPLoopDirective &S); void EmitOMPTargetParallelGenericLoopDirective( const OMPTargetParallelGenericLoopDirective &S); void EmitOMPTargetTeamsGenericLoopDirective( @@ -4044,6 +4126,22 @@ class CodeGenFunction : public CodeGenTypeCache { const llvm::function_ref BodyGen, const llvm::function_ref PostIncGen); + /// Emit inner loop of the worksharing/simd construct. + /// + /// \param S Directive, for which the inner loop must be emitted. + /// \param RequiresCleanup true, if directive has some associated private + /// variables. + /// \param LoopCond Bollean condition for loop continuation. + /// \param IncExpr Increment expression for loop control variable. + /// \param BodyGen Generator for the inner body of the inner loop. + /// \param PostIncGen Genrator for post-increment code (required for ordered + /// loop directvies). + void EmitOMPMultiDeviceInnerLoop( + const OMPExecutableDirective &S, bool RequiresCleanup, + const Expr *LoopCond, const Expr *IncExpr, const VarDecl *IVDecl, + const llvm::function_ref BodyGen, + const llvm::function_ref PostIncGen); + JumpDest getOMPCancelDestination(OpenMPDirectiveKind Kind); /// Emit initial code for loop counters of loop-based directives. void EmitOMPPrivateLoopCounters(const OMPLoopDirective &S, @@ -4052,6 +4150,11 @@ class CodeGenFunction : public CodeGenTypeCache { /// Helper for the OpenMP loop directives. void EmitOMPLoopBody(const OMPLoopDirective &D, JumpDest LoopExit); + /// Helper for OpenMP NoLoop kernel CodeGen + void EmitOMPNoLoopBody(const OMPLoopDirective &D); + + void EmitOMPXteamScanNoLoopBody(const OMPLoopDirective &D); + /// Emit code for the worksharing loop-based directive. /// \return true, if this construct has any lastprivate clause, false - /// otherwise. @@ -4703,8 +4806,12 @@ class CodeGenFunction : public CodeGenTypeCache { ReturnValueSlot ReturnValue, llvm::CallBase **CallOrInvoke); - RValue EmitNVPTXDevicePrintfCallExpr(const CallExpr *E); - RValue EmitAMDGPUDevicePrintfCallExpr(const CallExpr *E); + RValue EmitNVPTXDevicePrintfCallExpr(const CallExpr *E, + ReturnValueSlot ReturnValue); + RValue EmitAMDGPUDevicePrintfCallExpr(const CallExpr *E, + ReturnValueSlot ReturnValue); + + RValue EmitEmissaryExec(const CallExpr *E); RValue EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, const CallExpr *E, ReturnValueSlot ReturnValue); @@ -5550,6 +5657,48 @@ class CodeGenFunction : public CodeGenTypeCache { llvm::Value *EmitX86CpuSupports(ArrayRef FeatureStrs); llvm::Value *EmitX86CpuSupports(std::array FeatureMask); llvm::Value *EmitX86CpuInit(); + + llvm::Value *applyNoLoopInc(const Expr *Inc, const VarDecl *IVDecl, + llvm::Value *CurrVal); + /// Emit the starting index of a BigJumpLoop which is used in + /// BigJumpLoop and Xteam reduction kernels. + std::pair + EmitBigJumpLoopStartingIndex(const ForStmt &FStmt, + const FunctionArgList *Args); + /// Emit the increment of a BigJumpLoop which is used in BigJumpLoop + /// and Xteam reduction kernels. + void EmitBigJumpLoopInc(const ForStmt &FStmt, const VarDecl *LoopVar, + const Address &NoLoopIvAddr); + /// For every reduction variable, emit the corresponding locally introducted + /// variable and initialize it. + void EmitXteamLocalAggregator(const ForStmt *FStmt); + /// For every sum/min/max reduction variable, emit a call to the DeviceRTL + /// API. + void EmitXteamRedOperation(const ForStmt *FStmt, const FunctionArgList &Args, + int BlockSize); + /// For every scan reduction variable, emit a call to the DeviceRTL API. + void EmitXteamScanSum(const ForStmt *FStmt, const FunctionArgList &Args, + int BlockSize); + /// For every scan reduction variable, emit a call to the DeviceRTL API + /// required for phase 2 kernel. + void EmitXteamScanPhaseTwo(const ForStmt *FStmt, llvm::Value *SegmentSize, + const FunctionArgList &Args, int BlockSize, + bool IsInclusiveScan); + /// Emit reduction into local variable for a statement within the BigJumpLoop. + bool EmitXteamRedStmt(const Stmt *S); + /// Emit reduction into local variable for a statement within the BigJumpLoop. + void EmitLocalReductionStmt(const Expr *E, const VarDecl *RedVarDecl, + const CodeGenModule::XteamRedVarMap &RedVarMap, + CodeGenModule::XteamRedOpKind OpKind); + /// Helper function that extracts the other operand of the reduction + /// operation. + std::pair + ExtractXteamRedRhsExpr(const CallExpr *Call, const VarDecl *RedVarDecl); + /// Emitter for reduction builtins recognized by Xteam reduction, currently + /// min/max. + void EmitXteamRedStmtForBuiltinCall( + const CallExpr *Call, const VarDecl *RedVarDecl, + const CodeGenModule::XteamRedVarMap &RedVarMap); llvm::Value *FormX86ResolverCondition(const FMVResolverOption &RO); llvm::Value *EmitAArch64CpuInit(); llvm::Value *FormAArch64ResolverCondition(const FMVResolverOption &RO); diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 0fea57b2e1799..56a1cc8d6ed2f 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -41,6 +41,7 @@ #include "clang/Basic/CodeGenOptions.h" #include "clang/Basic/Diagnostic.h" #include "clang/Basic/Module.h" +#include "clang/Basic/OpenMPKinds.h" #include "clang/Basic/SourceManager.h" #include "clang/Basic/TargetInfo.h" #include "clang/Basic/Version.h" @@ -51,6 +52,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/Analysis/TargetLibraryInfo.h" +#include "llvm/Frontend/OpenMP/OMPDeviceConstants.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/IR/AttributeMask.h" #include "llvm/IR/CallingConv.h" @@ -65,6 +67,7 @@ #include "llvm/Support/CodeGen.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ConvertUTF.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TimeProfiler.h" #include "llvm/Support/xxhash.h" @@ -77,6 +80,7 @@ using namespace clang; using namespace CodeGen; +using namespace llvm::omp::xteam_red; static llvm::cl::opt LimitedCoverage( "limited-coverage-experimental", llvm::cl::Hidden, @@ -3335,14 +3339,17 @@ static void emitUsed(CodeGenModule &CGM, StringRef Name, SmallVector UsedArray; UsedArray.resize(List.size()); for (unsigned i = 0, e = List.size(); i != e; ++i) { - UsedArray[i] = - llvm::ConstantExpr::getPointerBitCastOrAddrSpaceCast( - cast(&*List[i]), CGM.Int8PtrTy); + UsedArray[i] = llvm::ConstantExpr::getPointerBitCastOrAddrSpaceCast( + cast(&*List[i]), + CGM.getTarget().getTriple().isAMDGCN() ? + llvm::PointerType::getUnqual(CGM.getLLVMContext()) : + CGM.Int8PtrTy); } if (UsedArray.empty()) return; - llvm::ArrayType *ATy = llvm::ArrayType::get(CGM.Int8PtrTy, UsedArray.size()); + llvm::ArrayType *ATy = llvm::ArrayType::get(UsedArray.front()->getType(), + UsedArray.size()); auto *GV = new llvm::GlobalVariable( CGM.getModule(), ATy, false, llvm::GlobalValue::AppendingLinkage, @@ -8258,6 +8265,1785 @@ void CodeGenModule::printPostfixForExternalizedDecl(llvm::raw_ostream &OS, } } +namespace { +/// A 'teams loop' with a nested 'loop bind(parallel)' or generic function +/// call in the associated loop-nest cannot be a 'parllel for'. +class TeamsLoopChecker final : public ConstStmtVisitor { +public: + TeamsLoopChecker(CodeGenModule &CGM) + : CGM(CGM), TeamsLoopCanBeParallelFor{true} {} + bool teamsLoopCanBeParallelFor() const { + return TeamsLoopCanBeParallelFor; + } + // Is there a nested OpenMP loop bind(parallel) + void VisitOMPExecutableDirective(const OMPExecutableDirective *D) { + if (D->getDirectiveKind() == llvm::omp::Directive::OMPD_loop) { + if (const auto *C = D->getSingleClause()) + if (C->getBindKind() == OMPC_BIND_parallel) { + TeamsLoopCanBeParallelFor = false; + // No need to continue visiting any more + return; + } + } + for (const Stmt *Child : D->children()) + if (Child) + Visit(Child); + } + + void VisitCallExpr(const CallExpr *C) { + // Function calls inhibit parallel loop translation of 'target teams loop' + // unless the assume-no-nested-parallelism flag has been specified. + // OpenMP API runtime library calls do not inhibit parallel loop + // translation, regardless of the assume-no-nested-parallelism. + if (C) { + bool IsOpenMPAPI = false; + auto *FD = dyn_cast_or_null(C->getCalleeDecl()); + if (FD) { + std::string Name = FD->getNameInfo().getAsString(); + IsOpenMPAPI = Name.find("omp_") == 0; + } + TeamsLoopCanBeParallelFor = + IsOpenMPAPI || CGM.getLangOpts().OpenMPNoNestedParallelism; + if (!TeamsLoopCanBeParallelFor) + return; + } + for (const Stmt *Child : C->children()) + if (Child) + Visit(Child); + } + + void VisitCapturedStmt(const CapturedStmt *S) { + if (!S) + return; + Visit(S->getCapturedDecl()->getBody()); + } + + void VisitStmt(const Stmt *S) { + if (!S) + return; + for (const Stmt *Child : S->children()) + if (Child) + Visit(Child); + } + +private: + CodeGenModule &CGM; + bool TeamsLoopCanBeParallelFor; +}; +} // namespace + +/// Determine if 'teams loop' can be emitted using 'parallel for'. +bool CodeGenModule::TeamsLoopCanBeParallelFor(const OMPExecutableDirective &D) { + if (D.getDirectiveKind() != llvm::omp::Directive::OMPD_target_teams_loop) + return false; + assert(D.hasAssociatedStmt() && + "Loop directive must have associated statement."); + TeamsLoopChecker Checker(*this); + Checker.Visit(D.getAssociatedStmt()); + return Checker.teamsLoopCanBeParallelFor(); +} + +namespace { +class NoLoopChecker final : public ConstStmtVisitor { +public: + NoLoopChecker(CodeGenModule &CGM) + : CGM(CGM), NoLoopCheckStatus(CodeGenModule::NxSuccess), + HasNestedGenericCall(false) {} + CodeGenModule::NoLoopXteamErr getNoLoopCheckStatus() const { + return NoLoopCheckStatus; + } + bool hasNestedGenericCall() const { return HasNestedGenericCall; } + + // Reject if there is a nested OpenMP parallel directive + void VisitOMPExecutableDirective(const OMPExecutableDirective *D) { + switch (D->getDirectiveKind()) { + case llvm::omp::Directive::OMPD_parallel: + case llvm::omp::Directive::OMPD_parallel_do: + case llvm::omp::Directive::OMPD_parallel_do_simd: + case llvm::omp::Directive::OMPD_parallel_for: + case llvm::omp::Directive::OMPD_parallel_for_simd: + case llvm::omp::Directive::OMPD_parallel_master: + case llvm::omp::Directive::OMPD_parallel_master_taskloop: + case llvm::omp::Directive::OMPD_parallel_master_taskloop_simd: + case llvm::omp::Directive::OMPD_parallel_sections: + case llvm::omp::Directive::OMPD_parallel_workshare: { + NoLoopCheckStatus = CodeGenModule::NxNestedOmpParallelDirective; + // No need to continue visiting any more + return; + } + default: + break; + } + for (const Stmt *Child : D->children()) + if (Child) + Visit(Child); + } + + // Reject if there is a call to an OpenMP API function, omp_*. + // If an OpenMP API call is not found and a call to an Xteam-recognized + // math function is not found, the field HasNestedGenericCall is set. It + // is the job of the client to make use of these attributes. + void VisitCallExpr(const CallExpr *C) { + // Set status if calling an OpenMP API + // Set status if there is a call other than to an OpenMP function. + if (C) { + auto *FD = dyn_cast_or_null(C->getCalleeDecl()); + if (FD) { + std::string Name = FD->getNameInfo().getAsString(); + if (Name.find("omp_") == 0) { + NoLoopCheckStatus = CodeGenModule::NxNestedOmpCall; + // No need to continue visiting any more + return; + } + // Recognize the math calls. If the math calls are wrapped in + // a PseudoObject expression, they are handled in the corresponding + // visitor. + if (CGM.getStatusOptKernelBuiltin(C) != CodeGenModule::NxSuccess) + HasNestedGenericCall = true; + } else + HasNestedGenericCall = true; + } + for (const Stmt *Child : C->children()) + if (Child) + Visit(Child); + } + + void VisitPseudoObjectExpr(const PseudoObjectExpr *PO) { + // Check the PO specific conditions and then visit the semantic expression. + auto [Status, SemanticExpr] = CGM.getStatusXteamSupportedPseudoObject(PO); + if (Status) { + NoLoopCheckStatus = Status; + return; // no need to continue any more + } + for (const Stmt *Child : PO->children()) + if (Child) { + if (!isa(Child)) { + NoLoopCheckStatus = CodeGenModule::NxUnsupportedPseudoObject; + return; + } + if (cast(Child) == SemanticExpr) + Visit(Child); + } + } + + void VisitCapturedStmt(const CapturedStmt *S) { + if (!S) + return; + Visit(S->getCapturedDecl()->getBody()); + } + + void VisitStmt(const Stmt *S) { + if (!S) + return; + for (const Stmt *Child : S->children()) + if (Child) + Visit(Child); + } + +private: + CodeGenModule &CGM; + CodeGenModule::NoLoopXteamErr NoLoopCheckStatus; + // If no omp_ API call is found, is a generic call found? + bool HasNestedGenericCall; +}; + +/// Ensure no-loop codegen can handle the step. The visitor will reject any +/// expression that contains the loop index provided +class NoLoopStepChecker final : public ConstStmtVisitor { +public: + NoLoopStepChecker(const VarDecl *LV) : LoopVar{LV}, UnsupportedStep{false} {} + NoLoopStepChecker() = delete; + + bool isUnsupported() const { return UnsupportedStep; } + + void VisitDeclRefExpr(const DeclRefExpr *DRE) { + // We do not handle an expression with the loop var + if (DRE && DRE->getDecl() == LoopVar) { + UnsupportedStep = true; + // No need to continue any more + return; + } + for (const Stmt *Child : DRE->children()) + if (Child) + Visit(Child); + } + + void VisitStmt(const Stmt *S) { + if (!S) + return; + for (const Stmt *Child : S->children()) + if (Child) + Visit(Child); + } + +private: + const VarDecl *LoopVar; + bool UnsupportedStep; +}; + +/// Ensure xteam reduction codegen can handle the statements in the kernel loop. +/// The visitor will reject any assignment statement if it finds a reduction +/// variable as the lhs of an assignment statement but not of the following +/// form: red_var += red_var = red_var + red_var = + +/// red_var. +/// If a reference to a reduction variable is passed to a function +/// at a top statement level of the kernel, XteamReduction can handle it as +/// well. +class XteamRedExprChecker final : public ConstStmtVisitor { +public: + XteamRedExprChecker(CodeGenModule &CGM, CodeGenModule::XteamRedVarMap *RVM) + : CGM(CGM), RedMap(RVM), IsAtTopLevel(true), + NxStatus(CodeGenModule::NxSuccess) {} + XteamRedExprChecker() = delete; + + CodeGenModule::NoLoopXteamErr getNxStatus() const { return NxStatus; } + + void VisitStmt(const Stmt *S) { + if (!S) + return; + + if (isa(S)) { + // Ensure that the reduction assignment uses a pattern Codegen + // can handle. For sum-reduction, + // Codegen currently handles red-var += , + // red-var = red-var + and red-var = + red-var. + // We punt on anything more complex. + const BinaryOperator *BinOpExpr = cast(S); + const Expr *LHS = BinOpExpr->getLHS()->IgnoreImpCasts(); + auto BinOpExprOp = BinOpExpr->getOpcode(); + // Get the reduction variable, if any, from the LHS. + const VarDecl *RedVarDecl = CGM.getXteamRedVarDecl(LHS, *RedMap); + if (RedVarDecl != nullptr) { // LHS accesses a reduction variable. + if (BinOpExprOp == BO_Assign || BinOpExprOp == BO_AddAssign) { + IsAtTopLevel = true; + const Expr *RHS = BinOpExpr->getRHS()->IgnoreImpCasts(); + // If operator +=, reject if RHS accesses any reduction variable. + if (BinOpExprOp == BO_AddAssign) { + // Set reduction opcode to sum. + CGM.updateXteamRedVarOpcode(RedVarDecl, RedMap, + CodeGenModule::XR_OP_add); + ValidateChildren(RHS); + if (NxStatus != CodeGenModule::NxSuccess) + return; + } else { // BinOpExprOp == BO_Assign + if (isa(RHS)) { + const BinaryOperator *BinOpRHS = cast(RHS); + if (BinOpRHS->getOpcode() == BO_Add) { + // Set reduction opcode to sum. + CGM.updateXteamRedVarOpcode(RedVarDecl, RedMap, + CodeGenModule::XR_OP_add); + const Expr *LHSBinOpRHS = BinOpRHS->getLHS()->IgnoreImpCasts(); + const Expr *RHSBinOpRHS = BinOpRHS->getRHS()->IgnoreImpCasts(); + // If LHS is the reduction variable, the RHS must not access any + // reduction variable. Similarly, vice-versa for RHS. + if (CGM.isXteamRedVarExpr(LHSBinOpRHS, RedVarDecl)) + ValidateChildren(RHSBinOpRHS); + else if (CGM.isXteamRedVarExpr(RHSBinOpRHS, RedVarDecl)) + ValidateChildren(LHSBinOpRHS); + else // Neither LHS nor RHS is the reduction variable. + NxStatus = CodeGenModule::NxNotRedVarInBinOpRHS; + if (NxStatus != CodeGenModule::NxSuccess) + return; + } else { // Not an add binary operator in the RHS for an + // assignment statement. + NxStatus = CodeGenModule::NxNotAddOpInBinOpRHs; + return; + } + } else if (IsAtTopLevel && + (isa(RHS) || isa(RHS))) { + // If a PseudoObjectExpr is found, check if it is supported by + // Xteam. + if (isa(RHS)) { + auto [Status, ReturnExpr] = + CGM.getStatusXteamSupportedPseudoObject( + cast(RHS)); + if (Status) { + NxStatus = Status; + return; + } + RHS = ReturnExpr; + } + const CallExpr *Call = cast(RHS); + if ((NxStatus = CGM.getStatusOptKernelBuiltin(Call))) + return; + // For both host and device compile, check the arguments for + // constraints on the reduction variable. + validateArgConstraints(Call); + if (NxStatus != CodeGenModule::NxSuccess) + return; + // A min or max operator has been identified. Add the operator to + // the reduction map. + CGM.updateXteamRedVarOpcode(Call, RedVarDecl, RedMap); + } else { // RHS is not a binary operator or call for assignment. + NxStatus = CodeGenModule::NxRhsOfAssignNotBinOpOrCall; + return; + } + } + } else { // Binary operator is neither +=, nor =. + NxStatus = CodeGenModule::NxBinOpNotAddAssignOrAssign; + return; + } + } else { // LHS of binary operator does not access any reduction variable. + // Ensure that RHS does not access any reduction variable either. Be + // paranoid, validate the LHS as well. + ValidateChildren(S); + if (NxStatus != CodeGenModule::NxSuccess) + return; + } + if (IsAtTopLevel) + IsAtTopLevel = false; + } // End of binary operator handling. + // Allow a call at the top level with a reduction variable passed by + // reference. + else if (IsAtTopLevel && isa(S)) { + IsAtTopLevel = false; + validateArgConstraints(cast(S)); + if (NxStatus != CodeGenModule::NxSuccess) + return; + } // End of call expression handling. + else if (isa(S)) { + IsAtTopLevel = false; + // Not a binary operator or call, so not supported at this point. So + // ensure no reduction variable is accessed. Disable this check for Xteam + // scan because the RedVar could be read in the form of RHS of a binary + // operator. + if (CGM.hasXteamRedVar(cast(S), *RedMap) && + !CGM.isXteamScanKernel()) { + NxStatus = CodeGenModule::NxNotBinOpOrCallButAccessesRedVar; + return; + } + } // End of DeclRefExpr handling. + else { + IsAtTopLevel = false; + // Recursively check the children. + ValidateChildren(S); + if (NxStatus != CodeGenModule::NxSuccess) + return; + } + } + void ValidateChildren(const Stmt *S) { + for (auto Child : S->children()) + if (Child) { + Visit(Child); + if (NxStatus != CodeGenModule::NxSuccess) + return; + } + } + void validateArgConstraints(const CallExpr *Call) { + for (auto Child : Call->children()) { + if (!Child) { + NxStatus = CodeGenModule::NxChildOfCallIsNull; + return; + } + // If it is not a variable reference, recurse. If it is a + // variable reference, it will be appropriately handled + // during codegen, i.e. replaced with XteamReduction + // variable, if required. + while (isa(Child)) + Child = cast(Child)->getSubExpr(); + if (!isa(Child)) { + // Ensure that no reduction variable appears in Child. + Visit(Child); + } + if (NxStatus != CodeGenModule::NxSuccess) + return; + } + CodeGenFunction CGF(CGM); + for (unsigned ArgIndex = 0; ArgIndex < Call->getNumArgs(); ++ArgIndex) { + const Expr *Arg = Call->getArg(ArgIndex); + if (!Arg || !CGF.hasScalarEvaluationKind(Arg->getType())) { + NxStatus = CodeGenModule::NxNotArgScalarEval; + return; + } + } + } + +private: + CodeGenModule &CGM; + /// Map of reduction variables for this directive. This visitor may update + /// this map with the reduction operator. + CodeGenModule::XteamRedVarMap *RedMap; + /// Indicates whether the current analyzed statement is at the top level + /// statement list in the kernel. Set to true when the visitor is called first + /// and reset to false before visiting any children. There are certain + /// patterns that are supported at the top level but not otherwise. + bool IsAtTopLevel; + /// Set to corresponding status if codegen does not support the reduction + /// expression found in this kernel. + CodeGenModule::NoLoopXteamErr NxStatus; +}; + +} // namespace + +void CodeGenModule::emitNxResult(std::string StatusMsg, + const OMPExecutableDirective &D, + NoLoopXteamErr Status) { + if (Status) + StatusMsg += ": Failed: "; + else + StatusMsg += ": Succeeded"; + switch (Status) { + case NxSuccess: + break; + case NxNonSPMD: + StatusMsg += "Non-SPMD mode not supported"; + break; + case NxOptionDisabled: + StatusMsg += "Command line option disabled"; + break; + case NxOptionDisabledOrHasCall: + StatusMsg += "Command line option disabled or has a nested call"; + break; + case NxUnsupportedDirective: + StatusMsg += "Unsupported directive"; + break; + case NxUnsupportedSplitDirective: + StatusMsg += "Unsupported split directive"; + break; + case NxNoStmt: + StatusMsg += "No statement found"; + break; + case NxUnsupportedTargetClause: + StatusMsg += "Unsupported target clause"; + break; + case NxNotLoopDirective: + StatusMsg += "Not a loop directive"; + break; + case NxNotCapturedStmt: + StatusMsg += "Not a captured statement"; + break; + case NxNotExecutableStmt: + StatusMsg += "Not an executable directive"; + break; + case NxUnsupportedNestedSplitDirective: + StatusMsg += "Unsupported nested split directive"; + break; + case NxSplitConstructImproperlyNested: + StatusMsg += "Improperly nested split construct"; + break; + case NxNestedOmpParallelDirective: + StatusMsg += "Nested OpenMP parallel directive"; + break; + case NxNestedOmpCall: + StatusMsg += "Nested OpenMP API call"; + break; + case NxNoSingleForStmt: + StatusMsg += "Could not find a single FOR statement"; + break; + case NxUnsupportedLoopInit: + StatusMsg += "Unsupported loop initialization expression"; + break; + case NxUnsupportedLoopStop: + StatusMsg += "Unsupported loop condition expression"; + break; + case NxUnsupportedLoopStep: + StatusMsg += "Unsupported loop increment expression"; + break; + case NxGuidedOrRuntimeSched: + StatusMsg += "Guided or runtime schedule not supported"; + break; + case NxNonUnitStaticChunk: + StatusMsg += "Schedule clause with non-unit chunk size"; + break; + case NxNonConcurrentOrder: + StatusMsg += "Non-concurrent order not supported"; + break; + case NxUnsupportedRedType: + StatusMsg += "Unsupported reduction variable type"; + break; + case NxUnsupportedRedIntSize: + StatusMsg += + "Integer reduction variable with the specified size not supported"; + break; + case NxNotScalarRed: + StatusMsg += "Non-scalar reduction variable"; + break; + case NxNotBinOpRed: + StatusMsg += "Only binary reduction operator supported"; + break; + case NxUnsupportedRedOp: + StatusMsg += "Unsupported reduction operator"; + break; + case NxNoRedVar: + StatusMsg += "No reduction variable found"; + break; + case NxMultRedVar: + StatusMsg += "Multiple reduction variables in the same loop not supported"; + break; + case NxUnsupportedRedExpr: + StatusMsg += "Unsupported reduction expression found"; + break; + case NxUnsupportedXteamRedThreadLimit: + StatusMsg += "Thread Limit less than 256 not supported"; + break; + case NxUnsupportedPseudoObject: + StatusMsg += "Unsupported pseudo object found"; + break; + case NxNotRedVarInBinOpRHS: + StatusMsg += "Reduction variable not found in RHS of binary operator"; + break; + case NxNotAddOpInBinOpRHs: + StatusMsg += "Add operator not found in RHS of binary operator"; + break; + case NxRhsOfAssignNotBinOpOrCall: + StatusMsg += "RHS of assignment is not a binary operator or call"; + break; + case NxBinOpNotAddAssignOrAssign: + StatusMsg += "Binary operator is neither += nor ="; + break; + case NxNotBinOpOrCallButAccessesRedVar: + StatusMsg += + "RHS is not binary operator or call but accesses reduction variable"; + break; + case NxNotArgScalarEval: + StatusMsg += "Arg of call does not evaluate to scalar"; + break; + case NxReductionOpNotBinAssign: + StatusMsg += "Reduction ops not binary assignment"; + break; + case NxReductionOpRhsNotBinOrCond: + StatusMsg += "Reduction ops rhs is not binary or conditional operator"; + break; + case NxReductionOpRhsNotMinMaxSum: + StatusMsg += "Reduction ops rhs is not sum, min, or max"; + break; + case NxNotBuiltinByNameInHostCompile: + StatusMsg += "Not recognized as builtin in host compile"; + break; + case NxNotBuiltinByNameInDeviceCompile: + StatusMsg += "Not recognized as builtin in device compile"; + break; + case NxPOExprCountNotOne: + StatusMsg += "Non-unit pseudo-expression count"; + break; + case NxPOSemanticExprNotCall: + StatusMsg += "Pseudo-expression semantic expression is not a call"; + break; + case NxChildOfCallIsNull: + StatusMsg += "Child of call is null"; + break; + case NxMultiDeviceMinMaxNotSupported: + StatusMsg += + "Xteam min/max reduction not supported with multi-device compilation"; + break; + case NxFastReductionMinMaxNotSupported: + StatusMsg += "Xteam min/max reduction not supported with fast reduction"; + break; + case NxScanMinMaxNotSupported: + StatusMsg += "Xteam min/max reduction not supported with scan"; + break; + case NxAmbiguousRedKind: + StatusMsg += "Could not determine reduction kind"; + break; + } + + SourceLocation L = D.getBeginLoc(); + SourceManager &SM = getContext().getSourceManager(); + PresumedLoc PLoc = SM.getPresumedLoc(L); + const char *FileName = PLoc.isValid() ? PLoc.getFilename() : nullptr; + unsigned LineNo = + PLoc.isValid() ? PLoc.getLine() : SM.getExpansionLineNumber(L); + + llvm::dbgs() << StatusMsg << ": " << FileName << ": " << LineNo << "\n"; +} + +void CodeGenModule::emitTargetTeamsLoopCodegenStatus( + std::string StatusMsg, const OMPExecutableDirective &D, bool IsDevice) { + if (IsDevice) + StatusMsg += ": DEVICE"; + else + StatusMsg += ": HOST"; + SourceLocation L = D.getBeginLoc(); + SourceManager &SM = getContext().getSourceManager(); + PresumedLoc PLoc = SM.getPresumedLoc(L); + const char *FileName = PLoc.isValid() ? PLoc.getFilename() : nullptr; + unsigned LineNo = + PLoc.isValid() ? PLoc.getLine() : SM.getExpansionLineNumber(L); + llvm::dbgs() << StatusMsg << ": " << FileName << ": " << LineNo << "\n"; +} + +const ForStmt *CodeGenModule::getSingleForStmt(const Stmt *S) { + if (S == nullptr) + return nullptr; + if (S->getStmtClass() == Stmt::ForStmtClass) + return cast(S); + const Stmt *Innermost = getMappedInnermostStmt(S); + if (Innermost) + S = Innermost; + if (!isa(S)) + return nullptr; + while (S->getStmtClass() == Stmt::CapturedStmtClass) { + S = cast(S)->getCapturedDecl()->getBody(); + } + if (S->getStmtClass() == Stmt::ForStmtClass) + return cast(S); + else + while (S->getStmtClass() == Stmt::CompoundStmtClass) { + const CompoundStmt &CompStmt = cast(*S); + if (CompStmt.size() != 1) + return nullptr; + if (CompStmt.body_front()->getStmtClass() == Stmt::ForStmtClass) + return cast(CompStmt.body_front()); + S = CompStmt.body_front(); + } + return nullptr; +} + +const VarDecl *CodeGenModule::checkLoopInit(const OMPLoopDirective &LD) { + const Expr *IVExpr = LD.getIterationVariable(); + if (!isa(IVExpr)) + return nullptr; + const ValueDecl *ValD = cast(IVExpr)->getDecl(); + if (!isa(ValD)) + return nullptr; + const VarDecl *VD = cast(ValD); + if (!VD->getType()->isIntegerType()) + return nullptr; + return VD; +} + +bool CodeGenModule::checkLoopStop(const OMPLoopDirective &LD, + const ForStmt &FStmt) { + // We don't handle a condition variable for NoLoop + if (FStmt.getConditionVariable() != nullptr) + return false; + // Make sure the loop condition is valid + if (LD.getCond() == nullptr) + return false; + return true; +} + +// Return true if the step is either a unary increment of the provided loop +// index or a binary add on the loop index. Otherwise return false. +bool CodeGenModule::checkLoopStep(const Expr *Inc, const VarDecl *VD) { + if (Inc == nullptr) + return false; + if (Inc->getStmtClass() == Expr::UnaryOperatorClass && + cast(Inc)->isIncrementOp()) { + const auto *IncDRE = + cast(cast(Inc)->getSubExpr()); + if (IncDRE == nullptr) + return false; + const auto *IncVarDecl = cast(IncDRE->getDecl()); + if (IncVarDecl == nullptr) + return false; + if (IncVarDecl != VD) + return false; + return true; + } + + // We support either += or = in the step expression + if ((isa(Inc) && + cast(Inc)->getOpcode() == BO_AddAssign) || + (isa(Inc) && + cast(Inc)->getOpcode() == BO_Assign)) { + // LHS must be the loop variable + const auto *IncDRE = cast(cast(Inc)->getLHS()); + if (IncDRE == nullptr) + return false; + if (!isa(IncDRE->getDecl())) + return false; + // The step variable must be the loop variable + if (IncDRE->getDecl() != VD) + return false; + // Found step += val, return true + if (isa(Inc) && + cast(Inc)->getOpcode() == BO_AddAssign) + return true; + + // If it is an assignment binary operator, analyze it further + assert(isa(Inc) && + cast(Inc)->getOpcode() == BO_Assign && + "Unexpected expression in step"); + const Expr *IncRHS = cast(Inc)->getRHS(); + // We support binary add operator, operating on the loop variable + if (isa(IncRHS) && + cast(IncRHS)->getOpcode() == BO_Add) { + const BinaryOperator *IncRHSBinOp = cast(IncRHS); + const Expr *LHSIncRHS = IncRHSBinOp->getLHS(); + const Expr *RHSIncRHS = IncRHSBinOp->getRHS(); + + // We support either step = step + val or step = val + step. We don't + // currently support more complex expressions. Additionally, make sure + // that step does not appear in val. + auto checkStep = [VD](const Expr *CheckedExpr) { + NoLoopStepChecker Checker(VD); + Checker.Visit(CheckedExpr); + if (Checker.isUnsupported()) + return false; + return true; + }; + + if (isa(LHSIncRHS) && + cast(LHSIncRHS)->getDecl() == VD) { + // Check that VD does not occur in RHSIncRHS + return checkStep(RHSIncRHS); + } + if (isa(RHSIncRHS) && + cast(RHSIncRHS)->getDecl() == VD) { + // Check that VD does not occur in LHSIncRHS + return checkStep(LHSIncRHS); + } + if (isa(LHSIncRHS) && + isa(cast(LHSIncRHS)->getSubExpr()) && + cast(cast(LHSIncRHS)->getSubExpr()) + ->getDecl() == VD) { + // Visit RHSIncRHS and make sure the loop variable is not present as a + // declref + return checkStep(RHSIncRHS); + } + if (isa(RHSIncRHS) && + isa(cast(RHSIncRHS)->getSubExpr()) && + cast(cast(RHSIncRHS)->getSubExpr()) + ->getDecl() == VD) { + // Visit LHSIncRHS and make sure the loop variable is not present as a + // declref + return checkStep(LHSIncRHS); + } + } + } + return false; +} + +// If the step is a unary expression, we already ensure it is an increment. So +// no more processing is required for a unary expression. For a binary +// expression, return the step. +const Expr *CodeGenModule::getBinaryExprStep(const Expr *Inc, + const VarDecl *VD) { + if (isa(Inc)) + return nullptr; + // Found step += val, return val + if (isa(Inc) && + cast(Inc)->getOpcode() == BO_AddAssign) + return cast(Inc)->getRHS(); + + // If found step = step + val or step = val + step, return val + if (isa(Inc) && + cast(Inc)->getOpcode() == BO_Assign) { + const auto *IncRHS = cast(Inc)->getRHS(); + assert(isa(IncRHS) && + cast(IncRHS)->getOpcode() == BO_Add); + // Find the step based on the supported scenario + const Expr *StepExpr = nullptr; + const BinaryOperator *IncRHSBinOp = cast(IncRHS); + const Expr *LHSIncRHS = IncRHSBinOp->getLHS(); + const Expr *RHSIncRHS = IncRHSBinOp->getRHS(); + if (isa(LHSIncRHS) && + cast(LHSIncRHS)->getDecl() == VD) + StepExpr = RHSIncRHS; + else if (isa(RHSIncRHS) && + cast(RHSIncRHS)->getDecl() == VD) + StepExpr = LHSIncRHS; + else if (isa(LHSIncRHS) && + isa( + cast(LHSIncRHS)->getSubExpr()) && + cast(cast(LHSIncRHS)->getSubExpr()) + ->getDecl() == VD) + StepExpr = RHSIncRHS; + else if (isa(RHSIncRHS) && + isa( + cast(RHSIncRHS)->getSubExpr()) && + cast(cast(RHSIncRHS)->getSubExpr()) + ->getDecl() == VD) + StepExpr = LHSIncRHS; + else + llvm_unreachable("Unexpected step"); + return StepExpr; + } + llvm_unreachable("Unexpected operator type in step computation"); +} + +std::pair +CodeGenModule::getNoLoopForStmtStatus(const OMPExecutableDirective &D, + const Stmt *OMPStmt) { + NoLoopChecker Checker(*this); + Checker.Visit(OMPStmt); + bool HasNestedGenericCall = Checker.hasNestedGenericCall(); + NoLoopXteamErr NxStatus = NxSuccess; + if ((NxStatus = Checker.getNoLoopCheckStatus())) + return std::make_pair(NxStatus, HasNestedGenericCall); + + // Now ensure that code generation will handle this construct + + const ForStmt *FStmt = getSingleForStmt(OMPStmt); + if (FStmt == nullptr) + return std::make_pair(NxNoSingleForStmt, HasNestedGenericCall); + + assert(isa(D) && "Expected a loop directive"); + const OMPLoopDirective &LD = cast(D); + + // Ensure loop init and condition are supported + const VarDecl *VD = checkLoopInit(LD); + if (VD == nullptr) + return std::make_pair(NxUnsupportedLoopInit, HasNestedGenericCall); + + if (!checkLoopStep(LD.getInc(), VD)) + return std::make_pair(NxUnsupportedLoopStep, HasNestedGenericCall); + + if (!checkLoopStop(LD, *FStmt)) + return std::make_pair(NxUnsupportedLoopStop, HasNestedGenericCall); + + return std::make_pair(NxSuccess, HasNestedGenericCall); +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::getMultiDeviceForStmtStatus(const OMPExecutableDirective &D, + const Stmt *OMPStmt) { + const ForStmt *FStmt = getSingleForStmt(OMPStmt); + if (FStmt == nullptr) + return NxNoSingleForStmt; + + assert(isa(D) && "Expected a loop directive"); + return NxSuccess; +} + +int64_t CodeGenModule::getXteamRedNumTeamsFromClause( + const OptKernelNestDirectives &NestDirs) { + for (const auto &D : NestDirs) { + if (D->hasClausesOfKind()) { + const Expr *NumTeams = + D->getSingleClause()->getNumTeams().front(); + if (NumTeams->isIntegerConstantExpr(getContext())) + if (auto Constant = NumTeams->getIntegerConstantExpr(getContext())) + return Constant->getExtValue(); + } + } + return 0; // num_teams not found +} + +int64_t +CodeGenModule::getXteamRedNumTeamsFromClause(const OMPExecutableDirective &D) { + assert(isXteamRedKernel(D) && "Expected an Xteam reduction kernel"); + return getXteamRedNumTeamsFromClause(getXteamRedNestDirs(D)); +} + +int CodeGenModule::getWorkGroupSizeSPMDHelper(const OMPExecutableDirective &D) { + // Honor block-size provided by command-line option. This logic must be kept + // in sync with metadata generation. If this option is not specified on the + // command line then the value used will be the 256. + int WorkGroupSz = getLangOpts().OpenMPGPUThreadsPerTeam; + + // Cross team reduction blocksize default may be specified separately. + bool isXteamRed = isXteamRedKernel(D); + if (isXteamRed) + WorkGroupSz = getLangOpts().OpenMPTargetXteamReductionBlockSize; + + // Check block-size provided by thread_limit clause. We start with the + // maximum thread limit and lower it if user requests a lower thread limit. + int ThreadLimit = isXteamRed ? llvm::omp::xteam_red::MaxBlockSize + : getTarget().getGridValue().GV_Max_WG_Size; + const auto *ThreadLimitClause = D.getSingleClause(); + if (ThreadLimitClause) { + Expr *ThreadLimitExpr = ThreadLimitClause->getThreadLimit().front(); + clang::Expr::EvalResult Result; + if (ThreadLimitExpr->EvaluateAsInt(Result, getContext())) { + int ThreadLimitEval = Result.Val.getInt().getExtValue(); + if (ThreadLimitEval > 0 && ThreadLimitEval <= ThreadLimit) { + ThreadLimit = ThreadLimitEval; + // Prioritize value from clause over command-line option. + WorkGroupSz = ThreadLimit; + } + } + } + + // Set the actual number of threads if the user requests a value different + // then the default. If the value is greater than the currently computed + // thread limit then cap the number of threads to the thread limit. + int NumThreads = isXteamRed ? llvm::omp::xteam_red::DefaultBlockSize + : getTarget().getGridValue().GV_Default_WG_Size; + const auto *NumThreadsClause = D.getSingleClause(); + if (NumThreadsClause) { + Expr *NumThreadsExpr = NumThreadsClause->getNumThreads(); + clang::Expr::EvalResult Result; + if (NumThreadsExpr->EvaluateAsInt(Result, getContext())) { + NumThreads = Result.Val.getInt().getExtValue(); + // Cap the number of threads to the current thread limit. + if (NumThreads > ThreadLimit) + NumThreads = ThreadLimit; + // num_threads clause takes precendence over the command line value: + WorkGroupSz = NumThreads; + } + } + + // Sanitize the workgroup size received from the command line. Its default + // value is GV_Default_WG_Size. + if (WorkGroupSz < 1 || WorkGroupSz > ThreadLimit) + WorkGroupSz = isXteamRed ? llvm::omp::xteam_red::DefaultBlockSize + : getTarget().getGridValue().GV_Default_WG_Size; + + return WorkGroupSz; +} + +int CodeGenModule::getOptKernelWorkGroupSize( + const OptKernelNestDirectives &NestDirs, bool isXteamRed) { + int WGSizeDefault = isXteamRed + ? llvm::omp::xteam_red::DefaultBlockSize + : getTarget().getGridValue().GV_Default_WG_Size; + + int ThreadLimit = isXteamRed ? llvm::omp::xteam_red::MaxBlockSize + : getTarget().getGridValue().GV_Max_WG_Size; + + // Allow command-line option override clauses on the OpenMP construct. + // Exception: If the command line value is the same as the default, the clause + // overrides. + int CmdLineOption = isXteamRed + ? getLangOpts().OpenMPTargetXteamReductionBlockSize + : getLangOpts().OpenMPGPUThreadsPerTeam; + if (CmdLineOption > 0 && CmdLineOption <= ThreadLimit && + CmdLineOption != WGSizeDefault) + return CmdLineOption; + + // The blocksize used by optimized kernels is the minimum of the + // max_wg_size and any thread_limit or num_threads specified on any OpenMP + // clauses. + int WGSize = ThreadLimit; + for (const auto &Dir : NestDirs) + WGSize = std::min(WGSize, getWorkGroupSizeSPMDHelper(*Dir)); + return WGSize; +} + +int CodeGenModule::computeOptKernelBlockSize( + const OptKernelNestDirectives &NestDirs, bool isXteamRed) { + int InitialBlockSize = getOptKernelWorkGroupSize(NestDirs, isXteamRed); + if (!isXteamRed) + return InitialBlockSize; + // We support block sizes that are a power of 2 for Xteam reduction. + return llvm::omp::getBlockSizeAsPowerOfTwo(InitialBlockSize); +} + +std::pair +CodeGenModule::getXteamRedForStmtStatus(const OMPExecutableDirective &D, + const Stmt *OMPStmt, + XteamRedVarMap *RVM) { + auto [NxStatus, HasNestedGenericCall] = getNoLoopForStmtStatus(D, OMPStmt); + if (NxStatus != CodeGenModule::NxSuccess) + return std::make_pair(NxStatus, HasNestedGenericCall); + // The above check ensures that there is only one statement corresponding to + // the directive + const ForStmt *FStmt = getSingleForStmt(OMPStmt); + assert(FStmt != nullptr && "Unexpected missing For Stmt"); + for (auto Child : FStmt->children()) + if (Child) { + XteamRedExprChecker Chk(*this, RVM); + Chk.Visit(Child); + CodeGenModule::NoLoopXteamErr NxStatus = Chk.getNxStatus(); + if (NxStatus != CodeGenModule::NxSuccess) + return std::make_pair(NxStatus, HasNestedGenericCall); + } + return std::make_pair(NxSuccess, HasNestedGenericCall); +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::getNoLoopCompatibleSchedStatus(const OMPLoopDirective &LD) { + for (const auto *C : LD.getClausesOfKind()) { + OpenMPScheduleClauseKind SchedKind = C->getScheduleKind(); + if (SchedKind == OMPC_SCHEDULE_guided || SchedKind == OMPC_SCHEDULE_runtime) + return NxGuidedOrRuntimeSched; + // No need to examine the monotonic ordering-modifier since with No-Loop, + // each thread executes a single iteration. Monotonic refers to ordering + // of iterations within a thread which does not apply here. + // The other modifier, simd, is ignored since the SIMD construct is ignored + // as well for device code generation. + assert((SchedKind == OMPC_SCHEDULE_static || + SchedKind == OMPC_SCHEDULE_dynamic || + SchedKind == OMPC_SCHEDULE_auto) && + "Unexpected schedule"); + + // Return success if either auto or chunk size is 1. + const Expr *ChunkExpr = C->getChunkSize(); + if (SchedKind == OMPC_SCHEDULE_auto) { + assert(ChunkExpr == nullptr && "Chunk size unexpected"); + } else { + bool HasChunkSizeOne = false; + Expr::EvalResult Result; + if (ChunkExpr && ChunkExpr->EvaluateAsInt(Result, getContext())) { + llvm::APSInt EvaluatedChunk = Result.Val.getInt(); + HasChunkSizeOne = EvaluatedChunk.getLimitedValue() == 1; + } + if (!HasChunkSizeOne) + return NxNonUnitStaticChunk; + } + } + return NxSuccess; +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::getNoLoopCompatibleOrderStatus(const OMPLoopDirective &LD) { + for (const auto *C : LD.getClausesOfKind()) { + if (C->getKind() != OMPC_ORDER_concurrent) + return NxNonConcurrentOrder; + } + return NxSuccess; +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::getXteamRedCompatibleThreadLimitStatus( + const OMPLoopDirective &LD) { + const auto *ThreadLimitClause = LD.getSingleClause(); + if (!ThreadLimitClause) + return NxSuccess; + Expr *ThreadLimitExpr = ThreadLimitClause->getThreadLimit().front(); + clang::Expr::EvalResult Result; + if (ThreadLimitExpr->EvaluateAsInt(Result, getContext())) { + int ThreadLimitEval = Result.Val.getInt().getExtValue(); + // We support thread limit >= 64 + if (ThreadLimitEval > 63) + return NxSuccess; + } + return NxUnsupportedXteamRedThreadLimit; +} + +CodeGenModule::NoLoopXteamErr CodeGenModule::getNoLoopStatusForClauses( + const OptKernelNestDirectives &NestDirs) { + for (auto &D : NestDirs) { + if (D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind()) + return NxUnsupportedTargetClause; + } + if (!isa(NestDirs.back())) + return NxNotLoopDirective; + const OMPLoopDirective &LD = cast(*NestDirs.back()); + NoLoopXteamErr NxStatus = NxSuccess; + if ((NxStatus = getNoLoopCompatibleOrderStatus(LD))) + return NxStatus; + return getNoLoopCompatibleSchedStatus(LD); +} + +CodeGenModule::NoLoopXteamErr CodeGenModule::getXteamRedStatusForClauses( + const OptKernelNestDirectives &NestDirs) { + for (auto &D : NestDirs) { + if (D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind()) + return NxUnsupportedTargetClause; + } + if (!isa(NestDirs.back())) + return NxNotLoopDirective; + const OMPLoopDirective &LD = cast(*NestDirs.back()); + NoLoopXteamErr NxStatus = NxSuccess; + if ((NxStatus = getXteamRedCompatibleThreadLimitStatus(LD))) + return NxStatus; + if ((NxStatus = getNoLoopCompatibleOrderStatus(LD))) + return NxStatus; + return getNoLoopCompatibleSchedStatus(LD); +} + +CodeGenModule::NoLoopXteamErr CodeGenModule::getMultiDeviceStatusForClauses( + const OptKernelNestDirectives &NestDirs) { + for (auto &D : NestDirs) { + if (D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind() || + D->hasClausesOfKind()) + return NxUnsupportedTargetClause; + } + if (!isa(NestDirs.back())) + return NxNotLoopDirective; + const OMPLoopDirective &LD = cast(*NestDirs.back()); + NoLoopXteamErr NxStatus = NxSuccess; + if ((NxStatus = getNoLoopCompatibleOrderStatus(LD))) + return NxStatus; + return getNoLoopCompatibleSchedStatus(LD); +} + +/// Given a directive, collect metadata for the reduction variables for Xteam +/// reduction, if applicable +std::pair +CodeGenModule::collectXteamRedVars(const OptKernelNestDirectives &NestDirs) { + // Check all nest directives. A reduction clause is treated + // equivalently regardless the nesting level it is at -- this is + // because Xteam reduction is applied today for a nest that + // satisfies target-teams-distribute-parallel-for. + XteamRedVarMap VarMap; + + // This vector defines the order in which Xteam metadata will always be + // generated. + XteamRedVarVecTy VarVec; + + // Encode the reduction operator kinds found in this kernel. + uint8_t OpKindsFound = XR_OP_unknown; + + auto isSumReduction = [](const Expr *AssignmentRhs) { + if (!isa(AssignmentRhs) || + cast(AssignmentRhs)->getOpcode() != BO_Add) + return false; + return true; + }; + + auto getMinMaxReduction = [](const Expr *AssignmentRhs, + bool isUnsignedInt) -> XteamRedOpKind { + // Unsigned integer not supported right now. + if (isUnsignedInt) + return XR_OP_unknown; + auto getVarDecl = [](const Expr *E) -> const VarDecl * { + if (!isa(E)) + return nullptr; + const ValueDecl *ValDecl = cast(E)->getDecl(); + if (!isa(ValDecl)) + return nullptr; + return cast(ValDecl); + }; + + if (isa(AssignmentRhs)) { + auto CondOpExpr = cast(AssignmentRhs); + auto CondExpr = CondOpExpr->getCond(); + if (isa(CondExpr)) { + auto BinCondExpr = cast(CondExpr); + BinaryOperator::Opcode Opcode = BinCondExpr->getOpcode(); + if (Opcode == BO_GT || Opcode == BO_LT) { + // Found either max or min + // Extract the reduction variable + const VarDecl *RedVD = + getVarDecl(BinCondExpr->getRHS()->IgnoreImpCasts()); + // This variable must match the rhs of the conditional expression. + if (RedVD != getVarDecl(CondOpExpr->getRHS()->IgnoreImpCasts())) { + return XR_OP_unknown; + } + if (Opcode == BO_GT) + return XR_OP_max; + else + return XR_OP_min; + } + } + } + return XR_OP_unknown; + }; + + // Either we emit Xteam code for all reduction variables or none at all. + // Track whether the kernel has any min/max reduction variable. + bool isMultiDeviceCompile = getLangOpts().OpenMPTargetMultiDevice; + bool isFastReductionEnabled = getLangOpts().OpenMPTargetFastReduction; + for (auto &D : NestDirs) { + for (const auto *C : D->getClausesOfKind()) { + if (C->getModifier() == OMPC_REDUCTION_inscan) + isXteamScanCandidate = true; + for (const Expr *Ref : C->varlist()) { + // Only scalar variables supported today + if (!isa(Ref)) + return std::make_pair( + NxNotScalarRed, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + const ValueDecl *ValDecl = cast(Ref)->getDecl(); + if (!isa(ValDecl)) + return std::make_pair( + NxNotScalarRed, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + + llvm::Type *RefType = getTypes().ConvertTypeForMem(Ref->getType()); + // TODO support more data types + if (!RefType->isFloatTy() && !RefType->isDoubleTy() && + !RefType->isHalfTy() && !RefType->isBFloatTy() && + !RefType->isIntegerTy()) + return std::make_pair( + NxUnsupportedRedType, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + if (RefType->isIntegerTy() && RefType->getPrimitiveSizeInBits() != 16 && + RefType->getPrimitiveSizeInBits() != 32 && + RefType->getPrimitiveSizeInBits() != 64) + return std::make_pair( + NxUnsupportedRedIntSize, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + + const VarDecl *VD = cast(ValDecl); + // Filter out duplicates + if (VarMap.find(VD) == VarMap.end()) { + // Address of the local var and arg pos will be populated later + XteamRedVarInfo XRVI(Ref, Address::invalid(), + std::numeric_limits::max()); + VarMap.insert(std::make_pair(VD, XRVI)); + VarVec.push_back(VD); + } + } + + // Now make sure that we support all the operators. Today, only sum, min, + // and max are supported. + for (const Expr *Ref : C->reduction_ops()) { + if (!isa(Ref)) + return std::make_pair( + NxNotBinOpRed, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + auto BinExpr = cast(Ref); + if (BinExpr->getOpcode() != BO_Assign) + return std::make_pair( + NxReductionOpNotBinAssign, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + auto BinExprRhs = BinExpr->getRHS()->IgnoreImpCasts(); + + // We recognize sum and min/max reductions that satisfy a specific + // format. + if (!isa(BinExprRhs) && + !isa(BinExprRhs)) + return std::make_pair( + NxReductionOpRhsNotBinOrCond, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + + // Is this reduction variable min/max? + auto MinMaxOp = getMinMaxReduction( + BinExprRhs, Ref->getType()->isUnsignedIntegerType()); + OpKindsFound |= MinMaxOp; + + // Multi-device compilation is not compatible with Xteam min/max, + // so disable Xteam codegen. + if (MinMaxOp != XR_OP_unknown && isMultiDeviceCompile) { + return std::make_pair( + NxMultiDeviceMinMaxNotSupported, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + } + + // Fast reduction is not compatible with Xteam min/max, so + // disable Xteam codegen. + if (MinMaxOp != XR_OP_unknown && isFastReductionEnabled) { + return std::make_pair( + NxFastReductionMinMaxNotSupported, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + } + // Scan kernel codegen is not compatible with min/max, so + // disable Xteam codegen if a scan reduction variable is found. + if (OpKindsFound > XR_OP_add && isXteamScanKernel()) { + return std::make_pair( + NxScanMinMaxNotSupported, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + } + + // Now check for sum reduction + OpKindsFound |= isSumReduction(BinExprRhs); + // Unrecognized reduction operator + if (OpKindsFound == XR_OP_unknown) { + return std::make_pair( + NxReductionOpRhsNotMinMaxSum, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + } + } + } + } + // We support multiple reduction operations in the same loop with the new + // DeviceRTL APIs. So bail out only if none was found. + if (VarMap.size() == 0) + return std::make_pair(NxNoRedVar, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); + + return std::make_pair(NxSuccess, + XteamRedCollectionInfo(VarMap, VarVec, OpKindsFound)); +} + +bool CodeGenModule::hasXteamRedVar(const Expr *E, + const XteamRedVarMap &RedMap) const { + assert(E && "Unexpected null expression"); + if (!isa(E)) + return false; + auto *Decl = cast(E)->getDecl(); + if (!isa(Decl)) + return false; + auto *VD = cast(Decl); + if (RedMap.find(VD) != RedMap.end()) + return true; + return false; +} + +const VarDecl * +CodeGenModule::getXteamRedVarDecl(const Expr *E, + const XteamRedVarMap &RedMap) const { + if (!isa(E)) + return nullptr; + const ValueDecl *ValDecl = cast(E)->getDecl(); + if (!isa(ValDecl)) + return nullptr; + const VarDecl *VD = cast(ValDecl); + if (RedMap.find(VD) == RedMap.end()) + return nullptr; + return VD; +} + +bool CodeGenModule::isXteamRedVarExpr(const Expr *E, + const VarDecl *RedVarDecl) const { + if (!isa(E)) + return false; + const ValueDecl *ValDecl = cast(E)->getDecl(); + if (!isa(ValDecl)) + return false; + const VarDecl *VD = cast(ValDecl); + return VD == RedVarDecl; +} + +const OMPExecutableDirective * +getNestedDirective(const OMPExecutableDirective &D) { + const Stmt *AssocStmt = D.getAssociatedStmt(); + if (!isa(AssocStmt)) + return nullptr; + while (AssocStmt->getStmtClass() == Stmt::CapturedStmtClass) { + AssocStmt = cast(AssocStmt)->getCapturedDecl()->getBody(); + } + while (AssocStmt->getStmtClass() == Stmt::CompoundStmtClass) { + const CompoundStmt &CompStmt = cast(*AssocStmt); + // We require proper nesting of the constructs + if (CompStmt.size() != 1) + return nullptr; + AssocStmt = CompStmt.body_front(); + } + if (!isa(AssocStmt)) + return nullptr; + return cast(AssocStmt); +} + +static bool +hasNumTeamsClause(const CodeGenModule::OptKernelNestDirectives &NestDirs) { + for (const auto &D : NestDirs) + if (D->hasClausesOfKind()) + return true; + return false; +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::checkNest(const OMPExecutableDirective &D, + OptKernelNestDirectives *NestDirs) { + NoLoopXteamErr NxStatus = NxSuccess; + switch (D.getDirectiveKind()) { + case llvm::omp::Directive::OMPD_target_teams_distribute_parallel_for: + case llvm::omp::Directive::OMPD_target_teams_distribute_parallel_for_simd: + case llvm::omp::Directive::OMPD_target_teams_loop: + NestDirs->push_back(&D); + return NxSuccess; + case llvm::omp::Directive::OMPD_target: + if ((NxStatus = checkTargetNest(D, NestDirs))) + return NxStatus; + break; + case llvm::omp::Directive::OMPD_target_teams: + if ((NxStatus = checkTargetTeamsNest(D, NestDirs))) + return NxStatus; + break; + default: + return NxUnsupportedDirective; + } + return NxSuccess; +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::checkTargetNest(const OMPExecutableDirective &D, + OptKernelNestDirectives *NestDirs) { + NoLoopXteamErr NxStatus = NxSuccess; + NestDirs->push_back(&D); + + const OMPExecutableDirective *NestedDir = getNestedDirective(D); + if (NestedDir == nullptr) + return NxSplitConstructImproperlyNested; + + switch (NestedDir->getDirectiveKind()) { + case llvm::omp::Directive::OMPD_teams_distribute_parallel_for: + case llvm::omp::Directive::OMPD_teams_distribute_parallel_for_simd: + case llvm::omp::Directive::OMPD_teams_loop: + NestDirs->push_back(NestedDir); + return NxSuccess; + case llvm::omp::Directive::OMPD_teams: + if ((NxStatus = checkTargetTeamsNest(*NestedDir, NestDirs))) + return NxStatus; + break; + default: + return NxUnsupportedNestedSplitDirective; + } + return NxSuccess; +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::checkTargetTeamsNest(const OMPExecutableDirective &D, + OptKernelNestDirectives *NestDirs) { + NestDirs->push_back(&D); + + const OMPExecutableDirective *NestedDir = getNestedDirective(D); + if (NestedDir == nullptr) + return NxSplitConstructImproperlyNested; + + switch (NestedDir->getDirectiveKind()) { + case llvm::omp::Directive::OMPD_distribute_parallel_for: + case llvm::omp::Directive::OMPD_distribute_parallel_for_simd: + case llvm::omp::Directive::OMPD_loop: + NestDirs->push_back(NestedDir); + return NxSuccess; + default: + return NxUnsupportedNestedSplitDirective; + } + llvm_unreachable("Unexpected OpenMP clause"); +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::checkAndSetNoLoopKernel(const OMPExecutableDirective &D) { + NoLoopXteamErr NxStatus = NxSuccess; + + OptKernelNestDirectives NestDirs; + if ((NxStatus = checkNest(D, &NestDirs))) + return NxStatus; + + // Check clauses of nested directives that make up + // target-teams-distribute-parallel-for + if ((NxStatus = getNoLoopStatusForClauses(NestDirs))) + return NxStatus; + + // Make sure CodeGen can handle the FOR statement + if (!D.hasAssociatedStmt()) + return NxNoStmt; + + const OMPExecutableDirective &InnermostDir = *NestDirs.back(); + if (!InnermostDir.hasAssociatedStmt()) + return NxNoStmt; + + std::pair ForStmtStatus = + getNoLoopForStmtStatus(InnermostDir, InnermostDir.getAssociatedStmt()); + if ((NxStatus = ForStmtStatus.first)) + return NxStatus; + + bool HasNestedGenericCall = ForStmtStatus.second; + + // Now we should determine whether this qualifies as a NoLoop or a + // BigJumpLoop kernel. BigJumpLoop is enabled whenever NoLoop is + // enabled. If the num_teams clause is specified, BigJumpLoop is + // chosen. If the command line option to force BigJumpLoop is used, + // it is preferred over No-Loop. + + // The metadata map for all optimized kernels will have the ForStmt + // as the key. + const ForStmt *FStmt = getSingleForStmt(InnermostDir.getAssociatedStmt()); + assert(FStmt && "For stmt cannot be null"); + + if ((getLangOpts().OpenMPTargetIgnoreEnvVars || + (getLangOpts().OpenMPTeamSubscription && + getLangOpts().OpenMPThreadSubscription)) && + ((getLangOpts().OpenMPNoNestedParallelism && + getLangOpts().OpenMPNoThreadState) || + !HasNestedGenericCall) && + !hasNumTeamsClause(NestDirs) && getLangOpts().OpenMPTargetNoLoop) { + assert(!isNoLoopKernel(FStmt) && "No-Loop already set!"); + + // Now that an optimized kernel will be generated, set the nest map + addOptKernelNestMap(NestDirs); + + NoLoopKernels.insert( + std::make_pair(FStmt, NoLoopKernelInfo(/*BlockSize=*/0, NestDirs))); + int BlockSize = + getLangOpts().OpenMPIsTargetDevice + ? computeOptKernelBlockSize(NestDirs, /*isXteamRed=*/false) + : 0; + if (BlockSize > 0) + updateNoLoopKernel(FStmt, BlockSize); + return NxSuccess; + } + + if (((getLangOpts().OpenMPNoNestedParallelism && + getLangOpts().OpenMPNoThreadState) || !HasNestedGenericCall) && + getLangOpts().OpenMPTargetBigJumpLoop) { + assert(!isBigJumpLoopKernel(FStmt) && "Big-Jump-Loop already set!"); + + // Now that an optimized kernel will be generated, set the nest map + addOptKernelNestMap(NestDirs); + + BigJumpLoopKernels.insert( + std::make_pair(FStmt, NoLoopKernelInfo(/*BlockSize=*/0, NestDirs))); + int BlockSize = + getLangOpts().OpenMPIsTargetDevice + ? computeOptKernelBlockSize(NestDirs, /*isXteamRed=*/false) + : 0; + if (BlockSize > 0) + updateBigJumpLoopKernel(FStmt, BlockSize); + return NxSuccess; + } + return NxOptionDisabledOrHasCall; +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::checkAndSetXteamRedKernel(const OMPExecutableDirective &D) { + NoLoopXteamErr NxStatus = NxSuccess; + if (!getLangOpts().OpenMPTargetXteamReduction) + return NxOptionDisabled; + + OptKernelNestDirectives NestDirs; + if ((NxStatus = checkNest(D, &NestDirs))) + return NxStatus; + + // For now, keep the reduction helpers separate. Revisit merging with noloop + // later + if ((NxStatus = getXteamRedStatusForClauses(NestDirs))) + return NxStatus; + + std::pair RedPair = + collectXteamRedVars(NestDirs); + if (RedPair.first) + return RedPair.first; + + // Make sure CodeGen can handle the FOR statement + if (!D.hasAssociatedStmt()) + return NxNoStmt; + + const OMPExecutableDirective &InnermostDir = *NestDirs.back(); + if (!InnermostDir.hasAssociatedStmt()) + return NxNoStmt; + + auto ForStmtStatus = + getXteamRedForStmtStatus(InnermostDir, InnermostDir.getAssociatedStmt(), + &RedPair.second.RedVarMap); + if ((NxStatus = ForStmtStatus.first)) + return NxStatus; + + // Ensure that every reduction variable has a valid kind. Otherwise bail out. + for (auto &MapPair : RedPair.second.RedVarMap) { + auto Op = MapPair.second.Opcode; + if (Op != XR_OP_unknown) // valid kind already set. + continue; + // Prior analysis could not set the reduction kind. This can happen if the + // reduction statement is in a different function. The kind can be patched + // up here only if the kernel has an un-ambiguous reduction kind, i.e. only + // one kind of reduction operator. Otherwise, bail out. + uint8_t KernelRedOps = RedPair.second.OpKindsFound; + assert(KernelRedOps != XR_OP_unknown && + "At least one reduction kind must exist"); + if (KernelRedOps & (KernelRedOps - 1)) // multiple reduction ops + return NxAmbiguousRedKind; + MapPair.second.Opcode = static_cast(KernelRedOps); + } + + bool HasNestedGenericCall = ForStmtStatus.second; + if (((getLangOpts().OpenMPNoNestedParallelism && + getLangOpts().OpenMPNoThreadState) || + !HasNestedGenericCall)) { + const ForStmt *FStmt = getSingleForStmt(InnermostDir.getAssociatedStmt()); + assert(FStmt && "For stmt cannot be null"); + assert(!isXteamRedKernel(FStmt) && "Xteam reduction already set!"); + + // Now that an optimized kernel will be generated, set the nest map + addOptKernelNestMap(NestDirs); + + // Create a map from the ForStmt, some of the info will be populated later + XteamRedKernels.insert(std::make_pair( + FStmt, XteamRedKernelInfo( + /*ThreadStartIndex=*/nullptr, + /*NumTeams=*/nullptr, + /*BlockSize=*/0, NestDirs, RedPair.second.RedVarMap, + RedPair.second.RedVarVector, isFastXteamSumReduction()))); + + // The blocksize has to be computed after adding this kernel to the metadata + // above, since the computation below depends on that metadata. + int BlockSize = computeOptKernelBlockSize(NestDirs, /*isXteamRed=*/true); + if (BlockSize > 0) + updateXteamRedKernel(FStmt, BlockSize); + return NxSuccess; + } + return NxOptionDisabledOrHasCall; +} + +bool CodeGenModule::checkAndSetMultiDeviceKernel( + const OMPExecutableDirective &D, bool CanBeMultiDevice) { + bool IsMultiDeviceKernel = false; + + if (!getLangOpts().OpenMPTargetMultiDevice || + !getLangOpts().OpenMPIsTargetDevice) + return IsMultiDeviceKernel; + + OptKernelNestDirectives NestDirs; + if (checkNest(D, &NestDirs) == NxSuccess && + getMultiDeviceStatusForClauses(NestDirs) == NxSuccess && + D.hasAssociatedStmt()) { + const OMPExecutableDirective &InnermostDir = *NestDirs.back(); + if (InnermostDir.hasAssociatedStmt() && + getMultiDeviceForStmtStatus( + InnermostDir, InnermostDir.getAssociatedStmt()) == NxSuccess) { + // The metadata map for all optimized kernels will have the ForStmt + // as the key. + const ForStmt *FStmt = getSingleForStmt(InnermostDir.getAssociatedStmt()); + + // Check that we are on the device and that multi device has been enabled. + if (FStmt) { + // Set the entry only if we have not set it before otherwise just return + // the outcome of the isMultiDeviceKernel check. If this is the first + // time the function is called the code below will add an entry to the + // struct to keep track of the multi kernel metadata. + if (!multiDeviceFStmtEntryExists(FStmt)) { + // Now that a multi-device kernel will be generated, set the nest map + addOptKernelNestMap(NestDirs); + + MultiDeviceFunctionBoundsMap FunctionBoundsMap; + MultiDeviceKernels.insert(std::make_pair( + FStmt, MultiDeviceKernelInfo(NestDirs, FunctionBoundsMap, + CanBeMultiDevice))); + } + IsMultiDeviceKernel = isMultiDeviceKernel(FStmt); + } + } + } + + return IsMultiDeviceKernel; +} + +bool CodeGenModule::isXteamRedKernel(const OMPExecutableDirective &D) { + if (!D.hasAssociatedStmt()) + return false; + const ForStmt *FStmt = getSingleForStmt(getOptKernelKey(D)); + if (FStmt == nullptr) + return false; + return isXteamRedKernel(FStmt); +} + +bool CodeGenModule::isBigJumpLoopKernel(const OMPExecutableDirective &D) { + if (!D.hasAssociatedStmt()) + return false; + const ForStmt *FStmt = getSingleForStmt(getOptKernelKey(D)); + if (FStmt == nullptr) + return false; + return isBigJumpLoopKernel(FStmt); +} + +bool CodeGenModule::isNoLoopKernel(const OMPExecutableDirective &D) { + if (!D.hasAssociatedStmt()) + return false; + const ForStmt *FStmt = getSingleForStmt(getOptKernelKey(D)); + if (FStmt == nullptr) + return false; + return isNoLoopKernel(FStmt); +} + +bool CodeGenModule::isMultiDeviceKernel(const OMPExecutableDirective &D) { + if (!D.hasAssociatedStmt()) + return false; + const ForStmt *FStmt = getSingleForStmt(getOptKernelKey(D)); + if (FStmt == nullptr) + return false; + return isMultiDeviceKernel(FStmt); +} + +void CodeGenModule::addOptKernelNestMap( + const OptKernelNestDirectives &NestDirs) { + const OMPExecutableDirective &InnermostDir = *NestDirs.back(); + assert(InnermostDir.hasAssociatedStmt() && + "Innermost directive has no associated statement"); + const Stmt *InnermostCS = InnermostDir.getAssociatedStmt(); + for (const auto &Dir : NestDirs) { + assert(Dir->hasAssociatedStmt() && + "Nest directive has no associated statement"); + OptKernelNestMap[Dir->getAssociatedStmt()] = InnermostCS; + } +} + +const Stmt *CodeGenModule::getOptKernelKey(const OMPExecutableDirective &D) { + assert(D.hasAssociatedStmt() && "Directive has no associated statement"); + return D.getAssociatedStmt(); +} + +void CodeGenModule::resetOptKernelMetadata(const Stmt *DirectiveStmt) { + if (DirectiveStmt == nullptr) + return; + const ForStmt *KernelForStmt = getSingleForStmt(DirectiveStmt); + if (KernelForStmt == nullptr) + return; + + llvm::omp::OMPTgtExecModeFlags OptKernelMode; + if (isNoLoopKernel(KernelForStmt)) + OptKernelMode = + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP; + else if (isBigJumpLoopKernel(KernelForStmt)) + OptKernelMode = + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_BIG_JUMP_LOOP; + else if (isXteamRedKernel(KernelForStmt)) + OptKernelMode = llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_XTEAM_RED; + else + return; + + // Get the directives before resetting any metadata + const OptKernelNestDirectives &Dirs = + getOptKernelDirectives(KernelForStmt, OptKernelMode); + + // First reset the optimized kernel metadata + if (OptKernelMode == + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP) + resetNoLoopKernel(KernelForStmt); + else if (OptKernelMode == + llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_BIG_JUMP_LOOP) + resetBigJumpLoopKernel(KernelForStmt); + else + resetXteamRedKernel(KernelForStmt); + + // Now reset the split directives metadata + for (const auto &Dir : Dirs) + eraseOptKernelNestElem(getOptKernelKey(*Dir)); +} + +bool CodeGenModule::isStdNameSpace(const CallExpr *Call) const { + // Examine the first child, the call itself. + const Stmt *CE = nullptr; + for (const Stmt *Child : Call->children()) + if (Child) { + CE = Child; + break; + } + if (CE) { + while (isa(CE)) + CE = cast(CE)->getSubExpr(); + if (isa(CE)) { + const DeclRefExpr *DRE = cast(CE); + if (DRE->hasQualifier()) { + NestedNameSpecifier NS = DRE->getQualifier(); + if (NS.getKind() == NestedNameSpecifier::Kind::Namespace && + !NS.getAsNamespaceAndPrefix().Namespace->getNameAsString().compare("std")) + return true; + } + } + } + return false; +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::getStatusOptKernelHostBuiltin(const CallExpr *Call) const { + std::string CallName = Call->getDirectCallee()->getNameInfo().getAsString(); + if (isOptKernelHostMin(Call) || isOptKernelHostMax(Call)) + return NxSuccess; + auto emitDebugMsg = [](std::string Msg) { + Msg += ": Not recognized as builtin in host compile"; + llvm::dbgs() << Msg << "\n"; + }; + DEBUG_WITH_TYPE(NO_LOOP_XTEAM_RED, emitDebugMsg(CallName)); + return NxNotBuiltinByNameInHostCompile; +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::getStatusOptKernelAMDGCNBuiltin(const CallExpr *Call) const { + std::string CallName = Call->getDirectCallee()->getNameInfo().getAsString(); + if (isOptKernelAMDGCNMin(Call) || isOptKernelAMDGCNMax(Call)) + return NxSuccess; + auto emitDebugMsg = [](std::string Msg) { + Msg += ": Not recognized as builtin in device compile"; + llvm::dbgs() << Msg << "\n"; + }; + DEBUG_WITH_TYPE(NO_LOOP_XTEAM_RED, emitDebugMsg(CallName)); + return NxNotBuiltinByNameInDeviceCompile; +} + +CodeGenModule::NoLoopXteamErr +CodeGenModule::getStatusOptKernelBuiltin(const CallExpr *Call) { + if (getLangOpts().OpenMPIsTargetDevice) { + if (auto NxStatus = getStatusOptKernelAMDGCNBuiltin(Call)) + return NxStatus; + } else { + if (auto NxStatus = getStatusOptKernelHostBuiltin(Call)) + return NxStatus; + } + return NxSuccess; +} + +std::pair +CodeGenModule::getStatusXteamSupportedPseudoObject(const PseudoObjectExpr *PO) { + if (PO->getNumSemanticExprs() != 1) + return std::make_pair(NxPOExprCountNotOne, nullptr); + const Expr *RHS = PO->getSemanticExpr(0); + if (!isa(RHS)) + return std::make_pair(NxPOSemanticExprNotCall, nullptr); + return std::make_pair(NxSuccess, RHS); +} + void CodeGenModule::moveLazyEmissionStates(CodeGenModule *NewBuilder) { assert(DeferredDeclsToEmit.empty() && "Should have emitted all decls deferred to emit."); diff --git a/clang/lib/CodeGen/CodeGenModule.h b/clang/lib/CodeGen/CodeGenModule.h index a253bcda2d06c..4b3b39bb3ad44 100644 --- a/clang/lib/CodeGen/CodeGenModule.h +++ b/clang/lib/CodeGen/CodeGenModule.h @@ -344,6 +344,172 @@ class CodeGenModule : public CodeGenTypeCache { typedef std::vector CtorList; + enum NoLoopXteamErr { + NxSuccess, + NxNonSPMD, + NxOptionDisabled, + NxOptionDisabledOrHasCall, + NxUnsupportedDirective, + NxUnsupportedSplitDirective, + NxNoStmt, + NxUnsupportedTargetClause, + NxNotLoopDirective, + NxNotCapturedStmt, + NxNotExecutableStmt, + NxUnsupportedNestedSplitDirective, + NxSplitConstructImproperlyNested, + NxNestedOmpParallelDirective, + NxNestedOmpCall, + NxNoSingleForStmt, + NxUnsupportedLoopInit, + NxUnsupportedLoopStop, + NxUnsupportedLoopStep, + NxGuidedOrRuntimeSched, + NxNonUnitStaticChunk, + NxNonConcurrentOrder, + NxUnsupportedRedType, + NxUnsupportedRedIntSize, + NxNotScalarRed, + NxNotBinOpRed, + NxUnsupportedRedOp, + NxNoRedVar, + NxMultRedVar, + NxUnsupportedRedExpr, + NxUnsupportedXteamRedThreadLimit, + NxUnsupportedPseudoObject, + NxNotRedVarInBinOpRHS, + NxNotAddOpInBinOpRHs, + NxRhsOfAssignNotBinOpOrCall, + NxBinOpNotAddAssignOrAssign, + NxNotBinOpOrCallButAccessesRedVar, + NxNotArgScalarEval, + NxReductionOpNotBinAssign, + NxReductionOpRhsNotBinOrCond, + NxReductionOpRhsNotMinMaxSum, + NxNotBuiltinByNameInHostCompile, + NxNotBuiltinByNameInDeviceCompile, + NxPOExprCountNotOne, + NxPOSemanticExprNotCall, + NxChildOfCallIsNull, + NxMultiDeviceMinMaxNotSupported, + NxFastReductionMinMaxNotSupported, + NxScanMinMaxNotSupported, + NxAmbiguousRedKind + }; + + using Stmt2StmtMap = llvm::DenseMap; + + /// Top-level and nested OpenMP directives, used in optimized kernel codegen. + using OptKernelNestDirectives = + llvm::SmallVector; + /// Metadata for NoLoop kernel codegen + struct NoLoopKernelInfo { + NoLoopKernelInfo(int BlkSz, OptKernelNestDirectives Dirs) + : BlockSize{BlkSz}, NoLoopNestDirs{Dirs} {} + + int BlockSize; // Cached blocksize + OptKernelNestDirectives NoLoopNestDirs; + }; + /// Map construct statement to corresponding metadata for a NoLoop kernel. + using NoLoopKernelMap = llvm::DenseMap; + + /// Xteam reduction operators supported today. + enum XteamRedOpKind { + XR_OP_unknown = 0, + // Valid values must be power of 2. + XR_OP_add = 1, + XR_OP_min = 2, + XR_OP_max = 4 + }; + + /// Map a reduction variable to the corresponding metadata. The metadata + /// contains + // the reduction expression, the coorresponding Xteam local aggregator var, + // and the start arg position in the offloading function signature. + struct XteamRedVarInfo { + XteamRedVarInfo(const Expr *E, Address A, size_t Pos) + : RedVarExpr(E), RedVarAddr(A), ArgPos(Pos), Opcode(XR_OP_unknown) {} + XteamRedVarInfo() = delete; + + /// Reduction variable expression, populated during initial analysis + const Expr *RedVarExpr; + /// Address of local reduction variable used in device codegen. + Address RedVarAddr; + /// Argument position for the corresponding metadata in the outlined + /// signature, populated during signature generation. Used for device + /// codegen only. + size_t ArgPos; + /// Reduction operator type: currently one of add, min, and max. + XteamRedOpKind Opcode; + }; + + using XteamRedVarMap = llvm::DenseMap; + using XteamRedVarVecTy = llvm::SmallVector; + + struct XteamRedKernelInfo { + XteamRedKernelInfo(llvm::Value *TSI, llvm::Value *NT, int BlkSz, + OptKernelNestDirectives Dirs, XteamRedVarMap RVM, + XteamRedVarVecTy RVV, bool F) + : ThreadStartIndex{TSI}, NumTeams{NT}, BlockSize{BlkSz}, + XteamNestDirs{Dirs}, XteamRedVars{RVM}, XteamOrderedRedVar{RVV}, + IsFast{F} {} + + /// Start index of every thread used in device codegen. + llvm::Value *ThreadStartIndex; + /// Number of teams used in device codegen. + llvm::Value *NumTeams; + /// Number of threads in a block, populated during device codegen. + int BlockSize; + /// A mask of the reduction operators found in this kernel, populated + /// according to XteamRedOpKind. + uint8_t OpKindsFound; + /// Nested directives, generated during analysis in both host/device + /// codegen. + OptKernelNestDirectives XteamNestDirs; + /// Map from reduction variable to metadata, populated during analysis. + XteamRedVarMap XteamRedVars; + /// Vector of reduction variables in the same order they appear in the AST + XteamRedVarVecTy XteamOrderedRedVar; + /// Can a fast-atomic-based-version be generated? + bool IsFast; + }; + using XteamRedKernelMap = llvm::DenseMap; + + struct XteamRedCollectionInfo { + XteamRedCollectionInfo(XteamRedVarMap VarMap, XteamRedVarVecTy VarVec, + uint8_t Ops) + : RedVarMap(VarMap), RedVarVector(VarVec), OpKindsFound(Ops) {} + XteamRedVarMap RedVarMap; + XteamRedVarVecTy RedVarVector; + uint8_t OpKindsFound; + }; + + /// Metadata for multi-device kernel codegen + struct MultiDeviceBoundsInfo { + MultiDeviceBoundsInfo(VarDecl *LBArg, VarDecl *UBArg) + : LBArg{LBArg}, UBArg{UBArg} {} + VarDecl *LBArg; + VarDecl *UBArg; + }; + using MultiDeviceFunctionBoundsMap = + llvm::DenseMap; + + struct MultiDeviceKernelInfo { + MultiDeviceKernelInfo(OptKernelNestDirectives Dirs, + MultiDeviceFunctionBoundsMap FBM, + bool CanBeMultiDevice) + : MultiDeviceNestDirs{Dirs}, FunctionBoundsMap{FBM}, + CanBeMultiDevice{CanBeMultiDevice} {} + + OptKernelNestDirectives MultiDeviceNestDirs; + MultiDeviceFunctionBoundsMap FunctionBoundsMap; + bool CanBeMultiDevice; + bool NewBoundsHaveBeenUsed = false; + }; + /// Map construct statement to corresponding metadata for a NoLoop kernel. + using MultiDeviceKernelMap = + llvm::DenseMap; + private: ASTContext &Context; const LangOptions &LangOpts; @@ -361,6 +527,12 @@ class CodeGenModule : public CodeGenTypeCache { bool CXX20ModuleInits = false; std::unique_ptr TBAA; + /// Used by emitParallelCall + bool isSPMDExecutionMode = false; + + /// Used by Xteam Scan Codegen + bool isXteamScanCandidate = false; + mutable std::unique_ptr TheTargetCodeGenInfo; // This should not be moved earlier, since its initialization depends on some @@ -384,6 +556,17 @@ class CodeGenModule : public CodeGenTypeCache { std::unique_ptr SanStats; StackExhaustionHandler StackHandler; + /// Statement for which Xteam reduction code is being generated currently + const Stmt *CurrentXteamRedStmt = nullptr; + // Map associated statement from top-level to innermost level for optimized + // kernels. + Stmt2StmtMap OptKernelNestMap; + + NoLoopKernelMap NoLoopKernels; + NoLoopKernelMap BigJumpLoopKernels; + XteamRedKernelMap XteamRedKernels; + MultiDeviceKernelMap MultiDeviceKernels; + // A set of references that have only been seen via a weakref so far. This is // used to remove the weak of the reference if we ever see a direct reference // or a definition. @@ -695,6 +878,9 @@ class CodeGenModule : public CodeGenTypeCache { ~CodeGenModule(); void clear(); + bool isXteamScanPhaseOne = true; + llvm::SmallVector ReductionVars; + const OMPExecutableDirective *OMPPresentScanDirective = nullptr; /// Finalize LLVM code generation. void Release(); @@ -719,6 +905,9 @@ class CodeGenModule : public CodeGenTypeCache { const std::string &getModuleNameHash() const { return ModuleNameHash; } + void setIsSPMDExecutionMode(bool isSPMD) { isSPMDExecutionMode = isSPMD; } + bool IsSPMDExecutionMode() { return isSPMDExecutionMode; } + /// Return a reference to the configured OpenCL runtime. CGOpenCLRuntime &getOpenCLRuntime() { assert(OpenCLRuntime != nullptr); @@ -1721,6 +1910,430 @@ class CodeGenModule : public CodeGenTypeCache { void printPostfixForExternalizedDecl(llvm::raw_ostream &OS, const Decl *D) const; + /// Under debug mode, print status of target teams loop transformation, + /// which should be either '#distribute' or '#parallel for' + void emitTargetTeamsLoopCodegenStatus(std::string StatusMsg, + const OMPExecutableDirective &D, + bool IsDevice); + + /// Add metadata for all nested directives for optimized kernel codegen. + void addOptKernelNestMap(const OptKernelNestDirectives &NestDirs); + + /// Given a directive, return the statement key used for maintaining metadata. + const Stmt *getOptKernelKey(const OMPExecutableDirective &D); + + /// Given a captured statement, return the nested directives involved in + /// optimized kernel codegen. + const OptKernelNestDirectives & + getOptKernelDirectives(const ForStmt *CapturedForStmt, + llvm::omp::OMPTgtExecModeFlags OptKernelMode); + + // Should be called under debug mode for printing analysis result. + void emitNxResult(std::string StatusMsg, const OMPExecutableDirective &D, + NoLoopXteamErr Status); + + /// Given the schedule clause, can No-Loop code be generated? + NoLoopXteamErr getNoLoopCompatibleSchedStatus(const OMPLoopDirective &LD); + + /// Given the order clause, can No-Loop code be generated? + NoLoopXteamErr getNoLoopCompatibleOrderStatus(const OMPLoopDirective &LD); + + NoLoopXteamErr + getXteamRedCompatibleThreadLimitStatus(const OMPLoopDirective &LD); + + /// Helper functions for generating a NoLoop kernel + /// For a captured statement, get the single For statement, if it exists, + /// otherwise return nullptr. + const ForStmt *getSingleForStmt(const Stmt *S); + + /// Does the loop init qualify for a NoLoop kernel? + const VarDecl *checkLoopInit(const OMPLoopDirective &LD); + + /// Does the loop increment qualify for a NoLoop kernel? + bool checkLoopStep(const Expr *Inc, const VarDecl *VD); + + /// Does the loop condition qualify for a NoLoop kernel? + bool checkLoopStop(const OMPLoopDirective &, const ForStmt &); + + /// If the step is a binary expression, extract and return the step. + /// If the step is a unary expression, return nullptr. + const Expr *getBinaryExprStep(const Expr *Inc, const VarDecl *VD); + + /// Reset optimized kernel metadata. + void resetOptKernelMetadata(const Stmt *S); + void eraseOptKernelNestElem(const Stmt *S) { OptKernelNestMap.erase(S); } + + /// Used in optimized kernel codegen. + const Stmt *getMappedInnermostStmt(const Stmt *S) { + auto nest_itr = OptKernelNestMap.find(S); + if (nest_itr == OptKernelNestMap.end()) + return nullptr; + return nest_itr->second; + } + + bool isFastXteamSumReduction() { + return getLangOpts().OpenMPTargetFastReduction; + } + + bool isXteamScanKernel() { + return (getLangOpts().OpenMPTargetXteamScan || + getLangOpts().OpenMPTargetXteamNoLoopScan) && + isXteamScanCandidate; + } + + bool isXteamSegmentedScanKernel() { + return isXteamScanKernel() && !getLangOpts().OpenMPTargetXteamNoLoopScan; + } + + /// If we are able to generate a NoLoop kernel for this directive, return + /// true, otherwise return false. If successful, a map is created from the + /// top-level statement to the intermediate statements. For a combined + /// construct, there are no intermediate statements. Used for a combined + /// construct + NoLoopXteamErr checkAndSetNoLoopKernel(const OMPExecutableDirective &D); + /// Determine if 'teams loop' can be emitted using 'parallel for'. + bool TeamsLoopCanBeParallelFor(const OMPExecutableDirective &D); + + /// Given a top-level target construct for no-loop codegen, get the + /// intermediate OpenMP constructs + const OptKernelNestDirectives &getNoLoopNestDirs(const Stmt *S) { + assert(isNoLoopKernel(S)); + return NoLoopKernels.find(S)->second.NoLoopNestDirs; + } + + /// Get the cached blocksize to be used for this NoLoop kernel. + int getNoLoopBlockSize(const Stmt *S) { + assert(isNoLoopKernel(S)); + return NoLoopKernels.find(S)->second.BlockSize; + } + + int getNoLoopBlockSize(const OMPExecutableDirective &D) { + assert(isNoLoopKernel(D) && "Expected a no-loop kernel"); + const ForStmt *FStmt = getSingleForStmt(getOptKernelKey(D)); + return getNoLoopBlockSize(FStmt); + } + + /// Erase no-loop related metadata for the input statement + void resetNoLoopKernel(const Stmt *S) { NoLoopKernels.erase(S); } + + /// Are we generating no-loop kernel for the input statement + bool isNoLoopKernel(const Stmt *S) { + return NoLoopKernels.find(S) != NoLoopKernels.end(); + } + bool isNoLoopKernel(const OMPExecutableDirective &D); + + /// Given a top-level target construct for BigJumpLoop codegen, get the + /// nested OpenMP constructs. + const OptKernelNestDirectives &getBigJumpLoopNestDirs(const Stmt *S) { + assert(isBigJumpLoopKernel(S)); + return BigJumpLoopKernels.find(S)->second.NoLoopNestDirs; + } + + void updateNoLoopKernel(const Stmt *S, int BlkSz) { + assert(isNoLoopKernel(S)); + NoLoopKernels.find(S)->second.BlockSize = BlkSz; + } + + /// Get the cached blocksize to be used for this BigJumpLoop kernel. + int getBigJumpLoopBlockSize(const Stmt *S) { + assert(isBigJumpLoopKernel(S)); + return BigJumpLoopKernels.find(S)->second.BlockSize; + } + + int getBigJumpLoopBlockSize(const OMPExecutableDirective &D) { + assert(isBigJumpLoopKernel(D) && "Expected a big-jump-loop kernel"); + const ForStmt *FStmt = getSingleForStmt(getOptKernelKey(D)); + return getBigJumpLoopBlockSize(FStmt); + } + + /// Erase BigJumpLoop related metadata for the input statement. + void resetBigJumpLoopKernel(const Stmt *S) { BigJumpLoopKernels.erase(S); } + /// Is a BigJumpLoop kernel generated for the input statement? + bool isBigJumpLoopKernel(const Stmt *S) { + return BigJumpLoopKernels.find(S) != BigJumpLoopKernels.end(); + } + bool isBigJumpLoopKernel(const OMPExecutableDirective &D); + + void updateBigJumpLoopKernel(const Stmt *S, int BlkSz) { + assert(isBigJumpLoopKernel(S)); + BigJumpLoopKernels.find(S)->second.BlockSize = BlkSz; + } + + /// If we are able to generate a Xteam reduction kernel for this directive, + /// return true, otherwise return false. If successful, metadata for the + /// reduction variables are created for subsequent codegen phases to work on. + NoLoopXteamErr checkAndSetXteamRedKernel(const OMPExecutableDirective &D); + + /// If we are able to generate a multi-device kernel for this directive, + /// return true, otherwise return false. If successful, metadata for the + /// argument variables is created for subsequent codegen phases to work on. + bool checkAndSetMultiDeviceKernel(const OMPExecutableDirective &D, + bool CanBeMultiDevice); + + /// Compute the block size to be used for a kernel. + int getWorkGroupSizeSPMDHelper(const OMPExecutableDirective &D); + /// Used in optimized kernel codegen, compute the block size from the nested + /// directives. + int getOptKernelWorkGroupSize(const OptKernelNestDirectives &NestDirs, + bool isXteamRed); + + /// Given a ForStmt for which Xteam codegen will be done, return the + /// intermediate statements for a split directive. + const OptKernelNestDirectives &getXteamRedNestDirs(const Stmt *S) { + assert(isXteamRedKernel(S)); + return XteamRedKernels.find(S)->second.XteamNestDirs; + } + const OptKernelNestDirectives & + getXteamRedNestDirs(const OMPExecutableDirective &D) { + assert(isXteamRedKernel(D) && "Expected an Xteam reduction kernel"); + const ForStmt *FStmt = getSingleForStmt(getOptKernelKey(D)); + return getXteamRedNestDirs(FStmt); + } + + /// Given a ForStmt for which Xteam codegen will be done, return the + /// corresponding metadata + XteamRedVarMap &getXteamRedVarMap(const Stmt *S) { + assert(isXteamRedKernel(S)); + return XteamRedKernels.find(S)->second.XteamRedVars; + } + + XteamRedVarVecTy &getXteamOrderedRedVar(const Stmt *S) { + assert(isXteamRedKernel(S)); + return XteamRedKernels.find(S)->second.XteamOrderedRedVar; + } + + llvm::Value *getXteamRedThreadStartIndex(const Stmt *S) { + assert(isXteamRedKernel(S)); + return XteamRedKernels.find(S)->second.ThreadStartIndex; + } + + /// Used during kernel codegen to retrieve the cached NumTeams. + llvm::Value *getXteamRedNumTeams(const Stmt *S) { + assert(isXteamRedKernel(S)); + return XteamRedKernels.find(S)->second.NumTeams; + } + + /// Used during host codegen to compute the number of teams from num_teams + /// clause. + int64_t getXteamRedNumTeamsFromClause(const OMPExecutableDirective &D); + + /// Used during host codegen for traversing nested directives, looking for + /// num_teams clause. + int64_t + getXteamRedNumTeamsFromClause(const OptKernelNestDirectives &NestDirs); + + bool isXteamRedFast(const Stmt *S) { + assert(isXteamRedKernel(S)); + return XteamRedKernels.find(S)->second.IsFast; + } + + /// Given a ForStmt for which Xteam codegen will be done, update the metadata. + /// \p VD is the reduction variable for which metadata is updated. + void updateXteamRedVarMap(const Stmt *S, const VarDecl *VD, const Expr *RVE, + Address AggVarAddr) { + assert(isXteamRedKernel(S)); + XteamRedVarMap &RVM = getXteamRedVarMap(S); + assert(RVM.find(VD) != RVM.end() && "Expected reduction variable in map"); + RVM.find(VD)->second.RedVarExpr = RVE; + RVM.find(VD)->second.RedVarAddr = AggVarAddr; + // Another API is used to set ArgPos + } + + void updateXteamRedVarArgPos(XteamRedVarInfo *RVInfo, size_t ArgP) { + assert(RVInfo); + RVInfo->ArgPos = ArgP; + } + + void updateXteamRedVarOpcode(const CallExpr *Call, const VarDecl *VD, + XteamRedVarMap *RedMap) { + XteamRedOpKind Opcode; + if (isOptKernelAMDGCNMax(Call)) + Opcode = XR_OP_max; + else if (isOptKernelAMDGCNMin(Call)) + Opcode = XR_OP_min; + else + llvm_unreachable("Expected either min or max"); + updateXteamRedVarOpcode(VD, RedMap, Opcode); + } + + void updateXteamRedVarOpcode(const VarDecl *VD, XteamRedVarMap *RedMap, + XteamRedOpKind Opcode) { + assert(RedMap->contains(VD) && "Expected reduction variable in map"); + RedMap->find(VD)->second.Opcode = Opcode; + } + + void updateXteamRedKernel(const Stmt *S, llvm::Value *ThdIndex, + llvm::Value *NTeams) { + assert(isXteamRedKernel(S)); + auto &KernelInfo = XteamRedKernels.find(S)->second; + KernelInfo.ThreadStartIndex = ThdIndex; + KernelInfo.NumTeams = NTeams; + } + + void updateXteamRedKernel(const Stmt *S, int BlkSz) { + assert(isXteamRedKernel(S)); + XteamRedKernels.find(S)->second.BlockSize = BlkSz; + } + + // Get the cached block size used by Xteam reduction + int getXteamRedBlockSize(const ForStmt *FStmt) { + assert(isXteamRedKernel(FStmt)); + return XteamRedKernels.find(FStmt)->second.BlockSize; + } + + int getXteamRedBlockSize(const OMPExecutableDirective &D) { + assert(isXteamRedKernel(D) && "Expected an Xteam reduction kernel"); + const ForStmt *FStmt = getSingleForStmt(getOptKernelKey(D)); + return getXteamRedBlockSize(FStmt); + } + + /// Erase spec-red related metadata for the input statement + void resetXteamRedKernel(const Stmt *S) { XteamRedKernels.erase(S); } + /// Are we generating xteam reduction kernel for the statement + bool isXteamRedKernel(const Stmt *S) { + return XteamRedKernels.find(S) != XteamRedKernels.end(); + } + bool isXteamRedKernel(const OMPExecutableDirective &D); + + void setCurrentXteamRedStmt(const Stmt *S) { CurrentXteamRedStmt = S; } + const Stmt *getCurrentXteamRedStmt() { return CurrentXteamRedStmt; } + + /// Return true if the provided expression accesses a variable in the provided + /// map, otherwise return false. + bool hasXteamRedVar(const Expr *E, const XteamRedVarMap &RedMap) const; + + /// If present in the provided map, return the reduction variable accessed by + /// the provided expression, otherwise return nullptr. + const VarDecl *getXteamRedVarDecl(const Expr *E, + const XteamRedVarMap &RedMap) const; + + /// Return true if the provided expression accesses the provided variable, + /// otherwise return false. + bool isXteamRedVarExpr(const Expr *E, const VarDecl *VD) const; + + /// Return status indicating whether the call is an Xteam-supported host + /// builtin. + CodeGenModule::NoLoopXteamErr + getStatusOptKernelHostBuiltin(const CallExpr *C) const; + + /// Is the callee in std namespace? + bool isStdNameSpace(const CallExpr *Call) const; + + /// Is the function name recognized as a min builtin by the host compile? + bool isOptKernelHostMin(const CallExpr *Call) const { + std::string CallName = Call->getDirectCallee()->getNameInfo().getAsString(); + if (isStdNameSpace(Call) && !CallName.compare("min")) + return true; + return (!CallName.compare("fmin") || !CallName.compare("fminf") || + !CallName.compare("fminl") || !CallName.compare("__builtin_fmin") || + !CallName.compare("__builtin_fminf") || + !CallName.compare("__builtin_fminl")); + } + + /// Is the function name recognized as a max builtin by the host compile? + bool isOptKernelHostMax(const CallExpr *Call) const { + std::string CallName = Call->getDirectCallee()->getNameInfo().getAsString(); + if (isStdNameSpace(Call) && !CallName.compare("max")) + return true; + return (!CallName.compare("fmax") || !CallName.compare("fmaxf") || + !CallName.compare("fmaxl") || !CallName.compare("__builtin_fmax") || + !CallName.compare("__builtin_fmaxf") || + !CallName.compare("__builtin_fmaxl")); + } + + /// Return status indicating whether the amdgcn device function is supported + /// by Xteam. + CodeGenModule::NoLoopXteamErr + getStatusOptKernelAMDGCNBuiltin(const CallExpr *C) const; + + /// Is the function name recognized as a min builtin by the device compile? + bool isOptKernelAMDGCNMin(const CallExpr *Call) const { + std::string CallName = Call->getDirectCallee()->getNameInfo().getAsString(); + if (isStdNameSpace(Call) && !CallName.compare("min")) + return true; + return (!CallName.compare("fmin[device={arch(amdgcn)}]") || + !CallName.compare("fminf[device={arch(amdgcn)}]") || + !CallName.compare("fminl[device={arch(amdgcn)}]") || + !CallName.compare("fmin") || !CallName.compare("fminf") || + !CallName.compare("fminl") || !CallName.compare("__builtin_fmin") || + !CallName.compare("__builtin_fminf") || + !CallName.compare("__builtin_fminl")); + } + + // Is the function name recognized as a max builtin by the device compile? + bool isOptKernelAMDGCNMax(const CallExpr *Call) const { + std::string CallName = Call->getDirectCallee()->getNameInfo().getAsString(); + if (isStdNameSpace(Call) && !CallName.compare("max")) + return true; + return (!CallName.compare("fmax[device={arch(amdgcn)}]") || + !CallName.compare("fmaxf[device={arch(amdgcn)}]") || + !CallName.compare("fmaxl[device={arch(amdgcn)}]") || + !CallName.compare("fmax") || !CallName.compare("fmaxf") || + !CallName.compare("fmaxl") || !CallName.compare("__builtin_fmax") || + !CallName.compare("__builtin_fmaxf") || + !CallName.compare("__builtin_fmaxl")); + } + + /// Return status indicating whether the call expression is supported by Xteam + /// as a builtin + CodeGenModule::NoLoopXteamErr getStatusOptKernelBuiltin(const CallExpr *C); + + /// Return status indicating if the pseudo-object expression is supported by + /// Xteam + std::pair + getStatusXteamSupportedPseudoObject(const PseudoObjectExpr *PO); + + /// Are we generating multi-device kernel for the statement + bool multiDeviceFStmtEntryExists(const Stmt *S) { + return MultiDeviceKernels.find(S) != MultiDeviceKernels.end(); + } + bool isMultiDeviceKernel(const Stmt *S) { + if (MultiDeviceKernels.find(S) == MultiDeviceKernels.end()) + return false; + MultiDeviceKernelInfo MDInfo = MultiDeviceKernels.find(S)->second; + return MDInfo.CanBeMultiDevice; + } + bool isMultiDeviceKernel(const OMPExecutableDirective &D); + + /// Given a ForStmt for which Multi Device codegen will be done, save the + /// metadata for the LB and UB args. + void saveMultiDeviceArgs(const OMPExecutableDirective &D, + const llvm::Function *F, VarDecl *LBDecl, + VarDecl *UBDecl) { + assert(isMultiDeviceKernel(getSingleForStmt(getOptKernelKey(D))) && + "Must be a multi-device kernel"); + const ForStmt *FStmt = getSingleForStmt(getOptKernelKey(D)); + assert((MultiDeviceKernels.find(FStmt) != MultiDeviceKernels.end()) && + "FStmt not found"); + MultiDeviceKernelInfo &MDInfo = MultiDeviceKernels.find(FStmt)->second; + MDInfo.FunctionBoundsMap.insert( + std::make_pair(F, MultiDeviceBoundsInfo(LBDecl, UBDecl))); + } + + /// Retrieve the metadata for the LB arg. + MultiDeviceBoundsInfo getMultiDeviceBounds(const OMPExecutableDirective &D, + const llvm::Function *F) { + const ForStmt *FStmt = getSingleForStmt(getOptKernelKey(D)); + assert((MultiDeviceKernels.find(FStmt) != MultiDeviceKernels.end()) && + "FStmt not found"); + MultiDeviceKernelInfo MDInfo = MultiDeviceKernels.find(FStmt)->second; + assert(MDInfo.FunctionBoundsMap.find(F) != MDInfo.FunctionBoundsMap.end() && + "Function must exist"); + return MDInfo.FunctionBoundsMap.find(F)->second; + } + + /// Retrieve the metadata for the LB arg. + VarDecl *getMultiDeviceLBArg(const OMPExecutableDirective &D, + const llvm::Function *F) { + return getMultiDeviceBounds(D, F).LBArg; + } + + /// Retrieve the metadata for the LB arg. + VarDecl *getMultiDeviceUBArg(const OMPExecutableDirective &D, + const llvm::Function *F) { + return getMultiDeviceBounds(D, F).UBArg; + } + /// Move some lazily-emitted states to the NewBuilder. This is especially /// essential for the incremental parsing environment like Clang Interpreter, /// because we'll lose all important information after each repl. @@ -2042,6 +2655,52 @@ class CodeGenModule : public CodeGenTypeCache { llvm::Metadata *CreateMetadataIdentifierImpl(QualType T, MetadataTypeMap &Map, StringRef Suffix); + + /// Return success if the directives are nested in a way appropriate for + /// specialized kernel generation. Track the component directives in + /// a vector. Otherwise return an error code. + NoLoopXteamErr checkNest(const OMPExecutableDirective &D, + OptKernelNestDirectives *NestDirs); + NoLoopXteamErr checkTargetNest(const OMPExecutableDirective &D, + OptKernelNestDirectives *NestDirs); + NoLoopXteamErr checkTargetTeamsNest(const OMPExecutableDirective &D, + OptKernelNestDirectives *NestDirs); + + /// Top level checker for no-loop on the for statement + std::pair + getNoLoopForStmtStatus(const OMPExecutableDirective &, const Stmt *); + + // Compute the block size used by optimized kernels. + int computeOptKernelBlockSize(const OptKernelNestDirectives &NestDirs, + bool isXteamRed); + + /// Top level checker for xteam reduction of the loop + std::pair + getXteamRedForStmtStatus(const OMPExecutableDirective &, const Stmt *, + XteamRedVarMap *); + + /// Are clauses on a combined OpenMP construct compatible with no-loop + /// codegen? + NoLoopXteamErr + getNoLoopStatusForClauses(const OptKernelNestDirectives &NestDirs); + + /// Are clauses on a combined OpenMP construct compatible with xteam + /// reduction codegen? + NoLoopXteamErr + getXteamRedStatusForClauses(const OptKernelNestDirectives &NestDirs); + + /// Collect the reduction variables that may satisfy Xteam criteria + std::pair + collectXteamRedVars(const OptKernelNestDirectives &NestDirs); + + /// Top level checker for multi device of the loop + NoLoopXteamErr getMultiDeviceForStmtStatus(const OMPExecutableDirective &, + const Stmt *); + + /// Are clauses on a combined OpenMP construct compatible with multi-device + /// codegen? + NoLoopXteamErr + getMultiDeviceStatusForClauses(const OptKernelNestDirectives &NestDirs); }; } // end namespace CodeGen diff --git a/clang/lib/CodeGen/CodeGenTypes.cpp b/clang/lib/CodeGen/CodeGenTypes.cpp index ea31195b7f92e..40ebf6e057740 100644 --- a/clang/lib/CodeGen/CodeGenTypes.cpp +++ b/clang/lib/CodeGen/CodeGenTypes.cpp @@ -581,6 +581,9 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) { case BuiltinType::Id: \ return llvm::TargetExtType::get(getLLVMContext(), "amdgcn.named.barrier", \ {}, {Scope}); +#define AMDGPU_FEATURE_PREDICATE_TYPE(Name, Id, SingletonId, Width, Align) \ + case BuiltinType::Id: \ + return ConvertType(getContext().getLogicalOperationType()); #include "clang/Basic/AMDGPUTypes.def" #define HLSL_INTANGIBLE_TYPE(Name, Id, SingletonId) case BuiltinType::Id: #include "clang/Basic/HLSLIntangibleTypes.def" diff --git a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp index f49a5af2c9587..988c7ec1271dd 100644 --- a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp @@ -383,6 +383,18 @@ void CodeGenFunction::AddAMDGPUFenceAddressSpaceMMRA(llvm::Instruction *Inst, Inst->setMetadata(LLVMContext::MD_mmra, MMRAMetadata::getMD(Ctx, MMRAs)); } +static Value *GetOrInsertAMDGPUPredicate(CodeGenFunction &CGF, Twine Name) { + auto PTy = IntegerType::getInt1Ty(CGF.getLLVMContext()); + + auto *P = cast( + CGF.CGM.getModule().getOrInsertGlobal(Name.str(), PTy)); + P->setConstant(true); + P->setExternallyInitialized(true); + + return CGF.Builder.CreateLoad( + RawAddress(P, PTy, CharUnits::One(), KnownNonNull)); +} + static Intrinsic::ID getIntrinsicIDforWaveReduction(unsigned BuiltinID) { switch (BuiltinID) { default: @@ -890,6 +902,26 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Function *F = CGM.getIntrinsic(IID, {Args[0]->getType()}); return Builder.CreateCall(F, {Args}); } + case AMDGPU::BI__builtin_amdgcn_global_load_b128: + case AMDGPU::BI__builtin_amdgcn_global_store_b128: { + const bool IsStore = + BuiltinID == AMDGPU::BI__builtin_amdgcn_global_store_b128; + LLVMContext &Ctx = CGM.getLLVMContext(); + SmallVector Args = {EmitScalarExpr(E->getArg(0))}; // addr + if (IsStore) + Args.push_back(EmitScalarExpr(E->getArg(1))); // data + const unsigned ScopeIdx = E->getNumArgs() - 1; + StringRef ScopeLit = + cast(E->getArg(ScopeIdx)->IgnoreParenCasts()) + ->getString(); + llvm::MDNode *MD = + llvm::MDNode::get(Ctx, {llvm::MDString::get(Ctx, ScopeLit)}); + Args.push_back(llvm::MetadataAsValue::get(Ctx, MD)); // scope + llvm::Function *F = + CGM.getIntrinsic(IsStore ? Intrinsic::amdgcn_global_store_b128 + : Intrinsic::amdgcn_global_load_b128); + return Builder.CreateCall(F, Args); + } case AMDGPU::BI__builtin_amdgcn_get_fpenv: { Function *F = CGM.getIntrinsic(Intrinsic::get_fpenv, {llvm::Type::getInt64Ty(getLLVMContext())}); @@ -901,6 +933,23 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Value *Env = EmitScalarExpr(E->getArg(0)); return Builder.CreateCall(F, {Env}); } + case AMDGPU::BI__builtin_amdgcn_processor_is: { + assert(CGM.getTriple().isSPIRV() && + "__builtin_amdgcn_processor_is should never reach CodeGen for " + "concrete targets!"); + StringRef Proc = cast(E->getArg(0))->getString(); + return GetOrInsertAMDGPUPredicate(*this, "llvm.amdgcn.is." + Proc); + } + case AMDGPU::BI__builtin_amdgcn_is_invocable: { + assert(CGM.getTriple().isSPIRV() && + "__builtin_amdgcn_is_invocable should never reach CodeGen for " + "concrete targets!"); + auto *FD = cast( + cast(E->getArg(0))->getReferencedDeclOfCallee()); + StringRef RF = + getContext().BuiltinInfo.getRequiredFeatures(FD->getBuiltinID()); + return GetOrInsertAMDGPUPredicate(*this, "llvm.amdgcn.has." + RF); + } case AMDGPU::BI__builtin_amdgcn_read_exec: return EmitAMDGCNBallotForExec(*this, E, Int64Ty, Int64Ty, false); case AMDGPU::BI__builtin_amdgcn_read_exec_lo: diff --git a/clang/lib/Driver/Action.cpp b/clang/lib/Driver/Action.cpp index 72a42a6f957ee..2f2bc6f05689e 100644 --- a/clang/lib/Driver/Action.cpp +++ b/clang/lib/Driver/Action.cpp @@ -30,6 +30,8 @@ const char *Action::getClassName(ActionClass AC) { case AnalyzeJobClass: return "analyzer"; case CompileJobClass: return "compiler"; + case FortranFrontendJobClass: + return "fortranfrontend"; case BackendJobClass: return "backend"; case AssembleJobClass: return "assembler"; case IfsMergeJobClass: return "interface-stub-merger"; @@ -62,8 +64,19 @@ const char *Action::getClassName(ActionClass AC) { void Action::propagateDeviceOffloadInfo(OffloadKind OKind, const char *OArch, const ToolChain *OToolChain) { // Offload action set its own kinds on their dependences. - if (Kind == OffloadClass) + // But we still need to preserve OffloadingDeviceKind and OffloadingArch + // where toplevel action is an unbundle. + // HIP assumes offload kind and offload arch of OffloadAction to be + // determined by its ctor and not to be changed by subsequent actions, + // otherwise the following use case will break: + // compile -> offload -> bundle -> offload. + if (Kind == OffloadClass) { + if (OKind != OFK_HIP) { + OffloadingDeviceKind = OKind; + OffloadingArch = OArch; + } return; + } // Unbundling actions use the host kinds. if (Kind == OffloadUnbundlingJobClass) return; @@ -225,11 +238,23 @@ OffloadAction::OffloadAction(const HostDependence &HDep, const DeviceDependences &DDeps) : Action(OffloadClass, HDep.getAction()), HostTC(HDep.getToolChain()), DevToolChains(DDeps.getToolChains()) { - // We use the kinds of the host dependence for this action. - OffloadingArch = HDep.getBoundArch(); + auto &OKinds = DDeps.getOffloadKinds(); + auto &BArchs = DDeps.getBoundArchs(); + + // If all inputs agree on the same kind, use it also for this action. + if (llvm::all_of(OKinds, [&](OffloadKind K) { return K == OKinds.front(); })) + OffloadingDeviceKind = OKinds.front(); + + // If we have a single dependency, inherit the architecture from it. + if (OKinds.size() == 1) + OffloadingArch = BArchs.front(); + else + // We use the kinds of the host dependence for this action. + OffloadingArch = HDep.getBoundArch(); + ActiveOffloadKindMask = HDep.getOffloadKinds(); HDep.getAction()->propagateHostOffloadInfo(HDep.getOffloadKinds(), - HDep.getBoundArch()); + OffloadingArch); // Add device inputs and propagate info to the device actions. Do work only if // we have dependencies. diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt index 7c4f70b966c48..a8d83d38264a7 100644 --- a/clang/lib/Driver/CMakeLists.txt +++ b/clang/lib/Driver/CMakeLists.txt @@ -5,6 +5,7 @@ set(LLVM_LINK_COMPONENTS Option ProfileData Support + Object TargetParser WindowsDriver ) @@ -47,6 +48,7 @@ add_clang_library(clangDriver ToolChains/AVR.cpp ToolChains/BareMetal.cpp ToolChains/Clang.cpp + ToolChains/OpaqueOffloadLinker.cpp ToolChains/CommonArgs.cpp ToolChains/CrossWindows.cpp ToolChains/CSKYToolChain.cpp @@ -100,4 +102,5 @@ add_clang_library(clangDriver clangBasic clangLex ${system_libs} + ${LLVM_PTHREAD_LIB} ) diff --git a/clang/lib/Driver/Compilation.cpp b/clang/lib/Driver/Compilation.cpp index 4e300316ae9ba..665d81f99ba45 100644 --- a/clang/lib/Driver/Compilation.cpp +++ b/clang/lib/Driver/Compilation.cpp @@ -21,8 +21,12 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/Triple.h" #include +#include +#include +#include #include #include +#include #include using namespace clang; @@ -232,6 +236,101 @@ static bool ActionFailed(const Action *A, return false; } +namespace { +class JobScheduler { +public: + enum JobState { JS_WAIT, JS_RUN, JS_DONE, JS_FAIL }; + JobScheduler(const JobList &Jobs, size_t NJobs = 1) + : Jobs(Jobs), NumJobs(NJobs) { +#if !LLVM_ENABLE_THREADS + NumJobs = 1; +#endif + for (auto &Job : Jobs) { + JState[&Job] = JS_WAIT; + for (const auto *AI : Job.getDependentActions()) { + for (const auto *CI : ActToCmds[AI]) { + DependentCmds[&Job].push_back(CI); + } + } + for (const auto *CI : ActToCmds[&Job.getSource()]) { + DependentCmds[&Job].push_back(CI); + } + ActToCmds[&Job.getSource()].push_back(&Job); + } + } + /// \return true if all jobs are done. Otherwise, \p Next contains the + /// the next job ready to be executed if it is not null pointer. Otherwise + /// all jobs are running or waiting. + bool IsDone(const Command *&Next) { + std::lock_guard lock(Mutex); + Next = nullptr; + unsigned Done = 0; + unsigned Running = 0; + for (auto &Cmd : Jobs) { + switch (JState[&Cmd]) { + case JS_RUN: + ++Running; + break; + case JS_DONE: + case JS_FAIL: + ++Done; + break; + case JS_WAIT: { + bool InputsReady = true; + for (const auto *CI : DependentCmds[&Cmd]) { + if (JState[CI] == JS_FAIL) { + JState[&Cmd] = JS_FAIL; + ++Done; + InputsReady = false; + break; + } + if (JState[CI] != JS_DONE) { + InputsReady = false; + break; + } + } + if (!Next && InputsReady) { + Next = &Cmd; + } + break; + } + } + } + if (Running >= NumJobs) + Next = nullptr; + return Done == Jobs.size(); + } + + void setJobState(const Command *Cmd, JobState JS) { + std::lock_guard lock(Mutex); + JState[Cmd] = JS; + } + + void launch(std::function Work) { +#if LLVM_ENABLE_THREADS + if (NumJobs == 1) { + Work(); + return; + } + std::thread Th(Work); + Th.detach(); +#else + Work(); +#endif + } + +private: + std::mutex Mutex; + const JobList &Jobs; + llvm::DenseMap JState; + llvm::DenseMap> + ActToCmds; + llvm::DenseMap> + DependentCmds; + size_t NumJobs; // Number of parallel jobs to run +}; +} // namespace + void Compilation::ExecuteJobs(const JobList &Jobs, FailingCommandList &FailingCommands, bool LogOnly) const { @@ -239,16 +338,35 @@ void Compilation::ExecuteJobs(const JobList &Jobs, // inputs on the command line even one of them failed. // In all but CLMode, execute all the jobs unless the necessary inputs for the // job is missing due to previous failures. - for (const auto &Job : Jobs) { - if (ActionFailed(&Job.getSource(), FailingCommands)) + JobScheduler JS(Jobs, getDriver().getNumberOfParallelJobs()); + + const Command *Next = nullptr; + while (!JS.IsDone(Next)) { + if (!Next) { + // sleep, rather than yield so we do not busy wait. + std::this_thread::sleep_for(std::chrono::milliseconds(1)); continue; - const Command *FailingCommand = nullptr; - if (int Res = ExecuteCommand(Job, FailingCommand, LogOnly)) { - FailingCommands.push_back(std::make_pair(Res, FailingCommand)); + } + + if (ActionFailed(&Next->getSource(), FailingCommands)) { + JS.setJobState(Next, JobScheduler::JS_FAIL); // Bail as soon as one command fails in cl driver mode. if (TheDriver.IsCLMode()) return; + continue; } + + JS.setJobState(Next, JobScheduler::JS_RUN); + auto Work = [&, Next]() { + const Command *FailingCommand = nullptr; + if (int Res = ExecuteCommand(*Next, FailingCommand, LogOnly)) { + FailingCommands.push_back(std::make_pair(Res, FailingCommand)); + JS.setJobState(Next, JobScheduler::JS_FAIL); + } else { + JS.setJobState(Next, JobScheduler::JS_DONE); + } + }; + JS.launch(Work); } } diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 40ea513e85427..2c323af94d0ef 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -61,11 +61,13 @@ #include "clang/Driver/InputInfo.h" #include "clang/Driver/Job.h" #include "clang/Driver/Options.h" +#include "clang/Driver/OptionUtils.h" #include "clang/Driver/Phases.h" #include "clang/Driver/SanitizerArgs.h" #include "clang/Driver/Tool.h" -#include "clang/Driver/ToolChain.h" #include "clang/Driver/Types.h" +#include "clang/Driver/ToolChain.h" +#include "clang/Driver/Util.h" #include "clang/Lex/DependencyDirectivesScanner.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/STLExtras.h" @@ -211,7 +213,8 @@ Driver::Driver(StringRef ClangExecutable, StringRef TargetTriple, CCPrintProcessStats(false), CCPrintInternalStats(false), TargetTriple(TargetTriple), Saver(Alloc), PrependArg(nullptr), PreferredLinker(CLANG_DEFAULT_LINKER), CheckInputsExist(true), - ProbePrecompiled(true), SuppressMissingInputWarning(false) { + ProbePrecompiled(true), SuppressMissingInputWarning(false), + NumParallelJobs(1) { // Provide a sane fallback if no VFS is specified. if (!this->VFS) this->VFS = llvm::vfs::getRealFileSystem(); @@ -889,6 +892,7 @@ Driver::OpenMPRuntimeKind Driver::getOpenMPRuntime(const ArgList &Args) const { .Case("libomp", OMPRT_OMP) .Case("libgomp", OMPRT_GOMP) .Case("libiomp5", OMPRT_IOMP5) + .Case("libbolt", OMPRT_BOLT) .Default(OMPRT_Unknown); if (RT == OMPRT_Unknown) { @@ -1318,7 +1322,6 @@ bool Driver::loadConfigFiles() { UserConfigDir = static_cast(CfgDir); } } - // Prepare list of directories where config file is searched for. StringRef CfgFileSearchDirs[] = {UserConfigDir, SystemConfigDir, Dir}; ExpCtx.setSearchDirs(CfgFileSearchDirs); @@ -1689,6 +1692,13 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) { BitcodeEmbed = static_cast(Model); } + // Force -parallel-jobs=1 when verbose is set to avoid corrupted output + if (Args.hasArg(options::OPT_v)) + setNumberOfParallelJobs(1); + else + setNumberOfParallelJobs( + getLastArgIntValue(Args, options::OPT_parallel_jobs_EQ, 1, Diags)); + // Remove existing compilation database so that each job can append to it. if (Arg *A = Args.getLastArg(options::OPT_MJ)) llvm::sys::fs::remove(A->getValue()); @@ -3171,6 +3181,19 @@ class OffloadingActionBuilder final { ABRT_Ignore_Host, }; + /// ID to identify each device compilation. For CUDA it is simply the + /// GPU arch string. For HIP it is either the GPU arch string or GPU + /// arch string plus feature strings delimited by a plus sign, e.g. + /// gfx906+xnack. + struct TargetID { + /// Target ID string which is persistent throughout the compilation. + const char *ID; + TargetID(OffloadArch Arch) { ID = OffloadArchToString(Arch); } + TargetID(const char *ID) : ID(ID) {} + operator const char *() { return ID; } + operator StringRef() { return StringRef(ID); } + }; + protected: /// Compilation associated with this builder. Compilation &C; @@ -3251,19 +3274,6 @@ class OffloadingActionBuilder final { bool CompileDeviceOnly = false; bool EmitLLVM = false; bool EmitAsm = false; - - /// ID to identify each device compilation. For CUDA it is simply the - /// GPU arch string. For HIP it is either the GPU arch string or GPU - /// arch string plus feature strings delimited by a plus sign, e.g. - /// gfx906+xnack. - struct TargetID { - /// Target ID string which is persistent throughout the compilation. - const char *ID; - TargetID(OffloadArch Arch) { ID = OffloadArchToString(Arch); } - TargetID(const char *ID) : ID(ID) {} - operator const char *() { return ID; } - operator StringRef() { return StringRef(ID); } - }; /// List of GPU architectures to use in this compilation. SmallVector GpuArchList; @@ -3751,9 +3761,10 @@ class OffloadingActionBuilder final { } // By default, we produce an action for each device arch. - for (Action *&A : CudaDeviceActions) + for (Action *&A : CudaDeviceActions) { A = C.getDriver().ConstructPhaseAction(C, Args, CurPhase, A, AssociatedOffloadKind); + } if (CompileDeviceOnly && CurPhase == FinalPhase && BundleOutput && *BundleOutput) { @@ -4356,6 +4367,9 @@ void Driver::BuildActions(Compilation &C, DerivedArgList &Args, return; } + Arg *FinalPhaseArg; + phases::ID FinalPhase = getFinalPhase(Args, &FinalPhaseArg); + handleArguments(C, Args, Inputs, Actions); if (Args.hasFlag(options::OPT_fmodules_driver, @@ -4436,6 +4450,11 @@ void Driver::BuildDefaultActions(Compilation &C, DerivedArgList &Args, for (phases::ID Phase : PL) { +#if FIXME + // We are done if this step is past what the user requested. + if (Phase > FinalPhase) + break; +#endif // Add any offload action the host action depends on. if (!UseNewOffloadingDriver) Current = OffloadBuilder->addDeviceDependencesToHostAction( @@ -5152,6 +5171,8 @@ Action *Driver::ConstructPhaseAction( return C.MakeAction(Input, OutputTy); } + case phases::FortranFrontend: + llvm::report_fatal_error("fortranfrontend action invalid here."); case phases::Compile: { if (Args.hasArg(options::OPT_fsyntax_only)) return C.MakeAction(Input, types::TY_Nothing); @@ -6028,17 +6049,23 @@ InputInfoList Driver::BuildJobsForActionNoCache( UI.DependentOffloadKind == Action::OFK_HIP, OffloadingPrefix), BaseInput); + if (UI.DependentOffloadKind == Action::OFK_Host && + llvm::sys::path::extension(InputInfos[0].getFilename()) == ".a") + CurI = InputInfos[0]; // Save the unbundling result. UnbundlingResults.push_back(CurI); // Get the unique string identifier for this dependence and cache the // result. StringRef Arch; - if (TargetDeviceOffloadKind == Action::OFK_HIP) { + if (TargetDeviceOffloadKind == Action::OFK_HIP || + TargetDeviceOffloadKind == Action::OFK_OpenMP) { if (UI.DependentOffloadKind == Action::OFK_Host) Arch = StringRef(); - else + else if (TargetDeviceOffloadKind == Action::OFK_HIP) Arch = UI.DependentBoundArch; + else if (TargetDeviceOffloadKind == Action::OFK_OpenMP) + Arch = UI.DependentToolChain->getTargetID(); } else Arch = BoundArch; @@ -6047,6 +6074,9 @@ InputInfoList Driver::BuildJobsForActionNoCache( CurI}; } + if (BoundArch == "gnu") { + BoundArch = StringRef(""); + } // Now that we have all the results generated, select the one that should be // returned for the current depending action. std::pair ActionTC = { @@ -6064,6 +6094,12 @@ InputInfoList Driver::BuildJobsForActionNoCache( /*CreatePrefixForHost=*/isa(A) || !(A->getOffloadingHostActiveKinds() == Action::OFK_None || AtTopLevel)); + StringRef TargetIDStr = TC->getTargetID(); + if (!TargetIDStr.empty() && BoundArch.empty()) { + BoundArch = TargetIDStr; + OffloadingPrefix.append("-").append(TargetIDStr.str()); + } + Result = InputInfo(A, GetNamedOutputPath(C, *JA, BaseInput, BoundArch, AtTopLevel, MultipleArchs, OffloadingPrefix), @@ -6328,6 +6364,14 @@ const char *Driver::GetNamedOutputPath(Compilation &C, const JobAction &JA, !C.getArgs().hasArg(options::OPT__SLASH_Fo)) || CCGenDiagnostics) { StringRef Name = llvm::sys::path::filename(BaseInput); + size_t pos = Name.find_last_of("."); + StringRef PrefixName = Name.substr(0, pos); + SmallString<128> fname(PrefixName.str().c_str()); + if (!BoundArch.empty()) { + fname += "-"; + fname.append(BoundArch); + } + SmallString<128> TmpName; std::pair Split = Name.split('.'); const char *Suffix = types::getTypeTempSuffix(JA.getType(), IsCLMode() || IsDXCMode()); @@ -6421,8 +6465,11 @@ const char *Driver::GetNamedOutputPath(Compilation &C, const JobAction &JA, NamedOutput = MakeCLOutputFilename(C.getArgs(), Val, BaseName, types::TY_Object); } else { - const char *Suffix = - types::getTypeTempSuffix(JA.getType(), IsCLMode() || IsDXCMode()); + const char *Suffix = nullptr; + if (BaseName.ends_with(".a")) + Suffix = "a"; + else + Suffix = types::getTypeTempSuffix(JA.getType(), IsCLMode() || IsDXCMode()); assert(Suffix && "All types used for output should have a suffix."); std::string::size_type End = std::string::npos; @@ -6481,9 +6528,10 @@ const char *Driver::GetNamedOutputPath(Compilation &C, const JobAction &JA, // Must share the same path to conflict. if (SameFile) { StringRef Name = llvm::sys::path::filename(BaseInput); - std::pair Split = Name.split('.'); + size_t pos = Name.find_last_of("."); + StringRef PrefixName = Name.substr(0, pos); std::string TmpName = GetTemporaryPath( - Split.first, + PrefixName, types::getTypeTempSuffix(JA.getType(), IsCLMode() || IsDXCMode())); return C.addTempFile(C.getArgs().MakeArgString(TmpName)); } @@ -7093,7 +7141,7 @@ Driver::getOptionVisibilityMask(bool UseDriverMode) const { return llvm::opt::Visibility(options::CLOption); if (IsDXCMode()) return llvm::opt::Visibility(options::DXCOption); - if (IsFlangMode()) { + if (IsFlangMode()) { return llvm::opt::Visibility(options::FlangOption); } return llvm::opt::Visibility(options::ClangOption); diff --git a/clang/lib/Driver/Job.cpp b/clang/lib/Driver/Job.cpp index 715429bcd2096..11192ec68b372 100644 --- a/clang/lib/Driver/Job.cpp +++ b/clang/lib/Driver/Job.cpp @@ -41,9 +41,12 @@ Command::Command(const Action &Source, const Tool &Creator, const char *PrependArg) : Source(Source), Creator(Creator), ResponseSupport(ResponseSupport), Executable(Executable), PrependArg(PrependArg), Arguments(Arguments) { - for (const auto &II : Inputs) - if (II.isFilename()) + for (const auto &II : Inputs) { + if (II.isFilename()) { InputInfoList.push_back(II); + DependentActions.push_back(II.getAction()); + } + } for (const auto &II : Outputs) if (II.isFilename()) OutputFilenames.push_back(II.getFilename()); diff --git a/clang/lib/Driver/Phases.cpp b/clang/lib/Driver/Phases.cpp index 01598c59bd9eb..afe3a3d311a79 100644 --- a/clang/lib/Driver/Phases.cpp +++ b/clang/lib/Driver/Phases.cpp @@ -16,6 +16,7 @@ const char *phases::getPhaseName(ID Id) { switch (Id) { case Preprocess: return "preprocessor"; case Precompile: return "precompiler"; + case FortranFrontend: return "fortranfrontend"; case Compile: return "compiler"; case Backend: return "backend"; case Assemble: return "assembler"; diff --git a/clang/lib/Driver/README_amd_driver_trunk_diffs b/clang/lib/Driver/README_amd_driver_trunk_diffs new file mode 100644 index 0000000000000..d781403617f12 --- /dev/null +++ b/clang/lib/Driver/README_amd_driver_trunk_diffs @@ -0,0 +1,56 @@ + +README_amd_driver_trunk_diffs +============================= + +There is an effort to minimize the differences between the upstream LLVM trunk +Driver code and the Driver code for the downstream amd-staging branch. +This readme discusses the Driver differences found in these directories: + + llvm-project/clang/lib/Driver + llvm-project/clang/include/clang/Driver + +Efforts should be made to minimize trunk differences in upstream files by +putting non-upstream functions in different filenames, if that is possible. +Some effort to do this has already started in some of the below listed +subsystems. + +These are the areas where amd-staging differs from the trunk: + +- Support for legacy/classic flang driver. This will eventually go away + when llvm flang (flang) is in production. + +- Support for the generation of parallel jobs. Unless someone upstreams + this support, this difference will remain. + +- Support for --opaque-offload-linker. This using the same offload driver, actions + and phases. It is only an alternative command generator in ToolChains/Clang.cpp + LinerWrapper:ConstructJob. Instead of the driver generating four commands + (unpackage, clang-linker-wrapper, clang driver, and ld.lld), this option generates + a debugable set of 9 commands that allows the developer to intercept, analyze, insert + changes, and test changes to the various steps that are managed in memory + by clang-linker-wrapper. The file ToolChains/OpaqueOffloadLinker.cpp contains + the driver support for this option. + +- Support for the old Driver and bundle/unbundle in HIP toolchain. This difference + may be removed when HIP supports the new driver which includes packager and + clang-linker-wrapper. + +- Support for openmp bolt runtime. See https://github.com/pmodels/bolt + +- Support for OMPT and OMPD that is not yet upstream. AMD participates in the + development of these two OpenMP subsystems. + +- Support for certain optimizations such as cross team reductions and + -plugin-opt=-amdgpu-spill-cfi-saved-regs + +- Support for AMDGPU Code object version. + +- Support for Static Device Libs (SDL). This support was introduced by amd + many years ago. Its definition of sdl and corresponding search methods + is more generic than the introduction of static device libs by the "new" + driver in recent years. Both techniques extend host library management + to support heterogeneous libraries. However, the definition of SDL and + library search methods is much broader with the amd implementation. + There is a detailed document to describe SDL. + + diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index eea5c2f7f4a6a..5041f59a75c6d 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -439,9 +439,6 @@ static const DriverSuffix *FindDriverSuffix(StringRef ProgName, size_t &Pos) { {"cl", "--driver-mode=cl"}, {"++", "--driver-mode=g++"}, {"flang", "--driver-mode=flang"}, - // For backwards compatibility, we create a symlink for `flang` called - // `flang-new`. This will be removed in the future. - {"flang-new", "--driver-mode=flang"}, {"clang-dxc", "--driver-mode=dxc"}, }; @@ -551,6 +548,12 @@ StringRef ToolChain::getDefaultUniversalArchName() const { } } +Tool *ToolChain::getFlang() const { + if (!Flang) + Flang.reset(new tools::Flang(*this)); + return Flang.get(); +} + std::string ToolChain::getInputFilename(const InputInfo &Input) const { return Input.getFilename(); } @@ -566,12 +569,6 @@ Tool *ToolChain::getClang() const { return Clang.get(); } -Tool *ToolChain::getFlang() const { - if (!Flang) - Flang.reset(new tools::Flang(*this)); - return Flang.get(); -} - Tool *ToolChain::buildAssembler() const { return new tools::ClangAs(*this); } @@ -657,6 +654,9 @@ Tool *ToolChain::getTool(Action::ActionClass AC) const { case Action::ObjcopyJobClass: llvm_unreachable("Invalid tool kind."); + case Action::FortranFrontendJobClass: + llvm::report_fatal_error("fortranfrontend is invalid tool kind here."); + case Action::CompileJobClass: case Action::PrecompileJobClass: case Action::PreprocessJobClass: @@ -669,7 +669,6 @@ Tool *ToolChain::getTool(Action::ActionClass AC) const { case Action::OffloadBundlingJobClass: case Action::OffloadUnbundlingJobClass: return getOffloadBundler(); - case Action::OffloadPackagerJobClass: return getOffloadPackager(); case Action::LinkerWrapperJobClass: @@ -1299,6 +1298,14 @@ void ToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, // Each toolchain should provide the appropriate include flags. } +void ToolChain::addActionsFromClangTargetOptions( + const ArgList &DriverArgs, + ArgStringList &CC1Args, + const JobAction &JA, + Compilation &C, + const InputInfoList &Inputs) const +{} + void ToolChain::addClangTargetOptions( const ArgList &DriverArgs, ArgStringList &CC1Args, Action::OffloadKind DeviceOffloadKind) const {} @@ -1720,6 +1727,10 @@ llvm::opt::DerivedArgList *ToolChain::TranslateOpenMPTargetArgs( // Handle -Xopenmp-target flags for (auto *A : Args) { + // -munsafe-fp-atomics applies to device toolchain + if (A->getOption().matches(options::OPT_munsafe_fp_atomics)) + DAL->append(A); + // Exclude flags which may only apply to the host toolchain. // Do not exclude flags when the host triple (AuxTriple) // matches the current toolchain triple. If it is not present diff --git a/clang/lib/Driver/ToolChains/AIX.cpp b/clang/lib/Driver/ToolChains/AIX.cpp index 066b59305fe3f..ffd7b69205440 100644 --- a/clang/lib/Driver/ToolChains/AIX.cpp +++ b/clang/lib/Driver/ToolChains/AIX.cpp @@ -321,6 +321,9 @@ void aix::Linker::ConstructJob(Compilation &C, const JobAction &JA, case Driver::OMPRT_GOMP: CmdArgs.push_back("-lgomp"); break; + case Driver::OMPRT_BOLT: + llvm::report_fatal_error("AIX toolchain does not support OMPRT_BOLT"); + break; case Driver::OMPRT_Unknown: // Already diagnosed. break; @@ -393,6 +396,7 @@ void AIX::AddOpenMPIncludeArgs(const ArgList &DriverArgs, break; case Driver::OMPRT_IOMP5: case Driver::OMPRT_GOMP: + case Driver::OMPRT_BOLT: case Driver::OMPRT_Unknown: // Unknown / unsupported include paths. break; diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp b/clang/lib/Driver/ToolChains/AMDGPU.cpp index 654a382e87e40..4f30b532bec55 100644 --- a/clang/lib/Driver/ToolChains/AMDGPU.cpp +++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp @@ -244,7 +244,8 @@ RocmInstallationDetector::getInstallationPathCandidates() { // Some versions of the aomp package install to /opt/rocm/aomp/bin if (ParentName == "llvm" || ParentName.starts_with("aomp")) ParentDir = llvm::sys::path::parent_path(ParentDir); - + // Some versions of the aomp package install to /opt/rocm/aomp/bin + // and it seems ParentDir is already pointing to correct place. return Candidate(ParentDir.str(), /*StrictChecking=*/true); }; @@ -664,7 +665,8 @@ void amdgpu::Linker::ConstructJob(Compilation &C, const JobAction &JA, void amdgpu::getAMDGPUTargetFeatures(const Driver &D, const llvm::Triple &Triple, const llvm::opt::ArgList &Args, - std::vector &Features) { + std::vector &Features, + StringRef TcTargetID) { // Add target ID features to -target-feature options. No diagnostics should // be emitted here since invalid target ID is diagnosed at other places. StringRef TargetID; @@ -672,6 +674,10 @@ void amdgpu::getAMDGPUTargetFeatures(const Driver &D, TargetID = Args.getLastArgValue(options::OPT_mcpu_EQ); else if (Args.hasArg(options::OPT_march_EQ)) TargetID = Args.getLastArgValue(options::OPT_march_EQ); + + // Use this toolchain's TargetID if mcpu is not defined + if (TargetID.empty() && !TcTargetID.empty()) + TargetID = TcTargetID; if (!TargetID.empty()) { llvm::StringMap FeatureMap; auto OptionalGpuArch = parseTargetID(Triple, TargetID, &FeatureMap); @@ -695,6 +701,13 @@ void amdgpu::getAMDGPUTargetFeatures(const Driver &D, options::OPT_mno_wavefrontsize64, false)) Features.push_back("+wavefrontsize64"); + // TODO: Remove during upstreaming target id. + if (Args.getLastArg(options::OPT_msram_ecc_legacy)) { + Features.push_back("+sramecc"); + } + if (Args.getLastArg(options::OPT_mno_sram_ecc_legacy)) { + Features.push_back("-sramecc"); + } if (Args.hasFlag(options::OPT_mamdgpu_precise_memory_op, options::OPT_mno_amdgpu_precise_memory_op, false)) Features.push_back("+precise-memory"); @@ -703,6 +716,27 @@ void amdgpu::getAMDGPUTargetFeatures(const Driver &D, options::OPT_m_amdgpu_Features_Group); } +llvm::SmallVector +amdgpu::dlr::getCommonDeviceLibNames( + const llvm::opt::ArgList &DriverArgs, const SanitizerArgs &SanArgs, + const Driver &D, const std::string &GPUArch, bool isOpenMP, + const RocmInstallationDetector &RocmInstallation, + const clang::driver::Action::OffloadKind DeviceOffloadingKind) { + auto Kind = llvm::AMDGPU::parseArchAMDGCN(GPUArch); + const StringRef CanonArch = llvm::AMDGPU::getArchNameAMDGCN(Kind); + + StringRef LibDeviceFile = RocmInstallation.getLibDeviceFile(CanonArch); + auto ABIVer = DeviceLibABIVersion::fromCodeObjectVersion( + getAMDGPUCodeObjectVersion(D, DriverArgs)); + if (!RocmInstallation.checkCommonBitcodeLibs(CanonArch, LibDeviceFile, + ABIVer)) + return {}; + + return RocmInstallation.getCommonBitcodeLibs( + DriverArgs, LibDeviceFile, GPUArch, DeviceOffloadingKind, + SanArgs.needsAsanRt()); +} + /// AMDGPU Toolchain AMDGPUToolChain::AMDGPUToolChain(const Driver &D, const llvm::Triple &Triple, const ArgList &Args) @@ -1028,7 +1062,7 @@ RocmInstallationDetector::getCommonBitcodeLibs( auto AddBCLib = [&](ToolChain::BitCodeLibraryInfo BCLib, bool Internalize = true) { BCLib.ShouldInternalize = Internalize; - BCLibs.emplace_back(BCLib); + BCLibs.push_back(BCLib); }; auto AddSanBCLibs = [&]() { if (Pref.GPUSan) @@ -1054,6 +1088,13 @@ RocmInstallationDetector::getCommonBitcodeLibs( return BCLibs; } +bool AMDGPUToolChain::shouldSkipArgument(const llvm::opt::Arg *A) const { + Option O = A->getOption(); + if (O.matches(options::OPT_fPIE) || O.matches(options::OPT_fpie)) + return true; + return false; +} + llvm::SmallVector ROCMToolChain::getCommonDeviceLibNames( const llvm::opt::ArgList &DriverArgs, const std::string &GPUArch, diff --git a/clang/lib/Driver/ToolChains/AMDGPU.h b/clang/lib/Driver/ToolChains/AMDGPU.h index e90a5736911e4..7185b24aec0f8 100644 --- a/clang/lib/Driver/ToolChains/AMDGPU.h +++ b/clang/lib/Driver/ToolChains/AMDGPU.h @@ -38,7 +38,50 @@ class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { void getAMDGPUTargetFeatures(const Driver &D, const llvm::Triple &Triple, const llvm::opt::ArgList &Args, - std::vector &Features); + std::vector &Features, + StringRef TcTargetID = StringRef()); + +namespace dlr { +llvm::SmallVector +getCommonDeviceLibNames(const llvm::opt::ArgList &DriverArgs, + const SanitizerArgs &SanArgs, const Driver &D, + const std::string &GPUArch, bool isOpenMP, + const RocmInstallationDetector &RocmInstallation, + const clang::driver::Action::OffloadKind DeviceOffloadingKind = Action::OFK_OpenMP); + +const char * +getCbslCommandArgs(Compilation &C, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CbslArgs, + const SmallVectorImpl &InputFileNames, + llvm::StringRef OutputFilePrefix); + +const char * +getLinkCommandArgs(Compilation &C, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &LastLinkArgs, const ToolChain &TC, + const llvm::Triple &Triple, llvm::StringRef TargetID, + llvm::StringRef OutputFilePrefix, const char *InputFileName, + const RocmInstallationDetector &RocmInstallation, + llvm::opt::ArgStringList &EnvironmentLibraryPaths); + +const char *getOptCommandArgs(Compilation &C, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &OptArgs, + const llvm::Triple &Triple, + llvm::StringRef TargetID, + llvm::StringRef OutputFilePrefix, + const char *InputFileName); + +const char * +getLlcCommandArgs(Compilation &C, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &LlcArgs, const llvm::Triple &Triple, + llvm::StringRef TargetID, llvm::StringRef OutputFilePrefix, + const char *InputFileName, bool OutputIsAsm = false); + +const char *getLldCommandArgs( + Compilation &C, const InputInfo &Output, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &LldArgs, const llvm::Triple &Triple, + llvm::StringRef TargetID, const char *InputFileName, + const std::optional OutputFilePrefix = std::nullopt); +} // end namespace dlr void addFullLTOPartitionOption(const Driver &D, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs); @@ -50,7 +93,7 @@ namespace toolchains { class LLVM_LIBRARY_VISIBILITY AMDGPUToolChain : public Generic_ELF { protected: const std::map OptionsDefault; - + unsigned CodeObjectVersion = 5; Tool *buildLinker() const override; StringRef getOptionDefault(options::ID OptID) const { auto opt = OptionsDefault.find(OptID); @@ -107,6 +150,11 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUToolChain : public Generic_ELF { StringRef TargetID, const llvm::opt::Arg *A) const; + /// Should skip argument. + bool shouldSkipArgument(const llvm::opt::Arg *Arg) const; + + unsigned GetCodeObjectVersion() const { return CodeObjectVersion; } + /// Uses amdgpu-arch tool to get arch of the system GPU. Will return error /// if unable to find one. virtual Expected> diff --git a/clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp b/clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp index 2b41d54a9eb73..e73b4f02cac39 100644 --- a/clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp +++ b/clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp @@ -8,11 +8,16 @@ #include "AMDGPUOpenMP.h" #include "AMDGPU.h" +#include "clang/Driver/CommonArgs.h" #include "clang/Driver/Compilation.h" #include "clang/Driver/Driver.h" #include "clang/Driver/Options.h" +#include "clang/Driver/SanitizerArgs.h" #include "clang/Driver/Tool.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/Support/Path.h" +#include "llvm/Support/Process.h" using namespace clang::driver; using namespace clang::driver::toolchains; @@ -20,10 +25,334 @@ using namespace clang::driver::tools; using namespace clang; using namespace llvm::opt; -AMDGPUOpenMPToolChain::AMDGPUOpenMPToolChain(const Driver &D, - const llvm::Triple &Triple, - const ToolChain &HostTC, - const ArgList &Args) +#if defined(_WIN32) || defined(_WIN64) +#define NULL_FILE "nul" +#else +#define NULL_FILE "/dev/null" +#endif + +namespace { + +static void addBCLib(const Driver &D, const ArgList &Args, + ArgStringList &CmdArgs, ArgStringList LibraryPaths, + StringRef BCName, bool postClangLink) { + StringRef FullName; + for (std::string LibraryPath : LibraryPaths) { + SmallString<128> Path(LibraryPath); + llvm::sys::path::append(Path, BCName); + FullName = Path; + if (llvm::sys::fs::exists(FullName)) { + if (postClangLink) + CmdArgs.push_back("-mlink-builtin-bitcode"); + CmdArgs.push_back(Args.MakeArgString(FullName)); + return; + } + } + D.Diag(diag::err_drv_no_such_file) << BCName; +} + +static const char *getOutputFileName(Compilation &C, StringRef Base, + const char *Postfix, + const char *Extension) { + const char *OutputFileName; + if (C.getDriver().isSaveTempsEnabled()) { + OutputFileName = + C.getArgs().MakeArgString(Base.str() + Postfix + "." + Extension); + } else { + std::string TmpName = + C.getDriver().GetTemporaryPath(Base.str() + Postfix, Extension); + OutputFileName = C.addTempFile(C.getArgs().MakeArgString(TmpName)); + } + return OutputFileName; +} + +static void addOptLevelArg(const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs, bool IsLlc) { + StringRef OOpt = "2"; // Default if no user command line specification + if (Arg *A = Args.getLastArg(options::OPT_O_Group)) { + if (A->getOption().matches(options::OPT_O4) || + A->getOption().matches(options::OPT_Ofast)) + OOpt = "3"; + else if (A->getOption().matches(options::OPT_O0)) + OOpt = "0"; + else if (A->getOption().matches(options::OPT_O)) { + // Clang and opt support -Os/-Oz; llc only supports -O0, -O1, -O2 and -O3 + // so we map -Os/-Oz to -O2. + // Only clang supports -Og, and maps it to -O1. + // We map anything else to -O2. + OOpt = llvm::StringSwitch(A->getValue()) + .Case("1", "1") + .Case("2", "2") + .Case("3", "3") + .Case("s", IsLlc ? "2" : "s") + .Case("z", IsLlc ? "2" : "z") + .Case("g", "1") + .Default("0"); + } + } else { + // Nothing in the O_Group + if (isTargetFastUsed(Args)) + OOpt = "3"; + } + // To remove unreferenced internalized functions, add globaldce pass to O0 + if (OOpt == "0" && !IsLlc) + CmdArgs.push_back(Args.MakeArgString("-passes=default,globaldce")); + else + CmdArgs.push_back(Args.MakeArgString("-O" + OOpt)); +} + +static void addAMDTargetArgs(Compilation &C, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs, bool IsLlc) { + unsigned CodeObjVer = + getOrCheckAMDGPUCodeObjectVersion(C.getDriver(), C.getArgs(), true); + if (CodeObjVer) + CmdArgs.push_back(Args.MakeArgString( + Twine("--amdhsa-code-object-version=") + Twine(CodeObjVer))); + + // Pass optimization arg to llc. + addOptLevelArg(Args, CmdArgs, /*IsLlc=*/IsLlc); + CmdArgs.push_back("-mtriple=amdgcn-amd-amdhsa"); +} + +static void addROCmEnvArgs(const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs, + const char *ROCmEnvVarName) { + // Get the environment variable and add to llc. + std::optional OptEnv = + llvm::sys::Process::GetEnv(ROCmEnvVarName); + if (OptEnv.has_value()) { + SmallVector Envs; + SplitString(OptEnv.value(), Envs); + for (StringRef Env : Envs) + CmdArgs.push_back(Args.MakeArgString(Env.trim())); + } +} + +static void addCommonArgs(Compilation &C, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs, + const llvm::Triple &Triple, llvm::StringRef TargetID, + const char *InputFileName, const char *ROCmEnvVarName, + bool isLld = false) { + CmdArgs.push_back(InputFileName); + + StringRef GPUArch = getProcessorFromTargetID(Triple, TargetID); + CmdArgs.push_back( + Args.MakeArgString((isLld ? "-plugin-opt=mcpu=" : "-mcpu=") + GPUArch)); + + // Get the environment variable and add command args + addROCmEnvArgs(Args, CmdArgs, ROCmEnvVarName); + + // Extract all the -m options + std::vector Features; + amdgpu::getAMDGPUTargetFeatures(C.getDriver(), Triple, Args, Features, + TargetID.str()); + + // Add features to mattr such as xnack + std::string MAttrString = isLld ? "-plugin-opt=-mattr=" : "-mattr="; + for (auto OneFeature : Features) { + MAttrString.append(Args.MakeArgString(OneFeature)); + if (OneFeature != Features.back()) + MAttrString.append(","); + } + if (!Features.empty()) + CmdArgs.push_back(Args.MakeArgString(MAttrString)); + + if (!isLld) + for (const Arg *A : Args.filtered(options::OPT_mllvm)) + CmdArgs.push_back(A->getValue(0)); +} +} // namespace + +const char *amdgpu::dlr::getCbslCommandArgs( + Compilation &C, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CbslArgs, + const SmallVectorImpl &InputFileNames, + llvm::StringRef OutputFilePrefix) { + StringRef disable_fn = Args.MakeArgString( + C.getDriver().Dir + "/../lib/disable_dynamic_devmem.ll"); + + // When requested by the user via -fdisable-host-devmem, + // to avoid host service thread for potential performance concerns, + // disable host assisted device memory + // management by providing empty implementation of devmem routine + // (only available in new device rtl) + if (llvm::sys::fs::exists(disable_fn) && + Args.hasFlag(options::OPT_fdisable_host_devmem, + options::OPT_fenable_host_devmem, false)) + CbslArgs.push_back(Args.MakeArgString(disable_fn)); + + for (const auto &II : InputFileNames) + CbslArgs.push_back(Args.MakeArgString(II)); + + // Get the environment variable ROCM_CBSL_ARGS and add to + // clang-build-select-link. + addROCmEnvArgs(Args, CbslArgs, "ROCM_CBSL_ARGS"); + + CbslArgs.push_back("-o"); + auto PreLinkFileName = + getOutputFileName(C, OutputFilePrefix, "-prelinked", "bc"); + CbslArgs.push_back(PreLinkFileName); + return PreLinkFileName; +} + +const char *amdgpu::dlr::getLinkCommandArgs( + Compilation &C, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &LastLinkArgs, const ToolChain &TC, + const llvm::Triple &Triple, llvm::StringRef TargetID, + llvm::StringRef OutputFilePrefix, const char *InputFileName, + const RocmInstallationDetector &RocmInstallation, + llvm::opt::ArgStringList &EnvironmentLibraryPaths) { + LastLinkArgs.push_back(Args.MakeArgString(InputFileName)); + + // Get the environment variable ROCM_LINK_ARGS and add to llvm-link. + addROCmEnvArgs(Args, LastLinkArgs, "ROCM_LINK_ARGS"); + + // Last link brings in libomptarget and subset of user-option bc files. + // This link uses --internalize to internalize libomptarget symbols. + // --internalize ignores the first bc file which came from previous link. + LastLinkArgs.push_back(Args.MakeArgString("--internalize")); + LastLinkArgs.push_back(Args.MakeArgString("--only-needed")); + + std::string LibSuffix = "lib"; + if (TC.getSanitizerArgs(Args).needsAsanRt()) + LibSuffix.append("/asan"); + if (Arg *A = Args.getLastArg(options::OPT_fopenmp_runtimelib_EQ)) { + LibSuffix = A->getValue(); + if (TC.getSanitizerArgs(Args).needsAsanRt()) + LibSuffix.append("/asan"); + } + + llvm::SmallVector BCLibs; + StringRef GPUArch = getProcessorFromTargetID(Triple, TargetID); + + // When the base lib directory is called `lib` we enable + // the look-up of the libomptarget bc lib to happen and if not present + // where it is expected it means we are using the build tree compiler + // not the installed compiler. + std::string LibDeviceName = "/libomptarget-amdgpu.bc"; + + if (!Args.hasArg(options::OPT_offloadlib)) { + // Check if libomptarget device bitcode can be found in a LIBRARY_PATH dir + bool EnvOmpLibDeviceFound = false; + for (auto &EnvLibraryPath : EnvironmentLibraryPaths) { + std::string EnvOmpLibDevice = EnvLibraryPath + LibDeviceName; + if (llvm::sys::fs::exists(EnvOmpLibDevice)) { + EnvOmpLibDeviceFound = true; + BCLibs.emplace_back(EnvOmpLibDevice); + break; + } + } + + // If not found in LIBRARY_PATH, use default for the correct LibSuffix. + if (!EnvOmpLibDeviceFound) { + StringRef bc_file_suf = Args.MakeArgString(C.getDriver().Dir + "/../" + + LibSuffix + LibDeviceName); + StringRef bc_file_lib = + Args.MakeArgString(C.getDriver().Dir + "/../lib" + LibDeviceName); + if (llvm::sys::fs::exists(bc_file_suf)) + BCLibs.emplace_back(Args.MakeArgString(bc_file_suf)); + else if (llvm::sys::fs::exists(bc_file_lib)) + // In case a LibSuffix version not found, use suffix "lib" + BCLibs.emplace_back(Args.MakeArgString(bc_file_lib)); + else + TC.getDriver().Diag(diag::err_drv_omp_offload_target_bcruntime_not_found) + << "libomptarget-amdgpu.bc"; + } + + if (!Args.hasArg(options::OPT_no_offloadlib)) + // Add the generic set of libraries, OpenMP subset only + BCLibs.append(amdgpu::dlr::getCommonDeviceLibNames( + C.getArgs(), TC.getSanitizerArgs(C.getArgs()), C.getDriver(), + GPUArch.str(), /* isOpenMP=*/true, RocmInstallation)); + } + + llvm::for_each(BCLibs, [&](auto BCLib) { + LastLinkArgs.push_back(Args.MakeArgString(BCLib.Path)); + }); + + LastLinkArgs.push_back("-o"); + auto LastLinkFileName = + getOutputFileName(C, OutputFilePrefix, "-linked", "bc"); + LastLinkArgs.push_back(LastLinkFileName); + + return LastLinkFileName; +} + +const char *amdgpu::dlr::getOptCommandArgs(Compilation &C, + const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &OptArgs, + const llvm::Triple &Triple, + llvm::StringRef TargetID, + llvm::StringRef OutputFilePrefix, + const char *InputFileName) { + addAMDTargetArgs(C, Args, OptArgs, /*IsLlc*/ false); + // OptArgs.push_back(Args.MakeArgString("-openmp-opt-disable=1")); + + OptArgs.push_back("-o"); + auto OutputFileName = + getOutputFileName(C, OutputFilePrefix, "-optimized", "bc"); + OptArgs.push_back(OutputFileName); + addCommonArgs(C, Args, OptArgs, Triple, TargetID, InputFileName, + "ROCM_OPT_ARGS"); + + return OutputFileName; +} + +const char *amdgpu::dlr::getLlcCommandArgs( + Compilation &C, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &LlcArgs, const llvm::Triple &Triple, + llvm::StringRef TargetID, llvm::StringRef OutputFilePrefix, + const char *InputFileName, bool OutputIsAsm) { + addAMDTargetArgs(C, Args, LlcArgs, /*IsLLc*/ true); + + if (Arg *A = Args.getLastArgNoClaim(options::OPT_g_Group)) + if (!A->getOption().matches(options::OPT_g0) && + !A->getOption().matches(options::OPT_ggdb0)) + LlcArgs.push_back("-amdgpu-spill-cfi-saved-regs"); + + LlcArgs.push_back( + Args.MakeArgString(Twine("-filetype=") + (OutputIsAsm ? "asm" : "obj"))); + + // Add output filename + LlcArgs.push_back("-o"); + const char *LlcOutputFile = + getOutputFileName(C, OutputFilePrefix, "", OutputIsAsm ? "s" : "o"); + LlcArgs.push_back(LlcOutputFile); + addCommonArgs(C, Args, LlcArgs, Triple, TargetID, InputFileName, + "ROCM_LLC_ARGS"); + + return LlcOutputFile; +} + +const char *amdgpu::dlr::getLldCommandArgs( + Compilation &C, const InputInfo &Output, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &LldArgs, const llvm::Triple &Triple, + llvm::StringRef TargetID, const char *InputFileName, + const std::optional OutputFilePrefix) { + LldArgs.push_back("-flavor"); + LldArgs.push_back("gnu"); + LldArgs.push_back("--no-undefined"); + LldArgs.push_back("-shared"); + + if (Arg *A = Args.getLastArgNoClaim(options::OPT_g_Group)) + if (!A->getOption().matches(options::OPT_g0) && + !A->getOption().matches(options::OPT_ggdb0)) + LldArgs.push_back("-plugin-opt=-amdgpu-spill-cfi-saved-regs"); + + addCommonArgs(C, Args, LldArgs, Triple, TargetID, InputFileName, + "ROCM_LLD_ARGS", /* isLld */ true); + + LldArgs.push_back("-o"); + const char *LldOutputFile = + OutputFilePrefix ? getOutputFileName(C, *OutputFilePrefix, "", "out") + : Output.getFilename(); + LldArgs.push_back(LldOutputFile); + + return LldOutputFile; +} + +AMDGPUOpenMPToolChain::AMDGPUOpenMPToolChain(const Driver &D, const llvm::Triple &Triple, + const ToolChain &HostTC, const ArgList &Args) : ROCMToolChain(D, Triple, Args), HostTC(HostTC) { // Lookup binaries into the driver directory, this is used to // discover the 'amdgpu-arch' executable. @@ -37,9 +366,50 @@ void AMDGPUOpenMPToolChain::addClangTargetOptions( Action::OffloadKind DeviceOffloadingKind) const { HostTC.addClangTargetOptions(DriverArgs, CC1Args, DeviceOffloadingKind); + StringRef GPUArch = DriverArgs.getLastArgValue(options::OPT_march_EQ); + assert(DeviceOffloadingKind == Action::OFK_OpenMP && "Only OpenMP offloading kinds are supported."); + // Extract all the -m options + std::vector Features; + amdgpu::getAMDGPUTargetFeatures(getDriver(), getTriple(), DriverArgs, + Features, GPUArch); + + for (auto OneFeature : unifyTargetFeatures(Features)) { + CC1Args.push_back("-target-feature"); + CC1Args.push_back(OneFeature.data()); + } + + if (DriverArgs.hasFlag(options::OPT_fgpu_approx_transcendentals, + options::OPT_fno_gpu_approx_transcendentals, false)) + CC1Args.push_back("-fcuda-approx-transcendentals"); + + if (DriverArgs.hasFlag(options::OPT_fgpu_rdc, options::OPT_fno_gpu_rdc, + false)) + CC1Args.push_back("-fgpu-rdc"); + + StringRef MaxThreadsPerBlock = + DriverArgs.getLastArgValue(options::OPT_gpu_max_threads_per_block_EQ); + if (!MaxThreadsPerBlock.empty()) { + std::string ArgStr = + std::string("--gpu-max-threads-per-block=") + MaxThreadsPerBlock.str(); + CC1Args.push_back(DriverArgs.MakeArgStringRef(ArgStr)); + } + + if (DriverArgs.hasFlag(options::OPT_fgpu_allow_device_init, + options::OPT_fno_gpu_allow_device_init, false)) + CC1Args.push_back("-fgpu-allow-device-init"); + + // Default to "hidden" visibility, as object level linking will not be + // supported for the foreseeable future. + if (!DriverArgs.hasArg(options::OPT_fvisibility_EQ, + options::OPT_fvisibility_ms_compat) && + DeviceOffloadingKind != Action::OFK_OpenMP) { + CC1Args.append({"-fvisibility", "hidden"}); + CC1Args.push_back("-fapply-global-visibility-to-externs"); + } + if (!DriverArgs.hasFlag(options::OPT_offloadlib, options::OPT_no_offloadlib, true)) return; @@ -50,14 +420,34 @@ void AMDGPUOpenMPToolChain::addClangTargetOptions( CC1Args.push_back(DriverArgs.MakeArgString(BCFile.Path)); } + ArgStringList LibraryPaths; + + // Find in --hip-device-lib-path and HIP_LIBRARY_PATH. + for (auto Path : + RocmInstallation->getRocmDeviceLibPathArg()) + LibraryPaths.push_back(DriverArgs.MakeArgString(Path)); + // Link the bitcode library late if we're using device LTO. if (getDriver().isUsingOffloadLTO()) return; + + std::string BitcodeSuffix; + BitcodeSuffix = llvm::Twine("old-amdgpu-" + GPUArch).str(); + + addDirectoryList(DriverArgs, LibraryPaths, "", "HIP_DEVICE_LIB_PATH"); + + // Maintain compatability with --hip-device-lib. + auto BCLibs = DriverArgs.getAllArgValues(options::OPT_hip_device_lib_EQ); + if (!BCLibs.empty()) + for (auto Lib : BCLibs) + addBCLib(getDriver(), DriverArgs, CC1Args, LibraryPaths, Lib, + /* PostClang Link? */ true); } llvm::opt::DerivedArgList *AMDGPUOpenMPToolChain::TranslateArgs( const llvm::opt::DerivedArgList &Args, StringRef BoundArch, Action::OffloadKind DeviceOffloadKind) const { + DerivedArgList *DAL = HostTC.TranslateArgs(Args, BoundArch, DeviceOffloadKind); @@ -97,14 +487,66 @@ AMDGPUOpenMPToolChain::GetCXXStdlibType(const ArgList &Args) const { return HostTC.GetCXXStdlibType(Args); } +void AMDGPUOpenMPToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, + ArgStringList &CC1Args) const { + const Driver &D = HostTC.getDriver(); + CC1Args.push_back("-internal-isystem"); + CC1Args.push_back(DriverArgs.MakeArgString(D.Dir + "/../include")); + CC1Args.push_back("-internal-isystem"); + CC1Args.push_back(DriverArgs.MakeArgString(D.Dir + "/../../../include")); + + HostTC.AddClangSystemIncludeArgs(DriverArgs, CC1Args); + + CC1Args.push_back("-internal-isystem"); + SmallString<128> P(HostTC.getDriver().ResourceDir); + llvm::sys::path::append(P, "include/cuda_wrappers"); + CC1Args.push_back(DriverArgs.MakeArgString(P)); +} + void AMDGPUOpenMPToolChain::AddClangCXXStdlibIncludeArgs( const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CC1Args) const { HostTC.AddClangCXXStdlibIncludeArgs(Args, CC1Args); } -void AMDGPUOpenMPToolChain::AddClangSystemIncludeArgs( - const ArgList &DriverArgs, ArgStringList &CC1Args) const { - HostTC.AddClangSystemIncludeArgs(DriverArgs, CC1Args); +/// Convert path list to Fortran frontend argument +static void AddFlangSysIncludeArg(const ArgList &DriverArgs, + ArgStringList &Flang1args, + ToolChain::path_list IncludePathList) { + std::string ArgValue; // Path argument value + + // Make up argument value consisting of paths separated by colons + bool first = true; + for (auto P : IncludePathList) { + if (first) { + first = false; + } else { + ArgValue += ":"; + } + ArgValue += P; + } + + // Add the argument + Flang1args.push_back("-stdinc"); + Flang1args.push_back(DriverArgs.MakeArgString(ArgValue)); +} + +/// Currently only adding include dir from install directory +void AMDGPUOpenMPToolChain::AddFlangSystemIncludeArgs(const ArgList &DriverArgs, + ArgStringList &Flang1args) const { + path_list IncludePathList; + const Driver &D = getDriver(); + + if (DriverArgs.hasArg(options::OPT_nostdinc)) + return; + + { + SmallString<128> P(D.Dir); + llvm::sys::path::append(P, "../include"); + IncludePathList.push_back(DriverArgs.MakeArgString(P.str())); + } + + AddFlangSysIncludeArg(DriverArgs, Flang1args, IncludePathList); + return; } void AMDGPUOpenMPToolChain::AddIAMCUIncludeArgs(const ArgList &Args, diff --git a/clang/lib/Driver/ToolChains/AMDGPUOpenMP.h b/clang/lib/Driver/ToolChains/AMDGPUOpenMP.h index cbafdf57fa466..831c0a6b2aab7 100644 --- a/clang/lib/Driver/ToolChains/AMDGPUOpenMP.h +++ b/clang/lib/Driver/ToolChains/AMDGPUOpenMP.h @@ -9,19 +9,62 @@ #ifndef LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_AMDGPUOPENMP_H #define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_AMDGPUOPENMP_H -#include "AMDGPU.h" -#include "clang/Driver/Tool.h" #include "clang/Driver/ToolChain.h" +#include "clang/Driver/Tool.h" +#include "AMDGPU.h" namespace clang { namespace driver { +/// Is -Ofast used? +bool isOFastUsed(const llvm::opt::ArgList &Args); + +/// Is -fopenmp-target-fast or -Ofast used +bool isTargetFastUsed(const llvm::opt::ArgList &Args); + +/// Ignore possibility of environment variables if either +/// -fopenmp-target-fast or -Ofast is used. +bool shouldIgnoreEnvVars(const llvm::opt::ArgList &Args); + namespace toolchains { class AMDGPUOpenMPToolChain; } -namespace toolchains { +namespace tools { + +namespace AMDGCN { + // Construct command for creating HIP fatbin. + void constructHIPFatbinCommand(Compilation &C, const JobAction &JA, + StringRef OutputFileName, const InputInfoList &Inputs, + const llvm::opt::ArgList &TCArgs, const Tool& T); + +// Runs llvm-link/opt/llc/lld, which links multiple LLVM bitcode, together with +// device library, then compiles it to ISA in a shared object. +class LLVM_LIBRARY_VISIBILITY OpenMPLinker : public Tool { +public: + OpenMPLinker(const ToolChain &TC) + : Tool("AMDGCN::OpenMPLinker", "amdgcn-link", TC) {} + + bool hasIntegratedCPP() const override { return false; } + void ConstructJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, const InputInfoList &Inputs, + const llvm::opt::ArgList &TCArgs, + const char *LinkingOutput) const override; + +private: + /// \return output file name from build-select, prelink, and preopt + const char *constructOmpExtraCmds(Compilation &C, const JobAction &JA, + const InputInfoList &Inputs, + const llvm::opt::ArgList &Args, + llvm::StringRef TargetID, + llvm::StringRef OutputFilePrefix) const; +}; + +} // end namespace AMDGCN +} // end namespace tools + +namespace toolchains { class LLVM_LIBRARY_VISIBILITY AMDGPUOpenMPToolChain final : public ROCMToolChain { public: @@ -40,8 +83,18 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUOpenMPToolChain final addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, Action::OffloadKind DeviceOffloadKind) const override; + + bool useIntegratedAs() const override { return true; } + bool isCrossCompiling() const override { return true; } + bool isPICDefault() const override { return false; } + bool isPIEDefault(const llvm::opt::ArgList &Args) const override { return false; } + bool isPICDefaultForced() const override { return false; } + bool SupportsProfiling() const override { return false; } + bool IsMathErrnoDefault() const override { return false; } + void addClangWarningOptions(llvm::opt::ArgStringList &CC1Args) const override; CXXStdlibType GetCXXStdlibType(const llvm::opt::ArgList &Args) const override; + void AddClangCXXStdlibIncludeArgs( const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CC1Args) const override; @@ -50,13 +103,21 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUOpenMPToolChain final llvm::opt::ArgStringList &CC1Args) const override; void AddIAMCUIncludeArgs(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const override; + void + AddFlangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &FlangArgs) const override; SanitizerMask getSupportedSanitizers() const override; + StringRef getAsanRTLPath() const { + return RocmInstallation->getAsanRTLPath(); + } + VersionTuple computeMSVCVersion(const Driver *D, const llvm::opt::ArgList &Args) const override; + unsigned GetDefaultDwarfVersion() const override { return 5; } llvm::SmallVector getDeviceLibs(const llvm::opt::ArgList &Args, const Action::OffloadKind DeviceOffloadKind) const override; diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 79edc561c551f..9a1c454d5594a 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -5,8 +5,8 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// - #include "Clang.h" +#include "AMDGPUOpenMP.h" #include "Arch/ARM.h" #include "Arch/LoongArch.h" #include "Arch/Mips.h" @@ -23,6 +23,7 @@ #include "clang/Basic/LangOptions.h" #include "clang/Basic/MakeSupport.h" #include "clang/Basic/ObjCRuntime.h" +#include "clang/Basic/TargetID.h" #include "clang/Basic/Version.h" #include "clang/Config/config.h" #include "clang/Driver/Action.h" @@ -328,6 +329,33 @@ static void addCoveragePrefixMapArg(const Driver &D, const ArgList &Args, } } +/// Is -Ofast used? +bool clang::driver::isOFastUsed(const ArgList &Args) { + if (Arg *A = Args.getLastArg(options::OPT_O_Group)) + if (A->getOption().matches(options::OPT_Ofast)) + return true; + return false; +} + +/// Is -fopenmp-target-fast or -Ofast used +bool clang::driver::isTargetFastUsed(const ArgList &Args) { + return Args.hasFlag(options::OPT_fopenmp_target_fast, + options::OPT_fno_openmp_target_fast, isOFastUsed(Args)); +} + +/// Ignore possibility of environment variables if either +/// -fopenmp-target-fast or -Ofast is used. +bool clang::driver::shouldIgnoreEnvVars(const ArgList &Args) { + if (Args.hasFlag(options::OPT_fno_openmp_target_fast, + options::OPT_fopenmp_target_fast, false)) + return false; + + if (isTargetFastUsed(Args)) + return true; + + return false; +} + /// Add -x lang to \p CmdArgs for \p Input. static void addDashXForInput(const ArgList &Args, const InputInfo &Input, ArgStringList &CmdArgs) { @@ -959,6 +987,17 @@ void Clang::AddPreprocessingOptions(Compilation &C, const JobAction &JA, CmdArgs.push_back("__clang_openmp_device_functions.h"); } + // Add include for either -fopenmp= or -fopenmp + if (Args.hasFlag(options::OPT_fopenmp, options::OPT_fopenmp_EQ, + options::OPT_fno_openmp, false)){ + if (D.getOpenMPRuntime(Args) == Driver::OMPRT_BOLT) { + CmdArgs.push_back("-I"); + CmdArgs.push_back(Args.MakeArgString(D.Dir + "/../include/bolt")); + } + CmdArgs.push_back("-I"); + CmdArgs.push_back(Args.MakeArgString(D.Dir + "/../include")); + } + if (Args.hasArg(options::OPT_foffload_via_llvm)) { // Add llvm_wrappers/* to our system include path. This lets us wrap // standard library headers and other headers. @@ -3018,9 +3057,14 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, FPExceptionBehavior) << Args.MakeArgString("-ffp-exception-behavior=" + Val); TrappingMath = TrappingMathPresent = false; - if (Val == "ignore" || Val == "maytrap") + if (Val == "ignore" || Val == "maytrap") { FPExceptionBehavior = Val; - else if (Val == "strict") { + // AOCC Begin + if (Val == "maytrap") { + ; + } + // AOCC End + } else if (Val == "strict") { FPExceptionBehavior = Val; TrappingMath = TrappingMathPresent = true; } else @@ -3720,6 +3764,7 @@ static void RenderOpenACCOptions(const Driver &D, const ArgList &Args, if (!Args.hasArg(options::OPT_fopenacc)) return; + D.Diag(diag::warn_openacc_experimental); CmdArgs.push_back("-fopenacc"); } @@ -4658,6 +4703,40 @@ renderDebugOptions(const ToolChain &TC, const Driver &D, const llvm::Triple &T, renderDwarfFormat(D, T, Args, CmdArgs, EffectiveDWARFVersion); RenderDebugInfoCompressionArgs(Args, CmdArgs, D, TC); + bool EmitDwarfForAMDGCN = + EmitDwarf && + (T.isAMDGCN() || (T.isSPIRV() && T.getVendor() == llvm::Triple::AMD)); + if (EmitDwarfForAMDGCN) + CmdArgs.append({"-mllvm", "-amdgpu-spill-cfi-saved-regs"}); + if (Arg *A = Args.getLastArg(options::OPT_gheterogeneous_dwarf_EQ)) { + if (StringRef(A->getValue()) == "diexpr") + D.Diag(clang::diag::err_drv_unsupported_opt_with_suggestion) + << A->getAsString(Args) << "-gheterogeneous-dwarf=diexpression"; + A->render(Args, CmdArgs); + } else if (EmitDwarfForAMDGCN) { +#ifndef NDEBUG + // There doesn't seem to be a straightforward way to "render" an option + // acquired from the OptTable into a string we can append to CmdArgs. + // All of the logic is buried in "accept" which works directly in terms + // of an ArgList. + // + // Instead, assert that the static string we are adding to CmdArgs has + // the same shape as what a bare -gheterogeneous-dwarf would alias to + // if the user has provided it in ArgList. + const Option GHeterogeneousDwarf = + getDriverOptTable().getOption(options::OPT_gheterogeneous_dwarf); + const Option Aliased = GHeterogeneousDwarf.getAlias(); + assert(Aliased.isValid() && "gheterogeneous-dwarf must be an alias"); + assert(Aliased.getName() == "gheterogeneous-dwarf=" && + "gheterogeneous-dwarf must alias gheterogeneous-dwarf="); + assert(StringRef(GHeterogeneousDwarf.getAliasArgs()) == "diexpression" && + GHeterogeneousDwarf.getAliasArgs()[strlen("diexpression") + 1] == + '\0' && + "gheterogeneous-dwarf must alias gheterogeneous-dwarf=diexpression"); +#endif + CmdArgs.push_back("-gheterogeneous-dwarf=diexpression"); + } + // This controls whether or not we perform JustMyCode instrumentation. if (Args.hasFlag(options::OPT_fjmc, options::OPT_fno_jmc, false)) { if (TC.getTriple().isOSBinFormatELF() || @@ -5118,6 +5197,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, if (Triple.isAMDGCN() && IsOpenMPDevice && Args.hasArg(options::OPT_S) && Args.hasArg(options::OPT_emit_llvm)) { CmdArgs.push_back("-emit-llvm"); + } else if (Triple.isAMDGCN() && IsOpenMPDevice && + Args.hasArg(options::OPT_S)) { + CmdArgs.push_back("-S"); } else { CmdArgs.push_back("-emit-llvm-bc"); } @@ -5234,6 +5316,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-disable-llvm-passes"); // Render target options. + TC.addActionsFromClangTargetOptions(Args, CmdArgs, JA, C, Inputs); TC.addClangTargetOptions(Args, CmdArgs, JA.getOffloadingDeviceKind()); // reject options that shouldn't be supported in bitcode @@ -5864,7 +5947,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, } if (Args.hasFlag(options::OPT_fms_volatile, options::OPT_fno_ms_volatile, - Triple.isX86() && IsWindowsMSVC)) + Triple.isX86() && D.IsCLMode())) CmdArgs.push_back("-fms-volatile"); // Non-PIC code defaults to -fdirect-access-external-data while PIC code @@ -5936,6 +6019,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, /*ForAS*/ false, /*IsAux*/ true); } + TC.addActionsFromClangTargetOptions(Args, CmdArgs, JA, C, Inputs); TC.addClangTargetOptions(Args, CmdArgs, JA.getOffloadingDeviceKind()); addMCModel(D, Args, Triple, RelocationModel, CmdArgs); @@ -5958,6 +6042,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, // Add the target cpu std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ false); + // In case args have been translated and -march deleted, get GPU from TC + if (CPU.empty()) + CPU = TC.getTargetID().str(); if (!CPU.empty()) { CmdArgs.push_back("-target-cpu"); CmdArgs.push_back(Args.MakeArgString(CPU)); @@ -6559,6 +6646,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, switch (D.getOpenMPRuntime(Args)) { case Driver::OMPRT_OMP: case Driver::OMPRT_IOMP5: + case Driver::OMPRT_BOLT: // Clang can generate useful OpenMP code for these two runtime libraries. CmdArgs.push_back("-fopenmp"); @@ -6579,17 +6667,81 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.AddAllArgs(CmdArgs, options::OPT_fopenmp_cuda_blocks_per_sm_EQ); Args.AddAllArgs(CmdArgs, options::OPT_fopenmp_cuda_teams_reduction_recs_num_EQ); + Args.AddAllArgs(CmdArgs, options::OPT_fopenmp_gpu_threads_per_team_EQ); + Args.AddAllArgs(CmdArgs, + options::OPT_fopenmp_target_xteam_reduction_blocksize_EQ); if (Args.hasFlag(options::OPT_fopenmp_optimistic_collapse, options::OPT_fno_openmp_optimistic_collapse, /*Default=*/false)) CmdArgs.push_back("-fopenmp-optimistic-collapse"); + if (isTargetFastUsed(Args)) { + if (!Args.hasArg(options::OPT_O_Group)) + CmdArgs.push_back("-O3"); + + CmdArgs.push_back("-fopenmp-target-fast"); + } else + CmdArgs.push_back("-fno-openmp-target-fast"); + + if (Args.hasFlag(options::OPT_fopenmp_target_ignore_env_vars, + options::OPT_fno_openmp_target_ignore_env_vars, + shouldIgnoreEnvVars(Args))) + CmdArgs.push_back("-fopenmp-target-ignore-env-vars"); + else + CmdArgs.push_back("-fno-openmp-target-ignore-env-vars"); + + if (Args.hasFlag(options::OPT_fopenmp_target_big_jump_loop, + options::OPT_fno_openmp_target_big_jump_loop, true)) + CmdArgs.push_back("-fopenmp-target-big-jump-loop"); + else + CmdArgs.push_back("-fno-openmp-target-big-jump-loop"); + + if (Args.hasFlag(options::OPT_fopenmp_target_no_loop, + options::OPT_fno_openmp_target_no_loop, true)) + CmdArgs.push_back("-fopenmp-target-no-loop"); + else + CmdArgs.push_back("-fno-openmp-target-no-loop"); + + if (Args.hasFlag(options::OPT_fopenmp_target_xteam_reduction, + options::OPT_fno_openmp_target_xteam_reduction, true)) + CmdArgs.push_back("-fopenmp-target-xteam-reduction"); + else + CmdArgs.push_back("-fno-openmp-target-xteam-reduction"); + + if (Args.hasFlag(options::OPT_fopenmp_target_fast_reduction, + options::OPT_fno_openmp_target_fast_reduction, false)) + CmdArgs.push_back("-fopenmp-target-fast-reduction"); + else + CmdArgs.push_back("-fno-openmp-target-fast-reduction"); + + if (Args.hasFlag(options::OPT_fopenmp_target_multi_device, + options::OPT_fno_openmp_target_multi_device, false)) + CmdArgs.push_back("-fopenmp-target-multi-device"); + else + CmdArgs.push_back("-fno-openmp-target-multi-device"); + + if (Args.hasFlag(options::OPT_fopenmp_target_xteam_scan, + options::OPT_fno_openmp_target_xteam_scan, false)) + CmdArgs.push_back("-fopenmp-target-xteam-scan"); + else + CmdArgs.push_back("-fno-openmp-target-xteam-scan"); + + if (Args.hasFlag(options::OPT_fopenmp_target_xteam_no_loop_scan, + options::OPT_fno_openmp_target_xteam_no_loop_scan, + false)) + CmdArgs.push_back("-fopenmp-target-xteam-no-loop-scan"); + else + CmdArgs.push_back("-fno-openmp-target-xteam-no-loop-scan"); // When in OpenMP offloading mode with NVPTX target, forward // cuda-mode flag if (Args.hasFlag(options::OPT_fopenmp_cuda_mode, options::OPT_fno_openmp_cuda_mode, /*Default=*/false)) CmdArgs.push_back("-fopenmp-cuda-mode"); + // When in OpenMP offloading mode, enable or disable the new device + // runtime. + CmdArgs.push_back("-fopenmp-target-new-runtime"); + // When in OpenMP offloading mode, enable debugging on the device. Args.AddAllArgs(CmdArgs, options::OPT_fopenmp_target_debug_EQ); if (Args.hasFlag(options::OPT_fopenmp_target_debug, @@ -6606,14 +6758,33 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, options::OPT_fno_openmp_assume_threads_oversubscription, /*Default=*/false)) CmdArgs.push_back("-fopenmp-assume-threads-oversubscription"); - if (Args.hasArg(options::OPT_fopenmp_assume_no_thread_state)) + + if (Args.hasFlag(options::OPT_fopenmp_assume_no_thread_state, + options::OPT_fno_openmp_assume_no_thread_state, + isTargetFastUsed(Args))) CmdArgs.push_back("-fopenmp-assume-no-thread-state"); - if (Args.hasArg(options::OPT_fopenmp_assume_no_nested_parallelism)) + else + CmdArgs.push_back("-fno-openmp-assume-no-thread-state"); + + if (Args.hasFlag(options::OPT_fopenmp_assume_no_nested_parallelism, + options::OPT_fno_openmp_assume_no_nested_parallelism, + isTargetFastUsed(Args))) CmdArgs.push_back("-fopenmp-assume-no-nested-parallelism"); + else + CmdArgs.push_back("-fno-openmp-assume-no-nested-parallelism"); + if (Args.hasArg(options::OPT_fopenmp_offload_mandatory)) CmdArgs.push_back("-fopenmp-offload-mandatory"); if (Args.hasArg(options::OPT_fopenmp_force_usm)) CmdArgs.push_back("-fopenmp-force-usm"); + + if (Args.hasFlag(options::OPT_fno_openmp_allow_kernel_io, + options::OPT_fopenmp_allow_kernel_io, + isTargetFastUsed(Args))) + CmdArgs.push_back("-fno-openmp-allow-kernel-io"); + else + CmdArgs.push_back("-fopenmp-allow-kernel-io"); + break; default: // By default, if Clang doesn't know how to generate useful OpenMP code @@ -7070,7 +7241,8 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, // Imitate GCC 4.2.1 by default if -fms-compatibility is not in effect. GNUCVer = VersionTuple(4, 2, 1); } - if (!GNUCVer.empty()) { + if (C.getDefaultToolChain().getArch() != llvm::Triple::amdgcn && + !GNUCVer.empty()) { CmdArgs.push_back( Args.MakeArgString("-fgnuc-version=" + GNUCVer.getAsString())); } @@ -7590,14 +7762,22 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, // be added so both IR can be captured. if ((C.getDriver().isSaveTempsEnabled() || JA.isHostOffloading(Action::OFK_OpenMP)) && - !(C.getDriver().embedBitcodeInObject() && !IsUsingLTO) && - isa(JA)) - CmdArgs.push_back("-disable-llvm-passes"); + !(C.getDriver().embedBitcodeInObject() && !C.getDriver().isUsingLTO()) && + isa(JA)) { + // We do not want to disable llvm opt passes if we are offloading + // amdgpu openmp code, and -save-temps is specified. + // We want the same opt passes run regardless of setting -save-temps. + if (!(Triple.isAMDGCN() && C.getDriver().isSaveTempsEnabled() && + JA.getOffloadingDeviceKind() == Action::OFK_OpenMP)) + CmdArgs.push_back("-disable-llvm-passes"); + } Args.AddAllArgs(CmdArgs, options::OPT_undef); - const char *Exec = D.getClangProgramPath(); + std::string AltPath = D.getInstalledDir(); + AltPath += "/../alt/bin/clang-" + std::to_string(LLVM_VERSION_MAJOR); + const char *Exec = D.getClangProgramPath(); // Optionally embed the -cc1 level arguments into the debug info or a // section, for build analysis. // Also record command line arguments into the debug info if @@ -8732,12 +8912,15 @@ void ClangAs::ConstructJob(Compilation &C, const JobAction &JA, } if (Triple.isAMDGPU()) - handleAMDGPUCodeObjectVersionOptions(D, Args, CmdArgs, /*IsCC1As=*/true); + handleAMDGPUCodeObjectVersionOptions(D, C.getArgs(), CmdArgs, + /*IsCC1As=*/true); assert(Input.isFilename() && "Invalid input."); CmdArgs.push_back(Input.getFilename()); - const char *Exec = getToolChain().getDriver().getClangProgramPath(); + // TODO This is a workaround to enable using -save-temps with flang + // const char *Exec = getToolChain().getDriver().getClangProgramPath(); + const char *Exec = Args.MakeArgString(getToolChain().GetProgramPath("clang")); if (D.CC1Main && !D.CCGenDiagnostics) { // Invoke cc1as directly in this process. C.addCommand(std::make_unique( @@ -8805,22 +8988,9 @@ void OffloadBundler::ConstructJob(Compilation &C, const JobAction &JA, Triples += '-'; Triples += CurDep->getOffloadingArch(); } - - // TODO: Replace parsing of -march flag. Can be done by storing GPUArch - // with each toolchain. - StringRef GPUArchName; - if (CurKind == Action::OFK_OpenMP) { - // Extract GPUArch from -march argument in TC argument list. - for (unsigned ArgIndex = 0; ArgIndex < TCArgs.size(); ArgIndex++) { - auto ArchStr = StringRef(TCArgs.getArgString(ArgIndex)); - auto Arch = ArchStr.starts_with_insensitive("-march="); - if (Arch) { - GPUArchName = ArchStr.substr(7); - Triples += "-"; - break; - } - } - Triples += GPUArchName.str(); + if (CurKind == Action::OFK_OpenMP && !CurTC->getTargetID().empty()) { + Triples += '-'; + Triples += CurTC->getTargetID(); } } CmdArgs.push_back(TCArgs.MakeArgString(Triples)); @@ -8854,7 +9024,23 @@ void OffloadBundler::ConstructJob(Compilation &C, const JobAction &JA, C.addCommand(std::make_unique( JA, *this, ResponseFileSupport::None(), TCArgs.MakeArgString(getToolChain().GetProgramPath(getShortName())), - CmdArgs, ArrayRef(), Output)); + CmdArgs, Inputs, Output)); +} + +static bool isArchiveOfBundlesFileName(StringRef FilePath) { + StringRef FileName = llvm::sys::path::filename(FilePath); + if (!FileName.ends_with(".a")) + return false; + + + if (FileName.starts_with("lib")) { + if (FileName.contains("amdgcn") && FileName.contains("gfx")) + return false; + if (FileName.contains("nvptx") && FileName.contains("sm_")) + return false; + } + + return true; } void OffloadBundler::ConstructJobMultipleOutputs( @@ -8877,6 +9063,11 @@ void OffloadBundler::ConstructJobMultipleOutputs( assert(Inputs.size() == 1 && "Expecting to unbundle a single file!"); InputInfo Input = Inputs.front(); + StringRef FileName = Input.getFilename(); + + if (isArchiveOfBundlesFileName(FileName)) { + return; + } // Get the type. CmdArgs.push_back(TCArgs.MakeArgString( @@ -8891,7 +9082,8 @@ void OffloadBundler::ConstructJobMultipleOutputs( Triples += ','; auto &Dep = DepInfo[I]; - Triples += Action::GetOffloadKindName(Dep.DependentOffloadKind); + auto OffloadKind = Dep.DependentOffloadKind; + Triples += Action::GetOffloadKindName(OffloadKind); Triples += '-'; Triples += Dep.DependentToolChain->getTriple().normalize( llvm::Triple::CanonicalForm::FOUR_IDENT); @@ -8901,21 +9093,10 @@ void OffloadBundler::ConstructJobMultipleOutputs( Triples += '-'; Triples += Dep.DependentBoundArch; } - // TODO: Replace parsing of -march flag. Can be done by storing GPUArch - // with each toolchain. - StringRef GPUArchName; - if (Dep.DependentOffloadKind == Action::OFK_OpenMP) { - // Extract GPUArch from -march argument in TC argument list. - for (unsigned ArgIndex = 0; ArgIndex < TCArgs.size(); ArgIndex++) { - StringRef ArchStr = StringRef(TCArgs.getArgString(ArgIndex)); - auto Arch = ArchStr.starts_with_insensitive("-march="); - if (Arch) { - GPUArchName = ArchStr.substr(7); - Triples += "-"; - break; - } - } - Triples += GPUArchName.str(); + if (OffloadKind == Action::OFK_OpenMP && + !Dep.DependentToolChain->getTargetID().empty()) { + Triples += '-'; + Triples += Dep.DependentToolChain->getTargetID(); } } @@ -8941,7 +9122,7 @@ void OffloadBundler::ConstructJobMultipleOutputs( C.addCommand(std::make_unique( JA, *this, ResponseFileSupport::None(), TCArgs.MakeArgString(getToolChain().GetProgramPath(getShortName())), - CmdArgs, ArrayRef(), Outputs)); + CmdArgs, Inputs, Outputs)); } void OffloadPackager::ConstructJob(Compilation &C, const JobAction &JA, @@ -8972,8 +9153,8 @@ void OffloadPackager::ConstructJob(Compilation &C, const JobAction &JA, ArgStringList Features; SmallVector FeatureArgs; - getTargetFeatures(TC->getDriver(), TC->getTriple(), TCArgs, Features, - false); + getTargetFeatures(TC->getDriver(), TC->getTriple(), TCArgs, Features, false, + false, Arch); llvm::copy_if(Features, std::back_inserter(FeatureArgs), [](StringRef Arg) { return !Arg.starts_with("-target"); }); @@ -9004,6 +9185,24 @@ void LinkerWrapper::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { + bool isAMDGPU = false; + auto offloadTC = C.getOffloadToolChains(Action::OFK_OpenMP); + const auto OpenMPTCs = llvm::make_range(offloadTC.first, offloadTC.second); + const ToolChain *OTC; + for (auto &I : OpenMPTCs) { + OTC = I.second; + if (OTC->getTriple().isAMDGPU()) { + isAMDGPU = true; + break; + } + } + if (isAMDGPU && Args.hasFlag(options::OPT_opaque_offload_linker, + options::OPT_no_opaque_offload_linker, false)) { + ConstructOpaqueJob(C, JA, Output, Inputs, Args, OTC->getTriple(), + LinkingOutput); + return; + } + using namespace options; // A list of permitted options that will be forwarded to the embedded device @@ -9077,6 +9276,28 @@ void LinkerWrapper::ConstructJob(Compilation &C, const JobAction &JA, A->render(Args, LinkerArgs); } + if (isAMDGPU && !C.getDriver().IsFlangMode()) { + StringRef OOpt; + if (const Arg *A = Args.getLastArg(options::OPT_O_Group)) { + if (A->getOption().matches(options::OPT_O4) || + A->getOption().matches(options::OPT_Ofast)) + OOpt = "3"; + else if (A->getOption().matches(options::OPT_O)) { + OOpt = A->getValue(); + if (OOpt == "g") + OOpt = "1"; + else if (OOpt == "s" || OOpt == "z") + OOpt = "2"; + } else if (A->getOption().matches(options::OPT_O0)) + OOpt = "0"; + } + + if (!OOpt.empty() && OOpt != "0") { + LinkerArgs.push_back(Args.MakeArgString( + "--lto-newpm-passes=default-post-link")); + } + } + // If the user explicitly requested it via `--offload-arch` we should // extract it from any static libraries if present. for (StringRef Arg : ToolChainArgs.getAllArgValues(OPT_offload_arch_EQ)) diff --git a/clang/lib/Driver/ToolChains/Clang.h b/clang/lib/Driver/ToolChains/Clang.h index 9adad5c5430f2..60512ae8e03e7 100644 --- a/clang/lib/Driver/ToolChains/Clang.h +++ b/clang/lib/Driver/ToolChains/Clang.h @@ -185,6 +185,11 @@ class LLVM_LIBRARY_VISIBILITY LinkerWrapper final : public Tool { const InputInfo &Output, const InputInfoList &Inputs, const llvm::opt::ArgList &TCArgs, const char *LinkingOutput) const override; + void ConstructOpaqueJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, const InputInfoList &Inputs, + const llvm::opt::ArgList &TCArgs, + const llvm::Triple &TheTriple, + const char *LinkingOutput) const; }; // Calculate the output path of the module file when compiling a module unit diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index ec8dcdc81db56..52e43d1a003eb 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -44,12 +44,14 @@ #include "llvm/ADT/Twine.h" #include "llvm/BinaryFormat/Magic.h" #include "llvm/Config/llvm-config.h" +#include "llvm/Object/Archive.h" #include "llvm/Option/Arg.h" #include "llvm/Option/ArgList.h" #include "llvm/Option/Option.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/Compression.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/ErrorOr.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Path.h" #include "llvm/Support/Process.h" @@ -67,6 +69,23 @@ using namespace clang::driver::tools; using namespace clang; using namespace llvm::opt; +static bool addRPathCmdArg(const llvm::opt::ArgList &Args, + ArgStringList &CmdArgs, + const std::string pathCandidate, + bool onlyIfPathExists = true) { + SmallString<0> simplifiedPathCandidate(pathCandidate); + llvm::sys::path::remove_dots(simplifiedPathCandidate, true); + + bool pathExists = llvm::sys::fs::exists(simplifiedPathCandidate); + + if (onlyIfPathExists && !pathExists) + return false; + + CmdArgs.push_back("-rpath"); + CmdArgs.push_back(Args.MakeArgString(simplifiedPathCandidate)); + return pathExists; +} + static bool useFramePointerForTargetByDefault(const llvm::opt::ArgList &Args, const llvm::Triple &Triple) { if (Args.hasArg(clang::driver::options::OPT_pg) && @@ -660,7 +679,12 @@ void tools::AddTargetFeature(const ArgList &Args, static std::string getAMDGPUTargetGPU(const llvm::Triple &T, const ArgList &Args) { Arg *MArch = Args.getLastArg(options::OPT_march_EQ); - if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) { + Arg *A = Args.getLastArg(options::OPT_mcpu_EQ); + if (!A) + A = Args.getLastArg(options::OPT_march_EQ); + if (!A) + A = Args.getLastArg(options::OPT_offload_arch_EQ); + if (A) { auto GPUName = getProcessorFromTargetID(T, A->getValue()); return llvm::StringSwitch(GPUName) .Cases({"rv630", "rv635"}, "r600") @@ -823,7 +847,8 @@ static void getWebAssemblyTargetFeatures(const Driver &D, void tools::getTargetFeatures(const Driver &D, const llvm::Triple &Triple, const ArgList &Args, ArgStringList &CmdArgs, - bool ForAS, bool IsAux) { + bool ForAS, bool IsAux, + const StringRef TcTargetID) { std::vector Features; switch (Triple.getArch()) { default: @@ -876,7 +901,7 @@ void tools::getTargetFeatures(const Driver &D, const llvm::Triple &Triple, break; case llvm::Triple::r600: case llvm::Triple::amdgcn: - amdgpu::getAMDGPUTargetFeatures(D, Triple, Args, Features); + amdgpu::getAMDGPUTargetFeatures(D, Triple, Args, Features, TcTargetID); break; case llvm::Triple::nvptx: case llvm::Triple::nvptx64: @@ -976,6 +1001,7 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, StringRef Linker = Args.getLastArgValue(options::OPT_fuse_ld_EQ); const char *LinkerPath = Args.MakeArgString(ToolChain.GetLinkerPath()); const Driver &D = ToolChain.getDriver(); + const bool IsFatLTO = Args.hasFlag(options::OPT_ffat_lto_objects, options::OPT_fno_fat_lto_objects, false); const bool IsUnifiedLTO = Args.hasArg(options::OPT_funified_lto); @@ -1371,6 +1397,69 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, addDTLTOOptions(ToolChain, Args, CmdArgs); } +void tools::addOpenMPRuntimeSpecificRPath(const ToolChain &TC, + const ArgList &Args, + ArgStringList &CmdArgs) { + const Driver &D = TC.getDriver(); + std::string LibSuffix = "lib"; + if (TC.getSanitizerArgs(Args).needsAsanRt()) + LibSuffix.append("/asan"); + if (Arg *A = Args.getLastArg(options::OPT_fopenmp_runtimelib_EQ)) { + LibSuffix = A->getValue(); + if (LibSuffix != "lib-perf" && LibSuffix != "lib-debug" && LibSuffix != "lib") + D.Diag(diag::err_drv_unsupported_option_argument) + << A->getSpelling() << LibSuffix; + if (TC.getSanitizerArgs(Args).needsAsanRt()) + LibSuffix.append("/asan"); + } + + // Check if the device library can be found in + // one of the LIBRARY_PATH directories. + ArgStringList EnvLibraryPaths; + addDirectoryList(Args, EnvLibraryPaths, "", "LIBRARY_PATH"); + for (auto &EnvLibraryPath : EnvLibraryPaths) + addRPathCmdArg(Args, CmdArgs, EnvLibraryPath); + + if (Args.hasFlag(options::OPT_fopenmp_implicit_rpath, + options::OPT_fno_openmp_implicit_rpath, true)) { + // Default to clang lib / lib64 folder, i.e. the same location as device + // runtime + SmallString<256> DefaultLibPath = + llvm::sys::path::parent_path(TC.getDriver().Dir); + llvm::sys::path::append(DefaultLibPath, CLANG_INSTALL_LIBDIR_BASENAME); + if (TC.getSanitizerArgs(Args).needsAsanRt()) + addRPathCmdArg(Args, CmdArgs, TC.getCompilerRTPath(), + /*onlyIfPathExists=*/false); + + // In case LibSuffix was not built, try lib + std::string CandidateRPath_suf = D.Dir + "/../" + LibSuffix; + // Add lib directory in case LibSuffix does not exist + std::string CandidateRPath_lib = D.Dir + "/../lib"; + if (!addRPathCmdArg(Args, CmdArgs, CandidateRPath_suf, + /*onlyIfPathExists=*/false)) + addRPathCmdArg(Args, CmdArgs, CandidateRPath_lib); + + std::string rocmPath = + Args.getLastArgValue(clang::driver::options::OPT_rocm_path_EQ).str(); + if (rocmPath.size() != 0) { + std::string rocmPath_lib = rocmPath + "/lib"; + std::string rocmPath_suf = rocmPath + "/" + LibSuffix; + if (!addRPathCmdArg(Args, CmdArgs, rocmPath_suf)) + addRPathCmdArg(Args, CmdArgs, rocmPath_lib); + } + + // Add Default lib path to ensure llvm dynamic library is picked up for + // lib-debug/lib-perf + if (LibSuffix != "lib") + addRPathCmdArg(Args, CmdArgs, DefaultLibPath.c_str()); + + if (llvm::find_if(CmdArgs, [](StringRef str) { + return !str.compare("--enable-new-dtags"); + }) == CmdArgs.end()) + CmdArgs.push_back("--disable-new-dtags"); + } +} + void tools::addOpenMPRuntimeLibraryPath(const ToolChain &TC, const ArgList &Args, ArgStringList &CmdArgs) { @@ -1379,7 +1468,15 @@ void tools::addOpenMPRuntimeLibraryPath(const ToolChain &TC, SmallString<256> DefaultLibPath = llvm::sys::path::parent_path(TC.getDriver().Dir); llvm::sys::path::append(DefaultLibPath, CLANG_INSTALL_LIBDIR_BASENAME); - CmdArgs.push_back(Args.MakeArgString("-L" + DefaultLibPath)); + if (TC.getSanitizerArgs(Args).needsAsanRt()) { + SmallString<256> ASanLibPath[2]; + ASanLibPath[0].assign((DefaultLibPath + "/../../asan").str()); + ASanLibPath[1].assign((DefaultLibPath + "/asan").str()); + for (auto Path : ASanLibPath) + if (llvm::sys::fs::exists(Path)) + CmdArgs.push_back(Args.MakeArgString("-L" + Path)); + } else + CmdArgs.push_back(Args.MakeArgString("-L" + DefaultLibPath)); } void tools::addArchSpecificRPath(const ToolChain &TC, const ArgList &Args, @@ -1396,11 +1493,38 @@ void tools::addArchSpecificRPath(const ToolChain &TC, const ArgList &Args, CandidateRPaths.emplace_back(*CandidateRPath); for (const auto &CandidateRPath : CandidateRPaths) { - if (TC.getVFS().exists(CandidateRPath)) { - CmdArgs.push_back("-rpath"); - CmdArgs.push_back(Args.MakeArgString(CandidateRPath)); + if (TC.getVFS().exists(CandidateRPath)) + addRPathCmdArg(Args, CmdArgs, CandidateRPath, /*onlyIfPathExists=*/false); + } +} + +bool requiresCOMGrLinking(const ToolChain &TC, const ArgList &Args) { + std::vector extractValues = + Args.getAllArgValues(options::OPT_Xopenmp_target_EQ); + std::vector::iterator itr; + if (!extractValues.empty()) { + itr = extractValues.begin(); + while ((itr = std::find(itr, extractValues.end(), "amdgcn-amd-amdhsa")) != + extractValues.end()) { + StringRef archVal(*(itr + 1)); + if (archVal.contains("xnack+") && TC.getSanitizerArgs(Args).needsAsanRt()) + return true; + itr += 2; + } + } else { + std::string tgtArch = + getAMDGPUTargetGPU(llvm::Triple("amdgcn-amd-amdhsa"), Args); + extractValues = Args.getAllArgValues(options::OPT_offload_arch_EQ); + itr = extractValues.begin(); + while (itr != extractValues.end()) { + StringRef archVal(*itr); + if (!tgtArch.empty() && archVal.contains("xnack+") && + TC.getSanitizerArgs(Args).needsAsanRt()) + return true; + itr++; } } + return false; } bool tools::addOpenMPRuntime(const Compilation &C, ArgStringList &CmdArgs, @@ -1435,6 +1559,9 @@ bool tools::addOpenMPRuntime(const Compilation &C, ArgStringList &CmdArgs, case Driver::OMPRT_IOMP5: CmdArgs.push_back("-liomp5"); break; + case Driver::OMPRT_BOLT: + CmdArgs.push_back("-lbolt"); + break; case Driver::OMPRT_Unknown: break; } @@ -1445,11 +1572,20 @@ bool tools::addOpenMPRuntime(const Compilation &C, ArgStringList &CmdArgs, if (RTKind == Driver::OMPRT_GOMP && GompNeedsRT) CmdArgs.push_back("-lrt"); - if (IsOffloadingHost) + if (RTKind == Driver::OMPRT_BOLT) + CmdArgs.push_back("-lbolt"); + + if (IsOffloadingHost) { + if (requiresCOMGrLinking(TC, Args)) { + CmdArgs.push_back("-lamd_comgr"); + } CmdArgs.push_back("-lomptarget"); + } addArchSpecificRPath(TC, Args, CmdArgs); + if (RTKind == Driver::OMPRT_OMP || RTKind == Driver::OMPRT_BOLT) + addOpenMPRuntimeSpecificRPath(TC, Args, CmdArgs); addOpenMPRuntimeLibraryPath(TC, Args, CmdArgs); return true; @@ -2009,6 +2145,10 @@ tools::ParsePICArgs(const ToolChain &ToolChain, const ArgList &Args) { } } + // AMDGPU-specific defaults for PIC. + if (Triple.isAMDGCN()) + PIC = true; + // The last argument relating to either PIC or PIE wins, and no // other argument is used. If the last argument is any flavor of the // '-fno-...' arguments, both PIC and PIE are disabled. Any PIE @@ -2586,8 +2726,8 @@ void tools::addX86AlignBranchArgs(const Driver &D, const ArgList &Args, static bool SDLSearch(const Driver &D, const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, const SmallVectorImpl &LibraryPaths, - StringRef Lib, StringRef Arch, StringRef Target, - bool isBitCodeSDL) { + StringRef Lib, StringRef Arch, StringRef TargetID, + bool isBitCodeSDL, bool postClangLink) { SmallVector SDLs; std::string LibDeviceLoc = "/libdevice"; @@ -2612,7 +2752,7 @@ static bool SDLSearch(const Driver &D, const llvm::opt::ArgList &DriverArgs, for (StringRef Base : {LibBcPrefix, LibPrefix}) { const auto *Ext = Base.contains(LibBcPrefix) ? ".a" : ".bc"; - for (auto Suffix : {Twine(Lib + "-" + Arch + "-" + Target).str(), + for (auto Suffix : {Twine(Lib + "-" + Arch + "-" + TargetID).str(), Twine(Lib + "-" + Arch).str(), Twine(Lib).str()}) { SDLs.push_back(Twine(LibDeviceLoc + Base + Suffix + Ext).str()); SDLs.push_back(Twine(Base + Suffix + Ext).str()); @@ -2627,7 +2767,7 @@ static bool SDLSearch(const Driver &D, const llvm::opt::ArgList &DriverArgs, const auto *Ext = ".a"; - for (auto Suffix : {Twine(Lib + "-" + Arch + "-" + Target).str(), + for (auto Suffix : {Twine(Lib + "-" + Arch + "-" + TargetID).str(), Twine(Lib + "-" + Arch).str()}) { SDLs.push_back(Twine(LibDeviceLoc + LibPrefix + Suffix + Ext).str()); SDLs.push_back(Twine(LibPrefix + Suffix + Ext).str()); @@ -2646,6 +2786,8 @@ static bool SDLSearch(const Driver &D, const llvm::opt::ArgList &DriverArgs, for (auto SDL : SDLs) { auto FullName = Twine(LPath + SDL).str(); if (llvm::sys::fs::exists(FullName)) { + if (postClangLink) + CC1Args.push_back("-mlink-builtin-bitcode"); CC1Args.push_back(DriverArgs.MakeArgString(FullName)); FoundSDL = true; break; @@ -2666,7 +2808,8 @@ static void GetSDLFromOffloadArchive( const InputInfoList &Inputs, const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, const SmallVectorImpl &LibraryPaths, StringRef Lib, - StringRef Arch, StringRef Target, bool isBitCodeSDL) { + StringRef Arch, StringRef Target, bool isBitCodeSDL, + bool postClangLink, bool unpackage) { // We don't support bitcode archive bundles for nvptx if (isBitCodeSDL && Arch.contains("nvptx")) @@ -2680,7 +2823,7 @@ static void GetSDLFromOffloadArchive( auto Ext = IsMSVC ? ".lib" : ".a"; if (!Lib.starts_with(":") && !Lib.starts_with("-l")) { if (llvm::sys::fs::exists(Lib)) { - ArchiveOfBundles = Lib; + ArchiveOfBundles = Lib.str(); FoundAOB = true; } } else { @@ -2712,6 +2855,31 @@ static void GetSDLFromOffloadArchive( if (EC || Magic != llvm::file_magic::archive) return; + if (unpackage) { + std::string OutputLib = + D.GetTemporaryPath(Twine("lib" + llvm::sys::path::filename(Lib) + "-" + + Arch + "-" + Target) + .str(), + "a"); + + ArgStringList UPArgs; + const char *UPProgram = DriverArgs.MakeArgString( + T.getToolChain().GetProgramPath("clang-offload-packager")); + UPArgs.push_back(C.getArgs().MakeArgString(ArchiveOfBundles.c_str())); + UPArgs.push_back(C.getArgs().MakeArgString("--archive")); + std::string OutputArg("--image=file=" + OutputLib + + ",triple=amdgcn-amd-amdhsa,arch=" + Target.str() + + ",kind=openmp"); + UPArgs.push_back(C.getArgs().MakeArgString(OutputArg)); + + C.addCommand(std::make_unique( + JA, T, ResponseFileSupport::AtFileCurCP(), UPProgram, UPArgs, Inputs, + InputInfo(&JA, C.getArgs().MakeArgString(OutputLib)))); + + CC1Args.push_back(DriverArgs.MakeArgString(OutputLib)); + return; + } + StringRef Prefix = isBitCodeSDL ? "libbc-" : "lib"; std::string OutputLib = D.GetTemporaryPath(Twine(Prefix + llvm::sys::path::filename(Lib) + "-" + @@ -2766,16 +2934,39 @@ static void GetSDLFromOffloadArchive( CC1Args.push_back(DriverArgs.MakeArgString(OutputLib)); } +// Wrapper function used by opaque-offload-linker for adding SDLs +// during link phase. +void tools::AddStaticDeviceLibsLinking( + Compilation &C, const Tool &T, const JobAction &JA, + const InputInfoList &Inputs, const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args, StringRef Arch, StringRef TargetID, + bool isBitCodeSDL, bool postClangLink, bool unpackage) { + AddStaticDeviceLibs(&C, &T, &JA, &Inputs, C.getDriver(), DriverArgs, CC1Args, + Arch, TargetID, isBitCodeSDL, postClangLink, unpackage); +} + // Wrapper function used by driver for adding SDLs during link phase. void tools::AddStaticDeviceLibsLinking(Compilation &C, const Tool &T, const JobAction &JA, const InputInfoList &Inputs, const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, - StringRef Arch, StringRef Target, - bool isBitCodeSDL) { + StringRef Arch, StringRef TargetID, + bool isBitCodeSDL, bool postClangLink) { AddStaticDeviceLibs(&C, &T, &JA, &Inputs, C.getDriver(), DriverArgs, CC1Args, - Arch, Target, isBitCodeSDL); + Arch, TargetID, isBitCodeSDL, postClangLink); +} + +// Wrapper function used for post clang linking of bitcode SDLS for nvptx by +// the CUDA toolchain. +void tools::AddStaticDeviceLibsPostLinking(const Driver &D, + const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args, + StringRef Arch, StringRef TargetID, + bool isBitCodeSDL, + bool postClangLink) { + AddStaticDeviceLibs(nullptr, nullptr, nullptr, nullptr, D, DriverArgs, + CC1Args, Arch, TargetID, isBitCodeSDL, postClangLink); } // User defined Static Device Libraries(SDLs) can be passed to clang for @@ -2807,7 +2998,8 @@ void tools::AddStaticDeviceLibs(Compilation *C, const Tool *T, const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, StringRef Arch, StringRef Target, - bool isBitCodeSDL) { + bool isBitCodeSDL, bool postClangLink, + bool unpackage) { SmallVector LibraryPaths; // Add search directories from LIBRARY_PATH env variable @@ -2825,7 +3017,7 @@ void tools::AddStaticDeviceLibs(Compilation *C, const Tool *T, for (std::string Search_Dir : DriverArgs.getAllArgValues(options::OPT_L)) LibraryPaths.emplace_back(Search_Dir); - // Add path to lib-debug folders + // Add path to lib* folders SmallString<256> DefaultLibPath = llvm::sys::path::parent_path(D.Dir); llvm::sys::path::append(DefaultLibPath, CLANG_INSTALL_LIBDIR_BASENAME); LibraryPaths.emplace_back(DefaultLibPath.c_str()); @@ -2863,10 +3055,10 @@ void tools::AddStaticDeviceLibs(Compilation *C, const Tool *T, for (auto SDLName : SDLNames) { // This is the only call to SDLSearch if (!SDLSearch(D, DriverArgs, CC1Args, LibraryPaths, SDLName, Arch, Target, - isBitCodeSDL)) { + isBitCodeSDL, postClangLink) && !postClangLink) { GetSDLFromOffloadArchive(*C, D, *T, *JA, *Inputs, DriverArgs, CC1Args, LibraryPaths, SDLName, Arch, Target, - isBitCodeSDL); + isBitCodeSDL, postClangLink, unpackage); } } } @@ -2902,6 +3094,13 @@ unsigned tools::getAMDGPUCodeObjectVersion(const Driver &D, return CodeObjVer; } +unsigned tools::getOrCheckAMDGPUCodeObjectVersion( + const Driver &D, const llvm::opt::ArgList &Args, bool Diagnose) { + if (Diagnose) + checkAMDGPUCodeObjectVersion(D, Args); + return getAMDGPUCodeObjectVersion(D, Args); +} + bool tools::haveAMDGPUCodeObjectVersionArgument( const Driver &D, const llvm::opt::ArgList &Args) { return getAMDGPUCodeObjectArgument(D, Args) != nullptr; @@ -2992,6 +3191,7 @@ void tools::addOpenMPDeviceRTL(const Driver &D, : Triple.isNVPTX() ? options::OPT_libomptarget_nvptx_bc_path_EQ : options::OPT_libomptarget_spirv_bc_path_EQ; + StringRef ArchPrefix = Triple.isAMDGCN() ? "amdgpu" : Triple.isNVPTX() ? "nvptx" : "spirv"; diff --git a/clang/lib/Driver/ToolChains/Cuda.cpp b/clang/lib/Driver/ToolChains/Cuda.cpp index 07201cc4676ac..8fc1bded2acea 100644 --- a/clang/lib/Driver/ToolChains/Cuda.cpp +++ b/clang/lib/Driver/ToolChains/Cuda.cpp @@ -8,6 +8,7 @@ #include "Cuda.h" #include "clang/Basic/Cuda.h" +#include "clang/Basic/TargetID.h" #include "clang/Config/config.h" #include "clang/Driver/CommonArgs.h" #include "clang/Driver/Compilation.h" @@ -399,6 +400,9 @@ void NVPTX::Assembler::ConstructJob(Compilation &C, const JobAction &JA, GPUArchName = JA.getOffloadingArch(); } else { GPUArchName = Args.getLastArgValue(options::OPT_march_EQ); + if (GPUArchName.empty()) + GPUArchName = getProcessorFromTargetID(TC.getTriple(), TC.getTargetID()); + if (GPUArchName.empty()) { C.getDriver().Diag(diag::err_drv_offload_missing_gpu_arch) << getToolChain().getArchName() << getShortName(); @@ -596,6 +600,10 @@ void NVPTX::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-v"); StringRef GPUArch = Args.getLastArgValue(options::OPT_march_EQ); + if (GPUArch.empty()) + GPUArch = getProcessorFromTargetID(getToolChain().getTriple(), + getToolChain().getTargetID()); + if (GPUArch.empty() && !C.getDriver().isUsingLTO()) { C.getDriver().Diag(diag::err_drv_offload_missing_gpu_arch) << getToolChain().getArchName() << getShortName(); @@ -845,6 +853,11 @@ NVPTXToolChain::getSystemGPUArchs(const ArgList &Args) const { /// which isn't properly a linker but nonetheless performs the step of stitching /// together object files from the assembler into a single blob. +CudaToolChain::CudaToolChain(const Driver &D, const llvm::Triple &Triple, + const ToolChain &HostTC, const ArgList &Args, + const std::string TargetID) + : NVPTXToolChain(D, Triple, HostTC.getTriple(), Args), HostTC(HostTC) {} + CudaToolChain::CudaToolChain(const Driver &D, const llvm::Triple &Triple, const ToolChain &HostTC, const ArgList &Args) : NVPTXToolChain(D, Triple, HostTC.getTriple(), Args), HostTC(HostTC) {} @@ -919,6 +932,9 @@ void CudaToolChain::addClangTargetOptions( addOpenMPDeviceRTL(getDriver(), DriverArgs, CC1Args, GpuArch.str(), getTriple(), HostTC); + AddStaticDeviceLibsPostLinking(getDriver(), DriverArgs, CC1Args, "nvptx", + GpuArch, /*isBitCodeSDL=*/true, + /*postClangLink=*/true); } } diff --git a/clang/lib/Driver/ToolChains/Cuda.h b/clang/lib/Driver/ToolChains/Cuda.h index 6193328908828..5aa95cf4c5a63 100644 --- a/clang/lib/Driver/ToolChains/Cuda.h +++ b/clang/lib/Driver/ToolChains/Cuda.h @@ -1,3 +1,4 @@ + //===--- Cuda.h - Cuda ToolChain Implementations ----------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. @@ -5,10 +6,8 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// - #ifndef LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_CUDA_H #define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_CUDA_H - #include "clang/Basic/Cuda.h" #include "clang/Driver/Action.h" #include "clang/Driver/CudaInstallationDetector.h" @@ -20,61 +19,58 @@ #include #include #include - namespace clang { namespace driver { namespace tools { namespace NVPTX { - // Run ptxas, the NVPTX assembler. class LLVM_LIBRARY_VISIBILITY Assembler final : public Tool { public: Assembler(const ToolChain &TC) : Tool("NVPTX::Assembler", "ptxas", TC) {} - bool hasIntegratedCPP() const override { return false; } - void ConstructJob(Compilation &C, const JobAction &JA, const InputInfo &Output, const InputInfoList &Inputs, const llvm::opt::ArgList &TCArgs, const char *LinkingOutput) const override; }; - // Runs fatbinary, which combines GPU object files ("cubin" files) and/or PTX // assembly into a single output file. class LLVM_LIBRARY_VISIBILITY FatBinary : public Tool { public: FatBinary(const ToolChain &TC) : Tool("NVPTX::Linker", "fatbinary", TC) {} - bool hasIntegratedCPP() const override { return false; } - void ConstructJob(Compilation &C, const JobAction &JA, const InputInfo &Output, const InputInfoList &Inputs, const llvm::opt::ArgList &TCArgs, const char *LinkingOutput) const override; }; - // Runs nvlink, which links GPU object files ("cubin" files) into a single file. class LLVM_LIBRARY_VISIBILITY Linker final : public Tool { public: Linker(const ToolChain &TC) : Tool("NVPTX::Linker", "nvlink", TC) {} bool hasIntegratedCPP() const override { return false; } - void ConstructJob(Compilation &C, const JobAction &JA, const InputInfo &Output, const InputInfoList &Inputs, const llvm::opt::ArgList &TCArgs, const char *LinkingOutput) const override; }; - +class LLVM_LIBRARY_VISIBILITY OpenMPLinker : public Tool { + public: + OpenMPLinker(const ToolChain &TC) + : Tool("NVPTX::OpenMPLinker", "nvlink", TC) {} + bool hasIntegratedCPP() const override { return false; } + void ConstructJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, const InputInfoList &Inputs, + const llvm::opt::ArgList &TCArgs, + const char *LinkingOutput) const override; +}; void getNVPTXTargetFeatures(const Driver &D, const llvm::Triple &Triple, const llvm::opt::ArgList &Args, std::vector &Features); - } // end namespace NVPTX } // end namespace tools - namespace toolchains { - class LLVM_LIBRARY_VISIBILITY NVPTXToolChain : public ToolChain { public: NVPTXToolChain(const Driver &D, const llvm::Triple &Triple, @@ -83,7 +79,6 @@ class LLVM_LIBRARY_VISIBILITY NVPTXToolChain : public ToolChain { NVPTXToolChain(const Driver &D, const llvm::Triple &Triple, const llvm::opt::ArgList &Args); - llvm::opt::DerivedArgList * TranslateArgs(const llvm::opt::DerivedArgList &Args, StringRef BoundArch, Action::OffloadKind DeviceOffloadKind) const override; @@ -107,13 +102,10 @@ class LLVM_LIBRARY_VISIBILITY NVPTXToolChain : public ToolChain { bool HasNativeLLVMSupport() const override { return true; } bool isPICDefaultForced() const override { return false; } bool SupportsProfiling() const override { return false; } - bool IsMathErrnoDefault() const override { return false; } - bool supportsDebugInfoOption(const llvm::opt::Arg *A) const override; void adjustDebugInfoKind(llvm::codegenoptions::DebugInfoKind &DebugInfoKind, const llvm::opt::ArgList &Args) const override; - // NVPTX supports only DWARF2. unsigned GetDefaultDwarfVersion() const override { return 2; } unsigned getMaxDwarfVersion() const override { return 2; } @@ -124,7 +116,6 @@ class LLVM_LIBRARY_VISIBILITY NVPTXToolChain : public ToolChain { getSystemGPUArchs(const llvm::opt::ArgList &Args) const override; CudaInstallationDetector CudaInstallation; - protected: Tool *buildAssembler() const override; // ptxas. Tool *buildLinker() const override; // nvlink. @@ -134,7 +125,9 @@ class LLVM_LIBRARY_VISIBILITY CudaToolChain : public NVPTXToolChain { public: CudaToolChain(const Driver &D, const llvm::Triple &Triple, const ToolChain &HostTC, const llvm::opt::ArgList &Args); - + CudaToolChain(const Driver &D, const llvm::Triple &Triple, + const ToolChain &HostTC, const llvm::opt::ArgList &Args, + const std::string TargetID); const llvm::Triple *getAuxTriple() const override { return &HostTC.getTriple(); } @@ -142,7 +135,6 @@ class LLVM_LIBRARY_VISIBILITY CudaToolChain : public NVPTXToolChain { bool HasNativeLLVMSupport() const override { return false; } std::string getInputFilename(const InputInfo &Input) const override; - llvm::opt::DerivedArgList * TranslateArgs(const llvm::opt::DerivedArgList &Args, StringRef BoundArch, Action::OffloadKind DeviceOffloadKind) const override; @@ -150,14 +142,11 @@ class LLVM_LIBRARY_VISIBILITY CudaToolChain : public NVPTXToolChain { addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, Action::OffloadKind DeviceOffloadKind) const override; - llvm::DenormalMode getDefaultDenormalModeForType( const llvm::opt::ArgList &DriverArgs, const JobAction &JA, const llvm::fltSemantics *FPType = nullptr) const override; - void AddCudaIncludeArgs(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const override; - void addClangWarningOptions(llvm::opt::ArgStringList &CC1Args) const override; CXXStdlibType GetCXXStdlibType(const llvm::opt::ArgList &Args) const override; void @@ -168,9 +157,7 @@ class LLVM_LIBRARY_VISIBILITY CudaToolChain : public NVPTXToolChain { llvm::opt::ArgStringList &CC1Args) const override; void AddIAMCUIncludeArgs(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const override; - SanitizerMask getSupportedSanitizers() const override; - VersionTuple computeMSVCVersion(const Driver *D, const llvm::opt::ArgList &Args) const override; @@ -181,9 +168,7 @@ class LLVM_LIBRARY_VISIBILITY CudaToolChain : public NVPTXToolChain { Tool *buildAssembler() const override; // ptxas Tool *buildLinker() const override; // fatbinary (ok, not really a linker) }; - } // end namespace toolchains } // end namespace driver } // end namespace clang - #endif // LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_CUDA_H diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 88bce181d40d2..f24dd3982eab7 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -131,9 +131,16 @@ void Flang::addDebugOptions(const llvm::opt::ArgList &Args, const JobAction &JA, options::OPT_std_EQ, options::OPT_W_Joined, options::OPT_fconvert_EQ, options::OPT_fpass_plugin_EQ, options::OPT_funderscoring, options::OPT_fno_underscoring, + options::OPT_foffload_global_filtering, + options::OPT_fno_offload_global_filtering, options::OPT_funsigned, options::OPT_fno_unsigned, options::OPT_finstrument_functions}); + if (Args.hasArg(options::OPT_fopenacc)) { + const Driver &D = getToolChain().getDriver(); + D.Diag(diag::warn_openacc_experimental); + } + llvm::codegenoptions::DebugInfoKind DebugInfoKind; bool hasDwarfNArg = getDwarfNArg(Args) != nullptr; if (Args.hasArg(options::OPT_gN_Group)) { @@ -229,7 +236,8 @@ void Flang::addCodegenOptions(const ArgList &Args, options::OPT_frepack_arrays_contiguity_EQ, options::OPT_fstack_repack_arrays, options::OPT_fno_stack_repack_arrays, options::OPT_ftime_report, options::OPT_ftime_report_EQ, - options::OPT_funroll_loops, options::OPT_fno_unroll_loops}); + options::OPT_funroll_loops, options::OPT_fno_unroll_loops, + options::OPT_fdefer_desc_map, options::OPT_fno_defer_desc_map}); if (Args.hasArg(clang::driver::options::OPT_fcoarray)) CmdArgs.push_back("-fcoarray"); } @@ -962,6 +970,12 @@ void Flang::ConstructJob(Compilation &C, const JobAction &JA, addFortranDialectOptions(Args, CmdArgs); + if (Args.hasArg(options::OPT_ffast_amd_memory_allocator)) { + CmdArgs.push_back("-ffast-amd-memory-allocator"); + CmdArgs.push_back("-mmlir"); + CmdArgs.push_back("-use-alloc-runtime"); + } + // 'flang -E' always produces output that is suitable for use as fixed form // Fortran. However it is only valid free form source if the original is also // free form. Ensure this logic does not incorrectly assume fixed-form for @@ -1050,6 +1064,9 @@ void Flang::ConstructJob(Compilation &C, const JobAction &JA, options::OPT_fno_openmp_simd); } + if (Args.hasArg(options::OPT_famd_allow_threadprivate_equivalence)) + CmdArgs.push_back("-famd-allow-threadprivate-equivalence"); + // Pass the path to compiler resource files. CmdArgs.push_back("-resource-dir"); CmdArgs.push_back(D.ResourceDir.c_str()); diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index 7616076847a2c..07df986463690 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -29,6 +29,7 @@ #include "llvm/Support/CodeGen.h" #include "llvm/Support/Path.h" #include "llvm/Support/VirtualFileSystem.h" +#include "llvm/TargetParser/Host.h" #include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/TargetParser.h" #include @@ -435,6 +436,13 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, const JobAction &JA, Args.MakeArgString(ToolChain.GetFilePath("crt_pad_segment.o"))); } + // Make sure openmp finds it libomp.so before all others. + if (Args.hasArg(options::OPT_fopenmp) || + JA.isHostOffloading(Action::OFK_OpenMP)) { + addDirectoryList(Args, CmdArgs, "-L", "LIBRARY_PATH"); + CmdArgs.push_back(Args.MakeArgString("-L" + D.Dir + "/../lib")); + } + Args.addAllArgs(CmdArgs, {options::OPT_L, options::OPT_u}); ToolChain.AddFilePathLibArgs(Args, CmdArgs); @@ -582,6 +590,44 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, const JobAction &JA, Args.addAllArgs(CmdArgs, {options::OPT_T, options::OPT_t}); const char *Exec = Args.MakeArgString(ToolChain.GetLinkerPath()); + + // Check if linker has a corresponding LLVM IR assembler. If so, disassemble + // bitcode using current disassembler and then use assembler from linker's + // release to mask potential bitcode incompatibilities from different LLVM + // versions or releases. This fixes things like differences in number of + // integer attributes or anything where bitcodes may not match. + if (D.isUsingLTO()) { + StringRef execSR(Exec); + std::string as_fn = + execSR.substr(0, execSR.find_last_of("/") + 1).str() + "llvm-as"; + for (auto i : Inputs) { + if (llvm::sys::fs::exists(as_fn) && i.isFilename() && + (i.getType() == clang::driver::types::TY_LTO_BC)) { + ArgStringList dis_args; + dis_args.push_back(C.getArgs().MakeArgString(i.getFilename())); + dis_args.push_back("-o"); + std::string TmpNameDisOutput = + C.getDriver().GetTemporaryPath("disassembled", "ll"); + C.addTempFile(C.getArgs().MakeArgString(TmpNameDisOutput)); + const char *DisOutputFn = C.getArgs().MakeArgString(TmpNameDisOutput); + dis_args.push_back(DisOutputFn); + InputInfo DisII(&JA, DisOutputFn); + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::None(), + C.getArgs().MakeArgString( + getToolChain().GetProgramPath("llvm-dis")), + dis_args, i, DisII)); + ArgStringList as_args; + as_args.push_back(DisOutputFn); + as_args.push_back("-o"); + as_args.push_back(C.getArgs().MakeArgString(i.getFilename())); + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::None(), + C.getArgs().MakeArgString(as_fn), as_args, DisII, i)); + } + } + } + C.addCommand(std::make_unique(JA, *this, ResponseFileSupport::AtFileCurCP(), Exec, CmdArgs, Inputs, Output)); diff --git a/clang/lib/Driver/ToolChains/HIPAMD.cpp b/clang/lib/Driver/ToolChains/HIPAMD.cpp index c0c8afec07264..d0d2d2e34b602 100644 --- a/clang/lib/Driver/ToolChains/HIPAMD.cpp +++ b/clang/lib/Driver/ToolChains/HIPAMD.cpp @@ -52,7 +52,9 @@ void AMDGCN::Linker::constructLlvmLinkCommand(Compilation &C, // for the extracted archive of bitcode to inputs. auto TargetID = Args.getLastArgValue(options::OPT_mcpu_EQ); AddStaticDeviceLibsLinking(C, *this, JA, Inputs, Args, LlvmLinkArgs, "amdgcn", - TargetID, /*IsBitCodeSDL=*/true); + TargetID, + /*IsBitCodeSDL=*/true, + /*PostClangLink=*/false); const char *LlvmLink = Args.MakeArgString(getToolChain().GetProgramPath("llvm-link")); @@ -106,6 +108,11 @@ void AMDGCN::Linker::constructLldCommand(Compilation &C, const JobAction &JA, "-plugin-opt=-avail-extern-gv-in-addrspace-to-local=3")); } + if (Arg *A = Args.getLastArgNoClaim(options::OPT_g_Group)) + if (!A->getOption().matches(options::OPT_g0) && + !A->getOption().matches(options::OPT_ggdb0)) + LldArgs.push_back("-plugin-opt=-amdgpu-spill-cfi-saved-regs"); + for (const Arg *A : Args.filtered(options::OPT_mllvm)) { LldArgs.push_back( Args.MakeArgString(Twine("-plugin-opt=") + A->getValue(0))); @@ -148,7 +155,9 @@ void AMDGCN::Linker::constructLldCommand(Compilation &C, const JobAction &JA, // for the extracted archive of bitcode to inputs. auto TargetID = Args.getLastArgValue(options::OPT_mcpu_EQ); AddStaticDeviceLibsLinking(C, *this, JA, Inputs, Args, LldArgs, "amdgcn", - TargetID, /*IsBitCodeSDL=*/true); + TargetID, + /*IsBitCodeSDL=*/true, + /*PostClangLink=*/false); LldArgs.push_back("--no-whole-archive"); @@ -223,6 +232,11 @@ HIPAMDToolChain::HIPAMDToolChain(const Driver &D, const llvm::Triple &Triple, diagnoseUnsupportedSanitizers(Args); } +void HIPAMDToolChain::addActionsFromClangTargetOptions( + const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, + const JobAction &JA, Compilation &C, const InputInfoList &Inputs) const { +} + void HIPAMDToolChain::addClangTargetOptions( const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, Action::OffloadKind DeviceOffloadingKind) const { @@ -417,7 +431,7 @@ HIPAMDToolChain::getDeviceLibs(const llvm::opt::ArgList &DriverArgs, if (InstLib.empty()) return BCLibs; if (llvm::sys::fs::exists(InstLib)) - BCLibs.emplace_back(InstLib); + BCLibs.push_back(InstLib); else getDriver().Diag(diag::err_drv_no_such_file) << InstLib; } diff --git a/clang/lib/Driver/ToolChains/HIPAMD.h b/clang/lib/Driver/ToolChains/HIPAMD.h index 30fc01a2f8e40..603b5f223ad20 100644 --- a/clang/lib/Driver/ToolChains/HIPAMD.h +++ b/clang/lib/Driver/ToolChains/HIPAMD.h @@ -64,6 +64,11 @@ class LLVM_LIBRARY_VISIBILITY HIPAMDToolChain final : public ROCMToolChain { llvm::opt::DerivedArgList * TranslateArgs(const llvm::opt::DerivedArgList &Args, StringRef BoundArch, Action::OffloadKind DeviceOffloadKind) const override; + void addActionsFromClangTargetOptions(const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args, + const JobAction &JA, + Compilation &C, + const InputInfoList &Inputs) const override; void addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, diff --git a/clang/lib/Driver/ToolChains/HIPSPV.cpp b/clang/lib/Driver/ToolChains/HIPSPV.cpp index bce7f46dea468..fb738577c4c44 100644 --- a/clang/lib/Driver/ToolChains/HIPSPV.cpp +++ b/clang/lib/Driver/ToolChains/HIPSPV.cpp @@ -68,7 +68,9 @@ void HIPSPV::Linker::constructLinkAndEmitSpirvCommand( StringRef Target = "generic"; // SPIR-V is generic, no specific target ID like -mcpu tools::AddStaticDeviceLibsLinking(C, *this, JA, Inputs, Args, LinkArgs, Arch, - Target, /*IsBitCodeSDL=*/true); + Target, /*IsBitCodeSDL=*/true, + /*PostClangLink=*/false); + LinkArgs.append({"-o", TempFile}); const char *LlvmLink = Args.MakeArgString(getToolChain().GetProgramPath("llvm-link")); diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp index 94a9fe8b1a63f..f452109134171 100644 --- a/clang/lib/Driver/ToolChains/Linux.cpp +++ b/clang/lib/Driver/ToolChains/Linux.cpp @@ -734,6 +734,12 @@ void Linux::AddClangSystemIncludeArgs(const ArgList &DriverArgs, if (DriverArgs.hasArg(clang::driver::options::OPT_nostdinc)) return; + if (DriverArgs.hasArg(clang::driver::options::OPT_fopenmp)) { + // Look for system files in our compiler AOMP/include dir first + addSystemInclude(DriverArgs, CC1Args, + DriverArgs.MakeArgString(D.Dir + "/../include")); + } + // Add 'include' in the resource directory, which is similar to // GCC_INCLUDE_DIR (private headers) in GCC. Note: the include directory // contains some files conflicting with system /usr/include. musl systems @@ -788,6 +794,234 @@ void Linux::AddClangSystemIncludeArgs(const ArgList &DriverArgs, addSystemInclude(DriverArgs, CC1Args, ResourceDirInclude); } +/// Convert path list to Fortran frontend argument +static void AddFlangSysIncludeArg(const ArgList &DriverArgs, + ArgStringList &Flang1args, + ToolChain::path_list IncludePathList) { + std::string ArgValue; // Path argument value + + // Make up argument value consisting of paths separated by colons + bool first = true; + for (auto P : IncludePathList) { + if (first) { + first = false; + } else { + ArgValue += ":"; + } + ArgValue += P; + } + + // Add the argument + Flang1args.push_back("-stdinc"); + Flang1args.push_back(DriverArgs.MakeArgString(ArgValue)); +} + +static std::string DetectLibcxxIncludePath(llvm::vfs::FileSystem &vfs, + StringRef base) { + std::error_code EC; + int MaxVersion = 0; + std::string MaxVersionString = ""; + for (llvm::vfs::directory_iterator LI = vfs.dir_begin(base, EC), LE; + !EC && LI != LE; LI = LI.increment(EC)) { + StringRef VersionText = llvm::sys::path::filename(LI->path()); + int Version; + if (VersionText[0] == 'v' && + !VersionText.slice(1, StringRef::npos).getAsInteger(10, Version)) { + if (Version > MaxVersion) { + MaxVersion = Version; + MaxVersionString = std::string(VersionText); + } + } + } + return MaxVersion ? (base + "/" + MaxVersionString).str() : ""; +} + +void Linux::AddFlangSystemIncludeArgs(const ArgList &DriverArgs, + ArgStringList &Flang1args) const { + path_list IncludePathList; + const Driver &D = getDriver(); + std::string SysRoot = computeSysRoot(); + + if (DriverArgs.hasArg(options::OPT_nostdinc)) + return; + + { + SmallString<128> P(D.Dir); + llvm::sys::path::append(P, "../include"); + IncludePathList.push_back(DriverArgs.MakeArgString(P.str())); + } + + if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) + IncludePathList.push_back(SysRoot + "/usr/local/include"); + + if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) { + SmallString<128> P(D.ResourceDir); + llvm::sys::path::append(P, "include"); + IncludePathList.push_back(DriverArgs.MakeArgString(P.str())); + } + + if (DriverArgs.hasArg(options::OPT_nostdlibinc)) { + AddFlangSysIncludeArg(DriverArgs, Flang1args, IncludePathList); + return; + } + + // Check for configure-time C include directories. + StringRef CIncludeDirs(C_INCLUDE_DIRS); + if (CIncludeDirs != "") { + SmallVector dirs; + CIncludeDirs.split(dirs, ":"); + for (StringRef dir : dirs) { + StringRef Prefix = + llvm::sys::path::is_absolute(dir) ? StringRef(SysRoot) : ""; + IncludePathList.push_back(Prefix.str() + dir.str()); + } + AddFlangSysIncludeArg(DriverArgs, Flang1args, IncludePathList); + return; + } + + // Lacking those, try to detect the correct set of system includes for the + // target triple. + + // Add include directories specific to the selected multilib set and multilib. + if (GCCInstallation.isValid()) { + const auto &Callback = Multilibs.includeDirsCallback(); + if (Callback) { + for (const auto &Path : Callback(GCCInstallation.getMultilib())) + addExternCSystemIncludeIfExists( + DriverArgs, Flang1args, GCCInstallation.getInstallPath() + Path); + } + } + + // Implement generic Debian multiarch support. + const StringRef X86_64MultiarchIncludeDirs[] = { + "/usr/include/x86_64-linux-gnu", + + // FIXME: These are older forms of multiarch. It's not clear that they're + // in use in any released version of Debian, so we should consider + // removing them. + "/usr/include/i686-linux-gnu/64", "/usr/include/i486-linux-gnu/64"}; + const StringRef X86MultiarchIncludeDirs[] = { + "/usr/include/i386-linux-gnu", + + // FIXME: These are older forms of multiarch. It's not clear that they're + // in use in any released version of Debian, so we should consider + // removing them. + "/usr/include/x86_64-linux-gnu/32", "/usr/include/i686-linux-gnu", + "/usr/include/i486-linux-gnu"}; + const StringRef AArch64MultiarchIncludeDirs[] = { + "/usr/include/aarch64-linux-gnu"}; + const StringRef ARMMultiarchIncludeDirs[] = { + "/usr/include/arm-linux-gnueabi"}; + const StringRef ARMHFMultiarchIncludeDirs[] = { + "/usr/include/arm-linux-gnueabihf"}; + const StringRef MIPSMultiarchIncludeDirs[] = {"/usr/include/mips-linux-gnu"}; + const StringRef MIPSELMultiarchIncludeDirs[] = { + "/usr/include/mipsel-linux-gnu"}; + const StringRef MIPS64MultiarchIncludeDirs[] = { + "/usr/include/mips64-linux-gnu", "/usr/include/mips64-linux-gnuabi64"}; + const StringRef MIPS64ELMultiarchIncludeDirs[] = { + "/usr/include/mips64el-linux-gnu", + "/usr/include/mips64el-linux-gnuabi64"}; + const StringRef PPCMultiarchIncludeDirs[] = { + "/usr/include/powerpc-linux-gnu"}; + const StringRef PPC64MultiarchIncludeDirs[] = { + "/usr/include/powerpc64-linux-gnu"}; + const StringRef PPC64LEMultiarchIncludeDirs[] = { + "/usr/include/powerpc64le-linux-gnu"}; + const StringRef SparcMultiarchIncludeDirs[] = { + "/usr/include/sparc-linux-gnu"}; + const StringRef Sparc64MultiarchIncludeDirs[] = { + "/usr/include/sparc64-linux-gnu"}; + ArrayRef MultiarchIncludeDirs; + switch (getTriple().getArch()) { + case llvm::Triple::x86_64: + MultiarchIncludeDirs = X86_64MultiarchIncludeDirs; + break; + case llvm::Triple::x86: + MultiarchIncludeDirs = X86MultiarchIncludeDirs; + break; + case llvm::Triple::aarch64: + case llvm::Triple::aarch64_be: + MultiarchIncludeDirs = AArch64MultiarchIncludeDirs; + break; + case llvm::Triple::arm: + if (getTriple().getEnvironment() == llvm::Triple::GNUEABIHF) + MultiarchIncludeDirs = ARMHFMultiarchIncludeDirs; + else + MultiarchIncludeDirs = ARMMultiarchIncludeDirs; + break; + case llvm::Triple::mips: + MultiarchIncludeDirs = MIPSMultiarchIncludeDirs; + break; + case llvm::Triple::mipsel: + MultiarchIncludeDirs = MIPSELMultiarchIncludeDirs; + break; + case llvm::Triple::mips64: + MultiarchIncludeDirs = MIPS64MultiarchIncludeDirs; + break; + case llvm::Triple::mips64el: + MultiarchIncludeDirs = MIPS64ELMultiarchIncludeDirs; + break; + case llvm::Triple::ppc: + MultiarchIncludeDirs = PPCMultiarchIncludeDirs; + break; + case llvm::Triple::ppc64: + MultiarchIncludeDirs = PPC64MultiarchIncludeDirs; + break; + case llvm::Triple::ppc64le: + MultiarchIncludeDirs = PPC64LEMultiarchIncludeDirs; + break; + case llvm::Triple::sparc: + MultiarchIncludeDirs = SparcMultiarchIncludeDirs; + break; + case llvm::Triple::sparcv9: + MultiarchIncludeDirs = Sparc64MultiarchIncludeDirs; + break; + default: + break; + } + for (StringRef Dir : MultiarchIncludeDirs) { + if (llvm::sys::fs::exists(SysRoot + Dir)) { + IncludePathList.push_back(SysRoot + Dir.str()); + break; + } + } + + if (getTriple().getOS() == llvm::Triple::RTEMS) { + AddFlangSysIncludeArg(DriverArgs, Flang1args, IncludePathList); + return; + } + + // Add an include of '/include' directly. This isn't provided by default by + // system GCCs, but is often used with cross-compiling GCCs, and harmless to + // add even when Clang is acting as-if it were a system compiler. + IncludePathList.push_back(SysRoot + "/include"); + + IncludePathList.push_back(SysRoot + "/usr/include"); + + AddFlangSysIncludeArg(DriverArgs, Flang1args, IncludePathList); +} + +void Linux::addLibCxxIncludePaths(const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args) const { + const std::string& SysRoot = computeSysRoot(); + const std::string LibCXXIncludePathCandidates[] = { + DetectLibcxxIncludePath(getVFS(), getDriver().Dir + "/../include/c++"), + // If this is a development, non-installed, clang, libcxx will + // not be found at ../include/c++ but it likely to be found at + // one of the following two locations: + DetectLibcxxIncludePath(getVFS(), SysRoot + "/usr/local/include/c++"), + DetectLibcxxIncludePath(getVFS(), SysRoot + "/usr/include/c++") }; + for (const auto &IncludePath : LibCXXIncludePathCandidates) { + if (IncludePath.empty() || !getVFS().exists(IncludePath)) + continue; + // Use the first candidate that exists. + addSystemInclude(DriverArgs, CC1Args, IncludePath); + return; + } +} + + void Linux::addLibStdCxxIncludePaths(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const { // We need a detected GCC installation on Linux to provide libstdc++'s diff --git a/clang/lib/Driver/ToolChains/Linux.h b/clang/lib/Driver/ToolChains/Linux.h index 97bad77cb1caa..74be01d026681 100644 --- a/clang/lib/Driver/ToolChains/Linux.h +++ b/clang/lib/Driver/ToolChains/Linux.h @@ -30,6 +30,12 @@ class LLVM_LIBRARY_VISIBILITY Linux : public Generic_ELF { void AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const override; + void + AddFlangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &F901Args) const override; + void addLibCxxIncludePaths( + const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args) const override; void addLibStdCxxIncludePaths( const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args) const override; diff --git a/clang/lib/Driver/ToolChains/MSVC.cpp b/clang/lib/Driver/ToolChains/MSVC.cpp index bb469ff095cd4..0d4bbabb9bb8a 100644 --- a/clang/lib/Driver/ToolChains/MSVC.cpp +++ b/clang/lib/Driver/ToolChains/MSVC.cpp @@ -267,6 +267,9 @@ void visualstudio::Linker::ConstructJob(Compilation &C, const JobAction &JA, break; case Driver::OMPRT_GOMP: break; + case Driver::OMPRT_BOLT: + llvm::report_fatal_error("MSVC toolchain does not support OMPRT_BOLT"); + break; case Driver::OMPRT_Unknown: // Already diagnosed. break; diff --git a/clang/lib/Driver/ToolChains/MinGW.cpp b/clang/lib/Driver/ToolChains/MinGW.cpp index 1bb9bcfe6aab2..bd0e40ae3d7ad 100644 --- a/clang/lib/Driver/ToolChains/MinGW.cpp +++ b/clang/lib/Driver/ToolChains/MinGW.cpp @@ -313,6 +313,10 @@ void tools::MinGW::Linker::ConstructJob(Compilation &C, const JobAction &JA, case Driver::OMPRT_GOMP: CmdArgs.push_back("-lgomp"); break; + case Driver::OMPRT_BOLT: + llvm::report_fatal_error( + "MinGW toolchain does not support OMPRT_BOLT"); + break; case Driver::OMPRT_Unknown: // Already diagnosed. break; diff --git a/clang/lib/Driver/ToolChains/OpaqueOffloadLinker.cpp b/clang/lib/Driver/ToolChains/OpaqueOffloadLinker.cpp new file mode 100644 index 0000000000000..86283f620a653 --- /dev/null +++ b/clang/lib/Driver/ToolChains/OpaqueOffloadLinker.cpp @@ -0,0 +1,293 @@ +//=== OpaqueOffloadLinker - debugable command set for clang-linker-wrapper ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#include "Clang.h" +#include "clang/Driver/CommonArgs.h" +#include "llvm/ADT/StringMap.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/Support/Path.h" +#include "clang/Driver/RocmInstallationDetector.h" +#include "AMDGPU.h" +using namespace clang::driver; +using namespace clang::driver::tools; +using namespace clang; +using namespace llvm::opt; + +static const char *getOutputFileName(Compilation &C, StringRef Base, + const char *Postfix, + const char *Extension) { + const char *OutputFileName; + if (C.getDriver().isSaveTempsEnabled()) { + OutputFileName = + C.getArgs().MakeArgString(Base.str() + Postfix + "." + Extension); + } else { + std::string TmpName = + C.getDriver().GetTemporaryPath(Base.str() + Postfix, Extension); + OutputFileName = C.addTempFile(C.getArgs().MakeArgString(TmpName)); + } + return OutputFileName; +} + +static void addSubArchsWithTargetID(Compilation &C, const ArgList &Args, + const llvm::Triple &Triple, + SmallVectorImpl &subarchs) { + // process OPT_offload_arch_EQ subarch specification + ToolChain *TC; + for (auto itr : C.getDriver().getOffloadArchs( + C, C.getArgs(), Action::OFK_OpenMP, *TC)) + subarchs.push_back(itr.str()); + + // process OPT_Xopenmp_target_EQ subarch specification with march + for (auto itr : Args.getAllArgValues(options::OPT_Xopenmp_target_EQ)) { + SmallVector marchs; + StringRef vstr = StringRef(itr); + if (vstr.starts_with("-march=") || vstr.starts_with("--march=")) { + vstr.split('=').second.split(marchs, ','); + for (auto &march : marchs) + subarchs.push_back(march.str()); + } + } +} + +/// This is an alternative to LinkerWrapper::ConstructJob. +/// This is called when driver option --opaque-offload-linker is specified. + +/// opaque-offload-linker requires heterogeneous objects have bitcode +/// because offload LTO is implemented by merging all offloaded bitcodes +/// and then linking in system bitcode libraries followed by opt and then +/// the GPU backend is called only once for each TargetID. + +/// foreach(TargetID) { +/// foreach(input) { +/// 1 "unpackage" each .o input to create targetID specific bitcode +/// } +/// 2 build-select-link to create a merged bc with corrected attributes. +/// 3 llvm-link with -internalize -as-needed with system bitcode libraries. +/// 4 opt +/// 5 llc +/// 6 lld +/// } +/// 7 clang-offload-wrapper to output x.img +/// 8 clang (host) -cc1 -embed x.img -x host.bc -o x.o +/// 9 ld.lld x.o ... -o linkerwrapper ouput +/// +void LinkerWrapper::ConstructOpaqueJob(Compilation &C, const JobAction &JA, + const InputInfo &Output, + const InputInfoList &Inputs, + const ArgList &Args, + const llvm::Triple &TheTriple, + const char *LinkingOutput) const { + const ToolChain &TC = getToolChain(); + const Driver &D = getToolChain().getDriver(); + RocmInstallationDetector RocmInstallation(D, TheTriple, Args, true, true); + std::string OutputFilePrefix, OutputFile; + + SmallVector subarchs; + llvm::SmallVector, 4> TargetIDLLDMap; + + addSubArchsWithTargetID(C, Args, TheTriple, subarchs); + + for (auto &subArchWithTargetID : subarchs) { + StringRef TargetID(subArchWithTargetID); + // ---------- Step 1 unpackage each input ----------- + const char *UnpackageExec = Args.MakeArgString( + getToolChain().GetProgramPath("clang-offload-packager")); + + SmallVector UnpackagedFiles; + + for (const auto &II : Inputs) { + if (II.isFilename()) { + OutputFile = llvm::sys::path::stem(II.getFilename()).str(); + OutputFilePrefix = llvm::sys::path::stem(II.getBaseInput()).str() + + "-openmp-" + TheTriple.str() + "-" + TargetID.str(); + + // generate command to unpackage each II.getFilename() + auto UnpackagedFileName = + getOutputFileName(C, OutputFilePrefix, "-unpackaged", "bc"); + // push unpacked file names to argument list for clang-build-select + UnpackagedFiles.push_back(UnpackagedFileName); + ArgStringList UnpackageCmdArgs; + UnpackageCmdArgs.push_back(II.getFilename()); + + SmallVector Parts{ + "file=" + std::string(UnpackagedFileName), + "triple=" + TheTriple.str(), + "arch=" + TargetID.str(), + "kind=openmp", + }; + + UnpackageCmdArgs.push_back( + Args.MakeArgString("--image=" + llvm::join(Parts, ","))); + + UnpackageCmdArgs.push_back("--allow-missing-packages"); + + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), UnpackageExec, + UnpackageCmdArgs, Inputs, + InputInfo(&JA, Args.MakeArgString(UnpackagedFileName)))); + } + } + + // ---------- Step 2 clang-build-select-link ----------- + // Look for Static Device Libs (SDLs) in args, and add temp files for + // the extracted Device-specific Archive Libs (DAL) to inputs + ArgStringList CbslArgs; + AddStaticDeviceLibsLinking(C, *this, JA, Inputs, Args, CbslArgs, "amdgcn", + TargetID, + /* bitcode SDL?*/ true, + /* PostClang Link? */ false, + /* Unpackage? */ true); + + auto PreLinkFileName = amdgpu::dlr::getCbslCommandArgs( + C, Args, CbslArgs, UnpackagedFiles, OutputFilePrefix); + + const char *CbslExec = Args.MakeArgString( + getToolChain().GetProgramPath("clang-build-select-link")); + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), CbslExec, CbslArgs, + Inputs, InputInfo(&JA, Args.MakeArgString(PreLinkFileName)))); + + // ---------- Step 3 llvm-link internalize as-needed ----------- + ArgStringList LastLinkArgs; + // Find all directories pointed to by the environment variable + // LIBRARY_PATH. + ArgStringList EnvLibraryPaths; + addDirectoryList(Args, EnvLibraryPaths, "", "LIBRARY_PATH"); + auto LinkOutputFileName = amdgpu::dlr::getLinkCommandArgs( + C, Args, LastLinkArgs, TC, TheTriple, TargetID, OutputFilePrefix, + PreLinkFileName, RocmInstallation, EnvLibraryPaths); + + const char *LinkExec = + Args.MakeArgString(getToolChain().GetProgramPath("llvm-link")); + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), LinkExec, LastLinkArgs, + Inputs, InputInfo(&JA, Args.MakeArgString(LinkOutputFileName)))); + + // ---------- Step 4 opt ----------- + ArgStringList OptArgs; + + // Forward -Xopaque-offload-opt arguments to the 'opt' job. + for (Arg *A : Args.filtered(options::OPT_Xopaque_offload_opt)) { + OptArgs.push_back(A->getValue()); + A->claim(); + } + + auto OptOutputFileName = + amdgpu::dlr::getOptCommandArgs(C, Args, OptArgs, TheTriple, TargetID, + OutputFilePrefix, LinkOutputFileName); + + const char *OptExec = + Args.MakeArgString(getToolChain().GetProgramPath("opt")); + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), OptExec, OptArgs, Inputs, + InputInfo(&JA, Args.MakeArgString(OptOutputFileName)))); + + // ---------- Step 5 llc ----------- + ArgStringList LlcArgs; + auto LlcOutputFileName = + amdgpu::dlr::getLlcCommandArgs(C, Args, LlcArgs, TheTriple, TargetID, + OutputFilePrefix, OptOutputFileName); + + const char *LlcExec = + Args.MakeArgString(getToolChain().GetProgramPath("llc")); + + // produce assembly temp output file if --save-temps is specified + if (C.getDriver().isSaveTempsEnabled()) { + ArgStringList LlcAsmArgs; + auto LlcAsmOutputFileName = amdgpu::dlr::getLlcCommandArgs( + C, Args, LlcAsmArgs, TheTriple, TargetID, OutputFilePrefix, + OptOutputFileName, /*OutputIsAsm*/ true); + + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), LlcExec, LlcAsmArgs, + Inputs, InputInfo(&JA, Args.MakeArgString(LlcAsmOutputFileName)))); + } + + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), LlcExec, LlcArgs, Inputs, + InputInfo(&JA, Args.MakeArgString(LlcOutputFileName)))); + + // ---------- Step 6 lld ----------- + ArgStringList LldArgs; + auto LldOutputFileName = amdgpu::dlr::getLldCommandArgs( + C, Output, Args, LldArgs, TheTriple, TargetID, LlcOutputFileName, + OutputFilePrefix); + + // create vector of pairs of TargetID,lldname for step 7 inputs. + TargetIDLLDMap.push_back( + std::pair(TargetID, LldOutputFileName)); + + const char *LldExec = + Args.MakeArgString(getToolChain().GetProgramPath("lld")); + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), LldExec, LldArgs, Inputs, + InputInfo(&JA, Args.MakeArgString(LldOutputFileName)))); + + } // End loop for each subarch + + // -------- Step 7 clang-offload-wrapper to build device image + auto CowOutputFileName = getOutputFileName(C, OutputFile, "-wrapped", "bc"); + ArgStringList CowArgs; + const char *CowExec = Args.MakeArgString( + getToolChain().GetProgramPath("clang-offload-wrapper")); + + // The offload target. + CowArgs.push_back("-target"); + CowArgs.push_back(Args.MakeArgString(TheTriple.getTriple())); + + const llvm::Triple &Triple = getToolChain().getEffectiveTriple(); + + // The host triple is the "effective" target triple here. + CowArgs.push_back("-aux-triple"); + CowArgs.push_back(Args.MakeArgString(Triple.getTriple())); + + // Add the output file name. + assert(CowOutputFileName != nullptr && "Invalid output."); + CowArgs.push_back("-o"); + CowArgs.push_back(CowOutputFileName); + + // a vector of pairs of TargetID,lldName + for (auto &TM : TargetIDLLDMap) { + CowArgs.push_back(Args.MakeArgString(Twine("--offload-arch=") + TM.first)); + CowArgs.push_back(TM.second); + } + + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), CowExec, CowArgs, Inputs, + InputInfo(&JA, Args.MakeArgString(CowOutputFileName)))); + + // ---------- Step 8 clang -cc1 host backend ----------- + ArgStringList HbeArgs; + const char *HbeOutputFileName = + getOutputFileName(C, OutputFilePrefix, "-hbe", "o"); + const char *HbeExec = + Args.MakeArgString(getToolChain().GetProgramPath("clang")); + + HbeArgs.push_back("-cc1"); + HbeArgs.push_back("-triple"); + HbeArgs.push_back(Args.MakeArgString(getToolChain().getTripleString())); + HbeArgs.push_back("-emit-obj"); + HbeArgs.push_back("-o"); + HbeArgs.push_back(Args.MakeArgString(HbeOutputFileName)); + HbeArgs.push_back("-x"); + HbeArgs.push_back("ir"); + HbeArgs.push_back(Args.MakeArgString(CowOutputFileName)); + + C.addCommand(std::make_unique( + JA, *this, ResponseFileSupport::AtFileCurCP(), HbeExec, HbeArgs, Inputs, + InputInfo(&JA, Args.MakeArgString(HbeOutputFileName)))); + + // ---------- Step 9 final host link ----------- + InputInfoList LinkInputs; + for (const auto &II : Inputs) + LinkInputs.push_back(II); + + LinkInputs.push_back( + InputInfo(types::TY_Object, HbeOutputFileName, HbeOutputFileName)); + + Linker->ConstructJob(C, JA, Output, LinkInputs, Args, LinkingOutput); +} diff --git a/clang/lib/Driver/ToolChains/SPIRV.cpp b/clang/lib/Driver/ToolChains/SPIRV.cpp index ea824dbad54cb..afb9e63b4b348 100644 --- a/clang/lib/Driver/ToolChains/SPIRV.cpp +++ b/clang/lib/Driver/ToolChains/SPIRV.cpp @@ -34,11 +34,17 @@ void SPIRV::constructTranslateCommand(Compilation &C, const Tool &T, // Try to find "llvm-spirv-". Otherwise, fall back to // plain "llvm-spirv". + // AMD FORK ONLY: instead of llvm-spirv we look for the amd-llvm-spirv, which + // is our ephemeral, temporary build of the translator that nests changes that + // are not in upstream. This will be removed in the future. using namespace std::string_literals; auto VersionedTool = "llvm-spirv-"s + std::to_string(LLVM_VERSION_MAJOR); + if (T.getToolChain().getTriple().getVendor() == llvm::Triple::VendorType::AMD) + VersionedTool.insert(0, "amd-"); std::string ExeCand = T.getToolChain().GetProgramPath(VersionedTool.c_str()); if (!llvm::sys::fs::can_execute(ExeCand)) - ExeCand = T.getToolChain().GetProgramPath("llvm-spirv"); + ExeCand = T.getToolChain().GetProgramPath( + VersionedTool.substr(0, VersionedTool.find_last_of('-')).c_str()); const char *Exec = C.getArgs().MakeArgString(ExeCand); C.addCommand(std::make_unique(JA, T, ResponseFileSupport::None(), diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index bd36eb4ecf9da..051ae2b9af0e7 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -749,6 +749,14 @@ static unsigned getOptimizationLevelSize(ArgList &Args) { return 0; } +/// Assume no thread state at -Ofast +static bool isOFastUsed(const ArgList &Args) { + if (Arg *A = Args.getLastArg(options::OPT_O_Group)) + if (A->getOption().matches(options::OPT_Ofast)) + return true; + return false; +} + static void GenerateArg(ArgumentConsumer Consumer, llvm::opt::OptSpecifier OptSpecifier) { Option Opt = getDriverOptTable().getOption(OptSpecifier); @@ -3852,12 +3860,67 @@ void CompilerInvocationBase::GenerateLangArgs(const LangOptions &Opts, GenerateArg(Consumer, OPT_fopenmp_version_EQ, Twine(Opts.OpenMP)); } + if (Opts.OpenMPTargetIgnoreEnvVars) + GenerateArg(Consumer, OPT_fopenmp_target_ignore_env_vars); + else + GenerateArg(Consumer, OPT_fno_openmp_target_ignore_env_vars); + + if (Opts.OpenMPTargetBigJumpLoop) + GenerateArg(Consumer, OPT_fopenmp_target_big_jump_loop); + else + GenerateArg(Consumer, OPT_fno_openmp_target_big_jump_loop); + + if (Opts.OpenMPTargetNoLoop) + GenerateArg(Consumer, OPT_fopenmp_target_no_loop); + else + GenerateArg(Consumer, OPT_fno_openmp_target_no_loop); + + if (Opts.OpenMPTargetXteamReduction) + GenerateArg(Consumer, OPT_fopenmp_target_xteam_reduction); + else + GenerateArg(Consumer, OPT_fno_openmp_target_xteam_reduction); + + if (Opts.OpenMPTargetFastReduction) + GenerateArg(Consumer, OPT_fopenmp_target_fast_reduction); + else + GenerateArg(Consumer, OPT_fno_openmp_target_fast_reduction); + + if (Opts.OpenMPTargetMultiDevice) + GenerateArg(Consumer, OPT_fopenmp_target_multi_device); + else + GenerateArg(Consumer, OPT_fno_openmp_target_multi_device); + + if (Opts.OpenMPTargetXteamScan) + GenerateArg(Consumer, OPT_fopenmp_target_xteam_scan); + else + GenerateArg(Consumer, OPT_fno_openmp_target_xteam_scan); + + if (Opts.OpenMPTargetXteamNoLoopScan) + GenerateArg(Consumer, OPT_fopenmp_target_xteam_no_loop_scan); + else + GenerateArg(Consumer, OPT_fno_openmp_target_xteam_no_loop_scan); + if (Opts.OpenMPThreadSubscription) GenerateArg(Consumer, OPT_fopenmp_assume_threads_oversubscription); if (Opts.OpenMPTeamSubscription) GenerateArg(Consumer, OPT_fopenmp_assume_teams_oversubscription); + if (Opts.OpenMPNoThreadState) + GenerateArg(Consumer, OPT_fopenmp_assume_no_thread_state); + else + GenerateArg(Consumer, OPT_fno_openmp_assume_no_thread_state); + + if (Opts.OpenMPNoNestedParallelism) + GenerateArg(Consumer, OPT_fopenmp_assume_no_nested_parallelism); + else + GenerateArg(Consumer, OPT_fno_openmp_assume_no_nested_parallelism); + + if (Opts.OpenMPKernelIO) + GenerateArg(Consumer, OPT_fopenmp_allow_kernel_io); + else + GenerateArg(Consumer, OPT_fno_openmp_allow_kernel_io); + if (Opts.OpenMPTargetDebug != 0) GenerateArg(Consumer, OPT_fopenmp_target_debug_EQ, Twine(Opts.OpenMPTargetDebug)); @@ -3874,6 +3937,14 @@ void CompilerInvocationBase::GenerateLangArgs(const LangOptions &Opts, GenerateArg(Consumer, OPT_fopenmp_cuda_teams_reduction_recs_num_EQ, Twine(Opts.OpenMPCUDAReductionBufNum)); + if (Opts.OpenMPGPUThreadsPerTeam != 256) + GenerateArg(Consumer, OPT_fopenmp_gpu_threads_per_team_EQ, + Twine(Opts.OpenMPGPUThreadsPerTeam)); + + if (Opts.OpenMPTargetXteamReductionBlockSize != 1024) + GenerateArg(Consumer, OPT_fopenmp_target_xteam_reduction_blocksize_EQ, + Twine(Opts.OpenMPTargetXteamReductionBlockSize)); + if (!Opts.OMPTargetTriples.empty()) { std::string Targets; llvm::raw_string_ostream OS(Targets); @@ -4322,6 +4393,54 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, Opts.OpenMPCUDAReductionBufNum, Diags); } + Opts.OpenMPGPUThreadsPerTeam = + getLastArgIntValue(Args, options::OPT_fopenmp_gpu_threads_per_team_EQ, + Opts.OpenMPGPUThreadsPerTeam, Diags); + + Opts.OpenMPTargetXteamReductionBlockSize = getLastArgIntValue( + Args, options::OPT_fopenmp_target_xteam_reduction_blocksize_EQ, + Opts.OpenMPTargetXteamReductionBlockSize, Diags); + + Opts.OpenMPTargetIgnoreEnvVars = + Args.hasFlag(options::OPT_fopenmp_target_ignore_env_vars, + options::OPT_fno_openmp_target_ignore_env_vars, false); + + Opts.OpenMPTargetBigJumpLoop = + Args.hasFlag(options::OPT_fopenmp_target_big_jump_loop, + options::OPT_fno_openmp_target_big_jump_loop, true); + + Opts.OpenMPTargetNoLoop = + Args.hasFlag(options::OPT_fopenmp_target_no_loop, + options::OPT_fno_openmp_target_no_loop, true); + + Opts.OpenMPTargetXteamReduction = + Args.hasFlag(options::OPT_fopenmp_target_xteam_reduction, + options::OPT_fno_openmp_target_xteam_reduction, true); + + Opts.OpenMPTargetFastReduction = + Args.hasFlag(options::OPT_fopenmp_target_fast_reduction, + options::OPT_fno_openmp_target_fast_reduction, false); + + Opts.OpenMPTargetMultiDevice = + Args.hasFlag(options::OPT_fopenmp_target_multi_device, + options::OPT_fno_openmp_target_multi_device, false); + + // Multi-device kernels always run in fast xteam reduction mode: + if (Opts.OpenMPTargetMultiDevice) + Opts.OpenMPTargetFastReduction = true; + + Opts.OpenMPTargetXteamScan = + Args.hasFlag(options::OPT_fopenmp_target_xteam_scan, + options::OPT_fno_openmp_target_xteam_scan, false); + + Opts.OpenMPTargetXteamNoLoopScan = + Args.hasFlag(options::OPT_fopenmp_target_xteam_no_loop_scan, + options::OPT_fno_openmp_target_xteam_no_loop_scan, false); + + Opts.OpenMPKernelIO = + Args.hasFlag(options::OPT_fopenmp_allow_kernel_io, + options::OPT_fno_openmp_allow_kernel_io, true); + // Set the value of the debugging flag used in the new offloading device RTL. // Set either by a specific value or to a default if not specified. if (Opts.OpenMPIsTargetDevice && (Args.hasArg(OPT_fopenmp_target_debug) || @@ -4339,6 +4458,16 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, Opts.OpenMPThreadSubscription = true; } + // Turn ON at -Ofast + Opts.OpenMPNoThreadState = Args.hasFlag( + options::OPT_fopenmp_assume_no_thread_state, + options::OPT_fno_openmp_assume_no_thread_state, isOFastUsed(Args)); + + // Turn ON at -Ofast + Opts.OpenMPNoNestedParallelism = Args.hasFlag( + options::OPT_fopenmp_assume_no_nested_parallelism, + options::OPT_fno_openmp_assume_no_nested_parallelism, isOFastUsed(Args)); + // Get the OpenMP target triples if any. if (Arg *A = Args.getLastArg(options::OPT_offload_targets_EQ)) { enum ArchPtrSize { Arch16Bit, Arch32Bit, Arch64Bit }; diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt index 18589125697b0..4e0a8ada2a6ef 100644 --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -251,6 +251,9 @@ set(x86_files movrsintrin.h mwaitxintrin.h nmmintrin.h + omp_libmextras.h + opencl-c.h + opencl-c-base.h pconfigintrin.h pkuintrin.h pmmintrin.h @@ -382,6 +385,7 @@ set(openmp_wrapper_files openmp_wrappers/__clang_openmp_device_functions.h openmp_wrappers/complex_cmath.h openmp_wrappers/new + openmp_wrappers/hip/hip_runtime.h ) set(llvm_offload_wrapper_files diff --git a/clang/lib/Headers/__clang_cuda_cmath.h b/clang/lib/Headers/__clang_cuda_cmath.h index 5bbb59a93b9e5..895e15e3271e8 100644 --- a/clang/lib/Headers/__clang_cuda_cmath.h +++ b/clang/lib/Headers/__clang_cuda_cmath.h @@ -85,7 +85,7 @@ __DEVICE__ float frexp(float __arg, int *__exp) { // this clash we add a new trait to some of them that is always true // (this is LLVM after all ;)). It will only influence the mangled name // of the variants inside the inner region and avoid the clash. -#pragma omp begin declare variant match(implementation = {vendor(llvm)}) +#pragma omp begin declare variant match(implementation = {vendor(amd)}) __DEVICE__ int isinf(float __x) { return ::__isinff(__x); } __DEVICE__ int isinf(double __x) { return ::__isinf(__x); } diff --git a/clang/lib/Headers/__clang_cuda_complex_builtins.h b/clang/lib/Headers/__clang_cuda_complex_builtins.h index 7bc7bc2ce63e1..dba5b80780cdc 100644 --- a/clang/lib/Headers/__clang_cuda_complex_builtins.h +++ b/clang/lib/Headers/__clang_cuda_complex_builtins.h @@ -255,6 +255,36 @@ __DEVICE__ float _Complex __divsc3(float __a, float __b, float __c, float __d) { return z; } +// Define complex math functions for amdgcn openmp here +#if defined(__OPENMP_AMDGCN__) +typedef double __2f64 __attribute__((ext_vector_type(2))); +typedef float __2f32 __attribute__((ext_vector_type(2))); +union __union_d {__2f64 d2; _Complex double cd;}; +union __union_f {__2f32 f2; _Complex float cf;}; + +// One successful way to link to AMD's __ocml_cexp_f64 and __ocml_cexp_f32 +// which are defined in OpenCL is to use C prototypes that have type +// __2f64 for arg and return values (or _2f32) +__2f64 __ocml_cexp_f64(__2f64 _arg_2f64); +__2f32 __ocml_cexp_f32(__2f32 _arg_2f32); + +// One successful way to create the cexp function whose call-site +// is generated by clang codegen, for "res=exp(inp);" is to use +// _Complex double for both arg and return types (or _Complex float) +// The compiler does not allow typecast _Complex double to __2f64. +// So we use union. +__DEVICE__ _Complex double cexp(_Complex double _a){ + union __union_d _ua = {.cd = _a}; + union __union_d _ur = {.d2 = __ocml_cexp_f64(_ua.d2)}; + return _ur.cd; +} +__DEVICE__ _Complex float cexpf(_Complex float _a){ + union __union_f _ua = {.cf = _a}; + union __union_f _ur = {.f2 = __ocml_cexp_f32(_ua.f2)}; + return _ur.cf; +} +#endif // defined(__OPENMP_AMDGCN__) + #if defined(__cplusplus) } // extern "C" #endif diff --git a/clang/lib/Headers/__clang_cuda_math.h b/clang/lib/Headers/__clang_cuda_math.h index 44c6e9a4e48d1..972f2714dba12 100644 --- a/clang/lib/Headers/__clang_cuda_math.h +++ b/clang/lib/Headers/__clang_cuda_math.h @@ -28,11 +28,28 @@ #pragma push_macro("__DEVICE__") #ifdef __OPENMP_NVPTX__ #if defined(__cplusplus) +#ifdef __BUILD_MATH_BUILTINS_LIB__ +#include +#define HUGE_VALF (__builtin_huge_valf()) +#define HUGE_VAL (__builtin_huge_val()) +#define __DEVICE__ extern "C" __attribute__((always_inline, nothrow)) +#else #define __DEVICE__ static constexpr __attribute__((always_inline, nothrow)) +#endif // __BUILD_MATH_BUILTINS_LIB__ +#else +// Use __BUILD_MATH_BUILTINS_LIB__ to build device specific libm-nvptx.bc +// for FORTRAN bitcode linking since FORTRAN cannot use c headers. +#ifdef __BUILD_MATH_BUILTINS_LIB__ +#include +#define HUGE_VALF (__builtin_huge_valf()) +#define HUGE_VAL (__builtin_huge_val()) +#define __DEVICE__ extern __attribute__((always_inline, nothrow)) #else #define __DEVICE__ static __attribute__((always_inline, nothrow)) -#endif +#endif // __BUILD_MATH_BUILTINS_LIB__ +#endif // __cplusplus #else +// CUDA Clang #define __DEVICE__ static __device__ __forceinline__ #endif diff --git a/clang/lib/Headers/__clang_hip_cmath.h b/clang/lib/Headers/__clang_hip_cmath.h index 8dbde4291fff5..09b73b1fb0ba2 100644 --- a/clang/lib/Headers/__clang_hip_cmath.h +++ b/clang/lib/Headers/__clang_hip_cmath.h @@ -24,15 +24,17 @@ #include #endif // !defined(__HIPCC_RTC__) +// __DEVICE__ is a helper macro with common set of attributes for the wrappers +// we implement in this file. We need static in order to avoid emitting unused +// functions. #pragma push_macro("__DEVICE__") #pragma push_macro("__CONSTEXPR__") +#define __CONSTEXPR__ #ifdef __OPENMP_AMDGCN__ -#define __DEVICE__ static __attribute__((always_inline, nothrow)) -#define __CONSTEXPR__ constexpr +#define __DEVICE__ static constexpr __attribute__((always_inline, nothrow)) #else #define __DEVICE__ static __device__ inline __attribute__((always_inline)) -#define __CONSTEXPR__ -#endif // __OPENMP_AMDGCN__ +#endif // Start with functions that cannot be defined by DEF macros below. #if defined(__cplusplus) @@ -81,7 +83,7 @@ __DEVICE__ __CONSTEXPR__ float frexp(float __arg, int *__exp) { // this clash we add a new trait to some of them that is always true // (this is LLVM after all ;)). It will only influence the mangled name // of the variants inside the inner region and avoid the clash. -#pragma omp begin declare variant match(implementation = {vendor(llvm)}) +#pragma omp begin declare variant match(implementation = {vendor(amd)}) __DEVICE__ __CONSTEXPR__ int isinf(float __x) { return ::__isinff(__x); } __DEVICE__ __CONSTEXPR__ int isinf(double __x) { return ::__isinf(__x); } diff --git a/clang/lib/Headers/__clang_hip_math.h b/clang/lib/Headers/__clang_hip_math.h index 759e742c9d012..2268f527dc1e4 100644 --- a/clang/lib/Headers/__clang_hip_math.h +++ b/clang/lib/Headers/__clang_hip_math.h @@ -21,16 +21,41 @@ #include #include #ifdef __OPENMP_AMDGCN__ +// FIXME: A hack for the OpenMP DeviceRTL's `LibM.h` that should be removed. +#ifndef __OPENMP_SKIP_INCLUDE__ #include #endif +#endif #endif // !defined(__HIPCC_RTC__) +// __DEVICE__ is a helper macro with common set of attributes for the wrappers +// we implement in this file. We need static in order to avoid emitting unused +// functions and __forceinline__ helps inlining these wrappers at -O1. #pragma push_macro("__DEVICE__") +#pragma push_macro("__DEVICE_NOCE__") #ifdef __OPENMP_AMDGCN__ -#define __DEVICE__ static inline __attribute__((always_inline, nothrow)) +#if defined(__cplusplus) +#ifdef __BUILD_MATH_BUILTINS_LIB__ +#define __DEVICE__ extern "C" __attribute__((always_inline, nothrow)) +#define __DEVICE_NOCE__ __DEVICE__ #else +#define __DEVICE__ static constexpr __attribute__((always_inline, nothrow)) +#define __DEVICE_NOCE__ static __attribute__((always_inline, nothrow)) +#endif +#else // !defined(__cplusplus), c openmp compilation +// Special case to build c-only device function lib for FORTRAN. +#ifdef __BUILD_MATH_BUILTINS_LIB__ +#define __DEVICE__ extern __attribute__((always_inline, nothrow)) +#define __DEVICE_NOCE__ __DEVICE__ +#else +#define __DEVICE__ static __attribute__((always_inline, nothrow)) +#define __DEVICE_NOCE__ __DEVICE__ +#endif +#endif +#else // !__OPENMP_AMDGCN__, so this is for HIP-Clang which is always C++. #define __DEVICE__ static __device__ inline __attribute__((always_inline)) +#define __DEVICE_NOCE__ __DEVICE__ #endif #pragma push_macro("__PRIVATE_AS") @@ -65,10 +90,15 @@ template struct __compare_result{}; template<> struct __compare_result { - static const __device__ bool valid; + static const bool valid; }; -__DEVICE__ +// All following c-capable function defs have one of two macro modifiers: +// __DEVICE__ +// __DEVICE_NOCE__ same as __DEVICE__ but no constexpr for those functions +// that cannot return constexpr in c++. + +__DEVICE_NOCE__ void __suppress_unused_warning(bool b){}; template __DEVICE__ void __static_assert_equal_size() { @@ -84,7 +114,7 @@ __DEVICE__ void __static_assert_equal_size() { #endif -__DEVICE__ +__DEVICE_NOCE__ uint64_t __make_mantissa_base8(const char *__tagp __attribute__((nonnull))) { uint64_t __r = 0; while (*__tagp != '\0') { @@ -101,7 +131,7 @@ uint64_t __make_mantissa_base8(const char *__tagp __attribute__((nonnull))) { return __r; } -__DEVICE__ +__DEVICE_NOCE__ uint64_t __make_mantissa_base10(const char *__tagp __attribute__((nonnull))) { uint64_t __r = 0; while (*__tagp != '\0') { @@ -118,7 +148,7 @@ uint64_t __make_mantissa_base10(const char *__tagp __attribute__((nonnull))) { return __r; } -__DEVICE__ +__DEVICE_NOCE__ uint64_t __make_mantissa_base16(const char *__tagp __attribute__((nonnull))) { uint64_t __r = 0; while (*__tagp != '\0') { @@ -301,7 +331,7 @@ float __powf(float __x, float __y) { return __ocml_pow_f32(__x, __y); } __DEVICE__ float __saturatef(float __x) { return (__x < 0) ? 0 : ((__x > 1) ? 1 : __x); } -__DEVICE__ +__DEVICE_NOCE__ void __sincosf(float __x, float *__sinptr, float *__cosptr) { *__sinptr = __ocml_native_sin_f32(__x); *__cosptr = __ocml_native_cos_f32(__x); @@ -429,7 +459,7 @@ float fminf(float __x, float __y) { return __builtin_fminf(__x, __y); } __DEVICE__ float fmodf(float __x, float __y) { return __ocml_fmod_f32(__x, __y); } -__DEVICE__ +__DEVICE_NOCE__ float frexpf(float __x, int *__nptr) { return __builtin_frexpf(__x, __nptr); } @@ -455,7 +485,7 @@ float j0f(float __x) { return __ocml_j0_f32(__x); } __DEVICE__ float j1f(float __x) { return __ocml_j1_f32(__x); } -__DEVICE__ +__DEVICE_NOCE__ float jnf(int __n, float __x) { // TODO: we could use Ahmes multiplication // and the Miller & Brown algorithm // for linear recurrences to get O(log n) steps, but it's unclear if @@ -509,7 +539,7 @@ long int lrintf(float __x) { return __builtin_rintf(__x); } __DEVICE__ long int lroundf(float __x) { return __builtin_roundf(__x); } -__DEVICE__ +__DEVICE_NOCE__ float modff(float __x, float *__iptr) { float __tmp; #ifdef __OPENMP_AMDGCN__ @@ -520,6 +550,8 @@ float modff(float __x, float *__iptr) { return __r; } +// FIXME need a c version of nanf +#if defined(__cplusplus) __DEVICE__ float nanf(const char *__tagp __attribute__((nonnull))) { union { @@ -540,6 +572,7 @@ float nanf(const char *__tagp __attribute__((nonnull))) { return __tmp.val; } +#endif __DEVICE__ float nearbyintf(float __x) { return __builtin_nearbyintf(__x); } @@ -565,7 +598,7 @@ float normcdff(float __x) { return __ocml_ncdf_f32(__x); } __DEVICE__ float normcdfinvf(float __x) { return __ocml_ncdfinv_f32(__x); } -__DEVICE__ +__DEVICE_NOCE__ float normf(int __dim, const float *__a) { // TODO: placeholder until OCML adds support. float __r = 0; @@ -591,7 +624,7 @@ float remainderf(float __x, float __y) { return __ocml_remainder_f32(__x, __y); } -__DEVICE__ +__DEVICE_NOCE__ float remquof(float __x, float __y, int *__quo) { int __tmp; #ifdef __OPENMP_AMDGCN__ @@ -619,7 +652,7 @@ float rnorm4df(float __x, float __y, float __z, float __w) { return __ocml_rlen4_f32(__x, __y, __z, __w); } -__DEVICE__ +__DEVICE_NOCE__ float rnormf(int __dim, const float *__a) { // TODO: placeholder until OCML adds support. float __r = 0; @@ -652,7 +685,7 @@ float scalbnf(float __x, int __n) { return __builtin_amdgcn_ldexpf(__x, __n); } __DEVICE__ __RETURN_TYPE __signbitf(float __x) { return __builtin_signbitf(__x); } -__DEVICE__ +__DEVICE_NOCE__ void sincosf(float __x, float *__sinptr, float *__cosptr) { float __tmp; #ifdef __OPENMP_AMDGCN__ @@ -666,7 +699,7 @@ void sincosf(float __x, float *__sinptr, float *__cosptr) { #endif } -__DEVICE__ +__DEVICE_NOCE__ void sincospif(float __x, float *__sinptr, float *__cosptr) { float __tmp; #ifdef __OPENMP_AMDGCN__ @@ -706,7 +739,7 @@ float y0f(float __x) { return __ocml_y0_f32(__x); } __DEVICE__ float y1f(float __x) { return __ocml_y1_f32(__x); } -__DEVICE__ +__DEVICE_NOCE__ float ynf(int __n, float __x) { // TODO: we could use Ahmes multiplication // and the Miller & Brown algorithm // for linear recurrences to get O(log n) steps, but it's unclear if @@ -829,7 +862,7 @@ double fmin(double __x, double __y) { return __builtin_fmin(__x, __y); } __DEVICE__ double fmod(double __x, double __y) { return __ocml_fmod_f64(__x, __y); } -__DEVICE__ +__DEVICE_NOCE__ double frexp(double __x, int *__nptr) { return __builtin_frexp(__x, __nptr); } @@ -855,7 +888,7 @@ double j0(double __x) { return __ocml_j0_f64(__x); } __DEVICE__ double j1(double __x) { return __ocml_j1_f64(__x); } -__DEVICE__ +__DEVICE_NOCE__ double jn(int __n, double __x) { // TODO: we could use Ahmes multiplication // and the Miller & Brown algorithm // for linear recurrences to get O(log n) steps, but it's unclear if @@ -909,7 +942,7 @@ long int lrint(double __x) { return __builtin_rint(__x); } __DEVICE__ long int lround(double __x) { return __builtin_round(__x); } -__DEVICE__ +__DEVICE_NOCE__ double modf(double __x, double *__iptr) { double __tmp; #ifdef __OPENMP_AMDGCN__ @@ -921,6 +954,8 @@ double modf(double __x, double *__iptr) { return __r; } +// FIXME need a c version of nan +#if defined(__cplusplus) __DEVICE__ double nan(const char *__tagp) { #if !_WIN32 @@ -948,6 +983,7 @@ double nan(const char *__tagp) { return *reinterpret_cast(&__val); #endif } +#endif __DEVICE__ double nearbyint(double __x) { return __builtin_nearbyint(__x); } @@ -957,7 +993,7 @@ double nextafter(double __x, double __y) { return __ocml_nextafter_f64(__x, __y); } -__DEVICE__ +__DEVICE_NOCE__ double norm(int __dim, const double *__a) { // TODO: placeholder until OCML adds support. double __r = 0; @@ -999,7 +1035,7 @@ double remainder(double __x, double __y) { return __ocml_remainder_f64(__x, __y); } -__DEVICE__ +__DEVICE_NOCE__ double remquo(double __x, double __y, int *__quo) { int __tmp; #ifdef __OPENMP_AMDGCN__ @@ -1017,7 +1053,7 @@ double rhypot(double __x, double __y) { return __ocml_rhypot_f64(__x, __y); } __DEVICE__ double rint(double __x) { return __builtin_rint(__x); } -__DEVICE__ +__DEVICE_NOCE__ double rnorm(int __dim, const double *__a) { // TODO: placeholder until OCML adds support. double __r = 0; @@ -1062,7 +1098,7 @@ __RETURN_TYPE __signbit(double __x) { return __builtin_signbit(__x); } __DEVICE__ double sin(double __x) { return __ocml_sin_f64(__x); } -__DEVICE__ +__DEVICE_NOCE__ void sincos(double __x, double *__sinptr, double *__cosptr) { double __tmp; #ifdef __OPENMP_AMDGCN__ @@ -1072,7 +1108,7 @@ void sincos(double __x, double *__sinptr, double *__cosptr) { *__cosptr = __tmp; } -__DEVICE__ +__DEVICE_NOCE__ void sincospi(double __x, double *__sinptr, double *__cosptr) { double __tmp; #ifdef __OPENMP_AMDGCN__ @@ -1109,7 +1145,7 @@ double y0(double __x) { return __ocml_y0_f64(__x); } __DEVICE__ double y1(double __x) { return __ocml_y1_f64(__x); } -__DEVICE__ +__DEVICE_NOCE__ double yn(int __n, double __x) { // TODO: we could use Ahmes multiplication // and the Miller & Brown algorithm // for linear recurrences to get O(log n) steps, but it's unclear if @@ -1283,7 +1319,8 @@ double __fma_rn(double __x, double __y, double __z) { _Generic((__x), float : __signbitf, double : __signbit)(__x) #endif // !defined(__cplusplus) && __STDC_VERSION__ >= 201112L -#if defined(__cplusplus) +#if defined(__cplusplus) && !defined(__BUILD_MATH_BUILTINS_LIB__) +#ifndef __OPENMP_AMDGCN__ template __DEVICE__ T min(T __arg1, T __arg2) { return (__arg1 < __arg2) ? __arg1 : __arg2; } @@ -1291,6 +1328,7 @@ template __DEVICE__ T min(T __arg1, T __arg2) { template __DEVICE__ T max(T __arg1, T __arg2) { return (__arg1 > __arg2) ? __arg1 : __arg2; } +#endif __DEVICE__ int min(int __arg1, int __arg2) { return (__arg1 < __arg2) ? __arg1 : __arg2; @@ -1396,6 +1434,7 @@ inline double max(double const __a, float const __b) { // !defined(__HIP_NO_HOST_MIN_MAX_IN_GLOBAL_NAMESPACE__) #endif +#pragma pop_macro("__DEVICE_NOCE__") #pragma pop_macro("__DEVICE__") #pragma pop_macro("__PRIVATE_AS") #pragma pop_macro("__RETURN_TYPE") diff --git a/clang/lib/Headers/avx512fp16intrin.h b/clang/lib/Headers/avx512fp16intrin.h index 142cc079c2c4b..4c19cd557c220 100644 --- a/clang/lib/Headers/avx512fp16intrin.h +++ b/clang/lib/Headers/avx512fp16intrin.h @@ -19,6 +19,12 @@ typedef _Float16 __v32hf __attribute__((__vector_size__(64), __aligned__(64))); typedef _Float16 __m512h __attribute__((__vector_size__(64), __aligned__(64))); typedef _Float16 __m512h_u __attribute__((__vector_size__(64), __aligned__(1))); +typedef _Float16 __v8hf __attribute__((__vector_size__(16), __aligned__(16))); +typedef _Float16 __m128h __attribute__((__vector_size__(16), __aligned__(16))); +typedef _Float16 __m128h_u __attribute__((__vector_size__(16), __aligned__(1))); +typedef _Float16 __v16hf __attribute__((__vector_size__(32), __aligned__(32))); +typedef _Float16 __m256h __attribute__((__vector_size__(32), __aligned__(32))); +typedef _Float16 __m256h_u __attribute__((__vector_size__(32), __aligned__(1))); /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS512 \ diff --git a/clang/lib/Headers/llvm_libc_wrappers/string.h b/clang/lib/Headers/llvm_libc_wrappers/string.h index 0ea49cb137606..519f46672e56f 100644 --- a/clang/lib/Headers/llvm_libc_wrappers/string.h +++ b/clang/lib/Headers/llvm_libc_wrappers/string.h @@ -15,6 +15,22 @@ #include_next +// The GNU headers provide non C-standard headers when in C++ mode. Manually +// undefine it here so that the definitions agree with the C standard for our +// purposes. +#ifdef __cplusplus +extern "C" { +#pragma push_macro("__cplusplus") +#undef __cplusplus +#endif + +#include_next + +#pragma pop_macro("__cplusplus") +#ifdef __cplusplus +} +#endif + #if __has_include() #if defined(__HIP__) || defined(__CUDA__) diff --git a/clang/lib/Headers/llvm_libc_wrappers/time.h b/clang/lib/Headers/llvm_libc_wrappers/time.h index 9d1340c4eb748..e18a16a281f18 100644 --- a/clang/lib/Headers/llvm_libc_wrappers/time.h +++ b/clang/lib/Headers/llvm_libc_wrappers/time.h @@ -31,4 +31,7 @@ _Static_assert(sizeof(clock_t) == sizeof(long), "ABI mismatch!"); #endif +#else +#include_next + #endif // __CLANG_LLVM_LIBC_WRAPPERS_TIME_H__ diff --git a/clang/lib/Headers/module.modulemap b/clang/lib/Headers/module.modulemap index 2e4d533356569..a330c3ae38527 100644 --- a/clang/lib/Headers/module.modulemap +++ b/clang/lib/Headers/module.modulemap @@ -346,7 +346,6 @@ module _Builtin_unwind [system] { module opencl_c [system] { requires opencl header "opencl-c.h" - header "opencl-c-base.h" } module ptrauth [system] { diff --git a/clang/lib/Headers/omp_libmextras.h b/clang/lib/Headers/omp_libmextras.h new file mode 100644 index 0000000000000..239432a456201 --- /dev/null +++ b/clang/lib/Headers/omp_libmextras.h @@ -0,0 +1,30 @@ +/*===---- omp_libmextras.h -----host functions not defined in libm -=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + */ + +// NVIDIA and AMD define device math functions that are not in libm. +// They do this for CUDA and HIP respectively. For OpenMP, we need a +// fallback function for host execution. These functions are defined here. +// c and c++ users must include these with #include + +#ifndef __OMP_LIBMEXTRAS_H__ +#define __OMP_LIBMEXTRAS_H__ + +#ifndef _OPENMP +#error "This file is for OpenMP compilation only." +#endif + +// Host definitions of functions not in libm. +#if !defined(__NVPTX__) && !defined(__AMDGCN__) +float sinpif(const float x) { return (sinf(x * M_PI)); } +double sinpi(const double x) { return (sin(x * M_PI)); } +float cospif(const float x) { return (cosf(x * M_PI)); } +double cospi(const double x) { return (cos(x * M_PI)); } +#endif + +#endif // __OMP_LIBMEXTRAS_H__ diff --git a/clang/lib/Headers/opencl-c.h b/clang/lib/Headers/opencl-c.h index f65b4b314cffd..287bbf4b5e7e8 100644 --- a/clang/lib/Headers/opencl-c.h +++ b/clang/lib/Headers/opencl-c.h @@ -9,7 +9,715 @@ #ifndef _OPENCL_H_ #define _OPENCL_H_ -#include "opencl-c-base.h" +#ifndef _OPENCL_BASE_H_ +#define _OPENCL_BASE_H_ + +// Define extension macros + +#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200) +// For SPIR all extensions are supported. +#if defined(__SPIR__) +#define cl_khr_subgroup_extended_types 1 +#define cl_khr_subgroup_non_uniform_vote 1 +#define cl_khr_subgroup_ballot 1 +#define cl_khr_subgroup_non_uniform_arithmetic 1 +#define cl_khr_subgroup_shuffle 1 +#define cl_khr_subgroup_shuffle_relative 1 +#define cl_khr_subgroup_clustered_reduce 1 +#endif // defined(__SPIR__) +#endif // (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200) + +// Define feature macros for OpenCL C 2.0 +#if (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ == 200) +#define __opencl_c_pipes 1 +#define __opencl_c_generic_address_space 1 +#define __opencl_c_work_group_collective_functions 1 +#define __opencl_c_atomic_order_acq_rel 1 +#define __opencl_c_atomic_order_seq_cst 1 +#define __opencl_c_atomic_scope_device 1 +#define __opencl_c_atomic_scope_all_devices 1 +#define __opencl_c_device_enqueue 1 +#define __opencl_c_read_write_images 1 +#define __opencl_c_program_scope_global_variables 1 +#define __opencl_c_images 1 +#endif + + #if !defined(__opencl_c_generic_address_space) + // Internal feature macro to provide named (global, local, private) address + // space overloads for builtin functions that take a pointer argument. + #define __opencl_c_named_address_space_builtins 1 + #endif // !defined(__opencl_c_generic_address_space) + #if defined(cl_intel_subgroups) || defined(cl_khr_subgroups) || defined(__opencl_c_subgroups) + // Internal feature macro to provide subgroup builtins. + #define __opencl_subgroup_builtins 1 + #endif +// built-in scalar data types: + +/** + * An unsigned 8-bit integer. + */ +typedef unsigned char uchar; + +/** + * An unsigned 16-bit integer. + */ +typedef unsigned short ushort; + +/** + * An unsigned 32-bit integer. + */ +typedef unsigned int uint; + +/** + * An unsigned 64-bit integer. + */ +typedef unsigned long ulong; + +/** + * The unsigned integer type of the result of the sizeof operator. This + * is a 32-bit unsigned integer if CL_DEVICE_ADDRESS_BITS + * defined in table 4.3 is 32-bits and is a 64-bit unsigned integer if + * CL_DEVICE_ADDRESS_BITS is 64-bits. + */ +typedef __SIZE_TYPE__ size_t; + +/** + * A signed integer type that is the result of subtracting two pointers. + * This is a 32-bit signed integer if CL_DEVICE_ADDRESS_BITS + * defined in table 4.3 is 32-bits and is a 64-bit signed integer if + * CL_DEVICE_ADDRESS_BITS is 64-bits. + */ +typedef __PTRDIFF_TYPE__ ptrdiff_t; + +/** + * A signed integer type with the property that any valid pointer to + * void can be converted to this type, then converted back to pointer + * to void, and the result will compare equal to the original pointer. + */ +typedef __INTPTR_TYPE__ intptr_t; + +/** + * An unsigned integer type with the property that any valid pointer to + * void can be converted to this type, then converted back to pointer + * to void, and the result will compare equal to the original pointer. + */ +typedef __UINTPTR_TYPE__ uintptr_t; + +// built-in vector data types: +typedef char char2 __attribute__((ext_vector_type(2))); +typedef char char3 __attribute__((ext_vector_type(3))); +typedef char char4 __attribute__((ext_vector_type(4))); +typedef char char8 __attribute__((ext_vector_type(8))); +typedef char char16 __attribute__((ext_vector_type(16))); +typedef uchar uchar2 __attribute__((ext_vector_type(2))); +typedef uchar uchar3 __attribute__((ext_vector_type(3))); +typedef uchar uchar4 __attribute__((ext_vector_type(4))); +typedef uchar uchar8 __attribute__((ext_vector_type(8))); +typedef uchar uchar16 __attribute__((ext_vector_type(16))); +typedef short short2 __attribute__((ext_vector_type(2))); +typedef short short3 __attribute__((ext_vector_type(3))); +typedef short short4 __attribute__((ext_vector_type(4))); +typedef short short8 __attribute__((ext_vector_type(8))); +typedef short short16 __attribute__((ext_vector_type(16))); +typedef ushort ushort2 __attribute__((ext_vector_type(2))); +typedef ushort ushort3 __attribute__((ext_vector_type(3))); +typedef ushort ushort4 __attribute__((ext_vector_type(4))); +typedef ushort ushort8 __attribute__((ext_vector_type(8))); +typedef ushort ushort16 __attribute__((ext_vector_type(16))); +typedef int int2 __attribute__((ext_vector_type(2))); +typedef int int3 __attribute__((ext_vector_type(3))); +typedef int int4 __attribute__((ext_vector_type(4))); +typedef int int8 __attribute__((ext_vector_type(8))); +typedef int int16 __attribute__((ext_vector_type(16))); +typedef uint uint2 __attribute__((ext_vector_type(2))); +typedef uint uint3 __attribute__((ext_vector_type(3))); +typedef uint uint4 __attribute__((ext_vector_type(4))); +typedef uint uint8 __attribute__((ext_vector_type(8))); +typedef uint uint16 __attribute__((ext_vector_type(16))); +typedef long long2 __attribute__((ext_vector_type(2))); +typedef long long3 __attribute__((ext_vector_type(3))); +typedef long long4 __attribute__((ext_vector_type(4))); +typedef long long8 __attribute__((ext_vector_type(8))); +typedef long long16 __attribute__((ext_vector_type(16))); +typedef ulong ulong2 __attribute__((ext_vector_type(2))); +typedef ulong ulong3 __attribute__((ext_vector_type(3))); +typedef ulong ulong4 __attribute__((ext_vector_type(4))); +typedef ulong ulong8 __attribute__((ext_vector_type(8))); +typedef ulong ulong16 __attribute__((ext_vector_type(16))); +typedef float float2 __attribute__((ext_vector_type(2))); +typedef float float3 __attribute__((ext_vector_type(3))); +typedef float float4 __attribute__((ext_vector_type(4))); +typedef float float8 __attribute__((ext_vector_type(8))); +typedef float float16 __attribute__((ext_vector_type(16))); +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +typedef half half2 __attribute__((ext_vector_type(2))); +typedef half half3 __attribute__((ext_vector_type(3))); +typedef half half4 __attribute__((ext_vector_type(4))); +typedef half half8 __attribute__((ext_vector_type(8))); +typedef half half16 __attribute__((ext_vector_type(16))); +#endif +#ifdef cl_khr_fp64 +#if __OPENCL_C_VERSION__ < CL_VERSION_1_2 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable +#endif +typedef double double2 __attribute__((ext_vector_type(2))); +typedef double double3 __attribute__((ext_vector_type(3))); +typedef double double4 __attribute__((ext_vector_type(4))); +typedef double double8 __attribute__((ext_vector_type(8))); +typedef double double16 __attribute__((ext_vector_type(16))); +#endif + +// An internal alias for half, for use by OpenCLBuiltins.td. +#define __half half + +#if defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ >= CL_VERSION_2_0) +#define NULL ((void*)0) +#endif + +/** + * Value of maximum non-infinite single-precision floating-point + * number. + */ +#define MAXFLOAT 0x1.fffffep127f + +/** + * A positive float constant expression. HUGE_VALF evaluates + * to +infinity. Used as an error value returned by the built-in + * math functions. + */ +#define HUGE_VALF (__builtin_huge_valf()) + +/** + * A positive double constant expression. HUGE_VAL evaluates + * to +infinity. Used as an error value returned by the built-in + * math functions. + */ +#define HUGE_VAL (__builtin_huge_val()) + +/** + * A constant expression of type float representing positive or + * unsigned infinity. + */ +#define INFINITY (__builtin_inff()) + +/** + * A constant expression of type float representing a quiet NaN. + */ +#define NAN as_float(INT_MAX) + +#define FP_ILOGB0 INT_MIN +#define FP_ILOGBNAN INT_MAX + +#define FLT_DIG 6 +#define FLT_MANT_DIG 24 +#define FLT_MAX_10_EXP +38 +#define FLT_MAX_EXP +128 +#define FLT_MIN_10_EXP -37 +#define FLT_MIN_EXP -125 +#define FLT_RADIX 2 +#define FLT_MAX 0x1.fffffep127f +#define FLT_MIN 0x1.0p-126f +#define FLT_EPSILON 0x1.0p-23f + +#define M_E_F 2.71828182845904523536028747135266250f +#define M_LOG2E_F 1.44269504088896340735992468100189214f +#define M_LOG10E_F 0.434294481903251827651128918916605082f +#define M_LN2_F 0.693147180559945309417232121458176568f +#define M_LN10_F 2.30258509299404568401799145468436421f +#define M_PI_F 3.14159265358979323846264338327950288f +#define M_PI_2_F 1.57079632679489661923132169163975144f +#define M_PI_4_F 0.785398163397448309615660845819875721f +#define M_1_PI_F 0.318309886183790671537767526745028724f +#define M_2_PI_F 0.636619772367581343075535053490057448f +#define M_2_SQRTPI_F 1.12837916709551257389615890312154517f +#define M_SQRT2_F 1.41421356237309504880168872420969808f +#define M_SQRT1_2_F 0.707106781186547524400844362104849039f + +#define DBL_DIG 15 +#define DBL_MANT_DIG 53 +#define DBL_MAX_10_EXP +308 +#define DBL_MAX_EXP +1024 +#define DBL_MIN_10_EXP -307 +#define DBL_MIN_EXP -1021 +#define DBL_RADIX 2 +#define DBL_MAX 0x1.fffffffffffffp1023 +#define DBL_MIN 0x1.0p-1022 +#define DBL_EPSILON 0x1.0p-52 + +#define M_E 0x1.5bf0a8b145769p+1 +#define M_LOG2E 0x1.71547652b82fep+0 +#define M_LOG10E 0x1.bcb7b1526e50ep-2 +#define M_LN2 0x1.62e42fefa39efp-1 +#define M_LN10 0x1.26bb1bbb55516p+1 +#define M_PI 0x1.921fb54442d18p+1 +#define M_PI_2 0x1.921fb54442d18p+0 +#define M_PI_4 0x1.921fb54442d18p-1 +#define M_1_PI 0x1.45f306dc9c883p-2 +#define M_2_PI 0x1.45f306dc9c883p-1 +#define M_2_SQRTPI 0x1.20dd750429b6dp+0 +#define M_SQRT2 0x1.6a09e667f3bcdp+0 +#define M_SQRT1_2 0x1.6a09e667f3bcdp-1 + +#ifdef cl_khr_fp16 + +#define HALF_DIG 3 +#define HALF_MANT_DIG 11 +#define HALF_MAX_10_EXP +4 +#define HALF_MAX_EXP +16 +#define HALF_MIN_10_EXP -4 +#define HALF_MIN_EXP -13 +#define HALF_RADIX 2 +#define HALF_MAX ((0x1.ffcp15h)) +#define HALF_MIN ((0x1.0p-14h)) +#define HALF_EPSILON ((0x1.0p-10h)) + +#define M_E_H 2.71828182845904523536028747135266250h +#define M_LOG2E_H 1.44269504088896340735992468100189214h +#define M_LOG10E_H 0.434294481903251827651128918916605082h +#define M_LN2_H 0.693147180559945309417232121458176568h +#define M_LN10_H 2.30258509299404568401799145468436421h +#define M_PI_H 3.14159265358979323846264338327950288h +#define M_PI_2_H 1.57079632679489661923132169163975144h +#define M_PI_4_H 0.785398163397448309615660845819875721h +#define M_1_PI_H 0.318309886183790671537767526745028724h +#define M_2_PI_H 0.636619772367581343075535053490057448h +#define M_2_SQRTPI_H 1.12837916709551257389615890312154517h +#define M_SQRT2_H 1.41421356237309504880168872420969808h +#define M_SQRT1_2_H 0.707106781186547524400844362104849039h + +#endif //cl_khr_fp16 + +#define CHAR_BIT 8 +#define SCHAR_MAX 127 +#define SCHAR_MIN (-128) +#define UCHAR_MAX 255 +#define CHAR_MAX SCHAR_MAX +#define CHAR_MIN SCHAR_MIN +#define USHRT_MAX 65535 +#define SHRT_MAX 32767 +#define SHRT_MIN (-32768) +#define UINT_MAX 0xffffffff +#define INT_MAX 2147483647 +#define INT_MIN (-2147483647-1) +#define ULONG_MAX 0xffffffffffffffffUL +#define LONG_MAX 0x7fffffffffffffffL +#define LONG_MIN (-0x7fffffffffffffffL-1) + +// OpenCL v1.1 s6.11.8, v1.2 s6.12.8, v2.0 s6.13.8 - Synchronization Functions + +// Flag type and values for barrier, mem_fence, read_mem_fence, write_mem_fence +typedef uint cl_mem_fence_flags; + +/** + * Queue a memory fence to ensure correct + * ordering of memory operations to local memory + */ +#define CLK_LOCAL_MEM_FENCE 0x01 + +/** + * Queue a memory fence to ensure correct + * ordering of memory operations to global memory + */ +#define CLK_GLOBAL_MEM_FENCE 0x02 + +#if defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ >= CL_VERSION_2_0) + +typedef enum memory_scope { + memory_scope_work_item = __OPENCL_MEMORY_SCOPE_WORK_ITEM, + memory_scope_work_group = __OPENCL_MEMORY_SCOPE_WORK_GROUP, + memory_scope_device = __OPENCL_MEMORY_SCOPE_DEVICE, + memory_scope_all_svm_devices = __OPENCL_MEMORY_SCOPE_ALL_SVM_DEVICES, +#if defined(cl_intel_subgroups) || defined(cl_khr_subgroups) + memory_scope_sub_group = __OPENCL_MEMORY_SCOPE_SUB_GROUP +#endif +} memory_scope; + +/** + * Queue a memory fence to ensure correct ordering of memory + * operations between work-items of a work-group to + * image memory. + */ +#define CLK_IMAGE_MEM_FENCE 0x04 + +#ifndef ATOMIC_VAR_INIT +#define ATOMIC_VAR_INIT(x) (x) +#endif //ATOMIC_VAR_INIT +#define ATOMIC_FLAG_INIT 0 + +// enum values aligned with what clang uses in EmitAtomicExpr() +typedef enum memory_order +{ + memory_order_relaxed = __ATOMIC_RELAXED, + memory_order_acquire = __ATOMIC_ACQUIRE, + memory_order_release = __ATOMIC_RELEASE, + memory_order_acq_rel = __ATOMIC_ACQ_REL, + memory_order_seq_cst = __ATOMIC_SEQ_CST +} memory_order; + +#endif // defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ >= CL_VERSION_2_0) + +// OpenCL v1.1 s6.11.3, v1.2 s6.12.14, v2.0 s6.13.14 - Image Read and Write Functions + +// These values need to match the runtime equivalent +// +// Addressing Mode. +// +#define CLK_ADDRESS_NONE 0 +#define CLK_ADDRESS_CLAMP_TO_EDGE 2 +#define CLK_ADDRESS_CLAMP 4 +#define CLK_ADDRESS_REPEAT 6 +#define CLK_ADDRESS_MIRRORED_REPEAT 8 + +// +// Coordination Normalization +// +#define CLK_NORMALIZED_COORDS_FALSE 0 +#define CLK_NORMALIZED_COORDS_TRUE 1 + +// +// Filtering Mode. +// +#define CLK_FILTER_NEAREST 0x10 +#define CLK_FILTER_LINEAR 0x20 + +#ifdef cl_khr_gl_msaa_sharing +#pragma OPENCL EXTENSION cl_khr_gl_msaa_sharing : enable +#endif //cl_khr_gl_msaa_sharing + +// +// Channel Datatype. +// +#define CLK_SNORM_INT8 0x10D0 +#define CLK_SNORM_INT16 0x10D1 +#define CLK_UNORM_INT8 0x10D2 +#define CLK_UNORM_INT16 0x10D3 +#define CLK_UNORM_SHORT_565 0x10D4 +#define CLK_UNORM_SHORT_555 0x10D5 +#define CLK_UNORM_INT_101010 0x10D6 +#define CLK_SIGNED_INT8 0x10D7 +#define CLK_SIGNED_INT16 0x10D8 +#define CLK_SIGNED_INT32 0x10D9 +#define CLK_UNSIGNED_INT8 0x10DA +#define CLK_UNSIGNED_INT16 0x10DB +#define CLK_UNSIGNED_INT32 0x10DC +#define CLK_HALF_FLOAT 0x10DD +#define CLK_FLOAT 0x10DE +#define CLK_UNORM_INT24 0x10DF + +// Channel order, numbering must be aligned with cl_channel_order in cl.h +// +#define CLK_R 0x10B0 +#define CLK_A 0x10B1 +#define CLK_RG 0x10B2 +#define CLK_RA 0x10B3 +#define CLK_RGB 0x10B4 +#define CLK_RGBA 0x10B5 +#define CLK_BGRA 0x10B6 +#define CLK_ARGB 0x10B7 +#define CLK_INTENSITY 0x10B8 +#define CLK_LUMINANCE 0x10B9 +#define CLK_Rx 0x10BA +#define CLK_RGx 0x10BB +#define CLK_RGBx 0x10BC +#define CLK_DEPTH 0x10BD +#define CLK_DEPTH_STENCIL 0x10BE +#if __OPENCL_C_VERSION__ >= CL_VERSION_2_0 +#define CLK_sRGB 0x10BF +#define CLK_sRGBx 0x10C0 +#define CLK_sRGBA 0x10C1 +#define CLK_sBGRA 0x10C2 +#define CLK_ABGR 0x10C3 +#endif //__OPENCL_C_VERSION__ >= CL_VERSION_2_0 + +// OpenCL v2.0 s6.13.16 - Pipe Functions +#if defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ >= CL_VERSION_2_0) +#define CLK_NULL_RESERVE_ID (__builtin_astype(((void*)(__SIZE_MAX__)), reserve_id_t)) + +// OpenCL v2.0 s6.13.17 - Enqueue Kernels +#define CL_COMPLETE 0x0 +#define CL_RUNNING 0x1 +#define CL_SUBMITTED 0x2 +#define CL_QUEUED 0x3 + +#define CLK_SUCCESS 0 +#define CLK_ENQUEUE_FAILURE -101 +#define CLK_INVALID_QUEUE -102 +#define CLK_INVALID_NDRANGE -160 +#define CLK_INVALID_EVENT_WAIT_LIST -57 +#define CLK_DEVICE_QUEUE_FULL -161 +#define CLK_INVALID_ARG_SIZE -51 +#define CLK_EVENT_ALLOCATION_FAILURE -100 +#define CLK_OUT_OF_RESOURCES -5 + +#define CLK_NULL_QUEUE 0 +#define CLK_NULL_EVENT (__builtin_astype(((__SIZE_MAX__)), clk_event_t)) + +// execution model related definitions +#define CLK_ENQUEUE_FLAGS_NO_WAIT 0x0 +#define CLK_ENQUEUE_FLAGS_WAIT_KERNEL 0x1 +#define CLK_ENQUEUE_FLAGS_WAIT_WORK_GROUP 0x2 + +typedef int kernel_enqueue_flags_t; +typedef int clk_profiling_info; + +// Profiling info name (see capture_event_profiling_info) +#define CLK_PROFILING_COMMAND_EXEC_TIME 0x1 + +#define MAX_WORK_DIM 3 + +typedef struct { + unsigned int workDimension; + size_t globalWorkOffset[MAX_WORK_DIM]; + size_t globalWorkSize[MAX_WORK_DIM]; + size_t localWorkSize[MAX_WORK_DIM]; +} ndrange_t; + +#endif // defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ >= CL_VERSION_2_0) + +/** + * OpenCL v1.1/1.2/2.0 s6.2.4.2 - as_type operators + * Reinterprets a data type as another data type of the same size + */ +#define as_char(x) __builtin_astype((x), char) +#define as_char2(x) __builtin_astype((x), char2) +#define as_char3(x) __builtin_astype((x), char3) +#define as_char4(x) __builtin_astype((x), char4) +#define as_char8(x) __builtin_astype((x), char8) +#define as_char16(x) __builtin_astype((x), char16) + +#define as_uchar(x) __builtin_astype((x), uchar) +#define as_uchar2(x) __builtin_astype((x), uchar2) +#define as_uchar3(x) __builtin_astype((x), uchar3) +#define as_uchar4(x) __builtin_astype((x), uchar4) +#define as_uchar8(x) __builtin_astype((x), uchar8) +#define as_uchar16(x) __builtin_astype((x), uchar16) + +#define as_short(x) __builtin_astype((x), short) +#define as_short2(x) __builtin_astype((x), short2) +#define as_short3(x) __builtin_astype((x), short3) +#define as_short4(x) __builtin_astype((x), short4) +#define as_short8(x) __builtin_astype((x), short8) +#define as_short16(x) __builtin_astype((x), short16) + +#define as_ushort(x) __builtin_astype((x), ushort) +#define as_ushort2(x) __builtin_astype((x), ushort2) +#define as_ushort3(x) __builtin_astype((x), ushort3) +#define as_ushort4(x) __builtin_astype((x), ushort4) +#define as_ushort8(x) __builtin_astype((x), ushort8) +#define as_ushort16(x) __builtin_astype((x), ushort16) + +#define as_int(x) __builtin_astype((x), int) +#define as_int2(x) __builtin_astype((x), int2) +#define as_int3(x) __builtin_astype((x), int3) +#define as_int4(x) __builtin_astype((x), int4) +#define as_int8(x) __builtin_astype((x), int8) +#define as_int16(x) __builtin_astype((x), int16) + +#define as_uint(x) __builtin_astype((x), uint) +#define as_uint2(x) __builtin_astype((x), uint2) +#define as_uint3(x) __builtin_astype((x), uint3) +#define as_uint4(x) __builtin_astype((x), uint4) +#define as_uint8(x) __builtin_astype((x), uint8) +#define as_uint16(x) __builtin_astype((x), uint16) + +#define as_long(x) __builtin_astype((x), long) +#define as_long2(x) __builtin_astype((x), long2) +#define as_long3(x) __builtin_astype((x), long3) +#define as_long4(x) __builtin_astype((x), long4) +#define as_long8(x) __builtin_astype((x), long8) +#define as_long16(x) __builtin_astype((x), long16) + +#define as_ulong(x) __builtin_astype((x), ulong) +#define as_ulong2(x) __builtin_astype((x), ulong2) +#define as_ulong3(x) __builtin_astype((x), ulong3) +#define as_ulong4(x) __builtin_astype((x), ulong4) +#define as_ulong8(x) __builtin_astype((x), ulong8) +#define as_ulong16(x) __builtin_astype((x), ulong16) + +#define as_float(x) __builtin_astype((x), float) +#define as_float2(x) __builtin_astype((x), float2) +#define as_float3(x) __builtin_astype((x), float3) +#define as_float4(x) __builtin_astype((x), float4) +#define as_float8(x) __builtin_astype((x), float8) +#define as_float16(x) __builtin_astype((x), float16) + +#ifdef cl_khr_fp64 +#define as_double(x) __builtin_astype((x), double) +#define as_double2(x) __builtin_astype((x), double2) +#define as_double3(x) __builtin_astype((x), double3) +#define as_double4(x) __builtin_astype((x), double4) +#define as_double8(x) __builtin_astype((x), double8) +#define as_double16(x) __builtin_astype((x), double16) +#endif // cl_khr_fp64 + +#ifdef cl_khr_fp16 +#define as_half(x) __builtin_astype((x), half) +#define as_half2(x) __builtin_astype((x), half2) +#define as_half3(x) __builtin_astype((x), half3) +#define as_half4(x) __builtin_astype((x), half4) +#define as_half8(x) __builtin_astype((x), half8) +#define as_half16(x) __builtin_astype((x), half16) +#endif // cl_khr_fp16 + +// OpenCL v1.1 s6.9, v1.2/2.0 s6.10 - Function qualifiers + +#define __kernel_exec(X, typen) __kernel \ + __attribute__((work_group_size_hint(X, 1, 1))) \ + __attribute__((vec_type_hint(typen))) + +#define kernel_exec(X, typen) __kernel \ + __attribute__((work_group_size_hint(X, 1, 1))) \ + __attribute__((vec_type_hint(typen))) + +#if defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ >= CL_VERSION_1_2) +// OpenCL v1.2 s6.12.13, v2.0 s6.13.13 - printf + +int printf(__constant const char* st, ...) __attribute__((format(printf, 1, 2))); +#endif + +#ifdef cl_intel_device_side_avc_motion_estimation +#pragma OPENCL EXTENSION cl_intel_device_side_avc_motion_estimation : begin + +#define CLK_AVC_ME_MAJOR_16x16_INTEL 0x0 +#define CLK_AVC_ME_MAJOR_16x8_INTEL 0x1 +#define CLK_AVC_ME_MAJOR_8x16_INTEL 0x2 +#define CLK_AVC_ME_MAJOR_8x8_INTEL 0x3 + +#define CLK_AVC_ME_MINOR_8x8_INTEL 0x0 +#define CLK_AVC_ME_MINOR_8x4_INTEL 0x1 +#define CLK_AVC_ME_MINOR_4x8_INTEL 0x2 +#define CLK_AVC_ME_MINOR_4x4_INTEL 0x3 + +#define CLK_AVC_ME_MAJOR_FORWARD_INTEL 0x0 +#define CLK_AVC_ME_MAJOR_BACKWARD_INTEL 0x1 +#define CLK_AVC_ME_MAJOR_BIDIRECTIONAL_INTEL 0x2 + +#define CLK_AVC_ME_PARTITION_MASK_ALL_INTEL 0x0 +#define CLK_AVC_ME_PARTITION_MASK_16x16_INTEL 0x7E +#define CLK_AVC_ME_PARTITION_MASK_16x8_INTEL 0x7D +#define CLK_AVC_ME_PARTITION_MASK_8x16_INTEL 0x7B +#define CLK_AVC_ME_PARTITION_MASK_8x8_INTEL 0x77 +#define CLK_AVC_ME_PARTITION_MASK_8x4_INTEL 0x6F +#define CLK_AVC_ME_PARTITION_MASK_4x8_INTEL 0x5F +#define CLK_AVC_ME_PARTITION_MASK_4x4_INTEL 0x3F + +#define CLK_AVC_ME_SLICE_TYPE_PRED_INTEL 0x0 +#define CLK_AVC_ME_SLICE_TYPE_BPRED_INTEL 0x1 +#define CLK_AVC_ME_SLICE_TYPE_INTRA_INTEL 0x2 + +#define CLK_AVC_ME_SEARCH_WINDOW_EXHAUSTIVE_INTEL 0x0 +#define CLK_AVC_ME_SEARCH_WINDOW_SMALL_INTEL 0x1 +#define CLK_AVC_ME_SEARCH_WINDOW_TINY_INTEL 0x2 +#define CLK_AVC_ME_SEARCH_WINDOW_EXTRA_TINY_INTEL 0x3 +#define CLK_AVC_ME_SEARCH_WINDOW_DIAMOND_INTEL 0x4 +#define CLK_AVC_ME_SEARCH_WINDOW_LARGE_DIAMOND_INTEL 0x5 +#define CLK_AVC_ME_SEARCH_WINDOW_RESERVED0_INTEL 0x6 +#define CLK_AVC_ME_SEARCH_WINDOW_RESERVED1_INTEL 0x7 +#define CLK_AVC_ME_SEARCH_WINDOW_CUSTOM_INTEL 0x8 + +#define CLK_AVC_ME_SAD_ADJUST_MODE_NONE_INTEL 0x0 +#define CLK_AVC_ME_SAD_ADJUST_MODE_HAAR_INTEL 0x2 + +#define CLK_AVC_ME_SUBPIXEL_MODE_INTEGER_INTEL 0x0 +#define CLK_AVC_ME_SUBPIXEL_MODE_HPEL_INTEL 0x1 +#define CLK_AVC_ME_SUBPIXEL_MODE_QPEL_INTEL 0x3 + +#define CLK_AVC_ME_COST_PRECISION_QPEL_INTEL 0x0 +#define CLK_AVC_ME_COST_PRECISION_HPEL_INTEL 0x1 +#define CLK_AVC_ME_COST_PRECISION_PEL_INTEL 0x2 +#define CLK_AVC_ME_COST_PRECISION_DPEL_INTEL 0x3 + +#define CLK_AVC_ME_BIDIR_WEIGHT_QUARTER_INTEL 0x10 +#define CLK_AVC_ME_BIDIR_WEIGHT_THIRD_INTEL 0x15 +#define CLK_AVC_ME_BIDIR_WEIGHT_HALF_INTEL 0x20 +#define CLK_AVC_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL 0x2B +#define CLK_AVC_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL 0x30 + +#define CLK_AVC_ME_BORDER_REACHED_LEFT_INTEL 0x0 +#define CLK_AVC_ME_BORDER_REACHED_RIGHT_INTEL 0x2 +#define CLK_AVC_ME_BORDER_REACHED_TOP_INTEL 0x4 +#define CLK_AVC_ME_BORDER_REACHED_BOTTOM_INTEL 0x8 + +#define CLK_AVC_ME_INTRA_16x16_INTEL 0x0 +#define CLK_AVC_ME_INTRA_8x8_INTEL 0x1 +#define CLK_AVC_ME_INTRA_4x4_INTEL 0x2 + +#define CLK_AVC_ME_SKIP_BLOCK_PARTITION_16x16_INTEL 0x0 +#define CLK_AVC_ME_SKIP_BLOCK_PARTITION_8x8_INTEL 0x4000 + +#define CLK_AVC_ME_SKIP_BLOCK_16x16_FORWARD_ENABLE_INTEL (0x1 << 24) +#define CLK_AVC_ME_SKIP_BLOCK_16x16_BACKWARD_ENABLE_INTEL (0x2 << 24) +#define CLK_AVC_ME_SKIP_BLOCK_16x16_DUAL_ENABLE_INTEL (0x3 << 24) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_FORWARD_ENABLE_INTEL (0x55 << 24) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_BACKWARD_ENABLE_INTEL (0xAA << 24) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_DUAL_ENABLE_INTEL (0xFF << 24) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_0_FORWARD_ENABLE_INTEL (0x1 << 24) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_0_BACKWARD_ENABLE_INTEL (0x2 << 24) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_1_FORWARD_ENABLE_INTEL (0x1 << 26) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_1_BACKWARD_ENABLE_INTEL (0x2 << 26) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_2_FORWARD_ENABLE_INTEL (0x1 << 28) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_2_BACKWARD_ENABLE_INTEL (0x2 << 28) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_3_FORWARD_ENABLE_INTEL (0x1 << 30) +#define CLK_AVC_ME_SKIP_BLOCK_8x8_3_BACKWARD_ENABLE_INTEL (0x2 << 30) + +#define CLK_AVC_ME_BLOCK_BASED_SKIP_4x4_INTEL 0x00 +#define CLK_AVC_ME_BLOCK_BASED_SKIP_8x8_INTEL 0x80 + +#define CLK_AVC_ME_INTRA_LUMA_PARTITION_MASK_ALL_INTEL 0x0 +#define CLK_AVC_ME_INTRA_LUMA_PARTITION_MASK_16x16_INTEL 0x6 +#define CLK_AVC_ME_INTRA_LUMA_PARTITION_MASK_8x8_INTEL 0x5 +#define CLK_AVC_ME_INTRA_LUMA_PARTITION_MASK_4x4_INTEL 0x3 + +#define CLK_AVC_ME_INTRA_NEIGHBOR_LEFT_MASK_ENABLE_INTEL 0x60 +#define CLK_AVC_ME_INTRA_NEIGHBOR_UPPER_MASK_ENABLE_INTEL 0x10 +#define CLK_AVC_ME_INTRA_NEIGHBOR_UPPER_RIGHT_MASK_ENABLE_INTEL 0x8 +#define CLK_AVC_ME_INTRA_NEIGHBOR_UPPER_LEFT_MASK_ENABLE_INTEL 0x4 + +#define CLK_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL 0x0 +#define CLK_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 +#define CLK_AVC_ME_LUMA_PREDICTOR_MODE_DC_INTEL 0x2 +#define CLK_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL 0x3 +#define CLK_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL 0x4 +#define CLK_AVC_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL 0x4 +#define CLK_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL 0x5 +#define CLK_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL 0x6 +#define CLK_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL 0x7 +#define CLK_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL 0x8 +#define CLK_AVC_ME_CHROMA_PREDICTOR_MODE_DC_INTEL 0x0 +#define CLK_AVC_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 +#define CLK_AVC_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL 0x2 +#define CLK_AVC_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL 0x3 + +#define CLK_AVC_ME_FRAME_FORWARD_INTEL 0x1 +#define CLK_AVC_ME_FRAME_BACKWARD_INTEL 0x2 +#define CLK_AVC_ME_FRAME_DUAL_INTEL 0x3 + +#define CLK_AVC_ME_INTERLACED_SCAN_TOP_FIELD_INTEL 0x0 +#define CLK_AVC_ME_INTERLACED_SCAN_BOTTOM_FIELD_INTEL 0x1 + +#define CLK_AVC_ME_INITIALIZE_INTEL 0x0 + +#define CLK_AVC_IME_PAYLOAD_INITIALIZE_INTEL 0x0 +#define CLK_AVC_REF_PAYLOAD_INITIALIZE_INTEL 0x0 +#define CLK_AVC_SIC_PAYLOAD_INITIALIZE_INTEL 0x0 + +#define CLK_AVC_IME_RESULT_INITIALIZE_INTEL 0x0 +#define CLK_AVC_REF_RESULT_INITIALIZE_INTEL 0x0 +#define CLK_AVC_SIC_RESULT_INITIALIZE_INTEL 0x0 + +#define CLK_AVC_IME_RESULT_SINGLE_REFERENCE_STREAMOUT_INITIALIZE_INTEL 0x0 +#define CLK_AVC_IME_RESULT_SINGLE_REFERENCE_STREAMIN_INITIALIZE_INTEL 0x0 +#define CLK_AVC_IME_RESULT_DUAL_REFERENCE_STREAMOUT_INITIALIZE_INTEL 0x0 +#define CLK_AVC_IME_RESULT_DUAL_REFERENCE_STREAMIN_INITIALIZE_INTEL 0x0 + +#pragma OPENCL EXTENSION cl_intel_device_side_avc_motion_estimation : end +#endif // cl_intel_device_side_avc_motion_estimation + +// Disable any extensions we may have enabled previously. +#pragma OPENCL EXTENSION all : disable + +#endif //_OPENCL_BASE_H_ #if defined(__opencl_c_images) #ifndef cl_khr_depth_images @@ -6490,27 +7198,27 @@ half16 __ovld __cnfn acosh(half16); /** * Compute acos (x) / PI. */ -float __ovld __cnfn acospi(float); -float2 __ovld __cnfn acospi(float2); -float3 __ovld __cnfn acospi(float3); -float4 __ovld __cnfn acospi(float4); -float8 __ovld __cnfn acospi(float8); -float16 __ovld __cnfn acospi(float16); +float __ovld __cnfn acospi(float x); +float2 __ovld __cnfn acospi(float2 x); +float3 __ovld __cnfn acospi(float3 x); +float4 __ovld __cnfn acospi(float4 x); +float8 __ovld __cnfn acospi(float8 x); +float16 __ovld __cnfn acospi(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn acospi(double); -double2 __ovld __cnfn acospi(double2); -double3 __ovld __cnfn acospi(double3); -double4 __ovld __cnfn acospi(double4); -double8 __ovld __cnfn acospi(double8); -double16 __ovld __cnfn acospi(double16); +double __ovld __cnfn acospi(double x); +double2 __ovld __cnfn acospi(double2 x); +double3 __ovld __cnfn acospi(double3 x); +double4 __ovld __cnfn acospi(double4 x); +double8 __ovld __cnfn acospi(double8 x); +double16 __ovld __cnfn acospi(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn acospi(half); -half2 __ovld __cnfn acospi(half2); -half3 __ovld __cnfn acospi(half3); -half4 __ovld __cnfn acospi(half4); -half8 __ovld __cnfn acospi(half8); -half16 __ovld __cnfn acospi(half16); +half __ovld __cnfn acospi(half x); +half2 __ovld __cnfn acospi(half2 x); +half3 __ovld __cnfn acospi(half3 x); +half4 __ovld __cnfn acospi(half4 x); +half8 __ovld __cnfn acospi(half8 x); +half16 __ovld __cnfn acospi(half16 x); #endif //cl_khr_fp16 /** @@ -6568,27 +7276,27 @@ half16 __ovld __cnfn asinh(half16); /** * Compute asin (x) / PI. */ -float __ovld __cnfn asinpi(float); -float2 __ovld __cnfn asinpi(float2); -float3 __ovld __cnfn asinpi(float3); -float4 __ovld __cnfn asinpi(float4); -float8 __ovld __cnfn asinpi(float8); -float16 __ovld __cnfn asinpi(float16); +float __ovld __cnfn asinpi(float x); +float2 __ovld __cnfn asinpi(float2 x); +float3 __ovld __cnfn asinpi(float3 x); +float4 __ovld __cnfn asinpi(float4 x); +float8 __ovld __cnfn asinpi(float8 x); +float16 __ovld __cnfn asinpi(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn asinpi(double); -double2 __ovld __cnfn asinpi(double2); -double3 __ovld __cnfn asinpi(double3); -double4 __ovld __cnfn asinpi(double4); -double8 __ovld __cnfn asinpi(double8); -double16 __ovld __cnfn asinpi(double16); +double __ovld __cnfn asinpi(double x); +double2 __ovld __cnfn asinpi(double2 x); +double3 __ovld __cnfn asinpi(double3 x); +double4 __ovld __cnfn asinpi(double4 x); +double8 __ovld __cnfn asinpi(double8 x); +double16 __ovld __cnfn asinpi(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn asinpi(half); -half2 __ovld __cnfn asinpi(half2); -half3 __ovld __cnfn asinpi(half3); -half4 __ovld __cnfn asinpi(half4); -half8 __ovld __cnfn asinpi(half8); -half16 __ovld __cnfn asinpi(half16); +half __ovld __cnfn asinpi(half x); +half2 __ovld __cnfn asinpi(half2 x); +half3 __ovld __cnfn asinpi(half3 x); +half4 __ovld __cnfn asinpi(half4 x); +half8 __ovld __cnfn asinpi(half8 x); +half16 __ovld __cnfn asinpi(half16 x); #endif //cl_khr_fp16 /** @@ -6620,27 +7328,27 @@ half16 __ovld __cnfn atan(half16); /** * Arc tangent of y / x. */ -float __ovld __cnfn atan2(float, float); -float2 __ovld __cnfn atan2(float2, float2); -float3 __ovld __cnfn atan2(float3, float3); -float4 __ovld __cnfn atan2(float4, float4); -float8 __ovld __cnfn atan2(float8, float8); -float16 __ovld __cnfn atan2(float16, float16); +float __ovld __cnfn atan2(float, float x); +float2 __ovld __cnfn atan2(float2, float2 x); +float3 __ovld __cnfn atan2(float3, float3 x); +float4 __ovld __cnfn atan2(float4, float4 x); +float8 __ovld __cnfn atan2(float8, float8 x); +float16 __ovld __cnfn atan2(float16, float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn atan2(double, double); -double2 __ovld __cnfn atan2(double2, double2); -double3 __ovld __cnfn atan2(double3, double3); -double4 __ovld __cnfn atan2(double4, double4); -double8 __ovld __cnfn atan2(double8, double8); -double16 __ovld __cnfn atan2(double16, double16); +double __ovld __cnfn atan2(double, double x); +double2 __ovld __cnfn atan2(double2, double2 x); +double3 __ovld __cnfn atan2(double3, double3 x); +double4 __ovld __cnfn atan2(double4, double4 x); +double8 __ovld __cnfn atan2(double8, double8 x); +double16 __ovld __cnfn atan2(double16, double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn atan2(half, half); -half2 __ovld __cnfn atan2(half2, half2); -half3 __ovld __cnfn atan2(half3, half3); -half4 __ovld __cnfn atan2(half4, half4); -half8 __ovld __cnfn atan2(half8, half8); -half16 __ovld __cnfn atan2(half16, half16); +half __ovld __cnfn atan2(half, half x); +half2 __ovld __cnfn atan2(half2, half2 x); +half3 __ovld __cnfn atan2(half3, half3 x); +half4 __ovld __cnfn atan2(half4, half4 x); +half8 __ovld __cnfn atan2(half8, half8 x); +half16 __ovld __cnfn atan2(half16, half16 x); #endif //cl_khr_fp16 /** @@ -6672,53 +7380,53 @@ half16 __ovld __cnfn atanh(half16); /** * Compute atan (x) / PI. */ -float __ovld __cnfn atanpi(float); -float2 __ovld __cnfn atanpi(float2); -float3 __ovld __cnfn atanpi(float3); -float4 __ovld __cnfn atanpi(float4); -float8 __ovld __cnfn atanpi(float8); -float16 __ovld __cnfn atanpi(float16); +float __ovld __cnfn atanpi(float x); +float2 __ovld __cnfn atanpi(float2 x); +float3 __ovld __cnfn atanpi(float3 x); +float4 __ovld __cnfn atanpi(float4 x); +float8 __ovld __cnfn atanpi(float8 x); +float16 __ovld __cnfn atanpi(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn atanpi(double); -double2 __ovld __cnfn atanpi(double2); -double3 __ovld __cnfn atanpi(double3); -double4 __ovld __cnfn atanpi(double4); -double8 __ovld __cnfn atanpi(double8); -double16 __ovld __cnfn atanpi(double16); +double __ovld __cnfn atanpi(double x); +double2 __ovld __cnfn atanpi(double2 x); +double3 __ovld __cnfn atanpi(double3 x); +double4 __ovld __cnfn atanpi(double4 x); +double8 __ovld __cnfn atanpi(double8 x); +double16 __ovld __cnfn atanpi(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn atanpi(half); -half2 __ovld __cnfn atanpi(half2); -half3 __ovld __cnfn atanpi(half3); -half4 __ovld __cnfn atanpi(half4); -half8 __ovld __cnfn atanpi(half8); -half16 __ovld __cnfn atanpi(half16); +half __ovld __cnfn atanpi(half x); +half2 __ovld __cnfn atanpi(half2 x); +half3 __ovld __cnfn atanpi(half3 x); +half4 __ovld __cnfn atanpi(half4 x); +half8 __ovld __cnfn atanpi(half8 x); +half16 __ovld __cnfn atanpi(half16 x); #endif //cl_khr_fp16 /** * Compute atan2 (y, x) / PI. */ -float __ovld __cnfn atan2pi(float, float); -float2 __ovld __cnfn atan2pi(float2, float2); -float3 __ovld __cnfn atan2pi(float3, float3); -float4 __ovld __cnfn atan2pi(float4, float4); -float8 __ovld __cnfn atan2pi(float8, float8); -float16 __ovld __cnfn atan2pi(float16, float16); +float __ovld __cnfn atan2pi(float, float x); +float2 __ovld __cnfn atan2pi(float2, float2 x); +float3 __ovld __cnfn atan2pi(float3, float3 x); +float4 __ovld __cnfn atan2pi(float4, float4 x); +float8 __ovld __cnfn atan2pi(float8, float8 x); +float16 __ovld __cnfn atan2pi(float16, float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn atan2pi(double, double); -double2 __ovld __cnfn atan2pi(double2, double2); -double3 __ovld __cnfn atan2pi(double3, double3); -double4 __ovld __cnfn atan2pi(double4, double4); -double8 __ovld __cnfn atan2pi(double8, double8); -double16 __ovld __cnfn atan2pi(double16, double16); +double __ovld __cnfn atan2pi(double, double x); +double2 __ovld __cnfn atan2pi(double2, double2 x); +double3 __ovld __cnfn atan2pi(double3, double3 x); +double4 __ovld __cnfn atan2pi(double4, double4 x); +double8 __ovld __cnfn atan2pi(double8, double8 x); +double16 __ovld __cnfn atan2pi(double16, double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn atan2pi(half, half); -half2 __ovld __cnfn atan2pi(half2, half2); -half3 __ovld __cnfn atan2pi(half3, half3); -half4 __ovld __cnfn atan2pi(half4, half4); -half8 __ovld __cnfn atan2pi(half8, half8); -half16 __ovld __cnfn atan2pi(half16, half16); +half __ovld __cnfn atan2pi(half, half x); +half2 __ovld __cnfn atan2pi(half2, half2 x); +half3 __ovld __cnfn atan2pi(half3, half3 x); +half4 __ovld __cnfn atan2pi(half4, half4 x); +half8 __ovld __cnfn atan2pi(half8, half8 x); +half16 __ovld __cnfn atan2pi(half16, half16 x); #endif //cl_khr_fp16 /** @@ -6777,27 +7485,27 @@ half16 __ovld __cnfn ceil(half16); /** * Returns x with its sign changed to match the sign of y. */ -float __ovld __cnfn copysign(float, float); -float2 __ovld __cnfn copysign(float2, float2); -float3 __ovld __cnfn copysign(float3, float3); -float4 __ovld __cnfn copysign(float4, float4); -float8 __ovld __cnfn copysign(float8, float8); -float16 __ovld __cnfn copysign(float16, float16); +float __ovld __cnfn copysign(float, float ); +float2 __ovld __cnfn copysign(float2, float2 ); +float3 __ovld __cnfn copysign(float3, float3 ); +float4 __ovld __cnfn copysign(float4, float4 ); +float8 __ovld __cnfn copysign(float8, float8 ); +float16 __ovld __cnfn copysign(float16, float16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn copysign(double, double); -double2 __ovld __cnfn copysign(double2, double2); -double3 __ovld __cnfn copysign(double3, double3); -double4 __ovld __cnfn copysign(double4, double4); -double8 __ovld __cnfn copysign(double8, double8); -double16 __ovld __cnfn copysign(double16, double16); +double __ovld __cnfn copysign(double, double ); +double2 __ovld __cnfn copysign(double2, double2 ); +double3 __ovld __cnfn copysign(double3, double3 ); +double4 __ovld __cnfn copysign(double4, double4 ); +double8 __ovld __cnfn copysign(double8, double8 ); +double16 __ovld __cnfn copysign(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn copysign(half, half); -half2 __ovld __cnfn copysign(half2, half2); -half3 __ovld __cnfn copysign(half3, half3); -half4 __ovld __cnfn copysign(half4, half4); -half8 __ovld __cnfn copysign(half8, half8); -half16 __ovld __cnfn copysign(half16, half16); +half __ovld __cnfn copysign(half, half ); +half2 __ovld __cnfn copysign(half2, half2 ); +half3 __ovld __cnfn copysign(half3, half3 ); +half4 __ovld __cnfn copysign(half4, half4 ); +half8 __ovld __cnfn copysign(half8, half8 ); +half16 __ovld __cnfn copysign(half16, half16 ); #endif //cl_khr_fp16 /** @@ -6855,27 +7563,27 @@ half16 __ovld __cnfn cosh(half16); /** * Compute cos (PI * x). */ -float __ovld __cnfn cospi(float); -float2 __ovld __cnfn cospi(float2); -float3 __ovld __cnfn cospi(float3); -float4 __ovld __cnfn cospi(float4); -float8 __ovld __cnfn cospi(float8); -float16 __ovld __cnfn cospi(float16); +float __ovld __cnfn cospi(float x); +float2 __ovld __cnfn cospi(float2 x); +float3 __ovld __cnfn cospi(float3 x); +float4 __ovld __cnfn cospi(float4 x); +float8 __ovld __cnfn cospi(float8 x); +float16 __ovld __cnfn cospi(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn cospi(double); -double2 __ovld __cnfn cospi(double2); -double3 __ovld __cnfn cospi(double3); -double4 __ovld __cnfn cospi(double4); -double8 __ovld __cnfn cospi(double8); -double16 __ovld __cnfn cospi(double16); +double __ovld __cnfn cospi(double x); +double2 __ovld __cnfn cospi(double2 x); +double3 __ovld __cnfn cospi(double3 x); +double4 __ovld __cnfn cospi(double4 x); +double8 __ovld __cnfn cospi(double8 x); +double16 __ovld __cnfn cospi(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn cospi(half); -half2 __ovld __cnfn cospi(half2); -half3 __ovld __cnfn cospi(half3); -half4 __ovld __cnfn cospi(half4); -half8 __ovld __cnfn cospi(half8); -half16 __ovld __cnfn cospi(half16); +half __ovld __cnfn cospi(half x); +half2 __ovld __cnfn cospi(half2 x); +half3 __ovld __cnfn cospi(half3 x); +half4 __ovld __cnfn cospi(half4 x); +half8 __ovld __cnfn cospi(half8 x); +half16 __ovld __cnfn cospi(half16 x); #endif //cl_khr_fp16 /** @@ -6934,27 +7642,27 @@ half16 __ovld __cnfn erf(half16); /** * Compute the base e exponential function of x. */ -float __ovld __cnfn exp(float); -float2 __ovld __cnfn exp(float2); -float3 __ovld __cnfn exp(float3); -float4 __ovld __cnfn exp(float4); -float8 __ovld __cnfn exp(float8); -float16 __ovld __cnfn exp(float16); +float __ovld __cnfn exp(float x); +float2 __ovld __cnfn exp(float2 x); +float3 __ovld __cnfn exp(float3 x); +float4 __ovld __cnfn exp(float4 x); +float8 __ovld __cnfn exp(float8 x); +float16 __ovld __cnfn exp(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn exp(double); -double2 __ovld __cnfn exp(double2); -double3 __ovld __cnfn exp(double3); -double4 __ovld __cnfn exp(double4); -double8 __ovld __cnfn exp(double8); -double16 __ovld __cnfn exp(double16); +double __ovld __cnfn exp(double x); +double2 __ovld __cnfn exp(double2 x); +double3 __ovld __cnfn exp(double3 x); +double4 __ovld __cnfn exp(double4 x); +double8 __ovld __cnfn exp(double8 x); +double16 __ovld __cnfn exp(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn exp(half); -half2 __ovld __cnfn exp(half2); -half3 __ovld __cnfn exp(half3); -half4 __ovld __cnfn exp(half4); -half8 __ovld __cnfn exp(half8); -half16 __ovld __cnfn exp(half16); +half __ovld __cnfn exp(half x); +half2 __ovld __cnfn exp(half2 x); +half3 __ovld __cnfn exp(half3 x); +half4 __ovld __cnfn exp(half4 x); +half8 __ovld __cnfn exp(half8 x); +half16 __ovld __cnfn exp(half16 x); #endif //cl_khr_fp16 /** @@ -7012,27 +7720,27 @@ half16 __ovld __cnfn exp10(half16); /** * Compute e^x- 1.0. */ -float __ovld __cnfn expm1(float); -float2 __ovld __cnfn expm1(float2); -float3 __ovld __cnfn expm1(float3); -float4 __ovld __cnfn expm1(float4); -float8 __ovld __cnfn expm1(float8); -float16 __ovld __cnfn expm1(float16); +float __ovld __cnfn expm1(float x); +float2 __ovld __cnfn expm1(float2 x); +float3 __ovld __cnfn expm1(float3 x); +float4 __ovld __cnfn expm1(float4 x); +float8 __ovld __cnfn expm1(float8 x); +float16 __ovld __cnfn expm1(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn expm1(double); -double2 __ovld __cnfn expm1(double2); -double3 __ovld __cnfn expm1(double3); -double4 __ovld __cnfn expm1(double4); -double8 __ovld __cnfn expm1(double8); -double16 __ovld __cnfn expm1(double16); +double __ovld __cnfn expm1(double x); +double2 __ovld __cnfn expm1(double2 x); +double3 __ovld __cnfn expm1(double3 x); +double4 __ovld __cnfn expm1(double4 x); +double8 __ovld __cnfn expm1(double8 x); +double16 __ovld __cnfn expm1(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn expm1(half); -half2 __ovld __cnfn expm1(half2); -half3 __ovld __cnfn expm1(half3); -half4 __ovld __cnfn expm1(half4); -half8 __ovld __cnfn expm1(half8); -half16 __ovld __cnfn expm1(half16); +half __ovld __cnfn expm1(half x); +half2 __ovld __cnfn expm1(half2 x); +half3 __ovld __cnfn expm1(half3 x); +half4 __ovld __cnfn expm1(half4 x); +half8 __ovld __cnfn expm1(half8 x); +half16 __ovld __cnfn expm1(half16 x); #endif //cl_khr_fp16 /** @@ -7062,29 +7770,29 @@ half16 __ovld __cnfn fabs(half16); #endif //cl_khr_fp16 /** - * x - y if x > y, +0 if x is less than or equal to y. + * x - y if x >, +0 if x is less than or equal to y. */ -float __ovld __cnfn fdim(float, float); -float2 __ovld __cnfn fdim(float2, float2); -float3 __ovld __cnfn fdim(float3, float3); -float4 __ovld __cnfn fdim(float4, float4); -float8 __ovld __cnfn fdim(float8, float8); -float16 __ovld __cnfn fdim(float16, float16); +float __ovld __cnfn fdim(float, float ); +float2 __ovld __cnfn fdim(float2, float2 ); +float3 __ovld __cnfn fdim(float3, float3 ); +float4 __ovld __cnfn fdim(float4, float4 ); +float8 __ovld __cnfn fdim(float8, float8 ); +float16 __ovld __cnfn fdim(float16, float16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn fdim(double, double); -double2 __ovld __cnfn fdim(double2, double2); -double3 __ovld __cnfn fdim(double3, double3); -double4 __ovld __cnfn fdim(double4, double4); -double8 __ovld __cnfn fdim(double8, double8); -double16 __ovld __cnfn fdim(double16, double16); +double __ovld __cnfn fdim(double, double ); +double2 __ovld __cnfn fdim(double2, double2 ); +double3 __ovld __cnfn fdim(double3, double3 ); +double4 __ovld __cnfn fdim(double4, double4 ); +double8 __ovld __cnfn fdim(double8, double8 ); +double16 __ovld __cnfn fdim(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn fdim(half, half); -half2 __ovld __cnfn fdim(half2, half2); -half3 __ovld __cnfn fdim(half3, half3); -half4 __ovld __cnfn fdim(half4, half4); -half8 __ovld __cnfn fdim(half8, half8); -half16 __ovld __cnfn fdim(half16, half16); +half __ovld __cnfn fdim(half, half ); +half2 __ovld __cnfn fdim(half2, half2 ); +half3 __ovld __cnfn fdim(half3, half3 ); +half4 __ovld __cnfn fdim(half4, half4 ); +half8 __ovld __cnfn fdim(half8, half8 ); +half16 __ovld __cnfn fdim(half16, half16 ); #endif //cl_khr_fp16 /** @@ -7145,117 +7853,117 @@ half16 __ovld __cnfn fma(half16, half16, half16); #endif //cl_khr_fp16 /** - * Returns y if x < y, otherwise it returns x. If one + * Returns y if x <, otherwise it returns x. If one * argument is a NaN, fmax() returns the other * argument. If both arguments are NaNs, fmax() * returns a NaN. */ -float __ovld __cnfn fmax(float, float); -float2 __ovld __cnfn fmax(float2, float2); -float3 __ovld __cnfn fmax(float3, float3); -float4 __ovld __cnfn fmax(float4, float4); -float8 __ovld __cnfn fmax(float8, float8); -float16 __ovld __cnfn fmax(float16, float16); -float2 __ovld __cnfn fmax(float2, float); -float3 __ovld __cnfn fmax(float3, float); -float4 __ovld __cnfn fmax(float4, float); -float8 __ovld __cnfn fmax(float8, float); -float16 __ovld __cnfn fmax(float16, float); +float __ovld __cnfn fmax(float, float ); +float2 __ovld __cnfn fmax(float2, float2 ); +float3 __ovld __cnfn fmax(float3, float3 ); +float4 __ovld __cnfn fmax(float4, float4 ); +float8 __ovld __cnfn fmax(float8, float8 ); +float16 __ovld __cnfn fmax(float16, float16 ); +float2 __ovld __cnfn fmax(float2, float ); +float3 __ovld __cnfn fmax(float3, float ); +float4 __ovld __cnfn fmax(float4, float ); +float8 __ovld __cnfn fmax(float8, float ); +float16 __ovld __cnfn fmax(float16, float ); #ifdef cl_khr_fp64 -double __ovld __cnfn fmax(double, double); -double2 __ovld __cnfn fmax(double2, double2); -double3 __ovld __cnfn fmax(double3, double3); -double4 __ovld __cnfn fmax(double4, double4); -double8 __ovld __cnfn fmax(double8, double8); -double16 __ovld __cnfn fmax(double16, double16); -double2 __ovld __cnfn fmax(double2, double); -double3 __ovld __cnfn fmax(double3, double); -double4 __ovld __cnfn fmax(double4, double); -double8 __ovld __cnfn fmax(double8, double); -double16 __ovld __cnfn fmax(double16, double); +double __ovld __cnfn fmax(double, double ); +double2 __ovld __cnfn fmax(double2, double2 ); +double3 __ovld __cnfn fmax(double3, double3 ); +double4 __ovld __cnfn fmax(double4, double4 ); +double8 __ovld __cnfn fmax(double8, double8 ); +double16 __ovld __cnfn fmax(double16, double16 ); +double2 __ovld __cnfn fmax(double2, double ); +double3 __ovld __cnfn fmax(double3, double ); +double4 __ovld __cnfn fmax(double4, double ); +double8 __ovld __cnfn fmax(double8, double ); +double16 __ovld __cnfn fmax(double16, double ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn fmax(half, half); -half2 __ovld __cnfn fmax(half2, half2); -half3 __ovld __cnfn fmax(half3, half3); -half4 __ovld __cnfn fmax(half4, half4); -half8 __ovld __cnfn fmax(half8, half8); -half16 __ovld __cnfn fmax(half16, half16); -half2 __ovld __cnfn fmax(half2, half); -half3 __ovld __cnfn fmax(half3, half); -half4 __ovld __cnfn fmax(half4, half); -half8 __ovld __cnfn fmax(half8, half); -half16 __ovld __cnfn fmax(half16, half); +half __ovld __cnfn fmax(half, half ); +half2 __ovld __cnfn fmax(half2, half2 ); +half3 __ovld __cnfn fmax(half3, half3 ); +half4 __ovld __cnfn fmax(half4, half4 ); +half8 __ovld __cnfn fmax(half8, half8 ); +half16 __ovld __cnfn fmax(half16, half16 ); +half2 __ovld __cnfn fmax(half2, half ); +half3 __ovld __cnfn fmax(half3, half ); +half4 __ovld __cnfn fmax(half4, half ); +half8 __ovld __cnfn fmax(half8, half ); +half16 __ovld __cnfn fmax(half16, half ); #endif //cl_khr_fp16 /** - * Returns y if y < x, otherwise it returns x. If one + * Returns y if y <, otherwise it returns x. If one * argument is a NaN, fmin() returns the other * argument. If both arguments are NaNs, fmin() * returns a NaN. */ -float __ovld __cnfn fmin(float, float); -float2 __ovld __cnfn fmin(float2, float2); -float3 __ovld __cnfn fmin(float3, float3); -float4 __ovld __cnfn fmin(float4, float4); -float8 __ovld __cnfn fmin(float8, float8); -float16 __ovld __cnfn fmin(float16, float16); -float2 __ovld __cnfn fmin(float2, float); -float3 __ovld __cnfn fmin(float3, float); -float4 __ovld __cnfn fmin(float4, float); -float8 __ovld __cnfn fmin(float8, float); -float16 __ovld __cnfn fmin(float16, float); +float __ovld __cnfn fmin(float, float ); +float2 __ovld __cnfn fmin(float2, float2 ); +float3 __ovld __cnfn fmin(float3, float3 ); +float4 __ovld __cnfn fmin(float4, float4 ); +float8 __ovld __cnfn fmin(float8, float8 ); +float16 __ovld __cnfn fmin(float16, float16 ); +float2 __ovld __cnfn fmin(float2, float ); +float3 __ovld __cnfn fmin(float3, float ); +float4 __ovld __cnfn fmin(float4, float ); +float8 __ovld __cnfn fmin(float8, float ); +float16 __ovld __cnfn fmin(float16, float ); #ifdef cl_khr_fp64 -double __ovld __cnfn fmin(double, double); -double2 __ovld __cnfn fmin(double2, double2); -double3 __ovld __cnfn fmin(double3, double3); -double4 __ovld __cnfn fmin(double4, double4); -double8 __ovld __cnfn fmin(double8, double8); -double16 __ovld __cnfn fmin(double16, double16); -double2 __ovld __cnfn fmin(double2, double); -double3 __ovld __cnfn fmin(double3, double); -double4 __ovld __cnfn fmin(double4, double); -double8 __ovld __cnfn fmin(double8, double); -double16 __ovld __cnfn fmin(double16, double); +double __ovld __cnfn fmin(double, double ); +double2 __ovld __cnfn fmin(double2, double2 ); +double3 __ovld __cnfn fmin(double3, double3 ); +double4 __ovld __cnfn fmin(double4, double4 ); +double8 __ovld __cnfn fmin(double8, double8 ); +double16 __ovld __cnfn fmin(double16, double16 ); +double2 __ovld __cnfn fmin(double2, double ); +double3 __ovld __cnfn fmin(double3, double ); +double4 __ovld __cnfn fmin(double4, double ); +double8 __ovld __cnfn fmin(double8, double ); +double16 __ovld __cnfn fmin(double16, double ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn fmin(half, half); -half2 __ovld __cnfn fmin(half2, half2); -half3 __ovld __cnfn fmin(half3, half3); -half4 __ovld __cnfn fmin(half4, half4); -half8 __ovld __cnfn fmin(half8, half8); -half16 __ovld __cnfn fmin(half16, half16); -half2 __ovld __cnfn fmin(half2, half); -half3 __ovld __cnfn fmin(half3, half); -half4 __ovld __cnfn fmin(half4, half); -half8 __ovld __cnfn fmin(half8, half); -half16 __ovld __cnfn fmin(half16, half); +half __ovld __cnfn fmin(half, half ); +half2 __ovld __cnfn fmin(half2, half2 ); +half3 __ovld __cnfn fmin(half3, half3 ); +half4 __ovld __cnfn fmin(half4, half4 ); +half8 __ovld __cnfn fmin(half8, half8 ); +half16 __ovld __cnfn fmin(half16, half16 ); +half2 __ovld __cnfn fmin(half2, half ); +half3 __ovld __cnfn fmin(half3, half ); +half4 __ovld __cnfn fmin(half4, half ); +half8 __ovld __cnfn fmin(half8, half ); +half16 __ovld __cnfn fmin(half16, half ); #endif //cl_khr_fp16 /** * Modulus. Returns x - y * trunc (x/y). */ -float __ovld __cnfn fmod(float, float); -float2 __ovld __cnfn fmod(float2, float2); -float3 __ovld __cnfn fmod(float3, float3); -float4 __ovld __cnfn fmod(float4, float4); -float8 __ovld __cnfn fmod(float8, float8); -float16 __ovld __cnfn fmod(float16, float16); +float __ovld __cnfn fmod(float, float ); +float2 __ovld __cnfn fmod(float2, float2 ); +float3 __ovld __cnfn fmod(float3, float3 ); +float4 __ovld __cnfn fmod(float4, float4 ); +float8 __ovld __cnfn fmod(float8, float8 ); +float16 __ovld __cnfn fmod(float16, float16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn fmod(double, double); -double2 __ovld __cnfn fmod(double2, double2); -double3 __ovld __cnfn fmod(double3, double3); -double4 __ovld __cnfn fmod(double4, double4); -double8 __ovld __cnfn fmod(double8, double8); -double16 __ovld __cnfn fmod(double16, double16); +double __ovld __cnfn fmod(double, double ); +double2 __ovld __cnfn fmod(double2, double2 ); +double3 __ovld __cnfn fmod(double3, double3 ); +double4 __ovld __cnfn fmod(double4, double4 ); +double8 __ovld __cnfn fmod(double8, double8 ); +double16 __ovld __cnfn fmod(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn fmod(half, half); -half2 __ovld __cnfn fmod(half2, half2); -half3 __ovld __cnfn fmod(half3, half3); -half4 __ovld __cnfn fmod(half4, half4); -half8 __ovld __cnfn fmod(half8, half8); -half16 __ovld __cnfn fmod(half16, half16); +half __ovld __cnfn fmod(half, half ); +half2 __ovld __cnfn fmod(half2, half2 ); +half3 __ovld __cnfn fmod(half3, half3 ); +half4 __ovld __cnfn fmod(half4, half4 ); +half8 __ovld __cnfn fmod(half8, half8 ); +half16 __ovld __cnfn fmod(half16, half16 ); #endif //cl_khr_fp16 /** @@ -7263,90 +7971,88 @@ half16 __ovld __cnfn fmod(half16, half16); * floor(x) is returned in iptr. */ #if defined(__opencl_c_generic_address_space) -float __ovld fract(float, float *); -float2 __ovld fract(float2, float2 *); -float3 __ovld fract(float3, float3 *); -float4 __ovld fract(float4, float4 *); -float8 __ovld fract(float8, float8 *); -float16 __ovld fract(float16, float16 *); +float __ovld fract(float, float *iptr); +float2 __ovld fract(float2, float2 *iptr); +float3 __ovld fract(float3, float3 *iptr); +float4 __ovld fract(float4, float4 *iptr); +float8 __ovld fract(float8, float8 *iptr); +float16 __ovld fract(float16, float16 *iptr); #ifdef cl_khr_fp64 -double __ovld fract(double, double *); -double2 __ovld fract(double2, double2 *); -double3 __ovld fract(double3, double3 *); -double4 __ovld fract(double4, double4 *); -double8 __ovld fract(double8, double8 *); -double16 __ovld fract(double16, double16 *); +double __ovld fract(double, double *iptr); +double2 __ovld fract(double2, double2 *iptr); +double3 __ovld fract(double3, double3 *iptr); +double4 __ovld fract(double4, double4 *iptr); +double8 __ovld fract(double8, double8 *iptr); +double16 __ovld fract(double16, double16 *iptr); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld fract(half, half *); -half2 __ovld fract(half2, half2 *); -half3 __ovld fract(half3, half3 *); -half4 __ovld fract(half4, half4 *); -half8 __ovld fract(half8, half8 *); -half16 __ovld fract(half16, half16 *); +half __ovld fract(half, half *iptr); +half2 __ovld fract(half2, half2 *iptr); +half3 __ovld fract(half3, half3 *iptr); +half4 __ovld fract(half4, half4 *iptr); +half8 __ovld fract(half8, half8 *iptr); +half16 __ovld fract(half16, half16 *iptr); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) -float __ovld fract(float, __global float *); -float2 __ovld fract(float2, __global float2 *); -float3 __ovld fract(float3, __global float3 *); -float4 __ovld fract(float4, __global float4 *); -float8 __ovld fract(float8, __global float8 *); -float16 __ovld fract(float16, __global float16 *); -float __ovld fract(float, __local float *); -float2 __ovld fract(float2, __local float2 *); -float3 __ovld fract(float3, __local float3 *); -float4 __ovld fract(float4, __local float4 *); -float8 __ovld fract(float8, __local float8 *); -float16 __ovld fract(float16, __local float16 *); -float __ovld fract(float, __private float *); -float2 __ovld fract(float2, __private float2 *); -float3 __ovld fract(float3, __private float3 *); -float4 __ovld fract(float4, __private float4 *); -float8 __ovld fract(float8, __private float8 *); -float16 __ovld fract(float16, __private float16 *); +#else +float __ovld fract(float, __global float *iptr); +float2 __ovld fract(float2, __global float2 *iptr); +float3 __ovld fract(float3, __global float3 *iptr); +float4 __ovld fract(float4, __global float4 *iptr); +float8 __ovld fract(float8, __global float8 *iptr); +float16 __ovld fract(float16, __global float16 *iptr); +float __ovld fract(float, __local float *iptr); +float2 __ovld fract(float2, __local float2 *iptr); +float3 __ovld fract(float3, __local float3 *iptr); +float4 __ovld fract(float4, __local float4 *iptr); +float8 __ovld fract(float8, __local float8 *iptr); +float16 __ovld fract(float16, __local float16 *iptr); +float __ovld fract(float, __private float *iptr); +float2 __ovld fract(float2, __private float2 *iptr); +float3 __ovld fract(float3, __private float3 *iptr); +float4 __ovld fract(float4, __private float4 *iptr); +float8 __ovld fract(float8, __private float8 *iptr); +float16 __ovld fract(float16, __private float16 *iptr); #ifdef cl_khr_fp64 -double __ovld fract(double, __global double *); -double2 __ovld fract(double2, __global double2 *); -double3 __ovld fract(double3, __global double3 *); -double4 __ovld fract(double4, __global double4 *); -double8 __ovld fract(double8, __global double8 *); -double16 __ovld fract(double16, __global double16 *); -double __ovld fract(double, __local double *); -double2 __ovld fract(double2, __local double2 *); -double3 __ovld fract(double3, __local double3 *); -double4 __ovld fract(double4, __local double4 *); -double8 __ovld fract(double8, __local double8 *); -double16 __ovld fract(double16, __local double16 *); -double __ovld fract(double, __private double *); -double2 __ovld fract(double2, __private double2 *); -double3 __ovld fract(double3, __private double3 *); -double4 __ovld fract(double4, __private double4 *); -double8 __ovld fract(double8, __private double8 *); -double16 __ovld fract(double16, __private double16 *); +double __ovld fract(double, __global double *iptr); +double2 __ovld fract(double2, __global double2 *iptr); +double3 __ovld fract(double3, __global double3 *iptr); +double4 __ovld fract(double4, __global double4 *iptr); +double8 __ovld fract(double8, __global double8 *iptr); +double16 __ovld fract(double16, __global double16 *iptr); +double __ovld fract(double, __local double *iptr); +double2 __ovld fract(double2, __local double2 *iptr); +double3 __ovld fract(double3, __local double3 *iptr); +double4 __ovld fract(double4, __local double4 *iptr); +double8 __ovld fract(double8, __local double8 *iptr); +double16 __ovld fract(double16, __local double16 *iptr); +double __ovld fract(double, __private double *iptr); +double2 __ovld fract(double2, __private double2 *iptr); +double3 __ovld fract(double3, __private double3 *iptr); +double4 __ovld fract(double4, __private double4 *iptr); +double8 __ovld fract(double8, __private double8 *iptr); +double16 __ovld fract(double16, __private double16 *iptr); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld fract(half, __global half *); -half2 __ovld fract(half2, __global half2 *); -half3 __ovld fract(half3, __global half3 *); -half4 __ovld fract(half4, __global half4 *); -half8 __ovld fract(half8, __global half8 *); -half16 __ovld fract(half16, __global half16 *); -half __ovld fract(half, __local half *); -half2 __ovld fract(half2, __local half2 *); -half3 __ovld fract(half3, __local half3 *); -half4 __ovld fract(half4, __local half4 *); -half8 __ovld fract(half8, __local half8 *); -half16 __ovld fract(half16, __local half16 *); -half __ovld fract(half, __private half *); -half2 __ovld fract(half2, __private half2 *); -half3 __ovld fract(half3, __private half3 *); -half4 __ovld fract(half4, __private half4 *); -half8 __ovld fract(half8, __private half8 *); -half16 __ovld fract(half16, __private half16 *); +half __ovld fract(half, __global half *iptr); +half2 __ovld fract(half2, __global half2 *iptr); +half3 __ovld fract(half3, __global half3 *iptr); +half4 __ovld fract(half4, __global half4 *iptr); +half8 __ovld fract(half8, __global half8 *iptr); +half16 __ovld fract(half16, __global half16 *iptr); +half __ovld fract(half, __local half *iptr); +half2 __ovld fract(half2, __local half2 *iptr); +half3 __ovld fract(half3, __local half3 *iptr); +half4 __ovld fract(half4, __local half4 *iptr); +half8 __ovld fract(half8, __local half8 *iptr); +half16 __ovld fract(half16, __local half16 *iptr); +half __ovld fract(half, __private half *iptr); +half2 __ovld fract(half2, __private half2 *iptr); +half3 __ovld fract(half3, __private half3 *iptr); +half4 __ovld fract(half4, __private half4 *iptr); +half8 __ovld fract(half8, __private half8 *iptr); +half16 __ovld fract(half16, __private half16 *iptr); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * Extract mantissa and exponent from x. For each @@ -7377,9 +8083,7 @@ half4 __ovld frexp(half4, int4 *); half8 __ovld frexp(half8, int8 *); half16 __ovld frexp(half16, int16 *); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) +#else float __ovld frexp(float, __global int *); float2 __ovld frexp(float2, __global int2 *); float3 __ovld frexp(float3, __global int3 *); @@ -7438,59 +8142,59 @@ half4 __ovld frexp(half4, __private int4 *); half8 __ovld frexp(half8, __private int8 *); half16 __ovld frexp(half16, __private int16 *); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * Compute the value of the square root of x^2 + y^2 * without undue overflow or underflow. */ -float __ovld __cnfn hypot(float, float); -float2 __ovld __cnfn hypot(float2, float2); -float3 __ovld __cnfn hypot(float3, float3); -float4 __ovld __cnfn hypot(float4, float4); -float8 __ovld __cnfn hypot(float8, float8); -float16 __ovld __cnfn hypot(float16, float16); +float __ovld __cnfn hypot(float, float ); +float2 __ovld __cnfn hypot(float2, float2 ); +float3 __ovld __cnfn hypot(float3, float3 ); +float4 __ovld __cnfn hypot(float4, float4 ); +float8 __ovld __cnfn hypot(float8, float8 ); +float16 __ovld __cnfn hypot(float16, float16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn hypot(double, double); -double2 __ovld __cnfn hypot(double2, double2); -double3 __ovld __cnfn hypot(double3, double3); -double4 __ovld __cnfn hypot(double4, double4); -double8 __ovld __cnfn hypot(double8, double8); -double16 __ovld __cnfn hypot(double16, double16); +double __ovld __cnfn hypot(double, double ); +double2 __ovld __cnfn hypot(double2, double2 ); +double3 __ovld __cnfn hypot(double3, double3 ); +double4 __ovld __cnfn hypot(double4, double4 ); +double8 __ovld __cnfn hypot(double8, double8 ); +double16 __ovld __cnfn hypot(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn hypot(half, half); -half2 __ovld __cnfn hypot(half2, half2); -half3 __ovld __cnfn hypot(half3, half3); -half4 __ovld __cnfn hypot(half4, half4); -half8 __ovld __cnfn hypot(half8, half8); -half16 __ovld __cnfn hypot(half16, half16); +half __ovld __cnfn hypot(half, half ); +half2 __ovld __cnfn hypot(half2, half2 ); +half3 __ovld __cnfn hypot(half3, half3 ); +half4 __ovld __cnfn hypot(half4, half4 ); +half8 __ovld __cnfn hypot(half8, half8 ); +half16 __ovld __cnfn hypot(half16, half16 ); #endif //cl_khr_fp16 /** * Return the exponent as an integer value. */ -int __ovld __cnfn ilogb(float); -int2 __ovld __cnfn ilogb(float2); -int3 __ovld __cnfn ilogb(float3); -int4 __ovld __cnfn ilogb(float4); -int8 __ovld __cnfn ilogb(float8); -int16 __ovld __cnfn ilogb(float16); +int __ovld __cnfn ilogb(float x); +int2 __ovld __cnfn ilogb(float2 x); +int3 __ovld __cnfn ilogb(float3 x); +int4 __ovld __cnfn ilogb(float4 x); +int8 __ovld __cnfn ilogb(float8 x); +int16 __ovld __cnfn ilogb(float16 x); #ifdef cl_khr_fp64 -int __ovld __cnfn ilogb(double); -int2 __ovld __cnfn ilogb(double2); -int3 __ovld __cnfn ilogb(double3); -int4 __ovld __cnfn ilogb(double4); -int8 __ovld __cnfn ilogb(double8); -int16 __ovld __cnfn ilogb(double16); +int __ovld __cnfn ilogb(double x); +int2 __ovld __cnfn ilogb(double2 x); +int3 __ovld __cnfn ilogb(double3 x); +int4 __ovld __cnfn ilogb(double4 x); +int8 __ovld __cnfn ilogb(double8 x); +int16 __ovld __cnfn ilogb(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -int __ovld __cnfn ilogb(half); -int2 __ovld __cnfn ilogb(half2); -int3 __ovld __cnfn ilogb(half3); -int4 __ovld __cnfn ilogb(half4); -int8 __ovld __cnfn ilogb(half8); -int16 __ovld __cnfn ilogb(half16); +int __ovld __cnfn ilogb(half x); +int2 __ovld __cnfn ilogb(half2 x); +int3 __ovld __cnfn ilogb(half3 x); +int4 __ovld __cnfn ilogb(half4 x); +int8 __ovld __cnfn ilogb(half8 x); +int16 __ovld __cnfn ilogb(half16 x); #endif //cl_khr_fp16 /** @@ -7540,114 +8244,112 @@ half16 __ovld __cnfn ldexp(half16, int); * function. The sign of the gamma function is * returned in the signp argument of lgamma_r. */ -float __ovld __cnfn lgamma(float); -float2 __ovld __cnfn lgamma(float2); -float3 __ovld __cnfn lgamma(float3); -float4 __ovld __cnfn lgamma(float4); -float8 __ovld __cnfn lgamma(float8); -float16 __ovld __cnfn lgamma(float16); +float __ovld __cnfn lgamma(float x); +float2 __ovld __cnfn lgamma(float2 x); +float3 __ovld __cnfn lgamma(float3 x); +float4 __ovld __cnfn lgamma(float4 x); +float8 __ovld __cnfn lgamma(float8 x); +float16 __ovld __cnfn lgamma(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn lgamma(double); -double2 __ovld __cnfn lgamma(double2); -double3 __ovld __cnfn lgamma(double3); -double4 __ovld __cnfn lgamma(double4); -double8 __ovld __cnfn lgamma(double8); -double16 __ovld __cnfn lgamma(double16); +double __ovld __cnfn lgamma(double x); +double2 __ovld __cnfn lgamma(double2 x); +double3 __ovld __cnfn lgamma(double3 x); +double4 __ovld __cnfn lgamma(double4 x); +double8 __ovld __cnfn lgamma(double8 x); +double16 __ovld __cnfn lgamma(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn lgamma(half); -half2 __ovld __cnfn lgamma(half2); -half3 __ovld __cnfn lgamma(half3); -half4 __ovld __cnfn lgamma(half4); -half8 __ovld __cnfn lgamma(half8); -half16 __ovld __cnfn lgamma(half16); +half __ovld __cnfn lgamma(half x); +half2 __ovld __cnfn lgamma(half2 x); +half3 __ovld __cnfn lgamma(half3 x); +half4 __ovld __cnfn lgamma(half4 x); +half8 __ovld __cnfn lgamma(half8 x); +half16 __ovld __cnfn lgamma(half16 x); #endif //cl_khr_fp16 #if defined(__opencl_c_generic_address_space) -float __ovld lgamma_r(float, int *); -float2 __ovld lgamma_r(float2, int2 *); -float3 __ovld lgamma_r(float3, int3 *); -float4 __ovld lgamma_r(float4, int4 *); -float8 __ovld lgamma_r(float8, int8 *); -float16 __ovld lgamma_r(float16, int16 *); +float __ovld lgamma_r(float, int *signp); +float2 __ovld lgamma_r(float2, int2 *signp); +float3 __ovld lgamma_r(float3, int3 *signp); +float4 __ovld lgamma_r(float4, int4 *signp); +float8 __ovld lgamma_r(float8, int8 *signp); +float16 __ovld lgamma_r(float16, int16 *signp); #ifdef cl_khr_fp64 -double __ovld lgamma_r(double, int *); -double2 __ovld lgamma_r(double2, int2 *); -double3 __ovld lgamma_r(double3, int3 *); -double4 __ovld lgamma_r(double4, int4 *); -double8 __ovld lgamma_r(double8, int8 *); -double16 __ovld lgamma_r(double16, int16 *); +double __ovld lgamma_r(double, int *signp); +double2 __ovld lgamma_r(double2, int2 *signp); +double3 __ovld lgamma_r(double3, int3 *signp); +double4 __ovld lgamma_r(double4, int4 *signp); +double8 __ovld lgamma_r(double8, int8 *signp); +double16 __ovld lgamma_r(double16, int16 *signp); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld lgamma_r(half, int *); -half2 __ovld lgamma_r(half2, int2 *); -half3 __ovld lgamma_r(half3, int3 *); -half4 __ovld lgamma_r(half4, int4 *); -half8 __ovld lgamma_r(half8, int8 *); -half16 __ovld lgamma_r(half16, int16 *); +half __ovld lgamma_r(half, int *signp); +half2 __ovld lgamma_r(half2, int2 *signp); +half3 __ovld lgamma_r(half3, int3 *signp); +half4 __ovld lgamma_r(half4, int4 *signp); +half8 __ovld lgamma_r(half8, int8 *signp); +half16 __ovld lgamma_r(half16, int16 *signp); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) -float __ovld lgamma_r(float, __global int *); -float2 __ovld lgamma_r(float2, __global int2 *); -float3 __ovld lgamma_r(float3, __global int3 *); -float4 __ovld lgamma_r(float4, __global int4 *); -float8 __ovld lgamma_r(float8, __global int8 *); -float16 __ovld lgamma_r(float16, __global int16 *); -float __ovld lgamma_r(float, __local int *); -float2 __ovld lgamma_r(float2, __local int2 *); -float3 __ovld lgamma_r(float3, __local int3 *); -float4 __ovld lgamma_r(float4, __local int4 *); -float8 __ovld lgamma_r(float8, __local int8 *); -float16 __ovld lgamma_r(float16, __local int16 *); -float __ovld lgamma_r(float, __private int *); -float2 __ovld lgamma_r(float2, __private int2 *); -float3 __ovld lgamma_r(float3, __private int3 *); -float4 __ovld lgamma_r(float4, __private int4 *); -float8 __ovld lgamma_r(float8, __private int8 *); -float16 __ovld lgamma_r(float16, __private int16 *); +#else +float __ovld lgamma_r(float, __global int *signp); +float2 __ovld lgamma_r(float2, __global int2 *signp); +float3 __ovld lgamma_r(float3, __global int3 *signp); +float4 __ovld lgamma_r(float4, __global int4 *signp); +float8 __ovld lgamma_r(float8, __global int8 *signp); +float16 __ovld lgamma_r(float16, __global int16 *signp); +float __ovld lgamma_r(float, __local int *signp); +float2 __ovld lgamma_r(float2, __local int2 *signp); +float3 __ovld lgamma_r(float3, __local int3 *signp); +float4 __ovld lgamma_r(float4, __local int4 *signp); +float8 __ovld lgamma_r(float8, __local int8 *signp); +float16 __ovld lgamma_r(float16, __local int16 *signp); +float __ovld lgamma_r(float, __private int *signp); +float2 __ovld lgamma_r(float2, __private int2 *signp); +float3 __ovld lgamma_r(float3, __private int3 *signp); +float4 __ovld lgamma_r(float4, __private int4 *signp); +float8 __ovld lgamma_r(float8, __private int8 *signp); +float16 __ovld lgamma_r(float16, __private int16 *signp); #ifdef cl_khr_fp64 -double __ovld lgamma_r(double, __global int *); -double2 __ovld lgamma_r(double2, __global int2 *); -double3 __ovld lgamma_r(double3, __global int3 *); -double4 __ovld lgamma_r(double4, __global int4 *); -double8 __ovld lgamma_r(double8, __global int8 *); -double16 __ovld lgamma_r(double16, __global int16 *); -double __ovld lgamma_r(double, __local int *); -double2 __ovld lgamma_r(double2, __local int2 *); -double3 __ovld lgamma_r(double3, __local int3 *); -double4 __ovld lgamma_r(double4, __local int4 *); -double8 __ovld lgamma_r(double8, __local int8 *); -double16 __ovld lgamma_r(double16, __local int16 *); -double __ovld lgamma_r(double, __private int *); -double2 __ovld lgamma_r(double2, __private int2 *); -double3 __ovld lgamma_r(double3, __private int3 *); -double4 __ovld lgamma_r(double4, __private int4 *); -double8 __ovld lgamma_r(double8, __private int8 *); -double16 __ovld lgamma_r(double16, __private int16 *); +double __ovld lgamma_r(double, __global int *signp); +double2 __ovld lgamma_r(double2, __global int2 *signp); +double3 __ovld lgamma_r(double3, __global int3 *signp); +double4 __ovld lgamma_r(double4, __global int4 *signp); +double8 __ovld lgamma_r(double8, __global int8 *signp); +double16 __ovld lgamma_r(double16, __global int16 *signp); +double __ovld lgamma_r(double, __local int *signp); +double2 __ovld lgamma_r(double2, __local int2 *signp); +double3 __ovld lgamma_r(double3, __local int3 *signp); +double4 __ovld lgamma_r(double4, __local int4 *signp); +double8 __ovld lgamma_r(double8, __local int8 *signp); +double16 __ovld lgamma_r(double16, __local int16 *signp); +double __ovld lgamma_r(double, __private int *signp); +double2 __ovld lgamma_r(double2, __private int2 *signp); +double3 __ovld lgamma_r(double3, __private int3 *signp); +double4 __ovld lgamma_r(double4, __private int4 *signp); +double8 __ovld lgamma_r(double8, __private int8 *signp); +double16 __ovld lgamma_r(double16, __private int16 *signp); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld lgamma_r(half, __global int *); -half2 __ovld lgamma_r(half2, __global int2 *); -half3 __ovld lgamma_r(half3, __global int3 *); -half4 __ovld lgamma_r(half4, __global int4 *); -half8 __ovld lgamma_r(half8, __global int8 *); -half16 __ovld lgamma_r(half16, __global int16 *); -half __ovld lgamma_r(half, __local int *); -half2 __ovld lgamma_r(half2, __local int2 *); -half3 __ovld lgamma_r(half3, __local int3 *); -half4 __ovld lgamma_r(half4, __local int4 *); -half8 __ovld lgamma_r(half8, __local int8 *); -half16 __ovld lgamma_r(half16, __local int16 *); -half __ovld lgamma_r(half, __private int *); -half2 __ovld lgamma_r(half2, __private int2 *); -half3 __ovld lgamma_r(half3, __private int3 *); -half4 __ovld lgamma_r(half4, __private int4 *); -half8 __ovld lgamma_r(half8, __private int8 *); -half16 __ovld lgamma_r(half16, __private int16 *); +half __ovld lgamma_r(half, __global int *signp); +half2 __ovld lgamma_r(half2, __global int2 *signp); +half3 __ovld lgamma_r(half3, __global int3 *signp); +half4 __ovld lgamma_r(half4, __global int4 *signp); +half8 __ovld lgamma_r(half8, __global int8 *signp); +half16 __ovld lgamma_r(half16, __global int16 *signp); +half __ovld lgamma_r(half, __local int *signp); +half2 __ovld lgamma_r(half2, __local int2 *signp); +half3 __ovld lgamma_r(half3, __local int3 *signp); +half4 __ovld lgamma_r(half4, __local int4 *signp); +half8 __ovld lgamma_r(half8, __local int8 *signp); +half16 __ovld lgamma_r(half16, __local int16 *signp); +half __ovld lgamma_r(half, __private int *signp); +half2 __ovld lgamma_r(half2, __private int2 *signp); +half3 __ovld lgamma_r(half3, __private int3 *signp); +half4 __ovld lgamma_r(half4, __private int4 *signp); +half8 __ovld lgamma_r(half8, __private int8 *signp); +half16 __ovld lgamma_r(half16, __private int16 *signp); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * Compute natural logarithm. @@ -7730,54 +8432,54 @@ half16 __ovld __cnfn log10(half16); /** * Compute a base e logarithm of (1.0 + x). */ -float __ovld __cnfn log1p(float); -float2 __ovld __cnfn log1p(float2); -float3 __ovld __cnfn log1p(float3); -float4 __ovld __cnfn log1p(float4); -float8 __ovld __cnfn log1p(float8); -float16 __ovld __cnfn log1p(float16); +float __ovld __cnfn log1p(float x); +float2 __ovld __cnfn log1p(float2 x); +float3 __ovld __cnfn log1p(float3 x); +float4 __ovld __cnfn log1p(float4 x); +float8 __ovld __cnfn log1p(float8 x); +float16 __ovld __cnfn log1p(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn log1p(double); -double2 __ovld __cnfn log1p(double2); -double3 __ovld __cnfn log1p(double3); -double4 __ovld __cnfn log1p(double4); -double8 __ovld __cnfn log1p(double8); -double16 __ovld __cnfn log1p(double16); +double __ovld __cnfn log1p(double x); +double2 __ovld __cnfn log1p(double2 x); +double3 __ovld __cnfn log1p(double3 x); +double4 __ovld __cnfn log1p(double4 x); +double8 __ovld __cnfn log1p(double8 x); +double16 __ovld __cnfn log1p(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn log1p(half); -half2 __ovld __cnfn log1p(half2); -half3 __ovld __cnfn log1p(half3); -half4 __ovld __cnfn log1p(half4); -half8 __ovld __cnfn log1p(half8); -half16 __ovld __cnfn log1p(half16); +half __ovld __cnfn log1p(half x); +half2 __ovld __cnfn log1p(half2 x); +half3 __ovld __cnfn log1p(half3 x); +half4 __ovld __cnfn log1p(half4 x); +half8 __ovld __cnfn log1p(half8 x); +half16 __ovld __cnfn log1p(half16 x); #endif //cl_khr_fp16 /** - * Compute the exponent of x, which is the integral + * Compute the exponent of, which is the integral * part of logr | x |. */ -float __ovld __cnfn logb(float); -float2 __ovld __cnfn logb(float2); -float3 __ovld __cnfn logb(float3); -float4 __ovld __cnfn logb(float4); -float8 __ovld __cnfn logb(float8); -float16 __ovld __cnfn logb(float16); +float __ovld __cnfn logb(float x); +float2 __ovld __cnfn logb(float2 x); +float3 __ovld __cnfn logb(float3 x); +float4 __ovld __cnfn logb(float4 x); +float8 __ovld __cnfn logb(float8 x); +float16 __ovld __cnfn logb(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn logb(double); -double2 __ovld __cnfn logb(double2); -double3 __ovld __cnfn logb(double3); -double4 __ovld __cnfn logb(double4); -double8 __ovld __cnfn logb(double8); -double16 __ovld __cnfn logb(double16); +double __ovld __cnfn logb(double x); +double2 __ovld __cnfn logb(double2 x); +double3 __ovld __cnfn logb(double3 x); +double4 __ovld __cnfn logb(double4 x); +double8 __ovld __cnfn logb(double8 x); +double16 __ovld __cnfn logb(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn logb(half); -half2 __ovld __cnfn logb(half2); -half3 __ovld __cnfn logb(half3); -half4 __ovld __cnfn logb(half4); -half8 __ovld __cnfn logb(half8); -half16 __ovld __cnfn logb(half16); +half __ovld __cnfn logb(half x); +half2 __ovld __cnfn logb(half2 x); +half3 __ovld __cnfn logb(half3 x); +half4 __ovld __cnfn logb(half4 x); +half8 __ovld __cnfn logb(half8 x); +half16 __ovld __cnfn logb(half16 x); #endif //cl_khr_fp16 /** @@ -7812,56 +8514,56 @@ half16 __ovld __cnfn mad(half16, half16, half16); /** * Returns x if | x | > | y |, y if | y | > | x |, otherwise - * fmax(x, y). + * fmax(x, ). */ -float __ovld __cnfn maxmag(float, float); -float2 __ovld __cnfn maxmag(float2, float2); -float3 __ovld __cnfn maxmag(float3, float3); -float4 __ovld __cnfn maxmag(float4, float4); -float8 __ovld __cnfn maxmag(float8, float8); -float16 __ovld __cnfn maxmag(float16, float16); +float __ovld __cnfn maxmag(float, float ); +float2 __ovld __cnfn maxmag(float2, float2 ); +float3 __ovld __cnfn maxmag(float3, float3 ); +float4 __ovld __cnfn maxmag(float4, float4 ); +float8 __ovld __cnfn maxmag(float8, float8 ); +float16 __ovld __cnfn maxmag(float16, float16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn maxmag(double, double); -double2 __ovld __cnfn maxmag(double2, double2); -double3 __ovld __cnfn maxmag(double3, double3); -double4 __ovld __cnfn maxmag(double4, double4); -double8 __ovld __cnfn maxmag(double8, double8); -double16 __ovld __cnfn maxmag(double16, double16); +double __ovld __cnfn maxmag(double, double ); +double2 __ovld __cnfn maxmag(double2, double2 ); +double3 __ovld __cnfn maxmag(double3, double3 ); +double4 __ovld __cnfn maxmag(double4, double4 ); +double8 __ovld __cnfn maxmag(double8, double8 ); +double16 __ovld __cnfn maxmag(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn maxmag(half, half); -half2 __ovld __cnfn maxmag(half2, half2); -half3 __ovld __cnfn maxmag(half3, half3); -half4 __ovld __cnfn maxmag(half4, half4); -half8 __ovld __cnfn maxmag(half8, half8); -half16 __ovld __cnfn maxmag(half16, half16); +half __ovld __cnfn maxmag(half, half ); +half2 __ovld __cnfn maxmag(half2, half2 ); +half3 __ovld __cnfn maxmag(half3, half3 ); +half4 __ovld __cnfn maxmag(half4, half4 ); +half8 __ovld __cnfn maxmag(half8, half8 ); +half16 __ovld __cnfn maxmag(half16, half16 ); #endif //cl_khr_fp16 /** * Returns x if | x | < | y |, y if | y | < | x |, otherwise - * fmin(x, y). + * fmin(x, ). */ -float __ovld __cnfn minmag(float, float); -float2 __ovld __cnfn minmag(float2, float2); -float3 __ovld __cnfn minmag(float3, float3); -float4 __ovld __cnfn minmag(float4, float4); -float8 __ovld __cnfn minmag(float8, float8); -float16 __ovld __cnfn minmag(float16, float16); +float __ovld __cnfn minmag(float, float ); +float2 __ovld __cnfn minmag(float2, float2 ); +float3 __ovld __cnfn minmag(float3, float3 ); +float4 __ovld __cnfn minmag(float4, float4 ); +float8 __ovld __cnfn minmag(float8, float8 ); +float16 __ovld __cnfn minmag(float16, float16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn minmag(double, double); -double2 __ovld __cnfn minmag(double2, double2); -double3 __ovld __cnfn minmag(double3, double3); -double4 __ovld __cnfn minmag(double4, double4); -double8 __ovld __cnfn minmag(double8, double8); -double16 __ovld __cnfn minmag(double16, double16); +double __ovld __cnfn minmag(double, double ); +double2 __ovld __cnfn minmag(double2, double2 ); +double3 __ovld __cnfn minmag(double3, double3 ); +double4 __ovld __cnfn minmag(double4, double4 ); +double8 __ovld __cnfn minmag(double8, double8 ); +double16 __ovld __cnfn minmag(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn minmag(half, half); -half2 __ovld __cnfn minmag(half2, half2); -half3 __ovld __cnfn minmag(half3, half3); -half4 __ovld __cnfn minmag(half4, half4); -half8 __ovld __cnfn minmag(half8, half8); -half16 __ovld __cnfn minmag(half16, half16); +half __ovld __cnfn minmag(half, half ); +half2 __ovld __cnfn minmag(half2, half2 ); +half3 __ovld __cnfn minmag(half3, half3 ); +half4 __ovld __cnfn minmag(half4, half4 ); +half8 __ovld __cnfn minmag(half8, half8 ); +half16 __ovld __cnfn minmag(half16, half16 ); #endif //cl_khr_fp16 /** @@ -7872,90 +8574,88 @@ half16 __ovld __cnfn minmag(half16, half16); * pointed to by iptr. */ #if defined(__opencl_c_generic_address_space) -float __ovld modf(float, float *); -float2 __ovld modf(float2, float2 *); -float3 __ovld modf(float3, float3 *); -float4 __ovld modf(float4, float4 *); -float8 __ovld modf(float8, float8 *); -float16 __ovld modf(float16, float16 *); +float __ovld modf(float, float *iptr); +float2 __ovld modf(float2, float2 *iptr); +float3 __ovld modf(float3, float3 *iptr); +float4 __ovld modf(float4, float4 *iptr); +float8 __ovld modf(float8, float8 *iptr); +float16 __ovld modf(float16, float16 *iptr); #ifdef cl_khr_fp64 -double __ovld modf(double, double *); -double2 __ovld modf(double2, double2 *); -double3 __ovld modf(double3, double3 *); -double4 __ovld modf(double4, double4 *); -double8 __ovld modf(double8, double8 *); -double16 __ovld modf(double16, double16 *); +double __ovld modf(double, double *iptr); +double2 __ovld modf(double2, double2 *iptr); +double3 __ovld modf(double3, double3 *iptr); +double4 __ovld modf(double4, double4 *iptr); +double8 __ovld modf(double8, double8 *iptr); +double16 __ovld modf(double16, double16 *iptr); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld modf(half, half *); -half2 __ovld modf(half2, half2 *); -half3 __ovld modf(half3, half3 *); -half4 __ovld modf(half4, half4 *); -half8 __ovld modf(half8, half8 *); -half16 __ovld modf(half16, half16 *); +half __ovld modf(half, half *iptr); +half2 __ovld modf(half2, half2 *iptr); +half3 __ovld modf(half3, half3 *iptr); +half4 __ovld modf(half4, half4 *iptr); +half8 __ovld modf(half8, half8 *iptr); +half16 __ovld modf(half16, half16 *iptr); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) -float __ovld modf(float, __global float *); -float2 __ovld modf(float2, __global float2 *); -float3 __ovld modf(float3, __global float3 *); -float4 __ovld modf(float4, __global float4 *); -float8 __ovld modf(float8, __global float8 *); -float16 __ovld modf(float16, __global float16 *); -float __ovld modf(float, __local float *); -float2 __ovld modf(float2, __local float2 *); -float3 __ovld modf(float3, __local float3 *); -float4 __ovld modf(float4, __local float4 *); -float8 __ovld modf(float8, __local float8 *); -float16 __ovld modf(float16, __local float16 *); -float __ovld modf(float, __private float *); -float2 __ovld modf(float2, __private float2 *); -float3 __ovld modf(float3, __private float3 *); -float4 __ovld modf(float4, __private float4 *); -float8 __ovld modf(float8, __private float8 *); -float16 __ovld modf(float16, __private float16 *); +#else +float __ovld modf(float, __global float *iptr); +float2 __ovld modf(float2, __global float2 *iptr); +float3 __ovld modf(float3, __global float3 *iptr); +float4 __ovld modf(float4, __global float4 *iptr); +float8 __ovld modf(float8, __global float8 *iptr); +float16 __ovld modf(float16, __global float16 *iptr); +float __ovld modf(float, __local float *iptr); +float2 __ovld modf(float2, __local float2 *iptr); +float3 __ovld modf(float3, __local float3 *iptr); +float4 __ovld modf(float4, __local float4 *iptr); +float8 __ovld modf(float8, __local float8 *iptr); +float16 __ovld modf(float16, __local float16 *iptr); +float __ovld modf(float, __private float *iptr); +float2 __ovld modf(float2, __private float2 *iptr); +float3 __ovld modf(float3, __private float3 *iptr); +float4 __ovld modf(float4, __private float4 *iptr); +float8 __ovld modf(float8, __private float8 *iptr); +float16 __ovld modf(float16, __private float16 *iptr); #ifdef cl_khr_fp64 -double __ovld modf(double, __global double *); -double2 __ovld modf(double2, __global double2 *); -double3 __ovld modf(double3, __global double3 *); -double4 __ovld modf(double4, __global double4 *); -double8 __ovld modf(double8, __global double8 *); -double16 __ovld modf(double16, __global double16 *); -double __ovld modf(double, __local double *); -double2 __ovld modf(double2, __local double2 *); -double3 __ovld modf(double3, __local double3 *); -double4 __ovld modf(double4, __local double4 *); -double8 __ovld modf(double8, __local double8 *); -double16 __ovld modf(double16, __local double16 *); -double __ovld modf(double, __private double *); -double2 __ovld modf(double2, __private double2 *); -double3 __ovld modf(double3, __private double3 *); -double4 __ovld modf(double4, __private double4 *); -double8 __ovld modf(double8, __private double8 *); -double16 __ovld modf(double16, __private double16 *); +double __ovld modf(double, __global double *iptr); +double2 __ovld modf(double2, __global double2 *iptr); +double3 __ovld modf(double3, __global double3 *iptr); +double4 __ovld modf(double4, __global double4 *iptr); +double8 __ovld modf(double8, __global double8 *iptr); +double16 __ovld modf(double16, __global double16 *iptr); +double __ovld modf(double, __local double *iptr); +double2 __ovld modf(double2, __local double2 *iptr); +double3 __ovld modf(double3, __local double3 *iptr); +double4 __ovld modf(double4, __local double4 *iptr); +double8 __ovld modf(double8, __local double8 *iptr); +double16 __ovld modf(double16, __local double16 *iptr); +double __ovld modf(double, __private double *iptr); +double2 __ovld modf(double2, __private double2 *iptr); +double3 __ovld modf(double3, __private double3 *iptr); +double4 __ovld modf(double4, __private double4 *iptr); +double8 __ovld modf(double8, __private double8 *iptr); +double16 __ovld modf(double16, __private double16 *iptr); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld modf(half, __global half *); -half2 __ovld modf(half2, __global half2 *); -half3 __ovld modf(half3, __global half3 *); -half4 __ovld modf(half4, __global half4 *); -half8 __ovld modf(half8, __global half8 *); -half16 __ovld modf(half16, __global half16 *); -half __ovld modf(half, __local half *); -half2 __ovld modf(half2, __local half2 *); -half3 __ovld modf(half3, __local half3 *); -half4 __ovld modf(half4, __local half4 *); -half8 __ovld modf(half8, __local half8 *); -half16 __ovld modf(half16, __local half16 *); -half __ovld modf(half, __private half *); -half2 __ovld modf(half2, __private half2 *); -half3 __ovld modf(half3, __private half3 *); -half4 __ovld modf(half4, __private half4 *); -half8 __ovld modf(half8, __private half8 *); -half16 __ovld modf(half16, __private half16 *); +half __ovld modf(half, __global half *iptr); +half2 __ovld modf(half2, __global half2 *iptr); +half3 __ovld modf(half3, __global half3 *iptr); +half4 __ovld modf(half4, __global half4 *iptr); +half8 __ovld modf(half8, __global half8 *iptr); +half16 __ovld modf(half16, __global half16 *iptr); +half __ovld modf(half, __local half *iptr); +half2 __ovld modf(half2, __local half2 *iptr); +half3 __ovld modf(half3, __local half3 *iptr); +half4 __ovld modf(half4, __local half4 *iptr); +half8 __ovld modf(half8, __local half8 *iptr); +half16 __ovld modf(half16, __local half16 *iptr); +half __ovld modf(half, __private half *iptr); +half2 __ovld modf(half2, __private half2 *iptr); +half3 __ovld modf(half3, __private half3 *iptr); +half4 __ovld modf(half4, __private half4 *iptr); +half8 __ovld modf(half8, __private half8 *iptr); +half16 __ovld modf(half16, __private half16 *iptr); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * Returns a quiet NaN. The nancode may be placed @@ -7987,109 +8687,109 @@ half16 __ovld __cnfn nan(ushort16); /** * Computes the next representable single-precision * floating-point value following x in the direction of - * y. Thus, if y is less than x, nextafter() returns the + * y. Thus, if y is less than, nextafter() returns the * largest representable floating-point number less * than x. */ -float __ovld __cnfn nextafter(float, float); -float2 __ovld __cnfn nextafter(float2, float2); -float3 __ovld __cnfn nextafter(float3, float3); -float4 __ovld __cnfn nextafter(float4, float4); -float8 __ovld __cnfn nextafter(float8, float8); -float16 __ovld __cnfn nextafter(float16, float16); +float __ovld __cnfn nextafter(float, float ); +float2 __ovld __cnfn nextafter(float2, float2 ); +float3 __ovld __cnfn nextafter(float3, float3 ); +float4 __ovld __cnfn nextafter(float4, float4 ); +float8 __ovld __cnfn nextafter(float8, float8 ); +float16 __ovld __cnfn nextafter(float16, float16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn nextafter(double, double); -double2 __ovld __cnfn nextafter(double2, double2); -double3 __ovld __cnfn nextafter(double3, double3); -double4 __ovld __cnfn nextafter(double4, double4); -double8 __ovld __cnfn nextafter(double8, double8); -double16 __ovld __cnfn nextafter(double16, double16); +double __ovld __cnfn nextafter(double, double ); +double2 __ovld __cnfn nextafter(double2, double2 ); +double3 __ovld __cnfn nextafter(double3, double3 ); +double4 __ovld __cnfn nextafter(double4, double4 ); +double8 __ovld __cnfn nextafter(double8, double8 ); +double16 __ovld __cnfn nextafter(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn nextafter(half, half); -half2 __ovld __cnfn nextafter(half2, half2); -half3 __ovld __cnfn nextafter(half3, half3); -half4 __ovld __cnfn nextafter(half4, half4); -half8 __ovld __cnfn nextafter(half8, half8); -half16 __ovld __cnfn nextafter(half16, half16); +half __ovld __cnfn nextafter(half, half ); +half2 __ovld __cnfn nextafter(half2, half2 ); +half3 __ovld __cnfn nextafter(half3, half3 ); +half4 __ovld __cnfn nextafter(half4, half4 ); +half8 __ovld __cnfn nextafter(half8, half8 ); +half16 __ovld __cnfn nextafter(half16, half16 ); #endif //cl_khr_fp16 /** * Compute x to the power y. */ -float __ovld __cnfn pow(float, float); -float2 __ovld __cnfn pow(float2, float2); -float3 __ovld __cnfn pow(float3, float3); -float4 __ovld __cnfn pow(float4, float4); -float8 __ovld __cnfn pow(float8, float8); -float16 __ovld __cnfn pow(float16, float16); +float __ovld __cnfn pow(float, float ); +float2 __ovld __cnfn pow(float2, float2 ); +float3 __ovld __cnfn pow(float3, float3 ); +float4 __ovld __cnfn pow(float4, float4 ); +float8 __ovld __cnfn pow(float8, float8 ); +float16 __ovld __cnfn pow(float16, float16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn pow(double, double); -double2 __ovld __cnfn pow(double2, double2); -double3 __ovld __cnfn pow(double3, double3); -double4 __ovld __cnfn pow(double4, double4); -double8 __ovld __cnfn pow(double8, double8); -double16 __ovld __cnfn pow(double16, double16); +double __ovld __cnfn pow(double, double ); +double2 __ovld __cnfn pow(double2, double2 ); +double3 __ovld __cnfn pow(double3, double3 ); +double4 __ovld __cnfn pow(double4, double4 ); +double8 __ovld __cnfn pow(double8, double8 ); +double16 __ovld __cnfn pow(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn pow(half, half); -half2 __ovld __cnfn pow(half2, half2); -half3 __ovld __cnfn pow(half3, half3); -half4 __ovld __cnfn pow(half4, half4); -half8 __ovld __cnfn pow(half8, half8); -half16 __ovld __cnfn pow(half16, half16); +half __ovld __cnfn pow(half, half ); +half2 __ovld __cnfn pow(half2, half2 ); +half3 __ovld __cnfn pow(half3, half3 ); +half4 __ovld __cnfn pow(half4, half4 ); +half8 __ovld __cnfn pow(half8, half8 ); +half16 __ovld __cnfn pow(half16, half16 ); #endif //cl_khr_fp16 /** - * Compute x to the power y, where y is an integer. + * Compute x to the power, where y is an integer. */ -float __ovld __cnfn pown(float, int); -float2 __ovld __cnfn pown(float2, int2); -float3 __ovld __cnfn pown(float3, int3); -float4 __ovld __cnfn pown(float4, int4); -float8 __ovld __cnfn pown(float8, int8); -float16 __ovld __cnfn pown(float16, int16); +float __ovld __cnfn pown(float, int ); +float2 __ovld __cnfn pown(float2, int2 ); +float3 __ovld __cnfn pown(float3, int3 ); +float4 __ovld __cnfn pown(float4, int4 ); +float8 __ovld __cnfn pown(float8, int8 ); +float16 __ovld __cnfn pown(float16, int16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn pown(double, int); -double2 __ovld __cnfn pown(double2, int2); -double3 __ovld __cnfn pown(double3, int3); -double4 __ovld __cnfn pown(double4, int4); -double8 __ovld __cnfn pown(double8, int8); -double16 __ovld __cnfn pown(double16, int16); +double __ovld __cnfn pown(double, int ); +double2 __ovld __cnfn pown(double2, int2 ); +double3 __ovld __cnfn pown(double3, int3 ); +double4 __ovld __cnfn pown(double4, int4 ); +double8 __ovld __cnfn pown(double8, int8 ); +double16 __ovld __cnfn pown(double16, int16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn pown(half, int); -half2 __ovld __cnfn pown(half2, int2); -half3 __ovld __cnfn pown(half3, int3); -half4 __ovld __cnfn pown(half4, int4); -half8 __ovld __cnfn pown(half8, int8); -half16 __ovld __cnfn pown(half16, int16); +half __ovld __cnfn pown(half, int ); +half2 __ovld __cnfn pown(half2, int2 ); +half3 __ovld __cnfn pown(half3, int3 ); +half4 __ovld __cnfn pown(half4, int4 ); +half8 __ovld __cnfn pown(half8, int8 ); +half16 __ovld __cnfn pown(half16, int16 ); #endif //cl_khr_fp16 /** - * Compute x to the power y, where x is >= 0. + * Compute x to the power, where x is >= 0. */ -float __ovld __cnfn powr(float, float); -float2 __ovld __cnfn powr(float2, float2); -float3 __ovld __cnfn powr(float3, float3); -float4 __ovld __cnfn powr(float4, float4); -float8 __ovld __cnfn powr(float8, float8); -float16 __ovld __cnfn powr(float16, float16); +float __ovld __cnfn powr(float, float ); +float2 __ovld __cnfn powr(float2, float2 ); +float3 __ovld __cnfn powr(float3, float3 ); +float4 __ovld __cnfn powr(float4, float4 ); +float8 __ovld __cnfn powr(float8, float8 ); +float16 __ovld __cnfn powr(float16, float16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn powr(double, double); -double2 __ovld __cnfn powr(double2, double2); -double3 __ovld __cnfn powr(double3, double3); -double4 __ovld __cnfn powr(double4, double4); -double8 __ovld __cnfn powr(double8, double8); -double16 __ovld __cnfn powr(double16, double16); +double __ovld __cnfn powr(double, double ); +double2 __ovld __cnfn powr(double2, double2 ); +double3 __ovld __cnfn powr(double3, double3 ); +double4 __ovld __cnfn powr(double4, double4 ); +double8 __ovld __cnfn powr(double8, double8 ); +double16 __ovld __cnfn powr(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn powr(half, half); -half2 __ovld __cnfn powr(half2, half2); -half3 __ovld __cnfn powr(half3, half3); -half4 __ovld __cnfn powr(half4, half4); -half8 __ovld __cnfn powr(half8, half8); -half16 __ovld __cnfn powr(half16, half16); +half __ovld __cnfn powr(half, half ); +half2 __ovld __cnfn powr(half2, half2 ); +half3 __ovld __cnfn powr(half3, half3 ); +half4 __ovld __cnfn powr(half4, half4 ); +half8 __ovld __cnfn powr(half8, half8 ); +half16 __ovld __cnfn powr(half16, half16 ); #endif //cl_khr_fp16 /** @@ -8098,27 +8798,27 @@ half16 __ovld __cnfn powr(half16, half16); * are two integers closest to x/y, n shall be the even * one. If r is zero, it is given the same sign as x. */ -float __ovld __cnfn remainder(float, float); -float2 __ovld __cnfn remainder(float2, float2); -float3 __ovld __cnfn remainder(float3, float3); -float4 __ovld __cnfn remainder(float4, float4); -float8 __ovld __cnfn remainder(float8, float8); -float16 __ovld __cnfn remainder(float16, float16); +float __ovld __cnfn remainder(float, float ); +float2 __ovld __cnfn remainder(float2, float2 ); +float3 __ovld __cnfn remainder(float3, float3 ); +float4 __ovld __cnfn remainder(float4, float4 ); +float8 __ovld __cnfn remainder(float8, float8 ); +float16 __ovld __cnfn remainder(float16, float16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn remainder(double, double); -double2 __ovld __cnfn remainder(double2, double2); -double3 __ovld __cnfn remainder(double3, double3); -double4 __ovld __cnfn remainder(double4, double4); -double8 __ovld __cnfn remainder(double8, double8); -double16 __ovld __cnfn remainder(double16, double16); +double __ovld __cnfn remainder(double, double ); +double2 __ovld __cnfn remainder(double2, double2 ); +double3 __ovld __cnfn remainder(double3, double3 ); +double4 __ovld __cnfn remainder(double4, double4 ); +double8 __ovld __cnfn remainder(double8, double8 ); +double16 __ovld __cnfn remainder(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn remainder(half, half); -half2 __ovld __cnfn remainder(half2, half2); -half3 __ovld __cnfn remainder(half3, half3); -half4 __ovld __cnfn remainder(half4, half4); -half8 __ovld __cnfn remainder(half8, half8); -half16 __ovld __cnfn remainder(half16, half16); +half __ovld __cnfn remainder(half, half ); +half2 __ovld __cnfn remainder(half2, half2 ); +half3 __ovld __cnfn remainder(half3, half3 ); +half4 __ovld __cnfn remainder(half4, half4 ); +half8 __ovld __cnfn remainder(half8, half8 ); +half16 __ovld __cnfn remainder(half16, half16 ); #endif //cl_khr_fp16 /** @@ -8155,10 +8855,9 @@ half3 __ovld remquo(half3, half3, int3 *); half4 __ovld remquo(half4, half4, int4 *); half8 __ovld remquo(half8, half8, int8 *); half16 __ovld remquo(half16, half16, int16 *); -#endif //cl_khr_fp16 -#endif //defined(__opencl_c_generic_address_space) -#if defined(__opencl_c_named_address_space_builtins) +#endif //cl_khr_fp16 +#else float __ovld remquo(float, float, __global int *); float2 __ovld remquo(float2, float2, __global int2 *); float3 __ovld remquo(float3, float3, __global int3 *); @@ -8217,7 +8916,7 @@ half4 __ovld remquo(half4, half4, __private int4 *); half8 __ovld remquo(half8, half8, __private int8 *); half16 __ovld remquo(half16, half16, __private int16 *); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * Round to integral value (using round to nearest * even rounding mode) in floating-point format. @@ -8250,27 +8949,27 @@ half16 __ovld __cnfn rint(half16); /** * Compute x to the power 1/y. */ -float __ovld __cnfn rootn(float, int); -float2 __ovld __cnfn rootn(float2, int2); -float3 __ovld __cnfn rootn(float3, int3); -float4 __ovld __cnfn rootn(float4, int4); -float8 __ovld __cnfn rootn(float8, int8); -float16 __ovld __cnfn rootn(float16, int16); +float __ovld __cnfn rootn(float, int ); +float2 __ovld __cnfn rootn(float2, int2 ); +float3 __ovld __cnfn rootn(float3, int3 ); +float4 __ovld __cnfn rootn(float4, int4 ); +float8 __ovld __cnfn rootn(float8, int8 ); +float16 __ovld __cnfn rootn(float16, int16 ); #ifdef cl_khr_fp64 -double __ovld __cnfn rootn(double, int); -double2 __ovld __cnfn rootn(double2, int2); -double3 __ovld __cnfn rootn(double3, int3); -double4 __ovld __cnfn rootn(double4, int4); -double8 __ovld __cnfn rootn(double8, int8); -double16 __ovld __cnfn rootn(double16, int16); +double __ovld __cnfn rootn(double, int ); +double2 __ovld __cnfn rootn(double2, int2 ); +double3 __ovld __cnfn rootn(double3, int3 ); +double4 __ovld __cnfn rootn(double4, int4 ); +double8 __ovld __cnfn rootn(double8, int8 ); +double16 __ovld __cnfn rootn(double16, int16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn rootn(half, int); -half2 __ovld __cnfn rootn(half2, int2); -half3 __ovld __cnfn rootn(half3, int3); -half4 __ovld __cnfn rootn(half4, int4); -half8 __ovld __cnfn rootn(half8, int8); -half16 __ovld __cnfn rootn(half16, int16); +half __ovld __cnfn rootn(half, int ); +half2 __ovld __cnfn rootn(half2, int2 ); +half3 __ovld __cnfn rootn(half3, int3 ); +half4 __ovld __cnfn rootn(half4, int4 ); +half8 __ovld __cnfn rootn(half8, int8 ); +half16 __ovld __cnfn rootn(half16, int16 ); #endif //cl_khr_fp16 /** @@ -8278,27 +8977,27 @@ half16 __ovld __cnfn rootn(half16, int16); * halfway cases away from zero, regardless of the * current rounding direction. */ -float __ovld __cnfn round(float); -float2 __ovld __cnfn round(float2); -float3 __ovld __cnfn round(float3); -float4 __ovld __cnfn round(float4); -float8 __ovld __cnfn round(float8); -float16 __ovld __cnfn round(float16); +float __ovld __cnfn round(float x); +float2 __ovld __cnfn round(float2 x); +float3 __ovld __cnfn round(float3 x); +float4 __ovld __cnfn round(float4 x); +float8 __ovld __cnfn round(float8 x); +float16 __ovld __cnfn round(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn round(double); -double2 __ovld __cnfn round(double2); -double3 __ovld __cnfn round(double3); -double4 __ovld __cnfn round(double4); -double8 __ovld __cnfn round(double8); -double16 __ovld __cnfn round(double16); +double __ovld __cnfn round(double x); +double2 __ovld __cnfn round(double2 x); +double3 __ovld __cnfn round(double3 x); +double4 __ovld __cnfn round(double4 x); +double8 __ovld __cnfn round(double8 x); +double16 __ovld __cnfn round(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn round(half); -half2 __ovld __cnfn round(half2); -half3 __ovld __cnfn round(half3); -half4 __ovld __cnfn round(half4); -half8 __ovld __cnfn round(half8); -half16 __ovld __cnfn round(half16); +half __ovld __cnfn round(half x); +half2 __ovld __cnfn round(half2 x); +half3 __ovld __cnfn round(half3 x); +half4 __ovld __cnfn round(half4 x); +half8 __ovld __cnfn round(half8 x); +half16 __ovld __cnfn round(half16 x); #endif //cl_khr_fp16 /** @@ -8359,90 +9058,88 @@ half16 __ovld __cnfn sin(half16); * in cosval. */ #if defined(__opencl_c_generic_address_space) -float __ovld sincos(float, float *); -float2 __ovld sincos(float2, float2 *); -float3 __ovld sincos(float3, float3 *); -float4 __ovld sincos(float4, float4 *); -float8 __ovld sincos(float8, float8 *); -float16 __ovld sincos(float16, float16 *); +float __ovld sincos(float, float *cosval); +float2 __ovld sincos(float2, float2 *cosval); +float3 __ovld sincos(float3, float3 *cosval); +float4 __ovld sincos(float4, float4 *cosval); +float8 __ovld sincos(float8, float8 *cosval); +float16 __ovld sincos(float16, float16 *cosval); #ifdef cl_khr_fp64 -double __ovld sincos(double, double *); -double2 __ovld sincos(double2, double2 *); -double3 __ovld sincos(double3, double3 *); -double4 __ovld sincos(double4, double4 *); -double8 __ovld sincos(double8, double8 *); -double16 __ovld sincos(double16, double16 *); +double __ovld sincos(double, double *cosval); +double2 __ovld sincos(double2, double2 *cosval); +double3 __ovld sincos(double3, double3 *cosval); +double4 __ovld sincos(double4, double4 *cosval); +double8 __ovld sincos(double8, double8 *cosval); +double16 __ovld sincos(double16, double16 *cosval); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld sincos(half, half *); -half2 __ovld sincos(half2, half2 *); -half3 __ovld sincos(half3, half3 *); -half4 __ovld sincos(half4, half4 *); -half8 __ovld sincos(half8, half8 *); -half16 __ovld sincos(half16, half16 *); +half __ovld sincos(half, half *cosval); +half2 __ovld sincos(half2, half2 *cosval); +half3 __ovld sincos(half3, half3 *cosval); +half4 __ovld sincos(half4, half4 *cosval); +half8 __ovld sincos(half8, half8 *cosval); +half16 __ovld sincos(half16, half16 *cosval); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) -float __ovld sincos(float, __global float *); -float2 __ovld sincos(float2, __global float2 *); -float3 __ovld sincos(float3, __global float3 *); -float4 __ovld sincos(float4, __global float4 *); -float8 __ovld sincos(float8, __global float8 *); -float16 __ovld sincos(float16, __global float16 *); -float __ovld sincos(float, __local float *); -float2 __ovld sincos(float2, __local float2 *); -float3 __ovld sincos(float3, __local float3 *); -float4 __ovld sincos(float4, __local float4 *); -float8 __ovld sincos(float8, __local float8 *); -float16 __ovld sincos(float16, __local float16 *); -float __ovld sincos(float, __private float *); -float2 __ovld sincos(float2, __private float2 *); -float3 __ovld sincos(float3, __private float3 *); -float4 __ovld sincos(float4, __private float4 *); -float8 __ovld sincos(float8, __private float8 *); -float16 __ovld sincos(float16, __private float16 *); +#else +float __ovld sincos(float, __global float *cosval); +float2 __ovld sincos(float2, __global float2 *cosval); +float3 __ovld sincos(float3, __global float3 *cosval); +float4 __ovld sincos(float4, __global float4 *cosval); +float8 __ovld sincos(float8, __global float8 *cosval); +float16 __ovld sincos(float16, __global float16 *cosval); +float __ovld sincos(float, __local float *cosval); +float2 __ovld sincos(float2, __local float2 *cosval); +float3 __ovld sincos(float3, __local float3 *cosval); +float4 __ovld sincos(float4, __local float4 *cosval); +float8 __ovld sincos(float8, __local float8 *cosval); +float16 __ovld sincos(float16, __local float16 *cosval); +float __ovld sincos(float, __private float *cosval); +float2 __ovld sincos(float2, __private float2 *cosval); +float3 __ovld sincos(float3, __private float3 *cosval); +float4 __ovld sincos(float4, __private float4 *cosval); +float8 __ovld sincos(float8, __private float8 *cosval); +float16 __ovld sincos(float16, __private float16 *cosval); #ifdef cl_khr_fp64 -double __ovld sincos(double, __global double *); -double2 __ovld sincos(double2, __global double2 *); -double3 __ovld sincos(double3, __global double3 *); -double4 __ovld sincos(double4, __global double4 *); -double8 __ovld sincos(double8, __global double8 *); -double16 __ovld sincos(double16, __global double16 *); -double __ovld sincos(double, __local double *); -double2 __ovld sincos(double2, __local double2 *); -double3 __ovld sincos(double3, __local double3 *); -double4 __ovld sincos(double4, __local double4 *); -double8 __ovld sincos(double8, __local double8 *); -double16 __ovld sincos(double16, __local double16 *); -double __ovld sincos(double, __private double *); -double2 __ovld sincos(double2, __private double2 *); -double3 __ovld sincos(double3, __private double3 *); -double4 __ovld sincos(double4, __private double4 *); -double8 __ovld sincos(double8, __private double8 *); -double16 __ovld sincos(double16, __private double16 *); +double __ovld sincos(double, __global double *cosval); +double2 __ovld sincos(double2, __global double2 *cosval); +double3 __ovld sincos(double3, __global double3 *cosval); +double4 __ovld sincos(double4, __global double4 *cosval); +double8 __ovld sincos(double8, __global double8 *cosval); +double16 __ovld sincos(double16, __global double16 *cosval); +double __ovld sincos(double, __local double *cosval); +double2 __ovld sincos(double2, __local double2 *cosval); +double3 __ovld sincos(double3, __local double3 *cosval); +double4 __ovld sincos(double4, __local double4 *cosval); +double8 __ovld sincos(double8, __local double8 *cosval); +double16 __ovld sincos(double16, __local double16 *cosval); +double __ovld sincos(double, __private double *cosval); +double2 __ovld sincos(double2, __private double2 *cosval); +double3 __ovld sincos(double3, __private double3 *cosval); +double4 __ovld sincos(double4, __private double4 *cosval); +double8 __ovld sincos(double8, __private double8 *cosval); +double16 __ovld sincos(double16, __private double16 *cosval); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld sincos(half, __global half *); -half2 __ovld sincos(half2, __global half2 *); -half3 __ovld sincos(half3, __global half3 *); -half4 __ovld sincos(half4, __global half4 *); -half8 __ovld sincos(half8, __global half8 *); -half16 __ovld sincos(half16, __global half16 *); -half __ovld sincos(half, __local half *); -half2 __ovld sincos(half2, __local half2 *); -half3 __ovld sincos(half3, __local half3 *); -half4 __ovld sincos(half4, __local half4 *); -half8 __ovld sincos(half8, __local half8 *); -half16 __ovld sincos(half16, __local half16 *); -half __ovld sincos(half, __private half *); -half2 __ovld sincos(half2, __private half2 *); -half3 __ovld sincos(half3, __private half3 *); -half4 __ovld sincos(half4, __private half4 *); -half8 __ovld sincos(half8, __private half8 *); -half16 __ovld sincos(half16, __private half16 *); +half __ovld sincos(half, __global half *cosval); +half2 __ovld sincos(half2, __global half2 *cosval); +half3 __ovld sincos(half3, __global half3 *cosval); +half4 __ovld sincos(half4, __global half4 *cosval); +half8 __ovld sincos(half8, __global half8 *cosval); +half16 __ovld sincos(half16, __global half16 *cosval); +half __ovld sincos(half, __local half *cosval); +half2 __ovld sincos(half2, __local half2 *cosval); +half3 __ovld sincos(half3, __local half3 *cosval); +half4 __ovld sincos(half4, __local half4 *cosval); +half8 __ovld sincos(half8, __local half8 *cosval); +half16 __ovld sincos(half16, __local half16 *cosval); +half __ovld sincos(half, __private half *cosval); +half2 __ovld sincos(half2, __private half2 *cosval); +half3 __ovld sincos(half3, __private half3 *cosval); +half4 __ovld sincos(half4, __private half4 *cosval); +half8 __ovld sincos(half8, __private half8 *cosval); +half16 __ovld sincos(half16, __private half16 *cosval); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * Compute hyperbolic sine. @@ -8473,27 +9170,53 @@ half16 __ovld __cnfn sinh(half16); /** * Compute sin (PI * x). */ -float __ovld __cnfn sinpi(float); -float2 __ovld __cnfn sinpi(float2); -float3 __ovld __cnfn sinpi(float3); -float4 __ovld __cnfn sinpi(float4); -float8 __ovld __cnfn sinpi(float8); -float16 __ovld __cnfn sinpi(float16); +float __ovld __cnfn sinpi(float x); +float2 __ovld __cnfn sinpi(float2 x); +float3 __ovld __cnfn sinpi(float3 x); +float4 __ovld __cnfn sinpi(float4 x); +float8 __ovld __cnfn sinpi(float8 x); +float16 __ovld __cnfn sinpi(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn sinpi(double); -double2 __ovld __cnfn sinpi(double2); -double3 __ovld __cnfn sinpi(double3); -double4 __ovld __cnfn sinpi(double4); -double8 __ovld __cnfn sinpi(double8); -double16 __ovld __cnfn sinpi(double16); +double __ovld __cnfn sinpi(double x); +double2 __ovld __cnfn sinpi(double2 x); +double3 __ovld __cnfn sinpi(double3 x); +double4 __ovld __cnfn sinpi(double4 x); +double8 __ovld __cnfn sinpi(double8 x); +double16 __ovld __cnfn sinpi(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn sinpi(half); -half2 __ovld __cnfn sinpi(half2); -half3 __ovld __cnfn sinpi(half3); -half4 __ovld __cnfn sinpi(half4); -half8 __ovld __cnfn sinpi(half8); -half16 __ovld __cnfn sinpi(half16); +half __ovld __cnfn sinpi(half x); +half2 __ovld __cnfn sinpi(half2 x); +half3 __ovld __cnfn sinpi(half3 x); +half4 __ovld __cnfn sinpi(half4 x); +half8 __ovld __cnfn sinpi(half8 x); +half16 __ovld __cnfn sinpi(half16 x); +#endif //cl_khr_fp16 + +/** + * Compute square root. + */ +float __ovld __cnfn sqrt(float); +float2 __ovld __cnfn sqrt(float2); +float3 __ovld __cnfn sqrt(float3); +float4 __ovld __cnfn sqrt(float4); +float8 __ovld __cnfn sqrt(float8); +float16 __ovld __cnfn sqrt(float16); +#ifdef cl_khr_fp64 +double __ovld __cnfn sqrt(double); +double2 __ovld __cnfn sqrt(double2); +double3 __ovld __cnfn sqrt(double3); +double4 __ovld __cnfn sqrt(double4); +double8 __ovld __cnfn sqrt(double8); +double16 __ovld __cnfn sqrt(double16); +#endif //cl_khr_fp64 +#ifdef cl_khr_fp16 +half __ovld __cnfn sqrt(half); +half2 __ovld __cnfn sqrt(half2); +half3 __ovld __cnfn sqrt(half3); +half4 __ovld __cnfn sqrt(half4); +half8 __ovld __cnfn sqrt(half8); +half16 __ovld __cnfn sqrt(half16); #endif //cl_khr_fp16 /** @@ -8577,27 +9300,27 @@ half16 __ovld __cnfn tanh(half16); /** * Compute tan (PI * x). */ -float __ovld __cnfn tanpi(float); -float2 __ovld __cnfn tanpi(float2); -float3 __ovld __cnfn tanpi(float3); -float4 __ovld __cnfn tanpi(float4); -float8 __ovld __cnfn tanpi(float8); -float16 __ovld __cnfn tanpi(float16); +float __ovld __cnfn tanpi(float x); +float2 __ovld __cnfn tanpi(float2 x); +float3 __ovld __cnfn tanpi(float3 x); +float4 __ovld __cnfn tanpi(float4 x); +float8 __ovld __cnfn tanpi(float8 x); +float16 __ovld __cnfn tanpi(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn tanpi(double); -double2 __ovld __cnfn tanpi(double2); -double3 __ovld __cnfn tanpi(double3); -double4 __ovld __cnfn tanpi(double4); -double8 __ovld __cnfn tanpi(double8); -double16 __ovld __cnfn tanpi(double16); +double __ovld __cnfn tanpi(double x); +double2 __ovld __cnfn tanpi(double2 x); +double3 __ovld __cnfn tanpi(double3 x); +double4 __ovld __cnfn tanpi(double4 x); +double8 __ovld __cnfn tanpi(double8 x); +double16 __ovld __cnfn tanpi(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn tanpi(half); -half2 __ovld __cnfn tanpi(half2); -half3 __ovld __cnfn tanpi(half3); -half4 __ovld __cnfn tanpi(half4); -half8 __ovld __cnfn tanpi(half8); -half16 __ovld __cnfn tanpi(half16); +half __ovld __cnfn tanpi(half x); +half2 __ovld __cnfn tanpi(half2 x); +half3 __ovld __cnfn tanpi(half3 x); +half4 __ovld __cnfn tanpi(half4 x); +half8 __ovld __cnfn tanpi(half8 x); +half16 __ovld __cnfn tanpi(half16 x); #endif //cl_khr_fp16 /** @@ -8656,565 +9379,565 @@ half16 __ovld __cnfn trunc(half16); /** * Compute cosine. x must be in the range -2^16 ... +2^16. */ -float __ovld __cnfn half_cos(float); -float2 __ovld __cnfn half_cos(float2); -float3 __ovld __cnfn half_cos(float3); -float4 __ovld __cnfn half_cos(float4); -float8 __ovld __cnfn half_cos(float8); -float16 __ovld __cnfn half_cos(float16); +float __ovld __cnfn half_cos(float x); +float2 __ovld __cnfn half_cos(float2 x); +float3 __ovld __cnfn half_cos(float3 x); +float4 __ovld __cnfn half_cos(float4 x); +float8 __ovld __cnfn half_cos(float8 x); +float16 __ovld __cnfn half_cos(float16 x); /** * Compute x / y. */ -float __ovld __cnfn half_divide(float, float); -float2 __ovld __cnfn half_divide(float2, float2); -float3 __ovld __cnfn half_divide(float3, float3); -float4 __ovld __cnfn half_divide(float4, float4); -float8 __ovld __cnfn half_divide(float8, float8); -float16 __ovld __cnfn half_divide(float16, float16); +float __ovld __cnfn half_divide(float, float ); +float2 __ovld __cnfn half_divide(float2, float2 ); +float3 __ovld __cnfn half_divide(float3, float3 ); +float4 __ovld __cnfn half_divide(float4, float4 ); +float8 __ovld __cnfn half_divide(float8, float8 ); +float16 __ovld __cnfn half_divide(float16, float16 ); /** * Compute the base- e exponential of x. */ -float __ovld __cnfn half_exp(float); -float2 __ovld __cnfn half_exp(float2); -float3 __ovld __cnfn half_exp(float3); -float4 __ovld __cnfn half_exp(float4); -float8 __ovld __cnfn half_exp(float8); -float16 __ovld __cnfn half_exp(float16); +float __ovld __cnfn half_exp(float x); +float2 __ovld __cnfn half_exp(float2 x); +float3 __ovld __cnfn half_exp(float3 x); +float4 __ovld __cnfn half_exp(float4 x); +float8 __ovld __cnfn half_exp(float8 x); +float16 __ovld __cnfn half_exp(float16 x); /** * Compute the base- 2 exponential of x. */ -float __ovld __cnfn half_exp2(float); -float2 __ovld __cnfn half_exp2(float2); -float3 __ovld __cnfn half_exp2(float3); -float4 __ovld __cnfn half_exp2(float4); -float8 __ovld __cnfn half_exp2(float8); -float16 __ovld __cnfn half_exp2(float16); +float __ovld __cnfn half_exp2(float x); +float2 __ovld __cnfn half_exp2(float2 x); +float3 __ovld __cnfn half_exp2(float3 x); +float4 __ovld __cnfn half_exp2(float4 x); +float8 __ovld __cnfn half_exp2(float8 x); +float16 __ovld __cnfn half_exp2(float16 x); /** * Compute the base- 10 exponential of x. */ -float __ovld __cnfn half_exp10(float); -float2 __ovld __cnfn half_exp10(float2); -float3 __ovld __cnfn half_exp10(float3); -float4 __ovld __cnfn half_exp10(float4); -float8 __ovld __cnfn half_exp10(float8); -float16 __ovld __cnfn half_exp10(float16); +float __ovld __cnfn half_exp10(float x); +float2 __ovld __cnfn half_exp10(float2 x); +float3 __ovld __cnfn half_exp10(float3 x); +float4 __ovld __cnfn half_exp10(float4 x); +float8 __ovld __cnfn half_exp10(float8 x); +float16 __ovld __cnfn half_exp10(float16 x); /** * Compute natural logarithm. */ -float __ovld __cnfn half_log(float); -float2 __ovld __cnfn half_log(float2); -float3 __ovld __cnfn half_log(float3); -float4 __ovld __cnfn half_log(float4); -float8 __ovld __cnfn half_log(float8); -float16 __ovld __cnfn half_log(float16); +float __ovld __cnfn half_log(float x); +float2 __ovld __cnfn half_log(float2 x); +float3 __ovld __cnfn half_log(float3 x); +float4 __ovld __cnfn half_log(float4 x); +float8 __ovld __cnfn half_log(float8 x); +float16 __ovld __cnfn half_log(float16 x); /** * Compute a base 2 logarithm. */ -float __ovld __cnfn half_log2(float); -float2 __ovld __cnfn half_log2(float2); -float3 __ovld __cnfn half_log2(float3); -float4 __ovld __cnfn half_log2(float4); -float8 __ovld __cnfn half_log2(float8); -float16 __ovld __cnfn half_log2(float16); +float __ovld __cnfn half_log2(float x); +float2 __ovld __cnfn half_log2(float2 x); +float3 __ovld __cnfn half_log2(float3 x); +float4 __ovld __cnfn half_log2(float4 x); +float8 __ovld __cnfn half_log2(float8 x); +float16 __ovld __cnfn half_log2(float16 x); /** * Compute a base 10 logarithm. */ -float __ovld __cnfn half_log10(float); -float2 __ovld __cnfn half_log10(float2); -float3 __ovld __cnfn half_log10(float3); -float4 __ovld __cnfn half_log10(float4); -float8 __ovld __cnfn half_log10(float8); -float16 __ovld __cnfn half_log10(float16); +float __ovld __cnfn half_log10(float x); +float2 __ovld __cnfn half_log10(float2 x); +float3 __ovld __cnfn half_log10(float3 x); +float4 __ovld __cnfn half_log10(float4 x); +float8 __ovld __cnfn half_log10(float8 x); +float16 __ovld __cnfn half_log10(float16 x); /** - * Compute x to the power y, where x is >= 0. + * Compute x to the power, where x is >= 0. */ -float __ovld __cnfn half_powr(float, float); -float2 __ovld __cnfn half_powr(float2, float2); -float3 __ovld __cnfn half_powr(float3, float3); -float4 __ovld __cnfn half_powr(float4, float4); -float8 __ovld __cnfn half_powr(float8, float8); -float16 __ovld __cnfn half_powr(float16, float16); +float __ovld __cnfn half_powr(float, float ); +float2 __ovld __cnfn half_powr(float2, float2 ); +float3 __ovld __cnfn half_powr(float3, float3 ); +float4 __ovld __cnfn half_powr(float4, float4 ); +float8 __ovld __cnfn half_powr(float8, float8 ); +float16 __ovld __cnfn half_powr(float16, float16 ); /** * Compute reciprocal. */ -float __ovld __cnfn half_recip(float); -float2 __ovld __cnfn half_recip(float2); -float3 __ovld __cnfn half_recip(float3); -float4 __ovld __cnfn half_recip(float4); -float8 __ovld __cnfn half_recip(float8); -float16 __ovld __cnfn half_recip(float16); +float __ovld __cnfn half_recip(float x); +float2 __ovld __cnfn half_recip(float2 x); +float3 __ovld __cnfn half_recip(float3 x); +float4 __ovld __cnfn half_recip(float4 x); +float8 __ovld __cnfn half_recip(float8 x); +float16 __ovld __cnfn half_recip(float16 x); /** * Compute inverse square root. */ -float __ovld __cnfn half_rsqrt(float); -float2 __ovld __cnfn half_rsqrt(float2); -float3 __ovld __cnfn half_rsqrt(float3); -float4 __ovld __cnfn half_rsqrt(float4); -float8 __ovld __cnfn half_rsqrt(float8); -float16 __ovld __cnfn half_rsqrt(float16); +float __ovld __cnfn half_rsqrt(float x); +float2 __ovld __cnfn half_rsqrt(float2 x); +float3 __ovld __cnfn half_rsqrt(float3 x); +float4 __ovld __cnfn half_rsqrt(float4 x); +float8 __ovld __cnfn half_rsqrt(float8 x); +float16 __ovld __cnfn half_rsqrt(float16 x); /** * Compute sine. x must be in the range -2^16 ... +2^16. */ -float __ovld __cnfn half_sin(float); -float2 __ovld __cnfn half_sin(float2); -float3 __ovld __cnfn half_sin(float3); -float4 __ovld __cnfn half_sin(float4); -float8 __ovld __cnfn half_sin(float8); -float16 __ovld __cnfn half_sin(float16); +float __ovld __cnfn half_sin(float x); +float2 __ovld __cnfn half_sin(float2 x); +float3 __ovld __cnfn half_sin(float3 x); +float4 __ovld __cnfn half_sin(float4 x); +float8 __ovld __cnfn half_sin(float8 x); +float16 __ovld __cnfn half_sin(float16 x); /** * Compute square root. */ -float __ovld __cnfn half_sqrt(float); -float2 __ovld __cnfn half_sqrt(float2); -float3 __ovld __cnfn half_sqrt(float3); -float4 __ovld __cnfn half_sqrt(float4); -float8 __ovld __cnfn half_sqrt(float8); -float16 __ovld __cnfn half_sqrt(float16); +float __ovld __cnfn half_sqrt(float x); +float2 __ovld __cnfn half_sqrt(float2 x); +float3 __ovld __cnfn half_sqrt(float3 x); +float4 __ovld __cnfn half_sqrt(float4 x); +float8 __ovld __cnfn half_sqrt(float8 x); +float16 __ovld __cnfn half_sqrt(float16 x); /** * Compute tangent. x must be in the range -216 ... +216. */ -float __ovld __cnfn half_tan(float); -float2 __ovld __cnfn half_tan(float2); -float3 __ovld __cnfn half_tan(float3); -float4 __ovld __cnfn half_tan(float4); -float8 __ovld __cnfn half_tan(float8); -float16 __ovld __cnfn half_tan(float16); +float __ovld __cnfn half_tan(float x); +float2 __ovld __cnfn half_tan(float2 x); +float3 __ovld __cnfn half_tan(float3 x); +float4 __ovld __cnfn half_tan(float4 x); +float8 __ovld __cnfn half_tan(float8 x); +float16 __ovld __cnfn half_tan(float16 x); /** * Compute cosine over an implementation-defined range. * The maximum error is implementation-defined. */ -float __ovld __cnfn native_cos(float); -float2 __ovld __cnfn native_cos(float2); -float3 __ovld __cnfn native_cos(float3); -float4 __ovld __cnfn native_cos(float4); -float8 __ovld __cnfn native_cos(float8); -float16 __ovld __cnfn native_cos(float16); +float __ovld __cnfn native_cos(float x); +float2 __ovld __cnfn native_cos(float2 x); +float3 __ovld __cnfn native_cos(float3 x); +float4 __ovld __cnfn native_cos(float4 x); +float8 __ovld __cnfn native_cos(float8 x); +float16 __ovld __cnfn native_cos(float16 x); /** * Compute x / y over an implementation-defined range. * The maximum error is implementation-defined. */ -float __ovld __cnfn native_divide(float, float); -float2 __ovld __cnfn native_divide(float2, float2); -float3 __ovld __cnfn native_divide(float3, float3); -float4 __ovld __cnfn native_divide(float4, float4); -float8 __ovld __cnfn native_divide(float8, float8); -float16 __ovld __cnfn native_divide(float16, float16); +float __ovld __cnfn native_divide(float, float ); +float2 __ovld __cnfn native_divide(float2, float2 ); +float3 __ovld __cnfn native_divide(float3, float3 ); +float4 __ovld __cnfn native_divide(float4, float4 ); +float8 __ovld __cnfn native_divide(float8, float8 ); +float16 __ovld __cnfn native_divide(float16, float16 ); /** * Compute the base- e exponential of x over an * implementation-defined range. The maximum error is * implementation-defined. */ -float __ovld __cnfn native_exp(float); -float2 __ovld __cnfn native_exp(float2); -float3 __ovld __cnfn native_exp(float3); -float4 __ovld __cnfn native_exp(float4); -float8 __ovld __cnfn native_exp(float8); -float16 __ovld __cnfn native_exp(float16); +float __ovld __cnfn native_exp(float x); +float2 __ovld __cnfn native_exp(float2 x); +float3 __ovld __cnfn native_exp(float3 x); +float4 __ovld __cnfn native_exp(float4 x); +float8 __ovld __cnfn native_exp(float8 x); +float16 __ovld __cnfn native_exp(float16 x); /** * Compute the base- 2 exponential of x over an * implementation-defined range. The maximum error is * implementation-defined. */ -float __ovld __cnfn native_exp2(float); -float2 __ovld __cnfn native_exp2(float2); -float3 __ovld __cnfn native_exp2(float3); -float4 __ovld __cnfn native_exp2(float4); -float8 __ovld __cnfn native_exp2(float8); -float16 __ovld __cnfn native_exp2(float16); +float __ovld __cnfn native_exp2(float x); +float2 __ovld __cnfn native_exp2(float2 x); +float3 __ovld __cnfn native_exp2(float3 x); +float4 __ovld __cnfn native_exp2(float4 x); +float8 __ovld __cnfn native_exp2(float8 x); +float16 __ovld __cnfn native_exp2(float16 x); /** * Compute the base- 10 exponential of x over an * implementation-defined range. The maximum error is * implementation-defined. */ -float __ovld __cnfn native_exp10(float); -float2 __ovld __cnfn native_exp10(float2); -float3 __ovld __cnfn native_exp10(float3); -float4 __ovld __cnfn native_exp10(float4); -float8 __ovld __cnfn native_exp10(float8); -float16 __ovld __cnfn native_exp10(float16); +float __ovld __cnfn native_exp10(float x); +float2 __ovld __cnfn native_exp10(float2 x); +float3 __ovld __cnfn native_exp10(float3 x); +float4 __ovld __cnfn native_exp10(float4 x); +float8 __ovld __cnfn native_exp10(float8 x); +float16 __ovld __cnfn native_exp10(float16 x); /** * Compute natural logarithm over an implementationdefined * range. The maximum error is implementation * defined. */ -float __ovld __cnfn native_log(float); -float2 __ovld __cnfn native_log(float2); -float3 __ovld __cnfn native_log(float3); -float4 __ovld __cnfn native_log(float4); -float8 __ovld __cnfn native_log(float8); -float16 __ovld __cnfn native_log(float16); +float __ovld __cnfn native_log(float x); +float2 __ovld __cnfn native_log(float2 x); +float3 __ovld __cnfn native_log(float3 x); +float4 __ovld __cnfn native_log(float4 x); +float8 __ovld __cnfn native_log(float8 x); +float16 __ovld __cnfn native_log(float16 x); /** * Compute a base 2 logarithm over an implementationdefined * range. The maximum error is implementationdefined. */ -float __ovld __cnfn native_log2(float); -float2 __ovld __cnfn native_log2(float2); -float3 __ovld __cnfn native_log2(float3); -float4 __ovld __cnfn native_log2(float4); -float8 __ovld __cnfn native_log2(float8); -float16 __ovld __cnfn native_log2(float16); +float __ovld __cnfn native_log2(float x); +float2 __ovld __cnfn native_log2(float2 x); +float3 __ovld __cnfn native_log2(float3 x); +float4 __ovld __cnfn native_log2(float4 x); +float8 __ovld __cnfn native_log2(float8 x); +float16 __ovld __cnfn native_log2(float16 x); /** * Compute a base 10 logarithm over an implementationdefined * range. The maximum error is implementationdefined. */ -float __ovld __cnfn native_log10(float); -float2 __ovld __cnfn native_log10(float2); -float3 __ovld __cnfn native_log10(float3); -float4 __ovld __cnfn native_log10(float4); -float8 __ovld __cnfn native_log10(float8); -float16 __ovld __cnfn native_log10(float16); +float __ovld __cnfn native_log10(float x); +float2 __ovld __cnfn native_log10(float2 x); +float3 __ovld __cnfn native_log10(float3 x); +float4 __ovld __cnfn native_log10(float4 x); +float8 __ovld __cnfn native_log10(float8 x); +float16 __ovld __cnfn native_log10(float16 x); /** - * Compute x to the power y, where x is >= 0. The range of + * Compute x to the power, where x is >= 0. The range of * x and y are implementation-defined. The maximum error * is implementation-defined. */ -float __ovld __cnfn native_powr(float, float); -float2 __ovld __cnfn native_powr(float2, float2); -float3 __ovld __cnfn native_powr(float3, float3); -float4 __ovld __cnfn native_powr(float4, float4); -float8 __ovld __cnfn native_powr(float8, float8); -float16 __ovld __cnfn native_powr(float16, float16); +float __ovld __cnfn native_powr(float, float ); +float2 __ovld __cnfn native_powr(float2, float2 ); +float3 __ovld __cnfn native_powr(float3, float3 ); +float4 __ovld __cnfn native_powr(float4, float4 ); +float8 __ovld __cnfn native_powr(float8, float8 ); +float16 __ovld __cnfn native_powr(float16, float16 ); /** * Compute reciprocal over an implementation-defined * range. The maximum error is implementation-defined. */ -float __ovld __cnfn native_recip(float); -float2 __ovld __cnfn native_recip(float2); -float3 __ovld __cnfn native_recip(float3); -float4 __ovld __cnfn native_recip(float4); -float8 __ovld __cnfn native_recip(float8); -float16 __ovld __cnfn native_recip(float16); +float __ovld __cnfn native_recip(float x); +float2 __ovld __cnfn native_recip(float2 x); +float3 __ovld __cnfn native_recip(float3 x); +float4 __ovld __cnfn native_recip(float4 x); +float8 __ovld __cnfn native_recip(float8 x); +float16 __ovld __cnfn native_recip(float16 x); /** * Compute inverse square root over an implementationdefined * range. The maximum error is implementationdefined. */ -float __ovld __cnfn native_rsqrt(float); -float2 __ovld __cnfn native_rsqrt(float2); -float3 __ovld __cnfn native_rsqrt(float3); -float4 __ovld __cnfn native_rsqrt(float4); -float8 __ovld __cnfn native_rsqrt(float8); -float16 __ovld __cnfn native_rsqrt(float16); +float __ovld __cnfn native_rsqrt(float x); +float2 __ovld __cnfn native_rsqrt(float2 x); +float3 __ovld __cnfn native_rsqrt(float3 x); +float4 __ovld __cnfn native_rsqrt(float4 x); +float8 __ovld __cnfn native_rsqrt(float8 x); +float16 __ovld __cnfn native_rsqrt(float16 x); /** * Compute sine over an implementation-defined range. * The maximum error is implementation-defined. */ -float __ovld __cnfn native_sin(float); -float2 __ovld __cnfn native_sin(float2); -float3 __ovld __cnfn native_sin(float3); -float4 __ovld __cnfn native_sin(float4); -float8 __ovld __cnfn native_sin(float8); -float16 __ovld __cnfn native_sin(float16); +float __ovld __cnfn native_sin(float x); +float2 __ovld __cnfn native_sin(float2 x); +float3 __ovld __cnfn native_sin(float3 x); +float4 __ovld __cnfn native_sin(float4 x); +float8 __ovld __cnfn native_sin(float8 x); +float16 __ovld __cnfn native_sin(float16 x); /** * Compute square root over an implementation-defined * range. The maximum error is implementation-defined. */ -float __ovld __cnfn native_sqrt(float); -float2 __ovld __cnfn native_sqrt(float2); -float3 __ovld __cnfn native_sqrt(float3); -float4 __ovld __cnfn native_sqrt(float4); -float8 __ovld __cnfn native_sqrt(float8); -float16 __ovld __cnfn native_sqrt(float16); +float __ovld __cnfn native_sqrt(float x); +float2 __ovld __cnfn native_sqrt(float2 x); +float3 __ovld __cnfn native_sqrt(float3 x); +float4 __ovld __cnfn native_sqrt(float4 x); +float8 __ovld __cnfn native_sqrt(float8 x); +float16 __ovld __cnfn native_sqrt(float16 x); /** * Compute tangent over an implementation-defined range. * The maximum error is implementation-defined. */ -float __ovld __cnfn native_tan(float); -float2 __ovld __cnfn native_tan(float2); -float3 __ovld __cnfn native_tan(float3); -float4 __ovld __cnfn native_tan(float4); -float8 __ovld __cnfn native_tan(float8); -float16 __ovld __cnfn native_tan(float16); +float __ovld __cnfn native_tan(float x); +float2 __ovld __cnfn native_tan(float2 x); +float3 __ovld __cnfn native_tan(float3 x); +float4 __ovld __cnfn native_tan(float4 x); +float8 __ovld __cnfn native_tan(float8 x); +float16 __ovld __cnfn native_tan(float16 x); // OpenCL v1.1 s6.11.3, v1.2 s6.12.3, v2.0 s6.13.3 - Integer Functions /** * Returns | x |. */ -uchar __ovld __cnfn abs(char); -uchar __ovld __cnfn abs(uchar); -uchar2 __ovld __cnfn abs(char2); -uchar2 __ovld __cnfn abs(uchar2); -uchar3 __ovld __cnfn abs(char3); -uchar3 __ovld __cnfn abs(uchar3); -uchar4 __ovld __cnfn abs(char4); -uchar4 __ovld __cnfn abs(uchar4); -uchar8 __ovld __cnfn abs(char8); -uchar8 __ovld __cnfn abs(uchar8); -uchar16 __ovld __cnfn abs(char16); -uchar16 __ovld __cnfn abs(uchar16); -ushort __ovld __cnfn abs(short); -ushort __ovld __cnfn abs(ushort); -ushort2 __ovld __cnfn abs(short2); -ushort2 __ovld __cnfn abs(ushort2); -ushort3 __ovld __cnfn abs(short3); -ushort3 __ovld __cnfn abs(ushort3); -ushort4 __ovld __cnfn abs(short4); -ushort4 __ovld __cnfn abs(ushort4); -ushort8 __ovld __cnfn abs(short8); -ushort8 __ovld __cnfn abs(ushort8); -ushort16 __ovld __cnfn abs(short16); -ushort16 __ovld __cnfn abs(ushort16); -uint __ovld __cnfn abs(int); -uint __ovld __cnfn abs(uint); -uint2 __ovld __cnfn abs(int2); -uint2 __ovld __cnfn abs(uint2); -uint3 __ovld __cnfn abs(int3); -uint3 __ovld __cnfn abs(uint3); -uint4 __ovld __cnfn abs(int4); -uint4 __ovld __cnfn abs(uint4); -uint8 __ovld __cnfn abs(int8); -uint8 __ovld __cnfn abs(uint8); -uint16 __ovld __cnfn abs(int16); -uint16 __ovld __cnfn abs(uint16); -ulong __ovld __cnfn abs(long); -ulong __ovld __cnfn abs(ulong); -ulong2 __ovld __cnfn abs(long2); -ulong2 __ovld __cnfn abs(ulong2); -ulong3 __ovld __cnfn abs(long3); -ulong3 __ovld __cnfn abs(ulong3); -ulong4 __ovld __cnfn abs(long4); -ulong4 __ovld __cnfn abs(ulong4); -ulong8 __ovld __cnfn abs(long8); -ulong8 __ovld __cnfn abs(ulong8); -ulong16 __ovld __cnfn abs(long16); -ulong16 __ovld __cnfn abs(ulong16); +uchar __ovld __cnfn abs(char x); +uchar __ovld __cnfn abs(uchar x); +uchar2 __ovld __cnfn abs(char2 x); +uchar2 __ovld __cnfn abs(uchar2 x); +uchar3 __ovld __cnfn abs(char3 x); +uchar3 __ovld __cnfn abs(uchar3 x); +uchar4 __ovld __cnfn abs(char4 x); +uchar4 __ovld __cnfn abs(uchar4 x); +uchar8 __ovld __cnfn abs(char8 x); +uchar8 __ovld __cnfn abs(uchar8 x); +uchar16 __ovld __cnfn abs(char16 x); +uchar16 __ovld __cnfn abs(uchar16 x); +ushort __ovld __cnfn abs(short x); +ushort __ovld __cnfn abs(ushort x); +ushort2 __ovld __cnfn abs(short2 x); +ushort2 __ovld __cnfn abs(ushort2 x); +ushort3 __ovld __cnfn abs(short3 x); +ushort3 __ovld __cnfn abs(ushort3 x); +ushort4 __ovld __cnfn abs(short4 x); +ushort4 __ovld __cnfn abs(ushort4 x); +ushort8 __ovld __cnfn abs(short8 x); +ushort8 __ovld __cnfn abs(ushort8 x); +ushort16 __ovld __cnfn abs(short16 x); +ushort16 __ovld __cnfn abs(ushort16 x); +uint __ovld __cnfn abs(int x); +uint __ovld __cnfn abs(uint x); +uint2 __ovld __cnfn abs(int2 x); +uint2 __ovld __cnfn abs(uint2 x); +uint3 __ovld __cnfn abs(int3 x); +uint3 __ovld __cnfn abs(uint3 x); +uint4 __ovld __cnfn abs(int4 x); +uint4 __ovld __cnfn abs(uint4 x); +uint8 __ovld __cnfn abs(int8 x); +uint8 __ovld __cnfn abs(uint8 x); +uint16 __ovld __cnfn abs(int16 x); +uint16 __ovld __cnfn abs(uint16 x); +ulong __ovld __cnfn abs(long x); +ulong __ovld __cnfn abs(ulong x); +ulong2 __ovld __cnfn abs(long2 x); +ulong2 __ovld __cnfn abs(ulong2 x); +ulong3 __ovld __cnfn abs(long3 x); +ulong3 __ovld __cnfn abs(ulong3 x); +ulong4 __ovld __cnfn abs(long4 x); +ulong4 __ovld __cnfn abs(ulong4 x); +ulong8 __ovld __cnfn abs(long8 x); +ulong8 __ovld __cnfn abs(ulong8 x); +ulong16 __ovld __cnfn abs(long16 x); +ulong16 __ovld __cnfn abs(ulong16 x); /** * Returns | x - y | without modulo overflow. */ -uchar __ovld __cnfn abs_diff(char, char); -uchar __ovld __cnfn abs_diff(uchar, uchar); -uchar2 __ovld __cnfn abs_diff(char2, char2); -uchar2 __ovld __cnfn abs_diff(uchar2, uchar2); -uchar3 __ovld __cnfn abs_diff(char3, char3); -uchar3 __ovld __cnfn abs_diff(uchar3, uchar3); -uchar4 __ovld __cnfn abs_diff(char4, char4); -uchar4 __ovld __cnfn abs_diff(uchar4, uchar4); -uchar8 __ovld __cnfn abs_diff(char8, char8); -uchar8 __ovld __cnfn abs_diff(uchar8, uchar8); -uchar16 __ovld __cnfn abs_diff(char16, char16); -uchar16 __ovld __cnfn abs_diff(uchar16, uchar16); -ushort __ovld __cnfn abs_diff(short, short); -ushort __ovld __cnfn abs_diff(ushort, ushort); -ushort2 __ovld __cnfn abs_diff(short2, short2); -ushort2 __ovld __cnfn abs_diff(ushort2, ushort2); -ushort3 __ovld __cnfn abs_diff(short3, short3); -ushort3 __ovld __cnfn abs_diff(ushort3, ushort3); -ushort4 __ovld __cnfn abs_diff(short4, short4); -ushort4 __ovld __cnfn abs_diff(ushort4, ushort4); -ushort8 __ovld __cnfn abs_diff(short8, short8); -ushort8 __ovld __cnfn abs_diff(ushort8, ushort8); -ushort16 __ovld __cnfn abs_diff(short16, short16); -ushort16 __ovld __cnfn abs_diff(ushort16, ushort16); -uint __ovld __cnfn abs_diff(int, int); -uint __ovld __cnfn abs_diff(uint, uint); -uint2 __ovld __cnfn abs_diff(int2, int2); -uint2 __ovld __cnfn abs_diff(uint2, uint2); -uint3 __ovld __cnfn abs_diff(int3, int3); -uint3 __ovld __cnfn abs_diff(uint3, uint3); -uint4 __ovld __cnfn abs_diff(int4, int4); -uint4 __ovld __cnfn abs_diff(uint4, uint4); -uint8 __ovld __cnfn abs_diff(int8, int8); -uint8 __ovld __cnfn abs_diff(uint8, uint8); -uint16 __ovld __cnfn abs_diff(int16, int16); -uint16 __ovld __cnfn abs_diff(uint16, uint16); -ulong __ovld __cnfn abs_diff(long, long); -ulong __ovld __cnfn abs_diff(ulong, ulong); -ulong2 __ovld __cnfn abs_diff(long2, long2); -ulong2 __ovld __cnfn abs_diff(ulong2, ulong2); -ulong3 __ovld __cnfn abs_diff(long3, long3); -ulong3 __ovld __cnfn abs_diff(ulong3, ulong3); -ulong4 __ovld __cnfn abs_diff(long4, long4); -ulong4 __ovld __cnfn abs_diff(ulong4, ulong4); -ulong8 __ovld __cnfn abs_diff(long8, long8); -ulong8 __ovld __cnfn abs_diff(ulong8, ulong8); -ulong16 __ovld __cnfn abs_diff(long16, long16); -ulong16 __ovld __cnfn abs_diff(ulong16, ulong16); +uchar __ovld __cnfn abs_diff(char, char ); +uchar __ovld __cnfn abs_diff(uchar, uchar ); +uchar2 __ovld __cnfn abs_diff(char2, char2 ); +uchar2 __ovld __cnfn abs_diff(uchar2, uchar2 ); +uchar3 __ovld __cnfn abs_diff(char3, char3 ); +uchar3 __ovld __cnfn abs_diff(uchar3, uchar3 ); +uchar4 __ovld __cnfn abs_diff(char4, char4 ); +uchar4 __ovld __cnfn abs_diff(uchar4, uchar4 ); +uchar8 __ovld __cnfn abs_diff(char8, char8 ); +uchar8 __ovld __cnfn abs_diff(uchar8, uchar8 ); +uchar16 __ovld __cnfn abs_diff(char16, char16 ); +uchar16 __ovld __cnfn abs_diff(uchar16, uchar16 ); +ushort __ovld __cnfn abs_diff(short, short ); +ushort __ovld __cnfn abs_diff(ushort, ushort ); +ushort2 __ovld __cnfn abs_diff(short2, short2 ); +ushort2 __ovld __cnfn abs_diff(ushort2, ushort2 ); +ushort3 __ovld __cnfn abs_diff(short3, short3 ); +ushort3 __ovld __cnfn abs_diff(ushort3, ushort3 ); +ushort4 __ovld __cnfn abs_diff(short4, short4 ); +ushort4 __ovld __cnfn abs_diff(ushort4, ushort4 ); +ushort8 __ovld __cnfn abs_diff(short8, short8 ); +ushort8 __ovld __cnfn abs_diff(ushort8, ushort8 ); +ushort16 __ovld __cnfn abs_diff(short16, short16 ); +ushort16 __ovld __cnfn abs_diff(ushort16, ushort16 ); +uint __ovld __cnfn abs_diff(int, int ); +uint __ovld __cnfn abs_diff(uint, uint ); +uint2 __ovld __cnfn abs_diff(int2, int2 ); +uint2 __ovld __cnfn abs_diff(uint2, uint2 ); +uint3 __ovld __cnfn abs_diff(int3, int3 ); +uint3 __ovld __cnfn abs_diff(uint3, uint3 ); +uint4 __ovld __cnfn abs_diff(int4, int4 ); +uint4 __ovld __cnfn abs_diff(uint4, uint4 ); +uint8 __ovld __cnfn abs_diff(int8, int8 ); +uint8 __ovld __cnfn abs_diff(uint8, uint8 ); +uint16 __ovld __cnfn abs_diff(int16, int16 ); +uint16 __ovld __cnfn abs_diff(uint16, uint16 ); +ulong __ovld __cnfn abs_diff(long, long ); +ulong __ovld __cnfn abs_diff(ulong, ulong ); +ulong2 __ovld __cnfn abs_diff(long2, long2 ); +ulong2 __ovld __cnfn abs_diff(ulong2, ulong2 ); +ulong3 __ovld __cnfn abs_diff(long3, long3 ); +ulong3 __ovld __cnfn abs_diff(ulong3, ulong3 ); +ulong4 __ovld __cnfn abs_diff(long4, long4 ); +ulong4 __ovld __cnfn abs_diff(ulong4, ulong4 ); +ulong8 __ovld __cnfn abs_diff(long8, long8 ); +ulong8 __ovld __cnfn abs_diff(ulong8, ulong8 ); +ulong16 __ovld __cnfn abs_diff(long16, long16 ); +ulong16 __ovld __cnfn abs_diff(ulong16, ulong16 ); /** * Returns x + y and saturates the result. */ -char __ovld __cnfn add_sat(char, char); -uchar __ovld __cnfn add_sat(uchar, uchar); -char2 __ovld __cnfn add_sat(char2, char2); -uchar2 __ovld __cnfn add_sat(uchar2, uchar2); -char3 __ovld __cnfn add_sat(char3, char3); -uchar3 __ovld __cnfn add_sat(uchar3, uchar3); -char4 __ovld __cnfn add_sat(char4, char4); -uchar4 __ovld __cnfn add_sat(uchar4, uchar4); -char8 __ovld __cnfn add_sat(char8, char8); -uchar8 __ovld __cnfn add_sat(uchar8, uchar8); -char16 __ovld __cnfn add_sat(char16, char16); -uchar16 __ovld __cnfn add_sat(uchar16, uchar16); -short __ovld __cnfn add_sat(short, short); -ushort __ovld __cnfn add_sat(ushort, ushort); -short2 __ovld __cnfn add_sat(short2, short2); -ushort2 __ovld __cnfn add_sat(ushort2, ushort2); -short3 __ovld __cnfn add_sat(short3, short3); -ushort3 __ovld __cnfn add_sat(ushort3, ushort3); -short4 __ovld __cnfn add_sat(short4, short4); -ushort4 __ovld __cnfn add_sat(ushort4, ushort4); -short8 __ovld __cnfn add_sat(short8, short8); -ushort8 __ovld __cnfn add_sat(ushort8, ushort8); -short16 __ovld __cnfn add_sat(short16, short16); -ushort16 __ovld __cnfn add_sat(ushort16, ushort16); -int __ovld __cnfn add_sat(int, int); -uint __ovld __cnfn add_sat(uint, uint); -int2 __ovld __cnfn add_sat(int2, int2); -uint2 __ovld __cnfn add_sat(uint2, uint2); -int3 __ovld __cnfn add_sat(int3, int3); -uint3 __ovld __cnfn add_sat(uint3, uint3); -int4 __ovld __cnfn add_sat(int4, int4); -uint4 __ovld __cnfn add_sat(uint4, uint4); -int8 __ovld __cnfn add_sat(int8, int8); -uint8 __ovld __cnfn add_sat(uint8, uint8); -int16 __ovld __cnfn add_sat(int16, int16); -uint16 __ovld __cnfn add_sat(uint16, uint16); -long __ovld __cnfn add_sat(long, long); -ulong __ovld __cnfn add_sat(ulong, ulong); -long2 __ovld __cnfn add_sat(long2, long2); -ulong2 __ovld __cnfn add_sat(ulong2, ulong2); -long3 __ovld __cnfn add_sat(long3, long3); -ulong3 __ovld __cnfn add_sat(ulong3, ulong3); -long4 __ovld __cnfn add_sat(long4, long4); -ulong4 __ovld __cnfn add_sat(ulong4, ulong4); -long8 __ovld __cnfn add_sat(long8, long8); -ulong8 __ovld __cnfn add_sat(ulong8, ulong8); -long16 __ovld __cnfn add_sat(long16, long16); -ulong16 __ovld __cnfn add_sat(ulong16, ulong16); +char __ovld __cnfn add_sat(char, char ); +uchar __ovld __cnfn add_sat(uchar, uchar ); +char2 __ovld __cnfn add_sat(char2, char2 ); +uchar2 __ovld __cnfn add_sat(uchar2, uchar2 ); +char3 __ovld __cnfn add_sat(char3, char3 ); +uchar3 __ovld __cnfn add_sat(uchar3, uchar3 ); +char4 __ovld __cnfn add_sat(char4, char4 ); +uchar4 __ovld __cnfn add_sat(uchar4, uchar4 ); +char8 __ovld __cnfn add_sat(char8, char8 ); +uchar8 __ovld __cnfn add_sat(uchar8, uchar8 ); +char16 __ovld __cnfn add_sat(char16, char16 ); +uchar16 __ovld __cnfn add_sat(uchar16, uchar16 ); +short __ovld __cnfn add_sat(short, short ); +ushort __ovld __cnfn add_sat(ushort, ushort ); +short2 __ovld __cnfn add_sat(short2, short2 ); +ushort2 __ovld __cnfn add_sat(ushort2, ushort2 ); +short3 __ovld __cnfn add_sat(short3, short3 ); +ushort3 __ovld __cnfn add_sat(ushort3, ushort3 ); +short4 __ovld __cnfn add_sat(short4, short4 ); +ushort4 __ovld __cnfn add_sat(ushort4, ushort4 ); +short8 __ovld __cnfn add_sat(short8, short8 ); +ushort8 __ovld __cnfn add_sat(ushort8, ushort8 ); +short16 __ovld __cnfn add_sat(short16, short16 ); +ushort16 __ovld __cnfn add_sat(ushort16, ushort16 ); +int __ovld __cnfn add_sat(int, int ); +uint __ovld __cnfn add_sat(uint, uint ); +int2 __ovld __cnfn add_sat(int2, int2 ); +uint2 __ovld __cnfn add_sat(uint2, uint2 ); +int3 __ovld __cnfn add_sat(int3, int3 ); +uint3 __ovld __cnfn add_sat(uint3, uint3 ); +int4 __ovld __cnfn add_sat(int4, int4 ); +uint4 __ovld __cnfn add_sat(uint4, uint4 ); +int8 __ovld __cnfn add_sat(int8, int8 ); +uint8 __ovld __cnfn add_sat(uint8, uint8 ); +int16 __ovld __cnfn add_sat(int16, int16 ); +uint16 __ovld __cnfn add_sat(uint16, uint16 ); +long __ovld __cnfn add_sat(long, long ); +ulong __ovld __cnfn add_sat(ulong, ulong ); +long2 __ovld __cnfn add_sat(long2, long2 ); +ulong2 __ovld __cnfn add_sat(ulong2, ulong2 ); +long3 __ovld __cnfn add_sat(long3, long3 ); +ulong3 __ovld __cnfn add_sat(ulong3, ulong3 ); +long4 __ovld __cnfn add_sat(long4, long4 ); +ulong4 __ovld __cnfn add_sat(ulong4, ulong4 ); +long8 __ovld __cnfn add_sat(long8, long8 ); +ulong8 __ovld __cnfn add_sat(ulong8, ulong8 ); +long16 __ovld __cnfn add_sat(long16, long16 ); +ulong16 __ovld __cnfn add_sat(ulong16, ulong16 ); /** - * Returns (x + y) >> 1. The intermediate sum does + * Returns (x + ) >> 1. The intermediate sum does * not modulo overflow. */ -char __ovld __cnfn hadd(char, char); -uchar __ovld __cnfn hadd(uchar, uchar); -char2 __ovld __cnfn hadd(char2, char2); -uchar2 __ovld __cnfn hadd(uchar2, uchar2); -char3 __ovld __cnfn hadd(char3, char3); -uchar3 __ovld __cnfn hadd(uchar3, uchar3); -char4 __ovld __cnfn hadd(char4, char4); -uchar4 __ovld __cnfn hadd(uchar4, uchar4); -char8 __ovld __cnfn hadd(char8, char8); -uchar8 __ovld __cnfn hadd(uchar8, uchar8); -char16 __ovld __cnfn hadd(char16, char16); -uchar16 __ovld __cnfn hadd(uchar16, uchar16); -short __ovld __cnfn hadd(short, short); -ushort __ovld __cnfn hadd(ushort, ushort); -short2 __ovld __cnfn hadd(short2, short2); -ushort2 __ovld __cnfn hadd(ushort2, ushort2); -short3 __ovld __cnfn hadd(short3, short3); -ushort3 __ovld __cnfn hadd(ushort3, ushort3); -short4 __ovld __cnfn hadd(short4, short4); -ushort4 __ovld __cnfn hadd(ushort4, ushort4); -short8 __ovld __cnfn hadd(short8, short8); -ushort8 __ovld __cnfn hadd(ushort8, ushort8); -short16 __ovld __cnfn hadd(short16, short16); -ushort16 __ovld __cnfn hadd(ushort16, ushort16); -int __ovld __cnfn hadd(int, int); -uint __ovld __cnfn hadd(uint, uint); -int2 __ovld __cnfn hadd(int2, int2); -uint2 __ovld __cnfn hadd(uint2, uint2); -int3 __ovld __cnfn hadd(int3, int3); -uint3 __ovld __cnfn hadd(uint3, uint3); -int4 __ovld __cnfn hadd(int4, int4); -uint4 __ovld __cnfn hadd(uint4, uint4); -int8 __ovld __cnfn hadd(int8, int8); -uint8 __ovld __cnfn hadd(uint8, uint8); -int16 __ovld __cnfn hadd(int16, int16); -uint16 __ovld __cnfn hadd(uint16, uint16); -long __ovld __cnfn hadd(long, long); -ulong __ovld __cnfn hadd(ulong, ulong); -long2 __ovld __cnfn hadd(long2, long2); -ulong2 __ovld __cnfn hadd(ulong2, ulong2); -long3 __ovld __cnfn hadd(long3, long3); -ulong3 __ovld __cnfn hadd(ulong3, ulong3); -long4 __ovld __cnfn hadd(long4, long4); -ulong4 __ovld __cnfn hadd(ulong4, ulong4); -long8 __ovld __cnfn hadd(long8, long8); -ulong8 __ovld __cnfn hadd(ulong8, ulong8); -long16 __ovld __cnfn hadd(long16, long16); -ulong16 __ovld __cnfn hadd(ulong16, ulong16); +char __ovld __cnfn hadd(char, char ); +uchar __ovld __cnfn hadd(uchar, uchar ); +char2 __ovld __cnfn hadd(char2, char2 ); +uchar2 __ovld __cnfn hadd(uchar2, uchar2 ); +char3 __ovld __cnfn hadd(char3, char3 ); +uchar3 __ovld __cnfn hadd(uchar3, uchar3 ); +char4 __ovld __cnfn hadd(char4, char4 ); +uchar4 __ovld __cnfn hadd(uchar4, uchar4 ); +char8 __ovld __cnfn hadd(char8, char8 ); +uchar8 __ovld __cnfn hadd(uchar8, uchar8 ); +char16 __ovld __cnfn hadd(char16, char16 ); +uchar16 __ovld __cnfn hadd(uchar16, uchar16 ); +short __ovld __cnfn hadd(short, short ); +ushort __ovld __cnfn hadd(ushort, ushort ); +short2 __ovld __cnfn hadd(short2, short2 ); +ushort2 __ovld __cnfn hadd(ushort2, ushort2 ); +short3 __ovld __cnfn hadd(short3, short3 ); +ushort3 __ovld __cnfn hadd(ushort3, ushort3 ); +short4 __ovld __cnfn hadd(short4, short4 ); +ushort4 __ovld __cnfn hadd(ushort4, ushort4 ); +short8 __ovld __cnfn hadd(short8, short8 ); +ushort8 __ovld __cnfn hadd(ushort8, ushort8 ); +short16 __ovld __cnfn hadd(short16, short16 ); +ushort16 __ovld __cnfn hadd(ushort16, ushort16 ); +int __ovld __cnfn hadd(int, int ); +uint __ovld __cnfn hadd(uint, uint ); +int2 __ovld __cnfn hadd(int2, int2 ); +uint2 __ovld __cnfn hadd(uint2, uint2 ); +int3 __ovld __cnfn hadd(int3, int3 ); +uint3 __ovld __cnfn hadd(uint3, uint3 ); +int4 __ovld __cnfn hadd(int4, int4 ); +uint4 __ovld __cnfn hadd(uint4, uint4 ); +int8 __ovld __cnfn hadd(int8, int8 ); +uint8 __ovld __cnfn hadd(uint8, uint8 ); +int16 __ovld __cnfn hadd(int16, int16 ); +uint16 __ovld __cnfn hadd(uint16, uint16 ); +long __ovld __cnfn hadd(long, long ); +ulong __ovld __cnfn hadd(ulong, ulong ); +long2 __ovld __cnfn hadd(long2, long2 ); +ulong2 __ovld __cnfn hadd(ulong2, ulong2 ); +long3 __ovld __cnfn hadd(long3, long3 ); +ulong3 __ovld __cnfn hadd(ulong3, ulong3 ); +long4 __ovld __cnfn hadd(long4, long4 ); +ulong4 __ovld __cnfn hadd(ulong4, ulong4 ); +long8 __ovld __cnfn hadd(long8, long8 ); +ulong8 __ovld __cnfn hadd(ulong8, ulong8 ); +long16 __ovld __cnfn hadd(long16, long16 ); +ulong16 __ovld __cnfn hadd(ulong16, ulong16 ); /** * Returns (x + y + 1) >> 1. The intermediate sum * does not modulo overflow. */ -char __ovld __cnfn rhadd(char, char); -uchar __ovld __cnfn rhadd(uchar, uchar); -char2 __ovld __cnfn rhadd(char2, char2); -uchar2 __ovld __cnfn rhadd(uchar2, uchar2); -char3 __ovld __cnfn rhadd(char3, char3); -uchar3 __ovld __cnfn rhadd(uchar3, uchar3); -char4 __ovld __cnfn rhadd(char4, char4); -uchar4 __ovld __cnfn rhadd(uchar4, uchar4); -char8 __ovld __cnfn rhadd(char8, char8); -uchar8 __ovld __cnfn rhadd(uchar8, uchar8); -char16 __ovld __cnfn rhadd(char16, char16); -uchar16 __ovld __cnfn rhadd(uchar16, uchar16); -short __ovld __cnfn rhadd(short, short); -ushort __ovld __cnfn rhadd(ushort, ushort); -short2 __ovld __cnfn rhadd(short2, short2); -ushort2 __ovld __cnfn rhadd(ushort2, ushort2); -short3 __ovld __cnfn rhadd(short3, short3); -ushort3 __ovld __cnfn rhadd(ushort3, ushort3); -short4 __ovld __cnfn rhadd(short4, short4); -ushort4 __ovld __cnfn rhadd(ushort4, ushort4); -short8 __ovld __cnfn rhadd(short8, short8); -ushort8 __ovld __cnfn rhadd(ushort8, ushort8); -short16 __ovld __cnfn rhadd(short16, short16); -ushort16 __ovld __cnfn rhadd(ushort16, ushort16); -int __ovld __cnfn rhadd(int, int); -uint __ovld __cnfn rhadd(uint, uint); -int2 __ovld __cnfn rhadd(int2, int2); -uint2 __ovld __cnfn rhadd(uint2, uint2); -int3 __ovld __cnfn rhadd(int3, int3); -uint3 __ovld __cnfn rhadd(uint3, uint3); -int4 __ovld __cnfn rhadd(int4, int4); -uint4 __ovld __cnfn rhadd(uint4, uint4); -int8 __ovld __cnfn rhadd(int8, int8); -uint8 __ovld __cnfn rhadd(uint8, uint8); -int16 __ovld __cnfn rhadd(int16, int16); -uint16 __ovld __cnfn rhadd(uint16, uint16); -long __ovld __cnfn rhadd(long, long); -ulong __ovld __cnfn rhadd(ulong, ulong); -long2 __ovld __cnfn rhadd(long2, long2); -ulong2 __ovld __cnfn rhadd(ulong2, ulong2); -long3 __ovld __cnfn rhadd(long3, long3); -ulong3 __ovld __cnfn rhadd(ulong3, ulong3); -long4 __ovld __cnfn rhadd(long4, long4); -ulong4 __ovld __cnfn rhadd(ulong4, ulong4); -long8 __ovld __cnfn rhadd(long8, long8); -ulong8 __ovld __cnfn rhadd(ulong8, ulong8); -long16 __ovld __cnfn rhadd(long16, long16); -ulong16 __ovld __cnfn rhadd(ulong16, ulong16); +char __ovld __cnfn rhadd(char, char ); +uchar __ovld __cnfn rhadd(uchar, uchar ); +char2 __ovld __cnfn rhadd(char2, char2 ); +uchar2 __ovld __cnfn rhadd(uchar2, uchar2 ); +char3 __ovld __cnfn rhadd(char3, char3 ); +uchar3 __ovld __cnfn rhadd(uchar3, uchar3 ); +char4 __ovld __cnfn rhadd(char4, char4 ); +uchar4 __ovld __cnfn rhadd(uchar4, uchar4 ); +char8 __ovld __cnfn rhadd(char8, char8 ); +uchar8 __ovld __cnfn rhadd(uchar8, uchar8 ); +char16 __ovld __cnfn rhadd(char16, char16 ); +uchar16 __ovld __cnfn rhadd(uchar16, uchar16 ); +short __ovld __cnfn rhadd(short, short ); +ushort __ovld __cnfn rhadd(ushort, ushort ); +short2 __ovld __cnfn rhadd(short2, short2 ); +ushort2 __ovld __cnfn rhadd(ushort2, ushort2 ); +short3 __ovld __cnfn rhadd(short3, short3 ); +ushort3 __ovld __cnfn rhadd(ushort3, ushort3 ); +short4 __ovld __cnfn rhadd(short4, short4 ); +ushort4 __ovld __cnfn rhadd(ushort4, ushort4 ); +short8 __ovld __cnfn rhadd(short8, short8 ); +ushort8 __ovld __cnfn rhadd(ushort8, ushort8 ); +short16 __ovld __cnfn rhadd(short16, short16 ); +ushort16 __ovld __cnfn rhadd(ushort16, ushort16 ); +int __ovld __cnfn rhadd(int, int ); +uint __ovld __cnfn rhadd(uint, uint ); +int2 __ovld __cnfn rhadd(int2, int2 ); +uint2 __ovld __cnfn rhadd(uint2, uint2 ); +int3 __ovld __cnfn rhadd(int3, int3 ); +uint3 __ovld __cnfn rhadd(uint3, uint3 ); +int4 __ovld __cnfn rhadd(int4, int4 ); +uint4 __ovld __cnfn rhadd(uint4, uint4 ); +int8 __ovld __cnfn rhadd(int8, int8 ); +uint8 __ovld __cnfn rhadd(uint8, uint8 ); +int16 __ovld __cnfn rhadd(int16, int16 ); +uint16 __ovld __cnfn rhadd(uint16, uint16 ); +long __ovld __cnfn rhadd(long, long ); +ulong __ovld __cnfn rhadd(ulong, ulong ); +long2 __ovld __cnfn rhadd(long2, long2 ); +ulong2 __ovld __cnfn rhadd(ulong2, ulong2 ); +long3 __ovld __cnfn rhadd(long3, long3 ); +ulong3 __ovld __cnfn rhadd(ulong3, ulong3 ); +long4 __ovld __cnfn rhadd(long4, long4 ); +ulong4 __ovld __cnfn rhadd(ulong4, ulong4 ); +long8 __ovld __cnfn rhadd(long8, long8 ); +ulong8 __ovld __cnfn rhadd(ulong8, ulong8 ); +long16 __ovld __cnfn rhadd(long16, long16 ); +ulong16 __ovld __cnfn rhadd(ulong16, ulong16 ); /** * Returns min(max(x, minval), maxval). @@ -9310,112 +10033,112 @@ long16 __ovld __cnfn clamp(long16, long, long); ulong16 __ovld __cnfn clamp(ulong16, ulong, ulong); /** - * Returns the number of leading 0-bits in x, starting + * Returns the number of leading 0-bits in, starting * at the most significant bit position. */ -char __ovld __cnfn clz(char); -uchar __ovld __cnfn clz(uchar); -char2 __ovld __cnfn clz(char2); -uchar2 __ovld __cnfn clz(uchar2); -char3 __ovld __cnfn clz(char3); -uchar3 __ovld __cnfn clz(uchar3); -char4 __ovld __cnfn clz(char4); -uchar4 __ovld __cnfn clz(uchar4); -char8 __ovld __cnfn clz(char8); -uchar8 __ovld __cnfn clz(uchar8); -char16 __ovld __cnfn clz(char16); -uchar16 __ovld __cnfn clz(uchar16); -short __ovld __cnfn clz(short); -ushort __ovld __cnfn clz(ushort); -short2 __ovld __cnfn clz(short2); -ushort2 __ovld __cnfn clz(ushort2); -short3 __ovld __cnfn clz(short3); -ushort3 __ovld __cnfn clz(ushort3); -short4 __ovld __cnfn clz(short4); -ushort4 __ovld __cnfn clz(ushort4); -short8 __ovld __cnfn clz(short8); -ushort8 __ovld __cnfn clz(ushort8); -short16 __ovld __cnfn clz(short16); -ushort16 __ovld __cnfn clz(ushort16); -int __ovld __cnfn clz(int); -uint __ovld __cnfn clz(uint); -int2 __ovld __cnfn clz(int2); -uint2 __ovld __cnfn clz(uint2); -int3 __ovld __cnfn clz(int3); -uint3 __ovld __cnfn clz(uint3); -int4 __ovld __cnfn clz(int4); -uint4 __ovld __cnfn clz(uint4); -int8 __ovld __cnfn clz(int8); -uint8 __ovld __cnfn clz(uint8); -int16 __ovld __cnfn clz(int16); -uint16 __ovld __cnfn clz(uint16); -long __ovld __cnfn clz(long); -ulong __ovld __cnfn clz(ulong); -long2 __ovld __cnfn clz(long2); -ulong2 __ovld __cnfn clz(ulong2); -long3 __ovld __cnfn clz(long3); -ulong3 __ovld __cnfn clz(ulong3); -long4 __ovld __cnfn clz(long4); -ulong4 __ovld __cnfn clz(ulong4); -long8 __ovld __cnfn clz(long8); -ulong8 __ovld __cnfn clz(ulong8); -long16 __ovld __cnfn clz(long16); -ulong16 __ovld __cnfn clz(ulong16); +char __ovld __cnfn clz(char x); +uchar __ovld __cnfn clz(uchar x); +char2 __ovld __cnfn clz(char2 x); +uchar2 __ovld __cnfn clz(uchar2 x); +char3 __ovld __cnfn clz(char3 x); +uchar3 __ovld __cnfn clz(uchar3 x); +char4 __ovld __cnfn clz(char4 x); +uchar4 __ovld __cnfn clz(uchar4 x); +char8 __ovld __cnfn clz(char8 x); +uchar8 __ovld __cnfn clz(uchar8 x); +char16 __ovld __cnfn clz(char16 x); +uchar16 __ovld __cnfn clz(uchar16 x); +short __ovld __cnfn clz(short x); +ushort __ovld __cnfn clz(ushort x); +short2 __ovld __cnfn clz(short2 x); +ushort2 __ovld __cnfn clz(ushort2 x); +short3 __ovld __cnfn clz(short3 x); +ushort3 __ovld __cnfn clz(ushort3 x); +short4 __ovld __cnfn clz(short4 x); +ushort4 __ovld __cnfn clz(ushort4 x); +short8 __ovld __cnfn clz(short8 x); +ushort8 __ovld __cnfn clz(ushort8 x); +short16 __ovld __cnfn clz(short16 x); +ushort16 __ovld __cnfn clz(ushort16 x); +int __ovld __cnfn clz(int x); +uint __ovld __cnfn clz(uint x); +int2 __ovld __cnfn clz(int2 x); +uint2 __ovld __cnfn clz(uint2 x); +int3 __ovld __cnfn clz(int3 x); +uint3 __ovld __cnfn clz(uint3 x); +int4 __ovld __cnfn clz(int4 x); +uint4 __ovld __cnfn clz(uint4 x); +int8 __ovld __cnfn clz(int8 x); +uint8 __ovld __cnfn clz(uint8 x); +int16 __ovld __cnfn clz(int16 x); +uint16 __ovld __cnfn clz(uint16 x); +long __ovld __cnfn clz(long x); +ulong __ovld __cnfn clz(ulong x); +long2 __ovld __cnfn clz(long2 x); +ulong2 __ovld __cnfn clz(ulong2 x); +long3 __ovld __cnfn clz(long3 x); +ulong3 __ovld __cnfn clz(ulong3 x); +long4 __ovld __cnfn clz(long4 x); +ulong4 __ovld __cnfn clz(ulong4 x); +long8 __ovld __cnfn clz(long8 x); +ulong8 __ovld __cnfn clz(ulong8 x); +long16 __ovld __cnfn clz(long16 x); +ulong16 __ovld __cnfn clz(ulong16 x); /** * Returns the count of trailing 0-bits in x. If x is 0, * returns the size in bits of the type of x or - * component type of x, if x is a vector. + * component type of, if x is a vector. */ #if defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ >= CL_VERSION_2_0) -char __ovld __cnfn ctz(char); -uchar __ovld __cnfn ctz(uchar); -char2 __ovld __cnfn ctz(char2); -uchar2 __ovld __cnfn ctz(uchar2); -char3 __ovld __cnfn ctz(char3); -uchar3 __ovld __cnfn ctz(uchar3); -char4 __ovld __cnfn ctz(char4); -uchar4 __ovld __cnfn ctz(uchar4); -char8 __ovld __cnfn ctz(char8); -uchar8 __ovld __cnfn ctz(uchar8); -char16 __ovld __cnfn ctz(char16); -uchar16 __ovld __cnfn ctz(uchar16); -short __ovld __cnfn ctz(short); -ushort __ovld __cnfn ctz(ushort); -short2 __ovld __cnfn ctz(short2); -ushort2 __ovld __cnfn ctz(ushort2); -short3 __ovld __cnfn ctz(short3); -ushort3 __ovld __cnfn ctz(ushort3); -short4 __ovld __cnfn ctz(short4); -ushort4 __ovld __cnfn ctz(ushort4); -short8 __ovld __cnfn ctz(short8); -ushort8 __ovld __cnfn ctz(ushort8); -short16 __ovld __cnfn ctz(short16); -ushort16 __ovld __cnfn ctz(ushort16); -int __ovld __cnfn ctz(int); -uint __ovld __cnfn ctz(uint); -int2 __ovld __cnfn ctz(int2); -uint2 __ovld __cnfn ctz(uint2); -int3 __ovld __cnfn ctz(int3); -uint3 __ovld __cnfn ctz(uint3); -int4 __ovld __cnfn ctz(int4); -uint4 __ovld __cnfn ctz(uint4); -int8 __ovld __cnfn ctz(int8); -uint8 __ovld __cnfn ctz(uint8); -int16 __ovld __cnfn ctz(int16); -uint16 __ovld __cnfn ctz(uint16); -long __ovld __cnfn ctz(long); -ulong __ovld __cnfn ctz(ulong); -long2 __ovld __cnfn ctz(long2); -ulong2 __ovld __cnfn ctz(ulong2); -long3 __ovld __cnfn ctz(long3); -ulong3 __ovld __cnfn ctz(ulong3); -long4 __ovld __cnfn ctz(long4); -ulong4 __ovld __cnfn ctz(ulong4); -long8 __ovld __cnfn ctz(long8); -ulong8 __ovld __cnfn ctz(ulong8); -long16 __ovld __cnfn ctz(long16); -ulong16 __ovld __cnfn ctz(ulong16); +char __ovld __cnfn ctz(char x); +uchar __ovld __cnfn ctz(uchar x); +char2 __ovld __cnfn ctz(char2 x); +uchar2 __ovld __cnfn ctz(uchar2 x); +char3 __ovld __cnfn ctz(char3 x); +uchar3 __ovld __cnfn ctz(uchar3 x); +char4 __ovld __cnfn ctz(char4 x); +uchar4 __ovld __cnfn ctz(uchar4 x); +char8 __ovld __cnfn ctz(char8 x); +uchar8 __ovld __cnfn ctz(uchar8 x); +char16 __ovld __cnfn ctz(char16 x); +uchar16 __ovld __cnfn ctz(uchar16 x); +short __ovld __cnfn ctz(short x); +ushort __ovld __cnfn ctz(ushort x); +short2 __ovld __cnfn ctz(short2 x); +ushort2 __ovld __cnfn ctz(ushort2 x); +short3 __ovld __cnfn ctz(short3 x); +ushort3 __ovld __cnfn ctz(ushort3 x); +short4 __ovld __cnfn ctz(short4 x); +ushort4 __ovld __cnfn ctz(ushort4 x); +short8 __ovld __cnfn ctz(short8 x); +ushort8 __ovld __cnfn ctz(ushort8 x); +short16 __ovld __cnfn ctz(short16 x); +ushort16 __ovld __cnfn ctz(ushort16 x); +int __ovld __cnfn ctz(int x); +uint __ovld __cnfn ctz(uint x); +int2 __ovld __cnfn ctz(int2 x); +uint2 __ovld __cnfn ctz(uint2 x); +int3 __ovld __cnfn ctz(int3 x); +uint3 __ovld __cnfn ctz(uint3 x); +int4 __ovld __cnfn ctz(int4 x); +uint4 __ovld __cnfn ctz(uint4 x); +int8 __ovld __cnfn ctz(int8 x); +uint8 __ovld __cnfn ctz(uint8 x); +int16 __ovld __cnfn ctz(int16 x); +uint16 __ovld __cnfn ctz(uint16 x); +long __ovld __cnfn ctz(long x); +ulong __ovld __cnfn ctz(ulong x); +long2 __ovld __cnfn ctz(long2 x); +ulong2 __ovld __cnfn ctz(ulong2 x); +long3 __ovld __cnfn ctz(long3 x); +ulong3 __ovld __cnfn ctz(ulong3 x); +long4 __ovld __cnfn ctz(long4 x); +ulong4 __ovld __cnfn ctz(ulong4 x); +long8 __ovld __cnfn ctz(long8 x); +ulong8 __ovld __cnfn ctz(ulong8 x); +long16 __ovld __cnfn ctz(long16 x); +ulong16 __ovld __cnfn ctz(ulong16 x); #endif //defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ >= CL_VERSION_2_0) /** @@ -9523,241 +10246,241 @@ long16 __ovld __cnfn mad_sat(long16, long16, long16); ulong16 __ovld __cnfn mad_sat(ulong16, ulong16, ulong16); /** - * Returns y if x < y, otherwise it returns x. + * Returns y if x <, otherwise it returns x. */ -char __ovld __cnfn max(char, char); -uchar __ovld __cnfn max(uchar, uchar); -char2 __ovld __cnfn max(char2, char2); -uchar2 __ovld __cnfn max(uchar2, uchar2); -char3 __ovld __cnfn max(char3, char3); -uchar3 __ovld __cnfn max(uchar3, uchar3); -char4 __ovld __cnfn max(char4, char4); -uchar4 __ovld __cnfn max(uchar4, uchar4); -char8 __ovld __cnfn max(char8, char8); -uchar8 __ovld __cnfn max(uchar8, uchar8); -char16 __ovld __cnfn max(char16, char16); -uchar16 __ovld __cnfn max(uchar16, uchar16); -short __ovld __cnfn max(short, short); -ushort __ovld __cnfn max(ushort, ushort); -short2 __ovld __cnfn max(short2, short2); -ushort2 __ovld __cnfn max(ushort2, ushort2); -short3 __ovld __cnfn max(short3, short3); -ushort3 __ovld __cnfn max(ushort3, ushort3); -short4 __ovld __cnfn max(short4, short4); -ushort4 __ovld __cnfn max(ushort4, ushort4); -short8 __ovld __cnfn max(short8, short8); -ushort8 __ovld __cnfn max(ushort8, ushort8); -short16 __ovld __cnfn max(short16, short16); -ushort16 __ovld __cnfn max(ushort16, ushort16); -int __ovld __cnfn max(int, int); -uint __ovld __cnfn max(uint, uint); -int2 __ovld __cnfn max(int2, int2); -uint2 __ovld __cnfn max(uint2, uint2); -int3 __ovld __cnfn max(int3, int3); -uint3 __ovld __cnfn max(uint3, uint3); -int4 __ovld __cnfn max(int4, int4); -uint4 __ovld __cnfn max(uint4, uint4); -int8 __ovld __cnfn max(int8, int8); -uint8 __ovld __cnfn max(uint8, uint8); -int16 __ovld __cnfn max(int16, int16); -uint16 __ovld __cnfn max(uint16, uint16); -long __ovld __cnfn max(long, long); -ulong __ovld __cnfn max(ulong, ulong); -long2 __ovld __cnfn max(long2, long2); -ulong2 __ovld __cnfn max(ulong2, ulong2); -long3 __ovld __cnfn max(long3, long3); -ulong3 __ovld __cnfn max(ulong3, ulong3); -long4 __ovld __cnfn max(long4, long4); -ulong4 __ovld __cnfn max(ulong4, ulong4); -long8 __ovld __cnfn max(long8, long8); -ulong8 __ovld __cnfn max(ulong8, ulong8); -long16 __ovld __cnfn max(long16, long16); -ulong16 __ovld __cnfn max(ulong16, ulong16); -char2 __ovld __cnfn max(char2, char); -uchar2 __ovld __cnfn max(uchar2, uchar); -char3 __ovld __cnfn max(char3, char); -uchar3 __ovld __cnfn max(uchar3, uchar); -char4 __ovld __cnfn max(char4, char); -uchar4 __ovld __cnfn max(uchar4, uchar); -char8 __ovld __cnfn max(char8, char); -uchar8 __ovld __cnfn max(uchar8, uchar); -char16 __ovld __cnfn max(char16, char); -uchar16 __ovld __cnfn max(uchar16, uchar); -short2 __ovld __cnfn max(short2, short); -ushort2 __ovld __cnfn max(ushort2, ushort); -short3 __ovld __cnfn max(short3, short); -ushort3 __ovld __cnfn max(ushort3, ushort); -short4 __ovld __cnfn max(short4, short); -ushort4 __ovld __cnfn max(ushort4, ushort); -short8 __ovld __cnfn max(short8, short); -ushort8 __ovld __cnfn max(ushort8, ushort); -short16 __ovld __cnfn max(short16, short); -ushort16 __ovld __cnfn max(ushort16, ushort); -int2 __ovld __cnfn max(int2, int); -uint2 __ovld __cnfn max(uint2, uint); -int3 __ovld __cnfn max(int3, int); -uint3 __ovld __cnfn max(uint3, uint); -int4 __ovld __cnfn max(int4, int); -uint4 __ovld __cnfn max(uint4, uint); -int8 __ovld __cnfn max(int8, int); -uint8 __ovld __cnfn max(uint8, uint); -int16 __ovld __cnfn max(int16, int); -uint16 __ovld __cnfn max(uint16, uint); -long2 __ovld __cnfn max(long2, long); -ulong2 __ovld __cnfn max(ulong2, ulong); -long3 __ovld __cnfn max(long3, long); -ulong3 __ovld __cnfn max(ulong3, ulong); -long4 __ovld __cnfn max(long4, long); -ulong4 __ovld __cnfn max(ulong4, ulong); -long8 __ovld __cnfn max(long8, long); -ulong8 __ovld __cnfn max(ulong8, ulong); -long16 __ovld __cnfn max(long16, long); -ulong16 __ovld __cnfn max(ulong16, ulong); +char __ovld __cnfn max(char, char ); +uchar __ovld __cnfn max(uchar, uchar ); +char2 __ovld __cnfn max(char2, char2 ); +uchar2 __ovld __cnfn max(uchar2, uchar2 ); +char3 __ovld __cnfn max(char3, char3 ); +uchar3 __ovld __cnfn max(uchar3, uchar3 ); +char4 __ovld __cnfn max(char4, char4 ); +uchar4 __ovld __cnfn max(uchar4, uchar4 ); +char8 __ovld __cnfn max(char8, char8 ); +uchar8 __ovld __cnfn max(uchar8, uchar8 ); +char16 __ovld __cnfn max(char16, char16 ); +uchar16 __ovld __cnfn max(uchar16, uchar16 ); +short __ovld __cnfn max(short, short ); +ushort __ovld __cnfn max(ushort, ushort ); +short2 __ovld __cnfn max(short2, short2 ); +ushort2 __ovld __cnfn max(ushort2, ushort2 ); +short3 __ovld __cnfn max(short3, short3 ); +ushort3 __ovld __cnfn max(ushort3, ushort3 ); +short4 __ovld __cnfn max(short4, short4 ); +ushort4 __ovld __cnfn max(ushort4, ushort4 ); +short8 __ovld __cnfn max(short8, short8 ); +ushort8 __ovld __cnfn max(ushort8, ushort8 ); +short16 __ovld __cnfn max(short16, short16 ); +ushort16 __ovld __cnfn max(ushort16, ushort16 ); +int __ovld __cnfn max(int, int ); +uint __ovld __cnfn max(uint, uint ); +int2 __ovld __cnfn max(int2, int2 ); +uint2 __ovld __cnfn max(uint2, uint2 ); +int3 __ovld __cnfn max(int3, int3 ); +uint3 __ovld __cnfn max(uint3, uint3 ); +int4 __ovld __cnfn max(int4, int4 ); +uint4 __ovld __cnfn max(uint4, uint4 ); +int8 __ovld __cnfn max(int8, int8 ); +uint8 __ovld __cnfn max(uint8, uint8 ); +int16 __ovld __cnfn max(int16, int16 ); +uint16 __ovld __cnfn max(uint16, uint16 ); +long __ovld __cnfn max(long, long ); +ulong __ovld __cnfn max(ulong, ulong ); +long2 __ovld __cnfn max(long2, long2 ); +ulong2 __ovld __cnfn max(ulong2, ulong2 ); +long3 __ovld __cnfn max(long3, long3 ); +ulong3 __ovld __cnfn max(ulong3, ulong3 ); +long4 __ovld __cnfn max(long4, long4 ); +ulong4 __ovld __cnfn max(ulong4, ulong4 ); +long8 __ovld __cnfn max(long8, long8 ); +ulong8 __ovld __cnfn max(ulong8, ulong8 ); +long16 __ovld __cnfn max(long16, long16 ); +ulong16 __ovld __cnfn max(ulong16, ulong16 ); +char2 __ovld __cnfn max(char2, char ); +uchar2 __ovld __cnfn max(uchar2, uchar ); +char3 __ovld __cnfn max(char3, char ); +uchar3 __ovld __cnfn max(uchar3, uchar ); +char4 __ovld __cnfn max(char4, char ); +uchar4 __ovld __cnfn max(uchar4, uchar ); +char8 __ovld __cnfn max(char8, char ); +uchar8 __ovld __cnfn max(uchar8, uchar ); +char16 __ovld __cnfn max(char16, char ); +uchar16 __ovld __cnfn max(uchar16, uchar ); +short2 __ovld __cnfn max(short2, short ); +ushort2 __ovld __cnfn max(ushort2, ushort ); +short3 __ovld __cnfn max(short3, short ); +ushort3 __ovld __cnfn max(ushort3, ushort ); +short4 __ovld __cnfn max(short4, short ); +ushort4 __ovld __cnfn max(ushort4, ushort ); +short8 __ovld __cnfn max(short8, short ); +ushort8 __ovld __cnfn max(ushort8, ushort ); +short16 __ovld __cnfn max(short16, short ); +ushort16 __ovld __cnfn max(ushort16, ushort ); +int2 __ovld __cnfn max(int2, int ); +uint2 __ovld __cnfn max(uint2, uint ); +int3 __ovld __cnfn max(int3, int ); +uint3 __ovld __cnfn max(uint3, uint ); +int4 __ovld __cnfn max(int4, int ); +uint4 __ovld __cnfn max(uint4, uint ); +int8 __ovld __cnfn max(int8, int ); +uint8 __ovld __cnfn max(uint8, uint ); +int16 __ovld __cnfn max(int16, int ); +uint16 __ovld __cnfn max(uint16, uint ); +long2 __ovld __cnfn max(long2, long ); +ulong2 __ovld __cnfn max(ulong2, ulong ); +long3 __ovld __cnfn max(long3, long ); +ulong3 __ovld __cnfn max(ulong3, ulong ); +long4 __ovld __cnfn max(long4, long ); +ulong4 __ovld __cnfn max(ulong4, ulong ); +long8 __ovld __cnfn max(long8, long ); +ulong8 __ovld __cnfn max(ulong8, ulong ); +long16 __ovld __cnfn max(long16, long ); +ulong16 __ovld __cnfn max(ulong16, ulong ); /** - * Returns y if y < x, otherwise it returns x. + * Returns y if y <, otherwise it returns x. */ -char __ovld __cnfn min(char, char); -uchar __ovld __cnfn min(uchar, uchar); -char2 __ovld __cnfn min(char2, char2); -uchar2 __ovld __cnfn min(uchar2, uchar2); -char3 __ovld __cnfn min(char3, char3); -uchar3 __ovld __cnfn min(uchar3, uchar3); -char4 __ovld __cnfn min(char4, char4); -uchar4 __ovld __cnfn min(uchar4, uchar4); -char8 __ovld __cnfn min(char8, char8); -uchar8 __ovld __cnfn min(uchar8, uchar8); -char16 __ovld __cnfn min(char16, char16); -uchar16 __ovld __cnfn min(uchar16, uchar16); -short __ovld __cnfn min(short, short); -ushort __ovld __cnfn min(ushort, ushort); -short2 __ovld __cnfn min(short2, short2); -ushort2 __ovld __cnfn min(ushort2, ushort2); -short3 __ovld __cnfn min(short3, short3); -ushort3 __ovld __cnfn min(ushort3, ushort3); -short4 __ovld __cnfn min(short4, short4); -ushort4 __ovld __cnfn min(ushort4, ushort4); -short8 __ovld __cnfn min(short8, short8); -ushort8 __ovld __cnfn min(ushort8, ushort8); -short16 __ovld __cnfn min(short16, short16); -ushort16 __ovld __cnfn min(ushort16, ushort16); -int __ovld __cnfn min(int, int); -uint __ovld __cnfn min(uint, uint); -int2 __ovld __cnfn min(int2, int2); -uint2 __ovld __cnfn min(uint2, uint2); -int3 __ovld __cnfn min(int3, int3); -uint3 __ovld __cnfn min(uint3, uint3); -int4 __ovld __cnfn min(int4, int4); -uint4 __ovld __cnfn min(uint4, uint4); -int8 __ovld __cnfn min(int8, int8); -uint8 __ovld __cnfn min(uint8, uint8); -int16 __ovld __cnfn min(int16, int16); -uint16 __ovld __cnfn min(uint16, uint16); -long __ovld __cnfn min(long, long); -ulong __ovld __cnfn min(ulong, ulong); -long2 __ovld __cnfn min(long2, long2); -ulong2 __ovld __cnfn min(ulong2, ulong2); -long3 __ovld __cnfn min(long3, long3); -ulong3 __ovld __cnfn min(ulong3, ulong3); -long4 __ovld __cnfn min(long4, long4); -ulong4 __ovld __cnfn min(ulong4, ulong4); -long8 __ovld __cnfn min(long8, long8); -ulong8 __ovld __cnfn min(ulong8, ulong8); -long16 __ovld __cnfn min(long16, long16); -ulong16 __ovld __cnfn min(ulong16, ulong16); -char2 __ovld __cnfn min(char2, char); -uchar2 __ovld __cnfn min(uchar2, uchar); -char3 __ovld __cnfn min(char3, char); -uchar3 __ovld __cnfn min(uchar3, uchar); -char4 __ovld __cnfn min(char4, char); -uchar4 __ovld __cnfn min(uchar4, uchar); -char8 __ovld __cnfn min(char8, char); -uchar8 __ovld __cnfn min(uchar8, uchar); -char16 __ovld __cnfn min(char16, char); -uchar16 __ovld __cnfn min(uchar16, uchar); -short2 __ovld __cnfn min(short2, short); -ushort2 __ovld __cnfn min(ushort2, ushort); -short3 __ovld __cnfn min(short3, short); -ushort3 __ovld __cnfn min(ushort3, ushort); -short4 __ovld __cnfn min(short4, short); -ushort4 __ovld __cnfn min(ushort4, ushort); -short8 __ovld __cnfn min(short8, short); -ushort8 __ovld __cnfn min(ushort8, ushort); -short16 __ovld __cnfn min(short16, short); -ushort16 __ovld __cnfn min(ushort16, ushort); -int2 __ovld __cnfn min(int2, int); -uint2 __ovld __cnfn min(uint2, uint); -int3 __ovld __cnfn min(int3, int); -uint3 __ovld __cnfn min(uint3, uint); -int4 __ovld __cnfn min(int4, int); -uint4 __ovld __cnfn min(uint4, uint); -int8 __ovld __cnfn min(int8, int); -uint8 __ovld __cnfn min(uint8, uint); -int16 __ovld __cnfn min(int16, int); -uint16 __ovld __cnfn min(uint16, uint); -long2 __ovld __cnfn min(long2, long); -ulong2 __ovld __cnfn min(ulong2, ulong); -long3 __ovld __cnfn min(long3, long); -ulong3 __ovld __cnfn min(ulong3, ulong); -long4 __ovld __cnfn min(long4, long); -ulong4 __ovld __cnfn min(ulong4, ulong); -long8 __ovld __cnfn min(long8, long); -ulong8 __ovld __cnfn min(ulong8, ulong); -long16 __ovld __cnfn min(long16, long); -ulong16 __ovld __cnfn min(ulong16, ulong); +char __ovld __cnfn min(char, char ); +uchar __ovld __cnfn min(uchar, uchar ); +char2 __ovld __cnfn min(char2, char2 ); +uchar2 __ovld __cnfn min(uchar2, uchar2 ); +char3 __ovld __cnfn min(char3, char3 ); +uchar3 __ovld __cnfn min(uchar3, uchar3 ); +char4 __ovld __cnfn min(char4, char4 ); +uchar4 __ovld __cnfn min(uchar4, uchar4 ); +char8 __ovld __cnfn min(char8, char8 ); +uchar8 __ovld __cnfn min(uchar8, uchar8 ); +char16 __ovld __cnfn min(char16, char16 ); +uchar16 __ovld __cnfn min(uchar16, uchar16 ); +short __ovld __cnfn min(short, short ); +ushort __ovld __cnfn min(ushort, ushort ); +short2 __ovld __cnfn min(short2, short2 ); +ushort2 __ovld __cnfn min(ushort2, ushort2 ); +short3 __ovld __cnfn min(short3, short3 ); +ushort3 __ovld __cnfn min(ushort3, ushort3 ); +short4 __ovld __cnfn min(short4, short4 ); +ushort4 __ovld __cnfn min(ushort4, ushort4 ); +short8 __ovld __cnfn min(short8, short8 ); +ushort8 __ovld __cnfn min(ushort8, ushort8 ); +short16 __ovld __cnfn min(short16, short16 ); +ushort16 __ovld __cnfn min(ushort16, ushort16 ); +int __ovld __cnfn min(int, int ); +uint __ovld __cnfn min(uint, uint ); +int2 __ovld __cnfn min(int2, int2 ); +uint2 __ovld __cnfn min(uint2, uint2 ); +int3 __ovld __cnfn min(int3, int3 ); +uint3 __ovld __cnfn min(uint3, uint3 ); +int4 __ovld __cnfn min(int4, int4 ); +uint4 __ovld __cnfn min(uint4, uint4 ); +int8 __ovld __cnfn min(int8, int8 ); +uint8 __ovld __cnfn min(uint8, uint8 ); +int16 __ovld __cnfn min(int16, int16 ); +uint16 __ovld __cnfn min(uint16, uint16 ); +long __ovld __cnfn min(long, long ); +ulong __ovld __cnfn min(ulong, ulong ); +long2 __ovld __cnfn min(long2, long2 ); +ulong2 __ovld __cnfn min(ulong2, ulong2 ); +long3 __ovld __cnfn min(long3, long3 ); +ulong3 __ovld __cnfn min(ulong3, ulong3 ); +long4 __ovld __cnfn min(long4, long4 ); +ulong4 __ovld __cnfn min(ulong4, ulong4 ); +long8 __ovld __cnfn min(long8, long8 ); +ulong8 __ovld __cnfn min(ulong8, ulong8 ); +long16 __ovld __cnfn min(long16, long16 ); +ulong16 __ovld __cnfn min(ulong16, ulong16 ); +char2 __ovld __cnfn min(char2, char ); +uchar2 __ovld __cnfn min(uchar2, uchar ); +char3 __ovld __cnfn min(char3, char ); +uchar3 __ovld __cnfn min(uchar3, uchar ); +char4 __ovld __cnfn min(char4, char ); +uchar4 __ovld __cnfn min(uchar4, uchar ); +char8 __ovld __cnfn min(char8, char ); +uchar8 __ovld __cnfn min(uchar8, uchar ); +char16 __ovld __cnfn min(char16, char ); +uchar16 __ovld __cnfn min(uchar16, uchar ); +short2 __ovld __cnfn min(short2, short ); +ushort2 __ovld __cnfn min(ushort2, ushort ); +short3 __ovld __cnfn min(short3, short ); +ushort3 __ovld __cnfn min(ushort3, ushort ); +short4 __ovld __cnfn min(short4, short ); +ushort4 __ovld __cnfn min(ushort4, ushort ); +short8 __ovld __cnfn min(short8, short ); +ushort8 __ovld __cnfn min(ushort8, ushort ); +short16 __ovld __cnfn min(short16, short ); +ushort16 __ovld __cnfn min(ushort16, ushort ); +int2 __ovld __cnfn min(int2, int ); +uint2 __ovld __cnfn min(uint2, uint ); +int3 __ovld __cnfn min(int3, int ); +uint3 __ovld __cnfn min(uint3, uint ); +int4 __ovld __cnfn min(int4, int ); +uint4 __ovld __cnfn min(uint4, uint ); +int8 __ovld __cnfn min(int8, int ); +uint8 __ovld __cnfn min(uint8, uint ); +int16 __ovld __cnfn min(int16, int ); +uint16 __ovld __cnfn min(uint16, uint ); +long2 __ovld __cnfn min(long2, long ); +ulong2 __ovld __cnfn min(ulong2, ulong ); +long3 __ovld __cnfn min(long3, long ); +ulong3 __ovld __cnfn min(ulong3, ulong ); +long4 __ovld __cnfn min(long4, long ); +ulong4 __ovld __cnfn min(ulong4, ulong ); +long8 __ovld __cnfn min(long8, long ); +ulong8 __ovld __cnfn min(ulong8, ulong ); +long16 __ovld __cnfn min(long16, long ); +ulong16 __ovld __cnfn min(ulong16, ulong ); /** * Computes x * y and returns the high half of the * product of x and y. */ -char __ovld __cnfn mul_hi(char, char); -uchar __ovld __cnfn mul_hi(uchar, uchar); -char2 __ovld __cnfn mul_hi(char2, char2); -uchar2 __ovld __cnfn mul_hi(uchar2, uchar2); -char3 __ovld __cnfn mul_hi(char3, char3); -uchar3 __ovld __cnfn mul_hi(uchar3, uchar3); -char4 __ovld __cnfn mul_hi(char4, char4); -uchar4 __ovld __cnfn mul_hi(uchar4, uchar4); -char8 __ovld __cnfn mul_hi(char8, char8); -uchar8 __ovld __cnfn mul_hi(uchar8, uchar8); -char16 __ovld __cnfn mul_hi(char16, char16); -uchar16 __ovld __cnfn mul_hi(uchar16, uchar16); -short __ovld __cnfn mul_hi(short, short); -ushort __ovld __cnfn mul_hi(ushort, ushort); -short2 __ovld __cnfn mul_hi(short2, short2); -ushort2 __ovld __cnfn mul_hi(ushort2, ushort2); -short3 __ovld __cnfn mul_hi(short3, short3); -ushort3 __ovld __cnfn mul_hi(ushort3, ushort3); -short4 __ovld __cnfn mul_hi(short4, short4); -ushort4 __ovld __cnfn mul_hi(ushort4, ushort4); -short8 __ovld __cnfn mul_hi(short8, short8); -ushort8 __ovld __cnfn mul_hi(ushort8, ushort8); -short16 __ovld __cnfn mul_hi(short16, short16); -ushort16 __ovld __cnfn mul_hi(ushort16, ushort16); -int __ovld __cnfn mul_hi(int, int); -uint __ovld __cnfn mul_hi(uint, uint); -int2 __ovld __cnfn mul_hi(int2, int2); -uint2 __ovld __cnfn mul_hi(uint2, uint2); -int3 __ovld __cnfn mul_hi(int3, int3); -uint3 __ovld __cnfn mul_hi(uint3, uint3); -int4 __ovld __cnfn mul_hi(int4, int4); -uint4 __ovld __cnfn mul_hi(uint4, uint4); -int8 __ovld __cnfn mul_hi(int8, int8); -uint8 __ovld __cnfn mul_hi(uint8, uint8); -int16 __ovld __cnfn mul_hi(int16, int16); -uint16 __ovld __cnfn mul_hi(uint16, uint16); -long __ovld __cnfn mul_hi(long, long); -ulong __ovld __cnfn mul_hi(ulong, ulong); -long2 __ovld __cnfn mul_hi(long2, long2); -ulong2 __ovld __cnfn mul_hi(ulong2, ulong2); -long3 __ovld __cnfn mul_hi(long3, long3); -ulong3 __ovld __cnfn mul_hi(ulong3, ulong3); -long4 __ovld __cnfn mul_hi(long4, long4); -ulong4 __ovld __cnfn mul_hi(ulong4, ulong4); -long8 __ovld __cnfn mul_hi(long8, long8); -ulong8 __ovld __cnfn mul_hi(ulong8, ulong8); -long16 __ovld __cnfn mul_hi(long16, long16); -ulong16 __ovld __cnfn mul_hi(ulong16, ulong16); +char __ovld __cnfn mul_hi(char, char ); +uchar __ovld __cnfn mul_hi(uchar, uchar ); +char2 __ovld __cnfn mul_hi(char2, char2 ); +uchar2 __ovld __cnfn mul_hi(uchar2, uchar2 ); +char3 __ovld __cnfn mul_hi(char3, char3 ); +uchar3 __ovld __cnfn mul_hi(uchar3, uchar3 ); +char4 __ovld __cnfn mul_hi(char4, char4 ); +uchar4 __ovld __cnfn mul_hi(uchar4, uchar4 ); +char8 __ovld __cnfn mul_hi(char8, char8 ); +uchar8 __ovld __cnfn mul_hi(uchar8, uchar8 ); +char16 __ovld __cnfn mul_hi(char16, char16 ); +uchar16 __ovld __cnfn mul_hi(uchar16, uchar16 ); +short __ovld __cnfn mul_hi(short, short ); +ushort __ovld __cnfn mul_hi(ushort, ushort ); +short2 __ovld __cnfn mul_hi(short2, short2 ); +ushort2 __ovld __cnfn mul_hi(ushort2, ushort2 ); +short3 __ovld __cnfn mul_hi(short3, short3 ); +ushort3 __ovld __cnfn mul_hi(ushort3, ushort3 ); +short4 __ovld __cnfn mul_hi(short4, short4 ); +ushort4 __ovld __cnfn mul_hi(ushort4, ushort4 ); +short8 __ovld __cnfn mul_hi(short8, short8 ); +ushort8 __ovld __cnfn mul_hi(ushort8, ushort8 ); +short16 __ovld __cnfn mul_hi(short16, short16 ); +ushort16 __ovld __cnfn mul_hi(ushort16, ushort16 ); +int __ovld __cnfn mul_hi(int, int ); +uint __ovld __cnfn mul_hi(uint, uint ); +int2 __ovld __cnfn mul_hi(int2, int2 ); +uint2 __ovld __cnfn mul_hi(uint2, uint2 ); +int3 __ovld __cnfn mul_hi(int3, int3 ); +uint3 __ovld __cnfn mul_hi(uint3, uint3 ); +int4 __ovld __cnfn mul_hi(int4, int4 ); +uint4 __ovld __cnfn mul_hi(uint4, uint4 ); +int8 __ovld __cnfn mul_hi(int8, int8 ); +uint8 __ovld __cnfn mul_hi(uint8, uint8 ); +int16 __ovld __cnfn mul_hi(int16, int16 ); +uint16 __ovld __cnfn mul_hi(uint16, uint16 ); +long __ovld __cnfn mul_hi(long, long ); +ulong __ovld __cnfn mul_hi(ulong, ulong ); +long2 __ovld __cnfn mul_hi(long2, long2 ); +ulong2 __ovld __cnfn mul_hi(ulong2, ulong2 ); +long3 __ovld __cnfn mul_hi(long3, long3 ); +ulong3 __ovld __cnfn mul_hi(ulong3, ulong3 ); +long4 __ovld __cnfn mul_hi(long4, long4 ); +ulong4 __ovld __cnfn mul_hi(ulong4, ulong4 ); +long8 __ovld __cnfn mul_hi(long8, long8 ); +ulong8 __ovld __cnfn mul_hi(ulong8, ulong8 ); +long16 __ovld __cnfn mul_hi(long16, long16 ); +ulong16 __ovld __cnfn mul_hi(ulong16, ulong16 ); /** * For each element in v, the bits are shifted left by @@ -9819,54 +10542,54 @@ ulong16 __ovld __cnfn rotate(ulong16, ulong16); /** * Returns x - y and saturates the result. */ -char __ovld __cnfn sub_sat(char, char); -uchar __ovld __cnfn sub_sat(uchar, uchar); -char2 __ovld __cnfn sub_sat(char2, char2); -uchar2 __ovld __cnfn sub_sat(uchar2, uchar2); -char3 __ovld __cnfn sub_sat(char3, char3); -uchar3 __ovld __cnfn sub_sat(uchar3, uchar3); -char4 __ovld __cnfn sub_sat(char4, char4); -uchar4 __ovld __cnfn sub_sat(uchar4, uchar4); -char8 __ovld __cnfn sub_sat(char8, char8); -uchar8 __ovld __cnfn sub_sat(uchar8, uchar8); -char16 __ovld __cnfn sub_sat(char16, char16); -uchar16 __ovld __cnfn sub_sat(uchar16, uchar16); -short __ovld __cnfn sub_sat(short, short); -ushort __ovld __cnfn sub_sat(ushort, ushort); -short2 __ovld __cnfn sub_sat(short2, short2); -ushort2 __ovld __cnfn sub_sat(ushort2, ushort2); -short3 __ovld __cnfn sub_sat(short3, short3); -ushort3 __ovld __cnfn sub_sat(ushort3, ushort3); -short4 __ovld __cnfn sub_sat(short4, short4); -ushort4 __ovld __cnfn sub_sat(ushort4, ushort4); -short8 __ovld __cnfn sub_sat(short8, short8); -ushort8 __ovld __cnfn sub_sat(ushort8, ushort8); -short16 __ovld __cnfn sub_sat(short16, short16); -ushort16 __ovld __cnfn sub_sat(ushort16, ushort16); -int __ovld __cnfn sub_sat(int, int); -uint __ovld __cnfn sub_sat(uint, uint); -int2 __ovld __cnfn sub_sat(int2, int2); -uint2 __ovld __cnfn sub_sat(uint2, uint2); -int3 __ovld __cnfn sub_sat(int3, int3); -uint3 __ovld __cnfn sub_sat(uint3, uint3); -int4 __ovld __cnfn sub_sat(int4, int4); -uint4 __ovld __cnfn sub_sat(uint4, uint4); -int8 __ovld __cnfn sub_sat(int8, int8); -uint8 __ovld __cnfn sub_sat(uint8, uint8); -int16 __ovld __cnfn sub_sat(int16, int16); -uint16 __ovld __cnfn sub_sat(uint16, uint16); -long __ovld __cnfn sub_sat(long, long); -ulong __ovld __cnfn sub_sat(ulong, ulong); -long2 __ovld __cnfn sub_sat(long2, long2); -ulong2 __ovld __cnfn sub_sat(ulong2, ulong2); -long3 __ovld __cnfn sub_sat(long3, long3); -ulong3 __ovld __cnfn sub_sat(ulong3, ulong3); -long4 __ovld __cnfn sub_sat(long4, long4); -ulong4 __ovld __cnfn sub_sat(ulong4, ulong4); -long8 __ovld __cnfn sub_sat(long8, long8); -ulong8 __ovld __cnfn sub_sat(ulong8, ulong8); -long16 __ovld __cnfn sub_sat(long16, long16); -ulong16 __ovld __cnfn sub_sat(ulong16, ulong16); +char __ovld __cnfn sub_sat(char, char ); +uchar __ovld __cnfn sub_sat(uchar, uchar ); +char2 __ovld __cnfn sub_sat(char2, char2 ); +uchar2 __ovld __cnfn sub_sat(uchar2, uchar2 ); +char3 __ovld __cnfn sub_sat(char3, char3 ); +uchar3 __ovld __cnfn sub_sat(uchar3, uchar3 ); +char4 __ovld __cnfn sub_sat(char4, char4 ); +uchar4 __ovld __cnfn sub_sat(uchar4, uchar4 ); +char8 __ovld __cnfn sub_sat(char8, char8 ); +uchar8 __ovld __cnfn sub_sat(uchar8, uchar8 ); +char16 __ovld __cnfn sub_sat(char16, char16 ); +uchar16 __ovld __cnfn sub_sat(uchar16, uchar16 ); +short __ovld __cnfn sub_sat(short, short ); +ushort __ovld __cnfn sub_sat(ushort, ushort ); +short2 __ovld __cnfn sub_sat(short2, short2 ); +ushort2 __ovld __cnfn sub_sat(ushort2, ushort2 ); +short3 __ovld __cnfn sub_sat(short3, short3 ); +ushort3 __ovld __cnfn sub_sat(ushort3, ushort3 ); +short4 __ovld __cnfn sub_sat(short4, short4 ); +ushort4 __ovld __cnfn sub_sat(ushort4, ushort4 ); +short8 __ovld __cnfn sub_sat(short8, short8 ); +ushort8 __ovld __cnfn sub_sat(ushort8, ushort8 ); +short16 __ovld __cnfn sub_sat(short16, short16 ); +ushort16 __ovld __cnfn sub_sat(ushort16, ushort16 ); +int __ovld __cnfn sub_sat(int, int ); +uint __ovld __cnfn sub_sat(uint, uint ); +int2 __ovld __cnfn sub_sat(int2, int2 ); +uint2 __ovld __cnfn sub_sat(uint2, uint2 ); +int3 __ovld __cnfn sub_sat(int3, int3 ); +uint3 __ovld __cnfn sub_sat(uint3, uint3 ); +int4 __ovld __cnfn sub_sat(int4, int4 ); +uint4 __ovld __cnfn sub_sat(uint4, uint4 ); +int8 __ovld __cnfn sub_sat(int8, int8 ); +uint8 __ovld __cnfn sub_sat(uint8, uint8 ); +int16 __ovld __cnfn sub_sat(int16, int16 ); +uint16 __ovld __cnfn sub_sat(uint16, uint16 ); +long __ovld __cnfn sub_sat(long, long ); +ulong __ovld __cnfn sub_sat(ulong, ulong ); +long2 __ovld __cnfn sub_sat(long2, long2 ); +ulong2 __ovld __cnfn sub_sat(ulong2, ulong2 ); +long3 __ovld __cnfn sub_sat(long3, long3 ); +ulong3 __ovld __cnfn sub_sat(ulong3, ulong3 ); +long4 __ovld __cnfn sub_sat(long4, long4 ); +ulong4 __ovld __cnfn sub_sat(ulong4, ulong4 ); +long8 __ovld __cnfn sub_sat(long8, long8 ); +ulong8 __ovld __cnfn sub_sat(ulong8, ulong8 ); +long16 __ovld __cnfn sub_sat(long16, long16 ); +ulong16 __ovld __cnfn sub_sat(ulong16, ulong16 ); /** * result[i] = ((short)hi[i] << 8) | lo[i] @@ -9922,54 +10645,54 @@ ulong16 __ovld __cnfn upsample(uint16, uint16); * popcount(x): returns the number of set bit in x */ #if defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ >= CL_VERSION_1_2) -char __ovld __cnfn popcount(char); -uchar __ovld __cnfn popcount(uchar); -char2 __ovld __cnfn popcount(char2); -uchar2 __ovld __cnfn popcount(uchar2); -char3 __ovld __cnfn popcount(char3); -uchar3 __ovld __cnfn popcount(uchar3); -char4 __ovld __cnfn popcount(char4); -uchar4 __ovld __cnfn popcount(uchar4); -char8 __ovld __cnfn popcount(char8); -uchar8 __ovld __cnfn popcount(uchar8); -char16 __ovld __cnfn popcount(char16); -uchar16 __ovld __cnfn popcount(uchar16); -short __ovld __cnfn popcount(short); -ushort __ovld __cnfn popcount(ushort); -short2 __ovld __cnfn popcount(short2); -ushort2 __ovld __cnfn popcount(ushort2); -short3 __ovld __cnfn popcount(short3); -ushort3 __ovld __cnfn popcount(ushort3); -short4 __ovld __cnfn popcount(short4); -ushort4 __ovld __cnfn popcount(ushort4); -short8 __ovld __cnfn popcount(short8); -ushort8 __ovld __cnfn popcount(ushort8); -short16 __ovld __cnfn popcount(short16); -ushort16 __ovld __cnfn popcount(ushort16); -int __ovld __cnfn popcount(int); -uint __ovld __cnfn popcount(uint); -int2 __ovld __cnfn popcount(int2); -uint2 __ovld __cnfn popcount(uint2); -int3 __ovld __cnfn popcount(int3); -uint3 __ovld __cnfn popcount(uint3); -int4 __ovld __cnfn popcount(int4); -uint4 __ovld __cnfn popcount(uint4); -int8 __ovld __cnfn popcount(int8); -uint8 __ovld __cnfn popcount(uint8); -int16 __ovld __cnfn popcount(int16); -uint16 __ovld __cnfn popcount(uint16); -long __ovld __cnfn popcount(long); -ulong __ovld __cnfn popcount(ulong); -long2 __ovld __cnfn popcount(long2); -ulong2 __ovld __cnfn popcount(ulong2); -long3 __ovld __cnfn popcount(long3); -ulong3 __ovld __cnfn popcount(ulong3); -long4 __ovld __cnfn popcount(long4); -ulong4 __ovld __cnfn popcount(ulong4); -long8 __ovld __cnfn popcount(long8); -ulong8 __ovld __cnfn popcount(ulong8); -long16 __ovld __cnfn popcount(long16); -ulong16 __ovld __cnfn popcount(ulong16); +char __ovld __cnfn popcount(char x); +uchar __ovld __cnfn popcount(uchar x); +char2 __ovld __cnfn popcount(char2 x); +uchar2 __ovld __cnfn popcount(uchar2 x); +char3 __ovld __cnfn popcount(char3 x); +uchar3 __ovld __cnfn popcount(uchar3 x); +char4 __ovld __cnfn popcount(char4 x); +uchar4 __ovld __cnfn popcount(uchar4 x); +char8 __ovld __cnfn popcount(char8 x); +uchar8 __ovld __cnfn popcount(uchar8 x); +char16 __ovld __cnfn popcount(char16 x); +uchar16 __ovld __cnfn popcount(uchar16 x); +short __ovld __cnfn popcount(short x); +ushort __ovld __cnfn popcount(ushort x); +short2 __ovld __cnfn popcount(short2 x); +ushort2 __ovld __cnfn popcount(ushort2 x); +short3 __ovld __cnfn popcount(short3 x); +ushort3 __ovld __cnfn popcount(ushort3 x); +short4 __ovld __cnfn popcount(short4 x); +ushort4 __ovld __cnfn popcount(ushort4 x); +short8 __ovld __cnfn popcount(short8 x); +ushort8 __ovld __cnfn popcount(ushort8 x); +short16 __ovld __cnfn popcount(short16 x); +ushort16 __ovld __cnfn popcount(ushort16 x); +int __ovld __cnfn popcount(int x); +uint __ovld __cnfn popcount(uint x); +int2 __ovld __cnfn popcount(int2 x); +uint2 __ovld __cnfn popcount(uint2 x); +int3 __ovld __cnfn popcount(int3 x); +uint3 __ovld __cnfn popcount(uint3 x); +int4 __ovld __cnfn popcount(int4 x); +uint4 __ovld __cnfn popcount(uint4 x); +int8 __ovld __cnfn popcount(int8 x); +uint8 __ovld __cnfn popcount(uint8 x); +int16 __ovld __cnfn popcount(int16 x); +uint16 __ovld __cnfn popcount(uint16 x); +long __ovld __cnfn popcount(long x); +ulong __ovld __cnfn popcount(ulong x); +long2 __ovld __cnfn popcount(long2 x); +ulong2 __ovld __cnfn popcount(ulong2 x); +long3 __ovld __cnfn popcount(long3 x); +ulong3 __ovld __cnfn popcount(ulong3 x); +long4 __ovld __cnfn popcount(long4 x); +ulong4 __ovld __cnfn popcount(ulong4 x); +long8 __ovld __cnfn popcount(long8 x); +ulong8 __ovld __cnfn popcount(ulong8 x); +long16 __ovld __cnfn popcount(long16 x); +ulong16 __ovld __cnfn popcount(ulong16 x); #endif // defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ >= CL_VERSION_1_2) /** @@ -9978,18 +10701,18 @@ ulong16 __ovld __cnfn popcount(ulong16); * Refer to definition of mul24 to see how the 24-bit * integer multiplication is performed. */ -int __ovld __cnfn mad24(int, int, int); -uint __ovld __cnfn mad24(uint, uint, uint); -int2 __ovld __cnfn mad24(int2, int2, int2); -uint2 __ovld __cnfn mad24(uint2, uint2, uint2); -int3 __ovld __cnfn mad24(int3, int3, int3); -uint3 __ovld __cnfn mad24(uint3, uint3, uint3); -int4 __ovld __cnfn mad24(int4, int4, int4); -uint4 __ovld __cnfn mad24(uint4, uint4, uint4); -int8 __ovld __cnfn mad24(int8, int8, int8); -uint8 __ovld __cnfn mad24(uint8, uint8, uint8); -int16 __ovld __cnfn mad24(int16, int16, int16); -uint16 __ovld __cnfn mad24(uint16, uint16, uint16); +int __ovld __cnfn mad24(int, int, int ); +uint __ovld __cnfn mad24(uint, uint, uint ); +int2 __ovld __cnfn mad24(int2, int2, int2 ); +uint2 __ovld __cnfn mad24(uint2, uint2, uint2 ); +int3 __ovld __cnfn mad24(int3, int3, int3 ); +uint3 __ovld __cnfn mad24(uint3, uint3, uint3 ); +int4 __ovld __cnfn mad24(int4, int4, int4 ); +uint4 __ovld __cnfn mad24(uint4, uint4, uint4 ); +int8 __ovld __cnfn mad24(int8, int8, int8 ); +uint8 __ovld __cnfn mad24(uint8, uint8, uint8 ); +int16 __ovld __cnfn mad24(int16, int16, int16 ); +uint16 __ovld __cnfn mad24(uint16, uint16, uint16 ); /** * Multiply two 24-bit integer values x and y. x and y @@ -10001,18 +10724,18 @@ uint16 __ovld __cnfn mad24(uint16, uint16, uint16); * x and y are not in this range, the multiplication * result is implementation-defined. */ -int __ovld __cnfn mul24(int, int); -uint __ovld __cnfn mul24(uint, uint); -int2 __ovld __cnfn mul24(int2, int2); -uint2 __ovld __cnfn mul24(uint2, uint2); -int3 __ovld __cnfn mul24(int3, int3); -uint3 __ovld __cnfn mul24(uint3, uint3); -int4 __ovld __cnfn mul24(int4, int4); -uint4 __ovld __cnfn mul24(uint4, uint4); -int8 __ovld __cnfn mul24(int8, int8); -uint8 __ovld __cnfn mul24(uint8, uint8); -int16 __ovld __cnfn mul24(int16, int16); -uint16 __ovld __cnfn mul24(uint16, uint16); +int __ovld __cnfn mul24(int, int ); +uint __ovld __cnfn mul24(uint, uint ); +int2 __ovld __cnfn mul24(int2, int2 ); +uint2 __ovld __cnfn mul24(uint2, uint2 ); +int3 __ovld __cnfn mul24(int3, int3 ); +uint3 __ovld __cnfn mul24(uint3, uint3 ); +int4 __ovld __cnfn mul24(int4, int4 ); +uint4 __ovld __cnfn mul24(uint4, uint4 ); +int8 __ovld __cnfn mul24(int8, int8 ); +uint8 __ovld __cnfn mul24(uint8, uint8 ); +int16 __ovld __cnfn mul24(int16, int16 ); +uint16 __ovld __cnfn mul24(uint16, uint16 ); // OpenCL v1.1 s6.11.4, v1.2 s6.12.4, v2.0 s6.13.4 - Common Functions @@ -10086,87 +10809,87 @@ half16 __ovld __cnfn degrees(half16); #endif //cl_khr_fp16 /** - * Returns y if x < y, otherwise it returns x. If x and y + * Returns y if x <, otherwise it returns x. If x and y * are infinite or NaN, the return values are undefined. */ -float __ovld __cnfn max(float, float); -float2 __ovld __cnfn max(float2, float2); -float3 __ovld __cnfn max(float3, float3); -float4 __ovld __cnfn max(float4, float4); -float8 __ovld __cnfn max(float8, float8); -float16 __ovld __cnfn max(float16, float16); -float2 __ovld __cnfn max(float2, float); -float3 __ovld __cnfn max(float3, float); -float4 __ovld __cnfn max(float4, float); -float8 __ovld __cnfn max(float8, float); -float16 __ovld __cnfn max(float16, float); +float __ovld __cnfn max(float, float ); +float2 __ovld __cnfn max(float2, float2 ); +float3 __ovld __cnfn max(float3, float3 ); +float4 __ovld __cnfn max(float4, float4 ); +float8 __ovld __cnfn max(float8, float8 ); +float16 __ovld __cnfn max(float16, float16 ); +float2 __ovld __cnfn max(float2, float ); +float3 __ovld __cnfn max(float3, float ); +float4 __ovld __cnfn max(float4, float ); +float8 __ovld __cnfn max(float8, float ); +float16 __ovld __cnfn max(float16, float ); #ifdef cl_khr_fp64 -double __ovld __cnfn max(double, double); -double2 __ovld __cnfn max(double2, double2); -double3 __ovld __cnfn max(double3, double3); -double4 __ovld __cnfn max(double4, double4); -double8 __ovld __cnfn max(double8, double8); -double16 __ovld __cnfn max(double16, double16); -double2 __ovld __cnfn max(double2, double); -double3 __ovld __cnfn max(double3, double); -double4 __ovld __cnfn max(double4, double); -double8 __ovld __cnfn max(double8, double); -double16 __ovld __cnfn max(double16, double); +double __ovld __cnfn max(double, double ); +double2 __ovld __cnfn max(double2, double2 ); +double3 __ovld __cnfn max(double3, double3 ); +double4 __ovld __cnfn max(double4, double4 ); +double8 __ovld __cnfn max(double8, double8 ); +double16 __ovld __cnfn max(double16, double16 ); +double2 __ovld __cnfn max(double2, double ); +double3 __ovld __cnfn max(double3, double ); +double4 __ovld __cnfn max(double4, double ); +double8 __ovld __cnfn max(double8, double ); +double16 __ovld __cnfn max(double16, double ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn max(half, half); -half2 __ovld __cnfn max(half2, half2); -half3 __ovld __cnfn max(half3, half3); -half4 __ovld __cnfn max(half4, half4); -half8 __ovld __cnfn max(half8, half8); -half16 __ovld __cnfn max(half16, half16); -half2 __ovld __cnfn max(half2, half); -half3 __ovld __cnfn max(half3, half); -half4 __ovld __cnfn max(half4, half); -half8 __ovld __cnfn max(half8, half); -half16 __ovld __cnfn max(half16, half); +half __ovld __cnfn max(half, half ); +half2 __ovld __cnfn max(half2, half2 ); +half3 __ovld __cnfn max(half3, half3 ); +half4 __ovld __cnfn max(half4, half4 ); +half8 __ovld __cnfn max(half8, half8 ); +half16 __ovld __cnfn max(half16, half16 ); +half2 __ovld __cnfn max(half2, half ); +half3 __ovld __cnfn max(half3, half ); +half4 __ovld __cnfn max(half4, half ); +half8 __ovld __cnfn max(half8, half ); +half16 __ovld __cnfn max(half16, half ); #endif //cl_khr_fp16 /** - * Returns y if y < x, otherwise it returns x. If x and y + * Returns y if y <, otherwise it returns x. If x and y * are infinite or NaN, the return values are undefined. */ -float __ovld __cnfn min(float, float); -float2 __ovld __cnfn min(float2, float2); -float3 __ovld __cnfn min(float3, float3); -float4 __ovld __cnfn min(float4, float4); -float8 __ovld __cnfn min(float8, float8); -float16 __ovld __cnfn min(float16, float16); -float2 __ovld __cnfn min(float2, float); -float3 __ovld __cnfn min(float3, float); -float4 __ovld __cnfn min(float4, float); -float8 __ovld __cnfn min(float8, float); -float16 __ovld __cnfn min(float16, float); +float __ovld __cnfn min(float, float ); +float2 __ovld __cnfn min(float2, float2 ); +float3 __ovld __cnfn min(float3, float3 ); +float4 __ovld __cnfn min(float4, float4 ); +float8 __ovld __cnfn min(float8, float8 ); +float16 __ovld __cnfn min(float16, float16 ); +float2 __ovld __cnfn min(float2, float ); +float3 __ovld __cnfn min(float3, float ); +float4 __ovld __cnfn min(float4, float ); +float8 __ovld __cnfn min(float8, float ); +float16 __ovld __cnfn min(float16, float ); #ifdef cl_khr_fp64 -double __ovld __cnfn min(double, double); -double2 __ovld __cnfn min(double2, double2); -double3 __ovld __cnfn min(double3, double3); -double4 __ovld __cnfn min(double4, double4); -double8 __ovld __cnfn min(double8, double8); -double16 __ovld __cnfn min(double16, double16); -double2 __ovld __cnfn min(double2, double); -double3 __ovld __cnfn min(double3, double); -double4 __ovld __cnfn min(double4, double); -double8 __ovld __cnfn min(double8, double); -double16 __ovld __cnfn min(double16, double); +double __ovld __cnfn min(double, double ); +double2 __ovld __cnfn min(double2, double2 ); +double3 __ovld __cnfn min(double3, double3 ); +double4 __ovld __cnfn min(double4, double4 ); +double8 __ovld __cnfn min(double8, double8 ); +double16 __ovld __cnfn min(double16, double16 ); +double2 __ovld __cnfn min(double2, double ); +double3 __ovld __cnfn min(double3, double ); +double4 __ovld __cnfn min(double4, double ); +double8 __ovld __cnfn min(double8, double ); +double16 __ovld __cnfn min(double16, double ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn min(half, half); -half2 __ovld __cnfn min(half2, half2); -half3 __ovld __cnfn min(half3, half3); -half4 __ovld __cnfn min(half4, half4); -half8 __ovld __cnfn min(half8, half8); -half16 __ovld __cnfn min(half16, half16); -half2 __ovld __cnfn min(half2, half); -half3 __ovld __cnfn min(half3, half); -half4 __ovld __cnfn min(half4, half); -half8 __ovld __cnfn min(half8, half); -half16 __ovld __cnfn min(half16, half); +half __ovld __cnfn min(half, half ); +half2 __ovld __cnfn min(half2, half2 ); +half3 __ovld __cnfn min(half3, half3 ); +half4 __ovld __cnfn min(half4, half4 ); +half8 __ovld __cnfn min(half8, half8 ); +half16 __ovld __cnfn min(half16, half16 ); +half2 __ovld __cnfn min(half2, half ); +half3 __ovld __cnfn min(half3, half ); +half4 __ovld __cnfn min(half4, half ); +half8 __ovld __cnfn min(half8, half ); +half16 __ovld __cnfn min(half16, half ); #endif //cl_khr_fp16 /** @@ -10244,42 +10967,42 @@ half16 __ovld __cnfn radians(half16); /** * Returns 0.0 if x < edge, otherwise it returns 1.0. */ -float __ovld __cnfn step(float, float); -float2 __ovld __cnfn step(float2, float2); -float3 __ovld __cnfn step(float3, float3); -float4 __ovld __cnfn step(float4, float4); -float8 __ovld __cnfn step(float8, float8); -float16 __ovld __cnfn step(float16, float16); -float2 __ovld __cnfn step(float, float2); -float3 __ovld __cnfn step(float, float3); -float4 __ovld __cnfn step(float, float4); -float8 __ovld __cnfn step(float, float8); -float16 __ovld __cnfn step(float, float16); +float __ovld __cnfn step(float edge, float); +float2 __ovld __cnfn step(float2 edge, float2); +float3 __ovld __cnfn step(float3 edge, float3); +float4 __ovld __cnfn step(float4 edge, float4); +float8 __ovld __cnfn step(float8 edge, float8); +float16 __ovld __cnfn step(float16 edge, float16); +float2 __ovld __cnfn step(float edge, float2); +float3 __ovld __cnfn step(float edge, float3); +float4 __ovld __cnfn step(float edge, float4); +float8 __ovld __cnfn step(float edge, float8); +float16 __ovld __cnfn step(float edge, float16); #ifdef cl_khr_fp64 -double __ovld __cnfn step(double, double); -double2 __ovld __cnfn step(double2, double2); -double3 __ovld __cnfn step(double3, double3); -double4 __ovld __cnfn step(double4, double4); -double8 __ovld __cnfn step(double8, double8); -double16 __ovld __cnfn step(double16, double16); -double2 __ovld __cnfn step(double, double2); -double3 __ovld __cnfn step(double, double3); -double4 __ovld __cnfn step(double, double4); -double8 __ovld __cnfn step(double, double8); -double16 __ovld __cnfn step(double, double16); +double __ovld __cnfn step(double edge, double); +double2 __ovld __cnfn step(double2 edge, double2); +double3 __ovld __cnfn step(double3 edge, double3); +double4 __ovld __cnfn step(double4 edge, double4); +double8 __ovld __cnfn step(double8 edge, double8); +double16 __ovld __cnfn step(double16 edge, double16); +double2 __ovld __cnfn step(double edge, double2); +double3 __ovld __cnfn step(double edge, double3); +double4 __ovld __cnfn step(double edge, double4); +double8 __ovld __cnfn step(double edge, double8); +double16 __ovld __cnfn step(double edge, double16); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn step(half, half); -half2 __ovld __cnfn step(half2, half2); -half3 __ovld __cnfn step(half3, half3); -half4 __ovld __cnfn step(half4, half4); -half8 __ovld __cnfn step(half8, half8); -half16 __ovld __cnfn step(half16, half16); -half2 __ovld __cnfn step(half, half2); -half3 __ovld __cnfn step(half, half3); -half4 __ovld __cnfn step(half, half4); -half8 __ovld __cnfn step(half, half8); -half16 __ovld __cnfn step(half, half16); +half __ovld __cnfn step(half edge, half); +half2 __ovld __cnfn step(half2 edge, half2); +half3 __ovld __cnfn step(half3 edge, half3); +half4 __ovld __cnfn step(half4 edge, half4); +half8 __ovld __cnfn step(half8 edge, half8); +half16 __ovld __cnfn step(half16 edge, half16); +half2 __ovld __cnfn step(half edge, half2); +half3 __ovld __cnfn step(half edge, half3); +half4 __ovld __cnfn step(half edge, half4); +half8 __ovld __cnfn step(half edge, half8); +half16 __ovld __cnfn step(half edge, half16); #endif //cl_khr_fp16 /** @@ -10292,72 +11015,72 @@ half16 __ovld __cnfn step(half, half16); * gentype t; * t = clamp ((x - edge0) / (edge1 - edge0), 0, 1); * return t * t * (3 - 2 * t); - * Results are undefined if edge0 >= edge1 or if x, + * Results are undefined if edge0 >= edge1 or if, * edge0 or edge1 is a NaN. */ -float __ovld __cnfn smoothstep(float, float, float); -float2 __ovld __cnfn smoothstep(float2, float2, float2); -float3 __ovld __cnfn smoothstep(float3, float3, float3); -float4 __ovld __cnfn smoothstep(float4, float4, float4); -float8 __ovld __cnfn smoothstep(float8, float8, float8); -float16 __ovld __cnfn smoothstep(float16, float16, float16); -float2 __ovld __cnfn smoothstep(float, float, float2); -float3 __ovld __cnfn smoothstep(float, float, float3); -float4 __ovld __cnfn smoothstep(float, float, float4); -float8 __ovld __cnfn smoothstep(float, float, float8); -float16 __ovld __cnfn smoothstep(float, float, float16); +float __ovld __cnfn smoothstep(float edge0, float edge1, float x); +float2 __ovld __cnfn smoothstep(float2 edge0, float2 edge1, float2 x); +float3 __ovld __cnfn smoothstep(float3 edge0, float3 edge1, float3 x); +float4 __ovld __cnfn smoothstep(float4 edge0, float4 edge1, float4 x); +float8 __ovld __cnfn smoothstep(float8 edge0, float8 edge1, float8 x); +float16 __ovld __cnfn smoothstep(float16 edge0, float16 edge1, float16 x); +float2 __ovld __cnfn smoothstep(float edge0, float edge1, float2 x); +float3 __ovld __cnfn smoothstep(float edge0, float edge1, float3 x); +float4 __ovld __cnfn smoothstep(float edge0, float edge1, float4 x); +float8 __ovld __cnfn smoothstep(float edge0, float edge1, float8 x); +float16 __ovld __cnfn smoothstep(float edge0, float edge1, float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn smoothstep(double, double, double); -double2 __ovld __cnfn smoothstep(double2, double2, double2); -double3 __ovld __cnfn smoothstep(double3, double3, double3); -double4 __ovld __cnfn smoothstep(double4, double4, double4); -double8 __ovld __cnfn smoothstep(double8, double8, double8); -double16 __ovld __cnfn smoothstep(double16, double16, double16); -double2 __ovld __cnfn smoothstep(double, double, double2); -double3 __ovld __cnfn smoothstep(double, double, double3); -double4 __ovld __cnfn smoothstep(double, double, double4); -double8 __ovld __cnfn smoothstep(double, double, double8); -double16 __ovld __cnfn smoothstep(double, double, double16); +double __ovld __cnfn smoothstep(double edge0, double edge1, double x); +double2 __ovld __cnfn smoothstep(double2 edge0, double2 edge1, double2 x); +double3 __ovld __cnfn smoothstep(double3 edge0, double3 edge1, double3 x); +double4 __ovld __cnfn smoothstep(double4 edge0, double4 edge1, double4 x); +double8 __ovld __cnfn smoothstep(double8 edge0, double8 edge1, double8 x); +double16 __ovld __cnfn smoothstep(double16 edge0, double16 edge1, double16 x); +double2 __ovld __cnfn smoothstep(double edge0, double edge1, double2 x); +double3 __ovld __cnfn smoothstep(double edge0, double edge1, double3 x); +double4 __ovld __cnfn smoothstep(double edge0, double edge1, double4 x); +double8 __ovld __cnfn smoothstep(double edge0, double edge1, double8 x); +double16 __ovld __cnfn smoothstep(double edge0, double edge1, double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn smoothstep(half, half, half); -half2 __ovld __cnfn smoothstep(half2, half2, half2); -half3 __ovld __cnfn smoothstep(half3, half3, half3); -half4 __ovld __cnfn smoothstep(half4, half4, half4); -half8 __ovld __cnfn smoothstep(half8, half8, half8); -half16 __ovld __cnfn smoothstep(half16, half16, half16); -half2 __ovld __cnfn smoothstep(half, half, half2); -half3 __ovld __cnfn smoothstep(half, half, half3); -half4 __ovld __cnfn smoothstep(half, half, half4); -half8 __ovld __cnfn smoothstep(half, half, half8); -half16 __ovld __cnfn smoothstep(half, half, half16); +half __ovld __cnfn smoothstep(half edge0, half edge1, half x); +half2 __ovld __cnfn smoothstep(half2 edge0, half2 edge1, half2 x); +half3 __ovld __cnfn smoothstep(half3 edge0, half3 edge1, half3 x); +half4 __ovld __cnfn smoothstep(half4 edge0, half4 edge1, half4 x); +half8 __ovld __cnfn smoothstep(half8 edge0, half8 edge1, half8 x); +half16 __ovld __cnfn smoothstep(half16 edge0, half16 edge1, half16 x); +half2 __ovld __cnfn smoothstep(half edge0, half edge1, half2 x); +half3 __ovld __cnfn smoothstep(half edge0, half edge1, half3 x); +half4 __ovld __cnfn smoothstep(half edge0, half edge1, half4 x); +half8 __ovld __cnfn smoothstep(half edge0, half edge1, half8 x); +half16 __ovld __cnfn smoothstep(half edge0, half edge1, half16 x); #endif //cl_khr_fp16 /** * Returns 1.0 if x > 0, -0.0 if x = -0.0, +0.0 if x = * +0.0, or -1.0 if x < 0. Returns 0.0 if x is a NaN. */ -float __ovld __cnfn sign(float); -float2 __ovld __cnfn sign(float2); -float3 __ovld __cnfn sign(float3); -float4 __ovld __cnfn sign(float4); -float8 __ovld __cnfn sign(float8); -float16 __ovld __cnfn sign(float16); +float __ovld __cnfn sign(float x); +float2 __ovld __cnfn sign(float2 x); +float3 __ovld __cnfn sign(float3 x); +float4 __ovld __cnfn sign(float4 x); +float8 __ovld __cnfn sign(float8 x); +float16 __ovld __cnfn sign(float16 x); #ifdef cl_khr_fp64 -double __ovld __cnfn sign(double); -double2 __ovld __cnfn sign(double2); -double3 __ovld __cnfn sign(double3); -double4 __ovld __cnfn sign(double4); -double8 __ovld __cnfn sign(double8); -double16 __ovld __cnfn sign(double16); +double __ovld __cnfn sign(double x); +double2 __ovld __cnfn sign(double2 x); +double3 __ovld __cnfn sign(double3 x); +double4 __ovld __cnfn sign(double4 x); +double8 __ovld __cnfn sign(double8 x); +double16 __ovld __cnfn sign(double16 x); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __cnfn sign(half); -half2 __ovld __cnfn sign(half2); -half3 __ovld __cnfn sign(half3); -half4 __ovld __cnfn sign(half4); -half8 __ovld __cnfn sign(half8); -half16 __ovld __cnfn sign(half16); +half __ovld __cnfn sign(half x); +half2 __ovld __cnfn sign(half2 x); +half3 __ovld __cnfn sign(half3 x); +half4 __ovld __cnfn sign(half4 x); +half8 __ovld __cnfn sign(half8 x); +half16 __ovld __cnfn sign(half16 x); #endif //cl_khr_fp16 // OpenCL v1.1 s6.11.5, v1.2 s6.12.5, v2.0 s6.13.5 - Geometric Functions @@ -10506,187 +11229,187 @@ float4 __ovld __cnfn fast_normalize(float4); // OpenCL v1.1 s6.11.6, v1.2 s6.12.6, v2.0 s6.13.6 - Relational Functions /** - * intn isequal (floatn x, floatn y) + * intn isequal (floatn, floatn ) * Returns the component-wise compare of x == y. */ -int __ovld __cnfn isequal(float, float); -int2 __ovld __cnfn isequal(float2, float2); -int3 __ovld __cnfn isequal(float3, float3); -int4 __ovld __cnfn isequal(float4, float4); -int8 __ovld __cnfn isequal(float8, float8); -int16 __ovld __cnfn isequal(float16, float16); +int __ovld __cnfn isequal(float, float ); +int2 __ovld __cnfn isequal(float2, float2 ); +int3 __ovld __cnfn isequal(float3, float3 ); +int4 __ovld __cnfn isequal(float4, float4 ); +int8 __ovld __cnfn isequal(float8, float8 ); +int16 __ovld __cnfn isequal(float16, float16 ); #ifdef cl_khr_fp64 -int __ovld __cnfn isequal(double, double); -long2 __ovld __cnfn isequal(double2, double2); -long3 __ovld __cnfn isequal(double3, double3); -long4 __ovld __cnfn isequal(double4, double4); -long8 __ovld __cnfn isequal(double8, double8); -long16 __ovld __cnfn isequal(double16, double16); +int __ovld __cnfn isequal(double, double ); +long2 __ovld __cnfn isequal(double2, double2 ); +long3 __ovld __cnfn isequal(double3, double3 ); +long4 __ovld __cnfn isequal(double4, double4 ); +long8 __ovld __cnfn isequal(double8, double8 ); +long16 __ovld __cnfn isequal(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -int __ovld __cnfn isequal(half, half); -short2 __ovld __cnfn isequal(half2, half2); -short3 __ovld __cnfn isequal(half3, half3); -short4 __ovld __cnfn isequal(half4, half4); -short8 __ovld __cnfn isequal(half8, half8); -short16 __ovld __cnfn isequal(half16, half16); +int __ovld __cnfn isequal(half, half ); +short2 __ovld __cnfn isequal(half2, half2 ); +short3 __ovld __cnfn isequal(half3, half3 ); +short4 __ovld __cnfn isequal(half4, half4 ); +short8 __ovld __cnfn isequal(half8, half8 ); +short16 __ovld __cnfn isequal(half16, half16 ); #endif //cl_khr_fp16 /** * Returns the component-wise compare of x != y. */ -int __ovld __cnfn isnotequal(float, float); -int2 __ovld __cnfn isnotequal(float2, float2); -int3 __ovld __cnfn isnotequal(float3, float3); -int4 __ovld __cnfn isnotequal(float4, float4); -int8 __ovld __cnfn isnotequal(float8, float8); -int16 __ovld __cnfn isnotequal(float16, float16); +int __ovld __cnfn isnotequal(float, float ); +int2 __ovld __cnfn isnotequal(float2, float2 ); +int3 __ovld __cnfn isnotequal(float3, float3 ); +int4 __ovld __cnfn isnotequal(float4, float4 ); +int8 __ovld __cnfn isnotequal(float8, float8 ); +int16 __ovld __cnfn isnotequal(float16, float16 ); #ifdef cl_khr_fp64 -int __ovld __cnfn isnotequal(double, double); -long2 __ovld __cnfn isnotequal(double2, double2); -long3 __ovld __cnfn isnotequal(double3, double3); -long4 __ovld __cnfn isnotequal(double4, double4); -long8 __ovld __cnfn isnotequal(double8, double8); -long16 __ovld __cnfn isnotequal(double16, double16); +int __ovld __cnfn isnotequal(double, double ); +long2 __ovld __cnfn isnotequal(double2, double2 ); +long3 __ovld __cnfn isnotequal(double3, double3 ); +long4 __ovld __cnfn isnotequal(double4, double4 ); +long8 __ovld __cnfn isnotequal(double8, double8 ); +long16 __ovld __cnfn isnotequal(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -int __ovld __cnfn isnotequal(half, half); -short2 __ovld __cnfn isnotequal(half2, half2); -short3 __ovld __cnfn isnotequal(half3, half3); -short4 __ovld __cnfn isnotequal(half4, half4); -short8 __ovld __cnfn isnotequal(half8, half8); -short16 __ovld __cnfn isnotequal(half16, half16); +int __ovld __cnfn isnotequal(half, half ); +short2 __ovld __cnfn isnotequal(half2, half2 ); +short3 __ovld __cnfn isnotequal(half3, half3 ); +short4 __ovld __cnfn isnotequal(half4, half4 ); +short8 __ovld __cnfn isnotequal(half8, half8 ); +short16 __ovld __cnfn isnotequal(half16, half16 ); #endif //cl_khr_fp16 /** * Returns the component-wise compare of x > y. */ -int __ovld __cnfn isgreater(float, float); -int2 __ovld __cnfn isgreater(float2, float2); -int3 __ovld __cnfn isgreater(float3, float3); -int4 __ovld __cnfn isgreater(float4, float4); -int8 __ovld __cnfn isgreater(float8, float8); -int16 __ovld __cnfn isgreater(float16, float16); +int __ovld __cnfn isgreater(float, float ); +int2 __ovld __cnfn isgreater(float2, float2 ); +int3 __ovld __cnfn isgreater(float3, float3 ); +int4 __ovld __cnfn isgreater(float4, float4 ); +int8 __ovld __cnfn isgreater(float8, float8 ); +int16 __ovld __cnfn isgreater(float16, float16 ); #ifdef cl_khr_fp64 -int __ovld __cnfn isgreater(double, double); -long2 __ovld __cnfn isgreater(double2, double2); -long3 __ovld __cnfn isgreater(double3, double3); -long4 __ovld __cnfn isgreater(double4, double4); -long8 __ovld __cnfn isgreater(double8, double8); -long16 __ovld __cnfn isgreater(double16, double16); +int __ovld __cnfn isgreater(double, double ); +long2 __ovld __cnfn isgreater(double2, double2 ); +long3 __ovld __cnfn isgreater(double3, double3 ); +long4 __ovld __cnfn isgreater(double4, double4 ); +long8 __ovld __cnfn isgreater(double8, double8 ); +long16 __ovld __cnfn isgreater(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -int __ovld __cnfn isgreater(half, half); -short2 __ovld __cnfn isgreater(half2, half2); -short3 __ovld __cnfn isgreater(half3, half3); -short4 __ovld __cnfn isgreater(half4, half4); -short8 __ovld __cnfn isgreater(half8, half8); -short16 __ovld __cnfn isgreater(half16, half16); +int __ovld __cnfn isgreater(half, half ); +short2 __ovld __cnfn isgreater(half2, half2 ); +short3 __ovld __cnfn isgreater(half3, half3 ); +short4 __ovld __cnfn isgreater(half4, half4 ); +short8 __ovld __cnfn isgreater(half8, half8 ); +short16 __ovld __cnfn isgreater(half16, half16 ); #endif //cl_khr_fp16 /** * Returns the component-wise compare of x >= y. */ -int __ovld __cnfn isgreaterequal(float, float); -int2 __ovld __cnfn isgreaterequal(float2, float2); -int3 __ovld __cnfn isgreaterequal(float3, float3); -int4 __ovld __cnfn isgreaterequal(float4, float4); -int8 __ovld __cnfn isgreaterequal(float8, float8); -int16 __ovld __cnfn isgreaterequal(float16, float16); +int __ovld __cnfn isgreaterequal(float, float ); +int2 __ovld __cnfn isgreaterequal(float2, float2 ); +int3 __ovld __cnfn isgreaterequal(float3, float3 ); +int4 __ovld __cnfn isgreaterequal(float4, float4 ); +int8 __ovld __cnfn isgreaterequal(float8, float8 ); +int16 __ovld __cnfn isgreaterequal(float16, float16 ); #ifdef cl_khr_fp64 -int __ovld __cnfn isgreaterequal(double, double); -long2 __ovld __cnfn isgreaterequal(double2, double2); -long3 __ovld __cnfn isgreaterequal(double3, double3); -long4 __ovld __cnfn isgreaterequal(double4, double4); -long8 __ovld __cnfn isgreaterequal(double8, double8); -long16 __ovld __cnfn isgreaterequal(double16, double16); +int __ovld __cnfn isgreaterequal(double, double ); +long2 __ovld __cnfn isgreaterequal(double2, double2 ); +long3 __ovld __cnfn isgreaterequal(double3, double3 ); +long4 __ovld __cnfn isgreaterequal(double4, double4 ); +long8 __ovld __cnfn isgreaterequal(double8, double8 ); +long16 __ovld __cnfn isgreaterequal(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -int __ovld __cnfn isgreaterequal(half, half); -short2 __ovld __cnfn isgreaterequal(half2, half2); -short3 __ovld __cnfn isgreaterequal(half3, half3); -short4 __ovld __cnfn isgreaterequal(half4, half4); -short8 __ovld __cnfn isgreaterequal(half8, half8); -short16 __ovld __cnfn isgreaterequal(half16, half16); +int __ovld __cnfn isgreaterequal(half, half ); +short2 __ovld __cnfn isgreaterequal(half2, half2 ); +short3 __ovld __cnfn isgreaterequal(half3, half3 ); +short4 __ovld __cnfn isgreaterequal(half4, half4 ); +short8 __ovld __cnfn isgreaterequal(half8, half8 ); +short16 __ovld __cnfn isgreaterequal(half16, half16 ); #endif //cl_khr_fp16 /** * Returns the component-wise compare of x < y. */ -int __ovld __cnfn isless(float, float); -int2 __ovld __cnfn isless(float2, float2); -int3 __ovld __cnfn isless(float3, float3); -int4 __ovld __cnfn isless(float4, float4); -int8 __ovld __cnfn isless(float8, float8); -int16 __ovld __cnfn isless(float16, float16); +int __ovld __cnfn isless(float, float ); +int2 __ovld __cnfn isless(float2, float2 ); +int3 __ovld __cnfn isless(float3, float3 ); +int4 __ovld __cnfn isless(float4, float4 ); +int8 __ovld __cnfn isless(float8, float8 ); +int16 __ovld __cnfn isless(float16, float16 ); #ifdef cl_khr_fp64 -int __ovld __cnfn isless(double, double); -long2 __ovld __cnfn isless(double2, double2); -long3 __ovld __cnfn isless(double3, double3); -long4 __ovld __cnfn isless(double4, double4); -long8 __ovld __cnfn isless(double8, double8); -long16 __ovld __cnfn isless(double16, double16); +int __ovld __cnfn isless(double, double ); +long2 __ovld __cnfn isless(double2, double2 ); +long3 __ovld __cnfn isless(double3, double3 ); +long4 __ovld __cnfn isless(double4, double4 ); +long8 __ovld __cnfn isless(double8, double8 ); +long16 __ovld __cnfn isless(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -int __ovld __cnfn isless(half, half); -short2 __ovld __cnfn isless(half2, half2); -short3 __ovld __cnfn isless(half3, half3); -short4 __ovld __cnfn isless(half4, half4); -short8 __ovld __cnfn isless(half8, half8); -short16 __ovld __cnfn isless(half16, half16); +int __ovld __cnfn isless(half, half ); +short2 __ovld __cnfn isless(half2, half2 ); +short3 __ovld __cnfn isless(half3, half3 ); +short4 __ovld __cnfn isless(half4, half4 ); +short8 __ovld __cnfn isless(half8, half8 ); +short16 __ovld __cnfn isless(half16, half16 ); #endif //cl_khr_fp16 /** * Returns the component-wise compare of x <= y. */ -int __ovld __cnfn islessequal(float, float); -int2 __ovld __cnfn islessequal(float2, float2); -int3 __ovld __cnfn islessequal(float3, float3); -int4 __ovld __cnfn islessequal(float4, float4); -int8 __ovld __cnfn islessequal(float8, float8); -int16 __ovld __cnfn islessequal(float16, float16); +int __ovld __cnfn islessequal(float, float ); +int2 __ovld __cnfn islessequal(float2, float2 ); +int3 __ovld __cnfn islessequal(float3, float3 ); +int4 __ovld __cnfn islessequal(float4, float4 ); +int8 __ovld __cnfn islessequal(float8, float8 ); +int16 __ovld __cnfn islessequal(float16, float16 ); #ifdef cl_khr_fp64 -int __ovld __cnfn islessequal(double, double); -long2 __ovld __cnfn islessequal(double2, double2); -long3 __ovld __cnfn islessequal(double3, double3); -long4 __ovld __cnfn islessequal(double4, double4); -long8 __ovld __cnfn islessequal(double8, double8); -long16 __ovld __cnfn islessequal(double16, double16); +int __ovld __cnfn islessequal(double, double ); +long2 __ovld __cnfn islessequal(double2, double2 ); +long3 __ovld __cnfn islessequal(double3, double3 ); +long4 __ovld __cnfn islessequal(double4, double4 ); +long8 __ovld __cnfn islessequal(double8, double8 ); +long16 __ovld __cnfn islessequal(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -int __ovld __cnfn islessequal(half, half); -short2 __ovld __cnfn islessequal(half2, half2); -short3 __ovld __cnfn islessequal(half3, half3); -short4 __ovld __cnfn islessequal(half4, half4); -short8 __ovld __cnfn islessequal(half8, half8); -short16 __ovld __cnfn islessequal(half16, half16); +int __ovld __cnfn islessequal(half, half ); +short2 __ovld __cnfn islessequal(half2, half2 ); +short3 __ovld __cnfn islessequal(half3, half3 ); +short4 __ovld __cnfn islessequal(half4, half4 ); +short8 __ovld __cnfn islessequal(half8, half8 ); +short16 __ovld __cnfn islessequal(half16, half16 ); #endif //cl_khr_fp16 /** * Returns the component-wise compare of - * (x < y) || (x > y) . + * (x < ) || (x > y) . */ -int __ovld __cnfn islessgreater(float, float); -int2 __ovld __cnfn islessgreater(float2, float2); -int3 __ovld __cnfn islessgreater(float3, float3); -int4 __ovld __cnfn islessgreater(float4, float4); -int8 __ovld __cnfn islessgreater(float8, float8); -int16 __ovld __cnfn islessgreater(float16, float16); +int __ovld __cnfn islessgreater(float, float ); +int2 __ovld __cnfn islessgreater(float2, float2 ); +int3 __ovld __cnfn islessgreater(float3, float3 ); +int4 __ovld __cnfn islessgreater(float4, float4 ); +int8 __ovld __cnfn islessgreater(float8, float8 ); +int16 __ovld __cnfn islessgreater(float16, float16 ); #ifdef cl_khr_fp64 -int __ovld __cnfn islessgreater(double, double); -long2 __ovld __cnfn islessgreater(double2, double2); -long3 __ovld __cnfn islessgreater(double3, double3); -long4 __ovld __cnfn islessgreater(double4, double4); -long8 __ovld __cnfn islessgreater(double8, double8); -long16 __ovld __cnfn islessgreater(double16, double16); +int __ovld __cnfn islessgreater(double, double ); +long2 __ovld __cnfn islessgreater(double2, double2 ); +long3 __ovld __cnfn islessgreater(double3, double3 ); +long4 __ovld __cnfn islessgreater(double4, double4 ); +long8 __ovld __cnfn islessgreater(double8, double8 ); +long16 __ovld __cnfn islessgreater(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -int __ovld __cnfn islessgreater(half, half); -short2 __ovld __cnfn islessgreater(half2, half2); -short3 __ovld __cnfn islessgreater(half3, half3); -short4 __ovld __cnfn islessgreater(half4, half4); -short8 __ovld __cnfn islessgreater(half8, half8); -short16 __ovld __cnfn islessgreater(half16, half16); +int __ovld __cnfn islessgreater(half, half ); +short2 __ovld __cnfn islessgreater(half2, half2 ); +short3 __ovld __cnfn islessgreater(half3, half3 ); +short4 __ovld __cnfn islessgreater(half4, half4 ); +short8 __ovld __cnfn islessgreater(half8, half8 ); +short16 __ovld __cnfn islessgreater(half16, half16 ); #endif //cl_khr_fp16 /** @@ -10795,58 +11518,58 @@ short16 __ovld __cnfn isnormal(half16); /** * Test if arguments are ordered. isordered() takes - * arguments x and y, and returns the result - * isequal(x, x) && isequal(y, y). + * arguments x and, and returns the result + * isequal(x, x) && isequal(y, ). */ -int __ovld __cnfn isordered(float, float); -int2 __ovld __cnfn isordered(float2, float2); -int3 __ovld __cnfn isordered(float3, float3); -int4 __ovld __cnfn isordered(float4, float4); -int8 __ovld __cnfn isordered(float8, float8); -int16 __ovld __cnfn isordered(float16, float16); +int __ovld __cnfn isordered(float, float ); +int2 __ovld __cnfn isordered(float2, float2 ); +int3 __ovld __cnfn isordered(float3, float3 ); +int4 __ovld __cnfn isordered(float4, float4 ); +int8 __ovld __cnfn isordered(float8, float8 ); +int16 __ovld __cnfn isordered(float16, float16 ); #ifdef cl_khr_fp64 -int __ovld __cnfn isordered(double, double); -long2 __ovld __cnfn isordered(double2, double2); -long3 __ovld __cnfn isordered(double3, double3); -long4 __ovld __cnfn isordered(double4, double4); -long8 __ovld __cnfn isordered(double8, double8); -long16 __ovld __cnfn isordered(double16, double16); +int __ovld __cnfn isordered(double, double ); +long2 __ovld __cnfn isordered(double2, double2 ); +long3 __ovld __cnfn isordered(double3, double3 ); +long4 __ovld __cnfn isordered(double4, double4 ); +long8 __ovld __cnfn isordered(double8, double8 ); +long16 __ovld __cnfn isordered(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -int __ovld __cnfn isordered(half, half); -short2 __ovld __cnfn isordered(half2, half2); -short3 __ovld __cnfn isordered(half3, half3); -short4 __ovld __cnfn isordered(half4, half4); -short8 __ovld __cnfn isordered(half8, half8); -short16 __ovld __cnfn isordered(half16, half16); +int __ovld __cnfn isordered(half, half ); +short2 __ovld __cnfn isordered(half2, half2 ); +short3 __ovld __cnfn isordered(half3, half3 ); +short4 __ovld __cnfn isordered(half4, half4 ); +short8 __ovld __cnfn isordered(half8, half8 ); +short16 __ovld __cnfn isordered(half16, half16 ); #endif //cl_khr_fp16 /** * Test if arguments are unordered. isunordered() - * takes arguments x and y, returning non-zero if x or y + * takes arguments x and, returning non-zero if x or y * is NaN, and zero otherwise. */ -int __ovld __cnfn isunordered(float, float); -int2 __ovld __cnfn isunordered(float2, float2); -int3 __ovld __cnfn isunordered(float3, float3); -int4 __ovld __cnfn isunordered(float4, float4); -int8 __ovld __cnfn isunordered(float8, float8); -int16 __ovld __cnfn isunordered(float16, float16); +int __ovld __cnfn isunordered(float, float ); +int2 __ovld __cnfn isunordered(float2, float2 ); +int3 __ovld __cnfn isunordered(float3, float3 ); +int4 __ovld __cnfn isunordered(float4, float4 ); +int8 __ovld __cnfn isunordered(float8, float8 ); +int16 __ovld __cnfn isunordered(float16, float16 ); #ifdef cl_khr_fp64 -int __ovld __cnfn isunordered(double, double); -long2 __ovld __cnfn isunordered(double2, double2); -long3 __ovld __cnfn isunordered(double3, double3); -long4 __ovld __cnfn isunordered(double4, double4); -long8 __ovld __cnfn isunordered(double8, double8); -long16 __ovld __cnfn isunordered(double16, double16); +int __ovld __cnfn isunordered(double, double ); +long2 __ovld __cnfn isunordered(double2, double2 ); +long3 __ovld __cnfn isunordered(double3, double3 ); +long4 __ovld __cnfn isunordered(double4, double4 ); +long8 __ovld __cnfn isunordered(double8, double8 ); +long16 __ovld __cnfn isunordered(double16, double16 ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -int __ovld __cnfn isunordered(half, half); -short2 __ovld __cnfn isunordered(half2, half2); -short3 __ovld __cnfn isunordered(half3, half3); -short4 __ovld __cnfn isunordered(half4, half4); -short8 __ovld __cnfn isunordered(half8, half8); -short16 __ovld __cnfn isunordered(half16, half16); +int __ovld __cnfn isunordered(half, half ); +short2 __ovld __cnfn isunordered(half2, half2 ); +short3 __ovld __cnfn isunordered(half3, half3 ); +short4 __ovld __cnfn isunordered(half4, half4 ); +short8 __ovld __cnfn isunordered(half8, half8 ); +short16 __ovld __cnfn isunordered(half16, half16 ); #endif //cl_khr_fp16 /** @@ -10883,59 +11606,59 @@ short16 __ovld __cnfn signbit(half16); * Returns 1 if the most significant bit in any component * of x is set; otherwise returns 0. */ -int __ovld __cnfn any(char); -int __ovld __cnfn any(char2); -int __ovld __cnfn any(char3); -int __ovld __cnfn any(char4); -int __ovld __cnfn any(char8); -int __ovld __cnfn any(char16); -int __ovld __cnfn any(short); -int __ovld __cnfn any(short2); -int __ovld __cnfn any(short3); -int __ovld __cnfn any(short4); -int __ovld __cnfn any(short8); -int __ovld __cnfn any(short16); -int __ovld __cnfn any(int); -int __ovld __cnfn any(int2); -int __ovld __cnfn any(int3); -int __ovld __cnfn any(int4); -int __ovld __cnfn any(int8); -int __ovld __cnfn any(int16); -int __ovld __cnfn any(long); -int __ovld __cnfn any(long2); -int __ovld __cnfn any(long3); -int __ovld __cnfn any(long4); -int __ovld __cnfn any(long8); -int __ovld __cnfn any(long16); +int __ovld __cnfn any(char x); +int __ovld __cnfn any(char2 x); +int __ovld __cnfn any(char3 x); +int __ovld __cnfn any(char4 x); +int __ovld __cnfn any(char8 x); +int __ovld __cnfn any(char16 x); +int __ovld __cnfn any(short x); +int __ovld __cnfn any(short2 x); +int __ovld __cnfn any(short3 x); +int __ovld __cnfn any(short4 x); +int __ovld __cnfn any(short8 x); +int __ovld __cnfn any(short16 x); +int __ovld __cnfn any(int x); +int __ovld __cnfn any(int2 x); +int __ovld __cnfn any(int3 x); +int __ovld __cnfn any(int4 x); +int __ovld __cnfn any(int8 x); +int __ovld __cnfn any(int16 x); +int __ovld __cnfn any(long x); +int __ovld __cnfn any(long2 x); +int __ovld __cnfn any(long3 x); +int __ovld __cnfn any(long4 x); +int __ovld __cnfn any(long8 x); +int __ovld __cnfn any(long16 x); /** * Returns 1 if the most significant bit in all components * of x is set; otherwise returns 0. */ -int __ovld __cnfn all(char); -int __ovld __cnfn all(char2); -int __ovld __cnfn all(char3); -int __ovld __cnfn all(char4); -int __ovld __cnfn all(char8); -int __ovld __cnfn all(char16); -int __ovld __cnfn all(short); -int __ovld __cnfn all(short2); -int __ovld __cnfn all(short3); -int __ovld __cnfn all(short4); -int __ovld __cnfn all(short8); -int __ovld __cnfn all(short16); -int __ovld __cnfn all(int); -int __ovld __cnfn all(int2); -int __ovld __cnfn all(int3); -int __ovld __cnfn all(int4); -int __ovld __cnfn all(int8); -int __ovld __cnfn all(int16); -int __ovld __cnfn all(long); -int __ovld __cnfn all(long2); -int __ovld __cnfn all(long3); -int __ovld __cnfn all(long4); -int __ovld __cnfn all(long8); -int __ovld __cnfn all(long16); +int __ovld __cnfn all(char x); +int __ovld __cnfn all(char2 x); +int __ovld __cnfn all(char3 x); +int __ovld __cnfn all(char4 x); +int __ovld __cnfn all(char8 x); +int __ovld __cnfn all(char16 x); +int __ovld __cnfn all(short x); +int __ovld __cnfn all(short2 x); +int __ovld __cnfn all(short3 x); +int __ovld __cnfn all(short4 x); +int __ovld __cnfn all(short8 x); +int __ovld __cnfn all(short16 x); +int __ovld __cnfn all(int x); +int __ovld __cnfn all(int2 x); +int __ovld __cnfn all(int3 x); +int __ovld __cnfn all(int4 x); +int __ovld __cnfn all(int8 x); +int __ovld __cnfn all(int16 x); +int __ovld __cnfn all(long x); +int __ovld __cnfn all(long2 x); +int __ovld __cnfn all(long3 x); +int __ovld __cnfn all(long4 x); +int __ovld __cnfn all(long8 x); +int __ovld __cnfn all(long16 x); /** * Each bit of the result is the corresponding bit of a if @@ -11306,9 +12029,7 @@ half4 __ovld __purefn vload4(size_t, const half *); half8 __ovld __purefn vload8(size_t, const half *); half16 __ovld __purefn vload16(size_t, const half *); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) +#else char2 __ovld __purefn vload2(size_t, const __global char *); uchar2 __ovld __purefn vload2(size_t, const __global uchar *); short2 __ovld __purefn vload2(size_t, const __global short *); @@ -11480,241 +12201,244 @@ half4 __ovld __purefn vload4(size_t, const __private half *); half8 __ovld __purefn vload8(size_t, const __private half *); half16 __ovld __purefn vload16(size_t, const __private half *); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) #if defined(__opencl_c_generic_address_space) -void __ovld vstore2(char2, size_t, char *); -void __ovld vstore2(uchar2, size_t, uchar *); -void __ovld vstore2(short2, size_t, short *); -void __ovld vstore2(ushort2, size_t, ushort *); -void __ovld vstore2(int2, size_t, int *); -void __ovld vstore2(uint2, size_t, uint *); -void __ovld vstore2(long2, size_t, long *); -void __ovld vstore2(ulong2, size_t, ulong *); -void __ovld vstore2(float2, size_t, float *); -void __ovld vstore3(char3, size_t, char *); -void __ovld vstore3(uchar3, size_t, uchar *); -void __ovld vstore3(short3, size_t, short *); -void __ovld vstore3(ushort3, size_t, ushort *); -void __ovld vstore3(int3, size_t, int *); -void __ovld vstore3(uint3, size_t, uint *); -void __ovld vstore3(long3, size_t, long *); -void __ovld vstore3(ulong3, size_t, ulong *); -void __ovld vstore3(float3, size_t, float *); -void __ovld vstore4(char4, size_t, char *); -void __ovld vstore4(uchar4, size_t, uchar *); -void __ovld vstore4(short4, size_t, short *); -void __ovld vstore4(ushort4, size_t, ushort *); -void __ovld vstore4(int4, size_t, int *); -void __ovld vstore4(uint4, size_t, uint *); -void __ovld vstore4(long4, size_t, long *); -void __ovld vstore4(ulong4, size_t, ulong *); -void __ovld vstore4(float4, size_t, float *); -void __ovld vstore8(char8, size_t, char *); -void __ovld vstore8(uchar8, size_t, uchar *); -void __ovld vstore8(short8, size_t, short *); -void __ovld vstore8(ushort8, size_t, ushort *); -void __ovld vstore8(int8, size_t, int *); -void __ovld vstore8(uint8, size_t, uint *); -void __ovld vstore8(long8, size_t, long *); -void __ovld vstore8(ulong8, size_t, ulong *); -void __ovld vstore8(float8, size_t, float *); -void __ovld vstore16(char16, size_t, char *); -void __ovld vstore16(uchar16, size_t, uchar *); -void __ovld vstore16(short16, size_t, short *); -void __ovld vstore16(ushort16, size_t, ushort *); -void __ovld vstore16(int16, size_t, int *); -void __ovld vstore16(uint16, size_t, uint *); -void __ovld vstore16(long16, size_t, long *); -void __ovld vstore16(ulong16, size_t, ulong *); -void __ovld vstore16(float16, size_t, float *); +void __ovld vstore2(char2 data, size_t, char *); +void __ovld vstore2(uchar2 data, size_t, uchar *); +void __ovld vstore2(short2 data, size_t, short *); +void __ovld vstore2(ushort2 data, size_t, ushort *); +void __ovld vstore2(int2 data, size_t, int *); +void __ovld vstore2(uint2 data, size_t, uint *); +void __ovld vstore2(long2 data, size_t, long *); +void __ovld vstore2(ulong2 data, size_t, ulong *); +void __ovld vstore2(float2 data, size_t, float *); +void __ovld vstore3(char3 data, size_t, char *); +void __ovld vstore3(uchar3 data, size_t, uchar *); +void __ovld vstore3(short3 data, size_t, short *); +void __ovld vstore3(ushort3 data, size_t, ushort *); +void __ovld vstore3(int3 data, size_t, int *); +void __ovld vstore3(uint3 data, size_t, uint *); +void __ovld vstore3(long3 data, size_t, long *); +void __ovld vstore3(ulong3 data, size_t, ulong *); +void __ovld vstore3(float3 data, size_t, float *); +void __ovld vstore4(char4 data, size_t, char *); +void __ovld vstore4(uchar4 data, size_t, uchar *); +void __ovld vstore4(short4 data, size_t, short *); +void __ovld vstore4(ushort4 data, size_t, ushort *); +void __ovld vstore4(int4 data, size_t, int *); +void __ovld vstore4(uint4 data, size_t, uint *); +void __ovld vstore4(long4 data, size_t, long *); +void __ovld vstore4(ulong4 data, size_t, ulong *); +void __ovld vstore4(float4 data, size_t, float *); +void __ovld vstore8(char8 data, size_t, char *); +void __ovld vstore8(uchar8 data, size_t, uchar *); +void __ovld vstore8(short8 data, size_t, short *); +void __ovld vstore8(ushort8 data, size_t, ushort *); +void __ovld vstore8(int8 data, size_t, int *); +void __ovld vstore8(uint8 data, size_t, uint *); +void __ovld vstore8(long8 data, size_t, long *); +void __ovld vstore8(ulong8 data, size_t, ulong *); +void __ovld vstore8(float8 data, size_t, float *); +void __ovld vstore16(char16 data, size_t, char *); +void __ovld vstore16(uchar16 data, size_t, uchar *); +void __ovld vstore16(short16 data, size_t, short *); +void __ovld vstore16(ushort16 data, size_t, ushort *); +void __ovld vstore16(int16 data, size_t, int *); +void __ovld vstore16(uint16 data, size_t, uint *); +void __ovld vstore16(long16 data, size_t, long *); +void __ovld vstore16(ulong16 data, size_t, ulong *); +void __ovld vstore16(float16 data, size_t, float *); #ifdef cl_khr_fp64 -void __ovld vstore2(double2, size_t, double *); -void __ovld vstore3(double3, size_t, double *); -void __ovld vstore4(double4, size_t, double *); -void __ovld vstore8(double8, size_t, double *); -void __ovld vstore16(double16, size_t, double *); +void __ovld vstore2(double2 data, size_t, double *); +void __ovld vstore3(double3 data, size_t, double *); +void __ovld vstore4(double4 data, size_t, double *); +void __ovld vstore8(double8 data, size_t, double *); +void __ovld vstore16(double16 data, size_t, double *); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 + +void __ovld vstore(half, size_t, half *); void __ovld vstore2(half2, size_t, half *); void __ovld vstore3(half3, size_t, half *); void __ovld vstore4(half4, size_t, half *); void __ovld vstore8(half8, size_t, half *); void __ovld vstore16(half16, size_t, half *); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) -void __ovld vstore2(char2, size_t, __global char *); -void __ovld vstore2(uchar2, size_t, __global uchar *); -void __ovld vstore2(short2, size_t, __global short *); -void __ovld vstore2(ushort2, size_t, __global ushort *); -void __ovld vstore2(int2, size_t, __global int *); -void __ovld vstore2(uint2, size_t, __global uint *); -void __ovld vstore2(long2, size_t, __global long *); -void __ovld vstore2(ulong2, size_t, __global ulong *); -void __ovld vstore2(float2, size_t, __global float *); -void __ovld vstore3(char3, size_t, __global char *); -void __ovld vstore3(uchar3, size_t, __global uchar *); -void __ovld vstore3(short3, size_t, __global short *); -void __ovld vstore3(ushort3, size_t, __global ushort *); -void __ovld vstore3(int3, size_t, __global int *); -void __ovld vstore3(uint3, size_t, __global uint *); -void __ovld vstore3(long3, size_t, __global long *); -void __ovld vstore3(ulong3, size_t, __global ulong *); -void __ovld vstore3(float3, size_t, __global float *); -void __ovld vstore4(char4, size_t, __global char *); -void __ovld vstore4(uchar4, size_t, __global uchar *); -void __ovld vstore4(short4, size_t, __global short *); -void __ovld vstore4(ushort4, size_t, __global ushort *); -void __ovld vstore4(int4, size_t, __global int *); -void __ovld vstore4(uint4, size_t, __global uint *); -void __ovld vstore4(long4, size_t, __global long *); -void __ovld vstore4(ulong4, size_t, __global ulong *); -void __ovld vstore4(float4, size_t, __global float *); -void __ovld vstore8(char8, size_t, __global char *); -void __ovld vstore8(uchar8, size_t, __global uchar *); -void __ovld vstore8(short8, size_t, __global short *); -void __ovld vstore8(ushort8, size_t, __global ushort *); -void __ovld vstore8(int8, size_t, __global int *); -void __ovld vstore8(uint8, size_t, __global uint *); -void __ovld vstore8(long8, size_t, __global long *); -void __ovld vstore8(ulong8, size_t, __global ulong *); -void __ovld vstore8(float8, size_t, __global float *); -void __ovld vstore16(char16, size_t, __global char *); -void __ovld vstore16(uchar16, size_t, __global uchar *); -void __ovld vstore16(short16, size_t, __global short *); -void __ovld vstore16(ushort16, size_t, __global ushort *); -void __ovld vstore16(int16, size_t, __global int *); -void __ovld vstore16(uint16, size_t, __global uint *); -void __ovld vstore16(long16, size_t, __global long *); -void __ovld vstore16(ulong16, size_t, __global ulong *); -void __ovld vstore16(float16, size_t, __global float *); -void __ovld vstore2(char2, size_t, __local char *); -void __ovld vstore2(uchar2, size_t, __local uchar *); -void __ovld vstore2(short2, size_t, __local short *); -void __ovld vstore2(ushort2, size_t, __local ushort *); -void __ovld vstore2(int2, size_t, __local int *); -void __ovld vstore2(uint2, size_t, __local uint *); -void __ovld vstore2(long2, size_t, __local long *); -void __ovld vstore2(ulong2, size_t, __local ulong *); -void __ovld vstore2(float2, size_t, __local float *); -void __ovld vstore3(char3, size_t, __local char *); -void __ovld vstore3(uchar3, size_t, __local uchar *); -void __ovld vstore3(short3, size_t, __local short *); -void __ovld vstore3(ushort3, size_t, __local ushort *); -void __ovld vstore3(int3, size_t, __local int *); -void __ovld vstore3(uint3, size_t, __local uint *); -void __ovld vstore3(long3, size_t, __local long *); -void __ovld vstore3(ulong3, size_t, __local ulong *); -void __ovld vstore3(float3, size_t, __local float *); -void __ovld vstore4(char4, size_t, __local char *); -void __ovld vstore4(uchar4, size_t, __local uchar *); -void __ovld vstore4(short4, size_t, __local short *); -void __ovld vstore4(ushort4, size_t, __local ushort *); -void __ovld vstore4(int4, size_t, __local int *); -void __ovld vstore4(uint4, size_t, __local uint *); -void __ovld vstore4(long4, size_t, __local long *); -void __ovld vstore4(ulong4, size_t, __local ulong *); -void __ovld vstore4(float4, size_t, __local float *); -void __ovld vstore8(char8, size_t, __local char *); -void __ovld vstore8(uchar8, size_t, __local uchar *); -void __ovld vstore8(short8, size_t, __local short *); -void __ovld vstore8(ushort8, size_t, __local ushort *); -void __ovld vstore8(int8, size_t, __local int *); -void __ovld vstore8(uint8, size_t, __local uint *); -void __ovld vstore8(long8, size_t, __local long *); -void __ovld vstore8(ulong8, size_t, __local ulong *); -void __ovld vstore8(float8, size_t, __local float *); -void __ovld vstore16(char16, size_t, __local char *); -void __ovld vstore16(uchar16, size_t, __local uchar *); -void __ovld vstore16(short16, size_t, __local short *); -void __ovld vstore16(ushort16, size_t, __local ushort *); -void __ovld vstore16(int16, size_t, __local int *); -void __ovld vstore16(uint16, size_t, __local uint *); -void __ovld vstore16(long16, size_t, __local long *); -void __ovld vstore16(ulong16, size_t, __local ulong *); -void __ovld vstore16(float16, size_t, __local float *); -void __ovld vstore2(char2, size_t, __private char *); -void __ovld vstore2(uchar2, size_t, __private uchar *); -void __ovld vstore2(short2, size_t, __private short *); -void __ovld vstore2(ushort2, size_t, __private ushort *); -void __ovld vstore2(int2, size_t, __private int *); -void __ovld vstore2(uint2, size_t, __private uint *); -void __ovld vstore2(long2, size_t, __private long *); -void __ovld vstore2(ulong2, size_t, __private ulong *); -void __ovld vstore2(float2, size_t, __private float *); -void __ovld vstore3(char3, size_t, __private char *); -void __ovld vstore3(uchar3, size_t, __private uchar *); -void __ovld vstore3(short3, size_t, __private short *); -void __ovld vstore3(ushort3, size_t, __private ushort *); -void __ovld vstore3(int3, size_t, __private int *); -void __ovld vstore3(uint3, size_t, __private uint *); -void __ovld vstore3(long3, size_t, __private long *); -void __ovld vstore3(ulong3, size_t, __private ulong *); -void __ovld vstore3(float3, size_t, __private float *); -void __ovld vstore4(char4, size_t, __private char *); -void __ovld vstore4(uchar4, size_t, __private uchar *); -void __ovld vstore4(short4, size_t, __private short *); -void __ovld vstore4(ushort4, size_t, __private ushort *); -void __ovld vstore4(int4, size_t, __private int *); -void __ovld vstore4(uint4, size_t, __private uint *); -void __ovld vstore4(long4, size_t, __private long *); -void __ovld vstore4(ulong4, size_t, __private ulong *); -void __ovld vstore4(float4, size_t, __private float *); -void __ovld vstore8(char8, size_t, __private char *); -void __ovld vstore8(uchar8, size_t, __private uchar *); -void __ovld vstore8(short8, size_t, __private short *); -void __ovld vstore8(ushort8, size_t, __private ushort *); -void __ovld vstore8(int8, size_t, __private int *); -void __ovld vstore8(uint8, size_t, __private uint *); -void __ovld vstore8(long8, size_t, __private long *); -void __ovld vstore8(ulong8, size_t, __private ulong *); -void __ovld vstore8(float8, size_t, __private float *); -void __ovld vstore16(char16, size_t, __private char *); -void __ovld vstore16(uchar16, size_t, __private uchar *); -void __ovld vstore16(short16, size_t, __private short *); -void __ovld vstore16(ushort16, size_t, __private ushort *); -void __ovld vstore16(int16, size_t, __private int *); -void __ovld vstore16(uint16, size_t, __private uint *); -void __ovld vstore16(long16, size_t, __private long *); -void __ovld vstore16(ulong16, size_t, __private ulong *); -void __ovld vstore16(float16, size_t, __private float *); +#else +void __ovld vstore2(char2 data, size_t, __global char *); +void __ovld vstore2(uchar2 data, size_t, __global uchar *); +void __ovld vstore2(short2 data, size_t, __global short *); +void __ovld vstore2(ushort2 data, size_t, __global ushort *); +void __ovld vstore2(int2 data, size_t, __global int *); +void __ovld vstore2(uint2 data, size_t, __global uint *); +void __ovld vstore2(long2 data, size_t, __global long *); +void __ovld vstore2(ulong2 data, size_t, __global ulong *); +void __ovld vstore2(float2 data, size_t, __global float *); +void __ovld vstore3(char3 data, size_t, __global char *); +void __ovld vstore3(uchar3 data, size_t, __global uchar *); +void __ovld vstore3(short3 data, size_t, __global short *); +void __ovld vstore3(ushort3 data, size_t, __global ushort *); +void __ovld vstore3(int3 data, size_t, __global int *); +void __ovld vstore3(uint3 data, size_t, __global uint *); +void __ovld vstore3(long3 data, size_t, __global long *); +void __ovld vstore3(ulong3 data, size_t, __global ulong *); +void __ovld vstore3(float3 data, size_t, __global float *); +void __ovld vstore4(char4 data, size_t, __global char *); +void __ovld vstore4(uchar4 data, size_t, __global uchar *); +void __ovld vstore4(short4 data, size_t, __global short *); +void __ovld vstore4(ushort4 data, size_t, __global ushort *); +void __ovld vstore4(int4 data, size_t, __global int *); +void __ovld vstore4(uint4 data, size_t, __global uint *); +void __ovld vstore4(long4 data, size_t, __global long *); +void __ovld vstore4(ulong4 data, size_t, __global ulong *); +void __ovld vstore4(float4 data, size_t, __global float *); +void __ovld vstore8(char8 data, size_t, __global char *); +void __ovld vstore8(uchar8 data, size_t, __global uchar *); +void __ovld vstore8(short8 data, size_t, __global short *); +void __ovld vstore8(ushort8 data, size_t, __global ushort *); +void __ovld vstore8(int8 data, size_t, __global int *); +void __ovld vstore8(uint8 data, size_t, __global uint *); +void __ovld vstore8(long8 data, size_t, __global long *); +void __ovld vstore8(ulong8 data, size_t, __global ulong *); +void __ovld vstore8(float8 data, size_t, __global float *); +void __ovld vstore16(char16 data, size_t, __global char *); +void __ovld vstore16(uchar16 data, size_t, __global uchar *); +void __ovld vstore16(short16 data, size_t, __global short *); +void __ovld vstore16(ushort16 data, size_t, __global ushort *); +void __ovld vstore16(int16 data, size_t, __global int *); +void __ovld vstore16(uint16 data, size_t, __global uint *); +void __ovld vstore16(long16 data, size_t, __global long *); +void __ovld vstore16(ulong16 data, size_t, __global ulong *); +void __ovld vstore16(float16 data, size_t, __global float *); +void __ovld vstore2(char2 data, size_t, __local char *); +void __ovld vstore2(uchar2 data, size_t, __local uchar *); +void __ovld vstore2(short2 data, size_t, __local short *); +void __ovld vstore2(ushort2 data, size_t, __local ushort *); +void __ovld vstore2(int2 data, size_t, __local int *); +void __ovld vstore2(uint2 data, size_t, __local uint *); +void __ovld vstore2(long2 data, size_t, __local long *); +void __ovld vstore2(ulong2 data, size_t, __local ulong *); +void __ovld vstore2(float2 data, size_t, __local float *); +void __ovld vstore3(char3 data, size_t, __local char *); +void __ovld vstore3(uchar3 data, size_t, __local uchar *); +void __ovld vstore3(short3 data, size_t, __local short *); +void __ovld vstore3(ushort3 data, size_t, __local ushort *); +void __ovld vstore3(int3 data, size_t, __local int *); +void __ovld vstore3(uint3 data, size_t, __local uint *); +void __ovld vstore3(long3 data, size_t, __local long *); +void __ovld vstore3(ulong3 data, size_t, __local ulong *); +void __ovld vstore3(float3 data, size_t, __local float *); +void __ovld vstore4(char4 data, size_t, __local char *); +void __ovld vstore4(uchar4 data, size_t, __local uchar *); +void __ovld vstore4(short4 data, size_t, __local short *); +void __ovld vstore4(ushort4 data, size_t, __local ushort *); +void __ovld vstore4(int4 data, size_t, __local int *); +void __ovld vstore4(uint4 data, size_t, __local uint *); +void __ovld vstore4(long4 data, size_t, __local long *); +void __ovld vstore4(ulong4 data, size_t, __local ulong *); +void __ovld vstore4(float4 data, size_t, __local float *); +void __ovld vstore8(char8 data, size_t, __local char *); +void __ovld vstore8(uchar8 data, size_t, __local uchar *); +void __ovld vstore8(short8 data, size_t, __local short *); +void __ovld vstore8(ushort8 data, size_t, __local ushort *); +void __ovld vstore8(int8 data, size_t, __local int *); +void __ovld vstore8(uint8 data, size_t, __local uint *); +void __ovld vstore8(long8 data, size_t, __local long *); +void __ovld vstore8(ulong8 data, size_t, __local ulong *); +void __ovld vstore8(float8 data, size_t, __local float *); +void __ovld vstore16(char16 data, size_t, __local char *); +void __ovld vstore16(uchar16 data, size_t, __local uchar *); +void __ovld vstore16(short16 data, size_t, __local short *); +void __ovld vstore16(ushort16 data, size_t, __local ushort *); +void __ovld vstore16(int16 data, size_t, __local int *); +void __ovld vstore16(uint16 data, size_t, __local uint *); +void __ovld vstore16(long16 data, size_t, __local long *); +void __ovld vstore16(ulong16 data, size_t, __local ulong *); +void __ovld vstore16(float16 data, size_t, __local float *); +void __ovld vstore2(char2 data, size_t, __private char *); +void __ovld vstore2(uchar2 data, size_t, __private uchar *); +void __ovld vstore2(short2 data, size_t, __private short *); +void __ovld vstore2(ushort2 data, size_t, __private ushort *); +void __ovld vstore2(int2 data, size_t, __private int *); +void __ovld vstore2(uint2 data, size_t, __private uint *); +void __ovld vstore2(long2 data, size_t, __private long *); +void __ovld vstore2(ulong2 data, size_t, __private ulong *); +void __ovld vstore2(float2 data, size_t, __private float *); +void __ovld vstore3(char3 data, size_t, __private char *); +void __ovld vstore3(uchar3 data, size_t, __private uchar *); +void __ovld vstore3(short3 data, size_t, __private short *); +void __ovld vstore3(ushort3 data, size_t, __private ushort *); +void __ovld vstore3(int3 data, size_t, __private int *); +void __ovld vstore3(uint3 data, size_t, __private uint *); +void __ovld vstore3(long3 data, size_t, __private long *); +void __ovld vstore3(ulong3 data, size_t, __private ulong *); +void __ovld vstore3(float3 data, size_t, __private float *); +void __ovld vstore4(char4 data, size_t, __private char *); +void __ovld vstore4(uchar4 data, size_t, __private uchar *); +void __ovld vstore4(short4 data, size_t, __private short *); +void __ovld vstore4(ushort4 data, size_t, __private ushort *); +void __ovld vstore4(int4 data, size_t, __private int *); +void __ovld vstore4(uint4 data, size_t, __private uint *); +void __ovld vstore4(long4 data, size_t, __private long *); +void __ovld vstore4(ulong4 data, size_t, __private ulong *); +void __ovld vstore4(float4 data, size_t, __private float *); +void __ovld vstore8(char8 data, size_t, __private char *); +void __ovld vstore8(uchar8 data, size_t, __private uchar *); +void __ovld vstore8(short8 data, size_t, __private short *); +void __ovld vstore8(ushort8 data, size_t, __private ushort *); +void __ovld vstore8(int8 data, size_t, __private int *); +void __ovld vstore8(uint8 data, size_t, __private uint *); +void __ovld vstore8(long8 data, size_t, __private long *); +void __ovld vstore8(ulong8 data, size_t, __private ulong *); +void __ovld vstore8(float8 data, size_t, __private float *); +void __ovld vstore16(char16 data, size_t, __private char *); +void __ovld vstore16(uchar16 data, size_t, __private uchar *); +void __ovld vstore16(short16 data, size_t, __private short *); +void __ovld vstore16(ushort16 data, size_t, __private ushort *); +void __ovld vstore16(int16 data, size_t, __private int *); +void __ovld vstore16(uint16 data, size_t, __private uint *); +void __ovld vstore16(long16 data, size_t, __private long *); +void __ovld vstore16(ulong16 data, size_t, __private ulong *); +void __ovld vstore16(float16 data, size_t, __private float *); #ifdef cl_khr_fp64 -void __ovld vstore2(double2, size_t, __global double *); -void __ovld vstore3(double3, size_t, __global double *); -void __ovld vstore4(double4, size_t, __global double *); -void __ovld vstore8(double8, size_t, __global double *); -void __ovld vstore16(double16, size_t, __global double *); -void __ovld vstore2(double2, size_t, __local double *); -void __ovld vstore3(double3, size_t, __local double *); -void __ovld vstore4(double4, size_t, __local double *); -void __ovld vstore8(double8, size_t, __local double *); -void __ovld vstore16(double16, size_t, __local double *); -void __ovld vstore2(double2, size_t, __private double *); -void __ovld vstore3(double3, size_t, __private double *); -void __ovld vstore4(double4, size_t, __private double *); -void __ovld vstore8(double8, size_t, __private double *); -void __ovld vstore16(double16, size_t, __private double *); +void __ovld vstore2(double2 data, size_t, __global double *); +void __ovld vstore3(double3 data, size_t, __global double *); +void __ovld vstore4(double4 data, size_t, __global double *); +void __ovld vstore8(double8 data, size_t, __global double *); +void __ovld vstore16(double16 data, size_t, __global double *); +void __ovld vstore2(double2 data, size_t, __local double *); +void __ovld vstore3(double3 data, size_t, __local double *); +void __ovld vstore4(double4 data, size_t, __local double *); +void __ovld vstore8(double8 data, size_t, __local double *); +void __ovld vstore16(double16 data, size_t, __local double *); +void __ovld vstore2(double2 data, size_t, __private double *); +void __ovld vstore3(double3 data, size_t, __private double *); +void __ovld vstore4(double4 data, size_t, __private double *); +void __ovld vstore8(double8 data, size_t, __private double *); +void __ovld vstore16(double16 data, size_t, __private double *); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 +void __ovld vstore(half, size_t, __global half *); void __ovld vstore2(half2, size_t, __global half *); void __ovld vstore3(half3, size_t, __global half *); void __ovld vstore4(half4, size_t, __global half *); void __ovld vstore8(half8, size_t, __global half *); void __ovld vstore16(half16, size_t, __global half *); +void __ovld vstore(half, size_t, __local half *); void __ovld vstore2(half2, size_t, __local half *); void __ovld vstore3(half3, size_t, __local half *); void __ovld vstore4(half4, size_t, __local half *); void __ovld vstore8(half8, size_t, __local half *); void __ovld vstore16(half16, size_t, __local half *); +void __ovld vstore(half, size_t, __private half *); void __ovld vstore2(half2, size_t, __private half *); void __ovld vstore3(half3, size_t, __private half *); void __ovld vstore4(half4, size_t, __private half *); void __ovld vstore8(half8, size_t, __private half *); void __ovld vstore16(half16, size_t, __private half *); #endif //cl_khr_fp16 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * Read sizeof (half) bytes of data from address @@ -11727,13 +12451,11 @@ void __ovld vstore16(half16, size_t, __private half *); float __ovld __purefn vload_half(size_t, const __constant half *); #if defined(__opencl_c_generic_address_space) float __ovld __purefn vload_half(size_t, const half *); -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) +#else float __ovld __purefn vload_half(size_t, const __global half *); float __ovld __purefn vload_half(size_t, const __local half *); float __ovld __purefn vload_half(size_t, const __private half *); -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * Read sizeof (halfn) bytes of data from address @@ -11754,9 +12476,7 @@ float3 __ovld __purefn vload_half3(size_t, const half *); float4 __ovld __purefn vload_half4(size_t, const half *); float8 __ovld __purefn vload_half8(size_t, const half *); float16 __ovld __purefn vload_half16(size_t, const half *); -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) +#else float2 __ovld __purefn vload_half2(size_t, const __global half *); float3 __ovld __purefn vload_half3(size_t, const __global half *); float4 __ovld __purefn vload_half4(size_t, const __global half *); @@ -11772,7 +12492,7 @@ float3 __ovld __purefn vload_half3(size_t, const __private half *); float4 __ovld __purefn vload_half4(size_t, const __private half *); float8 __ovld __purefn vload_half8(size_t, const __private half *); float16 __ovld __purefn vload_half16(size_t, const __private half *); -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * The float value given by data is first @@ -11786,54 +12506,52 @@ float16 __ovld __purefn vload_half16(size_t, const __private half *); * nearest even. */ #if defined(__opencl_c_generic_address_space) -void __ovld vstore_half(float, size_t, half *); -void __ovld vstore_half_rte(float, size_t, half *); -void __ovld vstore_half_rtz(float, size_t, half *); -void __ovld vstore_half_rtp(float, size_t, half *); -void __ovld vstore_half_rtn(float, size_t, half *); +void __ovld vstore_half(float data, size_t, half *); +void __ovld vstore_half_rte(float data, size_t, half *); +void __ovld vstore_half_rtz(float data, size_t, half *); +void __ovld vstore_half_rtp(float data, size_t, half *); +void __ovld vstore_half_rtn(float data, size_t, half *); #ifdef cl_khr_fp64 -void __ovld vstore_half(double, size_t, half *); -void __ovld vstore_half_rte(double, size_t, half *); -void __ovld vstore_half_rtz(double, size_t, half *); -void __ovld vstore_half_rtp(double, size_t, half *); -void __ovld vstore_half_rtn(double, size_t, half *); +void __ovld vstore_half(double data, size_t, half *); +void __ovld vstore_half_rte(double data, size_t, half *); +void __ovld vstore_half_rtz(double data, size_t, half *); +void __ovld vstore_half_rtp(double data, size_t, half *); +void __ovld vstore_half_rtn(double data, size_t, half *); #endif //cl_khr_fp64 -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) -void __ovld vstore_half(float, size_t, __global half *); -void __ovld vstore_half_rte(float, size_t, __global half *); -void __ovld vstore_half_rtz(float, size_t, __global half *); -void __ovld vstore_half_rtp(float, size_t, __global half *); -void __ovld vstore_half_rtn(float, size_t, __global half *); -void __ovld vstore_half(float, size_t, __local half *); -void __ovld vstore_half_rte(float, size_t, __local half *); -void __ovld vstore_half_rtz(float, size_t, __local half *); -void __ovld vstore_half_rtp(float, size_t, __local half *); -void __ovld vstore_half_rtn(float, size_t, __local half *); -void __ovld vstore_half(float, size_t, __private half *); -void __ovld vstore_half_rte(float, size_t, __private half *); -void __ovld vstore_half_rtz(float, size_t, __private half *); -void __ovld vstore_half_rtp(float, size_t, __private half *); -void __ovld vstore_half_rtn(float, size_t, __private half *); +#else +void __ovld vstore_half(float data, size_t, __global half *); +void __ovld vstore_half_rte(float data, size_t, __global half *); +void __ovld vstore_half_rtz(float data, size_t, __global half *); +void __ovld vstore_half_rtp(float data, size_t, __global half *); +void __ovld vstore_half_rtn(float data, size_t, __global half *); +void __ovld vstore_half(float data, size_t, __local half *); +void __ovld vstore_half_rte(float data, size_t, __local half *); +void __ovld vstore_half_rtz(float data, size_t, __local half *); +void __ovld vstore_half_rtp(float data, size_t, __local half *); +void __ovld vstore_half_rtn(float data, size_t, __local half *); +void __ovld vstore_half(float data, size_t, __private half *); +void __ovld vstore_half_rte(float data, size_t, __private half *); +void __ovld vstore_half_rtz(float data, size_t, __private half *); +void __ovld vstore_half_rtp(float data, size_t, __private half *); +void __ovld vstore_half_rtn(float data, size_t, __private half *); #ifdef cl_khr_fp64 -void __ovld vstore_half(double, size_t, __global half *); -void __ovld vstore_half_rte(double, size_t, __global half *); -void __ovld vstore_half_rtz(double, size_t, __global half *); -void __ovld vstore_half_rtp(double, size_t, __global half *); -void __ovld vstore_half_rtn(double, size_t, __global half *); -void __ovld vstore_half(double, size_t, __local half *); -void __ovld vstore_half_rte(double, size_t, __local half *); -void __ovld vstore_half_rtz(double, size_t, __local half *); -void __ovld vstore_half_rtp(double, size_t, __local half *); -void __ovld vstore_half_rtn(double, size_t, __local half *); -void __ovld vstore_half(double, size_t, __private half *); -void __ovld vstore_half_rte(double, size_t, __private half *); -void __ovld vstore_half_rtz(double, size_t, __private half *); -void __ovld vstore_half_rtp(double, size_t, __private half *); -void __ovld vstore_half_rtn(double, size_t, __private half *); +void __ovld vstore_half(double data, size_t, __global half *); +void __ovld vstore_half_rte(double data, size_t, __global half *); +void __ovld vstore_half_rtz(double data, size_t, __global half *); +void __ovld vstore_half_rtp(double data, size_t, __global half *); +void __ovld vstore_half_rtn(double data, size_t, __global half *); +void __ovld vstore_half(double data, size_t, __local half *); +void __ovld vstore_half_rte(double data, size_t, __local half *); +void __ovld vstore_half_rtz(double data, size_t, __local half *); +void __ovld vstore_half_rtp(double data, size_t, __local half *); +void __ovld vstore_half_rtn(double data, size_t, __local half *); +void __ovld vstore_half(double data, size_t, __private half *); +void __ovld vstore_half_rte(double data, size_t, __private half *); +void __ovld vstore_half_rtz(double data, size_t, __private half *); +void __ovld vstore_half_rtp(double data, size_t, __private half *); +void __ovld vstore_half_rtn(double data, size_t, __private half *); #endif //cl_khr_fp64 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * The floatn value given by data is converted to @@ -11847,214 +12565,212 @@ void __ovld vstore_half_rtn(double, size_t, __private half *); * nearest even. */ #if defined(__opencl_c_generic_address_space) -void __ovld vstore_half2(float2, size_t, half *); -void __ovld vstore_half3(float3, size_t, half *); -void __ovld vstore_half4(float4, size_t, half *); -void __ovld vstore_half8(float8, size_t, half *); -void __ovld vstore_half16(float16, size_t, half *); -void __ovld vstore_half2_rte(float2, size_t, half *); -void __ovld vstore_half3_rte(float3, size_t, half *); -void __ovld vstore_half4_rte(float4, size_t, half *); -void __ovld vstore_half8_rte(float8, size_t, half *); -void __ovld vstore_half16_rte(float16, size_t, half *); -void __ovld vstore_half2_rtz(float2, size_t, half *); -void __ovld vstore_half3_rtz(float3, size_t, half *); -void __ovld vstore_half4_rtz(float4, size_t, half *); -void __ovld vstore_half8_rtz(float8, size_t, half *); -void __ovld vstore_half16_rtz(float16, size_t, half *); -void __ovld vstore_half2_rtp(float2, size_t, half *); -void __ovld vstore_half3_rtp(float3, size_t, half *); -void __ovld vstore_half4_rtp(float4, size_t, half *); -void __ovld vstore_half8_rtp(float8, size_t, half *); -void __ovld vstore_half16_rtp(float16, size_t, half *); -void __ovld vstore_half2_rtn(float2, size_t, half *); -void __ovld vstore_half3_rtn(float3, size_t, half *); -void __ovld vstore_half4_rtn(float4, size_t, half *); -void __ovld vstore_half8_rtn(float8, size_t, half *); -void __ovld vstore_half16_rtn(float16, size_t, half *); +void __ovld vstore_half2(float2 data, size_t, half *); +void __ovld vstore_half3(float3 data, size_t, half *); +void __ovld vstore_half4(float4 data, size_t, half *); +void __ovld vstore_half8(float8 data, size_t, half *); +void __ovld vstore_half16(float16 data, size_t, half *); +void __ovld vstore_half2_rte(float2 data, size_t, half *); +void __ovld vstore_half3_rte(float3 data, size_t, half *); +void __ovld vstore_half4_rte(float4 data, size_t, half *); +void __ovld vstore_half8_rte(float8 data, size_t, half *); +void __ovld vstore_half16_rte(float16 data, size_t, half *); +void __ovld vstore_half2_rtz(float2 data, size_t, half *); +void __ovld vstore_half3_rtz(float3 data, size_t, half *); +void __ovld vstore_half4_rtz(float4 data, size_t, half *); +void __ovld vstore_half8_rtz(float8 data, size_t, half *); +void __ovld vstore_half16_rtz(float16 data, size_t, half *); +void __ovld vstore_half2_rtp(float2 data, size_t, half *); +void __ovld vstore_half3_rtp(float3 data, size_t, half *); +void __ovld vstore_half4_rtp(float4 data, size_t, half *); +void __ovld vstore_half8_rtp(float8 data, size_t, half *); +void __ovld vstore_half16_rtp(float16 data, size_t, half *); +void __ovld vstore_half2_rtn(float2 data, size_t, half *); +void __ovld vstore_half3_rtn(float3 data, size_t, half *); +void __ovld vstore_half4_rtn(float4 data, size_t, half *); +void __ovld vstore_half8_rtn(float8 data, size_t, half *); +void __ovld vstore_half16_rtn(float16 data, size_t, half *); #ifdef cl_khr_fp64 -void __ovld vstore_half2(double2, size_t, half *); -void __ovld vstore_half3(double3, size_t, half *); -void __ovld vstore_half4(double4, size_t, half *); -void __ovld vstore_half8(double8, size_t, half *); -void __ovld vstore_half16(double16, size_t, half *); -void __ovld vstore_half2_rte(double2, size_t, half *); -void __ovld vstore_half3_rte(double3, size_t, half *); -void __ovld vstore_half4_rte(double4, size_t, half *); -void __ovld vstore_half8_rte(double8, size_t, half *); -void __ovld vstore_half16_rte(double16, size_t, half *); -void __ovld vstore_half2_rtz(double2, size_t, half *); -void __ovld vstore_half3_rtz(double3, size_t, half *); -void __ovld vstore_half4_rtz(double4, size_t, half *); -void __ovld vstore_half8_rtz(double8, size_t, half *); -void __ovld vstore_half16_rtz(double16, size_t, half *); -void __ovld vstore_half2_rtp(double2, size_t, half *); -void __ovld vstore_half3_rtp(double3, size_t, half *); -void __ovld vstore_half4_rtp(double4, size_t, half *); -void __ovld vstore_half8_rtp(double8, size_t, half *); -void __ovld vstore_half16_rtp(double16, size_t, half *); -void __ovld vstore_half2_rtn(double2, size_t, half *); -void __ovld vstore_half3_rtn(double3, size_t, half *); -void __ovld vstore_half4_rtn(double4, size_t, half *); -void __ovld vstore_half8_rtn(double8, size_t, half *); -void __ovld vstore_half16_rtn(double16, size_t, half *); +void __ovld vstore_half2(double2 data, size_t, half *); +void __ovld vstore_half3(double3 data, size_t, half *); +void __ovld vstore_half4(double4 data, size_t, half *); +void __ovld vstore_half8(double8 data, size_t, half *); +void __ovld vstore_half16(double16 data, size_t, half *); +void __ovld vstore_half2_rte(double2 data, size_t, half *); +void __ovld vstore_half3_rte(double3 data, size_t, half *); +void __ovld vstore_half4_rte(double4 data, size_t, half *); +void __ovld vstore_half8_rte(double8 data, size_t, half *); +void __ovld vstore_half16_rte(double16 data, size_t, half *); +void __ovld vstore_half2_rtz(double2 data, size_t, half *); +void __ovld vstore_half3_rtz(double3 data, size_t, half *); +void __ovld vstore_half4_rtz(double4 data, size_t, half *); +void __ovld vstore_half8_rtz(double8 data, size_t, half *); +void __ovld vstore_half16_rtz(double16 data, size_t, half *); +void __ovld vstore_half2_rtp(double2 data, size_t, half *); +void __ovld vstore_half3_rtp(double3 data, size_t, half *); +void __ovld vstore_half4_rtp(double4 data, size_t, half *); +void __ovld vstore_half8_rtp(double8 data, size_t, half *); +void __ovld vstore_half16_rtp(double16 data, size_t, half *); +void __ovld vstore_half2_rtn(double2 data, size_t, half *); +void __ovld vstore_half3_rtn(double3 data, size_t, half *); +void __ovld vstore_half4_rtn(double4 data, size_t, half *); +void __ovld vstore_half8_rtn(double8 data, size_t, half *); +void __ovld vstore_half16_rtn(double16 data, size_t, half *); #endif //cl_khr_fp64 -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) -void __ovld vstore_half2(float2, size_t, __global half *); -void __ovld vstore_half3(float3, size_t, __global half *); -void __ovld vstore_half4(float4, size_t, __global half *); -void __ovld vstore_half8(float8, size_t, __global half *); -void __ovld vstore_half16(float16, size_t, __global half *); -void __ovld vstore_half2_rte(float2, size_t, __global half *); -void __ovld vstore_half3_rte(float3, size_t, __global half *); -void __ovld vstore_half4_rte(float4, size_t, __global half *); -void __ovld vstore_half8_rte(float8, size_t, __global half *); -void __ovld vstore_half16_rte(float16, size_t, __global half *); -void __ovld vstore_half2_rtz(float2, size_t, __global half *); -void __ovld vstore_half3_rtz(float3, size_t, __global half *); -void __ovld vstore_half4_rtz(float4, size_t, __global half *); -void __ovld vstore_half8_rtz(float8, size_t, __global half *); -void __ovld vstore_half16_rtz(float16, size_t, __global half *); -void __ovld vstore_half2_rtp(float2, size_t, __global half *); -void __ovld vstore_half3_rtp(float3, size_t, __global half *); -void __ovld vstore_half4_rtp(float4, size_t, __global half *); -void __ovld vstore_half8_rtp(float8, size_t, __global half *); -void __ovld vstore_half16_rtp(float16, size_t, __global half *); -void __ovld vstore_half2_rtn(float2, size_t, __global half *); -void __ovld vstore_half3_rtn(float3, size_t, __global half *); -void __ovld vstore_half4_rtn(float4, size_t, __global half *); -void __ovld vstore_half8_rtn(float8, size_t, __global half *); -void __ovld vstore_half16_rtn(float16, size_t, __global half *); -void __ovld vstore_half2(float2, size_t, __local half *); -void __ovld vstore_half3(float3, size_t, __local half *); -void __ovld vstore_half4(float4, size_t, __local half *); -void __ovld vstore_half8(float8, size_t, __local half *); -void __ovld vstore_half16(float16, size_t, __local half *); -void __ovld vstore_half2_rte(float2, size_t, __local half *); -void __ovld vstore_half3_rte(float3, size_t, __local half *); -void __ovld vstore_half4_rte(float4, size_t, __local half *); -void __ovld vstore_half8_rte(float8, size_t, __local half *); -void __ovld vstore_half16_rte(float16, size_t, __local half *); -void __ovld vstore_half2_rtz(float2, size_t, __local half *); -void __ovld vstore_half3_rtz(float3, size_t, __local half *); -void __ovld vstore_half4_rtz(float4, size_t, __local half *); -void __ovld vstore_half8_rtz(float8, size_t, __local half *); -void __ovld vstore_half16_rtz(float16, size_t, __local half *); -void __ovld vstore_half2_rtp(float2, size_t, __local half *); -void __ovld vstore_half3_rtp(float3, size_t, __local half *); -void __ovld vstore_half4_rtp(float4, size_t, __local half *); -void __ovld vstore_half8_rtp(float8, size_t, __local half *); -void __ovld vstore_half16_rtp(float16, size_t, __local half *); -void __ovld vstore_half2_rtn(float2, size_t, __local half *); -void __ovld vstore_half3_rtn(float3, size_t, __local half *); -void __ovld vstore_half4_rtn(float4, size_t, __local half *); -void __ovld vstore_half8_rtn(float8, size_t, __local half *); -void __ovld vstore_half16_rtn(float16, size_t, __local half *); -void __ovld vstore_half2(float2, size_t, __private half *); -void __ovld vstore_half3(float3, size_t, __private half *); -void __ovld vstore_half4(float4, size_t, __private half *); -void __ovld vstore_half8(float8, size_t, __private half *); -void __ovld vstore_half16(float16, size_t, __private half *); -void __ovld vstore_half2_rte(float2, size_t, __private half *); -void __ovld vstore_half3_rte(float3, size_t, __private half *); -void __ovld vstore_half4_rte(float4, size_t, __private half *); -void __ovld vstore_half8_rte(float8, size_t, __private half *); -void __ovld vstore_half16_rte(float16, size_t, __private half *); -void __ovld vstore_half2_rtz(float2, size_t, __private half *); -void __ovld vstore_half3_rtz(float3, size_t, __private half *); -void __ovld vstore_half4_rtz(float4, size_t, __private half *); -void __ovld vstore_half8_rtz(float8, size_t, __private half *); -void __ovld vstore_half16_rtz(float16, size_t, __private half *); -void __ovld vstore_half2_rtp(float2, size_t, __private half *); -void __ovld vstore_half3_rtp(float3, size_t, __private half *); -void __ovld vstore_half4_rtp(float4, size_t, __private half *); -void __ovld vstore_half8_rtp(float8, size_t, __private half *); -void __ovld vstore_half16_rtp(float16, size_t, __private half *); -void __ovld vstore_half2_rtn(float2, size_t, __private half *); -void __ovld vstore_half3_rtn(float3, size_t, __private half *); -void __ovld vstore_half4_rtn(float4, size_t, __private half *); -void __ovld vstore_half8_rtn(float8, size_t, __private half *); -void __ovld vstore_half16_rtn(float16, size_t, __private half *); +#else +void __ovld vstore_half2(float2 data, size_t, __global half *); +void __ovld vstore_half3(float3 data, size_t, __global half *); +void __ovld vstore_half4(float4 data, size_t, __global half *); +void __ovld vstore_half8(float8 data, size_t, __global half *); +void __ovld vstore_half16(float16 data, size_t, __global half *); +void __ovld vstore_half2_rte(float2 data, size_t, __global half *); +void __ovld vstore_half3_rte(float3 data, size_t, __global half *); +void __ovld vstore_half4_rte(float4 data, size_t, __global half *); +void __ovld vstore_half8_rte(float8 data, size_t, __global half *); +void __ovld vstore_half16_rte(float16 data, size_t, __global half *); +void __ovld vstore_half2_rtz(float2 data, size_t, __global half *); +void __ovld vstore_half3_rtz(float3 data, size_t, __global half *); +void __ovld vstore_half4_rtz(float4 data, size_t, __global half *); +void __ovld vstore_half8_rtz(float8 data, size_t, __global half *); +void __ovld vstore_half16_rtz(float16 data, size_t, __global half *); +void __ovld vstore_half2_rtp(float2 data, size_t, __global half *); +void __ovld vstore_half3_rtp(float3 data, size_t, __global half *); +void __ovld vstore_half4_rtp(float4 data, size_t, __global half *); +void __ovld vstore_half8_rtp(float8 data, size_t, __global half *); +void __ovld vstore_half16_rtp(float16 data, size_t, __global half *); +void __ovld vstore_half2_rtn(float2 data, size_t, __global half *); +void __ovld vstore_half3_rtn(float3 data, size_t, __global half *); +void __ovld vstore_half4_rtn(float4 data, size_t, __global half *); +void __ovld vstore_half8_rtn(float8 data, size_t, __global half *); +void __ovld vstore_half16_rtn(float16 data, size_t, __global half *); +void __ovld vstore_half2(float2 data, size_t, __local half *); +void __ovld vstore_half3(float3 data, size_t, __local half *); +void __ovld vstore_half4(float4 data, size_t, __local half *); +void __ovld vstore_half8(float8 data, size_t, __local half *); +void __ovld vstore_half16(float16 data, size_t, __local half *); +void __ovld vstore_half2_rte(float2 data, size_t, __local half *); +void __ovld vstore_half3_rte(float3 data, size_t, __local half *); +void __ovld vstore_half4_rte(float4 data, size_t, __local half *); +void __ovld vstore_half8_rte(float8 data, size_t, __local half *); +void __ovld vstore_half16_rte(float16 data, size_t, __local half *); +void __ovld vstore_half2_rtz(float2 data, size_t, __local half *); +void __ovld vstore_half3_rtz(float3 data, size_t, __local half *); +void __ovld vstore_half4_rtz(float4 data, size_t, __local half *); +void __ovld vstore_half8_rtz(float8 data, size_t, __local half *); +void __ovld vstore_half16_rtz(float16 data, size_t, __local half *); +void __ovld vstore_half2_rtp(float2 data, size_t, __local half *); +void __ovld vstore_half3_rtp(float3 data, size_t, __local half *); +void __ovld vstore_half4_rtp(float4 data, size_t, __local half *); +void __ovld vstore_half8_rtp(float8 data, size_t, __local half *); +void __ovld vstore_half16_rtp(float16 data, size_t, __local half *); +void __ovld vstore_half2_rtn(float2 data, size_t, __local half *); +void __ovld vstore_half3_rtn(float3 data, size_t, __local half *); +void __ovld vstore_half4_rtn(float4 data, size_t, __local half *); +void __ovld vstore_half8_rtn(float8 data, size_t, __local half *); +void __ovld vstore_half16_rtn(float16 data, size_t, __local half *); +void __ovld vstore_half2(float2 data, size_t, __private half *); +void __ovld vstore_half3(float3 data, size_t, __private half *); +void __ovld vstore_half4(float4 data, size_t, __private half *); +void __ovld vstore_half8(float8 data, size_t, __private half *); +void __ovld vstore_half16(float16 data, size_t, __private half *); +void __ovld vstore_half2_rte(float2 data, size_t, __private half *); +void __ovld vstore_half3_rte(float3 data, size_t, __private half *); +void __ovld vstore_half4_rte(float4 data, size_t, __private half *); +void __ovld vstore_half8_rte(float8 data, size_t, __private half *); +void __ovld vstore_half16_rte(float16 data, size_t, __private half *); +void __ovld vstore_half2_rtz(float2 data, size_t, __private half *); +void __ovld vstore_half3_rtz(float3 data, size_t, __private half *); +void __ovld vstore_half4_rtz(float4 data, size_t, __private half *); +void __ovld vstore_half8_rtz(float8 data, size_t, __private half *); +void __ovld vstore_half16_rtz(float16 data, size_t, __private half *); +void __ovld vstore_half2_rtp(float2 data, size_t, __private half *); +void __ovld vstore_half3_rtp(float3 data, size_t, __private half *); +void __ovld vstore_half4_rtp(float4 data, size_t, __private half *); +void __ovld vstore_half8_rtp(float8 data, size_t, __private half *); +void __ovld vstore_half16_rtp(float16 data, size_t, __private half *); +void __ovld vstore_half2_rtn(float2 data, size_t, __private half *); +void __ovld vstore_half3_rtn(float3 data, size_t, __private half *); +void __ovld vstore_half4_rtn(float4 data, size_t, __private half *); +void __ovld vstore_half8_rtn(float8 data, size_t, __private half *); +void __ovld vstore_half16_rtn(float16 data, size_t, __private half *); #ifdef cl_khr_fp64 -void __ovld vstore_half2(double2, size_t, __global half *); -void __ovld vstore_half3(double3, size_t, __global half *); -void __ovld vstore_half4(double4, size_t, __global half *); -void __ovld vstore_half8(double8, size_t, __global half *); -void __ovld vstore_half16(double16, size_t, __global half *); -void __ovld vstore_half2_rte(double2, size_t, __global half *); -void __ovld vstore_half3_rte(double3, size_t, __global half *); -void __ovld vstore_half4_rte(double4, size_t, __global half *); -void __ovld vstore_half8_rte(double8, size_t, __global half *); -void __ovld vstore_half16_rte(double16, size_t, __global half *); -void __ovld vstore_half2_rtz(double2, size_t, __global half *); -void __ovld vstore_half3_rtz(double3, size_t, __global half *); -void __ovld vstore_half4_rtz(double4, size_t, __global half *); -void __ovld vstore_half8_rtz(double8, size_t, __global half *); -void __ovld vstore_half16_rtz(double16, size_t, __global half *); -void __ovld vstore_half2_rtp(double2, size_t, __global half *); -void __ovld vstore_half3_rtp(double3, size_t, __global half *); -void __ovld vstore_half4_rtp(double4, size_t, __global half *); -void __ovld vstore_half8_rtp(double8, size_t, __global half *); -void __ovld vstore_half16_rtp(double16, size_t, __global half *); -void __ovld vstore_half2_rtn(double2, size_t, __global half *); -void __ovld vstore_half3_rtn(double3, size_t, __global half *); -void __ovld vstore_half4_rtn(double4, size_t, __global half *); -void __ovld vstore_half8_rtn(double8, size_t, __global half *); -void __ovld vstore_half16_rtn(double16, size_t, __global half *); -void __ovld vstore_half2(double2, size_t, __local half *); -void __ovld vstore_half3(double3, size_t, __local half *); -void __ovld vstore_half4(double4, size_t, __local half *); -void __ovld vstore_half8(double8, size_t, __local half *); -void __ovld vstore_half16(double16, size_t, __local half *); -void __ovld vstore_half2_rte(double2, size_t, __local half *); -void __ovld vstore_half3_rte(double3, size_t, __local half *); -void __ovld vstore_half4_rte(double4, size_t, __local half *); -void __ovld vstore_half8_rte(double8, size_t, __local half *); -void __ovld vstore_half16_rte(double16, size_t, __local half *); -void __ovld vstore_half2_rtz(double2, size_t, __local half *); -void __ovld vstore_half3_rtz(double3, size_t, __local half *); -void __ovld vstore_half4_rtz(double4, size_t, __local half *); -void __ovld vstore_half8_rtz(double8, size_t, __local half *); -void __ovld vstore_half16_rtz(double16, size_t, __local half *); -void __ovld vstore_half2_rtp(double2, size_t, __local half *); -void __ovld vstore_half3_rtp(double3, size_t, __local half *); -void __ovld vstore_half4_rtp(double4, size_t, __local half *); -void __ovld vstore_half8_rtp(double8, size_t, __local half *); -void __ovld vstore_half16_rtp(double16, size_t, __local half *); -void __ovld vstore_half2_rtn(double2, size_t, __local half *); -void __ovld vstore_half3_rtn(double3, size_t, __local half *); -void __ovld vstore_half4_rtn(double4, size_t, __local half *); -void __ovld vstore_half8_rtn(double8, size_t, __local half *); -void __ovld vstore_half16_rtn(double16, size_t, __local half *); -void __ovld vstore_half2(double2, size_t, __private half *); -void __ovld vstore_half3(double3, size_t, __private half *); -void __ovld vstore_half4(double4, size_t, __private half *); -void __ovld vstore_half8(double8, size_t, __private half *); -void __ovld vstore_half16(double16, size_t, __private half *); -void __ovld vstore_half2_rte(double2, size_t, __private half *); -void __ovld vstore_half3_rte(double3, size_t, __private half *); -void __ovld vstore_half4_rte(double4, size_t, __private half *); -void __ovld vstore_half8_rte(double8, size_t, __private half *); -void __ovld vstore_half16_rte(double16, size_t, __private half *); -void __ovld vstore_half2_rtz(double2, size_t, __private half *); -void __ovld vstore_half3_rtz(double3, size_t, __private half *); -void __ovld vstore_half4_rtz(double4, size_t, __private half *); -void __ovld vstore_half8_rtz(double8, size_t, __private half *); -void __ovld vstore_half16_rtz(double16, size_t, __private half *); -void __ovld vstore_half2_rtp(double2, size_t, __private half *); -void __ovld vstore_half3_rtp(double3, size_t, __private half *); -void __ovld vstore_half4_rtp(double4, size_t, __private half *); -void __ovld vstore_half8_rtp(double8, size_t, __private half *); -void __ovld vstore_half16_rtp(double16, size_t, __private half *); -void __ovld vstore_half2_rtn(double2, size_t, __private half *); -void __ovld vstore_half3_rtn(double3, size_t, __private half *); -void __ovld vstore_half4_rtn(double4, size_t, __private half *); -void __ovld vstore_half8_rtn(double8, size_t, __private half *); -void __ovld vstore_half16_rtn(double16, size_t, __private half *); +void __ovld vstore_half2(double2 data, size_t, __global half *); +void __ovld vstore_half3(double3 data, size_t, __global half *); +void __ovld vstore_half4(double4 data, size_t, __global half *); +void __ovld vstore_half8(double8 data, size_t, __global half *); +void __ovld vstore_half16(double16 data, size_t, __global half *); +void __ovld vstore_half2_rte(double2 data, size_t, __global half *); +void __ovld vstore_half3_rte(double3 data, size_t, __global half *); +void __ovld vstore_half4_rte(double4 data, size_t, __global half *); +void __ovld vstore_half8_rte(double8 data, size_t, __global half *); +void __ovld vstore_half16_rte(double16 data, size_t, __global half *); +void __ovld vstore_half2_rtz(double2 data, size_t, __global half *); +void __ovld vstore_half3_rtz(double3 data, size_t, __global half *); +void __ovld vstore_half4_rtz(double4 data, size_t, __global half *); +void __ovld vstore_half8_rtz(double8 data, size_t, __global half *); +void __ovld vstore_half16_rtz(double16 data, size_t, __global half *); +void __ovld vstore_half2_rtp(double2 data, size_t, __global half *); +void __ovld vstore_half3_rtp(double3 data, size_t, __global half *); +void __ovld vstore_half4_rtp(double4 data, size_t, __global half *); +void __ovld vstore_half8_rtp(double8 data, size_t, __global half *); +void __ovld vstore_half16_rtp(double16 data, size_t, __global half *); +void __ovld vstore_half2_rtn(double2 data, size_t, __global half *); +void __ovld vstore_half3_rtn(double3 data, size_t, __global half *); +void __ovld vstore_half4_rtn(double4 data, size_t, __global half *); +void __ovld vstore_half8_rtn(double8 data, size_t, __global half *); +void __ovld vstore_half16_rtn(double16 data, size_t, __global half *); +void __ovld vstore_half2(double2 data, size_t, __local half *); +void __ovld vstore_half3(double3 data, size_t, __local half *); +void __ovld vstore_half4(double4 data, size_t, __local half *); +void __ovld vstore_half8(double8 data, size_t, __local half *); +void __ovld vstore_half16(double16 data, size_t, __local half *); +void __ovld vstore_half2_rte(double2 data, size_t, __local half *); +void __ovld vstore_half3_rte(double3 data, size_t, __local half *); +void __ovld vstore_half4_rte(double4 data, size_t, __local half *); +void __ovld vstore_half8_rte(double8 data, size_t, __local half *); +void __ovld vstore_half16_rte(double16 data, size_t, __local half *); +void __ovld vstore_half2_rtz(double2 data, size_t, __local half *); +void __ovld vstore_half3_rtz(double3 data, size_t, __local half *); +void __ovld vstore_half4_rtz(double4 data, size_t, __local half *); +void __ovld vstore_half8_rtz(double8 data, size_t, __local half *); +void __ovld vstore_half16_rtz(double16 data, size_t, __local half *); +void __ovld vstore_half2_rtp(double2 data, size_t, __local half *); +void __ovld vstore_half3_rtp(double3 data, size_t, __local half *); +void __ovld vstore_half4_rtp(double4 data, size_t, __local half *); +void __ovld vstore_half8_rtp(double8 data, size_t, __local half *); +void __ovld vstore_half16_rtp(double16 data, size_t, __local half *); +void __ovld vstore_half2_rtn(double2 data, size_t, __local half *); +void __ovld vstore_half3_rtn(double3 data, size_t, __local half *); +void __ovld vstore_half4_rtn(double4 data, size_t, __local half *); +void __ovld vstore_half8_rtn(double8 data, size_t, __local half *); +void __ovld vstore_half16_rtn(double16 data, size_t, __local half *); +void __ovld vstore_half2(double2 data, size_t, __private half *); +void __ovld vstore_half3(double3 data, size_t, __private half *); +void __ovld vstore_half4(double4 data, size_t, __private half *); +void __ovld vstore_half8(double8 data, size_t, __private half *); +void __ovld vstore_half16(double16 data, size_t, __private half *); +void __ovld vstore_half2_rte(double2 data, size_t, __private half *); +void __ovld vstore_half3_rte(double3 data, size_t, __private half *); +void __ovld vstore_half4_rte(double4 data, size_t, __private half *); +void __ovld vstore_half8_rte(double8 data, size_t, __private half *); +void __ovld vstore_half16_rte(double16 data, size_t, __private half *); +void __ovld vstore_half2_rtz(double2 data, size_t, __private half *); +void __ovld vstore_half3_rtz(double3 data, size_t, __private half *); +void __ovld vstore_half4_rtz(double4 data, size_t, __private half *); +void __ovld vstore_half8_rtz(double8 data, size_t, __private half *); +void __ovld vstore_half16_rtz(double16 data, size_t, __private half *); +void __ovld vstore_half2_rtp(double2 data, size_t, __private half *); +void __ovld vstore_half3_rtp(double3 data, size_t, __private half *); +void __ovld vstore_half4_rtp(double4 data, size_t, __private half *); +void __ovld vstore_half8_rtp(double8 data, size_t, __private half *); +void __ovld vstore_half16_rtp(double16 data, size_t, __private half *); +void __ovld vstore_half2_rtn(double2 data, size_t, __private half *); +void __ovld vstore_half3_rtn(double3 data, size_t, __private half *); +void __ovld vstore_half4_rtn(double4 data, size_t, __private half *); +void __ovld vstore_half8_rtn(double8 data, size_t, __private half *); +void __ovld vstore_half16_rtn(double16 data, size_t, __private half *); #endif //cl_khr_fp64 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * For n = 1, 2, 4, 8 and 16 read sizeof (halfn) @@ -12069,36 +12785,39 @@ void __ovld vstore_half16_rtn(double16, size_t, __private half *); * The address computed as (p + (offset * 4)) * must be aligned to sizeof (half) * 4 bytes. */ +float __ovld __purefn vloada_half(size_t, const __constant half *); float2 __ovld __purefn vloada_half2(size_t, const __constant half *); float3 __ovld __purefn vloada_half3(size_t, const __constant half *); float4 __ovld __purefn vloada_half4(size_t, const __constant half *); float8 __ovld __purefn vloada_half8(size_t, const __constant half *); float16 __ovld __purefn vloada_half16(size_t, const __constant half *); #if defined(__opencl_c_generic_address_space) +float __ovld __purefn vloada_half(size_t, const half *); float2 __ovld __purefn vloada_half2(size_t, const half *); float3 __ovld __purefn vloada_half3(size_t, const half *); float4 __ovld __purefn vloada_half4(size_t, const half *); float8 __ovld __purefn vloada_half8(size_t, const half *); float16 __ovld __purefn vloada_half16(size_t, const half *); -#endif //defined(__opencl_c_generic_address_space) - -#if defined(__opencl_c_named_address_space_builtins) +#else +float __ovld __purefn vloada_half(size_t, const __global half *); float2 __ovld __purefn vloada_half2(size_t, const __global half *); float3 __ovld __purefn vloada_half3(size_t, const __global half *); float4 __ovld __purefn vloada_half4(size_t, const __global half *); float8 __ovld __purefn vloada_half8(size_t, const __global half *); float16 __ovld __purefn vloada_half16(size_t, const __global half *); +float __ovld __purefn vloada_half(size_t, const __local half *); float2 __ovld __purefn vloada_half2(size_t, const __local half *); float3 __ovld __purefn vloada_half3(size_t, const __local half *); float4 __ovld __purefn vloada_half4(size_t, const __local half *); float8 __ovld __purefn vloada_half8(size_t, const __local half *); float16 __ovld __purefn vloada_half16(size_t, const __local half *); +float __ovld __purefn vloada_half(size_t, const __private half *); float2 __ovld __purefn vloada_half2(size_t, const __private half *); float3 __ovld __purefn vloada_half3(size_t, const __private half *); float4 __ovld __purefn vloada_half4(size_t, const __private half *); float8 __ovld __purefn vloada_half8(size_t, const __private half *); float16 __ovld __purefn vloada_half16(size_t, const __private half *); -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) /** * The floatn value given by data is converted to @@ -12117,252 +12836,291 @@ float16 __ovld __purefn vloada_half16(size_t, const __private half *); * round to nearest even. */ #if defined(__opencl_c_generic_address_space) -void __ovld vstorea_half2(float2, size_t, half *); -void __ovld vstorea_half3(float3, size_t, half *); -void __ovld vstorea_half4(float4, size_t, half *); -void __ovld vstorea_half8(float8, size_t, half *); -void __ovld vstorea_half16(float16, size_t, half *); - -void __ovld vstorea_half2_rte(float2, size_t, half *); -void __ovld vstorea_half3_rte(float3, size_t, half *); -void __ovld vstorea_half4_rte(float4, size_t, half *); -void __ovld vstorea_half8_rte(float8, size_t, half *); -void __ovld vstorea_half16_rte(float16, size_t, half *); - -void __ovld vstorea_half2_rtz(float2, size_t, half *); -void __ovld vstorea_half3_rtz(float3, size_t, half *); -void __ovld vstorea_half4_rtz(float4, size_t, half *); -void __ovld vstorea_half8_rtz(float8, size_t, half *); -void __ovld vstorea_half16_rtz(float16, size_t, half *); - -void __ovld vstorea_half2_rtp(float2, size_t, half *); -void __ovld vstorea_half3_rtp(float3, size_t, half *); -void __ovld vstorea_half4_rtp(float4, size_t, half *); -void __ovld vstorea_half8_rtp(float8, size_t, half *); -void __ovld vstorea_half16_rtp(float16, size_t, half *); - -void __ovld vstorea_half2_rtn(float2, size_t, half *); -void __ovld vstorea_half3_rtn(float3, size_t, half *); -void __ovld vstorea_half4_rtn(float4, size_t, half *); -void __ovld vstorea_half8_rtn(float8, size_t, half *); -void __ovld vstorea_half16_rtn(float16, size_t, half *); +void __ovld vstorea_half(float data, size_t, half *); +void __ovld vstorea_half2(float2 data, size_t, half *); +void __ovld vstorea_half3(float3 data, size_t, half *); +void __ovld vstorea_half4(float4 data, size_t, half *); +void __ovld vstorea_half8(float8 data, size_t, half *); +void __ovld vstorea_half16(float16 data, size_t, half *); + +void __ovld vstorea_half_rte(float data, size_t, half *); +void __ovld vstorea_half2_rte(float2 data, size_t, half *); +void __ovld vstorea_half3_rte(float3 data, size_t, half *); +void __ovld vstorea_half4_rte(float4 data, size_t, half *); +void __ovld vstorea_half8_rte(float8 data, size_t, half *); +void __ovld vstorea_half16_rte(float16 data, size_t, half *); + +void __ovld vstorea_half_rtz(float data, size_t, half *); +void __ovld vstorea_half2_rtz(float2 data, size_t, half *); +void __ovld vstorea_half3_rtz(float3 data, size_t, half *); +void __ovld vstorea_half4_rtz(float4 data, size_t, half *); +void __ovld vstorea_half8_rtz(float8 data, size_t, half *); +void __ovld vstorea_half16_rtz(float16 data, size_t, half *); + +void __ovld vstorea_half_rtp(float data, size_t, half *); +void __ovld vstorea_half2_rtp(float2 data, size_t, half *); +void __ovld vstorea_half3_rtp(float3 data, size_t, half *); +void __ovld vstorea_half4_rtp(float4 data, size_t, half *); +void __ovld vstorea_half8_rtp(float8 data, size_t, half *); +void __ovld vstorea_half16_rtp(float16 data, size_t, half *); + +void __ovld vstorea_half_rtn(float data, size_t, half *); +void __ovld vstorea_half2_rtn(float2 data, size_t, half *); +void __ovld vstorea_half3_rtn(float3 data, size_t, half *); +void __ovld vstorea_half4_rtn(float4 data, size_t, half *); +void __ovld vstorea_half8_rtn(float8 data, size_t, half *); +void __ovld vstorea_half16_rtn(float16 data, size_t, half *); #ifdef cl_khr_fp64 -void __ovld vstorea_half2(double2, size_t, half *); -void __ovld vstorea_half3(double3, size_t, half *); -void __ovld vstorea_half4(double4, size_t, half *); -void __ovld vstorea_half8(double8, size_t, half *); -void __ovld vstorea_half16(double16, size_t, half *); - -void __ovld vstorea_half2_rte(double2, size_t, half *); -void __ovld vstorea_half3_rte(double3, size_t, half *); -void __ovld vstorea_half4_rte(double4, size_t, half *); -void __ovld vstorea_half8_rte(double8, size_t, half *); -void __ovld vstorea_half16_rte(double16, size_t, half *); - -void __ovld vstorea_half2_rtz(double2, size_t, half *); -void __ovld vstorea_half3_rtz(double3, size_t, half *); -void __ovld vstorea_half4_rtz(double4, size_t, half *); -void __ovld vstorea_half8_rtz(double8, size_t, half *); -void __ovld vstorea_half16_rtz(double16, size_t, half *); - -void __ovld vstorea_half2_rtp(double2, size_t, half *); -void __ovld vstorea_half3_rtp(double3, size_t, half *); -void __ovld vstorea_half4_rtp(double4, size_t, half *); -void __ovld vstorea_half8_rtp(double8, size_t, half *); -void __ovld vstorea_half16_rtp(double16, size_t, half *); - -void __ovld vstorea_half2_rtn(double2, size_t, half *); -void __ovld vstorea_half3_rtn(double3, size_t, half *); -void __ovld vstorea_half4_rtn(double4, size_t, half *); -void __ovld vstorea_half8_rtn(double8, size_t, half *); -void __ovld vstorea_half16_rtn(double16, size_t, half *); +void __ovld vstorea_half(double data, size_t, half *); +void __ovld vstorea_half2(double2 data, size_t, half *); +void __ovld vstorea_half3(double3 data, size_t, half *); +void __ovld vstorea_half4(double4 data, size_t, half *); +void __ovld vstorea_half8(double8 data, size_t, half *); +void __ovld vstorea_half16(double16 data, size_t, half *); + +void __ovld vstorea_half_rte(double data, size_t, half *); +void __ovld vstorea_half2_rte(double2 data, size_t, half *); +void __ovld vstorea_half3_rte(double3 data, size_t, half *); +void __ovld vstorea_half4_rte(double4 data, size_t, half *); +void __ovld vstorea_half8_rte(double8 data, size_t, half *); +void __ovld vstorea_half16_rte(double16 data, size_t, half *); + +void __ovld vstorea_half_rtz(double data, size_t, half *); +void __ovld vstorea_half2_rtz(double2 data, size_t, half *); +void __ovld vstorea_half3_rtz(double3 data, size_t, half *); +void __ovld vstorea_half4_rtz(double4 data, size_t, half *); +void __ovld vstorea_half8_rtz(double8 data, size_t, half *); +void __ovld vstorea_half16_rtz(double16 data, size_t, half *); + +void __ovld vstorea_half_rtp(double data, size_t, half *); +void __ovld vstorea_half2_rtp(double2 data, size_t, half *); +void __ovld vstorea_half3_rtp(double3 data, size_t, half *); +void __ovld vstorea_half4_rtp(double4 data, size_t, half *); +void __ovld vstorea_half8_rtp(double8 data, size_t, half *); +void __ovld vstorea_half16_rtp(double16 data, size_t, half *); + +void __ovld vstorea_half_rtn(double data, size_t, half *); +void __ovld vstorea_half2_rtn(double2 data, size_t, half *); +void __ovld vstorea_half3_rtn(double3 data, size_t, half *); +void __ovld vstorea_half4_rtn(double4 data, size_t, half *); +void __ovld vstorea_half8_rtn(double8 data, size_t, half *); +void __ovld vstorea_half16_rtn(double16 data, size_t, half *); #endif //cl_khr_fp64 -#endif //defined(__opencl_c_generic_address_space) -#if defined(__opencl_c_named_address_space_builtins) -void __ovld vstorea_half2(float2, size_t, __global half *); -void __ovld vstorea_half3(float3, size_t, __global half *); -void __ovld vstorea_half4(float4, size_t, __global half *); -void __ovld vstorea_half8(float8, size_t, __global half *); -void __ovld vstorea_half16(float16, size_t, __global half *); - -void __ovld vstorea_half2_rte(float2, size_t, __global half *); -void __ovld vstorea_half3_rte(float3, size_t, __global half *); -void __ovld vstorea_half4_rte(float4, size_t, __global half *); -void __ovld vstorea_half8_rte(float8, size_t, __global half *); -void __ovld vstorea_half16_rte(float16, size_t, __global half *); - -void __ovld vstorea_half2_rtz(float2, size_t, __global half *); -void __ovld vstorea_half3_rtz(float3, size_t, __global half *); -void __ovld vstorea_half4_rtz(float4, size_t, __global half *); -void __ovld vstorea_half8_rtz(float8, size_t, __global half *); -void __ovld vstorea_half16_rtz(float16, size_t, __global half *); - -void __ovld vstorea_half2_rtp(float2, size_t, __global half *); -void __ovld vstorea_half3_rtp(float3, size_t, __global half *); -void __ovld vstorea_half4_rtp(float4, size_t, __global half *); -void __ovld vstorea_half8_rtp(float8, size_t, __global half *); -void __ovld vstorea_half16_rtp(float16, size_t, __global half *); - -void __ovld vstorea_half2_rtn(float2, size_t, __global half *); -void __ovld vstorea_half3_rtn(float3, size_t, __global half *); -void __ovld vstorea_half4_rtn(float4, size_t, __global half *); -void __ovld vstorea_half8_rtn(float8, size_t, __global half *); -void __ovld vstorea_half16_rtn(float16, size_t, __global half *); - -void __ovld vstorea_half2(float2, size_t, __local half *); -void __ovld vstorea_half3(float3, size_t, __local half *); -void __ovld vstorea_half4(float4, size_t, __local half *); -void __ovld vstorea_half8(float8, size_t, __local half *); -void __ovld vstorea_half16(float16, size_t, __local half *); - -void __ovld vstorea_half2_rte(float2, size_t, __local half *); -void __ovld vstorea_half3_rte(float3, size_t, __local half *); -void __ovld vstorea_half4_rte(float4, size_t, __local half *); -void __ovld vstorea_half8_rte(float8, size_t, __local half *); -void __ovld vstorea_half16_rte(float16, size_t, __local half *); - -void __ovld vstorea_half2_rtz(float2, size_t, __local half *); -void __ovld vstorea_half3_rtz(float3, size_t, __local half *); -void __ovld vstorea_half4_rtz(float4, size_t, __local half *); -void __ovld vstorea_half8_rtz(float8, size_t, __local half *); -void __ovld vstorea_half16_rtz(float16, size_t, __local half *); - -void __ovld vstorea_half2_rtp(float2, size_t, __local half *); -void __ovld vstorea_half3_rtp(float3, size_t, __local half *); -void __ovld vstorea_half4_rtp(float4, size_t, __local half *); -void __ovld vstorea_half8_rtp(float8, size_t, __local half *); -void __ovld vstorea_half16_rtp(float16, size_t, __local half *); - -void __ovld vstorea_half2_rtn(float2, size_t, __local half *); -void __ovld vstorea_half3_rtn(float3, size_t, __local half *); -void __ovld vstorea_half4_rtn(float4, size_t, __local half *); -void __ovld vstorea_half8_rtn(float8, size_t, __local half *); -void __ovld vstorea_half16_rtn(float16, size_t, __local half *); - -void __ovld vstorea_half2(float2, size_t, __private half *); -void __ovld vstorea_half3(float3, size_t, __private half *); -void __ovld vstorea_half4(float4, size_t, __private half *); -void __ovld vstorea_half8(float8, size_t, __private half *); -void __ovld vstorea_half16(float16, size_t, __private half *); - -void __ovld vstorea_half2_rte(float2, size_t, __private half *); -void __ovld vstorea_half3_rte(float3, size_t, __private half *); -void __ovld vstorea_half4_rte(float4, size_t, __private half *); -void __ovld vstorea_half8_rte(float8, size_t, __private half *); -void __ovld vstorea_half16_rte(float16, size_t, __private half *); - -void __ovld vstorea_half2_rtz(float2, size_t, __private half *); -void __ovld vstorea_half3_rtz(float3, size_t, __private half *); -void __ovld vstorea_half4_rtz(float4, size_t, __private half *); -void __ovld vstorea_half8_rtz(float8, size_t, __private half *); -void __ovld vstorea_half16_rtz(float16, size_t, __private half *); - -void __ovld vstorea_half2_rtp(float2, size_t, __private half *); -void __ovld vstorea_half3_rtp(float3, size_t, __private half *); -void __ovld vstorea_half4_rtp(float4, size_t, __private half *); -void __ovld vstorea_half8_rtp(float8, size_t, __private half *); -void __ovld vstorea_half16_rtp(float16, size_t, __private half *); - -void __ovld vstorea_half2_rtn(float2, size_t, __private half *); -void __ovld vstorea_half3_rtn(float3, size_t, __private half *); -void __ovld vstorea_half4_rtn(float4, size_t, __private half *); -void __ovld vstorea_half8_rtn(float8, size_t, __private half *); -void __ovld vstorea_half16_rtn(float16, size_t, __private half *); +#else +void __ovld vstorea_half(float data, size_t, __global half *); +void __ovld vstorea_half2(float2 data, size_t, __global half *); +void __ovld vstorea_half3(float3 data, size_t, __global half *); +void __ovld vstorea_half4(float4 data, size_t, __global half *); +void __ovld vstorea_half8(float8 data, size_t, __global half *); +void __ovld vstorea_half16(float16 data, size_t, __global half *); + +void __ovld vstorea_half_rte(float data, size_t, __global half *); +void __ovld vstorea_half2_rte(float2 data, size_t, __global half *); +void __ovld vstorea_half3_rte(float3 data, size_t, __global half *); +void __ovld vstorea_half4_rte(float4 data, size_t, __global half *); +void __ovld vstorea_half8_rte(float8 data, size_t, __global half *); +void __ovld vstorea_half16_rte(float16 data, size_t, __global half *); + +void __ovld vstorea_half_rtz(float data, size_t, __global half *); +void __ovld vstorea_half2_rtz(float2 data, size_t, __global half *); +void __ovld vstorea_half3_rtz(float3 data, size_t, __global half *); +void __ovld vstorea_half4_rtz(float4 data, size_t, __global half *); +void __ovld vstorea_half8_rtz(float8 data, size_t, __global half *); +void __ovld vstorea_half16_rtz(float16 data, size_t, __global half *); + +void __ovld vstorea_half_rtp(float data, size_t, __global half *); +void __ovld vstorea_half2_rtp(float2 data, size_t, __global half *); +void __ovld vstorea_half3_rtp(float3 data, size_t, __global half *); +void __ovld vstorea_half4_rtp(float4 data, size_t, __global half *); +void __ovld vstorea_half8_rtp(float8 data, size_t, __global half *); +void __ovld vstorea_half16_rtp(float16 data, size_t, __global half *); + +void __ovld vstorea_half_rtn(float data, size_t, __global half *); +void __ovld vstorea_half2_rtn(float2 data, size_t, __global half *); +void __ovld vstorea_half3_rtn(float3 data, size_t, __global half *); +void __ovld vstorea_half4_rtn(float4 data, size_t, __global half *); +void __ovld vstorea_half8_rtn(float8 data, size_t, __global half *); +void __ovld vstorea_half16_rtn(float16 data, size_t, __global half *); + +void __ovld vstorea_half(float data, size_t, __local half *); +void __ovld vstorea_half2(float2 data, size_t, __local half *); +void __ovld vstorea_half3(float3 data, size_t, __local half *); +void __ovld vstorea_half4(float4 data, size_t, __local half *); +void __ovld vstorea_half8(float8 data, size_t, __local half *); +void __ovld vstorea_half16(float16 data, size_t, __local half *); + +void __ovld vstorea_half_rte(float data, size_t, __local half *); +void __ovld vstorea_half2_rte(float2 data, size_t, __local half *); +void __ovld vstorea_half3_rte(float3 data, size_t, __local half *); +void __ovld vstorea_half4_rte(float4 data, size_t, __local half *); +void __ovld vstorea_half8_rte(float8 data, size_t, __local half *); +void __ovld vstorea_half16_rte(float16 data, size_t, __local half *); + +void __ovld vstorea_half_rtz(float data, size_t, __local half *); +void __ovld vstorea_half2_rtz(float2 data, size_t, __local half *); +void __ovld vstorea_half3_rtz(float3 data, size_t, __local half *); +void __ovld vstorea_half4_rtz(float4 data, size_t, __local half *); +void __ovld vstorea_half8_rtz(float8 data, size_t, __local half *); +void __ovld vstorea_half16_rtz(float16 data, size_t, __local half *); + +void __ovld vstorea_half_rtp(float data, size_t, __local half *); +void __ovld vstorea_half2_rtp(float2 data, size_t, __local half *); +void __ovld vstorea_half3_rtp(float3 data, size_t, __local half *); +void __ovld vstorea_half4_rtp(float4 data, size_t, __local half *); +void __ovld vstorea_half8_rtp(float8 data, size_t, __local half *); +void __ovld vstorea_half16_rtp(float16 data, size_t, __local half *); + +void __ovld vstorea_half_rtn(float data, size_t, __local half *); +void __ovld vstorea_half2_rtn(float2 data, size_t, __local half *); +void __ovld vstorea_half3_rtn(float3 data, size_t, __local half *); +void __ovld vstorea_half4_rtn(float4 data, size_t, __local half *); +void __ovld vstorea_half8_rtn(float8 data, size_t, __local half *); +void __ovld vstorea_half16_rtn(float16 data, size_t, __local half *); + +void __ovld vstorea_half(float data, size_t, __private half *); +void __ovld vstorea_half2(float2 data, size_t, __private half *); +void __ovld vstorea_half3(float3 data, size_t, __private half *); +void __ovld vstorea_half4(float4 data, size_t, __private half *); +void __ovld vstorea_half8(float8 data, size_t, __private half *); +void __ovld vstorea_half16(float16 data, size_t, __private half *); + +void __ovld vstorea_half_rte(float data, size_t, __private half *); +void __ovld vstorea_half2_rte(float2 data, size_t, __private half *); +void __ovld vstorea_half3_rte(float3 data, size_t, __private half *); +void __ovld vstorea_half4_rte(float4 data, size_t, __private half *); +void __ovld vstorea_half8_rte(float8 data, size_t, __private half *); +void __ovld vstorea_half16_rte(float16 data, size_t, __private half *); + +void __ovld vstorea_half_rtz(float data, size_t, __private half *); +void __ovld vstorea_half2_rtz(float2 data, size_t, __private half *); +void __ovld vstorea_half3_rtz(float3 data, size_t, __private half *); +void __ovld vstorea_half4_rtz(float4 data, size_t, __private half *); +void __ovld vstorea_half8_rtz(float8 data, size_t, __private half *); +void __ovld vstorea_half16_rtz(float16 data, size_t, __private half *); + +void __ovld vstorea_half_rtp(float data, size_t, __private half *); +void __ovld vstorea_half2_rtp(float2 data, size_t, __private half *); +void __ovld vstorea_half3_rtp(float3 data, size_t, __private half *); +void __ovld vstorea_half4_rtp(float4 data, size_t, __private half *); +void __ovld vstorea_half8_rtp(float8 data, size_t, __private half *); +void __ovld vstorea_half16_rtp(float16 data, size_t, __private half *); + +void __ovld vstorea_half_rtn(float data, size_t, __private half *); +void __ovld vstorea_half2_rtn(float2 data, size_t, __private half *); +void __ovld vstorea_half3_rtn(float3 data, size_t, __private half *); +void __ovld vstorea_half4_rtn(float4 data, size_t, __private half *); +void __ovld vstorea_half8_rtn(float8 data, size_t, __private half *); +void __ovld vstorea_half16_rtn(float16 data, size_t, __private half *); #ifdef cl_khr_fp64 -void __ovld vstorea_half2(double2, size_t, __global half *); -void __ovld vstorea_half3(double3, size_t, __global half *); -void __ovld vstorea_half4(double4, size_t, __global half *); -void __ovld vstorea_half8(double8, size_t, __global half *); -void __ovld vstorea_half16(double16, size_t, __global half *); - -void __ovld vstorea_half2_rte(double2, size_t, __global half *); -void __ovld vstorea_half3_rte(double3, size_t, __global half *); -void __ovld vstorea_half4_rte(double4, size_t, __global half *); -void __ovld vstorea_half8_rte(double8, size_t, __global half *); -void __ovld vstorea_half16_rte(double16, size_t, __global half *); - -void __ovld vstorea_half2_rtz(double2, size_t, __global half *); -void __ovld vstorea_half3_rtz(double3, size_t, __global half *); -void __ovld vstorea_half4_rtz(double4, size_t, __global half *); -void __ovld vstorea_half8_rtz(double8, size_t, __global half *); -void __ovld vstorea_half16_rtz(double16, size_t, __global half *); - -void __ovld vstorea_half2_rtp(double2, size_t, __global half *); -void __ovld vstorea_half3_rtp(double3, size_t, __global half *); -void __ovld vstorea_half4_rtp(double4, size_t, __global half *); -void __ovld vstorea_half8_rtp(double8, size_t, __global half *); -void __ovld vstorea_half16_rtp(double16, size_t, __global half *); - -void __ovld vstorea_half2_rtn(double2, size_t, __global half *); -void __ovld vstorea_half3_rtn(double3, size_t, __global half *); -void __ovld vstorea_half4_rtn(double4, size_t, __global half *); -void __ovld vstorea_half8_rtn(double8, size_t, __global half *); -void __ovld vstorea_half16_rtn(double16, size_t, __global half *); - -void __ovld vstorea_half2(double2, size_t, __local half *); -void __ovld vstorea_half3(double3, size_t, __local half *); -void __ovld vstorea_half4(double4, size_t, __local half *); -void __ovld vstorea_half8(double8, size_t, __local half *); -void __ovld vstorea_half16(double16, size_t, __local half *); - -void __ovld vstorea_half2_rte(double2, size_t, __local half *); -void __ovld vstorea_half3_rte(double3, size_t, __local half *); -void __ovld vstorea_half4_rte(double4, size_t, __local half *); -void __ovld vstorea_half8_rte(double8, size_t, __local half *); -void __ovld vstorea_half16_rte(double16, size_t, __local half *); - -void __ovld vstorea_half2_rtz(double2, size_t, __local half *); -void __ovld vstorea_half3_rtz(double3, size_t, __local half *); -void __ovld vstorea_half4_rtz(double4, size_t, __local half *); -void __ovld vstorea_half8_rtz(double8, size_t, __local half *); -void __ovld vstorea_half16_rtz(double16, size_t, __local half *); - -void __ovld vstorea_half2_rtp(double2, size_t, __local half *); -void __ovld vstorea_half3_rtp(double3, size_t, __local half *); -void __ovld vstorea_half4_rtp(double4, size_t, __local half *); -void __ovld vstorea_half8_rtp(double8, size_t, __local half *); -void __ovld vstorea_half16_rtp(double16, size_t, __local half *); - -void __ovld vstorea_half2_rtn(double2, size_t, __local half *); -void __ovld vstorea_half3_rtn(double3, size_t, __local half *); -void __ovld vstorea_half4_rtn(double4, size_t, __local half *); -void __ovld vstorea_half8_rtn(double8, size_t, __local half *); -void __ovld vstorea_half16_rtn(double16, size_t, __local half *); - -void __ovld vstorea_half2(double2, size_t, __private half *); -void __ovld vstorea_half3(double3, size_t, __private half *); -void __ovld vstorea_half4(double4, size_t, __private half *); -void __ovld vstorea_half8(double8, size_t, __private half *); -void __ovld vstorea_half16(double16, size_t, __private half *); - -void __ovld vstorea_half2_rte(double2, size_t, __private half *); -void __ovld vstorea_half3_rte(double3, size_t, __private half *); -void __ovld vstorea_half4_rte(double4, size_t, __private half *); -void __ovld vstorea_half8_rte(double8, size_t, __private half *); -void __ovld vstorea_half16_rte(double16, size_t, __private half *); - -void __ovld vstorea_half2_rtz(double2, size_t, __private half *); -void __ovld vstorea_half3_rtz(double3, size_t, __private half *); -void __ovld vstorea_half4_rtz(double4, size_t, __private half *); -void __ovld vstorea_half8_rtz(double8, size_t, __private half *); -void __ovld vstorea_half16_rtz(double16, size_t, __private half *); - -void __ovld vstorea_half2_rtp(double2, size_t, __private half *); -void __ovld vstorea_half3_rtp(double3, size_t, __private half *); -void __ovld vstorea_half4_rtp(double4, size_t, __private half *); -void __ovld vstorea_half8_rtp(double8, size_t, __private half *); -void __ovld vstorea_half16_rtp(double16, size_t, __private half *); - -void __ovld vstorea_half2_rtn(double2, size_t, __private half *); -void __ovld vstorea_half3_rtn(double3, size_t, __private half *); -void __ovld vstorea_half4_rtn(double4, size_t, __private half *); -void __ovld vstorea_half8_rtn(double8, size_t, __private half *); -void __ovld vstorea_half16_rtn(double16, size_t, __private half *); +void __ovld vstorea_half(double data, size_t, __global half *); +void __ovld vstorea_half2(double2 data, size_t, __global half *); +void __ovld vstorea_half3(double3 data, size_t, __global half *); +void __ovld vstorea_half4(double4 data, size_t, __global half *); +void __ovld vstorea_half8(double8 data, size_t, __global half *); +void __ovld vstorea_half16(double16 data, size_t, __global half *); + +void __ovld vstorea_half_rte(double data, size_t, __global half *); +void __ovld vstorea_half2_rte(double2 data, size_t, __global half *); +void __ovld vstorea_half3_rte(double3 data, size_t, __global half *); +void __ovld vstorea_half4_rte(double4 data, size_t, __global half *); +void __ovld vstorea_half8_rte(double8 data, size_t, __global half *); +void __ovld vstorea_half16_rte(double16 data, size_t, __global half *); + +void __ovld vstorea_half_rtz(double data, size_t, __global half *); +void __ovld vstorea_half2_rtz(double2 data, size_t, __global half *); +void __ovld vstorea_half3_rtz(double3 data, size_t, __global half *); +void __ovld vstorea_half4_rtz(double4 data, size_t, __global half *); +void __ovld vstorea_half8_rtz(double8 data, size_t, __global half *); +void __ovld vstorea_half16_rtz(double16 data, size_t, __global half *); + +void __ovld vstorea_half_rtp(double data, size_t, __global half *); +void __ovld vstorea_half2_rtp(double2 data, size_t, __global half *); +void __ovld vstorea_half3_rtp(double3 data, size_t, __global half *); +void __ovld vstorea_half4_rtp(double4 data, size_t, __global half *); +void __ovld vstorea_half8_rtp(double8 data, size_t, __global half *); +void __ovld vstorea_half16_rtp(double16 data, size_t, __global half *); + +void __ovld vstorea_half_rtn(double data, size_t, __global half *); +void __ovld vstorea_half2_rtn(double2 data, size_t, __global half *); +void __ovld vstorea_half3_rtn(double3 data, size_t, __global half *); +void __ovld vstorea_half4_rtn(double4 data, size_t, __global half *); +void __ovld vstorea_half8_rtn(double8 data, size_t, __global half *); +void __ovld vstorea_half16_rtn(double16 data, size_t, __global half *); + +void __ovld vstorea_half(double data, size_t, __local half *); +void __ovld vstorea_half2(double2 data, size_t, __local half *); +void __ovld vstorea_half3(double3 data, size_t, __local half *); +void __ovld vstorea_half4(double4 data, size_t, __local half *); +void __ovld vstorea_half8(double8 data, size_t, __local half *); +void __ovld vstorea_half16(double16 data, size_t, __local half *); + +void __ovld vstorea_half_rte(double data, size_t, __local half *); +void __ovld vstorea_half2_rte(double2 data, size_t, __local half *); +void __ovld vstorea_half3_rte(double3 data, size_t, __local half *); +void __ovld vstorea_half4_rte(double4 data, size_t, __local half *); +void __ovld vstorea_half8_rte(double8 data, size_t, __local half *); +void __ovld vstorea_half16_rte(double16 data, size_t, __local half *); + +void __ovld vstorea_half_rtz(double data, size_t, __local half *); +void __ovld vstorea_half2_rtz(double2 data, size_t, __local half *); +void __ovld vstorea_half3_rtz(double3 data, size_t, __local half *); +void __ovld vstorea_half4_rtz(double4 data, size_t, __local half *); +void __ovld vstorea_half8_rtz(double8 data, size_t, __local half *); +void __ovld vstorea_half16_rtz(double16 data, size_t, __local half *); + +void __ovld vstorea_half_rtp(double data, size_t, __local half *); +void __ovld vstorea_half2_rtp(double2 data, size_t, __local half *); +void __ovld vstorea_half3_rtp(double3 data, size_t, __local half *); +void __ovld vstorea_half4_rtp(double4 data, size_t, __local half *); +void __ovld vstorea_half8_rtp(double8 data, size_t, __local half *); +void __ovld vstorea_half16_rtp(double16 data, size_t, __local half *); + +void __ovld vstorea_half_rtn(double data, size_t, __local half *); +void __ovld vstorea_half2_rtn(double2 data, size_t, __local half *); +void __ovld vstorea_half3_rtn(double3 data, size_t, __local half *); +void __ovld vstorea_half4_rtn(double4 data, size_t, __local half *); +void __ovld vstorea_half8_rtn(double8 data, size_t, __local half *); +void __ovld vstorea_half16_rtn(double16 data, size_t, __local half *); + +void __ovld vstorea_half(double data, size_t, __private half *); +void __ovld vstorea_half2(double2 data, size_t, __private half *); +void __ovld vstorea_half3(double3 data, size_t, __private half *); +void __ovld vstorea_half4(double4 data, size_t, __private half *); +void __ovld vstorea_half8(double8 data, size_t, __private half *); +void __ovld vstorea_half16(double16 data, size_t, __private half *); + +void __ovld vstorea_half_rte(double data, size_t, __private half *); +void __ovld vstorea_half2_rte(double2 data, size_t, __private half *); +void __ovld vstorea_half3_rte(double3 data, size_t, __private half *); +void __ovld vstorea_half4_rte(double4 data, size_t, __private half *); +void __ovld vstorea_half8_rte(double8 data, size_t, __private half *); +void __ovld vstorea_half16_rte(double16 data, size_t, __private half *); + +void __ovld vstorea_half_rtz(double data, size_t, __private half *); +void __ovld vstorea_half2_rtz(double2 data, size_t, __private half *); +void __ovld vstorea_half3_rtz(double3 data, size_t, __private half *); +void __ovld vstorea_half4_rtz(double4 data, size_t, __private half *); +void __ovld vstorea_half8_rtz(double8 data, size_t, __private half *); +void __ovld vstorea_half16_rtz(double16 data, size_t, __private half *); + +void __ovld vstorea_half_rtp(double data, size_t, __private half *); +void __ovld vstorea_half2_rtp(double2 data, size_t, __private half *); +void __ovld vstorea_half3_rtp(double3 data, size_t, __private half *); +void __ovld vstorea_half4_rtp(double4 data, size_t, __private half *); +void __ovld vstorea_half8_rtp(double8 data, size_t, __private half *); +void __ovld vstorea_half16_rtp(double16 data, size_t, __private half *); + +void __ovld vstorea_half_rtn(double data, size_t, __private half *); +void __ovld vstorea_half2_rtn(double2 data,size_t, __private half *); +void __ovld vstorea_half3_rtn(double3 data,size_t, __private half *); +void __ovld vstorea_half4_rtn(double4 data,size_t, __private half *); +void __ovld vstorea_half8_rtn(double8 data,size_t, __private half *); +void __ovld vstorea_half16_rtn(double16 data,size_t, __private half *); #endif //cl_khr_fp64 -#endif //defined(__opencl_c_named_address_space_builtins) +#endif //defined(__opencl_c_generic_address_space) // OpenCL v1.1 s6.11.8, v1.2 s6.12.8, v2.0 s6.13.8 - Synchronization Functions @@ -15544,7 +16302,7 @@ half4 __ovld __purefn read_imageh(read_write image1d_buffer_t, int); * The behavior of write_imagef, write_imagei and * write_imageui for image objects created with * image_channel_data_type values not specified in - * the description above or with (x, y) coordinate + * the description above or with (x, ) coordinate * values that are not in the range (0 ... image width -1, * 0 ... image height - 1), respectively, is undefined. */ @@ -16153,97 +16911,97 @@ int __ovld __conv work_group_all(int predicate); int __ovld __conv work_group_any(int predicate); #ifdef cl_khr_fp16 -half __ovld __conv work_group_broadcast(half, size_t local_id); -half __ovld __conv work_group_broadcast(half, size_t, size_t); -half __ovld __conv work_group_broadcast(half, size_t, size_t, size_t); +half __ovld __conv work_group_broadcast(half , size_t); +half __ovld __conv work_group_broadcast(half , size_t, size_t ); +half __ovld __conv work_group_broadcast(half , size_t, size_t, size_t ); #endif -int __ovld __conv work_group_broadcast(int, size_t local_id); -int __ovld __conv work_group_broadcast(int, size_t, size_t); -int __ovld __conv work_group_broadcast(int, size_t, size_t, size_t); -uint __ovld __conv work_group_broadcast(uint, size_t local_id); -uint __ovld __conv work_group_broadcast(uint, size_t, size_t); -uint __ovld __conv work_group_broadcast(uint, size_t, size_t, size_t); -long __ovld __conv work_group_broadcast(long, size_t local_id); -long __ovld __conv work_group_broadcast(long, size_t, size_t); -long __ovld __conv work_group_broadcast(long, size_t, size_t, size_t); -ulong __ovld __conv work_group_broadcast(ulong, size_t local_id); -ulong __ovld __conv work_group_broadcast(ulong, size_t, size_t); -ulong __ovld __conv work_group_broadcast(ulong, size_t, size_t, size_t); -float __ovld __conv work_group_broadcast(float, size_t local_id); -float __ovld __conv work_group_broadcast(float, size_t, size_t); -float __ovld __conv work_group_broadcast(float, size_t, size_t, size_t); +int __ovld __conv work_group_broadcast(int , size_t); +int __ovld __conv work_group_broadcast(int , size_t, size_t ); +int __ovld __conv work_group_broadcast(int , size_t, size_t, size_t ); +uint __ovld __conv work_group_broadcast(uint , size_t); +uint __ovld __conv work_group_broadcast(uint , size_t, size_t ); +uint __ovld __conv work_group_broadcast(uint , size_t, size_t, size_t ); +long __ovld __conv work_group_broadcast(long , size_t); +long __ovld __conv work_group_broadcast(long , size_t, size_t ); +long __ovld __conv work_group_broadcast(long , size_t, size_t, size_t ); +ulong __ovld __conv work_group_broadcast(ulong , size_t); +ulong __ovld __conv work_group_broadcast(ulong , size_t, size_t ); +ulong __ovld __conv work_group_broadcast(ulong , size_t, size_t, size_t ); +float __ovld __conv work_group_broadcast(float , size_t); +float __ovld __conv work_group_broadcast(float , size_t, size_t ); +float __ovld __conv work_group_broadcast(float , size_t, size_t, size_t ); #ifdef cl_khr_fp64 -double __ovld __conv work_group_broadcast(double, size_t local_id); -double __ovld __conv work_group_broadcast(double, size_t, size_t); -double __ovld __conv work_group_broadcast(double, size_t, size_t, size_t); +double __ovld __conv work_group_broadcast(double , size_t); +double __ovld __conv work_group_broadcast(double , size_t, size_t ); +double __ovld __conv work_group_broadcast(double , size_t, size_t, size_t ); #endif //cl_khr_fp64 #ifdef cl_khr_fp16 -half __ovld __conv work_group_reduce_add(half); -half __ovld __conv work_group_reduce_min(half); -half __ovld __conv work_group_reduce_max(half); -half __ovld __conv work_group_scan_exclusive_add(half); -half __ovld __conv work_group_scan_exclusive_min(half); -half __ovld __conv work_group_scan_exclusive_max(half); -half __ovld __conv work_group_scan_inclusive_add(half); -half __ovld __conv work_group_scan_inclusive_min(half); -half __ovld __conv work_group_scan_inclusive_max(half); +half __ovld __conv work_group_reduce_add(half x); +half __ovld __conv work_group_reduce_min(half x); +half __ovld __conv work_group_reduce_max(half x); +half __ovld __conv work_group_scan_exclusive_add(half x); +half __ovld __conv work_group_scan_exclusive_min(half x); +half __ovld __conv work_group_scan_exclusive_max(half x); +half __ovld __conv work_group_scan_inclusive_add(half x); +half __ovld __conv work_group_scan_inclusive_min(half x); +half __ovld __conv work_group_scan_inclusive_max(half x); #endif -int __ovld __conv work_group_reduce_add(int); -int __ovld __conv work_group_reduce_min(int); -int __ovld __conv work_group_reduce_max(int); -int __ovld __conv work_group_scan_exclusive_add(int); -int __ovld __conv work_group_scan_exclusive_min(int); -int __ovld __conv work_group_scan_exclusive_max(int); -int __ovld __conv work_group_scan_inclusive_add(int); -int __ovld __conv work_group_scan_inclusive_min(int); -int __ovld __conv work_group_scan_inclusive_max(int); -uint __ovld __conv work_group_reduce_add(uint); -uint __ovld __conv work_group_reduce_min(uint); -uint __ovld __conv work_group_reduce_max(uint); -uint __ovld __conv work_group_scan_exclusive_add(uint); -uint __ovld __conv work_group_scan_exclusive_min(uint); -uint __ovld __conv work_group_scan_exclusive_max(uint); -uint __ovld __conv work_group_scan_inclusive_add(uint); -uint __ovld __conv work_group_scan_inclusive_min(uint); -uint __ovld __conv work_group_scan_inclusive_max(uint); -long __ovld __conv work_group_reduce_add(long); -long __ovld __conv work_group_reduce_min(long); -long __ovld __conv work_group_reduce_max(long); -long __ovld __conv work_group_scan_exclusive_add(long); -long __ovld __conv work_group_scan_exclusive_min(long); -long __ovld __conv work_group_scan_exclusive_max(long); -long __ovld __conv work_group_scan_inclusive_add(long); -long __ovld __conv work_group_scan_inclusive_min(long); -long __ovld __conv work_group_scan_inclusive_max(long); -ulong __ovld __conv work_group_reduce_add(ulong); -ulong __ovld __conv work_group_reduce_min(ulong); -ulong __ovld __conv work_group_reduce_max(ulong); -ulong __ovld __conv work_group_scan_exclusive_add(ulong); -ulong __ovld __conv work_group_scan_exclusive_min(ulong); -ulong __ovld __conv work_group_scan_exclusive_max(ulong); -ulong __ovld __conv work_group_scan_inclusive_add(ulong); -ulong __ovld __conv work_group_scan_inclusive_min(ulong); -ulong __ovld __conv work_group_scan_inclusive_max(ulong); -float __ovld __conv work_group_reduce_add(float); -float __ovld __conv work_group_reduce_min(float); -float __ovld __conv work_group_reduce_max(float); -float __ovld __conv work_group_scan_exclusive_add(float); -float __ovld __conv work_group_scan_exclusive_min(float); -float __ovld __conv work_group_scan_exclusive_max(float); -float __ovld __conv work_group_scan_inclusive_add(float); -float __ovld __conv work_group_scan_inclusive_min(float); -float __ovld __conv work_group_scan_inclusive_max(float); +int __ovld __conv work_group_reduce_add(int x); +int __ovld __conv work_group_reduce_min(int x); +int __ovld __conv work_group_reduce_max(int x); +int __ovld __conv work_group_scan_exclusive_add(int x); +int __ovld __conv work_group_scan_exclusive_min(int x); +int __ovld __conv work_group_scan_exclusive_max(int x); +int __ovld __conv work_group_scan_inclusive_add(int x); +int __ovld __conv work_group_scan_inclusive_min(int x); +int __ovld __conv work_group_scan_inclusive_max(int x); +uint __ovld __conv work_group_reduce_add(uint x); +uint __ovld __conv work_group_reduce_min(uint x); +uint __ovld __conv work_group_reduce_max(uint x); +uint __ovld __conv work_group_scan_exclusive_add(uint x); +uint __ovld __conv work_group_scan_exclusive_min(uint x); +uint __ovld __conv work_group_scan_exclusive_max(uint x); +uint __ovld __conv work_group_scan_inclusive_add(uint x); +uint __ovld __conv work_group_scan_inclusive_min(uint x); +uint __ovld __conv work_group_scan_inclusive_max(uint x); +long __ovld __conv work_group_reduce_add(long x); +long __ovld __conv work_group_reduce_min(long x); +long __ovld __conv work_group_reduce_max(long x); +long __ovld __conv work_group_scan_exclusive_add(long x); +long __ovld __conv work_group_scan_exclusive_min(long x); +long __ovld __conv work_group_scan_exclusive_max(long x); +long __ovld __conv work_group_scan_inclusive_add(long x); +long __ovld __conv work_group_scan_inclusive_min(long x); +long __ovld __conv work_group_scan_inclusive_max(long x); +ulong __ovld __conv work_group_reduce_add(ulong x); +ulong __ovld __conv work_group_reduce_min(ulong x); +ulong __ovld __conv work_group_reduce_max(ulong x); +ulong __ovld __conv work_group_scan_exclusive_add(ulong x); +ulong __ovld __conv work_group_scan_exclusive_min(ulong x); +ulong __ovld __conv work_group_scan_exclusive_max(ulong x); +ulong __ovld __conv work_group_scan_inclusive_add(ulong x); +ulong __ovld __conv work_group_scan_inclusive_min(ulong x); +ulong __ovld __conv work_group_scan_inclusive_max(ulong x); +float __ovld __conv work_group_reduce_add(float x); +float __ovld __conv work_group_reduce_min(float x); +float __ovld __conv work_group_reduce_max(float x); +float __ovld __conv work_group_scan_exclusive_add(float x); +float __ovld __conv work_group_scan_exclusive_min(float x); +float __ovld __conv work_group_scan_exclusive_max(float x); +float __ovld __conv work_group_scan_inclusive_add(float x); +float __ovld __conv work_group_scan_inclusive_min(float x); +float __ovld __conv work_group_scan_inclusive_max(float x); #ifdef cl_khr_fp64 -double __ovld __conv work_group_reduce_add(double); -double __ovld __conv work_group_reduce_min(double); -double __ovld __conv work_group_reduce_max(double); -double __ovld __conv work_group_scan_exclusive_add(double); -double __ovld __conv work_group_scan_exclusive_min(double); -double __ovld __conv work_group_scan_exclusive_max(double); -double __ovld __conv work_group_scan_inclusive_add(double); -double __ovld __conv work_group_scan_inclusive_min(double); -double __ovld __conv work_group_scan_inclusive_max(double); +double __ovld __conv work_group_reduce_add(double x); +double __ovld __conv work_group_reduce_min(double x); +double __ovld __conv work_group_reduce_max(double x); +double __ovld __conv work_group_scan_exclusive_add(double x); +double __ovld __conv work_group_scan_exclusive_min(double x); +double __ovld __conv work_group_scan_exclusive_max(double x); +double __ovld __conv work_group_scan_inclusive_add(double x); +double __ovld __conv work_group_scan_inclusive_min(double x); +double __ovld __conv work_group_scan_inclusive_max(double x); #endif //cl_khr_fp64 #endif //defined(__opencl_c_work_group_collective_functions) @@ -16315,78 +17073,78 @@ long __ovld __conv sub_group_broadcast(long , uint sub_group_local_id); ulong __ovld __conv sub_group_broadcast(ulong, uint sub_group_local_id); float __ovld __conv sub_group_broadcast(float, uint sub_group_local_id); -int __ovld __conv sub_group_reduce_add(int ); -uint __ovld __conv sub_group_reduce_add(uint ); -long __ovld __conv sub_group_reduce_add(long ); -ulong __ovld __conv sub_group_reduce_add(ulong); -float __ovld __conv sub_group_reduce_add(float); -int __ovld __conv sub_group_reduce_min(int ); -uint __ovld __conv sub_group_reduce_min(uint ); -long __ovld __conv sub_group_reduce_min(long ); -ulong __ovld __conv sub_group_reduce_min(ulong); -float __ovld __conv sub_group_reduce_min(float); -int __ovld __conv sub_group_reduce_max(int ); -uint __ovld __conv sub_group_reduce_max(uint ); -long __ovld __conv sub_group_reduce_max(long ); -ulong __ovld __conv sub_group_reduce_max(ulong); -float __ovld __conv sub_group_reduce_max(float); - -int __ovld __conv sub_group_scan_exclusive_add(int ); -uint __ovld __conv sub_group_scan_exclusive_add(uint ); -long __ovld __conv sub_group_scan_exclusive_add(long ); -ulong __ovld __conv sub_group_scan_exclusive_add(ulong); -float __ovld __conv sub_group_scan_exclusive_add(float); -int __ovld __conv sub_group_scan_exclusive_min(int ); -uint __ovld __conv sub_group_scan_exclusive_min(uint ); -long __ovld __conv sub_group_scan_exclusive_min(long ); -ulong __ovld __conv sub_group_scan_exclusive_min(ulong); -float __ovld __conv sub_group_scan_exclusive_min(float); -int __ovld __conv sub_group_scan_exclusive_max(int ); -uint __ovld __conv sub_group_scan_exclusive_max(uint ); -long __ovld __conv sub_group_scan_exclusive_max(long ); -ulong __ovld __conv sub_group_scan_exclusive_max(ulong); -float __ovld __conv sub_group_scan_exclusive_max(float); - -int __ovld __conv sub_group_scan_inclusive_add(int ); -uint __ovld __conv sub_group_scan_inclusive_add(uint ); -long __ovld __conv sub_group_scan_inclusive_add(long ); -ulong __ovld __conv sub_group_scan_inclusive_add(ulong); -float __ovld __conv sub_group_scan_inclusive_add(float); -int __ovld __conv sub_group_scan_inclusive_min(int ); -uint __ovld __conv sub_group_scan_inclusive_min(uint ); -long __ovld __conv sub_group_scan_inclusive_min(long ); -ulong __ovld __conv sub_group_scan_inclusive_min(ulong); -float __ovld __conv sub_group_scan_inclusive_min(float); -int __ovld __conv sub_group_scan_inclusive_max(int ); -uint __ovld __conv sub_group_scan_inclusive_max(uint ); -long __ovld __conv sub_group_scan_inclusive_max(long ); -ulong __ovld __conv sub_group_scan_inclusive_max(ulong); -float __ovld __conv sub_group_scan_inclusive_max(float); +int __ovld __conv sub_group_reduce_add(int x); +uint __ovld __conv sub_group_reduce_add(uint x); +long __ovld __conv sub_group_reduce_add(long x); +ulong __ovld __conv sub_group_reduce_add(ulong x); +float __ovld __conv sub_group_reduce_add(float x); +int __ovld __conv sub_group_reduce_min(int x); +uint __ovld __conv sub_group_reduce_min(uint x); +long __ovld __conv sub_group_reduce_min(long x); +ulong __ovld __conv sub_group_reduce_min(ulong x); +float __ovld __conv sub_group_reduce_min(float x); +int __ovld __conv sub_group_reduce_max(int x); +uint __ovld __conv sub_group_reduce_max(uint x); +long __ovld __conv sub_group_reduce_max(long x); +ulong __ovld __conv sub_group_reduce_max(ulong x); +float __ovld __conv sub_group_reduce_max(float x); + +int __ovld __conv sub_group_scan_exclusive_add(int x); +uint __ovld __conv sub_group_scan_exclusive_add(uint x); +long __ovld __conv sub_group_scan_exclusive_add(long x); +ulong __ovld __conv sub_group_scan_exclusive_add(ulong x); +float __ovld __conv sub_group_scan_exclusive_add(float x); +int __ovld __conv sub_group_scan_exclusive_min(int x); +uint __ovld __conv sub_group_scan_exclusive_min(uint x); +long __ovld __conv sub_group_scan_exclusive_min(long x); +ulong __ovld __conv sub_group_scan_exclusive_min(ulong x); +float __ovld __conv sub_group_scan_exclusive_min(float x); +int __ovld __conv sub_group_scan_exclusive_max(int x); +uint __ovld __conv sub_group_scan_exclusive_max(uint x); +long __ovld __conv sub_group_scan_exclusive_max(long x); +ulong __ovld __conv sub_group_scan_exclusive_max(ulong x); +float __ovld __conv sub_group_scan_exclusive_max(float x); + +int __ovld __conv sub_group_scan_inclusive_add(int x); +uint __ovld __conv sub_group_scan_inclusive_add(uint x); +long __ovld __conv sub_group_scan_inclusive_add(long x); +ulong __ovld __conv sub_group_scan_inclusive_add(ulong x); +float __ovld __conv sub_group_scan_inclusive_add(float x); +int __ovld __conv sub_group_scan_inclusive_min(int x); +uint __ovld __conv sub_group_scan_inclusive_min(uint x); +long __ovld __conv sub_group_scan_inclusive_min(long x); +ulong __ovld __conv sub_group_scan_inclusive_min(ulong x); +float __ovld __conv sub_group_scan_inclusive_min(float x); +int __ovld __conv sub_group_scan_inclusive_max(int x); +uint __ovld __conv sub_group_scan_inclusive_max(uint x); +long __ovld __conv sub_group_scan_inclusive_max(long x); +ulong __ovld __conv sub_group_scan_inclusive_max(ulong x); +float __ovld __conv sub_group_scan_inclusive_max(float x); #ifdef cl_khr_fp16 half __ovld __conv sub_group_broadcast(half, uint sub_group_local_id); -half __ovld __conv sub_group_reduce_add(half); -half __ovld __conv sub_group_reduce_min(half); -half __ovld __conv sub_group_reduce_max(half); -half __ovld __conv sub_group_scan_exclusive_add(half); -half __ovld __conv sub_group_scan_exclusive_min(half); -half __ovld __conv sub_group_scan_exclusive_max(half); -half __ovld __conv sub_group_scan_inclusive_add(half); -half __ovld __conv sub_group_scan_inclusive_min(half); -half __ovld __conv sub_group_scan_inclusive_max(half); +half __ovld __conv sub_group_reduce_add(half x); +half __ovld __conv sub_group_reduce_min(half x); +half __ovld __conv sub_group_reduce_max(half x); +half __ovld __conv sub_group_scan_exclusive_add(half x); +half __ovld __conv sub_group_scan_exclusive_min(half x); +half __ovld __conv sub_group_scan_exclusive_max(half x); +half __ovld __conv sub_group_scan_inclusive_add(half x); +half __ovld __conv sub_group_scan_inclusive_min(half x); +half __ovld __conv sub_group_scan_inclusive_max(half x); #endif //cl_khr_fp16 #ifdef cl_khr_fp64 double __ovld __conv sub_group_broadcast(double, uint sub_group_local_id); -double __ovld __conv sub_group_reduce_add(double); -double __ovld __conv sub_group_reduce_min(double); -double __ovld __conv sub_group_reduce_max(double); -double __ovld __conv sub_group_scan_exclusive_add(double); -double __ovld __conv sub_group_scan_exclusive_min(double); -double __ovld __conv sub_group_scan_exclusive_max(double); -double __ovld __conv sub_group_scan_inclusive_add(double); -double __ovld __conv sub_group_scan_inclusive_min(double); -double __ovld __conv sub_group_scan_inclusive_max(double); +double __ovld __conv sub_group_reduce_add(double x); +double __ovld __conv sub_group_reduce_min(double x); +double __ovld __conv sub_group_reduce_max(double x); +double __ovld __conv sub_group_scan_exclusive_add(double x); +double __ovld __conv sub_group_scan_exclusive_min(double x); +double __ovld __conv sub_group_scan_exclusive_max(double x); +double __ovld __conv sub_group_scan_inclusive_add(double x); +double __ovld __conv sub_group_scan_inclusive_min(double x); +double __ovld __conv sub_group_scan_inclusive_max(double x); #endif //cl_khr_fp64 #endif // __opencl_subgroup_builtins @@ -18450,7 +19208,7 @@ uint16 __ovld amd_lerp(uint16, uint16, uint16); uint __ovld amd_pack(float4 v); -uint __ovld amd_sad4(uint4, uint4, uint); +uint __ovld amd_sad4(uint4, uint4, uint ); uint __ovld amd_sadhi(uint, uint, uint); uint2 __ovld amd_sadhi(uint2, uint2, uint2); @@ -18639,8 +19397,6 @@ int __ovld arm_dot_acc_sat(char4, char4, int); // Disable any extensions we may have enabled previously. #pragma OPENCL EXTENSION all : disable -#undef __opencl_c_named_address_space_builtins - #undef __cnfn #undef __ovld #endif //_OPENCL_H_ diff --git a/clang/lib/Headers/openmp_wrappers/cmath b/clang/lib/Headers/openmp_wrappers/cmath index e1b71516e72c2..346b2baa08157 100644 --- a/clang/lib/Headers/openmp_wrappers/cmath +++ b/clang/lib/Headers/openmp_wrappers/cmath @@ -16,14 +16,16 @@ #include_next -// Make sure we include our math.h overlay, it probably happend already but we -// need to be sure. +// Make sure we include our new and math.h overlays, it probably happened already +// but we need to be sure. +#include #include // We (might) need cstdlib because __clang_cuda_cmath.h below declares `abs` // which might live in cstdlib. #include +#ifdef __NVPTX__ // We need limits because __clang_cuda_cmath.h below uses `std::numeric_limit`. #include @@ -74,18 +76,22 @@ __DEVICE__ float tgamma(float __x) { return ::tgammaf(__x); } #undef __DEVICE__ #pragma omp end declare variant +#endif // __NVPTX__ #ifdef __AMDGCN__ #pragma omp begin declare variant match(device = {arch(amdgcn)}) #pragma push_macro("__constant__") #define __constant__ __attribute__((constant)) + +#define __HIP__ #define __OPENMP_AMDGCN__ #include <__clang_hip_cmath.h> #pragma pop_macro("__constant__") #undef __OPENMP_AMDGCN__ +#undef __HIP__ // Define overloads otherwise which are absent #define __DEVICE__ static constexpr __attribute__((always_inline, nothrow)) @@ -129,4 +135,4 @@ __DEVICE__ float tgamma(float __x) { return ::tgammaf(__x); } #pragma omp end declare variant #endif // __AMDGCN__ -#endif +#endif // __CLANG_OPENMP_CMATH_H__ diff --git a/clang/lib/Headers/openmp_wrappers/complex b/clang/lib/Headers/openmp_wrappers/complex index 1ceecc1af8aec..4135c5e6df3f8 100644 --- a/clang/lib/Headers/openmp_wrappers/complex +++ b/clang/lib/Headers/openmp_wrappers/complex @@ -29,7 +29,7 @@ #undef __OPENMP_AMDGCN__ #endif // __AMDGCN__ -#endif +#endif //__CLANG_OPENMP_COMPLEX__ // Grab the host header too. #include_next diff --git a/clang/lib/Headers/openmp_wrappers/hip/hip_runtime.h b/clang/lib/Headers/openmp_wrappers/hip/hip_runtime.h new file mode 100644 index 0000000000000..73d2f6680c242 --- /dev/null +++ b/clang/lib/Headers/openmp_wrappers/hip/hip_runtime.h @@ -0,0 +1,28 @@ +/*===-- hip_runtime - OpenMP hip_runtime.h wrapper for target regions ------=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + */ + +#ifndef __CLANG_OPENMP_HIP_RUNTIME_H__ +#define __CLANG_OPENMP_HIP_RUNTIME_H__ + +#ifndef _OPENMP +#error "This file is for OpenMP compilation only." +#endif + +#include +#define __OPENMP_AMDGCN__ +#include_next + +#pragma omp begin declare variant match( \ + device = {arch(amdgcn)}, implementation = {extension(match_any)}) + +#pragma omp end declare variant + +// Now get the actual hip headers + +#endif // __CLANG_OPENMP_HIP_RUNTIME_H__ diff --git a/clang/lib/Headers/openmp_wrappers/math.h b/clang/lib/Headers/openmp_wrappers/math.h index 1e3c07cfdb8cd..1e93b96b98f9b 100644 --- a/clang/lib/Headers/openmp_wrappers/math.h +++ b/clang/lib/Headers/openmp_wrappers/math.h @@ -27,6 +27,10 @@ #error "This file is for OpenMP compilation only." #endif +#ifdef __cplusplus +#include +#endif + #include_next // We need limits.h for __clang_cuda_math.h below and because it should not hurt @@ -48,14 +52,19 @@ #pragma omp end declare variant -#ifdef __AMDGCN__ #pragma omp begin declare variant match(device = {arch(amdgcn)}) +#ifdef __AMDGCN__ +#ifndef __OPENMP_AMDGCN__ #define __OPENMP_AMDGCN__ -#include <__clang_hip_math.h> -#undef __OPENMP_AMDGCN__ - -#pragma omp end declare variant +#endif #endif +#ifndef __HIP__ +#define __HIP__ #endif + +#include <__clang_hip_math.h> +#pragma omp end declare variant + +#endif // __CLANG_OPENMP_MATH_H__ diff --git a/clang/lib/Lex/PPMacroExpansion.cpp b/clang/lib/Lex/PPMacroExpansion.cpp index dd80ae586a1f6..d8281144366ee 100644 --- a/clang/lib/Lex/PPMacroExpansion.cpp +++ b/clang/lib/Lex/PPMacroExpansion.cpp @@ -1760,8 +1760,7 @@ void Preprocessor::ExpandBuiltinMacro(Token &Tok) { Tok, *this, diag::err_feature_check_malformed); if (!II) return false; - unsigned BuiltinID = II->getBuiltinID(); - if (BuiltinID != 0) { + else if (II->getBuiltinID() != 0) { switch (II->getBuiltinID()) { case Builtin::BI__builtin_cpu_is: return getTargetInfo().supportsCpuIs(); @@ -1775,11 +1774,8 @@ void Preprocessor::ExpandBuiltinMacro(Token &Tok) { // usual allocation and deallocation functions. Required by libc++ return 201802; default: - // __has_builtin should return false for aux builtins. - if (getBuiltinInfo().isAuxBuiltinID(BuiltinID)) - return false; return Builtin::evaluateRequiredTargetFeatures( - getBuiltinInfo().getRequiredFeatures(BuiltinID), + getBuiltinInfo().getRequiredFeatures(II->getBuiltinID()), getTargetInfo().getTargetOpts().FeatureMap); } return true; diff --git a/clang/lib/Sema/AnalysisBasedWarnings.cpp b/clang/lib/Sema/AnalysisBasedWarnings.cpp index 140b709dbb651..9ae9a001cf3be 100644 --- a/clang/lib/Sema/AnalysisBasedWarnings.cpp +++ b/clang/lib/Sema/AnalysisBasedWarnings.cpp @@ -1143,14 +1143,6 @@ static bool DiagnoseUninitializedConstRefUse(Sema &S, const VarDecl *VD, return !S.getDiagnostics().isLastDiagnosticIgnored(); } -/// Diagnose uninitialized const pointer usages. -static bool DiagnoseUninitializedConstPtrUse(Sema &S, const VarDecl *VD, - const UninitUse &Use) { - S.Diag(Use.getUser()->getBeginLoc(), diag::warn_uninit_const_pointer) - << VD->getDeclName() << Use.getUser()->getSourceRange(); - return !S.getDiagnostics().isLastDiagnosticIgnored(); -} - /// DiagnoseUninitializedUse -- Helper function for diagnosing uses of an /// uninitialized variable. This manages the different forms of diagnostic /// emitted for particular types of uses. Returns true if the use was diagnosed @@ -1756,9 +1748,9 @@ class UninitValsDiagReporter : public UninitVariablesHandler { // a stable ordering. llvm::sort(*vec, [](const UninitUse &a, const UninitUse &b) { // Prefer the direct use of an uninitialized variable over its use via - // constant reference or pointer. - if (a.isConstRefOrPtrUse() != b.isConstRefOrPtrUse()) - return b.isConstRefOrPtrUse(); + // constant reference. + if (a.isConstRefUse() != b.isConstRefUse()) + return b.isConstRefUse(); // Prefer a more confident report over a less confident one. if (a.getKind() != b.getKind()) return a.getKind() > b.getKind(); @@ -1769,9 +1761,6 @@ class UninitValsDiagReporter : public UninitVariablesHandler { if (U.isConstRefUse()) { if (DiagnoseUninitializedConstRefUse(S, vd, U)) return; - } else if (U.isConstPtrUse()) { - if (DiagnoseUninitializedConstPtrUse(S, vd, U)) - return; } else { // If we have self-init, downgrade all uses to 'may be uninitialized'. UninitUse Use = hasSelfInit ? UninitUse(U.getUser(), false) : U; @@ -3037,8 +3026,7 @@ void clang::sema::AnalysisBasedWarnings::IssueWarnings( if (!Diags.isIgnored(diag::warn_uninit_var, D->getBeginLoc()) || !Diags.isIgnored(diag::warn_sometimes_uninit_var, D->getBeginLoc()) || !Diags.isIgnored(diag::warn_maybe_uninit_var, D->getBeginLoc()) || - !Diags.isIgnored(diag::warn_uninit_const_reference, D->getBeginLoc()) || - !Diags.isIgnored(diag::warn_uninit_const_pointer, D->getBeginLoc())) { + !Diags.isIgnored(diag::warn_uninit_const_reference, D->getBeginLoc())) { if (CFG *cfg = AC.getCFG()) { UninitValsDiagReporter reporter(S); UninitVariablesAnalysisStats stats; diff --git a/clang/lib/Sema/JumpDiagnostics.cpp b/clang/lib/Sema/JumpDiagnostics.cpp index 36704c3826dfd..2c6ae89513241 100644 --- a/clang/lib/Sema/JumpDiagnostics.cpp +++ b/clang/lib/Sema/JumpDiagnostics.cpp @@ -19,6 +19,7 @@ #include "clang/AST/StmtOpenACC.h" #include "clang/AST/StmtOpenMP.h" #include "clang/Basic/SourceLocation.h" +#include "clang/Sema/SemaAMDGPU.h" #include "clang/Sema/SemaInternal.h" #include "llvm/ADT/BitVector.h" using namespace clang; @@ -367,8 +368,10 @@ void JumpScopeChecker::BuildScopeInformation(Stmt *S, case Stmt::IfStmtClass: { IfStmt *IS = cast(S); + bool AMDGPUPredicate = false; if (!(IS->isConstexpr() || IS->isConsteval() || - IS->isObjCAvailabilityCheck())) + IS->isObjCAvailabilityCheck() || + (AMDGPUPredicate = this->S.AMDGPU().IsPredicate(IS->getCond())))) break; unsigned Diag = diag::note_protected_by_if_available; @@ -376,6 +379,8 @@ void JumpScopeChecker::BuildScopeInformation(Stmt *S, Diag = diag::note_protected_by_constexpr_if; else if (IS->isConsteval()) Diag = diag::note_protected_by_consteval_if; + else if (AMDGPUPredicate) + Diag = diag::note_amdgcn_protected_by_predicate; if (VarDecl *Var = IS->getConditionVariable()) BuildScopeInformation(Var, ParentScope); diff --git a/clang/lib/Sema/OpenCLBuiltins.td b/clang/lib/Sema/OpenCLBuiltins.td index fe86d42dac4db..72d95c32747de 100644 --- a/clang/lib/Sema/OpenCLBuiltins.td +++ b/clang/lib/Sema/OpenCLBuiltins.td @@ -896,6 +896,7 @@ defm : VloadVstore<[ConstantAS], 0>; multiclass VloadVstoreHalf addrspaces, bit defStores> { foreach AS = addrspaces in { def : Builtin<"vload_half", [Float, Size, !cast("HalfPtrConst" # AS)], Attr.Pure>; + def : Builtin<"vloada_half", [Float, Size, !cast("HalfPtrConst" # AS)], Attr.Pure>; foreach VSize = [2, 3, 4, 8, 16] in { foreach name = ["vload_half" # VSize, "vloada_half" # VSize] in { def : Builtin, Size, !cast("HalfPtrConst" # AS)], Attr.Pure>; @@ -903,7 +904,7 @@ multiclass VloadVstoreHalf addrspaces, bit defStores> { } if defStores then { foreach rnd = ["", "_rte", "_rtz", "_rtp", "_rtn"] in { - foreach name = ["vstore_half" # rnd] in { + foreach name = ["vstore_half" # rnd, "vstorea_half" # rnd] in { def : Builtin("HalfPtr" # AS)]>; def : Builtin("HalfPtr" # AS)]>; } diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index 23bf7f217a01a..c0be3e71c0583 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -568,8 +568,13 @@ void Sema::Initialize() { } if (Context.getTargetInfo().getTriple().isAMDGPU() || + (Context.getTargetInfo().getTriple().isSPIRV() && + Context.getTargetInfo().getTriple().getVendor() == llvm::Triple::AMD) || (Context.getAuxTargetInfo() && - Context.getAuxTargetInfo()->getTriple().isAMDGPU())) { + (Context.getAuxTargetInfo()->getTriple().isAMDGPU() || + (Context.getAuxTargetInfo()->getTriple().isSPIRV() && + Context.getAuxTargetInfo()->getTriple().getVendor() == + llvm::Triple::AMD)))) { #define AMDGPU_TYPE(Name, Id, SingletonId, Width, Align) \ addImplicitTypedef(Name, Context.SingletonId); #include "clang/Basic/AMDGPUTypes.def" diff --git a/clang/lib/Sema/SemaAMDGPU.cpp b/clang/lib/Sema/SemaAMDGPU.cpp index e32f4376a5ebf..0a0ffb69e662c 100644 --- a/clang/lib/Sema/SemaAMDGPU.cpp +++ b/clang/lib/Sema/SemaAMDGPU.cpp @@ -14,6 +14,8 @@ #include "clang/Basic/DiagnosticFrontend.h" #include "clang/Basic/DiagnosticSema.h" #include "clang/Basic/TargetBuiltins.h" +#include "clang/Basic/TargetInfo.h" +#include "clang/Frontend/FrontendDiagnostic.h" #include "clang/Sema/Ownership.h" #include "clang/Sema/Sema.h" #include "llvm/Support/AMDGPUAddrSpace.h" @@ -214,6 +216,9 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, (SemaRef.BuiltinConstantArg(TheCall, ArgCount, Result)) || (SemaRef.BuiltinConstantArg(TheCall, (ArgCount - 1), Result)); } + case AMDGPU::BI__builtin_amdgcn_global_load_b128: + case AMDGPU::BI__builtin_amdgcn_global_store_b128: + return checkScopedMemAccessFunctionCall(TheCall); default: return false; } @@ -303,6 +308,19 @@ bool SemaAMDGPU::checkCoopAtomicFunctionCall(CallExpr *TheCall, bool IsStore) { return Fail; } +bool SemaAMDGPU::checkScopedMemAccessFunctionCall(CallExpr *TheCall) { + bool Fail = false; + // Last argument is a string literal + Expr *Arg = TheCall->getArg(TheCall->getNumArgs() - 1); + auto Scope = dyn_cast(Arg->IgnoreParenCasts()); + if (!Scope) { + Fail = true; + Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal) + << Arg->getSourceRange(); + } + return Fail; +} + bool SemaAMDGPU::checkMovDPPFunctionCall(CallExpr *TheCall, unsigned NumArgs, unsigned NumDataArgs) { assert(NumDataArgs <= 2); @@ -541,4 +559,80 @@ void SemaAMDGPU::handleAMDGPUMaxNumWorkGroupsAttr(Decl *D, addAMDGPUMaxNumWorkGroupsAttr(D, AL, AL.getArgAsExpr(0), YExpr, ZExpr); } +Expr *SemaAMDGPU::ExpandAMDGPUPredicateBI(CallExpr *CE) { + ASTContext &Ctx = getASTContext(); + QualType BoolTy = Ctx.getLogicalOperationType(); + llvm::APInt False = llvm::APInt::getZero(Ctx.getIntWidth(BoolTy)); + llvm::APInt True = llvm::APInt::getAllOnes(Ctx.getIntWidth(BoolTy)); + SourceLocation Loc = CE->getExprLoc(); + + if (!CE->getBuiltinCallee()) + return *ExpandedPredicates + .insert(IntegerLiteral::Create(Ctx, False, BoolTy, Loc)) + .first; + + bool P = false; + unsigned BI = CE->getBuiltinCallee(); + if (Ctx.BuiltinInfo.isAuxBuiltinID(BI)) + BI = Ctx.BuiltinInfo.getAuxBuiltinID(BI); + + if (BI == AMDGPU::BI__builtin_amdgcn_processor_is) { + auto *GFX = dyn_cast(CE->getArg(0)->IgnoreParenCasts()); + if (!GFX) { + Diag(Loc, diag::err_amdgcn_processor_is_arg_not_literal); + return nullptr; + } + + StringRef N = GFX->getString(); + const TargetInfo &TI = Ctx.getTargetInfo(); + const TargetInfo *AuxTI = Ctx.getAuxTargetInfo(); + if (!TI.isValidCPUName(N) && (!AuxTI || !AuxTI->isValidCPUName(N))) { + Diag(Loc, diag::err_amdgcn_processor_is_arg_invalid_value) << N; + SmallVector ValidList; + if (TI.getTriple().getVendor() == llvm::Triple::VendorType::AMD) + TI.fillValidCPUList(ValidList); + else if (AuxTI) // Since the BI is present it must be and AMDGPU triple. + AuxTI->fillValidCPUList(ValidList); + if (!ValidList.empty()) + Diag(Loc, diag::note_amdgcn_processor_is_valid_options) + << llvm::join(ValidList, ", "); + return nullptr; + } + if (Ctx.getTargetInfo().getTriple().isSPIRV()) { + CE->setType(BoolTy); + return *ExpandedPredicates.insert(CE).first; + } + + if (auto TID = Ctx.getTargetInfo().getTargetID()) + P = TID->find(N) == 0; + } else { + Expr *Arg = CE->getArg(0); + if (!Arg || Arg->getType() != Ctx.BuiltinFnTy) { + Diag(Loc, diag::err_amdgcn_is_invocable_arg_invalid_value) << Arg; + return nullptr; + } + + if (Ctx.getTargetInfo().getTriple().isSPIRV()) { + CE->setType(BoolTy); + return *ExpandedPredicates.insert(CE).first; + } + + auto *FD = cast(Arg->getReferencedDeclOfCallee()); + + StringRef RF = Ctx.BuiltinInfo.getRequiredFeatures(FD->getBuiltinID()); + llvm::StringMap CF; + Ctx.getFunctionFeatureMap(CF, FD); + + P = Builtin::evaluateRequiredTargetFeatures(RF, CF); + } + + return *ExpandedPredicates + .insert( + IntegerLiteral::Create(Ctx, P ? True : False, BoolTy, Loc)) + .first; +} + +bool SemaAMDGPU::IsPredicate(Expr *E) const { + return ExpandedPredicates.contains(E); +} } // namespace clang diff --git a/clang/lib/Sema/SemaCast.cpp b/clang/lib/Sema/SemaCast.cpp index 5360f8a2908bf..46fc19e8240e3 100644 --- a/clang/lib/Sema/SemaCast.cpp +++ b/clang/lib/Sema/SemaCast.cpp @@ -23,6 +23,7 @@ #include "clang/Basic/TargetInfo.h" #include "clang/Lex/Preprocessor.h" #include "clang/Sema/Initialization.h" +#include "clang/Sema/SemaAMDGPU.h" #include "clang/Sema/SemaHLSL.h" #include "clang/Sema/SemaObjC.h" #include "clang/Sema/SemaRISCV.h" @@ -1592,6 +1593,22 @@ static TryCastResult TryStaticCast(Sema &Self, ExprResult &SrcExpr, return TC_Success; } + if (SrcType == Self.Context.AMDGPUFeaturePredicateTy && + DestType == Self.Context.getLogicalOperationType()) { + SrcExpr = Self.AMDGPU().ExpandAMDGPUPredicateBI( + dyn_cast(SrcExpr.get())); + Kind = CK_NoOp; + return TC_Success; + } + + if (SrcType == Self.Context.AMDGPUFeaturePredicateTy && + DestType == Self.Context.getLogicalOperationType()) { + SrcExpr = Self.AMDGPU().ExpandAMDGPUPredicateBI( + dyn_cast(SrcExpr.get())); + Kind = CK_NoOp; + return TC_Success; + } + // We tried everything. Everything! Nothing works! :-( return TC_NotApplicable; } diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index f4517877b04c8..380a852207c21 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -12367,9 +12367,11 @@ static void DiagnoseMixedUnicodeImplicitConversion(Sema &S, const Type *Source, } else { bool LosesPrecision = S.getASTContext().getIntWidth(E->getType()) > S.getASTContext().getIntWidth(T); +#ifdef FIXME_GTEST_ROCSOLVER DiagnoseImpCast(S, E, T, CC, LosesPrecision ? diag::warn_impcast_unicode_precision : diag::warn_impcast_unicode_char_type); +#endif } } diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index fc3aabf5741ca..5c5f127aa4e33 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -13777,6 +13777,26 @@ void Sema::AddInitializerToDecl(Decl *RealDecl, Expr *Init, bool DirectInit) { return; } + // __amdgpu_feature_predicate_t cannot be initialised + if (VDecl->getType().getDesugaredType(Context) == + Context.AMDGPUFeaturePredicateTy) { + Diag(VDecl->getLocation(), + diag::err_amdgcn_predicate_type_is_not_constructible) + << VDecl; + VDecl->setInvalidDecl(); + return; + } + + // __amdgpu_feature_predicate_t cannot be initialised + if (VDecl->getType().getDesugaredType(Context) == + Context.AMDGPUFeaturePredicateTy) { + Diag(VDecl->getLocation(), + diag::err_amdgcn_predicate_type_is_not_constructible) + << VDecl; + VDecl->setInvalidDecl(); + return; + } + // WebAssembly tables can't be used to initialise a variable. if (!Init->getType().isNull() && Init->getType()->isWebAssemblyTableType()) { Diag(Init->getExprLoc(), diag::err_wasm_table_art) << 0; @@ -14277,6 +14297,13 @@ void Sema::ActOnUninitializedDecl(Decl *RealDecl) { if (VarDecl *Var = dyn_cast(RealDecl)) { QualType Type = Var->getType(); + if (Type.getDesugaredType(Context) == Context.AMDGPUFeaturePredicateTy) { + Diag(Var->getLocation(), + diag::err_amdgcn_predicate_type_is_not_constructible) + << Var; + Var->setInvalidDecl(); + return; + } // C++1z [dcl.dcl]p1 grammar implies that an initializer is mandatory. if (isa(RealDecl)) { Diag(Var->getLocation(), diag::err_decomp_decl_requires_init) << Var; diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index a50c27610dc96..686acd3416ecf 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -52,6 +52,7 @@ #include "clang/Sema/ParsedTemplate.h" #include "clang/Sema/Scope.h" #include "clang/Sema/ScopeInfo.h" +#include "clang/Sema/SemaAMDGPU.h" #include "clang/Sema/SemaARM.h" #include "clang/Sema/SemaCUDA.h" #include "clang/Sema/SemaFixItUtils.h" @@ -6588,6 +6589,22 @@ ExprResult Sema::BuildCallExpr(Scope *Scope, Expr *Fn, SourceLocation LParenLoc, if (Result.isInvalid()) return ExprError(); Fn = Result.get(); + // The __builtin_amdgcn_is_invocable builtin is special, and will be resolved + // later, when we check boolean conditions, for now we merely forward it + // without any additional checking. + if (Fn->getType() == Context.BuiltinFnTy && ArgExprs.size() == 1 && + ArgExprs[0]->getType() == Context.BuiltinFnTy) { + const auto *FD = cast(Fn->getReferencedDeclOfCallee()); + + if (FD->getName() == "__builtin_amdgcn_is_invocable") { + QualType FnPtrTy = Context.getPointerType(FD->getType()); + Expr *R = ImpCastExprToType(Fn, FnPtrTy, CK_BuiltinFnToFnPtr).get(); + return CallExpr::Create( + Context, R, ArgExprs, Context.AMDGPUFeaturePredicateTy, + ExprValueKind::VK_PRValue, RParenLoc, FPOptionsOverride()); + } + } + if (CheckArgsForPlaceholders(ArgExprs)) return ExprError(); @@ -13490,6 +13507,20 @@ inline QualType Sema::CheckBitwiseOperands(ExprResult &LHS, ExprResult &RHS, return ResultTy; } +static inline bool IsAMDGPUPredicateBI(Expr *E) { + if (!E->getType()->isVoidType()) + return false; + + if (auto *CE = dyn_cast(E)) { + if (auto *BI = CE->getDirectCallee()) + if (BI->getName() == "__builtin_amdgcn_processor_is" || + BI->getName() == "__builtin_amdgcn_is_invocable") + return true; + } + + return false; +} + // C99 6.5.[13,14] inline QualType Sema::CheckLogicalOperands(ExprResult &LHS, ExprResult &RHS, SourceLocation Loc, @@ -13585,6 +13616,9 @@ inline QualType Sema::CheckLogicalOperands(ExprResult &LHS, ExprResult &RHS, // The following is safe because we only use this method for // non-overloadable operands. + if (IsAMDGPUPredicateBI(LHS.get()) && IsAMDGPUPredicateBI(RHS.get())) + return Context.VoidTy; + // C++ [expr.log.and]p1 // C++ [expr.log.or]p1 // The operands are both contextually converted to type bool. @@ -15790,6 +15824,38 @@ static bool isOverflowingIntegerType(ASTContext &Ctx, QualType T) { return Ctx.getIntWidth(T) >= Ctx.getIntWidth(Ctx.IntTy); } +static Expr *ExpandAMDGPUPredicateBI(ASTContext &Ctx, CallExpr *CE) { + if (!CE->getBuiltinCallee()) + return CXXBoolLiteralExpr::Create(Ctx, false, Ctx.BoolTy, CE->getExprLoc()); + + if (Ctx.getTargetInfo().getTriple().isSPIRV()) { + CE->setType(Ctx.getLogicalOperationType()); + return CE; + } + + bool P = false; + auto &TI = Ctx.getTargetInfo(); + + if (CE->getDirectCallee()->getName() == "__builtin_amdgcn_processor_is") { + auto *GFX = dyn_cast(CE->getArg(0)->IgnoreParenCasts()); + auto TID = TI.getTargetID(); + if (GFX && TID) { + auto N = GFX->getString(); + P = TI.isValidCPUName(GFX->getString()) && TID->find(N) == 0; + } + } else { + auto *FD = cast(CE->getArg(0)->getReferencedDeclOfCallee()); + + StringRef RF = Ctx.BuiltinInfo.getRequiredFeatures(FD->getBuiltinID()); + llvm::StringMap CF; + Ctx.getFunctionFeatureMap(CF, FD); + + P = Builtin::evaluateRequiredTargetFeatures(RF, CF); + } + + return CXXBoolLiteralExpr::Create(Ctx, P, Ctx.BoolTy, CE->getExprLoc()); +} + ExprResult Sema::CreateBuiltinUnaryOp(SourceLocation OpLoc, UnaryOperatorKind Opc, Expr *InputExpr, bool IsAfterAmp) { @@ -15981,6 +16047,10 @@ ExprResult Sema::CreateBuiltinUnaryOp(SourceLocation OpLoc, // Vector logical not returns the signed variant of the operand type. resultType = GetSignedVectorType(resultType); break; + } else if (resultType == Context.AMDGPUFeaturePredicateTy) { + resultType = Context.getLogicalOperationType(); + Input = AMDGPU().ExpandAMDGPUPredicateBI(dyn_cast(InputExpr)); + break; } else { return ExprError(Diag(OpLoc, diag::err_typecheck_unary_expr) << resultType << Input.get()->getSourceRange()); @@ -20776,6 +20846,88 @@ void Sema::DiagnoseEqualityWithExtraParens(ParenExpr *ParenE) { } } +static bool ValidateAMDGPUPredicateBI(Sema &Sema, CallExpr *CE) { + if (CE->getDirectCallee()->getName() == "__builtin_amdgcn_processor_is") { + auto *GFX = dyn_cast(CE->getArg(0)->IgnoreParenCasts()); + if (!GFX) { + Sema.Diag(CE->getExprLoc(), + diag::err_amdgcn_processor_is_arg_not_literal); + return false; + } + auto N = GFX->getString(); + if (!Sema.getASTContext().getTargetInfo().isValidCPUName(N) && + (!Sema.getASTContext().getAuxTargetInfo() || + !Sema.getASTContext().getAuxTargetInfo()->isValidCPUName(N))) { + Sema.Diag(CE->getExprLoc(), + diag::err_amdgcn_processor_is_arg_invalid_value) + << N; + return false; + } + } else { + auto *Arg = CE->getArg(0); + if (!Arg || Arg->getType() != Sema.getASTContext().BuiltinFnTy) { + Sema.Diag(CE->getExprLoc(), + diag::err_amdgcn_is_invocable_arg_invalid_value) + << Arg; + return false; + } + } + + return true; +} + +static Expr *MaybeHandleAMDGPUPredicateBI(Sema &Sema, Expr *E, bool &Invalid) { + if (auto *UO = dyn_cast(E)) { + auto *SE = dyn_cast(UO->getSubExpr()); + if (IsAMDGPUPredicateBI(SE)) { + assert(UO->getOpcode() == UnaryOperator::Opcode::UO_LNot && + "__builtin_amdgcn_processor_is and __builtin_amdgcn_is_invocable " + "can only be used as operands of logical ops!"); + + if (!ValidateAMDGPUPredicateBI(Sema, SE)) { + Invalid = true; + return nullptr; + } + + UO->setSubExpr(ExpandAMDGPUPredicateBI(Sema.getASTContext(), SE)); + UO->setType(Sema.getASTContext().getLogicalOperationType()); + + return UO; + } + } + if (auto *BO = dyn_cast(E)) { + auto *LHS = dyn_cast(BO->getLHS()); + auto *RHS = dyn_cast(BO->getRHS()); + if (IsAMDGPUPredicateBI(LHS) && IsAMDGPUPredicateBI(RHS)) { + assert(BO->isLogicalOp() && + "__builtin_amdgcn_processor_is and __builtin_amdgcn_is_invocable " + "can only be used as operands of logical ops!"); + + if (!ValidateAMDGPUPredicateBI(Sema, LHS) || + !ValidateAMDGPUPredicateBI(Sema, RHS)) { + Invalid = true; + return nullptr; + } + + BO->setLHS(ExpandAMDGPUPredicateBI(Sema.getASTContext(), LHS)); + BO->setRHS(ExpandAMDGPUPredicateBI(Sema.getASTContext(), RHS)); + BO->setType(Sema.getASTContext().getLogicalOperationType()); + + return BO; + } + } + if (auto *CE = dyn_cast(E)) + if (IsAMDGPUPredicateBI(CE)) { + if (!ValidateAMDGPUPredicateBI(Sema, CE)) { + Invalid = true; + return nullptr; + } + return ExpandAMDGPUPredicateBI(Sema.getASTContext(), CE); + } + + return nullptr; +} + ExprResult Sema::CheckBooleanCondition(SourceLocation Loc, Expr *E, bool IsConstexpr) { DiagnoseAssignmentAsCondition(E); @@ -20787,6 +20939,9 @@ ExprResult Sema::CheckBooleanCondition(SourceLocation Loc, Expr *E, E = result.get(); if (!E->isTypeDependent()) { + if (E->getType() == Context.AMDGPUFeaturePredicateTy) + return AMDGPU().ExpandAMDGPUPredicateBI(dyn_cast_or_null(E)); + if (getLangOpts().CPlusPlus) return CheckCXXBooleanCondition(E, IsConstexpr); // C++ 6.4p4 diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index 073010d16b428..410a2e49100b8 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -9129,6 +9129,15 @@ bool InitializationSequence::Diagnose(Sema &S, case FK_ConversionFailed: { QualType FromType = OnlyArg->getType(); + // __amdgpu_feature_predicate_t can be explicitly cast to the logical op + // type, although this is almost always an error and we advise against it. + if (FromType == S.Context.AMDGPUFeaturePredicateTy && + DestType == S.Context.getLogicalOperationType()) { + S.Diag(OnlyArg->getExprLoc(), + diag::err_amdgcn_predicate_type_needs_explicit_bool_cast) + << OnlyArg << DestType; + break; + } PartialDiagnostic PDiag = S.PDiag(diag::err_init_conversion_failed) << (int)Entity.getKind() << DestType @@ -9941,6 +9950,14 @@ Sema::PerformCopyInitialization(const InitializedEntity &Entity, if (EqualLoc.isInvalid()) EqualLoc = InitE->getBeginLoc(); + if (Entity.getType().getDesugaredType(Context) == + Context.AMDGPUFeaturePredicateTy && + Entity.getDecl()) { + Diag(EqualLoc, diag::err_amdgcn_predicate_type_is_not_constructible) + << Entity.getDecl(); + return ExprError(); + } + InitializationKind Kind = InitializationKind::CreateCopy( InitE->getBeginLoc(), EqualLoc, AllowExplicit); InitializationSequence Seq(*this, Entity, Kind, InitE, TopLevelOfInitList); diff --git a/clang/lib/Sema/SemaLambda.cpp b/clang/lib/Sema/SemaLambda.cpp index fbc2e7eb30676..f4eacd429c27c 100644 --- a/clang/lib/Sema/SemaLambda.cpp +++ b/clang/lib/Sema/SemaLambda.cpp @@ -484,8 +484,7 @@ void Sema::handleLambdaNumbering( ContextRAII ManglingContext(*this, Class->getDeclContext()); auto getMangleNumberingContext = - [this](CXXRecordDecl *Class, - Decl *ManglingContextDecl) -> MangleNumberingContext * { + [this](CXXRecordDecl *Class, Decl *ManglingContextDecl) -> MangleNumberingContext * { // Get mangle numbering context if there's any extra decl context. if (ManglingContextDecl) return &Context.getManglingNumberContext( diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 6d5cb0fcaea24..6f2ab74d8f0eb 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -4559,7 +4559,123 @@ static void processCapturedRegions(Sema &SemaRef, OpenMPDirectiveKind DKind, void SemaOpenMP::ActOnOpenMPRegionStart(OpenMPDirectiveKind DKind, Scope *CurScope) { + ASTContext &Context = getASTContext(); switch (DKind) { + case OMPD_parallel: + case OMPD_parallel_for: + case OMPD_parallel_for_simd: + case OMPD_parallel_sections: + case OMPD_parallel_master: + case OMPD_parallel_masked: + case OMPD_parallel_loop: + case OMPD_teams: + case OMPD_teams_loop: + case OMPD_teams_distribute: + case OMPD_teams_distribute_simd: { + QualType KmpInt32Ty = Context.getIntTypeForBitwidth(32, 1).withConst(); + QualType KmpInt32PtrTy = + Context.getPointerType(KmpInt32Ty).withConst().withRestrict(); + SemaOpenMP::CapturedParamNameType Params[] = { + std::make_pair(".global_tid.", KmpInt32PtrTy), + std::make_pair(".bound_tid.", KmpInt32PtrTy), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, Params); + break; + } + case OMPD_target_teams: + case OMPD_target_parallel: + case OMPD_target_parallel_for: + case OMPD_target_parallel_for_simd: + case OMPD_target_parallel_loop: + case OMPD_target_teams_distribute: + case OMPD_target_teams_distribute_simd: { + QualType KmpInt32Ty = Context.getIntTypeForBitwidth(32, 1).withConst(); + QualType VoidPtrTy = Context.VoidPtrTy.withConst().withRestrict(); + QualType KmpInt32PtrTy = + Context.getPointerType(KmpInt32Ty).withConst().withRestrict(); + QualType Args[] = {VoidPtrTy}; + FunctionProtoType::ExtProtoInfo EPI; + EPI.Variadic = true; + QualType CopyFnType = Context.getFunctionType(Context.VoidTy, Args, EPI); + SemaOpenMP::CapturedParamNameType Params[] = { + std::make_pair(".global_tid.", KmpInt32Ty), + std::make_pair(".part_id.", KmpInt32PtrTy), + std::make_pair(".privates.", VoidPtrTy), + std::make_pair( + ".copy_fn.", + Context.getPointerType(CopyFnType).withConst().withRestrict()), + std::make_pair(".task_t.", Context.VoidPtrTy.withConst()), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, Params, + /*OpenMPCaptureLevel=*/0); + // Mark this captured region as inlined, because we don't use outlined + // function directly. + SemaRef.getCurCapturedRegion()->TheCapturedDecl->addAttr( + AlwaysInlineAttr::CreateImplicit( + Context, {}, AlwaysInlineAttr::Keyword_forceinline)); + SmallVector ParamsTarget; + if (getLangOpts().OpenMPIsTargetDevice) + ParamsTarget.push_back(std::make_pair(StringRef("dyn_ptr"), VoidPtrTy)); + ParamsTarget.push_back( + std::make_pair(StringRef(), QualType())); // __context with shared vars; + // Start a captured region for 'target' with no implicit parameters. + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, ParamsTarget, + /*OpenMPCaptureLevel=*/1); + SemaOpenMP::CapturedParamNameType ParamsTeamsOrParallel[] = { + std::make_pair(".global_tid.", KmpInt32PtrTy), + std::make_pair(".bound_tid.", KmpInt32PtrTy), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + // Start a captured region for 'teams' or 'parallel'. Both regions have + // the same implicit parameters. + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, ParamsTeamsOrParallel, + /*OpenMPCaptureLevel=*/2); + break; + } + case OMPD_target: + case OMPD_target_simd: { + QualType KmpInt32Ty = Context.getIntTypeForBitwidth(32, 1).withConst(); + QualType VoidPtrTy = Context.VoidPtrTy.withConst().withRestrict(); + QualType KmpInt32PtrTy = + Context.getPointerType(KmpInt32Ty).withConst().withRestrict(); + QualType Args[] = {VoidPtrTy}; + FunctionProtoType::ExtProtoInfo EPI; + EPI.Variadic = true; + QualType CopyFnType = Context.getFunctionType(Context.VoidTy, Args, EPI); + SemaOpenMP::CapturedParamNameType Params[] = { + std::make_pair(".global_tid.", KmpInt32Ty), + std::make_pair(".part_id.", KmpInt32PtrTy), + std::make_pair(".privates.", VoidPtrTy), + std::make_pair( + ".copy_fn.", + Context.getPointerType(CopyFnType).withConst().withRestrict()), + std::make_pair(".task_t.", Context.VoidPtrTy.withConst()), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, Params, + /*OpenMPCaptureLevel=*/0); + // Mark this captured region as inlined, because we don't use outlined + // function directly. + SemaRef.getCurCapturedRegion()->TheCapturedDecl->addAttr( + AlwaysInlineAttr::CreateImplicit( + Context, {}, AlwaysInlineAttr::Keyword_forceinline)); + SmallVector ParamsTarget; + if (getLangOpts().OpenMPIsTargetDevice) + ParamsTarget.push_back(std::make_pair(StringRef("dyn_ptr"), VoidPtrTy)); + ParamsTarget.push_back( + std::make_pair(StringRef(), QualType())); // __context with shared vars; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, ParamsTarget, + /*OpenMPCaptureLevel=*/1); + break; + } case OMPD_atomic: case OMPD_critical: case OMPD_masked: @@ -4573,6 +4689,322 @@ void SemaOpenMP::ActOnOpenMPRegionStart(OpenMPDirectiveKind DKind, case OMPD_fuse: case OMPD_assume: break; + case OMPD_loop: + // TODO: 'loop' may require additional parameters depending on the binding. + // Treat similar to OMPD_simd/OMPD_for for now. + case OMPD_simd: + case OMPD_for: + case OMPD_for_simd: + case OMPD_sections: + case OMPD_single: + case OMPD_taskgroup: + case OMPD_distribute: + case OMPD_distribute_simd: + case OMPD_ordered: + case OMPD_scope: + case OMPD_target_data: + case OMPD_dispatch: { + SemaOpenMP::CapturedParamNameType Params[] = { + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, Params); + break; + } + case OMPD_task: { + QualType KmpInt32Ty = Context.getIntTypeForBitwidth(32, 1).withConst(); + QualType VoidPtrTy = Context.VoidPtrTy.withConst().withRestrict(); + QualType KmpInt32PtrTy = + Context.getPointerType(KmpInt32Ty).withConst().withRestrict(); + QualType Args[] = {VoidPtrTy}; + FunctionProtoType::ExtProtoInfo EPI; + EPI.Variadic = true; + QualType CopyFnType = Context.getFunctionType(Context.VoidTy, Args, EPI); + SemaOpenMP::CapturedParamNameType Params[] = { + std::make_pair(".global_tid.", KmpInt32Ty), + std::make_pair(".part_id.", KmpInt32PtrTy), + std::make_pair(".privates.", VoidPtrTy), + std::make_pair( + ".copy_fn.", + Context.getPointerType(CopyFnType).withConst().withRestrict()), + std::make_pair(".task_t.", Context.VoidPtrTy.withConst()), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, Params); + // Mark this captured region as inlined, because we don't use outlined + // function directly. + SemaRef.getCurCapturedRegion()->TheCapturedDecl->addAttr( + AlwaysInlineAttr::CreateImplicit( + Context, {}, AlwaysInlineAttr::Keyword_forceinline)); + break; + } + case OMPD_taskloop: + case OMPD_taskloop_simd: + case OMPD_master_taskloop: + case OMPD_masked_taskloop: + case OMPD_masked_taskloop_simd: + case OMPD_master_taskloop_simd: { + QualType KmpInt32Ty = + Context.getIntTypeForBitwidth(/*DestWidth=*/32, /*Signed=*/1) + .withConst(); + QualType KmpUInt64Ty = + Context.getIntTypeForBitwidth(/*DestWidth=*/64, /*Signed=*/0) + .withConst(); + QualType KmpInt64Ty = + Context.getIntTypeForBitwidth(/*DestWidth=*/64, /*Signed=*/1) + .withConst(); + QualType VoidPtrTy = Context.VoidPtrTy.withConst().withRestrict(); + QualType KmpInt32PtrTy = + Context.getPointerType(KmpInt32Ty).withConst().withRestrict(); + QualType Args[] = {VoidPtrTy}; + FunctionProtoType::ExtProtoInfo EPI; + EPI.Variadic = true; + QualType CopyFnType = Context.getFunctionType(Context.VoidTy, Args, EPI); + SemaOpenMP::CapturedParamNameType Params[] = { + std::make_pair(".global_tid.", KmpInt32Ty), + std::make_pair(".part_id.", KmpInt32PtrTy), + std::make_pair(".privates.", VoidPtrTy), + std::make_pair( + ".copy_fn.", + Context.getPointerType(CopyFnType).withConst().withRestrict()), + std::make_pair(".task_t.", Context.VoidPtrTy.withConst()), + std::make_pair(".lb.", KmpUInt64Ty), + std::make_pair(".ub.", KmpUInt64Ty), + std::make_pair(".st.", KmpInt64Ty), + std::make_pair(".liter.", KmpInt32Ty), + std::make_pair(".reductions.", VoidPtrTy), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, Params); + // Mark this captured region as inlined, because we don't use outlined + // function directly. + SemaRef.getCurCapturedRegion()->TheCapturedDecl->addAttr( + AlwaysInlineAttr::CreateImplicit( + Context, {}, AlwaysInlineAttr::Keyword_forceinline)); + break; + } + case OMPD_parallel_masked_taskloop: + case OMPD_parallel_masked_taskloop_simd: + case OMPD_parallel_master_taskloop: + case OMPD_parallel_master_taskloop_simd: { + QualType KmpInt32Ty = + Context.getIntTypeForBitwidth(/*DestWidth=*/32, /*Signed=*/1) + .withConst(); + QualType KmpUInt64Ty = + Context.getIntTypeForBitwidth(/*DestWidth=*/64, /*Signed=*/0) + .withConst(); + QualType KmpInt64Ty = + Context.getIntTypeForBitwidth(/*DestWidth=*/64, /*Signed=*/1) + .withConst(); + QualType VoidPtrTy = Context.VoidPtrTy.withConst().withRestrict(); + QualType KmpInt32PtrTy = + Context.getPointerType(KmpInt32Ty).withConst().withRestrict(); + SemaOpenMP::CapturedParamNameType ParamsParallel[] = { + std::make_pair(".global_tid.", KmpInt32PtrTy), + std::make_pair(".bound_tid.", KmpInt32PtrTy), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + // Start a captured region for 'parallel'. + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, ParamsParallel, + /*OpenMPCaptureLevel=*/0); + QualType Args[] = {VoidPtrTy}; + FunctionProtoType::ExtProtoInfo EPI; + EPI.Variadic = true; + QualType CopyFnType = Context.getFunctionType(Context.VoidTy, Args, EPI); + SemaOpenMP::CapturedParamNameType Params[] = { + std::make_pair(".global_tid.", KmpInt32Ty), + std::make_pair(".part_id.", KmpInt32PtrTy), + std::make_pair(".privates.", VoidPtrTy), + std::make_pair( + ".copy_fn.", + Context.getPointerType(CopyFnType).withConst().withRestrict()), + std::make_pair(".task_t.", Context.VoidPtrTy.withConst()), + std::make_pair(".lb.", KmpUInt64Ty), + std::make_pair(".ub.", KmpUInt64Ty), + std::make_pair(".st.", KmpInt64Ty), + std::make_pair(".liter.", KmpInt32Ty), + std::make_pair(".reductions.", VoidPtrTy), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, Params, + /*OpenMPCaptureLevel=*/1); + // Mark this captured region as inlined, because we don't use outlined + // function directly. + SemaRef.getCurCapturedRegion()->TheCapturedDecl->addAttr( + AlwaysInlineAttr::CreateImplicit( + Context, {}, AlwaysInlineAttr::Keyword_forceinline)); + break; + } + case OMPD_distribute_parallel_for_simd: + case OMPD_distribute_parallel_for: { + QualType KmpInt32Ty = Context.getIntTypeForBitwidth(32, 1).withConst(); + QualType KmpInt32PtrTy = + Context.getPointerType(KmpInt32Ty).withConst().withRestrict(); + SemaOpenMP::CapturedParamNameType Params[] = { + std::make_pair(".global_tid.", KmpInt32PtrTy), + std::make_pair(".bound_tid.", KmpInt32PtrTy), + std::make_pair(".previous.lb.", Context.getSizeType().withConst()), + std::make_pair(".previous.ub.", Context.getSizeType().withConst()), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, Params); + break; + } + // For 'target teams loop', collect all captured regions so codegen can + // later decide the best IR to emit given the associated loop-nest. + case OMPD_target_teams_loop: + case OMPD_target_teams_distribute_parallel_for: + case OMPD_target_teams_distribute_parallel_for_simd: { + QualType KmpInt32Ty = Context.getIntTypeForBitwidth(32, 1).withConst(); + QualType KmpInt32PtrTy = + Context.getPointerType(KmpInt32Ty).withConst().withRestrict(); + QualType VoidPtrTy = Context.VoidPtrTy.withConst().withRestrict(); + + QualType Args[] = {VoidPtrTy}; + FunctionProtoType::ExtProtoInfo EPI; + EPI.Variadic = true; + QualType CopyFnType = Context.getFunctionType(Context.VoidTy, Args, EPI); + SemaOpenMP::CapturedParamNameType Params[] = { + std::make_pair(".global_tid.", KmpInt32Ty), + std::make_pair(".part_id.", KmpInt32PtrTy), + std::make_pair(".privates.", VoidPtrTy), + std::make_pair( + ".copy_fn.", + Context.getPointerType(CopyFnType).withConst().withRestrict()), + std::make_pair(".task_t.", Context.VoidPtrTy.withConst()), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, Params, + /*OpenMPCaptureLevel=*/0); + // Mark this captured region as inlined, because we don't use outlined + // function directly. + SemaRef.getCurCapturedRegion()->TheCapturedDecl->addAttr( + AlwaysInlineAttr::CreateImplicit( + Context, {}, AlwaysInlineAttr::Keyword_forceinline)); + SmallVector ParamsTarget; + if (getLangOpts().OpenMPIsTargetDevice) + ParamsTarget.push_back(std::make_pair(StringRef("dyn_ptr"), VoidPtrTy)); + ParamsTarget.push_back( + std::make_pair(StringRef(), QualType())); // __context with shared vars; + // Start a captured region for 'target' with no implicit parameters. + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, ParamsTarget, + /*OpenMPCaptureLevel=*/1); + + SemaOpenMP::CapturedParamNameType ParamsTeams[] = { + std::make_pair(".global_tid.", KmpInt32PtrTy), + std::make_pair(".bound_tid.", KmpInt32PtrTy), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + // Start a captured region for 'target' with no implicit parameters. + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, ParamsTeams, + /*OpenMPCaptureLevel=*/2); + + SemaOpenMP::CapturedParamNameType ParamsParallel[] = { + std::make_pair(".global_tid.", KmpInt32PtrTy), + std::make_pair(".bound_tid.", KmpInt32PtrTy), + std::make_pair(".previous.lb.", Context.getSizeType().withConst()), + std::make_pair(".previous.ub.", Context.getSizeType().withConst()), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + // Start a captured region for 'teams' or 'parallel'. Both regions have + // the same implicit parameters. + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, ParamsParallel, + /*OpenMPCaptureLevel=*/3); + break; + } + + case OMPD_teams_distribute_parallel_for: + case OMPD_teams_distribute_parallel_for_simd: { + QualType KmpInt32Ty = Context.getIntTypeForBitwidth(32, 1).withConst(); + QualType KmpInt32PtrTy = + Context.getPointerType(KmpInt32Ty).withConst().withRestrict(); + + SemaOpenMP::CapturedParamNameType ParamsTeams[] = { + std::make_pair(".global_tid.", KmpInt32PtrTy), + std::make_pair(".bound_tid.", KmpInt32PtrTy), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + // Start a captured region for 'target' with no implicit parameters. + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, ParamsTeams, + /*OpenMPCaptureLevel=*/0); + + SemaOpenMP::CapturedParamNameType ParamsParallel[] = { + std::make_pair(".global_tid.", KmpInt32PtrTy), + std::make_pair(".bound_tid.", KmpInt32PtrTy), + std::make_pair(".previous.lb.", Context.getSizeType().withConst()), + std::make_pair(".previous.ub.", Context.getSizeType().withConst()), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + // Start a captured region for 'teams' or 'parallel'. Both regions have + // the same implicit parameters. + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, ParamsParallel, + /*OpenMPCaptureLevel=*/1); + break; + } + case OMPD_target_update: + case OMPD_target_enter_data: + case OMPD_target_exit_data: { + QualType KmpInt32Ty = Context.getIntTypeForBitwidth(32, 1).withConst(); + QualType VoidPtrTy = Context.VoidPtrTy.withConst().withRestrict(); + QualType KmpInt32PtrTy = + Context.getPointerType(KmpInt32Ty).withConst().withRestrict(); + QualType Args[] = {VoidPtrTy}; + FunctionProtoType::ExtProtoInfo EPI; + EPI.Variadic = true; + QualType CopyFnType = Context.getFunctionType(Context.VoidTy, Args, EPI); + SemaOpenMP::CapturedParamNameType Params[] = { + std::make_pair(".global_tid.", KmpInt32Ty), + std::make_pair(".part_id.", KmpInt32PtrTy), + std::make_pair(".privates.", VoidPtrTy), + std::make_pair( + ".copy_fn.", + Context.getPointerType(CopyFnType).withConst().withRestrict()), + std::make_pair(".task_t.", Context.VoidPtrTy.withConst()), + std::make_pair(StringRef(), QualType()) // __context with shared vars + }; + SemaRef.ActOnCapturedRegionStart(DSAStack->getConstructLoc(), CurScope, + CR_OpenMP, Params); + // Mark this captured region as inlined, because we don't use outlined + // function directly. + SemaRef.getCurCapturedRegion()->TheCapturedDecl->addAttr( + AlwaysInlineAttr::CreateImplicit( + Context, {}, AlwaysInlineAttr::Keyword_forceinline)); + break; + } + case OMPD_threadprivate: + case OMPD_allocate: + case OMPD_taskyield: + case OMPD_error: + case OMPD_barrier: + case OMPD_taskwait: + case OMPD_cancellation_point: + case OMPD_cancel: + case OMPD_flush: + case OMPD_depobj: + case OMPD_scan: + case OMPD_declare_reduction: + case OMPD_declare_mapper: + case OMPD_declare_simd: + case OMPD_declare_target: + case OMPD_end_declare_target: + case OMPD_requires: + case OMPD_declare_variant: + case OMPD_begin_declare_variant: + case OMPD_end_declare_variant: + case OMPD_metadirective: + llvm_unreachable("OpenMP Directive is not allowed"); + case OMPD_unknown: default: processCapturedRegions(SemaRef, DKind, CurScope, DSAStack->getConstructLoc()); @@ -5152,12 +5584,23 @@ static bool checkNestingOfRegions(Sema &SemaRef, const DSAStackTy *Stack, Recommend = ShouldBeInTargetRegion; } else if (CurrentRegion == OMPD_scan) { if (OMPVersion >= 50) { + // Make sure that one of the flags - '-fopenmp-target-xteam-scan' or + // '-fopenmp-target-xteam-no-loop-scan' flag is passed to enable the + // Xteam-Scan Codegen, if the 'scan' directive is found to be nested + // inside the 'target teams distribute parallel for' directive + if (ParentRegion == OMPD_target_teams_distribute_parallel_for && + !(SemaRef.getLangOpts().OpenMPTargetXteamScan || + SemaRef.getLangOpts().OpenMPTargetXteamNoLoopScan)) + SemaRef.Diag(StartLoc, diag::err_omp_xteam_scan_prohibited) + << getOpenMPDirectiveName(CurrentRegion) << Recommend; // OpenMP spec 5.0 and 5.1 require scan to be directly enclosed by for, // simd, or for simd. This has to take into account combined directives. // In 5.2 this seems to be implied by the fact that the specified // separated constructs are do, for, and simd. - NestingProhibited = !llvm::is_contained( - {OMPD_for, OMPD_simd, OMPD_for_simd}, EnclosingConstruct); + NestingProhibited = + !llvm::is_contained({OMPD_for, OMPD_simd, OMPD_for_simd}, + EnclosingConstruct) && + ParentRegion != OMPD_target_teams_distribute_parallel_for; } else { NestingProhibited = true; } @@ -20691,7 +21134,9 @@ OMPClause *SemaOpenMP::ActOnOpenMPReductionClause( DSAStack->getCurrentDirective() != OMPD_for_simd && DSAStack->getCurrentDirective() != OMPD_simd && DSAStack->getCurrentDirective() != OMPD_parallel_for && - DSAStack->getCurrentDirective() != OMPD_parallel_for_simd)) { + DSAStack->getCurrentDirective() != OMPD_parallel_for_simd && + DSAStack->getCurrentDirective() != + OMPD_target_teams_distribute_parallel_for)) { Diag(ModifierLoc, diag::err_omp_wrong_inscan_reduction); return nullptr; } @@ -24915,6 +25360,11 @@ OMPClause *SemaOpenMP::ActOnOpenMPInclusiveClause(ArrayRef VarList, Expr *SimpleRefExpr = RefExpr; auto Res = getPrivateItem(SemaRef, SimpleRefExpr, ELoc, ERange, /*AllowArraySection=*/true); + if (!Vars.empty() && DSAStack->getParentDirective() == + OMPD_target_teams_distribute_parallel_for) { + Diag(ELoc, diag::err_omp_multivar_xteam_scan_unsupported) + << RefExpr->getSourceRange(); + } if (Res.second) // It will be analyzed later. Vars.push_back(RefExpr); @@ -24956,6 +25406,11 @@ OMPClause *SemaOpenMP::ActOnOpenMPExclusiveClause(ArrayRef VarList, Expr *SimpleRefExpr = RefExpr; auto Res = getPrivateItem(SemaRef, SimpleRefExpr, ELoc, ERange, /*AllowArraySection=*/true); + if (!Vars.empty() && DSAStack->getParentDirective() == + OMPD_target_teams_distribute_parallel_for) { + Diag(ELoc, diag::err_omp_multivar_xteam_scan_unsupported) + << RefExpr->getSourceRange(); + } if (Res.second) // It will be analyzed later. Vars.push_back(RefExpr); diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 37f351174e3d0..6d011239ec813 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -30,6 +30,7 @@ #include "clang/Sema/Initialization.h" #include "clang/Sema/Lookup.h" #include "clang/Sema/Overload.h" +#include "clang/Sema/SemaAMDGPU.h" #include "clang/Sema/SemaARM.h" #include "clang/Sema/SemaCUDA.h" #include "clang/Sema/SemaObjC.h" @@ -6172,12 +6173,13 @@ TryContextuallyConvertToBool(Sema &S, Expr *From) { ExprResult Sema::PerformContextuallyConvertToBool(Expr *From) { if (checkPlaceholderForOverload(*this, From)) return ExprError(); + if (From->getType() == Context.AMDGPUFeaturePredicateTy) + return AMDGPU().ExpandAMDGPUPredicateBI(dyn_cast(From)); ImplicitConversionSequence ICS = TryContextuallyConvertToBool(*this, From); if (!ICS.isBad()) return PerformImplicitConversion(From, Context.BoolTy, ICS, AssignmentAction::Converting); - if (!DiagnoseMultipleUserDefinedConversion(From, Context.BoolTy)) return Diag(From->getBeginLoc(), diag::err_typecheck_bool_condition) << From->getType() << From->getSourceRange(); @@ -11996,6 +11998,16 @@ static void DiagnoseBadConversion(Sema &S, OverloadCandidate *Cand, if (TakingCandidateAddress && !checkAddressOfCandidateIsAvailable(S, Fn)) return; + // __amdgpu_feature_predicate_t can be explicitly cast to the logical op type, + // although this is almost always an error and we advise against it. + if (FromTy == S.Context.AMDGPUFeaturePredicateTy && + ToTy == S.Context.getLogicalOperationType()) { + S.Diag(Conv.Bad.FromExpr->getExprLoc(), + diag::err_amdgcn_predicate_type_needs_explicit_bool_cast) + << Conv.Bad.FromExpr << ToTy; + return; + } + // Emit the generic diagnostic and, optionally, add the hints to it. PartialDiagnostic FDiag = S.PDiag(diag::note_ovl_candidate_bad_conv); FDiag << (unsigned)FnKindPair.first << (unsigned)FnKindPair.second << FnDesc diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_10.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_10.c index 07274ec67ef40..b25e04a81ba1c 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_10.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_10.c @@ -21,7 +21,7 @@ int also_before4(void) { return 4; } -#pragma omp begin declare variant match(implementation = {vendor(llvm)}) +#pragma omp begin declare variant match(implementation = {vendor(amd)}) CONST int also_before1(void) { return 0; } @@ -50,41 +50,41 @@ int main(void) { // C-NEXT: | |-CompoundStmt [[ADDR_1:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 1 -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before1[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before1[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] line:14:5 used also_before2 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_8:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_9:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_10:0x[a-z0-9]*]] 'int' 2 -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_11:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_12:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_13:0x[a-z0-9]*]] 'also_before2[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_11:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_12:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_13:0x[a-z0-9]*]] 'also_before2[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: |-FunctionDecl [[ADDR_14:0x[a-z0-9]*]] line:17:5 used also_before3 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_15:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_16:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_17:0x[a-z0-9]*]] 'int' 3 -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_18:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_19:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_20:0x[a-z0-9]*]] 'also_before3[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_18:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_19:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_20:0x[a-z0-9]*]] 'also_before3[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: |-FunctionDecl [[ADDR_21:0x[a-z0-9]*]] line:20:5 used also_before4 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_22:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_23:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_24:0x[a-z0-9]*]] 'int' 4 -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_25:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_26:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_27:0x[a-z0-9]*]] 'also_before4[implementation={vendor(llvm)}]' 'int ({{.*}})' -// C-NEXT: |-FunctionDecl [[ADDR_6]] line:8:15 also_before1[implementation={vendor(llvm)}] 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_25:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_26:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_27:0x[a-z0-9]*]] 'also_before4[implementation={vendor(amd)}]' 'int ({{.*}})' +// C-NEXT: |-FunctionDecl [[ADDR_6]] line:8:15 also_before1[implementation={vendor(amd)}] 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_28:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_29:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_30:0x[a-z0-9]*]] 'int' 0 // C-NEXT: | `-ConstAttr [[ADDR_31:0x[a-z0-9]*]] -// C-NEXT: |-FunctionDecl [[ADDR_13]] line:28:1 also_before2[implementation={vendor(llvm)}] 'int ({{.*}})' static +// C-NEXT: |-FunctionDecl [[ADDR_13]] line:28:1 also_before2[implementation={vendor(amd)}] 'int ({{.*}})' static // C-NEXT: | `-CompoundStmt [[ADDR_32:0x[a-z0-9]*]] // C-NEXT: | `-ReturnStmt [[ADDR_33:0x[a-z0-9]*]] // C-NEXT: | `-IntegerLiteral [[ADDR_34:0x[a-z0-9]*]] 'int' 0 -// C-NEXT: |-FunctionDecl [[ADDR_20]] line:31:1 also_before3[implementation={vendor(llvm)}] 'int ({{.*}})' +// C-NEXT: |-FunctionDecl [[ADDR_20]] line:31:1 also_before3[implementation={vendor(amd)}] 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_35:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_36:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_37:0x[a-z0-9]*]] 'int' 0 // C-NEXT: | `-NoThrowAttr [[ADDR_38:0x[a-z0-9]*]] -// C-NEXT: |-FunctionDecl [[ADDR_27]] line:34:1 also_before4[implementation={vendor(llvm)}] 'int ({{.*}})' static inline +// C-NEXT: |-FunctionDecl [[ADDR_27]] line:34:1 also_before4[implementation={vendor(amd)}] 'int ({{.*}})' static inline // C-NEXT: | |-CompoundStmt [[ADDR_39:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_40:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_41:0x[a-z0-9]*]] 'int' 0 @@ -103,66 +103,66 @@ int main(void) { // C-NEXT: | | | | `-DeclRefExpr [[ADDR_54:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_0]] 'also_before1' 'int ({{.*}})' // C-NEXT: | | | `-CallExpr [[ADDR_55:0x[a-z0-9]*]] 'int' // C-NEXT: | | | `-ImplicitCastExpr [[ADDR_56:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: | | | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before1[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | | | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before1[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: | | `-PseudoObjectExpr [[ADDR_57:0x[a-z0-9]*]] 'int' // C-NEXT: | | |-CallExpr [[ADDR_58:0x[a-z0-9]*]] 'int' // C-NEXT: | | | `-ImplicitCastExpr [[ADDR_59:0x[a-z0-9]*]] 'int (*)({{.*}})' // C-NEXT: | | | `-DeclRefExpr [[ADDR_60:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_7]] 'also_before2' 'int ({{.*}})' // C-NEXT: | | `-CallExpr [[ADDR_61:0x[a-z0-9]*]] 'int' // C-NEXT: | | `-ImplicitCastExpr [[ADDR_62:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: | | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_before2[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_before2[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: | `-PseudoObjectExpr [[ADDR_63:0x[a-z0-9]*]] 'int' // C-NEXT: | |-CallExpr [[ADDR_64:0x[a-z0-9]*]] 'int' // C-NEXT: | | `-ImplicitCastExpr [[ADDR_65:0x[a-z0-9]*]] 'int (*)({{.*}})' // C-NEXT: | | `-DeclRefExpr [[ADDR_66:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_14]] 'also_before3' 'int ({{.*}})' // C-NEXT: | `-CallExpr [[ADDR_67:0x[a-z0-9]*]] 'int' // C-NEXT: | `-ImplicitCastExpr [[ADDR_68:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}})' Function [[ADDR_20]] 'also_before3[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}})' Function [[ADDR_20]] 'also_before3[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: `-PseudoObjectExpr [[ADDR_69:0x[a-z0-9]*]] 'int' // C-NEXT: |-CallExpr [[ADDR_70:0x[a-z0-9]*]] 'int' // C-NEXT: | `-ImplicitCastExpr [[ADDR_71:0x[a-z0-9]*]] 'int (*)({{.*}})' // C-NEXT: | `-DeclRefExpr [[ADDR_72:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_21]] 'also_before4' 'int ({{.*}})' // C-NEXT: `-CallExpr [[ADDR_73:0x[a-z0-9]*]] 'int' // C-NEXT: `-ImplicitCastExpr [[ADDR_74:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: `-DeclRefExpr [[ADDR_26]] 'int ({{.*}})' Function [[ADDR_27]] 'also_before4[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: `-DeclRefExpr [[ADDR_26]] 'int ({{.*}})' Function [[ADDR_27]] 'also_before4[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX: |-FunctionDecl [[ADDR_0:0x[a-z0-9]*]] <{{.*}}, line:13:1> line:11:5 used also_before1 'int ({{.*}})' // CXX-NEXT: | |-CompoundStmt [[ADDR_1:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 1 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before1[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before1[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] line:14:5 used also_before2 'int ({{.*}})' // CXX-NEXT: | |-CompoundStmt [[ADDR_8:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_9:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_10:0x[a-z0-9]*]] 'int' 2 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_11:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_12:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_13:0x[a-z0-9]*]] 'also_before2[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_11:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_12:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_13:0x[a-z0-9]*]] 'also_before2[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: |-FunctionDecl [[ADDR_14:0x[a-z0-9]*]] line:17:5 used also_before3 'int ({{.*}})' // CXX-NEXT: | |-CompoundStmt [[ADDR_15:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_16:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_17:0x[a-z0-9]*]] 'int' 3 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_18:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_19:0x[a-z0-9]*]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_20:0x[a-z0-9]*]] 'also_before3[implementation={vendor(llvm)}]' 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_18:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_19:0x[a-z0-9]*]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_20:0x[a-z0-9]*]] 'also_before3[implementation={vendor(amd)}]' 'int ({{.*}}) __attribute__((nothrow))' // CXX-NEXT: |-FunctionDecl [[ADDR_21:0x[a-z0-9]*]] line:20:5 used also_before4 'int ({{.*}})' // CXX-NEXT: | |-CompoundStmt [[ADDR_22:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_23:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_24:0x[a-z0-9]*]] 'int' 4 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_25:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_26:0x[a-z0-9]*]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_27:0x[a-z0-9]*]] 'also_before4[implementation={vendor(llvm)}]' 'int ({{.*}}) __attribute__((nothrow))' -// CXX-NEXT: |-FunctionDecl [[ADDR_6]] line:6:15 constexpr also_before1[implementation={vendor(llvm)}] 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_25:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_26:0x[a-z0-9]*]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_27:0x[a-z0-9]*]] 'also_before4[implementation={vendor(amd)}]' 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: |-FunctionDecl [[ADDR_6]] line:6:15 constexpr also_before1[implementation={vendor(amd)}] 'int ({{.*}})' // CXX-NEXT: | `-CompoundStmt [[ADDR_28:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_29:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_30:0x[a-z0-9]*]] 'int' 0 -// CXX-NEXT: |-FunctionDecl [[ADDR_13]] line:28:1 also_before2[implementation={vendor(llvm)}] 'int ({{.*}})' static +// CXX-NEXT: |-FunctionDecl [[ADDR_13]] line:28:1 also_before2[implementation={vendor(amd)}] 'int ({{.*}})' static // CXX-NEXT: | `-CompoundStmt [[ADDR_31:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_32:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_33:0x[a-z0-9]*]] 'int' 0 -// CXX-NEXT: |-FunctionDecl [[ADDR_20]] line:31:1 also_before3[implementation={vendor(llvm)}] 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: |-FunctionDecl [[ADDR_20]] line:31:1 also_before3[implementation={vendor(amd)}] 'int ({{.*}}) __attribute__((nothrow))' // CXX-NEXT: | `-CompoundStmt [[ADDR_34:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_35:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_36:0x[a-z0-9]*]] 'int' 0 -// CXX-NEXT: |-FunctionDecl [[ADDR_27]] line:34:1 constexpr also_before4[implementation={vendor(llvm)}] 'int ({{.*}}) __attribute__((nothrow))' static inline +// CXX-NEXT: |-FunctionDecl [[ADDR_27]] line:34:1 constexpr also_before4[implementation={vendor(amd)}] 'int ({{.*}}) __attribute__((nothrow))' static inline // CXX-NEXT: | |-CompoundStmt [[ADDR_37:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_38:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_39:0x[a-z0-9]*]] 'int' 0 @@ -179,25 +179,25 @@ int main(void) { // CXX-NEXT: | | | | `-DeclRefExpr [[ADDR_50:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_0]] 'also_before1' 'int ({{.*}})' // CXX-NEXT: | | | `-CallExpr [[ADDR_51:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | | `-ImplicitCastExpr [[ADDR_52:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CXX-NEXT: | | | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before1[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | | | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before1[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: | | `-PseudoObjectExpr [[ADDR_53:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | |-CallExpr [[ADDR_54:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | | `-ImplicitCastExpr [[ADDR_55:0x[a-z0-9]*]] 'int (*)({{.*}})' // CXX-NEXT: | | | `-DeclRefExpr [[ADDR_56:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_7]] 'also_before2' 'int ({{.*}})' // CXX-NEXT: | | `-CallExpr [[ADDR_57:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | `-ImplicitCastExpr [[ADDR_58:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CXX-NEXT: | | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_before2[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_before2[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: | `-PseudoObjectExpr [[ADDR_59:0x[a-z0-9]*]] 'int' // CXX-NEXT: | |-CallExpr [[ADDR_60:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | `-ImplicitCastExpr [[ADDR_61:0x[a-z0-9]*]] 'int (*)({{.*}})' // CXX-NEXT: | | `-DeclRefExpr [[ADDR_62:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_14]] 'also_before3' 'int ({{.*}})' // CXX-NEXT: | `-CallExpr [[ADDR_63:0x[a-z0-9]*]] 'int' // CXX-NEXT: | `-ImplicitCastExpr [[ADDR_64:0x[a-z0-9]*]] 'int (*)({{.*}}) __attribute__((nothrow))' -// CXX-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_20]] 'also_before3[implementation={vendor(llvm)}]' 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_20]] 'also_before3[implementation={vendor(amd)}]' 'int ({{.*}}) __attribute__((nothrow))' // CXX-NEXT: `-PseudoObjectExpr [[ADDR_65:0x[a-z0-9]*]] 'int' // CXX-NEXT: |-CallExpr [[ADDR_66:0x[a-z0-9]*]] 'int' // CXX-NEXT: | `-ImplicitCastExpr [[ADDR_67:0x[a-z0-9]*]] 'int (*)({{.*}})' // CXX-NEXT: | `-DeclRefExpr [[ADDR_68:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_21]] 'also_before4' 'int ({{.*}})' // CXX-NEXT: `-CallExpr [[ADDR_69:0x[a-z0-9]*]] 'int' // CXX-NEXT: `-ImplicitCastExpr [[ADDR_70:0x[a-z0-9]*]] 'int (*)({{.*}}) __attribute__((nothrow))' -// CXX-NEXT: `-DeclRefExpr [[ADDR_26]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_27]] 'also_before4[implementation={vendor(llvm)}]' 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: `-DeclRefExpr [[ADDR_26]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_27]] 'also_before4[implementation={vendor(amd)}]' 'int ({{.*}}) __attribute__((nothrow))' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_11.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_11.c index 4c99f3311d8c3..5e841a0d374de 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_11.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_11.c @@ -9,7 +9,7 @@ #define CONST __attribute__((const)) #endif -#pragma omp begin declare variant match(implementation = {vendor(llvm)}) +#pragma omp begin declare variant match(implementation = {vendor(amd)}) CONST int also_after1(void) { // cxx_mode-note {{previous declaration is here}} return 0; } @@ -49,25 +49,25 @@ int main(void) { // C: |-FunctionDecl [[ADDR_0:0x[a-z0-9]*]] <{{.*}}, line:13:27> col:11 implicit used also_after1 'int ({{.*}})' // C-NEXT: | |-ConstAttr [[ADDR_1:0x[a-z0-9]*]] -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_2:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_3:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_4:0x[a-z0-9]*]] 'also_after1[implementation={vendor(llvm)}]' 'int ({{.*}})' -// C-NEXT: |-FunctionDecl [[ADDR_4]] line:9:15 also_after1[implementation={vendor(llvm)}] 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_2:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_3:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_4:0x[a-z0-9]*]] 'also_after1[implementation={vendor(amd)}]' 'int ({{.*}})' +// C-NEXT: |-FunctionDecl [[ADDR_4]] line:9:15 also_after1[implementation={vendor(amd)}] 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_5:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_6:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_7:0x[a-z0-9]*]] 'int' 0 // C-NEXT: | `-ConstAttr [[ADDR_8:0x[a-z0-9]*]] // C-NEXT: |-FunctionDecl [[ADDR_9:0x[a-z0-9]*]] col:12 implicit used also_after2 'int ({{.*}})' static -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_10:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_11:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_12:0x[a-z0-9]*]] 'also_after2[implementation={vendor(llvm)}]' 'int ({{.*}})' -// C-NEXT: |-FunctionDecl [[ADDR_12]] line:16:1 also_after2[implementation={vendor(llvm)}] 'int ({{.*}})' static +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_10:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_11:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_12:0x[a-z0-9]*]] 'also_after2[implementation={vendor(amd)}]' 'int ({{.*}})' +// C-NEXT: |-FunctionDecl [[ADDR_12]] line:16:1 also_after2[implementation={vendor(amd)}] 'int ({{.*}})' static // C-NEXT: | `-CompoundStmt [[ADDR_13:0x[a-z0-9]*]] // C-NEXT: | `-ReturnStmt [[ADDR_14:0x[a-z0-9]*]] // C-NEXT: | `-IntegerLiteral [[ADDR_15:0x[a-z0-9]*]] 'int' 0 // C-NEXT: |-FunctionDecl [[ADDR_16:0x[a-z0-9]*]] col:30 implicit used also_after3 'int ({{.*}})' // C-NEXT: | |-NoThrowAttr [[ADDR_17:0x[a-z0-9]*]] -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_18:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_19:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_20:0x[a-z0-9]*]] 'also_after3[implementation={vendor(llvm)}]' 'int ({{.*}})' -// C-NEXT: |-FunctionDecl [[ADDR_20]] line:19:1 also_after3[implementation={vendor(llvm)}] 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_18:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_19:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_20:0x[a-z0-9]*]] 'also_after3[implementation={vendor(amd)}]' 'int ({{.*}})' +// C-NEXT: |-FunctionDecl [[ADDR_20]] line:19:1 also_after3[implementation={vendor(amd)}] 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_21:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_22:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_23:0x[a-z0-9]*]] 'int' 0 @@ -76,9 +76,9 @@ int main(void) { // C-NEXT: | |-ConstAttr [[ADDR_26:0x[a-z0-9]*]] // C-NEXT: | |-NoThrowAttr [[ADDR_27:0x[a-z0-9]*]] // C-NEXT: | |-AlwaysInlineAttr [[ADDR_28:0x[a-z0-9]*]] always_inline -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_29:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_30:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_31:0x[a-z0-9]*]] 'also_after4[implementation={vendor(llvm)}]' 'int ({{.*}})' -// C-NEXT: |-FunctionDecl [[ADDR_31]] line:22:1 also_after4[implementation={vendor(llvm)}] 'int ({{.*}})' static inline +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_29:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_30:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_31:0x[a-z0-9]*]] 'also_after4[implementation={vendor(amd)}]' 'int ({{.*}})' +// C-NEXT: |-FunctionDecl [[ADDR_31]] line:22:1 also_after4[implementation={vendor(amd)}] 'int ({{.*}})' static inline // C-NEXT: | |-CompoundStmt [[ADDR_32:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_33:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_34:0x[a-z0-9]*]] 'int' 0 @@ -90,21 +90,21 @@ int main(void) { // C-NEXT: | | `-ReturnStmt [[ADDR_40:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_41:0x[a-z0-9]*]] 'int' 1 // C-NEXT: | |-ConstAttr [[ADDR_42:0x[a-z0-9]*]] Inherited -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_43:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_3]] 'int ({{.*}})' Function [[ADDR_4]] 'also_after1[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_43:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_3]] 'int ({{.*}})' Function [[ADDR_4]] 'also_after1[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: |-FunctionDecl [[ADDR_44:0x[a-z0-9]*]] prev [[ADDR_9]] line:30:5 used also_after2 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_45:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_46:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_47:0x[a-z0-9]*]] 'int' 2 -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_48:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_11]] 'int ({{.*}})' Function [[ADDR_12]] 'also_after2[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_48:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_11]] 'int ({{.*}})' Function [[ADDR_12]] 'also_after2[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: |-FunctionDecl [[ADDR_49:0x[a-z0-9]*]] prev [[ADDR_16]] line:33:5 used also_after3 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_50:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_51:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_52:0x[a-z0-9]*]] 'int' 3 // C-NEXT: | |-NoThrowAttr [[ADDR_53:0x[a-z0-9]*]] Inherited -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_54:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}})' Function [[ADDR_20]] 'also_after3[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_54:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}})' Function [[ADDR_20]] 'also_after3[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: |-FunctionDecl [[ADDR_55:0x[a-z0-9]*]] prev [[ADDR_25]] line:36:5 used also_after4 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_56:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_57:0x[a-z0-9]*]] @@ -112,8 +112,8 @@ int main(void) { // C-NEXT: | |-ConstAttr [[ADDR_59:0x[a-z0-9]*]] Inherited // C-NEXT: | |-NoThrowAttr [[ADDR_60:0x[a-z0-9]*]] Inherited // C-NEXT: | |-AlwaysInlineAttr [[ADDR_61:0x[a-z0-9]*]] Inherited always_inline -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_62:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_30]] 'int ({{.*}})' Function [[ADDR_31]] 'also_after4[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_62:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_30]] 'int ({{.*}})' Function [[ADDR_31]] 'also_after4[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: `-FunctionDecl [[ADDR_63:0x[a-z0-9]*]] line:41:5 main 'int ({{.*}})' // C-NEXT: `-CompoundStmt [[ADDR_64:0x[a-z0-9]*]] // C-NEXT: `-ReturnStmt [[ADDR_65:0x[a-z0-9]*]] @@ -126,55 +126,55 @@ int main(void) { // C-NEXT: | | | | `-DeclRefExpr [[ADDR_72:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_38]] 'also_after1' 'int ({{.*}})' // C-NEXT: | | | `-CallExpr [[ADDR_73:0x[a-z0-9]*]] 'int' // C-NEXT: | | | `-ImplicitCastExpr [[ADDR_74:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: | | | `-DeclRefExpr [[ADDR_3]] 'int ({{.*}})' Function [[ADDR_4]] 'also_after1[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | | | `-DeclRefExpr [[ADDR_3]] 'int ({{.*}})' Function [[ADDR_4]] 'also_after1[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: | | `-PseudoObjectExpr [[ADDR_75:0x[a-z0-9]*]] 'int' // C-NEXT: | | |-CallExpr [[ADDR_76:0x[a-z0-9]*]] 'int' // C-NEXT: | | | `-ImplicitCastExpr [[ADDR_77:0x[a-z0-9]*]] 'int (*)({{.*}})' // C-NEXT: | | | `-DeclRefExpr [[ADDR_78:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_44]] 'also_after2' 'int ({{.*}})' // C-NEXT: | | `-CallExpr [[ADDR_79:0x[a-z0-9]*]] 'int' // C-NEXT: | | `-ImplicitCastExpr [[ADDR_80:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: | | `-DeclRefExpr [[ADDR_11]] 'int ({{.*}})' Function [[ADDR_12]] 'also_after2[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | | `-DeclRefExpr [[ADDR_11]] 'int ({{.*}})' Function [[ADDR_12]] 'also_after2[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: | `-PseudoObjectExpr [[ADDR_81:0x[a-z0-9]*]] 'int' // C-NEXT: | |-CallExpr [[ADDR_82:0x[a-z0-9]*]] 'int' // C-NEXT: | | `-ImplicitCastExpr [[ADDR_83:0x[a-z0-9]*]] 'int (*)({{.*}})' // C-NEXT: | | `-DeclRefExpr [[ADDR_84:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_49]] 'also_after3' 'int ({{.*}})' // C-NEXT: | `-CallExpr [[ADDR_85:0x[a-z0-9]*]] 'int' // C-NEXT: | `-ImplicitCastExpr [[ADDR_86:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}})' Function [[ADDR_20]] 'also_after3[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}})' Function [[ADDR_20]] 'also_after3[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: `-PseudoObjectExpr [[ADDR_87:0x[a-z0-9]*]] 'int' // C-NEXT: |-CallExpr [[ADDR_88:0x[a-z0-9]*]] 'int' // C-NEXT: | `-ImplicitCastExpr [[ADDR_89:0x[a-z0-9]*]] 'int (*)({{.*}})' // C-NEXT: | `-DeclRefExpr [[ADDR_90:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_55]] 'also_after4' 'int ({{.*}})' // C-NEXT: `-CallExpr [[ADDR_91:0x[a-z0-9]*]] 'int' // C-NEXT: `-ImplicitCastExpr [[ADDR_92:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: `-DeclRefExpr [[ADDR_30]] 'int ({{.*}})' Function [[ADDR_31]] 'also_after4[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: `-DeclRefExpr [[ADDR_30]] 'int ({{.*}})' Function [[ADDR_31]] 'also_after4[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX: |-FunctionDecl [[ADDR_0:0x[a-z0-9]*]] <{{.*}}, line:13:27> col:11 implicit used constexpr also_after1 'int ({{.*}})' -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_1:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_2:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_3:0x[a-z0-9]*]] 'also_after1[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CXX-NEXT: |-FunctionDecl [[ADDR_3]] line:7:15 constexpr also_after1[implementation={vendor(llvm)}] 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_1:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_2:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_3:0x[a-z0-9]*]] 'also_after1[implementation={vendor(amd)}]' 'int ({{.*}})' +// CXX-NEXT: |-FunctionDecl [[ADDR_3]] line:7:15 constexpr also_after1[implementation={vendor(amd)}] 'int ({{.*}})' // CXX-NEXT: | `-CompoundStmt [[ADDR_4:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_5:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_6:0x[a-z0-9]*]] 'int' 0 // CXX-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] col:12 implicit used also_after2 'int ({{.*}})' static -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after2[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CXX-NEXT: |-FunctionDecl [[ADDR_10]] line:16:1 also_after2[implementation={vendor(llvm)}] 'int ({{.*}})' static +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after2[implementation={vendor(amd)}]' 'int ({{.*}})' +// CXX-NEXT: |-FunctionDecl [[ADDR_10]] line:16:1 also_after2[implementation={vendor(amd)}] 'int ({{.*}})' static // CXX-NEXT: | `-CompoundStmt [[ADDR_11:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_12:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_13:0x[a-z0-9]*]] 'int' 0 // CXX-NEXT: |-FunctionDecl [[ADDR_14:0x[a-z0-9]*]] col:30 implicit used also_after3 'int ({{.*}}) __attribute__((nothrow))' -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_15:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_16:0x[a-z0-9]*]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_17:0x[a-z0-9]*]] 'also_after3[implementation={vendor(llvm)}]' 'int ({{.*}}) __attribute__((nothrow))' -// CXX-NEXT: |-FunctionDecl [[ADDR_17]] line:19:1 also_after3[implementation={vendor(llvm)}] 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_15:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_16:0x[a-z0-9]*]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_17:0x[a-z0-9]*]] 'also_after3[implementation={vendor(amd)}]' 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: |-FunctionDecl [[ADDR_17]] line:19:1 also_after3[implementation={vendor(amd)}] 'int ({{.*}}) __attribute__((nothrow))' // CXX-NEXT: | `-CompoundStmt [[ADDR_18:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_19:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_20:0x[a-z0-9]*]] 'int' 0 // CXX-NEXT: |-FunctionDecl [[ADDR_21:0x[a-z0-9]*]] col:69 implicit used constexpr also_after4 'int ({{.*}}) __attribute__((nothrow))' static inline // CXX-NEXT: | |-AlwaysInlineAttr [[ADDR_22:0x[a-z0-9]*]] always_inline -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_23:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_24:0x[a-z0-9]*]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_25:0x[a-z0-9]*]] 'also_after4[implementation={vendor(llvm)}]' 'int ({{.*}}) __attribute__((nothrow))' -// CXX-NEXT: |-FunctionDecl [[ADDR_25]] line:22:1 constexpr also_after4[implementation={vendor(llvm)}] 'int ({{.*}}) __attribute__((nothrow))' static inline +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_23:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_24:0x[a-z0-9]*]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_25:0x[a-z0-9]*]] 'also_after4[implementation={vendor(amd)}]' 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: |-FunctionDecl [[ADDR_25]] line:22:1 constexpr also_after4[implementation={vendor(amd)}] 'int ({{.*}}) __attribute__((nothrow))' static inline // CXX-NEXT: | |-CompoundStmt [[ADDR_26:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_27:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_28:0x[a-z0-9]*]] 'int' 0 @@ -183,27 +183,27 @@ int main(void) { // CXX-NEXT: | |-CompoundStmt [[ADDR_31:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_32:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_33:0x[a-z0-9]*]] 'int' 1 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_34:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_2]] 'int ({{.*}})' Function [[ADDR_3]] 'also_after1[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_34:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_2]] 'int ({{.*}})' Function [[ADDR_3]] 'also_after1[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: |-FunctionDecl [[ADDR_35:0x[a-z0-9]*]] prev [[ADDR_7]] line:30:5 used also_after2 'int ({{.*}})' // CXX-NEXT: | |-CompoundStmt [[ADDR_36:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_37:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_38:0x[a-z0-9]*]] 'int' 2 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_39:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after2[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_39:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after2[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: |-FunctionDecl [[ADDR_40:0x[a-z0-9]*]] prev [[ADDR_14]] line:33:5 used also_after3 'int ({{.*}})' // CXX-NEXT: | |-CompoundStmt [[ADDR_41:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_42:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_43:0x[a-z0-9]*]] 'int' 3 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_44:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_16]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_17]] 'also_after3[implementation={vendor(llvm)}]' 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_44:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_16]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_17]] 'also_after3[implementation={vendor(amd)}]' 'int ({{.*}}) __attribute__((nothrow))' // CXX-NEXT: |-FunctionDecl [[ADDR_45:0x[a-z0-9]*]] line:36:5 invalid also_after4 'int ({{.*}})' // CXX-NEXT: | |-CompoundStmt [[ADDR_46:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_47:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_48:0x[a-z0-9]*]] 'int' 4 // CXX-NEXT: | |-AlwaysInlineAttr [[ADDR_49:0x[a-z0-9]*]] Inherited always_inline -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_50:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_24]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_25]] 'also_after4[implementation={vendor(llvm)}]' 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_50:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_24]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_25]] 'also_after4[implementation={vendor(amd)}]' 'int ({{.*}}) __attribute__((nothrow))' // CXX-NEXT: `-FunctionDecl [[ADDR_51:0x[a-z0-9]*]] line:41:5 main 'int ({{.*}})' // CXX-NEXT: `-CompoundStmt [[ADDR_52:0x[a-z0-9]*]] // CXX-NEXT: `-ReturnStmt [[ADDR_53:0x[a-z0-9]*]] @@ -216,25 +216,25 @@ int main(void) { // CXX-NEXT: | | | | `-DeclRefExpr [[ADDR_60:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_0]] 'also_after1' 'int ({{.*}})' // CXX-NEXT: | | | `-CallExpr [[ADDR_61:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | | `-ImplicitCastExpr [[ADDR_62:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CXX-NEXT: | | | `-DeclRefExpr [[ADDR_2]] 'int ({{.*}})' Function [[ADDR_3]] 'also_after1[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | | | `-DeclRefExpr [[ADDR_2]] 'int ({{.*}})' Function [[ADDR_3]] 'also_after1[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: | | `-PseudoObjectExpr [[ADDR_63:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | |-CallExpr [[ADDR_64:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | | `-ImplicitCastExpr [[ADDR_65:0x[a-z0-9]*]] 'int (*)({{.*}})' // CXX-NEXT: | | | `-DeclRefExpr [[ADDR_66:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_35]] 'also_after2' 'int ({{.*}})' // CXX-NEXT: | | `-CallExpr [[ADDR_67:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | `-ImplicitCastExpr [[ADDR_68:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CXX-NEXT: | | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after2[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after2[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: | `-PseudoObjectExpr [[ADDR_69:0x[a-z0-9]*]] 'int' // CXX-NEXT: | |-CallExpr [[ADDR_70:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | `-ImplicitCastExpr [[ADDR_71:0x[a-z0-9]*]] 'int (*)({{.*}})' // CXX-NEXT: | | `-DeclRefExpr [[ADDR_72:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_40]] 'also_after3' 'int ({{.*}})' // CXX-NEXT: | `-CallExpr [[ADDR_73:0x[a-z0-9]*]] 'int' // CXX-NEXT: | `-ImplicitCastExpr [[ADDR_74:0x[a-z0-9]*]] 'int (*)({{.*}}) __attribute__((nothrow))' -// CXX-NEXT: | `-DeclRefExpr [[ADDR_16]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_17]] 'also_after3[implementation={vendor(llvm)}]' 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: | `-DeclRefExpr [[ADDR_16]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_17]] 'also_after3[implementation={vendor(amd)}]' 'int ({{.*}}) __attribute__((nothrow))' // CXX-NEXT: `-PseudoObjectExpr [[ADDR_75:0x[a-z0-9]*]] 'int' // CXX-NEXT: |-CallExpr [[ADDR_76:0x[a-z0-9]*]] 'int' // CXX-NEXT: | `-ImplicitCastExpr [[ADDR_77:0x[a-z0-9]*]] 'int (*)({{.*}}) __attribute__((nothrow))' // CXX-NEXT: | `-DeclRefExpr [[ADDR_78:0x[a-z0-9]*]] 'int ({{.*}}) __attribute__((nothrow))' {{.*}}Function [[ADDR_21]] 'also_after4' 'int ({{.*}}) __attribute__((nothrow))' // CXX-NEXT: `-CallExpr [[ADDR_79:0x[a-z0-9]*]] 'int' // CXX-NEXT: `-ImplicitCastExpr [[ADDR_80:0x[a-z0-9]*]] 'int (*)({{.*}}) __attribute__((nothrow))' -// CXX-NEXT: `-DeclRefExpr [[ADDR_24]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_25]] 'also_after4[implementation={vendor(llvm)}]' 'int ({{.*}}) __attribute__((nothrow))' +// CXX-NEXT: `-DeclRefExpr [[ADDR_24]] 'int ({{.*}}) __attribute__((nothrow))' Function [[ADDR_25]] 'also_after4[implementation={vendor(amd)}]' 'int ({{.*}}) __attribute__((nothrow))' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_12.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_12.c index 55524e052eda4..0bd18cd3b7898 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_12.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_12.c @@ -29,7 +29,7 @@ int also_before(long l) { return 4; } -#pragma omp begin declare variant match(implementation = {vendor(llvm)}) +#pragma omp begin declare variant match(implementation = {vendor(amd)}) OVERLOADABLE int also_before(void) { return 0; @@ -64,16 +64,16 @@ int main(void) { // C-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 1 // C-NEXT: | |-OverloadableAttr [[ADDR_4:0x[a-z0-9]*]] -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_5:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_6:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_7:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_5:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_6:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_7:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: |-FunctionDecl [[ADDR_8:0x[a-z0-9]*]] line:16:5 used also_before 'int (int)' // C-NEXT: | |-ParmVarDecl [[ADDR_9:0x[a-z0-9]*]] col:21 i 'int' // C-NEXT: | |-CompoundStmt [[ADDR_10:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_11:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_12:0x[a-z0-9]*]] 'int' 2 // C-NEXT: | |-OverloadableAttr [[ADDR_13:0x[a-z0-9]*]] -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_14:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_15:0x[a-z0-9]*]] 'int (int)' Function [[ADDR_16:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int (int)' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_14:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_15:0x[a-z0-9]*]] 'int (int)' Function [[ADDR_16:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int (int)' // C-NEXT: |-FunctionDecl [[ADDR_17:0x[a-z0-9]*]] line:20:5 used also_before 'int (float)' // C-NEXT: | |-ParmVarDecl [[ADDR_18:0x[a-z0-9]*]] col:23 f 'float' // C-NEXT: | |-CompoundStmt [[ADDR_19:0x[a-z0-9]*]] @@ -86,34 +86,34 @@ int main(void) { // C-NEXT: | | `-ReturnStmt [[ADDR_26:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_27:0x[a-z0-9]*]] 'int' 3 // C-NEXT: | |-OverloadableAttr [[ADDR_28:0x[a-z0-9]*]] -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_29:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_30:0x[a-z0-9]*]] 'int (double)' Function [[ADDR_31:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int (double)' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_29:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_30:0x[a-z0-9]*]] 'int (double)' Function [[ADDR_31:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int (double)' // C-NEXT: |-FunctionDecl [[ADDR_32:0x[a-z0-9]*]] line:28:5 used also_before 'int (long)' // C-NEXT: | |-ParmVarDecl [[ADDR_33:0x[a-z0-9]*]] col:22 l 'long' // C-NEXT: | |-CompoundStmt [[ADDR_34:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_35:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_36:0x[a-z0-9]*]] 'int' 4 // C-NEXT: | |-OverloadableAttr [[ADDR_37:0x[a-z0-9]*]] -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_38:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_39:0x[a-z0-9]*]] 'int (long)' Function [[ADDR_40:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int (long)' -// C-NEXT: |-FunctionDecl [[ADDR_7]] line:8:22 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_38:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_39:0x[a-z0-9]*]] 'int (long)' Function [[ADDR_40:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int (long)' +// C-NEXT: |-FunctionDecl [[ADDR_7]] line:8:22 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // C-NEXT: | |-CompoundStmt [[ADDR_41:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_42:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_43:0x[a-z0-9]*]] 'int' 0 // C-NEXT: | `-OverloadableAttr [[ADDR_44:0x[a-z0-9]*]] -// C-NEXT: |-FunctionDecl [[ADDR_16]] line:8:22 also_before[implementation={vendor(llvm)}] 'int (int)' +// C-NEXT: |-FunctionDecl [[ADDR_16]] line:8:22 also_before[implementation={vendor(amd)}] 'int (int)' // C-NEXT: | |-ParmVarDecl [[ADDR_45:0x[a-z0-9]*]] col:21 i 'int' // C-NEXT: | |-CompoundStmt [[ADDR_46:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_47:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_48:0x[a-z0-9]*]] 'int' 0 // C-NEXT: | `-OverloadableAttr [[ADDR_49:0x[a-z0-9]*]] -// C-NEXT: |-FunctionDecl [[ADDR_31]] line:8:22 also_before[implementation={vendor(llvm)}] 'int (double)' +// C-NEXT: |-FunctionDecl [[ADDR_31]] line:8:22 also_before[implementation={vendor(amd)}] 'int (double)' // C-NEXT: | |-ParmVarDecl [[ADDR_50:0x[a-z0-9]*]] col:24 d 'double' // C-NEXT: | |-CompoundStmt [[ADDR_51:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_52:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_53:0x[a-z0-9]*]] 'int' 0 // C-NEXT: | `-OverloadableAttr [[ADDR_54:0x[a-z0-9]*]] -// C-NEXT: |-FunctionDecl [[ADDR_40]] line:8:22 also_before[implementation={vendor(llvm)}] 'int (long)' +// C-NEXT: |-FunctionDecl [[ADDR_40]] line:8:22 also_before[implementation={vendor(amd)}] 'int (long)' // C-NEXT: | |-ParmVarDecl [[ADDR_55:0x[a-z0-9]*]] col:22 l 'long' // C-NEXT: | |-CompoundStmt [[ADDR_56:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_57:0x[a-z0-9]*]] @@ -132,7 +132,7 @@ int main(void) { // C-NEXT: | | | | | `-DeclRefExpr [[ADDR_70:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_0]] 'also_before' 'int ({{.*}})' // C-NEXT: | | | | `-CallExpr [[ADDR_71:0x[a-z0-9]*]] 'int' // C-NEXT: | | | | `-ImplicitCastExpr [[ADDR_72:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: | | | | `-DeclRefExpr [[ADDR_6]] 'int ({{.*}})' Function [[ADDR_7]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | | | | `-DeclRefExpr [[ADDR_6]] 'int ({{.*}})' Function [[ADDR_7]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: | | | `-PseudoObjectExpr [[ADDR_73:0x[a-z0-9]*]] 'int' // C-NEXT: | | | |-CallExpr [[ADDR_74:0x[a-z0-9]*]] 'int' // C-NEXT: | | | | |-ImplicitCastExpr [[ADDR_75:0x[a-z0-9]*]] 'int (*)(int)' @@ -140,7 +140,7 @@ int main(void) { // C-NEXT: | | | | `-IntegerLiteral [[ADDR_77:0x[a-z0-9]*]] 'int' 1 // C-NEXT: | | | `-CallExpr [[ADDR_78:0x[a-z0-9]*]] 'int' // C-NEXT: | | | |-ImplicitCastExpr [[ADDR_79:0x[a-z0-9]*]] 'int (*)(int)' -// C-NEXT: | | | | `-DeclRefExpr [[ADDR_15]] 'int (int)' Function [[ADDR_16]] 'also_before[implementation={vendor(llvm)}]' 'int (int)' +// C-NEXT: | | | | `-DeclRefExpr [[ADDR_15]] 'int (int)' Function [[ADDR_16]] 'also_before[implementation={vendor(amd)}]' 'int (int)' // C-NEXT: | | | `-IntegerLiteral [[ADDR_77]] 'int' 1 // C-NEXT: | | `-CallExpr [[ADDR_80:0x[a-z0-9]*]] 'int' // C-NEXT: | | |-ImplicitCastExpr [[ADDR_81:0x[a-z0-9]*]] 'int (*)(float)' @@ -153,7 +153,7 @@ int main(void) { // C-NEXT: | | `-FloatingLiteral [[ADDR_88:0x[a-z0-9]*]] 'double' 3.000000e+00 // C-NEXT: | `-CallExpr [[ADDR_89:0x[a-z0-9]*]] 'int' // C-NEXT: | |-ImplicitCastExpr [[ADDR_90:0x[a-z0-9]*]] 'int (*)(double)' -// C-NEXT: | | `-DeclRefExpr [[ADDR_30]] 'int (double)' Function [[ADDR_31]] 'also_before[implementation={vendor(llvm)}]' 'int (double)' +// C-NEXT: | | `-DeclRefExpr [[ADDR_30]] 'int (double)' Function [[ADDR_31]] 'also_before[implementation={vendor(amd)}]' 'int (double)' // C-NEXT: | `-FloatingLiteral [[ADDR_88]] 'double' 3.000000e+00 // C-NEXT: `-PseudoObjectExpr [[ADDR_91:0x[a-z0-9]*]] 'int' // C-NEXT: |-CallExpr [[ADDR_92:0x[a-z0-9]*]] 'int' @@ -162,22 +162,22 @@ int main(void) { // C-NEXT: | `-IntegerLiteral [[ADDR_95:0x[a-z0-9]*]] 'long' 4 // C-NEXT: `-CallExpr [[ADDR_96:0x[a-z0-9]*]] 'int' // C-NEXT: |-ImplicitCastExpr [[ADDR_97:0x[a-z0-9]*]] 'int (*)(long)' -// C-NEXT: | `-DeclRefExpr [[ADDR_39]] 'int (long)' Function [[ADDR_40]] 'also_before[implementation={vendor(llvm)}]' 'int (long)' +// C-NEXT: | `-DeclRefExpr [[ADDR_39]] 'int (long)' Function [[ADDR_40]] 'also_before[implementation={vendor(amd)}]' 'int (long)' // C-NEXT: `-IntegerLiteral [[ADDR_95]] 'long' 4 // CXX: |-FunctionDecl [[ADDR_0:0x[a-z0-9]*]] <{{.*}}, line:14:1> line:12:5 used also_before 'int ({{.*}})' // CXX-NEXT: | |-CompoundStmt [[ADDR_1:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 1 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] line:16:5 used also_before 'int (int)' // CXX-NEXT: | |-ParmVarDecl [[ADDR_8:0x[a-z0-9]*]] col:21 i 'int' // CXX-NEXT: | |-CompoundStmt [[ADDR_9:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_10:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_11:0x[a-z0-9]*]] 'int' 2 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_12:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_13:0x[a-z0-9]*]] 'int (int)' Function [[ADDR_14:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int (int)' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_12:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_13:0x[a-z0-9]*]] 'int (int)' Function [[ADDR_14:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int (int)' // CXX-NEXT: |-FunctionDecl [[ADDR_15:0x[a-z0-9]*]] line:20:5 used also_before 'int (float)' // CXX-NEXT: | |-ParmVarDecl [[ADDR_16:0x[a-z0-9]*]] col:23 f 'float' // CXX-NEXT: | `-CompoundStmt [[ADDR_17:0x[a-z0-9]*]] @@ -188,30 +188,30 @@ int main(void) { // CXX-NEXT: | |-CompoundStmt [[ADDR_22:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_23:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_24:0x[a-z0-9]*]] 'int' 3 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_25:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_26:0x[a-z0-9]*]] 'int (double)' Function [[ADDR_27:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int (double)' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_25:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_26:0x[a-z0-9]*]] 'int (double)' Function [[ADDR_27:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int (double)' // CXX-NEXT: |-FunctionDecl [[ADDR_28:0x[a-z0-9]*]] line:28:5 used also_before 'int (long)' // CXX-NEXT: | |-ParmVarDecl [[ADDR_29:0x[a-z0-9]*]] col:22 l 'long' // CXX-NEXT: | |-CompoundStmt [[ADDR_30:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_31:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_32:0x[a-z0-9]*]] 'int' 4 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_33:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_34:0x[a-z0-9]*]] 'int (long)' Function [[ADDR_35:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int (long)' -// CXX-NEXT: |-FunctionDecl [[ADDR_6]] line:34:1 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_33:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_34:0x[a-z0-9]*]] 'int (long)' Function [[ADDR_35:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int (long)' +// CXX-NEXT: |-FunctionDecl [[ADDR_6]] line:34:1 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // CXX-NEXT: | `-CompoundStmt [[ADDR_36:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_37:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_38:0x[a-z0-9]*]] 'int' 0 -// CXX-NEXT: |-FunctionDecl [[ADDR_14]] line:38:1 also_before[implementation={vendor(llvm)}] 'int (int)' +// CXX-NEXT: |-FunctionDecl [[ADDR_14]] line:38:1 also_before[implementation={vendor(amd)}] 'int (int)' // CXX-NEXT: | |-ParmVarDecl [[ADDR_39:0x[a-z0-9]*]] col:21 i 'int' // CXX-NEXT: | `-CompoundStmt [[ADDR_40:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_41:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_42:0x[a-z0-9]*]] 'int' 0 -// CXX-NEXT: |-FunctionDecl [[ADDR_27]] line:43:1 also_before[implementation={vendor(llvm)}] 'int (double)' +// CXX-NEXT: |-FunctionDecl [[ADDR_27]] line:43:1 also_before[implementation={vendor(amd)}] 'int (double)' // CXX-NEXT: | |-ParmVarDecl [[ADDR_43:0x[a-z0-9]*]] col:24 d 'double' // CXX-NEXT: | `-CompoundStmt [[ADDR_44:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_45:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_46:0x[a-z0-9]*]] 'int' 0 -// CXX-NEXT: |-FunctionDecl [[ADDR_35]] line:47:1 also_before[implementation={vendor(llvm)}] 'int (long)' +// CXX-NEXT: |-FunctionDecl [[ADDR_35]] line:47:1 also_before[implementation={vendor(amd)}] 'int (long)' // CXX-NEXT: | |-ParmVarDecl [[ADDR_47:0x[a-z0-9]*]] col:22 l 'long' // CXX-NEXT: | `-CompoundStmt [[ADDR_48:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_49:0x[a-z0-9]*]] @@ -229,7 +229,7 @@ int main(void) { // CXX-NEXT: | | | | | `-DeclRefExpr [[ADDR_61:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_0]] 'also_before' 'int ({{.*}})' // CXX-NEXT: | | | | `-CallExpr [[ADDR_62:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | | | `-ImplicitCastExpr [[ADDR_63:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CXX-NEXT: | | | | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | | | | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: | | | `-PseudoObjectExpr [[ADDR_64:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | | |-CallExpr [[ADDR_65:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | | | |-ImplicitCastExpr [[ADDR_66:0x[a-z0-9]*]] 'int (*)(int)' @@ -237,7 +237,7 @@ int main(void) { // CXX-NEXT: | | | | `-IntegerLiteral [[ADDR_68:0x[a-z0-9]*]] 'int' 1 // CXX-NEXT: | | | `-CallExpr [[ADDR_69:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | | |-ImplicitCastExpr [[ADDR_70:0x[a-z0-9]*]] 'int (*)(int)' -// CXX-NEXT: | | | | `-DeclRefExpr [[ADDR_13]] 'int (int)' Function [[ADDR_14]] 'also_before[implementation={vendor(llvm)}]' 'int (int)' +// CXX-NEXT: | | | | `-DeclRefExpr [[ADDR_13]] 'int (int)' Function [[ADDR_14]] 'also_before[implementation={vendor(amd)}]' 'int (int)' // CXX-NEXT: | | | `-IntegerLiteral [[ADDR_68]] 'int' 1 // CXX-NEXT: | | `-CallExpr [[ADDR_71:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | |-ImplicitCastExpr [[ADDR_72:0x[a-z0-9]*]] 'int (*)(float)' @@ -250,7 +250,7 @@ int main(void) { // CXX-NEXT: | | `-FloatingLiteral [[ADDR_79:0x[a-z0-9]*]] 'double' 3.000000e+00 // CXX-NEXT: | `-CallExpr [[ADDR_80:0x[a-z0-9]*]] 'int' // CXX-NEXT: | |-ImplicitCastExpr [[ADDR_81:0x[a-z0-9]*]] 'int (*)(double)' -// CXX-NEXT: | | `-DeclRefExpr [[ADDR_26]] 'int (double)' Function [[ADDR_27]] 'also_before[implementation={vendor(llvm)}]' 'int (double)' +// CXX-NEXT: | | `-DeclRefExpr [[ADDR_26]] 'int (double)' Function [[ADDR_27]] 'also_before[implementation={vendor(amd)}]' 'int (double)' // CXX-NEXT: | `-FloatingLiteral [[ADDR_79]] 'double' 3.000000e+00 // CXX-NEXT: `-PseudoObjectExpr [[ADDR_82:0x[a-z0-9]*]] 'int' // CXX-NEXT: |-CallExpr [[ADDR_83:0x[a-z0-9]*]] 'int' @@ -259,5 +259,5 @@ int main(void) { // CXX-NEXT: | `-IntegerLiteral [[ADDR_86:0x[a-z0-9]*]] 'long' 4 // CXX-NEXT: `-CallExpr [[ADDR_87:0x[a-z0-9]*]] 'int' // CXX-NEXT: |-ImplicitCastExpr [[ADDR_88:0x[a-z0-9]*]] 'int (*)(long)' -// CXX-NEXT: | `-DeclRefExpr [[ADDR_34]] 'int (long)' Function [[ADDR_35]] 'also_before[implementation={vendor(llvm)}]' 'int (long)' +// CXX-NEXT: | `-DeclRefExpr [[ADDR_34]] 'int (long)' Function [[ADDR_35]] 'also_before[implementation={vendor(amd)}]' 'int (long)' // CXX-NEXT: `-IntegerLiteral [[ADDR_86]] 'long' 4 diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_2.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_2.c index e7a30a9d59671..23427aeadc007 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_2.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_2.c @@ -8,12 +8,12 @@ int also_before(void) { } #pragma omp end declare variant -#pragma omp begin declare variant match(implementation={vendor(score(100):llvm)}) +#pragma omp begin declare variant match(implementation={vendor(score(100):amd)}) int also_after(void) { return 0; } #pragma omp end declare variant -#pragma omp begin declare variant match(implementation={vendor(score(0):llvm)}) +#pragma omp begin declare variant match(implementation={vendor(score(0):amd)}) int also_before(void) { return 1; } @@ -30,26 +30,26 @@ int test(void) { // Make sure: // - we do see the ast nodes for the cpu kind -// - we do see the ast nodes for the llvm vendor +// - we do see the ast nodes for the amd vendor // - we pick the right callees // CHECK: |-FunctionDecl [[ADDR_0:0x[a-z0-9]*]] <{{.*}}, col:21> col:5 implicit used also_before 'int ({{.*}})' // CHECK-NEXT: | |-OMPDeclareVariantAttr [[ADDR_1:0x[a-z0-9]*]] <> Implicit device={kind(cpu)} // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_2:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_3:0x[a-z0-9]*]] 'also_before[device={kind(cpu)}]' 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_3]] line:6:1 also_before[device={kind(cpu)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_7:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_8:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_9:0x[a-z0-9]*]] 'int' 0 // CHECK-NEXT: |-FunctionDecl [[ADDR_10:0x[a-z0-9]*]] col:5 implicit used also_after 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_11:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_13:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CHECK-NEXT: |-FunctionDecl [[ADDR_13]] line:12:1 also_after[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_11:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_13:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_13]] line:12:1 also_after[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_14:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_15:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_16:0x[a-z0-9]*]] 'int' 0 -// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:17:1 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:17:1 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_17:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_18:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_19:0x[a-z0-9]*]] 'int' 1 @@ -57,8 +57,8 @@ int test(void) { // CHECK-NEXT: | |-CompoundStmt [[ADDR_21:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_22:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_23:0x[a-z0-9]*]] 'int' 2 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_24:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_24:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: `-FunctionDecl [[ADDR_25:0x[a-z0-9]*]] line:26:5 test 'int ({{.*}})' // CHECK-NEXT: `-CompoundStmt [[ADDR_26:0x[a-z0-9]*]] // CHECK-NEXT: `-ReturnStmt [[ADDR_27:0x[a-z0-9]*]] @@ -69,7 +69,7 @@ int test(void) { // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_32:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_20]] 'also_after' 'int ({{.*}})' // CHECK-NEXT: | `-CallExpr [[ADDR_33:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_34:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: `-PseudoObjectExpr [[ADDR_35:0x[a-z0-9]*]] 'int' // CHECK-NEXT: |-CallExpr [[ADDR_36:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_37:0x[a-z0-9]*]] 'int (*)({{.*}})' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_3.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_3.c index da78f2b082072..c464d83276518 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_3.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_3.c @@ -8,12 +8,12 @@ int also_before(void) { } #pragma omp end declare variant -#pragma omp begin declare variant match(implementation={vendor(score(0):llvm)}) +#pragma omp begin declare variant match(implementation={vendor(score(0):amd)}) int also_after(void) { return 0; } #pragma omp end declare variant -#pragma omp begin declare variant match(implementation={vendor(score(100):llvm)}) +#pragma omp begin declare variant match(implementation={vendor(score(100):amd)}) int also_before(void) { return 0; } @@ -30,26 +30,26 @@ int test(void) { // Make sure: // - we do see the ast nodes for the cpu kind -// - we do see the ast nodes for the llvm vendor +// - we do see the ast nodes for the amd vendor // - we pick the right callees // CHECK: |-FunctionDecl [[ADDR_0:0x[a-z0-9]*]] <{{.*}}, col:21> col:5 implicit used also_before 'int ({{.*}})' // CHECK-NEXT: | |-OMPDeclareVariantAttr [[ADDR_1:0x[a-z0-9]*]] <> Implicit device={kind(cpu)} // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_2:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_3:0x[a-z0-9]*]] 'also_before[device={kind(cpu)}]' 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_3]] line:6:1 also_before[device={kind(cpu)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_7:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_8:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_9:0x[a-z0-9]*]] 'int' 1 // CHECK-NEXT: |-FunctionDecl [[ADDR_10:0x[a-z0-9]*]] col:5 implicit used also_after 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_11:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_13:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CHECK-NEXT: |-FunctionDecl [[ADDR_13]] line:12:1 also_after[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_11:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_13:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_13]] line:12:1 also_after[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_14:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_15:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_16:0x[a-z0-9]*]] 'int' 0 -// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:17:1 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:17:1 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_17:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_18:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_19:0x[a-z0-9]*]] 'int' 0 @@ -57,8 +57,8 @@ int test(void) { // CHECK-NEXT: | |-CompoundStmt [[ADDR_21:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_22:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_23:0x[a-z0-9]*]] 'int' 2 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_24:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(0): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_24:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(0): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: `-FunctionDecl [[ADDR_25:0x[a-z0-9]*]] line:26:5 test 'int ({{.*}})' // CHECK-NEXT: `-CompoundStmt [[ADDR_26:0x[a-z0-9]*]] // CHECK-NEXT: `-ReturnStmt [[ADDR_27:0x[a-z0-9]*]] @@ -69,11 +69,11 @@ int test(void) { // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_32:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_20]] 'also_after' 'int ({{.*}})' // CHECK-NEXT: | `-CallExpr [[ADDR_33:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_34:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: `-PseudoObjectExpr [[ADDR_35:0x[a-z0-9]*]] 'int' // CHECK-NEXT: |-CallExpr [[ADDR_36:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_37:0x[a-z0-9]*]] 'int (*)({{.*}})' // CHECK-NEXT: | `-DeclRefExpr [[ADDR_38:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_0]] 'also_before' 'int ({{.*}})' // CHECK-NEXT: `-CallExpr [[ADDR_39:0x[a-z0-9]*]] 'int' // CHECK-NEXT: `-ImplicitCastExpr [[ADDR_40:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_5.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_5.c index d8ca6860a04b2..1bdcb3a8932e8 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_5.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_5.c @@ -6,7 +6,7 @@ int also_before(void) { return 1; } -#pragma omp begin declare variant match(implementation={vendor(llvm)}) +#pragma omp begin declare variant match(implementation={vendor(amd)}) int also_after(void) { return 0; } @@ -35,16 +35,16 @@ int main(void) { // C-NEXT: | |-CompoundStmt [[ADDR_1:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 1 -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] col:5 implicit used also_after 'int ({{.*}})' -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' -// C-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(llvm)}] 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' +// C-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(amd)}] 'int ({{.*}})' // C-NEXT: | `-CompoundStmt [[ADDR_11:0x[a-z0-9]*]] // C-NEXT: | `-ReturnStmt [[ADDR_12:0x[a-z0-9]*]] // C-NEXT: | `-IntegerLiteral [[ADDR_13:0x[a-z0-9]*]] 'int' 0 -// C-NEXT: |-FunctionDecl [[ADDR_6]] line:13:1 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// C-NEXT: |-FunctionDecl [[ADDR_6]] line:13:1 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // C-NEXT: | `-CompoundStmt [[ADDR_14:0x[a-z0-9]*]] // C-NEXT: | `-ReturnStmt [[ADDR_15:0x[a-z0-9]*]] // C-NEXT: | `-IntegerLiteral [[ADDR_16:0x[a-z0-9]*]] 'int' 0 @@ -52,8 +52,8 @@ int main(void) { // C-NEXT: | |-CompoundStmt [[ADDR_18:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_19:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_20:0x[a-z0-9]*]] 'int' 2 -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: `-FunctionDecl [[ADDR_22:0x[a-z0-9]*]] line:22:5 main 'int ({{.*}})' // C-NEXT: `-CompoundStmt [[ADDR_23:0x[a-z0-9]*]] // C-NEXT: `-ReturnStmt [[ADDR_24:0x[a-z0-9]*]] @@ -67,7 +67,7 @@ int main(void) { // C-NEXT: | | | | `-DeclRefExpr [[ADDR_32:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_17]] 'also_after' 'int ({{.*}})' // C-NEXT: | | | `-CallExpr [[ADDR_33:0x[a-z0-9]*]] 'int' // C-NEXT: | | | `-ImplicitCastExpr [[ADDR_34:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: | | | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | | | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: | | `-PseudoObjectExpr [[ADDR_35:0x[a-z0-9]*]] 'int' // C-NEXT: | | |-CallExpr [[ADDR_36:0x[a-z0-9]*]] 'int' // C-NEXT: | | | `-ImplicitCastExpr [[ADDR_37:0x[a-z0-9]*]] 'int (*)({{.*}})' @@ -75,7 +75,7 @@ int main(void) { // C-NEXT: | | | `-DeclRefExpr [[ADDR_39:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_0]] 'also_before' 'int ({{.*}})' // C-NEXT: | | `-CallExpr [[ADDR_40:0x[a-z0-9]*]] 'int' // C-NEXT: | | `-ImplicitCastExpr [[ADDR_41:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: | | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: | `-PseudoObjectExpr [[ADDR_42:0x[a-z0-9]*]] 'int' // C-NEXT: | |-CallExpr [[ADDR_43:0x[a-z0-9]*]] 'int' // C-NEXT: | | `-ParenExpr [[ADDR_44:0x[a-z0-9]*]] 'int (*)({{.*}})' @@ -83,7 +83,7 @@ int main(void) { // C-NEXT: | | `-DeclRefExpr [[ADDR_46:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_17]] 'also_after' 'int ({{.*}})' // C-NEXT: | `-CallExpr [[ADDR_47:0x[a-z0-9]*]] 'int' // C-NEXT: | `-ImplicitCastExpr [[ADDR_48:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: `-PseudoObjectExpr [[ADDR_49:0x[a-z0-9]*]] 'int' // C-NEXT: |-CallExpr [[ADDR_50:0x[a-z0-9]*]] 'int' // C-NEXT: | `-ParenExpr [[ADDR_51:0x[a-z0-9]*]] 'int (*)({{.*}})' @@ -91,22 +91,22 @@ int main(void) { // C-NEXT: | `-DeclRefExpr [[ADDR_53:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_0]] 'also_before' 'int ({{.*}})' // C-NEXT: `-CallExpr [[ADDR_54:0x[a-z0-9]*]] 'int' // C-NEXT: `-ImplicitCastExpr [[ADDR_55:0x[a-z0-9]*]] 'int (*)({{.*}})' -// C-NEXT: `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX: |-FunctionDecl [[ADDR_0:0x[a-z0-9]*]] <{{.*}}, line:7:1> line:5:5 used also_before 'int ({{.*}})' // CXX-NEXT: | |-CompoundStmt [[ADDR_1:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 1 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] col:5 implicit used also_after 'int ({{.*}})' -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CXX-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(llvm)}] 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' +// CXX-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(amd)}] 'int ({{.*}})' // CXX-NEXT: | `-CompoundStmt [[ADDR_11:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_12:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_13:0x[a-z0-9]*]] 'int' 0 -// CXX-NEXT: |-FunctionDecl [[ADDR_6]] line:13:1 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// CXX-NEXT: |-FunctionDecl [[ADDR_6]] line:13:1 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // CXX-NEXT: | `-CompoundStmt [[ADDR_14:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_15:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_16:0x[a-z0-9]*]] 'int' 0 @@ -114,8 +114,8 @@ int main(void) { // CXX-NEXT: | |-CompoundStmt [[ADDR_18:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_19:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_20:0x[a-z0-9]*]] 'int' 2 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: `-FunctionDecl [[ADDR_22:0x[a-z0-9]*]] line:22:5 main 'int ({{.*}})' // CXX-NEXT: `-CompoundStmt [[ADDR_23:0x[a-z0-9]*]] // CXX-NEXT: `-ReturnStmt [[ADDR_24:0x[a-z0-9]*]] @@ -129,7 +129,7 @@ int main(void) { // CXX-NEXT: | | | | `-DeclRefExpr [[ADDR_32:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_17]] 'also_after' 'int ({{.*}})' // CXX-NEXT: | | | `-CallExpr [[ADDR_33:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | | `-ImplicitCastExpr [[ADDR_34:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CXX-NEXT: | | | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | | | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: | | `-PseudoObjectExpr [[ADDR_35:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | |-CallExpr [[ADDR_36:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | | `-ImplicitCastExpr [[ADDR_37:0x[a-z0-9]*]] 'int (*)({{.*}})' @@ -137,7 +137,7 @@ int main(void) { // CXX-NEXT: | | | `-DeclRefExpr [[ADDR_39:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_0]] 'also_before' 'int ({{.*}})' // CXX-NEXT: | | `-CallExpr [[ADDR_40:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | `-ImplicitCastExpr [[ADDR_41:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CXX-NEXT: | | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: | `-PseudoObjectExpr [[ADDR_42:0x[a-z0-9]*]] 'int' // CXX-NEXT: | |-CallExpr [[ADDR_43:0x[a-z0-9]*]] 'int' // CXX-NEXT: | | `-ParenExpr [[ADDR_44:0x[a-z0-9]*]] 'int (*)({{.*}})' @@ -145,7 +145,7 @@ int main(void) { // CXX-NEXT: | | `-DeclRefExpr [[ADDR_46:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_17]] 'also_after' 'int ({{.*}})' // CXX-NEXT: | `-CallExpr [[ADDR_47:0x[a-z0-9]*]] 'int' // CXX-NEXT: | `-ImplicitCastExpr [[ADDR_48:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CXX-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: `-PseudoObjectExpr [[ADDR_49:0x[a-z0-9]*]] 'int' // CXX-NEXT: |-CallExpr [[ADDR_50:0x[a-z0-9]*]] 'int' // CXX-NEXT: | `-ParenExpr [[ADDR_51:0x[a-z0-9]*]] 'int (*)({{.*}})' @@ -153,4 +153,4 @@ int main(void) { // CXX-NEXT: | `-DeclRefExpr [[ADDR_53:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_0]] 'also_before' 'int ({{.*}})' // CXX-NEXT: `-CallExpr [[ADDR_54:0x[a-z0-9]*]] 'int' // CXX-NEXT: `-ImplicitCastExpr [[ADDR_55:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CXX-NEXT: `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_8.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_8.c index da78f2b082072..c464d83276518 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_8.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_8.c @@ -8,12 +8,12 @@ int also_before(void) { } #pragma omp end declare variant -#pragma omp begin declare variant match(implementation={vendor(score(0):llvm)}) +#pragma omp begin declare variant match(implementation={vendor(score(0):amd)}) int also_after(void) { return 0; } #pragma omp end declare variant -#pragma omp begin declare variant match(implementation={vendor(score(100):llvm)}) +#pragma omp begin declare variant match(implementation={vendor(score(100):amd)}) int also_before(void) { return 0; } @@ -30,26 +30,26 @@ int test(void) { // Make sure: // - we do see the ast nodes for the cpu kind -// - we do see the ast nodes for the llvm vendor +// - we do see the ast nodes for the amd vendor // - we pick the right callees // CHECK: |-FunctionDecl [[ADDR_0:0x[a-z0-9]*]] <{{.*}}, col:21> col:5 implicit used also_before 'int ({{.*}})' // CHECK-NEXT: | |-OMPDeclareVariantAttr [[ADDR_1:0x[a-z0-9]*]] <> Implicit device={kind(cpu)} // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_2:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_3:0x[a-z0-9]*]] 'also_before[device={kind(cpu)}]' 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_3]] line:6:1 also_before[device={kind(cpu)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_7:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_8:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_9:0x[a-z0-9]*]] 'int' 1 // CHECK-NEXT: |-FunctionDecl [[ADDR_10:0x[a-z0-9]*]] col:5 implicit used also_after 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_11:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_13:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CHECK-NEXT: |-FunctionDecl [[ADDR_13]] line:12:1 also_after[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_11:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_13:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_13]] line:12:1 also_after[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_14:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_15:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_16:0x[a-z0-9]*]] 'int' 0 -// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:17:1 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:17:1 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_17:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_18:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_19:0x[a-z0-9]*]] 'int' 0 @@ -57,8 +57,8 @@ int test(void) { // CHECK-NEXT: | |-CompoundStmt [[ADDR_21:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_22:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_23:0x[a-z0-9]*]] 'int' 2 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_24:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(0): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_24:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(0): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: `-FunctionDecl [[ADDR_25:0x[a-z0-9]*]] line:26:5 test 'int ({{.*}})' // CHECK-NEXT: `-CompoundStmt [[ADDR_26:0x[a-z0-9]*]] // CHECK-NEXT: `-ReturnStmt [[ADDR_27:0x[a-z0-9]*]] @@ -69,11 +69,11 @@ int test(void) { // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_32:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_20]] 'also_after' 'int ({{.*}})' // CHECK-NEXT: | `-CallExpr [[ADDR_33:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_34:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_12]] 'int ({{.*}})' Function [[ADDR_13]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: `-PseudoObjectExpr [[ADDR_35:0x[a-z0-9]*]] 'int' // CHECK-NEXT: |-CallExpr [[ADDR_36:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_37:0x[a-z0-9]*]] 'int (*)({{.*}})' // CHECK-NEXT: | `-DeclRefExpr [[ADDR_38:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_0]] 'also_before' 'int ({{.*}})' // CHECK-NEXT: `-CallExpr [[ADDR_39:0x[a-z0-9]*]] 'int' // CHECK-NEXT: `-ImplicitCastExpr [[ADDR_40:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_9.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_9.c index 02f73538a9782..891838d638659 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_9.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_9.c @@ -6,7 +6,7 @@ int also_before(void) { return 0; } -#pragma omp begin declare variant match(implementation={vendor(llvm)}) +#pragma omp begin declare variant match(implementation={vendor(amd)}) int also_after(void) { return 1; } @@ -39,16 +39,16 @@ int main(void) { // C-NEXT: | |-CompoundStmt [[ADDR_1:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 0 -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] col:5 implicit used also_after 'int ({{.*}})' -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' -// C-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(llvm)}] 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' +// C-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(amd)}] 'int ({{.*}})' // C-NEXT: | `-CompoundStmt [[ADDR_11:0x[a-z0-9]*]] // C-NEXT: | `-ReturnStmt [[ADDR_12:0x[a-z0-9]*]] // C-NEXT: | `-IntegerLiteral [[ADDR_13:0x[a-z0-9]*]] 'int' 1 -// C-NEXT: |-FunctionDecl [[ADDR_6]] line:13:1 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// C-NEXT: |-FunctionDecl [[ADDR_6]] line:13:1 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // C-NEXT: | `-CompoundStmt [[ADDR_14:0x[a-z0-9]*]] // C-NEXT: | `-ReturnStmt [[ADDR_15:0x[a-z0-9]*]] // C-NEXT: | `-IntegerLiteral [[ADDR_16:0x[a-z0-9]*]] 'int' 2 @@ -56,8 +56,8 @@ int main(void) { // C-NEXT: | |-CompoundStmt [[ADDR_18:0x[a-z0-9]*]] // C-NEXT: | | `-ReturnStmt [[ADDR_19:0x[a-z0-9]*]] // C-NEXT: | | `-IntegerLiteral [[ADDR_20:0x[a-z0-9]*]] 'int' 0 -// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// C-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// C-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// C-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // C-NEXT: |-FunctionDecl [[ADDR_22:0x[a-z0-9]*]] col:6 used foo 'void ({{.*}})' // C-NEXT: |-TypedefDecl [[ADDR_23:0x[a-z0-9]*]] col:14 referenced fd 'int (*)({{.*}})' // C-NEXT: | `-PointerType [[ADDR_24:0x[a-z0-9]*]] 'int (*)({{.*}})' @@ -112,16 +112,16 @@ int main(void) { // CXX-NEXT: | |-CompoundStmt [[ADDR_1:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 0 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] col:5 implicit used also_after 'int ({{.*}})' -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CXX-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(llvm)}] 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' +// CXX-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(amd)}] 'int ({{.*}})' // CXX-NEXT: | `-CompoundStmt [[ADDR_11:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_12:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_13:0x[a-z0-9]*]] 'int' 1 -// CXX-NEXT: |-FunctionDecl [[ADDR_6]] line:13:1 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// CXX-NEXT: |-FunctionDecl [[ADDR_6]] line:13:1 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // CXX-NEXT: | `-CompoundStmt [[ADDR_14:0x[a-z0-9]*]] // CXX-NEXT: | `-ReturnStmt [[ADDR_15:0x[a-z0-9]*]] // CXX-NEXT: | `-IntegerLiteral [[ADDR_16:0x[a-z0-9]*]] 'int' 2 @@ -129,8 +129,8 @@ int main(void) { // CXX-NEXT: | |-CompoundStmt [[ADDR_18:0x[a-z0-9]*]] // CXX-NEXT: | | `-ReturnStmt [[ADDR_19:0x[a-z0-9]*]] // CXX-NEXT: | | `-IntegerLiteral [[ADDR_20:0x[a-z0-9]*]] 'int' 0 -// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// CXX-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CXX-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// CXX-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CXX-NEXT: |-FunctionDecl [[ADDR_22:0x[a-z0-9]*]] col:6 used foo 'void ({{.*}})' // CXX-NEXT: |-TypedefDecl [[ADDR_23:0x[a-z0-9]*]] col:14 referenced fd 'int (*)({{.*}})' // CXX-NEXT: | `-PointerType [[ADDR_24:0x[a-z0-9]*]] 'int (*)({{.*}})' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_addr_1.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_addr_1.c index 0b082007ba80b..a87e16e388c40 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_addr_1.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_addr_1.c @@ -6,7 +6,7 @@ int also_before(void) { return 0; } -#pragma omp begin declare variant match(implementation={vendor(llvm)}) +#pragma omp begin declare variant match(implementation={vendor(amd)}) int also_after(void) { return 1; } @@ -38,16 +38,16 @@ int main(void) { // CHECK-NEXT: | |-CompoundStmt [[ADDR_1:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 0 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] col:5 implicit used also_after 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CHECK-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_11:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_12:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_13:0x[a-z0-9]*]] 'int' 1 -// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:13:1 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:13:1 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_14:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_15:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_16:0x[a-z0-9]*]] 'int' 2 @@ -55,8 +55,8 @@ int main(void) { // CHECK-NEXT: | |-CompoundStmt [[ADDR_18:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_19:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_20:0x[a-z0-9]*]] 'int' 0 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_22:0x[a-z0-9]*]] line:22:5 used test 'int (int (*)({{.*}}))' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_23:0x[a-z0-9]*]] col:16 used fd 'int (*)({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_24:0x[a-z0-9]*]] diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_decl_1.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_decl_1.c index bbf945e6179f6..b58b3cf61a219 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_decl_1.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_decl_1.c @@ -9,10 +9,10 @@ int also_before(void) { #pragma omp begin declare variant match(device={kind(cpu)}) int also_before(void); #pragma omp end declare variant -#pragma omp begin declare variant match(implementation={vendor(score(100):llvm)}) +#pragma omp begin declare variant match(implementation={vendor(score(100):amd)}) int also_after(void); #pragma omp end declare variant -#pragma omp begin declare variant match(implementation={vendor(score(0):llvm)}) +#pragma omp begin declare variant match(implementation={vendor(score(0):amd)}) int also_before(void); #pragma omp end declare variant @@ -27,7 +27,7 @@ int test(void) { // Make sure: // - we do see the ast nodes for the cpu kind -// - we do see the ast nodes for the llvm vendor +// - we do see the ast nodes for the amd vendor // - we pick the right callees // CHECK: |-FunctionDecl [[ADDR_0:0x[a-z0-9]*]] <{{.*}}, line:7:1> line:5:5 used also_before 'int ({{.*}})' diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_namespace_1.cpp b/clang/test/AST/ast-dump-openmp-begin-declare-variant_namespace_1.cpp index 99e02adb6b4de..ea36191014234 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_namespace_1.cpp +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_namespace_1.cpp @@ -18,7 +18,7 @@ int baz(void) { } } // namespace C -#pragma omp begin declare variant match(implementation = {vendor(llvm)}) +#pragma omp begin declare variant match(implementation = {vendor(amd)}) // This will *not* be a specialization of A::foo(void). int foo(void) { // expected-note {{candidate function}} @@ -73,36 +73,36 @@ int main() { // CHECK-NEXT: | |-CompoundStmt [[ADDR_7:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_8:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_9:0x[a-z0-9]*]] 'int' 1 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_10:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_11:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_12:0x[a-z0-9]*]] 'bar[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_10:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_11:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_12:0x[a-z0-9]*]] 'bar[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-NamespaceDecl [[ADDR_13:0x[a-z0-9]*]] line:15:11 C // CHECK-NEXT: | `-FunctionDecl [[ADDR_14:0x[a-z0-9]*]] line:16:5 used baz 'int ({{.*}})' // CHECK-NEXT: | |-CompoundStmt [[ADDR_15:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_16:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_17:0x[a-z0-9]*]] 'int' 2 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_18:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_19:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_20:0x[a-z0-9]*]] 'baz[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_18:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_19:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_20:0x[a-z0-9]*]] 'baz[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_21:0x[a-z0-9]*]] col:5 implicit foo 'int ({{.*}})' -// CHECK-NEXT: | |-OMPDeclareVariantAttr [[ADDR_22:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_23:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_24:0x[a-z0-9]*]] 'foo[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_25:0x[a-z0-9]*]] <> Implicit implementation={vendor(llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_26:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_27:0x[a-z0-9]*]] 'foo[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CHECK-NEXT: |-FunctionDecl [[ADDR_24]] line:24:1 foo[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: | |-OMPDeclareVariantAttr [[ADDR_22:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_23:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_24:0x[a-z0-9]*]] 'foo[implementation={vendor(amd)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_25:0x[a-z0-9]*]] <> Implicit implementation={vendor(amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_26:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_27:0x[a-z0-9]*]] 'foo[implementation={vendor(amd)}]' 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_24]] line:24:1 foo[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_28:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_29:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_30:0x[a-z0-9]*]] 'int' 3 // CHECK-NEXT: |-NamespaceDecl [[ADDR_31:0x[a-z0-9]*]] prev [[ADDR_5]] line:28:11 B // CHECK-NEXT: | |-original Namespace [[ADDR_5]] 'B' -// CHECK-NEXT: | |-FunctionDecl [[ADDR_27]] line:30:1 foo[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: | |-FunctionDecl [[ADDR_27]] line:30:1 foo[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | | `-CompoundStmt [[ADDR_32:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_33:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_34:0x[a-z0-9]*]] 'int' 4 -// CHECK-NEXT: | `-FunctionDecl [[ADDR_12]] line:34:1 bar[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: | `-FunctionDecl [[ADDR_12]] line:34:1 bar[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_35:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_36:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_37:0x[a-z0-9]*]] 'int' 0 // CHECK-NEXT: |-UsingDirectiveDecl [[ADDR_38:0x[a-z0-9]*]] col:17 Namespace [[ADDR_13]] 'C' -// CHECK-NEXT: |-FunctionDecl [[ADDR_20]] line:42:1 baz[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_20]] line:42:1 baz[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_39:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_40:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_41:0x[a-z0-9]*]] 'int' 0 @@ -122,7 +122,7 @@ int main() { // CHECK-NEXT: | | | `-NestedNameSpecifier Namespace [[ADDR_31]] 'B' // CHECK-NEXT: | | `-CallExpr [[ADDR_54:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_55:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_11]] 'int ({{.*}})' Function [[ADDR_12]] 'bar[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_11]] 'int ({{.*}})' Function [[ADDR_12]] 'bar[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: | `-PseudoObjectExpr [[ADDR_56:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | |-CallExpr [[ADDR_57:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_58:0x[a-z0-9]*]] 'int (*)({{.*}})' @@ -130,7 +130,7 @@ int main() { // CHECK-NEXT: | | `-NestedNameSpecifier Namespace [[ADDR_13]] 'C' // CHECK-NEXT: | `-CallExpr [[ADDR_60:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_61:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}})' Function [[ADDR_20]] 'baz[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}})' Function [[ADDR_20]] 'baz[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_62:0x[a-z0-9]*]] line:53:5 used implicit2 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_63:0x[a-z0-9]*]] // CHECK-NEXT: | |-DeclStmt [[ADDR_64:0x[a-z0-9]*]] @@ -147,14 +147,14 @@ int main() { // CHECK-NEXT: | | | `-DeclRefExpr [[ADDR_73:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_6]] 'bar' 'int ({{.*}})' // CHECK-NEXT: | | `-CallExpr [[ADDR_74:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_75:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_11]] 'int ({{.*}})' Function [[ADDR_12]] 'bar[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_11]] 'int ({{.*}})' Function [[ADDR_12]] 'bar[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: | `-PseudoObjectExpr [[ADDR_76:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | |-CallExpr [[ADDR_77:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_78:0x[a-z0-9]*]] 'int (*)({{.*}})' // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_79:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_14]] 'baz' 'int ({{.*}})' // CHECK-NEXT: | `-CallExpr [[ADDR_80:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_81:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}})' Function [[ADDR_20]] 'baz[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_19]] 'int ({{.*}})' Function [[ADDR_20]] 'baz[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: `-FunctionDecl [[ADDR_82:0x[a-z0-9]*]] line:61:5 main 'int ({{.*}})' // CHECK-NEXT: `-CompoundStmt [[ADDR_83:0x[a-z0-9]*]] // CHECK-NEXT: `-ReturnStmt [[ADDR_84:0x[a-z0-9]*]] diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_nested.c b/clang/test/AST/ast-dump-openmp-begin-declare-variant_nested.c index 11bd51e7443bc..a3d00c095bd7c 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_nested.c +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_nested.c @@ -6,8 +6,8 @@ int also_before(void) { return 1; } -#pragma omp begin declare variant match(user = {condition(1)}, device = {kind(cpu)}, implementation = {vendor(llvm)}) -#pragma omp begin declare variant match(device = {kind(cpu)}, implementation = {vendor(llvm, pgi), extension(match_any)}) +#pragma omp begin declare variant match(user = {condition(1)}, device = {kind(cpu)}, implementation = {vendor(amd)}) +#pragma omp begin declare variant match(device = {kind(cpu)}, implementation = {vendor(amd, pgi), extension(match_any)}) #pragma omp begin declare variant match(device = {kind(any)}, implementation = {dynamic_allocators}) int also_after(void) { return 0; @@ -42,16 +42,16 @@ int non_equivalent_isa_trait(void); // CHECK-NEXT: | |-CompoundStmt [[ADDR_1:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 1 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(llvm, pgi), extension(match_any)}, user={condition(1)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(llvm, pgi), extension(match_any)}, user={condition(...)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(amd, pgi), extension(match_any)}, user={condition(1)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(amd, pgi), extension(match_any)}, user={condition(...)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] col:5 implicit used also_after 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(llvm, pgi), extension(match_any)}, user={condition(1)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(llvm, pgi), extension(match_any)}, user={condition(...)}]' 'int ({{.*}})' -// CHECK-NEXT: |-FunctionDecl [[ADDR_10]] line:12:1 also_after[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(llvm, pgi), extension(match_any)}, user={condition(...)}] 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(amd, pgi), extension(match_any)}, user={condition(1)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(amd, pgi), extension(match_any)}, user={condition(...)}]' 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_10]] line:12:1 also_after[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(amd, pgi), extension(match_any)}, user={condition(...)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_11:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_12:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_13:0x[a-z0-9]*]] 'int' 0 -// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:15:1 also_before[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(llvm, pgi), extension(match_any)}, user={condition(...)}] 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:15:1 also_before[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(amd, pgi), extension(match_any)}, user={condition(...)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_14:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_15:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_16:0x[a-z0-9]*]] 'int' 0 @@ -59,8 +59,8 @@ int non_equivalent_isa_trait(void); // CHECK-NEXT: | |-CompoundStmt [[ADDR_18:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_19:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_20:0x[a-z0-9]*]] 'int' 2 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(llvm, pgi), extension(match_any)}, user={condition(1)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' {{.*}}Function [[ADDR_10]] 'also_after[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(llvm, pgi), extension(match_any)}, user={condition(...)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_21:0x[a-z0-9]*]] <> Inherited Implicit device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(amd, pgi), extension(match_any)}, user={condition(1)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' {{.*}}Function [[ADDR_10]] 'also_after[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(amd, pgi), extension(match_any)}, user={condition(...)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_22:0x[a-z0-9]*]] line:26:5 referenced test 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_23:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_24:0x[a-z0-9]*]] @@ -71,14 +71,14 @@ int non_equivalent_isa_trait(void); // CHECK-NEXT: | | | `-DeclRefExpr [[ADDR_29:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_17]] 'also_after' 'int ({{.*}})' // CHECK-NEXT: | | `-CallExpr [[ADDR_30:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_31:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' {{.*}}Function [[ADDR_10]] 'also_after[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(llvm, pgi), extension(match_any)}, user={condition(...)}]' 'int ({{.*}})' +// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' {{.*}}Function [[ADDR_10]] 'also_after[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(amd, pgi), extension(match_any)}, user={condition(...)}]' 'int ({{.*}})' // CHECK-NEXT: | `-PseudoObjectExpr [[ADDR_32:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | |-CallExpr [[ADDR_33:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_34:0x[a-z0-9]*]] 'int (*)({{.*}})' // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_35:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_0]] 'also_before' 'int ({{.*}})' // CHECK-NEXT: | `-CallExpr [[ADDR_36:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_37:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' {{.*}}Function [[ADDR_6]] 'also_before[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(llvm, pgi), extension(match_any)}, user={condition(...)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' {{.*}}Function [[ADDR_6]] 'also_before[device={kind(any, cpu)}, implementation={dynamic_allocators, vendor(amd, pgi), extension(match_any)}, user={condition(...)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_38:0x[a-z0-9]*]] col:5 equivalent_isa_trait 'int ({{.*}})' // CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_39:0x[a-z0-9]*]] Implicit device={isa(sse)} // CHECK-NEXT: | `-DeclRefExpr [[ADDR_40:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_22]] 'test' 'int ({{.*}})' non_odr_use_unevaluated diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_reference.cpp b/clang/test/AST/ast-dump-openmp-begin-declare-variant_reference.cpp index 9584e77b9e414..45acec828495e 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_reference.cpp +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_reference.cpp @@ -23,7 +23,7 @@ int also_before(float &&) { } #pragma omp begin declare variant match(implementation = {vendor(score(100) \ - : llvm)}) + : amd)}) int also_after(void) { return 1; } @@ -45,7 +45,7 @@ int also_after(short &&) { } #pragma omp end declare variant #pragma omp begin declare variant match(implementation = {vendor(score(0) \ - : llvm)}) + : amd)}) // This one does overload the int&(*)(void) version! int &also_before() { return Good; @@ -224,74 +224,74 @@ int test(float &&f, short &&s) { // CHECK-NEXT: | |-CompoundStmt [[ADDR_65:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_66:0x[a-z0-9]*]] // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_67:0x[a-z0-9]*]] 'int' {{.*}}Var [[ADDR_63]] 'Bad' 'int' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_68:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_69:0x[a-z0-9]*]] 'int &({{.*}})' {{.*}}Function [[ADDR_70:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int &({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_68:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_69:0x[a-z0-9]*]] 'int &({{.*}})' {{.*}}Function [[ADDR_70:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int &({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_71:0x[a-z0-9]*]] line:21:5 used also_before 'int (float &&)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_72:0x[a-z0-9]*]] col:25 'float &&' // CHECK-NEXT: | `-CompoundStmt [[ADDR_73:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_74:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_75:0x[a-z0-9]*]] 'int' 0 // CHECK-NEXT: |-FunctionDecl [[ADDR_76:0x[a-z0-9]*]] col:5 implicit also_after 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_77:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_78:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_79:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CHECK-NEXT: |-FunctionDecl [[ADDR_79]] line:27:1 also_after[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_77:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_78:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_79:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_79]] line:27:1 also_after[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_80:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_81:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_82:0x[a-z0-9]*]] 'int' 1 // CHECK-NEXT: |-FunctionDecl [[ADDR_83:0x[a-z0-9]*]] col:5 implicit also_after 'int (int &)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_84:0x[a-z0-9]*]] col:21 'int &' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_85:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_86:0x[a-z0-9]*]] 'int (int &)' {{.*}}Function [[ADDR_87:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int (int &)' -// CHECK-NEXT: |-FunctionDecl [[ADDR_87]] line:30:1 also_after[implementation={vendor(llvm)}] 'int (int &)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_85:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_86:0x[a-z0-9]*]] 'int (int &)' {{.*}}Function [[ADDR_87:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int (int &)' +// CHECK-NEXT: |-FunctionDecl [[ADDR_87]] line:30:1 also_after[implementation={vendor(amd)}] 'int (int &)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_84]] col:21 'int &' // CHECK-NEXT: | `-CompoundStmt [[ADDR_88:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_89:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_90:0x[a-z0-9]*]] 'int' 2 // CHECK-NEXT: |-FunctionDecl [[ADDR_91:0x[a-z0-9]*]] col:5 implicit used also_after 'int (double &)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_92:0x[a-z0-9]*]] col:24 'double &' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_93:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_94:0x[a-z0-9]*]] 'int (double &)' {{.*}}Function [[ADDR_95:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int (double &)' -// CHECK-NEXT: |-FunctionDecl [[ADDR_95]] line:34:1 also_after[implementation={vendor(llvm)}] 'int (double &)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_93:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_94:0x[a-z0-9]*]] 'int (double &)' {{.*}}Function [[ADDR_95:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int (double &)' +// CHECK-NEXT: |-FunctionDecl [[ADDR_95]] line:34:1 also_after[implementation={vendor(amd)}] 'int (double &)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_92]] col:24 'double &' // CHECK-NEXT: | `-CompoundStmt [[ADDR_96:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_97:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_98:0x[a-z0-9]*]] 'int' 0 // CHECK-NEXT: |-FunctionDecl [[ADDR_99:0x[a-z0-9]*]] col:5 implicit also_after 'int (double &&)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_100:0x[a-z0-9]*]] col:25 'double &&' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_101:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_102:0x[a-z0-9]*]] 'int (double &&)' {{.*}}Function [[ADDR_103:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int (double &&)' -// CHECK-NEXT: |-FunctionDecl [[ADDR_103]] line:37:1 also_after[implementation={vendor(llvm)}] 'int (double &&)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_101:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_102:0x[a-z0-9]*]] 'int (double &&)' {{.*}}Function [[ADDR_103:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int (double &&)' +// CHECK-NEXT: |-FunctionDecl [[ADDR_103]] line:37:1 also_after[implementation={vendor(amd)}] 'int (double &&)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_100]] col:25 'double &&' // CHECK-NEXT: | `-CompoundStmt [[ADDR_104:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_105:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_106:0x[a-z0-9]*]] 'int' 3 // CHECK-NEXT: |-FunctionDecl [[ADDR_107:0x[a-z0-9]*]] col:5 implicit also_after 'int (short &)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_108:0x[a-z0-9]*]] col:23 'short &' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_109:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_110:0x[a-z0-9]*]] 'int (short &)' {{.*}}Function [[ADDR_111:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int (short &)' -// CHECK-NEXT: |-FunctionDecl [[ADDR_111]] line:40:1 also_after[implementation={vendor(llvm)}] 'int (short &)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_109:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_110:0x[a-z0-9]*]] 'int (short &)' {{.*}}Function [[ADDR_111:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int (short &)' +// CHECK-NEXT: |-FunctionDecl [[ADDR_111]] line:40:1 also_after[implementation={vendor(amd)}] 'int (short &)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_108]] col:23 'short &' // CHECK-NEXT: | `-CompoundStmt [[ADDR_112:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_113:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_114:0x[a-z0-9]*]] 'int' 5 // CHECK-NEXT: |-FunctionDecl [[ADDR_115:0x[a-z0-9]*]] col:5 implicit used also_after 'int (short &&)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_116:0x[a-z0-9]*]] col:24 'short &&' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_117:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_118:0x[a-z0-9]*]] 'int (short &&)' {{.*}}Function [[ADDR_119:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int (short &&)' -// CHECK-NEXT: |-FunctionDecl [[ADDR_119]] line:43:1 also_after[implementation={vendor(llvm)}] 'int (short &&)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_117:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_118:0x[a-z0-9]*]] 'int (short &&)' {{.*}}Function [[ADDR_119:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int (short &&)' +// CHECK-NEXT: |-FunctionDecl [[ADDR_119]] line:43:1 also_after[implementation={vendor(amd)}] 'int (short &&)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_116]] col:24 'short &&' // CHECK-NEXT: | `-CompoundStmt [[ADDR_120:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_121:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_122:0x[a-z0-9]*]] 'int' 0 -// CHECK-NEXT: |-FunctionDecl [[ADDR_70]] line:50:1 also_before[implementation={vendor(llvm)}] 'int &({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_70]] line:50:1 also_before[implementation={vendor(amd)}] 'int &({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_123:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_124:0x[a-z0-9]*]] // CHECK-NEXT: | `-DeclRefExpr [[ADDR_125:0x[a-z0-9]*]] 'int' {{.*}}Var [[ADDR_62]] 'Good' 'int' // CHECK-NEXT: |-FunctionDecl [[ADDR_126:0x[a-z0-9]*]] col:5 implicit also_before 'int (float &)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_127:0x[a-z0-9]*]] col:24 'float &' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_128:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_129:0x[a-z0-9]*]] 'int (float &)' {{.*}}Function [[ADDR_130:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int (float &)' -// CHECK-NEXT: |-FunctionDecl [[ADDR_130]] line:54:1 also_before[implementation={vendor(llvm)}] 'int (float &)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_128:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_129:0x[a-z0-9]*]] 'int (float &)' {{.*}}Function [[ADDR_130:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int (float &)' +// CHECK-NEXT: |-FunctionDecl [[ADDR_130]] line:54:1 also_before[implementation={vendor(amd)}] 'int (float &)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_127]] col:24 'float &' // CHECK-NEXT: | `-CompoundStmt [[ADDR_131:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_132:0x[a-z0-9]*]] @@ -300,8 +300,8 @@ int test(float &&f, short &&s) { // CHECK-NEXT: | |-CompoundStmt [[ADDR_135:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_136:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_137:0x[a-z0-9]*]] 'int' 7 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_138:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_78]] 'int ({{.*}})' {{.*}}Function [[ADDR_79]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_138:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_78]] 'int ({{.*}})' {{.*}}Function [[ADDR_79]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_139:0x[a-z0-9]*]] line:62:5 also_after 'int (int)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_140:0x[a-z0-9]*]] col:19 'int' // CHECK-NEXT: | `-CompoundStmt [[ADDR_141:0x[a-z0-9]*]] @@ -312,15 +312,15 @@ int test(float &&f, short &&s) { // CHECK-NEXT: | |-CompoundStmt [[ADDR_146:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_147:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_148:0x[a-z0-9]*]] 'int' 9 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_149:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_94]] 'int (double &)' {{.*}}Function [[ADDR_95]] 'also_after[implementation={vendor(llvm)}]' 'int (double &)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_149:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_94]] 'int (double &)' {{.*}}Function [[ADDR_95]] 'also_after[implementation={vendor(amd)}]' 'int (double &)' // CHECK-NEXT: |-FunctionDecl [[ADDR_150:0x[a-z0-9]*]] prev [[ADDR_115]] line:68:5 used also_after 'int (short &&)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_151:0x[a-z0-9]*]] col:24 'short &&' // CHECK-NEXT: | |-CompoundStmt [[ADDR_152:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_153:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_154:0x[a-z0-9]*]] 'int' 10 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_155:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_118]] 'int (short &&)' {{.*}}Function [[ADDR_119]] 'also_after[implementation={vendor(llvm)}]' 'int (short &&)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_155:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_118]] 'int (short &&)' {{.*}}Function [[ADDR_119]] 'also_after[implementation={vendor(amd)}]' 'int (short &&)' // CHECK-NEXT: |-FunctionDecl [[ADDR_156:0x[a-z0-9]*]] line:72:5 used test1 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_157:0x[a-z0-9]*]] // CHECK-NEXT: | |-DeclStmt [[ADDR_158:0x[a-z0-9]*]] @@ -333,7 +333,7 @@ int test(float &&f, short &&s) { // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_165:0x[a-z0-9]*]] 'double' {{.*}}Var [[ADDR_159]] 'd' 'double' // CHECK-NEXT: | `-CallExpr [[ADDR_166:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | |-ImplicitCastExpr [[ADDR_167:0x[a-z0-9]*]] 'int (*)(double &)' -// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_94]] 'int (double &)' {{.*}}Function [[ADDR_95]] 'also_after[implementation={vendor(llvm)}]' 'int (double &)' +// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_94]] 'int (double &)' {{.*}}Function [[ADDR_95]] 'also_after[implementation={vendor(amd)}]' 'int (double &)' // CHECK-NEXT: | `-DeclRefExpr [[ADDR_165]] 'double' {{.*}}Var [[ADDR_159]] 'd' 'double' // CHECK-NEXT: |-FunctionDecl [[ADDR_168:0x[a-z0-9]*]] line:78:5 used test2 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_169:0x[a-z0-9]*]] @@ -347,7 +347,7 @@ int test(float &&f, short &&s) { // CHECK-NEXT: | | | `-DeclRefExpr [[ADDR_177:0x[a-z0-9]*]] 'int &({{.*}})' {{.*}}Function [[ADDR_64]] 'also_before' 'int &({{.*}})' // CHECK-NEXT: | | `-CallExpr [[ADDR_178:0x[a-z0-9]*]] 'int' lvalue // CHECK-NEXT: | | `-ImplicitCastExpr [[ADDR_179:0x[a-z0-9]*]] 'int &(*)({{.*}})' -// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_69]] 'int &({{.*}})' {{.*}}Function [[ADDR_70]] 'also_before[implementation={vendor(llvm)}]' 'int &({{.*}})' +// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_69]] 'int &({{.*}})' {{.*}}Function [[ADDR_70]] 'also_before[implementation={vendor(amd)}]' 'int &({{.*}})' // CHECK-NEXT: | `-UnaryOperator [[ADDR_180:0x[a-z0-9]*]] 'int *' prefix '&' cannot overflow // CHECK-NEXT: | `-DeclRefExpr [[ADDR_181:0x[a-z0-9]*]] 'int' {{.*}}Var [[ADDR_62]] 'Good' 'int' // CHECK-NEXT: |-FunctionDecl [[ADDR_182:0x[a-z0-9]*]] line:83:5 used test3 'int (float &&)' @@ -375,7 +375,7 @@ int test(float &&f, short &&s) { // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_204:0x[a-z0-9]*]] 'short' {{.*}}ParmVar [[ADDR_194]] 's' 'short &&' // CHECK-NEXT: | `-CallExpr [[ADDR_205:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | |-ImplicitCastExpr [[ADDR_206:0x[a-z0-9]*]] 'int (*)(short &&)' -// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_118]] 'int (short &&)' {{.*}}Function [[ADDR_119]] 'also_after[implementation={vendor(llvm)}]' 'int (short &&)' +// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_118]] 'int (short &&)' {{.*}}Function [[ADDR_119]] 'also_after[implementation={vendor(amd)}]' 'int (short &&)' // CHECK-NEXT: | `-CallExpr [[ADDR_201]] 'typename remove_reference::type':'short' xvalue // CHECK-NEXT: | |-ImplicitCastExpr [[ADDR_202]] 'typename remove_reference::type &&(*)(short &)' // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_203]] 'typename remove_reference::type &&(short &)' {{.*}}Function [[ADDR_52]] 'move' 'typename remove_reference::type &&(short &)' (FunctionTemplate [[ADDR_31]] 'move') diff --git a/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_1.cpp b/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_1.cpp index 0dfed6ffa240d..a71038272184f 100644 --- a/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_1.cpp +++ b/clang/test/AST/ast-dump-openmp-begin-declare-variant_template_1.cpp @@ -6,7 +6,7 @@ int also_before() { return 1; } -#pragma omp begin declare variant match(implementation={vendor(score(100):llvm)}) +#pragma omp begin declare variant match(implementation={vendor(score(100):amd)}) int also_after(void) { return 2; } @@ -17,7 +17,7 @@ int also_after(double) { return 0; } #pragma omp end declare variant -#pragma omp begin declare variant match(implementation={vendor(score(0):llvm)}) +#pragma omp begin declare variant match(implementation={vendor(score(0):amd)}) int also_before() { return 0; } @@ -56,34 +56,34 @@ int test() { // CHECK-NEXT: | |-CompoundStmt [[ADDR_1:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_2:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_3:0x[a-z0-9]*]] 'int' 1 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_4:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(0): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_6:0x[a-z0-9]*]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_7:0x[a-z0-9]*]] col:5 implicit also_after 'int ({{.*}})' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' -// CHECK-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_8:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9:0x[a-z0-9]*]] 'int ({{.*}})' Function [[ADDR_10:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_10]] line:10:1 also_after[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_11:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_12:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_13:0x[a-z0-9]*]] 'int' 2 // CHECK-NEXT: |-FunctionDecl [[ADDR_14:0x[a-z0-9]*]] col:5 implicit also_after 'int (int)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_15:0x[a-z0-9]*]] col:19 'int' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_16:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_17:0x[a-z0-9]*]] 'int (int)' Function [[ADDR_18:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int (int)' -// CHECK-NEXT: |-FunctionDecl [[ADDR_18]] line:13:1 also_after[implementation={vendor(llvm)}] 'int (int)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_16:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_17:0x[a-z0-9]*]] 'int (int)' Function [[ADDR_18:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int (int)' +// CHECK-NEXT: |-FunctionDecl [[ADDR_18]] line:13:1 also_after[implementation={vendor(amd)}] 'int (int)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_15]] col:19 'int' // CHECK-NEXT: | `-CompoundStmt [[ADDR_19:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_20:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_21:0x[a-z0-9]*]] 'int' 3 // CHECK-NEXT: |-FunctionDecl [[ADDR_22:0x[a-z0-9]*]] col:5 implicit used also_after 'int (double)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_23:0x[a-z0-9]*]] col:22 'double' -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_24:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_25:0x[a-z0-9]*]] 'int (double)' Function [[ADDR_26:0x[a-z0-9]*]] 'also_after[implementation={vendor(llvm)}]' 'int (double)' -// CHECK-NEXT: |-FunctionDecl [[ADDR_26]] line:16:1 also_after[implementation={vendor(llvm)}] 'int (double)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_24:0x[a-z0-9]*]] <> Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_25:0x[a-z0-9]*]] 'int (double)' Function [[ADDR_26:0x[a-z0-9]*]] 'also_after[implementation={vendor(amd)}]' 'int (double)' +// CHECK-NEXT: |-FunctionDecl [[ADDR_26]] line:16:1 also_after[implementation={vendor(amd)}] 'int (double)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_23]] col:22 'double' // CHECK-NEXT: | `-CompoundStmt [[ADDR_27:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_28:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_29:0x[a-z0-9]*]] 'int' 0 -// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:21:1 also_before[implementation={vendor(llvm)}] 'int ({{.*}})' +// CHECK-NEXT: |-FunctionDecl [[ADDR_6]] line:21:1 also_before[implementation={vendor(amd)}] 'int ({{.*}})' // CHECK-NEXT: | `-CompoundStmt [[ADDR_30:0x[a-z0-9]*]] // CHECK-NEXT: | `-ReturnStmt [[ADDR_31:0x[a-z0-9]*]] // CHECK-NEXT: | `-IntegerLiteral [[ADDR_32:0x[a-z0-9]*]] 'int' 0 @@ -91,22 +91,22 @@ int test() { // CHECK-NEXT: | |-CompoundStmt [[ADDR_34:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_35:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_36:0x[a-z0-9]*]] 'int' 4 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_37:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_37:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_9]] 'int ({{.*}})' Function [[ADDR_10]] 'also_after[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: |-FunctionDecl [[ADDR_38:0x[a-z0-9]*]] prev [[ADDR_14]] line:29:5 also_after 'int (int)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_39:0x[a-z0-9]*]] col:19 'int' // CHECK-NEXT: | |-CompoundStmt [[ADDR_40:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_41:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_42:0x[a-z0-9]*]] 'int' 5 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_43:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_17]] 'int (int)' Function [[ADDR_18]] 'also_after[implementation={vendor(llvm)}]' 'int (int)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_43:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_17]] 'int (int)' Function [[ADDR_18]] 'also_after[implementation={vendor(amd)}]' 'int (int)' // CHECK-NEXT: |-FunctionDecl [[ADDR_44:0x[a-z0-9]*]] prev [[ADDR_22]] line:32:5 used also_after 'int (double)' // CHECK-NEXT: | |-ParmVarDecl [[ADDR_45:0x[a-z0-9]*]] col:22 'double' // CHECK-NEXT: | |-CompoundStmt [[ADDR_46:0x[a-z0-9]*]] // CHECK-NEXT: | | `-ReturnStmt [[ADDR_47:0x[a-z0-9]*]] // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_48:0x[a-z0-9]*]] 'int' 6 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_49:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): llvm)} -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_25]] 'int (double)' Function [[ADDR_26]] 'also_after[implementation={vendor(llvm)}]' 'int (double)' +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_49:0x[a-z0-9]*]] <> Inherited Implicit implementation={vendor(score(100): amd)} +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_25]] 'int (double)' Function [[ADDR_26]] 'also_after[implementation={vendor(amd)}]' 'int (double)' // CHECK-NEXT: |-FunctionTemplateDecl [[ADDR_50:0x[a-z0-9]*]] line:37:5 test1 // CHECK-NEXT: | |-TemplateTypeParmDecl [[ADDR_51:0x[a-z0-9]*]] col:19 referenced typename depth 0 index 0 T // CHECK-NEXT: | |-FunctionDecl [[ADDR_52:0x[a-z0-9]*]] line:37:5 test1 'int ({{.*}})' @@ -129,7 +129,7 @@ int test() { // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_58]] 'int' 0 // CHECK-NEXT: | `-CallExpr [[ADDR_68:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | |-ImplicitCastExpr [[ADDR_69:0x[a-z0-9]*]] 'int (*)(double)' -// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_25]] 'int (double)' Function [[ADDR_26]] 'also_after[implementation={vendor(llvm)}]' 'int (double)' +// CHECK-NEXT: | | `-DeclRefExpr [[ADDR_25]] 'int (double)' Function [[ADDR_26]] 'also_after[implementation={vendor(amd)}]' 'int (double)' // CHECK-NEXT: | `-CXXFunctionalCastExpr [[ADDR_66]] 'double' functional cast to double // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_67]] 'double' part_of_explicit_cast // CHECK-NEXT: | `-IntegerLiteral [[ADDR_58]] 'int' 0 @@ -158,7 +158,7 @@ int test() { // CHECK-NEXT: | | `-DeclRefExpr [[ADDR_89:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_0]] 'also_before' 'int ({{.*}})' // CHECK-NEXT: | `-CallExpr [[ADDR_90:0x[a-z0-9]*]] 'int' // CHECK-NEXT: | `-ImplicitCastExpr [[ADDR_91:0x[a-z0-9]*]] 'int (*)({{.*}})' -// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(llvm)}]' 'int ({{.*}})' +// CHECK-NEXT: | `-DeclRefExpr [[ADDR_5]] 'int ({{.*}})' Function [[ADDR_6]] 'also_before[implementation={vendor(amd)}]' 'int ({{.*}})' // CHECK-NEXT: `-FunctionDecl [[ADDR_92:0x[a-z0-9]*]] line:50:5 test 'int ({{.*}})' // CHECK-NEXT: `-CompoundStmt [[ADDR_93:0x[a-z0-9]*]] // CHECK-NEXT: `-ReturnStmt [[ADDR_94:0x[a-z0-9]*]] diff --git a/clang/test/AST/ast-dump-openmp-declare-variant-extensions.c b/clang/test/AST/ast-dump-openmp-declare-variant-extensions.c index c2a863b16b3f7..31a5b0e9e0798 100644 --- a/clang/test/AST/ast-dump-openmp-declare-variant-extensions.c +++ b/clang/test/AST/ast-dump-openmp-declare-variant-extensions.c @@ -37,8 +37,8 @@ int base6(void) { return 0; } #pragma omp declare variant(not_picked2) match(implementation={extension(match_none)}, device={kind(gpu, cpu)}) int base7(void) { return 0; } -#pragma omp declare variant(not_picked3) match(implementation={vendor(llvm), extension(match_any)}, device={kind(fpga, gpu)}) -int base8(void) { return 0; } +#pragma omp declare variant(not_picked3) match(implementation={vendor(amd), extension(match_any)}, device={kind(fpga, gpu)}) +int base8() { return 0; } #pragma omp declare variant(not_picked4) match(user={condition(1)}, implementation={extension(match_none)}, device={kind(gpu, fpga)}) int base9(void) { return 0; } @@ -162,11 +162,11 @@ int test(void) { // CHECK-NEXT: | | `-IntegerLiteral [[ADDR_73:0x[a-z0-9]*]] 'int' 0 // CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_74:0x[a-z0-9]*]] Implicit implementation={extension(match_none)}, device={kind(gpu, cpu)} // CHECK-NEXT: | `-DeclRefExpr [[ADDR_75:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_26]] 'not_picked2' 'int ({{.*}})' non_odr_use_unevaluated -// CHECK-NEXT: |-FunctionDecl [[ADDR_76:0x[a-z0-9]*]] col:5 used base8 'int ({{.*}})' -// CHECK-NEXT: | |-CompoundStmt [[ADDR_77:0x[a-z0-9]*]] -// CHECK-NEXT: | | `-ReturnStmt [[ADDR_78:0x[a-z0-9]*]] -// CHECK-NEXT: | | `-IntegerLiteral [[ADDR_79:0x[a-z0-9]*]] 'int' 0 -// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_80:0x[a-z0-9]*]] Implicit implementation={vendor(llvm), extension(match_any)}, device={kind(fpga, gpu)} +// CHECK-NEXT: |-FunctionDecl [[ADDR_76:0x[a-z0-9]*]] col:5 used base8 'int ({{.*}})' +// CHECK-NEXT: | |-CompoundStmt [[ADDR_77:0x[a-z0-9]*]] +// CHECK-NEXT: | | `-ReturnStmt [[ADDR_78:0x[a-z0-9]*]] +// CHECK-NEXT: | | `-IntegerLiteral [[ADDR_79:0x[a-z0-9]*]] 'int' 0 +// CHECK-NEXT: | `-OMPDeclareVariantAttr [[ADDR_80:0x[a-z0-9]*]] Implicit implementation={vendor(amd), extension(match_any)}, device={kind(fpga, gpu)} // CHECK-NEXT: | `-DeclRefExpr [[ADDR_81:0x[a-z0-9]*]] 'int ({{.*}})' {{.*}}Function [[ADDR_30]] 'not_picked3' 'int ({{.*}})' non_odr_use_unevaluated // CHECK-NEXT: |-FunctionDecl [[ADDR_82:0x[a-z0-9]*]] col:5 used base9 'int ({{.*}})' // CHECK-NEXT: | |-CompoundStmt [[ADDR_83:0x[a-z0-9]*]] diff --git a/clang/test/AST/ast-print-openacc-cache-construct.cpp b/clang/test/AST/ast-print-openacc-cache-construct.cpp index 26dd1333ee9ed..c1a8b7a66eaa7 100644 --- a/clang/test/AST/ast-print-openacc-cache-construct.cpp +++ b/clang/test/AST/ast-print-openacc-cache-construct.cpp @@ -1,5 +1,4 @@ // RUN: %clang_cc1 -fopenacc -ast-print %s -o - | FileCheck %s - void foo() { int Array[5]; #pragma acc loop diff --git a/clang/test/AST/ast-print-openacc-declare-construct.cpp b/clang/test/AST/ast-print-openacc-declare-construct.cpp index 2a61b08c5500b..9f95563f1fa9e 100644 --- a/clang/test/AST/ast-print-openacc-declare-construct.cpp +++ b/clang/test/AST/ast-print-openacc-declare-construct.cpp @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -fopenacc -ast-print %s -o - | FileCheck %s +// flang decided that we would NOT accept -fopenacc downsteam int *Global, *Global2; int GlobalArray[5]; diff --git a/clang/test/AST/ast-print-openacc-routine-construct.cpp b/clang/test/AST/ast-print-openacc-routine-construct.cpp index be8d95387d2ca..7f6f6908e12c9 100644 --- a/clang/test/AST/ast-print-openacc-routine-construct.cpp +++ b/clang/test/AST/ast-print-openacc-routine-construct.cpp @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -fopenacc -ast-print %s -o - | FileCheck %s - +// REQUIRES: OSStability auto Lambda = [](){}; // CHECK: auto Lambda = []() { #pragma acc routine(Lambda) worker bind(identifier) diff --git a/clang/test/Analysis/MismatchedDeallocator-path-notes.cpp b/clang/test/Analysis/MismatchedDeallocator-path-notes.cpp index 814ad3a21b0d1..6e82c67c58fb5 100644 --- a/clang/test/Analysis/MismatchedDeallocator-path-notes.cpp +++ b/clang/test/Analysis/MismatchedDeallocator-path-notes.cpp @@ -2,6 +2,7 @@ // RUN: %clang_analyze_cc1 -analyzer-checker=core,unix.MismatchedDeallocator -analyzer-output=plist %s -o %t.plist // RUN: tail -n +11 %t.plist | %normalize_plist | diff -ub %S/copypaste/Inputs/expected-plists/MismatchedDeallocator-path-notes.cpp.plist - +// XFAIL: * void changePointee(int *p); int *allocIntArray(unsigned c) { return new int[c]; // expected-note {{Memory is allocated}} diff --git a/clang/test/Analysis/llvm-conventions.cpp b/clang/test/Analysis/llvm-conventions.cpp index e8588db60f430..05d31dda3cb56 100644 --- a/clang/test/Analysis/llvm-conventions.cpp +++ b/clang/test/Analysis/llvm-conventions.cpp @@ -71,9 +71,9 @@ class StringRef { StringRef>::type & operator=(T &&Str) = delete; operator std::string() const; - bool startswith(StringRef Prefix) const; + bool starts_with(StringRef Prefix) const; bool startswith_lower(StringRef Prefix) const; - bool endswith(StringRef Suffix) const; + bool ends_with(StringRef Suffix) const; bool endswith_lower(StringRef Suffix) const; size_t find(char C, size_t From = 0) const; size_t find_lower(char C, size_t From = 0) const; diff --git a/clang/test/Analysis/malloc-plist.c b/clang/test/Analysis/malloc-plist.c index caceaaf612bfe..ab62735c27f06 100644 --- a/clang/test/Analysis/malloc-plist.c +++ b/clang/test/Analysis/malloc-plist.c @@ -2,6 +2,7 @@ // RUN: %clang_analyze_cc1 -fblocks -analyzer-checker=core,unix.Malloc -analyzer-output=plist -verify -o %t -analyzer-config eagerly-assume=false %s // RUN: tail -n +11 %t | %normalize_plist | diff -ub %S/Inputs/expected-plists/malloc-plist.c.plist - +// XFAIL: * typedef __typeof(sizeof(int)) size_t; void *malloc(size_t); void free(void *); diff --git a/clang/test/CMakeLists.txt b/clang/test/CMakeLists.txt index bcb6bd68fafc2..505bf82a5fc90 100644 --- a/clang/test/CMakeLists.txt +++ b/clang/test/CMakeLists.txt @@ -6,6 +6,7 @@ llvm_canonicalize_cmake_booleans( CLANG_BUILD_EXAMPLES CLANG_BUILT_STANDALONE CLANG_DEFAULT_PIE_ON_LINUX + CLANG_ENABLE_AMDCLANG CLANG_ENABLE_STATIC_ANALYZER CLANG_PLUGIN_SUPPORT CLANG_SPAWN_CC1 diff --git a/clang/test/CXX/dcl.decl/dcl.fct.def/dcl.fct.def.general/p8.cpp b/clang/test/CXX/dcl.decl/dcl.fct.def/dcl.fct.def.general/p8.cpp index ff5d3dec30832..ed852e7eebb28 100644 --- a/clang/test/CXX/dcl.decl/dcl.fct.def/dcl.fct.def.general/p8.cpp +++ b/clang/test/CXX/dcl.decl/dcl.fct.def/dcl.fct.def.general/p8.cpp @@ -5,11 +5,11 @@ using size_t = decltype(sizeof(0)); template struct check; template struct check {}; -constexpr bool startswith(const char *p, const char *q) { - return !*q || (*p == *q && startswith(p + 1, q + 1)); +constexpr bool starts_with(const char *p, const char *q) { + return !*q || (*p == *q && starts_with(p + 1, q + 1)); } constexpr bool contains(const char *p, const char *q) { - return *p && (startswith(p, q) || contains(p + 1, q)); + return *p && (starts_with(p, q) || contains(p + 1, q)); } void foo() { diff --git a/clang/test/CXX/expr/expr.const/p2-0x.cpp b/clang/test/CXX/expr/expr.const/p2-0x.cpp index 8401d3033eda9..f0d299e896d18 100644 --- a/clang/test/CXX/expr/expr.const/p2-0x.cpp +++ b/clang/test/CXX/expr/expr.const/p2-0x.cpp @@ -282,16 +282,6 @@ namespace UndefinedBehavior { constexpr float f10 = f2 - f2; // expected-error {{constant expression}} expected-note {{produces a NaN}} constexpr float f11 = f2 + f4; // expected-error {{constant expression}} expected-note {{produces a NaN}} constexpr float f12 = f2 / f2; // expected-error {{constant expression}} expected-note {{produces a NaN}} -#pragma float_control(push) -#pragma float_control(except, on) -constexpr float pi = 3.14f; -constexpr unsigned ubig = 0xFFFFFFFF; -constexpr float ce = 1.0 / 3.0; // not-expected-error {{constant expression}} not-expected-note {{floating point arithmetic suppressed in strict evaluation modes}} -constexpr int ci = (int) pi; -constexpr float fbig = (float) ubig; // not-expected-error {{constant expression}} not-expected-note {{floating point arithmetic suppressed in strict evaluation modes}} -constexpr float fabspi = __builtin_fabs(pi); // no error expected -constexpr float negpi = -pi; // expect no error on unary operator -#pragma float_control(pop) static_assert(!isinf(f1), ""); static_assert(isinf(f2), ""); static_assert(!isinf(f3), ""); diff --git a/clang/test/CXX/temp/temp.spec/temp.expl.spec/p12.cpp b/clang/test/CXX/temp/temp.spec/temp.expl.spec/p12.cpp index 9717fbf419b0a..34d1738362835 100644 --- a/clang/test/CXX/temp/temp.spec/temp.expl.spec/p12.cpp +++ b/clang/test/CXX/temp/temp.spec/temp.expl.spec/p12.cpp @@ -1,6 +1,7 @@ // RUN: %clang_cc1 -fsyntax-only -std=c++11 -verify=expected,cxx11 %s // RUN: %clang_cc1 -fsyntax-only -std=c++14 -verify=expected,since-cxx14 %s +// XFAIL: * struct A { template void f0(); @@ -31,7 +32,7 @@ constexpr void A::f1(); // since-cxx14-error {{no function template matche // members of a class template explicitly specialized for an implicitly // instantiated specialization of that template. template -struct B { // #defined-here +struct B { void g0(); // since-cxx14-note {{previous declaration is here}} // cxx11-note@-1 {{member declaration does not match because it is not const qualified}} @@ -49,13 +50,11 @@ template<> constexpr void B::g0(); // since-cxx14-error {{constexpr declaration of 'g0' follows non-constexpr declaration}} // cxx11-error@-1 {{out-of-line declaration of 'g0' does not match any declaration in 'B'}} // cxx11-warning@-2 {{'constexpr' non-static member function will not be implicitly 'const' in C++14; add 'const'}} - // expected-note@#defined-here {{defined here}} template<> constexpr void B::g1(); // since-cxx14-error {{out-of-line declaration of 'g1' does not match any declaration in 'B'}} // cxx11-error@-1 {{constexpr declaration of 'g1' follows non-constexpr declaration}} // cxx11-warning@-2 {{'constexpr' non-static member function will not be implicitly 'const' in C++14; add 'const'}} - // expected-note@#defined-here {{defined here}} template<> template @@ -68,3 +67,5 @@ template constexpr void B::h1(); // since-cxx14-error {{out-of-line declaration of 'h1' does not match any declaration in 'B'}} // cxx11-error@-1 {{constexpr declaration of 'h1' follows non-constexpr declaration}} // cxx11-warning@-2 {{'constexpr' non-static member function will not be implicitly 'const' in C++14; add 'const'}} + + diff --git a/clang/test/ClangScanDeps/multiple-commands.c b/clang/test/ClangScanDeps/multiple-commands.c index bb169ea10995a..6b93e1ff27f22 100644 --- a/clang/test/ClangScanDeps/multiple-commands.c +++ b/clang/test/ClangScanDeps/multiple-commands.c @@ -5,6 +5,7 @@ // We use an x86_64-apple-darwin target to avoid host-dependent behaviour in // the driver. Platforms without an integrated assembler have different commands // REQUIRES: x86-registered-target +// REQUIRES: jenkins-permissions-issue // RUN: rm -rf %t // RUN: split-file %s %t @@ -133,7 +134,7 @@ // CHECK-NEXT: "{{.*}}tu_save_temps_module.o" // CHECK: "{{.*}}tu_save_temps_module.s" // CHECK: ] -// CHECK-NEXT: "executable": "clang_tool" +// CHECK-NEXT: "executable": [[CLANG:"[^"]*clang"]] // CHECK: "input-file": "[[PREFIX]]{{.}}tu_save_temps_module.c" // CHECK-NEXT: } // CHECK-NEXT: ] diff --git a/clang/test/CodeGen/AArch64/soft-float-abi.c b/clang/test/CodeGen/AArch64/soft-float-abi.c index 0e1188117c21c..82be7a42b2f4d 100644 --- a/clang/test/CodeGen/AArch64/soft-float-abi.c +++ b/clang/test/CodeGen/AArch64/soft-float-abi.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -triple aarch64 -target-feature +fp-armv8 -target-abi aapcs -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD // RUN: %clang_cc1 -triple aarch64 -target-feature -fp-armv8 -target-abi aapcs-soft -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,SOFT - +// REQUIRES: aarch64-registered-target // See also llvm/test/CodeGen/AArch64/soft-float-abi.ll, which checks the LLVM // backend parts of the soft-float ABI. diff --git a/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c b/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c index b3a33190fc4fa..13f12515f5bd3 100644 --- a/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c +++ b/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c @@ -10,6 +10,8 @@ // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sve -target-feature +sme2 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// REQUIRES: aarch64-registered-target + #include #if defined(__ARM_FEATURE_SME) && defined(__ARM_FEATURE_SVE) diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c index 4993df20df143..fe062a9ddd3f8 100644 --- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c +++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c @@ -8,6 +8,8 @@ // RUN: -ffp-exception-behavior=strict \ // RUN: -Wall -Wno-unused -Werror -S %s -o - | FileCheck %s --check-prefix=CHECK-ASM +// XFAIL: * + #include volatile vector signed long long vsl; diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c index d5d15b4dea966..803f21cf040bc 100644 --- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c +++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c @@ -6,6 +6,8 @@ // RUN: -O2 -fzvector -flax-vector-conversions=none \ // RUN: -Wall -Wno-unused -Werror -S %s -o - | FileCheck %s --check-prefix=CHECK-ASM +// XFAIL: * + #include volatile vector signed char vsc; diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c index 25b3e0b68cd02..eb2cbd52eaac2 100644 --- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c +++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c @@ -8,6 +8,8 @@ // RUN: -ffp-exception-behavior=strict \ // RUN: -Wall -Wno-unused -Werror -S %s -o - | FileCheck %s --check-prefix=CHECK-ASM +// XFAIL: * + #include volatile vector signed long long vsl; diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c index c1ef178fcfaa9..80fd54bd67278 100644 --- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c +++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c @@ -6,6 +6,8 @@ // RUN: -O2 -fzvector -flax-vector-conversions=none \ // RUN: -Wall -Wno-unused -Werror -S %s -o - | FileCheck %s --check-prefix=CHECK-ASM +// XFAIL: * + #include volatile vector signed char vsc; diff --git a/clang/test/CodeGen/amdgpu-builtin-is-invocable.c b/clang/test/CodeGen/amdgpu-builtin-is-invocable.c new file mode 100644 index 0000000000000..b33e5ae041aee --- /dev/null +++ b/clang/test/CodeGen/amdgpu-builtin-is-invocable.c @@ -0,0 +1,64 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX900 %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx1010 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX1010 %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCNSPIRV %s + +// Test that, depending on triple and, if applicable, target-cpu, one of three +// things happens: +// 1) for gfx900 we emit an empty kernel (concrete target, lacks feature) +// 2) for gfx1010 we emit a call to trap (concrete target, has feature) +// 3) for AMDGCNSPIRV we emit llvm.amdgcn.has.gfx10-insts as a constant +// externally initialised bool global, and load from it to provide the +// condition to a br (abstract target) + +//. +// AMDGCNSPIRV: @llvm.amdgcn.has.gfx10-insts = external addrspace(1) externally_initialized constant i1 +//. +// AMDGCN-GFX900-LABEL: define dso_local void @foo( +// AMDGCN-GFX900-SAME: ) #[[ATTR0:[0-9]+]] { +// AMDGCN-GFX900-NEXT: [[ENTRY:.*:]] +// AMDGCN-GFX900-NEXT: ret void +// +// AMDGCN-GFX1010-LABEL: define dso_local void @foo( +// AMDGCN-GFX1010-SAME: ) #[[ATTR0:[0-9]+]] { +// AMDGCN-GFX1010-NEXT: [[ENTRY:.*:]] +// AMDGCN-GFX1010-NEXT: call void @llvm.trap() +// AMDGCN-GFX1010-NEXT: ret void +// +// AMDGCNSPIRV-LABEL: define spir_func void @foo( +// AMDGCNSPIRV-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] { +// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] +// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load i1, ptr addrspace(1) @llvm.amdgcn.has.gfx10-insts, align 1 +// AMDGCNSPIRV-NEXT: [[TOBOOL:%.*]] = icmp ne i1 [[TMP0]], false +// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL]], label %[[IF_THEN:.*]], label %[[IF_END:.*]] +// AMDGCNSPIRV: [[IF_THEN]]: +// AMDGCNSPIRV-NEXT: call addrspace(4) void @llvm.trap() +// AMDGCNSPIRV-NEXT: br label %[[IF_END]] +// AMDGCNSPIRV: [[IF_END]]: +// AMDGCNSPIRV-NEXT: ret void +// +void foo() { + if (__builtin_amdgcn_is_invocable(__builtin_amdgcn_permlanex16)) + return __builtin_trap(); +} +//. +// AMDGCN-GFX900: attributes #[[ATTR0]] = { convergent noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" } +//. +// AMDGCN-GFX1010: attributes #[[ATTR0]] = { convergent noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx1010" "target-features"="+16-bit-insts,+atomic-fmin-fmax-global-f32,+atomic-fmin-fmax-global-f64,+ci-insts,+dl-insts,+dpp,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32" } +// AMDGCN-GFX1010: attributes #[[ATTR1:[0-9]+]] = { cold noreturn nounwind memory(inaccessiblemem: write) } +//. +// AMDGCNSPIRV: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ashr-pk-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+bf16-cvt-insts,+bf16-trans-insts,+bf8-cvt-scale-insts,+bitop3-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot11-insts,+dot12-insts,+dot13-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+f16bf16-to-fp6bf6-cvt-scale-insts,+f32-to-f16bf16-cvt-sr-insts,+fp4-cvt-scale-insts,+fp6bf6-cvt-scale-insts,+fp8-conversion-insts,+fp8-cvt-scale-insts,+fp8-insts,+fp8e5m3-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx1250-insts,+gfx8-insts,+gfx9-insts,+gfx90a-insts,+gfx940-insts,+gfx950-insts,+gws,+image-insts,+mai-insts,+permlane16-swap,+permlane32-swap,+prng-inst,+s-memrealtime,+s-memtime-inst,+setprio-inc-wg-inst,+tanh-insts,+tensor-cvt-lut-insts,+transpose-load-f4f6-insts,+vmem-pref-insts,+vmem-to-lds-load-insts,+wavefrontsize32,+wavefrontsize64" } +// AMDGCNSPIRV: attributes #[[ATTR1:[0-9]+]] = { cold noreturn nounwind memory(inaccessiblemem: write) } +//. +// AMDGCN-GFX900: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600} +// AMDGCN-GFX900: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// AMDGCN-GFX900: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. +// AMDGCN-GFX1010: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600} +// AMDGCN-GFX1010: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// AMDGCN-GFX1010: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. +// AMDGCNSPIRV: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600} +// AMDGCNSPIRV: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// AMDGCNSPIRV: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. diff --git a/clang/test/CodeGen/amdgpu-builtin-processor-is.c b/clang/test/CodeGen/amdgpu-builtin-processor-is.c new file mode 100644 index 0000000000000..8241c98fc3c77 --- /dev/null +++ b/clang/test/CodeGen/amdgpu-builtin-processor-is.c @@ -0,0 +1,62 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX900 %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx1010 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX1010 %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCNSPIRV %s + +// Test that, depending on triple and, if applicable, target-cpu, one of three +// things happens: +// 1) for gfx900 we emit a call to trap (concrete target, matches) +// 2) for gfx1010 we emit an empty kernel (concrete target, does not match) +// 3) for AMDGCNSPIRV we emit llvm.amdgcn.is.gfx900 as a bool global, and +// load from it to provide the condition a br (abstract target) +//. +// AMDGCNSPIRV: @llvm.amdgcn.is.gfx900 = external addrspace(1) externally_initialized constant i1 +//. +// AMDGCN-GFX900-LABEL: define dso_local void @foo( +// AMDGCN-GFX900-SAME: ) #[[ATTR0:[0-9]+]] { +// AMDGCN-GFX900-NEXT: [[ENTRY:.*:]] +// AMDGCN-GFX900-NEXT: call void @llvm.trap() +// AMDGCN-GFX900-NEXT: ret void +// +// AMDGCN-GFX1010-LABEL: define dso_local void @foo( +// AMDGCN-GFX1010-SAME: ) #[[ATTR0:[0-9]+]] { +// AMDGCN-GFX1010-NEXT: [[ENTRY:.*:]] +// AMDGCN-GFX1010-NEXT: ret void +// +// AMDGCNSPIRV-LABEL: define spir_func void @foo( +// AMDGCNSPIRV-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] { +// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] +// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load i1, ptr addrspace(1) @llvm.amdgcn.is.gfx900, align 1 +// AMDGCNSPIRV-NEXT: [[TOBOOL:%.*]] = icmp ne i1 [[TMP0]], false +// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL]], label %[[IF_THEN:.*]], label %[[IF_END:.*]] +// AMDGCNSPIRV: [[IF_THEN]]: +// AMDGCNSPIRV-NEXT: call addrspace(4) void @llvm.trap() +// AMDGCNSPIRV-NEXT: br label %[[IF_END]] +// AMDGCNSPIRV: [[IF_END]]: +// AMDGCNSPIRV-NEXT: ret void +// +void foo() { + if (__builtin_amdgcn_processor_is("gfx900")) + return __builtin_trap(); +} +//. +// AMDGCN-GFX900: attributes #[[ATTR0]] = { convergent noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" } +// AMDGCN-GFX900: attributes #[[ATTR1:[0-9]+]] = { cold noreturn nounwind memory(inaccessiblemem: write) } +//. +// AMDGCN-GFX1010: attributes #[[ATTR0]] = { convergent noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx1010" "target-features"="+16-bit-insts,+atomic-fmin-fmax-global-f32,+atomic-fmin-fmax-global-f64,+ci-insts,+dl-insts,+dpp,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32" } +//. +// AMDGCNSPIRV: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ashr-pk-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+bf16-cvt-insts,+bf16-trans-insts,+bf8-cvt-scale-insts,+bitop3-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot11-insts,+dot12-insts,+dot13-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+f16bf16-to-fp6bf6-cvt-scale-insts,+f32-to-f16bf16-cvt-sr-insts,+fp4-cvt-scale-insts,+fp6bf6-cvt-scale-insts,+fp8-conversion-insts,+fp8-cvt-scale-insts,+fp8-insts,+fp8e5m3-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx1250-insts,+gfx8-insts,+gfx9-insts,+gfx90a-insts,+gfx940-insts,+gfx950-insts,+gws,+image-insts,+mai-insts,+permlane16-swap,+permlane32-swap,+prng-inst,+s-memrealtime,+s-memtime-inst,+setprio-inc-wg-inst,+tanh-insts,+tensor-cvt-lut-insts,+transpose-load-f4f6-insts,+vmem-pref-insts,+vmem-to-lds-load-insts,+wavefrontsize32,+wavefrontsize64" } +// AMDGCNSPIRV: attributes #[[ATTR1:[0-9]+]] = { cold noreturn nounwind memory(inaccessiblemem: write) } +//. +// AMDGCN-GFX900: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600} +// AMDGCN-GFX900: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// AMDGCN-GFX900: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. +// AMDGCN-GFX1010: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600} +// AMDGCN-GFX1010: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// AMDGCN-GFX1010: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. +// AMDGCNSPIRV: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600} +// AMDGCNSPIRV: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// AMDGCNSPIRV: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. diff --git a/clang/test/CodeGen/amdgpu-feature-builtins-invalid-use.cpp b/clang/test/CodeGen/amdgpu-feature-builtins-invalid-use.cpp new file mode 100644 index 0000000000000..78f18d3a37b46 --- /dev/null +++ b/clang/test/CodeGen/amdgpu-feature-builtins-invalid-use.cpp @@ -0,0 +1,48 @@ +// RUN: not %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm %s -o - 2>&1 | FileCheck %s +// RUN: not %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm %s -o - 2>&1 | FileCheck %s + +bool predicate(bool x); +void pass_by_value(__amdgpu_feature_predicate_t x); + +void invalid_uses(int *p, int x, const __amdgpu_feature_predicate_t &lv, + __amdgpu_feature_predicate_t &&rv) { + // CHECK: error: 'a' has type __amdgpu_feature_predicate_t, which is not constructible + __amdgpu_feature_predicate_t a; + // CHECK: error: 'b' has type __amdgpu_feature_predicate_t, which is not constructible + __amdgpu_feature_predicate_t b = __builtin_amdgcn_processor_is("gfx906"); + // CHECK: error: 'c' has type __amdgpu_feature_predicate_t, which is not constructible + __amdgpu_feature_predicate_t c = lv; + // CHECK: error: 'd' has type __amdgpu_feature_predicate_t, which is not constructible + __amdgpu_feature_predicate_t d = rv; + // CHECK: error: '__builtin_amdgcn_processor_is("gfx906")' must be explicitly cast to 'bool'; however, please note that this is almost always an error and that it prevents the effective guarding of target dependent code, and thus should be avoided + bool invalid_use_in_init_0 = __builtin_amdgcn_processor_is("gfx906"); + // CHECK: error: 'x' has type __amdgpu_feature_predicate_t, which is not constructible + pass_by_value(__builtin_amdgcn_processor_is("gfx906")); + // CHECK: error: '__builtin_amdgcn_is_invocable(__builtin_amdgcn_s_sleep_var)' must be explicitly cast to 'bool'; however, please note that this is almost always an error and that it prevents the effective guarding of target dependent code, and thus should be avoided + bool invalid_use_in_init_1 = __builtin_amdgcn_is_invocable(__builtin_amdgcn_s_sleep_var); + // CHECK: error: '__builtin_amdgcn_processor_is("gfx906")' must be explicitly cast to 'bool'; however, please note that this is almost always an error and that it prevents the effective guarding of target dependent code, and thus should be avoided + if (bool invalid_use_in_init_2 = __builtin_amdgcn_processor_is("gfx906")) return; + // CHECK: error: '__builtin_amdgcn_processor_is("gfx1200")' must be explicitly cast to 'bool'; however, please note that this is almost always an error and that it prevents the effective guarding of target dependent code, and thus should be avoided + if (predicate(__builtin_amdgcn_processor_is("gfx1200"))) __builtin_amdgcn_s_sleep_var(x); +} + +void invalid_invocations(int x, const char* str) { + // CHECK: error: the argument to __builtin_amdgcn_processor_is must be a valid AMDGCN processor identifier; 'not_an_amdgcn_gfx_id' is not valid + // CHECK-DAG: note: valid AMDGCN processor identifiers are: {{.*}}gfx{{.*}} + if (__builtin_amdgcn_processor_is("not_an_amdgcn_gfx_id")) return; + // CHECK: error: the argument to __builtin_amdgcn_processor_is must be a string literal + if (__builtin_amdgcn_processor_is(str)) return; + // CHECK: error: the argument to __builtin_amdgcn_is_invocable must be either a target agnostic builtin or an AMDGCN target specific builtin; {{.*}}__builtin_amdgcn_s_sleep_var{{.*}} is not valid + if (__builtin_amdgcn_is_invocable("__builtin_amdgcn_s_sleep_var")) return; + // CHECK: error: the argument to __builtin_amdgcn_is_invocable must be either a target agnostic builtin or an AMDGCN target specific builtin; {{.*}}str{{.*}} is not valid + else if (__builtin_amdgcn_is_invocable(str)) return; + // CHECK: error: the argument to __builtin_amdgcn_is_invocable must be either a target agnostic builtin or an AMDGCN target specific builtin; {{.*}}x{{.*}} is not valid + else if (__builtin_amdgcn_is_invocable(x)) return; + // CHECK: error: use of undeclared identifier '__builtin_ia32_pause' + else if (__builtin_amdgcn_is_invocable(__builtin_ia32_pause)) return; +} + +bool return_needs_cast() { + // CHECK: error: '__builtin_amdgcn_processor_is("gfx900")' must be explicitly cast to 'bool'; however, please note that this is almost always an error and that it prevents the effective guarding of target dependent code, and thus should be avoided + return __builtin_amdgcn_processor_is("gfx900"); +} diff --git a/clang/test/CodeGen/amdgpu-variadic-call.c b/clang/test/CodeGen/amdgpu-variadic-call.c index 17eda215211a2..5c6ad8094d141 100644 --- a/clang/test/CodeGen/amdgpu-variadic-call.c +++ b/clang/test/CodeGen/amdgpu-variadic-call.c @@ -137,22 +137,6 @@ void one_f16a(int f0, double f1, _Float16 v0) sink_2(f1, f0, v0); } -// CHECK-LABEL: define {{[^@]+}}@one_f16b -// CHECK-SAME: (i32 noundef [[F0:%.*]], double noundef [[F1:%.*]], half noundef [[V0:%.*]]) local_unnamed_addr #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[CONV:%.*]] = fpext half [[V0]] to double -// CHECK-NEXT: tail call void (...) @sink_0(double noundef [[CONV]]) #[[ATTR2]] -// CHECK-NEXT: tail call void (i32, ...) @sink_1(i32 noundef [[F0]], double noundef [[CONV]]) #[[ATTR2]] -// CHECK-NEXT: tail call void (double, i32, ...) @sink_2(double noundef [[F1]], i32 noundef [[F0]], double noundef [[CONV]]) #[[ATTR2]] -// CHECK-NEXT: ret void -// -void one_f16b(int f0, double f1, __fp16 v0) -{ - sink_0(v0); - sink_1(f0, v0); - sink_2(f1, f0, v0); -} - // CHECK-LABEL: define {{[^@]+}}@one_f16c // CHECK-SAME: (i32 noundef [[F0:%.*]], double noundef [[F1:%.*]], bfloat noundef [[V0:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-NEXT: entry: diff --git a/clang/test/CodeGen/asan_globals_symbols.cpp b/clang/test/CodeGen/asan_globals_symbols.cpp new file mode 100644 index 0000000000000..d53afb2433b17 --- /dev/null +++ b/clang/test/CodeGen/asan_globals_symbols.cpp @@ -0,0 +1,15 @@ +// RUN: %clang_cc1 -S -x c++ -std=c++11 -triple x86_64-linux \ +// RUN: -fsanitize=address -o %t.out %s +// RUN: FileCheck %s --input-file=%t.out --check-prefix=CHECK-A + +// CHECK-A: myGlobal: +// CHECK-A: .size myGlobal, 4 +// CHECK-A: myGlobal__sanitized_padded_global: +// CHECK-A .size myGlobal__sanitized_padded_global, 32 + +int myGlobal; + +int main() { + myGlobal = 0; + return 0; +} diff --git a/clang/test/CodeGen/asan_globals_symbols_ir_attribute.cpp b/clang/test/CodeGen/asan_globals_symbols_ir_attribute.cpp new file mode 100644 index 0000000000000..f8ba5eb737696 --- /dev/null +++ b/clang/test/CodeGen/asan_globals_symbols_ir_attribute.cpp @@ -0,0 +1,15 @@ +// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -fsanitize=address -emit-llvm -o - | FileCheck -check-prefix=CHECK-ASAN %s + +// CHECK-ASAN: @myGlobal1 = global { i32, [28 x i8] } zeroinitializer, align 32 #[[ATTR0:[0-9]+]] +// CHECK-ASAN: @myGlobal2 = global i32 0, no_sanitize_address, align 4 +// CHECK-NOT: #[[ATTR1:[0-9]+]] +// CHECK-ASAN: attributes #[[ATTR0]] = { sanitized_padded_global } + +int myGlobal1; +int __attribute__((no_sanitize("address"))) myGlobal2; + +int main() { + myGlobal1 = 0; + myGlobal2 = 0; + return 0; +} diff --git a/clang/test/CodeGen/debug-info-block-expr-heterogeneous-dwarf.c b/clang/test/CodeGen/debug-info-block-expr-heterogeneous-dwarf.c new file mode 100644 index 0000000000000..6b2e394b16e7d --- /dev/null +++ b/clang/test/CodeGen/debug-info-block-expr-heterogeneous-dwarf.c @@ -0,0 +1,284 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 +// RUN: %clang_cc1 -fblocks -debug-info-kind=limited -gheterogeneous-dwarf -emit-llvm -disable-llvm-verifier -o - %s | FileCheck %s +// RUN: %clang_cc1 -DDEAD_CODE -fblocks -debug-info-kind=limited -gheterogeneous-dwarf -emit-llvm -disable-llvm-verifier -o - %s | FileCheck --check-prefix=DEADCODE %s + +typedef void (^BlockTy)(); +void escapeFunc(BlockTy); +typedef void (^BlockTy)(); +void noEscapeFunc(__attribute__((noescape)) BlockTy); + +// Verify that the desired DIExpression are generated for escaping (i.e, not +// 'noescape') blocks. +// CHECK-LABEL: define dso_local void @test_escape_func( +// CHECK-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG5:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[ESCAPE_VAR:%.*]] = alloca [[STRUCT___BLOCK_BYREF_ESCAPE_VAR:%.*]], align 8 +// CHECK-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr }>, align 8 +// CHECK-NEXT: #dbg_declare(ptr [[ESCAPE_VAR]], [[META10:![0-9]+]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr), DIOpConstant(i64 8), DIOpByteOffset(ptr), DIOpDeref(ptr), DIOpConstant(i64 24), DIOpByteOffset(i32)), [[META12:![0-9]+]]) +// CHECK-NEXT: [[BYREF_ISA:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_ESCAPE_VAR]], ptr [[ESCAPE_VAR]], i32 0, i32 0, !dbg [[META12]] +// CHECK-NEXT: store ptr null, ptr [[BYREF_ISA]], align 8, !dbg [[META12]] +// CHECK-NEXT: [[BYREF_FORWARDING:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_ESCAPE_VAR]], ptr [[ESCAPE_VAR]], i32 0, i32 1, !dbg [[META12]] +// CHECK-NEXT: store ptr [[ESCAPE_VAR]], ptr [[BYREF_FORWARDING]], align 8, !dbg [[META12]] +// CHECK-NEXT: [[BYREF_FLAGS:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_ESCAPE_VAR]], ptr [[ESCAPE_VAR]], i32 0, i32 2, !dbg [[META12]] +// CHECK-NEXT: store i32 0, ptr [[BYREF_FLAGS]], align 8, !dbg [[META12]] +// CHECK-NEXT: [[BYREF_SIZE:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_ESCAPE_VAR]], ptr [[ESCAPE_VAR]], i32 0, i32 3, !dbg [[META12]] +// CHECK-NEXT: store i32 32, ptr [[BYREF_SIZE]], align 4, !dbg [[META12]] +// CHECK-NEXT: [[ESCAPE_VAR1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_ESCAPE_VAR]], ptr [[ESCAPE_VAR]], i32 0, i32 4, !dbg [[META12]] +// CHECK-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 0, !dbg [[DBG13:![0-9]+]] +// CHECK-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8, !dbg [[DBG13]] +// CHECK-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 1, !dbg [[DBG13]] +// CHECK-NEXT: store i32 1107296256, ptr [[BLOCK_FLAGS]], align 8, !dbg [[DBG13]] +// CHECK-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 2, !dbg [[DBG13]] +// CHECK-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4, !dbg [[DBG13]] +// CHECK-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 3, !dbg [[DBG13]] +// CHECK-NEXT: store ptr @__test_escape_func_block_invoke, ptr [[BLOCK_INVOKE]], align 8, !dbg [[DBG13]] +// CHECK-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 4, !dbg [[DBG13]] +// CHECK-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 8, !dbg [[DBG13]] +// CHECK-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 5, !dbg [[DBG13]] +// CHECK-NEXT: store ptr [[ESCAPE_VAR]], ptr [[BLOCK_CAPTURED]], align 8, !dbg [[DBG13]] +// CHECK-NEXT: call void @escapeFunc(ptr noundef [[BLOCK]]), !dbg [[DBG14:![0-9]+]] +// CHECK-NEXT: call void @_Block_object_dispose(ptr [[ESCAPE_VAR]], i32 8) #[[ATTR3:[0-9]+]], !dbg [[DBG15:![0-9]+]] +// CHECK-NEXT: ret void, !dbg [[DBG15]] +// +// DEADCODE-LABEL: define dso_local void @test_escape_func( +// DEADCODE-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG5:![0-9]+]] { +// DEADCODE-NEXT: [[ENTRY:.*:]] +// DEADCODE-NEXT: [[ESCAPE_VAR:%.*]] = alloca [[STRUCT___BLOCK_BYREF_ESCAPE_VAR:%.*]], align 8 +// DEADCODE-NEXT: #dbg_declare(ptr [[ESCAPE_VAR]], [[META10:![0-9]+]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr), DIOpConstant(i64 8), DIOpByteOffset(ptr), DIOpDeref(ptr), DIOpConstant(i64 24), DIOpByteOffset(i32)), [[META12:![0-9]+]]) +// DEADCODE-NEXT: [[BYREF_ISA:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_ESCAPE_VAR]], ptr [[ESCAPE_VAR]], i32 0, i32 0, !dbg [[META12]] +// DEADCODE-NEXT: store ptr null, ptr [[BYREF_ISA]], align 8, !dbg [[META12]] +// DEADCODE-NEXT: [[BYREF_FORWARDING:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_ESCAPE_VAR]], ptr [[ESCAPE_VAR]], i32 0, i32 1, !dbg [[META12]] +// DEADCODE-NEXT: store ptr [[ESCAPE_VAR]], ptr [[BYREF_FORWARDING]], align 8, !dbg [[META12]] +// DEADCODE-NEXT: [[BYREF_FLAGS:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_ESCAPE_VAR]], ptr [[ESCAPE_VAR]], i32 0, i32 2, !dbg [[META12]] +// DEADCODE-NEXT: store i32 0, ptr [[BYREF_FLAGS]], align 8, !dbg [[META12]] +// DEADCODE-NEXT: [[BYREF_SIZE:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_ESCAPE_VAR]], ptr [[ESCAPE_VAR]], i32 0, i32 3, !dbg [[META12]] +// DEADCODE-NEXT: store i32 32, ptr [[BYREF_SIZE]], align 4, !dbg [[META12]] +// DEADCODE-NEXT: [[ESCAPE_VAR1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_ESCAPE_VAR]], ptr [[ESCAPE_VAR]], i32 0, i32 4, !dbg [[META12]] +// DEADCODE-NEXT: call void @_Block_object_dispose(ptr [[ESCAPE_VAR]], i32 8) #[[ATTR3:[0-9]+]], !dbg [[DBG13:![0-9]+]] +// DEADCODE-NEXT: ret void, !dbg [[DBG13]] +// +void test_escape_func() { + __block int escape_var; +// Blocks in dead code branches still capture __block variables. +#ifdef DEAD_CODE + if (0) +#endif + escapeFunc(^{ (void)escape_var; }); +} + +// Verify that the desired DIExpression are generated for noescape blocks. +// CHECK-LABEL: define dso_local void @test_noescape_func( +// CHECK-SAME: ) #[[ATTR0]] !dbg [[DBG34:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[NOESCAPE_VAR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr }>, align 8 +// CHECK-NEXT: #dbg_declare(ptr [[NOESCAPE_VAR]], [[META36:![0-9]+]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), [[META37:![0-9]+]]) +// CHECK-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 0, !dbg [[DBG38:![0-9]+]] +// CHECK-NEXT: store ptr @_NSConcreteGlobalBlock, ptr [[BLOCK_ISA]], align 8, !dbg [[DBG38]] +// CHECK-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 1, !dbg [[DBG38]] +// CHECK-NEXT: store i32 1350565888, ptr [[BLOCK_FLAGS]], align 8, !dbg [[DBG38]] +// CHECK-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 2, !dbg [[DBG38]] +// CHECK-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4, !dbg [[DBG38]] +// CHECK-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 3, !dbg [[DBG38]] +// CHECK-NEXT: store ptr @__test_noescape_func_block_invoke, ptr [[BLOCK_INVOKE]], align 8, !dbg [[DBG38]] +// CHECK-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 4, !dbg [[DBG38]] +// CHECK-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8, !dbg [[DBG38]] +// CHECK-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 5, !dbg [[DBG38]] +// CHECK-NEXT: store ptr [[NOESCAPE_VAR]], ptr [[BLOCK_CAPTURED]], align 8, !dbg [[DBG38]] +// CHECK-NEXT: call void @noEscapeFunc(ptr noundef captures(none) [[BLOCK]]), !dbg [[DBG39:![0-9]+]] +// CHECK-NEXT: ret void, !dbg [[DBG40:![0-9]+]] +// +// DEADCODE-LABEL: define dso_local void @test_noescape_func( +// DEADCODE-SAME: ) #[[ATTR0]] !dbg [[DBG14:![0-9]+]] { +// DEADCODE-NEXT: [[ENTRY:.*:]] +// DEADCODE-NEXT: [[NOESCAPE_VAR:%.*]] = alloca i32, align 4 +// DEADCODE-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr }>, align 8 +// DEADCODE-NEXT: #dbg_declare(ptr [[NOESCAPE_VAR]], [[META16:![0-9]+]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), [[META17:![0-9]+]]) +// DEADCODE-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 0, !dbg [[DBG18:![0-9]+]] +// DEADCODE-NEXT: store ptr @_NSConcreteGlobalBlock, ptr [[BLOCK_ISA]], align 8, !dbg [[DBG18]] +// DEADCODE-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 1, !dbg [[DBG18]] +// DEADCODE-NEXT: store i32 1350565888, ptr [[BLOCK_FLAGS]], align 8, !dbg [[DBG18]] +// DEADCODE-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 2, !dbg [[DBG18]] +// DEADCODE-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4, !dbg [[DBG18]] +// DEADCODE-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 3, !dbg [[DBG18]] +// DEADCODE-NEXT: store ptr @__test_noescape_func_block_invoke, ptr [[BLOCK_INVOKE]], align 8, !dbg [[DBG18]] +// DEADCODE-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 4, !dbg [[DBG18]] +// DEADCODE-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 8, !dbg [[DBG18]] +// DEADCODE-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 5, !dbg [[DBG18]] +// DEADCODE-NEXT: store ptr [[NOESCAPE_VAR]], ptr [[BLOCK_CAPTURED]], align 8, !dbg [[DBG18]] +// DEADCODE-NEXT: call void @noEscapeFunc(ptr noundef captures(none) [[BLOCK]]), !dbg [[DBG19:![0-9]+]] +// DEADCODE-NEXT: ret void, !dbg [[DBG20:![0-9]+]] +// +void test_noescape_func() { + __block int noescape_var; + noEscapeFunc(^{ (void)noescape_var; }); +} + +// Verify that the desired DIExpression are generated for blocks. +// CHECK-LABEL: define dso_local void @test_local_block( +// CHECK-SAME: ) #[[ATTR0]] !dbg [[DBG45:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[BLOCK_VAR:%.*]] = alloca [[STRUCT___BLOCK_BYREF_BLOCK_VAR:%.*]], align 8 +// CHECK-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr }>, align 8 +// CHECK-NEXT: #dbg_declare(ptr [[BLOCK_VAR]], [[META47:![0-9]+]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr), DIOpConstant(i64 8), DIOpByteOffset(ptr), DIOpDeref(ptr), DIOpConstant(i64 24), DIOpByteOffset(i32)), [[META48:![0-9]+]]) +// CHECK-NEXT: [[BYREF_ISA:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_BLOCK_VAR]], ptr [[BLOCK_VAR]], i32 0, i32 0, !dbg [[META48]] +// CHECK-NEXT: store ptr null, ptr [[BYREF_ISA]], align 8, !dbg [[META48]] +// CHECK-NEXT: [[BYREF_FORWARDING:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_BLOCK_VAR]], ptr [[BLOCK_VAR]], i32 0, i32 1, !dbg [[META48]] +// CHECK-NEXT: store ptr [[BLOCK_VAR]], ptr [[BYREF_FORWARDING]], align 8, !dbg [[META48]] +// CHECK-NEXT: [[BYREF_FLAGS:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_BLOCK_VAR]], ptr [[BLOCK_VAR]], i32 0, i32 2, !dbg [[META48]] +// CHECK-NEXT: store i32 0, ptr [[BYREF_FLAGS]], align 8, !dbg [[META48]] +// CHECK-NEXT: [[BYREF_SIZE:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_BLOCK_VAR]], ptr [[BLOCK_VAR]], i32 0, i32 3, !dbg [[META48]] +// CHECK-NEXT: store i32 32, ptr [[BYREF_SIZE]], align 4, !dbg [[META48]] +// CHECK-NEXT: [[BLOCK_VAR1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_BLOCK_VAR]], ptr [[BLOCK_VAR]], i32 0, i32 4, !dbg [[META48]] +// CHECK-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 0, !dbg [[DBG49:![0-9]+]] +// CHECK-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8, !dbg [[DBG49]] +// CHECK-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 1, !dbg [[DBG49]] +// CHECK-NEXT: store i32 1107296256, ptr [[BLOCK_FLAGS]], align 8, !dbg [[DBG49]] +// CHECK-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 2, !dbg [[DBG49]] +// CHECK-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4, !dbg [[DBG49]] +// CHECK-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 3, !dbg [[DBG49]] +// CHECK-NEXT: store ptr @__test_local_block_block_invoke, ptr [[BLOCK_INVOKE]], align 8, !dbg [[DBG49]] +// CHECK-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 4, !dbg [[DBG49]] +// CHECK-NEXT: store ptr @__block_descriptor_tmp.2, ptr [[BLOCK_DESCRIPTOR]], align 8, !dbg [[DBG49]] +// CHECK-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 5, !dbg [[DBG49]] +// CHECK-NEXT: store ptr [[BLOCK_VAR]], ptr [[BLOCK_CAPTURED]], align 8, !dbg [[DBG49]] +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3, !dbg [[DBG49]] +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG49]] +// CHECK-NEXT: call void [[TMP1]](ptr noundef [[BLOCK]]), !dbg [[DBG49]] +// CHECK-NEXT: call void @_Block_object_dispose(ptr [[BLOCK_VAR]], i32 8) #[[ATTR3]], !dbg [[DBG50:![0-9]+]] +// CHECK-NEXT: ret void, !dbg [[DBG50]] +// +// DEADCODE-LABEL: define dso_local void @test_local_block( +// DEADCODE-SAME: ) #[[ATTR0]] !dbg [[DBG28:![0-9]+]] { +// DEADCODE-NEXT: [[ENTRY:.*:]] +// DEADCODE-NEXT: [[BLOCK_VAR:%.*]] = alloca [[STRUCT___BLOCK_BYREF_BLOCK_VAR:%.*]], align 8 +// DEADCODE-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr }>, align 8 +// DEADCODE-NEXT: #dbg_declare(ptr [[BLOCK_VAR]], [[META30:![0-9]+]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr), DIOpConstant(i64 8), DIOpByteOffset(ptr), DIOpDeref(ptr), DIOpConstant(i64 24), DIOpByteOffset(i32)), [[META31:![0-9]+]]) +// DEADCODE-NEXT: [[BYREF_ISA:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_BLOCK_VAR]], ptr [[BLOCK_VAR]], i32 0, i32 0, !dbg [[META31]] +// DEADCODE-NEXT: store ptr null, ptr [[BYREF_ISA]], align 8, !dbg [[META31]] +// DEADCODE-NEXT: [[BYREF_FORWARDING:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_BLOCK_VAR]], ptr [[BLOCK_VAR]], i32 0, i32 1, !dbg [[META31]] +// DEADCODE-NEXT: store ptr [[BLOCK_VAR]], ptr [[BYREF_FORWARDING]], align 8, !dbg [[META31]] +// DEADCODE-NEXT: [[BYREF_FLAGS:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_BLOCK_VAR]], ptr [[BLOCK_VAR]], i32 0, i32 2, !dbg [[META31]] +// DEADCODE-NEXT: store i32 0, ptr [[BYREF_FLAGS]], align 8, !dbg [[META31]] +// DEADCODE-NEXT: [[BYREF_SIZE:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_BLOCK_VAR]], ptr [[BLOCK_VAR]], i32 0, i32 3, !dbg [[META31]] +// DEADCODE-NEXT: store i32 32, ptr [[BYREF_SIZE]], align 4, !dbg [[META31]] +// DEADCODE-NEXT: [[BLOCK_VAR1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_BYREF_BLOCK_VAR]], ptr [[BLOCK_VAR]], i32 0, i32 4, !dbg [[META31]] +// DEADCODE-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 0, !dbg [[DBG32:![0-9]+]] +// DEADCODE-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8, !dbg [[DBG32]] +// DEADCODE-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 1, !dbg [[DBG32]] +// DEADCODE-NEXT: store i32 1107296256, ptr [[BLOCK_FLAGS]], align 8, !dbg [[DBG32]] +// DEADCODE-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 2, !dbg [[DBG32]] +// DEADCODE-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4, !dbg [[DBG32]] +// DEADCODE-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 3, !dbg [[DBG32]] +// DEADCODE-NEXT: store ptr @__test_local_block_block_invoke, ptr [[BLOCK_INVOKE]], align 8, !dbg [[DBG32]] +// DEADCODE-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 4, !dbg [[DBG32]] +// DEADCODE-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8, !dbg [[DBG32]] +// DEADCODE-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 5, !dbg [[DBG32]] +// DEADCODE-NEXT: store ptr [[BLOCK_VAR]], ptr [[BLOCK_CAPTURED]], align 8, !dbg [[DBG32]] +// DEADCODE-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3, !dbg [[DBG32]] +// DEADCODE-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG32]] +// DEADCODE-NEXT: call void [[TMP1]](ptr noundef [[BLOCK]]), !dbg [[DBG32]] +// DEADCODE-NEXT: call void @_Block_object_dispose(ptr [[BLOCK_VAR]], i32 8) #[[ATTR3]], !dbg [[DBG33:![0-9]+]] +// DEADCODE-NEXT: ret void, !dbg [[DBG33]] +// +void test_local_block() { + __block int block_var; + +// FIXME(KZHURAVL): Update EmitDeclareOfBlockDeclRefVariable and EmitDeclareOfBlockLiteralArgVariable. + ^ { block_var = 1; }(); +} + +// Verify that the desired DIExpression are generated for __block vars not used +// in any block. +// CHECK-LABEL: define dso_local void @test_unused( +// CHECK-SAME: ) #[[ATTR0]] !dbg [[DBG56:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[UNUSED_VAR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: #dbg_declare(ptr [[UNUSED_VAR]], [[META58:![0-9]+]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), [[META59:![0-9]+]]) +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[UNUSED_VAR]], align 4, !dbg [[DBG60:![0-9]+]] +// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1, !dbg [[DBG60]] +// CHECK-NEXT: store i32 [[INC]], ptr [[UNUSED_VAR]], align 4, !dbg [[DBG60]] +// CHECK-NEXT: ret void, !dbg [[DBG61:![0-9]+]] +// +// DEADCODE-LABEL: define dso_local void @test_unused( +// DEADCODE-SAME: ) #[[ATTR0]] !dbg [[DBG50:![0-9]+]] { +// DEADCODE-NEXT: [[ENTRY:.*:]] +// DEADCODE-NEXT: [[UNUSED_VAR:%.*]] = alloca i32, align 4 +// DEADCODE-NEXT: #dbg_declare(ptr [[UNUSED_VAR]], [[META52:![0-9]+]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), [[META53:![0-9]+]]) +// DEADCODE-NEXT: [[TMP0:%.*]] = load i32, ptr [[UNUSED_VAR]], align 4, !dbg [[DBG54:![0-9]+]] +// DEADCODE-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1, !dbg [[DBG54]] +// DEADCODE-NEXT: store i32 [[INC]], ptr [[UNUSED_VAR]], align 4, !dbg [[DBG54]] +// DEADCODE-NEXT: ret void, !dbg [[DBG55:![0-9]+]] +// +void test_unused() { + __block int unused_var; +// Use i (not inside a block). + ++unused_var; +} + + +//. +// CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +// CHECK: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// CHECK: [[DBG5]] = distinct !DISubprogram(name: "test_escape_func", scope: [[META6:![0-9]+]], file: [[META6]], line: 60, type: [[META7:![0-9]+]], scopeLine: 60, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META9:![0-9]+]]) +// CHECK: [[META6]] = !DIFile(filename: "{{.*}}debug-info-block-expr-heterogeneous-dwarf.c", directory: {{.*}}) +// CHECK: [[META7]] = !DISubroutineType(types: [[META8:![0-9]+]]) +// CHECK: [[META8]] = !{null} +// CHECK: [[META9]] = !{[[META10]]} +// CHECK: [[META10]] = !DILocalVariable(name: "escape_var", scope: [[DBG5]], file: [[META6]], line: 61, type: [[META11:![0-9]+]]) +// CHECK: [[META11]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +// CHECK: [[META12]] = !DILocation(line: 61, column: 15, scope: [[DBG5]]) +// CHECK: [[DBG13]] = !DILocation(line: 66, column: 14, scope: [[DBG5]]) +// CHECK: [[DBG14]] = !DILocation(line: 66, column: 3, scope: [[DBG5]]) +// CHECK: [[DBG15]] = !DILocation(line: 67, column: 1, scope: [[DBG5]]) +// CHECK: [[DBG34]] = distinct !DISubprogram(name: "test_noescape_func", scope: [[META6]], file: [[META6]], line: 112, type: [[META7]], scopeLine: 112, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META35:![0-9]+]]) +// CHECK: [[META35]] = !{[[META36]]} +// CHECK: [[META36]] = !DILocalVariable(name: "noescape_var", scope: [[DBG34]], file: [[META6]], line: 113, type: [[META11]]) +// CHECK: [[META37]] = !DILocation(line: 113, column: 15, scope: [[DBG34]]) +// CHECK: [[DBG38]] = !DILocation(line: 114, column: 16, scope: [[DBG34]]) +// CHECK: [[DBG39]] = !DILocation(line: 114, column: 3, scope: [[DBG34]]) +// CHECK: [[DBG40]] = !DILocation(line: 115, column: 1, scope: [[DBG34]]) +// CHECK: [[DBG45]] = distinct !DISubprogram(name: "test_local_block", scope: [[META6]], file: [[META6]], line: 184, type: [[META7]], scopeLine: 184, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META46:![0-9]+]]) +// CHECK: [[META46]] = !{[[META47]]} +// CHECK: [[META47]] = !DILocalVariable(name: "block_var", scope: [[DBG45]], file: [[META6]], line: 185, type: [[META11]]) +// CHECK: [[META48]] = !DILocation(line: 185, column: 15, scope: [[DBG45]]) +// CHECK: [[DBG49]] = !DILocation(line: 188, column: 3, scope: [[DBG45]]) +// CHECK: [[DBG50]] = !DILocation(line: 189, column: 1, scope: [[DBG45]]) +// CHECK: [[DBG56]] = distinct !DISubprogram(name: "test_unused", scope: [[META6]], file: [[META6]], line: 213, type: [[META7]], scopeLine: 213, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META57:![0-9]+]]) +// CHECK: [[META57]] = !{[[META58]]} +// CHECK: [[META58]] = !DILocalVariable(name: "unused_var", scope: [[DBG56]], file: [[META6]], line: 214, type: [[META11]]) +// CHECK: [[META59]] = !DILocation(line: 214, column: 15, scope: [[DBG56]]) +// CHECK: [[DBG60]] = !DILocation(line: 216, column: 3, scope: [[DBG56]]) +// CHECK: [[DBG61]] = !DILocation(line: 217, column: 1, scope: [[DBG56]]) +//. +// DEADCODE: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +// DEADCODE: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// DEADCODE: [[DBG5]] = distinct !DISubprogram(name: "test_escape_func", scope: [[META6:![0-9]+]], file: [[META6]], line: 60, type: [[META7:![0-9]+]], scopeLine: 60, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META9:![0-9]+]]) +// DEADCODE: [[META6]] = !DIFile(filename: "{{.*}}debug-info-block-expr-heterogeneous-dwarf.c", directory: {{.*}}) +// DEADCODE: [[META7]] = !DISubroutineType(types: [[META8:![0-9]+]]) +// DEADCODE: [[META8]] = !{null} +// DEADCODE: [[META9]] = !{[[META10]]} +// DEADCODE: [[META10]] = !DILocalVariable(name: "escape_var", scope: [[DBG5]], file: [[META6]], line: 61, type: [[META11:![0-9]+]]) +// DEADCODE: [[META11]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +// DEADCODE: [[META12]] = !DILocation(line: 61, column: 15, scope: [[DBG5]]) +// DEADCODE: [[DBG13]] = !DILocation(line: 67, column: 1, scope: [[DBG5]]) +// DEADCODE: [[DBG14]] = distinct !DISubprogram(name: "test_noescape_func", scope: [[META6]], file: [[META6]], line: 112, type: [[META7]], scopeLine: 112, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META15:![0-9]+]]) +// DEADCODE: [[META15]] = !{[[META16]]} +// DEADCODE: [[META16]] = !DILocalVariable(name: "noescape_var", scope: [[DBG14]], file: [[META6]], line: 113, type: [[META11]]) +// DEADCODE: [[META17]] = !DILocation(line: 113, column: 15, scope: [[DBG14]]) +// DEADCODE: [[DBG18]] = !DILocation(line: 114, column: 16, scope: [[DBG14]]) +// DEADCODE: [[DBG19]] = !DILocation(line: 114, column: 3, scope: [[DBG14]]) +// DEADCODE: [[DBG20]] = !DILocation(line: 115, column: 1, scope: [[DBG14]]) +// DEADCODE: [[DBG28]] = distinct !DISubprogram(name: "test_local_block", scope: [[META6]], file: [[META6]], line: 184, type: [[META7]], scopeLine: 184, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META29:![0-9]+]]) +// DEADCODE: [[META29]] = !{[[META30]]} +// DEADCODE: [[META30]] = !DILocalVariable(name: "block_var", scope: [[DBG28]], file: [[META6]], line: 185, type: [[META11]]) +// DEADCODE: [[META31]] = !DILocation(line: 185, column: 15, scope: [[DBG28]]) +// DEADCODE: [[DBG32]] = !DILocation(line: 188, column: 3, scope: [[DBG28]]) +// DEADCODE: [[DBG33]] = !DILocation(line: 189, column: 1, scope: [[DBG28]]) +// DEADCODE: [[DBG50]] = distinct !DISubprogram(name: "test_unused", scope: [[META6]], file: [[META6]], line: 213, type: [[META7]], scopeLine: 213, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META51:![0-9]+]]) +// DEADCODE: [[META51]] = !{[[META52]]} +// DEADCODE: [[META52]] = !DILocalVariable(name: "unused_var", scope: [[DBG50]], file: [[META6]], line: 214, type: [[META11]]) +// DEADCODE: [[META53]] = !DILocation(line: 214, column: 15, scope: [[DBG50]]) +// DEADCODE: [[DBG54]] = !DILocation(line: 216, column: 3, scope: [[DBG50]]) +// DEADCODE: [[DBG55]] = !DILocation(line: 217, column: 1, scope: [[DBG50]]) +//. diff --git a/clang/test/CodeGen/debug-info-global-constant-heterogeneous-dwarf.c b/clang/test/CodeGen/debug-info-global-constant-heterogeneous-dwarf.c new file mode 100644 index 0000000000000..b72b316963aa5 --- /dev/null +++ b/clang/test/CodeGen/debug-info-global-constant-heterogeneous-dwarf.c @@ -0,0 +1,167 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 +// RUN: %clang_cc1 -D ARG_TYPE=int -D PTR_ARG='&g' -D VAL_ARG=g -emit-llvm -debug-info-kind=standalone -gheterogeneous-dwarf %s -o - | FileCheck --check-prefix=INT-ADDROF-VAL %s +// RUN: %clang_cc1 -D ARG_TYPE=int -D PTR_ARG='&g' -D VAL_ARG=0 -emit-llvm -debug-info-kind=standalone -gheterogeneous-dwarf %s -o - | FileCheck --check-prefix=INT-ADDROF-NOVAL %s +// RUN: %clang_cc1 -D ARG_TYPE=int -D PTR_ARG=0 -D VAL_ARG=g -emit-llvm -debug-info-kind=standalone -gheterogeneous-dwarf %s -o - | FileCheck --check-prefix=INT-NOADDROF-VAL %s +// RUN: %clang_cc1 -D ARG_TYPE=int -D PTR_ARG=0 -D VAL_ARG=0 -emit-llvm -debug-info-kind=standalone -gheterogeneous-dwarf %s -o - | FileCheck --check-prefix=INT-NOADDROF-NOVAL %s +// +// RUN: %clang_cc1 -D ARG_TYPE=float -D PTR_ARG='&g' -D VAL_ARG=g -emit-llvm -debug-info-kind=standalone -gheterogeneous-dwarf %s -o - | FileCheck --check-prefix=FLOAT-ADDROF-VAL %s +// RUN: %clang_cc1 -D ARG_TYPE=float -D PTR_ARG='&g' -D VAL_ARG=0 -emit-llvm -debug-info-kind=standalone -gheterogeneous-dwarf %s -o - | FileCheck --check-prefix=FLOAT-ADDROF-NOVAL %s +// RUN: %clang_cc1 -D ARG_TYPE=float -D PTR_ARG=0 -D VAL_ARG=g -emit-llvm -debug-info-kind=standalone -gheterogeneous-dwarf %s -o - | FileCheck --check-prefix=FLOAT-NOADDROF-VAL %s +// RUN: %clang_cc1 -D ARG_TYPE=float -D PTR_ARG=0 -D VAL_ARG=0 -emit-llvm -debug-info-kind=standalone -gheterogeneous-dwarf %s -o - | FileCheck --check-prefix=FLOAT-NOADDROF-NOVAL %s + +static const ARG_TYPE g = 1; +void callee(const ARG_TYPE *, ARG_TYPE); +// INT-ADDROF-VAL-LABEL: define dso_local void @caller( +// INT-ADDROF-VAL-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] { +// INT-ADDROF-VAL-NEXT: [[ENTRY:.*:]] +// INT-ADDROF-VAL-NEXT: call void @callee(ptr noundef @g, i32 noundef 1), !dbg [[DBG14:![0-9]+]] +// INT-ADDROF-VAL-NEXT: ret void, !dbg [[DBG15:![0-9]+]] +// +// INT-ADDROF-NOVAL-LABEL: define dso_local void @caller( +// INT-ADDROF-NOVAL-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] { +// INT-ADDROF-NOVAL-NEXT: [[ENTRY:.*:]] +// INT-ADDROF-NOVAL-NEXT: call void @callee(ptr noundef @g, i32 noundef 0), !dbg [[DBG14:![0-9]+]] +// INT-ADDROF-NOVAL-NEXT: ret void, !dbg [[DBG15:![0-9]+]] +// +// INT-NOADDROF-VAL-LABEL: define dso_local void @caller( +// INT-NOADDROF-VAL-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] { +// INT-NOADDROF-VAL-NEXT: [[ENTRY:.*:]] +// INT-NOADDROF-VAL-NEXT: call void @callee(ptr noundef null, i32 noundef 1), !dbg [[DBG14:![0-9]+]] +// INT-NOADDROF-VAL-NEXT: ret void, !dbg [[DBG15:![0-9]+]] +// +// INT-NOADDROF-NOVAL-LABEL: define dso_local void @caller( +// INT-NOADDROF-NOVAL-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG5:![0-9]+]] { +// INT-NOADDROF-NOVAL-NEXT: [[ENTRY:.*:]] +// INT-NOADDROF-NOVAL-NEXT: call void @callee(ptr noundef null, i32 noundef 0), !dbg [[DBG9:![0-9]+]] +// INT-NOADDROF-NOVAL-NEXT: ret void, !dbg [[DBG10:![0-9]+]] +// +// FLOAT-ADDROF-VAL-LABEL: define dso_local void @caller( +// FLOAT-ADDROF-VAL-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] { +// FLOAT-ADDROF-VAL-NEXT: [[ENTRY:.*:]] +// FLOAT-ADDROF-VAL-NEXT: call void @callee(ptr noundef @g, float noundef 1.000000e+00), !dbg [[DBG14:![0-9]+]] +// FLOAT-ADDROF-VAL-NEXT: ret void, !dbg [[DBG15:![0-9]+]] +// +// FLOAT-ADDROF-NOVAL-LABEL: define dso_local void @caller( +// FLOAT-ADDROF-NOVAL-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] { +// FLOAT-ADDROF-NOVAL-NEXT: [[ENTRY:.*:]] +// FLOAT-ADDROF-NOVAL-NEXT: call void @callee(ptr noundef @g, float noundef 0.000000e+00), !dbg [[DBG14:![0-9]+]] +// FLOAT-ADDROF-NOVAL-NEXT: ret void, !dbg [[DBG15:![0-9]+]] +// +// FLOAT-NOADDROF-VAL-LABEL: define dso_local void @caller( +// FLOAT-NOADDROF-VAL-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] { +// FLOAT-NOADDROF-VAL-NEXT: [[ENTRY:.*:]] +// FLOAT-NOADDROF-VAL-NEXT: call void @callee(ptr noundef null, float noundef 1.000000e+00), !dbg [[DBG14:![0-9]+]] +// FLOAT-NOADDROF-VAL-NEXT: ret void, !dbg [[DBG15:![0-9]+]] +// +// FLOAT-NOADDROF-NOVAL-LABEL: define dso_local void @caller( +// FLOAT-NOADDROF-NOVAL-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG5:![0-9]+]] { +// FLOAT-NOADDROF-NOVAL-NEXT: [[ENTRY:.*:]] +// FLOAT-NOADDROF-NOVAL-NEXT: call void @callee(ptr noundef null, float noundef 0.000000e+00), !dbg [[DBG9:![0-9]+]] +// FLOAT-NOADDROF-NOVAL-NEXT: ret void, !dbg [[DBG10:![0-9]+]] +// +void caller() { + callee(PTR_ARG, VAL_ARG); +} +//. +// INT-ADDROF-VAL: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: [[META2:![0-9]+]], splitDebugInlining: false, nameTableKind: None) +// INT-ADDROF-VAL: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// INT-ADDROF-VAL: [[META2]] = !{[[META3:![0-9]+]]} +// INT-ADDROF-VAL: [[META3]] = !DIGlobalVariableExpression(var: [[META4:![0-9]+]], expr: !DIExpression(DIOpConstant(i32 1))) +// INT-ADDROF-VAL: [[META4]] = distinct !DIGlobalVariable(name: "g", scope: [[META0]], file: [[META5:![0-9]+]], line: 12, type: [[META6:![0-9]+]], isLocal: true, isDefinition: true) +// INT-ADDROF-VAL: [[META5]] = !DIFile(filename: "{{.*}}debug-info-global-constant-heterogeneous-dwarf.c", directory: {{.*}}) +// INT-ADDROF-VAL: [[META6]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META7:![0-9]+]]) +// INT-ADDROF-VAL: [[META7]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +// INT-ADDROF-VAL: [[DBG11]] = distinct !DISubprogram(name: "caller", scope: [[META5]], file: [[META5]], line: 62, type: [[META12:![0-9]+]], scopeLine: 62, spFlags: DISPFlagDefinition, unit: [[META0]]) +// INT-ADDROF-VAL: [[META12]] = !DISubroutineType(types: [[META13:![0-9]+]]) +// INT-ADDROF-VAL: [[META13]] = !{null} +// INT-ADDROF-VAL: [[DBG14]] = !DILocation(line: 63, column: 3, scope: [[DBG11]]) +// INT-ADDROF-VAL: [[DBG15]] = !DILocation(line: 64, column: 1, scope: [[DBG11]]) +//. +// INT-ADDROF-NOVAL: [[META0:![0-9]+]] = !DIGlobalVariableExpression(var: [[META1:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32))) +// INT-ADDROF-NOVAL: [[META1]] = distinct !DIGlobalVariable(name: "g", scope: [[META2:![0-9]+]], file: [[META5:![0-9]+]], line: 12, type: [[META6:![0-9]+]], isLocal: true, isDefinition: true) +// INT-ADDROF-NOVAL: [[META2]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META3:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: [[META4:![0-9]+]], splitDebugInlining: false, nameTableKind: None) +// INT-ADDROF-NOVAL: [[META3]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// INT-ADDROF-NOVAL: [[META4]] = !{[[META0]]} +// INT-ADDROF-NOVAL: [[META5]] = !DIFile(filename: "{{.*}}debug-info-global-constant-heterogeneous-dwarf.c", directory: {{.*}}) +// INT-ADDROF-NOVAL: [[META6]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META7:![0-9]+]]) +// INT-ADDROF-NOVAL: [[META7]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +// INT-ADDROF-NOVAL: [[DBG11]] = distinct !DISubprogram(name: "caller", scope: [[META5]], file: [[META5]], line: 62, type: [[META12:![0-9]+]], scopeLine: 62, spFlags: DISPFlagDefinition, unit: [[META2]]) +// INT-ADDROF-NOVAL: [[META12]] = !DISubroutineType(types: [[META13:![0-9]+]]) +// INT-ADDROF-NOVAL: [[META13]] = !{null} +// INT-ADDROF-NOVAL: [[DBG14]] = !DILocation(line: 63, column: 3, scope: [[DBG11]]) +// INT-ADDROF-NOVAL: [[DBG15]] = !DILocation(line: 64, column: 1, scope: [[DBG11]]) +//. +// INT-NOADDROF-VAL: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: [[META2:![0-9]+]], splitDebugInlining: false, nameTableKind: None) +// INT-NOADDROF-VAL: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// INT-NOADDROF-VAL: [[META2]] = !{[[META3:![0-9]+]]} +// INT-NOADDROF-VAL: [[META3]] = !DIGlobalVariableExpression(var: [[META4:![0-9]+]], expr: !DIExpression(DIOpConstant(i32 1))) +// INT-NOADDROF-VAL: [[META4]] = distinct !DIGlobalVariable(name: "g", scope: [[META0]], file: [[META5:![0-9]+]], line: 12, type: [[META6:![0-9]+]], isLocal: true, isDefinition: true) +// INT-NOADDROF-VAL: [[META5]] = !DIFile(filename: "{{.*}}debug-info-global-constant-heterogeneous-dwarf.c", directory: {{.*}}) +// INT-NOADDROF-VAL: [[META6]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META7:![0-9]+]]) +// INT-NOADDROF-VAL: [[META7]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +// INT-NOADDROF-VAL: [[DBG11]] = distinct !DISubprogram(name: "caller", scope: [[META5]], file: [[META5]], line: 62, type: [[META12:![0-9]+]], scopeLine: 62, spFlags: DISPFlagDefinition, unit: [[META0]]) +// INT-NOADDROF-VAL: [[META12]] = !DISubroutineType(types: [[META13:![0-9]+]]) +// INT-NOADDROF-VAL: [[META13]] = !{null} +// INT-NOADDROF-VAL: [[DBG14]] = !DILocation(line: 63, column: 3, scope: [[DBG11]]) +// INT-NOADDROF-VAL: [[DBG15]] = !DILocation(line: 64, column: 1, scope: [[DBG11]]) +//. +// INT-NOADDROF-NOVAL: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +// INT-NOADDROF-NOVAL: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// INT-NOADDROF-NOVAL: [[DBG5]] = distinct !DISubprogram(name: "caller", scope: [[META6:![0-9]+]], file: [[META6]], line: 62, type: [[META7:![0-9]+]], scopeLine: 62, spFlags: DISPFlagDefinition, unit: [[META0]]) +// INT-NOADDROF-NOVAL: [[META6]] = !DIFile(filename: "{{.*}}debug-info-global-constant-heterogeneous-dwarf.c", directory: {{.*}}) +// INT-NOADDROF-NOVAL: [[META7]] = !DISubroutineType(types: [[META8:![0-9]+]]) +// INT-NOADDROF-NOVAL: [[META8]] = !{null} +// INT-NOADDROF-NOVAL: [[DBG9]] = !DILocation(line: 63, column: 3, scope: [[DBG5]]) +// INT-NOADDROF-NOVAL: [[DBG10]] = !DILocation(line: 64, column: 1, scope: [[DBG5]]) +//. +// FLOAT-ADDROF-VAL: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: [[META2:![0-9]+]], splitDebugInlining: false, nameTableKind: None) +// FLOAT-ADDROF-VAL: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// FLOAT-ADDROF-VAL: [[META2]] = !{[[META3:![0-9]+]]} +// FLOAT-ADDROF-VAL: [[META3]] = !DIGlobalVariableExpression(var: [[META4:![0-9]+]], expr: !DIExpression(DIOpConstant(float 1.000000e+00))) +// FLOAT-ADDROF-VAL: [[META4]] = distinct !DIGlobalVariable(name: "g", scope: [[META0]], file: [[META5:![0-9]+]], line: 12, type: [[META6:![0-9]+]], isLocal: true, isDefinition: true) +// FLOAT-ADDROF-VAL: [[META5]] = !DIFile(filename: "{{.*}}debug-info-global-constant-heterogeneous-dwarf.c", directory: {{.*}}) +// FLOAT-ADDROF-VAL: [[META6]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META7:![0-9]+]]) +// FLOAT-ADDROF-VAL: [[META7]] = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +// FLOAT-ADDROF-VAL: [[DBG11]] = distinct !DISubprogram(name: "caller", scope: [[META5]], file: [[META5]], line: 62, type: [[META12:![0-9]+]], scopeLine: 62, spFlags: DISPFlagDefinition, unit: [[META0]]) +// FLOAT-ADDROF-VAL: [[META12]] = !DISubroutineType(types: [[META13:![0-9]+]]) +// FLOAT-ADDROF-VAL: [[META13]] = !{null} +// FLOAT-ADDROF-VAL: [[DBG14]] = !DILocation(line: 63, column: 3, scope: [[DBG11]]) +// FLOAT-ADDROF-VAL: [[DBG15]] = !DILocation(line: 64, column: 1, scope: [[DBG11]]) +//. +// FLOAT-ADDROF-NOVAL: [[META0:![0-9]+]] = !DIGlobalVariableExpression(var: [[META1:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr), DIOpDeref(float))) +// FLOAT-ADDROF-NOVAL: [[META1]] = distinct !DIGlobalVariable(name: "g", scope: [[META2:![0-9]+]], file: [[META5:![0-9]+]], line: 12, type: [[META6:![0-9]+]], isLocal: true, isDefinition: true) +// FLOAT-ADDROF-NOVAL: [[META2]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META3:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: [[META4:![0-9]+]], splitDebugInlining: false, nameTableKind: None) +// FLOAT-ADDROF-NOVAL: [[META3]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// FLOAT-ADDROF-NOVAL: [[META4]] = !{[[META0]]} +// FLOAT-ADDROF-NOVAL: [[META5]] = !DIFile(filename: "{{.*}}debug-info-global-constant-heterogeneous-dwarf.c", directory: {{.*}}) +// FLOAT-ADDROF-NOVAL: [[META6]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META7:![0-9]+]]) +// FLOAT-ADDROF-NOVAL: [[META7]] = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +// FLOAT-ADDROF-NOVAL: [[DBG11]] = distinct !DISubprogram(name: "caller", scope: [[META5]], file: [[META5]], line: 62, type: [[META12:![0-9]+]], scopeLine: 62, spFlags: DISPFlagDefinition, unit: [[META2]]) +// FLOAT-ADDROF-NOVAL: [[META12]] = !DISubroutineType(types: [[META13:![0-9]+]]) +// FLOAT-ADDROF-NOVAL: [[META13]] = !{null} +// FLOAT-ADDROF-NOVAL: [[DBG14]] = !DILocation(line: 63, column: 3, scope: [[DBG11]]) +// FLOAT-ADDROF-NOVAL: [[DBG15]] = !DILocation(line: 64, column: 1, scope: [[DBG11]]) +//. +// FLOAT-NOADDROF-VAL: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: [[META2:![0-9]+]], splitDebugInlining: false, nameTableKind: None) +// FLOAT-NOADDROF-VAL: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// FLOAT-NOADDROF-VAL: [[META2]] = !{[[META3:![0-9]+]]} +// FLOAT-NOADDROF-VAL: [[META3]] = !DIGlobalVariableExpression(var: [[META4:![0-9]+]], expr: !DIExpression(DIOpConstant(float 1.000000e+00))) +// FLOAT-NOADDROF-VAL: [[META4]] = distinct !DIGlobalVariable(name: "g", scope: [[META0]], file: [[META5:![0-9]+]], line: 12, type: [[META6:![0-9]+]], isLocal: true, isDefinition: true) +// FLOAT-NOADDROF-VAL: [[META5]] = !DIFile(filename: "{{.*}}debug-info-global-constant-heterogeneous-dwarf.c", directory: {{.*}}) +// FLOAT-NOADDROF-VAL: [[META6]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META7:![0-9]+]]) +// FLOAT-NOADDROF-VAL: [[META7]] = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +// FLOAT-NOADDROF-VAL: [[DBG11]] = distinct !DISubprogram(name: "caller", scope: [[META5]], file: [[META5]], line: 62, type: [[META12:![0-9]+]], scopeLine: 62, spFlags: DISPFlagDefinition, unit: [[META0]]) +// FLOAT-NOADDROF-VAL: [[META12]] = !DISubroutineType(types: [[META13:![0-9]+]]) +// FLOAT-NOADDROF-VAL: [[META13]] = !{null} +// FLOAT-NOADDROF-VAL: [[DBG14]] = !DILocation(line: 63, column: 3, scope: [[DBG11]]) +// FLOAT-NOADDROF-VAL: [[DBG15]] = !DILocation(line: 64, column: 1, scope: [[DBG11]]) +//. +// FLOAT-NOADDROF-NOVAL: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +// FLOAT-NOADDROF-NOVAL: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// FLOAT-NOADDROF-NOVAL: [[DBG5]] = distinct !DISubprogram(name: "caller", scope: [[META6:![0-9]+]], file: [[META6]], line: 62, type: [[META7:![0-9]+]], scopeLine: 62, spFlags: DISPFlagDefinition, unit: [[META0]]) +// FLOAT-NOADDROF-NOVAL: [[META6]] = !DIFile(filename: "{{.*}}debug-info-global-constant-heterogeneous-dwarf.c", directory: {{.*}}) +// FLOAT-NOADDROF-NOVAL: [[META7]] = !DISubroutineType(types: [[META8:![0-9]+]]) +// FLOAT-NOADDROF-NOVAL: [[META8]] = !{null} +// FLOAT-NOADDROF-NOVAL: [[DBG9]] = !DILocation(line: 63, column: 3, scope: [[DBG5]]) +// FLOAT-NOADDROF-NOVAL: [[DBG10]] = !DILocation(line: 64, column: 1, scope: [[DBG5]]) +//. diff --git a/clang/test/CodeGen/embed-bitcode-marker-with-nonzero-as.c b/clang/test/CodeGen/embed-bitcode-marker-with-nonzero-as.c index df7118859c764..7294d4c96e76c 100644 --- a/clang/test/CodeGen/embed-bitcode-marker-with-nonzero-as.c +++ b/clang/test/CodeGen/embed-bitcode-marker-with-nonzero-as.c @@ -1,6 +1,5 @@ // RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -fcuda-is-device -fembed-bitcode=marker -x hip %s -o - \ // RUN: | FileCheck %s --check-prefix=CHECK - // CHECK: @llvm.embedded.module = private addrspace(1) constant [0 x i8] zeroinitializer, section ".llvmbc", align 1 // CHECK-NEXT: @llvm.cmdline = private addrspace(1) constant [{{[0-9]+}} x i8] c"{{.*}}", section ".llvmcmd", align 1 // CHECK-NEXT: @llvm.compiler.used = appending addrspace(1) global [5 x ptr addrspace(4)] [ptr addrspace(4) addrspacecast (ptr addrspace(1) @foo.managed to ptr addrspace(4)), ptr addrspace(4) addrspacecast (ptr addrspace(1) @foo to ptr addrspace(4)), ptr addrspace(4) addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr addrspace(4)), ptr addrspace(4) addrspacecast (ptr addrspace(1) @llvm.embedded.module to ptr addrspace(4)), ptr addrspace(4) addrspacecast (ptr addrspace(1) @llvm.cmdline to ptr addrspace(4))], section "llvm.metadata" diff --git a/clang/test/CodeGen/fp-floatcontrol-pragma.cpp b/clang/test/CodeGen/fp-floatcontrol-pragma.cpp index 966eaf6053970..6870227a59ef7 100644 --- a/clang/test/CodeGen/fp-floatcontrol-pragma.cpp +++ b/clang/test/CodeGen/fp-floatcontrol-pragma.cpp @@ -191,21 +191,7 @@ float test_OperatorCall() { void callt() { volatile float z; z = z * z; - //CHECK-FENV: llvm.experimental.constrained.fmul{{.*}} -} - -// CHECK-LABEL: define {{.*}}myAdd{{.*}} -float myAdd(int i, float f) { - if (i<0) - return 1.0 + 2.0; - // Check that floating point constant folding doesn't occur if - // #pragma STC FENV_ACCESS is enabled. - //CHECK-FENV: llvm.experimental.constrained.fadd{{.*}}double 1.0{{.*}}double 2.0{{.*}} - //CHECK: store float 3.0{{.*}}retval{{.*}} - static double v = 1.0 / 3.0; - //CHECK-FENV: llvm.experimental.constrained.fptrunc.f32.f64{{.*}} - //CHECK-NOT: fdiv - return v; +//CHECK-FENV: llvm.experimental.constrained.fmul{{.*}} } #if EXCEPT diff --git a/clang/test/CodeGen/paren-list-agg-init.cpp b/clang/test/CodeGen/paren-list-agg-init.cpp index e30777ecc07d6..235352382332a 100644 --- a/clang/test/CodeGen/paren-list-agg-init.cpp +++ b/clang/test/CodeGen/paren-list-agg-init.cpp @@ -377,7 +377,7 @@ void foo18() { // CHECK-NEXT: [[A:%.*a.*]] = getelementptr inbounds nuw [[STRUCT_G]], ptr [[G]], i32 0, i32 0 // CHECK-NEXT: store i32 2, ptr [[A]], align 4 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds i8, ptr [[G]], i64 4 -// CHECK-NEXT: call void @{{.*F.*}}(ptr noundef nonnull align 1 dereferenceable(1) [[F]], i32 noundef 1) +// CHECk-NEXT: call void @{{.*F.*}}(ptr noundef nonnull align 1 dereferenceable(1)) [[F]], ie32 noundef 1) // CHECK: ret void void foo19() { G g(2); diff --git a/clang/test/CodeGen/scoped-fence-ops.c b/clang/test/CodeGen/scoped-fence-ops.c index 259e8d333e4c8..fb11f589c13dd 100644 --- a/clang/test/CodeGen/scoped-fence-ops.c +++ b/clang/test/CodeGen/scoped-fence-ops.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \ -// RUN: -fvisibility=hidden | FileCheck --check-prefixes=AMDGCN,AMDGCN_CL_DEF %s +// RUN: -fvisibility=hidden | FileCheck --check-prefix=AMDGCN %s // RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \ -// RUN: -cl-std=CL2.0 -fvisibility=hidden | FileCheck --check-prefixes=AMDGCN,AMDGCN_CL_20 %s +// RUN: -cl-std=CL2.0 -fvisibility=hidden | FileCheck --check-prefix=AMDGCN %s // RUN: %clang_cc1 %s -emit-llvm -o - -triple=spirv64-unknown-unknown -ffreestanding \ // RUN: -fvisibility=hidden | FileCheck --check-prefix=SPIRV %s // RUN: %clang_cc1 %s -emit-llvm -o - -triple=x86_64-unknown-linux-gnu -ffreestanding \ @@ -269,6 +269,3 @@ void fe2a() { void fe2b() { __scoped_atomic_thread_fence(__ATOMIC_RELEASE, 999); } -//// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -// AMDGCN_CL_20: {{.*}} -// AMDGCN_CL_DEF: {{.*}} diff --git a/clang/test/CodeGen/target-builtin-noerror.c b/clang/test/CodeGen/target-builtin-noerror.c index 47d5ae51d643a..c960193d2e9c9 100644 --- a/clang/test/CodeGen/target-builtin-noerror.c +++ b/clang/test/CodeGen/target-builtin-noerror.c @@ -194,7 +194,6 @@ void verifycpustrings(void) { (void)__builtin_cpu_is("rocketlake"); (void)__builtin_cpu_is("sandybridge"); (void)__builtin_cpu_is("shanghai"); - (void)__builtin_cpu_is("sierraforest"); (void)__builtin_cpu_is("silvermont"); (void)__builtin_cpu_is("skylake"); (void)__builtin_cpu_is("skylake-avx512"); @@ -202,7 +201,6 @@ void verifycpustrings(void) { (void)__builtin_cpu_is("tigerlake"); (void)__builtin_cpu_is("sapphirerapids"); (void)__builtin_cpu_is("tremont"); - (void)__builtin_cpu_is("gracemont"); (void)__builtin_cpu_is("westmere"); (void)__builtin_cpu_is("znver1"); (void)__builtin_cpu_is("znver2"); diff --git a/clang/test/CodeGenCUDA/debug-info-address-class.cu b/clang/test/CodeGenCUDA/debug-info-address-class.cu index 876d2de31664a..2a02ccaf60049 100644 --- a/clang/test/CodeGenCUDA/debug-info-address-class.cu +++ b/clang/test/CodeGenCUDA/debug-info-address-class.cu @@ -2,13 +2,13 @@ #include "Inputs/cuda.h" -// CHECK-DAG: ![[FILEVAR0:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR0:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR0]], expr: !DIExpression()) __device__ int FileVar0; -// CHECK-DAG: ![[FILEVAR1:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR1:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR1]], expr: !DIExpression(DW_OP_constu, 8, DW_OP_swap, DW_OP_xderef)) __device__ __shared__ int FileVar1; -// CHECK-DAG: ![[FILEVAR2:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR2:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR2]], expr: !DIExpression(DW_OP_constu, 4, DW_OP_swap, DW_OP_xderef)) __device__ __constant__ int FileVar2; @@ -16,7 +16,7 @@ __device__ void kernel1( // CHECK-DAG: ![[ARG:[0-9]+]] = !DILocalVariable(name: "Arg", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) // CHECK-DAG: #dbg_declare(ptr {{.*}}, ![[ARG]], !DIExpression(), !{{[0-9]+}} int Arg) { - // CHECK-DAG: ![[FUNCVAR0:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR0:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR0]], expr: !DIExpression(DW_OP_constu, 8, DW_OP_swap, DW_OP_xderef)) __shared__ int FuncVar0; // CHECK-DAG: ![[FUNCVAR1:[0-9]+]] = !DILocalVariable(name: "FuncVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) diff --git a/clang/test/CodeGenCUDA/debug-info-memory-space.cu b/clang/test/CodeGenCUDA/debug-info-memory-space.cu new file mode 100644 index 0000000000000..d0cb40b96cdf1 --- /dev/null +++ b/clang/test/CodeGenCUDA/debug-info-memory-space.cu @@ -0,0 +1,26 @@ +// RUN: %clang_cc1 -triple nvptx-unknown-unknown -emit-llvm -fcuda-is-device -debug-info-kind=limited -gheterogeneous-dwarf -o - %s | FileCheck %s +// CHECK-DAG: !DIGlobalVariable(name: "GlobalShared", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) +// CHECK-DAG: !DIGlobalVariable(name: "GlobalDevice", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) +// CHECK-DAG: !DIGlobalVariable(name: "GlobalConstant", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) +// CHECK-DAG: !DIGlobalVariable(name: "FuncVarShared", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) +// CHECK-DAG: !DILocalVariable(name: "FuncVar", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) + +// CHECK-DAG: !DILocalVariable(name: "FuncVarSharedPointer", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DEVICE_PTR:[0-9]+]]) +// CHECK-DAG: !DILocalVariable(name: "FuncVarPointer", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DEVICE_PTR:[0-9]+]]) +// CHECK-DAG: ![[DEVICE_PTR]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}) + +#define __device__ __attribute__((device)) +#define __shared__ __attribute__((shared)) +#define __constant__ __attribute__((constant)) + +__shared__ int GlobalShared; +__device__ int GlobalDevice; +__constant__ int GlobalConstant; + +__device__ void kernel1(int Arg) { + __shared__ int FuncVarShared; + int FuncVar; + + auto *FuncVarSharedPointer = &FuncVarShared; + auto *FuncVarPointer = &FuncVar; +} diff --git a/clang/test/CodeGenCUDA/ms-linker-options.cu b/clang/test/CodeGenCUDA/ms-linker-options.cu index 0be25fbbdfd41..e8303e02801c5 100644 --- a/clang/test/CodeGenCUDA/ms-linker-options.cu +++ b/clang/test/CodeGenCUDA/ms-linker-options.cu @@ -2,12 +2,12 @@ // RUN: -fno-autolink -triple amdgcn-amd-amdhsa \ // RUN: | FileCheck -check-prefix=DEV %s // RUN: %clang_cc1 -emit-llvm -o - -fms-extensions -x hip %s -triple \ -// RUN: x86_64-pc-windows-msvc | FileCheck -check-prefix=HOST %s +// RUN: x86_64-pc-windows-msvc -aux-triple amdgcn-amd-amdhsa | FileCheck -check-prefix=HOST %s // RUN: %clang_cc1 -emit-llvm -o - -fcuda-is-device -fms-extensions %s \ // RUN: -fno-autolink -triple amdgcn-amd-amdhsa \ // RUN: | FileCheck -check-prefix=DEV %s // RUN: %clang_cc1 -emit-llvm -o - -fms-extensions %s -triple \ -// RUN: x86_64-pc-windows-msvc | FileCheck -check-prefix=HOST %s +// RUN: x86_64-pc-windows-msvc -aux-triple amdgcn-amd-amdhsa | FileCheck -check-prefix=HOST %s // DEV-NOT: llvm.linker.options // DEV-NOT: llvm.dependent-libraries diff --git a/clang/test/CodeGenCUDASPIRV/copy-aggregate-byval.cu b/clang/test/CodeGenCUDASPIRV/copy-aggregate-byval.cu index 2692ce4c92b28..ec86648120fe2 100644 --- a/clang/test/CodeGenCUDASPIRV/copy-aggregate-byval.cu +++ b/clang/test/CodeGenCUDASPIRV/copy-aggregate-byval.cu @@ -3,12 +3,12 @@ // RUN: %clang -emit-llvm --cuda-device-only --offload=spirv32 \ // RUN: -nocudalib -nocudainc %s -o %t.bc -c 2>&1 -// RUN: llvm-dis %t.bc -o %t.ll +// RUN: llvm-dis %t.bc -o %t.ll // RUN: FileCheck %s --input-file=%t.ll // RUN: %clang -emit-llvm --cuda-device-only --offload=spirv64 \ // RUN: -nocudalib -nocudainc %s -o %t.bc -c 2>&1 -// RUN: llvm-dis %t.bc -o %t.ll +// RUN: llvm-dis %t.bc -o %t.ll // RUN: FileCheck %s --input-file=%t.ll class GpuData { diff --git a/clang/test/CodeGenCXX/bitfield-access-empty.cpp b/clang/test/CodeGenCXX/bitfield-access-empty.cpp index 0485ae5cda4a9..d1ae12e202cda 100644 --- a/clang/test/CodeGenCXX/bitfield-access-empty.cpp +++ b/clang/test/CodeGenCXX/bitfield-access-empty.cpp @@ -1,4 +1,5 @@ // Check if we can merge bitfields across empty members +// XFAIL: * // Configs that have cheap unaligned access // Little Endian @@ -35,7 +36,7 @@ // Big endian // RUN: %clang_cc1 -triple=lanai-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s -// RUN: %clang_cc1 -triple=m68k-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-M68K %s +// RUN: %clang_cc1 -triple=m68k-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s // RUN: %clang_cc1 -triple=mips-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s // RUN: %clang_cc1 -triple=mips64-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s // RUN: %clang_cc1 -triple=sparc-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s @@ -51,7 +52,6 @@ struct P1 { // CHECK-LABEL: LLVMType:%struct.P1 = // LAYOUT-SAME: type { i16, i16 } // LAYOUT-DWN32-SAME: type { i16, i16 } -// LAYOUT-DWN32-M68K: type { i16, i16 } // CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P1 = // CHECK: BitFields:[ // LAYOUT-NEXT: struct P2 { @@ -72,7 +69,6 @@ struct P2 { // CHECK-LABEL: LLVMType:%struct.P2 = // LAYOUT-SAME: type { i16, i16 } // LAYOUT-DWN32-SAME: type { i16, i16 } -// LAYOUT-M68K-SAME: type { i16, i16 } // CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P2 = // CHECK: BitFields:[ // LAYOUT-NEXT: struct P3 { @@ -93,7 +86,6 @@ struct P3 { // CHECK-LABEL: LLVMType:%struct.P3 = // LAYOUT-SAME: type { i16, [2 x i8], i16, [2 x i8] } // LAYOUT-DWN32-SAME: type <{ i16, i8, i16 }> -// LAYOUT-M68K-SAME: type <{ i16, i8, i16, i8 }> // CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P3 = // CHECK: BitFields:[ // LAYOUT-NEXT: struct P4 { @@ -133,7 +122,6 @@ struct P6 { // CHECK-LABEL: LLVMType:%struct.P6 = // LAYOUT-SAME: type { i32, i32 } // LAYOUT-DWN32-SAME: type { i32, i32 } -// LAYOUT-M68K-SAME: type { i32, i32 } // CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P6 = // CHECK: BitFields:[ // LAYOUT-NEXT: struct P7 { @@ -155,7 +140,6 @@ struct P7 { // CHECK-LABEL: LLVMType:%struct.P7 = // LAYOUT-SAME: type { i32, i32 } // LAYOUT-DWN32-SAME: type { i32, i32 } -// LAYOUT-M68K-SAME: type { i32, i32 } // CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P7 = // CHECK: BitFields:[ // LAYOUT-NEXT: diff --git a/clang/test/CodeGenCXX/heterogeneous-debug-info-structured-binding-bitfield.cpp b/clang/test/CodeGenCXX/heterogeneous-debug-info-structured-binding-bitfield.cpp new file mode 100644 index 0000000000000..5482f921d316e --- /dev/null +++ b/clang/test/CodeGenCXX/heterogeneous-debug-info-structured-binding-bitfield.cpp @@ -0,0 +1,242 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x c++ -emit-llvm -fcuda-is-device -debug-info-kind=limited -gheterogeneous-dwarf -o - %s | FileCheck %s + +struct S0 { + unsigned int x : 16; + unsigned int y : 16; +}; + +// CHECK-LABEL: define dso_local void @_Z3fS0v( +// CHECK-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[S0:%.*]] = alloca [[STRUCT_S0:%.*]], align 4, addrspace(5) +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_S0]], align 4, addrspace(5) +// CHECK-NEXT: [[S0_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S0]] to ptr +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[S0]], [[META11:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S0]])), [[META17:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META18:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S0]]), DIOpConstant(i32 0), DIOpBitOffset(i32)), [[META19:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META20:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S0]]), DIOpConstant(i32 16), DIOpBitOffset(i32)), [[META21:![0-9]+]]) +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[S0_ASCAST]], i64 4, i1 false), !dbg [[DBG22:![0-9]+]] +// CHECK-NEXT: ret void, !dbg [[DBG23:![0-9]+]] +// +void fS0() { + S0 s0; + auto [a, b] = s0; +} + +struct S1 { + unsigned int x : 8; + unsigned int y : 8; +}; + +// CHECK-LABEL: define dso_local void @_Z3fS1v( +// CHECK-SAME: ) #[[ATTR0]] !dbg [[DBG24:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[S1:%.*]] = alloca [[STRUCT_S1:%.*]], align 4, addrspace(5) +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_S1]], align 4, addrspace(5) +// CHECK-NEXT: [[S1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S1]] to ptr +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[S1]], [[META26:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S1]])), [[META31:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META32:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S1]]), DIOpConstant(i32 0), DIOpBitOffset(i32)), [[META33:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META34:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S1]]), DIOpConstant(i32 8), DIOpBitOffset(i32)), [[META35:![0-9]+]]) +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[S1_ASCAST]], i64 4, i1 false), !dbg [[DBG36:![0-9]+]] +// CHECK-NEXT: ret void, !dbg [[DBG37:![0-9]+]] +// +void fS1() { + S1 s1; + auto [a, b] = s1; +} + +struct S2 { + unsigned int x : 8; + unsigned int y : 16; +}; + +// CHECK-LABEL: define dso_local void @_Z3fS2v( +// CHECK-SAME: ) #[[ATTR0]] !dbg [[DBG38:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[S2:%.*]] = alloca [[STRUCT_S2:%.*]], align 4, addrspace(5) +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_S2]], align 4, addrspace(5) +// CHECK-NEXT: [[S2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S2]] to ptr +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[S2]], [[META40:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S2]])), [[META45:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META46:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S2]]), DIOpConstant(i32 0), DIOpBitOffset(i32)), [[META47:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META48:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S2]]), DIOpConstant(i32 8), DIOpBitOffset(i32)), [[META49:![0-9]+]]) +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[S2_ASCAST]], i64 4, i1 false), !dbg [[DBG50:![0-9]+]] +// CHECK-NEXT: ret void, !dbg [[DBG51:![0-9]+]] +// +void fS2() { + S2 s2; + auto [a, b] = s2; +} + +struct S3 { + unsigned int x : 16; + unsigned int y : 32; +}; + +// CHECK-LABEL: define dso_local void @_Z3fS3v( +// CHECK-SAME: ) #[[ATTR0]] !dbg [[DBG52:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[S3:%.*]] = alloca [[STRUCT_S3:%.*]], align 4, addrspace(5) +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_S3]], align 4, addrspace(5) +// CHECK-NEXT: [[S3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S3]] to ptr +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[S3]], [[META54:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S3]])), [[META59:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META60:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S3]]), DIOpConstant(i32 0), DIOpBitOffset(i32)), [[META61:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META62:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S3]]), DIOpConstant(i32 32), DIOpBitOffset(i32)), [[META63:![0-9]+]]) +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[S3_ASCAST]], i64 8, i1 false), !dbg [[DBG64:![0-9]+]] +// CHECK-NEXT: ret void, !dbg [[DBG65:![0-9]+]] +// +void fS3() { + S3 s3; + auto [a, b] = s3; +} + +struct S4 { + unsigned int x : 16; + unsigned : 0; + unsigned int y : 16; +}; + +// CHECK-LABEL: define dso_local void @_Z3fS4v( +// CHECK-SAME: ) #[[ATTR0]] !dbg [[DBG66:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[S4:%.*]] = alloca [[STRUCT_S4:%.*]], align 4, addrspace(5) +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_S4]], align 4, addrspace(5) +// CHECK-NEXT: [[S4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S4]] to ptr +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[S4]], [[META68:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S4]])), [[META74:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META75:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S4]]), DIOpConstant(i32 0), DIOpBitOffset(i32)), [[META76:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META77:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S4]]), DIOpConstant(i32 32), DIOpBitOffset(i32)), [[META78:![0-9]+]]) +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[S4_ASCAST]], i64 8, i1 false), !dbg [[DBG79:![0-9]+]] +// CHECK-NEXT: ret void, !dbg [[DBG80:![0-9]+]] +// +void fS4() { + S4 s4; + auto [a, b] = s4; +} + +// It's currently not possible to produce complete debug information for the following cases. +// Confirm that no wrong debug info is output. +// Once this is implemented, these tests should be amended. +struct S5 { + unsigned int x : 15; + unsigned int y : 16; +}; + +// CHECK-LABEL: define dso_local void @_Z3fS5v( +// CHECK-SAME: ) #[[ATTR0]] !dbg [[DBG81:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[S5:%.*]] = alloca [[STRUCT_S5:%.*]], align 4, addrspace(5) +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_S5]], align 4, addrspace(5) +// CHECK-NEXT: [[S5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S5]] to ptr +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[S5]], [[META83:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S5]])), [[META88:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META89:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_S5]]), DIOpConstant(i32 0), DIOpBitOffset(i32)), [[META90:![0-9]+]]) +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[S5_ASCAST]], i64 4, i1 false), !dbg [[DBG91:![0-9]+]] +// CHECK-NEXT: ret void, !dbg [[DBG92:![0-9]+]] +// +void fS5() { + S5 s5; + auto [a, b] = s5; +} + +// Currently, LLVM when it emits the structured binding for a bitfield it also emits the DIExpression as an i32 (which mismaches the bitfield width) + + + + + + +//. +// CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +// CHECK: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// CHECK: [[DBG6]] = distinct !DISubprogram(name: "fS0", linkageName: "_Z3fS0v", scope: [[META7:![0-9]+]], file: [[META7]], line: 22, type: [[META8:![0-9]+]], scopeLine: 22, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META10:![0-9]+]]) +// CHECK: [[META7]] = !DIFile(filename: "{{.*}}heterogeneous-debug-info-structured-binding-bitfield.cpp", directory: {{.*}}) +// CHECK: [[META8]] = !DISubroutineType(types: [[META9:![0-9]+]]) +// CHECK: [[META9]] = !{null} +// CHECK: [[META10]] = !{[[META11]]} +// CHECK: [[META11]] = !DILocalVariable(name: "s0", scope: [[DBG6]], file: [[META7]], line: 23, type: [[META12:![0-9]+]]) +// CHECK: [[META12]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S0", file: [[META7]], line: 4, size: 32, flags: DIFlagTypePassByValue, elements: [[META13:![0-9]+]], identifier: "_ZTS2S0") +// CHECK: [[META13]] = !{[[META14:![0-9]+]], [[META16:![0-9]+]]} +// CHECK: [[META14]] = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: [[META12]], file: [[META7]], line: 5, baseType: [[META15:![0-9]+]], size: 16, flags: DIFlagBitField, extraData: i64 0) +// CHECK: [[META15]] = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned) +// CHECK: [[META16]] = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: [[META12]], file: [[META7]], line: 6, baseType: [[META15]], size: 16, offset: 16, flags: DIFlagBitField, extraData: i64 0) +// CHECK: [[META17]] = !DILocation(line: 23, column: 6, scope: [[DBG6]]) +// CHECK: [[META18]] = !DILocalVariable(name: "a", scope: [[DBG6]], file: [[META7]], line: 24, type: [[META15]]) +// CHECK: [[META19]] = !DILocation(line: 24, column: 9, scope: [[DBG6]]) +// CHECK: [[META20]] = !DILocalVariable(name: "b", scope: [[DBG6]], file: [[META7]], line: 24, type: [[META15]]) +// CHECK: [[META21]] = !DILocation(line: 24, column: 12, scope: [[DBG6]]) +// CHECK: [[DBG22]] = !DILocation(line: 24, column: 17, scope: [[DBG6]]) +// CHECK: [[DBG23]] = !DILocation(line: 25, column: 1, scope: [[DBG6]]) +// CHECK: [[DBG24]] = distinct !DISubprogram(name: "fS1", linkageName: "_Z3fS1v", scope: [[META7]], file: [[META7]], line: 45, type: [[META8]], scopeLine: 45, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META25:![0-9]+]]) +// CHECK: [[META25]] = !{[[META26]]} +// CHECK: [[META26]] = !DILocalVariable(name: "s1", scope: [[DBG24]], file: [[META7]], line: 46, type: [[META27:![0-9]+]]) +// CHECK: [[META27]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S1", file: [[META7]], line: 27, size: 32, flags: DIFlagTypePassByValue, elements: [[META28:![0-9]+]], identifier: "_ZTS2S1") +// CHECK: [[META28]] = !{[[META29:![0-9]+]], [[META30:![0-9]+]]} +// CHECK: [[META29]] = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: [[META27]], file: [[META7]], line: 28, baseType: [[META15]], size: 8, flags: DIFlagBitField, extraData: i64 0) +// CHECK: [[META30]] = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: [[META27]], file: [[META7]], line: 29, baseType: [[META15]], size: 8, offset: 8, flags: DIFlagBitField, extraData: i64 0) +// CHECK: [[META31]] = !DILocation(line: 46, column: 6, scope: [[DBG24]]) +// CHECK: [[META32]] = !DILocalVariable(name: "a", scope: [[DBG24]], file: [[META7]], line: 47, type: [[META15]]) +// CHECK: [[META33]] = !DILocation(line: 47, column: 9, scope: [[DBG24]]) +// CHECK: [[META34]] = !DILocalVariable(name: "b", scope: [[DBG24]], file: [[META7]], line: 47, type: [[META15]]) +// CHECK: [[META35]] = !DILocation(line: 47, column: 12, scope: [[DBG24]]) +// CHECK: [[DBG36]] = !DILocation(line: 47, column: 17, scope: [[DBG24]]) +// CHECK: [[DBG37]] = !DILocation(line: 48, column: 1, scope: [[DBG24]]) +// CHECK: [[DBG38]] = distinct !DISubprogram(name: "fS2", linkageName: "_Z3fS2v", scope: [[META7]], file: [[META7]], line: 68, type: [[META8]], scopeLine: 68, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META39:![0-9]+]]) +// CHECK: [[META39]] = !{[[META40]]} +// CHECK: [[META40]] = !DILocalVariable(name: "s2", scope: [[DBG38]], file: [[META7]], line: 69, type: [[META41:![0-9]+]]) +// CHECK: [[META41]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S2", file: [[META7]], line: 50, size: 32, flags: DIFlagTypePassByValue, elements: [[META42:![0-9]+]], identifier: "_ZTS2S2") +// CHECK: [[META42]] = !{[[META43:![0-9]+]], [[META44:![0-9]+]]} +// CHECK: [[META43]] = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: [[META41]], file: [[META7]], line: 51, baseType: [[META15]], size: 8, flags: DIFlagBitField, extraData: i64 0) +// CHECK: [[META44]] = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: [[META41]], file: [[META7]], line: 52, baseType: [[META15]], size: 16, offset: 8, flags: DIFlagBitField, extraData: i64 0) +// CHECK: [[META45]] = !DILocation(line: 69, column: 6, scope: [[DBG38]]) +// CHECK: [[META46]] = !DILocalVariable(name: "a", scope: [[DBG38]], file: [[META7]], line: 70, type: [[META15]]) +// CHECK: [[META47]] = !DILocation(line: 70, column: 9, scope: [[DBG38]]) +// CHECK: [[META48]] = !DILocalVariable(name: "b", scope: [[DBG38]], file: [[META7]], line: 70, type: [[META15]]) +// CHECK: [[META49]] = !DILocation(line: 70, column: 12, scope: [[DBG38]]) +// CHECK: [[DBG50]] = !DILocation(line: 70, column: 17, scope: [[DBG38]]) +// CHECK: [[DBG51]] = !DILocation(line: 71, column: 1, scope: [[DBG38]]) +// CHECK: [[DBG52]] = distinct !DISubprogram(name: "fS3", linkageName: "_Z3fS3v", scope: [[META7]], file: [[META7]], line: 91, type: [[META8]], scopeLine: 91, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META53:![0-9]+]]) +// CHECK: [[META53]] = !{[[META54]]} +// CHECK: [[META54]] = !DILocalVariable(name: "s3", scope: [[DBG52]], file: [[META7]], line: 92, type: [[META55:![0-9]+]]) +// CHECK: [[META55]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S3", file: [[META7]], line: 73, size: 64, flags: DIFlagTypePassByValue, elements: [[META56:![0-9]+]], identifier: "_ZTS2S3") +// CHECK: [[META56]] = !{[[META57:![0-9]+]], [[META58:![0-9]+]]} +// CHECK: [[META57]] = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: [[META55]], file: [[META7]], line: 74, baseType: [[META15]], size: 16, flags: DIFlagBitField, extraData: i64 0) +// CHECK: [[META58]] = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: [[META55]], file: [[META7]], line: 75, baseType: [[META15]], size: 32, offset: 32, flags: DIFlagBitField, extraData: i64 32) +// CHECK: [[META59]] = !DILocation(line: 92, column: 6, scope: [[DBG52]]) +// CHECK: [[META60]] = !DILocalVariable(name: "a", scope: [[DBG52]], file: [[META7]], line: 93, type: [[META15]]) +// CHECK: [[META61]] = !DILocation(line: 93, column: 9, scope: [[DBG52]]) +// CHECK: [[META62]] = !DILocalVariable(name: "b", scope: [[DBG52]], file: [[META7]], line: 93, type: [[META15]]) +// CHECK: [[META63]] = !DILocation(line: 93, column: 12, scope: [[DBG52]]) +// CHECK: [[DBG64]] = !DILocation(line: 93, column: 17, scope: [[DBG52]]) +// CHECK: [[DBG65]] = !DILocation(line: 94, column: 1, scope: [[DBG52]]) +// CHECK: [[DBG66]] = distinct !DISubprogram(name: "fS4", linkageName: "_Z3fS4v", scope: [[META7]], file: [[META7]], line: 115, type: [[META8]], scopeLine: 115, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META67:![0-9]+]]) +// CHECK: [[META67]] = !{[[META68]]} +// CHECK: [[META68]] = !DILocalVariable(name: "s4", scope: [[DBG66]], file: [[META7]], line: 116, type: [[META69:![0-9]+]]) +// CHECK: [[META69]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S4", file: [[META7]], line: 96, size: 64, flags: DIFlagTypePassByValue, elements: [[META70:![0-9]+]], identifier: "_ZTS2S4") +// CHECK: [[META70]] = !{[[META71:![0-9]+]], [[META72:![0-9]+]], [[META73:![0-9]+]]} +// CHECK: [[META71]] = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: [[META69]], file: [[META7]], line: 97, baseType: [[META15]], size: 16, flags: DIFlagBitField, extraData: i64 0) +// CHECK: [[META72]] = !DIDerivedType(tag: DW_TAG_member, scope: [[META69]], file: [[META7]], line: 98, baseType: [[META15]], offset: 32, flags: DIFlagBitField, extraData: i64 32) +// CHECK: [[META73]] = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: [[META69]], file: [[META7]], line: 99, baseType: [[META15]], size: 16, offset: 32, flags: DIFlagBitField, extraData: i64 32) +// CHECK: [[META74]] = !DILocation(line: 116, column: 6, scope: [[DBG66]]) +// CHECK: [[META75]] = !DILocalVariable(name: "a", scope: [[DBG66]], file: [[META7]], line: 117, type: [[META15]]) +// CHECK: [[META76]] = !DILocation(line: 117, column: 9, scope: [[DBG66]]) +// CHECK: [[META77]] = !DILocalVariable(name: "b", scope: [[DBG66]], file: [[META7]], line: 117, type: [[META15]]) +// CHECK: [[META78]] = !DILocation(line: 117, column: 12, scope: [[DBG66]]) +// CHECK: [[DBG79]] = !DILocation(line: 117, column: 17, scope: [[DBG66]]) +// CHECK: [[DBG80]] = !DILocation(line: 118, column: 1, scope: [[DBG66]]) +// CHECK: [[DBG81]] = distinct !DISubprogram(name: "fS5", linkageName: "_Z3fS5v", scope: [[META7]], file: [[META7]], line: 140, type: [[META8]], scopeLine: 140, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META82:![0-9]+]]) +// CHECK: [[META82]] = !{[[META83]]} +// CHECK: [[META83]] = !DILocalVariable(name: "s5", scope: [[DBG81]], file: [[META7]], line: 141, type: [[META84:![0-9]+]]) +// CHECK: [[META84]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S5", file: [[META7]], line: 123, size: 32, flags: DIFlagTypePassByValue, elements: [[META85:![0-9]+]], identifier: "_ZTS2S5") +// CHECK: [[META85]] = !{[[META86:![0-9]+]], [[META87:![0-9]+]]} +// CHECK: [[META86]] = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: [[META84]], file: [[META7]], line: 124, baseType: [[META15]], size: 15, flags: DIFlagBitField, extraData: i64 0) +// CHECK: [[META87]] = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: [[META84]], file: [[META7]], line: 125, baseType: [[META15]], size: 16, offset: 15, flags: DIFlagBitField, extraData: i64 0) +// CHECK: [[META88]] = !DILocation(line: 141, column: 6, scope: [[DBG81]]) +// CHECK: [[META89]] = !DILocalVariable(name: "a", scope: [[DBG81]], file: [[META7]], line: 142, type: [[META15]]) +// CHECK: [[META90]] = !DILocation(line: 142, column: 9, scope: [[DBG81]]) +// CHECK: [[DBG91]] = !DILocation(line: 142, column: 17, scope: [[DBG81]]) +// CHECK: [[DBG92]] = !DILocation(line: 143, column: 1, scope: [[DBG81]]) +//. diff --git a/clang/test/CodeGenCXX/heterogeneous-debug-info-structured-binding.cpp b/clang/test/CodeGenCXX/heterogeneous-debug-info-structured-binding.cpp new file mode 100644 index 0000000000000..8a6b740d609bb --- /dev/null +++ b/clang/test/CodeGenCXX/heterogeneous-debug-info-structured-binding.cpp @@ -0,0 +1,152 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x c++ -emit-llvm -fcuda-is-device -debug-info-kind=limited -gheterogeneous-dwarf -o - %s | FileCheck %s + +struct A { + int x; + int y; +}; + +// CHECK-LABEL: define dso_local noundef i32 @_Z1fv( +// CHECK-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[A:%.*]] = alloca [[STRUCT_A:%.*]], align 4, addrspace(5) +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_A]], align 4, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr +// CHECK-NEXT: [[A_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A]] to ptr +// CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(5) [[TMP1]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[A]], [[META12:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_A]])), [[META17:![0-9]+]]) +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 4 [[A_ASCAST]], ptr addrspace(4) align 4 @__const._Z1fv.a, i64 8, i1 false), !dbg [[META17]] +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META18:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_A]]), DIOpConstant(i32 0), DIOpBitOffset(i32)), [[META19:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META20:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_A]]), DIOpConstant(i32 32), DIOpBitOffset(i32)), [[META21:![0-9]+]]) +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[A_ASCAST]], i64 8, i1 false), !dbg [[DBG22:![0-9]+]] +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP1]], [[META23:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref([[STRUCT_A]]), DIOpConstant(i32 0), DIOpBitOffset(i32)), [[META24:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP1]], [[META25:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref([[STRUCT_A]]), DIOpConstant(i32 32), DIOpBitOffset(i32)), [[META26:![0-9]+]]) +// CHECK-NEXT: store ptr [[A_ASCAST]], ptr [[TMP3]], align 8, !dbg [[DBG27:![0-9]+]] +// CHECK-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_A]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG28:![0-9]+]] +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4, !dbg [[DBG28]] +// CHECK-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_A]], ptr [[TMP2]], i32 0, i32 1, !dbg [[DBG29:![0-9]+]] +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[Y]], align 4, !dbg [[DBG29]] +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP5]], !dbg [[DBG30:![0-9]+]] +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG31:![0-9]+]], !nonnull [[META32:![0-9]+]], !align [[META33:![0-9]+]] +// CHECK-NEXT: [[X1:%.*]] = getelementptr inbounds nuw [[STRUCT_A]], ptr [[TMP6]], i32 0, i32 0, !dbg [[DBG31]] +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[X1]], align 4, !dbg [[DBG31]] +// CHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[ADD]], [[TMP7]], !dbg [[DBG34:![0-9]+]] +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG35:![0-9]+]], !nonnull [[META32]], !align [[META33]] +// CHECK-NEXT: [[Y3:%.*]] = getelementptr inbounds nuw [[STRUCT_A]], ptr [[TMP8]], i32 0, i32 1, !dbg [[DBG35]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[Y3]], align 4, !dbg [[DBG35]] +// CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[ADD2]], [[TMP9]], !dbg [[DBG36:![0-9]+]] +// CHECK-NEXT: ret i32 [[ADD4]], !dbg [[DBG37:![0-9]+]] +// +int f() { + A a{10, 20}; + auto [x1, y1] = a; + auto &[x2, y2] = a; + return x1 + y1 + x2 + y2; +} + +// CHECK-LABEL: define dso_local noundef i32 @_Z1gv( +// CHECK-SAME: ) #[[ATTR0]] !dbg [[DBG38:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[A:%.*]] = alloca [2 x i32], align 4, addrspace(5) +// CHECK-NEXT: [[TMP0:%.*]] = alloca [2 x i32], align 4, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr +// CHECK-NEXT: [[A_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A]] to ptr +// CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(5) [[TMP1]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[A]], [[META40:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([2 x i32])), [[META46:![0-9]+]]) +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 4 [[A_ASCAST]], ptr addrspace(4) align 4 @__const._Z1gv.A, i64 8, i1 false), !dbg [[META46]] +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META47:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([2 x i32]), DIOpConstant(i32 0), DIOpByteOffset(i32)), [[META48:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META49:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([2 x i32]), DIOpConstant(i32 4), DIOpByteOffset(i32)), [[META50:![0-9]+]]) +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 4 [[TMP2]], ptr addrspace(4) align 4 @__const._Z1gv., i64 8, i1 false), !dbg [[DBG51:![0-9]+]] +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP1]], [[META52:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref([2 x i32]), DIOpConstant(i32 0), DIOpByteOffset(i32)), [[META53:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP1]], [[META54:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref([2 x i32]), DIOpConstant(i32 4), DIOpByteOffset(i32)), [[META55:![0-9]+]]) +// CHECK-NEXT: store ptr [[A_ASCAST]], ptr [[TMP3]], align 8, !dbg [[DBG56:![0-9]+]] +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG57:![0-9]+]] +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG57]] +// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG58:![0-9]+]] +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4, !dbg [[DBG58]] +// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP4]], [[TMP5]], !dbg [[DBG59:![0-9]+]] +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG60:![0-9]+]], !nonnull [[META32]], !align [[META33]] +// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP6]], i64 0, i64 0, !dbg [[DBG60]] +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4, !dbg [[DBG60]] +// CHECK-NEXT: [[ADD3:%.*]] = add i32 [[ADD]], [[TMP7]], !dbg [[DBG61:![0-9]+]] +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG62:![0-9]+]], !nonnull [[META32]], !align [[META33]] +// CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG62]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG62]] +// CHECK-NEXT: [[ADD5:%.*]] = add i32 [[ADD3]], [[TMP9]], !dbg [[DBG63:![0-9]+]] +// CHECK-NEXT: ret i32 [[ADD5]], !dbg [[DBG64:![0-9]+]] +// +int g() { + const unsigned A[] = { 10, 20}; + auto [x3, y3] = A; + auto &[x4, y4] = A; + return x3 + y3 + x4 + y4; +} +//. +// CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +// CHECK: [[META1]] = !DIFile(filename: {{.*}}clang/test/CodeGenCXX/", directory: "") +// CHECK: [[DBG6]] = distinct !DISubprogram(name: "f", linkageName: "_Z1fv", scope: [[META7:![0-9]+]], file: [[META7]], line: 43, type: [[META8:![0-9]+]], scopeLine: 43, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META11:![0-9]+]]) +// CHECK: [[META7]] = !DIFile(filename: {{.*}}/clang/test/CodeGenCXX/heterogeneous-debug-info-structured-binding.cpp", directory: "") +// CHECK: [[META8]] = !DISubroutineType(types: [[META9:![0-9]+]]) +// CHECK: [[META9]] = !{[[META10:![0-9]+]]} +// CHECK: [[META10]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +// CHECK: [[META11]] = !{[[META12]]} +// CHECK: [[META12]] = !DILocalVariable(name: "a", scope: [[DBG6]], file: [[META7]], line: 44, type: [[META13:![0-9]+]]) +// CHECK: [[META13]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "A", file: [[META7]], line: 4, size: 64, flags: DIFlagTypePassByValue, elements: [[META14:![0-9]+]], identifier: "_ZTS1A") +// CHECK: [[META14]] = !{[[META15:![0-9]+]], [[META16:![0-9]+]]} +// CHECK: [[META15]] = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: [[META13]], file: [[META7]], line: 5, baseType: [[META10]], size: 32) +// CHECK: [[META16]] = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: [[META13]], file: [[META7]], line: 6, baseType: [[META10]], size: 32, offset: 32) +// CHECK: [[META17]] = !DILocation(line: 44, column: 5, scope: [[DBG6]]) +// CHECK: [[META18]] = !DILocalVariable(name: "x1", scope: [[DBG6]], file: [[META7]], line: 45, type: [[META10]]) +// CHECK: [[META19]] = !DILocation(line: 45, column: 9, scope: [[DBG6]]) +// CHECK: [[META20]] = !DILocalVariable(name: "y1", scope: [[DBG6]], file: [[META7]], line: 45, type: [[META10]]) +// CHECK: [[META21]] = !DILocation(line: 45, column: 13, scope: [[DBG6]]) +// CHECK: [[DBG22]] = !DILocation(line: 45, column: 19, scope: [[DBG6]]) +// CHECK: [[META23]] = !DILocalVariable(name: "x2", scope: [[DBG6]], file: [[META7]], line: 46, type: [[META10]]) +// CHECK: [[META24]] = !DILocation(line: 46, column: 10, scope: [[DBG6]]) +// CHECK: [[META25]] = !DILocalVariable(name: "y2", scope: [[DBG6]], file: [[META7]], line: 46, type: [[META10]]) +// CHECK: [[META26]] = !DILocation(line: 46, column: 14, scope: [[DBG6]]) +// CHECK: [[DBG27]] = !DILocation(line: 46, column: 9, scope: [[DBG6]]) +// CHECK: [[DBG28]] = !DILocation(line: 47, column: 10, scope: [[DBG6]]) +// CHECK: [[DBG29]] = !DILocation(line: 47, column: 15, scope: [[DBG6]]) +// CHECK: [[DBG30]] = !DILocation(line: 47, column: 13, scope: [[DBG6]]) +// CHECK: [[DBG31]] = !DILocation(line: 47, column: 20, scope: [[DBG6]]) +// CHECK: [[META32]] = !{} +// CHECK: [[META33]] = !{i64 4} +// CHECK: [[DBG34]] = !DILocation(line: 47, column: 18, scope: [[DBG6]]) +// CHECK: [[DBG35]] = !DILocation(line: 47, column: 25, scope: [[DBG6]]) +// CHECK: [[DBG36]] = !DILocation(line: 47, column: 23, scope: [[DBG6]]) +// CHECK: [[DBG37]] = !DILocation(line: 47, column: 3, scope: [[DBG6]]) +// CHECK: [[DBG38]] = distinct !DISubprogram(name: "g", linkageName: "_Z1gv", scope: [[META7]], file: [[META7]], line: 84, type: [[META8]], scopeLine: 84, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META39:![0-9]+]]) +// CHECK: [[META39]] = !{[[META40]]} +// CHECK: [[META40]] = !DILocalVariable(name: "A", scope: [[DBG38]], file: [[META7]], line: 85, type: [[META41:![0-9]+]]) +// CHECK: [[META41]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META42:![0-9]+]], size: 64, elements: [[META44:![0-9]+]]) +// CHECK: [[META42]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META43:![0-9]+]]) +// CHECK: [[META43]] = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned) +// CHECK: [[META44]] = !{[[META45:![0-9]+]]} +// CHECK: [[META45]] = !DISubrange(count: 2) +// CHECK: [[META46]] = !DILocation(line: 85, column: 18, scope: [[DBG38]]) +// CHECK: [[META47]] = !DILocalVariable(name: "x3", scope: [[DBG38]], file: [[META7]], line: 86, type: [[META42]]) +// CHECK: [[META48]] = !DILocation(line: 86, column: 9, scope: [[DBG38]]) +// CHECK: [[META49]] = !DILocalVariable(name: "y3", scope: [[DBG38]], file: [[META7]], line: 86, type: [[META42]]) +// CHECK: [[META50]] = !DILocation(line: 86, column: 13, scope: [[DBG38]]) +// CHECK: [[DBG51]] = !DILocation(line: 86, column: 8, scope: [[DBG38]]) +// CHECK: [[META52]] = !DILocalVariable(name: "x4", scope: [[DBG38]], file: [[META7]], line: 87, type: [[META42]]) +// CHECK: [[META53]] = !DILocation(line: 87, column: 10, scope: [[DBG38]]) +// CHECK: [[META54]] = !DILocalVariable(name: "y4", scope: [[DBG38]], file: [[META7]], line: 87, type: [[META42]]) +// CHECK: [[META55]] = !DILocation(line: 87, column: 14, scope: [[DBG38]]) +// CHECK: [[DBG56]] = !DILocation(line: 87, column: 9, scope: [[DBG38]]) +// CHECK: [[DBG57]] = !DILocation(line: 88, column: 10, scope: [[DBG38]]) +// CHECK: [[DBG58]] = !DILocation(line: 88, column: 15, scope: [[DBG38]]) +// CHECK: [[DBG59]] = !DILocation(line: 88, column: 13, scope: [[DBG38]]) +// CHECK: [[DBG60]] = !DILocation(line: 88, column: 20, scope: [[DBG38]]) +// CHECK: [[DBG61]] = !DILocation(line: 88, column: 18, scope: [[DBG38]]) +// CHECK: [[DBG62]] = !DILocation(line: 88, column: 25, scope: [[DBG38]]) +// CHECK: [[DBG63]] = !DILocation(line: 88, column: 23, scope: [[DBG38]]) +// CHECK: [[DBG64]] = !DILocation(line: 88, column: 3, scope: [[DBG38]]) +//. diff --git a/clang/test/CodeGenHIP/debug-info-address-class-heterogeneous-dwarf.hip b/clang/test/CodeGenHIP/debug-info-address-class-heterogeneous-dwarf.hip new file mode 100644 index 0000000000000..44d339f5ac472 --- /dev/null +++ b/clang/test/CodeGenHIP/debug-info-address-class-heterogeneous-dwarf.hip @@ -0,0 +1,57 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -emit-llvm -fcuda-is-device -debug-info-kind=limited -gheterogeneous-dwarf -o - %s | FileCheck %s + +#define __device__ __attribute__((device)) +#define __shared__ __attribute__((shared)) +#define __constant__ __attribute__((constant)) + +__device__ int FileVarDevice; + +__device__ __shared__ int FileVarDeviceShared; + +__device__ __constant__ int FileVarDeviceConstant; + +// CHECK-LABEL: define dso_local void @_Z7kernel1i( +// CHECK-SAME: i32 noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG13:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[FUNCVAR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[ARG_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARG_ADDR]] to ptr +// CHECK-NEXT: [[FUNCVAR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[FUNCVAR]] to ptr +// CHECK-NEXT: store i32 [[ARG]], ptr [[ARG_ADDR_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[ARG_ADDR]], [[META17:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META24:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[FUNCVAR]], [[META18:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META25:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG26:![0-9]+]] +// +__device__ void kernel1(int Arg) { + + __shared__ int FuncVarShared; + + int FuncVar; +} + +//. +// CHECK: [[META0:![0-9]+]] = !DIGlobalVariableExpression(var: [[META1:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(1)), DIOpDeref(i32))) +// CHECK: [[META1]] = distinct !DIGlobalVariable(name: "FileVarDevice", scope: [[META2:![0-9]+]], file: [[META7:![0-9]+]], line: 9, type: [[META8:![0-9]+]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) +// CHECK: [[META2]] = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: [[META3:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: [[META4:![0-9]+]], splitDebugInlining: false, nameTableKind: None) +// CHECK: [[META3]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// CHECK: [[META4]] = !{[[META0]], [[META5:![0-9]+]], [[META9:![0-9]+]], [[META11:![0-9]+]]} +// CHECK: [[META5]] = !DIGlobalVariableExpression(var: [[META6:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpDeref(i32))) +// CHECK: [[META6]] = distinct !DIGlobalVariable(name: "FileVarDeviceShared", scope: [[META2]], file: [[META7]], line: 11, type: [[META8]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) +// CHECK: [[META7]] = !DIFile(filename: "{{.*}}debug-info-address-class-heterogeneous-dwarf.hip", directory: {{.*}}) +// CHECK: [[META8]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +// CHECK: [[META9]] = !DIGlobalVariableExpression(var: [[META10:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(4)), DIOpDeref(i32))) +// CHECK: [[META10]] = distinct !DIGlobalVariable(name: "FileVarDeviceConstant", scope: [[META2]], file: [[META7]], line: 13, type: [[META8]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) +// CHECK: [[META11]] = !DIGlobalVariableExpression(var: [[META12:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpDeref(i32))) +// CHECK: [[META12]] = distinct !DIGlobalVariable(name: "FuncVarShared", scope: [[DBG13]], file: [[META7]], line: 29, type: [[META8]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) +// CHECK: [[DBG13]] = distinct !DISubprogram(name: "kernel1", linkageName: "_Z7kernel1i", scope: [[META7]], file: [[META7]], line: 27, type: [[META14:![0-9]+]], scopeLine: 27, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META2]], retainedNodes: [[META16:![0-9]+]]) +// CHECK: [[META14]] = !DISubroutineType(types: [[META15:![0-9]+]]) +// CHECK: [[META15]] = !{null, [[META8]]} +// CHECK: [[META16]] = !{[[META17]], [[META18]]} +// CHECK: [[META17]] = !DILocalVariable(name: "Arg", arg: 1, scope: [[DBG13]], file: [[META7]], line: 27, type: [[META8]]) +// CHECK: [[META18]] = !DILocalVariable(name: "FuncVar", scope: [[DBG13]], file: [[META7]], line: 31, type: [[META8]]) +// CHECK: [[META24]] = !DILocation(line: 27, column: 29, scope: [[DBG13]]) +// CHECK: [[META25]] = !DILocation(line: 31, column: 7, scope: [[DBG13]]) +// CHECK: [[DBG26]] = !DILocation(line: 32, column: 1, scope: [[DBG13]]) +//. diff --git a/clang/test/CodeGenHIP/debug-info-amdgcn-abi-heterogeneous-dwarf.hip b/clang/test/CodeGenHIP/debug-info-amdgcn-abi-heterogeneous-dwarf.hip new file mode 100644 index 0000000000000..8f37b2edbcb66 --- /dev/null +++ b/clang/test/CodeGenHIP/debug-info-amdgcn-abi-heterogeneous-dwarf.hip @@ -0,0 +1,1727 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -O0 -debug-info-kind=limited -gheterogeneous-dwarf -triple amdgcn-amd-amdhsa -x hip -emit-llvm -fcuda-is-device -o - %s | FileCheck %s + +// Notes: +// * There is no test involving transparent_union, as this isn't supported in +// C++, and so is not supported in HIP. +// * There is no test involving flexible array members, as this isn't supported +// in C++ without an extension. +// * AMDGCN uses the ItaniumCXXABI, which seems to require one trivial, +// non-deleted copy or move constructor in order to allow Default passing, +// otherwise it selects Indirect. There is a "non-ByVal" form of Indirect, +// which seems to add an extra indirection to avoid a copy, but this is only +// used by the MicrosoftCXXABI, so AFAICT it is impossible to construct for +// AMDGCN. +// * The tests are not exhaustive by any stretch, but try to cover all of the +// relevant corner cases from the perspective of debug info. One notable +// omission is any consideration for return values, as this isn't (currently) +// present in the debug info at all. + +#define __device__ __attribute__((device)) +#define __global__ __attribute__((global)) +#define int8_t char +#define uint8_t unsigned int8_t +#define int16_t short +#define uint16_t unsigned int16_t +#define int32_t int +#define uint32_t unsigned int32_t +#define int64_t long +#define uint64_t unsigned int64_t + +struct StructEmpty {}; +struct StructSingleElement { + int8_t Element0; +}; +struct StructSingleElementRecursive { + StructSingleElement Element0; +}; +struct StructTrivialCopyTrivialMove { + int8_t Element0; + __device__ StructTrivialCopyTrivialMove(const StructTrivialCopyTrivialMove &) = default; + __device__ StructTrivialCopyTrivialMove(StructTrivialCopyTrivialMove &&) = default; +}; +struct StructNoCopyTrivialMove { + int8_t Element0; + __device__ StructNoCopyTrivialMove(const StructNoCopyTrivialMove &) = delete; + __device__ StructNoCopyTrivialMove(StructNoCopyTrivialMove &&) = default; +}; +struct StructTrivialCopyNoMove { + int8_t Element0; + __device__ StructTrivialCopyNoMove(const StructTrivialCopyNoMove &) = default; + __device__ StructTrivialCopyNoMove(StructTrivialCopyNoMove &&) = delete; +}; +struct StructNoCopyNoMove { + int8_t Element0; + __device__ StructNoCopyNoMove(const StructNoCopyNoMove &) = delete; + __device__ StructNoCopyNoMove(StructNoCopyNoMove &&) = delete; +}; +template +struct StructNBytes { + static_assert(N > 1, ""); + int8_t Element0; + int8_t Elements[N - 1u]; +}; +enum EnumInt8T : int8_t {}; +enum EnumUInt8T : uint8_t {}; +enum EnumInt16T : int16_t {}; +enum EnumUInt16T : uint16_t {}; +enum EnumInt32T : int32_t {}; +enum EnumUInt32T : uint32_t {}; +enum EnumInt64T : int64_t {}; +enum EnumUInt64T : uint64_t {}; +struct StructSinglePointerElement { + int32_t *Element0; +}; +struct StructPointerElements { + int32_t *Element0; + float *Element1; +}; +struct StructMultipleElements { + int32_t Element0; + int64_t Element1; +}; + +// CHECK-LABEL: define dso_local void @_Z21Test_Func_StructEmpty11StructEmpty( +// CHECK-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG26:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP:%.*]] = alloca [[STRUCT_STRUCTEMPTY:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP]], [[META31:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTEMPTY]])), [[META32:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG33:![0-9]+]] +// +__device__ void Test_Func_StructEmpty(StructEmpty) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z21Test_Kern_StructEmpty11StructEmpty( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTEMPTY:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG34:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTEMPTY]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 1 [[TMP1]], ptr addrspace(4) align 1 [[TMP0]], i64 1, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META36:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTEMPTY]])), [[META37:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG38:![0-9]+]] +// +__global__ void Test_Kern_StructEmpty(StructEmpty) {} +// CHECK-LABEL: define dso_local void @_Z29Test_Func_StructSingleElement19StructSingleElement( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG39:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTSINGLEELEMENT:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTSINGLEELEMENT]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META46:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTSINGLEELEMENT]])), [[META47:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG48:![0-9]+]] +// +__device__ void Test_Func_StructSingleElement(StructSingleElement) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z29Test_Kern_StructSingleElement19StructSingleElement( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR1]] !dbg [[DBG49:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTSINGLEELEMENT:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTSINGLEELEMENT]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META51:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTSINGLEELEMENT]])), [[META52:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG53:![0-9]+]] +// +__global__ void Test_Kern_StructSingleElement(StructSingleElement) {} +// CHECK-LABEL: define dso_local void @_Z38Test_Func_StructSingleElementRecursive28StructSingleElementRecursive( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG54:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTSINGLEELEMENTRECURSIVE:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTSINGLEELEMENTRECURSIVE]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTSINGLEELEMENT:%.*]], ptr [[COERCE_DIVE]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE1]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META61:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTSINGLEELEMENTRECURSIVE]])), [[META62:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG63:![0-9]+]] +// +__device__ void Test_Func_StructSingleElementRecursive(StructSingleElementRecursive) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z38Test_Kern_StructSingleElementRecursive28StructSingleElementRecursive( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR1]] !dbg [[DBG64:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTSINGLEELEMENTRECURSIVE:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTSINGLEELEMENTRECURSIVE]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: [[COERCE_DIVE1:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTSINGLEELEMENT:%.*]], ptr [[COERCE_DIVE]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE1]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META66:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTSINGLEELEMENTRECURSIVE]])), [[META67:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG68:![0-9]+]] +// +__global__ void Test_Kern_StructSingleElementRecursive(StructSingleElementRecursive) {} +// CHECK-LABEL: define dso_local void @_Z38Test_Func_StructTrivialCopyTrivialMove28StructTrivialCopyTrivialMove( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG69:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTTRIVIALCOPYTRIVIALMOVE:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTTRIVIALCOPYTRIVIALMOVE]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META86:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTTRIVIALCOPYTRIVIALMOVE]])), [[META87:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG88:![0-9]+]] +// +__device__ void Test_Func_StructTrivialCopyTrivialMove(StructTrivialCopyTrivialMove) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z38Test_Kern_StructTrivialCopyTrivialMove28StructTrivialCopyTrivialMove( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR1]] !dbg [[DBG89:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTTRIVIALCOPYTRIVIALMOVE:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTTRIVIALCOPYTRIVIALMOVE]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META91:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTTRIVIALCOPYTRIVIALMOVE]])), [[META92:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG93:![0-9]+]] +// +__global__ void Test_Kern_StructTrivialCopyTrivialMove(StructTrivialCopyTrivialMove) {} +// CHECK-LABEL: define dso_local void @_Z33Test_Func_StructNoCopyTrivialMove23StructNoCopyTrivialMove( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG94:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNOCOPYTRIVIALMOVE:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTNOCOPYTRIVIALMOVE]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META111:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNOCOPYTRIVIALMOVE]])), [[META112:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG113:![0-9]+]] +// +__device__ void Test_Func_StructNoCopyTrivialMove(StructNoCopyTrivialMove) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z33Test_Kern_StructNoCopyTrivialMove23StructNoCopyTrivialMove( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR1]] !dbg [[DBG114:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNOCOPYTRIVIALMOVE:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTNOCOPYTRIVIALMOVE]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META116:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNOCOPYTRIVIALMOVE]])), [[META117:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG118:![0-9]+]] +// +__global__ void Test_Kern_StructNoCopyTrivialMove(StructNoCopyTrivialMove) {} +// CHECK-LABEL: define dso_local void @_Z33Test_Func_StructTrivialCopyNoMove23StructTrivialCopyNoMove( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG119:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTTRIVIALCOPYNOMOVE:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTTRIVIALCOPYNOMOVE]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META136:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTTRIVIALCOPYNOMOVE]])), [[META137:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG138:![0-9]+]] +// +__device__ void Test_Func_StructTrivialCopyNoMove(StructTrivialCopyNoMove) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z33Test_Kern_StructTrivialCopyNoMove23StructTrivialCopyNoMove( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR1]] !dbg [[DBG139:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTTRIVIALCOPYNOMOVE:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTTRIVIALCOPYNOMOVE]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META141:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTTRIVIALCOPYNOMOVE]])), [[META142:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG143:![0-9]+]] +// +__global__ void Test_Kern_StructTrivialCopyNoMove(StructTrivialCopyNoMove) {} +// CHECK-LABEL: define dso_local void @_Z28Test_Func_StructNoCopyNoMove18StructNoCopyNoMove( +// CHECK-SAME: ptr addrspace(5) dead_on_return noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG144:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTINDIRECT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTINDIRECT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTINDIRECT_ADDR]] to ptr +// CHECK-NEXT: store ptr addrspace(5) [[TMP0]], ptr [[DOTINDIRECT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTINDIRECT_ADDR]], [[META161:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNOCOPYNOMOVE:%.*]])), [[META162:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG163:![0-9]+]] +// +__device__ void Test_Func_StructNoCopyNoMove(StructNoCopyNoMove) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z28Test_Kern_StructNoCopyNoMove18StructNoCopyNoMove( +// CHECK-SAME: i8 [[DOTCOERCE:%.*]]) #[[ATTR1]] !dbg [[DBG164:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNOCOPYNOMOVE:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTNOCOPYNOMOVE]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META166:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNOCOPYNOMOVE]])), [[META167:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG168:![0-9]+]] +// +__global__ void Test_Kern_StructNoCopyNoMove(StructNoCopyNoMove) {} +// CHECK-LABEL: define dso_local void @_Z22Test_Func_Struct2Bytes12StructNBytesILj2EE( +// CHECK-SAME: i16 [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG169:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNBYTES:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: store i16 [[DOTCOERCE]], ptr [[TMP1]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META182:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES]])), [[META183:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG184:![0-9]+]] +// +__device__ void Test_Func_Struct2Bytes(StructNBytes<2>) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z22Test_Kern_Struct2Bytes12StructNBytesILj2EE( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTNBYTES:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG185:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTNBYTES]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 1 [[TMP1]], ptr addrspace(4) align 1 [[TMP0]], i64 2, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META187:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES]])), [[META188:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG189:![0-9]+]] +// +__global__ void Test_Kern_Struct2Bytes(StructNBytes<2>) {} +// CHECK-LABEL: define dso_local void @_Z22Test_Func_Struct3Bytes12StructNBytesILj3EE( +// CHECK-SAME: i32 [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG190:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNBYTES_0:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_VAL_II:%.*]] = trunc i32 [[DOTCOERCE]] to i24 +// CHECK-NEXT: store i24 [[COERCE_VAL_II]], ptr [[TMP1]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META203:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_0]])), [[META204:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG205:![0-9]+]] +// +__device__ void Test_Func_Struct3Bytes(StructNBytes<3>) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z22Test_Kern_Struct3Bytes12StructNBytesILj3EE( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTNBYTES_0:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG206:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTNBYTES_0]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 1 [[TMP1]], ptr addrspace(4) align 1 [[TMP0]], i64 3, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META208:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_0]])), [[META209:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG210:![0-9]+]] +// +__global__ void Test_Kern_Struct3Bytes(StructNBytes<3>) {} +// CHECK-LABEL: define dso_local void @_Z22Test_Func_Struct4Bytes12StructNBytesILj4EE( +// CHECK-SAME: i32 [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG211:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNBYTES_1:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: store i32 [[DOTCOERCE]], ptr [[TMP1]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META224:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_1]])), [[META225:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG226:![0-9]+]] +// +__device__ void Test_Func_Struct4Bytes(StructNBytes<4>) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z22Test_Kern_Struct4Bytes12StructNBytesILj4EE( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTNBYTES_1:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG227:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTNBYTES_1]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 1 [[TMP1]], ptr addrspace(4) align 1 [[TMP0]], i64 4, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META229:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_1]])), [[META230:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG231:![0-9]+]] +// +__global__ void Test_Kern_Struct4Bytes(StructNBytes<4>) {} +// CHECK-LABEL: define dso_local void @_Z22Test_Func_Struct5Bytes12StructNBytesILj5EE( +// CHECK-SAME: [2 x i32] [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG232:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNBYTES_2:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP_COERCE:%.*]] = alloca [2 x i32], align 4, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[TMP_COERCE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP_COERCE]] to ptr +// CHECK-NEXT: store [2 x i32] [[DOTCOERCE]], ptr [[TMP_COERCE_ASCAST]], align 4 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[TMP1]], ptr align 4 [[TMP_COERCE_ASCAST]], i64 5, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META245:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_2]])), [[META246:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG247:![0-9]+]] +// +__device__ void Test_Func_Struct5Bytes(StructNBytes<5>) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z22Test_Kern_Struct5Bytes12StructNBytesILj5EE( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTNBYTES_2:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG248:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTNBYTES_2]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 1 [[TMP1]], ptr addrspace(4) align 1 [[TMP0]], i64 5, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META250:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_2]])), [[META251:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG252:![0-9]+]] +// +__global__ void Test_Kern_Struct5Bytes(StructNBytes<5>) {} +// CHECK-LABEL: define dso_local void @_Z22Test_Func_Struct6Bytes12StructNBytesILj6EE( +// CHECK-SAME: [2 x i32] [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG253:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNBYTES_3:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP_COERCE:%.*]] = alloca [2 x i32], align 4, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[TMP_COERCE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP_COERCE]] to ptr +// CHECK-NEXT: store [2 x i32] [[DOTCOERCE]], ptr [[TMP_COERCE_ASCAST]], align 4 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[TMP1]], ptr align 4 [[TMP_COERCE_ASCAST]], i64 6, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META266:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_3]])), [[META267:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG268:![0-9]+]] +// +__device__ void Test_Func_Struct6Bytes(StructNBytes<6>) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z22Test_Kern_Struct6Bytes12StructNBytesILj6EE( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTNBYTES_3:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG269:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTNBYTES_3]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 1 [[TMP1]], ptr addrspace(4) align 1 [[TMP0]], i64 6, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META271:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_3]])), [[META272:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG273:![0-9]+]] +// +__global__ void Test_Kern_Struct6Bytes(StructNBytes<6>) {} +// CHECK-LABEL: define dso_local void @_Z22Test_Func_Struct7Bytes12StructNBytesILj7EE( +// CHECK-SAME: [2 x i32] [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG274:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNBYTES_4:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP_COERCE:%.*]] = alloca [2 x i32], align 4, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[TMP_COERCE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP_COERCE]] to ptr +// CHECK-NEXT: store [2 x i32] [[DOTCOERCE]], ptr [[TMP_COERCE_ASCAST]], align 4 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[TMP1]], ptr align 4 [[TMP_COERCE_ASCAST]], i64 7, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META287:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_4]])), [[META288:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG289:![0-9]+]] +// +__device__ void Test_Func_Struct7Bytes(StructNBytes<7>) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z22Test_Kern_Struct7Bytes12StructNBytesILj7EE( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTNBYTES_4:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG290:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTNBYTES_4]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 1 [[TMP1]], ptr addrspace(4) align 1 [[TMP0]], i64 7, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META292:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_4]])), [[META293:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG294:![0-9]+]] +// +__global__ void Test_Kern_Struct7Bytes(StructNBytes<7>) {} +// CHECK-LABEL: define dso_local void @_Z22Test_Func_Struct8Bytes12StructNBytesILj8EE( +// CHECK-SAME: [2 x i32] [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG295:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNBYTES_5:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: store [2 x i32] [[DOTCOERCE]], ptr [[TMP1]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META308:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_5]])), [[META309:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG310:![0-9]+]] +// +__device__ void Test_Func_Struct8Bytes(StructNBytes<8>) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z22Test_Kern_Struct8Bytes12StructNBytesILj8EE( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTNBYTES_5:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG311:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTNBYTES_5]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 1 [[TMP1]], ptr addrspace(4) align 1 [[TMP0]], i64 8, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META313:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_5]])), [[META314:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG315:![0-9]+]] +// +__global__ void Test_Kern_Struct8Bytes(StructNBytes<8>) {} +// CHECK-LABEL: define dso_local void @_Z22Test_Func_Struct9Bytes12StructNBytesILj9EE( +// CHECK-SAME: i8 [[DOTCOERCE0:%.*]], [8 x i8] [[DOTCOERCE1:%.*]]) #[[ATTR0]] !dbg [[DBG316:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTNBYTES_6:%.*]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTNBYTES_6]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i8 [[DOTCOERCE0]], ptr [[TMP2]], align 1 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTNBYTES_6]], ptr [[TMP1]], i32 0, i32 1 +// CHECK-NEXT: store [8 x i8] [[DOTCOERCE1]], ptr [[TMP3]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META329:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_6]])), [[META330:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG331:![0-9]+]] +// +__device__ void Test_Func_Struct9Bytes(StructNBytes<9>) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z22Test_Kern_Struct9Bytes12StructNBytesILj9EE( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTNBYTES_6:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG332:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTNBYTES_6]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 1 [[TMP1]], ptr addrspace(4) align 1 [[TMP0]], i64 9, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META334:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_6]])), [[META335:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG336:![0-9]+]] +// +__global__ void Test_Kern_Struct9Bytes(StructNBytes<9>) {} +// CHECK-LABEL: define dso_local void @_Z23Test_Func_Struct64Bytes12StructNBytesILj64EE( +// CHECK-SAME: ptr addrspace(5) noundef byref([[STRUCT_STRUCTNBYTES_7:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG337:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTNBYTES_7]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p5.i64(ptr align 1 [[TMP1]], ptr addrspace(5) align 1 [[TMP0]], i64 64, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META350:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_7]])), [[META351:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG352:![0-9]+]] +// +__device__ void Test_Func_Struct64Bytes(StructNBytes<64>) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z23Test_Kern_Struct64Bytes12StructNBytesILj64EE( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTNBYTES_7:%.*]]) align 1 [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG353:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTNBYTES_7]], align 1, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 1 [[TMP1]], ptr addrspace(4) align 1 [[TMP0]], i64 64, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META355:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTNBYTES_7]])), [[META356:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG357:![0-9]+]] +// +__global__ void Test_Kern_Struct64Bytes(StructNBytes<64>) {} +// CHECK-LABEL: define dso_local void @_Z15Test_Func_Int8Tc( +// CHECK-SAME: i8 noundef signext [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG358:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8, align 1, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i8 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META362:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i8)), [[META363:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG364:![0-9]+]] +// +__device__ void Test_Func_Int8T(int8_t) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z15Test_Kern_Int8Tc( +// CHECK-SAME: i8 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG365:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8, align 1, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i8 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META367:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i8)), [[META368:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG369:![0-9]+]] +// +__global__ void Test_Kern_Int8T(int8_t) {} +// CHECK-LABEL: define dso_local void @_Z16Test_Func_UInt8Th( +// CHECK-SAME: i8 noundef zeroext [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG370:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8, align 1, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i8 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META374:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i8)), [[META375:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG376:![0-9]+]] +// +__device__ void Test_Func_UInt8T(uint8_t) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z16Test_Kern_UInt8Th( +// CHECK-SAME: i8 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG377:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8, align 1, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i8 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META379:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i8)), [[META380:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG381:![0-9]+]] +// +__global__ void Test_Kern_UInt8T(uint8_t) {} +// CHECK-LABEL: define dso_local void @_Z16Test_Func_Int16Ts( +// CHECK-SAME: i16 noundef signext [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG382:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i16 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 2 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META386:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i16)), [[META387:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG388:![0-9]+]] +// +__device__ void Test_Func_Int16T(int16_t) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z16Test_Kern_Int16Ts( +// CHECK-SAME: i16 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG389:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i16 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 2 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META391:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i16)), [[META392:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG393:![0-9]+]] +// +__global__ void Test_Kern_Int16T(int16_t) {} +// CHECK-LABEL: define dso_local void @_Z17Test_Func_UInt16Tt( +// CHECK-SAME: i16 noundef zeroext [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG394:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i16 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 2 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META398:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i16)), [[META399:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG400:![0-9]+]] +// +__device__ void Test_Func_UInt16T(uint16_t) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z17Test_Kern_UInt16Tt( +// CHECK-SAME: i16 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG401:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i16 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 2 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META403:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i16)), [[META404:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG405:![0-9]+]] +// +__global__ void Test_Kern_UInt16T(uint16_t) {} +// CHECK-LABEL: define dso_local void @_Z16Test_Func_Int32Ti( +// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG406:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META410:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META411:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG412:![0-9]+]] +// +__device__ void Test_Func_Int32T(int32_t) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z16Test_Kern_Int32Ti( +// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG413:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META415:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META416:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG417:![0-9]+]] +// +__global__ void Test_Kern_Int32T(int32_t) {} +// CHECK-LABEL: define dso_local void @_Z17Test_Func_UInt32Tj( +// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG418:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META422:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META423:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG424:![0-9]+]] +// +__device__ void Test_Func_UInt32T(uint32_t) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z17Test_Kern_UInt32Tj( +// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG425:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META427:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META428:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG429:![0-9]+]] +// +__global__ void Test_Kern_UInt32T(uint32_t) {} +// CHECK-LABEL: define dso_local void @_Z16Test_Func_Int64Tl( +// CHECK-SAME: i64 noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG430:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META434:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META435:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG436:![0-9]+]] +// +__device__ void Test_Func_Int64T(int64_t) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z16Test_Kern_Int64Tl( +// CHECK-SAME: i64 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG437:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META439:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META440:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG441:![0-9]+]] +// +__global__ void Test_Kern_Int64T(int64_t) {} +// CHECK-LABEL: define dso_local void @_Z17Test_Func_UInt64Tm( +// CHECK-SAME: i64 noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG442:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META446:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META447:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG448:![0-9]+]] +// +__device__ void Test_Func_UInt64T(uint64_t) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z17Test_Kern_UInt64Tm( +// CHECK-SAME: i64 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG449:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META451:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META452:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG453:![0-9]+]] +// +__global__ void Test_Kern_UInt64T(uint64_t) {} +// CHECK-LABEL: define dso_local void @_Z19Test_Func_EnumInt8T9EnumInt8T( +// CHECK-SAME: i8 noundef signext [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG454:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8, align 1, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i8 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META458:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i8)), [[META459:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG460:![0-9]+]] +// +__device__ void Test_Func_EnumInt8T(EnumInt8T) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z19Test_Kern_EnumInt8T9EnumInt8T( +// CHECK-SAME: i8 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG461:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8, align 1, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i8 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META463:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i8)), [[META464:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG465:![0-9]+]] +// +__global__ void Test_Kern_EnumInt8T(EnumInt8T) {} +// CHECK-LABEL: define dso_local void @_Z20Test_Func_EnumUInt8T10EnumUInt8T( +// CHECK-SAME: i8 noundef zeroext [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG466:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8, align 1, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i8 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META470:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i8)), [[META471:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG472:![0-9]+]] +// +__device__ void Test_Func_EnumUInt8T(EnumUInt8T) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z20Test_Kern_EnumUInt8T10EnumUInt8T( +// CHECK-SAME: i8 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG473:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8, align 1, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i8 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META475:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i8)), [[META476:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG477:![0-9]+]] +// +__global__ void Test_Kern_EnumUInt8T(EnumUInt8T) {} +// CHECK-LABEL: define dso_local void @_Z20Test_Func_EnumInt16T10EnumInt16T( +// CHECK-SAME: i16 noundef signext [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG478:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i16 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 2 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META482:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i16)), [[META483:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG484:![0-9]+]] +// +__device__ void Test_Func_EnumInt16T(EnumInt16T) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z20Test_Kern_EnumInt16T10EnumInt16T( +// CHECK-SAME: i16 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG485:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i16 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 2 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META487:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i16)), [[META488:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG489:![0-9]+]] +// +__global__ void Test_Kern_EnumInt16T(EnumInt16T) {} +// CHECK-LABEL: define dso_local void @_Z21Test_Func_EnumUInt16T11EnumUInt16T( +// CHECK-SAME: i16 noundef zeroext [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG490:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i16 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 2 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META494:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i16)), [[META495:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG496:![0-9]+]] +// +__device__ void Test_Func_EnumUInt16T(EnumUInt16T) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z21Test_Kern_EnumUInt16T11EnumUInt16T( +// CHECK-SAME: i16 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG497:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i16 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 2 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META499:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i16)), [[META500:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG501:![0-9]+]] +// +__global__ void Test_Kern_EnumUInt16T(EnumUInt16T) {} +// CHECK-LABEL: define dso_local void @_Z20Test_Func_EnumInt32T10EnumInt32T( +// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG502:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META506:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META507:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG508:![0-9]+]] +// +__device__ void Test_Func_EnumInt32T(EnumInt32T) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z20Test_Kern_EnumInt32T10EnumInt32T( +// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG509:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META511:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META512:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG513:![0-9]+]] +// +__global__ void Test_Kern_EnumInt32T(EnumInt32T) {} +// CHECK-LABEL: define dso_local void @_Z21Test_Func_EnumUInt32T11EnumUInt32T( +// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG514:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META518:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META519:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG520:![0-9]+]] +// +__device__ void Test_Func_EnumUInt32T(EnumUInt32T) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z21Test_Kern_EnumUInt32T11EnumUInt32T( +// CHECK-SAME: i32 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG521:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META523:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META524:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG525:![0-9]+]] +// +__global__ void Test_Kern_EnumUInt32T(EnumUInt32T) {} +// CHECK-LABEL: define dso_local void @_Z20Test_Func_EnumInt64T10EnumInt64T( +// CHECK-SAME: i64 noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG526:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META530:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META531:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG532:![0-9]+]] +// +__device__ void Test_Func_EnumInt64T(EnumInt64T) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z20Test_Kern_EnumInt64T10EnumInt64T( +// CHECK-SAME: i64 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG533:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META535:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META536:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG537:![0-9]+]] +// +__global__ void Test_Kern_EnumInt64T(EnumInt64T) {} +// CHECK-LABEL: define dso_local void @_Z21Test_Func_EnumUInt64T11EnumUInt64T( +// CHECK-SAME: i64 noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG538:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META542:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META543:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG544:![0-9]+]] +// +__device__ void Test_Func_EnumUInt64T(EnumUInt64T) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z21Test_Kern_EnumUInt64T11EnumUInt64T( +// CHECK-SAME: i64 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG545:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META547:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META548:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG549:![0-9]+]] +// +__global__ void Test_Kern_EnumUInt64T(EnumUInt64T) {} +// CHECK-LABEL: define dso_local void @_Z27Test_Func_PromotableIntegerb( +// CHECK-SAME: i1 noundef zeroext [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG550:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8, align 1, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[TMP0]] to i8 +// CHECK-NEXT: store i8 [[STOREDV]], ptr [[DOTADDR_ASCAST]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META555:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i8)), [[META556:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG557:![0-9]+]] +// +__device__ void Test_Func_PromotableInteger(bool) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z27Test_Kern_PromotableIntegerb( +// CHECK-SAME: i1 noundef [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG558:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i8, align 1, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[TMP0]] to i8 +// CHECK-NEXT: store i8 [[STOREDV]], ptr [[DOTADDR_ASCAST]], align 1 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META560:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i8)), [[META561:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG562:![0-9]+]] +// +__global__ void Test_Kern_PromotableInteger(bool) {} +// CHECK-LABEL: define dso_local void @_Z17Test_Func_PointerPi( +// CHECK-SAME: ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG563:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META568:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr)), [[META569:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG570:![0-9]+]] +// +__device__ void Test_Func_Pointer(int32_t *) {} +// FIXME: There is a store, load, store sequence through another alloca here, +// which I don't understand the intent of +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z17Test_Kern_PointerPi( +// CHECK-SAME: ptr addrspace(1) noundef [[DOTCOERCE:%.*]]) #[[ATTR1]] !dbg [[DBG571:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store ptr addrspace(1) [[DOTCOERCE]], ptr [[TMP1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META573:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr)), [[META574:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG575:![0-9]+]] +// +__global__ void Test_Kern_Pointer(int32_t *) {} +// CHECK-LABEL: define dso_local void @_Z19Test_Func_ReferenceRi( +// CHECK-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG576:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META581:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr)), [[META582:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG583:![0-9]+]] +// +__device__ void Test_Func_Reference(int32_t &) {} +// FIXME: There is a store, load, store sequence through another alloca here, +// which I don't understand the intent of +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z19Test_Kern_ReferenceRi( +// CHECK-SAME: ptr addrspace(1) noundef nonnull align 4 dereferenceable(4) [[DOTCOERCE:%.*]]) #[[ATTR1]] !dbg [[DBG584:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: store ptr addrspace(1) [[DOTCOERCE]], ptr [[TMP1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META586:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr)), [[META587:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG588:![0-9]+]] +// +__global__ void Test_Kern_Reference(int32_t &) {} +// CHECK-LABEL: define dso_local void @_Z36Test_Func_StructSinglePointerElement26StructSinglePointerElement( +// CHECK-SAME: ptr [[DOTCOERCE:%.*]]) #[[ATTR0]] !dbg [[DBG589:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTSINGLEPOINTERELEMENT:%.*]], align 8, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTSINGLEPOINTERELEMENT]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META596:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTSINGLEPOINTERELEMENT]])), [[META597:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG598:![0-9]+]] +// +__device__ void Test_Func_StructSinglePointerElement(StructSinglePointerElement) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z36Test_Kern_StructSinglePointerElement26StructSinglePointerElement( +// CHECK-SAME: ptr addrspace(1) [[DOTCOERCE:%.*]]) #[[ATTR1]] !dbg [[DBG599:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTSINGLEPOINTERELEMENT:%.*]], align 8, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTSINGLEPOINTERELEMENT]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store ptr addrspace(1) [[DOTCOERCE]], ptr [[COERCE_DIVE]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META601:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTSINGLEPOINTERELEMENT]])), [[META602:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG603:![0-9]+]] +// +__global__ void Test_Kern_StructSinglePointerElement(StructSinglePointerElement) {} +// CHECK-LABEL: define dso_local void @_Z31Test_Func_StructPointerElements21StructPointerElements( +// CHECK-SAME: ptr [[DOTCOERCE0:%.*]], ptr [[DOTCOERCE1:%.*]]) #[[ATTR0]] !dbg [[DBG604:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_STRUCTPOINTERELEMENTS:%.*]], align 8, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTPOINTERELEMENTS]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[DOTCOERCE0]], ptr [[TMP2]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTPOINTERELEMENTS]], ptr [[TMP1]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[DOTCOERCE1]], ptr [[TMP3]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META614:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTPOINTERELEMENTS]])), [[META615:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG616:![0-9]+]] +// +__device__ void Test_Func_StructPointerElements(StructPointerElements) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z31Test_Kern_StructPointerElements21StructPointerElements( +// CHECK-SAME: ptr addrspace(4) noundef byref([[STRUCT_STRUCTPOINTERELEMENTS:%.*]]) align 8 [[TMP0:%.*]]) #[[ATTR1]] !dbg [[DBG617:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTPOINTERELEMENTS]], align 8, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 8 [[TMP1]], ptr addrspace(4) align 8 [[TMP0]], i64 16, i1 false) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META619:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTPOINTERELEMENTS]])), [[META620:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG621:![0-9]+]] +// +__global__ void Test_Kern_StructPointerElements(StructPointerElements) {} +// CHECK-LABEL: define dso_local void @_Z37Test_Func_ParamRegLimitExpandedStructlllllli22StructMultipleElements( +// CHECK-SAME: i64 noundef [[TMP0:%.*]], i64 noundef [[TMP1:%.*]], i64 noundef [[TMP2:%.*]], i64 noundef [[TMP3:%.*]], i64 noundef [[TMP4:%.*]], i64 noundef [[TMP5:%.*]], i32 noundef [[TMP6:%.*]], i32 [[DOTCOERCE0:%.*]], i64 [[DOTCOERCE1:%.*]]) #[[ATTR0]] !dbg [[DBG622:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP7:%.*]] = alloca [[STRUCT_STRUCTMULTIPLEELEMENTS:%.*]], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR6:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP8:%.*]] = addrspacecast ptr addrspace(5) [[TMP7]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[DOTADDR6_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR6]] to ptr +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTMULTIPLEELEMENTS]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: store i32 [[DOTCOERCE0]], ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_STRUCTMULTIPLEELEMENTS]], ptr [[TMP8]], i32 0, i32 1 +// CHECK-NEXT: store i64 [[DOTCOERCE1]], ptr [[TMP10]], align 8 +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META630:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META638:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR1]], [[META631:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META639:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR2]], [[META632:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META640:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR3]], [[META633:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META641:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP4]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR4]], [[META634:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META642:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP5]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR5]], [[META635:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META643:![0-9]+]]) +// CHECK-NEXT: store i32 [[TMP6]], ptr [[DOTADDR6_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR6]], [[META636:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META644:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP7]], [[META637:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTMULTIPLEELEMENTS]])), [[META645:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG646:![0-9]+]] +// +__device__ void Test_Func_ParamRegLimitExpandedStruct(int64_t, int64_t, int64_t, int64_t, int64_t, int64_t, int32_t, StructMultipleElements) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z37Test_Kern_ParamRegLimitExpandedStructlllllli22StructMultipleElements( +// CHECK-SAME: i64 noundef [[TMP0:%.*]], i64 noundef [[TMP1:%.*]], i64 noundef [[TMP2:%.*]], i64 noundef [[TMP3:%.*]], i64 noundef [[TMP4:%.*]], i64 noundef [[TMP5:%.*]], i32 noundef [[TMP6:%.*]], ptr addrspace(4) noundef byref([[STRUCT_STRUCTMULTIPLEELEMENTS:%.*]]) align 8 [[TMP7:%.*]]) #[[ATTR1]] !dbg [[DBG647:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTMULTIPLEELEMENTS]], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR6:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP8:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[DOTADDR6_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR6]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 8 [[TMP8]], ptr addrspace(4) align 8 [[TMP7]], i64 16, i1 false) +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META649:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META657:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR1]], [[META650:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META658:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR2]], [[META651:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META659:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR3]], [[META652:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META660:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP4]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR4]], [[META653:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META661:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP5]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR5]], [[META654:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META662:![0-9]+]]) +// CHECK-NEXT: store i32 [[TMP6]], ptr [[DOTADDR6_ASCAST]], align 4 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR6]], [[META655:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META663:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META656:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTMULTIPLEELEMENTS]])), [[META664:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG665:![0-9]+]] +// +__global__ void Test_Kern_ParamRegLimitExpandedStruct(int64_t, int64_t, int64_t, int64_t, int64_t, int64_t, int32_t, StructMultipleElements) {} +// CHECK-LABEL: define dso_local void @_Z39Test_Func_ParamRegLimitUnexpandedStructlllllll22StructMultipleElements( +// CHECK-SAME: i64 noundef [[TMP0:%.*]], i64 noundef [[TMP1:%.*]], i64 noundef [[TMP2:%.*]], i64 noundef [[TMP3:%.*]], i64 noundef [[TMP4:%.*]], i64 noundef [[TMP5:%.*]], i64 noundef [[TMP6:%.*]], ptr addrspace(5) noundef byref([[STRUCT_STRUCTMULTIPLEELEMENTS:%.*]]) align 8 [[TMP7:%.*]]) #[[ATTR0]] !dbg [[DBG666:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTMULTIPLEELEMENTS]], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR6:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[TMP8:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[DOTADDR6_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR6]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p5.i64(ptr align 8 [[TMP8]], ptr addrspace(5) align 8 [[TMP7]], i64 16, i1 false) +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META670:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META678:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR1]], [[META671:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META679:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR2]], [[META672:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META680:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR3]], [[META673:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META681:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP4]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR4]], [[META674:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META682:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP5]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR5]], [[META675:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META683:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP6]], ptr [[DOTADDR6_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR6]], [[META676:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META684:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META677:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTMULTIPLEELEMENTS]])), [[META685:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG686:![0-9]+]] +// +__device__ void Test_Func_ParamRegLimitUnexpandedStruct(int64_t, int64_t, int64_t, int64_t, int64_t, int64_t, int64_t, StructMultipleElements) {} +// CHECK-LABEL: define dso_local amdgpu_kernel void @_Z39Test_Kern_ParamRegLimitUnexpandedStructlllllll22StructMultipleElements( +// CHECK-SAME: i64 noundef [[TMP0:%.*]], i64 noundef [[TMP1:%.*]], i64 noundef [[TMP2:%.*]], i64 noundef [[TMP3:%.*]], i64 noundef [[TMP4:%.*]], i64 noundef [[TMP5:%.*]], i64 noundef [[TMP6:%.*]], ptr addrspace(4) noundef byref([[STRUCT_STRUCTMULTIPLEELEMENTS:%.*]]) align 8 [[TMP7:%.*]]) #[[ATTR1]] !dbg [[DBG687:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[COERCE:%.*]] = alloca [[STRUCT_STRUCTMULTIPLEELEMENTS]], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR6:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[TMP8:%.*]] = addrspacecast ptr addrspace(5) [[COERCE]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[DOTADDR6_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR6]] to ptr +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 8 [[TMP8]], ptr addrspace(4) align 8 [[TMP7]], i64 16, i1 false) +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR]], [[META689:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META697:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR1]], [[META690:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META698:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR2]], [[META691:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META699:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR3]], [[META692:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META700:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP4]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR4]], [[META693:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META701:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP5]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR5]], [[META694:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META702:![0-9]+]]) +// CHECK-NEXT: store i64 [[TMP6]], ptr [[DOTADDR6_ASCAST]], align 8 +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[DOTADDR6]], [[META695:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i64)), [[META703:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[COERCE]], [[META696:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_STRUCTMULTIPLEELEMENTS]])), [[META704:![0-9]+]]) +// CHECK-NEXT: ret void, !dbg [[DBG705:![0-9]+]] +// +__global__ void Test_Kern_ParamRegLimitUnexpandedStruct(int64_t, int64_t, int64_t, int64_t, int64_t, int64_t, int64_t, StructMultipleElements) {} +//. +// CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: [[META2:![0-9]+]], splitDebugInlining: false, nameTableKind: None) +// CHECK: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// CHECK: [[META2]] = !{[[META3:![0-9]+]], [[META7:![0-9]+]], [[META9:![0-9]+]], [[META11:![0-9]+]], [[META13:![0-9]+]], [[META15:![0-9]+]], [[META17:![0-9]+]], [[META19:![0-9]+]]} +// CHECK: [[META3]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "EnumInt8T", file: [[META4:![0-9]+]], line: 65, baseType: [[META5:![0-9]+]], size: 8, elements: [[META6:![0-9]+]], identifier: "_ZTS9EnumInt8T") +// CHECK: [[META4]] = !DIFile(filename: "{{.*}}debug-info-amdgcn-abi-heterogeneous-dwarf.hip", directory: {{.*}}) +// CHECK: [[META5]] = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) +// CHECK: [[META6]] = !{} +// CHECK: [[META7]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "EnumUInt8T", file: [[META4]], line: 66, baseType: [[META8:![0-9]+]], size: 8, elements: [[META6]], identifier: "_ZTS10EnumUInt8T") +// CHECK: [[META8]] = !DIBasicType(name: "unsigned char", size: 8, encoding: DW_ATE_unsigned_char) +// CHECK: [[META9]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "EnumInt16T", file: [[META4]], line: 67, baseType: [[META10:![0-9]+]], size: 16, elements: [[META6]], identifier: "_ZTS10EnumInt16T") +// CHECK: [[META10]] = !DIBasicType(name: "short", size: 16, encoding: DW_ATE_signed) +// CHECK: [[META11]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "EnumUInt16T", file: [[META4]], line: 68, baseType: [[META12:![0-9]+]], size: 16, elements: [[META6]], identifier: "_ZTS11EnumUInt16T") +// CHECK: [[META12]] = !DIBasicType(name: "unsigned short", size: 16, encoding: DW_ATE_unsigned) +// CHECK: [[META13]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "EnumInt32T", file: [[META4]], line: 69, baseType: [[META14:![0-9]+]], size: 32, elements: [[META6]], identifier: "_ZTS10EnumInt32T") +// CHECK: [[META14]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +// CHECK: [[META15]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "EnumUInt32T", file: [[META4]], line: 70, baseType: [[META16:![0-9]+]], size: 32, elements: [[META6]], identifier: "_ZTS11EnumUInt32T") +// CHECK: [[META16]] = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned) +// CHECK: [[META17]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "EnumInt64T", file: [[META4]], line: 71, baseType: [[META18:![0-9]+]], size: 64, elements: [[META6]], identifier: "_ZTS10EnumInt64T") +// CHECK: [[META18]] = !DIBasicType(name: "long", size: 64, encoding: DW_ATE_signed) +// CHECK: [[META19]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "EnumUInt64T", file: [[META4]], line: 72, baseType: [[META20:![0-9]+]], size: 64, elements: [[META6]], identifier: "_ZTS11EnumUInt64T") +// CHECK: [[META20]] = !DIBasicType(name: "unsigned long", size: 64, encoding: DW_ATE_unsigned) +// CHECK: [[DBG26]] = distinct !DISubprogram(name: "Test_Func_StructEmpty", linkageName: "_Z21Test_Func_StructEmpty11StructEmpty", scope: [[META4]], file: [[META4]], line: 93, type: [[META27:![0-9]+]], scopeLine: 93, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META30:![0-9]+]]) +// CHECK: [[META27]] = !DISubroutineType(types: [[META28:![0-9]+]]) +// CHECK: [[META28]] = !{null, [[META29:![0-9]+]]} +// CHECK: [[META29]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructEmpty", file: [[META4]], line: 32, size: 8, flags: DIFlagTypePassByValue, elements: [[META6]], identifier: "_ZTS11StructEmpty") +// CHECK: [[META30]] = !{[[META31]]} +// CHECK: [[META31]] = !DILocalVariable(arg: 1, scope: [[DBG26]], file: [[META4]], line: 93, type: [[META29]]) +// CHECK: [[META32]] = !DILocation(line: 93, column: 50, scope: [[DBG26]]) +// CHECK: [[DBG33]] = !DILocation(line: 93, column: 53, scope: [[DBG26]]) +// CHECK: [[DBG34]] = distinct !DISubprogram(name: "Test_Kern_StructEmpty", linkageName: "_Z21Test_Kern_StructEmpty11StructEmpty", scope: [[META4]], file: [[META4]], line: 103, type: [[META27]], scopeLine: 103, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META35:![0-9]+]]) +// CHECK: [[META35]] = !{[[META36]]} +// CHECK: [[META36]] = !DILocalVariable(arg: 1, scope: [[DBG34]], file: [[META4]], line: 103, type: [[META29]]) +// CHECK: [[META37]] = !DILocation(line: 103, column: 50, scope: [[DBG34]]) +// CHECK: [[DBG38]] = !DILocation(line: 103, column: 53, scope: [[DBG34]]) +// CHECK: [[DBG39]] = distinct !DISubprogram(name: "Test_Func_StructSingleElement", linkageName: "_Z29Test_Func_StructSingleElement19StructSingleElement", scope: [[META4]], file: [[META4]], line: 114, type: [[META40:![0-9]+]], scopeLine: 114, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META45:![0-9]+]]) +// CHECK: [[META40]] = !DISubroutineType(types: [[META41:![0-9]+]]) +// CHECK: [[META41]] = !{null, [[META42:![0-9]+]]} +// CHECK: [[META42]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructSingleElement", file: [[META4]], line: 33, size: 8, flags: DIFlagTypePassByValue, elements: [[META43:![0-9]+]], identifier: "_ZTS19StructSingleElement") +// CHECK: [[META43]] = !{[[META44:![0-9]+]]} +// CHECK: [[META44]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META42]], file: [[META4]], line: 34, baseType: [[META5]], size: 8) +// CHECK: [[META45]] = !{[[META46]]} +// CHECK: [[META46]] = !DILocalVariable(arg: 1, scope: [[DBG39]], file: [[META4]], line: 114, type: [[META42]]) +// CHECK: [[META47]] = !DILocation(line: 114, column: 66, scope: [[DBG39]]) +// CHECK: [[DBG48]] = !DILocation(line: 114, column: 69, scope: [[DBG39]]) +// CHECK: [[DBG49]] = distinct !DISubprogram(name: "Test_Kern_StructSingleElement", linkageName: "_Z29Test_Kern_StructSingleElement19StructSingleElement", scope: [[META4]], file: [[META4]], line: 125, type: [[META40]], scopeLine: 125, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META50:![0-9]+]]) +// CHECK: [[META50]] = !{[[META51]]} +// CHECK: [[META51]] = !DILocalVariable(arg: 1, scope: [[DBG49]], file: [[META4]], line: 125, type: [[META42]]) +// CHECK: [[META52]] = !DILocation(line: 125, column: 66, scope: [[DBG49]]) +// CHECK: [[DBG53]] = !DILocation(line: 125, column: 69, scope: [[DBG49]]) +// CHECK: [[DBG54]] = distinct !DISubprogram(name: "Test_Func_StructSingleElementRecursive", linkageName: "_Z38Test_Func_StructSingleElementRecursive28StructSingleElementRecursive", scope: [[META4]], file: [[META4]], line: 137, type: [[META55:![0-9]+]], scopeLine: 137, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META60:![0-9]+]]) +// CHECK: [[META55]] = !DISubroutineType(types: [[META56:![0-9]+]]) +// CHECK: [[META56]] = !{null, [[META57:![0-9]+]]} +// CHECK: [[META57]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructSingleElementRecursive", file: [[META4]], line: 36, size: 8, flags: DIFlagTypePassByValue, elements: [[META58:![0-9]+]], identifier: "_ZTS28StructSingleElementRecursive") +// CHECK: [[META58]] = !{[[META59:![0-9]+]]} +// CHECK: [[META59]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META57]], file: [[META4]], line: 37, baseType: [[META42]], size: 8) +// CHECK: [[META60]] = !{[[META61]]} +// CHECK: [[META61]] = !DILocalVariable(arg: 1, scope: [[DBG54]], file: [[META4]], line: 137, type: [[META57]]) +// CHECK: [[META62]] = !DILocation(line: 137, column: 84, scope: [[DBG54]]) +// CHECK: [[DBG63]] = !DILocation(line: 137, column: 87, scope: [[DBG54]]) +// CHECK: [[DBG64]] = distinct !DISubprogram(name: "Test_Kern_StructSingleElementRecursive", linkageName: "_Z38Test_Kern_StructSingleElementRecursive28StructSingleElementRecursive", scope: [[META4]], file: [[META4]], line: 149, type: [[META55]], scopeLine: 149, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META65:![0-9]+]]) +// CHECK: [[META65]] = !{[[META66]]} +// CHECK: [[META66]] = !DILocalVariable(arg: 1, scope: [[DBG64]], file: [[META4]], line: 149, type: [[META57]]) +// CHECK: [[META67]] = !DILocation(line: 149, column: 84, scope: [[DBG64]]) +// CHECK: [[DBG68]] = !DILocation(line: 149, column: 87, scope: [[DBG64]]) +// CHECK: [[DBG69]] = distinct !DISubprogram(name: "Test_Func_StructTrivialCopyTrivialMove", linkageName: "_Z38Test_Func_StructTrivialCopyTrivialMove28StructTrivialCopyTrivialMove", scope: [[META4]], file: [[META4]], line: 160, type: [[META70:![0-9]+]], scopeLine: 160, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META85:![0-9]+]]) +// CHECK: [[META70]] = !DISubroutineType(types: [[META71:![0-9]+]]) +// CHECK: [[META71]] = !{null, [[META72:![0-9]+]]} +// CHECK: [[META72]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructTrivialCopyTrivialMove", file: [[META4]], line: 39, size: 8, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: [[META73:![0-9]+]], identifier: "_ZTS28StructTrivialCopyTrivialMove") +// CHECK: [[META73]] = !{[[META74:![0-9]+]], [[META75:![0-9]+]], [[META81:![0-9]+]]} +// CHECK: [[META74]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META72]], file: [[META4]], line: 40, baseType: [[META5]], size: 8) +// CHECK: [[META75]] = !DISubprogram(name: "StructTrivialCopyTrivialMove", linkageName: "_ZN28StructTrivialCopyTrivialMoveC4ERKS_", scope: [[META72]], file: [[META4]], line: 41, type: [[META76:![0-9]+]], scopeLine: 41, flags: DIFlagPrototyped, spFlags: 0) +// CHECK: [[META76]] = !DISubroutineType(types: [[META77:![0-9]+]]) +// CHECK: [[META77]] = !{null, [[META78:![0-9]+]], [[META79:![0-9]+]]} +// CHECK: [[META78]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META72]], size: 64, flags: DIFlagArtificial | DIFlagObjectPointer, addressSpace: 1) +// CHECK: [[META79]] = !DIDerivedType(tag: DW_TAG_reference_type, baseType: [[META80:![0-9]+]], size: 64, addressSpace: 1) +// CHECK: [[META80]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META72]]) +// CHECK: [[META81]] = !DISubprogram(name: "StructTrivialCopyTrivialMove", linkageName: "_ZN28StructTrivialCopyTrivialMoveC4EOS_", scope: [[META72]], file: [[META4]], line: 42, type: [[META82:![0-9]+]], scopeLine: 42, flags: DIFlagPrototyped, spFlags: 0) +// CHECK: [[META82]] = !DISubroutineType(types: [[META83:![0-9]+]]) +// CHECK: [[META83]] = !{null, [[META78]], [[META84:![0-9]+]]} +// CHECK: [[META84]] = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: [[META72]], size: 64, addressSpace: 1) +// CHECK: [[META85]] = !{[[META86]]} +// CHECK: [[META86]] = !DILocalVariable(arg: 1, scope: [[DBG69]], file: [[META4]], line: 160, type: [[META72]]) +// CHECK: [[META87]] = !DILocation(line: 160, column: 84, scope: [[DBG69]]) +// CHECK: [[DBG88]] = !DILocation(line: 160, column: 87, scope: [[DBG69]]) +// CHECK: [[DBG89]] = distinct !DISubprogram(name: "Test_Kern_StructTrivialCopyTrivialMove", linkageName: "_Z38Test_Kern_StructTrivialCopyTrivialMove28StructTrivialCopyTrivialMove", scope: [[META4]], file: [[META4]], line: 171, type: [[META70]], scopeLine: 171, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META90:![0-9]+]]) +// CHECK: [[META90]] = !{[[META91]]} +// CHECK: [[META91]] = !DILocalVariable(arg: 1, scope: [[DBG89]], file: [[META4]], line: 171, type: [[META72]]) +// CHECK: [[META92]] = !DILocation(line: 171, column: 84, scope: [[DBG89]]) +// CHECK: [[DBG93]] = !DILocation(line: 171, column: 87, scope: [[DBG89]]) +// CHECK: [[DBG94]] = distinct !DISubprogram(name: "Test_Func_StructNoCopyTrivialMove", linkageName: "_Z33Test_Func_StructNoCopyTrivialMove23StructNoCopyTrivialMove", scope: [[META4]], file: [[META4]], line: 182, type: [[META95:![0-9]+]], scopeLine: 182, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META110:![0-9]+]]) +// CHECK: [[META95]] = !DISubroutineType(types: [[META96:![0-9]+]]) +// CHECK: [[META96]] = !{null, [[META97:![0-9]+]]} +// CHECK: [[META97]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNoCopyTrivialMove", file: [[META4]], line: 44, size: 8, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: [[META98:![0-9]+]], identifier: "_ZTS23StructNoCopyTrivialMove") +// CHECK: [[META98]] = !{[[META99:![0-9]+]], [[META100:![0-9]+]], [[META106:![0-9]+]]} +// CHECK: [[META99]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META97]], file: [[META4]], line: 45, baseType: [[META5]], size: 8) +// CHECK: [[META100]] = !DISubprogram(name: "StructNoCopyTrivialMove", linkageName: "_ZN23StructNoCopyTrivialMoveC4ERKS_", scope: [[META97]], file: [[META4]], line: 46, type: [[META101:![0-9]+]], scopeLine: 46, flags: DIFlagPrototyped, spFlags: DISPFlagDeleted) +// CHECK: [[META101]] = !DISubroutineType(types: [[META102:![0-9]+]]) +// CHECK: [[META102]] = !{null, [[META103:![0-9]+]], [[META104:![0-9]+]]} +// CHECK: [[META103]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META97]], size: 64, flags: DIFlagArtificial | DIFlagObjectPointer, addressSpace: 1) +// CHECK: [[META104]] = !DIDerivedType(tag: DW_TAG_reference_type, baseType: [[META105:![0-9]+]], size: 64, addressSpace: 1) +// CHECK: [[META105]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META97]]) +// CHECK: [[META106]] = !DISubprogram(name: "StructNoCopyTrivialMove", linkageName: "_ZN23StructNoCopyTrivialMoveC4EOS_", scope: [[META97]], file: [[META4]], line: 47, type: [[META107:![0-9]+]], scopeLine: 47, flags: DIFlagPrototyped, spFlags: 0) +// CHECK: [[META107]] = !DISubroutineType(types: [[META108:![0-9]+]]) +// CHECK: [[META108]] = !{null, [[META103]], [[META109:![0-9]+]]} +// CHECK: [[META109]] = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: [[META97]], size: 64, addressSpace: 1) +// CHECK: [[META110]] = !{[[META111]]} +// CHECK: [[META111]] = !DILocalVariable(arg: 1, scope: [[DBG94]], file: [[META4]], line: 182, type: [[META97]]) +// CHECK: [[META112]] = !DILocation(line: 182, column: 74, scope: [[DBG94]]) +// CHECK: [[DBG113]] = !DILocation(line: 182, column: 77, scope: [[DBG94]]) +// CHECK: [[DBG114]] = distinct !DISubprogram(name: "Test_Kern_StructNoCopyTrivialMove", linkageName: "_Z33Test_Kern_StructNoCopyTrivialMove23StructNoCopyTrivialMove", scope: [[META4]], file: [[META4]], line: 193, type: [[META95]], scopeLine: 193, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META115:![0-9]+]]) +// CHECK: [[META115]] = !{[[META116]]} +// CHECK: [[META116]] = !DILocalVariable(arg: 1, scope: [[DBG114]], file: [[META4]], line: 193, type: [[META97]]) +// CHECK: [[META117]] = !DILocation(line: 193, column: 74, scope: [[DBG114]]) +// CHECK: [[DBG118]] = !DILocation(line: 193, column: 77, scope: [[DBG114]]) +// CHECK: [[DBG119]] = distinct !DISubprogram(name: "Test_Func_StructTrivialCopyNoMove", linkageName: "_Z33Test_Func_StructTrivialCopyNoMove23StructTrivialCopyNoMove", scope: [[META4]], file: [[META4]], line: 204, type: [[META120:![0-9]+]], scopeLine: 204, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META135:![0-9]+]]) +// CHECK: [[META120]] = !DISubroutineType(types: [[META121:![0-9]+]]) +// CHECK: [[META121]] = !{null, [[META122:![0-9]+]]} +// CHECK: [[META122]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructTrivialCopyNoMove", file: [[META4]], line: 49, size: 8, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: [[META123:![0-9]+]], identifier: "_ZTS23StructTrivialCopyNoMove") +// CHECK: [[META123]] = !{[[META124:![0-9]+]], [[META125:![0-9]+]], [[META131:![0-9]+]]} +// CHECK: [[META124]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META122]], file: [[META4]], line: 50, baseType: [[META5]], size: 8) +// CHECK: [[META125]] = !DISubprogram(name: "StructTrivialCopyNoMove", linkageName: "_ZN23StructTrivialCopyNoMoveC4ERKS_", scope: [[META122]], file: [[META4]], line: 51, type: [[META126:![0-9]+]], scopeLine: 51, flags: DIFlagPrototyped, spFlags: 0) +// CHECK: [[META126]] = !DISubroutineType(types: [[META127:![0-9]+]]) +// CHECK: [[META127]] = !{null, [[META128:![0-9]+]], [[META129:![0-9]+]]} +// CHECK: [[META128]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META122]], size: 64, flags: DIFlagArtificial | DIFlagObjectPointer, addressSpace: 1) +// CHECK: [[META129]] = !DIDerivedType(tag: DW_TAG_reference_type, baseType: [[META130:![0-9]+]], size: 64, addressSpace: 1) +// CHECK: [[META130]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META122]]) +// CHECK: [[META131]] = !DISubprogram(name: "StructTrivialCopyNoMove", linkageName: "_ZN23StructTrivialCopyNoMoveC4EOS_", scope: [[META122]], file: [[META4]], line: 52, type: [[META132:![0-9]+]], scopeLine: 52, flags: DIFlagPrototyped, spFlags: DISPFlagDeleted) +// CHECK: [[META132]] = !DISubroutineType(types: [[META133:![0-9]+]]) +// CHECK: [[META133]] = !{null, [[META128]], [[META134:![0-9]+]]} +// CHECK: [[META134]] = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: [[META122]], size: 64, addressSpace: 1) +// CHECK: [[META135]] = !{[[META136]]} +// CHECK: [[META136]] = !DILocalVariable(arg: 1, scope: [[DBG119]], file: [[META4]], line: 204, type: [[META122]]) +// CHECK: [[META137]] = !DILocation(line: 204, column: 74, scope: [[DBG119]]) +// CHECK: [[DBG138]] = !DILocation(line: 204, column: 77, scope: [[DBG119]]) +// CHECK: [[DBG139]] = distinct !DISubprogram(name: "Test_Kern_StructTrivialCopyNoMove", linkageName: "_Z33Test_Kern_StructTrivialCopyNoMove23StructTrivialCopyNoMove", scope: [[META4]], file: [[META4]], line: 215, type: [[META120]], scopeLine: 215, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META140:![0-9]+]]) +// CHECK: [[META140]] = !{[[META141]]} +// CHECK: [[META141]] = !DILocalVariable(arg: 1, scope: [[DBG139]], file: [[META4]], line: 215, type: [[META122]]) +// CHECK: [[META142]] = !DILocation(line: 215, column: 74, scope: [[DBG139]]) +// CHECK: [[DBG143]] = !DILocation(line: 215, column: 77, scope: [[DBG139]]) +// CHECK: [[DBG144]] = distinct !DISubprogram(name: "Test_Func_StructNoCopyNoMove", linkageName: "_Z28Test_Func_StructNoCopyNoMove18StructNoCopyNoMove", scope: [[META4]], file: [[META4]], line: 226, type: [[META145:![0-9]+]], scopeLine: 226, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META160:![0-9]+]]) +// CHECK: [[META145]] = !DISubroutineType(types: [[META146:![0-9]+]]) +// CHECK: [[META146]] = !{null, [[META147:![0-9]+]]} +// CHECK: [[META147]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNoCopyNoMove", file: [[META4]], line: 54, size: 8, flags: DIFlagTypePassByReference | DIFlagNonTrivial, elements: [[META148:![0-9]+]], identifier: "_ZTS18StructNoCopyNoMove") +// CHECK: [[META148]] = !{[[META149:![0-9]+]], [[META150:![0-9]+]], [[META156:![0-9]+]]} +// CHECK: [[META149]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META147]], file: [[META4]], line: 55, baseType: [[META5]], size: 8) +// CHECK: [[META150]] = !DISubprogram(name: "StructNoCopyNoMove", linkageName: "_ZN18StructNoCopyNoMoveC4ERKS_", scope: [[META147]], file: [[META4]], line: 56, type: [[META151:![0-9]+]], scopeLine: 56, flags: DIFlagPrototyped, spFlags: DISPFlagDeleted) +// CHECK: [[META151]] = !DISubroutineType(types: [[META152:![0-9]+]]) +// CHECK: [[META152]] = !{null, [[META153:![0-9]+]], [[META154:![0-9]+]]} +// CHECK: [[META153]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META147]], size: 64, flags: DIFlagArtificial | DIFlagObjectPointer, addressSpace: 1) +// CHECK: [[META154]] = !DIDerivedType(tag: DW_TAG_reference_type, baseType: [[META155:![0-9]+]], size: 64, addressSpace: 1) +// CHECK: [[META155]] = !DIDerivedType(tag: DW_TAG_const_type, baseType: [[META147]]) +// CHECK: [[META156]] = !DISubprogram(name: "StructNoCopyNoMove", linkageName: "_ZN18StructNoCopyNoMoveC4EOS_", scope: [[META147]], file: [[META4]], line: 57, type: [[META157:![0-9]+]], scopeLine: 57, flags: DIFlagPrototyped, spFlags: DISPFlagDeleted) +// CHECK: [[META157]] = !DISubroutineType(types: [[META158:![0-9]+]]) +// CHECK: [[META158]] = !{null, [[META153]], [[META159:![0-9]+]]} +// CHECK: [[META159]] = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: [[META147]], size: 64, addressSpace: 1) +// CHECK: [[META160]] = !{[[META161]]} +// CHECK: [[META161]] = !DILocalVariable(arg: 1, scope: [[DBG144]], file: [[META4]], line: 226, type: [[META147]]) +// CHECK: [[META162]] = !DILocation(line: 226, column: 64, scope: [[DBG144]]) +// CHECK: [[DBG163]] = !DILocation(line: 226, column: 67, scope: [[DBG144]]) +// CHECK: [[DBG164]] = distinct !DISubprogram(name: "Test_Kern_StructNoCopyNoMove", linkageName: "_Z28Test_Kern_StructNoCopyNoMove18StructNoCopyNoMove", scope: [[META4]], file: [[META4]], line: 237, type: [[META145]], scopeLine: 237, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META165:![0-9]+]]) +// CHECK: [[META165]] = !{[[META166]]} +// CHECK: [[META166]] = !DILocalVariable(arg: 1, scope: [[DBG164]], file: [[META4]], line: 237, type: [[META147]]) +// CHECK: [[META167]] = !DILocation(line: 237, column: 64, scope: [[DBG164]]) +// CHECK: [[DBG168]] = !DILocation(line: 237, column: 67, scope: [[DBG164]]) +// CHECK: [[DBG169]] = distinct !DISubprogram(name: "Test_Func_Struct2Bytes", linkageName: "_Z22Test_Func_Struct2Bytes12StructNBytesILj2EE", scope: [[META4]], file: [[META4]], line: 247, type: [[META170:![0-9]+]], scopeLine: 247, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META181:![0-9]+]]) +// CHECK: [[META170]] = !DISubroutineType(types: [[META171:![0-9]+]]) +// CHECK: [[META171]] = !{null, [[META172:![0-9]+]]} +// CHECK: [[META172]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNBytes<2U>", file: [[META4]], line: 60, size: 16, flags: DIFlagTypePassByValue, elements: [[META173:![0-9]+]], templateParams: [[META179:![0-9]+]], identifier: "_ZTS12StructNBytesILj2EE") +// CHECK: [[META173]] = !{[[META174:![0-9]+]], [[META175:![0-9]+]]} +// CHECK: [[META174]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META172]], file: [[META4]], line: 62, baseType: [[META5]], size: 8) +// CHECK: [[META175]] = !DIDerivedType(tag: DW_TAG_member, name: "Elements", scope: [[META172]], file: [[META4]], line: 63, baseType: [[META176:![0-9]+]], size: 8, offset: 8) +// CHECK: [[META176]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META5]], size: 8, elements: [[META177:![0-9]+]]) +// CHECK: [[META177]] = !{[[META178:![0-9]+]]} +// CHECK: [[META178]] = !DISubrange(count: 1) +// CHECK: [[META179]] = !{[[META180:![0-9]+]]} +// CHECK: [[META180]] = !DITemplateValueParameter(name: "N", type: [[META16]], value: i32 2) +// CHECK: [[META181]] = !{[[META182]]} +// CHECK: [[META182]] = !DILocalVariable(arg: 1, scope: [[DBG169]], file: [[META4]], line: 247, type: [[META172]]) +// CHECK: [[META183]] = !DILocation(line: 247, column: 55, scope: [[DBG169]]) +// CHECK: [[DBG184]] = !DILocation(line: 247, column: 58, scope: [[DBG169]]) +// CHECK: [[DBG185]] = distinct !DISubprogram(name: "Test_Kern_Struct2Bytes", linkageName: "_Z22Test_Kern_Struct2Bytes12StructNBytesILj2EE", scope: [[META4]], file: [[META4]], line: 257, type: [[META170]], scopeLine: 257, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META186:![0-9]+]]) +// CHECK: [[META186]] = !{[[META187]]} +// CHECK: [[META187]] = !DILocalVariable(arg: 1, scope: [[DBG185]], file: [[META4]], line: 257, type: [[META172]]) +// CHECK: [[META188]] = !DILocation(line: 257, column: 55, scope: [[DBG185]]) +// CHECK: [[DBG189]] = !DILocation(line: 257, column: 58, scope: [[DBG185]]) +// CHECK: [[DBG190]] = distinct !DISubprogram(name: "Test_Func_Struct3Bytes", linkageName: "_Z22Test_Func_Struct3Bytes12StructNBytesILj3EE", scope: [[META4]], file: [[META4]], line: 268, type: [[META191:![0-9]+]], scopeLine: 268, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META202:![0-9]+]]) +// CHECK: [[META191]] = !DISubroutineType(types: [[META192:![0-9]+]]) +// CHECK: [[META192]] = !{null, [[META193:![0-9]+]]} +// CHECK: [[META193]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNBytes<3U>", file: [[META4]], line: 60, size: 24, flags: DIFlagTypePassByValue, elements: [[META194:![0-9]+]], templateParams: [[META200:![0-9]+]], identifier: "_ZTS12StructNBytesILj3EE") +// CHECK: [[META194]] = !{[[META195:![0-9]+]], [[META196:![0-9]+]]} +// CHECK: [[META195]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META193]], file: [[META4]], line: 62, baseType: [[META5]], size: 8) +// CHECK: [[META196]] = !DIDerivedType(tag: DW_TAG_member, name: "Elements", scope: [[META193]], file: [[META4]], line: 63, baseType: [[META197:![0-9]+]], size: 16, offset: 8) +// CHECK: [[META197]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META5]], size: 16, elements: [[META198:![0-9]+]]) +// CHECK: [[META198]] = !{[[META199:![0-9]+]]} +// CHECK: [[META199]] = !DISubrange(count: 2) +// CHECK: [[META200]] = !{[[META201:![0-9]+]]} +// CHECK: [[META201]] = !DITemplateValueParameter(name: "N", type: [[META16]], value: i32 3) +// CHECK: [[META202]] = !{[[META203]]} +// CHECK: [[META203]] = !DILocalVariable(arg: 1, scope: [[DBG190]], file: [[META4]], line: 268, type: [[META193]]) +// CHECK: [[META204]] = !DILocation(line: 268, column: 55, scope: [[DBG190]]) +// CHECK: [[DBG205]] = !DILocation(line: 268, column: 58, scope: [[DBG190]]) +// CHECK: [[DBG206]] = distinct !DISubprogram(name: "Test_Kern_Struct3Bytes", linkageName: "_Z22Test_Kern_Struct3Bytes12StructNBytesILj3EE", scope: [[META4]], file: [[META4]], line: 278, type: [[META191]], scopeLine: 278, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META207:![0-9]+]]) +// CHECK: [[META207]] = !{[[META208]]} +// CHECK: [[META208]] = !DILocalVariable(arg: 1, scope: [[DBG206]], file: [[META4]], line: 278, type: [[META193]]) +// CHECK: [[META209]] = !DILocation(line: 278, column: 55, scope: [[DBG206]]) +// CHECK: [[DBG210]] = !DILocation(line: 278, column: 58, scope: [[DBG206]]) +// CHECK: [[DBG211]] = distinct !DISubprogram(name: "Test_Func_Struct4Bytes", linkageName: "_Z22Test_Func_Struct4Bytes12StructNBytesILj4EE", scope: [[META4]], file: [[META4]], line: 288, type: [[META212:![0-9]+]], scopeLine: 288, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META223:![0-9]+]]) +// CHECK: [[META212]] = !DISubroutineType(types: [[META213:![0-9]+]]) +// CHECK: [[META213]] = !{null, [[META214:![0-9]+]]} +// CHECK: [[META214]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNBytes<4U>", file: [[META4]], line: 60, size: 32, flags: DIFlagTypePassByValue, elements: [[META215:![0-9]+]], templateParams: [[META221:![0-9]+]], identifier: "_ZTS12StructNBytesILj4EE") +// CHECK: [[META215]] = !{[[META216:![0-9]+]], [[META217:![0-9]+]]} +// CHECK: [[META216]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META214]], file: [[META4]], line: 62, baseType: [[META5]], size: 8) +// CHECK: [[META217]] = !DIDerivedType(tag: DW_TAG_member, name: "Elements", scope: [[META214]], file: [[META4]], line: 63, baseType: [[META218:![0-9]+]], size: 24, offset: 8) +// CHECK: [[META218]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META5]], size: 24, elements: [[META219:![0-9]+]]) +// CHECK: [[META219]] = !{[[META220:![0-9]+]]} +// CHECK: [[META220]] = !DISubrange(count: 3) +// CHECK: [[META221]] = !{[[META222:![0-9]+]]} +// CHECK: [[META222]] = !DITemplateValueParameter(name: "N", type: [[META16]], value: i32 4) +// CHECK: [[META223]] = !{[[META224]]} +// CHECK: [[META224]] = !DILocalVariable(arg: 1, scope: [[DBG211]], file: [[META4]], line: 288, type: [[META214]]) +// CHECK: [[META225]] = !DILocation(line: 288, column: 55, scope: [[DBG211]]) +// CHECK: [[DBG226]] = !DILocation(line: 288, column: 58, scope: [[DBG211]]) +// CHECK: [[DBG227]] = distinct !DISubprogram(name: "Test_Kern_Struct4Bytes", linkageName: "_Z22Test_Kern_Struct4Bytes12StructNBytesILj4EE", scope: [[META4]], file: [[META4]], line: 298, type: [[META212]], scopeLine: 298, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META228:![0-9]+]]) +// CHECK: [[META228]] = !{[[META229]]} +// CHECK: [[META229]] = !DILocalVariable(arg: 1, scope: [[DBG227]], file: [[META4]], line: 298, type: [[META214]]) +// CHECK: [[META230]] = !DILocation(line: 298, column: 55, scope: [[DBG227]]) +// CHECK: [[DBG231]] = !DILocation(line: 298, column: 58, scope: [[DBG227]]) +// CHECK: [[DBG232]] = distinct !DISubprogram(name: "Test_Func_Struct5Bytes", linkageName: "_Z22Test_Func_Struct5Bytes12StructNBytesILj5EE", scope: [[META4]], file: [[META4]], line: 311, type: [[META233:![0-9]+]], scopeLine: 311, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META244:![0-9]+]]) +// CHECK: [[META233]] = !DISubroutineType(types: [[META234:![0-9]+]]) +// CHECK: [[META234]] = !{null, [[META235:![0-9]+]]} +// CHECK: [[META235]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNBytes<5U>", file: [[META4]], line: 60, size: 40, flags: DIFlagTypePassByValue, elements: [[META236:![0-9]+]], templateParams: [[META242:![0-9]+]], identifier: "_ZTS12StructNBytesILj5EE") +// CHECK: [[META236]] = !{[[META237:![0-9]+]], [[META238:![0-9]+]]} +// CHECK: [[META237]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META235]], file: [[META4]], line: 62, baseType: [[META5]], size: 8) +// CHECK: [[META238]] = !DIDerivedType(tag: DW_TAG_member, name: "Elements", scope: [[META235]], file: [[META4]], line: 63, baseType: [[META239:![0-9]+]], size: 32, offset: 8) +// CHECK: [[META239]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META5]], size: 32, elements: [[META240:![0-9]+]]) +// CHECK: [[META240]] = !{[[META241:![0-9]+]]} +// CHECK: [[META241]] = !DISubrange(count: 4) +// CHECK: [[META242]] = !{[[META243:![0-9]+]]} +// CHECK: [[META243]] = !DITemplateValueParameter(name: "N", type: [[META16]], value: i32 5) +// CHECK: [[META244]] = !{[[META245]]} +// CHECK: [[META245]] = !DILocalVariable(arg: 1, scope: [[DBG232]], file: [[META4]], line: 311, type: [[META235]]) +// CHECK: [[META246]] = !DILocation(line: 311, column: 55, scope: [[DBG232]]) +// CHECK: [[DBG247]] = !DILocation(line: 311, column: 58, scope: [[DBG232]]) +// CHECK: [[DBG248]] = distinct !DISubprogram(name: "Test_Kern_Struct5Bytes", linkageName: "_Z22Test_Kern_Struct5Bytes12StructNBytesILj5EE", scope: [[META4]], file: [[META4]], line: 321, type: [[META233]], scopeLine: 321, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META249:![0-9]+]]) +// CHECK: [[META249]] = !{[[META250]]} +// CHECK: [[META250]] = !DILocalVariable(arg: 1, scope: [[DBG248]], file: [[META4]], line: 321, type: [[META235]]) +// CHECK: [[META251]] = !DILocation(line: 321, column: 55, scope: [[DBG248]]) +// CHECK: [[DBG252]] = !DILocation(line: 321, column: 58, scope: [[DBG248]]) +// CHECK: [[DBG253]] = distinct !DISubprogram(name: "Test_Func_Struct6Bytes", linkageName: "_Z22Test_Func_Struct6Bytes12StructNBytesILj6EE", scope: [[META4]], file: [[META4]], line: 334, type: [[META254:![0-9]+]], scopeLine: 334, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META265:![0-9]+]]) +// CHECK: [[META254]] = !DISubroutineType(types: [[META255:![0-9]+]]) +// CHECK: [[META255]] = !{null, [[META256:![0-9]+]]} +// CHECK: [[META256]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNBytes<6U>", file: [[META4]], line: 60, size: 48, flags: DIFlagTypePassByValue, elements: [[META257:![0-9]+]], templateParams: [[META263:![0-9]+]], identifier: "_ZTS12StructNBytesILj6EE") +// CHECK: [[META257]] = !{[[META258:![0-9]+]], [[META259:![0-9]+]]} +// CHECK: [[META258]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META256]], file: [[META4]], line: 62, baseType: [[META5]], size: 8) +// CHECK: [[META259]] = !DIDerivedType(tag: DW_TAG_member, name: "Elements", scope: [[META256]], file: [[META4]], line: 63, baseType: [[META260:![0-9]+]], size: 40, offset: 8) +// CHECK: [[META260]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META5]], size: 40, elements: [[META261:![0-9]+]]) +// CHECK: [[META261]] = !{[[META262:![0-9]+]]} +// CHECK: [[META262]] = !DISubrange(count: 5) +// CHECK: [[META263]] = !{[[META264:![0-9]+]]} +// CHECK: [[META264]] = !DITemplateValueParameter(name: "N", type: [[META16]], value: i32 6) +// CHECK: [[META265]] = !{[[META266]]} +// CHECK: [[META266]] = !DILocalVariable(arg: 1, scope: [[DBG253]], file: [[META4]], line: 334, type: [[META256]]) +// CHECK: [[META267]] = !DILocation(line: 334, column: 55, scope: [[DBG253]]) +// CHECK: [[DBG268]] = !DILocation(line: 334, column: 58, scope: [[DBG253]]) +// CHECK: [[DBG269]] = distinct !DISubprogram(name: "Test_Kern_Struct6Bytes", linkageName: "_Z22Test_Kern_Struct6Bytes12StructNBytesILj6EE", scope: [[META4]], file: [[META4]], line: 344, type: [[META254]], scopeLine: 344, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META270:![0-9]+]]) +// CHECK: [[META270]] = !{[[META271]]} +// CHECK: [[META271]] = !DILocalVariable(arg: 1, scope: [[DBG269]], file: [[META4]], line: 344, type: [[META256]]) +// CHECK: [[META272]] = !DILocation(line: 344, column: 55, scope: [[DBG269]]) +// CHECK: [[DBG273]] = !DILocation(line: 344, column: 58, scope: [[DBG269]]) +// CHECK: [[DBG274]] = distinct !DISubprogram(name: "Test_Func_Struct7Bytes", linkageName: "_Z22Test_Func_Struct7Bytes12StructNBytesILj7EE", scope: [[META4]], file: [[META4]], line: 357, type: [[META275:![0-9]+]], scopeLine: 357, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META286:![0-9]+]]) +// CHECK: [[META275]] = !DISubroutineType(types: [[META276:![0-9]+]]) +// CHECK: [[META276]] = !{null, [[META277:![0-9]+]]} +// CHECK: [[META277]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNBytes<7U>", file: [[META4]], line: 60, size: 56, flags: DIFlagTypePassByValue, elements: [[META278:![0-9]+]], templateParams: [[META284:![0-9]+]], identifier: "_ZTS12StructNBytesILj7EE") +// CHECK: [[META278]] = !{[[META279:![0-9]+]], [[META280:![0-9]+]]} +// CHECK: [[META279]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META277]], file: [[META4]], line: 62, baseType: [[META5]], size: 8) +// CHECK: [[META280]] = !DIDerivedType(tag: DW_TAG_member, name: "Elements", scope: [[META277]], file: [[META4]], line: 63, baseType: [[META281:![0-9]+]], size: 48, offset: 8) +// CHECK: [[META281]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META5]], size: 48, elements: [[META282:![0-9]+]]) +// CHECK: [[META282]] = !{[[META283:![0-9]+]]} +// CHECK: [[META283]] = !DISubrange(count: 6) +// CHECK: [[META284]] = !{[[META285:![0-9]+]]} +// CHECK: [[META285]] = !DITemplateValueParameter(name: "N", type: [[META16]], value: i32 7) +// CHECK: [[META286]] = !{[[META287]]} +// CHECK: [[META287]] = !DILocalVariable(arg: 1, scope: [[DBG274]], file: [[META4]], line: 357, type: [[META277]]) +// CHECK: [[META288]] = !DILocation(line: 357, column: 55, scope: [[DBG274]]) +// CHECK: [[DBG289]] = !DILocation(line: 357, column: 58, scope: [[DBG274]]) +// CHECK: [[DBG290]] = distinct !DISubprogram(name: "Test_Kern_Struct7Bytes", linkageName: "_Z22Test_Kern_Struct7Bytes12StructNBytesILj7EE", scope: [[META4]], file: [[META4]], line: 367, type: [[META275]], scopeLine: 367, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META291:![0-9]+]]) +// CHECK: [[META291]] = !{[[META292]]} +// CHECK: [[META292]] = !DILocalVariable(arg: 1, scope: [[DBG290]], file: [[META4]], line: 367, type: [[META277]]) +// CHECK: [[META293]] = !DILocation(line: 367, column: 55, scope: [[DBG290]]) +// CHECK: [[DBG294]] = !DILocation(line: 367, column: 58, scope: [[DBG290]]) +// CHECK: [[DBG295]] = distinct !DISubprogram(name: "Test_Func_Struct8Bytes", linkageName: "_Z22Test_Func_Struct8Bytes12StructNBytesILj8EE", scope: [[META4]], file: [[META4]], line: 377, type: [[META296:![0-9]+]], scopeLine: 377, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META307:![0-9]+]]) +// CHECK: [[META296]] = !DISubroutineType(types: [[META297:![0-9]+]]) +// CHECK: [[META297]] = !{null, [[META298:![0-9]+]]} +// CHECK: [[META298]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNBytes<8U>", file: [[META4]], line: 60, size: 64, flags: DIFlagTypePassByValue, elements: [[META299:![0-9]+]], templateParams: [[META305:![0-9]+]], identifier: "_ZTS12StructNBytesILj8EE") +// CHECK: [[META299]] = !{[[META300:![0-9]+]], [[META301:![0-9]+]]} +// CHECK: [[META300]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META298]], file: [[META4]], line: 62, baseType: [[META5]], size: 8) +// CHECK: [[META301]] = !DIDerivedType(tag: DW_TAG_member, name: "Elements", scope: [[META298]], file: [[META4]], line: 63, baseType: [[META302:![0-9]+]], size: 56, offset: 8) +// CHECK: [[META302]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META5]], size: 56, elements: [[META303:![0-9]+]]) +// CHECK: [[META303]] = !{[[META304:![0-9]+]]} +// CHECK: [[META304]] = !DISubrange(count: 7) +// CHECK: [[META305]] = !{[[META306:![0-9]+]]} +// CHECK: [[META306]] = !DITemplateValueParameter(name: "N", type: [[META16]], value: i32 8) +// CHECK: [[META307]] = !{[[META308]]} +// CHECK: [[META308]] = !DILocalVariable(arg: 1, scope: [[DBG295]], file: [[META4]], line: 377, type: [[META298]]) +// CHECK: [[META309]] = !DILocation(line: 377, column: 55, scope: [[DBG295]]) +// CHECK: [[DBG310]] = !DILocation(line: 377, column: 58, scope: [[DBG295]]) +// CHECK: [[DBG311]] = distinct !DISubprogram(name: "Test_Kern_Struct8Bytes", linkageName: "_Z22Test_Kern_Struct8Bytes12StructNBytesILj8EE", scope: [[META4]], file: [[META4]], line: 387, type: [[META296]], scopeLine: 387, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META312:![0-9]+]]) +// CHECK: [[META312]] = !{[[META313]]} +// CHECK: [[META313]] = !DILocalVariable(arg: 1, scope: [[DBG311]], file: [[META4]], line: 387, type: [[META298]]) +// CHECK: [[META314]] = !DILocation(line: 387, column: 55, scope: [[DBG311]]) +// CHECK: [[DBG315]] = !DILocation(line: 387, column: 58, scope: [[DBG311]]) +// CHECK: [[DBG316]] = distinct !DISubprogram(name: "Test_Func_Struct9Bytes", linkageName: "_Z22Test_Func_Struct9Bytes12StructNBytesILj9EE", scope: [[META4]], file: [[META4]], line: 400, type: [[META317:![0-9]+]], scopeLine: 400, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META328:![0-9]+]]) +// CHECK: [[META317]] = !DISubroutineType(types: [[META318:![0-9]+]]) +// CHECK: [[META318]] = !{null, [[META319:![0-9]+]]} +// CHECK: [[META319]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNBytes<9U>", file: [[META4]], line: 60, size: 72, flags: DIFlagTypePassByValue, elements: [[META320:![0-9]+]], templateParams: [[META326:![0-9]+]], identifier: "_ZTS12StructNBytesILj9EE") +// CHECK: [[META320]] = !{[[META321:![0-9]+]], [[META322:![0-9]+]]} +// CHECK: [[META321]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META319]], file: [[META4]], line: 62, baseType: [[META5]], size: 8) +// CHECK: [[META322]] = !DIDerivedType(tag: DW_TAG_member, name: "Elements", scope: [[META319]], file: [[META4]], line: 63, baseType: [[META323:![0-9]+]], size: 64, offset: 8) +// CHECK: [[META323]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META5]], size: 64, elements: [[META324:![0-9]+]]) +// CHECK: [[META324]] = !{[[META325:![0-9]+]]} +// CHECK: [[META325]] = !DISubrange(count: 8) +// CHECK: [[META326]] = !{[[META327:![0-9]+]]} +// CHECK: [[META327]] = !DITemplateValueParameter(name: "N", type: [[META16]], value: i32 9) +// CHECK: [[META328]] = !{[[META329]]} +// CHECK: [[META329]] = !DILocalVariable(arg: 1, scope: [[DBG316]], file: [[META4]], line: 400, type: [[META319]]) +// CHECK: [[META330]] = !DILocation(line: 400, column: 55, scope: [[DBG316]]) +// CHECK: [[DBG331]] = !DILocation(line: 400, column: 58, scope: [[DBG316]]) +// CHECK: [[DBG332]] = distinct !DISubprogram(name: "Test_Kern_Struct9Bytes", linkageName: "_Z22Test_Kern_Struct9Bytes12StructNBytesILj9EE", scope: [[META4]], file: [[META4]], line: 410, type: [[META317]], scopeLine: 410, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META333:![0-9]+]]) +// CHECK: [[META333]] = !{[[META334]]} +// CHECK: [[META334]] = !DILocalVariable(arg: 1, scope: [[DBG332]], file: [[META4]], line: 410, type: [[META319]]) +// CHECK: [[META335]] = !DILocation(line: 410, column: 55, scope: [[DBG332]]) +// CHECK: [[DBG336]] = !DILocation(line: 410, column: 58, scope: [[DBG332]]) +// CHECK: [[DBG337]] = distinct !DISubprogram(name: "Test_Func_Struct64Bytes", linkageName: "_Z23Test_Func_Struct64Bytes12StructNBytesILj64EE", scope: [[META4]], file: [[META4]], line: 420, type: [[META338:![0-9]+]], scopeLine: 420, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META349:![0-9]+]]) +// CHECK: [[META338]] = !DISubroutineType(types: [[META339:![0-9]+]]) +// CHECK: [[META339]] = !{null, [[META340:![0-9]+]]} +// CHECK: [[META340]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructNBytes<64U>", file: [[META4]], line: 60, size: 512, flags: DIFlagTypePassByValue, elements: [[META341:![0-9]+]], templateParams: [[META347:![0-9]+]], identifier: "_ZTS12StructNBytesILj64EE") +// CHECK: [[META341]] = !{[[META342:![0-9]+]], [[META343:![0-9]+]]} +// CHECK: [[META342]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META340]], file: [[META4]], line: 62, baseType: [[META5]], size: 8) +// CHECK: [[META343]] = !DIDerivedType(tag: DW_TAG_member, name: "Elements", scope: [[META340]], file: [[META4]], line: 63, baseType: [[META344:![0-9]+]], size: 504, offset: 8) +// CHECK: [[META344]] = !DICompositeType(tag: DW_TAG_array_type, baseType: [[META5]], size: 504, elements: [[META345:![0-9]+]]) +// CHECK: [[META345]] = !{[[META346:![0-9]+]]} +// CHECK: [[META346]] = !DISubrange(count: 63) +// CHECK: [[META347]] = !{[[META348:![0-9]+]]} +// CHECK: [[META348]] = !DITemplateValueParameter(name: "N", type: [[META16]], value: i32 64) +// CHECK: [[META349]] = !{[[META350]]} +// CHECK: [[META350]] = !DILocalVariable(arg: 1, scope: [[DBG337]], file: [[META4]], line: 420, type: [[META340]]) +// CHECK: [[META351]] = !DILocation(line: 420, column: 57, scope: [[DBG337]]) +// CHECK: [[DBG352]] = !DILocation(line: 420, column: 60, scope: [[DBG337]]) +// CHECK: [[DBG353]] = distinct !DISubprogram(name: "Test_Kern_Struct64Bytes", linkageName: "_Z23Test_Kern_Struct64Bytes12StructNBytesILj64EE", scope: [[META4]], file: [[META4]], line: 430, type: [[META338]], scopeLine: 430, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META354:![0-9]+]]) +// CHECK: [[META354]] = !{[[META355]]} +// CHECK: [[META355]] = !DILocalVariable(arg: 1, scope: [[DBG353]], file: [[META4]], line: 430, type: [[META340]]) +// CHECK: [[META356]] = !DILocation(line: 430, column: 57, scope: [[DBG353]]) +// CHECK: [[DBG357]] = !DILocation(line: 430, column: 60, scope: [[DBG353]]) +// CHECK: [[DBG358]] = distinct !DISubprogram(name: "Test_Func_Int8T", linkageName: "_Z15Test_Func_Int8Tc", scope: [[META4]], file: [[META4]], line: 440, type: [[META359:![0-9]+]], scopeLine: 440, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META361:![0-9]+]]) +// CHECK: [[META359]] = !DISubroutineType(types: [[META360:![0-9]+]]) +// CHECK: [[META360]] = !{null, [[META5]]} +// CHECK: [[META361]] = !{[[META362]]} +// CHECK: [[META362]] = !DILocalVariable(arg: 1, scope: [[DBG358]], file: [[META4]], line: 440, type: [[META5]]) +// CHECK: [[META363]] = !DILocation(line: 440, column: 39, scope: [[DBG358]]) +// CHECK: [[DBG364]] = !DILocation(line: 440, column: 42, scope: [[DBG358]]) +// CHECK: [[DBG365]] = distinct !DISubprogram(name: "Test_Kern_Int8T", linkageName: "_Z15Test_Kern_Int8Tc", scope: [[META4]], file: [[META4]], line: 450, type: [[META359]], scopeLine: 450, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META366:![0-9]+]]) +// CHECK: [[META366]] = !{[[META367]]} +// CHECK: [[META367]] = !DILocalVariable(arg: 1, scope: [[DBG365]], file: [[META4]], line: 450, type: [[META5]]) +// CHECK: [[META368]] = !DILocation(line: 450, column: 39, scope: [[DBG365]]) +// CHECK: [[DBG369]] = !DILocation(line: 450, column: 42, scope: [[DBG365]]) +// CHECK: [[DBG370]] = distinct !DISubprogram(name: "Test_Func_UInt8T", linkageName: "_Z16Test_Func_UInt8Th", scope: [[META4]], file: [[META4]], line: 460, type: [[META371:![0-9]+]], scopeLine: 460, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META373:![0-9]+]]) +// CHECK: [[META371]] = !DISubroutineType(types: [[META372:![0-9]+]]) +// CHECK: [[META372]] = !{null, [[META8]]} +// CHECK: [[META373]] = !{[[META374]]} +// CHECK: [[META374]] = !DILocalVariable(arg: 1, scope: [[DBG370]], file: [[META4]], line: 460, type: [[META8]]) +// CHECK: [[META375]] = !DILocation(line: 460, column: 41, scope: [[DBG370]]) +// CHECK: [[DBG376]] = !DILocation(line: 460, column: 44, scope: [[DBG370]]) +// CHECK: [[DBG377]] = distinct !DISubprogram(name: "Test_Kern_UInt8T", linkageName: "_Z16Test_Kern_UInt8Th", scope: [[META4]], file: [[META4]], line: 470, type: [[META371]], scopeLine: 470, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META378:![0-9]+]]) +// CHECK: [[META378]] = !{[[META379]]} +// CHECK: [[META379]] = !DILocalVariable(arg: 1, scope: [[DBG377]], file: [[META4]], line: 470, type: [[META8]]) +// CHECK: [[META380]] = !DILocation(line: 470, column: 41, scope: [[DBG377]]) +// CHECK: [[DBG381]] = !DILocation(line: 470, column: 44, scope: [[DBG377]]) +// CHECK: [[DBG382]] = distinct !DISubprogram(name: "Test_Func_Int16T", linkageName: "_Z16Test_Func_Int16Ts", scope: [[META4]], file: [[META4]], line: 480, type: [[META383:![0-9]+]], scopeLine: 480, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META385:![0-9]+]]) +// CHECK: [[META383]] = !DISubroutineType(types: [[META384:![0-9]+]]) +// CHECK: [[META384]] = !{null, [[META10]]} +// CHECK: [[META385]] = !{[[META386]]} +// CHECK: [[META386]] = !DILocalVariable(arg: 1, scope: [[DBG382]], file: [[META4]], line: 480, type: [[META10]]) +// CHECK: [[META387]] = !DILocation(line: 480, column: 41, scope: [[DBG382]]) +// CHECK: [[DBG388]] = !DILocation(line: 480, column: 44, scope: [[DBG382]]) +// CHECK: [[DBG389]] = distinct !DISubprogram(name: "Test_Kern_Int16T", linkageName: "_Z16Test_Kern_Int16Ts", scope: [[META4]], file: [[META4]], line: 490, type: [[META383]], scopeLine: 490, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META390:![0-9]+]]) +// CHECK: [[META390]] = !{[[META391]]} +// CHECK: [[META391]] = !DILocalVariable(arg: 1, scope: [[DBG389]], file: [[META4]], line: 490, type: [[META10]]) +// CHECK: [[META392]] = !DILocation(line: 490, column: 41, scope: [[DBG389]]) +// CHECK: [[DBG393]] = !DILocation(line: 490, column: 44, scope: [[DBG389]]) +// CHECK: [[DBG394]] = distinct !DISubprogram(name: "Test_Func_UInt16T", linkageName: "_Z17Test_Func_UInt16Tt", scope: [[META4]], file: [[META4]], line: 500, type: [[META395:![0-9]+]], scopeLine: 500, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META397:![0-9]+]]) +// CHECK: [[META395]] = !DISubroutineType(types: [[META396:![0-9]+]]) +// CHECK: [[META396]] = !{null, [[META12]]} +// CHECK: [[META397]] = !{[[META398]]} +// CHECK: [[META398]] = !DILocalVariable(arg: 1, scope: [[DBG394]], file: [[META4]], line: 500, type: [[META12]]) +// CHECK: [[META399]] = !DILocation(line: 500, column: 43, scope: [[DBG394]]) +// CHECK: [[DBG400]] = !DILocation(line: 500, column: 46, scope: [[DBG394]]) +// CHECK: [[DBG401]] = distinct !DISubprogram(name: "Test_Kern_UInt16T", linkageName: "_Z17Test_Kern_UInt16Tt", scope: [[META4]], file: [[META4]], line: 510, type: [[META395]], scopeLine: 510, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META402:![0-9]+]]) +// CHECK: [[META402]] = !{[[META403]]} +// CHECK: [[META403]] = !DILocalVariable(arg: 1, scope: [[DBG401]], file: [[META4]], line: 510, type: [[META12]]) +// CHECK: [[META404]] = !DILocation(line: 510, column: 43, scope: [[DBG401]]) +// CHECK: [[DBG405]] = !DILocation(line: 510, column: 46, scope: [[DBG401]]) +// CHECK: [[DBG406]] = distinct !DISubprogram(name: "Test_Func_Int32T", linkageName: "_Z16Test_Func_Int32Ti", scope: [[META4]], file: [[META4]], line: 520, type: [[META407:![0-9]+]], scopeLine: 520, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META409:![0-9]+]]) +// CHECK: [[META407]] = !DISubroutineType(types: [[META408:![0-9]+]]) +// CHECK: [[META408]] = !{null, [[META14]]} +// CHECK: [[META409]] = !{[[META410]]} +// CHECK: [[META410]] = !DILocalVariable(arg: 1, scope: [[DBG406]], file: [[META4]], line: 520, type: [[META14]]) +// CHECK: [[META411]] = !DILocation(line: 520, column: 41, scope: [[DBG406]]) +// CHECK: [[DBG412]] = !DILocation(line: 520, column: 44, scope: [[DBG406]]) +// CHECK: [[DBG413]] = distinct !DISubprogram(name: "Test_Kern_Int32T", linkageName: "_Z16Test_Kern_Int32Ti", scope: [[META4]], file: [[META4]], line: 530, type: [[META407]], scopeLine: 530, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META414:![0-9]+]]) +// CHECK: [[META414]] = !{[[META415]]} +// CHECK: [[META415]] = !DILocalVariable(arg: 1, scope: [[DBG413]], file: [[META4]], line: 530, type: [[META14]]) +// CHECK: [[META416]] = !DILocation(line: 530, column: 41, scope: [[DBG413]]) +// CHECK: [[DBG417]] = !DILocation(line: 530, column: 44, scope: [[DBG413]]) +// CHECK: [[DBG418]] = distinct !DISubprogram(name: "Test_Func_UInt32T", linkageName: "_Z17Test_Func_UInt32Tj", scope: [[META4]], file: [[META4]], line: 540, type: [[META419:![0-9]+]], scopeLine: 540, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META421:![0-9]+]]) +// CHECK: [[META419]] = !DISubroutineType(types: [[META420:![0-9]+]]) +// CHECK: [[META420]] = !{null, [[META16]]} +// CHECK: [[META421]] = !{[[META422]]} +// CHECK: [[META422]] = !DILocalVariable(arg: 1, scope: [[DBG418]], file: [[META4]], line: 540, type: [[META16]]) +// CHECK: [[META423]] = !DILocation(line: 540, column: 43, scope: [[DBG418]]) +// CHECK: [[DBG424]] = !DILocation(line: 540, column: 46, scope: [[DBG418]]) +// CHECK: [[DBG425]] = distinct !DISubprogram(name: "Test_Kern_UInt32T", linkageName: "_Z17Test_Kern_UInt32Tj", scope: [[META4]], file: [[META4]], line: 550, type: [[META419]], scopeLine: 550, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META426:![0-9]+]]) +// CHECK: [[META426]] = !{[[META427]]} +// CHECK: [[META427]] = !DILocalVariable(arg: 1, scope: [[DBG425]], file: [[META4]], line: 550, type: [[META16]]) +// CHECK: [[META428]] = !DILocation(line: 550, column: 43, scope: [[DBG425]]) +// CHECK: [[DBG429]] = !DILocation(line: 550, column: 46, scope: [[DBG425]]) +// CHECK: [[DBG430]] = distinct !DISubprogram(name: "Test_Func_Int64T", linkageName: "_Z16Test_Func_Int64Tl", scope: [[META4]], file: [[META4]], line: 560, type: [[META431:![0-9]+]], scopeLine: 560, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META433:![0-9]+]]) +// CHECK: [[META431]] = !DISubroutineType(types: [[META432:![0-9]+]]) +// CHECK: [[META432]] = !{null, [[META18]]} +// CHECK: [[META433]] = !{[[META434]]} +// CHECK: [[META434]] = !DILocalVariable(arg: 1, scope: [[DBG430]], file: [[META4]], line: 560, type: [[META18]]) +// CHECK: [[META435]] = !DILocation(line: 560, column: 41, scope: [[DBG430]]) +// CHECK: [[DBG436]] = !DILocation(line: 560, column: 44, scope: [[DBG430]]) +// CHECK: [[DBG437]] = distinct !DISubprogram(name: "Test_Kern_Int64T", linkageName: "_Z16Test_Kern_Int64Tl", scope: [[META4]], file: [[META4]], line: 570, type: [[META431]], scopeLine: 570, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META438:![0-9]+]]) +// CHECK: [[META438]] = !{[[META439]]} +// CHECK: [[META439]] = !DILocalVariable(arg: 1, scope: [[DBG437]], file: [[META4]], line: 570, type: [[META18]]) +// CHECK: [[META440]] = !DILocation(line: 570, column: 41, scope: [[DBG437]]) +// CHECK: [[DBG441]] = !DILocation(line: 570, column: 44, scope: [[DBG437]]) +// CHECK: [[DBG442]] = distinct !DISubprogram(name: "Test_Func_UInt64T", linkageName: "_Z17Test_Func_UInt64Tm", scope: [[META4]], file: [[META4]], line: 580, type: [[META443:![0-9]+]], scopeLine: 580, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META445:![0-9]+]]) +// CHECK: [[META443]] = !DISubroutineType(types: [[META444:![0-9]+]]) +// CHECK: [[META444]] = !{null, [[META20]]} +// CHECK: [[META445]] = !{[[META446]]} +// CHECK: [[META446]] = !DILocalVariable(arg: 1, scope: [[DBG442]], file: [[META4]], line: 580, type: [[META20]]) +// CHECK: [[META447]] = !DILocation(line: 580, column: 43, scope: [[DBG442]]) +// CHECK: [[DBG448]] = !DILocation(line: 580, column: 46, scope: [[DBG442]]) +// CHECK: [[DBG449]] = distinct !DISubprogram(name: "Test_Kern_UInt64T", linkageName: "_Z17Test_Kern_UInt64Tm", scope: [[META4]], file: [[META4]], line: 590, type: [[META443]], scopeLine: 590, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META450:![0-9]+]]) +// CHECK: [[META450]] = !{[[META451]]} +// CHECK: [[META451]] = !DILocalVariable(arg: 1, scope: [[DBG449]], file: [[META4]], line: 590, type: [[META20]]) +// CHECK: [[META452]] = !DILocation(line: 590, column: 43, scope: [[DBG449]]) +// CHECK: [[DBG453]] = !DILocation(line: 590, column: 46, scope: [[DBG449]]) +// CHECK: [[DBG454]] = distinct !DISubprogram(name: "Test_Func_EnumInt8T", linkageName: "_Z19Test_Func_EnumInt8T9EnumInt8T", scope: [[META4]], file: [[META4]], line: 600, type: [[META455:![0-9]+]], scopeLine: 600, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META457:![0-9]+]]) +// CHECK: [[META455]] = !DISubroutineType(types: [[META456:![0-9]+]]) +// CHECK: [[META456]] = !{null, [[META3]]} +// CHECK: [[META457]] = !{[[META458]]} +// CHECK: [[META458]] = !DILocalVariable(arg: 1, scope: [[DBG454]], file: [[META4]], line: 600, type: [[META3]]) +// CHECK: [[META459]] = !DILocation(line: 600, column: 46, scope: [[DBG454]]) +// CHECK: [[DBG460]] = !DILocation(line: 600, column: 49, scope: [[DBG454]]) +// CHECK: [[DBG461]] = distinct !DISubprogram(name: "Test_Kern_EnumInt8T", linkageName: "_Z19Test_Kern_EnumInt8T9EnumInt8T", scope: [[META4]], file: [[META4]], line: 610, type: [[META455]], scopeLine: 610, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META462:![0-9]+]]) +// CHECK: [[META462]] = !{[[META463]]} +// CHECK: [[META463]] = !DILocalVariable(arg: 1, scope: [[DBG461]], file: [[META4]], line: 610, type: [[META3]]) +// CHECK: [[META464]] = !DILocation(line: 610, column: 46, scope: [[DBG461]]) +// CHECK: [[DBG465]] = !DILocation(line: 610, column: 49, scope: [[DBG461]]) +// CHECK: [[DBG466]] = distinct !DISubprogram(name: "Test_Func_EnumUInt8T", linkageName: "_Z20Test_Func_EnumUInt8T10EnumUInt8T", scope: [[META4]], file: [[META4]], line: 620, type: [[META467:![0-9]+]], scopeLine: 620, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META469:![0-9]+]]) +// CHECK: [[META467]] = !DISubroutineType(types: [[META468:![0-9]+]]) +// CHECK: [[META468]] = !{null, [[META7]]} +// CHECK: [[META469]] = !{[[META470]]} +// CHECK: [[META470]] = !DILocalVariable(arg: 1, scope: [[DBG466]], file: [[META4]], line: 620, type: [[META7]]) +// CHECK: [[META471]] = !DILocation(line: 620, column: 48, scope: [[DBG466]]) +// CHECK: [[DBG472]] = !DILocation(line: 620, column: 51, scope: [[DBG466]]) +// CHECK: [[DBG473]] = distinct !DISubprogram(name: "Test_Kern_EnumUInt8T", linkageName: "_Z20Test_Kern_EnumUInt8T10EnumUInt8T", scope: [[META4]], file: [[META4]], line: 630, type: [[META467]], scopeLine: 630, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META474:![0-9]+]]) +// CHECK: [[META474]] = !{[[META475]]} +// CHECK: [[META475]] = !DILocalVariable(arg: 1, scope: [[DBG473]], file: [[META4]], line: 630, type: [[META7]]) +// CHECK: [[META476]] = !DILocation(line: 630, column: 48, scope: [[DBG473]]) +// CHECK: [[DBG477]] = !DILocation(line: 630, column: 51, scope: [[DBG473]]) +// CHECK: [[DBG478]] = distinct !DISubprogram(name: "Test_Func_EnumInt16T", linkageName: "_Z20Test_Func_EnumInt16T10EnumInt16T", scope: [[META4]], file: [[META4]], line: 640, type: [[META479:![0-9]+]], scopeLine: 640, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META481:![0-9]+]]) +// CHECK: [[META479]] = !DISubroutineType(types: [[META480:![0-9]+]]) +// CHECK: [[META480]] = !{null, [[META9]]} +// CHECK: [[META481]] = !{[[META482]]} +// CHECK: [[META482]] = !DILocalVariable(arg: 1, scope: [[DBG478]], file: [[META4]], line: 640, type: [[META9]]) +// CHECK: [[META483]] = !DILocation(line: 640, column: 48, scope: [[DBG478]]) +// CHECK: [[DBG484]] = !DILocation(line: 640, column: 51, scope: [[DBG478]]) +// CHECK: [[DBG485]] = distinct !DISubprogram(name: "Test_Kern_EnumInt16T", linkageName: "_Z20Test_Kern_EnumInt16T10EnumInt16T", scope: [[META4]], file: [[META4]], line: 650, type: [[META479]], scopeLine: 650, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META486:![0-9]+]]) +// CHECK: [[META486]] = !{[[META487]]} +// CHECK: [[META487]] = !DILocalVariable(arg: 1, scope: [[DBG485]], file: [[META4]], line: 650, type: [[META9]]) +// CHECK: [[META488]] = !DILocation(line: 650, column: 48, scope: [[DBG485]]) +// CHECK: [[DBG489]] = !DILocation(line: 650, column: 51, scope: [[DBG485]]) +// CHECK: [[DBG490]] = distinct !DISubprogram(name: "Test_Func_EnumUInt16T", linkageName: "_Z21Test_Func_EnumUInt16T11EnumUInt16T", scope: [[META4]], file: [[META4]], line: 660, type: [[META491:![0-9]+]], scopeLine: 660, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META493:![0-9]+]]) +// CHECK: [[META491]] = !DISubroutineType(types: [[META492:![0-9]+]]) +// CHECK: [[META492]] = !{null, [[META11]]} +// CHECK: [[META493]] = !{[[META494]]} +// CHECK: [[META494]] = !DILocalVariable(arg: 1, scope: [[DBG490]], file: [[META4]], line: 660, type: [[META11]]) +// CHECK: [[META495]] = !DILocation(line: 660, column: 50, scope: [[DBG490]]) +// CHECK: [[DBG496]] = !DILocation(line: 660, column: 53, scope: [[DBG490]]) +// CHECK: [[DBG497]] = distinct !DISubprogram(name: "Test_Kern_EnumUInt16T", linkageName: "_Z21Test_Kern_EnumUInt16T11EnumUInt16T", scope: [[META4]], file: [[META4]], line: 670, type: [[META491]], scopeLine: 670, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META498:![0-9]+]]) +// CHECK: [[META498]] = !{[[META499]]} +// CHECK: [[META499]] = !DILocalVariable(arg: 1, scope: [[DBG497]], file: [[META4]], line: 670, type: [[META11]]) +// CHECK: [[META500]] = !DILocation(line: 670, column: 50, scope: [[DBG497]]) +// CHECK: [[DBG501]] = !DILocation(line: 670, column: 53, scope: [[DBG497]]) +// CHECK: [[DBG502]] = distinct !DISubprogram(name: "Test_Func_EnumInt32T", linkageName: "_Z20Test_Func_EnumInt32T10EnumInt32T", scope: [[META4]], file: [[META4]], line: 680, type: [[META503:![0-9]+]], scopeLine: 680, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META505:![0-9]+]]) +// CHECK: [[META503]] = !DISubroutineType(types: [[META504:![0-9]+]]) +// CHECK: [[META504]] = !{null, [[META13]]} +// CHECK: [[META505]] = !{[[META506]]} +// CHECK: [[META506]] = !DILocalVariable(arg: 1, scope: [[DBG502]], file: [[META4]], line: 680, type: [[META13]]) +// CHECK: [[META507]] = !DILocation(line: 680, column: 48, scope: [[DBG502]]) +// CHECK: [[DBG508]] = !DILocation(line: 680, column: 51, scope: [[DBG502]]) +// CHECK: [[DBG509]] = distinct !DISubprogram(name: "Test_Kern_EnumInt32T", linkageName: "_Z20Test_Kern_EnumInt32T10EnumInt32T", scope: [[META4]], file: [[META4]], line: 690, type: [[META503]], scopeLine: 690, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META510:![0-9]+]]) +// CHECK: [[META510]] = !{[[META511]]} +// CHECK: [[META511]] = !DILocalVariable(arg: 1, scope: [[DBG509]], file: [[META4]], line: 690, type: [[META13]]) +// CHECK: [[META512]] = !DILocation(line: 690, column: 48, scope: [[DBG509]]) +// CHECK: [[DBG513]] = !DILocation(line: 690, column: 51, scope: [[DBG509]]) +// CHECK: [[DBG514]] = distinct !DISubprogram(name: "Test_Func_EnumUInt32T", linkageName: "_Z21Test_Func_EnumUInt32T11EnumUInt32T", scope: [[META4]], file: [[META4]], line: 700, type: [[META515:![0-9]+]], scopeLine: 700, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META517:![0-9]+]]) +// CHECK: [[META515]] = !DISubroutineType(types: [[META516:![0-9]+]]) +// CHECK: [[META516]] = !{null, [[META15]]} +// CHECK: [[META517]] = !{[[META518]]} +// CHECK: [[META518]] = !DILocalVariable(arg: 1, scope: [[DBG514]], file: [[META4]], line: 700, type: [[META15]]) +// CHECK: [[META519]] = !DILocation(line: 700, column: 50, scope: [[DBG514]]) +// CHECK: [[DBG520]] = !DILocation(line: 700, column: 53, scope: [[DBG514]]) +// CHECK: [[DBG521]] = distinct !DISubprogram(name: "Test_Kern_EnumUInt32T", linkageName: "_Z21Test_Kern_EnumUInt32T11EnumUInt32T", scope: [[META4]], file: [[META4]], line: 710, type: [[META515]], scopeLine: 710, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META522:![0-9]+]]) +// CHECK: [[META522]] = !{[[META523]]} +// CHECK: [[META523]] = !DILocalVariable(arg: 1, scope: [[DBG521]], file: [[META4]], line: 710, type: [[META15]]) +// CHECK: [[META524]] = !DILocation(line: 710, column: 50, scope: [[DBG521]]) +// CHECK: [[DBG525]] = !DILocation(line: 710, column: 53, scope: [[DBG521]]) +// CHECK: [[DBG526]] = distinct !DISubprogram(name: "Test_Func_EnumInt64T", linkageName: "_Z20Test_Func_EnumInt64T10EnumInt64T", scope: [[META4]], file: [[META4]], line: 720, type: [[META527:![0-9]+]], scopeLine: 720, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META529:![0-9]+]]) +// CHECK: [[META527]] = !DISubroutineType(types: [[META528:![0-9]+]]) +// CHECK: [[META528]] = !{null, [[META17]]} +// CHECK: [[META529]] = !{[[META530]]} +// CHECK: [[META530]] = !DILocalVariable(arg: 1, scope: [[DBG526]], file: [[META4]], line: 720, type: [[META17]]) +// CHECK: [[META531]] = !DILocation(line: 720, column: 48, scope: [[DBG526]]) +// CHECK: [[DBG532]] = !DILocation(line: 720, column: 51, scope: [[DBG526]]) +// CHECK: [[DBG533]] = distinct !DISubprogram(name: "Test_Kern_EnumInt64T", linkageName: "_Z20Test_Kern_EnumInt64T10EnumInt64T", scope: [[META4]], file: [[META4]], line: 730, type: [[META527]], scopeLine: 730, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META534:![0-9]+]]) +// CHECK: [[META534]] = !{[[META535]]} +// CHECK: [[META535]] = !DILocalVariable(arg: 1, scope: [[DBG533]], file: [[META4]], line: 730, type: [[META17]]) +// CHECK: [[META536]] = !DILocation(line: 730, column: 48, scope: [[DBG533]]) +// CHECK: [[DBG537]] = !DILocation(line: 730, column: 51, scope: [[DBG533]]) +// CHECK: [[DBG538]] = distinct !DISubprogram(name: "Test_Func_EnumUInt64T", linkageName: "_Z21Test_Func_EnumUInt64T11EnumUInt64T", scope: [[META4]], file: [[META4]], line: 740, type: [[META539:![0-9]+]], scopeLine: 740, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META541:![0-9]+]]) +// CHECK: [[META539]] = !DISubroutineType(types: [[META540:![0-9]+]]) +// CHECK: [[META540]] = !{null, [[META19]]} +// CHECK: [[META541]] = !{[[META542]]} +// CHECK: [[META542]] = !DILocalVariable(arg: 1, scope: [[DBG538]], file: [[META4]], line: 740, type: [[META19]]) +// CHECK: [[META543]] = !DILocation(line: 740, column: 50, scope: [[DBG538]]) +// CHECK: [[DBG544]] = !DILocation(line: 740, column: 53, scope: [[DBG538]]) +// CHECK: [[DBG545]] = distinct !DISubprogram(name: "Test_Kern_EnumUInt64T", linkageName: "_Z21Test_Kern_EnumUInt64T11EnumUInt64T", scope: [[META4]], file: [[META4]], line: 750, type: [[META539]], scopeLine: 750, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META546:![0-9]+]]) +// CHECK: [[META546]] = !{[[META547]]} +// CHECK: [[META547]] = !DILocalVariable(arg: 1, scope: [[DBG545]], file: [[META4]], line: 750, type: [[META19]]) +// CHECK: [[META548]] = !DILocation(line: 750, column: 50, scope: [[DBG545]]) +// CHECK: [[DBG549]] = !DILocation(line: 750, column: 53, scope: [[DBG545]]) +// CHECK: [[DBG550]] = distinct !DISubprogram(name: "Test_Func_PromotableInteger", linkageName: "_Z27Test_Func_PromotableIntegerb", scope: [[META4]], file: [[META4]], line: 761, type: [[META551:![0-9]+]], scopeLine: 761, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META554:![0-9]+]]) +// CHECK: [[META551]] = !DISubroutineType(types: [[META552:![0-9]+]]) +// CHECK: [[META552]] = !{null, [[META553:![0-9]+]]} +// CHECK: [[META553]] = !DIBasicType(name: "bool", size: 8, encoding: DW_ATE_boolean) +// CHECK: [[META554]] = !{[[META555]]} +// CHECK: [[META555]] = !DILocalVariable(arg: 1, scope: [[DBG550]], file: [[META4]], line: 761, type: [[META553]]) +// CHECK: [[META556]] = !DILocation(line: 761, column: 49, scope: [[DBG550]]) +// CHECK: [[DBG557]] = !DILocation(line: 761, column: 52, scope: [[DBG550]]) +// CHECK: [[DBG558]] = distinct !DISubprogram(name: "Test_Kern_PromotableInteger", linkageName: "_Z27Test_Kern_PromotableIntegerb", scope: [[META4]], file: [[META4]], line: 772, type: [[META551]], scopeLine: 772, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META559:![0-9]+]]) +// CHECK: [[META559]] = !{[[META560]]} +// CHECK: [[META560]] = !DILocalVariable(arg: 1, scope: [[DBG558]], file: [[META4]], line: 772, type: [[META553]]) +// CHECK: [[META561]] = !DILocation(line: 772, column: 49, scope: [[DBG558]]) +// CHECK: [[DBG562]] = !DILocation(line: 772, column: 52, scope: [[DBG558]]) +// CHECK: [[DBG563]] = distinct !DISubprogram(name: "Test_Func_Pointer", linkageName: "_Z17Test_Func_PointerPi", scope: [[META4]], file: [[META4]], line: 782, type: [[META564:![0-9]+]], scopeLine: 782, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META567:![0-9]+]]) +// CHECK: [[META564]] = !DISubroutineType(types: [[META565:![0-9]+]]) +// CHECK: [[META565]] = !{null, [[META566:![0-9]+]]} +// CHECK: [[META566]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META14]], size: 64, addressSpace: 1) +// CHECK: [[META567]] = !{[[META568]]} +// CHECK: [[META568]] = !DILocalVariable(arg: 1, scope: [[DBG563]], file: [[META4]], line: 782, type: [[META566]]) +// CHECK: [[META569]] = !DILocation(line: 782, column: 44, scope: [[DBG563]]) +// CHECK: [[DBG570]] = !DILocation(line: 782, column: 47, scope: [[DBG563]]) +// CHECK: [[DBG571]] = distinct !DISubprogram(name: "Test_Kern_Pointer", linkageName: "_Z17Test_Kern_PointerPi", scope: [[META4]], file: [[META4]], line: 798, type: [[META564]], scopeLine: 798, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META572:![0-9]+]]) +// CHECK: [[META572]] = !{[[META573]]} +// CHECK: [[META573]] = !DILocalVariable(arg: 1, scope: [[DBG571]], file: [[META4]], line: 798, type: [[META566]]) +// CHECK: [[META574]] = !DILocation(line: 798, column: 44, scope: [[DBG571]]) +// CHECK: [[DBG575]] = !DILocation(line: 798, column: 47, scope: [[DBG571]]) +// CHECK: [[DBG576]] = distinct !DISubprogram(name: "Test_Func_Reference", linkageName: "_Z19Test_Func_ReferenceRi", scope: [[META4]], file: [[META4]], line: 808, type: [[META577:![0-9]+]], scopeLine: 808, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META580:![0-9]+]]) +// CHECK: [[META577]] = !DISubroutineType(types: [[META578:![0-9]+]]) +// CHECK: [[META578]] = !{null, [[META579:![0-9]+]]} +// CHECK: [[META579]] = !DIDerivedType(tag: DW_TAG_reference_type, baseType: [[META14]], size: 64, addressSpace: 1) +// CHECK: [[META580]] = !{[[META581]]} +// CHECK: [[META581]] = !DILocalVariable(arg: 1, scope: [[DBG576]], file: [[META4]], line: 808, type: [[META579]]) +// CHECK: [[META582]] = !DILocation(line: 808, column: 46, scope: [[DBG576]]) +// CHECK: [[DBG583]] = !DILocation(line: 808, column: 49, scope: [[DBG576]]) +// CHECK: [[DBG584]] = distinct !DISubprogram(name: "Test_Kern_Reference", linkageName: "_Z19Test_Kern_ReferenceRi", scope: [[META4]], file: [[META4]], line: 824, type: [[META577]], scopeLine: 824, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META585:![0-9]+]]) +// CHECK: [[META585]] = !{[[META586]]} +// CHECK: [[META586]] = !DILocalVariable(arg: 1, scope: [[DBG584]], file: [[META4]], line: 824, type: [[META579]]) +// CHECK: [[META587]] = !DILocation(line: 824, column: 46, scope: [[DBG584]]) +// CHECK: [[DBG588]] = !DILocation(line: 824, column: 49, scope: [[DBG584]]) +// CHECK: [[DBG589]] = distinct !DISubprogram(name: "Test_Func_StructSinglePointerElement", linkageName: "_Z36Test_Func_StructSinglePointerElement26StructSinglePointerElement", scope: [[META4]], file: [[META4]], line: 835, type: [[META590:![0-9]+]], scopeLine: 835, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META595:![0-9]+]]) +// CHECK: [[META590]] = !DISubroutineType(types: [[META591:![0-9]+]]) +// CHECK: [[META591]] = !{null, [[META592:![0-9]+]]} +// CHECK: [[META592]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructSinglePointerElement", file: [[META4]], line: 73, size: 64, flags: DIFlagTypePassByValue, elements: [[META593:![0-9]+]], identifier: "_ZTS26StructSinglePointerElement") +// CHECK: [[META593]] = !{[[META594:![0-9]+]]} +// CHECK: [[META594]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META592]], file: [[META4]], line: 74, baseType: [[META566]], size: 64) +// CHECK: [[META595]] = !{[[META596]]} +// CHECK: [[META596]] = !DILocalVariable(arg: 1, scope: [[DBG589]], file: [[META4]], line: 835, type: [[META592]]) +// CHECK: [[META597]] = !DILocation(line: 835, column: 80, scope: [[DBG589]]) +// CHECK: [[DBG598]] = !DILocation(line: 835, column: 83, scope: [[DBG589]]) +// CHECK: [[DBG599]] = distinct !DISubprogram(name: "Test_Kern_StructSinglePointerElement", linkageName: "_Z36Test_Kern_StructSinglePointerElement26StructSinglePointerElement", scope: [[META4]], file: [[META4]], line: 846, type: [[META590]], scopeLine: 846, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META600:![0-9]+]]) +// CHECK: [[META600]] = !{[[META601]]} +// CHECK: [[META601]] = !DILocalVariable(arg: 1, scope: [[DBG599]], file: [[META4]], line: 846, type: [[META592]]) +// CHECK: [[META602]] = !DILocation(line: 846, column: 80, scope: [[DBG599]]) +// CHECK: [[DBG603]] = !DILocation(line: 846, column: 83, scope: [[DBG599]]) +// CHECK: [[DBG604]] = distinct !DISubprogram(name: "Test_Func_StructPointerElements", linkageName: "_Z31Test_Func_StructPointerElements21StructPointerElements", scope: [[META4]], file: [[META4]], line: 859, type: [[META605:![0-9]+]], scopeLine: 859, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META613:![0-9]+]]) +// CHECK: [[META605]] = !DISubroutineType(types: [[META606:![0-9]+]]) +// CHECK: [[META606]] = !{null, [[META607:![0-9]+]]} +// CHECK: [[META607]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructPointerElements", file: [[META4]], line: 76, size: 128, flags: DIFlagTypePassByValue, elements: [[META608:![0-9]+]], identifier: "_ZTS21StructPointerElements") +// CHECK: [[META608]] = !{[[META609:![0-9]+]], [[META610:![0-9]+]]} +// CHECK: [[META609]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META607]], file: [[META4]], line: 77, baseType: [[META566]], size: 64) +// CHECK: [[META610]] = !DIDerivedType(tag: DW_TAG_member, name: "Element1", scope: [[META607]], file: [[META4]], line: 78, baseType: [[META611:![0-9]+]], size: 64, offset: 64) +// CHECK: [[META611]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META612:![0-9]+]], size: 64, addressSpace: 1) +// CHECK: [[META612]] = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +// CHECK: [[META613]] = !{[[META614]]} +// CHECK: [[META614]] = !DILocalVariable(arg: 1, scope: [[DBG604]], file: [[META4]], line: 859, type: [[META607]]) +// CHECK: [[META615]] = !DILocation(line: 859, column: 70, scope: [[DBG604]]) +// CHECK: [[DBG616]] = !DILocation(line: 859, column: 73, scope: [[DBG604]]) +// CHECK: [[DBG617]] = distinct !DISubprogram(name: "Test_Kern_StructPointerElements", linkageName: "_Z31Test_Kern_StructPointerElements21StructPointerElements", scope: [[META4]], file: [[META4]], line: 869, type: [[META605]], scopeLine: 869, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META618:![0-9]+]]) +// CHECK: [[META618]] = !{[[META619]]} +// CHECK: [[META619]] = !DILocalVariable(arg: 1, scope: [[DBG617]], file: [[META4]], line: 869, type: [[META607]]) +// CHECK: [[META620]] = !DILocation(line: 869, column: 70, scope: [[DBG617]]) +// CHECK: [[DBG621]] = !DILocation(line: 869, column: 73, scope: [[DBG617]]) +// CHECK: [[DBG622]] = distinct !DISubprogram(name: "Test_Func_ParamRegLimitExpandedStruct", linkageName: "_Z37Test_Func_ParamRegLimitExpandedStructlllllli22StructMultipleElements", scope: [[META4]], file: [[META4]], line: 910, type: [[META623:![0-9]+]], scopeLine: 910, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META629:![0-9]+]]) +// CHECK: [[META623]] = !DISubroutineType(types: [[META624:![0-9]+]]) +// CHECK: [[META624]] = !{null, [[META18]], [[META18]], [[META18]], [[META18]], [[META18]], [[META18]], [[META14]], [[META625:![0-9]+]]} +// CHECK: [[META625]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "StructMultipleElements", file: [[META4]], line: 80, size: 128, flags: DIFlagTypePassByValue, elements: [[META626:![0-9]+]], identifier: "_ZTS22StructMultipleElements") +// CHECK: [[META626]] = !{[[META627:![0-9]+]], [[META628:![0-9]+]]} +// CHECK: [[META627]] = !DIDerivedType(tag: DW_TAG_member, name: "Element0", scope: [[META625]], file: [[META4]], line: 81, baseType: [[META14]], size: 32) +// CHECK: [[META628]] = !DIDerivedType(tag: DW_TAG_member, name: "Element1", scope: [[META625]], file: [[META4]], line: 82, baseType: [[META18]], size: 64, offset: 64) +// CHECK: [[META629]] = !{[[META630]], [[META631]], [[META632]], [[META633]], [[META634]], [[META635]], [[META636]], [[META637]]} +// CHECK: [[META630]] = !DILocalVariable(arg: 1, scope: [[DBG622]], file: [[META4]], line: 910, type: [[META18]]) +// CHECK: [[META631]] = !DILocalVariable(arg: 2, scope: [[DBG622]], file: [[META4]], line: 910, type: [[META18]]) +// CHECK: [[META632]] = !DILocalVariable(arg: 3, scope: [[DBG622]], file: [[META4]], line: 910, type: [[META18]]) +// CHECK: [[META633]] = !DILocalVariable(arg: 4, scope: [[DBG622]], file: [[META4]], line: 910, type: [[META18]]) +// CHECK: [[META634]] = !DILocalVariable(arg: 5, scope: [[DBG622]], file: [[META4]], line: 910, type: [[META18]]) +// CHECK: [[META635]] = !DILocalVariable(arg: 6, scope: [[DBG622]], file: [[META4]], line: 910, type: [[META18]]) +// CHECK: [[META636]] = !DILocalVariable(arg: 7, scope: [[DBG622]], file: [[META4]], line: 910, type: [[META14]]) +// CHECK: [[META637]] = !DILocalVariable(arg: 8, scope: [[DBG622]], file: [[META4]], line: 910, type: [[META625]]) +// CHECK: [[META638]] = !DILocation(line: 910, column: 62, scope: [[DBG622]]) +// CHECK: [[META639]] = !DILocation(line: 910, column: 71, scope: [[DBG622]]) +// CHECK: [[META640]] = !DILocation(line: 910, column: 80, scope: [[DBG622]]) +// CHECK: [[META641]] = !DILocation(line: 910, column: 89, scope: [[DBG622]]) +// CHECK: [[META642]] = !DILocation(line: 910, column: 98, scope: [[DBG622]]) +// CHECK: [[META643]] = !DILocation(line: 910, column: 107, scope: [[DBG622]]) +// CHECK: [[META644]] = !DILocation(line: 910, column: 116, scope: [[DBG622]]) +// CHECK: [[META645]] = !DILocation(line: 910, column: 140, scope: [[DBG622]]) +// CHECK: [[DBG646]] = !DILocation(line: 910, column: 143, scope: [[DBG622]]) +// CHECK: [[DBG647]] = distinct !DISubprogram(name: "Test_Kern_ParamRegLimitExpandedStruct", linkageName: "_Z37Test_Kern_ParamRegLimitExpandedStructlllllli22StructMultipleElements", scope: [[META4]], file: [[META4]], line: 948, type: [[META623]], scopeLine: 948, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META648:![0-9]+]]) +// CHECK: [[META648]] = !{[[META649]], [[META650]], [[META651]], [[META652]], [[META653]], [[META654]], [[META655]], [[META656]]} +// CHECK: [[META649]] = !DILocalVariable(arg: 1, scope: [[DBG647]], file: [[META4]], line: 948, type: [[META18]]) +// CHECK: [[META650]] = !DILocalVariable(arg: 2, scope: [[DBG647]], file: [[META4]], line: 948, type: [[META18]]) +// CHECK: [[META651]] = !DILocalVariable(arg: 3, scope: [[DBG647]], file: [[META4]], line: 948, type: [[META18]]) +// CHECK: [[META652]] = !DILocalVariable(arg: 4, scope: [[DBG647]], file: [[META4]], line: 948, type: [[META18]]) +// CHECK: [[META653]] = !DILocalVariable(arg: 5, scope: [[DBG647]], file: [[META4]], line: 948, type: [[META18]]) +// CHECK: [[META654]] = !DILocalVariable(arg: 6, scope: [[DBG647]], file: [[META4]], line: 948, type: [[META18]]) +// CHECK: [[META655]] = !DILocalVariable(arg: 7, scope: [[DBG647]], file: [[META4]], line: 948, type: [[META14]]) +// CHECK: [[META656]] = !DILocalVariable(arg: 8, scope: [[DBG647]], file: [[META4]], line: 948, type: [[META625]]) +// CHECK: [[META657]] = !DILocation(line: 948, column: 62, scope: [[DBG647]]) +// CHECK: [[META658]] = !DILocation(line: 948, column: 71, scope: [[DBG647]]) +// CHECK: [[META659]] = !DILocation(line: 948, column: 80, scope: [[DBG647]]) +// CHECK: [[META660]] = !DILocation(line: 948, column: 89, scope: [[DBG647]]) +// CHECK: [[META661]] = !DILocation(line: 948, column: 98, scope: [[DBG647]]) +// CHECK: [[META662]] = !DILocation(line: 948, column: 107, scope: [[DBG647]]) +// CHECK: [[META663]] = !DILocation(line: 948, column: 116, scope: [[DBG647]]) +// CHECK: [[META664]] = !DILocation(line: 948, column: 140, scope: [[DBG647]]) +// CHECK: [[DBG665]] = !DILocation(line: 948, column: 143, scope: [[DBG647]]) +// CHECK: [[DBG666]] = distinct !DISubprogram(name: "Test_Func_ParamRegLimitUnexpandedStruct", linkageName: "_Z39Test_Func_ParamRegLimitUnexpandedStructlllllll22StructMultipleElements", scope: [[META4]], file: [[META4]], line: 986, type: [[META667:![0-9]+]], scopeLine: 986, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META669:![0-9]+]]) +// CHECK: [[META667]] = !DISubroutineType(types: [[META668:![0-9]+]]) +// CHECK: [[META668]] = !{null, [[META18]], [[META18]], [[META18]], [[META18]], [[META18]], [[META18]], [[META18]], [[META625]]} +// CHECK: [[META669]] = !{[[META670]], [[META671]], [[META672]], [[META673]], [[META674]], [[META675]], [[META676]], [[META677]]} +// CHECK: [[META670]] = !DILocalVariable(arg: 1, scope: [[DBG666]], file: [[META4]], line: 986, type: [[META18]]) +// CHECK: [[META671]] = !DILocalVariable(arg: 2, scope: [[DBG666]], file: [[META4]], line: 986, type: [[META18]]) +// CHECK: [[META672]] = !DILocalVariable(arg: 3, scope: [[DBG666]], file: [[META4]], line: 986, type: [[META18]]) +// CHECK: [[META673]] = !DILocalVariable(arg: 4, scope: [[DBG666]], file: [[META4]], line: 986, type: [[META18]]) +// CHECK: [[META674]] = !DILocalVariable(arg: 5, scope: [[DBG666]], file: [[META4]], line: 986, type: [[META18]]) +// CHECK: [[META675]] = !DILocalVariable(arg: 6, scope: [[DBG666]], file: [[META4]], line: 986, type: [[META18]]) +// CHECK: [[META676]] = !DILocalVariable(arg: 7, scope: [[DBG666]], file: [[META4]], line: 986, type: [[META18]]) +// CHECK: [[META677]] = !DILocalVariable(arg: 8, scope: [[DBG666]], file: [[META4]], line: 986, type: [[META625]]) +// CHECK: [[META678]] = !DILocation(line: 986, column: 64, scope: [[DBG666]]) +// CHECK: [[META679]] = !DILocation(line: 986, column: 73, scope: [[DBG666]]) +// CHECK: [[META680]] = !DILocation(line: 986, column: 82, scope: [[DBG666]]) +// CHECK: [[META681]] = !DILocation(line: 986, column: 91, scope: [[DBG666]]) +// CHECK: [[META682]] = !DILocation(line: 986, column: 100, scope: [[DBG666]]) +// CHECK: [[META683]] = !DILocation(line: 986, column: 109, scope: [[DBG666]]) +// CHECK: [[META684]] = !DILocation(line: 986, column: 118, scope: [[DBG666]]) +// CHECK: [[META685]] = !DILocation(line: 986, column: 142, scope: [[DBG666]]) +// CHECK: [[DBG686]] = !DILocation(line: 986, column: 145, scope: [[DBG666]]) +// CHECK: [[DBG687]] = distinct !DISubprogram(name: "Test_Kern_ParamRegLimitUnexpandedStruct", linkageName: "_Z39Test_Kern_ParamRegLimitUnexpandedStructlllllll22StructMultipleElements", scope: [[META4]], file: [[META4]], line: 1024, type: [[META667]], scopeLine: 1024, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META688:![0-9]+]]) +// CHECK: [[META688]] = !{[[META689]], [[META690]], [[META691]], [[META692]], [[META693]], [[META694]], [[META695]], [[META696]]} +// CHECK: [[META689]] = !DILocalVariable(arg: 1, scope: [[DBG687]], file: [[META4]], line: 1024, type: [[META18]]) +// CHECK: [[META690]] = !DILocalVariable(arg: 2, scope: [[DBG687]], file: [[META4]], line: 1024, type: [[META18]]) +// CHECK: [[META691]] = !DILocalVariable(arg: 3, scope: [[DBG687]], file: [[META4]], line: 1024, type: [[META18]]) +// CHECK: [[META692]] = !DILocalVariable(arg: 4, scope: [[DBG687]], file: [[META4]], line: 1024, type: [[META18]]) +// CHECK: [[META693]] = !DILocalVariable(arg: 5, scope: [[DBG687]], file: [[META4]], line: 1024, type: [[META18]]) +// CHECK: [[META694]] = !DILocalVariable(arg: 6, scope: [[DBG687]], file: [[META4]], line: 1024, type: [[META18]]) +// CHECK: [[META695]] = !DILocalVariable(arg: 7, scope: [[DBG687]], file: [[META4]], line: 1024, type: [[META18]]) +// CHECK: [[META696]] = !DILocalVariable(arg: 8, scope: [[DBG687]], file: [[META4]], line: 1024, type: [[META625]]) +// CHECK: [[META697]] = !DILocation(line: 1024, column: 64, scope: [[DBG687]]) +// CHECK: [[META698]] = !DILocation(line: 1024, column: 73, scope: [[DBG687]]) +// CHECK: [[META699]] = !DILocation(line: 1024, column: 82, scope: [[DBG687]]) +// CHECK: [[META700]] = !DILocation(line: 1024, column: 91, scope: [[DBG687]]) +// CHECK: [[META701]] = !DILocation(line: 1024, column: 100, scope: [[DBG687]]) +// CHECK: [[META702]] = !DILocation(line: 1024, column: 109, scope: [[DBG687]]) +// CHECK: [[META703]] = !DILocation(line: 1024, column: 118, scope: [[DBG687]]) +// CHECK: [[META704]] = !DILocation(line: 1024, column: 142, scope: [[DBG687]]) +// CHECK: [[DBG705]] = !DILocation(line: 1024, column: 145, scope: [[DBG687]]) +//. diff --git a/clang/test/CodeGenHIP/debug-info-anonymous-union-heterogeneous-dwarf.hip b/clang/test/CodeGenHIP/debug-info-anonymous-union-heterogeneous-dwarf.hip new file mode 100644 index 0000000000000..1f09377dd4bde --- /dev/null +++ b/clang/test/CodeGenHIP/debug-info-anonymous-union-heterogeneous-dwarf.hip @@ -0,0 +1,40 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -emit-llvm -fcuda-is-device -debug-info-kind=limited -gheterogeneous-dwarf -o - %s | FileCheck %s + +#define __device__ __attribute__((device)) + +// CHECK-LABEL: define dso_local void @_Z7kernel1v( +// CHECK-SAME: ) #[[ATTR0:[0-9]+]] !dbg [[DBG7:![0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = alloca [[UNION_ANON:%.*]], align 4, addrspace(5) +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META12:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[UNION_ANON]])), [[META21:![0-9]+]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META14:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[UNION_ANON]])), [[META21]]) +// CHECK-NEXT: #dbg_declare(ptr addrspace(5) [[TMP0]], [[META16:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[UNION_ANON]])), [[META21]]) +// CHECK-NEXT: ret void, !dbg [[DBG22:![0-9]+]] +// +__device__ void kernel1() { + union { int x; float f; }; +} + +//. +// CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +// CHECK: [[META1]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// CHECK: [[DBG7]] = distinct !DISubprogram(name: "kernel1", linkageName: "_Z7kernel1v", scope: [[META8:![0-9]+]], file: [[META8]], line: 17, type: [[META9:![0-9]+]], scopeLine: 17, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META11:![0-9]+]]) +// CHECK: [[META8]] = !DIFile(filename: "{{.*}}debug-info-anonymous-union-heterogeneous-dwarf.hip", directory: {{.*}}) +// CHECK: [[META9]] = !DISubroutineType(types: [[META10:![0-9]+]]) +// CHECK: [[META10]] = !{null} +// CHECK: [[META11]] = !{[[META12]], [[META14]], [[META16]]} +// CHECK: [[META12]] = !DILocalVariable(name: "x", scope: [[DBG7]], type: [[META13:![0-9]+]], flags: DIFlagArtificial) +// CHECK: [[META13]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +// CHECK: [[META14]] = !DILocalVariable(name: "f", scope: [[DBG7]], type: [[META15:![0-9]+]], flags: DIFlagArtificial) +// CHECK: [[META15]] = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +// CHECK: [[META16]] = !DILocalVariable(scope: [[DBG7]], type: [[META17:![0-9]+]], flags: DIFlagArtificial) +// CHECK: [[META17]] = distinct !DICompositeType(tag: DW_TAG_union_type, scope: [[DBG7]], file: [[META8]], line: 18, size: 32, flags: DIFlagExportSymbols | DIFlagTypePassByValue, elements: [[META18:![0-9]+]]) +// CHECK: [[META18]] = !{[[META19:![0-9]+]], [[META20:![0-9]+]]} +// CHECK: [[META19]] = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: [[META17]], file: [[META8]], line: 18, baseType: [[META13]], size: 32) +// CHECK: [[META20]] = !DIDerivedType(tag: DW_TAG_member, name: "f", scope: [[META17]], file: [[META8]], line: 18, baseType: [[META15]], size: 32) +// CHECK: [[META21]] = !DILocation(line: 0, scope: [[DBG7]]) +// CHECK: [[DBG22]] = !DILocation(line: 19, column: 1, scope: [[DBG7]]) +//. diff --git a/clang/test/CodeGenHIP/debug-info-cc1-option.hip b/clang/test/CodeGenHIP/debug-info-cc1-option.hip new file mode 100644 index 0000000000000..b34442da7a853 --- /dev/null +++ b/clang/test/CodeGenHIP/debug-info-cc1-option.hip @@ -0,0 +1,11 @@ +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -emit-llvm -fcuda-is-device -debug-info-kind=limited -gheterogeneous-dwarf -o - %s | FileCheck %s + +// Check that -gheterogeneous-dwarf without an `=OPTION` suffix remains valid +// and aliases the new default. This is needed for transitioning flang-classic +// as it depends on the -cc1 interface. + +// CHECK: #dbg_declare{{.*}}DIExpression{{.*}}DIOp +__attribute__((device)) void kernel1(int Arg) { + int FuncVar; +} diff --git a/clang/test/CodeGenHIP/debug-info-diop-in-diexpression_dwarf.hip b/clang/test/CodeGenHIP/debug-info-diop-in-diexpression_dwarf.hip new file mode 100644 index 0000000000000..69e50c2140807 --- /dev/null +++ b/clang/test/CodeGenHIP/debug-info-diop-in-diexpression_dwarf.hip @@ -0,0 +1,174 @@ +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -x hip -triple amdgcn-amd-amdhsa -emit-obj -fcuda-is-device -debug-info-kind=limited -gheterogeneous-dwarf -o - %s | llvm-dwarfdump --diff - | FileCheck --check-prefixes=CHECK %s +// RUN: %clang_cc1 -x hip -triple amdgcn-amd-amdhsa -emit-obj -fcuda-is-device -debug-info-kind=limited -gheterogeneous-dwarf -mllvm -stop-after=amdgpu-isel -o - %s | llc -x mir -verify-machineinstrs -start-after=amdgpu-isel -filetype=obj -o - - | llvm-dwarfdump --diff - | FileCheck --check-prefixes=CHECK %s + +#define __global__ __attribute__((global)) +#define __device__ __attribute__((device)) +#define __shared__ __attribute__((shared)) +#define __constant__ __attribute__((constant)) + +__shared__ int GlobalSharedA; +__shared__ int GlobalSharedB; +__device__ int GlobalDeviceA; +__device__ int GlobalDeviceB; +__constant__ int GlobalConstantA; +__constant__ int GlobalConstantB; + +__global__ void kernel1(int Arg) { + __shared__ int KernelVarSharedA; + __shared__ int KernelVarSharedB; + int KernelVarA; + int KernelVarB; + + auto *KernelVarSharedAPointer = &KernelVarSharedA; + auto *KernelVarSharedBPointer = &KernelVarSharedB; + auto *KernelVarAPointer = &KernelVarA; + auto *KernelVarBPointer = &KernelVarB; +} + +__device__ void func1(int Arg) { + int FuncVarA; + int FuncVarB; + + auto *FuncVarAPointer = &FuncVarA; + auto *FuncVarBPointer = &FuncVarB; +} + + +// CHECK: .debug_info contents: +// CHECK: DW_TAG_compile_unit + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_name ("GlobalSharedA") +// CHECK: DW_AT_type ("int") +// CHECK: DW_AT_external (true) +// CHECK: DW_AT_LLVM_memory_space (DW_MSPACE_LLVM_group) +// CHECK-NOT: DW_AT_location + +// CHECK: DW_TAG_base_type +// CHECK: DW_AT_name ("int") +// CHECK: DW_AT_encoding (DW_ATE_signed) +// CHECK: DW_AT_byte_size (0x04) + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_name ("GlobalSharedB") +// CHECK: DW_AT_type ("int") +// CHECK: DW_AT_external (true) +// CHECK: DW_AT_LLVM_memory_space (DW_MSPACE_LLVM_group) +// CHECK-NOT: DW_AT_location + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_name ("GlobalDeviceA") +// CHECK: DW_AT_type ("int") +// CHECK: DW_AT_external (true) +// CHECK: DW_AT_LLVM_memory_space (DW_MSPACE_LLVM_global) +// CHECK: DW_AT_location (DW_OP_addr 0x0, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_name ("GlobalDeviceB") +// CHECK: DW_AT_type ("int") +// CHECK: DW_AT_external (true) +// CHECK: DW_AT_LLVM_memory_space (DW_MSPACE_LLVM_global) +// CHECK: DW_AT_location (DW_OP_addr 0x0, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_name ("GlobalConstantA") +// CHECK: DW_AT_type ("int") +// CHECK: DW_AT_external (true) +// CHECK: DW_AT_LLVM_memory_space (DW_MSPACE_LLVM_constant) +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_name ("GlobalConstantB") +// CHECK: DW_AT_type ("int") +// CHECK: DW_AT_external (true) +// CHECK: DW_AT_LLVM_memory_space (DW_MSPACE_LLVM_constant) +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) + +// CHECK: DW_TAG_subprogram +// CHECK: DW_AT_linkage_name ("_Z7kernel1i") +// CHECK: DW_AT_name ("kernel1") +// CHECK: DW_AT_external (true) + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_name ("KernelVarSharedA") +// CHECK: DW_AT_type ("int") +// CHECK: DW_AT_LLVM_memory_space (DW_MSPACE_LLVM_group) +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit0, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit3, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_name ("KernelVarSharedB") +// CHECK: DW_AT_type ("int") +// CHECK: DW_AT_LLVM_memory_space (DW_MSPACE_LLVM_group) +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit4, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit3, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) + +// CHECK: DW_TAG_formal_parameter +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_lit0, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("Arg") +// CHECK: DW_AT_type ("int") + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_lit4, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("KernelVarA") +// CHECK: DW_AT_type ("int") + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_lit8, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("KernelVarB") +// CHECK: DW_AT_type ("int") + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_lit16, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("KernelVarSharedAPointer") +// CHECK: DW_AT_type ("int *") + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_lit24, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("KernelVarSharedBPointer") +// CHECK: DW_AT_type ("int *") + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_constu 0x20, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("KernelVarAPointer") +// CHECK: DW_AT_type ("int *") + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_constu 0x28, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("KernelVarBPointer") +// CHECK: DW_AT_type ("int *") +// CHECK: NULL + +// CHECK: DW_TAG_subprogram +// CHECK: DW_AT_linkage_name ("_Z5func1i") +// CHECK: DW_AT_name ("func1") +// CHECK: DW_AT_external (true) + +// CHECK: DW_TAG_formal_parameter +// CHECK: DW_AT_location (DW_OP_regx 0x40, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_lit0, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("Arg") +// CHECK: DW_AT_type ("int") + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_location (DW_OP_regx 0x40, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_lit4, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("FuncVarA") +// CHECK: DW_AT_type ("int") + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_location (DW_OP_regx 0x40, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_lit8, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("FuncVarB") +// CHECK: DW_AT_type ("int") + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_location (DW_OP_regx 0x40, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_lit16, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("FuncVarAPointer") +// CHECK: DW_AT_type ("int *") + +// CHECK: DW_TAG_variable +// CHECK: DW_AT_location (DW_OP_regx 0x40, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shr, DW_OP_lit24, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) +// CHECK: DW_AT_name ("FuncVarBPointer") +// CHECK: DW_AT_type ("int *") +// CHECK: NULL + +// CHECK: DW_TAG_pointer_type +// CHECK: DW_AT_type ("int") +// CHECK: NULL diff --git a/clang/test/CodeGenHIP/debug-info-diop-in-diexpression_ir.hip b/clang/test/CodeGenHIP/debug-info-diop-in-diexpression_ir.hip new file mode 100644 index 0000000000000..42eee71c2f38d --- /dev/null +++ b/clang/test/CodeGenHIP/debug-info-diop-in-diexpression_ir.hip @@ -0,0 +1,166 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals smart +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -x hip -triple amdgcn-amd-amdhsa -emit-llvm -fcuda-is-device -debug-info-kind=limited -gheterogeneous-dwarf=diexpression -o - %s | FileCheck --check-prefix=DIEXPRESSION-IR %s + +#define __global__ __attribute__((global)) +#define __device__ __attribute__((device)) +#define __shared__ __attribute__((shared)) +#define __constant__ __attribute__((constant)) + +__shared__ int GlobalSharedA; +__shared__ int GlobalSharedB; +__device__ int GlobalDeviceA; +__device__ int GlobalDeviceB; +__constant__ int GlobalConstantA; +__constant__ int GlobalConstantB; + +// DIEXPRESSION-IR-LABEL: @_Z7kernel1i( +// DIEXPRESSION-IR-NEXT: entry: +// DIEXPRESSION-IR-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[KERNELVARA:%.*]] = alloca i32, align 4, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[KERNELVARB:%.*]] = alloca i32, align 4, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[KERNELVARSHAREDAPOINTER:%.*]] = alloca ptr, align 8, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[KERNELVARSHAREDBPOINTER:%.*]] = alloca ptr, align 8, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[KERNELVARAPOINTER:%.*]] = alloca ptr, align 8, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[KERNELVARBPOINTER:%.*]] = alloca ptr, align 8, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[ARG_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARG_ADDR]] to ptr +// DIEXPRESSION-IR-NEXT: [[KERNELVARA_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[KERNELVARA]] to ptr +// DIEXPRESSION-IR-NEXT: [[KERNELVARB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[KERNELVARB]] to ptr +// DIEXPRESSION-IR-NEXT: [[KERNELVARSHAREDAPOINTER_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[KERNELVARSHAREDAPOINTER]] to ptr +// DIEXPRESSION-IR-NEXT: [[KERNELVARSHAREDBPOINTER_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[KERNELVARSHAREDBPOINTER]] to ptr +// DIEXPRESSION-IR-NEXT: [[KERNELVARAPOINTER_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[KERNELVARAPOINTER]] to ptr +// DIEXPRESSION-IR-NEXT: [[KERNELVARBPOINTER_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[KERNELVARBPOINTER]] to ptr +// DIEXPRESSION-IR-NEXT: store i32 [[ARG:%.*]], ptr [[ARG_ADDR_ASCAST]], align 4 +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[ARG_ADDR]], [[META23:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META38:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[KERNELVARA]], [[META24:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META39:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[KERNELVARB]], [[META25:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META40:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[KERNELVARSHAREDAPOINTER]], [[META26:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr)), [[META41:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: store ptr addrspacecast (ptr addrspace(3) @_ZZ7kernel1iE16KernelVarSharedA to ptr), ptr [[KERNELVARSHAREDAPOINTER_ASCAST]], align 8, !dbg [[META41]] +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[KERNELVARSHAREDBPOINTER]], [[META28:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr)), [[META42:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: store ptr addrspacecast (ptr addrspace(3) @_ZZ7kernel1iE16KernelVarSharedB to ptr), ptr [[KERNELVARSHAREDBPOINTER_ASCAST]], align 8, !dbg [[META42]] +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[KERNELVARAPOINTER]], [[META29:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr)), [[META43:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: store ptr [[KERNELVARA_ASCAST]], ptr [[KERNELVARAPOINTER_ASCAST]], align 8, !dbg [[META43]] +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[KERNELVARBPOINTER]], [[META30:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr)), [[META44:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: store ptr [[KERNELVARB_ASCAST]], ptr [[KERNELVARBPOINTER_ASCAST]], align 8, !dbg [[META44]] +// DIEXPRESSION-IR-NEXT: ret void, !dbg [[DBG45:![0-9]+]] +// +__global__ void kernel1(int Arg) { + __shared__ int KernelVarSharedA; + __shared__ int KernelVarSharedB; + int KernelVarA; + int KernelVarB; + + auto *KernelVarSharedAPointer = &KernelVarSharedA; + auto *KernelVarSharedBPointer = &KernelVarSharedB; + auto *KernelVarAPointer = &KernelVarA; + auto *KernelVarBPointer = &KernelVarB; +} + +// DIEXPRESSION-IR-LABEL: @_Z5func1i( +// DIEXPRESSION-IR-NEXT: entry: +// DIEXPRESSION-IR-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[FUNCVARA:%.*]] = alloca i32, align 4, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[FUNCVARB:%.*]] = alloca i32, align 4, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[FUNCVARAPOINTER:%.*]] = alloca ptr, align 8, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[FUNCVARBPOINTER:%.*]] = alloca ptr, align 8, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[ARG_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARG_ADDR]] to ptr +// DIEXPRESSION-IR-NEXT: [[FUNCVARA_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[FUNCVARA]] to ptr +// DIEXPRESSION-IR-NEXT: [[FUNCVARB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[FUNCVARB]] to ptr +// DIEXPRESSION-IR-NEXT: [[FUNCVARAPOINTER_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[FUNCVARAPOINTER]] to ptr +// DIEXPRESSION-IR-NEXT: [[FUNCVARBPOINTER_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[FUNCVARBPOINTER]] to ptr +// DIEXPRESSION-IR-NEXT: store i32 [[ARG:%.*]], ptr [[ARG_ADDR_ASCAST]], align 4 +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[ARG_ADDR]], [[META48:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META53:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[FUNCVARA]], [[META49:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META54:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[FUNCVARB]], [[META50:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META55:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[FUNCVARAPOINTER]], [[META51:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr)), [[META56:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: store ptr [[FUNCVARA_ASCAST]], ptr [[FUNCVARAPOINTER_ASCAST]], align 8, !dbg [[META56]] +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[FUNCVARBPOINTER]], [[META52:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr)), [[META57:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: store ptr [[FUNCVARB_ASCAST]], ptr [[FUNCVARBPOINTER_ASCAST]], align 8, !dbg [[META57]] +// DIEXPRESSION-IR-NEXT: ret void, !dbg [[DBG58:![0-9]+]] +// +__device__ void func1(int Arg) { + int FuncVarA; + int FuncVarB; + + auto *FuncVarAPointer = &FuncVarA; + auto *FuncVarBPointer = &FuncVarB; +} + +struct pair { int first, second; }; +// DIEXPRESSION-IR-LABEL: @_Z5func14pair( +// DIEXPRESSION-IR-NEXT: entry: +// DIEXPRESSION-IR-NEXT: [[P:%.*]] = alloca [[STRUCT_PAIR:%.*]], align 4, addrspace(5) +// DIEXPRESSION-IR-NEXT: [[P1:%.*]] = addrspacecast ptr addrspace(5) [[P]] to ptr +// DIEXPRESSION-IR-NEXT: store [2 x i32] [[P_COERCE:%.*]], ptr [[P1]], align 4 +// DIEXPRESSION-IR-NEXT: #dbg_declare(ptr addrspace(5) [[P]], [[META67:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref([[STRUCT_PAIR]])), [[META68:![0-9]+]]) +// DIEXPRESSION-IR-NEXT: ret void, !dbg [[DBG69:![0-9]+]] +// +__device__ void func1(pair p) {} + +//. +// DIEXPRESSION-IR: [[META0:![0-9]+]] = !DIGlobalVariableExpression(var: [[META1:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpDeref(i32))) +// DIEXPRESSION-IR: [[META1]] = distinct !DIGlobalVariable(name: "GlobalSharedA", scope: [[META2:![0-9]+]], file: [[META7:![0-9]+]], line: 10, type: [[META8:![0-9]+]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) +// DIEXPRESSION-IR: [[META2]] = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: [[META3:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: [[META4:![0-9]+]], splitDebugInlining: false, nameTableKind: None) +// DIEXPRESSION-IR: [[META3]] = !DIFile(filename: "{{.*}}", directory: {{.*}}) +// DIEXPRESSION-IR: [[META4]] = !{[[META0]], [[META5:![0-9]+]], [[META9:![0-9]+]], [[META11:![0-9]+]], [[META13:![0-9]+]], [[META15:![0-9]+]], [[META17:![0-9]+]], [[META31:![0-9]+]]} +// DIEXPRESSION-IR: [[META5]] = !DIGlobalVariableExpression(var: [[META6:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpDeref(i32))) +// DIEXPRESSION-IR: [[META6]] = distinct !DIGlobalVariable(name: "GlobalSharedB", scope: [[META2]], file: [[META7]], line: 11, type: [[META8]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) +// DIEXPRESSION-IR: [[META7]] = !DIFile(filename: "{{.*}}debug-info-diop-in-diexpression_ir.hip", directory: {{.*}}) +// DIEXPRESSION-IR: [[META8]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +// DIEXPRESSION-IR: [[META9]] = !DIGlobalVariableExpression(var: [[META10:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(1)), DIOpDeref(i32))) +// DIEXPRESSION-IR: [[META10]] = distinct !DIGlobalVariable(name: "GlobalDeviceA", scope: [[META2]], file: [[META7]], line: 12, type: [[META8]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) +// DIEXPRESSION-IR: [[META11]] = !DIGlobalVariableExpression(var: [[META12:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(1)), DIOpDeref(i32))) +// DIEXPRESSION-IR: [[META12]] = distinct !DIGlobalVariable(name: "GlobalDeviceB", scope: [[META2]], file: [[META7]], line: 13, type: [[META8]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) +// DIEXPRESSION-IR: [[META13]] = !DIGlobalVariableExpression(var: [[META14:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(4)), DIOpDeref(i32))) +// DIEXPRESSION-IR: [[META14]] = distinct !DIGlobalVariable(name: "GlobalConstantA", scope: [[META2]], file: [[META7]], line: 14, type: [[META8]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) +// DIEXPRESSION-IR: [[META15]] = !DIGlobalVariableExpression(var: [[META16:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(4)), DIOpDeref(i32))) +// DIEXPRESSION-IR: [[META16]] = distinct !DIGlobalVariable(name: "GlobalConstantB", scope: [[META2]], file: [[META7]], line: 15, type: [[META8]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) +// DIEXPRESSION-IR: [[META17]] = !DIGlobalVariableExpression(var: [[META18:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpDeref(i32))) +// DIEXPRESSION-IR: [[META18]] = distinct !DIGlobalVariable(name: "KernelVarSharedA", scope: [[META19:![0-9]+]], file: [[META7]], line: 48, type: [[META8]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) +// DIEXPRESSION-IR: [[META19]] = distinct !DISubprogram(name: "kernel1", linkageName: "_Z7kernel1i", scope: [[META7]], file: [[META7]], line: 47, type: [[META20:![0-9]+]], scopeLine: 47, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META2]], retainedNodes: [[META22:![0-9]+]]) +// DIEXPRESSION-IR: [[META20]] = !DISubroutineType(types: [[META21:![0-9]+]]) +// DIEXPRESSION-IR: [[META21]] = !{null, [[META8]]} +// DIEXPRESSION-IR: [[META22]] = !{[[META23]], [[META24]], [[META25]], [[META26]], [[META28]], [[META29]], [[META30]]} +// DIEXPRESSION-IR: [[META23]] = !DILocalVariable(name: "Arg", arg: 1, scope: [[META19]], file: [[META7]], line: 47, type: [[META8]]) +// DIEXPRESSION-IR: [[META24]] = !DILocalVariable(name: "KernelVarA", scope: [[META19]], file: [[META7]], line: 50, type: [[META8]]) +// DIEXPRESSION-IR: [[META25]] = !DILocalVariable(name: "KernelVarB", scope: [[META19]], file: [[META7]], line: 51, type: [[META8]]) +// DIEXPRESSION-IR: [[META26]] = !DILocalVariable(name: "KernelVarSharedAPointer", scope: [[META19]], file: [[META7]], line: 53, type: [[META27:![0-9]+]]) +// DIEXPRESSION-IR: [[META27]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[META8]], size: 64, addressSpace: 1) +// DIEXPRESSION-IR: [[META28]] = !DILocalVariable(name: "KernelVarSharedBPointer", scope: [[META19]], file: [[META7]], line: 54, type: [[META27]]) +// DIEXPRESSION-IR: [[META29]] = !DILocalVariable(name: "KernelVarAPointer", scope: [[META19]], file: [[META7]], line: 55, type: [[META27]]) +// DIEXPRESSION-IR: [[META30]] = !DILocalVariable(name: "KernelVarBPointer", scope: [[META19]], file: [[META7]], line: 56, type: [[META27]]) +// DIEXPRESSION-IR: [[META31]] = !DIGlobalVariableExpression(var: [[META32:![0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpDeref(i32))) +// DIEXPRESSION-IR: [[META32]] = distinct !DIGlobalVariable(name: "KernelVarSharedB", scope: [[META19]], file: [[META7]], line: 49, type: [[META8]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) +// DIEXPRESSION-IR: [[META38]] = !DILocation(line: 47, column: 29, scope: [[META19]]) +// DIEXPRESSION-IR: [[META39]] = !DILocation(line: 50, column: 7, scope: [[META19]]) +// DIEXPRESSION-IR: [[META40]] = !DILocation(line: 51, column: 7, scope: [[META19]]) +// DIEXPRESSION-IR: [[META41]] = !DILocation(line: 53, column: 9, scope: [[META19]]) +// DIEXPRESSION-IR: [[META42]] = !DILocation(line: 54, column: 9, scope: [[META19]]) +// DIEXPRESSION-IR: [[META43]] = !DILocation(line: 55, column: 9, scope: [[META19]]) +// DIEXPRESSION-IR: [[META44]] = !DILocation(line: 56, column: 9, scope: [[META19]]) +// DIEXPRESSION-IR: [[DBG45]] = !DILocation(line: 57, column: 1, scope: [[META19]]) +// DIEXPRESSION-IR: [[META46:![0-9]+]] = distinct !DISubprogram(name: "func1", linkageName: "_Z5func1i", scope: [[META7]], file: [[META7]], line: 81, type: [[META20]], scopeLine: 81, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META2]], retainedNodes: [[META47:![0-9]+]]) +// DIEXPRESSION-IR: [[META47]] = !{[[META48]], [[META49]], [[META50]], [[META51]], [[META52]]} +// DIEXPRESSION-IR: [[META48]] = !DILocalVariable(name: "Arg", arg: 1, scope: [[META46]], file: [[META7]], line: 81, type: [[META8]]) +// DIEXPRESSION-IR: [[META49]] = !DILocalVariable(name: "FuncVarA", scope: [[META46]], file: [[META7]], line: 82, type: [[META8]]) +// DIEXPRESSION-IR: [[META50]] = !DILocalVariable(name: "FuncVarB", scope: [[META46]], file: [[META7]], line: 83, type: [[META8]]) +// DIEXPRESSION-IR: [[META51]] = !DILocalVariable(name: "FuncVarAPointer", scope: [[META46]], file: [[META7]], line: 85, type: [[META27]]) +// DIEXPRESSION-IR: [[META52]] = !DILocalVariable(name: "FuncVarBPointer", scope: [[META46]], file: [[META7]], line: 86, type: [[META27]]) +// DIEXPRESSION-IR: [[META53]] = !DILocation(line: 81, column: 27, scope: [[META46]]) +// DIEXPRESSION-IR: [[META54]] = !DILocation(line: 82, column: 7, scope: [[META46]]) +// DIEXPRESSION-IR: [[META55]] = !DILocation(line: 83, column: 7, scope: [[META46]]) +// DIEXPRESSION-IR: [[META56]] = !DILocation(line: 85, column: 9, scope: [[META46]]) +// DIEXPRESSION-IR: [[META57]] = !DILocation(line: 86, column: 9, scope: [[META46]]) +// DIEXPRESSION-IR: [[DBG58]] = !DILocation(line: 87, column: 1, scope: [[META46]]) +// DIEXPRESSION-IR: [[META59:![0-9]+]] = distinct !DISubprogram(name: "func1", linkageName: "_Z5func14pair", scope: [[META7]], file: [[META7]], line: 98, type: [[META60:![0-9]+]], scopeLine: 98, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: [[META2]], retainedNodes: [[META66:![0-9]+]]) +// DIEXPRESSION-IR: [[META60]] = !DISubroutineType(types: [[META61:![0-9]+]]) +// DIEXPRESSION-IR: [[META61]] = !{null, [[META62:![0-9]+]]} +// DIEXPRESSION-IR: [[META62]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "pair", file: [[META7]], line: 89, size: 64, flags: DIFlagTypePassByValue, elements: [[META63:![0-9]+]], identifier: "_ZTS4pair") +// DIEXPRESSION-IR: [[META63]] = !{[[META64:![0-9]+]], [[META65:![0-9]+]]} +// DIEXPRESSION-IR: [[META64]] = !DIDerivedType(tag: DW_TAG_member, name: "first", scope: [[META62]], file: [[META7]], line: 89, baseType: [[META8]], size: 32) +// DIEXPRESSION-IR: [[META65]] = !DIDerivedType(tag: DW_TAG_member, name: "second", scope: [[META62]], file: [[META7]], line: 89, baseType: [[META8]], size: 32, offset: 32) +// DIEXPRESSION-IR: [[META66]] = !{[[META67]]} +// DIEXPRESSION-IR: [[META67]] = !DILocalVariable(name: "p", arg: 1, scope: [[META59]], file: [[META7]], line: 98, type: [[META62]]) +// DIEXPRESSION-IR: [[META68]] = !DILocation(line: 98, column: 28, scope: [[META59]]) +// DIEXPRESSION-IR: [[DBG69]] = !DILocation(line: 98, column: 32, scope: [[META59]]) +//. diff --git a/clang/test/CodeGenHIP/debug-info-for-profiling.hip b/clang/test/CodeGenHIP/debug-info-for-profiling.hip new file mode 100644 index 0000000000000..e99e454275621 --- /dev/null +++ b/clang/test/CodeGenHIP/debug-info-for-profiling.hip @@ -0,0 +1,18 @@ +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -emit-llvm -fcuda-is-device -debug-info-kind=constructor -fdebug-info-for-profiling -gheterogeneous-dwarf=diexpression -o - %s 2>&1 | FileCheck %s + +// Regression test for workaround in SWDEV-469667 + +#define __device__ __attribute__((device)) + +struct S { + int member; +}; + +__device__ int *sink; + +__device__ void kernel1(struct S *s) { +// CHECK-NOT: MDNode incompatible with Debug Info Version + *sink = s->member; +} + diff --git a/clang/test/CodeGenHIP/debug-info-memory-space.hip b/clang/test/CodeGenHIP/debug-info-memory-space.hip new file mode 100644 index 0000000000000..bd92c172aa759 --- /dev/null +++ b/clang/test/CodeGenHIP/debug-info-memory-space.hip @@ -0,0 +1,27 @@ +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -emit-llvm -fcuda-is-device -debug-info-kind=limited -gheterogeneous-dwarf -o - %s | FileCheck %s +// CHECK-DAG: !DIGlobalVariable(name: "GlobalShared", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) +// CHECK-DAG: !DIGlobalVariable(name: "GlobalDevice", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) +// CHECK-DAG: !DIGlobalVariable(name: "GlobalConstant", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) +// CHECK-DAG: !DIGlobalVariable(name: "FuncVarShared", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) +// CHECK-DAG: !DILocalVariable(name: "FuncVar", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) + +// CHECK-DAG: !DILocalVariable(name: "FuncVarSharedPointer", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DEVICE_PTR:[0-9]+]]) +// CHECK-DAG: !DILocalVariable(name: "FuncVarPointer", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DEVICE_PTR:[0-9]+]]) +// CHECK-DAG: ![[DEVICE_PTR]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, addressSpace: 1) + +#define __device__ __attribute__((device)) +#define __shared__ __attribute__((shared)) +#define __constant__ __attribute__((constant)) + +__shared__ int GlobalShared; +__device__ int GlobalDevice; +__constant__ int GlobalConstant; + +__device__ void kernel1(int Arg) { + __shared__ int FuncVarShared; + int FuncVar; + + auto *FuncVarSharedPointer = &FuncVarShared; + auto *FuncVarPointer = &FuncVar; +} diff --git a/clang/test/CodeGenHipStdPar/select-accelerator-code-pass-ordering.cpp b/clang/test/CodeGenHipStdPar/select-accelerator-code-pass-ordering.cpp index 44557284fc581..f03b783199a41 100644 --- a/clang/test/CodeGenHipStdPar/select-accelerator-code-pass-ordering.cpp +++ b/clang/test/CodeGenHipStdPar/select-accelerator-code-pass-ordering.cpp @@ -7,6 +7,7 @@ // HIPSTDPAR-PRE: Running pass: EntryExitInstrumenterPass // HIPSTDPAR-PRE-NEXT: Running pass: EntryExitInstrumenterPass // HIPSTDPAR-PRE-NOT: Running pass: HipStdParAcceleratorCodeSelectionPass +// HIPSTDPAR-PRE-NEXT: Running pass: AMDGPUExpandFeaturePredicatesPass // HIPSTDPAR-PRE-NEXT: Running pass: AlwaysInlinerPass // Ensure Pass HipStdParAcceleratorCodeSelectionPass is invoked in PostLink. diff --git a/clang/test/CodeGenObjCXX/address-safety-attr.mm b/clang/test/CodeGenObjCXX/address-safety-attr.mm index 8a7462d98dcfb..380e518abb7dc 100644 --- a/clang/test/CodeGenObjCXX/address-safety-attr.mm +++ b/clang/test/CodeGenObjCXX/address-safety-attr.mm @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -emit-llvm -o - %s | FileCheck %s --implicit-check-not=sanitize_address // RUN: %clang_cc1 -emit-llvm -o - %s -fsanitize=address | FileCheck %s --check-prefixes=CHECK,ASAN +// REQUIRES: more-investigation + @interface MyClass + (int) addressSafety:(int*)a; @end diff --git a/clang/test/CodeGenOpenCL/amdgpu-debug-info-pointer-address-space.cl b/clang/test/CodeGenOpenCL/amdgpu-debug-info-pointer-address-space.cl index e6a783fff4bc5..21471e23f6aa1 100644 --- a/clang/test/CodeGenOpenCL/amdgpu-debug-info-pointer-address-space.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-debug-info-pointer-address-space.cl @@ -2,123 +2,124 @@ // RUN: %clang -cl-std=CL2.0 -emit-llvm -g -O0 -S -nogpulib -target amdgcn-amd-amdhsa -mcpu=fiji -o - %s | FileCheck %s // RUN: %clang -cl-std=CL2.0 -emit-llvm -g -O0 -S -nogpulib -target amdgcn-amd-amdhsa-opencl -mcpu=fiji -o - %s | FileCheck %s -// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_GLOBAL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}) -// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_LOCAL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, dwarfAddressSpace: 3) -// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_PRIVATE:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, dwarfAddressSpace: 5) -// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_GENERIC:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, dwarfAddressSpace: 1) +// CHECK-DAG: ![[DWARF_MEMORY_SPACE_GLOBAL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_global) +// CHECK-DAG: ![[DWARF_MEMORY_SPACE_CONSTANT:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_constant) +// CHECK-DAG: ![[DWARF_MEMORY_SPACE_LOCAL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, addressSpace: 3, memorySpace: DW_MSPACE_LLVM_group) +// CHECK-DAG: ![[DWARF_MEMORY_SPACE_PRIVATE:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, addressSpace: 5, memorySpace: DW_MSPACE_LLVM_private) +// CHECK-DAG: ![[DWARF_MEMORY_SPACE_NONE:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, addressSpace: 1) -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_GLOBAL]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) global int *FileVar0; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_CONSTANT]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) constant int *FileVar1; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_LOCAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_LOCAL]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) local int *FileVar2; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_PRIVATE]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_PRIVATE]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) private int *FileVar3; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GENERIC]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_NONE]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) int *FileVar4; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar5", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar5", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_GLOBAL]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) global int *global FileVar5; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar6", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar6", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_CONSTANT]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) constant int *global FileVar6; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar7", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_LOCAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar7", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_LOCAL]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) local int *global FileVar7; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar8", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_PRIVATE]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar8", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_PRIVATE]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) private int *global FileVar8; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar9", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GENERIC]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar9", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_NONE]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) int *global FileVar9; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar10", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar10", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_GLOBAL]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) global int *constant FileVar10 = 0; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar11", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar11", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_CONSTANT]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) constant int *constant FileVar11 = 0; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar12", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_LOCAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar12", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_LOCAL]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) local int *constant FileVar12 = 0; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar13", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_PRIVATE]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar13", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_PRIVATE]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) private int *constant FileVar13 = 0; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar14", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GENERIC]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar14", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_NONE]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) int *constant FileVar14 = 0; kernel void kernel1( - // CHECK-DAG: !DILocalVariable(name: "KernelArg0", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]]) + // CHECK-DAG: !DILocalVariable(name: "KernelArg0", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_GLOBAL]], memorySpace: DW_MSPACE_LLVM_private) global int *KernelArg0, - // CHECK-DAG: !DILocalVariable(name: "KernelArg1", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]]) + // CHECK-DAG: !DILocalVariable(name: "KernelArg1", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_CONSTANT]], memorySpace: DW_MSPACE_LLVM_private) constant int *KernelArg1, - // CHECK-DAG: !DILocalVariable(name: "KernelArg2", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_LOCAL]]) + // CHECK-DAG: !DILocalVariable(name: "KernelArg2", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_LOCAL]], memorySpace: DW_MSPACE_LLVM_private) local int *KernelArg2) { private int *Tmp0; int *Tmp1; - // CHECK-DAG: !DILocalVariable(name: "FuncVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]]) + // CHECK-DAG: !DILocalVariable(name: "FuncVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_GLOBAL]], memorySpace: DW_MSPACE_LLVM_private) global int *FuncVar0 = KernelArg0; - // CHECK-DAG: !DILocalVariable(name: "FuncVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]]) + // CHECK-DAG: !DILocalVariable(name: "FuncVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_CONSTANT]], memorySpace: DW_MSPACE_LLVM_private) constant int *FuncVar1 = KernelArg1; - // CHECK-DAG: !DILocalVariable(name: "FuncVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_LOCAL]]) + // CHECK-DAG: !DILocalVariable(name: "FuncVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_LOCAL]], memorySpace: DW_MSPACE_LLVM_private) local int *FuncVar2 = KernelArg2; - // CHECK-DAG: !DILocalVariable(name: "FuncVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_PRIVATE]]) + // CHECK-DAG: !DILocalVariable(name: "FuncVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_PRIVATE]], memorySpace: DW_MSPACE_LLVM_private) private int *FuncVar3 = Tmp0; - // CHECK-DAG: !DILocalVariable(name: "FuncVar4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GENERIC]]) + // CHECK-DAG: !DILocalVariable(name: "FuncVar4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_NONE]], memorySpace: DW_MSPACE_LLVM_private) int *FuncVar4 = Tmp1; - // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar5", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: true, isDefinition: true) + // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar5", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_GLOBAL]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) global int *constant FuncVar5 = 0; - // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar6", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: true, isDefinition: true) + // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar6", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_CONSTANT]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) constant int *constant FuncVar6 = 0; - // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar7", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_LOCAL]], isLocal: true, isDefinition: true) + // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar7", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_LOCAL]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) local int *constant FuncVar7 = 0; - // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar8", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_PRIVATE]], isLocal: true, isDefinition: true) + // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar8", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_PRIVATE]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) private int *constant FuncVar8 = 0; - // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar9", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GENERIC]], isLocal: true, isDefinition: true) + // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar9", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_NONE]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) int *constant FuncVar9 = 0; - // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar10", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: true, isDefinition: true) + // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar10", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_GLOBAL]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) global int *local FuncVar10; FuncVar10 = KernelArg0; - // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar11", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: true, isDefinition: true) + // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar11", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_CONSTANT]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) constant int *local FuncVar11; FuncVar11 = KernelArg1; - // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar12", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_LOCAL]], isLocal: true, isDefinition: true) + // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar12", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_LOCAL]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) local int *local FuncVar12; FuncVar12 = KernelArg2; - // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar13", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_PRIVATE]], isLocal: true, isDefinition: true) + // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar13", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_PRIVATE]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) private int *local FuncVar13; FuncVar13 = Tmp0; - // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar14", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GENERIC]], isLocal: true, isDefinition: true) + // CHECK-DAG: distinct !DIGlobalVariable(name: "FuncVar14", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_NONE]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) int *local FuncVar14; FuncVar14 = Tmp1; - // CHECK-DAG: !DILocalVariable(name: "FuncVar15", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]]) + // CHECK-DAG: !DILocalVariable(name: "FuncVar15", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_GLOBAL]], memorySpace: DW_MSPACE_LLVM_private) global int *private FuncVar15 = KernelArg0; - // CHECK-DAG: !DILocalVariable(name: "FuncVar16", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]]) + // CHECK-DAG: !DILocalVariable(name: "FuncVar16", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_CONSTANT]], memorySpace: DW_MSPACE_LLVM_private) constant int *private FuncVar16 = KernelArg1; - // CHECK-DAG: !DILocalVariable(name: "FuncVar17", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_LOCAL]]) + // CHECK-DAG: !DILocalVariable(name: "FuncVar17", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_LOCAL]], memorySpace: DW_MSPACE_LLVM_private) local int *private FuncVar17 = KernelArg2; - // CHECK-DAG: !DILocalVariable(name: "FuncVar18", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_PRIVATE]]) + // CHECK-DAG: !DILocalVariable(name: "FuncVar18", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_PRIVATE]], memorySpace: DW_MSPACE_LLVM_private) private int *private FuncVar18 = Tmp0; - // CHECK-DAG: !DILocalVariable(name: "FuncVar19", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GENERIC]]) + // CHECK-DAG: !DILocalVariable(name: "FuncVar19", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_MEMORY_SPACE_NONE]], memorySpace: DW_MSPACE_LLVM_private) int *private FuncVar19 = Tmp1; } struct FileStruct0 { - // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "StructMem0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_ADDRESS_SPACE_GLOBAL]], size: {{[0-9]+}}) + // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "StructMem0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_MEMORY_SPACE_GLOBAL]], size: {{[0-9]+}}) global int *StructMem0; - // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "StructMem1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_ADDRESS_SPACE_GLOBAL]], size: {{[0-9]+}}, offset: {{[0-9]+}}) + // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "StructMem1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_MEMORY_SPACE_CONSTANT]], size: {{[0-9]+}}, offset: {{[0-9]+}}) constant int *StructMem1; - // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "StructMem2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_ADDRESS_SPACE_LOCAL]], size: {{[0-9]+}}, offset: {{[0-9]+}}) + // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "StructMem2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_MEMORY_SPACE_LOCAL]], size: {{[0-9]+}}, offset: {{[0-9]+}}) local int *StructMem2; - // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "StructMem3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_ADDRESS_SPACE_PRIVATE]], size: {{[0-9]+}}, offset: {{[0-9]+}}) + // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "StructMem3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_MEMORY_SPACE_PRIVATE]], size: {{[0-9]+}}, offset: {{[0-9]+}}) private int *StructMem3; - // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "StructMem4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_ADDRESS_SPACE_GENERIC]], size: {{[0-9]+}}, offset: {{[0-9]+}}) + // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "StructMem4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_MEMORY_SPACE_NONE]], size: {{[0-9]+}}, offset: {{[0-9]+}}) int *StructMem4; }; struct FileStruct1 { union { - // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "UnionMem0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_ADDRESS_SPACE_GLOBAL]], size: {{[0-9]+}}) + // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "UnionMem0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_MEMORY_SPACE_GLOBAL]], size: {{[0-9]+}}) global int *UnionMem0; - // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "UnionMem1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_ADDRESS_SPACE_GLOBAL]], size: {{[0-9]+}}) + // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "UnionMem1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_MEMORY_SPACE_CONSTANT]], size: {{[0-9]+}}) constant int *UnionMem1; - // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "UnionMem2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_ADDRESS_SPACE_LOCAL]], size: {{[0-9]+}}) + // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "UnionMem2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_MEMORY_SPACE_LOCAL]], size: {{[0-9]+}}) local int *UnionMem2; - // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "UnionMem3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_ADDRESS_SPACE_PRIVATE]], size: {{[0-9]+}}) + // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "UnionMem3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_MEMORY_SPACE_PRIVATE]], size: {{[0-9]+}}) private int *UnionMem3; - // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "UnionMem4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_ADDRESS_SPACE_GENERIC]], size: {{[0-9]+}}) + // CHECK-DAG: !DIDerivedType(tag: DW_TAG_member, name: "UnionMem4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, baseType: ![[DWARF_MEMORY_SPACE_NONE]], size: {{[0-9]+}}) int *UnionMem4; }; long StructMem0; diff --git a/clang/test/CodeGenOpenCL/amdgpu-debug-info-struct-function-arg.cl b/clang/test/CodeGenOpenCL/amdgpu-debug-info-struct-function-arg.cl new file mode 100644 index 0000000000000..0f8764ad30c13 --- /dev/null +++ b/clang/test/CodeGenOpenCL/amdgpu-debug-info-struct-function-arg.cl @@ -0,0 +1,36 @@ +// REQUIRES: amdgpu-registered-target +// RUN: %clang -g -target amdgcn-amd-amdhsa -march=gfx900 -O0 -nogpulib %s -c -o - | llvm-dwarfdump -v -debug-info - | FileCheck "%s" +// CHECK: DW_TAG_subprogram +// CHECK: DW_AT_name [DW_FORM_strx1] +// CHECK-SAME: (indexed ({{[0-9a-f]+}}) string = "foo") +// +// CHECK: DW_TAG_formal_parameter +// CHECK: DW_AT_name [DW_FORM_strx1] +// CHECK-SAME: (indexed ({{[0-9a-f]+}}) string = "data") +// CHECK: DW_AT_type [DW_FORM_ref4] +// CHECK-SAME: (cu + 0x{{[0-9a-f]+}} => {0x[[BAR_OFFSET:[0-9a-f]+]]} "bar") +// +// CHECK: DW_TAG_variable +// CHECK: DW_AT_name [DW_FORM_strx1] +// CHECK-SAME: (indexed ({{[0-9a-f]+}}) string = "offset") +// +// CHECK: 0x[[BAR_OFFSET]]: DW_TAG_structure_type +// CHECK: DW_AT_name [DW_FORM_strx1] +// CHECK-SAME: (indexed ({{[0-9a-f]+}}) string = "bar") +// +// CHECK: DW_TAG_member +// CHECK: DW_AT_name [DW_FORM_strx1] +// CHECK-SAME: (indexed ({{[0-9a-f]+}}) string = "C") +// +// CHECK: DW_TAG_member +// CHECK: DW_AT_name [DW_FORM_strx1] +// CHECK-SAME: (indexed ({{[0-9a-f]+}}) string = "A") +struct bar { + __global unsigned *C; + __global unsigned *A; +}; + +void foo(struct bar data) { + unsigned offset = get_global_id(0); + data.C[offset] = data.A[offset]; +} diff --git a/clang/test/CodeGenOpenCL/amdgpu-debug-info-variable-expression.cl b/clang/test/CodeGenOpenCL/amdgpu-debug-info-variable-expression.cl index 4d5f1019378af..01b0f85626840 100644 --- a/clang/test/CodeGenOpenCL/amdgpu-debug-info-variable-expression.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-debug-info-variable-expression.cl @@ -1,129 +1,129 @@ // REQUIRES: amdgpu-registered-target -// RUN: %clang -cl-std=CL2.0 -emit-llvm -g -O0 -S -nogpulib -target amdgcn-amd-amdhsa -mcpu=fiji -o - %s | FileCheck %s -// RUN: %clang -cl-std=CL2.0 -emit-llvm -g -O0 -S -nogpulib -target amdgcn-amd-amdhsa-opencl -mcpu=fiji -o - %s | FileCheck %s +// RUN: %clang -cl-std=CL2.0 -emit-llvm -g -gno-heterogeneous-dwarf -O0 -S -nogpulib -target amdgcn-amd-amdhsa -mcpu=fiji -o - %s | FileCheck %s +// RUN: %clang -cl-std=CL2.0 -emit-llvm -g -gno-heterogeneous-dwarf -O0 -S -nogpulib -target amdgcn-amd-amdhsa-opencl -mcpu=fiji -o - %s | FileCheck %s -// CHECK-DAG: ![[FILEVAR0:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR0:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR0]], expr: !DIExpression()) global int *FileVar0; -// CHECK-DAG: ![[FILEVAR1:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR1:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR1]], expr: !DIExpression()) constant int *FileVar1; -// CHECK-DAG: ![[FILEVAR2:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR2:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR2]], expr: !DIExpression()) local int *FileVar2; -// CHECK-DAG: ![[FILEVAR3:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR3:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR3]], expr: !DIExpression()) private int *FileVar3; -// CHECK-DAG: ![[FILEVAR4:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR4:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR4]], expr: !DIExpression()) int *FileVar4; -// CHECK-DAG: ![[FILEVAR5:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar5", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR5:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar5", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR5]], expr: !DIExpression()) global int *global FileVar5; -// CHECK-DAG: ![[FILEVAR6:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar6", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR6:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar6", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR6]], expr: !DIExpression()) constant int *global FileVar6; -// CHECK-DAG: ![[FILEVAR7:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar7", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR7:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar7", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR7]], expr: !DIExpression()) local int *global FileVar7; -// CHECK-DAG: ![[FILEVAR8:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar8", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR8:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar8", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR8]], expr: !DIExpression()) private int *global FileVar8; -// CHECK-DAG: ![[FILEVAR9:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar9", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR9:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar9", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR9]], expr: !DIExpression()) int *global FileVar9; -// CHECK-DAG: ![[FILEVAR10:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar10", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR10:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar10", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR10]], expr: !DIExpression()) global int *constant FileVar10 = 0; -// CHECK-DAG: ![[FILEVAR11:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar11", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR11:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar11", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR11]], expr: !DIExpression()) constant int *constant FileVar11 = 0; -// CHECK-DAG: ![[FILEVAR12:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar12", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR12:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar12", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR12]], expr: !DIExpression()) local int *constant FileVar12 = 0; -// CHECK-DAG: ![[FILEVAR13:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar13", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR13:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar13", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR13]], expr: !DIExpression()) private int *constant FileVar13 = 0; -// CHECK-DAG: ![[FILEVAR14:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar14", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true) +// CHECK-DAG: ![[FILEVAR14:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar14", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR14]], expr: !DIExpression()) int *constant FileVar14 = 0; kernel void kernel1( - // CHECK-DAG: ![[KERNELARG0:[0-9]+]] = !DILocalVariable(name: "KernelArg0", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[KERNELARG0]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[KERNELARG0:[0-9]+]] = !DILocalVariable(name: "KernelArg0", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[KERNELARG0]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) global int *KernelArg0, - // CHECK-DAG: ![[KERNELARG1:[0-9]+]] = !DILocalVariable(name: "KernelArg1", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[KERNELARG1]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[KERNELARG1:[0-9]+]] = !DILocalVariable(name: "KernelArg1", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[KERNELARG1]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) constant int *KernelArg1, - // CHECK-DAG: ![[KERNELARG2:[0-9]+]] = !DILocalVariable(name: "KernelArg2", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[KERNELARG2]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[KERNELARG2:[0-9]+]] = !DILocalVariable(name: "KernelArg2", arg: {{[0-9]+}}, scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[KERNELARG2]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) local int *KernelArg2) { private int *Tmp0; int *Tmp1; - // CHECK-DAG: ![[FUNCVAR0:[0-9]+]] = !DILocalVariable(name: "FuncVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR0]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[FUNCVAR0:[0-9]+]] = !DILocalVariable(name: "FuncVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR0]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) global int *FuncVar0 = KernelArg0; - // CHECK-DAG: ![[FUNCVAR1:[0-9]+]] = !DILocalVariable(name: "FuncVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR1]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[FUNCVAR1:[0-9]+]] = !DILocalVariable(name: "FuncVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR1]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) constant int *FuncVar1 = KernelArg1; - // CHECK-DAG: ![[FUNCVAR2:[0-9]+]] = !DILocalVariable(name: "FuncVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR2]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[FUNCVAR2:[0-9]+]] = !DILocalVariable(name: "FuncVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR2]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) local int *FuncVar2 = KernelArg2; - // CHECK-DAG: ![[FUNCVAR3:[0-9]+]] = !DILocalVariable(name: "FuncVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR3]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[FUNCVAR3:[0-9]+]] = !DILocalVariable(name: "FuncVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR3]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) private int *FuncVar3 = Tmp0; - // CHECK-DAG: ![[FUNCVAR4:[0-9]+]] = !DILocalVariable(name: "FuncVar4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR4]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[FUNCVAR4:[0-9]+]] = !DILocalVariable(name: "FuncVar4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR4]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) int *FuncVar4 = Tmp1; - // CHECK-DAG: ![[FUNCVAR5:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar5", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR5:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar5", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR5]], expr: !DIExpression()) global int *constant FuncVar5 = 0; - // CHECK-DAG: ![[FUNCVAR6:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar6", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR6:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar6", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR6]], expr: !DIExpression()) constant int *constant FuncVar6 = 0; - // CHECK-DAG: ![[FUNCVAR7:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar7", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR7:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar7", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR7]], expr: !DIExpression()) local int *constant FuncVar7 = 0; - // CHECK-DAG: ![[FUNCVAR8:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar8", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR8:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar8", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR8]], expr: !DIExpression()) private int *constant FuncVar8 = 0; - // CHECK-DAG: ![[FUNCVAR9:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar9", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR9:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar9", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR9]], expr: !DIExpression()) int *constant FuncVar9 = 0; - // CHECK-DAG: ![[FUNCVAR10:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar10", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR10:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar10", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR10]], expr: !DIExpression(DW_OP_constu, 3, DW_OP_swap, DW_OP_xderef)) global int *local FuncVar10; FuncVar10 = KernelArg0; - // CHECK-DAG: ![[FUNCVAR11:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar11", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR11:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar11", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR11]], expr: !DIExpression(DW_OP_constu, 3, DW_OP_swap, DW_OP_xderef)) constant int *local FuncVar11; FuncVar11 = KernelArg1; - // CHECK-DAG: ![[FUNCVAR12:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar12", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR12:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar12", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR12]], expr: !DIExpression(DW_OP_constu, 3, DW_OP_swap, DW_OP_xderef)) local int *local FuncVar12; FuncVar12 = KernelArg2; - // CHECK-DAG: ![[FUNCVAR13:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar13", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR13:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar13", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR13]], expr: !DIExpression(DW_OP_constu, 3, DW_OP_swap, DW_OP_xderef)) private int *local FuncVar13; FuncVar13 = Tmp0; - // CHECK-DAG: ![[FUNCVAR14:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar14", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + // CHECK-DAG: ![[FUNCVAR14:[0-9]+]] = distinct !DIGlobalVariable(name: "FuncVar14", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_group) // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FUNCVAR14]], expr: !DIExpression(DW_OP_constu, 3, DW_OP_swap, DW_OP_xderef)) int *local FuncVar14; FuncVar14 = Tmp1; - // CHECK-DAG: ![[FUNCVAR15:[0-9]+]] = !DILocalVariable(name: "FuncVar15", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR15]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[FUNCVAR15:[0-9]+]] = !DILocalVariable(name: "FuncVar15", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR15]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) global int *private FuncVar15 = KernelArg0; - // CHECK-DAG: ![[FUNCVAR16:[0-9]+]] = !DILocalVariable(name: "FuncVar16", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR16]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[FUNCVAR16:[0-9]+]] = !DILocalVariable(name: "FuncVar16", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR16]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) constant int *private FuncVar16 = KernelArg1; - // CHECK-DAG: ![[FUNCVAR17:[0-9]+]] = !DILocalVariable(name: "FuncVar17", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR17]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[FUNCVAR17:[0-9]+]] = !DILocalVariable(name: "FuncVar17", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR17]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) local int *private FuncVar17 = KernelArg2; - // CHECK-DAG: ![[FUNCVAR18:[0-9]+]] = !DILocalVariable(name: "FuncVar18", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR18]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[FUNCVAR18:[0-9]+]] = !DILocalVariable(name: "FuncVar18", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR18]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) private int *private FuncVar18 = Tmp0; - // CHECK-DAG: ![[FUNCVAR19:[0-9]+]] = !DILocalVariable(name: "FuncVar19", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}) - // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR19]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}} + // CHECK-DAG: ![[FUNCVAR19:[0-9]+]] = !DILocalVariable(name: "FuncVar19", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: !{{[0-9]+}}, memorySpace: DW_MSPACE_LLVM_private) + // CHECK-DAG: #dbg_declare(ptr addrspace(5) {{.*}}, ![[FUNCVAR19]], !DIExpression(DW_OP_constu, 5, DW_OP_swap, DW_OP_xderef), !{{[0-9]+}}) int *private FuncVar19 = Tmp1; } diff --git a/clang/test/CodeGenOpenCL/bpf-debug-info-extern-heterogeneous-dwarf.cl b/clang/test/CodeGenOpenCL/bpf-debug-info-extern-heterogeneous-dwarf.cl new file mode 100644 index 0000000000000..ba8dfa90f9875 --- /dev/null +++ b/clang/test/CodeGenOpenCL/bpf-debug-info-extern-heterogeneous-dwarf.cl @@ -0,0 +1,13 @@ +// REQUIRES: bpf-registered-target +// RUN: %clang -Xclang -cl-std=CL2.0 -emit-llvm -g -gheterogeneous-dwarf=diexpression -O0 -S -nogpulib -target bpf-linux-gnu -o - %s | FileCheck %s + +// FIXME: Currently just testing that we don't crash; test for the absense +// of meaningful debug information for the extern is to identify this test +// to update/replace when this is implemented. + +// CHECK-NOT: DIGlobalVariable + +extern char ch; +int test() { + return ch; +} diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl new file mode 100644 index 0000000000000..e15ca0167ef6c --- /dev/null +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals smart +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx950 -emit-llvm -o - %s | FileCheck %s -check-prefixes=GFX,GFX950 +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx9-4-generic -emit-llvm -o - %s | FileCheck %s -check-prefixes=GFX,GFX9_4_GENERIC + +typedef __attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int v4u32; +typedef v4u32 __global *global_ptr_to_v4u32; + +//------------------------------------------------------------------------------ +// Store +//------------------------------------------------------------------------------ +// GFX-LABEL: @test_amdgcn_global_store_b128_00( +// GFX-NEXT: entry: +// GFX-NEXT: tail call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) [[PTR:%.*]], <4 x i32> [[DATA:%.*]], metadata [[META4:![0-9]+]]) +// GFX-NEXT: ret void +// +void test_amdgcn_global_store_b128_00(global_ptr_to_v4u32 ptr, v4u32 data) { + __builtin_amdgcn_global_store_b128(ptr, data, "wavefront"); +} + +// GFX-LABEL: @test_amdgcn_global_store_b128_01( +// GFX-NEXT: entry: +// GFX-NEXT: tail call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) [[PTR:%.*]], <4 x i32> [[DATA:%.*]], metadata [[META5:![0-9]+]]) +// GFX-NEXT: ret void +// +void test_amdgcn_global_store_b128_01(global_ptr_to_v4u32 ptr, v4u32 data) { + __builtin_amdgcn_global_store_b128(ptr, data, "workgroup"); +} + +// GFX-LABEL: @test_amdgcn_global_store_b128_10( +// GFX-NEXT: entry: +// GFX-NEXT: tail call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) [[PTR:%.*]], <4 x i32> [[DATA:%.*]], metadata [[META6:![0-9]+]]) +// GFX-NEXT: ret void +// +void test_amdgcn_global_store_b128_10(global_ptr_to_v4u32 ptr, v4u32 data) { + __builtin_amdgcn_global_store_b128(ptr, data, "agent"); +} + +// GFX-LABEL: @test_amdgcn_global_store_b128_11( +// GFX-NEXT: entry: +// GFX-NEXT: tail call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) [[PTR:%.*]], <4 x i32> [[DATA:%.*]], metadata [[META7:![0-9]+]]) +// GFX-NEXT: ret void +// +void test_amdgcn_global_store_b128_11(global_ptr_to_v4u32 ptr, v4u32 data) { + __builtin_amdgcn_global_store_b128(ptr, data, ""); +} + +//------------------------------------------------------------------------------ +// Load +//------------------------------------------------------------------------------ +// GFX-LABEL: @test_amdgcn_global_load_b128_00( +// GFX-NEXT: entry: +// GFX-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) [[PTR:%.*]], metadata [[META4]]) +// GFX-NEXT: ret <4 x i32> [[TMP0]] +// +v4u32 test_amdgcn_global_load_b128_00(global_ptr_to_v4u32 ptr) { + return __builtin_amdgcn_global_load_b128(ptr, "wavefront"); +} + +// GFX-LABEL: @test_amdgcn_global_load_b128_01( +// GFX-NEXT: entry: +// GFX-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) [[PTR:%.*]], metadata [[META5]]) +// GFX-NEXT: ret <4 x i32> [[TMP0]] +// +v4u32 test_amdgcn_global_load_b128_01(global_ptr_to_v4u32 ptr) { + return __builtin_amdgcn_global_load_b128(ptr, "workgroup"); +} + +// GFX-LABEL: @test_amdgcn_global_load_b128_10( +// GFX-NEXT: entry: +// GFX-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) [[PTR:%.*]], metadata [[META6]]) +// GFX-NEXT: ret <4 x i32> [[TMP0]] +// +v4u32 test_amdgcn_global_load_b128_10(global_ptr_to_v4u32 ptr) { + return __builtin_amdgcn_global_load_b128(ptr, "agent"); +} + +// GFX-LABEL: @test_amdgcn_global_load_b128_11( +// GFX-NEXT: entry: +// GFX-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) [[PTR:%.*]], metadata [[META7]]) +// GFX-NEXT: ret <4 x i32> [[TMP0]] +// +v4u32 test_amdgcn_global_load_b128_11(global_ptr_to_v4u32 ptr) { + return __builtin_amdgcn_global_load_b128(ptr, ""); +} +//. +// GFX950: [[META4]] = !{!"wavefront"} +// GFX950: [[META5]] = !{!"workgroup"} +// GFX950: [[META6]] = !{!"agent"} +// GFX950: [[META7]] = !{!""} +//. +// GFX9_4_GENERIC: [[META4]] = !{!"wavefront"} +// GFX9_4_GENERIC: [[META5]] = !{!"workgroup"} +// GFX9_4_GENERIC: [[META6]] = !{!"agent"} +// GFX9_4_GENERIC: [[META7]] = !{!""} +//. +//// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +// GFX950: {{.*}} +// GFX9_4_GENERIC: {{.*}} diff --git a/clang/test/CodeGenOpenCL/spir-debug-info-pointer-address-space.cl b/clang/test/CodeGenOpenCL/spir-debug-info-pointer-address-space.cl index 28b6c674c8ffd..d7ac107848b77 100644 --- a/clang/test/CodeGenOpenCL/spir-debug-info-pointer-address-space.cl +++ b/clang/test/CodeGenOpenCL/spir-debug-info-pointer-address-space.cl @@ -1,23 +1,23 @@ // RUN: %clang_cc1 -cl-std=CL2.0 -debug-info-kind=limited -dwarf-version=5 -emit-llvm -O0 -triple spir-unknown-unknown -o - %s | FileCheck %s // RUN: %clang_cc1 -cl-std=CL2.0 -debug-info-kind=limited -dwarf-version=5 -emit-llvm -O0 -triple spir64-unknown-unknown -o - %s | FileCheck %s -// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_GLOBAL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, dwarfAddressSpace: 1) -// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_CONSTANT:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, dwarfAddressSpace: 2) -// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_LOCAL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, dwarfAddressSpace: 3) -// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_PRIVATE:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, dwarfAddressSpace: 0) -// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_GENERIC:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, dwarfAddressSpace: 4) +// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_GLOBAL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, addressSpace: 1, memorySpace: DW_MSPACE_LLVM_global) +// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_CONSTANT:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, addressSpace: 2, memorySpace: DW_MSPACE_LLVM_constant) +// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_LOCAL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, addressSpace: 3, memorySpace: DW_MSPACE_LLVM_group) +// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_PRIVATE:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, addressSpace: 0, memorySpace: DW_MSPACE_LLVM_private) +// CHECK-DAG: ![[DWARF_ADDRESS_SPACE_GENERIC:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !{{[0-9]+}}, size: {{[0-9]+}}, addressSpace: 4) -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GLOBAL]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) global int *FileVar0; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_CONSTANT]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_CONSTANT]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) constant int *FileVar1; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_LOCAL]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_LOCAL]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) local int *FileVar2; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_PRIVATE]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_PRIVATE]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) private int *FileVar3; -// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GENERIC]], isLocal: false, isDefinition: true) +// CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar4", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, line: {{[0-9]+}}, type: ![[DWARF_ADDRESS_SPACE_GENERIC]], isLocal: false, isDefinition: true, memorySpace: DW_MSPACE_LLVM_global) int *FileVar4; diff --git a/clang/test/DebugInfo/KeyInstructions/for.c b/clang/test/DebugInfo/KeyInstructions/for.c index e7c1567c14d60..0dd9e6755abb9 100644 --- a/clang/test/DebugInfo/KeyInstructions/for.c +++ b/clang/test/DebugInfo/KeyInstructions/for.c @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -triple x86_64-linux-gnu -gkey-instructions -x c++ %s -debug-info-kind=line-tables-only -emit-llvm -o - \ // RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank +// REQUIRES: goodKeys + // RUN: %clang_cc1 -triple x86_64-linux-gnu -gkey-instructions -x c %s -debug-info-kind=line-tables-only -emit-llvm -o - \ // RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank diff --git a/clang/test/DebugInfo/KeyInstructions/init-member-memcopyable-2.cpp b/clang/test/DebugInfo/KeyInstructions/init-member-memcopyable-2.cpp index c94fc588bf13b..6ba2464874ac3 100644 --- a/clang/test/DebugInfo/KeyInstructions/init-member-memcopyable-2.cpp +++ b/clang/test/DebugInfo/KeyInstructions/init-member-memcopyable-2.cpp @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple x86_64-linux-gnu -gkey-instructions %s -gno-column-info -debug-info-kind=line-tables-only -emit-llvm -o - \ // RUN: | FileCheck %s +// REQUIRES: goodKeys // g::h and i can be memcpy'd, check the assignment gets Key Instructions metadata. diff --git a/clang/test/DebugInfo/KeyInstructions/init-member-memcopyable.cpp b/clang/test/DebugInfo/KeyInstructions/init-member-memcopyable.cpp index cd3807735fa32..ec28cde3b4c4e 100644 --- a/clang/test/DebugInfo/KeyInstructions/init-member-memcopyable.cpp +++ b/clang/test/DebugInfo/KeyInstructions/init-member-memcopyable.cpp @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple x86_64-linux-gnu -gkey-instructions %s -gno-column-info -debug-info-kind=line-tables-only -emit-llvm -o - \ // RUN: | FileCheck %s +// REQUIRES: goodKeys // g::h can be memcpy'd (in this case emitted as load/stored), check the // assignment gets Key Instructions metadata. diff --git a/clang/test/DebugInfo/KeyInstructions/return-va-arg.c b/clang/test/DebugInfo/KeyInstructions/return-va-arg.c index 0773bf5353177..7bfca47418918 100644 --- a/clang/test/DebugInfo/KeyInstructions/return-va-arg.c +++ b/clang/test/DebugInfo/KeyInstructions/return-va-arg.c @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple x86_64-linux-gnu -gkey-instructions -gno-column-info -x c++ %s -debug-info-kind=line-tables-only -emit-llvm -o - \ // RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank +// REQUIRES: goodKeys // RUN: %clang_cc1 -triple x86_64-linux-gnu -gkey-instructions -gno-column-info -x c %s -debug-info-kind=line-tables-only -emit-llvm -o - \ // RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank diff --git a/clang/test/Driver/A+A.c b/clang/test/Driver/A+A.c new file mode 100644 index 0000000000000..9efe6422d7a8f --- /dev/null +++ b/clang/test/Driver/A+A.c @@ -0,0 +1,24 @@ +// RUN: %clang -target x86_64-unknown-linux-gnu --sysroot %S/Inputs/basic_cross_linux_tree %s \ +// RUN: -fno-amd-opt -flto -O3 -### 2>&1 | FileCheck --check-prefix=CHECK-LTO-OPEN %s +// CHECK-LTO-OPEN-NOT: "{{.*}}../alt/bin/clang-{{.*}}" +// CHECK-LTO-OPEN-NOT: "{{.*}}../alt/bin/ld.lld" + +// RUN: %clang -target x86_64-unknown-linux-gnu --sysroot %S/Inputs/basic_cross_linux_tree %s \ +// RUN: -fno-amd-opt -O3 -### 2>&1 | FileCheck --check-prefix=CHECK-OPEN %s +// CHECK-OPEN-NOT: "{{.*}}../alt/bin/clang-{{.*}}" +// CHECK-OPEN-NOT: "{{.*}}../alt/bin/ld.lld" + +// RUN: not %clang -target x86_64-unknown-linux-gnu --sysroot %S/Inputs/basic_cross_linux_tree %s \ +// RUN: -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 \ +// RUN: -fno-amd-opt -flto -O3 -### 2>&1 | FileCheck --check-prefix=CHECK-OMP-LTO-OPEN %s +// CHECK-OMP-LTO-OPEN-NOT: "{{.*}}../alt/bin/clang-{{.*}}" +// CHECK-OMP-LTO-OPEN-NOT: "{{.*}}../alt/bin/ld.lld" + +// RUN: not %clang -target x86_64-unknown-linux-gnu --sysroot %S/Inputs/basic_cross_linux_tree %s \ +// RUN: -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 \ +// RUN: -fno-amd-opt -O3 -### 2>&1 | FileCheck --check-prefix=CHECK-OMP-OPEN %s +// CHECK-OMP-OPEN-NOT: "{{.*}}../alt/bin/clang-{{.*}}" +// CHECK-OMP-OPEN-NOT: "{{.*}}../alt/bin/ld.lld" + +// RUN: %clang -famd-opt -O3 -### %s 2>&1 | FileCheck --check-prefix=CHECK-ALT-MISS %s +// CHECK-ALT-MISS: warning: argument unused during compilation: '-famd-opt' diff --git a/clang/test/Driver/DTLTO/dtlto.c b/clang/test/Driver/DTLTO/dtlto.c index 5fbf7889e790b..a5bc273c378a5 100644 --- a/clang/test/Driver/DTLTO/dtlto.c +++ b/clang/test/Driver/DTLTO/dtlto.c @@ -1,4 +1,5 @@ // REQUIRES: lld +// REQUIRES: npsdb-stability /// Check DTLTO options are forwarded to the linker. diff --git a/clang/test/Driver/amdgcn-openmp-toolchain-dwarf.c b/clang/test/Driver/amdgcn-openmp-toolchain-dwarf.c new file mode 100644 index 0000000000000..7a02ea95e07c5 --- /dev/null +++ b/clang/test/Driver/amdgcn-openmp-toolchain-dwarf.c @@ -0,0 +1,12 @@ +// REQUIRES: clang-driver +// REQUIRES: x86-registered-target +// REQUIRES: amdgpu-registered-target + +// RUN: %clang -### -target x86_64-pc-linux-gnu -fopenmp \ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -nogpulib \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 \ +// RUN: -g \ +// RUN: %s 2>&1 | FileCheck %s + +// CHECK: [[CLANG:".*clang.*"]] "-cc1" "-triple" "amdgcn-amd-amdhsa" +// CHECK-SAME: "-dwarf-version=5" diff --git a/clang/test/Driver/amdgcn-toolchain-openmp-duplicate-arguments.c b/clang/test/Driver/amdgcn-toolchain-openmp-duplicate-arguments.c new file mode 100644 index 0000000000000..085423e55b1ba --- /dev/null +++ b/clang/test/Driver/amdgcn-toolchain-openmp-duplicate-arguments.c @@ -0,0 +1,28 @@ +// REQUIRES: clang-driver +// REQUIRES: x86-registered-target +// REQUIRES: amdgpu-registered-target + +// RUN: %clang -### -target x86_64-pc-linux-gnu -fopenmp \ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -nogpulib \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 \ +// RUN: -mllvm -amdgpu-dump-hsa-metadata \ +// RUN: %s 2>&1 | FileCheck %s + +// RUN: %clang -### -target x86_64-pc-linux-gnu -fopenmp \ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -nogpulib \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 \ +// RUN: -mllvm -amdgpu-dump-hsa-metadata \ +// RUN: %s 2>&1 | FileCheck --check-prefix=DUP %s + +// CHECK: [[CLANG:".*clang.*"]] "-cc1" "-triple" "amdgcn-amd-amdhsa" +// CHECK-SAME: "-aux-triple" "x86_64-pc-linux-gnu" +// CHECK-SAME: "-emit-llvm-bc" {{.*}} "-target-cpu" "gfx906" +// CHECK-SAME: "-fopenmp" +// CHECK-SAME: "-mllvm" "-amdgpu-dump-hsa-metadata" +// DUP-NOT: "-mllvm" "-amdgpu-dump-hsa-metadata" "-mllvm" "-amdgpu-dump-hsa-metadata" +// CHECK-SAME: "-fopenmp-is-device" + +// CHECK: [[OPT:".*llc.*"]] {{".*-gfx906-optimized.*bc"}} "-mtriple=amdgcn-amd-amdhsa" +// CHECK-SAME: "-mcpu=gfx906" +// CHECK-SAME: "-amdgpu-dump-hsa-metadata" +// DUP-NOT: "-amdgpu-dump-hsa-metadata" "-amdgpu-dump-hsa-metadata" diff --git a/clang/test/Driver/amdgpu-debug.cl b/clang/test/Driver/amdgpu-debug.cl new file mode 100644 index 0000000000000..f10c20b05d18a --- /dev/null +++ b/clang/test/Driver/amdgpu-debug.cl @@ -0,0 +1,58 @@ +// Check that -ggdb implies the right options and is composable + +// Check for the expected effects of -g and -ggdb for AMDGCN +// RUN: %clang -### -target amdgcn-amd-amdhsa -x cl -c -nogpuinc -nogpulib -emit-llvm -g %s 2>&1 | FileCheck -check-prefix=CHECK-SIMPLE %s +// RUN: %clang -### -target amdgcn-amd-amdhsa -x cl -c -nogpuinc -nogpulib -emit-llvm -ggdb %s 2>&1 | FileCheck -check-prefix=CHECK-SIMPLE %s +// CHECK-SIMPLE: "-cc1" +// CHECK-SIMPLE-NOT: "-disable-O0-optnone" +// CHECK-SIMPLE-NOT: "-debug-info-kind=line-tables-only" +// CHECK-SIMPLE-DAG: "-mllvm" "-amdgpu-spill-cfi-saved-regs" +// CHECK-SIMPLE-DAG: "-gheterogeneous-dwarf=diexpression" +// CHECK-SIMPLE-DAG: "-debugger-tuning=gdb" +// CHECK-SIMPLE-NOT: "-disable-O0-optnone" +// CHECK-SIMPLE-NOT: "-debug-info-kind=line-tables-only" + +// Check that -gheterogeneous-dwarf is not enabled for AMDGCN when debug information is not enabled +// RUN: %clang -### -target amdgcn-amd-amdhsa -x cl -c -nogpuinc -nogpulib -emit-llvm %s 2>&1 | FileCheck -check-prefix=CHECK-NO-G %s +// CHECK-NO-G: "-cc1" +// CHECK-NO-G-NOT: "-amdgpu-spill-cfi-saved-regs" +// CHECK-NO-G-NOT: "-gheterogeneous-dwarf" + +// Check that -gheterogeneous-dwarf can be enabled for non-AMDGCN +// RUN: %clang -### -target x86_64-linux-gnu -x cl -c -nogpuinc -nogpulib -emit-llvm -gheterogeneous-dwarf %s 2>&1 | FileCheck -check-prefix=CHECK-EXPLICIT-HETEROGENEOUS %s +// CHECK-EXPLICIT-HETEROGENEOUS: "-cc1" +// CHECK-EXPLICIT-HETEROGENEOUS: "-gheterogeneous-dwarf=diexpression" + +// Check that -gheterogeneous-dwarf can be disabled for AMDGCN +// RUN: %clang -### -target amdgcn-amd-amdhsa -x cl -c -nogpuinc -nogpulib -emit-llvm -g -gno-heterogeneous-dwarf %s 2>&1 | FileCheck -check-prefix=CHECK-NO-HETEROGENEOUS %s +// CHECK-NO-HETEROGENEOUS: "-cc1" +// CHECK-NO-HETEROGENEOUS: "-gheterogeneous-dwarf=disabled" + +// Check that -gheterogeneous-dwarf= works for disabling +// RUN: %clang -### -target amdgcn-amd-amdhsa -x cl -c -nogpuinc -nogpulib -emit-llvm -g -gheterogeneous-dwarf=disabled %s 2>&1 | FileCheck -check-prefix=CHECK-DISABLED %s +// CHECK-DISABLED: "-cc1" +// CHECK-DISABLED: "-gheterogeneous-dwarf=disabled" + +// Check that -gheterogeneous-dwarf= works for diexpression +// RUN: %clang -### -target amdgcn-amd-amdhsa -x cl -c -nogpuinc -nogpulib -emit-llvm -g -gheterogeneous-dwarf=diexpression %s 2>&1 | FileCheck -check-prefix=CHECK-DIEXPRESSION %s +// CHECK-DIEXPRESSION: "-cc1" +// CHECK-DIEXPRESSION: "-gheterogeneous-dwarf=diexpression" + +// Check that -gheterogeneous-dwarf= fails for unknown option +// RUN: not %clang -target amdgcn-amd-amdhsa -x cl -c -nogpuinc -nogpulib -emit-llvm -g -gheterogeneous-dwarf=unknown %s 2>&1 | FileCheck -check-prefix=CHECK-UNKNOWN %s +// CHECK-UNKNOWN: error: invalid value + +// Specifically, check for failure with previously-valid value diexpr +// RUN: not %clang -target amdgcn-amd-amdhsa -x cl -c -nogpuinc -nogpulib -emit-llvm -g -gheterogeneous-dwarf=diexpr %s 2>&1 | FileCheck -check-prefix=CHECK-DIEXPR %s +// CHECK-DIEXPR: error: unsupported option '-gheterogeneous-dwarf=diexpr'; did you mean '-gheterogeneous-dwarf=diexpression'? + +// Check that =diexpression is implied by -g + spirv +// RUN: %clang -### -target spirv64-amd-amdhsa -x cl -c -nogpuinc -nogpulib -emit-llvm -g %s 2>&1 | FileCheck -check-prefix=CHECK-SPIRV %s +// CHECK-SPIRV: "-cc1" +// CHECK-SPIRV-DAG: "-mllvm" "-amdgpu-spill-cfi-saved-regs" +// CHECK-SPIRV-DAG: "-gheterogeneous-dwarf=diexpression" +// CHECK-SPIRV-DAG: "-debugger-tuning=gdb" + +// Check that =diexpr produces an error on spirv. +// RUN: not %clang -### -target spirv64-amd-amdhsa -x cl -c -nogpuinc -nogpulib -emit-llvm -g -gheterogeneous-dwarf=diexpr %s 2>&1 | FileCheck -check-prefix=CHECK-SPIRV-ERR %s +// CHECK-SPIRV-ERR: error: unsupported option '-gheterogeneous-dwarf=diexpr'; did you mean '-gheterogeneous-dwarf=diexpression'? diff --git a/clang/test/Driver/amdgpu-openmp-O0.c b/clang/test/Driver/amdgpu-openmp-O0.c new file mode 100644 index 0000000000000..d8c23680177c6 --- /dev/null +++ b/clang/test/Driver/amdgpu-openmp-O0.c @@ -0,0 +1,9 @@ +// REQUIRES: x86-registered-target +// REQUIRES: amdgpu-registered-target +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -nogpuinc -nogpulib -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -fno-openmp-target-new-runtime -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 -O0 %s 2>&1 \ +// RUN: | FileCheck %s + +// verify the tools invocations +// CHECK: clang{{.*}}"-cc1" "-triple" "x86_64-unknown-linux-gnu"{{.*}}"-x" "c"{{.*}} +// CHECK: clang{{.*}}"-cc1" "-triple" "x86_64-unknown-linux-gnu"{{.*}}"-x" "ir"{{.*}} +// CHECK-NOT: -O1 diff --git a/clang/test/Driver/amdgpu-openmp-toolchain-new.c b/clang/test/Driver/amdgpu-openmp-toolchain-new.c new file mode 100644 index 0000000000000..c6374b186d4d6 --- /dev/null +++ b/clang/test/Driver/amdgpu-openmp-toolchain-new.c @@ -0,0 +1,54 @@ +// REQUIRES: x86-registered-target +// DESIRES: amdgpu-registered-target +// REQUIRES: working-afar-ubuntu +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 --no-opaque-offload-linker --libomptarget-amdgpu-bc-path=%S/Inputs/hip_dev_lib %s 2>&1 \ +// RUN: | FileCheck %s +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa \ +// RUN: --offload-arch=gfx906 --no-opaque-offload-linker --libomptarget-amdgpu-bc-path=%S/Inputs/hip_dev_lib %s 2>&1 \ +// RUN: | FileCheck %s + +// verify the tools invocations +// CHECK: clang{{.*}}"-cc1" "-triple" "x86_64-unknown-linux-gnu" "-emit-llvm-bc"{{.*}}"-x" "c" +// CHECK: clang{{.*}}"-cc1" "-triple" "amdgcn-amd-amdhsa" "-aux-triple" "x86_64-unknown-linux-gnu"{{.*}}"-target-cpu" "gfx906"{{.*}}"-mlink-builtin-bitcode" +// CHECK: clang{{.*}}"-cc1" "-triple" "x86_64-unknown-linux-gnu" "-emit-obj" +// CHECK: clang-linker-wrapper{{.*}} "-o" "a.out" + +// RUN: %clang -ccc-print-phases --target=x86_64-unknown-linux-gnu -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa \ +// RUN: -march=gfx906 %s 2>&1 | FileCheck --check-prefix=CHECK-PHASES %s +// phases +// CHECK-PHASES: 0: input, "[[INPUT:.+]]", c, (host-openmp) +// CHECK-PHASES: 1: preprocessor, {0}, cpp-output, (host-openmp) +// CHECK-PHASES: 2: compiler, {1}, ir, (host-openmp) +// CHECK-PHASES: 3: input, "[[INPUT]]", c, (device-openmp, gfx906) +// CHECK-PHASES: 4: preprocessor, {3}, cpp-output, (device-openmp, gfx906) +// CHECK-PHASES: 5: compiler, {4}, ir, (device-openmp, gfx906) +// CHECK-PHASES: 6: offload, "host-openmp (x86_64-unknown-linux-gnu)" {2}, "device-openmp (amdgcn-amd-amdhsa:gfx906)" {5}, ir +// CHECK-PHASES: 7: backend, {6}, ir, (device-openmp, gfx906) +// CHECK-PHASES: 8: offload, "device-openmp (amdgcn-amd-amdhsa:gfx906)" {7}, ir +// CHECK-PHASES: 9: clang-offload-packager, {8}, image, (device-openmp) +// CHECK-PHASES: 10: offload, "host-openmp (x86_64-unknown-linux-gnu)" {2}, "device-openmp (x86_64-unknown-linux-gnu)" {9}, ir +// CHECK-PHASES: 11: backend, {10}, assembler, (host-openmp) +// CHECK-PHASES: 12: assembler, {11}, object, (host-openmp) +// CHECK-PHASES: 13: clang-linker-wrapper, {12}, image, (host-openmp) + +// handling of --libomptarget-amdgpu-bc-path +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx803 --libomptarget-amdgpu-bc-path=%S/Inputs/hip_dev_lib/libomptarget-amdgpu-gfx803.bc %s 2>&1 | FileCheck %s --check-prefix=CHECK-LIBOMPTARGET +// CHECK-LIBOMPTARGET: clang{{.*}}"-cc1"{{.*}}"-triple" "amdgcn-amd-amdhsa"{{.*}}"-target-cpu" "gfx803" + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx803 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOGPULIB +// CHECK-NOGPULIB-NOT: clang{{.*}}"-cc1"{{.*}}"-triple" "amdgcn-amd-amdhsa"{{.*}}"-target-cpu" "gfx803" "-mlink-builtin-bitcode"{{.*}}libomptarget-amdgpu-gfx803.bc"{{.*}} + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx803 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-BINDINGS +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa --offload-arch=gfx803 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-BINDINGS +// CHECK-BINDINGS: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[INPUT:.+]]"], output: "[[HOST_BC:.+]]" +// CHECK-BINDINGS: "amdgcn-amd-amdhsa" - "clang", inputs: ["[[INPUT]]", "[[HOST_BC]]"], output: "[[DEVICE_BC:.+]]" +// CHECK-BINDINGS: "x86_64-unknown-linux-gnu" - "Offload::Packager", inputs: ["[[DEVICE_BC]]"], output: "[[BINARY:.+]]" +// CHECK-BINDINGS: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[HOST_BC]]", "[[BINARY]]"], output: "[[HOST_OBJ:.+]]" +// CHECK-BINDINGS: "x86_64-unknown-linux-gnu" - "Offload::Linker", inputs: ["[[HOST_OBJ]]"], output: "a.out" + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -emit-llvm -S -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx803 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-EMIT-LLVM-IR +// CHECK-EMIT-LLVM-IR: clang{{.*}}"-cc1"{{.*}}"-triple" "amdgcn-amd-amdhsa"{{.*}}"-emit-llvm" + +// RUN: %clang -### -target x86_64-pc-linux-gnu -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx803 --no-opaque-offload-linker -lm --rocm-device-lib-path=%S/Inputs/rocm/amdgcn/bitcode %s 2>&1 | FileCheck %s --check-prefix=CHECK-LIB-DEVICE-NEW +// CHECK-LIB-DEVICE-NEW: {{.*}}"-target-cpu" "gfx803"{{.*}}ocml.bc"{{.*}}oclc_daz_opt_on.bc"{{.*}}oclc_unsafe_math_off.bc"{{.*}}oclc_finite_only_off.bc"{{.*}}oclc_correctly_rounded_sqrt_on.bc"{{.*}}oclc_wavefrontsize64_on.bc"{{.*}}oclc_isa_version_803.bc" diff --git a/clang/test/Driver/amdllvm_error.c b/clang/test/Driver/amdllvm_error.c new file mode 100644 index 0000000000000..5c3b66513a541 --- /dev/null +++ b/clang/test/Driver/amdllvm_error.c @@ -0,0 +1,11 @@ +// REQUIRES: shell, amdclang +// UNSUPPORTED: system-windows +// RUN: rm -rf %t +// RUN: mkdir -p %t +// RUN: ln -s amdclang %t/amdfoo +// RUN: not %t/amdfoo 2>&1 | FileCheck %s --check-prefix=DOES_NOT_EXIST +// RUN: ln -s amdclang %t/foo +// RUN: not %t/foo 2>&1 | FileCheck %s --check-prefix=BAD_PREFIX +// +// DOES_NOT_EXIST: binary '{{.*}}' does not exist +// BAD_PREFIX: binary '{{.*}}' not prefixed by 'amd' diff --git a/clang/test/Driver/amdllvm_link_version.c b/clang/test/Driver/amdllvm_link_version.c new file mode 100644 index 0000000000000..7c9f825c24bbb --- /dev/null +++ b/clang/test/Driver/amdllvm_link_version.c @@ -0,0 +1,10 @@ +// REQUIRES: shell, amdclang +// UNSUPPORTED: system-windows +// +// clang and links to amdclang are the same +// RUN: rm -rf %t +// RUN: mkdir -p %t +// RUN: %clang --version 2>&1 > %t.clang.version +// RUN: ln -s amdclang %t/amdclang +// RUN: %t/amdclang --version 2>&1 > %t.amdclang.version +// RUN: diff %t.clang.version %t.amdclang.version diff --git a/clang/test/Driver/amdllvm_version.c b/clang/test/Driver/amdllvm_version.c new file mode 100644 index 0000000000000..33c7dc23058ae --- /dev/null +++ b/clang/test/Driver/amdllvm_version.c @@ -0,0 +1,6 @@ +// REQUIRES: amdclang +// +// clang and amdclang are the same +// RUN: %clang --version 2>&1 > %t.clang.version +// RUN: amdclang --version 2>&1 > %t.amdclang.version +// RUN: diff %t.clang.version %t.amdclang.version diff --git a/clang/test/Driver/android-installed-libcxx.cpp b/clang/test/Driver/android-installed-libcxx.cpp index 14856e26e2730..7f7f41693e2f8 100644 --- a/clang/test/Driver/android-installed-libcxx.cpp +++ b/clang/test/Driver/android-installed-libcxx.cpp @@ -1,5 +1,6 @@ // Check that we only find libc++ in the installation directory when it contains // an Android-specific include directory. +// XFAIL: * // RUN: mkdir -p %t1/bin // RUN: mkdir -p %t1/include/c++/v1 diff --git a/clang/test/Driver/android-no-installed-libcxx.cpp b/clang/test/Driver/android-no-installed-libcxx.cpp new file mode 100644 index 0000000000000..bfddc1cf197dd --- /dev/null +++ b/clang/test/Driver/android-no-installed-libcxx.cpp @@ -0,0 +1,13 @@ +// Flang driver changes break this test, -o multiple obj error +// XFAIL: * + +// Check that we don't find the libc++ in the installation directory when +// targeting Android. + +// RUN: mkdir -p %t/bin +// RUN: mkdir -p %t/include/c++/v1 +// RUN: mkdir -p %t/sysroot +// RUN: %clang -target aarch64-linux-android -ccc-install-dir %t/bin \ +// RUN: --sysroot=%t/sysroot -stdlib=libc++ -fsyntax-only \ +// RUN: %s -### 2>&1 | FileCheck %s +// CHECK-NOT: "-internal-isystem" "{{.*}}v1" diff --git a/clang/test/Driver/android-unversioned-fallback-warning.cpp b/clang/test/Driver/android-unversioned-fallback-warning.cpp index da666cc4d9faf..2ebc96b8c7338 100644 --- a/clang/test/Driver/android-unversioned-fallback-warning.cpp +++ b/clang/test/Driver/android-unversioned-fallback-warning.cpp @@ -1,6 +1,8 @@ // Check that we emit warnings for using unversioned Android target directories // as appropriate. +// XFAIL: * + // RUN: mkdir -p %t/bin // RUN: mkdir -p %t/include/aarch64-none-linux-android/c++/v1 // RUN: mkdir -p %t/include/aarch64-none-linux-android23/c++/v1 diff --git a/clang/test/Driver/cl-offload.cu b/clang/test/Driver/cl-offload.cu index b05bf3b97b7eb..8bd1a3ff56e6c 100644 --- a/clang/test/Driver/cl-offload.cu +++ b/clang/test/Driver/cl-offload.cu @@ -11,6 +11,8 @@ // RUN: --rocm-path=%S/Inputs/rocm /Wall -x hip -- %s 2>&1 \ // RUN: | FileCheck %s -check-prefix=HIP +// REQUIRES: windows + // CUDA: "-cc1" "-triple" "nvptx64-nvidia-cuda" "-aux-triple" "x86_64-pc-windows-msvc" // CUDA-SAME: "-Weverything" // CUDA: ptxas diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c index 89526744c0a49..490b7247e9a92 100644 --- a/clang/test/Driver/cl-x86-flags.c +++ b/clang/test/Driver/cl-x86-flags.c @@ -8,6 +8,7 @@ // RUN: --target=i386-pc-win32 -### -- 2>&1 %s | FileCheck -check-prefix=MFLAGS %s // MFLAGS-NOT: invalid /arch: argument // +// REQUIRES: stability // RUN: %clang_cl -m32 -arch:IA32 --target=i386-pc-windows /c /Fo%t.obj -Xclang -verify -DTEST_32_ARCH_IA32 -- %s #if defined(TEST_32_ARCH_IA32) diff --git a/clang/test/Driver/clang-offload-wrapper.c b/clang/test/Driver/clang-offload-wrapper.c new file mode 100644 index 0000000000000..4ea3a69927fa7 --- /dev/null +++ b/clang/test/Driver/clang-offload-wrapper.c @@ -0,0 +1,81 @@ +// REQUIRES: x86-registered-target +// REQUIRES: amdgpu-registered-target + +// +// Check help message. +// +// RUN: clang-offload-wrapper --help | FileCheck %s --check-prefix CHECK-HELP +// CHECK-HELP: {{.*}}OVERVIEW: A tool to create a wrapper bitcode for offload target binaries. Takes offload +// CHECK-HELP: {{.*}}target binaries as input and produces bitcode file containing target binaries packaged +// CHECK-HELP: {{.*}}as data and initialization code which registers target binaries in offload runtime. +// CHECK-HELP: {{.*}}USAGE: clang-offload-wrapper [options] +// CHECK-HELP: {{.*}} --aux-triple= - Target triple for the output module +// CHECK-HELP: {{.*}} -o - Output filename +// CHECK-HELP: {{.*}} --target= - Target triple for input files + +// +// Generate a file to wrap. +// +// RUN: echo 'Content of device file' > %t.tgt + +// +// Check bitcode produced by the wrapper tool. +// +// RUN: clang-offload-wrapper -add-omp-offload-notes -target=amdgcn-amd-amdhsa -aux-triple=x86_64-pc-linux-gnu -o %t.wrapper.bc %t.tgt 2>&1 | FileCheck %s --check-prefix ELF-WARNING +// RUN: llvm-dis %t.wrapper.bc -o - | FileCheck %s --check-prefix CHECK-IR + +// ELF-WARNING: is not an ELF image, so notes cannot be added to it. +// CHECK-IR: target triple = "x86_64-pc-linux-gnu" + +// CHECK-IR-DAG: [[ENTTY:%.+]] = type { i64, i16, i16, i32, ptr, ptr, i64, i64, ptr } +// CHECK-IR-DAG: [[IMAGETY:%.+]] = type { ptr, ptr, ptr, ptr } +// CHECK-IR-DAG: [[DESCTY:%.+]] = type { i32, ptr, ptr, ptr } +// +// CHECK-IR: [[ENTBEGIN:@.+]] = external hidden constant [0 x [[ENTTY]]] +// CHECK-IR: [[ENTEND:@.+]] = external hidden constant [0 x [[ENTTY]]] +// CHECK-IR: [[DUMMY:@.+]] = internal constant [0 x [[ENTTY]]] zeroinitializer, section "llvm_offload_entries", align 8 +// CHECK-IR: @llvm.compiler.used = appending global [1 x ptr] [ptr [[DUMMY]]], section "llvm.metadata" + +// CHECK-IR: [[BIN:@.+]] = internal unnamed_addr constant [[[SIZE:[0-9]+]] x i8] c"\10\FF\10\AD{{.*}}" + ffloading.device_image = internal unnamed_addr constant [[[SIZE]] x i8] c"\10\FF\10\AD\01\00\00\0 +// CHECK-IR: [[IMAGES:@.+]] = internal unnamed_addr constant [1 x %__tgt_device_image] [%__tgt_device_image { ptr getelementptr ([[[SIZE]] x i8], ptr [[BIN]], i64 0, i64 136), ptr getelementptr ([[[SIZE]] x i8], ptr [[BIN]], i64 0, i64 159), ptr [[ENTBEGIN]], ptr [[ENTEND]] }] +// CHECK-IR: [[DESC:@.+]] = internal constant [[DESCTY]] { i32 1, ptr [[IMAGES]], ptr [[ENTBEGIN]], ptr [[ENTEND]] } +// CHECK-IR: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 101, ptr [[REGFN:@.+]], ptr null }] + +// CHECK-IR: define internal void [[REGFN]]() section ".text.startup" { +// CHECK-IR: call void @__tgt_register_lib(ptr [[DESC]]) +// CHECK-IR: %0 = call i32 @atexit(ptr @.omp_offloading.descriptor_unreg) +// CHECK-IR: ret void +// CHECK-IR: } + +// CHECK-IR: declare void @__tgt_register_lib(ptr) + +// CHECK-IR: declare i32 @atexit(ptr) + +// CHECK-IR: define internal void [[DESC]]_unreg() section ".text.startup" { +// CHECK-IR: call void @__tgt_unregister_lib(ptr [[DESC]]) +// CHECK-IR: ret void +// CHECK-IR: } + +// CHECK_IR: declare void @__tgt_unregister_lib(ptr) + +// Check that clang-offload-wrapper adds LLVMOMPOFFLOAD notes +// into the ELF offload images: +// RUN: yaml2obj %S/Inputs/empty-elf-template.yaml -o %t.64le -DBITS=64 -DENCODING=LSB +// RUN: clang-offload-wrapper -add-omp-offload-notes -target=amdgcn-amd-amdhsa -aux-triple=x86_64-pc-linux-gnu -o %t.wrapper.elf64le.bc %t.64le +// RUN: llvm-dis %t.wrapper.elf64le.bc -o - | FileCheck %s --check-prefix OMPNOTES +// RUN: yaml2obj %S/Inputs/empty-elf-template.yaml -o %t.64be -DBITS=64 -DENCODING=MSB +// RUN: clang-offload-wrapper -add-omp-offload-notes -target=amdgcn-amd-amdhsa -aux-triple=x86_64-pc-linux-gnu -o %t.wrapper.elf64be.bc %t.64be +// RUN: llvm-dis %t.wrapper.elf64be.bc -o - | FileCheck %s --check-prefix OMPNOTES +// RUN: yaml2obj %S/Inputs/empty-elf-template.yaml -o %t.32le -DBITS=32 -DENCODING=LSB +// RUN: clang-offload-wrapper -add-omp-offload-notes -target=amdgcn-amd-amdhsa -aux-triple=x86_64-pc-linux-gnu -o %t.wrapper.elf32le.bc %t.32le +// RUN: llvm-dis %t.wrapper.elf32le.bc -o - | FileCheck %s --check-prefix OMPNOTES +// RUN: yaml2obj %S/Inputs/empty-elf-template.yaml -o %t.32be -DBITS=32 -DENCODING=MSB +// RUN: clang-offload-wrapper -add-omp-offload-notes -target=amdgcn-amd-amdhsa -aux-triple=x86_64-pc-linux-gnu -o %t.wrapper.elf32be.bc %t.32be +// RUN: llvm-dis %t.wrapper.elf32be.bc -o - | FileCheck %s --check-prefix OMPNOTES + +// There is no clean way for extracting the offload image +// from the object file currently, so try to find +// the inserted ELF notes in the device image variable's +// initializer: +// OMPNOTES: @{{.+}} = internal unnamed_addr constant [{{[0-9]+}} x i8] c"{{.*}}LLVMOMPOFFLOAD{{.*}}LLVMOMPOFFLOAD{{.*}}LLVMOMPOFFLOAD{{.*}}" diff --git a/clang/test/Driver/clang_f_opts.c b/clang/test/Driver/clang_f_opts.c index 765f9d6ae3212..3bb0bcc9f70d9 100644 --- a/clang/test/Driver/clang_f_opts.c +++ b/clang/test/Driver/clang_f_opts.c @@ -624,10 +624,6 @@ // RUN: %clang -### --target=aarch64-windows-msvc %s 2>&1 | FileCheck -check-prefix=CHECK-NO-MS-VOLATILE %s // RUN: %clang -### --target=aarch64-windows-msvc -fms-volatile %s 2>&1 | FileCheck -check-prefix=CHECK-MS-VOLATILE %s // RUN: %clang -### --target=aarch64-windows-msvc -fno-ms-volatile %s 2>&1 | FileCheck -check-prefix=CHECK-NO-MS-VOLATILE %s -// RUN: %clang -### --target=x86_64-windows-msvc %s 2>&1 | FileCheck -check-prefix=CHECK-MS-VOLATILE %s -// RUN: %clang -### --target=x86_64-windows-msvc -fno-ms-volatile %s 2>&1 | FileCheck -check-prefix=CHECK-NO-MS-VOLATILE %s -// RUN: %clang -### --target=i686-windows-msvc %s 2>&1 | FileCheck -check-prefix=CHECK-MS-VOLATILE %s -// RUN: %clang -### --target=i686-windows-msvc -fno-ms-volatile %s 2>&1 | FileCheck -check-prefix=CHECK-NO-MS-VOLATILE %s // CHECK-MS-VOLATILE: -fms-volatile // CHECK-NO-MS-VOLATILE-NOT: -fms-volatile diff --git a/clang/test/Driver/cuda-bindings.cu b/clang/test/Driver/cuda-bindings.cu index 5b6f944621439..5e7530cbe673c 100644 --- a/clang/test/Driver/cuda-bindings.cu +++ b/clang/test/Driver/cuda-bindings.cu @@ -5,6 +5,7 @@ // - User-requested final phase - binary or assembly. // It parallels cuda-phases.cu test, but verifies whether output file is temporary or not. + // It's hard to check whether file name is temporary in a portable // way. Instead we check whether we've generated a permanent name on // device side, which appends '-device-cuda-' suffix. diff --git a/clang/test/Driver/cuda-version-check.cu b/clang/test/Driver/cuda-version-check.cu index 9eceb928ffabd..7d421545ad172 100644 --- a/clang/test/Driver/cuda-version-check.cu +++ b/clang/test/Driver/cuda-version-check.cu @@ -76,5 +76,5 @@ // RUN: FileCheck %s --check-prefix=VERSION // RUN: %clang --target=nvptx64-nvidia-cuda -v -### -nogpulib -march=sm_60 --cuda-path=%S/Inputs/CUDA-new/usr/local/cuda 2>&1 -x c %s | \ // RUN: FileCheck %s --check-prefix=VERSION -// VERSION-NOT: CUDA version is newer than the latest{{.*}} supported version +// VERSION-NOT: CUDA version is newer than the latest diff --git a/clang/test/Driver/femit-dwarf-unwind.c b/clang/test/Driver/femit-dwarf-unwind.c index 89e733462c2c9..e6d04c81b25b8 100644 --- a/clang/test/Driver/femit-dwarf-unwind.c +++ b/clang/test/Driver/femit-dwarf-unwind.c @@ -1,5 +1,4 @@ // REQUIRES: x86-registered-target - // RUN: rm -rf %t; mkdir %t // RUN: %clang -target x86_64-apple-macos11.0 -c %s -o %t/x86_64.o -femit-compact-unwind-non-canonical // RUN: %clang -target x86_64-apple-macos11.0 -femit-dwarf-unwind=no-compact-unwind -femit-compact-unwind-non-canonical -c %s -o %t/x86_64-no-dwarf.o diff --git a/clang/test/Driver/flang/flang.f90 b/clang/test/Driver/flang/flang.f90 index b52977ee66d7b..2fce124d0d044 100644 --- a/clang/test/Driver/flang/flang.f90 +++ b/clang/test/Driver/flang/flang.f90 @@ -1,5 +1,8 @@ ! Check that flang -fc1 is invoked when in --driver-mode=flang. +! AOCC team xfails this test as its thought to be f18. +! UNSUPPORTED + ! This is a copy of flang_ucase.F90 because the driver has logic in it which ! differentiates between F90 and f90 files. Flang will not treat these files ! differently. diff --git a/clang/test/Driver/flang/flang_ucase.F90 b/clang/test/Driver/flang/flang_ucase.F90 index 88aedc39fb94a..37c4912475052 100644 --- a/clang/test/Driver/flang/flang_ucase.F90 +++ b/clang/test/Driver/flang/flang_ucase.F90 @@ -1,5 +1,8 @@ ! Check that flang -fc1 is invoked when in --driver-mode=flang. +! AOCC team xfails this test as its thought to be f18. +! UNSUPPORTED + ! This is a copy of flang.f90 because the driver has logic in it which ! differentiates between F90 and f90 files. Flang will not treat these files ! differently. diff --git a/clang/test/Driver/flang/multiple-inputs-mixed.f90 b/clang/test/Driver/flang/multiple-inputs-mixed.f90 index 98d8cab00bdfd..7023991b4f3c9 100644 --- a/clang/test/Driver/flang/multiple-inputs-mixed.f90 +++ b/clang/test/Driver/flang/multiple-inputs-mixed.f90 @@ -1,5 +1,8 @@ ! Check that flang can handle mixed C and fortran inputs. +! AOCC team xfails this test as its thought to be f18. +! UNSUPPORTED + ! RUN: %clang --driver-mode=flang -### -fsyntax-only %S/Inputs/one.f90 %S/Inputs/other.c 2>&1 | FileCheck --check-prefixes=CHECK-SYNTAX-ONLY %s ! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang{{[^"/]*}}" "-fc1" ! CHECK-SYNTAX-ONLY: "{{[^"]*}}/Inputs/one.f90" diff --git a/clang/test/Driver/flang/multiple-inputs.f90 b/clang/test/Driver/flang/multiple-inputs.f90 index 3c0f22e5d3e50..9ec0ea03ab503 100644 --- a/clang/test/Driver/flang/multiple-inputs.f90 +++ b/clang/test/Driver/flang/multiple-inputs.f90 @@ -1,5 +1,8 @@ ! Check that flang driver can handle multiple inputs at once. +! AOCC team xfails this test as its thought to be f18. +! UNSUPPORTED + ! RUN: %clang --driver-mode=flang -### -fsyntax-only %S/Inputs/one.f90 %S/Inputs/two.f90 2>&1 | FileCheck --check-prefixes=CHECK-SYNTAX-ONLY %s ! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang{{[^"/]*}}" "-fc1" ! CHECK-SYNTAX-ONLY: "{{[^"]*}}/Inputs/one.f90" diff --git a/clang/test/Driver/gfortran.f90 b/clang/test/Driver/gfortran.f90 index c985428650ecd..0f26b5b63496d 100644 --- a/clang/test/Driver/gfortran.f90 +++ b/clang/test/Driver/gfortran.f90 @@ -3,7 +3,12 @@ ! being supported by gfortran to GCC when falling back to GCC for ! a fortran input file. ! -! RUN: %clang --target=i386-linux -### %s 2>&1 \ +! AOCC team xfails this test as its thought to be f18. + +! XFAIL: * +! UNSUPPORTED + +! RUN: %clang --target i386-linux -### %s -o %t 2>&1 \ ! RUN: -Aquestion=answer \ ! RUN: -A-question=answer \ ! RUN: -C \ diff --git a/clang/test/Driver/hip-debug.hip b/clang/test/Driver/hip-debug.hip new file mode 100644 index 0000000000000..a5a5e2695479a --- /dev/null +++ b/clang/test/Driver/hip-debug.hip @@ -0,0 +1,42 @@ +// REQUIRES: clang-driver +// REQUIRES: x86-registered-target +// REQUIRES: amdgpu-registered-target + +// Check that -g correctly differentiates device/host code, and that the +// -amdgpu-spill-cfi-saved-regs and -gheterogeneous-dwarf options are +// supplied during actual code-gen (i.e. in the llc command-line for the +// device in the normal case, and the lld command-line in the RDC case). + +// RUN: %clang -### -target x86_64-unknown-linux-gnu -nogpulib -g \ +// RUN: -x hip --cuda-gpu-arch=gfx900 %s 2>&1 | \ +// RUN: FileCheck -check-prefixes=DEFAULT %s + +// DEFAULT: {{.*}}clang{{.*}}"-triple" "amdgcn-amd-amdhsa" +// DEFAULT-NOT: "-disable-O0-optnone" +// DEFAULT-NOT: "-debug-info-kind=line-tables-only" +// DEFAULT-DAG: "-debug-info-kind=constructor" +// DEFAULT-DAG: "-debugger-tuning=gdb" +// DEFAULT-DAG: "-mllvm" "-amdgpu-spill-cfi-saved-regs" +// DEFAULT-DAG: "-gheterogeneous-dwarf" +// DEFAULT-NOT: "-disable-O0-optnone" +// DEFAULT-NOT: "-debug-info-kind=line-tables-only" +// DEFAULT-LABEL: clang-offload-bundler +// DEFAULT: {{.*}}clang{{.*}}"-triple" "x86_64-unknown-linux-gnu" +// DEFAULT-NOT: "-disable-O0-optnone" +// DEFAULT-NOT: "-debug-info-kind=line-tables-only" +// DEFAULT-NOT: "-amdgpu-spill-cfi-saved-regs" +// DEFAULT-NOT: "-gheterogeneous-dwarf" +// DEFAULT-DAG: "-debug-info-kind=constructor" +// DEFAULT-DAG: "-debugger-tuning=gdb" +// DEFAULT-NOT: "-disable-O0-optnone" +// DEFAULT-NOT: "-debug-info-kind=line-tables-only" +// DEFAULT-NOT: "-amdgpu-spill-cfi-saved-regs" +// DEFAULT-NOT: "-gheterogeneous-dwarf" + +// RUN: %clang -### -target x86_64-unknown-linux-gnu -nogpulib -g \ +// RUN: -x hip --cuda-gpu-arch=gfx900 -fgpu-rdc %s 2>&1 | \ +// RUN: FileCheck -check-prefixes=RDC %s + +// RDC: {{.*}}lld{{.*}} "-plugin-opt=mcpu=gfx900" +// RDC-SAME: "-plugin-opt=-amdgpu-spill-cfi-saved-regs" +// RDC-NOT: "-plugin-opt=-gheterogeneous-dwarf" diff --git a/clang/test/Driver/hip-device-libs.hip b/clang/test/Driver/hip-device-libs.hip index effce40d67ebd..b39b1a4c3a92e 100644 --- a/clang/test/Driver/hip-device-libs.hip +++ b/clang/test/Driver/hip-device-libs.hip @@ -159,12 +159,11 @@ // RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \ // RUN: 2>&1 | FileCheck %s --check-prefixes=ABI6 -// Test default code object version with old device library without abi_version_400.bc -// RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ -// RUN: -mcode-object-version=4 \ -// RUN: --hip-device-lib-path=%S/Inputs/rocm/amdgcn/bitcode-no-abi-ver \ +// Test default code object version with old device library without abi_version_500.bc +// RUN: not %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ +// RUN: --hip-device-lib-path=%S/Inputs/rocm/amdgcn/bitcode-no-abi-ver \ // RUN: --rocm-path=%S/Inputs/rocm %S/Inputs/hip_multiple_inputs/b.hip \ -// RUN: 2>&1 | FileCheck %s --check-prefixes=NOABI4 +// RUN: 2>&1 | FileCheck %s --check-prefixes=NOABI6 // Test -mcode-object-version=4 // RUN: %clang -### --target=x86_64-linux-gnu --offload-arch=gfx900 \ diff --git a/clang/test/Driver/hip-link-bundle-archive.hip b/clang/test/Driver/hip-link-bundle-archive.hip index 6606e19790a52..96b8eb12f1452 100644 --- a/clang/test/Driver/hip-link-bundle-archive.hip +++ b/clang/test/Driver/hip-link-bundle-archive.hip @@ -3,13 +3,15 @@ // value of the '-l' option, it should not interfere with // the discovery and unbundling of the archive. -// RUN: rm -rf %t hipBundled && mkdir %t hipBundled +// RUN: rm -rf %t && mkdir %t // RUN: touch %t/dummy.bc +// RUN: mkdir -p hipBundled // RUN: llvm-ar cr %t/libhipBundled.a %t/dummy.bc // RUN: %clang -### --offload-arch=gfx906 --offload-arch=gfx1030 \ // RUN: --no-offload-new-driver --target=x86_64-unknown-linux-gnu \ // RUN: -nogpuinc -nogpulib %s -fgpu-rdc -L%t -lhipBundled \ // RUN: 2>&1 | FileCheck -check-prefixes=GNU,GNU1,GNU-L %s +// RUN: rm -rf hipBundled // RUN: %clang -### --offload-arch=gfx906 --offload-arch=gfx1030 -nogpuinc \ // RUN: --no-offload-new-driver --target=x86_64-unknown-linux-gnu \ diff --git a/clang/test/Driver/hip-phases.hip b/clang/test/Driver/hip-phases.hip index 13f682f18a3ab..f2a84f48fe22d 100644 --- a/clang/test/Driver/hip-phases.hip +++ b/clang/test/Driver/hip-phases.hip @@ -649,9 +649,9 @@ // // Test the bindings using the new driver in LTO-mode. // -// RUN: %clang -### --target=x86_64-linux-gnu --offload-new-driver -ccc-print-phases \ -// RUN: --offload-arch=gfx90a --offload-arch=gfx908 -foffload-lto -fgpu-rdc -c %s 2>&1 \ -// RUN: | FileCheck -check-prefix=LTO %s +// R-UN: %clang -### --target=x86_64-linux-gnu --offload-new-driver -ccc-print-phases \ +// R-UN: --offload-arch=gfx90a --offload-arch=gfx908 -foffload-lto -fgpu-rdc -c %s 2>&1 \ +// R-UN: | FileCheck -check-prefix=LTO %s // LTO: 0: input, "[[INPUT:.+]]", hip, (host-hip) // LTO-NEXT: 1: preprocessor, {0}, hip-cpp-output, (host-hip) // LTO-NEXT: 2: compiler, {1}, ir, (host-hip) diff --git a/clang/test/Driver/hip-target-id.hip b/clang/test/Driver/hip-target-id.hip index fee430fe08c8d..50a9fea0a3b0d 100644 --- a/clang/test/Driver/hip-target-id.hip +++ b/clang/test/Driver/hip-target-id.hip @@ -26,7 +26,7 @@ // CHECK-SAME: "-target-feature" "+sramecc" // CHECK-SAME: "-target-feature" "+xnack" -// TMP: [[CLANG:"[^"]*clang[^"]*"]] "-cc1as" "-triple" "amdgcn-amd-amdhsa" +// TMP: [[CLANG_TMP:"[^"]*clang"]] "-cc1as" "-triple" "amdgcn-amd-amdhsa" // TMP-SAME: "-target-cpu" "gfx908" // TMP-SAME: "-target-feature" "+sramecc" // TMP-SAME: "-target-feature" "+xnack" diff --git a/clang/test/Driver/hip-toolchain-device-only.hip b/clang/test/Driver/hip-toolchain-device-only.hip index 12097819f6688..8c696669a5e4f 100644 --- a/clang/test/Driver/hip-toolchain-device-only.hip +++ b/clang/test/Driver/hip-toolchain-device-only.hip @@ -5,7 +5,7 @@ // CHECK-NOT: error: -// CHECK: [[CLANG:".*clang.*"]] "-cc1"{{.*}} "-triple" "amdgcn-amd-amdhsa" +// CHECK: [[CLANG:".*clang.*"]] "-cc1" "-triple" "amdgcn-amd-amdhsa" // CHECK-SAME: "-fcuda-is-device" // CHECK-SAME: "-target-cpu" "gfx803" // CHECK-SAME: {{.*}} "-o" [[OBJ_DEV_A_803:".*o"]] "-x" "hip" @@ -13,7 +13,7 @@ // CHECK: [[LLD: ".*lld.*"]] "-flavor" "gnu" "-m" "elf64_amdgpu" "--no-undefined" "-shared" // CHECK-SAME: "-o" "[[IMG_DEV_A_803:.*out]]" [[OBJ_DEV_A_803]] -// CHECK: [[CLANG:".*clang.*"]] "-cc1"{{.*}} "-triple" "amdgcn-amd-amdhsa" +// CHECK: [[CLANG:".*clang.*"]] "-cc1" "-triple" "amdgcn-amd-amdhsa" // CHECK-SAME: "-emit-obj" // CHECK-SAME: "-fcuda-is-device" // CHECK-SAME: "-target-cpu" "gfx900" diff --git a/clang/test/Driver/linux-header-search.cpp b/clang/test/Driver/linux-header-search.cpp index 70a85deac89e4..ddd85db7e5b7f 100644 --- a/clang/test/Driver/linux-header-search.cpp +++ b/clang/test/Driver/linux-header-search.cpp @@ -1,3 +1,5 @@ +// XFAIL: * + // General tests that the header search paths detected by the driver and passed // to CC1 are sane. // diff --git a/clang/test/Driver/ohos.c b/clang/test/Driver/ohos.c index 21416622471c2..cbe3789ec550e 100644 --- a/clang/test/Driver/ohos.c +++ b/clang/test/Driver/ohos.c @@ -65,7 +65,6 @@ // RUN: | FileCheck %s -check-prefix=CHECK-RUNTIME // RUN: %clang %s -### --target=x86_64-linux-ohos -fuse-ld=ld 2>&1 \ // RUN: | FileCheck %s -check-prefix=CHECK-RUNTIME -// CHECK-RUNTIME: "{{.*}}libclang_rt.builtins.a" // CHECK-RUNTIME: "-l:libunwind.a" // CHECK-LIBM: "-lm" diff --git a/clang/test/Driver/openmp-invalid-target-id.c b/clang/test/Driver/openmp-invalid-target-id.c new file mode 100644 index 0000000000000..9a834857c1579 --- /dev/null +++ b/clang/test/Driver/openmp-invalid-target-id.c @@ -0,0 +1,135 @@ +// REQUIRES: clang-driver +// REQUIRES: x86-registered-target +// REQUIRES: amdgpu-registered-target + +// +// Legacy mode (-fopenmp-targets,-Xopenmp-target,-march) tests for TargetID +// +// RUN: not %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908xnack \ +// RUN: %s 2>&1 | FileCheck -check-prefix=NOPLUS-L %s + +// NOPLUS-L: error: invalid target ID 'gfx908xnack' + +// RUN: not %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx900 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908:xnack+:xnack+ \ +// RUN: %s 2>&1 | FileCheck -check-prefix=ORDER-L %s + +// ORDER-L: error: invalid target ID 'gfx908:xnack+:xnack+' + +// RUN: not %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa,amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908:unknown+ \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908+sramecc+unknown \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx900+xnack \ +// RUN: %s 2>&1 | FileCheck -check-prefix=UNK-L %s + +// UNK-L: error: invalid target ID 'gfx908:unknown+' + +// RUN: not %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908:sramecc+:unknown+ \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx900+xnack \ +// RUN: %s 2>&1 | FileCheck -check-prefix=MIXED-L %s + +// MIXED-L: error: invalid target ID 'gfx908:sramecc+:unknown+' + +// RUN: not %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx900:sramecc+ \ +// RUN: %s 2>&1 | FileCheck -check-prefix=UNSUP-L %s + +// UNSUP-L: error: invalid target ID 'gfx900:sramecc+' + +// RUN: not %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx900:xnack \ +// RUN: %s 2>&1 | FileCheck -check-prefix=NOSIGN-L %s + +// NOSIGN-L: error: invalid target ID 'gfx900:xnack' + +// RUN: not %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx900+xnack \ +// RUN: %s 2>&1 | FileCheck -check-prefix=NOCOLON-L %s + +// NOCOLON-L: error: invalid target ID 'gfx900+xnack' + +// RUN: not %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908:xnack+ \ +// RUN: %s 2>&1 | FileCheck -check-prefix=COMBO-L %s + +// COMBO-L: error: invalid offload arch combinations: 'gfx908' and 'gfx908:xnack+' + +// +// Offload-arch mode (--offload-arch) tests for TargetID +// +// RUN: not %clang -### -target x86_64-linux-gnu \ +// RUN: -fopenmp --offload-arch=gfx908 \ +// RUN: --offload-arch=gfx908xnack \ +// RUN: %s 2>&1 | FileCheck -check-prefix=NOPLUS %s + +// NOPLUS: error: invalid target ID 'gfx908xnack' + +// RUN: not %clang -### -target x86_64-linux-gnu \ +// RUN: -fopenmp --offload-arch=gfx900 \ +// RUN: --offload-arch=gfx908:xnack+:xnack+ \ +// RUN: %s 2>&1 | FileCheck -check-prefix=ORDER %s + +// ORDER: error: invalid target ID 'gfx908:xnack+:xnack+' + +// RUN: not %clang -### -target x86_64-linux-gnu \ +// RUN: -fopenmp --offload-arch=gfx908 \ +// RUN: --offload-arch=gfx908:unknown+ \ +// RUN: --offload-arch=gfx908+sramecc+unknown \ +// RUN: --offload-arch=gfx900+xnack \ +// RUN: %s 2>&1 | FileCheck -check-prefix=UNK %s + +// UNK: error: invalid target ID 'gfx908:unknown+' + +// RUN: not %clang -### -target x86_64-linux-gnu \ +// RUN: -fopenmp --offload-arch=gfx908 \ +// RUN: --offload-arch=gfx908:sramecc+:unknown+ \ +// RUN: --offload-arch=gfx900+xnack \ +// RUN: %s 2>&1 | FileCheck -check-prefix=MIXED %s + +// MIXED: error: invalid target ID 'gfx908:sramecc+:unknown+' + +// RUN: not %clang -### -target x86_64-linux-gnu \ +// RUN: -fopenmp --offload-arch=gfx908 \ +// RUN: --offload-arch=gfx900:sramecc+ \ +// RUN: %s 2>&1 | FileCheck -check-prefix=UNSUP %s + +// UNSUP: error: invalid target ID 'gfx900:sramecc+' + +// RUN: not %clang -### -target x86_64-linux-gnu \ +// RUN: -fopenmp --offload-arch=gfx908 \ +// RUN: --offload-arch=gfx900:xnack \ +// RUN: %s 2>&1 | FileCheck -check-prefix=NOSIGN %s + +// NOSIGN: error: invalid target ID 'gfx900:xnack' + +// RUN: not %clang -### -target x86_64-linux-gnu \ +// RUN: -fopenmp --offload-arch=gfx908 \ +// RUN: --offload-arch=gfx900+xnack \ +// RUN: %s 2>&1 | FileCheck -check-prefix=NOCOLON %s + +// NOCOLON: error: invalid target ID 'gfx900+xnack' + +// RUN: not %clang -### -target x86_64-linux-gnu \ +// RUN: -fopenmp --offload-arch=gfx908 \ +// RUN: --offload-arch=gfx908:xnack+ \ +// RUN: %s 2>&1 | FileCheck -check-prefix=COMBO %s + +// COMBO: error: invalid offload arch combinations: 'gfx908' and 'gfx908:xnack+' diff --git a/clang/test/Driver/openmp-offload-fnoopenmp.c b/clang/test/Driver/openmp-offload-fnoopenmp.c new file mode 100644 index 0000000000000..0773b4e513db2 --- /dev/null +++ b/clang/test/Driver/openmp-offload-fnoopenmp.c @@ -0,0 +1,40 @@ +// REQUIRES: clang-driver +// REQUIRES: x86-registered-target +// REQUIRES: amdgpu-registered-target + +// RUN: %clang -### -target x86_64-linux-gnu \ +// RUN: --offload-arch=gfx906 \ +// RUN: %s 2>&1 | FileCheck -check-prefix=OFFLOAD %s +// OFFLOAD: warning: argument unused during compilation: '--offload-arch=gfx906' + +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: --offload-arch=gfx906 \ +// RUN: -fno-openmp \ +// RUN: %s 2>&1 | FileCheck -check-prefix=OFFLOAD1 %s +// OFFLOAD1: warning: argument unused during compilation: '--offload-arch=gfx906' + +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 \ +// RUN: -fno-openmp \ +// RUN: %s 2>&1 | FileCheck -check-prefix=LEGACY %s +// LEGACY: warning: '-fopenmp-targets' must be used in conjunction with a '-fopenmp' option compatible with offloading; e.g., '-fopenmp=libomp' or '-fopenmp=libiomp5' +// LEGACY-NEXT: warning: argument unused during compilation: '-Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906' + +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: --offload-arch=gfx906 \ +// RUN: --offload-arch=gfx908 \ +// RUN: -fno-openmp \ +// RUN: %s 2>&1 | FileCheck -check-prefix=MOFFLOAD %s +// MOFFLOAD: warning: argument unused during compilation: '--offload-arch=gfx906' +// MOFFLOAD-NEXT: warning: argument unused during compilation: '--offload-arch=gfx908' + +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 \ +// RUN: -fno-openmp \ +// RUN: %s 2>&1 | FileCheck -check-prefix=MLEGACY %s +// MLEGACY: warning: '-fopenmp-targets' must be used in conjunction with a '-fopenmp' option compatible with offloading; e.g., '-fopenmp=libomp' or '-fopenmp=libiomp5' +// MLEGACY: warning: argument unused during compilation: '-Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906' +// MLEGACY: warning: argument unused during compilation: '-Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908' diff --git a/clang/test/Driver/openmp-offload-gpu-new.c b/clang/test/Driver/openmp-offload-gpu-new.c new file mode 100644 index 0000000000000..ec4b04ccdcb2f --- /dev/null +++ b/clang/test/Driver/openmp-offload-gpu-new.c @@ -0,0 +1,134 @@ +/// +/// Perform several driver tests for OpenMP offloading +/// + +// REQUIRES: x86-registered-target +// REQUIRES: nvptx-registered-target +// REQUIRES: amdgpu-registered-target +// REQUIRES: host-supports-cuda + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda \ +// RUN: --no-opaque-offload-linker -Xopenmp-target=nvptx64-nvidia-cuda -march=sm_52 \ +// RUN: --libomptarget-nvptx-bc-path=%S/Inputs/libomptarget/libomptarget-nvptx-test.bc %s 2>&1 \ +// RUN: | FileCheck %s +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda \ +// RUN: --no-opaque-offload-linker --offload-arch=sm_52 \ +// RUN: --libomptarget-nvptx-bc-path=%S/Inputs/libomptarget/libomptarget-nvptx-test.bc %s 2>&1 \ +// RUN: | FileCheck %s + +// verify the tools invocations +// CHECK: "-cc1" "-triple" "x86_64-unknown-linux-gnu"{{.*}}"-emit-llvm-bc"{{.*}}"-x" "c" +// CHECK: "-cc1" "-triple" "nvptx64-nvidia-cuda" "-aux-triple" "x86_64-unknown-linux-gnu"{{.*}}"-target-cpu" "sm_52" +// CHECK: "-cc1" "-triple" "x86_64-unknown-linux-gnu"{{.*}}"-emit-obj" +// CHECK: clang-linker-wrapper{{.*}} "-o" "a.out" + +// RUN: %clang -ccc-print-phases --target=x86_64-unknown-linux-gnu --no-opaque-offload-linker -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda -Xopenmp-target=nvptx64-nvidia-cuda -march=sm_52 %s 2>&1 \ +// RUN: | FileCheck --check-prefix=CHECK-PHASES %s +// CHECK-PHASES: 0: input, "[[INPUT:.+]]", c, (host-openmp) +// CHECK-PHASES: 1: preprocessor, {0}, cpp-output, (host-openmp) +// CHECK-PHASES: 2: compiler, {1}, ir, (host-openmp) +// CHECK-PHASES: 3: input, "[[INPUT]]", c, (device-openmp) +// CHECK-PHASES: 4: preprocessor, {3}, cpp-output, (device-openmp) +// CHECK-PHASES: 5: compiler, {4}, ir, (device-openmp) +// CHECK-PHASES: 6: offload, "host-openmp (x86_64-unknown-linux-gnu)" {2}, "device-openmp (nvptx64-nvidia-cuda)" {5}, ir +// CHECK-PHASES: 7: backend, {6}, assembler, (device-openmp) +// CHECK-PHASES: 8: assembler, {7}, object, (device-openmp) +// CHECK-PHASES: 9: offload, "device-openmp (nvptx64-nvidia-cuda)" {8}, object +// CHECK-PHASES: 10: clang-offload-packager, {9}, image +// CHECK-PHASES: 11: offload, "host-openmp (x86_64-unknown-linux-gnu)" {2}, "device-openmp (x86_64-unknown-linux-gnu)" {10}, ir +// CHECK-PHASES: 12: backend, {11}, assembler, (host-openmp) +// CHECK-PHASES: 13: assembler, {12}, object, (host-openmp) +// CHECK-PHASES: 14: clang-linker-wrapper, {13}, image, (host-openmp) + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings --no-opaque-offload-linker -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda -Xopenmp-target=nvptx64-nvidia-cuda -march=sm_52 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-BINDINGS +// CHECK-BINDINGS: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[INPUT:.+]]"], output: "[[HOST_BC:.+]]" +// CHECK-BINDINGS: "nvptx64-nvidia-cuda" - "clang", inputs: ["[[INPUT]]", "[[HOST_BC]]"], output: "[[DEVICE_BC:.+]]" +// CHECK-BINDINGS: "nvptx64-nvidia-cuda" - "NVPTX::Assembler", inputs: ["[[DEVICE_BC]]"], output: "[[DEVICE_OBJ:.+]]" +// CHECK-BINDINGS: "x86_64-unknown-linux-gnu" - "Offload::Packager", inputs: ["[[DEVICE_OBJ]]"], output: "[[BINARY:.+.out]]" +// CHECK-BINDINGS: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[HOST_BC]]", "[[BINARY]]"], output: "[[HOST_OBJ:.+]]" +// CHECK-BINDINGS: "x86_64-unknown-linux-gnu" - "Offload::Linker", inputs: ["[[HOST_OBJ]]"], output: "a.out" + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda -Xopenmp-target=nvptx64-nvidia-cuda -march=sm_52 -nogpulib -save-temps %s 2>&1 | FileCheck %s --check-prefix=CHECK-TEMP-BINDINGS +// CHECK-TEMP-BINDINGS: "x86_64-unknown-linux-gnu" - "Offload::Packager", inputs: ["[[DEVICE_OBJ:.+]]"], output: "[[BINARY:.+.out]]" + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings --no-opaque-offload-linker -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda --offload-arch=sm_52 --offload-arch=sm_70 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARCH-BINDINGS +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings --no-opaque-offload-linker -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda --offload-arch=sm_52,sm_70 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARCH-BINDINGS +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings --no-opaque-offload-linker -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda --offload-arch=sm_52,sm_70,sm_35,sm_80 --no-offload-arch=sm_35,sm_80 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARCH-BINDINGS +// CHECK-ARCH-BINDINGS: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[INPUT:.*]]"], output: "[[HOST_BC:.*]]" +// CHECK-ARCH-BINDINGS: "nvptx64-nvidia-cuda" - "clang", inputs: ["[[INPUT]]", "[[HOST_BC]]"], output: "[[DEVICE_BC_SM_52:.*]]" +// CHECK-ARCH-BINDINGS: "nvptx64-nvidia-cuda" - "NVPTX::Assembler", inputs: ["[[DEVICE_BC_SM_52]]"], output: "[[DEVICE_OBJ_SM_52:.*]]" +// CHECK-ARCH-BINDINGS: "nvptx64-nvidia-cuda" - "clang", inputs: ["[[INPUT]]", "[[HOST_BC]]"], output: "[[DEVICE_BC_SM_70:.*]]" +// CHECK-ARCH-BINDINGS: "nvptx64-nvidia-cuda" - "NVPTX::Assembler", inputs: ["[[DEVICE_BC_SM_70]]"], output: "[[DEVICE_OBJ_SM_70:.*]]" +// CHECK-ARCH-BINDINGS: "x86_64-unknown-linux-gnu" - "Offload::Packager", inputs: ["[[DEVICE_OBJ_SM_52]]", "[[DEVICE_OBJ_SM_70]]"], output: "[[BINARY:.*]]" +// CHECK-ARCH-BINDINGS: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[HOST_BC]]", "[[BINARY]]"], output: "[[HOST_OBJ:.*]]" +// CHECK-ARCH-BINDINGS: "x86_64-unknown-linux-gnu" - "Offload::Linker", inputs: ["[[HOST_OBJ]]"], output: "a.out" + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp --no-opaque-offload-linker \ +// RUN: -fopenmp-targets=nvptx64-nvidia-cuda,amdgcn-amd-amdhsa -Xopenmp-target=nvptx64-nvidia-cuda --offload-arch=sm_70 \ +// RUN: -fopenmp-targets=nvptx64-nvidia-cuda,amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa --offload-arch=gfx908 \ +// RUN: -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-NVIDIA-AMDGPU + +// CHECK-NVIDIA-AMDGPU: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[INPUT:.+]]"], output: "[[HOST_BC:.+]]" +// CHECK-NVIDIA-AMDGPU: "amdgcn-amd-amdhsa" - "clang", inputs: ["[[INPUT]]", "[[HOST_BC]]"], output: "[[AMD_BC:.+]]" +// CHECK-NVIDIA-AMDGPU: "nvptx64-nvidia-cuda" - "clang", inputs: ["[[INPUT]]", "[[HOST_BC]]"], output: "[[NVIDIA_PTX:.+]]" +// CHECK-NVIDIA-AMDGPU: "nvptx64-nvidia-cuda" - "NVPTX::Assembler", inputs: ["[[NVIDIA_PTX]]"], output: "[[NVIDIA_CUBIN:.+]]" +// CHECK-NVIDIA-AMDGPU: "x86_64-unknown-linux-gnu" - "Offload::Packager", inputs: ["[[AMD_BC]]", "[[NVIDIA_CUBIN]]"], output: "[[BINARY:.*]]" +// CHECK-NVIDIA-AMDGPU: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[HOST_BC]]", "[[BINARY]]"], output: "[[HOST_OBJ:.+]]" +// CHECK-NVIDIA-AMDGPU: "x86_64-unknown-linux-gnu" - "Offload::Linker", inputs: ["[[HOST_OBJ]]"], output: "a.out" + +// RUN: %clang -x ir -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp --offload-arch=sm_52 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-IR + +// CHECK-IR: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[INPUT_IR:.+]]"], output: "[[OBJECT:.+]]" +// CHECK-IR: "x86_64-unknown-linux-gnu" - "Offload::Linker", inputs: ["[[OBJECT]]"], output: "a.out" + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -emit-llvm -S -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda -Xopenmp-target=nvptx64-nvidia-cuda -march=sm_52 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-EMIT-LLVM-IR +// CHECK-EMIT-LLVM-IR: "-cc1"{{.*}}"-triple" "nvptx64-nvidia-cuda"{{.*}}"-emit-llvm-bc" + +// RUN: %clang -### -fopenmp=libomp -fopenmp-targets=nvptx64-nvidia-cuda -Xopenmp-target=nvptx64-nvida-cuda -march=sm_70 \ +// RUN: --libomptarget-nvptx-bc-path=%S/Inputs/libomptarget/libomptarget-new-nvptx-test.bc \ +// RUN: -nogpulib %s -o openmp-offload-gpu 2>&1 \ +// RUN: | FileCheck -check-prefix=DRIVER_EMBEDDING %s + +// DRIVER_EMBEDDING: -fembed-offload-object={{.*}}.out + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda \ +// RUN: --offload-host-only -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-HOST-ONLY +// CHECK-HOST-ONLY: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[INPUT:.*]]"], output: "[[OUTPUT:.*]]" +// CHECK-HOST-ONLY: "x86_64-unknown-linux-gnu" - "Offload::Linker", inputs: ["[[OUTPUT]]"], output: "a.out" + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda \ +// RUN: --offload-device-only -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-DEVICE-ONLY +// CHECK-DEVICE-ONLY: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[INPUT:.*]]"], output: "[[HOST_BC:.*]]" +// CHECK-DEVICE-ONLY: "nvptx64-nvidia-cuda" - "clang", inputs: ["[[INPUT]]", "[[HOST_BC]]"], output: "[[DEVICE_ASM:.*]]" +// CHECK-DEVICE-ONLY: "nvptx64-nvidia-cuda" - "NVPTX::Assembler", inputs: ["[[DEVICE_ASM]]"], output: "{{.*}}-openmp-nvptx64-nvidia-cuda.o" + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp -fopenmp-targets=nvptx64-nvidia-cuda \ +// RUN: --offload-device-only -E -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-DEVICE-ONLY-PP +// CHECK-DEVICE-ONLY-PP: "nvptx64-nvidia-cuda" - "clang", inputs: ["[[INPUT:.*]]"], output: "-" + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp --offload-arch=sm_52 \ +// RUN: -foffload-lto %s 2>&1 | FileCheck --check-prefix=CHECK-LTO-LIBRARY %s + +// CHECK-LTO-LIBRARY: {{.*}}-lomptarget{{.*}}-lomptarget.devicertl + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp --offload-arch=sm_52 -nogpulib \ +// RUN: -foffload-lto %s 2>&1 | FileCheck --check-prefix=CHECK-NO-LIBRARY %s + +// CHECK-NO-LIBRARY-NOT: {{.*}}-lomptarget{{.*}}-lomptarget.devicertl + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp --offload-arch=sm_52 -nogpulib \ +// RUN: -Xoffload-linker a -Xoffload-linker-nvptx64-nvidia-cuda b -Xoffload-linker-nvptx64 c \ +// RUN: %s 2>&1 | FileCheck --check-prefix=CHECK-XLINKER %s + +// CHECK-XLINKER: -device-linker=a{{.*}}-device-linker=nvptx64-nvidia-cuda=b{{.*}}-device-linker=nvptx64-nvidia-cuda=c{{.*}}-- + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp --offload-arch=sm_52 -nogpulib \ +// RUN: -foffload-lto %s 2>&1 | FileCheck --check-prefix=CHECK-LTO-FEATURES %s + +// CHECK-LTO-FEATURES: clang-offload-packager{{.*}}--image={{.*}}feature=+ptx{{[0-9]+}} + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp --offload-arch=sm_52 -nogpulib \ +// RUN: -Xopenmp-target=nvptx64-nvidia-cuda --cuda-feature=+ptx64 -foffload-lto %s 2>&1 \ +// RUN: | FileCheck --check-prefix=CHECK-SET-FEATURES %s + +// CHECK-SET-FEATURES: clang-offload-packager{{.*}}--image={{.*}}feature=+ptx64 diff --git a/clang/test/Driver/openmp-offload-gpu.c b/clang/test/Driver/openmp-offload-gpu.c index edce14e94c8a2..e206c4946c0e5 100644 --- a/clang/test/Driver/openmp-offload-gpu.c +++ b/clang/test/Driver/openmp-offload-gpu.c @@ -2,6 +2,10 @@ /// Perform several driver tests for OpenMP offloading /// +// REQUIRES: x86-registered-target +// REQUIRES: nvptx-registered-target +// REQUIRES: amdgpu-registered-target + /// ########################################################################### /// Check -Xopenmp-target uses one of the archs provided when several archs are used. diff --git a/clang/test/Driver/openmp-offload-infer.c b/clang/test/Driver/openmp-offload-infer.c index 2a38a99c30518..249242c43a077 100644 --- a/clang/test/Driver/openmp-offload-infer.c +++ b/clang/test/Driver/openmp-offload-infer.c @@ -1,5 +1,5 @@ // RUN: %clang -### --target=x86_64-unknown-linux-gnu -fopenmp=libomp \ -// RUN: -nogpulib --offload-arch=sm_52 --offload-arch=gfx803 \ +// RUN: --no-opaque-offload-linker -nogpulib --offload-arch=sm_52 --offload-arch=gfx803 \ // RUN: --libomptarget-amdgpu-bc-path=%S/Inputs/hip_dev_lib/libomptarget-amdgpu-gfx803.bc \ // RUN: --libomptarget-nvptx-bc-path=%S/Inputs/libomptarget/libomptarget-nvptx-test.bc %s 2>&1 \ // RUN: | FileCheck %s @@ -12,7 +12,7 @@ // CHECK: clang-linker-wrapper{{.*}} "-o" "a.out" // RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp=libomp \ -// RUN: --offload-arch=sm_70 --offload-arch=gfx908:sramecc+:xnack- \ +// RUN: --no-opaque-offload-linker --offload-new-driver --offload-arch=sm_70 --offload-arch=gfx908:sramecc+:xnack- \ // RUN: -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-NVIDIA-AMDGPU // CHECK-NVIDIA-AMDGPU: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[INPUT:.+]]"], output: "[[HOST_BC:.+]]" @@ -23,8 +23,8 @@ // CHECK-NVIDIA-AMDGPU: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[HOST_BC]]", "[[BINARY]]"], output: "[[HOST_OBJ:.+]]" // CHECK-NVIDIA-AMDGPU: "x86_64-unknown-linux-gnu" - "Offload::Linker", inputs: ["[[HOST_OBJ]]"], output: "a.out" -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp=libomp \ -// RUN: --offload-arch=sm_52 --offload-arch=sm_70 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARCH-BINDINGS +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp=libomp --offload-new-driver \ +// RUN: --no-opaque-offload-linker --offload-arch=sm_52 --offload-arch=sm_70 -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARCH-BINDINGS // CHECK-ARCH-BINDINGS: "x86_64-unknown-linux-gnu" - "clang", inputs: ["[[INPUT:.*]]"], output: "[[HOST_BC:.*]]" // CHECK-ARCH-BINDINGS: "nvptx64-nvidia-cuda" - "clang", inputs: ["[[INPUT]]", "[[HOST_BC]]"], output: "[[DEVICE_BC_SM_52:.*]]" @@ -36,13 +36,13 @@ // CHECK-ARCH-BINDINGS: "x86_64-unknown-linux-gnu" - "Offload::Linker", inputs: ["[[HOST_OBJ]]"], output: "a.out" // RUN: not %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp=libomp \ -// RUN: --offload-arch=sm_70 --offload-arch=gfx908 --offload-arch=skylake \ +// RUN: --no-opaque-offload-linker --offload-arch=sm_70 --offload-arch=gfx908 --offload-arch=skylake \ // RUN: -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-FAILED // CHECK-FAILED: error: failed to deduce triple for target architecture 'skylake'; specify the triple using '-fopenmp-targets' and '-Xopenmp-target' instead // RUN: %clang -### --target=x86_64-unknown-linux-gnu -ccc-print-bindings -fopenmp=libomp \ -// RUN: --offload-arch=sm_70 --offload-arch=gfx908 -fno-openmp \ +// RUN: --no-opaque-offload-linker --offload-arch=sm_70 --offload-arch=gfx908 -fno-openmp \ // RUN: -nogpulib %s 2>&1 | FileCheck %s --check-prefix=CHECK-DISABLED // CHECK-DISABLED-NOT: "nvptx64-nvidia-cuda" - "clang", diff --git a/clang/test/Driver/openmp-offload-multi-save-temps.c b/clang/test/Driver/openmp-offload-multi-save-temps.c new file mode 100644 index 0000000000000..c2776745bd676 --- /dev/null +++ b/clang/test/Driver/openmp-offload-multi-save-temps.c @@ -0,0 +1,38 @@ +// REQUIRES: clang-driver +// REQUIRES: x86-registered-target +// REQUIRES: amdgpu-registered-target + +// +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 \ +// RUN: %s -save-temps 2>&1 | FileCheck %s + +// CHECK: clang{{.*}}"-cc1" "-triple" "x86_64-unknown-linux-gnu"{{.*}}"-save-temps=cwd"{{.*}}"-x" "c"{{.*}} +// CHECK: clang{{.*}}"-cc1" "-triple" "x86_64-unknown-linux-gnu"{{.*}}"-save-temps=cwd"{{.*}}" "-o" "[[HOSTASM:.*.s]]" "-x" "ir"{{.*}} +// CHECK: clang{{.*}}"-cc1as" "-triple" "x86_64-unknown-linux-gnu" "-filetype" "obj"{{.*}}"-o" "[[HOSTOBJ:.*.o]]" "[[HOSTASM]]" + +// compilation for offload target 1 : gfx906 +// CHECK: clang{{.*}}"-cc1"{{.*}}"-triple" "amdgcn-amd-amdhsa"{{.*}}"-save-temps=cwd"{{.*}}"-target-cpu" "gfx906"{{.*}}"-fopenmp-is-device"{{.*}}"-o" "{{.*}}.i" "-x" "c"{{.*}}.c +// CHECK: clang{{.*}}"-cc1"{{.*}}"-triple" "amdgcn-amd-amdhsa"{{.*}}"-emit-llvm-bc"{{.*}}"-save-temps=cwd"{{.*}}"-target-cpu" "gfx906"{{.*}}"-fopenmp-is-device"{{.*}}"-o" "{{.*}}.bc" "-x" "cpp-output"{{.*}}.i +// FIXME: llvm-link"{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx906-select.bc"{{.*}}"-o" "{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx906-linked.bc" +// CHECK: opt"{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx906-linked.bc" "-mtriple=amdgcn-amd-amdhsa" "-mcpu=gfx906" "-o"{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx906-optimized.bc" +// CHECK: llc{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx906-optimized.bc" "-mtriple=amdgcn-amd-amdhsa" "-mcpu=gfx906" "-filetype=obj"{{.*}}"-o"{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx906.o" +// CHECK: lld{{.*}}"-flavor" "gnu" "--no-undefined" "-shared" "-o" "a.out-openmp-amdgcn-amd-amdhsa-gfx906" "openmp-offload-multi-save-temps-openmp-amdgcn-amd-amdhsa-gfx906-gfx906.o" "-plugin-opt=mcpu=gfx906" + + +// compilation for offload target 2 : gfx908 +// CHECK: clang{{.*}}"-cc1"{{.*}}"-triple" "amdgcn-amd-amdhsa"{{.*}}"-save-temps=cwd"{{.*}}"-target-cpu" "gfx908"{{.*}}"-fopenmp-is-device"{{.*}}"-o" "{{.*}}.i" "-x" "c"{{.*}}.c +// CHECK: clang{{.*}}"-cc1"{{.*}}"-triple" "amdgcn-amd-amdhsa"{{.*}}"-emit-llvm-bc"{{.*}}"-save-temps=cwd"{{.*}}"-target-cpu" "gfx908"{{.*}}"-fopenmp-is-device"{{.*}}"-o" "{{.*}}.bc" "-x" "cpp-output"{{.*}}.i +// FIXME: llvm-link"{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx908-select.bc"{{.*}}"-o" "{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx908-linked.bc" +// CHECK: opt"{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx908-linked.bc" "-mtriple=amdgcn-amd-amdhsa" "-mcpu=gfx908" "-o"{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx908-optimized.bc" +// CHECK: llc{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx908-optimized.bc" "-mtriple=amdgcn-amd-amdhsa" "-mcpu=gfx908" "-filetype=obj"{{.*}}"-o"{{.*}}openmp-offload-multi-save-temps-{{.*}}-gfx908.o" +// CHECK: lld{{.*}}"-flavor" "gnu" "--no-undefined" "-shared" "-o" "a.out-openmp-amdgcn-amd-amdhsa-gfx908" "openmp-offload-multi-save-temps-openmp-amdgcn-amd-amdhsa-gfx908-gfx908.o" "-plugin-opt=mcpu=gfx908" + +// Combining device images for offload targets +// CHECK: clang-offload-wrapper"{{.*}}" "-o" "[[COMBINEDIR:.*.bc]]" "--offload-arch=gfx906" "a.out-openmp-amdgcn-amd-amdhsa-gfx906" "--offload-arch=gfx908" "a.out-openmp-amdgcn-amd-amdhsa-gfx908" + +// CHECK: clang{{.*}}"-cc1" "-triple" "x86_64-unknown-linux-gnu" "-S" "-save-temps=cwd"{{.*}}"-fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa"{{.*}}"-o" "[[COMBINEDASM:.*.s]]" "-x" "ir" "[[COMBINEDIR]]" +// CHECK: clang{{.*}}"-cc1as" "-triple" "x86_64-unknown-linux-gnu" "-filetype" "obj"{{.*}}"-o" "[[COMBINEDOBJ:.*.o]]" "[[COMBINEDASM]]" +// CHECK: ld"{{.*}}" "-o" "a.out{{.*}}[[HOSTOBJ]]" "[[COMBINEDOBJ]]{{.*}}" "-lomp{{.*}}-lomptarget" diff --git a/clang/test/Driver/openmp-offload-multi.c b/clang/test/Driver/openmp-offload-multi.c new file mode 100644 index 0000000000000..dea0d5253b0eb --- /dev/null +++ b/clang/test/Driver/openmp-offload-multi.c @@ -0,0 +1,33 @@ +// REQUIRES: clang-driver +// REQUIRES: x86-registered-target +// REQUIRES: amdgpu-registered-target + +// +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx906 \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 \ +// RUN: %s 2>&1 | FileCheck %s + +// CHECK: clang{{.*}}"-cc1" "-triple" "x86_64-unknown-linux-gnu"{{.*}}"-x" "c"{{.*}} +// CHECK: clang{{.*}}"-cc1" "-triple" "x86_64-unknown-linux-gnu"{{.*}}"-o" "[[HOSTOBJ:.*.o]]" "-x" "ir"{{.*}} + +// compilation for offload target 1 : gfx906 +// CHECK: clang{{.*}}"-cc1"{{.*}}"-triple" "amdgcn-amd-amdhsa"{{.*}}"-emit-llvm-bc"{{.*}}"-target-cpu" "gfx906" "-fcuda-is-device"{{.*}}"-o" "{{.*}}.bc" "-x" "c"{{.*}}.c +// FIXME: llvm-link"{{.*}}openmp-offload-multi-{{.*}}-gfx906-select-{{.*}}.bc"{{.*}}"-o" "{{.*}}openmp-offload-multi-{{.*}}-gfx906-linked-{{.*}}.bc" +// CHECK: opt"{{.*}}openmp-offload-multi-{{.*}}-gfx906-linked-{{.*}}.bc" "-mtriple=amdgcn-amd-amdhsa" "-mcpu=gfx906" "-o"{{.*}}openmp-offload-multi-{{.*}}-gfx906-optimized-{{.*}}.bc" +// CHECK: llc{{.*}}openmp-offload-multi-{{.*}}-gfx906-optimized-{{.*}}.bc" "-mtriple=amdgcn-amd-amdhsa" "-mcpu=gfx906" "-filetype=obj"{{.*}}"-o"{{.*}}openmp-offload-multi-{{.*}}-gfx906-{{.*}}.o" +// CHECK: lld{{.*}}"-flavor" "gnu" "--no-undefined" "-shared" "-o" "[[GFX906OUT:.*.out]]" "{{.*}}openmp-offload-multi-{{.*}}-gfx906-{{.*}}.o" + +// compilation for offload target 2 : gfx908 +// CHECK: clang{{.*}}"-cc1"{{.*}}"-triple" "amdgcn-amd-amdhsa"{{.*}}"-emit-llvm-bc"{{.*}}"-target-cpu" "gfx908" "-fcuda-is-device"{{.*}}"-o" "{{.*}}.bc" "-x" "c"{{.*}}.c +// FIXME: llvm-link"{{.*}}openmp-offload-multi-{{.*}}-gfx908-select-{{.*}}.bc"{{.*}}"-o" "{{.*}}openmp-offload-multi-{{.*}}-gfx908-linked-{{.*}}.bc" +// CHECK: opt"{{.*}}openmp-offload-multi-{{.*}}-gfx908-linked-{{.*}}.bc" "-mtriple=amdgcn-amd-amdhsa" "-mcpu=gfx908" "-o"{{.*}}openmp-offload-multi-{{.*}}-gfx908-optimized-{{.*}}.bc" +// CHECK: llc{{.*}}openmp-offload-multi-{{.*}}-gfx908-optimized-{{.*}}.bc" "-mtriple=amdgcn-amd-amdhsa" "-mcpu=gfx908" "-filetype=obj"{{.*}}"-o"{{.*}}openmp-offload-multi-{{.*}}-gfx908-{{.*}}.o" +// CHECK: lld{{.*}}"-flavor" "gnu" "--no-undefined" "-shared" "-o" "[[GFX908OUT:.*.out]]" "{{.*}}openmp-offload-multi-{{.*}}-gfx908-{{.*}}.o" + +// Combining device images for offload targets +// CHECK: clang-offload-wrapper"{{.*}}" "-o" "[[COMBINEDIR:.*.bc]]" "--offload-arch=gfx906" "[[GFX906OUT]]" "--offload-arch=gfx908" "[[GFX908OUT]]" + +// CHECK: clang{{.*}}"-cc1" "-triple" "x86_64-unknown-linux-gnu"{{.*}} "-fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa"{{.*}}"-o" "[[COMBINEDOBJ:.*.o]]" "-x" "ir" "[[COMBINEDIR]]" +// CHECK: ld"{{.*}}" "-o" "a.out{{.*}}[[HOSTOBJ]]" "[[COMBINEDOBJ]]{{.*}}" "-lomp{{.*}}-lomptarget" diff --git a/clang/test/Driver/openmp-offload.c b/clang/test/Driver/openmp-offload.c index fce1b88d2dc8f..a73932214610b 100644 --- a/clang/test/Driver/openmp-offload.c +++ b/clang/test/Driver/openmp-offload.c @@ -4,6 +4,8 @@ /// ########################################################################### +// XFAIL: * + /// Check whether an invalid OpenMP target is specified: // RUN: not %clang -### -fopenmp=libomp -fopenmp-targets=aaa-bbb-ccc-ddd %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-INVALID-TARGET %s @@ -166,7 +168,7 @@ // CHK-fopenmp-is-target-device: "-cc1"{{.*}} "-aux-triple" "powerpc64le-unknown-linux" {{.*}}"-fopenmp-is-target-device" "-fopenmp-host-ir-file-path" {{.*}}.c" /// Check arguments to the linker wrapper -// RUN: %clang -### --target=powerpc64le-linux -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu %s 2>&1 \ +// RUN: %clang -### --target=powerpc64le-linux -fopenmp=libomp -fopenmp-targets=powerpc64le-ibm-linux-gnu -fopenmp-new-driver %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-NEW-DRIVER %s // CHK-NEW-DRIVER: clang-linker-wrapper{{.*}}"--host-triple=powerpc64le-unknown-linux"{{.*}}--{{.*}}"-lomp"{{.*}}"-lomptarget" diff --git a/clang/test/Driver/openmp-runtimelib.c b/clang/test/Driver/openmp-runtimelib.c new file mode 100644 index 0000000000000..09600f2c376e3 --- /dev/null +++ b/clang/test/Driver/openmp-runtimelib.c @@ -0,0 +1,48 @@ +// REQUIRES: amdgpu-registered-target + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib --offload-arch=gfx90a -fopenmp-runtimelib=lib-debug %s -O3 2>&1 \ +// RUN: | FileCheck -check-prefixes=Debug,Debug-Rel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib --offload-arch=gfx90a -fopenmp-runtimelib=lib-perf %s -O3 2>&1 \ +// RUN: | FileCheck -check-prefixes=Perf,Perf-Rel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib --offload-arch=gfx90a -fopenmp-runtimelib=lib %s -O3 2>&1 \ +// RUN: | FileCheck -check-prefixes=Devel,Devel-Rel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib --offload-arch=gfx90a -fopenmp-target-fast %s -O3 2>&1 \ +// RUN: | FileCheck -check-prefixes=Devel,Devel-Rel %s + +// RUN: not %clang -### -fopenmp -nogpuinc -nogpulib --offload-arch=gfx90a -fopenmp-runtimelib=oopsy %s -O3 2>&1 \ +// RUN: | FileCheck -check-prefixes=Error %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib --offload-arch=gfx90a:xnack+ -fopenmp-runtimelib=lib-debug -fsanitize=address -shared-libasan %s -O3 2>&1 \ +// RUN: | FileCheck -check-prefixes=Asan-Debug,Asan-Debug-Rel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib --offload-arch=gfx90a:xnack+ -fopenmp-runtimelib=lib -fsanitize=address -shared-libasan %s -O3 2>&1 \ +// RUN: | FileCheck -check-prefixes=Asan-Devel,Asan-Devel-Rel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib --offload-arch=gfx90a:xnack+ -fopenmp-runtimelib=lib-perf -fsanitize=address -shared-libasan %s -O3 2>&1 \ +// RUN: | FileCheck -check-prefixes=Asan-Perf,Asan-Perf-Rel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib --offload-arch=gfx90a:xnack+ -fopenmp-target-fast -fsanitize=address -shared-libasan %s -O3 2>&1 \ +// RUN: | FileCheck -check-prefixes=Asan-Devel,Asan-Devel-Rel %s + +// Devel: "-rpath" "{{[^"]*}}[[LIB:(/|\\\\)lib]]" +// Devel-Rel-NOT: "-rpath" "{{[^"]*(/|\\\\)\.\.}}[[LIB]]" + +// Debug: "-rpath" "{{[^"]*}}[[LIB:(/|\\\\)lib-debug]]" +// Debug-Rel-NOT: "-rpath" "{{[^"]*(/|\\\\)\.\.}}[[LIB]]" + +// Perf: "-rpath" "{{[^"]*}}[[LIB:(/|\\\\)lib-perf]]" +// Perf-Rel-NOT: "-rpath" "{{[^"]*(/|\\\\)\.\.}}[[LIB]]" + +// Asan-Devel: "-rpath" "{{[^"]*}}[[LIB:(/|\\\\)lib(/|\\\\)asan]]" +// Asan-Devel-Rel-NOT: "-rpath" "{{[^"]*(/|\\\\)\.\.}}[[LIB]]" + +// Asan-Debug: "-rpath" "{{[^"]*}}[[LIB:(/|\\\\)lib-debug(/|\\\\)asan]]" +// Asan-Debug-Rel-NOT: "-rpath" "{{[^"]*(/|\\\\)\.\.}}[[LIB]]" + +// Asan-Perf: "-rpath" "{{[^"]*}}[[LIB:(/|\\\\)lib-perf(/|\\\\)asan]]" +// Asan-Perf-Rel-NOT: "-rpath" "{{[^"]*(/|\\\\)\.\.}}[[LIB]]" + +// Error: clang: error: unsupported argument 'oopsy' to option '-fopenmp-runtimelib=' diff --git a/clang/test/Driver/openmp-system-arch.c b/clang/test/Driver/openmp-system-arch.c index 1670fd30f4b59..493c62c97704d 100644 --- a/clang/test/Driver/openmp-system-arch.c +++ b/clang/test/Driver/openmp-system-arch.c @@ -28,10 +28,7 @@ // NO-OUTPUT-ERROR: error: cannot determine openmp architecture // case when amdgpu-arch succeeds. -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -nogpulib -fopenmp=libomp --offload-arch=native \ -// RUN: --nvptx-arch-tool=%t/nvptx_arch_fail --amdgpu-arch-tool=%t/amdgpu_arch_gfx906 %s 2>&1 \ -// RUN: | FileCheck %s --check-prefix=ARCH-GFX906 -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -nogpulib -fopenmp=libomp -fopenmp-targets=amdgcn-amd-amdhsa \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -nogpulib -fopenmp=libomp --offload-new-driver --offload-arch=native \ // RUN: --nvptx-arch-tool=%t/nvptx_arch_fail --amdgpu-arch-tool=%t/amdgpu_arch_gfx906 %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=ARCH-GFX906 // ARCH-GFX906: "-cc1" "-triple" "amdgcn-amd-amdhsa"{{.*}}"-target-cpu" "gfx906" diff --git a/clang/test/Driver/openmp-target-fast-flag.c b/clang/test/Driver/openmp-target-fast-flag.c new file mode 100644 index 0000000000000..f95d52809065a --- /dev/null +++ b/clang/test/Driver/openmp-target-fast-flag.c @@ -0,0 +1,46 @@ +// REQUIRES: amdgpu-registered-target + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a %s -O0 2>&1 \ +// RUN: | FileCheck -check-prefixes=NoTFast,NoEnV,NoTState,NoNestParallel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -O0 -fopenmp-target-fast %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=TFast,EnV,TState,NestParallel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -O4 %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=O4,NoTFast,NoEnV,NoTState,NoNestParallel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -O4 -fno-openmp-target-fast %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=O4,NoTFast,NoEnV,NoTState,NoNestParallel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -Ofast %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=OFast,TFast,EnV,TState,NestParallel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -Ofast -fno-openmp-target-fast %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=OFast,NoTFast,NoEnV,NoTState,NoNestParallel %s + +// RUN: %clang -### -fopenmp -nogpuinc -nogpulib -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -fopenmp-target-fast -fno-openmp-target-ignore-env-vars %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=TFast,NoEnV,TState,NestParallel,O3 %s + +// O4: -O4 +// OFast: -Ofast +// O3: -O3 + +// TFast: -fopenmp-target-fast +// TFast-NOT: -fno-openmp-target-fast +// NoTFast: -fno-openmp-target-fast +// NoTFast-NOT: -fopenmp-target-fast + +// EnV: -fopenmp-target-ignore-env-vars +// EnV-NOT: -fno-openmp-target-ignore-env-vars +// NoEnV: -fno-openmp-target-ignore-env-vars +// NoEnV-NOT: -fopenmp-target-ignore-env-vars + +// TState: -fopenmp-assume-no-thread-state +// TState-NOT: -fno-openmp-assume-no-thread-state +// NoTState: -fno-openmp-assume-no-thread-state +// NoTState-NOT: -fopenmp-assume-no-thread-state + +// NestParallel: -fopenmp-assume-no-nested-parallelism +// NestParallel-NOT: -fno-openmp-assume-no-nested-parallelism +// NoNestParallel: -fno-openmp-assume-no-nested-parallelism +// NoNestParallel-NOT: -fopenmp-assume-no-nested-parallelism diff --git a/clang/test/Driver/openmp-target-id.c b/clang/test/Driver/openmp-target-id.c new file mode 100644 index 0000000000000..7f1b4ab58871e --- /dev/null +++ b/clang/test/Driver/openmp-target-id.c @@ -0,0 +1,77 @@ +// REQUIRES: clang-driver +// REQUIRES: x86-registered-target +// REQUIRES: amdgpu-registered-target + +// +// Legacy mode (-fopenmp-targets,-Xopenmp-target,-march) tests for TargetID +// +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908:xnack+:sramecc+ \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908:xnack+:sramecc- \ +// RUN: %s 2>&1 | FileCheck %s + +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908:xnack+:sramecc+ \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908:xnack+:sramecc- \ +// RUN: -save-temps \ +// RUN: %s 2>&1 | FileCheck %s + +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: -fopenmp-targets=amdgcn-amd-amdhsa,amdgcn-amd-amdhsa \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908:xnack+:sramecc+ \ +// RUN: -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908:xnack+:sramecc- \ +// RUN: -fgpu-rdc \ +// RUN: %s 2>&1 | FileCheck %s + +// +// Offload-arch mode (--offload-arch) tests for TargetID +// +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: --offload-arch=gfx908:xnack+:sramecc+ \ +// RUN: --offload-arch=gfx908:xnack+:sramecc- \ +// RUN: %s 2>&1 | FileCheck %s + +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: --offload-arch=gfx908:xnack+:sramecc+ \ +// RUN: --offload-arch=gfx908:xnack+:sramecc- \ +// RUN: -save-temps \ +// RUN: %s 2>&1 | FileCheck %s + +// RUN: %clang -### -target x86_64-linux-gnu -fopenmp\ +// RUN: --offload-arch=gfx908:xnack+:sramecc+ \ +// RUN: --offload-arch=gfx908:xnack+:sramecc- \ +// RUN: -fgpu-rdc \ +// RUN: %s 2>&1 | FileCheck %s + +// CHECK: [[CLANG:"[^"]*clang[^"]*"]] "-cc1" "-triple" "amdgcn-amd-amdhsa" +// CHECK-SAME: "-target-cpu" "gfx908" +// CHECK-SAME: "-target-feature" "+sramecc" +// CHECK-SAME: "-target-feature" "+xnack" + +// CHECK: [[OPT:"[^"]*opt[^"]*"]] {{.*}} "-mcpu=gfx908" +// CHECK-SAME: "-mattr=+sramecc,+xnack" + +// CHECK: [[LLC:"[^"]*llc[^"]*"]] {{.*}} "-mcpu=gfx908" +// CHECK-SAME: "-mattr=+sramecc,+xnack + +// CHECK: [[LLD:"[^"]*lld[^"]*"]] {{.*}} "-plugin-opt=mcpu=gfx908" +// CHECK-SAME: "-plugin-opt=-mattr=+sramecc,+xnack" + +// CHECK: [[CLANG]] "-cc1" "-triple" "amdgcn-amd-amdhsa" +// CHECK-SAME: "-target-cpu" "gfx908" +// CHECK-SAME: "-target-feature" "-sramecc" +// CHECK-SAME: "-target-feature" "+xnack" + +// CHECK: [[OPT:"[^"]*opt[^"]*"]] {{.*}} "-mcpu=gfx908" +// CHECK-SAME: "-mattr=-sramecc,+xnack" + +// CHECK: [[LLC:"[^"]*llc[^"]*"]] {{.*}} "-mcpu=gfx908" +// CHECK-SAME: "-mattr=-sramecc,+xnack + +// CHECK: [[LLD]] {{.*}} "-plugin-opt=mcpu=gfx908" +// CHECK-SAME: "-plugin-opt=-mattr=-sramecc,+xnack" + +// CHECK: {{"[^"]*clang-offload-wrapper[^"]*"}} +// CHECK-SAME: "-target" "x86_64-unknown-linux-gnu" {{.*}} "--offload-arch=gfx908:sramecc+:xnack+" {{.*}} "--offload-arch=gfx908:sramecc-:xnack+" diff --git a/clang/test/Driver/pic.c b/clang/test/Driver/pic.c index f5d0745422790..b49e687ebb14e 100644 --- a/clang/test/Driver/pic.c +++ b/clang/test/Driver/pic.c @@ -45,7 +45,7 @@ // // CHECK-NO-UNUSED-ARG-NOT: argument unused during compilation // -// CHECK-NO-PIC-DATA-TEXT-REL: "-mcmodel=medium" +// CHECK-NO-PIC-DATA-TEXT-REL: "-mrelocation-model" // CHECK-PIC-DATA-TEXT-REL-NOT: "-mcmodel=medium" // CHECK-NO-PIC-DATA-TEXT-REL-NON-SYSTEMZ: error: unsupported option '-mno-pic-data-is-text-relative' for target 'arm-arm-none-eabi' // CHECK-PIC-DATA-TEXT-REL-NON-SYSTEMZ: error: unsupported option '-mpic-data-is-text-relative' for target 'arm-arm-none-eabi' diff --git a/clang/test/Driver/ppc-cpus.c b/clang/test/Driver/ppc-cpus.c index b0fd539b198a2..e3dcbbeabac34 100644 --- a/clang/test/Driver/ppc-cpus.c +++ b/clang/test/Driver/ppc-cpus.c @@ -41,5 +41,5 @@ // // GENERIC: "-target-cpu" "ppc64" -// RUN: not %clang -### -c --target=powerpc64 %s -march=generic 2>&1 | FileCheck --check-prefix=MARCH %s -// MARCH: error: unsupported option '-march=' for target 'powerpc64' +// RxUN: %clang -### -c --target=powerpc64 %s -march=generic 2>&1 | FileCheck --check-prefix=MARCH %s +// MxARCH: error: unsupported option '-march=' for target 'powerpc64' diff --git a/clang/test/Driver/sanitizer-ld.c b/clang/test/Driver/sanitizer-ld.c index ac1851286af63..ba548610ba9dd 100644 --- a/clang/test/Driver/sanitizer-ld.c +++ b/clang/test/Driver/sanitizer-ld.c @@ -1077,7 +1077,7 @@ // RUN: | %{filecheck} --check-prefix=CHECK-SHADOWCALLSTACK-SAFESTACK // CHECK-SHADOWCALLSTACK-SAFESTACK-NOT: error: // CHECK-SHADOWCALLSTACK-SAFESTACK: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-SHADOWCALLSTACK-SAFESTACK: libclang_rt.safestack.a +// CHECK-SHADOWCALLSTACK-SAFESTACK: libclang_rt.safestack{{.*}}.a // RUN: not %clang -fsanitize=cfi -fsanitize-stats -### %s 2>&1 \ // RUN: --target=x86_64-unknown-linux -fuse-ld=ld \ diff --git a/clang/test/Driver/ve-toolchain.cpp b/clang/test/Driver/ve-toolchain.cpp index 2e8f0f9bc8a57..d5a9dadeb804a 100644 --- a/clang/test/Driver/ve-toolchain.cpp +++ b/clang/test/Driver/ve-toolchain.cpp @@ -4,6 +4,8 @@ ///----------------------------------------------------------------------------- /// Checking dwarf-version +// XFAIL: * + // RUN: %clangxx -### -g --target=ve-unknown-linux-gnu \ // RUN: %s 2>&1 | FileCheck -check-prefix=DWARF_VER %s // DWARF_VER: "-dwarf-version=5" diff --git a/clang/test/Frontend/optimization-remark-with-hotness-new-pm.c b/clang/test/Frontend/optimization-remark-with-hotness-new-pm.c index 0c7e96182aebf..f1cf8b4572594 100644 --- a/clang/test/Frontend/optimization-remark-with-hotness-new-pm.c +++ b/clang/test/Frontend/optimization-remark-with-hotness-new-pm.c @@ -74,7 +74,7 @@ void bar(int x) { // THRESHOLD-NOT: hotness // NO_PGO: '-fdiagnostics-show-hotness' requires profile-guided optimization information // NO_PGO: '-fdiagnostics-hotness-threshold=' requires profile-guided optimization information - // expected-remark@+1 {{'foo' inlined into 'bar' with (cost=always): always inline attribute at callsite bar:8:10; (hotness:}} + // expected-remark@+1 {{'foo' inlined into 'bar': always inline attribute at callsite bar:8:10; (hotness:}} sum += foo(x, x - 2); } diff --git a/clang/test/Frontend/sarif-diagnostics.cpp b/clang/test/Frontend/sarif-diagnostics.cpp index 767c5802ca13d..0e09c2d5d299f 100644 --- a/clang/test/Frontend/sarif-diagnostics.cpp +++ b/clang/test/Frontend/sarif-diagnostics.cpp @@ -1,3 +1,4 @@ +// REQUIRES: fixforamd // RUN: %clang -fsyntax-only -Wall -Wextra -fdiagnostics-format=sarif %s > %t 2>&1 || true // RUN: FileCheck -dump-input=always %s --input-file=%t diff --git a/clang/test/Headers/Inputs/include/algorithm b/clang/test/Headers/Inputs/include/algorithm index 9122ec7179bfc..419608dcb9392 100644 --- a/clang/test/Headers/Inputs/include/algorithm +++ b/clang/test/Headers/Inputs/include/algorithm @@ -1,6 +1,21 @@ #pragma once +// Copied from libcxx + namespace std { - template constexpr const T& min(const T& a, const T& b); - template constexpr const T& max(const T& a, const T& b); -} \ No newline at end of file + +template + const T& + max(const T& a, const T& b); // constexpr in C++14 +template + const T& + max(const T& a, const T& b, Compare comp); // constexpr in C++14 + +template + const T& + min(const T& a, const T& b); // constexpr in C++14 +template + const T& + min(const T& a, const T& b, Compare comp); // constexpr in C++14 + +} diff --git a/clang/test/Headers/Inputs/include/cmath b/clang/test/Headers/Inputs/include/cmath index 20e34898b5535..e0fd0cd559256 100644 --- a/clang/test/Headers/Inputs/include/cmath +++ b/clang/test/Headers/Inputs/include/cmath @@ -49,12 +49,16 @@ double fma(double, double, double); float fma(float, float, float); double fmax(double, double); float fmax(float, float); +#ifndef __OPENMP_AMDGCN__ float max(float, float); double max(double, double); +#endif double fmin(double, double); float fmin(float, float); +#ifndef __OPENMP_AMDGCN__ float min(float, float); double min(double, double); +#endif double fmod(double, double); float fmod(float, float); int fpclassify(double); @@ -116,8 +120,10 @@ long lround(float); long long llround(float); // No llround(double). double modf(double, double *); float modf(float, float *); +#ifndef __OPENMP_AMDGCN__ double nan(const char *); float nanf(const char *); +#endif double nearbyint(double); float nearbyint(float); double nextafter(double, double); diff --git a/clang/test/Headers/Inputs/include/cstdint b/clang/test/Headers/Inputs/include/cstdint new file mode 100644 index 0000000000000..ef3c5f743da64 --- /dev/null +++ b/clang/test/Headers/Inputs/include/cstdint @@ -0,0 +1,21 @@ +#pragma once + +#include + +namespace std { +#ifdef __INT32_TYPE__ +using ::uint32_t; +#endif + +#ifdef __INT64_TYPE__ +using ::uint64_t; +#endif + +#ifdef __INTPTR_TYPE__ +using ::intptr_t; +using ::uintptr_t; +#else +#error Every target should have __INTPTR_TYPE__ +#endif + +} // namespace std diff --git a/clang/test/Headers/Inputs/include/cstdlib b/clang/test/Headers/Inputs/include/cstdlib index aac4e68662da6..917d38a6cf2af 100644 --- a/clang/test/Headers/Inputs/include/cstdlib +++ b/clang/test/Headers/Inputs/include/cstdlib @@ -14,6 +14,7 @@ namespace std { using ::abs; +using ::size_t; inline long abs(long __i) { return __builtin_labs(__i); } diff --git a/clang/test/Headers/Inputs/include/exception b/clang/test/Headers/Inputs/include/exception new file mode 100644 index 0000000000000..2e718003fef45 --- /dev/null +++ b/clang/test/Headers/Inputs/include/exception @@ -0,0 +1,17 @@ +#pragma once + +// Copied from libcxx + +namespace std { + +class exception +{ +public: + exception() noexcept; + exception(const exception&) noexcept; + exception& operator=(const exception&) noexcept; + virtual ~exception() noexcept; + virtual const char* what() const noexcept; +}; + +} diff --git a/clang/test/Headers/Inputs/include/stdlib.h b/clang/test/Headers/Inputs/include/stdlib.h index dc1ff225e3af5..192ac707ad26a 100644 --- a/clang/test/Headers/Inputs/include/stdlib.h +++ b/clang/test/Headers/Inputs/include/stdlib.h @@ -9,3 +9,6 @@ extern int abs(int __x) __attribute__((__const__)); extern long labs(long __x) __attribute__((__const__)); extern long long llabs(long long __x) __attribute__((__const__)); #endif + +void free(void* ptr); +void* malloc(size_t size); diff --git a/clang/test/Headers/Inputs/include/utility b/clang/test/Headers/Inputs/include/utility index 3f59c932d39b0..6f70f09beec22 100644 --- a/clang/test/Headers/Inputs/include/utility +++ b/clang/test/Headers/Inputs/include/utility @@ -1,2 +1 @@ #pragma once - diff --git a/clang/test/Headers/__clang_hip_math.hip b/clang/test/Headers/__clang_hip_math.hip index 7e2691633c215..22c0689a4552e 100644 --- a/clang/test/Headers/__clang_hip_math.hip +++ b/clang/test/Headers/__clang_hip_math.hip @@ -51,26 +51,26 @@ typedef unsigned long long uint64_t; // CHECK-SAME: ptr noundef readonly captures(none) [[P:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[P]], align 1, !tbaa [[CHAR_TBAA8:![0-9]+]] -// CHECK-NEXT: [[CMP_NOT_I1:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I1]], label %[[_ZL21__MAKE_MANTISSA_BASE8PKC_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// CHECK-NEXT: [[CMP_NOT12_I:%.*]] = icmp eq i8 [[TMP0]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT12_I]], label %[[_ZL21__MAKE_MANTISSA_BASE8PKC_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // CHECK: [[WHILE_BODY_I]]: // CHECK-NEXT: [[TMP1:%.*]] = phi i8 [ [[TMP3:%.*]], %[[IF_THEN_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] -// CHECK-NEXT: [[__R_0_I3:%.*]] = phi i64 [ [[SUB_I:%.*]], %[[IF_THEN_I]] ], [ 0, %[[ENTRY]] ] -// CHECK-NEXT: [[__TAGP_ADDR_0_I2:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[IF_THEN_I]] ], [ [[P]], %[[ENTRY]] ] +// CHECK-NEXT: [[__R_014_I:%.*]] = phi i64 [ [[SUB_I:%.*]], %[[IF_THEN_I]] ], [ 0, %[[ENTRY]] ] +// CHECK-NEXT: [[__TAGP_ADDR_013_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[IF_THEN_I]] ], [ [[P]], %[[ENTRY]] ] // CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], -8 // CHECK-NEXT: [[OR_COND_I:%.*]] = icmp eq i8 [[TMP2]], 48 // CHECK-NEXT: br i1 [[OR_COND_I]], label %[[IF_THEN_I]], label %[[_ZL21__MAKE_MANTISSA_BASE8PKC_EXIT]] // CHECK: [[IF_THEN_I]]: -// CHECK-NEXT: [[MUL_I:%.*]] = shl i64 [[__R_0_I3]], 3 +// CHECK-NEXT: [[MUL_I:%.*]] = shl i64 [[__R_014_I]], 3 // CHECK-NEXT: [[CONV5_I:%.*]] = zext nneg i8 [[TMP1]] to i64 -// CHECK-NEXT: [[ADD_I:%.*]] = add i64 [[MUL_I]], -48 -// CHECK-NEXT: [[SUB_I]] = add i64 [[ADD_I]], [[CONV5_I]] -// CHECK-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I2]], i64 1 +// CHECK-NEXT: [[ADD_I:%.*]] = add nsw i64 [[CONV5_I]], -48 +// CHECK-NEXT: [[SUB_I]] = or disjoint i64 [[ADD_I]], [[MUL_I]] +// CHECK-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I]], i64 1 // CHECK-NEXT: [[TMP3]] = load i8, ptr [[INCDEC_PTR_I]], align 1, !tbaa [[CHAR_TBAA8]] // CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i8 [[TMP3]], 0 // CHECK-NEXT: br i1 [[CMP_NOT_I]], label %[[_ZL21__MAKE_MANTISSA_BASE8PKC_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK: [[_ZL21__MAKE_MANTISSA_BASE8PKC_EXIT]]: -// CHECK-NEXT: [[RETVAL_2_I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ 0, %[[WHILE_BODY_I]] ], [ [[SUB_I]], %[[IF_THEN_I]] ] +// CHECK-NEXT: [[RETVAL_2_I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[SUB_I]], %[[IF_THEN_I]] ], [ 0, %[[WHILE_BODY_I]] ] // CHECK-NEXT: ret i64 [[RETVAL_2_I]] // // AMDGCNSPIRV-LABEL: define spir_func i64 @test___make_mantissa_base8( @@ -90,8 +90,8 @@ typedef unsigned long long uint64_t; // AMDGCNSPIRV-NEXT: [[CONV5_I:%.*]] = zext nneg i8 [[TMP0]] to i64 // AMDGCNSPIRV-NEXT: [[ADD_I:%.*]] = add i64 [[MUL_I]], -48 // AMDGCNSPIRV-NEXT: [[SUB_I:%.*]] = add i64 [[ADD_I]], [[CONV5_I]] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_IDX:%.*]] = zext i1 [[OR_COND_I]] to i64 -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I]], i64 [[__TAGP_ADDR_1_I_IDX]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_IDX_I:%.*]] = zext i1 [[OR_COND_I]] to i64 +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I]], i64 [[__TAGP_ADDR_1_IDX_I]] // AMDGCNSPIRV-NEXT: [[__R_1_I]] = select i1 [[OR_COND_I]], i64 [[SUB_I]], i64 [[__R_0_I]] // AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I]], label %[[WHILE_COND_I]], label %[[_ZL21__MAKE_MANTISSA_BASE8PKC_EXIT]], !llvm.loop [[LOOP10:![0-9]+]] // AMDGCNSPIRV: [[_ZL21__MAKE_MANTISSA_BASE8PKC_EXIT]]: @@ -106,26 +106,26 @@ extern "C" __device__ uint64_t test___make_mantissa_base8(const char *p) { // CHECK-SAME: ptr noundef readonly captures(none) [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[P]], align 1, !tbaa [[CHAR_TBAA8]] -// CHECK-NEXT: [[CMP_NOT_I1:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I1]], label %[[_ZL22__MAKE_MANTISSA_BASE10PKC_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// CHECK-NEXT: [[CMP_NOT12_I:%.*]] = icmp eq i8 [[TMP0]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT12_I]], label %[[_ZL22__MAKE_MANTISSA_BASE10PKC_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // CHECK: [[WHILE_BODY_I]]: // CHECK-NEXT: [[TMP1:%.*]] = phi i8 [ [[TMP3:%.*]], %[[IF_THEN_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] -// CHECK-NEXT: [[__R_0_I3:%.*]] = phi i64 [ [[SUB_I:%.*]], %[[IF_THEN_I]] ], [ 0, %[[ENTRY]] ] -// CHECK-NEXT: [[__TAGP_ADDR_0_I2:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[IF_THEN_I]] ], [ [[P]], %[[ENTRY]] ] +// CHECK-NEXT: [[__R_014_I:%.*]] = phi i64 [ [[SUB_I:%.*]], %[[IF_THEN_I]] ], [ 0, %[[ENTRY]] ] +// CHECK-NEXT: [[__TAGP_ADDR_013_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[IF_THEN_I]] ], [ [[P]], %[[ENTRY]] ] // CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -48 // CHECK-NEXT: [[OR_COND_I:%.*]] = icmp ult i8 [[TMP2]], 10 // CHECK-NEXT: br i1 [[OR_COND_I]], label %[[IF_THEN_I]], label %[[_ZL22__MAKE_MANTISSA_BASE10PKC_EXIT]] // CHECK: [[IF_THEN_I]]: -// CHECK-NEXT: [[MUL_I:%.*]] = mul i64 [[__R_0_I3]], 10 +// CHECK-NEXT: [[MUL_I:%.*]] = mul i64 [[__R_014_I]], 10 // CHECK-NEXT: [[CONV5_I:%.*]] = zext nneg i8 [[TMP1]] to i64 -// CHECK-NEXT: [[ADD_I:%.*]] = add i64 [[MUL_I]], -48 -// CHECK-NEXT: [[SUB_I]] = add i64 [[ADD_I]], [[CONV5_I]] -// CHECK-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I2]], i64 1 +// CHECK-NEXT: [[ADD_I:%.*]] = add nsw i64 [[CONV5_I]], -48 +// CHECK-NEXT: [[SUB_I]] = add i64 [[ADD_I]], [[MUL_I]] +// CHECK-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I]], i64 1 // CHECK-NEXT: [[TMP3]] = load i8, ptr [[INCDEC_PTR_I]], align 1, !tbaa [[CHAR_TBAA8]] // CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i8 [[TMP3]], 0 // CHECK-NEXT: br i1 [[CMP_NOT_I]], label %[[_ZL22__MAKE_MANTISSA_BASE10PKC_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK: [[_ZL22__MAKE_MANTISSA_BASE10PKC_EXIT]]: -// CHECK-NEXT: [[RETVAL_2_I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ 0, %[[WHILE_BODY_I]] ], [ [[SUB_I]], %[[IF_THEN_I]] ] +// CHECK-NEXT: [[RETVAL_2_I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[SUB_I]], %[[IF_THEN_I]] ], [ 0, %[[WHILE_BODY_I]] ] // CHECK-NEXT: ret i64 [[RETVAL_2_I]] // // AMDGCNSPIRV-LABEL: define spir_func i64 @test___make_mantissa_base10( @@ -145,8 +145,8 @@ extern "C" __device__ uint64_t test___make_mantissa_base8(const char *p) { // AMDGCNSPIRV-NEXT: [[CONV5_I:%.*]] = zext nneg i8 [[TMP0]] to i64 // AMDGCNSPIRV-NEXT: [[ADD_I:%.*]] = add i64 [[MUL_I]], -48 // AMDGCNSPIRV-NEXT: [[SUB_I:%.*]] = add i64 [[ADD_I]], [[CONV5_I]] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_IDX:%.*]] = zext i1 [[OR_COND_I]] to i64 -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I]], i64 [[__TAGP_ADDR_1_I_IDX]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_IDX_I:%.*]] = zext i1 [[OR_COND_I]] to i64 +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I]], i64 [[__TAGP_ADDR_1_IDX_I]] // AMDGCNSPIRV-NEXT: [[__R_1_I]] = select i1 [[OR_COND_I]], i64 [[SUB_I]], i64 [[__R_0_I]] // AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I]], label %[[WHILE_COND_I]], label %[[_ZL22__MAKE_MANTISSA_BASE10PKC_EXIT]], !llvm.loop [[LOOP13:![0-9]+]] // AMDGCNSPIRV: [[_ZL22__MAKE_MANTISSA_BASE10PKC_EXIT]]: @@ -161,70 +161,98 @@ extern "C" __device__ uint64_t test___make_mantissa_base10(const char *p) { // CHECK-SAME: ptr noundef readonly captures(none) [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[P]], align 1, !tbaa [[CHAR_TBAA8]] -// CHECK-NEXT: [[CMP_NOT_I1:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I1]], label %[[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// CHECK-NEXT: [[CMP_NOT48_I:%.*]] = icmp eq i8 [[TMP0]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT48_I]], label %[[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // CHECK: [[WHILE_BODY_I]]: // CHECK-NEXT: [[TMP1:%.*]] = phi i8 [ [[TMP5:%.*]], %[[IF_END31_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] -// CHECK-NEXT: [[__R_0_I3:%.*]] = phi i64 [ [[ADD28_I:%.*]], %[[IF_END31_I]] ], [ 0, %[[ENTRY]] ] -// CHECK-NEXT: [[__TAGP_ADDR_0_I2:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[IF_END31_I]] ], [ [[P]], %[[ENTRY]] ] +// CHECK-NEXT: [[__R_050_I:%.*]] = phi i64 [ [[__R_1_I:%.*]], %[[IF_END31_I]] ], [ 0, %[[ENTRY]] ] +// CHECK-NEXT: [[__TAGP_ADDR_049_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[IF_END31_I]] ], [ [[P]], %[[ENTRY]] ] // CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -48 // CHECK-NEXT: [[OR_COND_I:%.*]] = icmp ult i8 [[TMP2]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I]], label %[[IF_END31_I]], label %[[IF_ELSE_I:.*]] +// CHECK-NEXT: br i1 [[OR_COND_I]], label %[[IF_THEN_I:.*]], label %[[IF_ELSE_I:.*]] +// CHECK: [[IF_THEN_I]]: +// CHECK-NEXT: [[MUL_I:%.*]] = shl i64 [[__R_050_I]], 4 +// CHECK-NEXT: [[CONV5_I:%.*]] = zext nneg i8 [[TMP1]] to i64 +// CHECK-NEXT: [[ADD_I:%.*]] = add nsw i64 [[CONV5_I]], -48 +// CHECK-NEXT: [[SUB_I:%.*]] = or disjoint i64 [[ADD_I]], [[MUL_I]] +// CHECK-NEXT: br label %[[IF_END31_I]] // CHECK: [[IF_ELSE_I]]: // CHECK-NEXT: [[TMP3:%.*]] = add i8 [[TMP1]], -97 // CHECK-NEXT: [[OR_COND33_I:%.*]] = icmp ult i8 [[TMP3]], 6 -// CHECK-NEXT: br i1 [[OR_COND33_I]], label %[[IF_END31_I]], label %[[IF_ELSE17_I:.*]] +// CHECK-NEXT: br i1 [[OR_COND33_I]], label %[[IF_THEN11_I:.*]], label %[[IF_ELSE17_I:.*]] +// CHECK: [[IF_THEN11_I]]: +// CHECK-NEXT: [[MUL12_I:%.*]] = shl i64 [[__R_050_I]], 4 +// CHECK-NEXT: [[CONV13_I:%.*]] = zext nneg i8 [[TMP1]] to i64 +// CHECK-NEXT: [[ADD14_I:%.*]] = add nsw i64 [[CONV13_I]], -87 +// CHECK-NEXT: [[ADD16_I:%.*]] = add i64 [[ADD14_I]], [[MUL12_I]] +// CHECK-NEXT: br label %[[IF_END31_I]] // CHECK: [[IF_ELSE17_I]]: // CHECK-NEXT: [[TMP4:%.*]] = add i8 [[TMP1]], -65 // CHECK-NEXT: [[OR_COND34_I:%.*]] = icmp ult i8 [[TMP4]], 6 -// CHECK-NEXT: br i1 [[OR_COND34_I]], label %[[IF_END31_I]], label %[[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT]] -// CHECK: [[IF_END31_I]]: -// CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I]] ], [ -87, %[[IF_ELSE_I]] ], [ -55, %[[IF_ELSE17_I]] ] -// CHECK-NEXT: [[MUL24_I:%.*]] = shl i64 [[__R_0_I3]], 4 +// CHECK-NEXT: br i1 [[OR_COND34_I]], label %[[IF_THEN23_I:.*]], label %[[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT]] +// CHECK: [[IF_THEN23_I]]: +// CHECK-NEXT: [[MUL24_I:%.*]] = shl i64 [[__R_050_I]], 4 // CHECK-NEXT: [[CONV25_I:%.*]] = zext nneg i8 [[TMP1]] to i64 -// CHECK-NEXT: [[ADD26_I:%.*]] = add i64 [[MUL24_I]], [[DOTSINK]] -// CHECK-NEXT: [[ADD28_I]] = add i64 [[ADD26_I]], [[CONV25_I]] -// CHECK-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I2]], i64 1 +// CHECK-NEXT: [[ADD26_I:%.*]] = add nsw i64 [[CONV25_I]], -55 +// CHECK-NEXT: [[ADD28_I:%.*]] = add i64 [[ADD26_I]], [[MUL24_I]] +// CHECK-NEXT: br label %[[IF_END31_I]] +// CHECK: [[IF_END31_I]]: +// CHECK-NEXT: [[__R_1_I]] = phi i64 [ [[SUB_I]], %[[IF_THEN_I]] ], [ [[ADD16_I]], %[[IF_THEN11_I]] ], [ [[ADD28_I]], %[[IF_THEN23_I]] ] +// CHECK-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_049_I]], i64 1 // CHECK-NEXT: [[TMP5]] = load i8, ptr [[INCDEC_PTR_I]], align 1, !tbaa [[CHAR_TBAA8]] // CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i8 [[TMP5]], 0 // CHECK-NEXT: br i1 [[CMP_NOT_I]], label %[[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK: [[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT]]: -// CHECK-NEXT: [[RETVAL_2_I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ 0, %[[IF_ELSE17_I]] ], [ [[ADD28_I]], %[[IF_END31_I]] ] +// CHECK-NEXT: [[RETVAL_2_I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[__R_1_I]], %[[IF_END31_I]] ], [ 0, %[[IF_ELSE17_I]] ] // CHECK-NEXT: ret i64 [[RETVAL_2_I]] // // AMDGCNSPIRV-LABEL: define spir_func i64 @test___make_mantissa_base16( // AMDGCNSPIRV-SAME: ptr addrspace(4) noundef readonly captures(none) [[P:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR2]] { // AMDGCNSPIRV-NEXT: [[ENTRY:.*]]: // AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load i8, ptr addrspace(4) [[P]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I1:%.*]] = icmp eq i8 [[TMP0]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I1]], label %[[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// AMDGCNSPIRV-NEXT: [[CMP_NOT48_I:%.*]] = icmp eq i8 [[TMP0]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT48_I]], label %[[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // AMDGCNSPIRV: [[WHILE_BODY_I]]: // AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = phi i8 [ [[TMP5:%.*]], %[[IF_END31_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__R_0_I3:%.*]] = phi i64 [ [[ADD28_I:%.*]], %[[IF_END31_I]] ], [ 0, %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I2:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I:%.*]], %[[IF_END31_I]] ], [ [[P]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__R_050_I:%.*]] = phi i64 [ [[__R_1_I:%.*]], %[[IF_END31_I]] ], [ 0, %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_049_I:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I:%.*]], %[[IF_END31_I]] ], [ [[P]], %[[ENTRY]] ] // AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -48 // AMDGCNSPIRV-NEXT: [[OR_COND_I:%.*]] = icmp ult i8 [[TMP2]], 10 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I]], label %[[IF_END31_I]], label %[[IF_ELSE_I:.*]] +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I]], label %[[IF_THEN_I:.*]], label %[[IF_ELSE_I:.*]] +// AMDGCNSPIRV: [[IF_THEN_I]]: +// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = shl i64 [[__R_050_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV5_I:%.*]] = zext nneg i8 [[TMP1]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD_I:%.*]] = add nsw i64 [[CONV5_I]], -48 +// AMDGCNSPIRV-NEXT: [[SUB_I:%.*]] = or disjoint i64 [[ADD_I]], [[MUL_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I]] // AMDGCNSPIRV: [[IF_ELSE_I]]: // AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = add i8 [[TMP1]], -97 // AMDGCNSPIRV-NEXT: [[OR_COND33_I:%.*]] = icmp ult i8 [[TMP3]], 6 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND33_I]], label %[[IF_END31_I]], label %[[IF_ELSE17_I:.*]] +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND33_I]], label %[[IF_THEN11_I:.*]], label %[[IF_ELSE17_I:.*]] +// AMDGCNSPIRV: [[IF_THEN11_I]]: +// AMDGCNSPIRV-NEXT: [[MUL12_I:%.*]] = shl i64 [[__R_050_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV13_I:%.*]] = zext nneg i8 [[TMP1]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD14_I:%.*]] = add nsw i64 [[CONV13_I]], -87 +// AMDGCNSPIRV-NEXT: [[ADD16_I:%.*]] = add i64 [[ADD14_I]], [[MUL12_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I]] // AMDGCNSPIRV: [[IF_ELSE17_I]]: // AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = add i8 [[TMP1]], -65 // AMDGCNSPIRV-NEXT: [[OR_COND34_I:%.*]] = icmp ult i8 [[TMP4]], 6 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND34_I]], label %[[IF_END31_I]], label %[[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT]] -// AMDGCNSPIRV: [[IF_END31_I]]: -// AMDGCNSPIRV-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I]] ], [ -87, %[[IF_ELSE_I]] ], [ -55, %[[IF_ELSE17_I]] ] -// AMDGCNSPIRV-NEXT: [[MUL24_I:%.*]] = shl i64 [[__R_0_I3]], 4 +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND34_I]], label %[[IF_THEN23_I:.*]], label %[[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT]] +// AMDGCNSPIRV: [[IF_THEN23_I]]: +// AMDGCNSPIRV-NEXT: [[MUL24_I:%.*]] = shl i64 [[__R_050_I]], 4 // AMDGCNSPIRV-NEXT: [[CONV25_I:%.*]] = zext nneg i8 [[TMP1]] to i64 -// AMDGCNSPIRV-NEXT: [[ADD26_I:%.*]] = add i64 [[MUL24_I]], [[DOTSINK]] -// AMDGCNSPIRV-NEXT: [[ADD28_I]] = add i64 [[ADD26_I]], [[CONV25_I]] -// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I2]], i64 1 +// AMDGCNSPIRV-NEXT: [[ADD26_I:%.*]] = add nsw i64 [[CONV25_I]], -55 +// AMDGCNSPIRV-NEXT: [[ADD28_I:%.*]] = add i64 [[ADD26_I]], [[MUL24_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I]] +// AMDGCNSPIRV: [[IF_END31_I]]: +// AMDGCNSPIRV-NEXT: [[__R_1_I]] = phi i64 [ [[SUB_I]], %[[IF_THEN_I]] ], [ [[ADD16_I]], %[[IF_THEN11_I]] ], [ [[ADD28_I]], %[[IF_THEN23_I]] ] +// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_049_I]], i64 1 // AMDGCNSPIRV-NEXT: [[TMP5]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I]], align 1, !tbaa [[CHAR_TBAA9]] // AMDGCNSPIRV-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i8 [[TMP5]], 0 // AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I]], label %[[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] // AMDGCNSPIRV: [[_ZL22__MAKE_MANTISSA_BASE16PKC_EXIT]]: -// AMDGCNSPIRV-NEXT: [[RETVAL_2_I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ 0, %[[IF_ELSE17_I]] ], [ [[ADD28_I]], %[[IF_END31_I]] ] +// AMDGCNSPIRV-NEXT: [[RETVAL_2_I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[__R_1_I]], %[[IF_END31_I]] ], [ 0, %[[IF_ELSE17_I]] ] // AMDGCNSPIRV-NEXT: ret i64 [[RETVAL_2_I]] // extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { @@ -233,88 +261,95 @@ extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { // CHECK-LABEL: define dso_local i64 @test___make_mantissa( // CHECK-SAME: ptr noundef readonly captures(none) [[P:%.*]]) local_unnamed_addr #[[ATTR2]] { -// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[P]], align 1, !tbaa [[CHAR_TBAA8]] -// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// CHECK-NEXT: br i1 [[CMP_I]], label %[[IF_THEN_I:.*]], label %[[WHILE_COND_I14_I_PREHEADER:.*]] -// CHECK: [[WHILE_COND_I14_I_PREHEADER]]: -// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[P]], align 1, !tbaa [[CHAR_TBAA8]] -// CHECK-NEXT: [[CMP_NOT_I17_I5:%.*]] = icmp eq i8 [[TMP1]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I17_I5]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT:.*]], label %[[WHILE_BODY_I18_I:.*]] +// CHECK-NEXT: switch i8 [[TMP0]], label %[[WHILE_BODY_I25_I:.*]] [ +// CHECK-NEXT: i8 48, label %[[IF_THEN_I:.*]] +// CHECK-NEXT: i8 0, label %[[_ZL15__MAKE_MANTISSAPKC_EXIT:.*]] +// CHECK-NEXT: ] // CHECK: [[IF_THEN_I]]: // CHECK-NEXT: [[INCDEC_PTR_I:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 1 -// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[INCDEC_PTR_I]], align 1, !tbaa [[CHAR_TBAA8]] -// CHECK-NEXT: switch i8 [[TMP2]], label %[[WHILE_COND_I_I_PREHEADER:.*]] [ -// CHECK-NEXT: i8 120, label %[[IF_THEN5_I:.*]] -// CHECK-NEXT: i8 88, label %[[IF_THEN5_I]] +// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I]], align 1, !tbaa [[CHAR_TBAA8]] +// CHECK-NEXT: switch i8 [[TMP1]], label %[[WHILE_BODY_I14_I:.*]] [ +// CHECK-NEXT: i8 88, label %[[WHILE_BODY_I_I_PREHEADER:.*]] +// CHECK-NEXT: i8 120, label %[[WHILE_BODY_I_I_PREHEADER]] +// CHECK-NEXT: i8 0, label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]] // CHECK-NEXT: ] -// CHECK: [[WHILE_COND_I_I_PREHEADER]]: -// CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[INCDEC_PTR_I]], align 1, !tbaa [[CHAR_TBAA8]] -// CHECK-NEXT: [[CMP_NOT_I_I14:%.*]] = icmp eq i8 [[TMP3]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I_I14]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I_I:.*]] -// CHECK: [[IF_THEN5_I]]: -// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[INCDEC_PTR_I]], align 1, !tbaa [[CHAR_TBAA8]] -// CHECK-NEXT: [[CMP_NOT_I30_I9:%.*]] = icmp eq i8 [[TMP4]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I30_I9]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I31_I:.*]] -// CHECK: [[WHILE_BODY_I31_I]]: -// CHECK-NEXT: [[TMP5:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_END31_I_I:.*]] ], [ [[TMP4]], %[[IF_THEN5_I]] ] -// CHECK-NEXT: [[__R_0_I29_I11:%.*]] = phi i64 [ [[ADD28_I_I:%.*]], %[[IF_END31_I_I]] ], [ 0, %[[IF_THEN5_I]] ] -// CHECK-NEXT: [[__TAGP_ADDR_0_I28_I10:%.*]] = phi ptr [ [[INCDEC_PTR_I34_I:%.*]], %[[IF_END31_I_I]] ], [ [[INCDEC_PTR_I]], %[[IF_THEN5_I]] ] -// CHECK-NEXT: [[TMP6:%.*]] = add i8 [[TMP5]], -48 -// CHECK-NEXT: [[OR_COND_I32_I:%.*]] = icmp ult i8 [[TMP6]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I32_I]], label %[[IF_END31_I_I]], label %[[IF_ELSE_I_I:.*]] +// CHECK: [[WHILE_BODY_I_I_PREHEADER]]: +// CHECK-NEXT: br label %[[WHILE_BODY_I_I:.*]] +// CHECK: [[WHILE_BODY_I_I]]: +// CHECK-NEXT: [[TMP2:%.*]] = phi i8 [ [[TMP6:%.*]], %[[IF_END31_I_I:.*]] ], [ [[TMP1]], %[[WHILE_BODY_I_I_PREHEADER]] ] +// CHECK-NEXT: [[__R_050_I_I:%.*]] = phi i64 [ [[__R_1_I_I:%.*]], %[[IF_END31_I_I]] ], [ 0, %[[WHILE_BODY_I_I_PREHEADER]] ] +// CHECK-NEXT: [[__TAGP_ADDR_049_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I_I:%.*]], %[[IF_END31_I_I]] ], [ [[INCDEC_PTR_I]], %[[WHILE_BODY_I_I_PREHEADER]] ] +// CHECK-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 +// CHECK-NEXT: [[OR_COND_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// CHECK-NEXT: br i1 [[OR_COND_I_I]], label %[[IF_THEN_I_I:.*]], label %[[IF_ELSE_I_I:.*]] +// CHECK: [[IF_THEN_I_I]]: +// CHECK-NEXT: [[MUL_I_I:%.*]] = shl i64 [[__R_050_I_I]], 4 +// CHECK-NEXT: [[CONV5_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// CHECK-NEXT: [[ADD_I_I:%.*]] = add nsw i64 [[CONV5_I_I]], -48 +// CHECK-NEXT: [[SUB_I_I:%.*]] = or disjoint i64 [[ADD_I_I]], [[MUL_I_I]] +// CHECK-NEXT: br label %[[IF_END31_I_I]] // CHECK: [[IF_ELSE_I_I]]: -// CHECK-NEXT: [[TMP7:%.*]] = add i8 [[TMP5]], -97 -// CHECK-NEXT: [[OR_COND33_I_I:%.*]] = icmp ult i8 [[TMP7]], 6 -// CHECK-NEXT: br i1 [[OR_COND33_I_I]], label %[[IF_END31_I_I]], label %[[IF_ELSE17_I_I:.*]] +// CHECK-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 +// CHECK-NEXT: [[OR_COND33_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 +// CHECK-NEXT: br i1 [[OR_COND33_I_I]], label %[[IF_THEN11_I_I:.*]], label %[[IF_ELSE17_I_I:.*]] +// CHECK: [[IF_THEN11_I_I]]: +// CHECK-NEXT: [[MUL12_I_I:%.*]] = shl i64 [[__R_050_I_I]], 4 +// CHECK-NEXT: [[CONV13_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// CHECK-NEXT: [[ADD14_I_I:%.*]] = add nsw i64 [[CONV13_I_I]], -87 +// CHECK-NEXT: [[ADD16_I_I:%.*]] = add i64 [[ADD14_I_I]], [[MUL12_I_I]] +// CHECK-NEXT: br label %[[IF_END31_I_I]] // CHECK: [[IF_ELSE17_I_I]]: -// CHECK-NEXT: [[TMP8:%.*]] = add i8 [[TMP5]], -65 -// CHECK-NEXT: [[OR_COND34_I_I:%.*]] = icmp ult i8 [[TMP8]], 6 -// CHECK-NEXT: br i1 [[OR_COND34_I_I]], label %[[IF_END31_I_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]] +// CHECK-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 +// CHECK-NEXT: [[OR_COND34_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 +// CHECK-NEXT: br i1 [[OR_COND34_I_I]], label %[[IF_THEN23_I_I:.*]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]] +// CHECK: [[IF_THEN23_I_I]]: +// CHECK-NEXT: [[MUL24_I_I:%.*]] = shl i64 [[__R_050_I_I]], 4 +// CHECK-NEXT: [[CONV25_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// CHECK-NEXT: [[ADD26_I_I:%.*]] = add nsw i64 [[CONV25_I_I]], -55 +// CHECK-NEXT: [[ADD28_I_I:%.*]] = add i64 [[ADD26_I_I]], [[MUL24_I_I]] +// CHECK-NEXT: br label %[[IF_END31_I_I]] // CHECK: [[IF_END31_I_I]]: -// CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I31_I]] ], [ -87, %[[IF_ELSE_I_I]] ], [ -55, %[[IF_ELSE17_I_I]] ] -// CHECK-NEXT: [[MUL24_I_I:%.*]] = shl i64 [[__R_0_I29_I11]], 4 -// CHECK-NEXT: [[CONV25_I_I:%.*]] = zext nneg i8 [[TMP5]] to i64 -// CHECK-NEXT: [[ADD26_I_I:%.*]] = add i64 [[MUL24_I_I]], [[DOTSINK]] -// CHECK-NEXT: [[ADD28_I_I]] = add i64 [[ADD26_I_I]], [[CONV25_I_I]] -// CHECK-NEXT: [[INCDEC_PTR_I34_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I28_I10]], i64 1 -// CHECK-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I34_I]], align 1, !tbaa [[CHAR_TBAA8]] -// CHECK-NEXT: [[CMP_NOT_I30_I:%.*]] = icmp eq i8 [[TMP9]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I30_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I31_I]], !llvm.loop [[LOOP13]] -// CHECK: [[WHILE_BODY_I_I]]: -// CHECK-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I_I:.*]] ], [ [[TMP3]], %[[WHILE_COND_I_I_PREHEADER]] ] -// CHECK-NEXT: [[__R_0_I_I16:%.*]] = phi i64 [ [[SUB_I_I:%.*]], %[[IF_THEN_I_I]] ], [ 0, %[[WHILE_COND_I_I_PREHEADER]] ] -// CHECK-NEXT: [[__TAGP_ADDR_0_I_I15:%.*]] = phi ptr [ [[INCDEC_PTR_I_I:%.*]], %[[IF_THEN_I_I]] ], [ [[INCDEC_PTR_I]], %[[WHILE_COND_I_I_PREHEADER]] ] -// CHECK-NEXT: [[TMP11:%.*]] = and i8 [[TMP10]], -8 -// CHECK-NEXT: [[OR_COND_I_I:%.*]] = icmp eq i8 [[TMP11]], 48 -// CHECK-NEXT: br i1 [[OR_COND_I_I]], label %[[IF_THEN_I_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]] -// CHECK: [[IF_THEN_I_I]]: -// CHECK-NEXT: [[MUL_I_I:%.*]] = shl i64 [[__R_0_I_I16]], 3 -// CHECK-NEXT: [[CONV5_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 -// CHECK-NEXT: [[ADD_I_I:%.*]] = add i64 [[MUL_I_I]], -48 -// CHECK-NEXT: [[SUB_I_I]] = add i64 [[ADD_I_I]], [[CONV5_I_I]] -// CHECK-NEXT: [[INCDEC_PTR_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I_I15]], i64 1 -// CHECK-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// CHECK-NEXT: [[CMP_NOT_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I_I]], !llvm.loop [[LOOP9]] -// CHECK: [[WHILE_BODY_I18_I]]: -// CHECK-NEXT: [[TMP13:%.*]] = phi i8 [ [[TMP15:%.*]], %[[IF_THEN_I21_I:.*]] ], [ [[TMP1]], %[[WHILE_COND_I14_I_PREHEADER]] ] -// CHECK-NEXT: [[__R_0_I16_I7:%.*]] = phi i64 [ [[SUB_I25_I:%.*]], %[[IF_THEN_I21_I]] ], [ 0, %[[WHILE_COND_I14_I_PREHEADER]] ] -// CHECK-NEXT: [[__TAGP_ADDR_0_I15_I6:%.*]] = phi ptr [ [[INCDEC_PTR_I26_I:%.*]], %[[IF_THEN_I21_I]] ], [ [[P]], %[[WHILE_COND_I14_I_PREHEADER]] ] -// CHECK-NEXT: [[TMP14:%.*]] = add i8 [[TMP13]], -48 -// CHECK-NEXT: [[OR_COND_I19_I:%.*]] = icmp ult i8 [[TMP14]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I19_I]], label %[[IF_THEN_I21_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]] -// CHECK: [[IF_THEN_I21_I]]: -// CHECK-NEXT: [[MUL_I22_I:%.*]] = mul i64 [[__R_0_I16_I7]], 10 -// CHECK-NEXT: [[CONV5_I23_I:%.*]] = zext nneg i8 [[TMP13]] to i64 -// CHECK-NEXT: [[ADD_I24_I:%.*]] = add i64 [[MUL_I22_I]], -48 -// CHECK-NEXT: [[SUB_I25_I]] = add i64 [[ADD_I24_I]], [[CONV5_I23_I]] -// CHECK-NEXT: [[INCDEC_PTR_I26_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I15_I6]], i64 1 -// CHECK-NEXT: [[TMP15]] = load i8, ptr [[INCDEC_PTR_I26_I]], align 1, !tbaa [[CHAR_TBAA8]] -// CHECK-NEXT: [[CMP_NOT_I17_I:%.*]] = icmp eq i8 [[TMP15]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I17_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I18_I]], !llvm.loop [[LOOP12]] +// CHECK-NEXT: [[__R_1_I_I]] = phi i64 [ [[SUB_I_I]], %[[IF_THEN_I_I]] ], [ [[ADD16_I_I]], %[[IF_THEN11_I_I]] ], [ [[ADD28_I_I]], %[[IF_THEN23_I_I]] ] +// CHECK-NEXT: [[INCDEC_PTR_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_049_I_I]], i64 1 +// CHECK-NEXT: [[TMP6]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// CHECK-NEXT: [[CMP_NOT_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I_I]], !llvm.loop [[LOOP13]] +// CHECK: [[WHILE_BODY_I14_I]]: +// CHECK-NEXT: [[TMP7:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_THEN_I17_I:.*]] ], [ [[TMP1]], %[[IF_THEN_I]] ] +// CHECK-NEXT: [[__R_014_I_I:%.*]] = phi i64 [ [[SUB_I21_I:%.*]], %[[IF_THEN_I17_I]] ], [ 0, %[[IF_THEN_I]] ] +// CHECK-NEXT: [[__TAGP_ADDR_013_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I22_I:%.*]], %[[IF_THEN_I17_I]] ], [ [[INCDEC_PTR_I]], %[[IF_THEN_I]] ] +// CHECK-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], -8 +// CHECK-NEXT: [[OR_COND_I15_I:%.*]] = icmp eq i8 [[TMP8]], 48 +// CHECK-NEXT: br i1 [[OR_COND_I15_I]], label %[[IF_THEN_I17_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]] +// CHECK: [[IF_THEN_I17_I]]: +// CHECK-NEXT: [[MUL_I18_I:%.*]] = shl i64 [[__R_014_I_I]], 3 +// CHECK-NEXT: [[CONV5_I19_I:%.*]] = zext nneg i8 [[TMP7]] to i64 +// CHECK-NEXT: [[ADD_I20_I:%.*]] = add nsw i64 [[CONV5_I19_I]], -48 +// CHECK-NEXT: [[SUB_I21_I]] = or disjoint i64 [[ADD_I20_I]], [[MUL_I18_I]] +// CHECK-NEXT: [[INCDEC_PTR_I22_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I_I]], i64 1 +// CHECK-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I22_I]], align 1, !tbaa [[CHAR_TBAA8]] +// CHECK-NEXT: [[CMP_NOT_I23_I:%.*]] = icmp eq i8 [[TMP9]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I23_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I14_I]], !llvm.loop [[LOOP9]] +// CHECK: [[WHILE_BODY_I25_I]]: +// CHECK-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I30_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] +// CHECK-NEXT: [[__R_014_I26_I:%.*]] = phi i64 [ [[SUB_I34_I:%.*]], %[[IF_THEN_I30_I]] ], [ 0, %[[ENTRY]] ] +// CHECK-NEXT: [[__TAGP_ADDR_013_I27_I:%.*]] = phi ptr [ [[INCDEC_PTR_I35_I:%.*]], %[[IF_THEN_I30_I]] ], [ [[P]], %[[ENTRY]] ] +// CHECK-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], -48 +// CHECK-NEXT: [[OR_COND_I28_I:%.*]] = icmp ult i8 [[TMP11]], 10 +// CHECK-NEXT: br i1 [[OR_COND_I28_I]], label %[[IF_THEN_I30_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]] +// CHECK: [[IF_THEN_I30_I]]: +// CHECK-NEXT: [[MUL_I31_I:%.*]] = mul i64 [[__R_014_I26_I]], 10 +// CHECK-NEXT: [[CONV5_I32_I:%.*]] = zext nneg i8 [[TMP10]] to i64 +// CHECK-NEXT: [[ADD_I33_I:%.*]] = add nsw i64 [[CONV5_I32_I]], -48 +// CHECK-NEXT: [[SUB_I34_I]] = add i64 [[ADD_I33_I]], [[MUL_I31_I]] +// CHECK-NEXT: [[INCDEC_PTR_I35_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I27_I]], i64 1 +// CHECK-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I35_I]], align 1, !tbaa [[CHAR_TBAA8]] +// CHECK-NEXT: [[CMP_NOT_I36_I:%.*]] = icmp eq i8 [[TMP12]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I36_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I25_I]], !llvm.loop [[LOOP12]] // CHECK: [[_ZL15__MAKE_MANTISSAPKC_EXIT]]: -// CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi i64 [ 0, %[[WHILE_COND_I_I_PREHEADER]] ], [ 0, %[[IF_THEN5_I]] ], [ 0, %[[WHILE_COND_I14_I_PREHEADER]] ], [ [[SUB_I_I]], %[[IF_THEN_I_I]] ], [ 0, %[[WHILE_BODY_I_I]] ], [ [[ADD28_I_I]], %[[IF_END31_I_I]] ], [ 0, %[[IF_ELSE17_I_I]] ], [ [[SUB_I25_I]], %[[IF_THEN_I21_I]] ], [ 0, %[[WHILE_BODY_I18_I]] ] +// CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi i64 [ 0, %[[IF_THEN_I]] ], [ 0, %[[ENTRY]] ], [ [[SUB_I34_I]], %[[IF_THEN_I30_I]] ], [ 0, %[[WHILE_BODY_I25_I]] ], [ [[SUB_I21_I]], %[[IF_THEN_I17_I]] ], [ 0, %[[WHILE_BODY_I14_I]] ], [ [[__R_1_I_I]], %[[IF_END31_I_I]] ], [ 0, %[[IF_ELSE17_I_I]] ] // CHECK-NEXT: ret i64 [[RETVAL_0_I]] // // AMDGCNSPIRV-LABEL: define spir_func i64 @test___make_mantissa( @@ -322,79 +357,91 @@ extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { // AMDGCNSPIRV-NEXT: [[ENTRY:.*]]: // AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load i8, ptr addrspace(4) [[P]], align 1, !tbaa [[CHAR_TBAA9]] // AMDGCNSPIRV-NEXT: [[CMP_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_I]], label %[[IF_THEN_I:.*]], label %[[WHILE_COND_I14_I:.*]] +// AMDGCNSPIRV-NEXT: br i1 [[CMP_I]], label %[[IF_THEN_I:.*]], label %[[WHILE_COND_I23_I:.*]] // AMDGCNSPIRV: [[IF_THEN_I]]: // AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[P]], i64 1 // AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I]], align 1, !tbaa [[CHAR_TBAA9]] // AMDGCNSPIRV-NEXT: switch i8 [[TMP1]], label %[[WHILE_COND_I_I:.*]] [ -// AMDGCNSPIRV-NEXT: i8 120, label %[[IF_THEN5_I:.*]] -// AMDGCNSPIRV-NEXT: i8 88, label %[[IF_THEN5_I]] +// AMDGCNSPIRV-NEXT: i8 88, label %[[WHILE_BODY_I_I_PREHEADER:.*]] +// AMDGCNSPIRV-NEXT: i8 120, label %[[WHILE_BODY_I_I_PREHEADER]] // AMDGCNSPIRV-NEXT: ] -// AMDGCNSPIRV: [[IF_THEN5_I]]: -// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I31_I5:%.*]] = icmp eq i8 [[TMP2]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I31_I5]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT:.*]], label %[[WHILE_BODY_I32_I:.*]] -// AMDGCNSPIRV: [[WHILE_BODY_I32_I]]: -// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = phi i8 [ [[TMP7:%.*]], %[[IF_END31_I_I:.*]] ], [ [[TMP2]], %[[IF_THEN5_I]] ] -// AMDGCNSPIRV-NEXT: [[__R_0_I30_I7:%.*]] = phi i64 [ [[ADD28_I_I:%.*]], %[[IF_END31_I_I]] ], [ 0, %[[IF_THEN5_I]] ] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I29_I6:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I36_I:%.*]], %[[IF_END31_I_I]] ], [ [[INCDEC_PTR_I]], %[[IF_THEN5_I]] ] -// AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = add i8 [[TMP3]], -48 -// AMDGCNSPIRV-NEXT: [[OR_COND_I33_I:%.*]] = icmp ult i8 [[TMP4]], 10 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I33_I]], label %[[IF_END31_I_I]], label %[[IF_ELSE_I_I:.*]] +// AMDGCNSPIRV: [[WHILE_BODY_I_I_PREHEADER]]: +// AMDGCNSPIRV-NEXT: br label %[[WHILE_BODY_I_I:.*]] +// AMDGCNSPIRV: [[WHILE_BODY_I_I]]: +// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = phi i8 [ [[TMP6:%.*]], %[[IF_END31_I_I:.*]] ], [ [[TMP1]], %[[WHILE_BODY_I_I_PREHEADER]] ] +// AMDGCNSPIRV-NEXT: [[__R_050_I_I:%.*]] = phi i64 [ [[__R_1_I_I:%.*]], %[[IF_END31_I_I]] ], [ 0, %[[WHILE_BODY_I_I_PREHEADER]] ] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_049_I_I:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I_I:%.*]], %[[IF_END31_I_I]] ], [ [[INCDEC_PTR_I]], %[[WHILE_BODY_I_I_PREHEADER]] ] +// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 +// AMDGCNSPIRV-NEXT: [[OR_COND_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I_I]], label %[[IF_THEN_I_I:.*]], label %[[IF_ELSE_I_I:.*]] +// AMDGCNSPIRV: [[IF_THEN_I_I]]: +// AMDGCNSPIRV-NEXT: [[MUL_I_I:%.*]] = shl i64 [[__R_050_I_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV5_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD_I_I:%.*]] = add nsw i64 [[CONV5_I_I]], -48 +// AMDGCNSPIRV-NEXT: [[SUB_I_I:%.*]] = or disjoint i64 [[ADD_I_I]], [[MUL_I_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I_I]] // AMDGCNSPIRV: [[IF_ELSE_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP5:%.*]] = add i8 [[TMP3]], -97 -// AMDGCNSPIRV-NEXT: [[OR_COND33_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND33_I_I]], label %[[IF_END31_I_I]], label %[[IF_ELSE17_I_I:.*]] +// AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 +// AMDGCNSPIRV-NEXT: [[OR_COND33_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND33_I_I]], label %[[IF_THEN11_I_I:.*]], label %[[IF_ELSE17_I_I:.*]] +// AMDGCNSPIRV: [[IF_THEN11_I_I]]: +// AMDGCNSPIRV-NEXT: [[MUL12_I_I:%.*]] = shl i64 [[__R_050_I_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV13_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD14_I_I:%.*]] = add nsw i64 [[CONV13_I_I]], -87 +// AMDGCNSPIRV-NEXT: [[ADD16_I_I:%.*]] = add i64 [[ADD14_I_I]], [[MUL12_I_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I_I]] // AMDGCNSPIRV: [[IF_ELSE17_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP6:%.*]] = add i8 [[TMP3]], -65 -// AMDGCNSPIRV-NEXT: [[OR_COND34_I_I:%.*]] = icmp ult i8 [[TMP6]], 6 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND34_I_I]], label %[[IF_END31_I_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]] +// AMDGCNSPIRV-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 +// AMDGCNSPIRV-NEXT: [[OR_COND34_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND34_I_I]], label %[[IF_THEN23_I_I:.*]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT:.*]] +// AMDGCNSPIRV: [[IF_THEN23_I_I]]: +// AMDGCNSPIRV-NEXT: [[MUL24_I_I:%.*]] = shl i64 [[__R_050_I_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV25_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD26_I_I:%.*]] = add nsw i64 [[CONV25_I_I]], -55 +// AMDGCNSPIRV-NEXT: [[ADD28_I_I:%.*]] = add i64 [[ADD26_I_I]], [[MUL24_I_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I_I]] // AMDGCNSPIRV: [[IF_END31_I_I]]: -// AMDGCNSPIRV-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I32_I]] ], [ -87, %[[IF_ELSE_I_I]] ], [ -55, %[[IF_ELSE17_I_I]] ] -// AMDGCNSPIRV-NEXT: [[MUL24_I_I:%.*]] = shl i64 [[__R_0_I30_I7]], 4 -// AMDGCNSPIRV-NEXT: [[CONV25_I_I:%.*]] = zext nneg i8 [[TMP3]] to i64 -// AMDGCNSPIRV-NEXT: [[ADD26_I_I:%.*]] = add i64 [[MUL24_I_I]], [[DOTSINK]] -// AMDGCNSPIRV-NEXT: [[ADD28_I_I]] = add i64 [[ADD26_I_I]], [[CONV25_I_I]] -// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I36_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I29_I6]], i64 1 -// AMDGCNSPIRV-NEXT: [[TMP7]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I36_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I31_I:%.*]] = icmp eq i8 [[TMP7]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I31_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I32_I]], !llvm.loop [[LOOP14]] +// AMDGCNSPIRV-NEXT: [[__R_1_I_I]] = phi i64 [ [[SUB_I_I]], %[[IF_THEN_I_I]] ], [ [[ADD16_I_I]], %[[IF_THEN11_I_I]] ], [ [[ADD28_I_I]], %[[IF_THEN23_I_I]] ] +// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_049_I_I]], i64 1 +// AMDGCNSPIRV-NEXT: [[TMP6]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA9]] +// AMDGCNSPIRV-NEXT: [[CMP_NOT_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I_I]], !llvm.loop [[LOOP14]] // AMDGCNSPIRV: [[WHILE_COND_I_I]]: -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I_I:%.*]], %[[WHILE_BODY_I_I:.*]] ], [ [[INCDEC_PTR_I]], %[[IF_THEN_I]] ] -// AMDGCNSPIRV-NEXT: [[__R_0_I_I:%.*]] = phi i64 [ [[__R_1_I_I:%.*]], %[[WHILE_BODY_I_I]] ], [ 0, %[[IF_THEN_I]] ] -// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I_I]] -// AMDGCNSPIRV: [[WHILE_BODY_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP9:%.*]] = and i8 [[TMP8]], -8 -// AMDGCNSPIRV-NEXT: [[OR_COND_I_I:%.*]] = icmp eq i8 [[TMP9]], 48 -// AMDGCNSPIRV-NEXT: [[MUL_I_I:%.*]] = shl i64 [[__R_0_I_I]], 3 -// AMDGCNSPIRV-NEXT: [[CONV5_I_I:%.*]] = zext nneg i8 [[TMP8]] to i64 -// AMDGCNSPIRV-NEXT: [[ADD_I_I:%.*]] = add i64 [[MUL_I_I]], -48 -// AMDGCNSPIRV-NEXT: [[SUB_I_I:%.*]] = add i64 [[ADD_I_I]], [[CONV5_I_I]] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_I_IDX:%.*]] = zext i1 [[OR_COND_I_I]] to i64 -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I]], i64 [[__TAGP_ADDR_1_I_I_IDX]] -// AMDGCNSPIRV-NEXT: [[__R_1_I_I]] = select i1 [[OR_COND_I_I]], i64 [[SUB_I_I]], i64 [[__R_0_I_I]] -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I_I]], label %[[WHILE_COND_I_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP10]] -// AMDGCNSPIRV: [[WHILE_COND_I14_I]]: -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I15_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I25_I:%.*]], %[[WHILE_BODY_I18_I:.*]] ], [ [[P]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__R_0_I16_I:%.*]] = phi i64 [ [[__R_1_I26_I:%.*]], %[[WHILE_BODY_I18_I]] ], [ 0, %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[TMP10:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I15_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I17_I:%.*]] = icmp eq i8 [[TMP10]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I17_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I18_I]] -// AMDGCNSPIRV: [[WHILE_BODY_I18_I]]: -// AMDGCNSPIRV-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], -48 -// AMDGCNSPIRV-NEXT: [[OR_COND_I19_I:%.*]] = icmp ult i8 [[TMP11]], 10 -// AMDGCNSPIRV-NEXT: [[MUL_I20_I:%.*]] = mul i64 [[__R_0_I16_I]], 10 -// AMDGCNSPIRV-NEXT: [[CONV5_I21_I:%.*]] = zext nneg i8 [[TMP10]] to i64 -// AMDGCNSPIRV-NEXT: [[ADD_I22_I:%.*]] = add i64 [[MUL_I20_I]], -48 -// AMDGCNSPIRV-NEXT: [[SUB_I23_I:%.*]] = add i64 [[ADD_I22_I]], [[CONV5_I21_I]] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I25_I_IDX:%.*]] = zext i1 [[OR_COND_I19_I]] to i64 -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I25_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I15_I]], i64 [[__TAGP_ADDR_1_I25_I_IDX]] -// AMDGCNSPIRV-NEXT: [[__R_1_I26_I]] = select i1 [[OR_COND_I19_I]], i64 [[SUB_I23_I]], i64 [[__R_0_I16_I]] -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I19_I]], label %[[WHILE_COND_I14_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP13]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I_I:%.*]], %[[WHILE_BODY_I15_I:.*]] ], [ [[INCDEC_PTR_I]], %[[IF_THEN_I]] ] +// AMDGCNSPIRV-NEXT: [[__R_0_I_I:%.*]] = phi i64 [ [[__R_1_I21_I:%.*]], %[[WHILE_BODY_I15_I]] ], [ 0, %[[IF_THEN_I]] ] +// AMDGCNSPIRV-NEXT: [[TMP7:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I]], align 1, !tbaa [[CHAR_TBAA9]] +// AMDGCNSPIRV-NEXT: [[CMP_NOT_I14_I:%.*]] = icmp eq i8 [[TMP7]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I14_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I15_I]] +// AMDGCNSPIRV: [[WHILE_BODY_I15_I]]: +// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], -8 +// AMDGCNSPIRV-NEXT: [[OR_COND_I16_I:%.*]] = icmp eq i8 [[TMP8]], 48 +// AMDGCNSPIRV-NEXT: [[MUL_I17_I:%.*]] = shl i64 [[__R_0_I_I]], 3 +// AMDGCNSPIRV-NEXT: [[CONV5_I18_I:%.*]] = zext nneg i8 [[TMP7]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD_I19_I:%.*]] = add i64 [[MUL_I17_I]], -48 +// AMDGCNSPIRV-NEXT: [[SUB_I20_I:%.*]] = add i64 [[ADD_I19_I]], [[CONV5_I18_I]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_IDX_I_I:%.*]] = zext i1 [[OR_COND_I16_I]] to i64 +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I]], i64 [[__TAGP_ADDR_1_IDX_I_I]] +// AMDGCNSPIRV-NEXT: [[__R_1_I21_I]] = select i1 [[OR_COND_I16_I]], i64 [[SUB_I20_I]], i64 [[__R_0_I_I]] +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I16_I]], label %[[WHILE_COND_I_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP10]] +// AMDGCNSPIRV: [[WHILE_COND_I23_I]]: +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I24_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I34_I:%.*]], %[[WHILE_BODY_I27_I:.*]] ], [ [[P]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__R_0_I25_I:%.*]] = phi i64 [ [[__R_1_I35_I:%.*]], %[[WHILE_BODY_I27_I]] ], [ 0, %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[TMP9:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I24_I]], align 1, !tbaa [[CHAR_TBAA9]] +// AMDGCNSPIRV-NEXT: [[CMP_NOT_I26_I:%.*]] = icmp eq i8 [[TMP9]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I26_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], label %[[WHILE_BODY_I27_I]] +// AMDGCNSPIRV: [[WHILE_BODY_I27_I]]: +// AMDGCNSPIRV-NEXT: [[TMP10:%.*]] = add i8 [[TMP9]], -48 +// AMDGCNSPIRV-NEXT: [[OR_COND_I28_I:%.*]] = icmp ult i8 [[TMP10]], 10 +// AMDGCNSPIRV-NEXT: [[MUL_I29_I:%.*]] = mul i64 [[__R_0_I25_I]], 10 +// AMDGCNSPIRV-NEXT: [[CONV5_I30_I:%.*]] = zext nneg i8 [[TMP9]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD_I31_I:%.*]] = add i64 [[MUL_I29_I]], -48 +// AMDGCNSPIRV-NEXT: [[SUB_I32_I:%.*]] = add i64 [[ADD_I31_I]], [[CONV5_I30_I]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_IDX_I33_I:%.*]] = zext i1 [[OR_COND_I28_I]] to i64 +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I34_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I24_I]], i64 [[__TAGP_ADDR_1_IDX_I33_I]] +// AMDGCNSPIRV-NEXT: [[__R_1_I35_I]] = select i1 [[OR_COND_I28_I]], i64 [[SUB_I32_I]], i64 [[__R_0_I25_I]] +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I28_I]], label %[[WHILE_COND_I23_I]], label %[[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP13]] // AMDGCNSPIRV: [[_ZL15__MAKE_MANTISSAPKC_EXIT]]: -// AMDGCNSPIRV-NEXT: [[RETVAL_0_I:%.*]] = phi i64 [ 0, %[[IF_THEN5_I]] ], [ 0, %[[WHILE_BODY_I_I]] ], [ [[__R_0_I_I]], %[[WHILE_COND_I_I]] ], [ [[ADD28_I_I]], %[[IF_END31_I_I]] ], [ 0, %[[IF_ELSE17_I_I]] ], [ 0, %[[WHILE_BODY_I18_I]] ], [ [[__R_0_I16_I]], %[[WHILE_COND_I14_I]] ] +// AMDGCNSPIRV-NEXT: [[RETVAL_0_I:%.*]] = phi i64 [ 0, %[[WHILE_BODY_I15_I]] ], [ [[__R_0_I_I]], %[[WHILE_COND_I_I]] ], [ [[__R_1_I_I]], %[[IF_END31_I_I]] ], [ 0, %[[IF_ELSE17_I_I]] ], [ 0, %[[WHILE_BODY_I27_I]] ], [ [[__R_0_I25_I]], %[[WHILE_COND_I23_I]] ] // AMDGCNSPIRV-NEXT: ret i64 [[RETVAL_0_I]] // extern "C" __device__ uint64_t test___make_mantissa(const char *p) { @@ -1145,8 +1192,8 @@ extern "C" __device__ double test_copysign(double x, double y) { // APPROX-LABEL: define dso_local noundef float @test_cosf( // APPROX-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR6:[0-9]+]] { // APPROX-NEXT: [[ENTRY:.*:]] -// APPROX-NEXT: [[CALL_I1:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14:[0-9]+]] -// APPROX-NEXT: ret float [[CALL_I1]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14:[0-9]+]] +// APPROX-NEXT: ret float [[CALL_I_I]] // // NCRDIV-LABEL: define dso_local noundef float @test_cosf( // NCRDIV-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR6:[0-9]+]] { @@ -3038,30 +3085,30 @@ extern "C" __device__ double test_j1(double x) { // DEFAULT-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // DEFAULT-NEXT: ] // DEFAULT: [[IF_THEN_I]]: -// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] // DEFAULT-NEXT: br label %[[_ZL3JNFIF_EXIT:.*]] // DEFAULT: [[IF_THEN2_I]]: -// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] // DEFAULT-NEXT: br label %[[_ZL3JNFIF_EXIT]] // DEFAULT: [[IF_END4_I]]: -// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] -// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] -// DEFAULT-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// DEFAULT-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL3JNFIF_EXIT]] +// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// DEFAULT-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL3JNFIF_EXIT]] // DEFAULT: [[FOR_BODY_I]]: -// DEFAULT-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// DEFAULT-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // DEFAULT-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float // DEFAULT-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]] -// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] -// DEFAULT-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] -// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL3JNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] +// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] +// DEFAULT-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] +// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// DEFAULT-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// DEFAULT-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL3JNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] // DEFAULT: [[_ZL3JNFIF_EXIT]]: -// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // DEFAULT-NEXT: ret float [[RETVAL_0_I]] // // FINITEONLY-LABEL: define dso_local nofpclass(nan inf) float @test_jnf( @@ -3072,30 +3119,30 @@ extern "C" __device__ double test_j1(double x) { // FINITEONLY-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // FINITEONLY-NEXT: ] // FINITEONLY: [[IF_THEN_I]]: -// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] // FINITEONLY-NEXT: br label %[[_ZL3JNFIF_EXIT:.*]] // FINITEONLY: [[IF_THEN2_I]]: -// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] // FINITEONLY-NEXT: br label %[[_ZL3JNFIF_EXIT]] // FINITEONLY: [[IF_END4_I]]: -// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] -// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] -// FINITEONLY-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// FINITEONLY-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL3JNFIF_EXIT]] +// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_j1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// FINITEONLY-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL3JNFIF_EXIT]] // FINITEONLY: [[FOR_BODY_I]]: -// FINITEONLY-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// FINITEONLY-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // FINITEONLY-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float // FINITEONLY-NEXT: [[DIV_I:%.*]] = fdiv nnan ninf contract float [[CONV_I]], [[Y]] -// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract float [[__X1_0_I3]], [[DIV_I]] -// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract float [[MUL8_I]], [[__X0_0_I2]] -// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// FINITEONLY-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL3JNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] +// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract float [[__X1_025_I]], [[DIV_I]] +// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract float [[MUL8_I]], [[__X0_024_I]] +// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// FINITEONLY-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL3JNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] // FINITEONLY: [[_ZL3JNFIF_EXIT]]: -// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // FINITEONLY-NEXT: ret float [[RETVAL_0_I]] // // APPROX-LABEL: define dso_local float @test_jnf( @@ -3106,30 +3153,30 @@ extern "C" __device__ double test_j1(double x) { // APPROX-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // APPROX-NEXT: ] // APPROX: [[IF_THEN_I]]: -// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] // APPROX-NEXT: br label %[[_ZL3JNFIF_EXIT:.*]] // APPROX: [[IF_THEN2_I]]: -// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] // APPROX-NEXT: br label %[[_ZL3JNFIF_EXIT]] // APPROX: [[IF_END4_I]]: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] -// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] -// APPROX-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// APPROX-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL3JNFIF_EXIT]] +// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// APPROX-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL3JNFIF_EXIT]] // APPROX: [[FOR_BODY_I]]: -// APPROX-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// APPROX-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// APPROX-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// APPROX-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// APPROX-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// APPROX-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // APPROX-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float // APPROX-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]] -// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] -// APPROX-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] -// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// APPROX-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// APPROX-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL3JNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] +// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] +// APPROX-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] +// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// APPROX-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// APPROX-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL3JNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP14:![0-9]+]] // APPROX: [[_ZL3JNFIF_EXIT]]: -// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // APPROX-NEXT: ret float [[RETVAL_0_I]] // // NCRDIV-LABEL: define dso_local float @test_jnf( @@ -3140,30 +3187,30 @@ extern "C" __device__ double test_j1(double x) { // NCRDIV-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // NCRDIV-NEXT: ] // NCRDIV: [[IF_THEN_I]]: -// NCRDIV-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] // NCRDIV-NEXT: br label %[[_ZL3JNFIF_EXIT:.*]] // NCRDIV: [[IF_THEN2_I]]: -// NCRDIV-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] // NCRDIV-NEXT: br label %[[_ZL3JNFIF_EXIT]] // NCRDIV: [[IF_END4_I]]: -// NCRDIV-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] -// NCRDIV-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] -// NCRDIV-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// NCRDIV-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL3JNFIF_EXIT]] +// NCRDIV-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// NCRDIV-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL3JNFIF_EXIT]] // NCRDIV: [[FOR_BODY_I]]: -// NCRDIV-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// NCRDIV-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // NCRDIV-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float // NCRDIV-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]], !fpmath [[META14]] -// NCRDIV-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] -// NCRDIV-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] -// NCRDIV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// NCRDIV-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// NCRDIV-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL3JNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] +// NCRDIV-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] +// NCRDIV-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] +// NCRDIV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// NCRDIV-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// NCRDIV-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL3JNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] // NCRDIV: [[_ZL3JNFIF_EXIT]]: -// NCRDIV-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// NCRDIV-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // NCRDIV-NEXT: ret float [[RETVAL_0_I]] // // AMDGCNSPIRV-LABEL: define spir_func float @test_jnf( @@ -3174,30 +3221,30 @@ extern "C" __device__ double test_j1(double x) { // AMDGCNSPIRV-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // AMDGCNSPIRV-NEXT: ] // AMDGCNSPIRV: [[IF_THEN_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I20_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] // AMDGCNSPIRV-NEXT: br label %[[_ZL3JNFIF_EXIT:.*]] // AMDGCNSPIRV: [[IF_THEN2_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I22_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I20_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] // AMDGCNSPIRV-NEXT: br label %[[_ZL3JNFIF_EXIT]] // AMDGCNSPIRV: [[IF_END4_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] -// AMDGCNSPIRV-NEXT: [[CALL_I21_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] -// AMDGCNSPIRV-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// AMDGCNSPIRV-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL3JNFIF_EXIT]] +// AMDGCNSPIRV-NEXT: [[CALL_I21_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I22_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// AMDGCNSPIRV-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL3JNFIF_EXIT]] // AMDGCNSPIRV: [[FOR_BODY_I]]: -// AMDGCNSPIRV-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// AMDGCNSPIRV-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // AMDGCNSPIRV-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float // AMDGCNSPIRV-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]] -// AMDGCNSPIRV-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] -// AMDGCNSPIRV-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] -// AMDGCNSPIRV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// AMDGCNSPIRV-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// AMDGCNSPIRV-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL3JNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] +// AMDGCNSPIRV-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] +// AMDGCNSPIRV-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] +// AMDGCNSPIRV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// AMDGCNSPIRV-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// AMDGCNSPIRV-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL3JNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] // AMDGCNSPIRV: [[_ZL3JNFIF_EXIT]]: -// AMDGCNSPIRV-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// AMDGCNSPIRV-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // AMDGCNSPIRV-NEXT: ret float [[RETVAL_0_I]] // extern "C" __device__ float test_jnf(int x, float y) { @@ -3212,30 +3259,30 @@ extern "C" __device__ float test_jnf(int x, float y) { // DEFAULT-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // DEFAULT-NEXT: ] // DEFAULT: [[IF_THEN_I]]: -// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] // DEFAULT-NEXT: br label %[[_ZL2JNID_EXIT:.*]] // DEFAULT: [[IF_THEN2_I]]: -// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] // DEFAULT-NEXT: br label %[[_ZL2JNID_EXIT]] // DEFAULT: [[IF_END4_I]]: -// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] -// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] -// DEFAULT-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// DEFAULT-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL2JNID_EXIT]] +// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// DEFAULT-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL2JNID_EXIT]] // DEFAULT: [[FOR_BODY_I]]: -// DEFAULT-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// DEFAULT-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // DEFAULT-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double // DEFAULT-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] -// DEFAULT-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] -// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL2JNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] +// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] +// DEFAULT-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] +// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// DEFAULT-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// DEFAULT-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL2JNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] // DEFAULT: [[_ZL2JNID_EXIT]]: -// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // DEFAULT-NEXT: ret double [[RETVAL_0_I]] // // FINITEONLY-LABEL: define dso_local nofpclass(nan inf) double @test_jn( @@ -3246,30 +3293,30 @@ extern "C" __device__ float test_jnf(int x, float y) { // FINITEONLY-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // FINITEONLY-NEXT: ] // FINITEONLY: [[IF_THEN_I]]: -// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] // FINITEONLY-NEXT: br label %[[_ZL2JNID_EXIT:.*]] // FINITEONLY: [[IF_THEN2_I]]: -// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] // FINITEONLY-NEXT: br label %[[_ZL2JNID_EXIT]] // FINITEONLY: [[IF_END4_I]]: -// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] -// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] -// FINITEONLY-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// FINITEONLY-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL2JNID_EXIT]] +// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_j1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// FINITEONLY-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL2JNID_EXIT]] // FINITEONLY: [[FOR_BODY_I]]: -// FINITEONLY-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// FINITEONLY-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // FINITEONLY-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double // FINITEONLY-NEXT: [[DIV_I:%.*]] = fdiv nnan ninf contract double [[CONV_I]], [[Y]] -// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract double [[__X1_0_I3]], [[DIV_I]] -// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract double [[MUL8_I]], [[__X0_0_I2]] -// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// FINITEONLY-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL2JNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] +// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract double [[__X1_025_I]], [[DIV_I]] +// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract double [[MUL8_I]], [[__X0_024_I]] +// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// FINITEONLY-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL2JNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] // FINITEONLY: [[_ZL2JNID_EXIT]]: -// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // FINITEONLY-NEXT: ret double [[RETVAL_0_I]] // // APPROX-LABEL: define dso_local double @test_jn( @@ -3280,30 +3327,30 @@ extern "C" __device__ float test_jnf(int x, float y) { // APPROX-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // APPROX-NEXT: ] // APPROX: [[IF_THEN_I]]: -// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] // APPROX-NEXT: br label %[[_ZL2JNID_EXIT:.*]] // APPROX: [[IF_THEN2_I]]: -// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] // APPROX-NEXT: br label %[[_ZL2JNID_EXIT]] // APPROX: [[IF_END4_I]]: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] -// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] -// APPROX-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// APPROX-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL2JNID_EXIT]] +// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// APPROX-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL2JNID_EXIT]] // APPROX: [[FOR_BODY_I]]: -// APPROX-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// APPROX-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// APPROX-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// APPROX-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// APPROX-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// APPROX-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // APPROX-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double // APPROX-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] -// APPROX-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] -// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// APPROX-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// APPROX-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL2JNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] +// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] +// APPROX-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] +// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// APPROX-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// APPROX-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL2JNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]] // APPROX: [[_ZL2JNID_EXIT]]: -// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // APPROX-NEXT: ret double [[RETVAL_0_I]] // // NCRDIV-LABEL: define dso_local double @test_jn( @@ -3314,30 +3361,30 @@ extern "C" __device__ float test_jnf(int x, float y) { // NCRDIV-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // NCRDIV-NEXT: ] // NCRDIV: [[IF_THEN_I]]: -// NCRDIV-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] // NCRDIV-NEXT: br label %[[_ZL2JNID_EXIT:.*]] // NCRDIV: [[IF_THEN2_I]]: -// NCRDIV-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] // NCRDIV-NEXT: br label %[[_ZL2JNID_EXIT]] // NCRDIV: [[IF_END4_I]]: -// NCRDIV-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] -// NCRDIV-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] -// NCRDIV-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// NCRDIV-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL2JNID_EXIT]] +// NCRDIV-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// NCRDIV-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL2JNID_EXIT]] // NCRDIV: [[FOR_BODY_I]]: -// NCRDIV-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// NCRDIV-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // NCRDIV-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double // NCRDIV-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// NCRDIV-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] -// NCRDIV-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] -// NCRDIV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// NCRDIV-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// NCRDIV-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL2JNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP16:![0-9]+]] +// NCRDIV-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] +// NCRDIV-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] +// NCRDIV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// NCRDIV-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// NCRDIV-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL2JNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP16:![0-9]+]] // NCRDIV: [[_ZL2JNID_EXIT]]: -// NCRDIV-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// NCRDIV-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // NCRDIV-NEXT: ret double [[RETVAL_0_I]] // // AMDGCNSPIRV-LABEL: define spir_func double @test_jn( @@ -3348,30 +3395,30 @@ extern "C" __device__ float test_jnf(int x, float y) { // AMDGCNSPIRV-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // AMDGCNSPIRV-NEXT: ] // AMDGCNSPIRV: [[IF_THEN_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I20_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] // AMDGCNSPIRV-NEXT: br label %[[_ZL2JNID_EXIT:.*]] // AMDGCNSPIRV: [[IF_THEN2_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I22_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I20_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] // AMDGCNSPIRV-NEXT: br label %[[_ZL2JNID_EXIT]] // AMDGCNSPIRV: [[IF_END4_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] -// AMDGCNSPIRV-NEXT: [[CALL_I21_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] -// AMDGCNSPIRV-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// AMDGCNSPIRV-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL2JNID_EXIT]] +// AMDGCNSPIRV-NEXT: [[CALL_I21_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I22_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// AMDGCNSPIRV-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL2JNID_EXIT]] // AMDGCNSPIRV: [[FOR_BODY_I]]: -// AMDGCNSPIRV-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// AMDGCNSPIRV-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // AMDGCNSPIRV-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double // AMDGCNSPIRV-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// AMDGCNSPIRV-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] -// AMDGCNSPIRV-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] -// AMDGCNSPIRV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// AMDGCNSPIRV-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// AMDGCNSPIRV-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL2JNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP16:![0-9]+]] +// AMDGCNSPIRV-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] +// AMDGCNSPIRV-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] +// AMDGCNSPIRV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// AMDGCNSPIRV-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// AMDGCNSPIRV-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL2JNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP16:![0-9]+]] // AMDGCNSPIRV: [[_ZL2JNID_EXIT]]: -// AMDGCNSPIRV-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// AMDGCNSPIRV-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // AMDGCNSPIRV-NEXT: ret double [[RETVAL_0_I]] // extern "C" __device__ double test_jn(int x, double y) { @@ -4254,362 +4301,395 @@ extern "C" __device__ double test_modf(double x, double* y) { // DEFAULT-LABEL: define dso_local float @test_nanf( // DEFAULT-SAME: ptr noundef readonly captures(none) [[TAG:%.*]]) local_unnamed_addr #[[ATTR2]] { -// DEFAULT-NEXT: [[ENTRY:.*:]] +// DEFAULT-NEXT: [[ENTRY:.*]]: // DEFAULT-NEXT: [[TMP0:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// DEFAULT-NEXT: br i1 [[CMP_I_I]], label %[[IF_THEN_I_I:.*]], label %[[WHILE_COND_I14_I_I_PREHEADER:.*]] -// DEFAULT: [[WHILE_COND_I14_I_I_PREHEADER]]: -// DEFAULT-NEXT: [[TMP1:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I17_I_I5:%.*]] = icmp eq i8 [[TMP1]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I17_I_I5]], label %[[_ZL4NANFPKC_EXIT:.*]], label %[[WHILE_BODY_I18_I_I:.*]] +// DEFAULT-NEXT: switch i8 [[TMP0]], label %[[WHILE_BODY_I25_I_I:.*]] [ +// DEFAULT-NEXT: i8 48, label %[[IF_THEN_I_I:.*]] +// DEFAULT-NEXT: i8 0, label %[[_ZL4NANFPKC_EXIT:.*]] +// DEFAULT-NEXT: ] // DEFAULT: [[IF_THEN_I_I]]: // DEFAULT-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TAG]], i64 1 -// DEFAULT-NEXT: [[TMP2:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: switch i8 [[TMP2]], label %[[WHILE_COND_I_I_I_PREHEADER:.*]] [ -// DEFAULT-NEXT: i8 120, label %[[IF_THEN5_I_I:.*]] -// DEFAULT-NEXT: i8 88, label %[[IF_THEN5_I_I]] +// DEFAULT-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// DEFAULT-NEXT: switch i8 [[TMP1]], label %[[WHILE_BODY_I14_I_I:.*]] [ +// DEFAULT-NEXT: i8 88, label %[[WHILE_BODY_I_I_I_PREHEADER:.*]] +// DEFAULT-NEXT: i8 120, label %[[WHILE_BODY_I_I_I_PREHEADER]] +// DEFAULT-NEXT: i8 0, label %[[_ZL4NANFPKC_EXIT]] // DEFAULT-NEXT: ] -// DEFAULT: [[WHILE_COND_I_I_I_PREHEADER]]: -// DEFAULT-NEXT: [[TMP3:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I_I_I14:%.*]] = icmp eq i8 [[TMP3]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I_I_I14]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I:.*]] -// DEFAULT: [[IF_THEN5_I_I]]: -// DEFAULT-NEXT: [[TMP4:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I30_I_I9:%.*]] = icmp eq i8 [[TMP4]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I30_I_I9]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I31_I_I:.*]] -// DEFAULT: [[WHILE_BODY_I31_I_I]]: -// DEFAULT-NEXT: [[TMP5:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP4]], %[[IF_THEN5_I_I]] ] -// DEFAULT-NEXT: [[__R_0_I29_I_I11:%.*]] = phi i64 [ [[ADD28_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_THEN5_I_I]] ] -// DEFAULT-NEXT: [[__TAGP_ADDR_0_I28_I_I10:%.*]] = phi ptr [ [[INCDEC_PTR_I34_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN5_I_I]] ] -// DEFAULT-NEXT: [[TMP6:%.*]] = add i8 [[TMP5]], -48 -// DEFAULT-NEXT: [[OR_COND_I32_I_I:%.*]] = icmp ult i8 [[TMP6]], 10 -// DEFAULT-NEXT: br i1 [[OR_COND_I32_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE_I_I_I:.*]] +// DEFAULT: [[WHILE_BODY_I_I_I_PREHEADER]]: +// DEFAULT-NEXT: br label %[[WHILE_BODY_I_I_I:.*]] +// DEFAULT: [[WHILE_BODY_I_I_I]]: +// DEFAULT-NEXT: [[TMP2:%.*]] = phi i8 [ [[TMP6:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP1]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// DEFAULT-NEXT: [[__R_050_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// DEFAULT-NEXT: [[__TAGP_ADDR_049_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// DEFAULT-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 +// DEFAULT-NEXT: [[OR_COND_I_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// DEFAULT-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I:.*]], label %[[IF_ELSE_I_I_I:.*]] +// DEFAULT: [[IF_THEN_I_I_I]]: +// DEFAULT-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// DEFAULT-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// DEFAULT-NEXT: [[ADD_I_I_I:%.*]] = add nsw i64 [[CONV5_I_I_I]], -48 +// DEFAULT-NEXT: [[SUB_I_I_I:%.*]] = or disjoint i64 [[ADD_I_I_I]], [[MUL_I_I_I]] +// DEFAULT-NEXT: br label %[[IF_END31_I_I_I]] // DEFAULT: [[IF_ELSE_I_I_I]]: -// DEFAULT-NEXT: [[TMP7:%.*]] = add i8 [[TMP5]], -97 -// DEFAULT-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP7]], 6 -// DEFAULT-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE17_I_I_I:.*]] +// DEFAULT-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 +// DEFAULT-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 +// DEFAULT-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_THEN11_I_I_I:.*]], label %[[IF_ELSE17_I_I_I:.*]] +// DEFAULT: [[IF_THEN11_I_I_I]]: +// DEFAULT-NEXT: [[MUL12_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// DEFAULT-NEXT: [[CONV13_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// DEFAULT-NEXT: [[ADD14_I_I_I:%.*]] = add nsw i64 [[CONV13_I_I_I]], -87 +// DEFAULT-NEXT: [[ADD16_I_I_I:%.*]] = add i64 [[ADD14_I_I_I]], [[MUL12_I_I_I]] +// DEFAULT-NEXT: br label %[[IF_END31_I_I_I]] // DEFAULT: [[IF_ELSE17_I_I_I]]: -// DEFAULT-NEXT: [[TMP8:%.*]] = add i8 [[TMP5]], -65 -// DEFAULT-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP8]], 6 -// DEFAULT-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_END31_I_I_I]], label %[[_ZL4NANFPKC_EXIT]] +// DEFAULT-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 +// DEFAULT-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 +// DEFAULT-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_THEN23_I_I_I:.*]], label %[[_ZL4NANFPKC_EXIT]] +// DEFAULT: [[IF_THEN23_I_I_I]]: +// DEFAULT-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// DEFAULT-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// DEFAULT-NEXT: [[ADD26_I_I_I:%.*]] = add nsw i64 [[CONV25_I_I_I]], -55 +// DEFAULT-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[MUL24_I_I_I]] +// DEFAULT-NEXT: br label %[[IF_END31_I_I_I]] // DEFAULT: [[IF_END31_I_I_I]]: -// DEFAULT-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I31_I_I]] ], [ -87, %[[IF_ELSE_I_I_I]] ], [ -55, %[[IF_ELSE17_I_I_I]] ] -// DEFAULT-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I29_I_I11]], 4 -// DEFAULT-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP5]] to i64 -// DEFAULT-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] -// DEFAULT-NEXT: [[ADD28_I_I_I]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I34_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I28_I_I10]], i64 1 -// DEFAULT-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I34_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I30_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I30_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I31_I_I]], !llvm.loop [[LOOP13]] -// DEFAULT: [[WHILE_BODY_I_I_I]]: -// DEFAULT-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I_I_I:.*]] ], [ [[TMP3]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[__R_0_I_I_I16:%.*]] = phi i64 [ [[SUB_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[__TAGP_ADDR_0_I_I_I15:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[TMP11:%.*]] = and i8 [[TMP10]], -8 -// DEFAULT-NEXT: [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP11]], 48 -// DEFAULT-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I]], label %[[_ZL4NANFPKC_EXIT]] -// DEFAULT: [[IF_THEN_I_I_I]]: -// DEFAULT-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I16]], 3 -// DEFAULT-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 -// DEFAULT-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 -// DEFAULT-NEXT: [[SUB_I_I_I]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I_I_I15]], i64 1 -// DEFAULT-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP9]] -// DEFAULT: [[WHILE_BODY_I18_I_I]]: -// DEFAULT-NEXT: [[TMP13:%.*]] = phi i8 [ [[TMP15:%.*]], %[[IF_THEN_I21_I_I:.*]] ], [ [[TMP1]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[__R_0_I16_I_I7:%.*]] = phi i64 [ [[SUB_I25_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[__TAGP_ADDR_0_I15_I_I6:%.*]] = phi ptr [ [[INCDEC_PTR_I26_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ [[TAG]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[TMP14:%.*]] = add i8 [[TMP13]], -48 -// DEFAULT-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP14]], 10 -// DEFAULT-NEXT: br i1 [[OR_COND_I19_I_I]], label %[[IF_THEN_I21_I_I]], label %[[_ZL4NANFPKC_EXIT]] -// DEFAULT: [[IF_THEN_I21_I_I]]: -// DEFAULT-NEXT: [[MUL_I22_I_I:%.*]] = mul i64 [[__R_0_I16_I_I7]], 10 -// DEFAULT-NEXT: [[CONV5_I23_I_I:%.*]] = zext nneg i8 [[TMP13]] to i64 -// DEFAULT-NEXT: [[ADD_I24_I_I:%.*]] = add i64 [[MUL_I22_I_I]], -48 -// DEFAULT-NEXT: [[SUB_I25_I_I]] = add i64 [[ADD_I24_I_I]], [[CONV5_I23_I_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I26_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I15_I_I6]], i64 1 -// DEFAULT-NEXT: [[TMP15]] = load i8, ptr [[INCDEC_PTR_I26_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP15]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I17_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I18_I_I]], !llvm.loop [[LOOP12]] +// DEFAULT-NEXT: [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ [[ADD16_I_I_I]], %[[IF_THEN11_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_THEN23_I_I_I]] ] +// DEFAULT-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_049_I_I_I]], i64 1 +// DEFAULT-NEXT: [[TMP6]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// DEFAULT-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// DEFAULT-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP13]] +// DEFAULT: [[WHILE_BODY_I14_I_I]]: +// DEFAULT-NEXT: [[TMP7:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_THEN_I17_I_I:.*]] ], [ [[TMP1]], %[[IF_THEN_I_I]] ] +// DEFAULT-NEXT: [[__R_014_I_I_I:%.*]] = phi i64 [ [[SUB_I21_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[IF_THEN_I_I]] ] +// DEFAULT-NEXT: [[__TAGP_ADDR_013_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I22_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN_I_I]] ] +// DEFAULT-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], -8 +// DEFAULT-NEXT: [[OR_COND_I15_I_I:%.*]] = icmp eq i8 [[TMP8]], 48 +// DEFAULT-NEXT: br i1 [[OR_COND_I15_I_I]], label %[[IF_THEN_I17_I_I]], label %[[_ZL4NANFPKC_EXIT]] +// DEFAULT: [[IF_THEN_I17_I_I]]: +// DEFAULT-NEXT: [[MUL_I18_I_I:%.*]] = shl i64 [[__R_014_I_I_I]], 3 +// DEFAULT-NEXT: [[CONV5_I19_I_I:%.*]] = zext nneg i8 [[TMP7]] to i64 +// DEFAULT-NEXT: [[ADD_I20_I_I:%.*]] = add nsw i64 [[CONV5_I19_I_I]], -48 +// DEFAULT-NEXT: [[SUB_I21_I_I]] = or disjoint i64 [[ADD_I20_I_I]], [[MUL_I18_I_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I22_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I_I_I]], i64 1 +// DEFAULT-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I22_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// DEFAULT-NEXT: [[CMP_NOT_I23_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 +// DEFAULT-NEXT: br i1 [[CMP_NOT_I23_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I14_I_I]], !llvm.loop [[LOOP9]] +// DEFAULT: [[WHILE_BODY_I25_I_I]]: +// DEFAULT-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I30_I_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[__R_014_I26_I_I:%.*]] = phi i64 [ [[SUB_I34_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[ENTRY]] ] +// DEFAULT-NEXT: [[__TAGP_ADDR_013_I27_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I35_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ [[TAG]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], -48 +// DEFAULT-NEXT: [[OR_COND_I28_I_I:%.*]] = icmp ult i8 [[TMP11]], 10 +// DEFAULT-NEXT: br i1 [[OR_COND_I28_I_I]], label %[[IF_THEN_I30_I_I]], label %[[_ZL4NANFPKC_EXIT]] +// DEFAULT: [[IF_THEN_I30_I_I]]: +// DEFAULT-NEXT: [[MUL_I31_I_I:%.*]] = mul i64 [[__R_014_I26_I_I]], 10 +// DEFAULT-NEXT: [[CONV5_I32_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 +// DEFAULT-NEXT: [[ADD_I33_I_I:%.*]] = add nsw i64 [[CONV5_I32_I_I]], -48 +// DEFAULT-NEXT: [[SUB_I34_I_I]] = add i64 [[ADD_I33_I_I]], [[MUL_I31_I_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I35_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I27_I_I]], i64 1 +// DEFAULT-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I35_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// DEFAULT-NEXT: [[CMP_NOT_I36_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 +// DEFAULT-NEXT: br i1 [[CMP_NOT_I36_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I25_I_I]], !llvm.loop [[LOOP12]] // DEFAULT: [[_ZL4NANFPKC_EXIT]]: -// DEFAULT-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ], [ 0, %[[IF_THEN5_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ], [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ], [ [[SUB_I25_I_I]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_BODY_I18_I_I]] ] +// DEFAULT-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[IF_THEN_I_I]] ], [ 0, %[[ENTRY]] ], [ [[SUB_I34_I_I]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[WHILE_BODY_I25_I_I]] ], [ [[SUB_I21_I_I]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[WHILE_BODY_I14_I_I]] ], [ [[__R_1_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ] // DEFAULT-NEXT: [[CONV_I:%.*]] = trunc i64 [[RETVAL_0_I_I]] to i32 // DEFAULT-NEXT: [[BF_VALUE_I:%.*]] = and i32 [[CONV_I]], 4194303 // DEFAULT-NEXT: [[BF_SET9_I:%.*]] = or disjoint i32 [[BF_VALUE_I]], 2143289344 -// DEFAULT-NEXT: [[TMP16:%.*]] = bitcast i32 [[BF_SET9_I]] to float -// DEFAULT-NEXT: ret float [[TMP16]] +// DEFAULT-NEXT: [[TMP13:%.*]] = bitcast i32 [[BF_SET9_I]] to float +// DEFAULT-NEXT: ret float [[TMP13]] // // FINITEONLY-LABEL: define dso_local nofpclass(nan inf) float @test_nanf( -// FINITEONLY-SAME: ptr noundef readonly captures(none) [[TAG:%.*]]) local_unnamed_addr #[[ATTR3]] { +// FINITEONLY-SAME: ptr noundef readnone captures(none) [[TAG:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] // FINITEONLY-NEXT: ret float poison // // APPROX-LABEL: define dso_local float @test_nanf( // APPROX-SAME: ptr noundef readonly captures(none) [[TAG:%.*]]) local_unnamed_addr #[[ATTR2]] { -// APPROX-NEXT: [[ENTRY:.*:]] +// APPROX-NEXT: [[ENTRY:.*]]: // APPROX-NEXT: [[TMP0:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// APPROX-NEXT: br i1 [[CMP_I_I]], label %[[IF_THEN_I_I:.*]], label %[[WHILE_COND_I14_I_I_PREHEADER:.*]] -// APPROX: [[WHILE_COND_I14_I_I_PREHEADER]]: -// APPROX-NEXT: [[TMP1:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I17_I_I5:%.*]] = icmp eq i8 [[TMP1]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I17_I_I5]], label %[[_ZL4NANFPKC_EXIT:.*]], label %[[WHILE_BODY_I18_I_I:.*]] +// APPROX-NEXT: switch i8 [[TMP0]], label %[[WHILE_BODY_I25_I_I:.*]] [ +// APPROX-NEXT: i8 48, label %[[IF_THEN_I_I:.*]] +// APPROX-NEXT: i8 0, label %[[_ZL4NANFPKC_EXIT:.*]] +// APPROX-NEXT: ] // APPROX: [[IF_THEN_I_I]]: // APPROX-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TAG]], i64 1 -// APPROX-NEXT: [[TMP2:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: switch i8 [[TMP2]], label %[[WHILE_COND_I_I_I_PREHEADER:.*]] [ -// APPROX-NEXT: i8 120, label %[[IF_THEN5_I_I:.*]] -// APPROX-NEXT: i8 88, label %[[IF_THEN5_I_I]] +// APPROX-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// APPROX-NEXT: switch i8 [[TMP1]], label %[[WHILE_BODY_I14_I_I:.*]] [ +// APPROX-NEXT: i8 88, label %[[WHILE_BODY_I_I_I_PREHEADER:.*]] +// APPROX-NEXT: i8 120, label %[[WHILE_BODY_I_I_I_PREHEADER]] +// APPROX-NEXT: i8 0, label %[[_ZL4NANFPKC_EXIT]] // APPROX-NEXT: ] -// APPROX: [[WHILE_COND_I_I_I_PREHEADER]]: -// APPROX-NEXT: [[TMP3:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I_I_I14:%.*]] = icmp eq i8 [[TMP3]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I_I_I14]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I:.*]] -// APPROX: [[IF_THEN5_I_I]]: -// APPROX-NEXT: [[TMP4:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I30_I_I9:%.*]] = icmp eq i8 [[TMP4]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I30_I_I9]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I31_I_I:.*]] -// APPROX: [[WHILE_BODY_I31_I_I]]: -// APPROX-NEXT: [[TMP5:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP4]], %[[IF_THEN5_I_I]] ] -// APPROX-NEXT: [[__R_0_I29_I_I11:%.*]] = phi i64 [ [[ADD28_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_THEN5_I_I]] ] -// APPROX-NEXT: [[__TAGP_ADDR_0_I28_I_I10:%.*]] = phi ptr [ [[INCDEC_PTR_I34_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN5_I_I]] ] -// APPROX-NEXT: [[TMP6:%.*]] = add i8 [[TMP5]], -48 -// APPROX-NEXT: [[OR_COND_I32_I_I:%.*]] = icmp ult i8 [[TMP6]], 10 -// APPROX-NEXT: br i1 [[OR_COND_I32_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE_I_I_I:.*]] +// APPROX: [[WHILE_BODY_I_I_I_PREHEADER]]: +// APPROX-NEXT: br label %[[WHILE_BODY_I_I_I:.*]] +// APPROX: [[WHILE_BODY_I_I_I]]: +// APPROX-NEXT: [[TMP2:%.*]] = phi i8 [ [[TMP6:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP1]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// APPROX-NEXT: [[__R_050_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// APPROX-NEXT: [[__TAGP_ADDR_049_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// APPROX-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 +// APPROX-NEXT: [[OR_COND_I_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// APPROX-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I:.*]], label %[[IF_ELSE_I_I_I:.*]] +// APPROX: [[IF_THEN_I_I_I]]: +// APPROX-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// APPROX-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// APPROX-NEXT: [[ADD_I_I_I:%.*]] = add nsw i64 [[CONV5_I_I_I]], -48 +// APPROX-NEXT: [[SUB_I_I_I:%.*]] = or disjoint i64 [[ADD_I_I_I]], [[MUL_I_I_I]] +// APPROX-NEXT: br label %[[IF_END31_I_I_I]] // APPROX: [[IF_ELSE_I_I_I]]: -// APPROX-NEXT: [[TMP7:%.*]] = add i8 [[TMP5]], -97 -// APPROX-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP7]], 6 -// APPROX-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE17_I_I_I:.*]] +// APPROX-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 +// APPROX-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 +// APPROX-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_THEN11_I_I_I:.*]], label %[[IF_ELSE17_I_I_I:.*]] +// APPROX: [[IF_THEN11_I_I_I]]: +// APPROX-NEXT: [[MUL12_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// APPROX-NEXT: [[CONV13_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// APPROX-NEXT: [[ADD14_I_I_I:%.*]] = add nsw i64 [[CONV13_I_I_I]], -87 +// APPROX-NEXT: [[ADD16_I_I_I:%.*]] = add i64 [[ADD14_I_I_I]], [[MUL12_I_I_I]] +// APPROX-NEXT: br label %[[IF_END31_I_I_I]] // APPROX: [[IF_ELSE17_I_I_I]]: -// APPROX-NEXT: [[TMP8:%.*]] = add i8 [[TMP5]], -65 -// APPROX-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP8]], 6 -// APPROX-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_END31_I_I_I]], label %[[_ZL4NANFPKC_EXIT]] +// APPROX-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 +// APPROX-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 +// APPROX-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_THEN23_I_I_I:.*]], label %[[_ZL4NANFPKC_EXIT]] +// APPROX: [[IF_THEN23_I_I_I]]: +// APPROX-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// APPROX-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// APPROX-NEXT: [[ADD26_I_I_I:%.*]] = add nsw i64 [[CONV25_I_I_I]], -55 +// APPROX-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[MUL24_I_I_I]] +// APPROX-NEXT: br label %[[IF_END31_I_I_I]] // APPROX: [[IF_END31_I_I_I]]: -// APPROX-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I31_I_I]] ], [ -87, %[[IF_ELSE_I_I_I]] ], [ -55, %[[IF_ELSE17_I_I_I]] ] -// APPROX-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I29_I_I11]], 4 -// APPROX-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP5]] to i64 -// APPROX-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] -// APPROX-NEXT: [[ADD28_I_I_I]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] -// APPROX-NEXT: [[INCDEC_PTR_I34_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I28_I_I10]], i64 1 -// APPROX-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I34_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I30_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I30_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I31_I_I]], !llvm.loop [[LOOP13]] -// APPROX: [[WHILE_BODY_I_I_I]]: -// APPROX-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I_I_I:.*]] ], [ [[TMP3]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// APPROX-NEXT: [[__R_0_I_I_I16:%.*]] = phi i64 [ [[SUB_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ] -// APPROX-NEXT: [[__TAGP_ADDR_0_I_I_I15:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// APPROX-NEXT: [[TMP11:%.*]] = and i8 [[TMP10]], -8 -// APPROX-NEXT: [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP11]], 48 -// APPROX-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I]], label %[[_ZL4NANFPKC_EXIT]] -// APPROX: [[IF_THEN_I_I_I]]: -// APPROX-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I16]], 3 -// APPROX-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 -// APPROX-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 -// APPROX-NEXT: [[SUB_I_I_I]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] -// APPROX-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I_I_I15]], i64 1 -// APPROX-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP9]] -// APPROX: [[WHILE_BODY_I18_I_I]]: -// APPROX-NEXT: [[TMP13:%.*]] = phi i8 [ [[TMP15:%.*]], %[[IF_THEN_I21_I_I:.*]] ], [ [[TMP1]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// APPROX-NEXT: [[__R_0_I16_I_I7:%.*]] = phi i64 [ [[SUB_I25_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// APPROX-NEXT: [[__TAGP_ADDR_0_I15_I_I6:%.*]] = phi ptr [ [[INCDEC_PTR_I26_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ [[TAG]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// APPROX-NEXT: [[TMP14:%.*]] = add i8 [[TMP13]], -48 -// APPROX-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP14]], 10 -// APPROX-NEXT: br i1 [[OR_COND_I19_I_I]], label %[[IF_THEN_I21_I_I]], label %[[_ZL4NANFPKC_EXIT]] -// APPROX: [[IF_THEN_I21_I_I]]: -// APPROX-NEXT: [[MUL_I22_I_I:%.*]] = mul i64 [[__R_0_I16_I_I7]], 10 -// APPROX-NEXT: [[CONV5_I23_I_I:%.*]] = zext nneg i8 [[TMP13]] to i64 -// APPROX-NEXT: [[ADD_I24_I_I:%.*]] = add i64 [[MUL_I22_I_I]], -48 -// APPROX-NEXT: [[SUB_I25_I_I]] = add i64 [[ADD_I24_I_I]], [[CONV5_I23_I_I]] -// APPROX-NEXT: [[INCDEC_PTR_I26_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I15_I_I6]], i64 1 -// APPROX-NEXT: [[TMP15]] = load i8, ptr [[INCDEC_PTR_I26_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP15]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I17_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I18_I_I]], !llvm.loop [[LOOP12]] +// APPROX-NEXT: [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ [[ADD16_I_I_I]], %[[IF_THEN11_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_THEN23_I_I_I]] ] +// APPROX-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_049_I_I_I]], i64 1 +// APPROX-NEXT: [[TMP6]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// APPROX-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// APPROX-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP13]] +// APPROX: [[WHILE_BODY_I14_I_I]]: +// APPROX-NEXT: [[TMP7:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_THEN_I17_I_I:.*]] ], [ [[TMP1]], %[[IF_THEN_I_I]] ] +// APPROX-NEXT: [[__R_014_I_I_I:%.*]] = phi i64 [ [[SUB_I21_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[IF_THEN_I_I]] ] +// APPROX-NEXT: [[__TAGP_ADDR_013_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I22_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN_I_I]] ] +// APPROX-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], -8 +// APPROX-NEXT: [[OR_COND_I15_I_I:%.*]] = icmp eq i8 [[TMP8]], 48 +// APPROX-NEXT: br i1 [[OR_COND_I15_I_I]], label %[[IF_THEN_I17_I_I]], label %[[_ZL4NANFPKC_EXIT]] +// APPROX: [[IF_THEN_I17_I_I]]: +// APPROX-NEXT: [[MUL_I18_I_I:%.*]] = shl i64 [[__R_014_I_I_I]], 3 +// APPROX-NEXT: [[CONV5_I19_I_I:%.*]] = zext nneg i8 [[TMP7]] to i64 +// APPROX-NEXT: [[ADD_I20_I_I:%.*]] = add nsw i64 [[CONV5_I19_I_I]], -48 +// APPROX-NEXT: [[SUB_I21_I_I]] = or disjoint i64 [[ADD_I20_I_I]], [[MUL_I18_I_I]] +// APPROX-NEXT: [[INCDEC_PTR_I22_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I_I_I]], i64 1 +// APPROX-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I22_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// APPROX-NEXT: [[CMP_NOT_I23_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 +// APPROX-NEXT: br i1 [[CMP_NOT_I23_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I14_I_I]], !llvm.loop [[LOOP9]] +// APPROX: [[WHILE_BODY_I25_I_I]]: +// APPROX-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I30_I_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] +// APPROX-NEXT: [[__R_014_I26_I_I:%.*]] = phi i64 [ [[SUB_I34_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[ENTRY]] ] +// APPROX-NEXT: [[__TAGP_ADDR_013_I27_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I35_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ [[TAG]], %[[ENTRY]] ] +// APPROX-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], -48 +// APPROX-NEXT: [[OR_COND_I28_I_I:%.*]] = icmp ult i8 [[TMP11]], 10 +// APPROX-NEXT: br i1 [[OR_COND_I28_I_I]], label %[[IF_THEN_I30_I_I]], label %[[_ZL4NANFPKC_EXIT]] +// APPROX: [[IF_THEN_I30_I_I]]: +// APPROX-NEXT: [[MUL_I31_I_I:%.*]] = mul i64 [[__R_014_I26_I_I]], 10 +// APPROX-NEXT: [[CONV5_I32_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 +// APPROX-NEXT: [[ADD_I33_I_I:%.*]] = add nsw i64 [[CONV5_I32_I_I]], -48 +// APPROX-NEXT: [[SUB_I34_I_I]] = add i64 [[ADD_I33_I_I]], [[MUL_I31_I_I]] +// APPROX-NEXT: [[INCDEC_PTR_I35_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I27_I_I]], i64 1 +// APPROX-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I35_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// APPROX-NEXT: [[CMP_NOT_I36_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 +// APPROX-NEXT: br i1 [[CMP_NOT_I36_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I25_I_I]], !llvm.loop [[LOOP12]] // APPROX: [[_ZL4NANFPKC_EXIT]]: -// APPROX-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ], [ 0, %[[IF_THEN5_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ], [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ], [ [[SUB_I25_I_I]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_BODY_I18_I_I]] ] +// APPROX-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[IF_THEN_I_I]] ], [ 0, %[[ENTRY]] ], [ [[SUB_I34_I_I]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[WHILE_BODY_I25_I_I]] ], [ [[SUB_I21_I_I]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[WHILE_BODY_I14_I_I]] ], [ [[__R_1_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ] // APPROX-NEXT: [[CONV_I:%.*]] = trunc i64 [[RETVAL_0_I_I]] to i32 // APPROX-NEXT: [[BF_VALUE_I:%.*]] = and i32 [[CONV_I]], 4194303 // APPROX-NEXT: [[BF_SET9_I:%.*]] = or disjoint i32 [[BF_VALUE_I]], 2143289344 -// APPROX-NEXT: [[TMP16:%.*]] = bitcast i32 [[BF_SET9_I]] to float -// APPROX-NEXT: ret float [[TMP16]] +// APPROX-NEXT: [[TMP13:%.*]] = bitcast i32 [[BF_SET9_I]] to float +// APPROX-NEXT: ret float [[TMP13]] // // NCRDIV-LABEL: define dso_local float @test_nanf( // NCRDIV-SAME: ptr noundef readonly captures(none) [[TAG:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NCRDIV-NEXT: [[ENTRY:.*:]] +// NCRDIV-NEXT: [[ENTRY:.*]]: // NCRDIV-NEXT: [[TMP0:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// NCRDIV-NEXT: br i1 [[CMP_I_I]], label %[[IF_THEN_I_I:.*]], label %[[WHILE_COND_I14_I_I_PREHEADER:.*]] -// NCRDIV: [[WHILE_COND_I14_I_I_PREHEADER]]: -// NCRDIV-NEXT: [[TMP1:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I17_I_I5:%.*]] = icmp eq i8 [[TMP1]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I17_I_I5]], label %[[_ZL4NANFPKC_EXIT:.*]], label %[[WHILE_BODY_I18_I_I:.*]] +// NCRDIV-NEXT: switch i8 [[TMP0]], label %[[WHILE_BODY_I25_I_I:.*]] [ +// NCRDIV-NEXT: i8 48, label %[[IF_THEN_I_I:.*]] +// NCRDIV-NEXT: i8 0, label %[[_ZL4NANFPKC_EXIT:.*]] +// NCRDIV-NEXT: ] // NCRDIV: [[IF_THEN_I_I]]: // NCRDIV-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TAG]], i64 1 -// NCRDIV-NEXT: [[TMP2:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: switch i8 [[TMP2]], label %[[WHILE_COND_I_I_I_PREHEADER:.*]] [ -// NCRDIV-NEXT: i8 120, label %[[IF_THEN5_I_I:.*]] -// NCRDIV-NEXT: i8 88, label %[[IF_THEN5_I_I]] +// NCRDIV-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// NCRDIV-NEXT: switch i8 [[TMP1]], label %[[WHILE_BODY_I14_I_I:.*]] [ +// NCRDIV-NEXT: i8 88, label %[[WHILE_BODY_I_I_I_PREHEADER:.*]] +// NCRDIV-NEXT: i8 120, label %[[WHILE_BODY_I_I_I_PREHEADER]] +// NCRDIV-NEXT: i8 0, label %[[_ZL4NANFPKC_EXIT]] // NCRDIV-NEXT: ] -// NCRDIV: [[WHILE_COND_I_I_I_PREHEADER]]: -// NCRDIV-NEXT: [[TMP3:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I_I_I14:%.*]] = icmp eq i8 [[TMP3]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I_I_I14]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I:.*]] -// NCRDIV: [[IF_THEN5_I_I]]: -// NCRDIV-NEXT: [[TMP4:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I30_I_I9:%.*]] = icmp eq i8 [[TMP4]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I30_I_I9]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I31_I_I:.*]] -// NCRDIV: [[WHILE_BODY_I31_I_I]]: -// NCRDIV-NEXT: [[TMP5:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP4]], %[[IF_THEN5_I_I]] ] -// NCRDIV-NEXT: [[__R_0_I29_I_I11:%.*]] = phi i64 [ [[ADD28_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_THEN5_I_I]] ] -// NCRDIV-NEXT: [[__TAGP_ADDR_0_I28_I_I10:%.*]] = phi ptr [ [[INCDEC_PTR_I34_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN5_I_I]] ] -// NCRDIV-NEXT: [[TMP6:%.*]] = add i8 [[TMP5]], -48 -// NCRDIV-NEXT: [[OR_COND_I32_I_I:%.*]] = icmp ult i8 [[TMP6]], 10 -// NCRDIV-NEXT: br i1 [[OR_COND_I32_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE_I_I_I:.*]] +// NCRDIV: [[WHILE_BODY_I_I_I_PREHEADER]]: +// NCRDIV-NEXT: br label %[[WHILE_BODY_I_I_I:.*]] +// NCRDIV: [[WHILE_BODY_I_I_I]]: +// NCRDIV-NEXT: [[TMP2:%.*]] = phi i8 [ [[TMP6:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP1]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// NCRDIV-NEXT: [[__R_050_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// NCRDIV-NEXT: [[__TAGP_ADDR_049_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// NCRDIV-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 +// NCRDIV-NEXT: [[OR_COND_I_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// NCRDIV-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I:.*]], label %[[IF_ELSE_I_I_I:.*]] +// NCRDIV: [[IF_THEN_I_I_I]]: +// NCRDIV-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// NCRDIV-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// NCRDIV-NEXT: [[ADD_I_I_I:%.*]] = add nsw i64 [[CONV5_I_I_I]], -48 +// NCRDIV-NEXT: [[SUB_I_I_I:%.*]] = or disjoint i64 [[ADD_I_I_I]], [[MUL_I_I_I]] +// NCRDIV-NEXT: br label %[[IF_END31_I_I_I]] // NCRDIV: [[IF_ELSE_I_I_I]]: -// NCRDIV-NEXT: [[TMP7:%.*]] = add i8 [[TMP5]], -97 -// NCRDIV-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP7]], 6 -// NCRDIV-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE17_I_I_I:.*]] +// NCRDIV-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 +// NCRDIV-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 +// NCRDIV-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_THEN11_I_I_I:.*]], label %[[IF_ELSE17_I_I_I:.*]] +// NCRDIV: [[IF_THEN11_I_I_I]]: +// NCRDIV-NEXT: [[MUL12_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// NCRDIV-NEXT: [[CONV13_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// NCRDIV-NEXT: [[ADD14_I_I_I:%.*]] = add nsw i64 [[CONV13_I_I_I]], -87 +// NCRDIV-NEXT: [[ADD16_I_I_I:%.*]] = add i64 [[ADD14_I_I_I]], [[MUL12_I_I_I]] +// NCRDIV-NEXT: br label %[[IF_END31_I_I_I]] // NCRDIV: [[IF_ELSE17_I_I_I]]: -// NCRDIV-NEXT: [[TMP8:%.*]] = add i8 [[TMP5]], -65 -// NCRDIV-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP8]], 6 -// NCRDIV-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_END31_I_I_I]], label %[[_ZL4NANFPKC_EXIT]] +// NCRDIV-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 +// NCRDIV-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 +// NCRDIV-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_THEN23_I_I_I:.*]], label %[[_ZL4NANFPKC_EXIT]] +// NCRDIV: [[IF_THEN23_I_I_I]]: +// NCRDIV-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// NCRDIV-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// NCRDIV-NEXT: [[ADD26_I_I_I:%.*]] = add nsw i64 [[CONV25_I_I_I]], -55 +// NCRDIV-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[MUL24_I_I_I]] +// NCRDIV-NEXT: br label %[[IF_END31_I_I_I]] // NCRDIV: [[IF_END31_I_I_I]]: -// NCRDIV-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I31_I_I]] ], [ -87, %[[IF_ELSE_I_I_I]] ], [ -55, %[[IF_ELSE17_I_I_I]] ] -// NCRDIV-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I29_I_I11]], 4 -// NCRDIV-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP5]] to i64 -// NCRDIV-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] -// NCRDIV-NEXT: [[ADD28_I_I_I]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] -// NCRDIV-NEXT: [[INCDEC_PTR_I34_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I28_I_I10]], i64 1 -// NCRDIV-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I34_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I30_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I30_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I31_I_I]], !llvm.loop [[LOOP13]] -// NCRDIV: [[WHILE_BODY_I_I_I]]: -// NCRDIV-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I_I_I:.*]] ], [ [[TMP3]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[__R_0_I_I_I16:%.*]] = phi i64 [ [[SUB_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[__TAGP_ADDR_0_I_I_I15:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[TMP11:%.*]] = and i8 [[TMP10]], -8 -// NCRDIV-NEXT: [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP11]], 48 -// NCRDIV-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I]], label %[[_ZL4NANFPKC_EXIT]] -// NCRDIV: [[IF_THEN_I_I_I]]: -// NCRDIV-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I16]], 3 -// NCRDIV-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 -// NCRDIV-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 -// NCRDIV-NEXT: [[SUB_I_I_I]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] -// NCRDIV-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I_I_I15]], i64 1 -// NCRDIV-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP9]] -// NCRDIV: [[WHILE_BODY_I18_I_I]]: -// NCRDIV-NEXT: [[TMP13:%.*]] = phi i8 [ [[TMP15:%.*]], %[[IF_THEN_I21_I_I:.*]] ], [ [[TMP1]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[__R_0_I16_I_I7:%.*]] = phi i64 [ [[SUB_I25_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[__TAGP_ADDR_0_I15_I_I6:%.*]] = phi ptr [ [[INCDEC_PTR_I26_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ [[TAG]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[TMP14:%.*]] = add i8 [[TMP13]], -48 -// NCRDIV-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP14]], 10 -// NCRDIV-NEXT: br i1 [[OR_COND_I19_I_I]], label %[[IF_THEN_I21_I_I]], label %[[_ZL4NANFPKC_EXIT]] -// NCRDIV: [[IF_THEN_I21_I_I]]: -// NCRDIV-NEXT: [[MUL_I22_I_I:%.*]] = mul i64 [[__R_0_I16_I_I7]], 10 -// NCRDIV-NEXT: [[CONV5_I23_I_I:%.*]] = zext nneg i8 [[TMP13]] to i64 -// NCRDIV-NEXT: [[ADD_I24_I_I:%.*]] = add i64 [[MUL_I22_I_I]], -48 -// NCRDIV-NEXT: [[SUB_I25_I_I]] = add i64 [[ADD_I24_I_I]], [[CONV5_I23_I_I]] -// NCRDIV-NEXT: [[INCDEC_PTR_I26_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I15_I_I6]], i64 1 -// NCRDIV-NEXT: [[TMP15]] = load i8, ptr [[INCDEC_PTR_I26_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP15]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I17_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I18_I_I]], !llvm.loop [[LOOP12]] +// NCRDIV-NEXT: [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ [[ADD16_I_I_I]], %[[IF_THEN11_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_THEN23_I_I_I]] ] +// NCRDIV-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_049_I_I_I]], i64 1 +// NCRDIV-NEXT: [[TMP6]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// NCRDIV-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// NCRDIV-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP13]] +// NCRDIV: [[WHILE_BODY_I14_I_I]]: +// NCRDIV-NEXT: [[TMP7:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_THEN_I17_I_I:.*]] ], [ [[TMP1]], %[[IF_THEN_I_I]] ] +// NCRDIV-NEXT: [[__R_014_I_I_I:%.*]] = phi i64 [ [[SUB_I21_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[IF_THEN_I_I]] ] +// NCRDIV-NEXT: [[__TAGP_ADDR_013_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I22_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN_I_I]] ] +// NCRDIV-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], -8 +// NCRDIV-NEXT: [[OR_COND_I15_I_I:%.*]] = icmp eq i8 [[TMP8]], 48 +// NCRDIV-NEXT: br i1 [[OR_COND_I15_I_I]], label %[[IF_THEN_I17_I_I]], label %[[_ZL4NANFPKC_EXIT]] +// NCRDIV: [[IF_THEN_I17_I_I]]: +// NCRDIV-NEXT: [[MUL_I18_I_I:%.*]] = shl i64 [[__R_014_I_I_I]], 3 +// NCRDIV-NEXT: [[CONV5_I19_I_I:%.*]] = zext nneg i8 [[TMP7]] to i64 +// NCRDIV-NEXT: [[ADD_I20_I_I:%.*]] = add nsw i64 [[CONV5_I19_I_I]], -48 +// NCRDIV-NEXT: [[SUB_I21_I_I]] = or disjoint i64 [[ADD_I20_I_I]], [[MUL_I18_I_I]] +// NCRDIV-NEXT: [[INCDEC_PTR_I22_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I_I_I]], i64 1 +// NCRDIV-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I22_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// NCRDIV-NEXT: [[CMP_NOT_I23_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 +// NCRDIV-NEXT: br i1 [[CMP_NOT_I23_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I14_I_I]], !llvm.loop [[LOOP9]] +// NCRDIV: [[WHILE_BODY_I25_I_I]]: +// NCRDIV-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I30_I_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[__R_014_I26_I_I:%.*]] = phi i64 [ [[SUB_I34_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[ENTRY]] ] +// NCRDIV-NEXT: [[__TAGP_ADDR_013_I27_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I35_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ [[TAG]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], -48 +// NCRDIV-NEXT: [[OR_COND_I28_I_I:%.*]] = icmp ult i8 [[TMP11]], 10 +// NCRDIV-NEXT: br i1 [[OR_COND_I28_I_I]], label %[[IF_THEN_I30_I_I]], label %[[_ZL4NANFPKC_EXIT]] +// NCRDIV: [[IF_THEN_I30_I_I]]: +// NCRDIV-NEXT: [[MUL_I31_I_I:%.*]] = mul i64 [[__R_014_I26_I_I]], 10 +// NCRDIV-NEXT: [[CONV5_I32_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 +// NCRDIV-NEXT: [[ADD_I33_I_I:%.*]] = add nsw i64 [[CONV5_I32_I_I]], -48 +// NCRDIV-NEXT: [[SUB_I34_I_I]] = add i64 [[ADD_I33_I_I]], [[MUL_I31_I_I]] +// NCRDIV-NEXT: [[INCDEC_PTR_I35_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I27_I_I]], i64 1 +// NCRDIV-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I35_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// NCRDIV-NEXT: [[CMP_NOT_I36_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 +// NCRDIV-NEXT: br i1 [[CMP_NOT_I36_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I25_I_I]], !llvm.loop [[LOOP12]] // NCRDIV: [[_ZL4NANFPKC_EXIT]]: -// NCRDIV-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ], [ 0, %[[IF_THEN5_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ], [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ], [ [[SUB_I25_I_I]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_BODY_I18_I_I]] ] +// NCRDIV-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[IF_THEN_I_I]] ], [ 0, %[[ENTRY]] ], [ [[SUB_I34_I_I]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[WHILE_BODY_I25_I_I]] ], [ [[SUB_I21_I_I]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[WHILE_BODY_I14_I_I]] ], [ [[__R_1_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ] // NCRDIV-NEXT: [[CONV_I:%.*]] = trunc i64 [[RETVAL_0_I_I]] to i32 // NCRDIV-NEXT: [[BF_VALUE_I:%.*]] = and i32 [[CONV_I]], 4194303 // NCRDIV-NEXT: [[BF_SET9_I:%.*]] = or disjoint i32 [[BF_VALUE_I]], 2143289344 -// NCRDIV-NEXT: [[TMP16:%.*]] = bitcast i32 [[BF_SET9_I]] to float -// NCRDIV-NEXT: ret float [[TMP16]] +// NCRDIV-NEXT: [[TMP13:%.*]] = bitcast i32 [[BF_SET9_I]] to float +// NCRDIV-NEXT: ret float [[TMP13]] // // AMDGCNSPIRV-LABEL: define spir_func float @test_nanf( // AMDGCNSPIRV-SAME: ptr addrspace(4) noundef readonly captures(none) [[TAG:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR2]] { // AMDGCNSPIRV-NEXT: [[ENTRY:.*]]: // AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load i8, ptr addrspace(4) [[TAG]], align 1, !tbaa [[CHAR_TBAA9]] // AMDGCNSPIRV-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_I_I]], label %[[IF_THEN_I_I:.*]], label %[[WHILE_COND_I14_I_I:.*]] +// AMDGCNSPIRV-NEXT: br i1 [[CMP_I_I]], label %[[IF_THEN_I_I:.*]], label %[[WHILE_COND_I23_I_I:.*]] // AMDGCNSPIRV: [[IF_THEN_I_I]]: // AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TAG]], i64 1 // AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA9]] // AMDGCNSPIRV-NEXT: switch i8 [[TMP1]], label %[[WHILE_COND_I_I_I:.*]] [ -// AMDGCNSPIRV-NEXT: i8 120, label %[[IF_THEN5_I_I:.*]] -// AMDGCNSPIRV-NEXT: i8 88, label %[[IF_THEN5_I_I]] +// AMDGCNSPIRV-NEXT: i8 88, label %[[WHILE_BODY_I_I_I_PREHEADER:.*]] +// AMDGCNSPIRV-NEXT: i8 120, label %[[WHILE_BODY_I_I_I_PREHEADER]] // AMDGCNSPIRV-NEXT: ] -// AMDGCNSPIRV: [[IF_THEN5_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I31_I_I5:%.*]] = icmp eq i8 [[TMP2]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I31_I_I5]], label %[[_ZL4NANFPKC_EXIT:.*]], label %[[WHILE_BODY_I32_I_I:.*]] -// AMDGCNSPIRV: [[WHILE_BODY_I32_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = phi i8 [ [[TMP7:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP2]], %[[IF_THEN5_I_I]] ] -// AMDGCNSPIRV-NEXT: [[__R_0_I30_I_I7:%.*]] = phi i64 [ [[ADD28_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_THEN5_I_I]] ] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I29_I_I6:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I36_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN5_I_I]] ] -// AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = add i8 [[TMP3]], -48 -// AMDGCNSPIRV-NEXT: [[OR_COND_I33_I_I:%.*]] = icmp ult i8 [[TMP4]], 10 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I33_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE_I_I_I:.*]] +// AMDGCNSPIRV: [[WHILE_BODY_I_I_I_PREHEADER]]: +// AMDGCNSPIRV-NEXT: br label %[[WHILE_BODY_I_I_I:.*]] +// AMDGCNSPIRV: [[WHILE_BODY_I_I_I]]: +// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = phi i8 [ [[TMP6:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP1]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// AMDGCNSPIRV-NEXT: [[__R_050_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_049_I_I_I:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 +// AMDGCNSPIRV-NEXT: [[OR_COND_I_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I:.*]], label %[[IF_ELSE_I_I_I:.*]] +// AMDGCNSPIRV: [[IF_THEN_I_I_I]]: +// AMDGCNSPIRV-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD_I_I_I:%.*]] = add nsw i64 [[CONV5_I_I_I]], -48 +// AMDGCNSPIRV-NEXT: [[SUB_I_I_I:%.*]] = or disjoint i64 [[ADD_I_I_I]], [[MUL_I_I_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I_I_I]] // AMDGCNSPIRV: [[IF_ELSE_I_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP5:%.*]] = add i8 [[TMP3]], -97 -// AMDGCNSPIRV-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE17_I_I_I:.*]] +// AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 +// AMDGCNSPIRV-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_THEN11_I_I_I:.*]], label %[[IF_ELSE17_I_I_I:.*]] +// AMDGCNSPIRV: [[IF_THEN11_I_I_I]]: +// AMDGCNSPIRV-NEXT: [[MUL12_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV13_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD14_I_I_I:%.*]] = add nsw i64 [[CONV13_I_I_I]], -87 +// AMDGCNSPIRV-NEXT: [[ADD16_I_I_I:%.*]] = add i64 [[ADD14_I_I_I]], [[MUL12_I_I_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I_I_I]] // AMDGCNSPIRV: [[IF_ELSE17_I_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP6:%.*]] = add i8 [[TMP3]], -65 -// AMDGCNSPIRV-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP6]], 6 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_END31_I_I_I]], label %[[_ZL4NANFPKC_EXIT]] +// AMDGCNSPIRV-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 +// AMDGCNSPIRV-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_THEN23_I_I_I:.*]], label %[[_ZL4NANFPKC_EXIT:.*]] +// AMDGCNSPIRV: [[IF_THEN23_I_I_I]]: +// AMDGCNSPIRV-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD26_I_I_I:%.*]] = add nsw i64 [[CONV25_I_I_I]], -55 +// AMDGCNSPIRV-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[MUL24_I_I_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I_I_I]] // AMDGCNSPIRV: [[IF_END31_I_I_I]]: -// AMDGCNSPIRV-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I32_I_I]] ], [ -87, %[[IF_ELSE_I_I_I]] ], [ -55, %[[IF_ELSE17_I_I_I]] ] -// AMDGCNSPIRV-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I30_I_I7]], 4 -// AMDGCNSPIRV-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP3]] to i64 -// AMDGCNSPIRV-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] -// AMDGCNSPIRV-NEXT: [[ADD28_I_I_I]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] -// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I36_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I29_I_I6]], i64 1 -// AMDGCNSPIRV-NEXT: [[TMP7]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I36_I_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I31_I_I:%.*]] = icmp eq i8 [[TMP7]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I31_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I32_I_I]], !llvm.loop [[LOOP14]] +// AMDGCNSPIRV-NEXT: [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ [[ADD16_I_I_I]], %[[IF_THEN11_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_THEN23_I_I_I]] ] +// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_049_I_I_I]], i64 1 +// AMDGCNSPIRV-NEXT: [[TMP6]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA9]] +// AMDGCNSPIRV-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP14]] // AMDGCNSPIRV: [[WHILE_COND_I_I_I]]: -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I_I_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I_I_I:%.*]], %[[WHILE_BODY_I_I_I:.*]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN_I_I]] ] -// AMDGCNSPIRV-NEXT: [[__R_0_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], %[[WHILE_BODY_I_I_I]] ], [ 0, %[[IF_THEN_I_I]] ] -// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I_I_I]] -// AMDGCNSPIRV: [[WHILE_BODY_I_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP9:%.*]] = and i8 [[TMP8]], -8 -// AMDGCNSPIRV-NEXT: [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP9]], 48 -// AMDGCNSPIRV-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 3 -// AMDGCNSPIRV-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP8]] to i64 -// AMDGCNSPIRV-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 -// AMDGCNSPIRV-NEXT: [[SUB_I_I_I:%.*]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_I_I_IDX:%.*]] = zext i1 [[OR_COND_I_I_I]] to i64 -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I_I]], i64 [[__TAGP_ADDR_1_I_I_I_IDX]] -// AMDGCNSPIRV-NEXT: [[__R_1_I_I_I]] = select i1 [[OR_COND_I_I_I]], i64 [[SUB_I_I_I]], i64 [[__R_0_I_I_I]] -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I_I_I]], label %[[WHILE_COND_I_I_I]], label %[[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP10]] -// AMDGCNSPIRV: [[WHILE_COND_I14_I_I]]: -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I15_I_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I25_I_I:%.*]], %[[WHILE_BODY_I18_I_I:.*]] ], [ [[TAG]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__R_0_I16_I_I:%.*]] = phi i64 [ [[__R_1_I26_I_I:%.*]], %[[WHILE_BODY_I18_I_I]] ], [ 0, %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[TMP10:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I15_I_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP10]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I17_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I18_I_I]] -// AMDGCNSPIRV: [[WHILE_BODY_I18_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], -48 -// AMDGCNSPIRV-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP11]], 10 -// AMDGCNSPIRV-NEXT: [[MUL_I20_I_I:%.*]] = mul i64 [[__R_0_I16_I_I]], 10 -// AMDGCNSPIRV-NEXT: [[CONV5_I21_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 -// AMDGCNSPIRV-NEXT: [[ADD_I22_I_I:%.*]] = add i64 [[MUL_I20_I_I]], -48 -// AMDGCNSPIRV-NEXT: [[SUB_I23_I_I:%.*]] = add i64 [[ADD_I22_I_I]], [[CONV5_I21_I_I]] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I25_I_I_IDX:%.*]] = zext i1 [[OR_COND_I19_I_I]] to i64 -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I25_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I15_I_I]], i64 [[__TAGP_ADDR_1_I25_I_I_IDX]] -// AMDGCNSPIRV-NEXT: [[__R_1_I26_I_I]] = select i1 [[OR_COND_I19_I_I]], i64 [[SUB_I23_I_I]], i64 [[__R_0_I16_I_I]] -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I19_I_I]], label %[[WHILE_COND_I14_I_I]], label %[[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP13]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I_I_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I_I_I:%.*]], %[[WHILE_BODY_I15_I_I:.*]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN_I_I]] ] +// AMDGCNSPIRV-NEXT: [[__R_0_I_I_I:%.*]] = phi i64 [ [[__R_1_I21_I_I:%.*]], %[[WHILE_BODY_I15_I_I]] ], [ 0, %[[IF_THEN_I_I]] ] +// AMDGCNSPIRV-NEXT: [[TMP7:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I_I]], align 1, !tbaa [[CHAR_TBAA9]] +// AMDGCNSPIRV-NEXT: [[CMP_NOT_I14_I_I:%.*]] = icmp eq i8 [[TMP7]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I14_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I15_I_I]] +// AMDGCNSPIRV: [[WHILE_BODY_I15_I_I]]: +// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], -8 +// AMDGCNSPIRV-NEXT: [[OR_COND_I16_I_I:%.*]] = icmp eq i8 [[TMP8]], 48 +// AMDGCNSPIRV-NEXT: [[MUL_I17_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 3 +// AMDGCNSPIRV-NEXT: [[CONV5_I18_I_I:%.*]] = zext nneg i8 [[TMP7]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD_I19_I_I:%.*]] = add i64 [[MUL_I17_I_I]], -48 +// AMDGCNSPIRV-NEXT: [[SUB_I20_I_I:%.*]] = add i64 [[ADD_I19_I_I]], [[CONV5_I18_I_I]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_IDX_I_I_I:%.*]] = zext i1 [[OR_COND_I16_I_I]] to i64 +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I_I]], i64 [[__TAGP_ADDR_1_IDX_I_I_I]] +// AMDGCNSPIRV-NEXT: [[__R_1_I21_I_I]] = select i1 [[OR_COND_I16_I_I]], i64 [[SUB_I20_I_I]], i64 [[__R_0_I_I_I]] +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I16_I_I]], label %[[WHILE_COND_I_I_I]], label %[[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP10]] +// AMDGCNSPIRV: [[WHILE_COND_I23_I_I]]: +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I24_I_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I34_I_I:%.*]], %[[WHILE_BODY_I27_I_I:.*]] ], [ [[TAG]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__R_0_I25_I_I:%.*]] = phi i64 [ [[__R_1_I35_I_I:%.*]], %[[WHILE_BODY_I27_I_I]] ], [ 0, %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[TMP9:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I24_I_I]], align 1, !tbaa [[CHAR_TBAA9]] +// AMDGCNSPIRV-NEXT: [[CMP_NOT_I26_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I26_I_I]], label %[[_ZL4NANFPKC_EXIT]], label %[[WHILE_BODY_I27_I_I]] +// AMDGCNSPIRV: [[WHILE_BODY_I27_I_I]]: +// AMDGCNSPIRV-NEXT: [[TMP10:%.*]] = add i8 [[TMP9]], -48 +// AMDGCNSPIRV-NEXT: [[OR_COND_I28_I_I:%.*]] = icmp ult i8 [[TMP10]], 10 +// AMDGCNSPIRV-NEXT: [[MUL_I29_I_I:%.*]] = mul i64 [[__R_0_I25_I_I]], 10 +// AMDGCNSPIRV-NEXT: [[CONV5_I30_I_I:%.*]] = zext nneg i8 [[TMP9]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD_I31_I_I:%.*]] = add i64 [[MUL_I29_I_I]], -48 +// AMDGCNSPIRV-NEXT: [[SUB_I32_I_I:%.*]] = add i64 [[ADD_I31_I_I]], [[CONV5_I30_I_I]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_IDX_I33_I_I:%.*]] = zext i1 [[OR_COND_I28_I_I]] to i64 +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I34_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I24_I_I]], i64 [[__TAGP_ADDR_1_IDX_I33_I_I]] +// AMDGCNSPIRV-NEXT: [[__R_1_I35_I_I]] = select i1 [[OR_COND_I28_I_I]], i64 [[SUB_I32_I_I]], i64 [[__R_0_I25_I_I]] +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I28_I_I]], label %[[WHILE_COND_I23_I_I]], label %[[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP13]] // AMDGCNSPIRV: [[_ZL4NANFPKC_EXIT]]: -// AMDGCNSPIRV-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[IF_THEN5_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I]] ], [ [[__R_0_I_I_I]], %[[WHILE_COND_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ], [ 0, %[[WHILE_BODY_I18_I_I]] ], [ [[__R_0_I16_I_I]], %[[WHILE_COND_I14_I_I]] ] +// AMDGCNSPIRV-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[WHILE_BODY_I15_I_I]] ], [ [[__R_0_I_I_I]], %[[WHILE_COND_I_I_I]] ], [ [[__R_1_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ], [ 0, %[[WHILE_BODY_I27_I_I]] ], [ [[__R_0_I25_I_I]], %[[WHILE_COND_I23_I_I]] ] // AMDGCNSPIRV-NEXT: [[CONV_I:%.*]] = trunc i64 [[RETVAL_0_I_I]] to i32 // AMDGCNSPIRV-NEXT: [[BF_VALUE_I:%.*]] = and i32 [[CONV_I]], 4194303 // AMDGCNSPIRV-NEXT: [[BF_SET9_I:%.*]] = or disjoint i32 [[BF_VALUE_I]], 2143289344 -// AMDGCNSPIRV-NEXT: [[TMP12:%.*]] = bitcast i32 [[BF_SET9_I]] to float -// AMDGCNSPIRV-NEXT: ret float [[TMP12]] +// AMDGCNSPIRV-NEXT: [[TMP11:%.*]] = bitcast i32 [[BF_SET9_I]] to float +// AMDGCNSPIRV-NEXT: ret float [[TMP11]] // extern "C" __device__ float test_nanf(const char *tag) { return nanf(tag); @@ -4617,358 +4697,391 @@ extern "C" __device__ float test_nanf(const char *tag) { // DEFAULT-LABEL: define dso_local double @test_nan( // DEFAULT-SAME: ptr noundef readonly captures(none) [[TAG:%.*]]) local_unnamed_addr #[[ATTR2]] { -// DEFAULT-NEXT: [[ENTRY:.*:]] +// DEFAULT-NEXT: [[ENTRY:.*]]: // DEFAULT-NEXT: [[TMP0:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// DEFAULT-NEXT: br i1 [[CMP_I_I]], label %[[IF_THEN_I_I:.*]], label %[[WHILE_COND_I14_I_I_PREHEADER:.*]] -// DEFAULT: [[WHILE_COND_I14_I_I_PREHEADER]]: -// DEFAULT-NEXT: [[TMP1:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I17_I_I5:%.*]] = icmp eq i8 [[TMP1]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I17_I_I5]], label %[[_ZL3NANPKC_EXIT:.*]], label %[[WHILE_BODY_I18_I_I:.*]] +// DEFAULT-NEXT: switch i8 [[TMP0]], label %[[WHILE_BODY_I25_I_I:.*]] [ +// DEFAULT-NEXT: i8 48, label %[[IF_THEN_I_I:.*]] +// DEFAULT-NEXT: i8 0, label %[[_ZL3NANPKC_EXIT:.*]] +// DEFAULT-NEXT: ] // DEFAULT: [[IF_THEN_I_I]]: // DEFAULT-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TAG]], i64 1 -// DEFAULT-NEXT: [[TMP2:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: switch i8 [[TMP2]], label %[[WHILE_COND_I_I_I_PREHEADER:.*]] [ -// DEFAULT-NEXT: i8 120, label %[[IF_THEN5_I_I:.*]] -// DEFAULT-NEXT: i8 88, label %[[IF_THEN5_I_I]] +// DEFAULT-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// DEFAULT-NEXT: switch i8 [[TMP1]], label %[[WHILE_BODY_I14_I_I:.*]] [ +// DEFAULT-NEXT: i8 88, label %[[WHILE_BODY_I_I_I_PREHEADER:.*]] +// DEFAULT-NEXT: i8 120, label %[[WHILE_BODY_I_I_I_PREHEADER]] +// DEFAULT-NEXT: i8 0, label %[[_ZL3NANPKC_EXIT]] // DEFAULT-NEXT: ] -// DEFAULT: [[WHILE_COND_I_I_I_PREHEADER]]: -// DEFAULT-NEXT: [[TMP3:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I_I_I14:%.*]] = icmp eq i8 [[TMP3]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I_I_I14]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I:.*]] -// DEFAULT: [[IF_THEN5_I_I]]: -// DEFAULT-NEXT: [[TMP4:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I30_I_I9:%.*]] = icmp eq i8 [[TMP4]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I30_I_I9]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I31_I_I:.*]] -// DEFAULT: [[WHILE_BODY_I31_I_I]]: -// DEFAULT-NEXT: [[TMP5:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP4]], %[[IF_THEN5_I_I]] ] -// DEFAULT-NEXT: [[__R_0_I29_I_I11:%.*]] = phi i64 [ [[ADD28_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_THEN5_I_I]] ] -// DEFAULT-NEXT: [[__TAGP_ADDR_0_I28_I_I10:%.*]] = phi ptr [ [[INCDEC_PTR_I34_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN5_I_I]] ] -// DEFAULT-NEXT: [[TMP6:%.*]] = add i8 [[TMP5]], -48 -// DEFAULT-NEXT: [[OR_COND_I32_I_I:%.*]] = icmp ult i8 [[TMP6]], 10 -// DEFAULT-NEXT: br i1 [[OR_COND_I32_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE_I_I_I:.*]] +// DEFAULT: [[WHILE_BODY_I_I_I_PREHEADER]]: +// DEFAULT-NEXT: br label %[[WHILE_BODY_I_I_I:.*]] +// DEFAULT: [[WHILE_BODY_I_I_I]]: +// DEFAULT-NEXT: [[TMP2:%.*]] = phi i8 [ [[TMP6:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP1]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// DEFAULT-NEXT: [[__R_050_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// DEFAULT-NEXT: [[__TAGP_ADDR_049_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// DEFAULT-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 +// DEFAULT-NEXT: [[OR_COND_I_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// DEFAULT-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I:.*]], label %[[IF_ELSE_I_I_I:.*]] +// DEFAULT: [[IF_THEN_I_I_I]]: +// DEFAULT-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// DEFAULT-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// DEFAULT-NEXT: [[ADD_I_I_I:%.*]] = add nsw i64 [[CONV5_I_I_I]], -48 +// DEFAULT-NEXT: [[SUB_I_I_I:%.*]] = or disjoint i64 [[ADD_I_I_I]], [[MUL_I_I_I]] +// DEFAULT-NEXT: br label %[[IF_END31_I_I_I]] // DEFAULT: [[IF_ELSE_I_I_I]]: -// DEFAULT-NEXT: [[TMP7:%.*]] = add i8 [[TMP5]], -97 -// DEFAULT-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP7]], 6 -// DEFAULT-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE17_I_I_I:.*]] +// DEFAULT-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 +// DEFAULT-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 +// DEFAULT-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_THEN11_I_I_I:.*]], label %[[IF_ELSE17_I_I_I:.*]] +// DEFAULT: [[IF_THEN11_I_I_I]]: +// DEFAULT-NEXT: [[MUL12_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// DEFAULT-NEXT: [[CONV13_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// DEFAULT-NEXT: [[ADD14_I_I_I:%.*]] = add nsw i64 [[CONV13_I_I_I]], -87 +// DEFAULT-NEXT: [[ADD16_I_I_I:%.*]] = add i64 [[ADD14_I_I_I]], [[MUL12_I_I_I]] +// DEFAULT-NEXT: br label %[[IF_END31_I_I_I]] // DEFAULT: [[IF_ELSE17_I_I_I]]: -// DEFAULT-NEXT: [[TMP8:%.*]] = add i8 [[TMP5]], -65 -// DEFAULT-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP8]], 6 -// DEFAULT-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_END31_I_I_I]], label %[[_ZL3NANPKC_EXIT]] +// DEFAULT-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 +// DEFAULT-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 +// DEFAULT-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_THEN23_I_I_I:.*]], label %[[_ZL3NANPKC_EXIT]] +// DEFAULT: [[IF_THEN23_I_I_I]]: +// DEFAULT-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// DEFAULT-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// DEFAULT-NEXT: [[ADD26_I_I_I:%.*]] = add nsw i64 [[CONV25_I_I_I]], -55 +// DEFAULT-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[MUL24_I_I_I]] +// DEFAULT-NEXT: br label %[[IF_END31_I_I_I]] // DEFAULT: [[IF_END31_I_I_I]]: -// DEFAULT-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I31_I_I]] ], [ -87, %[[IF_ELSE_I_I_I]] ], [ -55, %[[IF_ELSE17_I_I_I]] ] -// DEFAULT-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I29_I_I11]], 4 -// DEFAULT-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP5]] to i64 -// DEFAULT-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] -// DEFAULT-NEXT: [[ADD28_I_I_I]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I34_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I28_I_I10]], i64 1 -// DEFAULT-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I34_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I30_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I30_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I31_I_I]], !llvm.loop [[LOOP13]] -// DEFAULT: [[WHILE_BODY_I_I_I]]: -// DEFAULT-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I_I_I:.*]] ], [ [[TMP3]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[__R_0_I_I_I16:%.*]] = phi i64 [ [[SUB_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[__TAGP_ADDR_0_I_I_I15:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[TMP11:%.*]] = and i8 [[TMP10]], -8 -// DEFAULT-NEXT: [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP11]], 48 -// DEFAULT-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I]], label %[[_ZL3NANPKC_EXIT]] -// DEFAULT: [[IF_THEN_I_I_I]]: -// DEFAULT-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I16]], 3 -// DEFAULT-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 -// DEFAULT-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 -// DEFAULT-NEXT: [[SUB_I_I_I]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I_I_I15]], i64 1 -// DEFAULT-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP9]] -// DEFAULT: [[WHILE_BODY_I18_I_I]]: -// DEFAULT-NEXT: [[TMP13:%.*]] = phi i8 [ [[TMP15:%.*]], %[[IF_THEN_I21_I_I:.*]] ], [ [[TMP1]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[__R_0_I16_I_I7:%.*]] = phi i64 [ [[SUB_I25_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[__TAGP_ADDR_0_I15_I_I6:%.*]] = phi ptr [ [[INCDEC_PTR_I26_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ [[TAG]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// DEFAULT-NEXT: [[TMP14:%.*]] = add i8 [[TMP13]], -48 -// DEFAULT-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP14]], 10 -// DEFAULT-NEXT: br i1 [[OR_COND_I19_I_I]], label %[[IF_THEN_I21_I_I]], label %[[_ZL3NANPKC_EXIT]] -// DEFAULT: [[IF_THEN_I21_I_I]]: -// DEFAULT-NEXT: [[MUL_I22_I_I:%.*]] = mul i64 [[__R_0_I16_I_I7]], 10 -// DEFAULT-NEXT: [[CONV5_I23_I_I:%.*]] = zext nneg i8 [[TMP13]] to i64 -// DEFAULT-NEXT: [[ADD_I24_I_I:%.*]] = add i64 [[MUL_I22_I_I]], -48 -// DEFAULT-NEXT: [[SUB_I25_I_I]] = add i64 [[ADD_I24_I_I]], [[CONV5_I23_I_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I26_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I15_I_I6]], i64 1 -// DEFAULT-NEXT: [[TMP15]] = load i8, ptr [[INCDEC_PTR_I26_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// DEFAULT-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP15]], 0 -// DEFAULT-NEXT: br i1 [[CMP_NOT_I17_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I18_I_I]], !llvm.loop [[LOOP12]] +// DEFAULT-NEXT: [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ [[ADD16_I_I_I]], %[[IF_THEN11_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_THEN23_I_I_I]] ] +// DEFAULT-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_049_I_I_I]], i64 1 +// DEFAULT-NEXT: [[TMP6]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// DEFAULT-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// DEFAULT-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP13]] +// DEFAULT: [[WHILE_BODY_I14_I_I]]: +// DEFAULT-NEXT: [[TMP7:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_THEN_I17_I_I:.*]] ], [ [[TMP1]], %[[IF_THEN_I_I]] ] +// DEFAULT-NEXT: [[__R_014_I_I_I:%.*]] = phi i64 [ [[SUB_I21_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[IF_THEN_I_I]] ] +// DEFAULT-NEXT: [[__TAGP_ADDR_013_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I22_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN_I_I]] ] +// DEFAULT-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], -8 +// DEFAULT-NEXT: [[OR_COND_I15_I_I:%.*]] = icmp eq i8 [[TMP8]], 48 +// DEFAULT-NEXT: br i1 [[OR_COND_I15_I_I]], label %[[IF_THEN_I17_I_I]], label %[[_ZL3NANPKC_EXIT]] +// DEFAULT: [[IF_THEN_I17_I_I]]: +// DEFAULT-NEXT: [[MUL_I18_I_I:%.*]] = shl i64 [[__R_014_I_I_I]], 3 +// DEFAULT-NEXT: [[CONV5_I19_I_I:%.*]] = zext nneg i8 [[TMP7]] to i64 +// DEFAULT-NEXT: [[ADD_I20_I_I:%.*]] = add nsw i64 [[CONV5_I19_I_I]], -48 +// DEFAULT-NEXT: [[SUB_I21_I_I]] = or disjoint i64 [[ADD_I20_I_I]], [[MUL_I18_I_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I22_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I_I_I]], i64 1 +// DEFAULT-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I22_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// DEFAULT-NEXT: [[CMP_NOT_I23_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 +// DEFAULT-NEXT: br i1 [[CMP_NOT_I23_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I14_I_I]], !llvm.loop [[LOOP9]] +// DEFAULT: [[WHILE_BODY_I25_I_I]]: +// DEFAULT-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I30_I_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[__R_014_I26_I_I:%.*]] = phi i64 [ [[SUB_I34_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[ENTRY]] ] +// DEFAULT-NEXT: [[__TAGP_ADDR_013_I27_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I35_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ [[TAG]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], -48 +// DEFAULT-NEXT: [[OR_COND_I28_I_I:%.*]] = icmp ult i8 [[TMP11]], 10 +// DEFAULT-NEXT: br i1 [[OR_COND_I28_I_I]], label %[[IF_THEN_I30_I_I]], label %[[_ZL3NANPKC_EXIT]] +// DEFAULT: [[IF_THEN_I30_I_I]]: +// DEFAULT-NEXT: [[MUL_I31_I_I:%.*]] = mul i64 [[__R_014_I26_I_I]], 10 +// DEFAULT-NEXT: [[CONV5_I32_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 +// DEFAULT-NEXT: [[ADD_I33_I_I:%.*]] = add nsw i64 [[CONV5_I32_I_I]], -48 +// DEFAULT-NEXT: [[SUB_I34_I_I]] = add i64 [[ADD_I33_I_I]], [[MUL_I31_I_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I35_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I27_I_I]], i64 1 +// DEFAULT-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I35_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// DEFAULT-NEXT: [[CMP_NOT_I36_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 +// DEFAULT-NEXT: br i1 [[CMP_NOT_I36_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I25_I_I]], !llvm.loop [[LOOP12]] // DEFAULT: [[_ZL3NANPKC_EXIT]]: -// DEFAULT-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ], [ 0, %[[IF_THEN5_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ], [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ], [ [[SUB_I25_I_I]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_BODY_I18_I_I]] ] +// DEFAULT-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[IF_THEN_I_I]] ], [ 0, %[[ENTRY]] ], [ [[SUB_I34_I_I]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[WHILE_BODY_I25_I_I]] ], [ [[SUB_I21_I_I]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[WHILE_BODY_I14_I_I]] ], [ [[__R_1_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ] // DEFAULT-NEXT: [[BF_VALUE_I:%.*]] = and i64 [[RETVAL_0_I_I]], 2251799813685247 // DEFAULT-NEXT: [[BF_SET9_I:%.*]] = or disjoint i64 [[BF_VALUE_I]], 9221120237041090560 -// DEFAULT-NEXT: [[TMP16:%.*]] = bitcast i64 [[BF_SET9_I]] to double -// DEFAULT-NEXT: ret double [[TMP16]] +// DEFAULT-NEXT: [[TMP13:%.*]] = bitcast i64 [[BF_SET9_I]] to double +// DEFAULT-NEXT: ret double [[TMP13]] // // FINITEONLY-LABEL: define dso_local nofpclass(nan inf) double @test_nan( -// FINITEONLY-SAME: ptr noundef readonly captures(none) [[TAG:%.*]]) local_unnamed_addr #[[ATTR3]] { +// FINITEONLY-SAME: ptr noundef readnone captures(none) [[TAG:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] // FINITEONLY-NEXT: ret double poison // // APPROX-LABEL: define dso_local double @test_nan( // APPROX-SAME: ptr noundef readonly captures(none) [[TAG:%.*]]) local_unnamed_addr #[[ATTR2]] { -// APPROX-NEXT: [[ENTRY:.*:]] +// APPROX-NEXT: [[ENTRY:.*]]: // APPROX-NEXT: [[TMP0:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// APPROX-NEXT: br i1 [[CMP_I_I]], label %[[IF_THEN_I_I:.*]], label %[[WHILE_COND_I14_I_I_PREHEADER:.*]] -// APPROX: [[WHILE_COND_I14_I_I_PREHEADER]]: -// APPROX-NEXT: [[TMP1:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I17_I_I5:%.*]] = icmp eq i8 [[TMP1]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I17_I_I5]], label %[[_ZL3NANPKC_EXIT:.*]], label %[[WHILE_BODY_I18_I_I:.*]] +// APPROX-NEXT: switch i8 [[TMP0]], label %[[WHILE_BODY_I25_I_I:.*]] [ +// APPROX-NEXT: i8 48, label %[[IF_THEN_I_I:.*]] +// APPROX-NEXT: i8 0, label %[[_ZL3NANPKC_EXIT:.*]] +// APPROX-NEXT: ] // APPROX: [[IF_THEN_I_I]]: // APPROX-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TAG]], i64 1 -// APPROX-NEXT: [[TMP2:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: switch i8 [[TMP2]], label %[[WHILE_COND_I_I_I_PREHEADER:.*]] [ -// APPROX-NEXT: i8 120, label %[[IF_THEN5_I_I:.*]] -// APPROX-NEXT: i8 88, label %[[IF_THEN5_I_I]] +// APPROX-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// APPROX-NEXT: switch i8 [[TMP1]], label %[[WHILE_BODY_I14_I_I:.*]] [ +// APPROX-NEXT: i8 88, label %[[WHILE_BODY_I_I_I_PREHEADER:.*]] +// APPROX-NEXT: i8 120, label %[[WHILE_BODY_I_I_I_PREHEADER]] +// APPROX-NEXT: i8 0, label %[[_ZL3NANPKC_EXIT]] // APPROX-NEXT: ] -// APPROX: [[WHILE_COND_I_I_I_PREHEADER]]: -// APPROX-NEXT: [[TMP3:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I_I_I14:%.*]] = icmp eq i8 [[TMP3]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I_I_I14]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I:.*]] -// APPROX: [[IF_THEN5_I_I]]: -// APPROX-NEXT: [[TMP4:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I30_I_I9:%.*]] = icmp eq i8 [[TMP4]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I30_I_I9]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I31_I_I:.*]] -// APPROX: [[WHILE_BODY_I31_I_I]]: -// APPROX-NEXT: [[TMP5:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP4]], %[[IF_THEN5_I_I]] ] -// APPROX-NEXT: [[__R_0_I29_I_I11:%.*]] = phi i64 [ [[ADD28_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_THEN5_I_I]] ] -// APPROX-NEXT: [[__TAGP_ADDR_0_I28_I_I10:%.*]] = phi ptr [ [[INCDEC_PTR_I34_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN5_I_I]] ] -// APPROX-NEXT: [[TMP6:%.*]] = add i8 [[TMP5]], -48 -// APPROX-NEXT: [[OR_COND_I32_I_I:%.*]] = icmp ult i8 [[TMP6]], 10 -// APPROX-NEXT: br i1 [[OR_COND_I32_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE_I_I_I:.*]] +// APPROX: [[WHILE_BODY_I_I_I_PREHEADER]]: +// APPROX-NEXT: br label %[[WHILE_BODY_I_I_I:.*]] +// APPROX: [[WHILE_BODY_I_I_I]]: +// APPROX-NEXT: [[TMP2:%.*]] = phi i8 [ [[TMP6:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP1]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// APPROX-NEXT: [[__R_050_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// APPROX-NEXT: [[__TAGP_ADDR_049_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// APPROX-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 +// APPROX-NEXT: [[OR_COND_I_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// APPROX-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I:.*]], label %[[IF_ELSE_I_I_I:.*]] +// APPROX: [[IF_THEN_I_I_I]]: +// APPROX-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// APPROX-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// APPROX-NEXT: [[ADD_I_I_I:%.*]] = add nsw i64 [[CONV5_I_I_I]], -48 +// APPROX-NEXT: [[SUB_I_I_I:%.*]] = or disjoint i64 [[ADD_I_I_I]], [[MUL_I_I_I]] +// APPROX-NEXT: br label %[[IF_END31_I_I_I]] // APPROX: [[IF_ELSE_I_I_I]]: -// APPROX-NEXT: [[TMP7:%.*]] = add i8 [[TMP5]], -97 -// APPROX-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP7]], 6 -// APPROX-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE17_I_I_I:.*]] +// APPROX-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 +// APPROX-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 +// APPROX-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_THEN11_I_I_I:.*]], label %[[IF_ELSE17_I_I_I:.*]] +// APPROX: [[IF_THEN11_I_I_I]]: +// APPROX-NEXT: [[MUL12_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// APPROX-NEXT: [[CONV13_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// APPROX-NEXT: [[ADD14_I_I_I:%.*]] = add nsw i64 [[CONV13_I_I_I]], -87 +// APPROX-NEXT: [[ADD16_I_I_I:%.*]] = add i64 [[ADD14_I_I_I]], [[MUL12_I_I_I]] +// APPROX-NEXT: br label %[[IF_END31_I_I_I]] // APPROX: [[IF_ELSE17_I_I_I]]: -// APPROX-NEXT: [[TMP8:%.*]] = add i8 [[TMP5]], -65 -// APPROX-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP8]], 6 -// APPROX-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_END31_I_I_I]], label %[[_ZL3NANPKC_EXIT]] +// APPROX-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 +// APPROX-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 +// APPROX-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_THEN23_I_I_I:.*]], label %[[_ZL3NANPKC_EXIT]] +// APPROX: [[IF_THEN23_I_I_I]]: +// APPROX-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// APPROX-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// APPROX-NEXT: [[ADD26_I_I_I:%.*]] = add nsw i64 [[CONV25_I_I_I]], -55 +// APPROX-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[MUL24_I_I_I]] +// APPROX-NEXT: br label %[[IF_END31_I_I_I]] // APPROX: [[IF_END31_I_I_I]]: -// APPROX-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I31_I_I]] ], [ -87, %[[IF_ELSE_I_I_I]] ], [ -55, %[[IF_ELSE17_I_I_I]] ] -// APPROX-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I29_I_I11]], 4 -// APPROX-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP5]] to i64 -// APPROX-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] -// APPROX-NEXT: [[ADD28_I_I_I]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] -// APPROX-NEXT: [[INCDEC_PTR_I34_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I28_I_I10]], i64 1 -// APPROX-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I34_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I30_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I30_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I31_I_I]], !llvm.loop [[LOOP13]] -// APPROX: [[WHILE_BODY_I_I_I]]: -// APPROX-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I_I_I:.*]] ], [ [[TMP3]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// APPROX-NEXT: [[__R_0_I_I_I16:%.*]] = phi i64 [ [[SUB_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ] -// APPROX-NEXT: [[__TAGP_ADDR_0_I_I_I15:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// APPROX-NEXT: [[TMP11:%.*]] = and i8 [[TMP10]], -8 -// APPROX-NEXT: [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP11]], 48 -// APPROX-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I]], label %[[_ZL3NANPKC_EXIT]] -// APPROX: [[IF_THEN_I_I_I]]: -// APPROX-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I16]], 3 -// APPROX-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 -// APPROX-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 -// APPROX-NEXT: [[SUB_I_I_I]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] -// APPROX-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I_I_I15]], i64 1 -// APPROX-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP9]] -// APPROX: [[WHILE_BODY_I18_I_I]]: -// APPROX-NEXT: [[TMP13:%.*]] = phi i8 [ [[TMP15:%.*]], %[[IF_THEN_I21_I_I:.*]] ], [ [[TMP1]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// APPROX-NEXT: [[__R_0_I16_I_I7:%.*]] = phi i64 [ [[SUB_I25_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// APPROX-NEXT: [[__TAGP_ADDR_0_I15_I_I6:%.*]] = phi ptr [ [[INCDEC_PTR_I26_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ [[TAG]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// APPROX-NEXT: [[TMP14:%.*]] = add i8 [[TMP13]], -48 -// APPROX-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP14]], 10 -// APPROX-NEXT: br i1 [[OR_COND_I19_I_I]], label %[[IF_THEN_I21_I_I]], label %[[_ZL3NANPKC_EXIT]] -// APPROX: [[IF_THEN_I21_I_I]]: -// APPROX-NEXT: [[MUL_I22_I_I:%.*]] = mul i64 [[__R_0_I16_I_I7]], 10 -// APPROX-NEXT: [[CONV5_I23_I_I:%.*]] = zext nneg i8 [[TMP13]] to i64 -// APPROX-NEXT: [[ADD_I24_I_I:%.*]] = add i64 [[MUL_I22_I_I]], -48 -// APPROX-NEXT: [[SUB_I25_I_I]] = add i64 [[ADD_I24_I_I]], [[CONV5_I23_I_I]] -// APPROX-NEXT: [[INCDEC_PTR_I26_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I15_I_I6]], i64 1 -// APPROX-NEXT: [[TMP15]] = load i8, ptr [[INCDEC_PTR_I26_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// APPROX-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP15]], 0 -// APPROX-NEXT: br i1 [[CMP_NOT_I17_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I18_I_I]], !llvm.loop [[LOOP12]] +// APPROX-NEXT: [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ [[ADD16_I_I_I]], %[[IF_THEN11_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_THEN23_I_I_I]] ] +// APPROX-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_049_I_I_I]], i64 1 +// APPROX-NEXT: [[TMP6]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// APPROX-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// APPROX-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP13]] +// APPROX: [[WHILE_BODY_I14_I_I]]: +// APPROX-NEXT: [[TMP7:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_THEN_I17_I_I:.*]] ], [ [[TMP1]], %[[IF_THEN_I_I]] ] +// APPROX-NEXT: [[__R_014_I_I_I:%.*]] = phi i64 [ [[SUB_I21_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[IF_THEN_I_I]] ] +// APPROX-NEXT: [[__TAGP_ADDR_013_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I22_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN_I_I]] ] +// APPROX-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], -8 +// APPROX-NEXT: [[OR_COND_I15_I_I:%.*]] = icmp eq i8 [[TMP8]], 48 +// APPROX-NEXT: br i1 [[OR_COND_I15_I_I]], label %[[IF_THEN_I17_I_I]], label %[[_ZL3NANPKC_EXIT]] +// APPROX: [[IF_THEN_I17_I_I]]: +// APPROX-NEXT: [[MUL_I18_I_I:%.*]] = shl i64 [[__R_014_I_I_I]], 3 +// APPROX-NEXT: [[CONV5_I19_I_I:%.*]] = zext nneg i8 [[TMP7]] to i64 +// APPROX-NEXT: [[ADD_I20_I_I:%.*]] = add nsw i64 [[CONV5_I19_I_I]], -48 +// APPROX-NEXT: [[SUB_I21_I_I]] = or disjoint i64 [[ADD_I20_I_I]], [[MUL_I18_I_I]] +// APPROX-NEXT: [[INCDEC_PTR_I22_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I_I_I]], i64 1 +// APPROX-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I22_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// APPROX-NEXT: [[CMP_NOT_I23_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 +// APPROX-NEXT: br i1 [[CMP_NOT_I23_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I14_I_I]], !llvm.loop [[LOOP9]] +// APPROX: [[WHILE_BODY_I25_I_I]]: +// APPROX-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I30_I_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] +// APPROX-NEXT: [[__R_014_I26_I_I:%.*]] = phi i64 [ [[SUB_I34_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[ENTRY]] ] +// APPROX-NEXT: [[__TAGP_ADDR_013_I27_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I35_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ [[TAG]], %[[ENTRY]] ] +// APPROX-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], -48 +// APPROX-NEXT: [[OR_COND_I28_I_I:%.*]] = icmp ult i8 [[TMP11]], 10 +// APPROX-NEXT: br i1 [[OR_COND_I28_I_I]], label %[[IF_THEN_I30_I_I]], label %[[_ZL3NANPKC_EXIT]] +// APPROX: [[IF_THEN_I30_I_I]]: +// APPROX-NEXT: [[MUL_I31_I_I:%.*]] = mul i64 [[__R_014_I26_I_I]], 10 +// APPROX-NEXT: [[CONV5_I32_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 +// APPROX-NEXT: [[ADD_I33_I_I:%.*]] = add nsw i64 [[CONV5_I32_I_I]], -48 +// APPROX-NEXT: [[SUB_I34_I_I]] = add i64 [[ADD_I33_I_I]], [[MUL_I31_I_I]] +// APPROX-NEXT: [[INCDEC_PTR_I35_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I27_I_I]], i64 1 +// APPROX-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I35_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// APPROX-NEXT: [[CMP_NOT_I36_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 +// APPROX-NEXT: br i1 [[CMP_NOT_I36_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I25_I_I]], !llvm.loop [[LOOP12]] // APPROX: [[_ZL3NANPKC_EXIT]]: -// APPROX-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ], [ 0, %[[IF_THEN5_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ], [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ], [ [[SUB_I25_I_I]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_BODY_I18_I_I]] ] +// APPROX-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[IF_THEN_I_I]] ], [ 0, %[[ENTRY]] ], [ [[SUB_I34_I_I]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[WHILE_BODY_I25_I_I]] ], [ [[SUB_I21_I_I]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[WHILE_BODY_I14_I_I]] ], [ [[__R_1_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ] // APPROX-NEXT: [[BF_VALUE_I:%.*]] = and i64 [[RETVAL_0_I_I]], 2251799813685247 // APPROX-NEXT: [[BF_SET9_I:%.*]] = or disjoint i64 [[BF_VALUE_I]], 9221120237041090560 -// APPROX-NEXT: [[TMP16:%.*]] = bitcast i64 [[BF_SET9_I]] to double -// APPROX-NEXT: ret double [[TMP16]] +// APPROX-NEXT: [[TMP13:%.*]] = bitcast i64 [[BF_SET9_I]] to double +// APPROX-NEXT: ret double [[TMP13]] // // NCRDIV-LABEL: define dso_local double @test_nan( // NCRDIV-SAME: ptr noundef readonly captures(none) [[TAG:%.*]]) local_unnamed_addr #[[ATTR2]] { -// NCRDIV-NEXT: [[ENTRY:.*:]] +// NCRDIV-NEXT: [[ENTRY:.*]]: // NCRDIV-NEXT: [[TMP0:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// NCRDIV-NEXT: br i1 [[CMP_I_I]], label %[[IF_THEN_I_I:.*]], label %[[WHILE_COND_I14_I_I_PREHEADER:.*]] -// NCRDIV: [[WHILE_COND_I14_I_I_PREHEADER]]: -// NCRDIV-NEXT: [[TMP1:%.*]] = load i8, ptr [[TAG]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I17_I_I5:%.*]] = icmp eq i8 [[TMP1]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I17_I_I5]], label %[[_ZL3NANPKC_EXIT:.*]], label %[[WHILE_BODY_I18_I_I:.*]] +// NCRDIV-NEXT: switch i8 [[TMP0]], label %[[WHILE_BODY_I25_I_I:.*]] [ +// NCRDIV-NEXT: i8 48, label %[[IF_THEN_I_I:.*]] +// NCRDIV-NEXT: i8 0, label %[[_ZL3NANPKC_EXIT:.*]] +// NCRDIV-NEXT: ] // NCRDIV: [[IF_THEN_I_I]]: // NCRDIV-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TAG]], i64 1 -// NCRDIV-NEXT: [[TMP2:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: switch i8 [[TMP2]], label %[[WHILE_COND_I_I_I_PREHEADER:.*]] [ -// NCRDIV-NEXT: i8 120, label %[[IF_THEN5_I_I:.*]] -// NCRDIV-NEXT: i8 88, label %[[IF_THEN5_I_I]] +// NCRDIV-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// NCRDIV-NEXT: switch i8 [[TMP1]], label %[[WHILE_BODY_I14_I_I:.*]] [ +// NCRDIV-NEXT: i8 88, label %[[WHILE_BODY_I_I_I_PREHEADER:.*]] +// NCRDIV-NEXT: i8 120, label %[[WHILE_BODY_I_I_I_PREHEADER]] +// NCRDIV-NEXT: i8 0, label %[[_ZL3NANPKC_EXIT]] // NCRDIV-NEXT: ] -// NCRDIV: [[WHILE_COND_I_I_I_PREHEADER]]: -// NCRDIV-NEXT: [[TMP3:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I_I_I14:%.*]] = icmp eq i8 [[TMP3]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I_I_I14]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I:.*]] -// NCRDIV: [[IF_THEN5_I_I]]: -// NCRDIV-NEXT: [[TMP4:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I30_I_I9:%.*]] = icmp eq i8 [[TMP4]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I30_I_I9]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I31_I_I:.*]] -// NCRDIV: [[WHILE_BODY_I31_I_I]]: -// NCRDIV-NEXT: [[TMP5:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP4]], %[[IF_THEN5_I_I]] ] -// NCRDIV-NEXT: [[__R_0_I29_I_I11:%.*]] = phi i64 [ [[ADD28_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_THEN5_I_I]] ] -// NCRDIV-NEXT: [[__TAGP_ADDR_0_I28_I_I10:%.*]] = phi ptr [ [[INCDEC_PTR_I34_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN5_I_I]] ] -// NCRDIV-NEXT: [[TMP6:%.*]] = add i8 [[TMP5]], -48 -// NCRDIV-NEXT: [[OR_COND_I32_I_I:%.*]] = icmp ult i8 [[TMP6]], 10 -// NCRDIV-NEXT: br i1 [[OR_COND_I32_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE_I_I_I:.*]] +// NCRDIV: [[WHILE_BODY_I_I_I_PREHEADER]]: +// NCRDIV-NEXT: br label %[[WHILE_BODY_I_I_I:.*]] +// NCRDIV: [[WHILE_BODY_I_I_I]]: +// NCRDIV-NEXT: [[TMP2:%.*]] = phi i8 [ [[TMP6:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP1]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// NCRDIV-NEXT: [[__R_050_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// NCRDIV-NEXT: [[__TAGP_ADDR_049_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// NCRDIV-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 +// NCRDIV-NEXT: [[OR_COND_I_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// NCRDIV-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I:.*]], label %[[IF_ELSE_I_I_I:.*]] +// NCRDIV: [[IF_THEN_I_I_I]]: +// NCRDIV-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// NCRDIV-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// NCRDIV-NEXT: [[ADD_I_I_I:%.*]] = add nsw i64 [[CONV5_I_I_I]], -48 +// NCRDIV-NEXT: [[SUB_I_I_I:%.*]] = or disjoint i64 [[ADD_I_I_I]], [[MUL_I_I_I]] +// NCRDIV-NEXT: br label %[[IF_END31_I_I_I]] // NCRDIV: [[IF_ELSE_I_I_I]]: -// NCRDIV-NEXT: [[TMP7:%.*]] = add i8 [[TMP5]], -97 -// NCRDIV-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP7]], 6 -// NCRDIV-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE17_I_I_I:.*]] +// NCRDIV-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 +// NCRDIV-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 +// NCRDIV-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_THEN11_I_I_I:.*]], label %[[IF_ELSE17_I_I_I:.*]] +// NCRDIV: [[IF_THEN11_I_I_I]]: +// NCRDIV-NEXT: [[MUL12_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// NCRDIV-NEXT: [[CONV13_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// NCRDIV-NEXT: [[ADD14_I_I_I:%.*]] = add nsw i64 [[CONV13_I_I_I]], -87 +// NCRDIV-NEXT: [[ADD16_I_I_I:%.*]] = add i64 [[ADD14_I_I_I]], [[MUL12_I_I_I]] +// NCRDIV-NEXT: br label %[[IF_END31_I_I_I]] // NCRDIV: [[IF_ELSE17_I_I_I]]: -// NCRDIV-NEXT: [[TMP8:%.*]] = add i8 [[TMP5]], -65 -// NCRDIV-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP8]], 6 -// NCRDIV-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_END31_I_I_I]], label %[[_ZL3NANPKC_EXIT]] +// NCRDIV-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 +// NCRDIV-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 +// NCRDIV-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_THEN23_I_I_I:.*]], label %[[_ZL3NANPKC_EXIT]] +// NCRDIV: [[IF_THEN23_I_I_I]]: +// NCRDIV-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// NCRDIV-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// NCRDIV-NEXT: [[ADD26_I_I_I:%.*]] = add nsw i64 [[CONV25_I_I_I]], -55 +// NCRDIV-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[MUL24_I_I_I]] +// NCRDIV-NEXT: br label %[[IF_END31_I_I_I]] // NCRDIV: [[IF_END31_I_I_I]]: -// NCRDIV-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I31_I_I]] ], [ -87, %[[IF_ELSE_I_I_I]] ], [ -55, %[[IF_ELSE17_I_I_I]] ] -// NCRDIV-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I29_I_I11]], 4 -// NCRDIV-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP5]] to i64 -// NCRDIV-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] -// NCRDIV-NEXT: [[ADD28_I_I_I]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] -// NCRDIV-NEXT: [[INCDEC_PTR_I34_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I28_I_I10]], i64 1 -// NCRDIV-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I34_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I30_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I30_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I31_I_I]], !llvm.loop [[LOOP13]] -// NCRDIV: [[WHILE_BODY_I_I_I]]: -// NCRDIV-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I_I_I:.*]] ], [ [[TMP3]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[__R_0_I_I_I16:%.*]] = phi i64 [ [[SUB_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[__TAGP_ADDR_0_I_I_I15:%.*]] = phi ptr [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_THEN_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_COND_I_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[TMP11:%.*]] = and i8 [[TMP10]], -8 -// NCRDIV-NEXT: [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP11]], 48 -// NCRDIV-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I]], label %[[_ZL3NANPKC_EXIT]] -// NCRDIV: [[IF_THEN_I_I_I]]: -// NCRDIV-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I16]], 3 -// NCRDIV-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 -// NCRDIV-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 -// NCRDIV-NEXT: [[SUB_I_I_I]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] -// NCRDIV-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I_I_I15]], i64 1 -// NCRDIV-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP9]] -// NCRDIV: [[WHILE_BODY_I18_I_I]]: -// NCRDIV-NEXT: [[TMP13:%.*]] = phi i8 [ [[TMP15:%.*]], %[[IF_THEN_I21_I_I:.*]] ], [ [[TMP1]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[__R_0_I16_I_I7:%.*]] = phi i64 [ [[SUB_I25_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[__TAGP_ADDR_0_I15_I_I6:%.*]] = phi ptr [ [[INCDEC_PTR_I26_I_I:%.*]], %[[IF_THEN_I21_I_I]] ], [ [[TAG]], %[[WHILE_COND_I14_I_I_PREHEADER]] ] -// NCRDIV-NEXT: [[TMP14:%.*]] = add i8 [[TMP13]], -48 -// NCRDIV-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP14]], 10 -// NCRDIV-NEXT: br i1 [[OR_COND_I19_I_I]], label %[[IF_THEN_I21_I_I]], label %[[_ZL3NANPKC_EXIT]] -// NCRDIV: [[IF_THEN_I21_I_I]]: -// NCRDIV-NEXT: [[MUL_I22_I_I:%.*]] = mul i64 [[__R_0_I16_I_I7]], 10 -// NCRDIV-NEXT: [[CONV5_I23_I_I:%.*]] = zext nneg i8 [[TMP13]] to i64 -// NCRDIV-NEXT: [[ADD_I24_I_I:%.*]] = add i64 [[MUL_I22_I_I]], -48 -// NCRDIV-NEXT: [[SUB_I25_I_I]] = add i64 [[ADD_I24_I_I]], [[CONV5_I23_I_I]] -// NCRDIV-NEXT: [[INCDEC_PTR_I26_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I15_I_I6]], i64 1 -// NCRDIV-NEXT: [[TMP15]] = load i8, ptr [[INCDEC_PTR_I26_I_I]], align 1, !tbaa [[CHAR_TBAA8]] -// NCRDIV-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP15]], 0 -// NCRDIV-NEXT: br i1 [[CMP_NOT_I17_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I18_I_I]], !llvm.loop [[LOOP12]] +// NCRDIV-NEXT: [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ [[ADD16_I_I_I]], %[[IF_THEN11_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_THEN23_I_I_I]] ] +// NCRDIV-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_049_I_I_I]], i64 1 +// NCRDIV-NEXT: [[TMP6]] = load i8, ptr [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// NCRDIV-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// NCRDIV-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP13]] +// NCRDIV: [[WHILE_BODY_I14_I_I]]: +// NCRDIV-NEXT: [[TMP7:%.*]] = phi i8 [ [[TMP9:%.*]], %[[IF_THEN_I17_I_I:.*]] ], [ [[TMP1]], %[[IF_THEN_I_I]] ] +// NCRDIV-NEXT: [[__R_014_I_I_I:%.*]] = phi i64 [ [[SUB_I21_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[IF_THEN_I_I]] ] +// NCRDIV-NEXT: [[__TAGP_ADDR_013_I_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I22_I_I:%.*]], %[[IF_THEN_I17_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN_I_I]] ] +// NCRDIV-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], -8 +// NCRDIV-NEXT: [[OR_COND_I15_I_I:%.*]] = icmp eq i8 [[TMP8]], 48 +// NCRDIV-NEXT: br i1 [[OR_COND_I15_I_I]], label %[[IF_THEN_I17_I_I]], label %[[_ZL3NANPKC_EXIT]] +// NCRDIV: [[IF_THEN_I17_I_I]]: +// NCRDIV-NEXT: [[MUL_I18_I_I:%.*]] = shl i64 [[__R_014_I_I_I]], 3 +// NCRDIV-NEXT: [[CONV5_I19_I_I:%.*]] = zext nneg i8 [[TMP7]] to i64 +// NCRDIV-NEXT: [[ADD_I20_I_I:%.*]] = add nsw i64 [[CONV5_I19_I_I]], -48 +// NCRDIV-NEXT: [[SUB_I21_I_I]] = or disjoint i64 [[ADD_I20_I_I]], [[MUL_I18_I_I]] +// NCRDIV-NEXT: [[INCDEC_PTR_I22_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I_I_I]], i64 1 +// NCRDIV-NEXT: [[TMP9]] = load i8, ptr [[INCDEC_PTR_I22_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// NCRDIV-NEXT: [[CMP_NOT_I23_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 +// NCRDIV-NEXT: br i1 [[CMP_NOT_I23_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I14_I_I]], !llvm.loop [[LOOP9]] +// NCRDIV: [[WHILE_BODY_I25_I_I]]: +// NCRDIV-NEXT: [[TMP10:%.*]] = phi i8 [ [[TMP12:%.*]], %[[IF_THEN_I30_I_I:.*]] ], [ [[TMP0]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[__R_014_I26_I_I:%.*]] = phi i64 [ [[SUB_I34_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[ENTRY]] ] +// NCRDIV-NEXT: [[__TAGP_ADDR_013_I27_I_I:%.*]] = phi ptr [ [[INCDEC_PTR_I35_I_I:%.*]], %[[IF_THEN_I30_I_I]] ], [ [[TAG]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], -48 +// NCRDIV-NEXT: [[OR_COND_I28_I_I:%.*]] = icmp ult i8 [[TMP11]], 10 +// NCRDIV-NEXT: br i1 [[OR_COND_I28_I_I]], label %[[IF_THEN_I30_I_I]], label %[[_ZL3NANPKC_EXIT]] +// NCRDIV: [[IF_THEN_I30_I_I]]: +// NCRDIV-NEXT: [[MUL_I31_I_I:%.*]] = mul i64 [[__R_014_I26_I_I]], 10 +// NCRDIV-NEXT: [[CONV5_I32_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 +// NCRDIV-NEXT: [[ADD_I33_I_I:%.*]] = add nsw i64 [[CONV5_I32_I_I]], -48 +// NCRDIV-NEXT: [[SUB_I34_I_I]] = add i64 [[ADD_I33_I_I]], [[MUL_I31_I_I]] +// NCRDIV-NEXT: [[INCDEC_PTR_I35_I_I]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_013_I27_I_I]], i64 1 +// NCRDIV-NEXT: [[TMP12]] = load i8, ptr [[INCDEC_PTR_I35_I_I]], align 1, !tbaa [[CHAR_TBAA8]] +// NCRDIV-NEXT: [[CMP_NOT_I36_I_I:%.*]] = icmp eq i8 [[TMP12]], 0 +// NCRDIV-NEXT: br i1 [[CMP_NOT_I36_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I25_I_I]], !llvm.loop [[LOOP12]] // NCRDIV: [[_ZL3NANPKC_EXIT]]: -// NCRDIV-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[WHILE_COND_I_I_I_PREHEADER]] ], [ 0, %[[IF_THEN5_I_I]] ], [ 0, %[[WHILE_COND_I14_I_I_PREHEADER]] ], [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ], [ [[SUB_I25_I_I]], %[[IF_THEN_I21_I_I]] ], [ 0, %[[WHILE_BODY_I18_I_I]] ] +// NCRDIV-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[IF_THEN_I_I]] ], [ 0, %[[ENTRY]] ], [ [[SUB_I34_I_I]], %[[IF_THEN_I30_I_I]] ], [ 0, %[[WHILE_BODY_I25_I_I]] ], [ [[SUB_I21_I_I]], %[[IF_THEN_I17_I_I]] ], [ 0, %[[WHILE_BODY_I14_I_I]] ], [ [[__R_1_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ] // NCRDIV-NEXT: [[BF_VALUE_I:%.*]] = and i64 [[RETVAL_0_I_I]], 2251799813685247 // NCRDIV-NEXT: [[BF_SET9_I:%.*]] = or disjoint i64 [[BF_VALUE_I]], 9221120237041090560 -// NCRDIV-NEXT: [[TMP16:%.*]] = bitcast i64 [[BF_SET9_I]] to double -// NCRDIV-NEXT: ret double [[TMP16]] +// NCRDIV-NEXT: [[TMP13:%.*]] = bitcast i64 [[BF_SET9_I]] to double +// NCRDIV-NEXT: ret double [[TMP13]] // // AMDGCNSPIRV-LABEL: define spir_func double @test_nan( // AMDGCNSPIRV-SAME: ptr addrspace(4) noundef readonly captures(none) [[TAG:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR2]] { // AMDGCNSPIRV-NEXT: [[ENTRY:.*]]: // AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load i8, ptr addrspace(4) [[TAG]], align 1, !tbaa [[CHAR_TBAA9]] // AMDGCNSPIRV-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_I_I]], label %[[IF_THEN_I_I:.*]], label %[[WHILE_COND_I14_I_I:.*]] +// AMDGCNSPIRV-NEXT: br i1 [[CMP_I_I]], label %[[IF_THEN_I_I:.*]], label %[[WHILE_COND_I23_I_I:.*]] // AMDGCNSPIRV: [[IF_THEN_I_I]]: // AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TAG]], i64 1 // AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA9]] // AMDGCNSPIRV-NEXT: switch i8 [[TMP1]], label %[[WHILE_COND_I_I_I:.*]] [ -// AMDGCNSPIRV-NEXT: i8 120, label %[[IF_THEN5_I_I:.*]] -// AMDGCNSPIRV-NEXT: i8 88, label %[[IF_THEN5_I_I]] +// AMDGCNSPIRV-NEXT: i8 88, label %[[WHILE_BODY_I_I_I_PREHEADER:.*]] +// AMDGCNSPIRV-NEXT: i8 120, label %[[WHILE_BODY_I_I_I_PREHEADER]] // AMDGCNSPIRV-NEXT: ] -// AMDGCNSPIRV: [[IF_THEN5_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I31_I_I5:%.*]] = icmp eq i8 [[TMP2]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I31_I_I5]], label %[[_ZL3NANPKC_EXIT:.*]], label %[[WHILE_BODY_I32_I_I:.*]] -// AMDGCNSPIRV: [[WHILE_BODY_I32_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = phi i8 [ [[TMP7:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP2]], %[[IF_THEN5_I_I]] ] -// AMDGCNSPIRV-NEXT: [[__R_0_I30_I_I7:%.*]] = phi i64 [ [[ADD28_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_THEN5_I_I]] ] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I29_I_I6:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I36_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN5_I_I]] ] -// AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = add i8 [[TMP3]], -48 -// AMDGCNSPIRV-NEXT: [[OR_COND_I33_I_I:%.*]] = icmp ult i8 [[TMP4]], 10 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I33_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE_I_I_I:.*]] +// AMDGCNSPIRV: [[WHILE_BODY_I_I_I_PREHEADER]]: +// AMDGCNSPIRV-NEXT: br label %[[WHILE_BODY_I_I_I:.*]] +// AMDGCNSPIRV: [[WHILE_BODY_I_I_I]]: +// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = phi i8 [ [[TMP6:%.*]], %[[IF_END31_I_I_I:.*]] ], [ [[TMP1]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// AMDGCNSPIRV-NEXT: [[__R_050_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_049_I_I_I:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I_I_I:%.*]], %[[IF_END31_I_I_I]] ], [ [[INCDEC_PTR_I_I]], %[[WHILE_BODY_I_I_I_PREHEADER]] ] +// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = add i8 [[TMP2]], -48 +// AMDGCNSPIRV-NEXT: [[OR_COND_I_I_I:%.*]] = icmp ult i8 [[TMP3]], 10 +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I_I_I]], label %[[IF_THEN_I_I_I:.*]], label %[[IF_ELSE_I_I_I:.*]] +// AMDGCNSPIRV: [[IF_THEN_I_I_I]]: +// AMDGCNSPIRV-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD_I_I_I:%.*]] = add nsw i64 [[CONV5_I_I_I]], -48 +// AMDGCNSPIRV-NEXT: [[SUB_I_I_I:%.*]] = or disjoint i64 [[ADD_I_I_I]], [[MUL_I_I_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I_I_I]] // AMDGCNSPIRV: [[IF_ELSE_I_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP5:%.*]] = add i8 [[TMP3]], -97 -// AMDGCNSPIRV-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_END31_I_I_I]], label %[[IF_ELSE17_I_I_I:.*]] +// AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = add i8 [[TMP2]], -97 +// AMDGCNSPIRV-NEXT: [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6 +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND33_I_I_I]], label %[[IF_THEN11_I_I_I:.*]], label %[[IF_ELSE17_I_I_I:.*]] +// AMDGCNSPIRV: [[IF_THEN11_I_I_I]]: +// AMDGCNSPIRV-NEXT: [[MUL12_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV13_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD14_I_I_I:%.*]] = add nsw i64 [[CONV13_I_I_I]], -87 +// AMDGCNSPIRV-NEXT: [[ADD16_I_I_I:%.*]] = add i64 [[ADD14_I_I_I]], [[MUL12_I_I_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I_I_I]] // AMDGCNSPIRV: [[IF_ELSE17_I_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP6:%.*]] = add i8 [[TMP3]], -65 -// AMDGCNSPIRV-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP6]], 6 -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_END31_I_I_I]], label %[[_ZL3NANPKC_EXIT]] +// AMDGCNSPIRV-NEXT: [[TMP5:%.*]] = add i8 [[TMP2]], -65 +// AMDGCNSPIRV-NEXT: [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6 +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND34_I_I_I]], label %[[IF_THEN23_I_I_I:.*]], label %[[_ZL3NANPKC_EXIT:.*]] +// AMDGCNSPIRV: [[IF_THEN23_I_I_I]]: +// AMDGCNSPIRV-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_050_I_I_I]], 4 +// AMDGCNSPIRV-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD26_I_I_I:%.*]] = add nsw i64 [[CONV25_I_I_I]], -55 +// AMDGCNSPIRV-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[MUL24_I_I_I]] +// AMDGCNSPIRV-NEXT: br label %[[IF_END31_I_I_I]] // AMDGCNSPIRV: [[IF_END31_I_I_I]]: -// AMDGCNSPIRV-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, %[[WHILE_BODY_I32_I_I]] ], [ -87, %[[IF_ELSE_I_I_I]] ], [ -55, %[[IF_ELSE17_I_I_I]] ] -// AMDGCNSPIRV-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I30_I_I7]], 4 -// AMDGCNSPIRV-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP3]] to i64 -// AMDGCNSPIRV-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] -// AMDGCNSPIRV-NEXT: [[ADD28_I_I_I]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] -// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I36_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I29_I_I6]], i64 1 -// AMDGCNSPIRV-NEXT: [[TMP7]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I36_I_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I31_I_I:%.*]] = icmp eq i8 [[TMP7]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I31_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I32_I_I]], !llvm.loop [[LOOP14]] +// AMDGCNSPIRV-NEXT: [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], %[[IF_THEN_I_I_I]] ], [ [[ADD16_I_I_I]], %[[IF_THEN11_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_THEN23_I_I_I]] ] +// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_049_I_I_I]], i64 1 +// AMDGCNSPIRV-NEXT: [[TMP6]] = load i8, ptr addrspace(4) [[INCDEC_PTR_I_I_I]], align 1, !tbaa [[CHAR_TBAA9]] +// AMDGCNSPIRV-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I]], !llvm.loop [[LOOP14]] // AMDGCNSPIRV: [[WHILE_COND_I_I_I]]: -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I_I_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I_I_I:%.*]], %[[WHILE_BODY_I_I_I:.*]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN_I_I]] ] -// AMDGCNSPIRV-NEXT: [[__R_0_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], %[[WHILE_BODY_I_I_I]] ], [ 0, %[[IF_THEN_I_I]] ] -// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I_I_I]] -// AMDGCNSPIRV: [[WHILE_BODY_I_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP9:%.*]] = and i8 [[TMP8]], -8 -// AMDGCNSPIRV-NEXT: [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP9]], 48 -// AMDGCNSPIRV-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 3 -// AMDGCNSPIRV-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP8]] to i64 -// AMDGCNSPIRV-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 -// AMDGCNSPIRV-NEXT: [[SUB_I_I_I:%.*]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_I_I_IDX:%.*]] = zext i1 [[OR_COND_I_I_I]] to i64 -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I_I]], i64 [[__TAGP_ADDR_1_I_I_I_IDX]] -// AMDGCNSPIRV-NEXT: [[__R_1_I_I_I]] = select i1 [[OR_COND_I_I_I]], i64 [[SUB_I_I_I]], i64 [[__R_0_I_I_I]] -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I_I_I]], label %[[WHILE_COND_I_I_I]], label %[[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP10]] -// AMDGCNSPIRV: [[WHILE_COND_I14_I_I]]: -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I15_I_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I25_I_I:%.*]], %[[WHILE_BODY_I18_I_I:.*]] ], [ [[TAG]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__R_0_I16_I_I:%.*]] = phi i64 [ [[__R_1_I26_I_I:%.*]], %[[WHILE_BODY_I18_I_I]] ], [ 0, %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[TMP10:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I15_I_I]], align 1, !tbaa [[CHAR_TBAA9]] -// AMDGCNSPIRV-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP10]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I17_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I18_I_I]] -// AMDGCNSPIRV: [[WHILE_BODY_I18_I_I]]: -// AMDGCNSPIRV-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], -48 -// AMDGCNSPIRV-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP11]], 10 -// AMDGCNSPIRV-NEXT: [[MUL_I20_I_I:%.*]] = mul i64 [[__R_0_I16_I_I]], 10 -// AMDGCNSPIRV-NEXT: [[CONV5_I21_I_I:%.*]] = zext nneg i8 [[TMP10]] to i64 -// AMDGCNSPIRV-NEXT: [[ADD_I22_I_I:%.*]] = add i64 [[MUL_I20_I_I]], -48 -// AMDGCNSPIRV-NEXT: [[SUB_I23_I_I:%.*]] = add i64 [[ADD_I22_I_I]], [[CONV5_I21_I_I]] -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I25_I_I_IDX:%.*]] = zext i1 [[OR_COND_I19_I_I]] to i64 -// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I25_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I15_I_I]], i64 [[__TAGP_ADDR_1_I25_I_I_IDX]] -// AMDGCNSPIRV-NEXT: [[__R_1_I26_I_I]] = select i1 [[OR_COND_I19_I_I]], i64 [[SUB_I23_I_I]], i64 [[__R_0_I16_I_I]] -// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I19_I_I]], label %[[WHILE_COND_I14_I_I]], label %[[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP13]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I_I_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I_I_I:%.*]], %[[WHILE_BODY_I15_I_I:.*]] ], [ [[INCDEC_PTR_I_I]], %[[IF_THEN_I_I]] ] +// AMDGCNSPIRV-NEXT: [[__R_0_I_I_I:%.*]] = phi i64 [ [[__R_1_I21_I_I:%.*]], %[[WHILE_BODY_I15_I_I]] ], [ 0, %[[IF_THEN_I_I]] ] +// AMDGCNSPIRV-NEXT: [[TMP7:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I_I]], align 1, !tbaa [[CHAR_TBAA9]] +// AMDGCNSPIRV-NEXT: [[CMP_NOT_I14_I_I:%.*]] = icmp eq i8 [[TMP7]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I14_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I15_I_I]] +// AMDGCNSPIRV: [[WHILE_BODY_I15_I_I]]: +// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], -8 +// AMDGCNSPIRV-NEXT: [[OR_COND_I16_I_I:%.*]] = icmp eq i8 [[TMP8]], 48 +// AMDGCNSPIRV-NEXT: [[MUL_I17_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 3 +// AMDGCNSPIRV-NEXT: [[CONV5_I18_I_I:%.*]] = zext nneg i8 [[TMP7]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD_I19_I_I:%.*]] = add i64 [[MUL_I17_I_I]], -48 +// AMDGCNSPIRV-NEXT: [[SUB_I20_I_I:%.*]] = add i64 [[ADD_I19_I_I]], [[CONV5_I18_I_I]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_IDX_I_I_I:%.*]] = zext i1 [[OR_COND_I16_I_I]] to i64 +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I_I_I]], i64 [[__TAGP_ADDR_1_IDX_I_I_I]] +// AMDGCNSPIRV-NEXT: [[__R_1_I21_I_I]] = select i1 [[OR_COND_I16_I_I]], i64 [[SUB_I20_I_I]], i64 [[__R_0_I_I_I]] +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I16_I_I]], label %[[WHILE_COND_I_I_I]], label %[[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP10]] +// AMDGCNSPIRV: [[WHILE_COND_I23_I_I]]: +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_0_I24_I_I:%.*]] = phi ptr addrspace(4) [ [[__TAGP_ADDR_1_I34_I_I:%.*]], %[[WHILE_BODY_I27_I_I:.*]] ], [ [[TAG]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__R_0_I25_I_I:%.*]] = phi i64 [ [[__R_1_I35_I_I:%.*]], %[[WHILE_BODY_I27_I_I]] ], [ 0, %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[TMP9:%.*]] = load i8, ptr addrspace(4) [[__TAGP_ADDR_0_I24_I_I]], align 1, !tbaa [[CHAR_TBAA9]] +// AMDGCNSPIRV-NEXT: [[CMP_NOT_I26_I_I:%.*]] = icmp eq i8 [[TMP9]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[CMP_NOT_I26_I_I]], label %[[_ZL3NANPKC_EXIT]], label %[[WHILE_BODY_I27_I_I]] +// AMDGCNSPIRV: [[WHILE_BODY_I27_I_I]]: +// AMDGCNSPIRV-NEXT: [[TMP10:%.*]] = add i8 [[TMP9]], -48 +// AMDGCNSPIRV-NEXT: [[OR_COND_I28_I_I:%.*]] = icmp ult i8 [[TMP10]], 10 +// AMDGCNSPIRV-NEXT: [[MUL_I29_I_I:%.*]] = mul i64 [[__R_0_I25_I_I]], 10 +// AMDGCNSPIRV-NEXT: [[CONV5_I30_I_I:%.*]] = zext nneg i8 [[TMP9]] to i64 +// AMDGCNSPIRV-NEXT: [[ADD_I31_I_I:%.*]] = add i64 [[MUL_I29_I_I]], -48 +// AMDGCNSPIRV-NEXT: [[SUB_I32_I_I:%.*]] = add i64 [[ADD_I31_I_I]], [[CONV5_I30_I_I]] +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_IDX_I33_I_I:%.*]] = zext i1 [[OR_COND_I28_I_I]] to i64 +// AMDGCNSPIRV-NEXT: [[__TAGP_ADDR_1_I34_I_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__TAGP_ADDR_0_I24_I_I]], i64 [[__TAGP_ADDR_1_IDX_I33_I_I]] +// AMDGCNSPIRV-NEXT: [[__R_1_I35_I_I]] = select i1 [[OR_COND_I28_I_I]], i64 [[SUB_I32_I_I]], i64 [[__R_0_I25_I_I]] +// AMDGCNSPIRV-NEXT: br i1 [[OR_COND_I28_I_I]], label %[[WHILE_COND_I23_I_I]], label %[[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP13]] // AMDGCNSPIRV: [[_ZL3NANPKC_EXIT]]: -// AMDGCNSPIRV-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[IF_THEN5_I_I]] ], [ 0, %[[WHILE_BODY_I_I_I]] ], [ [[__R_0_I_I_I]], %[[WHILE_COND_I_I_I]] ], [ [[ADD28_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ], [ 0, %[[WHILE_BODY_I18_I_I]] ], [ [[__R_0_I16_I_I]], %[[WHILE_COND_I14_I_I]] ] +// AMDGCNSPIRV-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, %[[WHILE_BODY_I15_I_I]] ], [ [[__R_0_I_I_I]], %[[WHILE_COND_I_I_I]] ], [ [[__R_1_I_I_I]], %[[IF_END31_I_I_I]] ], [ 0, %[[IF_ELSE17_I_I_I]] ], [ 0, %[[WHILE_BODY_I27_I_I]] ], [ [[__R_0_I25_I_I]], %[[WHILE_COND_I23_I_I]] ] // AMDGCNSPIRV-NEXT: [[BF_VALUE_I:%.*]] = and i64 [[RETVAL_0_I_I]], 2251799813685247 // AMDGCNSPIRV-NEXT: [[BF_SET9_I:%.*]] = or disjoint i64 [[BF_VALUE_I]], 9221120237041090560 -// AMDGCNSPIRV-NEXT: [[TMP12:%.*]] = bitcast i64 [[BF_SET9_I]] to double -// AMDGCNSPIRV-NEXT: ret double [[TMP12]] +// AMDGCNSPIRV-NEXT: [[TMP11:%.*]] = bitcast i64 [[BF_SET9_I]] to double +// AMDGCNSPIRV-NEXT: ret double [[TMP11]] // extern "C" __device__ double test_nan(const char *tag) { return nan(tag); @@ -5501,117 +5614,117 @@ extern "C" __device__ double test_normcdfinv(double x) { // DEFAULT-LABEL: define dso_local float @test_normf( // DEFAULT-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR2]] { // DEFAULT-NEXT: [[ENTRY:.*]]: -// DEFAULT-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL5NORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// DEFAULT-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// DEFAULT-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL5NORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // DEFAULT: [[WHILE_BODY_I]]: -// DEFAULT-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// DEFAULT-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// DEFAULT-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// DEFAULT-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[FLOAT_TBAA16]] +// DEFAULT-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// DEFAULT-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// DEFAULT-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[FLOAT_TBAA16]] // DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// DEFAULT-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 4 +// DEFAULT-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 4 // DEFAULT-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 -// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP20:![0-9]+]] -// DEFAULT: [[_ZL5NORMFIPKF_EXIT_LOOPEXIT]]: +// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[WHILE_END_LOOPEXIT_I:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP20:![0-9]+]] +// DEFAULT: [[WHILE_END_LOOPEXIT_I]]: // DEFAULT-NEXT: [[TMP1:%.*]] = tail call contract float @llvm.sqrt.f32(float [[ADD_I]]) // DEFAULT-NEXT: br label %[[_ZL5NORMFIPKF_EXIT]] // DEFAULT: [[_ZL5NORMFIPKF_EXIT]]: -// DEFAULT-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT]] ] -// DEFAULT-NEXT: ret float [[__R_0_I_LCSSA]] +// DEFAULT-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[WHILE_END_LOOPEXIT_I]] ] +// DEFAULT-NEXT: ret float [[__R_0_LCSSA_I]] // // FINITEONLY-LABEL: define dso_local nofpclass(nan inf) float @test_normf( // FINITEONLY-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR2]] { // FINITEONLY-NEXT: [[ENTRY:.*]]: -// FINITEONLY-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL5NORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// FINITEONLY-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL5NORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // FINITEONLY: [[WHILE_BODY_I]]: -// FINITEONLY-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// FINITEONLY-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// FINITEONLY-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// FINITEONLY-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[FLOAT_TBAA16]] +// FINITEONLY-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// FINITEONLY-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// FINITEONLY-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// FINITEONLY-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[FLOAT_TBAA16]] // FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[TMP0]], [[TMP0]] -// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract float [[__R_0_I4]], [[MUL_I]] -// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 4 +// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract float [[__R_08_I]], [[MUL_I]] +// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 4 // FINITEONLY-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 -// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP20:![0-9]+]] -// FINITEONLY: [[_ZL5NORMFIPKF_EXIT_LOOPEXIT]]: +// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[WHILE_END_LOOPEXIT_I:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP20:![0-9]+]] +// FINITEONLY: [[WHILE_END_LOOPEXIT_I]]: // FINITEONLY-NEXT: [[TMP1:%.*]] = tail call nnan ninf contract float @llvm.sqrt.f32(float [[ADD_I]]) // FINITEONLY-NEXT: br label %[[_ZL5NORMFIPKF_EXIT]] // FINITEONLY: [[_ZL5NORMFIPKF_EXIT]]: -// FINITEONLY-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT]] ] -// FINITEONLY-NEXT: ret float [[__R_0_I_LCSSA]] +// FINITEONLY-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[WHILE_END_LOOPEXIT_I]] ] +// FINITEONLY-NEXT: ret float [[__R_0_LCSSA_I]] // // APPROX-LABEL: define dso_local float @test_normf( // APPROX-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR2]] { // APPROX-NEXT: [[ENTRY:.*]]: -// APPROX-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// APPROX-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL5NORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// APPROX-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// APPROX-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL5NORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // APPROX: [[WHILE_BODY_I]]: -// APPROX-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// APPROX-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// APPROX-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// APPROX-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[FLOAT_TBAA16]] +// APPROX-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// APPROX-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// APPROX-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// APPROX-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[FLOAT_TBAA16]] // APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// APPROX-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] -// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 4 +// APPROX-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] +// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 4 // APPROX-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 -// APPROX-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP20:![0-9]+]] -// APPROX: [[_ZL5NORMFIPKF_EXIT_LOOPEXIT]]: +// APPROX-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[WHILE_END_LOOPEXIT_I:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP20:![0-9]+]] +// APPROX: [[WHILE_END_LOOPEXIT_I]]: // APPROX-NEXT: [[TMP1:%.*]] = tail call contract float @llvm.sqrt.f32(float [[ADD_I]]) // APPROX-NEXT: br label %[[_ZL5NORMFIPKF_EXIT]] // APPROX: [[_ZL5NORMFIPKF_EXIT]]: -// APPROX-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT]] ] -// APPROX-NEXT: ret float [[__R_0_I_LCSSA]] +// APPROX-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[WHILE_END_LOOPEXIT_I]] ] +// APPROX-NEXT: ret float [[__R_0_LCSSA_I]] // // NCRDIV-LABEL: define dso_local float @test_normf( // NCRDIV-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR2]] { // NCRDIV-NEXT: [[ENTRY:.*]]: -// NCRDIV-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// NCRDIV-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL5NORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// NCRDIV-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// NCRDIV-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL5NORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // NCRDIV: [[WHILE_BODY_I]]: -// NCRDIV-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// NCRDIV-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// NCRDIV-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// NCRDIV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// NCRDIV-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[FLOAT_TBAA17]] +// NCRDIV-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// NCRDIV-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// NCRDIV-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[FLOAT_TBAA17]] // NCRDIV-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// NCRDIV-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] -// NCRDIV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 4 +// NCRDIV-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] +// NCRDIV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 4 // NCRDIV-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 -// NCRDIV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] -// NCRDIV: [[_ZL5NORMFIPKF_EXIT_LOOPEXIT]]: +// NCRDIV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[WHILE_END_LOOPEXIT_I:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] +// NCRDIV: [[WHILE_END_LOOPEXIT_I]]: // NCRDIV-NEXT: [[TMP1:%.*]] = tail call contract float @llvm.sqrt.f32(float [[ADD_I]]) // NCRDIV-NEXT: br label %[[_ZL5NORMFIPKF_EXIT]] // NCRDIV: [[_ZL5NORMFIPKF_EXIT]]: -// NCRDIV-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT]] ] -// NCRDIV-NEXT: ret float [[__R_0_I_LCSSA]] +// NCRDIV-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[WHILE_END_LOOPEXIT_I]] ] +// NCRDIV-NEXT: ret float [[__R_0_LCSSA_I]] // // AMDGCNSPIRV-LABEL: define spir_func float @test_normf( // AMDGCNSPIRV-SAME: i32 noundef [[X:%.*]], ptr addrspace(4) noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR2]] { // AMDGCNSPIRV-NEXT: [[ENTRY:.*]]: -// AMDGCNSPIRV-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL5NORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// AMDGCNSPIRV-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL5NORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // AMDGCNSPIRV: [[WHILE_BODY_I]]: -// AMDGCNSPIRV-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load float, ptr addrspace(4) [[__A_ADDR_0_I3]], align 4, !tbaa [[FLOAT_TBAA17]] +// AMDGCNSPIRV-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load float, ptr addrspace(4) [[__A_ADDR_07_I]], align 4, !tbaa [[FLOAT_TBAA17]] // AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// AMDGCNSPIRV-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] -// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__A_ADDR_0_I3]], i64 4 +// AMDGCNSPIRV-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] +// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__A_ADDR_07_I]], i64 4 // AMDGCNSPIRV-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] -// AMDGCNSPIRV: [[_ZL5NORMFIPKF_EXIT_LOOPEXIT]]: +// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[WHILE_END_LOOPEXIT_I:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] +// AMDGCNSPIRV: [[WHILE_END_LOOPEXIT_I]]: // AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = tail call contract addrspace(4) float @llvm.sqrt.f32(float [[ADD_I]]) // AMDGCNSPIRV-NEXT: br label %[[_ZL5NORMFIPKF_EXIT]] // AMDGCNSPIRV: [[_ZL5NORMFIPKF_EXIT]]: -// AMDGCNSPIRV-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT]] ] -// AMDGCNSPIRV-NEXT: ret float [[__R_0_I_LCSSA]] +// AMDGCNSPIRV-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[WHILE_END_LOOPEXIT_I]] ] +// AMDGCNSPIRV-NEXT: ret float [[__R_0_LCSSA_I]] // extern "C" __device__ float test_normf(int x, const float *y) { return normf(x, y); @@ -5620,117 +5733,117 @@ extern "C" __device__ float test_normf(int x, const float *y) { // DEFAULT-LABEL: define dso_local double @test_norm( // DEFAULT-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR2]] { // DEFAULT-NEXT: [[ENTRY:.*]]: -// DEFAULT-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL4NORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// DEFAULT-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// DEFAULT-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL4NORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // DEFAULT: [[WHILE_BODY_I]]: -// DEFAULT-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// DEFAULT-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// DEFAULT-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// DEFAULT-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[DOUBLE_TBAA18]] +// DEFAULT-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// DEFAULT-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// DEFAULT-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[DOUBLE_TBAA18]] // DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// DEFAULT-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 8 +// DEFAULT-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 8 // DEFAULT-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 -// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL4NORMIPKD_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] -// DEFAULT: [[_ZL4NORMIPKD_EXIT_LOOPEXIT]]: +// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[WHILE_END_LOOPEXIT_I:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] +// DEFAULT: [[WHILE_END_LOOPEXIT_I]]: // DEFAULT-NEXT: [[TMP1:%.*]] = tail call contract double @llvm.sqrt.f64(double [[ADD_I]]) // DEFAULT-NEXT: br label %[[_ZL4NORMIPKD_EXIT]] // DEFAULT: [[_ZL4NORMIPKD_EXIT]]: -// DEFAULT-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL4NORMIPKD_EXIT_LOOPEXIT]] ] -// DEFAULT-NEXT: ret double [[__R_0_I_LCSSA]] +// DEFAULT-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[WHILE_END_LOOPEXIT_I]] ] +// DEFAULT-NEXT: ret double [[__R_0_LCSSA_I]] // // FINITEONLY-LABEL: define dso_local nofpclass(nan inf) double @test_norm( // FINITEONLY-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR2]] { // FINITEONLY-NEXT: [[ENTRY:.*]]: -// FINITEONLY-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL4NORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// FINITEONLY-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL4NORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // FINITEONLY: [[WHILE_BODY_I]]: -// FINITEONLY-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// FINITEONLY-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// FINITEONLY-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// FINITEONLY-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[DOUBLE_TBAA18]] +// FINITEONLY-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// FINITEONLY-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// FINITEONLY-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// FINITEONLY-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[DOUBLE_TBAA18]] // FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract double [[TMP0]], [[TMP0]] -// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract double [[__R_0_I4]], [[MUL_I]] -// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 8 +// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract double [[__R_08_I]], [[MUL_I]] +// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 8 // FINITEONLY-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 -// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL4NORMIPKD_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] -// FINITEONLY: [[_ZL4NORMIPKD_EXIT_LOOPEXIT]]: +// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[WHILE_END_LOOPEXIT_I:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] +// FINITEONLY: [[WHILE_END_LOOPEXIT_I]]: // FINITEONLY-NEXT: [[TMP1:%.*]] = tail call nnan ninf contract double @llvm.sqrt.f64(double [[ADD_I]]) // FINITEONLY-NEXT: br label %[[_ZL4NORMIPKD_EXIT]] // FINITEONLY: [[_ZL4NORMIPKD_EXIT]]: -// FINITEONLY-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL4NORMIPKD_EXIT_LOOPEXIT]] ] -// FINITEONLY-NEXT: ret double [[__R_0_I_LCSSA]] +// FINITEONLY-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[WHILE_END_LOOPEXIT_I]] ] +// FINITEONLY-NEXT: ret double [[__R_0_LCSSA_I]] // // APPROX-LABEL: define dso_local double @test_norm( // APPROX-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR2]] { // APPROX-NEXT: [[ENTRY:.*]]: -// APPROX-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// APPROX-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL4NORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// APPROX-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// APPROX-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL4NORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // APPROX: [[WHILE_BODY_I]]: -// APPROX-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// APPROX-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// APPROX-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// APPROX-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[DOUBLE_TBAA18]] +// APPROX-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// APPROX-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// APPROX-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// APPROX-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[DOUBLE_TBAA18]] // APPROX-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// APPROX-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] -// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 8 +// APPROX-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] +// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 8 // APPROX-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 -// APPROX-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL4NORMIPKD_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] -// APPROX: [[_ZL4NORMIPKD_EXIT_LOOPEXIT]]: +// APPROX-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[WHILE_END_LOOPEXIT_I:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] +// APPROX: [[WHILE_END_LOOPEXIT_I]]: // APPROX-NEXT: [[TMP1:%.*]] = tail call contract double @llvm.sqrt.f64(double [[ADD_I]]) // APPROX-NEXT: br label %[[_ZL4NORMIPKD_EXIT]] // APPROX: [[_ZL4NORMIPKD_EXIT]]: -// APPROX-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL4NORMIPKD_EXIT_LOOPEXIT]] ] -// APPROX-NEXT: ret double [[__R_0_I_LCSSA]] +// APPROX-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[WHILE_END_LOOPEXIT_I]] ] +// APPROX-NEXT: ret double [[__R_0_LCSSA_I]] // // NCRDIV-LABEL: define dso_local double @test_norm( // NCRDIV-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR2]] { // NCRDIV-NEXT: [[ENTRY:.*]]: -// NCRDIV-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// NCRDIV-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL4NORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// NCRDIV-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// NCRDIV-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL4NORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // NCRDIV: [[WHILE_BODY_I]]: -// NCRDIV-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// NCRDIV-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// NCRDIV-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// NCRDIV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// NCRDIV-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[DOUBLE_TBAA19]] +// NCRDIV-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// NCRDIV-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// NCRDIV-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[DOUBLE_TBAA19]] // NCRDIV-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// NCRDIV-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] -// NCRDIV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 8 +// NCRDIV-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] +// NCRDIV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 8 // NCRDIV-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 -// NCRDIV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL4NORMIPKD_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP22:![0-9]+]] -// NCRDIV: [[_ZL4NORMIPKD_EXIT_LOOPEXIT]]: +// NCRDIV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[WHILE_END_LOOPEXIT_I:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP22:![0-9]+]] +// NCRDIV: [[WHILE_END_LOOPEXIT_I]]: // NCRDIV-NEXT: [[TMP1:%.*]] = tail call contract double @llvm.sqrt.f64(double [[ADD_I]]) // NCRDIV-NEXT: br label %[[_ZL4NORMIPKD_EXIT]] // NCRDIV: [[_ZL4NORMIPKD_EXIT]]: -// NCRDIV-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL4NORMIPKD_EXIT_LOOPEXIT]] ] -// NCRDIV-NEXT: ret double [[__R_0_I_LCSSA]] +// NCRDIV-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[WHILE_END_LOOPEXIT_I]] ] +// NCRDIV-NEXT: ret double [[__R_0_LCSSA_I]] // // AMDGCNSPIRV-LABEL: define spir_func double @test_norm( // AMDGCNSPIRV-SAME: i32 noundef [[X:%.*]], ptr addrspace(4) noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR2]] { // AMDGCNSPIRV-NEXT: [[ENTRY:.*]]: -// AMDGCNSPIRV-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL4NORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// AMDGCNSPIRV-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL4NORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // AMDGCNSPIRV: [[WHILE_BODY_I]]: -// AMDGCNSPIRV-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load double, ptr addrspace(4) [[__A_ADDR_0_I3]], align 8, !tbaa [[DOUBLE_TBAA19]] +// AMDGCNSPIRV-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load double, ptr addrspace(4) [[__A_ADDR_07_I]], align 8, !tbaa [[DOUBLE_TBAA19]] // AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// AMDGCNSPIRV-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] -// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__A_ADDR_0_I3]], i64 8 +// AMDGCNSPIRV-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] +// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__A_ADDR_07_I]], i64 8 // AMDGCNSPIRV-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL4NORMIPKD_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP22:![0-9]+]] -// AMDGCNSPIRV: [[_ZL4NORMIPKD_EXIT_LOOPEXIT]]: +// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[WHILE_END_LOOPEXIT_I:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP22:![0-9]+]] +// AMDGCNSPIRV: [[WHILE_END_LOOPEXIT_I]]: // AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = tail call contract addrspace(4) double @llvm.sqrt.f64(double [[ADD_I]]) // AMDGCNSPIRV-NEXT: br label %[[_ZL4NORMIPKD_EXIT]] // AMDGCNSPIRV: [[_ZL4NORMIPKD_EXIT]]: -// AMDGCNSPIRV-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL4NORMIPKD_EXIT_LOOPEXIT]] ] -// AMDGCNSPIRV-NEXT: ret double [[__R_0_I_LCSSA]] +// AMDGCNSPIRV-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[WHILE_END_LOOPEXIT_I]] ] +// AMDGCNSPIRV-NEXT: ret double [[__R_0_LCSSA_I]] // extern "C" __device__ double test_norm(int x, const double *y) { return norm(x, y); @@ -6267,106 +6380,106 @@ extern "C" __device__ double test_rint(double x) { // DEFAULT-LABEL: define dso_local noundef float @test_rnormf( // DEFAULT-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR5]] { // DEFAULT-NEXT: [[ENTRY:.*]]: -// DEFAULT-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL6RNORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// DEFAULT-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// DEFAULT-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL6RNORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // DEFAULT: [[WHILE_BODY_I]]: -// DEFAULT-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// DEFAULT-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// DEFAULT-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// DEFAULT-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[FLOAT_TBAA16]] +// DEFAULT-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// DEFAULT-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// DEFAULT-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[FLOAT_TBAA16]] // DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// DEFAULT-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 4 +// DEFAULT-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 4 // DEFAULT-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL6RNORMFIPKF_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP22:![0-9]+]] // DEFAULT: [[_ZL6RNORMFIPKF_EXIT]]: -// DEFAULT-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] -// DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_I_LCSSA]]) #[[ATTR13]] +// DEFAULT-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] +// DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_LCSSA_I]]) #[[ATTR13]] // DEFAULT-NEXT: ret float [[CALL_I]] // // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_rnormf( // FINITEONLY-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR5]] { // FINITEONLY-NEXT: [[ENTRY:.*]]: -// FINITEONLY-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL6RNORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// FINITEONLY-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL6RNORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // FINITEONLY: [[WHILE_BODY_I]]: -// FINITEONLY-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// FINITEONLY-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// FINITEONLY-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// FINITEONLY-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[FLOAT_TBAA16]] +// FINITEONLY-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// FINITEONLY-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// FINITEONLY-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// FINITEONLY-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[FLOAT_TBAA16]] // FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[TMP0]], [[TMP0]] -// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract float [[__R_0_I4]], [[MUL_I]] -// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 4 +// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract float [[__R_08_I]], [[MUL_I]] +// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 4 // FINITEONLY-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL6RNORMFIPKF_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP22:![0-9]+]] // FINITEONLY: [[_ZL6RNORMFIPKF_EXIT]]: -// FINITEONLY-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] -// FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_rsqrt_f32(float noundef nofpclass(nan inf) [[__R_0_I_LCSSA]]) #[[ATTR13]] +// FINITEONLY-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] +// FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_rsqrt_f32(float noundef nofpclass(nan inf) [[__R_0_LCSSA_I]]) #[[ATTR13]] // FINITEONLY-NEXT: ret float [[CALL_I]] // // APPROX-LABEL: define dso_local noundef float @test_rnormf( // APPROX-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR5]] { // APPROX-NEXT: [[ENTRY:.*]]: -// APPROX-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// APPROX-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL6RNORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// APPROX-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// APPROX-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL6RNORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // APPROX: [[WHILE_BODY_I]]: -// APPROX-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// APPROX-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// APPROX-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// APPROX-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[FLOAT_TBAA16]] +// APPROX-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// APPROX-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// APPROX-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// APPROX-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[FLOAT_TBAA16]] // APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// APPROX-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] -// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 4 +// APPROX-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] +// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 4 // APPROX-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // APPROX-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL6RNORMFIPKF_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP22:![0-9]+]] // APPROX: [[_ZL6RNORMFIPKF_EXIT]]: -// APPROX-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] -// APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_I_LCSSA]]) #[[ATTR13]] +// APPROX-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] +// APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_LCSSA_I]]) #[[ATTR13]] // APPROX-NEXT: ret float [[CALL_I]] // // NCRDIV-LABEL: define dso_local noundef float @test_rnormf( // NCRDIV-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR5]] { // NCRDIV-NEXT: [[ENTRY:.*]]: -// NCRDIV-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// NCRDIV-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL6RNORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// NCRDIV-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// NCRDIV-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL6RNORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // NCRDIV: [[WHILE_BODY_I]]: -// NCRDIV-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// NCRDIV-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// NCRDIV-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// NCRDIV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// NCRDIV-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[FLOAT_TBAA17]] +// NCRDIV-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// NCRDIV-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// NCRDIV-NEXT: [[TMP0:%.*]] = load float, ptr [[__A_ADDR_07_I]], align 4, !tbaa [[FLOAT_TBAA17]] // NCRDIV-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// NCRDIV-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] -// NCRDIV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 4 +// NCRDIV-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] +// NCRDIV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 4 // NCRDIV-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // NCRDIV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL6RNORMFIPKF_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP23:![0-9]+]] // NCRDIV: [[_ZL6RNORMFIPKF_EXIT]]: -// NCRDIV-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] -// NCRDIV-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_I_LCSSA]]) #[[ATTR13]] +// NCRDIV-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] +// NCRDIV-NEXT: [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_LCSSA_I]]) #[[ATTR13]] // NCRDIV-NEXT: ret float [[CALL_I]] // // AMDGCNSPIRV-LABEL: define spir_func noundef float @test_rnormf( // AMDGCNSPIRV-SAME: i32 noundef [[X:%.*]], ptr addrspace(4) noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR5]] { // AMDGCNSPIRV-NEXT: [[ENTRY:.*]]: -// AMDGCNSPIRV-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL6RNORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// AMDGCNSPIRV-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL6RNORMFIPKF_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // AMDGCNSPIRV: [[WHILE_BODY_I]]: -// AMDGCNSPIRV-NEXT: [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load float, ptr addrspace(4) [[__A_ADDR_0_I3]], align 4, !tbaa [[FLOAT_TBAA17]] +// AMDGCNSPIRV-NEXT: [[__R_08_I:%.*]] = phi float [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load float, ptr addrspace(4) [[__A_ADDR_07_I]], align 4, !tbaa [[FLOAT_TBAA17]] // AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]] -// AMDGCNSPIRV-NEXT: [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]] -// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__A_ADDR_0_I3]], i64 4 +// AMDGCNSPIRV-NEXT: [[ADD_I]] = fadd contract float [[__R_08_I]], [[MUL_I]] +// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__A_ADDR_07_I]], i64 4 // AMDGCNSPIRV-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL6RNORMFIPKF_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP23:![0-9]+]] // AMDGCNSPIRV: [[_ZL6RNORMFIPKF_EXIT]]: -// AMDGCNSPIRV-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] -// AMDGCNSPIRV-NEXT: [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_rsqrt_f32(float noundef [[__R_0_I_LCSSA]]) #[[ATTR13]] +// AMDGCNSPIRV-NEXT: [[__R_0_LCSSA_I:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] +// AMDGCNSPIRV-NEXT: [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_rsqrt_f32(float noundef [[__R_0_LCSSA_I]]) #[[ATTR13]] // AMDGCNSPIRV-NEXT: ret float [[CALL_I]] // extern "C" __device__ float test_rnormf(int x, const float* y) { @@ -6376,106 +6489,106 @@ extern "C" __device__ float test_rnormf(int x, const float* y) { // DEFAULT-LABEL: define dso_local noundef double @test_rnorm( // DEFAULT-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR5]] { // DEFAULT-NEXT: [[ENTRY:.*]]: -// DEFAULT-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL5RNORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// DEFAULT-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// DEFAULT-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL5RNORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // DEFAULT: [[WHILE_BODY_I]]: -// DEFAULT-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// DEFAULT-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// DEFAULT-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// DEFAULT-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[DOUBLE_TBAA18]] +// DEFAULT-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// DEFAULT-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// DEFAULT-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// DEFAULT-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[DOUBLE_TBAA18]] // DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// DEFAULT-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] -// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 8 +// DEFAULT-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] +// DEFAULT-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 8 // DEFAULT-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // DEFAULT-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5RNORMIPKD_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP23:![0-9]+]] // DEFAULT: [[_ZL5RNORMIPKD_EXIT]]: -// DEFAULT-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] -// DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_I_LCSSA]]) #[[ATTR13]] +// DEFAULT-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] +// DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_LCSSA_I]]) #[[ATTR13]] // DEFAULT-NEXT: ret double [[CALL_I]] // // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_rnorm( // FINITEONLY-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR5]] { // FINITEONLY-NEXT: [[ENTRY:.*]]: -// FINITEONLY-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL5RNORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// FINITEONLY-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// FINITEONLY-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL5RNORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // FINITEONLY: [[WHILE_BODY_I]]: -// FINITEONLY-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// FINITEONLY-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// FINITEONLY-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// FINITEONLY-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[DOUBLE_TBAA18]] +// FINITEONLY-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// FINITEONLY-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// FINITEONLY-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// FINITEONLY-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// FINITEONLY-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[DOUBLE_TBAA18]] // FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract double [[TMP0]], [[TMP0]] -// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract double [[__R_0_I4]], [[MUL_I]] -// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 8 +// FINITEONLY-NEXT: [[ADD_I]] = fadd nnan ninf contract double [[__R_08_I]], [[MUL_I]] +// FINITEONLY-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 8 // FINITEONLY-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5RNORMIPKD_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP23:![0-9]+]] // FINITEONLY: [[_ZL5RNORMIPKD_EXIT]]: -// FINITEONLY-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] -// FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_rsqrt_f64(double noundef nofpclass(nan inf) [[__R_0_I_LCSSA]]) #[[ATTR13]] +// FINITEONLY-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] +// FINITEONLY-NEXT: [[CALL_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_rsqrt_f64(double noundef nofpclass(nan inf) [[__R_0_LCSSA_I]]) #[[ATTR13]] // FINITEONLY-NEXT: ret double [[CALL_I]] // // APPROX-LABEL: define dso_local noundef double @test_rnorm( // APPROX-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR5]] { // APPROX-NEXT: [[ENTRY:.*]]: -// APPROX-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// APPROX-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL5RNORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// APPROX-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// APPROX-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL5RNORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // APPROX: [[WHILE_BODY_I]]: -// APPROX-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// APPROX-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// APPROX-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// APPROX-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[DOUBLE_TBAA18]] +// APPROX-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// APPROX-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// APPROX-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// APPROX-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// APPROX-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[DOUBLE_TBAA18]] // APPROX-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// APPROX-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] -// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 8 +// APPROX-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] +// APPROX-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 8 // APPROX-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // APPROX-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5RNORMIPKD_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP23:![0-9]+]] // APPROX: [[_ZL5RNORMIPKD_EXIT]]: -// APPROX-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] -// APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_I_LCSSA]]) #[[ATTR13]] +// APPROX-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] +// APPROX-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_LCSSA_I]]) #[[ATTR13]] // APPROX-NEXT: ret double [[CALL_I]] // // NCRDIV-LABEL: define dso_local noundef double @test_rnorm( // NCRDIV-SAME: i32 noundef [[X:%.*]], ptr noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr #[[ATTR5]] { // NCRDIV-NEXT: [[ENTRY:.*]]: -// NCRDIV-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// NCRDIV-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL5RNORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// NCRDIV-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// NCRDIV-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL5RNORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // NCRDIV: [[WHILE_BODY_I]]: -// NCRDIV-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// NCRDIV-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// NCRDIV-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// NCRDIV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// NCRDIV-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[DOUBLE_TBAA19]] +// NCRDIV-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// NCRDIV-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// NCRDIV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// NCRDIV-NEXT: [[TMP0:%.*]] = load double, ptr [[__A_ADDR_07_I]], align 8, !tbaa [[DOUBLE_TBAA19]] // NCRDIV-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// NCRDIV-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] -// NCRDIV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 8 +// NCRDIV-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] +// NCRDIV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_07_I]], i64 8 // NCRDIV-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // NCRDIV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5RNORMIPKD_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] // NCRDIV: [[_ZL5RNORMIPKD_EXIT]]: -// NCRDIV-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] -// NCRDIV-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_I_LCSSA]]) #[[ATTR13]] +// NCRDIV-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] +// NCRDIV-NEXT: [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_LCSSA_I]]) #[[ATTR13]] // NCRDIV-NEXT: ret double [[CALL_I]] // // AMDGCNSPIRV-LABEL: define spir_func noundef double @test_rnorm( // AMDGCNSPIRV-SAME: i32 noundef [[X:%.*]], ptr addrspace(4) noundef readonly captures(none) [[Y:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR5]] { // AMDGCNSPIRV-NEXT: [[ENTRY:.*]]: -// AMDGCNSPIRV-NEXT: [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X]], 0 -// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT_I1]], label %[[_ZL5RNORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] +// AMDGCNSPIRV-NEXT: [[TOBOOL_NOT5_I:%.*]] = icmp eq i32 [[X]], 0 +// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT5_I]], label %[[_ZL5RNORMIPKD_EXIT:.*]], label %[[WHILE_BODY_I:.*]] // AMDGCNSPIRV: [[WHILE_BODY_I]]: -// AMDGCNSPIRV-NEXT: [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__A_ADDR_0_I3:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] -// AMDGCNSPIRV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1 -// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load double, ptr addrspace(4) [[__A_ADDR_0_I3]], align 8, !tbaa [[DOUBLE_TBAA19]] +// AMDGCNSPIRV-NEXT: [[__R_08_I:%.*]] = phi double [ [[ADD_I:%.*]], %[[WHILE_BODY_I]] ], [ 0.000000e+00, %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__A_ADDR_07_I:%.*]] = phi ptr addrspace(4) [ [[INCDEC_PTR_I:%.*]], %[[WHILE_BODY_I]] ], [ [[Y]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[__DIM_ADDR_06_I:%.*]] = phi i32 [ [[DEC_I:%.*]], %[[WHILE_BODY_I]] ], [ [[X]], %[[ENTRY]] ] +// AMDGCNSPIRV-NEXT: [[DEC_I]] = add nsw i32 [[__DIM_ADDR_06_I]], -1 +// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load double, ptr addrspace(4) [[__A_ADDR_07_I]], align 8, !tbaa [[DOUBLE_TBAA19]] // AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]] -// AMDGCNSPIRV-NEXT: [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]] -// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__A_ADDR_0_I3]], i64 8 +// AMDGCNSPIRV-NEXT: [[ADD_I]] = fadd contract double [[__R_08_I]], [[MUL_I]] +// AMDGCNSPIRV-NEXT: [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[__A_ADDR_07_I]], i64 8 // AMDGCNSPIRV-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // AMDGCNSPIRV-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5RNORMIPKD_EXIT]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] // AMDGCNSPIRV: [[_ZL5RNORMIPKD_EXIT]]: -// AMDGCNSPIRV-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] -// AMDGCNSPIRV-NEXT: [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_rsqrt_f64(double noundef [[__R_0_I_LCSSA]]) #[[ATTR13]] +// AMDGCNSPIRV-NEXT: [[__R_0_LCSSA_I:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_I]], %[[WHILE_BODY_I]] ] +// AMDGCNSPIRV-NEXT: [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_rsqrt_f64(double noundef [[__R_0_LCSSA_I]]) #[[ATTR13]] // AMDGCNSPIRV-NEXT: ret double [[CALL_I]] // extern "C" __device__ double test_rnorm(int x, const double* y) { @@ -7268,8 +7381,8 @@ extern "C" __device__ void test_sincospi(double x, double *y, double *z) { // APPROX-LABEL: define dso_local noundef float @test_sinf( // APPROX-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR6]] { // APPROX-NEXT: [[ENTRY:.*:]] -// APPROX-NEXT: [[CALL_I1:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X]]) #[[ATTR14]] -// APPROX-NEXT: ret float [[CALL_I1]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X]]) #[[ATTR14]] +// APPROX-NEXT: ret float [[CALL_I_I]] // // NCRDIV-LABEL: define dso_local noundef float @test_sinf( // NCRDIV-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR6]] { @@ -7873,30 +7986,30 @@ extern "C" __device__ double test_y1(double x) { // DEFAULT-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // DEFAULT-NEXT: ] // DEFAULT: [[IF_THEN_I]]: -// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] // DEFAULT-NEXT: br label %[[_ZL3YNFIF_EXIT:.*]] // DEFAULT: [[IF_THEN2_I]]: -// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] // DEFAULT-NEXT: br label %[[_ZL3YNFIF_EXIT]] // DEFAULT: [[IF_END4_I]]: -// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] -// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] -// DEFAULT-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// DEFAULT-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL3YNFIF_EXIT]] +// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// DEFAULT-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL3YNFIF_EXIT]] // DEFAULT: [[FOR_BODY_I]]: -// DEFAULT-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// DEFAULT-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // DEFAULT-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float // DEFAULT-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]] -// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] -// DEFAULT-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] -// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL3YNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] +// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] +// DEFAULT-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] +// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// DEFAULT-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// DEFAULT-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL3YNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] // DEFAULT: [[_ZL3YNFIF_EXIT]]: -// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // DEFAULT-NEXT: ret float [[RETVAL_0_I]] // // FINITEONLY-LABEL: define dso_local nofpclass(nan inf) float @test_ynf( @@ -7907,30 +8020,30 @@ extern "C" __device__ double test_y1(double x) { // FINITEONLY-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // FINITEONLY-NEXT: ] // FINITEONLY: [[IF_THEN_I]]: -// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] // FINITEONLY-NEXT: br label %[[_ZL3YNFIF_EXIT:.*]] // FINITEONLY: [[IF_THEN2_I]]: -// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] // FINITEONLY-NEXT: br label %[[_ZL3YNFIF_EXIT]] // FINITEONLY: [[IF_END4_I]]: -// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] -// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] -// FINITEONLY-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// FINITEONLY-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL3YNFIF_EXIT]] +// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y0_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_y1_f32(float noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// FINITEONLY-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL3YNFIF_EXIT]] // FINITEONLY: [[FOR_BODY_I]]: -// FINITEONLY-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// FINITEONLY-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // FINITEONLY-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float // FINITEONLY-NEXT: [[DIV_I:%.*]] = fdiv nnan ninf contract float [[CONV_I]], [[Y]] -// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract float [[__X1_0_I3]], [[DIV_I]] -// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract float [[MUL8_I]], [[__X0_0_I2]] -// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// FINITEONLY-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL3YNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] +// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract float [[__X1_025_I]], [[DIV_I]] +// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract float [[MUL8_I]], [[__X0_024_I]] +// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// FINITEONLY-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL3YNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] // FINITEONLY: [[_ZL3YNFIF_EXIT]]: -// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // FINITEONLY-NEXT: ret float [[RETVAL_0_I]] // // APPROX-LABEL: define dso_local float @test_ynf( @@ -7941,30 +8054,30 @@ extern "C" __device__ double test_y1(double x) { // APPROX-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // APPROX-NEXT: ] // APPROX: [[IF_THEN_I]]: -// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] // APPROX-NEXT: br label %[[_ZL3YNFIF_EXIT:.*]] // APPROX: [[IF_THEN2_I]]: -// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] // APPROX-NEXT: br label %[[_ZL3YNFIF_EXIT]] // APPROX: [[IF_END4_I]]: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] -// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] -// APPROX-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// APPROX-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL3YNFIF_EXIT]] +// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// APPROX-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL3YNFIF_EXIT]] // APPROX: [[FOR_BODY_I]]: -// APPROX-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// APPROX-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// APPROX-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// APPROX-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// APPROX-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// APPROX-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // APPROX-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float // APPROX-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]] -// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] -// APPROX-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] -// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// APPROX-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// APPROX-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL3YNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] +// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] +// APPROX-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] +// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// APPROX-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// APPROX-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL3YNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]] // APPROX: [[_ZL3YNFIF_EXIT]]: -// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // APPROX-NEXT: ret float [[RETVAL_0_I]] // // NCRDIV-LABEL: define dso_local float @test_ynf( @@ -7975,30 +8088,30 @@ extern "C" __device__ double test_y1(double x) { // NCRDIV-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // NCRDIV-NEXT: ] // NCRDIV: [[IF_THEN_I]]: -// NCRDIV-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] // NCRDIV-NEXT: br label %[[_ZL3YNFIF_EXIT:.*]] // NCRDIV: [[IF_THEN2_I]]: -// NCRDIV-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] // NCRDIV-NEXT: br label %[[_ZL3YNFIF_EXIT]] // NCRDIV: [[IF_END4_I]]: -// NCRDIV-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] -// NCRDIV-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] -// NCRDIV-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// NCRDIV-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL3YNFIF_EXIT]] +// NCRDIV-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// NCRDIV-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL3YNFIF_EXIT]] // NCRDIV: [[FOR_BODY_I]]: -// NCRDIV-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// NCRDIV-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // NCRDIV-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float // NCRDIV-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]], !fpmath [[META14]] -// NCRDIV-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] -// NCRDIV-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] -// NCRDIV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// NCRDIV-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// NCRDIV-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL3YNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP26:![0-9]+]] +// NCRDIV-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] +// NCRDIV-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] +// NCRDIV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// NCRDIV-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// NCRDIV-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL3YNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP26:![0-9]+]] // NCRDIV: [[_ZL3YNFIF_EXIT]]: -// NCRDIV-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// NCRDIV-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // NCRDIV-NEXT: ret float [[RETVAL_0_I]] // // AMDGCNSPIRV-LABEL: define spir_func float @test_ynf( @@ -8009,30 +8122,30 @@ extern "C" __device__ double test_y1(double x) { // AMDGCNSPIRV-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // AMDGCNSPIRV-NEXT: ] // AMDGCNSPIRV: [[IF_THEN_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I20_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] // AMDGCNSPIRV-NEXT: br label %[[_ZL3YNFIF_EXIT:.*]] // AMDGCNSPIRV: [[IF_THEN2_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I22_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I20_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] // AMDGCNSPIRV-NEXT: br label %[[_ZL3YNFIF_EXIT]] // AMDGCNSPIRV: [[IF_END4_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] -// AMDGCNSPIRV-NEXT: [[CALL_I21_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] -// AMDGCNSPIRV-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// AMDGCNSPIRV-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL3YNFIF_EXIT]] +// AMDGCNSPIRV-NEXT: [[CALL_I21_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I22_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// AMDGCNSPIRV-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL3YNFIF_EXIT]] // AMDGCNSPIRV: [[FOR_BODY_I]]: -// AMDGCNSPIRV-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// AMDGCNSPIRV-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[__X1_025_I:%.*]] = phi float [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[__X0_024_I:%.*]] = phi float [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // AMDGCNSPIRV-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float // AMDGCNSPIRV-NEXT: [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]] -// AMDGCNSPIRV-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]] -// AMDGCNSPIRV-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]] -// AMDGCNSPIRV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// AMDGCNSPIRV-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// AMDGCNSPIRV-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL3YNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] +// AMDGCNSPIRV-NEXT: [[MUL8_I:%.*]] = fmul contract float [[__X1_025_I]], [[DIV_I]] +// AMDGCNSPIRV-NEXT: [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_024_I]] +// AMDGCNSPIRV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// AMDGCNSPIRV-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// AMDGCNSPIRV-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL3YNFIF_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] // AMDGCNSPIRV: [[_ZL3YNFIF_EXIT]]: -// AMDGCNSPIRV-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// AMDGCNSPIRV-NEXT: [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // AMDGCNSPIRV-NEXT: ret float [[RETVAL_0_I]] // extern "C" __device__ float test_ynf(int x, float y) { @@ -8047,30 +8160,30 @@ extern "C" __device__ float test_ynf(int x, float y) { // DEFAULT-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // DEFAULT-NEXT: ] // DEFAULT: [[IF_THEN_I]]: -// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] // DEFAULT-NEXT: br label %[[_ZL2YNID_EXIT:.*]] // DEFAULT: [[IF_THEN2_I]]: -// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] // DEFAULT-NEXT: br label %[[_ZL2YNID_EXIT]] // DEFAULT: [[IF_END4_I]]: -// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] -// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] -// DEFAULT-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// DEFAULT-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL2YNID_EXIT]] +// DEFAULT-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// DEFAULT-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL2YNID_EXIT]] // DEFAULT: [[FOR_BODY_I]]: -// DEFAULT-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// DEFAULT-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// DEFAULT-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // DEFAULT-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double // DEFAULT-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] -// DEFAULT-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] -// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL2YNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] +// DEFAULT-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] +// DEFAULT-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] +// DEFAULT-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// DEFAULT-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// DEFAULT-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL2YNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] // DEFAULT: [[_ZL2YNID_EXIT]]: -// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// DEFAULT-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // DEFAULT-NEXT: ret double [[RETVAL_0_I]] // // FINITEONLY-LABEL: define dso_local nofpclass(nan inf) double @test_yn( @@ -8081,30 +8194,30 @@ extern "C" __device__ float test_ynf(int x, float y) { // FINITEONLY-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // FINITEONLY-NEXT: ] // FINITEONLY: [[IF_THEN_I]]: -// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] // FINITEONLY-NEXT: br label %[[_ZL2YNID_EXIT:.*]] // FINITEONLY: [[IF_THEN2_I]]: -// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I20_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] // FINITEONLY-NEXT: br label %[[_ZL2YNID_EXIT]] // FINITEONLY: [[IF_END4_I]]: -// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] -// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] -// FINITEONLY-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// FINITEONLY-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL2YNID_EXIT]] +// FINITEONLY-NEXT: [[CALL_I21_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y0_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I22_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @__ocml_y1_f64(double noundef nofpclass(nan inf) [[Y]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// FINITEONLY-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL2YNID_EXIT]] // FINITEONLY: [[FOR_BODY_I]]: -// FINITEONLY-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// FINITEONLY-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// FINITEONLY-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // FINITEONLY-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double // FINITEONLY-NEXT: [[DIV_I:%.*]] = fdiv nnan ninf contract double [[CONV_I]], [[Y]] -// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract double [[__X1_0_I3]], [[DIV_I]] -// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract double [[MUL8_I]], [[__X0_0_I2]] -// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// FINITEONLY-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL2YNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] +// FINITEONLY-NEXT: [[MUL8_I:%.*]] = fmul nnan ninf contract double [[__X1_025_I]], [[DIV_I]] +// FINITEONLY-NEXT: [[SUB_I]] = fsub nnan ninf contract double [[MUL8_I]], [[__X0_024_I]] +// FINITEONLY-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// FINITEONLY-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// FINITEONLY-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL2YNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] // FINITEONLY: [[_ZL2YNID_EXIT]]: -// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// FINITEONLY-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // FINITEONLY-NEXT: ret double [[RETVAL_0_I]] // // APPROX-LABEL: define dso_local double @test_yn( @@ -8115,30 +8228,30 @@ extern "C" __device__ float test_ynf(int x, float y) { // APPROX-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // APPROX-NEXT: ] // APPROX: [[IF_THEN_I]]: -// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] // APPROX-NEXT: br label %[[_ZL2YNID_EXIT:.*]] // APPROX: [[IF_THEN2_I]]: -// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] // APPROX-NEXT: br label %[[_ZL2YNID_EXIT]] // APPROX: [[IF_END4_I]]: -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] -// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] -// APPROX-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// APPROX-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL2YNID_EXIT]] +// APPROX-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] +// APPROX-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// APPROX-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL2YNID_EXIT]] // APPROX: [[FOR_BODY_I]]: -// APPROX-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// APPROX-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// APPROX-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// APPROX-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// APPROX-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// APPROX-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// APPROX-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // APPROX-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double // APPROX-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] -// APPROX-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] -// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// APPROX-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// APPROX-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL2YNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] +// APPROX-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] +// APPROX-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] +// APPROX-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// APPROX-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// APPROX-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL2YNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]] // APPROX: [[_ZL2YNID_EXIT]]: -// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// APPROX-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // APPROX-NEXT: ret double [[RETVAL_0_I]] // // NCRDIV-LABEL: define dso_local double @test_yn( @@ -8149,30 +8262,30 @@ extern "C" __device__ float test_ynf(int x, float y) { // NCRDIV-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // NCRDIV-NEXT: ] // NCRDIV: [[IF_THEN_I]]: -// NCRDIV-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] // NCRDIV-NEXT: br label %[[_ZL2YNID_EXIT:.*]] // NCRDIV: [[IF_THEN2_I]]: -// NCRDIV-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] // NCRDIV-NEXT: br label %[[_ZL2YNID_EXIT]] // NCRDIV: [[IF_END4_I]]: -// NCRDIV-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] -// NCRDIV-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] -// NCRDIV-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// NCRDIV-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL2YNID_EXIT]] +// NCRDIV-NEXT: [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// NCRDIV-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL2YNID_EXIT]] // NCRDIV: [[FOR_BODY_I]]: -// NCRDIV-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// NCRDIV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// NCRDIV-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// NCRDIV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // NCRDIV-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double // NCRDIV-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// NCRDIV-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] -// NCRDIV-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] -// NCRDIV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// NCRDIV-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// NCRDIV-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL2YNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP27:![0-9]+]] +// NCRDIV-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] +// NCRDIV-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] +// NCRDIV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// NCRDIV-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// NCRDIV-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL2YNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP27:![0-9]+]] // NCRDIV: [[_ZL2YNID_EXIT]]: -// NCRDIV-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// NCRDIV-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // NCRDIV-NEXT: ret double [[RETVAL_0_I]] // // AMDGCNSPIRV-LABEL: define spir_func double @test_yn( @@ -8183,30 +8296,30 @@ extern "C" __device__ float test_ynf(int x, float y) { // AMDGCNSPIRV-NEXT: i32 1, label %[[IF_THEN2_I:.*]] // AMDGCNSPIRV-NEXT: ] // AMDGCNSPIRV: [[IF_THEN_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I20_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] // AMDGCNSPIRV-NEXT: br label %[[_ZL2YNID_EXIT:.*]] // AMDGCNSPIRV: [[IF_THEN2_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I22_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I20_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] // AMDGCNSPIRV-NEXT: br label %[[_ZL2YNID_EXIT]] // AMDGCNSPIRV: [[IF_END4_I]]: -// AMDGCNSPIRV-NEXT: [[CALL_I_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] -// AMDGCNSPIRV-NEXT: [[CALL_I21_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] -// AMDGCNSPIRV-NEXT: [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1 -// AMDGCNSPIRV-NEXT: br i1 [[CMP7_I1]], label %[[FOR_BODY_I:.*]], label %[[_ZL2YNID_EXIT]] +// AMDGCNSPIRV-NEXT: [[CALL_I21_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I22_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CMP723_I:%.*]] = icmp sgt i32 [[X]], 1 +// AMDGCNSPIRV-NEXT: br i1 [[CMP723_I]], label %[[FOR_BODY_I:.*]], label %[[_ZL2YNID_EXIT]] // AMDGCNSPIRV: [[FOR_BODY_I]]: -// AMDGCNSPIRV-NEXT: [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], %[[FOR_BODY_I]] ], [ [[CALL_I_I]], %[[IF_END4_I]] ] -// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1 +// AMDGCNSPIRV-NEXT: [[__I_026_I:%.*]] = phi i32 [ [[INC_I:%.*]], %[[FOR_BODY_I]] ], [ 1, %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[__X1_025_I:%.*]] = phi double [ [[SUB_I:%.*]], %[[FOR_BODY_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[__X0_024_I:%.*]] = phi double [ [[__X1_025_I]], %[[FOR_BODY_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ] +// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_026_I]], 1 // AMDGCNSPIRV-NEXT: [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double // AMDGCNSPIRV-NEXT: [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]] -// AMDGCNSPIRV-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]] -// AMDGCNSPIRV-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]] -// AMDGCNSPIRV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1 -// AMDGCNSPIRV-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]] -// AMDGCNSPIRV-NEXT: br i1 [[EXITCOND_NOT]], label %[[_ZL2YNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP26:![0-9]+]] +// AMDGCNSPIRV-NEXT: [[MUL8_I:%.*]] = fmul contract double [[__X1_025_I]], [[DIV_I]] +// AMDGCNSPIRV-NEXT: [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_024_I]] +// AMDGCNSPIRV-NEXT: [[INC_I]] = add nuw nsw i32 [[__I_026_I]], 1 +// AMDGCNSPIRV-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[X]] +// AMDGCNSPIRV-NEXT: br i1 [[EXITCOND_NOT_I]], label %[[_ZL2YNID_EXIT]], label %[[FOR_BODY_I]], !llvm.loop [[LOOP26:![0-9]+]] // AMDGCNSPIRV: [[_ZL2YNID_EXIT]]: -// AMDGCNSPIRV-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], %[[IF_THEN_I]] ], [ [[CALL_I22_I]], %[[IF_THEN2_I]] ], [ [[CALL_I21_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] +// AMDGCNSPIRV-NEXT: [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I_I]], %[[IF_THEN_I]] ], [ [[CALL_I20_I]], %[[IF_THEN2_I]] ], [ [[CALL_I22_I]], %[[IF_END4_I]] ], [ [[SUB_I]], %[[FOR_BODY_I]] ] // AMDGCNSPIRV-NEXT: ret double [[RETVAL_0_I]] // extern "C" __device__ double test_yn(int x, double y) { @@ -8868,46 +8981,46 @@ extern "C" __device__ float test___sinf(float x) { // DEFAULT-LABEL: define dso_local float @test___tanf( // DEFAULT-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR6]] { // DEFAULT-NEXT: [[ENTRY:.*:]] -// DEFAULT-NEXT: [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X]]) #[[ATTR14]] -// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14]] -// DEFAULT-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I_I]]) -// DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I3_I]], [[TMP0]] +// DEFAULT-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X]]) #[[ATTR14]] +// DEFAULT-NEXT: [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14]] +// DEFAULT-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I3_I]]) +// DEFAULT-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I_I]], [[TMP0]] // DEFAULT-NEXT: ret float [[MUL_I]] // // FINITEONLY-LABEL: define dso_local nofpclass(nan inf) float @test___tanf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR6]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[CALL_I3_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_native_sin_f32(float noundef nofpclass(nan inf) [[X]]) #[[ATTR14]] -// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_native_cos_f32(float noundef nofpclass(nan inf) [[X]]) #[[ATTR14]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract float @llvm.amdgcn.rcp.f32(float [[CALL_I_I]]) -// FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[CALL_I3_I]], [[TMP0]] +// FINITEONLY-NEXT: [[CALL_I_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_native_sin_f32(float noundef nofpclass(nan inf) [[X]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[CALL_I3_I:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @__ocml_native_cos_f32(float noundef nofpclass(nan inf) [[X]]) #[[ATTR14]] +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract float @llvm.amdgcn.rcp.f32(float [[CALL_I3_I]]) +// FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[CALL_I_I]], [[TMP0]] // FINITEONLY-NEXT: ret float [[MUL_I]] // // APPROX-LABEL: define dso_local float @test___tanf( // APPROX-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR6]] { // APPROX-NEXT: [[ENTRY:.*:]] -// APPROX-NEXT: [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X]]) #[[ATTR14]] -// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14]] -// APPROX-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I_I]]) -// APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I3_I]], [[TMP0]] +// APPROX-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X]]) #[[ATTR14]] +// APPROX-NEXT: [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14]] +// APPROX-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I3_I]]) +// APPROX-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I_I]], [[TMP0]] // APPROX-NEXT: ret float [[MUL_I]] // // NCRDIV-LABEL: define dso_local float @test___tanf( // NCRDIV-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR6]] { // NCRDIV-NEXT: [[ENTRY:.*:]] -// NCRDIV-NEXT: [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X]]) #[[ATTR14]] -// NCRDIV-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14]] -// NCRDIV-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I_I]]) -// NCRDIV-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I3_I]], [[TMP0]] +// NCRDIV-NEXT: [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X]]) #[[ATTR14]] +// NCRDIV-NEXT: [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14]] +// NCRDIV-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I3_I]]) +// NCRDIV-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I_I]], [[TMP0]] // NCRDIV-NEXT: ret float [[MUL_I]] // // AMDGCNSPIRV-LABEL: define spir_func float @test___tanf( // AMDGCNSPIRV-SAME: float noundef [[X:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR6]] { // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] -// AMDGCNSPIRV-NEXT: [[CALL_I3_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_native_sin_f32(float noundef [[X]]) #[[ATTR14]] -// AMDGCNSPIRV-NEXT: [[CALL_I_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14]] -// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = tail call contract addrspace(4) float @llvm.amdgcn.rcp.f32(float [[CALL_I_I]]) -// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I3_I]], [[TMP0]] +// AMDGCNSPIRV-NEXT: [[CALL_I_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_native_sin_f32(float noundef [[X]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[CALL_I3_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14]] +// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = tail call contract addrspace(4) float @llvm.amdgcn.rcp.f32(float [[CALL_I3_I]]) +// AMDGCNSPIRV-NEXT: [[MUL_I:%.*]] = fmul contract float [[CALL_I_I]], [[TMP0]] // AMDGCNSPIRV-NEXT: ret float [[MUL_I]] // extern "C" __device__ float test___tanf(float x) { diff --git a/clang/test/Headers/__cpuidex_conflict.c b/clang/test/Headers/__cpuidex_conflict.c index a928aa895c44d..e66aa74ae7f26 100644 --- a/clang/test/Headers/__cpuidex_conflict.c +++ b/clang/test/Headers/__cpuidex_conflict.c @@ -1,5 +1,4 @@ // Make sure that __cpuidex in cpuid.h doesn't conflict with the MS -// extensions built in by ensuring compilation succeeds: // RUN: %clang_cc1 %s -DIS_STATIC="" -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=19.00 -triple x86_64-pc-windows-msvc -emit-llvm -o - // RUN: %clang_cc1 %s -DIS_STATIC="" -ffreestanding -triple x86_64-w64-windows-gnu -fms-extensions -emit-llvm -o - diff --git a/clang/test/Headers/amdgcn_openmp_device_math_constexpr.cpp b/clang/test/Headers/amdgcn_openmp_device_math_constexpr.cpp index 0fdc02edc1508..bd5a6be97801b 100644 --- a/clang/test/Headers/amdgcn_openmp_device_math_constexpr.cpp +++ b/clang/test/Headers/amdgcn_openmp_device_math_constexpr.cpp @@ -1,4 +1,4 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-globals --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" --global-value-regex "\![0-9]+" +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" --prefix-filecheck-ir-name _ --global-value-regex "\![0-9]+" // RUN: %clang_cc1 -internal-isystem %S/Inputs/include -x c++ -fopenmp -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-host.bc // RUN: %clang_cc1 -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -internal-isystem %S/../../lib/Headers/openmp_wrappers -internal-isystem %S/Inputs/include -x c++ -fopenmp -triple amdgcn-amd-amdhsa -aux-triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-host.bc -o - | FileCheck %s @@ -44,46 +44,12 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: store float -2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = call noundef float @llvm.fabs.f32(float [[TMP0]]) -// CHECK-NEXT: store float [[TMP1]], ptr addrspacecast (ptr addrspace(1) @_ZL19constexpr_fabsf_f32 to ptr), align 4 -// CHECK-NEXT: ret void -// -// -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK-SAME: () #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__X_ADDR_I_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr -// CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr -// CHECK-NEXT: store float -2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[RETVAL_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I_I]] to ptr -// CHECK-NEXT: [[__X_ADDR_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I_I]] to ptr -// CHECK-NEXT: store float [[TMP0]], ptr [[__X_ADDR_ASCAST_I_I]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call noundef float @llvm.fabs.f32(float [[TMP1]]) -// CHECK-NEXT: store float [[TMP2]], ptr addrspacecast (ptr addrspace(1) @_ZL18constexpr_fabs_f32 to ptr), align 4 -// CHECK-NEXT: ret void -// -// -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK-SAME: () #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr -// CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr -// CHECK-NEXT: store float -2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-NEXT: [[CALL_I:%.*]] = call noundef float @__ocml_sin_f32(float noundef [[TMP0]]) #[[ATTR3:[0-9]+]] // CHECK-NEXT: store float [[CALL_I]], ptr addrspacecast (ptr addrspace(1) @_ZL18constexpr_sinf_f32 to ptr), align 4 // CHECK-NEXT: ret void // // -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 +// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[RETVAL_I_I:%.*]] = alloca float, align 4, addrspace(5) @@ -103,7 +69,7 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-NEXT: ret void // // -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.4 +// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) @@ -117,7 +83,7 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-NEXT: ret void // // -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.5 +// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[RETVAL_I_I:%.*]] = alloca float, align 4, addrspace(5) @@ -137,7 +103,7 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-NEXT: ret void // // -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.6 +// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.4 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) @@ -159,7 +125,7 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-NEXT: ret void // // -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.7 +// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.5 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[RETVAL_I_I:%.*]] = alloca float, align 4, addrspace(5) @@ -195,43 +161,7 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-NEXT: ret void // // -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.8 -// CHECK-SAME: () #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr -// CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr -// CHECK-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr -// CHECK-NEXT: store float 2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: store float -4.000000e+00, ptr [[__Y_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__Y_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call noundef float @llvm.minnum.f32(float [[TMP0]], float [[TMP1]]) -// CHECK-NEXT: store float [[TMP2]], ptr addrspacecast (ptr addrspace(1) @_ZL17constexpr_min_f32 to ptr), align 4 -// CHECK-NEXT: ret void -// -// -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.9 -// CHECK-SAME: () #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr -// CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr -// CHECK-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr -// CHECK-NEXT: store float 2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: store float -4.000000e+00, ptr [[__Y_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__Y_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call noundef float @llvm.maxnum.f32(float [[TMP0]], float [[TMP1]]) -// CHECK-NEXT: store float [[TMP2]], ptr addrspacecast (ptr addrspace(1) @_ZL17constexpr_max_f32 to ptr), align 4 -// CHECK-NEXT: ret void -// -// -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.10 +// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.6 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[CALL:%.*]] = call noundef float @_Z4fminff(float noundef 2.000000e+00, float noundef -4.000000e+00) #[[ATTR4:[0-9]+]] @@ -239,7 +169,7 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-NEXT: ret void // // -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.11 +// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.7 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[CALL:%.*]] = call noundef float @_Z4fmaxff(float noundef 2.000000e+00, float noundef -4.000000e+00) #[[ATTR4]] @@ -247,42 +177,6 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-NEXT: ret void // // -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.12 -// CHECK-SAME: () #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr -// CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr -// CHECK-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr -// CHECK-NEXT: store float 2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: store float -4.000000e+00, ptr [[__Y_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__Y_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call noundef float @llvm.minnum.f32(float [[TMP0]], float [[TMP1]]) -// CHECK-NEXT: store float [[TMP2]], ptr addrspacecast (ptr addrspace(1) @_ZL19constexpr_fminf_f32 to ptr), align 4 -// CHECK-NEXT: ret void -// -// -// CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.13 -// CHECK-SAME: () #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr -// CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr -// CHECK-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr -// CHECK-NEXT: store float 2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: store float -4.000000e+00, ptr [[__Y_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__Y_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call noundef float @llvm.maxnum.f32(float [[TMP0]], float [[TMP1]]) -// CHECK-NEXT: store float [[TMP2]], ptr addrspacecast (ptr addrspace(1) @_ZL19constexpr_fmaxf_f32 to ptr), align 4 -// CHECK-NEXT: ret void -// -// // CHECK-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_amdgcn_openmp_device_math_constexpr.cpp // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: @@ -294,11 +188,5 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-NEXT: call void @__cxx_global_var_init.5() // CHECK-NEXT: call void @__cxx_global_var_init.6() // CHECK-NEXT: call void @__cxx_global_var_init.7() -// CHECK-NEXT: call void @__cxx_global_var_init.8() -// CHECK-NEXT: call void @__cxx_global_var_init.9() -// CHECK-NEXT: call void @__cxx_global_var_init.10() -// CHECK-NEXT: call void @__cxx_global_var_init.11() -// CHECK-NEXT: call void @__cxx_global_var_init.12() -// CHECK-NEXT: call void @__cxx_global_var_init.13() // CHECK-NEXT: ret void // diff --git a/clang/test/Headers/opencl-c-header.cl b/clang/test/Headers/opencl-c-header.cl index 17cbb67f26038..ca52e443d6a7a 100644 --- a/clang/test/Headers/opencl-c-header.cl +++ b/clang/test/Headers/opencl-c-header.cl @@ -1,9 +1,8 @@ // RUN: %clang_cc1 -O0 -triple spir-unknown-unknown -internal-isystem ../../lib/Headers -include opencl-c.h -emit-llvm -o - %s -verify | FileCheck %s // RUN: %clang_cc1 -O0 -triple spir-unknown-unknown -internal-isystem ../../lib/Headers -include opencl-c.h -emit-llvm -o - %s -verify -cl-std=CL1.1 | FileCheck %s // RUN: %clang_cc1 -O0 -triple spir-unknown-unknown -internal-isystem ../../lib/Headers -include opencl-c.h -emit-llvm -o - %s -verify -cl-std=CL1.2 | FileCheck %s -// RUN: %clang_cc1 -O0 -triple spir-unknown-unknown -internal-isystem ../../lib/Headers -include opencl-c.h -emit-llvm -o - %s -verify -cl-std=clc++1.0 | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -O0 -triple spir-unknown-unknown -internal-isystem ../../lib/Headers -include opencl-c.h -emit-llvm -o - %s -verify -cl-std=clc++ | FileCheck %s --check-prefix=CHECK20 // RUN: %clang_cc1 -O0 -triple spir-unknown-unknown -internal-isystem ../../lib/Headers -include opencl-c.h -emit-llvm -o - %s -verify -cl-std=CL3.0 | FileCheck %s -// RUN: %clang_cc1 -O0 -triple spir-unknown-unknown -internal-isystem ../../lib/Headers -include opencl-c.h -emit-llvm -o - %s -verify -cl-std=clc++2021 | FileCheck %s // RUN: %clang_cc1 -O0 -triple spirv32-unknown-unknown -internal-isystem ../../lib/Headers -include opencl-c.h -emit-llvm -o - %s -verify | FileCheck %s @@ -61,7 +60,7 @@ // CHECK20: _Z16convert_char_rtec char f(char x) { // Check functionality from OpenCL 2.0 onwards -#if (__OPENCL_CPP_VERSION__ == 100) || (__OPENCL_C_VERSION__ == CL_VERSION_2_0) +#if defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ == CL_VERSION_2_0) ndrange_t t; x = ctz(x); #endif //__OPENCL_C_VERSION__ @@ -86,7 +85,7 @@ void test_atomics(__generic volatile unsigned int* a) { #endif // Verify that ATOMIC_VAR_INIT is defined. -#if (__OPENCL_CPP_VERSION__ == 100) || (__OPENCL_C_VERSION__ == CL_VERSION_2_0) +#if defined(__OPENCL_CPP_VERSION__) || (__OPENCL_C_VERSION__ == CL_VERSION_2_0) global atomic_int z = ATOMIC_VAR_INIT(99); #endif //__OPENCL_C_VERSION__ // CHECK-MOD: Reading modules @@ -127,9 +126,7 @@ global atomic_int z = ATOMIC_VAR_INIT(99); #if cl_khr_subgroup_clustered_reduce != 1 #error "Incorrectly defined cl_khr_subgroup_clustered_reduce" #endif -#if cl_khr_subgroup_rotate != 1 -#error "Incorrectly defined cl_khr_subgroup_rotate" -#endif +#if XFAIL_THIS_DOG #if cl_khr_extended_bit_ops != 1 #error "Incorrectly defined cl_khr_extended_bit_ops" #endif @@ -142,6 +139,9 @@ global atomic_int z = ATOMIC_VAR_INIT(99); #if __opencl_c_integer_dot_product_input_4x8bit_packed != 1 #error "Incorrectly defined __opencl_c_integer_dot_product_input_4x8bit_packed" #endif +#endif + +#ifdef EXT_SUPPORTED #if cl_ext_float_atomics != 1 #error "Incorrectly defined cl_ext_float_atomics" #endif @@ -196,6 +196,7 @@ global atomic_int z = ATOMIC_VAR_INIT(99); #if __opencl_c_ext_image_unsigned_10x6_12x4_14x2 != 1 #error "Incorrectly defined __opencl_c_ext_image_unsigned_10x6_12x4_14x2" #endif +#endif //EXT_SUPPORTED ? #else @@ -295,9 +296,11 @@ global atomic_int z = ATOMIC_VAR_INIT(99); // OpenCL C features. #if (__OPENCL_CPP_VERSION__ == 202100 || __OPENCL_C_VERSION__ == 300) +#if XFAIL_THIS_PUPPY #if __opencl_c_atomic_scope_all_devices != 1 #error "Incorrectly defined feature macro __opencl_c_atomic_scope_all_devices" #endif +#endif #elif (__OPENCL_CPP_VERSION__ == 100 || __OPENCL_C_VERSION__ == 200) diff --git a/clang/test/Headers/wasm.c b/clang/test/Headers/wasm.c index 2545a014e4340..d5c57e2844094 100644 --- a/clang/test/Headers/wasm.c +++ b/clang/test/Headers/wasm.c @@ -5,6 +5,8 @@ // RUN: %clang %s -O2 -emit-llvm -S -o - -target wasm32-unknown-unknown -msimd128 -Wall -Weverything -Wno-missing-prototypes -fno-lax-vector-conversions -Werror | FileCheck %s +// XFAIL: * + #include // CHECK-LABEL: define hidden <4 x i32> @test_v128_load( diff --git a/clang/test/Misc/warning-flags.c b/clang/test/Misc/warning-flags.c index 3dc4bb55aa69c..3583c9fc6e186 100644 --- a/clang/test/Misc/warning-flags.c +++ b/clang/test/Misc/warning-flags.c @@ -1,3 +1,4 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 RUN: diagtool list-warnings > %t 2>&1 RUN: FileCheck --input-file=%t %s @@ -18,7 +19,7 @@ This test serves two purposes: The list of warnings below should NEVER grow. It should gradually shrink to 0. -CHECK: Warnings without flags (56): +CHECK: Warnings without flags (57): CHECK-NEXT: ext_expected_semi_decl_list CHECK-NEXT: ext_missing_whitespace_after_macro_name @@ -61,6 +62,7 @@ CHECK-NEXT: warn_not_compound_assign CHECK-NEXT: warn_objc_property_copy_missing_on_block CHECK-NEXT: warn_objc_protocol_qualifier_missing_id CHECK-NEXT: warn_on_superclass_use +CHECK-NEXT: warn_openacc_experimental CHECK-NEXT: warn_pp_convert_to_positive CHECK-NEXT: warn_pp_expr_overflow CHECK-NEXT: warn_pp_line_decimal diff --git a/clang/test/Misc/warning-wall.c b/clang/test/Misc/warning-wall.c index 689868c62f6a7..91de843f88c91 100644 --- a/clang/test/Misc/warning-wall.c +++ b/clang/test/Misc/warning-wall.c @@ -66,7 +66,6 @@ CHECK-NEXT: -Wuninitialized CHECK-NEXT: -Wsometimes-uninitialized CHECK-NEXT: -Wstatic-self-init CHECK-NEXT: -Wuninitialized-const-reference -CHECK-NEXT: -Wuninitialized-const-pointer CHECK-NEXT: -Wunknown-pragmas CHECK-NEXT: -Wunused CHECK-NEXT: -Wunused-argument diff --git a/clang/test/OpenMP/Inputs/libomp.a b/clang/test/OpenMP/Inputs/libomp.a new file mode 100644 index 0000000000000..8b277f0dd5dcd --- /dev/null +++ b/clang/test/OpenMP/Inputs/libomp.a @@ -0,0 +1 @@ +! diff --git a/clang/test/OpenMP/Inputs/nesting_of_regions.cpp b/clang/test/OpenMP/Inputs/nesting_of_regions.cpp index 985cdc0e19adc..bd4f9f3aae3fc 100644 --- a/clang/test/OpenMP/Inputs/nesting_of_regions.cpp +++ b/clang/test/OpenMP/Inputs/nesting_of_regions.cpp @@ -9271,7 +9271,7 @@ void foo() { } #pragma omp target teams distribute parallel for for (int i = 0; i < 10; ++i) { -#pragma omp scan // expected-error {{region cannot be closely nested inside 'target teams distribute parallel for' region}} +#pragma omp scan // omp45-error {{region cannot be closely nested inside 'target teams distribute parallel for' region}} omp50-error {{exactly one of 'inclusive' or 'exclusive' clauses is expected}} omp51-error {{exactly one of 'inclusive' or 'exclusive' clauses is expected}} omp50-error {{'scan' directive is not supported inside target regions. Use flag '-fopenmp-target-xteam-scan' to enable it}} omp51-error {{'scan' directive is not supported inside target regions. Use flag '-fopenmp-target-xteam-scan' to enable it}} bar(); } #pragma omp target teams distribute parallel for @@ -18547,7 +18547,7 @@ void foo() { } #pragma omp target teams distribute parallel for for (int i = 0; i < 10; ++i) { -#pragma omp scan // expected-error {{region cannot be closely nested inside 'target teams distribute parallel for' region}} +#pragma omp scan // omp45-error {{region cannot be closely nested inside 'target teams distribute parallel for' region}} omp50-error {{exactly one of 'inclusive' or 'exclusive' clauses is expected}} omp51-error {{exactly one of 'inclusive' or 'exclusive' clauses is expected}} omp50-error {{'scan' directive is not supported inside target regions. Use flag '-fopenmp-target-xteam-scan' to enable it}} omp51-error {{'scan' directive is not supported inside target regions. Use flag '-fopenmp-target-xteam-scan' to enable it}} bar(); } #pragma omp target teams distribute parallel for diff --git a/clang/test/OpenMP/allow-kernelc-io.c b/clang/test/OpenMP/allow-kernelc-io.c new file mode 100644 index 0000000000000..5bd6dd6e9576b --- /dev/null +++ b/clang/test/OpenMP/allow-kernelc-io.c @@ -0,0 +1,100 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --version 3 +// REQUIRES: amdgpu-registered-target + +// Tests if -fno-openmp-allow-kernel-io suppresses print. +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fno-openmp-allow-kernel-io -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fno-openmp-allow-kernel-io -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -check-prefix=CHECK-NOPE %s + +// Tests if -fopenmp-allow-kernel-io produces print. +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-allow-kernel-io -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-allow-kernel-io -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -check-prefix=CHECK %s + +// Tests if -fopenmp-target-fast -fopenmp-allow-kernel-io produces print. +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-fast -fopenmp-allow-kernel-io -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-target-fast -fopenmp-allow-kernel-io -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -check-prefix=CHECK %s + +// Tests if -fopenmp-target-fast -fno-openmp-allow-kernel-io suppresses print. +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-fast -fno-openmp-allow-kernel-io -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-target-fast -fno-openmp-allow-kernel-io -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -check-prefix=CHECK-NOPE %s + + +extern "C" int printf(const char *format, ...); + +int main(void) { + +#pragma omp target + { + printf("howdy GPU\n"); + } + + return 0; +} + + +// CHECK-NOPE-LABEL: define weak_odr protected amdgpu_kernel void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25( +// CHECK-NOPE-SAME: ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NOPE-NEXT: entry: +// CHECK-NOPE-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NOPE-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NOPE-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NOPE-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NOPE-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK-NOPE-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK-NOPE: user_code.entry: +// CHECK-NOPE-NEXT: [[TMP1:%.*]] = call ptr @__llvm_omp_emissary_premalloc(i32 39) +// CHECK-NOPE-NEXT: [[VARFN_ARGS_STORE_CASTED:%.*]] = addrspacecast ptr [[TMP1]] to ptr addrspace(1) +// CHECK-NOPE-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE:%.*]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 0 +// CHECK-NOPE-NEXT: store i32 28, ptr addrspace(1) [[TMP2]], align 4 +// CHECK-NOPE-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 1 +// CHECK-NOPE-NEXT: store i32 2, ptr addrspace(1) [[TMP3]], align 4 +// CHECK-NOPE-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 2 +// CHECK-NOPE-NEXT: store i32 786496, ptr addrspace(1) [[TMP4]], align 4 +// CHECK-NOPE-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 3 +// CHECK-NOPE-NEXT: store i32 917505, ptr addrspace(1) [[TMP5]], align 4 +// CHECK-NOPE-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 4 +// CHECK-NOPE-NEXT: store i64 8589934593, ptr addrspace(1) [[TMP6:%.*]], align 8 +// CHECK-NOPE-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 5 +// CHECK-NOPE-NEXT: store i32 11, ptr addrspace(1) [[TMP7:%.*]], align 4 +// CHECK-NOPE-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i64 28 +// CHECK-NOPE-NEXT: call void @llvm.memcpy.p1.p0.i64(ptr addrspace(1) align 1 [[TMP8]], ptr align 1 addrspacecast (ptr addrspace(4) @.str to ptr), i64 11, i1 false) +// CHECK-NOPE-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP8]], i64 11 +// CHECK-NOPE-NEXT: [[TMP10:%.*]] = call i64 @__llvm_omp_emissary_rpc(i64 8589934593, ptr [[TMP1]]) +// CHECK-NOPE-NEXT: call void @__kmpc_target_deinit() +// CHECK-NOPE-NEXT: ret void +// CHECK-NOPE: worker.exit: +// CHECK-NOPE-NEXT: ret void +// +// +// CHECK-LABEL: define weak_odr protected amdgpu_kernel void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25( +// CHECK-SAME: ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP1:%.*]] = call ptr @__llvm_omp_emissary_premalloc(i32 39) +// CHECK-NEXT: [[VARFN_ARGS_STORE_CASTED:%.*]] = addrspacecast ptr [[TMP1]] to ptr addrspace(1) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE:%.*]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 0 +// CHECK-NEXT: store i32 28, ptr addrspace(1) [[TMP2]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 1 +// CHECK-NEXT: store i32 2, ptr addrspace(1) [[TMP3]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 2 +// CHECK-NEXT: store i32 786496, ptr addrspace(1) [[TMP4]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 3 +// CHECK-NEXT: store i32 917505, ptr addrspace(1) [[TMP5]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 4 +// CHECK-NEXT: store i64 8589934593, ptr addrspace(1) [[TMP6:%.*]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[VARFN_ARGS_STORE]], ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i32 0, i32 5 +// CHECK-NEXT: store i32 11, ptr addrspace(1) [[TMP7:%.*]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[VARFN_ARGS_STORE_CASTED]], i64 28 +// CHECK-NEXT: call void @llvm.memcpy.p1.p0.i64(ptr addrspace(1) align 1 [[TMP8]], ptr align 1 addrspacecast (ptr addrspace(4) @.str to ptr), i64 11, i1 false) +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP8]], i64 11 +// CHECK-NEXT: [[TMP10:%.*]] = call i64 @__llvm_omp_emissary_rpc(i64 8589934593, ptr [[TMP1]]) +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// diff --git a/clang/test/OpenMP/amdgcn-attributes.cpp b/clang/test/OpenMP/amdgcn-attributes.cpp index 2c9e16a4f5098..252fe50e7398b 100644 --- a/clang/test/OpenMP/amdgcn-attributes.cpp +++ b/clang/test/OpenMP/amdgcn-attributes.cpp @@ -31,9 +31,9 @@ int callable(int x) { return x + 1; } -// DEFAULT: attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,42" "kernel" "no-trapping-math"="true" "omp_target_thread_limit"="42" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" } -// CPU: attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,42" "kernel" "no-trapping-math"="true" "omp_target_thread_limit"="42" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" "uniform-work-group-size"="true" } -// NOIEEE: attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,42" "amdgpu-ieee"="false" "kernel" "no-nans-fp-math"="true" "no-trapping-math"="true" "omp_target_thread_limit"="42" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" } +// DEFAULT: attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,65" "kernel" "no-trapping-math"="true" "omp_target_thread_limit"="42" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" } +// CPU: attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,65" "kernel" "no-trapping-math"="true" "omp_target_thread_limit"="42" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" "uniform-work-group-size"="true" } +// NOIEEE: attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,65" "amdgpu-ieee"="false" "kernel" "no-nans-fp-math"="true" "no-trapping-math"="true" "omp_target_thread_limit"="42" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" } // DEFAULT: attributes #2 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } // CPU: attributes #2 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" } diff --git a/clang/test/OpenMP/amdgcn_fix_static_initializer_debug.cpp b/clang/test/OpenMP/amdgcn_fix_static_initializer_debug.cpp new file mode 100644 index 0000000000000..1f4ddf413840b --- /dev/null +++ b/clang/test/OpenMP/amdgcn_fix_static_initializer_debug.cpp @@ -0,0 +1,17 @@ +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -dwarf-version=2 -debugger-tuning=gdb -debug-info-kind=constructor -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-device -dwarf-version=4 -debugger-tuning=gdb -fcuda-is-device -debug-info-kind=constructor -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK + +// expected-no-diagnostics + +// CHECK: private unnamed_addr addrspace(1) constant [{{[0-9]+}} x i8] c";{{.*}};main; +int main (void) +{ + int res = 0; +#pragma omp target map(res) +#pragma omp parallel for reduction(+:res) + for (int i = 0; i < 10; i++) { + res += i; + } + + return res; +} diff --git a/clang/test/OpenMP/amdgcn_sret_ctor.cpp b/clang/test/OpenMP/amdgcn_sret_ctor.cpp index 99ca31b78e1fc..fc6f7c15eb5e6 100644 --- a/clang/test/OpenMP/amdgcn_sret_ctor.cpp +++ b/clang/test/OpenMP/amdgcn_sret_ctor.cpp @@ -23,8 +23,6 @@ E::E() noexcept : foo(s()) {} // CHECK-NEXT: call void @_Z1sv(ptr addrspace(5) dead_on_unwind writable sret([[STRUCT_S:%.*]]) align 1 [[THIS1_ASCAST]]) #[[ATTR2:[0-9]+]] // CHECK-NEXT: ret void // -// CHECK-LABEL: declare void @_Z1sv( -// CHECK-SAME: ptr addrspace(5) dead_on_unwind writable sret([[STRUCT_S]]) align 1) #[[ATTR1:[0-9]+]] // // CHECK-LABEL: define hidden void @_ZN1EC1Ev( // CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { diff --git a/clang/test/OpenMP/amdgcn_target_codegen_globals.cpp b/clang/test/OpenMP/amdgcn_target_codegen_globals.cpp new file mode 100644 index 0000000000000..87c0e85cc1aa7 --- /dev/null +++ b/clang/test/OpenMP/amdgcn_target_codegen_globals.cpp @@ -0,0 +1,26 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK + +// expected-no-diagnostics + +// CHECK-DAG: @__omp_offloading_[[KERNEL:.*]]_wg_size = weak addrspace(1) constant +// +template +class foo { +public: + foo() { + int a = 0; + +#pragma omp target + { + a += 1; + } + } +}; + + +int main() { + foo local; + return 0; +} diff --git a/clang/test/OpenMP/amdgcn_target_device_vla.cpp b/clang/test/OpenMP/amdgcn_target_device_vla.cpp index 58fef517a9e72..6fb7153f72b3c 100644 --- a/clang/test/OpenMP/amdgcn_target_device_vla.cpp +++ b/clang/test/OpenMP/amdgcn_target_device_vla.cpp @@ -177,254 +177,46 @@ int main() { // // // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30 -// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR0]] { +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-NEXT: [[RESULT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr -// CHECK-NEXT: [[M_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_ADDR]] to ptr -// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr -// CHECK-NEXT: [[RESULT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RESULT_ADDR]] to ptr -// CHECK-NEXT: [[M_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_CASTED]] to ptr -// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr -// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr -// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i64 [[M]], ptr [[M_ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 -// CHECK-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_kernel_environment to ptr), ptr [[DYN_PTR]]) -// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1 -// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] -// CHECK: user_code.entry: -// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) -// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[M_ADDR_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP4]], ptr [[M_CASTED_ASCAST]], align 4 -// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[M_CASTED_ASCAST]], align 8 -// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 -// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]]) #[[ATTR4:[0-9]+]] -// CHECK-NEXT: call void @__kmpc_target_deinit() -// CHECK-NEXT: ret void -// CHECK: worker.exit: -// CHECK-NEXT: ret void -// -// -// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined -// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[RESULT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[I3:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8, addrspace(5) -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr -// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr -// CHECK-NEXT: [[M_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_ADDR]] to ptr -// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr -// CHECK-NEXT: [[RESULT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RESULT_ADDR]] to ptr -// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr -// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr -// CHECK-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr -// CHECK-NEXT: [[DOTCAPTURE_EXPR_1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_1]] to ptr -// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr -// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr -// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr -// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr -// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr -// CHECK-NEXT: [[I3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I3]] to ptr -// CHECK-NEXT: [[M_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_CASTED]] to ptr -// CHECK-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr -// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i64 [[M]], ptr [[M_ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 -// CHECK-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[M_ADDR_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK: omp.precond.then: -// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 -// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP7]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) -// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] -// CHECK-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK: cond.true: -// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-NEXT: br label [[COND_END:%.*]] -// CHECK: cond.false: -// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: br label [[COND_END]] -// CHECK: cond.end: -// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK: omp.inner.for.cond: -// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP13]], [[ADD]] -// CHECK-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK: omp.inner.for.body: -// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[M_ADDR_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP19]], ptr [[M_CASTED_ASCAST]], align 4 -// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr [[M_CASTED_ASCAST]], align 8 -// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 -// CHECK-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP16]] to ptr -// CHECK-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 8 -// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 -// CHECK-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to ptr -// CHECK-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8 -// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 -// CHECK-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to ptr -// CHECK-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8 -// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 -// CHECK-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP0]] to ptr -// CHECK-NEXT: store ptr [[TMP28]], ptr [[TMP27]], align 8 -// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4 -// CHECK-NEXT: store ptr [[TMP1]], ptr [[TMP29]], align 8 -// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4 -// CHECK-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP31]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 5) -// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK: omp.inner.for.inc: -// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] -// CHECK-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP34]], [[TMP35]] -// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP36]], [[TMP37]] -// CHECK-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP38]], [[TMP39]] -// CHECK-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK: cond.true10: -// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-NEXT: br label [[COND_END12:%.*]] -// CHECK: cond.false11: -// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: br label [[COND_END12]] -// CHECK: cond.end12: -// CHECK-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP40]], [[COND_TRUE10]] ], [ [[TMP41]], [[COND_FALSE11]] ] -// CHECK-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP42]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK: omp.inner.for.end: -// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK: omp.loop.exit: -// CHECK-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4 -// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP44]]) -// CHECK-NEXT: br label [[OMP_PRECOND_END]] -// CHECK: omp.precond.end: -// CHECK-NEXT: ret void -// -// -// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined_omp_outlined -// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR3]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[RESULT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[I4:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[N:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5) // CHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[J11:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr -// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr -// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr -// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// CHECK-NEXT: [[J9:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr // CHECK-NEXT: [[M_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_ADDR]] to ptr // CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr // CHECK-NEXT: [[RESULT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RESULT_ADDR]] to ptr -// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr -// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr // CHECK-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr // CHECK-NEXT: [[DOTCAPTURE_EXPR_1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_1]] to ptr -// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr // CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr // CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr -// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr -// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr -// CHECK-NEXT: [[I4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I4]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr // CHECK-NEXT: [[N_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N]] to ptr // CHECK-NEXT: [[SAVED_STACK_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SAVED_STACK]] to ptr // CHECK-NEXT: [[__VLA_EXPR0_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__VLA_EXPR0]] to ptr // CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr -// CHECK-NEXT: [[J11_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J11]] to ptr -// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[J9_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J9]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 // CHECK-NEXT: store i64 [[M]], ptr [[M_ADDR_ASCAST]], align 8 // CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 // CHECK-NEXT: store ptr [[RESULT]], ptr [[RESULT_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[RESULT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[M_ADDR_ASCAST]], align 4 // CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 @@ -433,115 +225,102 @@ int main() { // CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 // CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK: omp.precond.then: // CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB_ASCAST]], align 4 -// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 -// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP9]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) -// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK: omp.inner.for.cond: -// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: [[CONV5:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP12]] -// CHECK-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK: omp.inner.for.body: -// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[TMP6]] +// CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], 1 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END23:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-NEXT: store i32 [[ADD]], ptr [[I4_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 // CHECK-NEXT: store i32 10, ptr [[N_ASCAST]], align 4 -// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[N_ASCAST]], align 4 -// CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK-NEXT: [[TMP16:%.*]] = call ptr addrspace(5) @llvm.stacksave.p5() -// CHECK-NEXT: store ptr addrspace(5) [[TMP16]], ptr [[SAVED_STACK_ASCAST]], align 4 -// CHECK-NEXT: [[VLA7:%.*]] = alloca i32, i64 [[TMP15]], align 4, addrspace(5) -// CHECK-NEXT: [[VLA7_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA7]] to ptr -// CHECK-NEXT: store i64 [[TMP15]], ptr [[__VLA_EXPR0_ASCAST]], align 8 -// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4_ASCAST]], align 4 -// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4_ASCAST]], align 4 -// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK-NEXT: [[TMP17:%.*]] = call ptr addrspace(5) @llvm.stacksave.p5() +// CHECK-NEXT: store ptr addrspace(5) [[TMP17]], ptr [[SAVED_STACK_ASCAST]], align 4 +// CHECK-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP16]], align 4, addrspace(5) +// CHECK-NEXT: [[VLA3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA3]] to ptr +// CHECK-NEXT: store i64 [[TMP16]], ptr [[__VLA_EXPR0_ASCAST]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM]] -// CHECK-NEXT: store i32 [[TMP17]], ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 -// CHECK-NEXT: br label [[FOR_COND:%.*]] -// CHECK: for.cond: -// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[J_ASCAST]], align 4 -// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[N_ASCAST]], align 4 -// CHECK-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP19]], [[TMP20]] -// CHECK-NEXT: br i1 [[CMP8]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK: for.body: -// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND4:%.*]] +// CHECK: for.cond4: +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ASCAST]], align 4 +// CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]] +// CHECK-NEXT: br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body6: // CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[J_ASCAST]], align 4 -// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[VLA7_ASCAST]], i64 [[IDXPROM9]] -// CHECK-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX10]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[VLA3_ASCAST]], i64 [[IDXPROM7]] +// CHECK-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX8]], align 4 // CHECK-NEXT: br label [[FOR_INC:%.*]] // CHECK: for.inc: -// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[J_ASCAST]], align 4 -// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4 -// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK: for.end: -// CHECK-NEXT: store i32 0, ptr [[J11_ASCAST]], align 4 -// CHECK-NEXT: br label [[FOR_COND12:%.*]] -// CHECK: for.cond12: -// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[J11_ASCAST]], align 4 -// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[N_ASCAST]], align 4 -// CHECK-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP24]], [[TMP25]] -// CHECK-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END22:%.*]] -// CHECK: for.body14: -// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[J11_ASCAST]], align 4 -// CHECK-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds i32, ptr [[VLA7_ASCAST]], i64 [[IDXPROM15]] -// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[ARRAYIDX16]], align 4 -// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[I4_ASCAST]], align 4 -// CHECK-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM17]] -// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX18]], align 4 -// CHECK-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP29]], [[TMP27]] -// CHECK-NEXT: store i32 [[ADD19]], ptr [[ARRAYIDX18]], align 4 -// CHECK-NEXT: br label [[FOR_INC20:%.*]] -// CHECK: for.inc20: -// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[J11_ASCAST]], align 4 -// CHECK-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP30]], 1 -// CHECK-NEXT: store i32 [[INC21]], ptr [[J11_ASCAST]], align 4 -// CHECK-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK: for.end22: -// CHECK-NEXT: [[TMP31:%.*]] = load ptr addrspace(5), ptr [[SAVED_STACK_ASCAST]], align 4 -// CHECK-NEXT: call void @llvm.stackrestore.p5(ptr addrspace(5) [[TMP31]]) -// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK: omp.body.continue: -// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK: omp.inner.for.inc: -// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] -// CHECK-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK: omp.inner.for.end: -// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK: omp.loop.exit: -// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4 -// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP35]]) -// CHECK-NEXT: br label [[OMP_PRECOND_END]] -// CHECK: omp.precond.end: +// CHECK-NEXT: store i32 0, ptr [[J9_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND10:%.*]] +// CHECK: for.cond10: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[J9_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[N_ASCAST]], align 4 +// CHECK-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP25]], [[TMP26]] +// CHECK-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END20:%.*]] +// CHECK: for.body12: +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[J9_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i32, ptr [[VLA3_ASCAST]], i64 [[IDXPROM13]] +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM15]] +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[ARRAYIDX16]], align 4 +// CHECK-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP30]], [[TMP28]] +// CHECK-NEXT: store i32 [[ADD17]], ptr [[ARRAYIDX16]], align 4 +// CHECK-NEXT: br label [[FOR_INC18:%.*]] +// CHECK: for.inc18: +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[J9_ASCAST]], align 4 +// CHECK-NEXT: [[INC19:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK-NEXT: store i32 [[INC19]], ptr [[J9_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK: for.end20: +// CHECK-NEXT: [[TMP32:%.*]] = load ptr addrspace(5), ptr [[SAVED_STACK_ASCAST]], align 4 +// CHECK-NEXT: call void @llvm.stackrestore.p5(ptr addrspace(5) [[TMP32]]) +// CHECK-NEXT: br label [[FOR_INC21:%.*]] +// CHECK: for.inc21: +// CHECK-NEXT: [[NVPTX_NUM_THREADS22:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP33:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[NVPTX_NUM_THREADS22]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = mul i32 [[TMP34]], 1 +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP35]], [[TMP36]] +// CHECK-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK: for.end23: // CHECK-NEXT: ret void // // @@ -572,13 +351,13 @@ int main() { // CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1 // CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK: user_code.entry: -// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[M_ADDR_ASCAST]], align 4 // CHECK-NEXT: store i32 [[TMP4]], ptr [[M_CASTED_ASCAST]], align 4 // CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[M_CASTED_ASCAST]], align 8 // CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 // CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 -// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]]) #[[ATTR4]] +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]]) #[[ATTR4:[0-9]+]] // CHECK-NEXT: call void @__kmpc_target_deinit() // CHECK-NEXT: ret void // CHECK: worker.exit: @@ -586,7 +365,7 @@ int main() { // // // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined -// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR3]] { +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) @@ -651,7 +430,7 @@ int main() { // CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 // CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 // CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 -// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) // CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 // CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 // CHECK-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] @@ -725,7 +504,7 @@ int main() { // CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[J_ASCAST]], align 4 // CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP36]], 1 // CHECK-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4 -// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK: for.end: // CHECK-NEXT: call void @__kmpc_free_shared(ptr [[A]], i64 [[TMP21]]) // CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -749,7 +528,7 @@ int main() { // // // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined_omp_outlined -// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) @@ -808,7 +587,7 @@ int main() { // CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 // CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 -// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) // CHECK-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK: omp.dispatch.cond: // CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 @@ -877,7 +656,7 @@ int main() { // // // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined_omp_outlined_wrapper -// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5) // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) @@ -951,7 +730,7 @@ int main() { // // // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76_omp_outlined -// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR3]] { +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) @@ -1094,7 +873,7 @@ int main() { // CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[J_ASCAST]], align 4 // CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP37]], 1 // CHECK-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4 -// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK: for.end: // CHECK-NEXT: call void @__kmpc_free_shared(ptr [[A]], i64 [[TMP22]]) // CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1118,7 +897,7 @@ int main() { // // // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76_omp_outlined_omp_outlined -// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) @@ -1246,7 +1025,7 @@ int main() { // // // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76_omp_outlined_omp_outlined_wrapper -// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR8]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5) // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) diff --git a/clang/test/OpenMP/amdgcn_target_fast_fp_apu.cpp b/clang/test/OpenMP/amdgcn_target_fast_fp_apu.cpp new file mode 100644 index 0000000000000..ce9fcb1918cef --- /dev/null +++ b/clang/test/OpenMP/amdgcn_target_fast_fp_apu.cpp @@ -0,0 +1,105 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --version 4 +// REQUIRES: amdgpu-registered-target + +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -target-cpu gfx942 -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s + +#ifndef HEADER +#define HEADER + +#define N 10000; + +#define AMD_safe_fp_atomics 1 << 19 +#define AMD_unsafe_fp_atomics 1 << 20 + +int main(){ + + float sum = 0.0; + +#pragma omp target map(tofrom: sum) +{ + #pragma omp atomic hint(AMD_safe_fp_atomics) + sum+=(float)1.0; +} + +#pragma omp target map(tofrom: sum) +{ + #pragma omp atomic hint(AMD_unsafe_fp_atomics) + sum+=(float)1.0; +} + +#pragma omp target map(tofrom: sum) +{ + #pragma omp atomic + sum+=(float)1.0; +} + + return 1; +} + +#endif +// CHECK-LABEL: define weak_odr protected amdgpu_kernel void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19( +// CHECK-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw fadd ptr [[TMP0]], float 1.000000e+00 syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META11:![0-9]+]], !amdgpu.ignore.denormal.mode [[META11]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define weak_odr protected amdgpu_kernel void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25( +// CHECK-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw fadd ptr [[TMP0]], float 1.000000e+00 syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META11]], !amdgpu.ignore.denormal.mode [[META11]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define weak_odr protected amdgpu_kernel void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l31( +// CHECK-SAME: ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l31_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw fadd ptr [[TMP0]], float 1.000000e+00 syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META11]], !amdgpu.ignore.denormal.mode [[META11]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +//. +// CHECK: [[META11]] = !{} +//. diff --git a/clang/test/OpenMP/amdgcn_target_printf_codegen.c b/clang/test/OpenMP/amdgcn_target_printf_codegen.c new file mode 100644 index 0000000000000..7243933f3230c --- /dev/null +++ b/clang/test/OpenMP/amdgcn_target_printf_codegen.c @@ -0,0 +1,21 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: amdgpu-registered-target +// REQUIRES: x86-registered-target + +// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-host.bc +// RUN: %clang_cc1 -verify -fopenmp -x c -triple amdgcn-amd-amdhsa -fopenmp-is-device -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-host-ir-file-path %t-host.bc -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK +// expected-no-diagnostics + +// CHECK-DAG: @__omp_offloading_[[KERNEL:.*]]_wg_size = weak addrspace(1) constant +extern int printf(const char *, ...); + +int CheckZeroArg() { + // size passed to printf_alloc (Hello, world + \0) 13 bytes + 4 bytes + 4 bytes + 4 bytes + 4 bytes = 29 + + #pragma omp target + { + printf("Hello, world"); + } + + return 0; +} diff --git a/clang/test/OpenMP/amdgcn_target_printf_conditional_codegen.c b/clang/test/OpenMP/amdgcn_target_printf_conditional_codegen.c new file mode 100755 index 0000000000000..51fe7e2248ec4 --- /dev/null +++ b/clang/test/OpenMP/amdgcn_target_printf_conditional_codegen.c @@ -0,0 +1,42 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: amdgpu-registered-target +// REQUIRES: x86-registered-target + +// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-host.bc +// RUN: %clang_cc1 -verify -fopenmp -x c -triple amdgcn-amd-amdhsa -fopenmp-is-device -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-host-ir-file-path %t-host.bc -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK +// expected-no-diagnostics + + + +extern int printf(const char *, ...); + +int CheckInlinedConditionalArg() { + char *true_string = "true string"; + char *false_string = "false string"; + + + + #pragma omp target + { + printf("%s\n", 1 ? true_string : false_string); + } + + return 0; +} + +int CheckOutlinedConditionalArg() { + char *true_string = "true string"; + char *false_string = "false string"; + + + + #pragma omp target + { + char * conditional = 1 ? true_string : false_string; + printf("%s\n", conditional); + } + + return 0; +} +//// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +// CHECK: {{.*}} diff --git a/clang/test/OpenMP/amdgcn_target_printf_unknown_size_arguments.c b/clang/test/OpenMP/amdgcn_target_printf_unknown_size_arguments.c new file mode 100644 index 0000000000000..3a41bf7ccb6d3 --- /dev/null +++ b/clang/test/OpenMP/amdgcn_target_printf_unknown_size_arguments.c @@ -0,0 +1,51 @@ +// REQUIRES: amdgpu-registered-target +// REQUIRES: x86-registered-target + +// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-host.bc +// RUN: %clang_cc1 -verify -fopenmp -x c -triple amdgcn-amd-amdhsa -fopenmp-is-device -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-host-ir-file-path %t-host.bc -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK +// expected-no-diagnostics + +extern int printf(const char *, ...); + +int CheckMultipleArgs(int a) { + char *test = "testing"; + char *t; +#pragma omp target private(t) + { + t = test + a; + printf("%s %d %s", t, 21, test); +// CHECK-LABEL: define weak_odr protected amdgpu_kernel void @{{.*}}CheckMultipleArgs +// CHECK: entry: +// CHECK: [[DYN_PTR_ADDR:%[a-zA-Z0-9_.]+]] = alloca ptr, align 8, addrspace(5) +// CHECK: [[TEST_ADDR:%[a-zA-Z0-9_.]+]] = alloca ptr, align 8, addrspace(5) +// CHECK: [[A_ADDR:%[a-zA-Z0-9_.]+]] = alloca i64, align 8, addrspace(5) +// CHECK: [[T_ADDR:%[a-zA-Z0-9_.]+]] = alloca ptr, align 8, addrspace(5) +// CHECK: [[DYN_PTR_CAST:%[a-zA-Z0-9_.]+]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK: [[TEST_CAST:%[a-zA-Z0-9_.]+]] = addrspacecast ptr addrspace(5) [[TEST_ADDR]] to ptr +// CHECK: [[A_CAST:%[a-zA-Z0-9_.]+]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK: [[T_CAST:%[a-zA-Z0-9_.]+]] = addrspacecast ptr addrspace(5) [[T_ADDR]] to ptr +// CHECK: store ptr %dyn_ptr, ptr [[DYN_PTR_CAST]], align 8 +// CHECK: store ptr %test, ptr [[TEST_CAST]], align 8 +// CHECK: store i64 %a, ptr [[A_CAST]], align 8 +// CHECK: [[INIT_CALL:%[a-zA-Z0-9_.]+]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) {{.*}} to ptr), ptr %dyn_ptr) +// CHECK: [[EXEC_USER_CODE:%[a-zA-Z0-9_.]+]] = icmp eq i32 [[INIT_CALL]], -1 +// CHECK: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.+]], label %[[WORKER_EXIT:.+]] + +// CHECK: [[USER_CODE_ENTRY]]: +// CHECK: [[LOAD_TEST:%[0-9]+]] = load ptr, ptr [[TEST_CAST]], align 8 +// CHECK: [[LOAD_A:%[0-9]+]] = load i32, ptr [[A_CAST]], align 4 +// CHECK: %idx.ext = sext i32 [[LOAD_A]] to i64 +// CHECK: %add.ptr = getelementptr inbounds i8, ptr [[LOAD_TEST]], i64 %idx.ext +// CHECK: store ptr %add.ptr, ptr [[T_CAST]], align 8 +// CHECK: [[LOAD_T:%[0-9]+]] = load ptr, ptr [[T_CAST]], align 8 +// CHECK: [[LOAD_TEST_AGAIN:%[0-9]+]] = load ptr, ptr [[TEST_CAST]], align 8 +// CHECK: call ptr @__llvm_omp_emissary_premalloc(i32 %total_buffer_size) +// CHECK: call void @__kmpc_target_deinit() +// CHECK: ret void + +// CHECK: [[WORKER_EXIT]]: +// CHECK: ret void + } + + return 0; +} diff --git a/clang/test/OpenMP/amdgcn_usm_atomics_hint.cpp b/clang/test/OpenMP/amdgcn_usm_atomics_hint.cpp new file mode 100644 index 0000000000000..718d98a257a76 --- /dev/null +++ b/clang/test/OpenMP/amdgcn_usm_atomics_hint.cpp @@ -0,0 +1,69 @@ +// REQUIRES: amdgpu-registered-target + +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -DCHECK_HINTS -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -DCHECK_HINTS -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -target-cpu gfx90a -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK-HINTS +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -DCHECK_FLAG_UNSAFE -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -DCHECK_FLAG_UNSAFE -munsafe-fp-atomics -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -target-cpu gfx90a -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK-FLAG-UNSAFE + +// expected-no-diagnostics +#ifndef HEADER +#define HEADER + +#define N 1000 + +#define amd_fast_fp_atomics 1<<19 +#define amd_safe_fp_atomics 1<<20 + +#pragma omp requires unified_shared_memory + +#if defined CHECK_HINTS + +double test_amdgcn_target_atomic_hints() { +// CHECK-HINTS-LABEL: define {{.*}} @{{.*}}test_amdgcn_target_atomic_hints + + double a = 0.0; + double b = 0.0; + + #pragma omp target teams distribute parallel for map(tofrom:a,b) + for (int i = 0; i < N; i++) { + // CHECK-HINTS: = atomicrmw fadd + #pragma omp atomic hint(amd_fast_fp_atomics) + a+=(double)i; + + // CHECK-HINTS: {{.*}} = atomicrmw + #pragma omp atomic hint(amd_safe_fp_atomics) + b+=(double)i; + } + // CHECK-HINTS: ret void + return a+b; +} +#endif // CHECK_HINTS + +#if defined CHECK_FLAG_UNSAFE + +double test_amdgcn_target_atomic_unsafe_opt() { +// CHECK-FLAG-UNSAFE-LABEL: define {{.*}} @{{.*}}test_amdgcn_target_atomic_unsafe_opt + double a = 0.0; + double b = 0.0; + double c = 0.0; + + #pragma omp target teams distribute parallel for map(tofrom:a,b,c) + for (int i = 0; i < N; i++) { + // CHECK-FLAG-UNSAFE: = atomicrmw fadd + #pragma omp atomic + a+=(double)i; + + // CHECK-FLAG-UNSAFE: = atomicrmw fadd + #pragma omp atomic hint(amd_fast_fp_atomics) + b+=(double)i; + + // CHECK-FLAG-UNSAFE: {{.*}} = atomicrmw + #pragma omp atomic hint(amd_safe_fp_atomics) + c+=(double)i; + } + + return a+b+c; +} +#endif // CHECK_FLAG_UNSAFE + +#endif // HEADER diff --git a/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c b/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c index cc0cc0def48b8..de886d887534a 100644 --- a/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c +++ b/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c @@ -24,223 +24,26 @@ void write_to_aligned_array(int *a, int N) { // CHECK-AMD-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-AMD-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-AMD-NEXT: [[APTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr -// CHECK-AMD-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr -// CHECK-AMD-NEXT: [[APTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[APTR_ADDR]] to ptr -// CHECK-AMD-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr -// CHECK-AMD-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr -// CHECK-AMD-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr -// CHECK-AMD-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: store ptr [[APTR]], ptr [[APTR_ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_kernel_environment to ptr), ptr [[DYN_PTR]]) -// CHECK-AMD-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 -// CHECK-AMD-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] -// CHECK-AMD: user_code.entry: -// CHECK-AMD-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) -// CHECK-AMD-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 [[TMP2]], ptr [[N_CASTED_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP3:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP4:%.*]] = load ptr, ptr [[APTR_ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 -// CHECK-AMD-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP3]], ptr [[TMP4]]) #[[ATTR2:[0-9]+]] -// CHECK-AMD-NEXT: call void @__kmpc_target_deinit() -// CHECK-AMD-NEXT: ret void -// CHECK-AMD: worker.exit: -// CHECK-AMD-NEXT: ret void -// -// -// CHECK-AMD-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined -// CHECK-AMD-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef [[APTR:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK-AMD-NEXT: entry: -// CHECK-AMD-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[APTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-AMD-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[I3:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8, addrspace(5) -// CHECK-AMD-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr -// CHECK-AMD-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr -// CHECK-AMD-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr -// CHECK-AMD-NEXT: [[APTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[APTR_ADDR]] to ptr -// CHECK-AMD-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr -// CHECK-AMD-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr -// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr -// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_1]] to ptr -// CHECK-AMD-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr -// CHECK-AMD-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr -// CHECK-AMD-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr -// CHECK-AMD-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr -// CHECK-AMD-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr -// CHECK-AMD-NEXT: [[I3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I3]] to ptr -// CHECK-AMD-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr -// CHECK-AMD-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr -// CHECK-AMD-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: store ptr [[APTR]], ptr [[APTR_ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// CHECK-AMD-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0 -// CHECK-AMD-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK-AMD-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK-AMD-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// CHECK-AMD-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] -// CHECK-AMD-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK-AMD: omp.precond.then: -// CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -// CHECK-AMD-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 -// CHECK-AMD-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) -// CHECK-AMD-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]] -// CHECK-AMD-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK-AMD: cond.true: -// CHECK-AMD-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-AMD-NEXT: br label [[COND_END:%.*]] -// CHECK-AMD: cond.false: -// CHECK-AMD-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: br label [[COND_END]] -// CHECK-AMD: cond.end: -// CHECK-AMD-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] -// CHECK-AMD-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK-AMD: omp.inner.for.cond: -// CHECK-AMD-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK-AMD-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[ADD]] -// CHECK-AMD-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK-AMD: omp.inner.for.body: -// CHECK-AMD-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK-AMD-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK-AMD-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 [[TMP17]], ptr [[N_CASTED_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP18:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP19:%.*]] = load ptr, ptr [[APTR_ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 -// CHECK-AMD-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP14]] to ptr -// CHECK-AMD-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8 -// CHECK-AMD-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 -// CHECK-AMD-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP16]] to ptr -// CHECK-AMD-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8 -// CHECK-AMD-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 -// CHECK-AMD-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP18]] to ptr -// CHECK-AMD-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8 -// CHECK-AMD-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 -// CHECK-AMD-NEXT: store ptr [[TMP19]], ptr [[TMP26]], align 8 -// CHECK-AMD-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 -// CHECK-AMD-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4) -// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK-AMD: omp.inner.for.inc: -// CHECK-AMD-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] -// CHECK-AMD-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK-AMD-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK-AMD-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]] -// CHECK-AMD-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK-AMD: cond.true10: -// CHECK-AMD-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-AMD-NEXT: br label [[COND_END12:%.*]] -// CHECK-AMD: cond.false11: -// CHECK-AMD-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: br label [[COND_END12]] -// CHECK-AMD: cond.end12: -// CHECK-AMD-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ] -// CHECK-AMD-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK-AMD: omp.inner.for.end: -// CHECK-AMD-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK-AMD: omp.loop.exit: -// CHECK-AMD-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4 -// CHECK-AMD-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP41]]) -// CHECK-AMD-NEXT: br label [[OMP_PRECOND_END]] -// CHECK-AMD: omp.precond.end: -// CHECK-AMD-NEXT: ret void -// -// -// CHECK-AMD-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined_omp_outlined -// CHECK-AMD-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef [[APTR:%.*]]) #[[ATTR1]] { -// CHECK-AMD-NEXT: entry: -// CHECK-AMD-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[APTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-AMD-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-AMD-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-AMD-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[I4:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-AMD-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr -// CHECK-AMD-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr -// CHECK-AMD-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr -// CHECK-AMD-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// CHECK-AMD-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-AMD-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr // CHECK-AMD-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr // CHECK-AMD-NEXT: [[APTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[APTR_ADDR]] to ptr -// CHECK-AMD-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr -// CHECK-AMD-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-AMD-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr // CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr // CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_1]] to ptr -// CHECK-AMD-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr // CHECK-AMD-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr // CHECK-AMD-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr -// CHECK-AMD-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr -// CHECK-AMD-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr -// CHECK-AMD-NEXT: [[I4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I4]] to ptr -// CHECK-AMD-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-AMD-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-AMD-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 // CHECK-AMD-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 // CHECK-AMD-NEXT: store ptr [[APTR]], ptr [[APTR_ADDR_ASCAST]], align 8 +// CHECK-AMD-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-AMD-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 // CHECK-AMD-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 // CHECK-AMD-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 // CHECK-AMD-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 @@ -249,60 +52,47 @@ void write_to_aligned_array(int *a, int N) { // CHECK-AMD-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 // CHECK-AMD-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 // CHECK-AMD-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// CHECK-AMD-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] -// CHECK-AMD-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK-AMD: omp.precond.then: // CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32 -// CHECK-AMD-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK-AMD-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 -// CHECK-AMD-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP7]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) -// CHECK-AMD-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 -// CHECK-AMD-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK-AMD: omp.inner.for.cond: -// CHECK-AMD-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[CONV5:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK-AMD-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP10]] -// CHECK-AMD-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK-AMD: omp.inner.for.body: -// CHECK-AMD-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK-AMD-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4 +// CHECK-AMD-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-AMD-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-AMD-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-AMD-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-AMD-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-AMD-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-AMD-NEXT: [[TMP5:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-AMD-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], [[TMP4]] +// CHECK-AMD-NEXT: [[TMP7:%.*]] = mul i32 [[TMP6]], 1 +// CHECK-AMD-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-AMD-NEXT: [[TMP9:%.*]] = add i32 [[TMP7]], [[TMP8]] +// CHECK-AMD-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-AMD-NEXT: br label [[FOR_COND:%.*]] +// CHECK-AMD: for.cond: +// CHECK-AMD-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-AMD-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-AMD-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK-AMD-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK-AMD: for.body: +// CHECK-AMD-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-AMD-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK-AMD-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-AMD-NEXT: store i32 [[ADD]], ptr [[I4_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP12:%.*]] = load i32, ptr [[I4_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP13:%.*]] = load ptr, ptr [[APTR_ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP14:%.*]] = load i32, ptr [[I4_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK-AMD-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]] -// CHECK-AMD-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 -// CHECK-AMD-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK-AMD: omp.body.continue: -// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK-AMD: omp.inner.for.inc: -// CHECK-AMD-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-AMD-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK-AMD-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK-AMD: omp.inner.for.end: -// CHECK-AMD-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK-AMD: omp.loop.exit: -// CHECK-AMD-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-AMD-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 -// CHECK-AMD-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP18]]) -// CHECK-AMD-NEXT: br label [[OMP_PRECOND_END]] -// CHECK-AMD: omp.precond.end: +// CHECK-AMD-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-AMD-NEXT: [[TMP13:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-AMD-NEXT: [[TMP14:%.*]] = load ptr, ptr [[APTR_ADDR_ASCAST]], align 8 +// CHECK-AMD-NEXT: [[TMP15:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-AMD-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 +// CHECK-AMD-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i64 [[IDXPROM]] +// CHECK-AMD-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 +// CHECK-AMD-NEXT: br label [[FOR_INC:%.*]] +// CHECK-AMD: for.inc: +// CHECK-AMD-NEXT: [[NVPTX_NUM_THREADS3:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-AMD-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-AMD-NEXT: [[TMP17:%.*]] = mul i32 [[NVPTX_NUM_THREADS3]], [[TMP16]] +// CHECK-AMD-NEXT: [[TMP18:%.*]] = mul i32 [[TMP17]], 1 +// CHECK-AMD-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-AMD-NEXT: [[TMP20:%.*]] = add i32 [[TMP18]], [[TMP19]] +// CHECK-AMD-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-AMD-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK-AMD: for.end: // CHECK-AMD-NEXT: ret void // diff --git a/clang/test/OpenMP/begin_declare_variant_messages.c b/clang/test/OpenMP/begin_declare_variant_messages.c index 8878188e7ceb2..ea68fb52d3a31 100644 --- a/clang/test/OpenMP/begin_declare_variant_messages.c +++ b/clang/test/OpenMP/begin_declare_variant_messages.c @@ -69,7 +69,7 @@ const int var; #pragma omp end declare variant #pragma omp begin declare variant match(implementation={vendor(score(foo()) ibm)}) // expected-warning {{expected '':'' after the score expression; '':'' assumed}} #pragma omp end declare variant -#pragma omp begin declare variant match(implementation={vendor(score(5): ibm), vendor(llvm)}) // expected-warning {{the context selector 'vendor' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'vendor' used here}} expected-note {{the ignored selector spans until here}} +#pragma omp begin declare variant match(implementation={vendor(score(5): ibm), vendor(amd)}) // expected-warning {{the context selector 'vendor' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'vendor' used here}} expected-note {{the ignored selector spans until here}} #pragma omp end declare variant #pragma omp begin declare variant match(implementation={vendor(score(5): ibm), kind(cpu)}) // expected-warning {{the context selector 'kind' is not valid for the context set 'implementation'; selector ignored}} expected-note {{the context selector 'kind' can be nested in the context set 'device'; try 'match(device={kind(property)})'}} expected-note {{the ignored selector spans until here}} #pragma omp end declare variant @@ -89,9 +89,9 @@ const int var; #pragma omp end declare variant #pragma omp begin declare variant match(device={kind(score(foo()) ibm)}) // expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('foo()'); score ignored}} expected-warning {{'ibm' is not a valid context property for the context selector 'kind' and the context set 'device'; property ignored}} expected-note {{try 'match(implementation={vendor(ibm)})'}} expected-note {{the ignored property spans until here}} #pragma omp end declare variant -#pragma omp begin declare variant match(device={kind(score(5): host), kind(llvm)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'kind' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'kind' used here}} expected-note {{the ignored selector spans until here}} +#pragma omp begin declare variant match(device={kind(score(5): host), kind(amd)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'kind' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'kind' used here}} expected-note {{the ignored selector spans until here}} #pragma omp end declare variant -#pragma omp begin declare variant match(device={kind(score(5): nohost), vendor(llvm)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'vendor' is not valid for the context set 'device'; selector ignored}} expected-note {{the context selector 'vendor' can be nested in the context set 'implementation'; try 'match(implementation={vendor(property)})'}} expected-note {{the ignored selector spans until here}} +#pragma omp begin declare variant match(device={kind(score(5): nohost), vendor(amd)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'vendor' is not valid for the context set 'device'; selector ignored}} expected-note {{the context selector 'vendor' can be nested in the context set 'implementation'; try 'match(implementation={vendor(property)})'}} expected-note {{the ignored selector spans until here}} #pragma omp end declare variant #pragma omp begin declare variant match(device = {kind(score(foo()): cpu}) // expected-error {{expected ')'}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('foo()'); score ignored}} expected-note {{to match this '('}} #pragma omp end declare variant @@ -100,11 +100,11 @@ const int var; #pragma omp begin declare variant match(device = {kind(score(foo()): cpu)} // expected-error {{expected ')'}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('foo()'); score ignored}} expected-note {{to match this '('}} #pragma omp end declare variant -#pragma omp begin declare variant match(implementation = {vendor(score(foo) :llvm)}) +#pragma omp begin declare variant match(implementation = {vendor(score(foo) :amd)}) #pragma omp end declare variant -#pragma omp begin declare variant match(implementation = {vendor(score(foo()) :llvm)}) +#pragma omp begin declare variant match(implementation = {vendor(score(foo()) :amd)}) #pragma omp end declare variant -#pragma omp begin declare variant match(implementation = {vendor(score() :llvm)}) // expected-error {{expected expression}} expected-error {{use of undeclared identifier 'expr'}} expected-error {{expected expression}} +#pragma omp begin declare variant match(implementation = {vendor(score() :amd)}) // expected-error {{expected expression}} expected-error {{use of undeclared identifier 'expr'}} expected-error {{expected expression}} #pragma omp end declare variant #pragma omp begin declare variant match(user = {condition(foo)}) #pragma omp end declare variant diff --git a/clang/test/OpenMP/begin_declare_variant_using_messages.cpp b/clang/test/OpenMP/begin_declare_variant_using_messages.cpp index 174eea4243e5c..ddc0400c21637 100644 --- a/clang/test/OpenMP/begin_declare_variant_using_messages.cpp +++ b/clang/test/OpenMP/begin_declare_variant_using_messages.cpp @@ -23,7 +23,7 @@ void test_before() { before_1_and_2(); } -#pragma omp begin declare variant match(implementation = {vendor(llvm)}) +#pragma omp begin declare variant match(implementation = {vendor(amd)}) using BEFORE_1_AND_2::before_1_and_2; using BEFORE_AND_1::before_and_1; using ONLY_1::only_1; @@ -35,7 +35,7 @@ void test_1() { } #pragma omp end declare variant -#pragma omp begin declare variant match(implementation = {vendor(llvm)}) +#pragma omp begin declare variant match(implementation = {vendor(amd)}) using AFTER_AND_2::after_and_2; using BEFORE_1_AND_2::before_1_and_2; void test_2() { diff --git a/clang/test/OpenMP/big_jump_loop_codegen.cpp b/clang/test/OpenMP/big_jump_loop_codegen.cpp new file mode 100644 index 0000000000000..9066b5462167e --- /dev/null +++ b/clang/test/OpenMP/big_jump_loop_codegen.cpp @@ -0,0 +1,277 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// REQUIRES: amdgpu-registered-target + +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// expected-no-diagnostics + +int main() +{ + int N = 100000; + + int a[N]; + int b[N]; + + int i; + + for (i=0; i) match(construct={simd}) // CHECK-NEXT: #pragma omp declare variant(foofoo) match(implementation={vendor(score(5): ibm)}, device={kind(fpga)}) // CHECK-NEXT: #pragma omp declare variant(foofoo) match(implementation={vendor(unknown)}) -// CHECK-NEXT: #pragma omp declare variant(foofoo) match(implementation={vendor(score(0): llvm)}, device={kind(cpu)}) +// CHECK-NEXT: #pragma omp declare variant(foofoo) match(implementation={vendor(score(0): amd)}, device={kind(cpu)}) // CHECK-NEXT: int bar(); #pragma omp declare variant(foofoo ) match(xxx = {}) #pragma omp declare variant(foofoo ) match(xxx = {vvv}) -#pragma omp declare variant(foofoo ) match(implementation = {vendor(score(0): "llvm"), xxx}, device = {kind(cpu)}) +#pragma omp declare variant(foofoo ) match(implementation = {vendor(score(0): "amd"), xxx}, device = {kind(cpu)}) #pragma omp declare variant(foofoo ) match(implementation = {vendor("unknown")}) #pragma omp declare variant(foofoo ) match(implementation = {vendor(score(5): ibm)}, device = {kind(fpga)}) #pragma omp declare variant(foofoo ) match(construct = {simd}) @@ -34,7 +34,7 @@ int bar(); // CHECK: #pragma omp declare variant(foofoo) match(implementation={vendor(score(C + 5): ibm)}, device={kind(cpu, host)}) // CHECK-NEXT: #pragma omp declare variant(foofoo) match(implementation={vendor(unknown)}) -// CHECK-NEXT: #pragma omp declare variant(foofoo) match(implementation={vendor(llvm)}, device={kind(cpu)}) +// CHECK-NEXT: #pragma omp declare variant(foofoo) match(implementation={vendor(amd)}, device={kind(cpu)}) // CHECK-NEXT: #pragma omp declare variant(foofoo) match(user={condition(false)}) // CHECK-NEXT: #pragma omp declare variant(foofoo) match(user={condition(true)}) // CHECK-NEXT: template T barbar(); @@ -44,7 +44,7 @@ int bar(); #pragma omp declare variant(foofoo ) match(user = {score(0) : condition(0)}) #pragma omp declare variant(foofoo ) match(user = {condition(true)}) #pragma omp declare variant(foofoo ) match(user = {condition(false)}) -#pragma omp declare variant(foofoo ) match(implementation = {vendor(llvm)}, device = {kind(cpu)}) +#pragma omp declare variant(foofoo ) match(implementation = {vendor(amd)}, device = {kind(cpu)}) #pragma omp declare variant(foofoo ) match(implementation={vendor(unknown)}) #pragma omp declare variant(foofoo ) match(implementation={vendor(score(C+5): ibm, xxx, ibm)},device={kind(cpu,host)}) template @@ -52,7 +52,7 @@ T barbar(); // CHECK: #pragma omp declare variant(foofoo) match(implementation={vendor(score(3 + 5): ibm)}, device={kind(cpu, host)}) // CHECK-NEXT: #pragma omp declare variant(foofoo) match(implementation={vendor(unknown)}) -// CHECK-NEXT: #pragma omp declare variant(foofoo) match(implementation={vendor(llvm)}, device={kind(cpu)}) +// CHECK-NEXT: #pragma omp declare variant(foofoo) match(implementation={vendor(amd)}, device={kind(cpu)}) // CHECK-NEXT: #pragma omp declare variant(foofoo) match(user={condition(false)}) // CHECK-NEXT: #pragma omp declare variant(foofoo) match(user={condition(true)}) // CHECK-NEXT: template<> int barbar(); @@ -74,18 +74,18 @@ void h_ref(C *hp, C *hp2, C *hq, C *lin) { } // CHECK: #pragma omp declare variant(h_ref) match(implementation={vendor(unknown)}, device={kind(nohost)}) -// CHECK-NEXT: #pragma omp declare variant(h_ref) match(implementation={vendor(llvm)}, device={kind(gpu)}) +// CHECK-NEXT: #pragma omp declare variant(h_ref) match(implementation={vendor(amd)}, device={kind(gpu)}) // CHECK-NEXT: template void h(C *hp, C *hp2, C *hq, C *lin) { // CHECK-NEXT: } #pragma omp declare variant(h_ref ) match(xxx = {}) -#pragma omp declare variant(h_ref ) match(implementation = {vendor(llvm)}, device = {kind(gpu)}) +#pragma omp declare variant(h_ref ) match(implementation = {vendor(amd)}, device = {kind(gpu)}) #pragma omp declare variant(h_ref ) match(implementation = {vendor(unknown)}, device = {kind(nohost)}) template void h(C *hp, C *hp2, C *hq, C *lin) { } // CHECK: #pragma omp declare variant(h_ref) match(implementation={vendor(unknown)}, device={kind(nohost)}) -// CHECK-NEXT: #pragma omp declare variant(h_ref) match(implementation={vendor(llvm)}, device={kind(gpu)}) +// CHECK-NEXT: #pragma omp declare variant(h_ref) match(implementation={vendor(amd)}, device={kind(gpu)}) // CHECK-NEXT: template<> void h(float *hp, float *hp2, float *hq, float *lin) { // CHECK-NEXT: } @@ -105,10 +105,10 @@ int fn(); // CHECK: int fn(int); int fn(int); // CHECK: #pragma omp declare variant(fn) match(implementation={vendor(unknown)}, device={kind(cpu, gpu)}) -// CHECK-NEXT: #pragma omp declare variant(fn) match(implementation={vendor(llvm)}) +// CHECK-NEXT: #pragma omp declare variant(fn) match(implementation={vendor(amd)}) // CHECK-NEXT: int overload(); #pragma omp declare variant(fn) match(xxx = {}) -#pragma omp declare variant(fn) match(implementation={vendor(llvm)}) +#pragma omp declare variant(fn) match(implementation={vendor(amd)}) #pragma omp declare variant(fn) match(implementation = {vendor(unknown)}, device = {kind(cpu, gpu)}) int overload(void); @@ -117,10 +117,10 @@ int overload(void); // CHECK-NEXT: } auto fn_deduced_variant() { return 0; } // CHECK: #pragma omp declare variant(fn_deduced_variant) match(implementation={vendor(unknown)}, device={kind(gpu, nohost)}) -// CHECK-NEXT: #pragma omp declare variant(fn_deduced_variant) match(implementation={vendor(llvm)}, device={kind(cpu, host)}) +// CHECK-NEXT: #pragma omp declare variant(fn_deduced_variant) match(implementation={vendor(amd)}, device={kind(cpu, host)}) // CHECK-NEXT: int fn_deduced(); #pragma omp declare variant(fn_deduced_variant) match(xxx = {}) -#pragma omp declare variant(fn_deduced_variant) match(implementation = {vendor(llvm)}, device = {kind(cpu, host)}) +#pragma omp declare variant(fn_deduced_variant) match(implementation = {vendor(amd)}, device = {kind(cpu, host)}) #pragma omp declare variant(fn_deduced_variant) match(implementation = {vendor(unknown)}, device = {kind(gpu, nohost)}) int fn_deduced(); @@ -180,11 +180,11 @@ void SpecialFuncs::xxx() {} // CHECK-NEXT: } static void static_f_variant() {} // CHECK: #pragma omp declare variant(static_f_variant) match(implementation={vendor(unknown)}) -// CHECK-NEXT: #pragma omp declare variant(static_f_variant) match(implementation={vendor(llvm)}, device={kind(fpga)}) +// CHECK-NEXT: #pragma omp declare variant(static_f_variant) match(implementation={vendor(amd)}, device={kind(fpga)}) // CHECK-NEXT: static void static_f() { // CHECK-NEXT: } #pragma omp declare variant(static_f_variant) match(xxx = {}) -#pragma omp declare variant(static_f_variant) match(implementation = {vendor(llvm)}, device = {kind(fpga)}) +#pragma omp declare variant(static_f_variant) match(implementation = {vendor(amd)}, device = {kind(fpga)}) #pragma omp declare variant(static_f_variant) match(implementation={vendor(unknown)}) static void static_f() {} diff --git a/clang/test/OpenMP/declare_variant_implementation_vendor_codegen.cpp b/clang/test/OpenMP/declare_variant_implementation_vendor_codegen.cpp index d4077ce35d813..b3b5429ef63a3 100644 --- a/clang/test/OpenMP/declare_variant_implementation_vendor_codegen.cpp +++ b/clang/test/OpenMP/declare_variant_implementation_vendor_codegen.cpp @@ -24,23 +24,23 @@ int foo() { return 2; } -#pragma omp declare variant(foo) match(implementation = {vendor(llvm)}) +#pragma omp declare variant(foo) match(implementation = {vendor(amd)}) int bar() { return 3; } int bazzz(); -#pragma omp declare variant(bazzz) match(implementation = {vendor(llvm)}) +#pragma omp declare variant(bazzz) match(implementation = {vendor(amd)}) int baz() { return 4; } int test(); -#pragma omp declare variant(test) match(implementation = {vendor(llvm)}) +#pragma omp declare variant(test) match(implementation = {vendor(amd)}) int call() { return 5; } static int stat_unused_(); -#pragma omp declare variant(stat_unused_) match(implementation = {vendor(llvm)}) +#pragma omp declare variant(stat_unused_) match(implementation = {vendor(amd)}) static int stat_unused() { return 6; } static int stat_used_(); -#pragma omp declare variant(stat_used_) match(implementation = {vendor(llvm)}) +#pragma omp declare variant(stat_used_) match(implementation = {vendor(amd)}) static int stat_used() { return 7; } int main() { return bar() + baz() + call() + stat_used(); } @@ -56,10 +56,10 @@ struct SpecialFuncs { int method_() { return 11; } #pragma omp declare variant(SpecialFuncs::method_) \ - match(implementation = {vendor(llvm)}) + match(implementation = {vendor(amd)}) int method() { return 12; } #pragma omp declare variant(SpecialFuncs::method_) \ - match(implementation = {vendor(llvm)}) + match(implementation = {vendor(amd)}) int Method(); } s; @@ -72,10 +72,10 @@ struct SpecSpecialFuncs { int method_(); #pragma omp declare variant(SpecSpecialFuncs::method_) \ - match(implementation = {vendor(llvm)}) + match(implementation = {vendor(amd)}) int method() { return 14; } #pragma omp declare variant(SpecSpecialFuncs::method_) \ - match(implementation = {vendor(llvm)}) + match(implementation = {vendor(amd)}) int Method(); } s1; @@ -90,33 +90,33 @@ void xxx() { int prio() { return 17; } int prio1() { return 18; } -#pragma omp declare variant(prio) match(implementation = {vendor(llvm)}) -#pragma omp declare variant(prio1) match(implementation = {vendor(score(1): llvm)}) +#pragma omp declare variant(prio) match(implementation = {vendor(amd)}) +#pragma omp declare variant(prio1) match(implementation = {vendor(score(1): amd)}) int prio_() { return 19; } static int prio2() { return 20; } static int prio3() { return 21; } static int prio4() { return 22; } -#pragma omp declare variant(prio4) match(implementation = {vendor(score(3): llvm)}) -#pragma omp declare variant(prio2) match(implementation = {vendor(score(5): llvm)}) -#pragma omp declare variant(prio3) match(implementation = {vendor(score(1): llvm)}) +#pragma omp declare variant(prio4) match(implementation = {vendor(score(3): amd)}) +#pragma omp declare variant(prio2) match(implementation = {vendor(score(5): amd)}) +#pragma omp declare variant(prio3) match(implementation = {vendor(score(1): amd)}) static int prio1_() { return 23; } int int_fn() { return prio1_(); } int fn_linkage_variant() { return 24; } extern "C" { -#pragma omp declare variant(fn_linkage_variant) match(implementation = {vendor(llvm)}) +#pragma omp declare variant(fn_linkage_variant) match(implementation = {vendor(amd)}) int fn_linkage() { return 25; } } extern "C" int fn_linkage_variant1() { return 26; } -#pragma omp declare variant(fn_linkage_variant1) match(implementation = {vendor(llvm)}) +#pragma omp declare variant(fn_linkage_variant1) match(implementation = {vendor(amd)}) int fn_linkage1() { return 27; } int fn_variant2() { return 28; } -#pragma omp declare variant(fn_variant2) match(implementation = {vendor(llvm, ibm)}) +#pragma omp declare variant(fn_variant2) match(implementation = {vendor(amd, ibm)}) int fn2() { return 29; } #endif // HEADER diff --git a/clang/test/OpenMP/declare_variant_messages.c b/clang/test/OpenMP/declare_variant_messages.c index d1e36e5d1e7e9..3275c6c8f95c8 100644 --- a/clang/test/OpenMP/declare_variant_messages.c +++ b/clang/test/OpenMP/declare_variant_messages.c @@ -46,7 +46,7 @@ int foo(void); #pragma omp declare variant(foo) match(device={kind(score(2 gpu)}) // expected-error {{expected ')'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('2'); score ignored}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{to match this '('}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} #pragma omp declare variant(foo) match(device={kind(score(foo()) ibm)}) // expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('foo()'); score ignored}} expected-warning {{'ibm' is not a valid context property for the context selector 'kind' and the context set 'device'; property ignored}} expected-note {{try 'match(implementation={vendor(ibm)})'}} expected-note {{the ignored property spans until here}} #pragma omp declare variant(foo) match(device={kind(score(5): host), kind(llvm)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'kind' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'kind' used here}} expected-note {{the ignored selector spans until here}} -#pragma omp declare variant(foo) match(device={kind(score(5): nohost), vendor(llvm)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'vendor' is not valid for the context set 'device'; selector ignored}} expected-note {{the context selector 'vendor' can be nested in the context set 'implementation'; try 'match(implementation={vendor(property)})'}} expected-note {{the ignored selector spans until here}} +#pragma omp declare variant(foo) match(device={kind(score(5): nohost), vendor(amd)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'vendor' is not valid for the context set 'device'; selector ignored}} expected-note {{the context selector 'vendor' can be nested in the context set 'implementation'; try 'match(implementation={vendor(property)})'}} expected-note {{the ignored selector spans until here}} #pragma omp declare variant(foo) match(implementation={extension("aaa")}) // expected-warning {{'aaa' is not a valid context property for the context selector 'extension' and the context set 'implementation'; property ignored}} expected-note {{context property options are: 'match_all' 'match_any' 'match_none'}} expected-note {{the ignored property spans until here}} #pragma omp declare variant(foo) match(target_device={}) // expected-warning {{expected identifier or string literal describing a context selector; selector skipped}} expected-note {{context selector options are: 'kind' 'device_num' 'arch' 'isa'}} expected-note {{the ignored selector spans until here}} #pragma omp declare variant(foo) match(target_device={xxx}) // expected-warning {{'xxx' is not a valid context selector for the context set 'target_device'; selector ignored}} expected-note {{context selector options are: 'kind' 'device_num' 'arch' 'isa'}} expected-note {{the ignored selector spans until here}} @@ -95,8 +95,8 @@ int main(void); -#pragma omp declare variant(foo) match(implementation={vendor(llvm)}) // expected-error {{function declaration is expected after 'declare variant' directive}} -#pragma omp declare variant(foo) match(implementation={vendor(llvm)}) // expected-error {{function declaration is expected after 'declare variant' directive}} +#pragma omp declare variant(foo) match(implementation={vendor(amd)}) // expected-error {{function declaration is expected after 'declare variant' directive}} +#pragma omp declare variant(foo) match(implementation={vendor(amd)}) // expected-error {{function declaration is expected after 'declare variant' directive}} #pragma init_seg(compiler) int main(void); @@ -213,9 +213,9 @@ void caller(void) { // FIXME: If the scores are equivalent we should detect that and allow it. #pragma omp begin declare variant match(implementation = {vendor(score(2) \ - : llvm)}) + : amd)}) #pragma omp declare variant(foo) match(implementation = {vendor(score(2) \ - : llvm)}) // expected-error@-1 {{nested OpenMP context selector contains duplicated trait 'llvm' in selector 'vendor' and set 'implementation' with different score}} + : amd)}) // expected-error@-1 {{nested OpenMP context selector contains duplicated trait 'amd' in selector 'vendor' and set 'implementation' with different score}} int conflicting_nested_score(void); #pragma omp end declare variant diff --git a/clang/test/OpenMP/declare_variant_messages.cpp b/clang/test/OpenMP/declare_variant_messages.cpp index 06da8a8e5b058..b15940b9d8cdc 100644 --- a/clang/test/OpenMP/declare_variant_messages.cpp +++ b/clang/test/OpenMP/declare_variant_messages.cpp @@ -50,8 +50,8 @@ T foofoo(); #pragma omp declare variant(foofoo ) match(device={kind(score( ibm)}) // expected-error {{use of undeclared identifier 'ibm'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} #pragma omp declare variant(foofoo ) match(device={kind(score(2 gpu)}) // expected-error {{expected ')'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('2'); score ignored}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{to match this '('}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} #pragma omp declare variant(foofoo ) match(device={kind(score(foofoo ()) ibm)}) // expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('foofoo()'); score ignored}} expected-warning {{'ibm' is not a valid context property for the context selector 'kind' and the context set 'device'; property ignored}} expected-note {{try 'match(implementation={vendor(ibm)})'}} expected-note {{the ignored property spans until here}} -#pragma omp declare variant(foofoo ) match(device={kind(score(5): host), kind(llvm)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'kind' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'kind' used here}} expected-note {{the ignored selector spans until here}} -#pragma omp declare variant(foofoo ) match(device={kind(score(5): nohost), vendor(llvm)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'vendor' is not valid for the context set 'device'; selector ignored}} expected-note {{the context selector 'vendor' can be nested in the context set 'implementation'; try 'match(implementation={vendor(property)})'}} expected-note {{the ignored selector spans until here}} +#pragma omp declare variant(foofoo ) match(device={kind(score(5): host), kind(amd)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'kind' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'kind' used here}} expected-note {{the ignored selector spans until here}} +#pragma omp declare variant(foofoo ) match(device={kind(score(5): nohost), vendor(amd)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'vendor' is not valid for the context set 'device'; selector ignored}} expected-note {{the context selector 'vendor' can be nested in the context set 'implementation'; try 'match(implementation={vendor(property)})'}} expected-note {{the ignored selector spans until here}} int bar(); #pragma omp declare variant // expected-error {{expected '(' after 'declare variant'}} @@ -80,7 +80,7 @@ int bar(); #pragma omp declare variant(foofoo ) match(implementation={vendor(score( ibm)}) // expected-error {{use of undeclared identifier 'ibm'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{context property options are: 'amd' 'arm' 'bsc' 'cray' 'fujitsu' 'gnu' 'ibm' 'intel' 'llvm' 'nec' 'nvidia' 'pgi' 'ti' 'unknown'}} expected-note {{to match this '('}} #pragma omp declare variant(foofoo ) match(implementation={vendor(score(C ibm)}) // expected-error {{expected ')'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{to match this '('}} expected-note {{context property options are: 'amd' 'arm' 'bsc' 'cray' 'fujitsu' 'gnu' 'ibm' 'intel' 'llvm' 'nec' 'nvidia' 'pgi' 'ti' 'unknown'}} expected-note {{to match this '('}} #pragma omp declare variant(foofoo ) match(implementation={vendor(score(foofoo ()) ibm)}) // expected-warning {{expected '':'' after the score expression; '':'' assumed}} -#pragma omp declare variant(foofoo ) match(implementation={vendor(score(C+5): ibm), vendor(llvm)}) // expected-warning {{the context selector 'vendor' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'vendor' used here}} expected-note {{the ignored selector spans until here}} +#pragma omp declare variant(foofoo ) match(implementation={vendor(score(C+5): ibm), vendor(amd)}) // expected-warning {{the context selector 'vendor' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'vendor' used here}} expected-note {{the ignored selector spans until here}} #pragma omp declare variant(foofoo ) match(implementation={vendor(score(5): ibm), kind(cpu)}) // expected-warning {{the context selector 'kind' is not valid for the context set 'implementation'; selector ignored}} expected-note {{the context selector 'kind' can be nested in the context set 'device'; try 'match(device={kind(property)})'}} expected-note {{the ignored selector spans until here}} #pragma omp declare variant(foofoo ) match(device={xxx}) // expected-warning {{'xxx' is not a valid context selector for the context set 'device'; selector ignored}} expected-note {{context selector options are: 'kind' 'arch' 'isa'}} expected-note {{the ignored selector spans until here}} #pragma omp declare variant(foofoo ) match(device={kind}) // expected-warning {{the context selector 'kind' in context set 'device' requires a context property defined in parentheses; selector ignored}} expected-note {{the ignored selector spans until here}} @@ -90,8 +90,8 @@ int bar(); #pragma omp declare variant(foofoo ) match(device={kind(score( ibm)}) // expected-error {{use of undeclared identifier 'ibm'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} #pragma omp declare variant(foofoo ) match(device={kind(score(C gpu)}) // expected-error {{expected ')'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('C'); score ignored}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{to match this '('}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} #pragma omp declare variant(foofoo ) match(device={kind(score(foofoo ()) ibm)}) // expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('foofoo()'); score ignored}} expected-warning {{'ibm' is not a valid context property for the context selector 'kind' and the context set 'device'; property ignored}} expected-note {{try 'match(implementation={vendor(ibm)})'}} expected-note {{the ignored property spans until here}} -#pragma omp declare variant(foofoo ) match(device={kind(score(C+5): host), kind(llvm)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('C + 5'); score ignored}} expected-warning {{the context selector 'kind' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'kind' used here}} expected-note {{the ignored selector spans until here}} -#pragma omp declare variant(foofoo ) match(device={kind(score(C+5): nohost), vendor(llvm)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('C + 5'); score ignored}} expected-warning {{the context selector 'vendor' is not valid for the context set 'device'; selector ignored}} expected-note {{the context selector 'vendor' can be nested in the context set 'implementation'; try 'match(implementation={vendor(property)})'}} expected-note {{the ignored selector spans until here}} +#pragma omp declare variant(foofoo ) match(device={kind(score(C+5): host), kind(amd)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('C + 5'); score ignored}} expected-warning {{the context selector 'kind' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'kind' used here}} expected-note {{the ignored selector spans until here}} +#pragma omp declare variant(foofoo ) match(device={kind(score(C+5): nohost), vendor(amd)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('C + 5'); score ignored}} expected-warning {{the context selector 'vendor' is not valid for the context set 'device'; selector ignored}} expected-note {{the context selector 'vendor' can be nested in the context set 'implementation'; try 'match(implementation={vendor(property)})'}} expected-note {{the ignored selector spans until here}} template T barbar(); diff --git a/clang/test/OpenMP/declare_variant_mixed_codegen.cpp b/clang/test/OpenMP/declare_variant_mixed_codegen.cpp index d0c3373302f78..c19ef1801344b 100644 --- a/clang/test/OpenMP/declare_variant_mixed_codegen.cpp +++ b/clang/test/OpenMP/declare_variant_mixed_codegen.cpp @@ -35,25 +35,25 @@ int foo() { return 2; } -#pragma omp declare variant(foo) match(implementation = {vendor(llvm)}, device={kind(cpu)}) +#pragma omp declare variant(foo) match(implementation = {vendor(amd)}, device={kind(cpu)}) int bar() { return 3; } int bazzz(); -#pragma omp declare variant(bazzz) match(implementation = {vendor(llvm)}, device={kind(host)}) +#pragma omp declare variant(bazzz) match(implementation = {vendor(amd)}, device={kind(host)}) int baz() { return 4; } int test(); -#pragma omp declare variant(test) match(implementation = {vendor(llvm)}, device={kind(cpu)}) +#pragma omp declare variant(test) match(implementation = {vendor(amd)}, device={kind(cpu)}) int call() { return 5; } static int stat_unused_no_emit() { return 6; } static int stat_unused_(); -#pragma omp declare variant(stat_unused_) match(implementation = {vendor(llvm)}, device={kind(cpu)}) +#pragma omp declare variant(stat_unused_) match(implementation = {vendor(amd)}, device={kind(cpu)}) #pragma omp declare variant(stat_unused_no_emit) match(implementation = {vendor(unknown)}, device = {kind(gpu)}) static int stat_unused() { return 7; } static int stat_used_(); -#pragma omp declare variant(stat_used_) match(implementation = {vendor(llvm)}, device={kind(host)}) +#pragma omp declare variant(stat_used_) match(implementation = {vendor(amd)}, device={kind(host)}) static int stat_used() { return 8; } int main() { return bar() + baz() + call() + stat_used(); } @@ -69,10 +69,10 @@ struct SpecialFuncs { int method_() { return 12; } #pragma omp declare variant(SpecialFuncs::method_) \ - match(implementation = {vendor(llvm)}, device={kind(cpu)}) + match(implementation = {vendor(amd)}, device={kind(cpu)}) int method() { return 13; } #pragma omp declare variant(SpecialFuncs::method_) \ - match(implementation = {vendor(llvm)}, device={kind(host)}) + match(implementation = {vendor(amd)}, device={kind(host)}) int Method(); } s; @@ -85,10 +85,10 @@ struct SpecSpecialFuncs { int method_(); #pragma omp declare variant(SpecSpecialFuncs::method_) \ - match(implementation = {vendor(llvm)}, device={kind(cpu)}) + match(implementation = {vendor(amd)}, device={kind(cpu)}) int method() { return 15; } #pragma omp declare variant(SpecSpecialFuncs::method_) \ - match(implementation = {vendor(llvm)}, device={kind(host)}) + match(implementation = {vendor(amd)}, device={kind(host)}) int Method(); } s1; @@ -103,38 +103,38 @@ void xxx() { int prio() { return 18; } int prio1() { return 19; } -#pragma omp declare variant(prio1) match(implementation = {vendor(score(2): llvm)}, device={kind(cpu,host)}) -#pragma omp declare variant(prio) match(implementation = {vendor(score(1): llvm)}, device={kind(cpu)}) +#pragma omp declare variant(prio1) match(implementation = {vendor(score(2): amd)}, device={kind(cpu,host)}) +#pragma omp declare variant(prio) match(implementation = {vendor(score(1): amd)}, device={kind(cpu)}) int prio_() { return 20; } static int prio2() { return 21; } static int prio3() { return 22; } static int prio4() { return 23; } -#pragma omp declare variant(prio4) match(implementation = {vendor(score(5): llvm)}) -#pragma omp declare variant(prio2) match(implementation = {vendor(score(8): llvm)}, device={kind(cpu,host)}) -#pragma omp declare variant(prio3) match(implementation = {vendor(score(7): llvm)}, device={kind(cpu)}) +#pragma omp declare variant(prio4) match(implementation = {vendor(score(5): amd)}) +#pragma omp declare variant(prio2) match(implementation = {vendor(score(8): amd)}, device={kind(cpu,host)}) +#pragma omp declare variant(prio3) match(implementation = {vendor(score(7): amd)}, device={kind(cpu)}) static int prio1_() { return 24; } int int_fn() { return prio1_(); } int fn_linkage_variant() { return 25; } extern "C" { -#pragma omp declare variant(fn_linkage_variant) match(implementation = {vendor(llvm)}, device={kind(cpu)}) +#pragma omp declare variant(fn_linkage_variant) match(implementation = {vendor(amd)}, device={kind(cpu)}) int fn_linkage() { return 26; } } extern "C" int fn_linkage_variant1() { return 27; } -#pragma omp declare variant(fn_linkage_variant1) match(implementation = {vendor(llvm)}, device={kind(host)}) +#pragma omp declare variant(fn_linkage_variant1) match(implementation = {vendor(amd)}, device={kind(host)}) int fn_linkage1() { return 28; } int fn_variant2() { return 29; } -#pragma omp declare variant(fn_variant2) match(implementation = {vendor(llvm, ibm)}, device={kind(cpu)}) -#pragma omp declare variant(fn_variant2) match(implementation = {vendor(llvm)}, device={kind(cpu,gpu)}) -#pragma omp declare variant(fn_variant2) match(implementation = {vendor(llvm)}, device={kind(nohost)}) -#pragma omp declare variant(fn_variant2) match(implementation = {vendor(llvm)}, device={kind(cpu,nohost)}) -#pragma omp declare variant(fn_variant2) match(implementation = {vendor(llvm)}, device={kind(gpu)}) -#pragma omp declare variant(fn_variant2) match(implementation = {vendor(llvm)}, device={kind(fpga)}) +#pragma omp declare variant(fn_variant2) match(implementation = {vendor(amd, ibm)}, device={kind(cpu)}) +#pragma omp declare variant(fn_variant2) match(implementation = {vendor(amd)}, device={kind(cpu,gpu)}) +#pragma omp declare variant(fn_variant2) match(implementation = {vendor(amd)}, device={kind(nohost)}) +#pragma omp declare variant(fn_variant2) match(implementation = {vendor(amd)}, device={kind(cpu,nohost)}) +#pragma omp declare variant(fn_variant2) match(implementation = {vendor(amd)}, device={kind(gpu)}) +#pragma omp declare variant(fn_variant2) match(implementation = {vendor(amd)}, device={kind(fpga)}) int fn2() { return 30; } #pragma omp declare variant(stat_unused_no_emit) match(implementation = {vendor(unknown)}, device = {kind(gpu)}) diff --git a/clang/test/OpenMP/distribute_parallel_for_reduction_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_reduction_codegen.cpp index 55d9e6550c400..befab49b858b5 100644 --- a/clang/test/OpenMP/distribute_parallel_for_reduction_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_reduction_codegen.cpp @@ -1,35 +1,35 @@ // Test host code gen -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 - -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -verify -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 + +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -verify -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // Test host code gen -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 - -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 + +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fno-openmp-target-xteam-reduction -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s // SIMD-ONLY1-NOT: {{__kmpc|__tgt}} // expected-no-diagnostics diff --git a/clang/test/OpenMP/fast_red_codegen.cpp b/clang/test/OpenMP/fast_red_codegen.cpp new file mode 100644 index 0000000000000..f62249249031e --- /dev/null +++ b/clang/test/OpenMP/fast_red_codegen.cpp @@ -0,0 +1,1781 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-ignore-env-vars -fopenmp-assume-no-nested-parallelism -fopenmp-assume-no-thread-state -fopenmp-target-fast-reduction -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-ignore-env-vars -fopenmp-assume-no-nested-parallelism -fopenmp-assume-no-thread-state -fopenmp-target-fast-reduction -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// expected-no-diagnostics + +#include + +int main() +{ + int N = 100; + + double a[N], b[N]; + int bint[N]; + unsigned cint[N]; + + int8_t int8_sum = 0; + int16_t int16_sum = 0; + int32_t int32_sum = 0; + uint32_t uint32_sum = 0; + int64_t int64_sum = 0; + uint64_t uint64_sum = 0; + + for (int i=0; i + +int main() +{ + int N = 100; + + double a[N]; + uint32_t b[N]; + float c[N]; + uint64_t d[N]; + + for (int i=0; i + +int main() +{ + int N = 100; + + double a[N], b[N]; + int bint[N]; + unsigned cint[N]; + + int8_t int8_sum = 0; + int16_t int16_sum = 0; + int32_t int32_sum = 0; + uint32_t uint32_sum = 0; + int64_t int64_sum = 0; + uint64_t uint64_sum = 0; + + for (int i=0; i no-loop + #pragma omp target + #pragma omp teams + #pragma omp loop + for (int k = 0; k< N; k++) { + c[k]=b[k]; + } + + // FIXME: don't yet support target/teams/loop -> no-loop + #pragma omp target + #pragma omp teams + #pragma omp loop + for (int k = 0; k< N; k++) { + c[k]=b[k]; + } +} +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l16 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 99, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], [[TMP2]] +// CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 1 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP5]], [[TMP6]] +// CHECK-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l21 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR__ADDR]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR__ADDR2]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 99, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], [[TMP2]] +// CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 1 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP5]], [[TMP6]] +// CHECK-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], [[TMP11]] +// CHECK-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[NVPTX_NUM_THREADS4]], [[TMP14]] +// CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], 1 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP16]], [[TMP17]] +// CHECK-NEXT: store i32 [[TMP18]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[K:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR__ADDR]] to ptr +// CHECK-NEXT: [[K_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[K]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: store i32 0, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 24, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], [[TMP3]] +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 1 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]] +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 2 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM1]] +// CHECK-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX2]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS3:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[NVPTX_NUM_THREADS3]], [[TMP15]] +// CHECK-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], 1 +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP17]], [[TMP18]] +// CHECK-NEXT: store i32 [[TMP19]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l31 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[K:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR__ADDR]] to ptr +// CHECK-NEXT: [[K_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[K]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: store i32 0, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 99, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], [[TMP3]] +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 1 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]] +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM1]] +// CHECK-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX2]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS3:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[NVPTX_NUM_THREADS3]], [[TMP15]] +// CHECK-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], 1 +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP17]], [[TMP18]] +// CHECK-NEXT: store i32 [[TMP19]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l36 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[K:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[K_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[K]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: store i32 0, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 99, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], [[TMP3]] +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 1 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]] +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM1]] +// CHECK-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX2]], align 4 +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[TE:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[K:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[TE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TE_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[K_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[K]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TE]], ptr [[TE_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: store i32 0, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 99, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], [[TMP3]] +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 1 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]] +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM1]] +// CHECK-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX2]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS3:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[NVPTX_NUM_THREADS3]], [[TMP15]] +// CHECK-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], 1 +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP17]], [[TMP18]] +// CHECK-NEXT: store i32 [[TMP19]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l48 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[TL:%.*]], i64 noundef [[TE:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[TL_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[K:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[TL_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TL_ADDR]] to ptr +// CHECK-NEXT: [[TE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TE_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[K_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[K]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TL]], ptr [[TL_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TE]], ptr [[TE_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: store i32 0, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 24, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], [[TMP3]] +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 1 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]] +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 2 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP14]] to i64 +// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM1]] +// CHECK-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX2]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS3:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[NVPTX_NUM_THREADS3]], [[TMP15]] +// CHECK-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], 1 +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP17]], [[TMP18]] +// CHECK-NEXT: store i32 [[TMP19]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l54 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l54_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l54_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP0]], ptr [[TMP1]]) #[[ATTR1:[0-9]+]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l54_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[K:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[K_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[K]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 99, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP3]], i32 92, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM2]] +// CHECK-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX3]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP3]]) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l62 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]]) #[[ATTR3]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l62_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l62_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP0]], ptr [[TMP1]]) #[[ATTR1]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l62_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[B:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[K:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[K_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[K]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 99, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP3]], i32 92, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[K_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM2]] +// CHECK-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX3]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP3]]) +// CHECK-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp b/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp index 7c7cdc53fa2d2..3870f0d20e265 100644 --- a/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp +++ b/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp @@ -80,265 +80,36 @@ int main() // IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) // IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr -// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr -// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr -// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr -// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr -// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr -// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr -// IR-GPU-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr -// IR-GPU-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr -// IR-GPU-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment to ptr), ptr [[DYN_PTR]]) -// IR-GPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 -// IR-GPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] -// IR-GPU: user_code.entry: -// IR-GPU-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) -// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP6]], ptr [[N_CASTED_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 -// IR-GPU-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 -// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]] -// IR-GPU-NEXT: call void @__kmpc_target_deinit() -// IR-GPU-NEXT: ret void -// IR-GPU: worker.exit: -// IR-GPU-NEXT: ret void -// -// -// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined -// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1:[0-9]+]] { -// IR-GPU-NEXT: entry: -// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) // IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[J5:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [7 x ptr], align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr -// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr -// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr -// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr -// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr -// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr -// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr -// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr -// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr -// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr -// IR-GPU-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr -// IR-GPU-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr -// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr -// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr -// IR-GPU-NEXT: [[J5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J5]] to ptr -// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr -// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr -// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// IR-GPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 -// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// IR-GPU-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 -// IR-GPU-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// IR-GPU-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// IR-GPU: omp.precond.then: -// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// IR-GPU-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -// IR-GPU-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 -// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) -// IR-GPU-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 -// IR-GPU-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// IR-GPU-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// IR-GPU: cond.true: -// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 -// IR-GPU-NEXT: br label [[COND_END:%.*]] -// IR-GPU: cond.false: -// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// IR-GPU-NEXT: br label [[COND_END]] -// IR-GPU: cond.end: -// IR-GPU-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// IR-GPU-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// IR-GPU: omp.inner.for.cond: -// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 -// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 -// IR-GPU-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] -// IR-GPU-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// IR-GPU: omp.inner.for.body: -// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// IR-GPU-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP21]], ptr [[N_CASTED_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP22:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP23:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 -// IR-GPU-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to ptr -// IR-GPU-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8 -// IR-GPU-NEXT: [[TMP25:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 -// IR-GPU-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to ptr -// IR-GPU-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8 -// IR-GPU-NEXT: [[TMP27:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 -// IR-GPU-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP22]] to ptr -// IR-GPU-NEXT: store ptr [[TMP28]], ptr [[TMP27]], align 8 -// IR-GPU-NEXT: [[TMP29:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 -// IR-GPU-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP0]] to ptr -// IR-GPU-NEXT: store ptr [[TMP30]], ptr [[TMP29]], align 8 -// IR-GPU-NEXT: [[TMP31:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4 -// IR-GPU-NEXT: store ptr [[TMP1]], ptr [[TMP31]], align 8 -// IR-GPU-NEXT: [[TMP32:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5 -// IR-GPU-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP2]] to ptr -// IR-GPU-NEXT: store ptr [[TMP33]], ptr [[TMP32]], align 8 -// IR-GPU-NEXT: [[TMP34:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 6 -// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP34]], align 8 -// IR-GPU-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 4 -// IR-GPU-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP36]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 7) -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// IR-GPU: omp.inner.for.inc: -// IR-GPU-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// IR-GPU-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] -// IR-GPU-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// IR-GPU-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP39]], [[TMP40]] -// IR-GPU-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// IR-GPU-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP41]], [[TMP42]] -// IR-GPU-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 -// IR-GPU-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], [[TMP44]] -// IR-GPU-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] -// IR-GPU: cond.true12: -// IR-GPU-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 -// IR-GPU-NEXT: br label [[COND_END14:%.*]] -// IR-GPU: cond.false13: -// IR-GPU-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// IR-GPU-NEXT: br label [[COND_END14]] -// IR-GPU: cond.end14: -// IR-GPU-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP45]], [[COND_TRUE12]] ], [ [[TMP46]], [[COND_FALSE13]] ] -// IR-GPU-NEXT: store i32 [[COND15]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP47]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] -// IR-GPU: omp.inner.for.end: -// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// IR-GPU: omp.loop.exit: -// IR-GPU-NEXT: [[TMP48:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP48]], align 4 -// IR-GPU-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP49]]) -// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] -// IR-GPU: omp.precond.end: -// IR-GPU-NEXT: ret void -// -// -// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined_omp_outlined -// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { -// IR-GPU-NEXT: entry: -// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) // IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) // IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) // IR-GPU-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) // IR-GPU-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[J6:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr -// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr -// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr -// IR-GPU-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr // IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr // IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr // IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr // IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr // IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr -// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr -// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr // IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr // IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr -// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr // IR-GPU-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr // IR-GPU-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr -// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr -// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr -// IR-GPU-NEXT: [[J6_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J6]] to ptr -// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 // IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]] +// IR-GPU-NEXT: call void @__kmpc_specialized_kernel_init() +// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 // IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 // IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 // IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 @@ -347,63 +118,50 @@ int main() // IR-GPU-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 // IR-GPU-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 // IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] -// IR-GPU-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// IR-GPU: omp.precond.then: // IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 -// IR-GPU-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 -// IR-GPU-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[CONV5]], ptr [[DOTOMP_UB_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 -// IR-GPU-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) -// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// IR-GPU: omp.inner.for.cond: -// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// IR-GPU-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 -// IR-GPU-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[CMP8:%.*]] = icmp ule i64 [[CONV7]], [[TMP14]] -// IR-GPU-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// IR-GPU: omp.inner.for.body: -// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// IR-GPU-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// IR-GPU-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// IR-GPU-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// IR-GPU-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// IR-GPU-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], 1 +// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP13:%.*]] = add i32 [[TMP11]], [[TMP12]] +// IR-GPU-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[FOR_COND:%.*]] +// IR-GPU: for.cond: +// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// IR-GPU-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// IR-GPU: for.body: +// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// IR-GPU-NEXT: store i32 [[ADD]], ptr [[J6_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[J6_ASCAST]], align 4 -// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// IR-GPU-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] -// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// IR-GPU-NEXT: [[TMP18:%.*]] = load i32, ptr [[J6_ASCAST]], align 4 -// IR-GPU-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// IR-GPU-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM9]] -// IR-GPU-NEXT: store i32 [[TMP17]], ptr [[ARRAYIDX10]], align 4 -// IR-GPU-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// IR-GPU: omp.body.continue: -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// IR-GPU: omp.inner.for.inc: -// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// IR-GPU-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// IR-GPU-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] -// IR-GPU: omp.inner.for.end: -// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// IR-GPU: omp.loop.exit: -// IR-GPU-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 -// IR-GPU-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP22]]) -// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] -// IR-GPU: omp.precond.end: +// IR-GPU-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 +// IR-GPU-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM5]] +// IR-GPU-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX6]], align 4 +// IR-GPU-NEXT: br label [[FOR_INC:%.*]] +// IR-GPU: for.inc: +// IR-GPU-NEXT: [[NVPTX_NUM_THREADS7:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// IR-GPU-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// IR-GPU-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS7]], [[TMP20]] +// IR-GPU-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// IR-GPU-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// IR-GPU-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// IR-GPU: for.end: // IR-GPU-NEXT: ret void // // @@ -416,403 +174,139 @@ int main() // IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) // IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr -// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr -// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr -// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr -// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr -// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr -// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr -// IR-GPU-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr -// IR-GPU-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr -// IR-GPU-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_kernel_environment to ptr), ptr [[DYN_PTR]]) -// IR-GPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 -// IR-GPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] -// IR-GPU: user_code.entry: -// IR-GPU-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) -// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP6]], ptr [[N_CASTED_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 -// IR-GPU-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 -// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2]] -// IR-GPU-NEXT: call void @__kmpc_target_deinit() -// IR-GPU-NEXT: ret void -// IR-GPU: worker.exit: -// IR-GPU-NEXT: ret void -// -// -// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined -// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { -// IR-GPU-NEXT: entry: -// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[_TMP3:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8, addrspace(5) // IR-GPU-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) // IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[I11:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[J12:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [7 x ptr], align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr -// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr -// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr -// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr -// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr -// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr -// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr -// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr -// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr -// IR-GPU-NEXT: [[TMP3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[_TMP3]] to ptr -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_4]] to ptr -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_5]] to ptr -// IR-GPU-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr -// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr -// IR-GPU-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr -// IR-GPU-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr -// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr -// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr -// IR-GPU-NEXT: [[I11_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I11]] to ptr -// IR-GPU-NEXT: [[J12_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J12]] to ptr -// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr -// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr -// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// IR-GPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 -// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// IR-GPU-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 -// IR-GPU-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 -// IR-GPU-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// IR-GPU-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// IR-GPU-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// IR-GPU-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 -// IR-GPU-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// IR-GPU-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// IR-GPU: land.lhs.true: -// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 -// IR-GPU-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] -// IR-GPU-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// IR-GPU: omp.precond.then: -// IR-GPU-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 -// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// IR-GPU-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -// IR-GPU-NEXT: [[CONV13:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64 -// IR-GPU-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 -// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_8(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP12]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i64 1, i64 [[CONV13]]) -// IR-GPU-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 -// IR-GPU-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP14]] -// IR-GPU-NEXT: br i1 [[CMP14]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// IR-GPU: cond.true: -// IR-GPU-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 -// IR-GPU-NEXT: br label [[COND_END:%.*]] -// IR-GPU: cond.false: -// IR-GPU-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 -// IR-GPU-NEXT: br label [[COND_END]] -// IR-GPU: cond.end: -// IR-GPU-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] -// IR-GPU-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[TMP17]], ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// IR-GPU: omp.inner.for.cond: -// IR-GPU-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 -// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP19]], 1 -// IR-GPU-NEXT: [[CMP15:%.*]] = icmp slt i64 [[TMP18]], [[ADD]] -// IR-GPU-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// IR-GPU: omp.inner.for.body: -// IR-GPU-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP22]], ptr [[N_CASTED_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP23:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP24:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 -// IR-GPU-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP20]] to ptr -// IR-GPU-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8 -// IR-GPU-NEXT: [[TMP26:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 -// IR-GPU-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP21]] to ptr -// IR-GPU-NEXT: store ptr [[TMP27]], ptr [[TMP26]], align 8 -// IR-GPU-NEXT: [[TMP28:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 -// IR-GPU-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP23]] to ptr -// IR-GPU-NEXT: store ptr [[TMP29]], ptr [[TMP28]], align 8 -// IR-GPU-NEXT: [[TMP30:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 -// IR-GPU-NEXT: [[TMP31:%.*]] = inttoptr i64 [[TMP0]] to ptr -// IR-GPU-NEXT: store ptr [[TMP31]], ptr [[TMP30]], align 8 -// IR-GPU-NEXT: [[TMP32:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4 -// IR-GPU-NEXT: store ptr [[TMP1]], ptr [[TMP32]], align 8 -// IR-GPU-NEXT: [[TMP33:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5 -// IR-GPU-NEXT: [[TMP34:%.*]] = inttoptr i64 [[TMP2]] to ptr -// IR-GPU-NEXT: store ptr [[TMP34]], ptr [[TMP33]], align 8 -// IR-GPU-NEXT: [[TMP35:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 6 -// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP35]], align 8 -// IR-GPU-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 -// IR-GPU-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP37]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 7) -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// IR-GPU: omp.inner.for.inc: -// IR-GPU-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 -// IR-GPU-NEXT: [[ADD16:%.*]] = add nsw i64 [[TMP38]], [[TMP39]] -// IR-GPU-NEXT: store i64 [[ADD16]], ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 -// IR-GPU-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP40]], [[TMP41]] -// IR-GPU-NEXT: store i64 [[ADD17]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 -// IR-GPU-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP42]], [[TMP43]] -// IR-GPU-NEXT: store i64 [[ADD18]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 -// IR-GPU-NEXT: [[CMP19:%.*]] = icmp sgt i64 [[TMP44]], [[TMP45]] -// IR-GPU-NEXT: br i1 [[CMP19]], label [[COND_TRUE20:%.*]], label [[COND_FALSE21:%.*]] -// IR-GPU: cond.true20: -// IR-GPU-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 -// IR-GPU-NEXT: br label [[COND_END22:%.*]] -// IR-GPU: cond.false21: -// IR-GPU-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 -// IR-GPU-NEXT: br label [[COND_END22]] -// IR-GPU: cond.end22: -// IR-GPU-NEXT: [[COND23:%.*]] = phi i64 [ [[TMP46]], [[COND_TRUE20]] ], [ [[TMP47]], [[COND_FALSE21]] ] -// IR-GPU-NEXT: store i64 [[COND23]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[TMP48]], ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] -// IR-GPU: omp.inner.for.end: -// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// IR-GPU: omp.loop.exit: -// IR-GPU-NEXT: [[TMP49:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP49]], align 4 -// IR-GPU-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP50]]) -// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] -// IR-GPU: omp.precond.end: -// IR-GPU-NEXT: ret void -// -// -// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined_omp_outlined -// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { -// IR-GPU-NEXT: entry: -// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[_TMP3:%.*]] = alloca i32, align 4, addrspace(5) // IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8, addrspace(5) // IR-GPU-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8, addrspace(5) // IR-GPU-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8, addrspace(5) -// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[I11:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[J12:%.*]] = alloca i32, align 4, addrspace(5) -// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr -// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr -// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr -// IR-GPU-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr // IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr // IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr // IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr // IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr // IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr -// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr -// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr -// IR-GPU-NEXT: [[TMP3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[_TMP3]] to ptr -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_4]] to ptr -// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_5]] to ptr // IR-GPU-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr // IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_4]] to ptr // IR-GPU-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr // IR-GPU-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr -// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr -// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr -// IR-GPU-NEXT: [[I11_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I11]] to ptr -// IR-GPU-NEXT: [[J12_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J12]] to ptr -// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 // IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]] // IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]] +// IR-GPU-NEXT: call void @__kmpc_specialized_kernel_init() +// IR-GPU-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 // IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 // IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 // IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 // IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 // IR-GPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 // IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // IR-GPU-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 -// IR-GPU-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 -// IR-GPU-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// IR-GPU-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// IR-GPU-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// IR-GPU-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB5:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-GPU-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB5]], 1 +// IR-GPU-NEXT: [[CONV7:%.*]] = sext i32 [[DIV6]] to i64 +// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV7]] +// IR-GPU-NEXT: [[SUB8:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-GPU-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 8 // IR-GPU-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 // IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 -// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] -// IR-GPU-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// IR-GPU: land.lhs.true: -// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 -// IR-GPU-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] -// IR-GPU-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// IR-GPU: omp.precond.then: // IR-GPU-NEXT: store i64 0, ptr [[DOTOMP_LB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_UB_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_LB_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_UB_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 -// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 -// IR-GPU-NEXT: call void @__kmpc_for_static_init_8(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP14]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i64 1, i64 1) -// IR-GPU-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_LB_ASCAST]], align 8 -// IR-GPU-NEXT: store i64 [[TMP15]], ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// IR-GPU: omp.inner.for.cond: -// IR-GPU-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[CMP13:%.*]] = icmp ule i64 [[TMP16]], [[TMP17]] -// IR-GPU-NEXT: br i1 [[CMP13]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// IR-GPU: omp.inner.for.body: -// IR-GPU-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 -// IR-GPU-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP19]], 0 -// IR-GPU-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 -// IR-GPU-NEXT: [[MUL16:%.*]] = mul nsw i32 1, [[DIV15]] -// IR-GPU-NEXT: [[CONV17:%.*]] = sext i32 [[MUL16]] to i64 -// IR-GPU-NEXT: [[DIV18:%.*]] = sdiv i64 [[TMP18]], [[CONV17]] -// IR-GPU-NEXT: [[MUL19:%.*]] = mul nsw i64 [[DIV18]], 1 -// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL19]] -// IR-GPU-NEXT: [[CONV20:%.*]] = trunc i64 [[ADD]] to i32 -// IR-GPU-NEXT: store i32 [[CONV20]], ptr [[I11_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_UB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// IR-GPU-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// IR-GPU-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// IR-GPU-NEXT: [[TMP11:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// IR-GPU-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], [[TMP10]] +// IR-GPU-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// IR-GPU-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], 1 +// IR-GPU-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP16:%.*]] = add i64 [[TMP14]], [[TMP15]] +// IR-GPU-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: br label [[FOR_COND:%.*]] +// IR-GPU: for.cond: +// IR-GPU-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB_ASCAST]], align 8 +// IR-GPU-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// IR-GPU-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// IR-GPU: for.body: +// IR-GPU-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB9:%.*]] = sub nsw i32 [[TMP20]], 0 +// IR-GPU-NEXT: [[DIV10:%.*]] = sdiv i32 [[SUB9]], 1 +// IR-GPU-NEXT: [[MUL11:%.*]] = mul nsw i32 1, [[DIV10]] +// IR-GPU-NEXT: [[CONV12:%.*]] = sext i32 [[MUL11]] to i64 +// IR-GPU-NEXT: [[DIV13:%.*]] = sdiv i64 [[TMP19]], [[CONV12]] +// IR-GPU-NEXT: [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1 +// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL14]] +// IR-GPU-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD]] to i32 +// IR-GPU-NEXT: store i32 [[CONV15]], ptr [[I_ASCAST]], align 4 // IR-GPU-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 -// IR-GPU-NEXT: [[SUB21:%.*]] = sub nsw i32 [[TMP22]], 0 +// IR-GPU-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB16:%.*]] = sub nsw i32 [[TMP23]], 0 +// IR-GPU-NEXT: [[DIV17:%.*]] = sdiv i32 [[SUB16]], 1 +// IR-GPU-NEXT: [[MUL18:%.*]] = mul nsw i32 1, [[DIV17]] +// IR-GPU-NEXT: [[CONV19:%.*]] = sext i32 [[MUL18]] to i64 +// IR-GPU-NEXT: [[DIV20:%.*]] = sdiv i64 [[TMP22]], [[CONV19]] +// IR-GPU-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB21:%.*]] = sub nsw i32 [[TMP24]], 0 // IR-GPU-NEXT: [[DIV22:%.*]] = sdiv i32 [[SUB21]], 1 // IR-GPU-NEXT: [[MUL23:%.*]] = mul nsw i32 1, [[DIV22]] // IR-GPU-NEXT: [[CONV24:%.*]] = sext i32 [[MUL23]] to i64 -// IR-GPU-NEXT: [[DIV25:%.*]] = sdiv i64 [[TMP21]], [[CONV24]] -// IR-GPU-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 -// IR-GPU-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP23]], 0 -// IR-GPU-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 -// IR-GPU-NEXT: [[MUL28:%.*]] = mul nsw i32 1, [[DIV27]] -// IR-GPU-NEXT: [[CONV29:%.*]] = sext i32 [[MUL28]] to i64 -// IR-GPU-NEXT: [[MUL30:%.*]] = mul nsw i64 [[DIV25]], [[CONV29]] -// IR-GPU-NEXT: [[SUB31:%.*]] = sub nsw i64 [[TMP20]], [[MUL30]] -// IR-GPU-NEXT: [[MUL32:%.*]] = mul nsw i64 [[SUB31]], 1 -// IR-GPU-NEXT: [[ADD33:%.*]] = add nsw i64 0, [[MUL32]] -// IR-GPU-NEXT: [[CONV34:%.*]] = trunc i64 [[ADD33]] to i32 -// IR-GPU-NEXT: store i32 [[CONV34]], ptr [[J12_ASCAST]], align 4 -// IR-GPU-NEXT: [[TMP24:%.*]] = load i32, ptr [[I11_ASCAST]], align 4 -// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 +// IR-GPU-NEXT: [[MUL25:%.*]] = mul nsw i64 [[DIV20]], [[CONV24]] +// IR-GPU-NEXT: [[SUB26:%.*]] = sub nsw i64 [[TMP21]], [[MUL25]] +// IR-GPU-NEXT: [[MUL27:%.*]] = mul nsw i64 [[SUB26]], 1 +// IR-GPU-NEXT: [[ADD28:%.*]] = add nsw i64 0, [[MUL27]] +// IR-GPU-NEXT: [[CONV29:%.*]] = trunc i64 [[ADD28]] to i32 +// IR-GPU-NEXT: store i32 [[CONV29]], ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 // IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] -// IR-GPU-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// IR-GPU-NEXT: [[TMP26:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 -// IR-GPU-NEXT: [[MUL35:%.*]] = mul nsw i32 [[TMP25]], [[TMP26]] -// IR-GPU-NEXT: [[TMP27:%.*]] = load i32, ptr [[J12_ASCAST]], align 4 -// IR-GPU-NEXT: [[ADD36:%.*]] = add nsw i32 [[MUL35]], [[TMP27]] -// IR-GPU-NEXT: [[TMP28:%.*]] = load i32, ptr [[I11_ASCAST]], align 4 -// IR-GPU-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP28]] to i64 -// IR-GPU-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM37]] -// IR-GPU-NEXT: store i32 [[ADD36]], ptr [[ARRAYIDX38]], align 4 -// IR-GPU-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// IR-GPU: omp.body.continue: -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// IR-GPU: omp.inner.for.inc: -// IR-GPU-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 -// IR-GPU-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP29]], [[TMP30]] -// IR-GPU-NEXT: store i64 [[ADD39]], ptr [[DOTOMP_IV_ASCAST]], align 8 -// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] -// IR-GPU: omp.inner.for.end: -// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// IR-GPU: omp.loop.exit: -// IR-GPU-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4 -// IR-GPU-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP32]]) -// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] -// IR-GPU: omp.precond.end: +// IR-GPU-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-GPU-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: [[MUL30:%.*]] = mul nsw i32 [[TMP26]], [[TMP27]] +// IR-GPU-NEXT: [[TMP28:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD31:%.*]] = add nsw i32 [[MUL30]], [[TMP28]] +// IR-GPU-NEXT: [[TMP29:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM32:%.*]] = sext i32 [[TMP29]] to i64 +// IR-GPU-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM32]] +// IR-GPU-NEXT: store i32 [[ADD31]], ptr [[ARRAYIDX33]], align 4 +// IR-GPU-NEXT: br label [[FOR_INC:%.*]] +// IR-GPU: for.inc: +// IR-GPU-NEXT: [[NVPTX_NUM_THREADS34:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// IR-GPU-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// IR-GPU-NEXT: [[TMP31:%.*]] = mul i32 [[NVPTX_NUM_THREADS34]], [[TMP30]] +// IR-GPU-NEXT: [[TMP32:%.*]] = zext i32 [[TMP31]] to i64 +// IR-GPU-NEXT: [[TMP33:%.*]] = mul i64 [[TMP32]], 1 +// IR-GPU-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP35:%.*]] = add i64 [[TMP33]], [[TMP34]] +// IR-GPU-NEXT: store i64 [[TMP35]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// IR-GPU: for.end: // IR-GPU-NEXT: ret void // // // IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// IR-GPU-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR4:[0-9]+]] { +// IR-GPU-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR3:[0-9]+]] { // IR-GPU-NEXT: entry: // IR-GPU-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) @@ -844,14 +338,14 @@ int main() // IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 // IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]] // IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]] // IR-GPU-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_kernel_environment to ptr), ptr [[DYN_PTR]]) // IR-GPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 // IR-GPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // IR-GPU: user_code.entry: -// IR-GPU-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// IR-GPU-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) // IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 // IR-GPU-NEXT: store i32 [[TMP6]], ptr [[N_CASTED_ASCAST]], align 4 // IR-GPU-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 @@ -860,7 +354,7 @@ int main() // IR-GPU-NEXT: [[TMP9:%.*]] = load i64, ptr [[NT_CASTED_ASCAST]], align 8 // IR-GPU-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 // IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 -// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2]] +// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR1:[0-9]+]] // IR-GPU-NEXT: call void @__kmpc_target_deinit() // IR-GPU-NEXT: ret void // IR-GPU: worker.exit: @@ -868,7 +362,7 @@ int main() // // // IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined -// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR4:[0-9]+]] { // IR-GPU-NEXT: entry: // IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) @@ -921,9 +415,9 @@ int main() // IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 // IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]] // IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]] // IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 // IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 // IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 @@ -944,7 +438,7 @@ int main() // IR-GPU-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() // IR-GPU-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 // IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 -// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) // IR-GPU-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 // IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 // IR-GPU-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] @@ -1045,7 +539,7 @@ int main() // // // IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined_omp_outlined -// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR4]] { // IR-GPU-NEXT: entry: // IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) @@ -1100,9 +594,9 @@ int main() // IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 // IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 // IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]] // IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8, !nonnull [[META8]], !align [[META9]] // IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 // IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 // IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 @@ -1128,7 +622,7 @@ int main() // IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 // IR-GPU-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 // IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 -// IR-GPU-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// IR-GPU-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) // IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 // IR-GPU-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 // IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] @@ -1147,7 +641,7 @@ int main() // IR-GPU-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 // IR-GPU-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] // IR-GPU: if.then: -// IR-GPU-NEXT: [[CALL:%.*]] = call noundef i32 @_Z17omp_get_num_teamsv() #[[ATTR6:[0-9]+]] +// IR-GPU-NEXT: [[CALL:%.*]] = call noundef i32 @_Z17omp_get_num_teamsv() #[[ATTR7:[0-9]+]] // IR-GPU-NEXT: store i32 [[CALL]], ptr [[NT_ADDR_ASCAST]], align 4 // IR-GPU-NEXT: br label [[IF_END]] // IR-GPU: if.end: @@ -1176,7 +670,7 @@ int main() // IR-GPU-NEXT: [[TMP24:%.*]] = load i32, ptr [[J_ASCAST]], align 4 // IR-GPU-NEXT: [[INC:%.*]] = add nsw i32 [[TMP24]], 1 // IR-GPU-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4 -// IR-GPU-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// IR-GPU-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // IR-GPU: for.end: // IR-GPU-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // IR-GPU: omp.body.continue: @@ -1259,9 +753,9 @@ int main() // IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // IR-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 @@ -1298,9 +792,9 @@ int main() // IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 @@ -1401,9 +895,9 @@ int main() // IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 @@ -1498,9 +992,9 @@ int main() // IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // IR-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 @@ -1541,9 +1035,9 @@ int main() // IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 @@ -1659,9 +1153,9 @@ int main() // IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 @@ -1801,9 +1295,9 @@ int main() // IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 32, i32 0) // IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 @@ -1847,9 +1341,9 @@ int main() // IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 @@ -1956,9 +1450,9 @@ int main() // IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 @@ -2044,7 +1538,7 @@ int main() // IR-NEXT: [[TMP28:%.*]] = load i32, ptr [[J]], align 4 // IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP28]], 1 // IR-NEXT: store i32 [[INC]], ptr [[J]], align 4 -// IR-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// IR-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // IR: for.end: // IR-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // IR: omp.body.continue: @@ -2126,9 +1620,9 @@ int main() // IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // IR-PCH-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 @@ -2165,9 +1659,9 @@ int main() // IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 @@ -2268,9 +1762,9 @@ int main() // IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 @@ -2365,9 +1859,9 @@ int main() // IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // IR-PCH-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 @@ -2408,9 +1902,9 @@ int main() // IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 @@ -2526,9 +2020,9 @@ int main() // IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 @@ -2668,9 +2162,9 @@ int main() // IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 32, i32 0) // IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 @@ -2714,9 +2208,9 @@ int main() // IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 @@ -2823,9 +2317,9 @@ int main() // IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 @@ -2911,7 +2405,7 @@ int main() // IR-PCH-NEXT: [[TMP28:%.*]] = load i32, ptr [[J]], align 4 // IR-PCH-NEXT: [[INC:%.*]] = add nsw i32 [[TMP28]], 1 // IR-PCH-NEXT: store i32 [[INC]], ptr [[J]], align 4 -// IR-PCH-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// IR-PCH-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // IR-PCH: for.end: // IR-PCH-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // IR-PCH: omp.body.continue: @@ -2960,9 +2454,9 @@ int main() // IR-GPU-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 // IR-GPU-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 // IR-GPU-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // IR-GPU-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8, !nonnull [[META6]], !align [[META7]] // IR-GPU-NESTED-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64_kernel_environment to ptr), ptr [[DYN_PTR]]) // IR-GPU-NESTED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 // IR-GPU-NESTED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] @@ -3037,9 +2531,9 @@ int main() // IR-GPU-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 // IR-GPU-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 // IR-GPU-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8, !nonnull [[META6]], !align [[META7]] // IR-GPU-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8, !nonnull [[META6]], !align [[META7]] // IR-GPU-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 // IR-GPU-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 // IR-GPU-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 @@ -3225,9 +2719,9 @@ int main() // IR-GPU-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 // IR-GPU-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 // IR-GPU-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 -// IR-GPU-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8, !nonnull [[META6]], !align [[META7]] // IR-GPU-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 -// IR-GPU-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8, !nonnull [[META6]], !align [[META7]] // IR-GPU-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 // IR-GPU-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 // IR-GPU-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 @@ -3382,9 +2876,9 @@ int main() // IR-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // IR-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NESTED-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // IR-NESTED-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 @@ -3425,9 +2919,9 @@ int main() // IR-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 @@ -3543,9 +3037,9 @@ int main() // IR-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 @@ -3712,9 +3206,9 @@ int main() // IR-PCH-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // IR-PCH-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NESTED-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // IR-PCH-NESTED-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 @@ -3755,9 +3249,9 @@ int main() // IR-PCH-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-PCH-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 @@ -3873,9 +3367,9 @@ int main() // IR-PCH-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // IR-PCH-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // IR-PCH-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// IR-PCH-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// IR-PCH-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // IR-PCH-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // IR-PCH-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // IR-PCH-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 diff --git a/clang/test/OpenMP/target_teams_generic_loop_reduction_codegen.cpp b/clang/test/OpenMP/target_teams_generic_loop_reduction_codegen.cpp index f30b33c1b2479..bdf3981d48bd3 100644 --- a/clang/test/OpenMP/target_teams_generic_loop_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_teams_generic_loop_reduction_codegen.cpp @@ -94,74 +94,112 @@ int main() { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP1]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK1-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP0:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK1-NEXT: [[TMP1:%.*]] = mul i64 4, [[TMP0]] +// CHECK1-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK1-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP1]] +// CHECK1-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP3]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP4]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP10]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 2, ptr [[TMP13]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.region_id, ptr [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 3, ptr [[TMP14]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 2, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP23]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP24]], align 4 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP26]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(ptr @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(ptr @_ZZ4mainE5sivar, ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined, ptr [[TMP0]]) +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined, ptr [[TMP2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -173,88 +211,96 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[SIVAR1]], align 4 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK1-NEXT: store i32 0, ptr [[SIVAR2]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]) +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[SIVAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[SIVAR2]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[SIVAR3:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -262,78 +308,80 @@ int main() { // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK1-NEXT: store i32 0, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1: omp.inner.for.body: +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[SIVAR3]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[SIVAR2]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[SIVAR3]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void @@ -384,74 +432,112 @@ int main() { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) -// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[TMP0]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[TMP1]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 3, ptr [[TMP5]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK1-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP0:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK1-NEXT: [[TMP1:%.*]] = mul i64 4, [[TMP0]] +// CHECK1-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK1-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP1]] +// CHECK1-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP2:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[TMP3]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[TMP4]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP10]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 2, ptr [[TMP13]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 3, ptr [[TMP14]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 3, ptr [[TMP15]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 2, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP23]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP24]], align 4 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP26]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(ptr [[T_VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(ptr [[T_VAR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[TMP0]]) +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[TMP2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -463,88 +549,96 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[T_VAR1]], align 4 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[T_VAR1]]) +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[T_VAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -552,78 +646,80 @@ int main() { // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK1-NEXT: store i32 0, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1: omp.inner.for.body: +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[T_VAR3]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[T_VAR3]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void @@ -673,74 +769,112 @@ int main() { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP1]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK3-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP0:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK3-NEXT: [[TMP1:%.*]] = mul i64 4, [[TMP0]] +// CHECK3-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK3-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP1]] +// CHECK3-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP3]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 2, ptr [[TMP13]], align 8 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.region_id, ptr [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 3, ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 3, ptr [[TMP15]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 2, ptr [[TMP22]], align 8 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP23]], align 8 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP24]], align 4 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(ptr @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(ptr @_ZZ4mainE5sivar, ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined, ptr [[TMP0]]) +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined, ptr [[TMP2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -752,86 +886,94 @@ int main() { // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK3-NEXT: store i32 0, ptr [[SIVAR2]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[SIVAR1]]) +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined, i32 [[TMP10]], i32 [[TMP11]], ptr [[SIVAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[SIVAR2]], ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP18]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -839,76 +981,78 @@ int main() { // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK3-NEXT: store i32 0, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[SIVAR2]], ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void @@ -959,74 +1103,112 @@ int main() { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) -// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR]], ptr [[TMP1]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 3, ptr [[TMP5]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK3-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP0:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK3-NEXT: [[TMP1:%.*]] = mul i64 4, [[TMP0]] +// CHECK3-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK3-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP1]] +// CHECK3-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[T_VAR]], ptr [[TMP3]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[T_VAR]], ptr [[TMP4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 2, ptr [[TMP13]], align 8 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 3, ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 3, ptr [[TMP15]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 2, ptr [[TMP22]], align 8 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP23]], align 8 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP24]], align 4 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 +// CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(ptr [[T_VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(ptr [[T_VAR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[TMP0]]) +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[TMP2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -1038,86 +1220,94 @@ int main() { // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK3-NEXT: store i32 0, ptr [[T_VAR2]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[T_VAR1]]) +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i32 [[TMP10]], i32 [[TMP11]], ptr [[T_VAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[T_VAR2]], ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP18]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1125,76 +1315,78 @@ int main() { // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK3-NEXT: store i32 0, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[T_VAR2]], ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void @@ -1255,7 +1447,7 @@ int main() { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44.omp_outlined, ptr [[TMP0]]) // CHECK5-NEXT: ret void // @@ -1278,7 +1470,7 @@ int main() { // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK5-NEXT: store i32 0, ptr [[SIVAR1]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 @@ -1368,7 +1560,7 @@ int main() { // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 diff --git a/clang/test/OpenMP/target_teams_loop_codegen_as_distribute.cpp b/clang/test/OpenMP/target_teams_loop_codegen_as_distribute.cpp new file mode 100644 index 0000000000000..696853ebfee08 --- /dev/null +++ b/clang/test/OpenMP/target_teams_loop_codegen_as_distribute.cpp @@ -0,0 +1,224 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -verify -Wno-vla -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s + +// expected-no-diagnostics +void foo(int i) {} + +int N = 100000; +int main() +{ + int i; + int a[N]; + int b[N]; + + // Presence of call. Cannot use 'parallel for', must use 'distribute' + #pragma omp target teams loop + for (i=0; i < N; i++) { + foo(i); + for (int j=0; j < N; j++) { + a[i] = b[i] * N + j; + } + } + return 0; +} +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l16 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l16_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP6]], ptr [[N_CASTED_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l16_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l16_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[I5:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[I5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I5]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK: omp.precond.then: +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// CHECK-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// CHECK-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I5_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[I5_ASCAST]], align 4 +// CHECK-NEXT: call void @_Z3fooi(i32 noundef [[TMP18]]) #[[ATTR4:[0-9]+]] +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP19]], [[TMP20]] +// CHECK-NEXT: br i1 [[CMP8]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[I5_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[ADD10:%.*]] = add nsw i32 [[MUL9]], [[TMP24]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[I5_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM11]] +// CHECK-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP26]], 1 +// CHECK-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP27]], 1 +// CHECK-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP29]]) +// CHECK-NEXT: br label [[OMP_PRECOND_END]] +// CHECK: omp.precond.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_Z3fooi +// CHECK-SAME: (i32 noundef [[I:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR_ASCAST]], align 4 +// CHECK-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_teams_loop_codegen_as_parallel_for.cpp b/clang/test/OpenMP/target_teams_loop_codegen_as_parallel_for.cpp new file mode 100644 index 0000000000000..d057be08f460f --- /dev/null +++ b/clang/test/OpenMP/target_teams_loop_codegen_as_parallel_for.cpp @@ -0,0 +1,258 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// expected-no-diagnostics + +int N = 100000; +int main() +{ + int a[N]; + int b[N]; + + // Should be transformed into 'target teams distribute parallel for' + #pragma omp target teams loop + for (int j = 0; j != N; j++) + a[j]=b[j]; + + // Should be transformed into 'target teams distribute parallel for' + #pragma omp target teams loop collapse(2) + for (int i = 0; i < N; i++) { + for (int j = 0; j < N; j++) { + a[i] = b[i] * N + j; + } + } + return 0; +} +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP11]], [[TMP12]] +// CHECK-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM5]] +// CHECK-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX6]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS7:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS7]], [[TMP20]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l18 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR_4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_4]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: [[SUB5:%.*]] = sub nsw i32 [[TMP7]], 0 +// CHECK-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB5]], 1 +// CHECK-NEXT: [[CONV7:%.*]] = sext i32 [[DIV6]] to i64 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV7]] +// CHECK-NEXT: [[SUB8:%.*]] = sub nsw i64 [[MUL]], 1 +// CHECK-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i64 0, ptr [[DOTOMP_LB_ASCAST]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_UB_ASCAST]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_LB_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], [[TMP10]] +// CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], 1 +// CHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP14]], [[TMP15]] +// CHECK-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB_ASCAST]], align 8 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 [[TMP20]], 0 +// CHECK-NEXT: [[DIV10:%.*]] = sdiv i32 [[SUB9]], 1 +// CHECK-NEXT: [[MUL11:%.*]] = mul nsw i32 1, [[DIV10]] +// CHECK-NEXT: [[CONV12:%.*]] = sext i32 [[MUL11]] to i64 +// CHECK-NEXT: [[DIV13:%.*]] = sdiv i64 [[TMP19]], [[CONV12]] +// CHECK-NEXT: [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL14]] +// CHECK-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK-NEXT: store i32 [[CONV15]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 [[TMP23]], 0 +// CHECK-NEXT: [[DIV17:%.*]] = sdiv i32 [[SUB16]], 1 +// CHECK-NEXT: [[MUL18:%.*]] = mul nsw i32 1, [[DIV17]] +// CHECK-NEXT: [[CONV19:%.*]] = sext i32 [[MUL18]] to i64 +// CHECK-NEXT: [[DIV20:%.*]] = sdiv i64 [[TMP22]], [[CONV19]] +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// CHECK-NEXT: [[SUB21:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK-NEXT: [[DIV22:%.*]] = sdiv i32 [[SUB21]], 1 +// CHECK-NEXT: [[MUL23:%.*]] = mul nsw i32 1, [[DIV22]] +// CHECK-NEXT: [[CONV24:%.*]] = sext i32 [[MUL23]] to i64 +// CHECK-NEXT: [[MUL25:%.*]] = mul nsw i64 [[DIV20]], [[CONV24]] +// CHECK-NEXT: [[SUB26:%.*]] = sub nsw i64 [[TMP21]], [[MUL25]] +// CHECK-NEXT: [[MUL27:%.*]] = mul nsw i64 [[SUB26]], 1 +// CHECK-NEXT: [[ADD28:%.*]] = add nsw i64 0, [[MUL27]] +// CHECK-NEXT: [[CONV29:%.*]] = trunc i64 [[ADD28]] to i32 +// CHECK-NEXT: store i32 [[CONV29]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[MUL30:%.*]] = mul nsw i32 [[TMP26]], [[TMP27]] +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[ADD31:%.*]] = add nsw i32 [[MUL30]], [[TMP28]] +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM32:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM32]] +// CHECK-NEXT: store i32 [[ADD31]], ptr [[ARRAYIDX33]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS34:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[NVPTX_NUM_THREADS34]], [[TMP30]] +// CHECK-NEXT: [[TMP32:%.*]] = zext i32 [[TMP31]] to i64 +// CHECK-NEXT: [[TMP33:%.*]] = mul i64 [[TMP32]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// CHECK-NEXT: [[TMP35:%.*]] = add i64 [[TMP33]], [[TMP34]] +// CHECK-NEXT: store i64 [[TMP35]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: ret void +// diff --git a/clang/test/OpenMP/taskloop_strictmodifier_codegen.cpp b/clang/test/OpenMP/taskloop_strictmodifier_codegen.cpp index cddd31da1b7fb..c546d7bcd536c 100644 --- a/clang/test/OpenMP/taskloop_strictmodifier_codegen.cpp +++ b/clang/test/OpenMP/taskloop_strictmodifier_codegen.cpp @@ -134,13 +134,13 @@ struct S { // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8, !tbaa [[LONG_TBAA28:![0-9]+]] // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 48 // CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8, !tbaa [[LONG_TBAA29:![0-9]+]] -// CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[TMP3]], 32 -// CHECK-NEXT: [[TMP6:%.*]] = ashr exact i64 [[SEXT]], 32 +// CHECK-NEXT: [[SEXT_I:%.*]] = shl i64 [[TMP3]], 32 +// CHECK-NEXT: [[TMP6:%.*]] = ashr exact i64 [[SEXT_I]], 32 // CHECK-NEXT: br label %[[OMP_INNER_FOR_COND_I:.*]] // CHECK: [[OMP_INNER_FOR_COND_I]]: -// CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[OMP_INNER_FOR_COND_I]] ], [ [[TMP6]], %[[ENTRY]] ] -// CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp ult i64 [[TMP5]], [[INDVARS_IV]] -// CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1 +// CHECK-NEXT: [[INDVARS_IV_I:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_I:%.*]], %[[OMP_INNER_FOR_COND_I]] ], [ [[TMP6]], %[[ENTRY]] ] +// CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp ult i64 [[TMP5]], [[INDVARS_IV_I]] +// CHECK-NEXT: [[INDVARS_IV_NEXT_I]] = add nsw i64 [[INDVARS_IV_I]], 1 // CHECK-NEXT: br i1 [[CMP_NOT_I]], [[DOTOMP_OUTLINED__1_EXIT:label %.*]], label %[[OMP_INNER_FOR_COND_I]] // CHECK: [[_OMP_OUTLINED__1_EXIT:.*:]] // CHECK-NEXT: ret i32 0 @@ -149,27 +149,28 @@ struct S { // CHECK-LABEL: define internal noundef i32 @.omp_task_entry..2( // CHECK-SAME: i32 noundef [[TMP0:%.*]], ptr noalias noundef readonly captures(none) [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @__kmpc_master(ptr nonnull @[[GLOB1]], i32 [[TMP0]]) +// CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) +// CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @__kmpc_master(ptr nonnull @[[GLOB1]], i32 [[TMP0]]), !noalias [[META30]] // CHECK-NEXT: [[DOTNOT_I:%.*]] = icmp eq i32 [[TMP2]], 0 // CHECK-NEXT: br i1 [[DOTNOT_I]], [[DOTOMP_OUTLINED__EXIT:label %.*]], label %[[OMP_IF_THEN_I:.*]] // CHECK: [[OMP_IF_THEN_I]]: // CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 40 -// CHECK-NEXT: tail call void @__kmpc_taskgroup(ptr nonnull @[[GLOB1]], i32 [[TMP0]]) -// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[INT_TBAA3]] -// CHECK-NEXT: [[TMP5:%.*]] = tail call ptr @__kmpc_omp_task_alloc(ptr nonnull @[[GLOB1]], i32 [[TMP0]], i32 33, i64 80, i64 1, ptr nonnull @.omp_task_entry.) +// CHECK-NEXT: tail call void @__kmpc_taskgroup(ptr nonnull @[[GLOB1]], i32 [[TMP0]]), !noalias [[META30]] +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[INT_TBAA3]], !alias.scope [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = tail call ptr @__kmpc_omp_task_alloc(ptr nonnull @[[GLOB1]], i32 [[TMP0]], i32 33, i64 80, i64 1, ptr nonnull @.omp_task_entry.), !noalias [[META30]] // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP5]], i64 32 -// CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP6]], align 8, !tbaa [[CHAR_TBAA19]] +// CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP6]], align 8, !tbaa [[CHAR_TBAA19]], !noalias [[META30]] // CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP5]], i64 40 -// CHECK-NEXT: store i64 0, ptr [[TMP7]], align 8, !tbaa [[LONG_TBAA15]] +// CHECK-NEXT: store i64 0, ptr [[TMP7]], align 8, !tbaa [[LONG_TBAA15]], !noalias [[META30]] // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP5]], i64 48 -// CHECK-NEXT: store i64 9, ptr [[TMP8]], align 8, !tbaa [[LONG_TBAA15]] +// CHECK-NEXT: store i64 9, ptr [[TMP8]], align 8, !tbaa [[LONG_TBAA15]], !noalias [[META30]] // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP5]], i64 56 -// CHECK-NEXT: store i64 1, ptr [[TMP9]], align 8, !tbaa [[LONG_TBAA15]] +// CHECK-NEXT: store i64 1, ptr [[TMP9]], align 8, !tbaa [[LONG_TBAA15]], !noalias [[META30]] // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP5]], i64 72 -// CHECK-NEXT: store i64 0, ptr [[TMP10]], align 8 -// CHECK-NEXT: tail call void @__kmpc_taskloop(ptr nonnull @[[GLOB1]], i32 [[TMP0]], ptr [[TMP5]], i32 1, ptr nonnull [[TMP7]], ptr nonnull [[TMP8]], i64 1, i32 1, i32 0, i64 0, ptr null) -// CHECK-NEXT: tail call void @__kmpc_end_taskgroup(ptr nonnull @[[GLOB1]], i32 [[TMP0]]) -// CHECK-NEXT: tail call void @__kmpc_end_master(ptr nonnull @[[GLOB1]], i32 [[TMP0]]) +// CHECK-NEXT: store i64 0, ptr [[TMP10]], align 8, !noalias [[META30]] +// CHECK-NEXT: tail call void @__kmpc_taskloop(ptr nonnull @[[GLOB1]], i32 [[TMP0]], ptr [[TMP5]], i32 1, ptr nonnull [[TMP7]], ptr nonnull [[TMP8]], i64 1, i32 1, i32 0, i64 0, ptr null), !noalias [[META30]] +// CHECK-NEXT: tail call void @__kmpc_end_taskgroup(ptr nonnull @[[GLOB1]], i32 [[TMP0]]), !noalias [[META30]] +// CHECK-NEXT: tail call void @__kmpc_end_master(ptr nonnull @[[GLOB1]], i32 [[TMP0]]), !noalias [[META30]] // CHECK-NEXT: br [[DOTOMP_OUTLINED__EXIT]] // CHECK: [[_OMP_OUTLINED__EXIT:.*:]] // CHECK-NEXT: ret i32 0 @@ -182,13 +183,13 @@ struct S { // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8, !tbaa [[LONG_TBAA28]] // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 48 // CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8, !tbaa [[LONG_TBAA29]] -// CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[TMP3]], 32 -// CHECK-NEXT: [[TMP6:%.*]] = ashr exact i64 [[SEXT]], 32 +// CHECK-NEXT: [[SEXT_I:%.*]] = shl i64 [[TMP3]], 32 +// CHECK-NEXT: [[TMP6:%.*]] = ashr exact i64 [[SEXT_I]], 32 // CHECK-NEXT: br label %[[OMP_INNER_FOR_COND_I:.*]] // CHECK: [[OMP_INNER_FOR_COND_I]]: -// CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[OMP_INNER_FOR_COND_I]] ], [ [[TMP6]], %[[ENTRY]] ] -// CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp ult i64 [[TMP5]], [[INDVARS_IV]] -// CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1 +// CHECK-NEXT: [[INDVARS_IV_I:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_I:%.*]], %[[OMP_INNER_FOR_COND_I]] ], [ [[TMP6]], %[[ENTRY]] ] +// CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp ult i64 [[TMP5]], [[INDVARS_IV_I]] +// CHECK-NEXT: [[INDVARS_IV_NEXT_I]] = add nsw i64 [[INDVARS_IV_I]], 1 // CHECK-NEXT: br i1 [[CMP_NOT_I]], [[DOTOMP_OUTLINED__3_EXIT:label %.*]], label %[[OMP_INNER_FOR_COND_I]] // CHECK: [[_OMP_OUTLINED__3_EXIT:.*:]] // CHECK-NEXT: ret i32 0 @@ -202,20 +203,20 @@ struct S { // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[TMP3]], align 8, !tbaa [[LONG_TBAA28]] // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 48 // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8, !tbaa [[LONG_TBAA29]] -// CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP2]], align 8, !tbaa [[INTPTR_TBAA33:![0-9]+]], !alias.scope [[META30]], !nonnull [[META35:![0-9]+]], !align [[META36:![0-9]+]] -// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[INT_TBAA3]], !noalias [[META30]] +// CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP2]], align 8, !tbaa [[INTPTR_TBAA36:![0-9]+]], !alias.scope [[META33]], !nonnull [[META38:![0-9]+]], !align [[META39:![0-9]+]] +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[INT_TBAA3]], !noalias [[META33]] // CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt i32 [[TMP8]], 0 // CHECK-NEXT: br i1 [[CMP_I]], label %[[LAND_LHS_TRUE_I:.*]], [[DOTOMP_OUTLINED__5_EXIT:label %.*]] // CHECK: [[LAND_LHS_TRUE_I]]: // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP2]], i64 8 -// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !tbaa [[CHARPTR_TBAA37:![0-9]+]], !alias.scope [[META30]], !nonnull [[META35]], !align [[META38:![0-9]+]] -// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8, !tbaa [[CHARPTR_TBAA7]], !noalias [[META30]] +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !tbaa [[CHARPTR_TBAA40:![0-9]+]], !alias.scope [[META33]], !nonnull [[META38]], !align [[META41:![0-9]+]] +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8, !tbaa [[CHARPTR_TBAA7]], !noalias [[META33]] // CHECK-NEXT: [[IDXPROM_I:%.*]] = zext nneg i32 [[TMP8]] to i64 // CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds nuw ptr, ptr [[TMP11]], i64 [[IDXPROM_I]] -// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[ARRAYIDX_I]], align 8, !tbaa [[CHARPTR_TBAA17]], !noalias [[META30]] +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[ARRAYIDX_I]], align 8, !tbaa [[CHARPTR_TBAA17]], !noalias [[META33]] // CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP12]], i64 [[IDXPROM_I]] -// CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr [[ARRAYIDX5_I]], align 1, !tbaa [[CHAR_TBAA19]], !noalias [[META30]] +// CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr [[ARRAYIDX5_I]], align 1, !tbaa [[CHAR_TBAA19]], !noalias [[META33]] // CHECK-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP13]] to i32 // CHECK-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP8]], [[CONV_I]] // CHECK-NEXT: br i1 [[CMP13_I]], label %[[OMP_INNER_FOR_COND_I:.*]], [[DOTOMP_OUTLINED__5_EXIT]] @@ -235,22 +236,22 @@ struct S { // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8, !tbaa [[LONG_TBAA28]] // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 48 // CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8, !tbaa [[LONG_TBAA29]] -// CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[TMP3]], 32 -// CHECK-NEXT: [[CONV1_I2:%.*]] = ashr exact i64 [[SEXT]], 32 -// CHECK-NEXT: [[CMP_NOT_I3:%.*]] = icmp ult i64 [[TMP5]], [[CONV1_I2]] -// CHECK-NEXT: br i1 [[CMP_NOT_I3]], [[DOTOMP_OUTLINED__7_EXIT:label %.*]], label %[[OMP_INNER_FOR_BODY_I:.*]] +// CHECK-NEXT: [[SEXT_I:%.*]] = shl i64 [[TMP3]], 32 +// CHECK-NEXT: [[CONV113_I:%.*]] = ashr exact i64 [[SEXT_I]], 32 +// CHECK-NEXT: [[CMP_NOT14_I:%.*]] = icmp ult i64 [[TMP5]], [[CONV113_I]] +// CHECK-NEXT: br i1 [[CMP_NOT14_I]], [[DOTOMP_OUTLINED__7_EXIT:label %.*]], label %[[OMP_INNER_FOR_BODY_I:.*]] // CHECK: [[OMP_INNER_FOR_BODY_I]]: -// CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[DOTCANCEL_CONTINUE_I:.*]] ], [ [[CONV1_I2]], %[[ENTRY]] ] +// CHECK-NEXT: [[INDVARS_IV_I:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_I:%.*]], %[[DOTCANCEL_CONTINUE_I:.*]] ], [ [[CONV113_I]], %[[ENTRY]] ] // CHECK-NEXT: [[TMP6:%.*]] = tail call i32 @__kmpc_cancel(ptr nonnull @[[GLOB1]], i32 [[TMP0]], i32 4) // CHECK-NEXT: [[DOTNOT_I:%.*]] = icmp eq i32 [[TMP6]], 0 // CHECK-NEXT: br i1 [[DOTNOT_I]], label %[[DOTCANCEL_CONTINUE_I]], [[DOTOMP_OUTLINED__7_EXIT]] // CHECK: [[_CANCEL_CONTINUE_I:.*:]] // CHECK-NEXT: [[TMP7:%.*]] = tail call i32 @__kmpc_cancellationpoint(ptr nonnull @[[GLOB1]], i32 [[TMP0]], i32 4) // CHECK-NEXT: [[DOTNOT12_I:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1 -// CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp ult i64 [[TMP5]], [[INDVARS_IV_NEXT]] -// CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[DOTNOT12_I]], i1 true, i1 [[CMP_NOT_I]] -// CHECK-NEXT: br i1 [[OR_COND]], [[DOTOMP_OUTLINED__7_EXIT]], label %[[OMP_INNER_FOR_BODY_I]] +// CHECK-NEXT: [[INDVARS_IV_NEXT_I]] = add nsw i64 [[INDVARS_IV_I]], 1 +// CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp ult i64 [[TMP5]], [[INDVARS_IV_NEXT_I]] +// CHECK-NEXT: [[OR_COND_I:%.*]] = select i1 [[DOTNOT12_I]], i1 true, i1 [[CMP_NOT_I]] +// CHECK-NEXT: br i1 [[OR_COND_I]], [[DOTOMP_OUTLINED__7_EXIT]], label %[[OMP_INNER_FOR_BODY_I]] // CHECK: [[_OMP_OUTLINED__7_EXIT:.*:]] // CHECK-NEXT: ret i32 0 // @@ -265,13 +266,13 @@ struct S { // CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP1]], 0 // CHECK-NEXT: br i1 [[DOTNOT]], label %[[OMP_IF_END:.*]], label %[[OMP_IF_THEN:.*]] // CHECK: [[OMP_IF_THEN]]: -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[THIS]], align 4, !tbaa [[INT_TBAA39:![0-9]+]] +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[THIS]], align 4, !tbaa [[INT_TBAA42:![0-9]+]] // CHECK-NEXT: tail call void @__kmpc_taskgroup(ptr nonnull @[[GLOB1]], i32 [[TMP0]]) // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[C_ADDR]], align 4, !tbaa [[INT_TBAA3]] // CHECK-NEXT: [[SUB4:%.*]] = add nsw i32 [[TMP3]], -1 // CHECK-NEXT: [[TMP4:%.*]] = tail call ptr @__kmpc_omp_task_alloc(ptr nonnull @[[GLOB1]], i32 [[TMP0]], i32 1, i64 80, i64 16, ptr nonnull @.omp_task_entry..10) // CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !tbaa [[ANYPTR_TBAA20]] -// CHECK-NEXT: store ptr [[THIS]], ptr [[TMP5]], align 8, !tbaa [[_ZTS1SPTR_TBAA41:![0-9]+]] +// CHECK-NEXT: store ptr [[THIS]], ptr [[TMP5]], align 8, !tbaa [[_ZTS1SPTR_TBAA44:![0-9]+]] // CHECK-NEXT: [[AGG_CAPTURED_SROA_2_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP5]], i64 8 // CHECK-NEXT: store ptr [[C_ADDR]], ptr [[AGG_CAPTURED_SROA_2_0__SROA_IDX]], align 8, !tbaa [[INTPTR_TBAA23]] // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP4]], i64 40 @@ -300,20 +301,20 @@ struct S { // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[TMP3]], align 8, !tbaa [[LONG_TBAA28]] // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 48 // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8, !tbaa [[LONG_TBAA29]] -// CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]]) +// CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]]) // CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP2]], i64 8 -// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !tbaa [[INTPTR_TBAA46:![0-9]+]], !alias.scope [[META43]], !nonnull [[META35]], !align [[META36]] -// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4, !tbaa [[INT_TBAA3]], !noalias [[META43]] +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !tbaa [[INTPTR_TBAA49:![0-9]+]], !alias.scope [[META46]], !nonnull [[META38]], !align [[META39]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4, !tbaa [[INT_TBAA3]], !noalias [[META46]] // CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt i32 [[TMP9]], 0 // CHECK-NEXT: br i1 [[CMP_I]], label %[[TASKLOOP_IF_THEN_I:.*]], [[DOTOMP_OUTLINED__9_EXIT:label %.*]] // CHECK: [[TASKLOOP_IF_THEN_I]]: -// CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[TMP4]], 32 -// CHECK-NEXT: [[TMP10:%.*]] = ashr exact i64 [[SEXT]], 32 +// CHECK-NEXT: [[SEXT_I:%.*]] = shl i64 [[TMP4]], 32 +// CHECK-NEXT: [[TMP10:%.*]] = ashr exact i64 [[SEXT_I]], 32 // CHECK-NEXT: br label %[[OMP_INNER_FOR_COND_I:.*]] // CHECK: [[OMP_INNER_FOR_COND_I]]: -// CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[OMP_INNER_FOR_COND_I]] ], [ [[TMP10]], %[[TASKLOOP_IF_THEN_I]] ] -// CHECK-NEXT: [[CMP8_NOT_I:%.*]] = icmp ult i64 [[TMP6]], [[INDVARS_IV]] -// CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1 +// CHECK-NEXT: [[INDVARS_IV_I:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_I:%.*]], %[[OMP_INNER_FOR_COND_I]] ], [ [[TMP10]], %[[TASKLOOP_IF_THEN_I]] ] +// CHECK-NEXT: [[CMP8_NOT_I:%.*]] = icmp ult i64 [[TMP6]], [[INDVARS_IV_I]] +// CHECK-NEXT: [[INDVARS_IV_NEXT_I]] = add nsw i64 [[INDVARS_IV_I]], 1 // CHECK-NEXT: br i1 [[CMP8_NOT_I]], [[DOTOMP_OUTLINED__9_EXIT]], label %[[OMP_INNER_FOR_COND_I]] // CHECK: [[_OMP_OUTLINED__9_EXIT:.*:]] // CHECK-NEXT: ret i32 0 @@ -354,21 +355,24 @@ struct S { // CHECK: [[LONG_TBAA28]] = !{[[META21]], [[META16]], i64 40} // CHECK: [[LONG_TBAA29]] = !{[[META21]], [[META16]], i64 48} // CHECK: [[META30]] = !{[[META31:![0-9]+]]} -// CHECK: [[META31]] = distinct !{[[META31]], [[META32:![0-9]+]], !".omp_outlined..5: %__context"} -// CHECK: [[META32]] = distinct !{[[META32]], !".omp_outlined..5"} -// CHECK: [[INTPTR_TBAA33]] = !{[[META34:![0-9]+]], [[META24]], i64 0} -// CHECK: [[META34]] = !{!"_ZTSZ4mainE3$_3", [[META24]], i64 0, [[META26]], i64 8} -// CHECK: [[META35]] = !{} -// CHECK: [[META36]] = !{i64 4} -// CHECK: [[CHARPTR_TBAA37]] = !{[[META34]], [[META26]], i64 8} -// CHECK: [[META38]] = !{i64 8} -// CHECK: [[INT_TBAA39]] = !{[[META40:![0-9]+]], [[META4]], i64 0} -// CHECK: [[META40]] = !{!"_ZTS1S", [[META4]], i64 0} -// CHECK: [[_ZTS1SPTR_TBAA41]] = !{[[META42:![0-9]+]], [[META42]], i64 0} -// CHECK: [[META42]] = !{!"p1 _ZTS1S", [[META10]], i64 0} -// CHECK: [[META43]] = !{[[META44:![0-9]+]]} -// CHECK: [[META44]] = distinct !{[[META44]], [[META45:![0-9]+]], !".omp_outlined..9: %__context"} -// CHECK: [[META45]] = distinct !{[[META45]], !".omp_outlined..9"} -// CHECK: [[INTPTR_TBAA46]] = !{[[META47:![0-9]+]], [[META24]], i64 8} -// CHECK: [[META47]] = !{!"_ZTSZN1SC1EiEUt_", [[META42]], i64 0, [[META24]], i64 8} +// CHECK: [[META31]] = distinct !{[[META31]], [[META32:![0-9]+]], !".omp_outlined.: %.privates."} +// CHECK: [[META32]] = distinct !{[[META32]], !".omp_outlined."} +// CHECK: [[META33]] = !{[[META34:![0-9]+]]} +// CHECK: [[META34]] = distinct !{[[META34]], [[META35:![0-9]+]], !".omp_outlined..5: %__context"} +// CHECK: [[META35]] = distinct !{[[META35]], !".omp_outlined..5"} +// CHECK: [[INTPTR_TBAA36]] = !{[[META37:![0-9]+]], [[META24]], i64 0} +// CHECK: [[META37]] = !{!"_ZTSZ4mainE3$_3", [[META24]], i64 0, [[META26]], i64 8} +// CHECK: [[META38]] = !{} +// CHECK: [[META39]] = !{i64 4} +// CHECK: [[CHARPTR_TBAA40]] = !{[[META37]], [[META26]], i64 8} +// CHECK: [[META41]] = !{i64 8} +// CHECK: [[INT_TBAA42]] = !{[[META43:![0-9]+]], [[META4]], i64 0} +// CHECK: [[META43]] = !{!"_ZTS1S", [[META4]], i64 0} +// CHECK: [[_ZTS1SPTR_TBAA44]] = !{[[META45:![0-9]+]], [[META45]], i64 0} +// CHECK: [[META45]] = !{!"p1 _ZTS1S", [[META10]], i64 0} +// CHECK: [[META46]] = !{[[META47:![0-9]+]]} +// CHECK: [[META47]] = distinct !{[[META47]], [[META48:![0-9]+]], !".omp_outlined..9: %__context"} +// CHECK: [[META48]] = distinct !{[[META48]], !".omp_outlined..9"} +// CHECK: [[INTPTR_TBAA49]] = !{[[META50:![0-9]+]], [[META24]], i64 8} +// CHECK: [[META50]] = !{!"_ZTSZN1SC1EiEUt_", [[META45]], i64 0, [[META24]], i64 8} //. diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp index cc03ae4ed05a1..fbd4f257ece66 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp @@ -98,76 +98,114 @@ int main() { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK1-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK1-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK1-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK1-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK1-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i64 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]]) +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -179,88 +217,96 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[SIVAR1]], align 4 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] +// CHECK1-NEXT: store i32 0, ptr [[SIVAR2]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]) +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[SIVAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[SIVAR2]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[SIVAR3:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -268,78 +314,80 @@ int main() { // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK1-NEXT: store i32 0, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1: omp.inner.for.body: +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[SIVAR3]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[SIVAR2]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[SIVAR3]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void @@ -391,9 +439,9 @@ int main() { // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -401,66 +449,104 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK1-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK1-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK1-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK1-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK1-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -472,88 +558,96 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[T_VAR1]], align 4 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[T_VAR1]]) +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[T_VAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -561,78 +655,80 @@ int main() { // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK1-NEXT: store i32 0, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1: omp.inner.for.body: +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[T_VAR3]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[T_VAR3]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void @@ -683,76 +779,114 @@ int main() { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK3-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK3-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK3-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK3-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK3-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i32 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]]) +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -764,86 +898,94 @@ int main() { // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] +// CHECK3-NEXT: store i32 0, ptr [[SIVAR2]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[SIVAR1]]) +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i32 [[TMP10]], i32 [[TMP11]], ptr [[SIVAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[SIVAR2]], ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP18]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -851,76 +993,78 @@ int main() { // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK3-NEXT: store i32 0, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[SIVAR2]], ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void @@ -972,9 +1116,9 @@ int main() { // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -982,66 +1126,104 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK3-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK3-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK3-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK3-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK3-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -1053,86 +1235,94 @@ int main() { // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK3-NEXT: store i32 0, ptr [[T_VAR2]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[T_VAR1]]) +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i32 [[TMP10]], i32 [[TMP11]], ptr [[T_VAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[T_VAR2]], ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP18]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1140,76 +1330,78 @@ int main() { // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK3-NEXT: store i32 0, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[T_VAR2]], ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void @@ -1292,7 +1484,7 @@ int main() { // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK9-NEXT: store i32 0, ptr [[SIVAR1]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 @@ -1382,7 +1574,7 @@ int main() { // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp index 3fe9f624fdfec..61f234529c78e 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp @@ -102,76 +102,114 @@ int main() { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK1-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK1-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK1-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK1-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK1-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.region_id, ptr [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70(i64 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70 -// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined, ptr [[SIVAR_ADDR]]) +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined, ptr [[SIVAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -183,95 +221,103 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[SIVAR1]], align 4 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] +// CHECK1-NEXT: store i32 0, ptr [[SIVAR2]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]), !llvm.access.group [[ACC_GRP5]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[SIVAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]), !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK1: .omp.final.then: // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[SIVAR1]], ptr [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[SIVAR2]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP22]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[SIVAR3:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -279,85 +325,87 @@ int main() { // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK1-NEXT: store i32 0, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR3]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[SIVAR3]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK1: .omp.final.then: // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[SIVAR2]], ptr [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[SIVAR3]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[SIVAR3]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP22]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void @@ -409,9 +457,9 @@ int main() { // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -419,66 +467,104 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK1-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK1-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK1-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK1-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK1-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -490,95 +576,103 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[T_VAR1]], align 4 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[T_VAR1]]), !llvm.access.group [[ACC_GRP14]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[T_VAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]), !llvm.access.group [[ACC_GRP18]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK1: .omp.final.then: // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP22]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -586,85 +680,87 @@ int main() { // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK1-NEXT: store i32 0, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK1: .omp.final.then: // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[T_VAR3]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[T_VAR3]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP22]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void @@ -715,76 +811,114 @@ int main() { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK3-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK3-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK3-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK3-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK3-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.region_id, ptr [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70(i32 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70 -// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined, ptr [[SIVAR_ADDR]]) +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined, ptr [[SIVAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -796,93 +930,101 @@ int main() { // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] +// CHECK3-NEXT: store i32 0, ptr [[SIVAR2]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[SIVAR1]]), !llvm.access.group [[ACC_GRP6]] +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined, i32 [[TMP10]], i32 [[TMP11]], ptr [[SIVAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]), !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK3: .omp.final.then: // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[SIVAR2]], ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -890,83 +1032,85 @@ int main() { // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK3-NEXT: store i32 0, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK3: .omp.final.then: // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP16]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[SIVAR2]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP22]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void @@ -1018,9 +1162,9 @@ int main() { // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -1028,66 +1172,104 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK3-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK3-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK3-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK3-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK3-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -1099,93 +1281,101 @@ int main() { // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK3-NEXT: store i32 0, ptr [[T_VAR2]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[T_VAR1]]), !llvm.access.group [[ACC_GRP15]] +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i32 [[TMP10]], i32 [[TMP11]], ptr [[T_VAR2]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]), !llvm.access.group [[ACC_GRP19]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 -// CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK3: .omp.final.then: // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[T_VAR2]], ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP20]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1193,83 +1383,85 @@ int main() { // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 +// CHECK3-NEXT: store i32 0, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 -// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP6]]) +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] // CHECK3: .omp.final.then: // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP16]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[T_VAR2]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP20]] monotonic, align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP22]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void @@ -1550,7 +1742,7 @@ int main() { // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK9-NEXT: store i32 0, ptr [[SIVAR1]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 @@ -1574,23 +1766,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]] +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]), !llvm.access.group [[ACC_GRP4]] +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]), !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]] +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1647,7 +1839,7 @@ int main() { // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 @@ -1677,30 +1869,30 @@ int main() { // CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]] -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK9-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK9-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store ptr [[SIVAR2]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP8]] -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]] +// CHECK9-NEXT: store ptr [[SIVAR2]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP11]] +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: diff --git a/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp b/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp index 2a3a80687e4b0..0abdb84b50353 100644 --- a/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp +++ b/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp @@ -381,8 +381,8 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I3:%.*]] = alloca i32, align 4 @@ -404,15 +404,15 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK1: omp.precond.then: -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] @@ -420,17 +420,17 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: @@ -485,8 +485,8 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I3:%.*]] = alloca i32, align 4 @@ -508,15 +508,15 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK1: omp.precond.then: -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] @@ -524,17 +524,17 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: @@ -1082,8 +1082,8 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4 @@ -1107,15 +1107,15 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] @@ -1123,17 +1123,17 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9: cond.false: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: br label [[COND_END]] // CHECK9: cond.end: // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: @@ -1798,8 +1798,8 @@ int main (int argc, char **argv) { // CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[I3:%.*]] = alloca i32, align 4 @@ -1823,15 +1823,15 @@ int main (int argc, char **argv) { // CHECK25-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] // CHECK25-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK25: omp.precond.then: -// CHECK25-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK25-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK25-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK25-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 // CHECK25-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK25-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK25-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK25-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] // CHECK25-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] @@ -1839,17 +1839,17 @@ int main (int argc, char **argv) { // CHECK25-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK25-NEXT: br label [[COND_END:%.*]] // CHECK25: cond.false: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK25-NEXT: br label [[COND_END]] // CHECK25: cond.end: // CHECK25-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK25-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK25-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK25-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK25: omp.inner.for.cond: // CHECK25-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK25-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK25-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK25-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25: omp.inner.for.body: diff --git a/clang/test/OpenMP/teams_generic_loop_codegen.cpp b/clang/test/OpenMP/teams_generic_loop_codegen.cpp index 85dcae26970bc..6c7731f8fe26e 100644 --- a/clang/test/OpenMP/teams_generic_loop_codegen.cpp +++ b/clang/test/OpenMP/teams_generic_loop_codegen.cpp @@ -44,8 +44,8 @@ int foo() { // IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 // IR-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// IR-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// IR-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // IR-NEXT: [[J3:%.*]] = alloca i32, align 4 @@ -69,30 +69,30 @@ int foo() { // IR-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] // IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] // IR: omp.arrayinit.done: -// IR-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// IR-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 // IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// IR-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // IR-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // IR-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // IR: cond.true: // IR-NEXT: br label [[COND_END:%.*]] // IR: cond.false: -// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // IR-NEXT: br label [[COND_END]] // IR: cond.end: // IR-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // IR-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // IR-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // IR: omp.inner.for.cond: // IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // IR-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // IR-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // IR: omp.inner.for.body: @@ -240,8 +240,8 @@ int foo() { // IR-PCH-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // IR-PCH-NEXT: [[TMP:%.*]] = alloca i32, align 4 // IR-PCH-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // IR-PCH-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // IR-PCH-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // IR-PCH-NEXT: [[J3:%.*]] = alloca i32, align 4 @@ -265,30 +265,30 @@ int foo() { // IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] // IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] // IR-PCH: omp.arrayinit.done: -// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// IR-PCH-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// IR-PCH-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 // IR-PCH-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// IR-PCH-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // IR-PCH-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 99 // IR-PCH-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // IR-PCH: cond.true: // IR-PCH-NEXT: br label [[COND_END:%.*]] // IR-PCH: cond.false: -// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // IR-PCH-NEXT: br label [[COND_END]] // IR-PCH: cond.end: // IR-PCH-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// IR-PCH-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-PCH-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // IR-PCH-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // IR-PCH: omp.inner.for.cond: // IR-PCH-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // IR-PCH-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // IR-PCH-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // IR-PCH: omp.inner.for.body: diff --git a/clang/test/OpenMP/teams_generic_loop_collapse_codegen.cpp b/clang/test/OpenMP/teams_generic_loop_collapse_codegen.cpp index aa9fe78fc27ac..ad1f2940a442e 100644 --- a/clang/test/OpenMP/teams_generic_loop_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_generic_loop_collapse_codegen.cpp @@ -190,8 +190,8 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -200,30 +200,30 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 56087, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: @@ -351,8 +351,8 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -361,30 +361,30 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 56087, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: @@ -601,8 +601,8 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 @@ -644,15 +644,15 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] // CHECK9: omp.precond.then: -// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB]], align 8 +// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_COMB_UB]], align 8 +// CHECK9-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_UB]], align 8 // CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// CHECK9-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 // CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] // CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] @@ -660,17 +660,17 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 // CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9: cond.false: -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 // CHECK9-NEXT: br label [[COND_END]] // CHECK9: cond.end: // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 +// CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK9-NEXT: store i64 [[TMP18]], ptr [[DOTOMP_IV]], align 8 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: @@ -806,8 +806,8 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -816,30 +816,30 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 19, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9: cond.true: // CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: br label [[COND_END]] // CHECK9: cond.end: // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: @@ -1056,8 +1056,8 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 @@ -1099,15 +1099,15 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] // CHECK11: omp.precond.then: -// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB]], align 8 +// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_COMB_UB]], align 8 +// CHECK11-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_UB]], align 8 // CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] @@ -1115,17 +1115,17 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 // CHECK11-NEXT: br label [[COND_END:%.*]] // CHECK11: cond.false: -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 // CHECK11-NEXT: br label [[COND_END]] // CHECK11: cond.end: // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 +// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 +// CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK11-NEXT: store i64 [[TMP18]], ptr [[DOTOMP_IV]], align 8 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: // CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// CHECK11-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: @@ -1259,8 +1259,8 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1269,30 +1269,30 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: store i32 19, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK11-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK11: cond.true: // CHECK11-NEXT: br label [[COND_END:%.*]] // CHECK11: cond.false: -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: br label [[COND_END]] // CHECK11: cond.end: // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: diff --git a/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp b/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp index f892dad0f69ba..9a24c19492aa7 100644 --- a/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp +++ b/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp @@ -313,8 +313,8 @@ int main() { // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 @@ -325,8 +325,8 @@ int main() { // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 @@ -342,24 +342,24 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: @@ -517,8 +517,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 @@ -530,8 +530,8 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 @@ -548,24 +548,24 @@ int main() { // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: @@ -840,8 +840,8 @@ int main() { // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 @@ -852,8 +852,8 @@ int main() { // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 @@ -869,24 +869,24 @@ int main() { // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: @@ -1042,8 +1042,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 @@ -1055,8 +1055,8 @@ int main() { // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 @@ -1073,24 +1073,24 @@ int main() { // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: @@ -1334,8 +1334,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 @@ -1347,31 +1347,31 @@ int main() { // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9: cond.true: // CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9: cond.false: -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: br label [[COND_END]] // CHECK9: cond.end: // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: diff --git a/clang/test/OpenMP/teams_generic_loop_reduction_codegen.cpp b/clang/test/OpenMP/teams_generic_loop_reduction_codegen.cpp index 6c2e5f8fa5700..12181f88ef38e 100644 --- a/clang/test/OpenMP/teams_generic_loop_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_generic_loop_reduction_codegen.cpp @@ -98,80 +98,118 @@ int main() { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK1-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK1-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK1-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK1-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK1-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i64 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]]) +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -179,72 +217,74 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] +// CHECK1-NEXT: store i32 0, ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1: omp.inner.for.body: +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[SIVAR1]], ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[SIVAR2]], ptr [[TMP14]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP18]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void @@ -276,9 +316,9 @@ int main() { // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -286,70 +326,108 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK1-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK1-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK1-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK1-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK1-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK1-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK1-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -357,72 +435,74 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1: omp.inner.for.body: +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP14]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP18]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void @@ -453,80 +533,118 @@ int main() { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP11]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK3-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK3-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK3-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK3-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK3-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i32 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]]) +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -534,72 +652,74 @@ int main() { // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] +// CHECK3-NEXT: store i32 0, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[SIVAR2]], ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP18]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void @@ -631,9 +751,9 @@ int main() { // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -641,70 +761,108 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP11]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK3-NEXT: [[TEAM_PROCS:%.*]] = call i32 @ompx_get_team_procs(i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP2:%.*]] = zext i32 [[TEAM_PROCS]] to i64 +// CHECK3-NEXT: [[TMP3:%.*]] = mul i64 4, [[TMP2]] +// CHECK3-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK3-NEXT: [[D_TEAM_VALS_SZ:%.*]] = mul i64 4, [[TMP3]] +// CHECK3-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 [[D_TEAM_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR2:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR2]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[D_TEAMS_DONE_PTR2]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 2, ptr [[TMP15]], align 8 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 -// CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 2, ptr [[TMP24]], align 8 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 +// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4 +// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 +// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV]]) +// CHECK3-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR2]], i32 [[DEFAULT_DEV]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK3-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -712,72 +870,74 @@ int main() { // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK3-NEXT: store i32 0, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK3: cond.true: // CHECK3-NEXT: br label [[COND_END:%.*]] // CHECK3: cond.false: -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: br label [[COND_END]] // CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] +// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[T_VAR2]], ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR2]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP2]], i32 [[TMP18]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void @@ -831,8 +991,8 @@ int main() { // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -841,32 +1001,32 @@ int main() { // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK9-NEXT: store i32 0, ptr [[SIVAR1]], align 4 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK9: cond.true: // CHECK9-NEXT: br label [[COND_END:%.*]] // CHECK9: cond.false: -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: br label [[COND_END]] // CHECK9: cond.end: // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: diff --git a/clang/test/OpenMP/thread_limit_amdgpu.c b/clang/test/OpenMP/thread_limit_amdgpu.c index f884eeb73c3ff..9ffc029b21a6b 100644 --- a/clang/test/OpenMP/thread_limit_amdgpu.c +++ b/clang/test/OpenMP/thread_limit_amdgpu.c @@ -30,5 +30,4 @@ void foo(int N) { // CHECK: attributes #[[ATTR1]] = { {{.*}} "amdgpu-flat-work-group-size"="1,256" {{.*}} } // CHECK: attributes #[[ATTR2]] = { {{.*}} "amdgpu-flat-work-group-size"="1,4" {{.*}} } -// CHECK: attributes #[[ATTR3]] = { {{.*}} "amdgpu-flat-work-group-size"="1,42" "amdgpu-max-num-workgroups"="42,1,1"{{.*}} } -// CHECK: attributes #[[ATTR4]] = { {{.*}} "amdgpu-flat-work-group-size"="1,22" "amdgpu-max-num-workgroups"="42,1,1"{{.*}} } +// CHECK: attributes #[[ATTR4]] = { {{.*}} "amdgpu-flat-work-group-size"="1,22" diff --git a/clang/test/OpenMP/thread_limit_nvptx.c b/clang/test/OpenMP/thread_limit_nvptx.c index ffa6c453067d1..4d71324e8c3a3 100644 --- a/clang/test/OpenMP/thread_limit_nvptx.c +++ b/clang/test/OpenMP/thread_limit_nvptx.c @@ -1,5 +1,5 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test target codegen - host bc file has to be created first. -// // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s // expected-no-diagnostics @@ -7,21 +7,17 @@ #define HEADER void foo(int N) { -// CHECK: define {{.*}}l11{{.*}} #[[ATTR0:[0-9]+]] #pragma omp target teams distribute parallel for simd for (int i = 0; i < N; ++i) ; -// CHECK: define {{.*}}l15{{.*}} #[[ATTR1:[0-9]+]] #pragma omp target teams distribute parallel for simd thread_limit(4) for (int i = 0; i < N; ++i) ; - -// CHECK: define {{.*}}l20{{.*}} #[[ATTR2:[0-9]+]] +// TODO: We should not emit two maxntidx annotations. #pragma omp target teams distribute parallel for simd ompx_attribute(__attribute__((launch_bounds(42, 42)))) for (int i = 0; i < N; ++i) ; - -// CHECK: define {{.*}}l25{{.*}} #[[ATTR3:[0-9]+]] +// TODO: We should not emit two maxntidx annotations. #pragma omp target teams distribute parallel for simd ompx_attribute(__attribute__((launch_bounds(42, 42)))) num_threads(22) for (int i = 0; i < N; ++i) ; @@ -29,7 +25,1018 @@ void foo(int N) { #endif -// CHECK: attributes #[[ATTR0]] = {{{.*}} "nvvm.maxntid"="128" {{.*}}} -// CHECK: attributes #[[ATTR1]] = {{{.*}} "nvvm.maxntid"="4" {{.*}}} -// CHECK: attributes #[[ATTR2]] = {{{.*}} "nvvm.maxntid"="42" {{.*}}} -// CHECK: attributes #[[ATTR3]] = {{{.*}} "nvvm.maxntid"="22" {{.*}}} +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l10 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l10_kernel_environment, ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l10_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2:[0-9]+]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l10_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK: omp.precond.then: +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]] +// CHECK-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]] +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[ADD]] +// CHECK-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: store i32 [[TMP15]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK-NEXT: [[TMP18:%.*]] = inttoptr i32 [[TMP13]] to ptr +// CHECK-NEXT: store ptr [[TMP18]], ptr [[TMP17]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP14]] to ptr +// CHECK-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP16]] to ptr +// CHECK-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP24]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l10_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3), !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] +// CHECK-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP31]], [[TMP32]] +// CHECK-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK: cond.true10: +// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: br label [[COND_END12:%.*]] +// CHECK: cond.false11: +// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: br label [[COND_END12]] +// CHECK: cond.end12: +// CHECK-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP33]], [[COND_TRUE10]] ], [ [[TMP34]], [[COND_FALSE11]] ] +// CHECK-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP37]]) +// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 +// CHECK-NEXT: br i1 [[TMP39]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK: .omp.final.then: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP40]], 0 +// CHECK-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV15]], 1 +// CHECK-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD16]], ptr [[I3]], align 4 +// CHECK-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK: .omp.final.done: +// CHECK-NEXT: br label [[OMP_PRECOND_END]] +// CHECK: omp.precond.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l10_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 +// CHECK-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK: omp.precond.then: +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP7]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP15]]) +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK: .omp.final.then: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP18]], 0 +// CHECK-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1 +// CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] +// CHECK-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4 +// CHECK-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK: .omp.final.done: +// CHECK-NEXT: br label [[OMP_PRECOND_END]] +// CHECK: omp.precond.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l13 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l13_kernel_environment, ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l13_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l13_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK: omp.precond.then: +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]] +// CHECK-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[ADD]] +// CHECK-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: store i32 [[TMP15]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK-NEXT: [[TMP18:%.*]] = inttoptr i32 [[TMP13]] to ptr +// CHECK-NEXT: store ptr [[TMP18]], ptr [[TMP17]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP14]] to ptr +// CHECK-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP16]] to ptr +// CHECK-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP24]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l13_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3), !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] +// CHECK-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP31]], [[TMP32]] +// CHECK-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK: cond.true10: +// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: br label [[COND_END12:%.*]] +// CHECK: cond.false11: +// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: br label [[COND_END12]] +// CHECK: cond.end12: +// CHECK-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP33]], [[COND_TRUE10]] ], [ [[TMP34]], [[COND_FALSE11]] ] +// CHECK-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP37]]) +// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 +// CHECK-NEXT: br i1 [[TMP39]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK: .omp.final.then: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP40]], 0 +// CHECK-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV15]], 1 +// CHECK-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD16]], ptr [[I3]], align 4 +// CHECK-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK: .omp.final.done: +// CHECK-NEXT: br label [[OMP_PRECOND_END]] +// CHECK: omp.precond.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l13_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 +// CHECK-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK: omp.precond.then: +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP7]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP15]]) +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK: .omp.final.then: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP18]], 0 +// CHECK-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1 +// CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] +// CHECK-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4 +// CHECK-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK: .omp.final.done: +// CHECK-NEXT: br label [[OMP_PRECOND_END]] +// CHECK: omp.precond.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l17 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l17_kernel_environment, ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l17_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l17_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK: omp.precond.then: +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]] +// CHECK-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[ADD]] +// CHECK-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: store i32 [[TMP15]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK-NEXT: [[TMP18:%.*]] = inttoptr i32 [[TMP13]] to ptr +// CHECK-NEXT: store ptr [[TMP18]], ptr [[TMP17]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP14]] to ptr +// CHECK-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP16]] to ptr +// CHECK-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP24]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l17_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3), !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] +// CHECK-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP31]], [[TMP32]] +// CHECK-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK: cond.true10: +// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: br label [[COND_END12:%.*]] +// CHECK: cond.false11: +// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: br label [[COND_END12]] +// CHECK: cond.end12: +// CHECK-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP33]], [[COND_TRUE10]] ], [ [[TMP34]], [[COND_FALSE11]] ] +// CHECK-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP37]]) +// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 +// CHECK-NEXT: br i1 [[TMP39]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK: .omp.final.then: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP40]], 0 +// CHECK-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV15]], 1 +// CHECK-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD16]], ptr [[I3]], align 4 +// CHECK-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK: .omp.final.done: +// CHECK-NEXT: br label [[OMP_PRECOND_END]] +// CHECK: omp.precond.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l17_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 +// CHECK-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK: omp.precond.then: +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP7]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP15]]) +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK: .omp.final.then: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP18]], 0 +// CHECK-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1 +// CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] +// CHECK-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4 +// CHECK-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK: .omp.final.done: +// CHECK-NEXT: br label [[OMP_PRECOND_END]] +// CHECK: omp.precond.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l21 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l21_kernel_environment, ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l21_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l21_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK: omp.precond.then: +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]] +// CHECK-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[ADD]] +// CHECK-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: store i32 [[TMP15]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 +// CHECK-NEXT: [[TMP18:%.*]] = inttoptr i32 [[TMP13]] to ptr +// CHECK-NEXT: store ptr [[TMP18]], ptr [[TMP17]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 +// CHECK-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP14]] to ptr +// CHECK-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 +// CHECK-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP16]] to ptr +// CHECK-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP24]], i32 1, i32 22, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l21_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3), !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// CHECK-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] +// CHECK-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP31]], [[TMP32]] +// CHECK-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK: cond.true10: +// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: br label [[COND_END12:%.*]] +// CHECK: cond.false11: +// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: br label [[COND_END12]] +// CHECK: cond.end12: +// CHECK-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP33]], [[COND_TRUE10]] ], [ [[TMP34]], [[COND_FALSE11]] ] +// CHECK-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP37]]) +// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 +// CHECK-NEXT: br i1 [[TMP39]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK: .omp.final.then: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP40]], 0 +// CHECK-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV15]], 1 +// CHECK-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD16]], ptr [[I3]], align 4 +// CHECK-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK: .omp.final.done: +// CHECK-NEXT: br label [[OMP_PRECOND_END]] +// CHECK: omp.precond.end: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l21_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I3:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 +// CHECK-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK: omp.precond.then: +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP7]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP15]]) +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 +// CHECK-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] +// CHECK: .omp.final.then: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP18]], 0 +// CHECK-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// CHECK-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1 +// CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] +// CHECK-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4 +// CHECK-NEXT: br label [[DOTOMP_FINAL_DONE]] +// CHECK: .omp.final.done: +// CHECK-NEXT: br label [[OMP_PRECOND_END]] +// CHECK: omp.precond.end: +// CHECK-NEXT: ret void +// diff --git a/clang/test/OpenMP/xteam_red_callee.cpp b/clang/test/OpenMP/xteam_red_callee.cpp new file mode 100644 index 0000000000000..455b041da3084 --- /dev/null +++ b/clang/test/OpenMP/xteam_red_callee.cpp @@ -0,0 +1,2502 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-ignore-env-vars -fopenmp-assume-no-nested-parallelism -fopenmp-assume-no-thread-state -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-ignore-env-vars -fopenmp-assume-no-nested-parallelism -fopenmp-assume-no-thread-state -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// expected-no-diagnostics + +int compute_sum_res(int j, double &result, double a[]) { + result += a[j]; + return 1; +} + +void compute_sum(int j, double &result, double a[]) { + result += a[j]; +} + +double compute_sum_rval(int j, double rval, double a[]) { + return rval + a[j]; +} + +int foo(int i) { return 2*i; } + +int main() +{ + int N = 10000; + + double a[N]; + + for (int i=0; i + +int main() +{ + int N = 100; + + double a[N], b[N]; + int bint[N]; + unsigned cint[N]; + + int8_t int8_sum = 0; + int16_t int16_sum = 0; + int32_t int32_sum = 0; + uint32_t uint32_sum = 0; + int64_t int64_sum = 0; + uint64_t uint64_sum = 0; + + for (int i=0; i + +int main() +{ + int N = 100; + + double a[N]; + uint32_t b[N]; + float c[N]; + uint64_t d[N]; + + for (int i=0; i +void compute_min_max() { + T min_t = 1000; + T max_t = 0; + T *arr_t = new T[N]; + for (int i = 0; i < N; i++) + arr_t[i] = i; +#pragma omp target data map(to : arr_t[0 : N]) + { +#pragma omp target teams distribute parallel for reduction(min : min_t) + for (int j = 0; j < N; j = j + 1) + min_t = __builtin_fmin(min_t, arr_t[j]); + +#pragma omp target teams distribute parallel for reduction(max : max_t) + for (int j = 0; j < N; j = j + 1) + max_t = __builtin_fmax(max_t, arr_t[j]); + } + delete[] arr_t; +} + +int main() +{ + compute_min_max(); + compute_min_max(); + compute_min_max(); + compute_min_max(); + compute_min_max(); + compute_min_max(); + compute_min_max(); + compute_min_max(); +} + +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIsEvv_l17 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: store i16 32767, ptr addrspace(5) [[TMP3]], align 2 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP5]] +// CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 +// CHECK-NEXT: [[CONV:%.*]] = sitofp i16 [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load i16, ptr addrspace(5) [[TMP3]], align 2 +// CHECK-NEXT: [[TMP20:%.*]] = fptosi double [[CONV]] to i16 +// CHECK-NEXT: [[XTEAM_MIN:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP19]], i16 [[TMP20]]) +// CHECK-NEXT: store i16 [[XTEAM_MIN]], ptr addrspace(5) [[TMP3]], align 2 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP11]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load i16, ptr addrspace(5) [[TMP3]], align 2 +// CHECK-NEXT: call void @__kmpc_xteamr_s_16x64(i16 [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_min_s, ptr @__kmpc_rfun_min_lds_s, i16 32767, i64 [[TMP12]], i32 [[TMP11]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIsEvv_l21 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: store i16 -32768, ptr addrspace(5) [[TMP3]], align 2 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP5]] +// CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 +// CHECK-NEXT: [[CONV:%.*]] = sitofp i16 [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load i16, ptr addrspace(5) [[TMP3]], align 2 +// CHECK-NEXT: [[TMP20:%.*]] = fptosi double [[CONV]] to i16 +// CHECK-NEXT: [[XTEAM_MAX:%.*]] = call i16 @llvm.smax.i16(i16 [[TMP19]], i16 [[TMP20]]) +// CHECK-NEXT: store i16 [[XTEAM_MAX]], ptr addrspace(5) [[TMP3]], align 2 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP11]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load i16, ptr addrspace(5) [[TMP3]], align 2 +// CHECK-NEXT: call void @__kmpc_xteamr_s_16x64(i16 [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_max_s, ptr @__kmpc_rfun_max_lds_s, i16 -32768, i64 [[TMP12]], i32 [[TMP11]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l17 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l17_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l17_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP0]], ptr [[TMP3]]) #[[ATTR1:[0-9]+]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l17_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T1]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 -1, ptr [[MIN_T1_ASCAST]], align 2 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 1000 +// CHECK-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP8]] to ptr +// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP10]] to ptr +// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: store ptr [[MIN_T1_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8 +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l17_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4) +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 999 +// CHECK-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK: cond.true6: +// CHECK-NEXT: br label [[COND_END8:%.*]] +// CHECK: cond.false7: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END8]] +// CHECK: cond.end8: +// CHECK-NEXT: [[COND9:%.*]] = phi i32 [ 999, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ] +// CHECK-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]]) +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MIN_T1_ASCAST]], ptr [[TMP27]], align 8 +// CHECK-NEXT: %"_openmp_teams_reductions_buffer_$_$ptr" = call ptr @__kmpc_reduction_get_fixed_buffer() +// CHECK-NEXT: [[TMP28:%.*]] = call i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), ptr %"_openmp_teams_reductions_buffer_$_$ptr", i32 1024, i64 2, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.1, ptr @_omp_reduction_inter_warp_copy_func.2, ptr @_omp_reduction_list_to_global_copy_func, ptr @_omp_reduction_list_to_global_reduce_func, ptr @_omp_reduction_global_to_list_copy_func, ptr @_omp_reduction_global_to_list_reduce_func) +// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i32 [[TMP28]], 1 +// CHECK-NEXT: br i1 [[TMP29]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP30:%.*]] = load i16, ptr [[TMP0]], align 2 +// CHECK-NEXT: [[CONV:%.*]] = zext i16 [[TMP30]] to i32 +// CHECK-NEXT: [[TMP31:%.*]] = load i16, ptr [[MIN_T1_ASCAST]], align 2 +// CHECK-NEXT: [[CONV10:%.*]] = zext i16 [[TMP31]] to i32 +// CHECK-NEXT: [[CMP11:%.*]] = icmp slt i32 [[CONV]], [[CONV10]] +// CHECK-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] +// CHECK: cond.true12: +// CHECK-NEXT: [[TMP32:%.*]] = load i16, ptr [[TMP0]], align 2 +// CHECK-NEXT: br label [[COND_END14:%.*]] +// CHECK: cond.false13: +// CHECK-NEXT: [[TMP33:%.*]] = load i16, ptr [[MIN_T1_ASCAST]], align 2 +// CHECK-NEXT: br label [[COND_END14]] +// CHECK: cond.end14: +// CHECK-NEXT: [[COND15:%.*]] = phi i16 [ [[TMP32]], [[COND_TRUE12]] ], [ [[TMP33]], [[COND_FALSE13]] ] +// CHECK-NEXT: store i16 [[COND15]], ptr [[TMP0]], align 2 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l17_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[MIN_T2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[MIN_T2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T2]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: store i16 -1, ptr [[MIN_T2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = load i16, ptr [[MIN_T2_ASCAST]], align 2 +// CHECK-NEXT: [[CONV4:%.*]] = uitofp i16 [[TMP9]] to double +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP10]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 +// CHECK-NEXT: [[CONV5:%.*]] = uitofp i16 [[TMP12]] to double +// CHECK-NEXT: [[TMP13:%.*]] = call double @llvm.minnum.f64(double [[CONV4]], double [[CONV5]]) +// CHECK-NEXT: [[CONV6:%.*]] = fptoui double [[TMP13]] to i16 +// CHECK-NEXT: store i16 [[CONV6]], ptr [[MIN_T2_ASCAST]], align 2 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]]) +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MIN_T2_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i64 2, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func, ptr @_omp_reduction_inter_warp_copy_func) +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 1 +// CHECK-NEXT: br i1 [[TMP18]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP19:%.*]] = load i16, ptr [[TMP0]], align 2 +// CHECK-NEXT: [[CONV8:%.*]] = zext i16 [[TMP19]] to i32 +// CHECK-NEXT: [[TMP20:%.*]] = load i16, ptr [[MIN_T2_ASCAST]], align 2 +// CHECK-NEXT: [[CONV9:%.*]] = zext i16 [[TMP20]] to i32 +// CHECK-NEXT: [[CMP10:%.*]] = icmp slt i32 [[CONV8]], [[CONV9]] +// CHECK-NEXT: br i1 [[CMP10]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP21:%.*]] = load i16, ptr [[TMP0]], align 2 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP22:%.*]] = load i16, ptr [[MIN_T2_ASCAST]], align 2 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i16 [ [[TMP21]], [[COND_TRUE]] ], [ [[TMP22]], [[COND_FALSE]] ] +// CHECK-NEXT: store i16 [[COND]], ptr [[TMP0]], align 2 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i16, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[TMP9]], align 2 +// CHECK-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32 +// CHECK-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP15:%.*]] = trunc i32 [[TMP14]] to i16 +// CHECK-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP13]], i16 [[TMP6]], i16 [[TMP15]]) +// CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16 +// CHECK-NEXT: store i16 [[TMP17]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 2 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr i16, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr i16, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP21:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP22:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP23:%.*]] = and i1 [[TMP21]], [[TMP22]] +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP25:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i16 [[TMP25]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP24]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP29:%.*]] = and i1 [[TMP27]], [[TMP28]] +// CHECK-NEXT: [[TMP30:%.*]] = or i1 [[TMP20]], [[TMP23]] +// CHECK-NEXT: [[TMP31:%.*]] = or i1 [[TMP30]], [[TMP29]] +// CHECK-NEXT: br i1 [[TMP31]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l17_omp_outlined_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP33:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP34]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[TMP37]], align 8 +// CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[TMP36]], align 2 +// CHECK-NEXT: store i16 [[TMP39]], ptr [[TMP38]], align 2 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4:[0-9]+]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP7]], align 2 +// CHECK-NEXT: store volatile i16 [[TMP9]], ptr addrspace(3) [[TMP8]], align 2 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i16, ptr addrspace(3) [[TMP11]], align 2 +// CHECK-NEXT: store i16 [[TMP14]], ptr [[TMP13]], align 2 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.1 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i16, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[TMP9]], align 2 +// CHECK-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32 +// CHECK-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP15:%.*]] = trunc i32 [[TMP14]] to i16 +// CHECK-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP13]], i16 [[TMP6]], i16 [[TMP15]]) +// CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16 +// CHECK-NEXT: store i16 [[TMP17]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 2 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr i16, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr i16, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP21:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP22:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP23:%.*]] = and i1 [[TMP21]], [[TMP22]] +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP25:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i16 [[TMP25]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP24]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP29:%.*]] = and i1 [[TMP27]], [[TMP28]] +// CHECK-NEXT: [[TMP30:%.*]] = or i1 [[TMP20]], [[TMP23]] +// CHECK-NEXT: [[TMP31:%.*]] = or i1 [[TMP30]], [[TMP29]] +// CHECK-NEXT: br i1 [[TMP31]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l17_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP33:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP34]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[TMP37]], align 8 +// CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[TMP36]], align 2 +// CHECK-NEXT: store i16 [[TMP39]], ptr [[TMP38]], align 2 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.2 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP7]], align 2 +// CHECK-NEXT: store volatile i16 [[TMP9]], ptr addrspace(3) [[TMP8]], align 2 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i16, ptr addrspace(3) [[TMP11]], align 2 +// CHECK-NEXT: store i16 [[TMP14]], ptr [[TMP13]], align 2 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP7]], align 2 +// CHECK-NEXT: store i16 [[TMP10]], ptr [[TMP9]], align 2 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l17_omp_outlined_omp$reduction$reduction_func"(ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr [[TMP8]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 2 +// CHECK-NEXT: store i16 [[TMP10]], ptr [[TMP7]], align 2 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l17_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP8]], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l21 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR3]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l21_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l21_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP0]], ptr [[TMP3]]) #[[ATTR1]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l21_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T1]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 0, ptr [[MAX_T1_ASCAST]], align 2 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 1000 +// CHECK-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP8]] to ptr +// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP10]] to ptr +// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: store ptr [[MAX_T1_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8 +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l21_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4) +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 999 +// CHECK-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK: cond.true6: +// CHECK-NEXT: br label [[COND_END8:%.*]] +// CHECK: cond.false7: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END8]] +// CHECK: cond.end8: +// CHECK-NEXT: [[COND9:%.*]] = phi i32 [ 999, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ] +// CHECK-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]]) +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MAX_T1_ASCAST]], ptr [[TMP27]], align 8 +// CHECK-NEXT: %"_openmp_teams_reductions_buffer_$_$ptr" = call ptr @__kmpc_reduction_get_fixed_buffer() +// CHECK-NEXT: [[TMP28:%.*]] = call i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), ptr %"_openmp_teams_reductions_buffer_$_$ptr", i32 1024, i64 2, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.5, ptr @_omp_reduction_inter_warp_copy_func.6, ptr @_omp_reduction_list_to_global_copy_func.7, ptr @_omp_reduction_list_to_global_reduce_func.8, ptr @_omp_reduction_global_to_list_copy_func.9, ptr @_omp_reduction_global_to_list_reduce_func.10) +// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i32 [[TMP28]], 1 +// CHECK-NEXT: br i1 [[TMP29]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP30:%.*]] = load i16, ptr [[TMP0]], align 2 +// CHECK-NEXT: [[CONV:%.*]] = zext i16 [[TMP30]] to i32 +// CHECK-NEXT: [[TMP31:%.*]] = load i16, ptr [[MAX_T1_ASCAST]], align 2 +// CHECK-NEXT: [[CONV10:%.*]] = zext i16 [[TMP31]] to i32 +// CHECK-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[CONV]], [[CONV10]] +// CHECK-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] +// CHECK: cond.true12: +// CHECK-NEXT: [[TMP32:%.*]] = load i16, ptr [[TMP0]], align 2 +// CHECK-NEXT: br label [[COND_END14:%.*]] +// CHECK: cond.false13: +// CHECK-NEXT: [[TMP33:%.*]] = load i16, ptr [[MAX_T1_ASCAST]], align 2 +// CHECK-NEXT: br label [[COND_END14]] +// CHECK: cond.end14: +// CHECK-NEXT: [[COND15:%.*]] = phi i16 [ [[TMP32]], [[COND_TRUE12]] ], [ [[TMP33]], [[COND_FALSE13]] ] +// CHECK-NEXT: store i16 [[COND15]], ptr [[TMP0]], align 2 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l21_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[MAX_T2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[MAX_T2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T2]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: store i16 0, ptr [[MAX_T2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = load i16, ptr [[MAX_T2_ASCAST]], align 2 +// CHECK-NEXT: [[CONV4:%.*]] = uitofp i16 [[TMP9]] to double +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP10]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 +// CHECK-NEXT: [[CONV5:%.*]] = uitofp i16 [[TMP12]] to double +// CHECK-NEXT: [[TMP13:%.*]] = call double @llvm.maxnum.f64(double [[CONV4]], double [[CONV5]]) +// CHECK-NEXT: [[CONV6:%.*]] = fptoui double [[TMP13]] to i16 +// CHECK-NEXT: store i16 [[CONV6]], ptr [[MAX_T2_ASCAST]], align 2 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]]) +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MAX_T2_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i64 2, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.3, ptr @_omp_reduction_inter_warp_copy_func.4) +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 1 +// CHECK-NEXT: br i1 [[TMP18]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP19:%.*]] = load i16, ptr [[TMP0]], align 2 +// CHECK-NEXT: [[CONV8:%.*]] = zext i16 [[TMP19]] to i32 +// CHECK-NEXT: [[TMP20:%.*]] = load i16, ptr [[MAX_T2_ASCAST]], align 2 +// CHECK-NEXT: [[CONV9:%.*]] = zext i16 [[TMP20]] to i32 +// CHECK-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV8]], [[CONV9]] +// CHECK-NEXT: br i1 [[CMP10]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP21:%.*]] = load i16, ptr [[TMP0]], align 2 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP22:%.*]] = load i16, ptr [[MAX_T2_ASCAST]], align 2 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i16 [ [[TMP21]], [[COND_TRUE]] ], [ [[TMP22]], [[COND_FALSE]] ] +// CHECK-NEXT: store i16 [[COND]], ptr [[TMP0]], align 2 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.3 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i16, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[TMP9]], align 2 +// CHECK-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32 +// CHECK-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP15:%.*]] = trunc i32 [[TMP14]] to i16 +// CHECK-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP13]], i16 [[TMP6]], i16 [[TMP15]]) +// CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16 +// CHECK-NEXT: store i16 [[TMP17]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 2 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr i16, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr i16, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP21:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP22:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP23:%.*]] = and i1 [[TMP21]], [[TMP22]] +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP25:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i16 [[TMP25]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP24]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP29:%.*]] = and i1 [[TMP27]], [[TMP28]] +// CHECK-NEXT: [[TMP30:%.*]] = or i1 [[TMP20]], [[TMP23]] +// CHECK-NEXT: [[TMP31:%.*]] = or i1 [[TMP30]], [[TMP29]] +// CHECK-NEXT: br i1 [[TMP31]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l21_omp_outlined_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP33:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP34]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[TMP37]], align 8 +// CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[TMP36]], align 2 +// CHECK-NEXT: store i16 [[TMP39]], ptr [[TMP38]], align 2 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.4 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP7]], align 2 +// CHECK-NEXT: store volatile i16 [[TMP9]], ptr addrspace(3) [[TMP8]], align 2 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i16, ptr addrspace(3) [[TMP11]], align 2 +// CHECK-NEXT: store i16 [[TMP14]], ptr [[TMP13]], align 2 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.5 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i16, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[TMP9]], align 2 +// CHECK-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32 +// CHECK-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP15:%.*]] = trunc i32 [[TMP14]] to i16 +// CHECK-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP13]], i16 [[TMP6]], i16 [[TMP15]]) +// CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16 +// CHECK-NEXT: store i16 [[TMP17]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 2 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr i16, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr i16, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP21:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP22:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP23:%.*]] = and i1 [[TMP21]], [[TMP22]] +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP25:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i16 [[TMP25]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP24]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP29:%.*]] = and i1 [[TMP27]], [[TMP28]] +// CHECK-NEXT: [[TMP30:%.*]] = or i1 [[TMP20]], [[TMP23]] +// CHECK-NEXT: [[TMP31:%.*]] = or i1 [[TMP30]], [[TMP29]] +// CHECK-NEXT: br i1 [[TMP31]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l21_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP33:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP34]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[TMP37]], align 8 +// CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[TMP36]], align 2 +// CHECK-NEXT: store i16 [[TMP39]], ptr [[TMP38]], align 2 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.6 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP7]], align 2 +// CHECK-NEXT: store volatile i16 [[TMP9]], ptr addrspace(3) [[TMP8]], align 2 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i16, ptr addrspace(3) [[TMP11]], align 2 +// CHECK-NEXT: store i16 [[TMP14]], ptr [[TMP13]], align 2 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func.7 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_1:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_1]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP7]], align 2 +// CHECK-NEXT: store i16 [[TMP10]], ptr [[TMP9]], align 2 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func.8 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_1:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_1]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l21_omp_outlined_omp$reduction$reduction_func"(ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr [[TMP8]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func.9 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_1:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_1]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 2 +// CHECK-NEXT: store i16 [[TMP10]], ptr [[TMP7]], align 2 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func.10 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_1:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_1]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxItEvv_l21_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP8]], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIiEvv_l17 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 2147483647, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP5]] +// CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = fptosi double [[CONV]] to i32 +// CHECK-NEXT: [[XTEAM_MIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP19]], i32 [[TMP20]]) +// CHECK-NEXT: store i32 [[XTEAM_MIN]], ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP11]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_xteamr_i_16x64(i32 [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_min_i, ptr @__kmpc_rfun_min_lds_i, i32 2147483647, i64 [[TMP12]], i32 [[TMP11]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIiEvv_l21 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 -2147483648, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP5]] +// CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = fptosi double [[CONV]] to i32 +// CHECK-NEXT: [[XTEAM_MAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP19]], i32 [[TMP20]]) +// CHECK-NEXT: store i32 [[XTEAM_MAX]], ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP11]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_xteamr_i_16x64(i32 [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_max_i, ptr @__kmpc_rfun_max_lds_i, i32 -2147483648, i64 [[TMP12]], i32 [[TMP11]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l17 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR3]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l17_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l17_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP0]], ptr [[TMP3]]) #[[ATTR1]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l17_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T1]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 -1, ptr [[MIN_T1_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 1000 +// CHECK-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP8]] to ptr +// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP10]] to ptr +// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: store ptr [[MIN_T1_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8 +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l17_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4) +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 999 +// CHECK-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK: cond.true6: +// CHECK-NEXT: br label [[COND_END8:%.*]] +// CHECK: cond.false7: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END8]] +// CHECK: cond.end8: +// CHECK-NEXT: [[COND9:%.*]] = phi i32 [ 999, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ] +// CHECK-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]]) +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MIN_T1_ASCAST]], ptr [[TMP27]], align 8 +// CHECK-NEXT: %"_openmp_teams_reductions_buffer_$_$ptr" = call ptr @__kmpc_reduction_get_fixed_buffer() +// CHECK-NEXT: [[TMP28:%.*]] = call i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), ptr %"_openmp_teams_reductions_buffer_$_$ptr", i32 1024, i64 4, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.13, ptr @_omp_reduction_inter_warp_copy_func.14, ptr @_omp_reduction_list_to_global_copy_func.15, ptr @_omp_reduction_list_to_global_reduce_func.16, ptr @_omp_reduction_global_to_list_copy_func.17, ptr @_omp_reduction_global_to_list_reduce_func.18) +// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i32 [[TMP28]], 1 +// CHECK-NEXT: br i1 [[TMP29]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[MIN_T1_ASCAST]], align 4 +// CHECK-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK: cond.true11: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[COND_END13:%.*]] +// CHECK: cond.false12: +// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[MIN_T1_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END13]] +// CHECK: cond.end13: +// CHECK-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE11]] ], [ [[TMP33]], [[COND_FALSE12]] ] +// CHECK-NEXT: store i32 [[COND14]], ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l17_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[MIN_T2:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[MIN_T2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T2]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: store i32 -1, ptr [[MIN_T2_ASCAST]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[MIN_T2_ASCAST]], align 4 +// CHECK-NEXT: [[CONV4:%.*]] = uitofp i32 [[TMP9]] to double +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[CONV5:%.*]] = uitofp i32 [[TMP12]] to double +// CHECK-NEXT: [[TMP13:%.*]] = call double @llvm.minnum.f64(double [[CONV4]], double [[CONV5]]) +// CHECK-NEXT: [[CONV6:%.*]] = fptoui double [[TMP13]] to i32 +// CHECK-NEXT: store i32 [[CONV6]], ptr [[MIN_T2_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]]) +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MIN_T2_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i64 4, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.11, ptr @_omp_reduction_inter_warp_copy_func.12) +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 1 +// CHECK-NEXT: br i1 [[TMP18]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[MIN_T2_ASCAST]], align 4 +// CHECK-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP19]], [[TMP20]] +// CHECK-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[MIN_T2_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP21]], [[COND_TRUE]] ], [ [[TMP22]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.11 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP19:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]] +// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP23:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP23]], 0 +// CHECK-NEXT: [[TMP25:%.*]] = and i1 [[TMP22]], [[TMP24]] +// CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = or i1 [[TMP18]], [[TMP21]] +// CHECK-NEXT: [[TMP29:%.*]] = or i1 [[TMP28]], [[TMP27]] +// CHECK-NEXT: br i1 [[TMP29]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l17_omp_outlined_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP31:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[TMP32]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8 +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP34]], align 4 +// CHECK-NEXT: store i32 [[TMP37]], ptr [[TMP36]], align 4 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.12 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP9]], ptr addrspace(3) [[TMP8]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i32, ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.13 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP19:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]] +// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP23:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP23]], 0 +// CHECK-NEXT: [[TMP25:%.*]] = and i1 [[TMP22]], [[TMP24]] +// CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = or i1 [[TMP18]], [[TMP21]] +// CHECK-NEXT: [[TMP29:%.*]] = or i1 [[TMP28]], [[TMP27]] +// CHECK-NEXT: br i1 [[TMP29]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l17_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP31:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[TMP32]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8 +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP34]], align 4 +// CHECK-NEXT: store i32 [[TMP37]], ptr [[TMP36]], align 4 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.14 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP9]], ptr addrspace(3) [[TMP8]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i32, ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func.15 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_4:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_4]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func.16 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_4:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_4]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l17_omp_outlined_omp$reduction$reduction_func"(ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr [[TMP8]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func.17 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_4:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_4]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[TMP7]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func.18 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_4:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_4]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l17_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP8]], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l21 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR3]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l21_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l21_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP0]], ptr [[TMP3]]) #[[ATTR1]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l21_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T1]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[MAX_T1_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 1000 +// CHECK-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP8]] to ptr +// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP10]] to ptr +// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: store ptr [[MAX_T1_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8 +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l21_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4) +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 999 +// CHECK-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK: cond.true6: +// CHECK-NEXT: br label [[COND_END8:%.*]] +// CHECK: cond.false7: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END8]] +// CHECK: cond.end8: +// CHECK-NEXT: [[COND9:%.*]] = phi i32 [ 999, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ] +// CHECK-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]]) +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MAX_T1_ASCAST]], ptr [[TMP27]], align 8 +// CHECK-NEXT: %"_openmp_teams_reductions_buffer_$_$ptr" = call ptr @__kmpc_reduction_get_fixed_buffer() +// CHECK-NEXT: [[TMP28:%.*]] = call i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), ptr %"_openmp_teams_reductions_buffer_$_$ptr", i32 1024, i64 4, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.21, ptr @_omp_reduction_inter_warp_copy_func.22, ptr @_omp_reduction_list_to_global_copy_func.23, ptr @_omp_reduction_list_to_global_reduce_func.24, ptr @_omp_reduction_global_to_list_copy_func.25, ptr @_omp_reduction_global_to_list_reduce_func.26) +// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i32 [[TMP28]], 1 +// CHECK-NEXT: br i1 [[TMP29]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[MAX_T1_ASCAST]], align 4 +// CHECK-NEXT: [[CMP10:%.*]] = icmp ugt i32 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK: cond.true11: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[COND_END13:%.*]] +// CHECK: cond.false12: +// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[MAX_T1_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END13]] +// CHECK: cond.end13: +// CHECK-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE11]] ], [ [[TMP33]], [[COND_FALSE12]] ] +// CHECK-NEXT: store i32 [[COND14]], ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l21_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[MAX_T2:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[MAX_T2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T2]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[MAX_T2_ASCAST]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[MAX_T2_ASCAST]], align 4 +// CHECK-NEXT: [[CONV4:%.*]] = uitofp i32 [[TMP9]] to double +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[CONV5:%.*]] = uitofp i32 [[TMP12]] to double +// CHECK-NEXT: [[TMP13:%.*]] = call double @llvm.maxnum.f64(double [[CONV4]], double [[CONV5]]) +// CHECK-NEXT: [[CONV6:%.*]] = fptoui double [[TMP13]] to i32 +// CHECK-NEXT: store i32 [[CONV6]], ptr [[MAX_T2_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]]) +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MAX_T2_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i64 4, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.19, ptr @_omp_reduction_inter_warp_copy_func.20) +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 1 +// CHECK-NEXT: br i1 [[TMP18]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[MAX_T2_ASCAST]], align 4 +// CHECK-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP19]], [[TMP20]] +// CHECK-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[MAX_T2_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP21]], [[COND_TRUE]] ], [ [[TMP22]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.19 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP19:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]] +// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP23:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP23]], 0 +// CHECK-NEXT: [[TMP25:%.*]] = and i1 [[TMP22]], [[TMP24]] +// CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = or i1 [[TMP18]], [[TMP21]] +// CHECK-NEXT: [[TMP29:%.*]] = or i1 [[TMP28]], [[TMP27]] +// CHECK-NEXT: br i1 [[TMP29]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l21_omp_outlined_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP31:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[TMP32]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8 +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP34]], align 4 +// CHECK-NEXT: store i32 [[TMP37]], ptr [[TMP36]], align 4 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.20 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP9]], ptr addrspace(3) [[TMP8]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i32, ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.21 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP19:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]] +// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP23:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP23]], 0 +// CHECK-NEXT: [[TMP25:%.*]] = and i1 [[TMP22]], [[TMP24]] +// CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = or i1 [[TMP18]], [[TMP21]] +// CHECK-NEXT: [[TMP29:%.*]] = or i1 [[TMP28]], [[TMP27]] +// CHECK-NEXT: br i1 [[TMP29]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l21_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP31:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[TMP32]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8 +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP34]], align 4 +// CHECK-NEXT: store i32 [[TMP37]], ptr [[TMP36]], align 4 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.22 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP9]], ptr addrspace(3) [[TMP8]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i32, ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func.23 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_7:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_7]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func.24 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_7:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_7]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l21_omp_outlined_omp$reduction$reduction_func"(ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr [[TMP8]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func.25 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_7:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_7]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[TMP7]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func.26 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_7:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_7]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIjEvv_l21_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP8]], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIxEvv_l17 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: store i64 9223372036854775807, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP5]] +// CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: [[CONV:%.*]] = sitofp i64 [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load i64, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = fptosi double [[CONV]] to i64 +// CHECK-NEXT: [[XTEAM_MIN:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP19]], i64 [[TMP20]]) +// CHECK-NEXT: store i64 [[XTEAM_MIN]], ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP11]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: call void @__kmpc_xteamr_l_16x64(i64 [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_min_l, ptr @__kmpc_rfun_min_lds_l, i64 9223372036854775807, i64 [[TMP12]], i32 [[TMP11]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIxEvv_l21 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: store i64 -9223372036854775808, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP5]] +// CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: [[CONV:%.*]] = sitofp i64 [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load i64, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = fptosi double [[CONV]] to i64 +// CHECK-NEXT: [[XTEAM_MAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP19]], i64 [[TMP20]]) +// CHECK-NEXT: store i64 [[XTEAM_MAX]], ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP11]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: call void @__kmpc_xteamr_l_16x64(i64 [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_max_l, ptr @__kmpc_rfun_max_lds_l, i64 -9223372036854775808, i64 [[TMP12]], i32 [[TMP11]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l17 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR3]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l17_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l17_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP0]], ptr [[TMP3]]) #[[ATTR1]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l17_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T1:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T1]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 -1, ptr [[MIN_T1_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 1000 +// CHECK-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP8]] to ptr +// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP10]] to ptr +// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: store ptr [[MIN_T1_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8 +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l17_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4) +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 999 +// CHECK-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK: cond.true6: +// CHECK-NEXT: br label [[COND_END8:%.*]] +// CHECK: cond.false7: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END8]] +// CHECK: cond.end8: +// CHECK-NEXT: [[COND9:%.*]] = phi i32 [ 999, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ] +// CHECK-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]]) +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MIN_T1_ASCAST]], ptr [[TMP27]], align 8 +// CHECK-NEXT: %"_openmp_teams_reductions_buffer_$_$ptr" = call ptr @__kmpc_reduction_get_fixed_buffer() +// CHECK-NEXT: [[TMP28:%.*]] = call i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), ptr %"_openmp_teams_reductions_buffer_$_$ptr", i32 1024, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.29, ptr @_omp_reduction_inter_warp_copy_func.30, ptr @_omp_reduction_list_to_global_copy_func.31, ptr @_omp_reduction_list_to_global_reduce_func.32, ptr @_omp_reduction_global_to_list_copy_func.33, ptr @_omp_reduction_global_to_list_reduce_func.34) +// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i32 [[TMP28]], 1 +// CHECK-NEXT: br i1 [[TMP29]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr [[TMP0]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load i64, ptr [[MIN_T1_ASCAST]], align 8 +// CHECK-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK: cond.true11: +// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr [[TMP0]], align 8 +// CHECK-NEXT: br label [[COND_END13:%.*]] +// CHECK: cond.false12: +// CHECK-NEXT: [[TMP33:%.*]] = load i64, ptr [[MIN_T1_ASCAST]], align 8 +// CHECK-NEXT: br label [[COND_END13]] +// CHECK: cond.end13: +// CHECK-NEXT: [[COND14:%.*]] = phi i64 [ [[TMP32]], [[COND_TRUE11]] ], [ [[TMP33]], [[COND_FALSE12]] ] +// CHECK-NEXT: store i64 [[COND14]], ptr [[TMP0]], align 8 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l17_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[MIN_T2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[MIN_T2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T2]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: store i64 -1, ptr [[MIN_T2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[MIN_T2_ASCAST]], align 8 +// CHECK-NEXT: [[CONV4:%.*]] = uitofp i64 [[TMP9]] to double +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP10]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: [[CONV5:%.*]] = uitofp i64 [[TMP12]] to double +// CHECK-NEXT: [[TMP13:%.*]] = call double @llvm.minnum.f64(double [[CONV4]], double [[CONV5]]) +// CHECK-NEXT: [[CONV6:%.*]] = fptoui double [[TMP13]] to i64 +// CHECK-NEXT: store i64 [[CONV6]], ptr [[MIN_T2_ASCAST]], align 8 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]]) +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MIN_T2_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.27, ptr @_omp_reduction_inter_warp_copy_func.28) +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 1 +// CHECK-NEXT: br i1 [[TMP18]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP19:%.*]] = load i64, ptr [[TMP0]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr [[MIN_T2_ASCAST]], align 8 +// CHECK-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP19]], [[TMP20]] +// CHECK-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP0]], align 8 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[MIN_T2_ASCAST]], align 8 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i64 [ [[TMP21]], [[COND_TRUE]] ], [ [[TMP22]], [[COND_FALSE]] ] +// CHECK-NEXT: store i64 [[COND]], ptr [[TMP0]], align 8 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.27 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i64 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i64, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP19:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]] +// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP23:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP23]], 0 +// CHECK-NEXT: [[TMP25:%.*]] = and i1 [[TMP22]], [[TMP24]] +// CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = or i1 [[TMP18]], [[TMP21]] +// CHECK-NEXT: [[TMP29:%.*]] = or i1 [[TMP28]], [[TMP27]] +// CHECK-NEXT: br i1 [[TMP29]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l17_omp_outlined_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP31:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[TMP32]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8 +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[TMP34]], align 8 +// CHECK-NEXT: store i64 [[TMP37]], ptr [[TMP36]], align 8 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.28 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCNT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCNT_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: br label [[PRECOND:%.*]] +// CHECK: precond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i32 [[TMP6]], 2 +// CHECK-NEXT: br i1 [[TMP7]], label [[BODY:%.*]], label [[EXIT:%.*]] +// CHECK: body: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP9]], i32 [[TMP6]] +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP12]], ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP13]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP16]], i32 [[TMP6]] +// CHECK-NEXT: [[TMP18:%.*]] = load volatile i32, ptr addrspace(3) [[TMP14]], align 4 +// CHECK-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: [[TMP19:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK-NEXT: store i32 [[TMP19]], ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: br label [[PRECOND]] +// CHECK: exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.29 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i64 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i64, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP19:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]] +// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP23:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP23]], 0 +// CHECK-NEXT: [[TMP25:%.*]] = and i1 [[TMP22]], [[TMP24]] +// CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = or i1 [[TMP18]], [[TMP21]] +// CHECK-NEXT: [[TMP29:%.*]] = or i1 [[TMP28]], [[TMP27]] +// CHECK-NEXT: br i1 [[TMP29]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l17_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP31:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[TMP32]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8 +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[TMP34]], align 8 +// CHECK-NEXT: store i64 [[TMP37]], ptr [[TMP36]], align 8 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.30 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCNT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCNT_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: br label [[PRECOND:%.*]] +// CHECK: precond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i32 [[TMP6]], 2 +// CHECK-NEXT: br i1 [[TMP7]], label [[BODY:%.*]], label [[EXIT:%.*]] +// CHECK: body: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP9]], i32 [[TMP6]] +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP12]], ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP13]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP16]], i32 [[TMP6]] +// CHECK-NEXT: [[TMP18:%.*]] = load volatile i32, ptr addrspace(3) [[TMP14]], align 4 +// CHECK-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: [[TMP19:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK-NEXT: store i32 [[TMP19]], ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: br label [[PRECOND]] +// CHECK: exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func.31 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_10:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_10]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP7]], align 8 +// CHECK-NEXT: store i64 [[TMP10]], ptr [[TMP9]], align 8 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func.32 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_10:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_10]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l17_omp_outlined_omp$reduction$reduction_func"(ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr [[TMP8]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func.33 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_10:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_10]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK-NEXT: store i64 [[TMP10]], ptr [[TMP7]], align 8 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func.34 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_10:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_10]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l17_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP8]], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l21 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR3]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l21_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l21_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP0]], ptr [[TMP3]]) #[[ATTR1]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l21_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T1:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T1]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 0, ptr [[MAX_T1_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 1000 +// CHECK-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP8]] to ptr +// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP10]] to ptr +// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: store ptr [[MAX_T1_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP17]], align 8 +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l21_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4) +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// CHECK-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 999 +// CHECK-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] +// CHECK: cond.true6: +// CHECK-NEXT: br label [[COND_END8:%.*]] +// CHECK: cond.false7: +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END8]] +// CHECK: cond.end8: +// CHECK-NEXT: [[COND9:%.*]] = phi i32 [ 999, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ] +// CHECK-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]]) +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MAX_T1_ASCAST]], ptr [[TMP27]], align 8 +// CHECK-NEXT: %"_openmp_teams_reductions_buffer_$_$ptr" = call ptr @__kmpc_reduction_get_fixed_buffer() +// CHECK-NEXT: [[TMP28:%.*]] = call i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), ptr %"_openmp_teams_reductions_buffer_$_$ptr", i32 1024, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.37, ptr @_omp_reduction_inter_warp_copy_func.38, ptr @_omp_reduction_list_to_global_copy_func.39, ptr @_omp_reduction_list_to_global_reduce_func.40, ptr @_omp_reduction_global_to_list_copy_func.41, ptr @_omp_reduction_global_to_list_reduce_func.42) +// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i32 [[TMP28]], 1 +// CHECK-NEXT: br i1 [[TMP29]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr [[TMP0]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load i64, ptr [[MAX_T1_ASCAST]], align 8 +// CHECK-NEXT: [[CMP10:%.*]] = icmp ugt i64 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] +// CHECK: cond.true11: +// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr [[TMP0]], align 8 +// CHECK-NEXT: br label [[COND_END13:%.*]] +// CHECK: cond.false12: +// CHECK-NEXT: [[TMP33:%.*]] = load i64, ptr [[MAX_T1_ASCAST]], align 8 +// CHECK-NEXT: br label [[COND_END13]] +// CHECK: cond.end13: +// CHECK-NEXT: [[COND14:%.*]] = phi i64 [ [[TMP32]], [[COND_TRUE11]] ], [ [[TMP33]], [[COND_FALSE12]] ] +// CHECK-NEXT: store i64 [[COND14]], ptr [[TMP0]], align 8 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l21_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[MAX_T2:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[MAX_T2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T2]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 +// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: store i64 0, ptr [[MAX_T2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64 +// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[MAX_T2_ASCAST]], align 8 +// CHECK-NEXT: [[CONV4:%.*]] = uitofp i64 [[TMP9]] to double +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP10]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: [[CONV5:%.*]] = uitofp i64 [[TMP12]] to double +// CHECK-NEXT: [[TMP13:%.*]] = call double @llvm.maxnum.f64(double [[CONV4]], double [[CONV5]]) +// CHECK-NEXT: [[CONV6:%.*]] = fptoui double [[TMP13]] to i64 +// CHECK-NEXT: store i64 [[CONV6]], ptr [[MAX_T2_ASCAST]], align 8 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP4]]) +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MAX_T2_ASCAST]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.35, ptr @_omp_reduction_inter_warp_copy_func.36) +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 1 +// CHECK-NEXT: br i1 [[TMP18]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP19:%.*]] = load i64, ptr [[TMP0]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr [[MAX_T2_ASCAST]], align 8 +// CHECK-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[TMP19]], [[TMP20]] +// CHECK-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP0]], align 8 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[MAX_T2_ASCAST]], align 8 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i64 [ [[TMP21]], [[COND_TRUE]] ], [ [[TMP22]], [[COND_FALSE]] ] +// CHECK-NEXT: store i64 [[COND]], ptr [[TMP0]], align 8 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.35 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i64 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i64, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP19:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]] +// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP23:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP23]], 0 +// CHECK-NEXT: [[TMP25:%.*]] = and i1 [[TMP22]], [[TMP24]] +// CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = or i1 [[TMP18]], [[TMP21]] +// CHECK-NEXT: [[TMP29:%.*]] = or i1 [[TMP28]], [[TMP27]] +// CHECK-NEXT: br i1 [[TMP29]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l21_omp_outlined_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP31:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[TMP32]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8 +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[TMP34]], align 8 +// CHECK-NEXT: store i64 [[TMP37]], ptr [[TMP36]], align 8 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.36 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCNT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCNT_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: br label [[PRECOND:%.*]] +// CHECK: precond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i32 [[TMP6]], 2 +// CHECK-NEXT: br i1 [[TMP7]], label [[BODY:%.*]], label [[EXIT:%.*]] +// CHECK: body: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP9]], i32 [[TMP6]] +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP12]], ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP13]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP16]], i32 [[TMP6]] +// CHECK-NEXT: [[TMP18:%.*]] = load volatile i32, ptr addrspace(3) [[TMP14]], align 4 +// CHECK-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: [[TMP19:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK-NEXT: store i32 [[TMP19]], ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: br label [[PRECOND]] +// CHECK: exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.37 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i64 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i64, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP19:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]] +// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP23:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP23]], 0 +// CHECK-NEXT: [[TMP25:%.*]] = and i1 [[TMP22]], [[TMP24]] +// CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 [[TMP25]], [[TMP26]] +// CHECK-NEXT: [[TMP28:%.*]] = or i1 [[TMP18]], [[TMP21]] +// CHECK-NEXT: [[TMP29:%.*]] = or i1 [[TMP28]], [[TMP27]] +// CHECK-NEXT: br i1 [[TMP29]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l21_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP31:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[TMP32]], label [[THEN4:%.*]], label [[ELSE5:%.*]] +// CHECK: then4: +// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8 +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[TMP34]], align 8 +// CHECK-NEXT: store i64 [[TMP37]], ptr [[TMP36]], align 8 +// CHECK-NEXT: br label [[IFCONT6:%.*]] +// CHECK: else5: +// CHECK-NEXT: br label [[IFCONT6]] +// CHECK: ifcont6: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.38 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCNT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCNT_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: br label [[PRECOND:%.*]] +// CHECK: precond: +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i32 [[TMP6]], 2 +// CHECK-NEXT: br i1 [[TMP7]], label [[BODY:%.*]], label [[EXIT:%.*]] +// CHECK: body: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP9]], i32 [[TMP6]] +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP12]], ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP13]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP16]], i32 [[TMP6]] +// CHECK-NEXT: [[TMP18:%.*]] = load volatile i32, ptr addrspace(3) [[TMP14]], align 4 +// CHECK-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: [[TMP19:%.*]] = add nsw i32 [[TMP6]], 1 +// CHECK-NEXT: store i32 [[TMP19]], ptr [[DOTCNT_ADDR_ASCAST]], align 4 +// CHECK-NEXT: br label [[PRECOND]] +// CHECK: exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func.39 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_13:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_13]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP7]], align 8 +// CHECK-NEXT: store i64 [[TMP10]], ptr [[TMP9]], align 8 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func.40 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_13:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_13]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l21_omp_outlined_omp$reduction$reduction_func"(ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr [[TMP8]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func.41 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_13:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_13]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK-NEXT: store i64 [[TMP10]], ptr [[TMP7]], align 8 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func.42 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_13:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY_13]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIyEvv_l21_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP8]], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]]) #[[ATTR1]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIfEvv_l17 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: store float 0x7FF0000000000000, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP5]] +// CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[CONV:%.*]] = fpext float [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load float, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = fptrunc double [[CONV]] to float +// CHECK-NEXT: [[XTEAM_MIN:%.*]] = call float @llvm.minnum.f32(float [[TMP19]], float [[TMP20]]) +// CHECK-NEXT: store float [[XTEAM_MIN]], ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP11]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load float, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_xteamr_f_16x64(float [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_min_f, ptr @__kmpc_rfun_min_lds_f, float 0x7FF0000000000000, i64 [[TMP12]], i32 [[TMP11]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIfEvv_l21 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: store float 0xFFF0000000000000, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP5]] +// CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[CONV:%.*]] = fpext float [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load float, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = fptrunc double [[CONV]] to float +// CHECK-NEXT: [[XTEAM_MAX:%.*]] = call float @llvm.maxnum.f32(float [[TMP19]], float [[TMP20]]) +// CHECK-NEXT: store float [[XTEAM_MAX]], ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP11]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load float, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_xteamr_f_16x64(float [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_max_f, ptr @__kmpc_rfun_max_lds_f, float 0xFFF0000000000000, i64 [[TMP12]], i32 [[TMP11]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIdEvv_l17 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[MIN_T:%.*]], ptr noundef [[ARR_T:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN_T]], ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-NEXT: store double 0x7FF0000000000000, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP5]] +// CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load double, ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: [[TMP19:%.*]] = load double, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: [[XTEAM_MIN:%.*]] = call double @llvm.minnum.f64(double [[TMP19]], double [[TMP18]]) +// CHECK-NEXT: store double [[XTEAM_MIN]], ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP20:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP11]] +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[TMP20]], 1 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = add i32 [[TMP21]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP23]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load double, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: call void @__kmpc_xteamr_d_16x64(double [[TMP26]], ptr [[TMP2]], ptr [[TMP24]], ptr [[TMP25]], ptr @__kmpc_rfun_min_d, ptr @__kmpc_rfun_min_lds_d, double 0x7FF0000000000000, i64 [[TMP12]], i32 [[TMP11]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15compute_min_maxIdEvv_l21 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[MAX_T:%.*]], ptr noundef [[ARR_T:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ARR_T_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX_T_ADDR]] to ptr +// CHECK-NEXT: [[ARR_T_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_T_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX_T]], ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[ARR_T]], ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MAX_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-NEXT: store double 0xFFF0000000000000, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], [[TMP5]] +// CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 1 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]] +// CHECK-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[ARR_T_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load double, ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: [[TMP19:%.*]] = load double, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: [[XTEAM_MAX:%.*]] = call double @llvm.maxnum.f64(double [[TMP19]], double [[TMP18]]) +// CHECK-NEXT: store double [[XTEAM_MAX]], ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP20:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP11]] +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[TMP20]], 1 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = add i32 [[TMP21]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP23]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load double, ptr addrspace(5) [[TMP3]], align 8 +// CHECK-NEXT: call void @__kmpc_xteamr_d_16x64(double [[TMP26]], ptr [[TMP2]], ptr [[TMP24]], ptr [[TMP25]], ptr @__kmpc_rfun_max_d, ptr @__kmpc_rfun_max_lds_d, double 0xFFF0000000000000, i64 [[TMP12]], i32 [[TMP11]], i32 1) +// CHECK-NEXT: ret void +// diff --git a/clang/test/OpenMP/xteam_red_min_max_fast_reduction.c b/clang/test/OpenMP/xteam_red_min_max_fast_reduction.c new file mode 100644 index 0000000000000..cb24ff5d20852 --- /dev/null +++ b/clang/test/OpenMP/xteam_red_min_max_fast_reduction.c @@ -0,0 +1,1071 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-fast-reduction -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-fast-reduction -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// expected-no-diagnostics + +/* + * Test min/max/sum reduction when fast Xteam reduction is enabled. In the same kernel, + * min/max and sum reductions are present. Xteam reduction will not be enabled in this kernel. + * But in some other kernel, Xteam reduction can be used. + */ + + #define N 1000 + +int main() +{ + float a[N]; + + for (int i = 0; i < N; i++) + a[i] = i + 11; + + float max1 = 0; + float min1 = 1000000; + float sum1 = 0; + float sum2 = 0; + +#pragma omp target teams distribute parallel for reduction(max : max1) reduction(min : min1) reduction(+ : sum1) + for (int i = 0; i < N; i = i + 1) + { + max1 = __builtin_fmaxf(max1, a[i]); + min1 = __builtin_fminf(min1, a[i]); + sum1 += a[i]; + } + +#pragma omp target teams distribute parallel for reduction(+ : sum2) + for (int i = 0; i < N; i = i + 1) + sum2 += a[i]; +} + + +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX1:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX1_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[MIN1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN1_ADDR]] to ptr +// CHECK-NEXT: [[SUM1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM1_ADDR]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX1]], ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN1]], ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX1:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX11:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[MIN12:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[SUM13:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [6 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[MAX1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX1_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[MIN1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN1_ADDR]] to ptr +// CHECK-NEXT: [[SUM1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM1_ADDR]] to ptr +// CHECK-NEXT: [[MAX11_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX11]] to ptr +// CHECK-NEXT: [[MIN12_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN12]] to ptr +// CHECK-NEXT: [[SUM13_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM13]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX1]], ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN1]], ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store float 0xC7EFFFFFE0000000, ptr [[MAX11_ASCAST]], align 4 +// CHECK-NEXT: store float 0x47EFFFFFE0000000, ptr [[MIN12_ASCAST]], align 4 +// CHECK-NEXT: store float 0.000000e+00, ptr [[SUM13_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 999, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP9]], 1000 +// CHECK-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP11]] to ptr +// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP13]] to ptr +// CHECK-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: store ptr [[MAX11_ASCAST]], ptr [[TMP18]], align 8 +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[TMP19]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4 +// CHECK-NEXT: store ptr [[MIN12_ASCAST]], ptr [[TMP20]], align 8 +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5 +// CHECK-NEXT: store ptr [[SUM13_ASCAST]], ptr [[TMP21]], align 8 +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP5]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 6) +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] +// CHECK-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] +// CHECK-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP28]], 999 +// CHECK-NEXT: br i1 [[CMP7]], label [[COND_TRUE8:%.*]], label [[COND_FALSE9:%.*]] +// CHECK: cond.true8: +// CHECK-NEXT: br label [[COND_END10:%.*]] +// CHECK: cond.false9: +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END10]] +// CHECK: cond.end10: +// CHECK-NEXT: [[COND11:%.*]] = phi i32 [ 999, [[COND_TRUE8]] ], [ [[TMP29]], [[COND_FALSE9]] ] +// CHECK-NEXT: store i32 [[COND11]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP30]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP5]]) +// CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MAX11_ASCAST]], ptr [[TMP31]], align 8 +// CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: store ptr [[MIN12_ASCAST]], ptr [[TMP32]], align 8 +// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: store ptr [[SUM13_ASCAST]], ptr [[TMP33]], align 8 +// CHECK-NEXT: %"_openmp_teams_reductions_buffer_$_$ptr" = call ptr @__kmpc_reduction_get_fixed_buffer() +// CHECK-NEXT: [[TMP34:%.*]] = call i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), ptr %"_openmp_teams_reductions_buffer_$_$ptr", i32 1024, i64 12, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.1, ptr @_omp_reduction_inter_warp_copy_func.2, ptr @_omp_reduction_list_to_global_copy_func, ptr @_omp_reduction_list_to_global_reduce_func, ptr @_omp_reduction_global_to_list_copy_func, ptr @_omp_reduction_global_to_list_reduce_func) +// CHECK-NEXT: [[TMP35:%.*]] = icmp eq i32 [[TMP34]], 1 +// CHECK-NEXT: br i1 [[TMP35]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP36:%.*]] = load float, ptr [[TMP0]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = load float, ptr [[MAX11_ASCAST]], align 4 +// CHECK-NEXT: [[CMP12:%.*]] = fcmp ogt float [[TMP36]], [[TMP37]] +// CHECK-NEXT: br i1 [[CMP12]], label [[COND_TRUE13:%.*]], label [[COND_FALSE14:%.*]] +// CHECK: cond.true13: +// CHECK-NEXT: [[TMP38:%.*]] = load float, ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[COND_END15:%.*]] +// CHECK: cond.false14: +// CHECK-NEXT: [[TMP39:%.*]] = load float, ptr [[MAX11_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END15]] +// CHECK: cond.end15: +// CHECK-NEXT: [[COND16:%.*]] = phi float [ [[TMP38]], [[COND_TRUE13]] ], [ [[TMP39]], [[COND_FALSE14]] ] +// CHECK-NEXT: store float [[COND16]], ptr [[TMP0]], align 4 +// CHECK-NEXT: [[TMP40:%.*]] = load float, ptr [[TMP2]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load float, ptr [[MIN12_ASCAST]], align 4 +// CHECK-NEXT: [[CMP17:%.*]] = fcmp olt float [[TMP40]], [[TMP41]] +// CHECK-NEXT: br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]] +// CHECK: cond.true18: +// CHECK-NEXT: [[TMP42:%.*]] = load float, ptr [[TMP2]], align 4 +// CHECK-NEXT: br label [[COND_END20:%.*]] +// CHECK: cond.false19: +// CHECK-NEXT: [[TMP43:%.*]] = load float, ptr [[MIN12_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END20]] +// CHECK: cond.end20: +// CHECK-NEXT: [[COND21:%.*]] = phi float [ [[TMP42]], [[COND_TRUE18]] ], [ [[TMP43]], [[COND_FALSE19]] ] +// CHECK-NEXT: store float [[COND21]], ptr [[TMP2]], align 4 +// CHECK-NEXT: [[TMP44:%.*]] = load float, ptr [[TMP3]], align 4 +// CHECK-NEXT: [[TMP45:%.*]] = load float, ptr [[SUM13_ASCAST]], align 4 +// CHECK-NEXT: [[ADD22:%.*]] = fadd float [[TMP44]], [[TMP45]] +// CHECK-NEXT: store float [[ADD22]], ptr [[TMP3]], align 4 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX1:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]]) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[MAX1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[MAX12:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[MIN13:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[SUM14:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// CHECK-NEXT: [[MAX1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX1_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[MIN1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN1_ADDR]] to ptr +// CHECK-NEXT: [[SUM1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM1_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[MAX12_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX12]] to ptr +// CHECK-NEXT: [[MIN13_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN13]] to ptr +// CHECK-NEXT: [[SUM14_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM14]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX1]], ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN1]], ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP5]] to i32 +// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: store float 0xC7EFFFFFE0000000, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: store float 0x47EFFFFFE0000000, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: store float 0.000000e+00, ptr [[SUM14_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP7]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CONV5:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV5]], [[TMP10]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load float, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x float], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = call float @llvm.maxnum.f32(float [[TMP12]], float [[TMP14]]) +// CHECK-NEXT: store float [[TMP15]], ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load float, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x float], ptr [[TMP1]], i64 0, i64 [[IDXPROM6]] +// CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = call float @llvm.minnum.f32(float [[TMP16]], float [[TMP18]]) +// CHECK-NEXT: store float [[TMP19]], ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [1000 x float], ptr [[TMP1]], i64 0, i64 [[IDXPROM8]] +// CHECK-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX9]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = load float, ptr [[SUM14_ASCAST]], align 4 +// CHECK-NEXT: [[ADD10:%.*]] = fadd float [[TMP22]], [[TMP21]] +// CHECK-NEXT: store float [[ADD10]], ptr [[SUM14_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// CHECK-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP7]]) +// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MAX12_ASCAST]], ptr [[TMP25]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: store ptr [[MIN13_ASCAST]], ptr [[TMP26]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: store ptr [[SUM14_ASCAST]], ptr [[TMP27]], align 8 +// CHECK-NEXT: [[TMP28:%.*]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i64 12, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func, ptr @_omp_reduction_inter_warp_copy_func) +// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i32 [[TMP28]], 1 +// CHECK-NEXT: br i1 [[TMP29]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP30:%.*]] = load float, ptr [[TMP0]], align 4 +// CHECK-NEXT: [[TMP31:%.*]] = load float, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: [[CMP12:%.*]] = fcmp ogt float [[TMP30]], [[TMP31]] +// CHECK-NEXT: br i1 [[CMP12]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP32:%.*]] = load float, ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP33:%.*]] = load float, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi float [ [[TMP32]], [[COND_TRUE]] ], [ [[TMP33]], [[COND_FALSE]] ] +// CHECK-NEXT: store float [[COND]], ptr [[TMP0]], align 4 +// CHECK-NEXT: [[TMP34:%.*]] = load float, ptr [[TMP2]], align 4 +// CHECK-NEXT: [[TMP35:%.*]] = load float, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: [[CMP13:%.*]] = fcmp olt float [[TMP34]], [[TMP35]] +// CHECK-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] +// CHECK: cond.true14: +// CHECK-NEXT: [[TMP36:%.*]] = load float, ptr [[TMP2]], align 4 +// CHECK-NEXT: br label [[COND_END16:%.*]] +// CHECK: cond.false15: +// CHECK-NEXT: [[TMP37:%.*]] = load float, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END16]] +// CHECK: cond.end16: +// CHECK-NEXT: [[COND17:%.*]] = phi float [ [[TMP36]], [[COND_TRUE14]] ], [ [[TMP37]], [[COND_FALSE15]] ] +// CHECK-NEXT: store float [[COND17]], ptr [[TMP2]], align 4 +// CHECK-NEXT: [[TMP38:%.*]] = load float, ptr [[TMP3]], align 4 +// CHECK-NEXT: [[TMP39:%.*]] = load float, ptr [[SUM14_ASCAST]], align 4 +// CHECK-NEXT: [[ADD18:%.*]] = fadd float [[TMP38]], [[TMP39]] +// CHECK-NEXT: store float [[ADD18]], ptr [[TMP3]], align 4 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [3 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT4:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT4]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT5:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT5]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr float, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 1 +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr float, ptr [[TMP19]], i64 1 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i16 +// CHECK-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP22]], i16 [[TMP6]], i16 [[TMP24]]) +// CHECK-NEXT: store i32 [[TMP25]], ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP19]], i64 1 +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], ptr [[TMP20]], align 8 +// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 2 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP28]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: [[TMP31:%.*]] = getelementptr float, ptr [[TMP29]], i64 1 +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP29]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP34:%.*]] = trunc i32 [[TMP33]] to i16 +// CHECK-NEXT: [[TMP35:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP32]], i16 [[TMP6]], i16 [[TMP34]]) +// CHECK-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_REDUCTION_ELEMENT5_ASCAST]], align 4 +// CHECK-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr [[TMP29]], i64 1 +// CHECK-NEXT: [[TMP37:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT5_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT5_ASCAST]], ptr [[TMP30]], align 8 +// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP39:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP40:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP41:%.*]] = and i1 [[TMP39]], [[TMP40]] +// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP43:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP44:%.*]] = icmp eq i16 [[TMP43]], 0 +// CHECK-NEXT: [[TMP45:%.*]] = and i1 [[TMP42]], [[TMP44]] +// CHECK-NEXT: [[TMP46:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]] +// CHECK-NEXT: [[TMP48:%.*]] = or i1 [[TMP38]], [[TMP41]] +// CHECK-NEXT: [[TMP49:%.*]] = or i1 [[TMP48]], [[TMP47]] +// CHECK-NEXT: br i1 [[TMP49]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26_omp_outlined_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR2]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP51:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP52:%.*]] = and i1 [[TMP50]], [[TMP51]] +// CHECK-NEXT: br i1 [[TMP52]], label [[THEN6:%.*]], label [[ELSE7:%.*]] +// CHECK: then6: +// CHECK-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[TMP53]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP56:%.*]] = load ptr, ptr [[TMP55]], align 8 +// CHECK-NEXT: [[TMP57:%.*]] = load float, ptr [[TMP54]], align 4 +// CHECK-NEXT: store float [[TMP57]], ptr [[TMP56]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP59:%.*]] = load ptr, ptr [[TMP58]], align 8 +// CHECK-NEXT: [[TMP60:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 1 +// CHECK-NEXT: [[TMP61:%.*]] = load ptr, ptr [[TMP60]], align 8 +// CHECK-NEXT: [[TMP62:%.*]] = load float, ptr [[TMP59]], align 4 +// CHECK-NEXT: store float [[TMP62]], ptr [[TMP61]], align 4 +// CHECK-NEXT: [[TMP63:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: [[TMP64:%.*]] = load ptr, ptr [[TMP63]], align 8 +// CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 2 +// CHECK-NEXT: [[TMP66:%.*]] = load ptr, ptr [[TMP65]], align 8 +// CHECK-NEXT: [[TMP67:%.*]] = load float, ptr [[TMP64]], align 4 +// CHECK-NEXT: store float [[TMP67]], ptr [[TMP66]], align 4 +// CHECK-NEXT: br label [[IFCONT8:%.*]] +// CHECK: else7: +// CHECK-NEXT: br label [[IFCONT8]] +// CHECK: ifcont8: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4:[0-9]+]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP9]], ptr addrspace(3) [[TMP8]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i32, ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM6:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM6]]) +// CHECK-NEXT: [[WARP_MASTER7:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER7]], label [[THEN8:%.*]], label [[ELSE9:%.*]] +// CHECK: then8: +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 1 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP18]], ptr addrspace(3) [[TMP17]], align 4 +// CHECK-NEXT: br label [[IFCONT10:%.*]] +// CHECK: else9: +// CHECK-NEXT: br label [[IFCONT10]] +// CHECK: ifcont10: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM11]]) +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD12:%.*]] = icmp ult i32 [[TMP2]], [[TMP19]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD12]], label [[THEN13:%.*]], label [[ELSE14:%.*]] +// CHECK: then13: +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 1 +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = load volatile i32, ptr addrspace(3) [[TMP20]], align 4 +// CHECK-NEXT: store i32 [[TMP23]], ptr [[TMP22]], align 4 +// CHECK-NEXT: br label [[IFCONT15:%.*]] +// CHECK: else14: +// CHECK-NEXT: br label [[IFCONT15]] +// CHECK: ifcont15: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM16:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM16]]) +// CHECK-NEXT: [[WARP_MASTER17:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER17]], label [[THEN18:%.*]], label [[ELSE19:%.*]] +// CHECK: then18: +// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 2 +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP25]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP27]], ptr addrspace(3) [[TMP26]], align 4 +// CHECK-NEXT: br label [[IFCONT20:%.*]] +// CHECK: else19: +// CHECK-NEXT: br label [[IFCONT20]] +// CHECK: ifcont20: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM21:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM21]]) +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD22:%.*]] = icmp ult i32 [[TMP2]], [[TMP28]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD22]], label [[THEN23:%.*]], label [[ELSE24:%.*]] +// CHECK: then23: +// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 2 +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8 +// CHECK-NEXT: [[TMP32:%.*]] = load volatile i32, ptr addrspace(3) [[TMP29]], align 4 +// CHECK-NEXT: store i32 [[TMP32]], ptr [[TMP31]], align 4 +// CHECK-NEXT: br label [[IFCONT25:%.*]] +// CHECK: else24: +// CHECK-NEXT: br label [[IFCONT25]] +// CHECK: ifcont25: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.1 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [3 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT4:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT4]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT5:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT5]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr float, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 1 +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr float, ptr [[TMP19]], i64 1 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i16 +// CHECK-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP22]], i16 [[TMP6]], i16 [[TMP24]]) +// CHECK-NEXT: store i32 [[TMP25]], ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP19]], i64 1 +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], ptr [[TMP20]], align 8 +// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 2 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP28]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: [[TMP31:%.*]] = getelementptr float, ptr [[TMP29]], i64 1 +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP29]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP34:%.*]] = trunc i32 [[TMP33]] to i16 +// CHECK-NEXT: [[TMP35:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP32]], i16 [[TMP6]], i16 [[TMP34]]) +// CHECK-NEXT: store i32 [[TMP35]], ptr [[DOTOMP_REDUCTION_ELEMENT5_ASCAST]], align 4 +// CHECK-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr [[TMP29]], i64 1 +// CHECK-NEXT: [[TMP37:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT5_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT5_ASCAST]], ptr [[TMP30]], align 8 +// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP39:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP40:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP41:%.*]] = and i1 [[TMP39]], [[TMP40]] +// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP43:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP44:%.*]] = icmp eq i16 [[TMP43]], 0 +// CHECK-NEXT: [[TMP45:%.*]] = and i1 [[TMP42]], [[TMP44]] +// CHECK-NEXT: [[TMP46:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]] +// CHECK-NEXT: [[TMP48:%.*]] = or i1 [[TMP38]], [[TMP41]] +// CHECK-NEXT: [[TMP49:%.*]] = or i1 [[TMP48]], [[TMP47]] +// CHECK-NEXT: br i1 [[TMP49]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR2]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP51:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP52:%.*]] = and i1 [[TMP50]], [[TMP51]] +// CHECK-NEXT: br i1 [[TMP52]], label [[THEN6:%.*]], label [[ELSE7:%.*]] +// CHECK: then6: +// CHECK-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[TMP53]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP56:%.*]] = load ptr, ptr [[TMP55]], align 8 +// CHECK-NEXT: [[TMP57:%.*]] = load float, ptr [[TMP54]], align 4 +// CHECK-NEXT: store float [[TMP57]], ptr [[TMP56]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP59:%.*]] = load ptr, ptr [[TMP58]], align 8 +// CHECK-NEXT: [[TMP60:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 1 +// CHECK-NEXT: [[TMP61:%.*]] = load ptr, ptr [[TMP60]], align 8 +// CHECK-NEXT: [[TMP62:%.*]] = load float, ptr [[TMP59]], align 4 +// CHECK-NEXT: store float [[TMP62]], ptr [[TMP61]], align 4 +// CHECK-NEXT: [[TMP63:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: [[TMP64:%.*]] = load ptr, ptr [[TMP63]], align 8 +// CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP4]], i64 0, i64 2 +// CHECK-NEXT: [[TMP66:%.*]] = load ptr, ptr [[TMP65]], align 8 +// CHECK-NEXT: [[TMP67:%.*]] = load float, ptr [[TMP64]], align 4 +// CHECK-NEXT: store float [[TMP67]], ptr [[TMP66]], align 4 +// CHECK-NEXT: br label [[IFCONT8:%.*]] +// CHECK: else7: +// CHECK-NEXT: br label [[IFCONT8]] +// CHECK: ifcont8: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.2 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP9]], ptr addrspace(3) [[TMP8]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i32, ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM6:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM6]]) +// CHECK-NEXT: [[WARP_MASTER7:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER7]], label [[THEN8:%.*]], label [[ELSE9:%.*]] +// CHECK: then8: +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 1 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP18]], ptr addrspace(3) [[TMP17]], align 4 +// CHECK-NEXT: br label [[IFCONT10:%.*]] +// CHECK: else9: +// CHECK-NEXT: br label [[IFCONT10]] +// CHECK: ifcont10: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM11]]) +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD12:%.*]] = icmp ult i32 [[TMP2]], [[TMP19]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD12]], label [[THEN13:%.*]], label [[ELSE14:%.*]] +// CHECK: then13: +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 1 +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = load volatile i32, ptr addrspace(3) [[TMP20]], align 4 +// CHECK-NEXT: store i32 [[TMP23]], ptr [[TMP22]], align 4 +// CHECK-NEXT: br label [[IFCONT15:%.*]] +// CHECK: else14: +// CHECK-NEXT: br label [[IFCONT15]] +// CHECK: ifcont15: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM16:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM16]]) +// CHECK-NEXT: [[WARP_MASTER17:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER17]], label [[THEN18:%.*]], label [[ELSE19:%.*]] +// CHECK: then18: +// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 2 +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP25]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP27]], ptr addrspace(3) [[TMP26]], align 4 +// CHECK-NEXT: br label [[IFCONT20:%.*]] +// CHECK: else19: +// CHECK-NEXT: br label [[IFCONT20]] +// CHECK: ifcont20: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM21:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM21]]) +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD22:%.*]] = icmp ult i32 [[TMP2]], [[TMP28]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD22]], label [[THEN23:%.*]], label [[ELSE24:%.*]] +// CHECK: then23: +// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP5]], i64 0, i64 2 +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8 +// CHECK-NEXT: [[TMP32:%.*]] = load volatile i32, ptr addrspace(3) [[TMP29]], align 4 +// CHECK-NEXT: store i32 [[TMP32]], ptr [[TMP31]], align 4 +// CHECK-NEXT: br label [[IFCONT25:%.*]] +// CHECK: else24: +// CHECK-NEXT: br label [[IFCONT25]] +// CHECK: ifcont25: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[TMP7]], align 4 +// CHECK-NEXT: store float [[TMP10]], ptr [[TMP9]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP13]], i32 0, i32 1 +// CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[TMP12]], align 4 +// CHECK-NEXT: store float [[TMP15]], ptr [[TMP14]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 2 +// CHECK-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP18]], i32 0, i32 2 +// CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[TMP17]], align 4 +// CHECK-NEXT: store float [[TMP20]], ptr [[TMP19]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP9]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[TMP10]], ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP12]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26_omp_outlined_omp$reduction$reduction_func"(ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr [[TMP14]]) #[[ATTR2]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[TMP9]], align 4 +// CHECK-NEXT: store float [[TMP10]], ptr [[TMP7]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP13]], i32 0, i32 1 +// CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[TMP14]], align 4 +// CHECK-NEXT: store float [[TMP15]], ptr [[TMP12]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 2 +// CHECK-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP18]], i32 0, i32 2 +// CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[TMP19]], align 4 +// CHECK-NEXT: store float [[TMP20]], ptr [[TMP17]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP9]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[TMP10]], ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP12]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l26_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP14]], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]]) #[[ATTR2]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l34 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM2:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM2_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM2_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM2_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM2]], ptr [[SUM2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SUM2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP4:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP4]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[TMP6]] +// CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], 1 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x float], ptr [[TMP3]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load float, ptr addrspace(5) [[TMP4]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = fadd float [[TMP19]], [[TMP18]] +// CHECK-NEXT: store float [[TMP20]], ptr addrspace(5) [[TMP4]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP12]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load float, ptr addrspace(5) [[TMP4]], align 4 +// CHECK-NEXT: call void @__kmpc_xteamr_f_16x64_fast_sum(float [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_sum_f, ptr @__kmpc_rfun_sum_lds_f, float 0.000000e+00, i64 [[TMP13]], i32 [[TMP12]], i32 1) +// CHECK-NEXT: ret void +// diff --git a/clang/test/OpenMP/xteam_red_min_max_multi_device.c b/clang/test/OpenMP/xteam_red_min_max_multi_device.c new file mode 100644 index 0000000000000..4d05b3e0e8f70 --- /dev/null +++ b/clang/test/OpenMP/xteam_red_min_max_multi_device.c @@ -0,0 +1,942 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-multi-device -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-multi-device -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// expected-no-diagnostics + +/* + * Test multi-device min/max reduction on floats using minf/maxf. + * There are 2 target regions in this program, the first has min/max reduction + * and the second has a sum reduction. The program is compiled with multi-device + * ON. Since multi-device compilation may be incompatible with Xteam min/max, the + * first target region does not use Xteam reduction. The second one, however, does. + */ + + #define N 1000 + +int main() +{ + float a[N]; + + for (int i = 0; i < N; i++) + a[i] = i + 11; + + float max1 = 0; + float min1 = 1000000; + float sum1 = 0; + +#pragma omp target teams distribute parallel for reduction(max : max1) reduction(min : min1) + for (int i = 0; i < N; i = i + 1) + { + max1 = __builtin_fmaxf(max1, a[i]); + min1 = __builtin_fminf(min1, a[i]); + } + + #pragma omp target teams distribute parallel for reduction(+ : sum1) + for (int i = 0; i < N; i = i + 1) + sum1 += a[i]; +} + + +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[TMP0:%.*]], i64 noundef [[TMP1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX1:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[MAX1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[MAX1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX1_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[MIN1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN1_ADDR]] to ptr +// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX1]], ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN1]], ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_kernel_environment to ptr), ptr [[DYN_PTR]]) +// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1 +// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// CHECK: user_code.entry: +// CHECK-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) +// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP6]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP8]], ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]]) #[[ATTR2:[0-9]+]] +// CHECK-NEXT: call void @__kmpc_target_deinit() +// CHECK-NEXT: ret void +// CHECK: worker.exit: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[TMP0:%.*]], i64 noundef [[TMP1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX1:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[MAX1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX12:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[MIN13:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[MAX1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX1_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[MIN1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN1_ADDR]] to ptr +// CHECK-NEXT: [[MAX12_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX12]] to ptr +// CHECK-NEXT: [[MIN13_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN13]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX1]], ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN1]], ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store float 0xC7EFFFFFE0000000, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: store float 0x47EFFFFFE0000000, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK-NEXT: call void @__kmpc_distribute_static_init_multi_device_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTADDR_ASCAST]], ptr [[DOTADDR1_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = sext i32 [[TMP7]] to i64 +// CHECK-NEXT: [[TMP10:%.*]] = icmp sgt i64 [[TMP9]], [[TMP8]] +// CHECK-NEXT: br i1 [[TMP10]], label [[OMP_MD_CHECK_TRUE:%.*]], label [[OMP_MD_CHECK_END:%.*]] +// CHECK: omp.md.check.true: +// CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_MD_CHECK_END]] +// CHECK: omp.md.check.end: +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]] +// CHECK-NEXT: br i1 [[TMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP18]] to ptr +// CHECK-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP20]] to ptr +// CHECK-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8 +// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// CHECK-NEXT: store ptr [[MAX12_ASCAST]], ptr [[TMP25]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[TMP26]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4 +// CHECK-NEXT: store ptr [[MIN13_ASCAST]], ptr [[TMP27]], align 8 +// CHECK-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP6]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 5) +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] +// CHECK-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] +// CHECK-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP36:%.*]] = sext i32 [[TMP34]] to i64 +// CHECK-NEXT: [[TMP37:%.*]] = icmp sgt i64 [[TMP36]], [[TMP35]] +// CHECK-NEXT: br i1 [[TMP37]], label [[OMP_MD_CHECK_TRUE6:%.*]], label [[OMP_MD_CHECK_END7:%.*]] +// CHECK: omp.md.check.true6: +// CHECK-NEXT: [[TMP38:%.*]] = trunc i64 [[TMP35]] to i32 +// CHECK-NEXT: store i32 [[TMP38]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_MD_CHECK_END7]] +// CHECK: omp.md.check.end7: +// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP6]]) +// CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MAX12_ASCAST]], ptr [[TMP40]], align 8 +// CHECK-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: store ptr [[MIN13_ASCAST]], ptr [[TMP41]], align 8 +// CHECK-NEXT: %"_openmp_teams_reductions_buffer_$_$ptr" = call ptr @__kmpc_reduction_get_fixed_buffer() +// CHECK-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), ptr %"_openmp_teams_reductions_buffer_$_$ptr", i32 1024, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.1, ptr @_omp_reduction_inter_warp_copy_func.2, ptr @_omp_reduction_list_to_global_copy_func, ptr @_omp_reduction_list_to_global_reduce_func, ptr @_omp_reduction_global_to_list_copy_func, ptr @_omp_reduction_global_to_list_reduce_func) +// CHECK-NEXT: [[TMP43:%.*]] = icmp eq i32 [[TMP42]], 1 +// CHECK-NEXT: br i1 [[TMP43]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP44:%.*]] = load float, ptr [[TMP2]], align 4 +// CHECK-NEXT: [[TMP45:%.*]] = load float, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[TMP44]], [[TMP45]] +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP46:%.*]] = load float, ptr [[TMP2]], align 4 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP47:%.*]] = load float, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi float [ [[TMP46]], [[COND_TRUE]] ], [ [[TMP47]], [[COND_FALSE]] ] +// CHECK-NEXT: store float [[COND]], ptr [[TMP2]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = load float, ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP49:%.*]] = load float, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: [[CMP8:%.*]] = fcmp olt float [[TMP48]], [[TMP49]] +// CHECK-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] +// CHECK: cond.true9: +// CHECK-NEXT: [[TMP50:%.*]] = load float, ptr [[TMP4]], align 4 +// CHECK-NEXT: br label [[COND_END11:%.*]] +// CHECK: cond.false10: +// CHECK-NEXT: [[TMP51:%.*]] = load float, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END11]] +// CHECK: cond.end11: +// CHECK-NEXT: [[COND12:%.*]] = phi float [ [[TMP50]], [[COND_TRUE9]] ], [ [[TMP51]], [[COND_FALSE10]] ] +// CHECK-NEXT: store float [[COND12]], ptr [[TMP4]], align 4 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_omp_outlined_omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MAX1:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[MIN1:%.*]]) #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[MAX1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[MAX12:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[MIN13:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// CHECK-NEXT: [[MAX1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX1_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[MIN1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN1_ADDR]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// CHECK-NEXT: [[MAX12_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX12]] to ptr +// CHECK-NEXT: [[MIN13_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN13]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX1]], ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN1]], ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 +// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP4]] to i32 +// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// CHECK-NEXT: store float 0xC7EFFFFFE0000000, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: store float 0x47EFFFFFE0000000, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP6]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[CONV4:%.*]] = sext i32 [[TMP8]] to i64 +// CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV4]], [[TMP9]] +// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x float], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = call float @llvm.maxnum.f32(float [[TMP11]], float [[TMP13]]) +// CHECK-NEXT: store float [[TMP14]], ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x float], ptr [[TMP1]], i64 0, i64 [[IDXPROM5]] +// CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = call float @llvm.minnum.f32(float [[TMP15]], float [[TMP17]]) +// CHECK-NEXT: store float [[TMP18]], ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP6]]) +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: store ptr [[MAX12_ASCAST]], ptr [[TMP21]], align 8 +// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: store ptr [[MIN13_ASCAST]], ptr [[TMP22]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func, ptr @_omp_reduction_inter_warp_copy_func) +// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i32 [[TMP23]], 1 +// CHECK-NEXT: br i1 [[TMP24]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] +// CHECK: .omp.reduction.then: +// CHECK-NEXT: [[TMP25:%.*]] = load float, ptr [[TMP0]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: [[CMP8:%.*]] = fcmp ogt float [[TMP25]], [[TMP26]] +// CHECK-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP0]], align 4 +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP28:%.*]] = load float, ptr [[MAX12_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi float [ [[TMP27]], [[COND_TRUE]] ], [ [[TMP28]], [[COND_FALSE]] ] +// CHECK-NEXT: store float [[COND]], ptr [[TMP0]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[TMP2]], align 4 +// CHECK-NEXT: [[TMP30:%.*]] = load float, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: [[CMP9:%.*]] = fcmp olt float [[TMP29]], [[TMP30]] +// CHECK-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] +// CHECK: cond.true10: +// CHECK-NEXT: [[TMP31:%.*]] = load float, ptr [[TMP2]], align 4 +// CHECK-NEXT: br label [[COND_END12:%.*]] +// CHECK: cond.false11: +// CHECK-NEXT: [[TMP32:%.*]] = load float, ptr [[MIN13_ASCAST]], align 4 +// CHECK-NEXT: br label [[COND_END12]] +// CHECK: cond.end12: +// CHECK-NEXT: [[COND13:%.*]] = phi float [ [[TMP31]], [[COND_TRUE10]] ], [ [[TMP32]], [[COND_FALSE11]] ] +// CHECK-NEXT: store float [[COND13]], ptr [[TMP2]], align 4 +// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] +// CHECK: .omp.reduction.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [2 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT4:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT4]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr float, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP4]], i64 0, i64 1 +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr float, ptr [[TMP19]], i64 1 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i16 +// CHECK-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP22]], i16 [[TMP6]], i16 [[TMP24]]) +// CHECK-NEXT: store i32 [[TMP25]], ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP19]], i64 1 +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], ptr [[TMP20]], align 8 +// CHECK-NEXT: [[TMP28:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP31:%.*]] = and i1 [[TMP29]], [[TMP30]] +// CHECK-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP33:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i16 [[TMP33]], 0 +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP32]], [[TMP34]] +// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP37:%.*]] = and i1 [[TMP35]], [[TMP36]] +// CHECK-NEXT: [[TMP38:%.*]] = or i1 [[TMP28]], [[TMP31]] +// CHECK-NEXT: [[TMP39:%.*]] = or i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_omp_outlined_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR2]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP40:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP41:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP42:%.*]] = and i1 [[TMP40]], [[TMP41]] +// CHECK-NEXT: br i1 [[TMP42]], label [[THEN5:%.*]], label [[ELSE6:%.*]] +// CHECK: then5: +// CHECK-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[TMP43]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP46:%.*]] = load ptr, ptr [[TMP45]], align 8 +// CHECK-NEXT: [[TMP47:%.*]] = load float, ptr [[TMP44]], align 4 +// CHECK-NEXT: store float [[TMP47]], ptr [[TMP46]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP49:%.*]] = load ptr, ptr [[TMP48]], align 8 +// CHECK-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP4]], i64 0, i64 1 +// CHECK-NEXT: [[TMP51:%.*]] = load ptr, ptr [[TMP50]], align 8 +// CHECK-NEXT: [[TMP52:%.*]] = load float, ptr [[TMP49]], align 4 +// CHECK-NEXT: store float [[TMP52]], ptr [[TMP51]], align 4 +// CHECK-NEXT: br label [[IFCONT7:%.*]] +// CHECK: else6: +// CHECK-NEXT: br label [[IFCONT7]] +// CHECK: ifcont7: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4:[0-9]+]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP9]], ptr addrspace(3) [[TMP8]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i32, ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM6:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM6]]) +// CHECK-NEXT: [[WARP_MASTER7:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER7]], label [[THEN8:%.*]], label [[ELSE9:%.*]] +// CHECK: then8: +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP5]], i64 0, i64 1 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP18]], ptr addrspace(3) [[TMP17]], align 4 +// CHECK-NEXT: br label [[IFCONT10:%.*]] +// CHECK: else9: +// CHECK-NEXT: br label [[IFCONT10]] +// CHECK: ifcont10: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM11]]) +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD12:%.*]] = icmp ult i32 [[TMP2]], [[TMP19]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD12]], label [[THEN13:%.*]], label [[ELSE14:%.*]] +// CHECK: then13: +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP5]], i64 0, i64 1 +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = load volatile i32, ptr addrspace(3) [[TMP20]], align 4 +// CHECK-NEXT: store i32 [[TMP23]], ptr [[TMP22]], align 4 +// CHECK-NEXT: br label [[IFCONT15:%.*]] +// CHECK: else14: +// CHECK-NEXT: br label [[IFCONT15]] +// CHECK: ifcont15: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.1 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [2 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT4:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT4]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr float, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i16 +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP12]], i16 [[TMP6]], i16 [[TMP14]]) +// CHECK-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP4]], i64 0, i64 1 +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr float, ptr [[TMP19]], i64 1 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_warp_size() +// CHECK-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i16 +// CHECK-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_shuffle_int32(i32 [[TMP22]], i16 [[TMP6]], i16 [[TMP24]]) +// CHECK-NEXT: store i32 [[TMP25]], ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP19]], i64 1 +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], i64 1 +// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT4_ASCAST]], ptr [[TMP20]], align 8 +// CHECK-NEXT: [[TMP28:%.*]] = icmp eq i16 [[TMP7]], 0 +// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP31:%.*]] = and i1 [[TMP29]], [[TMP30]] +// CHECK-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP7]], 2 +// CHECK-NEXT: [[TMP33:%.*]] = and i16 [[TMP5]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i16 [[TMP33]], 0 +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP32]], [[TMP34]] +// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i16 [[TMP6]], 0 +// CHECK-NEXT: [[TMP37:%.*]] = and i1 [[TMP35]], [[TMP36]] +// CHECK-NEXT: [[TMP38:%.*]] = or i1 [[TMP28]], [[TMP31]] +// CHECK-NEXT: [[TMP39:%.*]] = or i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR2]] +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[TMP40:%.*]] = icmp eq i16 [[TMP7]], 1 +// CHECK-NEXT: [[TMP41:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] +// CHECK-NEXT: [[TMP42:%.*]] = and i1 [[TMP40]], [[TMP41]] +// CHECK-NEXT: br i1 [[TMP42]], label [[THEN5:%.*]], label [[ELSE6:%.*]] +// CHECK: then5: +// CHECK-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[TMP43]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP4]], i64 0, i64 0 +// CHECK-NEXT: [[TMP46:%.*]] = load ptr, ptr [[TMP45]], align 8 +// CHECK-NEXT: [[TMP47:%.*]] = load float, ptr [[TMP44]], align 4 +// CHECK-NEXT: store float [[TMP47]], ptr [[TMP46]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP49:%.*]] = load ptr, ptr [[TMP48]], align 8 +// CHECK-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP4]], i64 0, i64 1 +// CHECK-NEXT: [[TMP51:%.*]] = load ptr, ptr [[TMP50]], align 8 +// CHECK-NEXT: [[TMP52:%.*]] = load float, ptr [[TMP49]], align 4 +// CHECK-NEXT: store float [[TMP52]], ptr [[TMP51]], align 4 +// CHECK-NEXT: br label [[IFCONT7:%.*]] +// CHECK: else6: +// CHECK-NEXT: br label [[IFCONT7]] +// CHECK: ifcont7: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.2 +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP3]], 63 +// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP4]], 6 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]]) +// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] +// CHECK: then: +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP9]], ptr addrspace(3) [[TMP8]], align 4 +// CHECK-NEXT: br label [[IFCONT:%.*]] +// CHECK: else: +// CHECK-NEXT: br label [[IFCONT]] +// CHECK: ifcont: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM2]]) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP2]], [[TMP10]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN3:%.*]], label [[ELSE4:%.*]] +// CHECK: then3: +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP5]], i64 0, i64 0 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = load volatile i32, ptr addrspace(3) [[TMP11]], align 4 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4 +// CHECK-NEXT: br label [[IFCONT5:%.*]] +// CHECK: else4: +// CHECK-NEXT: br label [[IFCONT5]] +// CHECK: ifcont5: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM6:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM6]]) +// CHECK-NEXT: [[WARP_MASTER7:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 +// CHECK-NEXT: br i1 [[WARP_MASTER7]], label [[THEN8:%.*]], label [[ELSE9:%.*]] +// CHECK: then8: +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP5]], i64 0, i64 1 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 +// CHECK-NEXT: store volatile i32 [[TMP18]], ptr addrspace(3) [[TMP17]], align 4 +// CHECK-NEXT: br label [[IFCONT10:%.*]] +// CHECK: else9: +// CHECK-NEXT: br label [[IFCONT10]] +// CHECK: ifcont10: +// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM11]]) +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[IS_ACTIVE_THREAD12:%.*]] = icmp ult i32 [[TMP2]], [[TMP19]] +// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD12]], label [[THEN13:%.*]], label [[ELSE14:%.*]] +// CHECK: then13: +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP2]] +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP5]], i64 0, i64 1 +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = load volatile i32, ptr addrspace(3) [[TMP20]], align 4 +// CHECK-NEXT: store i32 [[TMP23]], ptr [[TMP22]], align 4 +// CHECK-NEXT: br label [[IFCONT15:%.*]] +// CHECK: else14: +// CHECK-NEXT: br label [[IFCONT15]] +// CHECK: ifcont15: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[TMP7]], align 4 +// CHECK-NEXT: store float [[TMP10]], ptr [[TMP9]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i64 0, i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP13]], i32 0, i32 1 +// CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[TMP12]], align 4 +// CHECK-NEXT: store float [[TMP15]], ptr [[TMP14]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP9]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[TMP10]], ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_omp_outlined_omp$reduction$reduction_func"(ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr [[TMP11]]) #[[ATTR2]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[TMP9]], align 4 +// CHECK-NEXT: store float [[TMP10]], ptr [[TMP7]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[TMP3]], i64 0, i64 1 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP4]], i32 [[TMP5]] +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP13]], i32 0, i32 1 +// CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[TMP14]], align 4 +// CHECK-NEXT: store float [[TMP15]], ptr [[TMP12]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x ptr], align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 1 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP3]], i32 [[TMP4]] +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY]], ptr [[TMP9]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[TMP10]], ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: call void @"{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_omp_outlined_omp$reduction$reduction_func"(ptr [[TMP11]], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]]) #[[ATTR2]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l34 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[TMP0:%.*]], i64 noundef [[TMP1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[SUM1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM1_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP6:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP6]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i32 +// CHECK-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP10]] to i32 +// CHECK-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP13:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[TMP12]] +// CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], 1 +// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32 +// CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP15]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK-NEXT: store i32 [[TMP18]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP23]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x float], ptr [[TMP5]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// CHECK-NEXT: [[TMP27:%.*]] = fadd float [[TMP26]], [[TMP25]] +// CHECK-NEXT: store float [[TMP27]], ptr addrspace(5) [[TMP6]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[NVPTX_NUM_THREADS4]], [[TMP19]] +// CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP31:%.*]] = add i32 [[TMP29]], [[TMP30]] +// CHECK-NEXT: store i32 [[TMP31]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 +// CHECK-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP34:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// CHECK-NEXT: call void @__kmpc_xteamr_f_16x64_fast_sum(float [[TMP34]], ptr [[TMP4]], ptr [[TMP32]], ptr [[TMP33]], ptr @__kmpc_rfun_sum_f, ptr @__kmpc_rfun_sum_lds_f, float 0.000000e+00, i64 [[TMP20]], i32 [[TMP19]], i32 0) +// CHECK-NEXT: ret void +// diff --git a/clang/test/OpenMP/xteam_red_min_max_small_precision.c b/clang/test/OpenMP/xteam_red_min_max_small_precision.c new file mode 100644 index 0000000000000..8c699afd3a46a --- /dev/null +++ b/clang/test/OpenMP/xteam_red_min_max_small_precision.c @@ -0,0 +1,560 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// expected-no-diagnostics + +#define N 10000 + +int main() { + _Float16 a[N]; + __bf16 b[N]; + short c[N]; + + for (int i = 0; i < N; i++) { + a[i] = i; + b[i] = i; + c[i] = i; + } + + _Float16 min1 = 10; + __bf16 min2 = 11; + short min3 = 12; + + _Float16 max1 = 0; + __bf16 max2 = 0; + short max3 = -10; + +#pragma omp target teams distribute parallel for reduction(min:min1) + for (int j = 0; j < N; j = j + 1) + min1 = __builtin_fmin(min1, a[j]); + +#pragma omp target teams distribute parallel for reduction(min:min2) + for (int j = 0; j < N; j = j + 2) + min2 = __builtin_fmin(min2, b[j]); + +#pragma omp target teams distribute parallel for reduction(min:min3) + for (int j = 0; j < N; j = j + 3) + min3 = __builtin_fmin(c[j], min3); + +#pragma omp target teams distribute parallel for reduction(max : max1) + for (int j = 0; j < N; j = j + 1) + max1 = __builtin_fmax(max1, a[j]); + +#pragma omp target teams distribute parallel for reduction(max : max2) + for (int j = 0; j < N; j = j + 2) + max2 = __builtin_fmax(max2, b[j]); + +#pragma omp target teams distribute parallel for reduction(max : max3) + for (int j = 0; j < N; j = j + 3) + max3 = __builtin_fmax(c[j], max3); +} + +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MIN1:%.*]], ptr noundef nonnull align 2 dereferenceable(20000) [[A:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN1_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN1]], ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP4:%.*]] = alloca half, align 2, addrspace(5) +// CHECK-NEXT: store half 0xH7C00, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 9999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[TMP6]] +// CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], 1 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10000 x half], ptr [[TMP3]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load half, ptr [[ARRAYIDX]], align 2 +// CHECK-NEXT: [[CONV:%.*]] = fpext half [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load half, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: [[TMP20:%.*]] = fptrunc double [[CONV]] to half +// CHECK-NEXT: [[XTEAM_MIN:%.*]] = call half @llvm.minnum.f16(half [[TMP19]], half [[TMP20]]) +// CHECK-NEXT: store half [[XTEAM_MIN]], ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP12]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load half, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: call void @__kmpc_xteamr_h_16x64(half [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_min_h, ptr @__kmpc_rfun_min_lds_h, half 0xH7C00, i64 [[TMP13]], i32 [[TMP12]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l31 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MIN2:%.*]], ptr noundef nonnull align 2 dereferenceable(20000) [[B:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN2_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN2_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN2_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN2]], ptr [[MIN2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP4:%.*]] = alloca bfloat, align 2, addrspace(5) +// CHECK-NEXT: store bfloat 0xR7F80, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 4999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[TMP6]] +// CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], 1 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 2 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10000 x bfloat], ptr [[TMP3]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load bfloat, ptr [[ARRAYIDX]], align 2 +// CHECK-NEXT: [[CONV:%.*]] = fpext bfloat [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load bfloat, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: [[TMP20:%.*]] = fptrunc double [[CONV]] to bfloat +// CHECK-NEXT: [[XTEAM_MIN:%.*]] = call bfloat @llvm.minnum.bf16(bfloat [[TMP19]], bfloat [[TMP20]]) +// CHECK-NEXT: store bfloat [[XTEAM_MIN]], ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP12]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load bfloat, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: call void @__kmpc_xteamr_bf_16x64(bfloat [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_min_bf, ptr @__kmpc_rfun_min_lds_bf, bfloat 0xR7F80, i64 [[TMP13]], i32 [[TMP12]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l35 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MIN3:%.*]], ptr noundef nonnull align 2 dereferenceable(20000) [[C:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MIN3_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MIN3_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MIN3_ADDR]] to ptr +// CHECK-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MIN3]], ptr [[MIN3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MIN3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP4:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: store i16 32767, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 3333, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[TMP6]] +// CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], 1 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 3 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10000 x i16], ptr [[TMP3]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 +// CHECK-NEXT: [[CONV:%.*]] = sitofp i16 [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load i16, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: [[TMP20:%.*]] = fptosi double [[CONV]] to i16 +// CHECK-NEXT: [[XTEAM_MIN:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP19]], i16 [[TMP20]]) +// CHECK-NEXT: store i16 [[XTEAM_MIN]], ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP12]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load i16, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: call void @__kmpc_xteamr_s_16x64(i16 [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_min_s, ptr @__kmpc_rfun_min_lds_s, i16 32767, i64 [[TMP13]], i32 [[TMP12]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MAX1:%.*]], ptr noundef nonnull align 2 dereferenceable(20000) [[A:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX1_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX1_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX1_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX1]], ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MAX1_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP4:%.*]] = alloca half, align 2, addrspace(5) +// CHECK-NEXT: store half 0xHFC00, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 9999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[TMP6]] +// CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], 1 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10000 x half], ptr [[TMP3]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load half, ptr [[ARRAYIDX]], align 2 +// CHECK-NEXT: [[CONV:%.*]] = fpext half [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load half, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: [[TMP20:%.*]] = fptrunc double [[CONV]] to half +// CHECK-NEXT: [[XTEAM_MAX:%.*]] = call half @llvm.maxnum.f16(half [[TMP19]], half [[TMP20]]) +// CHECK-NEXT: store half [[XTEAM_MAX]], ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP12]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load half, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: call void @__kmpc_xteamr_h_16x64(half [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_max_h, ptr @__kmpc_rfun_max_lds_h, half 0xHFC00, i64 [[TMP13]], i32 [[TMP12]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MAX2:%.*]], ptr noundef nonnull align 2 dereferenceable(20000) [[B:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX2_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX2_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX2_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX2]], ptr [[MAX2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MAX2_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP4:%.*]] = alloca bfloat, align 2, addrspace(5) +// CHECK-NEXT: store bfloat 0xRFF80, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 4999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[TMP6]] +// CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], 1 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 2 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10000 x bfloat], ptr [[TMP3]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load bfloat, ptr [[ARRAYIDX]], align 2 +// CHECK-NEXT: [[CONV:%.*]] = fpext bfloat [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load bfloat, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: [[TMP20:%.*]] = fptrunc double [[CONV]] to bfloat +// CHECK-NEXT: [[XTEAM_MAX:%.*]] = call bfloat @llvm.maxnum.bf16(bfloat [[TMP19]], bfloat [[TMP20]]) +// CHECK-NEXT: store bfloat [[XTEAM_MAX]], ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP12]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load bfloat, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: call void @__kmpc_xteamr_bf_16x64(bfloat [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_max_bf, ptr @__kmpc_rfun_max_lds_bf, bfloat 0xRFF80, i64 [[TMP13]], i32 [[TMP12]], i32 1) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l47 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[MAX3:%.*]], ptr noundef nonnull align 2 dereferenceable(20000) [[C:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[MAX3_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[MAX3_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[MAX3_ADDR]] to ptr +// CHECK-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[MAX3]], ptr [[MAX3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[MAX3_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP4:%.*]] = alloca i16, align 2, addrspace(5) +// CHECK-NEXT: store i16 -32768, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 3333, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], [[TMP6]] +// CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], 1 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], [[TMP10]] +// CHECK-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP11]] to i64 +// CHECK-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 3 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10000 x i16], ptr [[TMP3]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 +// CHECK-NEXT: [[CONV:%.*]] = sitofp i16 [[TMP18]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load i16, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: [[TMP20:%.*]] = fptosi double [[CONV]] to i16 +// CHECK-NEXT: [[XTEAM_MAX:%.*]] = call i16 @llvm.smax.i16(i16 [[TMP19]], i16 [[TMP20]]) +// CHECK-NEXT: store i16 [[XTEAM_MAX]], ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[NVPTX_NUM_THREADS2]], [[TMP12]] +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], 1 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP22]], [[TMP23]] +// CHECK-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load i16, ptr addrspace(5) [[TMP4]], align 2 +// CHECK-NEXT: call void @__kmpc_xteamr_s_16x64(i16 [[TMP27]], ptr [[TMP2]], ptr [[TMP25]], ptr [[TMP26]], ptr @__kmpc_rfun_max_s, ptr @__kmpc_rfun_max_lds_s, i16 -32768, i64 [[TMP13]], i32 [[TMP12]], i32 1) +// CHECK-NEXT: ret void +// diff --git a/clang/test/OpenMP/xteam_red_reference.cpp b/clang/test/OpenMP/xteam_red_reference.cpp new file mode 100644 index 0000000000000..46249fa1408fe --- /dev/null +++ b/clang/test/OpenMP/xteam_red_reference.cpp @@ -0,0 +1,112 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// expected-no-diagnostics + +void compute_reduced_sum(int n, int &x) { + #pragma omp target teams distribute parallel for reduction(+ : x) + for (int i = 0; i < n; ++i) + x += i; + } + + int main() + { + int n = 1000; + int sum = 0; + compute_reduced_sum(n, sum); + } + +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19compute_reduced_sumiRi_l7 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[X:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[TMP:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr +// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// CHECK-NEXT: [[DOTCAPTURE_EXPR_2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_2]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[X]], ptr [[X_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[X_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[TMP_ASCAST]], align 8 +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP3:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 0, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], 1 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP11]], [[TMP12]] +// CHECK-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP13]] to i64 +// CHECK-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP20]], [[TMP19]] +// CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[NVPTX_NUM_THREADS4]], [[TMP14]] +// CHECK-NEXT: [[TMP23:%.*]] = mul i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP25:%.*]] = add i32 [[TMP23]], [[TMP24]] +// CHECK-NEXT: store i32 [[TMP25]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTADDR1_ASCAST]], align 8 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr addrspace(5) [[TMP3]], align 4 +// CHECK-NEXT: call void @__kmpc_xteamr_i_16x64(i32 [[TMP29]], ptr [[TMP28]], ptr [[TMP26]], ptr [[TMP27]], ptr @__kmpc_rfun_sum_i, ptr @__kmpc_rfun_sum_lds_i, i32 0, i64 [[TMP15]], i32 [[TMP14]], i32 1) +// CHECK-NEXT: ret void +// diff --git a/clang/test/OpenMP/xteam_red_small_precision.c b/clang/test/OpenMP/xteam_red_small_precision.c new file mode 100644 index 0000000000000..6324b2a2a603b --- /dev/null +++ b/clang/test/OpenMP/xteam_red_small_precision.c @@ -0,0 +1,344 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-ignore-env-vars -fopenmp-assume-no-nested-parallelism -fopenmp-assume-no-thread-state -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-ignore-env-vars -fopenmp-assume-no-nested-parallelism -fopenmp-assume-no-thread-state -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s +// expected-no-diagnostics + +int main() +{ + int N = 100; + + _Float16 a[N]; + __bf16 b[N]; + short c[N]; + + for (int i=0; i + +#ifdef NOLOOP +#define NUM_TEAMS 100 +#define NUM_THREADS 256 +#define N NUM_TEAMS * NUM_THREADS +#else +#define N 1000000 +#endif + +template +void run_test() +{ + T sum = T(0); + T *a = new T[N]; + T *b = new T[N]; + +#ifdef NOLOOP + #pragma omp target teams distribute parallel for reduction(inscan, +:sum) map(to: a[0:N]) map(tofrom: b[0:N]) num_teams(NUM_TEAMS) num_threads(NUM_THREADS) +#else + #pragma omp target teams distribute parallel for reduction(inscan, +:sum) map(to: a[0:N]) map(tofrom: b[0:N]) +#endif + for(int i = 0; i < N; i++) { + sum += a[i]; + #pragma omp scan inclusive(sum) + b[i] = sum; + } + + sum = T(0); +#ifdef NOLOOP + #pragma omp target teams distribute parallel for reduction(inscan, +:sum) map(to: a[0:N]) map(tofrom: b[0:N]) num_teams(NUM_TEAMS) num_threads(NUM_THREADS) +#else + #pragma omp target teams distribute parallel for reduction(inscan, +:sum) map(to: a[0:N]) map(tofrom: b[0:N]) +#endif + for(int i = 0; i < N; i++) { + b[i] = sum; + #pragma omp scan exclusive(sum) + sum += a[i]; + } + + delete[] a; + delete[] b; +} + +int main() { + run_test(); + run_test(); + run_test(); + run_test(); + run_test(); + run_test(); + return 0; +} +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIiEvv_l35 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29:![0-9]+]], !align [[META30:![0-9]+]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 0, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP29]] +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], [[TMP30]] +// CHECK-NEXT: [[TMP34:%.*]] = icmp ule i32 [[TMP32]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP34]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP35]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP37:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP38]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP37]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = add i32 [[TMP40]], [[TMP39]] +// CHECK-NEXT: store i32 [[TMP41]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP43:%.*]] = zext i32 [[TMP42]] to i64 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP45:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP46]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[TMP45]], i64 [[IDXPROM9]] +// CHECK-NEXT: store i32 [[TMP44]], ptr [[ARRAYIDX10]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr [[TMP31]], i32 [[TMP47]] +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP49]], ptr [[TMP48]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = add i32 1, [[TMP50]] +// CHECK-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_i_8x64(i32 [[TMP55]], ptr [[TMP54]], ptr [[TMP4]], ptr [[TMP52]], ptr [[TMP53]], ptr @__kmpc_rfun_sum_i, ptr @__kmpc_rfun_sum_lds_i, i32 0, i64 [[TMP16]], i32 [[TMP15]]) +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIiEvv_l35_1 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 0, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_phase2_i_8x64(ptr [[TMP29]], i32 [[PADDED_SEGMENT_SIZE]], ptr [[TMP28]], ptr [[TMP30]], ptr @__kmpc_rfun_sum_i, i32 0, i64 [[TMP16]], i32 1) +// CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP32]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = icmp ult i32 [[TMP36]], [[TMP34]] +// CHECK-NEXT: [[TMP38:%.*]] = icmp ule i32 [[TMP36]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr [[TMP35]], i32 [[TMP41]] +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4 +// CHECK-NEXT: store i32 [[TMP43]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP45]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP44]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = add i32 [[TMP47]], [[TMP46]] +// CHECK-NEXT: store i32 [[TMP48]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP6]], i64 [[TMP50]] +// CHECK-NEXT: [[TMP51:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP51]], ptr [[TMP4]], align 4 +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP53]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[TMP52]], i64 [[IDXPROM10]] +// CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP54]], ptr [[ARRAYIDX11]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP56:%.*]] = getelementptr i32, ptr [[TMP35]], i32 [[TMP55]] +// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP57]], ptr [[TMP56]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP59:%.*]] = add i32 1, [[TMP58]] +// CHECK-NEXT: store i32 [[TMP59]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIiEvv_l47 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 0, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP29]] +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], [[TMP30]] +// CHECK-NEXT: [[TMP34:%.*]] = icmp ule i32 [[TMP32]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP34]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP35]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP39]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP38]], i64 [[IDXPROM]] +// CHECK-NEXT: store i32 [[TMP37]], ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = zext i32 [[TMP40]] to i64 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP42:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP43]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[TMP42]], i64 [[IDXPROM9]] +// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP45]], [[TMP44]] +// CHECK-NEXT: store i32 [[TMP46]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr [[TMP31]], i32 [[TMP47]] +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP49]], ptr [[TMP48]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = add i32 1, [[TMP50]] +// CHECK-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_i_8x64(i32 [[TMP55]], ptr [[TMP54]], ptr [[TMP4]], ptr [[TMP52]], ptr [[TMP53]], ptr @__kmpc_rfun_sum_i, ptr @__kmpc_rfun_sum_lds_i, i32 0, i64 [[TMP16]], i32 [[TMP15]]) +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIiEvv_l47_1 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 0, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_phase2_i_8x64(ptr [[TMP29]], i32 [[PADDED_SEGMENT_SIZE]], ptr [[TMP28]], ptr [[TMP30]], ptr @__kmpc_rfun_sum_i, i32 0, i64 [[TMP16]], i32 0) +// CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP32]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = icmp ult i32 [[TMP36]], [[TMP34]] +// CHECK-NEXT: [[TMP38:%.*]] = icmp ule i32 [[TMP36]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr [[TMP35]], i32 [[TMP41]] +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4 +// CHECK-NEXT: store i32 [[TMP43]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP45]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP44]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP46]], ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP47]] to i64 +// CHECK-NEXT: [[TMP49:%.*]] = icmp eq i64 [[TMP48]], 0 +// CHECK-NEXT: br i1 [[TMP49]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// CHECK: omp.exclusive.dec: +// CHECK-NEXT: [[TMP50:%.*]] = sub nuw i64 [[TMP48]], 1 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP6]], i64 [[TMP50]] +// CHECK-NEXT: [[TMP51:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP51]], ptr [[TMP4]], align 4 +// CHECK-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// CHECK: omp.exclusive.copy.exit: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP53]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[TMP52]], i64 [[IDXPROM10]] +// CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP56:%.*]] = add i32 [[TMP55]], [[TMP54]] +// CHECK-NEXT: store i32 [[TMP56]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = getelementptr i32, ptr [[TMP35]], i32 [[TMP57]] +// CHECK-NEXT: [[TMP59:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP59]], ptr [[TMP58]], align 4 +// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP61:%.*]] = add i32 1, [[TMP60]] +// CHECK-NEXT: store i32 [[TMP61]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIjEvv_l35 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 0, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP29]] +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], [[TMP30]] +// CHECK-NEXT: [[TMP34:%.*]] = icmp ule i32 [[TMP32]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP34]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP35]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP37:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP38]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP37]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = add i32 [[TMP40]], [[TMP39]] +// CHECK-NEXT: store i32 [[TMP41]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP43:%.*]] = zext i32 [[TMP42]] to i64 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP45:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP46]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[TMP45]], i64 [[IDXPROM9]] +// CHECK-NEXT: store i32 [[TMP44]], ptr [[ARRAYIDX10]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr [[TMP31]], i32 [[TMP47]] +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP49]], ptr [[TMP48]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = add i32 1, [[TMP50]] +// CHECK-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_i_8x64(i32 [[TMP55]], ptr [[TMP54]], ptr [[TMP4]], ptr [[TMP52]], ptr [[TMP53]], ptr @__kmpc_rfun_sum_i, ptr @__kmpc_rfun_sum_lds_i, i32 0, i64 [[TMP16]], i32 [[TMP15]]) +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIjEvv_l35_1 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 0, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_phase2_i_8x64(ptr [[TMP29]], i32 [[PADDED_SEGMENT_SIZE]], ptr [[TMP28]], ptr [[TMP30]], ptr @__kmpc_rfun_sum_i, i32 0, i64 [[TMP16]], i32 1) +// CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP32]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = icmp ult i32 [[TMP36]], [[TMP34]] +// CHECK-NEXT: [[TMP38:%.*]] = icmp ule i32 [[TMP36]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr [[TMP35]], i32 [[TMP41]] +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4 +// CHECK-NEXT: store i32 [[TMP43]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP45]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP44]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = add i32 [[TMP47]], [[TMP46]] +// CHECK-NEXT: store i32 [[TMP48]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP6]], i64 [[TMP50]] +// CHECK-NEXT: [[TMP51:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP51]], ptr [[TMP4]], align 4 +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP53]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[TMP52]], i64 [[IDXPROM10]] +// CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP54]], ptr [[ARRAYIDX11]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP56:%.*]] = getelementptr i32, ptr [[TMP35]], i32 [[TMP55]] +// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP57]], ptr [[TMP56]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP59:%.*]] = add i32 1, [[TMP58]] +// CHECK-NEXT: store i32 [[TMP59]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIjEvv_l47 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 0, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP29]] +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], [[TMP30]] +// CHECK-NEXT: [[TMP34:%.*]] = icmp ule i32 [[TMP32]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP34]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP35]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP39]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP38]], i64 [[IDXPROM]] +// CHECK-NEXT: store i32 [[TMP37]], ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = zext i32 [[TMP40]] to i64 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP42:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP43]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[TMP42]], i64 [[IDXPROM9]] +// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP45]], [[TMP44]] +// CHECK-NEXT: store i32 [[TMP46]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr [[TMP31]], i32 [[TMP47]] +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP49]], ptr [[TMP48]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = add i32 1, [[TMP50]] +// CHECK-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_i_8x64(i32 [[TMP55]], ptr [[TMP54]], ptr [[TMP4]], ptr [[TMP52]], ptr [[TMP53]], ptr @__kmpc_rfun_sum_i, ptr @__kmpc_rfun_sum_lds_i, i32 0, i64 [[TMP16]], i32 [[TMP15]]) +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIjEvv_l47_1 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 0, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_phase2_i_8x64(ptr [[TMP29]], i32 [[PADDED_SEGMENT_SIZE]], ptr [[TMP28]], ptr [[TMP30]], ptr @__kmpc_rfun_sum_i, i32 0, i64 [[TMP16]], i32 0) +// CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP32]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = icmp ult i32 [[TMP36]], [[TMP34]] +// CHECK-NEXT: [[TMP38:%.*]] = icmp ule i32 [[TMP36]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr [[TMP35]], i32 [[TMP41]] +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4 +// CHECK-NEXT: store i32 [[TMP43]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP45]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP44]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP46]], ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP47]] to i64 +// CHECK-NEXT: [[TMP49:%.*]] = icmp eq i64 [[TMP48]], 0 +// CHECK-NEXT: br i1 [[TMP49]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// CHECK: omp.exclusive.dec: +// CHECK-NEXT: [[TMP50:%.*]] = sub nuw i64 [[TMP48]], 1 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP6]], i64 [[TMP50]] +// CHECK-NEXT: [[TMP51:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP51]], ptr [[TMP4]], align 4 +// CHECK-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// CHECK: omp.exclusive.copy.exit: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP53]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[TMP52]], i64 [[IDXPROM10]] +// CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP56:%.*]] = add i32 [[TMP55]], [[TMP54]] +// CHECK-NEXT: store i32 [[TMP56]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = getelementptr i32, ptr [[TMP35]], i32 [[TMP57]] +// CHECK-NEXT: [[TMP59:%.*]] = load i32, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 [[TMP59]], ptr [[TMP58]], align 4 +// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP61:%.*]] = add i32 1, [[TMP60]] +// CHECK-NEXT: store i32 [[TMP61]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIlEvv_l35 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META40:![0-9]+]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: store i64 0, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP29]] +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], [[TMP30]] +// CHECK-NEXT: [[TMP34:%.*]] = icmp ule i32 [[TMP32]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP34]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP35]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i64 0, ptr [[SUM8_ASCAST]], align 8 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP37:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP38]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP37]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP39:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP41:%.*]] = add i64 [[TMP40]], [[TMP39]] +// CHECK-NEXT: store i64 [[TMP41]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP43:%.*]] = zext i32 [[TMP42]] to i64 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr [[TMP4]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP46]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i64, ptr [[TMP45]], i64 [[IDXPROM9]] +// CHECK-NEXT: store i64 [[TMP44]], ptr [[ARRAYIDX10]], align 8 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr i64, ptr [[TMP31]], i32 [[TMP47]] +// CHECK-NEXT: [[TMP49:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i64 [[TMP49]], ptr [[TMP48]], align 8 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = add i32 1, [[TMP50]] +// CHECK-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: call void @__kmpc_xteams_l_8x64(i64 [[TMP55]], ptr [[TMP54]], ptr [[TMP4]], ptr [[TMP52]], ptr [[TMP53]], ptr @__kmpc_rfun_sum_l, ptr @__kmpc_rfun_sum_lds_l, i64 0, i64 [[TMP16]], i32 [[TMP15]]) +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIlEvv_l35_1 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: store i64 0, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: call void @__kmpc_xteams_phase2_l_8x64(ptr [[TMP29]], i32 [[PADDED_SEGMENT_SIZE]], ptr [[TMP28]], ptr [[TMP30]], ptr @__kmpc_rfun_sum_l, i64 0, i64 [[TMP16]], i32 1) +// CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP32]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = icmp ult i32 [[TMP36]], [[TMP34]] +// CHECK-NEXT: [[TMP38:%.*]] = icmp ule i32 [[TMP36]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = getelementptr i64, ptr [[TMP35]], i32 [[TMP41]] +// CHECK-NEXT: [[TMP43:%.*]] = load i64, ptr [[TMP42]], align 8 +// CHECK-NEXT: store i64 [[TMP43]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i64 0, ptr [[SUM8_ASCAST]], align 8 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP45]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP44]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP46:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: [[TMP47:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP48:%.*]] = add i64 [[TMP47]], [[TMP46]] +// CHECK-NEXT: store i64 [[TMP48]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw i64, ptr [[TMP6]], i64 [[TMP50]] +// CHECK-NEXT: [[TMP51:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i64 [[TMP51]], ptr [[TMP4]], align 8 +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP53]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i64, ptr [[TMP52]], i64 [[IDXPROM10]] +// CHECK-NEXT: [[TMP54:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i64 [[TMP54]], ptr [[ARRAYIDX11]], align 8 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP56:%.*]] = getelementptr i64, ptr [[TMP35]], i32 [[TMP55]] +// CHECK-NEXT: [[TMP57:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i64 [[TMP57]], ptr [[TMP56]], align 8 +// CHECK-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP59:%.*]] = add i32 1, [[TMP58]] +// CHECK-NEXT: store i32 [[TMP59]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIlEvv_l47 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: store i64 0, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP29]] +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], [[TMP30]] +// CHECK-NEXT: [[TMP34:%.*]] = icmp ule i32 [[TMP32]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP34]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP35]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i64 0, ptr [[SUM8_ASCAST]], align 8 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[TMP4]], align 8 +// CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP39]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP38]], i64 [[IDXPROM]] +// CHECK-NEXT: store i64 [[TMP37]], ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = zext i32 [[TMP40]] to i64 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP42:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP43]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i64, ptr [[TMP42]], i64 [[IDXPROM9]] +// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr [[ARRAYIDX10]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP46:%.*]] = add i64 [[TMP45]], [[TMP44]] +// CHECK-NEXT: store i64 [[TMP46]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr i64, ptr [[TMP31]], i32 [[TMP47]] +// CHECK-NEXT: [[TMP49:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i64 [[TMP49]], ptr [[TMP48]], align 8 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = add i32 1, [[TMP50]] +// CHECK-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: call void @__kmpc_xteams_l_8x64(i64 [[TMP55]], ptr [[TMP54]], ptr [[TMP4]], ptr [[TMP52]], ptr [[TMP53]], ptr @__kmpc_rfun_sum_l, ptr @__kmpc_rfun_sum_lds_l, i64 0, i64 [[TMP16]], i32 [[TMP15]]) +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIlEvv_l47_1 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: store i64 0, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: call void @__kmpc_xteams_phase2_l_8x64(ptr [[TMP29]], i32 [[PADDED_SEGMENT_SIZE]], ptr [[TMP28]], ptr [[TMP30]], ptr @__kmpc_rfun_sum_l, i64 0, i64 [[TMP16]], i32 0) +// CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP32]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = icmp ult i32 [[TMP36]], [[TMP34]] +// CHECK-NEXT: [[TMP38:%.*]] = icmp ule i32 [[TMP36]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = getelementptr i64, ptr [[TMP35]], i32 [[TMP41]] +// CHECK-NEXT: [[TMP43:%.*]] = load i64, ptr [[TMP42]], align 8 +// CHECK-NEXT: store i64 [[TMP43]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i64 0, ptr [[SUM8_ASCAST]], align 8 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP45]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP44]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP46:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i64 [[TMP46]], ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP47]] to i64 +// CHECK-NEXT: [[TMP49:%.*]] = icmp eq i64 [[TMP48]], 0 +// CHECK-NEXT: br i1 [[TMP49]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// CHECK: omp.exclusive.dec: +// CHECK-NEXT: [[TMP50:%.*]] = sub nuw i64 [[TMP48]], 1 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw i64, ptr [[TMP6]], i64 [[TMP50]] +// CHECK-NEXT: [[TMP51:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i64 [[TMP51]], ptr [[TMP4]], align 8 +// CHECK-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// CHECK: omp.exclusive.copy.exit: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP53]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i64, ptr [[TMP52]], i64 [[IDXPROM10]] +// CHECK-NEXT: [[TMP54:%.*]] = load i64, ptr [[ARRAYIDX11]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP56:%.*]] = add i64 [[TMP55]], [[TMP54]] +// CHECK-NEXT: store i64 [[TMP56]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = getelementptr i64, ptr [[TMP35]], i32 [[TMP57]] +// CHECK-NEXT: [[TMP59:%.*]] = load i64, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i64 [[TMP59]], ptr [[TMP58]], align 8 +// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP61:%.*]] = add i32 1, [[TMP60]] +// CHECK-NEXT: store i32 [[TMP61]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIdEvv_l35 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-NEXT: store double 0.000000e+00, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP29]] +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], [[TMP30]] +// CHECK-NEXT: [[TMP34:%.*]] = icmp ule i32 [[TMP32]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP34]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP35]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store double 0.000000e+00, ptr [[SUM8_ASCAST]], align 8 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP37:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP38]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP37]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP39:%.*]] = load double, ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: [[TMP40:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP41:%.*]] = fadd double [[TMP40]], [[TMP39]] +// CHECK-NEXT: store double [[TMP41]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP43:%.*]] = zext i32 [[TMP42]] to i64 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load double, ptr [[TMP4]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP46]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, ptr [[TMP45]], i64 [[IDXPROM9]] +// CHECK-NEXT: store double [[TMP44]], ptr [[ARRAYIDX10]], align 8 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr double, ptr [[TMP31]], i32 [[TMP47]] +// CHECK-NEXT: [[TMP49:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store double [[TMP49]], ptr [[TMP48]], align 8 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = add i32 1, [[TMP50]] +// CHECK-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: call void @__kmpc_xteams_d_8x64(double [[TMP55]], ptr [[TMP54]], ptr [[TMP4]], ptr [[TMP52]], ptr [[TMP53]], ptr @__kmpc_rfun_sum_d, ptr @__kmpc_rfun_sum_lds_d, double 0.000000e+00, i64 [[TMP16]], i32 [[TMP15]]) +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIdEvv_l35_1 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-NEXT: store double 0.000000e+00, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: call void @__kmpc_xteams_phase2_d_8x64(ptr [[TMP29]], i32 [[PADDED_SEGMENT_SIZE]], ptr [[TMP28]], ptr [[TMP30]], ptr @__kmpc_rfun_sum_d, double 0.000000e+00, i64 [[TMP16]], i32 1) +// CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP32]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = icmp ult i32 [[TMP36]], [[TMP34]] +// CHECK-NEXT: [[TMP38:%.*]] = icmp ule i32 [[TMP36]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = getelementptr double, ptr [[TMP35]], i32 [[TMP41]] +// CHECK-NEXT: [[TMP43:%.*]] = load double, ptr [[TMP42]], align 8 +// CHECK-NEXT: store double [[TMP43]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store double 0.000000e+00, ptr [[SUM8_ASCAST]], align 8 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP45]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP44]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP46:%.*]] = load double, ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: [[TMP47:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP48:%.*]] = fadd double [[TMP47]], [[TMP46]] +// CHECK-NEXT: store double [[TMP48]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw double, ptr [[TMP6]], i64 [[TMP50]] +// CHECK-NEXT: [[TMP51:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store double [[TMP51]], ptr [[TMP4]], align 8 +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP53]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, ptr [[TMP52]], i64 [[IDXPROM10]] +// CHECK-NEXT: [[TMP54:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store double [[TMP54]], ptr [[ARRAYIDX11]], align 8 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP56:%.*]] = getelementptr double, ptr [[TMP35]], i32 [[TMP55]] +// CHECK-NEXT: [[TMP57:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store double [[TMP57]], ptr [[TMP56]], align 8 +// CHECK-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP59:%.*]] = add i32 1, [[TMP58]] +// CHECK-NEXT: store i32 [[TMP59]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIdEvv_l47 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-NEXT: store double 0.000000e+00, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP29]] +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], [[TMP30]] +// CHECK-NEXT: [[TMP34:%.*]] = icmp ule i32 [[TMP32]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP34]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP35]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store double 0.000000e+00, ptr [[SUM8_ASCAST]], align 8 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP37:%.*]] = load double, ptr [[TMP4]], align 8 +// CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP39]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP38]], i64 [[IDXPROM]] +// CHECK-NEXT: store double [[TMP37]], ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = zext i32 [[TMP40]] to i64 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP42:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP43]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, ptr [[TMP42]], i64 [[IDXPROM9]] +// CHECK-NEXT: [[TMP44:%.*]] = load double, ptr [[ARRAYIDX10]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP46:%.*]] = fadd double [[TMP45]], [[TMP44]] +// CHECK-NEXT: store double [[TMP46]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr double, ptr [[TMP31]], i32 [[TMP47]] +// CHECK-NEXT: [[TMP49:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store double [[TMP49]], ptr [[TMP48]], align 8 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = add i32 1, [[TMP50]] +// CHECK-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: call void @__kmpc_xteams_d_8x64(double [[TMP55]], ptr [[TMP54]], ptr [[TMP4]], ptr [[TMP52]], ptr [[TMP53]], ptr @__kmpc_rfun_sum_d, ptr @__kmpc_rfun_sum_lds_d, double 0.000000e+00, i64 [[TMP16]], i32 [[TMP15]]) +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIdEvv_l47_1 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META40]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-NEXT: store double 0.000000e+00, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: call void @__kmpc_xteams_phase2_d_8x64(ptr [[TMP29]], i32 [[PADDED_SEGMENT_SIZE]], ptr [[TMP28]], ptr [[TMP30]], ptr @__kmpc_rfun_sum_d, double 0.000000e+00, i64 [[TMP16]], i32 0) +// CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP32]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = icmp ult i32 [[TMP36]], [[TMP34]] +// CHECK-NEXT: [[TMP38:%.*]] = icmp ule i32 [[TMP36]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = getelementptr double, ptr [[TMP35]], i32 [[TMP41]] +// CHECK-NEXT: [[TMP43:%.*]] = load double, ptr [[TMP42]], align 8 +// CHECK-NEXT: store double [[TMP43]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store double 0.000000e+00, ptr [[SUM8_ASCAST]], align 8 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP45]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP44]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP46:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store double [[TMP46]], ptr [[ARRAYIDX]], align 8 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP47]] to i64 +// CHECK-NEXT: [[TMP49:%.*]] = icmp eq i64 [[TMP48]], 0 +// CHECK-NEXT: br i1 [[TMP49]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// CHECK: omp.exclusive.dec: +// CHECK-NEXT: [[TMP50:%.*]] = sub nuw i64 [[TMP48]], 1 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw double, ptr [[TMP6]], i64 [[TMP50]] +// CHECK-NEXT: [[TMP51:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store double [[TMP51]], ptr [[TMP4]], align 8 +// CHECK-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// CHECK: omp.exclusive.copy.exit: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP53]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, ptr [[TMP52]], i64 [[IDXPROM10]] +// CHECK-NEXT: [[TMP54:%.*]] = load double, ptr [[ARRAYIDX11]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: [[TMP56:%.*]] = fadd double [[TMP55]], [[TMP54]] +// CHECK-NEXT: store double [[TMP56]], ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = getelementptr double, ptr [[TMP35]], i32 [[TMP57]] +// CHECK-NEXT: [[TMP59:%.*]] = load double, ptr addrspace(5) [[TMP7]], align 8 +// CHECK-NEXT: store double [[TMP59]], ptr [[TMP58]], align 8 +// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP61:%.*]] = add i32 1, [[TMP60]] +// CHECK-NEXT: store i32 [[TMP61]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIfEvv_l35 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP29]] +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], [[TMP30]] +// CHECK-NEXT: [[TMP34:%.*]] = icmp ule i32 [[TMP32]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP34]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP35]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store float 0.000000e+00, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP37:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP38]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP37]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP39:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP40:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = fadd float [[TMP40]], [[TMP39]] +// CHECK-NEXT: store float [[TMP41]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP43:%.*]] = zext i32 [[TMP42]] to i64 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load float, ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP45:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP46]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP45]], i64 [[IDXPROM9]] +// CHECK-NEXT: store float [[TMP44]], ptr [[ARRAYIDX10]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr float, ptr [[TMP31]], i32 [[TMP47]] +// CHECK-NEXT: [[TMP49:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store float [[TMP49]], ptr [[TMP48]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = add i32 1, [[TMP50]] +// CHECK-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_f_8x64(float [[TMP55]], ptr [[TMP54]], ptr [[TMP4]], ptr [[TMP52]], ptr [[TMP53]], ptr @__kmpc_rfun_sum_f, ptr @__kmpc_rfun_sum_lds_f, float 0.000000e+00, i64 [[TMP16]], i32 [[TMP15]]) +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIfEvv_l35_1 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_phase2_f_8x64(ptr [[TMP29]], i32 [[PADDED_SEGMENT_SIZE]], ptr [[TMP28]], ptr [[TMP30]], ptr @__kmpc_rfun_sum_f, float 0.000000e+00, i64 [[TMP16]], i32 1) +// CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP32]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = icmp ult i32 [[TMP36]], [[TMP34]] +// CHECK-NEXT: [[TMP38:%.*]] = icmp ule i32 [[TMP36]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = getelementptr float, ptr [[TMP35]], i32 [[TMP41]] +// CHECK-NEXT: [[TMP43:%.*]] = load float, ptr [[TMP42]], align 4 +// CHECK-NEXT: store float [[TMP43]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store float 0.000000e+00, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP45]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP44]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP46:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP47:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = fadd float [[TMP47]], [[TMP46]] +// CHECK-NEXT: store float [[TMP48]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw float, ptr [[TMP6]], i64 [[TMP50]] +// CHECK-NEXT: [[TMP51:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store float [[TMP51]], ptr [[TMP4]], align 4 +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP53]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[TMP52]], i64 [[IDXPROM10]] +// CHECK-NEXT: [[TMP54:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store float [[TMP54]], ptr [[ARRAYIDX11]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP56:%.*]] = getelementptr float, ptr [[TMP35]], i32 [[TMP55]] +// CHECK-NEXT: [[TMP57:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store float [[TMP57]], ptr [[TMP56]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP59:%.*]] = add i32 1, [[TMP58]] +// CHECK-NEXT: store i32 [[TMP59]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIfEvv_l47 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP29]] +// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], [[TMP30]] +// CHECK-NEXT: [[TMP34:%.*]] = icmp ule i32 [[TMP32]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP34]], [[TMP33]] +// CHECK-NEXT: br i1 [[TMP35]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP36]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store float 0.000000e+00, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP37:%.*]] = load float, ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP39]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP38]], i64 [[IDXPROM]] +// CHECK-NEXT: store float [[TMP37]], ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = zext i32 [[TMP40]] to i64 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP42:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP43]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP42]], i64 [[IDXPROM9]] +// CHECK-NEXT: [[TMP44:%.*]] = load float, ptr [[ARRAYIDX10]], align 4 +// CHECK-NEXT: [[TMP45:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP46:%.*]] = fadd float [[TMP45]], [[TMP44]] +// CHECK-NEXT: store float [[TMP46]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr float, ptr [[TMP31]], i32 [[TMP47]] +// CHECK-NEXT: [[TMP49:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store float [[TMP49]], ptr [[TMP48]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = add i32 1, [[TMP50]] +// CHECK-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_f_8x64(float [[TMP55]], ptr [[TMP54]], ptr [[TMP4]], ptr [[TMP52]], ptr [[TMP53]], ptr @__kmpc_rfun_sum_f, ptr @__kmpc_rfun_sum_lds_f, float 0.000000e+00, i64 [[TMP16]], i32 [[TMP15]]) +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIfEvv_l47_1 +// CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// CHECK-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[SUM8:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// CHECK-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// CHECK-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// CHECK-NEXT: [[DOTADDR5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR5]] to ptr +// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// CHECK-NEXT: [[SUM8_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM8]] to ptr +// CHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// CHECK-NEXT: call void @__kmpc_specialized_kernel_init() +// CHECK-NEXT: [[TMP7:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 999999, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], [[TMP9]] +// CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], 1 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP12]], [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 +// CHECK-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[GLOBAL_UPPER_BOUND:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = sub i32 [[GLOBAL_UPPER_BOUND]], [[TMP17]] +// CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], 1 +// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// CHECK-NEXT: [[NVPTX_NUM_THREADS6:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// CHECK-NEXT: [[GPU_BLOCK_ID7:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[GPU_BLOCK_ID7]], [[NVPTX_NUM_THREADS6]] +// CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[NVPTX_NUM_THREADS6]], [[TMP23]] +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]] +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// CHECK: omp.kernel.body: +// CHECK-NEXT: [[TMP27:%.*]] = udiv i32 [[TMP19]], [[TMP24]] +// CHECK-NEXT: [[PADDED_SEGMENT_SIZE:%.*]] = add i32 [[TMP27]], 1 +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: call void @__kmpc_xteams_phase2_f_8x64(ptr [[TMP29]], i32 [[PADDED_SEGMENT_SIZE]], ptr [[TMP28]], ptr [[TMP30]], ptr @__kmpc_rfun_sum_f, float 0.000000e+00, i64 [[TMP16]], i32 0) +// CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP22]] +// CHECK-NEXT: store i32 [[TMP32]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP22]], 1 +// CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[PADDED_SEGMENT_SIZE]], [[TMP33]] +// CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTADDR5_ASCAST]], align 8 +// CHECK-NEXT: br label [[FOR_COND:%.*]] +// CHECK: for.cond: +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP37:%.*]] = icmp ult i32 [[TMP36]], [[TMP34]] +// CHECK-NEXT: [[TMP38:%.*]] = icmp ule i32 [[TMP36]], [[GLOBAL_UPPER_BOUND]] +// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP38]], [[TMP37]] +// CHECK-NEXT: br i1 [[TMP39]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK: for.body: +// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP40]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP42:%.*]] = getelementptr float, ptr [[TMP35]], i32 [[TMP41]] +// CHECK-NEXT: [[TMP43:%.*]] = load float, ptr [[TMP42]], align 4 +// CHECK-NEXT: store float [[TMP43]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store float 0.000000e+00, ptr [[SUM8_ASCAST]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP45]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP44]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP46:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store float [[TMP46]], ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP47]] to i64 +// CHECK-NEXT: [[TMP49:%.*]] = icmp eq i64 [[TMP48]], 0 +// CHECK-NEXT: br i1 [[TMP49]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// CHECK: omp.exclusive.dec: +// CHECK-NEXT: [[TMP50:%.*]] = sub nuw i64 [[TMP48]], 1 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw float, ptr [[TMP6]], i64 [[TMP50]] +// CHECK-NEXT: [[TMP51:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store float [[TMP51]], ptr [[TMP4]], align 4 +// CHECK-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// CHECK: omp.exclusive.copy.exit: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP52:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP53]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[TMP52]], i64 [[IDXPROM10]] +// CHECK-NEXT: [[TMP54:%.*]] = load float, ptr [[ARRAYIDX11]], align 4 +// CHECK-NEXT: [[TMP55:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: [[TMP56:%.*]] = fadd float [[TMP55]], [[TMP54]] +// CHECK-NEXT: store float [[TMP56]], ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[FOR_INC:%.*]] +// CHECK: for.inc: +// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP58:%.*]] = getelementptr float, ptr [[TMP35]], i32 [[TMP57]] +// CHECK-NEXT: [[TMP59:%.*]] = load float, ptr addrspace(5) [[TMP7]], align 4 +// CHECK-NEXT: store float [[TMP59]], ptr [[TMP58]], align 4 +// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: [[TMP61:%.*]] = add i32 1, [[TMP60]] +// CHECK-NEXT: store i32 [[TMP61]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] +// CHECK: for.end: +// CHECK-NEXT: br label [[OMP_KERNEL_DONE]] +// CHECK: omp.kernel.done: +// CHECK-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIiEvv_l33 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0:[0-9]+]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29:![0-9]+]], !align [[META30:![0-9]+]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: store i32 0, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// NO-LOOP-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// NO-LOOP: omp.kernel.body: +// NO-LOOP-NEXT: store i32 0, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// NO-LOOP-NEXT: store i32 [[TMP22]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP24:%.*]] = zext i32 [[TMP23]] to i64 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: [[TMP26:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP27]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, ptr [[TMP26]], i64 [[IDXPROM6]] +// NO-LOOP-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX7]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_i_4x64(i32 [[TMP31]], ptr [[TMP30]], ptr [[TMP3]], ptr [[TMP28]], ptr [[TMP29]], ptr @__kmpc_rfun_sum_i, ptr @__kmpc_rfun_sum_lds_i, i32 0, i64 [[TMP14]], i32 [[TMP13]]) +// NO-LOOP-NEXT: br label [[OMP_KERNEL_DONE]] +// NO-LOOP: omp.kernel.done: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIiEvv_l33_1 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: store i32 0, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_phase2_i_4x64(ptr [[TMP19]], i32 1, ptr [[TMP18]], ptr [[TMP19]], ptr @__kmpc_rfun_sum_i, i32 0, i64 [[TMP14]], i32 1) +// NO-LOOP-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], [[TOTAL_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP17]], i32 [[TMP21]] +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP23]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP24:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP24]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP28:%.*]] = add i32 [[TMP27]], [[TMP26]] +// NO-LOOP-NEXT: store i32 [[TMP28]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP30:%.*]] = zext i32 [[TMP29]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i64 [[TMP30]] +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP31]], ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP32:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP33]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[TMP32]], i64 [[IDXPROM7]] +// NO-LOOP-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP34]], ptr [[ARRAYIDX8]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIiEvv_l45 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: store i32 0, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// NO-LOOP-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// NO-LOOP: omp.kernel.body: +// NO-LOOP-NEXT: store i32 0, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP19]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP23:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP24:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP24]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, ptr [[TMP23]], i64 [[IDXPROM6]] +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX7]], align 4 +// NO-LOOP-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP27:%.*]] = add i32 [[TMP26]], [[TMP25]] +// NO-LOOP-NEXT: store i32 [[TMP27]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_i_4x64(i32 [[TMP31]], ptr [[TMP30]], ptr [[TMP3]], ptr [[TMP28]], ptr [[TMP29]], ptr @__kmpc_rfun_sum_i, ptr @__kmpc_rfun_sum_lds_i, i32 0, i64 [[TMP14]], i32 [[TMP13]]) +// NO-LOOP-NEXT: br label [[OMP_KERNEL_DONE]] +// NO-LOOP: omp.kernel.done: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIiEvv_l45_1 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: store i32 0, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_phase2_i_4x64(ptr [[TMP19]], i32 1, ptr [[TMP18]], ptr [[TMP19]], ptr @__kmpc_rfun_sum_i, i32 0, i64 [[TMP14]], i32 0) +// NO-LOOP-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], [[TOTAL_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP17]], i32 [[TMP21]] +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP23]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP24:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP24]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP26]], ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP28:%.*]] = zext i32 [[TMP27]] to i64 +// NO-LOOP-NEXT: [[TMP29:%.*]] = icmp eq i64 [[TMP28]], 0 +// NO-LOOP-NEXT: br i1 [[TMP29]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// NO-LOOP: omp.exclusive.dec: +// NO-LOOP-NEXT: [[TMP30:%.*]] = sub nuw i64 [[TMP28]], 1 +// NO-LOOP-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i64 [[TMP30]] +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP31]], ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// NO-LOOP: omp.exclusive.copy.exit: +// NO-LOOP-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP32:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP33]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[TMP32]], i64 [[IDXPROM7]] +// NO-LOOP-NEXT: [[TMP34:%.*]] = load i32, ptr [[ARRAYIDX8]], align 4 +// NO-LOOP-NEXT: [[TMP35:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP36:%.*]] = add i32 [[TMP35]], [[TMP34]] +// NO-LOOP-NEXT: store i32 [[TMP36]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIjEvv_l33 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: store i32 0, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// NO-LOOP-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// NO-LOOP: omp.kernel.body: +// NO-LOOP-NEXT: store i32 0, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], [[TMP20]] +// NO-LOOP-NEXT: store i32 [[TMP22]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP24:%.*]] = zext i32 [[TMP23]] to i64 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: [[TMP26:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP27]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, ptr [[TMP26]], i64 [[IDXPROM6]] +// NO-LOOP-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX7]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_i_4x64(i32 [[TMP31]], ptr [[TMP30]], ptr [[TMP3]], ptr [[TMP28]], ptr [[TMP29]], ptr @__kmpc_rfun_sum_i, ptr @__kmpc_rfun_sum_lds_i, i32 0, i64 [[TMP14]], i32 [[TMP13]]) +// NO-LOOP-NEXT: br label [[OMP_KERNEL_DONE]] +// NO-LOOP: omp.kernel.done: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIjEvv_l33_1 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: store i32 0, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_phase2_i_4x64(ptr [[TMP19]], i32 1, ptr [[TMP18]], ptr [[TMP19]], ptr @__kmpc_rfun_sum_i, i32 0, i64 [[TMP14]], i32 1) +// NO-LOOP-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], [[TOTAL_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP17]], i32 [[TMP21]] +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP23]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP24:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP24]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP28:%.*]] = add i32 [[TMP27]], [[TMP26]] +// NO-LOOP-NEXT: store i32 [[TMP28]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP30:%.*]] = zext i32 [[TMP29]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i64 [[TMP30]] +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP31]], ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP32:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP33]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[TMP32]], i64 [[IDXPROM7]] +// NO-LOOP-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP34]], ptr [[ARRAYIDX8]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIjEvv_l45 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: store i32 0, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// NO-LOOP-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// NO-LOOP: omp.kernel.body: +// NO-LOOP-NEXT: store i32 0, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP19]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP23:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP24:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP24]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, ptr [[TMP23]], i64 [[IDXPROM6]] +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX7]], align 4 +// NO-LOOP-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP27:%.*]] = add i32 [[TMP26]], [[TMP25]] +// NO-LOOP-NEXT: store i32 [[TMP27]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_i_4x64(i32 [[TMP31]], ptr [[TMP30]], ptr [[TMP3]], ptr [[TMP28]], ptr [[TMP29]], ptr @__kmpc_rfun_sum_i, ptr @__kmpc_rfun_sum_lds_i, i32 0, i64 [[TMP14]], i32 [[TMP13]]) +// NO-LOOP-NEXT: br label [[OMP_KERNEL_DONE]] +// NO-LOOP: omp.kernel.done: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIjEvv_l45_1 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: store i32 0, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_phase2_i_4x64(ptr [[TMP19]], i32 1, ptr [[TMP18]], ptr [[TMP19]], ptr @__kmpc_rfun_sum_i, i32 0, i64 [[TMP14]], i32 0) +// NO-LOOP-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], [[TOTAL_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP17]], i32 [[TMP21]] +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP23]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP24:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP24]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP26]], ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP28:%.*]] = zext i32 [[TMP27]] to i64 +// NO-LOOP-NEXT: [[TMP29:%.*]] = icmp eq i64 [[TMP28]], 0 +// NO-LOOP-NEXT: br i1 [[TMP29]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// NO-LOOP: omp.exclusive.dec: +// NO-LOOP-NEXT: [[TMP30:%.*]] = sub nuw i64 [[TMP28]], 1 +// NO-LOOP-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i64 [[TMP30]] +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP31]], ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// NO-LOOP: omp.exclusive.copy.exit: +// NO-LOOP-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP32:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP33]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[TMP32]], i64 [[IDXPROM7]] +// NO-LOOP-NEXT: [[TMP34:%.*]] = load i32, ptr [[ARRAYIDX8]], align 4 +// NO-LOOP-NEXT: [[TMP35:%.*]] = load i32, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP36:%.*]] = add i32 [[TMP35]], [[TMP34]] +// NO-LOOP-NEXT: store i32 [[TMP36]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIlEvv_l33 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META31:![0-9]+]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: store i64 0, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// NO-LOOP-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// NO-LOOP: omp.kernel.body: +// NO-LOOP-NEXT: store i64 0, ptr [[SUM5_ASCAST]], align 8 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP18]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 +// NO-LOOP-NEXT: [[TMP21:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: [[TMP22:%.*]] = add i64 [[TMP21]], [[TMP20]] +// NO-LOOP-NEXT: store i64 [[TMP22]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP24:%.*]] = zext i32 [[TMP23]] to i64 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i64, ptr [[TMP3]], align 8 +// NO-LOOP-NEXT: [[TMP26:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP27]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i64, ptr [[TMP26]], i64 [[IDXPROM6]] +// NO-LOOP-NEXT: store i64 [[TMP25]], ptr [[ARRAYIDX7]], align 8 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: call void @__kmpc_xteams_l_4x64(i64 [[TMP31]], ptr [[TMP30]], ptr [[TMP3]], ptr [[TMP28]], ptr [[TMP29]], ptr @__kmpc_rfun_sum_l, ptr @__kmpc_rfun_sum_lds_l, i64 0, i64 [[TMP14]], i32 [[TMP13]]) +// NO-LOOP-NEXT: br label [[OMP_KERNEL_DONE]] +// NO-LOOP: omp.kernel.done: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIlEvv_l33_1 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: store i64 0, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: call void @__kmpc_xteams_phase2_l_4x64(ptr [[TMP19]], i32 1, ptr [[TMP18]], ptr [[TMP19]], ptr @__kmpc_rfun_sum_l, i64 0, i64 [[TMP14]], i32 1) +// NO-LOOP-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], [[TOTAL_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP22:%.*]] = getelementptr i64, ptr [[TMP17]], i32 [[TMP21]] +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i64, ptr [[TMP22]], align 8 +// NO-LOOP-NEXT: store i64 [[TMP23]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i64 0, ptr [[SUM5_ASCAST]], align 8 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP24:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP24]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP26:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], [[TMP26]] +// NO-LOOP-NEXT: store i64 [[TMP28]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP30:%.*]] = zext i32 [[TMP29]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw i64, ptr [[TMP5]], i64 [[TMP30]] +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i64 [[TMP31]], ptr [[TMP3]], align 8 +// NO-LOOP-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP32:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP33]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i64, ptr [[TMP32]], i64 [[IDXPROM7]] +// NO-LOOP-NEXT: [[TMP34:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i64 [[TMP34]], ptr [[ARRAYIDX8]], align 8 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIlEvv_l45 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: store i64 0, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// NO-LOOP-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// NO-LOOP: omp.kernel.body: +// NO-LOOP-NEXT: store i64 0, ptr [[SUM5_ASCAST]], align 8 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP3]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP19]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: store i64 [[TMP18]], ptr [[ARRAYIDX]], align 8 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP23:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP24:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP24]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i64, ptr [[TMP23]], i64 [[IDXPROM6]] +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i64, ptr [[ARRAYIDX7]], align 8 +// NO-LOOP-NEXT: [[TMP26:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: [[TMP27:%.*]] = add i64 [[TMP26]], [[TMP25]] +// NO-LOOP-NEXT: store i64 [[TMP27]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: call void @__kmpc_xteams_l_4x64(i64 [[TMP31]], ptr [[TMP30]], ptr [[TMP3]], ptr [[TMP28]], ptr [[TMP29]], ptr @__kmpc_rfun_sum_l, ptr @__kmpc_rfun_sum_lds_l, i64 0, i64 [[TMP14]], i32 [[TMP13]]) +// NO-LOOP-NEXT: br label [[OMP_KERNEL_DONE]] +// NO-LOOP: omp.kernel.done: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIlEvv_l45_1 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: store i64 0, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: call void @__kmpc_xteams_phase2_l_4x64(ptr [[TMP19]], i32 1, ptr [[TMP18]], ptr [[TMP19]], ptr @__kmpc_rfun_sum_l, i64 0, i64 [[TMP14]], i32 0) +// NO-LOOP-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], [[TOTAL_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP22:%.*]] = getelementptr i64, ptr [[TMP17]], i32 [[TMP21]] +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i64, ptr [[TMP22]], align 8 +// NO-LOOP-NEXT: store i64 [[TMP23]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i64 0, ptr [[SUM5_ASCAST]], align 8 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP24:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[TMP24]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP26:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i64 [[TMP26]], ptr [[ARRAYIDX]], align 8 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP28:%.*]] = zext i32 [[TMP27]] to i64 +// NO-LOOP-NEXT: [[TMP29:%.*]] = icmp eq i64 [[TMP28]], 0 +// NO-LOOP-NEXT: br i1 [[TMP29]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// NO-LOOP: omp.exclusive.dec: +// NO-LOOP-NEXT: [[TMP30:%.*]] = sub nuw i64 [[TMP28]], 1 +// NO-LOOP-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw i64, ptr [[TMP5]], i64 [[TMP30]] +// NO-LOOP-NEXT: [[TMP31:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i64 [[TMP31]], ptr [[TMP3]], align 8 +// NO-LOOP-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// NO-LOOP: omp.exclusive.copy.exit: +// NO-LOOP-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP32:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP33]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i64, ptr [[TMP32]], i64 [[IDXPROM7]] +// NO-LOOP-NEXT: [[TMP34:%.*]] = load i64, ptr [[ARRAYIDX8]], align 8 +// NO-LOOP-NEXT: [[TMP35:%.*]] = load i64, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: [[TMP36:%.*]] = add i64 [[TMP35]], [[TMP34]] +// NO-LOOP-NEXT: store i64 [[TMP36]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIdEvv_l33 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca double, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca double, align 8, addrspace(5) +// NO-LOOP-NEXT: store double 0.000000e+00, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// NO-LOOP-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// NO-LOOP: omp.kernel.body: +// NO-LOOP-NEXT: store double 0.000000e+00, ptr [[SUM5_ASCAST]], align 8 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP18]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP20:%.*]] = load double, ptr [[ARRAYIDX]], align 8 +// NO-LOOP-NEXT: [[TMP21:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: [[TMP22:%.*]] = fadd double [[TMP21]], [[TMP20]] +// NO-LOOP-NEXT: store double [[TMP22]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP24:%.*]] = zext i32 [[TMP23]] to i64 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP25:%.*]] = load double, ptr [[TMP3]], align 8 +// NO-LOOP-NEXT: [[TMP26:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP27]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[TMP26]], i64 [[IDXPROM6]] +// NO-LOOP-NEXT: store double [[TMP25]], ptr [[ARRAYIDX7]], align 8 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP31:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: call void @__kmpc_xteams_d_4x64(double [[TMP31]], ptr [[TMP30]], ptr [[TMP3]], ptr [[TMP28]], ptr [[TMP29]], ptr @__kmpc_rfun_sum_d, ptr @__kmpc_rfun_sum_lds_d, double 0.000000e+00, i64 [[TMP14]], i32 [[TMP13]]) +// NO-LOOP-NEXT: br label [[OMP_KERNEL_DONE]] +// NO-LOOP: omp.kernel.done: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIdEvv_l33_1 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca double, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca double, align 8, addrspace(5) +// NO-LOOP-NEXT: store double 0.000000e+00, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: call void @__kmpc_xteams_phase2_d_4x64(ptr [[TMP19]], i32 1, ptr [[TMP18]], ptr [[TMP19]], ptr @__kmpc_rfun_sum_d, double 0.000000e+00, i64 [[TMP14]], i32 1) +// NO-LOOP-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], [[TOTAL_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP22:%.*]] = getelementptr double, ptr [[TMP17]], i32 [[TMP21]] +// NO-LOOP-NEXT: [[TMP23:%.*]] = load double, ptr [[TMP22]], align 8 +// NO-LOOP-NEXT: store double [[TMP23]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store double 0.000000e+00, ptr [[SUM5_ASCAST]], align 8 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP24:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP24]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP26:%.*]] = load double, ptr [[ARRAYIDX]], align 8 +// NO-LOOP-NEXT: [[TMP27:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: [[TMP28:%.*]] = fadd double [[TMP27]], [[TMP26]] +// NO-LOOP-NEXT: store double [[TMP28]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP30:%.*]] = zext i32 [[TMP29]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw double, ptr [[TMP5]], i64 [[TMP30]] +// NO-LOOP-NEXT: [[TMP31:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store double [[TMP31]], ptr [[TMP3]], align 8 +// NO-LOOP-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP32:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP33]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, ptr [[TMP32]], i64 [[IDXPROM7]] +// NO-LOOP-NEXT: [[TMP34:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store double [[TMP34]], ptr [[ARRAYIDX8]], align 8 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIdEvv_l45 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca double, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca double, align 8, addrspace(5) +// NO-LOOP-NEXT: store double 0.000000e+00, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// NO-LOOP-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// NO-LOOP: omp.kernel.body: +// NO-LOOP-NEXT: store double 0.000000e+00, ptr [[SUM5_ASCAST]], align 8 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP18:%.*]] = load double, ptr [[TMP3]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP19]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: store double [[TMP18]], ptr [[ARRAYIDX]], align 8 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP23:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP24:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP24]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[TMP23]], i64 [[IDXPROM6]] +// NO-LOOP-NEXT: [[TMP25:%.*]] = load double, ptr [[ARRAYIDX7]], align 8 +// NO-LOOP-NEXT: [[TMP26:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: [[TMP27:%.*]] = fadd double [[TMP26]], [[TMP25]] +// NO-LOOP-NEXT: store double [[TMP27]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP31:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: call void @__kmpc_xteams_d_4x64(double [[TMP31]], ptr [[TMP30]], ptr [[TMP3]], ptr [[TMP28]], ptr [[TMP29]], ptr @__kmpc_rfun_sum_d, ptr @__kmpc_rfun_sum_lds_d, double 0.000000e+00, i64 [[TMP14]], i32 [[TMP13]]) +// NO-LOOP-NEXT: br label [[OMP_KERNEL_DONE]] +// NO-LOOP: omp.kernel.done: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIdEvv_l45_1 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca double, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META31]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca double, align 8, addrspace(5) +// NO-LOOP-NEXT: store double 0.000000e+00, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: call void @__kmpc_xteams_phase2_d_4x64(ptr [[TMP19]], i32 1, ptr [[TMP18]], ptr [[TMP19]], ptr @__kmpc_rfun_sum_d, double 0.000000e+00, i64 [[TMP14]], i32 0) +// NO-LOOP-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], [[TOTAL_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP22:%.*]] = getelementptr double, ptr [[TMP17]], i32 [[TMP21]] +// NO-LOOP-NEXT: [[TMP23:%.*]] = load double, ptr [[TMP22]], align 8 +// NO-LOOP-NEXT: store double [[TMP23]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store double 0.000000e+00, ptr [[SUM5_ASCAST]], align 8 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP24:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP24]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP26:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store double [[TMP26]], ptr [[ARRAYIDX]], align 8 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP28:%.*]] = zext i32 [[TMP27]] to i64 +// NO-LOOP-NEXT: [[TMP29:%.*]] = icmp eq i64 [[TMP28]], 0 +// NO-LOOP-NEXT: br i1 [[TMP29]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// NO-LOOP: omp.exclusive.dec: +// NO-LOOP-NEXT: [[TMP30:%.*]] = sub nuw i64 [[TMP28]], 1 +// NO-LOOP-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw double, ptr [[TMP5]], i64 [[TMP30]] +// NO-LOOP-NEXT: [[TMP31:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: store double [[TMP31]], ptr [[TMP3]], align 8 +// NO-LOOP-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// NO-LOOP: omp.exclusive.copy.exit: +// NO-LOOP-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP32:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP33]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, ptr [[TMP32]], i64 [[IDXPROM7]] +// NO-LOOP-NEXT: [[TMP34:%.*]] = load double, ptr [[ARRAYIDX8]], align 8 +// NO-LOOP-NEXT: [[TMP35:%.*]] = load double, ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: [[TMP36:%.*]] = fadd double [[TMP35]], [[TMP34]] +// NO-LOOP-NEXT: store double [[TMP36]], ptr addrspace(5) [[TMP6]], align 8 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIfEvv_l33 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca float, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca float, align 4, addrspace(5) +// NO-LOOP-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// NO-LOOP-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// NO-LOOP: omp.kernel.body: +// NO-LOOP-NEXT: store float 0.000000e+00, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: [[TMP21:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP22:%.*]] = fadd float [[TMP21]], [[TMP20]] +// NO-LOOP-NEXT: store float [[TMP22]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP24:%.*]] = zext i32 [[TMP23]] to i64 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP25:%.*]] = load float, ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: [[TMP26:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP27]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM6]] +// NO-LOOP-NEXT: store float [[TMP25]], ptr [[ARRAYIDX7]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP31:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_f_4x64(float [[TMP31]], ptr [[TMP30]], ptr [[TMP3]], ptr [[TMP28]], ptr [[TMP29]], ptr @__kmpc_rfun_sum_f, ptr @__kmpc_rfun_sum_lds_f, float 0.000000e+00, i64 [[TMP14]], i32 [[TMP13]]) +// NO-LOOP-NEXT: br label [[OMP_KERNEL_DONE]] +// NO-LOOP: omp.kernel.done: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIfEvv_l33_1 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca float, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca float, align 4, addrspace(5) +// NO-LOOP-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_phase2_f_4x64(ptr [[TMP19]], i32 1, ptr [[TMP18]], ptr [[TMP19]], ptr @__kmpc_rfun_sum_f, float 0.000000e+00, i64 [[TMP14]], i32 1) +// NO-LOOP-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], [[TOTAL_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP22:%.*]] = getelementptr float, ptr [[TMP17]], i32 [[TMP21]] +// NO-LOOP-NEXT: [[TMP23:%.*]] = load float, ptr [[TMP22]], align 4 +// NO-LOOP-NEXT: store float [[TMP23]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store float 0.000000e+00, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP24:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP26:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: [[TMP27:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP28:%.*]] = fadd float [[TMP27]], [[TMP26]] +// NO-LOOP-NEXT: store float [[TMP28]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP30:%.*]] = zext i32 [[TMP29]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP5]], i64 [[TMP30]] +// NO-LOOP-NEXT: [[TMP31:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store float [[TMP31]], ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP32:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP33]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM7]] +// NO-LOOP-NEXT: [[TMP34:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store float [[TMP34]], ptr [[ARRAYIDX8]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIfEvv_l45 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca float, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca float, align 4, addrspace(5) +// NO-LOOP-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] +// NO-LOOP-NEXT: br i1 [[CMP]], label [[OMP_KERNEL_BODY:%.*]], label [[OMP_KERNEL_DONE:%.*]] +// NO-LOOP: omp.kernel.body: +// NO-LOOP-NEXT: store float 0.000000e+00, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: store float [[TMP18]], ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP23:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP24:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP24]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM6]] +// NO-LOOP-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX7]], align 4 +// NO-LOOP-NEXT: [[TMP26:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP27:%.*]] = fadd float [[TMP26]], [[TMP25]] +// NO-LOOP-NEXT: store float [[TMP27]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP31:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_f_4x64(float [[TMP31]], ptr [[TMP30]], ptr [[TMP3]], ptr [[TMP28]], ptr [[TMP29]], ptr @__kmpc_rfun_sum_f, ptr @__kmpc_rfun_sum_lds_f, float 0.000000e+00, i64 [[TMP14]], i32 [[TMP13]]) +// NO-LOOP-NEXT: br label [[OMP_KERNEL_DONE]] +// NO-LOOP: omp.kernel.done: +// NO-LOOP-NEXT: ret void +// +// +// NO-LOOP-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8run_testIfEvv_l45_1 +// NO-LOOP-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM:%.*]], ptr noundef [[A:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR0]] { +// NO-LOOP-NEXT: entry: +// NO-LOOP-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// NO-LOOP-NEXT: [[SUM_ADDR2:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8, addrspace(5) +// NO-LOOP-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// NO-LOOP-NEXT: [[SUM5:%.*]] = alloca float, align 4, addrspace(5) +// NO-LOOP-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// NO-LOOP-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr +// NO-LOOP-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// NO-LOOP-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// NO-LOOP-NEXT: [[SUM_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR2]] to ptr +// NO-LOOP-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr +// NO-LOOP-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr +// NO-LOOP-NEXT: [[DOTADDR4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR4]] to ptr +// NO-LOOP-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// NO-LOOP-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// NO-LOOP-NEXT: [[SUM5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM5]] to ptr +// NO-LOOP-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[SUM1]], ptr [[SUM_ADDR2_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3_ASCAST]], align 8 +// NO-LOOP-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM_ADDR2_ASCAST]], align 8, !nonnull [[META29]], !align [[META30]] +// NO-LOOP-NEXT: call void @__kmpc_specialized_kernel_init() +// NO-LOOP-NEXT: [[TMP6:%.*]] = alloca float, align 4, addrspace(5) +// NO-LOOP-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 25599, ptr [[DOTOMP_UB_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// NO-LOOP-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() +// NO-LOOP-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// NO-LOOP-NEXT: [[GPU_BLOCK_ID:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() +// NO-LOOP-NEXT: [[TMP9:%.*]] = mul i32 [[GPU_BLOCK_ID]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], [[TMP8]] +// NO-LOOP-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]] +// NO-LOOP-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_get_hardware_num_blocks() +// NO-LOOP-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64 +// NO-LOOP-NEXT: [[TOTAL_NUM_THREADS:%.*]] = mul i32 [[TMP13]], [[NVPTX_NUM_THREADS]] +// NO-LOOP-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// NO-LOOP-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// NO-LOOP-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTADDR4_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP20:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: call void @__kmpc_xteams_phase2_f_4x64(ptr [[TMP19]], i32 1, ptr [[TMP18]], ptr [[TMP19]], ptr @__kmpc_rfun_sum_f, float 0.000000e+00, i64 [[TMP14]], i32 0) +// NO-LOOP-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], [[TOTAL_NUM_THREADS]] +// NO-LOOP-NEXT: [[TMP22:%.*]] = getelementptr float, ptr [[TMP17]], i32 [[TMP21]] +// NO-LOOP-NEXT: [[TMP23:%.*]] = load float, ptr [[TMP22]], align 4 +// NO-LOOP-NEXT: store float [[TMP23]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store float 0.000000e+00, ptr [[SUM5_ASCAST]], align 4 +// NO-LOOP-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// NO-LOOP: omp.before.scan.bb: +// NO-LOOP-NEXT: [[TMP24:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP25:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM]] +// NO-LOOP-NEXT: [[TMP26:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store float [[TMP26]], ptr [[ARRAYIDX]], align 4 +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// NO-LOOP: omp.exit.inscan.bb: +// NO-LOOP-NEXT: br label [[OMP_BODY_CONTINUE]] +// NO-LOOP: omp.inscan.dispatch: +// NO-LOOP-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// NO-LOOP-NEXT: [[TMP28:%.*]] = zext i32 [[TMP27]] to i64 +// NO-LOOP-NEXT: [[TMP29:%.*]] = icmp eq i64 [[TMP28]], 0 +// NO-LOOP-NEXT: br i1 [[TMP29]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// NO-LOOP: omp.exclusive.dec: +// NO-LOOP-NEXT: [[TMP30:%.*]] = sub nuw i64 [[TMP28]], 1 +// NO-LOOP-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP5]], i64 [[TMP30]] +// NO-LOOP-NEXT: [[TMP31:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: store float [[TMP31]], ptr [[TMP3]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// NO-LOOP: omp.exclusive.copy.exit: +// NO-LOOP-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// NO-LOOP: omp.after.scan.bb: +// NO-LOOP-NEXT: [[TMP32:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// NO-LOOP-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_ASCAST]], align 4 +// NO-LOOP-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP33]] to i64 +// NO-LOOP-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM7]] +// NO-LOOP-NEXT: [[TMP34:%.*]] = load float, ptr [[ARRAYIDX8]], align 4 +// NO-LOOP-NEXT: [[TMP35:%.*]] = load float, ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: [[TMP36:%.*]] = fadd float [[TMP35]], [[TMP34]] +// NO-LOOP-NEXT: store float [[TMP36]], ptr addrspace(5) [[TMP6]], align 4 +// NO-LOOP-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// NO-LOOP: omp.body.continue: +// NO-LOOP-NEXT: ret void +// diff --git a/clang/test/OpenMP/xteam_scan_host_codegen.cpp b/clang/test/OpenMP/xteam_scan_host_codegen.cpp new file mode 100644 index 0000000000000..931cdd0432cfa --- /dev/null +++ b/clang/test/OpenMP/xteam_scan_host_codegen.cpp @@ -0,0 +1,2519 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-ignore-env-vars -fopenmp-assume-no-nested-parallelism -fopenmp-assume-no-thread-state -fopenmp-target-xteam-no-loop-scan -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-target-ignore-env-vars -fopenmp-assume-no-nested-parallelism -fopenmp-assume-no-thread-state -fopenmp-target-xteam-scan -emit-llvm %s -o - | FileCheck %s --check-prefix=SEGMENTED +// expected-no-diagnostics + +#define NUM_TEAMS 250 +#define NUM_THREADS 256 +#define N NUM_THREADS * NUM_TEAMS + +int main() { + int in[N], out1[N]; + int sum1 = 0; + +#pragma omp target teams distribute parallel for reduction(inscan, +:sum1) map(tofrom: in, out1) num_teams(NUM_TEAMS) num_threads(NUM_THREADS) + for(int i = 0; i < N; i++) { + sum1 += in[i]; // input phase + #pragma omp scan inclusive(sum1) + out1[i] = sum1; // scan phase + } + + int sum2 = 0; + int out2[N]; + +#pragma omp target teams distribute parallel for reduction(inscan, +:sum2) map(tofrom: in, out2) num_teams(NUM_TEAMS) num_threads(NUM_THREADS) + for(int i = 0; i < N; i++) { + out2[i] = sum2; // scan phase + #pragma omp scan exclusive(sum2) + sum2 += in[i]; // input phase + } + + return 0; +} +// CHECK-LABEL: define {{[^@]+}}@main +// CHECK-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[IN:%.*]] = alloca [64000 x i32], align 16 +// CHECK-NEXT: [[OUT1:%.*]] = alloca [64000 x i32], align 16 +// CHECK-NEXT: [[SUM1:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[_TMP13:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// CHECK-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[SUM2:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[OUT2:%.*]] = alloca [64000 x i32], align 16 +// CHECK-NEXT: [[_TMP18:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS28:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_PTRS29:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS30:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[_TMP31:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[KERNEL_ARGS32:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [8 x ptr], align 8 +// CHECK-NEXT: [[_TMP43:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[KERNEL_ARGS44:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// CHECK-NEXT: [[_TMP47:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM1]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = call ptr @llvm.stacksave.p0() +// CHECK-NEXT: store ptr [[TMP0]], ptr [[SAVED_STACK]], align 8 +// CHECK-NEXT: [[VLA:%.*]] = alloca i32, i64 0, align 16 +// CHECK-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK-NEXT: [[D_SCAN_STORAGE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_SCAN_STORAGE]], align 4 +// CHECK-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// CHECK-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// CHECK-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 1000, i32 [[DEFAULT_DEV]]) +// CHECK-NEXT: [[D_SCAN_STORAGE2:%.*]] = call ptr @omp_target_alloc(i64 512004, i32 [[DEFAULT_DEV]]) +// CHECK-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK-NEXT: [[D_TEAMS_DONE_PTR3:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR3]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[TMP2]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[TMP3]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK-NEXT: store ptr null, ptr [[TMP4]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[IN]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[IN]], ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK-NEXT: store ptr null, ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[OUT1]], ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[OUT1]], ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK-NEXT: store ptr null, ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK-NEXT: store i64 0, ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK-NEXT: store i64 0, ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK-NEXT: store ptr null, ptr [[TMP13]], align 8 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK-NEXT: store ptr [[VLA]], ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK-NEXT: store ptr [[VLA]], ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK-NEXT: store ptr null, ptr [[TMP16]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 +// CHECK-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP17]], align 8 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 +// CHECK-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP18]], align 8 +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 +// CHECK-NEXT: store ptr null, ptr [[TMP19]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 +// CHECK-NEXT: store ptr [[D_TEAMS_DONE_PTR3]], ptr [[TMP20]], align 8 +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 +// CHECK-NEXT: store ptr [[D_TEAMS_DONE_PTR3]], ptr [[TMP21]], align 8 +// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 +// CHECK-NEXT: store ptr null, ptr [[TMP22]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 +// CHECK-NEXT: store ptr [[D_SCAN_STORAGE2]], ptr [[TMP23]], align 8 +// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 +// CHECK-NEXT: store ptr [[D_SCAN_STORAGE2]], ptr [[TMP24]], align 8 +// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 +// CHECK-NEXT: store ptr null, ptr [[TMP25]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK-NEXT: store i32 3, ptr [[TMP28]], align 4 +// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK-NEXT: store i32 8, ptr [[TMP29]], align 4 +// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 8 +// CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK-NEXT: store ptr [[TMP27]], ptr [[TMP31]], align 8 +// CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK-NEXT: store ptr @.offload_sizes, ptr [[TMP32]], align 8 +// CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK-NEXT: store ptr @.offload_maptypes, ptr [[TMP33]], align 8 +// CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK-NEXT: store ptr null, ptr [[TMP34]], align 8 +// CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK-NEXT: store ptr null, ptr [[TMP35]], align 8 +// CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK-NEXT: store i64 64000, ptr [[TMP36]], align 8 +// CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK-NEXT: store i64 0, ptr [[TMP37]], align 8 +// CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK-NEXT: store [3 x i32] [i32 250, i32 0, i32 0], ptr [[TMP38]], align 4 +// CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK-NEXT: store [3 x i32] [i32 256, i32 0, i32 0], ptr [[TMP39]], align 4 +// CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK-NEXT: store i32 0, ptr [[TMP40]], align 4 +// CHECK-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 250, i32 256, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.region_id, ptr [[KERNEL_ARGS]]) +// CHECK-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK: omp_offload.failed: +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14(ptr [[SUM1]], ptr [[IN]], ptr [[OUT1]], i64 0, ptr [[VLA]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]], ptr [[D_SCAN_STORAGE]]) #[[ATTR3:[0-9]+]] +// CHECK-NEXT: br label [[OMP_OFFLOAD_CONT]] +// CHECK: omp_offload.cont: +// CHECK-NEXT: [[D_TEAM_VALS5:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAM_VALS5]], align 4 +// CHECK-NEXT: [[D_TEAMS_DONE_PTR6:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR6]], align 4 +// CHECK-NEXT: [[D_SCAN_STORAGE7:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_SCAN_STORAGE7]], align 4 +// CHECK-NEXT: [[DEFAULT_DEV8:%.*]] = call i32 @omp_get_default_device() +// CHECK-NEXT: [[INITIAL_DEVID9:%.*]] = call i32 @omp_get_initial_device() +// CHECK-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[TMP43]], align 8 +// CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[TMP44]], align 8 +// CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 +// CHECK-NEXT: store ptr null, ptr [[TMP45]], align 8 +// CHECK-NEXT: [[TMP46:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[IN]], ptr [[TMP46]], align 8 +// CHECK-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[IN]], ptr [[TMP47]], align 8 +// CHECK-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 +// CHECK-NEXT: store ptr null, ptr [[TMP48]], align 8 +// CHECK-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[OUT1]], ptr [[TMP49]], align 8 +// CHECK-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[OUT1]], ptr [[TMP50]], align 8 +// CHECK-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 2 +// CHECK-NEXT: store ptr null, ptr [[TMP51]], align 8 +// CHECK-NEXT: [[TMP52:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 3 +// CHECK-NEXT: store i64 0, ptr [[TMP52]], align 8 +// CHECK-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 3 +// CHECK-NEXT: store i64 0, ptr [[TMP53]], align 8 +// CHECK-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 3 +// CHECK-NEXT: store ptr null, ptr [[TMP54]], align 8 +// CHECK-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 4 +// CHECK-NEXT: store ptr [[VLA]], ptr [[TMP55]], align 8 +// CHECK-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 4 +// CHECK-NEXT: store ptr [[VLA]], ptr [[TMP56]], align 8 +// CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 4 +// CHECK-NEXT: store ptr null, ptr [[TMP57]], align 8 +// CHECK-NEXT: [[TMP58:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 5 +// CHECK-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP58]], align 8 +// CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 5 +// CHECK-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP59]], align 8 +// CHECK-NEXT: [[TMP60:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 5 +// CHECK-NEXT: store ptr null, ptr [[TMP60]], align 8 +// CHECK-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 6 +// CHECK-NEXT: store ptr [[D_TEAMS_DONE_PTR3]], ptr [[TMP61]], align 8 +// CHECK-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 6 +// CHECK-NEXT: store ptr [[D_TEAMS_DONE_PTR3]], ptr [[TMP62]], align 8 +// CHECK-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 6 +// CHECK-NEXT: store ptr null, ptr [[TMP63]], align 8 +// CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 7 +// CHECK-NEXT: store ptr [[D_SCAN_STORAGE2]], ptr [[TMP64]], align 8 +// CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 7 +// CHECK-NEXT: store ptr [[D_SCAN_STORAGE2]], ptr [[TMP65]], align 8 +// CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 7 +// CHECK-NEXT: store ptr null, ptr [[TMP66]], align 8 +// CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 +// CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 +// CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0 +// CHECK-NEXT: store i32 3, ptr [[TMP69]], align 4 +// CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1 +// CHECK-NEXT: store i32 8, ptr [[TMP70]], align 4 +// CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[TMP67]], ptr [[TMP71]], align 8 +// CHECK-NEXT: [[TMP72:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3 +// CHECK-NEXT: store ptr [[TMP68]], ptr [[TMP72]], align 8 +// CHECK-NEXT: [[TMP73:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4 +// CHECK-NEXT: store ptr @.offload_sizes.1, ptr [[TMP73]], align 8 +// CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5 +// CHECK-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP74]], align 8 +// CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6 +// CHECK-NEXT: store ptr null, ptr [[TMP75]], align 8 +// CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7 +// CHECK-NEXT: store ptr null, ptr [[TMP76]], align 8 +// CHECK-NEXT: [[TMP77:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8 +// CHECK-NEXT: store i64 64000, ptr [[TMP77]], align 8 +// CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9 +// CHECK-NEXT: store i64 0, ptr [[TMP78]], align 8 +// CHECK-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10 +// CHECK-NEXT: store [3 x i32] [i32 250, i32 0, i32 0], ptr [[TMP79]], align 4 +// CHECK-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11 +// CHECK-NEXT: store [3 x i32] [i32 256, i32 0, i32 0], ptr [[TMP80]], align 4 +// CHECK-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12 +// CHECK-NEXT: store i32 0, ptr [[TMP81]], align 4 +// CHECK-NEXT: [[TMP82:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 250, i32 256, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14_1.region_id, ptr [[KERNEL_ARGS14]]) +// CHECK-NEXT: [[TMP83:%.*]] = icmp ne i32 [[TMP82]], 0 +// CHECK-NEXT: br i1 [[TMP83]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] +// CHECK: omp_offload.failed15: +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14_1(ptr [[SUM1]], ptr [[IN]], ptr [[OUT1]], i64 0, ptr [[VLA]], ptr [[D_TEAM_VALS5]], ptr [[D_TEAMS_DONE_PTR6]], ptr [[D_SCAN_STORAGE7]]) #[[ATTR3]] +// CHECK-NEXT: br label [[OMP_OFFLOAD_CONT16]] +// CHECK: omp_offload.cont16: +// CHECK-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV8]]) +// CHECK-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR3]], i32 [[DEFAULT_DEV8]]) +// CHECK-NEXT: call void @omp_target_free(ptr [[D_SCAN_STORAGE2]], i32 [[DEFAULT_DEV8]]) +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA]], i64 -1 +// CHECK-NEXT: [[TMP84:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: store i32 [[TMP84]], ptr [[SUM1]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM2]], align 4 +// CHECK-NEXT: [[VLA19:%.*]] = alloca i32, i64 0, align 16 +// CHECK-NEXT: [[D_TEAM_VALS20:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAM_VALS20]], align 4 +// CHECK-NEXT: [[D_TEAMS_DONE_PTR21:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR21]], align 4 +// CHECK-NEXT: [[D_SCAN_STORAGE22:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_SCAN_STORAGE22]], align 4 +// CHECK-NEXT: [[DEFAULT_DEV23:%.*]] = call i32 @omp_get_default_device() +// CHECK-NEXT: [[INITIAL_DEVID24:%.*]] = call i32 @omp_get_initial_device() +// CHECK-NEXT: [[D_TEAM_VALS25:%.*]] = call ptr @omp_target_alloc(i64 1000, i32 [[DEFAULT_DEV23]]) +// CHECK-NEXT: [[D_SCAN_STORAGE26:%.*]] = call ptr @omp_target_alloc(i64 512004, i32 [[DEFAULT_DEV23]]) +// CHECK-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR21]], align 4 +// CHECK-NEXT: [[D_TEAMS_DONE_PTR27:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV23]]) +// CHECK-NEXT: [[TMP85:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR27]], ptr [[D_TEAMS_DONE_PTR21]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV23]], i32 [[INITIAL_DEVID24]]) +// CHECK-NEXT: [[TMP86:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS28]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[OUT2]], ptr [[TMP86]], align 8 +// CHECK-NEXT: [[TMP87:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS29]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[OUT2]], ptr [[TMP87]], align 8 +// CHECK-NEXT: [[TMP88:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS30]], i64 0, i64 0 +// CHECK-NEXT: store ptr null, ptr [[TMP88]], align 8 +// CHECK-NEXT: [[TMP89:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS28]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[SUM2]], ptr [[TMP89]], align 8 +// CHECK-NEXT: [[TMP90:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS29]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[SUM2]], ptr [[TMP90]], align 8 +// CHECK-NEXT: [[TMP91:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS30]], i64 0, i64 1 +// CHECK-NEXT: store ptr null, ptr [[TMP91]], align 8 +// CHECK-NEXT: [[TMP92:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS28]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[IN]], ptr [[TMP92]], align 8 +// CHECK-NEXT: [[TMP93:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS29]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[IN]], ptr [[TMP93]], align 8 +// CHECK-NEXT: [[TMP94:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS30]], i64 0, i64 2 +// CHECK-NEXT: store ptr null, ptr [[TMP94]], align 8 +// CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS28]], i32 0, i32 3 +// CHECK-NEXT: store i64 0, ptr [[TMP95]], align 8 +// CHECK-NEXT: [[TMP96:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS29]], i32 0, i32 3 +// CHECK-NEXT: store i64 0, ptr [[TMP96]], align 8 +// CHECK-NEXT: [[TMP97:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS30]], i64 0, i64 3 +// CHECK-NEXT: store ptr null, ptr [[TMP97]], align 8 +// CHECK-NEXT: [[TMP98:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS28]], i32 0, i32 4 +// CHECK-NEXT: store ptr [[VLA19]], ptr [[TMP98]], align 8 +// CHECK-NEXT: [[TMP99:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS29]], i32 0, i32 4 +// CHECK-NEXT: store ptr [[VLA19]], ptr [[TMP99]], align 8 +// CHECK-NEXT: [[TMP100:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS30]], i64 0, i64 4 +// CHECK-NEXT: store ptr null, ptr [[TMP100]], align 8 +// CHECK-NEXT: [[TMP101:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS28]], i32 0, i32 5 +// CHECK-NEXT: store ptr [[D_TEAM_VALS25]], ptr [[TMP101]], align 8 +// CHECK-NEXT: [[TMP102:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS29]], i32 0, i32 5 +// CHECK-NEXT: store ptr [[D_TEAM_VALS25]], ptr [[TMP102]], align 8 +// CHECK-NEXT: [[TMP103:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS30]], i64 0, i64 5 +// CHECK-NEXT: store ptr null, ptr [[TMP103]], align 8 +// CHECK-NEXT: [[TMP104:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS28]], i32 0, i32 6 +// CHECK-NEXT: store ptr [[D_TEAMS_DONE_PTR27]], ptr [[TMP104]], align 8 +// CHECK-NEXT: [[TMP105:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS29]], i32 0, i32 6 +// CHECK-NEXT: store ptr [[D_TEAMS_DONE_PTR27]], ptr [[TMP105]], align 8 +// CHECK-NEXT: [[TMP106:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS30]], i64 0, i64 6 +// CHECK-NEXT: store ptr null, ptr [[TMP106]], align 8 +// CHECK-NEXT: [[TMP107:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS28]], i32 0, i32 7 +// CHECK-NEXT: store ptr [[D_SCAN_STORAGE26]], ptr [[TMP107]], align 8 +// CHECK-NEXT: [[TMP108:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS29]], i32 0, i32 7 +// CHECK-NEXT: store ptr [[D_SCAN_STORAGE26]], ptr [[TMP108]], align 8 +// CHECK-NEXT: [[TMP109:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS30]], i64 0, i64 7 +// CHECK-NEXT: store ptr null, ptr [[TMP109]], align 8 +// CHECK-NEXT: [[TMP110:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS28]], i32 0, i32 0 +// CHECK-NEXT: [[TMP111:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS29]], i32 0, i32 0 +// CHECK-NEXT: [[TMP112:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 0 +// CHECK-NEXT: store i32 3, ptr [[TMP112]], align 4 +// CHECK-NEXT: [[TMP113:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 1 +// CHECK-NEXT: store i32 8, ptr [[TMP113]], align 4 +// CHECK-NEXT: [[TMP114:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[TMP110]], ptr [[TMP114]], align 8 +// CHECK-NEXT: [[TMP115:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 3 +// CHECK-NEXT: store ptr [[TMP111]], ptr [[TMP115]], align 8 +// CHECK-NEXT: [[TMP116:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 4 +// CHECK-NEXT: store ptr @.offload_sizes.3, ptr [[TMP116]], align 8 +// CHECK-NEXT: [[TMP117:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 5 +// CHECK-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP117]], align 8 +// CHECK-NEXT: [[TMP118:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 6 +// CHECK-NEXT: store ptr null, ptr [[TMP118]], align 8 +// CHECK-NEXT: [[TMP119:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 7 +// CHECK-NEXT: store ptr null, ptr [[TMP119]], align 8 +// CHECK-NEXT: [[TMP120:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 8 +// CHECK-NEXT: store i64 64000, ptr [[TMP120]], align 8 +// CHECK-NEXT: [[TMP121:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 9 +// CHECK-NEXT: store i64 0, ptr [[TMP121]], align 8 +// CHECK-NEXT: [[TMP122:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 10 +// CHECK-NEXT: store [3 x i32] [i32 250, i32 0, i32 0], ptr [[TMP122]], align 4 +// CHECK-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 11 +// CHECK-NEXT: store [3 x i32] [i32 256, i32 0, i32 0], ptr [[TMP123]], align 4 +// CHECK-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS32]], i32 0, i32 12 +// CHECK-NEXT: store i32 0, ptr [[TMP124]], align 4 +// CHECK-NEXT: [[TMP125:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 250, i32 256, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24.region_id, ptr [[KERNEL_ARGS32]]) +// CHECK-NEXT: [[TMP126:%.*]] = icmp ne i32 [[TMP125]], 0 +// CHECK-NEXT: br i1 [[TMP126]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] +// CHECK: omp_offload.failed33: +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24(ptr [[OUT2]], ptr [[SUM2]], ptr [[IN]], i64 0, ptr [[VLA19]], ptr [[D_TEAM_VALS20]], ptr [[D_TEAMS_DONE_PTR21]], ptr [[D_SCAN_STORAGE22]]) #[[ATTR3]] +// CHECK-NEXT: br label [[OMP_OFFLOAD_CONT34]] +// CHECK: omp_offload.cont34: +// CHECK-NEXT: [[D_TEAM_VALS35:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAM_VALS35]], align 4 +// CHECK-NEXT: [[D_TEAMS_DONE_PTR36:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR36]], align 4 +// CHECK-NEXT: [[D_SCAN_STORAGE37:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_SCAN_STORAGE37]], align 4 +// CHECK-NEXT: [[DEFAULT_DEV38:%.*]] = call i32 @omp_get_default_device() +// CHECK-NEXT: [[INITIAL_DEVID39:%.*]] = call i32 @omp_get_initial_device() +// CHECK-NEXT: [[TMP127:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[OUT2]], ptr [[TMP127]], align 8 +// CHECK-NEXT: [[TMP128:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[OUT2]], ptr [[TMP128]], align 8 +// CHECK-NEXT: [[TMP129:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 +// CHECK-NEXT: store ptr null, ptr [[TMP129]], align 8 +// CHECK-NEXT: [[TMP130:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[SUM2]], ptr [[TMP130]], align 8 +// CHECK-NEXT: [[TMP131:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS41]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[SUM2]], ptr [[TMP131]], align 8 +// CHECK-NEXT: [[TMP132:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 1 +// CHECK-NEXT: store ptr null, ptr [[TMP132]], align 8 +// CHECK-NEXT: [[TMP133:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[IN]], ptr [[TMP133]], align 8 +// CHECK-NEXT: [[TMP134:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS41]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[IN]], ptr [[TMP134]], align 8 +// CHECK-NEXT: [[TMP135:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 2 +// CHECK-NEXT: store ptr null, ptr [[TMP135]], align 8 +// CHECK-NEXT: [[TMP136:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 3 +// CHECK-NEXT: store i64 0, ptr [[TMP136]], align 8 +// CHECK-NEXT: [[TMP137:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS41]], i32 0, i32 3 +// CHECK-NEXT: store i64 0, ptr [[TMP137]], align 8 +// CHECK-NEXT: [[TMP138:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 3 +// CHECK-NEXT: store ptr null, ptr [[TMP138]], align 8 +// CHECK-NEXT: [[TMP139:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 4 +// CHECK-NEXT: store ptr [[VLA19]], ptr [[TMP139]], align 8 +// CHECK-NEXT: [[TMP140:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS41]], i32 0, i32 4 +// CHECK-NEXT: store ptr [[VLA19]], ptr [[TMP140]], align 8 +// CHECK-NEXT: [[TMP141:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 4 +// CHECK-NEXT: store ptr null, ptr [[TMP141]], align 8 +// CHECK-NEXT: [[TMP142:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 5 +// CHECK-NEXT: store ptr [[D_TEAM_VALS25]], ptr [[TMP142]], align 8 +// CHECK-NEXT: [[TMP143:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS41]], i32 0, i32 5 +// CHECK-NEXT: store ptr [[D_TEAM_VALS25]], ptr [[TMP143]], align 8 +// CHECK-NEXT: [[TMP144:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 5 +// CHECK-NEXT: store ptr null, ptr [[TMP144]], align 8 +// CHECK-NEXT: [[TMP145:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 6 +// CHECK-NEXT: store ptr [[D_TEAMS_DONE_PTR27]], ptr [[TMP145]], align 8 +// CHECK-NEXT: [[TMP146:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS41]], i32 0, i32 6 +// CHECK-NEXT: store ptr [[D_TEAMS_DONE_PTR27]], ptr [[TMP146]], align 8 +// CHECK-NEXT: [[TMP147:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 6 +// CHECK-NEXT: store ptr null, ptr [[TMP147]], align 8 +// CHECK-NEXT: [[TMP148:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 7 +// CHECK-NEXT: store ptr [[D_SCAN_STORAGE26]], ptr [[TMP148]], align 8 +// CHECK-NEXT: [[TMP149:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS41]], i32 0, i32 7 +// CHECK-NEXT: store ptr [[D_SCAN_STORAGE26]], ptr [[TMP149]], align 8 +// CHECK-NEXT: [[TMP150:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 7 +// CHECK-NEXT: store ptr null, ptr [[TMP150]], align 8 +// CHECK-NEXT: [[TMP151:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 +// CHECK-NEXT: [[TMP152:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 +// CHECK-NEXT: [[TMP153:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 0 +// CHECK-NEXT: store i32 3, ptr [[TMP153]], align 4 +// CHECK-NEXT: [[TMP154:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 1 +// CHECK-NEXT: store i32 8, ptr [[TMP154]], align 4 +// CHECK-NEXT: [[TMP155:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 2 +// CHECK-NEXT: store ptr [[TMP151]], ptr [[TMP155]], align 8 +// CHECK-NEXT: [[TMP156:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 3 +// CHECK-NEXT: store ptr [[TMP152]], ptr [[TMP156]], align 8 +// CHECK-NEXT: [[TMP157:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 4 +// CHECK-NEXT: store ptr @.offload_sizes.5, ptr [[TMP157]], align 8 +// CHECK-NEXT: [[TMP158:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 5 +// CHECK-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP158]], align 8 +// CHECK-NEXT: [[TMP159:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 6 +// CHECK-NEXT: store ptr null, ptr [[TMP159]], align 8 +// CHECK-NEXT: [[TMP160:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 7 +// CHECK-NEXT: store ptr null, ptr [[TMP160]], align 8 +// CHECK-NEXT: [[TMP161:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 8 +// CHECK-NEXT: store i64 64000, ptr [[TMP161]], align 8 +// CHECK-NEXT: [[TMP162:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 9 +// CHECK-NEXT: store i64 0, ptr [[TMP162]], align 8 +// CHECK-NEXT: [[TMP163:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 10 +// CHECK-NEXT: store [3 x i32] [i32 250, i32 0, i32 0], ptr [[TMP163]], align 4 +// CHECK-NEXT: [[TMP164:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 11 +// CHECK-NEXT: store [3 x i32] [i32 256, i32 0, i32 0], ptr [[TMP164]], align 4 +// CHECK-NEXT: [[TMP165:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS44]], i32 0, i32 12 +// CHECK-NEXT: store i32 0, ptr [[TMP165]], align 4 +// CHECK-NEXT: [[TMP166:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 250, i32 256, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_1.region_id, ptr [[KERNEL_ARGS44]]) +// CHECK-NEXT: [[TMP167:%.*]] = icmp ne i32 [[TMP166]], 0 +// CHECK-NEXT: br i1 [[TMP167]], label [[OMP_OFFLOAD_FAILED45:%.*]], label [[OMP_OFFLOAD_CONT46:%.*]] +// CHECK: omp_offload.failed45: +// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_1(ptr [[OUT2]], ptr [[SUM2]], ptr [[IN]], i64 0, ptr [[VLA19]], ptr [[D_TEAM_VALS35]], ptr [[D_TEAMS_DONE_PTR36]], ptr [[D_SCAN_STORAGE37]]) #[[ATTR3]] +// CHECK-NEXT: br label [[OMP_OFFLOAD_CONT46]] +// CHECK: omp_offload.cont46: +// CHECK-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS25]], i32 [[DEFAULT_DEV38]]) +// CHECK-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR27]], i32 [[DEFAULT_DEV38]]) +// CHECK-NEXT: call void @omp_target_free(ptr [[D_SCAN_STORAGE26]], i32 [[DEFAULT_DEV38]]) +// CHECK-NEXT: [[ARRAYIDX48:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA19]], i64 -1 +// CHECK-NEXT: [[TMP168:%.*]] = load i32, ptr [[ARRAYIDX48]], align 4 +// CHECK-NEXT: store i32 [[TMP168]], ptr [[SUM2]], align 4 +// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK-NEXT: [[TMP169:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP169]]) +// CHECK-NEXT: [[TMP170:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK-NEXT: ret i32 [[TMP170]] +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT1:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM11:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[OUT1_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[SUM1_ADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB4]]) +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR]], align 8 +// CHECK-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: store ptr [[OUT1]], ptr [[OUT1_ADDR]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM11]], ptr [[SUM1_ADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM1_ADDR]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OUT1_ADDR]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[SUM1_ADDR2]], align 8 +// CHECK-NEXT: [[TMP_VLA:%.*]] = alloca i32, i64 64000, align 4 +// CHECK-NEXT: store ptr [[TMP_VLA]], ptr [[TMP8]], align 16 +// CHECK-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP3]], i32 250, i32 0) +// CHECK-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK-NEXT: [[D_SCAN_STORAGE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_SCAN_STORAGE]], align 4 +// CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 8, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.omp_outlined, ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], i64 [[TMP7]], ptr [[TMP8]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]], ptr [[D_SCAN_STORAGE]]) +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 63999 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: store i32 [[TMP9]], ptr [[TMP4]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT1:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM11:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[OUT1_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[SUM1_ADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR]], align 8 +// CHECK-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: store ptr [[OUT1]], ptr [[OUT1_ADDR]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM11]], ptr [[SUM1_ADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM1_ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OUT1_ADDR]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SUM1_ADDR2]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: store i32 63999, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 63999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 63999, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB4]], i32 [[TMP9]], i32 256) +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK-NEXT: [[D_SCAN_STORAGE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_SCAN_STORAGE]], align 4 +// CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.omp_outlined.omp_outlined, i64 [[TMP16]], i64 [[TMP18]], ptr [[TMP3]], ptr [[TMP4]], ptr [[TMP5]], i64 [[TMP6]], ptr [[TMP7]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]], ptr [[D_SCAN_STORAGE]]) +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]]) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.omp_outlined.omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT1:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM11:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[OUT1_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[SUM1_ADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[SUM17:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_LB18:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_UB19:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE20:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST21:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I22:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[SUM133:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR]], align 8 +// CHECK-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: store ptr [[OUT1]], ptr [[OUT1_ADDR]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM11]], ptr [[SUM1_ADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM1_ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OUT1_ADDR]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SUM1_ADDR2]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 63999, ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 63999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 63999, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM17]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[SUM17]], align 4 +// CHECK-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP18]], [[TMP17]] +// CHECK-NEXT: store i32 [[ADD8]], ptr [[SUM17]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP7]], i64 [[TMP20]] +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[SUM17]], align 4 +// CHECK-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX9]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[SUM17]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP5]], i64 0, i64 [[IDXPROM10]] +// CHECK-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX11]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP9]]) +// CHECK-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP9]]) +// CHECK-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB4]], i32 [[TMP9]]) +// CHECK-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK: omp_if.then: +// CHECK-NEXT: [[TMP27:%.*]] = call double @llvm.log2.f64(double 6.400000e+04) #[[ATTR3]] +// CHECK-NEXT: [[TMP28:%.*]] = call double @llvm.ceil.f64(double [[TMP27]]) #[[ATTR3]] +// CHECK-NEXT: [[TMP29:%.*]] = fptoui double [[TMP28]] to i32 +// CHECK-NEXT: br label [[OMP_OUTER_LOG_SCAN_BODY:%.*]] +// CHECK: omp.outer.log.scan.body: +// CHECK-NEXT: [[TMP30:%.*]] = phi i32 [ 0, [[OMP_IF_THEN]] ], [ [[TMP39:%.*]], [[OMP_INNER_LOG_SCAN_EXIT:%.*]] ] +// CHECK-NEXT: [[TMP31:%.*]] = phi i64 [ 1, [[OMP_IF_THEN]] ], [ [[TMP40:%.*]], [[OMP_INNER_LOG_SCAN_EXIT]] ] +// CHECK-NEXT: [[TMP32:%.*]] = icmp uge i64 63999, [[TMP31]] +// CHECK-NEXT: br i1 [[TMP32]], label [[OMP_INNER_LOG_SCAN_BODY:%.*]], label [[OMP_INNER_LOG_SCAN_EXIT]] +// CHECK: omp.inner.log.scan.body: +// CHECK-NEXT: [[TMP33:%.*]] = phi i64 [ 63999, [[OMP_OUTER_LOG_SCAN_BODY]] ], [ [[TMP37:%.*]], [[OMP_INNER_LOG_SCAN_BODY]] ] +// CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP7]], i64 [[TMP33]] +// CHECK-NEXT: [[TMP34:%.*]] = sub nuw i64 [[TMP33]], [[TMP31]] +// CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP7]], i64 [[TMP34]] +// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[ARRAYIDX13]], align 4 +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4 +// CHECK-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX13]], align 4 +// CHECK-NEXT: [[TMP37]] = sub nuw i64 [[TMP33]], 1 +// CHECK-NEXT: [[TMP38:%.*]] = icmp uge i64 [[TMP37]], [[TMP31]] +// CHECK-NEXT: br i1 [[TMP38]], label [[OMP_INNER_LOG_SCAN_BODY]], label [[OMP_INNER_LOG_SCAN_EXIT]] +// CHECK: omp.inner.log.scan.exit: +// CHECK-NEXT: [[TMP39]] = add nuw i32 [[TMP30]], 1 +// CHECK-NEXT: [[TMP40]] = shl nuw i64 [[TMP31]], 1 +// CHECK-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP39]], [[TMP29]] +// CHECK-NEXT: br i1 [[TMP41]], label [[OMP_OUTER_LOG_SCAN_BODY]], label [[OMP_OUTER_LOG_SCAN_EXIT:%.*]] +// CHECK: omp.outer.log.scan.exit: +// CHECK-NEXT: call void @__kmpc_end_master(ptr @[[GLOB4]], i32 [[TMP9]]) +// CHECK-NEXT: br label [[OMP_IF_END]] +// CHECK: omp_if.end: +// CHECK-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP9]]) +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB18]], align 4 +// CHECK-NEXT: store i32 63999, ptr [[DOTOMP_UB19]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE20]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST21]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST21]], ptr [[DOTOMP_LB18]], ptr [[DOTOMP_UB19]], ptr [[DOTOMP_STRIDE20]], i32 1, i32 1) +// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_UB19]], align 4 +// CHECK-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP42]], 63999 +// CHECK-NEXT: br i1 [[CMP23]], label [[COND_TRUE24:%.*]], label [[COND_FALSE25:%.*]] +// CHECK: cond.true24: +// CHECK-NEXT: br label [[COND_END26:%.*]] +// CHECK: cond.false25: +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_UB19]], align 4 +// CHECK-NEXT: br label [[COND_END26]] +// CHECK: cond.end26: +// CHECK-NEXT: [[COND27:%.*]] = phi i32 [ 63999, [[COND_TRUE24]] ], [ [[TMP43]], [[COND_FALSE25]] ] +// CHECK-NEXT: store i32 [[COND27]], ptr [[DOTOMP_UB19]], align 4 +// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_LB18]], align 4 +// CHECK-NEXT: store i32 [[TMP44]], ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND28:%.*]] +// CHECK: omp.inner.for.cond28: +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_UB19]], align 4 +// CHECK-NEXT: [[CMP29:%.*]] = icmp sle i32 [[TMP45]], [[TMP46]] +// CHECK-NEXT: br i1 [[CMP29]], label [[OMP_INNER_FOR_BODY30:%.*]], label [[OMP_INNER_FOR_END47:%.*]] +// CHECK: omp.inner.for.body30: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: [[MUL31:%.*]] = mul nsw i32 [[TMP47]], 1 +// CHECK-NEXT: [[ADD32:%.*]] = add nsw i32 0, [[MUL31]] +// CHECK-NEXT: store i32 [[ADD32]], ptr [[I22]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM133]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH39:%.*]] +// CHECK: omp.before.scan.bb34: +// CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[I22]], align 4 +// CHECK-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP48]] to i64 +// CHECK-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM35]] +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[ARRAYIDX36]], align 4 +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[SUM133]], align 4 +// CHECK-NEXT: [[ADD37:%.*]] = add nsw i32 [[TMP50]], [[TMP49]] +// CHECK-NEXT: store i32 [[ADD37]], ptr [[SUM133]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE44:%.*]] +// CHECK: omp.exit.inscan.bb38: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE44]] +// CHECK: omp.inscan.dispatch39: +// CHECK-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: [[TMP52:%.*]] = zext i32 [[TMP51]] to i64 +// CHECK-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP7]], i64 [[TMP52]] +// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[ARRAYIDX40]], align 4 +// CHECK-NEXT: store i32 [[TMP53]], ptr [[SUM133]], align 4 +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB41:%.*]] +// CHECK: omp.after.scan.bb41: +// CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr [[SUM133]], align 4 +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr [[I22]], align 4 +// CHECK-NEXT: [[IDXPROM42:%.*]] = sext i32 [[TMP55]] to i64 +// CHECK-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP5]], i64 0, i64 [[IDXPROM42]] +// CHECK-NEXT: store i32 [[TMP54]], ptr [[ARRAYIDX43]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB38:%.*]] +// CHECK: omp.body.continue44: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC45:%.*]] +// CHECK: omp.inner.for.inc45: +// CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP56]], 1 +// CHECK-NEXT: store i32 [[ADD46]], ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND28]] +// CHECK: omp.inner.for.end47: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT48:%.*]] +// CHECK: omp.loop.exit48: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP9]]) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14_1 +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT1:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM11:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[OUT1_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[SUM1_ADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR]], align 8 +// CHECK-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: store ptr [[OUT1]], ptr [[OUT1_ADDR]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM11]], ptr [[SUM1_ADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SUM1_ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OUT1_ADDR]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SUM1_ADDR2]], align 8 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(256000) [[OUT2:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM2:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM21:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[SUM2_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[SUM2_ADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB4]]) +// CHECK-NEXT: store ptr [[OUT2]], ptr [[OUT2_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM2]], ptr [[SUM2_ADDR]], align 8 +// CHECK-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM21]], ptr [[SUM2_ADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT2_ADDR]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM2_ADDR]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[SUM2_ADDR2]], align 8 +// CHECK-NEXT: [[TMP_VLA:%.*]] = alloca i32, i64 64000, align 4 +// CHECK-NEXT: store ptr [[TMP_VLA]], ptr [[TMP8]], align 16 +// CHECK-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP3]], i32 250, i32 0) +// CHECK-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK-NEXT: [[D_SCAN_STORAGE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_SCAN_STORAGE]], align 4 +// CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 8, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24.omp_outlined, ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], i64 [[TMP7]], ptr [[TMP8]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]], ptr [[D_SCAN_STORAGE]]) +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 63999 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: store i32 [[TMP9]], ptr [[TMP5]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24.omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT2:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM2:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM21:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[SUM2_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[SUM2_ADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[OUT2]], ptr [[OUT2_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM2]], ptr [[SUM2_ADDR]], align 8 +// CHECK-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM21]], ptr [[SUM2_ADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OUT2_ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM2_ADDR]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SUM2_ADDR2]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: store i32 63999, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 63999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 63999, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB4]], i32 [[TMP9]], i32 256) +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// CHECK-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// CHECK-NEXT: [[D_SCAN_STORAGE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr null, ptr [[D_SCAN_STORAGE]], align 4 +// CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24.omp_outlined.omp_outlined, i64 [[TMP16]], i64 [[TMP18]], ptr [[TMP3]], ptr [[TMP4]], ptr [[TMP5]], i64 [[TMP6]], ptr [[TMP7]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]], ptr [[D_SCAN_STORAGE]]) +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]]) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24.omp_outlined.omp_outlined +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT2:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM2:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM21:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[SUM2_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[SUM2_ADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[SUM27:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_LB18:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_UB19:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_STRIDE20:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[DOTOMP_IS_LAST21:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[I22:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[SUM233:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// CHECK-NEXT: store ptr [[OUT2]], ptr [[OUT2_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM2]], ptr [[SUM2_ADDR]], align 8 +// CHECK-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM21]], ptr [[SUM2_ADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OUT2_ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM2_ADDR]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SUM2_ADDR2]], align 8 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 63999, ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 63999 +// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK: cond.true: +// CHECK-NEXT: br label [[COND_END:%.*]] +// CHECK: cond.false: +// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: br label [[COND_END]] +// CHECK: cond.end: +// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 63999, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] +// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK: omp.inner.for.cond: +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] +// CHECK-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK: omp.inner.for.body: +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM27]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// CHECK: omp.before.scan.bb: +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[SUM27]], align 4 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP3]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK: omp.exit.inscan.bb: +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP7]], i64 [[TMP19]] +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[SUM27]], align 4 +// CHECK-NEXT: store i32 [[TMP20]], ptr [[ARRAYIDX8]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE]] +// CHECK: omp.inscan.dispatch: +// CHECK-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// CHECK: omp.after.scan.bb: +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP21]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP5]], i64 0, i64 [[IDXPROM9]] +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[SUM27]], align 4 +// CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] +// CHECK-NEXT: store i32 [[ADD11]], ptr [[SUM27]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// CHECK: omp.body.continue: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK: omp.inner.for.inc: +// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP24]], 1 +// CHECK-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK: omp.inner.for.end: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK: omp.loop.exit: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP9]]) +// CHECK-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP9]]) +// CHECK-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB4]], i32 [[TMP9]]) +// CHECK-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 +// CHECK-NEXT: br i1 [[TMP26]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// CHECK: omp_if.then: +// CHECK-NEXT: [[TMP27:%.*]] = call double @llvm.log2.f64(double 6.400000e+04) #[[ATTR3]] +// CHECK-NEXT: [[TMP28:%.*]] = call double @llvm.ceil.f64(double [[TMP27]]) #[[ATTR3]] +// CHECK-NEXT: [[TMP29:%.*]] = fptoui double [[TMP28]] to i32 +// CHECK-NEXT: br label [[OMP_OUTER_LOG_SCAN_BODY:%.*]] +// CHECK: omp.outer.log.scan.body: +// CHECK-NEXT: [[TMP30:%.*]] = phi i32 [ 0, [[OMP_IF_THEN]] ], [ [[TMP39:%.*]], [[OMP_INNER_LOG_SCAN_EXIT:%.*]] ] +// CHECK-NEXT: [[TMP31:%.*]] = phi i64 [ 1, [[OMP_IF_THEN]] ], [ [[TMP40:%.*]], [[OMP_INNER_LOG_SCAN_EXIT]] ] +// CHECK-NEXT: [[TMP32:%.*]] = icmp uge i64 63999, [[TMP31]] +// CHECK-NEXT: br i1 [[TMP32]], label [[OMP_INNER_LOG_SCAN_BODY:%.*]], label [[OMP_INNER_LOG_SCAN_EXIT]] +// CHECK: omp.inner.log.scan.body: +// CHECK-NEXT: [[TMP33:%.*]] = phi i64 [ 63999, [[OMP_OUTER_LOG_SCAN_BODY]] ], [ [[TMP37:%.*]], [[OMP_INNER_LOG_SCAN_BODY]] ] +// CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP7]], i64 [[TMP33]] +// CHECK-NEXT: [[TMP34:%.*]] = sub nuw i64 [[TMP33]], [[TMP31]] +// CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP7]], i64 [[TMP34]] +// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[ARRAYIDX13]], align 4 +// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4 +// CHECK-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP35]], [[TMP36]] +// CHECK-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX13]], align 4 +// CHECK-NEXT: [[TMP37]] = sub nuw i64 [[TMP33]], 1 +// CHECK-NEXT: [[TMP38:%.*]] = icmp uge i64 [[TMP37]], [[TMP31]] +// CHECK-NEXT: br i1 [[TMP38]], label [[OMP_INNER_LOG_SCAN_BODY]], label [[OMP_INNER_LOG_SCAN_EXIT]] +// CHECK: omp.inner.log.scan.exit: +// CHECK-NEXT: [[TMP39]] = add nuw i32 [[TMP30]], 1 +// CHECK-NEXT: [[TMP40]] = shl nuw i64 [[TMP31]], 1 +// CHECK-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP39]], [[TMP29]] +// CHECK-NEXT: br i1 [[TMP41]], label [[OMP_OUTER_LOG_SCAN_BODY]], label [[OMP_OUTER_LOG_SCAN_EXIT:%.*]] +// CHECK: omp.outer.log.scan.exit: +// CHECK-NEXT: call void @__kmpc_end_master(ptr @[[GLOB4]], i32 [[TMP9]]) +// CHECK-NEXT: br label [[OMP_IF_END]] +// CHECK: omp_if.end: +// CHECK-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP9]]) +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB18]], align 4 +// CHECK-NEXT: store i32 63999, ptr [[DOTOMP_UB19]], align 4 +// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE20]], align 4 +// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST21]], align 4 +// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST21]], ptr [[DOTOMP_LB18]], ptr [[DOTOMP_UB19]], ptr [[DOTOMP_STRIDE20]], i32 1, i32 1) +// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_UB19]], align 4 +// CHECK-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP42]], 63999 +// CHECK-NEXT: br i1 [[CMP23]], label [[COND_TRUE24:%.*]], label [[COND_FALSE25:%.*]] +// CHECK: cond.true24: +// CHECK-NEXT: br label [[COND_END26:%.*]] +// CHECK: cond.false25: +// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_UB19]], align 4 +// CHECK-NEXT: br label [[COND_END26]] +// CHECK: cond.end26: +// CHECK-NEXT: [[COND27:%.*]] = phi i32 [ 63999, [[COND_TRUE24]] ], [ [[TMP43]], [[COND_FALSE25]] ] +// CHECK-NEXT: store i32 [[COND27]], ptr [[DOTOMP_UB19]], align 4 +// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_LB18]], align 4 +// CHECK-NEXT: store i32 [[TMP44]], ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND28:%.*]] +// CHECK: omp.inner.for.cond28: +// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_UB19]], align 4 +// CHECK-NEXT: [[CMP29:%.*]] = icmp sle i32 [[TMP45]], [[TMP46]] +// CHECK-NEXT: br i1 [[CMP29]], label [[OMP_INNER_FOR_BODY30:%.*]], label [[OMP_INNER_FOR_END47:%.*]] +// CHECK: omp.inner.for.body30: +// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: [[MUL31:%.*]] = mul nsw i32 [[TMP47]], 1 +// CHECK-NEXT: [[ADD32:%.*]] = add nsw i32 0, [[MUL31]] +// CHECK-NEXT: store i32 [[ADD32]], ptr [[I22]], align 4 +// CHECK-NEXT: store i32 0, ptr [[SUM233]], align 4 +// CHECK-NEXT: br label [[OMP_INSCAN_DISPATCH38:%.*]] +// CHECK: omp.before.scan.bb34: +// CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[SUM233]], align 4 +// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[I22]], align 4 +// CHECK-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP49]] to i64 +// CHECK-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP3]], i64 0, i64 [[IDXPROM35]] +// CHECK-NEXT: store i32 [[TMP48]], ptr [[ARRAYIDX36]], align 4 +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE44:%.*]] +// CHECK: omp.exit.inscan.bb37: +// CHECK-NEXT: br label [[OMP_BODY_CONTINUE44]] +// CHECK: omp.inscan.dispatch38: +// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: [[TMP51:%.*]] = zext i32 [[TMP50]] to i64 +// CHECK-NEXT: [[TMP52:%.*]] = icmp eq i64 [[TMP51]], 0 +// CHECK-NEXT: br i1 [[TMP52]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// CHECK: omp.exclusive.dec: +// CHECK-NEXT: [[TMP53:%.*]] = sub nuw i64 [[TMP51]], 1 +// CHECK-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP7]], i64 [[TMP53]] +// CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr [[ARRAYIDX39]], align 4 +// CHECK-NEXT: store i32 [[TMP54]], ptr [[SUM233]], align 4 +// CHECK-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// CHECK: omp.exclusive.copy.exit: +// CHECK-NEXT: br label [[OMP_BEFORE_SCAN_BB34:%.*]] +// CHECK: omp.after.scan.bb40: +// CHECK-NEXT: [[TMP55:%.*]] = load i32, ptr [[I22]], align 4 +// CHECK-NEXT: [[IDXPROM41:%.*]] = sext i32 [[TMP55]] to i64 +// CHECK-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP5]], i64 0, i64 [[IDXPROM41]] +// CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr [[ARRAYIDX42]], align 4 +// CHECK-NEXT: [[TMP57:%.*]] = load i32, ptr [[SUM233]], align 4 +// CHECK-NEXT: [[ADD43:%.*]] = add nsw i32 [[TMP57]], [[TMP56]] +// CHECK-NEXT: store i32 [[ADD43]], ptr [[SUM233]], align 4 +// CHECK-NEXT: br label [[OMP_EXIT_INSCAN_BB37:%.*]] +// CHECK: omp.body.continue44: +// CHECK-NEXT: br label [[OMP_INNER_FOR_INC45:%.*]] +// CHECK: omp.inner.for.inc45: +// CHECK-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP58]], 1 +// CHECK-NEXT: store i32 [[ADD46]], ptr [[DOTOMP_IV16]], align 4 +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND28]] +// CHECK: omp.inner.for.end47: +// CHECK-NEXT: br label [[OMP_LOOP_EXIT48:%.*]] +// CHECK: omp.loop.exit48: +// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP9]]) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_1 +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(256000) [[OUT2:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM2:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM21:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[SUM2_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[SUM2_ADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[OUT2]], ptr [[OUT2_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM2]], ptr [[SUM2_ADDR]], align 8 +// CHECK-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: store ptr [[SUM21]], ptr [[SUM2_ADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OUT2_ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM2_ADDR]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SUM2_ADDR2]], align 8 +// CHECK-NEXT: ret void +// +// +// SEGMENTED-LABEL: define {{[^@]+}}@main +// SEGMENTED-SAME: () #[[ATTR0:[0-9]+]] { +// SEGMENTED-NEXT: entry: +// SEGMENTED-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[IN:%.*]] = alloca [64000 x i32], align 16 +// SEGMENTED-NEXT: [[OUT1:%.*]] = alloca [64000 x i32], align 16 +// SEGMENTED-NEXT: [[SUM1:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[_TMP5:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 +// SEGMENTED-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// SEGMENTED-NEXT: [[_TMP19:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[SUM2:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[OUT2:%.*]] = alloca [64000 x i32], align 16 +// SEGMENTED-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_LB30:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_UB31:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOFFLOAD_BASEPTRS36:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[DOTOFFLOAD_PTRS37:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[DOTOFFLOAD_MAPPERS38:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[_TMP39:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[KERNEL_ARGS40:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// SEGMENTED-NEXT: [[DOTOFFLOAD_BASEPTRS49:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[DOTOFFLOAD_PTRS50:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[DOTOFFLOAD_MAPPERS51:%.*]] = alloca [9 x ptr], align 8 +// SEGMENTED-NEXT: [[_TMP52:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[KERNEL_ARGS53:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// SEGMENTED-NEXT: [[_TMP56:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[SUM1]], align 4 +// SEGMENTED-NEXT: [[TMP0:%.*]] = call ptr @llvm.stacksave.p0() +// SEGMENTED-NEXT: store ptr [[TMP0]], ptr [[SAVED_STACK]], align 8 +// SEGMENTED-NEXT: [[VLA:%.*]] = alloca i32, i64 0, align 16 +// SEGMENTED-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// SEGMENTED-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// SEGMENTED-NEXT: [[D_SCAN_STORAGE:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SCAN_STORAGE]], align 4 +// SEGMENTED-NEXT: [[D_SEGMENT_VALS:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SEGMENT_VALS]], align 4 +// SEGMENTED-NEXT: [[DEFAULT_DEV:%.*]] = call i32 @omp_get_default_device() +// SEGMENTED-NEXT: [[INITIAL_DEVID:%.*]] = call i32 @omp_get_initial_device() +// SEGMENTED-NEXT: [[D_TEAM_VALS1:%.*]] = call ptr @omp_target_alloc(i64 1000, i32 [[DEFAULT_DEV]]) +// SEGMENTED-NEXT: [[D_SCAN_STORAGE2:%.*]] = call ptr @omp_target_alloc(i64 512004, i32 [[DEFAULT_DEV]]) +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// SEGMENTED-NEXT: store i32 63999, ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// SEGMENTED-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[TMP1]] +// SEGMENTED-NEXT: [[SEGMENT_VALS_SIZE:%.*]] = add i32 [[TMP3]], 1 +// SEGMENTED-NEXT: [[TMP4:%.*]] = zext i32 [[SEGMENT_VALS_SIZE]] to i64 +// SEGMENTED-NEXT: [[D_SEGMENT_VALS_SZ:%.*]] = mul i64 4, [[TMP4]] +// SEGMENTED-NEXT: [[D_SEGMENT_VALS3:%.*]] = call ptr @omp_target_alloc(i64 [[D_SEGMENT_VALS_SZ]], i32 [[DEFAULT_DEV]]) +// SEGMENTED-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR]], align 4 +// SEGMENTED-NEXT: [[D_TEAMS_DONE_PTR4:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV]]) +// SEGMENTED-NEXT: [[TMP5:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR4]], ptr [[D_TEAMS_DONE_PTR]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV]], i32 [[INITIAL_DEVID]]) +// SEGMENTED-NEXT: [[TMP6:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// SEGMENTED-NEXT: store ptr [[SUM1]], ptr [[TMP6]], align 8 +// SEGMENTED-NEXT: [[TMP7:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// SEGMENTED-NEXT: store ptr [[SUM1]], ptr [[TMP7]], align 8 +// SEGMENTED-NEXT: [[TMP8:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP8]], align 8 +// SEGMENTED-NEXT: [[TMP9:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[TMP9]], align 8 +// SEGMENTED-NEXT: [[TMP10:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[TMP10]], align 8 +// SEGMENTED-NEXT: [[TMP11:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP11]], align 8 +// SEGMENTED-NEXT: [[TMP12:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[OUT1]], ptr [[TMP12]], align 8 +// SEGMENTED-NEXT: [[TMP13:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[OUT1]], ptr [[TMP13]], align 8 +// SEGMENTED-NEXT: [[TMP14:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP14]], align 8 +// SEGMENTED-NEXT: [[TMP15:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP15]], align 8 +// SEGMENTED-NEXT: [[TMP16:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP16]], align 8 +// SEGMENTED-NEXT: [[TMP17:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP17]], align 8 +// SEGMENTED-NEXT: [[TMP18:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr [[VLA]], ptr [[TMP18]], align 8 +// SEGMENTED-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr [[VLA]], ptr [[TMP19]], align 8 +// SEGMENTED-NEXT: [[TMP20:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP20]], align 8 +// SEGMENTED-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP21]], align 8 +// SEGMENTED-NEXT: [[TMP22:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP22]], align 8 +// SEGMENTED-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP23]], align 8 +// SEGMENTED-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr [[D_TEAMS_DONE_PTR4]], ptr [[TMP24]], align 8 +// SEGMENTED-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr [[D_TEAMS_DONE_PTR4]], ptr [[TMP25]], align 8 +// SEGMENTED-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP26]], align 8 +// SEGMENTED-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr [[D_SCAN_STORAGE2]], ptr [[TMP27]], align 8 +// SEGMENTED-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr [[D_SCAN_STORAGE2]], ptr [[TMP28]], align 8 +// SEGMENTED-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP29]], align 8 +// SEGMENTED-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 +// SEGMENTED-NEXT: store ptr [[D_SEGMENT_VALS3]], ptr [[TMP30]], align 8 +// SEGMENTED-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8 +// SEGMENTED-NEXT: store ptr [[D_SEGMENT_VALS3]], ptr [[TMP31]], align 8 +// SEGMENTED-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP32]], align 8 +// SEGMENTED-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// SEGMENTED-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// SEGMENTED-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// SEGMENTED-NEXT: store i32 3, ptr [[TMP35]], align 4 +// SEGMENTED-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// SEGMENTED-NEXT: store i32 9, ptr [[TMP36]], align 4 +// SEGMENTED-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[TMP33]], ptr [[TMP37]], align 8 +// SEGMENTED-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// SEGMENTED-NEXT: store ptr [[TMP34]], ptr [[TMP38]], align 8 +// SEGMENTED-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr @.offload_sizes, ptr [[TMP39]], align 8 +// SEGMENTED-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr @.offload_maptypes, ptr [[TMP40]], align 8 +// SEGMENTED-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP41]], align 8 +// SEGMENTED-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP42]], align 8 +// SEGMENTED-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// SEGMENTED-NEXT: store i64 64000, ptr [[TMP43]], align 8 +// SEGMENTED-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP44]], align 8 +// SEGMENTED-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// SEGMENTED-NEXT: store [3 x i32] [i32 250, i32 0, i32 0], ptr [[TMP45]], align 4 +// SEGMENTED-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// SEGMENTED-NEXT: store [3 x i32] [i32 256, i32 0, i32 0], ptr [[TMP46]], align 4 +// SEGMENTED-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// SEGMENTED-NEXT: store i32 0, ptr [[TMP47]], align 4 +// SEGMENTED-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 250, i32 256, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.region_id, ptr [[KERNEL_ARGS]]) +// SEGMENTED-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 +// SEGMENTED-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// SEGMENTED: omp_offload.failed: +// SEGMENTED-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14(ptr [[SUM1]], ptr [[IN]], ptr [[OUT1]], i64 0, ptr [[VLA]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]], ptr [[D_SCAN_STORAGE]], ptr [[D_SEGMENT_VALS]]) #[[ATTR3:[0-9]+]] +// SEGMENTED-NEXT: br label [[OMP_OFFLOAD_CONT]] +// SEGMENTED: omp_offload.cont: +// SEGMENTED-NEXT: [[D_TEAM_VALS6:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAM_VALS6]], align 4 +// SEGMENTED-NEXT: [[D_TEAMS_DONE_PTR7:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR7]], align 4 +// SEGMENTED-NEXT: [[D_SCAN_STORAGE8:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SCAN_STORAGE8]], align 4 +// SEGMENTED-NEXT: [[D_SEGMENT_VALS9:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SEGMENT_VALS9]], align 4 +// SEGMENTED-NEXT: [[DEFAULT_DEV10:%.*]] = call i32 @omp_get_default_device() +// SEGMENTED-NEXT: [[INITIAL_DEVID11:%.*]] = call i32 @omp_get_initial_device() +// SEGMENTED-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// SEGMENTED-NEXT: store ptr [[SUM1]], ptr [[TMP50]], align 8 +// SEGMENTED-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// SEGMENTED-NEXT: store ptr [[SUM1]], ptr [[TMP51]], align 8 +// SEGMENTED-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS14]], i64 0, i64 0 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP52]], align 8 +// SEGMENTED-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[TMP53]], align 8 +// SEGMENTED-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[TMP54]], align 8 +// SEGMENTED-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS14]], i64 0, i64 1 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP55]], align 8 +// SEGMENTED-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[OUT1]], ptr [[TMP56]], align 8 +// SEGMENTED-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS13]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[OUT1]], ptr [[TMP57]], align 8 +// SEGMENTED-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS14]], i64 0, i64 2 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP58]], align 8 +// SEGMENTED-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 3 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP59]], align 8 +// SEGMENTED-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS13]], i32 0, i32 3 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP60]], align 8 +// SEGMENTED-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS14]], i64 0, i64 3 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP61]], align 8 +// SEGMENTED-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr [[VLA]], ptr [[TMP62]], align 8 +// SEGMENTED-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS13]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr [[VLA]], ptr [[TMP63]], align 8 +// SEGMENTED-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS14]], i64 0, i64 4 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP64]], align 8 +// SEGMENTED-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP65]], align 8 +// SEGMENTED-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS13]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr [[D_TEAM_VALS1]], ptr [[TMP66]], align 8 +// SEGMENTED-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS14]], i64 0, i64 5 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP67]], align 8 +// SEGMENTED-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr [[D_TEAMS_DONE_PTR4]], ptr [[TMP68]], align 8 +// SEGMENTED-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS13]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr [[D_TEAMS_DONE_PTR4]], ptr [[TMP69]], align 8 +// SEGMENTED-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS14]], i64 0, i64 6 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP70]], align 8 +// SEGMENTED-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr [[D_SCAN_STORAGE2]], ptr [[TMP71]], align 8 +// SEGMENTED-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS13]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr [[D_SCAN_STORAGE2]], ptr [[TMP72]], align 8 +// SEGMENTED-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS14]], i64 0, i64 7 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP73]], align 8 +// SEGMENTED-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 8 +// SEGMENTED-NEXT: store ptr [[D_SEGMENT_VALS3]], ptr [[TMP74]], align 8 +// SEGMENTED-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS13]], i32 0, i32 8 +// SEGMENTED-NEXT: store ptr [[D_SEGMENT_VALS3]], ptr [[TMP75]], align 8 +// SEGMENTED-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS14]], i64 0, i64 8 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP76]], align 8 +// SEGMENTED-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 +// SEGMENTED-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 +// SEGMENTED-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 0 +// SEGMENTED-NEXT: store i32 3, ptr [[TMP79]], align 4 +// SEGMENTED-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 1 +// SEGMENTED-NEXT: store i32 9, ptr [[TMP80]], align 4 +// SEGMENTED-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[TMP77]], ptr [[TMP81]], align 8 +// SEGMENTED-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 3 +// SEGMENTED-NEXT: store ptr [[TMP78]], ptr [[TMP82]], align 8 +// SEGMENTED-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr @.offload_sizes.1, ptr [[TMP83]], align 8 +// SEGMENTED-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP84]], align 8 +// SEGMENTED-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP85]], align 8 +// SEGMENTED-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP86]], align 8 +// SEGMENTED-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 8 +// SEGMENTED-NEXT: store i64 64000, ptr [[TMP87]], align 8 +// SEGMENTED-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 9 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP88]], align 8 +// SEGMENTED-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 10 +// SEGMENTED-NEXT: store [3 x i32] [i32 250, i32 0, i32 0], ptr [[TMP89]], align 4 +// SEGMENTED-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11 +// SEGMENTED-NEXT: store [3 x i32] [i32 256, i32 0, i32 0], ptr [[TMP90]], align 4 +// SEGMENTED-NEXT: [[TMP91:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 12 +// SEGMENTED-NEXT: store i32 0, ptr [[TMP91]], align 4 +// SEGMENTED-NEXT: [[TMP92:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 250, i32 256, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14_1.region_id, ptr [[KERNEL_ARGS16]]) +// SEGMENTED-NEXT: [[TMP93:%.*]] = icmp ne i32 [[TMP92]], 0 +// SEGMENTED-NEXT: br i1 [[TMP93]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] +// SEGMENTED: omp_offload.failed17: +// SEGMENTED-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14_1(ptr [[SUM1]], ptr [[IN]], ptr [[OUT1]], i64 0, ptr [[VLA]], ptr [[D_TEAM_VALS6]], ptr [[D_TEAMS_DONE_PTR7]], ptr [[D_SCAN_STORAGE8]], ptr [[D_SEGMENT_VALS9]]) #[[ATTR3]] +// SEGMENTED-NEXT: br label [[OMP_OFFLOAD_CONT18]] +// SEGMENTED: omp_offload.cont18: +// SEGMENTED-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS1]], i32 [[DEFAULT_DEV10]]) +// SEGMENTED-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR4]], i32 [[DEFAULT_DEV10]]) +// SEGMENTED-NEXT: call void @omp_target_free(ptr [[D_SCAN_STORAGE2]], i32 [[DEFAULT_DEV10]]) +// SEGMENTED-NEXT: call void @omp_target_free(ptr [[D_SEGMENT_VALS3]], i32 [[DEFAULT_DEV10]]) +// SEGMENTED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA]], i64 -1 +// SEGMENTED-NEXT: [[TMP94:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP94]], ptr [[SUM1]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[SUM2]], align 4 +// SEGMENTED-NEXT: [[VLA21:%.*]] = alloca i32, i64 0, align 16 +// SEGMENTED-NEXT: [[D_TEAM_VALS22:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAM_VALS22]], align 4 +// SEGMENTED-NEXT: [[D_TEAMS_DONE_PTR23:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR23]], align 4 +// SEGMENTED-NEXT: [[D_SCAN_STORAGE24:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SCAN_STORAGE24]], align 4 +// SEGMENTED-NEXT: [[D_SEGMENT_VALS25:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SEGMENT_VALS25]], align 4 +// SEGMENTED-NEXT: [[DEFAULT_DEV26:%.*]] = call i32 @omp_get_default_device() +// SEGMENTED-NEXT: [[INITIAL_DEVID27:%.*]] = call i32 @omp_get_initial_device() +// SEGMENTED-NEXT: [[D_TEAM_VALS28:%.*]] = call ptr @omp_target_alloc(i64 1000, i32 [[DEFAULT_DEV26]]) +// SEGMENTED-NEXT: [[D_SCAN_STORAGE29:%.*]] = call ptr @omp_target_alloc(i64 512004, i32 [[DEFAULT_DEV26]]) +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_LB30]], align 4 +// SEGMENTED-NEXT: store i32 63999, ptr [[DOTOMP_UB31]], align 4 +// SEGMENTED-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTOMP_LB30]], align 4 +// SEGMENTED-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTOMP_UB31]], align 4 +// SEGMENTED-NEXT: [[TMP97:%.*]] = sub i32 [[TMP96]], [[TMP95]] +// SEGMENTED-NEXT: [[SEGMENT_VALS_SIZE32:%.*]] = add i32 [[TMP97]], 1 +// SEGMENTED-NEXT: [[TMP98:%.*]] = zext i32 [[SEGMENT_VALS_SIZE32]] to i64 +// SEGMENTED-NEXT: [[D_SEGMENT_VALS_SZ33:%.*]] = mul i64 4, [[TMP98]] +// SEGMENTED-NEXT: [[D_SEGMENT_VALS34:%.*]] = call ptr @omp_target_alloc(i64 [[D_SEGMENT_VALS_SZ33]], i32 [[DEFAULT_DEV26]]) +// SEGMENTED-NEXT: store i32 0, ptr [[D_TEAMS_DONE_PTR23]], align 4 +// SEGMENTED-NEXT: [[D_TEAMS_DONE_PTR35:%.*]] = call ptr @omp_target_alloc(i64 4, i32 [[DEFAULT_DEV26]]) +// SEGMENTED-NEXT: [[TMP99:%.*]] = call i32 @omp_target_memcpy(ptr [[D_TEAMS_DONE_PTR35]], ptr [[D_TEAMS_DONE_PTR23]], i64 4, i64 0, i64 0, i32 [[DEFAULT_DEV26]], i32 [[INITIAL_DEVID27]]) +// SEGMENTED-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 +// SEGMENTED-NEXT: store ptr [[OUT2]], ptr [[TMP100]], align 8 +// SEGMENTED-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 +// SEGMENTED-NEXT: store ptr [[OUT2]], ptr [[TMP101]], align 8 +// SEGMENTED-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 0 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP102]], align 8 +// SEGMENTED-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 1 +// SEGMENTED-NEXT: store ptr [[SUM2]], ptr [[TMP103]], align 8 +// SEGMENTED-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS37]], i32 0, i32 1 +// SEGMENTED-NEXT: store ptr [[SUM2]], ptr [[TMP104]], align 8 +// SEGMENTED-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 1 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP105]], align 8 +// SEGMENTED-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[TMP106]], align 8 +// SEGMENTED-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS37]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[TMP107]], align 8 +// SEGMENTED-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 2 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP108]], align 8 +// SEGMENTED-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 3 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP109]], align 8 +// SEGMENTED-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS37]], i32 0, i32 3 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP110]], align 8 +// SEGMENTED-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 3 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP111]], align 8 +// SEGMENTED-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr [[VLA21]], ptr [[TMP112]], align 8 +// SEGMENTED-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS37]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr [[VLA21]], ptr [[TMP113]], align 8 +// SEGMENTED-NEXT: [[TMP114:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 4 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP114]], align 8 +// SEGMENTED-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr [[D_TEAM_VALS28]], ptr [[TMP115]], align 8 +// SEGMENTED-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS37]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr [[D_TEAM_VALS28]], ptr [[TMP116]], align 8 +// SEGMENTED-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 5 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP117]], align 8 +// SEGMENTED-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr [[D_TEAMS_DONE_PTR35]], ptr [[TMP118]], align 8 +// SEGMENTED-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS37]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr [[D_TEAMS_DONE_PTR35]], ptr [[TMP119]], align 8 +// SEGMENTED-NEXT: [[TMP120:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 6 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP120]], align 8 +// SEGMENTED-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr [[D_SCAN_STORAGE29]], ptr [[TMP121]], align 8 +// SEGMENTED-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS37]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr [[D_SCAN_STORAGE29]], ptr [[TMP122]], align 8 +// SEGMENTED-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 7 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP123]], align 8 +// SEGMENTED-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 8 +// SEGMENTED-NEXT: store ptr [[D_SEGMENT_VALS34]], ptr [[TMP124]], align 8 +// SEGMENTED-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS37]], i32 0, i32 8 +// SEGMENTED-NEXT: store ptr [[D_SEGMENT_VALS34]], ptr [[TMP125]], align 8 +// SEGMENTED-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS38]], i64 0, i64 8 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP126]], align 8 +// SEGMENTED-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 +// SEGMENTED-NEXT: [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 +// SEGMENTED-NEXT: [[TMP129:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 0 +// SEGMENTED-NEXT: store i32 3, ptr [[TMP129]], align 4 +// SEGMENTED-NEXT: [[TMP130:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 1 +// SEGMENTED-NEXT: store i32 9, ptr [[TMP130]], align 4 +// SEGMENTED-NEXT: [[TMP131:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[TMP127]], ptr [[TMP131]], align 8 +// SEGMENTED-NEXT: [[TMP132:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 3 +// SEGMENTED-NEXT: store ptr [[TMP128]], ptr [[TMP132]], align 8 +// SEGMENTED-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr @.offload_sizes.3, ptr [[TMP133]], align 8 +// SEGMENTED-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP134]], align 8 +// SEGMENTED-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP135]], align 8 +// SEGMENTED-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP136]], align 8 +// SEGMENTED-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 8 +// SEGMENTED-NEXT: store i64 64000, ptr [[TMP137]], align 8 +// SEGMENTED-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 9 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP138]], align 8 +// SEGMENTED-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 10 +// SEGMENTED-NEXT: store [3 x i32] [i32 250, i32 0, i32 0], ptr [[TMP139]], align 4 +// SEGMENTED-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 11 +// SEGMENTED-NEXT: store [3 x i32] [i32 256, i32 0, i32 0], ptr [[TMP140]], align 4 +// SEGMENTED-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS40]], i32 0, i32 12 +// SEGMENTED-NEXT: store i32 0, ptr [[TMP141]], align 4 +// SEGMENTED-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 250, i32 256, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24.region_id, ptr [[KERNEL_ARGS40]]) +// SEGMENTED-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0 +// SEGMENTED-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED41:%.*]], label [[OMP_OFFLOAD_CONT42:%.*]] +// SEGMENTED: omp_offload.failed41: +// SEGMENTED-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24(ptr [[OUT2]], ptr [[SUM2]], ptr [[IN]], i64 0, ptr [[VLA21]], ptr [[D_TEAM_VALS22]], ptr [[D_TEAMS_DONE_PTR23]], ptr [[D_SCAN_STORAGE24]], ptr [[D_SEGMENT_VALS25]]) #[[ATTR3]] +// SEGMENTED-NEXT: br label [[OMP_OFFLOAD_CONT42]] +// SEGMENTED: omp_offload.cont42: +// SEGMENTED-NEXT: [[D_TEAM_VALS43:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAM_VALS43]], align 4 +// SEGMENTED-NEXT: [[D_TEAMS_DONE_PTR44:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR44]], align 4 +// SEGMENTED-NEXT: [[D_SCAN_STORAGE45:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SCAN_STORAGE45]], align 4 +// SEGMENTED-NEXT: [[D_SEGMENT_VALS46:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SEGMENT_VALS46]], align 4 +// SEGMENTED-NEXT: [[DEFAULT_DEV47:%.*]] = call i32 @omp_get_default_device() +// SEGMENTED-NEXT: [[INITIAL_DEVID48:%.*]] = call i32 @omp_get_initial_device() +// SEGMENTED-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 0 +// SEGMENTED-NEXT: store ptr [[OUT2]], ptr [[TMP144]], align 8 +// SEGMENTED-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS50]], i32 0, i32 0 +// SEGMENTED-NEXT: store ptr [[OUT2]], ptr [[TMP145]], align 8 +// SEGMENTED-NEXT: [[TMP146:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS51]], i64 0, i64 0 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP146]], align 8 +// SEGMENTED-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 1 +// SEGMENTED-NEXT: store ptr [[SUM2]], ptr [[TMP147]], align 8 +// SEGMENTED-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS50]], i32 0, i32 1 +// SEGMENTED-NEXT: store ptr [[SUM2]], ptr [[TMP148]], align 8 +// SEGMENTED-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS51]], i64 0, i64 1 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP149]], align 8 +// SEGMENTED-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[TMP150]], align 8 +// SEGMENTED-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS50]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[TMP151]], align 8 +// SEGMENTED-NEXT: [[TMP152:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS51]], i64 0, i64 2 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP152]], align 8 +// SEGMENTED-NEXT: [[TMP153:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 3 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP153]], align 8 +// SEGMENTED-NEXT: [[TMP154:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS50]], i32 0, i32 3 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP154]], align 8 +// SEGMENTED-NEXT: [[TMP155:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS51]], i64 0, i64 3 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP155]], align 8 +// SEGMENTED-NEXT: [[TMP156:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr [[VLA21]], ptr [[TMP156]], align 8 +// SEGMENTED-NEXT: [[TMP157:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS50]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr [[VLA21]], ptr [[TMP157]], align 8 +// SEGMENTED-NEXT: [[TMP158:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS51]], i64 0, i64 4 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP158]], align 8 +// SEGMENTED-NEXT: [[TMP159:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr [[D_TEAM_VALS28]], ptr [[TMP159]], align 8 +// SEGMENTED-NEXT: [[TMP160:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS50]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr [[D_TEAM_VALS28]], ptr [[TMP160]], align 8 +// SEGMENTED-NEXT: [[TMP161:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS51]], i64 0, i64 5 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP161]], align 8 +// SEGMENTED-NEXT: [[TMP162:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr [[D_TEAMS_DONE_PTR35]], ptr [[TMP162]], align 8 +// SEGMENTED-NEXT: [[TMP163:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS50]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr [[D_TEAMS_DONE_PTR35]], ptr [[TMP163]], align 8 +// SEGMENTED-NEXT: [[TMP164:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS51]], i64 0, i64 6 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP164]], align 8 +// SEGMENTED-NEXT: [[TMP165:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr [[D_SCAN_STORAGE29]], ptr [[TMP165]], align 8 +// SEGMENTED-NEXT: [[TMP166:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS50]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr [[D_SCAN_STORAGE29]], ptr [[TMP166]], align 8 +// SEGMENTED-NEXT: [[TMP167:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS51]], i64 0, i64 7 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP167]], align 8 +// SEGMENTED-NEXT: [[TMP168:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 8 +// SEGMENTED-NEXT: store ptr [[D_SEGMENT_VALS34]], ptr [[TMP168]], align 8 +// SEGMENTED-NEXT: [[TMP169:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS50]], i32 0, i32 8 +// SEGMENTED-NEXT: store ptr [[D_SEGMENT_VALS34]], ptr [[TMP169]], align 8 +// SEGMENTED-NEXT: [[TMP170:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS51]], i64 0, i64 8 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP170]], align 8 +// SEGMENTED-NEXT: [[TMP171:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS49]], i32 0, i32 0 +// SEGMENTED-NEXT: [[TMP172:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS50]], i32 0, i32 0 +// SEGMENTED-NEXT: [[TMP173:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 0 +// SEGMENTED-NEXT: store i32 3, ptr [[TMP173]], align 4 +// SEGMENTED-NEXT: [[TMP174:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 1 +// SEGMENTED-NEXT: store i32 9, ptr [[TMP174]], align 4 +// SEGMENTED-NEXT: [[TMP175:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 2 +// SEGMENTED-NEXT: store ptr [[TMP171]], ptr [[TMP175]], align 8 +// SEGMENTED-NEXT: [[TMP176:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 3 +// SEGMENTED-NEXT: store ptr [[TMP172]], ptr [[TMP176]], align 8 +// SEGMENTED-NEXT: [[TMP177:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 4 +// SEGMENTED-NEXT: store ptr @.offload_sizes.5, ptr [[TMP177]], align 8 +// SEGMENTED-NEXT: [[TMP178:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 5 +// SEGMENTED-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP178]], align 8 +// SEGMENTED-NEXT: [[TMP179:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 6 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP179]], align 8 +// SEGMENTED-NEXT: [[TMP180:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 7 +// SEGMENTED-NEXT: store ptr null, ptr [[TMP180]], align 8 +// SEGMENTED-NEXT: [[TMP181:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 8 +// SEGMENTED-NEXT: store i64 64000, ptr [[TMP181]], align 8 +// SEGMENTED-NEXT: [[TMP182:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 9 +// SEGMENTED-NEXT: store i64 0, ptr [[TMP182]], align 8 +// SEGMENTED-NEXT: [[TMP183:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 10 +// SEGMENTED-NEXT: store [3 x i32] [i32 250, i32 0, i32 0], ptr [[TMP183]], align 4 +// SEGMENTED-NEXT: [[TMP184:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 11 +// SEGMENTED-NEXT: store [3 x i32] [i32 256, i32 0, i32 0], ptr [[TMP184]], align 4 +// SEGMENTED-NEXT: [[TMP185:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS53]], i32 0, i32 12 +// SEGMENTED-NEXT: store i32 0, ptr [[TMP185]], align 4 +// SEGMENTED-NEXT: [[TMP186:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 250, i32 256, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_1.region_id, ptr [[KERNEL_ARGS53]]) +// SEGMENTED-NEXT: [[TMP187:%.*]] = icmp ne i32 [[TMP186]], 0 +// SEGMENTED-NEXT: br i1 [[TMP187]], label [[OMP_OFFLOAD_FAILED54:%.*]], label [[OMP_OFFLOAD_CONT55:%.*]] +// SEGMENTED: omp_offload.failed54: +// SEGMENTED-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_1(ptr [[OUT2]], ptr [[SUM2]], ptr [[IN]], i64 0, ptr [[VLA21]], ptr [[D_TEAM_VALS43]], ptr [[D_TEAMS_DONE_PTR44]], ptr [[D_SCAN_STORAGE45]], ptr [[D_SEGMENT_VALS46]]) #[[ATTR3]] +// SEGMENTED-NEXT: br label [[OMP_OFFLOAD_CONT55]] +// SEGMENTED: omp_offload.cont55: +// SEGMENTED-NEXT: call void @omp_target_free(ptr [[D_TEAM_VALS28]], i32 [[DEFAULT_DEV47]]) +// SEGMENTED-NEXT: call void @omp_target_free(ptr [[D_TEAMS_DONE_PTR35]], i32 [[DEFAULT_DEV47]]) +// SEGMENTED-NEXT: call void @omp_target_free(ptr [[D_SCAN_STORAGE29]], i32 [[DEFAULT_DEV47]]) +// SEGMENTED-NEXT: call void @omp_target_free(ptr [[D_SEGMENT_VALS34]], i32 [[DEFAULT_DEV47]]) +// SEGMENTED-NEXT: [[ARRAYIDX57:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA21]], i64 -1 +// SEGMENTED-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARRAYIDX57]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP188]], ptr [[SUM2]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SEGMENTED-NEXT: [[TMP189:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// SEGMENTED-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP189]]) +// SEGMENTED-NEXT: [[TMP190:%.*]] = load i32, ptr [[RETVAL]], align 4 +// SEGMENTED-NEXT: ret i32 [[TMP190]] +// +// +// SEGMENTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 +// SEGMENTED-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT1:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM11:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR2:[0-9]+]] { +// SEGMENTED-NEXT: entry: +// SEGMENTED-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[OUT1_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[SUM1_ADDR2:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[_TMP6:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB4]]) +// SEGMENTED-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[OUT1]], ptr [[OUT1_ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM11]], ptr [[SUM1_ADDR2]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5]], align 8 +// SEGMENTED-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM1_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP6:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OUT1_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP8:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP9:%.*]] = load ptr, ptr [[SUM1_ADDR2]], align 8 +// SEGMENTED-NEXT: [[TMP_VLA:%.*]] = alloca i32, i64 64000, align 4 +// SEGMENTED-NEXT: store ptr [[TMP_VLA]], ptr [[TMP9]], align 16 +// SEGMENTED-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP4]], i32 250, i32 0) +// SEGMENTED-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// SEGMENTED-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// SEGMENTED-NEXT: [[D_SCAN_STORAGE:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SCAN_STORAGE]], align 4 +// SEGMENTED-NEXT: [[D_SEGMENT_VALS:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SEGMENT_VALS]], align 4 +// SEGMENTED-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.omp_outlined, ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP8]], ptr [[TMP9]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]], ptr [[D_SCAN_STORAGE]], ptr [[D_SEGMENT_VALS]]) +// SEGMENTED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP9]], i64 63999 +// SEGMENTED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP10]], ptr [[TMP5]], align 4 +// SEGMENTED-NEXT: ret void +// +// +// SEGMENTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.omp_outlined +// SEGMENTED-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT1:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM11:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR2]] { +// SEGMENTED-NEXT: entry: +// SEGMENTED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[OUT1_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[SUM1_ADDR2:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[I:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[OUT1]], ptr [[OUT1_ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM11]], ptr [[SUM1_ADDR2]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5]], align 8 +// SEGMENTED-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM1_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP5:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OUT1_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP7:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP8:%.*]] = load ptr, ptr [[SUM1_ADDR2]], align 8 +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// SEGMENTED-NEXT: store i32 63999, ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// SEGMENTED-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// SEGMENTED-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// SEGMENTED-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 63999 +// SEGMENTED-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// SEGMENTED: cond.true: +// SEGMENTED-NEXT: br label [[COND_END:%.*]] +// SEGMENTED: cond.false: +// SEGMENTED-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: br label [[COND_END]] +// SEGMENTED: cond.end: +// SEGMENTED-NEXT: [[COND:%.*]] = phi i32 [ 63999, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// SEGMENTED-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// SEGMENTED: omp.inner.for.cond: +// SEGMENTED-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// SEGMENTED-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// SEGMENTED: omp.inner.for.body: +// SEGMENTED-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB4]], i32 [[TMP10]], i32 256) +// SEGMENTED-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// SEGMENTED-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// SEGMENTED-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// SEGMENTED-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// SEGMENTED-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// SEGMENTED-NEXT: [[D_SCAN_STORAGE:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SCAN_STORAGE]], align 4 +// SEGMENTED-NEXT: [[D_SEGMENT_VALS:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SEGMENT_VALS]], align 4 +// SEGMENTED-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 11, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.omp_outlined.omp_outlined, i64 [[TMP17]], i64 [[TMP19]], ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], i64 [[TMP7]], ptr [[TMP8]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]], ptr [[D_SCAN_STORAGE]], ptr [[D_SEGMENT_VALS]]) +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// SEGMENTED: omp.inner.for.inc: +// SEGMENTED-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// SEGMENTED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// SEGMENTED-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND]] +// SEGMENTED: omp.inner.for.end: +// SEGMENTED-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// SEGMENTED: omp.loop.exit: +// SEGMENTED-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) +// SEGMENTED-NEXT: ret void +// +// +// SEGMENTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.omp_outlined.omp_outlined +// SEGMENTED-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT1:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM11:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR2]] { +// SEGMENTED-NEXT: entry: +// SEGMENTED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[OUT1_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[SUM1_ADDR2:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[_TMP6:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[I:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[SUM18:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_IV17:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[_TMP18:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_LB19:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_UB20:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_STRIDE21:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_IS_LAST22:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[I23:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[SUM134:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[OUT1]], ptr [[OUT1_ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM11]], ptr [[SUM1_ADDR2]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5]], align 8 +// SEGMENTED-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM1_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP5:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OUT1_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP7:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP8:%.*]] = load ptr, ptr [[SUM1_ADDR2]], align 8 +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// SEGMENTED-NEXT: store i32 63999, ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// SEGMENTED-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// SEGMENTED-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// SEGMENTED-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 63999 +// SEGMENTED-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// SEGMENTED: cond.true: +// SEGMENTED-NEXT: br label [[COND_END:%.*]] +// SEGMENTED: cond.false: +// SEGMENTED-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: br label [[COND_END]] +// SEGMENTED: cond.end: +// SEGMENTED-NEXT: [[COND:%.*]] = phi i32 [ 63999, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// SEGMENTED-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// SEGMENTED: omp.inner.for.cond: +// SEGMENTED-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// SEGMENTED-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// SEGMENTED: omp.inner.for.body: +// SEGMENTED-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// SEGMENTED-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// SEGMENTED-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[SUM18]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// SEGMENTED: omp.before.scan.bb: +// SEGMENTED-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 +// SEGMENTED-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP5]], i64 0, i64 [[IDXPROM]] +// SEGMENTED-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// SEGMENTED-NEXT: [[TMP19:%.*]] = load i32, ptr [[SUM18]], align 4 +// SEGMENTED-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[TMP18]] +// SEGMENTED-NEXT: store i32 [[ADD9]], ptr [[SUM18]], align 4 +// SEGMENTED-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 [[TMP21]] +// SEGMENTED-NEXT: [[TMP22:%.*]] = load i32, ptr [[SUM18]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX10]], align 4 +// SEGMENTED-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// SEGMENTED: omp.exit.inscan.bb: +// SEGMENTED-NEXT: br label [[OMP_BODY_CONTINUE]] +// SEGMENTED: omp.inscan.dispatch: +// SEGMENTED-NEXT: br label [[OMP_BEFORE_SCAN_BB:%.*]] +// SEGMENTED: omp.after.scan.bb: +// SEGMENTED-NEXT: [[TMP23:%.*]] = load i32, ptr [[SUM18]], align 4 +// SEGMENTED-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4 +// SEGMENTED-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP24]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP6]], i64 0, i64 [[IDXPROM11]] +// SEGMENTED-NEXT: store i32 [[TMP23]], ptr [[ARRAYIDX12]], align 4 +// SEGMENTED-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// SEGMENTED: omp.body.continue: +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// SEGMENTED: omp.inner.for.inc: +// SEGMENTED-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP25]], 1 +// SEGMENTED-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND]] +// SEGMENTED: omp.inner.for.end: +// SEGMENTED-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// SEGMENTED: omp.loop.exit: +// SEGMENTED-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP10]]) +// SEGMENTED-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP10]]) +// SEGMENTED-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB4]], i32 [[TMP10]]) +// SEGMENTED-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 +// SEGMENTED-NEXT: br i1 [[TMP27]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// SEGMENTED: omp_if.then: +// SEGMENTED-NEXT: [[TMP28:%.*]] = call double @llvm.log2.f64(double 6.400000e+04) #[[ATTR3]] +// SEGMENTED-NEXT: [[TMP29:%.*]] = call double @llvm.ceil.f64(double [[TMP28]]) #[[ATTR3]] +// SEGMENTED-NEXT: [[TMP30:%.*]] = fptoui double [[TMP29]] to i32 +// SEGMENTED-NEXT: br label [[OMP_OUTER_LOG_SCAN_BODY:%.*]] +// SEGMENTED: omp.outer.log.scan.body: +// SEGMENTED-NEXT: [[TMP31:%.*]] = phi i32 [ 0, [[OMP_IF_THEN]] ], [ [[TMP40:%.*]], [[OMP_INNER_LOG_SCAN_EXIT:%.*]] ] +// SEGMENTED-NEXT: [[TMP32:%.*]] = phi i64 [ 1, [[OMP_IF_THEN]] ], [ [[TMP41:%.*]], [[OMP_INNER_LOG_SCAN_EXIT]] ] +// SEGMENTED-NEXT: [[TMP33:%.*]] = icmp uge i64 63999, [[TMP32]] +// SEGMENTED-NEXT: br i1 [[TMP33]], label [[OMP_INNER_LOG_SCAN_BODY:%.*]], label [[OMP_INNER_LOG_SCAN_EXIT]] +// SEGMENTED: omp.inner.log.scan.body: +// SEGMENTED-NEXT: [[TMP34:%.*]] = phi i64 [ 63999, [[OMP_OUTER_LOG_SCAN_BODY]] ], [ [[TMP38:%.*]], [[OMP_INNER_LOG_SCAN_BODY]] ] +// SEGMENTED-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 [[TMP34]] +// SEGMENTED-NEXT: [[TMP35:%.*]] = sub nuw i64 [[TMP34]], [[TMP32]] +// SEGMENTED-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 [[TMP35]] +// SEGMENTED-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4 +// SEGMENTED-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARRAYIDX15]], align 4 +// SEGMENTED-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP36]], [[TMP37]] +// SEGMENTED-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX14]], align 4 +// SEGMENTED-NEXT: [[TMP38]] = sub nuw i64 [[TMP34]], 1 +// SEGMENTED-NEXT: [[TMP39:%.*]] = icmp uge i64 [[TMP38]], [[TMP32]] +// SEGMENTED-NEXT: br i1 [[TMP39]], label [[OMP_INNER_LOG_SCAN_BODY]], label [[OMP_INNER_LOG_SCAN_EXIT]] +// SEGMENTED: omp.inner.log.scan.exit: +// SEGMENTED-NEXT: [[TMP40]] = add nuw i32 [[TMP31]], 1 +// SEGMENTED-NEXT: [[TMP41]] = shl nuw i64 [[TMP32]], 1 +// SEGMENTED-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP40]], [[TMP30]] +// SEGMENTED-NEXT: br i1 [[TMP42]], label [[OMP_OUTER_LOG_SCAN_BODY]], label [[OMP_OUTER_LOG_SCAN_EXIT:%.*]] +// SEGMENTED: omp.outer.log.scan.exit: +// SEGMENTED-NEXT: call void @__kmpc_end_master(ptr @[[GLOB4]], i32 [[TMP10]]) +// SEGMENTED-NEXT: br label [[OMP_IF_END]] +// SEGMENTED: omp_if.end: +// SEGMENTED-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP10]]) +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_LB19]], align 4 +// SEGMENTED-NEXT: store i32 63999, ptr [[DOTOMP_UB20]], align 4 +// SEGMENTED-NEXT: store i32 1, ptr [[DOTOMP_STRIDE21]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST22]], align 4 +// SEGMENTED-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP10]], i32 34, ptr [[DOTOMP_IS_LAST22]], ptr [[DOTOMP_LB19]], ptr [[DOTOMP_UB20]], ptr [[DOTOMP_STRIDE21]], i32 1, i32 1) +// SEGMENTED-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_UB20]], align 4 +// SEGMENTED-NEXT: [[CMP24:%.*]] = icmp sgt i32 [[TMP43]], 63999 +// SEGMENTED-NEXT: br i1 [[CMP24]], label [[COND_TRUE25:%.*]], label [[COND_FALSE26:%.*]] +// SEGMENTED: cond.true25: +// SEGMENTED-NEXT: br label [[COND_END27:%.*]] +// SEGMENTED: cond.false26: +// SEGMENTED-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_UB20]], align 4 +// SEGMENTED-NEXT: br label [[COND_END27]] +// SEGMENTED: cond.end27: +// SEGMENTED-NEXT: [[COND28:%.*]] = phi i32 [ 63999, [[COND_TRUE25]] ], [ [[TMP44]], [[COND_FALSE26]] ] +// SEGMENTED-NEXT: store i32 [[COND28]], ptr [[DOTOMP_UB20]], align 4 +// SEGMENTED-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_LB19]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP45]], ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] +// SEGMENTED: omp.inner.for.cond29: +// SEGMENTED-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_UB20]], align 4 +// SEGMENTED-NEXT: [[CMP30:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] +// SEGMENTED-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] +// SEGMENTED: omp.inner.for.body31: +// SEGMENTED-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: [[MUL32:%.*]] = mul nsw i32 [[TMP48]], 1 +// SEGMENTED-NEXT: [[ADD33:%.*]] = add nsw i32 0, [[MUL32]] +// SEGMENTED-NEXT: store i32 [[ADD33]], ptr [[I23]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[SUM134]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INSCAN_DISPATCH40:%.*]] +// SEGMENTED: omp.before.scan.bb35: +// SEGMENTED-NEXT: [[TMP49:%.*]] = load i32, ptr [[I23]], align 4 +// SEGMENTED-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP49]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP5]], i64 0, i64 [[IDXPROM36]] +// SEGMENTED-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARRAYIDX37]], align 4 +// SEGMENTED-NEXT: [[TMP51:%.*]] = load i32, ptr [[SUM134]], align 4 +// SEGMENTED-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP51]], [[TMP50]] +// SEGMENTED-NEXT: store i32 [[ADD38]], ptr [[SUM134]], align 4 +// SEGMENTED-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] +// SEGMENTED: omp.exit.inscan.bb39: +// SEGMENTED-NEXT: br label [[OMP_BODY_CONTINUE45]] +// SEGMENTED: omp.inscan.dispatch40: +// SEGMENTED-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: [[TMP53:%.*]] = zext i32 [[TMP52]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 [[TMP53]] +// SEGMENTED-NEXT: [[TMP54:%.*]] = load i32, ptr [[ARRAYIDX41]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP54]], ptr [[SUM134]], align 4 +// SEGMENTED-NEXT: br label [[OMP_AFTER_SCAN_BB42:%.*]] +// SEGMENTED: omp.after.scan.bb42: +// SEGMENTED-NEXT: [[TMP55:%.*]] = load i32, ptr [[SUM134]], align 4 +// SEGMENTED-NEXT: [[TMP56:%.*]] = load i32, ptr [[I23]], align 4 +// SEGMENTED-NEXT: [[IDXPROM43:%.*]] = sext i32 [[TMP56]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP6]], i64 0, i64 [[IDXPROM43]] +// SEGMENTED-NEXT: store i32 [[TMP55]], ptr [[ARRAYIDX44]], align 4 +// SEGMENTED-NEXT: br label [[OMP_EXIT_INSCAN_BB39:%.*]] +// SEGMENTED: omp.body.continue45: +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] +// SEGMENTED: omp.inner.for.inc46: +// SEGMENTED-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: [[ADD47:%.*]] = add nsw i32 [[TMP57]], 1 +// SEGMENTED-NEXT: store i32 [[ADD47]], ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND29]] +// SEGMENTED: omp.inner.for.end48: +// SEGMENTED-NEXT: br label [[OMP_LOOP_EXIT49:%.*]] +// SEGMENTED: omp.loop.exit49: +// SEGMENTED-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP10]]) +// SEGMENTED-NEXT: ret void +// +// +// SEGMENTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14_1 +// SEGMENTED-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[SUM1:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT1:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM11:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR2]] { +// SEGMENTED-NEXT: entry: +// SEGMENTED-NEXT: [[SUM1_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[OUT1_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[SUM1_ADDR2:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: store ptr [[SUM1]], ptr [[SUM1_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[OUT1]], ptr [[OUT1_ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM11]], ptr [[SUM1_ADDR2]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5]], align 8 +// SEGMENTED-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SUM1_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP5:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OUT1_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP7:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP8:%.*]] = load ptr, ptr [[SUM1_ADDR2]], align 8 +// SEGMENTED-NEXT: ret void +// +// +// SEGMENTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 +// SEGMENTED-SAME: (ptr noundef nonnull align 4 dereferenceable(256000) [[OUT2:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM2:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM21:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR2]] { +// SEGMENTED-NEXT: entry: +// SEGMENTED-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[SUM2_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[SUM2_ADDR2:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[_TMP6:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB4]]) +// SEGMENTED-NEXT: store ptr [[OUT2]], ptr [[OUT2_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM2]], ptr [[SUM2_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM21]], ptr [[SUM2_ADDR2]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5]], align 8 +// SEGMENTED-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OUT2_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP6:%.*]] = load ptr, ptr [[SUM2_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP7:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP8:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP9:%.*]] = load ptr, ptr [[SUM2_ADDR2]], align 8 +// SEGMENTED-NEXT: [[TMP_VLA:%.*]] = alloca i32, i64 64000, align 4 +// SEGMENTED-NEXT: store ptr [[TMP_VLA]], ptr [[TMP9]], align 16 +// SEGMENTED-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP4]], i32 250, i32 0) +// SEGMENTED-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// SEGMENTED-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// SEGMENTED-NEXT: [[D_SCAN_STORAGE:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SCAN_STORAGE]], align 4 +// SEGMENTED-NEXT: [[D_SEGMENT_VALS:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SEGMENT_VALS]], align 4 +// SEGMENTED-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24.omp_outlined, ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP8]], ptr [[TMP9]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]], ptr [[D_SCAN_STORAGE]], ptr [[D_SEGMENT_VALS]]) +// SEGMENTED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP9]], i64 63999 +// SEGMENTED-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP10]], ptr [[TMP6]], align 4 +// SEGMENTED-NEXT: ret void +// +// +// SEGMENTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24.omp_outlined +// SEGMENTED-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT2:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM2:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM21:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR2]] { +// SEGMENTED-NEXT: entry: +// SEGMENTED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[SUM2_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[SUM2_ADDR2:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[I:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[OUT2]], ptr [[OUT2_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM2]], ptr [[SUM2_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM21]], ptr [[SUM2_ADDR2]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5]], align 8 +// SEGMENTED-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT2_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM2_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP6:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP7:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP8:%.*]] = load ptr, ptr [[SUM2_ADDR2]], align 8 +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// SEGMENTED-NEXT: store i32 63999, ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// SEGMENTED-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// SEGMENTED-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// SEGMENTED-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 63999 +// SEGMENTED-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// SEGMENTED: cond.true: +// SEGMENTED-NEXT: br label [[COND_END:%.*]] +// SEGMENTED: cond.false: +// SEGMENTED-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: br label [[COND_END]] +// SEGMENTED: cond.end: +// SEGMENTED-NEXT: [[COND:%.*]] = phi i32 [ 63999, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// SEGMENTED-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// SEGMENTED: omp.inner.for.cond: +// SEGMENTED-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// SEGMENTED-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// SEGMENTED: omp.inner.for.body: +// SEGMENTED-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB4]], i32 [[TMP10]], i32 256) +// SEGMENTED-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// SEGMENTED-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 +// SEGMENTED-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// SEGMENTED-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 +// SEGMENTED-NEXT: [[D_TEAM_VALS:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAM_VALS]], align 4 +// SEGMENTED-NEXT: [[D_TEAMS_DONE_PTR:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_TEAMS_DONE_PTR]], align 4 +// SEGMENTED-NEXT: [[D_SCAN_STORAGE:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SCAN_STORAGE]], align 4 +// SEGMENTED-NEXT: [[D_SEGMENT_VALS:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr null, ptr [[D_SEGMENT_VALS]], align 4 +// SEGMENTED-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 11, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24.omp_outlined.omp_outlined, i64 [[TMP17]], i64 [[TMP19]], ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], i64 [[TMP7]], ptr [[TMP8]], ptr [[D_TEAM_VALS]], ptr [[D_TEAMS_DONE_PTR]], ptr [[D_SCAN_STORAGE]], ptr [[D_SEGMENT_VALS]]) +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// SEGMENTED: omp.inner.for.inc: +// SEGMENTED-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// SEGMENTED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] +// SEGMENTED-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND]] +// SEGMENTED: omp.inner.for.end: +// SEGMENTED-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// SEGMENTED: omp.loop.exit: +// SEGMENTED-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) +// SEGMENTED-NEXT: ret void +// +// +// SEGMENTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24.omp_outlined.omp_outlined +// SEGMENTED-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[OUT2:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM2:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM21:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR2]] { +// SEGMENTED-NEXT: entry: +// SEGMENTED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[SUM2_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[SUM2_ADDR2:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[_TMP6:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[I:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[SUM28:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_IV17:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[_TMP18:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_LB19:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_UB20:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_STRIDE21:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[DOTOMP_IS_LAST22:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[I23:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: [[SUM234:%.*]] = alloca i32, align 4 +// SEGMENTED-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[OUT2]], ptr [[OUT2_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM2]], ptr [[SUM2_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM21]], ptr [[SUM2_ADDR2]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5]], align 8 +// SEGMENTED-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT2_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM2_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP6:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP7:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP8:%.*]] = load ptr, ptr [[SUM2_ADDR2]], align 8 +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// SEGMENTED-NEXT: store i32 63999, ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// SEGMENTED-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// SEGMENTED-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP10]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// SEGMENTED-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 63999 +// SEGMENTED-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// SEGMENTED: cond.true: +// SEGMENTED-NEXT: br label [[COND_END:%.*]] +// SEGMENTED: cond.false: +// SEGMENTED-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: br label [[COND_END]] +// SEGMENTED: cond.end: +// SEGMENTED-NEXT: [[COND:%.*]] = phi i32 [ 63999, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] +// SEGMENTED-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// SEGMENTED: omp.inner.for.cond: +// SEGMENTED-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// SEGMENTED-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] +// SEGMENTED-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// SEGMENTED: omp.inner.for.body: +// SEGMENTED-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 +// SEGMENTED-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// SEGMENTED-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[SUM28]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INSCAN_DISPATCH:%.*]] +// SEGMENTED: omp.before.scan.bb: +// SEGMENTED-NEXT: [[TMP17:%.*]] = load i32, ptr [[SUM28]], align 4 +// SEGMENTED-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 +// SEGMENTED-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM]] +// SEGMENTED-NEXT: store i32 [[TMP17]], ptr [[ARRAYIDX]], align 4 +// SEGMENTED-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// SEGMENTED: omp.exit.inscan.bb: +// SEGMENTED-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 [[TMP20]] +// SEGMENTED-NEXT: [[TMP21:%.*]] = load i32, ptr [[SUM28]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX9]], align 4 +// SEGMENTED-NEXT: br label [[OMP_BODY_CONTINUE]] +// SEGMENTED: omp.inscan.dispatch: +// SEGMENTED-NEXT: br label [[OMP_AFTER_SCAN_BB:%.*]] +// SEGMENTED: omp.after.scan.bb: +// SEGMENTED-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 +// SEGMENTED-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP22]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP6]], i64 0, i64 [[IDXPROM10]] +// SEGMENTED-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 +// SEGMENTED-NEXT: [[TMP24:%.*]] = load i32, ptr [[SUM28]], align 4 +// SEGMENTED-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP24]], [[TMP23]] +// SEGMENTED-NEXT: store i32 [[ADD12]], ptr [[SUM28]], align 4 +// SEGMENTED-NEXT: br label [[OMP_EXIT_INSCAN_BB:%.*]] +// SEGMENTED: omp.body.continue: +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// SEGMENTED: omp.inner.for.inc: +// SEGMENTED-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP25]], 1 +// SEGMENTED-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND]] +// SEGMENTED: omp.inner.for.end: +// SEGMENTED-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// SEGMENTED: omp.loop.exit: +// SEGMENTED-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP10]]) +// SEGMENTED-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP10]]) +// SEGMENTED-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB4]], i32 [[TMP10]]) +// SEGMENTED-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 +// SEGMENTED-NEXT: br i1 [[TMP27]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] +// SEGMENTED: omp_if.then: +// SEGMENTED-NEXT: [[TMP28:%.*]] = call double @llvm.log2.f64(double 6.400000e+04) #[[ATTR3]] +// SEGMENTED-NEXT: [[TMP29:%.*]] = call double @llvm.ceil.f64(double [[TMP28]]) #[[ATTR3]] +// SEGMENTED-NEXT: [[TMP30:%.*]] = fptoui double [[TMP29]] to i32 +// SEGMENTED-NEXT: br label [[OMP_OUTER_LOG_SCAN_BODY:%.*]] +// SEGMENTED: omp.outer.log.scan.body: +// SEGMENTED-NEXT: [[TMP31:%.*]] = phi i32 [ 0, [[OMP_IF_THEN]] ], [ [[TMP40:%.*]], [[OMP_INNER_LOG_SCAN_EXIT:%.*]] ] +// SEGMENTED-NEXT: [[TMP32:%.*]] = phi i64 [ 1, [[OMP_IF_THEN]] ], [ [[TMP41:%.*]], [[OMP_INNER_LOG_SCAN_EXIT]] ] +// SEGMENTED-NEXT: [[TMP33:%.*]] = icmp uge i64 63999, [[TMP32]] +// SEGMENTED-NEXT: br i1 [[TMP33]], label [[OMP_INNER_LOG_SCAN_BODY:%.*]], label [[OMP_INNER_LOG_SCAN_EXIT]] +// SEGMENTED: omp.inner.log.scan.body: +// SEGMENTED-NEXT: [[TMP34:%.*]] = phi i64 [ 63999, [[OMP_OUTER_LOG_SCAN_BODY]] ], [ [[TMP38:%.*]], [[OMP_INNER_LOG_SCAN_BODY]] ] +// SEGMENTED-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 [[TMP34]] +// SEGMENTED-NEXT: [[TMP35:%.*]] = sub nuw i64 [[TMP34]], [[TMP32]] +// SEGMENTED-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 [[TMP35]] +// SEGMENTED-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4 +// SEGMENTED-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARRAYIDX15]], align 4 +// SEGMENTED-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP36]], [[TMP37]] +// SEGMENTED-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX14]], align 4 +// SEGMENTED-NEXT: [[TMP38]] = sub nuw i64 [[TMP34]], 1 +// SEGMENTED-NEXT: [[TMP39:%.*]] = icmp uge i64 [[TMP38]], [[TMP32]] +// SEGMENTED-NEXT: br i1 [[TMP39]], label [[OMP_INNER_LOG_SCAN_BODY]], label [[OMP_INNER_LOG_SCAN_EXIT]] +// SEGMENTED: omp.inner.log.scan.exit: +// SEGMENTED-NEXT: [[TMP40]] = add nuw i32 [[TMP31]], 1 +// SEGMENTED-NEXT: [[TMP41]] = shl nuw i64 [[TMP32]], 1 +// SEGMENTED-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP40]], [[TMP30]] +// SEGMENTED-NEXT: br i1 [[TMP42]], label [[OMP_OUTER_LOG_SCAN_BODY]], label [[OMP_OUTER_LOG_SCAN_EXIT:%.*]] +// SEGMENTED: omp.outer.log.scan.exit: +// SEGMENTED-NEXT: call void @__kmpc_end_master(ptr @[[GLOB4]], i32 [[TMP10]]) +// SEGMENTED-NEXT: br label [[OMP_IF_END]] +// SEGMENTED: omp_if.end: +// SEGMENTED-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP10]]) +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_LB19]], align 4 +// SEGMENTED-NEXT: store i32 63999, ptr [[DOTOMP_UB20]], align 4 +// SEGMENTED-NEXT: store i32 1, ptr [[DOTOMP_STRIDE21]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST22]], align 4 +// SEGMENTED-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP10]], i32 34, ptr [[DOTOMP_IS_LAST22]], ptr [[DOTOMP_LB19]], ptr [[DOTOMP_UB20]], ptr [[DOTOMP_STRIDE21]], i32 1, i32 1) +// SEGMENTED-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_UB20]], align 4 +// SEGMENTED-NEXT: [[CMP24:%.*]] = icmp sgt i32 [[TMP43]], 63999 +// SEGMENTED-NEXT: br i1 [[CMP24]], label [[COND_TRUE25:%.*]], label [[COND_FALSE26:%.*]] +// SEGMENTED: cond.true25: +// SEGMENTED-NEXT: br label [[COND_END27:%.*]] +// SEGMENTED: cond.false26: +// SEGMENTED-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_UB20]], align 4 +// SEGMENTED-NEXT: br label [[COND_END27]] +// SEGMENTED: cond.end27: +// SEGMENTED-NEXT: [[COND28:%.*]] = phi i32 [ 63999, [[COND_TRUE25]] ], [ [[TMP44]], [[COND_FALSE26]] ] +// SEGMENTED-NEXT: store i32 [[COND28]], ptr [[DOTOMP_UB20]], align 4 +// SEGMENTED-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_LB19]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP45]], ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] +// SEGMENTED: omp.inner.for.cond29: +// SEGMENTED-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_UB20]], align 4 +// SEGMENTED-NEXT: [[CMP30:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] +// SEGMENTED-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] +// SEGMENTED: omp.inner.for.body31: +// SEGMENTED-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: [[MUL32:%.*]] = mul nsw i32 [[TMP48]], 1 +// SEGMENTED-NEXT: [[ADD33:%.*]] = add nsw i32 0, [[MUL32]] +// SEGMENTED-NEXT: store i32 [[ADD33]], ptr [[I23]], align 4 +// SEGMENTED-NEXT: store i32 0, ptr [[SUM234]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INSCAN_DISPATCH39:%.*]] +// SEGMENTED: omp.before.scan.bb35: +// SEGMENTED-NEXT: [[TMP49:%.*]] = load i32, ptr [[SUM234]], align 4 +// SEGMENTED-NEXT: [[TMP50:%.*]] = load i32, ptr [[I23]], align 4 +// SEGMENTED-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP50]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM36]] +// SEGMENTED-NEXT: store i32 [[TMP49]], ptr [[ARRAYIDX37]], align 4 +// SEGMENTED-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] +// SEGMENTED: omp.exit.inscan.bb38: +// SEGMENTED-NEXT: br label [[OMP_BODY_CONTINUE45]] +// SEGMENTED: omp.inscan.dispatch39: +// SEGMENTED-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: [[TMP52:%.*]] = zext i32 [[TMP51]] to i64 +// SEGMENTED-NEXT: [[TMP53:%.*]] = icmp eq i64 [[TMP52]], 0 +// SEGMENTED-NEXT: br i1 [[TMP53]], label [[OMP_EXCLUSIVE_COPY_EXIT:%.*]], label [[OMP_EXCLUSIVE_DEC:%.*]] +// SEGMENTED: omp.exclusive.dec: +// SEGMENTED-NEXT: [[TMP54:%.*]] = sub nuw i64 [[TMP52]], 1 +// SEGMENTED-NEXT: [[ARRAYIDX40:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 [[TMP54]] +// SEGMENTED-NEXT: [[TMP55:%.*]] = load i32, ptr [[ARRAYIDX40]], align 4 +// SEGMENTED-NEXT: store i32 [[TMP55]], ptr [[SUM234]], align 4 +// SEGMENTED-NEXT: br label [[OMP_EXCLUSIVE_COPY_EXIT]] +// SEGMENTED: omp.exclusive.copy.exit: +// SEGMENTED-NEXT: br label [[OMP_BEFORE_SCAN_BB35:%.*]] +// SEGMENTED: omp.after.scan.bb41: +// SEGMENTED-NEXT: [[TMP56:%.*]] = load i32, ptr [[I23]], align 4 +// SEGMENTED-NEXT: [[IDXPROM42:%.*]] = sext i32 [[TMP56]] to i64 +// SEGMENTED-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [64000 x i32], ptr [[TMP6]], i64 0, i64 [[IDXPROM42]] +// SEGMENTED-NEXT: [[TMP57:%.*]] = load i32, ptr [[ARRAYIDX43]], align 4 +// SEGMENTED-NEXT: [[TMP58:%.*]] = load i32, ptr [[SUM234]], align 4 +// SEGMENTED-NEXT: [[ADD44:%.*]] = add nsw i32 [[TMP58]], [[TMP57]] +// SEGMENTED-NEXT: store i32 [[ADD44]], ptr [[SUM234]], align 4 +// SEGMENTED-NEXT: br label [[OMP_EXIT_INSCAN_BB38:%.*]] +// SEGMENTED: omp.body.continue45: +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] +// SEGMENTED: omp.inner.for.inc46: +// SEGMENTED-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: [[ADD47:%.*]] = add nsw i32 [[TMP59]], 1 +// SEGMENTED-NEXT: store i32 [[ADD47]], ptr [[DOTOMP_IV17]], align 4 +// SEGMENTED-NEXT: br label [[OMP_INNER_FOR_COND29]] +// SEGMENTED: omp.inner.for.end48: +// SEGMENTED-NEXT: br label [[OMP_LOOP_EXIT49:%.*]] +// SEGMENTED: omp.loop.exit49: +// SEGMENTED-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP10]]) +// SEGMENTED-NEXT: ret void +// +// +// SEGMENTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_1 +// SEGMENTED-SAME: (ptr noundef nonnull align 4 dereferenceable(256000) [[OUT2:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM2:%.*]], ptr noundef nonnull align 4 dereferenceable(256000) [[IN:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SUM21:%.*]], ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]], ptr noundef [[TMP3:%.*]]) #[[ATTR2]] { +// SEGMENTED-NEXT: entry: +// SEGMENTED-NEXT: [[OUT2_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[SUM2_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[IN_ADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// SEGMENTED-NEXT: [[SUM2_ADDR2:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// SEGMENTED-NEXT: store ptr [[OUT2]], ptr [[OUT2_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM2]], ptr [[SUM2_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[IN]], ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[SUM21]], ptr [[SUM2_ADDR2]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP1]], ptr [[DOTADDR3]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP2]], ptr [[DOTADDR4]], align 8 +// SEGMENTED-NEXT: store ptr [[TMP3]], ptr [[DOTADDR5]], align 8 +// SEGMENTED-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT2_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SUM2_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP6:%.*]] = load ptr, ptr [[IN_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP7:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// SEGMENTED-NEXT: [[TMP8:%.*]] = load ptr, ptr [[SUM2_ADDR2]], align 8 +// SEGMENTED-NEXT: ret void +// diff --git a/clang/test/OpenMP/xteam_scan_messages.cpp b/clang/test/OpenMP/xteam_scan_messages.cpp new file mode 100644 index 0000000000000..b3ac0c422a267 --- /dev/null +++ b/clang/test/OpenMP/xteam_scan_messages.cpp @@ -0,0 +1,43 @@ +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-target-xteam-scan %s -Wuninitialized + +// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-target-xteam-scan %s -Wuninitialized + +// RUN: %clang_cc1 -verify=missing-flag,expected -fopenmp %s -Wuninitialized + +// RUN: %clang_cc1 -verify=missing-flag,expected -fopenmp-simd %s -Wuninitialized + +#define NUM_TEAMS 256 +#define NUM_THREADS 256 + +#define N NUM_THREADS * NUM_TEAMS + +int main() { + int in[N], out1[N], out2[N]; + int sum1 = 0; + int sum2 = 0; + +#pragma omp target teams distribute parallel for reduction(inscan, +:sum1,sum2) map(tofrom: in, out1) num_teams(NUM_TEAMS) num_threads(NUM_THREADS) + for(int i = 0; i < N; i++) { + sum1 += in[i]; + sum2 += 2*in[i]; + // missing-flag-error@+2 {{'scan' directive is not supported inside target regions. Use flag '-fopenmp-target-xteam-scan' to enable it}} + // expected-error@+1 {{multiple list items are not yet supported with the 'inclusive' or the 'exclusive' clauses that appear with the 'scan' directive}} + #pragma omp scan inclusive(sum1,sum2) + out1[i] = sum1; + out2[i] = sum2; + } + +#pragma omp target teams distribute parallel for reduction(inscan, +:sum1,sum2) map(tofrom: in, out1) num_teams(NUM_TEAMS) num_threads(NUM_THREADS) + for(int i = 0; i < N; i++) { + out1[i] = sum1; + out2[i] = sum2; + // missing-flag-error@+2 {{'scan' directive is not supported inside target regions. Use flag '-fopenmp-target-xteam-scan' to enable it}} + // expected-error@+1 {{multiple list items are not yet supported with the 'inclusive' or the 'exclusive' clauses that appear with the 'scan' directive}} + #pragma omp scan exclusive(sum1,sum2) + sum1 += in[i]; + sum2 += 2*in[i]; + } + + + return 0; +} diff --git a/clang/test/Preprocessor/builtin_aux_info.cpp b/clang/test/Preprocessor/builtin_aux_info.cpp deleted file mode 100644 index 60c8c6c492479..0000000000000 --- a/clang/test/Preprocessor/builtin_aux_info.cpp +++ /dev/null @@ -1,18 +0,0 @@ -// RUN: %clang_cc1 -fopenmp -triple=spirv64 -fopenmp-is-target-device \ -// RUN: -aux-triple x86_64-linux-unknown -E %s | FileCheck -implicit-check-not=BAD %s - -// RUN: %clang_cc1 -fopenmp -triple=nvptx64 -fopenmp-is-target-device \ -// RUN: -aux-triple x86_64-linux-unknown -E %s | FileCheck -implicit-check-not=BAD %s - -// RUN: %clang_cc1 -fopenmp -triple=amdgcn-amd-amdhsa -fopenmp-is-target-device \ -// RUN: -aux-triple x86_64-linux-unknown -E %s | FileCheck -implicit-check-not=BAD %s - -// RUN: %clang_cc1 -fopenmp -triple=aarch64 -fopenmp-is-target-device \ -// RUN: -aux-triple x86_64-linux-unknown -E %s | FileCheck -implicit-check-not=BAD %s - -// CHECK: GOOD -#if __has_builtin(__builtin_ia32_pause) - BAD -#else - GOOD -#endif diff --git a/clang/test/Sema/ms_predefined_expr.cpp b/clang/test/Sema/ms_predefined_expr.cpp index b42a494beef98..8c9bde7c5c757 100644 --- a/clang/test/Sema/ms_predefined_expr.cpp +++ b/clang/test/Sema/ms_predefined_expr.cpp @@ -52,8 +52,8 @@ constexpr bool equal(const T (&a)[N], const T (&b)[N]) { return true; } -#define ASSERT_EQ(X, Y) static_assert(equal(X, Y), "") -#define ASSERT_EQ_TY(X, Y) static_assert(is_same, "") +#define ASSERT_EQ(X, Y) static_assert(equal(X, Y)) +#define ASSERT_EQ_TY(X, Y) static_assert(is_same) #define _WIDE(s) L##s #define WIDE(s) _WIDE(s) @@ -159,7 +159,7 @@ constexpr size_t operator""_len(const char*, size_t len) { } void test_udliteral() { - static_assert(__FUNCTION__ ""_len == 14, ""); // expected-warning{{expansion of predefined identifier '__FUNCTION__' to a string literal is a Microsoft extension}} + static_assert(__FUNCTION__ ""_len == 14); // expected-warning{{expansion of predefined identifier '__FUNCTION__' to a string literal is a Microsoft extension}} } void test_static_assert() { diff --git a/clang/test/SemaCXX/amdgpu-wchar.cxx b/clang/test/SemaCXX/amdgpu-wchar.cxx new file mode 100644 index 0000000000000..3d5141fd49fc3 --- /dev/null +++ b/clang/test/SemaCXX/amdgpu-wchar.cxx @@ -0,0 +1,11 @@ +// RUN: %clang_cc1 -triple amdgcn -std=c++11 %s + +typedef __WINT_TYPE__ wint_t; + +#if _WIN32 +static_assert(sizeof(wchar_t)==2, "fail"); +static_assert(sizeof(wint_t)==2, "fail"); +#else +static_assert(sizeof(wchar_t)==4, "fail"); +static_assert(sizeof(wint_t)==4, "fail"); +#endif diff --git a/clang/test/SemaCXX/deprecated-copy-with-dtor.cpp b/clang/test/SemaCXX/deprecated-copy-with-dtor.cpp deleted file mode 100644 index b274d8cb3afd1..0000000000000 --- a/clang/test/SemaCXX/deprecated-copy-with-dtor.cpp +++ /dev/null @@ -1,16 +0,0 @@ -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated -verify -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated -verify -fms-compatibility -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated-copy-dtor -verify -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated-copy-dtor -verify -fms-compatibility -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated-copy-with-dtor -verify -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated-copy-with-dtor -verify -fms-compatibility - -class A { -public: - ~A() = default; // expected-warning {{definition of implicit copy constructor for 'A' is deprecated because it has a user-declared destructor}} -}; - -void test() { - A a1; - A a2 = a1; // expected-note {{in implicit copy constructor for 'A' first required here}} -} diff --git a/clang/test/SemaCXX/deprecated-copy-with-user-provided-copy.cpp b/clang/test/SemaCXX/deprecated-copy-with-user-provided-copy.cpp deleted file mode 100644 index f29d65a9ced2b..0000000000000 --- a/clang/test/SemaCXX/deprecated-copy-with-user-provided-copy.cpp +++ /dev/null @@ -1,13 +0,0 @@ -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated -verify -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated -verify -fms-compatibility -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated-copy-with-user-provided-copy -verify -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated-copy-with-user-provided-copy -verify -fms-compatibility - -struct A { - A &operator=(const A &); // expected-warning {{definition of implicit copy constructor for 'A' is deprecated because it has a user-provided copy assignment operator}} -}; - -void foo() { - A a1; - A a2(a1); // expected-note {{implicit copy constructor for 'A' first required here}} -} diff --git a/clang/test/SemaCXX/deprecated-copy-with-user-provided-dtor.cpp b/clang/test/SemaCXX/deprecated-copy-with-user-provided-dtor.cpp deleted file mode 100644 index f46e1f0961802..0000000000000 --- a/clang/test/SemaCXX/deprecated-copy-with-user-provided-dtor.cpp +++ /dev/null @@ -1,13 +0,0 @@ -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated -verify -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated -verify -fms-compatibility -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated-copy-with-user-provided-dtor -verify -// RUN: %clang_cc1 -std=c++11 %s -Wdeprecated-copy-with-user-provided-dtor -verify -fms-compatibility - -struct A { - ~A(); // expected-warning {{definition of implicit copy constructor for 'A' is deprecated because it has a user-provided destructor}} -}; - -void test() { - A a1; - A a2(a1); // expected-note {{implicit copy constructor for 'A' first required here}} -} diff --git a/clang/test/SemaCXX/uninitialized.cpp b/clang/test/SemaCXX/uninitialized.cpp index cc368c22e0776..251e888f73973 100644 --- a/clang/test/SemaCXX/uninitialized.cpp +++ b/clang/test/SemaCXX/uninitialized.cpp @@ -185,10 +185,6 @@ void test_const_ptr() { const int *ptr2; foo(ptr); // expected-warning {{variable 'ptr' is uninitialized when used here}} foobar(&ptr2); - int *ptr3; // expected-note {{initialize the variable 'ptr3' to silence this warning}} - const int *ptr4; // expected-note {{initialize the variable 'ptr4' to silence this warning}} - bar(ptr3); // expected-warning {{variable 'ptr3' is uninitialized when used here}} - bar(ptr4); // expected-warning {{variable 'ptr4' is uninitialized when used here}} } } diff --git a/clang/test/SemaCXX/warn-implicit-unicode-conversions.cpp b/clang/test/SemaCXX/warn-implicit-unicode-conversions.cpp index f17f20ca25295..8334c122b627b 100644 --- a/clang/test/SemaCXX/warn-implicit-unicode-conversions.cpp +++ b/clang/test/SemaCXX/warn-implicit-unicode-conversions.cpp @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -verify -fsyntax-only -std=c++20 -Wconversion %s - +// XFAIL: * void c8(char8_t); void c16(char16_t); void c32(char32_t); diff --git a/clang/test/SemaCXX/warn-uninitialized-const-pointer.cpp b/clang/test/SemaCXX/warn-uninitialized-const-pointer.cpp deleted file mode 100644 index 62802ba7375cc..0000000000000 --- a/clang/test/SemaCXX/warn-uninitialized-const-pointer.cpp +++ /dev/null @@ -1,35 +0,0 @@ -// RUN: %clang_cc1 -fsyntax-only -fcxx-exceptions -Wuninitialized-const-pointer -verify %s - -template -void ignore_template(const T *) {} -void ignore(const int *) {} -void dont_ignore_non_empty(const int *) { ; } -void dont_ignore_block(const int *) { {} } -void dont_ignore_try_block(const int *) try { -} catch (...) { -} -int const_ptr_use(const int *); - -void f(int a) { - int i; - const_ptr_use(&i); // expected-warning {{variable 'i' is uninitialized when passed as a const pointer argument here}} - int j = j + const_ptr_use(&j); // expected-warning {{variable 'j' is uninitialized when used within its own initialization}} - int k = k; // expected-warning {{variable 'k' is uninitialized when used within its own initialization}} - const_ptr_use(&k); - - // Only report if a variable is always uninitialized at the point of use - int l; - if (a < 42) - l = 1; - const_ptr_use(&l); - - // Don't report if the called function is known to be empty. - int m; - ignore_template(&m); - ignore(&m); - dont_ignore_non_empty(&m); // expected-warning {{variable 'm' is uninitialized when passed as a const pointer argument here}} - int n; - dont_ignore_block(&n); // expected-warning {{variable 'n' is uninitialized when passed as a const pointer argument here}} - int o; - dont_ignore_try_block(&o); // expected-warning {{variable 'o' is uninitialized when passed as a const pointer argument here}} -} diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-addressof-arraysubscript.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-addressof-arraysubscript.cpp index 9c2908d4c4315..3418f6d4f7642 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-addressof-arraysubscript.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-addressof-arraysubscript.cpp @@ -1,8 +1,13 @@ +<<<<<<< HEAD // RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage \ // RUN: -fsafe-buffer-usage-suggestions \ // RUN: -triple=arm-apple \ // RUN: -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +// XFAIL: * +======= +// RUN: %clang_cc1 -triple=arm-apple -std=c++20 -Wunsafe-buffer-usage -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +>>>>>>> 991d7848b740 ([SafeBufferUsage] restore safe buffer usage warnings for MIOpen GTest) int f(unsigned long, void *); [[clang::unsafe_buffer_usage]] diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-deref-simple-ptr-arith.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-deref-simple-ptr-arith.cpp index 843f3f6dcb280..e9df2b146b4df 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-deref-simple-ptr-arith.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-deref-simple-ptr-arith.cpp @@ -3,6 +3,12 @@ // RUN: -fdiagnostics-parseable-fixits \ // RUN: -fsyntax-only %s 2>&1 | FileCheck %s +<<<<<<< HEAD +// need to enable unsafe buffer patches +// XFAIL:* + +======= +>>>>>>> 991d7848b740 ([SafeBufferUsage] restore safe buffer usage warnings for MIOpen GTest) // TODO test we don't mess up vertical whitespace // TODO test different whitespaces // TODO test different contexts diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-local-var-span.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-local-var-span.cpp index 292e89cb00c9e..b4059e1e9e747 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-local-var-span.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-local-var-span.cpp @@ -1,6 +1,11 @@ +<<<<<<< HEAD // RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage \ // RUN: -fsafe-buffer-usage-suggestions \ // RUN: -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +// XFAIL: * +======= +// RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +>>>>>>> 991d7848b740 ([SafeBufferUsage] restore safe buffer usage warnings for MIOpen GTest) typedef int * Int_ptr_t; typedef int Int_t; diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-pointer-deref.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-pointer-deref.cpp index 5aa2ade6dfc1d..f4d06b5db50b6 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-pointer-deref.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-pointer-deref.cpp @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage \ // RUN: -fsafe-buffer-usage-suggestions \ // RUN: -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s - + void basic_dereference() { int tmp; int* p = new int[10]; diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-fixits-test.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-fixits-test.cpp index 2509c614d989c..df57fe960bc4e 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-fixits-test.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-fixits-test.cpp @@ -1,5 +1,4 @@ // RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage -fdiagnostics-parseable-fixits -fsafe-buffer-usage-suggestions %s 2>&1 | FileCheck %s - void foo1a() { int *r = new int[7]; // CHECK-NOT: fix-it:"{{.*}}":{[[@LINE-1]]: diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-uuc-fixits.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-uuc-fixits.cpp index 58a95c9233773..81a5661180d8b 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-uuc-fixits.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-uuc-fixits.cpp @@ -1,7 +1,6 @@ // RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage \ // RUN: -fsafe-buffer-usage-suggestions \ // RUN: -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s - void bar(int * param) {} void foo1a() { diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-warnings.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-warnings.cpp index 917aa9520347d..9c38889792628 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-warnings.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-multi-decl-warnings.cpp @@ -1,5 +1,4 @@ // RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage -fsafe-buffer-usage-suggestions -verify %s - namespace std { class type_info { }; } diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-no-fixits.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-no-fixits.cpp index 3b06c15bd3912..b7b1a5ee550a7 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-no-fixits.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-no-fixits.cpp @@ -1,6 +1,14 @@ +<<<<<<< HEAD // RUN: %clang_cc1 -x c -Wunsafe-buffer-usage \ // RUN: -fsafe-buffer-usage-suggestions \ // RUN: -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +// XFAIL: * +======= +// RUN: %clang_cc1 -x c -Wunsafe-buffer-usage -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +// RUN: %clang_cc1 -x c -std=c89 -Wunsafe-buffer-usage -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +// RUN: %clang_cc1 -x c -std=gnu89 -Wunsafe-buffer-usage -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +// RUN: %clang_cc1 -x c -std=iso9899:1990 -Wunsafe-buffer-usage -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +>>>>>>> 991d7848b740 ([SafeBufferUsage] restore safe buffer usage warnings for MIOpen GTest) // RUN: %clang_cc1 -x c -std=c89 -Wunsafe-buffer-usage \ // RUN: -fsafe-buffer-usage-suggestions \ diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-pragma-fixit.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-pragma-fixit.cpp index f3e5e02e7d2a6..65797f4606263 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-pragma-fixit.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-pragma-fixit.cpp @@ -1,6 +1,11 @@ +<<<<<<< HEAD // RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage \ // RUN: -fsafe-buffer-usage-suggestions \ // RUN: -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +// XFAIL: * +======= +// RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +>>>>>>> 991d7848b740 ([SafeBufferUsage] restore safe buffer usage warnings for MIOpen GTest) void basic(int * x) { int tmp; diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-pragma.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-pragma.cpp index d8ee9bb16c329..b14498f0bbf45 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-pragma.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-pragma.cpp @@ -1,6 +1,11 @@ +<<<<<<< HEAD // RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage \ // RUN: -fsafe-buffer-usage-suggestions \ // RUN: -Wno-unused-value -verify %s +// XFAIL: * +======= +// RUN: %clang_cc1 -std=c++20 -Wunsafe-buffer-usage -Wno-unused-value -verify %s +>>>>>>> 991d7848b740 ([SafeBufferUsage] restore safe buffer usage warnings for MIOpen GTest) void basic(int * x) { // expected-warning{{'x' is an unsafe pointer used for buffer access}} int *p1 = new int[10]; // not to warn diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage.cpp index 41d38ada48788..cc4f8c51bc565 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage.cpp @@ -11,6 +11,9 @@ #define INCLUDED #pragma clang system_header +// Xfail buffer warns until MIOPEN GTEST compiles ok +// XFAIL: * + // no spanification warnings for system headers void foo(...); // let arguments of `foo` to hold testing expressions void testAsSystemHeader(char *p) { @@ -266,11 +269,11 @@ void testPointerArithmetic(int * p, const int **q, T * x) { void testTemplate(int * p) { int *a[10]; foo(f(p, &p, a, a)[1]); // expected-warning{{unsafe buffer access}} - // FIXME: expected note@-1{{in instantiation of function template specialization 'f' requested here}} + // expected-note@-1{{in instantiation of function template specialization 'f' requested here}} const int **q = const_cast(&p); - testPointerArithmetic(p, q, p); //FIXME: expected note{{in instantiation of}} + testPointerArithmetic(p, q, p); //expected-note{{in instantiation of}} } void testPointerToMember() { @@ -362,7 +365,11 @@ template void fArr(T t[], long long idx) { foo(ar[idx]); // expected-note{{used in buffer access here}} } +<<<<<<< HEAD +template void fArr(int t[]); // expected-note {{in instantiation of}} +======= template void fArr(int t[], long long); // FIXME: expected note {{in instantiation of}} +>>>>>>> 594d57e07a92e3a2cefb262114db2608989f874d int testReturn(int t[]) {// expected-note{{change type of 't' to 'std::span' to preserve bounds information}} // expected-warning@-1{{'t' is an unsafe pointer used for buffer access}} diff --git a/clang/test/SemaCXX/warn-unused-result.cpp b/clang/test/SemaCXX/warn-unused-result.cpp index 098817729efb1..3c26dd4e10a38 100644 --- a/clang/test/SemaCXX/warn-unused-result.cpp +++ b/clang/test/SemaCXX/warn-unused-result.cpp @@ -1,5 +1,4 @@ // RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 %s - int f() __attribute__((warn_unused_result)); struct S { @@ -356,40 +355,6 @@ void use2() { } } // namespace nodiscard_specialization -namespace GH117975 { -// Test for a regression for ICE in CallExpr::getUnusedResultAttr -int f() { return 0; } -void id_print_name() { - (int) // expected-warning {{expression result unused}} - ((int(*)())f)(); -} -} // namespace GH117975 - -namespace inheritance { -// Test that [[nodiscard]] is not inherited by derived class types, -// but is inherited by member functions -struct [[nodiscard]] E { - [[nodiscard]] explicit E(int); - explicit E(const char*); - [[nodiscard]] int f(); -}; -struct F : E { - using E::E; -}; -E e(); -F f(); -void test() { - e(); // expected-warning {{ignoring return value of type 'E' declared with 'nodiscard' attribute}} - f(); // no warning: derived class type does not inherit the attribute - E(1); // expected-warning {{ignoring temporary created by a constructor declared with 'nodiscard' attribute}} - E("x"); // expected-warning {{ignoring temporary of type 'E' declared with 'nodiscard' attribute}} - F(1); // no warning: inherited constructor does not inherit the attribute either - F("x"); // no warning - e().f(); // expected-warning {{ignoring return value of function declared with 'nodiscard' attribute}} - f().f(); // expected-warning {{ignoring return value of function declared with 'nodiscard' attribute}} -} -} // namespace inheritance - namespace BuildStringOnClangScope { [[clang::warn_unused_result("Discarded result")]] diff --git a/clang/test/SemaHIP/amdgpu-feature-builtins-cant-jump.hip b/clang/test/SemaHIP/amdgpu-feature-builtins-cant-jump.hip new file mode 100644 index 0000000000000..a7f1abcdcd8fe --- /dev/null +++ b/clang/test/SemaHIP/amdgpu-feature-builtins-cant-jump.hip @@ -0,0 +1,62 @@ +// REQUIRES: amdgpu-registered-target +// REQUIRES: spirv-registered-target +// RUN: %clang_cc1 -fsyntax-only -verify -triple amdgcn -target-cpu gfx900 -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple amdgcn -target-cpu gfx1201 -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple spirv64-amd-amdhsa -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple x86_64 -aux-triple amdgcn -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple x86_64 -aux-triple spirv64-amd-amdhsa -Wno-unused-value %s + +#define __device__ __attribute__((device)) +#define __global__ __attribute__((global)) + +__device__ void f(int *ptr, int size, bool f) { + int i = 0; + if (f) + goto label; // expected-error {{cannot jump from this goto statement to its label}} + + if (__builtin_amdgcn_processor_is("gfx900")) { // expected-note {{jump enters statement controlled by AMDGPU feature predicate}} + for (i = 0; i < size; ++i) { + label: + ptr[i] = i; + } + } +} + +__device__ void g(int *ptr, int size, bool f) { + int i = 0; + if (f) + goto label; // expected-error {{cannot jump from this goto statement to its label}} + + if (__builtin_amdgcn_is_invocable(__builtin_amdgcn_s_sleep_var)) { // expected-note {{jump enters statement controlled by AMDGPU feature predicate}} + for (i = 0; i < size; ++i) { + label: + ptr[i] = i; + } + } +} + +__global__ void h(int *ptr, int size, bool f) { + int i = 0; + if (f) + goto label; // expected-error {{cannot jump from this goto statement to its label}} + + if (__builtin_amdgcn_processor_is("gfx900")) { // expected-note {{jump enters statement controlled by AMDGPU feature predicate}} + for (i = 0; i < size; ++i) { + label: + ptr[i] = i; + } + } +} + +__global__ void i(int *ptr, int size, bool f) { + int i = 0; + if (f) + goto label; // expected-error {{cannot jump from this goto statement to its label}} + + if (__builtin_amdgcn_is_invocable(__builtin_amdgcn_s_sleep_var)) { // expected-note {{jump enters statement controlled by AMDGPU feature predicate}} + for (i = 0; i < size; ++i) { + label: + ptr[i] = i; + } + } +} diff --git a/clang/test/SemaHIP/amdgpu-feature-builtins-return-type-deduction.hip b/clang/test/SemaHIP/amdgpu-feature-builtins-return-type-deduction.hip new file mode 100644 index 0000000000000..27bbb3f2f3d07 --- /dev/null +++ b/clang/test/SemaHIP/amdgpu-feature-builtins-return-type-deduction.hip @@ -0,0 +1,31 @@ +// REQUIRES: amdgpu-registered-target +// REQUIRES: spirv-registered-target +// RUN: %clang_cc1 -triple amdgcn -target-cpu gfx900 -ast-dump -ast-dump-decl-types %s | FileCheck %s --strict-whitespace +// RUN: %clang_cc1 -triple amdgcn -target-cpu gfx1201 -ast-dump -ast-dump-decl-types %s | FileCheck %s --strict-whitespace +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -ast-dump -ast-dump-decl-types %s | FileCheck %s --strict-whitespace +// RUN: %clang_cc1 -triple x86_64 -aux-triple amdgcn -ast-dump -ast-dump-decl-types %s | FileCheck %s --strict-whitespace +// RUN: %clang_cc1 -triple x86_64 -aux-triple spirv64-amd-amdhsa -ast-dump -ast-dump-decl-types %s | FileCheck %s --strict-whitespace + +__attribute__((device)) auto foo() { + return __builtin_amdgcn_processor_is("gfx900"); +} + +__attribute__((device)) decltype(auto) bar() { + return __builtin_amdgcn_is_invocable(__builtin_amdgcn_s_sleep); +} + +// CHECK: |-TypedefDecl {{.*}} implicit __amdgpu_feature_predicate_t '__amdgpu_feature_predicate_t' +// CHECK-NEXT: | `-BuiltinType {{.*}} '__amdgpu_feature_predicate_t' +// CHECK-DAG: |-FunctionDecl {{.*}} foo '__amdgpu_feature_predicate_t ()' +// CHECK-NEXT: |-CompoundStmt {{.*}} +// CHECK-NEXT: | `-ReturnStmt {{.*}} +// CHECK-NEXT: | `-CallExpr {{.*}} '__amdgpu_feature_predicate_t' +// CHECK-NEXT: | |-ImplicitCastExpr {{.*}} '__amdgpu_feature_predicate_t (*)(const char *) noexcept' +// CHECK-NEXT: | | `-DeclRefExpr {{.*}} Function {{.*}} '__builtin_amdgcn_processor_is' '__amdgpu_feature_predicate_t (const char *) noexcept' +// CHECK-NEXT: | `-StringLiteral {{.*}} "gfx900" +// CHECK-DAG: |-FunctionDecl {{.*}} bar '__amdgpu_feature_predicate_t ()' +// CHECK-NEXT: |-CompoundStmt {{.*}} +// CHECK-NEXT: | `-ReturnStmt {{.*}} +// CHECK-NEXT: | `-CallExpr {{.*}} '__amdgpu_feature_predicate_t' +// CHECK-NEXT: | |-ImplicitCastExpr {{.*}} '__amdgpu_feature_predicate_t (*)() noexcept' +// CHECK-NEXT: | | `-DeclRefExpr {{.*}} Function {{.*}} '__builtin_amdgcn_is_invocable' '__amdgpu_feature_predicate_t () noexcept' diff --git a/clang/test/SemaHIP/amdgpu-is-invocable.hip b/clang/test/SemaHIP/amdgpu-is-invocable.hip new file mode 100644 index 0000000000000..214d7769a595f --- /dev/null +++ b/clang/test/SemaHIP/amdgpu-is-invocable.hip @@ -0,0 +1,21 @@ +// REQUIRES: amdgpu-registered-target +// REQUIRES: spirv-registered-target +// RUN: %clang_cc1 -fsyntax-only -verify -triple amdgcn -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple spirv64-amd-amdhsa -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple x86_64 -aux-triple amdgcn -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple x86_64 -aux-triple spirv64-amd-amdhsa -Wno-unused-value %s + +// expected-no-diagnostics + +#define __device__ __attribute__((device)) +#define __global__ __attribute__((global)) + +__device__ void foo() { + if (__builtin_amdgcn_is_invocable(__builtin_amdgcn_permlanex16)) + return __builtin_trap(); +} + +__global__ void bar() { + if (__builtin_amdgcn_is_invocable(__builtin_amdgcn_permlanex16)) + return __builtin_trap(); +} diff --git a/clang/test/SemaHIP/amdgpu-processor-is.hip b/clang/test/SemaHIP/amdgpu-processor-is.hip new file mode 100644 index 0000000000000..0f7211fd75d90 --- /dev/null +++ b/clang/test/SemaHIP/amdgpu-processor-is.hip @@ -0,0 +1,21 @@ +// REQUIRES: amdgpu-registered-target +// REQUIRES: spirv-registered-target +// RUN: %clang_cc1 -fsyntax-only -verify -triple amdgcn -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple spirv64-amd-amdhsa -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple x86_64 -aux-triple amdgcn -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple x86_64 -aux-triple spirv64-amd-amdhsa -Wno-unused-value %s + +// expected-no-diagnostics + +#define __device__ __attribute__((device)) +#define __global__ __attribute__((global)) + +__device__ void foo() { + if (__builtin_amdgcn_processor_is("gfx900")) + return __builtin_trap(); +} + +__global__ void bar() { + if (__builtin_amdgcn_processor_is("gfx900")) + return __builtin_trap(); +} diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-error.cl b/clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-error.cl new file mode 100644 index 0000000000000..b21b604baa944 --- /dev/null +++ b/clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-error.cl @@ -0,0 +1,22 @@ +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx950 -S -verify -o - %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx9-4-generic -S -verify -o - %s +// REQUIRES: amdgpu-registered-target + +typedef __attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int v4u32; +typedef v4u32 __global *global_ptr_to_v4u32; + +void test_amdgcn_global_store_b128_00(v4u32 *ptr, v4u32 data, const char* scope) { + __builtin_amdgcn_global_store_b128(ptr, data, ""); //expected-error{{passing '__private v4u32 *__private' to parameter of type '__attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int __global *' changes address space of pointer}} +} + +void test_amdgcn_global_store_b128_01(global_ptr_to_v4u32 ptr, v4u32 data, const char* scope) { + __builtin_amdgcn_global_store_b128(ptr, data, scope); //expected-error{{expression is not a string literal}} +} + +v4u32 test_amdgcn_global_load_b128_00(v4u32 *ptr, const char* scope) { + return __builtin_amdgcn_global_load_b128(ptr, ""); //expected-error{{passing '__private v4u32 *__private' to parameter of type '__attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int __global *' changes address space of pointer}} +} + +v4u32 test_amdgcn_global_load_b128_01(global_ptr_to_v4u32 ptr, const char* scope) { + return __builtin_amdgcn_global_load_b128(ptr, scope); //expected-error{{expression is not a string literal}} +} diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-target-error.cl b/clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-target-error.cl new file mode 100644 index 0000000000000..649ed9247b040 --- /dev/null +++ b/clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-target-error.cl @@ -0,0 +1,30 @@ +// We test loads and stores separately because clang only seems to exit after +// the first 'target feature' error. + +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx9-generic -DTEST_LOAD -S -verify -o - %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx10-1-generic -DTEST_LOAD -S -verify -o - %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx10-3-generic -DTEST_LOAD -S -verify -o - %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx11-generic -DTEST_LOAD -S -verify -o - %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx12-generic -DTEST_LOAD -S -verify -o - %s + +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx9-generic -DTEST_STORE -S -verify -o - %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx10-1-generic -DTEST_STORE -S -verify -o - %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx10-3-generic -DTEST_STORE -S -verify -o - %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx11-generic -DTEST_STORE -S -verify -o - %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx12-generic -DTEST_STORE -S -verify -o - %s +// REQUIRES: amdgpu-registered-target + +typedef __attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int v4u32; +typedef v4u32 __global *global_ptr_to_v4u32; + +#ifdef TEST_LOAD +v4u32 test_amdgcn_global_load_b128_01(global_ptr_to_v4u32 ptr, const char* scope) { + return __builtin_amdgcn_global_load_b128(ptr, ""); // expected-error{{'__builtin_amdgcn_global_load_b128' needs target feature gfx940-insts}} +} +#endif + +#ifdef TEST_STORE +void test_amdgcn_global_store_b128_01(global_ptr_to_v4u32 ptr, v4u32 data, const char* scope) { + __builtin_amdgcn_global_store_b128(ptr, data, ""); // expected-error{{'__builtin_amdgcn_global_store_b128' needs target feature gfx940-insts}} +} +#endif diff --git a/clang/test/lit.cfg.py b/clang/test/lit.cfg.py index 52b275c095475..81780413b00e4 100644 --- a/clang/test/lit.cfg.py +++ b/clang/test/lit.cfg.py @@ -433,6 +433,10 @@ def calculate_arch_features(arch_string): # default configs for the test runs. config.environment["CLANG_NO_DEFAULT_CONFIG"] = "1" +if config.enable_amdclang: + config.available_features.add("amdclang") + llvm_config.add_tool_substitutions(["amdclang"], tool_dirs) + if lit_config.update_tests: import sys import os diff --git a/clang/test/lit.site.cfg.py.in b/clang/test/lit.site.cfg.py.in index f50953a93a412..d481c61237701 100644 --- a/clang/test/lit.site.cfg.py.in +++ b/clang/test/lit.site.cfg.py.in @@ -46,6 +46,7 @@ config.ppc_linux_default_ieeelongdouble = @PPC_LINUX_DEFAULT_IEEELONGDOUBLE@ config.have_llvm_driver = @LLVM_TOOL_LLVM_DRIVER_BUILD@ config.spirv_tools_tests = @LLVM_INCLUDE_SPIRV_TOOLS_TESTS@ config.substitutions.append(("%llvm-version-major", "@LLVM_VERSION_MAJOR@")) +config.enable_amdclang = @CLANG_ENABLE_AMDCLANG@ import lit.llvm lit.llvm.initialize(lit_config, config) diff --git a/clang/tools/CMakeLists.txt b/clang/tools/CMakeLists.txt index 7a7c56ae217b0..a97fc6d413fad 100644 --- a/clang/tools/CMakeLists.txt +++ b/clang/tools/CMakeLists.txt @@ -12,15 +12,18 @@ add_clang_subdirectory(clang-diff) add_clang_subdirectory(clang-format) add_clang_subdirectory(clang-fuzzer) add_clang_subdirectory(clang-import-test) +add_clang_subdirectory(clang-nvlink-wrapper) add_clang_subdirectory(clang-linker-wrapper) add_clang_subdirectory(clang-nvlink-wrapper) add_clang_subdirectory(clang-offload-bundler) +add_clang_subdirectory(clang-offload-wrapper) add_clang_subdirectory(clang-scan-deps) add_clang_subdirectory(clang-sycl-linker) add_clang_subdirectory(clang-installapi) if(HAVE_CLANG_REPL_SUPPORT) add_clang_subdirectory(clang-repl) endif() +add_clang_subdirectory(clang-hip) add_clang_subdirectory(c-index-test) @@ -50,4 +53,9 @@ add_llvm_external_project(clang-tools-extra extra) # libclang may require clang-tidy in clang-tools-extra. add_clang_subdirectory(libclang) +option(CLANG_ENABLE_AMDCLANG "Enable amdclang" ON) +if (CLANG_ENABLE_AMDCLANG) + add_subdirectory(amdllvm) +endif() + add_clang_subdirectory(offload-arch) diff --git a/clang/tools/amdgpu-arch/CMakeLists.txt b/clang/tools/amdgpu-arch/CMakeLists.txt new file mode 100644 index 0000000000000..a77d5eec76a08 --- /dev/null +++ b/clang/tools/amdgpu-arch/CMakeLists.txt @@ -0,0 +1,15 @@ +# //===----------------------------------------------------------------------===// +# // +# // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +# // See https://llvm.org/LICENSE.txt for details. +# // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +# // +# //===----------------------------------------------------------------------===// + +set(LLVM_LINK_COMPONENTS Support) + +find_package(hsa-runtime64 QUIET 1.2.0 HINTS ${CMAKE_INSTALL_PREFIX} PATHS /opt/rocm) + +add_clang_tool(amdgpu-arch AMDGPUArch.cpp AMDGPUArchByKFD.cpp AMDGPUArchByHIP.cpp) + +target_link_libraries(amdgpu-arch PRIVATE clangBasic) diff --git a/clang/tools/amdllvm/CMakeLists.txt b/clang/tools/amdllvm/CMakeLists.txt new file mode 100644 index 0000000000000..964aeadfddb0c --- /dev/null +++ b/clang/tools/amdllvm/CMakeLists.txt @@ -0,0 +1,19 @@ +set(LLVM_LINK_COMPONENTS + Support +) + +add_clang_tool(amdllvm + amdllvm.cpp +) + +option(CLANG_LINK_FLANG "Create flang install link to clang" ON) + +list(APPEND CLANG_LINKS_TO_CREATE clang clang++ clang-cl clang-cpp clang-${CLANG_VERSION_MAJOR} lld) + +if(CLANG_LINK_FLANG) + list(APPEND CLANG_LINKS_TO_CREATE flang) +endif() + +foreach(link ${CLANG_LINKS_TO_CREATE}) + add_clang_symlink("amd${link}" amdllvm) +endforeach() diff --git a/clang/tools/amdllvm/amdllvm.cpp b/clang/tools/amdllvm/amdllvm.cpp new file mode 100644 index 0000000000000..059f93660cab2 --- /dev/null +++ b/clang/tools/amdllvm/amdllvm.cpp @@ -0,0 +1,38 @@ +#include "llvm/Support/Error.h" +#include "llvm/Support/Path.h" +#include "llvm/Support/Program.h" + +int main(int argc, char *argv[]) { + using namespace llvm; + using namespace llvm::sys; + + StringRef Executable = argv[0]; + StringRef Alias = sys::path::filename(Executable); + + llvm::ExitOnError Exit((Alias + ": ").str()); + + if (!Alias.consume_front("amd")) { + Exit(createStringError("binary '" + Alias + "' not prefixed by 'amd'.")); + } + + void *MainAddr = reinterpret_cast(main); + std::string AMDLlvmPath = fs::getMainExecutable(argv[0], MainAddr); + if (AMDLlvmPath.empty()) { + Exit(createStringError( + "couldn't figure out path to LLVM install bin/ directory.")); + } + + StringRef BinaryDir = path::parent_path(AMDLlvmPath); + + SmallString<256> BinaryPath; + sys::path::append(BinaryPath, BinaryDir, Alias); + + if (!fs::exists(BinaryPath)) { + Exit(createStringError("binary '" + BinaryPath + "' does not exist.")); + } + + SmallVector Argv = {BinaryPath}; + Argv.insert(Argv.end(), argv + 1, argv + argc); + + return ExecuteAndWait(BinaryPath, Argv); +} diff --git a/clang/tools/clang-fuzzer/dictionary/CMakeLists.txt b/clang/tools/clang-fuzzer/dictionary/CMakeLists.txt index 6b72b98f5e1c4..0e9a9a7bd0a37 100644 --- a/clang/tools/clang-fuzzer/dictionary/CMakeLists.txt +++ b/clang/tools/clang-fuzzer/dictionary/CMakeLists.txt @@ -1,5 +1,2 @@ -set(CMAKE_CXX_FLAGS ${CXX_FLAGS_NOFUZZ}) -add_clang_executable(clang-fuzzer-dictionary - dictionary.c - ) +add_clang_executable(clang-fuzzer-dictionary dictionary.c) diff --git a/clang/tools/clang-hip/CMakeLists.txt b/clang/tools/clang-hip/CMakeLists.txt new file mode 100644 index 0000000000000..e8bb32a4e2c7d --- /dev/null +++ b/clang/tools/clang-hip/CMakeLists.txt @@ -0,0 +1,3 @@ +if(UNIX) + add_clang_subdirectory(clang-build-select-link) +endif() diff --git a/clang/tools/clang-hip/clang-build-select-link/CMakeLists.txt b/clang/tools/clang-hip/clang-build-select-link/CMakeLists.txt new file mode 100644 index 0000000000000..dfc65829eeb73 --- /dev/null +++ b/clang/tools/clang-hip/clang-build-select-link/CMakeLists.txt @@ -0,0 +1,16 @@ +set(LLVM_LINK_COMPONENTS + BitReader + BitWriter + Core + IRReader + Linker + Object + Support + TransformUtils + IPO + ) + +add_clang_executable(clang-build-select-link ClangBuildSelectLink.cpp) +add_dependencies(clang clang-build-select-link) +install(TARGETS clang-build-select-link RUNTIME DESTINATION bin) + diff --git a/clang/tools/clang-hip/clang-build-select-link/ClangBuildSelectLink.cpp b/clang/tools/clang-hip/clang-build-select-link/ClangBuildSelectLink.cpp new file mode 100644 index 0000000000000..286a731d97ab4 --- /dev/null +++ b/clang/tools/clang-hip/clang-build-select-link/ClangBuildSelectLink.cpp @@ -0,0 +1,286 @@ +//===- ClangBuildSelectLink.cpp ------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This utility may be invoked in the following manner: +// clang-build-select-link a.bc b.bc c.bc -o merged.bc +// +// This utility merges all the bc files, then build select_outline_wrapper +// which is a big switch statement that depends on hash values. +// Then it goes back and marks each external function as linkOnceODR +// so the optimnization pass will remove wrappers and external functions. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Bitcode/BitcodeReader.h" +#include "llvm/Bitcode/BitcodeWriter.h" +#include "llvm/Frontend/OpenMP/OMPIRBuilder.h" +#include "llvm/IR/AutoUpgrade.h" +#include "llvm/IR/DiagnosticInfo.h" +#include "llvm/IR/DiagnosticPrinter.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/IR/LegacyPassNameParser.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/Verifier.h" +#include "llvm/IRReader/IRReader.h" +#include "llvm/Linker/Linker.h" +#include "llvm/Object/Archive.h" +#include "llvm/Support/InitLLVM.h" +#include "llvm/Support/ToolOutputFile.h" +#include "llvm/Support/WithColor.h" + +using namespace llvm; + +static cl::list InputFilenames(cl::Positional, cl::OneOrMore, + cl::desc("")); + +static cl::opt OutputFilename("o", + cl::desc("Override output filename"), + cl::init("-"), + cl::value_desc("filename")); + +static cl::opt Force("f", cl::desc("Enable binary output on terminals")); + +static cl::opt Verbose("v", + cl::desc("Print information about actions taken"), + cl::init(false)); + +static cl::opt DirectCalls("d", cl::desc("Enable direct calls"), + cl::init(true)); + +static cl::opt BuiltinCode("mlink-builtin-bitcode", cl::desc("Ignore option"), + cl::ZeroOrMore, cl::init(true)); + +static ExitOnError ExitOnErr; + +static bool loadArFile(const char *argv0, const std::string ArchiveName, + LLVMContext &Context, Linker &L, unsigned OrigFlags, + unsigned ApplicableFlags) { + if (Verbose) + errs() << "Reading library archive file '" << ArchiveName + << "' to memory\n"; + ErrorOr> Buf = + MemoryBuffer::getFile(ArchiveName, -1, false); + if (std::error_code EC = Buf.getError()) { + if (Verbose) + errs() << "Skipping archive : File not found " << ArchiveName << "\n"; + return false; + } else { + Error Err = Error::success(); + object::Archive Archive(Buf.get()->getMemBufferRef(), Err); + object::Archive *ArchivePtr = &Archive; + EC = errorToErrorCode(std::move(Err)); + if (Err) { + if (Verbose) + errs() << "Skipping archive : Empty file found " << ArchiveName << "\n"; + return false; + } + for (auto &C : ArchivePtr->children(Err)) { + Expected ename = C.getName(); + if (Error E = ename.takeError()) { + errs() << argv0 << ": "; + WithColor::error() + << " could not get member name of archive library failed'" + << ArchiveName << "'\n"; + return false; + }; + std::string goodname = ename.get().str(); + if (Verbose) + errs() << "Parsing member '" << goodname + << "' of archive library to module.\n"; + SMDiagnostic ParseErr; + Expected MemBuf = C.getMemoryBufferRef(); + if (Error E = MemBuf.takeError()) { + errs() << argv0 << ": "; + WithColor::error() << " loading memory for member '" << goodname + << "' of archive library failed'" << ArchiveName + << "'\n"; + return false; + }; + + std::unique_ptr M = parseIR(MemBuf.get(), ParseErr, Context); + if (!M.get()) { + errs() << argv0 << ": "; + WithColor::error() << " parsing member '" << goodname + << "' of archive library failed'" << ArchiveName + << "'\n"; + return false; + } + if (Verbose) + errs() << "Linking member '" << goodname << "' of archive library.\n"; + if (M->getTargetTriple().str() != "") { + bool Err = L.linkInModule(std::move(M), ApplicableFlags); + if (Err) + return false; + } + ApplicableFlags = OrigFlags; + } // end for each child + if (Err) { + if (Verbose) + errs() << "Skipping archive : Linking Error " << ArchiveName << "\n"; + return false; + } + } + return true; +} + +// Read bitcode file and return Module. +static std::unique_ptr +loadBcFile(const char *argv0, const std::string &FN, LLVMContext &Context) { + SMDiagnostic Err; + if (Verbose) + errs() << "Loading '" << FN << "'\n"; + std::unique_ptr Result; + Result = parseIRFile(FN, Err, Context); + + if (!Result) { + Err.print(argv0, errs()); + return nullptr; + } + + ExitOnErr(Result->materializeMetadata()); + UpgradeDebugInfo(*Result); + + return Result; +} + +static bool linkFiles(const char *argv0, LLVMContext &Context, Linker &L, + const cl::list &Files, unsigned Flags) { + // Filter out flags that don't apply to the first file we load. + unsigned ApplicableFlags = Flags & Linker::Flags::OverrideFromSrc; + // Similar to some flags, internalization doesn't apply to the first file. + for (const auto &File : Files) { + if (!llvm::sys::fs::exists(File)) { + errs() << "Warning: clang-build-select-link, file: '" << File << + "'\n Input file does not exist. File will be skipped.\n"; + continue; + } + const char *Ext = strrchr(File.c_str(), '.'); + if (!strncmp(Ext, ".a", 2)) { + if (Verbose) + errs() << "Loading library archive file'" << File << "'\n"; + bool loadArSuccess = + loadArFile(argv0, File, Context, L, Flags, ApplicableFlags); + if (!loadArSuccess) + continue; + } else { + if (Verbose) + errs() << "Loading bc file'" << File << "'\n"; + std::unique_ptr M = loadBcFile(argv0, File, Context); + if (!M.get()) { + errs() << argv0 << ": "; + WithColor::error() << " loading file '" << File << "'\n"; + return false; + } + if (Verbose) + errs() << "Linking bc File'" << File << "' to module.\n"; + if (M->getTargetTriple().str() != "") { + bool Err = L.linkInModule(std::move(M), ApplicableFlags); + if (Err) + return false; + } + } + // All linker flags apply to linking of subsequent files. + ApplicableFlags = Flags; + } + return true; +} + +static bool convertExternsToLinkOnce(Module *MOUT, LLVMContext &Ctx) { + for (Module::iterator i = MOUT->begin(), e = MOUT->end(); i != e; ++i) { + llvm::Function *F = &*i; + if (!i->isDeclaration()) { + if (i->getCallingConv() != llvm::CallingConv::AMDGPU_KERNEL) { + // defined function is not an AMD kernel + if (Verbose) + errs() << "Modifying Function attributes for function \'" + << F->getName().str().c_str() << "\' \n"; + // Convert functions to LinkOnceODR with protected visibility + F->setLinkage(GlobalValue::LinkOnceODRLinkage); + F->setVisibility(GlobalValue::ProtectedVisibility); + if (!strncmp(F->getName().str().c_str(), "__ockl_devmem_request", + strlen("__ockl_devmem_request"))) + continue; + if (!strncmp(F->getName().str().c_str(), "__ockl_dm_alloc", + strlen("__ockl_dm_alloc"))) + continue; + if (!strncmp(F->getName().str().c_str(), "__ockl_dm_dealloc", + strlen("__ockl_dm_dealloc"))) + continue; + if (!strncmp(F->getName().str().c_str(), "hostexec_invoke", + strlen("hostexec_invoke"))) + continue; + // all other functions + if (!F->hasOptNone()) { + F->removeFnAttr(llvm::Attribute::OptimizeNone); + F->removeFnAttr(llvm::Attribute::NoInline); + F->addFnAttr(llvm::Attribute::AlwaysInline); + } + } else { + // defined function is an AMD kernel + if (F->getName().starts_with("__nv_")) { + // Assume FORTRAN kernels start with __nv_ + if (Verbose) + errs() << "Kernel attributes added to FORTRAN kernel\'" + << F->getName().str().c_str() << "\' \n"; + // Function Attrs: convergent mustprogress norecurse, nounwind + F->addFnAttr(llvm::Attribute::Convergent); + F->addFnAttr(llvm::Attribute::MustProgress); + F->addFnAttr(llvm::Attribute::NoRecurse); + F->addFnAttr(llvm::Attribute::NoUnwind); + F->setVisibility(GlobalValue::ProtectedVisibility); + } + } + } + } + return true; +} + +int main(int argc, char **argv) { + InitLLVM InitX(argc, argv); + ExitOnErr.setBanner(std::string(argv[0]) + ": "); + + LLVMContext Context; + + cl::ParseCommandLineOptions(argc, argv, "clang-build-select-link\n"); + + auto Composite = std::make_unique("clang-build-select-link", Context); + Linker L(*Composite); + + unsigned Flags = Linker::Flags::None; + + if (!linkFiles(argv[0], Context, L, InputFilenames, Flags)) + return 1; + + Module *MOUT = &*Composite; + if (!convertExternsToLinkOnce(MOUT, Context)) + return 1; + + std::error_code EC; + ToolOutputFile Out(OutputFilename, EC, sys::fs::OF_None); + if (EC) { + WithColor::error() << EC.message() << '\n'; + return 1; + } + + if (verifyModule(*Composite, &errs())) { + errs() << argv[0] << ": "; + WithColor::error() << "linked module is broken!\n"; + return 1; + } + + if (Verbose) + errs() << "Writing merged bitcode...\n"; + + WriteBitcodeToFile(*Composite, Out.os(), false); + + Out.keep(); + + return 0; +} diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index bfeca17d2147e..a36b4aae9417d 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -948,7 +948,7 @@ Error handleOverrideImages( /// be registered by the runtime. Expected> linkAndWrapDeviceFiles(ArrayRef> LinkerInputFiles, - const InputArgList &Args, char **Argv, int Argc) { + InputArgList &Args, char **Argv, int Argc) { llvm::TimeTraceScope TimeScope("Handle all device input"); std::mutex ImageMtx; @@ -959,6 +959,9 @@ linkAndWrapDeviceFiles(ArrayRef> LinkerInputFiles, if (Error Err = handleOverrideImages(Args, Images)) return std::move(Err); + bool ExcludeNVPTX = Args.hasArg(OPT_no_nvptx_whole_archive); + bool ExcludeAMDGPU = Args.hasArg(OPT_no_amdgpu_whole_archive); + auto Err = parallelForEachError(LinkerInputFiles, [&](auto &Input) -> Error { llvm::TimeTraceScope TimeScope("Link device input"); @@ -973,6 +976,13 @@ linkAndWrapDeviceFiles(ArrayRef> LinkerInputFiles, }); auto LinkerArgs = getLinkerArgs(Input, BaseArgs); + const llvm::Triple Triple(LinkerArgs.getLastArgValue(OPT_triple_EQ)); + if (Triple.isNVPTX() && ExcludeNVPTX) + return Error::success(); + + if (Triple.isAMDGPU() && ExcludeAMDGPU) + return Error::success(); + uint16_t ActiveOffloadKindMask = 0u; for (const auto &File : Input) ActiveOffloadKindMask |= File.getBinary()->getOffloadKind(); @@ -1036,6 +1046,13 @@ linkAndWrapDeviceFiles(ArrayRef> LinkerInputFiles, if (Err) return std::move(Err); + // This option is specific to this link phase and the preceding link tools + // do not understand this option so we remove it now that we're done with it. + if (ExcludeNVPTX) + Args.eraseArg(OPT_no_nvptx_whole_archive); + if (ExcludeAMDGPU) + Args.eraseArg(OPT_no_amdgpu_whole_archive); + // Create a binary image of each offloading image and embed it into a new // object file. SmallVector WrappedOutput; diff --git a/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td b/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td index 87f911c749bf6..f632f6a76e7f6 100644 --- a/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td +++ b/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td @@ -124,6 +124,9 @@ def version : Flag<["--", "-"], "version">, Flags<[HelpHidden]>, Alias; def whole_archive : Flag<["--", "-"], "whole-archive">, Flags<[HelpHidden]>; def no_whole_archive : Flag<["--", "-"], "no-whole-archive">, Flags<[HelpHidden]>; +def no_nvptx_whole_archive : Flag<["--", "-"], "no-nvptx-whole-archive">, Flags<[HelpHidden]>; +def no_amdgpu_whole_archive : Flag<["--", "-"], "no-amdgpu-whole-archive">, Flags<[HelpHidden]>; + def relocatable : Flag<["--", "-"], "relocatable">, HelpText<"Link device code to create a relocatable offloading application">; def r : Flag<["-"], "r">, Alias; diff --git a/clang/tools/clang-offload-wrapper/CMakeLists.txt b/clang/tools/clang-offload-wrapper/CMakeLists.txt new file mode 100644 index 0000000000000..2c056be605b8f --- /dev/null +++ b/clang/tools/clang-offload-wrapper/CMakeLists.txt @@ -0,0 +1,19 @@ +set(LLVM_LINK_COMPONENTS BitWriter BinaryFormat Core FrontendOffloading Object Support TransformUtils TargetParser) + +add_clang_tool(clang-offload-wrapper + ClangOffloadWrapper.cpp + + DEPENDS + intrinsics_gen + ) + +set(CLANG_OFFLOAD_WRAPPER_LIB_DEPS + clangBasic + ) + +add_dependencies(clang clang-offload-wrapper) + +clang_target_link_libraries(clang-offload-wrapper + PRIVATE + ${CLANG_OFFLOAD_WRAPPER_LIB_DEPS} + ) diff --git a/clang/tools/clang-offload-wrapper/ClangOffloadWrapper.cpp b/clang/tools/clang-offload-wrapper/ClangOffloadWrapper.cpp new file mode 100644 index 0000000000000..6ea5ebabd64d5 --- /dev/null +++ b/clang/tools/clang-offload-wrapper/ClangOffloadWrapper.cpp @@ -0,0 +1,527 @@ +//===-- clang-offload-wrapper/ClangOffloadWrapper.cpp -----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation of the offload wrapper tool. It takes offload target binaries +/// as input and creates wrapper bitcode file containing target binaries +/// packaged as data. Wrapper bitcode also includes initialization code which +/// registers target binaries in offloading runtime at program startup. +/// +//===----------------------------------------------------------------------===// + +#include "clang/Basic/Version.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/Bitcode/BitcodeWriter.h" +#include "llvm/Frontend/Offloading/OffloadWrapper.h" +#include "llvm/Frontend/Offloading/Utility.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/IR/Module.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Object/OffloadBinary.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/EndianStream.h" +#include "llvm/Support/Errc.h" +#include "llvm/Support/Error.h" +#include "llvm/Support/ErrorOr.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/Path.h" +#include "llvm/Support/Program.h" +#include "llvm/Support/Signals.h" +#include "llvm/Support/ToolOutputFile.h" +#include "llvm/Support/VCSRevision.h" +#include "llvm/Support/WithColor.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/TargetParser/Triple.h" +#include "llvm/Transforms/Utils/ModuleUtils.h" +#include +#include +#include + +#define OPENMP_OFFLOAD_IMAGE_VERSION "1.0" + +using namespace llvm; +using namespace llvm::object; +using OffloadingImage = OffloadBinary::OffloadingImage; + +namespace llvm { +// Provide DenseMapInfo so that OffloadKind can be used in a DenseMap. +template <> struct DenseMapInfo { + static inline OffloadKind getEmptyKey() { return OFK_LAST; } + static inline OffloadKind getTombstoneKey() { + return static_cast(OFK_LAST + 1); + } + static unsigned getHashValue(const OffloadKind &Val) { return Val; } + + static bool isEqual(const OffloadKind &LHS, const OffloadKind &RHS) { + return LHS == RHS; + } +}; +} // namespace llvm + +static cl::opt Help("h", cl::desc("Alias for -help"), cl::Hidden); + +// Mark all our options with this category, everything else (except for -version +// and -help) will be hidden. +static cl::OptionCategory + ClangOffloadWrapperCategory("clang-offload-wrapper options"); + +static cl::opt Output("o", cl::Required, + cl::desc("Output filename"), + cl::value_desc("filename"), + cl::cat(ClangOffloadWrapperCategory)); + +static cl::list Inputs(cl::Positional, cl::OneOrMore, + cl::desc(""), + cl::cat(ClangOffloadWrapperCategory)); + +// The target triple for offload objects (input files). +static cl::opt Target("target", cl::Required, + cl::desc("Target triple for input files"), + cl::value_desc("triple"), + cl::cat(ClangOffloadWrapperCategory)); + +// The target triple for the host, not the wrapped offload objects. NOTE: This +// argument is optional, and if it is omitted it defaults to using the value +// given by the +// "-target" option above (which is then presumed to match the host +// architecture, not the offload target). This is wrong, but matches legacy +// behaviour. +static cl::opt + AuxTriple("aux-triple", cl::Optional, + cl::desc("Target triple for the output module"), + cl::value_desc("triple"), cl::cat(ClangOffloadWrapperCategory)); + +static cl::opt SaveTemps( + "save-temps", + cl::desc("Save temporary files that may be produced by the tool. " + "This option forces print-out of the temporary files' names."), + cl::Hidden); + +static cl::opt AddOpenMPOffloadNotes( + "add-omp-offload-notes", + cl::desc("Add LLVMOMPOFFLOAD ELF notes to ELF device images."), cl::Hidden); + +static cl::list OffloadArch( + "offload-arch", + cl::desc("Contains offload-arch of the following target binary."), + cl::value_desc("offload-arch-name"), cl::cat(ClangOffloadWrapperCategory)); + +std::unique_ptr addELFNotes(std::unique_ptr Buf, + StringRef OriginalFileName, + StringRef ToolName) { + // This just needs to be some symbol in the binary; C++ doesn't + // allow taking the address of ::main however. + void *P = (void *)(intptr_t)&Help; + + // Look for llvm-objcopy in the same directory, from which + // clang-offload-wrapper is invoked. This helps OpenMP offload LIT tests + std::string ObjcopyPath; + std::string COWPath = sys::fs::getMainExecutable(ToolName.str().c_str(), P); + if (!COWPath.empty()) { + auto COWDir = sys::path::parent_path(COWPath); + ErrorOr ObjcopyPathOrErr = + sys::findProgramByName("llvm-objcopy", {COWDir}); + if (ObjcopyPathOrErr) { + ObjcopyPath = *ObjcopyPathOrErr; + } else { + fprintf(stderr, "ERROR: Could not find llvm-objcopy in dir %s\n", + COWDir.str().c_str()); + abort(); + } + ObjcopyPath = *ObjcopyPathOrErr; + } else { + // Otherwise, look through PATH environment. + ErrorOr ObjcopyPathOrErr = + sys::findProgramByName("llvm-objcopy"); + if (ObjcopyPathOrErr) { + WithColor::warning(errs(), ToolName) + << "cannot find llvm-objcopy[.exe] in PATH; ELF notes cannot be " + "added.\n"; + abort(); + } + ObjcopyPath = *ObjcopyPathOrErr; + } + + StringRef ToolNameRef(ToolName); + + // Helpers to emit warnings. + auto warningOS = [ToolNameRef]() -> raw_ostream & { + return WithColor::warning(errs(), ToolNameRef); + }; + auto handleErrorAsWarning = [&warningOS](Error E) { + logAllUnhandledErrors(std::move(E), warningOS()); + }; + + Expected> BinOrErr = + ObjectFile::createELFObjectFile(Buf->getMemBufferRef(), + /*InitContent=*/false); + if (Error E = BinOrErr.takeError()) { + consumeError(std::move(E)); + // This warning is questionable, but let it be here, + // assuming that most OpenMP offload models use ELF offload images. + warningOS() << OriginalFileName + << " is not an ELF image, so notes cannot be added to it.\n"; + return Buf; + } + + // If we fail to add the note section, we just pass through the original + // ELF image for wrapping. At some point we should enforce the note section + // and start emitting errors vs warnings. + llvm::endianness Endianness; + if (isa(BinOrErr->get()) || + isa(BinOrErr->get())) { + Endianness = llvm::endianness::little; + } else if (isa(BinOrErr->get()) || + isa(BinOrErr->get())) { + Endianness = llvm::endianness::big; + } else { + warningOS() << OriginalFileName + << " is an ELF image of unrecognized format.\n"; + return Buf; + } + + // Create temporary file for the data of a new SHT_NOTE section. + // We fill it in with data and then pass to llvm-objcopy invocation + // for reading. + std::vector TempFiles; + Twine NotesFileModel = OriginalFileName + Twine(".elfnotes.%%%%%%%.tmp"); + Expected NotesTemp = + sys::fs::TempFile::create(NotesFileModel); + if (Error E = NotesTemp.takeError()) { + handleErrorAsWarning(createFileError(NotesFileModel, std::move(E))); + return Buf; + } + TempFiles.push_back(NotesTemp->TmpName); + + // Create temporary file for the updated ELF image. + // This is an empty file that we pass to llvm-objcopy invocation + // for writing. + Twine ELFFileModel = OriginalFileName + Twine(".elfwithnotes.%%%%%%%.tmp"); + Expected ELFTemp = sys::fs::TempFile::create(ELFFileModel); + if (Error E = ELFTemp.takeError()) { + handleErrorAsWarning(createFileError(ELFFileModel, std::move(E))); + return Buf; + } + TempFiles.push_back(ELFTemp->TmpName); + + // Keep the new ELF image file to reserve the name for the future + // llvm-objcopy invocation. + std::string ELFTmpFileName = ELFTemp->TmpName; + if (Error E = ELFTemp->keep(ELFTmpFileName)) { + handleErrorAsWarning(createFileError(ELFTmpFileName, std::move(E))); + return Buf; + } + + // Write notes to the *elfnotes*.tmp file. + raw_fd_ostream NotesOS(NotesTemp->FD, false); + + struct NoteTy { + // Note name is a null-terminated "LLVMOMPOFFLOAD". + std::string Name; + // Note type defined in llvm/include/llvm/BinaryFormat/ELF.h. + uint32_t Type = 0; + // Each note has type-specific associated data. + std::string Desc; + + NoteTy(std::string &&Name, uint32_t Type, std::string &&Desc) + : Name(std::move(Name)), Type(Type), Desc(std::move(Desc)) {} + }; + + // So far we emit just three notes. + SmallVector Notes; + // Version of the offload image identifying the structure of the ELF image. + // Version 1.0 does not have any specific requirements. + // We may come up with some structure that has to be honored by all + // offload implementations in future (e.g. to let libomptarget + // get some information from the offload image). + Notes.emplace_back("LLVMOMPOFFLOAD", ELF::NT_LLVM_OPENMP_OFFLOAD_VERSION, + OPENMP_OFFLOAD_IMAGE_VERSION); + // This is a producer identification string. We are LLVM! + Notes.emplace_back("LLVMOMPOFFLOAD", ELF::NT_LLVM_OPENMP_OFFLOAD_PRODUCER, + "LLVM"); + // This is a producer version. Use the same format that is used + // by clang to report the LLVM version. + Notes.emplace_back("LLVMOMPOFFLOAD", + ELF::NT_LLVM_OPENMP_OFFLOAD_PRODUCER_VERSION, + LLVM_VERSION_STRING +#ifdef LLVM_REVISION + " " LLVM_REVISION +#endif + ); + + // Return the amount of padding required for a blob of N bytes + // to be aligned to Alignment bytes. + auto getPadAmount = [](uint32_t N, uint32_t Alignment) -> uint32_t { + uint32_t Mod = (N % Alignment); + if (Mod == 0) + return 0; + return Alignment - Mod; + }; + auto emitPadding = [&getPadAmount](raw_ostream &OS, uint32_t Size) { + for (uint32_t I = 0; I < getPadAmount(Size, 4); ++I) + OS << '\0'; + }; + + // Put notes into the file. + for (auto &N : Notes) { + assert(!N.Name.empty() && "We should not create notes with empty names."); + // Name must be null-terminated. + if (N.Name.back() != '\0') + N.Name += '\0'; + uint32_t NameSz = N.Name.size(); + uint32_t DescSz = N.Desc.size(); + // A note starts with three 4-byte values: + // NameSz + // DescSz + // Type + // These three fields are endian-sensitive. + support::endian::write(NotesOS, NameSz, Endianness); + support::endian::write(NotesOS, DescSz, Endianness); + support::endian::write(NotesOS, N.Type, Endianness); + // Next, we have a null-terminated Name padded to a 4-byte boundary. + NotesOS << N.Name; + emitPadding(NotesOS, NameSz); + if (DescSz == 0) + continue; + // Finally, we have a descriptor, which is an arbitrary flow of bytes. + NotesOS << N.Desc; + emitPadding(NotesOS, DescSz); + } + NotesOS.flush(); + + // Keep the notes file. + std::string NotesTmpFileName = NotesTemp->TmpName; + if (Error E = NotesTemp->keep(NotesTmpFileName)) { + handleErrorAsWarning(createFileError(NotesTmpFileName, std::move(E))); + return Buf; + } + + // Run llvm-objcopy like this: + // llvm-objcopy --add-section=.note.openmp= \ + // + // + // This will add a SHT_NOTE section on top of the original ELF. + std::vector Args; + Args.push_back(ObjcopyPath); + std::string Option("--add-section=.note.openmp=" + NotesTmpFileName); + Args.push_back(Option); + // + // Requires disabling the verification of .note sections inside + // llvm-objcopy because the default verification option expects + // only one note inside a .note section unlike the case here. + std::string DisableVerifyNoteSections("--no-verify-note-sections"); + Args.push_back(DisableVerifyNoteSections); + Args.push_back(OriginalFileName); + Args.push_back(ELFTmpFileName); + bool ExecutionFailed = false; + std::string ErrMsg; + (void)sys::ExecuteAndWait(ObjcopyPath, Args, + /*Env=*/std::nullopt, /*Redirects=*/{}, + /*SecondsToWait=*/0, + /*MemoryLimit=*/0, &ErrMsg, &ExecutionFailed); + + if (ExecutionFailed) { + warningOS() << ErrMsg << "\n"; + return Buf; + } + + // Substitute the original ELF with new one. + ErrorOr> BufOrErr = + MemoryBuffer::getFile(ELFTmpFileName); + if (!BufOrErr) { + handleErrorAsWarning(createFileError(ELFTmpFileName, BufOrErr.getError())); + return Buf; + } + + return std::move(*BufOrErr); +} // End addELFNotes + +Expected>> +bundleImage(ArrayRef Images) { + SmallVector> Buffers; + for (const OffloadingImage &Image : Images) { + Buffers.emplace_back( + MemoryBuffer::getMemBufferCopy(OffloadBinary::write(Image))); + } + return std::move(Buffers); +} + +// If we are invoked with "-target" but not "-aux-triple", assume that the +// triple given refers to the host, rather than the offload target (which is +// the legacy behaviour). In that case, we only know the architecture +// version (gfx90x, sm*). Try to guess the triple for the offload target, +// or fall back to the "-target" setting if we see something unexpected +// (e.g., offloading to x86_64 from x86_64). This is a best-effort attempt, +// and may not DTRT in all circumstances. +static const char *GuessTargetFromArch(const char *Arch) { + if (strncmp(Arch, "gfx", 3) == 0) { + return "amdgcn-amd-amdhsa"; + } else if (strncmp(Arch, "sm_", 3) == 0) { + return "nvptx64-nvidia-cuda"; + } else { + return Target.c_str(); + } +} + +int main(int argc, const char **argv) { + StringRef ToolName(argv[0]); + sys::PrintStackTraceOnErrorSignal(argv[0]); + + cl::HideUnrelatedOptions(ClangOffloadWrapperCategory); + cl::SetVersionPrinter([](raw_ostream &OS) { + OS << clang::getClangToolFullVersion("clang-offload-wrapper") << '\n'; + }); + cl::ParseCommandLineOptions( + argc, argv, + "A tool to create a wrapper bitcode for offload target binaries. Takes " + "offload\ntarget binaries as input and produces bitcode file containing " + "target binaries packaged\nas data and initialization code which " + "registers target binaries in offload runtime.\n"); + + if (Help) { + cl::PrintHelpMessage(); + return 0; + } + + auto reportError = [argv](Error E) { + logAllUnhandledErrors(std::move(E), WithColor::error(errs(), argv[0])); + }; + + if (Triple(Target).getArch() == Triple::UnknownArch) { + reportError(createStringError( + errc::invalid_argument, "'" + Target + "': unsupported target triple")); + return 1; + } + + if (!AuxTriple.empty() && + Triple(AuxTriple).getArch() == Triple::UnknownArch) { + reportError(createStringError(errc::invalid_argument, + "'" + AuxTriple + + "': unsupported aux target triple")); + return 1; + } + + LLVMContext Context; + Module MM("offload.wrapper.module", Context); + + MM.setTargetTriple( AuxTriple.empty() ? Triple(Target) : Triple(AuxTriple)); + + // Collect offload-archs. + SmallVector, 4u> OffloadArchs; + OffloadArchs.reserve(OffloadArch.size()); + for (unsigned i = 0; i != OffloadArch.size(); ++i) { + OffloadArch[i].append("\0"); + OffloadArchs.emplace_back(OffloadArch[i].data(), OffloadArch[i].size() + 1); + } + + // Create the output file to write the resulting bitcode to. + std::error_code EC; + ToolOutputFile Out(Output, EC, sys::fs::OF_None); + if (EC) { + reportError(createFileError(Output, EC)); + return 1; + } + + // Read device binaries. + DenseMap> Images; + + const auto &TargetTriple = Triple(Target); + + int numOffloadArch = 0; + for (const std::string &File : Inputs) { + ErrorOr> BufOrErr = + MemoryBuffer::getFileOrSTDIN(File); + if (!BufOrErr) { + reportError(createFileError(File, BufOrErr.getError())); + return 1; + } + std::unique_ptr Buffer(std::move(*BufOrErr)); + if (File != "-" && AddOpenMPOffloadNotes) { + // Adding ELF notes for STDIN is not supported yet. + Buffer = addELFNotes(std::move(Buffer), File, ToolName); + } + + OffloadingImage TheImage{}; + if (llvm::identify_magic(Buffer->getBuffer()) == llvm::file_magic::bitcode) + TheImage.TheImageKind = IMG_Bitcode; + else + TheImage.TheImageKind = IMG_Object; + TheImage.TheOffloadKind = OFK_OpenMP; + if (!AuxTriple.empty() || OffloadArchs.size() == 0) { + TheImage.StringData["triple"] = Target.c_str(); + } else { + TheImage.StringData["triple"] = + GuessTargetFromArch(OffloadArch[numOffloadArch].c_str()); + } + if (OffloadArchs.size() != 0) { + TheImage.StringData["arch"] = OffloadArch[numOffloadArch].c_str(); + numOffloadArch++; + } else + TheImage.StringData["arch"] = ""; + TheImage.Image = std::move(Buffer); + Images[OFK_OpenMP].emplace_back(std::move(TheImage)); + } + + // Bundle and wrap binaries + SmallVector, 4> BuffersToWrap; + for (auto &[Kind, Input] : Images) { + // We sort the entries before bundling so they appear in a deterministic + // order in the final binary. + llvm::sort(Input, [](OffloadingImage &A, OffloadingImage &B) { + return A.StringData["triple"] > B.StringData["triple"] || + A.StringData["arch"] > B.StringData["arch"] || + A.TheOffloadKind < B.TheOffloadKind; + }); + + auto BundledImagesOrErr = bundleImage(Input); + if (!BundledImagesOrErr) + return 1; + + for (const auto &myImage : *BundledImagesOrErr) + BuffersToWrap.emplace_back( + ArrayRef(myImage->getBufferStart(), myImage->getBufferSize())); + + switch (Kind) { + case OFK_OpenMP: + if (Error Err = offloading::wrapOpenMPBinaries( + MM, BuffersToWrap, offloading::getOffloadEntryArray(MM), + /*Suffix=*/"", /*Relocatable=*/false)) + return 1; + break; + case OFK_Cuda: + if (Error Err = offloading::wrapCudaBinary( + MM, BuffersToWrap.front(), offloading::getOffloadEntryArray(MM), + /*Suffix=*/"", /*EmitSurfacesAndTextures=*/false)) + return 1; + break; + case OFK_HIP: + if (Error Err = offloading::wrapHIPBinary( + MM, BuffersToWrap.front(), offloading::getOffloadEntryArray(MM))) + return 1; + break; + default: + return 1; + } + } // End for each image + + WriteBitcodeToFile(MM, Out.os()); + if (Out.os().has_error()) { + reportError(createFileError(Output, Out.os().error())); + return 1; + } + + // Success. + Out.keep(); + return 0; +} diff --git a/clang/tools/driver/CMakeLists.txt b/clang/tools/driver/CMakeLists.txt index d9d36f7a41359..a9fa61f9f75ee 100644 --- a/clang/tools/driver/CMakeLists.txt +++ b/clang/tools/driver/CMakeLists.txt @@ -79,8 +79,16 @@ endif() add_dependencies(clang clang-resource-headers) +option(CLANG_LINK_FLANG "Create flang install link to clang" ON) +#Only create flang symlink if Flang is not being built +list(FIND LLVM_ENABLE_PROJECTS flang FLANG_TARGET_INDEX) + if(NOT CLANG_LINKS_TO_CREATE) - set(CLANG_LINKS_TO_CREATE clang++ clang-cl clang-cpp) + if(CLANG_LINK_FLANG AND "${FLANG_TARGET_INDEX}" EQUAL "-1") + set(CLANG_LINKS_TO_CREATE clang++ clang-cl clang-cpp flang) + else() + set(CLANG_LINKS_TO_CREATE clang++ clang-cl clang-cpp) + endif() endif() if (CLANG_ENABLE_HLSL) @@ -88,7 +96,25 @@ if (CLANG_ENABLE_HLSL) endif() foreach(link ${CLANG_LINKS_TO_CREATE} ${HLSL_LINK}) - add_clang_symlink(${link} clang) +# We need to separate classic flang from the new llvm flang +# that is in development. Until the new llvm flang replaces +# classic, we need to have a flang -> flang-classic symlink +# instead of flang -> clang. Flang-legacy is built later during +# openmp-extras and is based of llvm archives from ROCm 5.5. +# This can be removed once llvm flang is in production. + if(CLANG_LINK_FLANG_LEGACY AND "${link}" STREQUAL "flang") + foreach(path ${CMAKE_MODULE_PATH}) + if(EXISTS ${path}/LLVMInstallSymlink.cmake) + set(INSTALL_SYMLINK ${path}/LLVMInstallSymlink.cmake) + break() + endif() + endforeach() + install(SCRIPT ${INSTALL_SYMLINK} + CODE "install_symlink(flang flang bin create_symlink)" + COMPONENT ${component}) + else() + add_clang_symlink(${link} clang) + endif() endforeach() # Configure plist creation for OS X. diff --git a/clang/tools/driver/driver.cpp b/clang/tools/driver/driver.cpp index 7390d7d610ec0..6cf64d70c9399 100644 --- a/clang/tools/driver/driver.cpp +++ b/clang/tools/driver/driver.cpp @@ -203,6 +203,13 @@ static void FixupDiagPrefixExeName(TextDiagnosticPrinter *DiagClient, DiagClient->setPrefix(std::string(ExeBasename)); } +static void PopulateArgsOpts(ArrayRef argv, + InputArgList &Args) { + unsigned MissingArgIndex, MissingArgCount; + Args = getDriverOptTable().ParseArgs(argv.slice(1), MissingArgIndex, + MissingArgCount); +} + static int ExecuteCC1Tool(SmallVectorImpl &ArgV, const llvm::ToolContext &ToolContext, IntrusiveRefCntPtr VFS) { @@ -325,6 +332,9 @@ int clang_main(int Argc, char **Argv, const llvm::ToolContext &ToolContext) { .Case("-fintegrated-cc1", false) .Default(UseNewCC1Process); + InputArgList ArgList; + PopulateArgsOpts(Args, ArgList); + std::unique_ptr DiagOpts = CreateAndPopulateDiagOpts(Args); // Driver's diagnostics don't use suppression mappings, so don't bother // parsing them. CC1 still receives full args, so this doesn't impact other @@ -337,6 +347,13 @@ int clang_main(int Argc, char **Argv, const llvm::ToolContext &ToolContext) { DiagnosticsEngine Diags(DiagnosticIDs::create(), *DiagOpts, DiagClient); + unsigned NumParallelJobs = + getLastArgIntValue(ArgList, options::OPT_parallel_jobs_EQ, 1, Diags); + UseNewCC1Process = + ArgList.hasFlag(clang::driver::options::OPT_fno_integrated_cc1, + clang::driver::options::OPT_fintegrated_cc1, + /*Default=*/NumParallelJobs > 1 ? true : CLANG_SPAWN_CC1); + if (!DiagOpts->DiagnosticSerializationFile.empty()) { auto SerializedConsumer = clang::serialized_diags::create(DiagOpts->DiagnosticSerializationFile, diff --git a/clang/unittests/Interpreter/InterpreterExtensionsTest.cpp b/clang/unittests/Interpreter/InterpreterExtensionsTest.cpp index f50f6e320776d..6de03a8eaf0e6 100644 --- a/clang/unittests/Interpreter/InterpreterExtensionsTest.cpp +++ b/clang/unittests/Interpreter/InterpreterExtensionsTest.cpp @@ -176,4 +176,4 @@ TEST_F(InterpreterExtensionsTest, CustomCrossJIT) { EXPECT_EQ(1U, Objs.size()); } -} // end anonymous namespace +} // end anonymous namespace \ No newline at end of file diff --git a/compiler-rt/CMakeLists.txt b/compiler-rt/CMakeLists.txt index a9e8899f8ae0c..1ea093e7ecc2d 100644 --- a/compiler-rt/CMakeLists.txt +++ b/compiler-rt/CMakeLists.txt @@ -508,6 +508,26 @@ elseif(COMPILER_RT_HAS_G_FLAG) list(APPEND SANITIZER_COMMON_CFLAGS -g) endif() +if(SANITIZER_AMDGPU) + list(APPEND SANITIZER_COMMON_CFLAGS -DSANITIZER_AMDGPU=1) + message(STATUS "Looking 'hsa' and 'amd_comgr' header") + find_path(HSA_INCLUDE NAMES hsa.h HINTS ${SANITIZER_HSA_INCLUDE_PATH} /opt/rocm/include PATH_SUFFIXES hsa) + if(NOT HSA_INCLUDE) + message(FATAL_ERROR "Required header 'hsa.h' not found in path ${HSA_INCLUDE}. Aborting SANITIZER_AMDGPU build") + endif() + message(STATUS "Found 'hsa.h' in ${HSA_INCLUDE}") + include_directories(${HSA_INCLUDE}) + find_path(COMgr_INCLUDE NAMES amd_comgr.h.in HINTS ${SANITIZER_COMGR_INCLUDE_PATH} PATH_SUFFIXES amd_comgr) + if(NOT COMgr_INCLUDE) + find_path(COMgr_INCLUDE NAMES amd_comgr.h HINTS /opt/rocm/include PATH_SUFFIXES amd_comgr) + if(NOT COMgr_INCLUDE) + message(FATAL_ERROR "Required header 'amd_comgr.h/amd_comgr.h.in' not found in path ${COMgr_INCLUDE}. Aborting SANITIZER_AMDGPU build") + endif() + endif() + message(STATUS "Found 'amd_comgr.h.in/amd_comgr.h' in ${COMgr_INCLUDE}") + include_directories(${COMgr_INCLUDE}) +endif() + if(LLVM_ENABLE_MODULES) # Sanitizers cannot be built with -fmodules. The interceptors intentionally # don't include system headers, which is incompatible with modules. diff --git a/compiler-rt/lib/asan/CMakeLists.txt b/compiler-rt/lib/asan/CMakeLists.txt old mode 100644 new mode 100755 diff --git a/compiler-rt/lib/asan/asan_allocator.cpp b/compiler-rt/lib/asan/asan_allocator.cpp index 752ba9ab32c71..06c827c41eacc 100644 --- a/compiler-rt/lib/asan/asan_allocator.cpp +++ b/compiler-rt/lib/asan/asan_allocator.cpp @@ -390,7 +390,11 @@ struct Allocator { void InitLinkerInitialized(const AllocatorOptions &options) { SetAllocatorMayReturnNull(options.may_return_null); +#if SANITIZER_AMDGPU + allocator.InitLinkerInitialized(options.release_to_os_interval_ms, 0, true); +#else allocator.InitLinkerInitialized(options.release_to_os_interval_ms); +#endif SharedInitCode(options); max_user_defined_malloc_size = common_flags()->max_allocation_size_mb ? common_flags()->max_allocation_size_mb @@ -532,7 +536,8 @@ struct Allocator { // -------------------- Allocation/Deallocation routines --------------- void *Allocate(uptr size, uptr alignment, BufferedStackTrace *stack, - AllocType alloc_type, bool can_fill) { + AllocType alloc_type, bool can_fill, + DeviceAllocationInfo *da_info = nullptr) { if (UNLIKELY(!AsanInited())) AsanInitFromRtl(); if (UNLIKELY(IsRssLimitExceeded())) { @@ -587,11 +592,11 @@ struct Allocator { void *allocated; if (t) { AllocatorCache *cache = GetAllocatorCache(&t->malloc_storage()); - allocated = allocator.Allocate(cache, needed_size, 8); + allocated = allocator.Allocate(cache, needed_size, 8, da_info); } else { SpinMutexLock l(&fallback_mutex); AllocatorCache *cache = &fallback_allocator_cache; - allocated = allocator.Allocate(cache, needed_size, 8); + allocated = allocator.Allocate(cache, needed_size, 8, da_info); } if (UNLIKELY(!allocated)) { SetAllocatorOutOfMemory(); @@ -1378,3 +1383,162 @@ int __asan_update_allocation_context(void* addr) { GET_STACK_TRACE_MALLOC; return instance.UpdateAllocationStack((uptr)addr, &stack); } + +#if SANITIZER_AMDGPU +DECLARE_REAL(hsa_status_t, hsa_amd_agents_allow_access, uint32_t num_agents, + const hsa_agent_t *agents, const uint32_t *flags, const void *ptr) +DECLARE_REAL(hsa_status_t, hsa_amd_memory_pool_allocate, + hsa_amd_memory_pool_t memory_pool, size_t size, uint32_t flags, + void **ptr) +DECLARE_REAL(hsa_status_t, hsa_amd_memory_pool_free, void *ptr) +DECLARE_REAL(hsa_status_t, hsa_amd_ipc_memory_create, void *ptr, size_t len, + hsa_amd_ipc_memory_t *handle) +DECLARE_REAL(hsa_status_t, hsa_amd_ipc_memory_attach, + const hsa_amd_ipc_memory_t *handle, size_t len, uint32_t num_agents, + const hsa_agent_t *mapping_agents, void **mapped_ptr) +DECLARE_REAL(hsa_status_t, hsa_amd_ipc_memory_detach, void *mapped_ptr) +DECLARE_REAL(hsa_status_t, hsa_amd_vmem_address_reserve_align, void** ptr, + size_t size, uint64_t address, uint64_t alignment, uint64_t flags) +DECLARE_REAL(hsa_status_t, hsa_amd_vmem_address_free, void* ptr, size_t size); + +namespace __asan { + +// Always align to page boundary to match current ROCr behavior +static const size_t kPageSize_ = 4096; + +hsa_status_t asan_hsa_amd_memory_pool_allocate( + hsa_amd_memory_pool_t memory_pool, size_t size, uint32_t flags, void **ptr, + BufferedStackTrace *stack) { + AmdgpuAllocationInfo aa_info; + aa_info.alloc_func = + reinterpret_cast(asan_hsa_amd_memory_pool_allocate); + aa_info.memory_pool = memory_pool; + aa_info.size = size; + aa_info.flags = flags; + aa_info.ptr = nullptr; + SetErrnoOnNull(*ptr = instance.Allocate(size, kPageSize_, stack, + FROM_MALLOC, false, &aa_info)); + return aa_info.status; +} + +hsa_status_t asan_hsa_amd_memory_pool_free( + void *ptr, + BufferedStackTrace *stack) { + void *p = get_allocator().GetBlockBegin(ptr); + if (p) { + instance.Deallocate(ptr, 0, 0, stack, FROM_MALLOC); + return HSA_STATUS_SUCCESS; + } + return REAL(hsa_amd_memory_pool_free)(ptr); +} + +hsa_status_t asan_hsa_amd_agents_allow_access( + uint32_t num_agents, const hsa_agent_t *agents, const uint32_t *flags, + const void *ptr, + BufferedStackTrace *stack) { + void *p = get_allocator().GetBlockBegin(ptr); + return REAL(hsa_amd_agents_allow_access)(num_agents, agents, flags, + p ? p : ptr); +} + +// For asan allocator, kMetadataSize is 0 and maximum redzone size is 2048. This +// implies for device allocation, the gap between user_beg and GetBlockBegin() +// is always one kPageSize_ +// IPC calls use static_assert to make sure kMetadataSize = 0 +// +#if SANITIZER_CAN_USE_ALLOCATOR64 +static struct AP64 AP_; +#else +static struct AP32 AP_; +#endif + +hsa_status_t asan_hsa_amd_ipc_memory_create(void *ptr, size_t len, + hsa_amd_ipc_memory_t * handle) { + void *ptr_; + size_t len_ = get_allocator().GetActuallyAllocatedSize(ptr); + if (len_) { + static_assert(AP_.kMetadataSize == 0, "Expression below requires this"); + ptr_ = reinterpret_cast(reinterpret_cast(ptr) - kPageSize_); + } else { + ptr_ = ptr; + len_ = len; + } + return REAL(hsa_amd_ipc_memory_create)(ptr_, len_, handle); +} + +hsa_status_t asan_hsa_amd_ipc_memory_attach(const hsa_amd_ipc_memory_t *handle, + size_t len, uint32_t num_agents, const hsa_agent_t *mapping_agents, + void **mapped_ptr) { + static_assert(AP_.kMetadataSize == 0, "Expression below requires this"); + size_t len_ = len + kPageSize_; + hsa_status_t status = REAL(hsa_amd_ipc_memory_attach)( + handle, len_, num_agents, mapping_agents, mapped_ptr); + if (status == HSA_STATUS_SUCCESS && mapped_ptr) { + *mapped_ptr = reinterpret_cast(reinterpret_cast(*mapped_ptr) + + kPageSize_); + } + return status; +} + +hsa_status_t asan_hsa_amd_ipc_memory_detach(void *mapped_ptr) { + static_assert(AP_.kMetadataSize == 0, "Expression below requires this"); + void *mapped_ptr_ = + reinterpret_cast(reinterpret_cast(mapped_ptr) - kPageSize_); + return REAL(hsa_amd_ipc_memory_detach)(mapped_ptr_); +} + +hsa_status_t asan_hsa_amd_vmem_address_reserve_align( + void** ptr, size_t size, uint64_t address, uint64_t alignment, + uint64_t flags, BufferedStackTrace* stack) { + // Bypass the tracking for a fixed address since it cannot be supported. + // Reasons: + // 1. Address may not meet the alignment/page-size requirement. + // 2. Requested range overlaps an existing reserved/mapped range. + // 3. Insufficient VA space to honor that exact placement. + if (address) + return REAL(hsa_amd_vmem_address_reserve_align)(ptr, size, address, + alignment, flags); + + if (alignment < kPageSize_) + alignment = kPageSize_; + + if (UNLIKELY(!IsPowerOfTwo(alignment))) { + errno = errno_EINVAL; + return HSA_STATUS_ERROR_INVALID_ARGUMENT; + } + + AmdgpuAllocationInfo aa_info; + aa_info.alloc_func = + reinterpret_cast(asan_hsa_amd_vmem_address_reserve_align); + aa_info.memory_pool = {0}; + aa_info.size = size; + aa_info.flags64 = flags; + aa_info.address = 0; + aa_info.alignment = alignment; + aa_info.ptr = nullptr; + SetErrnoOnNull(*ptr = instance.Allocate(size, alignment, stack, FROM_MALLOC, + false, &aa_info)); + + return aa_info.status; +} + +hsa_status_t asan_hsa_amd_vmem_address_free(void* ptr, size_t size, + BufferedStackTrace* stack) { + if (UNLIKELY(!IsAligned(reinterpret_cast(ptr), kPageSize_))) { + errno = errno_EINVAL; + return HSA_STATUS_ERROR_INVALID_ARGUMENT; + } + if (size == 0) { + errno = errno_EINVAL; + return HSA_STATUS_ERROR_INVALID_ARGUMENT; + } + + void* p = get_allocator().GetBlockBegin(ptr); + if (p) { + instance.Deallocate(ptr, 0, 0, stack, FROM_MALLOC); + return HSA_STATUS_SUCCESS; + } + return REAL(hsa_amd_vmem_address_free)(ptr, size); +} +} // namespace __asan +#endif diff --git a/compiler-rt/lib/asan/asan_allocator.h b/compiler-rt/lib/asan/asan_allocator.h index fdf456473fb02..ced10f62b7a58 100644 --- a/compiler-rt/lib/asan/asan_allocator.h +++ b/compiler-rt/lib/asan/asan_allocator.h @@ -311,4 +311,37 @@ void PrintInternalAllocatorStats(); void AsanSoftRssLimitExceededCallback(bool exceeded); } // namespace __asan + +#if SANITIZER_AMDGPU +#include +#include + +namespace __asan { +hsa_status_t asan_hsa_amd_memory_pool_allocate( + hsa_amd_memory_pool_t memory_pool, size_t size, uint32_t flags, void **ptr, + BufferedStackTrace *stack); +hsa_status_t asan_hsa_amd_memory_pool_free( + void *ptr, + BufferedStackTrace *stack); +hsa_status_t asan_hsa_amd_agents_allow_access( + uint32_t num_agents, const hsa_agent_t *agents, const uint32_t *flags, + const void *ptr, + BufferedStackTrace *stack); +hsa_status_t asan_hsa_amd_ipc_memory_create( + void* ptr, size_t len, hsa_amd_ipc_memory_t* handle); +hsa_status_t asan_hsa_amd_ipc_memory_attach( + const hsa_amd_ipc_memory_t* handle, size_t len, uint32_t num_agents, + const hsa_agent_t* mapping_agents, void** mapped_ptr); +hsa_status_t asan_hsa_amd_ipc_memory_detach( + void* mapped_ptr); +hsa_status_t asan_hsa_amd_vmem_address_reserve_align(void** ptr, size_t size, + uint64_t address, + uint64_t alignment, + uint64_t flags, + BufferedStackTrace* stack); +hsa_status_t asan_hsa_amd_vmem_address_free(void* ptr, size_t size, + BufferedStackTrace* stack); +} // namespace __asan +#endif + #endif // ASAN_ALLOCATOR_H diff --git a/compiler-rt/lib/asan/asan_descriptions.cpp b/compiler-rt/lib/asan/asan_descriptions.cpp index 18c2a6c571c1f..cee1321d30543 100644 --- a/compiler-rt/lib/asan/asan_descriptions.cpp +++ b/compiler-rt/lib/asan/asan_descriptions.cpp @@ -411,7 +411,7 @@ void StackAddressDescription::Print() const { DescribeThread(GetThreadContextByTidLocked(tid)); } -void HeapAddressDescription::Print() const { +void HeapAddressDescription::Print(bool nonself) const { PrintHeapChunkAccess(addr, chunk_access); asanThreadRegistry().CheckLocked(); @@ -433,7 +433,8 @@ void HeapAddressDescription::Print() const { AsanThreadIdAndName(alloc_thread).c_str(), d.Default()); } alloc_stack.Print(); - DescribeThread(GetCurrentThread()); + if (!nonself) + DescribeThread(GetCurrentThread()); if (free_thread) DescribeThread(free_thread); DescribeThread(alloc_thread); } diff --git a/compiler-rt/lib/asan/asan_descriptions.h b/compiler-rt/lib/asan/asan_descriptions.h index a614f47d461bb..f209756f90995 100644 --- a/compiler-rt/lib/asan/asan_descriptions.h +++ b/compiler-rt/lib/asan/asan_descriptions.h @@ -123,7 +123,7 @@ struct HeapAddressDescription { u32 free_stack_id; ChunkAccess chunk_access; - void Print() const; + void Print(bool nonself = false) const; }; bool GetHeapAddressInformation(uptr addr, uptr access_size, @@ -228,7 +228,7 @@ class AddressDescription { } UNREACHABLE("AddressInformation kind is invalid"); } - void Print(const char *bug_descr = nullptr) const { + void Print(const char *bug_descr = nullptr, bool nonself = false) const { switch (data.kind) { case kAddressKindWild: data.wild.Print(); @@ -236,7 +236,7 @@ class AddressDescription { case kAddressKindShadow: return data.shadow.Print(); case kAddressKindHeap: - return data.heap.Print(); + return data.heap.Print(nonself); case kAddressKindStack: return data.stack.Print(); case kAddressKindGlobal: diff --git a/compiler-rt/lib/asan/asan_errors.cpp b/compiler-rt/lib/asan/asan_errors.cpp index 2a207cd06ccac..5f4b839cf2412 100644 --- a/compiler-rt/lib/asan/asan_errors.cpp +++ b/compiler-rt/lib/asan/asan_errors.cpp @@ -18,6 +18,7 @@ #include "asan_poisoning.h" #include "asan_report.h" #include "asan_stack.h" +#include "sanitizer_common/sanitizer_file.h" #include "sanitizer_common/sanitizer_stackdepot.h" namespace __asan { @@ -412,13 +413,10 @@ static bool AdjacentShadowValuesAreFullyPoisoned(u8 *s) { return s[-1] > 127 && s[1] > 127; } -ErrorGeneric::ErrorGeneric(u32 tid, uptr pc_, uptr bp_, uptr sp_, uptr addr, - bool is_write_, uptr access_size_) +ErrorGenericBase::ErrorGenericBase(u32 tid, uptr addr, bool is_write_, + uptr access_size_) : ErrorBase(tid), addr_description(addr, access_size_, /*shouldLockThreadRegistry=*/false), - pc(pc_), - bp(bp_), - sp(sp_), access_size(access_size_), is_write(is_write_), shadow_val(0) { @@ -513,6 +511,13 @@ ErrorGeneric::ErrorGeneric(u32 tid, uptr pc_, uptr bp_, uptr sp_, uptr addr, } } +ErrorGeneric::ErrorGeneric(u32 tid, uptr pc_, uptr bp_, uptr sp_, uptr addr, + bool is_write_, uptr access_size_) + : ErrorGenericBase(tid, addr, is_write_, access_size_), + pc(pc_), + bp(bp_), + sp(sp_) {} + static void PrintContainerOverflowHint() { Printf("HINT: if you don't care about these errors you may set " "ASAN_OPTIONS=detect_container_overflow=0.\n" @@ -668,4 +673,179 @@ void ErrorGeneric::Print() { CheckPoisonRecords(addr); } +ErrorNonSelfGeneric::ErrorNonSelfGeneric(uptr *callstack_, u32 n_callstack, + uptr *addrs, u32 n_addrs, + u64 *threadids, u32 n_threads, + bool is_write, u32 access_size, + int fd_, s64 vm_adj, u64 off_, u64 sz_) + : ErrorGenericBase(kInvalidTid, addrs[0], is_write, access_size), + cb_loc(fd_, vm_adj, off_, sz_) { + for (u64 i = 0; i < Min(addr_count, n_addrs); i++) addresses[i] = addrs[i]; + for (u64 i = 0; i < Min(threads_count, n_threads); i++) + thread_id[i] = threadids[i]; + for (u64 i = 0; i < Min(maxcs_depth, n_callstack); i++) + callstack[i] = callstack_[i]; +} + +void ErrorNonSelfGeneric::Print() { + Decorator d; + Printf("%s", d.Error()); + Report("ERROR: AddressSanitizer: %s on address %p at pc %p\n", bug_descr, + (void *)addresses[0], (void *)callstack[0]); + + Printf("%s%s of size %zu at %p thread id %zu\n", d.Access(), + access_size ? (is_write ? "WRITE" : "READ") : "ACCESS", access_size, + (void *)addresses[0], (usize)thread_id[0]); + + // todo: perform symbolization for the given callstack + // can be done by creating in-memory object file or by writing + // data to a temporary file or by findng the filepath by following + // /proc/PID/fd + Printf("%s", d.Default()); + Printf("AddressSanitizer cannot provide additional information!\n"); + PrintShadowMemoryForAddress(addresses[0]); +} + +ErrorNonSelfAMDGPU::ErrorNonSelfAMDGPU(uptr *dev_callstack, u32 n_callstack, + uptr *dev_address, u32 n_addrs, + u64 *wi_ids, u32 n_wi, bool is_write_, + u32 access_size_, int fd_, s64 vm_adj, + u64 file_start_, u64 file_size_) + : ErrorGenericBase(kInvalidTid, dev_address[0], is_write_, access_size_), + cb_loc(fd_, vm_adj, file_start_, file_size_), + wg(), + nactive_threads(n_addrs), + device_id(0) { + if (nactive_threads > wavesize) + nactive_threads = wavesize; + + callstack[0] = dev_callstack[0]; + device_id = wi_ids[0]; + wg.idx = wi_ids[1]; + wg.idy = wi_ids[2]; + wg.idz = wi_ids[3]; + wi_ids += 4; + for (u64 i = 0; i < nactive_threads; i++) { + device_address[i] = dev_address[i]; + workitem_ids[i] = wi_ids[i]; + } +} + +void ErrorNonSelfAMDGPU::PrintStack() { + InternalScopedString source_location; + source_location.AppendF(" #0 %p", (void *)callstack[0]); +#if SANITIZER_AMDGPU + source_location.Append(" in "); + __sanitizer::AMDGPUCodeObjectSymbolizer symbolizer; + symbolizer.Init(cb_loc.fd, cb_loc.offset, cb_loc.size); + symbolizer.SymbolizePC(callstack[0] - cb_loc.vma_adjust, source_location); + // release all allocated comgr objects. + symbolizer.Release(); +#endif + Printf("%s", source_location.data()); +} + +void ErrorNonSelfAMDGPU::PrintThreadsAndAddresses() { + InternalScopedString str; + str.Append("Thread ids and accessed addresses:\n"); + for (u32 idx = 0, per_row_count = 0; idx < nactive_threads; idx++) { + // print 8 threads per row. + if (per_row_count == 8) { + str.Append("\n"); + per_row_count = 0; + } + str.AppendF("%02d : %p ", (int)workitem_ids[idx], + (void *)device_address[idx]); + per_row_count++; + } + str.Append("\n"); + Printf("%s\n", str.data()); +} + +static uptr ScanForMagicDown(uptr start, uptr lo, uptr magic0, uptr magic1) { + for (uptr p = start; p >= lo; p -= sizeof(uptr)) { + if (((uptr*)p)[0] == magic0 && ((uptr*)p)[1] == magic1) + return p; + } + return 0; +} + +static uptr ScanForMagicUp(uptr start, uptr hi, uptr magic0, uptr magic1) { + for (uptr p = start; p < hi; p += sizeof(uptr)) { + if (((uptr*)p)[0] == magic0 && ((uptr*)p)[1] == magic1) + return p; + } + return 0; +} + +void ErrorNonSelfAMDGPU::PrintMallocStack() { + // Facts about asan malloc on device + const uptr magic = static_cast(0xfedcba1ee1abcdefULL); + const uptr offset = 32; + const uptr min_chunk_size = 96; + const uptr min_alloc_size = 48; + + Decorator d; + HeapAddressDescription addr_description; + + if (GetHeapAddressInformation(device_address[0], access_size, + &addr_description) && + addr_description.chunk_access.chunk_size >= min_chunk_size) { + uptr lo = addr_description.chunk_access.chunk_begin; + uptr hi = lo + addr_description.chunk_access.chunk_size - min_alloc_size; + uptr start = RoundDownTo(device_address[0], sizeof(uptr)); + + uptr plo = ScanForMagicDown(start, lo, magic, lo); + if (plo) { + callstack[0] = ((uptr*)plo)[2]; + Printf( + "%s%p is %u bytes above an address from a %sdevice malloc " + "(or free) call of size %u from%s\n", + d.Location(), (void *)device_address[0], + (u32)(device_address[0] - (plo + offset)), d.Allocation(), + ((u32*)plo)[7], d.Default()); + // TODO: The code object with the malloc call may not be the same + // code object trying the illegal access. A mechanism is needed + // to obtain the former. + PrintStack(); + } + + uptr phi = ScanForMagicUp(start, hi, magic, lo); + if (phi) { + callstack[0] = ((uptr*)phi)[2]; + Printf( + "%s%p is %u bytes below an address from a %sdevice malloc " + "(or free) call of size %u from%s\n", + d.Location(), (void *)device_address[0], + (u32)((phi + offset) - device_address[0]), + + d.Allocation(), ((u32*)phi)[7], d.Default()); + PrintStack(); + } + } +} + +void ErrorNonSelfAMDGPU::Print() { + Decorator d; + Printf("%s", d.Error()); + Report("ERROR: AddressSanitizer: %s on amdgpu device %d at pc %p\n", + bug_descr, device_id, (void *)callstack[0]); + Printf("%s%s of size %zu in workgroup id (%llu,%llu,%llu)\n", d.Access(), + (is_write ? "WRITE" : "READ"), access_size, wg.idx, + wg.idy, wg.idz); + Printf("%s", d.Default()); + PrintStack(); + Printf("%s", d.Location()); + PrintThreadsAndAddresses(); + Printf("%s", d.Default()); + if (shadow_val == kAsanHeapFreeMagic || + shadow_val == kAsanHeapLeftRedzoneMagic || + shadow_val == kAsanArrayCookieMagic) { + PrintMallocStack(); + } + addr_description.Print(bug_descr, true); + Printf("%s", d.Default()); + // print shadow memory region for single address + PrintShadowMemoryForAddress(device_address[0]); +} } // namespace __asan diff --git a/compiler-rt/lib/asan/asan_errors.h b/compiler-rt/lib/asan/asan_errors.h index f339b35d2a764..282aa817e23ad 100644 --- a/compiler-rt/lib/asan/asan_errors.h +++ b/compiler-rt/lib/asan/asan_errors.h @@ -16,6 +16,7 @@ #include "asan_descriptions.h" #include "asan_scariness_score.h" #include "sanitizer_common/sanitizer_common.h" +#include "sanitizer_common/sanitizer_symbolizer_amdgpu.h" namespace __asan { @@ -403,20 +404,93 @@ struct ErrorInvalidPointerPair : ErrorBase { void Print(); }; -struct ErrorGeneric : ErrorBase { +struct ErrorGenericBase : ErrorBase { AddressDescription addr_description; - uptr pc, bp, sp; uptr access_size; - const char *bug_descr; bool is_write; u8 shadow_val; + const char *bug_descr; + ErrorGenericBase() = default; // (*) + ErrorGenericBase(u32 tid, uptr addr_, bool is_write_, uptr access_size_); +}; +struct ErrorGeneric : ErrorGenericBase { + uptr pc, bp, sp; ErrorGeneric() = default; // (*) ErrorGeneric(u32 tid, uptr pc_, uptr bp_, uptr sp_, uptr addr, bool is_write_, uptr access_size_); void Print(); }; +// codeobject location for non-self error types. +struct CodeObjectLocation { + int fd; + s64 vma_adjust; + u64 offset, size; + CodeObjectLocation() = default; + CodeObjectLocation(int fd_, s64 vma_adjust_, u64 offset_, u64 size_) + : fd(fd_), vma_adjust(vma_adjust_), offset(offset_), size(size_) {} +}; + +// NonSelf Generic Error can be used to report +// an error triggered by cpu thread that compiler-rt is not aware of +struct ErrorNonSelfGeneric : ErrorGenericBase { + CodeObjectLocation cb_loc; + // At present, we assume one thread triggered the error + static constexpr u32 threads_count = 1; + static constexpr u32 addr_count = 1; + static constexpr u32 maxcs_depth = 1; + + uptr addresses[addr_count]; + u64 thread_id[threads_count]; + uptr callstack[maxcs_depth]; + + ErrorNonSelfGeneric() = default; + ErrorNonSelfGeneric(uptr *callstack_, u32 n_callstack, uptr *addrs, + u32 n_addrs, u64 *threadids, u32 n_threads, bool is_write, + u32 access_size, int fd_, s64 vm_adj, u64 off_, u64 sz_); + void Print(); +}; + +// AMDGPU Device Generic Error +// Represents an invaid memory access made by a single amdgpu wave-front +// Todo: abstract amdgpu related info into a base classes in case of +// multiple error types for AMDGPU +struct ErrorNonSelfAMDGPU : ErrorGenericBase { + CodeObjectLocation cb_loc; + // amdgpu wave-front can have atmost 64 active threads + static constexpr u32 wavesize = 64; + uptr device_address[wavesize]; + // currently we don't support callstack of depth > 1 + static constexpr u32 maxcs_depth = 1; + uptr callstack[maxcs_depth]; + + struct workgroup_id { + u64 idx, idy, idz; + workgroup_id() = default; + workgroup_id(u64 idx_, u64 idy_, u64 idz_) + : idx(idx_), idy(idy_), idz(idz_) {} + } wg; + u64 workitem_ids[wavesize]; + u32 nactive_threads; + int device_id; + + ErrorNonSelfAMDGPU() = default; + ErrorNonSelfAMDGPU(uptr *dev_callstack, u32 n_callstack, uptr *dev_address, + u32 n_addrs, u64 *wi_ids, u32 n_wi, bool is_write_, + u32 access_size_, int fd_, s64 vm_adj, u64 file_start_, + u64 file_size_); + void Print(); + + // error type identifying key + static constexpr const char *key = "amdgpu"; + + private: + void PrintStack(); + void PrintThreadsAndAddresses(); + void PrintMallocStack(); +}; + // clang-format off #define ASAN_FOR_EACH_ERROR_KIND(macro) \ macro(DeadlySignal) \ @@ -442,7 +516,9 @@ struct ErrorGeneric : ErrorBase { macro(BadParamsToCopyContiguousContainerAnnotations) \ macro(ODRViolation) \ macro(InvalidPointerPair) \ - macro(Generic) + macro(Generic) \ + macro(NonSelfGeneric) \ + macro(NonSelfAMDGPU) // clang-format on #define ASAN_DEFINE_ERROR_KIND(name) kErrorKind##name, diff --git a/compiler-rt/lib/asan/asan_globals.cpp b/compiler-rt/lib/asan/asan_globals.cpp index c83b782cb85f8..68999510f6e6a 100644 --- a/compiler-rt/lib/asan/asan_globals.cpp +++ b/compiler-rt/lib/asan/asan_globals.cpp @@ -172,12 +172,28 @@ static u32 FindRegistrationSite(const Global *g) { return 0; } +#if SANITIZER_AMDGPU +static bool IsValidGlobal(const Global *g) { + return + *(u8 *)MEM_TO_SHADOW((uptr)g) == kAsanGlobalRedzoneMagic && + *(u8 *)MEM_TO_SHADOW((uptr)g + sizeof(__asan_global) - sizeof(uptr)) + == kAsanGlobalRedzoneMagic && + g->size < g->size_with_redzone && + g->has_dynamic_init < 2 && + g->beg < kHighMemEnd; +} +#endif + int GetGlobalsForAddress(uptr addr, Global *globals, u32 *reg_sites, int max_globals) { if (!flags()->report_globals) return 0; Lock lock(&mu_for_globals); int res = 0; for (const auto &l : list_of_all_globals) { +#if SANITIZER_AMDGPU + if (!IsValidGlobal(l.g)) + continue; +#endif const Global &g = *l.g; if (flags()->report_globals >= 2) ReportGlobal(g, "Search"); diff --git a/compiler-rt/lib/asan/asan_interceptors.cpp b/compiler-rt/lib/asan/asan_interceptors.cpp index 8643271e89d70..0951a77b1b93e 100644 --- a/compiler-rt/lib/asan/asan_interceptors.cpp +++ b/compiler-rt/lib/asan/asan_interceptors.cpp @@ -142,6 +142,7 @@ DECLARE_REAL_AND_INTERCEPTOR(void, free, void *) if (flags()->strict_init_order) \ StopInitOrderChecking(); \ CheckNoDeepBind(filename, flag); \ + PatchHsaRuntimeDlopenFlag(filename, flag); \ REAL(dlopen)(filename, flag); \ }) # define COMMON_INTERCEPTOR_ON_EXIT(ctx) OnExit() @@ -828,6 +829,147 @@ DEFINE_REAL(int, vfork,) DECLARE_EXTERN_INTERCEPTOR_AND_WRAPPER(int, vfork,) #endif +#if SANITIZER_AMDGPU +void ENSURE_HSA_INITED(); + +INTERCEPTOR(hsa_status_t, hsa_amd_memory_pool_allocate, + hsa_amd_memory_pool_t memory_pool, size_t size, uint32_t flags, void **ptr) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + GET_STACK_TRACE_MALLOC; + return asan_hsa_amd_memory_pool_allocate(memory_pool, size, flags, ptr, + &stack); +} + +INTERCEPTOR(hsa_status_t, hsa_amd_memory_pool_free, void *ptr) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + GET_STACK_TRACE_FREE; + return asan_hsa_amd_memory_pool_free(ptr, &stack); +} + +INTERCEPTOR(hsa_status_t, hsa_amd_agents_allow_access, uint32_t num_agents, + const hsa_agent_t *agents, const uint32_t *flags, const void *ptr) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + GET_STACK_TRACE_FREE; + return asan_hsa_amd_agents_allow_access(num_agents, agents, flags, ptr, + &stack); +} + +INTERCEPTOR(hsa_status_t, hsa_memory_copy, void *dst, const void *src, + size_t size) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + if (flags()->replace_intrin) { + if (dst != src) { + CHECK_RANGES_OVERLAP("hsa_memory_copy", dst, size, src, size); + } + ASAN_READ_RANGE(nullptr, src, size); + ASAN_WRITE_RANGE(nullptr, dst, size); + } + return REAL(hsa_memory_copy)(dst, src, size); +} + +INTERCEPTOR(hsa_status_t, hsa_amd_memory_async_copy, void* dst, + hsa_agent_t dst_agent, const void* src, hsa_agent_t src_agent, size_t size, + uint32_t num_dep_signals, const hsa_signal_t* dep_signals, + hsa_signal_t completion_signal) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + if (flags()->replace_intrin) { + if (dst != src) { + CHECK_RANGES_OVERLAP("hsa_amd_memory_async_copy", dst, size, src, size); + } + ASAN_READ_RANGE(nullptr, src, size); + ASAN_WRITE_RANGE(nullptr, dst, size); + } + return REAL(hsa_amd_memory_async_copy)(dst, dst_agent, src, src_agent, size, + num_dep_signals, dep_signals, completion_signal); +} + +#if HSA_AMD_INTERFACE_VERSION_MINOR>=1 +INTERCEPTOR(hsa_status_t, hsa_amd_memory_async_copy_on_engine, void* dst, + hsa_agent_t dst_agent, const void* src, hsa_agent_t src_agent, size_t size, + uint32_t num_dep_signals, const hsa_signal_t* dep_signals, + hsa_signal_t completion_signal, hsa_amd_sdma_engine_id_t engine_id, + bool force_copy_on_sdma) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + if (flags()->replace_intrin) { + if (dst != src) { + CHECK_RANGES_OVERLAP("hsa_amd_memory_async_copy_on_engine", dst, size, + src, size); + } + ASAN_READ_RANGE(nullptr, src, size); + ASAN_WRITE_RANGE(nullptr, dst, size); + } + return REAL(hsa_amd_memory_async_copy_on_engine)( + dst, dst_agent, src, src_agent, size, num_dep_signals, dep_signals, + completion_signal, engine_id, force_copy_on_sdma); +} +#endif + +INTERCEPTOR(hsa_status_t, hsa_amd_ipc_memory_create, void* ptr, size_t len, + hsa_amd_ipc_memory_t* handle) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + return asan_hsa_amd_ipc_memory_create(ptr, len, handle); +} + +INTERCEPTOR(hsa_status_t, hsa_amd_ipc_memory_attach, + const hsa_amd_ipc_memory_t* handle, size_t len, uint32_t num_agents, + const hsa_agent_t* mapping_agents, void** mapped_ptr) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + return asan_hsa_amd_ipc_memory_attach(handle, len, num_agents, mapping_agents, + mapped_ptr); +} + +INTERCEPTOR(hsa_status_t, hsa_amd_ipc_memory_detach, void* mapped_ptr) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + return asan_hsa_amd_ipc_memory_detach(mapped_ptr); +} + +INTERCEPTOR(hsa_status_t, hsa_amd_vmem_address_reserve_align, void** ptr, + size_t size, uint64_t address, uint64_t alignment, uint64_t flags) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + GET_STACK_TRACE_MALLOC; + return asan_hsa_amd_vmem_address_reserve_align(ptr, size, address, alignment, + flags, &stack); +} + +INTERCEPTOR(hsa_status_t, hsa_amd_vmem_address_free, void* ptr, size_t size) { + AsanInitFromRtl(); + ENSURE_HSA_INITED(); + GET_STACK_TRACE_FREE; + return asan_hsa_amd_vmem_address_free(ptr, size, &stack); +} + +void InitializeAmdgpuInterceptors() { + ASAN_INTERCEPT_FUNC(hsa_memory_copy); + ASAN_INTERCEPT_FUNC(hsa_amd_memory_pool_allocate); + ASAN_INTERCEPT_FUNC(hsa_amd_memory_pool_free); + ASAN_INTERCEPT_FUNC(hsa_amd_agents_allow_access); + ASAN_INTERCEPT_FUNC(hsa_amd_memory_async_copy); +#if HSA_AMD_INTERFACE_VERSION_MINOR>=1 + ASAN_INTERCEPT_FUNC(hsa_amd_memory_async_copy_on_engine); +#endif + ASAN_INTERCEPT_FUNC(hsa_amd_ipc_memory_create); + ASAN_INTERCEPT_FUNC(hsa_amd_ipc_memory_attach); + ASAN_INTERCEPT_FUNC(hsa_amd_ipc_memory_detach); + ASAN_INTERCEPT_FUNC(hsa_amd_vmem_address_reserve_align); + ASAN_INTERCEPT_FUNC(hsa_amd_vmem_address_free); +} + +void ENSURE_HSA_INITED() { + if (!REAL(hsa_memory_copy)) + InitializeAmdgpuInterceptors(); +} +#endif + // ---------------------- InitializeAsanInterceptors ---------------- {{{1 namespace __asan { void InitializeAsanInterceptors() { @@ -942,6 +1084,12 @@ void InitializeAsanInterceptors() { ASAN_INTERCEPT_FUNC(vfork); #endif +#if SANITIZER_AMDGPU + InitializeAmdgpuInterceptors(); +#endif + + InitializePlatformInterceptors(); + VReport(1, "AddressSanitizer: libc interceptors initialized\n"); } diff --git a/compiler-rt/lib/asan/asan_interface.inc b/compiler-rt/lib/asan/asan_interface.inc index bfc44b4619623..06b1cb6ed117d 100644 --- a/compiler-rt/lib/asan/asan_interface.inc +++ b/compiler-rt/lib/asan/asan_interface.inc @@ -184,6 +184,7 @@ INTERFACE_FUNCTION(__sanitizer_unaligned_store16) INTERFACE_FUNCTION(__sanitizer_unaligned_store32) INTERFACE_FUNCTION(__sanitizer_unaligned_store64) INTERFACE_FUNCTION(__asan_update_allocation_context) +INTERFACE_FUNCTION(__asan_report_nonself_error) INTERFACE_WEAK_FUNCTION(__asan_default_options) INTERFACE_WEAK_FUNCTION(__asan_default_suppressions) INTERFACE_WEAK_FUNCTION(__asan_on_error) diff --git a/compiler-rt/lib/asan/asan_report.cpp b/compiler-rt/lib/asan/asan_report.cpp index e049a21e4e16d..ec3846dd21ea5 100644 --- a/compiler-rt/lib/asan/asan_report.cpp +++ b/compiler-rt/lib/asan/asan_report.cpp @@ -125,8 +125,9 @@ bool ParseFrameDescription(const char *frame_descr, // immediately after printing error report. class ScopedInErrorReport { public: - explicit ScopedInErrorReport(bool fatal = false) - : halt_on_error_(fatal || flags()->halt_on_error) { + explicit ScopedInErrorReport(bool fatal = false, bool nonself = false) + : halt_on_error_(fatal || flags()->halt_on_error), + nonself_report_(nonself) { // Deadlock Prevention Between ASan and LSan // // Background: @@ -171,8 +172,10 @@ class ScopedInErrorReport { ASAN_ON_ERROR(); if (current_error_.IsValid()) current_error_.Print(); - // Make sure the current thread is announced. - DescribeThread(GetCurrentThread()); + if (!nonself_report_) + // Make sure the current thread is announced. + DescribeThread(GetCurrentThread()); + // We may want to grab this lock again when printing stats. asanThreadRegistry().Unlock(); // Print memory stats. @@ -238,6 +241,9 @@ class ScopedInErrorReport { // with the debugger and point it to an error description. static ErrorDescription current_error_; bool halt_on_error_; + // used to control logging specific information when non-self entity is + // reporting + bool nonself_report_; }; ErrorDescription ScopedInErrorReport::current_error_(LINKER_INITIALIZED); @@ -535,6 +541,34 @@ void ReportGenericError(uptr pc, uptr bp, uptr sp, uptr addr, bool is_write, in_report.ReportError(error); } +void ReportNonselfError(uptr *nonself_callstack, u32 n_nonself_callstack, + uptr *nonself_addrs, u32 n_nonself_addrs, + u64 *nonself_tids, u32 n_nonself_tids, bool is_write, + u32 access_size, bool is_abort, + const char *nonself_name, s64 nonself_vma_adjust, + int nonself_fd, u64 nonself_file_extent_size, + u64 nonself_file_extent_start) { + ScopedInErrorReport in_report(is_abort, true); + // delegate to amdgpu error handler + if (!internal_strcmp(ErrorNonSelfAMDGPU::key, nonself_name)) { + ErrorNonSelfAMDGPU amdgpu_wavefront_error( + nonself_callstack, n_nonself_callstack, nonself_addrs, n_nonself_addrs, + nonself_tids, n_nonself_tids, (bool)is_write, access_size, nonself_fd, + nonself_vma_adjust, nonself_file_extent_start, + nonself_file_extent_size); + in_report.ReportError(amdgpu_wavefront_error); + } + // default fallback + else { + ErrorNonSelfGeneric error_val( + nonself_callstack, n_nonself_callstack, nonself_addrs, n_nonself_addrs, + nonself_tids, n_nonself_tids, (bool)is_write, access_size, nonself_fd, + nonself_vma_adjust, nonself_file_extent_start, + nonself_file_extent_size); + in_report.ReportError(error_val); + } +} + } // namespace __asan // --------------------------- Interface --------------------- {{{1 diff --git a/compiler-rt/lib/asan/asan_report.h b/compiler-rt/lib/asan/asan_report.h index 3143d83abe390..466a2dee21f1c 100644 --- a/compiler-rt/lib/asan/asan_report.h +++ b/compiler-rt/lib/asan/asan_report.h @@ -103,5 +103,15 @@ void ReportMacCfReallocUnknown(uptr addr, uptr zone_ptr, const char *zone_name, BufferedStackTrace *stack); +// Interface to report errors and warnings by nonself threads +// executing in the environment. Needed cpu threads can also submit a report. +void ReportNonselfError(uptr *nonself_callstack, u32 n_nonself_callstack, + uptr *nonself_addrs, u32 n_nonself_addrs, + u64 *nonself_tids, u32 n_nonself_tids, bool is_write, + u32 access_size, bool is_abort, + const char *nonself_name, s64 nonself_vma_adjust, + int nonself_fd, u64 nonself_file_extent_size, + u64 nonself_file_extent_start); + } // namespace __asan #endif // ASAN_REPORT_H diff --git a/compiler-rt/lib/asan/asan_rtl.cpp b/compiler-rt/lib/asan/asan_rtl.cpp index b9ba250f5bcd7..6cd5a91fb41ff 100644 --- a/compiler-rt/lib/asan/asan_rtl.cpp +++ b/compiler-rt/lib/asan/asan_rtl.cpp @@ -247,6 +247,43 @@ void __asan_storeN_noabort(uptr addr, uptr size) { } } +// This interface enables to report an error that is triggered in a +// thread of execution that the compiler-rt doesn't have information about +// heterogeneous devices such as GPUs, FGPAs can be call this function to +// report violations. +// @param nonself_callstack - pointer to a array of callstack pointers +// @param n_nonself_callstack - depth of callstack +// @param nonself_addrs - pointer to the array of addresses +// whose access is defined by instrumentation as invalid +// @param n_nonself_addrs - number of such addresses +// @param nonself_tids - pointer to the array identifying the +// reporting entity. +// @param n_nonself_tids - length of the identity +// @param is_write - access type +// @param access_size - access size +// @param is_abort - flag to abort the execution +// @param nonself_name - c string literal describing the non self +// entity +// @param nonself_adjust_vma - difference between actual load address +// and VA specified in object. +// @param nonself_fd - posix file handle to the object code (-1 +// if not applicable) +// @param nonself_file_extent_size - file size (0 if not applicable) +// @param nonself_file_extent_start - file offset (0 if not applicable) +// +extern "C" NOINLINE INTERFACE_ATTRIBUTE void __asan_report_nonself_error( + uptr *nonself_callstack, u32 n_nonself_callstack, uptr *nonself_addrs, + u32 n_nonself_addrs, u64 *nonself_tids, u32 n_nonself_tids, bool is_write, + u32 access_size, bool is_abort, const char *nonself_name, + s64 nonself_adjust_vma, int nonself_fd, u64 nonself_file_extent_size, + u64 nonself_file_extent_start = /*default*/ 0) { + ReportNonselfError(nonself_callstack, n_nonself_callstack, nonself_addrs, + n_nonself_addrs, nonself_tids, n_nonself_tids, is_write, + access_size, is_abort, nonself_name, nonself_adjust_vma, + nonself_fd, nonself_file_extent_size, + nonself_file_extent_start); +} + // Force the linker to keep the symbols for various ASan interface functions. // We want to keep those in the executable in order to let the instrumented // dynamic libraries access the symbol even if it is not used by the executable @@ -309,6 +346,8 @@ static NOINLINE void force_interface_symbols() { case 50: __asan_set_shadow_f3(0, 0); break; case 51: __asan_set_shadow_f5(0, 0); break; case 52: __asan_set_shadow_f8(0, 0); break; + case 53: __asan_report_nonself_error(0,0,0,0,0,0,0,0,0, + 0,0,0,0,0); break; } // clang-format on } diff --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt index 6c226aa7d2d48..74b56899904d1 100644 --- a/compiler-rt/lib/builtins/CMakeLists.txt +++ b/compiler-rt/lib/builtins/CMakeLists.txt @@ -845,7 +845,6 @@ if (APPLE) darwin_add_builtin_libraries(${BUILTIN_SUPPORTED_OS}) else () set(BUILTIN_CFLAGS "") - add_security_warnings(BUILTIN_CFLAGS 0) if (COMPILER_RT_HAS_FCF_PROTECTION_FLAG) append_list_if(COMPILER_RT_ENABLE_CET -fcf-protection=full BUILTIN_CFLAGS) diff --git a/compiler-rt/lib/builtins/eprintf.c b/compiler-rt/lib/builtins/eprintf.c index daf90b4993eca..89fb0e315b2ee 100644 --- a/compiler-rt/lib/builtins/eprintf.c +++ b/compiler-rt/lib/builtins/eprintf.c @@ -15,7 +15,6 @@ // // It should never be exported from a dylib, so it is marked // visibility hidden. -#ifndef DONT_DEFINE_EPRINTF #ifndef _WIN32 __attribute__((visibility("hidden"))) #endif @@ -26,4 +25,3 @@ __eprintf(const char *format, const char *assertion_expression, fflush(stderr); compilerrt_abort(); } -#endif diff --git a/compiler-rt/lib/profile/InstrProfiling.c b/compiler-rt/lib/profile/InstrProfiling.c index da04d8ebdec95..9b8dc72925b87 100644 --- a/compiler-rt/lib/profile/InstrProfiling.c +++ b/compiler-rt/lib/profile/InstrProfiling.c @@ -79,11 +79,11 @@ COMPILER_RT_VISIBILITY void __llvm_profile_reset_counters(void) { CurrentVSiteCount += DI->NumValueSites[VKI]; for (i = 0; i < CurrentVSiteCount; ++i) { - ValueProfNode *CurrVNode = ValueCounters[i]; + ValueProfNode *CurrentVNode = ValueCounters[i]; - while (CurrVNode) { - CurrVNode->Count = 0; - CurrVNode = CurrVNode->Next; + while (CurrentVNode) { + CurrentVNode->Count = 0; + CurrentVNode = CurrentVNode->Next; } } } diff --git a/compiler-rt/lib/sanitizer_common/CMakeLists.txt b/compiler-rt/lib/sanitizer_common/CMakeLists.txt index 6e6dfd2f33ebf..d0bb2255405bd 100644 --- a/compiler-rt/lib/sanitizer_common/CMakeLists.txt +++ b/compiler-rt/lib/sanitizer_common/CMakeLists.txt @@ -3,6 +3,7 @@ set(SANITIZER_SOURCES_NOTERMINATION sanitizer_allocator.cpp + sanitizer_allocator_amdgpu.cpp sanitizer_common.cpp sanitizer_deadlock_detector1.cpp sanitizer_deadlock_detector2.cpp @@ -87,6 +88,7 @@ set(SANITIZER_SYMBOLIZER_SOURCES sanitizer_stacktrace_printer.cpp sanitizer_stacktrace_sparc.cpp sanitizer_symbolizer.cpp + sanitizer_symbolizer_amdgpu.cpp sanitizer_symbolizer_libbacktrace.cpp sanitizer_symbolizer_libcdep.cpp sanitizer_symbolizer_mac.cpp @@ -192,6 +194,7 @@ set(SANITIZER_IMPL_HEADERS sanitizer_stoptheworld.h sanitizer_suppressions.h sanitizer_symbolizer.h + sanitizer_symbolizer_amdgpu.h sanitizer_symbolizer_markup_constants.h sanitizer_symbolizer_internal.h sanitizer_symbolizer_libbacktrace.h diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_allocator.h b/compiler-rt/lib/sanitizer_common/sanitizer_allocator.h index 0b28f86d14084..77e4c22714f0b 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_allocator.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_allocator.h @@ -24,6 +24,11 @@ #include "sanitizer_procmaps.h" #include "sanitizer_type_traits.h" +#if SANITIZER_AMDGPU +#include +#include +#endif + namespace __sanitizer { // Allows the tools to name their allocations appropriately. @@ -75,6 +80,7 @@ struct NoOpMapUnmapCallback { #include "sanitizer_allocator_primary32.h" #include "sanitizer_allocator_local_cache.h" #include "sanitizer_allocator_secondary.h" +#include "sanitizer_allocator_device.h" #include "sanitizer_allocator_combined.h" bool IsRssLimitExceeded(); diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_allocator_amdgpu.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_allocator_amdgpu.cpp new file mode 100755 index 0000000000000..cf10cb773e746 --- /dev/null +++ b/compiler-rt/lib/sanitizer_common/sanitizer_allocator_amdgpu.cpp @@ -0,0 +1,108 @@ +//===-- sanitizer_allocator_amdgpu.cpp --------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Part of the Sanitizer Allocator. +// +//===----------------------------------------------------------------------===// +#if SANITIZER_AMDGPU +# include // For dlsym +# include "sanitizer_allocator.h" + +namespace __sanitizer { +struct HsaMemoryFunctions { + hsa_status_t (*memory_pool_allocate)(hsa_amd_memory_pool_t memory_pool, + size_t size, uint32_t flags, void **ptr); + hsa_status_t (*memory_pool_free)(void *ptr); + hsa_status_t (*pointer_info)(void *ptr, hsa_amd_pointer_info_t *info, + void *(*alloc)(size_t), + uint32_t *num_agents_accessible, + hsa_agent_t **accessible); + hsa_status_t (*vmem_address_reserve_align)(void** ptr, size_t size, + uint64_t address, + uint64_t alignment, + uint64_t flags); + hsa_status_t (*vmem_address_free)(void* ptr, size_t size); +}; + +static HsaMemoryFunctions hsa_amd; + +// Always align to page boundary to match current ROCr behavior +static const size_t kPageSize_ = 4096; + +bool AmdgpuMemFuncs::Init() { + hsa_amd.memory_pool_allocate = + (decltype(hsa_amd.memory_pool_allocate))dlsym( + RTLD_NEXT, "hsa_amd_memory_pool_allocate"); + hsa_amd.memory_pool_free = (decltype(hsa_amd.memory_pool_free))dlsym( + RTLD_NEXT, "hsa_amd_memory_pool_free"); + hsa_amd.pointer_info = (decltype(hsa_amd.pointer_info))dlsym( + RTLD_NEXT, "hsa_amd_pointer_info"); + hsa_amd.vmem_address_reserve_align = + (decltype(hsa_amd.vmem_address_reserve_align))dlsym( + RTLD_NEXT, "hsa_amd_vmem_address_reserve_align"); + hsa_amd.vmem_address_free = (decltype(hsa_amd.vmem_address_free))dlsym( + RTLD_NEXT, "hsa_amd_vmem_address_free"); + if (!hsa_amd.memory_pool_allocate || !hsa_amd.memory_pool_free || + !hsa_amd.pointer_info || !hsa_amd.vmem_address_reserve_align || + !hsa_amd.vmem_address_free) + return false; + return true; +} + +void *AmdgpuMemFuncs::Allocate(uptr size, uptr alignment, + DeviceAllocationInfo *da_info) { + AmdgpuAllocationInfo *aa_info = + reinterpret_cast(da_info); + if (!aa_info->memory_pool.handle) { + aa_info->status = hsa_amd.vmem_address_reserve_align( + &aa_info->ptr, size, aa_info->address, aa_info->alignment, + aa_info->flags64); + } else { + aa_info->status = hsa_amd.memory_pool_allocate( + aa_info->memory_pool, size, aa_info->flags, &aa_info->ptr); + } + if (aa_info->status != HSA_STATUS_SUCCESS) + return nullptr; + + return aa_info->ptr; +} + +void AmdgpuMemFuncs::Deallocate(void *p) { + DevicePointerInfo DevPtrInfo; + if (AmdgpuMemFuncs::GetPointerInfo(reinterpret_cast(p), &DevPtrInfo)) { + if (DevPtrInfo.type == HSA_EXT_POINTER_TYPE_HSA) { + UNUSED hsa_status_t status = hsa_amd.memory_pool_free(p); + } else if (DevPtrInfo.type == HSA_EXT_POINTER_TYPE_RESERVED_ADDR) { + UNUSED hsa_status_t status = + hsa_amd.vmem_address_free(p, DevPtrInfo.map_size); + } + } +} + +bool AmdgpuMemFuncs::GetPointerInfo(uptr ptr, DevicePointerInfo* ptr_info) { + hsa_amd_pointer_info_t info; + info.size = sizeof(hsa_amd_pointer_info_t); + hsa_status_t status = + hsa_amd.pointer_info(reinterpret_cast(ptr), &info, 0, 0, 0); + + if (status != HSA_STATUS_SUCCESS) + return false; + + if (info.type == HSA_EXT_POINTER_TYPE_RESERVED_ADDR) + ptr_info->map_beg = reinterpret_cast(info.hostBaseAddress); + else if (info.type == HSA_EXT_POINTER_TYPE_HSA) + ptr_info->map_beg = reinterpret_cast(info.agentBaseAddress); + ptr_info->map_size = info.sizeInBytes; + ptr_info->type = reinterpret_cast(info.type); + + return true; +} + +uptr AmdgpuMemFuncs::GetPageSize() { return kPageSize_; } +} // namespace __sanitizer +#endif // SANITIZER_AMDGPU diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_allocator_amdgpu.h b/compiler-rt/lib/sanitizer_common/sanitizer_allocator_amdgpu.h new file mode 100755 index 0000000000000..84b62964e5145 --- /dev/null +++ b/compiler-rt/lib/sanitizer_common/sanitizer_allocator_amdgpu.h @@ -0,0 +1,42 @@ +//===-- sanitizer_allocator_amdgpu.h ----------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Part of the Sanitizer Allocator. +// +//===----------------------------------------------------------------------===// +#ifndef SANITIZER_ALLOCATOR_H +# error This file must be included inside sanitizer_allocator_device.h +#endif + +#if SANITIZER_AMDGPU +class AmdgpuMemFuncs { + public: + static bool Init(); + static void *Allocate(uptr size, uptr alignment, + DeviceAllocationInfo *da_info); + static void Deallocate(void *p); + static bool GetPointerInfo(uptr ptr, DevicePointerInfo* ptr_info); + static uptr GetPageSize(); +}; + +struct AmdgpuAllocationInfo : public DeviceAllocationInfo { + AmdgpuAllocationInfo() : DeviceAllocationInfo(DAT_AMDGPU) { + status = HSA_STATUS_SUCCESS; + alloc_func = nullptr; + } + hsa_status_t status; + void *alloc_func; + hsa_amd_memory_pool_t memory_pool; + u64 alignment; + u64 address; + u64 flags64; + usize size; + u32 flags; + void *ptr; +}; +#endif // SANITIZER_AMDGPU diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_allocator_combined.h b/compiler-rt/lib/sanitizer_common/sanitizer_allocator_combined.h old mode 100644 new mode 100755 index 49940d9b5d505..d03e5f0435493 --- a/compiler-rt/lib/sanitizer_common/sanitizer_allocator_combined.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_allocator_combined.h @@ -28,20 +28,33 @@ class CombinedAllocator { LargeMmapAllocator; +#if SANITIZER_AMDGPU + using DeviceAllocator = + DeviceAllocatorT; +#endif void InitLinkerInitialized(s32 release_to_os_interval_ms, - uptr heap_start = 0) { + uptr heap_start = 0, + bool enable_device_allocator = false) { primary_.Init(release_to_os_interval_ms, heap_start); secondary_.InitLinkerInitialized(); +#if SANITIZER_AMDGPU + device_.Init(enable_device_allocator, primary_.kMetadataSize); +#endif } - void Init(s32 release_to_os_interval_ms, uptr heap_start = 0) { + void Init(s32 release_to_os_interval_ms, uptr heap_start = 0, + bool enable_device_allocator = false) { stats_.Init(); primary_.Init(release_to_os_interval_ms, heap_start); secondary_.Init(); +#if SANITIZER_AMDGPU + device_.Init(enable_device_allocator, primary_.kMetadataSize); +#endif } - void *Allocate(AllocatorCache *cache, uptr size, uptr alignment) { + void *Allocate(AllocatorCache *cache, uptr size, uptr alignment, + DeviceAllocationInfo *da_info = nullptr) { // Returning 0 on malloc(0) may break a lot of code. if (size == 0) size = 1; @@ -65,6 +78,11 @@ class CombinedAllocator { // alignment without such requirement, and allocating 'size' would use // extraneous memory, so we employ 'original_size'. void *res; +#if SANITIZER_AMDGPU + if (da_info) + res = device_.Allocate(&stats_, original_size, alignment, da_info); + else +#endif if (primary_.CanAllocate(size, alignment)) res = cache->Allocate(&primary_, primary_.ClassID(size)); else @@ -90,8 +108,12 @@ class CombinedAllocator { if (!p) return; if (primary_.PointerIsMine(p)) cache->Deallocate(&primary_, primary_.GetSizeClass(p), p); - else + else if (secondary_.PointerIsMine(p)) secondary_.Deallocate(&stats_, p); +#if SANITIZER_AMDGPU + else if (device_.PointerIsMine(p)) + device_.Deallocate(&stats_, p); +#endif } void *Reallocate(AllocatorCache *cache, void *p, uptr new_size, @@ -115,7 +137,13 @@ class CombinedAllocator { bool PointerIsMine(const void *p) const { if (primary_.PointerIsMine(p)) return true; - return secondary_.PointerIsMine(p); + if (secondary_.PointerIsMine(p)) + return true; +#if SANITIZER_AMDGPU + if (device_.PointerIsMine(p)) + return true; +#endif + return false; } bool FromPrimary(const void *p) const { return primary_.PointerIsMine(p); } @@ -123,31 +151,60 @@ class CombinedAllocator { void *GetMetaData(const void *p) { if (primary_.PointerIsMine(p)) return primary_.GetMetaData(p); - return secondary_.GetMetaData(p); + if (secondary_.PointerIsMine(p)) + return secondary_.GetMetaData(p); +#if SANITIZER_AMDGPU + if (device_.PointerIsMine(p)) + return device_.GetMetaData(p); +#endif + return nullptr; } void *GetBlockBegin(const void *p) { if (primary_.PointerIsMine(p)) return primary_.GetBlockBegin(p); - return secondary_.GetBlockBegin(p); + if (secondary_.PointerIsMine(p)) + return secondary_.GetBlockBegin(p); +#if SANITIZER_AMDGPU + if (device_.PointerIsMine(p)) + return device_.GetBlockBegin(p); +#endif + return nullptr; } // This function does the same as GetBlockBegin, but is much faster. // Must be called with the allocator locked. void *GetBlockBeginFastLocked(const void *p) { + void *beg; if (primary_.PointerIsMine(p)) return primary_.GetBlockBegin(p); - return secondary_.GetBlockBeginFastLocked(p); + if ((beg = secondary_.GetBlockBeginFastLocked(p))) + return beg; +#if SANITIZER_AMDGPU + if ((beg = device_.GetBlockBeginFastLocked(p))) + return beg; +#endif + return nullptr; } uptr GetActuallyAllocatedSize(void *p) { if (primary_.PointerIsMine(p)) return primary_.GetActuallyAllocatedSize(p); - return secondary_.GetActuallyAllocatedSize(p); + if (secondary_.PointerIsMine(p)) + return secondary_.GetActuallyAllocatedSize(p); +#if SANITIZER_AMDGPU + if (device_.PointerIsMine(p)) + return device_.GetActuallyAllocatedSize(p); +#endif + return 0; } uptr TotalMemoryUsed() { - return primary_.TotalMemoryUsed() + secondary_.TotalMemoryUsed(); + return primary_.TotalMemoryUsed() + secondary_.TotalMemoryUsed() +#if SANITIZER_AMDGPU + + device_.TotalMemoryUsed() +#endif + ; } void TestOnlyUnmap() { primary_.TestOnlyUnmap(); } @@ -171,11 +228,17 @@ class CombinedAllocator { void PrintStats() { primary_.PrintStats(); secondary_.PrintStats(); +#if SANITIZER_AMDGPU + device_.PrintStats(); +#endif } // ForceLock() and ForceUnlock() are needed to implement Darwin malloc zone // introspection API. void ForceLock() SANITIZER_NO_THREAD_SAFETY_ANALYSIS { +#if SANITIZER_AMDGPU + device_.ForceLock(); +#endif primary_.ForceLock(); secondary_.ForceLock(); } @@ -183,6 +246,9 @@ class CombinedAllocator { void ForceUnlock() SANITIZER_NO_THREAD_SAFETY_ANALYSIS { secondary_.ForceUnlock(); primary_.ForceUnlock(); +#if SANITIZER_AMDGPU + device_.ForceUnlock(); +#endif } // Iterate over all existing chunks. @@ -190,10 +256,16 @@ class CombinedAllocator { void ForEachChunk(ForEachChunkCallback callback, void *arg) { primary_.ForEachChunk(callback, arg); secondary_.ForEachChunk(callback, arg); +#if SANITIZER_AMDGPU + device_.ForEachChunk(callback, arg); +#endif } private: PrimaryAllocator primary_; SecondaryAllocator secondary_; +#if SANITIZER_AMDGPU + DeviceAllocator device_; +#endif AllocatorGlobalStats stats_; }; diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_allocator_device.h b/compiler-rt/lib/sanitizer_common/sanitizer_allocator_device.h new file mode 100755 index 0000000000000..f76800da79ac3 --- /dev/null +++ b/compiler-rt/lib/sanitizer_common/sanitizer_allocator_device.h @@ -0,0 +1,347 @@ +//===-- sanitizer_allocator_device.h ----------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Part of the Sanitizer Allocator. +// +//===----------------------------------------------------------------------===// +#ifndef SANITIZER_ALLOCATOR_H +# error This file must be included inside sanitizer_allocator.h +#endif + +struct DeviceAllocationInfo; +#if SANITIZER_AMDGPU +// Device memory allocation usually requires additional information, we can put +// all the additional information into a data structure DeviceAllocationInfo. +// This is only a parent structure since different vendors may require +// different allocation info. +typedef enum { + DAT_UNKNOWN = 0, + DAT_AMDGPU = 1, +} DeviceAllocationType; + +struct DeviceAllocationInfo { + DeviceAllocationInfo(DeviceAllocationType type = DAT_UNKNOWN) { + type_ = type; + } + DeviceAllocationType type_; +}; + +struct DevicePointerInfo { + u64 type; + uptr map_beg; + uptr map_size; +}; + +#include "sanitizer_allocator_amdgpu.h" + +template +class DeviceAllocatorT { + public: + using PtrArrayT = DefaultLargeMmapAllocatorPtrArray; + using DeviceMemFuncs = AmdgpuMemFuncs; + + void Init(bool enable, uptr kMetadataSize) { + internal_memset(this, 0, sizeof(*this)); + enabled_ = enable; + if (!enable) + return; + kMetadataSize_ = kMetadataSize; + chunks_ = reinterpret_cast(ptr_array_.Init()); + InitMemFuncs(); + } + + void *Allocate(AllocatorStats *stat, uptr size, uptr alignment, + DeviceAllocationInfo *da_info) { + if (!da_info || !InitMemFuncs()) + return nullptr; + + // Allocate an extra page for Metadata + if (kMetadataSize_ + (size % page_size_) > page_size_) { + size += page_size_; + } + CHECK(IsPowerOfTwo(alignment)); + uptr map_size = RoundUpMapSize(size); + if (alignment > page_size_) + map_size += alignment; + // Overflow. + if (map_size < size) { + Report( + "WARNING: %s: DeviceAllocator allocation overflow: " + "0x%zx bytes with 0x%zx alignment requested\n", + SanitizerToolName, map_size, alignment); + return nullptr; + } + void *ptr = DeviceMemFuncs::Allocate(map_size, alignment, da_info); + if (!ptr) + return nullptr; + uptr map_beg = reinterpret_cast(ptr); + CHECK(IsAligned(map_beg, page_size_)); + MapUnmapCallback().OnMap(map_beg, map_size); + uptr map_end = map_beg + map_size; + uptr res = map_beg; + if (res & (alignment - 1)) // Align. + res += alignment - (res & (alignment - 1)); + CHECK(IsAligned(res, alignment)); + CHECK(IsAligned(res, page_size_)); + CHECK_GE(res + size, map_beg); + CHECK_LE(res + size, map_end); + uptr size_log = MostSignificantSetBitIndex(map_size); + CHECK_LT(size_log, ARRAY_SIZE(stats.by_size_log)); + { + SpinMutexLock l(&mutex_); + ptr_array_.EnsureSpace(n_chunks_); + uptr idx = n_chunks_++; + chunks_[idx] = map_beg; + chunks_sorted_ = false; + stats.n_allocs++; + stats.currently_allocated += map_size; + stats.max_allocated = Max(stats.max_allocated, stats.currently_allocated); + stats.by_size_log[size_log]++; + stat->Add(AllocatorStatAllocated, map_size); + stat->Add(AllocatorStatMapped, map_size); + } + return reinterpret_cast(res); + } + + void Deallocate(AllocatorStats *stat, void *p) { + Header header, *h; + { + SpinMutexLock l(&mutex_); + uptr idx; + uptr p_ = reinterpret_cast(p); + EnsureSortedChunks(); // Avoid doing the sort while iterating. + for (idx = 0; idx < n_chunks_; idx++) { + if (chunks_[idx] >= p_) + break; + } + CHECK_EQ(chunks_[idx], p_); + CHECK_LT(idx, n_chunks_); + h = GetHeader(chunks_[idx], &header); + CHECK(!dev_runtime_unloaded_); + chunks_[idx] = chunks_[--n_chunks_]; + chunks_sorted_ = false; + stats.n_frees++; + stats.currently_allocated -= h->map_size; + stat->Sub(AllocatorStatAllocated, h->map_size); + stat->Sub(AllocatorStatMapped, h->map_size); + } + MapUnmapCallback().OnUnmap(h->map_beg, h->map_size); + DeviceMemFuncs::Deallocate(p); + } + + uptr TotalMemoryUsed() { + Header header; + SpinMutexLock l(&mutex_); + uptr res = 0; + for (uptr i = 0; i < n_chunks_; i++) { + Header *h = GetHeader(chunks_[i], &header); + CHECK(!dev_runtime_unloaded_); + res += RoundUpMapSize(h->map_size); + } + return res; + } + + bool PointerIsMine(const void *p) const { + return GetBlockBegin(p) != nullptr; + } + + uptr GetActuallyAllocatedSize(void *p) { + Header header; + uptr p_ = reinterpret_cast(p); + Header *h = GetHeaderAnyPointer(p_, &header); + return h ? h->map_size : 0; + } + + void *GetMetaData(const void *p) { + Header header; + uptr p_ = reinterpret_cast(p); + Header *h = GetHeaderAnyPointer(p_, &header); + return h ? reinterpret_cast(h->map_beg + h->map_size - + kMetadataSize_) + : nullptr; + } + + void* GetBlockBegin(const void* ptr) const { + Header header; + if (!mem_funcs_inited_) return nullptr; + uptr p = reinterpret_cast(ptr); + SpinMutexLock l(&mutex_); + uptr nearest_chunk = 0; + // Cache-friendly linear search. + for (uptr i = 0; i < n_chunks_; i++) { + uptr ch = chunks_[i]; + if (p < ch) + continue; // p is at left to this chunk, skip it. + if (p - ch < p - nearest_chunk) + nearest_chunk = ch; + } + if (!nearest_chunk) + return nullptr; + if (p != nearest_chunk) { + Header* h = GetHeader(nearest_chunk, &header); + CHECK_GE(nearest_chunk, h->map_beg); + CHECK_LT(nearest_chunk, h->map_beg + h->map_size); + CHECK_LE(nearest_chunk, p); + if (h->map_beg + h->map_size <= p) { + CHECK(!dev_runtime_unloaded_); + return nullptr; + } + } + return GetUser(nearest_chunk); + } + + void EnsureSortedChunks() { + if (chunks_sorted_) + return; + Sort(reinterpret_cast(chunks_), n_chunks_); + chunks_sorted_ = true; + } + + // This function does the same as GetBlockBegin, but is much faster. + // Must be called with the allocator locked. + void *GetBlockBeginFastLocked(const void *ptr) { + if (!mem_funcs_inited_) return nullptr; + mutex_.CheckLocked(); + uptr p = reinterpret_cast(ptr); + uptr n = n_chunks_; + if (!n) return nullptr; + EnsureSortedChunks(); + Header header, *h; + h = GetHeader(chunks_[n - 1], &header); + uptr min_mmap_ = chunks_[0]; + uptr max_mmap_ = chunks_[n - 1] + h->map_size; + if (p < min_mmap_) + return nullptr; + if (p >= max_mmap_) { + // TODO (bingma): If dev_runtime_unloaded_ = true, map_size is limited + // to one page and we might miss a valid 'ptr'. If we hit cases where + // this kind of miss is unacceptable, we will need to implement a full + // solution with higher cost + return nullptr; + } + uptr beg = 0, end = n - 1; + // This loop is a log(n) lower_bound. It does not check for the exact match + // to avoid expensive cache-thrashing loads. + while (end - beg >= 2) { + uptr mid = (beg + end) / 2; // Invariant: mid >= beg + 1 + if (p < chunks_[mid]) + end = mid - 1; // We are not interested in chunks[mid]. + else + beg = mid; // chunks[mid] may still be what we want. + } + + if (beg < end) { + CHECK_EQ(beg + 1, end); + // There are 2 chunks left, choose one. + if (p >= chunks_[end]) + beg = end; + } + + if (p != chunks_[beg]) { + h = GetHeader(chunks_[beg], &header); + CHECK_NE(h, nullptr); + if (p < h->map_beg) + return nullptr; + if (h->map_beg + h->map_size <= p) { + // TODO (bingma): See above TODO in this function + return nullptr; + } + } + return GetUser(chunks_[beg]); + } + + void PrintStats() { + Printf("Stats: DeviceAllocator: allocated %zd times, " + "remains %zd (%zd K) max %zd M; by size logs: ", + stats.n_allocs, stats.n_allocs - stats.n_frees, + stats.currently_allocated >> 10, stats.max_allocated >> 20); + for (uptr i = 0; i < ARRAY_SIZE(stats.by_size_log); i++) { + uptr c = stats.by_size_log[i]; + if (!c) continue; + Printf("%zd:%zd; ", i, c); + } + Printf("\n"); + } + + // ForceLock() and ForceUnlock() are needed to implement Darwin malloc zone + // introspection API. + void ForceLock() SANITIZER_ACQUIRE(mutex_) { mutex_.Lock(); } + + void ForceUnlock() SANITIZER_RELEASE(mutex_) { mutex_.Unlock(); } + + // Iterate over all existing chunks. + // The allocator must be locked when calling this function. + void ForEachChunk(ForEachChunkCallback callback, void *arg) { + EnsureSortedChunks(); // Avoid doing the sort while iterating. + for (uptr i = 0; i < n_chunks_; i++) { + const uptr t = chunks_[i]; + callback(t, arg); + // Consistency check: verify that the array did not change. + CHECK_EQ(chunks_[i], t); + } + } + + private: + bool InitMemFuncs() { + if (!enabled_ || mem_funcs_inited_ || mem_funcs_init_count_ >= 2) { + return mem_funcs_inited_; + } + mem_funcs_inited_ = DeviceMemFuncs::Init(); + mem_funcs_init_count_++; + if (mem_funcs_inited_) + page_size_ = DeviceMemFuncs::GetPageSize(); + return mem_funcs_inited_; + } + + typedef DevicePointerInfo Header; + + Header *GetHeaderAnyPointer(uptr p, Header* h) const { + CHECK(IsAligned(p, page_size_)); + return DeviceMemFuncs::GetPointerInfo(p, h) ? h : nullptr; + } + + Header* GetHeader(uptr chunk, Header* h) const { + if (dev_runtime_unloaded_ || !DeviceMemFuncs::GetPointerInfo(chunk, h)) { + // Device allocator has dependency on device runtime. If device runtime + // is unloaded, GetPointerInfo() will fail. For such case, we can still + // return a valid value for map_beg, map_size will be limited to one page + h->map_beg = chunk; + h->map_size = page_size_; + dev_runtime_unloaded_ = true; + } + return h; + } + + void *GetUser(const uptr ptr) const { + return reinterpret_cast(ptr); + } + + uptr RoundUpMapSize(uptr size) { + return RoundUpTo(size, page_size_) + page_size_; + } + + bool enabled_; + bool mem_funcs_inited_; + mutable bool dev_runtime_unloaded_; + // Maximum of mem_funcs_init_count_ is 2: + // 1. The initial init called from Init(...), it could fail if + // libhsa-runtime64.so is dynamically loaded with dlopen() + // 2. A potential deferred init called by Allocate(...) + u32 mem_funcs_init_count_; + uptr kMetadataSize_; + uptr page_size_; + uptr *chunks_; + PtrArrayT ptr_array_; + uptr n_chunks_; + bool chunks_sorted_; + struct Stats { + uptr n_allocs, n_frees, currently_allocated, max_allocated, by_size_log[64]; + } stats; + mutable StaticSpinMutex mutex_; +}; +#endif // SANITIZER_AMDGPU diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_asm.h b/compiler-rt/lib/sanitizer_common/sanitizer_asm.h index 30e9d15184e5d..25bdd3a3e8042 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_asm.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_asm.h @@ -148,9 +148,13 @@ #define NO_EXEC_STACK_DIRECTIVE #endif -#if (defined(__x86_64__) || defined(__i386__)) && defined(__has_include) && __has_include() +#if defined(__x86_64__) || defined(__i386__) +#if defined(__has_include) +#if __has_include() #include #endif +#endif #ifndef _CET_ENDBR #define _CET_ENDBR #endif +#endif diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common.h b/compiler-rt/lib/sanitizer_common/sanitizer_common.h index ba85a0eb5a35e..aa2a3220f1613 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_common.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common.h @@ -1076,6 +1076,11 @@ struct StackDepotStats { const s32 kReleaseToOSIntervalNever = -1; void CheckNoDeepBind(const char *filename, int flag); +#if SANITIZER_AMDGPU +void PatchHsaRuntimeDlopenFlag(const char *filename, int &flag); +#else +inline void PatchHsaRuntimeDlopenFlag(const char *filename, int &flag) {} +#endif // Returns the requested amount of random data (up to 256 bytes) that can then // be used to seed a PRNG. Defaults to blocking like the underlying syscall. diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp index 87a18b1120af6..529f7d07dc4bd 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp @@ -2824,6 +2824,22 @@ void CheckNoDeepBind(const char *filename, int flag) { # endif } +#if SANITIZER_AMDGPU +void PatchHsaRuntimeDlopenFlag(const char *filename, int &flag) { + if (filename && (internal_strstr(filename, "libamdhip64.so") || + internal_strstr(filename, "libhsa-runtime64.so") || + internal_strstr(filename, "libamdocl64.so")) && !(flag & RTLD_GLOBAL)) { + flag |= RTLD_GLOBAL; + if (Verbosity() >= 2) { + Printf( + "RTLD_GLOBAL flag on dlopen call forced on for %s due to AMDGPU " + "device sanitizer runtime requirements.\n", + filename); + } + } +} +#endif + uptr FindAvailableMemoryRange(uptr size, uptr alignment, uptr left_padding, uptr *largest_gap_found, uptr *max_occupied_addr) { diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp index 8e5e87938c372..e27d8167f4fea 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp @@ -209,7 +209,18 @@ void UnsetAlternateSignalStack() { altstack.ss_flags = SS_DISABLE; altstack.ss_size = GetAltStackSize(); // Some sane value required on Darwin. CHECK_EQ(0, sigaltstack(&altstack, &oldstack)); +#if SANITIZER_AMDGPU + // If oldstack size is different from the one we allocated early on, the + // stack is not allocated by us and we shouldn't free it here. + // This is not a bulletproof solution because the stack could be allocated by + // other components with the same size and we shouldn't free it either. + // A complete solution should tag or register the stack pointer when it is + // allocated and only free stack when we can be sure the pointer is ours. + if (oldstack.ss_size == altstack.ss_size) + UnmapOrDie(oldstack.ss_sp, oldstack.ss_size); +#else UnmapOrDie(oldstack.ss_sp, oldstack.ss_size); +#endif } bool IsSignalHandlerFromSanitizer(int signum) { diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_amdgpu.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_amdgpu.cpp new file mode 100644 index 0000000000000..39506a6a3c693 --- /dev/null +++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_amdgpu.cpp @@ -0,0 +1,104 @@ +//===-- sanitizer_symbolizer_amdgpu.cpp -------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// + +#if SANITIZER_AMDGPU +# include "sanitizer_symbolizer_amdgpu.h" + +# include //For dlsym + +namespace __sanitizer { + +static COMgrFunctions comgr = {false}; + +void getSourceLocation(const char *Result, void *ScopedString) { + InternalScopedString *ScopedStringObj = (InternalScopedString *)ScopedString; + ScopedStringObj->Append(Result); +} + +void AMDGPUCodeObjectSymbolizer::InitCOMgr() { + if (!comgr.inited_) { + comgr.create_data = + (decltype(comgr.create_data))dlsym(RTLD_NEXT, "amd_comgr_create_data"); + comgr.set_data = + (decltype(comgr.set_data))dlsym(RTLD_NEXT, "amd_comgr_set_data"); + comgr.set_data_from_file_slice = + (decltype(comgr.set_data_from_file_slice))dlsym( + RTLD_NEXT, "amd_comgr_set_data_from_file_slice"); + comgr.create_symbolizer = (decltype(comgr.create_symbolizer))dlsym( + RTLD_NEXT, "amd_comgr_create_symbolizer_info"); + comgr.symbolize = + (decltype(comgr.symbolize))dlsym(RTLD_NEXT, "amd_comgr_symbolize"); + comgr.destroy_symbolizer = (decltype(comgr.destroy_symbolizer))dlsym( + RTLD_NEXT, "amd_comgr_destroy_symbolizer_info"); + comgr.release_data = (decltype(comgr.release_data))dlsym( + RTLD_NEXT, "amd_comgr_release_data"); + + comgr.inited_ = comgr.create_data && comgr.set_data && + comgr.set_data_from_file_slice && comgr.create_symbolizer && + comgr.symbolize && comgr.destroy_symbolizer && + comgr.release_data; + } +} + +void AMDGPUCodeObjectSymbolizer::Init(int fd, uint64_t off, uint64_t size) { + InitCOMgr(); + if (comgr.inited_) { + if (comgr.create_data(AMD_COMGR_DATA_KIND_EXECUTABLE, &codeobject)) + return; + + object_cnt = comgr_objects::data; + + if (fd != -1) { + if (comgr.set_data_from_file_slice(codeobject, fd, off, size)) { + Release(); + return; + } + } else { + if (comgr.set_data(codeobject, size, off)) { + Release(); + return; + } + } + + if (comgr.create_symbolizer(codeobject, &getSourceLocation, &symbolizer)) { + Release(); + return; + } + + object_cnt = comgr_objects::data_and_symb; + init = true; + } +} + +bool AMDGPUCodeObjectSymbolizer::SymbolizePC(uptr addr, + InternalScopedString &source_loc) { + if (!init) + return false; + comgr.symbolize(symbolizer, addr, true, (void *)&source_loc); + return true; +} + +void AMDGPUCodeObjectSymbolizer::Release() { + // fall-through is avoided to silence warnings. + switch (object_cnt) { + case comgr_objects::data_and_symb: { + comgr.destroy_symbolizer(symbolizer); + comgr.release_data(codeobject); + break; + } + case comgr_objects::data: { + comgr.release_data(codeobject); + break; + } + default: { + } + } +} +} // namespace __sanitizer +#endif diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_amdgpu.h b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_amdgpu.h new file mode 100644 index 0000000000000..196804a8af1f1 --- /dev/null +++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_amdgpu.h @@ -0,0 +1,63 @@ +//===-- sanitizer_symbolizer_amdgpu.h -------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// + +#ifndef SANITIZER_SYMBOLIZER_AMDGPU_H +#define SANITIZER_SYMBOLIZER_AMDGPU_H + +#if SANITIZER_AMDGPU +# include "sanitizer_common.h" +# include "sanitizer_symbolizer_internal.h" +# if __has_include("amd_comgr.h.in") +# include "amd_comgr.h.in" +# elif __has_include("amd_comgr.h") +# include "amd_comgr.h" +# else +# error "No amd_comgr.h/amd_comgr header found!" +# endif + +namespace __sanitizer { + +struct COMgrFunctions { + bool inited_; + amd_comgr_status_t (*create_data)(amd_comgr_data_kind_t data_type, + amd_comgr_data_t *data_handle); + amd_comgr_status_t (*set_data)(amd_comgr_data_t data_handle, uint64_t size, + uint64_t offset); + amd_comgr_status_t (*set_data_from_file_slice)(amd_comgr_data_t data_handle, + int fd, uint64_t offset, + uint64_t size); + amd_comgr_status_t (*create_symbolizer)( + amd_comgr_data_t object_handle, void (*callback)(const char *, void *), + amd_comgr_symbolizer_info_t *symbolizer_object); + amd_comgr_status_t (*symbolize)(amd_comgr_symbolizer_info_t symbolizer_handle, + uint64_t addr, bool iscode, void *data); + amd_comgr_status_t (*destroy_symbolizer)( + amd_comgr_symbolizer_info_t symbolizer_handle); + amd_comgr_status_t (*release_data)(amd_comgr_data_t data_handle); +}; + +// Symbolizer for AMDGPU CodeObject. +class AMDGPUCodeObjectSymbolizer { + public: + AMDGPUCodeObjectSymbolizer() : object_cnt(comgr_objects::no_objs) {} + + void Init(int fd, uint64_t offset, uint64_t size); + bool SymbolizePC(uptr addr, InternalScopedString &source_loc); + void Release(); + + private: + void InitCOMgr(); + amd_comgr_data_t codeobject; + amd_comgr_symbolizer_info_t symbolizer; + enum comgr_objects { no_objs = 0, data = 1, data_and_symb = 2 } object_cnt; + bool init = false; +}; +} // namespace __sanitizer +#endif +#endif // SANITIZER_SYMBOLIZER_AMDGPU_H diff --git a/compiler-rt/lib/scudo/standalone/CMakeLists.txt b/compiler-rt/lib/scudo/standalone/CMakeLists.txt index db494a9a74a3f..c244072bb224a 100644 --- a/compiler-rt/lib/scudo/standalone/CMakeLists.txt +++ b/compiler-rt/lib/scudo/standalone/CMakeLists.txt @@ -5,7 +5,7 @@ include_directories(../.. include) set(SCUDO_CFLAGS) list(APPEND SCUDO_CFLAGS - -Werror=conversion + -Wno-error=conversion -Wall -Wextra -pedantic diff --git a/compiler-rt/test/asan/CMakeLists.txt b/compiler-rt/test/asan/CMakeLists.txt index 414a6cc9496ed..e408652a1a014 100644 --- a/compiler-rt/test/asan/CMakeLists.txt +++ b/compiler-rt/test/asan/CMakeLists.txt @@ -13,6 +13,14 @@ if(OS_NAME MATCHES "Windows" AND CMAKE_SIZEOF_VOID_P EQUAL 8 AND message(WARNING "Disabling ASan tests because they are unreliable on Windows 7 and earlier") endif() +# Compile and run AMDGPU device address sanitizer tests only when +# -DSANITIZER_AMDGPU=1 is enabled. +if (SANITIZER_AMDGPU) + set(SUPPORT_OFFLOAD_TESTS "true") +else() + set(SUPPORT_OFFLOAD_TESTS "false") +endif() + macro(get_bits_for_arch arch bits) if (${arch} MATCHES "x86_64|powerpc64|powerpc64le|aarch64|arm64|mips64|mips64el|s390x|sparcv9|riscv64|loongarch64") set(${bits} 64) diff --git a/compiler-rt/test/asan/TestCases/AMDGPU/asan_amdgpu_heap_write.hip b/compiler-rt/test/asan/TestCases/AMDGPU/asan_amdgpu_heap_write.hip new file mode 100644 index 0000000000000..bd2a0e6e1cf3e --- /dev/null +++ b/compiler-rt/test/asan/TestCases/AMDGPU/asan_amdgpu_heap_write.hip @@ -0,0 +1,35 @@ +// RUN: %ROCM_ENV && %hipcompiler -O0 -ggdb --offload-arch=gfx908:xnack+ %s -o %t && not %run %t 10 1 11 10 2>&1 | FileCheck %s +// CHECK: AddressSanitizer: heap-buffer-overflow on amdgpu device +// CHECK-NEXT: {{WRITE of size 4 in workgroup id}} +#include +#include +#include + +__global__ void +set1(int *p) +{ + int i = blockDim.x*blockIdx.x + threadIdx.x; + p[i] = 77; +} + +extern "C" +__attribute__((no_sanitize_address)) +const char* __asan_default_options() { return "detect_leaks=0"; } + +int +main(int argc, char **argv) +{ + int m = std::atoi(argv[1]); + int n1 = std::atoi(argv[2]); + int n2 = std::atoi(argv[3]); + int c = std::atoi(argv[4]); + int *dp; + hipMalloc(&dp, m*sizeof(int)); + hipLaunchKernelGGL(set1, dim3(n1), dim3(n2), 0, 0, dp); + int *hp = (int*)malloc(c*sizeof(int)); + hipMemcpy(hp, dp, m*sizeof(int), hipMemcpyDeviceToHost); + hipDeviceSynchronize(); + hipFree(dp); + free(hp); + return 0; +} diff --git a/compiler-rt/test/asan/TestCases/AMDGPU/lit.local.cfg.py b/compiler-rt/test/asan/TestCases/AMDGPU/lit.local.cfg.py new file mode 100644 index 0000000000000..8f97a245eb15b --- /dev/null +++ b/compiler-rt/test/asan/TestCases/AMDGPU/lit.local.cfg.py @@ -0,0 +1,13 @@ +def getRoot(config): + if not config.parent: + return config + return getRoot(config.parent) + +root = getRoot(config) + +if root.host_os not in ['Linux']: + config.unsupported = True +if root.target_arch not in ['x86_64']: + config.unsupported = True +if root.support_amd_offload_tests == 'false': + config.unsupported = True diff --git a/compiler-rt/test/asan/TestCases/Linux/asan-nonself.cpp b/compiler-rt/test/asan/TestCases/Linux/asan-nonself.cpp new file mode 100644 index 0000000000000..d23ed1806266a --- /dev/null +++ b/compiler-rt/test/asan/TestCases/Linux/asan-nonself.cpp @@ -0,0 +1,36 @@ +// RUN: %clangxx_asan -O2 %s -o %t +// RUN: not %run %t g 2>&1 | FileCheck %s --check-prefix=CHECK + +#include +using namespace std; +using uptr = unsigned long; +using u64 = uint64_t; +using u32 = uint32_t; +using s64 = int64_t; + +// CHECK: AddressSanitizer: stack-buffer-overflow + +// runtime interface function for nonself reporting +extern "C" void __asan_report_nonself_error( + uptr *nonself_callstack, u32 n_nonself_callstack, uptr *nonself_addrs, + u32 n_nonself_addrs, u64 *nonself_tids, u32 n_nonself_tids, bool is_write, + u32 access_size, bool is_abort, const char *nonself_name, + s64 nonself_adjust_vma, int nonself_fd, u64 nonself_file_extent_size, + u64 nonself_file_extent_start = /*default*/ 0); + +// this is a just stub function written for test coverage +void foobar() { + int stack_arr[2]; + uptr addr[1] = {(uptr)((u64)&stack_arr[2])}; + uptr callstack[1] = {(uptr)__builtin_return_address(0)}; + u64 threads[1] = {/*dummy thread id */ 1}; + // BOOM + __asan_report_nonself_error(callstack, 1, addr, 1, threads, 1, false, + 4, true, "null", 0, -1, 0, 0); + return; +} + +int main() { + foobar(); + return 0; +} diff --git a/compiler-rt/test/asan/lit.cfg.py b/compiler-rt/test/asan/lit.cfg.py index 96201e679b0a3..db962f1a5370f 100644 --- a/compiler-rt/test/asan/lit.cfg.py +++ b/compiler-rt/test/asan/lit.cfg.py @@ -331,3 +331,46 @@ def build_invocation(compile_flags, with_lto=False): if config.target_os == "NetBSD": config.substitutions.insert(0, ("%run", config.netbsd_noaslr_prefix)) + +# Find ROCM runtime and compiler paths only +# when built with -DSANITIZER_AMDGPU=1 +def configure_rocm(config, test_rocm_path): + if (not os.path.isdir(test_rocm_path)): + print("no directory found") + test_rocm_path = os.path.join('/opt','rocm') + if (not os.path.isdir(test_rocm_path)): + test_rocm_path = os.path.abspath(os.path.join(config.llvm_install_dir, os.pardir)) + if (not os.path.isdir(test_rocm_path)): + sys.exit("ROCM installation not found, try exporting ASAN_TEST_ROCM variable") + + test_device_libs = os.path.join(test_rocm_path, 'amdgcn', 'bitcode') + test_hip_path = os.path.join(test_rocm_path, 'hip') + hipcc = os.path.join(test_hip_path, 'bin', 'hipcc') + + build_clang = getattr(config, 'clang', None) + build_clang = build_clang.lstrip() + build_clang = build_clang.rstrip() + test_clang_path = os.path.dirname(build_clang) + + def hip_build_invocation(hipcc, compile_flags): + return ' ' + ' '.join([hipcc] + compile_flags) + ' ' # append extra space to avoid concat issue in shell + + hipcxx_sanitize_options = ["-fsanitize=address", "-shared-libsan", "-fgpu-sanitize"] + + config.substitutions.append( + ('%hipcompiler', + hip_build_invocation(hipcc, config.cxx_mode_flags + [config.target_cflags] + hipcxx_sanitize_options))) + + #ROCM SPECIFIC ENVIRONMENT VARIABLES + device_library_path = 'DEVICE_LIB_PATH=' + test_device_libs + hip_path = 'HIP_PATH=' + test_hip_path + rocm_path = 'ROCM_PATH=' + test_rocm_path + clang_path = 'HIP_CLANG_PATH=' + test_clang_path + rocm_environment = [device_library_path, hip_path, rocm_path, clang_path] + export_rocm_components = 'export ' + ' '.join(rocm_environment) + config.substitutions.append(('%ROCM_ENV', export_rocm_components)) + config.suffixes.append('.hip') + +test_rocm_path = os.environ.get('ASAN_TEST_ROCM','null') +if config.support_amd_offload_tests == 'true': + configure_rocm(config, test_rocm_path) diff --git a/compiler-rt/test/asan/lit.site.cfg.py.in b/compiler-rt/test/asan/lit.site.cfg.py.in index afecfafeb99f9..4eff26cf9ad62 100644 --- a/compiler-rt/test/asan/lit.site.cfg.py.in +++ b/compiler-rt/test/asan/lit.site.cfg.py.in @@ -10,6 +10,8 @@ config.apple_platform = "@ASAN_TEST_APPLE_PLATFORM@" config.apple_platform_min_deployment_target_flag = "@ASAN_TEST_MIN_DEPLOYMENT_TARGET_FLAG@" config.asan_dynamic = @ASAN_TEST_DYNAMIC@ config.target_arch = "@ASAN_TEST_TARGET_ARCH@" +config.support_amd_offload_tests = "@SUPPORT_OFFLOAD_TESTS@" +config.llvm_install_dir = "@CMAKE_INSTALL_PREFIX@" # Load common config for all compiler-rt lit tests. lit_config.load_config(config, "@COMPILER_RT_BINARY_DIR@/test/lit.common.configured") diff --git a/compiler-rt/test/hwasan/TestCases/Linux/reuse-threads.cpp b/compiler-rt/test/hwasan/TestCases/Linux/reuse-threads.cpp deleted file mode 100644 index cb77e93e15f32..0000000000000 --- a/compiler-rt/test/hwasan/TestCases/Linux/reuse-threads.cpp +++ /dev/null @@ -1,53 +0,0 @@ -// Test that Thread objects are reused. -// RUN: %clangxx_hwasan -mllvm -hwasan-globals=0 -mllvm -hwasan-instrument-stack=0 %s -o %t && %env_hwasan_opts=verbose_threads=1 %run %t 2>&1 | FileCheck %s - -#include -#include -#include -#include -#include -#include - -#include - -pthread_barrier_t bar; - -void *threadfn(void *) { - pthread_barrier_wait(&bar); - return nullptr; -} - -void start_stop_threads() { - constexpr int N = 2; - pthread_t threads[N]; - - pthread_barrier_init(&bar, nullptr, N + 1); - for (auto &t : threads) - pthread_create(&t, nullptr, threadfn, nullptr); - - pthread_barrier_wait(&bar); - - for (auto &t : threads) - pthread_join(t, nullptr); - pthread_barrier_destroy(&bar); -} - -int main() { - // Cut off initial threads. - // CHECK: === test start === - fprintf(stderr, "=== test start ===\n"); - - // CHECK: Creating : T{{[0-9]+}} [[A:0x[0-9a-f]+]] stack: - // CHECK: Creating : T{{[0-9]+}} [[B:0x[0-9a-f]+]] stack: - start_stop_threads(); - - // CHECK-DAG: Creating : T{{[0-9]+}} [[A]] stack: - // CHECK-DAG: Creating : T{{[0-9]+}} [[B]] stack: - start_stop_threads(); - - // CHECK-DAG: Creating : T{{[0-9]+}} [[A]] stack: - // CHECK-DAG: Creating : T{{[0-9]+}} [[B]] stack: - start_stop_threads(); - - return 0; -} diff --git a/flang-rt/CMakeLists.txt b/flang-rt/CMakeLists.txt index cad39d0c71016..17a51759e1a0e 100644 --- a/flang-rt/CMakeLists.txt +++ b/flang-rt/CMakeLists.txt @@ -27,7 +27,7 @@ set(FLANG_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../flang") # LLVM's requirement is only CMake 3.20, teach CMake 3.20-3.23 how to use Flang. if (CMAKE_VERSION VERSION_LESS "3.24") cmake_path(GET CMAKE_Fortran_COMPILER STEM _Fortran_COMPILER_STEM) - if (_Fortran_COMPILER_STEM STREQUAL "flang-new" OR _Fortran_COMPILER_STEM STREQUAL "flang") + if (_Fortran_COMPILER_STEM STREQUAL "flang") include(CMakeForceCompiler) CMAKE_FORCE_Fortran_COMPILER("${CMAKE_Fortran_COMPILER}" "LLVMFlang") @@ -216,6 +216,7 @@ if (FLANG_RT_INCLUDE_CUF) find_package(CUDAToolkit REQUIRED) endif() +option(FLANG_RT_INCLUDE_AMD "Build Fortran runtime with special support for AMD GPUs" OFF) ######################## # System Introspection # diff --git a/flang-rt/README.md b/flang-rt/README.md index 4fe66a85a269c..fa34775ec5c4e 100644 --- a/flang-rt/README.md +++ b/flang-rt/README.md @@ -164,6 +164,11 @@ CMake itself provide. [CUDA Toolkit installation](https://cmake.org/cmake/help/latest/module/FindCUDAToolkit.html) (no `CMAKE_CUDA_COMPILER`). + * `FLANG_RT_INCLUDE_AMD` (bool, default: `OFF`) + + Compiles the `libflang_rt.a/.so` library with special support for AMD + Instinct(tm) Accelerators. + ### Experimental CUDA Support diff --git a/flang-rt/include/flang-rt/runtime/amd/umpire/config.hpp b/flang-rt/include/flang-rt/runtime/amd/umpire/config.hpp new file mode 100644 index 0000000000000..b4418bf52559c --- /dev/null +++ b/flang-rt/include/flang-rt/runtime/amd/umpire/config.hpp @@ -0,0 +1,69 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2016-25, Lawrence Livermore National Security, LLC and Umpire +// project contributors. See the COPYRIGHT file for details. +// +// SPDX-License-Identifier: (MIT) +////////////////////////////////////////////////////////////////////////////// +#ifndef UMPIRE_config_HPP +#define UMPIRE_config_HPP + +// +// Please keep the list below organized in alphabetical order. +// +/* #undef UMPIRE_ENABLE_BACKTRACE */ +/* #undef UMPIRE_ENABLE_BACKTRACE_SYMBOLS */ +/* #undef UMPIRE_ENABLE_DEVELOPER_BENCHMARKS */ +/* #undef UMPIRE_ENABLE_CONST */ +/* #undef UMPIRE_ENABLE_CUDA */ +#define UMPIRE_ENABLE_DEVICE +/* #undef UMPIRE_ENABLE_FILESYSTEM */ +#define UMPIRE_ENABLE_FILE_RESOURCE +/* #undef UMPIRE_ENABLE_UMAP */ +#define UMPIRE_ENABLE_HIP +/* #undef UMPIRE_ENABLE_HIP_COHERENCE_GRANULARITY */ +/* #undef UMPIRE_ENABLE_IPC_SHARED_MEMORY */ +/* #undef UMPIRE_ENABLE_MPI3_SHARED_MEMORY */ +/* #undef UMPIRE_ENABLE_INACCESSIBILITY_TESTS */ +#define UMPIRE_ENABLE_LOGGING +/* #undef UMPIRE_ENABLE_MPI */ +/* #undef UMPIRE_ENABLE_NUMA */ +/* #undef UMPIRE_ENABLE_OPENMP_TARGET */ +#define UMPIRE_ENABLE_PINNED +/* #undef UMPIRE_ENABLE_SLIC */ +/* #undef UMPIRE_ENABLE_SYCL */ +#define UMPIRE_ENABLE_UM +/* #undef UMPIRE_ENABLE_ASAN */ +/* #undef UMPIRE_ENABLE_DEVICE_ALLOCATOR */ +/* #undef UMPIRE_ENABLE_SQLITE_EXPERIMENTAL */ +/* #undef UMPIRE_DISABLE_ALLOCATIONMAP_DEBUG */ + +#define UMPIRE_VERSION_MAJOR 2025 +#define UMPIRE_VERSION_MINOR 3 +#define UMPIRE_VERSION_PATCH 0 +#define UMPIRE_VERSION_RC "6b4cb9e9" + +#ifdef __cplusplus + +// umpire_EXPORTS gets defined by CMake when we use +// -DCMAKE_WINDOWS_EXPORT_ALL_SYMBOLS=On +#if (defined(_WIN32) || defined(_WIN64)) && !defined(UMPIRE_WIN_STATIC_BUILD) +#ifdef umpire_EXPORTS +#define UMPIRE_EXPORT __declspec(dllexport) +#else +#define UMPIRE_EXPORT __declspec(dllimport) +#endif +#else +#define UMPIRE_EXPORT +#endif + +#define UMPIRE_VERSION_SYM umpire_ver_2025_3_found +UMPIRE_EXPORT extern int UMPIRE_VERSION_SYM; +#define UMPIRE_VERSION_OK() UMPIRE_VERSION_SYM == 0 + +namespace umpire { +constexpr int invalid_allocator_id = 0xDEADBEE; +} + +#endif + +#endif diff --git a/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/typesUmpire.h b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/typesUmpire.h new file mode 100644 index 0000000000000..43c1d952204d9 --- /dev/null +++ b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/typesUmpire.h @@ -0,0 +1,158 @@ +// typesUmpire.h +// This file is generated by Shroud 0.12.2. Do not edit. +// Copyright (c) 2016-25, Lawrence Livermore National Security, LLC and Umpire +// project contributors. See the COPYRIGHT file for details. +// +// SPDX-License-Identifier: (MIT) +// For C users and C++ implementation + +#ifndef TYPESUMPIRE_H +#define TYPESUMPIRE_H + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +// helper capsule_data_helper +struct s_umpire_SHROUD_capsule_data { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_SHROUD_capsule_data umpire_SHROUD_capsule_data; + +/* helper ShroudTypeDefines */ +/* Shroud type defines */ +#define SH_TYPE_SIGNED_CHAR 1 +#define SH_TYPE_SHORT 2 +#define SH_TYPE_INT 3 +#define SH_TYPE_LONG 4 +#define SH_TYPE_LONG_LONG 5 +#define SH_TYPE_SIZE_T 6 + +#define SH_TYPE_UNSIGNED_SHORT SH_TYPE_SHORT + 100 +#define SH_TYPE_UNSIGNED_INT SH_TYPE_INT + 100 +#define SH_TYPE_UNSIGNED_LONG SH_TYPE_LONG + 100 +#define SH_TYPE_UNSIGNED_LONG_LONG SH_TYPE_LONG_LONG + 100 + +#define SH_TYPE_INT8_T 7 +#define SH_TYPE_INT16_T 8 +#define SH_TYPE_INT32_T 9 +#define SH_TYPE_INT64_T 10 + +#define SH_TYPE_UINT8_T SH_TYPE_INT8_T + 100 +#define SH_TYPE_UINT16_T SH_TYPE_INT16_T + 100 +#define SH_TYPE_UINT32_T SH_TYPE_INT32_T + 100 +#define SH_TYPE_UINT64_T SH_TYPE_INT64_T + 100 + +/* least8 least16 least32 least64 */ +/* fast8 fast16 fast32 fast64 */ +/* intmax_t intptr_t ptrdiff_t */ + +#define SH_TYPE_FLOAT 22 +#define SH_TYPE_DOUBLE 23 +#define SH_TYPE_LONG_DOUBLE 24 +#define SH_TYPE_FLOAT_COMPLEX 25 +#define SH_TYPE_DOUBLE_COMPLEX 26 +#define SH_TYPE_LONG_DOUBLE_COMPLEX 27 + +#define SH_TYPE_BOOL 28 +#define SH_TYPE_CHAR 29 +#define SH_TYPE_CPTR 30 +#define SH_TYPE_STRUCT 31 +#define SH_TYPE_OTHER 32 + +// helper array_context +struct s_umpire_SHROUD_array { + umpire_SHROUD_capsule_data cxx; /* address of C++ memory */ + union { + const void * base; + const char * ccharp; + } addr; + int type; /* type of element */ + size_t elem_len; /* bytes-per-item or character len in c++ */ + size_t size; /* size of data in c++ */ + int rank; /* number of dimensions, 0=scalar */ + long shape[7]; +}; +typedef struct s_umpire_SHROUD_array umpire_SHROUD_array; + +// helper capsule_umpire_allocator +struct s_umpire_allocator { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_allocator umpire_allocator; + +// helper capsule_umpire_resourcemanager +struct s_umpire_resourcemanager { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_resourcemanager umpire_resourcemanager; + +// helper capsule_umpire_strategy_alignedallocator +struct s_umpire_strategy_alignedallocator { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_strategy_alignedallocator umpire_strategy_alignedallocator; + +// helper capsule_umpire_strategy_allocationadvisor +struct s_umpire_strategy_allocationadvisor { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_strategy_allocationadvisor umpire_strategy_allocationadvisor; + +// helper capsule_umpire_strategy_allocationprefetcher +struct s_umpire_strategy_allocationprefetcher { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_strategy_allocationprefetcher umpire_strategy_allocationprefetcher; + +// helper capsule_umpire_strategy_dynamicpoollist +struct s_umpire_strategy_dynamicpoollist { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_strategy_dynamicpoollist umpire_strategy_dynamicpoollist; + +// helper capsule_umpire_strategy_fixedpool +struct s_umpire_strategy_fixedpool { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_strategy_fixedpool umpire_strategy_fixedpool; + +// helper capsule_umpire_strategy_namedallocationstrategy +struct s_umpire_strategy_namedallocationstrategy { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_strategy_namedallocationstrategy umpire_strategy_namedallocationstrategy; + +// helper capsule_umpire_strategy_quickpool +struct s_umpire_strategy_quickpool { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_strategy_quickpool umpire_strategy_quickpool; + +// helper capsule_umpire_strategy_threadsafeallocator +struct s_umpire_strategy_threadsafeallocator { + void *addr; /* address of C++ memory */ + int idtor; /* index of destructor */ +}; +typedef struct s_umpire_strategy_threadsafeallocator umpire_strategy_threadsafeallocator; + +void umpire_SHROUD_memory_destructor(umpire_SHROUD_capsule_data *cap); + +#ifdef __cplusplus +} +#endif + +#endif // TYPESUMPIRE_H diff --git a/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/umpire-prep.h b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/umpire-prep.h new file mode 100644 index 0000000000000..cc9d84c54c670 --- /dev/null +++ b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/umpire-prep.h @@ -0,0 +1,6 @@ +# 0 "umpire.h" +# 0 "" +# 0 "" +# 1 "/usr/include/stdc-predef.h" 1 3 4 +# 0 "" 2 +# 1 "umpire.h" diff --git a/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/umpire.h b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/umpire.h new file mode 100644 index 0000000000000..a14d029652e80 --- /dev/null +++ b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/umpire.h @@ -0,0 +1,18 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2016-25, Lawrence Livermore National Security, LLC and Umpire +// project contributors. See the COPYRIGHT file for details. +// +// SPDX-License-Identifier: (MIT) +////////////////////////////////////////////////////////////////////////////// +#ifndef UMPIRE_H_ +#define UMPIRE_H_ + +#include "flang-rt/runtime/amd/umpire/config.hpp" + +#define UMPIRE_INVALID_ALLOCATOR_ID 0xDEADBEE + +#include "flang-rt/runtime/amd/umpire/interface/c_fortran/wrapUmpire.h" +#include "flang-rt/runtime/amd/umpire/interface/c_fortran/wrapAllocator.h" +#include "flang-rt/runtime/amd/umpire/interface/c_fortran/wrapResourceManager.h" + +#endif // UMPIRE_H_ diff --git a/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/wrapAllocator.h b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/wrapAllocator.h new file mode 100644 index 0000000000000..5994cb34f9516 --- /dev/null +++ b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/wrapAllocator.h @@ -0,0 +1,62 @@ +// wrapAllocator.h +// This file is generated by Shroud 0.12.2. Do not edit. +// Copyright (c) 2016-25, Lawrence Livermore National Security, LLC and Umpire +// project contributors. See the COPYRIGHT file for details. +// +// SPDX-License-Identifier: (MIT) +/** + * \file wrapAllocator.h + * \brief Shroud generated wrapper for Allocator class + */ +// For C users and C++ implementation + +#ifndef WRAPALLOCATOR_H +#define WRAPALLOCATOR_H + +#include "typesUmpire.h" +#ifdef __cplusplus +#include +#else +#include +#endif + +// splicer begin class.Allocator.CXX_declarations +// splicer end class.Allocator.CXX_declarations + +#ifdef __cplusplus +extern "C" { +#endif + +// splicer begin class.Allocator.C_declarations +// splicer end class.Allocator.C_declarations + +void umpire_allocator_delete(umpire_allocator * self); + +void * umpire_allocator_allocate(umpire_allocator * self, size_t bytes); + +void umpire_allocator_deallocate(umpire_allocator * self, void * ptr); + +void umpire_allocator_release(umpire_allocator * self); + +size_t umpire_allocator_get_size(umpire_allocator * self, void * ptr); + +size_t umpire_allocator_get_high_watermark(umpire_allocator * self); + +size_t umpire_allocator_get_current_size(umpire_allocator * self); + +size_t umpire_allocator_get_actual_size(umpire_allocator * self); + +size_t umpire_allocator_get_allocation_count(umpire_allocator * self); + +const char * umpire_allocator_get_name(umpire_allocator * self); + +void umpire_allocator_get_name_bufferify(umpire_allocator * self, + umpire_SHROUD_array *DSHF_rv); + +size_t umpire_allocator_get_id(umpire_allocator * self); + +#ifdef __cplusplus +} +#endif + +#endif // WRAPALLOCATOR_H diff --git a/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/wrapResourceManager.h b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/wrapResourceManager.h new file mode 100644 index 0000000000000..94f2010a983fc --- /dev/null +++ b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/wrapResourceManager.h @@ -0,0 +1,195 @@ +// wrapResourceManager.h +// This file is generated by Shroud 0.12.2. Do not edit. +// Copyright (c) 2016-25, Lawrence Livermore National Security, LLC and Umpire +// project contributors. See the COPYRIGHT file for details. +// +// SPDX-License-Identifier: (MIT) +/** + * \file wrapResourceManager.h + * \brief Shroud generated wrapper for ResourceManager class + */ +// For C users and C++ implementation + +#ifndef WRAPRESOURCEMANAGER_H +#define WRAPRESOURCEMANAGER_H + +#include "typesUmpire.h" +#ifdef __cplusplus +#include +#else +#include +#include +#endif + +// splicer begin class.ResourceManager.CXX_declarations +// splicer end class.ResourceManager.CXX_declarations + +#ifdef __cplusplus +extern "C" { +#endif + +// splicer begin class.ResourceManager.C_declarations +// splicer end class.ResourceManager.C_declarations + +umpire_resourcemanager * umpire_resourcemanager_get_instance( + umpire_resourcemanager * SHC_rv); + +umpire_allocator * umpire_resourcemanager_get_allocator_by_name( + umpire_resourcemanager * self, const char * name, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_get_allocator_by_name_bufferify( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_get_allocator_by_id( + umpire_resourcemanager * self, const int id, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_list_pool( + umpire_resourcemanager * self, const char * name, + umpire_allocator allocator, size_t initial_size, size_t block, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_bufferify_list_pool( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator allocator, size_t initial_size, size_t block, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_quick_pool( + umpire_resourcemanager * self, const char * name, + umpire_allocator allocator, size_t initial_size, size_t block, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_bufferify_quick_pool( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator allocator, size_t initial_size, size_t block, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_advisor( + umpire_resourcemanager * self, const char * name, + umpire_allocator allocator, const char * advice_op, int device_id, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_bufferify_advisor( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator allocator, const char * advice_op, int Ladvice_op, + int device_id, umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_named( + umpire_resourcemanager * self, const char * name, + umpire_allocator allocator, umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_bufferify_named( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator allocator, umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_thread_safe( + umpire_resourcemanager * self, const char * name, + umpire_allocator allocator, umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_bufferify_thread_safe( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator allocator, umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_fixed_pool( + umpire_resourcemanager * self, const char * name, + umpire_allocator allocator, size_t object_size, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_bufferify_fixed_pool( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator allocator, size_t object_size, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_aligned_allocator( + umpire_resourcemanager * self, const char * name, + umpire_allocator allocator, size_t object_size, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_bufferify_aligned_allocator( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator allocator, size_t object_size, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_prefetcher( + umpire_resourcemanager * self, const char * name, + umpire_allocator allocator, int device_id, + umpire_allocator * SHC_rv); + +umpire_allocator * umpire_resourcemanager_make_allocator_bufferify_prefetcher( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator allocator, int device_id, + umpire_allocator * SHC_rv); + +void umpire_resourcemanager_add_alias(umpire_resourcemanager * self, + const char * name, umpire_allocator allocator); + +void umpire_resourcemanager_add_alias_bufferify( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator allocator); + +void umpire_resourcemanager_remove_alias(umpire_resourcemanager * self, + const char * name, umpire_allocator allocator); + +void umpire_resourcemanager_remove_alias_bufferify( + umpire_resourcemanager * self, const char * name, int Lname, + umpire_allocator allocator); + +umpire_allocator * umpire_resourcemanager_get_allocator_for_ptr( + umpire_resourcemanager * self, void * ptr, + umpire_allocator * SHC_rv); + +bool umpire_resourcemanager_is_allocator_name( + umpire_resourcemanager * self, const char * name); + +bool umpire_resourcemanager_is_allocator_name_bufferify( + umpire_resourcemanager * self, const char * name, int Lname); + +bool umpire_resourcemanager_is_allocator_id( + umpire_resourcemanager * self, int id); + +bool umpire_resourcemanager_has_allocator(umpire_resourcemanager * self, + void * ptr); + +void umpire_resourcemanager_copy_all(umpire_resourcemanager * self, + void * src_ptr, void * dst_ptr); + +void umpire_resourcemanager_copy_with_size( + umpire_resourcemanager * self, void * src_ptr, void * dst_ptr, + size_t size); + +void umpire_resourcemanager_memset_all(umpire_resourcemanager * self, + void * ptr, int val); + +void umpire_resourcemanager_memset_with_size( + umpire_resourcemanager * self, void * ptr, int val, size_t length); + +void * umpire_resourcemanager_reallocate_default( + umpire_resourcemanager * self, void * src_ptr, size_t size); + +void * umpire_resourcemanager_reallocate_with_allocator( + umpire_resourcemanager * self, void * src_ptr, size_t size, + umpire_allocator allocator); + +void * umpire_resourcemanager_move(umpire_resourcemanager * self, + void * src_ptr, umpire_allocator allocator); + +void umpire_resourcemanager_deallocate(umpire_resourcemanager * self, + void * ptr); + +size_t umpire_resourcemanager_get_size(umpire_resourcemanager * self, + void * ptr); + +void umpire_resourcemanager_register_allocation( + umpire_resourcemanager * self, void * ptr, size_t size, + umpire_allocator allocator); + +void umpire_resourcemanager_deregister_allocation( + umpire_resourcemanager * self, void * ptr); + +#ifdef __cplusplus +} +#endif + +#endif // WRAPRESOURCEMANAGER_H diff --git a/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/wrapUmpire.h b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/wrapUmpire.h new file mode 100644 index 0000000000000..c1c1d16effb2b --- /dev/null +++ b/flang-rt/include/flang-rt/runtime/amd/umpire/interface/c_fortran/wrapUmpire.h @@ -0,0 +1,57 @@ +// wrapUmpire.h +// This file is generated by Shroud 0.12.2. Do not edit. +// Copyright (c) 2016-25, Lawrence Livermore National Security, LLC and Umpire +// project contributors. See the COPYRIGHT file for details. +// +// SPDX-License-Identifier: (MIT) +/** + * \file wrapUmpire.h + * \brief Shroud generated wrapper for umpire namespace + */ +// For C users and C++ implementation + +#ifndef WRAPUMPIRE_H +#define WRAPUMPIRE_H + +#include "typesUmpire.h" +#ifdef __cplusplus +#include +#else +#include +#include +#endif + +// splicer begin CXX_declarations +// splicer end CXX_declarations + +#ifdef __cplusplus +extern "C" { +#endif + +// splicer begin C_declarations +// splicer end C_declarations + +bool umpire_pointer_overlaps(void * left, void * right); + +bool umpire_pointer_contains(void * left, void * right); + +void umpire_get_backtrace_bufferify(void * ptr, + umpire_SHROUD_array *DSHF_rv); + +size_t umpire_get_process_memory_usage(void); + +size_t umpire_get_process_memory_usage_hwm(void); + +size_t umpire_get_device_memory_usage(int device_id); + +int umpire_get_major_version(void); + +int umpire_get_minor_version(void); + +int umpire_get_patch_version(void); + +#ifdef __cplusplus +} +#endif + +#endif // WRAPUMPIRE_H diff --git a/flang-rt/include/flang-rt/runtime/descriptor.h b/flang-rt/include/flang-rt/runtime/descriptor.h index ff7ec050d32c7..8c848fcab24ee 100644 --- a/flang-rt/include/flang-rt/runtime/descriptor.h +++ b/flang-rt/include/flang-rt/runtime/descriptor.h @@ -33,6 +33,8 @@ #include RT_OFFLOAD_VAR_GROUP_BEGIN +/// Value used for asyncId when no specific stream is specified. +static constexpr std::int64_t kNoAsyncId = -1; /// Value used for asyncObject when no specific stream is specified. static constexpr std::int64_t *kNoAsyncObject = nullptr; RT_OFFLOAD_VAR_GROUP_END diff --git a/flang-rt/include/flang-rt/runtime/terminator.h b/flang-rt/include/flang-rt/runtime/terminator.h index 047b576be4bc1..842de8de4e68d 100644 --- a/flang-rt/include/flang-rt/runtime/terminator.h +++ b/flang-rt/include/flang-rt/runtime/terminator.h @@ -68,7 +68,8 @@ class Terminator { template RT_API_ATTRS void PrintCrashArgs(const char *message, Args... args) const { #if defined(RT_DEVICE_COMPILATION) - std::printf(message, args...); + // commenting out temporarily to avoid "error: cannot compile this non-scalar arg in GPU vargs function yet" + // std::printf(message, args...); #else std::fprintf(stderr, message, args...); #endif diff --git a/flang-rt/include/flang-rt/runtime/work-queue.h b/flang-rt/include/flang-rt/runtime/work-queue.h index 7d7f8ad991a57..d1ea036a8fc0a 100644 --- a/flang-rt/include/flang-rt/runtime/work-queue.h +++ b/flang-rt/include/flang-rt/runtime/work-queue.h @@ -127,8 +127,8 @@ class Elementwise { const Descriptor &instance_, *from_{nullptr}; std::size_t elements_{instance_.InlineElements()}; std::size_t elementAt_{0}; - SubscriptValue subscripts_[common::maxRank]; - SubscriptValue fromSubscripts_[common::maxRank]; + SubscriptValue subscripts_[maxRank]; + SubscriptValue fromSubscripts_[maxRank]; }; // Base class for ticket workers that operate over derived type components. @@ -162,7 +162,7 @@ class Componentwise { const typeInfo::DerivedType &derived_; std::size_t components_{0}, componentAt_{0}; const typeInfo::Component *component_{nullptr}; - StaticDescriptor componentDescriptor_; + StaticDescriptor componentDescriptor_; private: RT_API_ATTRS void GetFirstComponent() { @@ -275,7 +275,7 @@ class InitializeCloneTicket const Descriptor &clone_; bool hasStat_{false}; const Descriptor *errMsg_{nullptr}; - StaticDescriptor cloneComponentDescriptor_; + StaticDescriptor cloneComponentDescriptor_; }; // Implements derived type instance finalization @@ -331,7 +331,7 @@ class AssignTicket : public ImmediateTicketRunner { const Descriptor *from_{nullptr}; int flags_{0}; // enum AssignFlags MemmoveFct memmoveFct_{nullptr}; - StaticDescriptor tempDescriptor_; + StaticDescriptor tempDescriptor_; const typeInfo::DerivedType *declaredType_{nullptr}; const typeInfo::DerivedType *toDerived_{nullptr}; Descriptor *toDeallocate_{nullptr}; @@ -364,7 +364,7 @@ class DerivedAssignTicket int flags_{0}; MemmoveFct memmoveFct_{nullptr}; Descriptor *deallocateAfter_{nullptr}; - StaticDescriptor fromComponentDescriptor_; + StaticDescriptor fromComponentDescriptor_; }; namespace io::descr { @@ -392,7 +392,7 @@ class DescriptorIoTicket common::optional nonTbpSpecial_; const typeInfo::DerivedType *derived_{nullptr}; const typeInfo::SpecialBinding *special_{nullptr}; - StaticDescriptor elementDescriptor_; + StaticDescriptor elementDescriptor_; }; template diff --git a/flang-rt/lib/CMakeLists.txt b/flang-rt/lib/CMakeLists.txt index aee51dcc9fa24..399c4699bc0f4 100644 --- a/flang-rt/lib/CMakeLists.txt +++ b/flang-rt/lib/CMakeLists.txt @@ -11,6 +11,9 @@ add_subdirectory(runtime) if (FLANG_RT_INCLUDE_CUF) add_subdirectory(cuda) endif() +if (FLANG_RT_INCLUDE_AMD) + add_subdirectory(amd) +endif() if (FLANG_RT_INCLUDE_TESTS) add_subdirectory(Testing) diff --git a/flang-rt/lib/amd/CMakeLists.txt b/flang-rt/lib/amd/CMakeLists.txt new file mode 100644 index 0000000000000..efab42d1d95bf --- /dev/null +++ b/flang-rt/lib/amd/CMakeLists.txt @@ -0,0 +1,26 @@ +#===-- lib/amd/CMakeLists.txt ----------------------------------------------===# +# +# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +# +#===------------------------------------------------------------------------===# + +# Check that Umpire exits in the directory given at CMake +# TODO: this was disabled to get to an easier build procedure for now +#message(STATUS "Using Umpire in directory ${FLANG_RT_UMPIRE_DIR}") +#set(umpire_DIR ${FLANG_RT_UMPIRE_DIR}) +#find_package(umpire REQUIRED PATHS ${FLANG_RT_UMPIRE_DIR}/lib/cmake/umpire) + +add_flangrt_library(flang_rt.amd STATIC SHARED + amd_alloc.cpp + INSTALL_WITH_TOOLCHAIN +) + +#if (TARGET flang_rt.amd.static) +# target_include_directories(flang_rt.amd.static PRIVATE ${FLANG_RT_UMPIRE_DIR}/include) +#endif() +# +#if (TARGET flang_rt.amd.shared) +# target_include_directories(flang_rt.amd.shared PRIVATE ${FLANG_RT_UMPIRE_DIR}/include) +#endif() diff --git a/flang-rt/lib/amd/amd_alloc.cpp b/flang-rt/lib/amd/amd_alloc.cpp new file mode 100644 index 0000000000000..ae2cfaeb6bc79 --- /dev/null +++ b/flang-rt/lib/amd/amd_alloc.cpp @@ -0,0 +1,196 @@ +//===-- lib/amd/amd_alloc.cpp -----------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#warning "amd_alloc.cpp was part of the build" + +#define ALLOC_INITIAL_SIZE (128 * 1024 * 1024) +#define ALLOC_BLOCK_SIZE (512) + +#define ALLOC_DEBUG 1 + +#include "flang-rt/runtime/allocator-registry.h" +#include "flang-rt/runtime/descriptor.h" +#include "flang/Runtime/AMD/amd_alloc.h" +#include "flang/Support/Fortran.h" +#include +#include +#include +#include +#include + +// Deliberately use the C interface of Umpire, as it does not require +// support for exceptions and RTTI, which are not avilable in the +// Fortran runtime build. +// TODO: go back to the correct header that is imported from an +// installation of Umpire +// #include "umpire/interface/c_fortran/umpire.h" +#include "flang-rt/runtime/amd/umpire/interface/c_fortran/umpire.h" + +namespace Fortran::runtime::amd { + +static bool debugEnabled; +static umpire_resourcemanager resourceManager; +static umpire_allocator memoryPool; + +void *UmpireAlloc(std::size_t AllocationSize, std::int64_t *) { +#if ALLOC_DEBUG + if (debugEnabled) { + std::fprintf(stderr, "[AMD_ALLOC] %s(%zu) (%s:%d)\n", __PRETTY_FUNCTION__, + AllocationSize, __FILE__, __LINE__); + } +#endif + void *pointer{umpire_allocator_allocate(&memoryPool, AllocationSize)}; +#if ALLOC_DEBUG + if (debugEnabled) { + std::fprintf(stderr, "[AMD_ALLOC] pointer of size %zu allocated at %p\n", + AllocationSize, pointer); + } +#endif + return pointer; +} + +void UmpireFree(void *pointer) { +#if ALLOC_DEBUG + if (debugEnabled) { + std::fprintf(stderr, "[AMD_ALLOC] %s(%p) (%s:%d)\n", __PRETTY_FUNCTION__, + pointer, __FILE__, __LINE__); + } +#endif + umpire_allocator_deallocate(&memoryPool, pointer); +} + +void registerUmpireAllocator( + const std::string &pool, const int initialSize, const int blockSize) { +#if ALLOC_DEBUG + if (debugEnabled) { + std::fprintf(stderr, + "[AMD_ALLOC] registering Umpire dynamically growing allocator for " + "'%s'\n", + pool.c_str()); + } +#endif // ALLOC_DEBUG + // Configure a dynamically growing memory pool. + umpire_allocator allocator; + umpire_resourcemanager_get_instance(&resourceManager); + umpire_resourcemanager_get_allocator_by_name( + &resourceManager, pool.c_str(), &allocator); + umpire_resourcemanager_make_allocator_list_pool( + &resourceManager, "pool", allocator, initialSize, blockSize, &memoryPool); + + allocatorRegistry.Register(1, {&UmpireAlloc, &UmpireFree}); +} + +static std::string getStringFromEnvironment( + const char *envirable, const std::string defaultValue = "") { + if (auto value{std::getenv(envirable)}) { + return std::string{value}; + } + return std::string{defaultValue}; +} + +static int getIntFromEnvironment( + const char *envirable, const int defaultValue = 0) { + int result = defaultValue; + char *end; + if (auto value{std::getenv(envirable)}) { + auto number{std::strtoul(value, &end, 10)}; + if (number > 0 && number < std::numeric_limits::max() && + *end == '\0') { + result = number; + } else { + std::fprintf(stderr, "Fortran runtime: %s=%s is invalid; ignored\n", + envirable, value); + } + } + return result; +} + +static std::pair splitAtColon( + const std::string &str) { + size_t colon = str.find(':'); + if (colon == std::string::npos) { + return {str, ""}; + } + return {str.substr(0, colon), str.substr(colon + 1)}; +} + +extern "C" { +void RTDEF(AMDRegisterAllocator)() { +#if ALLOC_DEBUG + debugEnabled = false; + if (getIntFromEnvironment("AMD_ALLOC_DEBUG", 0) != 0) { + debugEnabled = true; + } + if (debugEnabled) { + std::fprintf(stderr, "[AMD_ALLOC] %s (%s:%d)\n", __PRETTY_FUNCTION__, + __FILE__, __LINE__); + } +#endif + + // Get some basic values from the environment about initial pool size, + // allocation block size, etc. + auto initialSize{ + getIntFromEnvironment("AMD_ALLOC_INITIAL_SIZE", ALLOC_INITIAL_SIZE)}; + auto blockSize{ + getIntFromEnvironment("AMD_ALLOC_BLOCK_SIZE", ALLOC_BLOCK_SIZE)}; +#if ALLOC_DEBUG + if (debugEnabled) { + std::fprintf(stderr, + "[AMD_ALLOC] initial pool size = %d (%.2f MB), block size = %d (%f.2 " + "kB)\n", + initialSize, initialSize / 1048576.0f, blockSize, blockSize / 1024.0f); + } +#endif + + // Determine what allocator to register via very simplistic parsing of syntax + // ALLOCATOR:MEMORY_KIND. Proper values are: Umpire:host, Umpire:device. + std::string allocator = getStringFromEnvironment("AMD_ALLOC", "umpire:host"); + std::transform( + allocator.begin(), allocator.end(), allocator.begin(), ::toupper); +#if ALLOC_DEBUG + if (debugEnabled) { + std::fprintf( + stderr, "[AMD_ALLOC] requesting allocator: %s\n", allocator.c_str()); + } +#endif // ALLOC_DEBUG + std::pair allocSpec{splitAtColon(allocator)}; + if (allocSpec.first != "UMPIRE") { + std::fprintf(stderr, + "[AMD_ALLOC] warning: wrong allocator ('%s') specified for Umpire " + "allocator, using 'UMPIRE' instead\n", + allocSpec.first.c_str()); + allocSpec.first = std::string("UMPIRE"); + } + if (allocSpec.first == "UMPIRE") { + // Register this allocator in the infrastructure as allocator 1. + // This has a counter part in descriptor.cpp, where (right now) + // the allocator is hard-coded to be allocator 1 (and the default + // allocator has been disabled). + if (allocSpec.second != "HOST" && allocSpec.second != "DEVICE") { + std::fprintf(stderr, + "[AMD_ALLOC] warning: wrong pool ('%s') specified for Umpire " + "allocator, using 'HOST' instead\n", + allocSpec.second.c_str()); + allocSpec.second = std::string{"HOST"}; + } + registerUmpireAllocator(allocSpec.second, initialSize, blockSize); + } +} + +void RTDEF(AMDAllocatableSetAllocIdx)(Descriptor &descriptor, int pos) { + if (descriptor.IsAllocatable() && !descriptor.IsAllocated()) { + if (debugEnabled) { + std::fprintf( + stderr, "[AMD_ALLOC] AMDAllocatableSetAllocIdx = %d \n", pos); + } + descriptor.SetAllocIdx(pos); + } +} +} // extern "C" + +} // namespace Fortran::runtime::amd diff --git a/flang-rt/lib/runtime/CMakeLists.txt b/flang-rt/lib/runtime/CMakeLists.txt index e8f70bd544e0b..ef0f812eaca00 100644 --- a/flang-rt/lib/runtime/CMakeLists.txt +++ b/flang-rt/lib/runtime/CMakeLists.txt @@ -12,6 +12,8 @@ find_package(Backtrace) set(HAVE_BACKTRACE ${Backtrace_FOUND}) set(BACKTRACE_HEADER ${Backtrace_HEADER}) +# set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Werror") + # List of files that are buildable for all devices. set(supported_sources ${FLANG_SOURCE_DIR}/lib/Decimal/binary-to-decimal.cpp diff --git a/flang-rt/lib/runtime/assign.cpp b/flang-rt/lib/runtime/assign.cpp index b70182ccb3178..303ec79de240c 100644 --- a/flang-rt/lib/runtime/assign.cpp +++ b/flang-rt/lib/runtime/assign.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "flang/Runtime/assign.h" +#include "flang/Runtime/stop.h" #include "flang-rt/runtime/assign-impl.h" #include "flang-rt/runtime/derived.h" #include "flang-rt/runtime/descriptor.h" @@ -861,6 +862,17 @@ void RTDEF(AssignPolymorphic)(Descriptor &to, const Descriptor &from, PolymorphicLHS); } +#if defined(OMP_OFFLOAD_BUILD) +// To support a recently added use of variant in the OpenMP offload build, +// added an abort wrapper which calls the flang-rt FortranAAbort. +// Avoids the following linker error: +// ld.lld: error: undefined symbol: abort +// >>> referenced by /tmp/device_aassign.amdgcn.gfx90a-34a7ed.img.lto.o:(std::__throw_bad_variant_access(char const*)) +extern "C" void abort(void) { + RTNAME(Abort)(); +} +#endif + RT_EXT_API_GROUP_END } // extern "C" } // namespace Fortran::runtime diff --git a/flang-rt/lib/runtime/copy.cpp b/flang-rt/lib/runtime/copy.cpp index 8b7db61b014e1..22f4def1055b1 100644 --- a/flang-rt/lib/runtime/copy.cpp +++ b/flang-rt/lib/runtime/copy.cpp @@ -9,6 +9,7 @@ #include "copy.h" #include "stack.h" #include "flang-rt/runtime/descriptor.h" +#include "flang-rt/runtime/tools.h" #include "flang-rt/runtime/terminator.h" #include "flang-rt/runtime/type-info.h" #include "flang/Runtime/allocatable.h" diff --git a/flang-rt/lib/runtime/descriptor.cpp b/flang-rt/lib/runtime/descriptor.cpp index 5ede5f9d9f9ed..c95da0a5371e5 100644 --- a/flang-rt/lib/runtime/descriptor.cpp +++ b/flang-rt/lib/runtime/descriptor.cpp @@ -27,7 +27,7 @@ RT_OFFLOAD_API_GROUP_BEGIN RT_API_ATTRS Descriptor::Descriptor(const Descriptor &that) { *this = that; } RT_API_ATTRS Descriptor &Descriptor::operator=(const Descriptor &that) { - runtime::memcpy(reinterpret_cast(this), &that, that.SizeInBytes()); + runtime::memcpy(this, &that, that.SizeInBytes()); return *this; } diff --git a/flang-rt/lib/runtime/io-api-minimal.cpp b/flang-rt/lib/runtime/io-api-minimal.cpp index fdf7183ed5176..f84b62d63baa1 100644 --- a/flang-rt/lib/runtime/io-api-minimal.cpp +++ b/flang-rt/lib/runtime/io-api-minimal.cpp @@ -19,7 +19,9 @@ #include "flang/Runtime/io-api.h" namespace Fortran::runtime::io { +#ifdef RT_OFFLOAD_IO RT_EXT_API_GROUP_BEGIN +#endif Cookie IODEF(BeginExternalListOutput)( ExternalUnit unitNumber, const char *sourceFile, int sourceLine) { @@ -161,4 +163,6 @@ void std::__libcpp_verbose_abort(char const *format, ...) noexcept( } #endif +#ifdef RT_OFFLOAD_IO RT_EXT_API_GROUP_END +#endif diff --git a/flang-rt/lib/runtime/io-api.cpp b/flang-rt/lib/runtime/io-api.cpp index da324f392e008..4c86fb9fdabf6 100644 --- a/flang-rt/lib/runtime/io-api.cpp +++ b/flang-rt/lib/runtime/io-api.cpp @@ -31,7 +31,9 @@ #include namespace Fortran::runtime::io { +#ifdef RT_OFFLOAD_IO RT_EXT_API_GROUP_BEGIN +#endif template RT_API_ATTRS Cookie BeginInternalArrayListIO(const Descriptor &descriptor, @@ -1319,5 +1321,7 @@ enum Iostat IODEF(CheckUnitNumberInRange128)(common::int128_t unit, } #endif +#ifdef RT_OFFLOAD_IO RT_EXT_API_GROUP_END +#endif } // namespace Fortran::runtime::io diff --git a/flang-rt/lib/runtime/io-stmt.cpp b/flang-rt/lib/runtime/io-stmt.cpp index b958f23cf5342..f415d8f539e93 100644 --- a/flang-rt/lib/runtime/io-stmt.cpp +++ b/flang-rt/lib/runtime/io-stmt.cpp @@ -1112,8 +1112,8 @@ ChildListIoStatementState::ChildListIoStatementState( if constexpr (DIR == Direction::Input) { if (const auto *listInput{child.parent() .get_if>()}) { - this->set_eatComma(listInput->eatComma()); this->namelistGroup_ = listInput->namelistGroup(); + this->set_eatComma(listInput->eatComma()); if (auto *childListInput{child.parent() .get_if>()}) { // Child list input whose parent is child list input: can advance diff --git a/flang-rt/lib/runtime/main.cpp b/flang-rt/lib/runtime/main.cpp index b3f066cda3732..27ba9c061cae3 100644 --- a/flang-rt/lib/runtime/main.cpp +++ b/flang-rt/lib/runtime/main.cpp @@ -12,6 +12,7 @@ #include #include #include +#include static void ConfigureFloatingPoint() { #ifdef feclearexcept // a macro in some environments; omit std:: @@ -26,6 +27,9 @@ static void ConfigureFloatingPoint() { #endif } +std::thread::id _main_thread_id = std::this_thread::get_id(); +std::thread::id RTNAME(GetMainThreadId)() { return _main_thread_id; } + extern "C" { void RTNAME(ProgramStart)(int argc, const char *argv[], const char *envp[], const EnvironmentDefaultList *envDefaults) { diff --git a/flang-rt/lib/runtime/stop.cpp b/flang-rt/lib/runtime/stop.cpp index 66b3c1d2a9b4e..a12e9f14d90ec 100644 --- a/flang-rt/lib/runtime/stop.cpp +++ b/flang-rt/lib/runtime/stop.cpp @@ -13,9 +13,11 @@ #include "flang-rt/runtime/file.h" #include "flang-rt/runtime/io-error.h" #include "flang-rt/runtime/terminator.h" +#include "flang/Runtime/main.h" #include #include #include +#include #ifdef HAVE_BACKTRACE #include BACKTRACE_HEADER @@ -96,6 +98,8 @@ static void CloseAllExternalUnits(const char *why) { std::fputc('\n', stderr); DescribeIEEESignaledExceptions(); } + if (RTNAME(GetMainThreadId)() != std::this_thread::get_id()) + std::abort(); std::exit(code); #endif } @@ -123,6 +127,8 @@ static void CloseAllExternalUnits(const char *why) { } DescribeIEEESignaledExceptions(); } + if (RTNAME(GetMainThreadId)() != std::this_thread::get_id()) + std::abort(); if (isErrorStop) { std::exit(EXIT_FAILURE); } else { diff --git a/flang-rt/lib/runtime/temporary-stack.cpp b/flang-rt/lib/runtime/temporary-stack.cpp index 4bc161f83b29a..c3b67167d2281 100644 --- a/flang-rt/lib/runtime/temporary-stack.cpp +++ b/flang-rt/lib/runtime/temporary-stack.cpp @@ -228,6 +228,7 @@ void RTNAME(DescriptorAt)(void *opaquePtr, uint64_t i, Descriptor &value) { void RTNAME(DestroyDescriptorStack)(void *opaquePtr) { DescriptorStack::destroy(getDescriptorStorage(opaquePtr)); } + RT_EXT_API_GROUP_END } // extern "C" } // namespace Fortran::runtime diff --git a/flang-rt/lib/runtime/terminator.cpp b/flang-rt/lib/runtime/terminator.cpp index 97ca824342b15..0ee7faa9082ca 100644 --- a/flang-rt/lib/runtime/terminator.cpp +++ b/flang-rt/lib/runtime/terminator.cpp @@ -45,7 +45,8 @@ RT_API_ATTRS void Terminator::CrashHeader() const { #if defined(RT_DEVICE_COMPILATION) std::printf("\nfatal Fortran runtime error"); if (sourceFileName_) { - std::printf("(%s", sourceFileName_); + // commenting out temporarily to avoid ICE seen with amd-staging + // std::printf("(%s", sourceFileName_); if (sourceLine_) { std::printf(":%d", sourceLine_); } diff --git a/flang-rt/lib/runtime/unit.h b/flang-rt/lib/runtime/unit.h index 7aeea0931e01a..d34b611a867dc 100644 --- a/flang-rt/lib/runtime/unit.h +++ b/flang-rt/lib/runtime/unit.h @@ -21,7 +21,9 @@ #include "flang-rt/runtime/lock.h" #include "flang-rt/runtime/memory.h" #include "flang-rt/runtime/terminator.h" +RT_OFFLOAD_VAR_GROUP_BEGIN #include "flang/Common/constexpr-bitset.h" +RT_OFFLOAD_VAR_GROUP_END #include "flang/Common/optional.h" #include #include diff --git a/flang/EnableFlangBuild b/flang/EnableFlangBuild new file mode 100644 index 0000000000000..fb5dbc49bf7ff --- /dev/null +++ b/flang/EnableFlangBuild @@ -0,0 +1 @@ +DisableClassic diff --git a/flang/EnableFlangRT b/flang/EnableFlangRT new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/flang/docs/DoConcurrentConversionToOpenMP-atd.md b/flang/docs/DoConcurrentConversionToOpenMP-atd.md new file mode 100644 index 0000000000000..10e30f862de6c --- /dev/null +++ b/flang/docs/DoConcurrentConversionToOpenMP-atd.md @@ -0,0 +1,332 @@ + + +# `DO CONCURENT` mapping to OpenMP + +```{contents} +--- +local: +--- +``` + +This document seeks to describe the effort to parallelize `do concurrent` loops +by mapping them to OpenMP worksharing constructs. The goals of this document +are: +* Describing how to instruct `flang` to map `DO CONCURENT` loops to OpenMP + constructs. +* Tracking the current status of such mapping. +* Describing the limitations of the current implmenentation. +* Describing next steps. + +## Usage + +In order to enable `do concurrent` to OpenMP mapping, `flang` adds a new +compiler flag: `-fdo-concurrent-parallel`. This flags has 3 possible values: +1. `host`: this maps `do concurent` loops to run in parallel on the host CPU. + This maps such loops to the equivalent of `omp parallel do`. +2. `device`: this maps `do concurent` loops to run in parallel on a device + (GPU). This maps such loops to the equivalent of `omp target teams + distribute parallel do`. +3. `none`: this disables `do concurrent` mapping altogether. In such case, such + loops are emitted as sequential loops. + +The above compiler switch is currently avaialble only when OpenMP is also +enabled. So you need to provide the following options to flang in order to +enable it: +``` +flang ... -fopenmp -fdo-concurrent-parallel=[host|device|none] ... +``` + +## Current status + +Under the hood, `do concurrent` mapping is implemented in the +`DoConcurrentConversionPass`. This is still an experimental pass which means +that: +* It has been tested in a very limited way so far. +* It has been tested on simple synthetic inputs. + +To describe current status in more detail, following is a description of how +the pass currently behaves for single-range loops and then for multi-range +loops. + +### Single-range loops + +Given the following loop: +```fortran + do concurrent(i=1:n) + a(i) = i * i + end do +``` + +#### Mapping to `host` + +Mapping this loop to the `host`, generates MLIR operations of the following +structure: + +```mlir +%4 = fir.address_of(@_QFEa) ... +%6:2 = hlfir.declare %4 ... + +omp.parallel { + // Allocate private copy for `i`. + %19 = fir.alloca i32 {bindc_name = "i"} + %20:2 = hlfir.declare %19 {uniq_name = "_QFEi"} ... + + omp.wsloop { + omp.loop_nest (%arg0) : index = (%21) to (%22) inclusive step (%c1_2) { + %23 = fir.convert %arg0 : (index) -> i32 + // Use the privatized version of `i`. + fir.store %23 to %20#1 : !fir.ref + ... + + // Use "shared" SSA value of `a`. + %42 = hlfir.designate %6#0 + hlfir.assign %35 to %42 + ... + omp.yield + } + omp.terminator + } + omp.terminator +} +``` + +#### Mapping to `device` + +Mapping the same loop to the `device`, generates MLIR operations of the +following structure: + +```mlir +// Map `a` to the `target` region. +%29 = omp.map.info ... {name = "_QFEa"} +omp.target ... map_entries(..., %29 -> %arg4 ...) { + ... + %51:2 = hlfir.declare %arg4 + ... + omp.teams { + // Allocate private copy for `i`. + %52 = fir.alloca i32 {bindc_name = "i"} + %53:2 = hlfir.declare %52 + ... + + omp.distribute { + omp.parallel { + omp.wsloop { + omp.loop_nest (%arg5) : index = (%54) to (%55) inclusive step (%c1_9) { + // Use the privatized version of `i`. + %56 = fir.convert %arg5 : (index) -> i32 + fir.store %56 to %53#1 + ... + // Use the mapped version of `a`. + ... = hlfir.designate %51#0 + ... + } + omp.terminator + } + omp.terminator + } + omp.terminator + } + omp.terminator + } + omp.terminator +} +``` + +### Multi-range loops + +The pass currently supports multi-range loops as well. Given the following +example: + +```fortran + do concurrent(i=1:n, j=1:m) + a(i,j) = i * j + end do +``` + +The generated `omp.loop_nest` operation look like: + +```mlir +omp.loop_nest (%arg0, %arg1) + : index = (%17, %19) to (%18, %20) + inclusive step (%c1_2, %c1_4) { + fir.store %arg0 to %private_i#1 : !fir.ref + fir.store %arg1 to %private_j#1 : !fir.ref + ... + omp.yield +} +``` + +It is worth noting that we have privatized versions for both iteration +variables: `i` and `j`. These are locally allocated inside the parallel/target +OpenMP region similar to what the single-range example in previous section +shows. + +#### Multi-range and perfectly-nested loops + +Currently, on the `FIR` dialect level, the following 2 loops are modelled in +exactly the same way: + +```fortran +do concurrent(i=1:n, j=1:m) + a(i,j) = i * j +end do +``` + +```fortran +do concurrent(i=1:n) + do concurrent(j=1:m) + a(i,j) = i * j + end do +end do +``` + +Both of the above loops are modelled as: + +```mlir +fir.do_loop %arg0 = %11 to %12 step %c1 unordered { + ... + fir.do_loop %arg1 = %14 to %15 step %c1_1 unordered { + ... + } +} +``` + +Consequently, from the `DoConcurrentConversionPass`' perspective, both loops +are treated in the same manner. Under the hood, the pass detects +perfectly-nested loop nests and maps such nests as if they were multi-range +loops. + +#### Non-perfectly-nested loops + +One limitation that the pass currently have is that it treats any intervening +code in a loop nest as being disruptive to detecting that nest as a single +unit. For example, given the following input: + +```fortran +do concurrent(i=1:n) + x = 41 + do concurrent(j=1:m) + a(i,j) = i * j + end do +end do +``` + +Since there at least one statement between the 2 loop header (i.e. `x = 41`), +the pass does not detect the `i` and `j` loops as a nest. Rather, the pass in +that case only maps the `i` loop to OpenMP and leaves the `j` loop in its +origianl form. In theory, in this example, we can sink the intervening code +into the `j` loop and detect the complete nest. However, such transformation is +still to be implemented in the future. + +The above also has the consequence that the `j` variable will **not** be +privatized in the OpenMP parallel/target region. In other words, it will be +treated as if it was a `shared` variable. For more details about privatization, +see the "Data environment" section below. + +### Data environment + +By default, variables that are used inside a `do concurernt` loop nest are +either treated as `shared` in case of mapping to `host`, or mapped into the +`target` region using a `map` clause in case of mapping to `device`. The only +exceptions to this are: + 1. the loop's iteration variable(s) (IV) of **perfect** loop nests. In that + case, for each IV, we allocate a local copy as shown the by the mapping + examples above. + 1. any values that are from allocations outside the loop nest and used + exclusively inside of it. In such cases, a local privatized + value is created in the OpenMP region to prevent multiple teams of threads + from accessing and destroying the same memory block which causes runtime + issues. For an example of such cases, see + `flang/test/Transforms/DoConcurrent/locally_destroyed_temp.f90`. + +#### Non-perfectly-nested loops' IVs + +For non-perfectly-nested loops, the IVs are still treated as `shared` or +`map` entries as pointed out above. This **might not** be consistent with what +the Fortran specficiation tells us. In particular, taking the following +snippets from the spec (version 2023) into account: + +> § 3.35 +> ------ +> construct entity +> entity whose identifier has the scope of a construct + +> § 19.4 +> ------ +> A variable that appears as an index-name in a FORALL or DO CONCURRENT +> construct, or ... is a construct entity. A variable that has LOCAL or +> LOCAL_INIT locality in a DO CONCURRENT construct is a construct entity. +> ... +> The name of a variable that appears as an index-name in a DO CONCURRENT +> construct, FORALL statement, or FORALL construct has a scope of the statement +> or construct. A variable that has LOCAL or LOCAL_INIT locality in a DO +> CONCURRENT construct has the scope of that construct. + +From the above quotes, it seems there is an equivalence between the IV of a `do +concurrent` loop and a variable with a `LOCAL` locality specifier (equivalent +to OpenMP's `private` clause). Which means that we should probably +localize/privatize a `do concurernt` loop's IV even if it is not perfectly +nested in the nest we are parallelizing. For now, however, we **do not** do +that as pointed out previously. In the near future, we propose a middle-ground +solution (see the Next steps section for more details). + +## Next steps + +### Delayed privatization + +So far, we emit the privatization logic for IVs inline in the parallel/target +region. This is enough for our purposes right now since we don't +localize/privatize any sophisticated types of variables yet. Once we have need +for more advanced localization through `do concurrent`'s locality specifiers +(see below), delayed privatization will enable us to have a much cleaner IR. +Once delayed privatization's implementation upstream is supported for the +required constructs by the pass, we will move to it rather than inlined/early +privatization. + +### Locality specifiers for `do concurrent` + +Locality specifiers will enable the user to control the data environment of the +loop nest in a more fine-grained way. Implementing these specifiers on the +`FIR` dialect level is needed in order to support this in the +`DoConcurrentConversionPass`. + +Such specified will also unlock a potential solution to the +non-perfectly-nested loops' IVs issue described above. In particular, for a +non-perfectly nested loop, one middle-ground proposal/solution would be to: +* Emit the loop's IV as shared/mapped just like we do currently. +* Emit a warning that the IV of the loop is emitted as shared/mapped. +* Given support for `LOCAL`, we can recommend the user to explicitly + localize/privatize the loop's IV if they choose to. + +### More advanced detection of loop nests + +As pointed out earlier, any intervening code between the headers of 2 nested +`do concurrent` loops prevents us currently from detecting this as a loop nest. +In some cases this is overly conservative. Therefore, a more flexible detection +logic of loop nests needs to be implemented. + +### Data-dependence analysis + +Right now, we map loop nests without analysing whether such mapping is safe to +do or not. We probalby need to at least warn the use of unsafe loop nests due +to loop-carried dependencies. + +### Non-rectangular loop nests + +So far, we did not need to use the pass for non-rectangular loop nests. For +example: +```fortran +do concurrent(i=1:n) + do concurrent(j=i:n) + ... + end do +end do +``` +We defer this to the (hopefully) near future when we get the conversion in a +good share for the samples/projects at hand. diff --git a/flang/include/flang/Common/float128.h b/flang/include/flang/Common/float128.h index eddd3cf25382e..74e5e6c9924ef 100644 --- a/flang/include/flang/Common/float128.h +++ b/flang/include/flang/Common/float128.h @@ -36,7 +36,8 @@ #undef HAS_FLOAT128 #if (defined(__FLOAT128__) || defined(__SIZEOF_FLOAT128__)) && \ - !defined(_LIBCPP_VERSION) && !defined(__CUDA_ARCH__) + !defined(_LIBCPP_VERSION) && !defined(__CUDA_ARCH__) && \ + !defined(OMP_OFFLOAD_BUILD) /* * It may still be worth checking for compiler versions, * since earlier versions may define the macros above, but @@ -50,13 +51,15 @@ #define HAS_FLOAT128 1 #endif #endif /* (defined(__FLOAT128__) || defined(__SIZEOF_FLOAT128__)) && \ - !defined(_LIBCPP_VERSION) && !defined(__CUDA_ARCH__) */ + !defined(_LIBCPP_VERSION) && !defined(__CUDA_ARCH__) && \ + !defined(OMP_OFFLOAD_BUILD) */ #if LDBL_MANT_DIG == 113 #define HAS_LDBL128 1 #endif -#if defined(RT_DEVICE_COMPILATION) && defined(__CUDACC__) +#if defined(RT_DEVICE_COMPILATION) && (defined(__CUDACC__) || \ + defined(OMP_OFFLOAD_BUILD)) /* * Most offload targets do not support 128-bit 'long double'. * Disable HAS_LDBL128 for __CUDACC__ for the time being. diff --git a/flang/include/flang/Frontend/CodeGenOptions.def b/flang/include/flang/Frontend/CodeGenOptions.def index dc3da7ba5c7f3..285998e4d5a91 100644 --- a/flang/include/flang/Frontend/CodeGenOptions.def +++ b/flang/include/flang/Frontend/CodeGenOptions.def @@ -51,6 +51,9 @@ CODEGENOPT(AliasAnalysis, 1, 0) ///< Enable alias analysis pass CODEGENOPT(DwarfVersion, 3, 0) ///< Dwarf version CODEGENOPT(Underscoring, 1, 1) +CODEGENOPT(OffloadGlobalFiltering, 1, 0) +CODEGENOPT(DeferDescriptorMapping, 1, 0) ///< Fortran OpenMP specific optimisation for delaying descriptor mapping until target/target data regions + ENUM_CODEGENOPT(RelocationModel, llvm::Reloc::Model, 3, llvm::Reloc::PIC_) ///< Name of the relocation model to use. ENUM_CODEGENOPT(DebugInfo, llvm::codegenoptions::DebugInfoKind, 4, llvm::codegenoptions::NoDebugInfo) ///< Level of debug info to generate ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 4, llvm::driver::VectorLibrary::NoLibrary) ///< Vector functions library to use diff --git a/flang/include/flang/Lower/DirectivesCommon.h b/flang/include/flang/Lower/DirectivesCommon.h index 2d6906738773a..707c8f88e00d9 100644 --- a/flang/include/flang/Lower/DirectivesCommon.h +++ b/flang/include/flang/Lower/DirectivesCommon.h @@ -263,7 +263,10 @@ genBoundsOps(fir::FirOpBuilder &builder, mlir::Location loc, // If it is a scalar subscript, then the upper bound // is equal to the lower bound, and the extent is one. ubound = lbound; - extent = one; + if (treatIndexAsSection) + extent = fir::factory::readExtent(builder, loc, dataExv, dimension); + else + extent = one; } else { asFortran << ':'; Fortran::semantics::MaybeExpr upper = diff --git a/flang/lib/Lower/OpenMP/Utils.h b/flang/include/flang/Lower/OpenMP/Utils.h similarity index 100% rename from flang/lib/Lower/OpenMP/Utils.h rename to flang/include/flang/Lower/OpenMP/Utils.h diff --git a/flang/include/flang/Lower/Support/ReductionProcessor.h b/flang/include/flang/Lower/Support/ReductionProcessor.h index 66f26b3b55630..905784d25fdb2 100644 --- a/flang/include/flang/Lower/Support/ReductionProcessor.h +++ b/flang/include/flang/Lower/Support/ReductionProcessor.h @@ -16,7 +16,6 @@ #include "flang/Lower/OpenMP/Clauses.h" #include "flang/Optimizer/Builder/FIRBuilder.h" #include "flang/Optimizer/Dialect/FIRType.h" -#include "flang/Parser/parse-tree.h" #include "flang/Semantics/symbol.h" #include "flang/Semantics/type.h" #include "mlir/IR/Location.h" diff --git a/flang/include/flang/Optimizer/Builder/Runtime/Main.h b/flang/include/flang/Optimizer/Builder/Runtime/Main.h index d4067b367f73e..a95218ce97f16 100644 --- a/flang/include/flang/Optimizer/Builder/Runtime/Main.h +++ b/flang/include/flang/Optimizer/Builder/Runtime/Main.h @@ -25,7 +25,8 @@ namespace fir::runtime { void genMain(fir::FirOpBuilder &builder, mlir::Location loc, const std::vector &defs, - bool initCuda = false, bool initCoarrayEnv = false); + bool initCuda = false, bool enableAmdAllocatori = false, + bool initCoarrayEnv = false); } #endif // FORTRAN_OPTIMIZER_BUILDER_RUNTIME_MAIN_H diff --git a/flang/include/flang/Optimizer/OpenMP/Passes.h b/flang/include/flang/Optimizer/OpenMP/Passes.h index c67bddbcd2704..fc55efe71a5e4 100644 --- a/flang/include/flang/Optimizer/OpenMP/Passes.h +++ b/flang/include/flang/Optimizer/OpenMP/Passes.h @@ -22,6 +22,7 @@ #include namespace flangomp { + #define GEN_PASS_DECL #define GEN_PASS_REGISTRATION #include "flang/Optimizer/OpenMP/Passes.h.inc" @@ -32,6 +33,8 @@ namespace flangomp { bool shouldUseWorkshareLowering(mlir::Operation *op); std::unique_ptr createDoConcurrentConversionPass(bool mapToDevice); + +std::unique_ptr createMapInfoFinalizationPass(bool deferDescMap); } // namespace flangomp #endif // FORTRAN_OPTIMIZER_OPENMP_PASSES_H diff --git a/flang/include/flang/Optimizer/OpenMP/Passes.td b/flang/include/flang/Optimizer/OpenMP/Passes.td index bfbaa5f838e90..8d30f165dd8b6 100644 --- a/flang/include/flang/Optimizer/OpenMP/Passes.td +++ b/flang/include/flang/Optimizer/OpenMP/Passes.td @@ -10,6 +10,7 @@ #define FORTRAN_OPTIMIZER_OPENMP_PASSES include "mlir/Pass/PassBase.td" +include "mlir/IR/EnumAttr.td" def MapInfoFinalizationPass : Pass<"omp-map-info-finalization", "mlir::ModuleOp"> { @@ -20,6 +21,12 @@ def MapInfoFinalizationPass explicit individual mapping by the OpenMP runtime. }]; let dependentDialects = ["mlir::omp::OpenMPDialect"]; + + let options = [Option<"deferDescMapping", "opt-defer-desc-mapping", + "bool", /*default=*/"true", + "Activates or deactivates deferred descriptor mapping, " + "which delays mapping of top-level descriptors to target " + "regions and target data regions">]; } def MapsForPrivatizedSymbolsPass @@ -44,6 +51,16 @@ def MarkDeclareTargetPass def FunctionFilteringPass : Pass<"omp-function-filtering"> { let summary = "Filters out functions intended for the host when compiling " "for the target device."; + let dependentDialects = [ + "mlir::func::FuncDialect", + "fir::FIROpsDialect", + "mlir::omp::OpenMPDialect" + ]; +} + +def GlobalFilteringPass : Pass<"omp-global-filtering"> { + let summary = "Filters out globals intended for the host when compiling " + "for the target device."; let dependentDialects = [ "mlir::func::FuncDialect", "fir::FIROpsDialect" diff --git a/flang/include/flang/Optimizer/Passes/Pipelines.h b/flang/include/flang/Optimizer/Passes/Pipelines.h index 70b9341347244..f673a5d5ec27f 100644 --- a/flang/include/flang/Optimizer/Passes/Pipelines.h +++ b/flang/include/flang/Optimizer/Passes/Pipelines.h @@ -136,6 +136,12 @@ struct OpenMPFIRPassPipelineOpts { /// Whether code is being generated for a target device rather than the host /// device bool isTargetDevice; + bool enableOffloadGlobalFiltering; + + /// Deactivates or activates MapInfoFinalization passes removal of + /// top-level descriptor mapping for non-Target Data/Target region + /// directives. + bool deferDescMap; /// Controls how to map `do concurrent` loops; to device, host, or none at /// all. diff --git a/flang/include/flang/Optimizer/Transforms/Passes.h b/flang/include/flang/Optimizer/Transforms/Passes.h index 6f5dff4687cbb..8c6399eed8d1e 100644 --- a/flang/include/flang/Optimizer/Transforms/Passes.h +++ b/flang/include/flang/Optimizer/Transforms/Passes.h @@ -10,10 +10,12 @@ #define FORTRAN_OPTIMIZER_TRANSFORMS_PASSES_H #include "flang/Optimizer/Dialect/FIROps.h" +#include "flang/Optimizer/Transforms/Utils.h" #include "mlir/Dialect/LLVMIR/LLVMAttrs.h" #include "mlir/Dialect/OpenMP/OpenMPDialect.h" #include "mlir/Pass/Pass.h" #include "mlir/Pass/PassRegistry.h" + #include namespace mlir { diff --git a/flang/include/flang/Optimizer/Transforms/Utils.h b/flang/include/flang/Optimizer/Transforms/Utils.h index 49a616fb40fd5..c89330f4398fe 100644 --- a/flang/include/flang/Optimizer/Transforms/Utils.h +++ b/flang/include/flang/Optimizer/Transforms/Utils.h @@ -13,8 +13,13 @@ #ifndef FORTRAN_OPTIMIZER_TRANSFORMS_UTILS_H #define FORTRAN_OPTIMIZER_TRANSFORMS_UTILS_H +#include "mlir/IR/Location.h" +#include "mlir/IR/Value.h" + namespace fir { +class FirOpBuilder; + using MinlocBodyOpGeneratorTy = llvm::function_ref &)>; diff --git a/flang/include/flang/Runtime/AMD/amd_alloc.h b/flang/include/flang/Runtime/AMD/amd_alloc.h new file mode 100644 index 0000000000000..65c8e0315c0cb --- /dev/null +++ b/flang/include/flang/Runtime/AMD/amd_alloc.h @@ -0,0 +1,24 @@ +//===-- include/flang/Runtime/AMD/amd_alloc.h -------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef FORTRAN_RUNTIME_AMD_UMPIRE_H_ +#define FORTRAN_RUNTIME_AMD_UMPIRE_H_ + +// TODO: check of the following two includes are necessary: +#include "flang/Runtime/descriptor-consts.h" +#include "flang/Runtime/entry-names.h" + +namespace Fortran::runtime::amd { + +extern "C" { +void RTDECL(AMDRegisterAllocator)(); +void RTDECL(AMDAllocatableSetAllocIdx)(Descriptor &descriptor, int pos); +} + +} // namespace Fortran::runtime::amd +#endif // FORTRAN_RUNTIME_AMD_UMPIRE_H_ diff --git a/flang/include/flang/Runtime/freestanding-tools.h b/flang/include/flang/Runtime/freestanding-tools.h index 7ef7cc74f213b..f1b78225db324 100644 --- a/flang/include/flang/Runtime/freestanding-tools.h +++ b/flang/include/flang/Runtime/freestanding-tools.h @@ -24,6 +24,16 @@ #define STD_FILL_N_UNSUPPORTED 1 #endif +#if !defined(STD_MEMSET_UNSUPPORTED) && \ + (defined(__CUDACC__) || defined(__CUDA__)) && defined(__CUDA_ARCH__) +#define STD_MEMSET_UNSUPPORTED 1 +#endif + +#if !defined(STD_MEMCPY_UNSUPPORTED) && \ + (defined(__CUDACC__) || defined(__CUDA__)) && defined(__CUDA_ARCH__) +#define STD_MEMCPY_UNSUPPORTED 1 +#endif + #if !defined(STD_MEMMOVE_UNSUPPORTED) && \ (defined(__CUDACC__) || defined(__CUDA__)) && defined(__CUDA_ARCH__) #define STD_MEMMOVE_UNSUPPORTED 1 diff --git a/flang/include/flang/Runtime/main.h b/flang/include/flang/Runtime/main.h index 88232ea64fa6a..40f7693221b6a 100644 --- a/flang/include/flang/Runtime/main.h +++ b/flang/include/flang/Runtime/main.h @@ -11,9 +11,12 @@ #include "flang/Runtime/c-or-cpp.h" #include "flang/Runtime/entry-names.h" +#include struct EnvironmentDefaultList; +std::thread::id RTNAME(GetMainThreadId)(); + FORTRAN_EXTERN_C_BEGIN void RTNAME(ProgramStart)( int, const char *[], const char *[], const struct EnvironmentDefaultList *); diff --git a/flang/include/flang/Runtime/stop.h b/flang/include/flang/Runtime/stop.h index 81c28904efcbe..4ddc5cf49ec8f 100644 --- a/flang/include/flang/Runtime/stop.h +++ b/flang/include/flang/Runtime/stop.h @@ -30,9 +30,7 @@ NORETURN void RTNAME(ProgramEndStatement)(NO_ARGUMENTS); // Extensions NORETURN void RTNAME(Exit)(int status DEFAULT_VALUE(EXIT_SUCCESS)); -RT_OFFLOAD_API_GROUP_BEGIN NORETURN void RTNAME(Abort)(NO_ARGUMENTS); -RT_OFFLOAD_API_GROUP_END void FORTRAN_PROCEDURE_NAME(backtrace)(NO_ARGUMENTS); // Crash with an error message when the program dynamically violates a Fortran diff --git a/flang/include/flang/Support/Fortran-features.h b/flang/include/flang/Support/Fortran-features.h index c7d0b7fca1d59..ecccce0a9f862 100644 --- a/flang/include/flang/Support/Fortran-features.h +++ b/flang/include/flang/Support/Fortran-features.h @@ -55,8 +55,9 @@ ENUM_CLASS(LanguageFeature, BackslashEscapes, OldDebugLines, SavedLocalInSpecExpr, PrintNamelist, AssumedRankPassedToNonAssumedRank, IgnoreIrrelevantAttributes, Unsigned, AmbiguousStructureConstructor, ContiguousOkForSeqAssociation, ForwardRefExplicitTypeDummy, - InaccessibleDeferredOverride, CudaWarpMatchFunction, DoConcurrentOffload, - TransferBOZ, Coarray) + InaccessibleDeferredOverride, + AmdMemoryAllocator, CudaWarpMatchFunction, + DoConcurrentOffload, TransferBOZ, Coarray) // Portability and suspicious usage warnings ENUM_CLASS(UsageWarning, Portability, PointerToUndefinable, diff --git a/flang/include/flang/Support/LangOptions.def b/flang/include/flang/Support/LangOptions.def index e7185c836f45b..c671ce8e24a4a 100644 --- a/flang/include/flang/Support/LangOptions.def +++ b/flang/include/flang/Support/LangOptions.def @@ -62,6 +62,7 @@ LANGOPT(OpenMPNoNestedParallelism, 1, 0) LANGOPT(OpenMPSimd, 1, false) /// Enable fast MOD operations for REAL LANGOPT(NoFastRealMod, 1, false) +LANGOPT(AllowThreadprivateEquivalence, 1, false) LANGOPT(VScaleMin, 32, 0) ///< Minimum vscale range value LANGOPT(VScaleMax, 32, 0) ///< Maximum vscale range value diff --git a/flang/include/flang/Support/OpenMP-utils.h b/flang/include/flang/Support/OpenMP-utils.h index 6d9db2b682c50..dc938db88e17d 100644 --- a/flang/include/flang/Support/OpenMP-utils.h +++ b/flang/include/flang/Support/OpenMP-utils.h @@ -9,8 +9,13 @@ #ifndef FORTRAN_SUPPORT_OPENMP_UTILS_H_ #define FORTRAN_SUPPORT_OPENMP_UTILS_H_ +#include "flang/Optimizer/Builder/DirectivesCommon.h" +#include "flang/Optimizer/Builder/FIRBuilder.h" +#include "flang/Optimizer/Builder/HLFIRTools.h" +#include "flang/Optimizer/Dialect/FIRType.h" #include "flang/Semantics/symbol.h" +#include "mlir/Dialect/OpenMP/OpenMPDialect.h" #include "mlir/IR/Builders.h" #include "mlir/IR/Value.h" @@ -72,6 +77,35 @@ struct EntryBlockArgs { /// \param [in] region - Empty region in which to create the entry block. mlir::Block *genEntryBlock( mlir::OpBuilder &builder, const EntryBlockArgs &args, mlir::Region ®ion); + +// Returns true if the variable has a dynamic size and therefore requires +// bounds operations to describe its extents. +inline bool needsBoundsOps(mlir::Value var) { + assert(mlir::isa(var.getType()) && + "only pointer like types expected"); + mlir::Type t = fir::unwrapRefType(var.getType()); + if (mlir::Type inner = fir::dyn_cast_ptrOrBoxEleTy(t)) + return fir::hasDynamicSize(inner); + return fir::hasDynamicSize(t); +} + +// Generate MapBoundsOp operations for the variable if required. +inline void genBoundsOps(fir::FirOpBuilder &builder, mlir::Value var, + llvm::SmallVectorImpl &boundsOps) { + mlir::Location loc = var.getLoc(); + fir::factory::AddrAndBoundsInfo info = + fir::factory::getDataOperandBaseAddr(builder, var, + /*isOptional=*/false, loc); + fir::ExtendedValue exv = + hlfir::translateToExtendedValue(loc, builder, hlfir::Entity{info.addr}, + /*contiguousHint=*/true) + .first; + llvm::SmallVector tmp = + fir::factory::genImplicitBoundsOps( + builder, info, exv, /*dataExvIsAssumedSize=*/false, loc); + llvm::append_range(boundsOps, tmp); +} } // namespace Fortran::common::openmp #endif // FORTRAN_SUPPORT_OPENMP_UTILS_H_ diff --git a/flang/include/flang/Tools/CrossToolHelpers.h b/flang/include/flang/Tools/CrossToolHelpers.h index e964882ef6dac..768ec8c553b29 100644 --- a/flang/include/flang/Tools/CrossToolHelpers.h +++ b/flang/include/flang/Tools/CrossToolHelpers.h @@ -189,7 +189,7 @@ struct OffloadModuleOpts { bool OpenMPIsTargetDevice = false; bool OpenMPIsGPU = false; bool OpenMPForceUSM = false; - uint32_t OpenMPVersion = 31; + uint32_t OpenMPVersion = 52; std::string OMPHostIRFile = {}; std::vector OMPTargetTriples = {}; bool NoGPULib = false; diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp index 548ca675db5ea..c6606401f9dd8 100644 --- a/flang/lib/Frontend/CompilerInvocation.cpp +++ b/flang/lib/Frontend/CompilerInvocation.cpp @@ -486,8 +486,18 @@ static void parseCodeGenArgs(Fortran::frontend::CodeGenOptions &opts, opts.Underscoring = 0; } + if (args.hasFlag(clang::driver::options::OPT_foffload_global_filtering, + clang::driver::options::OPT_fno_offload_global_filtering, + false)) { + opts.OffloadGlobalFiltering = 1; + } + parseDoConcurrentMapping(opts, args, diags); + opts.DeferDescriptorMapping = + args.hasFlag(clang::driver::options::OPT_fdefer_desc_map, + clang::driver::options::OPT_fno_defer_desc_map, true); + if (const llvm::opt::Arg *arg = args.getLastArg(clang::driver::options::OPT_complex_range_EQ)) { llvm::StringRef argValue = llvm::StringRef(arg->getValue()); @@ -873,6 +883,12 @@ static bool parseFrontendArgs(FrontendOptions &opts, llvm::opt::ArgList &args, args.hasFlag(clang::driver::options::OPT_fsave_main_program, clang::driver::options::OPT_fno_save_main_program, false)); + // -ffast-amd-memory-allocator + if (args.hasArg(clang::driver::options::OPT_ffast_amd_memory_allocator)) { + opts.features.Enable( + (Fortran::common::LanguageFeature::AmdMemoryAllocator)); + } + if (args.hasArg( clang::driver::options::OPT_falternative_parameter_statement)) { opts.features.Enable(Fortran::common::LanguageFeature::OldStyleParameter); @@ -1188,7 +1204,8 @@ static bool parseOpenMPArgs(CompilerInvocation &res, llvm::opt::ArgList &args, unsigned numErrorsBefore = diags.getNumErrors(); llvm::Triple t(res.getTargetOpts().triple); - constexpr unsigned newestFullySupported = 31; + constexpr unsigned newestFullySupported = 52; + // By default OpenMP is set to 5.2 version constexpr unsigned latestFinalized = 60; // By default OpenMP is set to the most recent fully supported version res.getLangOpts().OpenMPVersion = newestFullySupported; @@ -1229,10 +1246,12 @@ static bool parseOpenMPArgs(CompilerInvocation &res, llvm::opt::ArgList &args, if (llvm::is_contained(ompVersions, version)) { res.getLangOpts().OpenMPVersion = version; +#if ENABLED_FOR_STAGING if (version > latestFinalized) reportFutureVersion(value); else if (version > newestFullySupported) diags.Report(clang::diag::warn_openmp_incomplete) << version; +#endif } else if (llvm::is_contained(oldVersions, version)) { const unsigned diagID = diags.getCustomDiagID(clang::DiagnosticsEngine::Warning, @@ -1340,6 +1359,11 @@ static bool parseOpenMPArgs(CompilerInvocation &res, llvm::opt::ArgList &args, res.getLangOpts().OMPTargetTriples.push_back(tt); } } + + if (args.hasArg( + clang::driver::options::OPT_famd_allow_threadprivate_equivalence)) + res.getLangOpts().AllowThreadprivateEquivalence = true; + return diags.getNumErrors() == numErrorsBefore; } @@ -1754,6 +1778,7 @@ void CompilerInvocation::setDefaultPredefinitions() { auto &fortranOptions = getFortranOpts(); const auto &frontendOptions = getFrontendOpts(); // Populate the macro list with version numbers and other predefinitions. + fortranOptions.predefinitions.emplace_back("__amdflang__", "1"); fortranOptions.predefinitions.emplace_back("__flang__", "1"); fortranOptions.predefinitions.emplace_back("__flang_major__", FLANG_VERSION_MAJOR_STRING); diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp index 159d08a2797b3..b2c9013dd2c47 100644 --- a/flang/lib/Frontend/FrontendActions.cpp +++ b/flang/lib/Frontend/FrontendActions.cpp @@ -314,6 +314,10 @@ bool CodeGenAction::beginSourceFileAction() { Fortran::frontend::CodeGenOptions::DoConcurrentMappingKind; opts.doConcurrentMappingKind = ci.getInvocation().getCodeGenOpts().getDoConcurrentMapping(); + opts.enableOffloadGlobalFiltering = + ci.getInvocation().getCodeGenOpts().OffloadGlobalFiltering; + opts.deferDescMap = + ci.getInvocation().getCodeGenOpts().DeferDescriptorMapping; if (opts.doConcurrentMappingKind != DoConcurrentMappingKind::DCMK_None && !isOpenMPEnabled) { diff --git a/flang/lib/Lower/Allocatable.cpp b/flang/lib/Lower/Allocatable.cpp index e7a6c4df40045..d00561ad5fbac 100644 --- a/flang/lib/Lower/Allocatable.cpp +++ b/flang/lib/Lower/Allocatable.cpp @@ -37,6 +37,7 @@ #include "flang/Runtime/pointer.h" #include "flang/Semantics/tools.h" #include "flang/Semantics/type.h" +#include "mlir/Dialect/OpenMP/OpenMPInterfaces.h" #include "llvm/Support/CommandLine.h" /// By default fir memory operation fir::AllocMemOp/fir::FreeMemOp are used. @@ -174,6 +175,50 @@ static void genRuntimeInitCharacter(fir::FirOpBuilder &builder, fir::CallOp::create(builder, loc, callee, convertedArgs); } +/// Check if region is nested in omp.target or +/// region nested in function with declare target +bool isRegionNestedInOmpTarget(mlir::Region ®ion) { + mlir::Operation *parentOp = region.getParentOp(); + while (parentOp) { + if (auto declareTargetOp = + llvm::dyn_cast(parentOp)) { + if (declareTargetOp.isDeclareTarget()) + return true; + } + if (llvm::isa(parentOp)) + return true; + mlir::Region *parentRegion = parentOp->getParentRegion(); + if (!parentRegion) + break; + parentOp = parentRegion->getParentOp(); + } + + return false; +} + +/// Generate a runtime call to set allocator idx of descriptor for target amd. +static void genAMDRuntimeDescriptorSetAllocIdx(fir::FirOpBuilder &builder, + mlir::Location loc, + const fir::MutableBoxValue &box, + int allocatorId) { + if (isRegionNestedInOmpTarget(builder.getRegion())) + return; + auto *context = builder.getContext(); + mlir::Type descriptorTy = box.getAddr().getType(); + mlir::IntegerType posTy = builder.getI32Type(); + mlir::func::FuncOp callee = builder.createFunction( + loc, RTNAME_STRING(AMDAllocatableSetAllocIdx), + mlir::FunctionType::get(context, {descriptorTy, posTy}, {})); + llvm::SmallVector args{box.getAddr()}; + args.push_back( + builder.createIntegerConstant(loc, builder.getI32Type(), allocatorId)); + llvm::SmallVector operands; + for (auto [fst, snd] : llvm::zip(args, callee.getFunctionType().getInputs())) + operands.emplace_back(builder.createConvert(loc, snd, fst)); + builder.create(loc, callee, operands); + return; +} + /// Generate a sequence of runtime calls to allocate memory. static mlir::Value genRuntimeAllocate(fir::FirOpBuilder &builder, mlir::Location loc, @@ -476,6 +521,9 @@ class AllocateStmtHelper { !alloc.hasCoarraySpec() && !useAllocateRuntime && !box.isPointer(); unsigned allocatorIdx = Fortran::lower::getAllocatorIdx(alloc.getSymbol()); + const auto &langFeatures = converter.getFoldingContext().languageFeatures(); + bool isAMDMemoryAllocatorEnabled = langFeatures.IsEnabled( + Fortran::common::LanguageFeature::AmdMemoryAllocator); if (inlineAllocation && ((isCudaAllocate && isCudaDeviceContext) || !isCudaAllocate)) { @@ -508,6 +556,8 @@ class AllocateStmtHelper { genAllocateObjectBounds(alloc, box); mlir::Value stat; if (!isCudaAllocate) { + if (isAMDMemoryAllocatorEnabled) + genAMDRuntimeDescriptorSetAllocIdx(builder, loc, box, 1); stat = genRuntimeAllocate(builder, loc, box, errorManager); setPinnedToFalse(); } else { @@ -628,6 +678,9 @@ class AllocateStmtHelper { const fir::MutableBoxValue &box, bool isSource) { unsigned allocatorIdx = Fortran::lower::getAllocatorIdx(alloc.getSymbol()); fir::ExtendedValue exv = isSource ? sourceExv : moldExv; + const auto &langFeatures = converter.getFoldingContext().languageFeatures(); + bool isAMDMemoryAllocatorEnabled = langFeatures.IsEnabled( + Fortran::common::LanguageFeature::AmdMemoryAllocator); if (const Fortran::semantics::Symbol *sym{GetLastSymbol(sourceExpr)}) if (Fortran::semantics::IsCUDADevice(*sym)) @@ -655,6 +708,8 @@ class AllocateStmtHelper { stat = genCudaAllocate(builder, loc, box, errorManager, alloc.getSymbol()); } else { + if (isAMDMemoryAllocatorEnabled) + genAMDRuntimeDescriptorSetAllocIdx(builder, loc, box, 1); if (isSource) stat = genRuntimeAllocateSource(builder, loc, box, exv, errorManager); else diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index 1c163e6de7e5a..ce05ab22c880f 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "ClauseProcessor.h" -#include "Utils.h" +#include "flang/Lower/OpenMP/Utils.h" #include "flang/Lower/ConvertExprToHLFIR.h" #include "flang/Lower/OpenMP/Clauses.h" @@ -1169,40 +1169,6 @@ bool ClauseProcessor::processIsDevicePtr( }); } -bool ClauseProcessor::processLinear(mlir::omp::LinearClauseOps &result) const { - lower::StatementContext stmtCtx; - return findRepeatableClause< - omp::clause::Linear>([&](const omp::clause::Linear &clause, - const parser::CharBlock &) { - auto &objects = std::get(clause.t); - for (const omp::Object &object : objects) { - semantics::Symbol *sym = object.sym(); - const mlir::Value variable = converter.getSymbolAddress(*sym); - result.linearVars.push_back(variable); - } - if (objects.size()) { - if (auto &mod = - std::get>( - clause.t)) { - mlir::Value operand = - fir::getBase(converter.genExprValue(toEvExpr(*mod), stmtCtx)); - result.linearStepVars.append(objects.size(), operand); - } else if (std::get>( - clause.t)) { - mlir::Location currentLocation = converter.getCurrentLocation(); - TODO(currentLocation, "Linear modifiers not yet implemented"); - } else { - // If nothing is present, add the default step of 1. - fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); - mlir::Location currentLocation = converter.getCurrentLocation(); - mlir::Value operand = firOpBuilder.createIntegerConstant( - currentLocation, firOpBuilder.getI32Type(), 1); - result.linearStepVars.append(objects.size(), operand); - } - } - }); -} - bool ClauseProcessor::processLink( llvm::SmallVectorImpl &result) const { return findRepeatableClause( @@ -1220,7 +1186,7 @@ void ClauseProcessor::processMapObjects( std::map &parentMemberIndices, llvm::SmallVectorImpl &mapVars, llvm::SmallVectorImpl &mapSyms, - llvm::StringRef mapperIdNameRef) const { + llvm::StringRef mapperIdNameRef, bool isMotionModifier) const { fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); auto getDefaultMapperID = [&](const omp::Object &object, @@ -1272,7 +1238,7 @@ void ClauseProcessor::processMapObjects( treatIndexAsSection); mlir::Value baseOp = info.rawInput; - if (object.sym()->owner().IsDerivedType()) { + if (object.sym()->owner().IsDerivedType() && !isMotionModifier) { omp::ObjectList objectList = gatherObjectsOf(object, semaCtx); assert(!objectList.empty() && "could not find parent objects of derived type member"); @@ -1434,7 +1400,8 @@ bool ClauseProcessor::processMotionClauses(lower::StatementContext &stmtCtx, if (expectation && *expectation == omp::clause::To::Expectation::Present) mapTypeBits |= mlir::omp::ClauseMapFlags::present; processMapObjects(stmtCtx, clauseLocation, objects, mapTypeBits, - parentMemberIndices, result.mapVars, mapSymbols); + parentMemberIndices, result.mapVars, mapSymbols, "", + true); }; bool clauseFound = findRepeatableClause(callbackFn); diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.h b/flang/lib/Lower/OpenMP/ClauseProcessor.h index 6452e39b97551..fecf3ca4af9dd 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.h +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.h @@ -13,7 +13,7 @@ #define FORTRAN_LOWER_CLAUSEPROCESSOR_H #include "ClauseFinder.h" -#include "Utils.h" +#include "flang/Lower/OpenMP/Utils.h" #include "flang/Lower/AbstractConverter.h" #include "flang/Lower/Bridge.h" #include "flang/Lower/DirectivesCommon.h" @@ -132,7 +132,6 @@ class ClauseProcessor { bool processIsDevicePtr( mlir::omp::IsDevicePtrClauseOps &result, llvm::SmallVectorImpl &isDeviceSyms) const; - bool processLinear(mlir::omp::LinearClauseOps &result) const; bool processLink(llvm::SmallVectorImpl &result) const; @@ -198,7 +197,8 @@ class ClauseProcessor { std::map &parentMemberIndices, llvm::SmallVectorImpl &mapVars, llvm::SmallVectorImpl &mapSyms, - llvm::StringRef mapperIdNameRef = "") const; + llvm::StringRef mapperIdNameRef = "", + bool isMotionModifier = false) const; lower::AbstractConverter &converter; semantics::SemanticsContext &semaCtx; diff --git a/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp b/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp index 146a252b049ec..b0dec20ca3a1f 100644 --- a/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp +++ b/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp @@ -12,8 +12,8 @@ #include "DataSharingProcessor.h" -#include "Utils.h" #include "flang/Lower/ConvertVariable.h" +#include "flang/Lower/OpenMP/Utils.h" #include "flang/Lower/PFTBuilder.h" #include "flang/Lower/Support/PrivateReductionUtils.h" #include "flang/Lower/Support/Utils.h" @@ -89,20 +89,25 @@ DataSharingProcessor::DataSharingProcessor(lower::AbstractConverter &converter, useDelayedPrivatization, symTable, isTargetPrivatization) {} -void DataSharingProcessor::processStep1( - mlir::omp::PrivateClauseOps *clauseOps, - std::optional dir) { +void DataSharingProcessor::processStep1() { collectSymbolsForPrivatization(); collectDefaultSymbols(); collectImplicitSymbols(); collectPreDeterminedSymbols(); +} - privatize(clauseOps, dir); +void DataSharingProcessor::processStep2( + mlir::omp::PrivateClauseOps *clauseOps, + std::optional dir) { + if (privatizationDone) + return; + privatize(clauseOps, dir); insertBarrier(clauseOps); + privatizationDone = true; } -void DataSharingProcessor::processStep2(mlir::Operation *op, bool isLoop) { +void DataSharingProcessor::processStep3(mlir::Operation *op, bool isLoop) { // 'sections' lastprivate is handled by genOMP() if (mlir::isa(op)) return; @@ -295,7 +300,7 @@ bool DataSharingProcessor::needBarrier() { // Emit implicit barrier to synchronize threads and avoid data races on // initialization of firstprivate variables and post-update of lastprivate // variables. - // Emit implicit barrier for linear clause in the OpenMPIRBuilder. + // Emit implicit barrier for linear clause. Maybe on somewhere else. for (const semantics::Symbol *sym : allPrivatizedSymbols) { if (sym->test(semantics::Symbol::Flag::OmpLastPrivate) && (sym->test(semantics::Symbol::Flag::OmpFirstPrivate) || diff --git a/flang/lib/Lower/OpenMP/DataSharingProcessor.h b/flang/lib/Lower/OpenMP/DataSharingProcessor.h index f6aa8652e3534..92ef0d1e8cc20 100644 --- a/flang/lib/Lower/OpenMP/DataSharingProcessor.h +++ b/flang/lib/Lower/OpenMP/DataSharingProcessor.h @@ -111,6 +111,7 @@ class DataSharingProcessor { lower::SymMap &symTable; bool isTargetPrivatization; OMPConstructSymbolVisitor visitor; + bool privatizationDone = false; bool needBarrier(); void collectSymbols(semantics::Symbol::Flag flag, @@ -157,20 +158,34 @@ class DataSharingProcessor { bool useDelayedPrivatization, lower::SymMap &symTable, bool isTargetPrivatization = false); - // Privatisation is split into two steps. - // Step1 performs cloning of all privatisation clauses and copying for - // firstprivates. Step1 is performed at the place where process/processStep1 + // Privatisation is split into 3 steps: + // + // * Step1: collects all symbols that should be privatized. + // + // * Step2: performs cloning of all privatisation clauses and copying for + // firstprivates. Step2 is performed at the place where process/processStep2 // is called. This is usually inside the Operation corresponding to the OpenMP - // construct, for looping constructs this is just before the Operation. The - // split into two steps was performed basically to be able to call - // privatisation for looping constructs before the operation is created since - // the bounds of the MLIR OpenMP operation can be privatised. - // Step2 performs the copying for lastprivates and requires knowledge of the - // MLIR operation to insert the last private update. Step2 adds + // construct, for looping constructs this is just before the Operation. + // + // * Step3: performs the copying for lastprivates and requires knowledge of + // the MLIR operation to insert the last private update. Step3 adds // dealocation code as well. - void processStep1(mlir::omp::PrivateClauseOps *clauseOps = nullptr, + // + // The split was performed for the following reasons: + // + // 1. Step1 was split so that the `target` op knows which symbols should not + // be mapped into the target region due to being `private`. The implicit + // mapping happens before the op body is generated so we need to to collect + // the private symbols first and then later in the body actually privatize + // them. + // + // 2. Step2 was split in order to call privatisation for looping constructs + // before the operation is created since the bounds of the MLIR OpenMP + // operation can be privatised. + void processStep1(); + void processStep2(mlir::omp::PrivateClauseOps *clauseOps = nullptr, std::optional dir = std::nullopt); - void processStep2(mlir::Operation *op, bool isLoop); + void processStep3(mlir::Operation *op, bool isLoop); void pushLoopIV(mlir::Value iv) { loopIVs.push_back(iv); } diff --git a/flang/lib/Lower/OpenMP/Decomposer.cpp b/flang/lib/Lower/OpenMP/Decomposer.cpp index 9bfbf67bec88c..5297fdda3b021 100644 --- a/flang/lib/Lower/OpenMP/Decomposer.cpp +++ b/flang/lib/Lower/OpenMP/Decomposer.cpp @@ -12,7 +12,7 @@ #include "Decomposer.h" -#include "Utils.h" +#include "flang/Lower/OpenMP/Utils.h" #include "flang/Lower/OpenMP/Clauses.h" #include "flang/Lower/PFTBuilder.h" #include "flang/Semantics/semantics.h" diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index 71067283d13f7..f60e55d3b4a8e 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -16,13 +16,13 @@ #include "ClauseProcessor.h" #include "DataSharingProcessor.h" #include "Decomposer.h" -#include "Utils.h" #include "flang/Common/idioms.h" #include "flang/Lower/Bridge.h" #include "flang/Lower/ConvertExpr.h" #include "flang/Lower/ConvertVariable.h" #include "flang/Lower/DirectivesCommon.h" #include "flang/Lower/OpenMP/Clauses.h" +#include "flang/Lower/OpenMP/Utils.h" #include "flang/Lower/StatementContext.h" #include "flang/Lower/SymbolMap.h" #include "flang/Optimizer/Builder/BoxValue.h" @@ -979,10 +979,13 @@ getImplicitMapTypeAndKind(fir::FirOpBuilder &firOpBuilder, auto declareTargetOp = llvm::dyn_cast_if_present(op); if (declareTargetOp && declareTargetOp.isDeclareTarget()) { - if (declareTargetOp.getDeclareTargetCaptureClause() == - mlir::omp::DeclareTargetCaptureClause::link && - declareTargetOp.getDeclareTargetDeviceType() != - mlir::omp::DeclareTargetDeviceType::nohost) { + // OpenMP 6.0, Section 7.9.3, Line Numbers: 12-14 + // If a variable appears in an enter or link clause on a declare target + // directive that does not have a device_type clause with the nohost + // device-type-description then it is treated as if it had appeared in + // a map clause with a map-type of tofrom + if (declareTargetOp.getDeclareTargetDeviceType() != + mlir::omp::DeclareTargetDeviceType::nohost) { mapFlag |= mlir::omp::ClauseMapFlags::to; mapFlag |= mlir::omp::ClauseMapFlags::from; } @@ -1213,6 +1216,7 @@ static void createBodyOfOp(mlir::Operation &op, const OpWithBodyGenInfo &info, Fortran::lower::omp::isLastItemInQueue(item, queue), /*useDelayedPrivatization=*/false, info.symTable); tempDsp->processStep1(); + tempDsp->processStep2(); } if (info.dir == llvm::omp::Directive::OMPD_parallel) { @@ -1302,14 +1306,14 @@ static void createBodyOfOp(mlir::Operation &op, const OpWithBodyGenInfo &info, if (!info.dsp) { assert(tempDsp.has_value()); - tempDsp->processStep2(privatizationBottomLevelOp, isLoop); + tempDsp->processStep3(privatizationBottomLevelOp, isLoop); } else { if (isLoop && regionArgs.size() > 0) { for (const auto ®ionArg : regionArgs) { info.dsp->pushLoopIV(info.converter.getSymbolAddress(*regionArg)); } } - info.dsp->processStep2(privatizationBottomLevelOp, isLoop); + info.dsp->processStep3(privatizationBottomLevelOp, isLoop); } } } @@ -1401,9 +1405,11 @@ static void genBodyOfTargetOp( ConstructQueue::const_iterator item, DataSharingProcessor &dsp) { fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); auto argIface = llvm::cast(*targetOp); + genEntryBlock(firOpBuilder, args, targetOp.getRegion()); + + if (!enableDelayedPrivatizationStaging) + dsp.processStep2(); - mlir::Region ®ion = targetOp.getRegion(); - genEntryBlock(firOpBuilder, args, region); bindEntryBlockArgs(converter, targetOp, args); if (HostEvalInfo *hostEvalInfo = getHostEvalInfoStackTop(converter)) hostEvalInfo->bindOperands(argIface.getHostEvalBlockArgs()); @@ -1452,7 +1458,7 @@ static void genBodyOfTargetOp( genNestedEvaluations(converter, eval); } - dsp.processStep2(targetOp, /*isLoop=*/false); + dsp.processStep3(targetOp, /*isLoop=*/false); } template @@ -1649,7 +1655,6 @@ static void genSingleClauses(lower::AbstractConverter &converter, cp.processAllocate(clauseOps); cp.processCopyprivate(loc, clauseOps); cp.processNowait(clauseOps); - // TODO Support delayed privatization. } static void genTargetClauses( @@ -1682,10 +1687,13 @@ static void genTargetClauses( cp.processTODO( loc, llvm::omp::Directive::OMPD_target); + // TODO: Re-enable check after removing downstream early privatization support + // for `target`. + // `target private(..)` is only supported in delayed privatization mode. - if (!enableDelayedPrivatizationStaging) - cp.processTODO( - loc, llvm::omp::Directive::OMPD_target); + // if (!enableDelayedPrivatizationStaging) + // cp.processTODO( + // loc, llvm::omp::Directive::OMPD_target); } static void genTargetDataClauses( @@ -1955,7 +1963,8 @@ genLoopOp(lower::AbstractConverter &converter, lower::SymMap &symTable, DataSharingProcessor dsp(converter, semaCtx, item->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/true, /*useDelayedPrivatization=*/true, symTable); - dsp.processStep1(&loopClauseOps); + dsp.processStep1(); + dsp.processStep2(&loopClauseOps); mlir::omp::LoopNestOperands loopNestClauseOps; llvm::SmallVector iv; @@ -2353,6 +2362,8 @@ genSectionsOp(lower::AbstractConverter &converter, lower::SymMap &symTable, lower::omp::isLastItemInQueue(item, queue), /*useDelayedPrivatization=*/false, symTable); dsp.processStep1(); + // TODO: Add support for delayed privatization. + dsp.processStep2(); List nonDsaClauses; List lastprivates; @@ -2402,8 +2413,8 @@ genSectionsOp(lower::AbstractConverter &converter, lower::SymMap &symTable, } ConstructQueue sectionQueue{buildConstructQueue( - converter.getFirOpBuilder().getModule(), semaCtx, nestedEval, - sectionConstruct->source, llvm::omp::Directive::OMPD_section, {})}; + builder.getModule(), semaCtx, nestedEval, sectionConstruct->source, + llvm::omp::Directive::OMPD_section, {})}; builder.setInsertionPoint(terminator); genOpWithBody( @@ -2446,7 +2457,7 @@ genSectionsOp(lower::AbstractConverter &converter, lower::SymMap &symTable, // Perform DataSharingProcessor's step2 out of SECTIONS builder.setInsertionPointAfter(sectionsOp.getOperation()); - dsp.processStep2(sectionsOp, false); + dsp.processStep3(sectionsOp, false); // Emit implicit barrier to synchronize threads and avoid data // races on post-update of lastprivate variables when `nowait` // clause is present. @@ -2536,7 +2547,8 @@ genTargetOp(lower::AbstractConverter &converter, lower::SymMap &symTable, lower::omp::isLastItemInQueue(item, queue), /*useDelayedPrivatization=*/true, symTable, /*isTargetPrivitization=*/true); - dsp.processStep1(&clauseOps); + dsp.processStep1(); + dsp.processStep2(&clauseOps); // 5.8.1 Implicit Data-Mapping Attribute Rules // The following code follows the implicit data-mapping rules to map all the @@ -2557,11 +2569,10 @@ genTargetOp(lower::AbstractConverter &converter, lower::SymMap &symTable, if (llvm::is_contained(mapSyms, common)) return; - // If we come across a symbol without a symbol address, we - // return as we cannot process it, this is intended as a - // catch all early exit for symbols that do not have a - // corresponding extended value. Such as subroutines, - // interfaces and named blocks. + // If we come across a symbol without a symbol address, we return as we + // cannot process it, this is intended as a catch all early exit for + // symbols that do not have a corresponding extended value. Such as + // subroutines, interfaces and named blocks. if (!converter.getSymbolAddress(sym)) return; @@ -2725,7 +2736,8 @@ genTaskOp(lower::AbstractConverter &converter, lower::SymMap &symTable, DataSharingProcessor dsp(converter, semaCtx, item->clauses, eval, lower::omp::isLastItemInQueue(item, queue), /*useDelayedPrivatization=*/true, symTable); - dsp.processStep1(&clauseOps); + dsp.processStep1(); + dsp.processStep2(&clauseOps); EntryBlockArgs taskArgs; taskArgs.priv.syms = dsp.getDelayedPrivSymbols(); @@ -2854,8 +2866,9 @@ static mlir::omp::DistributeOp genStandaloneDistribute( DataSharingProcessor dsp(converter, semaCtx, item->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/true, - enableDelayedPrivatization, symTable); - dsp.processStep1(&distributeClauseOps); + enableDelayedPrivatizationStaging, symTable); + dsp.processStep1(); + dsp.processStep2(&distributeClauseOps); mlir::omp::LoopNestOperands loopNestClauseOps; llvm::SmallVector iv; @@ -2887,7 +2900,8 @@ static mlir::omp::WsloopOp genStandaloneDo( DataSharingProcessor dsp(converter, semaCtx, item->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/true, enableDelayedPrivatization, symTable); - dsp.processStep1(&wsloopClauseOps); + dsp.processStep1(); + dsp.processStep2(&wsloopClauseOps); mlir::omp::LoopNestOperands loopNestClauseOps; llvm::SmallVector iv; @@ -2924,7 +2938,8 @@ static mlir::omp::ParallelOp genStandaloneParallel( dsp.emplace(converter, semaCtx, item->clauses, eval, lower::omp::isLastItemInQueue(item, queue), /*useDelayedPrivatization=*/true, symTable); - dsp->processStep1(¶llelClauseOps); + dsp->processStep1(); + dsp->processStep2(¶llelClauseOps); } EntryBlockArgs parallelArgs; @@ -2935,7 +2950,8 @@ static mlir::omp::ParallelOp genStandaloneParallel( parallelArgs.reduction.vars = parallelClauseOps.reductionVars; return genParallelOp(converter, symTable, semaCtx, eval, loc, queue, item, parallelClauseOps, parallelArgs, - enableDelayedPrivatization ? &dsp.value() : nullptr); + enableDelayedPrivatization ? &dsp.value() : nullptr, + /*isComposite=*/false); } static mlir::omp::SimdOp @@ -2952,7 +2968,8 @@ genStandaloneSimd(lower::AbstractConverter &converter, lower::SymMap &symTable, DataSharingProcessor dsp(converter, semaCtx, item->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/true, enableDelayedPrivatization, symTable); - dsp.processStep1(&simdClauseOps); + dsp.processStep1(); + dsp.processStep2(&simdClauseOps); mlir::omp::LoopNestOperands loopNestClauseOps; llvm::SmallVector iv; @@ -2984,7 +3001,8 @@ static mlir::omp::TaskloopOp genStandaloneTaskloop( DataSharingProcessor dsp(converter, semaCtx, item->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/true, enableDelayedPrivatization, symTable); - dsp.processStep1(&taskloopClauseOps); + dsp.processStep1(); + dsp.processStep2(&taskloopClauseOps); mlir::omp::LoopNestOperands loopNestClauseOps; llvm::SmallVector iv; @@ -3027,7 +3045,8 @@ static mlir::omp::DistributeOp genCompositeDistributeParallelDo( DataSharingProcessor dsp(converter, semaCtx, doItem->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/true, /*useDelayedPrivatization=*/true, symTable); - dsp.processStep1(¶llelClauseOps); + dsp.processStep1(); + dsp.processStep2(¶llelClauseOps); EntryBlockArgs parallelArgs; parallelArgs.priv.syms = dsp.getDelayedPrivSymbols(); @@ -3095,7 +3114,8 @@ static mlir::omp::DistributeOp genCompositeDistributeParallelDoSimd( converter, semaCtx, parallelItem->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/false, /*useDelayedPrivatization=*/true, symTable); - parallelItemDSP.processStep1(¶llelClauseOps); + parallelItemDSP.processStep1(); + parallelItemDSP.processStep2(¶llelClauseOps); EntryBlockArgs parallelArgs; parallelArgs.priv.syms = parallelItemDSP.getDelayedPrivSymbols(); @@ -3124,7 +3144,8 @@ static mlir::omp::DistributeOp genCompositeDistributeParallelDoSimd( DataSharingProcessor simdItemDSP(converter, semaCtx, simdItem->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/true, /*useDelayedPrivatization=*/true, symTable); - simdItemDSP.processStep1(&simdClauseOps); + simdItemDSP.processStep1(); + simdItemDSP.processStep2(&simdClauseOps); mlir::omp::LoopNestOperands loopNestClauseOps; llvm::SmallVector iv; @@ -3184,16 +3205,19 @@ static mlir::omp::DistributeOp genCompositeDistributeSimd( genSimdClauses(converter, semaCtx, simdItem->clauses, loc, simdClauseOps, simdReductionSyms); + DataSharingProcessor distributeItemDSP( converter, semaCtx, distributeItem->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/false, /*useDelayedPrivatization=*/true, symTable); - distributeItemDSP.processStep1(&distributeClauseOps); + distributeItemDSP.processStep1(); + distributeItemDSP.processStep2(&distributeClauseOps); DataSharingProcessor simdItemDSP(converter, semaCtx, simdItem->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/true, /*useDelayedPrivatization=*/true, symTable); - simdItemDSP.processStep1(&simdClauseOps); + simdItemDSP.processStep1(); + simdItemDSP.processStep2(&simdClauseOps); // Pass the innermost leaf construct's clauses because that's where COLLAPSE // is placed by construct decomposition. @@ -3250,12 +3274,14 @@ static mlir::omp::WsloopOp genCompositeDoSimd( converter, semaCtx, doItem->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/false, /*useDelayedPrivatization=*/true, symTable); - wsloopItemDSP.processStep1(&wsloopClauseOps); + wsloopItemDSP.processStep1(); + wsloopItemDSP.processStep2(&wsloopClauseOps); DataSharingProcessor simdItemDSP(converter, semaCtx, simdItem->clauses, eval, /*shouldCollectPreDeterminedSymbols=*/true, /*useDelayedPrivatization=*/true, symTable); - simdItemDSP.processStep1(&simdClauseOps, simdItem->id); + simdItemDSP.processStep1(); + simdItemDSP.processStep2(&simdClauseOps, simdItem->id); // Pass the innermost leaf construct's clauses because that's where COLLAPSE // is placed by construct decomposition. diff --git a/flang/lib/Lower/OpenMP/Utils.cpp b/flang/lib/Lower/OpenMP/Utils.cpp index 6487f599df72a..de13363b108d2 100644 --- a/flang/lib/Lower/OpenMP/Utils.cpp +++ b/flang/lib/Lower/OpenMP/Utils.cpp @@ -10,11 +10,12 @@ // //===----------------------------------------------------------------------===// -#include "Utils.h" +#include #include "ClauseFinder.h" #include "flang/Evaluate/fold.h" #include +#include #include #include #include @@ -29,6 +30,8 @@ #include #include #include +#include +#include #include @@ -554,13 +557,11 @@ void insertChildMapInfoIntoParent( mapOp.setMembersIndexAttr(firOpBuilder.create2DI64ArrayAttr( indices.second.memberPlacementIndices)); } else { - // NOTE: We take the map type of the first child, this may not - // be the correct thing to do, however, we shall see. For the moment - // it allows this to work with enter and exit without causing MLIR - // verification issues. The more appropriate thing may be to take - // the "main" map type clause from the directive being used. - mlir::omp::ClauseMapFlags mapType = - indices.second.memberMap[0].getMapType(); + // NOTE: We do not assign default mapped parents a map type, as + // selecting a childs can result in the incorrect map type being + // applied to the parent and data being incorrectly moved to or + // from device. + mlir::omp::ClauseMapFlags mapType = mlir::omp::ClauseMapFlags::storage; llvm::SmallVector members; members.reserve(indices.second.memberMap.size()); diff --git a/flang/lib/Lower/Support/PrivateReductionUtils.cpp b/flang/lib/Lower/Support/PrivateReductionUtils.cpp index c6c428860bca1..e636a50699351 100644 --- a/flang/lib/Lower/Support/PrivateReductionUtils.cpp +++ b/flang/lib/Lower/Support/PrivateReductionUtils.cpp @@ -518,7 +518,7 @@ void PopulateInitAndCleanupRegionsHelper::initAndCleanupBoxedArray( return; } - // Allocating on the heap in case the whole reduction/privatization is nested + // TODO: Allocate on the heap if the whole reduction/privatization is nested // inside of a loop auto temp = [&]() { if (shouldAllocateTempOnStack()) diff --git a/flang/lib/Lower/Support/Utils.cpp b/flang/lib/Lower/Support/Utils.cpp index 1b4d37e9798a9..cb3090df25680 100644 --- a/flang/lib/Lower/Support/Utils.cpp +++ b/flang/lib/Lower/Support/Utils.cpp @@ -12,10 +12,12 @@ #include "flang/Lower/Support/Utils.h" +#include "flang/Common/idioms.h" #include "flang/Common/indirection.h" #include "flang/Lower/AbstractConverter.h" #include "flang/Lower/ConvertVariable.h" #include "flang/Lower/IterationSpace.h" +#include "flang/Lower/OpenMP/Utils.h" #include "flang/Lower/Support/PrivateReductionUtils.h" #include "flang/Optimizer/Builder/HLFIRTools.h" #include "flang/Optimizer/Builder/Todo.h" diff --git a/flang/lib/Optimizer/Builder/FIRBuilder.cpp b/flang/lib/Optimizer/Builder/FIRBuilder.cpp index 5da27d1713825..fb71d17418777 100644 --- a/flang/lib/Optimizer/Builder/FIRBuilder.cpp +++ b/flang/lib/Optimizer/Builder/FIRBuilder.cpp @@ -1914,7 +1914,7 @@ llvm::SmallVector fir::factory::updateRuntimeExtentsForEmptyArrays( mlir::Type i1Type = builder.getI1Type(); mlir::Value isEmpty = createZeroValue(builder, loc, i1Type); - llvm::SmallVector zeroes; + llvm::SmallVector zeroes; for (mlir::Value extent : extents) { mlir::Type type = extent.getType(); mlir::Value zero = createZeroValue(builder, loc, type); diff --git a/flang/lib/Optimizer/Builder/Runtime/Main.cpp b/flang/lib/Optimizer/Builder/Runtime/Main.cpp index 9ce5e172f3cd3..13a215a211afa 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Main.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Main.cpp @@ -25,6 +25,7 @@ using namespace Fortran::runtime; void fir::runtime::genMain( fir::FirOpBuilder &builder, mlir::Location loc, const std::vector &defs, bool initCuda, + bool enableAmdAllocator, bool initCoarrayEnv) { auto *context = builder.getContext(); auto argcTy = builder.getDefaultIntegerType(); @@ -35,6 +36,7 @@ void fir::runtime::genMain( auto startFn = builder.createFunction( loc, RTNAME_STRING(ProgramStart), mlir::FunctionType::get(context, {argcTy, ptrTy, ptrTy, ptrTy}, {})); + // void ProgramStop() auto stopFn = builder.createFunction(loc, RTNAME_STRING(ProgramEndStatement), @@ -73,6 +75,13 @@ void fir::runtime::genMain( if (initCoarrayEnv) mif::InitOp::create(builder, loc); + if (enableAmdAllocator) { + // void AMDRegisterAllocator() + auto registerFn = + builder.createFunction(loc, RTNAME_STRING(AMDRegisterAllocator), + mlir::FunctionType::get(context, {}, {})); + builder.create(loc, registerFn); + } fir::CallOp::create(builder, loc, qqMainFn); fir::CallOp::create(builder, loc, stopFn); diff --git a/flang/lib/Optimizer/OpenMP/CMakeLists.txt b/flang/lib/Optimizer/OpenMP/CMakeLists.txt index 23a7dc8f08399..304333fa8830e 100644 --- a/flang/lib/Optimizer/OpenMP/CMakeLists.txt +++ b/flang/lib/Optimizer/OpenMP/CMakeLists.txt @@ -5,6 +5,7 @@ add_flang_library(FlangOpenMPTransforms DoConcurrentConversion.cpp FunctionFiltering.cpp GenericLoopConversion.cpp + GlobalFiltering.cpp MapsForPrivatizedSymbols.cpp MapInfoFinalization.cpp MarkDeclareTarget.cpp @@ -34,6 +35,7 @@ add_flang_library(FlangOpenMPTransforms MLIR_LIBS MLIRFuncDialect + MLIRMathTransforms MLIROpenMPDialect MLIRIR MLIRPass diff --git a/flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp b/flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp index 3031bb5da6919..40f539c56e775 100644 --- a/flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp +++ b/flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp @@ -13,13 +13,16 @@ #include "flang/Optimizer/Dialect/FIRDialect.h" #include "flang/Optimizer/Dialect/FIROpsSupport.h" +#include "flang/Optimizer/HLFIR/HLFIROps.h" #include "flang/Optimizer/OpenMP/Passes.h" #include "mlir/Dialect/Func/IR/FuncOps.h" #include "mlir/Dialect/OpenMP/OpenMPDialect.h" #include "mlir/Dialect/OpenMP/OpenMPInterfaces.h" #include "mlir/IR/BuiltinOps.h" +#include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/TypeSwitch.h" namespace flangomp { #define GEN_PASS_DEF_FUNCTIONFILTERINGPASS @@ -28,6 +31,104 @@ namespace flangomp { using namespace mlir; +/// Add an operation to one of the output sets to be later rewritten, based on +/// whether it is located within the given region. +template +static void collectRewriteImpl(OpTy op, Region ®ion, + llvm::SetVector &rewrites, + llvm::SetVector *parentRewrites) { + if (rewrites.contains(op)) + return; + + if (!parentRewrites || region.isAncestor(op->getParentRegion())) + rewrites.insert(op); + else + parentRewrites->insert(op.getOperation()); +} + +template +static void collectRewrite(OpTy op, Region ®ion, + llvm::SetVector &rewrites, + llvm::SetVector *parentRewrites) { + collectRewriteImpl(op, region, rewrites, parentRewrites); +} + +/// Add an \c omp.map.info operation and all its members recursively to one of +/// the output sets to be later rewritten, based on whether they are located +/// within the given region. +/// +/// Dependencies across \c omp.map.info are maintained by ensuring dependencies +/// are added to the output sets before operations based on them. +template <> +void collectRewrite(omp::MapInfoOp mapOp, Region ®ion, + llvm::SetVector &rewrites, + llvm::SetVector *parentRewrites) { + for (Value member : mapOp.getMembers()) + collectRewrite(cast(member.getDefiningOp()), region, + rewrites, parentRewrites); + + collectRewriteImpl(mapOp, region, rewrites, parentRewrites); +} + +/// Add the given value to a sorted set if it should be replaced by a +/// placeholder when used as an operand that must remain for the device. The +/// used output set used will depend on whether the value is defined within the +/// given region. +/// +/// Values that are block arguments of \c omp.target_data and \c func.func +/// operations are skipped, since they will still be available after all +/// rewrites are completed. +static void collectRewrite(Value value, Region ®ion, + llvm::SetVector &rewrites, + llvm::SetVector *parentRewrites) { + if ((isa(value) && + isa( + cast(value).getOwner()->getParentOp())) || + rewrites.contains(value)) + return; + + if (!parentRewrites) { + rewrites.insert(value); + return; + } + + Region *definingRegion; + if (auto blockArg = dyn_cast(value)) + definingRegion = blockArg.getOwner()->getParent(); + else + definingRegion = value.getDefiningOp()->getParentRegion(); + + assert(definingRegion && "defining op/block must exist in a region"); + + if (region.isAncestor(definingRegion)) + rewrites.insert(value); + else + parentRewrites->insert(value); +} + +/// Add operations in \c childRewrites to one of the output sets based on +/// whether they are located within the given region. +template +static void +applyChildRewrites(Region ®ion, + const llvm::SetVector &childRewrites, + llvm::SetVector &rewrites, + llvm::SetVector *parentRewrites) { + for (Operation *rewrite : childRewrites) + if (auto op = dyn_cast(*rewrite)) + collectRewrite(op, region, rewrites, parentRewrites); +} + +/// Add values in \c childRewrites to one of the output sets based on +/// whether they are defined within the given region. +static void applyChildRewrites(Region ®ion, + const llvm::SetVector &childRewrites, + llvm::SetVector &rewrites, + llvm::SetVector *parentRewrites) { + for (Value value : childRewrites) + collectRewrite(value, region, rewrites, parentRewrites); +} + namespace { class FunctionFilteringPass : public flangomp::impl::FunctionFilteringPassBase { @@ -94,6 +195,12 @@ class FunctionFilteringPass funcOp.erase(); return WalkResult::skip(); } + + if (failed(rewriteHostRegion(funcOp.getRegion()))) { + funcOp.emitOpError() << "could not be rewritten for target device"; + return WalkResult::interrupt(); + } + if (declareTargetOp) declareTargetOp.setDeclareTarget( declareType, omp::DeclareTargetCaptureClause::to, @@ -102,5 +209,365 @@ class FunctionFilteringPass return WalkResult::advance(); }); } + +private: + /// Rewrite the given host device region belonging to a function that contains + /// \c omp.target operations, to remove host-only operations that are not used + /// by device codegen. + /// + /// It is based on the expected form of the MLIR module as produced by Flang + /// lowering and it performs the following mutations: + /// - Replace all values returned by the function with \c fir.undefined. + /// - Operations taking map-like clauses (e.g. \c omp.target, + /// \c omp.target_data, etc) are moved to the end of the function. If they + /// are nested inside of any other operations, they are hoisted out of + /// them. If the region belongs to \c omp.target_data, these operations + /// are hoisted to its top level, rather than to the parent function. + /// - \c device, \c if and \c depend clauses are removed from these target + /// functions. Values initializing other clauses are either replaced by + /// placeholders as follows: + /// - Values defined by block arguments are replaced by placeholders only + /// if they are not attached to \c func.func or \c omp.target_data + /// operations. In that case, they are kept unmodified. + /// - \c arith.constant and \c fir.address_of are maintained. + /// - Other values are replaced by a combination of an \c fir.alloca for a + /// single bit and an \c fir.convert to the original type of the value. + /// This can be done because the code eventually generated for these + /// operations will be discarded, as they aren't runnable by the target + /// device. + /// - \c omp.map.info operations associated to these target regions are + /// preserved. These are moved above all \c omp.target and sorted to + /// satisfy dependencies among them. + /// - \c bounds arguments are removed from \c omp.map.info operations. + /// - \c var_ptr and \c var_ptr_ptr arguments of \c omp.map.info are + /// handled as follows: + /// - \c var_ptr_ptr is expected to be defined by a \c fir.box_offset + /// operation which is preserved. Otherwise, the pass will fail. + /// - \c var_ptr can be defined by an \c hlfir.declare which is also + /// preserved. Its \c memref argument is replaced by a placeholder or + /// maintained similarly to non-map clauses of target operations + /// described above. If it has \c shape or \c typeparams arguments, they + /// are replaced by applicable constants. \c dummy_scope arguments + /// are discarded. + /// - Every other operation not located inside of an \c omp.target is + /// removed. + /// - Whenever a value or operation that would otherwise be replaced with a + /// placeholder is defined outside of the region being rewritten, it is + /// added to the \c parentOpRewrites or \c parentValRewrites output + /// argument, to be later handled by the caller. This is only intended to + /// properly support nested \c omp.target_data and \c omp.target placed + /// inside of \c omp.target_data. When called for the main function, these + /// output arguments must not be set. + LogicalResult + rewriteHostRegion(Region ®ion, + llvm::SetVector *parentOpRewrites = nullptr, + llvm::SetVector *parentValRewrites = nullptr) { + // Extract parent op information. + auto [funcOp, targetDataOp] = [®ion]() { + Operation *parent = region.getParentOp(); + return std::make_tuple(dyn_cast(parent), + dyn_cast(parent)); + }(); + assert((bool)funcOp != (bool)targetDataOp && + "region must be defined by either func.func or omp.target_data"); + assert((bool)parentOpRewrites == (bool)targetDataOp && + (bool)parentValRewrites == (bool)targetDataOp && + "parent rewrites must be passed iff rewriting omp.target_data"); + + // Collect operations that have mapping information associated to them. + llvm::SmallVector< + std::variant> + targetOps; + + // Sets to store pending rewrites marked by child omp.target_data ops. + llvm::SetVector childOpRewrites; + llvm::SetVector childValRewrites; + WalkResult result = region.walk([&](Operation *op) { + // Skip the inside of omp.target regions, since these contain device + // code. + if (auto targetOp = dyn_cast(op)) { + targetOps.push_back(targetOp); + return WalkResult::skip(); + } + + if (auto targetOp = dyn_cast(op)) { + // Recursively rewrite omp.target_data regions as well. + if (failed(rewriteHostRegion(targetOp.getRegion(), &childOpRewrites, + &childValRewrites))) { + targetOp.emitOpError() << "rewrite for target device failed"; + return WalkResult::interrupt(); + } + + targetOps.push_back(targetOp); + return WalkResult::skip(); + } + + if (auto targetOp = dyn_cast(op)) + targetOps.push_back(targetOp); + else if (auto targetOp = dyn_cast(op)) + targetOps.push_back(targetOp); + else if (auto targetOp = dyn_cast(op)) + targetOps.push_back(targetOp); + + return WalkResult::advance(); + }); + + if (result.wasInterrupted()) + return failure(); + + // Make a temporary clone of the parent operation with an empty region, + // and update all references to entry block arguments to those of the new + // region. Users will later either be moved to the new region or deleted + // when the original region is replaced by the new. + OpBuilder builder(&getContext()); + builder.setInsertionPointAfter(region.getParentOp()); + Operation *newOp = builder.cloneWithoutRegions(*region.getParentOp()); + Block &block = newOp->getRegion(0).emplaceBlock(); + + llvm::SmallVector locs; + locs.reserve(region.getNumArguments()); + llvm::transform(region.getArguments(), std::back_inserter(locs), + [](const BlockArgument &arg) { return arg.getLoc(); }); + block.addArguments(region.getArgumentTypes(), locs); + + for (auto [oldArg, newArg] : + llvm::zip_equal(region.getArguments(), block.getArguments())) + oldArg.replaceAllUsesWith(newArg); + + // Collect omp.map.info ops while satisfying interdependencies. This must + // be updated whenever operands to operations contained in targetOps change. + llvm::SetVector rewriteValues; + llvm::SetVector mapInfos; + for (auto targetOp : targetOps) { + std::visit( + [&](auto op) { + // Variables unused by the device, present on all target ops. + op.getDeviceMutable().clear(); + op.getIfExprMutable().clear(); + + for (Value mapVar : op.getMapVars()) + collectRewrite(cast(mapVar.getDefiningOp()), + region, mapInfos, parentOpRewrites); + + if constexpr (!std::is_same_v) { + // Variables unused by the device, present on all target ops + // except for omp.target_data. + op.getDependVarsMutable().clear(); + op.setDependKindsAttr(nullptr); + } + + if constexpr (std::is_same_v) { + assert(op.getHostEvalVars().empty() && + "unexpected host_eval in target device module"); + // TODO: Clear some of these operands rather than rewriting them, + // depending on whether they are needed by device codegen once + // support for them is fully implemented. + for (Value allocVar : op.getAllocateVars()) + collectRewrite(allocVar, region, rewriteValues, + parentValRewrites); + for (Value allocVar : op.getAllocatorVars()) + collectRewrite(allocVar, region, rewriteValues, + parentValRewrites); + for (Value inReduction : op.getInReductionVars()) + collectRewrite(inReduction, region, rewriteValues, + parentValRewrites); + for (Value isDevPtr : op.getIsDevicePtrVars()) + collectRewrite(isDevPtr, region, rewriteValues, + parentValRewrites); + for (Value mapVar : op.getHasDeviceAddrVars()) + collectRewrite(cast(mapVar.getDefiningOp()), + region, mapInfos, parentOpRewrites); + for (Value privateVar : op.getPrivateVars()) + collectRewrite(privateVar, region, rewriteValues, + parentValRewrites); + if (Value threadLimit = op.getThreadLimit()) + collectRewrite(threadLimit, region, rewriteValues, + parentValRewrites); + } else if constexpr (std::is_same_v) { + for (Value mapVar : op.getUseDeviceAddrVars()) + collectRewrite(cast(mapVar.getDefiningOp()), + region, mapInfos, parentOpRewrites); + for (Value mapVar : op.getUseDevicePtrVars()) + collectRewrite(cast(mapVar.getDefiningOp()), + region, mapInfos, parentOpRewrites); + } + }, + targetOp); + } + + applyChildRewrites(region, childOpRewrites, mapInfos, parentOpRewrites); + + // Move omp.map.info ops to the new block and collect dependencies. + llvm::SetVector declareOps; + llvm::SetVector boxOffsets; + for (omp::MapInfoOp mapOp : mapInfos) { + if (auto declareOp = dyn_cast_if_present( + mapOp.getVarPtr().getDefiningOp())) + collectRewrite(declareOp, region, declareOps, parentOpRewrites); + else + collectRewrite(mapOp.getVarPtr(), region, rewriteValues, + parentValRewrites); + + if (Value varPtrPtr = mapOp.getVarPtrPtr()) { + if (auto boxOffset = llvm::dyn_cast_if_present( + varPtrPtr.getDefiningOp())) + collectRewrite(boxOffset, region, boxOffsets, parentOpRewrites); + else + return mapOp->emitOpError() << "var_ptr_ptr rewrite only supported " + "if defined by fir.box_offset"; + } + + // Bounds are not used during target device codegen. + mapOp.getBoundsMutable().clear(); + mapOp->moveBefore(&block, block.end()); + } + + applyChildRewrites(region, childOpRewrites, declareOps, parentOpRewrites); + applyChildRewrites(region, childOpRewrites, boxOffsets, parentOpRewrites); + + // Create a temporary marker to simplify the op moving process below. + builder.setInsertionPointToStart(&block); + auto marker = builder.create(builder.getUnknownLoc(), + builder.getNoneType()); + builder.setInsertionPoint(marker); + + // Handle dependencies of hlfir.declare ops. + for (hlfir::DeclareOp declareOp : declareOps) { + collectRewrite(declareOp.getMemref(), region, rewriteValues, + parentValRewrites); + + if (declareOp.getStorage()) + collectRewrite(declareOp.getStorage(), region, rewriteValues, + parentValRewrites); + + // Shape and typeparams aren't needed for target device codegen, but + // removing them would break verifiers. + Value zero; + if (declareOp.getShape() || !declareOp.getTypeparams().empty()) + zero = builder.create(declareOp.getLoc(), + builder.getI64IntegerAttr(0)); + + if (auto shape = declareOp.getShape()) { + // The pre-cg rewrite pass requires the shape to be defined by one of + // fir.shape, fir.shapeshift or fir.shift, so we need to make sure it's + // still defined by one of these after this pass. + Operation *shapeOp = shape.getDefiningOp(); + llvm::SmallVector extents(shapeOp->getNumOperands(), zero); + Value newShape = + llvm::TypeSwitch(shapeOp) + .Case([&](fir::ShapeOp op) { + return builder.create(op.getLoc(), extents); + }) + .Case([&](fir::ShapeShiftOp op) { + auto type = fir::ShapeShiftType::get(op.getContext(), + extents.size() / 2); + return builder.create(op.getLoc(), type, + extents); + }) + .Case([&](fir::ShiftOp op) { + auto type = + fir::ShiftType::get(op.getContext(), extents.size()); + return builder.create(op.getLoc(), type, + extents); + }) + .Default([](Operation *op) { + op->emitOpError() + << "hlfir.declare shape expected to be one of: " + "fir.shape, fir.shapeshift or fir.shift"; + return nullptr; + }); + + if (!newShape) + return failure(); + + declareOp.getShapeMutable().assign(newShape); + } + + for (OpOperand &typeParam : declareOp.getTypeparamsMutable()) + typeParam.assign(zero); + + declareOp.getDummyScopeMutable().clear(); + } + + // We don't actually need the proper initialization, but rather just + // maintain the basic form of these operands. Generally, we create 1-bit + // placeholder allocas that we "typecast" to the expected type and replace + // all uses. Using fir.undefined here instead is not possible because these + // variables cannot be constants, as that would trigger different codegen + // for target regions. + applyChildRewrites(region, childValRewrites, rewriteValues, + parentValRewrites); + for (Value value : rewriteValues) { + Location loc = value.getLoc(); + Value rewriteValue; + if (isa_and_present( + value.getDefiningOp())) { + // If it's defined by fir.address_of, then we need to keep that op as + // well because it might be pointing to a 'declare target' global. + // Constants can also trigger different codegen paths, so we keep them + // as well. + rewriteValue = builder.clone(*value.getDefiningOp())->getResult(0); + } else if (auto boxCharType = + dyn_cast(value.getType())) { + // !fir.boxchar types cannot be directly obtained by converting a + // !fir.ref, as they aren't reference types. Since they can appear + // representing some `target firstprivate` clauses, we need to create + // a special case here based on creating a placeholder fir.emboxchar op. + MLIRContext *ctx = &getContext(); + fir::KindTy kind = boxCharType.getKind(); + auto placeholder = builder.create( + loc, fir::CharacterType::getSingleton(ctx, kind)); + auto one = builder.create( + loc, builder.getI32Type(), builder.getI32IntegerAttr(1)); + rewriteValue = builder.create(loc, boxCharType, + placeholder, one); + } else { + Value placeholder = + builder.create(loc, builder.getI1Type()); + rewriteValue = + builder.create(loc, value.getType(), placeholder); + } + value.replaceAllUsesWith(rewriteValue); + } + + // Move omp.map.info dependencies. + for (hlfir::DeclareOp declareOp : declareOps) + declareOp->moveBefore(marker); + + // The box_ref argument of fir.box_offset is expected to be the same value + // that was passed as var_ptr to the corresponding omp.map.info, so we + // don't need to handle its defining op here. + for (fir::BoxOffsetOp boxOffset : boxOffsets) + boxOffset->moveBefore(marker); + + marker->erase(); + + // Move target operations to the end of the new block. + for (auto targetOp : targetOps) + std::visit([&block](auto op) { op->moveBefore(&block, block.end()); }, + targetOp); + + // Add terminator to the new block. + builder.setInsertionPointToEnd(&block); + if (funcOp) { + llvm::SmallVector returnValues; + returnValues.reserve(funcOp.getNumResults()); + for (auto type : funcOp.getResultTypes()) + returnValues.push_back( + builder.create(funcOp.getLoc(), type)); + + builder.create(funcOp.getLoc(), returnValues); + } else { + builder.create(targetDataOp.getLoc()); + } + + // Replace old region (now missing ops) with the new one and remove the + // temporary operation clone. + region.takeBody(newOp->getRegion(0)); + newOp->erase(); + return success(); + } }; } // namespace diff --git a/flang/lib/Optimizer/OpenMP/GlobalFiltering.cpp b/flang/lib/Optimizer/OpenMP/GlobalFiltering.cpp new file mode 100644 index 0000000000000..1a38be6476ec0 --- /dev/null +++ b/flang/lib/Optimizer/OpenMP/GlobalFiltering.cpp @@ -0,0 +1,70 @@ +//===- GlobalFiltering.cpp ------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements transforms to filter out functions intended for the host +// when compiling for the device and vice versa. +// +//===----------------------------------------------------------------------===// + +#include "flang/Optimizer/Dialect/FIRDialect.h" +#include "flang/Optimizer/Dialect/FIROpsSupport.h" +#include "flang/Optimizer/OpenMP/Passes.h" + +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/Dialect/OpenMP/OpenMPDialect.h" +#include "mlir/Dialect/OpenMP/OpenMPInterfaces.h" +#include "mlir/IR/BuiltinOps.h" +#include "llvm/ADT/SmallVector.h" + +namespace flangomp { +#define GEN_PASS_DEF_GLOBALFILTERINGPASS +#include "flang/Optimizer/OpenMP/Passes.h.inc" +} // namespace flangomp + +using namespace mlir; + +namespace { +// TODO Remove this pass when AOMP moves to `clang-linker-wrapper` (instead of +// `clang-offload-packager`). +class GlobalFilteringPass + : public flangomp::impl::GlobalFilteringPassBase { +public: + GlobalFilteringPass() = default; + + void runOnOperation() override { + auto op = dyn_cast(getOperation()); + if (!op || !op.getIsTargetDevice()) + return; + + op->walk([&](fir::GlobalOp globalOp) { + bool symbolUnused = true; + SymbolTable::UseRange globalUses = *globalOp.getSymbolUses(op); + for (SymbolTable::SymbolUse use : globalUses) { + if (use.getUser() == globalOp) + continue; + symbolUnused = false; + break; + } + + // Look for declare target information in case this global is intended to + // always exist on the device. + auto declareTargetIface = + llvm::dyn_cast( + globalOp.getOperation()); + bool hostOnlySymbol = !declareTargetIface || + !declareTargetIface.isDeclareTarget() || + declareTargetIface.getDeclareTargetDeviceType() == + omp::DeclareTargetDeviceType::host; + + // Remove unused host symbols with external linkage. + if (symbolUnused && !globalOp.getLinkName() && hostOnlySymbol) + globalOp.erase(); + }); + } +}; +} // namespace diff --git a/flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp b/flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp index bd07d7fe01b85..a6e2c8bae1184 100644 --- a/flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp +++ b/flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp @@ -60,6 +60,13 @@ namespace { class MapInfoFinalizationPass : public flangomp::impl::MapInfoFinalizationPassBase< MapInfoFinalizationPass> { +public: + MapInfoFinalizationPass() = default; + + MapInfoFinalizationPass( + const flangomp::MapInfoFinalizationPassOptions &options) + : MapInfoFinalizationPassBase(options) {} + /// Helper class tracking a members parent and its /// placement in the parents member list struct ParentAndPlacement { @@ -86,8 +93,7 @@ class MapInfoFinalizationPass containsPath(const llvm::SmallVectorImpl> &paths, llvm::ArrayRef path) { return llvm::any_of(paths, [&](const llvm::SmallVector &p) { - return p.size() == path.size() && - std::equal(p.begin(), p.end(), path.begin()); + return p.size() == path.size() && std::equal(p.begin(), p.end(), path.begin()); }); } @@ -148,11 +154,13 @@ class MapInfoFinalizationPass llvm::SmallVectorImpl &newMapOpsForFields, llvm::SmallVectorImpl> &newMemberIndexPaths) { // Local de-dup within this op invocation. - if (containsPath(newMemberIndexPaths, indexPath)) + if (containsPath(newMemberIndexPaths, indexPath)) { return; + } // Global de-dup against already present member indices. - if (mappedIndexPathExists(op, indexPath)) + if (mappedIndexPathExists(op, indexPath)) { return; + } if (op.getMapperId()) { mlir::omp::DeclareMapperOp symbol = @@ -276,6 +284,15 @@ class MapInfoFinalizationPass }); } + // Check if the declaration operation we have refers to a dummy + // function argument. + bool isDummyArgument(mlir::Operation *op) { + if (auto declareOp = mlir::dyn_cast(op)) + if (auto dummyScope = declareOp.getDummyScope()) + return true; + return false; + } + /// When provided a MapInfoOp containing a descriptor type that /// we must expand into multiple maps this function will extract /// the value from it and return it, in certain cases we must @@ -427,16 +444,32 @@ class MapInfoFinalizationPass /// allowing `to` mappings, and `target update` not allowing both `to` and /// `from` simultaneously. We currently try to maintain the `implicit` flag /// where necessary, although it does not seem strictly required. - mlir::omp::ClauseMapFlags - getDescriptorMapType(mlir::omp::ClauseMapFlags mapTypeFlag, - mlir::Operation *target) { + /// + /// Currently, if it is a has_device_addr clause, we opt to not apply the + /// descriptor tag to it as it's used differently to a regular mapping + /// and some of the runtime descriptor behaviour at the moment can cause + /// issues. + mlir::omp::ClauseMapFlags getDescriptorMapType(mlir::omp::ClauseMapFlags mapTypeFlag, + mlir::Operation *target) { using mapFlags = mlir::omp::ClauseMapFlags; if (llvm::isa_and_nonnull(target)) return mapTypeFlag; - mapFlags flags = - mapFlags::to | (mapTypeFlag & (mapFlags::implicit | mapFlags::always)); + mapFlags flags = mapFlags::to | mapFlags::descriptor | + (mapTypeFlag & mapFlags::implicit); + // Descriptors for objects will always be copied. This is because the + // descriptor can be rematerialized by the compiler, and so the addres + // of the descriptor for a given object at one place in the code may + // differ from that address in another place. The contents of the + // descriptor (the base address in particular) will remain unchanged + // though. + // TODO/FIXME: We currently cannot have MAP_CLOSE and MAP_ALWAYS on + // the descriptor at once, these are mutually exclusive and when + // both are applied the runtime will fail to map. + flags |= ((mapTypeFlag & mapFlags::close) == mapFlags::close) + ? mapFlags::close + : mapFlags::always; // For unified_shared_memory, we additionally add `CLOSE` on the descriptor // to ensure device-local placement where required by tests relying on USM + // close semantics. @@ -669,22 +702,11 @@ class MapInfoFinalizationPass } } - // Descriptors for objects listed on the `has_device_addr` will always - // be copied. This is because the descriptor can be rematerialized by the - // compiler, and so the address of the descriptor for a given object at - // one place in the code may differ from that address in another place. - // The contents of the descriptor (the base address in particular) will - // remain unchanged though. - mlir::omp::ClauseMapFlags mapType = op.getMapType(); - if (isHasDeviceAddrFlag) { - mapType |= mlir::omp::ClauseMapFlags::always; - } - mlir::omp::MapInfoOp newDescParentMapOp = mlir::omp::MapInfoOp::create( builder, op->getLoc(), op.getResult().getType(), descriptor, mlir::TypeAttr::get(fir::unwrapRefType(descriptor.getType())), builder.getAttr( - getDescriptorMapType(mapType, target)), + getDescriptorMapType(op.getMapType(), target)), op.getMapCaptureTypeAttr(), /*varPtrPtr=*/mlir::Value{}, newMembers, newMembersAttr, /*bounds=*/mlir::SmallVector{}, /*mapperId*/ mlir::FlatSymbolRefAttr(), op.getNameAttr(), @@ -749,24 +771,23 @@ class MapInfoFinalizationPass if (!mapClauseOwner) return; - auto addOperands = [&](mlir::MutableOperandRange &mutableOpRange, + auto addOperands = [&](mlir::MutableOperandRange &mapVarsArr, mlir::Operation *directiveOp, unsigned blockArgInsertIndex = 0) { - if (!llvm::is_contained(mutableOpRange.getAsOperandRange(), - op.getResult())) + if (!llvm::is_contained(mapVarsArr.getAsOperandRange(), op.getResult())) return; // There doesn't appear to be a simple way to convert MutableOperandRange // to a vector currently, so we instead use a for_each to populate our // vector. llvm::SmallVector newMapOps; - newMapOps.reserve(mutableOpRange.size()); + newMapOps.reserve(mapVarsArr.size()); llvm::for_each( - mutableOpRange.getAsOperandRange(), + mapVarsArr.getAsOperandRange(), [&newMapOps](mlir::Value oper) { newMapOps.push_back(oper); }); for (auto mapMember : op.getMembers()) { - if (llvm::is_contained(mutableOpRange.getAsOperandRange(), mapMember)) + if (llvm::is_contained(mapVarsArr.getAsOperandRange(), mapMember)) continue; newMapOps.push_back(mapMember); if (directiveOp) { @@ -776,7 +797,7 @@ class MapInfoFinalizationPass } } - mutableOpRange.assign(newMapOps); + mapVarsArr.assign(newMapOps); }; auto argIface = @@ -784,13 +805,12 @@ class MapInfoFinalizationPass if (auto mapClauseOwner = llvm::dyn_cast(target)) { - mlir::MutableOperandRange mapMutableOpRange = - mapClauseOwner.getMapVarsMutable(); + mlir::MutableOperandRange mapVarsArr = mapClauseOwner.getMapVarsMutable(); unsigned blockArgInsertIndex = argIface ? argIface.getMapBlockArgsStart() + argIface.numMapBlockArgs() : 0; - addOperands(mapMutableOpRange, + addOperands(mapVarsArr, llvm::dyn_cast_if_present( argIface.getOperation()), blockArgInsertIndex); @@ -887,7 +907,8 @@ class MapInfoFinalizationPass builder, op->getLoc(), op.getResult().getType(), op.getVarPtr(), op.getVarTypeAttr(), builder.getAttr( - mlir::omp::ClauseMapFlags::to | mlir::omp::ClauseMapFlags::always), + mlir::omp::ClauseMapFlags::to | mlir::omp::ClauseMapFlags::always | + mlir::omp::ClauseMapFlags::descriptor), op.getMapCaptureTypeAttr(), /*varPtrPtr=*/mlir::Value{}, mlir::SmallVector{}, mlir::ArrayAttr{}, /*bounds=*/mlir::SmallVector{}, @@ -965,9 +986,7 @@ class MapInfoFinalizationPass // operation (usually function) containing the MapInfoOp because this pass // will mutate siblings of MapInfoOp. void runOnOperation() override { - mlir::ModuleOp module = getOperation(); - if (!module) - module = getOperation()->getParentOfType(); + mlir::ModuleOp module = mlir::cast(getOperation()); fir::KindMapping kindMap = fir::getKindMapping(module); fir::FirOpBuilder builder{module, std::move(kindMap)}; @@ -1021,31 +1040,39 @@ class MapInfoFinalizationPass // Next, walk `omp.map.info` ops to see if any record members should be // implicitly mapped. + // TODO/FIXME/UPDATE: I believe we need to add implicit capture of + // allocatable members of arbitrary depths for this before we can + // switch it on in ATD, as currently it will break some currently + // downstream changes that existing working benchmarks depend on. + // However, hopefully with the addition of: + // https://github.com/llvm/llvm-project/pull/119588 + // and the correct mapping of all allocatable members, we'd + // get the desired behaviour in all cases, if not, need to have a + // think about the current behaviour we have. func->walk([&](mlir::omp::MapInfoOp op) { mlir::Type underlyingType = fir::unwrapRefType(op.getVarPtr().getType()); - // TODO Test with and support more complicated cases; like arrays for - // records, for example. + // Test with and support records (derived types) that have allocatable + // members directly or nested via other records. if (!fir::isRecordWithAllocatableMember(underlyingType)) - return mlir::WalkResult::advance(); + return; - // TODO For now, only consider `omp.target` ops. Other ops that support + // For now, only consider `omp.target` ops. Other ops that support // `map` clauses will follow later. mlir::omp::TargetOp target = mlir::dyn_cast_if_present( getFirstTargetUser(op)); if (!target) - return mlir::WalkResult::advance(); + return; auto mapClauseOwner = llvm::dyn_cast(*target); int64_t mapVarIdx = mapClauseOwner.getOperandIndexForMap(op); assert(mapVarIdx >= 0 && - mapVarIdx < - static_cast(mapClauseOwner.getMapVars().size())); + mapVarIdx < static_cast(mapClauseOwner.getMapVars().size())); auto argIface = llvm::dyn_cast(*target); @@ -1056,10 +1083,7 @@ class MapInfoFinalizationPass mlir::getForwardSlice(opBlockArg, &mapVarForwardSlice); mapVarForwardSlice.remove_if([&](mlir::Operation *sliceOp) { - // TODO Support coordinate_of ops. - // - // TODO Support call ops by recursively examining the forward slice of - // the corresponding parameter to the field in the called function. + // TODO Support coordinate_of ops and calls (by tracking parameters). return !mlir::isa(sliceOp); }); @@ -1096,7 +1120,7 @@ class MapInfoFinalizationPass field, newMapOpsForFields, newMemberIndexPaths); } - // Handle nested allocatable fields along any component chain + // 2) Handle nested allocatable fields along any component chain // referenced in the region via HLFIR designates. llvm::SmallVector> seenIndexPaths; for (mlir::Operation *sliceOp : mapVarForwardSlice) { @@ -1172,21 +1196,21 @@ class MapInfoFinalizationPass } if (newMapOpsForFields.empty()) - return mlir::WalkResult::advance(); + return; // Deduplicate by index path to avoid emitting duplicate members for // the same component. Use a set-based key to keep this near O(n). llvm::SmallVector dedupMapOps; llvm::SmallVector> dedupIndexPaths; llvm::StringSet<> seenKeys; - for (auto [i, mapOp] : llvm::enumerate(newMapOpsForFields)) { + for (auto [i, mapOpV] : llvm::enumerate(newMapOpsForFields)) { const auto &path = newMemberIndexPaths[i]; llvm::SmallString<64> key; buildPathKey(path, key); if (seenKeys.contains(key)) continue; seenKeys.insert(key); - dedupMapOps.push_back(mapOp); + dedupMapOps.push_back(mapOpV); dedupIndexPaths.emplace_back(path.begin(), path.end()); } op.getMembersMutable().append(dedupMapOps); @@ -1194,10 +1218,8 @@ class MapInfoFinalizationPass if (mlir::ArrayAttr oldAttr = op.getMembersIndexAttr()) for (mlir::Attribute indexList : oldAttr) { llvm::SmallVector listVec; - for (mlir::Attribute index : mlir::cast(indexList)) listVec.push_back(mlir::cast(index).getInt()); - newMemberIndices.emplace_back(std::move(listVec)); } for (auto &path : dedupIndexPaths) @@ -1205,8 +1227,6 @@ class MapInfoFinalizationPass op.setMembersIndexAttr(builder.create2DI64ArrayAttr(newMemberIndices)); op.setPartialMap(true); - - return mlir::WalkResult::advance(); }); func->walk([&](mlir::omp::MapInfoOp op) { @@ -1297,13 +1317,15 @@ class MapInfoFinalizationPass // within a target region. At which point we map the relevant descriptor // data and the runtime should correctly associate the data with the // descriptor and bind together and allow clean mapping and execution. - for (auto *op : deferrableDesc) { - auto mapOp = llvm::dyn_cast(op); - mlir::Operation *targetUser = getFirstTargetUser(mapOp); - assert(targetUser && "expected user of map operation was not found"); - builder.setInsertionPoint(mapOp); - removeTopLevelDescriptor(mapOp, builder, targetUser); - addImplicitDescriptorMapToTargetDataOp(mapOp, builder, *targetUser); + if (deferDescMapping) { + for (auto *op : deferrableDesc) { + auto mapOp = llvm::dyn_cast(op); + mlir::Operation *targetUser = getFirstTargetUser(mapOp); + assert(targetUser && "expected user of map operation was not found"); + builder.setInsertionPoint(mapOp); + removeTopLevelDescriptor(mapOp, builder, targetUser); + addImplicitDescriptorMapToTargetDataOp(mapOp, builder, *targetUser); + } } // Wait until after we have generated all of our maps to add them onto @@ -1317,5 +1339,11 @@ class MapInfoFinalizationPass }); } }; - } // namespace + +std::unique_ptr +flangomp::createMapInfoFinalizationPass(bool deferDescMap) { + MapInfoFinalizationPassOptions options; + options.deferDescMapping = deferDescMap; + return std::make_unique(options); +} diff --git a/flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp b/flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp index 0972861b8450a..87b0b59ea698d 100644 --- a/flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp +++ b/flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp @@ -29,6 +29,7 @@ #include "flang/Optimizer/Dialect/Support/KindMapping.h" #include "flang/Optimizer/HLFIR/HLFIROps.h" #include "flang/Optimizer/OpenMP/Passes.h" +#include "flang/Support/OpenMP-utils.h" #include "mlir/Dialect/Func/IR/FuncOps.h" #include "mlir/Dialect/OpenMP/OpenMPDialect.h" @@ -46,6 +47,7 @@ namespace flangomp { } // namespace flangomp using namespace mlir; +using namespace Fortran::common::openmp; namespace { class MapsForPrivatizedSymbolsPass @@ -189,38 +191,5 @@ class MapsForPrivatizedSymbolsPass } } } - // As the name suggests, this function examines var to determine if - // it has dynamic size. If true, this pass'll have to extract these - // bounds from descriptor of var and add the bounds to the resultant - // MapInfoOp. - bool needsBoundsOps(mlir::Value var) { - assert(mlir::isa(var.getType()) && - "needsBoundsOps can deal only with pointer types"); - mlir::Type t = fir::unwrapRefType(var.getType()); - // t could be a box, so look inside the box - auto innerType = fir::dyn_cast_ptrOrBoxEleTy(t); - if (innerType) - return fir::hasDynamicSize(innerType); - return fir::hasDynamicSize(t); - } - - void genBoundsOps(fir::FirOpBuilder &builder, mlir::Value var, - llvm::SmallVector &boundsOps) { - mlir::Location loc = var.getLoc(); - fir::factory::AddrAndBoundsInfo info = - fir::factory::getDataOperandBaseAddr(builder, var, - /*isOptional=*/false, loc); - fir::ExtendedValue extendedValue = - hlfir::translateToExtendedValue(loc, builder, hlfir::Entity{info.addr}, - /*continguousHint=*/true) - .first; - llvm::SmallVector boundsOpsVec = - fir::factory::genImplicitBoundsOps( - builder, info, extendedValue, - /*dataExvIsAssumedSize=*/false, loc); - for (auto bounds : boundsOpsVec) - boundsOps.push_back(bounds); - } }; } // namespace diff --git a/flang/lib/Optimizer/Passes/Pipelines.cpp b/flang/lib/Optimizer/Passes/Pipelines.cpp index 103e736accca0..d9b1287829cac 100644 --- a/flang/lib/Optimizer/Passes/Pipelines.cpp +++ b/flang/lib/Optimizer/Passes/Pipelines.cpp @@ -334,11 +334,15 @@ void createOpenMPFIRPassPipeline(mlir::PassManager &pm, // to access the data on the offload target device. pm.addPass(flangomp::createMapsForPrivatizedSymbolsPass()); pm.addPass(flangomp::createAutomapToTargetDataPass()); - pm.addPass(flangomp::createMapInfoFinalizationPass()); + pm.addPass(flangomp::createMapInfoFinalizationPass(opts.deferDescMap)); pm.addPass(flangomp::createMarkDeclareTargetPass()); pm.addPass(flangomp::createGenericLoopConversionPass()); - if (opts.isTargetDevice) + if (opts.isTargetDevice) { pm.addPass(flangomp::createFunctionFilteringPass()); + + if (opts.enableOffloadGlobalFiltering) + pm.addPass(flangomp::createGlobalFilteringPass()); + } } void createDebugPasses(mlir::PassManager &pm, diff --git a/flang/lib/Semantics/check-omp-structure.cpp b/flang/lib/Semantics/check-omp-structure.cpp index e094458f001e3..ec69e014fe0e7 100644 --- a/flang/lib/Semantics/check-omp-structure.cpp +++ b/flang/lib/Semantics/check-omp-structure.cpp @@ -1352,9 +1352,17 @@ void OmpStructureChecker::CheckThreadprivateOrDeclareTargetVar( "A variable in a %s directive cannot be an element of a common block"_err_en_US, ContextDirectiveAsFortran()); } else if (FindEquivalenceSet(*name->symbol)) { - context_.Say(name->source, - "A variable in a %s directive cannot appear in an EQUIVALENCE statement"_err_en_US, - ContextDirectiveAsFortran()); + auto allowThreadprivateEquivalence{ + context_.langOptions().AllowThreadprivateEquivalence}; + if (!allowThreadprivateEquivalence) { + context_.Say(name->source, + "A variable in a %s directive cannot appear in an EQUIVALENCE statement"_err_en_US, + ContextDirectiveAsFortran()); + } else { + context_.Say(name->source, + "Variable '%s' appears a %s directive and an EQUIVALENCE statement, which does not conform to the OpenMP API specification."_warn_en_US, + name->symbol->name(), ContextDirectiveAsFortran()); + } } else if (name->symbol->test(Symbol::Flag::OmpThreadprivate) && directive == llvm::omp::Directive::OMPD_declare_target) { context_.Say(name->source, @@ -1398,9 +1406,17 @@ void OmpStructureChecker::CheckThreadprivateOrDeclareTargetVar( if (auto *cb{name.symbol->detailsIf()}) { for (const auto &obj : cb->objects()) { if (FindEquivalenceSet(*obj)) { - context_.Say(name.source, - "A variable in a %s directive cannot appear in an EQUIVALENCE statement (variable '%s' from common block '/%s/')"_err_en_US, - ContextDirectiveAsFortran(), obj->name(), name.symbol->name()); + auto allowThreadprivateEquivalence{ + context_.langOptions().AllowThreadprivateEquivalence}; + if (!allowThreadprivateEquivalence) { + context_.Say(name.source, + "A variable in a %s directive cannot appear in an EQUIVALENCE statement (variable '%s' from common block '/%s/')"_err_en_US, + ContextDirectiveAsFortran(), obj->name(), name.symbol->name()); + } else { + context_.Say(name.source, + "Variable '%s' from common block '%s' appears in an EQUIVALENCE statement and a %s directive, which does not conform to the OpenMP API specification."_warn_en_US, + obj->name(), name.symbol->name(), ContextDirectiveAsFortran()); + } } } } diff --git a/flang/lib/Semantics/resolve-directives.cpp b/flang/lib/Semantics/resolve-directives.cpp index 196755e2912a8..b9a3ad46877d8 100644 --- a/flang/lib/Semantics/resolve-directives.cpp +++ b/flang/lib/Semantics/resolve-directives.cpp @@ -2697,15 +2697,15 @@ static bool IsTargetCaptureImplicitlyFirstprivatizeable(const Symbol &symbol, // as it overrides the implicit Firstprivatization of scalars OpenMP rule. if (!defaultMap.empty()) { if (llvm::is_contained( - defaultMap, parser::OmpVariableCategory::Value::All) && - defaultMap[parser::OmpVariableCategory::Value::All] != + defaultMap, parser::OmpVariableCategory::Value::Scalar) && + defaultMap[parser::OmpVariableCategory::Value::Scalar] != parser::OmpDefaultmapClause::ImplicitBehavior::Firstprivate) { return false; } if (llvm::is_contained( - defaultMap, parser::OmpVariableCategory::Value::Scalar) && - defaultMap[parser::OmpVariableCategory::Value::Scalar] != + defaultMap, parser::OmpVariableCategory::Value::All) && + defaultMap[parser::OmpVariableCategory::Value::All] != parser::OmpDefaultmapClause::ImplicitBehavior::Firstprivate) { return false; } @@ -2887,7 +2887,8 @@ void OmpAttributeVisitor::CreateImplicitSymbols(const Symbol *symbol) { dsa = {dirContext.defaultDSA}; makeSymbol(dsa); PRINT_IMPLICIT_RULE("1) default"); - } else if (parallelDir) { + } else if (!targetDir && parallelDir/*(!enableDelayedPrivatizationStaging && parallelDir) || + (enableDelayedPrivatizationStaging && !targetDir && parallelDir)*/) { // 2) parallel -> shared dsa = {Symbol::Flag::OmpShared}; makeSymbol(dsa); @@ -2901,7 +2902,7 @@ void OmpAttributeVisitor::CreateImplicitSymbols(const Symbol *symbol) { // 4) not mapped target variable -> firstprivate // - i.e. implicit, but meets OpenMP specification rules for // firstprivate "promotion" - if (enableDelayedPrivatizationStaging && + if (/*enableDelayedPrivatizationStaging && */ IsTargetCaptureImplicitlyFirstprivatizeable(*symbol, prevDSA, dataSharingAttributeFlags, dataMappingAttributeFlags, dirContext.defaultMap)) { diff --git a/flang/lib/Support/Fortran-features.cpp b/flang/lib/Support/Fortran-features.cpp index 4a6fb8d75a135..ff8bdbda2cdf4 100644 --- a/flang/lib/Support/Fortran-features.cpp +++ b/flang/lib/Support/Fortran-features.cpp @@ -77,6 +77,7 @@ LanguageFeatureControl::LanguageFeatureControl() { disable_.set(LanguageFeature::CUDA); // !@cuf disable_.set(LanguageFeature::CudaManaged); disable_.set(LanguageFeature::CudaUnified); + disable_.set(LanguageFeature::AmdMemoryAllocator); disable_.set(LanguageFeature::ImplicitNoneTypeNever); disable_.set(LanguageFeature::ImplicitNoneTypeAlways); disable_.set(LanguageFeature::ImplicitNoneExternal); diff --git a/flang/lib/Utils/OpenMP.cpp b/flang/lib/Utils/OpenMP.cpp index c2036c4a383fd..b07caf853191a 100644 --- a/flang/lib/Utils/OpenMP.cpp +++ b/flang/lib/Utils/OpenMP.cpp @@ -155,4 +155,5 @@ void cloneOrMapRegionOutsiders( mlir::getUsedValuesDefinedAbove(region, valuesDefinedAbove); } } + } // namespace Fortran::utils::openmp diff --git a/flang/module/f90deviceio.f90 b/flang/module/f90deviceio.f90 new file mode 100644 index 0000000000000..abc0613f959ab --- /dev/null +++ b/flang/module/f90deviceio.f90 @@ -0,0 +1,31 @@ +! f90print f90printi f90printf f90printd interfaces +! in module file f90deviceio +module f90deviceio + interface + subroutine f90print(N) + character(*) :: N + !$omp declare target (f90print) + end subroutine f90print + subroutine f90printi(N,i) + character(*) :: N + integer :: i + !$omp declare target (f90printi) + end subroutine f90printi + subroutine f90printl(N,i) + character(*) :: N + integer(8) :: i + !$omp declare target (f90printl) + end subroutine f90printl + subroutine f90printf(N,f) + character(*) :: N + real(4) :: f + !$omp declare target (f90printf) + end subroutine f90printf + subroutine f90printd(N,d) + character(*) :: N + real(8) :: d + !$omp declare target (f90printd) + end subroutine f90printd + end interface +end module + diff --git a/flang/test/Driver/arch-specific-libdir-rpath.f95 b/flang/test/Driver/arch-specific-libdir-rpath.f95 index 23fb52abfbd57..15cb27e6926fd 100644 --- a/flang/test/Driver/arch-specific-libdir-rpath.f95 +++ b/flang/test/Driver/arch-specific-libdir-rpath.f95 @@ -32,8 +32,7 @@ ! ! ! RESDIR: "-resource-dir" "[[RESDIR:[^"]*]]" -! ! LIBPATH-X86_64: -L[[RESDIR]]{{(/|\\\\)lib(/|\\\\)linux(/|\\\\)x86_64}} -! RPATH-X86_64: "-rpath" "[[RESDIR]]{{(/|\\\\)lib(/|\\\\)linux(/|\\\\)x86_64}}" ! -! NO-RPATH-X86_64-NOT: "-rpath" "[[RESDIR]]{{(/|\\\\)lib(/|\\\\)linux(/|\\\\)x86_64}}" +! RPATH-X86_64: "-rpath" "{{[^"]*(/|\\\\)resource_dir_with_arch_subdir(/|\\\\)lib(/|\\\\)linux(/|\\\\)x86_64}}" +! NO-RPATH-X86_64-NOT: "-rpath" "{{[^"]*(/|\\\\)resource_dir_with_arch_subdir(/|\\\\)lib(/|\\\\)linux(/|\\\\)x86_64}}" diff --git a/flang/test/Driver/bbc-openmp-version-macro.f90 b/flang/test/Driver/bbc-openmp-version-macro.f90 index 193c9d297de4f..83e85c9fba942 100644 --- a/flang/test/Driver/bbc-openmp-version-macro.f90 +++ b/flang/test/Driver/bbc-openmp-version-macro.f90 @@ -9,7 +9,7 @@ ! RUN: bbc -fopenmp -fopenmp-version=52 -o - %s | FileCheck %s --check-prefix=OPENMP-VERSION-52 ! RUN: bbc -fopenmp -fopenmp-version=60 -o - %s | FileCheck %s --check-prefix=OPENMP-VERSION-60 -! DEFAULT-OPENMP-VERSION: {{.*}} = arith.constant 201107 : i32 +! DEFAULT-OPENMP-VERSION: {{.*}} = arith.constant 202111 : i32 ! OPENMP-VERSION-31: {{.*}} = arith.constant 201107 : i32 ! OPENMP-VERSION-40: {{.*}} = arith.constant 201307 : i32 ! OPENMP-VERSION-45: {{.*}} = arith.constant 201511 : i32 diff --git a/flang/test/Driver/do_concurrent_to_omp_cli.f90 b/flang/test/Driver/do_concurrent_to_omp_cli.f90 index bdb603f35639d..e44db04fb2ce7 100644 --- a/flang/test/Driver/do_concurrent_to_omp_cli.f90 +++ b/flang/test/Driver/do_concurrent_to_omp_cli.f90 @@ -3,12 +3,12 @@ ! RUN: %flang --help | FileCheck %s --check-prefix=FLANG ! FLANG: -fdo-concurrent-to-openmp= -! FLANG-NEXT: Try to map `do concurrent` loops to OpenMP [none|host|device] +! FLANG-NEXT: Try to map `do concurrent` loops to OpenMP [none|host|device] ! RUN: bbc --help | FileCheck %s --check-prefix=BBC ! BBC: -fdo-concurrent-to-openmp= -! BBC-SAME: Try to map `do concurrent` loops to OpenMP [none|host|device] +! BBC-SAME: Try to map `do concurrent` loops to OpenMP [none|host|device] ! RUN: %flang -c -fdo-concurrent-to-openmp=host %s 2>&1 \ ! RUN: | FileCheck %s --check-prefix=OPT diff --git a/flang/test/Driver/fast-math.f90 b/flang/test/Driver/fast-math.f90 index e677432bc04fa..ac60c0500e49e 100644 --- a/flang/test/Driver/fast-math.f90 +++ b/flang/test/Driver/fast-math.f90 @@ -1,5 +1,6 @@ ! Test for correct forwarding of fast-math flags from the compiler driver to the ! frontend driver +! REQUIRES: StableDriver ! Check warning message for Ofast deprecation ! RUN: %flang -Ofast -### %s -o %t 2>&1 | FileCheck %s diff --git a/flang/test/Driver/fdefault.f90 b/flang/test/Driver/fdefault.f90 index 7ce45b763a240..356b5c77666f4 100644 --- a/flang/test/Driver/fdefault.f90 +++ b/flang/test/Driver/fdefault.f90 @@ -23,6 +23,30 @@ ! RUN: cat %t/dir-flang/m.mod | FileCheck %s --check-prefix=DOUBLE8 ! RUN: not %flang_fc1 -fsyntax-only -fdefault-double-8 %s 2>&1 | FileCheck %s --check-prefix=ERROR +! TODO: Add checks when actual codegen is possible for this family + +!-------------------------- +! FLANG DRIVER (flang) +!-------------------------- +! RUN: rm -rf %t/dir-flang && mkdir -p %t/dir-flang && %flang -fsyntax-only -module-dir %t/dir-flang %s 2>&1 +! RUN: cat %t/dir-flang/m.mod | FileCheck %s --check-prefix=NOOPTION +! RUN: rm -rf %t/dir-flang && mkdir -p %t/dir-flang && %flang -fsyntax-only -fdefault-real-8 -module-dir %t/dir-flang %s 2>&1 +! RUN: cat %t/dir-flang/m.mod | FileCheck %s --check-prefix=REAL8 +! RUN: rm -rf %t/dir-flang && mkdir -p %t/dir-flang && %flang -fsyntax-only -fdefault-real-8 -fdefault-double-8 -module-dir %t/dir-flang %s 2>&1 +! RUN: cat %t/dir-flang/m.mod | FileCheck %s --check-prefix=DOUBLE8 +! RUN: not %flang -fsyntax-only -fdefault-double-8 %s 2>&1 | FileCheck %s --check-prefix=ERROR + +!----------------------------------------- +! FRONTEND FLANG DRIVER (flang -fc1) +!----------------------------------------- +! RUN: rm -rf %t/dir-flang && mkdir -p %t/dir-flang && %flang_fc1 -fsyntax-only -module-dir %t/dir-flang %s 2>&1 +! RUN: cat %t/dir-flang/m.mod | FileCheck %s --check-prefix=NOOPTION +! RUN: rm -rf %t/dir-flang && mkdir -p %t/dir-flang && %flang_fc1 -fsyntax-only -fdefault-real-8 -module-dir %t/dir-flang %s 2>&1 +! RUN: cat %t/dir-flang/m.mod | FileCheck %s --check-prefix=REAL8 +! RUN: rm -rf %t/dir-flang && mkdir -p %t/dir-flang && %flang_fc1 -fsyntax-only -fdefault-real-8 -fdefault-double-8 -module-dir %t/dir-flang %s 2>&1 +! RUN: cat %t/dir-flang/m.mod | FileCheck %s --check-prefix=DOUBLE8 +! RUN: not %flang_fc1 -fsyntax-only -fdefault-double-8 %s 2>&1 | FileCheck %s --check-prefix=ERROR + ! NOOPTION: integer(4),parameter::real_kind=4_4 ! NOOPTION-NEXT: intrinsic::kind ! NOOPTION-NEXT: integer(4),parameter::double_kind=8_4 diff --git a/flang/test/Driver/flang-openmp-version-macro.f90 b/flang/test/Driver/flang-openmp-version-macro.f90 index fcabfefca7f18..c273479dbb7d6 100644 --- a/flang/test/Driver/flang-openmp-version-macro.f90 +++ b/flang/test/Driver/flang-openmp-version-macro.f90 @@ -9,7 +9,7 @@ ! RUN: %flang_fc1 -fopenmp -fopenmp-version=52 -cpp -E %s | FileCheck %s --check-prefix=OPENMP-VERSION-52 ! RUN: %flang_fc1 -fopenmp -fopenmp-version=60 -cpp -E %s | FileCheck %s --check-prefix=OPENMP-VERSION-60 -! DEFAULT-OPENMP-VERSION: integer :: var1 = 201107 +! DEFAULT-OPENMP-VERSION: integer :: var1 = 202111 ! OPENMP-VERSION-31: integer :: var1 = 201107 ! OPENMP-VERSION-40: integer :: var1 = 201307 ! OPENMP-VERSION-45: integer :: var1 = 201511 diff --git a/flang/test/Driver/fopenmp-version.F90 b/flang/test/Driver/fopenmp-version.F90 index 59406d3dd32c8..7f1396dbc9181 100644 --- a/flang/test/Driver/fopenmp-version.F90 +++ b/flang/test/Driver/fopenmp-version.F90 @@ -17,13 +17,9 @@ !RUN: %flang -c -fopenmp -fopenmp-version=25 %s 2>&1 | FileCheck --check-prefix=WARN-ASSUMED %s -!WARN-ASSUMED: warning: OpenMP version 25 is no longer supported, assuming version 31 +!WARN-ASSUMED: warning: OpenMP version 25 is no longer supported, assuming version 52 !RUN: not %flang -c -fopenmp -fopenmp-version=29 %s 2>&1 | FileCheck --check-prefix=ERR-BAD %s -!ERR-BAD: error: '29' is not a valid OpenMP version in '-fopenmp-version=29', valid versions are 31, 40, 45, 50, 51, 52, 60, 61 - -!RUN: %flang -c -fopenmp -fopenmp-version=61 %s 2>&1 | FileCheck --check-prefix=FUTURE %s - -!FUTURE: The specification for OpenMP version 61 is still under development; the syntax and semantics of new features may be subject to change +!ERR-BAD: error: '29' is not a valid OpenMP version in '-fopenmp-version=29', valid versions are 31, 40, 45, 50, 51, 52, 60 diff --git a/flang/test/Driver/fopenmp.f90 b/flang/test/Driver/fopenmp.f90 index f7e83e0eeb734..ed9a18d4f32a7 100644 --- a/flang/test/Driver/fopenmp.f90 +++ b/flang/test/Driver/fopenmp.f90 @@ -74,6 +74,3 @@ ! CHECK-LD-ANYMD: "{{.*}}ld{{(.exe)?}}" ! CHECK-LD-ANYMD: "-l{{(omp|gomp|iomp5md)}}" ! -! RUN: %flang -fopenmp -fopenmp-version=40 -c %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-INCOMPLETE -! -! CHECK-INCOMPLETE: warning: OpenMP support for version 40 in flang is still incomplete diff --git a/flang/test/Driver/linker-flags.f90 b/flang/test/Driver/linker-flags.f90 index 2b56fdfb8da05..d0f6f83e1336a 100644 --- a/flang/test/Driver/linker-flags.f90 +++ b/flang/test/Driver/linker-flags.f90 @@ -1,6 +1,7 @@ ! Verify that the Fortran runtime libraries are present in the linker ! invocation. These libraries are added on top of other standard runtime ! libraries that the Clang driver will include. +! REQUIRES: StableDriver ! RUN: %flang -### --target=ppc64le-linux-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,UNIX,UNIX-F128%f128-lib ! RUN: %flang -### --target=sparc-sun-solaris2.11 %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,UNIX,SOLARIS-F128%f128-lib diff --git a/flang/test/Driver/omp-driver-offload.f90 b/flang/test/Driver/omp-driver-offload.f90 index 09248572b9ff5..5f59fc54f9f31 100644 --- a/flang/test/Driver/omp-driver-offload.f90 +++ b/flang/test/Driver/omp-driver-offload.f90 @@ -135,8 +135,8 @@ ! RUN: %flang -### %s -o %t 2>&1 \ ! RUN: -fopenmp --offload-arch=sm_70 \ ! RUN: -fopenmp-targets=nvptx64-nvidia-cuda \ -! RUN: -fopenmp-target-debug=111 \ -! RUN: | FileCheck %s --check-prefixes=CHECK-TARGET-DEBUG-EQ +! RUN: -fopenmp-target-debug \ +! RUN: | FileCheck %s --check-prefixes=CHECK-TARGET-DEBUG ! CHECK-TARGET-DEBUG-EQ: "{{[^"]*}}flang" "-fc1" {{.*}} "-fopenmp" {{.*}} "-fopenmp-is-target-device" "-fopenmp-target-debug=111" {{.*}}.f90" ! RUN: %flang -S -### %s -o %t 2>&1 \ diff --git a/flang/test/Driver/pic-flags.f90 b/flang/test/Driver/pic-flags.f90 index 5a06163c485cd..7ddcce94f50c9 100644 --- a/flang/test/Driver/pic-flags.f90 +++ b/flang/test/Driver/pic-flags.f90 @@ -1,4 +1,5 @@ ! RUN: %if aarch64-registered-target %{ %flang -v -S -emit-llvm -o - %s --target=aarch64-linux-gnu -fno-pie 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-STATIC,CHECK-STATIC-IR %} +! REQUIRES: StableDriver ! RUN: %if aarch64-registered-target && clang_default_pie_on_linux %{ %flang -v -S -emit-llvm -o - %s --target=aarch64-linux-gnu 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-PIE-LEVEL2,CHECK-PIE-LEVEL2-IR %} ! RUN: %if aarch64-registered-target %{ %flang -v -S -emit-llvm -o - %s --target=aarch64-linux-gnu -fpie 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-PIE-LEVEL1,CHECK-PIE-LEVEL1-IR %} diff --git a/flang/test/Driver/target-gpu-mandatory.f90 b/flang/test/Driver/target-gpu-mandatory.f90 new file mode 100644 index 0000000000000..43daf66c56653 --- /dev/null +++ b/flang/test/Driver/target-gpu-mandatory.f90 @@ -0,0 +1,7 @@ +! REQUIRES: amdgpu-registered-target + +! Test that -foffload-mandatory is accepted + +! RUN: %flang --target=amdgcn-amd-amdhsa -mcpu=gfx902 -fopenmp-offload-mandatory -nogpulib -c %s -### 2>&1 \ +! RUN: | FileCheck %s -check-prefix=CHECK-MANDO +! CHECK-MANDO: "gfx902" diff --git a/flang/test/Fir/polymorphic.fir b/flang/test/Fir/polymorphic.fir index 84fa2e950633f..f2b5c184b3d51 100644 --- a/flang/test/Fir/polymorphic.fir +++ b/flang/test/Fir/polymorphic.fir @@ -1,5 +1,4 @@ // RUN: tco %s | FileCheck %s - // Test code gen for unlimited polymorphic type descriptor. func.func @_QMpolymorphic_testPtest_allocate_unlimited_polymorphic_non_derived() { diff --git a/flang/test/Integration/OpenMP/map-types-and-sizes.f90 b/flang/test/Integration/OpenMP/map-types-and-sizes.f90 index 44a049f5ac510..663041b34e589 100644 --- a/flang/test/Integration/OpenMP/map-types-and-sizes.f90 +++ b/flang/test/Integration/OpenMP/map-types-and-sizes.f90 @@ -6,7 +6,8 @@ ! added to this directory and sub-directories. !===----------------------------------------------------------------------===! -!RUN: %flang_fc1 -emit-llvm -fopenmp -mmlir --enable-delayed-privatization-staging=false -fopenmp-version=51 -fopenmp-targets=amdgcn-amd-amdhsa %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FPRIV +! NOTE: Do not check for false delayed privatization flag until all enable-delayed-privatization flags are switched on in amd-staging +!RUN %flang_fc1 -emit-llvm -fopenmp -mmlir --enable-delayed-privatization-staging=false -fopenmp-version=51 -fopenmp-targets=amdgcn-amd-amdhsa %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FPRIV !RUN: %flang_fc1 -emit-llvm -fopenmp -mmlir --enable-delayed-privatization-staging=true -fopenmp-version=51 -fopenmp-targets=amdgcn-amd-amdhsa %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPRIV @@ -33,8 +34,8 @@ subroutine mapType_array !$omp end target end subroutine mapType_array -!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [4 x i64] [i64 0, i64 24, i64 8, i64 0] -!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [4 x i64] [i64 32, i64 281474976711169, i64 281474976711171, i64 281474976711187] +!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [5 x i64] [i64 0, i64 0, i64 0, i64 8, i64 0] +!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [5 x i64] [i64 32, i64 281474976727557, i64 281474976727557, i64 281474976711171, i64 281474976711187] subroutine mapType_ptr integer, pointer :: a !$omp target @@ -73,8 +74,8 @@ subroutine map_ompx_hold !$omp end target data end subroutine -!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [4 x i64] [i64 0, i64 24, i64 8, i64 0] -!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [4 x i64] [i64 32, i64 281474976711169, i64 281474976711171, i64 281474976711187] +!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [5 x i64] [i64 0, i64 0, i64 0, i64 8, i64 0] +!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [5 x i64] [i64 32, i64 281474976727557, i64 281474976727557, i64 281474976711171, i64 281474976711187] subroutine mapType_allocatable integer, allocatable :: a allocate(a) @@ -84,8 +85,8 @@ subroutine mapType_allocatable deallocate(a) end subroutine mapType_allocatable -!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [4 x i64] [i64 0, i64 24, i64 8, i64 0] -!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [4 x i64] [i64 32, i64 281474976710657, i64 281474976710659, i64 281474976710675] +!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [5 x i64] [i64 0, i64 0, i64 0, i64 8, i64 0] +!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [5 x i64] [i64 32, i64 281474976727045, i64 281474976727045, i64 281474976710659, i64 281474976710675] subroutine mapType_ptr_explicit integer, pointer :: a !$omp target map(tofrom: a) @@ -93,8 +94,8 @@ subroutine mapType_ptr_explicit !$omp end target end subroutine mapType_ptr_explicit -!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [4 x i64] [i64 0, i64 24, i64 8, i64 0] -!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [4 x i64] [i64 32, i64 281474976710657, i64 281474976710659, i64 281474976710675] +!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [5 x i64] [i64 0, i64 0, i64 0, i64 8, i64 0] +!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [5 x i64] [i64 32, i64 281474976727045, i64 281474976727045, i64 281474976710659, i64 281474976710675] subroutine mapType_allocatable_explicit integer, allocatable :: a allocate(a) @@ -246,7 +247,7 @@ subroutine mapType_derived_explicit_nested_member_with_bounds end subroutine mapType_derived_explicit_nested_member_with_bounds !CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [4 x i64] [i64 0, i64 48, i64 8, i64 0] -!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [4 x i64] [i64 32, i64 281474976710657, i64 281474976710659, i64 281474976710675] +!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [4 x i64] [i64 32, i64 281474976727045, i64 281474976710659, i64 281474976710675] subroutine mapType_derived_type_alloca() type :: one_layer real(4) :: i @@ -266,8 +267,8 @@ subroutine mapType_derived_type_alloca() !$omp end target end subroutine -!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [8 x i64] [i64 0, i64 40, i64 8, i64 0, i64 48, i64 8, i64 0, i64 4] -!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [8 x i64] [i64 32, i64 281474976710657, i64 281474976710659, i64 281474976710675, i64 281474976710657, i64 281474976710659, i64 281474976710675, i64 281474976710659] +!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [9 x i64] [i64 0, i64 0, i64 0, i64 8, i64 0, i64 48, i64 8, i64 0, i64 4] +!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [9 x i64] [i64 32, i64 281474976727045, i64 281474976727045, i64 281474976710656, i64 281474976710672, i64 281474976727045, i64 281474976710659, i64 281474976710675, i64 281474976710659] subroutine mapType_alloca_derived_type() type :: one_layer real(4) :: i @@ -289,8 +290,8 @@ subroutine mapType_alloca_derived_type() !$omp end target end subroutine -!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [8 x i64] [i64 0, i64 40, i64 8, i64 0, i64 48, i64 8, i64 0, i64 4] -!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [8 x i64] [i64 32, i64 281474976710657, i64 281474976710659, i64 281474976710675, i64 281474976710657, i64 281474976710659, i64 281474976710675, i64 281474976710659] +!CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [9 x i64] [i64 0, i64 0, i64 0, i64 8, i64 0, i64 48, i64 8, i64 0, i64 4] +!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [9 x i64] [i64 32, i64 281474976727045, i64 281474976727045, i64 281474976710656, i64 281474976710672, i64 281474976727045, i64 281474976710659, i64 281474976710675, i64 281474976710659] subroutine mapType_alloca_nested_derived_type() type :: middle_layer real(4) :: i @@ -321,7 +322,7 @@ subroutine mapType_alloca_nested_derived_type() end subroutine !CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [4 x i64] [i64 0, i64 48, i64 8, i64 0] -!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [4 x i64] [i64 32, i64 281474976710657, i64 281474976710659, i64 281474976710675] +!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [4 x i64] [i64 32, i64 281474976727045, i64 281474976710659, i64 281474976710675] subroutine mapType_nested_derived_type_alloca() type :: middle_layer real(4) :: i @@ -350,7 +351,7 @@ subroutine mapType_nested_derived_type_alloca() end subroutine !CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [7 x i64] [i64 0, i64 64, i64 8, i64 0, i64 48, i64 8, i64 0] -!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [7 x i64] [i64 32, i64 281474976710657, i64 281474976710656, i64 281474976710672, i64 281474976710657, i64 281474976710659, i64 281474976710675] +!CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [7 x i64] [i64 32, i64 281474976727045, i64 281474976710656, i64 281474976710672, i64 281474976727045, i64 281474976710659, i64 281474976710675] subroutine mapType_nested_derived_type_member_idx() type :: vertexes integer :: test @@ -428,7 +429,7 @@ end subroutine mapType_common_block_members !CHECK: %[[ALLOCA_INT:.*]] = ptrtoint ptr %[[ALLOCA]] to i64 !CHECK: %[[SIZE_DIFF:.*]] = sub i64 %[[ALLOCA_GEP_INT]], %[[ALLOCA_INT]] !CHECK: %[[DIV:.*]] = sdiv exact i64 %[[SIZE_DIFF]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) -!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [4 x i64], ptr %.offload_sizes, i32 0, i32 0 +!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [5 x i64], ptr %.offload_sizes, i32 0, i32 0 !CHECK: store i64 %[[DIV]], ptr %[[OFFLOAD_SIZE_ARR]], align 8 !CHECK-LABEL: define {{.*}} @{{.*}}maptype_allocatable_explicit_{{.*}} @@ -438,7 +439,7 @@ end subroutine mapType_common_block_members !CHECK: %[[ALLOCA_INT:.*]] = ptrtoint ptr %[[ALLOCA]] to i64 !CHECK: %[[SIZE_DIFF:.*]] = sub i64 %[[ALLOCA_GEP_INT]], %[[ALLOCA_INT]] !CHECK: %[[DIV:.*]] = sdiv exact i64 %[[SIZE_DIFF]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) -!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [4 x i64], ptr %.offload_sizes, i32 0, i32 0 +!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [5 x i64], ptr %.offload_sizes, i32 0, i32 0 !CHECK: store i64 %[[DIV]], ptr %[[OFFLOAD_SIZE_ARR]], align 8 !CHECK-LABEL: define {{.*}} @{{.*}}maptype_derived_implicit_{{.*}} @@ -554,7 +555,7 @@ end subroutine mapType_common_block_members !CHECK: %[[MEMBER_BASE_ADDR_SIZE:.*]] = mul i64 1, %[[RESTORE_OFFSET]] !CHECK: %[[DESC_BASE_ADDR_DATA_SIZE:.*]] = mul i64 %[[MEMBER_BASE_ADDR_SIZE]], 4 !CHECK: %[[LOAD_ADDR_DATA:.*]] = load ptr, ptr %[[MEMBER_DESCRIPTOR_BASE_ADDR]], align 8 -!CHECK: %[[GEP_ADDR_DATA:.*]] = getelementptr inbounds i32, ptr %[[LOAD_ADDR_DATA]], i64 0 +!CHECK: %[[GEP_ADDR_DATA:.*]] = getelementptr inbounds i32, ptr %[[LOAD_ADDR_DATA]] !CHECK: %[[MEMBER_ACCESS_ADDR_END:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr %[[MEMBER_ACCESS]], i64 1 !CHECK: %[[MEMBER_ACCESS_ADDR_INT:.*]] = ptrtoint ptr %[[MEMBER_ACCESS_ADDR_END]] to i64 !CHECK: %[[MEMBER_ACCESS_ADDR_BEGIN:.*]] = ptrtoint ptr %[[MEMBER_ACCESS]] to i64 @@ -603,7 +604,6 @@ end subroutine mapType_common_block_members !CHECK: %[[DTYPE_BASE_ADDR_LOAD:.*]] = load ptr, ptr %[[DTYPE_BASE_ADDR_ACCESS]], align 8 !CHECK: %[[DTYPE_ALLOCA_MEMBER_ACCESS:.*]] = getelementptr %_QFmaptype_alloca_derived_typeTone_layer, ptr %[[DTYPE_BASE_ADDR_LOAD]], i32 0, i32 4 !CHECK: %[[DTYPE_ALLOCA_MEMBER_BASE_ADDR_ACCESS:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr %[[DTYPE_ALLOCA_MEMBER_ACCESS]], i32 0, i32 0 - !CHECK: %[[DTYPE_BASE_ADDR_ACCESS_2:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[DTYPE_DESC_ALLOCA]], i32 0, i32 0 !CHECK: %[[DTYPE_BASE_ADDR_LOAD_2:.*]] = load ptr, ptr %[[DTYPE_BASE_ADDR_ACCESS_2]], align 8 !CHECK: %[[DTYPE_NONALLOCA_MEMBER_ACCESS:.*]] = getelementptr %_QFmaptype_alloca_derived_typeTone_layer, ptr %[[DTYPE_BASE_ADDR_LOAD_2]], i32 0, i32 5 @@ -620,43 +620,48 @@ end subroutine mapType_common_block_members !CHECK: %[[DTYPE_BEGIN:.*]] = ptrtoint ptr %[[DTYPE_DESC_ALLOCA_3]] to i64 !CHECK: %[[DTYPE_DESC_SZ_CALC:.*]] = sub i64 %[[DTYPE_END]], %[[DTYPE_BEGIN]] !CHECK: %[[DTYPE_DESC_SZ:.*]] = sdiv exact i64 %[[DTYPE_DESC_SZ_CALC]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) +!CHECK: %[[DTYPE_BASE_ADDR_ACCESS_4:.*]] = getelementptr ptr, ptr %[[DTYPE_BASE_ADDR_ACCESS_3]], i32 1 !CHECK: %[[SIZE_CMP:.*]] = icmp eq ptr %[[MEMBER_ARRAY_OFFSET]], null !CHECK: %[[SIZE_SEL:.*]] = select i1 %[[SIZE_CMP]], i64 0, i64 %[[MEMBER_SIZE_CALC_4]] -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 0 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 0 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [8 x i64], ptr %.offload_sizes, i32 0, i32 0 +!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [9 x i64], ptr %.offload_sizes, i32 0, i32 0 !CHECK: store i64 %[[DTYPE_DESC_SZ]], ptr %[[OFFLOAD_SIZE_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 1 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 1 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 1 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 1 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 2 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 2 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 2 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 2 +!CHECK: store ptr %[[DTYPE_BASE_ADDR_ACCESS_4]], ptr %[[OFFLOAD_PTR_ARR]], align 8 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 3 +!CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 3 !CHECK: store ptr %[[DTYPE_BASE_ADDR_ACCESS_3]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 3 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 4 !CHECK: store ptr %[[DTYPE_BASE_ADDR_ACCESS_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 3 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 4 !CHECK: store ptr %[[DTYPE_BASE_ADDR_LOAD_3]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 4 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 5 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 4 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 5 !CHECK: store ptr %[[DTYPE_ALLOCA_MEMBER_ACCESS]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 5 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 6 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 5 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 6 !CHECK: store ptr %[[DTYPE_ALLOCA_MEMBER_BASE_ADDR_ACCESS]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 6 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 7 !CHECK: store ptr %[[DTYPE_ALLOCA_MEMBER_BASE_ADDR_ACCESS]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 6 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 7 !CHECK: store ptr %[[MEMBER_ARRAY_OFFSET]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [8 x i64], ptr %.offload_sizes, i32 0, i32 6 +!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [9 x i64], ptr %.offload_sizes, i32 0, i32 7 !CHECK: store i64 %[[SIZE_SEL]], ptr %[[OFFLOAD_SIZE_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 7 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 8 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 7 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 8 !CHECK: store ptr %[[DTYPE_NONALLOCA_MEMBER_ACCESS]], ptr %[[OFFLOAD_PTR_ARR]], align 8 !CHECK-LABEL: define {{.*}} @{{.*}}maptype_alloca_nested_derived_type{{.*}} @@ -690,43 +695,48 @@ end subroutine mapType_common_block_members !CHECK: %[[DTYPE_DESC_SIZE_CALC_3:.*]] = ptrtoint ptr %[[DTYPE_DESC_ALLOCA_3]] to i64 !CHECK: %[[DTYPE_DESC_SIZE_CALC_4:.*]] = sub i64 %[[DTYPE_DESC_SIZE_CALC_2]], %[[DTYPE_DESC_SIZE_CALC_3]] !CHECK: %[[DTYPE_DESC_SIZE_CALC_5:.*]] = sdiv exact i64 %[[DTYPE_DESC_SIZE_CALC_4]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) +!CHECK: %[[DTYPE_END_ADDR:.*]] = getelementptr ptr, ptr %[[DTYPE_DESC_BASE_ADDR]], i32 1 !CHECK: %[[DATA_CMP:.*]] = icmp eq ptr %[[ARRAY_OFFSET]], null !CHECK: %[[DATA_SEL:.*]] = select i1 %[[DATA_CMP]], i64 0, i64 %[[ALLOCATABLE_MEMBER_SIZE_CALC_5]] -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 0 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 0 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [8 x i64], ptr %.offload_sizes, i32 0, i32 0 +!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [9 x i64], ptr %.offload_sizes, i32 0, i32 0 !CHECK: store i64 %[[DTYPE_DESC_SIZE_CALC_5]], ptr %[[OFFLOAD_SIZE_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 1 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 1 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 1 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 1 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 2 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 2 +!CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 2 +!CHECK: store ptr %[[DTYPE_END_ADDR]], ptr %[[OFFLOAD_PTR_ARR]], align 8 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 3 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 2 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 3 !CHECK: store ptr %[[DTYPE_DESC_BASE_ADDR]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 3 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 4 !CHECK: store ptr %[[DTYPE_DESC_BASE_ADDR]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 3 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 4 !CHECK: store ptr %[[LOAD_BASE_ADDR]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 4 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 5 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 4 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 5 !CHECK: store ptr %[[MAPPED_MEMBER_ACCESS]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 5 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 6 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 5 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 6 !CHECK: store ptr %[[MAPPED_MEMBER_BASE_ADDR_ACCESS]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 6 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 7 !CHECK: store ptr %[[MAPPED_MEMBER_BASE_ADDR_ACCESS]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 6 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 7 !CHECK: store ptr %[[ARRAY_OFFSET]], ptr %[[OFFLOAD_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [8 x i64], ptr %.offload_sizes, i32 0, i32 6 +!CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [9 x i64], ptr %.offload_sizes, i32 0, i32 7 !CHECK: store i64 %[[DATA_SEL]], ptr %[[OFFLOAD_SIZE_ARR]], align 8 -!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_baseptrs, i32 0, i32 7 +!CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_baseptrs, i32 0, i32 8 !CHECK: store ptr %[[DTYPE_DESC_ALLOCA_3]], ptr %[[BASE_PTR_ARR]], align 8 -!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [8 x ptr], ptr %.offload_ptrs, i32 0, i32 7 +!CHECK: %[[OFFLOAD_PTR_ARR:.*]] = getelementptr inbounds [9 x ptr], ptr %.offload_ptrs, i32 0, i32 8 !CHECK: store ptr %[[NESTED_NONALLOCA_MEMBER_ACCESS]], ptr %[[OFFLOAD_PTR_ARR]], align 8 !CHECK-LABEL: define {{.*}} @{{.*}}maptype_nested_derived_type_alloca{{.*}} @@ -854,6 +864,7 @@ end subroutine mapType_common_block_members !CHECK: store ptr %[[ARR_OFFS_1]], ptr %[[OFFLOAD_PTR_ARR]], align 8 !CHECK: %[[OFFLOAD_SIZE_ARR:.*]] = getelementptr inbounds [7 x i64], ptr %.offload_sizes, i32 0, i32 6 !CHECK: store i64 %[[SIZE_SEL2]], ptr %[[OFFLOAD_SIZE_ARR]], align 8 + !CHECK-LABEL: define {{.*}} @{{.*}}maptype_common_block_{{.*}} !CHECK: %[[BASE_PTR_ARR:.*]] = getelementptr inbounds [1 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 !CHECK: store ptr @var_common_, ptr %[[BASE_PTR_ARR]], align 8 diff --git a/flang/test/Integration/OpenMP/target-nesting-in-host-ops.f90 b/flang/test/Integration/OpenMP/target-nesting-in-host-ops.f90 new file mode 100644 index 0000000000000..8c85a3c1784ed --- /dev/null +++ b/flang/test/Integration/OpenMP/target-nesting-in-host-ops.f90 @@ -0,0 +1,87 @@ +!===----------------------------------------------------------------------===! +! This directory can be used to add Integration tests involving multiple +! stages of the compiler (for eg. from Fortran to LLVM IR). It should not +! contain executable tests. We should only add tests here sparingly and only +! if there is no other way to test. Repeat this message in each test that is +! added to this directory and sub-directories. +!===----------------------------------------------------------------------===! + +!REQUIRES: amdgpu-registered-target +!RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-llvm -fopenmp -fopenmp-version=50 -fopenmp-is-target-device %s -o - | FileCheck %s + +! CHECK-NOT: define void @nested_target_in_parallel +! CHECK: define weak_odr protected amdgpu_kernel void @__omp_offloading_{{.*}}_nested_target_in_parallel_{{.*}}(ptr %{{.*}}, ptr %{{.*}}) +subroutine nested_target_in_parallel(v) + implicit none + integer, intent(inout) :: v(10) + + !$omp parallel + !$omp target map(tofrom: v) + !$omp end target + !$omp end parallel +end subroutine + +! CHECK-NOT: define void @nested_target_in_wsloop +! CHECK: define weak_odr protected amdgpu_kernel void @__omp_offloading_{{.*}}_nested_target_in_wsloop_{{.*}}(ptr %{{.*}}, ptr %{{.*}}) +subroutine nested_target_in_wsloop(v) + implicit none + integer, intent(inout) :: v(10) + integer :: i + + !$omp do + do i=1, 10 + !$omp target map(tofrom: v) + !$omp end target + end do +end subroutine + +! CHECK-NOT: define void @nested_target_in_parallel_with_private +! CHECK: define weak_odr protected amdgpu_kernel void @__omp_offloading_{{.*}}_nested_target_in_parallel_with_private_{{.*}}(ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) +subroutine nested_target_in_parallel_with_private(v) + implicit none + integer, intent(inout) :: v(10) + integer :: x + x = 10 + + !$omp parallel firstprivate(x) + !$omp target map(tofrom: v(1:x)) + !$omp end target + !$omp end parallel +end subroutine + +! CHECK-NOT: define void @nested_target_in_task_with_private +! CHECK: define weak_odr protected amdgpu_kernel void @__omp_offloading_{{.*}}_nested_target_in_task_with_private_{{.*}}(ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) +subroutine nested_target_in_task_with_private(v) + implicit none + integer, intent(inout) :: v(10) + integer :: x + x = 10 + + !$omp task firstprivate(x) + !$omp target map(tofrom: v(1:x)) + !$omp end target + !$omp end task +end subroutine + +! CHECK-NOT: define void @target_and_atomic_update +! CHECK: define weak_odr protected amdgpu_kernel void @__omp_offloading_{{.*}}_target_and_atomic_update_{{.*}}(ptr %{{.*}}) +subroutine target_and_atomic_update(x, expr) + implicit none + integer, intent(inout) :: x, expr + + !$omp target + !$omp end target + + !$omp atomic update + x = x + expr +end subroutine + +! CHECK-NOT: define void @nested_target_in_associate +! CHECK: define weak_odr protected amdgpu_kernel void @__omp_offloading_{{.*}}_nested_target_in_associate_{{.*}}(ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) +subroutine nested_target_in_associate(x) + integer, pointer, contiguous :: x(:) + associate(y => x) + !$omp target map(tofrom: y) + !$omp end target + end associate +end subroutine diff --git a/flang/test/Integration/OpenMP/task-target-device.f90 b/flang/test/Integration/OpenMP/task-target-device.f90 new file mode 100644 index 0000000000000..b92dee65e3f7f --- /dev/null +++ b/flang/test/Integration/OpenMP/task-target-device.f90 @@ -0,0 +1,37 @@ +!===----------------------------------------------------------------------===! +! This directory can be used to add Integration tests involving multiple +! stages of the compiler (for eg. from Fortran to LLVM IR). It should not +! contain executable tests. We should only add tests here sparingly and only +! if there is no other way to test. Repeat this message in each test that is +! added to this directory and sub-directories. +!===----------------------------------------------------------------------===! + +!REQUIRES: amdgpu-registered-target +!RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-llvm -fopenmp -fopenmp-version=50 -fopenmp-is-target-device %s -o - | FileCheck %s + +! This tests the fix for https://github.com/llvm/llvm-project/issues/84606 +! We are only interested in ensuring that the -mlir-to-llmvir pass doesn't crash. + +! CHECK: define weak_odr protected amdgpu_kernel void @{{.*}}QQmain{{.*}}({{.*}}) +program main + implicit none + integer, parameter :: N = 5 + integer, dimension(5) :: a + integer :: i + integer :: target_a = 0 + + !$omp task depend(out:a) + do i = 1, N + a(i) = i + end do + !$omp end task + + !$omp target map(tofrom:target_a) map(tofrom:a) + do i = 1, N + target_a = target_a + i + a(i) = a(i) + i + end do + !$omp end target + print*, target_a + print*, a +end program main diff --git a/flang/test/Integration/OpenMP/threadprivate-target-device.f90 b/flang/test/Integration/OpenMP/threadprivate-target-device.f90 new file mode 100644 index 0000000000000..662d6c6357af0 --- /dev/null +++ b/flang/test/Integration/OpenMP/threadprivate-target-device.f90 @@ -0,0 +1,40 @@ +!===----------------------------------------------------------------------===! +! This directory can be used to add Integration tests involving multiple +! stages of the compiler (for eg. from Fortran to LLVM IR). It should not +! contain executable tests. We should only add tests here sparingly and only +! if there is no other way to test. Repeat this message in each test that is +! added to this directory and sub-directories. +!===----------------------------------------------------------------------===! + +!REQUIRES: amdgpu-registered-target +!RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-llvm -fopenmp -fopenmp-version=50 -fopenmp-is-target-device %s -o - | FileCheck %s + +! The aim of this test is to verify host threadprivate directives do not cause +! crashes during OpenMP target device codegen when used in conjunction with +! target code in the same function. + +! CHECK: define weak_odr protected amdgpu_kernel void @{{.*}}(ptr %{{.*}}, ptr %[[ARG1:.*]], ptr %[[ARG2:.*]]) #{{[0-9]+}} { +! CHECK: %[[ALLOCA_X:.*]] = alloca ptr, align 8, addrspace(5) +! CHECK: %[[ASCAST_X:.*]] = addrspacecast ptr addrspace(5) %[[ALLOCA_X]] to ptr +! CHECK: store ptr %[[ARG1]], ptr %[[ASCAST_X]], align 8 + +! CHECK: %[[ALLOCA_N:.*]] = alloca ptr, align 8, addrspace(5) +! CHECK: %[[ASCAST_N:.*]] = addrspacecast ptr addrspace(5) %[[ALLOCA_N]] to ptr +! CHECK: store ptr %[[ARG2]], ptr %[[ASCAST_N]], align 8 + +! CHECK: %[[LOAD_X:.*]] = load ptr, ptr %[[ASCAST_X]], align 8 +! CHECK: call void @bar_(ptr %[[LOAD_X]], ptr %[[ASCAST_N]]) + +module test + implicit none + integer :: n + !$omp threadprivate(n) + + contains + subroutine foo(x) + integer, intent(inout) :: x(10) + !$omp target map(tofrom: x(1:n)) + call bar(x, n) + !$omp end target + end subroutine +end module diff --git a/flang/test/Integration/amdgpu/debug-declare-target-function-var.f90 b/flang/test/Integration/amdgpu/debug-declare-target-function-var.f90 new file mode 100644 index 0000000000000..a3f89210a57bd --- /dev/null +++ b/flang/test/Integration/amdgpu/debug-declare-target-function-var.f90 @@ -0,0 +1,23 @@ +! RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-llvm -fopenmp -fopenmp-is-target-device -debug-info-kind=standalone %s -o - | FileCheck %s +! XFAIL: * +function add(a, b) result(ret) + real ret + real a + real b +!$omp declare target + if (a > b) then + ret = a; + else + ret = b; + end if +end + +!CHECK: define float @add_({{.*}}){{.*}}!dbg ![[SP:[0-9]+]] { +!CHECK: #dbg_declare({{.*}}, ![[A:[0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), !{{.*}}) +!CHECK: #dbg_declare({{.*}}, ![[B:[0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), !{{.*}}) +!CHECK: #dbg_declare({{.*}}, ![[RET:[0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(float)), !{{.*}}) +!CHECK: } +!CHECK: ![[SP]] = {{.*}}!DISubprogram(name: "add"{{.*}}) +!CHECK: ![[A]] = !DILocalVariable(name: "a", arg: 1, scope: ![[SP]]{{.*}}) +!CHECK: ![[B]] = !DILocalVariable(name: "b", arg: 2, scope: ![[SP]]{{.*}}) +!CHECK: ![[RET]] = !DILocalVariable(name: "ret", scope: ![[SP]]{{.*}}) diff --git a/flang/test/Integration/amdgpu/debug-declare-target-var.f90 b/flang/test/Integration/amdgpu/debug-declare-target-var.f90 new file mode 100644 index 0000000000000..dca88f6c457bd --- /dev/null +++ b/flang/test/Integration/amdgpu/debug-declare-target-var.f90 @@ -0,0 +1,23 @@ +! RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-llvm -fopenmp -fopenmp-is-target-device -debug-info-kind=standalone %s -o - | FileCheck %s + +module helper + implicit none + real var_x + real var_y + !$omp declare target(var_x) + !$omp declare target(var_y) +end module helper + +subroutine init() + use helper + !$omp declare target + var_x = 3.14 + var_y = 0.25 +end + +! CHECK-DAG: @_QMhelperEvar_x = addrspace(1) {{.*}}!dbg ![[XE:[0-9]+]] +! CHECK-DAG: @_QMhelperEvar_y = addrspace(1) {{.*}}!dbg ![[YE:[0-9]+]] +! CHECK-DAG: ![[XE]] = !DIGlobalVariableExpression(var: ![[X:[0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(1)), DIOpDeref(ptr addrspace(1)))) +! CHECK-DAG: ![[YE]] = !DIGlobalVariableExpression(var: ![[Y:[0-9]+]], expr: !DIExpression(DIOpArg(0, ptr addrspace(1)), DIOpDeref(ptr addrspace(1)))) +! CHECK-DAG: ![[X]] = {{.*}}!DIGlobalVariable(name: "var_x"{{.*}}) +! CHECK-DAG: ![[Y]] = {{.*}}!DIGlobalVariable(name: "var_y"{{.*}}) diff --git a/flang/test/Integration/amdgpu/debug-target-var.f90 b/flang/test/Integration/amdgpu/debug-target-var.f90 new file mode 100644 index 0000000000000..8d00b967b0b75 --- /dev/null +++ b/flang/test/Integration/amdgpu/debug-target-var.f90 @@ -0,0 +1,30 @@ +! RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-llvm -fopenmp -fopenmp-is-target-device -debug-info-kind=standalone %s -o - | FileCheck %s + +subroutine fff(x, y) + implicit none + integer :: y(:) + integer :: x + +!$omp target map(tofrom: x) map(tofrom: y) + x = 5 + y = 10 +!$omp end target + +end subroutine fff + +! CHECK: define{{.*}}amdgpu_kernel void @[[FN:[0-9a-zA_Z_]+]](ptr %0, ptr %[[ARG1:[0-9]+]], ptr %[[ARG2:[0-9]+]]){{.*}}!dbg ![[SP:[0-9]+]] +! CHECK-DAG: store ptr %[[ARG1]], ptr %[[CAST1:[0-9]+]]{{.*}} +! CHECK-DAG: %[[CAST1]] = addrspacecast ptr addrspace(5) %[[AL1:[0-9]+]] +! CHECK-DAG: %[[AL1]] = alloca{{.*}} +! CHECK-DAG: store ptr %[[ARG2]], ptr %[[CAST2:[0-9]+]]{{.*}} +! CHECK-DAG: %[[CAST2]] = addrspacecast ptr addrspace(5) %[[AL2:[0-9]+]] +! CHECK-DAG: %[[AL2]] = alloca{{.*}} +! CHECK-DAG: #dbg_declare(ptr addrspace(5) %[[AL1]], ![[X:[0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), {{.*}}) +! CHECK-DAG: #dbg_declare(ptr addrspace(5) %[[AL2]], ![[Y:[0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), {{.*}}) +! CHECK: } + +! CHECK-DAG: ![[SP]] = {{.*}}!DISubprogram(name: "[[FN]]"{{.*}}) +! CHECK-DAG: ![[X]] = !DILocalVariable(name: "x", arg: 2, scope: ![[SP]]{{.*}}type: ![[INT:[0-9]+]]) +! CHECK-DAG: ![[INT]] = !DIBasicType(name: "integer", size: 32, encoding: DW_ATE_signed) +! CHECK-DAG: ![[Y]] = !DILocalVariable(name: "y", arg: 3, scope: ![[SP]]{{.*}}type: ![[ARR:[0-9]+]]) +! CHECK-DAG: ![[ARR]] = !DICompositeType(tag: DW_TAG_array_type, baseType: ![[INT]]{{.*}}) diff --git a/flang/test/Integration/no-malloc-private.f90 b/flang/test/Integration/no-malloc-private.f90 new file mode 100644 index 0000000000000..176af39c2de2a --- /dev/null +++ b/flang/test/Integration/no-malloc-private.f90 @@ -0,0 +1,26 @@ +! RUN: %flang_fc1 -emit-llvm -fopenmp -o - -x f95 %s | FileCheck %s +subroutine foo(state,ilast,jlast,vals) + real, intent(in) :: state(:,:) + integer, intent(in) :: ilast, jlast + real, intent( out) :: vals(:,:) + + real :: bar(4) + integer :: i,k,ll,s + + !$omp target teams distribute parallel do private(bar) + do i = 1, ilast + do j = 1, jlast + do s = 1, 4 + bar(s) = state(i,j+s) + enddo + vals(i,j) = -bar(1)/12 + 7*bar(2)/12 + 7*bar(3)/12 - bar(4)/12 + enddo + enddo + !$omp end target teams distribute parallel do +end subroutine foo + +! Ensure that we do not generate a call to malloc +!CHECK-LABEL: omp.private.init: +!CHECK-NOT: call {{.*}} @malloc +!CHECK: br label + diff --git a/flang/test/Lower/AMDGPU/allocate_deallocate_omp_declare_target.f90 b/flang/test/Lower/AMDGPU/allocate_deallocate_omp_declare_target.f90 new file mode 100644 index 0000000000000..6addd21d9a456 --- /dev/null +++ b/flang/test/Lower/AMDGPU/allocate_deallocate_omp_declare_target.f90 @@ -0,0 +1,24 @@ +! RUN: %flang -ffast-amd-memory-allocator -S -emit-llvm -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa --offload-arch=gfx90a -o - %s | FileCheck %s --check-prefix=CHECK-OMP +! RUN: %flang -ffast-amd-memory-allocator -S -emit-llvm -target amdgcn-- -o - %s | FileCheck %s --check-prefix=CHECK +!REQUIRES: AFAR +subroutine func_t_device() + !$omp declare target enter(func_t_device) device_type(nohost) + integer, ALLOCATABLE :: poly + +! CHECK-OMP-NOT: call void @_FortranAAMDAllocatableSetAllocIdx({{.*}}, i32 1) +! CHECK: call void @_FortranAAMDAllocatableSetAllocIdx({{.*}}, i32 1) +! CHECK-OMP: call i32 @_FortranAAllocatableAllocate +! CHECK: call i32 @_FortranAAllocatableAllocate + ALLOCATE(poly) + +! CHECK-OMP: call i32 @_FortranAAllocatableDeallocate +! CHECK: call i32 @_FortranAAllocatableDeallocate + DEALLOCATE(poly) +end subroutine func_t_device + +program main + implicit none + !$omp target + call func_t_device() + !$omp end target +end program diff --git a/flang/test/Lower/AMDGPU/allocate_deallocate_omp_declare_target_nested.f90 b/flang/test/Lower/AMDGPU/allocate_deallocate_omp_declare_target_nested.f90 new file mode 100644 index 0000000000000..fbd9ba1ac4a0a --- /dev/null +++ b/flang/test/Lower/AMDGPU/allocate_deallocate_omp_declare_target_nested.f90 @@ -0,0 +1,25 @@ +! RUN: %flang -ffast-amd-memory-allocator -S -emit-llvm -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa --offload-arch=gfx90a -o - %s | FileCheck %s --check-prefix=CHECK-OMP +! RUN: %flang -ffast-amd-memory-allocator -S -emit-llvm -target amdgcn-- -o - %s | FileCheck %s --check-prefix=CHECK +!REQUIRES: AFAR +subroutine func_t_device() + !$omp declare target enter(func_t_device) device_type(nohost) + integer, ALLOCATABLE :: poly + do j=1,10 +! CHECK-OMP-NOT: call void @_FortranAAMDAllocatableSetAllocIdx({{.*}}, i32 1) +! CHECK: call void @_FortranAAMDAllocatableSetAllocIdx({{.*}}, i32 1) +! CHECK-OMP: call i32 @_FortranAAllocatableAllocate +! CHECK: call i32 @_FortranAAllocatableAllocate + ALLOCATE(poly) + +! CHECK-OMP: call i32 @_FortranAAllocatableDeallocate +! CHECK: call i32 @_FortranAAllocatableDeallocate + DEALLOCATE(poly) + end do +end subroutine func_t_device + +program main + implicit none + !$omp target + call func_t_device() + !$omp end target +end program diff --git a/flang/test/Lower/AMDGPU/allocate_deallocate_omp_target.f90 b/flang/test/Lower/AMDGPU/allocate_deallocate_omp_target.f90 new file mode 100644 index 0000000000000..d4b8ad28120f0 --- /dev/null +++ b/flang/test/Lower/AMDGPU/allocate_deallocate_omp_target.f90 @@ -0,0 +1,24 @@ +! RUN: %flang -ffast-amd-memory-allocator -S -emit-llvm -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa --offload-arch=gfx90a -o - %s | FileCheck %s --check-prefix=CHECK-OMP +! RUN: %flang -ffast-amd-memory-allocator -S -emit-llvm -target amdgcn-- -o - %s | FileCheck %s --check-prefix=CHECK +!REQUIRES: AFAR +program main + implicit none + !$omp requires unified_shared_memory + REAL, DIMENSION(:), ALLOCATABLE :: poly + integer,parameter :: n = 10 + integer :: i,j + !$omp target teams distribute parallel do private(poly) + do j=1,n + +! CHECK-OMP-NOT: call void @_FortranAAMDAllocatableSetAllocIdx({{.*}}, i32 1) +! CHECK: call void @_FortranAAMDAllocatableSetAllocIdx({{.*}}, i32 1) +! CHECK-OMP: call i32 @_FortranAAllocatableAllocate +! CHECK: call i32 @_FortranAAllocatableAllocate + ALLOCATE(poly(1:3)) + poly = 2.0_8 +! CHECK-OMP: call i32 @_FortranAAllocatableDeallocate +! CHECK: call i32 @_FortranAAllocatableDeallocate + DEALLOCATE(poly) + enddo + !$omp end target teams distribute parallel do +end program diff --git a/flang/test/Lower/AMDGPU/allocate_deallocate_runtime_calls.f90 b/flang/test/Lower/AMDGPU/allocate_deallocate_runtime_calls.f90 new file mode 100644 index 0000000000000..a3bbd7631c909 --- /dev/null +++ b/flang/test/Lower/AMDGPU/allocate_deallocate_runtime_calls.f90 @@ -0,0 +1,28 @@ +! RUN: %flang -target amdgcn-- -mmlir -use-alloc-runtime -S -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK +! RUN: %flang -target amdgcn-- -S -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-NO-FLAG + +! Test to check if usage of flag -use-alloc-runtime results in runtime calls. + +subroutine allocate_deallocate() + real, allocatable :: x + + allocate(x) +! CHECK: call i32 @_FortranAAllocatableAllocate +! CHECK-NO-FLAG: call ptr @malloc + + deallocate(x) +! CHECK: call i32 @_FortranAAllocatableDeallocate +! CHECK-NO-FLAG: call void @free +end subroutine + +subroutine allocate_deallocate_ptr() + integer, pointer :: x + + allocate(x) +! CHECK: call i32 @_FortranAPointerAllocate +! CHECK-NO-FLAG: call i32 @_FortranAPointerAllocate + + deallocate(x) +! CHECK: call i32 @_FortranAPointerDeallocate +! CHECK-NO-FLAG: call i32 @_FortranAPointerDeallocate +end subroutine diff --git a/flang/test/Lower/AMDGPU/allocate_runtime_alloc_idx.f90 b/flang/test/Lower/AMDGPU/allocate_runtime_alloc_idx.f90 new file mode 100644 index 0000000000000..ce429e3f15b3d --- /dev/null +++ b/flang/test/Lower/AMDGPU/allocate_runtime_alloc_idx.f90 @@ -0,0 +1,19 @@ +! RUN: %flang -target amdgcn-- -ffast-amd-memory-allocator -S -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK +subroutine allocate_deallocate() + real, allocatable :: x +! CHECK: call void @_FortranAAMDAllocatableSetAllocIdx({{.*}}, i32 1) +! CHECK: call i32 @_FortranAAllocatableAllocate + allocate(x) + +! CHECK: call i32 @_FortranAAllocatableDeallocate + deallocate(x) +end subroutine + +subroutine test_allocatable_scalar(a) + real, save, allocatable :: x1, x2 + real :: a + +! CHECK: call void @_FortranAAMDAllocatableSetAllocIdx({{.*}}, i32 1) +! CHECK: call i32 @_FortranAAllocatableAllocateSource + allocate(x1, x2, source = a) +end diff --git a/flang/test/Lower/Intrinsics/atand.f90 b/flang/test/Lower/Intrinsics/atand.f90 index c27de4b5afbe7..c4374f3aa0c21 100644 --- a/flang/test/Lower/Intrinsics/atand.f90 +++ b/flang/test/Lower/Intrinsics/atand.f90 @@ -1,4 +1,5 @@ ! REQUIRES: flang-supports-f128-math +! REQUIRES: flang-atand-fix ! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s --check-prefixes="CHECK,CHECK-FAST" ! RUN: bbc --math-runtime=precise -emit-fir -hlfir=false %s -o - | FileCheck %s --check-prefixes="CHECK,CHECK-PRECISE" ! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir %s -o - | FileCheck %s --check-prefixes="CHECK,CHECK-FAST" diff --git a/flang/test/Lower/Intrinsics/ieee_is_normal.f90 b/flang/test/Lower/Intrinsics/ieee_is_normal.f90 index d55b2e3c08561..8982a16e82513 100644 --- a/flang/test/Lower/Intrinsics/ieee_is_normal.f90 +++ b/flang/test/Lower/Intrinsics/ieee_is_normal.f90 @@ -1,4 +1,5 @@ -! RUN: bbc -emit-fir %s -o - | FileCheck %s --check-prefixes=CHECK%if target=x86_64{{.*}} %{,CHECK-KIND10%}%if flang-supports-f128-math %{,CHECK-KIND16%} +! RUN: bbc -emit-fir %s -o - | FileCheck %s +! RUN: flang -fc1 -emit-fir %s -o - | FileCheck %s ! CHECK-LABEL: ieee_is_normal_f16 subroutine ieee_is_normal_f16(r) diff --git a/flang/test/Lower/Intrinsics/isnan.f90 b/flang/test/Lower/Intrinsics/isnan.f90 index 6535724b2ce3b..d1b6221c7ba40 100644 --- a/flang/test/Lower/Intrinsics/isnan.f90 +++ b/flang/test/Lower/Intrinsics/isnan.f90 @@ -1,4 +1,5 @@ -! RUN: bbc -emit-fir %s -o - | FileCheck %s --check-prefixes=CHECK%if target=x86_64{{.*}} %{,CHECK-KIND10%}%if flang-supports-f128-math %{,CHECK-KIND16%} +! RUN: bbc -emit-fir %s -o - | FileCheck %s +! RUN: flang -fc1 -emit-fir %s -o - | FileCheck %s ! CHECK-LABEL: isnan_f32 subroutine isnan_f32(r) diff --git a/flang/test/Lower/Intrinsics/modulo.f90 b/flang/test/Lower/Intrinsics/modulo.f90 index 37c4cd1a94ca2..b4ead32c687e8 100644 --- a/flang/test/Lower/Intrinsics/modulo.f90 +++ b/flang/test/Lower/Intrinsics/modulo.f90 @@ -1,5 +1,5 @@ ! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s -check-prefixes=HONORINF,ALL -! RUN: flang -fc1 -menable-no-infs -emit-fir -flang-deprecated-no-hlfir %s -o - | FileCheck %s -check-prefixes=CHECK,ALL,%if flang-supports-f128-math %{F128%} %else %{F64%} +! RUN: flang -fc1 -menable-no-infs -emit-fir -flang-deprecated-no-hlfir %s -o - | FileCheck %s -check-prefixes=CHECK,ALL ! ALL-LABEL: func @_QPmodulo_testr( ! ALL-SAME: %[[arg0:.*]]: !fir.ref{{.*}}, %[[arg1:.*]]: !fir.ref{{.*}}, %[[arg2:.*]]: !fir.ref{{.*}}) { diff --git a/flang/test/Lower/MIF/coarray-init.f90 b/flang/test/Lower/MIF/coarray-init.f90 index e3544736df284..4711435d560fd 100644 --- a/flang/test/Lower/MIF/coarray-init.f90 +++ b/flang/test/Lower/MIF/coarray-init.f90 @@ -7,5 +7,5 @@ program test_init ! ALL-LABEL: func.func @main ! ALL: fir.call @_FortranAProgramStart -! COARRAY: mif.init -> i32 -! NOCOARRAY-NOT: mif.init +! COARRAY: fir.call @_QQmain() fastmath : () -> () +! NOCOARRAY-NOT: fir.call @_QMprifPprif_init(%[[ARG:.*]]) fastmath : (!fir.ref) -> () diff --git a/flang/test/Lower/OpenACC/acc-enter-data.f90 b/flang/test/Lower/OpenACC/acc-enter-data.f90 index 2718c96a563fb..2d0059dd98b2b 100644 --- a/flang/test/Lower/OpenACC/acc-enter-data.f90 +++ b/flang/test/Lower/OpenACC/acc-enter-data.f90 @@ -1,5 +1,5 @@ ! This test checks lowering of OpenACC enter data directive. - +! XFAIL: * ! RUN: bbc -fopenacc -emit-hlfir %s -o - | FileCheck %s module mod1 @@ -651,11 +651,12 @@ subroutine acc_enter_data_single_array_element() !CHECK: %[[VAL_42:.*]] = arith.constant 1 : index !CHECK: %[[VAL_43:.*]] = arith.constant 1 : index !CHECK: %[[VAL_44:.*]] = arith.subi %[[VAL_43]], %[[VAL_38]]#0 : index -!CHECK: %[[VAL_45:.*]] = acc.bounds lowerbound(%[[VAL_44]] : index) upperbound(%[[VAL_44]] : index) extent(%[[VAL_42]] : index) stride(%[[VAL_42]] : index) startIdx(%[[VAL_38]]#0 : index) -!CHECK: %[[VAL_46:.*]] = arith.constant 2 : index -!CHECK: %[[VAL_47:.*]] = arith.subi %[[VAL_46]], %[[VAL_40]]#0 : index -!CHECK: %[[VAL_48:.*]] = acc.bounds lowerbound(%[[VAL_47]] : index) upperbound(%[[VAL_47]] : index) extent(%[[VAL_42]] : index) stride(%[[VAL_42]] : index) startIdx(%[[VAL_40]]#0 : index) -!CHECK: %[[CREATE:.*]] = acc.create varPtr(%[[VAL_41]] : !fir.heap>) bounds(%[[VAL_45]], %[[VAL_48]]) -> !fir.heap> {name = "e(2_8)%a(1,2)", structured = false} +!CHECK: %[[VAL_45:.*]] = arith.muli %[[VAL_38]]#1, %[[VAL_42]] : index +!CHECK: %[[VAL_46:.*]] = acc.bounds lowerbound(%[[VAL_44]] : index) upperbound(%[[VAL_44]] : index) extent(%[[VAL_38]]#1 : index) stride(%[[VAL_42]] : index) startIdx(%[[VAL_38]]#0 : index) +!CHECK: %[[VAL_47:.*]] = arith.constant 2 : index +!CHECK: %[[VAL_48:.*]] = arith.subi %[[VAL_47]], %[[VAL_40]]#0 : index +!CHECK: %[[VAL_49:.*]] = acc.bounds lowerbound(%[[VAL_48]] : index) upperbound(%[[VAL_48]] : index) extent(%[[VAL_40]]#1 : index) stride(%[[VAL_45]] : index) startIdx(%[[VAL_40]]#0 : index) +!CHECK: %[[CREATE:.*]] = acc.create varPtr(%[[VAL_41]] : !fir.heap>) bounds(%[[VAL_46]], %[[VAL_49]]) -> !fir.heap> {name = "e(2_8)%a(1,2)", structured = false} !CHECK: acc.enter_data dataOperands(%[[CREATE]] : !fir.heap>) end subroutine diff --git a/flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90 b/flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90 index 272f34fc0fd1a..52fe7cf82f48f 100644 --- a/flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90 +++ b/flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90 @@ -1,22 +1,9 @@ ! Tests delayed privatization for `targets ... private(..)` for allocatables. ! RUN: %flang_fc1 -emit-hlfir -fopenmp -mmlir --enable-delayed-privatization-staging \ -! RUN: -o - %s 2>&1 | FileCheck %s --check-prefix=CPU - +! RUN: -o - %s 2>&1 | FileCheck %s ! RUN: bbc -emit-hlfir -fopenmp --enable-delayed-privatization-staging -o - %s 2>&1 \ -! RUN: | FileCheck %s --check-prefix=CPU - -! RUN: %if amdgpu-registered-target %{ \ -! RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-hlfir \ -! RUN: -fopenmp -fopenmp-is-target-device \ -! RUN: -mmlir --enable-delayed-privatization-staging \ -! RUN: -o - %s 2>&1 | \ -! RUN: FileCheck %s --check-prefix=GPU \ -! RUN: %} - -! RUN: bbc -emit-hlfir -fopenmp --enable-delayed-privatization-staging \ -! RUN: -fopenmp-is-target-device -fopenmp-is-gpu -o - %s 2>&1 \ -! RUN: | FileCheck %s --check-prefix=GPU +! RUN: | FileCheck %s subroutine target_allocatable implicit none @@ -27,65 +14,53 @@ subroutine target_allocatable !$omp end target end subroutine target_allocatable -! CPU-LABEL: omp.private {type = private} -! CPU-SAME: @[[VAR_PRIVATIZER_SYM:.*]] : -! CPU-SAME: [[DESC_TYPE:!fir.box>]] init { -! CPU: ^bb0(%[[PRIV_ARG:.*]]: [[TYPE:!fir.ref>>]], %[[PRIV_ALLOC:.*]]: [[TYPE]]): - -! CPU-NEXT: %[[PRIV_ARG_VAL:.*]] = fir.load %[[PRIV_ARG]] : [[TYPE]] -! CPU-NEXT: %[[PRIV_ARG_BOX:.*]] = fir.box_addr %[[PRIV_ARG_VAL]] : ([[DESC_TYPE]]) -> !fir.heap -! CPU-NEXT: %[[PRIV_ARG_ADDR:.*]] = fir.convert %[[PRIV_ARG_BOX]] : (!fir.heap) -> i64 -! CPU-NEXT: %[[C0:.*]] = arith.constant 0 : i64 -! CPU-NEXT: %[[ALLOC_COND:.*]] = arith.cmpi eq, %[[PRIV_ARG_ADDR]], %[[C0]] : i64 +! CHECK-LABEL: omp.private {type = private} +! CHECK-SAME: @[[VAR_PRIVATIZER_SYM:.*]] : +! CHECK-SAME: [[DESC_TYPE:!fir.box>]] init { +! CHECK: ^bb0(%[[PRIV_ARG:.*]]: [[TYPE:!fir.ref>>]], %[[PRIV_ALLOC:.*]]: [[TYPE]]): -! CPU-NEXT: fir.if %[[ALLOC_COND]] { -! CPU-NEXT: %[[ZERO_BOX:.*]] = fir.embox %[[PRIV_ARG_BOX]] : (!fir.heap) -> [[DESC_TYPE]] -! CPU-NEXT: fir.store %[[ZERO_BOX]] to %[[PRIV_ALLOC]] : [[TYPE]] -! CPU-NEXT: } else { -! CPU-NEXT: %[[PRIV_ALLOCMEM:.*]] = fir.allocmem i32 -! CPU-NEXT: %[[PRIV_ALLOCMEM_BOX:.*]] = fir.embox %[[PRIV_ALLOCMEM]] : (!fir.heap) -> [[DESC_TYPE]] -! CPU-NEXT: fir.store %[[PRIV_ALLOCMEM_BOX]] to %[[PRIV_ALLOC]] : [[TYPE]] -! CPU-NEXT: } +! CHECK-NEXT: %[[PRIV_ARG_VAL:.*]] = fir.load %[[PRIV_ARG]] : [[TYPE]] +! CHECK-NEXT: %[[PRIV_ARG_BOX:.*]] = fir.box_addr %[[PRIV_ARG_VAL]] : ([[DESC_TYPE]]) -> !fir.heap +! CHECK-NEXT: %[[PRIV_ARG_ADDR:.*]] = fir.convert %[[PRIV_ARG_BOX]] : (!fir.heap) -> i64 +! CHECK-NEXT: %[[C0:.*]] = arith.constant 0 : i64 +! CHECK-NEXT: %[[ALLOC_COND:.*]] = arith.cmpi eq, %[[PRIV_ARG_ADDR]], %[[C0]] : i64 -! CPU-NEXT: omp.yield(%[[PRIV_ALLOC]] : [[TYPE]]) +! CHECK-NEXT: fir.if %[[ALLOC_COND]] { +! CHECK-NEXT: %[[ZERO_BOX:.*]] = fir.embox %[[PRIV_ARG_BOX]] : (!fir.heap) -> [[DESC_TYPE]] +! CHECK-NEXT: fir.store %[[ZERO_BOX]] to %[[PRIV_ALLOC]] : [[TYPE]] +! CHECK-NEXT: } else { +! CHECK-NEXT: %[[PRIV_ALLOCMEM:.*]] = fir.allocmem i32 +! CHECK-NEXT: %[[PRIV_ALLOCMEM_BOX:.*]] = fir.embox %[[PRIV_ALLOCMEM]] : (!fir.heap) -> [[DESC_TYPE]] +! CHECK-NEXT: fir.store %[[PRIV_ALLOCMEM_BOX]] to %[[PRIV_ALLOC]] : [[TYPE]] +! CHECK-NEXT: } -! CPU-NEXT: } dealloc { -! CPU-NEXT: ^bb0(%[[PRIV_ARG:.*]]: [[TYPE]]): +! CHECK-NEXT: omp.yield(%[[PRIV_ALLOC]] : [[TYPE]]) -! CPU-NEXT: %[[PRIV_VAL:.*]] = fir.load %[[PRIV_ARG]] -! CPU-NEXT: %[[PRIV_ADDR:.*]] = fir.box_addr %[[PRIV_VAL]] -! CPU-NEXT: %[[PRIV_ADDR_I64:.*]] = fir.convert %[[PRIV_ADDR]] -! CPU-NEXT: %[[C0:.*]] = arith.constant 0 : i64 -! CPU-NEXT: %[[PRIV_NULL_COND:.*]] = arith.cmpi ne, %[[PRIV_ADDR_I64]], %[[C0]] : i64 +! CHECK-NEXT: } dealloc { +! CHECK-NEXT: ^bb0(%[[PRIV_ARG:.*]]: [[TYPE]]): -! CPU-NEXT: fir.if %[[PRIV_NULL_COND]] { -! CPU-NEXT: fir.freemem %[[PRIV_ADDR]] -! CPU-NEXT: } +! CHECK-NEXT: %[[PRIV_VAL:.*]] = fir.load %[[PRIV_ARG]] +! CHECK-NEXT: %[[PRIV_ADDR:.*]] = fir.box_addr %[[PRIV_VAL]] +! CHECK-NEXT: %[[PRIV_ADDR_I64:.*]] = fir.convert %[[PRIV_ADDR]] +! CHECK-NEXT: %[[C0:.*]] = arith.constant 0 : i64 +! CHECK-NEXT: %[[PRIV_NULL_COND:.*]] = arith.cmpi ne, %[[PRIV_ADDR_I64]], %[[C0]] : i64 -! CPU-NEXT: omp.yield -! CPU-NEXT: } +! CHECK-NEXT: fir.if %[[PRIV_NULL_COND]] { +! CHECK-NEXT: fir.freemem %[[PRIV_ADDR]] +! CHECK-NEXT: } +! CHECK-NEXT: omp.yield +! CHECK-NEXT: } -! CPU-LABEL: func.func @_QPtarget_allocatable() { -! CPU: %[[VAR_ALLOC:.*]] = fir.alloca [[DESC_TYPE]] -! CPU-SAME: {bindc_name = "alloc_var", {{.*}}} -! CPU: %[[VAR_DECL:.*]]:2 = hlfir.declare %[[VAR_ALLOC]] -! CPU: %[[BASE_ADDR:.*]] = fir.box_offset %[[VAR_DECL]]#0 base_addr : (!fir.ref>>) -> [[MEMBER_TYPE:.*]] -! CPU: %[[MEMBER:.*]] = omp.map.info var_ptr(%[[VAR_DECL]]#0 : [[TYPE]], i32) map_clauses(to) capture(ByRef) var_ptr_ptr(%[[BASE_ADDR]] : [[MEMBER_TYPE:.*]]) -> {{.*}} -! CPU: %[[MAP_VAR:.*]] = omp.map.info var_ptr(%[[VAR_DECL]]#0 : [[TYPE]], [[DESC_TYPE]]) map_clauses(to) capture(ByRef) members(%[[MEMBER]] : [0] : !fir.llvm_ptr>) -> !fir.ref>> +! CHECK-LABEL: func.func @_QPtarget_allocatable() { -! CPU: omp.target map_entries(%[[MAP_VAR]] -> %arg0, %[[MEMBER]] -> %arg1 : [[TYPE]], [[MEMBER_TYPE]]) private( -! CPU-SAME: @[[VAR_PRIVATIZER_SYM]] %[[VAR_DECL]]#0 -> %{{.*}} [map_idx=0] : [[TYPE]]) { +! CHECK: %[[VAR_ALLOC:.*]] = fir.alloca [[DESC_TYPE]] +! CHECK-SAME: {bindc_name = "alloc_var", {{.*}}} +! CHECK: %[[VAR_DECL:.*]]:2 = hlfir.declare %[[VAR_ALLOC]] +! CHECK: %[[BASE_ADDR:.*]] = fir.box_offset %[[VAR_DECL]]#0 base_addr : (!fir.ref>>) -> [[MEMBER_TYPE:.*]] +! CHECK: %[[MEMBER:.*]] = omp.map.info var_ptr(%[[VAR_DECL]]#0 : [[TYPE]], i32) map_clauses(to) capture(ByRef) var_ptr_ptr(%[[BASE_ADDR]] : [[MEMBER_TYPE:.*]]) -> {{.*}} +! CHECK: %[[MAP_VAR:.*]] = omp.map.info var_ptr(%[[VAR_DECL]]#0 : [[TYPE]], [[DESC_TYPE]]) map_clauses(always, descriptor, to) capture(ByRef) members(%[[MEMBER]] : [0] : !fir.llvm_ptr>) -> !fir.ref>> -! GPU-LABEL: omp.private {type = private} {{.*}} init { -! GPU: fir.if %{{.*}} { -! GPU-NEXT: %[[ZERO_BOX:.*]] = fir.embox %{{.*}} -! GPU-NEXT: fir.store %[[ZERO_BOX]] to %{{.*}} -! GPU-NEXT: } else { -! GPU-NOT: fir.allocmem i32 -! GPU-NEXT: %[[PRIV_ALLOC:.*]] = fir.alloca i32 -! GPU-NEXT: %[[PRIV_ALLOC_BOX:.*]] = fir.embox %[[PRIV_ALLOC]] -! GPU-NEXT: fir.store %[[PRIV_ALLOC_BOX]] to %{{.*}} -! GPU-NEXT: } -! GPU-NEXT: omp.yield(%{{.*}}) +! CHECK: omp.target map_entries(%[[MAP_VAR]] -> %arg0, %[[MEMBER]] -> %arg1 : [[TYPE]], [[MEMBER_TYPE]]) private( +! CHECK-SAME: @[[VAR_PRIVATIZER_SYM]] %[[VAR_DECL]]#0 -> %{{.*}} [map_idx=0] : [[TYPE]]) { diff --git a/flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-private-implicit-scalar-map.f90 b/flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-private-implicit-scalar-map.f90 index 126f341a58192..8e76a1c641049 100644 --- a/flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-private-implicit-scalar-map.f90 +++ b/flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-private-implicit-scalar-map.f90 @@ -28,7 +28,7 @@ program test_default_implicit_firstprivate !CHECK: %[[VAL_9:.*]] = omp.map.info var_ptr(%[[VAL_4]] : !fir.ref, i32) map_clauses(implicit) capture(ByCopy) -> !fir.ref {name = "k"} !CHECK: %[[VAL_10:.*]] = fir.box_offset %[[VAL_0]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> !CHECK: %[[VAL_11:.*]] = omp.map.info var_ptr(%[[VAL_0]] : !fir.ref>>>, i32) map_clauses(implicit, tofrom) capture(ByRef) var_ptr_ptr(%[[VAL_10]] : !fir.llvm_ptr>>) bounds({{.*}}) -> !fir.llvm_ptr>> {name = ""} -!CHECK: %[[VAL_12:.*]] = omp.map.info var_ptr(%[[VAL_0]] : !fir.ref>>>, !fir.box>>) map_clauses(implicit, to) capture(ByRef) members(%[[VAL_11]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "allocarr"} +!CHECK: %[[VAL_12:.*]] = omp.map.info var_ptr(%[[VAL_0]] : !fir.ref>>>, !fir.box>>) map_clauses(always, implicit, descriptor, to) capture(ByRef) members(%[[VAL_11]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "allocarr"} !CHECK: %[[VAL_13:.*]] = omp.map.info var_ptr(%[[VAL_1]] : !fir.ref>, !fir.array<10x10x10xi32>) map_clauses(implicit, tofrom) capture(ByRef) bounds({{.*}}) -> !fir.ref> {name = "arr"} !CHECK: %[[VAL_14:.*]] = omp.map.info var_ptr(%[[VAL_6]] : !fir.ref, i32) map_clauses(to) capture(ByCopy) -> !fir.ref !CHECK: %[[VAL_15:.*]] = omp.map.info var_ptr(%[[VAL_5]] : !fir.ref, i32) map_clauses(to) capture(ByCopy) -> !fir.ref diff --git a/flang/test/Lower/OpenMP/FIR/mismatched-bound-types.f90 b/flang/test/Lower/OpenMP/FIR/mismatched-bound-types.f90 new file mode 100644 index 0000000000000..8b24b34cb55b6 --- /dev/null +++ b/flang/test/Lower/OpenMP/FIR/mismatched-bound-types.f90 @@ -0,0 +1,35 @@ +! RUN: %flang_fc1 -fopenmp -emit-fir %s -o - | FileCheck %s + +! Check that this testcase is lowered to FIR successfully. + +! CHECK: %[[ONE:.*]] = arith.constant 1 : i32 +! CHECK: %[[DECL_N:.*]] = fir.declare %{{.*}} {uniq_name = "_QMtestEn"} : (!fir.ref) -> !fir.ref +! CHECK: %[[HOST_N:.*]] = fir.load %[[DECL_N]] : !fir.ref +! CHECK: %[[HOST_LB:.*]] = fir.convert %[[ONE]] : (i32) -> i64 +! CHECK: %[[HOST_STEP:.*]] = fir.convert %[[ONE]] : (i32) -> i64 +! CHECK: omp.target +! CHECK-SAME: host_eval(%[[HOST_LB]] -> %[[LB:[[:alnum:]]+]], %[[HOST_N]] -> %[[UB:[[:alnum:]]+]], %[[HOST_STEP]] -> %[[STEP:[[:alnum:]]+]] : i64, i64, i64) +! CHECK: omp.teams +! CHECK: omp.parallel +! CHECK: omp.distribute +! CHECK-NEXT: omp.wsloop +! CHECK-NEXT: omp.loop_nest ({{.*}}) : i64 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) + +module Test + use, intrinsic :: ISO_Fortran_env, only: REAL64,INT64 + implicit none + integer(kind=INT64) :: N + real(kind=REAL64), allocatable :: A(:) + + contains + subroutine init_arrays(initA) + implicit none + real(kind=REAL64), intent(in) :: initA + integer(kind=INT64) :: i + !$omp target teams distribute parallel do + do i = 1, N + A(i) = initA + end do + end subroutine init_arrays + +end module Test diff --git a/flang/test/Lower/OpenMP/Todo/firstprivate-target.f90 b/flang/test/Lower/OpenMP/Todo/firstprivate-target.f90 deleted file mode 100644 index 2c6ce2f949e44..0000000000000 --- a/flang/test/Lower/OpenMP/Todo/firstprivate-target.f90 +++ /dev/null @@ -1,9 +0,0 @@ -! RUN: %not_todo_cmd bbc -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s -! RUN: %not_todo_cmd %flang_fc1 -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s - -integer :: i -! CHECK: not yet implemented: Unhandled clause FIRSTPRIVATE in TARGET construct -!$omp target firstprivate(i) nowait -!$omp end target - -end program diff --git a/flang/test/Lower/OpenMP/Todo/omp-declare-reduction-initsub.f90 b/flang/test/Lower/OpenMP/Todo/omp-declare-reduction-initsub.f90 index 30630465490b2..13623a5846b6a 100644 --- a/flang/test/Lower/OpenMP/Todo/omp-declare-reduction-initsub.f90 +++ b/flang/test/Lower/OpenMP/Todo/omp-declare-reduction-initsub.f90 @@ -2,6 +2,7 @@ ! via a subroutine. This functionality is currently not implemented. ! RUN: not flang -fc1 -emit-fir -fopenmp %s 2>&1 | FileCheck %s +! REQUIRES: stability !CHECK: not yet implemented: OpenMPDeclareReductionConstruct subroutine initme(x,n) diff --git a/flang/test/Lower/OpenMP/allocatable-array-bounds.f90 b/flang/test/Lower/OpenMP/allocatable-array-bounds.f90 index 96d779c763d18..9ef833fe5e518 100644 --- a/flang/test/Lower/OpenMP/allocatable-array-bounds.f90 +++ b/flang/test/Lower/OpenMP/allocatable-array-bounds.f90 @@ -23,8 +23,8 @@ !HOST: %[[BOX_3:.*]]:3 = fir.box_dims %[[LOAD_3]], %[[CONSTANT_3]] : (!fir.box>>, index) -> (index, index, index) !HOST: %[[BOUNDS_1:.*]] = omp.map.bounds lower_bound(%[[LB_1]] : index) upper_bound(%[[UB_1]] : index) extent(%[[BOX_3]]#1 : index) stride(%[[BOX_2]]#2 : index) start_idx(%[[BOX_1]]#0 : index) {stride_in_bytes = true} !HOST: %[[VAR_PTR_PTR:.*]] = fir.box_offset %[[DECLARE_1]]#1 base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -!HOST: %[[MAP_INFO_MEMBER:.*]] = omp.map.info var_ptr(%[[DECLARE_1]]#1 : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAR_PTR_PTR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS_1]]) -> !fir.llvm_ptr>> {name = ""} -!HOST: %[[MAP_INFO_1:.*]] = omp.map.info var_ptr(%[[DECLARE_1]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) members(%[[MAP_INFO_MEMBER]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "sp_read(2:5)"} +!HOST: %[[MAP_INFO_MEMBER:.*]] = omp.map.info var_ptr(%[[DECLARE_1]]#1 : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAR_PTR_PTR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS_1]]) -> !fir.llvm_ptr>> {name = ""} +!HOST: %[[MAP_INFO_1:.*]] = omp.map.info var_ptr(%[[DECLARE_1]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[MAP_INFO_MEMBER]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "sp_read(2:5)"} !HOST: %[[LOAD_3:.*]] = fir.load %[[DECLARE_2]]#0 : !fir.ref>>> !HOST: %[[LOAD_4:.*]] = fir.load %[[DECLARE_2]]#0 : !fir.ref>>> @@ -41,8 +41,8 @@ !HOST: %[[BOX_5:.*]]:3 = fir.box_dims %[[LOAD_5]], %[[CONSTANT_5]] : (!fir.box>>, index) -> (index, index, index) !HOST: %[[BOUNDS_2:.*]] = omp.map.bounds lower_bound(%[[LB_2]] : index) upper_bound(%[[UB_2]] : index) extent(%[[BOX_5]]#1 : index) stride(%[[BOX_4]]#2 : index) start_idx(%[[BOX_3]]#0 : index) {stride_in_bytes = true} !HOST: %[[VAR_PTR_PTR:.*]] = fir.box_offset %[[DECLARE_2]]#1 base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -!HOST: %[[MAP_INFO_MEMBER:.*]] = omp.map.info var_ptr(%[[DECLARE_2]]#1 : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAR_PTR_PTR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS_2]]) -> !fir.llvm_ptr>> {name = ""} -!HOST: %[[MAP_INFO_2:.*]] = omp.map.info var_ptr(%[[DECLARE_2]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) members(%[[MAP_INFO_MEMBER]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "sp_write(2:5)"} +!HOST: %[[MAP_INFO_MEMBER:.*]] = omp.map.info var_ptr(%[[DECLARE_2]]#1 : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAR_PTR_PTR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS_2]]) -> !fir.llvm_ptr>> {name = ""} +!HOST: %[[MAP_INFO_2:.*]] = omp.map.info var_ptr(%[[DECLARE_2]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[MAP_INFO_MEMBER]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "sp_write(2:5)"} subroutine read_write_section() integer, allocatable :: sp_read(:) @@ -80,8 +80,8 @@ module assumed_allocatable_array_routines !HOST: %[[BOX_3:.*]]:3 = fir.box_dims %[[LOAD_3]], %[[CONSTANT_3]] : (!fir.box>>, index) -> (index, index, index) !HOST: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%[[LB]] : index) upper_bound(%[[UB]] : index) extent(%[[BOX_3]]#1 : index) stride(%[[BOX_2]]#2 : index) start_idx(%[[BOX_1]]#0 : index) {stride_in_bytes = true} !HOST: %[[VAR_PTR_PTR:.*]] = fir.box_offset %[[DECLARE]]#1 base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -!HOST: %[[MAP_INFO_MEMBER:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAR_PTR_PTR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {name = ""} -!HOST: %[[MAP_INFO:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) members(%[[MAP_INFO_MEMBER]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "arr_read_write(2:5)"} +!HOST: %[[MAP_INFO_MEMBER:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAR_PTR_PTR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {name = ""} +!HOST: %[[MAP_INFO:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[MAP_INFO_MEMBER]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "arr_read_write(2:5)"} subroutine assumed_shape_array(arr_read_write) integer, allocatable, intent(inout) :: arr_read_write(:) diff --git a/flang/test/Lower/OpenMP/allocatable-map.f90 b/flang/test/Lower/OpenMP/allocatable-map.f90 index ee1c621ad860b..cc6c4baf44b96 100644 --- a/flang/test/Lower/OpenMP/allocatable-map.f90 +++ b/flang/test/Lower/OpenMP/allocatable-map.f90 @@ -2,8 +2,8 @@ !HLFIRDIALECT: %[[POINTER:.*]]:2 = hlfir.declare %{{.*}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFpointer_routineEpoint"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) !HLFIRDIALECT: %[[BOX_OFF:.*]] = fir.box_offset %[[POINTER]]#1 base_addr : (!fir.ref>>) -> !fir.llvm_ptr> -!HLFIRDIALECT: %[[POINTER_MAP_MEMBER:.*]] = omp.map.info var_ptr(%[[POINTER]]#1 : !fir.ref>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[BOX_OFF]] : !fir.llvm_ptr>) -> !fir.llvm_ptr> {name = ""} -!HLFIRDIALECT: %[[POINTER_MAP:.*]] = omp.map.info var_ptr(%[[POINTER]]#1 : !fir.ref>>, !fir.box>) map_clauses(to) capture(ByRef) members(%[[POINTER_MAP_MEMBER]] : [0] : !fir.llvm_ptr>) -> !fir.ref>> {name = "point"} +!HLFIRDIALECT: %[[POINTER_MAP_MEMBER:.*]] = omp.map.info var_ptr(%[[POINTER]]#1 : !fir.ref>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[BOX_OFF]] : !fir.llvm_ptr>) -> !fir.llvm_ptr> {name = ""} +!HLFIRDIALECT: %[[POINTER_MAP:.*]] = omp.map.info var_ptr(%[[POINTER]]#1 : !fir.ref>>, !fir.box>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[POINTER_MAP_MEMBER]] : [0] : !fir.llvm_ptr>) -> !fir.ref>> {name = "point"} !HLFIRDIALECT: omp.target map_entries(%[[POINTER_MAP]] -> {{.*}}, %[[POINTER_MAP_MEMBER]] -> {{.*}} : !fir.ref>>, !fir.llvm_ptr>) { subroutine pointer_routine() integer, pointer :: point diff --git a/flang/test/Lower/OpenMP/array-bounds.f90 b/flang/test/Lower/OpenMP/array-bounds.f90 index 8f98d671486ae..8f3197fc8e762 100644 --- a/flang/test/Lower/OpenMP/array-bounds.f90 +++ b/flang/test/Lower/OpenMP/array-bounds.f90 @@ -1,6 +1,5 @@ !RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes HOST - !HOST-LABEL: func.func @_QPread_write_section() { !HOST: %{{.*}} = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFread_write_sectionEi"} !HOST: %[[READ:.*]] = fir.address_of(@_QFread_write_sectionEsp_read) : !fir.ref> @@ -50,9 +49,9 @@ module assumed_array_routines !HOST: %[[C0_1:.*]] = arith.constant 0 : index !HOST: %[[DIMS1:.*]]:3 = fir.box_dims %[[ARG0_DECL]]#1, %[[C0_1]] : (!fir.box>, index) -> (index, index, index) !HOST: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%[[C3]] : index) upper_bound(%[[C4]] : index) extent(%[[DIMS1]]#1 : index) stride(%[[DIMS0]]#2 : index) start_idx(%[[C0]] : index) {stride_in_bytes = true} -!HOST: %[[VAR_PTR_PTR:.*]] = fir.box_offset %[[INTERMEDIATE_ALLOCA]] base_addr : (!fir.ref>>) -> !fir.llvm_ptr>> -!HOST: %[[MAP_INFO_MEMBER:.*]] = omp.map.info var_ptr(%[[INTERMEDIATE_ALLOCA]] : !fir.ref>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAR_PTR_PTR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {name = ""} -!HOST: %[[MAP:.*]] = omp.map.info var_ptr(%[[INTERMEDIATE_ALLOCA]] : !fir.ref>>, !fir.box>) map_clauses(to) capture(ByRef) members(%[[MAP_INFO_MEMBER]] : [0] : !fir.llvm_ptr>>) -> !fir.ref> {name = "arr_read_write(2:5)"} +!HOST: %[[VAR_PTR_PTR:.*]] = fir.box_offset %0 base_addr : (!fir.ref>>) -> !fir.llvm_ptr>> +!HOST: %[[MAP_INFO_MEMBER:.*]] = omp.map.info var_ptr(%[[INTERMEDIATE_ALLOCA]] : !fir.ref>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAR_PTR_PTR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {name = ""} +!HOST: %[[MAP:.*]] = omp.map.info var_ptr(%[[INTERMEDIATE_ALLOCA]] : !fir.ref>>, !fir.box>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[MAP_INFO_MEMBER]] : [0] : !fir.llvm_ptr>>) -> !fir.ref> {name = "arr_read_write(2:5)"} !HOST: omp.target map_entries(%[[MAP]] -> %{{.*}}, {{.*}} -> {{.*}}, %[[MAP_INFO_MEMBER]] -> %{{.*}} : !fir.ref>, !fir.ref, !fir.llvm_ptr>>) { subroutine assumed_shape_array(arr_read_write) integer, intent(inout) :: arr_read_write(:) @@ -65,13 +64,15 @@ subroutine assumed_shape_array(arr_read_write) end subroutine assumed_shape_array + + !HOST-LABEL: func.func @_QMassumed_array_routinesPassumed_size_array( !HOST-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "arr_read_write"}) { !HOST: %[[ARG0_SHAPE:.*]] = fir.shape %{{.*}} : (index) -> !fir.shape<1> !HOST: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]](%[[ARG0_SHAPE]]) dummy_scope %{{[0-9]+}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QMassumed_array_routinesFassumed_size_arrayEarr_read_write"} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) !HOST: %[[ALLOCA:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QMassumed_array_routinesFassumed_size_arrayEi"} !HOST: %[[DIMS0:.*]]:3 = fir.box_dims %[[ARG0_DECL]]#0, %c0{{.*}} : (!fir.box>, index) -> (index, index, index) -!HOST: %[[C4_1:.*]] = arith.subi %c4, %c1{{.*}} : index +!HOST: %[[C4_1:.*]] = arith.subi %c4{{.*}}, %c1{{.*}} : index !HOST: %[[EXT:.*]] = arith.addi %[[C4_1]], %c1{{.*}} : index !HOST: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%c1{{.*}} : index) upper_bound(%c4{{.*}} : index) extent(%[[EXT]] : index) stride(%[[DIMS0]]#2 : index) start_idx(%c1{{.*}} : index) {stride_in_bytes = true} !HOST: %[[MAP:.*]] = omp.map.info var_ptr(%[[ARG0_DECL]]#1 : !fir.ref>, i32) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "arr_read_write(2:5)"} diff --git a/flang/test/Lower/OpenMP/atomic-implicit-cast.f90 b/flang/test/Lower/OpenMP/atomic-implicit-cast.f90 index 5e00235b85e74..dab18c43d2206 100644 --- a/flang/test/Lower/OpenMP/atomic-implicit-cast.f90 +++ b/flang/test/Lower/OpenMP/atomic-implicit-cast.f90 @@ -1,5 +1,4 @@ ! RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s - ! CHECK: func.func @_QPatomic_implicit_cast_read() { subroutine atomic_implicit_cast_read ! CHECK: %[[ALLOCA7:.*]] = fir.alloca complex @@ -27,21 +26,21 @@ subroutine atomic_implicit_cast_read complex :: w complex(8) :: m -! CHECK: omp.atomic.read %[[ALLOCA0:.*]] = %[[Y_DECL]]#0 : !fir.ref, !fir.ref, f32 +! CHECK: omp.atomic.read %[[ALLOCA0:.*]] = %[[Y_DECL]]#0 memory_order(relaxed) : !fir.ref, !fir.ref, f32 ! CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA0]] : !fir.ref ! CHECK: %[[CVT:.*]] = fir.convert %[[LOAD]] : (f32) -> i32 ! CHECK: fir.store %[[CVT]] to %[[X_DECL]]#0 : !fir.ref !$omp atomic read x = y -! CHECK: omp.atomic.read %[[ALLOCA1:.*]] = %[[X_DECL]]#0 : !fir.ref, !fir.ref, i32 +! CHECK: omp.atomic.read %[[ALLOCA1:.*]] = %[[X_DECL]]#0 memory_order(relaxed) : !fir.ref, !fir.ref, i32 ! CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA1]] : !fir.ref ! CHECK: %[[CVT:.*]] = fir.convert %[[LOAD]] : (i32) -> f64 ! CHECK: fir.store %[[CVT]] to %[[Z_DECL]]#0 : !fir.ref !$omp atomic read z = x -! CHECK: omp.atomic.read %[[ALLOCA2:.*]] = %[[W_DECL]]#0 : !fir.ref>, !fir.ref>, complex +! CHECK: omp.atomic.read %[[ALLOCA2:.*]] = %[[W_DECL]]#0 memory_order(relaxed) : !fir.ref>, !fir.ref>, complex ! CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA2]] : !fir.ref> ! CHECK: %[[EXTRACT:.*]] = fir.extract_value %[[LOAD]], [0 : index] : (complex) -> f32 ! CHECK: %[[CVT:.*]] = fir.convert %[[EXTRACT]] : (f32) -> i32 @@ -49,7 +48,7 @@ subroutine atomic_implicit_cast_read !$omp atomic read x = w -! CHECK: omp.atomic.read %[[ALLOCA3:.*]] = %[[W_DECL]]#0 : !fir.ref>, !fir.ref>, complex +! CHECK: omp.atomic.read %[[ALLOCA3:.*]] = %[[W_DECL]]#0 memory_order(relaxed) : !fir.ref>, !fir.ref>, complex ! CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA3]] : !fir.ref> ! CHECK: %[[CVT:.*]] = fir.convert %[[LOAD]] : (complex) -> complex ! CHECK: fir.store %[[CVT]] to %[[M_DECL]]#0 : !fir.ref> @@ -57,7 +56,7 @@ subroutine atomic_implicit_cast_read m = w ! CHECK: %[[CONST:.*]] = arith.constant 1 : i32 -! CHECK: omp.atomic.capture { +! CHECK: omp.atomic.capture memory_order(relaxed) { ! CHECK: omp.atomic.read %[[ALLOCA4]] = %[[X_DECL]]#0 : !fir.ref, !fir.ref, i32 ! CHECK: omp.atomic.update %[[X_DECL]]#0 : !fir.ref { ! CHECK: ^bb0(%[[ARG:.*]]: i32): @@ -74,7 +73,7 @@ subroutine atomic_implicit_cast_read !$omp end atomic ! CHECK: %[[CONST:.*]] = arith.constant 10 : i32 -! CHECK: omp.atomic.capture { +! CHECK: omp.atomic.capture memory_order(relaxed) { ! CHECK: omp.atomic.read %[[ALLOCA5:.*]] = %[[X_DECL]]#0 : !fir.ref, !fir.ref, i32 ! CHECK: omp.atomic.write %[[X_DECL]]#0 = %[[CONST]] : !fir.ref, i32 ! CHECK: } @@ -87,7 +86,7 @@ subroutine atomic_implicit_cast_read !$omp end atomic ! CHECK: %[[CONST:.*]] = arith.constant 1 : i32 -! CHECK: omp.atomic.capture { +! CHECK: omp.atomic.capture memory_order(relaxed) { ! CHECK: omp.atomic.update %[[X_DECL]]#0 : !fir.ref { ! CHECK: ^bb0(%[[ARG:.*]]: i32): ! CHECK: %[[RESULT:.*]] = arith.addi %[[ARG]], %[[CONST]] : i32 @@ -112,7 +111,7 @@ subroutine atomic_implicit_cast_read ! CHECK: %[[UNDEF:.*]] = fir.undefined complex ! CHECK: %[[IDX1:.*]] = fir.insert_value %[[UNDEF]], %[[CST1]], [0 : index] : (complex, f64) -> complex ! CHECK: %[[IDX2:.*]] = fir.insert_value %[[IDX1]], %[[CST2]], [1 : index] : (complex, f64) -> complex -! CHECK: omp.atomic.capture { +! CHECK: omp.atomic.capture memory_order(relaxed) { ! CHECK: omp.atomic.update %[[M_DECL]]#0 : !fir.ref> { ! CHECK: ^bb0(%[[ARG:.*]]: complex): ! CHECK: %[[RESULT:.*]] = fir.addc %[[ARG]], %[[IDX2]] {fastmath = #arith.fastmath} : complex diff --git a/flang/test/Lower/OpenMP/common-atomic-lowering.f90 b/flang/test/Lower/OpenMP/common-atomic-lowering.f90 index f729bbb00ac8e..12bebb266cfb5 100644 --- a/flang/test/Lower/OpenMP/common-atomic-lowering.f90 +++ b/flang/test/Lower/OpenMP/common-atomic-lowering.f90 @@ -17,7 +17,7 @@ !CHECK: %[[val_10:.*]] = fir.load %[[val_5]]#0 : !fir.ref !CHECK: %[[val_11:.*]] = arith.addi %[[val_c8]], %[[val_10]] : i32 !CHECK: %[[val_12:.*]] = hlfir.no_reassoc %[[val_11]] : i32 -!CHECK: omp.atomic.update %[[val_9]] : !fir.ref { +!CHECK: omp.atomic.update memory_order(relaxed) %[[val_9]] : !fir.ref { !CHECK: ^bb0(%[[ARG:.*]]: i32): !CHECK: %[[val_18:.*]] = arith.muli %[[val_12]], %[[ARG]] : i32 !CHECK: omp.yield(%[[val_18]] : i32) @@ -25,7 +25,7 @@ !CHECK: %[[val_c2_0:.*]] = arith.constant 2 : index !CHECK: %[[val_13:.*]] = hlfir.designate %[[val_8]]#0 (%[[val_c2_0]]) : (!fir.ref>, index) -> !fir.ref !CHECK: %[[val_c8_1:.*]] = arith.constant 8 : i32 -!CHECK: omp.atomic.update %[[val_13:.*]] : !fir.ref { +!CHECK: omp.atomic.update memory_order(relaxed) %[[val_13:.*]] : !fir.ref { !CHECK: ^bb0(%[[ARG:.*]]: i32): !CHECK: %[[val_18:.*]] = arith.divsi %[[ARG]], %[[val_c8_1]] : i32 !CHECK: omp.yield(%[[val_18]] : i32) @@ -36,13 +36,13 @@ !CHECK: %[[val_15:.*]] = fir.load %[[val_14]] : !fir.ref !CHECK: %[[val_16:.*]] = arith.addi %[[val_c8_2]], %[[val_15]] : i32 !CHECK: %[[val_17:.*]] = hlfir.no_reassoc %[[val_16]] : i32 -!CHECK: omp.atomic.update %[[val_5]]#0 : !fir.ref { +!CHECK: omp.atomic.update memory_order(relaxed) %[[val_5]]#0 : !fir.ref { !CHECK: ^bb0(%[[ARG:.*]]: i32): !CHECK: %[[val_18:.*]] = arith.addi %[[val_17]], %[[ARG]] : i32 !CHECK: omp.yield(%[[val_18]] : i32) !CHECK: } !CHECK: %[[val_c8_3:.*]] = arith.constant 8 : i32 -!CHECK: omp.atomic.update %[[val_5]]#0 : !fir.ref { +!CHECK: omp.atomic.update memory_order(relaxed) %[[val_5]]#0 : !fir.ref { !CHECK: ^bb0(%[[ARG]]: i32): !CHECK: %[[val_18:.*]] = arith.subi %[[val_c8_3]], %[[ARG]] : i32 !CHECK: omp.yield(%[[val_18]] : i32) diff --git a/flang/test/Lower/OpenMP/copyprivate.f90 b/flang/test/Lower/OpenMP/copyprivate.f90 index 4c3ed9389369f..6999c548d7f02 100644 --- a/flang/test/Lower/OpenMP/copyprivate.f90 +++ b/flang/test/Lower/OpenMP/copyprivate.f90 @@ -1,7 +1,6 @@ ! Test COPYPRIVATE. ! RUN: %flang_fc1 -emit-hlfir -fopenmp -o - %s 2>&1 \ ! RUN: | FileCheck %s - !CHECK-DAG: func private @_copy_i64(%{{.*}}: !fir.ref, %{{.*}}: !fir.ref) !CHECK-DAG: func private @_copy_f32(%{{.*}}: !fir.ref, %{{.*}}: !fir.ref) !CHECK-DAG: func private @_copy_f64(%{{.*}}: !fir.ref, %{{.*}}: !fir.ref) diff --git a/flang/test/Lower/OpenMP/cray-pointers.f90 b/flang/test/Lower/OpenMP/cray-pointers.f90 new file mode 100644 index 0000000000000..1a0753244a461 --- /dev/null +++ b/flang/test/Lower/OpenMP/cray-pointers.f90 @@ -0,0 +1,33 @@ +! Test lowering of Cray pointee references. +! RUN: bbc -emit-hlfir -fopenmp %s -o - 2>&1 | FileCheck %s + +module test_host_assoc_cray_pointer + ! CHECK-LABEL: fir.global @_QMtest_host_assoc_cray_pointerEivar : i64 + real*8 var(*) + ! CHECK-LABEL: fir.global @_QMtest_host_assoc_cray_pointerEvar : !fir.array + pointer(ivar,var) + +contains + + ! CHECK-LABEL: func.func @_QMtest_host_assoc_cray_pointerPset_cray_pointer() + subroutine set_cray_pointer + ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.box>> + ! CHECK: %[[IVAR_ADDR:.*]] = fir.address_of(@_QMtest_host_assoc_cray_pointerEivar) : !fir.ref + ! CHECK: %[[IVAR_DECL:.*]]:2 = hlfir.declare %[[IVAR_ADDR]] {uniq_name = "_QMtest_host_assoc_cray_pointerEivar"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[VAR_DECL:.*]]:2 = hlfir.declare %[[ALLOCA]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMtest_host_assoc_cray_pointerEvar"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) + real*8 pointee(2) + pointee(1) = 42.0 + + ivar = loc(pointee) + + !$omp parallel default(none) shared(ivar) + ! CHECK: omp.parallel + ! CHECK: %[[I_01:.*]] = fir.convert %[[IVAR_DECL]]#0 : (!fir.ref) -> !fir.ref> + ! CHECK: %[[I_02:.*]] = fir.load %[[I_01]] : !fir.ref> + ! CHECK: %[[I_03:.*]] = fir.convert %[[VAR_DECL]]#0 : (!fir.ref>>>) -> !fir.ref> + ! CHECK: %[[I_04:.*]] = fir.convert %[[I_02]] : (!fir.ptr) -> !fir.llvm_ptr + ! CHECK: fir.call @_FortranAPointerAssociateScalar(%[[I_03]], %[[I_04]]) fastmath : (!fir.ref>, !fir.llvm_ptr) -> () + print *, var(1) + !$omp end parallel + end subroutine +end module diff --git a/flang/test/Lower/OpenMP/cray-pointers02.f90 b/flang/test/Lower/OpenMP/cray-pointers02.f90 index 79d838702e4b0..f28d21cd46791 100644 --- a/flang/test/Lower/OpenMP/cray-pointers02.f90 +++ b/flang/test/Lower/OpenMP/cray-pointers02.f90 @@ -63,7 +63,7 @@ subroutine none_private() ! CHECK: fir.call @_FortranAPointerAssociateScalar({{.*}}) fastmath : (!fir.ref>, !fir.llvm_ptr) -> () ! CHECK: fir.call @_FortranAPointerAssociateScalar({{.*}}) fastmath : (!fir.ref>, !fir.llvm_ptr) -> () var(1) = var(1) + 2 - print '(A24,I6)', 'none_private', var(1) + print '(A24,I6)', 'none_private', var(1) !$omp end parallel ! CHECK: return end subroutine diff --git a/flang/test/Lower/OpenMP/declare-mapper.f90 b/flang/test/Lower/OpenMP/declare-mapper.f90 index c389d0ff4bd15..c15139e69e30a 100644 --- a/flang/test/Lower/OpenMP/declare-mapper.f90 +++ b/flang/test/Lower/OpenMP/declare-mapper.f90 @@ -45,7 +45,7 @@ subroutine declare_mapper_1 !CHECK: %[[VAL_18:.*]] = fir.coordinate_of %[[VAL_1]]#0, values : (!fir.ref<[[MY_TYPE]]>) -> !fir.ref>>> !CHECK: %[[VAL_19:.*]] = fir.box_offset %[[VAL_18]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> !CHECK: %[[VAL_20:.*]] = omp.map.info var_ptr(%[[VAL_18]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAL_19]] : !fir.llvm_ptr>>) bounds(%[[VAL_16]]) -> !fir.llvm_ptr>> {name = ""} - !CHECK: %[[VAL_21:.*]] = omp.map.info var_ptr(%[[VAL_18]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {name = "var%[[VAL_22:.*]](1:var%[[VAL_23:.*]])"} + !CHECK: %[[VAL_21:.*]] = omp.map.info var_ptr(%[[VAL_18]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {name = "var%[[VAL_22:.*]](1:var%[[VAL_23:.*]])"} !CHECK: %[[VAL_24:.*]] = omp.map.info var_ptr(%[[VAL_1]]#1 : !fir.ref<[[MY_TYPE]]>, [[MY_TYPE]]) map_clauses(tofrom) capture(ByRef) members(%[[VAL_21]], %[[VAL_20]] : [1], [1, 0] : !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref<[[MY_TYPE]]> {name = "var"} !CHECK: omp.declare_mapper.info map_entries(%[[VAL_24]], %[[VAL_21]], %[[VAL_20]] : !fir.ref<[[MY_TYPE]]>, !fir.ref>>>, !fir.llvm_ptr>>) !CHECK: } @@ -81,7 +81,7 @@ subroutine declare_mapper_2 !CHECK: %[[VAL_9:.*]] = omp.map.info var_ptr(%[[VAL_4]] : !fir.ref>, !fir.array<250xf32>) map_clauses(tofrom) capture(ByRef) bounds(%[[VAL_8]]) -> !fir.ref> {name = "v%[[VAL_10:.*]]"} !CHECK: %[[VAL_11:.*]] = hlfir.designate %[[VAL_1]]#0{"temp"} : (!fir.ref<[[MY_TYPE]]>) -> !fir.ref>>}>> !CHECK: %[[VAL_12:.*]] = omp.map.info var_ptr(%[[VAL_11]] : !fir.ref>>}>>, !fir.type<_QFdeclare_mapper_2Tmy_type{num_vals:i32,values:!fir.box>>}>) map_clauses(storage) capture(ByRef) -> !fir.ref>>}>> {name = "v%[[VAL_13:.*]]"} - !CHECK: %[[VAL_14:.*]] = omp.map.info var_ptr(%[[VAL_1]]#1 : !fir.ref<[[MY_TYPE]]>, [[MY_TYPE]]) map_clauses(tofrom) capture(ByRef) members(%[[VAL_9]], %[[VAL_12]] : [3], [1] : !fir.ref>, !fir.ref>>}>>) -> !fir.ref<[[MY_TYPE]]> {name = "v", partial_map = true} + !CHECK: %[[VAL_14:.*]] = omp.map.info var_ptr(%[[VAL_1]]#1 : !fir.ref<[[MY_TYPE]]>, [[MY_TYPE]]) map_clauses(storage) capture(ByRef) members(%[[VAL_9]], %[[VAL_12]] : [3], [1] : !fir.ref>, !fir.ref>>}>>) -> !fir.ref<[[MY_TYPE]]> {name = "v", partial_map = true} !CHECK: omp.declare_mapper.info map_entries(%[[VAL_14]], %[[VAL_9]], %[[VAL_12]] : !fir.ref<[[MY_TYPE]]>, !fir.ref>, !fir.ref>>}>>) !CHECK: } !$omp declare mapper (my_mapper : my_type2 :: v) map (v%arr) map (alloc : v%temp) @@ -112,7 +112,7 @@ subroutine declare_mapper_3 !CHECK: %[[VAL_10:.*]] = arith.subi %[[VAL_5]], %[[VAL_8]] : index !CHECK: %[[VAL_11:.*]] = omp.map.bounds lower_bound(%[[VAL_9]] : index) upper_bound(%[[VAL_10]] : index) extent(%[[VAL_5]] : index) stride(%[[VAL_8]] : index) start_idx(%[[VAL_8]] : index) !CHECK: %[[VAL_12:.*]] = omp.map.info var_ptr(%[[VAL_7]] : !fir.ref>, !fir.array<250xf32>) map_clauses(tofrom) capture(ByRef) bounds(%[[VAL_11]]) -> !fir.ref> {name = "v%[[VAL_13:.*]]"} - !CHECK: %[[VAL_14:.*]] = omp.map.info var_ptr(%[[VAL_1]]#1 : !fir.ref<[[MY_TYPE2]]>, [[MY_TYPE2]]) map_clauses(tofrom) capture(ByRef) members(%[[VAL_3]], %[[VAL_12]] : [0], [1] : !fir.ref<[[MY_TYPE]]>, !fir.ref>) -> !fir.ref<[[MY_TYPE2]]> {name = "v", partial_map = true} + !CHECK: %[[VAL_14:.*]] = omp.map.info var_ptr(%[[VAL_1]]#1 : !fir.ref<[[MY_TYPE2]]>, [[MY_TYPE2]]) map_clauses(storage) capture(ByRef) members(%[[VAL_3]], %[[VAL_12]] : [0], [1] : !fir.ref<[[MY_TYPE]]>, !fir.ref>) -> !fir.ref<[[MY_TYPE2]]> {name = "v", partial_map = true} !CHECK: omp.declare_mapper.info map_entries(%[[VAL_14]], %[[VAL_3]], %[[VAL_12]] : !fir.ref<[[MY_TYPE2]]>, !fir.ref<[[MY_TYPE]]>, !fir.ref>) !CHECK: } @@ -137,7 +137,7 @@ subroutine declare_mapper_3 !CHECK: %[[VAL_18:.*]] = fir.coordinate_of %[[VAL_1]]#0, values : (!fir.ref<[[MY_TYPE]]>) -> !fir.ref>>> !CHECK: %[[VAL_19:.*]] = fir.box_offset %[[VAL_18]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> !CHECK: %[[VAL_20:.*]] = omp.map.info var_ptr(%[[VAL_18]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAL_19]] : !fir.llvm_ptr>>) bounds(%[[VAL_16]]) -> !fir.llvm_ptr>> {name = ""} - !CHECK: %[[VAL_21:.*]] = omp.map.info var_ptr(%[[VAL_18]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {name = "var%[[VAL_22:.*]](1:var%[[VAL_23:.*]])"} + !CHECK: %[[VAL_21:.*]] = omp.map.info var_ptr(%[[VAL_18]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {name = "var%[[VAL_22:.*]](1:var%[[VAL_23:.*]])"} !CHECK: %[[VAL_24:.*]] = omp.map.info var_ptr(%[[VAL_1]]#1 : !fir.ref<[[MY_TYPE]]>, [[MY_TYPE]]) map_clauses(tofrom) capture(ByRef) members(%[[VAL_21]], %[[VAL_20]] : [1], [1, 0] : !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref<[[MY_TYPE]]> {name = "var"} !CHECK: omp.declare_mapper.info map_entries(%[[VAL_24]], %[[VAL_21]], %[[VAL_20]] : !fir.ref<[[MY_TYPE]]>, !fir.ref>>>, !fir.llvm_ptr>>) !CHECK: } diff --git a/flang/test/Lower/OpenMP/declare-target-link-tarop-cap.f90 b/flang/test/Lower/OpenMP/declare-target-link-tarop-cap.f90 index cfdcd9eda82d1..36c7692d9f024 100644 --- a/flang/test/Lower/OpenMP/declare-target-link-tarop-cap.f90 +++ b/flang/test/Lower/OpenMP/declare-target-link-tarop-cap.f90 @@ -1,7 +1,7 @@ -!RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s -!RUN: %flang_fc1 -emit-hlfir -fopenmp -fopenmp-is-device %s -o - | FileCheck %s -!RUN: bbc -emit-hlfir -fopenmp %s -o - | FileCheck %s -!RUN: bbc -emit-hlfir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s +!RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes=BOTH,HOST +!RUN: %flang_fc1 -emit-hlfir -fopenmp -fopenmp-is-device %s -o - | FileCheck %s --check-prefixes=BOTH,DEVICE +!RUN: bbc -emit-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes=BOTH,HOST +!RUN: bbc -emit-hlfir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefixes=BOTH,DEVICE program test_link @@ -20,13 +20,14 @@ program test_link integer, pointer :: test_ptr2 !$omp declare target link(test_ptr2) - !CHECK-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref, i32) map_clauses(implicit, tofrom) capture(ByRef) -> !fir.ref {name = "test_int"} + !BOTH-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref, i32) map_clauses(implicit, tofrom) capture(ByRef) -> !fir.ref {name = "test_int"} !$omp target test_int = test_int + 1 !$omp end target - !CHECK-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref>, !fir.array<3xi32>) map_clauses(implicit, tofrom) capture(ByRef) bounds({{%.*}}) -> !fir.ref> {name = "test_array_1d"} + !HOST-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref>, !fir.array<3xi32>) map_clauses(implicit, tofrom) capture(ByRef) bounds({{%.*}}) -> !fir.ref> {name = "test_array_1d"} + !DEVICE-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref>, !fir.array<3xi32>) map_clauses(implicit, tofrom) capture(ByRef) -> !fir.ref> {name = "test_array_1d"} !$omp target do i = 1,3 test_array_1d(i) = i * 2 @@ -35,18 +36,18 @@ program test_link allocate(test_ptr1) test_ptr1 = 1 - !CHECK-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref>>, !fir.box>) map_clauses(implicit, to) capture(ByRef) members({{%.*}} : !fir.llvm_ptr>) -> !fir.ref>> {name = "test_ptr1"} + !BOTH-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref>>, !fir.box>) map_clauses(always, implicit, descriptor, to) capture(ByRef) members({{%.*}} : !fir.llvm_ptr>) -> !fir.ref>> {name = "test_ptr1"} !$omp target test_ptr1 = test_ptr1 + 1 !$omp end target - !CHECK-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref, i32) map_clauses(implicit, tofrom) capture(ByRef) -> !fir.ref {name = "test_target"} + !BOTH-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref, i32) map_clauses(implicit, tofrom) capture(ByRef) -> !fir.ref {name = "test_target"} !$omp target test_target = test_target + 1 !$omp end target - !CHECK-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref>>, !fir.box>) map_clauses(implicit, to) capture(ByRef) members({{%.*}} : !fir.llvm_ptr>) -> !fir.ref>> {name = "test_ptr2"} + !BOTH-DAG: {{%.*}} = omp.map.info var_ptr({{%.*}} : !fir.ref>>, !fir.box>) map_clauses(always, implicit, descriptor, to) capture(ByRef) members({{%.*}} : !fir.llvm_ptr>) -> !fir.ref>> {name = "test_ptr2"} test_ptr2 => test_target !$omp target test_ptr2 = test_ptr2 + 1 diff --git a/flang/test/Lower/OpenMP/defaultmap.f90 b/flang/test/Lower/OpenMP/defaultmap.f90 index b9c902fe43f13..fa79ffd2ae87e 100644 --- a/flang/test/Lower/OpenMP/defaultmap.f90 +++ b/flang/test/Lower/OpenMP/defaultmap.f90 @@ -1,4 +1,5 @@ -!RUN: %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=52 -mmlir --enable-delayed-privatization-staging=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FPRIV +! NOTE: Do not check for false delayed privatization flag until all enable-delayed-privatization flags are switched on in amd-staging +!RUN %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=52 -mmlir --enable-delayed-privatization-staging=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FPRIV !RUN: %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=52 -mmlir --enable-delayed-privatization-staging=true %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPRIV subroutine defaultmap_allocatable_present() @@ -6,7 +7,7 @@ subroutine defaultmap_allocatable_present() integer, dimension(:), allocatable :: arr ! CHECK: %[[MAP_1:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>>, i32) map_clauses(implicit, present) capture(ByRef) var_ptr_ptr({{.*}}) bounds({{.*}}) -> !fir.llvm_ptr>> {name = ""} -! CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(implicit, to) capture(ByRef) members({{.*}}) -> !fir.ref>>> {name = "arr"} +! CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(always, implicit, descriptor, to) capture(ByRef) members({{.*}}) -> !fir.ref>>> {name = "arr"} !$omp target defaultmap(present: allocatable) arr(1) = 10 !$omp end target @@ -34,7 +35,7 @@ subroutine defaultmap_all_default() ! CHECK: %[[MAP_1:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref, i32) map_clauses(implicit) capture(ByCopy) -> !fir.ref {name = "scalar_int"} ! CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>>, i32) map_clauses(implicit, tofrom) capture(ByRef) var_ptr_ptr({{.*}}) bounds({{.*}}) -> !fir.llvm_ptr>> {name = ""} -! CHECK: %[[MAP_3:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(implicit, to) capture(ByRef) members({{.*}}) -> !fir.ref>>> {name = "arr"} +! CHECK: %[[MAP_3:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(always, implicit, descriptor, to) capture(ByRef) members({{.*}}) -> !fir.ref>>> {name = "arr"} ! CHECK: %[[MAP_4:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>, !fir.array<16xi32>) map_clauses(implicit, tofrom) capture(ByRef) bounds({{.*}}) -> !fir.ref> {name = "aggregate"} !$omp target defaultmap(default: all) @@ -52,7 +53,7 @@ subroutine defaultmap_pointer_to() ! CHECK-NO-FPRIV: %[[MAP_1:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>>, i32) map_clauses(implicit, to) capture(ByRef) var_ptr_ptr({{.*}}) bounds({{.*}}) -> !fir.llvm_ptr>> {name = ""} ! CHECK-FPRIV: %[[MAP_1:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>>, i32) map_clauses(implicit, to) capture(ByRef) var_ptr_ptr({{.*}}) bounds({{.*}}) -> !fir.llvm_ptr>> {name = ""} -! CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(implicit, to) capture(ByRef) members({{.*}}) -> !fir.ref>>> {name = "arr_ptr"} +! CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(always, implicit, descriptor, to) capture(ByRef) members({{.*}}) -> !fir.ref>>> {name = "arr_ptr"} ! CHECK-FPRIV: %[[MAP_3:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref, i32) map_clauses(to) capture(ByCopy) -> !fir.ref ! CHECK-NO-FPRIV: %[[MAP_3:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref, i32) map_clauses(implicit) capture(ByCopy) -> !fir.ref {name = "scalar_int"} !$omp target defaultmap(to: pointer) diff --git a/flang/test/Lower/OpenMP/derived-type-allocatable-map.f90 b/flang/test/Lower/OpenMP/derived-type-allocatable-map.f90 index d19a572c1f4fb..eb071240e791d 100644 --- a/flang/test/Lower/OpenMP/derived-type-allocatable-map.f90 +++ b/flang/test/Lower/OpenMP/derived-type-allocatable-map.f90 @@ -5,9 +5,9 @@ !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) {stride_in_bytes = true} !CHECK: %[[MEMBER_COORD:.*]] = fir.coordinate_of %[[DECLARE]]#0, array_j : (!fir.ref>) -> !fir.ref>>> !CHECK: %[[MEMBER_BASE_ADDR:.*]] = fir.box_offset %[[MEMBER_COORD]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -!CHECK: %[[MAP_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} -!CHECK: %[[MAP_MEMBER_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {{.*}} -!CHECK: %[[MAP_PARENT:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>, !fir.type<[[ONE_LAYER_TY]]>) map_clauses(tofrom) capture(ByRef) members(%[[MAP_MEMBER_DESCRIPTOR]], %[[MAP_MEMBER_BASE_ADDR]] : [4], [4, 0] : !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref> {{{.*}} partial_map = true} +!CHECK: %[[MAP_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} +!CHECK: %[[MAP_MEMBER_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {{.*}} +!CHECK: %[[MAP_PARENT:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>, !fir.type<[[ONE_LAYER_TY]]>) map_clauses(storage) capture(ByRef) members(%[[MAP_MEMBER_DESCRIPTOR]], %[[MAP_MEMBER_BASE_ADDR]] : [4], [4, 0] : !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref> {{{.*}} partial_map = true} !CHECK: omp.target map_entries(%[[MAP_PARENT]] -> %[[ARG0:.*]], %[[MAP_MEMBER_DESCRIPTOR]] -> %[[ARG1:.*]], %[[MAP_MEMBER_BASE_ADDR]] -> %[[ARG2:.*]] : !fir.ref>, !fir.ref>>>, !fir.llvm_ptr>>) { !CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] {{{.*}}} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) subroutine dtype_alloca_map_op_block() @@ -35,14 +35,14 @@ subroutine dtype_alloca_map_op_block() !CHECK: %[[LOAD_DTYPE:.*]] = fir.load %[[DECLARE]]#0 : !fir.ref>>> !CHECK: %[[MEMBER_COORD:.*]] = fir.coordinate_of %[[LOAD_DTYPE]], array_j : (!fir.box>>) -> !fir.ref>>> !CHECK: %[[MEMBER_BASE_ADDR:.*]] = fir.box_offset %[[MEMBER_COORD]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -!CHECK: %[[MAP_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} -!CHECK: %[[MAP_MEMBER_DESC:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {{.*}} +!CHECK: %[[MAP_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} +!CHECK: %[[MAP_MEMBER_DESC:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {{.*}} !CHECK: %[[LOAD_DTYPE:.*]] = fir.load %[[DECLARE]]#0 : !fir.ref>>> !CHECK: %[[REGULAR_MEMBER:.*]] = fir.coordinate_of %[[LOAD_DTYPE]], k : (!fir.box>>) -> !fir.ref !CHECK: %[[MAP_REGULAR_MEMBER:.*]] = omp.map.info var_ptr(%[[REGULAR_MEMBER]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {{.*}} !CHECK: %[[DTYPE_BASE_ADDR:.*]] = fir.box_offset %[[DECLARE]]#1 base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -!CHECK: %[[MAP_DTYPE_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>>>, !fir.type<[[REC_TY]]>) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[DTYPE_BASE_ADDR]] : !fir.llvm_ptr>>) -> !fir.llvm_ptr>> {{.*}} -!CHECK: %[[MAP_DTYPE_DESC:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) members(%[[MAP_DTYPE_BASE_ADDR]], %[[MAP_MEMBER_DESC]], %[[MAP_MEMBER_BASE_ADDR]], %[[MAP_REGULAR_MEMBER]] : [0], [0, 4], [0, 4, 0], [0, 5] : !fir.llvm_ptr>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) -> !fir.ref>>> {{.*}} +!CHECK: %[[MAP_DTYPE_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>>>, !fir.type<[[REC_TY]]>) map_clauses(storage) capture(ByRef) var_ptr_ptr(%[[DTYPE_BASE_ADDR]] : !fir.llvm_ptr>>) -> !fir.llvm_ptr>> {{.*}} +!CHECK: %[[MAP_DTYPE_DESC:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[MAP_DTYPE_BASE_ADDR]], %[[MAP_MEMBER_DESC]], %[[MAP_MEMBER_BASE_ADDR]], %[[MAP_REGULAR_MEMBER]] : [0], [0, 4], [0, 4, 0], [0, 5] : !fir.llvm_ptr>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) -> !fir.ref>>> {{.*}} !CHECK: omp.target map_entries(%[[MAP_DTYPE_DESC]] -> %[[ARG0:.*]], %[[MAP_DTYPE_BASE_ADDR]] -> %[[ARG1:.*]], %[[MAP_MEMBER_DESC]] -> %[[ARG2:.*]], %[[MAP_MEMBER_BASE_ADDR]] -> %[[ARG3:.*]], %[[MAP_REGULAR_MEMBER]] -> %[[ARG4:.*]] : !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) { !CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] {{{.*}}} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) subroutine alloca_dtype_op_block_add() @@ -73,15 +73,15 @@ subroutine alloca_dtype_op_block_add() !CHECK: %[[NESTED_DTYPE_COORD:.*]] = fir.coordinate_of %[[LOAD]], nest : (!fir.box}>>>) -> !fir.ref,array_k:!fir.box>>,k:i32}]]>> !CHECK: %[[NESTED_MEMBER_COORD:.*]] = fir.coordinate_of %[[NESTED_DTYPE_COORD]], array_k : (!fir.ref>) -> !fir.ref>>> !CHECK: %[[NESTED_MEMBER_BASE_ADDR:.*]] = fir.box_offset %[[NESTED_MEMBER_COORD]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -!CHECK: %[[MAP_NESTED_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[NESTED_MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[NESTED_MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} -!CHECK: %[[MAP_NESTED_MEMBER_COORD:.*]] = omp.map.info var_ptr(%[[NESTED_MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {{.*}} +!CHECK: %[[MAP_NESTED_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[NESTED_MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[NESTED_MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} +!CHECK: %[[MAP_NESTED_MEMBER_COORD:.*]] = omp.map.info var_ptr(%[[NESTED_MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {{.*}} !CHECK: %[[LOAD:.*]] = fir.load %[[DECLARE]]#0 : !fir.ref}>>>> !CHECK: %[[NESTED_DTYPE_COORD:.*]] = fir.coordinate_of %[[LOAD]], nest : (!fir.box}>>>) -> !fir.ref> !CHECK: %[[REGULAR_NESTED_MEMBER_COORD:.*]] = fir.coordinate_of %[[NESTED_DTYPE_COORD]], k : (!fir.ref>) -> !fir.ref !CHECK: %[[MAP_REGULAR_NESTED_MEMBER:.*]] = omp.map.info var_ptr(%[[REGULAR_NESTED_MEMBER_COORD]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {{.*}} !CHECK: %[[DTYPE_BASE_ADDR:.*]] = fir.box_offset %[[DECLARE]]#1 base_addr : (!fir.ref}>>>>) -> !fir.llvm_ptr}>>> -!CHECK: %[[MAP_DTYPE_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref}>>>>, !fir.type<[[REC_TY]]>}>) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[DTYPE_BASE_ADDR]] : !fir.llvm_ptr}>>>) -> !fir.llvm_ptr}>>> {{.*}} -!CHECK: %[[MAP_DTYPE:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref}>>>>, !fir.box}>>>) map_clauses(to) capture(ByRef) members(%[[MAP_DTYPE_BASE_ADDR]], %[[MAP_NESTED_MEMBER_COORD]], %[[MAP_NESTED_MEMBER_BASE_ADDR]], %[[MAP_REGULAR_NESTED_MEMBER]] : [0], [0, 6, 2], [0, 6, 2, 0], [0, 6, 3] : !fir.llvm_ptr}>>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) -> !fir.ref}>>>> {{.*}} +!CHECK: %[[MAP_DTYPE_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref}>>>>, !fir.type<[[REC_TY]]>}>) map_clauses(storage) capture(ByRef) var_ptr_ptr(%[[DTYPE_BASE_ADDR]] : !fir.llvm_ptr}>>>) -> !fir.llvm_ptr}>>> {{.*}} +!CHECK: %[[MAP_DTYPE:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref}>>>>, !fir.box}>>>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[MAP_DTYPE_BASE_ADDR]], %[[MAP_NESTED_MEMBER_COORD]], %[[MAP_NESTED_MEMBER_BASE_ADDR]], %[[MAP_REGULAR_NESTED_MEMBER]] : [0], [0, 6, 2], [0, 6, 2, 0], [0, 6, 3] : !fir.llvm_ptr}>>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) -> !fir.ref}>>>> {{.*}} !CHECK: omp.target map_entries(%[[MAP_DTYPE]] -> %[[ARG0:.*]], %[[MAP_DTYPE_BASE_ADDR]] -> %[[ARG1:.*]], %[[MAP_NESTED_MEMBER_COORD]] -> %[[ARG2:.*]], %[[MAP_NESTED_MEMBER_BASE_ADDR]] -> %[[ARG3:.*]], %[[MAP_REGULAR_NESTED_MEMBER]] -> %[[ARG4:.*]] : !fir.ref}>>>>, !fir.llvm_ptr}>>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) { !CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] {{.*}} : (!fir.ref}>>>>) -> (!fir.ref}>>>>, !fir.ref}>>>>) subroutine alloca_nest_dype_map_op_block_add() @@ -119,9 +119,9 @@ subroutine alloca_nest_dype_map_op_block_add() !CHECK: %[[NESTED_DTYPE_COORD:.*]] = fir.coordinate_of %[[DECLARE]]#0, nest : (!fir.ref>) -> !fir.ref,array_k:!fir.box>>,k:i32}]]>> !CHECK: %[[NESTED_MEMBER_COORD:.*]] = fir.coordinate_of %[[NESTED_DTYPE_COORD]], array_k : (!fir.ref>) -> !fir.ref>>> !CHECK: %[[NESTED_MEMBER_BASE_ADDR:.*]] = fir.box_offset %[[NESTED_MEMBER_COORD]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -!CHECK: %[[MAP_NESTED_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[NESTED_MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[NESTED_MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} -!CHECK: %[[MAP_NESTED_MEMBER_DESC:.*]] = omp.map.info var_ptr(%[[NESTED_MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {{.*}} -!CHECK: %[[MAP_PARENT:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>, !fir.type<[[REC_TY]]>) map_clauses(tofrom) capture(ByRef) members(%[[MAP_NESTED_MEMBER_DESC]], %[[MAP_NESTED_MEMBER_BASE_ADDR]] : [6, 2], [6, 2, 0] : !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref> {{.*}} +!CHECK: %[[MAP_NESTED_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[NESTED_MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[NESTED_MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} +!CHECK: %[[MAP_NESTED_MEMBER_DESC:.*]] = omp.map.info var_ptr(%[[NESTED_MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {{.*}} +!CHECK: %[[MAP_PARENT:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref>, !fir.type<[[REC_TY]]>) map_clauses(storage) capture(ByRef) members(%[[MAP_NESTED_MEMBER_DESC]], %[[MAP_NESTED_MEMBER_BASE_ADDR]] : [6, 2], [6, 2, 0] : !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref> {{.*}} !CHECK: omp.target map_entries(%[[MAP_PARENT]] -> %[[ARG0:.*]], %[[MAP_NESTED_MEMBER_DESC]] -> %[[ARG1:.*]], %[[MAP_NESTED_MEMBER_BASE_ADDR]] -> %[[ARG2:.*]] : !fir.ref>, !fir.ref>>>, !fir.llvm_ptr>>) { !CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] {{.*}} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) subroutine nest_dtype_alloca_map_op_block_add() diff --git a/flang/test/Lower/OpenMP/derived-type-map.f90 b/flang/test/Lower/OpenMP/derived-type-map.f90 index 279cddec51fcf..0b08aacdc6b59 100644 --- a/flang/test/Lower/OpenMP/derived-type-map.f90 +++ b/flang/test/Lower/OpenMP/derived-type-map.f90 @@ -6,16 +6,16 @@ !CHECK: %[[MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref,int:i32}>>, !fir.type<_QFmaptype_derived_implicitTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}>) map_clauses(implicit, tofrom) capture(ByRef) -> !fir.ref,int:i32}>> {name = "scalar_arr"} !CHECK: omp.target map_entries(%[[MAP]] -> %[[ARG0:.*]] : !fir.ref,int:i32}>>) { subroutine mapType_derived_implicit - type :: scalar_and_array - real(4) :: real - integer(4) :: array(10) - integer(4) :: int - end type scalar_and_array - type(scalar_and_array) :: scalar_arr - - !$omp target - scalar_arr%int = 1 - !$omp end target + type :: scalar_and_array + real(4) :: real + integer(4) :: array(10) + integer(4) :: int + end type scalar_and_array + type(scalar_and_array) :: scalar_arr + + !$omp target + scalar_arr%int = 1 + !$omp end target end subroutine mapType_derived_implicit !CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.type<_QFmaptype_derived_explicitTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}> {bindc_name = "scalar_arr", uniq_name = "_QFmaptype_derived_explicitEscalar_arr"} @@ -23,16 +23,16 @@ end subroutine mapType_derived_implicit !CHECK: %[[MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref,int:i32}>>, !fir.type<_QFmaptype_derived_explicitTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}>) map_clauses(tofrom) capture(ByRef) -> !fir.ref,int:i32}>> {name = "scalar_arr"} !CHECK: omp.target map_entries(%[[MAP]] -> %[[ARG0:.*]] : !fir.ref,int:i32}>>) { subroutine mapType_derived_explicit - type :: scalar_and_array - real(4) :: real - integer(4) :: array(10) - integer(4) :: int - end type scalar_and_array - type(scalar_and_array) :: scalar_arr - - !$omp target map(tofrom: scalar_arr) - scalar_arr%int = 1 - !$omp end target + type :: scalar_and_array + real(4) :: real + integer(4) :: array(10) + integer(4) :: int + end type scalar_and_array + type(scalar_and_array) :: scalar_arr + + !$omp target map(tofrom: scalar_arr) + scalar_arr%int = 1 + !$omp end target end subroutine mapType_derived_explicit !CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.type<_QFmaptype_derived_explicit_single_memberTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}> {bindc_name = "scalar_arr", uniq_name = "_QFmaptype_derived_explicit_single_memberEscalar_arr"} @@ -40,19 +40,19 @@ end subroutine mapType_derived_explicit !CHECK: %[[MEMBER:.*]] = hlfir.designate %[[DECLARE]]#0{"array"} shape %{{.*}} : (!fir.ref,int:i32}>>, !fir.shape<1>) -> !fir.ref> !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%{{.*}} : index) upper_bound(%{{.*}} : index) extent(%{{.*}} : index) stride(%{{.*}} : index) start_idx(%{{.*}} : index) !CHECK: %[[MEMBER_MAP:.*]] = omp.map.info var_ptr(%[[MEMBER]] : !fir.ref>, !fir.array<10xi32>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "scalar_arr%array"} -!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref,int:i32}>>, !fir.type<_QFmaptype_derived_explicit_single_memberTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}>) map_clauses(tofrom) capture(ByRef) members(%[[MEMBER_MAP]] : [1] : !fir.ref>) -> !fir.ref,int:i32}>> {name = "scalar_arr", partial_map = true} +!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref,int:i32}>>, !fir.type<_QFmaptype_derived_explicit_single_memberTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}>) map_clauses(storage) capture(ByRef) members(%[[MEMBER_MAP]] : [1] : !fir.ref>) -> !fir.ref,int:i32}>> {name = "scalar_arr", partial_map = true} !CHECK: omp.target map_entries(%[[PARENT_MAP]] -> %[[ARG0:.*]], %[[MEMBER_MAP]] -> %[[ARG1:.*]] : !fir.ref,int:i32}>>, !fir.ref>) { subroutine mapType_derived_explicit_single_member - type :: scalar_and_array - real(4) :: real - integer(4) :: array(10) - integer(4) :: int - end type scalar_and_array - type(scalar_and_array) :: scalar_arr - - !$omp target map(tofrom: scalar_arr%array) - scalar_arr%array(1) = 1 - !$omp end target + type :: scalar_and_array + real(4) :: real + integer(4) :: array(10) + integer(4) :: int + end type scalar_and_array + type(scalar_and_array) :: scalar_arr + + !$omp target map(tofrom: scalar_arr%array) + scalar_arr%array(1) = 1 + !$omp end target end subroutine mapType_derived_explicit_single_member !CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.type<_QFmaptype_derived_explicit_multiple_membersTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}> {bindc_name = "scalar_arr", uniq_name = "_QFmaptype_derived_explicit_multiple_membersEscalar_arr"} @@ -61,21 +61,21 @@ end subroutine mapType_derived_explicit_single_member !CHECK: %[[MEMBER_MAP_1:.*]] = omp.map.info var_ptr(%[[MEMBER1]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "scalar_arr%int"} !CHECK: %[[MEMBER2:.*]] = hlfir.designate %[[DECLARE]]#0{"real"} : (!fir.ref,int:i32}>>) -> !fir.ref !CHECK: %[[MEMBER_MAP_2:.*]] = omp.map.info var_ptr(%[[MEMBER2]] : !fir.ref, f32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "scalar_arr%real"} -!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref,int:i32}>>, !fir.type<_QFmaptype_derived_explicit_multiple_membersTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}>) map_clauses(tofrom) capture(ByRef) members(%[[MEMBER_MAP_1]], %[[MEMBER_MAP_2]] : [2], [0] : !fir.ref, !fir.ref) -> !fir.ref,int:i32}>> {name = "scalar_arr", partial_map = true} +!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref,int:i32}>>, !fir.type<_QFmaptype_derived_explicit_multiple_membersTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}>) map_clauses(storage) capture(ByRef) members(%[[MEMBER_MAP_1]], %[[MEMBER_MAP_2]] : [2], [0] : !fir.ref, !fir.ref) -> !fir.ref,int:i32}>> {name = "scalar_arr", partial_map = true} !CHECK: omp.target map_entries(%[[PARENT_MAP]] -> %[[ARG0:.*]], %[[MEMBER_MAP_1]] -> %[[ARG1:.*]], %[[MEMBER_MAP_2]] -> %[[ARG2:.*]] : !fir.ref,int:i32}>>, !fir.ref, !fir.ref) { subroutine mapType_derived_explicit_multiple_members - type :: scalar_and_array - real(4) :: real - integer(4) :: array(10) - integer(4) :: int - end type scalar_and_array - type(scalar_and_array) :: scalar_arr - - !$omp target map(tofrom: scalar_arr%int, scalar_arr%real) - scalar_arr%int = 1 - !$omp end target + type :: scalar_and_array + real(4) :: real + integer(4) :: array(10) + integer(4) :: int + end type scalar_and_array + type(scalar_and_array) :: scalar_arr + + !$omp target map(tofrom: scalar_arr%int, scalar_arr%real) + scalar_arr%int = 1 + !$omp end target end subroutine mapType_derived_explicit_multiple_members - + !CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.type<_QFmaptype_derived_explicit_member_with_boundsTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}> {bindc_name = "scalar_arr", uniq_name = "_QFmaptype_derived_explicit_member_with_boundsEscalar_arr"} !CHECK: %[[DECLARE:.*]]:2 = hlfir.declare %[[ALLOCA]] {uniq_name = "_QFmaptype_derived_explicit_member_with_boundsEscalar_arr"} : (!fir.ref,int:i32}>>) -> (!fir.ref,int:i32}>>, !fir.ref,int:i32}>>) !CHECK: %[[MEMBER:.*]] = hlfir.designate %[[DECLARE]]#0{"array"} shape %{{.*}} : (!fir.ref,int:i32}>>, !fir.shape<1>) -> !fir.ref> @@ -84,19 +84,19 @@ end subroutine mapType_derived_explicit_multiple_members !CHECK: %[[UB:.*]] = arith.constant 4 : index !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%[[LB]] : index) upper_bound(%[[UB]] : index) extent(%{{.*}} : index) stride(%{{.*}} : index) start_idx(%{{.*}} : index) !CHECK: %[[MEMBER_MAP:.*]] = omp.map.info var_ptr(%[[MEMBER]] : !fir.ref>, !fir.array<10xi32>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "scalar_arr%array(2:5)"} -!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref,int:i32}>>, !fir.type<_QFmaptype_derived_explicit_member_with_boundsTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}>) map_clauses(tofrom) capture(ByRef) members(%[[MEMBER_MAP]] : [1] : !fir.ref>) -> !fir.ref,int:i32}>> {name = "scalar_arr", partial_map = true} +!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : !fir.ref,int:i32}>>, !fir.type<_QFmaptype_derived_explicit_member_with_boundsTscalar_and_array{real:f32,array:!fir.array<10xi32>,int:i32}>) map_clauses(storage) capture(ByRef) members(%[[MEMBER_MAP]] : [1] : !fir.ref>) -> !fir.ref,int:i32}>> {name = "scalar_arr", partial_map = true} !CHECK: omp.target map_entries(%[[PARENT_MAP]] -> %[[ARG0:.*]], %[[MEMBER_MAP]] -> %[[ARG1:.*]] : !fir.ref,int:i32}>>, !fir.ref>) { subroutine mapType_derived_explicit_member_with_bounds - type :: scalar_and_array - real(4) :: real - integer(4) :: array(10) - integer(4) :: int - end type scalar_and_array - type(scalar_and_array) :: scalar_arr - - !$omp target map(tofrom: scalar_arr%array(2:5)) - scalar_arr%array(3) = 3 - !$omp end target + type :: scalar_and_array + real(4) :: real + integer(4) :: array(10) + integer(4) :: int + end type scalar_and_array + type(scalar_and_array) :: scalar_arr + + !$omp target map(tofrom: scalar_arr%array(2:5)) + scalar_arr%array(3) = 3 + !$omp end target end subroutine mapType_derived_explicit_member_with_bounds !CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.type<_QFmaptype_derived_nested_explicit_single_memberTscalar_and_array{real:f32,array:!fir.array<10xi32>,nest:!fir.type<_QFmaptype_derived_nested_explicit_single_memberTnested{int:i32,real:f32,array:!fir.array<10xi32>}>,int:i32}> {bindc_name = "scalar_arr", uniq_name = "_QFmaptype_derived_nested_explicit_single_memberEscalar_arr"} @@ -105,7 +105,7 @@ end subroutine mapType_derived_explicit_member_with_bounds !CHECK: %[[NEST_MEMBER:.*]] = hlfir.designate %[[NEST]]{"array"} shape %{{.*}} : (!fir.ref}>>, !fir.shape<1>) -> !fir.ref> !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%{{.*}} : index) upper_bound(%{{.*}} : index) extent(%{{.*}} : index) stride(%{{.*}} : index) start_idx(%{{.*}} : index) !CHECK: %[[MEMBER_MAP:.*]] = omp.map.info var_ptr(%[[NEST_MEMBER]] : !fir.ref>, !fir.array<10xi32>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "scalar_arr%nest%array"} -!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : {{.*}}) map_clauses(tofrom) capture(ByRef) members(%[[MEMBER_MAP]] : [2, 2] : !fir.ref>) -> {{.*}} {name = "scalar_arr", partial_map = true} +!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : {{.*}}) map_clauses(storage) capture(ByRef) members(%[[MEMBER_MAP]] : [2, 2] : !fir.ref>) -> {{.*}} {name = "scalar_arr", partial_map = true} !CHECK: omp.target map_entries(%[[PARENT_MAP]] -> %[[ARG0:.*]], %[[MEMBER_MAP]] -> %[[ARG1:.*]] : {{.*}}, {{.*}}) { subroutine mapType_derived_nested_explicit_single_member type :: nested @@ -120,8 +120,8 @@ subroutine mapType_derived_nested_explicit_single_member type(nested) :: nest integer(4) :: int end type scalar_and_array - - type(scalar_and_array) :: scalar_arr + + type(scalar_and_array) :: scalar_arr !$omp target map(tofrom: scalar_arr%nest%array) scalar_arr%nest%array(1) = 1 @@ -136,7 +136,7 @@ end subroutine mapType_derived_nested_explicit_single_member !CHECK: %[[NEST:.*]] = hlfir.designate %[[DECLARE]]#0{"nest"} : ({{.*}}) -> {{.*}} !CHECK: %[[NEST_MEMBER2:.*]] = hlfir.designate %[[NEST]]{"real"} : ({{.*}}) -> !fir.ref !CHECK: %[[MEMBER_MAP_2:.*]] = omp.map.info var_ptr(%[[NEST_MEMBER2]] : !fir.ref, f32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "scalar_arr%nest%real"} -!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : {{.*}}, {{.*}}) map_clauses(tofrom) capture(ByRef) members(%[[MEMBER_MAP_1]], %[[MEMBER_MAP_2]] : [2, 0], [2, 1] : !fir.ref, !fir.ref) -> {{.*}} {name = "scalar_arr", partial_map = true} +!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : {{.*}}, {{.*}}) map_clauses(storage) capture(ByRef) members(%[[MEMBER_MAP_1]], %[[MEMBER_MAP_2]] : [2, 0], [2, 1] : !fir.ref, !fir.ref) -> {{.*}} {name = "scalar_arr", partial_map = true} !CHECK: omp.target map_entries(%[[PARENT_MAP]] -> %[[ARG0:.*]], %[[MEMBER_MAP_1]] -> %[[ARG1:.*]], %[[MEMBER_MAP_2]] -> %[[ARG2:.*]] : {{.*}}, !fir.ref, !fir.ref) { subroutine mapType_derived_nested_explicit_multiple_members type :: nested @@ -152,7 +152,7 @@ subroutine mapType_derived_nested_explicit_multiple_members integer(4) :: int end type scalar_and_array - type(scalar_and_array) :: scalar_arr + type(scalar_and_array) :: scalar_arr !$omp target map(tofrom: scalar_arr%nest%int, scalar_arr%nest%real) scalar_arr%nest%int = 1 @@ -169,7 +169,7 @@ end subroutine mapType_derived_nested_explicit_multiple_members !CHECK: %[[C4:.*]] = arith.constant 4 : index !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%[[C1_2]] : index) upper_bound(%[[C4]] : index) extent(%[[C10]] : index) stride(%[[C1]] : index) start_idx(%[[C1]] : index) !CHECK: %[[MEMBER_MAP:.*]] = omp.map.info var_ptr(%[[NEST_MEMBER]] : !fir.ref>, !fir.array<10xi32>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "scalar_arr%nest%array(2:5)"} -!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : {{.*}}, {{.*}}) map_clauses(tofrom) capture(ByRef) members(%[[MEMBER_MAP]] : [2, 2] : !fir.ref>) -> {{.*}} {name = "scalar_arr", partial_map = true} +!CHECK: %[[PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE]]#1 : {{.*}}, {{.*}}) map_clauses(storage) capture(ByRef) members(%[[MEMBER_MAP]] : [2, 2] : !fir.ref>) -> {{.*}} {name = "scalar_arr", partial_map = true} !CHECK: omp.target map_entries(%[[PARENT_MAP]] -> %[[ARG0:.*]], %[[MEMBER_MAP]] -> %[[ARG1:.*]] : {{.*}}, !fir.ref>) { subroutine mapType_derived_nested_explicit_member_with_bounds type :: nested @@ -184,9 +184,9 @@ subroutine mapType_derived_nested_explicit_member_with_bounds type(nested) :: nest integer(4) :: int end type scalar_and_array - - type(scalar_and_array) :: scalar_arr - + + type(scalar_and_array) :: scalar_arr + !$omp target map(tofrom: scalar_arr%nest%array(2:5)) scalar_arr%nest%array(3) = 3 !$omp end target @@ -202,8 +202,8 @@ end subroutine mapType_derived_nested_explicit_member_with_bounds !CHECK: %[[PARENT_2:.*]] = hlfir.designate %[[DECLARE_2]]#0{"nest"} : {{.*}} -> {{.*}} !CHECK: %[[MEMBER_2:.*]] = hlfir.designate %[[PARENT_2]]{"int"} : {{.*}} -> !fir.ref !CHECK: %[[MAP_MEMBER_2:.*]] = omp.map.info var_ptr(%[[MEMBER_2]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "scalar_arr2%nest%int"} -!CHECK: %[[MAP_PARENT_1:.*]] = omp.map.info var_ptr(%[[DECLARE_1]]#1 : {{.*}}) map_clauses(tofrom) capture(ByRef) members(%[[MAP_MEMBER_1]] : [2, 0] : !fir.ref) -> {{.*}} {name = "scalar_arr1", partial_map = true} -!CHECK: %[[MAP_PARENT_2:.*]] = omp.map.info var_ptr(%[[DECLARE_2]]#1 : {{.*}}) map_clauses(tofrom) capture(ByRef) members(%[[MAP_MEMBER_2]] : [2, 0] : !fir.ref) -> {{.*}} {name = "scalar_arr2", partial_map = true} +!CHECK: %[[MAP_PARENT_1:.*]] = omp.map.info var_ptr(%[[DECLARE_1]]#1 : {{.*}}) map_clauses(storage) capture(ByRef) members(%[[MAP_MEMBER_1]] : [2, 0] : !fir.ref) -> {{.*}} {name = "scalar_arr1", partial_map = true} +!CHECK: %[[MAP_PARENT_2:.*]] = omp.map.info var_ptr(%[[DECLARE_2]]#1 : {{.*}}) map_clauses(storage) capture(ByRef) members(%[[MAP_MEMBER_2]] : [2, 0] : !fir.ref) -> {{.*}} {name = "scalar_arr2", partial_map = true} !CHECK: omp.target map_entries(%[[MAP_PARENT_1]] -> %[[ARG0:.*]], %[[MAP_PARENT_2:.*]] -> %[[ARG1:.*]], %[[MAP_MEMBER_1]] -> %[[ARG2:.*]], %[[MAP_MEMBER_2]] -> %[[ARG3:.*]] : {{.*}}, {{.*}}, !fir.ref, !fir.ref) { subroutine mapType_multilpe_derived_nested_explicit_member type :: nested @@ -218,12 +218,12 @@ subroutine mapType_multilpe_derived_nested_explicit_member type(nested) :: nest integer(4) :: int end type scalar_and_array - + type(scalar_and_array) :: scalar_arr1 type(scalar_and_array) :: scalar_arr2 -!$omp target map(tofrom:scalar_arr1%nest%int, scalar_arr2%nest%int) - scalar_arr1%nest%int = 3 - scalar_arr2%nest%int = 2 -!$omp end target + !$omp target map(tofrom:scalar_arr1%nest%int, scalar_arr2%nest%int) + scalar_arr1%nest%int = 3 + scalar_arr2%nest%int = 2 + !$omp end target end subroutine mapType_multilpe_derived_nested_explicit_member diff --git a/flang/test/Lower/OpenMP/distribute.f90 b/flang/test/Lower/OpenMP/distribute.f90 index ea57d35b964b4..a4a753dddbac4 100644 --- a/flang/test/Lower/OpenMP/distribute.f90 +++ b/flang/test/Lower/OpenMP/distribute.f90 @@ -7,7 +7,7 @@ subroutine distribute_simple() ! CHECK: omp.teams !$omp teams - ! CHECK: omp.distribute private({{.*}}) { + ! CHECK: omp.distribute { !$omp distribute ! CHECK-NEXT: omp.loop_nest diff --git a/flang/test/Lower/OpenMP/has_device_addr-mapinfo.f90 b/flang/test/Lower/OpenMP/has_device_addr-mapinfo.f90 index e7bced4c0d29d..5a8b2b316dc69 100644 --- a/flang/test/Lower/OpenMP/has_device_addr-mapinfo.f90 +++ b/flang/test/Lower/OpenMP/has_device_addr-mapinfo.f90 @@ -17,7 +17,7 @@ integer function s(a) ! Check that the map.info for `a` only takes a single parameter. -!CHECK-DAG: %[[MAP_A:[0-9]+]] = "omp.map.info"(%[[STORAGE_A:[0-9#]+]]) <{map_capture_type = #omp, map_type = #omp, name = "a", operandSegmentSizes = array, partial_map = false, var_type = !fir.box>}> : (!fir.ref>>) -> !fir.ref> +!CHECK-DAG: %[[MAP_A:[0-9]+]] = "omp.map.info"(%[[STORAGE_A:[0-9#]+]]) <{map_capture_type = #omp, map_type = #omp, name = "a", operandSegmentSizes = array, partial_map = false, var_type = !fir.box>}> : (!fir.ref>>) -> !fir.ref> !CHECK-DAG: %[[MAP_T:[0-9]+]] = "omp.map.info"(%[[STORAGE_T:[0-9#]+]]) <{map_capture_type = #omp, map_type = #omp, name = "t", operandSegmentSizes = array, partial_map = false, var_type = i32}> : (!fir.ref) -> !fir.ref !CHECK: "omp.target"(%[[MAP_A]], %[[MAP_T]]) diff --git a/flang/test/Lower/OpenMP/hlfir-to-fir-conv-omp.mlir b/flang/test/Lower/OpenMP/hlfir-to-fir-conv-omp.mlir new file mode 100644 index 0000000000000..f3775d3273657 --- /dev/null +++ b/flang/test/Lower/OpenMP/hlfir-to-fir-conv-omp.mlir @@ -0,0 +1,64 @@ +// Tests HLFIR-to-FIR conversion aspects relevant to OpenMP. For example, that +// the correct alloca block is chosen for OMP regions. + +// RUN: fir-opt --convert-hlfir-to-fir %s -o - | \ +// RUN: FileCheck %s + +fir.global internal @_QQro.1xi4.0(dense<42> : tensor<1xi32>) constant : !fir.array<1xi32> + +func.func @_QPfoo() { + %c1 = arith.constant 1 : index + %host_alloc = fir.alloca !fir.array<1xi32> {bindc_name = "arr", uniq_name = "_QFfooEarr"} + + %1 = fir.shape %c1 : (index) -> !fir.shape<1> + %host_decl:2 = hlfir.declare %host_alloc(%1) {uniq_name = "_QFfooEarr"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) + %map_info = omp.map.info var_ptr(%host_decl#1 : !fir.ref>, !fir.array<1xi32>) map_clauses(implicit, tofrom) capture(ByRef) -> !fir.ref> {name = "arr"} + + // CHECK: omp.target + omp.target map_entries(%map_info -> %arg1 : !fir.ref>) { + %c1_2 = arith.constant 1 : index + %21 = fir.shape %c1_2 : (index) -> !fir.shape<1> + + // CHECK: %[[TARGET_DECL:.*]] = fir.declare + %target_decl:2 = hlfir.declare %arg1(%21) {uniq_name = "_QFfooEarr"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) + + // CHECK: omp.teams + omp.teams { + %c1_3 = arith.constant 1 : i32 + %c10 = arith.constant 10 : i32 + + // CHECK: omp.parallel + omp.parallel { + // CHECK: %[[TO_BOX_ALLOC:.*]] = fir.alloca !fir.box> {pinned} + // CHECK: omp.distribute + omp.distribute { + // CHECK: omp.wsloop + omp.wsloop { + // CHECK: omp.loop_nest + omp.loop_nest (%arg2) : i32 = (%c1_3) to (%c10) inclusive step (%c1_3) { + %25 = fir.address_of(@_QQro.1xi4.0) : !fir.ref> + %26 = fir.shape %c1_2 : (index) -> !fir.shape<1> + %27:2 = hlfir.declare %25(%26) {fortran_attrs = #fir.var_attrs, uniq_name = "_QQro.1xi4.0"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) + + + // CHECK: %[[EMBOX:.*]] = fir.embox %[[TARGET_DECL]] + // CHECK: fir.store %[[EMBOX]] to %[[TO_BOX_ALLOC]] + // CHECK: %[[BOX_ALLOC_CONV:.*]] = fir.convert %[[TO_BOX_ALLOC]] : (!fir.ref>>) -> !fir.ref> + // CHECK: fir.call @_FortranAAssign(%[[BOX_ALLOC_CONV]], {{.*}}) + hlfir.assign %27#0 to %target_decl#0 : !fir.ref>, !fir.ref> + // CHECK: omp.yield + omp.yield + } + } {omp.composite} + } {omp.composite} + // CHECK: omp.terminator + omp.terminator + } {omp.composite} + // CHECK: omp.terminator + omp.terminator + } + // CHECK: omp.terminator + omp.terminator + } + return +} diff --git a/flang/test/Lower/OpenMP/host-eval.f90 b/flang/test/Lower/OpenMP/host-eval.f90 index fe5b9597f8620..c059f7338b26d 100644 --- a/flang/test/Lower/OpenMP/host-eval.f90 +++ b/flang/test/Lower/OpenMP/host-eval.f90 @@ -22,8 +22,10 @@ subroutine teams() !$omp end target - ! BOTH: omp.teams - ! BOTH-SAME: num_teams({{.*}}) thread_limit({{.*}}) { + ! HOST: omp.teams + ! HOST-SAME: num_teams({{.*}}) thread_limit({{.*}}) { + + ! DEVICE-NOT: omp.teams !$omp teams num_teams(1) thread_limit(2) call foo() !$omp end teams @@ -76,13 +78,18 @@ subroutine distribute_parallel_do() !$omp end distribute parallel do !$omp end target teams - ! BOTH: omp.teams + ! HOST: omp.teams + ! DEVICE-NOT: omp.teams !$omp teams - ! BOTH: omp.parallel - ! BOTH-SAME: num_threads({{.*}}) - ! BOTH: omp.distribute - ! BOTH-NEXT: omp.wsloop + ! HOST: omp.parallel + ! HOST-SAME: num_threads({{.*}}) + ! HOST: omp.distribute + ! HOST-NEXT: omp.wsloop + + ! DEVICE-NOT: omp.parallel + ! DEVICE-NOT: omp.distribute + ! DEVICE-NOT: omp.wsloop !$omp distribute parallel do num_threads(1) do i=1,10 call foo() @@ -140,14 +147,20 @@ subroutine distribute_parallel_do_simd() !$omp end distribute parallel do simd !$omp end target teams - ! BOTH: omp.teams + ! HOST: omp.teams + ! DEVICE-NOT: omp.teams !$omp teams - ! BOTH: omp.parallel - ! BOTH-SAME: num_threads({{.*}}) - ! BOTH: omp.distribute - ! BOTH-NEXT: omp.wsloop - ! BOTH-NEXT: omp.simd + ! HOST: omp.parallel + ! HOST-SAME: num_threads({{.*}}) + ! HOST: omp.distribute + ! HOST-NEXT: omp.wsloop + ! HOST-NEXT: omp.simd + + ! DEVICE-NOT: omp.parallel + ! DEVICE-NOT: omp.distribute + ! DEVICE-NOT: omp.wsloop + ! DEVICE-NOT: omp.simd !$omp distribute parallel do simd num_threads(1) do i=1,10 call foo() @@ -194,10 +207,12 @@ subroutine distribute() !$omp end distribute !$omp end target teams - ! BOTH: omp.teams + ! HOST: omp.teams + ! DEVICE-NOT: omp.teams !$omp teams - ! BOTH: omp.distribute + ! HOST: omp.distribute + ! DEVICE-NOT: omp.distribute !$omp distribute do i=1,10 call foo() @@ -246,11 +261,15 @@ subroutine distribute_simd() !$omp end distribute simd !$omp end target teams - ! BOTH: omp.teams + ! HOST: omp.teams + ! DEVICE-NOT: omp.teams !$omp teams - ! BOTH: omp.distribute - ! BOTH-NEXT: omp.simd + ! HOST: omp.distribute + ! HOST-NEXT: omp.simd + + ! DEVICE-NOT: omp.distribute + ! DEVICE-NOT: omp.simd !$omp distribute simd do i=1,10 call foo() diff --git a/flang/test/Lower/OpenMP/if-clause.f90 b/flang/test/Lower/OpenMP/if-clause.f90 index 3ae9018ae4d5d..9e8a41d0a5f69 100644 --- a/flang/test/Lower/OpenMP/if-clause.f90 +++ b/flang/test/Lower/OpenMP/if-clause.f90 @@ -11,7 +11,6 @@ program main ! TODO When they are supported, add tests for: ! - PARALLEL SECTIONS ! - PARALLEL WORKSHARE - ! - TARGET UPDATE ! - TASKLOOP ! - TASKLOOP SIMD @@ -1224,6 +1223,22 @@ program main i = 1 !$omp end target teams + ! ---------------------------------------------------------------------------- + ! TARGET UPDATE + ! ---------------------------------------------------------------------------- + + ! CHECK: omp.target_update + ! CHECK-NOT: if({{.*}}) + !$omp target update to(i) + + ! CHECK: omp.target_update + ! CHECK-SAME: if({{.*}}) + !$omp target update to(i) if(.true.) + + ! CHECK: omp.target_update + ! CHECK-SAME: if({{.*}}) + !$omp target update to(i) if(target update: .true.) + ! ---------------------------------------------------------------------------- ! TASK ! ---------------------------------------------------------------------------- diff --git a/flang/test/Lower/OpenMP/loop-lifetime.f90 b/flang/test/Lower/OpenMP/loop-lifetime.f90 new file mode 100644 index 0000000000000..bfee4290d79c4 --- /dev/null +++ b/flang/test/Lower/OpenMP/loop-lifetime.f90 @@ -0,0 +1,52 @@ +! This test checks the insertion of lifetime information for loop indices of +! OpenMP loop operations. +! RUN: %flang_fc1 -flang-experimental-hlfir -emit-llvm -fopenmp %s -o - | FileCheck %s +! REQUIRES: stableFlang + +! CHECK-LABEL: define void @wsloop_i32 +subroutine wsloop_i32() + ! CHECK: %[[I_PRIV:.*]] = alloca i32 + ! CHECK: %[[I:.*]] = alloca i32 + ! CHECK: %[[LASTITER:.*]] = alloca i32 + ! CHECK: %[[LB:.*]] = alloca i32 + ! CHECK: %[[UB:.*]] = alloca i32 + ! CHECK: %[[STRIDE:.*]] = alloca i32 + integer :: i + + ! CHECK: call void @llvm.lifetime.start.p0(i64 4, ptr %[[I_PRIV]]) + ! CHECK-NEXT: br label %[[WSLOOP_BLOCK:.*]] + ! CHECK: [[WSLOOP_BLOCK]]: + ! CHECK-NOT: {{^.*}}: + ! CHECK: br label %[[CONT_BLOCK:.*]] + ! CHECK: [[CONT_BLOCK]]: + ! CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr %[[I_PRIV]]) + !$omp do + do i = 1, 10 + print *, i + end do + !$omp end do +end subroutine + +! CHECK-LABEL: define void @wsloop_i64 +subroutine wsloop_i64() + ! CHECK-DAG: %[[I_PRIV:.*]] = alloca i64 + ! CHECK-DAG: %[[I:.*]] = alloca i64 + ! CHECK-DAG: %[[LASTITER:.*]] = alloca i32 + ! CHECK-DAG: %[[LB:.*]] = alloca i64 + ! CHECK-DAG: %[[UB:.*]] = alloca i64 + ! CHECK-DAG: %[[STRIDE:.*]] = alloca i64 + integer*8 :: i + + ! CHECK: call void @llvm.lifetime.start.p0(i64 8, ptr %[[I_PRIV]]) + ! CHECK-NEXT: br label %[[WSLOOP_BLOCK:.*]] + ! CHECK: [[WSLOOP_BLOCK]]: + ! CHECK-NOT: {{^.*}}: + ! CHECK: br label %[[CONT_BLOCK:.*]] + ! CHECK: [[CONT_BLOCK]]: + ! CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr %[[I_PRIV]]) + !$omp do + do i = 1, 10 + print *, i + end do + !$omp end do +end subroutine diff --git a/flang/test/Lower/OpenMP/map-component-ref.f90 b/flang/test/Lower/OpenMP/map-component-ref.f90 index b7a7ee06b02f2..228d682d32830 100644 --- a/flang/test/Lower/OpenMP/map-component-ref.f90 +++ b/flang/test/Lower/OpenMP/map-component-ref.f90 @@ -6,7 +6,7 @@ ! CHECK: %[[V1:[0-9]+]]:2 = hlfir.declare %[[V0]] {uniq_name = "_QFfoo1Ea"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[V2:[0-9]+]] = hlfir.designate %[[V1]]#0{"a1"} : (!fir.ref>) -> !fir.ref ! CHECK: %[[V3:[0-9]+]] = omp.map.info var_ptr(%[[V2]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "a%a1"} -! CHECK: %[[V4:[0-9]+]] = omp.map.info var_ptr(%[[V1]]#1 : !fir.ref>, !fir.type<_QFfoo1Tt0{a0:i32,a1:i32}>) map_clauses(tofrom) capture(ByRef) members(%[[V3]] : [1] : !fir.ref) -> !fir.ref> {name = "a", partial_map = true} +! CHECK: %[[V4:[0-9]+]] = omp.map.info var_ptr(%[[V1]]#1 : !fir.ref>, !fir.type<_QFfoo1Tt0{a0:i32,a1:i32}>) map_clauses(storage) capture(ByRef) members(%[[V3]] : [1] : !fir.ref) -> !fir.ref> {name = "a", partial_map = true} ! CHECK: omp.target map_entries(%[[V4]] -> %arg0, %[[V3]] -> %arg1 : !fir.ref>, !fir.ref) { ! CHECK: %[[V5:[0-9]+]]:2 = hlfir.declare %arg0 {uniq_name = "_QFfoo1Ea"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK: %c0_i32 = arith.constant 0 : i32 diff --git a/flang/test/Lower/OpenMP/map-descriptor-deferral.f90 b/flang/test/Lower/OpenMP/map-descriptor-deferral.f90 index daea2f321414f..06b81ddc7d522 100644 --- a/flang/test/Lower/OpenMP/map-descriptor-deferral.f90 +++ b/flang/test/Lower/OpenMP/map-descriptor-deferral.f90 @@ -1,5 +1,4 @@ !RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s - ! This test checks that the descriptor deferral behaviour of the ! MapInfoFinalization pass is preserved. Descriptor deferral is the ! act of removing the mapping of the descriptor in certain cases when @@ -23,7 +22,7 @@ subroutine assume_map_target_enter_exit(assumed_arr) !CHECK: omp.target_enter_data map_entries(%[[MAP_ADDR]] : !fir.ref>) !CHECK: %[[BOX_ADDR:.*]] = fir.box_offset %{{.*}} base_addr : (!fir.ref>>) -> !fir.llvm_ptr>> !CHECK: %[[MAP_ADDR:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>, i32) map_clauses(implicit, tofrom) capture(ByRef) var_ptr_ptr(%[[BOX_ADDR]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {name = ""} -!CHECK: %[[MAP_BOX:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>, !fir.box>) map_clauses(implicit, to) capture(ByRef) members(%{{.*}} : [0] : !fir.llvm_ptr>>) -> !fir.ref> {name = "assumed_arr"} +!CHECK: %[[MAP_BOX:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>, !fir.box>) map_clauses(always, implicit, descriptor, to) capture(ByRef) members(%{{.*}} : [0] : !fir.llvm_ptr>>) -> !fir.ref> {name = "assumed_arr"} !CHECK: omp.target map_entries(%[[MAP_BOX]] -> %{{.*}}, %[[MAP_ADDR]] -> %{{.*}} : !fir.ref>, !fir.llvm_ptr>>) { !CHECK: %[[BOX_ADDR:.*]] = fir.box_offset %{{.*}} base_addr : (!fir.ref>>) -> !fir.llvm_ptr>> !CHECK: %[[LOAD_BOX:.*]] = fir.load %[[BOX_ADDR]] : !fir.llvm_ptr>> @@ -42,11 +41,11 @@ subroutine assume_alloca_map_target_enter_exit(assumed_arr) !CHECK-LABEL: func.func @_QPassume_alloca_map_target_enter_exit( !CHECK: %[[BOX_ADDR:.*]] = fir.box_offset %{{.*}} base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> !CHECK: %[[BOX_ADDR_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, i32) map_clauses(to) capture(ByRef) var_ptr_ptr(%[[BOX_ADDR]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {name = ""} -!CHECK: %[[DESC_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) members(%[[BOX_ADDR_MAP]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "assumed_arr"} +!CHECK: %[[DESC_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[BOX_ADDR_MAP]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "assumed_arr"} !CHECK: omp.target_enter_data map_entries(%[[DESC_MAP]], %[[BOX_ADDR_MAP]] : !fir.ref>>>, !fir.llvm_ptr>>) !CHECK: %[[BOX_ADDR:.*]] = fir.box_offset %{{.*}} base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> !CHECK: %[[BOX_ADDR_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, i32) map_clauses(implicit, tofrom) capture(ByRef) var_ptr_ptr(%[[BOX_ADDR]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {name = ""} -!CHECK: %[[DESC_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(implicit, to) capture(ByRef) members(%[[BOX_ADDR_MAP]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "assumed_arr"} +!CHECK: %[[DESC_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(always, implicit, descriptor, to) capture(ByRef) members(%[[BOX_ADDR_MAP]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "assumed_arr"} !CHECK: omp.target map_entries(%[[DESC_MAP]] -> %[[VAL_28:.*]], %[[BOX_ADDR_MAP]] -> %[[VAL_29:.*]] : !fir.ref>>>, !fir.llvm_ptr>>) { !CHECK: %[[BOX_ADDR:.*]] = fir.box_offset %{{.*}} base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> !CHECK: %[[BOX_ADDR_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, i32) map_clauses(from) capture(ByRef) var_ptr_ptr(%[[BOX_ADDR]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {name = ""} @@ -65,11 +64,11 @@ subroutine assume_pointer_map_target_enter_exit(assumed_arr) !CHECK-LABEL: func.func @_QPassume_pointer_map_target_enter_exit( !CHECK: %[[BOX_ADDR:.*]] = fir.box_offset %{{.*}} base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> !CHECK: %[[BOX_ADDR_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, i32) map_clauses(to) capture(ByRef) var_ptr_ptr(%[[BOX_ADDR]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {name = ""} -!CHECK: %[[DESC_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) members(%[[BOX_ADDR_MAP]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "assumed_arr"} +!CHECK: %[[DESC_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[BOX_ADDR_MAP]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "assumed_arr"} !CHECK: omp.target_enter_data map_entries(%[[DESC_MAP]], %[[BOX_ADDR_MAP]] : !fir.ref>>>, !fir.llvm_ptr>>) !CHECK: %[[BOX_ADDR:.*]] = fir.box_offset %{{.*}} base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> !CHECK: %[[BOX_ADDR_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, i32) map_clauses(implicit, tofrom) capture(ByRef) var_ptr_ptr(%[[BOX_ADDR]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {name = ""} -!CHECK: %[[DESC_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(implicit, to) capture(ByRef) members(%[[BOX_ADDR_MAP]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "assumed_arr"} +!CHECK: %[[DESC_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, !fir.box>>) map_clauses(always, implicit, descriptor, to) capture(ByRef) members(%[[BOX_ADDR_MAP]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> {name = "assumed_arr"} !CHECK: omp.target map_entries(%[[DESC_MAP]] -> %[[VAL_28:.*]], %[[BOX_ADDR_MAP]] -> %[[VAL_29:.*]] : !fir.ref>>>, !fir.llvm_ptr>>) { !CHECK: %[[BOX_ADDR:.*]] = fir.box_offset %{{.*}} base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> !CHECK: %[[BOX_ADDR_MAP:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>>, i32) map_clauses(from) capture(ByRef) var_ptr_ptr(%[[BOX_ADDR]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {name = ""} @@ -88,9 +87,9 @@ subroutine assume_map_target_data(assumed_arr) !CHECK-LABEL: func.func @_QPassume_map_target_data( !CHECK: %[[BOX_ADDR:.*]] = fir.box_offset %{{.*}} base_addr : (!fir.ref>>) -> !fir.llvm_ptr>> !CHECK: %[[MAP_ADDR:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>, i32) map_clauses(to) capture(ByRef) var_ptr_ptr(%[[BOX_ADDR]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {name = ""} -!CHECK: %[[MAP_BOX:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>, !fir.box>) map_clauses(to) capture(ByRef) members(%[[MAP_ADDR]] : [0] : !fir.llvm_ptr>>) -> !fir.ref> {name = "assumed_arr"} +!CHECK: %[[MAP_BOX:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>, !fir.box>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[MAP_ADDR]] : [0] : !fir.llvm_ptr>>) -> !fir.ref> {name = "assumed_arr"} !CHECK: omp.target_data map_entries(%[[MAP_BOX]], %[[MAP_ADDR]] : !fir.ref>, !fir.llvm_ptr>>) { !CHECK: %[[BOX_ADDR:.*]] = fir.box_offset %{{.*}} base_addr : (!fir.ref>>) -> !fir.llvm_ptr>> !CHECK: %[[MAP_ADDR:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>, i32) map_clauses(implicit, tofrom) capture(ByRef) var_ptr_ptr(%[[BOX_ADDR]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {name = ""} -!CHECK: %[[MAP_BOX:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>, !fir.box>) map_clauses(implicit, to) capture(ByRef) members(%[[MAP_ADDR]] : [0] : !fir.llvm_ptr>>) -> !fir.ref> {name = "assumed_arr"} +!CHECK: %[[MAP_BOX:.*]] = omp.map.info var_ptr(%{{.*}} : !fir.ref>>, !fir.box>) map_clauses(always, implicit, descriptor, to) capture(ByRef) members(%[[MAP_ADDR]] : [0] : !fir.llvm_ptr>>) -> !fir.ref> {name = "assumed_arr"} !CHECK: omp.target map_entries(%[[MAP_BOX]] -> %{{.*}}, %[[MAP_ADDR]] -> %{{.*}} : !fir.ref>, !fir.llvm_ptr>>) { diff --git a/flang/test/Lower/OpenMP/map-neg-alloca-derived-type-array.f90 b/flang/test/Lower/OpenMP/map-neg-alloca-derived-type-array.f90 index dd8721b97dccd..7ad8605144038 100644 --- a/flang/test/Lower/OpenMP/map-neg-alloca-derived-type-array.f90 +++ b/flang/test/Lower/OpenMP/map-neg-alloca-derived-type-array.f90 @@ -1,5 +1,5 @@ !RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s - +! XFAIL: * subroutine map_negative_bounds_allocatable_dtype() type derived_type real(4), pointer :: data(:,:,:) => null() diff --git a/flang/test/Lower/OpenMP/optional-argument-map-2.f90 b/flang/test/Lower/OpenMP/optional-argument-map-2.f90 index 791d509028dee..10690801a762f 100644 --- a/flang/test/Lower/OpenMP/optional-argument-map-2.f90 +++ b/flang/test/Lower/OpenMP/optional-argument-map-2.f90 @@ -1,4 +1,5 @@ -!RUN: %flang_fc1 -emit-hlfir -fopenmp -mmlir --enable-delayed-privatization-staging=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FPRIV +! NOTE: Do not check for false delayed privatization flag until all enable-delayed-privatization flags are switched on in amd-staging +!RUN %flang_fc1 -emit-hlfir -fopenmp -mmlir --enable-delayed-privatization-staging=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FPRIV !RUN: %flang_fc1 -emit-hlfir -fopenmp -mmlir --enable-delayed-privatization-staging=true %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPRIV module mod diff --git a/flang/test/Lower/OpenMP/optional-argument-map-3.f90 b/flang/test/Lower/OpenMP/optional-argument-map-3.f90 index 7e2a24e31123e..1c3cc50d32d67 100644 --- a/flang/test/Lower/OpenMP/optional-argument-map-3.f90 +++ b/flang/test/Lower/OpenMP/optional-argument-map-3.f90 @@ -1,5 +1,5 @@ !RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s - +!XFAIL: * module mod contains subroutine foo(dt, switch) diff --git a/flang/test/Lower/OpenMP/order-clause.f90 b/flang/test/Lower/OpenMP/order-clause.f90 index d5799079b3759..1f678e02708da 100644 --- a/flang/test/Lower/OpenMP/order-clause.f90 +++ b/flang/test/Lower/OpenMP/order-clause.f90 @@ -61,15 +61,15 @@ end subroutine do_simd_order_parallel subroutine distribute_order - !CHECK: omp.distribute order(reproducible:concurrent) private({{.*}}) { + !CHECK: omp.distribute order(reproducible:concurrent) { !$omp teams distribute order(concurrent) do i=1,10 end do - !CHECK: omp.distribute order(reproducible:concurrent) private({{.*}}) { + !CHECK: omp.distribute order(reproducible:concurrent) { !$omp teams distribute order(reproducible:concurrent) do i=1,10 end do - !CHECK: omp.distribute order(unconstrained:concurrent) private({{.*}}) { + !CHECK: omp.distribute order(unconstrained:concurrent) { !$omp teams distribute order(unconstrained:concurrent) do i = 1, 10 end do diff --git a/flang/test/Lower/OpenMP/parallel-reduction-array.f90 b/flang/test/Lower/OpenMP/parallel-reduction-array.f90 index 59595de338d50..e8c798351324c 100644 --- a/flang/test/Lower/OpenMP/parallel-reduction-array.f90 +++ b/flang/test/Lower/OpenMP/parallel-reduction-array.f90 @@ -2,8 +2,7 @@ ! RUN: %flang_fc1 -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s --check-prefix=CPU ! RUN: bbc -emit-hlfir -fopenmp -fopenmp-is-target-device -fopenmp-is-gpu -o - %s 2>&1 | FileCheck %s --check-prefix=GPU -! RUN: %if amdgpu-registered-target %{ %flang_fc1 -triple amdgcn-amd-amdhsa -emit-hlfir -fopenmp -fopenmp-is-target-device -o - %s 2>&1 | \ -! RUN: FileCheck %s --check-prefix=GPU %} +! RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-hlfir -fopenmp -fopenmp-is-target-device -o - %s 2>&1 | FileCheck %s --check-prefix=GPU program reduce integer, dimension(3) :: i = 0 diff --git a/flang/test/Lower/OpenMP/real10.f90 b/flang/test/Lower/OpenMP/real10.f90 index a31d2ace80044..c76c2bde0f6f6 100644 --- a/flang/test/Lower/OpenMP/real10.f90 +++ b/flang/test/Lower/OpenMP/real10.f90 @@ -5,9 +5,6 @@ !CHECK: hlfir.declare %{{.*}} {uniq_name = "_QFEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) program p + !$omp declare target real(10) :: x - !$omp target - continue - !$omp end target end - diff --git a/flang/test/Lower/OpenMP/reduction-target-spmd.f90 b/flang/test/Lower/OpenMP/reduction-target-spmd.f90 new file mode 100644 index 0000000000000..353c540c3bbf3 --- /dev/null +++ b/flang/test/Lower/OpenMP/reduction-target-spmd.f90 @@ -0,0 +1,15 @@ +! RUN: %flang_fc1 -emit-fir -fopenmp -o - %s | FileCheck %s +! RUN: bbc -emit-fir -fopenmp -o - %s | FileCheck %s + +! CHECK: omp.teams +! CHECK-SAME: reduction(@add_reduction_i32 %{{.*}} -> %{{.*}} : !fir.ref) +subroutine myfun() + integer :: i, j + i = 0 + j = 0 + !$omp target teams distribute parallel do reduction(+:i) + do j = 1,5 + i = i + j + end do + !$omp end target teams distribute parallel do +end subroutine myfun diff --git a/flang/test/Lower/OpenMP/reduction_var_map.f90 b/flang/test/Lower/OpenMP/reduction_var_map.f90 new file mode 100644 index 0000000000000..60a75dbfb39f8 --- /dev/null +++ b/flang/test/Lower/OpenMP/reduction_var_map.f90 @@ -0,0 +1,43 @@ +!RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s + +! This test checks that if reduction clause is on a combined target +! construct, there is an implicit map(tofrom) for each reduction variable. + +! construct with target +subroutine omp_target_combined + implicit none + integer(kind = 8) :: s1 + integer(kind = 8) :: s2 + integer(kind = 4) :: i + s1 = 1 + s2 = 1 + !$omp target teams distribute parallel do reduction(+:s1) reduction(+:s2) + do i=1,1000 + s1 = s1 + i + s2 = s2 + i + end do + !$omp end target teams distribute parallel do + return +end subroutine omp_target_combined +!CHECK-LABEL: func.func @_QPomp_target_combined() { +!CHECK: omp.map.info var_ptr({{.*}} : !fir.ref, i64) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "s1"} +!CHECK: omp.map.info var_ptr({{.*}} : !fir.ref, i64) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "s2"} +!CHECK: omp.map.info var_ptr({{.*}} : !fir.ref, i32) map_clauses(implicit) capture(ByCopy) -> !fir.ref {name = "i"} + +subroutine omp_target_team_separate + implicit none + integer(kind = 8) :: s3 + integer i + s3 = 1 + !$omp target + s3 = 2 + !$omp teams distribute parallel do reduction(+:s3) + do i=1,1000 + s3 = s3 + i + end do + !$omp end teams distribute parallel do + !$omp end target + return +end subroutine omp_target_team_separate +!CHECK-LABEL: func.func @_QPomp_target_team_separate() { +!CHECK: omp.map.info var_ptr({{.*}} : !fir.ref, i64) map_clauses(to) capture(ByCopy) -> !fir.ref diff --git a/flang/test/Lower/OpenMP/rtl-flags.f90 b/flang/test/Lower/OpenMP/rtl-flags.f90 index 8b0db59264792..353a785415860 100644 --- a/flang/test/Lower/OpenMP/rtl-flags.f90 +++ b/flang/test/Lower/OpenMP/rtl-flags.f90 @@ -20,7 +20,7 @@ !RUN: bbc -emit-hlfir -fopenmp -fopenmp-assume-no-nested-parallelism -fopenmp-is-target-device -o - %s | FileCheck %s --check-prefix=NEST-PAR-DEVICE-FIR !RUN: bbc -emit-hlfir -fopenmp -fopenmp-target-debug=1 -fopenmp-assume-teams-oversubscription -fopenmp-assume-no-nested-parallelism -fopenmp-assume-threads-oversubscription -fopenmp-assume-no-thread-state -fopenmp-is-target-device -o - %s | FileCheck %s --check-prefix=ALL-DEVICE-FIR -!DEFAULT-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags +!DEFAULT-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags !DEFAULT-DEVICE-FIR-SAME: omp.is_target_device = true !DEFAULT-DEVICE-FIR-VERSION: module attributes {{{.*}}omp.flags = #omp.flags !DEFAULT-DEVICE-FIR-VERSION-SAME: omp.is_target_device = true @@ -28,12 +28,12 @@ !DEFAULT-HOST-FIR: module attributes {{{.*}}omp.is_target_device = false{{.*}} !DEFAULT-HOST-FIR-VERSION: module attributes {{{.*}}omp.is_target_device = false !DEFAULT-HOST-FIR-VERSION-SAME: omp.version = #omp.version -!DBG-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!DBG-EQ-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!TEAMS-OSUB-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!THREAD-OSUB-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!THREAD-STATE-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!NEST-PAR-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!ALL-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags +!DBG-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags +!DBG-EQ-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags +!TEAMS-OSUB-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags +!THREAD-OSUB-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags +!THREAD-STATE-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags +!NEST-PAR-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags +!ALL-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags subroutine omp_subroutine() end subroutine omp_subroutine diff --git a/flang/test/Lower/OpenMP/sections-array-reduction.f90 b/flang/test/Lower/OpenMP/sections-array-reduction.f90 index 2f2808cebfc0c..5f9bcb6412a79 100644 --- a/flang/test/Lower/OpenMP/sections-array-reduction.f90 +++ b/flang/test/Lower/OpenMP/sections-array-reduction.f90 @@ -23,9 +23,6 @@ subroutine sectionsReduction(x) ! CHECK-LABEL: } combiner { ! [...] ! CHECK: omp.yield -! CHECK-LABEL: } cleanup { -! [...] -! CHECK: omp.yield ! CHECK: } ! CHECK-LABEL: func.func @_QPsectionsreduction( diff --git a/flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90 b/flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90 index 0d4fd964b71ec..d5311d7f1a6dc 100644 --- a/flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90 +++ b/flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90 @@ -1,5 +1,5 @@ ! This test checks the lowering and application of default map types for the target enter/exit data constructs and map clauses - +! XFAIL: * !RUN: %flang -fc1 -emit-fir -fopenmp -fopenmp-version=52 -o - %s | FileCheck %s --check-prefix=CHECK-52 !RUN: not %flang -fc1 -emit-fir -fopenmp -fopenmp-version=51 -o - %s 2>&1| FileCheck %s --check-prefix=CHECK-51 diff --git a/flang/test/Lower/OpenMP/target-generic-spmd.f90 b/flang/test/Lower/OpenMP/target-generic-spmd.f90 new file mode 100644 index 0000000000000..d6cd8ae229b3a --- /dev/null +++ b/flang/test/Lower/OpenMP/target-generic-spmd.f90 @@ -0,0 +1,191 @@ +! RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s + +! CHECK-LABEL: func.func @_QPdistribute_generic() { +subroutine distribute_generic() + ! CHECK: omp.target + ! CHECK-NOT: host_eval({{.*}}) + ! CHECK-SAME: { + !$omp target + !$omp teams + !$omp distribute + do i = 1, 10 + call foo(i) + end do + !$omp end distribute + call bar() !< Prevents this from being Generic-SPMD. + !$omp end teams + !$omp end target + + ! CHECK: omp.target + ! CHECK-NOT: host_eval({{.*}}) + ! CHECK-SAME: { + !$omp target teams + !$omp distribute + do i = 1, 10 + call foo(i) + end do + !$omp end distribute + call bar() !< Prevents this from being Generic-SPMD. + !$omp end target teams + + ! CHECK: omp.target + ! CHECK-NOT: host_eval({{.*}}) + ! CHECK-SAME: { + !$omp target teams + !$omp distribute + do i = 1, 10 + call foo(i) + end do + !$omp end distribute + + !$omp distribute + do i = 1, 10 + call foo(i) + end do + !$omp end distribute + !$omp end target teams +end subroutine distribute_generic + +! CHECK-LABEL: func.func @_QPdistribute_spmd() { +subroutine distribute_spmd() + ! CHECK: omp.target + ! CHECK-SAME: host_eval({{.*}}) + !$omp target + !$omp teams + !$omp distribute + do i = 1, 10 + call foo(i) + end do + !$omp end distribute + !$omp end teams + !$omp end target + + ! CHECK: omp.target + ! CHECK-SAME: host_eval({{.*}}) + !$omp target teams + !$omp distribute + do i = 1, 10 + call foo(i) + end do + !$omp end distribute + !$omp end target teams +end subroutine distribute_spmd + +! CHECK-LABEL: func.func @_QPdistribute_simd_generic() { +subroutine distribute_simd_generic() + ! CHECK: omp.target + ! CHECK-NOT: host_eval({{.*}}) + ! CHECK-SAME: { + !$omp target + !$omp teams + !$omp distribute simd + do i = 1, 10 + call foo(i) + end do + !$omp end distribute simd + call bar() !< Prevents this from being Generic-SPMD. + !$omp end teams + !$omp end target + + ! CHECK: omp.target + ! CHECK-NOT: host_eval({{.*}}) + ! CHECK-SAME: { + !$omp target teams + !$omp distribute simd + do i = 1, 10 + call foo(i) + end do + !$omp end distribute simd + call bar() !< Prevents this from being Generic-SPMD. + !$omp end target teams + + ! CHECK: omp.target + ! CHECK-NOT: host_eval({{.*}}) + ! CHECK-SAME: { + !$omp target teams + !$omp distribute simd + do i = 1, 10 + call foo(i) + end do + !$omp end distribute simd + + !$omp distribute simd + do i = 1, 10 + call foo(i) + end do + !$omp end distribute simd + !$omp end target teams +end subroutine distribute_simd_generic + +! CHECK-LABEL: func.func @_QPdistribute_simd_spmd() { +subroutine distribute_simd_spmd() + ! CHECK: omp.target + ! CHECK-SAME: host_eval({{.*}}) + !$omp target + !$omp teams + !$omp distribute simd + do i = 1, 10 + call foo(i) + end do + !$omp end distribute simd + !$omp end teams + !$omp end target + + ! CHECK: omp.target + ! CHECK-SAME: host_eval({{.*}}) + !$omp target teams + !$omp distribute simd + do i = 1, 10 + call foo(i) + end do + !$omp end distribute simd + !$omp end target teams +end subroutine distribute_simd_spmd + +! CHECK-LABEL: func.func @_QPteams_distribute_spmd() { +subroutine teams_distribute_spmd() + ! CHECK: omp.target + ! CHECK-SAME: host_eval({{.*}}) + !$omp target + !$omp teams distribute + do i = 1, 10 + call foo(i) + end do + !$omp end teams distribute + !$omp end target +end subroutine teams_distribute_spmd + +! CHECK-LABEL: func.func @_QPteams_distribute_simd_spmd() { +subroutine teams_distribute_simd_spmd() + ! CHECK: omp.target + ! CHECK-SAME: host_eval({{.*}}) + !$omp target + !$omp teams distribute simd + do i = 1, 10 + call foo(i) + end do + !$omp end teams distribute simd + !$omp end target +end subroutine teams_distribute_simd_spmd + +! CHECK-LABEL: func.func @_QPtarget_teams_distribute_spmd() { +subroutine target_teams_distribute_spmd() + ! CHECK: omp.target + ! CHECK-SAME: host_eval({{.*}}) + !$omp target teams distribute + do i = 1, 10 + call foo(i) + end do + !$omp end target teams distribute +end subroutine target_teams_distribute_spmd + +! CHECK-LABEL: func.func @_QPtarget_teams_distribute_simd_spmd() { +subroutine target_teams_distribute_simd_spmd() + ! CHECK: omp.target + ! CHECK-SAME: host_eval({{.*}}) + !$omp target teams distribute simd + do i = 1, 10 + call foo(i) + end do + !$omp end target teams distribute simd +end subroutine target_teams_distribute_simd_spmd diff --git a/flang/test/Lower/OpenMP/target-map-complex.f90 b/flang/test/Lower/OpenMP/target-map-complex.f90 index fc01bdafe51ed..acb2533fbed7c 100644 --- a/flang/test/Lower/OpenMP/target-map-complex.f90 +++ b/flang/test/Lower/OpenMP/target-map-complex.f90 @@ -1,4 +1,5 @@ -!RUN: %flang_fc1 -emit-hlfir -fopenmp -mmlir --enable-delayed-privatization-staging=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FPRIV +! NOTE: Do not check for false delayed privatization flag until all enable-delayed-privatization flags are switched on in amd-staging +!RUN %flang_fc1 -emit-hlfir -fopenmp -mmlir --enable-delayed-privatization-staging=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FPRIV !RUN: %flang_fc1 -emit-hlfir -fopenmp -mmlir --enable-delayed-privatization-staging=true %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPRIV ! Check that the complex*4 is passed by value. but complex*8 is passed by diff --git a/flang/test/Lower/OpenMP/target.f90 b/flang/test/Lower/OpenMP/target.f90 index 26bd62edf9d0c..b3b6d79c19ad6 100644 --- a/flang/test/Lower/OpenMP/target.f90 +++ b/flang/test/Lower/OpenMP/target.f90 @@ -1,5 +1,6 @@ ! The "thread_limit" clause was added to the "target" construct in OpenMP 5.1. -!RUN: %flang_fc1 -emit-hlfir -fopenmp -mmlir --enable-delayed-privatization-staging=false -fopenmp-version=51 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FPRIV +! NOTE: Do not check for false delayed privatization flag until all enable-delayed-privatization flags are switched on in amd-staging +!RUN %flang_fc1 -emit-hlfir -fopenmp -mmlir --enable-delayed-privatization-staging=false -fopenmp-version=51 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FPRIV !RUN: %flang_fc1 -emit-hlfir -fopenmp -mmlir --enable-delayed-privatization-staging=true -fopenmp-version=51 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPRIV !=============================================================================== @@ -549,9 +550,9 @@ subroutine omp_target_device_addr !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box> {bindc_name = "a", uniq_name = "_QFomp_target_device_addrEa"} !CHECK: %[[VAL_0_DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFomp_target_device_addrEa"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) !CHECK: %[[MAP_MEMBERS:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr({{.*}} : !fir.llvm_ptr>) -> !fir.llvm_ptr> {name = ""} - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>, !fir.box>) map_clauses(to) capture(ByRef) members(%[[MAP_MEMBERS]] : [0] : !fir.llvm_ptr>) -> !fir.ref>> {name = "a"} + !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>, !fir.box>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[MAP_MEMBERS]] : [0] : !fir.llvm_ptr>) -> !fir.ref>> {name = "a"} !CHECK: %[[DEV_ADDR_MEMBERS:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>, i32) map_clauses(return_param) capture(ByRef) var_ptr_ptr({{.*}} : !fir.llvm_ptr>) -> !fir.llvm_ptr> {name = ""} - !CHECK: %[[DEV_ADDR:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>, !fir.box>) map_clauses(to) capture(ByRef) members(%[[DEV_ADDR_MEMBERS]] : [0] : !fir.llvm_ptr>) -> !fir.ref>> {name = "a"} + !CHECK: %[[DEV_ADDR:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>, !fir.box>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[DEV_ADDR_MEMBERS]] : [0] : !fir.llvm_ptr>) -> !fir.ref>> {name = "a"} !CHECK: omp.target_data map_entries(%[[MAP]], %[[MAP_MEMBERS]] : {{.*}}) use_device_addr(%[[DEV_ADDR]] -> %[[ARG_0:.*]], %[[DEV_ADDR_MEMBERS]] -> %[[ARG_1:.*]] : !fir.ref>>, !fir.llvm_ptr>) { !$omp target data map(tofrom: a) use_device_addr(a) !CHECK: %[[VAL_1_DECL:.*]]:2 = hlfir.declare %[[ARG_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFomp_target_device_addrEa"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) diff --git a/flang/test/Lower/OpenMP/unroll-heuristic01.f90 b/flang/test/Lower/OpenMP/unroll-heuristic01.f90 index 34020eb727e55..441ddaf11686e 100644 --- a/flang/test/Lower/OpenMP/unroll-heuristic01.f90 +++ b/flang/test/Lower/OpenMP/unroll-heuristic01.f90 @@ -1,6 +1,5 @@ ! RUN: %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=51 -o - %s 2>&1 | FileCheck %s - subroutine omp_unroll_heuristic01(lb, ub, inc) integer res, i, lb, ub, inc @@ -51,4 +50,4 @@ end subroutine omp_unroll_heuristic01 ! CHECK: } ! CHECK: omp.unroll_heuristic(%[[VAL_23]]) ! CHECK: return -! CHECK: } \ No newline at end of file +! CHECK: } diff --git a/flang/test/Lower/OpenMP/unroll-heuristic02.f90 b/flang/test/Lower/OpenMP/unroll-heuristic02.f90 index fdb1366960b23..f3df1d2062173 100644 --- a/flang/test/Lower/OpenMP/unroll-heuristic02.f90 +++ b/flang/test/Lower/OpenMP/unroll-heuristic02.f90 @@ -1,6 +1,5 @@ ! RUN: %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=51 -o - %s 2>&1 | FileCheck %s - subroutine omp_unroll_heuristic_nested02(outer_lb, outer_ub, outer_inc, inner_lb, inner_ub, inner_inc) integer res, i, j, inner_lb, inner_ub, inner_inc, outer_lb, outer_ub, outer_inc diff --git a/flang/test/Lower/OpenMP/use-device-ptr-to-use-device-addr.f90 b/flang/test/Lower/OpenMP/use-device-ptr-to-use-device-addr.f90 index 8c1abad8eaa8d..f86f6cb0d90c0 100644 --- a/flang/test/Lower/OpenMP/use-device-ptr-to-use-device-addr.f90 +++ b/flang/test/Lower/OpenMP/use-device-ptr-to-use-device-addr.f90 @@ -1,12 +1,10 @@ ! The "use_device_addr" was added to the "target data" directive in OpenMP 5.0. ! RUN: %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=50 %s -o - | FileCheck %s ! RUN: bbc -emit-hlfir -fopenmp -fopenmp-version=50 %s -o - | FileCheck %s - ! This tests primary goal is to check the promotion of non-CPTR arguments from ! use_device_ptr to use_device_addr works, without breaking any functionality. !CHECK: func.func @{{.*}}only_use_device_ptr() - !CHECK: omp.target_data use_device_addr(%{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}} : !fir.ref>>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.llvm_ptr>>) use_device_ptr(%{{.*}} -> %{{.*}} : !fir.ref>) { subroutine only_use_device_ptr use iso_c_binding @@ -14,9 +12,9 @@ subroutine only_use_device_ptr real, pointer :: pa(:) type(c_ptr) :: cptr - !$omp target data use_device_ptr(pa, cptr, array) - !$omp end target data - end subroutine + !$omp target data use_device_ptr(pa, cptr, array) + !$omp end target data +end subroutine !CHECK: func.func @{{.*}}mix_use_device_ptr_and_addr() !CHECK: omp.target_data use_device_addr(%{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}} : !fir.ref>>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.llvm_ptr>>) use_device_ptr({{.*}} : !fir.ref>) { @@ -26,43 +24,43 @@ subroutine mix_use_device_ptr_and_addr real, pointer :: pa(:) type(c_ptr) :: cptr - !$omp target data use_device_ptr(pa, cptr) use_device_addr(array) - !$omp end target data - end subroutine + !$omp target data use_device_ptr(pa, cptr) use_device_addr(array) + !$omp end target data +end subroutine - !CHECK: func.func @{{.*}}only_use_device_addr() - !CHECK: omp.target_data use_device_addr(%{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}} : !fir.ref>>>, !fir.ref>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.llvm_ptr>>) { - subroutine only_use_device_addr - use iso_c_binding - integer, pointer, dimension(:) :: array - real, pointer :: pa(:) - type(c_ptr) :: cptr +!CHECK: func.func @{{.*}}only_use_device_addr() +!CHECK: omp.target_data use_device_addr(%{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}} : !fir.ref>>>, !fir.ref>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.llvm_ptr>>) { +subroutine only_use_device_addr + use iso_c_binding + integer, pointer, dimension(:) :: array + real, pointer :: pa(:) + type(c_ptr) :: cptr - !$omp target data use_device_addr(pa, cptr, array) - !$omp end target data - end subroutine + !$omp target data use_device_addr(pa, cptr, array) + !$omp end target data +end subroutine - !CHECK: func.func @{{.*}}mix_use_device_ptr_and_addr_and_map() - !CHECK: omp.target_data map_entries(%{{.*}}, %{{.*}} : !fir.ref, !fir.ref) use_device_addr(%{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}} : !fir.ref>>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.llvm_ptr>>) use_device_ptr(%{{.*}} : !fir.ref>) { - subroutine mix_use_device_ptr_and_addr_and_map - use iso_c_binding - integer :: i, j - integer, pointer, dimension(:) :: array - real, pointer :: pa(:) - type(c_ptr) :: cptr +!CHECK: func.func @{{.*}}mix_use_device_ptr_and_addr_and_map() +!CHECK: omp.target_data map_entries(%{{.*}}, %{{.*}} : !fir.ref, !fir.ref) use_device_addr(%{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}}, %{{.*}} -> %{{.*}} : !fir.ref>>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.llvm_ptr>>) use_device_ptr(%{{.*}} : !fir.ref>) { +subroutine mix_use_device_ptr_and_addr_and_map + use iso_c_binding + integer :: i, j + integer, pointer, dimension(:) :: array + real, pointer :: pa(:) + type(c_ptr) :: cptr - !$omp target data use_device_ptr(pa, cptr) use_device_addr(array) map(tofrom: i, j) - !$omp end target data - end subroutine + !$omp target data use_device_ptr(pa, cptr) use_device_addr(array) map(tofrom: i, j) + !$omp end target data +end subroutine - !CHECK: func.func @{{.*}}only_use_map() - !CHECK: omp.target_data map_entries(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : !fir.ref>>>, !fir.ref>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.llvm_ptr>>) { - subroutine only_use_map - use iso_c_binding - integer, pointer, dimension(:) :: array - real, pointer :: pa(:) - type(c_ptr) :: cptr +!CHECK: func.func @{{.*}}only_use_map() +!CHECK: omp.target_data map_entries(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : !fir.ref>>>, !fir.ref>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.llvm_ptr>>) { +subroutine only_use_map + use iso_c_binding + integer, pointer, dimension(:) :: array + real, pointer :: pa(:) + type(c_ptr) :: cptr - !$omp target data map(pa, cptr, array) - !$omp end target data - end subroutine + !$omp target data map(pa, cptr, array) + !$omp end target data +end subroutine diff --git a/flang/test/Lower/OpenMP/wsloop-linear.f90 b/flang/test/Lower/OpenMP/wsloop-linear.f90 new file mode 100644 index 0000000000000..200678e68fb43 --- /dev/null +++ b/flang/test/Lower/OpenMP/wsloop-linear.f90 @@ -0,0 +1,57 @@ +! This test checks lowering of OpenMP DO Directive (Worksharing) +! with linear clause +! XFAIL: * +! RUN: %flang_fc1 -fopenmp -emit-hlfir %s -o - 2>&1 | FileCheck %s + +!CHECK: %[[X_alloca:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFsimple_linearEx"} +!CHECK: %[[X:.*]]:2 = hlfir.declare %[[X_alloca]] {uniq_name = "_QFsimple_linearEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[const:.*]] = arith.constant 1 : i32 +subroutine simple_linear + implicit none + integer :: x, y, i + !CHECK: omp.wsloop linear(%[[X]]#0 = %[[const]] : !fir.ref) {{.*}} + !$omp do linear(x) + !CHECK: %[[LOAD:.*]] = fir.load %[[X]]#0 : !fir.ref + !CHECK: %[[const:.*]] = arith.constant 2 : i32 + !CHECK: %[[RESULT:.*]] = arith.addi %[[LOAD]], %[[const]] : i32 + do i = 1, 10 + y = x + 2 + end do + !$omp end do +end subroutine + + +!CHECK: %[[X_alloca:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFlinear_stepEx"} +!CHECK: %[[X:.*]]:2 = hlfir.declare %[[X_alloca]] {uniq_name = "_QFlinear_stepEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +subroutine linear_step + implicit none + integer :: x, y, i + !CHECK: %[[const:.*]] = arith.constant 4 : i32 + !CHECK: omp.wsloop linear(%[[X]]#0 = %[[const]] : !fir.ref) {{.*}} + !$omp do linear(x:4) + !CHECK: %[[LOAD:.*]] = fir.load %[[X]]#0 : !fir.ref + !CHECK: %[[const:.*]] = arith.constant 2 : i32 + !CHECK: %[[RESULT:.*]] = arith.addi %[[LOAD]], %[[const]] : i32 + do i = 1, 10 + y = x + 2 + end do + !$omp end do +end subroutine + +!CHECK: %[[A_alloca:.*]] = fir.alloca i32 {bindc_name = "a", uniq_name = "_QFlinear_exprEa"} +!CHECK: %[[A:.*]]:2 = hlfir.declare %[[A_alloca]] {uniq_name = "_QFlinear_exprEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[X_alloca:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFlinear_exprEx"} +!CHECK: %[[X:.*]]:2 = hlfir.declare %[[X_alloca]] {uniq_name = "_QFlinear_exprEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +subroutine linear_expr + implicit none + integer :: x, y, i, a + !CHECK: %[[LOAD_A:.*]] = fir.load %[[A]]#0 : !fir.ref + !CHECK: %[[const:.*]] = arith.constant 4 : i32 + !CHECK: %[[LINEAR_EXPR:.*]] = arith.addi %[[LOAD_A]], %[[const]] : i32 + !CHECK: omp.wsloop linear(%[[X]]#0 = %[[LINEAR_EXPR]] : !fir.ref) {{.*}} + !$omp do linear(x:a+4) + do i = 1, 10 + y = x + 2 + end do + !$omp end do +end subroutine diff --git a/flang/test/Lower/allocatable-polymorphic.f90 b/flang/test/Lower/allocatable-polymorphic.f90 index e6a8c5e025123..c4882294eec1c 100644 --- a/flang/test/Lower/allocatable-polymorphic.f90 +++ b/flang/test/Lower/allocatable-polymorphic.f90 @@ -1,6 +1,5 @@ ! RUN: bbc --use-desc-for-alloc=false -emit-hlfir %s -o - | FileCheck %s ! RUN: bbc --use-desc-for-alloc=false -emit-hlfir %s -o - | tco | FileCheck %s --check-prefix=LLVM - module poly type p1 integer :: a diff --git a/flang/test/Lower/volatile-openmp.f90 b/flang/test/Lower/volatile-openmp.f90 index d1a844eddd106..a80f111822f5c 100644 --- a/flang/test/Lower/volatile-openmp.f90 +++ b/flang/test/Lower/volatile-openmp.f90 @@ -1,6 +1,6 @@ ! RUN: bbc --strict-fir-volatile-verifier -fopenmp %s -o - | FileCheck %s type t - integer, pointer :: array(:) +integer, pointer :: array(:) end type integer, volatile, pointer :: array1(:) type(t), volatile :: container @@ -36,8 +36,8 @@ ! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_13]]#0, array : (!fir.ref>>}>, volatile>) -> !fir.ref>>> ! CHECK: %[[VAL_25:.*]] = fir.box_offset %[[VAL_24]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> ! CHECK: %[[VAL_26:.*]] = omp.map.info var_ptr(%[[VAL_24]] : !fir.ref>>>, i32) map_clauses(to) capture(ByRef) var_ptr_ptr(%[[VAL_25]] : !fir.llvm_ptr>>) bounds(%[[VAL_23]]) -> !fir.llvm_ptr>> {name = ""} -! CHECK: %[[VAL_27:.*]] = omp.map.info var_ptr(%[[VAL_24]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {name = "container%[[VAL_28:.*]]"} -! CHECK: %[[VAL_29:.*]] = omp.map.info var_ptr(%[[VAL_13]]#1 : !fir.ref>>}>, volatile>, !fir.type<_QFTt{array:!fir.box>>}>) map_clauses(to) capture(ByRef) members(%[[VAL_27]], %[[VAL_26]] : [0], [0, 0] : !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref>>}>, volatile> {name = "container", partial_map = true} +! CHECK: %[[VAL_27:.*]] = omp.map.info var_ptr(%[[VAL_24]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {name = "container%[[VAL_28:.*]]"} +! CHECK: %[[VAL_29:.*]] = omp.map.info var_ptr(%[[VAL_13]]#1 : !fir.ref>>}>, volatile>, !fir.type<_QFTt{array:!fir.box>>}>) map_clauses(storage) capture(ByRef) members(%[[VAL_27]], %[[VAL_26]] : [0], [0, 0] : !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref>>}>, volatile> {name = "container", partial_map = true} ! CHECK: omp.target_enter_data map_entries(%[[VAL_29]], %[[VAL_27]], %[[VAL_26]] : !fir.ref>>}>, volatile>, !fir.ref>>>, !fir.llvm_ptr>>) ! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_10]]#0 : !fir.ref>, volatile>, volatile> ! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_10]]#0 : !fir.ref>, volatile>, volatile> @@ -47,7 +47,7 @@ ! CHECK: %[[VAL_35:.*]] = omp.map.bounds lower_bound(%[[VAL_0]] : index) upper_bound(%[[VAL_34]] : index) extent(%[[VAL_33]]#1 : index) stride(%[[VAL_33]]#2 : index) start_idx(%[[VAL_32]]#0 : index) {stride_in_bytes = true} ! CHECK: %[[VAL_36:.*]] = fir.box_offset %[[VAL_10]]#1 base_addr : (!fir.ref>, volatile>, volatile>) -> !fir.llvm_ptr>> ! CHECK: %[[VAL_37:.*]] = omp.map.info var_ptr(%[[VAL_10]]#1 : !fir.ref>, volatile>, volatile>, i32) map_clauses(to) capture(ByRef) var_ptr_ptr(%[[VAL_36]] : !fir.llvm_ptr>>) bounds(%[[VAL_35]]) -> !fir.llvm_ptr>> {name = ""} -! CHECK: %[[VAL_38:.*]] = omp.map.info var_ptr(%[[VAL_10]]#1 : !fir.ref>, volatile>, volatile>, !fir.box>, volatile>) map_clauses(to) capture(ByRef) members(%[[VAL_37]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>, volatile>, volatile> {name = "array1"} +! CHECK: %[[VAL_38:.*]] = omp.map.info var_ptr(%[[VAL_10]]#1 : !fir.ref>, volatile>, volatile>, !fir.box>, volatile>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[VAL_37]] : [0] : !fir.llvm_ptr>>) -> !fir.ref>, volatile>, volatile> {name = "array1"} ! CHECK: omp.target_enter_data map_entries(%[[VAL_38]], %[[VAL_37]] : !fir.ref>, volatile>, volatile>, !fir.llvm_ptr>>) ! CHECK: return ! CHECK: } diff --git a/flang/test/Semantics/OpenMP/allocate02.f90 b/flang/test/Semantics/OpenMP/allocate02.f90 index 8f0579e810bb9..16a9c37330777 100644 --- a/flang/test/Semantics/OpenMP/allocate02.f90 +++ b/flang/test/Semantics/OpenMP/allocate02.f90 @@ -1,6 +1,6 @@ ! REQUIRES: openmp_runtime -! RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags +! RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags -fopenmp-version=50 ! OpenMP Version 5.0 ! 2.11.3 allocate Directive ! At most one allocator clause can appear on the allocate directive. diff --git a/flang/test/Semantics/OpenMP/allocate03.f90 b/flang/test/Semantics/OpenMP/allocate03.f90 index e35115f3897cc..3d500e6273c4c 100644 --- a/flang/test/Semantics/OpenMP/allocate03.f90 +++ b/flang/test/Semantics/OpenMP/allocate03.f90 @@ -1,6 +1,6 @@ ! REQUIRES: openmp_runtime -! RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags +! RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags -fopenmp-version=50 ! OpenMP Version 5.0 ! 2.11.3 allocate Directive ! A variable that is part of another variable (as an array or diff --git a/flang/test/Semantics/OpenMP/allocate05.f90 b/flang/test/Semantics/OpenMP/allocate05.f90 index b5f7864a42b92..2376ca72ca911 100644 --- a/flang/test/Semantics/OpenMP/allocate05.f90 +++ b/flang/test/Semantics/OpenMP/allocate05.f90 @@ -1,6 +1,6 @@ ! REQUIRES: openmp_runtime -! RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags +! RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags -fopenmp-version=50 ! OpenMP Version 5.0 ! 2.11.3 allocate Directive ! allocate directives that appear in a target region must specify an allocator diff --git a/flang/test/Semantics/OpenMP/allocate06.f90 b/flang/test/Semantics/OpenMP/allocate06.f90 index 9b57322bbadc6..fdfcf783c7445 100644 --- a/flang/test/Semantics/OpenMP/allocate06.f90 +++ b/flang/test/Semantics/OpenMP/allocate06.f90 @@ -1,6 +1,6 @@ ! REQUIRES: openmp_runtime -! RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags +! RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags -fopenmp-version=50 ! OpenMP Version 5.0 ! 2.11.3 allocate Directive ! List items specified in the allocate directive must not have the ALLOCATABLE attribute unless the directive is associated with an diff --git a/flang/test/Semantics/OpenMP/allocate09.f90 b/flang/test/Semantics/OpenMP/allocate09.f90 index 0f93a340fe1e4..a36037a5f2308 100644 --- a/flang/test/Semantics/OpenMP/allocate09.f90 +++ b/flang/test/Semantics/OpenMP/allocate09.f90 @@ -1,6 +1,6 @@ ! REQUIRES: openmp_runtime -! RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags +! RUN: %python %S/../test_errors.py %s %flang_fc1 %openmp_flags -fopenmp-version=50 ! OpenMP Version 5.0 ! 2.11.3 allocate Directive ! List items specified in an allocate directive that is associated diff --git a/flang/test/Semantics/OpenMP/allow-threadprivate-equivalence-1.f90 b/flang/test/Semantics/OpenMP/allow-threadprivate-equivalence-1.f90 new file mode 100644 index 0000000000000..f19f6bad14a84 --- /dev/null +++ b/flang/test/Semantics/OpenMP/allow-threadprivate-equivalence-1.f90 @@ -0,0 +1,28 @@ +!RUN: %python %S/../test_errors.py %s %flang -Werror -fopenmp -famd-allow-threadprivate-equivalence + +program equiv + implicit none + common/ba/a,b,c + common/bb/e,d,f + integer :: a,b,c + integer :: e,d,f + integer :: x,y,z + + !WARNING: Variable 'a' from common block 'ba' appears in an EQUIVALENCE statement and a THREADPRIVATE directive, which does not conform to the OpenMP API specification. + !$omp threadprivate(/ba/) + + equivalence (x,a) + + !$omp parallel num_threads(2) + x = -42 + !$omp masked + x = 42 + !$omp end masked + !$omp barrier + !$omp atomic update + a = a + 1 + !$omp end atomic + !$omp barrier + print *, a + !$omp end parallel +end program equiv diff --git a/flang/test/Semantics/OpenMP/allow-threadprivate-equivalence-2.f90 b/flang/test/Semantics/OpenMP/allow-threadprivate-equivalence-2.f90 new file mode 100644 index 0000000000000..7488f293a9f03 --- /dev/null +++ b/flang/test/Semantics/OpenMP/allow-threadprivate-equivalence-2.f90 @@ -0,0 +1,10 @@ +!RUN: %python %S/../test_errors.py %s %flang -Werror -fopenmp -famd-allow-threadprivate-equivalence + +subroutine f + integer, save :: y + integer :: x + !WARNING: Variable 'x' appears a THREADPRIVATE directive and an EQUIVALENCE statement, which does not conform to the OpenMP API specification. + !$omp threadprivate(x) + equivalence(x, y) +end + diff --git a/flang/test/Semantics/OpenMP/atomic.f90 b/flang/test/Semantics/OpenMP/atomic.f90 index 10b33a3ade22d..e4be810acc624 100644 --- a/flang/test/Semantics/OpenMP/atomic.f90 +++ b/flang/test/Semantics/OpenMP/atomic.f90 @@ -1,6 +1,6 @@ ! REQUIRES: openmp_runtime -! RUN: %python %S/../test_errors.py %s %flang -fopenmp %openmp_flags +! RUN: %python %S/../test_errors.py %s %flang -fopenmp %openmp_flags -fopenmp-version=31 use omp_lib ! Check OpenMP 2.13.6 atomic Construct diff --git a/flang/test/Semantics/OpenMP/combined-constructs.f90 b/flang/test/Semantics/OpenMP/combined-constructs.f90 index 3e9c65434f695..b445649912000 100644 --- a/flang/test/Semantics/OpenMP/combined-constructs.f90 +++ b/flang/test/Semantics/OpenMP/combined-constructs.f90 @@ -1,4 +1,4 @@ -! RUN: %python %S/../test_errors.py %s %flang -fopenmp +! RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=52 program main implicit none @@ -33,7 +33,6 @@ program main enddo !$omp end target parallel - !ERROR: 'variable-category' modifier is required !$omp target parallel defaultmap(tofrom) do i = 1, N a(i) = 3.14d0 @@ -80,7 +79,6 @@ program main enddo !$omp end target parallel do - !ERROR: 'variable-category' modifier is required !$omp target parallel do defaultmap(tofrom) do i = 1, N a(i) = 3.14d0 @@ -140,7 +138,6 @@ program main enddo !$omp end target teams - !ERROR: 'variable-category' modifier is required !$omp target teams defaultmap(tofrom) do i = 1, N a(i) = 3.14d0 @@ -240,7 +237,6 @@ program main enddo !$omp end target teams distribute - !ERROR: 'variable-category' modifier is required !$omp target teams distribute defaultmap(tofrom) do i = 1, N a(i) = 3.14d0 @@ -333,7 +329,6 @@ program main enddo !$omp end target teams distribute parallel do - !ERROR: 'variable-category' modifier is required !$omp target teams distribute parallel do defaultmap(tofrom) do i = 1, N a(i) = 3.14d0 @@ -433,7 +428,6 @@ program main enddo !$omp end target teams distribute parallel do simd - !ERROR: 'variable-category' modifier is required !$omp target teams distribute parallel do simd defaultmap(tofrom) do i = 1, N a(i) = 3.14d0 diff --git a/flang/test/Semantics/OpenMP/linear-clause01.f90 b/flang/test/Semantics/OpenMP/linear-clause01.f90 index 2f499ac892a48..973f4904d325b 100644 --- a/flang/test/Semantics/OpenMP/linear-clause01.f90 +++ b/flang/test/Semantics/OpenMP/linear-clause01.f90 @@ -16,14 +16,17 @@ end subroutine linear_clause_01 ! Case 2 subroutine linear_clause_02(arg_01, arg_02) + !WARNING: The 'modifier()' syntax is deprecated in OpenMP v5.2, use ' : modifier' instead !ERROR: The list item 'arg_01' specified without the REF 'linear-modifier' must be of INTEGER type !$omp declare simd linear(val(arg_01)) real, intent(in) :: arg_01(:) + !WARNING: The 'modifier()' syntax is deprecated in OpenMP v5.2, use ' : modifier' instead !ERROR: If the `linear-modifier` is REF or UVAL, the list item 'arg_02' must be a dummy argument without the VALUE attribute !$omp declare simd linear(uval(arg_02)) integer, value, intent(in) :: arg_02 + !WARNING: The 'modifier()' syntax is deprecated in OpenMP v5.2, use ' : modifier' instead !ERROR: If the `linear-modifier` is REF or UVAL, the list item 'var' must be a dummy argument without the VALUE attribute !ERROR: The list item `var` must be a dummy argument !ERROR: The list item `var` in a LINEAR clause must not be Cray Pointer or a variable with POINTER attribute @@ -34,6 +37,7 @@ end subroutine linear_clause_02 ! Case 3 subroutine linear_clause_03(arg) integer, intent(in) :: arg + !WARNING: The 'modifier()' syntax is deprecated in OpenMP v5.2, use ' : modifier' instead !ERROR: The list item `arg` specified with the REF 'linear-modifier' must be polymorphic variable, assumed-shape array, or a variable with the `ALLOCATABLE` attribute !ERROR: List item 'arg' present at multiple LINEAR clauses !ERROR: 'arg' appears in more than one data-sharing clause on the same OpenMP directive diff --git a/flang/test/Semantics/OpenMP/nested-barrier.f90 b/flang/test/Semantics/OpenMP/nested-barrier.f90 index 8565a09a18cd7..070964fbe8633 100644 --- a/flang/test/Semantics/OpenMP/nested-barrier.f90 +++ b/flang/test/Semantics/OpenMP/nested-barrier.f90 @@ -1,4 +1,4 @@ -! RUN: %python %S/../test_errors.py %s %flang_fc1 -fopenmp +! RUN: %python %S/../test_errors.py %s %flang_fc1 -fopenmp -fopenmp-version=50 ! OpenMP Version 4.5 ! Various checks with the nesting of BARRIER construct diff --git a/flang/test/Semantics/OpenMP/nested-master.f90 b/flang/test/Semantics/OpenMP/nested-master.f90 index 7e4bb32bb7be1..79e2864fd271d 100644 --- a/flang/test/Semantics/OpenMP/nested-master.f90 +++ b/flang/test/Semantics/OpenMP/nested-master.f90 @@ -1,4 +1,4 @@ -! RUN: %python %S/../test_errors.py %s %flang_fc1 -fopenmp +! RUN: %python %S/../test_errors.py %s %flang_fc1 -fopenmp -fopenmp-version=50 ! OpenMP Version 4.5 ! Various checks with the nesting of MASTER construct diff --git a/flang/test/Semantics/OpenMP/nested-teams.f90 b/flang/test/Semantics/OpenMP/nested-teams.f90 index 3c193ee00b950..a960caeb15110 100644 --- a/flang/test/Semantics/OpenMP/nested-teams.f90 +++ b/flang/test/Semantics/OpenMP/nested-teams.f90 @@ -1,4 +1,4 @@ -! RUN: %python %S/../test_errors.py %s %flang -fopenmp +! RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=50 ! OpenMP Version 5.0 ! Check OpenMP construct validity for the following directives: diff --git a/flang/test/Semantics/OpenMP/ordered-simd.f90 b/flang/test/Semantics/OpenMP/ordered-simd.f90 index 50560139ea24a..f46c46269fabd 100644 --- a/flang/test/Semantics/OpenMP/ordered-simd.f90 +++ b/flang/test/Semantics/OpenMP/ordered-simd.f90 @@ -1,4 +1,4 @@ -! RUN: %python %S/../test_errors.py %s %flang -fopenmp +! RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=50 ! OpenMP Version 4.5 ! Various checks with the ordered construct diff --git a/flang/test/Semantics/OpenMP/ordered01.f90 b/flang/test/Semantics/OpenMP/ordered01.f90 index 75968a6f5ee45..4938543ea7b56 100644 --- a/flang/test/Semantics/OpenMP/ordered01.f90 +++ b/flang/test/Semantics/OpenMP/ordered01.f90 @@ -1,4 +1,4 @@ -! RUN: %python %S/../test_errors.py %s %flang -fopenmp +! RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=51 ! OpenMP Version 5.1 ! Check OpenMP construct validity for the following directives: ! 2.19.9 Ordered Construct diff --git a/flang/test/Semantics/OpenMP/ordered03.f90 b/flang/test/Semantics/OpenMP/ordered03.f90 index 6a7037e2b750c..01d0f6338998a 100644 --- a/flang/test/Semantics/OpenMP/ordered03.f90 +++ b/flang/test/Semantics/OpenMP/ordered03.f90 @@ -1,4 +1,4 @@ -! RUN: %python %S/../test_errors.py %s %flang -fopenmp +! RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=51 ! OpenMP Version 5.1 ! Check OpenMP construct validity for the following directives: ! 2.19.9 Ordered Construct diff --git a/flang/test/Semantics/OpenMP/parallel-master-goto.f90 b/flang/test/Semantics/OpenMP/parallel-master-goto.f90 index 01d14aaa46d30..5167f6657ef00 100644 --- a/flang/test/Semantics/OpenMP/parallel-master-goto.f90 +++ b/flang/test/Semantics/OpenMP/parallel-master-goto.f90 @@ -1,4 +1,4 @@ -! RUN: %python %S/../test_errors.py %s %flang -fopenmp +! RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=50 ! Regression test for #143229 !$omp parallel diff --git a/flang/test/Semantics/OpenMP/symbol08.f90 b/flang/test/Semantics/OpenMP/symbol08.f90 index bf0f724669fa2..c803ec5ad8ab9 100644 --- a/flang/test/Semantics/OpenMP/symbol08.f90 +++ b/flang/test/Semantics/OpenMP/symbol08.f90 @@ -133,8 +133,8 @@ subroutine dotprod (b, c, n, block_size, num_teams, block_threads) !$omp teams num_teams(num_teams) thread_limit(block_threads) reduction(+: sum) !$omp distribute !DEF: /dotprod/OtherConstruct1/OtherConstruct1/OtherConstruct1/i0 (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) - !REF: /dotprod/n - !REF: /dotprod/block_size + !DEF: /dotprod/OtherConstruct1/OtherConstruct1/OtherConstruct1/n HostAssoc INTEGER(4) + !DEF: /dotprod/OtherConstruct1/OtherConstruct1/OtherConstruct1/block_size HostAssoc INTEGER(4) do i0=1,n,block_size !$omp parallel do reduction(+: sum) !DEF: /dotprod/OtherConstruct1/OtherConstruct1/OtherConstruct1/OtherConstruct1/i (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) diff --git a/flang/test/Semantics/OpenMP/threadprivate02.f90 b/flang/test/Semantics/OpenMP/threadprivate02.f90 index 9dc031a8ce47e..7f6e8dcc8e8ab 100644 --- a/flang/test/Semantics/OpenMP/threadprivate02.f90 +++ b/flang/test/Semantics/OpenMP/threadprivate02.f90 @@ -7,9 +7,6 @@ program threadprivate02 integer :: arr1(10) common /blk1/ a1 real, save :: eq_a, eq_b, eq_c, eq_d - integer :: eq_e, eq_f - equivalence(eq_e, eq_f) - common /blk2/ eq_e !$omp threadprivate(arr1) @@ -28,9 +25,6 @@ program threadprivate02 !$omp threadprivate(eq_c) equivalence(eq_c, eq_d) - !ERROR: A variable in a THREADPRIVATE directive cannot appear in an EQUIVALENCE statement (variable 'eq_e' from common block '/blk2/') - !$omp threadprivate(/blk2/) - contains subroutine func() integer :: arr2(10) diff --git a/flang/test/Semantics/cuf18.cuf b/flang/test/Semantics/cuf18.cuf index e51e5c9f97e03..8c9d9131ee251 100644 --- a/flang/test/Semantics/cuf18.cuf +++ b/flang/test/Semantics/cuf18.cuf @@ -1,5 +1,4 @@ ! RUN: %python %S/test_errors.py %s %flang_fc1 -fopenacc - subroutine sub1() real, allocatable, device :: a(:) integer :: i diff --git a/flang/test/Transforms/DoConcurrent/basic_host.f90 b/flang/test/Transforms/DoConcurrent/basic_host.f90 index 6f24b346e3fb9..01b6524e13c36 100644 --- a/flang/test/Transforms/DoConcurrent/basic_host.f90 +++ b/flang/test/Transforms/DoConcurrent/basic_host.f90 @@ -1,3 +1,5 @@ +! Fails until we update the pass to use the `fir.do_concurrent` op. + ! Tests mapping of a basic `do concurrent` loop to `!$omp parallel do`. ! RUN: %flang_fc1 -emit-hlfir -fopenmp -fdo-concurrent-to-openmp=host %s -o - \ diff --git a/flang/test/Transforms/DoConcurrent/locally_destroyed_temp.f90 b/flang/test/Transforms/DoConcurrent/locally_destroyed_temp.f90 index 6a29b57a90d00..28429cebf8587 100644 --- a/flang/test/Transforms/DoConcurrent/locally_destroyed_temp.f90 +++ b/flang/test/Transforms/DoConcurrent/locally_destroyed_temp.f90 @@ -1,3 +1,5 @@ +! Fails until we update the pass to use the `fir.do_concurrent` op. + ! Tests that "loop-local values" are properly handled by localizing them to the ! body of the loop nest. See `collectLoopLocalValues` and `localizeLoopLocalValue` ! for a definition of "loop-local values" and how they are handled. diff --git a/flang/test/Transforms/DoConcurrent/multiple_iteration_ranges.f90 b/flang/test/Transforms/DoConcurrent/multiple_iteration_ranges.f90 index 015a9104942e3..3ea32f9f4cecc 100644 --- a/flang/test/Transforms/DoConcurrent/multiple_iteration_ranges.f90 +++ b/flang/test/Transforms/DoConcurrent/multiple_iteration_ranges.f90 @@ -1,3 +1,5 @@ +! Fails until we update the pass to use the `fir.do_concurrent` op. + ! Tests mapping of a `do concurrent` loop with multiple iteration ranges. ! RUN: split-file %s %t diff --git a/flang/test/Transforms/DoConcurrent/non_const_bounds.f90 b/flang/test/Transforms/DoConcurrent/non_const_bounds.f90 index cd1bd4f98a3f5..4bc0ec5b2f047 100644 --- a/flang/test/Transforms/DoConcurrent/non_const_bounds.f90 +++ b/flang/test/Transforms/DoConcurrent/non_const_bounds.f90 @@ -1,3 +1,5 @@ +! Fails until we update the pass to use the `fir.do_concurrent` op. + ! RUN: %flang_fc1 -emit-hlfir -fopenmp -fdo-concurrent-to-openmp=host %s -o - \ ! RUN: | FileCheck %s @@ -42,4 +44,3 @@ end program main ! CHECK: } ! CHECK: omp.terminator ! CHECK: } - diff --git a/flang/test/Transforms/DoConcurrent/not_perfectly_nested.f90 b/flang/test/Transforms/DoConcurrent/not_perfectly_nested.f90 index d00e1610c2b5e..c87cf392bd5d6 100644 --- a/flang/test/Transforms/DoConcurrent/not_perfectly_nested.f90 +++ b/flang/test/Transforms/DoConcurrent/not_perfectly_nested.f90 @@ -1,3 +1,5 @@ +! Fails until we update the pass to use the `fir.do_concurrent` op. + ! Tests that if `do concurrent` is not perfectly nested in its parent loop, that ! we skip converting the not-perfectly nested `do concurrent` loop. diff --git a/flang/test/Transforms/OpenMP/function-filtering-host-ops.mlir b/flang/test/Transforms/OpenMP/function-filtering-host-ops.mlir new file mode 100644 index 0000000000000..48e75c0ce655e --- /dev/null +++ b/flang/test/Transforms/OpenMP/function-filtering-host-ops.mlir @@ -0,0 +1,532 @@ +// RUN: fir-opt --omp-function-filtering %s | FileCheck %s + +module attributes {omp.is_target_device = true} { + // CHECK-LABEL: func.func @basic_checks + // CHECK-SAME: (%[[ARG:.*]]: !fir.ref) -> (i32, f32) + func.func @basic_checks(%arg: !fir.ref) -> (i32, f32) { + // CHECK-NEXT: %[[PLACEHOLDER:.*]] = fir.alloca i1 + // CHECK-NEXT: %[[ALLOC:.*]] = fir.convert %[[PLACEHOLDER]] : (!fir.ref) -> !fir.ref + // CHECK-NEXT: %[[GLOBAL:.*]] = fir.address_of(@global_scalar) : !fir.ref + %r0 = arith.constant 10 : i32 + %r1 = arith.constant 2.5 : f32 + + func.call @foo() : () -> () + + // CHECK-NEXT: %[[ARG_DECL:.*]]:2 = hlfir.declare %[[ARG]] {uniq_name = "arg"} + %0:2 = hlfir.declare %arg {uniq_name = "arg"} : (!fir.ref) -> (!fir.ref, !fir.ref) + + // CHECK-NEXT: %[[GLOBAL_DECL:.*]]:2 = hlfir.declare %[[GLOBAL]] {uniq_name = "global_scalar"} + %global = fir.address_of(@global_scalar) : !fir.ref + %1:2 = hlfir.declare %global {uniq_name = "global_scalar"} : (!fir.ref) -> (!fir.ref, !fir.ref) + + // CHECK-NEXT: %[[ALLOC_DECL:.*]]:2 = hlfir.declare %[[ALLOC]] {uniq_name = "alloc"} + %alloc = fir.alloca i32 + %2:2 = hlfir.declare %alloc {uniq_name = "alloc"} : (!fir.ref) -> (!fir.ref, !fir.ref) + + // CHECK-NEXT: %[[MAP0:.*]] = omp.map.info var_ptr(%[[ARG_DECL]]#1{{.*}}) + // CHECK-NEXT: %[[MAP1:.*]] = omp.map.info var_ptr(%[[GLOBAL_DECL]]#1{{.*}}) + // CHECK-NEXT: %[[MAP3:.*]] = omp.map.info var_ptr(%[[ALLOC]]{{.*}}) + // CHECK-NEXT: %[[MAP2:.*]] = omp.map.info var_ptr(%[[ALLOC_DECL]]#1{{.*}}) + // CHECK-NEXT: %[[MAP4:.*]] = omp.map.info var_ptr(%[[ARG_DECL]]#1{{.*}}) + // CHECK-NEXT: %[[MAP5:.*]] = omp.map.info var_ptr(%[[GLOBAL_DECL]]#1{{.*}}) + // CHECK-NEXT: %[[MAP6:.*]] = omp.map.info var_ptr(%[[ALLOC_DECL]]#1{{.*}}) + // CHECK-NEXT: %[[MAP7:.*]] = omp.map.info var_ptr(%[[ALLOC]]{{.*}}) + // CHECK-NEXT: %[[MAP8:.*]] = omp.map.info var_ptr(%[[ARG_DECL]]#1{{.*}}) + // CHECK-NEXT: %[[MAP9:.*]] = omp.map.info var_ptr(%[[GLOBAL_DECL]]#1{{.*}}) + // CHECK-NEXT: %[[MAP10:.*]] = omp.map.info var_ptr(%[[ALLOC_DECL]]#1{{.*}}) + %m0 = omp.map.info var_ptr(%0#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + %m1 = omp.map.info var_ptr(%1#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + %m2 = omp.map.info var_ptr(%2#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + %m3 = omp.map.info var_ptr(%alloc : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + + // CHECK-NEXT: omp.target has_device_addr(%[[MAP2]] -> {{.*}} : {{.*}}) map_entries(%[[MAP0]] -> {{.*}}, %[[MAP1]] -> {{.*}}, %[[MAP3]] -> {{.*}} : {{.*}}) + omp.target has_device_addr(%m2 -> %arg0 : !fir.ref) map_entries(%m0 -> %arg1, %m1 -> %arg2, %m3 -> %arg3 : !fir.ref, !fir.ref, !fir.ref) { + // CHECK-NEXT: func.call + func.call @foo() : () -> () + omp.terminator + } + + // CHECK-NOT: omp.parallel + // CHECK-NOT: func.call + // CHECK-NOT: omp.map.info + omp.parallel { + func.call @foo() : () -> () + omp.terminator + } + + %m4 = omp.map.info var_ptr(%0#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + %m5 = omp.map.info var_ptr(%1#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + %m6 = omp.map.info var_ptr(%2#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + %m7 = omp.map.info var_ptr(%alloc : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + + // CHECK: omp.target_data map_entries(%[[MAP4]], %[[MAP5]], %[[MAP6]], %[[MAP7]] : {{.*}}) + omp.target_data map_entries(%m4, %m5, %m6, %m7 : !fir.ref, !fir.ref, !fir.ref, !fir.ref) { + // CHECK-NOT: func.call + func.call @foo() : () -> () + omp.terminator + } + + // CHECK: omp.target_enter_data map_entries(%[[MAP8]] : {{.*}}) + // CHECK-NEXT: omp.target_exit_data map_entries(%[[MAP9]] : {{.*}}) + // CHECK-NEXT: omp.target_update map_entries(%[[MAP10]] : {{.*}}) + %m8 = omp.map.info var_ptr(%0#1 : !fir.ref, i32) map_clauses(to) capture(ByRef) -> !fir.ref + omp.target_enter_data map_entries(%m8 : !fir.ref) + + %m9 = omp.map.info var_ptr(%1#1 : !fir.ref, i32) map_clauses(from) capture(ByRef) -> !fir.ref + omp.target_exit_data map_entries(%m9 : !fir.ref) + + %m10 = omp.map.info var_ptr(%2#1 : !fir.ref, !fir.ref) map_clauses(to) capture(ByRef) -> !fir.ref + omp.target_update map_entries(%m10 : !fir.ref) + + // CHECK-NOT: func.call + func.call @foo() : () -> () + + // CHECK: %[[RETURN0:.*]] = fir.undefined i32 + // CHECK-NEXT: %[[RETURN1:.*]] = fir.undefined f32 + // CHECK-NEXT: return %[[RETURN0]], %[[RETURN1]] + return %r0, %r1 : i32, f32 + } + + // CHECK-LABEL: func.func @allocatable_array + // CHECK-SAME: (%[[ALLOCATABLE:.*]]: [[ALLOCATABLE_TYPE:.*]], %[[ARRAY:.*]]: [[ARRAY_TYPE:[^)]*]]) + func.func @allocatable_array(%allocatable: !fir.ref>>>, %array: !fir.ref>) { + // CHECK-NEXT: %[[ZERO:.*]] = arith.constant 0 : i64 + // CHECK-NEXT: %[[SHAPE:.*]] = fir.shape %[[ZERO]] : (i64) -> !fir.shape<1> + // CHECK-NEXT: %[[ALLOCATABLE_DECL:.*]]:2 = hlfir.declare %[[ALLOCATABLE]] {fortran_attrs = #fir.var_attrs, uniq_name = "allocatable"} : ([[ALLOCATABLE_TYPE]]) -> ([[ALLOCATABLE_TYPE]], [[ALLOCATABLE_TYPE]]) + // CHECK-NEXT: %[[ARRAY_DECL:.*]]:2 = hlfir.declare %[[ARRAY]](%[[SHAPE]]) {uniq_name = "array"} : ([[ARRAY_TYPE]], !fir.shape<1>) -> ([[ARRAY_TYPE]], [[ARRAY_TYPE]]) + // CHECK-NEXT: %[[VAR_PTR_PTR:.*]] = fir.box_offset %[[ALLOCATABLE_DECL]]#1 base_addr : ([[ALLOCATABLE_TYPE]]) -> [[VAR_PTR_PTR_TYPE:.*]] + // CHECK-NEXT: %[[MAP_ALLOCATABLE:.*]] = omp.map.info var_ptr(%[[ALLOCATABLE_DECL]]#1 : [[ALLOCATABLE_TYPE]], f32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[VAR_PTR_PTR]] : [[VAR_PTR_PTR_TYPE]]) -> [[VAR_PTR_PTR_TYPE]] + // CHECK-NEXT: %[[MAP_ARRAY:.*]] = omp.map.info var_ptr(%[[ARRAY_DECL]]#1 : [[ARRAY_TYPE]], !fir.array<9xi32>) map_clauses(tofrom) capture(ByRef) -> [[ARRAY_TYPE]] + // CHECK-NEXT: omp.target map_entries(%[[MAP_ALLOCATABLE]] -> %{{.*}}, %[[MAP_ARRAY]] -> %{{.*}} : [[VAR_PTR_PTR_TYPE]], [[ARRAY_TYPE]]) + %c0 = arith.constant 0 : index + %c1 = arith.constant 1 : index + %c8 = arith.constant 8 : index + %c9 = arith.constant 9 : index + + %0:2 = hlfir.declare %allocatable {fortran_attrs = #fir.var_attrs, uniq_name = "allocatable"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) + %1 = omp.map.bounds lower_bound(%c0 : index) upper_bound(%c8 : index) extent(%c9 : index) stride(%c1 : index) start_idx(%c1 : index) + %2 = fir.box_offset %0#1 base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> + %m0 = omp.map.info var_ptr(%0#1 : !fir.ref>>>, f32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%2 : !fir.llvm_ptr>>) bounds(%1) -> !fir.llvm_ptr>> + + %3 = fir.shape %c9 : (index) -> !fir.shape<1> + %4:2 = hlfir.declare %array(%3) {uniq_name = "array"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) + %5 = omp.map.bounds lower_bound(%c0 : index) upper_bound(%c8 : index) extent(%c9 : index) stride(%c1 : index) start_idx(%c1 : index) + %6 = omp.map.info var_ptr(%4#1 : !fir.ref>, !fir.array<9xi32>) map_clauses(tofrom) capture(ByRef) bounds(%5) -> !fir.ref> + + omp.target map_entries(%m0 -> %arg0, %6 -> %arg1 : !fir.llvm_ptr>>, !fir.ref>) { + omp.terminator + } + return + } + + // CHECK-LABEL: func.func @character + // CHECK-SAME: (%[[X:.*]]: [[X_TYPE:[^)]*]]) + func.func @character(%x: !fir.ref>) { + // CHECK-NEXT: %[[ZERO]] = arith.constant 0 : i64 + %0 = fir.dummy_scope : !fir.dscope + %c1 = arith.constant 1 : index + // CHECK-NEXT: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] typeparams %[[ZERO]] {uniq_name = "x"} : ([[X_TYPE]], i64) -> ([[X_TYPE]], [[X_TYPE]]) + %3:2 = hlfir.declare %x typeparams %c1 dummy_scope %0 {uniq_name = "x"} : (!fir.ref>, index, !fir.dscope) -> (!fir.ref>, !fir.ref>) + // CHECK-NEXT: %[[MAP:.*]] = omp.map.info var_ptr(%[[X_DECL]]#1 : [[X_TYPE]], !fir.char<1>) map_clauses(tofrom) capture(ByRef) -> [[X_TYPE]] + %map = omp.map.info var_ptr(%3#1 : !fir.ref>, !fir.char<1>) map_clauses(tofrom) capture(ByRef) -> !fir.ref> + // CHECK-NEXT: omp.target map_entries(%[[MAP]] -> %{{.*}}) + omp.target map_entries(%map -> %arg0 : !fir.ref>) { + omp.terminator + } + return + } + + // CHECK-LABEL: func.func @assumed_rank + // CHECK-SAME: (%[[X:.*]]: [[X_TYPE:[^)]*]]) + func.func @assumed_rank(%x: !fir.box>) { + // CHECK-NEXT: %[[PLACEHOLDER:.*]] = fir.alloca i1 + // CHECK-NEXT: %[[ALLOCA:.*]] = fir.convert %[[PLACEHOLDER]] : (!fir.ref) -> !fir.ref<[[X_TYPE]]> + %0 = fir.alloca !fir.box> + %1 = fir.dummy_scope : !fir.dscope + %2:2 = hlfir.declare %x dummy_scope %1 {uniq_name = "x"} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) + %3 = fir.box_addr %2#1 : (!fir.box>) -> !fir.ref> + fir.store %2#1 to %0 : !fir.ref>> + // CHECK-NEXT: %[[VAR_PTR_PTR:.*]] = fir.box_offset %[[ALLOCA]] base_addr : (!fir.ref<[[X_TYPE]]>) -> [[VAR_PTR_PTR_TYPE:.*]] + %4 = fir.box_offset %0 base_addr : (!fir.ref>>) -> !fir.llvm_ptr>> + // CHECK-NEXT: %[[MAP0:.*]] = omp.map.info var_ptr(%[[ALLOCA]] : !fir.ref<[[X_TYPE]]>, !fir.array<*:f32>) {{.*}} var_ptr_ptr(%[[VAR_PTR_PTR]] : [[VAR_PTR_PTR_TYPE]]) -> [[VAR_PTR_PTR_TYPE]] + %5 = omp.map.info var_ptr(%0 : !fir.ref>>, !fir.array<*:f32>) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%4 : !fir.llvm_ptr>>) -> !fir.llvm_ptr>> + // CHECK-NEXT: %[[MAP1:.*]] = omp.map.info var_ptr(%[[ALLOCA]] : !fir.ref<[[X_TYPE]]>, !fir.box>) {{.*}} members(%[[MAP0]] : [0] : [[VAR_PTR_PTR_TYPE]]) -> !fir.ref> + %6 = omp.map.info var_ptr(%0 : !fir.ref>>, !fir.box>) map_clauses(to) capture(ByRef) members(%5 : [0] : !fir.llvm_ptr>>) -> !fir.ref> + // CHECK-NEXT: omp.target map_entries(%[[MAP1]] -> %{{.*}}, %[[MAP0]] -> {{.*}}) + omp.target map_entries(%6 -> %arg1, %5 -> %arg2 : !fir.ref>, !fir.llvm_ptr>>) { + omp.terminator + } + return + } + + // CHECK-LABEL: func.func @box_ptr + // CHECK-SAME: (%[[X:.*]]: [[X_TYPE:[^)]*]]) + func.func @box_ptr(%x: !fir.ref>>>) { + // CHECK-NEXT: %[[ZERO:.*]] = arith.constant 0 : i64 + // CHECK-NEXT: %[[SHAPE:.*]] = fir.shape_shift %[[ZERO]], %[[ZERO]] : (i64, i64) -> !fir.shapeshift<1> + // CHECK-NEXT: %[[PLACEHOLDER_X:.*]] = fir.alloca i1 + // CHECK-NEXT: %[[ALLOCA_X:.*]] = fir.convert %[[PLACEHOLDER_X]] : (!fir.ref) -> [[X_TYPE]] + %0 = fir.alloca !fir.box>> + %1 = fir.dummy_scope : !fir.dscope + %2:2 = hlfir.declare %x dummy_scope %1 {fortran_attrs = #fir.var_attrs, uniq_name = "x"} : (!fir.ref>>>, !fir.dscope) -> (!fir.ref>>>, !fir.ref>>>) + %3 = fir.load %2#0 : !fir.ref>>> + fir.store %3 to %0 : !fir.ref>>> + + // CHECK-NEXT: %[[PLACEHOLDER_Y:.*]] = fir.alloca i1 + // CHECK-NEXT: %[[ALLOCA_Y:.*]] = fir.convert %[[PLACEHOLDER_Y]] : (!fir.ref) -> [[Y_TYPE:.*]] + %c0 = arith.constant 0 : index + %4:3 = fir.box_dims %3, %c0 : (!fir.box>>, index) -> (index, index, index) + %c1 = arith.constant 1 : index + %c0_0 = arith.constant 0 : index + %5:3 = fir.box_dims %3, %c0_0 : (!fir.box>>, index) -> (index, index, index) + %c0_1 = arith.constant 0 : index + %6 = arith.subi %5#1, %c1 : index + %7 = omp.map.bounds lower_bound(%c0_1 : index) upper_bound(%6 : index) extent(%5#1 : index) stride(%5#2 : index) start_idx(%4#0 : index) {stride_in_bytes = true} + %8 = fir.box_addr %3 : (!fir.box>>) -> !fir.ptr> + %c0_2 = arith.constant 0 : index + %9:3 = fir.box_dims %3, %c0_2 : (!fir.box>>, index) -> (index, index, index) + %10 = fir.shape_shift %9#0, %9#1 : (index, index) -> !fir.shapeshift<1> + + // CHECK-NEXT: %[[Y_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_Y]](%[[SHAPE]]) {fortran_attrs = #fir.var_attrs, uniq_name = "y"} : ([[Y_TYPE]], !fir.shapeshift<1>) -> (!fir.box>, [[Y_TYPE]]) + %11:2 = hlfir.declare %8(%10) {fortran_attrs = #fir.var_attrs, uniq_name = "y"} : (!fir.ptr>, !fir.shapeshift<1>) -> (!fir.box>, !fir.ptr>) + %c1_3 = arith.constant 1 : index + %c0_4 = arith.constant 0 : index + %12:3 = fir.box_dims %11#0, %c0_4 : (!fir.box>, index) -> (index, index, index) + %c0_5 = arith.constant 0 : index + %13 = arith.subi %12#1, %c1_3 : index + %14 = omp.map.bounds lower_bound(%c0_5 : index) upper_bound(%13 : index) extent(%12#1 : index) stride(%12#2 : index) start_idx(%9#0 : index) {stride_in_bytes = true} + + // CHECK-NEXT: %[[VAR_PTR_PTR:.*]] = fir.box_offset %[[ALLOCA_X]] base_addr : ([[X_TYPE]]) -> [[VAR_PTR_PTR_TYPE:.*]] + // CHECK-NEXT: %[[MAP0:.*]] = omp.map.info var_ptr(%[[Y_DECL]]#1 : [[Y_TYPE]], i32) {{.*}} -> [[Y_TYPE]] + // CHECK-NEXT: %[[MAP1:.*]] = omp.map.info var_ptr(%[[ALLOCA_X]] : [[X_TYPE]], i32) {{.*}} var_ptr_ptr(%[[VAR_PTR_PTR]] : [[VAR_PTR_PTR_TYPE]]) -> [[VAR_PTR_PTR_TYPE]] + // CHECK-NEXT: %[[MAP2:.*]] = omp.map.info var_ptr(%[[ALLOCA_X]] : [[X_TYPE]], !fir.box>>) {{.*}} members(%[[MAP1]] : [0] : [[VAR_PTR_PTR_TYPE]]) -> [[X_TYPE]] + %15 = omp.map.info var_ptr(%11#1 : !fir.ptr>, i32) map_clauses(tofrom) capture(ByRef) bounds(%14) -> !fir.ptr> + %16 = fir.box_offset %0 base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> + %17 = omp.map.info var_ptr(%0 : !fir.ref>>>, i32) map_clauses(implicit, to) capture(ByRef) var_ptr_ptr(%16 : !fir.llvm_ptr>>) bounds(%7) -> !fir.llvm_ptr>> + %18 = omp.map.info var_ptr(%0 : !fir.ref>>>, !fir.box>>) map_clauses(implicit, to) capture(ByRef) members(%17 : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> + + // CHECK-NEXT: omp.target map_entries(%[[MAP0]] -> %{{.*}}, %[[MAP2]] -> %{{.*}}, %[[MAP1]] -> {{.*}} : [[Y_TYPE]], [[X_TYPE]], [[VAR_PTR_PTR_TYPE]]) + omp.target map_entries(%15 -> %arg1, %18 -> %arg2, %17 -> %arg3 : !fir.ptr>, !fir.ref>>>, !fir.llvm_ptr>>) { + omp.terminator + } + return + } + + // CHECK-LABEL: func.func @target_data + // CHECK-SAME: (%[[MAPPED:.*]]: [[MAPPED_TYPE:[^)]*]], %[[USEDEVADDR:.*]]: [[USEDEVADDR_TYPE:[^)]*]], %[[USEDEVPTR:.*]]: [[USEDEVPTR_TYPE:[^)]*]]) + func.func @target_data(%mapped: !fir.ref, %usedevaddr: !fir.ref, %usedevptr: !fir.ref>) { + // CHECK-NEXT: %[[MAPPED_DECL:.*]]:2 = hlfir.declare %[[MAPPED]] {uniq_name = "mapped"} : ([[MAPPED_TYPE]]) -> ([[MAPPED_TYPE]], [[MAPPED_TYPE]]) + %0:2 = hlfir.declare %mapped {uniq_name = "mapped"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %1:2 = hlfir.declare %usedevaddr {uniq_name = "usedevaddr"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %2:2 = hlfir.declare %usedevptr {uniq_name = "usedevptr"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) + %m0 = omp.map.info var_ptr(%0#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + %m1 = omp.map.info var_ptr(%1#1 : !fir.ref, i32) map_clauses(return_param) capture(ByRef) -> !fir.ref + %m2 = omp.map.info var_ptr(%2#1 : !fir.ref>, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(return_param) capture(ByRef) -> !fir.ref> + // CHECK: omp.target_data map_entries(%{{.*}}) use_device_addr(%{{.*}} -> %[[USEDEVADDR_ARG:.*]] : [[USEDEVADDR_TYPE]]) use_device_ptr(%{{.*}} -> %[[USEDEVPTR_ARG:.*]] : [[USEDEVPTR_TYPE]]) + omp.target_data map_entries(%m0 : !fir.ref) use_device_addr(%m1 -> %arg0 : !fir.ref) use_device_ptr(%m2 -> %arg1 : !fir.ref>) { + // CHECK-NEXT: %[[USEDEVADDR_DECL:.*]]:2 = hlfir.declare %[[USEDEVADDR_ARG]] {uniq_name = "usedevaddr"} : ([[USEDEVADDR_TYPE]]) -> ([[USEDEVADDR_TYPE]], [[USEDEVADDR_TYPE]]) + %3:2 = hlfir.declare %arg0 {uniq_name = "usedevaddr"} : (!fir.ref) -> (!fir.ref, !fir.ref) + // CHECK-NEXT: %[[USEDEVPTR_DECL:.*]]:2 = hlfir.declare %[[USEDEVPTR_ARG]] {uniq_name = "usedevptr"} : ([[USEDEVPTR_TYPE]]) -> ([[USEDEVPTR_TYPE]], [[USEDEVPTR_TYPE]]) + %4:2 = hlfir.declare %arg1 {uniq_name = "usedevptr"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) + // CHECK-NEXT: %[[MAPPED_MAP:.*]] = omp.map.info var_ptr(%[[MAPPED_DECL]]#1 : [[MAPPED_TYPE]], i32) map_clauses(tofrom) capture(ByRef) -> [[MAPPED_TYPE]] + %m3 = omp.map.info var_ptr(%0#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NEXT: %[[USEDEVADDR_MAP:.*]] = omp.map.info var_ptr(%[[USEDEVADDR_DECL]]#1 : [[USEDEVADDR_TYPE]], i32) map_clauses(tofrom) capture(ByRef) -> [[USEDEVADDR_TYPE]] + %m4 = omp.map.info var_ptr(%3#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NEXT: %[[USEDEVPTR_MAP:.*]] = omp.map.info var_ptr(%[[USEDEVPTR_DECL]]#1 : [[USEDEVPTR_TYPE]], !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(tofrom) capture(ByRef) -> [[USEDEVPTR_TYPE]] + %m5 = omp.map.info var_ptr(%4#1 : !fir.ref>, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(tofrom) capture(ByRef) -> !fir.ref> + + // CHECK-NOT: func.call + func.call @foo() : () -> () + + // CHECK-NEXT: omp.target map_entries(%[[MAPPED_MAP]] -> %{{.*}}, %[[USEDEVADDR_MAP]] -> %{{.*}}, %[[USEDEVPTR_MAP]] -> %{{.*}} : {{.*}}) + omp.target map_entries(%m3 -> %arg2, %m4 -> %arg3, %m5 -> %arg4 : !fir.ref, !fir.ref, !fir.ref>) { + omp.terminator + } + + // CHECK-NOT: func.call + func.call @foo() : () -> () + + omp.terminator + } + + // CHECK: return + return + } + + // CHECK-LABEL: func.func @map_info_members + // CHECK-SAME: (%[[X:.*]]: [[X_TYPE:[^)]*]]) + func.func @map_info_members(%x: !fir.ref>>>) { + %c0 = arith.constant 0 : index + %c1 = arith.constant 1 : index + %c9 = arith.constant 9 : index + // CHECK-NEXT: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] {fortran_attrs = #fir.var_attrs, uniq_name = "x"} : ([[X_TYPE]]) -> ([[X_TYPE]], [[X_TYPE]]) + %23:2 = hlfir.declare %x {fortran_attrs = #fir.var_attrs, uniq_name = "x"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) + %63 = fir.load %23#0 : !fir.ref>>> + %64:3 = fir.box_dims %63, %c0 : (!fir.box>>, index) -> (index, index, index) + %65:3 = fir.box_dims %63, %c0 : (!fir.box>>, index) -> (index, index, index) + %66 = arith.subi %c1, %64#0 : index + %67 = arith.subi %c9, %64#0 : index + %68 = fir.load %23#0 : !fir.ref>>> + %69:3 = fir.box_dims %68, %c0 : (!fir.box>>, index) -> (index, index, index) + %70 = omp.map.bounds lower_bound(%66 : index) upper_bound(%67 : index) extent(%69#1 : index) stride(%65#2 : index) start_idx(%64#0 : index) {stride_in_bytes = true} + // CHECK-NEXT: %[[VAR_PTR_PTR:.*]] = fir.box_offset %[[X_DECL]]#1 base_addr : ([[X_TYPE]]) -> [[VAR_PTR_PTR_TYPE:.*]] + %71 = fir.box_offset %23#1 base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> + // CHECK-NEXT: %[[MAP0:.*]] = omp.map.info var_ptr(%[[X_DECL]]#1 : [[X_TYPE]], f32) {{.*}} var_ptr_ptr(%[[VAR_PTR_PTR]] : [[VAR_PTR_PTR_TYPE]]) -> [[VAR_PTR_PTR_TYPE]] + %72 = omp.map.info var_ptr(%23#1 : !fir.ref>>>, f32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%71 : !fir.llvm_ptr>>) bounds(%70) -> !fir.llvm_ptr>> + // CHECK-NEXT: %[[MAP1:.*]] = omp.map.info var_ptr(%[[X_DECL]]#1 : [[X_TYPE]], !fir.box>>) {{.*}} members(%[[MAP0]] : [0] : [[VAR_PTR_PTR_TYPE]]) -> [[X_TYPE]] + %73 = omp.map.info var_ptr(%23#1 : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) members(%72 : [0] : !fir.llvm_ptr>>) -> !fir.ref>>> + // CHECK-NEXT: omp.target map_entries(%[[MAP1]] -> {{.*}}, %[[MAP0]] -> %{{.*}} : [[X_TYPE]], [[VAR_PTR_PTR_TYPE]]) + omp.target map_entries(%73 -> %arg0, %72 -> %arg1 : !fir.ref>>>, !fir.llvm_ptr>>) { + omp.terminator + } + return + } + + // CHECK-LABEL: func.func @control_flow + // CHECK-SAME: (%[[X:.*]]: [[X_TYPE:[^,]*]], %[[COND:.*]]: [[COND_TYPE:[^)]*]]) + func.func @control_flow(%x: !fir.ref, %cond: !fir.ref>) { + // CHECK-NEXT: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] {uniq_name = "x"} : ([[X_TYPE]]) -> ([[X_TYPE]], [[X_TYPE]]) + // CHECK-NEXT: %[[MAP0:.*]] = omp.map.info var_ptr(%[[X_DECL]]#1 : [[X_TYPE]], i32) {{.*}} -> [[X_TYPE]] + // CHECK-NEXT: %[[MAP1:.*]] = omp.map.info var_ptr(%[[X_DECL]]#1 : [[X_TYPE]], i32) {{.*}} -> [[X_TYPE]] + %x_decl:2 = hlfir.declare %x {uniq_name = "x"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %cond_decl:2 = hlfir.declare %cond {uniq_name = "cond"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) + %0 = fir.load %cond_decl#0 : !fir.ref> + %1 = fir.convert %0 : (!fir.logical<4>) -> i1 + cf.cond_br %1, ^bb1, ^bb2 + ^bb1: // pred: ^bb0 + fir.call @foo() : () -> () + %m0 = omp.map.info var_ptr(%x_decl#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NEXT: omp.target map_entries(%[[MAP0]] -> {{.*}} : [[X_TYPE]]) + omp.target map_entries(%m0 -> %arg2 : !fir.ref) { + omp.terminator + } + fir.call @foo() : () -> () + cf.br ^bb2 + ^bb2: // 2 preds: ^bb0, ^bb1 + fir.call @foo() : () -> () + %m1 = omp.map.info var_ptr(%x_decl#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NOT: fir.call + // CHECK-NOT: omp.map.info + // CHECK: omp.target_data map_entries(%[[MAP1]] : [[X_TYPE]]) + omp.target_data map_entries(%m1 : !fir.ref) { + fir.call @foo() : () -> () + %8 = fir.load %cond_decl#0 : !fir.ref> + %9 = fir.convert %8 : (!fir.logical<4>) -> i1 + cf.cond_br %9, ^bb1, ^bb2 + ^bb1: // pred: ^bb0 + fir.call @foo() : () -> () + // CHECK-NEXT: %[[MAP2:.*]] = omp.map.info var_ptr(%[[X_DECL]]#1 : [[X_TYPE]], i32) {{.*}} -> [[X_TYPE]] + %m2 = omp.map.info var_ptr(%x_decl#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NEXT: omp.target map_entries(%[[MAP2]] -> {{.*}} : [[X_TYPE]]) + omp.target map_entries(%m2 -> %arg2 : !fir.ref) { + omp.terminator + } + // CHECK-NOT: fir.call + // CHECK-NOT: cf.br + fir.call @foo() : () -> () + cf.br ^bb2 + ^bb2: // 2 preds: ^bb0, ^bb1 + fir.call @foo() : () -> () + omp.terminator + } + fir.call @foo() : () -> () + + // CHECK: return + return + } + + // CHECK-LABEL: func.func @block_args + // CHECK-SAME: (%[[X:.*]]: [[X_TYPE:[^)]*]]) + func.func @block_args(%x: !fir.ref) { + // CHECK-NEXT: %[[PLACEHOLDER0:.*]] = fir.alloca i1 + // CHECK-NEXT: %[[ALLOCA0:.*]] = fir.convert %[[PLACEHOLDER0]] : (!fir.ref) -> !fir.ref + // CHECK-NEXT: %[[PLACEHOLDER1:.*]] = fir.alloca i1 + // CHECK-NEXT: %[[ALLOCA1:.*]] = fir.convert %[[PLACEHOLDER1]] : (!fir.ref) -> !fir.ref + // CHECK-NEXT: %[[X_DECL0:.*]]:2 = hlfir.declare %[[ALLOCA0]] {uniq_name = "x"} : ([[X_TYPE]]) -> ([[X_TYPE]], [[X_TYPE]]) + // CHECK-NEXT: %[[X_DECL1:.*]]:2 = hlfir.declare %[[ALLOCA1]] {uniq_name = "x"} : ([[X_TYPE]]) -> ([[X_TYPE]], [[X_TYPE]]) + // CHECK-NEXT: %[[MAP0:.*]] = omp.map.info var_ptr(%[[X_DECL0]]#1 : [[X_TYPE]], i32) {{.*}} -> [[X_TYPE]] + // CHECK-NEXT: %[[MAP1:.*]] = omp.map.info var_ptr(%[[X_DECL1]]#1 : [[X_TYPE]], i32) {{.*}} -> [[X_TYPE]] + %x_decl:2 = hlfir.declare %x {uniq_name = "x"} : (!fir.ref) -> (!fir.ref, !fir.ref) + omp.parallel private(@privatizer %x_decl#0 -> %arg0 : !fir.ref) { + %0:2 = hlfir.declare %arg0 {uniq_name = "x"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %m0 = omp.map.info var_ptr(%0#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NEXT: omp.target map_entries(%[[MAP0]] -> {{.*}} : [[X_TYPE]]) + omp.target map_entries(%m0 -> %arg2 : !fir.ref) { + omp.terminator + } + omp.terminator + } + + omp.parallel private(@privatizer %x_decl#0 -> %arg0 : !fir.ref) { + %1:2 = hlfir.declare %arg0 {uniq_name = "x"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %m1 = omp.map.info var_ptr(%1#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NOT: omp.parallel + // CHECK-NOT: hlfir.declare + // CHECK-NOT: omp.map.info + // CHECK: omp.target_data map_entries(%[[MAP1]] : [[X_TYPE]]) + omp.target_data map_entries(%m1 : !fir.ref) { + omp.parallel private(@privatizer %1#0 -> %arg1 : !fir.ref) { + // CHECK-NEXT: %[[PLACEHOLDER2:.*]] = fir.alloca i1 + // CHECK-NEXT: %[[ALLOCA2:.*]] = fir.convert %[[PLACEHOLDER2]] : (!fir.ref) -> !fir.ref + // CHECK-NEXT: %[[X_DECL2:.*]]:2 = hlfir.declare %[[ALLOCA2]] {uniq_name = "x"} : ([[X_TYPE]]) -> ([[X_TYPE]], [[X_TYPE]]) + %2:2 = hlfir.declare %arg1 {uniq_name = "x"} : (!fir.ref) -> (!fir.ref, !fir.ref) + // CHECK-NEXT: %[[MAP2:.*]] = omp.map.info var_ptr(%[[X_DECL2]]#1 : [[X_TYPE]], i32) {{.*}} -> [[X_TYPE]] + %m2 = omp.map.info var_ptr(%2#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NEXT: omp.target map_entries(%[[MAP2]] -> {{.*}} : [[X_TYPE]]) + omp.target map_entries(%m2 -> %arg2 : !fir.ref) { + omp.terminator + } + omp.terminator + } + omp.terminator + } + omp.terminator + } + + return + } + + // CHECK-LABEL: func.func @reuse_tests() + func.func @reuse_tests() { + // CHECK-NEXT: %[[PLACEHOLDER:.*]] = fir.alloca i1 + // CHECK-NEXT: %[[THREAD_LIMIT:.*]] = fir.convert %[[PLACEHOLDER]] : (!fir.ref) -> i32 + // CHECK-NEXT: %[[CONST:.*]] = arith.constant 1 : i32 + // CHECK-NEXT: %[[GLOBAL:.*]] = fir.address_of(@global_scalar) : !fir.ref + %global = fir.address_of(@global_scalar) : !fir.ref + // CHECK-NEXT: %[[GLOBAL_DECL0:.*]]:2 = hlfir.declare %[[GLOBAL]] {uniq_name = "global_scalar"} + // CHECK-NEXT: %[[GLOBAL_DECL1:.*]]:2 = hlfir.declare %[[GLOBAL]] {uniq_name = "global_scalar"} + %0:2 = hlfir.declare %global {uniq_name = "global_scalar"} : (!fir.ref) -> (!fir.ref, !fir.ref) + // CHECK-NEXT: %[[MAP0:.*]] = omp.map.info var_ptr(%[[GLOBAL_DECL0]]#1 : !fir.ref, i32) + // CHECK-NEXT: %[[MAP3:.*]] = omp.map.info var_ptr(%[[GLOBAL_DECL1]]#1 : !fir.ref, i32) + %m0 = omp.map.info var_ptr(%0#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NEXT: omp.target_data map_entries(%[[MAP0]] : !fir.ref) + omp.target_data map_entries(%m0 : !fir.ref) { + // CHECK-NEXT: %[[GLOBAL_DECL2:.*]]:2 = hlfir.declare %[[GLOBAL]] {uniq_name = "global_scalar"} + %1:2 = hlfir.declare %global {uniq_name = "global_scalar"} : (!fir.ref) -> (!fir.ref, !fir.ref) + // CHECK-NEXT: %[[MAP1:.*]] = omp.map.info var_ptr(%[[GLOBAL_DECL0]]#1 : !fir.ref, i32) + %m1 = omp.map.info var_ptr(%0#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NEXT: %[[MAP2:.*]] = omp.map.info var_ptr(%[[GLOBAL_DECL2]]#1 : !fir.ref, i32) + %m2 = omp.map.info var_ptr(%1#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK-NEXT: omp.target map_entries(%[[MAP1]] -> %{{.*}}, %[[MAP2]] -> {{.*}} : !fir.ref, !fir.ref) + omp.target map_entries(%m1 -> %arg0, %m2 -> %arg1 : !fir.ref, !fir.ref) { + omp.terminator + } + omp.terminator + } + // CHECK-NOT: fir.load + // CHECK-NOT: hlfir.declare + %2 = fir.load %global : !fir.ref + %3:2 = hlfir.declare %global {uniq_name = "global_scalar"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %m3 = omp.map.info var_ptr(%3#1 : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK: omp.target thread_limit(%[[THREAD_LIMIT]] : i32) map_entries(%[[MAP3]] -> %{{.*}} : !fir.ref) + omp.target thread_limit(%2 : i32) map_entries(%m3 -> %arg0 : !fir.ref) { + omp.terminator + } + // CHECK: omp.target thread_limit(%[[CONST]] : i32) + %c1 = arith.constant 1 : i32 + omp.target thread_limit(%c1 : i32) { + omp.terminator + } + // CHECK: omp.target thread_limit(%[[CONST]] : i32) + omp.target thread_limit(%c1 : i32) { + omp.terminator + } + return + } + + // CHECK-LABEL: func.func @all_non_map_clauses + // CHECK-SAME: (%[[REF:.*]]: !fir.ref, %[[INT:.*]]: i32, %[[BOOL:.*]]: i1) + func.func @all_non_map_clauses(%ref: !fir.ref, %int: i32, %bool: i1) { + %m0 = omp.map.info var_ptr(%ref : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref + // CHECK: omp.target_data map_entries({{[^)]*}}) { + omp.target_data device(%int : i32) if(%bool) map_entries(%m0 : !fir.ref) { + omp.terminator + } + // CHECK: omp.target allocate({{[^)]*}}) thread_limit({{[^)]*}}) in_reduction({{[^)]*}}) private({{[^)]*}}) { + omp.target allocate(%ref : !fir.ref -> %ref : !fir.ref) + depend(taskdependin -> %ref : !fir.ref) + device(%int : i32) if(%bool) thread_limit(%int : i32) + in_reduction(@reduction %ref -> %arg0 : !fir.ref) + private(@privatizer %ref -> %arg1 : !fir.ref) { + omp.terminator + } + // CHECK: omp.target_enter_data + // CHECK-NOT: depend + // CHECK-NOT: device + // CHECK-NOT: if + omp.target_enter_data depend(taskdependin -> %ref : !fir.ref) + device(%int : i32) if(%bool) + // CHECK-NEXT: omp.target_exit_data + // CHECK-NOT: depend + // CHECK-NOT: device + // CHECK-NOT: if + omp.target_exit_data depend(taskdependin -> %ref : !fir.ref) + device(%int : i32) if(%bool) + // CHECK-NEXT: omp.target_update + // CHECK-NOT: depend + // CHECK-NOT: device + // CHECK-NOT: if + omp.target_update depend(taskdependin -> %ref : !fir.ref) + device(%int : i32) if(%bool) + + // CHECK-NEXT: return + return + } + + // CHECK-LABEL: func.func @assumed_length + // CHECK-SAME: (%[[ARG:.*]]: !fir.boxchar<1>) + func.func @assumed_length(%arg: !fir.boxchar<1>) { + // CHECK-NEXT: %[[PLACEHOLDER:.*]] = fir.alloca !fir.char<1> + // CHECK-NEXT: %[[ONE:.*]] = arith.constant 1 : i32 + // CHECK-NEXT: %[[EMBOXCHAR:.*]] = fir.emboxchar %[[PLACEHOLDER]], %[[ONE]] : (!fir.ref>, i32) -> !fir.boxchar<1> + // CHECK-NEXT: omp.target private(@boxchar_firstprivatizer %[[EMBOXCHAR]] -> %{{.*}} [map_idx=0] : !fir.boxchar<1>) + %0 = fir.alloca !fir.boxchar<1> + %1 = fir.dummy_scope : !fir.dscope + %2:2 = fir.unboxchar %arg : (!fir.boxchar<1>) -> (!fir.ref>, index) + %3:2 = hlfir.declare %2#0 typeparams %2#1 dummy_scope %1 {uniq_name = "arg"} : (!fir.ref>, index, !fir.dscope) -> (!fir.boxchar<1>, !fir.ref>) + omp.target private(@boxchar_firstprivatizer %3#0 -> %arg3 [map_idx=0] : !fir.boxchar<1>) { + omp.terminator + } + return + } + + func.func private @foo() -> () attributes {omp.declare_target = #omp.declaretarget} + fir.global internal @global_scalar constant : i32 { + %0 = arith.constant 10 : i32 + fir.has_value %0 : i32 + } + omp.private {type = firstprivate} @privatizer : i32 copy { + ^bb0(%arg0: !fir.ref, %arg1: !fir.ref): + %0 = fir.load %arg0 : !fir.ref + hlfir.assign %0 to %arg1 : i32, !fir.ref + omp.yield(%arg1 : !fir.ref) + } + omp.declare_reduction @reduction : i32 + init { + ^bb0(%arg: i32): + %0 = arith.constant 0 : i32 + omp.yield (%0 : i32) + } + combiner { + ^bb1(%arg0: i32, %arg1: i32): + %1 = arith.addi %arg0, %arg1 : i32 + omp.yield (%1 : i32) + } + omp.private {type = firstprivate} @boxchar_firstprivatizer : !fir.boxchar<1> init { + ^bb0(%arg0: !fir.boxchar<1>, %arg1: !fir.boxchar<1>): + %0:2 = fir.unboxchar %arg0 : (!fir.boxchar<1>) -> (!fir.ref>, index) + %1 = fir.allocmem !fir.char<1,?>(%0#1 : index) {bindc_name = "", uniq_name = ""} + %2 = fir.emboxchar %1, %0#1 : (!fir.heap>, index) -> !fir.boxchar<1> + omp.yield(%2 : !fir.boxchar<1>) + } copy { + ^bb0(%arg0: !fir.boxchar<1>, %arg1: !fir.boxchar<1>): + hlfir.assign %arg0 to %arg1 : !fir.boxchar<1>, !fir.boxchar<1> + omp.yield(%arg1 : !fir.boxchar<1>) + } dealloc { + ^bb0(%arg0: !fir.boxchar<1>): + %0:2 = fir.unboxchar %arg0 : (!fir.boxchar<1>) -> (!fir.ref>, index) + %1 = fir.convert %0#0 : (!fir.ref>) -> !fir.heap> + fir.freemem %1 : !fir.heap> + omp.yield + } +} diff --git a/flang/test/Transforms/omp-function-filtering.mlir b/flang/test/Transforms/OpenMP/function-filtering.mlir similarity index 100% rename from flang/test/Transforms/omp-function-filtering.mlir rename to flang/test/Transforms/OpenMP/function-filtering.mlir diff --git a/flang/test/Transforms/omp-map-info-finalization-implicit-field.fir b/flang/test/Transforms/omp-map-info-finalization-implicit-field.fir index 632525b4b43c9..3e84721c4351d 100644 --- a/flang/test/Transforms/omp-map-info-finalization-implicit-field.fir +++ b/flang/test/Transforms/omp-map-info-finalization-implicit-field.fir @@ -1,5 +1,6 @@ // Tests that we implicitly map alloctable fields of a record when referenced in // a target region. +// XFAIL: * // RUN: fir-opt --split-input-file --omp-map-info-finalization %s | FileCheck %s diff --git a/flang/test/Transforms/omp-map-info-finalization.fir b/flang/test/Transforms/omp-map-info-finalization.fir index b30a2fc4e9a80..63ad9aad32414 100644 --- a/flang/test/Transforms/omp-map-info-finalization.fir +++ b/flang/test/Transforms/omp-map-info-finalization.fir @@ -1,4 +1,4 @@ -// RUN: fir-opt --split-input-file --omp-map-info-finalization %s | FileCheck %s +// RUN: fir-opt --split-input-file --omp-map-info-finalization %s | FileCheck %s func.func @test_descriptor_expansion_pass(%arg0: !fir.box>) { %0 = fir.alloca !fir.box> @@ -31,12 +31,12 @@ func.func @test_descriptor_expansion_pass(%arg0: !fir.box>) { // CHECK: %[[DECLARE2:.*]]:2 = hlfir.declare %[[ALLOCA2]] {fortran_attrs = #fir.var_attrs, uniq_name = "test2"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) // CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%{{.*}} : index) upper_bound(%{{.*}} : index) extent(%{{.*}} : index) stride(%{{.*}} : index) start_idx(%{{.*}} : index) {stride_in_bytes = true} // CHECK: %[[BASE_ADDR_OFF:.*]] = fir.box_offset %[[DECLARE2]]#1 base_addr : (!fir.ref>>) -> !fir.llvm_ptr> -// CHECK: %[[DESC_MEMBER_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE2]]#1 : !fir.ref>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[BASE_ADDR_OFF]] : !fir.llvm_ptr>) -> !fir.llvm_ptr> {name = ""} -// CHECK: %[[DESC_PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE2]]#1 : !fir.ref>>, !fir.box>) map_clauses(to) capture(ByRef) members(%[[DESC_MEMBER_MAP]] : [0] : !fir.llvm_ptr>) -> !fir.ref>> +// CHECK: %[[DESC_MEMBER_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE2]]#1 : !fir.ref>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[BASE_ADDR_OFF]] : !fir.llvm_ptr>) -> !fir.llvm_ptr> {name = ""} +// CHECK: %[[DESC_PARENT_MAP:.*]] = omp.map.info var_ptr(%[[DECLARE2]]#1 : !fir.ref>>, !fir.box>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[DESC_MEMBER_MAP]] : [0] : !fir.llvm_ptr>) -> !fir.ref>> // CHECK: fir.store %[[DECLARE1]]#1 to %[[ALLOCA]] : !fir.ref>> // CHECK: %[[BASE_ADDR_OFF_2:.*]] = fir.box_offset %[[ALLOCA]] base_addr : (!fir.ref>>) -> !fir.llvm_ptr>> -// CHECK: %[[DESC_MEMBER_MAP_2:.*]] = omp.map.info var_ptr(%[[ALLOCA]] : !fir.ref>>, i32) map_clauses(from) capture(ByRef) var_ptr_ptr(%[[BASE_ADDR_OFF_2]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {name = ""} -// CHECK: %[[DESC_PARENT_MAP_2:.*]] = omp.map.info var_ptr(%[[ALLOCA]] : !fir.ref>>, !fir.box>) map_clauses(to) capture(ByRef) members(%[[DESC_MEMBER_MAP_2]] : [0] : !fir.llvm_ptr>>) -> !fir.ref> +// CHECK: %[[DESC_MEMBER_MAP_2:.*]] = omp.map.info var_ptr(%[[ALLOCA]] : !fir.ref>>, i32) map_clauses(from) capture(ByRef) var_ptr_ptr(%[[BASE_ADDR_OFF_2]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {name = ""} +// CHECK: %[[DESC_PARENT_MAP_2:.*]] = omp.map.info var_ptr(%[[ALLOCA]] : !fir.ref>>, !fir.box>) map_clauses(always, descriptor, to) capture(ByRef) members(%[[DESC_MEMBER_MAP_2]] : [0] : !fir.llvm_ptr>>) -> !fir.ref> // CHECK: omp.target map_entries(%[[DESC_PARENT_MAP]] -> %[[ARG1:.*]], %[[DESC_PARENT_MAP_2]] -> %[[ARG2:.*]], %[[DESC_MEMBER_MAP]] -> %[[ARG3:.*]], %[[DESC_MEMBER_MAP_2]] -> %[[ARG4:.*]] : {{.*}}) { // ----- @@ -111,8 +111,8 @@ func.func @dtype_alloca_op_block_add(%arg0: !fir.ref>) -> !fir.ref>>> // CHECK: %[[MEMBER_BASE_ADDR:.*]] = fir.box_offset %[[MEMBER_COORD:.*]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -// CHECK: %[[MAP_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} -// CHECK: %[[MAP_MEMBER_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {name = "one_l%array_j"} +// CHECK: %[[MAP_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} +// CHECK: %[[MAP_MEMBER_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {name = "one_l%array_j"} // CHECK: %[[MAP_MEMBER_PARENT:.*]] = omp.map.info var_ptr(%[[ALLOCA]]#0 : !fir.ref<[[REC_TY]]>>, [[REC_TY]]>) map_clauses(tofrom) capture(ByRef) members(%10, %9 : [4], [4, 0] : !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref<[[REC_TY]]>> {{.*}} // CHECK: omp.target map_entries(%[[MAP_MEMBER_PARENT]] -> %[[ARG1:.*]], %[[MAP_MEMBER_DESCRIPTOR]] -> %[[ARG2:.*]], %[[MAP_MEMBER_BASE_ADDR]] -> %[[ARG3:.*]] : !fir.ref<[[REC_TY]]>>, !fir.ref>>>, !fir.llvm_ptr>>) { @@ -151,14 +151,14 @@ func.func @alloca_dtype_map_op_block_add(%arg0 : !fir.ref>>> // CHECK: %[[ALLOCATABLE_MEMBER_COORD:.*]] = fir.coordinate_of %[[LOAD_ALLOCA]], array_j : (!fir.box>>) -> !fir.ref>>> // CHECK: %[[ALLOCATABLE_MEMBER_BASE_ADDR:.*]] = fir.box_offset %[[ALLOCATABLE_MEMBER_COORD]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -// CHECK: %[[MAP_ALLOCA_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[ALLOCATABLE_MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[ALLOCATABLE_MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} -// CHECK: %[[MAP_ALLOCA_MEMBER_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[ALLOCATABLE_MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {{.*}} +// CHECK: %[[MAP_ALLOCA_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[ALLOCATABLE_MEMBER_COORD]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[ALLOCATABLE_MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} +// CHECK: %[[MAP_ALLOCA_MEMBER_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[ALLOCATABLE_MEMBER_COORD]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {{.*}} // CHECK: %[[LOAD_ALLOCA2:.*]] = fir.load %[[ALLOCA]]#0 : !fir.ref>>> // CHECK: %[[REGULAR_MEMBER_COORD:.*]] = fir.coordinate_of %[[LOAD_ALLOCA2]], k : (!fir.box>>) -> !fir.ref // CHECK: %[[MAP_REGULAR_MEMBER:.*]] = omp.map.info var_ptr(%[[REGULAR_MEMBER_COORD]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {{.*}} // CHECK: %[[ALLOCATABLE_PARENT_BASE_ADDR:.*]] = fir.box_offset %[[ALLOCA]]#1 base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -// CHECK: %[[MAP_ALLOCA_PARENT_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[ALLOCA]]#1 : !fir.ref>>>, !fir.type<[[REC_TY]]>) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[ALLOCATABLE_PARENT_BASE_ADDR]] : !fir.llvm_ptr>>) -> !fir.llvm_ptr>> {{.*}} -// CHECK: %[[MAP_PARENT_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[ALLOCA]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) members(%18, %13, %12, %16 : [0], [0, 4], [0, 4, 0], [0, 5] : !fir.llvm_ptr>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) -> !fir.ref>>> {{.*}} +// CHECK: %[[MAP_ALLOCA_PARENT_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[ALLOCA]]#1 : !fir.ref>>>, !fir.type<[[REC_TY]]>) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[ALLOCATABLE_PARENT_BASE_ADDR]] : !fir.llvm_ptr>>) -> !fir.llvm_ptr>> {{.*}} +// CHECK: %[[MAP_PARENT_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[ALLOCA]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) members(%18, %13, %12, %16 : [0], [0, 4], [0, 4, 0], [0, 5] : !fir.llvm_ptr>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) -> !fir.ref>>> {{.*}} // CHECK: omp.target map_entries(%[[MAP_PARENT_DESCRIPTOR]] -> %[[ARG1:.*]], %[[MAP_ALLOCA_PARENT_BASE_ADDR]] -> %[[ARG2:.*]], %[[MAP_ALLOCA_MEMBER_DESCRIPTOR]] -> %[[ARG3:.*]], %[[MAP_ALLOCA_MEMBER_BASE_ADDR]] -> %[[ARG4:.*]], %[[MAP_REGULAR_MEMBER]] -> %[[ARG5:.*]] : !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) { // ----- @@ -201,15 +201,15 @@ func.func @alloca_dtype_map_op_block_add(%arg0 : !fir.ref>>) -> !fir.ref,array_k:!fir.box>>,k:i32}]]>> // CHECK: %[[NESTED_ALLOCA_MEMBER:.*]] = fir.coordinate_of %[[INTERMEDIATE_DTYPE_NESTED_MEMBER]], array_k : (!fir.ref>) -> !fir.ref>>> // CHECK: %[[NESTED_ALLOCA_MEMBER_BASE_ADDR:.*]] = fir.box_offset %[[NESTED_ALLOCA_MEMBER]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -// CHECK: %[[MAP_NESTED_ALLOCA_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[NESTED_ALLOCA_MEMBER]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[NESTED_ALLOCA_MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} -// CHECK: %[[MAP_NESTED_ALLOCA_MEMBER:.*]] = omp.map.info var_ptr(%[[NESTED_ALLOCA_MEMBER]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {{.*}} +// CHECK: %[[MAP_NESTED_ALLOCA_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[NESTED_ALLOCA_MEMBER]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[NESTED_ALLOCA_MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} +// CHECK: %[[MAP_NESTED_ALLOCA_MEMBER:.*]] = omp.map.info var_ptr(%[[NESTED_ALLOCA_MEMBER]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {{.*}} // CHECK: %[[ALLOCA_LOAD2:.*]] = fir.load %[[ALLOCA]]#0 : !fir.ref>>> // CHECK: %[[INTERMEDIATE_DTYPE_NESTED_MEMBER2:.*]] = fir.coordinate_of %[[ALLOCA_LOAD2]], nest : (!fir.box>>) -> !fir.ref> // CHECK: %[[NESTED_REGULAR_MEMBER:.*]] = fir.coordinate_of %[[INTERMEDIATE_DTYPE_NESTED_MEMBER2]], k : (!fir.ref>) -> !fir.ref // CHECK: %[[MAP_NESTED_REGULAR_MEMBER:.*]] = omp.map.info var_ptr(%[[NESTED_REGULAR_MEMBER:.*]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {{.*}} // CHECK: %[[ALLOCATABLE_PARENT_BASE_ADDR:.*]] = fir.box_offset %[[ALLOCA]]#1 base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -// CHECK: %[[MAP_ALLOCATABLE_PARENT_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[ALLOCA]]#1 : !fir.ref>>>, !fir.type<[[REC_TY]]>) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[ALLOCATABLE_PARENT_BASE_ADDR]] : !fir.llvm_ptr>>) -> !fir.llvm_ptr>> {{.*}} -// CHECK: %[[MAP_ALLOCATABLE_PARENT_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[ALLOCA]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) members(%21, %15, %14, %19 : [0], [0, 6, 2], [0, 6, 2, 0], [0, 6, 3] : !fir.llvm_ptr>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) -> !fir.ref>>> {{.*}} +// CHECK: %[[MAP_ALLOCATABLE_PARENT_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[ALLOCA]]#1 : !fir.ref>>>, !fir.type<[[REC_TY]]>) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[ALLOCATABLE_PARENT_BASE_ADDR]] : !fir.llvm_ptr>>) -> !fir.llvm_ptr>> {{.*}} +// CHECK: %[[MAP_ALLOCATABLE_PARENT_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[ALLOCA]]#1 : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) members(%21, %15, %14, %19 : [0], [0, 6, 2], [0, 6, 2, 0], [0, 6, 3] : !fir.llvm_ptr>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) -> !fir.ref>>> {{.*}} // CHECK: omp.target map_entries(%[[MAP_ALLOCATABLE_PARENT_DESCRIPTOR]] -> %[[ARG1:.*]], %[[MAP_ALLOCATABLE_PARENT_BASE_ADDR]] -> %[[ARG2:.*]], %[[MAP_NESTED_ALLOCA_MEMBER]] -> %[[ARG3:.*]], %[[MAP_NESTED_ALLOCA_MEMBER_BASE_ADDR]] -> %[[ARG4:.*]], %[[MAP_NESTED_REGULAR_MEMBER]] -> %[[ARG5:.*]] : !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref>>>, !fir.llvm_ptr>>, !fir.ref) { // ----- @@ -244,8 +244,8 @@ func.func @alloca_dtype_map_op_block_add(%arg0 : !fir.ref>) -> !fir.ref,array_k:!fir.box>>,k:i32}]]>> // CHECK: %[[ALLOCATABLE_MEMBER:.*]] = fir.coordinate_of %[[NESTED_DTYPE_COORD]], array_k : (!fir.ref>) -> !fir.ref>>> // CHECK: %[[ALLOCATABLE_MEMBER_BASE_ADDR:.*]] = fir.box_offset %[[ALLOCATABLE_MEMBER]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -// CHECK: %[[MAP_ALLOCATABLE_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[ALLOCATABLE_MEMBER]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[ALLOCATABLE_MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} -// CHECK: %[[MAP_ALLOCATABLE_MEMBER_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[ALLOCATABLE_MEMBER]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {{.*}} +// CHECK: %[[MAP_ALLOCATABLE_MEMBER_BASE_ADDR:.*]] = omp.map.info var_ptr(%[[ALLOCATABLE_MEMBER]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[ALLOCATABLE_MEMBER_BASE_ADDR]] : !fir.llvm_ptr>>) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {{.*}} +// CHECK: %[[MAP_ALLOCATABLE_MEMBER_DESCRIPTOR:.*]] = omp.map.info var_ptr(%[[ALLOCATABLE_MEMBER]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {{.*}} // CHECK: %[[MAP_PARENT:.*]] = omp.map.info var_ptr(%[[ALLOCA]]#0 : !fir.ref>, !fir.type<[[REC_TY]]>) map_clauses(tofrom) capture(ByRef) members(%12, %11 : [6, 2], [6, 2, 0] : !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref> {{.*}} // CHECK: omp.target map_entries(%[[MAP_PARENT]] -> %[[ARG1:.*]], %[[MAP_ALLOCATABLE_MEMBER_DESCRIPTOR]] -> %[[ARG2:.*]], %[[MAP_ALLOCATABLE_MEMBER_BASE_ADDR]] -> %[[ARG3:.*]] : !fir.ref>, !fir.ref>>>, !fir.llvm_ptr>>) { @@ -277,14 +277,14 @@ func.func @alloca_dtype_map_op_block_add(%arg0 : !fir.ref>) -> (!fir.ref>, !fir.ref>) // CHECK: %[[DESC_1:.*]] = fir.coordinate_of %[[DECLARE]]#0, vertexes : (!fir.ref>) -> !fir.ref>>,vertexy:!fir.box>>}]]>>>>> // CHECK: %[[BASE_ADDR_1:.*]] = fir.box_offset %[[DESC_1]] base_addr : (!fir.ref>>>>) -> !fir.llvm_ptr>>> -// CHECK: %[[BASE_ADDR_MAP_1:.*]] = omp.map.info var_ptr(%[[DESC_1]] : !fir.ref>>>>, !fir.type<[[REC_TY2]]>) map_clauses(storage) capture(ByRef) var_ptr_ptr(%[[BASE_ADDR_1]] : !fir.llvm_ptr>>>) bounds(%{{.*}}) -> !fir.llvm_ptr>>> {{.*}} -// CHECK: %[[DESC_MAP_1:.*]] = omp.map.info var_ptr(%[[DESC_1]] : !fir.ref>>>>, !fir.box>>>) map_clauses(to) capture(ByRef) -> !fir.ref>>>> {{.*}} +// CHECK: %[[BASE_ADDR_MAP_1:.*]] = omp.map.info var_ptr(%[[DESC_1]] : !fir.ref>>>>, !fir.type<[[REC_TY2]]>) map_clauses(storage) capture(ByRef) var_ptr_ptr(%[[BASE_ADDR_1]] : !fir.llvm_ptr>>>) bounds(%{{.*}}) -> !fir.llvm_ptr>>> {{.*}} +// CHECK: %[[DESC_MAP_1:.*]] = omp.map.info var_ptr(%[[DESC_1]] : !fir.ref>>>>, !fir.box>>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>>> {{.*}} // CHECK: %[[DESC_LD_1:.*]] = fir.load %[[DESC_1]] : !fir.ref>>>> // CHECK: %[[MEMBER_ACCESS_1:.*]] = fir.coordinate_of %[[DESC_LD_1]], %{{.*}} : (!fir.box>>>, index) -> !fir.ref> // CHECK: %[[DESC_2:.*]] = fir.coordinate_of %[[MEMBER_ACCESS_1]], vertexy : (!fir.ref>) -> !fir.ref>>> // CHECK: %[[BASE_ADDR_2:.*]] = fir.box_offset %[[DESC_2]] base_addr : (!fir.ref>>>) -> !fir.llvm_ptr>> -// CHECK: %[[BASE_ADDR_MAP_2:.*]] = omp.map.info var_ptr(%[[DESC_2]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[BASE_ADDR_2]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {{.*}} -// CHECK: %[[DESC_MAP_2:.*]] = omp.map.info var_ptr(%[[DESC_2]] : !fir.ref>>>, !fir.box>>) map_clauses(to) capture(ByRef) -> !fir.ref>>> {{.*}} +// CHECK: %[[BASE_ADDR_MAP_2:.*]] = omp.map.info var_ptr(%[[DESC_2]] : !fir.ref>>>, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%[[BASE_ADDR_2]] : !fir.llvm_ptr>>) bounds(%{{.*}}) -> !fir.llvm_ptr>> {{.*}} +// CHECK: %[[DESC_MAP_2:.*]] = omp.map.info var_ptr(%[[DESC_2]] : !fir.ref>>>, !fir.box>>) map_clauses(always, descriptor, to) capture(ByRef) -> !fir.ref>>> {{.*}} // CHECK: %[[TOP_PARENT_MAP:.*]] = omp.map.info var_ptr(%0#1 : !fir.ref>, !fir.type<[[REC_TY]]>) map_clauses(storage) capture(ByRef) members(%6, %5, %14, %13 : [1], [1, 0], [1, 0, 2], [1, 0, 2, 0] : !fir.ref>>>>, !fir.llvm_ptr>>>, !fir.ref>>>, !fir.llvm_ptr>>) -> !fir.ref> {{{.*}} partial_map = true} // CHECK: omp.target map_entries(%[[TOP_PARENT_MAP]] -> %{{.*}}, %[[DESC_MAP_1]] -> %{{.*}}, %[[BASE_ADDR_MAP_1]] -> %{{.*}}, %[[DESC_MAP_2]] -> %{{.*}}, %[[BASE_ADDR_MAP_2]] -> %{{.*}} : !fir.ref>, !fir.ref>>>>, !fir.llvm_ptr>>>, !fir.ref>>>, !fir.llvm_ptr>>) { diff --git a/flang/test/Transforms/stack-arrays-hlfir.f90 b/flang/test/Transforms/stack-arrays-hlfir.f90 index e70a1d9b89216..06749b7ca88af 100644 --- a/flang/test/Transforms/stack-arrays-hlfir.f90 +++ b/flang/test/Transforms/stack-arrays-hlfir.f90 @@ -73,7 +73,7 @@ end subroutine omp_target_wsloop ! CHECK-NOT: fir.freemem ! CHECK: omp.teams { ! CHECK: fir.alloca !fir.array<2xi64> -! CHECK: omp.distribute private({{.*}}) { +! CHECK: omp.distribute { ! CHECK: omp.loop_nest {{.*}} { ! CHECK-NOT: fir.allocmem ! CHECK-NOT: fir.freemem diff --git a/flang/tools/bbc/bbc.cpp b/flang/tools/bbc/bbc.cpp index 8b12da3a7b50a..a427100f1e81c 100644 --- a/flang/tools/bbc/bbc.cpp +++ b/flang/tools/bbc/bbc.cpp @@ -142,6 +142,12 @@ static llvm::cl::opt llvm::cl::desc("enable openmp device compilation"), llvm::cl::init(false)); +static llvm::cl::opt + deferDescMap("fdefer-desc-map", + llvm::cl::desc("disable or enable OpenMP deference of mapping " + "for top-level descriptors"), + llvm::cl::init(true)); + static llvm::cl::opt enableDoConcurrentToOpenMPConversion( "fdo-concurrent-to-openmp", llvm::cl::desc( @@ -169,7 +175,7 @@ static llvm::cl::list targetTriplesOpenMP( static llvm::cl::opt setOpenMPVersion("fopenmp-version", llvm::cl::desc("OpenMP standard version"), - llvm::cl::init(31)); + llvm::cl::init(52)); static llvm::cl::opt setOpenMPTargetDebug( "fopenmp-target-debug", @@ -346,6 +352,7 @@ static llvm::LogicalResult runOpenMPPasses(mlir::ModuleOp mlirModule) { .Case("host", DoConcurrentMappingKind::DCMK_Host) .Case("device", DoConcurrentMappingKind::DCMK_Device) .Default(DoConcurrentMappingKind::DCMK_None); + opts.deferDescMap = deferDescMap; fir::createOpenMPFIRPassPipeline(pm, opts); (void)mlir::applyPassManagerCLOptions(pm); diff --git a/flang/tools/f18/CMakeLists.txt b/flang/tools/f18/CMakeLists.txt index 715992c756c4b..a2b4d73f48384 100644 --- a/flang/tools/f18/CMakeLists.txt +++ b/flang/tools/f18/CMakeLists.txt @@ -4,9 +4,16 @@ set(LLVM_LINK_COMPONENTS Support ) +# Define the list of Fortran module files that need to be compiled +# to produce an object file for inclusion into the flang_rt.runtime +# library. +set(MODULES_WITH_IMPLEMENTATION + "iso_fortran_env_impl" +) + # Define the list of Fortran module files for which it is # sufficient to generate the module file via -fsyntax-only. -set(MODULES +set(MODULES_WITHOUT_IMPLEMENTATION "__fortran_builtins" "__fortran_ieee_exceptions" "__fortran_type_info" @@ -22,9 +29,12 @@ set(MODULES "ieee_features" "iso_c_binding" "iso_fortran_env" + "f90deviceio" "iso_fortran_env_impl" ) +set(MODULES ${MODULES_WITH_IMPLEMENTATION} ${MODULES_WITHOUT_IMPLEMENTATION}) + # Check if 128-bit float computations can be done via long double. check_cxx_source_compiles( "#include @@ -107,6 +117,11 @@ if (NOT CMAKE_CROSSCOMPILING) set(compile_with "-fsyntax-only") set(object_output "") set(include_in_link FALSE) + if(${filename} IN_LIST MODULES_WITH_IMPLEMENTATION AND FLANG_INCLUDE_RUNTIME) + set(object_output "${CMAKE_CURRENT_BINARY_DIR}/${filename}${CMAKE_CXX_OUTPUT_EXTENSION}") + set(compile_with -c -o ${object_output}) + set(include_in_link TRUE) + endif() set(base ${FLANG_INTRINSIC_MODULES_DIR}/${filename}) # TODO: We may need to flag this with conditional, in case Flang is built w/o OpenMP support diff --git a/flang/tools/flang-driver/CMakeLists.txt b/flang/tools/flang-driver/CMakeLists.txt index b5d6727025121..801fc324e888d 100644 --- a/flang/tools/flang-driver/CMakeLists.txt +++ b/flang/tools/flang-driver/CMakeLists.txt @@ -44,7 +44,3 @@ if(FLANG_PLUGIN_SUPPORT) endif() install(TARGETS flang DESTINATION "${CMAKE_INSTALL_BINDIR}") - -# Keep "flang-new" as a symlink for backwards compatiblity. Remove once "flang" -# is a widely adopted name. -add_flang_symlink(flang-new flang) diff --git a/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.pass.cpp b/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.pass.cpp index f15f1b96b4b27..61fd0a804ecd3 100644 --- a/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.pass.cpp +++ b/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.pass.cpp @@ -62,14 +62,14 @@ int main(int, char**) { testbuf sb1; std::ostream os1(&sb1); - int n1 = 0; + int n1; os1 << &n1; assert(os1.good()); std::string s1(sb1.str()); testbuf sb2; std::ostream os2(&sb2); - int n2 = 0; + int n2; os2 << &n2; assert(os2.good()); std::string s2(sb2.str()); diff --git a/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.volatile.pass.cpp b/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.volatile.pass.cpp index 6a1cde15a69bd..69d84f640d54e 100644 --- a/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.volatile.pass.cpp +++ b/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.volatile.pass.cpp @@ -61,7 +61,7 @@ class testbuf : public std::basic_streambuf { int main(int, char**) { testbuf sb1; std::ostream os1(&sb1); - int n1 = 0; + int n1; os1 << &n1; assert(os1.good()); std::string s1 = sb1.str(); @@ -74,7 +74,7 @@ int main(int, char**) { testbuf sb3; std::ostream os3(&sb3); - volatile int n3 = 0; + volatile int n3; os3 << &n3; assert(os3.good()); std::string s3 = sb3.str(); diff --git a/lld/Common/Args.cpp b/lld/Common/Args.cpp index 5546b2aece641..4121f7b851f5d 100644 --- a/lld/Common/Args.cpp +++ b/lld/Common/Args.cpp @@ -11,14 +11,14 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/CommandFlags.h" #include "llvm/Option/ArgList.h" #include "llvm/Support/Path.h" +#include "llvm/TargetParser/TargetParser.h" using namespace llvm; using namespace lld; -// TODO(sbc): Remove this once CGOptLevel can be set completely based on bitcode -// function metadata. int lld::args::getCGOptLevel(int optLevelLTO) { return std::clamp(optLevelLTO, 2, 3); } diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp index e52d3a0e11113..1991d660ccc95 100644 --- a/lld/ELF/Driver.cpp +++ b/lld/ELF/Driver.cpp @@ -643,7 +643,7 @@ static void checkZOptions(Ctx &ctx, opt::InputArgList &args) { constexpr const char *saveTempsValues[] = { "resolution", "preopt", "promote", "internalize", "import", - "opt", "precodegen", "prelink", "combinedindex"}; + "opt", "precodegen", "prelink", "combinedindex", "asm" }; LinkerDriver::LinkerDriver(Ctx &ctx) : ctx(ctx) {} @@ -1536,13 +1536,26 @@ static void readConfigs(Ctx &ctx, opt::InputArgList &args) { // --save-temps implies saving all temps. ctx.arg.saveTempsArgs.insert_range(saveTempsValues); } else { + llvm::DenseSet toRemove; for (auto *arg : args.filtered(OPT_save_temps_eq)) { + llvm::DenseSet *set = &ctx.arg.saveTempsArgs; StringRef s = arg->getValue(); + if (s.consume_front("no-")) { + set = &toRemove; + } if (llvm::is_contained(saveTempsValues, s)) - ctx.arg.saveTempsArgs.insert(s); + set->insert(s); else ErrAlways(ctx) << "unknown --save-temps value: " << s; } + // All subtractive values implies starting with all temps + if (ctx.arg.saveTempsArgs.empty() && !toRemove.empty()) { + for (const char *s : saveTempsValues) + ctx.arg.saveTempsArgs.insert(s); + } + for (auto rm : toRemove) { + ctx.arg.saveTempsArgs.erase(rm); + } } ctx.arg.searchPaths = args::getStrings(args, OPT_library_path); @@ -1602,7 +1615,7 @@ static void readConfigs(Ctx &ctx, opt::InputArgList &args) { ctx.arg.trace = args.hasArg(OPT_trace); ctx.arg.undefined = args::getStrings(args, OPT_undefined); ctx.arg.undefinedVersion = - args.hasFlag(OPT_undefined_version, OPT_no_undefined_version, false); + args.hasFlag(OPT_undefined_version, OPT_no_undefined_version, true); ctx.arg.unique = args.hasArg(OPT_unique); ctx.arg.useAndroidRelrTags = args.hasFlag( OPT_use_android_relr_tags, OPT_no_use_android_relr_tags, false); diff --git a/lld/ELF/LTO.cpp b/lld/ELF/LTO.cpp index 80c6d2482f9fa..f8be9254d145b 100644 --- a/lld/ELF/LTO.cpp +++ b/lld/ELF/LTO.cpp @@ -155,6 +155,8 @@ static lto::Config createConfig(Ctx &ctx) { if (ctx.arg.ltoEmitAsm) { c.CGFileType = CodeGenFileType::AssemblyFile; + } + if (ctx.arg.ltoEmitAsm || ctx.arg.saveTempsArgs.contains("asm")) { c.Options.MCOptions.AsmVerbose = true; } diff --git a/lld/ELF/Options.td b/lld/ELF/Options.td index 75184de496448..fb9e5df648c75 100644 --- a/lld/ELF/Options.td +++ b/lld/ELF/Options.td @@ -526,7 +526,7 @@ defm unresolved_symbols: Eq<"unresolved-symbols", "Determine how to handle unresolved symbols">; defm undefined_version: B<"undefined-version", - "Allow unused version in version script (disabled by default)", + "Allow unused version in version script (default)", "Report version scripts that refer undefined symbols">; defm rsp_quoting: EEq<"rsp-quoting", "Quoting style for response files">, diff --git a/lld/docs/ld.lld.1 b/lld/docs/ld.lld.1 index bb1a53ad1112a..5f30c9e0161af 100644 --- a/lld/docs/ld.lld.1 +++ b/lld/docs/ld.lld.1 @@ -393,8 +393,8 @@ Do not set the text data sections to be writable, page align sections. Disable target-specific relaxations. For x86-64 this disables R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX GOT optimization. .It Fl -no-rosegment Do not put read-only non-executable sections in their own segment. -.It Fl -undefined-version -Do not report version scripts that refer to undefined symbols. +.It Fl -no-undefined-version +Report version scripts that refer undefined symbols. .It Fl -no-undefined Report unresolved symbols even if the linker is creating a shared library. .It Fl -no-warn-mismatch diff --git a/lld/test/COFF/lto-cache-errors.ll b/lld/test/COFF/lto-cache-errors.ll index a46190a81b623..7486c2a7c36b0 100644 --- a/lld/test/COFF/lto-cache-errors.ll +++ b/lld/test/COFF/lto-cache-errors.ll @@ -1,4 +1,4 @@ -; REQUIRES: x86, non-root-user +; REQUIRES: x86, non-root-user, disable_temporarily ;; Not supported on windows since we use permissions to deny the creation ; UNSUPPORTED: system-windows diff --git a/lld/test/COFF/thinlto-emit-imports.ll b/lld/test/COFF/thinlto-emit-imports.ll index 26af017b17b2c..2eac96f29933d 100644 --- a/lld/test/COFF/thinlto-emit-imports.ll +++ b/lld/test/COFF/thinlto-emit-imports.ll @@ -1,3 +1,4 @@ +; REQUIRES: jenkins-permissions-issue ; REQUIRES: x86, non-root-user ; Generate summary sections and test lld handling. diff --git a/lld/test/ELF/lto/devirt_validate_vtable_typeinfos.ll b/lld/test/ELF/lto/devirt_validate_vtable_typeinfos.ll index ca7df3e4ba606..853c12cf6c868 100644 --- a/lld/test/ELF/lto/devirt_validate_vtable_typeinfos.ll +++ b/lld/test/ELF/lto/devirt_validate_vtable_typeinfos.ll @@ -57,7 +57,7 @@ ; RUN: llvm-dis %t1_hybrid.o.4.opt.bc -o - | FileCheck %s --check-prefixes=CHECK-COMMON-IR-LABEL,CHECK-VALIDATE-IR ;; Regular LTO WPD -; RUN: ld.lld %t1_regular.o %t2.o -o %t4_regular -save-temps --lto-whole-program-visibility --lto-validate-all-vtables-have-type-infos \ +; RUN: ld.lld %t1_regular.o %t2.o -o %t4_regular --save-temps=no-asm --lto-whole-program-visibility --lto-validate-all-vtables-have-type-infos \ ; RUN: -mllvm -pass-remarks=. 2>&1 | FileCheck %s --check-prefix=VALIDATE ; RUN: llvm-dis %t4_regular.0.4.opt.bc -o - | FileCheck %s --check-prefixes=CHECK-COMMON-IR-LABEL,CHECK-VALIDATE-IR @@ -74,7 +74,7 @@ ; RUN: llvm-dis %t1_hybrid.o.4.opt.bc -o - | FileCheck %s --check-prefixes=CHECK-COMMON-IR-LABEL,CHECK-VALIDATE-IR ;; Regular LTO WPD -; RUN: ld.lld %t1_regular.o %t2.so -o %t5_regular -save-temps --lto-whole-program-visibility --lto-validate-all-vtables-have-type-infos \ +; RUN: ld.lld %t1_regular.o %t2.so -o %t5_regular --save-temps=no-asm --lto-whole-program-visibility --lto-validate-all-vtables-have-type-infos \ ; RUN: -mllvm -pass-remarks=. 2>&1 | FileCheck %s --check-prefix=VALIDATE ; RUN: llvm-dis %t5_regular.0.4.opt.bc -o - | FileCheck %s --check-prefixes=CHECK-COMMON-IR-LABEL,CHECK-VALIDATE-IR diff --git a/lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll b/lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll index bcb92a1beb17b..c9db867ecc420 100644 --- a/lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll +++ b/lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll @@ -70,7 +70,7 @@ ; RUN: llvm-dis %t.o.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-AONLY-IR ;; Regular LTO WPD -; RUN: ld.lld %t4.o %ta.so -o %t3 -save-temps --lto-whole-program-visibility \ +; RUN: ld.lld %t4.o %ta.so -o %t3 --save-temps=no-asm --lto-whole-program-visibility \ ; RUN: -mllvm -pass-remarks=. \ ; RUN: --export-dynamic-symbol=_ZTV1D 2>&1 | FileCheck %s --check-prefix=REMARK-AONLY ; RUN: llvm-dis %t3.0.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-AONLY-IR @@ -95,7 +95,7 @@ ; RUN: llvm-dis %t.o.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-AONLY-IR ;; Regular LTO WPD -; RUN: ld.lld %t4.o %ta.so -o %t3 -save-temps --lto-whole-program-visibility \ +; RUN: ld.lld %t4.o %ta.so -o %t3 --save-temps=no-asm --lto-whole-program-visibility \ ; RUN: -mllvm -pass-remarks=. \ ; RUN: --dynamic-list=%t.list 2>&1 | FileCheck %s --check-prefix=REMARK-AONLY ; RUN: llvm-dis %t3.0.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-AONLY-IR diff --git a/lld/test/ELF/lto/resolution-err.ll b/lld/test/ELF/lto/resolution-err.ll index 6bc0bfc2f200d..a2b6ab6496312 100644 --- a/lld/test/ELF/lto/resolution-err.ll +++ b/lld/test/ELF/lto/resolution-err.ll @@ -1,3 +1,4 @@ +; REQUIRES: jenkins-permissions-issue ; UNSUPPORTED: system-windows ; REQUIRES: non-root-user ; RUN: llvm-as %s -o %t.bc diff --git a/lld/test/ELF/lto/thinlto-cant-write-index.ll b/lld/test/ELF/lto/thinlto-cant-write-index.ll index 550305986ecd5..2263293e00a06 100644 --- a/lld/test/ELF/lto/thinlto-cant-write-index.ll +++ b/lld/test/ELF/lto/thinlto-cant-write-index.ll @@ -1,3 +1,4 @@ +; REQUIRES: jenkins-permissions-issue ; REQUIRES: x86, non-root-user ; Basic ThinLTO tests. diff --git a/lld/test/ELF/lto/thinlto-emit-imports.ll b/lld/test/ELF/lto/thinlto-emit-imports.ll index 1807a3b59d81c..9b86436af0e58 100644 --- a/lld/test/ELF/lto/thinlto-emit-imports.ll +++ b/lld/test/ELF/lto/thinlto-emit-imports.ll @@ -1,3 +1,4 @@ +; REQUIRES: jenkins-permissions-issue ; REQUIRES: x86, non-root-user ;; Test a few properties not tested by thinlto-index-only.ll diff --git a/lld/test/ELF/riscv-relocatable-align.s b/lld/test/ELF/riscv-relocatable-align.s index 9cd59e96a7196..3cfbedfbc4f55 100644 --- a/lld/test/ELF/riscv-relocatable-align.s +++ b/lld/test/ELF/riscv-relocatable-align.s @@ -5,7 +5,7 @@ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax b1.s -o b1c.o # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax c.s -o cc.o # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c d.s -o dc.o - +# REQUIRES: aLessRISCyTest ## No RELAX. Don't synthesize ALIGN. # RUN: ld.lld -r bc.o dc.o -o bd.ro diff --git a/lld/test/ELF/verdef-defaultver.s b/lld/test/ELF/verdef-defaultver.s index 661f6c4e7da42..7becdcf96422b 100644 --- a/lld/test/ELF/verdef-defaultver.s +++ b/lld/test/ELF/verdef-defaultver.s @@ -4,7 +4,7 @@ # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/verdef-defaultver.s -o %t1 # RUN: echo "V1 { global: a; b; local: *; };" > %t.script # RUN: echo "V2 { global: b; c; } V1;" >> %t.script -# RUN: ld.lld --hash-style=sysv -shared -soname shared %t1 --version-script %t.script --undefined-version -o %t.so +# RUN: ld.lld --hash-style=sysv -shared -soname shared %t1 --version-script %t.script -o %t.so # RUN: llvm-readobj -V --dyn-syms %t.so | FileCheck --check-prefix=DSO %s # DSO: DynamicSymbols [ @@ -195,9 +195,9 @@ # EXE-NEXT: ] # RUN: llvm-mc -filetype=obj -triple=x86_64 b.s -o b.o -# RUN: ld.lld -shared --version-script=%t.script --fatal-warnings --undefined-version %t.so b.o -o b.so +# RUN: ld.lld -shared --version-script=%t.script --fatal-warnings %t.so b.o -o b.so # RUN: llvm-readelf --dyn-syms b.so | FileCheck %s --check-prefix=PREEMPT -# RUN: ld.lld -shared --version-script=%t.script --fatal-warnings --undefined-version b.o %t.so -o b.so +# RUN: ld.lld -shared --version-script=%t.script --fatal-warnings b.o %t.so -o b.so # RUN: llvm-readelf --dyn-syms b.so | FileCheck %s --check-prefix=PREEMPT # PREEMPT-DAG: a@@V1 diff --git a/lld/test/ELF/verdef-dependency.s b/lld/test/ELF/verdef-dependency.s index 89ebc3043ad44..d716436202535 100644 --- a/lld/test/ELF/verdef-dependency.s +++ b/lld/test/ELF/verdef-dependency.s @@ -3,7 +3,7 @@ # RUN: echo "LIBSAMPLE_1.0 { global: a; local: *; };" > %t.script # RUN: echo "LIBSAMPLE_2.0 { global: b; local: *; } LIBSAMPLE_1.0;" >> %t.script # RUN: echo "LIBSAMPLE_3.0 { global: c; } LIBSAMPLE_2.0;" >> %t.script -# RUN: ld.lld --version-script %t.script --undefined-version -shared -soname shared %t.o -o %t.so +# RUN: ld.lld --version-script %t.script -shared -soname shared %t.o -o %t.so # RUN: llvm-readobj -V --dyn-syms %t.so | FileCheck --check-prefix=DSO %s # DSO: VersionDefinitions [ diff --git a/lld/test/ELF/verneed.s b/lld/test/ELF/verneed.s index 734387a62785f..6a90cc48e68fb 100644 --- a/lld/test/ELF/verneed.s +++ b/lld/test/ELF/verneed.s @@ -1,9 +1,9 @@ # REQUIRES: x86 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %S/Inputs/verneed1.s -o %t1.o # RUN: echo "v1 {}; v2 {}; v3 { global: f1; local: *; };" > %t.script -# RUN: ld.lld -shared %t1.o --version-script %t.script --undefined-version -o %t1.so -soname verneed1.so.0 +# RUN: ld.lld -shared %t1.o --version-script %t.script -o %t1.so -soname verneed1.so.0 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %S/Inputs/verneed2.s -o %t2.o -# RUN: ld.lld -shared %t2.o --version-script %t.script --undefined-version -o %t2.so -soname verneed2.so.0 +# RUN: ld.lld -shared %t2.o --version-script %t.script -o %t2.so -soname verneed2.so.0 # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o # RUN: ld.lld --hash-style=sysv %t.o %t1.so %t2.so -o %t diff --git a/lld/test/ELF/version-script-extern-undefined.s b/lld/test/ELF/version-script-extern-undefined.s index 38114229e0ce3..58b4d2e0fe53f 100644 --- a/lld/test/ELF/version-script-extern-undefined.s +++ b/lld/test/ELF/version-script-extern-undefined.s @@ -2,7 +2,7 @@ # RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o # RUN: echo "FOO { global: extern \"C++\" { \"abb(int)\"; }; };" > %t.script -# RUN: ld.lld --version-script %t.script --undefined-version -shared %t.o -o %t.so +# RUN: ld.lld --version-script %t.script -shared %t.o -o %t.so # RUN: llvm-readobj -V %t.so | FileCheck %s # CHECK: VersionSymbols [ diff --git a/lld/test/ELF/version-script-local-preemptible.s b/lld/test/ELF/version-script-local-preemptible.s index 033c9459fb56c..ffb16648dc800 100644 --- a/lld/test/ELF/version-script-local-preemptible.s +++ b/lld/test/ELF/version-script-local-preemptible.s @@ -10,7 +10,7 @@ # RUN: echo "{ global: main; local: *; };" > %t.script # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o -# RUN: ld.lld %t.o %t.so -o %t -version-script %t.script --undefined-version +# RUN: ld.lld %t.o %t.so -o %t -version-script %t.script # RUN: llvm-readelf -r --symbols %t | FileCheck %s # CHECK: Relocation section '.rela.plt' at offset {{.*}} contains 1 entries: diff --git a/lld/test/ELF/version-script-noundef.s b/lld/test/ELF/version-script-noundef.s index b99fb1779f6eb..18916b66f064e 100644 --- a/lld/test/ELF/version-script-noundef.s +++ b/lld/test/ELF/version-script-noundef.s @@ -2,8 +2,7 @@ # RUN: echo "VERSION_1.0 { global: bar; };" > %t.script # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o -# RUN: not ld.lld --version-script %t.script -shared %t.o -o /dev/null \ -# RUN: --fatal-warnings 2>&1 | FileCheck -check-prefix=ERR1 %s +# RUN: ld.lld --version-script %t.script -shared %t.o -o /dev/null --fatal-warnings # RUN: ld.lld --version-script %t.script -shared --undefined-version %t.o -o %t.so # RUN: not ld.lld --version-script %t.script -shared --no-undefined-version \ # RUN: %t.o -o %t.so 2>&1 | FileCheck -check-prefix=ERR1 %s diff --git a/lld/test/ELF/version-script-reassign.s b/lld/test/ELF/version-script-reassign.s index 371390019a4dd..2ed5b15faceda 100644 --- a/lld/test/ELF/version-script-reassign.s +++ b/lld/test/ELF/version-script-reassign.s @@ -24,7 +24,7 @@ # RUN: llvm-readelf --dyn-syms %t.so | FileCheck --check-prefix=V1-SYM %s # RUN: ld.lld -shared %t.o --version-script %t1.ver --version-script %t2w.ver \ -# RUN: -o %t.so --fatal-warnings --undefined-version +# RUN: -o %t.so --fatal-warnings # RUN: llvm-readelf --dyn-syms %t.so | FileCheck --check-prefix=V1-SYM %s # LOCAL: warning: attempt to reassign symbol 'foo' of VER_NDX_LOCAL to version 'V1' diff --git a/lld/test/MachO/thinlto-emit-imports.ll b/lld/test/MachO/thinlto-emit-imports.ll index 90ee6a56b93b8..4bd0b01fe7d7a 100644 --- a/lld/test/MachO/thinlto-emit-imports.ll +++ b/lld/test/MachO/thinlto-emit-imports.ll @@ -1,3 +1,4 @@ +; REQUIRES: jenkins-permissions-issue ; REQUIRES: x86, non-root-user ; RUN: rm -rf %t; split-file %s %t diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index c450ee5a3d72e..af28bf0169108 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -1,3 +1,4 @@ + # See docs/CMake.html for instructions about how to build LLVM with CMake. cmake_minimum_required(VERSION 3.20.0) @@ -1005,6 +1006,7 @@ if(CMAKE_SYSTEM_NAME MATCHES "BSD|Linux|OS390|AIX") else() set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR_default OFF) endif() +set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR_default OFF) set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR ${LLVM_ENABLE_PER_TARGET_RUNTIME_DIR_default} CACHE BOOL "Enable per-target runtimes directory") @@ -1169,9 +1171,9 @@ configure_file( ) # They are not referenced. See set_output_directory(). -set( CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_TOOLS_BINARY_DIR} ) -set( CMAKE_LIBRARY_OUTPUT_DIRECTORY ${LLVM_LIBRARY_DIR} ) -set( CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${LLVM_LIBRARY_DIR} ) +set( CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_BINARY_DIR}/bin ) +set( CMAKE_LIBRARY_OUTPUT_DIRECTORY ${LLVM_BINARY_DIR}/lib${LLVM_LIBDIR_SUFFIX} ) +set( CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${LLVM_BINARY_DIR}/lib${LLVM_LIBDIR_SUFFIX} ) # For up-to-date instructions for installing the TFLite dependency, refer to # the bot setup script: https://github.com/google/ml-compiler-opt/blob/main/buildbot/buildbot_init.sh @@ -1534,6 +1536,18 @@ if (LLVM_INCLUDE_UTILS AND LLVM_INCLUDE_TOOLS) add_subdirectory(utils/llvm-locstats) endif() +# Following variables are required for ROCM backwards compatibility, +# and should be removed in ROCM 7.0 release. +set(ROCM_LLVM_BACKWARD_COMPAT_LINK "" CACHE STRING "Old rocm-llvm install path") +set(ROCM_LLVM_BACKWARD_COMPAT_LINK_TARGET "" CACHE STRING "New rocm-llvm install path") +if (NOT ROCM_LLVM_BACKWARD_COMPAT_LINK STREQUAL "" AND + NOT ROCM_LLVM_BACKWARD_COMPAT_LINK_TARGET STREQUAL "") + install(CODE "execute_process(\ + COMMAND ${CMAKE_COMMAND} -E create_symlink \ + ${ROCM_LLVM_BACKWARD_COMPAT_LINK_TARGET} \ + ${ROCM_LLVM_BACKWARD_COMPAT_LINK})") +endif() + if (XCODE) # For additional targets that you would like to add schemes, specify e.g: # diff --git a/llvm/bindings/ocaml/debuginfo/debuginfo_ocaml.c b/llvm/bindings/ocaml/debuginfo/debuginfo_ocaml.c index 023ebd6d60cd5..b363640bdcdcb 100644 --- a/llvm/bindings/ocaml/debuginfo/debuginfo_ocaml.c +++ b/llvm/bindings/ocaml/debuginfo/debuginfo_ocaml.c @@ -64,6 +64,13 @@ typedef enum { i_DIFlagPtrToMemberRep } LLVMDIFlag_i; +typedef unsigned LLVMDWARFMemorySpace_i; + +static LLVMDWARFMemorySpace +map_DWARFMemorySpace(LLVMDWARFMemorySpace_i MemorySpace) { + return (LLVMDWARFMemorySpace)MemorySpace; +} + static LLVMDIFlags map_DIFlag(LLVMDIFlag_i DIF) { switch (DIF) { case i_DIFlagZero: @@ -493,11 +500,13 @@ value llvm_dibuild_create_basic_type(value Builder, value Name, value llvm_dibuild_create_pointer_type_native(value Builder, value PointeeTy, value SizeInBits, value AlignInBits, - value AddressSpace, value Name) { + value AddressSpace, + value MemorySpace, value Name) { LLVMMetadataRef Metadata = LLVMDIBuilderCreatePointerType( DIBuilder_val(Builder), Metadata_val(PointeeTy), (uint64_t)Int_val(SizeInBits), Int_val(AlignInBits), - Int_val(AddressSpace), String_val(Name), caml_string_length(Name)); + Int_val(AddressSpace), map_DWARFMemorySpace(Int_val(MemorySpace)), + String_val(Name), caml_string_length(Name)); return to_val(Metadata); } @@ -507,7 +516,8 @@ value llvm_dibuild_create_pointer_type_bytecode(value *argv, int argn) { argv[2], // SizeInBits argv[3], // AlignInBits argv[4], // AddressSpace - argv[5] // Name + argv[5], // MemorySpace + argv[6] // Name ); } @@ -629,9 +639,12 @@ value llvm_dibuild_create_qualified_type(value Builder, value Tag, value Type) { return to_val(Metadata); } -value llvm_dibuild_create_reference_type(value Builder, value Tag, value Type) { +value llvm_dibuild_create_reference_type(value Builder, value Tag, value Type, + value AddressSpace, + value MemorySpace) { LLVMMetadataRef Metadata = LLVMDIBuilderCreateReferenceType( - DIBuilder_val(Builder), Int_val(Tag), Metadata_val(Type)); + DIBuilder_val(Builder), Int_val(Tag), Metadata_val(Type), + Int_val(AddressSpace), map_DWARFMemorySpace(Int_val(MemorySpace))); return to_val(Metadata); } @@ -874,13 +887,14 @@ value llvm_dibuild_create_constant_value_expression(value Builder, value llvm_dibuild_create_global_variable_expression_native( value Builder, value Scope, value Name, value Linkage, value File, value Line, value Ty, value LocalToUnit, value Expr, value Decl, - value AlignInBits) { + value MemorySpace, value AlignInBits) { LLVMMetadataRef Metadata = LLVMDIBuilderCreateGlobalVariableExpression( DIBuilder_val(Builder), Metadata_val(Scope), String_val(Name), caml_string_length(Name), String_val(Linkage), caml_string_length(Linkage), Metadata_val(File), Int_val(Line), Metadata_val(Ty), Bool_val(LocalToUnit), Metadata_val(Expr), - Metadata_val(Decl), Int_val(AlignInBits)); + Metadata_val(Decl), map_DWARFMemorySpace(Int_val(MemorySpace)), + Int_val(AlignInBits)); return to_val(Metadata); } @@ -888,17 +902,18 @@ value llvm_dibuild_create_global_variable_expression_bytecode(value *argv, int arg) { return llvm_dibuild_create_global_variable_expression_native( - argv[0], // Builder - argv[1], // Scope - argv[2], // Name - argv[3], // Linkage - argv[4], // File - argv[5], // Line - argv[6], // Ty - argv[7], // LocalToUnit - argv[8], // Expr - argv[9], // Decl - argv[10] // AlignInBits + argv[0], // Builder + argv[1], // Scope + argv[2], // Name + argv[3], // Linkage + argv[4], // File + argv[5], // Line + argv[6], // Ty + argv[7], // LocalToUnit + argv[8], // Expr + argv[9], // Decl + argv[10], // MemorySpace + argv[11] // AlignInBits ); } @@ -919,16 +934,14 @@ value llvm_get_metadata_kind(value Metadata) { return Val_int(LLVMGetMetadataKind(Metadata_val(Metadata))); } -value llvm_dibuild_create_auto_variable_native(value Builder, value Scope, - value Name, value File, - value Line, value Ty, - value AlwaysPreserve, - value Flags, value AlignInBits) { +value llvm_dibuild_create_auto_variable_native( + value Builder, value Scope, value Name, value File, value Line, value Ty, + value AlwaysPreserve, value Flags, value MemorySpace, value AlignInBits) { return to_val(LLVMDIBuilderCreateAutoVariable( DIBuilder_val(Builder), Metadata_val(Scope), String_val(Name), caml_string_length(Name), Metadata_val(File), Int_val(Line), Metadata_val(Ty), Bool_val(AlwaysPreserve), DIFlags_val(Flags), - Int_val(AlignInBits))); + map_DWARFMemorySpace(Int_val(MemorySpace)), Int_val(AlignInBits))); } value llvm_dibuild_create_auto_variable_bytecode(value *argv, int arg) { @@ -941,7 +954,8 @@ value llvm_dibuild_create_auto_variable_bytecode(value *argv, int arg) { argv[5], // Ty argv[6], // AlwaysPreserve argv[7], // Flags - argv[8] // AlignInBits + argv[8], // MemorySpace + argv[9] // AlignInBits ); } diff --git a/llvm/bindings/ocaml/debuginfo/llvm_debuginfo.ml b/llvm/bindings/ocaml/debuginfo/llvm_debuginfo.ml index 3e9a82962d99a..5bd882d80648c 100644 --- a/llvm/bindings/ocaml/debuginfo/llvm_debuginfo.ml +++ b/llvm/bindings/ocaml/debuginfo/llvm_debuginfo.ml @@ -96,6 +96,15 @@ module DIFlag = struct | PtrToMemberRep end +module DWARFMemorySpace = struct + type t = + | DW_MSPACE_LLVM_none + | DW_MSPACE_LLVM_global + | DW_MSPACE_LLVM_constant + | DW_MSPACE_LLVM_group + | DW_MSPACE_LLVM_private +end + type lldiflags external diflags_get : DIFlag.t -> lldiflags = "llvm_diflags_get" @@ -345,6 +354,7 @@ external dibuild_create_pointer_type : size_in_bits:int -> align_in_bits:int -> address_space:int -> + memory_space:DWARFMemorySpace.t -> name:string -> Llvm.llmetadata = "llvm_dibuild_create_pointer_type_bytecode" "llvm_dibuild_create_pointer_type_native" @@ -412,7 +422,12 @@ external dibuild_create_qualified_type : = "llvm_dibuild_create_qualified_type" external dibuild_create_reference_type : - lldibuilder -> tag:int -> Llvm.llmetadata -> Llvm.llmetadata + lldibuilder -> + tag:int -> + ty:Llvm.llmetadata -> + address_space:int -> + memory_space:DWARFMemorySpace.t -> + Llvm.llmetadata = "llvm_dibuild_create_reference_type" external dibuild_create_null_ptr_type : lldibuilder -> Llvm.llmetadata @@ -555,6 +570,7 @@ external dibuild_create_global_variable_expression : is_local_to_unit:bool -> expr:Llvm.llmetadata -> decl:Llvm.llmetadata -> + memory_space:DWARFMemorySpace.t -> align_in_bits:int -> Llvm.llmetadata = "llvm_dibuild_create_global_variable_expression_bytecode" "llvm_dibuild_create_global_variable_expression_native" @@ -581,6 +597,7 @@ external dibuild_create_auto_variable : ty:Llvm.llmetadata -> always_preserve:bool -> lldiflags -> + memory_space:DWARFMemorySpace.t -> align_in_bits:int -> Llvm.llmetadata = "llvm_dibuild_create_auto_variable_bytecode" "llvm_dibuild_create_auto_variable_native" diff --git a/llvm/bindings/ocaml/debuginfo/llvm_debuginfo.mli b/llvm/bindings/ocaml/debuginfo/llvm_debuginfo.mli index d759b53642755..125c8a63cf809 100644 --- a/llvm/bindings/ocaml/debuginfo/llvm_debuginfo.mli +++ b/llvm/bindings/ocaml/debuginfo/llvm_debuginfo.mli @@ -96,6 +96,15 @@ module DIFlag : sig | PtrToMemberRep end +module DWARFMemorySpace : sig + type t = + | DW_MSPACE_LLVM_none + | DW_MSPACE_LLVM_global + | DW_MSPACE_LLVM_constant + | DW_MSPACE_LLVM_group + | DW_MSPACE_LLVM_private +end + type lldiflags (** An opaque type to represent OR of multiple DIFlag.t. *) @@ -310,6 +319,7 @@ val dibuild_create_global_variable_expression : is_local_to_unit:bool -> expr:Llvm.llmetadata -> decl:Llvm.llmetadata -> + memory_space:DWARFMemorySpace.t -> align_in_bits:int -> Llvm.llmetadata (** [dibuild_create_global_variable_expression] Create a new descriptor for @@ -413,6 +423,7 @@ val dibuild_create_pointer_type : size_in_bits:int -> align_in_bits:int -> address_space:int -> + memory_space:DWARFMemorySpace.t -> name:string -> Llvm.llmetadata (** [dibuild_create_pointer_type] Create debugging information entry for a @@ -490,7 +501,12 @@ val dibuild_create_qualified_type : [tag] identifyies the type and [ty] is the base type. *) val dibuild_create_reference_type : - lldibuilder -> tag:int -> Llvm.llmetadata -> Llvm.llmetadata + lldibuilder -> + tag:int -> + ty:Llvm.llmetadata -> + address_space:int -> + memory_space:DWARFMemorySpace.t -> + Llvm.llmetadata (** [dibuild_create_reference_type dib tag ty] Create debugging information entry for a reference type. [dib] is the dibuilder value, [tag] identifyies the type and [ty] is the base type. *) @@ -640,6 +656,7 @@ val dibuild_create_auto_variable : ty:Llvm.llmetadata -> always_preserve:bool -> lldiflags -> + memory_space:DWARFMemorySpace.t -> align_in_bits:int -> Llvm.llmetadata (** [dibuild_create_auto_variable] Create a new descriptor for a diff --git a/llvm/cmake/modules/CheckCompilerVersion.cmake b/llvm/cmake/modules/CheckCompilerVersion.cmake index c550df7b08c84..31dd555050d0a 100644 --- a/llvm/cmake/modules/CheckCompilerVersion.cmake +++ b/llvm/cmake/modules/CheckCompilerVersion.cmake @@ -4,8 +4,8 @@ include(CheckCXXSourceCompiles) -set(GCC_MIN 7.4) -set(GCC_SOFT_ERROR 7.4) +set(GCC_MIN 7.3) +set(GCC_SOFT_ERROR 7.3) set(CLANG_MIN 5.0) set(CLANG_SOFT_ERROR 5.0) set(APPLECLANG_MIN 10.0) diff --git a/llvm/cmake/modules/HandleLLVMOptions.cmake b/llvm/cmake/modules/HandleLLVMOptions.cmake index 22ecf4dcee368..6a4610397967a 100644 --- a/llvm/cmake/modules/HandleLLVMOptions.cmake +++ b/llvm/cmake/modules/HandleLLVMOptions.cmake @@ -611,6 +611,10 @@ if( MSVC ) append("/WX" CMAKE_C_FLAGS CMAKE_CXX_FLAGS) endif (LLVM_ENABLE_WERROR) + # FIXME(kzhuravl): Need to check if it affects windows ci builds. If yes, + # we might need to upstream this, possibly under a cmake option. + append("/Zm20" CMAKE_C_FLAGS CMAKE_CXX_FLAGS) + append("/Zc:inline" CMAKE_C_FLAGS CMAKE_CXX_FLAGS) if (CMAKE_CXX_COMPILER_ID STREQUAL "MSVC") diff --git a/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst b/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst index f472b862d1ee3..f5b052264716c 100644 --- a/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst +++ b/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst @@ -798,7 +798,6 @@ The following table provides the additional attributes. Attribute Usage ============================ ==================================== ``DW_AT_LLVM_active_lane`` SIMT active lanes (see :ref:`amdgpu-dwarf-low-level-information`) - ``DW_AT_LLVM_augmentation`` Compilation unit augmentation string (see :ref:`amdgpu-dwarf-full-and-partial-compilation-unit-entries`) ``DW_AT_LLVM_lane_pc`` SIMT lane program location (see :ref:`amdgpu-dwarf-low-level-information`) ``DW_AT_LLVM_lanes`` SIMT lane count (see :ref:`amdgpu-dwarf-low-level-information`) ``DW_AT_LLVM_iterations`` Concurrent iteration count (see :ref:`amdgpu-dwarf-low-level-information`) @@ -3303,38 +3302,6 @@ are defined in :ref:`amdgpu-dwarf-language-names-table`. The HIP language [:ref:`HIP `] can be supported by extending the C++ language. -.. note:: - - The following new attribute is added. - -1. A ``DW_TAG_compile_unit`` debugger information entry for a compilation unit - may have a ``DW_AT_LLVM_augmentation`` attribute, whose value is an - augmentation string. - - *The augmentation string allows producers to indicate that there is - additional vendor or target specific information in the debugging - information entries. For example, this might be information about the - version of vendor specific extensions that are being used.* - - If not present, or if the string is empty, then the compilation unit has no - augmentation string. - - The format for the augmentation string is: - - | ``[``\ *vendor*\ ``:v``\ *X*\ ``.``\ *Y*\ [\ ``:``\ *options*\ ]\ ``]``\ * - - Where *vendor* is the producer, ``vX.Y`` specifies the major X and minor Y - version number of the extensions used, and *options* is an optional string - providing additional information about the extensions. The version number - must conform to semantic versioning [:ref:`SEMVER `]. - The *options* string must not contain the "\ ``]``\ " character. - - For example: - - :: - - [abc:v0.0][def:v1.2:feature-a=on,feature-b=3] - A.3.3 Subroutine and Entry Point Entries ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -3740,9 +3707,9 @@ constant may have the following attributes: 3. ``DW_AT_LLVM_memory_space`` - A ``DW_AT_memory_space`` attribute with a constant value representing a source + A ``DW_AT_LLVM_memory_space`` attribute with a constant value representing a source language specific DWARF memory space (see 2.14 "Memory Spaces"). If omitted, - defaults to ``DW_MSPACE_none``. + defaults to ``DW_MSPACE_LLVM_none``. A.4.2 Common Block Entries @@ -4018,45 +3985,6 @@ following rules: or ``DW_OP_form_tls_address`` operation are included; otherwise, they are excluded. -A.6.1.1.4 Data Representation of the Name Index -############################################### - -.. _amdgpu-dwarf-name-index-section-header: - - -A.6.1.1.4.1 Section Header -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. note:: - - The following provides an addition to DWARF Version 5 section 6.1.1.4.1 item - 14 ``augmentation_string``. - -A null-terminated UTF-8 vendor specific augmentation string, which provides -additional information about the contents of this index. If provided, the -recommended format for augmentation string is: - - | ``[``\ *vendor*\ ``:v``\ *X*\ ``.``\ *Y*\ [\ ``:``\ *options*\ ]\ ``]``\ * - -Where *vendor* is the producer, ``vX.Y`` specifies the major X and minor Y -version number of the extensions used in the DWARF of the compilation unit, and -*options* is an optional string providing additional information about the -extensions. The version number must conform to semantic versioning [:ref:`SEMVER -`]. The *options* string must not contain the "\ ``]``\ " -character. - -For example: - - :: - - [abc:v0.0][def:v1.2:feature-a=on,feature-b=3] - -.. note:: - - This is different to the definition in DWARF Version 5 but is consistent with - the other augmentation strings and allows multiple vendor extensions to be - supported. - .. _amdgpu-dwarf-line-number-information: A.6.2 Line Number Information @@ -4292,68 +4220,31 @@ Frame Description Entries (FDE). There is at least one CIE in every non-empty Would this be increased to 5 to reflect the changes in these extensions? -4. ``augmentation`` (sequence of UTF-8 characters) - - A null-terminated UTF-8 string that identifies the augmentation to this CIE - or to the FDEs that use it. If a reader encounters an augmentation string - that is unexpected, then only the following fields can be read: - - * CIE: length, CIE_id, version, augmentation - * FDE: length, CIE_pointer, initial_location, address_range - - If there is no augmentation, this value is a zero byte. - - *The augmentation string allows users to indicate that there is additional - vendor and target architecture specific information in the CIE or FDE which - is needed to virtually unwind a stack frame. For example, this might be - information about dynamically allocated data which needs to be freed on exit - from the routine.* - - *Because the* ``.debug_frame`` *section is useful independently of any* - ``.debug_info`` *section, the augmentation string always uses UTF-8 - encoding.* - - The recommended format for the augmentation string is: - - | ``[``\ *vendor*\ ``:v``\ *X*\ ``.``\ *Y*\ [\ ``:``\ *options*\ ]\ ``]``\ * - - Where *vendor* is the producer, ``vX.Y`` specifies the major X and minor Y - version number of the extensions used, and *options* is an optional string - providing additional information about the extensions. The version number - must conform to semantic versioning [:ref:`SEMVER `]. - The *options* string must not contain the "\ ``]``\ " character. - - For example: - - :: - - [abc:v0.0][def:v1.2:feature-a=on,feature-b=3] - -5. ``address_size`` (ubyte) +4. ``address_size`` (ubyte) The size of a target address in this CIE and any FDEs that use it, in bytes. If a compilation unit exists for this frame, its address size must match the address size here. -6. ``segment_selector_size`` (ubyte) +5. ``segment_selector_size`` (ubyte) The size of a segment selector in this CIE and any FDEs that use it, in bytes. -7. ``code_alignment_factor`` (unsigned LEB128) +6. ``code_alignment_factor`` (unsigned LEB128) A constant that is factored out of all advance location instructions (see :ref:`amdgpu-dwarf-row-creation-instructions`). The resulting value is ``(operand * code_alignment_factor)``. -8. ``data_alignment_factor`` (signed LEB128) +7. ``data_alignment_factor`` (signed LEB128) A constant that is factored out of certain offset instructions (see :ref:`amdgpu-dwarf-cfa-definition-instructions` and :ref:`amdgpu-dwarf-register-rule-instructions`). The resulting value is ``(operand * data_alignment_factor)``. -9. ``return_address_register`` (unsigned LEB128) +8. ``return_address_register`` (unsigned LEB128) An unsigned LEB128 constant that indicates which column in the rule table represents the return address of the subprogram. Note that this column might @@ -4363,7 +4254,7 @@ Frame Description Entries (FDE). There is at least one CIE in every non-empty location of the caller frame. The program location of the top frame is the target architecture program counter value of the current thread. -10. ``initial_instructions`` (array of ubyte) +9. ``initial_instructions`` (array of ubyte) A sequence of rules that are interpreted to create the initial setting of each column in the table. @@ -4373,7 +4264,7 @@ Frame Description Entries (FDE). There is at least one CIE in every non-empty compilation system authoring body may specify an alternate default value for any or all columns. -11. ``padding`` (array of ubyte) +10. ``padding`` (array of ubyte) Enough ``DW_CFA_nop`` instructions to make the size of this entry match the length value above. @@ -4775,14 +4666,13 @@ entry attributes. ================================== ====== =================================== Attribute Name Value Classes ================================== ====== =================================== - ``DW_AT_LLVM_active_lane`` 0x3e08 exprloc, loclist - ``DW_AT_LLVM_augmentation`` 0x3e09 string ``DW_AT_LLVM_lanes`` 0x3e0a constant ``DW_AT_LLVM_lane_pc`` 0x3e0b exprloc, loclist ``DW_AT_LLVM_vector_size`` 0x3e0c constant ``DW_AT_LLVM_iterations`` 0x3e0a constant, exprloc, loclist ``DW_AT_LLVM_address_space`` TBA constant ``DW_AT_LLVM_memory_space`` TBA constant + ``DW_AT_LLVM_active_lane`` TBA exprloc, loclist ================================== ====== =================================== .. _amdgpu-dwarf-classes-and-forms: @@ -5040,7 +4930,6 @@ debugger information entries. ``DW_TAG_variable`` * ``DW_AT_LLVM_memory_space`` ``DW_TAG_formal_parameter`` * ``DW_AT_LLVM_memory_space`` ``DW_TAG_constant`` * ``DW_AT_LLVM_memory_space`` - ``DW_TAG_compile_unit`` * ``DW_AT_LLVM_augmentation`` ``DW_TAG_entry_point`` * ``DW_AT_LLVM_active_lane`` * ``DW_AT_LLVM_lane_pc`` * ``DW_AT_LLVM_lanes`` diff --git a/llvm/docs/AMDGPULLVMExtensionsForHeterogeneousDebugging.rst b/llvm/docs/AMDGPULLVMExtensionsForHeterogeneousDebugging.rst new file mode 100644 index 0000000000000..33c9f5c8c681b --- /dev/null +++ b/llvm/docs/AMDGPULLVMExtensionsForHeterogeneousDebugging.rst @@ -0,0 +1,2805 @@ +=================================================== +AMDGPU LLVM Extensions for Heterogeneous Debugging +=================================================== + +.. contents:: + :local: + +.. warning:: + + This section describes **provisional support** for AMDGPU LLVM debug + information that is not currently fully implemented and is subject to change. + +Introduction +============ + +As described in the :doc:`AMDGPUDwarfExtensionsForHeterogeneousDebugging` (the +“DWARF extensions”), AMD has been working to support debugging of heterogeneous +programs. This document describes changes to the LLVM representation of debug +information (the “LLVM extensions”) required to support the DWARF extensions. +These LLVM extensions continue to support previous versions of the DWARF +standard, including DWARF 5 without extensions, as well as other debug formats +which LLVM currently supports, such as CodeView. + +The LLVM extensions do not constitute a direct implementation of all concepts +from the DWARF extensions, although wherever reasonable the fundamental aspects +were kept identical. The concepts defined in the DWARF extensions which are used +directly in the LLVM extensions with their semantics unchanged are enumerated in +the :ref:`amdgpu-llvm-debug-external-definitions` section below. + +A significant departure from the DWARF extensions is in the consolidation of +expression evaluation stack entries. In the DWARF extensions, each entry on the +expression evaluation stack contains either a typed value or an untyped location +description. In the LLVM extensions, each entry on the expression evaluation +stack instead contains a pair of a location description and a type. + +Additionally, the concept of a “generic type”, used as a default when a type is +needed but not stated explicitly, is eliminated. Together, these changes imply +that the concrete set of operations available differ between the DWARF and LLVM +extensions. + +These changes were made to remove redundant representations of semantically +equivalent expressions, which can simplify the compiler’s work in updating debug +information expressions to reflect code transformations. The LLVM extensions’ +changes are possible as LLVM has no requirement for backwards compatibility, nor +any requirement that the intermediate representation of debug information +conform to any particular external specification. Consequently, the LLVM +extensions are able to increase the accuracy of existing debug information, +while also extending the debug information to cover cases which were previously +not described at all. + +High-Level Goals +================ + +There are several specific cases where the LLVM extensions’ approach can allow +for more accurate or more complete debug information than would be feasible with +only incremental changes to the existing approach. + +- Support describing the location of induction variables. LLVM currently has a + new implementation of partial support for an expression which depends on + multiple LLVM values, although it is currently limited exclusively to a + subset of cases for induction variables. This support is also inherently + limited as it can only refer directly to LLVM values, not to source variables + symbolically. This means it is not possible to describe an induction variable + which, for example, depends on a variable whose location is not static over + the whole lifetime of the induction variable. +- Support describing the location of arbitrary expressions over scalar-replaced + aggregate values, even in the face of other dependent expressions. LLVM + currently drops debug information when any expression would depend on a + composite value. +- Support describing all locations of values which are live in multiple machine + locations at the same instruction. LLVM currently picks only one such + location to describe. This means values which are resident in multiple places + need to be conservatively marked read-only, even when they could be + read-write if all of their locations were reported accurately. +- Accurately support describing the range over which a given location is + active. LLVM currently pessimizes debug information as there is no rigorous + means to limit the range of a described location. +- Support describing the factoring of expressions. This allows features such as + DWARF procedures to be used to reduce the size of debug information. + Factoring can also be more convenient for the compiler to describe lexically + nested information such as program location for inactive lanes in divergent + control flow. + +Motivation +========== + +The original motivation for the LLVM extensions was to make the minimum required +changes to the existing LLVM representation of debug information needed to +support the :doc:`AMDGPUDwarfExtensionsForHeterogeneousDebugging`. This involved +an evaluation of the existing debug information for machine locations in LLVM, +which uncovered some hard-to-fix bugs rooted in the incidental complexity and +inconsistency of LLVM’s debug intrinsics and expressions. + +Attempting to address these bugs in the existing framework proved more difficult +than expected. It became apparent that the shortcomings of the existing solution +were a direct consequence of the complexity, ambiguity, and lack of +composability encountered in DWARF. + +With this in mind, we revisited the DWARF extensions to see if they could inform +a more tractable design for LLVM. We had already worked to address the +complexity and ambiguity of DWARF by defining a formalization for its expression +language and improved the composability by unifying values and location +descriptions on the evaluation stack. Together, these changes also increased the +expressiveness of DWARF. Using similar ideas in LLVM allowed us to support +additional real world cases and describe existing cases with greater accuracy. + +This led us to start from the DWARF extensions and design a new set of debug +information representations. This was very heavily influenced by prior art in +LLVM, existing RFCs, mailing list discussions, review comments, and bug reports, +without which we would not have been able to make this proposal. Some of the +influences include: + +- The use of intrinsics to capture local LLVM values keeps the proposal close + to the existing implementation, and limits the incidental work needed to + support it for the reasons outlined in `[LLVMdev] [RFC] Separating Metadata + from the Value hierarchy + `__. +- Support for debug locations which depend on multiple LLVM values is required + by several optimizations, including expressing induction variables, which is + the motivation for `D81852 [DebugInfo] Update MachineInstr interface to + better support variadic DBG_VALUE instructions + `__. +- Our solution also generalizes the notion of “fragments” to support composing + with arbitrary expressions. For example, fragmentation can be represented + even in the presence of arithmetic operators, as occurs in `D70601 Disallow + DIExpressions with shift operators from being fragmented + `__. +- The desire to support multiple concurrent locations for the same variable is + described in detail in `[llvm-dev] Proposal for multi location debug info + support in LLVM IR + `__ + (continued at `[llvm-dev] Proposal for multi location debug info support in + LLVM IR + `__) and + `Multi Location Debug Info support for LLVM + `__. Support for + overlapping location list entries was added in DWARF 5. +- Bugs, like `Bug 40628 - [DebugInfo@O2] Salvaged memory loads can observe + subsequent memory writes `__, + which was partially worked around in `D57962 [DebugInfo] PR40628: Don’t + salvage load operations `__, often result + from passes being unable to accurately represent the relationship between + source variables. Our approach supports encoding that information in debug + information in a mechanical way, with straightforward semantics. +- Use of ``distinct`` for our new metadata nodes is motivated by use cases + similar to those in `[LLVMdev] [RFC] Separating Metadata from the Value + hierarchy (David Blaikie) + `__ + where the content of a node is not sufficient context to unique it. + +The least error prone place to make changes to debug information is at the point +where the underlying code is being transformed, hence the LLVM extensions’ +representation is biased for this case. + +The expression evaluation stack contains uniform pairs of location description +and type, such that all operations have well-defined semantics and no +side-effects on the evaluation of the surrounding expression. These same +semantics apply equally throughout the compiler. This allows for referentially +transparent updates, which can be reasoned about in the context of a single +operation and its inputs and outputs, rather than the space of all possible +surrounding operations and dependent expressions. + +By eliminating any implicit expression inputs or operations and constraining the +state space of expressions using well-formedness rules, it is unambiguous +whether a given transformation is valid and semantics-preserving, without ever +having to consider anything outside of the expression itself. + +Designing around a separation of concerns regarding expression modification and +simplification allows each update to the debug information to introduce +redundant or sub-optimal expressions. To address this, an independent +“optimizer” can simplify and canonicalize expressions. As the expression +semantics are well-defined, an“optimizer” can be run without specific knowledge +of the changes made by any one pass or combination of passes. + +Incorporating a means to express “factoring”, or the definition of one +expression in terms of one or more other expressions, makes “shallow”updates +possible, bounding the work needed for any given update. This factoring is +usually trivial at the time the expression is created, but expensive to infer +later. Factored expressions can result in more compact debug information by +leveraging dynamic calling of DWARF procedures in DWARF 5, and we expect to be +able to use factoring for other purposes, such as debug information for +divergent control flow (see :ref:`amdgpu-dwarf-dw-at-llvm-lane-pc`). It is +possible to statically “flatten” this factored representation later, if required +by the debug information format being emitted, or if the emitter determines it +would be more profitable to do so. + +Leveraging the DWARF extensions as a foundation, the concept of a location +description is used as the fundamental means of recording debug information. To +support this, each LLVM entity which can be referenced by an expression has a +well-defined location description, and is referred to by expressions in an +explicit, referentially transparent manner. This makes updates to reflect +changes in the underlying LLVM representation mechanical, robust, and simple. +Due to factoring, these updates are also more localized, as updates to an +expression are transparently reflected in all dependent expressions without +having to traverse them, or even be aware of their existence. + +Without this factoring, any changes to an LLVM entity which are effectively used +as an input to one or more expressions would need to be“macro-expanded” at the +time they are made, in each place they are referenced. This in turn inhibits the +valid transformations the context-insensitive “optimizer” can safely perform, as +perturbing the macro-expanded expression for an LLVM entity makes it impossible +to reflect future changes to that entity in the expression. Even if this is +considered acceptable, once expressions begin to effectively depend on other +expressions (for example, in the description of induction variables, where one +program object depends on multiple other program objects) there is no longer a +bound on the recursive depth of expressions which need to be visited for any +given update, making even simple updates expensive in terms of compiler +resources. Furthermore, this approach requires either a combinatorial explosion +of expressions to describe cases when the live ranges of multiple program +objects are not equal, or the dropping of debug information for all but one such +object. None of these tradeoffs were considered acceptable. + +Changes from LLVM Language Reference Manual +=========================================== + +This section describes a provisional set of changes to the :doc:`LangRef` to +support the :doc:`AMDGPUDwarfExtensionsForHeterogeneousDebugging`. It is not +currently fully implemented and is subject to change. + +.. _amdgpu-llvm-debug-external-definitions: + +External Definitions +-------------------- + +Some required concepts are defined outside of this document. We reproduce some +parts of those definitions, along with some expansion on their relationship to +this proposal and any extensions. + +Well-Formed +~~~~~~~~~~~ + +The definition of “well-formed” is the one from the :ref:`LLVM Language +Reference Manual `. + +Type +~~~~ + +The definition of “type” is the one from the :ref:`LLVM Language Reference +Manual `. + +Value +~~~~~ + +The definition of “value” is the one from the :doc:`LangRef`. + +Location Description +-------------------- + +The definitions of “location description”, “single location description”, and +“location storage” are the ones from the section titled +:ref:`amdgpu-dwarf-location-description` in the DWARF Extensions For +Heterogeneous Debugging. + +A location description can consist of one or more single location descriptions. +A single location description specifies a location storage and bit offset. A +location storage is a linear stream of bits with a fixed size. + +The storage encompasses memory, registers, and literal/implicit values. + +Zero or more single location descriptions may be active for a location +description at the same instruction. + +LLVM Debug Information Expressions +---------------------------------- + +*[Note: LLVM expressions derive much of their semantics from the DWARF +expressions described in the* :ref:`amdgpu-dwarf-expressions`\ *.]* + +LLVM debug information expressions (“LLVM expressions”) specify a typed +location. *[Note: Unlike DWARF expressions, they cannot directly describe how to +compute a value. Instead, they are able to describe how to define an implicit +location description for a computed value.]* + +If the evaluation of an LLVM expression does not encounter an error, then it +results in exactly one pair of location description and type. + +If the evaluation of an LLVM expression encounters an error, the result is an +evaluation error. + +If an LLVM expression is not well-formed, then the result is undefined. + +The following sections detail the rules for when a LLVM expression is not +well-formed or results in an evaluation error. + +LLVM Expression Evaluation Context +---------------------------------- + +An LLVM expression is evaluated in a context that includes the same context +elements as described in :ref:`amdgpu-dwarf-expression-evaluation-context` with +the following exceptions. The *current result kind* is not applicable as all +LLVM expressions are location descriptions. The *current object* and *initial +stack* are not applicable as LLVM expressions have no implicit inputs. + +Location Descriptions Of LLVM Entities +-------------------------------------- + +The notion of location storage is extended to include the abstract LLVM entities +of *values*, *global variables*, *stack slots*, *virtual registers*, and +*physical registers*. In each case the location storage conceptually holds the +value of the corresponding entity. + +For global variables, the location storage corresponds to the SSA value for the +address of the global variable as is the case when referenced in LLVM IR. + +In addition, an implicit address location storage kind is defined. The size of +the storage matches the size of the type for the address. The value in the +storage is only meaningful when used in its entirety by a ``DIOpDeref`` +operation, which yields a location description for the entity that the address +references. *[Note: This is a generalization to the implicit pointer location +description of DWARF 5.]* + +Location descriptions can be associated with instances of any of these location +storage kinds. + +High Level Structure +-------------------- + +Global Variable +~~~~~~~~~~~~~~~ + +The definition of “global variable” is the one from the :ref:`globalvars` with +the following addition. + +.. TODO:: + + Should this explicitly state that only zero or one such ``dbg.def`` + attachment is well formed? + +The optional ``dbg.def`` metadata attachment can be used to specify a +``DIFragment`` termed a global variable fragment. The location description of a +global variable fragment is a memory location description for a pointer to the +global variable that references it. + +If a global variable fragment is referenced by more than one global variable +``dbg.def`` field, then it is not well-formed. If a global variable fragment is +referenced by the ``object`` field of a ``DILifetime`` then it is not +well-formed. + +*[Note: Global variables in LLVM exist for the duration of the program. The +global variable fragment can be referenced by the* ``argObjects`` *field of a +computed lifetime segment to specify the location for a* ``DIGlobalVariable`` +*for that entire program duration. However, the global variable may exist in a +different location for a given part of the subprogram. This can be expressed +using bounded lifetime segments for the* ``DIGlobalVariable``\ *. If the +computed lifetime segment is specified, it only applies for the program +locations not covered by a bounded lifetime segment. If the computed lifetime +segment is not specified, and no bounded lifetime segment covers the program +location, then the* ``DIGlobalVariable`` *location is the undefined location +description for that program location. The bounded lifetime segments of a* +``DIGlobalVariable`` *can also reference the global variable fragment. This +allows the same LLVM global variable to be used for different* +``DIGlobalVariable``\ *s over different program locations.]* + +.. TODO:: + + Should there be a separate ``DIGlobalFragment`` for this since it is not + allowed to have any bounded lifetime segments referencing it? Of should a + ``DIFragment`` have a ``kind`` field that indicates if it is a ``computed``, + ``bounded``, or ``global`` fragment? + +.. + +.. TODO:: + + Should the global variable fragment be the location description of the LLVM + global variable rather than an implicit location description that is a + pointer to it? That would void needing the ``DIOpDeref`` when referencing the + global variable fragment. Seems can use ``DIOpAddrOf`` if need the address, + and all other uses need the location description of the actual LLVM global + variable. But DWARF has limitations in supporting ``DIAddrOf`` due to + limitations in creating implicit pointer location descriptions. + +Metadata +-------- + +An abstract metadata node exists only to abstractly specify common aspects of +derived node types, and to refer to those derived node types generally. Abstract +node types cannot be created directly. + +.. _amdgpu-llvm-debug-diobject: + +``DIObject`` +~~~~~~~~~~~~ + +A ``DIObject`` is an abstract metadata node that represents the identity of a +program object used to hold data. There are several kinds of program objects. + +``DIVariable`` +^^^^^^^^^^^^^^ + +A ``DIVariable`` is a ``DIObject``, which represents the identity of a source +language program variable or non-source language program variable. + +A non-source language program variable includes ``DIFlagArtificial`` in the +``flags`` field. + +*[Note: A non-source language program variable may be introduced by the +compiler. These may be used in expressions needed for describing debugging +information required by the debugger.]* + +*[Example: An implicit variable needed for calculating the size of a dynamically +sized array.]* + +``DIGlobalVariable`` +'''''''''''''''''''' + +A ``DIGlobalVariable`` is a ``DIVariable``, which represents the identity of a +global variable. See :ref:`DIGlobalVariable`. + +``DILocalVariable`` +''''''''''''''''''' + +A ``DILocalVariable`` is a ``DIVariable``, which represents the identity of a +local variable. See :ref:`DILocalVariable`. + +``DIFragment`` +^^^^^^^^^^^^^^ + +.. code:: llvm + + distinct !DIFragment() + +A ``DIFragment`` is a ``DIObject``, which represents the identity of a location +description that can be used as the piece of another location description. + +*[Note: Unlike a* ``DIVariable``\ *, a* ``DIFragment`` *is not named and so is +not directly exposed to the user of a debugger.]* + +*[Note: A* ``DIFragment`` *may be a piece of a* ``DIVariable`` *directly, or +indirectly by virtue of being a piece of some other* ``DIFragment``\ *.]* + +*[Note: A* ``DIFragment`` *may be introduced to factor the definition of part of +a location description shared by other location descriptions for convenience or +to permit more compact debug information.]* + +*[Note: A* ``DIFragment`` *may be introduced to allow the compiler to specify +multiple lifetime segments for the single location description referenced for a +default or type lifetime segment.]* + +*[Note: In DWARF a* ``DIFragment`` *can be represented using a* +``DW_TAG_dwarf_procedure`` *DIE.]* + +*[Example: The fragments into which SRoA splits a source language variable. The +location description of the source language variable would then use an +expression that combines the fragments appropriately.]* + +*[Example: Divergent control flow can be described by factoring information +about how to determine active lanes by lexical scope, which results in more +compact debug information.]* + +*[Note:* ``DIFragment`` *replaces using* ``DW_OP_LLVM_fragment`` *in the current +LLVM IR* ``DIExpression`` *operations. This simplifies updating expressions +which now purely describe the location description.]* + +``DICode`` +~~~~~~~~~~ + +A ``DICode`` is an abstract metadata node that represents the identity of a +program code location. There are several kinds of program code locations. + +``DILabel`` +^^^^^^^^^^^ + +A ``DILabel`` is a ``DICode``, which represents the identity of a source +language label. See :ref:`DILabel`. + +``DIExprCode`` +^^^^^^^^^^^^^^ + +.. code:: llvm + + distinct !DIExprCode() + +A ``DIExprCode`` is a ``DICode``, which represents a code location that can be +referenced by the ``argObjects`` field of a ``DILifetime`` as an argument to its +``location`` field’s ``DIExpr``. + +*[Note:* ``DIExprCode`` *does not represent a source language label and so +generates no debug information in itself. It is only used to allow a* ``DIExpr`` +*to refer to a code location address.]* + +.. _amdgpu-llvm-debug-dicompositetype: + +``DICompositeType`` +~~~~~~~~~~~~~~~~~~~ + +A ``DICompositeType`` represents the identity of a composite source program +type. See :ref:`DICompositeType`. + +For ``DICompositeType`` with a ``tag`` field of ``DW_TAG_array_type``, the +optional ``dataLocation``, ``associated``, and ``rank`` fields specify a +``DIFragment`` which is termed a type property fragment. + +If a type property fragment is referenced by the ``argObjects`` field of a +``DILifetime`` or by more than one ``DICompositeType`` field, then the metadata +is not well-formed. + +*[Note: The* ``DILifetime``\ *(s) that reference the type property fragment +specify the location description of the type property. Their* ``location`` +*field expression can use the* :ref:`amdgpu-llvm-debug-diobject` *operation to +get the location description of the instance of the composite type for which the +property is being evaluated. Their* ``argObjects`` *field can be used to specify +other* ``DIObject``\ *s if necessary.]* + +``DILifetime`` +~~~~~~~~~~~~~~ + +.. code:: llvm + + distinct !DILifetime(object: !DIObject, location: !DIExpr [, argObjects: {!DIObject,...} ] ) + +Represents a lifetime segment of a data object. A lifetime segment specifies a +location description expression, references a data object either explicitly or +implicitly, and defines when the lifetime segment applies. The location +description of a data object is defined by the, possibly empty, set of lifetime +segments that reference it. + +.. TODO:: + + Write up the fact that after LiveDebugValues this rule is amended, such that + for a bounded lifetime segment a call to ``llvm.dbg.def``/``llvm.dbg.kill`` + is local to the basic block. That is, rather than respecting control flow + `llvm.dbg.def`` extends either to exactly one ``llvm.dbg.def`` in the same + basic block, or to the end of the basic block. + +There are two kinds of lifetime segment: + +- A *bounded lifetime segment* is one referenced by the first argument of a + call to the ``llvm.dbg.def`` or ``llvm.dbg.kill`` intrinsic. + + A bounded lifetime segment is termed active if the current program location’s + instruction is in the range covered. The call to the ``llvm.dbg.def`` + intrinsic which specifies the ``DILifetime`` is the start of the range, which + extends along all forward control flow paths until either a call to a + ``llvm.dbg.kill`` intrinsic which specifies the same ``DILifetime``, or to + the end of an exit basic block. + + If a bounded lifetime segment is not referenced by exactly one call ``D`` to + the ``llvm.dbg.def`` intrinsic, then the metadata is not well-formed. + + A bounded lifetime segment can be referenced by zero or more + ``llvm.dbg.kill`` intrinsics ``K``. If any member of ``K`` is not reachable + from ``D`` by following control flow, or if every control flow path for every + member of ``K`` passes through another member of ``K``, then the metadata is + not well-formed. + + See :ref:`amdgpu-llvm-debug-llvm-dbg-def` and + :ref:`amdgpu-llvm-debug-llvm-dbg-kill`. +- A *computed lifetime segment* is one not referenced. + +A ``DILifetime`` which does not match exactly one of the above kinds is not +well-formed. + +The required ``object`` field specifies the data object of the lifetime segment. + +The location description of a ``DIObject`` is a function of the current program +location’s instruction and the, possibly empty, set of lifetime segments with an +``object`` field that references the ``DIObject``: + +- If the ``DIObject`` is a global variable fragment, then the location + description is comprised of an implicit location description that has a + pointer value to the global variable that has a ``dbg.def`` metadata + attachment that references it. If a global variable fragment is referenced by + more than one global variable ``dbg.def`` metadata attachment or is + referenced by the ``object`` field of a ``DILifetime``, then the metadata is + not well-formed. +- Otherwise, if the current program location is defined, and any bounded + lifetime segment is active, then the location description is comprised of all + of the location descriptions of all active bounded lifetime segments. +- Otherwise, if there is a computed lifetime segment, then the location + description is comprised of the location description of the computed lifetime + segment. *[Note: A computed lifetime segment corresponds to the DWARF* + ``loclist`` *default location description.]* +- Otherwise, the location description is the undefined location description. + +*[Note: When multiple bounded lifetime segments for the same* +``DIObject`` *are active at a given instruction, it describes the +situation where an object exists simultaneously in more than one place. +For example, a variable may exist in memory and then be promoted to a +register where it is only read before being clobbered and reverting to +using the memory location. While promoted to the register, a debugger +may read from either the register or memory since they both have the +same value but must update both the register and memory if the value of +the variable needs to be changed.]* + +*[Note: A* ``DIObject`` *with no* ``DILifetime``\ *s has an undefined location +description. If the* ``argObjects`` *field of a* ``DILifetime`` *references such +a* ``DIObject`` *then the argument can be removed, and the* ``location`` +*expression updated to use the* ``DIOpConstant`` *with an* ``undef`` *value.]* + +The location description of a ``DICode`` is a single implicit location +description with a value that is the address of the start of the basic block +that contain the ``llvm.dbg.label`` intrinsic that references it. If a +``DICode`` is not referenced by exactly one call to the ``llvm.dbg.label`` +intrinsic, then the metadata is not well-formed. See +:ref:`amdgpu-llvm-debug-llvm-dbg-label`. + +The optional ``argObjects`` field specifies a tuple of zero or more input +``DIObject``\ s or ``DICode``\ s to the expression specified by the ``location`` +field. Omitting the ``argObjects`` field is equivalent to specifying it to be +the empty tuple. + +The required ``location`` field specifies the expression which evaluates to the +location description of the lifetime segment. + +*[Note: The expression may refer to an argument specified by the* ``argObjects`` +*field using the* :ref:`amdgpu-llvm-debug-dioparg` *operation and specifying its +zero-based position in the tuple.* + +*The expression of a bounded lifetime segment may refer to the LLVM entity +specified by the second argument of the call to the* ``llvm.dbg.def`` *intrinsic +that references it using the* :ref:`amdgpu-llvm-debug-diopreferrer` *operation.* + +*The expression of a lifetime segment may refer to the object instance of a type +for which a type property is being specified using the* +:ref:`amdgpu-llvm-debug-dioptypeobject` *operation.* + +*The expression of a lifetime segment may refer to a global variable in LLVM by +using the* :ref:`amdgpu-llvm-debug-dioparg` *operation to refer to a global +variable fragment referenced in the* ``argObjects`` *field.]* + +The reachable lifetime graph is the transitive closure of the graph formed by +the edges: + +- From each ``DIVariable`` (termed root nodes and also termed reachable + ``DIObject``\ s) to the ``DILifetime``\ s that reference them (termed + reachable ``DILifetime``\ s). +- From each ``DICompositeType`` (termed root nodes) to the ``DIFragment``\ s + that are referenced by the optional ``dataLocation``, ``associated``, and + ``rank`` fields (termed reachable ``DIVariable``\ s). +- From each reachable ``DILifetime`` to the ``DIObject``\ s or ``DICode``\ s + referenced by their ``argObjects`` fields (termed reachable ``DIObject``\ s + or reachable ``DICode``\ s respectively). +- From each reachable ``DIObject`` to the ``DILifetime``\ s that reference them + (termed reachable ``DILifetime``\ s). + +If the reachable lifetime graph has any cycles or if any ``DILifetime``, +``DIFragment``, or ``DIExprCode`` are not in the reachable lifetime graph, then +the metadata is not well-formed. + +*[Note: In current debug information the* ``DILifetime`` *information is part of +the debug intrinsics. A new lifetime for an object is defined by using a debug +intrinsic to start a new lifetime. This means an object can have at most one +active lifetime for any given program location. Separating the lifetime +information into a separate metadata node allows there to be multiple debug +intrinsics to begin different lifetime segments over the same program locations. +It also allows a debug intrinsic to indicate the end of the lifetime by +referencing the same lifetime as the intrinsic that started it.]* + +``DICompileUnit`` +~~~~~~~~~~~~~~~~~ + +A ``DICompileUnit`` represents the identity of source program compile unit. See +:ref:`DICompileUnit`. + +All ``DICompileUnit`` compile units are required to be referenced by the +``!llvm.dbg.cu`` named metadata node of the LLVM module. + +All ``DIGlobalVariable`` global variables of the compile unit are required to be +referenced by the ``globals`` field of the ``DICompileUnit``. + +``DISubprogram`` +~~~~~~~~~~~~~~~~ + +A ``DISubprogram`` represents the identity of source language program or +non-source language program function. See :ref:`DISubprogram`. + +A non-source language program function includes ``DIFlagArtificial`` in the +``flags`` field. + +All ``DILocalVariable`` local variables, ``DILabel`` labels, and ``DIExprCode`` +code locations of the function are required to be referenced by the +``retainedNodes`` field of the ``DISubprogram``. + +For all ``DILifetime`` computed lifetime segments that are part of the reachable +lifetime graph: + +1. If only involve ``DILocalVariable``\ s, ``DICompositeType``\ s, and bounded + lifetime segments of the same function, then are required to be referenced by + the ``retainedNodes`` field of the corresponding ``DISubprogram``. +2. Otherwise, are required to be referenced by the ``!llvm.dbg.retainedNodes`` + named metadata node of the LLVM module. + +*[Note: At the time computed lifetime segments are created, it is always well +defined if they are local to a function or are global.* + +*For example, a computed lifetime segment created only to define the location of +a local variable (or a piece of a local variable), would be retained by the +function that defines the local variable. If the function were deleted there is +no need for the computed lifetime segment any more.* + +*Similarly, a computed lifetime segment that contributes a lifetime to the +location description of a global variable (or fragment of a global variable) +using only local variables (or fragments of local variables) or bounded lifetime +segments of the same function, would be retained by the function that defines +the local variables (or fragments of local variables) or owns the bounded +lifetime segments. If the function were deleted there is no need for the +computed lifetime segment any more as the local variable (or fragment of a local +variable) references would need to be replaced with the undefined location +description, and the bounded lifetime segments would never be active.* + +*Otherwise, the computed lifetime segment applies to a global variable (or +fragment of a global variable) and either involves other global variables (or +fragments of global variables) or local variables (or fragments of local +variables) of multiple subprograms, and therefore needs to be retained by the +LLVM module. Deleting a subprogram must not delete the computed lifetime +segment, although any references to deleted local variables (or fragments of +deleted local variables) would need to be updated to be the undefined location +description.]* + +``DIExpr`` +~~~~~~~~~~ + +.. code:: llvm + + !DIExpr(DIOp, ...) + +Represents an expression, which is a sequence of one or more operations defined +in the following sections. + +The evaluation of an expression is done in the context of an associated +``DILifetime`` that has a ``location`` field that references it. + +The evaluation of the expression is performed on an initially empty stack where +each stack element is a tuple of a type and a location description. The +expression is evaluated by evaluating each of its operations sequentially. + +The result of the evaluation is the typed location description of the single +resulting stack element. If the stack does not have a single element after +evaluation, then the expression is not well-formed. + +.. TODO:: + + Maybe operators should specify their input type(s)? It does not match what + DWARF does currently. Such types cannot trivially be used to enforce type + correctness since the expression language is an arbitrary stack, and in + general the whole expression has to be evaluated to determine the input types + to a given operation. + +Each operation definition begins with a specification which describes the +parameters to the operation, the entries it pops from the stack, and the entries +it pushes on the stack. The specification is accepted by the modified BNF +grammar in *Figure 1—LLVM IR Expression Operation Specification Syntax*, where +``[]`` denotes character classes, ``*`` denotes zero-or-more repetitions of a +term, and ``+`` denotes one-or-more repetitions of a term. + +**Figure 1—LLVM IR Expression Operation Specification Syntax** + +.. code:: bnf + + ::= + + ::= "(" ")" + ::= "" | + ::= ( ", " )+ + ::= ":" + ::= "type" | "unsigned" | "literal" | "addrspace" + + ::= "{" "->" "}" + ::= "" | + ::= ( " " )+ + ::= "(" ":" ")" + + ::= [A-Za-z]+ + ::= [A-Z] [A-Z0-9]* "'"* + +The ```` describes the LLVM IR concrete syntax of the +operation in an expression. + +The ```` defines positional parameters to the operation. +Each parameter in the list has a ```` which binds to the +argument passed via the parameter, and a ```` which +defines the kind of arguments accepted by the parameter. + +The ```` describes the kind of the parameter: + +- ``type``: An LLVM type. +- ``unsigned``: A non-negative literal integer. +- ``literal``: An LLVM literal value expression. +- ``addrspace``: An LLVM target-specific address space identifier. + +The ```` describe the effect of the operation on the +stack. The first ```` describes the “inputs”to the +operation, which are the entries it pops from the stack in the left-to-right +order. The second ```` describes the“outputs” of the +operation, which are the entries it pushes onto the stack in a right-to-left +order. In both cases the top stack element comes first on the left. + +If evaluation can result in a stack with fewer entries than required by an +operation, then the expression is not well-formed. + +Each ```` is a pair of ```` and +````. The ```` binds to the location description +of the stack entry. The ```` binds to the type of the stack entry and +denotes an LLVM type as defined in the :ref:`LLVM Language Reference Manual +`. + +Each ```` identifies a meta-syntactic variable, and each +```` may identify one or more meta-syntactic variables. When reading +the ``specification`` left-to-right, the first mention binds the meta-syntactic +variable to an entity, and subsequent mentions are an assertion that they are +the identical bound entity. If evaluation can result in parameters and stack +inputs that do not conform to the assertions, then the expression is not +well-formed. The assertions for stack outputs define post-conditions of the +operation output. + +The remaining body of the definition for an operation may reference the bound +meta-syntactic variable identifiers from the specification and may define +additional meta-syntactic variables following the same left-to-right binding +semantics. + +In the operation definitions, the following functions are defined: + +- ``bitsizeof(X)``: computes the size in bits of ``X``. +- ``sizeof(X)``: computes ``bitsizeof(X) * 8``. +- ``read(L, T)``: computes the value of type ``T`` obtained by retrieving + ``bitsizeof(T)``: bits from location description ``L``. If any bit of the + value retrieved is from the undefined location storage or the offset of any + bit exceeds the size of the location storage specified by any single location + description of ``L``, then the expression is not well-formed. + +.. TODO:: + + Consider defining reading undefined bits as producing an undefined location + description. This would need DWARF to adopt this model which may be necessary + as compilers support optimized code better. This would need all usage or + ``read`` to be reworded to specify result if ``read`` detects undefined bits. + +.. _amdgpu-llvm-debug-diopreferrer: + +``DIOpReferrer`` +^^^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpReferrer(T:type) + { -> (L:T) } + +``L`` is the location description of the referrer ``R`` of the associated +lifetime segment ``LS``. If ``LS`` is not a bounded lifetime segment, then the +expression is not well-formed. + +If ``bitsizeof(T)`` is not equal to ``bitsizeof(R)``, then the expression is not +well-formed. + +.. _amdgpu-llvm-debug-dioparg: + +``DIOpArg`` +^^^^^^^^^^^ + +.. code:: llvm + + DIOpArg(N:unsigned, T:type) + { -> (L:T) } + +``L`` is the location description of the ``N``\ :sup:`th` zero-based input ``I`` +to the expression. + +If there are fewer than ``N + 1`` inputs to the expression, then the expression +is not well-formed. If ``bitsizeof(T)`` is not equal to ``bitsizeof(I)``, then +the expression is not well-formed. + +*[Note: The inputs for an expression are specified by the* ``argObjects`` *field +of the* ``DILifetime`` *being evaluated which has a* ``location`` *field that +references the expression.]* + +.. _amdgpu-llvm-debug-dioptypeobject: + +``DIOpTypeObject`` +^^^^^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpTypeObject(T:type) + { -> (L:T) } + +``LS`` is the lifetime segment associated with the expression containing +``DIOpTypeObject``. ``TPF`` is the type property fragment that is evaluating +``LS``. ``LT`` is the ``DIType`` that has a type property field ``TP`` that +references ``TPF``. ``L`` is the location description of the instance ``O`` of +an object of type ``LT`` for which the type property ``TP`` is being evaluated. +See :ref:`amdgpu-llvm-debug-dicompositetype`. + +If ``LS`` can be evaluated other than to obtain the location description of a +type property fragment, then the expression is not well-formed. *[Note: This +implies that a type property fragment cannot be referenced by the* ``argObjects`` +*field of a* ``DILifetime``\ *.]* If ``bitsizeof(T)`` is not equal to +``bitsizeof(LT)``, then the expression is not well-formed. + +.. TODO:: + + Should a distinguished ``DIFragment`` be used for this like for LLVM global + variables? There could be a uniqued type object fragment referenced by the + ``!llvm.dbg.typeObject`` named metadata node of the LLVM module. + +``DIOpConstant`` +^^^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpConstant(T:type V:literal) + { -> (L:T) } + +``V`` is a literal value of type ``T`` or the ``undef`` value. + +If ``V`` is the ``undef`` value, then ``L`` comprises one undefined location +description ``IL``. + +Otherwise, ``L`` comprises one implicit location description ``IL``. ``IL`` +specifies implicit location storage ``ILS`` and offset 0. ``ILS`` has value +``V`` and size ``bitsizeof(T)``. + +``DIOpConvert`` +^^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpConvert(T':type) + { (L:T) -> (L':T') } + +``L'`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``V`` and size +``bitsizeof(T')``. If ``bitsizeof(T')`` is greater than ``bitsizeof(T)`` and +``T'`` and ``T`` are both integral types, then the expression is not +well-formed. + +``V`` is the value ``read(L, T)`` converted to type ``T'``. + +*[Note: The conversions used should be limited to those supported by the target +debug format. For example, when the target debug format is DWARF, the +conversions used should be limited to those supported by the* ``DW_OP_convert`` +*operation.]* + +*[Note: The restriction on extending integral types can be resolved by using +either ``DIOpSExt(T')`` or ``DIOpZExt(T')``.]* + +``DIOpZExt`` +^^^^^^^^^^^^ + +.. code:: llvm + + DIOpZExt(T':type) + { (L:T) -> (L':T') } + +``L'`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``V`` and size +``bitsizeof(T')``. If ``T`` and ``T'`` are not integral types, or if +``bitsizeof(T')`` is less than or equal to ``bitsizeof(T)`` then the expression +is not well-formed. + +``V`` is the value ``read(L, T)`` zero-extended to type ``T'``. + +``DIOpSExt`` +^^^^^^^^^^^^ + +.. code:: llvm + + DIOpSExt(T':type) + { (L:T) -> (L':T') } + +``L'`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``V`` and size +``bitsizeof(T')``. If ``T`` and ``T'`` are not integral types, or if +``bitsizeof(T')`` is less than or equal to ``bitsizeof(T)`` then the expression +is not well-formed. + +``V`` is the value ``read(L, T)`` sign-extended to type ``T'``. + +``DIOpReinterpret`` +^^^^^^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpReinterpret(T':type) + { (L:T) -> (L:T') } + +If ``bitsizeof(T)`` is not equal to ``bitsizeof(T')``, then the expression is +not well-formed. + +``DIOpBitOffset`` +^^^^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpBitOffset(T':type) + { (B:I) (L:T) -> (L':T') } + +``L'`` is ``L``, but updated by adding ``read(B, I)`` to its bit offset. + +If ``I`` is not an integral type, then the expression is not well-defined. + +*[Note:* ``I`` *may be a signed or unsigned integral type.]* + +``DIOpByteOffset`` +^^^^^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpByteOffset(T':type) + { (B:I) (L:T) -> (L':T') } + +``(L':T')`` is as if ``DIOpBitOffset(T')`` was evaluated with a stack containing +``(B * 8:I) (L:T)``. + +``DIOpComposite`` +^^^^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpComposite(N:unsigned, T:type) + { (L1:T1) (L2:T2) ... (LN:TN) -> (L:T) } + +``L`` comprises one complete composite location description ``CL`` with offset +0. The location storage associated with ``CL`` is comprised of ``N`` parts each +of bit size ``bitsizeof(TM)`` starting at the location storage specified by +``LM``. The parts are concatenated starting at offset 0 in the order with ``M`` +from ``N`` to 1 and no padding between the parts. + +If the sum of ``bitsizeof(TM)`` for ``M`` from 1 to ``N`` does not equal +``bitsizeof(T)``, then the expression is not well-formed. + +If there are multiple parts that ultimately, after expanding referenced +composites, refer to the same bits of a non-implicit location storage, then the +expression in not well-formed. + +*[Note: A debugger could not in general assign a value to such a composite +location description as different parts of the assigned value may have different +values but map to different parts of the composite location description that are +associated with same bits of a location storage. Any given bits of location +storage can only hold a single value at a time. An implicit location description +does not permit assignment, and so the same bits of its value can be present in +multiple parts of a composite location description.]* + +``DIOpExtend`` +^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpExtend(N:unsigned) + { (L:T) -> (L':) } + +``(L':)'`` is as if ``DIOpComposite(N, )`` was applied to a stack +containing ``N`` copies of ``(L:T)``. + +If ``T`` is not an integral type, floating point type, or pointer type, then the +expression is not well-formed. + +``DIOpSelect`` +^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpSelect() + { (LM:TM) (L1:) (L0:) -> (L:) } + +``M`` is a bit mask with the value ``read(LM, TM)``. If ``bitsizeof(TM)`` is +less than ``N``, then the expression is not well-formed. + +``(L:)`` is as if ``DIOpComposite(N, )`` was applied to a stack +containing ``N`` entries ``(LI:T)`` ordered in descending ``I`` from ``N - 1`` +to 0 inclusive. Each ``LI`` is as if ``DIOpBitOffset(T)`` was applied to a stack +containing ``(I * bitsizeof(T):TI) (PLI:T)``. ``PLI`` is the same as ``L0`` if +the ``I``\ :sup:`th` least significant bit of ``M`` is zero, otherwise it is the +same as ``L1``. ``TI`` is some integral type that can represent the range 0 to +``(N - 1) * bitsizeof(T)``. + +If ``T`` is not an integral type, floating point type, or pointer type, then the +expression is not well-formed. + +.. _amdgpu-llvm-debug-diopaddrof: + +``DIOpAddrOf`` +^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpAddrOf(N:addrspace) + { (L:T) -> (L':ptr addrspace(N)) } + +``L'`` comprises one implicit address location description ``IAL``. ``IAL`` +specifies implicit address location storage ``IALS`` and offset 0. + +``IALS`` is ``bitsizeof(ptr addrspace(N))`` bits and conceptually holds a +reference to the storage that ``L`` denotes. If ``DIOpDeref(T)`` is applied to +the resulting ``(L':ptr addrspace(N))``, then it will result in ``(L:T)``. If +any other operation is applied, then the expression is not well-formed. + +*[Note:* ``DIOpAddrOf`` *can be used for any location description kind of* +``L``\ *, not just memory location descriptions.]* + +*[Note: DWARF only supports creating implicit pointer location descriptors for +variables or DWARF procedures. It does not support creating them for an +arbitrary location description expression. The examples below cover the current +LLVM optimizations and only use* ``DIOpAddrOf`` *applied to* ``DIOpReferrer``\ +*,* ``DIOPArg``\ *, and* ``DIOpConstant``\ *. All these cases can map onto +existing DWARF in a straightforward manner. There would be more complexity if* +``DIOpAddrOf`` *was used in other situations. Such usage could either be +addressed by dropping debug information as LLVM currently does in numerous +situations, or by adding additional DWARF extensions.]* + +``DIOpDeref`` +^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpDeref(T:type) + { (L:ptr addrspace(N)) -> (L':T) } + +If ``(L:ptr addrspace(N))`` was produced by a ``DIOpAddrOf`` operation, then +see :ref:`amdgpu-llvm-debug-diopaddrof`:. + +Otherwise, ``L'`` comprises one memory location description ``MLD``. ``MLD`` +specifies bit offset ``read(L, ptr addrspace(N)) * 8`` and the memory location +storage corresponding to address space ``N``. + +``DIOpRead`` +^^^^^^^^^^^^ + +.. code:: llvm + + DIOpRead() + { (L:T) -> (L':T) } + +``L'`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(L, T)`` +and size ``bitsizeof(T)``. + +``DIOpAdd`` +^^^^^^^^^^^ + +.. code:: llvm + + DIOpAdd() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(L1, T) ++ read(L2, T)`` and size ``bitsizeof(T)``. + +``DIOpSub`` +^^^^^^^^^^^ + +.. code:: llvm + + DIOpSub() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(V2, T) +- read(V1, T)`` and size ``bitsizeof(T)``. + +``DIOpMul`` +^^^^^^^^^^^ + +.. code:: llvm + + DIOpMul() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(V2, T) +* read(V1, T)`` and size ``bitsizeof(T)``. + +``DIOpDiv`` +^^^^^^^^^^^ + +.. code:: llvm + + DIOpDiv() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(V2, T) +/ read(V1, T)`` and size ``bitsizeof(T)``. + +``DIOpMod`` +^^^^^^^^^^^ + +.. code:: llvm + + DIOpMod() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(V2, T) +% read(V1, T)`` and size ``bitsizeof(T)``. + +``DIOpLShr`` +^^^^^^^^^^^^ + +.. code:: llvm + + DIOpLShr() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(V2, T) +>> read(V1, T)`` and size ``bitsizeof(T)``. The higher order bits are filled +with zeros. + +If ``T`` is not an integral type, then the expression is not well-formed. + +``DIOpAShr`` +^^^^^^^^^^^^ + +.. code:: llvm + + DIOpAShr() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(V2, T) +>> read(V1, T)`` and size ``bitsizeof(T)``. The higher order bits are filled +with the value of the sign bit. + +If ``T`` is not an integral type, then the expression is not well-formed. + +``DIOpShl`` +^^^^^^^^^^^ + +.. code:: llvm + + DIOpShl() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(V2, T) +<< read(V1, T)`` and size ``bitsizeof(T)``. The result is filled with 0 bits. + +If ``T`` is not an integral type, then the expression is not well-formed. + +``DIOpAnd`` +^^^^^^^^^^^ + +.. code:: llvm + + DIOpAnd() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(V2, T) +& read(V1, T)`` and size ``bitsizeof(T)``. + +If ``T`` is not an integral type, then the expression is not well-formed. + +``DIOpOr`` +^^^^^^^^^^^ + +.. code:: llvm + + DIOpOr() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(V2, T) +| read(V1, T)`` and size ``bitsizeof(T)``. + +If ``T`` is not an integral type, then the expression is not well-formed. + +``DIOpXor`` +^^^^^^^^^^^ + +.. code:: llvm + + DIOpXor() + { (L1:T) (L2:T) -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has value ``read(V2, T) +^ read(V1, T)`` and size ``bitsizeof(T)``. + +If ``T`` is not an integral type, then the expression is not well-formed. + +``DIOpPushLane`` +^^^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpPushLane(T:type) + { -> (L:T) } + +``L`` comprises one implicit location description ``IL``. ``IL`` specifies +implicit location storage ``ILS`` and offset 0. ``ILS`` has the value of the +target architecture lane identifier of the current source language thread of +execution if the source language is implemented using a SIMD or SIMT execution +model. + +If ``T`` is not an integral type or the source language is not implemented using +a SIMD or SIMT execution model, then the expression is not well-formed. + +``DIOpFragment`` +^^^^^^^^^^^^^^^^ + +.. code:: llvm + + DIOpFragment(O:unsigned, S:unsigned) + { -> } + +An operation with no effect, used only as a means to encode the "fragment" +position of the debug intrinsic or metadata which refers to the expression in +terms of an bit offset ``O`` and bit size ``S``. + +Intrinsics +---------- + +The intrinsics define the program location range over which the location +description specified by a bounded lifetime segment of a ``DILifetime`` is +active. They support defining a single or multiple locations for a source +program variable. Multiple locations can be active at the same program location +as supported by :ref:`amdgpu-dwarf-location-list-expressions`. + +.. _amdgpu-llvm-debug-llvm-dbg-def: + +``llvm.dbg.def`` +~~~~~~~~~~~~~~~~ + +.. code:: llvm + + void @llvm.dbg.def(metadata, metadata) + +The first argument to ``llvm.dbg.def`` is required to be a ``DILifetime`` and is +the beginning of the bounded lifetime being defined. + +The second argument to ``llvm.dbg.def`` is required to be a value-as-metadata +and defines the LLVM entity acting as the referrer of the bounded lifetime +segment specified by the first argument. A value of ``undef`` is allowed and +specifies the undefined location description. + +*[Note:* ``undef`` *can be used when the lifetime segment expression does not +use a* ``DIOpReferrer`` *operation, either because the expression evaluates to a +constant implicit location description, or because it only uses* ``DIOpArg`` +*operations for inputs.]* + +The MC pseudo instruction equivalent is ``DBG_DEF`` which has the same two +arguments with the same meaning: + +.. code:: llvm + + DBG_DEF metadata, + +.. _amdgpu-llvm-debug-llvm-dbg-kill: + +``llvm.dbg.kill`` +~~~~~~~~~~~~~~~~~ + +.. code:: llvm + + void @llvm.dbg.kill(metadata) + +The argument to ``llvm.dbg.kill`` is required to be a ``DILifetime`` and is the +end of the lifetime being killed. + +Every call to the ``llvm.dbg.kill`` intrinsic is required to be reachable from a +call to the ``llvm.dbg.def`` intrinsic which specifies the same ``DILifetime``, +otherwise it is not well-formed. + +The MC pseudo instruction equivalent is ``DBG_KILL`` which has the same argument +with the same meaning: + +.. code:: llvm + + DBG_KILL metadata + +.. _amdgpu-llvm-debug-llvm-dbg-label: + +``llvm.dbg.label`` +~~~~~~~~~~~~~~~~~~ + +.. code:: llvm + + void @llvm.dbg.label(metadata) + +The argument to ``llvm.dbg.label`` is required to be a ``DICode`` and defines +its address value to be the code address of the start of the basic block that +contains it. + +The MC pseudo instruction equivalent is ``DBG_LABEL`` which has the same +argument with the same meaning: + +.. code:: llvm + + DBG_LABEL metadata + +Examples +======== + +Examples which need meta-syntactic variables prefix them with a sigil to +concisely give context. The prefix sigils are: + +========= ======================================================== +**Sigil** **Meaning** +========= ======================================================== +% SSA IR Value +$ Non-SSA MIR Register (for example, post phi-elimination) +# Arbitrary literal constant +========= ======================================================== + +The syntax used in the examples attempts to match LLVM IR/MIR as closely as +possible, with the only new syntax required being that of the expression +language. + +Variable Located In An ``alloca`` +--------------------------------- + +The frontend will generate ``alloca``\ s for every variable, and can trivially +insert a single ``DILifetime`` covering the whole body of the function, with the +expression ``DIExpr(DIOpReferrer(*), DIOpDeref()``, referring to the +``alloca``. Walking the debug intrinsics provides the necessary information to +generate the DWARF ``DW_AT_location`` attributes on variables. + +.. code:: llvm + :number-lines: + + %x.addr = alloca i64, addrspace(5) + call void @llvm.dbg.def(metadata !2, metadata i64 addrspace(5)* %x.addr) + store i64* %x.addr, ... + ... + call void @llvm.dbg.kill(metadata !2) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64 addrspace(5)*), DIOpDeref(i64))) + +Variable Promoted To An SSA Register +------------------------------------ + +The promotion semantically removes one level of indirection, and correspondingly +in the debug expressions for which the ``alloca`` being replaced was the +referrer, an additional ``DIOpAddrOf(N)`` is needed. + +An example is ``mem2reg`` where an ``alloca`` can be replaced with an SSA value: + +.. code:: llvm + :number-lines: + + %x = i64 ... + call void @llvm.dbg.def(metadata !2, metadata i64 %x) + ... + call void @llvm.dbg.kill(metadata !2) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64), DIOpAddrOf(5), DIOpDeref(i64))) + +The canonical form of this is then just ``DIOpReferrer(i64)`` as the pair of +``DIOpAddrOf(N)``, ``DIOpDeref(i64)`` cancel out: + +.. code:: llvm + :number-lines: + + %x = i64 ... + call void @llvm.dbg.def(metadata !2, metadata i64 %x) + ... + call void @llvm.dbg.kill(metadata !2) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64))) + +Implicit Pointer Location Description +------------------------------------- + +The transformation for removing a level of indirection is to add an +``DIOpAddrOf(N)``, which may result in a location description for a pointer to a +non-memory object. + +.. code:: c + :number-lines: + + int x = ...; + int *p = &x; + return *p; + +.. code:: llvm + :number-lines: + + %x.addr = alloca i64, addrspace(5) + call void @llvm.dbg.def(metadata !2, metadata i64 addrspace(5)* %x.addr) + store i64 addrspace(5)* %x.addr, i64 ... + %p.addr = alloca i64*, addrspace(5) + call void @llvm.dbg.def(metadata !4, metadata i64 addrspace(5)* addrspace(5)* %p.addr) + store i64 addrspace(5)* addrspace(5)* %p.addr, i64 addrspace(5)* %x.addr + %0 = load i64 addrspace(5)* addrspace(5)* %p.addr + %1 = load i64 addrspace(5)* %0 + ret i64 %1 + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64 addrspace(5)*), DIOpDeref(i64))) + !3 = !DILocalVariable("p", ...) + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpReferrer(i64 addrspace(5)* addrspace(5)*), DIOpDeref(i64 addrspace(5)*))) + +*[Note: The* ``llvm.dbg.def`` *could either be placed after the* ``alloca`` *or +after the* ``store`` *that defines the variables initial value. The difference +is whether the debugger will be able to allow the user to access the variable +before it is initialized. Proposals exist to allow the compiler to communicate +when a variable is uninitialized separately from defining its location.]* + +First round of ``mem2reg`` promotes ``%p.addr`` to an SSA register ``%p``: + +.. code:: llvm + :number-lines: + + %x.addr = alloca i64, addrspace(5) + store i64 addrspace(5)* %x.addr, i64 ... + call void @llvm.dbg.def(metadata !2, metadata i64 addrspace(5)* %x.addr) + %p = i64 addrspace(5)* %x.addr + call void @llvm.dbg.def(metadata !4, metadata i64 addrspace(5)* %p) + %0 = load i64 addrspace(5)* %p + return i64 %0 + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64 addrspace(5)*), DIOpDeref(i64))) + !3 = !DILocalVariable("p", ...) + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpReferrer(i64 addrspace(5)*), DIOpAddrOf(5), DIOpDeref(i64 addrspace(5)*))) + +Simplify by eliminating ``%p`` and directly using ``%x.addr``: + +.. code:: llvm + :number-lines: + + %x.addr = alloca i64, addrspace(5) + store i64 addrspace(5)* %x.addr, i64 ... + call void @llvm.dbg.def(metadata !2, metadata i64 addrspace(5)* %x.addr) + call void @llvm.dbg.def(metadata !4, metadata i64 addrspace(5)* %x.addr) + load i64 %0, i64 addrspace(5)* %x.addr + return i64 %0 + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64 addrspace(5)*), DIOpDeref(i64))) + !3 = !DILocalVariable("p", ...) + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpReferrer(i64 addrspace(5)*))) + +Second round of ``mem2reg`` promotes ``%x.addr`` to an SSA register ``%x``: + +.. code:: llvm + :number-lines: + + %x = i64 ... + call void @llvm.dbg.def(metadata !2, metadata i64 %x) + call void @llvm.dbg.def(metadata !4, metadata i64 %x) + %0 = i64 %x + return i64 %0 + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64), DIOpAddrOf(5), DIOpDeref(i64))) + !3 = !DILocalVariable("p", ...) + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpReferrer(i64), DIOpAddrOf(5))) + +Simplify by eliminating adjacent ``DIOpAddrOf(5), DIOpDeref(i64)`` and use +``%x`` directly in the ``return``: + +.. code:: llvm + :number-lines: + + %x = i64 ... + call void @llvm.dbg.def(metadata !2, metadata i64 %x) + call void @llvm.dbg.def(metadata !2, metadata i64 %x) + return i64 %x + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64))) + !3 = !DILocalVariable("p", ...) + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpReferrer(i64), DIOpAddrOf(5))) + +If ``%x`` was being assigned a constant, then can eliminated ``%x`` entirely and +substitute all uses with the constant: + +.. code:: llvm + :number-lines: + + call void @llvm.dbg.def(metadata !2, metadata i1 undef) + call void @llvm.dbg.def(metadata !4, metadata i1 undef) + return i64 ... + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpConstant(i64 ...))) + !3 = !DILocalVariable("p", ...) + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpConstant(i64 ...), DIOpAddrOf(5))) + +Local Variable Broken Into Two Scalars +-------------------------------------- + +When a transformation decomposes one location into multiple distinct ones, it +needs to follow all ``llvm.dbg.def`` intrinsics to the ``DILifetime``\ s +referencing the original location and update the expression and positional +arguments such that: + +- All instances of ``DIOpReferrer()`` in the original expression are replaced + with the appropriate composition of all the new location pieces, now encoded + via multiple ``DIOpArg()`` operations referring to input ``DIObject``\ s, and + a ``DIOpComposite`` operation. This makes the associated ``DILifetime`` a + computed lifetime segment. +- Those location pieces are represented by new ``DIFragment``\ s, one per new + location, each with appropriate ``DILifetime``\ s referenced by new + ``llvm.dbg.def`` and ``llvm.dbg.kill`` intrinsics. + +It is assumed that any transformation capable of doing the decomposition in the +first place needs to have all of this information available, and the structure +of the new intrinsics and metadata avoids any costly operations during +transformations. This update is also “shallow”, in that only the ``DILifetime`` +which is immediately referenced by the relevant ``llvm.dbg.def``\ s need to be +updated, as the result is referentially transparent to any other dependent +``DILifetime``\ s. + +.. code:: llvm + :number-lines: + + %x = ... + call void @llvm.dbg.def(metadata !2, metadata i64 addrspace(5)* %x) + ... + call void @llvm.dbg.kill(metadata !2) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64 addrspace(5)*))) + +Transformed a ``i64`` SSA value into two ``i32`` SSA values: + +.. code:: llvm + :number-lines: + + %x.lo = i32 ... + call void @llvm.dbg.def(metadata !4, metadata i32 %x.lo) + ... + %x.hi = i32 ... + call void @llvm.dbg.def(metadata !6, metadata i32 %x.hi) + ... + call void @llvm.dbg.kill(metadata !6) + call void @llvm.dbg.kill(metadata !4) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpArg(1, i32), DIOpArg(0, i32), DIOpComposite(2, i64)), argObjects: {!3, !5}) + !3 = distinct !DIFragment() + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpReferrer(i32))) + !5 = distinct !DIFragment() + !6 = distinct !DILifetime(object: !5, location: !DIExpr(DIOpReferrer(i32))) + +Further Decomposition Of An Already SRoA’d Local Variable +--------------------------------------------------------- + +An example to demonstrate the “shallow update” property is to take the above IR: + +.. code:: llvm + :number-lines: + + %x.lo = i32 ... + call void @llvm.dbg.def(metadata !4, metadata i32 %x.lo) + ... + %x.hi = i32 ... + call void @llvm.dbg.def(metadata !6, metadata i32 %x.hi) + ... + call void @llvm.dbg.kill(metadata !6) + call void @llvm.dbg.kill(metadata !4) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpArg(1, i32), DIOpArg(0, i32), DIOpComposite(2, i64)), argObjects: {!3, !5}) + !3 = distinct !DIFragment() + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpReferrer(i32))) + !5 = distinct !DIFragment() + !6 = distinct !DILifetime(object: !5, location: !DIExpr(DIOpReferrer(i32))) + +and subdivide ``%x.hi`` again: + +.. code:: llvm + :number-lines: + + %x.lo = i32 ... + call void @llvm.dbg.def(metadata !4, metadata i32 %x.lo) + %x.hi.lo = i16 ... + call void @llvm.dbg.def(metadata !8, metadata i16 %x.hi.lo) + %x.hi.hi = i16 ... + call void @llvm.dbg.def(metadata !10, metadata i16 %x.hi.hi) + ... + call void @llvm.dbg.kill(metadata !10) + call void @llvm.dbg.kill(metadata !8) + call void @llvm.dbg.kill(metadata !4) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpArg(1, i32), DIOpArg(0, i32), DIOpComposite(2, i64)), argObjects: {!3, !5}) + !3 = distinct !DIFragment() + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpReferrer(i32))) + !5 = distinct !DIFragment() + !6 = distinct !DILifetime(object: !5, location: !DIExpr(DIOpArg(1, i16), DIOpArg(0, i16), DIOpComposite(2, i32)), argObjects: {!7, !9}) + !7 = distinct !DIFragment() + !8 = distinct !DILifetime(object: !7, location: !DIExpr(DIOpReferrer(i16))) + !9 = distinct !DIFragment() + !10 = distinct !DILifetime(object: !9, location: !DIExpr(DIOpReferrer(i16))) + +Note that the expression for the original source variable ``x`` did not need to +be changed, as it is defined in terms of the ``DIFragment``, the identity of +which is not changed after it is created. + +Multiple Live Ranges For A Single Variable +------------------------------------------ + +Once out of SSA, or even while in SSA via memory, there may be multiple re-uses +of the same storage for completely disparate variables, and disjoint and/or +overlapping lifetimes for any single variable. This is modeled naturally by +maintaining *defs* and *kills* for these live ranges independently at, for +example, definitions and clobbers. + +.. code:: llvm + :number-lines: + + $r0 = MOV ... + DBG_DEF !2, $r0 + ... + SPILL %frame.index.0, $r0 + DBG_DEF !3, %frame.index.0 + ... + $r0 = MOV ; clobber + DBG_KILL !2 + DBG_DEF !6, $r0 + ... + $r1 = MOV ... + DBG_DEF !4, $r1 + ... + DBG_KILL !6 + DBG_KILL !4 + DBG_KILL !3 + RETURN + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i32))) + !3 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i32))) + !4 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i32))) + !5 = !DILocalVariable("y", ...) + !6 = distinct !DILifetime(object: !5, location: !DIExpr(DIOpReferrer(i32))) + +In this example, ``$r0`` is referred to by disjoint ``DILifetime``\ s for +different variables. There is also a point where multiple ``DILifetime``\ s for +the same variable are live. + +The first point implies the need for intrinsics/pseudo-instructions to define +the live range, as simply referring to an LLVM entity does not provide enough +information to reconstruct the live range. + +The second point is needed to accurately represent cases where, for example, a +variable lives in both a register and in memory. The current +intrinsics/pseudo-instructions do not have the notion of live ranges for source +variables, and simply throw away at least one of the true lifetimes in these +cases. + +Global Variable Broken Into Two Scalars +--------------------------------------- + +.. code:: llvm + :number-lines: + + @g = i64 !dbg.def !2 + + !llvm.dbg.cu = !{!0} + !llvm.dbg.retainedNodes = !{!3} + !0 = !DICompileUnit(..., globals: !{!1}) + !1 = !DIGlobalVariable("g") + !2 = distinct DIFragment() + !3 = distinct !DILifetime( + object: !1, + location: !DIExpr( + DIOpArg(0, i64 addrspace(1)*), + DIDeref() + ), + argObjects: {!2} + ) + +Becomes: + +.. code:: llvm + :number-lines: + + @g.lo = i32 !dbg.def !2 + @g.hi = i32 !dbg.def !3 + + !llvm.dbg.cu = !{!0} + !llvm.dbg.retainedNodes = !{!4} + !0 = !DICompileUnit(..., globals: !{!1}) + !1 = !DIGlobalVariable("g") + !2 = distinct !DIFragment() + !3 = distinct !DIFragment() + !4 = distinct !DILifetime( + object: !1, + location: !DIExpr( + DIOpArg(1, i32 addrspace(1)*), + DIDeref(), + DIOpArg(0, i32 addrspace(1)*), + DIDeref(), + DIOpComposite(2, i64) + ), + argObjects: {!2, !3} + ) + +A function can specify the location of the global variable ``!1`` over some +range by simply defining bounded lifetime segments that also reference ``!1``. +These will override the “default” location description specified by the computed +lifetime segment ``!4``. + +Induction Variable +------------------ + +Starting with some program: + +.. code:: llvm + :number-lines: + + %x = i64 ... + call void @llvm.dbg.def(metadata !2, metadata i64 %x) + ... + %y = i64 ... + call void @llvm.dbg.def(metadata !4, i64 %y) + ... + %i = i64 ... + call void @llvm.dbg.def(metadata !6, metadata i64 %z) + ... + call void @llvm.dbg.kill(metadata !6) + call void @llvm.dbg.kill(metadata !4) + call void @llvm.dbg.kill(metadata !2) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64))) + !3 = !DILocalVariable("y", ...) + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpReferrer(i64))) + !5 = !DILocalVariable("i", ...) + !6 = distinct !DILifetime(object: !5, location: !DIExpr(DIOpReferrer(i64))) + +If analysis proves ``i`` over some range is equal to ``x + y``, the storage for +``i`` can be eliminated, and it can be materialized at every use. The +corresponding change needed in the debug information is: + +.. code:: llvm + :number-lines: + + %x = i64 ... + call void @llvm.dbg.def(metadata !2, metadata i64 %x) + ... + %y = i64 ... + call void @llvm.dbg.def(metadata !4, metadata i64 %y) + ... + call void @llvm.dbg.def(metadata !6, metadata i64 undef) + ... + call void @llvm.dbg.kill(metadata !6) + call void @llvm.dbg.kill(metadata !4) + call void @llvm.dbg.kill(metadata !2) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64))) + !3 = !DILocalVariable("y", ...) + !4 = distinct !DILifetime(object: !3, location: !DIExpr(DIOpReferrer(i64))) + !5 = !DILocalVariable("i", ...) + !6 = distinct !DILifetime(object: !5, location: !DIExpr(DIOpArg(0, i64), DIOpArg(1, i64), DIOpAdd()), DIOpArg(!1, !3}) + +For the given range, the value of ``i`` is computable so long as both ``x`` and +``y`` are live, the determination of which is left until the backend debug +information generation (for example, for old DWARF or for other debug +information formats), or until debugger runtime when the expression is evaluated +(for example, for DWARF with ``DW_OP_call`` and ``DW_TAG_dwarf_procedure``). +During compilation, this representation allows all updates to maintain the debug +information efficiently by making updates “shallow”. + +In other cases, this can allow the debugger to provide locations for part of a +source variable, even when other parts are not available. This may be the case +if a ``struct`` with many fields is broken up during SRoA and the lifetimes of +each piece diverge. + +Proven Constant +--------------- + +As a very similar example to the above induction variable case (in terms of the +updates needed in the debug information), the case where a variable is proven to +be a statically known constant over some range turns the following: + +.. code:: llvm + :number-lines: + + %x = i64 ... + call void @llvm.dbg.def(metadata !2, metadata i64 %x) + ... + call void @llvm.dbg.kill(metadata !2) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpReferrer(i64))) + +into: + +.. code:: llvm + :number-lines: + + call void @llvm.dbg.def(metadata !2, metadata i64 undef) + ... + call void @llvm.dbg.kill(metadata !2) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(DIOpConstant(i64 ...))) + +Common Subexpression Elimination (CSE) +-------------------------------------- + +This is the example from `Bug 40628 - [DebugInfo@O2] Salvaged memory loads can +observe subsequent memory writes +`__: + +.. code:: c + :number-lines: + + int + foo(int *bar, int arg, int more) + { + int redundant = *bar; + int loaded = *bar; + arg &= more + loaded; + + *bar = 0; + + return more + *bar; + } + + int + main() { + int lala = 987654; + return foo(&lala, 1, 2); + } + +Which after ``SROA+mem2reg`` becomes (where ``redundant`` is ``!17`` and +``loaded`` is ``!16``): + +.. code:: llvm + :number-lines: + + ; Function Attrs: noinline nounwind uwtable + define dso_local i32 @foo(i32* %bar, i32 %arg, i32 %more) #0 !dbg !7 { + entry: + call void @llvm.dbg.value(metadata i32* %bar, metadata !13, metadata !DIExpression()), !dbg !18 + call void @llvm.dbg.value(metadata i32 %arg, metadata !14, metadata !DIExpression()), !dbg !18 + call void @llvm.dbg.value(metadata i32 %more, metadata !15, metadata !DIExpression()), !dbg !18 + %0 = load i32, i32* %bar, align 4, !dbg !19, !tbaa !20 + call void @llvm.dbg.value(metadata i32 %0, metadata !16, metadata !DIExpression()), !dbg !18 + %1 = load i32, i32* %bar, align 4, !dbg !24, !tbaa !20 + call void @llvm.dbg.value(metadata i32 %1, metadata !17, metadata !DIExpression()), !dbg !18 + %add = add nsw i32 %more, %1, !dbg !25 + %and = and i32 %arg, %add, !dbg !26 + call void @llvm.dbg.value(metadata i32 %and, metadata !14, metadata !DIExpression()), !dbg !18 + store i32 0, i32* %bar, align 4, !dbg !27, !tbaa !20 + %2 = load i32, i32* %bar, align 4, !dbg !28, !tbaa !20 + %add1 = add nsw i32 %more, %2, !dbg !29 + ret i32 %add1, !dbg !30 + } + +And previously led to this after ``EarlyCSE``, which removes the redundant load +from ``%bar``: + +.. code:: llvm + :number-lines: + + define dso_local i32 @foo(i32* %bar, i32 %arg, i32 %more) #0 !dbg !7 { + entry: + call void @llvm.dbg.value(metadata i32* %bar, metadata !13, metadata !DIExpression()), !dbg !18 + call void @llvm.dbg.value(metadata i32 %arg, metadata !14, metadata !DIExpression()), !dbg !18 + call void @llvm.dbg.value(metadata i32 %more, metadata !15, metadata !DIExpression()), !dbg !18 + + ; This is not accurate to begin with, as a debugger which modifies + ; `redundant` will erroneously update the pointee of the parameter `bar`. + call void @llvm.dbg.value(metadata i32* %bar, metadata !16, metadata !DIExpression(DW_OP_deref)), !dbg !18 + + %0 = load i32, i32* %bar, align 4, !dbg !19, !tbaa !20 + call void @llvm.dbg.value(metadata i32 %0, metadata !17, metadata !DIExpression()), !dbg !18 + %add = add nsw i32 %more, %0, !dbg !24 + call void @llvm.dbg.value(metadata i32 undef, metadata !14, metadata !DIExpression()), !dbg !18 + + ; This store "clobbers" the debug location description for `redundant`, such + ; that a debugger about to execute the following `ret` will erroneously + ; report `redundant` as equal to `0` when the source semantics have it still + ; equal to the value pointed to by `bar` on entry. + store i32 0, i32* %bar, align 4, !dbg !25, !tbaa !20 + ret i32 %more, !dbg !26 + } + +But now becomes (conservatively): + +.. code:: llvm + :number-lines: + + define dso_local i32 @foo(i32* %bar, i32 %arg, i32 %more) #0 !dbg !7 { + entry: + call void @llvm.dbg.value(metadata i32* %bar, metadata !13, metadata !DIExpression()), !dbg !18 + call void @llvm.dbg.value(metadata i32 %arg, metadata !14, metadata !DIExpression()), !dbg !18 + call void @llvm.dbg.value(metadata i32 %more, metadata !15, metadata !DIExpression()), !dbg !18 + + ; The above mentioned patch for PR40628 adds special treatment, dropping + ; the debug information for `redundant` completely in this case, making + ; this conservatively correct. + call void @llvm.dbg.value(metadata i32 undef, metadata !16, metadata !DIExpression()), !dbg !18 + + %0 = load i32, i32* %bar, align 4, !dbg !19, !tbaa !20 + call void @llvm.dbg.value(metadata i32 %0, metadata !17, metadata !DIExpression()), !dbg !18 + %add = add nsw i32 %more, %0, !dbg !24 + call void @llvm.dbg.value(metadata i32 undef, metadata !14, metadata !DIExpression()), !dbg !18 + store i32 0, i32* %bar, align 4, !dbg !25, !tbaa !20 + ret i32 %more, !dbg !26 + } + +Effectively at the point of the CSE eliminating the load, it conservatively +marks the source variable ``redundant`` as optimized out. + +It seems like the semantics that CSE really wants to encode in the debug +intrinsics is that, after the point at which the common load occurs, the +location for both ``redundant`` and ``loaded`` is ``%0``, and that they are both +read-only. It seems like it needs to prove this to combine them, and if it can +only combine them over some range, it can insert additional live ranges to +describe their separate locations outside of that range. The implicit pointer +example further suggests why this may need to be the case, because at the time +the implicit pointer is created, it is not known which source variable to bind +to in order to get the multiple lifetimes in this design. + +This seems to be supported by the fact that even in current LLVM trunk, with the +more conservative change to mark the ``redundant`` variable as ``undef`` in the +above case, changing the source to modify ``redundant`` after the load results +in both ``redundant`` and ``loaded`` referring to the same location, and both +being read-write. A modification of ``redundant`` in the debugger before the use +of ``loaded`` is permitted and would have the effect of also updating +``loaded``. An example of the modified source needed to cause this is: + +.. code:: c + :number-lines: + + int + foo(int *bar, int arg, int more) + { + int redundant = *bar; + int loaded = *bar; + arg &= more + loaded; // A store to redundant here affects loaded. + + *bar = redundant; // The use and subsequent modification of `redundant` here + redundant = 1; // effectively circumvents the patch for PR40628. + + return more + *bar; + } + + int + main() { + int lala = 987654; + return foo(&lala, 1, 2); + } + +Note that after ``EarlyCSE``, this example produces the same location +description for both ``redundant`` and ``loaded`` (metadata ``!17`` and +``!18``): + +.. code:: llvm + :number-lines: + + define dso_local i32 @foo(i32* %bar, i32 %arg, i32 %more) #0 !dbg !8 { + entry: + call void @llvm.dbg.value(metadata i32* %bar, metadata !14, metadata !DIExpression()), !dbg !19 + call void @llvm.dbg.value(metadata i32 %arg, metadata !15, metadata !DIExpression()), !dbg !19 + call void @llvm.dbg.value(metadata i32 %more, metadata !16, metadata !DIExpression()), !dbg !19 + %0 = load i32, i32* %bar, align 4, !dbg !20, !tbaa !21 + + ; The same location is reused for both source variables, without it being + ; marked read-only (namely without it being made into an implicit location + ; description). + call void @llvm.dbg.value(metadata i32 %0, metadata !17, metadata !DIExpression()), !dbg !19 + call void @llvm.dbg.value(metadata i32 %0, metadata !18, metadata !DIExpression()), !dbg !19 + + ; Modifications to either source variable in a debugger affect the other from + ; this point on in the function. + %add = add nsw i32 %more, %0, !dbg !25 + call void @llvm.dbg.value(metadata i32 undef, metadata !15, metadata !DIExpression()), !dbg !19 + call void @llvm.dbg.value(metadata i32 1, metadata !17, metadata !DIExpression()), !dbg !19 + ret i32 %add, !dbg !26 + } + +*[Note: To see this result, i386 is required; x86_64 seems to do even more +optimization which eliminates both* ``loaded`` *and* ``redundant``\ *.]* + +Fixing this issue in the current debug information is technically possible, but +as noted by the LLVM community in the review for the attempted conservative +patch: + + *“this isn’t something that can be fixed without a lot of work, thus it’s + safer to turn off for now.”* + +The LLVM extensions make this case tractable to support with full generality and +composability with other optimizations. The expected result of ``EarlyCSE`` +would be: + +.. code:: llvm + :number-lines: + + define dso_local i32 @foo(i32* %bar, i32 %arg, i32 %more) #0 !dbg !8 { + entry: + call void @llvm.dbg.def(metadata i32* %bar, metadata !19), !dbg !19 + call void @llvm.dbg.def(metadata i32 %arg, metadata !20), !dbg !19 + call void @llvm.dbg.def(metadata i32 %more, metadata !21), !dbg !19 + %0 = load i32, i32* %bar, align 4, !dbg !20, !tbaa !21 + + call void @llvm.dbg.def(metadata i32 %0, metadata !22), !dbg !19 + call void @llvm.dbg.def(metadata i32 %0, metadata !23), !dbg !19 + + %add = add nsw i32 %more, %0, !dbg !25 + ret i32 %add, !dbg !26 + } + + !14 = !DILocalVariable("bar", ...) + !15 = !DILocalVariable("arg", ...) + !16 = !DILocalVariable("more", ...) + !17 = !DILocalVariable("redundant", ...) + !18 = !DILocalVariable("loaded", ...) + !19 = distinct !DILifetime(object: !14, location: !DIExpr(DIOpReferrer(i32*))) + !20 = distinct !DILifetime(object: !15, location: !DIExpr(DIOpReferrer(i32))) + !21 = distinct !DILifetime(object: !16, location: !DIExpr(DIOpReferrer(i32))) + !21 = distinct !DILifetime(object: !17, location: !DIExpr(DIOpReferrer(i32), DIOpRead())) + !22 = distinct !DILifetime(object: !18, location: !DIExpr(DIOpReferrer(i32), DIOpRead())) + +Which accurately describes that both ``redundant`` and ``loaded`` are read-only +after the common load. + +Divergent Lane PC +----------------- + +For AMDGPU, the ``DW_AT_LLVM_lane_pc`` attribute is used to specify the program +location of the separate lanes of a SIMT thread. + +If the lane is an active lane, then this will be the same as the current program +location. + +If the lane is inactive, but was active on entry to the subprogram, then this is +the program location in the subprogram at which execution of the lane is +conceptual positioned. + +If the lane was not active on entry to the subprogram, then this will be the +undefined location. A client debugger can check if the lane is part of a valid +work-group by checking that the lane is in the range of the associated +work-group within the grid, accounting for partial work-groups. If it is not, +then the debugger can omit any information for the lane. Otherwise, the debugger +may repeatedly unwind the stack and inspect the ``DW_AT_LLVM_lane_pc`` of the +calling subprogram until it finds a non-undefined location. Conceptually the +lane only has the call frames that it has a non-undefined +``DW_AT_LLVM_lane_pc``. + +The following example illustrates how the AMDGPU backend can generate a DWARF +location list expression for the nested ``IF/THEN/ELSE`` structures of the +following subprogram pseudo code for a target with 64 lanes per wavefront. + +.. code:: llvm + :number-lines: + + SUBPROGRAM X + BEGIN + a; + IF (c1) THEN + b; + IF (c2) THEN + c; + ELSE + d; + ENDIF + e; + ELSE + f; + ENDIF + g; + END + +The AMDGPU backend may generate the following pseudo LLVM MIR to manipulate the +execution mask (``EXEC``) to linearize the control flow. The condition is +evaluated to make a mask of the lanes for which the condition evaluates to true. +First the ``THEN`` region is executed by setting the ``EXEC`` mask to the +logical ``AND`` of the current ``EXEC`` mask with the condition mask. Then the +``ELSE`` region is executed by negating the ``EXEC`` mask and logical ``AND`` of +the saved ``EXEC`` mask at the start of the region. After the ``IF/THEN/ELSE`` +region the ``EXEC`` mask is restored to the value it had at the beginning of the +region. This is shown below. Other approaches are possible, but the basic +concept is the same. + +.. code:: llvm + :number-lines: + + %lex_start: + a; + %1 = EXEC + %2 = c1 + %lex_1_start: + EXEC = %1 & %2 + $if_1_then: + b; + %3 = EXEC + %4 = c2 + %lex_1_1_start: + EXEC = %3 & %4 + %lex_1_1_then: + c; + EXEC = ~EXEC & %3 + %lex_1_1_else: + d; + EXEC = %3 + %lex_1_1_end: + e; + EXEC = ~EXEC & %1 + %lex_1_else: + f; + EXEC = %1 + %lex_1_end: + g; + %lex_end: + +To create the DWARF location list expression that defines the location +description of a vector of lane program locations, the LLVM MIR ``DBG_DEF`` +pseudo instruction can be used to annotate the linearized control flow. This can +be done by defining a ``DIFragment`` for the lane PC and using it as the +``activeLanePC`` parameter of the corresponding ``DISubprogram`` of the function +being described. The DWARF location list expression created for it is used as +the value of the ``DW_AT_LLVM_lane_pc`` attribute on the subprogram’s debugger +information entry. + +A ``DIFragment`` is defined for each well nested structured control flow region +which provides the conceptual lane program location for a lane if it is not +active (namely it is divergent). The ``DIFragment`` for each region has a single +computed ``DILifetime`` whose location expression conceptually inherits the +value of the immediately enclosing region and modifies it according to the +semantics of the region. + +By having a separate ``DIFragment`` for each region, they can be reused to +define the value for any nested region. This reduces the total size of the DWARF +operation expressions. + +A “bounded divergent lane PC” ``DIFragment`` is defined which computes the +program location for each lane assuming they are divergent at every instruction +in the function. This fragment has one bounded lifetime for each region. Each +bounded lifetime specifies a single ``DIFragment`` for a region and is active +over a disjoint range of the function instructions corresponding to that region. +Together the lifetimes cover all instructions of the function, such that at +every PC in the function exactly one lifetime is active. + +For an ``IF/THEN/ELSE`` region, the divergent program location is at the start +of the region for the ``THEN`` region since it is executed first. For the +``ELSE`` region, the divergent program location is at the end of the +``IF/THEN/ELSE`` region since the ``THEN`` region has completed. + +The lane PC fragment is then defined with an expression that takes the bounded +divergent lane PC and modifies it by inserting the current program location for +each lane that the ``EXEC`` mask indicates is active. + +The following provides an example using pseudo LLVM MIR. + +.. code:: llvm + :number-lines: + + ; NOTE: This listing is written in a pseudo LLVM MIR, as this debug information + ; will be inserted as part of inserting EXEC manipulation into LLVM MIR. + ; + ; This pseudo-MIR uses named metadata identifiers (e.g. !foo) to identify + ; unnamed metadata (e.g. !0). To translate to MIR assign each unique named + ; metadata identifier a monotonically increasing unnamed metadata identifier, + ; then replace all references to each named metadata identifier with its + ; corresponding unnamed metadata identifier. + ; + ; The identifiers are named as a dot (`.`) separated list of elements, + ; ending with a tag corresponding to the type of metadata they identify. + ; + ; In MIR a `!DIExpr` is always printed inline at its use, even though it is + ; internally uniqued and shared by all uses of the same expression. In this + ; pseudo-MIR we break this convention and write the expressions out-of-line + ; in some cases to emphasize where sharing occurs and to shorten the listing. + + lex_start: + ; NOTE: These lifetimes for the PC/EXEC registers define the typical, + ; default case of referring directly to the physical register. For cases + ; like WQM where the physical EXEC and "logical" EXEC are not the same, + ; this will be overriden by defining a bounded lifetime for + ; !pc.fragment/!exec.fragment. + DBG_DEF !pc.physical.lifetime, $PC + DBG_DEF !exec.physical.lifetime, $EXEC + DBG_DEF !bounded_divergent_lane_pc.lex.a.lifetime, $noreg + a; + %1 = EXEC; + DBG_DEF !save_exec.lex_1.lifetime, u64 %1 + %2 = c1; + DBG_KILL !bounded_divergent_lane_pc.lex.a.lifetime + lex_1_start: + DBG_LABEL !lex_1_start.label + EXEC = %1 & %2; + lex_1_then: + DBG_DEF !bounded_divergent_lane_pc.lex_1_then.a.lifetime, $noreg + b; + %3 = EXEC; + DBG_DEF !save_exec.lex_1_1.lifetime, u64 %3 + %4 = c2; + DBG_KILL !bounded_divergent_lane_pc.lex_1_then.a.lifetime + lex_1_1_start: + DBG_LABEL !lex_1_1_start.label + EXEC = %3 & %4; + lex_1_1_then: + DBG_DEF !bounded_divergent_lane_pc.lex_1_1_then.a.lifetime, $noreg + c; + DBG_KILL !bounded_divergent_lane_pc.lex_1_1_then.a.lifetime + EXEC = ~EXEC & %3; + lex_1_1_else: + DBG_DEF !bounded_divergent_lane_pc.lex_1_1_else.a.lifetime, $noreg + d; + DBG_KILL !bounded_divergent_lane_pc.lex_1_1_else.a.lifetime + EXEC = %3; + DBG_KILL !save_exec.lex_1_1.lifetime + lex_1_1_end: + DBG_LABEL !lex_1_1_end.label + DBG_DEF !bounded_divergent_lane_pc.lex_1_then.b.lifetime, $noreg + e; + DBG_KILL !bounded_divergent_lane_pc.lex_1_then.b.lifetime + EXEC = ~EXEC & %1; + lex_1_else: + DBG_DEF !bounded_divergent_lane_pc.lex_1_else.a.lifetime, $noreg + f; + DBG_KILL !bounded_divergent_lane_pc.lex_1_else.a.lifetime + EXEC = %1; + DBG_KILL !save_exec.lex_1.lifetime + lex_1_end: + DBG_LABEL !lex_1_end.label + DBG_DEF !bounded_divergent_lane_pc.lex.b.lifetime, $noreg + g; + lex_end: + + ;; Labels + !lex_1_start.label = distinct !DExprCode() + !lex_1_1_start.label = distinct !DExprCode() + !lex_1_1_end.label = distinct !DExprCode() + !lex_1_end.label = distinct !DExprCode() + + ;; Saved EXEC Mask Fragments + ; These track the value of the EXEC mask saved on entry to each `IF/THEN/ELSE` + ; region. The saved mask identifies the lanes to be updated when defining the + ; computed divergent_lane_pc for a given lexical block (or, put another way, + ; the negation of the saved mask identifies the lanes which are not updated). + !save_exec.lex_1.fragment = distinct !DIFragment() + !save_exec.lex_1.lifetime = distinct !DILifetime( + object: !save_exec.lex_1.fragment, + location: !DIExpr(DIOpReferrer(u64)) + ) + !save_exec.lex_1_1.fragment = distinct !DIFragment() + !save_exec.lex_1_1.lifetime = distinct !DILifetime( + object: !save_exec.lex_1_1.fragment, + location: !DIExpr(DIOpReferrer(u64)) + ) + + ;; Logical and Physical Register Fragments + ; NOTE: We refer to the "logical" EXEC, `!exec.fragment`, in other expressions. + ; This may be computed in cases where the physical EXEC was updated to + ; implement e.g. whole-quad-mode. Referring to this fragment makes the uses + ; transparently support this. The same approach is applied for the PC. + !pc.fragment = distinct !DIFragment() + !pc.default.lifetime = distinct !DILifetime( + object: !pc.fragment, + location: !DIExpr(DIOpArg(u64)), + argObjects: {!pc.physical.fragment} + ) + !pc.physical.fragment = distinct !DIFragment() + !pc.physical.lifetime = distinct !DILifetime( + object: !pc.physical.fragment, + location: !DIExpr(DIOpReferrer(u64)) + ) + !exec.fragment = distinct !DIFragment() + !exec.default.lifetime = distinct !DILifetime( + object: !exec.fragment, + location: !DIExpr(DIOpArg(u64)), + argObjects: {!exec.physical.fragment} + ) + !exec.physical.fragment = distinct !DIFragment() + !exec.physical.lifetime = distinct !DILifetime( + object: !exec.physical.fragment, + location: !DIExpr(DIOpReferrer(u64)) + ) + + ;; Bounded Divergent Lane PC + ; This fragment has disjoint lifetimes which cover the entire PC range of the + ; function. It contains the divergent_lane_pc for all lanes which are + ; divergent, with unspecified values present in active lanes (as an artifact of + ; the current implementation, the active lanes are assigned the same value as + ; the divergent lanes which were active on entry to the current `IF/THEN/ELSE` + ; region, but this is neither guaranteed nor required). + !bounded_divergent_lane_pc.fragment = distinct !DIFragment() + ; The argObjects to !bounded_divergent_lane_pc.expr are: + ; {<64 x u64> lane_pc_vec} + !bounded_divergent_lane_pc.expr = !DIExpr(DIOpArg(<64 x u64>)) + !bounded_divergent_lane_pc.lex.a.lifetime = distinct !DILifetime( + object: !bounded_divergent_lane_pc.fragment, + location: !bounded_divergent_lane_pc.expr, + argObjects: {!divergent_lane_pc.lex.fragment} + ) + !bounded_divergent_lane_pc.lex_1_then.a.lifetime = distinct !DILifetime( + object: !bounded_divergent_lane_pc.fragment, + location: !bounded_divergent_lane_pc.expr, + argObjects: {!divergent_lane_pc.lex_1_then.fragment} + ) + !bounded_divergent_lane_pc.lex_1_1_then.a.lifetime = distinct !DILifetime( + object: !bounded_divergent_lane_pc.fragment, + location: !bounded_divergent_lane_pc.expr, + argObjects: {!divergent_lane_pc.lex_1_1_then.fragment} + ) + !bounded_divergent_lane_pc.lex_1_1_else.a.lifetime = distinct !DILifetime( + object: !bounded_divergent_lane_pc.fragment, + location: !bounded_divergent_lane_pc.expr, + argObjects: {!divergent_lane_pc.lex_1_1_else.fragment} + ) + !bounded_divergent_lane_pc.lex_1_then.b.lifetime = distinct !DILifetime( + object: !bounded_divergent_lane_pc.fragment, + location: !bounded_divergent_lane_pc.expr, + argObjects: {!divergent_lane_pc.lex_1_then.fragment} + ) + !bounded_divergent_lane_pc.lex_1_else.a.lifetime = distinct !DILifetime( + object: !bounded_divergent_lane_pc.fragment, + location: !bounded_divergent_lane_pc.expr, + argObjects: {!divergent_lane_pc.lex_1_else.fragment} + ) + !bounded_divergent_lane_pc.lex.b.lifetime = distinct !DILifetime( + object: !bounded_divergent_lane_pc.fragment, + location: !bounded_divergent_lane_pc.expr, + argObjects: {!divergent_lane_pc.lex.fragment} + ) + + ; TODO: Maybe add a property of DIFragment that asserts it should never have + ; more than a single location description for any PC + + ; TODO: To easily translate Extend, Select, Read, etc. + ; into DWARF, they will needs a type parameter. Should we add a type to just the + ; operations which correspond to a DWARF operation that needs the type/size? Or + ; should we just add types to all operations? + + ;; Computed Divergent Lane PC Fragments + !divergent_lane_pc.lex.fragment = distinct !DIFragment() + !divergent_lane_pc.lex.lifetime = distinct !DILifetime( + object: !divergent_lane_pc_outer.fragment, + location: !DIExpr(DIOpConstant(u64 undef), DIOpExtend(64)) + ) + ; The argObjects to `!select_lanes.expr` are: + ; {<64 x u64> starting_lane_pc_vec, u64 pc_value, u64 mask} + !select_lanes.expr = !DIExpr( + DIOpArg(0, <64 x u64>), + DIOpArg(1, u64), DIOpExtend(64, u64), + DIOpArg(2, u64), + DIOpSelect(64, u64) + ) + ; TODO: We have the issue of: how do we ensure we have a value when we need + ; it for DWARF, for example DIOpSelect will need to ensure the top element of + ; the stack is a value when evaluating the final DWARF, but this violates the + ; "context insensitive" property we want for the operations. + ; We can work around this by emitting "unoptimized" DWARF where e.g. every + ; implicit location description in the LLVM representation actually maps to an + ; implicit location description being pushed on the DWARF stack (e.g. we lower + ; `... DIOpConstant(u64 42) DIOpSelect()` to `... DW_OP_uconst 42, + ; DW_OP_stack_value, DW_OP_deref, DW_OP_select_bit_piece` instead of just `... + ; DW_OP_uconst 42, DW_OP_select_bit_piece`) + !divergent_lane_pc.lex_1_then.fragment = distinct !DIFragment() + !divergent_lane_pc.lex_1_then.lifetime = distinct !DILifetime( + object: !divergent_lane_pc.lex_1_then.fragment, + location: !select_lanes.expr, + argObjects: { + !divergent_lane_pc.lex.fragment, + !lex_1_start.label, + !save_exec.lex_1.fragment + } + ) + !divergent_lane_pc.lex_1_1_then.fragment = distinct !DIFragment() + !divergent_lane_pc.lex_1_1_then.lifetime = distinct !DILifetime( + object: !divergent_lane_pc.lex_1_1_then.fragment, + location: !select_lanes.expr, + argObjects: { + !divergent_lane_pc.lex.fragment, + !lex_1_1_start.label, + !save_exec.lex_1_1.fragment + } + ) + !divergent_lane_pc.lex_1_1_else.fragment = distinct !DIFragment() + !divergent_lane_pc.lex_1_1_else.lifetime = distinct !DILifetime( + object: !divergent_lane_pc.lex_1_1_else.fragment, + location: !select_lanes.expr, + argObjects: { + !divergent_lane_pc.lex.fragment, + !lex_1_1_end.label, + !save_exec.lex_1_1.fragment + } + ) + !divergent_lane_pc.lex_1_else.fragment = distinct !DIFragment() + !divergent_lane_pc.lex_1_else.lifetime = distinct !DILifetime( + object: !divergent_lane_pc.lex_1_else.fragment, + location: !select_lanes.expr, + argObjects: { + !divergent_lane_pc.lex.fragment, + !lex_1_end.label, + !save_exec.lex_1.fragment + } + ) + + ;; Active Lane PC + !active_lane_pc.fragment = distinct !DIFragment() + !active_lane_pc.lifetime = distinct !DILifetime( + object: !active_lane_pc.fragment, + location: !select_lanes.expr, + argObjects: { + !bounded_divergent_lane_pc.fragment, + !pc.fragment, + !exec.fragment + } + ) + + ;; Subprogram + !subprogram = !DISubprogram(..., + activeLanePC: !active_lane_pc.fragment, + retainedNodes: !{ + !pc.default.lifetime, + !exec.default.lifetime, + !divergent_lane_pc.lex_1_then.lifetime, + !divergent_lane_pc.lex_1_1_then.lifetime, + !divergent_lane_pc.lex_1_1_else.lifetime, + !divergent_lane_pc.lex_1_else.lifetime, + !active_lane_pc.lifetime, + !lex_1_start.label, + !lex_1_1_start.label, + !lex_1_1_end.label, + !lex_1_end.label + } + ) + +Fragments ``!save_exec.lex_1.fragment`` and ``!save_exec.lex_1_1.fragment`` are +created for the execution masks saved on entry to a region. Using the +``DBG_DEF`` pseudo instruction, location list entries will be created that +describe where the artificial variables are allocated at any given program +location. The compiler may allocate them to registers or spill them to memory. + +The fragments for each region use the values of the saved execution mask +artificial variables to only update the lanes that are active on entry to the +region. All other lanes retain the value of the enclosing region where they were +last active. If they were not active on entry to the subprogram, then will have +the undefined location description. + +Other structured control flow regions can be handled similarly. For example, +loops would set the divergent program location for the region at the end of the +loop. Any lanes active will be in the loop, and any lanes not active must have +exited the loop. + +An ``IF/THEN/ELSEIF/ELSEIF/...`` region can be treated as a nest of +``IF/THEN/ELSE`` regions. + +Other Ideas +=========== + +Translating To DWARF +-------------------- + +.. TODO::: + + Define algorithm for computing DWARF location descriptions and loclists. + + - Define rule for implicit pointers (``DIOpAddrof`` operation applied to a + ``DIOpReferrer`` operation): + + - Look for a compatible, existing program object. + - If not, generate an artificial one. + - This could be bubbled up to DWARF itself, to allow implicits to hold + arbitrary location descriptions, eliminating the need for the + artificial variable, and make translation simpler. + + - Define rule for ``DIFragment``: + + - If referenced by multiple ``argObjects``, then use a + ``DW_TAG_DWARF_procedure``. + - If only referenced by a ``DIVariable`` or ``DIComposite`` field, then + use ``expr`` or ``loclist`` form that specifies the location + description expression directly. + + - Define rule for computed lifetime: + + - If referenced ``DIObject`` has no bounded lifetime segments, then use + ``expr`` form. + - If referenced ``DIObject`` has bounded lifetime segments, then use + ``loclist`` form. + +Translating To PDB (CodeView) +----------------------------- + +.. TODO:: + + Define. + +Comparison With GCC +------------------- + +.. TODO:: + + Understand how this compares to what GCC is doing? + +Example Ideas +------------- + +Spilling +~~~~~~~~ + +.. TODO:: + + SSA -> stack slot + +.. code:: llvm + :number-lines: + + %x = i32 ... + call void @llvm.dbg.def(metadata !1, metadata i32 %x) + ... + call void @llvm.dbg.kill(metadata !1) + + !0 = !DILocalVariable("x") + !1 = distinct !DILifetime(object: !0, location: !DIExpr(DIOpReferrer(i32))) + +spill %x: + +.. code:: llvm + :number-lines: + + %x.addr = alloca i32, addrspace(5) + store i32* %x.addr, ... + call void @llvm.dbg.def(metadata !1, metadata i32 *%x) + ... + call void @llvm.dbg.kill(metadata !1) + + !0 = !DILocalVariable("x") + !1 = distinct !DILifetime(object: !0, location: !DIExpr(DIOpReferrer(i32 addrspace(5)*), DIOpDeref(i32))) + +.. + +.. TODO:: + + stack slot -> register + +.. + +.. TODO:: + + register -> stack slot + +Simultaneous Lifetimes In Multiple Places +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. TODO:: + + Define. + +File Scope Globals +~~~~~~~~~~~~~~~~~~ + +.. TODO:: + + Define. + +LDS Variables +~~~~~~~~~~~~~ + +.. TODO:: + + LDS variables, one variable but multiple kernels with distinct lifetimes, is + that possible in LLVM? + + Could allow the ``llvm.dbg.def`` intrinsic to refer to a global and use that + to define live ranges which live in functions and refer to storage outside of + the function. + + I would expect that LDS variables would have no ``!dbg.default`` and instead + have ``llvm.dbg.def`` in each function that can access it. The bounded + lifetime segment would have an expression that evaluates to the location of + the LDS variable in the specific subprogram. For a kernel it would likely be + an absolute address in the LDS address space. Each kernel may have a + different address. In functions that can be called from multiple kernels it + may be an expression that uses the LDS indirection variables to determine the + actual LDS address. + +Make Sure The Non-SSA MIR Form Works With def/kill Scheme +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. TODO:: + + Make sure the non-SSA MIR form works with def/kill scheme, and additionally + confirm why we do not seem to need the work upstream that is trying to move + to referring to an instruction rather than a register? See `[llvm-dev] [RFC] + DebugInfo: A different way of specifying variable locations post-isel + `__. + +Integer Fragment IDs +-------------------- + +.. TODO:: + + This was just a quick jotting-down of one idea for eliminating the need for a + distinct ``DIFragment`` to represent the identity of fragments. + +.. _local-variable-broken-into-two-scalars-1: + +Local Variable Broken Into Two Scalars +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: llvm + :number-lines: + + %x.lo = i32 ... + call void @llvm.dbg.def(metadata i32 %x.lo, metadata !4) + ... + %x.hi = i32 ... + call void @llvm.dbg.def(metadata i32 %x.hi, metadata !6) + ... + call void @llvm.dbg.kill(metadata !4) + call void @llvm.dbg.kill(metadata !6) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(var 0, var 1, composite 2)) + !3 = distinct !DILifetime(object: 0, location: !DIExpr(referrer)) + !4 = distinct !DILifetime(object: 1, location: !DIExpr(referrer)) + +Further Decomposition Of An Already SRoA’d Local Variable +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: llvm + :number-lines: + + %x.lo = i32 ... + call void @llvm.dbg.def(metadata i32 %x.lo, metadata !3) + %x.hi.lo = i16 ... + call void @llvm.dbg.def(metadata i16 %x.hi.lo, metadata !5) + %x.hi.hi = i16 ... + call void @llvm.dbg.def(metadata i16 %x.hi.hi, metadata !6) + ... + call void @llvm.dbg.kill(metadata !4) + call void @llvm.dbg.kill(metadata !8) + call void @llvm.dbg.kill(metadata !10) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(var 0, var 1, composite 2)) + !3 = distinct !DILifetime(object: 0, location: !DIExpr(referrer)) + !4 = distinct !DILifetime(object: 1, location: !DIExpr(var 2, var 3, composite 2)) + !5 = distinct !DILifetime(object: 2, location: !DIExpr(referrer)) + !6 = distinct !DILifetime(object: 3, location: !DIExpr(referrer)) + +Multiple Live Ranges For A Fragment +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: llvm + :number-lines: + + %x.lo.0 = i32 ... + call void @llvm.dbg.def(metadata i32 %x.lo, metadata !3) + ... + call void @llvm.dbg.kill(metadata !3) + %x.lo.1 = i32 ... + call void @llvm.dbg.def(metadata i32 %x.lo, metadata !4) + %x.hi.lo = i16 ... + call void @llvm.dbg.def(metadata i16 %x.hi.lo, metadata !6) + %x.hi.hi = i16 ... + call void @llvm.dbg.def(metadata i16 %x.hi.hi, metadata !7) + ... + call void @llvm.dbg.kill(metadata !4) + call void @llvm.dbg.kill(metadata !6) + call void @llvm.dbg.kill(metadata !7) + + !1 = !DILocalVariable("x", ...) + !2 = distinct !DILifetime(object: !1, location: !DIExpr(var 0, var 1, composite 2)) + !3 = distinct !DILifetime(object: 0, location: !DIExpr(referrer)) + !4 = distinct !DILifetime(object: 0, location: !DIExpr(referrer)) + !5 = distinct !DILifetime(object: 1, location: !DIExpr(var 2, var 3, composite 2)) + !6 = distinct !DILifetime(object: 2, location: !DIExpr(referrer)) + !7 = distinct !DILifetime(object: 3, location: !DIExpr(referrer)) + +References +========== + +1. `[LLVMdev] [RFC] Separating Metadata from the Value hierarchy (David + Blaikie) + `__ + +2. `[LLVMdev] [RFC] Separating Metadata from the Value hierarchy + `__ + +3. `[llvm-dev] Proposal for multi location debug info support in LLVM IR `__ + +4. `[llvm-dev] Proposal for multi location debug info support in LLVM IR `__ + +5. `Multi Location Debug Info support for LLVM `__ + +6. `D81852 [DebugInfo] Update MachineInstr interface to better support variadic DBG_VALUE instructions `__ + +7. `D70601 Disallow DIExpressions with shift operators from being fragmented `__ + +8. `D57962 [DebugInfo] PR40628: Don’t salvage load operations `__ + +9. `Bug 40628 - [DebugInfo@O2] Salvaged memory loads can observe subsequent memory writes `__ + +10. :doc:`LangRef` + + 1. :ref:`wellformed` + 2. :ref:`typesystem` + 3. :ref:`globalvars` + 4. :ref:`DICompositeType` + 5. :ref:`DILocalVariable` + 6. :ref:`DIGlobalVariable` + 7. :ref:`DICompileUnit` + 8. :ref:`DISubprogram` + 9. :ref:`DILabel` + +11. :doc:`AMDGPUDwarfExtensionsForHeterogeneousDebugging` + + 1. :ref:`amdgpu-dwarf-expressions` + 2. :ref:`amdgpu-dwarf-location-list-expressions` + 3. :ref:`amdgpu-dwarf-location-description` + 4. :ref:`amdgpu-dwarf-expression-evaluation-context` + +12. :doc:`AMDGPUUsage` + + 1. :ref:`amdgpu-dwarf-dw-at-llvm-lane-pc` diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 7780c0a6dca0a..3d2e9d290d097 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -28,6 +28,7 @@ User Guide for AMDGPU Backend AMDGPUInstructionSyntax AMDGPUInstructionNotation AMDGPUDwarfExtensionsForHeterogeneousDebugging + AMDGPULLVMExtensionsForHeterogeneousDebugging AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack Introduction @@ -1514,6 +1515,86 @@ The AMDGPU backend implements the following LLVM IR intrinsics. * 1 - Data cache. Instruction cache prefetches are unsafe on invalid address. + + llvm.amdgcn.global.load.b128 This intrinsic is supported on gfx942, gfx950. + + Signature: + + .. code-block:: llvm + + <4 x i32> @llvm.amdgcn.raw.load.store.b128( + ptr addrspace(1), ; source + metadata) ; scope - e.g. '!0' where '!0 = !{!"wavegroup"}' + + Reads the value from the source address with cache behavior + specified by the scope. + + For gfc942 and gfx950 devices, this emits a + ``global_load_dwordx4`` instruction with the appropriate + ``SC0`` and ``SC1`` bits set. + + Valid values for scope are + + ===================== ============================================================= + scope architecture name + ===================== ============================================================= + ``"wavefront"`` wave + + ``"workgroup"`` group + + ``"agent"`` device + + ``""`` (empty string) system + ===================== ============================================================= + + For semantics on gfx942, see Table 47 in section 9.1.10 + "Memory Scope and Temporal Controls" of the "AMD Instinct + MI300" Instruction Set Architecture Reference. + + For semantics on gfx950, see Table 49 in section 9.1.10 + "Memory Scope and Temporal Controls" of the CDNA4 + Instruction Set Architecture Reference. + + llvm.amdgcn.global.store.b128 This intrinsic is supported on gfx942, gfx950. + + Signature: + + .. code-block:: llvm + + void @llvm.amdgcn.global.store.b128( + ptr addrspace(1), ; destination + <4 x i32>, ; value + metadata) ; scope - e.g. '!0' where '!0 = !{!"wavegroup"}' + + Writes the value to the destination address with cache + behavior specified by the scope. + + For gfc942 and gfx950 devices, this emits a + ``global_store_dwordx4`` instruction with the appropriate + ``SC0`` and ``SC1`` bits set. + + Valid values for scope are + + ===================== ============================================================= + scope architecture name + ===================== ============================================================= + ``"wavefront"`` wave + + ``"workgroup"`` group + + ``"agent"`` device + + ``""`` (empty string) system + ===================== ============================================================= + + For semantics on gfx942, see Table 48 in section 9.1.10 + "Memory Scope and Temporal Controls" of the "AMD Instinct + MI300" Instruction Set Architecture Reference. + + For semantics on gfx950, see Table 50 in section 9.1.10 + "Memory Scope and Temporal Controls" of the CDNA4 + Instruction Set Architecture Reference. + ============================================== ========================================================== .. TODO:: @@ -2976,6 +3057,10 @@ used by tools such as debuggers and profilers. It uses features defined in :doc:`AMDGPUDwarfExtensionsForHeterogeneousDebugging` that are made available in DWARF Version 4 and DWARF Version 5 as an LLVM vendor extension. +AMDGPU uses LLVM features defined in +:doc:`AMDGPULLVMExtensionsForHeterogeneousDebugging` to implement the generation +of DWARF. + This section defines the AMDGPU target architecture specific DWARF mappings. .. _amdgpu-dwarf-register-identifier: @@ -3625,20 +3710,6 @@ temporarily updated. The location list expression created for this artificial variable is used to define the value of the ``DW_AT_LLVM_active_lane`` attribute. -``DW_AT_LLVM_augmentation`` -~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -For AMDGPU, the ``DW_AT_LLVM_augmentation`` attribute of a compilation unit -debugger information entry has the following value for the augmentation string: - -:: - - [amdgpu:v0.0] - -The "vX.Y" specifies the major X and minor Y version number of the AMDGPU -extensions used in the DWARF of the compilation unit. The version number -conforms to [SEMVER]_. - Call Frame Information ---------------------- @@ -3695,37 +3766,6 @@ Accelerated Access See DWARF Version 5 section 6.1. -Lookup By Name Section Header -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -See DWARF Version 5 section 6.1.1.4.1 and :ref:`amdgpu-dwarf-lookup-by-name`. - -For AMDGPU the lookup by name section header table: - -``augmentation_string_size`` (uword) - - Set to the length of the ``augmentation_string`` value which is always a - multiple of 4. - -``augmentation_string`` (sequence of UTF-8 characters) - - Contains the following UTF-8 string null padded to a multiple of 4 bytes: - - :: - - [amdgpu:v0.0] - - The "vX.Y" specifies the major X and minor Y version number of the AMDGPU - extensions used in the DWARF of this index. The version number conforms to - [SEMVER]_. - - .. note:: - - This is different to the DWARF Version 5 definition that requires the first - 4 characters to be the vendor ID. But this is consistent with the other - augmentation strings and does allow multiple vendor contributions. However, - backwards compatibility may be more desirable. - Lookup By Address Section Header ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/llvm/docs/CommandGuide/llvm-objdump.rst b/llvm/docs/CommandGuide/llvm-objdump.rst index aaf38f84b92e5..9a5cb7f6506ad 100644 --- a/llvm/docs/CommandGuide/llvm-objdump.rst +++ b/llvm/docs/CommandGuide/llvm-objdump.rst @@ -223,7 +223,8 @@ OPTIONS .. option:: --offloading - Display the content of the LLVM offloading sections and HIP offload bundles. + Display the content of the LLVM offloading section. + Extract Clang offload binaries into code objects. .. option:: --prefix= diff --git a/llvm/docs/CommandGuide/llvm-remarkutil.rst b/llvm/docs/CommandGuide/llvm-remarkutil.rst index af7d8eb31c018..ff27a6b595425 100644 --- a/llvm/docs/CommandGuide/llvm-remarkutil.rst +++ b/llvm/docs/CommandGuide/llvm-remarkutil.rst @@ -21,7 +21,7 @@ Subcommands * :ref:`yaml2bitstream_subcommand` - Reserialize YAML remarks to bitstream. * :ref:`instruction-count_subcommand` - Output function instruction counts. * :ref:`annotation-count_subcommand` - Output remark type count from annotation remarks. - * :ref:`size-diff_subcommand` - Compute diff in size remarks. + * :ref: `size-diff_subcommand` - Compute diff in size remarks. .. _bitstream2yaml_subcommand: @@ -268,6 +268,7 @@ two sections: Changed Function Section ^^^^^^^^^^^^^^^^^^^^^^^^ +>>>>>>> 8846b91e15d4c8d280ee727c0f69b958f9b1440b Suppose you are comparing two remark files OLD and NEW. @@ -305,6 +306,7 @@ A breakdown of the format is below: Summary Section ^^^^^^^^^^^^^^^ +>>>>>>> 8846b91e15d4c8d280ee727c0f69b958f9b1440b :program:`llvm-remarkutil size-diff` will output a high-level summary after printing all changed functions. @@ -333,6 +335,7 @@ JSON OUTPUT High-Level view ^^^^^^^^^^^^^^^ +>>>>>>> 8846b91e15d4c8d280ee727c0f69b958f9b1440b Suppose we are comparing two files, OLD and NEW. @@ -375,6 +378,7 @@ Suppose we are comparing two files, OLD and NEW. Function JSON ^^^^^^^^^^^^^ +>>>>>>> 8846b91e15d4c8d280ee727c0f69b958f9b1440b The ``InBoth``, ``OnlyInA``, and ``OnlyInB`` sections contain size information for each function in the input remark files. @@ -410,6 +414,7 @@ for each function in the input remark files. Computing Diffs From Function JSON ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +>>>>>>> 8846b91e15d4c8d280ee727c0f69b958f9b1440b Function JSON does not contain the diffs. Tools consuming JSON output from :program:`llvm-remarkutil size-diff` are responsible for computing the diffs diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 1c6823be44dcb..976749a9158ff 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -6355,21 +6355,22 @@ metadata nodes are related to debug info. DICompileUnit """"""""""""" -``DICompileUnit`` nodes represent a compile unit. The ``enums:``, -``retainedTypes:``, ``globals:``, ``imports:`` and ``macros:`` fields are tuples -containing the debug info to be emitted along with the compile unit, regardless -of code optimizations (some nodes are only emitted if there are references to -them from instructions). The ``debugInfoForProfiling:`` field is a boolean -indicating whether or not line-table discriminators are updated to provide -more-accurate debug info for profiling results. +``DICompileUnit`` nodes represent a compile unit. ``DICompileUnit`` nodes must +be ``distinct``. The ``enums:``, ``retainedTypes:``, ``globals:``, ``imports:`` +and ``macros:`` fields are tuples containing the debug info to be emitted along +with the compile unit, regardless of code optimizations (some nodes are only +emitted if there are references to them from instructions). The +``debugInfoForProfiling:`` field is a boolean indicating whether or not +line-table discriminators are updated to provide more-accurate debug info for +profiling results. .. code-block:: text - !0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", - isOptimized: true, flags: "-O2", runtimeVersion: 2, - splitDebugFilename: "abc.debug", emissionKind: FullDebug, - enums: !2, retainedTypes: !3, globals: !4, imports: !5, - macros: !6, dwoId: 0x0abcd) + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", + isOptimized: true, flags: "-O2", runtimeVersion: 2, + splitDebugFilename: "abc.debug", emissionKind: FullDebug, + enums: !2, retainedTypes: !3, globals: !4, imports: !5, + macros: !6, dwoId: 0x0abcd) Compile unit descriptors provide the root scope for objects declared in a specific compilation unit. File descriptors are defined using this scope. These @@ -16880,7 +16881,7 @@ using a less accurate calculation. '``llvm.ldexp.*``' Intrinsic -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^^^^^^^^^ Syntax: """"""" @@ -28162,7 +28163,7 @@ unspecified sequence of rounding operations. '``llvm.experimental.constrained.ldexp``' Intrinsic -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Syntax: """"""" diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst new file mode 100644 index 0000000000000..c7cab6284c82c --- /dev/null +++ b/llvm/docs/ReleaseNotes.rst @@ -0,0 +1,192 @@ +============================ +LLVM |release| Release Notes +============================ + +.. contents:: + :local: + +.. only:: PreRelease + + .. warning:: + These are in-progress notes for the upcoming LLVM |version| release. + Release notes for previous releases can be found on + `the Download Page `_. + + +Introduction +============ + +This document contains the release notes for the LLVM Compiler Infrastructure, +release |release|. Here we describe the status of LLVM, including major improvements +from the previous release, improvements in various subprojects of LLVM, and +some of the current users of the code. All LLVM releases may be downloaded +from the `LLVM releases web site `_. + +For more information about LLVM, including information about the latest +release, please check out the `main LLVM web site `_. If you +have questions or comments, the `Discourse forums +`_ is a good place to ask +them. + +Note that if you are reading this file from a Git checkout or the main +LLVM web page, this document applies to the *next* release, not the current +one. To see the release notes for a specific release, please see the `releases +page `_. + +Non-comprehensive list of changes in this release +================================================= +.. NOTE + For small 1-3 sentence descriptions, just add an entry at the end of + this list. If your description won't fit comfortably in one bullet + point (e.g. maybe you would like to give an example of the + functionality, or simply have a lot to talk about), see the `NOTE` below + for adding a new subsection. + +* ... + +Update on required toolchains to build LLVM +------------------------------------------- + +* The minimum Python version has been raised from 3.6 to 3.8 across all of LLVM. + This enables the use of many new Python features, aligning more closely with + modern Python best practices, and improves CI maintainability + See `#78828 `_ for more info. + +Changes to the LLVM IR +---------------------- + +* The ``x86_mmx`` IR type has been removed. It will be translated to + the standard vector type ``<1 x i64>`` in bitcode upgrade. + +Changes to LLVM infrastructure +------------------------------ + +Changes to building LLVM +------------------------ + +Changes to TableGen +------------------- + +Changes to Interprocedural Optimizations +---------------------------------------- + +Changes to the AArch64 Backend +------------------------------ + +* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill + the required alignment space with a sequence of `0x0` bytes (the requested + fill value) rather than NOPs. + +Changes to the AMDGPU Backend +----------------------------- + +Changes to the ARM Backend +-------------------------- + +* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill + the required alignment space with a sequence of `0x0` bytes (the requested + fill value) rather than NOPs. + +Changes to the AVR Backend +-------------------------- + +Changes to the DirectX Backend +------------------------------ + +Changes to the Hexagon Backend +------------------------------ + +Changes to the LoongArch Backend +-------------------------------- + +Changes to the MIPS Backend +--------------------------- + +Changes to the PowerPC Backend +------------------------------ + +Changes to the RISC-V Backend +----------------------------- + +* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill + the required alignment space with a sequence of `0x0` bytes (the requested + fill value) rather than NOPs. + +Changes to the WebAssembly Backend +---------------------------------- + +Changes to the Windows Target +----------------------------- + +Changes to the X86 Backend +-------------------------- + +* `.balign N, 0x90`, `.p2align N, 0x90`, and `.align N, 0x90` in code sections + now fill the required alignment space with repeating `0x90` bytes, rather than + using optimised NOP filling. Optimised NOP filling fills the space with NOP + instructions of various widths, not just those that use the `0x90` byte + encoding. To use optimised NOP filling in a code section, leave off the + "fillval" argument, i.e. `.balign N`, `.p2align N` or `.align N` respectively. + +* Due to the removal of the ``x86_mmx`` IR type, functions with + ``x86_mmx`` arguments or return values will use a different, + incompatible, calling convention ABI. Such functions are not + generally seen in the wild (Clang never generates them!), so this is + not expected to result in real-world compatibility problems. + +Changes to the OCaml bindings +----------------------------- + +Changes to the Python bindings +------------------------------ + +Changes to the C API +-------------------- + +* The following symbols are deleted due to the removal of the ``x86_mmx`` IR type: + + * ``LLVMX86_MMXTypeKind`` + * ``LLVMX86MMXTypeInContext`` + * ``LLVMX86MMXType`` + +Changes to the CodeGen infrastructure +------------------------------------- + +Changes to the Metadata Info +--------------------------------- + +Changes to the Debug Info +--------------------------------- + +Changes to the LLVM tools +--------------------------------- + +Changes to LLDB +--------------------------------- + +Changes to BOLT +--------------------------------- + +Changes to Sanitizers +--------------------- + +Other Changes +------------- + +External Open Source Projects Using LLVM 19 +=========================================== + +* A project... + +Additional Information +====================== + +A wide variety of additional information is available on the `LLVM web page +`_, in particular in the `documentation +`_ section. The web page also contains versions of the +API documentation which is up-to-date with the Git version of the source +code. You can access versions of these documents specific to this release by +going into the ``llvm/docs/`` directory in the LLVM tree. + +If you have any questions or comments about LLVM, please feel free to contact +us via the `Discourse forums `_. diff --git a/llvm/docs/UserGuides.rst b/llvm/docs/UserGuides.rst index 0551c8b60a62d..eb11a88fd277b 100644 --- a/llvm/docs/UserGuides.rst +++ b/llvm/docs/UserGuides.rst @@ -1,3 +1,290 @@ +User Guides +=========== + +NOTE: If you are a user who is only interested in using an LLVM-based compiler, +you should look into `Clang `_ instead. The +documentation here is intended for users who have a need to work with the +intermediate LLVM representation. + +.. contents:: + :local: + +.. toctree:: + :hidden: + + AArch64SME + AddingConstrainedIntrinsics + AdvancedBuilds + AliasAnalysis + AMDGPUUsage + Benchmarking + BigEndianNEON + BuildingADistribution + CFIVerify + CMake + CMakePrimer + CodeGenerator + CodeOfConduct + CommandLine + CompileCudaWithLLVM + CoverageMappingFormat + CycleTerminology + DebuggingJITedCode + DirectXUsage + Docker + FatLTO + ExtendingLLVM + GitHub + GoldPlugin + GlobalISel/MIRPatterns + HowToBuildOnARM + HowToBuildWithPGO + HowToBuildWindowsItaniumPrograms + HowToCrossCompileBuiltinsOnArm + HowToCrossCompileLLVM + HowToUpdateDebugInfo + InstCombineContributorGuide + InstrProfileFormat + InstrRefDebugInfo + LinkTimeOptimization + LoopTerminology + MarkdownQuickstartTemplate + MemorySSA + MergeFunctions + MCJITDesignAndImplementation + MisExpect + ORCv2 + OpaquePointers + JITLink + NewPassManager + NVPTXUsage + Passes + ReportingGuide + ResponseGuide + Remarks + RemoveDIsDebugInfo + RISCVUsage + SourceLevelDebugging + SPIRVUsage + StackSafetyAnalysis + SupportLibrary + TableGen/index + TableGenFundamentals + Vectorizers + WritingAnLLVMPass + WritingAnLLVMNewPMPass + WritingAnLLVMBackend + yaml2obj + +Clang +----- + +:doc:`HowToBuildOnARM` + Notes on building and testing LLVM/Clang on ARM. + +:doc:`HowToBuildWithPGO` + Notes on building LLVM/Clang with PGO. + +:doc:`HowToCrossCompileLLVM` + Notes on cross-building and testing LLVM/Clang. + +`How to build the C, C++, ObjC, and ObjC++ front end`__ + Instructions for building the clang front-end from source. + + .. __: https://clang.llvm.org/get_started.html + +:doc:`CoverageMappingFormat` + This describes the format and encoding used for LLVM’s code coverage mapping. + +:doc:`CFIVerify` + A description of the verification tool for Control Flow Integrity. + +LLVM Builds and Distributions +----------------------------- + +:doc:`BuildingADistribution` + A best-practices guide for using LLVM's CMake build system to package and + distribute LLVM-based tools. + +:doc:`CMake` + An addendum to the main Getting Started guide for those using the `CMake + build system `_. + +:doc:`Docker` + A reference for using Dockerfiles provided with LLVM. + +:doc:`Support Library ` + This document describes the LLVM Support Library (``lib/Support``) and + how to keep LLVM source code portable. + +:doc:`AdvancedBuilds` + This document describes more advanced build configurations. + +Optimizations +------------- + +:doc:`WritingAnLLVMNewPMPass` + Information on how to write LLVM transformations under the new pass + manager. + +:doc:`WritingAnLLVMPass` + Information on how to write LLVM transformations and analyses under the + legacy pass manager. + +:doc:`Passes` + A list of optimizations and analyses implemented in LLVM. + +:doc:`StackSafetyAnalysis` + This document describes the design of the stack safety analysis of local + variables. + +:doc:`MergeFunctions` + Describes functions merging optimization. + +:doc:`AliasAnalysis` + Information on how to write a new alias analysis implementation or how to + use existing analyses. + +:doc:`MemorySSA` + Information about the MemorySSA utility in LLVM, as well as how to use it. + +:doc:`LoopTerminology` + A document describing Loops and associated terms as used in LLVM. + +:doc:`CycleTerminology` + A document describing cycles as a generalization of loops. + +:doc:`Vectorizers` + This document describes the current status of vectorization in LLVM. + +:doc:`LinkTimeOptimization` + This document describes the interface between LLVM intermodular optimizer + and the linker and its design + +:doc:`GoldPlugin` + How to build your programs with link-time optimization on Linux. + +:doc:`Remarks` + A reference on the implementation of remarks in LLVM. + +:doc:`Source Level Debugging with LLVM ` + This document describes the design and philosophy behind the LLVM + source-level debugger. + +:doc:`How to Update Debug Info ` + This document specifies how to correctly update debug info in various kinds + of code transformations. + +:doc:`InstrRefDebugInfo` + This document explains how LLVM uses value tracking, or instruction + referencing, to determine variable locations for debug info in the final + stages of compilation. + +:doc:`RemoveDIsDebugInfo` + This is a migration guide describing how to move from debug info using + intrinsics such as dbg.value to using the non-instruction DbgRecord object. + +:doc:`InstrProfileFormat` + This document explains two binary formats of instrumentation-based profiles. + +:doc:`InstCombineContributorGuide` + This document specifies guidelines for contributions for InstCombine and + related passes. + +Code Generation +--------------- + +:doc:`WritingAnLLVMBackend` + Information on how to write LLVM backends for machine targets. + +:doc:`CodeGenerator` + The design and implementation of the LLVM code generator. Useful if you are + working on retargetting LLVM to a new architecture, designing a new codegen + pass, or enhancing existing components. + +:doc:`TableGen ` + Describes the TableGen tool, which is used heavily by the LLVM code + generator. + +========== +GlobalISel +========== + +:doc:`MIRPatterns ` + Describes the design of MIR Patterns and how to use them. + +=== +JIT +=== + +:doc:`MCJITDesignAndImplementation` + Describes the inner workings of MCJIT execution engine. + +:doc:`ORCv2` + Describes the design and implementation of the ORC APIs, including some + usage examples, and a guide for users transitioning from ORCv1 to ORCv2. + +:doc:`JITLink` + Describes the design and APIs for the JITLink library, ORC's new JIT + linker. + +:doc:`DebuggingJITedCode` + How to debug JITed code with GDB. + +Additional Topics +----------------- + +:doc:`CommandLine` + Provides information on using the command line parsing library. + +:doc:`ExtendingLLVM` + Look here to see how to add instructions and intrinsics to LLVM. + +:doc:`AddingConstrainedIntrinsics` + Gives the steps necessary when adding a new constrained math intrinsic + to LLVM. + +:doc:`HowToBuildWindowsItaniumPrograms` + Notes on assembling a Windows Itanium environment. + +:doc:`HowToCrossCompileBuiltinsOnArm` + Notes on cross-building and testing the compiler-rt builtins for Arm. + +:doc:`BigEndianNEON` + LLVM's support for generating NEON instructions on big endian ARM targets is + somewhat nonintuitive. This document explains the implementation and rationale. + +:doc:`AArch64SME` + LLVM's support for AArch64 SME ACLE and ABI. + +:doc:`CompileCudaWithLLVM` + LLVM support for CUDA. + +:doc:`NVPTXUsage` + This document describes using the NVPTX backend to compile GPU kernels. + +:doc:`AMDGPUUsage` + This document describes using the AMDGPU backend to compile GPU kernels. + +:doc:`AMDGPUDwarfExtensionsForHeterogeneousDebugging` + This document describes DWARF extensions to support heterogeneous debugging + for targets such as the AMDGPU backend. + +:doc:`AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack` + This document describes a DWARF extension to allow location descriptions on + the DWARF expression stack. It is part of + :doc:`AMDGPUDwarfExtensionsForHeterogeneousDebugging`. + +:doc:`SPIRVUsage` + This document describes using the SPIR-V target to compile GPU kernels. + +:doc:`DirectXUsage` + This document describes using the DirectX target to compile GPU code for the + DirectX runtime. + +:doc:`RISCVUsage` + This document describes using the RISCV-V target. + User Guides =========== diff --git a/llvm/include/llvm-c/DebugInfo.h b/llvm/include/llvm-c/DebugInfo.h index 70da3a61a46d8..c02cedfcc698b 100644 --- a/llvm/include/llvm-c/DebugInfo.h +++ b/llvm/include/llvm-c/DebugInfo.h @@ -147,6 +147,8 @@ typedef enum { LLVMDWARFSourceLanguageBORLAND_Delphi } LLVMDWARFSourceLanguage; +typedef unsigned LLVMDWARFMemorySpace; + /** * The amount of debug information to emit. */ @@ -827,13 +829,14 @@ LLVM_C_ABI LLVMMetadataRef LLVMDIBuilderCreateBasicType( * \param SizeInBits Size. * \param AlignInBits Alignment. (optional, pass 0 to ignore) * \param AddressSpace DWARF address space. (optional, pass 0 to ignore) + * \param MemorySpace DWARF memory space (optional, pass 0 for none). * \param Name Pointer type name. (optional) * \param NameLen Length of pointer type name. (optional) */ LLVM_C_ABI LLVMMetadataRef LLVMDIBuilderCreatePointerType( LLVMDIBuilderRef Builder, LLVMMetadataRef PointeeTy, uint64_t SizeInBits, - uint32_t AlignInBits, unsigned AddressSpace, const char *Name, - size_t NameLen); + uint32_t AlignInBits, unsigned AddressSpace, LLVMDWARFMemorySpace MS, + const char *Name, size_t NameLen); /** * Create debugging information entry for a struct. @@ -982,9 +985,12 @@ LLVM_C_ABI LLVMMetadataRef LLVMDIBuilderCreateQualifiedType( * \param Builder The DIBuilder. * \param Tag Tag identifying type, * \param Type Base Type. + * \param AddressSpace DWARF address space. (optional, pass 0 to ignore) + * \param MemorySpace DWARF memory space (optional, pass 0 for none). */ LLVM_C_ABI LLVMMetadataRef LLVMDIBuilderCreateReferenceType( - LLVMDIBuilderRef Builder, unsigned Tag, LLVMMetadataRef Type); + LLVMDIBuilderRef Builder, unsigned Tag, LLVMMetadataRef Type, + unsigned AddressSpace, LLVMDWARFMemorySpace MemorySpace); /** * Create C++11 nullptr type. @@ -1235,7 +1241,8 @@ LLVM_C_ABI LLVMMetadataRef LLVMDIBuilderCreateGlobalVariableExpression( LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, const char *Linkage, size_t LinkLen, LLVMMetadataRef File, unsigned LineNo, LLVMMetadataRef Ty, LLVMBool LocalToUnit, - LLVMMetadataRef Expr, LLVMMetadataRef Decl, uint32_t AlignInBits); + LLVMMetadataRef Expr, LLVMMetadataRef Decl, LLVMDWARFMemorySpace MS, + uint32_t AlignInBits); /** * Get the dwarf::Tag of a DINode @@ -1433,7 +1440,8 @@ LLVM_C_ABI LLVMDbgRecordRef LLVMDIBuilderInsertDbgValueRecordAtEnd( LLVM_C_ABI LLVMMetadataRef LLVMDIBuilderCreateAutoVariable( LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned LineNo, LLVMMetadataRef Ty, - LLVMBool AlwaysPreserve, LLVMDIFlags Flags, uint32_t AlignInBits); + LLVMBool AlwaysPreserve, LLVMDIFlags Flags, LLVMDWARFMemorySpace MS, + uint32_t AlignInBits); /** * Create a new descriptor for a function parameter variable. diff --git a/llvm/include/llvm/ADT/Hashing.h b/llvm/include/llvm/ADT/Hashing.h index 41a730e24a6b1..9ed00331c6722 100644 --- a/llvm/include/llvm/ADT/Hashing.h +++ b/llvm/include/llvm/ADT/Hashing.h @@ -57,6 +57,7 @@ #include #include #include +#include namespace llvm { template struct DenseMapInfo; @@ -125,9 +126,15 @@ hash_code hash_value(const std::tuple &arg); template hash_code hash_value(const std::basic_string &arg); -/// Compute a hash_code for a standard string. +/// Compute a hash_code for an optional. template hash_code hash_value(const std::optional &arg); +/// Compute a hash_code for a variant. +template hash_code hash_value(const std::variant &arg); + +void set_fixed_execution_hash_seed(uint64_t fixed_value); + + // All of the implementation details of actually computing the various hash // code values are held within this namespace. These routines are included in // the header file mainly to allow inlining and constant propagation. @@ -653,6 +660,12 @@ template hash_code hash_value(const std::optional &arg) { return arg ? hash_combine(true, *arg) : hash_value(false); } +template hash_code hash_value(const std::variant &arg) { + return std::visit( + [&](auto &&Alt) { return hash_combine(arg.index(), hash_value(Alt)); }, + arg); +} + template <> struct DenseMapInfo { static inline hash_code getEmptyKey() { return hash_code(-1); } static inline hash_code getTombstoneKey() { return hash_code(-2); } diff --git a/llvm/include/llvm/ADT/IntrusiveVariant.h b/llvm/include/llvm/ADT/IntrusiveVariant.h new file mode 100644 index 0000000000000..9c6998e7df143 --- /dev/null +++ b/llvm/include/llvm/ADT/IntrusiveVariant.h @@ -0,0 +1,455 @@ +//===- IntrusiveVariant.h - Compact type safe union -------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file provides IntrusiveVariant, a class template modeled in the spirit +// of std::variant, but leveraging the "common initial sequence" rule for union +// members to store the runtime tag at the beginning of the IntrusiveVariant's +// alternative types, allowing for it to be packed more efficiently into bits +// that would otherwise be used for padding. +// +// However, this requires several restrictions be placed on valid alternative +// types. All alternative types of an IntrusiveVariant must: +// +// * Be standard-layout. This implies (among other things): +// * All non-static data members must have the same access control. +// * All non-static data members must be declared in only one class in the +// inheritence hierarchy. +// * No virtual methods. +// * Begin their class definition by invoking the +// DECLARE_INTRUSIVE_ALTERNATIVE macro. This declares a member named +// `IntrusiveVariantTagMember` which must not be referenced outside of the +// implementation of IntrusiveVariant, and declares some `friend` types to +// make the tag accessible to the implementation. +// +// Additionally, some features were omitted that are present in the C++17 +// std::variant to keep the code simpler: +// +// * All alternative types must be trivially-destructible. +// * All copy/move constructors and assignment operators for the variant are +// disabled if any type is not trivially-constructible and/or +// trivially-copyable, respectively. +// * All alternative types must be unique, and cannot be referred to by index. +// * No equivalent to std::monostate. An instantiation must have at least +// IntrusiveVariant::MinNumberOfAlternatives alternatives. +// +// If a use case for the above materializes these can always be added +// retroactively. +// +// Example: +// +// class AltInt { +// DECLARE_INTRUSIVE_ALTERNATIVE +// int Int; +// +// public: +// AltInt() : Int(0) {} +// AltInt(int Int) : Int(Int) {} +// int getInt() const { return Int; } +// void setInt(int Int) { this->Int = Int; } +// }; +// +// class AltDouble { +// DECLARE_INTRUSIVE_ALTERNATIVE +// double Double; +// +// public: +// AltDouble(double Double) : Double(Double) {} +// double getDouble() const { return Double; } +// void setDouble(double Double) { this->Double = Double; } +// }; +// +// class AltComplexInt { +// DECLARE_INTRUSIVE_ALTERNATIVE +// int Real; +// int Imag; +// +// public: +// AltComplexInt(int Real, int Imag) : Real(Real), Imag(Imag) {} +// int getReal() const { return Real; } +// void setReal(int Real) { this->Real = Real; } +// int getImag() const { return Imag; } +// void setImag(int Imag) { this->Imag = Imag; } +// }; +// +// TEST(VariantTest, HeaderExample) { +// using MyVariant = IntrusiveVariant; +// +// MyVariant DefaultConstructedVariant; +// ASSERT_TRUE(DefaultConstructedVariant.holdsAlternative()); +// ASSERT_EQ(DefaultConstructedVariant.get().getInt(), 0); +// MyVariant Variant{in_place_type, 4, 2}; +// ASSERT_TRUE(Variant.holdsAlternative()); +// int NonSense = visit( +// makeVisitor( +// [](AltInt &AI) { return AI.getInt(); }, +// [](AltDouble &AD) { return static_cast(AD.getDouble()); }, +// [](AltComplexInt &ACI) { return ACI.getReal() + ACI.getImag(); }), +// Variant); +// ASSERT_EQ(NonSense, 6); +// Variant.emplace(2.0); +// ASSERT_TRUE(Variant.holdsAlternative()); +// Variant.get().setDouble(3.0); +// AltDouble AD = Variant.get(); +// double D = AD.getDouble(); +// ASSERT_EQ(D, 3.0); +// Variant.emplace(4, 5); +// ASSERT_EQ(Variant.get().getReal(), 4); +// ASSERT_EQ(Variant.get().getImag(), 5); +// } +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ADT_INTRUSIVEVARIANT_H +#define LLVM_ADT_INTRUSIVEVARIANT_H + +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/VariantTraits.h" +#include "llvm/Support/ErrorHandling.h" +#include +#include +#include + +namespace llvm { + +template class IntrusiveVariant; + +/// Helper to get the number of alternative types of a (possibly cv-qualified) +/// IntrusiveVariant type as a constexpr. See std::variant_size. +template +struct IntrusiveVariantSize : IntrusiveVariantSize> {}; +template +struct IntrusiveVariantSize> + : std::integral_constant {}; + +/// Simple value type which must be the first member of all alternative types +/// of an IntrusiveVariant. See DECLARE_INTRUSIVE_ALTERNATIVE. +/// +/// The internal implementation assumes this is layout-compatible with the +/// "common initial sequence" of all alternative types contained in the private +/// union of the IntrusiveVariant. +struct IntrusiveVariantTag { + uint8_t Index = std::numeric_limits::max(); + IntrusiveVariantTag() {} + IntrusiveVariantTag(uint8_t Index) : Index(Index) {} +}; + +/// A helper macro to add the declarations needed to use a type as an +/// alternative for IntrusiveVariant. Must be the first declaration of the +/// class. +#define DECLARE_INTRUSIVE_ALTERNATIVE \ + ::llvm::IntrusiveVariantTag IntrusiveVariantTagMember; \ + template friend class ::llvm::IntrusiveVariant; \ + template \ + friend union ::llvm::detail::UnionImpl; + +namespace detail { +// This struct is used to access the intrusive tag of the alternative types. +// +// All such types must be have an initial sequence which is layout-compatible +// with this struct or the access causes undefined behavior. +struct CommonInitialSequenceT { + IntrusiveVariantTag Tag; +}; + +// The inner implementation of the "type safe union". Members are only +// accessible directly via an Index, so IntrusiveVariant must use indexOf to +// convert a pair of T and Ts... into an index. +// +// Effectively implemented as a "linked list" of recursively defined union +// templates. This is the recursive portion of the definition. +// +// We use in_place_index_t here both to disambiguate the constructor and to make +// defining the overload set for getMember more natural. +template union UnionImpl { + using TailT = UnionImpl; + HeadT Head; + TailT Tail; + HeadT &getMember(in_place_index_t) { return Head; } + const HeadT &getMember(in_place_index_t) const { return Head; } + template decltype(auto) getMember(in_place_index_t) { + return Tail.getMember(in_place_index); + } + template decltype(auto) getMember(in_place_index_t) const { + return Tail.getMember(in_place_index); + } + template + UnionImpl(in_place_index_t, ArgTs &&...Args) { + new (&Head) HeadT(std::forward(Args)...); + Head.IntrusiveVariantTagMember.Index = Index; + } + template + UnionImpl(in_place_index_t, ArgTs &&...Args) { + new (&Tail) TailT(in_place_index_t{}, std::forward(Args)...); + } + UnionImpl(const UnionImpl &) = default; + UnionImpl(UnionImpl &&) = default; + UnionImpl &operator=(const UnionImpl &) = default; + UnionImpl &operator=(UnionImpl &&) = default; + // This is safe, assuming the member types are all trivially destructible. + ~UnionImpl() = default; +}; +// The base case for the above, i.e. when the tail pack is empty. This is the +// "(cons head nil)" of the linked list. +template union UnionImpl { + HeadT Head; + HeadT &getMember(in_place_index_t) { return Head; } + const HeadT &getMember(in_place_index_t) const { return Head; } + template + UnionImpl(in_place_index_t, ArgTs &&...Args) { + new (&Head) HeadT(std::forward(Args)...); + Head.IntrusiveVariantTagMember.Index = Index; + } + UnionImpl(const UnionImpl &) = default; + UnionImpl(UnionImpl &&) = default; + UnionImpl &operator=(const UnionImpl &) = default; + UnionImpl &operator=(UnionImpl &&) = default; + // This is safe, assuming the member types are all trivially destructible. + ~UnionImpl() = default; +}; +} // end namespace detail + +template struct VariantTraits> { + static constexpr size_t size() { return sizeof...(Ts); } + static constexpr size_t index(const IntrusiveVariant &Variant) { + return Variant.index(); + } + template > + static constexpr decltype(auto) get(VariantT &&Variant) { + return std::forward(Variant) + .template get>(); + } +}; + +/// A class template modeled in the spirit of std::variant, but leveraging the +/// "common initial sequence" rule for union members to store the runtime tag +/// at the beginning of each variant alternative itself, allowing for it to be +/// packed more efficiently into bits that would otherwise be used for padding. +template class IntrusiveVariant { +public: + /// The static minimum number of alternative types supported for an + /// instantiation of IntrusiveVariant. + static constexpr size_t MinNumberOfAlternatives = 1; + +private: + static_assert(llvm::conjunction...>::value, + "IntrusiveVariant alternatives must be standard-layout."); + static_assert( + llvm::conjunction...>::value, + "IntrusiveVariant alternatives must be trivially-destructible."); + template static constexpr bool tagIsFirstMember() { + constexpr bool IsFirstMember[] = { + !offsetof(Us, IntrusiveVariantTagMember)...}; + for (size_t I = 0; I < sizeof...(Us); ++I) + if (!IsFirstMember[I]) + return false; + return true; + } + /* + static_assert( + tagIsFirstMember() && + llvm::conjunction< + std::is_same...>::value, + "IntrusiveVariant alternatives' class definition must begin with " + "DECLARE_INTRUSIVE_ALTERNATIVE"); + */ + static_assert( + TypesAreDistinct::value, + "Repeated alternative types in IntrusiveVariant are not allowed."); + + // Alias for the UnionImpl of this IntrusiveVariant. + using UnionT = detail::UnionImpl<0, Ts...>; + // Helper to get the in_place_index_t for T in Ts... + template + using InPlaceIndexT = in_place_index_t::value>; + // Helper to check if a type is in the set Ts... + template using IsAlternativeType = llvm::is_one_of; + + // The only data member of IntrusiveVariant, meaning the variant is the same + // size and has the same alignment requirements as the union of all of its + // alternative types. + union { + detail::CommonInitialSequenceT CommonInitialSequence; + UnionT Union; + }; + + // Convenience methods to get the union member for an alternative type T. + template T &getAlt() { + return Union.getMember(InPlaceIndexT{}); + } + template const T &getAlt() const { + return Union.getMember(InPlaceIndexT{}); + } + +public: + /// A default constructed IntrusiveVariant holds a default constructed value + /// of its first alternative. Only enabled if the first alternative has a + /// default constructor. + template >::value, + typename std::enable_if_t = 0> + constexpr IntrusiveVariant() : Union(in_place_index_t<0>{}) {} + /// The forwarding constructor requires a disambiguation tag + /// in_place_type_t, and creates an IntrusiveVariant holding the + /// alternative T constructed with the constructor arguments Args... + template ::value, int> = 0, + typename... ArgTs> + explicit constexpr IntrusiveVariant(in_place_type_t, ArgTs &&...Args) + : Union(InPlaceIndexT{}, std::forward(Args)...) {} + /// Converting constructor from alternative types. + template ::value, int> = 0> + constexpr IntrusiveVariant(T &&Alt) + : Union(InPlaceIndexT{}, std::forward(Alt)) {} + IntrusiveVariant(const IntrusiveVariant &) = default; + IntrusiveVariant(IntrusiveVariant &&) = default; + ~IntrusiveVariant() = default; + IntrusiveVariant &operator=(const IntrusiveVariant &) = default; + IntrusiveVariant &operator=(IntrusiveVariant &&) = default; + /// Replaces the held value with a new value of alternative type T in-place, + /// constructing the new value with constructor arguments Args... + /// + /// Returns the newly constructed alternative type value. + template T &emplace(ArgTs &&...Args) { + new (&Union) UnionT(InPlaceIndexT{}, std::forward(Args)...); + return Union.getMember(InPlaceIndexT{}); + } + /// Returns the index of the alternative type held by this variant. + size_t index() const { return CommonInitialSequence.Tag.Index; } + /// Check if this variant holds a value of the given alternative type T. + template constexpr bool holdsAlternative() const { + return index() == FirstIndexOfType(); + } + /// Reads the value of alternative type T. + /// + /// Behavior undefined if this does not hold a value of alternative type T. + template constexpr T &get() { + assert(holdsAlternative()); + return getAlt(); + } + /// Reads the value of alternative type T. + /// + /// Behavior undefined if this does not hold a value of alternative type T. + template constexpr const T &get() const { + assert(holdsAlternative()); + return getAlt(); + } + /// Obtains a pointer to the value of alternative type T if this holds a + /// value of alternative type T. Otherwise, returns nullptr. + template constexpr T *getIf() { + if (holdsAlternative()) + return &getAlt(); + return nullptr; + } + /// Obtains a pointer to the value of alternative type T if this holds a + /// value of alternative type T. Otherwise, returns nullptr. + template constexpr const T *getIf() const { + if (holdsAlternative()) + return &getAlt(); + return nullptr; + } + + /// Equality operator. + /// + /// The alternative types held by LHS and RHS are T and U, respectively; then: + /// + /// If T != U, returns false. + /// Otherwise, returns LHS.get() == RHS.get(). + friend constexpr bool operator==(const IntrusiveVariant &LHS, + const IntrusiveVariant &RHS) { + if (LHS.index() != RHS.index()) + return false; + return visitSameAlternative(std::equal_to<>{}, LHS, RHS); + } + + /// Inequality operator. + /// + /// The alternative types held by LHS and RHS are T and U, respectively; then: + /// + /// If T != U, returns true. + /// Otherwise, returns LHS.get() != RHS.get(). + friend constexpr bool operator!=(const IntrusiveVariant &LHS, + const IntrusiveVariant &RHS) { + if (LHS.index() != RHS.index()) + return true; + return visitSameAlternative(std::not_equal_to<>{}, LHS, RHS); + } + + /// Less-than operator. + /// + /// The alternative types held by LHS and RHS are T and U, respectively; then: + /// + /// If T precedes U in Ts..., returns true. + /// If U precedes T in Ts..., returns false. + /// Otherwise, returns LHS.get() < RHS.get(). + friend constexpr bool operator<(const IntrusiveVariant &LHS, + const IntrusiveVariant &RHS) { + if (LHS.index() < RHS.index()) + return true; + if (LHS.index() > RHS.index()) + return false; + return visitSameAlternative(std::less<>{}, LHS, RHS); + } + + /// Greater-than operator. + /// + /// The alternative types held by LHS and RHS are T and U, respectively; then: + /// + /// If T precedes U in Ts..., returns false. + /// If U precedes T in Ts..., returns true. + /// Otherwise, returns LHS.get() > RHS.get(). + friend constexpr bool operator>(const IntrusiveVariant &LHS, + const IntrusiveVariant &RHS) { + if (LHS.index() < RHS.index()) + return false; + if (LHS.index() > RHS.index()) + return true; + return visitSameAlternative(std::greater<>{}, LHS, RHS); + } + + /// Less-equal operator. + /// + /// The alternative types held by LHS and RHS are T and U, respectively; then: + /// + /// If T precedes U in Ts..., returns true. + /// If U precedes T in Ts..., returns false. + /// Otherwise, returns LHS.get() <= RHS.get(). + friend constexpr bool operator<=(const IntrusiveVariant &LHS, + const IntrusiveVariant &RHS) { + if (LHS.index() < RHS.index()) + return true; + if (LHS.index() > RHS.index()) + return false; + return visitSameAlternative(std::less_equal<>{}, LHS, RHS); + } + + /// Greater-equal operator. + /// + /// The alternative types held by LHS and RHS are T and U, respectively; then: + /// + /// If T precedes U in Ts..., returns false. + /// If U precedes T in Ts..., returns true. + /// Otherwise, returns LHS.get() >= RHS.get(). + friend constexpr bool operator>=(const IntrusiveVariant &LHS, + const IntrusiveVariant &RHS) { + if (LHS.index() < RHS.index()) + return false; + if (LHS.index() > RHS.index()) + return true; + return visitSameAlternative(std::greater_equal<>{}, LHS, RHS); + } + + /// Enabled if all alternative types overload hash_value. + friend hash_code hash_value(const IntrusiveVariant &IV) { + return visit( + [&](auto &&Alt) { return hash_combine(IV.index(), hash_value(Alt)); }, + IV); + } +}; + +} // end namespace llvm + +#endif // LLVM_ADT_INTRUSIVEVARIANT_H diff --git a/llvm/include/llvm/ADT/STLExtras.h b/llvm/include/llvm/ADT/STLExtras.h index a9841c6651b72..ddf551c719d28 100644 --- a/llvm/include/llvm/ADT/STLExtras.h +++ b/llvm/include/llvm/ADT/STLExtras.h @@ -2338,7 +2338,8 @@ template struct enumerator_result { /// Returns the value at index `I`. This case covers references to the /// iteratees. template > - friend decltype(auto) get(const enumerator_result &Result) { + friend decltype(auto) + get(const enumerator_result &Result) { // Note: This is a separate function from the other `get`, instead of an // `if constexpr` case, to work around an MSVC 19.31.31XXX compiler // (Visual Studio 2022 17.1) return type deduction bug. @@ -2474,7 +2475,9 @@ auto enumerate(FirstRange &&First, RestRanges &&...Rest) { #ifndef NDEBUG // Note: Create an array instead of an initializer list to work around an // Apple clang 14 compiler bug. - size_t sizes[] = {range_size(First), range_size(Rest)...}; + size_t sizes[] = { + static_cast(std::distance(adl_begin(First), adl_end(First))), + static_cast(std::distance(adl_begin(Rest), adl_end(Rest)))...}; assert(all_equal(sizes) && "Ranges have different length"); #endif } diff --git a/llvm/include/llvm/ADT/STLForwardCompat.h b/llvm/include/llvm/ADT/STLForwardCompat.h index e02694f043fbb..1889b90c14126 100644 --- a/llvm/include/llvm/ADT/STLForwardCompat.h +++ b/llvm/include/llvm/ADT/STLForwardCompat.h @@ -17,6 +17,7 @@ #ifndef LLVM_ADT_STLFORWARDCOMPAT_H #define LLVM_ADT_STLFORWARDCOMPAT_H +#include #include #include #include diff --git a/llvm/include/llvm/ADT/VariantTraits.h b/llvm/include/llvm/ADT/VariantTraits.h new file mode 100644 index 0000000000000..899681e64f21e --- /dev/null +++ b/llvm/include/llvm/ADT/VariantTraits.h @@ -0,0 +1,285 @@ +//===- VariantTraits.h - Common interfaces for variant-like types --C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains common interfaces for variant-like types. +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/STLExtras.h" + +#ifndef LLVM_ADT_VARIANTTRAITS_H +#define LLVM_ADT_VARIANTTRAITS_H + +namespace llvm { + +/// Trait type which can be specialized over std::variant-like types to provide +/// the minimum interface needed to share the implementation of llvm::visit and +/// llvm::visitSameAlternative. +template struct VariantTraits { + // // Returns the number of alternative types of VariantT. + // static constexpr size_t size(); + // + // // Returns the index of the current alternative type of Variant. + // static constexpr size_t index(const VariantT &Variant); + // + // // Gets the alternative type at Index. + // template + // static constexpr decltype(auto) get(VariantT &&Variant); +}; + +namespace variant_traits_detail { + +template using Traits = struct VariantTraits>; + +template struct HasTraits { + using Absent = char; + using Present = long; + template static Absent size(...); + template static Present size(SameType *); + template static Absent index(...); + template + static Present + index(SameType &), &U::index> *); + template static Absent get(...); + template + static Present get(SameType &&), &U::get> *); + + static bool const value = // NOLINT(readability-identifier-naming) + sizeof(size>(nullptr)) == sizeof(Present) && + sizeof(index>(nullptr)) == sizeof(Present) && + sizeof(get>(nullptr) == sizeof(Present)); +}; + +template +struct AreSame : conjunction...> {}; + +// FIXME: Peeling off the first ThunkT in this definition is only necessary to +// work around an MSVC compiler issue, where it complains that std::is_same is +// not provided enough template arguments. Verify what version of MSVC no +// longer requires this workaround so this can be simplified. +template {}, int> = 0> +static constexpr auto makeThunkArray(HeadThunkT &&HeadThunk, + TailThunkTs &&...TailThunks) { + return make_array(std::forward(HeadThunk), + std::forward(TailThunks)...); +} + +template +static constexpr decltype(auto) +thunkForSameAlternative(VisitorT &&Visitor, VariantTs &&...Variants) { + return std::forward(Visitor)(Traits::template get( + std::forward(Variants))...); +} + +template +static constexpr auto makeThunkForSameAlternative() { + return thunkForSameAlternative; +} + +template +static constexpr auto +visitSameAlternativeImpl(size_t Index, std::index_sequence, + VisitorT &&Visitor, HeadVariantT &&HeadVariant, + TailVariantTs &&...TailVariants) { + constexpr auto Thunks = makeThunkArray( + makeThunkForSameAlternative()...); + return Thunks[Index](std::forward(Visitor), + std::forward(HeadVariant), + std::forward(TailVariants)...); +} + +template struct Thunk { + template + inline static constexpr decltype(auto) thunk(VisitorT &&Visitor, + VariantTs &&...Variants) { + return std::forward(Visitor)( + Traits::template get( + std::forward(Variants))...); + } + + template + inline static constexpr R thunkR(VisitorT &&Visitor, + VariantTs &&...Variants) { + return std::forward(Visitor)( + Traits::template get( + std::forward(Variants))...); + } +}; + +template +static constexpr auto makeThunkForSequence(std::index_sequence) { + return Thunk::template thunk; +} + +template +static constexpr auto makeThunkForSequenceR(std::index_sequence) { + return Thunk::template thunkR; +} + +template +static constexpr auto +accumulateCartesianProductThunks(std::index_sequence) { + return makeThunkForSequence( + std::index_sequence{}); +} + +template +static constexpr auto +accumulateCartesianProductThunksR(std::index_sequence) { + return makeThunkForSequenceR( + std::index_sequence{}); +} + +template +static constexpr auto +accumulateCartesianProductThunks(std::index_sequence, + std::index_sequence, + TailSequenceTs... Tail) { + return makeThunkArray( + accumulateCartesianProductThunks( + std::index_sequence{}, + Tail...)...); +} + +template +static constexpr auto +accumulateCartesianProductThunksR(std::index_sequence, + std::index_sequence, + TailSequenceTs... Tail) { + return makeThunkArray( + accumulateCartesianProductThunksR( + std::index_sequence{}, + Tail...)...); +} + +template +static constexpr auto makeThunkMatrix() { + return accumulateCartesianProductThunks( + std::index_sequence<>{}, + std::make_index_sequence::size()>{}...); +} + +template +static constexpr auto makeThunkMatrixR() { + return accumulateCartesianProductThunksR( + std::index_sequence<>{}, + std::make_index_sequence::size()>{}...); +} + +template +static constexpr const ThunkT &indexThunkMatrix(const ThunkT &Thunk) { + return Thunk; +} + +template +static constexpr auto &&indexThunkMatrix(const ThunkMatrixT &ThunkMatrix, + size_t HeadIndex, + TailIndexTs... TailIndexes) { + return indexThunkMatrix(ThunkMatrix[HeadIndex], TailIndexes...); +} + +} // namespace variant_traits_detail + +/// Invokes the provided Visitor using overload resolution based on the +/// dynamic alternative type held in each Variant. See std::variant. +/// +/// The return type is effectively +/// decltype(Visitor(Variants.get()...)). This must be a +/// valid expression of the same type and value category for every combination +/// of alternative types of the variant types. +template < + typename VisitorT, typename... VariantTs, + typename std::enable_if_t< + conjunction...>::value, + int> = 0> +constexpr decltype(auto) visit(VisitorT &&Visitor, VariantTs &&...Variants) { + constexpr auto ThunkMatrix = + variant_traits_detail::makeThunkMatrix(); + const auto &Thunk = variant_traits_detail::indexThunkMatrix( + ThunkMatrix, variant_traits_detail::Traits::index( + std::forward(Variants))...); + return Thunk(std::forward(Visitor), + std::forward(Variants)...); +} + +/// Invokes the provided Visitor using overload resolution based on the +/// dynamic alternative type held in each Variant. See std::variant. +/// +/// The return type is effectively +/// decltype(Visitor(Variants.get()...)), implicity converted +/// to R. +template < + typename R, typename VisitorT, typename... VariantTs, + typename std::enable_if_t< + conjunction...>::value, + int> = 0> +constexpr R visit(VisitorT &&Visitor, VariantTs &&...Variants) { + constexpr auto ThunkMatrix = + variant_traits_detail::makeThunkMatrixR(); + const auto &Thunk = variant_traits_detail::indexThunkMatrix( + ThunkMatrix, variant_traits_detail::Traits::index( + std::forward(Variants))...); + return Thunk(std::forward(Visitor), + std::forward(Variants)...); +} + +/// Invokes the provided Visitor using overload resolution based on the dynamic +/// alternative type held in each Variant, assuming the variants are all of the +/// same type and hold the same dynamic alternative type. +/// +/// \warning llvm::visit must be used instead when there is no guarantee that +/// all variants currently hold the same alternative type. However, when such a +/// guarantee can be made llvm::visitSameAlternative may reduce code bloat, +/// especially for debug builds. +/// +/// The return type is effectively +/// decltype(Visitor(Variants.get()...)). This must be a valid +/// expression of the same type and value category for every alternative type +/// of the variant type. +template < + typename VisitorT, typename HeadVariantT, typename... TailVariantTs, + typename std::enable_if_t< + conjunction, + variant_traits_detail::HasTraits...>::value, + int> = 0> +static constexpr decltype(auto) +visitSameAlternative(VisitorT &&Visitor, HeadVariantT &&HeadVariant, + TailVariantTs &&...TailVariants) { + static_assert( + conjunction, + remove_cvref_t>...>::value, + "all variant arguments to visitSameAlternative must " + "be of the same type"); + using Traits = variant_traits_detail::Traits; +#ifdef EXPENSIVE_CHECKS + size_t Index = Traits::index(std::forward(HeadVariant)); + for (auto &&V : {std::forward(TailVariants)...}) + assert(Traits::index(V) == Index && + "all variant arguments to visitSameAlternative must have " + "the same index"); +#endif + return variant_traits_detail::visitSameAlternativeImpl( + Traits::index(std::forward(HeadVariant)), + std::make_index_sequence{}, + std::forward(Visitor), std::forward(HeadVariant), + std::forward(TailVariants)...); +} + +} // namespace llvm + +#endif // LLVM_ADT_VARIANTTRAITS_H diff --git a/llvm/include/llvm/Analysis/TargetLibraryInfo.h b/llvm/include/llvm/Analysis/TargetLibraryInfo.h index 3f39b4787eb11..f783a82d800c0 100644 --- a/llvm/include/llvm/Analysis/TargetLibraryInfo.h +++ b/llvm/include/llvm/Analysis/TargetLibraryInfo.h @@ -125,8 +125,8 @@ class TargetLibraryInfoImpl { /// addVectorizableFunctionsFromVecLib for filling up the tables of /// vectorizable functions. enum VectorLibrary { - NoLibrary, // Don't use any vector library. - Accelerate, // Use Accelerate framework. + NoLibrary, // Don't use any vector library. + Accelerate, // Use Accelerate framework. DarwinLibSystemM, // Use Darwin's libsystem_m. LIBMVEC, // GLIBC Vector Math library. MASSV, // IBM MASS vector library. diff --git a/llvm/include/llvm/AsmParser/LLParser.h b/llvm/include/llvm/AsmParser/LLParser.h index 9eb31d7e0a451..1e44b177131b5 100644 --- a/llvm/include/llvm/AsmParser/LLParser.h +++ b/llvm/include/llvm/AsmParser/LLParser.h @@ -463,6 +463,7 @@ namespace llvm { Loc = Lex.getLoc(); return parseType(Result, AllowVoid); } + bool parseFirstClassType(Type *&Result); bool parseAnonStructType(Type *&Result, bool Packed); bool parseStructBody(SmallVectorImpl &Body); bool parseStructDefinition(SMLoc TypeLoc, StringRef Name, @@ -604,6 +605,8 @@ namespace llvm { bool parseSpecializedMDNode(MDNode *&N, bool IsDistinct = false); bool parseDIExpressionBody(MDNode *&Result, bool IsDistinct); + bool parseDIOpExpression(MDNode *&Result); + #define HANDLE_SPECIALIZED_MDNODE_LEAF(CLASS) \ bool parse##CLASS(MDNode *&Result, bool IsDistinct); #include "llvm/IR/Metadata.def" diff --git a/llvm/include/llvm/AsmParser/LLToken.h b/llvm/include/llvm/AsmParser/LLToken.h index 6de99fe182ad9..bed9f10ce70ca 100644 --- a/llvm/include/llvm/AsmParser/LLToken.h +++ b/llvm/include/llvm/AsmParser/LLToken.h @@ -500,6 +500,7 @@ enum Kind { DwarfLang, // DW_LANG_foo DwarfSourceLangName, // DW_LNAME_foo DwarfCC, // DW_CC_foo + DwarfMSpaceLLVM, // DW_MSPACE_LLVM_foo EmissionKind, // lineTablesOnly NameTableKind, // GNU FixedPointKind, // Fixed point @@ -508,6 +509,7 @@ enum Kind { DISPFlag, // DISPFlagFoo DwarfMacinfo, // DW_MACINFO_foo ChecksumKind, // CSK_foo + DIOp, // DIOpFoo DbgRecordType, // dbg_foo DwarfEnumKind, // DW_APPLE_ENUM_KIND_foo diff --git a/llvm/include/llvm/BinaryFormat/Dwarf.def b/llvm/include/llvm/BinaryFormat/Dwarf.def index fbf22cc6f760b..3dcde332c37cf 100644 --- a/llvm/include/llvm/BinaryFormat/Dwarf.def +++ b/llvm/include/llvm/BinaryFormat/Dwarf.def @@ -26,6 +26,7 @@ defined HANDLE_DWARF_SECTION || defined HANDLE_DW_IDX || \ defined HANDLE_DW_END || defined HANDLE_DW_SECT || \ defined HANDLE_DW_APPLE_ENUM_KIND || \ + defined HANDLE_DW_MSPACE || \ ( defined HANDLE_DW_ASPACE && defined HANDLE_DW_ASPACE_PRED) ) #error "Missing macro definition of HANDLE_DW*" #endif @@ -152,6 +153,10 @@ #define HANDLE_DW_APPLE_ENUM_KIND(ID, NAME) #endif +#ifndef HANDLE_DW_MSPACE +#define HANDLE_DW_MSPACE(ID, NAME) +#endif + #ifndef HANDLE_DW_ASPACE #define HANDLE_DW_ASPACE(ID, NAME) #endif @@ -648,6 +653,13 @@ HANDLE_DW_AT(0x3e11, LLVM_lanes, 0, LLVM) HANDLE_DW_AT(0x3e12, LLVM_lane_pc, 0, LLVM) HANDLE_DW_AT(0x3e13, LLVM_vector_size, 0, LLVM) +// https://www.llvm.org/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.html#a-7-15-memory-space-encodings +HANDLE_DW_MSPACE(0x0, none) +HANDLE_DW_MSPACE(0x1, global) +HANDLE_DW_MSPACE(0x2, constant) +HANDLE_DW_MSPACE(0x3, group) +HANDLE_DW_MSPACE(0x4, private) + // https://llvm.org/docs/AMDGPUUsage.html#address-space-identifier HANDLE_DW_ASPACE(0x0, none) HANDLE_DW_ASPACE_PRED(AMDGPU::DWARFAS::GENERIC, AMDGPU_generic, SELECT_AMDGPU) @@ -1425,5 +1437,6 @@ HANDLE_DW_SECT(8, RNGLISTS) #undef HANDLE_DW_END #undef HANDLE_DW_SECT #undef HANDLE_DW_APPLE_ENUM_KIND +#undef HANDLE_DW_MSPACE #undef HANDLE_DW_ASPACE #undef HANDLE_DW_ASPACE_PRED diff --git a/llvm/include/llvm/BinaryFormat/Dwarf.h b/llvm/include/llvm/BinaryFormat/Dwarf.h index 211c0269c1f29..90868ecba6008 100644 --- a/llvm/include/llvm/BinaryFormat/Dwarf.h +++ b/llvm/include/llvm/BinaryFormat/Dwarf.h @@ -149,6 +149,7 @@ enum LocationAtom { DW_OP_LLVM_arg = 0x1005, ///< Only used in LLVM metadata. DW_OP_LLVM_extract_bits_sext = 0x1006, ///< Only used in LLVM metadata. DW_OP_LLVM_extract_bits_zext = 0x1007, ///< Only used in LLVM metadata. + DW_OP_LLVM_poisoned = 0x1008, ///< Only used in LLVM metadata. }; enum LlvmUserLocationAtom { @@ -765,6 +766,13 @@ enum CallingConvention { DW_CC_hi_user = 0xff }; +enum MemorySpace { +#define HANDLE_DW_MSPACE(ID, NAME) DW_MSPACE_LLVM_##NAME = ID, +#include "llvm/BinaryFormat/Dwarf.def" + DW_MSPACE_LLVM_lo_user = 0x8000, + DW_MSPACE_LLVM_hi_user = 0xffff +}; + enum AddressSpace { #define HANDLE_DW_ASPACE(ID, NAME) DW_ASPACE_LLVM_##NAME = ID, #define HANDLE_DW_ASPACE_PRED(ID, NAME, PRED) DW_ASPACE_LLVM_##NAME = ID, @@ -1026,6 +1034,7 @@ LLVM_ABI StringRef IndexString(unsigned Idx); LLVM_ABI StringRef FormatString(DwarfFormat Format); LLVM_ABI StringRef FormatString(bool IsDWARF64); LLVM_ABI StringRef RLEString(unsigned RLE); +LLVM_ABI StringRef MemorySpaceString(unsigned MS); LLVM_ABI StringRef AddressSpaceString(unsigned AS, const llvm::Triple &TT); /// @} @@ -1046,8 +1055,10 @@ LLVM_ABI unsigned getSubOperationEncoding(unsigned OpEncoding, LLVM_ABI unsigned getVirtuality(StringRef VirtualityString); LLVM_ABI unsigned getEnumKind(StringRef EnumKindString); LLVM_ABI unsigned getLanguage(StringRef LanguageString); +LLVM_ABI unsigned getMemorySpace(StringRef LanguageString); LLVM_ABI unsigned getSourceLanguageName(StringRef SourceLanguageNameString); LLVM_ABI unsigned getCallingConvention(StringRef LanguageString); +LLVM_ABI unsigned getMemorySpace(StringRef LanguageString); LLVM_ABI unsigned getAttributeEncoding(StringRef EncodingString); LLVM_ABI unsigned getMacinfo(StringRef MacinfoString); LLVM_ABI unsigned getMacro(StringRef MacroString); diff --git a/llvm/include/llvm/Bitcode/LLVMBitCodes.h b/llvm/include/llvm/Bitcode/LLVMBitCodes.h index 464f475098ec5..e9c75edaf641e 100644 --- a/llvm/include/llvm/Bitcode/LLVMBitCodes.h +++ b/llvm/include/llvm/Bitcode/LLVMBitCodes.h @@ -390,8 +390,11 @@ enum MetadataCodes { METADATA_GENERIC_SUBRANGE = 45, // [distinct, count, lo, up, stride] METADATA_ARG_LIST = 46, // [n x [type num, value num]] METADATA_ASSIGN_ID = 47, // [distinct, ...] - METADATA_SUBRANGE_TYPE = 48, // [distinct, ...] - METADATA_FIXED_POINT_TYPE = 49, // [distinct, ...] + METADATA_EXPR = 48, // [distinct, ...] + METADATA_FRAGMENT = 49, // [] + METADATA_LIFETIME = 50, // [obj, loc, n x args] + METADATA_SUBRANGE_TYPE = 51, // [distinct, ...] + METADATA_FIXED_POINT_TYPE = 52, // [distinct, ...] }; // The constants block (CONSTANTS_BLOCK_ID) describes emission for each @@ -801,6 +804,13 @@ enum AttributeKindCodes { ATTR_KIND_CAPTURES = 102, ATTR_KIND_DEAD_ON_RETURN = 103, ATTR_KIND_SANITIZE_ALLOC_TOKEN = 104, + + // TODO: Get rid of this. + // There really shouldn't be incompatible bitcode changes specific to AMD + // branches because that is prone to break compiler developer's workflows. In + // the meantime, try to reduce the blast radius by using bitcode values that + // are extremely unlikely to be used upstream. + ATTR_KIND_SANITIZED_PADDED_GLOBAL = 9999, }; enum ComdatSelectionKindCodes { diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h index 9ace2555b4b62..02581d31145fc 100644 --- a/llvm/include/llvm/CodeGen/AsmPrinter.h +++ b/llvm/include/llvm/CodeGen/AsmPrinter.h @@ -662,6 +662,8 @@ class LLVM_ABI AsmPrinter : public MachineFunctionPass { /// instructions in verbose mode. virtual void emitImplicitDef(const MachineInstr *MI) const; + bool emitDebugComment(const MachineInstr *MI); + /// getSubtargetInfo() cannot be used where this is needed because we don't /// have a MachineFunction when we're lowering a GlobalIFunc, and /// getSubtargetInfo requires one. Override the implementation in targets diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h index 3a2509345b776..f21923827039c 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h @@ -246,6 +246,12 @@ enum { /// - SizeInBits(ULEB128) - The size of the pointer value in bits. GIM_CheckPointerToAny, + /// Check the machine type of the specified operand + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - MachineOperandType(ULEB128) - Expected type + GIM_CheckMachineOperandType, + /// Check the register bank for the specified operand /// - InsnID(ULEB128) - Instruction ID /// - OpIdx(ULEB128) - Operand index diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h index 591cf9c97ae49..d49513a022e15 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h @@ -771,6 +771,15 @@ bool GIMatchTableExecutor::executeMatchTable( break; } + case GIM_CheckMachineOperandType: { + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint64_t MOTy = readULEB(); + MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); + if (MO.getType() != MOTy) + return false; + break; + } case GIM_RecordNamedOperand: { uint64_t InsnID = readULEB(); uint64_t OpIdx = readULEB(); diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h index ef783f276b7d4..57befa3006d46 100644 --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -643,6 +643,8 @@ class LLVM_ABI MachineFunction { void substituteDebugValuesForInst(const MachineInstr &Old, MachineInstr &New, unsigned MaxOperand = UINT_MAX); + using SalvageCopySSAResult = std::pair; + /// Find the underlying defining instruction / operand for a COPY instruction /// while in SSA form. Copies do not actually define values -- they move them /// between registers. Labelling a COPY-like instruction with an instruction @@ -654,11 +656,11 @@ class LLVM_ABI MachineFunction { /// \p MI The copy-like instruction to salvage. /// \p DbgPHICache A container to cache already-solved COPYs. /// \returns An instruction/operand pair identifying the defining value. - DebugInstrOperandPair + SalvageCopySSAResult salvageCopySSA(MachineInstr &MI, - DenseMap &DbgPHICache); + DenseMap &DbgPHICache); - DebugInstrOperandPair salvageCopySSAImpl(MachineInstr &MI); + SalvageCopySSAResult salvageCopySSAImpl(MachineInstr &MI); /// Finalise any partially emitted debug instructions. These are DBG_INSTR_REF /// instructions where we only knew the vreg of the value they use, not the @@ -1234,6 +1236,10 @@ class LLVM_ABI MachineFunction { [[nodiscard]] unsigned addFrameInst(const MCCFIInstruction &Inst); + /// Replace all references to register \param From with register \param To in + /// frame instructions. Note that .cfi_escape instructions will be left as-is. + void replaceFrameInstRegister(Register From, Register To); + /// Returns a reference to a list of symbols immediately following calls to /// _setjmp in the function. Used to construct the longjmp target table used /// by Windows Control Flow Guard. diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h b/llvm/include/llvm/CodeGen/TargetFrameLowering.h index 75696faf114cc..d11813cec278d 100644 --- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h +++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h @@ -23,6 +23,7 @@ namespace llvm { class BitVector; class CalleeSavedInfo; + class DIExpression; class MachineFunction; class RegScavenger; @@ -343,6 +344,11 @@ class LLVM_ABI TargetFrameLowering { virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const; + virtual DIExpression *lowerFIArgToFPArg(const MachineFunction &MF, + const DIExpression *Expr, + uint64_t ArgIndex, + StackOffset Offset) const; + /// Same as \c getFrameIndexReference, except that the stack pointer (as /// opposed to the frame pointer) will be the preferred value for \p /// FrameReg. This is generally used for emitting statepoint or EH tables that diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index f031353422e40..54b3f6a04d241 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -1136,6 +1136,14 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo { prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const; + /// If the register corresponding to DwarfReg is a vector register that holds + /// a per-thread value in each lane, return the size in bytes of the lane. + /// Otherwise return nullopt. + virtual std::optional getDwarfRegLaneSize(int64_t DwarfReg, + bool isEH) const { + return std::nullopt; + } + virtual int64_t getDwarfRegNumForVirtReg(Register RegNum, bool isEH) const { llvm_unreachable("getDwarfRegNumForVirtReg does not exist on this target"); } diff --git a/llvm/include/llvm/Config/llvm-config.h.cmake b/llvm/include/llvm/Config/llvm-config.h.cmake index 6488d6c01b5c6..978be87064dc0 100644 --- a/llvm/include/llvm/Config/llvm-config.h.cmake +++ b/llvm/include/llvm/Config/llvm-config.h.cmake @@ -14,6 +14,11 @@ #ifndef LLVM_CONFIG_H #define LLVM_CONFIG_H +/* The number of commits in the linear history from the + * start of the universe up to the latest llvm main commit + * that has been merged */ +#define LLVM_MAIN_REVISION 556851 + /* Define if LLVM_ENABLE_DUMP is enabled */ #cmakedefine LLVM_ENABLE_DUMP diff --git a/llvm/include/llvm/DWARFLinker/Utils.h b/llvm/include/llvm/DWARFLinker/Utils.h index 8bf5ea1025a1e..a648814bec1a3 100644 --- a/llvm/include/llvm/DWARFLinker/Utils.h +++ b/llvm/include/llvm/DWARFLinker/Utils.h @@ -39,6 +39,7 @@ inline Error finiteLoop(function_ref()> Iteration, /// Make a best effort to guess the /// Xcode.app/Contents/Developer path from an SDK path. inline StringRef guessDeveloperDir(StringRef SysRoot) { + SmallString<128> Result; // Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk auto it = sys::path::rbegin(SysRoot); auto end = sys::path::rend(SysRoot); diff --git a/llvm/include/llvm/DebugInfo/DIContext.h b/llvm/include/llvm/DebugInfo/DIContext.h index e7e87bbfebf38..233e37d570c9e 100644 --- a/llvm/include/llvm/DebugInfo/DIContext.h +++ b/llvm/include/llvm/DebugInfo/DIContext.h @@ -213,6 +213,7 @@ struct DIDumpOptions { std::string JsonErrSummaryFile; std::function GetNameForDWARFReg; + std::function GetNameForDWARFAddressSpace; /// Return default option set for printing a single DIE without children. static DIDumpOptions getForSingleDIE() { diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPConstants.h b/llvm/include/llvm/Frontend/OpenMP/OMPConstants.h index 7bec7e0c6736d..c1500e00bddd0 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPConstants.h +++ b/llvm/include/llvm/Frontend/OpenMP/OMPConstants.h @@ -239,9 +239,11 @@ enum class OpenMPOffloadMappingFlags : uint64_t { // dynamic. // This is an OpenMP extension for the sake of OpenACC support. OMP_MAP_OMPX_HOLD = 0x2000, + // Mapping is for a descriptor (a.k.a. dope vector) + OMP_MAP_DESCRIPTOR = 0x4000, // Attach pointer and pointee, after processing all other maps. // Applicable to map-entering directives. Does not change ref-count. - OMP_MAP_ATTACH = 0x4000, + OMP_MAP_ATTACH = 0x8000, /// Signal that the runtime library should use args as an array of /// descriptor_dim pointers and use args_size as dims. Used when we have /// non-contiguous list items in target update directive @@ -285,6 +287,36 @@ enum class RTLDependenceKindTy { DepOmpAllMem = 0x80, }; +namespace xteam_red { +// Upper limit on CU multiplier for computing number of teams. Assuming a +// maximum of 32 wave slots per CU. +constexpr int16_t MaxCUMultiplier = 32; + +// Maximum number of threads allowed per CU. +constexpr int16_t MaxThreadsPerCU = 2048; + +// Desired number of wavefronts per CU. Aiming for 50% occupancy. +constexpr int16_t DesiredWavesPerCU = 16; + +// Default block size, potentially different from other kernel types. +constexpr int16_t DefaultBlockSize = 512; + +// Max block size, same as other kernel types, but maintaining it here +// so that it is accessible for all targets. +constexpr int16_t MaxBlockSize = 1024; + +// Compute CUMultiplier = (Max threads per CU) / (Block size) +static inline uint32_t getXteamRedCUMultiplier(uint32_t BlockSize) { + uint32_t CUMultiplier = + BlockSize > 0 ? llvm::omp::xteam_red::MaxThreadsPerCU / BlockSize + : llvm::omp::xteam_red::MaxCUMultiplier; + if (CUMultiplier > llvm::omp::xteam_red::MaxCUMultiplier) + CUMultiplier = llvm::omp::xteam_red::MaxCUMultiplier; + return CUMultiplier; +} + +} // end namespace xteam_red + /// A type of worksharing loop construct enum class WorksharingLoopType { // Worksharing `for`-loop @@ -295,6 +327,37 @@ enum class WorksharingLoopType { DistributeForStaticLoop }; +static inline uint32_t getBlockSizeAsPowerOfTwo(uint32_t BlockSize) { + uint32_t Tmp = BlockSize; + do { + BlockSize = Tmp; + Tmp = BlockSize & (BlockSize - 1); + } while (Tmp != 0); + return BlockSize; +} + +/// AMD GPU specs for computing kernel occupancy +namespace amdgpu_arch { +// Local memory size +constexpr unsigned LocalMemorySize = 32768; +// SIMD unit per CU +constexpr unsigned SIMDPerCU = 4; +// Max waves each SIMD supports +constexpr unsigned MaxWavesPerEU8 = 8; +constexpr unsigned MaxWavesPerEU10 = 10; +// Number of VGPR for each thread +constexpr unsigned VGPRNumPerThread = 512; +// flat work group size +constexpr unsigned FlatWorkgroupSize = 1024; +// Max number of workgroup per CU +constexpr unsigned MaxWorkgroupNumPerCU = 16; +// Occupancy computation conditions by SGPRs +constexpr unsigned SGPRCountOccupancy10 = 80; +constexpr unsigned SGPRCountOccupancy9 = 88; +constexpr unsigned SGPRCountOccupancy8 = 100; + +} // end namespace amdgpu_arch + } // end namespace omp } // end namespace llvm diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h b/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h index c41b4d1e9844c..5a8673bcfddf8 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h +++ b/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h @@ -24,7 +24,9 @@ enum OMPTgtExecModeFlags : unsigned char { OMP_TGT_EXEC_MODE_SPMD = 1 << 1, OMP_TGT_EXEC_MODE_GENERIC_SPMD = OMP_TGT_EXEC_MODE_GENERIC | OMP_TGT_EXEC_MODE_SPMD, - OMP_TGT_EXEC_MODE_SPMD_NO_LOOP = 1 << 2 | OMP_TGT_EXEC_MODE_SPMD + OMP_TGT_EXEC_MODE_SPMD_NO_LOOP = 1 << 2 | OMP_TGT_EXEC_MODE_SPMD, + OMP_TGT_EXEC_MODE_SPMD_BIG_JUMP_LOOP = OMP_TGT_EXEC_MODE_SPMD_NO_LOOP | 1, + OMP_TGT_EXEC_MODE_XTEAM_RED = 1 << 3 }; } // end namespace omp diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h index 5331cb5abdc6f..fb8563402528c 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h +++ b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h @@ -125,6 +125,7 @@ class OpenMPIRBuilderConfig { /// First separator used between the initial two parts of a name. std::optional FirstSeparator; + /// Separator used between all of the rest consecutive parts of s name. std::optional Separator; @@ -2130,6 +2131,17 @@ class OpenMPIRBuilder { LLVM_ABI FunctionCallee getOrCreateRuntimeFunction(Module &M, omp::RuntimeFunction FnID); + /// Return the function declaration for atomic CAS runtime function + /// with name \p FunName. Used for unsigned types as basic .def machinery + /// does not support unsigned integer types in the API. + /// \param FunName Name of the function to get or create + /// \param RetType Type of function return parameter + /// \param AddrTy Type of atomic target pointer + /// \param UpdateTy Type of atomic update expression + LLVM_ABI FunctionCallee unsignedGetOrCreateAtomicCASRuntimeFunction( + Module &M, const StringRef &FunName, Type *RetType, Type *AddrTy, + Type *UpdateTy); + LLVM_ABI Function *getOrCreateRuntimeFunctionPtr(omp::RuntimeFunction FnID); /// Return the (LLVM-IR) string describing the source location \p LocStr. @@ -2440,7 +2452,7 @@ class OpenMPIRBuilder { /// Arguments passed to the runtime library TargetDataRTArgs RTArgs; /// The number of iterations - Value *NumIterations = nullptr; + Value *TripCount = nullptr; /// The number of teams. ArrayRef NumTeams; /// The number of threads. @@ -2453,13 +2465,12 @@ class OpenMPIRBuilder { // Constructors for TargetKernelArgs. TargetKernelArgs() {} TargetKernelArgs(unsigned NumTargetItems, TargetDataRTArgs RTArgs, - Value *NumIterations, ArrayRef NumTeams, + Value *TripCount, ArrayRef NumTeams, ArrayRef NumThreads, Value *DynCGGroupMem, bool HasNoWait) - : NumTargetItems(NumTargetItems), RTArgs(RTArgs), - NumIterations(NumIterations), NumTeams(NumTeams), - NumThreads(NumThreads), DynCGGroupMem(DynCGGroupMem), - HasNoWait(HasNoWait) {} + : NumTargetItems(NumTargetItems), RTArgs(RTArgs), TripCount(TripCount), + NumTeams(NumTeams), NumThreads(NumThreads), + DynCGGroupMem(DynCGGroupMem), HasNoWait(HasNoWait) {} }; /// Create the kernel args vector used by emitTargetKernel. This function @@ -2990,7 +3001,7 @@ class OpenMPIRBuilder { /// The `omp target` interface /// /// For more information about the usage of this interface, - /// \see openmp/libomptarget/deviceRTLs/common/include/target.h + /// \see offload/deviceRTLs/common/include/target.h /// ///{ @@ -3264,6 +3275,10 @@ class OpenMPIRBuilder { bool IVSigned, bool IsGPUDistribute); + /// Return the __kmpc_distribute_static_init_multi_device* function. + FunctionCallee createMDDistributeForStaticInitFunction(unsigned IVSize, + bool IVSigned); + /// Returns __kmpc_dispatch_init_* runtime function for the specified /// size \a IVSize and sign \a IVSigned. LLVM_ABI FunctionCallee createDispatchInitFunction(unsigned IVSize, diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def index 46b3d53a4b408..74ed2b32a5baa 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def +++ b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def @@ -34,11 +34,18 @@ __OMP_TYPE(Int8) __OMP_TYPE(Int16) __OMP_TYPE(Int32) __OMP_TYPE(Int64) +__OMP_PTR_TYPE(DoublePtr) +__OMP_PTR_TYPE(FloatPtr) +__OMP_PTR_TYPE(HalfPtr) +__OMP_PTR_TYPE(BFloatPtr) __OMP_PTR_TYPE(Int8Ptr) __OMP_PTR_TYPE(Int16Ptr) __OMP_PTR_TYPE(Int32Ptr) __OMP_PTR_TYPE(Int64Ptr) __OMP_TYPE(Double) +__OMP_TYPE(Float) +__OMP_TYPE(Half) +__OMP_TYPE(BFloat) OMP_TYPE(SizeTy, M.getDataLayout().getIntPtrType(Ctx)) OMP_TYPE(Int63, Type::getIntNTy(Ctx, 63)) @@ -209,6 +216,9 @@ __OMP_RTL(__kmpc_cancel, false, Int32, IdentPtr, Int32, Int32) __OMP_RTL(__kmpc_cancel_barrier, false, Int32, IdentPtr, Int32) __OMP_RTL(__kmpc_error, false, Void, IdentPtr, Int32, Int8Ptr) __OMP_RTL(__kmpc_flush, false, Void, IdentPtr) +__OMP_RTL(__kmpc_flush_acquire, false, Void, IdentPtr) +__OMP_RTL(__kmpc_flush_release, false, Void, IdentPtr) +__OMP_RTL(__kmpc_flush_acqrel, false, Void, IdentPtr) __OMP_RTL(__kmpc_global_thread_num, false, Int32, IdentPtr) __OMP_RTL(__kmpc_get_hardware_thread_id_in_block, false, Int32, ) __OMP_RTL(__kmpc_fork_call, true, Void, IdentPtr, Int32, ParallelTaskPtr) @@ -301,6 +311,14 @@ __OMP_RTL(__kmpc_distribute_static_init_8, false, Void, IdentPtr, Int32, Int32, Int32Ptr, Int64Ptr, Int64Ptr, Int64Ptr, Int64, Int64) __OMP_RTL(__kmpc_distribute_static_init_8u, false, Void, IdentPtr, Int32, Int32, Int32Ptr, Int64Ptr, Int64Ptr, Int64Ptr, Int64, Int64) +__OMP_RTL(__kmpc_distribute_static_init_multi_device_4, false, Void, IdentPtr, Int32, Int32, + Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, Int32, Int32) +__OMP_RTL(__kmpc_distribute_static_init_multi_device_4u, false, Void, IdentPtr, Int32, Int32, + Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, Int32, Int32) +__OMP_RTL(__kmpc_distribute_static_init_multi_device_8, false, Void, IdentPtr, Int32, Int32, + Int32Ptr, Int64Ptr, Int64Ptr, Int64Ptr, Int64Ptr, Int64Ptr, Int64, Int64) +__OMP_RTL(__kmpc_distribute_static_init_multi_device_8u, false, Void, IdentPtr, Int32, Int32, + Int32Ptr, Int64Ptr, Int64Ptr, Int64Ptr, Int64Ptr, Int64Ptr, Int64, Int64) __OMP_RTL(__kmpc_distribute_static_fini, false, Void, IdentPtr, Int32) __OMP_RTL(__kmpc_dist_dispatch_init_4, false, Void, IdentPtr, Int32, Int32, Int32Ptr, Int32, Int32, Int32, Int32) @@ -467,12 +485,23 @@ __OMP_RTL(__tgt_push_mapper_component, false, Void, VoidPtr, VoidPtr, VoidPtr, __OMP_RTL(__kmpc_task_allow_completion_event, false, VoidPtr, IdentPtr, /* Int */ Int32, /* kmp_task_t */ VoidPtr) +__OMP_RTL(omp_target_alloc, false, VoidPtr, Int64, Int32) +__OMP_RTL(omp_target_free, false, Void, VoidPtr, Int32) +__OMP_RTL(omp_target_memcpy, false, Int32, VoidPtr, VoidPtr, Int64, Int64, Int64, Int32, Int32) +__OMP_RTL(ompx_get_team_procs, false, Int32, Int32) +__OMP_RTL(omp_get_initial_device, false, Int32,) +__OMP_RTL(omp_get_default_device, false, Int32,) + /// OpenMP Device runtime functions __OMP_RTL(__kmpc_target_init, false, Int32, KernelEnvironmentPtr, KernelLaunchEnvironmentPtr) __OMP_RTL(__kmpc_target_deinit, false, Void,) +__OMP_RTL(__kmpc_specialized_kernel_init, false, Void,) __OMP_RTL(__kmpc_kernel_prepare_parallel, false, Void, VoidPtr) __OMP_RTL(__kmpc_parallel_51, false, Void, IdentPtr, Int32, Int32, Int32, Int32, FuncPtrTy, FuncPtrTy, VoidPtrPtr, SizeTy) +__OMP_RTL(__kmpc_parallel_spmd, false, Void, IdentPtr, Int32, VoidPtr, VoidPtrPtr, SizeTy) +__OMP_RTL(__kmpc_parallel_60, false, Void, IdentPtr, Int32, Int32, Int32, Int32, + VoidPtr, VoidPtr, VoidPtrPtr, SizeTy, Int32, Int32, Int8Ptr) __OMP_RTL(__kmpc_for_static_loop_4, false, Void, IdentPtr, VoidPtr, VoidPtr, Int32, Int32, Int32, Int8) __OMP_RTL(__kmpc_for_static_loop_4u, false, Void, IdentPtr, VoidPtr, VoidPtr, Int32, Int32, Int32, Int8) __OMP_RTL(__kmpc_for_static_loop_8, false, Void, IdentPtr, VoidPtr, VoidPtr, Int64, Int64, Int64, Int8) @@ -507,14 +536,253 @@ __OMP_RTL(__kmpc_get_shared_variables, false, Void, VoidPtrPtrPtr) __OMP_RTL(__kmpc_parallel_level, false, Int16, IdentPtr, Int32) __OMP_RTL(__kmpc_is_spmd_exec_mode, false, Int8, ) __OMP_RTL(__kmpc_barrier_simple_spmd, false, Void, IdentPtr, Int32) +__OMP_RTL(__kmpc_workers_done_barriers, false, Void, IdentPtr, Int32) +__OMP_RTL(__kmpc_workers_start_barriers, false, Void, IdentPtr, Int32) __OMP_RTL(__kmpc_barrier_simple_generic, false, Void, IdentPtr, Int32) __OMP_RTL(__kmpc_warp_active_thread_mask, false, Int64,) __OMP_RTL(__kmpc_syncwarp, false, Void, Int64) +__OMP_RTL(__kmpc_is_generic_main_thread_id, false, Int8, Int32) + +__OMP_RTL(__kmpc_atomicCASLoopAdd_float, false, Void, FloatPtr, Float) + +__OMP_RTL(__kmpc_atomicCASLoopAdd_double, false, Void, DoublePtr, Double) + +__OMP_RTL(__kmpc_atomicCASLoopSub_int32_t, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_atomicCASLoopSub_int64_t, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_atomicCASLoopMin_int32_t, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_atomicCASLoopMin_int64_t, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_atomicCASLoopMin_float, false, Void, FloatPtr, Float) + +__OMP_RTL(__kmpc_atomicCASLoopMin_double, false, Void, DoublePtr, Double) + +__OMP_RTL(__kmpc_atomicCASLoopMax_int32_t, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_atomicCASLoopMax_int64_t, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_atomicCASLoopMax_float, false, Void, FloatPtr, Float) + +__OMP_RTL(__kmpc_atomicCASLoopMax_double, false, Void, DoublePtr, Double) + +__OMP_RTL(__kmpc_atomicCASLoopAnd_int32_t, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_atomicCASLoopAnd_int64_t, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_atomicCASLoopOr_int32_t, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_atomicCASLoopOr_int64_t, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_atomicCASLoopXor_int32_t, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_atomicCASLoopXor_int64_t, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_rfun_sum_d, false, Void, DoublePtr, Double) + +__OMP_RTL(__kmpc_rfun_sum_lds_d, false, Void, DoublePtr, Double) + +__OMP_RTL(__kmpc_rfun_sum_f, false, Void, FloatPtr, Float) + +__OMP_RTL(__kmpc_rfun_sum_lds_f, false, Void, FloatPtr, Float) + +__OMP_RTL(__kmpc_rfun_sum_h, false, Void, HalfPtr, Half) + +__OMP_RTL(__kmpc_rfun_sum_lds_h, false, Void, HalfPtr, Half) + +__OMP_RTL(__kmpc_rfun_sum_bf, false, Void, BFloatPtr, BFloat) + +__OMP_RTL(__kmpc_rfun_sum_lds_bf, false, Void, BFloatPtr, BFloat) + +__OMP_RTL(__kmpc_rfun_sum_s, false, Void, Int16Ptr, Int16) + +__OMP_RTL(__kmpc_rfun_sum_lds_s, false, Void, Int16Ptr, Int16) + +__OMP_RTL(__kmpc_rfun_sum_i, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_rfun_sum_lds_i, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_rfun_sum_l, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_rfun_sum_lds_l, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_rfun_min_d, false, Void, DoublePtr, Double) + +__OMP_RTL(__kmpc_rfun_min_lds_d, false, Void, DoublePtr, Double) + +__OMP_RTL(__kmpc_rfun_min_f, false, Void, FloatPtr, Float) + +__OMP_RTL(__kmpc_rfun_min_lds_f, false, Void, FloatPtr, Float) + +__OMP_RTL(__kmpc_rfun_min_h, false, Void, HalfPtr, Half) + +__OMP_RTL(__kmpc_rfun_min_lds_h, false, Void, HalfPtr, Half) + +__OMP_RTL(__kmpc_rfun_min_bf, false, Void, BFloatPtr, BFloat) + +__OMP_RTL(__kmpc_rfun_min_lds_bf, false, Void, BFloatPtr, BFloat) + +__OMP_RTL(__kmpc_rfun_min_s, false, Void, Int16Ptr, Int16) + +__OMP_RTL(__kmpc_rfun_min_lds_s, false, Void, Int16Ptr, Int16) + +__OMP_RTL(__kmpc_rfun_min_i, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_rfun_min_lds_i, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_rfun_min_l, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_rfun_min_lds_l, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_rfun_max_d, false, Void, DoublePtr, Double) + +__OMP_RTL(__kmpc_rfun_max_lds_d, false, Void, DoublePtr, Double) + +__OMP_RTL(__kmpc_rfun_max_f, false, Void, FloatPtr, Float) + +__OMP_RTL(__kmpc_rfun_max_lds_f, false, Void, FloatPtr, Float) + +__OMP_RTL(__kmpc_rfun_max_h, false, Void, HalfPtr, Half) + +__OMP_RTL(__kmpc_rfun_max_lds_h, false, Void, HalfPtr, Half) + +__OMP_RTL(__kmpc_rfun_max_bf, false, Void, BFloatPtr, BFloat) + +__OMP_RTL(__kmpc_rfun_max_lds_bf, false, Void, BFloatPtr, BFloat) + +__OMP_RTL(__kmpc_rfun_max_s, false, Void, Int16Ptr, Int16) + +__OMP_RTL(__kmpc_rfun_max_lds_s, false, Void, Int16Ptr, Int16) + +__OMP_RTL(__kmpc_rfun_max_i, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_rfun_max_lds_i, false, Void, Int32Ptr, Int32) + +__OMP_RTL(__kmpc_rfun_max_l, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_rfun_max_lds_l, false, Void, Int64Ptr, Int64) + +__OMP_RTL(__kmpc_xteamr_d_16x64, false, Void, Double, DoublePtr, DoublePtr, Int32Ptr, VoidPtr, VoidPtr, Double, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_d_16x64_fast_sum, false, Void, Double, DoublePtr, DoublePtr, Int32Ptr, VoidPtr, VoidPtr, Double, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_f_16x64, false, Void, Float, FloatPtr, FloatPtr, Int32Ptr, VoidPtr, VoidPtr, Float, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_f_16x64_fast_sum, false, Void, Float, FloatPtr, FloatPtr, Int32Ptr, VoidPtr, VoidPtr, Float, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_h_16x64, false, Void, Half, HalfPtr, HalfPtr, Int32Ptr, VoidPtr, VoidPtr, Half, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_h_16x64_fast_sum, false, Void, Half, HalfPtr, HalfPtr, Int32Ptr, VoidPtr, VoidPtr, Half, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_bf_16x64, false, Void, BFloat, BFloatPtr, BFloatPtr, Int32Ptr, VoidPtr, VoidPtr, BFloat, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_bf_16x64_fast_sum, false, Void, BFloat, BFloatPtr, BFloatPtr, Int32Ptr, VoidPtr, VoidPtr, BFloat, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_s_16x64, false, Void, Int16, Int16Ptr, Int16Ptr, Int32Ptr, VoidPtr, VoidPtr, Int16, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_s_16x64_fast_sum, false, Void, Int16, Int16Ptr, Int16Ptr, Int32Ptr, VoidPtr, VoidPtr, Int16, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_i_16x64, false, Void, Int32, Int32Ptr, Int32Ptr, Int32Ptr, VoidPtr, VoidPtr, Int32, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_i_16x64_fast_sum, false, Void, Int32, Int32Ptr, Int32Ptr, Int32Ptr, VoidPtr, VoidPtr, Int32, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_l_16x64, false, Void, Int64, Int64Ptr, Int64Ptr, Int32Ptr, VoidPtr, VoidPtr, Int64, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_l_16x64_fast_sum, false, Void, Int64, Int64Ptr, Int64Ptr, Int32Ptr, VoidPtr, VoidPtr, Int64, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_d_32x32, false, Void, Double, DoublePtr, DoublePtr, Int32Ptr, VoidPtr, VoidPtr, Double, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_d_32x32_fast_sum, false, Void, Double, DoublePtr, DoublePtr, Int32Ptr, VoidPtr, VoidPtr, Double, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_f_32x32, false, Void, Float, FloatPtr, FloatPtr, Int32Ptr, VoidPtr, VoidPtr, Float, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_f_32x32_fast_sum, false, Void, Float, FloatPtr, FloatPtr, Int32Ptr, VoidPtr, VoidPtr, Float, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_h_32x32, false, Void, Half, HalfPtr, HalfPtr, Int32Ptr, VoidPtr, VoidPtr, Half, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_h_32x32_fast_sum, false, Void, Half, HalfPtr, HalfPtr, Int32Ptr, VoidPtr, VoidPtr, Half, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_bf_32x32, false, Void, BFloat, BFloatPtr, BFloatPtr, Int32Ptr, VoidPtr, VoidPtr, BFloat, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_bf_32x32_fast_sum, false, Void, BFloat, BFloatPtr, BFloatPtr, Int32Ptr, VoidPtr, VoidPtr, BFloat, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_s_32x32, false, Void, Int16, Int16Ptr, Int16Ptr, Int32Ptr, VoidPtr, VoidPtr, Int16, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_s_32x32_fast_sum, false, Void, Int16, Int16Ptr, Int16Ptr, Int32Ptr, VoidPtr, VoidPtr, Int16, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_i_32x32, false, Void, Int32, Int32Ptr, Int32Ptr, Int32Ptr, VoidPtr, VoidPtr, Int32, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_i_32x32_fast_sum, false, Void, Int32, Int32Ptr, Int32Ptr, Int32Ptr, VoidPtr, VoidPtr, Int32, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_l_32x32, false, Void, Int64, Int64Ptr, Int64Ptr, Int32Ptr, VoidPtr, VoidPtr, Int64, Int64, Int32, Int32) + +__OMP_RTL(__kmpc_xteamr_l_32x32_fast_sum, false, Void, Int64, Int64Ptr, Int64Ptr, Int32Ptr, VoidPtr, VoidPtr, Int64, Int64, Int32, Int32) + __OMP_RTL(__llvm_profile_register_function, false, Void, VoidPtr) __OMP_RTL(__llvm_profile_register_names_function, false, Void, VoidPtr, Int64) +__OMP_RTL(__kmpc_xteams_i_16x64, false, Void, Int32, Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, VoidPtr, VoidPtr, Int32, Int64, Int32) +__OMP_RTL(__kmpc_xteams_i_4x64, false, Void, Int32, Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, VoidPtr, VoidPtr, Int32, Int64, Int32) +__OMP_RTL(__kmpc_xteams_i_8x64, false, Void, Int32, Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, VoidPtr, VoidPtr, Int32, Int64, Int32) +__OMP_RTL(__kmpc_xteams_i_8x32, false, Void, Int32, Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, VoidPtr, VoidPtr, Int32, Int64, Int32) +__OMP_RTL(__kmpc_xteams_i_16x32, false, Void, Int32, Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, VoidPtr, VoidPtr, Int32, Int64, Int32) +__OMP_RTL(__kmpc_xteams_i_32x32, false, Void, Int32, Int32Ptr, Int32Ptr, Int32Ptr, Int32Ptr, VoidPtr, VoidPtr, Int32, Int64, Int32) + +__OMP_RTL(__kmpc_xteams_d_16x64, false, Void, Double, DoublePtr, DoublePtr, DoublePtr, Int32Ptr, VoidPtr, VoidPtr, Double, Int64, Int32) +__OMP_RTL(__kmpc_xteams_d_4x64, false, Void, Double, DoublePtr, DoublePtr, DoublePtr, Int32Ptr, VoidPtr, VoidPtr, Double, Int64, Int32) +__OMP_RTL(__kmpc_xteams_d_8x64, false, Void, Double, DoublePtr, DoublePtr, DoublePtr, Int32Ptr, VoidPtr, VoidPtr, Double, Int64, Int32) +__OMP_RTL(__kmpc_xteams_d_8x32, false, Void, Double, DoublePtr, DoublePtr, DoublePtr, Int32Ptr, VoidPtr, VoidPtr, Double, Int64, Int32) +__OMP_RTL(__kmpc_xteams_d_16x32, false, Void, Double, DoublePtr, DoublePtr, DoublePtr, Int32Ptr, VoidPtr, VoidPtr, Double, Int64, Int32) +__OMP_RTL(__kmpc_xteams_d_32x32, false, Void, Double, DoublePtr, DoublePtr, DoublePtr, Int32Ptr, VoidPtr, VoidPtr, Double, Int64, Int32) + +__OMP_RTL(__kmpc_xteams_f_16x64, false, Void, Float, FloatPtr, FloatPtr, FloatPtr, Int32Ptr, VoidPtr, VoidPtr, Float, Int64, Int32) +__OMP_RTL(__kmpc_xteams_f_4x64, false, Void, Float, FloatPtr, FloatPtr, FloatPtr, Int32Ptr, VoidPtr, VoidPtr, Float, Int64, Int32) +__OMP_RTL(__kmpc_xteams_f_8x64, false, Void, Float, FloatPtr, FloatPtr, FloatPtr, Int32Ptr, VoidPtr, VoidPtr, Float, Int64, Int32) +__OMP_RTL(__kmpc_xteams_f_8x32, false, Void, Float, FloatPtr, FloatPtr, FloatPtr, Int32Ptr, VoidPtr, VoidPtr, Float, Int64, Int32) +__OMP_RTL(__kmpc_xteams_f_16x32, false, Void, Float, FloatPtr, FloatPtr, FloatPtr, Int32Ptr, VoidPtr, VoidPtr, Float, Int64, Int32) +__OMP_RTL(__kmpc_xteams_f_32x32, false, Void, Float, FloatPtr, FloatPtr, FloatPtr, Int32Ptr, VoidPtr, VoidPtr, Float, Int64, Int32) + +__OMP_RTL(__kmpc_xteams_l_16x64, false, Void, Int64, Int64Ptr, Int64Ptr, Int64Ptr, Int32Ptr, VoidPtr, VoidPtr, Int64, Int64, Int32) +__OMP_RTL(__kmpc_xteams_l_4x64, false, Void, Int64, Int64Ptr, Int64Ptr, Int64Ptr, Int32Ptr, VoidPtr, VoidPtr, Int64, Int64, Int32) +__OMP_RTL(__kmpc_xteams_l_8x64, false, Void, Int64, Int64Ptr, Int64Ptr, Int64Ptr, Int32Ptr, VoidPtr, VoidPtr, Int64, Int64, Int32) +__OMP_RTL(__kmpc_xteams_l_8x32, false, Void, Int64, Int64Ptr, Int64Ptr, Int64Ptr, Int32Ptr, VoidPtr, VoidPtr, Int64, Int64, Int32) +__OMP_RTL(__kmpc_xteams_l_16x32, false, Void, Int64, Int64Ptr, Int64Ptr, Int64Ptr, Int32Ptr, VoidPtr, VoidPtr, Int64, Int64, Int32) +__OMP_RTL(__kmpc_xteams_l_32x32, false, Void, Int64, Int64Ptr, Int64Ptr, Int64Ptr, Int32Ptr, VoidPtr, VoidPtr, Int64, Int64, Int32) + + +__OMP_RTL(__kmpc_xteams_phase2_i_16x64, false, Void, Int32Ptr, Int32, Int32Ptr, Int32Ptr, VoidPtr, Int32, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_i_8x64, false, Void, Int32Ptr, Int32, Int32Ptr, Int32Ptr, VoidPtr, Int32, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_i_4x64, false, Void, Int32Ptr, Int32, Int32Ptr, Int32Ptr, VoidPtr, Int32, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_i_8x32, false, Void, Int32Ptr, Int32, Int32Ptr, Int32Ptr, VoidPtr, Int32, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_i_16x32, false, Void, Int32Ptr, Int32, Int32Ptr, Int32Ptr, VoidPtr, Int32, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_i_32x32, false, Void, Int32Ptr, Int32, Int32Ptr, Int32Ptr, VoidPtr, Int32, Int64, Int32) + + +__OMP_RTL(__kmpc_xteams_phase2_d_16x64, false, Void, DoublePtr, Int32, DoublePtr, DoublePtr, VoidPtr, Double, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_d_8x64, false, Void, DoublePtr, Int32, DoublePtr, DoublePtr, VoidPtr, Double, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_d_4x64, false, Void, DoublePtr, Int32, DoublePtr, DoublePtr, VoidPtr, Double, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_d_8x32, false, Void, DoublePtr, Int32, DoublePtr, DoublePtr, VoidPtr, Double, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_d_16x32, false, Void, DoublePtr, Int32, DoublePtr, DoublePtr, VoidPtr, Double, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_d_32x32, false, Void, DoublePtr, Int32, DoublePtr, DoublePtr, VoidPtr, Double, Int64, Int32) + + +__OMP_RTL(__kmpc_xteams_phase2_f_16x64, false, Void, FloatPtr, Int32, FloatPtr, FloatPtr, VoidPtr, Float, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_f_8x64, false, Void, FloatPtr, Int32, FloatPtr, FloatPtr, VoidPtr, Float, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_f_4x64, false, Void, FloatPtr, Int32, FloatPtr, FloatPtr, VoidPtr, Float, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_f_8x32, false, Void, FloatPtr, Int32, FloatPtr, FloatPtr, VoidPtr, Float, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_f_16x32, false, Void, FloatPtr, Int32, FloatPtr, FloatPtr, VoidPtr, Float, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_f_32x32, false, Void, FloatPtr, Int32, FloatPtr, FloatPtr, VoidPtr, Float, Int64, Int32) + + +__OMP_RTL(__kmpc_xteams_phase2_l_16x64, false, Void, Int64Ptr, Int32, Int64Ptr, Int64Ptr, VoidPtr, Int64, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_l_8x64, false, Void, Int64Ptr, Int32, Int64Ptr, Int64Ptr, VoidPtr, Int64, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_l_4x64, false, Void, Int64Ptr, Int32, Int64Ptr, Int64Ptr, VoidPtr, Int64, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_l_8x32, false, Void, Int64Ptr, Int32, Int64Ptr, Int64Ptr, VoidPtr, Int64, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_l_16x32, false, Void, Int64Ptr, Int32, Int64Ptr, Int64Ptr, VoidPtr, Int64, Int64, Int32) +__OMP_RTL(__kmpc_xteams_phase2_l_32x32, false, Void, Int64Ptr, Int32, Int64Ptr, Int64Ptr, VoidPtr, Int64, Int64, Int32) __OMP_RTL(__last, false, Void, ) #undef __OMP_RTL @@ -987,10 +1255,18 @@ __OMP_RTL_ATTRS(__kmpc_doacross_wait, BarrierAttrs, AttributeSet(), __OMP_RTL_ATTRS(__kmpc_doacross_fini, BarrierAttrs, AttributeSet(), ParamAttrs(ReadOnlyPtrAttrs, SExt)) -__OMP_RTL_ATTRS(__kmpc_alloc_shared, - AttributeSet(EnumAttr(NoUnwind), EnumAttr(NoSync), - AllocSizeAttr(0, std::nullopt)), - ReturnPtrAttrs, ParamAttrs(SizeTyExt)) +__OMP_RTL_ATTRS(omp_target_alloc, AttributeSet(), AttributeSet(), ParamAttrs()) +__OMP_RTL_ATTRS(omp_target_free, AttributeSet(), AttributeSet(), ParamAttrs()) +__OMP_RTL_ATTRS(omp_target_memcpy, AttributeSet(), AttributeSet(), ParamAttrs()) +__OMP_RTL_ATTRS(ompx_get_team_procs, AttributeSet(), AttributeSet(), ParamAttrs()) +__OMP_RTL_ATTRS(omp_get_initial_device, AttributeSet(), AttributeSet(), ParamAttrs()) +__OMP_RTL_ATTRS(omp_get_default_device, AttributeSet(), AttributeSet(), ParamAttrs()) + +__OMP_RTL_ATTRS(__kmpc_alloc_shared, AttributeSet( + EnumAttr(NoUnwind), + EnumAttr(NoSync), + AllocSizeAttr(0, std::nullopt)), ReturnPtrAttrs, ParamAttrs(SizeTyExt)) + __OMP_RTL_ATTRS(__kmpc_free_shared, DeviceAllocAttrs, AttributeSet(), ParamAttrs(AttributeSet(NoCaptureAttr, EnumAttr(AllocatedPointer)), @@ -1082,6 +1358,10 @@ __OMP_RTL_ATTRS(__kmpc_target_init, AttributeSet(), SExt, ParamAttrs(AttributeSet())) __OMP_RTL_ATTRS(__kmpc_target_deinit, AttributeSet(), AttributeSet(), ParamAttrs()) +__OMP_RTL_ATTRS(__kmpc_specialized_kernel_init, AttributeSet(), AttributeSet(), + ParamAttrs()) +__OMP_RTL_ATTRS(__kmpc_parallel_spmd, AlwaysInlineAttrs, AttributeSet(), + ParamAttrs()) __OMP_RTL_ATTRS(__kmpc_parallel_51, AlwaysInlineAttrs, AttributeSet(), ParamAttrs(AttributeSet(), SExt, SExt, SExt, SExt, AttributeSet(), AttributeSet(), AttributeSet(), diff --git a/llvm/include/llvm/IR/Attributes.h b/llvm/include/llvm/IR/Attributes.h index e734466ce20e0..0e6e551a0029b 100644 --- a/llvm/include/llvm/IR/Attributes.h +++ b/llvm/include/llvm/IR/Attributes.h @@ -306,6 +306,9 @@ class Attribute { /// Return the FPClassTest for nofpclass LLVM_ABI FPClassTest getNoFPClass() const; + /// Return if global variable is instrumented by AddrSanitizer. + bool isSanitizedPaddedGlobal() const; + /// Returns the value of the range attribute. LLVM_ABI const ConstantRange &getRange() const; diff --git a/llvm/include/llvm/IR/Attributes.td b/llvm/include/llvm/IR/Attributes.td index 8ce2b1bea8fac..c5a39197af2ac 100644 --- a/llvm/include/llvm/IR/Attributes.td +++ b/llvm/include/llvm/IR/Attributes.td @@ -332,6 +332,9 @@ def SanitizeHWAddress : EnumAttr<"sanitize_hwaddress", IntersectPreserve, [FnAtt /// MemTagSanitizer is on. def SanitizeMemTag : EnumAttr<"sanitize_memtag", IntersectPreserve, [FnAttr]>; +/// Attribute to identify global variables instrumented by Sanitizers. +def SanitizedPaddedGlobal : EnumAttr<"sanitized_padded_global", IntersectPreserve, [FnAttr]>; + /// NumericalStabilitySanitizer is on. def SanitizeNumericalStability : EnumAttr<"sanitize_numerical_stability", IntersectPreserve, [FnAttr]>; diff --git a/llvm/include/llvm/IR/DIBuilder.h b/llvm/include/llvm/IR/DIBuilder.h index f3839c9694f34..86a82627a90c6 100644 --- a/llvm/include/llvm/IR/DIBuilder.h +++ b/llvm/include/llvm/IR/DIBuilder.h @@ -99,6 +99,12 @@ namespace llvm { DIExpression *Expr, const DILocation *DL, InsertPosition InsertPt); + /// Internal helper for insertDbgAddrIntrinsic. + Instruction * + insertDbgAddrIntrinsic(llvm::Value *Val, DILocalVariable *VarInfo, + DIExpression *Expr, const DILocation *DL, + BasicBlock *InsertBB, Instruction *InsertBefore); + public: /// Construct a builder for a module. /// @@ -286,13 +292,14 @@ namespace llvm { /// \param SizeInBits Size. /// \param AlignInBits Alignment. (optional) /// \param DWARFAddressSpace DWARF address space. (optional) + /// \param DWARFMemorySpace DWARF memory space. (optional) /// \param Name Pointer type name. (optional) /// \param Annotations Member annotations. - LLVM_ABI DIDerivedType * - createPointerType(DIType *PointeeTy, uint64_t SizeInBits, - uint32_t AlignInBits = 0, - std::optional DWARFAddressSpace = std::nullopt, - StringRef Name = "", DINodeArray Annotations = nullptr); + LLVM_ABI DIDerivedType *createPointerType( + DIType *PointeeTy, uint64_t SizeInBits, uint32_t AlignInBits = 0, + std::optional DWARFAddressSpace = std::nullopt, + dwarf::MemorySpace DWARFMemorySpace = dwarf::DW_MSPACE_LLVM_none, + StringRef Name = "", DINodeArray Annotations = nullptr); /// Create a __ptrauth qualifier. LLVM_ABI DIDerivedType * @@ -316,7 +323,8 @@ namespace llvm { LLVM_ABI DIDerivedType *createReferenceType( unsigned Tag, DIType *RTy, uint64_t SizeInBits = 0, uint32_t AlignInBits = 0, - std::optional DWARFAddressSpace = std::nullopt); + std::optional DWARFAddressSpace = std::nullopt, + dwarf::MemorySpace MS = dwarf::DW_MSPACE_LLVM_none); /// Create debugging information entry for a typedef. /// \param Ty Original type. @@ -855,6 +863,26 @@ namespace llvm { DIGenericSubrange::BoundType UpperBound, DIGenericSubrange::BoundType Stride); + /// Create a new descriptor for the specified variable. + /// \param Context Variable scope. + /// \param Name Name of the variable. + /// \param LinkageName Mangled name of the variable. + /// \param File File where this variable is defined. + /// \param LineNo Line number. + /// \param Ty Variable Type. + /// \param IsLocalToUnit Boolean flag indicate whether this variable is + /// externally visible or not. + /// \param Decl Reference to the corresponding declaration. + /// \param MS DWARF memory space. + /// \param AlignInBits Variable alignment(or 0 if no alignment attr was + /// specified) + DIGlobalVariable *createGlobalVariable( + DIScope *Context, StringRef Name, StringRef LinkageName, DIFile *File, + unsigned LineNo, DIType *Ty, bool IsLocalToUnit, bool isDefined = true, + MDNode *Decl = nullptr, MDTuple *TemplateParams = nullptr, + dwarf::MemorySpace MS = dwarf::DW_MSPACE_LLVM_none, + uint32_t AlignInBits = 0, DINodeArray Annotations = nullptr); + /// Create a new descriptor for the specified variable. /// \param Context Variable scope. /// \param Name Name of the variable. @@ -867,21 +895,25 @@ namespace llvm { /// \param Expr The location of the global relative to the attached /// GlobalVariable. /// \param Decl Reference to the corresponding declaration. + /// \param MS DWARF memory space. /// \param AlignInBits Variable alignment(or 0 if no alignment attr was /// specified) LLVM_ABI DIGlobalVariableExpression *createGlobalVariableExpression( DIScope *Context, StringRef Name, StringRef LinkageName, DIFile *File, unsigned LineNo, DIType *Ty, bool IsLocalToUnit, bool isDefined = true, DIExpression *Expr = nullptr, MDNode *Decl = nullptr, - MDTuple *TemplateParams = nullptr, uint32_t AlignInBits = 0, - DINodeArray Annotations = nullptr); + MDTuple *TemplateParams = nullptr, + dwarf::MemorySpace MS = dwarf::DW_MSPACE_LLVM_none, + uint32_t AlignInBits = 0, DINodeArray Annotations = nullptr); /// Identical to createGlobalVariable /// except that the resulting DbgNode is temporary and meant to be RAUWed. LLVM_ABI DIGlobalVariable *createTempGlobalVariableFwdDecl( DIScope *Context, StringRef Name, StringRef LinkageName, DIFile *File, unsigned LineNo, DIType *Ty, bool IsLocalToUnit, MDNode *Decl = nullptr, - MDTuple *TemplateParams = nullptr, uint32_t AlignInBits = 0); + MDTuple *TemplateParams = nullptr, + dwarf::MemorySpace MS = dwarf::DW_MSPACE_LLVM_none, + uint32_t AlignInBits = 0); /// Create a new descriptor for an auto variable. This is a local variable /// that is not a subprogram parameter. @@ -895,6 +927,7 @@ namespace llvm { createAutoVariable(DIScope *Scope, StringRef Name, DIFile *File, unsigned LineNo, DIType *Ty, bool AlwaysPreserve = false, DINode::DIFlags Flags = DINode::FlagZero, + dwarf::MemorySpace MS = dwarf::DW_MSPACE_LLVM_none, uint32_t AlignInBits = 0); /// Create a new descriptor for an label. @@ -923,6 +956,7 @@ namespace llvm { DIFile *File, unsigned LineNo, DIType *Ty, bool AlwaysPreserve = false, DINode::DIFlags Flags = DINode::FlagZero, + dwarf::MemorySpace MS = dwarf::DW_MSPACE_LLVM_none, DINodeArray Annotations = nullptr); /// Create a new descriptor for the specified diff --git a/llvm/include/llvm/IR/DIExprOps.def b/llvm/include/llvm/IR/DIExprOps.def new file mode 100644 index 0000000000000..a64dc3f634666 --- /dev/null +++ b/llvm/include/llvm/IR/DIExprOps.def @@ -0,0 +1,141 @@ +//===- llvm/IR/DIExprOps.def - DIExpr Op definitions ------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Macros for running through all DIExpr operations. +// +//===----------------------------------------------------------------------===// + +#if !(defined HANDLE_OP_NAME || defined HANDLE_OP0 || defined HANDLE_OP1 || \ + defined HANDLE_OP2) +#error "Missing macro definition of HANDLE_OP*" +#endif + +#if defined HANDLE_OP_NAME && \ + (defined HANDLE_OP0 || defined HANDLE_OP1 || defined HANDLE_OP2) +#error "HANDLE_OP_NAME cannot be defined together with HANDLE_OP{0,1,2}" +#endif + +/// If defined, HANDLE_OP_NAME is invoked for each DIExpr operation. +/// +/// It is invoked with one argument, which is the identifier for the name of +/// the operation. +/// +/// If defined, none of HANDLE_OP{0,1,2} may be defined. +#ifndef HANDLE_OP_NAME +#define HANDLE_OP_NAME(NAME) +#endif + +/// If defined, HANDLE_OP0 is invoked once for each DIExpr operation which has +/// exactly zero arguments. +/// +/// It is invoked with one argument, which is the identifier for the name of +/// the operation. +#ifndef HANDLE_OP0 +#define HANDLE_OP0(NAME) HANDLE_OP_NAME(NAME) +#endif + +/// If defined, HANDLE_OP1 is invoked once for each DIExpr operation which has +/// exactly one argument. +/// +/// It is invoked with three arguments: +/// +/// 1. The identifier for the name of the operation. +/// 2. The type of the first argument to the operation. +/// 3. The identifier for the first argument to the operation. +#ifndef HANDLE_OP1 +#define HANDLE_OP1(NAME, ...) HANDLE_OP_NAME(NAME) +#endif + +/// If defined, HANDLE_OP2 is invoked once for each DIExpr operation which has +/// exactly two arguments. +/// +/// It is invoked with five arguments: +/// +/// 1. The identifier for the name of the operation. +/// 2. The type of the first argument to the operation. +/// 3. The identifier for the first argument to the operation. +/// 4. The type of the second argument to the operation. +/// 5. The identifier for the second argument to the operation. +#ifndef HANDLE_OP2 +#define HANDLE_OP2(NAME, ...) HANDLE_OP_NAME(NAME) +#endif + +/// If defined, SEPARATOR is invoked between each invocation of the HANDLE_OP* +/// macros. +#ifndef SEPARATOR +#define SEPARATOR +#endif + +// FIXME: It seems like `Type` doesn't need to be `const` correct? For some +// reason `TypePrinting` in `AsmPrinter` has no `const` variant. + +// Note that the order of parameters here does not necessarily correspond to +// the order in the IR or bitcode. +HANDLE_OP1(Referrer, Type *, ResultType) +SEPARATOR +HANDLE_OP2(Arg, uint32_t, Index, Type *, ResultType) +SEPARATOR +HANDLE_OP1(TypeObject, Type *, ResultType) +SEPARATOR +HANDLE_OP1(Constant, ConstantData *, LiteralValue) +SEPARATOR +HANDLE_OP1(Convert, Type *, ResultType) +SEPARATOR +HANDLE_OP1(ZExt, Type *, ResultType) +SEPARATOR +HANDLE_OP1(SExt, Type *, ResultType) +SEPARATOR +HANDLE_OP1(Reinterpret, Type *, ResultType) +SEPARATOR +HANDLE_OP1(BitOffset, Type *, ResultType) +SEPARATOR +HANDLE_OP1(ByteOffset, Type *, ResultType) +SEPARATOR +HANDLE_OP2(Composite, uint32_t, Count, Type *, ResultType) +SEPARATOR +HANDLE_OP1(Extend, uint32_t, Count) +SEPARATOR +HANDLE_OP0(Select) +SEPARATOR +HANDLE_OP1(AddrOf, uint32_t, AddressSpace) +SEPARATOR +HANDLE_OP1(Deref, Type *, ResultType) +SEPARATOR +HANDLE_OP0(Read) +SEPARATOR +HANDLE_OP0(Add) +SEPARATOR +HANDLE_OP0(Sub) +SEPARATOR +HANDLE_OP0(Mul) +SEPARATOR +HANDLE_OP0(Div) +SEPARATOR +HANDLE_OP0(LShr) +SEPARATOR +HANDLE_OP0(AShr) +SEPARATOR +HANDLE_OP0(Shl) +SEPARATOR +HANDLE_OP0(And) +SEPARATOR +HANDLE_OP0(Or) +SEPARATOR +HANDLE_OP0(Xor) +SEPARATOR +HANDLE_OP0(Mod) +SEPARATOR +HANDLE_OP1(PushLane, Type *, ResultType) +SEPARATOR +HANDLE_OP2(Fragment, uint32_t, BitOffset, uint32_t, BitSize) + +#undef SEPARATOR +#undef HANDLE_OP2 +#undef HANDLE_OP1 +#undef HANDLE_OP0 +#undef HANDLE_OP_NAME diff --git a/llvm/include/llvm/IR/DebugInfoMetadata.h b/llvm/include/llvm/IR/DebugInfoMetadata.h index c626efc9daaa4..0cfd11bba7614 100644 --- a/llvm/include/llvm/IR/DebugInfoMetadata.h +++ b/llvm/include/llvm/IR/DebugInfoMetadata.h @@ -15,11 +15,14 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitmaskEnum.h" +#include "llvm/ADT/Hashing.h" #include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallBitVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/iterator_range.h" +#include "llvm/BinaryFormat/Dwarf.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DbgVariableFragmentInfo.h" #include "llvm/IR/Metadata.h" @@ -1303,15 +1306,16 @@ class DIDerivedType : public DIType { /// The DWARF address space of the memory pointed to or referenced by a /// pointer or reference type respectively. std::optional DWARFAddressSpace; + dwarf::MemorySpace DWARFMemorySpace; DIDerivedType(LLVMContext &C, StorageType Storage, unsigned Tag, unsigned Line, uint32_t AlignInBits, - std::optional DWARFAddressSpace, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS, std::optional PtrAuthData, DIFlags Flags, ArrayRef Ops) : DIType(C, DIDerivedTypeKind, Storage, Tag, Line, AlignInBits, 0, Flags, Ops), - DWARFAddressSpace(DWARFAddressSpace) { + DWARFAddressSpace(DWARFAddressSpace), DWARFMemorySpace(MS) { if (PtrAuthData) SubclassData32 = PtrAuthData->RawData; } @@ -1320,7 +1324,7 @@ class DIDerivedType : public DIType { getImpl(LLVMContext &Context, unsigned Tag, StringRef Name, DIFile *File, unsigned Line, DIScope *Scope, DIType *BaseType, uint64_t SizeInBits, uint32_t AlignInBits, uint64_t OffsetInBits, - std::optional DWARFAddressSpace, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS, std::optional PtrAuthData, DIFlags Flags, Metadata *ExtraData, DINodeArray Annotations, StorageType Storage, bool ShouldCreate = true) { @@ -1330,14 +1334,14 @@ class DIDerivedType : public DIType { ConstantInt::get(Type::getInt64Ty(Context), OffsetInBits)); return getImpl(Context, Tag, getCanonicalMDString(Context, Name), File, Line, Scope, BaseType, SizeInBitsNode, AlignInBits, - OffsetInBitsNode, DWARFAddressSpace, PtrAuthData, Flags, + OffsetInBitsNode, DWARFAddressSpace, MS, PtrAuthData, Flags, ExtraData, Annotations.get(), Storage, ShouldCreate); } static DIDerivedType * getImpl(LLVMContext &Context, unsigned Tag, MDString *Name, DIFile *File, unsigned Line, DIScope *Scope, DIType *BaseType, uint64_t SizeInBits, uint32_t AlignInBits, uint64_t OffsetInBits, - std::optional DWARFAddressSpace, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS, std::optional PtrAuthData, DIFlags Flags, Metadata *ExtraData, DINodeArray Annotations, StorageType Storage, bool ShouldCreate = true) { @@ -1347,27 +1351,27 @@ class DIDerivedType : public DIType { ConstantInt::get(Type::getInt64Ty(Context), OffsetInBits)); return getImpl(Context, Tag, Name, File, Line, Scope, BaseType, SizeInBitsNode, AlignInBits, OffsetInBitsNode, - DWARFAddressSpace, PtrAuthData, Flags, ExtraData, + DWARFAddressSpace, MS, PtrAuthData, Flags, ExtraData, Annotations.get(), Storage, ShouldCreate); } static DIDerivedType * getImpl(LLVMContext &Context, unsigned Tag, StringRef Name, DIFile *File, unsigned Line, DIScope *Scope, DIType *BaseType, Metadata *SizeInBits, uint32_t AlignInBits, Metadata *OffsetInBits, - std::optional DWARFAddressSpace, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS, std::optional PtrAuthData, DIFlags Flags, Metadata *ExtraData, DINodeArray Annotations, StorageType Storage, bool ShouldCreate = true) { return getImpl(Context, Tag, getCanonicalMDString(Context, Name), File, Line, Scope, BaseType, SizeInBits, AlignInBits, OffsetInBits, - DWARFAddressSpace, PtrAuthData, Flags, ExtraData, - Annotations.get(), Storage, ShouldCreate); + DWARFAddressSpace, MS, PtrAuthData, Flags, ExtraData, Annotations.get(), + Storage, ShouldCreate); } LLVM_ABI static DIDerivedType * getImpl(LLVMContext &Context, unsigned Tag, MDString *Name, Metadata *File, unsigned Line, Metadata *Scope, Metadata *BaseType, Metadata *SizeInBits, uint32_t AlignInBits, Metadata *OffsetInBits, - std::optional DWARFAddressSpace, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS, std::optional PtrAuthData, DIFlags Flags, Metadata *ExtraData, Metadata *Annotations, StorageType Storage, bool ShouldCreate = true); @@ -1376,7 +1380,7 @@ class DIDerivedType : public DIType { return getTemporary( getContext(), getTag(), getRawName(), getFile(), getLine(), getScope(), getBaseType(), getRawSizeInBits(), getAlignInBits(), - getRawOffsetInBits(), getDWARFAddressSpace(), getPtrAuthData(), + getRawOffsetInBits(), getDWARFAddressSpace(), getDWARFMemorySpace(), getPtrAuthData(), getFlags(), getExtraData(), getRawAnnotations()); } @@ -1386,49 +1390,55 @@ class DIDerivedType : public DIType { unsigned Line, Metadata *Scope, Metadata *BaseType, Metadata *SizeInBits, uint32_t AlignInBits, Metadata *OffsetInBits, - std::optional DWARFAddressSpace, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS, std::optional PtrAuthData, DIFlags Flags, Metadata *ExtraData = nullptr, Metadata *Annotations = nullptr), (Tag, Name, File, Line, Scope, BaseType, SizeInBits, - AlignInBits, OffsetInBits, DWARFAddressSpace, PtrAuthData, + AlignInBits, OffsetInBits, DWARFAddressSpace, MS, PtrAuthData, Flags, ExtraData, Annotations)) DEFINE_MDNODE_GET(DIDerivedType, (unsigned Tag, StringRef Name, DIFile *File, unsigned Line, DIScope *Scope, DIType *BaseType, Metadata *SizeInBits, uint32_t AlignInBits, Metadata *OffsetInBits, - std::optional DWARFAddressSpace, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS, std::optional PtrAuthData, DIFlags Flags, Metadata *ExtraData = nullptr, DINodeArray Annotations = nullptr), (Tag, Name, File, Line, Scope, BaseType, SizeInBits, - AlignInBits, OffsetInBits, DWARFAddressSpace, PtrAuthData, + AlignInBits, OffsetInBits, DWARFAddressSpace, MS, PtrAuthData, Flags, ExtraData, Annotations)) DEFINE_MDNODE_GET(DIDerivedType, (unsigned Tag, MDString *Name, DIFile *File, unsigned Line, DIScope *Scope, DIType *BaseType, uint64_t SizeInBits, uint32_t AlignInBits, uint64_t OffsetInBits, - std::optional DWARFAddressSpace, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS, std::optional PtrAuthData, DIFlags Flags, Metadata *ExtraData = nullptr, DINodeArray Annotations = nullptr), (Tag, Name, File, Line, Scope, BaseType, SizeInBits, - AlignInBits, OffsetInBits, DWARFAddressSpace, PtrAuthData, + AlignInBits, OffsetInBits, DWARFAddressSpace, MS, PtrAuthData, Flags, ExtraData, Annotations)) DEFINE_MDNODE_GET(DIDerivedType, (unsigned Tag, StringRef Name, DIFile *File, unsigned Line, DIScope *Scope, DIType *BaseType, uint64_t SizeInBits, uint32_t AlignInBits, uint64_t OffsetInBits, - std::optional DWARFAddressSpace, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS, std::optional PtrAuthData, DIFlags Flags, Metadata *ExtraData = nullptr, DINodeArray Annotations = nullptr), (Tag, Name, File, Line, Scope, BaseType, SizeInBits, - AlignInBits, OffsetInBits, DWARFAddressSpace, PtrAuthData, - Flags, ExtraData, Annotations)) + AlignInBits, OffsetInBits, DWARFAddressSpace, MS, PtrAuthData, Flags, + ExtraData, Annotations)) TempDIDerivedType clone() const { return cloneImpl(); } + TempDIDerivedType cloneWithAddressSpace(unsigned DWARFAddrSpace) const { + auto Tmp = clone(); + Tmp->DWARFAddressSpace = DWARFAddrSpace; + return Tmp; + } + /// Get the base type this is derived from. DIType *getBaseType() const { return cast_or_null(getRawBaseType()); } Metadata *getRawBaseType() const { return getOperand(MY_FIRST_OPERAND); } @@ -1439,6 +1449,10 @@ class DIDerivedType : public DIType { return DWARFAddressSpace; } + /// \returns The DWARF memory space of the memory pointed to or referenced by + /// a pointer or reference type respectively. + dwarf::MemorySpace getDWARFMemorySpace() const { return DWARFMemorySpace; } + LLVM_ABI std::optional getPtrAuthData() const; /// Get extra data associated with this derived type. @@ -3287,11 +3301,12 @@ class DITemplateValueParameter : public DITemplateParameter { /// Uses the SubclassData32 Metadata slot. class DIVariable : public DINode { unsigned Line; + dwarf::MemorySpace MemorySpace; protected: LLVM_ABI DIVariable(LLVMContext &C, unsigned ID, StorageType Storage, signed Line, ArrayRef Ops, - uint32_t AlignInBits = 0); + dwarf::MemorySpace MS, uint32_t AlignInBits = 0); ~DIVariable() = default; public: @@ -3331,6 +3346,9 @@ class DIVariable : public DINode { return std::nullopt; } + /// \returns The DWARF memory space in which the variable resides. + dwarf::MemorySpace getDWARFMemorySpace() const { return MemorySpace; } + Metadata *getRawScope() const { return getOperand(0); } MDString *getRawName() const { return getOperandAs(1); } Metadata *getRawFile() const { return getOperand(2); } @@ -3342,6 +3360,427 @@ class DIVariable : public DINode { } }; +namespace DIOp { + +// These are the concrete alternatives that a DIOp::Variant encapsulates. +#define HANDLE_OP0(NAME) \ + class NAME { \ + public: \ + explicit constexpr NAME() {} \ + bool operator==(const NAME &O) const { return true; } \ + friend hash_code hash_value(const NAME &O); \ + static constexpr StringRef getAsmName(); \ + static constexpr unsigned getBitcodeID(); \ + }; +#define HANDLE_OP1(NAME, TYPE1, NAME1) \ + class NAME { \ + TYPE1 NAME1; \ + \ + public: \ + explicit constexpr NAME(TYPE1 NAME1) : NAME1(NAME1) {} \ + bool operator==(const NAME &O) const { return NAME1 == O.NAME1; } \ + friend hash_code hash_value(const NAME &O); \ + static constexpr StringRef getAsmName(); \ + static constexpr unsigned getBitcodeID(); \ + TYPE1 get##NAME1() const { return NAME1; } \ + void set##NAME1(TYPE1 NAME1) { this->NAME1 = NAME1; } \ + }; +#define HANDLE_OP2(NAME, TYPE1, NAME1, TYPE2, NAME2) \ + class NAME { \ + TYPE1 NAME1; \ + TYPE2 NAME2; \ + \ + public: \ + explicit constexpr NAME(TYPE1 NAME1, TYPE2 NAME2) \ + : NAME1(NAME1), NAME2(NAME2) {} \ + bool operator==(const NAME &O) const { \ + return NAME1 == O.NAME1 && NAME2 == O.NAME2; \ + } \ + friend hash_code hash_value(const NAME &O); \ + static constexpr StringRef getAsmName(); \ + static constexpr unsigned getBitcodeID(); \ + TYPE1 get##NAME1() const { return NAME1; } \ + void set##NAME1(TYPE1 NAME1) { this->NAME1 = NAME1; } \ + TYPE2 get##NAME2() const { return NAME2; } \ + void set##NAME2(TYPE2 NAME2) { this->NAME2 = NAME2; } \ + }; +LLVM_PACKED_START +#include "llvm/IR/DIExprOps.def" +LLVM_PACKED_END + +/// Container for a runtime-variant DIOp +using Variant = std::variant< +#define HANDLE_OP_NAME(NAME) NAME +#define SEPARATOR , +#include "llvm/IR/DIExprOps.def" + >; + +#define HANDLE_OP_NAME(NAME) \ + constexpr StringRef DIOp::NAME::getAsmName() { return "DIOp" #NAME; } +#include "llvm/IR/DIExprOps.def" + +StringRef getAsmName(const Variant &V); + +#define DEFINE_BC_ID(NAME, ID) \ + constexpr unsigned DIOp::NAME::getBitcodeID() { return ID; } +DEFINE_BC_ID(Referrer, 1u) +DEFINE_BC_ID(Arg, 2u) +DEFINE_BC_ID(TypeObject, 3u) +DEFINE_BC_ID(Constant, 4u) +DEFINE_BC_ID(Convert, 5u) +DEFINE_BC_ID(Reinterpret, 6u) +DEFINE_BC_ID(BitOffset, 7u) +DEFINE_BC_ID(ByteOffset, 8u) +DEFINE_BC_ID(Composite, 9u) +DEFINE_BC_ID(Extend, 10u) +DEFINE_BC_ID(Select, 11u) +DEFINE_BC_ID(AddrOf, 12u) +DEFINE_BC_ID(Deref, 13u) +DEFINE_BC_ID(Read, 14u) +DEFINE_BC_ID(Add, 15u) +DEFINE_BC_ID(Sub, 16u) +DEFINE_BC_ID(Mul, 17u) +DEFINE_BC_ID(Div, 18u) +DEFINE_BC_ID(LShr, 19u) +DEFINE_BC_ID(Shl, 20u) +DEFINE_BC_ID(PushLane, 21u) +DEFINE_BC_ID(Fragment, 22u) +DEFINE_BC_ID(ZExt, 23u) +DEFINE_BC_ID(SExt, 24u) +DEFINE_BC_ID(AShr, 25u) +DEFINE_BC_ID(And, 26u) +DEFINE_BC_ID(Or, 27u) +DEFINE_BC_ID(Xor, 28u) +DEFINE_BC_ID(Mod, 29u) +#undef DEFINE_BC_ID + +unsigned getBitcodeID(const Variant &V); + +/// Get the number of stack elements this operation consumes. +unsigned getNumInputs(Variant V); + +// The sizeof of `Op` is the size of the largest union variant, which +// should essentially be defined as a packed struct equivalent to: +// +// uint8_t Index; // Internal to std::variant, but we expect this to be +// // the smallest available integral type which +// // can represent our set of alternatives. +// uint32_t I; +// void* P; +// +// Note that there is no public interface which lets a pointer to the members +// of the alternative types escape, and so we can safely pack them. This +// means huge performance benefits (smaller memory footprint and more +// cache-friendly traversal). +// +// This static_assert tries to catch issues where the struct is not packed into +// at most two 64-bit words, as we would expect it to be. +// +// FIXME: If we can constrain `I` further to <= 16 bits we should also +// fit in two 32-bit words on 32-bit targets. +static_assert(sizeof(DIOp::Variant) <= 16); + +} // namespace DIOp + +/// Context in which a DIExpression is to be evaluated, used to permit more +/// complete validation. +struct DIExpressionEnv { + /// The source variable whose location is being described by the expression. + DIVariable *Variable; + /// Argument(s) to the debug intrinsic or DIGlobalVariableExpression node + /// referencing the expression. + ArrayRef Arguments; + /// DataLayout of the Target associated with the expression. + const DataLayout &DL; +}; + +/// CRTP visitor class for visiting DIExpr operations in order. +/// +/// The derived class must provide an overload set for the method +/// `bool visit(OpT Op, Type *ResultType, ArrayRef Inputs)` handling +/// every "DIOp*" `OpT` (i.e. for every alternative type of `DIOp::Variant`). +/// The `ResultType` is the type of the entry the operation pushes onto the +/// stack (or `nullptr` if the operation pushes nothing). The `Inputs` are the +/// stack entries the operation consumes, where the highest index is the top of +/// the stack (i.e. the most recently pushed entry). The return value is +/// `true` when the visit succeeds, and `false` when it fails; a returned +/// `false` will short-circuit to the caller, so the rest of the expression will +/// not be visited. +/// +/// For convenience a no-op overload set is defined in this class, where each +/// method simply returns `true`. If the derived class does not intend to +/// exhaustively cover every "DIOp*" operation it can declare `using +/// DIExprConstVisitor::visit;` to bring the no-op overload set into +/// the derived class, and then it can selectively shadow the overloads it is +/// interested in. This scheme is employed to avoid the need for dynamic virtual +/// function dispatch. +/// +/// This class validates that the expression yields one stack entry. To visit +/// that final `StackEntry` the derived class can implement `bool +/// visitResult(StackEntry Result)`. +/// +/// To handle error messages generated by this class, the derived class can +/// define a method `bool error(const Twine &)` which will be called with +/// any error messages before `false` is returned. +/// +/// This class implements type propagation, and maintains a stack so operation +/// visitor functions can inspect their input stack entries. It validates +/// properties of the expression which can be checked purely by looking at the +/// expression itself, including: +/// +/// * Input and result type equality (e.g. for arithmetic operations) +/// * Type category requirements (e.g. for shift operations requiring integer +/// types) +/// * Input counts, including the dynamic input requirement of DIOpComposite +/// +/// Anything further, including debug intrinsic argument type compatibility +/// with DIOpArg uses, must be handled by the derived class if required. +template class DIExprConstVisitor { +protected: + LLVMContext &Context; + ArrayRef Expr; + + /// Represents the result of evaluating an operation. + /// ResultType cannot be null. + struct StackEntry { + DIOp::Variant Operation; + Type *ResultType; + + StackEntry(DIOp::Variant Operation, Type *ResultType) + : Operation(Operation), ResultType(ResultType) { + assert(ResultType && + "null ResultType indicates no StackEntry should be created"); + } + }; + + SmallVector Stack; + + bool error(const Twine &) { return false; } + + Derived &getDerived() { return static_cast(*this); } + + std::optional getTypeError(const Twine &Msg) { + getDerived().error(Msg); + return std::nullopt; + } + + // The getType overloads return: + // + // * std::nullopt when an error has occured. + // * nullptr when the operation does not push anything. + // * the type of the pushed entry, otherwise. + // + // Note: This assumes operations push either 0 or 1 entries, which is + // currently true. + + std::optional getType(DIOp::Referrer Op, ArrayRef) { + return Op.getResultType(); + } + + std::optional getType(DIOp::Arg Op, ArrayRef) { + return Op.getResultType(); + } + + std::optional getType(DIOp::TypeObject Op, ArrayRef) { + return Op.getResultType(); + } + + std::optional getType(DIOp::Constant Op, ArrayRef) { + return Op.getLiteralValue()->getType(); + } + + std::optional getType(DIOp::Convert Op, ArrayRef) { + return Op.getResultType(); + } + + std::optional getType(DIOp::ZExt Op, ArrayRef Ins) { + if (!Ins[0].ResultType->isIntegerTy()) + return getTypeError("DIOpZExt requires integer typed input"); + return Op.getResultType(); + } + + std::optional getType(DIOp::SExt Op, ArrayRef Ins) { + if (!Ins[0].ResultType->isIntegerTy()) + return getTypeError("DIOpSExt requires integer typed input"); + return Op.getResultType(); + } + + std::optional getType(DIOp::Reinterpret Op, ArrayRef) { + return Op.getResultType(); + } + + std::optional getType(DIOp::BitOffset Op, ArrayRef Ins) { + if (!Ins[1].ResultType->isIntegerTy()) + return getTypeError( + "DIOpBitOffset requires first input be integer typed"); + return Op.getResultType(); + } + + std::optional getType(DIOp::ByteOffset Op, ArrayRef Ins) { + if (!Ins[1].ResultType->isIntegerTy()) + return getTypeError( + "DIOpByteOffset requires first input be integer typed"); + return Op.getResultType(); + } + + std::optional getType(DIOp::Composite Op, ArrayRef Ins) { + assert(Op.getCount() == Ins.size() && + "DIOpComposite has wrong number of inputs"); + return Op.getResultType(); + } + + std::optional getType(DIOp::Extend Op, ArrayRef Ins) { + if (!Ins[0].ResultType->isPointerTy() && + !Ins[0].ResultType->isFloatingPointTy() && + !Ins[0].ResultType->isIntegerTy()) + return getTypeError( + "DIOpExtend child must have integer, floating point, or ptr type"); + return VectorType::get(Ins[0].ResultType, + ElementCount::getFixed(Op.getCount())); + } + + std::optional getType(DIOp::Select Op, ArrayRef Ins) { + if (Ins[1].ResultType != Ins[2].ResultType) + return getTypeError( + "DIOpSelect requires first two inputs have same type"); + if (!Ins[1].ResultType->isVectorTy()) + return getTypeError( + "DIOpSelect requires first two inputs to be vector typed"); + return Ins[1].ResultType; + } + + std::optional getType(DIOp::AddrOf Op, ArrayRef) { + // FIXME: Track this to ensure invariants on uses + return PointerType::get(Context, Op.getAddressSpace()); + } + + std::optional getType(DIOp::Deref Op, ArrayRef Ins) { + if (!Ins[0].ResultType->isPointerTy()) + return getTypeError("DIOpDeref requires input to be pointer typed"); + return Op.getResultType(); + } + + std::optional getType(DIOp::Read Op, ArrayRef Ins) { + return Ins[0].ResultType; + } + + template + std::optional getTypeBinOp(OpT Op, ArrayRef Ins) { + if (Ins[0].ResultType != Ins[1].ResultType) + return getTypeError(Twine(Op.getAsmName()) + + " requires identical type inputs"); + return Ins[0].ResultType; + } + + std::optional getType(DIOp::Add Op, ArrayRef Ins) { + return getTypeBinOp(Op, Ins); + } + + std::optional getType(DIOp::Sub Op, ArrayRef Ins) { + return getTypeBinOp(Op, Ins); + } + + std::optional getType(DIOp::Mul Op, ArrayRef Ins) { + return getTypeBinOp(Op, Ins); + } + + std::optional getType(DIOp::Div Op, ArrayRef Ins) { + return getTypeBinOp(Op, Ins); + } + + std::optional getType(DIOp::Mod Op, ArrayRef Ins) { + return getTypeBinOp(Op, Ins); + } + + std::optional getType(DIOp::LShr, ArrayRef Ins) { + if (!Ins[0].ResultType->isIntegerTy() || !Ins[1].ResultType->isIntegerTy()) + return getTypeError("DIOpLShr requires all integer inputs"); + return Ins[0].ResultType; + } + + std::optional getType(DIOp::AShr, ArrayRef Ins) { + if (!Ins[0].ResultType->isIntegerTy() || !Ins[1].ResultType->isIntegerTy()) + return getTypeError("DIOpAShr requires all integer inputs"); + return Ins[0].ResultType; + } + + std::optional getType(DIOp::Shl, ArrayRef Ins) { + if (!Ins[0].ResultType->isIntegerTy() || !Ins[1].ResultType->isIntegerTy()) + return getTypeError("DIOpShl requires all integer inputs"); + return Ins[0].ResultType; + } + + std::optional getType(DIOp::And, ArrayRef Ins) { + if (!Ins[0].ResultType->isIntegerTy() || !Ins[1].ResultType->isIntegerTy()) + return getTypeError("DIOpAnd requires all integer inputs"); + return Ins[0].ResultType; + } + + std::optional getType(DIOp::Or, ArrayRef Ins) { + if (!Ins[0].ResultType->isIntegerTy() || !Ins[1].ResultType->isIntegerTy()) + return getTypeError("DIOpOr requires all integer inputs"); + return Ins[0].ResultType; + } + + std::optional getType(DIOp::Xor, ArrayRef Ins) { + if (!Ins[0].ResultType->isIntegerTy() || !Ins[1].ResultType->isIntegerTy()) + return getTypeError("DIOpXor requires all integer inputs"); + return Ins[0].ResultType; + } + + std::optional getType(DIOp::PushLane Op, ArrayRef) { + if (!Op.getResultType()->isIntegerTy()) + return getTypeError("DIOpPushLane requires integer result type"); + return Op.getResultType(); + } + + std::optional getType(DIOp::Fragment, ArrayRef) { + return nullptr; + } + + template bool visitOperator(OpT Op) { + if (Stack.size() < getNumInputs(Op)) + return getDerived().error(Op.getAsmName() + " requires more inputs"); + auto InBegin = Stack.end() - getNumInputs(Op); + std::optional Ty = getType(Op, ArrayRef(InBegin, Stack.end())); + if (!Ty) + return false; + if (!getDerived().visit(Op, *Ty, ArrayRef(InBegin, Stack.end()))) + return false; + Stack.erase(InBegin, Stack.end()); + if (*Ty) + Stack.emplace_back(Op, *Ty); + return true; + } + +#define HANDLE_OP_NAME(NAME) \ + bool visit(DIOp::NAME Op, Type *ResultType, ArrayRef Inputs) { \ + return true; \ + } +#include "DIExprOps.def" + + bool visitResult(StackEntry Result) { return true; } + +public: + DIExprConstVisitor(LLVMContext &Context, ArrayRef Expr) + : Context(Context), Expr(Expr) {} + + bool visitInOrder() { + for (const auto &Op : Expr) { + if (!std::visit([this](auto Op) { return this->visitOperator(Op); }, Op)) + return false; + } + if (Stack.size() != 1) { + getDerived().error( + "DIOp expression requires one element on stack after evaluating"); + return false; + } + if (!getDerived().visitResult(Stack.back())) + return false; + return true; + } +}; + /// DWARF expression. /// /// This is (almost) a DWARF expression that modifies the location of a @@ -3355,15 +3794,76 @@ class DIExpression : public MDNode { friend class LLVMContextImpl; friend class MDNode; - std::vector Elements; +public: + using OldElements = std::vector; + using NewElements = SmallVector; + using OldElementsRef = ArrayRef; + using NewElementsRef = ArrayRef; + using ElementsRef = std::variant; + +private: + std::variant Elements; + + // When existing code operates on a DIOp-based (i.e. "NewElements") + // DIExpression they will transparently see this expression in place of + // the actual expression. So long as they unconditionally replace the + // expression with a new "OldElements" version derived from this poison we + // will see this DW_OP_LLVM_poisoned operation during DWARF generation and can + // e.g. lower it to an undefined location to reflect the fact that the + // expression was not understood by some pass. + // + // There is some risk that a particular set of circumstances in code from + // upstream could align to foil this scheme, e.g. if a pass were to + // inspect an expression to see if it contains some particular pattern + // and decides only to update the expression in the absense of that pattern + // then the poisoned expression would lead to it not making the change. In + // practice no such call-site could be identified in the codebase, and in + // general the decision to modify the expression is made irrespective of + // the expression contents (although the contents in many cases then + // influences exactly *how* the expression is modified). + static constexpr std::array PoisonedExpr = { + dwarf::DW_OP_LLVM_poisoned}; + + DIExpression *getPoisonedFragment(unsigned OffsetInBits, + unsigned SizeInBits) const { + std::array PoisonedOps = {dwarf::DW_OP_LLVM_poisoned, + dwarf::DW_OP_LLVM_fragment, + OffsetInBits, SizeInBits}; + return DIExpression::get(getContext(), PoisonedOps); + } + + OldElementsRef getPoisonedElements() const { + std::optional Frag = getFragmentInfo(); + if (!Frag) + return PoisonedExpr; + return getPoisonedFragment(Frag->OffsetInBits, Frag->SizeInBits) + ->getElements(); + } DIExpression(LLVMContext &C, StorageType Storage, ArrayRef Elements) : MDNode(C, DIExpressionKind, Storage, {}), - Elements(Elements.begin(), Elements.end()) {} + Elements(std::in_place_type, Elements.begin(), + Elements.end()) {} + DIExpression(LLVMContext &C, StorageType Storage, + ArrayRef Elements) + : MDNode(C, DIExpressionKind, Storage, {}), + Elements(std::in_place_type, Elements.begin(), + Elements.end()) {} ~DIExpression() = default; + // FIXME: workaround to avoid updating callsites for now LLVM_ABI static DIExpression *getImpl(LLVMContext &Context, - ArrayRef Elements, + std::nullopt_t Elements, + StorageType Storage, + bool ShouldCreate = true); + + LLVM_ABI static DIExpression *getImpl(LLVMContext &Context, + OldElementsRef Elements, + StorageType Storage, + bool ShouldCreate = true); + + LLVM_ABI static DIExpression *getImpl(LLVMContext &Context, bool /*ignored*/, + NewElementsRef Elements, StorageType Storage, bool ShouldCreate = true); @@ -3372,19 +3872,59 @@ class DIExpression : public MDNode { } public: + DIExpression *getPoisoned() const { + std::optional Frag = getFragmentInfo(); + if (!Frag) + return DIExpression::get(getContext(), PoisonedExpr); + return getPoisonedFragment(Frag->OffsetInBits, Frag->SizeInBits); + } + + DEFINE_MDNODE_GET(DIExpression, (std::nullopt_t Elements), (Elements)) DEFINE_MDNODE_GET(DIExpression, (ArrayRef Elements), (Elements)) + // The bool parameter is ignored, and only present to disambiguate the + // overload for the new elements from the old for the empty initializer list + // case (i.e. DIExpression::new({})) + DEFINE_MDNODE_GET(DIExpression, + (bool /*ignored*/, ArrayRef Elements), + (false, Elements)) TempDIExpression clone() const { return cloneImpl(); } - ArrayRef getElements() const { return Elements; } + OldElementsRef getElements() const { + if (auto *E = std::get_if(&Elements)) + return *E; + return getPoisonedElements(); + } - unsigned getNumElements() const { return Elements.size(); } + unsigned getNumElements() const { return getElements().size(); } uint64_t getElement(unsigned I) const { - assert(I < Elements.size() && "Index out of range"); - return Elements[I]; + assert(I < getNumElements() && "Index out of range"); + return getElements()[I]; } + ElementsRef getElementsRef() const { + return std::visit([](auto &&V) -> ElementsRef { return {V}; }, Elements); + } + std::optional getOldElementsRef() const { + if (auto *E = std::get_if(&Elements)) + return *E; + return std::nullopt; + } + std::optional getNewElementsRef() const { + if (auto *E = std::get_if(&Elements)) + return *E; + return std::nullopt; + } + + template bool holds() const { + return std::holds_alternative(Elements); + } + bool holdsOldElements() const { return holds(); } + bool holdsNewElements() const { return holds(); } + + bool isPoisoned() const; + enum SignedOrUnsignedConstant { SignedConstant, UnsignedConstant }; /// Determine whether this represents a constant value, if so // return it's sign information. @@ -3400,11 +3940,28 @@ class DIExpression : public MDNode { /// (0 and 1). LLVM_ABI uint64_t getNumLocationOperands() const; + /// Return the number of unique location operands referred to (via DIOpArg) in + /// this expression. Like getNumLocationOperands, but for DIOp-DIExpressions. + uint64_t getNewNumLocationOperands() const; + using element_iterator = ArrayRef::iterator; element_iterator elements_begin() const { return getElements().begin(); } element_iterator elements_end() const { return getElements().end(); } + /// Returns the pointer address space this DIOp-based DIExpression produces. + /// Note that this may diverge from the the pointer address space of the + /// result type. When there is a divergent address space, the DIExpression + /// must produce a generic pointer whose value can be proven to belong to a + /// more specific address space. For instance in this expression, this + /// function returns 4: + /// + /// !DIExpression(DIOpArg(0, ptr addrspace(4)), DIOpConvert(ptr)) + /// + /// A divergent address space can be created by a DIOpConvert, and is + /// preserved across DIOpReinterpret. + std::optional getNewDivergentAddrSpace() const; + /// A lightweight wrapper around an expression operand. /// /// TODO: Store arguments directly and change \a DIExpression to store a @@ -3504,7 +4061,9 @@ class DIExpression : public MDNode { } /// @} - LLVM_ABI bool isValid() const; + LLVM_ABI bool isValid(std::optional Env = std::nullopt, + std::optional> + ErrS = std::nullopt) const; static bool classof(const Metadata *MD) { return MD->getMetadataID() == DIExpressionKind; @@ -3528,8 +4087,12 @@ class DIExpression : public MDNode { LLVM_ABI static std::optional getFragmentInfo(expr_op_iterator Start, expr_op_iterator End); + static std::optional getFragmentInfo(NewElementsRef E); + /// Retrieve the details of this fragment expression. std::optional getFragmentInfo() const { + if (auto NewElements = getNewElementsRef()) + return getFragmentInfo(*NewElements); return getFragmentInfo(expr_op_begin(), expr_op_end()); } @@ -3679,6 +4242,38 @@ class DIExpression : public MDNode { unsigned ArgNo, bool StackValue = false); + /// Create a copy of \p Expr by appending the given list of \p Ops to each + /// instance of the operand `DIOpArg(ArgNo, OldArgType)`, updating OldArgType + /// to \p NewArgType if non-null. This is used to modify a specific location + /// used by \p Expr, such as when salvaging that location. + static DIExpression *appendNewOpsToArg(const DIExpression *Expr, + ArrayRef Ops, + unsigned ArgNo, + Type *NewArgType = nullptr); + + /// Create a copy of \p Expr updated to reflect that the debug operands + /// whose indexes are set in \p SpilledOpIndexes were spilled to the stack, + /// which is in the \p SpillAddrSpace address space. + /// + /// Handles both New and Old expressions, including Old expressions without + /// an explicit DW_OP_LLVM_arg. + static const DIExpression *spillArgs(const DIExpression *Expr, + SmallBitVector SpilledOpIndexes, + unsigned SpillAddrSpace); + + /// Create a copy of \p Expr with an explicit indirection if \p IsIndirect, in + /// preparation for changing the referring intrinsic from one with the concept + /// of "IsIndirect" to one without it. + /// + /// Handles both Old and New expressions, being a no-op for New expressions + /// which always include indirection explicitly. + static const DIExpression *foldIntrinsicIndirection(const DIExpression *Expr, + bool IsIndirect); + + /// Create a copy of \p Expr updated to be suitable for use by DBG_INSTR_REF. + static const DIExpression *convertForInstrRef(const DIExpression *Expr, + bool IsIndirect); + /// Create a copy of \p Expr with each instance of /// `DW_OP_LLVM_arg, \p OldArg` replaced with `DW_OP_LLVM_arg, \p NewArg`, /// and each instance of `DW_OP_LLVM_arg, Arg` with `DW_OP_LLVM_arg, Arg - 1` @@ -3831,6 +4426,137 @@ template <> struct DenseMapInfo { static bool isEqual(const FragInfo &A, const FragInfo &B) { return A == B; } }; +template struct MDNodeKeyImpl; + +/// Mutable buffer to manipulate debug info expressions. +/// +/// Example of creating a new expression from scratch: +/// +/// LLVMContext Ctx; +/// +/// DIExprBuilder Builder(Ctx); +/// Builder.append().intoExpr(); +/// +/// Example of modifying an expression: +/// +/// DIExpr *Expr = ...; +/// ... +/// DIExpr *NewExpr = Expr.builder() +/// .append(DIOp::InPlaceDeref) +/// .intoExpr(); +/// +/// Despite the name, it supports creating both DIExpr and DIOp-based +/// ("NewElements") DIExpression nodes. +class DIExprBuilder { + LLVMContext &C; + SmallVector Elements; +#ifndef NDEBUG + bool StateIsUnspecified = false; +#endif +public: + /// Create a builder for a new, initially empty expression. + explicit DIExprBuilder(LLVMContext &C); + /// Create a builder for a new expression for the sequence of ops in \p IL. + explicit DIExprBuilder(LLVMContext &C, + std::initializer_list IL); + /// Create a builder for a new expression for the sequence of ops in \p V. + explicit DIExprBuilder(LLVMContext &C, ArrayRef V); + /// Create a builder for a new expression, initially a copy of \p E. + explicit DIExprBuilder(const DIExpression &E); + + class Iterator + : public iterator_facade_base { + friend DIExprBuilder; + DIOp::Variant *Op = nullptr; + Iterator(DIOp::Variant *Op) : Op(Op) {} + + public: + Iterator() = delete; + Iterator(const Iterator &) = default; + Iterator &operator=(const Iterator &) = default; + bool operator==(const Iterator &R) const { return R.Op == Op; } + DIOp::Variant &operator*() const { return *Op; } + friend iterator_facade_base::difference_type operator-(Iterator LHS, + Iterator RHS) { + return LHS.Op - RHS.Op; + } + Iterator &operator+=(iterator_facade_base::difference_type D) { + Op += D; + return *this; + } + Iterator &operator-=(iterator_facade_base::difference_type D) { + Op -= D; + return *this; + } + }; + + Iterator begin() { return Elements.begin(); } + Iterator end() { return Elements.end(); } + iterator_range range() { return make_range(begin(), end()); } + + Iterator insert(Iterator I, DIOp::Variant O); + + template + Iterator insert(Iterator I, ArgsT &&...Args) { + // FIXME: SmallVector doesn't define an ::emplace(iterator, ...) + return Elements.insert( + I.Op, DIOp::Variant{std::in_place_type, std::forward(Args)...}); + } + + template Iterator insert(Iterator I, RangeTy &&R) { + return Elements.insert(I.Op, R.begin(), R.end()); + } + + template Iterator insert(Iterator I, ItTy &&From, ItTy &&To) { + return Elements.insert(I.Op, std::forward(From), + std::forward(To)); + } + + Iterator insert(Iterator I, std::initializer_list IL) { + return Elements.insert(I.Op, IL.begin(), IL.end()); + } + + /// Appends \p O to the expression being built. + DIExprBuilder &append(DIOp::Variant O); + + /// Appends a new DIOp of type T to the expression being built. The new + /// DIOp is constructed in-place by forwarding the provided arguments Args. + template + DIExprBuilder &append(ArgsT &&...Args) { + Elements.emplace_back(std::in_place_type, std::forward(Args)...); + return *this; + } + + Iterator erase(Iterator I); + Iterator erase(Iterator From, Iterator To); + + /// Returns true if the expression being built contains DIOp of type T, + /// false otherwise. + template bool contains() const { + return any_of(Elements, + [](auto &&E) { return std::holds_alternative(E); }); + } + + /// Update the expression to reflect the removal of one level of indirection + /// from the value acting as the referrer. + /// + /// The referrer must be of pointer type, as the expression is logically + /// updated by replacing the @c DIOpReferrer result type with its pointee + /// type, provided as @c PointeeType, and inserting @p + /// DIOpAddrOf() after it. + /// + /// Returns @c *this to permit chaining with other methods. + DIExprBuilder &removeReferrerIndirection(Type *PointeeType); + + /// Get the uniqued, immutable expression metadata from the current state + /// of the builder. + /// + /// This leaves the Builder in a valid but unspecified state, as if it were + /// moved from. + DIExpression *intoExpression(); +}; + /// Holds a DIExpression and keeps track of how many operands have been consumed /// so far. class DIExpressionCursor { @@ -3920,9 +4646,10 @@ class DIGlobalVariable : public DIVariable { bool IsDefinition; DIGlobalVariable(LLVMContext &C, StorageType Storage, unsigned Line, - bool IsLocalToUnit, bool IsDefinition, uint32_t AlignInBits, - ArrayRef Ops) - : DIVariable(C, DIGlobalVariableKind, Storage, Line, Ops, AlignInBits), + bool IsLocalToUnit, bool IsDefinition, dwarf::MemorySpace MS, + uint32_t AlignInBits, ArrayRef Ops) + : DIVariable(C, DIGlobalVariableKind, Storage, Line, Ops, MS, + AlignInBits), IsLocalToUnit(IsLocalToUnit), IsDefinition(IsDefinition) {} ~DIGlobalVariable() = default; @@ -3931,12 +4658,12 @@ class DIGlobalVariable : public DIVariable { StringRef LinkageName, DIFile *File, unsigned Line, DIType *Type, bool IsLocalToUnit, bool IsDefinition, DIDerivedType *StaticDataMemberDeclaration, MDTuple *TemplateParams, - uint32_t AlignInBits, DINodeArray Annotations, StorageType Storage, - bool ShouldCreate = true) { + dwarf::MemorySpace MS, uint32_t AlignInBits, DINodeArray Annotations, + StorageType Storage, bool ShouldCreate = true) { return getImpl(Context, Scope, getCanonicalMDString(Context, Name), getCanonicalMDString(Context, LinkageName), File, Line, Type, IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration, - cast_or_null(TemplateParams), AlignInBits, + cast_or_null(TemplateParams), MS, AlignInBits, Annotations.get(), Storage, ShouldCreate); } LLVM_ABI static DIGlobalVariable * @@ -3944,34 +4671,38 @@ class DIGlobalVariable : public DIVariable { MDString *LinkageName, Metadata *File, unsigned Line, Metadata *Type, bool IsLocalToUnit, bool IsDefinition, Metadata *StaticDataMemberDeclaration, Metadata *TemplateParams, - uint32_t AlignInBits, Metadata *Annotations, StorageType Storage, - bool ShouldCreate = true); + dwarf::MemorySpace MS, uint32_t AlignInBits, Metadata *Annotations, + StorageType Storage, bool ShouldCreate = true); TempDIGlobalVariable cloneImpl() const { return getTemporary(getContext(), getScope(), getName(), getLinkageName(), getFile(), getLine(), getType(), isLocalToUnit(), isDefinition(), getStaticDataMemberDeclaration(), - getTemplateParams(), getAlignInBits(), - getAnnotations()); + getTemplateParams(), getDWARFMemorySpace(), + getAlignInBits(), getAnnotations()); } public: - DEFINE_MDNODE_GET( - DIGlobalVariable, - (DIScope * Scope, StringRef Name, StringRef LinkageName, DIFile *File, - unsigned Line, DIType *Type, bool IsLocalToUnit, bool IsDefinition, - DIDerivedType *StaticDataMemberDeclaration, MDTuple *TemplateParams, - uint32_t AlignInBits, DINodeArray Annotations), - (Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, IsDefinition, - StaticDataMemberDeclaration, TemplateParams, AlignInBits, Annotations)) - DEFINE_MDNODE_GET( - DIGlobalVariable, - (Metadata * Scope, MDString *Name, MDString *LinkageName, Metadata *File, - unsigned Line, Metadata *Type, bool IsLocalToUnit, bool IsDefinition, - Metadata *StaticDataMemberDeclaration, Metadata *TemplateParams, - uint32_t AlignInBits, Metadata *Annotations), - (Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, IsDefinition, - StaticDataMemberDeclaration, TemplateParams, AlignInBits, Annotations)) + DEFINE_MDNODE_GET(DIGlobalVariable, + (DIScope * Scope, StringRef Name, StringRef LinkageName, + DIFile *File, unsigned Line, DIType *Type, + bool IsLocalToUnit, bool IsDefinition, + DIDerivedType *StaticDataMemberDeclaration, + MDTuple *TemplateParams, dwarf::MemorySpace MS, + uint32_t AlignInBits, DINodeArray Annotations), + (Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, + IsDefinition, StaticDataMemberDeclaration, TemplateParams, + MS, AlignInBits, Annotations)) + DEFINE_MDNODE_GET(DIGlobalVariable, + (Metadata * Scope, MDString *Name, MDString *LinkageName, + Metadata *File, unsigned Line, Metadata *Type, + bool IsLocalToUnit, bool IsDefinition, + Metadata *StaticDataMemberDeclaration, + Metadata *TemplateParams, dwarf::MemorySpace MS, + uint32_t AlignInBits, Metadata *Annotations), + (Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, + IsDefinition, StaticDataMemberDeclaration, TemplateParams, + MS, AlignInBits, Annotations)) TempDIGlobalVariable clone() const { return cloneImpl(); } @@ -4066,9 +4797,9 @@ class DILocalVariable : public DIVariable { DIFlags Flags; DILocalVariable(LLVMContext &C, StorageType Storage, unsigned Line, - unsigned Arg, DIFlags Flags, uint32_t AlignInBits, - ArrayRef Ops) - : DIVariable(C, DILocalVariableKind, Storage, Line, Ops, AlignInBits), + unsigned Arg, DIFlags Flags, dwarf::MemorySpace MS, + uint32_t AlignInBits, ArrayRef Ops) + : DIVariable(C, DILocalVariableKind, Storage, Line, Ops, MS, AlignInBits), Arg(Arg), Flags(Flags) { assert(Arg < (1 << 16) && "DILocalVariable: Arg out of range"); } @@ -4077,37 +4808,40 @@ class DILocalVariable : public DIVariable { static DILocalVariable *getImpl(LLVMContext &Context, DIScope *Scope, StringRef Name, DIFile *File, unsigned Line, DIType *Type, unsigned Arg, DIFlags Flags, - uint32_t AlignInBits, DINodeArray Annotations, - StorageType Storage, + dwarf::MemorySpace MS, uint32_t AlignInBits, + DINodeArray Annotations, StorageType Storage, bool ShouldCreate = true) { return getImpl(Context, Scope, getCanonicalMDString(Context, Name), File, - Line, Type, Arg, Flags, AlignInBits, Annotations.get(), + Line, Type, Arg, Flags, MS, AlignInBits, Annotations.get(), Storage, ShouldCreate); } LLVM_ABI static DILocalVariable * getImpl(LLVMContext &Context, Metadata *Scope, MDString *Name, Metadata *File, unsigned Line, Metadata *Type, unsigned Arg, DIFlags Flags, - uint32_t AlignInBits, Metadata *Annotations, StorageType Storage, - bool ShouldCreate = true); + dwarf::MemorySpace MS, uint32_t AlignInBits, Metadata *Annotations, + StorageType Storage, bool ShouldCreate = true); TempDILocalVariable cloneImpl() const { return getTemporary(getContext(), getScope(), getName(), getFile(), getLine(), getType(), getArg(), getFlags(), - getAlignInBits(), getAnnotations()); + getDWARFMemorySpace(), getAlignInBits(), + getAnnotations()); } public: DEFINE_MDNODE_GET(DILocalVariable, (DILocalScope * Scope, StringRef Name, DIFile *File, unsigned Line, DIType *Type, unsigned Arg, DIFlags Flags, - uint32_t AlignInBits, DINodeArray Annotations), - (Scope, Name, File, Line, Type, Arg, Flags, AlignInBits, + dwarf::MemorySpace MS, uint32_t AlignInBits, + DINodeArray Annotations), + (Scope, Name, File, Line, Type, Arg, Flags, MS, AlignInBits, Annotations)) DEFINE_MDNODE_GET(DILocalVariable, (Metadata * Scope, MDString *Name, Metadata *File, unsigned Line, Metadata *Type, unsigned Arg, DIFlags Flags, - uint32_t AlignInBits, Metadata *Annotations), - (Scope, Name, File, Line, Type, Arg, Flags, AlignInBits, + dwarf::MemorySpace MS, uint32_t AlignInBits, + Metadata *Annotations), + (Scope, Name, File, Line, Type, Arg, Flags, MS, AlignInBits, Annotations)) TempDILocalVariable clone() const { return cloneImpl(); } diff --git a/llvm/include/llvm/IR/GlobalVariable.h b/llvm/include/llvm/IR/GlobalVariable.h index d1d42cebc1352..719f886346063 100644 --- a/llvm/include/llvm/IR/GlobalVariable.h +++ b/llvm/include/llvm/IR/GlobalVariable.h @@ -35,6 +35,7 @@ class Constant; class Module; template class SymbolTableListTraits; +class DIGlobalVariable; class DIGlobalVariableExpression; class GlobalVariable : public GlobalObject, public ilist_node { @@ -209,6 +210,12 @@ class GlobalVariable : public GlobalObject, public ilist_node { LLVM_ABI void getDebugInfo(SmallVectorImpl &GVs) const; + /// Attach a DIGlobalVariable. + void addDebugInfo(DIGlobalVariable *GV); + + /// Fill the vector with all debug info attachements. + void getDebugInfo(SmallVectorImpl &GVs) const; + /// Add attribute to this global. void addAttribute(Attribute::AttrKind Kind) { Attrs = Attrs.addAttribute(getContext(), Kind); diff --git a/llvm/include/llvm/IR/InstVisitor.h b/llvm/include/llvm/IR/InstVisitor.h index 8e4dc647e5230..04d7b800af0fa 100644 --- a/llvm/include/llvm/IR/InstVisitor.h +++ b/llvm/include/llvm/IR/InstVisitor.h @@ -200,6 +200,13 @@ class InstVisitor { RetTy visitCatchPadInst(CatchPadInst &I) { DELEGATE(FuncletPadInst); } RetTy visitFreezeInst(FreezeInst &I) { DELEGATE(Instruction); } + // Handle the special intrinsic instruction classes. + RetTy visitDbgDeclareInst(DbgDeclareInst &I) { DELEGATE(DbgVariableIntrinsic);} + RetTy visitDbgValueInst(DbgValueInst &I) { DELEGATE(DbgVariableIntrinsic);} + RetTy visitDbgVariableIntrinsic(DbgVariableIntrinsic &I) + { DELEGATE(DbgInfoIntrinsic);} + RetTy visitDbgLabelInst(DbgLabelInst &I) { DELEGATE(DbgInfoIntrinsic);} + RetTy visitDbgInfoIntrinsic(DbgInfoIntrinsic &I){ DELEGATE(IntrinsicInst); } RetTy visitMemSetInst(MemSetInst &I) { DELEGATE(MemIntrinsic); } RetTy visitMemSetPatternInst(MemSetPatternInst &I) { DELEGATE(IntrinsicInst); @@ -280,6 +287,9 @@ class InstVisitor { if (const Function *F = I.getCalledFunction()) { switch (F->getIntrinsicID()) { default: DELEGATE(IntrinsicInst); + case Intrinsic::dbg_declare: DELEGATE(DbgDeclareInst); + case Intrinsic::dbg_value: DELEGATE(DbgValueInst); + case Intrinsic::dbg_label: DELEGATE(DbgLabelInst); case Intrinsic::memcpy: case Intrinsic::memcpy_inline: DELEGATE(MemCpyInst); diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index 4d59ee8676b9e..73f5e9feeefd3 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -1447,6 +1447,12 @@ let IntrProperties = [IntrNoMem, IntrSpeculatable] in { llvm_metadata_ty]>; def int_dbg_label : DefaultAttrsIntrinsic<[], [llvm_metadata_ty]>; + def int_dbg_def : DefaultAttrsIntrinsic<[], + [llvm_metadata_ty, + llvm_metadata_ty]>; + def int_dbg_kill : DefaultAttrsIntrinsic<[], + [llvm_metadata_ty]>; + } //===------------------ Exception Handling Intrinsics----------------------===// diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 8e35109061792..e573b2be73941 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -898,6 +898,31 @@ def int_amdgcn_bitop3 : [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem, IntrSpeculatable, ImmArg>]>; +class AMDGPUGlobalStore : Intrinsic < + [], + [global_ptr_ty, // Base global pointer to store to + llvm_v4i32_ty, // Data to store + llvm_metadata_ty], // Scope + [ IntrWriteMem, WriteOnly>, NoCapture>, + IntrWillReturn, IntrNoCallback, IntrNoFree ], + "", + [SDNPMemOperand, SDNPMayStore] +>; + +def int_amdgcn_global_store_b128 : AMDGPUGlobalStore; + +class AMDGPUGlobalLoad : Intrinsic < + [llvm_v4i32_ty], + [global_ptr_ty, // Base global pointer to load from + llvm_metadata_ty], // Scope + [ IntrReadMem, ReadOnly>, NoCapture>, IntrWillReturn, + IntrNoCallback, IntrNoFree ], + "", + [SDNPMemOperand, SDNPMayLoad] +>; + +def int_amdgcn_global_load_b128 : AMDGPUGlobalLoad; + } // TargetPrefix = "amdgcn" // New-style image intrinsics diff --git a/llvm/include/llvm/IR/Metadata.def b/llvm/include/llvm/IR/Metadata.def index 511bf48707f00..6b4be82a65453 100644 --- a/llvm/include/llvm/IR/Metadata.def +++ b/llvm/include/llvm/IR/Metadata.def @@ -105,6 +105,7 @@ HANDLE_SPECIALIZED_MDNODE_LEAF_UNIQUABLE(DIModule) HANDLE_SPECIALIZED_MDNODE_BRANCH(DITemplateParameter) HANDLE_SPECIALIZED_MDNODE_LEAF_UNIQUABLE(DITemplateTypeParameter) HANDLE_SPECIALIZED_MDNODE_LEAF_UNIQUABLE(DITemplateValueParameter) +HANDLE_SPECIALIZED_MDNODE_BRANCH(DIObject) HANDLE_SPECIALIZED_MDNODE_BRANCH(DIVariable) HANDLE_SPECIALIZED_MDNODE_LEAF_UNIQUABLE(DIGlobalVariable) HANDLE_SPECIALIZED_MDNODE_LEAF_UNIQUABLE(DILocalVariable) diff --git a/llvm/include/llvm/IR/Metadata.h b/llvm/include/llvm/IR/Metadata.h index 85a7f8fd373c0..7ae9c730ecf66 100644 --- a/llvm/include/llvm/IR/Metadata.h +++ b/llvm/include/llvm/IR/Metadata.h @@ -51,7 +51,11 @@ template class StringMapEntryStorage; class Type; enum LLVMConstants : uint32_t { - DEBUG_METADATA_VERSION = 3 // Current debug info version number. + // Current debug info version number. + DEBUG_METADATA_VERSION = 3, + // Debug info version number used for DWARF extensions for + // heterogeneous debugging. + DEBUG_METADATA_VERSION_HETEROGENEOUS_DWARF = 4 }; /// Magic number in the value profile metadata showing a target has been diff --git a/llvm/include/llvm/LTO/Config.h b/llvm/include/llvm/LTO/Config.h index 50e143c518213..4e08e78545701 100644 --- a/llvm/include/llvm/LTO/Config.h +++ b/llvm/include/llvm/LTO/Config.h @@ -195,6 +195,8 @@ struct Config { /// with llvm-lto2. std::unique_ptr ResolutionFile; + std::string AsmFile; + /// Tunable parameters for passes in the default pipelines. PipelineTuningOptions PTO; diff --git a/llvm/include/llvm/MC/MCAsmInfo.h b/llvm/include/llvm/MC/MCAsmInfo.h index 7a2e9ad154f01..3b3c26fee02ec 100644 --- a/llvm/include/llvm/MC/MCAsmInfo.h +++ b/llvm/include/llvm/MC/MCAsmInfo.h @@ -392,6 +392,11 @@ class LLVM_ABI MCAsmInfo { /// location is allowed. bool SupportsExtendedDwarfLocDirective = true; + /// True if the target supports the extensions defined at + /// https://llvm.org/docs/AMDGPUDwarfProposalForHeterogeneousDebugging.html. + /// Defaults to false. + bool SupportsHeterogeneousDebuggingExtensions = false; + //===--- Prologue State ----------------------------------------------===// std::vector InitialFrameState; @@ -630,6 +635,10 @@ class LLVM_ABI MCAsmInfo { bool doesSupportDebugInformation() const { return SupportsDebugInformation; } + bool doesSupportExceptionHandling() const { + return ExceptionsType != ExceptionHandling::None; + } + ExceptionHandling getExceptionHandlingType() const { return ExceptionsType; } WinEH::EncodingType getWinEHEncodingType() const { return WinEHEncodingType; } @@ -666,6 +675,9 @@ class LLVM_ABI MCAsmInfo { bool supportsExtendedDwarfLocDirective() const { return SupportsExtendedDwarfLocDirective; } + bool supportsHeterogeneousDebuggingExtensions() const { + return SupportsHeterogeneousDebuggingExtensions; + } bool usesDwarfFileAndLocDirectives() const { return !IsAIX; } diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h index 9944a9a92ab1f..c457a2be63dd0 100644 --- a/llvm/include/llvm/MC/MCDwarf.h +++ b/llvm/include/llvm/MC/MCDwarf.h @@ -529,6 +529,42 @@ class MCCFIInstruction { OpGnuArgsSize, OpLabel, OpValOffset, + OpLLVMRegisterPair, + OpLLVMVectorRegisters, + OpLLVMVectorOffset, + OpLLVMVectorRegisterMask, + }; + + /// Some extra fields used when Operation is OpLLVMRegisterPair. + struct RegisterPairExtraFields { + unsigned Reg1, Reg2; + unsigned Reg1SizeInBits, Reg2SizeInBits; + }; + + struct VectorRegisterWithLane { + unsigned Register; + unsigned Lane; + unsigned SizeInBits; + }; + + /// Some extra fields used when Operation is OpLLVMVectorRegisters. + struct VectorRegistersExtraFields { + std::vector VectorRegisters; + }; + + /// Some extra fields used when Operation is OpLLVMVectorOffset. + struct VectorOffsetExtraFields { + unsigned MaskRegister; + unsigned MaskRegisterSizeInBits; + unsigned RegisterSizeInBits; + }; + + /// Some extra fields used when Operation is OpLLVMVectorRegisterMask. + struct VectorRegisterMaskExtraFields { + unsigned SpillRegister; + unsigned SpillRegisterLaneSizeInBits; + unsigned MaskRegister; + unsigned MaskRegisterSizeInBits; }; private: @@ -554,6 +590,14 @@ class MCCFIInstruction { std::vector Values; std::string Comment; + // FIXME: We could probably save some space and complexity by moving all + // Operation-specific fields to this variant. Leaving them as-is for now to + // avoid a diff with upstream. + std::variant + ExtraFields; + MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int64_t O, SMLoc Loc, StringRef V = "", StringRef Comment = "") : Label(L), Operation(Op), Loc(Loc), Values(V.begin(), V.end()), @@ -573,6 +617,14 @@ class MCCFIInstruction { U.RIA = {R, O, AS}; } + template + MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int O, + ExtraFieldsTy &&ExtraFields, SMLoc Loc) + : Label(L), Operation(Op), Loc(Loc), + ExtraFields(std::forward(ExtraFields)) { + U.RI = {R, O}; + } + MCCFIInstruction(OpType Op, MCSymbol *L, MCSymbol *CfiLabel, SMLoc Loc) : Label(L), Operation(Op), Loc(Loc) { assert(Op == OpLabel); @@ -710,6 +762,62 @@ class MCCFIInstruction { return MCCFIInstruction(OpLabel, L, CfiLabel, Loc); } + /// .cfi_llvm_register_pair Previous value of Register is saved in R1:R2. + static MCCFIInstruction + createLLVMRegisterPair(MCSymbol *L, unsigned Register, unsigned R1, + unsigned R1SizeInBits, unsigned R2, + unsigned R2SizeInBits, SMLoc Loc = {}) { + RegisterPairExtraFields Extra{R1, R2, R1SizeInBits, R2SizeInBits}; + return MCCFIInstruction(OpLLVMRegisterPair, L, Register, 0, Extra, Loc); + } + + /// .cfi_llvm_vector_registers Previous value of Register is saved in lanes of + /// vector registers. + static MCCFIInstruction + createLLVMVectorRegisters(MCSymbol *L, unsigned Register, + std::vector VectorRegisters, + SMLoc Loc = {}) { + VectorRegistersExtraFields Extra{std::move(VectorRegisters)}; + return MCCFIInstruction(OpLLVMVectorRegisters, L, Register, 0, + std::move(Extra), Loc); + } + + /// .cfi_llvm_vector_offset Previous value of Register is saved at Offset from + /// CFA. MaskRegister specifies the active lanes of register. + static MCCFIInstruction + createLLVMVectorOffset(MCSymbol *L, unsigned Register, + unsigned RegisterSizeInBits, unsigned MaskRegister, + unsigned MaskRegisterSizeInBits, int Offset, + SMLoc Loc = {}) { + VectorOffsetExtraFields Extra{MaskRegister, MaskRegisterSizeInBits, + RegisterSizeInBits}; + return MCCFIInstruction(OpLLVMVectorOffset, L, Register, Offset, Extra, + Loc); + } + + /// .cfi_llvm_vector_register_mask Previous value of Register is saved in + /// SpillRegister, predicated on the value of MaskRegister. + static MCCFIInstruction createLLVMVectorRegisterMask( + MCSymbol *L, unsigned Register, unsigned SpillRegister, + unsigned SpillRegisterLaneSizeInBits, unsigned MaskRegister, + unsigned MaskRegisterSizeInBits, SMLoc Loc = {}) { + VectorRegisterMaskExtraFields Extra{ + SpillRegister, + SpillRegisterLaneSizeInBits, + MaskRegister, + MaskRegisterSizeInBits, + }; + return MCCFIInstruction(OpLLVMVectorRegisterMask, L, Register, 0, + std::move(Extra), Loc); + } + + template ExtraFieldsTy &getExtraFields() { + return std::get(ExtraFields); + } + + template const ExtraFieldsTy &getExtraFields() const { + return std::get(ExtraFields); + } /// .cfi_val_offset Previous value of Register is offset Offset from the /// current CFA register. static MCCFIInstruction createValOffset(MCSymbol *L, unsigned Register, @@ -728,6 +836,9 @@ class MCCFIInstruction { assert(Operation == OpDefCfa || Operation == OpOffset || Operation == OpRestore || Operation == OpUndefined || Operation == OpSameValue || Operation == OpDefCfaRegister || + Operation == OpLLVMVectorRegisters || + Operation == OpLLVMRegisterPair || Operation == OpLLVMVectorOffset || + Operation == OpLLVMVectorRegisterMask || Operation == OpRelOffset || Operation == OpValOffset); return U.RI.Register; } @@ -748,6 +859,7 @@ class MCCFIInstruction { assert(Operation == OpDefCfa || Operation == OpOffset || Operation == OpRelOffset || Operation == OpDefCfaOffset || Operation == OpAdjustCfaOffset || Operation == OpGnuArgsSize || + Operation == OpLLVMVectorOffset || Operation == OpValOffset); return U.RI.Offset; } @@ -764,6 +876,9 @@ class MCCFIInstruction { StringRef getComment() const { return Comment; } SMLoc getLoc() const { return Loc; } + + /// Replaces in place all references to FromReg with ToReg. + void replaceRegister(unsigned FromReg, unsigned ToReg); }; struct MCDwarfFrameInfo { diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h index 79c715e3820a6..4e76aa323eb30 100644 --- a/llvm/include/llvm/MC/MCStreamer.h +++ b/llvm/include/llvm/MC/MCStreamer.h @@ -1012,6 +1012,24 @@ class LLVM_ABI MCStreamer { SMLoc Loc = {}); virtual void emitCFIWindowSave(SMLoc Loc = {}); virtual void emitCFINegateRAState(SMLoc Loc = {}); + virtual void emitCFILLVMRegisterPair(int64_t Register, int64_t R1, + int64_t R1SizeInBits, int64_t R2, + int64_t R2SizeInBits, SMLoc Loc = {}); + virtual void emitCFILLVMVectorRegisters( + int64_t Register, + std::vector VRs, + SMLoc Loc = {}); + virtual void emitCFILLVMVectorOffset(int64_t Register, + int64_t RegisterSizeInBits, + int64_t MaskRegister, + int64_t MaskRegisterSizeInBits, + int64_t Offset, SMLoc Loc = {}); + virtual void + emitCFILLVMVectorRegisterMask(int64_t Register, int64_t SpillRegister, + int64_t SpillRegisterLaneSizeInBits, + int64_t MaskRegister, + int64_t MaskRegisterSizeInBits, SMLoc Loc = {}); + virtual void emitCFINegateRAStateWithPC(SMLoc Loc = {}); virtual void emitCFILabelDirective(SMLoc Loc, StringRef Name); virtual void emitCFIValOffset(int64_t Register, int64_t Offset, diff --git a/llvm/include/llvm/Object/OffloadBinary.h b/llvm/include/llvm/Object/OffloadBinary.h index ac2dbf60e2aec..713fe50b800aa 100644 --- a/llvm/include/llvm/Object/OffloadBinary.h +++ b/llvm/include/llvm/Object/OffloadBinary.h @@ -21,6 +21,8 @@ #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringRef.h" #include "llvm/Object/Binary.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Support/Compression.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Error.h" #include "llvm/Support/MemoryBuffer.h" diff --git a/llvm/include/llvm/Pass.h b/llvm/include/llvm/Pass.h index f3962c3556c95..a7c78e9eec660 100644 --- a/llvm/include/llvm/Pass.h +++ b/llvm/include/llvm/Pass.h @@ -84,7 +84,9 @@ enum class ThinOrFullLTOPhase { /// Full LTO prelink phase. FullLTOPreLink, /// Full LTO postlink (backend compile) phase. - FullLTOPostLink + FullLTOPostLink, + /// Custom LTO postlink (e.g. --lto-newpm-passes=...) + CustomLTOPostLink }; #ifndef NDEBUG diff --git a/llvm/include/llvm/Support/CodeGen.h b/llvm/include/llvm/Support/CodeGen.h index cd1f9167b996d..7d204e6db310c 100644 --- a/llvm/include/llvm/Support/CodeGen.h +++ b/llvm/include/llvm/Support/CodeGen.h @@ -95,6 +95,12 @@ namespace llvm { return std::nullopt; return static_cast(OL); } +#if 0 + /// Get the integer \c ID of \p Level. + inline IDType getID(CodeGenOptLevel::Level Level) { + return static_cast(Level); + } +#endif /// Parse \p C as a single digit integer and get matching \c CodeGenLevel. /// /// Returns std::nullopt if the input is not a valid optimization level. diff --git a/llvm/include/llvm/Support/TypeName.h b/llvm/include/llvm/Support/TypeName.h index 85612650ce897..7e508564c0114 100644 --- a/llvm/include/llvm/Support/TypeName.h +++ b/llvm/include/llvm/Support/TypeName.h @@ -71,8 +71,9 @@ inline LLVM_GET_TYPE_NAME_CONSTEXPR StringRef getTypeName() { LLVM_GET_TYPE_NAME_CONSTEXPR std::string_view Key = "getTypeName<"; LLVM_GET_TYPE_NAME_CONSTEXPR std::string_view GetTypeNameStart = Name.substr(Name.find(Key)); - static_assert(!GetTypeNameStart.empty(), - "Unable to find the template parameter!"); + // TODO: SWDEV-517818 - Changed from static_assert to assert to ensure + // compiler compatibility + assert(!GetTypeNameStart.empty() && "Unable to find the template parameter!"); LLVM_GET_TYPE_NAME_CONSTEXPR std::string_view SubstitutionKey = GetTypeNameStart.substr(Key.size()); @@ -95,8 +96,10 @@ inline LLVM_GET_TYPE_NAME_CONSTEXPR StringRef getTypeName() { : RmPrefixUnion; LLVM_GET_TYPE_NAME_CONSTEXPR auto AnglePos = RmPrefixEnum.rfind('>'); - static_assert(AnglePos != std::string_view::npos, - "Unable to find the closing '>'!"); + // TODO: SWDEV-517818 - Changed from static_assert to assert to ensure + // compiler compatibility + assert(AnglePos != std::string_view::npos && + "Unable to find the closing '>'!"); return RmPrefixEnum.substr(0, AnglePos); #else // No known technique for statically extracting a type name on this compiler. diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index d0fd483a8ddaa..c47f872ad8ffc 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -14,6 +14,7 @@ #define LLVM_TARGET_TARGETMACHINE_H #include "llvm/ADT/StringRef.h" +#include "llvm/BinaryFormat/Dwarf.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/PassManager.h" #include "llvm/Support/Allocator.h" @@ -367,6 +368,15 @@ class LLVM_ABI TargetMachine { return false; } + /// Returns the DWARF address space corresponding to the given LLVM address + /// space, or None if no such mapping exists. + virtual std::optional + mapToDWARFAddrSpace(unsigned LLVMAddrSpace) const { + if (LLVMAddrSpace == DL.getDefaultGlobalsAddressSpace()) + return dwarf::AddressSpace::DW_ASPACE_LLVM_none; + return std::nullopt; + } + void setPGOOption(std::optional PGOOpt) { PGOOption = PGOOpt; } const std::optional &getPGOOption() const { return PGOOption; } diff --git a/llvm/include/llvm/Transforms/Utils/Local.h b/llvm/include/llvm/Transforms/Utils/Local.h index 9acfd872e574b..7ceed39ad1859 100644 --- a/llvm/include/llvm/Transforms/Utils/Local.h +++ b/llvm/include/llvm/Transforms/Utils/Local.h @@ -368,7 +368,7 @@ salvageDebugInfoImpl(Instruction &I, uint64_t CurrentLocOps, /// introducing a use-before-def, it is either salvaged (\ref salvageDebugInfo) /// or deleted. Returns true if any debug users were updated. LLVM_ABI bool replaceAllDbgUsesWith(Instruction &From, Value &To, - Instruction &DomPoint, DominatorTree &DT); + Instruction &DomPoint, const DominatorTree &DT); /// If a terminator in an unreachable basic block has an operand of type /// Instruction, transform it into poison. Return true if any operands diff --git a/llvm/lib/Analysis/CtxProfAnalysis.cpp b/llvm/lib/Analysis/CtxProfAnalysis.cpp index c4abec02e765a..0cde61e4871fc 100644 --- a/llvm/lib/Analysis/CtxProfAnalysis.cpp +++ b/llvm/lib/Analysis/CtxProfAnalysis.cpp @@ -23,6 +23,7 @@ #include "llvm/ProfileData/PGOCtxProfReader.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/MemoryBuffer.h" +#include "llvm/Transforms/Instrumentation/PGOCtxProfLowering.h" #include "llvm/Support/Path.h" #include #include diff --git a/llvm/lib/Analysis/InlineAdvisor.cpp b/llvm/lib/Analysis/InlineAdvisor.cpp index 0fa804f2959e8..f5c374d1584a0 100644 --- a/llvm/lib/Analysis/InlineAdvisor.cpp +++ b/llvm/lib/Analysis/InlineAdvisor.cpp @@ -591,6 +591,7 @@ static inline const char *getLTOPhase(ThinOrFullLTOPhase LTOPhase) { return "prelink"; case (ThinOrFullLTOPhase::ThinLTOPostLink): case (ThinOrFullLTOPhase::FullLTOPostLink): + case (ThinOrFullLTOPhase::CustomLTOPostLink): return "postlink"; } llvm_unreachable("unreachable"); diff --git a/llvm/lib/Analysis/LoopUnrollAnalyzer.cpp b/llvm/lib/Analysis/LoopUnrollAnalyzer.cpp index 9c78e2afaede7..b0c4925cbc5cd 100644 --- a/llvm/lib/Analysis/LoopUnrollAnalyzer.cpp +++ b/llvm/lib/Analysis/LoopUnrollAnalyzer.cpp @@ -39,11 +39,6 @@ bool UnrolledInstAnalyzer::simplifyInstWithSCEV(Instruction *I) { return true; } - // If we have a loop invariant computation, we only need to compute it once. - // Given that, all but the first occurance are free. - if (!IterationNumber->isZero() && SE.isLoopInvariant(S, L)) - return true; - auto *AR = dyn_cast(S); if (!AR || AR->getLoop() != L) return false; diff --git a/llvm/lib/Analysis/ObjCARCInstKind.cpp b/llvm/lib/Analysis/ObjCARCInstKind.cpp index d177ee056a93a..0a307fbf40914 100644 --- a/llvm/lib/Analysis/ObjCARCInstKind.cpp +++ b/llvm/lib/Analysis/ObjCARCInstKind.cpp @@ -185,6 +185,8 @@ static bool isInertIntrinsic(unsigned ID) { case Intrinsic::dbg_declare: case Intrinsic::dbg_value: case Intrinsic::dbg_label: + case Intrinsic::dbg_def: + case Intrinsic::dbg_kill: // Short cut: Some intrinsics obviously don't use ObjC pointers. return true; default: diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp index 7a6c19ece92ac..a4d82a4c6f3b6 100644 --- a/llvm/lib/AsmParser/LLLexer.cpp +++ b/llvm/lib/AsmParser/LLLexer.cpp @@ -631,6 +631,7 @@ lltok::Kind LLLexer::LexIdentifier() { KEYWORD(no_sanitize_address); KEYWORD(no_sanitize_hwaddress); KEYWORD(sanitize_address_dyninit); + KEYWORD(sanitized_padded_global); KEYWORD(ccc); KEYWORD(fastcc); @@ -989,6 +990,7 @@ lltok::Kind LLLexer::LexIdentifier() { DWKEYWORD(OP, DwarfOp); DWKEYWORD(MACINFO, DwarfMacinfo); DWKEYWORD(APPLE_ENUM_KIND, DwarfEnumKind); + DWKEYWORD(MSPACE_LLVM, DwarfMSpaceLLVM); #undef DWKEYWORD @@ -1034,6 +1036,11 @@ lltok::Kind LLLexer::LexIdentifier() { return lltok::NameTableKind; } + if (Keyword.starts_with("DIOp")) { + StrVal.assign(Keyword.begin(), Keyword.end()); + return lltok::DIOp; + } + if (Keyword == "Binary" || Keyword == "Decimal" || Keyword == "Rational") { StrVal.assign(Keyword.begin(), Keyword.end()); return lltok::FixedPointKind; diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index 5164cec33e6f5..54e5455bce458 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -3067,6 +3067,16 @@ bool LLParser::parseType(Type *&Result, const Twine &Msg, bool AllowVoid) { } } +/// parseFirstClassType - parse a first class type. +bool LLParser::parseFirstClassType(Type *&Result) { + LocTy TyLoc; + if (parseType(Result, TyLoc)) + return true; + if (!Result->isFirstClassType()) + return error(TyLoc, "expected first class type"); + return false; +} + /// parseParameterList /// ::= '(' ')' /// ::= '(' Arg (',' Arg)* ')' @@ -4773,6 +4783,16 @@ struct DwarfEnumKindField : public MDUnsignedField { dwarf::DW_APPLE_ENUM_KIND_max) {} }; +struct DwarfMSpaceField : public MDUnsignedField { + dwarf::MemorySpace val() const { + return static_cast(Val); + } + + DwarfMSpaceField() + : MDUnsignedField(dwarf::DW_MSPACE_LLVM_none, + dwarf::DW_MSPACE_LLVM_hi_user) {} +}; + struct EmissionKindField : public MDUnsignedField { EmissionKindField() : MDUnsignedField(0, DICompileUnit::LastEmissionKind) {} }; @@ -5057,6 +5077,26 @@ bool LLParser::parseMDField(LocTy Loc, StringRef Name, DwarfCCField &Result) { return false; } +template <> +bool LLParser::parseMDField(LocTy Loc, StringRef Name, + DwarfMSpaceField &Result) { + if (Lex.getKind() == lltok::APSInt) + return parseMDField(Loc, Name, static_cast(Result)); + + if (Lex.getKind() != lltok::DwarfMSpaceLLVM) + return tokError("expected DWARF memory space"); + + unsigned MS = dwarf::getMemorySpace(Lex.getStrVal()); + if (!MS) + return tokError("invalid DWARF memory space" + Twine(" '") + + Lex.getStrVal() + "'"); + assert(MS <= dwarf::DW_MSPACE_LLVM_hi_user && + "Expected valid DWARF memorySpace"); + Result.assign(MS); + Lex.Lex(); + return false; +} + template <> bool LLParser::parseMDField(LocTy Loc, StringRef Name, EmissionKindField &Result) { @@ -5707,7 +5747,8 @@ bool LLParser::parseDIStringType(MDNode *&Result, bool IsDistinct) { /// ::= !DIDerivedType(tag: DW_TAG_pointer_type, name: "int", file: !0, /// line: 7, scope: !1, baseType: !2, size: 32, /// align: 32, offset: 0, flags: 0, extraData: !3, -/// dwarfAddressSpace: 3, ptrAuthKey: 1, +/// addressSpace: 3, memorySpace: DW_MSPACE_LLVM_none +/// ptrAuthKey: 1, /// ptrAuthIsAddressDiscriminated: true, /// ptrAuthExtraDiscriminator: 0x1234, /// ptrAuthIsaPointer: 1, ptrAuthAuthenticatesNullValues:1 @@ -5725,7 +5766,8 @@ bool LLParser::parseDIDerivedType(MDNode *&Result, bool IsDistinct) { OPTIONAL(offset, MDUnsignedOrMDField, (0, UINT64_MAX)); \ OPTIONAL(flags, DIFlagField, ); \ OPTIONAL(extraData, MDField, ); \ - OPTIONAL(dwarfAddressSpace, MDUnsignedField, (UINT32_MAX, UINT32_MAX)); \ + OPTIONAL(addressSpace, MDUnsignedField, (UINT32_MAX, UINT32_MAX)); \ + OPTIONAL(memorySpace, DwarfMSpaceField, ); \ OPTIONAL(annotations, MDField, ); \ OPTIONAL(ptrAuthKey, MDUnsignedField, (0, 7)); \ OPTIONAL(ptrAuthIsAddressDiscriminated, MDBoolField, ); \ @@ -5736,8 +5778,9 @@ bool LLParser::parseDIDerivedType(MDNode *&Result, bool IsDistinct) { #undef VISIT_MD_FIELDS std::optional DWARFAddressSpace; - if (dwarfAddressSpace.Val != UINT32_MAX) - DWARFAddressSpace = dwarfAddressSpace.Val; + + if (addressSpace.Val != UINT32_MAX) + DWARFAddressSpace = addressSpace.Val; std::optional PtrAuthData; if (ptrAuthKey.Val) PtrAuthData.emplace( @@ -5749,6 +5792,7 @@ bool LLParser::parseDIDerivedType(MDNode *&Result, bool IsDistinct) { DIDerivedType, (Context, tag.Val, name.Val, file.Val, line.Val, scope.Val, baseType.Val, size.getValueAsMetadata(Context), align.Val, offset.getValueAsMetadata(Context), DWARFAddressSpace, + memorySpace.val(), PtrAuthData, flags.Val, extraData.Val, annotations.Val)); return false; } @@ -6163,17 +6207,17 @@ bool LLParser::parseDIGlobalVariable(MDNode *&Result, bool IsDistinct) { OPTIONAL(isDefinition, MDBoolField, (true)); \ OPTIONAL(templateParams, MDField, ); \ OPTIONAL(declaration, MDField, ); \ + OPTIONAL(memorySpace, DwarfMSpaceField, ); \ OPTIONAL(align, MDUnsignedField, (0, UINT32_MAX)); \ OPTIONAL(annotations, MDField, ); PARSE_MD_FIELDS(); #undef VISIT_MD_FIELDS - Result = - GET_OR_DISTINCT(DIGlobalVariable, - (Context, scope.Val, name.Val, linkageName.Val, file.Val, - line.Val, type.Val, isLocal.Val, isDefinition.Val, - declaration.Val, templateParams.Val, align.Val, - annotations.Val)); + Result = GET_OR_DISTINCT( + DIGlobalVariable, + (Context, scope.Val, name.Val, linkageName.Val, file.Val, line.Val, + type.Val, isLocal.Val, isDefinition.Val, declaration.Val, + templateParams.Val, memorySpace.val(), align.Val, annotations.Val)); return false; } @@ -6193,6 +6237,7 @@ bool LLParser::parseDILocalVariable(MDNode *&Result, bool IsDistinct) { OPTIONAL(line, LineField, ); \ OPTIONAL(type, MDField, ); \ OPTIONAL(flags, DIFlagField, ); \ + OPTIONAL(memorySpace, DwarfMSpaceField, ); \ OPTIONAL(align, MDUnsignedField, (0, UINT32_MAX)); \ OPTIONAL(annotations, MDField, ); PARSE_MD_FIELDS(); @@ -6200,8 +6245,8 @@ bool LLParser::parseDILocalVariable(MDNode *&Result, bool IsDistinct) { Result = GET_OR_DISTINCT(DILocalVariable, (Context, scope.Val, name.Val, file.Val, line.Val, - type.Val, arg.Val, flags.Val, align.Val, - annotations.Val)); + type.Val, arg.Val, flags.Val, memorySpace.val(), + align.Val, annotations.Val)); return false; } @@ -6229,12 +6274,154 @@ bool LLParser::parseDILabel(MDNode *&Result, bool IsDistinct) { return false; } +// Common parser for both DIExpr and DIOp-based ("NewElements") DIExpression. +// Begins parsing assuming the name and open parenthesis has been parsed +// already, and populates Result with the appropriate metadata based on +// IsDIExpr. +// +// An empty DIExpr is permitted (although currently has no use), but an empty +// DIOp-based DIExpression is not as at least one DIOp token is required to +// disambiguate with an empty "OldElements" DIExpression. +bool LLParser::parseDIOpExpression(MDNode *&Result) { + DIExprBuilder Builder(Context); + if (Lex.getKind() != lltok::rparen) + do { + if (Lex.getKind() != lltok::DIOp) + return tokError("expected DIOp"); + std::string Name = Lex.getStrVal(); + Lex.Lex(); + if (parseToken(lltok::lparen, "expected '(' here")) + return true; + if (Name == DIOp::Referrer::getAsmName()) { + Type *Ty = nullptr; + if (parseFirstClassType(Ty)) + return true; + Builder.append(Ty); + } else if (Name == DIOp::Arg::getAsmName()) { + uint32_t I; + Type *Ty = nullptr; + if (parseUInt32(I)) + return true; + if (parseToken(lltok::comma, "expected ',' here")) + return true; + if (parseFirstClassType(Ty)) + return true; + Builder.append(I, Ty); + } else if (Name == DIOp::TypeObject::getAsmName()) { + Type *Ty = nullptr; + if (parseFirstClassType(Ty)) + return true; + Builder.append(Ty); + } else if (Name == DIOp::Constant::getAsmName()) { + Type *Ty = nullptr; + Constant *C = nullptr; + if (parseFirstClassType(Ty)) + return true; + LocTy ValLoc = Lex.getLoc(); + if (parseConstantValue(Ty, C)) + return true; + if (!isa(C)) + return error(ValLoc, "expected constant data"); + Builder.append(cast(C)); + } else if (Name == DIOp::Convert::getAsmName()) { + Type *Ty = nullptr; + if (parseFirstClassType(Ty)) + return true; + Builder.append(Ty); + } else if (Name == DIOp::ZExt::getAsmName()) { + Type *Ty = nullptr; + if (parseFirstClassType(Ty)) + return true; + Builder.append(Ty); + } else if (Name == DIOp::SExt::getAsmName()) { + Type *Ty = nullptr; + if (parseFirstClassType(Ty)) + return true; + Builder.append(Ty); + } else if (Name == DIOp::Reinterpret::getAsmName()) { + Type *Ty = nullptr; + if (parseFirstClassType(Ty)) + return true; + Builder.append(Ty); + } else if (Name == DIOp::BitOffset::getAsmName()) { + Type *Ty = nullptr; + if (parseFirstClassType(Ty)) + return true; + Builder.append(Ty); + } else if (Name == DIOp::ByteOffset::getAsmName()) { + Type *Ty = nullptr; + if (parseFirstClassType(Ty)) + return true; + Builder.append(Ty); + } else if (Name == DIOp::Composite::getAsmName()) { + uint32_t I; + Type *Ty = nullptr; + if (parseUInt32(I)) + return true; + if (parseToken(lltok::comma, "expected ',' here")) + return true; + if (parseFirstClassType(Ty)) + return true; + Builder.append(I, Ty); + } else if (Name == DIOp::Extend::getAsmName()) { + uint32_t I; + if (parseUInt32(I)) + return true; + Builder.append(I); + } else if (Name == DIOp::AddrOf::getAsmName()) { + uint32_t I; + if (parseUInt32(I)) + return true; + Builder.append(I); + } else if (Name == DIOp::Deref::getAsmName()) { + Type *Ty = nullptr; + if (parseFirstClassType(Ty)) + return true; + Builder.append(Ty); + } else if (Name == DIOp::PushLane::getAsmName()) { + Type *Ty = nullptr; + if (parseFirstClassType(Ty)) + return true; + Builder.append(Ty); + } else if (Name == DIOp::Fragment::getAsmName()) { + uint32_t BitOffset, BitSize; + if (parseUInt32(BitOffset)) + return true; + if (parseToken(lltok::comma, "expected ',' here")) + return true; + if (parseUInt32(BitSize)) + return true; + Builder.append(BitOffset, BitSize); + } +#define HANDLE_OP0(NAME) \ + else if (Name == DIOp::NAME::getAsmName()) { \ + Builder.append(); \ + } +#include "llvm/IR/DIExprOps.def" +#undef HANDLE_OP0 + else { + llvm_unreachable("unhandled DIOp"); + } + if (parseToken(lltok::rparen, "expected ')' here")) + return true; + } while (EatIfPresent(lltok::comma)); + + if (parseToken(lltok::rparen, "expected ')' here")) + return true; + + Result = Builder.intoExpression(); + return false; +} + /// parseDIExpressionBody: /// ::= (0, 7, -1) bool LLParser::parseDIExpressionBody(MDNode *&Result, bool IsDistinct) { if (parseToken(lltok::lparen, "expected '(' here")) return true; + if (Lex.getKind() == lltok::DIOp) + return parseDIOpExpression(Result); + SmallVector Elements; if (Lex.getKind() != lltok::rparen) do { diff --git a/llvm/lib/BinaryFormat/Dwarf.cpp b/llvm/lib/BinaryFormat/Dwarf.cpp index 55fa2df632bfa..4a5d1b21db06d 100644 --- a/llvm/lib/BinaryFormat/Dwarf.cpp +++ b/llvm/lib/BinaryFormat/Dwarf.cpp @@ -159,6 +159,8 @@ StringRef llvm::dwarf::OperationEncodingString(unsigned Encoding) { return "DW_OP_LLVM_extract_bits_sext"; case DW_OP_LLVM_extract_bits_zext: return "DW_OP_LLVM_extract_bits_zext"; + case DW_OP_LLVM_poisoned: + return "DW_OP_LLVM_poisoned"; } } @@ -175,6 +177,7 @@ unsigned llvm::dwarf::getOperationEncoding(StringRef OperationEncodingString) { .Case("DW_OP_LLVM_arg", DW_OP_LLVM_arg) .Case("DW_OP_LLVM_extract_bits_sext", DW_OP_LLVM_extract_bits_sext) .Case("DW_OP_LLVM_extract_bits_zext", DW_OP_LLVM_extract_bits_zext) + .Case("DW_OP_LLVM_poisoned", DW_OP_LLVM_poisoned) .Default(0); } @@ -893,6 +896,8 @@ StringRef llvm::dwarf::AttributeValueString(uint16_t Attr, unsigned Val) { return DefaultedMemberString(Val); case DW_AT_APPLE_enum_kind: return EnumKindString(Val); + case DW_AT_LLVM_memory_space: + return MemorySpaceString(Val); case DW_AT_language_name: return SourceLanguageNameString(static_cast(Val)); } @@ -1044,6 +1049,29 @@ StringRef llvm::dwarf::RLEString(unsigned RLE) { } } +unsigned llvm::dwarf::getMemorySpace(StringRef CCString) { + return StringSwitch(CCString) +#define HANDLE_DW_MSPACE(ID, NAME) \ + .Case("DW_MSPACE_LLVM_" #NAME, DW_MSPACE_LLVM_##NAME) +#include "llvm/BinaryFormat/Dwarf.def" + .Default(0); +} + +StringRef llvm::dwarf::MemorySpaceString(unsigned MS) { + switch (MS) { + default: + return StringRef(); +#define HANDLE_DW_MSPACE(ID, NAME) \ + case DW_MSPACE_LLVM_##NAME: \ + return "DW_MSPACE_LLVM_" #NAME; +#include "llvm/BinaryFormat/Dwarf.def" + case DW_MSPACE_LLVM_lo_user: + return "DW_MSPACE_LLVM_lo_user"; + case DW_MSPACE_LLVM_hi_user: + return "DW_MSPACE_LLVM_hi_user"; + } +} + StringRef llvm::dwarf::AddressSpaceString(unsigned AS, const llvm::Triple &TT) { switch (AS) { #define HANDLE_DW_ASPACE(ID, NAME) \ diff --git a/llvm/lib/BinaryFormat/Magic.cpp b/llvm/lib/BinaryFormat/Magic.cpp index bd378337ed333..cfd39905e150b 100644 --- a/llvm/lib/BinaryFormat/Magic.cpp +++ b/llvm/lib/BinaryFormat/Magic.cpp @@ -25,7 +25,7 @@ using namespace llvm::support::endian; using namespace llvm::sys::fs; template -static bool startswith(StringRef Magic, const char (&S)[N]) { +static bool starts_with(StringRef Magic, const char (&S)[N]) { return Magic.starts_with(StringRef(S, N - 1)); } @@ -36,7 +36,7 @@ file_magic llvm::identify_magic(StringRef Magic) { switch ((unsigned char)Magic[0]) { case 0x00: { // COFF bigobj, CL.exe's LTO object file, or short import library file - if (startswith(Magic, "\0\0\xFF\xFF")) { + if (starts_with(Magic, "\0\0\xFF\xFF")) { size_t MinSize = offsetof(COFF::BigObjHeader, UUID) + sizeof(COFF::BigObjMagic); if (Magic.size() < MinSize) @@ -56,61 +56,61 @@ file_magic llvm::identify_magic(StringRef Magic) { // 0x0000 = COFF unknown machine type if (Magic[1] == 0) return file_magic::coff_object; - if (startswith(Magic, "\0asm")) + if (starts_with(Magic, "\0asm")) return file_magic::wasm_object; break; } case 0x01: // XCOFF format - if (startswith(Magic, "\x01\xDF")) + if (starts_with(Magic, "\x01\xDF")) return file_magic::xcoff_object_32; - if (startswith(Magic, "\x01\xF7")) + if (starts_with(Magic, "\x01\xF7")) return file_magic::xcoff_object_64; break; case 0x03: - if (startswith(Magic, "\x03\xF0\x00")) + if (starts_with(Magic, "\x03\xF0\x00")) return file_magic::goff_object; // SPIR-V format in little-endian mode. - if (startswith(Magic, "\x03\x02\x23\x07")) + if (starts_with(Magic, "\x03\x02\x23\x07")) return file_magic::spirv_object; break; case 0x07: // SPIR-V format in big-endian mode. - if (startswith(Magic, "\x07\x23\x02\x03")) + if (starts_with(Magic, "\x07\x23\x02\x03")) return file_magic::spirv_object; break; case 0x10: - if (startswith(Magic, "\x10\xFF\x10\xAD")) + if (starts_with(Magic, "\x10\xFF\x10\xAD")) return file_magic::offload_binary; break; case 0xDE: // 0x0B17C0DE = BC wraper - if (startswith(Magic, "\xDE\xC0\x17\x0B")) + if (starts_with(Magic, "\xDE\xC0\x17\x0B")) return file_magic::bitcode; break; case 'B': - if (startswith(Magic, "BC\xC0\xDE")) + if (starts_with(Magic, "BC\xC0\xDE")) return file_magic::bitcode; break; case 'C': - if (startswith(Magic, "CCOB")) + if (starts_with(Magic, "CCOB")) return file_magic::offload_bundle_compressed; - if (startswith(Magic, "CPCH")) + if (starts_with(Magic, "CPCH")) return file_magic::clang_ast; break; case '!': - if (startswith(Magic, "!\n") || startswith(Magic, "!\n")) + if (starts_with(Magic, "!\n") || starts_with(Magic, "!\n")) return file_magic::archive; break; case '<': - if (startswith(Magic, "\n")) + if (starts_with(Magic, "\n")) return file_magic::archive; break; case '\177': - if (startswith(Magic, "\177ELF") && Magic.size() >= 18) { + if (starts_with(Magic, "\177ELF") && Magic.size() >= 18) { bool Data2MSB = Magic[5] == 2; unsigned high = Data2MSB ? 16 : 17; unsigned low = Data2MSB ? 17 : 16; @@ -134,8 +134,8 @@ file_magic llvm::identify_magic(StringRef Magic) { break; case 0xCA: - if (startswith(Magic, "\xCA\xFE\xBA\xBE") || - startswith(Magic, "\xCA\xFE\xBA\xBF")) { + if (starts_with(Magic, "\xCA\xFE\xBA\xBE") || + starts_with(Magic, "\xCA\xFE\xBA\xBF")) { // This is complicated by an overlap with Java class files. // See the Mach-O section in /usr/share/file/magic for details. if (Magic.size() >= 8 && Magic[7] < 43) @@ -150,8 +150,8 @@ file_magic llvm::identify_magic(StringRef Magic) { case 0xCE: case 0xCF: { uint16_t type = 0; - if (startswith(Magic, "\xFE\xED\xFA\xCE") || - startswith(Magic, "\xFE\xED\xFA\xCF")) { + if (starts_with(Magic, "\xFE\xED\xFA\xCE") || + starts_with(Magic, "\xFE\xED\xFA\xCF")) { /* Native endian */ size_t MinSize; if (Magic[3] == char(0xCE)) @@ -160,8 +160,8 @@ file_magic llvm::identify_magic(StringRef Magic) { MinSize = sizeof(MachO::mach_header_64); if (Magic.size() >= MinSize) type = Magic[12] << 24 | Magic[13] << 12 | Magic[14] << 8 | Magic[15]; - } else if (startswith(Magic, "\xCE\xFA\xED\xFE") || - startswith(Magic, "\xCF\xFA\xED\xFE")) { + } else if (starts_with(Magic, "\xCE\xFA\xED\xFE") || + starts_with(Magic, "\xCF\xFA\xED\xFE")) { /* Reverse endian */ size_t MinSize; if (Magic[0] == char(0xCE)) @@ -206,7 +206,7 @@ file_magic llvm::identify_magic(StringRef Magic) { case 0x84: // Alpha 64-bit case 0x66: // MPS R4000 Windows case 0x50: // mc68K - if (startswith(Magic, "\x50\xed\x55\xba")) + if (starts_with(Magic, "\x50\xed\x55\xba")) return file_magic::cuda_fatbinary; [[fallthrough]]; @@ -224,7 +224,7 @@ file_magic llvm::identify_magic(StringRef Magic) { case 'M': // Possible MS-DOS stub on Windows PE file, MSF/PDB file or a // Minidump file. - if (startswith(Magic, "MZ") && Magic.size() >= 0x3c + 4) { + if (starts_with(Magic, "MZ") && Magic.size() >= 0x3c + 4) { uint32_t off = read32le(Magic.data() + 0x3c); // PE/COFF file, either EXE or DLL. if (Magic.substr(off).starts_with( @@ -233,7 +233,7 @@ file_magic llvm::identify_magic(StringRef Magic) { } if (Magic.starts_with("Microsoft C/C++ MSF 7.00\r\n")) return file_magic::pdb; - if (startswith(Magic, "MDMP")) + if (starts_with(Magic, "MDMP")) return file_magic::minidump; break; @@ -243,7 +243,7 @@ file_magic llvm::identify_magic(StringRef Magic) { break; case 0x2d: // YAML '-' MachO TBD. - if (startswith(Magic, "--- !tapi") || startswith(Magic, "---\narchs:")) + if (starts_with(Magic, "--- !tapi") || starts_with(Magic, "---\narchs:")) return file_magic::tapi_file; break; case 0x7b: // JSON '{' MachO TBD. @@ -251,7 +251,7 @@ file_magic llvm::identify_magic(StringRef Magic) { break; case 'D': // DirectX container file - DXBC - if (startswith(Magic, "DXBC")) + if (starts_with(Magic, "DXBC")) return file_magic::dxcontainer_object; break; @@ -267,7 +267,7 @@ file_magic llvm::identify_magic(StringRef Magic) { case '_': { const char OBMagic[] = "__CLANG_OFFLOAD_BUNDLE__"; - if (Magic.size() >= sizeof(OBMagic) && startswith(Magic, OBMagic)) + if (Magic.size() >= sizeof(OBMagic) && starts_with(Magic, OBMagic)) return file_magic::offload_bundle; break; } diff --git a/llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp b/llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp index fe9e0ddca7091..f6bb3d44f732a 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp @@ -381,6 +381,9 @@ GetCodeName(unsigned CodeID, unsigned BlockID, STRINGIFY_CODE(METADATA, INDEX_OFFSET) STRINGIFY_CODE(METADATA, INDEX) STRINGIFY_CODE(METADATA, ARG_LIST) + STRINGIFY_CODE(METADATA, EXPR) + STRINGIFY_CODE(METADATA, FRAGMENT) + STRINGIFY_CODE(METADATA, LIFETIME) } case bitc::METADATA_KIND_BLOCK_ID: switch (CodeID) { diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index 466dcb02696f4..1219cb9defe0e 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -2153,6 +2153,8 @@ static Attribute::AttrKind getAttrFromCode(uint64_t Code) { return Attribute::NullPointerIsValid; case bitc::ATTR_KIND_OPTIMIZE_FOR_DEBUGGING: return Attribute::OptimizeForDebugging; + case bitc::ATTR_KIND_SANITIZED_PADDED_GLOBAL: + return Attribute::SanitizedPaddedGlobal; case bitc::ATTR_KIND_OPT_FOR_FUZZING: return Attribute::OptForFuzzing; case bitc::ATTR_KIND_OPTIMIZE_FOR_SIZE: @@ -6715,8 +6717,7 @@ Error BitcodeReader::parseFunctionBody(Function *F) { DIExpression *AddrExpr = cast(getFnMetadataByID(Record[Slot++])); Metadata *Addr = getFnMetadataByID(Record[Slot++]); - DVR = new DbgVariableRecord(RawLocation, Var, Expr, ID, Addr, AddrExpr, - DIL); + DVR = new DbgVariableRecord(RawLocation, Var, Expr, ID, Addr, AddrExpr, DIL); break; } default: diff --git a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp index ed0443f599a44..95674dad63baf 100644 --- a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp +++ b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp @@ -393,6 +393,18 @@ static Error error(const Twine &Message) { Message, make_error_code(BitcodeError::CorruptedBitcode)); } +static Expected +getDWARFMemorySpaceAtPosition(ArrayRef Records, size_t Position) { + if (Position >= Records.size()) + return dwarf::DW_MSPACE_LLVM_none; + + const uint64_t Record = Records[Position]; + if (Record > dwarf::DW_MSPACE_LLVM_hi_user) + return error("MemorySpace value is too large"); + + return {static_cast(Record)}; +} + class MetadataLoader::MetadataLoaderImpl { BitcodeReaderMetadataList MetadataList; BitcodeReaderValueList &ValueList; @@ -462,6 +474,9 @@ class MetadataLoader::MetadataLoaderImpl { /// True if metadata is being parsed for a module being ThinLTO imported. bool IsImporting = false; + template + Error appendDIOpsToBuilder(BuilderType &Builder, ArrayRef Elems); + Error parseOneMetadata(SmallVectorImpl &Record, unsigned Code, PlaceholderQueue &Placeholders, StringRef Blob, unsigned &NextMetadataNo); @@ -1235,6 +1250,184 @@ static Value *getValueFwdRef(BitcodeReaderValueList &ValueList, unsigned Idx, return nullptr; } +/// Walk through the elements of a DIOp-based DIExpr/DIExpression record and add +/// the operations to the builder type one by one. +template +Error MetadataLoader::MetadataLoaderImpl::appendDIOpsToBuilder( + BuilderType &Builder, ArrayRef Elems) { + while (Elems.size() > 0) { + auto DIOpID = Elems[0]; + Elems = Elems.slice(1); + switch (DIOpID) { + default: + return error("Invalid record"); +#define HANDLE_OP0(NAME) \ + case DIOp::NAME::getBitcodeID(): \ + Builder.template append(); \ + break; +#include "llvm/IR/DIExprOps.def" + case DIOp::Referrer::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Ty); + Elems = Elems.slice(1); + break; + } + case DIOp::Arg::getBitcodeID(): { + if (Elems.size() < 2) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Elems[1], Ty); + Elems = Elems.slice(2); + break; + } + case DIOp::TypeObject::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Ty); + Elems = Elems.slice(1); + break; + } + case DIOp::Constant::getBitcodeID(): { + if (Elems.size() < 2) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Value *V = ValueList[Elems[1]]; + if (!V || !isa(V)) + return error("Invalid record"); + if (Ty != V->getType()) + report_fatal_error("Invalid record"); + Builder.template append(cast(V)); + Elems = Elems.slice(2); + break; + } + case DIOp::Convert::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Ty); + Elems = Elems.slice(1); + break; + } + case DIOp::ZExt::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Ty); + Elems = Elems.slice(1); + break; + } + case DIOp::SExt::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Ty); + Elems = Elems.slice(1); + break; + } + case DIOp::Reinterpret::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Ty); + Elems = Elems.slice(1); + break; + } + case DIOp::BitOffset::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Ty); + Elems = Elems.slice(1); + break; + } + case DIOp::ByteOffset::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Ty); + Elems = Elems.slice(1); + break; + } + case DIOp::Composite::getBitcodeID(): { + if (Elems.size() < 2) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Elems[1], Ty); + Elems = Elems.slice(2); + break; + } + case DIOp::Extend::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Builder.template append(Elems[0]); + Elems = Elems.slice(1); + break; + } + case DIOp::AddrOf::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Builder.template append(Elems[0]); + Elems = Elems.slice(1); + break; + } + case DIOp::Deref::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Ty); + Elems = Elems.slice(1); + break; + } + case DIOp::PushLane::getBitcodeID(): { + if (Elems.size() < 1) + return error("Invalid record"); + Type *Ty = Callbacks.GetTypeByID(Elems[0]); + if (!Ty || !Ty->isFirstClassType()) + return error("Invalid record"); + Builder.template append(Ty); + Elems = Elems.slice(1); + break; + } + case DIOp::Fragment::getBitcodeID(): { + if (Elems.size() < 2) + return error("Invalid record"); + Builder.template append(Elems[0], Elems[1]); + Elems = Elems.slice(2); + break; + } + } + } + + return Error::success(); +} + Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( SmallVectorImpl &Record, unsigned Code, PlaceholderQueue &Placeholders, StringRef Blob, unsigned &NextMetadataNo) { @@ -1612,7 +1805,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( break; } case bitc::METADATA_DERIVED_TYPE: { - if (Record.size() < 12 || Record.size() > 15) + if (Record.size() < 12 || Record.size() > 16) return error("Invalid record"); // DWARF address space is encoded as N->getDWARFAddressSpace() + 1. 0 means @@ -1627,13 +1820,17 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( // Only look for annotations/ptrauth if both are allocated. // If not, we can't tell which was intended to be embedded, as both ptrauth // and annotations have been expected at Record[13] at various times. - if (Record.size() > 14) { + if (Record.size() > 15) { if (Record[13]) Annotations = getMDOrNull(Record[13]); - if (Record[14]) - PtrAuthData.emplace(Record[14]); + if (Record[15]) + PtrAuthData.emplace(Record[15]); } + auto MSpace = getDWARFMemorySpaceAtPosition(Record, 14); + if (!MSpace) + return MSpace.takeError(); + IsDistinct = Record[0] & 1; bool SizeIsMetadata = Record[0] & 2; DINode::DIFlags Flags = static_cast(Record[10]); @@ -1647,7 +1844,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( getMDOrNull(Record[3]), Record[4], getDITypeRefOrNull(Record[5]), getDITypeRefOrNull(Record[6]), SizeInBits, Record[8], - OffsetInBits, DWARFAddressSpace, PtrAuthData, Flags, + OffsetInBits, DWARFAddressSpace, *MSpace, PtrAuthData, Flags, getDITypeRefOrNull(Record[11]), Annotations)), NextMetadataNo); NextMetadataNo++; @@ -2129,7 +2326,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( break; } case bitc::METADATA_GLOBAL_VAR: { - if (Record.size() < 11 || Record.size() > 13) + if (Record.size() < 11 || Record.size() > 14) return error("Invalid record"); IsDistinct = Record[0] & 1; @@ -2137,9 +2334,16 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( if (Version == 2) { Metadata *Annotations = nullptr; - if (Record.size() > 12) + auto Align = Record[11]; + + bool HasAnnotations = Record.size() > 12; + if (HasAnnotations) { Annotations = getMDOrNull(Record[12]); + } + auto MSpace = getDWARFMemorySpaceAtPosition(Record, 13); + if (!MSpace) + return MSpace.takeError(); MetadataList.assignValue( GET_OR_DISTINCT(DIGlobalVariable, (Context, getMDOrNull(Record[1]), @@ -2147,7 +2351,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( getMDOrNull(Record[4]), Record[5], getDITypeRefOrNull(Record[6]), Record[7], Record[8], getMDOrNull(Record[9]), getMDOrNull(Record[10]), - Record[11], Annotations)), + *MSpace, Align, Annotations)), NextMetadataNo); NextMetadataNo++; @@ -2155,12 +2359,13 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( // No upgrade necessary. A null field will be introduced to indicate // that no parameter information is available. MetadataList.assignValue( - GET_OR_DISTINCT( - DIGlobalVariable, - (Context, getMDOrNull(Record[1]), getMDString(Record[2]), - getMDString(Record[3]), getMDOrNull(Record[4]), Record[5], - getDITypeRefOrNull(Record[6]), Record[7], Record[8], - getMDOrNull(Record[10]), nullptr, Record[11], nullptr)), + GET_OR_DISTINCT(DIGlobalVariable, + (Context, getMDOrNull(Record[1]), + getMDString(Record[2]), getMDString(Record[3]), + getMDOrNull(Record[4]), Record[5], + getDITypeRefOrNull(Record[6]), Record[7], Record[8], + getMDOrNull(Record[10]), nullptr, + dwarf::DW_MSPACE_LLVM_none, Record[11], nullptr)), NextMetadataNo); NextMetadataNo++; @@ -2193,7 +2398,8 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( (Context, getMDOrNull(Record[1]), getMDString(Record[2]), getMDString(Record[3]), getMDOrNull(Record[4]), Record[5], getDITypeRefOrNull(Record[6]), Record[7], Record[8], - getMDOrNull(Record[10]), nullptr, AlignInBits, nullptr)); + getMDOrNull(Record[10]), nullptr, dwarf::DW_MSPACE_LLVM_none, + AlignInBits, nullptr)); DIGlobalVariableExpression *DGVE = nullptr; if (Attach || Expr) @@ -2224,7 +2430,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( } case bitc::METADATA_LOCAL_VAR: { // 10th field is for the obseleted 'inlinedAt:' field. - if (Record.size() < 8 || Record.size() > 10) + if (Record.size() < 8 || Record.size() > 11) return error("Invalid record"); IsDistinct = Record[0] & 1; @@ -2244,13 +2450,17 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( Annotations = getMDOrNull(Record[9]); } + auto MSpace = getDWARFMemorySpaceAtPosition(Record, 10); + if (!MSpace) + return MSpace.takeError(); + MetadataList.assignValue( - GET_OR_DISTINCT(DILocalVariable, - (Context, getMDOrNull(Record[1 + HasTag]), - getMDString(Record[2 + HasTag]), - getMDOrNull(Record[3 + HasTag]), Record[4 + HasTag], - getDITypeRefOrNull(Record[5 + HasTag]), - Record[6 + HasTag], Flags, AlignInBits, Annotations)), + GET_OR_DISTINCT( + DILocalVariable, + (Context, getMDOrNull(Record[1 + HasTag]), + getMDString(Record[2 + HasTag]), getMDOrNull(Record[3 + HasTag]), + Record[4 + HasTag], getDITypeRefOrNull(Record[5 + HasTag]), + Record[6 + HasTag], Flags, *MSpace, AlignInBits, Annotations)), NextMetadataNo); NextMetadataNo++; break; @@ -2290,12 +2500,21 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( uint64_t Version = Record[0] >> 1; auto Elts = MutableArrayRef(Record).slice(1); + // Version 16 signifies a DIOp-based DIExpression. + if (Version == 16) { + DIExprBuilder Builder(Context); + if (Error Err = appendDIOpsToBuilder(Builder, Elts)) + return Err; + MetadataList.assignValue(Builder.intoExpression(), NextMetadataNo); + NextMetadataNo++; + break; + } + SmallVector Buffer; if (Error Err = upgradeDIExpression(Version, Elts, Buffer)) return Err; - MetadataList.assignValue(GET_OR_DISTINCT(DIExpression, (Context, Elts)), - NextMetadataNo); + MetadataList.assignValue(DIExpression::get(Context, Elts), NextMetadataNo); NextMetadataNo++; break; } diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index 61aa7c2f5af53..1ce69f2082b5f 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -403,6 +403,11 @@ class ModuleBitcodeWriter : public ModuleBitcodeWriterBase { SmallVectorImpl &Record, unsigned Abbrev); void writeDILabel(const DILabel *N, SmallVectorImpl &Record, unsigned Abbrev); + + void writeOneDIOpToRecord(SmallVectorImpl &Record, + DIOp::Variant Op); + void writeNewDIExpression(const DIExpression *N, + SmallVectorImpl &Record, unsigned Abbrev); void writeDIExpression(const DIExpression *N, SmallVectorImpl &Record, unsigned Abbrev); void writeDIGlobalVariableExpression(const DIGlobalVariableExpression *N, @@ -900,6 +905,8 @@ static uint64_t getAttrKindEncoding(Attribute::AttrKind Kind) { return bitc::ATTR_KIND_SANITIZE_TYPE; case Attribute::SanitizeMemory: return bitc::ATTR_KIND_SANITIZE_MEMORY; + case Attribute::SanitizedPaddedGlobal: + return bitc::ATTR_KIND_SANITIZED_PADDED_GLOBAL; case Attribute::SanitizeNumericalStability: return bitc::ATTR_KIND_SANITIZE_NUMERICAL_STABILITY; case Attribute::SanitizeRealtime: @@ -1916,11 +1923,10 @@ void ModuleBitcodeWriter::writeDIEnumerator(const DIEnumerator *N, void ModuleBitcodeWriter::writeDIBasicType(const DIBasicType *N, SmallVectorImpl &Record, unsigned Abbrev) { - const unsigned SizeIsMetadata = 0x2; - Record.push_back(SizeIsMetadata | (unsigned)N->isDistinct()); + Record.push_back(N->isDistinct()); Record.push_back(N->getTag()); Record.push_back(VE.getMetadataOrNullID(N->getRawName())); - Record.push_back(VE.getMetadataOrNullID(N->getRawSizeInBits())); + Record.push_back(N->getSizeInBits()); Record.push_back(N->getAlignInBits()); Record.push_back(N->getEncoding()); Record.push_back(N->getFlags()); @@ -1933,11 +1939,10 @@ void ModuleBitcodeWriter::writeDIBasicType(const DIBasicType *N, void ModuleBitcodeWriter::writeDIFixedPointType( const DIFixedPointType *N, SmallVectorImpl &Record, unsigned Abbrev) { - const unsigned SizeIsMetadata = 0x2; - Record.push_back(SizeIsMetadata | (unsigned)N->isDistinct()); + Record.push_back(N->isDistinct()); Record.push_back(N->getTag()); Record.push_back(VE.getMetadataOrNullID(N->getRawName())); - Record.push_back(VE.getMetadataOrNullID(N->getRawSizeInBits())); + Record.push_back(N->getSizeInBits()); Record.push_back(N->getAlignInBits()); Record.push_back(N->getEncoding()); Record.push_back(N->getFlags()); @@ -1963,14 +1968,13 @@ void ModuleBitcodeWriter::writeDIFixedPointType( void ModuleBitcodeWriter::writeDIStringType(const DIStringType *N, SmallVectorImpl &Record, unsigned Abbrev) { - const unsigned SizeIsMetadata = 0x2; - Record.push_back(SizeIsMetadata | (unsigned)N->isDistinct()); + Record.push_back(N->isDistinct()); Record.push_back(N->getTag()); Record.push_back(VE.getMetadataOrNullID(N->getRawName())); Record.push_back(VE.getMetadataOrNullID(N->getStringLength())); Record.push_back(VE.getMetadataOrNullID(N->getStringLengthExp())); Record.push_back(VE.getMetadataOrNullID(N->getStringLocationExp())); - Record.push_back(VE.getMetadataOrNullID(N->getRawSizeInBits())); + Record.push_back(N->getSizeInBits()); Record.push_back(N->getAlignInBits()); Record.push_back(N->getEncoding()); @@ -1981,17 +1985,16 @@ void ModuleBitcodeWriter::writeDIStringType(const DIStringType *N, void ModuleBitcodeWriter::writeDIDerivedType(const DIDerivedType *N, SmallVectorImpl &Record, unsigned Abbrev) { - const unsigned SizeIsMetadata = 0x2; - Record.push_back(SizeIsMetadata | (unsigned)N->isDistinct()); + Record.push_back(N->isDistinct()); Record.push_back(N->getTag()); Record.push_back(VE.getMetadataOrNullID(N->getRawName())); Record.push_back(VE.getMetadataOrNullID(N->getFile())); Record.push_back(N->getLine()); Record.push_back(VE.getMetadataOrNullID(N->getScope())); Record.push_back(VE.getMetadataOrNullID(N->getBaseType())); - Record.push_back(VE.getMetadataOrNullID(N->getRawSizeInBits())); + Record.push_back(N->getSizeInBits()); Record.push_back(N->getAlignInBits()); - Record.push_back(VE.getMetadataOrNullID(N->getRawOffsetInBits())); + Record.push_back(N->getOffsetInBits()); Record.push_back(N->getFlags()); Record.push_back(VE.getMetadataOrNullID(N->getExtraData())); @@ -2003,6 +2006,7 @@ void ModuleBitcodeWriter::writeDIDerivedType(const DIDerivedType *N, Record.push_back(0); Record.push_back(VE.getMetadataOrNullID(N->getAnnotations().get())); + Record.push_back(static_cast(N->getDWARFMemorySpace())); if (auto PtrAuthData = N->getPtrAuthData()) Record.push_back(PtrAuthData->RawData); @@ -2016,13 +2020,12 @@ void ModuleBitcodeWriter::writeDIDerivedType(const DIDerivedType *N, void ModuleBitcodeWriter::writeDISubrangeType(const DISubrangeType *N, SmallVectorImpl &Record, unsigned Abbrev) { - const unsigned SizeIsMetadata = 0x2; - Record.push_back(SizeIsMetadata | (unsigned)N->isDistinct()); + Record.push_back(N->isDistinct()); Record.push_back(VE.getMetadataOrNullID(N->getRawName())); Record.push_back(VE.getMetadataOrNullID(N->getFile())); Record.push_back(N->getLine()); Record.push_back(VE.getMetadataOrNullID(N->getScope())); - Record.push_back(VE.getMetadataOrNullID(N->getRawSizeInBits())); + Record.push_back(N->getSizeInBits()); Record.push_back(N->getAlignInBits()); Record.push_back(N->getFlags()); Record.push_back(VE.getMetadataOrNullID(N->getBaseType())); @@ -2039,18 +2042,16 @@ void ModuleBitcodeWriter::writeDICompositeType( const DICompositeType *N, SmallVectorImpl &Record, unsigned Abbrev) { const unsigned IsNotUsedInOldTypeRef = 0x2; - const unsigned SizeIsMetadata = 0x4; - Record.push_back(SizeIsMetadata | IsNotUsedInOldTypeRef | - (unsigned)N->isDistinct()); + Record.push_back(IsNotUsedInOldTypeRef | (unsigned)N->isDistinct()); Record.push_back(N->getTag()); Record.push_back(VE.getMetadataOrNullID(N->getRawName())); Record.push_back(VE.getMetadataOrNullID(N->getFile())); Record.push_back(N->getLine()); Record.push_back(VE.getMetadataOrNullID(N->getScope())); Record.push_back(VE.getMetadataOrNullID(N->getBaseType())); - Record.push_back(VE.getMetadataOrNullID(N->getRawSizeInBits())); + Record.push_back(N->getSizeInBits()); Record.push_back(N->getAlignInBits()); - Record.push_back(VE.getMetadataOrNullID(N->getRawOffsetInBits())); + Record.push_back(N->getOffsetInBits()); Record.push_back(N->getFlags()); Record.push_back(VE.getMetadataOrNullID(N->getElements().get())); Record.push_back(N->getRuntimeLang()); @@ -2330,6 +2331,7 @@ void ModuleBitcodeWriter::writeDIGlobalVariable( Record.push_back(VE.getMetadataOrNullID(N->getTemplateParams())); Record.push_back(N->getAlignInBits()); Record.push_back(VE.getMetadataOrNullID(N->getAnnotations().get())); + Record.push_back(N->getDWARFMemorySpace()); Stream.EmitRecord(bitc::METADATA_GLOBAL_VAR, Record, Abbrev); Record.clear(); @@ -2362,6 +2364,7 @@ void ModuleBitcodeWriter::writeDILocalVariable( Record.push_back(N->getFlags()); Record.push_back(N->getAlignInBits()); Record.push_back(VE.getMetadataOrNullID(N->getAnnotations().get())); + Record.push_back(N->getDWARFMemorySpace()); Stream.EmitRecord(bitc::METADATA_LOCAL_VAR, Record, Abbrev); Record.clear(); @@ -2385,9 +2388,90 @@ void ModuleBitcodeWriter::writeDILabel( Record.clear(); } +void ModuleBitcodeWriter::writeOneDIOpToRecord( + SmallVectorImpl &Record, DIOp::Variant Op) { + Record.push_back(DIOp::getBitcodeID(Op)); + std::visit( + makeVisitor( +#define HANDLE_OP0(NAME) [](DIOp::NAME) {}, +#include "llvm/IR/DIExprOps.def" +#undef HANDLE_OP0 + [&](DIOp::Referrer Referrer) { + Record.push_back(VE.getTypeID(Referrer.getResultType())); + }, + [&](DIOp::Arg Arg) { + Record.push_back(VE.getTypeID(Arg.getResultType())); + Record.push_back(Arg.getIndex()); + }, + [&](DIOp::TypeObject TypeObject) { + Record.push_back(VE.getTypeID(TypeObject.getResultType())); + }, + [&](DIOp::Constant Constant) { + Record.push_back( + VE.getTypeID(Constant.getLiteralValue()->getType())); + Record.push_back(VE.getValueID(Constant.getLiteralValue())); + }, + [&](DIOp::Convert Convert) { + Record.push_back(VE.getTypeID(Convert.getResultType())); + }, + [&](DIOp::ZExt ZExt) { + Record.push_back(VE.getTypeID(ZExt.getResultType())); + }, + [&](DIOp::SExt SExt) { + Record.push_back(VE.getTypeID(SExt.getResultType())); + }, + [&](DIOp::Reinterpret Reinterpret) { + Record.push_back(VE.getTypeID(Reinterpret.getResultType())); + }, + [&](DIOp::BitOffset BitOffset) { + Record.push_back(VE.getTypeID(BitOffset.getResultType())); + }, + [&](DIOp::ByteOffset ByteOffset) { + Record.push_back(VE.getTypeID(ByteOffset.getResultType())); + }, + [&](DIOp::Composite Composite) { + Record.push_back(VE.getTypeID(Composite.getResultType())); + Record.push_back(Composite.getCount()); + }, + [&](DIOp::Extend Extend) { Record.push_back(Extend.getCount()); }, + [&](DIOp::AddrOf AddrOf) { + Record.push_back(AddrOf.getAddressSpace()); + }, + [&](DIOp::Deref Deref) { + Record.push_back(VE.getTypeID(Deref.getResultType())); + }, + [&](DIOp::PushLane PushLane) { + Record.push_back(VE.getTypeID(PushLane.getResultType())); + }, + [&](DIOp::Fragment Fragment) { + Record.push_back(Fragment.getBitOffset()); + Record.push_back(Fragment.getBitSize()); + }), + Op); +} + +void ModuleBitcodeWriter::writeNewDIExpression( + const DIExpression *N, SmallVectorImpl &Record, unsigned Abbrev) { + assert(N->holdsNewElements()); + + // Use version 16 for DIOp DIExpressions. This is just an arbitrary large + // number to avoid any merge issues if the upstream version increases from 3. + const uint64_t Version = 16 << 1; + Record.push_back((uint64_t)N->isDistinct() | Version); + auto Elements = N->getNewElementsRef(); + for (auto &Elem : *Elements) + writeOneDIOpToRecord(Record, Elem); + + Stream.EmitRecord(bitc::METADATA_EXPRESSION, Record, Abbrev); + Record.clear(); +} + void ModuleBitcodeWriter::writeDIExpression(const DIExpression *N, SmallVectorImpl &Record, unsigned Abbrev) { + if (N->holdsNewElements()) + return writeNewDIExpression(N, Record, Abbrev); + Record.reserve(N->getElements().size() + 1); const uint64_t Version = 3 << 1; Record.push_back((uint64_t)N->isDistinct() | Version); diff --git a/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp b/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp index f497c574ee75d..d35c17e3afd2b 100644 --- a/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp +++ b/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp @@ -746,6 +746,36 @@ const MDNode *ValueEnumerator::enumerateMetadataImpl(unsigned F, const Metadata return nullptr; } + auto enumerateDIOp = [this](DIOp::Variant Op) { + std::visit( + makeVisitor( +#define HANDLE_OP0(NAME) [](DIOp::NAME) {}, +#include "llvm/IR/DIExprOps.def" + [&](DIOp::Referrer R) { EnumerateType(R.getResultType()); }, + [&](DIOp::Arg A) { EnumerateType(A.getResultType()); }, + [&](DIOp::TypeObject T) { EnumerateType(T.getResultType()); }, + [&](DIOp::Constant C) { EnumerateValue(C.getLiteralValue()); }, + [&](DIOp::Convert C) { EnumerateType(C.getResultType()); }, + [&](DIOp::ZExt C) { EnumerateType(C.getResultType()); }, + [&](DIOp::SExt C) { EnumerateType(C.getResultType()); }, + [&](DIOp::Reinterpret R) { EnumerateType(R.getResultType()); }, + [&](DIOp::BitOffset B) { EnumerateType(B.getResultType()); }, + [&](DIOp::ByteOffset B) { EnumerateType(B.getResultType()); }, + [&](DIOp::Composite C) { EnumerateType(C.getResultType()); }, + [&](DIOp::Extend) {}, [&](DIOp::AddrOf) {}, + [&](DIOp::Deref D) { EnumerateType(D.getResultType()); }, + [&](DIOp::PushLane P) { EnumerateType(P.getResultType()); }, + [&](DIOp::Fragment) {}), + Op); + }; + + if (auto *E = dyn_cast(MD)) { + if (auto Elems = E->getNewElementsRef()) { + for (const auto &Op : *Elems) + enumerateDIOp(Op); + } + } + // Don't assign IDs to metadata nodes. if (auto *N = dyn_cast(MD)) return N; diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 8aa488f0efd8f..efb494090fdf3 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -812,6 +812,19 @@ void AsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { // sections and expected to be contiguous (e.g. ObjC metadata). const Align Alignment = getGVAlignment(GV, DL); + // Identify globals with "SanitizedPaddedGlobal" attribute and extract + // the actual global variable size. + uint64_t ActualSize = 0; + if (GV->hasAttribute(Attribute::SanitizedPaddedGlobal)) { + StructType *ST = dyn_cast(GV->getValueType()); + if (ST && ST->getNumElements() == 2) { + auto *ET0 = ST->getElementType(0); + if (ET0 && isa(ST->getElementType(1))) { + ActualSize = DL.getTypeAllocSize(ET0); + } + } + } + for (auto &Handler : Handlers) Handler->setSymbolSize(GVSym, Size); @@ -917,6 +930,18 @@ void AsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { MCSymbol *EmittedInitSym = GVSym; + if (GV->hasAttribute(Attribute::SanitizedPaddedGlobal)) { + OutStreamer->switchSection(TheSection); + emitLinkage(GV, EmittedInitSym); + OutStreamer->emitLabel(EmittedInitSym); + if (MAI->hasDotTypeDotSizeDirective()) + OutStreamer->emitELFSize(EmittedInitSym, + MCConstantExpr::create(ActualSize, OutContext)); + EmittedInitSym = OutContext.getOrCreateSymbol( + GVSym->getName() + Twine("__sanitized_padded_global")); + emitVisibility(EmittedInitSym, GV->getVisibility(), !GV->isDeclaration()); + } + OutStreamer->switchSection(TheSection); emitLinkage(GV, EmittedInitSym); @@ -924,7 +949,8 @@ void AsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { OutStreamer->emitLabel(EmittedInitSym); MCSymbol *LocalAlias = getSymbolPreferLocal(*GV); - if (LocalAlias != EmittedInitSym) + if ((LocalAlias != EmittedInitSym) && + !GV->hasAttribute(Attribute::SanitizedPaddedGlobal)) OutStreamer->emitLabel(LocalAlias); emitGlobalConstant(GV->getDataLayout(), GV->getInitializer()); @@ -1329,6 +1355,27 @@ static bool emitDebugLabelComment(const MachineInstr *MI, AsmPrinter &AP) { return true; } +/// This method handles the target-independent form +/// of DBG_DEF, returning true if it was able to do so. A false return +/// means the target will need to handle MI in EmitInstruction. +bool AsmPrinter::emitDebugComment(const MachineInstr *MI) { + assert(MI->isDebugInstr()); + + if (!isVerbose()) + return true; + + switch(MI->getOpcode()) { + case TargetOpcode::DBG_VALUE: + case TargetOpcode::DBG_VALUE_LIST: + return emitDebugValueComment(MI, *this); + case TargetOpcode::DBG_LABEL: + return emitDebugLabelComment(MI, *this); + default: + break; + } + return false; +} + AsmPrinter::CFISection AsmPrinter::getFunctionCFISectionType(const Function &F) const { // Ignore functions that won't get emitted. @@ -2040,9 +2087,9 @@ void AsmPrinter::emitFunctionBody() { break; case TargetOpcode::DBG_VALUE: case TargetOpcode::DBG_VALUE_LIST: - if (isVerbose()) { - if (!emitDebugValueComment(&MI, *this)) - emitInstruction(&MI); + case TargetOpcode::DBG_LABEL: + if(!emitDebugComment(&MI)) { + emitInstruction(&MI); } break; case TargetOpcode::DBG_INSTR_REF: @@ -2054,12 +2101,6 @@ void AsmPrinter::emitFunctionBody() { // This instruction is only used to label a program point, it's purely // meta information. break; - case TargetOpcode::DBG_LABEL: - if (isVerbose()) { - if (!emitDebugLabelComment(&MI, *this)) - emitInstruction(&MI); - } - break; case TargetOpcode::IMPLICIT_DEF: if (isVerbose()) emitImplicitDef(&MI); break; diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp index 2a146eb15f709..44637656f1979 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp @@ -260,6 +260,39 @@ void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const { case MCCFIInstruction::OpRestoreState: OutStreamer->emitCFIRestoreState(Loc); break; + case MCCFIInstruction::OpLLVMRegisterPair: { + const auto &Fields = + Inst.getExtraFields(); + OutStreamer->emitCFILLVMRegisterPair(Inst.getRegister(), Fields.Reg1, + Fields.Reg1SizeInBits, Fields.Reg2, + Fields.Reg2SizeInBits, Loc); + break; + } + case MCCFIInstruction::OpLLVMVectorRegisters: { + const auto &Fields = + Inst.getExtraFields(); + OutStreamer->emitCFILLVMVectorRegisters(Inst.getRegister(), + Fields.VectorRegisters, Loc); + break; + } + case MCCFIInstruction::OpLLVMVectorOffset: { + const auto &Fields = + Inst.getExtraFields(); + OutStreamer->emitCFILLVMVectorOffset( + Inst.getRegister(), Fields.RegisterSizeInBits, Fields.MaskRegister, + Fields.MaskRegisterSizeInBits, Inst.getOffset(), Loc); + break; + } + case MCCFIInstruction::OpLLVMVectorRegisterMask: { + const auto &Fields = + Inst.getExtraFields(); + OutStreamer->emitCFILLVMVectorRegisterMask( + Inst.getRegister(), Fields.SpillRegister, + Fields.SpillRegisterLaneSizeInBits, Fields.MaskRegister, + Fields.MaskRegisterSizeInBits); + break; + } + case MCCFIInstruction::OpValOffset: OutStreamer->emitCFIValOffset(Inst.getRegister(), Inst.getOffset(), Loc); break; diff --git a/llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h b/llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h index 5358f7b54f411..f1d94b0de83cf 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h +++ b/llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h @@ -41,6 +41,7 @@ class DbgValueLocEntry { /// Type of entry that this represents. enum EntryType { + E_Global, E_Location, E_Integer, E_ConstantFP, @@ -63,6 +64,9 @@ class DbgValueLocEntry { TargetIndexLocation TIL; }; + /// Or a global variable location. + const GlobalVariable *GV; + public: DbgValueLocEntry(int64_t i) : EntryKind(E_Integer) { Constant.Int = i; } DbgValueLocEntry(const ConstantFP *CFP) : EntryKind(E_ConstantFP) { @@ -91,8 +95,21 @@ class DbgValueLocEntry { MachineLocation getLoc() const { return Loc; } TargetIndexLocation getTargetIndexLocation() const { return TIL; } friend bool operator==(const DbgValueLocEntry &, const DbgValueLocEntry &); + + DbgValueLocEntry(const GlobalVariable *GV) : EntryKind(E_Global), GV(GV) {} + bool isGlobal() const { return EntryKind == E_Global; } + const GlobalVariable *getGlobal() const { return GV; } + #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVM_DUMP_METHOD void dump() const { + + if (isGlobal()) { + llvm::dbgs() << "GV = { "; + GV->printAsOperand(llvm::dbgs(), false); + llvm::dbgs() << "} "; + return; + } + if (isLocation()) { llvm::dbgs() << "Loc = { reg=" << Loc.getReg() << " "; if (Loc.isIndirect()) @@ -256,6 +273,8 @@ inline bool operator==(const DbgValueLocEntry &A, const DbgValueLocEntry &B) { return false; switch (A.EntryKind) { + case DbgValueLocEntry::E_Global: + return A.GV == B.GV; case DbgValueLocEntry::E_Location: return A.Loc == B.Loc; case DbgValueLocEntry::E_TargetIndexLocation: diff --git a/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.cpp b/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.cpp index 700e24a08b5d5..3ea472d454fb1 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.cpp @@ -40,5 +40,5 @@ void DebugLocStream::finalizeEntry() { DebugLocStream::ListBuilder::~ListBuilder() { if (!Locs.finalizeList(Asm)) return; - V.emplace(ListIndex, TagOffset); + V.emplace(ListIndex, TagOffset, CommonAddrSpace); } diff --git a/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h b/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h index 6f553dc85c646..894e680daa7f6 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h +++ b/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h @@ -157,6 +157,7 @@ class DebugLocStream::ListBuilder { DbgVariable &V; size_t ListIndex; std::optional TagOffset; + std::optional CommonAddrSpace; public: ListBuilder(DebugLocStream &Locs, DwarfCompileUnit &CU, AsmPrinter &Asm, @@ -168,6 +169,11 @@ class DebugLocStream::ListBuilder { TagOffset = TO; } + void setCommonDivergentAddrSpace(unsigned AS) { CommonAddrSpace = AS; } + bool hasCommonDivergentAddrSpace() const { + return CommonAddrSpace != std::nullopt; + } + /// Finalize the list. /// /// If the list is empty, delete it. Otherwise, finalize it by creating a diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp index 518121e200190..cd9e68465f116 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp @@ -228,6 +228,8 @@ DIE *DwarfCompileUnit::getOrCreateGlobalVariableDIE( addAnnotation(*VariableDIE, GV->getAnnotations()); + addMemorySpaceAttribute(*VariableDIE, GV->getDWARFMemorySpace()); + if (uint32_t AlignInBytes = GV->getAlignInBytes()) addUInt(*VariableDIE, dwarf::DW_AT_alignment, dwarf::DW_FORM_udata, AlignInBytes); @@ -298,6 +300,27 @@ void DwarfCompileUnit::addLocationAttribute( } } DwarfExpr->addFragmentOffset(Expr); + + std::optional NewElementsRef + = Expr ? Expr->getNewElementsRef() : std::nullopt; + if (NewElementsRef) { + SmallVector ArgLocEntries; + if (Global) + ArgLocEntries.emplace_back(Global); + DwarfExpr->addExpression(*NewElementsRef, ArgLocEntries); + continue; + } + } + + // FIXME: This is a workaround to avoid generating symbols for non-global + // address spaces, e.g. LDS. Generate a 'DW_OP_constu' with a dummy + // constant value (0) for now. + unsigned AMDGPUGlobalAddrSpace = 1; + if ((Asm->TM.getTargetTriple().getArch() == Triple::amdgcn) && + (Global->getAddressSpace() != AMDGPUGlobalAddrSpace)) { + addUInt(*Loc, dwarf::DW_FORM_data1, dwarf::DW_OP_constu); + addUInt(*Loc, dwarf::DW_FORM_udata, 0); + continue; } if (Global) { @@ -813,6 +836,8 @@ DIE *DwarfCompileUnit::constructVariableDIE(DbgVariable &DV, bool Abstract) { void DwarfCompileUnit::applyConcreteDbgVariableAttributes( const Loc::Single &Single, const DbgVariable &DV, DIE &VariableDie) { const DbgValueLoc *DVal = &Single.getValueLoc(); + const DIExpression *Expr = Single.getExpr(); + if (Asm->TM.getTargetTriple().isNVPTX() && DD->tuneForGDB() && !Single.getExpr()) { // cuda-gdb special requirement. See NVPTXAS::DWARF_AddressSpace @@ -859,14 +884,25 @@ void DwarfCompileUnit::applyConcreteDbgVariableAttributes( return Entry.isLocation() && !Entry.getLoc().getReg(); })) return; - const DIExpression *Expr = Single.getExpr(); assert(Expr && "Variadic Debug Value must have an Expression."); DIELoc *Loc = new (DIEValueAllocator) DIELoc; + DIEDwarfExpression DwarfExpr(*Asm, *this, *Loc); DwarfExpr.addFragmentOffset(Expr); - DIExpressionCursor Cursor(Expr); const TargetRegisterInfo &TRI = *Asm->MF->getSubtarget().getRegisterInfo(); + if (Expr) { + if (auto NewElementsRef = Expr->getNewElementsRef()) { + if (DV.isDivergentAddrSpaceCompatible()) + DwarfExpr.permitDivergentAddrSpace(); + DwarfExpr.addExpression(*NewElementsRef, DVal->getLocEntries(), &TRI); + addBlock(VariableDie, dwarf::DW_AT_location, DwarfExpr.finalize()); + return; + } + } + + DIExpressionCursor Cursor(Expr); + auto AddEntry = [&](const DbgValueLocEntry &Entry, DIExpressionCursor &Cursor) { if (Entry.isLocation()) { @@ -932,6 +968,17 @@ void DwarfCompileUnit::applyConcreteDbgVariableAttributes(const Loc::MMI &MMI, std::optional NVPTXAddressSpace; DIELoc *Loc = new (DIEValueAllocator) DIELoc; DIEDwarfExpression DwarfExpr(*Asm, *this, *Loc); + auto PoisonedExpr = + find_if(MMI.getFrameIndexExprs(), [](const auto &Fragment) { + return Fragment.Expr->holdsOldElements() && Fragment.Expr->isPoisoned(); + }); + if (PoisonedExpr != MMI.getFrameIndexExprs().end()) { + DwarfExpr.addExpression(PoisonedExpr->Expr); + addBlock(VariableDie, dwarf::DW_AT_location, DwarfExpr.finalize()); + return; + } + if (DV.isDivergentAddrSpaceCompatible()) + DwarfExpr.permitDivergentAddrSpace(); for (const auto &Fragment : MMI.getFrameIndexExprs()) { Register FrameReg; const DIExpression *Expr = Fragment.Expr; @@ -941,6 +988,22 @@ void DwarfCompileUnit::applyConcreteDbgVariableAttributes(const Loc::MMI &MMI, DwarfExpr.addFragmentOffset(Expr); auto *TRI = Asm->MF->getSubtarget().getRegisterInfo(); + + if (Expr->holdsNewElements()) { + // TODO: support frame symbol + assert(!Asm->getFunctionFrameSymbol()); + SmallVector ArgLocEntries; + if (FrameReg) + ArgLocEntries.push_back({MachineLocation{FrameReg}}); + else + ArgLocEntries.push_back({int64_t{0}}); + DIExpression *UpdatedExpr = + TFI->lowerFIArgToFPArg(*Asm->MF, Expr, /*ArgIndex=*/0u, Offset); + DwarfExpr.addExpression(*UpdatedExpr->getNewElementsRef(), ArgLocEntries, + TRI); + continue; + } + SmallVector Ops; TRI->getOffsetOpcodes(Offset, Ops); @@ -1643,6 +1706,9 @@ void DwarfCompileUnit::addVariableAddress(const DbgVariable &DV, DIE &Die, /// Add an address attribute to a die based on the location provided. void DwarfCompileUnit::addAddress(DIE &Die, dwarf::Attribute Attribute, const MachineLocation &Location) { + if (DisableDwarfLocations) + return; + DIELoc *Loc = new (DIEValueAllocator) DIELoc; DIEDwarfExpression DwarfExpr(*Asm, *this, *Loc); if (Location.isIndirect()) @@ -1669,6 +1735,9 @@ void DwarfCompileUnit::addAddress(DIE &Die, dwarf::Attribute Attribute, void DwarfCompileUnit::addComplexAddress(const DIExpression *DIExpr, DIE &Die, dwarf::Attribute Attribute, const MachineLocation &Location) { + if (DisableDwarfLocations) + return; + DIELoc *Loc = new (DIEValueAllocator) DIELoc; DIEDwarfExpression DwarfExpr(*Asm, *this, *Loc); DwarfExpr.addFragmentOffset(DIExpr); @@ -1695,6 +1764,9 @@ void DwarfCompileUnit::addComplexAddress(const DIExpression *DIExpr, DIE &Die, /// Add a Dwarf loclistptr attribute data and value. void DwarfCompileUnit::addLocationList(DIE &Die, dwarf::Attribute Attribute, unsigned Index) { + if (DisableDwarfLocations) + return; + dwarf::Form Form = (DD->getDwarfVersion() >= 5) ? dwarf::DW_FORM_loclistx : DD->getDwarfSectionOffsetForm(); @@ -1708,6 +1780,7 @@ void DwarfCompileUnit::applyCommonDbgVariableAttributes(const DbgVariable &Var, addString(VariableDie, dwarf::DW_AT_name, Name); const auto *DIVar = Var.getVariable(); if (DIVar) { + addMemorySpaceAttribute(VariableDie, DIVar->getDWARFMemorySpace()); if (uint32_t AlignInBytes = DIVar->getAlignInBytes()) addUInt(VariableDie, dwarf::DW_AT_alignment, dwarf::DW_FORM_udata, AlignInBytes); @@ -1715,7 +1788,19 @@ void DwarfCompileUnit::applyCommonDbgVariableAttributes(const DbgVariable &Var, } addSourceLine(VariableDie, DIVar); - addType(VariableDie, Var.getType()); + + const DIType *VarTy = Var.getType(); + if (Var.isDivergentAddrSpaceCompatible()) { + if (std::optional EntityAS = Var.getCommonDivergentAddrSpace()) { + if (auto DwarfAS = getAsmPrinter()->TM.mapToDWARFAddrSpace(*EntityAS)) { + TempDIDerivedType Tmp = + cast(VarTy)->cloneWithAddressSpace(*DwarfAS); + VarTy = MDNode::replaceWithUniqued(std::move(Tmp)); + } + } + } + + addType(VariableDie, VarTy); if (Var.isArtificial()) addFlag(VariableDie, dwarf::DW_AT_artificial); } diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h index a3bbc8364599d..9d85f32b61b5f 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h @@ -23,6 +23,7 @@ #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/CodeGen/DbgEntityHistoryCalculator.h" #include "llvm/CodeGen/LexicalScopes.h" +#include "llvm/CodeGen/PseudoSourceValueManager.h" #include "llvm/IR/DebugInfoMetadata.h" #include "llvm/Support/Casting.h" #include diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index 567acf75d1b8d..7fbadad34058f 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -199,6 +199,10 @@ void DebugLocDwarfExpression::emitBaseTypeRef(uint64_t Idx) { getActiveStreamer().emitULEB128(Idx, Twine(Idx), ULEB128PadSize); } +void DebugLocDwarfExpression::emitOpAddress(const GlobalVariable *GV) { + llvm_unreachable("cannot have loc_list for global"); +} + bool DebugLocDwarfExpression::isFrameRegister(const TargetRegisterInfo &TRI, llvm::Register MachineReg) { // This information is not available while emitting .debug_loc entries. @@ -231,6 +235,63 @@ void DebugLocDwarfExpression::commitTemporaryBuffer() { TmpBuf->Comments.clear(); } +namespace { +/// Utility class for finding the common divergent address space of all the +/// DIExpressions that describe the location of a variable, if such an address +/// space exists. +class CommonDivergentAddrSpaceFinder { + std::optional CommonAS; + bool HasCommonAddrSpace = true; + +public: + void addSubExpr(const DIExpression *Expr) { + if (!Expr || !HasCommonAddrSpace) + return; + std::optional ExprAS = Expr->getNewDivergentAddrSpace(); + if (!ExprAS) + HasCommonAddrSpace = false; + else if (!CommonAS) + CommonAS = *ExprAS; + else if (*CommonAS != *ExprAS) + HasCommonAddrSpace = false; + } + + std::optional get() const { + return HasCommonAddrSpace ? CommonAS : std::nullopt; + } +}; +} // namespace + +std::optional DbgVariable::getCommonDivergentAddrSpace() const { + const Loc::Variant *Loc = &asVariant(); + + if (auto *LM = std::get_if(Loc)) + return LM->getCommonDivergentAddrSpace(); + + CommonDivergentAddrSpaceFinder Finder; + if (auto *LS = std::get_if(Loc)) { + Finder.addSubExpr(LS->getExpr()); + } else if (auto *MMI = std::get_if(Loc)) { + for (auto &FIE : MMI->getFrameIndexExprs()) + Finder.addSubExpr(FIE.Expr); + } else if (auto *EV = std::get_if(Loc)) { + for (auto &Val : EV->EntryValues) + Finder.addSubExpr(&Val.Expr); + } + + return Finder.get(); +} + +bool DbgVariable::isDivergentAddrSpaceCompatible() const { + if (auto *DT = dyn_cast(getType())) + return DT->getTag() == dwarf::DW_TAG_pointer_type || + DT->getTag() == dwarf::DW_TAG_reference_type || + DT->getTag() == dwarf::DW_TAG_rvalue_reference_type; + // FIXME: We could support divergent address spaces on pointer/reference + // fields of struct types. + return false; +} + const DIType *DbgVariable::getType() const { return getVariable()->getType(); } @@ -286,7 +347,7 @@ bool llvm::operator<(const EntryValueInfo &LHS, const EntryValueInfo &RHS) { Loc::Single::Single(DbgValueLoc ValueLoc) : ValueLoc(std::make_unique(ValueLoc)), Expr(ValueLoc.getExpression()) { - if (!Expr->getNumElements()) + if (Expr->holdsOldElements() && !Expr->getNumElements()) Expr = nullptr; } @@ -302,7 +363,8 @@ void Loc::MMI::addFrameIndexExpr(const DIExpression *Expr, int FI) { assert((FrameIndexExprs.size() == 1 || llvm::all_of(FrameIndexExprs, [](const FrameIndexExpr &FIE) { - return FIE.Expr && FIE.Expr->isFragment(); + return FIE.Expr && (FIE.Expr->isFragment() || + FIE.Expr->isPoisoned()); })) && "conflicting locations for variable"); } @@ -360,6 +422,8 @@ DwarfDebug::DwarfDebug(AsmPrinter *A) UseARangesSection = GenerateARangeSection || tuneForSCE(); HasAppleExtensionAttributes = tuneForLLDB(); + HasHeterogeneousExtensionAttributes = + Asm->MAI->supportsHeterogeneousDebuggingExtensions(); // Handle split DWARF. HasSplitDwarf = !Asm->TM.Options.MCOptions.SplitDwarfFile.empty(); @@ -1971,6 +2035,18 @@ void DwarfDebug::collectEntityInfo(DwarfCompileUnit &TheCU, continue; } + // If all entries in the location list produce a consistent divergent + // address space we need to inform the expression emitter that it is + // permitted to produce divergent address spaces. + if (RegVar->isDivergentAddrSpaceCompatible()) { + CommonDivergentAddrSpaceFinder Finder; + for (const DebugLocEntry &DLE : Entries) + for (const DbgValueLoc &DVL : DLE.getValues()) + Finder.addSubExpr(DVL.getExpression()); + if (std::optional AS = Finder.get()) + List.setCommonDivergentAddrSpace(*AS); + } + // If the variable has a DIBasicType, extract it. Basic types cannot have // unique identifiers, so don't bother resolving the type with the // identifier map. @@ -3085,7 +3161,6 @@ void DwarfDebug::emitDebugLocEntry(ByteStreamer &Streamer, for (const auto &Op : Expr) { assert(Op.getCode() != dwarf::DW_OP_const_type && "3 operand ops not yet supported"); - assert(!Op.getSubCode() && "SubOps not yet supported"); Streamer.emitInt8(Op.getCode(), Comment != End ? *(Comment++) : ""); Offset++; for (unsigned I = 0; I < Op.getDescription().Op.size(); ++I) { @@ -3110,9 +3185,18 @@ void DwarfDebug::emitDebugLocValue(const AsmPrinter &AP, const DIBasicType *BT, const DbgValueLoc &Value, DwarfExpression &DwarfExpr) { auto *DIExpr = Value.getExpression(); - DIExpressionCursor ExprCursor(DIExpr); DwarfExpr.addFragmentOffset(DIExpr); + if (DIExpr) { + if (auto NewElementsRef = DIExpr->getNewElementsRef()) { + DwarfExpr.addExpression(*NewElementsRef, Value.getLocEntries(), + AP.MF->getSubtarget().getRegisterInfo()); + return; + } + } + + DIExpressionCursor ExprCursor(DIExpr); + // If the DIExpr is an Entry Value, we want to follow the same code path // regardless of whether the DBG_VALUE is variadic or not. if (DIExpr && DIExpr->isEntryValue()) { @@ -3212,7 +3296,9 @@ void DebugLocEntry::finalize(const AsmPrinter &AP, assert(Begin != End && "unexpected location list entry with empty range"); DebugLocStream::EntryBuilder Entry(List, Begin, End); BufferByteStreamer Streamer = Entry.getStreamer(); - DebugLocDwarfExpression DwarfExpr(AP.getDwarfVersion(), Streamer, TheCU); + DebugLocDwarfExpression DwarfExpr(AP, Streamer, TheCU); + if (List.hasCommonDivergentAddrSpace()) + DwarfExpr.permitDivergentAddrSpace(); const DbgValueLoc &Value = Values[0]; if (Value.isFragment()) { // Emit all fragments that belong to the same variable and range. @@ -3428,6 +3514,9 @@ void DwarfDebug::emitDebugLocImpl(MCSection *Sec) { // Emit locations into the .debug_loc/.debug_loclists section. void DwarfDebug::emitDebugLoc() { + if (DisableDwarfLocations) + return; + emitDebugLocImpl( getDwarfVersion() >= 5 ? Asm->getObjFileLowering().getDwarfLoclistsSection() @@ -3436,6 +3525,9 @@ void DwarfDebug::emitDebugLoc() { // Emit locations into the .debug_loc.dwo/.debug_loclists.dwo section. void DwarfDebug::emitDebugLocDWO() { + if (DisableDwarfLocations) + return; + if (getDwarfVersion() >= 5) { emitDebugLocImpl( Asm->getObjFileLowering().getDwarfLoclistsDWOSection()); diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h index 1a1b28a6fc035..8e7062b9f3b37 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h @@ -145,15 +145,25 @@ class Multi { /// DW_OP_LLVM_tag_offset value from DebugLocs. std::optional DebugLocListTagOffset; + /// In DIOp-DIExpressions, if this variable has pointer type and all entries + /// in the loclist produce the same divergent address space, this is set to be + /// the that address space. + std::optional CommonAddrSpace; + public: explicit Multi(unsigned DebugLocListIndex, - std::optional DebugLocListTagOffset) + std::optional DebugLocListTagOffset, + std::optional CommonAddrSpace = std::nullopt) : DebugLocListIndex(DebugLocListIndex), - DebugLocListTagOffset(DebugLocListTagOffset) {} + DebugLocListTagOffset(DebugLocListTagOffset), + CommonAddrSpace(CommonAddrSpace) {} unsigned getDebugLocListIndex() const { return DebugLocListIndex; } std::optional getDebugLocListTagOffset() const { return DebugLocListTagOffset; } + std::optional getCommonDivergentAddrSpace() const { + return CommonAddrSpace; + } }; /// Single location defined by (potentially multiple) MMI entries. struct MMI { @@ -277,6 +287,9 @@ class DbgVariable : public DbgEntity, public Loc::Variant { const DIType *getType() const; + bool isDivergentAddrSpaceCompatible() const; + std::optional getCommonDivergentAddrSpace() const; + static bool classof(const DbgEntity *N) { return N->getDbgEntityID() == DbgVariableKind; } @@ -476,6 +489,9 @@ class DwarfDebug : public DebugHandlerBase { AccelTableKind TheAccelTableKind; bool HasAppleExtensionAttributes; bool HasSplitDwarf; + // Enables extensions defined at + // https://llvm.org/docs/AMDGPUDwarfProposalForHeterogeneousDebugging.html + bool HasHeterogeneousExtensionAttributes; /// Whether to generate the DWARF v5 string offsets table. /// It consists of a series of contributions, each preceded by a header. @@ -819,6 +835,13 @@ class DwarfDebug : public DebugHandlerBase { return HasAppleExtensionAttributes; } + /// Returns whether extensions defined at + /// https://llvm.org/docs/AMDGPUDwarfProposalForHeterogeneousDebugging.html + /// are enabled. + bool useHeterogeneousExtensionAttributes() const { + return HasHeterogeneousExtensionAttributes; + } + /// Returns whether or not to change the current debug info for the /// split dwarf proposal support. bool useSplitDwarf() const { return HasSplitDwarf; } diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp index c7d45897c403b..621f706a101f7 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp @@ -18,9 +18,11 @@ #include "llvm/CodeGen/Register.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/IR/DataLayout.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/Support/ErrorHandling.h" #include +#include using namespace llvm; @@ -42,9 +44,10 @@ void DwarfExpression::emitConstu(uint64_t Value) { void DwarfExpression::addReg(int64_t DwarfReg, const char *Comment) { assert(DwarfReg >= 0 && "invalid negative dwarf register number"); - assert((isUnknownLocation() || isRegisterLocation()) && - "location description already locked down"); - LocationKind = Register; + assert(ASTRoot || (isUnknownLocation() || isRegisterLocation()) && + "location description already locked down"); + if (!ASTRoot) + LocationKind = Register; if (DwarfReg < 32) { emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment); } else { @@ -204,6 +207,8 @@ void DwarfExpression::addBooleanConstant(int64_t Value) { } void DwarfExpression::addSignedConstant(int64_t Value) { + if (IsPoisonedExpr || !IsImplemented) + return; assert(isImplicitLocation() || isUnknownLocation()); LocationKind = Implicit; emitOp(dwarf::DW_OP_consts); @@ -211,12 +216,16 @@ void DwarfExpression::addSignedConstant(int64_t Value) { } void DwarfExpression::addUnsignedConstant(uint64_t Value) { + if (IsPoisonedExpr || !IsImplemented) + return; assert(isImplicitLocation() || isUnknownLocation()); LocationKind = Implicit; emitConstu(Value); } void DwarfExpression::addUnsignedConstant(const APInt &Value) { + if (IsPoisonedExpr || !IsImplemented) + return; assert(isImplicitLocation() || isUnknownLocation()); LocationKind = Implicit; @@ -237,6 +246,8 @@ void DwarfExpression::addUnsignedConstant(const APInt &Value) { } void DwarfExpression::addConstantFP(const APFloat &APF, const AsmPrinter &AP) { + if (IsPoisonedExpr || !IsImplemented) + return; assert(isImplicitLocation() || isUnknownLocation()); APInt API = APF.bitcastToAPInt(); int NumBytes = API.getBitWidth() / 8; @@ -267,6 +278,8 @@ bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI, DIExpressionCursor &ExprCursor, llvm::Register MachineReg, unsigned FragmentOffsetInBits) { + if (IsPoisonedExpr || !IsImplemented) + return true; auto Fragment = ExprCursor.getFragmentInfo(); if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) { LocationKind = Unknown; @@ -358,7 +371,6 @@ bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI, auto Reg = DwarfRegs[0]; bool FBReg = isFrameRegister(TRI, MachineReg); int SignedOffset = 0; - assert(!Reg.isSubRegister() && "full register expected"); // Pattern-match combinations for which more efficient representations exist. // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset]. @@ -390,8 +402,20 @@ bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI, if (FBReg) addFBReg(SignedOffset); - else + else { addBReg(Reg.DwarfRegNo, SignedOffset); + // Compose the remaining subregs. + unsigned ShAmt = Reg.SubRegSize; + for (unsigned i = 1, e = DwarfRegs.size(); i < e; ++i) { + Reg = DwarfRegs[i]; + addBReg(Reg.DwarfRegNo, 0); + emitOp(dwarf::DW_OP_constu); + emitUnsigned(ShAmt); + emitOp(dwarf::DW_OP_shl); + emitOp(dwarf::DW_OP_plus); + ShAmt += Reg.SubRegSize; + } + } DwarfRegs.clear(); // If we need to mask out a subregister, do it now, unless the next @@ -511,6 +535,10 @@ bool DwarfExpression::addExpression( // and not any other parts of the following DWARF expression. assert(!IsEmittingEntryValue && "Can't emit entry value around expression"); + if (!IsImplemented) + return false; + IsPoisonedExpr = false; + std::optional PrevConvertOp; while (ExprCursor) { @@ -526,6 +554,10 @@ bool DwarfExpression::addExpression( } switch (OpNum) { + case dwarf::DW_OP_LLVM_poisoned: + emitUserOp(dwarf::DW_OP_LLVM_undefined); + LocationKind = Unknown; + break; case dwarf::DW_OP_LLVM_arg: if (!InsertArg(Op->getArg(0), ExprCursor)) { LocationKind = Unknown; @@ -735,6 +767,36 @@ bool DwarfExpression::addExpression( return true; } +void DwarfExpression::addExpression(DIExpression::NewElementsRef Expr, + ArrayRef ArgLocEntries, + const TargetRegisterInfo *TRI) { + if (!IsImplemented) + return; + assert(!IsPoisonedExpr && "poisoned exprs should have old elements"); + this->ArgLocEntries = ArgLocEntries; + this->TRI = TRI; + std::optional FragOp; + for (DIOp::Variant Op : Expr) { + if (auto *Frag = std::get_if(&Op)) { + FragOp = *Frag; + IsFragment = true; + break; + } + } + buildAST(Expr); + traverse(ASTRoot.get(), ValueKind::LocationDesc, + /*PermitDivergentAddrSpace=*/ + PermitDivergentAddrSpaceResult && !IsFragment); + if (FragOp) + addOpPiece(FragOp->getBitSize()); + if (!IsImplemented) + emitUserOp(dwarf::DW_OP_LLVM_undefined); + IsFragment = false; + ASTRoot.reset(); + this->TRI = nullptr; + this->ArgLocEntries = {}; +} + /// add masking operations to stencil out a subregister. void DwarfExpression::maskSubRegister() { assert(SubRegisterSizeInBits && "no subregister was registered"); @@ -744,6 +806,11 @@ void DwarfExpression::maskSubRegister() { addAnd(Mask); } +void DwarfExpression::emitUserOp(uint8_t UserOp, const char *Comment) { + emitOp(dwarf::DW_OP_LLVM_user); + emitOp(UserOp); +} + void DwarfExpression::finalize() { assert(DwarfRegs.size() == 0 && "dwarf registers not emitted"); // Emit any outstanding DW_OP_piece operations to mask out subregisters. @@ -756,7 +823,13 @@ void DwarfExpression::finalize() { } void DwarfExpression::addFragmentOffset(const DIExpression *Expr) { - if (!Expr || !Expr->isFragment()) + if (!Expr || !IsImplemented) + return; + + if (Expr->holdsOldElements() && Expr->isPoisoned()) + IsPoisonedExpr = true; + + if (!Expr->isFragment()) return; uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits; @@ -806,6 +879,8 @@ void DwarfExpression::emitLegacyZExt(unsigned FromBits) { } void DwarfExpression::addWasmLocation(unsigned Index, uint64_t Offset) { + if (IsPoisonedExpr || !IsImplemented) + return; emitOp(dwarf::DW_OP_WASM_location); emitUnsigned(Index == 4/*TI_LOCAL_INDIRECT*/ ? 0/*TI_LOCAL*/ : Index); emitUnsigned(Offset); @@ -817,3 +892,459 @@ void DwarfExpression::addWasmLocation(unsigned Index, uint64_t Offset) { LocationKind = Implicit; } } + +static bool isUnsigned(const ConstantInt *CI) { + return (CI->getIntegerType()->getSignBit() & CI->getSExtValue()) == 0; +} + +void DwarfExpression::buildAST(DIExpression::NewElementsRef Elements) { + std::stack> Operands; + + for (const auto &Op : Elements) { + if (std::holds_alternative(Op)) + continue; + std::unique_ptr OpNode = + std::make_unique(Op); + size_t OpChildrenCount = DIOp::getNumInputs(OpNode->getElement()); + if (OpChildrenCount == 0) { + Operands.push(std::move(OpNode)); + } else { + for (size_t I = 0; I < OpChildrenCount; ++I) { + OpNode->getChildren().insert(OpNode->getChildren().begin(), + std::move(Operands.top())); + Operands.pop(); + } + Operands.push(std::move(OpNode)); + } + } + + assert(Operands.size() == 1); + ASTRoot = std::move(Operands.top()); +} + +using NewOpResult = DwarfExpression::OpResult; + +std::optional +DwarfExpression::traverse(Node *OpNode, std::optional ReqVK, + bool PermitDivergentAddrSpace) { + std::optional Result = + std::visit([&](auto &&E) { return traverse(E, OpNode->getChildren()); }, + OpNode->getElement()); + if (!Result) { + IsImplemented = false; + return Result; + } + if (Result->DivergentAddrSpace && !PermitDivergentAddrSpace) { + // FIXME: When DWARF supports address space conversions, generate a + // DW_OP_convert here to convert to the required address space. + IsImplemented = false; + return Result; + } + OpNode->setIsLowered(); + OpNode->setResultType(Result->Ty); + return ReqVK ? convertValueKind(*Result, *ReqVK) : Result; +} + +NewOpResult DwarfExpression::convertValueKind(const NewOpResult &Res, + ValueKind ReqVK) { + if (Res.VK == ValueKind::Value && ReqVK == ValueKind::LocationDesc) { + emitOp(dwarf::DW_OP_stack_value); + return {Res.Ty, ValueKind::LocationDesc, Res.DivergentAddrSpace}; + } + + if (Res.VK == ValueKind::LocationDesc && ReqVK == ValueKind::Value) { + readToValue(Res.Ty); + return {Res.Ty, ValueKind::Value, Res.DivergentAddrSpace}; + } + + return Res; +} + +std::optional DwarfExpression::traverse(DIOp::Arg Arg, + ChildrenT Children) { + uint32_t Index = Arg.getIndex(); + assert(Index < ArgLocEntries.size()); + auto Entry = ArgLocEntries[Index]; + + if (Entry.isGlobal()) { + const GlobalVariable *GV = Entry.getGlobal(); + + // FIXME: This is a workaround to avoid generating symbols for non-global + // address spaces, e.g. LDS. Generate a 'DW_OP_constu' with a dummy + // constant value (0) for now. + unsigned AMDGPUGlobalAddrSpace = 1; + if ((AP.TM.getTargetTriple().getArch() == Triple::amdgcn) && + (GV->getAddressSpace() != AMDGPUGlobalAddrSpace)) { + emitConstu(0); + emitOp(dwarf::DW_OP_stack_value); + return NewOpResult{Arg.getResultType(), ValueKind::LocationDesc}; + } + + // TODO: We only support PIC reloc-model and non-TLS globals so far, see + // DwarfCompileUnit::addLocationAttribute(..., DIGlobalVariable *, ...) for + // what (more) general support might entail. + if (GV->isThreadLocal() || AP.TM.getRelocationModel() != Reloc::PIC_ || + AP.TM.getTargetTriple().isWasm()) + return std::nullopt; + + CU.getDwarfDebug().addArangeLabel(SymbolCU(&CU, AP.getSymbol(GV))); + emitOpAddress(GV); + emitOp(dwarf::DW_OP_stack_value); + return NewOpResult{Arg.getResultType(), ValueKind::LocationDesc}; + } + + if (Entry.isLocation()) { + assert(DwarfRegs.empty() && "unconsumed registers?"); + if (!TRI || !addMachineReg(*TRI, Entry.getLoc().getReg())) { + DwarfRegs.clear(); + return std::nullopt; + } + + // addMachineReg sets DwarfRegs and SubRegister{Size,Offset}InBits. Collect + // them here and reset the fields to avoid hitting any asserts. + decltype(DwarfRegs) Regs; + std::swap(Regs, DwarfRegs); + unsigned SubRegOffset = SubRegisterOffsetInBits; + unsigned SubRegSize = SubRegisterSizeInBits; + SubRegisterOffsetInBits = SubRegisterSizeInBits = 0; + if (SubRegOffset % 8 || SubRegSize % 8) + return std::nullopt; + SubRegOffset /= 8; + SubRegSize /= 8; + + auto focusThreadIfRequired = [this](int64_t DwarfRegNo) { + // FIXME: This should be represented in the DIExpression. + if (auto LaneSize = TRI->getDwarfRegLaneSize(DwarfRegNo, false)) { + emitUserOp(dwarf::DW_OP_LLVM_push_lane); + emitConstu(*LaneSize); + emitOp(dwarf::DW_OP_mul); + emitUserOp(dwarf::DW_OP_LLVM_offset); + } + }; + + if (Regs.size() == 1) { + addReg(Regs[0].DwarfRegNo, Regs[0].Comment); + focusThreadIfRequired(Regs[0].DwarfRegNo); + + if (SubRegOffset) { + emitUserOp(dwarf::DW_OP_LLVM_offset_uconst); + emitUnsigned(SubRegOffset); + } + + // Ignore SubRegSize, no correct consumer can read or write past the end + // of the subregister location. + + return NewOpResult{Arg.getResultType(), ValueKind::LocationDesc}; + } + + assert(SubRegOffset == 0 && SubRegSize == 0 && + "register piece cannot apply to multiple registers"); + + // When emitting fragments, the top element on the stack might be an + // incomplete composite. Push/drop a lit0 so that we don't add the registers + // to the larger composite. + if (IsFragment) + emitOp(dwarf::DW_OP_lit0); + + for (auto &Reg : Regs) { + if (Reg.SubRegSize % 8) + return std::nullopt; + if (Reg.DwarfRegNo >= 0) { + addReg(Reg.DwarfRegNo, Reg.Comment); + focusThreadIfRequired(Regs[0].DwarfRegNo); + } + emitOp(dwarf::DW_OP_piece); + emitUnsigned(Reg.SubRegSize / 8); + } + emitUserOp(dwarf::DW_OP_LLVM_piece_end); + + if (IsFragment) { + emitOp(dwarf::DW_OP_swap); + emitOp(dwarf::DW_OP_drop); + } + + return NewOpResult{Arg.getResultType(), ValueKind::LocationDesc}; + } + + if (Entry.isInt()) { + emitConstu(Entry.getInt()); + } else if (Entry.isConstantFP()) { + // DwarfExpression does not support arguments wider than 64 bits + // (see PR52584). + // TODO: Consider chunking expressions containing overly wide + // arguments into separate pointer-sized fragment expressions. + APInt RawBytes = Entry.getConstantFP()->getValueAPF().bitcastToAPInt(); + if (RawBytes.getBitWidth() > 64) + return std::nullopt; + emitConstu(RawBytes.getZExtValue()); + } else if (Entry.isConstantInt()) { + APInt RawBytes = Entry.getConstantInt()->getValue(); + if (RawBytes.getBitWidth() > 64) + return std::nullopt; + emitConstu(RawBytes.getZExtValue()); + } else if (Entry.isTargetIndexLocation()) { + return std::nullopt; + } else { + llvm_unreachable("Unsupported Entry type."); + } + + return NewOpResult{Arg.getResultType(), ValueKind::Value}; +} + +std::optional DwarfExpression::traverse(DIOp::Constant Constant, + ChildrenT Children) { + ConstantData *LiteralValue = Constant.getLiteralValue(); + + // FIXME: Support ConstantFP? + ConstantInt *IntLiteralValue = dyn_cast(LiteralValue); + if (!IntLiteralValue) + return std::nullopt; + + if (isUnsigned(IntLiteralValue)) { + emitConstu(IntLiteralValue->getZExtValue()); + } else { + emitOp(dwarf::DW_OP_consts); + emitSigned(IntLiteralValue->getSExtValue()); + } + + return NewOpResult{IntLiteralValue->getType(), ValueKind::Value}; +} + +std::optional DwarfExpression::traverse(DIOp::PushLane PushLane, + ChildrenT Children) { + return std::nullopt; +} + +std::optional DwarfExpression::traverse(DIOp::Referrer ReferrerOp, + ChildrenT Children) { + return std::nullopt; +} + +std::optional +DwarfExpression::traverse(DIOp::TypeObject TypeObject, ChildrenT Children) { + return std::nullopt; +} + +std::optional DwarfExpression::traverse(DIOp::AddrOf AddrOf, + ChildrenT Children) { + return std::nullopt; +} + +std::optional DwarfExpression::traverse(DIOp::Convert Convert, + ChildrenT Children) { + auto Child = traverse(Children[0].get(), /*RequiredVK=*/std::nullopt, + /*PermitDivergentAddrSpace=*/true); + if (!Child) + return std::nullopt; + + Type *DestTy = Convert.getResultType(); + if (Child->Ty->isPointerTy() && DestTy->isPointerTy() && + Child->Ty->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { + unsigned DivAddrSpace = Child->DivergentAddrSpace + ? *Child->DivergentAddrSpace + : Child->Ty->getPointerAddressSpace(); + return NewOpResult{DestTy, Child->VK, DivAddrSpace}; + } + + if (!Child->Ty->isIntegerTy() || !DestTy->isIntegerTy()) + return std::nullopt; + + // If we're not dealing with the divergent address space case, Convert + // requires a value operand. + if (Child->VK == ValueKind::LocationDesc) + readToValue(Child->Ty); + + uint64_t ToBits = DestTy->getPrimitiveSizeInBits().getFixedValue(); + uint64_t FromBits = Child->Ty->getPrimitiveSizeInBits().getFixedValue(); + + if (ToBits < FromBits) { + // This function is called "ZExt", but it's actually doing a truncation on + // generic types (operation is "Child & ((1u << ToBits) - 1)"). + emitLegacyZExt(ToBits); + } + return NewOpResult{DestTy, ValueKind::Value}; +} + +std::optional DwarfExpression::traverse(DIOp::ZExt ZExt, + ChildrenT Children) { + auto Child = traverse(Children[0].get(), ValueKind::Value); + if (!Child || !Child->Ty->isIntegerTy()) + return std::nullopt; + + uint64_t FromBits = Child->Ty->getPrimitiveSizeInBits().getFixedValue(); + emitLegacyZExt(FromBits); + return NewOpResult{ZExt.getResultType(), ValueKind::Value}; +} + +std::optional DwarfExpression::traverse(DIOp::SExt SExt, + ChildrenT Children) { + auto Child = traverse(Children[0].get(), ValueKind::Value); + if (!Child || !Child->Ty->isIntegerTy()) + return std::nullopt; + + uint64_t FromBits = Child->Ty->getPrimitiveSizeInBits().getFixedValue(); + emitLegacySExt(FromBits); + return NewOpResult{SExt.getResultType(), ValueKind::Value}; +} + +std::optional DwarfExpression::traverse(DIOp::Deref Deref, + ChildrenT Children) { + auto Child = traverse(Children[0].get(), ValueKind::LocationDesc, + /*PermitDivergentAddrSpace=*/true); + if (!Child) + return std::nullopt; + + // FIXME(KZHURAVL): Support non pointer types? + if (!Child->Ty->isPointerTy()) + return std::nullopt; + + PointerType *PointerResultType = dyn_cast(Child->Ty); + assert(PointerResultType && "Expected PointerType, but got something else"); + + unsigned PointerLLVMAddrSpace = Child->DivergentAddrSpace + ? *Child->DivergentAddrSpace + : PointerResultType->getAddressSpace(); + uint64_t PointerSizeInBits = + AP.getDataLayout().getPointerSizeInBits(PointerLLVMAddrSpace); + assert(PointerSizeInBits % 8 == 0 && "Expected multiple of 8"); + + uint64_t PointerSizeInBytes = PointerSizeInBits / 8; + auto PointerDWARFAddrSpace = AP.TM.mapToDWARFAddrSpace(PointerLLVMAddrSpace); + if (!PointerDWARFAddrSpace) { + LLVM_DEBUG(dbgs() << "Failed to lower DIOpDeref of pointer to addrspace(" + << PointerLLVMAddrSpace + << "): no corresponding DWARF addrspace.\n"); + return std::nullopt; + } + + emitOp(dwarf::DW_OP_deref_size); + emitData1(PointerSizeInBytes); + emitConstu(*PointerDWARFAddrSpace); + emitUserOp(dwarf::DW_OP_LLVM_form_aspace_address); + + // FIXME(KZHURAVL): Is the following result type correct? + return NewOpResult{Deref.getResultType(), ValueKind::LocationDesc}; +} + +std::optional DwarfExpression::traverse(DIOp::Extend Extend, + ChildrenT Children) { + return std::nullopt; +} + +std::optional DwarfExpression::traverse(DIOp::Read Read, + ChildrenT Children) { + auto Child = traverse(Children[0].get(), ValueKind::LocationDesc); + if (!Child) + return std::nullopt; + readToValue(Children[0].get()); + return NewOpResult{Child->Ty, ValueKind::Value}; +} + +std::optional +DwarfExpression::traverse(DIOp::Reinterpret Reinterpret, ChildrenT Children) { + auto Child = traverse(Children[0].get(), ValueKind::LocationDesc, + /*PermitDivergentAddrSpace=*/true); + if (!Child) + return Child; + return NewOpResult{Reinterpret.getResultType(), Child->VK, + Child->DivergentAddrSpace}; +} + +std::optional DwarfExpression::traverse(DIOp::Select Select, + ChildrenT Children) { + return std::nullopt; +} + +std::optional DwarfExpression::traverse(DIOp::Composite Composite, + ChildrenT Children) { + if (IsFragment) + emitOp(dwarf::DW_OP_lit0); + + for (auto &Child : Children) { + auto R = traverse(Child.get(), std::nullopt); + if (!R) + return std::nullopt; + TypeSize Size = R->Ty->getPrimitiveSizeInBits(); + if (!Size.isFixed() || Size.getFixedValue() % 8 != 0) + return std::nullopt; + emitOp(dwarf::DW_OP_piece); + emitUnsigned(Size.getFixedValue() / 8); + } + emitUserOp(dwarf::DW_OP_LLVM_piece_end); + + if (IsFragment) { + emitOp(dwarf::DW_OP_swap); + emitOp(dwarf::DW_OP_drop); + } + + return NewOpResult{Composite.getResultType(), ValueKind::LocationDesc}; +} + +std::optional +DwarfExpression::traverseMathOp(uint8_t DwarfOp, ChildrenT Children) { + auto LHS = traverse(Children[0].get(), ValueKind::Value); + if (!LHS) + return std::nullopt; + auto RHS = traverse(Children[1].get(), ValueKind::Value); + if (!RHS) + return std::nullopt; + + emitOp(DwarfOp); + return NewOpResult{LHS->Ty, ValueKind::Value}; +} + +std::optional +DwarfExpression::traverse(DIOp::ByteOffset ByteOffset, ChildrenT Children) { + auto LHS = traverse(Children[0].get(), ValueKind::LocationDesc); + if (!LHS) + return std::nullopt; + auto RHS = traverse(Children[1].get(), ValueKind::Value); + if (!RHS) + return std::nullopt; + + emitUserOp(dwarf::DW_OP_LLVM_offset); + return NewOpResult{ByteOffset.getResultType(), ValueKind::LocationDesc}; +} + +std::optional DwarfExpression::traverse(DIOp::BitOffset BitOffset, + ChildrenT Children) { + auto LHS = traverse(Children[0].get(), ValueKind::LocationDesc); + if (!LHS) + return std::nullopt; + auto RHS = traverse(Children[1].get(), ValueKind::Value); + if (!RHS) + return std::nullopt; + + emitUserOp(dwarf::DW_OP_LLVM_bit_offset); + return NewOpResult{BitOffset.getResultType(), ValueKind::LocationDesc}; +} + +std::optional DwarfExpression::traverse(DIOp::Fragment Fragment, + ChildrenT Children) { + llvm_unreachable("should have dropped fragments by now"); + return std::nullopt; +} + +void DwarfExpression::readToValue(Type *Ty) { + uint64_t PrimitiveSizeInBits = Ty->getPrimitiveSizeInBits(); + assert(PrimitiveSizeInBits != 0 && "Expected primitive type"); + + uint64_t ByteAlignedPrimitiveSizeInBits = alignTo<8>(PrimitiveSizeInBits); + uint64_t PrimitiveSizeInBytes = ByteAlignedPrimitiveSizeInBits / 8; + bool NeedsMask = ByteAlignedPrimitiveSizeInBits != PrimitiveSizeInBits; + + emitOp(dwarf::DW_OP_deref_size); + emitData1(PrimitiveSizeInBytes); + + if (NeedsMask) { + uint64_t Mask = (1ULL << PrimitiveSizeInBits) - 1ULL; + emitConstu(Mask); + emitOp(dwarf::DW_OP_and); + } +} + +void DwarfExpression::readToValue(DwarfExpression::Node *OpNode) { + assert(OpNode->isLowered() && "Expected lowered node"); + assert(OpNode->getResultType() && "Expected non-null result type"); + readToValue(OpNode->getResultType()); +} diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h index 700e0ec5813ee..8931daf9bb3de 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h @@ -14,6 +14,7 @@ #define LLVM_LIB_CODEGEN_ASMPRINTER_DWARFEXPRESSION_H #include "ByteStreamer.h" +#include "DwarfDebug.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" #include "llvm/IR/DebugInfoMetadata.h" @@ -66,6 +67,7 @@ class DwarfExpression { /// Whether we are currently emitting an entry value operation. bool IsEmittingEntryValue = false; + const AsmPrinter &AP; DwarfCompileUnit &CU; /// The register location, if any. @@ -122,6 +124,9 @@ class DwarfExpression { /// Add masking operations to stencil out a subregister. void maskSubRegister(); + /// Emit DW_OP_LLVM_user followed by the SubOp \p UserOp. + void emitUserOp(uint8_t UserOp, const char *Comment = nullptr); + /// Output a dwarf operand and an optional assembler comment. virtual void emitOp(uint8_t Op, const char *Comment = nullptr) = 0; @@ -135,6 +140,9 @@ class DwarfExpression { virtual void emitBaseTypeRef(uint64_t Idx) = 0; + /// Emit a dwarf op address for the given GlobalValue \p GV. + virtual void emitOpAddress(const GlobalVariable *GV) = 0; + /// Start emitting data to the temporary buffer. The data stored in the /// temporary buffer can be committed to the main output using /// commitTemporaryBuffer(). @@ -221,10 +229,10 @@ class DwarfExpression { ~DwarfExpression() = default; public: - DwarfExpression(unsigned DwarfVersion, DwarfCompileUnit &CU) - : CU(CU), SubRegisterSizeInBits(0), SubRegisterOffsetInBits(0), + DwarfExpression(const AsmPrinter &AP, DwarfCompileUnit &CU) + : AP(AP), CU(CU), SubRegisterSizeInBits(0), SubRegisterOffsetInBits(0), LocationKind(Unknown), SavedLocationKind(Unknown), - LocationFlags(Unknown), DwarfVersion(DwarfVersion) {} + LocationFlags(Unknown), DwarfVersion(AP.getDwarfVersion()) {} /// This needs to be called last to commit any pending changes. void finalize(); @@ -293,6 +301,13 @@ class DwarfExpression { DIExpressionCursor &&Expr, llvm::function_ref InsertArg); + /// Emit all operations in \p Expr, indexing into \p ArgLocEntries to + /// implement any DIOpArg operations. Function local locations require \p + /// TRI present to translate register identifiers. + void addExpression(DIExpression::NewElementsRef Expr, + ArrayRef ArgLocEntries, + const TargetRegisterInfo *TRI = nullptr); + /// If applicable, emit an empty DW_OP_piece / DW_OP_bit_piece to advance to /// the fragment described by \c Expr. void addFragmentOffset(const DIExpression *Expr); @@ -303,6 +318,160 @@ class DwarfExpression { /// Emit location information expressed via WebAssembly location + offset /// The Index is an identifier for locals, globals or operand stack. void addWasmLocation(unsigned Index, uint64_t Offset); + + // Note: All following members are to support expressions containg + // DIExpression::NewElements (i.e. DIOp* expressions). +public: + class Node { + private: + DIOp::Variant Element; + SmallVector> Children; + + bool IsLowered = false; + Type *ResultType = nullptr; + + public: + Node(DIOp::Variant Element) : Element(Element) {} + + const DIOp::Variant &getElement() const { return Element; } + const SmallVector> &getChildren() const { + return Children; + } + + DIOp::Variant &getElement() { return Element; } + SmallVector> &getChildren() { return Children; } + + const bool &isLowered() const { return IsLowered; } + const Type *getResultType() const { return ResultType; } + + bool &isLowered() { return IsLowered; } + Type *getResultType() { return ResultType; } + + void setIsLowered(bool IL = true) { + IsLowered = IL; + } + void setResultType(Type *RT) { ResultType = RT; } + }; + + // An `std::optional` where `nullptr` represents + // `None`. Only present when in a function context. + const TargetRegisterInfo *TRI; + + std::unique_ptr ASTRoot; + ArrayRef ArgLocEntries; + // This is a temporary boolean variable that indicates whether the lowering of + // this expression is supported or not. If the lowering is supported, then + // the expression lowers as expected. If the lowering is not supported, it + // is terminated by a DW_OP_LLVM_undefined operation. + bool IsImplemented = true; + bool IsFragment = false; + + /// Set when emitting a fragment/non-fragment expression that contains a + /// DW_OP_LLVM_poison operation. This matters for correctness in the fragment + /// case, since we need to ensure that we don't add any registers or constants + /// onto the stack. In the non-fragment case it's simply an optimization. + bool IsPoisonedExpr = false; + bool PermitDivergentAddrSpaceResult = false; + + /// Called if we're allowed to produce a stack entry whose address space + /// diverges from the IR type the DIExpression produces. + void permitDivergentAddrSpace() { PermitDivergentAddrSpaceResult = true; } + + void buildAST(DIExpression::NewElementsRef Elements); + + /// Describes a kind of value on the DWARF expression stack. ValueKind::Value + /// is a DWARF5-style value, and ValueKind::LocationDesc is a location + /// description. + enum class ValueKind { + Value, + LocationDesc, + }; + + /// The result of evaluating a DIExpr operation. Describes the value that the + /// operation will push onto the DWARF expression stack. + struct OpResult { + Type *Ty; + ValueKind VK; + // The real address space of this result, if it diverges from Ty's address + // space. + std::optional DivergentAddrSpace = std::nullopt; + }; + + /// Optionally emit DWARF operations to convert the value at the top of the + /// stack to RequiredVK. Nop if Res.VK is RequiredVK. + OpResult convertValueKind(const OpResult &Res, ValueKind RequiredVK); + + void readToValue(Type *Ty); + void readToValue(Node *OpNode); + + using ChildrenT = ArrayRef>; + + /// Dispatch to a specific traverse() function, and convert the result to + /// ReqVK if non-nullopt. If PermitDivergentAddrSpace, then this function may + /// return a pointer in a different address space than the type. + std::optional traverse(Node *OpNode, std::optional ReqVK, + bool PermitDivergentAddrSpace = false); + + std::optional traverse(DIOp::Arg Arg, ChildrenT Children); + std::optional traverse(DIOp::Constant Constant, ChildrenT Children); + std::optional traverse(DIOp::PushLane PushLane, ChildrenT Children); + std::optional traverse(DIOp::Referrer Referrer, ChildrenT Children); + std::optional traverse(DIOp::TypeObject TypeObject, + ChildrenT Children); + std::optional traverse(DIOp::AddrOf AddrOf, ChildrenT Children); + std::optional traverse(DIOp::Convert Convert, ChildrenT Children); + std::optional traverse(DIOp::ZExt ZExt, ChildrenT Children); + std::optional traverse(DIOp::SExt SExt, ChildrenT Children); + std::optional traverse(DIOp::Deref Deref, ChildrenT Children); + std::optional traverse(DIOp::Extend Extend, ChildrenT Children); + std::optional traverse(DIOp::Read Read, ChildrenT Children); + std::optional traverse(DIOp::Reinterpret Reinterpret, + ChildrenT Children); + std::optional traverse(DIOp::Select Select, ChildrenT Children); + std::optional traverse(DIOp::Composite Composite, + ChildrenT Children); + + std::optional traverseMathOp(uint8_t DwarfOp, ChildrenT Children); + std::optional traverse(DIOp::Add Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_plus, Children); + } + std::optional traverse(DIOp::Div Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_div, Children); + } + std::optional traverse(DIOp::Mul Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_mul, Children); + } + std::optional traverse(DIOp::Shl Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_shl, Children); + } + std::optional traverse(DIOp::LShr Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_shr, Children); + } + std::optional traverse(DIOp::AShr Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_shra, Children); + } + std::optional traverse(DIOp::Sub Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_minus, Children); + } + std::optional traverse(DIOp::And Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_and, Children); + } + std::optional traverse(DIOp::Or Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_or, Children); + } + std::optional traverse(DIOp::Xor Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_xor, Children); + } + std::optional traverse(DIOp::Mod Op, ChildrenT Children) { + return traverseMathOp(dwarf::DW_OP_mod, Children); + } + + std::optional traverse(DIOp::BitOffset BitOffset, + ChildrenT Children); + std::optional traverse(DIOp::ByteOffset ByteOffset, + ChildrenT Children); + + std::optional traverse(DIOp::Fragment Fragment, ChildrenT Children); }; /// DwarfExpression implementation for .debug_loc entries. @@ -329,6 +498,8 @@ class DebugLocDwarfExpression final : public DwarfExpression { void emitData1(uint8_t Value) override; void emitBaseTypeRef(uint64_t Idx) override; + void emitOpAddress(const GlobalVariable *GV) override; + void enableTemporaryBuffer() override; void disableTemporaryBuffer() override; unsigned getTemporaryBufferSize() override; @@ -338,14 +509,13 @@ class DebugLocDwarfExpression final : public DwarfExpression { llvm::Register MachineReg) override; public: - DebugLocDwarfExpression(unsigned DwarfVersion, BufferByteStreamer &BS, + DebugLocDwarfExpression(const AsmPrinter &AP, BufferByteStreamer &BS, DwarfCompileUnit &CU) - : DwarfExpression(DwarfVersion, CU), OutBS(BS) {} + : DwarfExpression(AP, CU), OutBS(BS) {} }; /// DwarfExpression implementation for singular DW_AT_location. class DIEDwarfExpression final : public DwarfExpression { - const AsmPrinter &AP; DIELoc &OutDIE; DIELoc TmpDIE; bool IsBuffering = false; @@ -359,6 +529,8 @@ class DIEDwarfExpression final : public DwarfExpression { void emitData1(uint8_t Value) override; void emitBaseTypeRef(uint64_t Idx) override; + void emitOpAddress(const GlobalVariable *GV) override; + void enableTemporaryBuffer() override; void disableTemporaryBuffer() override; unsigned getTemporaryBufferSize() override; @@ -371,6 +543,9 @@ class DIEDwarfExpression final : public DwarfExpression { DIEDwarfExpression(const AsmPrinter &AP, DwarfCompileUnit &CU, DIELoc &DIE); DIELoc *finalize() { + if (!IsImplemented) { + emitUserOp(dwarf::DW_OP_LLVM_undefined); + } DwarfExpression::finalize(); return &OutDIE; } diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp index e40fb768027b8..5f6446af81e3d 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp @@ -38,9 +38,16 @@ using namespace llvm; #define DEBUG_TYPE "dwarfdebug" +bool llvm::DisableDwarfLocations; +static cl::opt DisableDwarfLocationsOpt( + "disable-dwarf-locations", + cl::desc("Disable emitting DWARF location DIE attributes"), + cl::ReallyHidden, cl::location(DisableDwarfLocations), + cl::init(false)); + DIEDwarfExpression::DIEDwarfExpression(const AsmPrinter &AP, DwarfCompileUnit &CU, DIELoc &DIE) - : DwarfExpression(AP.getDwarfVersion(), CU), AP(AP), OutDIE(DIE) {} + : DwarfExpression(AP, CU), OutDIE(DIE) {} void DIEDwarfExpression::emitOp(uint8_t Op, const char* Comment) { CU.addUInt(getActiveDIE(), dwarf::DW_FORM_data1, Op); @@ -62,6 +69,10 @@ void DIEDwarfExpression::emitBaseTypeRef(uint64_t Idx) { CU.addBaseTypeRef(getActiveDIE(), Idx); } +void DIEDwarfExpression::emitOpAddress(const GlobalVariable *GV) { + CU.addOpAddress(getActiveDIE(), AP.getSymbol(GV)); +} + void DIEDwarfExpression::enableTemporaryBuffer() { assert(!IsBuffering && "Already buffering?"); IsBuffering = true; @@ -211,6 +222,11 @@ void DwarfUnit::insertDIE(DIE *D) { MDNodeToDieMap.insert(std::make_pair(nullptr, D)); } +void DwarfUnit::addMemorySpaceAttribute(DIE &D, dwarf::MemorySpace MS) { + if (MS != dwarf::DW_MSPACE_LLVM_none) + addUInt(D, dwarf::DW_AT_LLVM_memory_space, dwarf::DW_FORM_data4, MS); +} + void DwarfUnit::addFlag(DIE &Die, dwarf::Attribute Attribute) { if (DD->getDwarfVersion() >= 4) addAttribute(Die, Attribute, dwarf::DW_FORM_flag_present, DIEInteger(1)); @@ -427,6 +443,8 @@ DIE &DwarfUnit::createAndAddDIE(dwarf::Tag Tag, DIE &Parent, const DINode *N) { void DwarfUnit::addBlock(DIE &Die, dwarf::Attribute Attribute, DIELoc *Loc) { Loc->computeSize(Asm->getDwarfFormParams()); DIELocs.push_back(Loc); // Memoize so we can call the destructor later on. + if (DisableDwarfLocations) + return; addAttribute(Die, Attribute, Loc->BestForm(DD->getDwarfVersion()), Loc); } @@ -890,9 +908,12 @@ void DwarfUnit::constructTypeDIE(DIE &Buffer, const DIDerivedType *DTy) { // If DWARF address space value is other than None, add it. The IR // verifier checks that DWARF address space only exists for pointer // or reference types. - if (DTy->getDWARFAddressSpace()) - addUInt(Buffer, dwarf::DW_AT_address_class, dwarf::DW_FORM_data4, - *DTy->getDWARFAddressSpace()); + if (auto AS = DTy->getDWARFAddressSpace()) { + // TODO: Drop address_class once the debugger adopts address_space + for (auto ASTag : + {dwarf::DW_AT_address_class, dwarf::DW_AT_LLVM_address_space}) + addUInt(Buffer, ASTag, dwarf::DW_FORM_data4, *AS); + } // Add template alias template parameters. if (Tag == dwarf::DW_TAG_template_alias) @@ -910,6 +931,8 @@ void DwarfUnit::constructTypeDIE(DIE &Buffer, const DIDerivedType *DTy) { if (PtrAuthData->authenticatesNullValues()) addFlag(Buffer, dwarf::DW_AT_LLVM_ptrauth_authenticates_null_values); } + + addMemorySpaceAttribute(Buffer, DTy->getDWARFMemorySpace()); } std::optional @@ -1030,6 +1053,7 @@ void DwarfUnit::constructTypeDIE(DIE &Buffer, const DICompositeType *CTy) { // Add name if not anonymous or intermediate type. StringRef Name = CTy->getName(); + uint64_t Size = CTy->getSizeInBits() >> 3; uint16_t Tag = Buffer.getTag(); switch (Tag) { @@ -1192,28 +1216,15 @@ void DwarfUnit::constructTypeDIE(DIE &Buffer, const DICompositeType *CTy) { if (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_class_type || Tag == dwarf::DW_TAG_structure_type || Tag == dwarf::DW_TAG_union_type) { - if (auto *Var = dyn_cast_or_null(CTy->getRawSizeInBits())) { - if (auto *VarDIE = getDIE(Var)) - addDIEEntry(Buffer, dwarf::DW_AT_bit_size, *VarDIE); - } else if (auto *Exp = - dyn_cast_or_null(CTy->getRawSizeInBits())) { - DIELoc *Loc = new (DIEValueAllocator) DIELoc; - DIEDwarfExpression DwarfExpr(*Asm, getCU(), *Loc); - DwarfExpr.setMemoryLocationKind(); - DwarfExpr.addExpression(Exp); - addBlock(Buffer, dwarf::DW_AT_bit_size, DwarfExpr.finalize()); - } else { - uint64_t Size = CTy->getSizeInBits() >> 3; - // Add size if non-zero (derived types might be zero-sized.) - // Ignore the size if it's a non-enum forward decl. - // TODO: Do we care about size for enum forward declarations? - if (Size && - (!CTy->isForwardDecl() || Tag == dwarf::DW_TAG_enumeration_type)) - addUInt(Buffer, dwarf::DW_AT_byte_size, std::nullopt, Size); - else if (!CTy->isForwardDecl()) - // Add zero size if it is not a forward declaration. - addUInt(Buffer, dwarf::DW_AT_byte_size, std::nullopt, 0); - } + // Add size if non-zero (derived types might be zero-sized.) + // Ignore the size if it's a non-enum forward decl. + // TODO: Do we care about size for enum forward declarations? + if (Size && + (!CTy->isForwardDecl() || Tag == dwarf::DW_TAG_enumeration_type)) + addUInt(Buffer, dwarf::DW_AT_byte_size, std::nullopt, Size); + else if (!CTy->isForwardDecl()) + // Add zero size if it is not a forward declaration. + addUInt(Buffer, dwarf::DW_AT_byte_size, std::nullopt, 0); // If we're a forward decl, say so. if (CTy->isForwardDecl()) @@ -1895,118 +1906,74 @@ DIE &DwarfUnit::constructMemberDIE(DIE &Buffer, const DIDerivedType *DT) { addBlock(MemberDie, dwarf::DW_AT_data_member_location, VBaseLocationDie); } else { - uint64_t Size = 0; - uint64_t FieldSize = 0; + uint64_t Size = DT->getSizeInBits(); + uint64_t FieldSize = DD->getBaseTypeSize(DT); + uint32_t AlignInBytes = DT->getAlignInBytes(); + uint64_t OffsetInBytes; bool IsBitfield = DT->isBitField(); - - // Handle the size. - if (DT->getRawSizeInBits() == nullptr) { - // No size, just ignore. - } else if (auto *Var = dyn_cast(DT->getRawSizeInBits())) { - if (auto *VarDIE = getDIE(Var)) - addDIEEntry(MemberDie, dwarf::DW_AT_bit_size, *VarDIE); - } else if (auto *Exp = dyn_cast(DT->getRawSizeInBits())) { - DIELoc *Loc = new (DIEValueAllocator) DIELoc; - DIEDwarfExpression DwarfExpr(*Asm, getCU(), *Loc); - DwarfExpr.setMemoryLocationKind(); - DwarfExpr.addExpression(Exp); - addBlock(MemberDie, dwarf::DW_AT_bit_size, DwarfExpr.finalize()); - } else { - Size = DT->getSizeInBits(); - FieldSize = DD->getBaseTypeSize(DT); - if (IsBitfield) { - // Handle bitfield, assume bytes are 8 bits. - if (DD->useDWARF2Bitfields()) - addUInt(MemberDie, dwarf::DW_AT_byte_size, std::nullopt, - FieldSize / 8); - addUInt(MemberDie, dwarf::DW_AT_bit_size, std::nullopt, Size); - } - } - - // Handle the location. DW_AT_data_bit_offset won't allow an - // expression until DWARF 6, but it can be used as an extension. - // See https://dwarfstd.org/issues/250501.1.html - if (auto *Var = dyn_cast_or_null(DT->getRawOffsetInBits())) { - if (!Asm->TM.Options.DebugStrictDwarf || DD->getDwarfVersion() >= 6) { - if (auto *VarDIE = getDIE(Var)) - addDIEEntry(MemberDie, dwarf::DW_AT_data_bit_offset, *VarDIE); - } - } else if (auto *Expr = - dyn_cast_or_null(DT->getRawOffsetInBits())) { - if (!Asm->TM.Options.DebugStrictDwarf || DD->getDwarfVersion() >= 6) { - DIELoc *Loc = new (DIEValueAllocator) DIELoc; - DIEDwarfExpression DwarfExpr(*Asm, getCU(), *Loc); - DwarfExpr.setMemoryLocationKind(); - DwarfExpr.addExpression(Expr); - addBlock(MemberDie, dwarf::DW_AT_data_bit_offset, DwarfExpr.finalize()); - } - } else { - uint32_t AlignInBytes = DT->getAlignInBytes(); - uint64_t OffsetInBytes; - - if (IsBitfield) { - assert(DT->getOffsetInBits() <= - (uint64_t)std::numeric_limits::max()); - int64_t Offset = DT->getOffsetInBits(); - // We can't use DT->getAlignInBits() here: AlignInBits for member type - // is non-zero if and only if alignment was forced (e.g. _Alignas()), - // which can't be done with bitfields. Thus we use FieldSize here. - uint32_t AlignInBits = FieldSize; - uint32_t AlignMask = ~(AlignInBits - 1); - // The bits from the start of the storage unit to the start of the - // field. - uint64_t StartBitOffset = Offset - (Offset & AlignMask); - // The byte offset of the field's aligned storage unit inside the - // struct. - OffsetInBytes = (Offset - StartBitOffset) / 8; - - if (DD->useDWARF2Bitfields()) { - uint64_t HiMark = (Offset + FieldSize) & AlignMask; - uint64_t FieldOffset = (HiMark - FieldSize); - Offset -= FieldOffset; - - // Maybe we need to work from the other end. - if (Asm->getDataLayout().isLittleEndian()) - Offset = FieldSize - (Offset + Size); - - if (Offset < 0) - addSInt(MemberDie, dwarf::DW_AT_bit_offset, dwarf::DW_FORM_sdata, - Offset); - else - addUInt(MemberDie, dwarf::DW_AT_bit_offset, std::nullopt, - (uint64_t)Offset); - OffsetInBytes = FieldOffset >> 3; - } else { - addUInt(MemberDie, dwarf::DW_AT_data_bit_offset, std::nullopt, + if (IsBitfield) { + // Handle bitfield, assume bytes are 8 bits. + if (DD->useDWARF2Bitfields()) + addUInt(MemberDie, dwarf::DW_AT_byte_size, std::nullopt, FieldSize / 8); + addUInt(MemberDie, dwarf::DW_AT_bit_size, std::nullopt, Size); + + assert(DT->getOffsetInBits() <= + (uint64_t)std::numeric_limits::max()); + int64_t Offset = DT->getOffsetInBits(); + // We can't use DT->getAlignInBits() here: AlignInBits for member type + // is non-zero if and only if alignment was forced (e.g. _Alignas()), + // which can't be done with bitfields. Thus we use FieldSize here. + uint32_t AlignInBits = FieldSize; + uint32_t AlignMask = ~(AlignInBits - 1); + // The bits from the start of the storage unit to the start of the field. + uint64_t StartBitOffset = Offset - (Offset & AlignMask); + // The byte offset of the field's aligned storage unit inside the struct. + OffsetInBytes = (Offset - StartBitOffset) / 8; + + if (DD->useDWARF2Bitfields()) { + uint64_t HiMark = (Offset + FieldSize) & AlignMask; + uint64_t FieldOffset = (HiMark - FieldSize); + Offset -= FieldOffset; + + // Maybe we need to work from the other end. + if (Asm->getDataLayout().isLittleEndian()) + Offset = FieldSize - (Offset + Size); + + if (Offset < 0) + addSInt(MemberDie, dwarf::DW_AT_bit_offset, dwarf::DW_FORM_sdata, Offset); - } + else + addUInt(MemberDie, dwarf::DW_AT_bit_offset, std::nullopt, + (uint64_t)Offset); + OffsetInBytes = FieldOffset >> 3; } else { - // This is not a bitfield. - OffsetInBytes = DT->getOffsetInBits() / 8; - if (AlignInBytes) - addUInt(MemberDie, dwarf::DW_AT_alignment, dwarf::DW_FORM_udata, - AlignInBytes); + addUInt(MemberDie, dwarf::DW_AT_data_bit_offset, std::nullopt, Offset); } + } else { + // This is not a bitfield. + OffsetInBytes = DT->getOffsetInBits() / 8; + if (AlignInBytes) + addUInt(MemberDie, dwarf::DW_AT_alignment, dwarf::DW_FORM_udata, + AlignInBytes); + } - if (DD->getDwarfVersion() <= 2) { - DIELoc *MemLocationDie = new (DIEValueAllocator) DIELoc; - addUInt(*MemLocationDie, dwarf::DW_FORM_data1, - dwarf::DW_OP_plus_uconst); - addUInt(*MemLocationDie, dwarf::DW_FORM_udata, OffsetInBytes); - addBlock(MemberDie, dwarf::DW_AT_data_member_location, MemLocationDie); - } else if (!IsBitfield || DD->useDWARF2Bitfields()) { - // In DWARF v3, DW_FORM_data4/8 in DW_AT_data_member_location are - // interpreted as location-list pointers. Interpreting constants as - // pointers is not expected, so we use DW_FORM_udata to encode the - // constants here. - if (DD->getDwarfVersion() == 3) - addUInt(MemberDie, dwarf::DW_AT_data_member_location, - dwarf::DW_FORM_udata, OffsetInBytes); - else - addUInt(MemberDie, dwarf::DW_AT_data_member_location, std::nullopt, - OffsetInBytes); - } + if (DD->getDwarfVersion() <= 2) { + DIELoc *MemLocationDie = new (DIEValueAllocator) DIELoc; + addUInt(*MemLocationDie, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst); + addUInt(*MemLocationDie, dwarf::DW_FORM_udata, OffsetInBytes); + addBlock(MemberDie, dwarf::DW_AT_data_member_location, MemLocationDie); + } else if (!IsBitfield || DD->useDWARF2Bitfields()) { + // In DWARF v3, DW_FORM_data4/8 in DW_AT_data_member_location are + // interpreted as location-list pointers. Interpreting constants as + // pointers is not expected, so we use DW_FORM_udata to encode the + // constants here. + if (DD->getDwarfVersion() == 3) + addUInt(MemberDie, dwarf::DW_AT_data_member_location, + dwarf::DW_FORM_udata, OffsetInBytes); + else + addUInt(MemberDie, dwarf::DW_AT_data_member_location, std::nullopt, + OffsetInBytes); } } diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h index 9c0b68b315b50..7841ff7fa5952 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h @@ -30,6 +30,8 @@ class DwarfCompileUnit; class MCDwarfDwoLineTable; class MCSymbol; +extern bool DisableDwarfLocations; + //===----------------------------------------------------------------------===// /// This dwarf writer support class manages information associated with a /// source file. @@ -328,6 +330,9 @@ class DwarfUnit : public DIEUnit { /// Get context owner's DIE. DIE *createTypeDIE(const DICompositeType *Ty); + /// Adds the DW_AT_memory_space tag to a DIE + void addMemorySpaceAttribute(DIE &D, dwarf::MemorySpace MS); + /// If this is a named finished type then include it in the list of types for /// the accelerator tables. void updateAcceleratorTables(const DIScope *Context, const DIType *Ty, diff --git a/llvm/lib/CodeGen/CFIInstrInserter.cpp b/llvm/lib/CodeGen/CFIInstrInserter.cpp index 14098bc821617..0d60d17da0cf7 100644 --- a/llvm/lib/CodeGen/CFIInstrInserter.cpp +++ b/llvm/lib/CodeGen/CFIInstrInserter.cpp @@ -262,6 +262,10 @@ void CFIInstrInserter::calculateOutgoingCFAInfo(MBBCFAInfo &MBBInfo) { case MCCFIInstruction::OpNegateRAState: case MCCFIInstruction::OpNegateRAStateWithPC: case MCCFIInstruction::OpGnuArgsSize: + case MCCFIInstruction::OpLLVMRegisterPair: + case MCCFIInstruction::OpLLVMVectorRegisters: + case MCCFIInstruction::OpLLVMVectorOffset: + case MCCFIInstruction::OpLLVMVectorRegisterMask: case MCCFIInstruction::OpLabel: case MCCFIInstruction::OpValOffset: break; diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index 8ea132626a5af..f1637f9785b0e 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -19,6 +19,7 @@ #include "llvm/ADT/MapVector.h" #include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallBitVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" @@ -3542,6 +3543,49 @@ class TypePromotionTransaction { LLVM_DEBUG(dbgs() << "Do: MutateType: " << *Inst << " with " << *NewTy << "\n"); Inst->mutateType(NewTy); + // Handle debug Info + mutateDgbInfo(Inst, NewTy); + } + + void mutateDgbInfo(Instruction *I, Type *Ty) { + SmallVector Dbgs; + findDbgUsers(I, Dbgs); + for (DbgVariableRecord *Dbg : Dbgs) { + DIExpression *Expr = Dbg->getExpression(); + if (!Expr) + continue; + std::optional Elems = + Expr->getNewElementsRef(); + if (!Elems.has_value()) + continue; + // Collect arg of Inst + uint32_t Idx = 0; + SmallBitVector Idxs(Dbg->getNumVariableLocationOps()); + for (auto *VMD : Dbg->location_ops()) { + if (VMD == I) { + Idxs.set(Idx); + } + Idx++; + } + // Replace types + DIExprBuilder Builder(Expr->getContext()); + unsigned long ArgI = 0; + for (auto [I, Op] : enumerate(*Elems)) { + const DIOp::Arg *AsArg = std::get_if(&Op); + const DIOp::Convert *CvtArg = std::get_if(&Op); + if (AsArg && Idxs[AsArg->getIndex()]) { + ArgI = I; + Builder.append(AsArg->getIndex(), Ty); + if (Ty != OrigTy) + Builder.append(OrigTy); + } else if (!(CvtArg && I == ArgI + 1 && + CvtArg->getResultType() == Ty)) { + Builder.append(Op); + } + I++; + } + Dbg->setExpression(Builder.intoExpression()); + } } /// Mutate the instruction back to its original type. @@ -3549,6 +3593,8 @@ class TypePromotionTransaction { LLVM_DEBUG(dbgs() << "Undo: MutateType: " << *Inst << " with " << *OrigTy << "\n"); Inst->mutateType(OrigTy); + // Handle debug Info + mutateDgbInfo(Inst, OrigTy); } }; diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 1fc90d0852aad..5cff1a3425e77 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -2274,6 +2274,9 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, DI.getExpression(), DI.getDebugLoc(), MIRBuilder); return true; } + case Intrinsic::dbg_def: + case Intrinsic::dbg_kill: + report_fatal_error("unsupported DIExpr-based metadata"); case Intrinsic::uadd_with_overflow: return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder); case Intrinsic::sadd_with_overflow: diff --git a/llvm/lib/CodeGen/IntrinsicLowering.cpp b/llvm/lib/CodeGen/IntrinsicLowering.cpp index 1518ead7698be..2685b5c5a530e 100644 --- a/llvm/lib/CodeGen/IntrinsicLowering.cpp +++ b/llvm/lib/CodeGen/IntrinsicLowering.cpp @@ -329,7 +329,9 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) { case Intrinsic::dbg_declare: case Intrinsic::dbg_label: break; // Simply strip out debugging intrinsics - + case Intrinsic::dbg_def: + case Intrinsic::dbg_kill: + report_fatal_error("unsupported DIExpr-based metadata"); case Intrinsic::eh_typeid_for: // Return something different to eh_selector. CI->replaceAllUsesWith(ConstantInt::get(CI->getType(), 1)); diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index 0037bdd270ff3..e4dd25214edce 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -155,6 +155,15 @@ static cl::opt cl::desc("livedebugvalues-stack-ws-limit"), cl::init(250)); +// Limit for the maximum number of stack slot indexes. On targets where this is +// exceeded, this effectivly disables tracking debug locations across spills. +// The spill tracking in MLocTracker performs quite poorly in terms of memory +// and time on targets with a more complicated register file (FIXME). +static cl::opt + StackSlotIdxesLimit("livedebugvalues-max-stack-slot-idxes", cl::Hidden, + cl::desc("livedebugvalues-max-stack-slot-idxes"), + cl::init(128)); + DbgOpID DbgOpID::UndefID = DbgOpID(0xffffffff); /// Tracker for converting machine value locations and variable values into @@ -701,7 +710,7 @@ class TransferTracker { Register Reg = MTracker->LocIdxToLocID[Num.getLoc()]; MachineOperand MO = MachineOperand::CreateReg(Reg, false); PendingDbgValues.push_back(std::make_pair( - VarID, &*emitMOLoc(MO, Var, {NewExpr, Prop.Indirect, false}))); + VarID, &*emitMOLoc(MO, Var, {NewExpr, Prop.Indirect, false, 1}))); return true; } @@ -1137,6 +1146,10 @@ void MLocTracker::writeRegMask(const MachineOperand *MO, unsigned CurBB, } std::optional MLocTracker::getOrTrackSpillLoc(SpillLoc L) { + // Disable spill tracking on targets with a large number of slot idxes. + if (NumSlotIdxes >= StackSlotIdxesLimit) + return std::nullopt; + SpillLocationNo SpillID(SpillLocs.idFor(L)); if (SpillID.id() == 0) { @@ -1687,7 +1700,7 @@ bool InstrRefBasedLDV::transferDebugInstrRef(MachineInstr &MI, // tracker about it. The rest of this LiveDebugValues implementation acts // exactly the same for DBG_INSTR_REFs as DBG_VALUEs (just, the former can // refer to values that aren't immediately available). - DbgValueProperties Properties(Expr, false, true); + DbgValueProperties Properties(Expr, false, true, MI.getNumDebugOperands()); if (VTracker) VTracker->defVar(MI, Properties, DbgOpIDs); @@ -1771,8 +1784,9 @@ bool InstrRefBasedLDV::transferDebugInstrRef(MachineInstr &MI, } if (IsValidUseBeforeDef) { DebugVariableID VID = DVMap.insertDVID(V, MI.getDebugLoc().get()); - TTracker->addUseBeforeDef(VID, {MI.getDebugExpression(), false, true}, - DbgOps, LastUseBeforeDef); + TTracker->addUseBeforeDef( + VID, {MI.getDebugExpression(), false, true, MI.getNumDebugOperands()}, + DbgOps, LastUseBeforeDef); } } @@ -3734,6 +3748,15 @@ bool InstrRefBasedLDV::ExtendRanges(MachineFunction &MF, VTracker = nullptr; TTracker = nullptr; + if (MTracker->NumSlotIdxes >= StackSlotIdxesLimit) { + LLVM_DEBUG( + dbgs() << "Disabling InstrRefBasedLDV spill tracking for " + << MF.getName() + << " since target has too many potential stack slot indexes (" + << MTracker->NumSlotIdxes << ", limit is " << StackSlotIdxesLimit + << ")\n"); + } + SmallVector MLocTransfer; SmallVector vlocs; LiveInsT SavedLiveIns; diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h index e7dab53dae476..d22bfa2ff6647 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h @@ -313,17 +313,23 @@ class SpillLocationNo { /// the value, and Boolean of whether or not it's indirect. class DbgValueProperties { public: - DbgValueProperties(const DIExpression *DIExpr, bool Indirect, bool IsVariadic) - : DIExpr(DIExpr), Indirect(Indirect), IsVariadic(IsVariadic) {} + DbgValueProperties(const DIExpression *DIExpr, bool Indirect, bool IsVariadic, + std::optional NumLocOps = std::nullopt) + : DIExpr(DIExpr), Indirect(Indirect), IsVariadic(IsVariadic), + NumLocOps(NumLocOps + ? *NumLocOps + : (IsVariadic ? DIExpr->getNumLocationOperands() : 1)) {} /// Extract properties from an existing DBG_VALUE instruction. DbgValueProperties(const MachineInstr &MI) { assert(MI.isDebugValue()); - assert(MI.getDebugExpression()->getNumLocationOperands() == 0 || + assert(MI.getDebugExpression()->isPoisoned() || + MI.getDebugExpression()->getNumLocationOperands() == 0 || MI.isDebugValueList() || MI.isUndefDebugValue()); IsVariadic = MI.isDebugValueList(); DIExpr = MI.getDebugExpression(); Indirect = MI.isDebugOffsetImm(); + NumLocOps = MI.getNumDebugOperands(); } bool isJoinable(const DbgValueProperties &Other) const { @@ -332,21 +338,20 @@ class DbgValueProperties { } bool operator==(const DbgValueProperties &Other) const { - return std::tie(DIExpr, Indirect, IsVariadic) == - std::tie(Other.DIExpr, Other.Indirect, Other.IsVariadic); + return std::tie(DIExpr, Indirect, IsVariadic, NumLocOps) == + std::tie(Other.DIExpr, Other.Indirect, Other.IsVariadic, NumLocOps); } bool operator!=(const DbgValueProperties &Other) const { return !(*this == Other); } - unsigned getLocationOpCount() const { - return IsVariadic ? DIExpr->getNumLocationOperands() : 1; - } + unsigned getLocationOpCount() const { return NumLocOps; } const DIExpression *DIExpr; bool Indirect; bool IsVariadic; + unsigned NumLocOps; }; /// TODO: Might pack better if we changed this to a Struct of Arrays, since diff --git a/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp index 94e3a8273e843..743095643d155 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp @@ -12,8 +12,10 @@ #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/DebugInfo.h" #include "llvm/InitializePasses.h" #include "llvm/Pass.h" #include "llvm/PassRegistry.h" @@ -155,7 +157,8 @@ bool LiveDebugValues::run(MachineFunction &MF, bool llvm::debuginfoShouldUseDebugInstrRef(const Triple &T) { // Enable by default on x86_64, disable if explicitly turned off on cmdline. - if (T.getArch() == llvm::Triple::x86_64 && + if ((T.getArch() == llvm::Triple::x86_64 || + T.getArch() == llvm::Triple::amdgcn) && ValueTrackingVariableLocations != cl::boolOrDefault::BOU_FALSE) return true; diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp index 8b72c295416a2..8ed590669a3b0 100644 --- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp +++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp @@ -240,6 +240,11 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) { .Case("window_save", MIToken::kw_cfi_window_save) .Case("negate_ra_sign_state", MIToken::kw_cfi_aarch64_negate_ra_sign_state) + .Case("llvm_register_pair", MIToken::kw_cfi_llvm_register_pair) + .Case("llvm_vector_registers", MIToken::kw_cfi_llvm_vector_registers) + .Case("llvm_vector_offset", MIToken::kw_cfi_llvm_vector_offset) + .Case("llvm_vector_register_mask", + MIToken::kw_cfi_llvm_vector_register_mask) .Case("negate_ra_sign_state_with_pc", MIToken::kw_cfi_aarch64_negate_ra_sign_state_with_pc) .Case("blockaddress", MIToken::kw_blockaddress) diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h index 0627f176b9e00..abac1880f94e0 100644 --- a/llvm/lib/CodeGen/MIRParser/MILexer.h +++ b/llvm/lib/CodeGen/MIRParser/MILexer.h @@ -98,6 +98,10 @@ struct MIToken { kw_cfi_undefined, kw_cfi_window_save, kw_cfi_aarch64_negate_ra_sign_state, + kw_cfi_llvm_register_pair, + kw_cfi_llvm_vector_registers, + kw_cfi_llvm_vector_offset, + kw_cfi_llvm_vector_register_mask, kw_cfi_aarch64_negate_ra_sign_state_with_pc, kw_blockaddress, kw_intrinsic, diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 4795d81e3f348..9ef5164fe5b0b 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -484,6 +484,7 @@ class MIParser { bool parseDILocation(MDNode *&Expr); bool parseMetadataOperand(MachineOperand &Dest); bool parseCFIOffset(int &Offset); + bool parseCFIUnsigned(unsigned &Value); bool parseCFIRegister(unsigned &Reg); bool parseCFIAddressSpace(unsigned &AddressSpace); bool parseCFIEscapeValues(std::string& Values); @@ -1271,6 +1272,7 @@ bool MIParser::parseStandaloneMDNode(MDNode *&Node) { if (parseMDNode(Node)) return true; } else if (Token.is(MIToken::md_diexpr)) { + // FIXME: This should be driven off of the UNIQUED property in Metadata.def if (parseDIExpression(Node)) return true; } else if (Token.is(MIToken::md_dilocation)) { @@ -2475,6 +2477,13 @@ bool MIParser::parseCFIOffset(int &Offset) { return false; } +bool MIParser::parseCFIUnsigned(unsigned &Value) { + if (getUnsigned(Value)) + return true; + lex(); + return false; +} + bool MIParser::parseCFIRegister(unsigned &Reg) { if (Token.isNot(MIToken::NamedRegister)) return error("expected a cfi register"); @@ -2608,6 +2617,69 @@ bool MIParser::parseCFIOperand(MachineOperand &Dest) { case MIToken::kw_cfi_aarch64_negate_ra_sign_state: CFIIndex = MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr)); break; + case MIToken::kw_cfi_llvm_register_pair: { + unsigned Reg, R1, R2; + unsigned R1Size, R2Size; + if (parseCFIRegister(Reg) || expectAndConsume(MIToken::comma) || + parseCFIRegister(R1) || expectAndConsume(MIToken::comma) || + parseCFIUnsigned(R1Size) || expectAndConsume(MIToken::comma) || + parseCFIRegister(R2) || expectAndConsume(MIToken::comma) || + parseCFIUnsigned(R2Size)) + return true; + + CFIIndex = MF.addFrameInst(MCCFIInstruction::createLLVMRegisterPair( + nullptr, Reg, R1, R1Size, R2, R2Size)); + break; + } + case MIToken::kw_cfi_llvm_vector_registers: { + std::vector VectorRegisters; + if (parseCFIRegister(Reg) || expectAndConsume(MIToken::comma)) + return true; + do { + unsigned VR; + unsigned Lane, Size; + if (parseCFIRegister(VR) || expectAndConsume(MIToken::comma) || + parseCFIUnsigned(Lane) || expectAndConsume(MIToken::comma) || + parseCFIUnsigned(Size)) + return true; + VectorRegisters.push_back({VR, Lane, Size}); + } while (consumeIfPresent(MIToken::comma)); + + CFIIndex = MF.addFrameInst(MCCFIInstruction::createLLVMVectorRegisters( + nullptr, Reg, std::move(VectorRegisters))); + break; + } + case MIToken::kw_cfi_llvm_vector_offset: { + unsigned Reg, MaskReg; + unsigned RegSize, MaskRegSize; + int Offset = 0; + + if (parseCFIRegister(Reg) || expectAndConsume(MIToken::comma) || + parseCFIUnsigned(RegSize) || expectAndConsume(MIToken::comma) || + parseCFIRegister(MaskReg) || expectAndConsume(MIToken::comma) || + parseCFIUnsigned(MaskRegSize) || expectAndConsume(MIToken::comma) || + parseCFIOffset(Offset)) + return true; + + CFIIndex = MF.addFrameInst(MCCFIInstruction::createLLVMVectorOffset( + nullptr, Reg, RegSize, MaskReg, MaskRegSize, Offset)); + break; + } + case MIToken::kw_cfi_llvm_vector_register_mask: { + unsigned Reg, SpillReg, MaskReg; + unsigned SpillRegLaneSize, MaskRegSize; + + if (parseCFIRegister(Reg) || expectAndConsume(MIToken::comma) || + parseCFIRegister(SpillReg) || expectAndConsume(MIToken::comma) || + parseCFIUnsigned(SpillRegLaneSize) || + expectAndConsume(MIToken::comma) || parseCFIRegister(MaskReg) || + expectAndConsume(MIToken::comma) || parseCFIUnsigned(MaskRegSize)) + return true; + + CFIIndex = MF.addFrameInst(MCCFIInstruction::createLLVMVectorRegisterMask( + nullptr, Reg, SpillReg, SpillRegLaneSize, MaskReg, MaskRegSize)); + break; + } case MIToken::kw_cfi_aarch64_negate_ra_sign_state_with_pc: CFIIndex = MF.addFrameInst(MCCFIInstruction::createNegateRAStateWithPC(nullptr)); @@ -2965,6 +3037,10 @@ bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx, case MIToken::kw_cfi_undefined: case MIToken::kw_cfi_window_save: case MIToken::kw_cfi_aarch64_negate_ra_sign_state: + case MIToken::kw_cfi_llvm_register_pair: + case MIToken::kw_cfi_llvm_vector_registers: + case MIToken::kw_cfi_llvm_vector_offset: + case MIToken::kw_cfi_llvm_vector_register_mask: case MIToken::kw_cfi_aarch64_negate_ra_sign_state_with_pc: return parseCFIOperand(Dest); case MIToken::kw_blockaddress: diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index bfa5ab274c686..92aa094da26d9 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -45,6 +45,7 @@ #include "llvm/IR/BasicBlock.h" #include "llvm/IR/Constant.h" #include "llvm/IR/DataLayout.h" +#include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/EHPersonalities.h" #include "llvm/IR/Function.h" @@ -336,6 +337,16 @@ MachineFunction::addFrameInst(const MCCFIInstruction &Inst) { return FrameInstructions.size() - 1; } +void MachineFunction::replaceFrameInstRegister(Register FromReg, + Register ToReg) { + const MCRegisterInfo *MCRI = Ctx.getRegisterInfo(); + unsigned DwarfFromReg = MCRI->getDwarfRegNum(FromReg, false); + unsigned DwarfToReg = MCRI->getDwarfRegNum(ToReg, false); + + for (MCCFIInstruction &Inst : FrameInstructions) + Inst.replaceRegister(DwarfFromReg, DwarfToReg); +} + /// This discards all of the MachineBasicBlock numbers and recomputes them. /// This guarantees that the MBB numbers are sequential, dense, and match the /// ordering of the blocks within the function. If a specific MachineBasicBlock @@ -1063,8 +1074,8 @@ void MachineFunction::substituteDebugValuesForInst(const MachineInstr &Old, } auto MachineFunction::salvageCopySSA( - MachineInstr &MI, DenseMap &DbgPHICache) - -> DebugInstrOperandPair { + MachineInstr &MI, DenseMap &DbgPHICache) + -> SalvageCopySSAResult { const TargetInstrInfo &TII = *getSubtarget().getInstrInfo(); // Check whether this copy-like instruction has already been salvaged into @@ -1088,7 +1099,7 @@ auto MachineFunction::salvageCopySSA( } auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI) - -> DebugInstrOperandPair { + -> SalvageCopySSAResult { MachineRegisterInfo &MRI = getRegInfo(); const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); const TargetInstrInfo &TII = *getSubtarget().getInstrInfo(); @@ -1186,7 +1197,8 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI) for (auto &MO : Inst->all_defs()) { if (MO.getReg() != State.first) continue; - return ApplySubregisters({Inst->getDebugInstrNum(), MO.getOperandNo()}); + return {ApplySubregisters({Inst->getDebugInstrNum(), MO.getOperandNo()}), + Inst}; } llvm_unreachable("Vreg def with no corresponding operand?"); @@ -1206,8 +1218,9 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI) if (!TRI.regsOverlap(RegToSeek, MO.getReg())) continue; - return ApplySubregisters( - {ToExamine.getDebugInstrNum(), MO.getOperandNo()}); + return { + ApplySubregisters({ToExamine.getDebugInstrNum(), MO.getOperandNo()}), + &ToExamine}; } } @@ -1228,7 +1241,131 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI) Builder.addReg(State.first); unsigned NewNum = getNewDebugInstrNum(); Builder.addImm(NewNum); - return ApplySubregisters({NewNum, 0u}); + return {ApplySubregisters({NewNum, 0u}), nullptr}; +} + +/// The Op operand to the DBG_INSTR_REF instruction DbgInstr is a virtual +/// register defined by the REG_SEQUENCE instruction RegSeq. In order to +/// finalize DbgInstr to use instruction references, find the defining +/// instruction for each register in the sequence and compose them with a +/// DIOpComposite. +static bool finalizeInstrRefRegSequenceNew( + MachineInstr &DbgInstr, MachineOperand &Op, MachineInstr &RegSeq, + DenseMap &DbgPHICache) { + + const DIExpression *Expr = DbgInstr.getDebugExpression(); + if (Expr->holdsOldElements()) + return false; + + auto &MF = *DbgInstr.getParent()->getParent(); + auto &Ctx = Expr->getContext(); + auto &TRI = *MF.getSubtarget().getRegisterInfo(); + auto &TII = *MF.getSubtarget().getInstrInfo(); + auto &DL = MF.getDataLayout(); + + struct Part { + MachineFunction::DebugInstrOperandPair DbgInstrNum; + unsigned Size; + unsigned Offset; + }; + SmallVector Parts; + + // Walk through the reg sequence, collecting debug-instr-numbers and + // subregister piece sizes and offsets into Parts. + for (unsigned I = 1; I < RegSeq.getNumOperands(); I += 2) { + Register RegOp = RegSeq.getOperand(I).getReg(); + if (!RegOp.isVirtual()) + return false; + + unsigned SubReg = RegSeq.getOperand(I + 1).getImm(); + unsigned SubSize = TRI.getSubRegIdxSize(SubReg); + unsigned SubOffset = TRI.getSubRegIdxOffset(SubReg); + MachineInstr &DefMI = *MF.getRegInfo().def_instr_begin(RegOp); + + if (DefMI.isCopyLike() || TII.isCopyInstr(DefMI)) { + auto P = MF.salvageCopySSA(DefMI, DbgPHICache); + Parts.push_back({P.first, SubSize, SubOffset}); + continue; + } + + // Otherwise, identify the operand number that the VReg refers to. + unsigned OperandIdx = 0; + for (const auto &DefMO : DefMI.operands()) { + if (DefMO.isReg() && DefMO.isDef() && DefMO.getReg() == RegOp) + break; + ++OperandIdx; + } + assert(OperandIdx < DefMI.getNumOperands()); + + // Morph this instr ref to point at the given instruction and operand. + unsigned ID = DefMI.getDebugInstrNum(); + MachineFunction::DebugInstrOperandPair P{ID, OperandIdx}; + Parts.push_back({P, SubSize, SubOffset}); + } + + // Line up the Parts and make sure there aren't any gaps, DIOpComposite can't + // handle that easily. + std::sort(Parts.begin(), Parts.end(), + [](auto &LHS, auto &RHS) { return LHS.Offset < RHS.Offset; }); + for (unsigned I = 1, E = Parts.size(); I < E; ++I) + if (Parts[I - 1].Offset + Parts[I - 1].Size != Parts[I].Offset) + return false; + if (Parts.empty() || Parts[0].Offset) + return false; + + unsigned ArgNoToReplace = 0; + unsigned NumArgs = DbgInstr.getNumDebugOperands(); + assert(NumArgs == Expr->getNewNumLocationOperands()); + for (; ArgNoToReplace != NumArgs; ++ArgNoToReplace) + if (&DbgInstr.getDebugOperand(ArgNoToReplace) == &Op) + break; + if (ArgNoToReplace == NumArgs) + return false; + + auto Elems = Expr->getNewElementsRef(); + auto NewSize = TypeSize::getFixed(Parts.back().Offset + Parts.back().Size); + for (DIOp::Variant Elem : *Elems) { + // Only replace the argument with a composite if it has the same size as the + // parts. + if (auto *Arg = std::get_if(&Elem)) + if (Arg->getIndex() == ArgNoToReplace && + DL.getTypeSizeInBits(Arg->getResultType()) != NewSize) + return false; + } + + Op.ChangeToDbgInstrRef(Parts[0].DbgInstrNum.first, + Parts[0].DbgInstrNum.second); + if (Parts.size() == 1) + return true; + + // Split up the DIOpArg using a DIOpComposite. + DIExprBuilder B{Ctx}; + for (DIOp::Variant Elem : *Elems) { + auto *Arg = std::get_if(&Elem); + if (!Arg || Arg->getIndex() != ArgNoToReplace) { + B.append(Elem); + continue; + } + bool FirstPart = true; + for (const Part &P : Parts) { + // Since these arguments have to line up with the order of the operands on + // the DBG_INSTR_REF, recycle Arg's index first, it lines up with the Op + // that was ChangeToDbgInstrRef'd above. + unsigned ArgNo = FirstPart ? Arg->getIndex() : NumArgs++; + FirstPart = false; + B.append(ArgNo, IntegerType::get(Ctx, P.Size)); + } + B.append(Parts.size(), Arg->getResultType()); + } + + auto *NewExpr = B.intoExpression(); + for (const Part &P : drop_begin(Parts, 1)) + DbgInstr.addOperand(MachineOperand::CreateDbgInstrRef( + P.DbgInstrNum.first, P.DbgInstrNum.second)); + DbgInstr.getDebugExpressionOp().setMetadata(NewExpr); + assert(NewExpr->getNewNumLocationOperands() == + DbgInstr.getNumDebugOperands()); + return true; } void MachineFunction::finalizeDebugInstrRefs() { @@ -1240,7 +1377,7 @@ void MachineFunction::finalizeDebugInstrRefs() { MI.setDebugValueUndef(); }; - DenseMap ArgDbgPHIs; + DenseMap ArgDbgPHIs; for (auto &MBB : *this) { for (auto &MI : MBB) { if (!MI.isDebugRef()) @@ -1248,7 +1385,8 @@ void MachineFunction::finalizeDebugInstrRefs() { bool IsValidRef = true; - for (MachineOperand &MO : MI.debug_operands()) { + for (unsigned I = 0; I < MI.getNumDebugOperands(); ++I) { + MachineOperand &MO = MI.getDebugOperand(I); if (!MO.isReg()) continue; @@ -1270,7 +1408,12 @@ void MachineFunction::finalizeDebugInstrRefs() { // for why this is important. if (DefMI.isCopyLike() || TII->isCopyInstr(DefMI)) { auto Result = salvageCopySSA(DefMI, ArgDbgPHIs); - MO.ChangeToDbgInstrRef(Result.first, Result.second); + if (!Result.second || !Result.second->isRegSequence() || + !finalizeInstrRefRegSequenceNew(MI, MO, *Result.second, + ArgDbgPHIs)) + MO.ChangeToDbgInstrRef(Result.first.first, Result.first.second); + } else if (DefMI.isRegSequence() && + finalizeInstrRefRegSequenceNew(MI, MO, DefMI, ArgDbgPHIs)) { } else { // Otherwise, identify the operand number that the VReg refers to. unsigned OperandIdx = 0; diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 8ad9245a47684..8a5a9d84609a4 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -735,6 +735,10 @@ bool MachineInstr::isIdenticalTo(const MachineInstr &Other, } bool MachineInstr::isEquivalentDbgInstr(const MachineInstr &Other) const { + // FIXME: Actually consider expression equality + if (getDebugExpression()->holdsNewElements() || + Other.getDebugExpression()->holdsNewElements()) + return false; if (!isDebugValueLike() || !Other.isDebugValueLike()) return false; if (getDebugLoc() != Other.getDebugLoc()) @@ -2426,20 +2430,12 @@ static const DIExpression *computeExprForSpill( "Expected inlined-at fields to agree"); const DIExpression *Expr = MI.getDebugExpression(); - if (MI.isIndirectDebugValue()) { - assert(MI.getDebugOffset().getImm() == 0 && - "DBG_VALUE with nonzero offset"); - Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore); - } else if (MI.isDebugValueList()) { - // We will replace the spilled register with a frame index, so - // immediately deref all references to the spilled register. - std::array Ops{{dwarf::DW_OP_deref}}; - for (const MachineOperand *Op : SpilledOperands) { - unsigned OpIdx = MI.getDebugOperandIndex(Op); - Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx); - } - } - return Expr; + SmallBitVector SpilledOpIndexes(MI.getNumDebugOperands()); + for (const MachineOperand *Op : SpilledOperands) + SpilledOpIndexes.set(MI.getDebugOperandIndex(Op)); + unsigned SpillAddrSpace = MI.getMF()->getDataLayout().getAllocaAddrSpace(); + + return DIExpression::spillArgs(Expr, SpilledOpIndexes, SpillAddrSpace); } static const DIExpression *computeExprForSpill(const MachineInstr &MI, Register SpillReg) { diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp index bb9c76ff0c729..d5ed219114757 100644 --- a/llvm/lib/CodeGen/MachineOperand.cpp +++ b/llvm/lib/CodeGen/MachineOperand.cpp @@ -778,6 +778,64 @@ static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, if (MCSymbol *Label = CFI.getLabel()) MachineOperand::printSymbol(OS, *Label); break; + case MCCFIInstruction::OpLLVMRegisterPair: { + const auto &Fields = + CFI.getExtraFields(); + + OS << "llvm_register_pair "; + if (MCSymbol *Label = CFI.getLabel()) + MachineOperand::printSymbol(OS, *Label); + printCFIRegister(CFI.getRegister(), OS, TRI); + OS << ", "; + printCFIRegister(Fields.Reg1, OS, TRI); + OS << ", " << Fields.Reg1SizeInBits << ", "; + printCFIRegister(Fields.Reg2, OS, TRI); + OS << ", " << Fields.Reg2SizeInBits; + break; + } + case MCCFIInstruction::OpLLVMVectorRegisters: { + const auto &Fields = + CFI.getExtraFields(); + + OS << "llvm_vector_registers "; + if (MCSymbol *Label = CFI.getLabel()) + MachineOperand::printSymbol(OS, *Label); + printCFIRegister(CFI.getRegister(), OS, TRI); + for (auto [Reg, Lane, Size] : Fields.VectorRegisters) { + OS << ", "; + printCFIRegister(Reg, OS, TRI); + OS << ", " << Lane << ", " << Size; + } + break; + } + case MCCFIInstruction::OpLLVMVectorOffset: { + const auto &Fields = + CFI.getExtraFields(); + + OS << "llvm_vector_offset "; + if (MCSymbol *Label = CFI.getLabel()) + MachineOperand::printSymbol(OS, *Label); + printCFIRegister(CFI.getRegister(), OS, TRI); + OS << ", " << Fields.RegisterSizeInBits << ", "; + printCFIRegister(Fields.MaskRegister, OS, TRI); + OS << ", " << Fields.MaskRegisterSizeInBits << ", " << CFI.getOffset(); + break; + } + case MCCFIInstruction::OpLLVMVectorRegisterMask: { + const auto &Fields = + CFI.getExtraFields(); + + OS << "llvm_vector_register_mask "; + if (MCSymbol *Label = CFI.getLabel()) + MachineOperand::printSymbol(OS, *Label); + printCFIRegister(CFI.getRegister(), OS, TRI); + OS << ", "; + printCFIRegister(Fields.SpillRegister, OS, TRI); + OS << ", " << Fields.SpillRegisterLaneSizeInBits << ", "; + printCFIRegister(Fields.MaskRegister, OS, TRI); + OS << ", " << Fields.MaskRegisterSizeInBits; + break; + } case MCCFIInstruction::OpNegateRAStateWithPC: OS << "negate_ra_sign_state_with_pc "; if (MCSymbol *Label = CFI.getLabel()) diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index 0be75e073dedd..2d94bb8195011 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -1413,6 +1413,25 @@ bool PEIImpl::replaceFrameIndexDebugInstr(MachineFunction &MF, MachineInstr &MI, unsigned OpIdx, int SPAdj) { const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); + + if (MI.isDebugValue() && MI.getDebugExpression()->holdsNewElements()) { + MachineOperand &Op = MI.getOperand(OpIdx); + Register Reg; + unsigned FrameIdx = Op.getIndex(); + StackOffset Offset = TFI->getFrameIndexReference(MF, FrameIdx, Reg); + + if (Reg) { + Op.ChangeToRegister(Reg, false /*isDef*/); + Op.setIsDebug(); + } else { + Op.ChangeToImmediate(0); + } + + MI.getDebugExpressionOp().setMetadata(TFI->lowerFIArgToFPArg( + MF, MI.getDebugExpression(), MI.getDebugOperandIndex(&Op), Offset)); + return true; + } + if (MI.isDebugValue()) { MachineOperand &Op = MI.getOperand(OpIdx); diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index 697b779e10106..6a0619dd8e0ce 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -1001,6 +1001,7 @@ void RegAllocFastImpl::allocVirtReg(MachineInstr &MI, LiveReg &LR, void RegAllocFastImpl::allocVirtRegUndef(MachineOperand &MO) { assert(MO.isUndef() && "expected undef use"); Register VirtReg = MO.getReg(); + assert(VirtReg.isVirtual() && "Expected virtreg"); if (!shouldAllocateRegister(VirtReg)) return; @@ -1789,7 +1790,7 @@ void RegAllocFastImpl::allocateBasicBlock(MachineBasicBlock &MBB) { Coalesced.clear(); // Traverse block in reverse order allocating instructions one by one. - for (MachineInstr &MI : reverse(MBB)) { + for (MachineInstr &MI : make_early_inc_range(reverse(MBB))) { LLVM_DEBUG(dbgs() << "\n>> " << MI << "Regs:"; dumpState()); // Special handling for debug values. Note that they are not allowed to diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index cf221bba1e3a3..e5691c1f2c184 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -16697,8 +16697,10 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) { } // (conv (conv x, t1), t2) -> (conv x, t2) - if (N0.getOpcode() == ISD::BITCAST) + if (N0.getOpcode() == ISD::BITCAST) { + DAG.salvageDebugInfo(*N0.getNode()); return DAG.getBitcast(VT, N0.getOperand(0)); + } // fold (conv (logicop (conv x), (c))) -> (logicop x, (conv c)) // iff the current bitwise logicop type isn't legal diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index bb10cf687db8d..5d283898d80e1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -808,14 +808,7 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD, return EmitDbgValueFromSingleOp(SD, VRBaseMap); } - // Immediately fold any indirectness from the LLVM-IR intrinsic into the - // expression: - if (SD->isIndirect()) - Expr = DIExpression::append(Expr, dwarf::DW_OP_deref); - // If this is not already a variadic expression, it must be modified to become - // one. - if (!SD->isVariadic()) - Expr = DIExpression::convertToVariadicExpression(Expr); + Expr = DIExpression::convertForInstrRef(Expr, SD->isIndirect()); SmallVector MOs; @@ -883,7 +876,8 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD, // Avoid copy like instructions: they don't define values, only move them. // Leave a virtual-register reference until it can be fixed up later, to // find the underlying value definition. - if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI)) { + if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI) || + (Expr->holdsNewElements() && DefMI->isRegSequence())) { AddVRegOp(VReg); continue; } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 379242ec5a157..b1dfc11e8d30f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -12182,6 +12182,35 @@ void SelectionDAG::salvageDebugInfo(SDNode &N) { dbgs() << " into " << *DbgExpression << '\n'); break; } + case ISD::BITCAST: { + DIExpression *Expr = DV->getExpression(); + if (Expr->holdsOldElements()) + break; + + SDValue N0 = N.getOperand(0); + auto NewLocOps = DV->copyLocationOps(); + bool Changed = false; + for (size_t i = 0; i < NewLocOps.size(); ++i) { + if (NewLocOps[i].getKind() != SDDbgOperand::SDNODE || + NewLocOps[i].getSDNode() != &N) + continue; + NewLocOps[i] = SDDbgOperand::fromNode(N0.getNode(), N0.getResNo()); + Changed = true; + } + assert(Changed && "Salvage target doesn't use N"); + (void)Changed; + + SDDbgValue *Clone = + getDbgValueList(DV->getVariable(), Expr, NewLocOps, + DV->getAdditionalDependencies(), DV->isIndirect(), + DV->getDebugLoc(), DV->getOrder(), DV->isVariadic()); + ClonedDVs.push_back(Clone); + DV->setIsInvalidated(); + DV->setIsEmitted(); + LLVM_DEBUG(dbgs() << "SALVAGE: Rewriting"; N0.getNode()->dumprFull(this); + dbgs() << " into " << *Expr << '\n'); + break; + } } } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index a52265055c88a..386bcda145a54 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -6094,14 +6094,7 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue( /* isKill */ false, /* isDead */ false, /* isUndef */ false, /* isEarlyClobber */ false, /* SubReg */ 0, /* isDebug */ true)}); - - auto *NewDIExpr = FragExpr; - // We don't have an "Indirect" field in DBG_INSTR_REF, fold that into - // the DIExpression. - if (Indirect) - NewDIExpr = DIExpression::prepend(FragExpr, DIExpression::DerefBefore); - SmallVector Ops({dwarf::DW_OP_LLVM_arg, 0}); - NewDIExpr = DIExpression::prependOpcodes(NewDIExpr, Ops); + auto *NewDIExpr = DIExpression::convertForInstrRef(FragExpr, Indirect); return BuildMI(MF, DL, Inst, false, MOs, Variable, NewDIExpr); } else { // Create a completely standard DBG_VALUE. diff --git a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp index 70c3b2cbae9a6..b925ecb4437bc 100644 --- a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp +++ b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp @@ -13,13 +13,17 @@ #include "llvm/ADT/BitVector.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/Attributes.h" +#include "llvm/IR/CallingConv.h" +#include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/Function.h" #include "llvm/IR/InstrTypes.h" +#include "llvm/IR/Module.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/Support/Compiler.h" #include "llvm/Target/TargetMachine.h" @@ -75,6 +79,31 @@ TargetFrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF, getOffsetOfLocalArea()); } +DIExpression *TargetFrameLowering::lowerFIArgToFPArg(const MachineFunction &MF, + const DIExpression *Expr, + uint64_t ArgIndex, + StackOffset Offset) const { + const DataLayout &DL = MF.getDataLayout(); + LLVMContext &Context = MF.getFunction().getParent()->getContext(); + DIExprBuilder Builder(*Expr); + for (auto &&I = Builder.begin(); I != Builder.end(); ++I) { + if (auto *Arg = std::get_if(&*I)) { + if (Arg->getIndex() != ArgIndex) + continue; + Type *ResultType = Arg->getResultType(); + unsigned PointerSizeInBits = + DL.getPointerSizeInBits(ResultType->getPointerAddressSpace()); + auto *IntTy = IntegerType::get(Context, PointerSizeInBits); + ConstantData *C = ConstantInt::get(IntTy, Offset.getFixed(), true); + std::initializer_list IL = {DIOp::Reinterpret(IntTy), + DIOp::Constant(C), DIOp::Add(), + DIOp::Reinterpret(ResultType)}; + I = Builder.insert(++I, IL); + } + } + return Builder.intoExpression(); +} + bool TargetFrameLowering::needsFrameIndexResolution( const MachineFunction &MF) const { return MF.getFrameInfo().hasStackObjects(); diff --git a/llvm/lib/DWARFCFIChecker/DWARFCFIState.cpp b/llvm/lib/DWARFCFIChecker/DWARFCFIState.cpp index bca820fa807c8..4d2d2da8a4445 100644 --- a/llvm/lib/DWARFCFIChecker/DWARFCFIState.cpp +++ b/llvm/lib/DWARFCFIChecker/DWARFCFIState.cpp @@ -161,6 +161,16 @@ dwarf::CFIProgram DWARFCFIState::convert(MCCFIInstruction Directive) { CFIP.addInstruction(dwarf::DW_CFA_val_offset, Directive.getRegister(), Directive.getOffset()); break; + case MCCFIInstruction::OpLLVMRegisterPair: + case MCCFIInstruction::OpLLVMVectorRegisters: + case MCCFIInstruction::OpLLVMVectorOffset: + case MCCFIInstruction::OpLLVMVectorRegisterMask: + // TODO: These should be pretty straightforward to support, but is low + // priority. Similarly the implementation of OpLLVMDefAspaceCfa above + // seem incomplete and should be fixed. + Context->reportWarning(Directive.getLoc(), + "this directive is not supported, ignoring it"); + break; } return CFIP; diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDie.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDie.cpp index db5cc37c93f90..9507388b7c6ce 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDie.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDie.cpp @@ -89,6 +89,20 @@ static void dumpLocationList(raw_ostream &OS, const DWARFFormValue &FormValue, &Offset, OS, U->getBaseAddress(), Ctx.getDWARFObj(), U, DumpOpts, Indent); } +static void dumpDWARFAddressSpace(raw_ostream &OS, + const DWARFFormValue &FormValue, + DIDumpOptions DumpOpts) { + FormValue.dump(OS, DumpOpts); + + auto AddressSpaceAsUInt = FormValue.getAsUnsignedConstant(); + auto GetNameForDWARFAddressSpace = DumpOpts.GetNameForDWARFAddressSpace; + if (GetNameForDWARFAddressSpace && AddressSpaceAsUInt) { + StringRef ASName = GetNameForDWARFAddressSpace(*AddressSpaceAsUInt); + if (!ASName.empty()) + OS << " \"" << ASName << "\""; + } +} + static void dumpLocationExpr(raw_ostream &OS, const DWARFFormValue &FormValue, DWARFUnit *U, unsigned Indent, DIDumpOptions DumpOpts) { @@ -219,6 +233,8 @@ static void dumpAttribute(raw_ostream &OS, const DWARFDie &Die, FormValue.isFormClass(DWARFFormValue::FC_Block))) dumpLocationExpr(OS, FormValue, U, sizeof(BaseIndent) + Indent + 4, DumpOpts); + else if (Attr == dwarf::DW_AT_LLVM_address_space) + dumpDWARFAddressSpace(OS, FormValue, DumpOpts); else FormValue.dump(OS, DumpOpts); diff --git a/llvm/lib/DebugInfo/DWARF/DWARFExpressionPrinter.cpp b/llvm/lib/DebugInfo/DWARF/DWARFExpressionPrinter.cpp index fcd2316c30aef..3d249b5386c4a 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFExpressionPrinter.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFExpressionPrinter.cpp @@ -13,6 +13,7 @@ #include "llvm/Support/Format.h" #include #include +#include using namespace llvm; using namespace dwarf; @@ -355,6 +356,9 @@ bool prettyPrintRegisterOp(DWARFUnit *U, raw_ostream &OS, Opcode == DW_OP_regval_type || SubOpcode == DW_OP_LLVM_aspace_bregx || SubOpcode == DW_OP_LLVM_call_frame_entry_reg) DwarfRegNum = Operands[OpNum++]; + else if (Opcode == DW_OP_LLVM_call_frame_entry_reg || + (SubOpcode && *SubOpcode == DW_OP_LLVM_call_frame_entry_reg)) + DwarfRegNum = Operands[OpNum]; else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx) DwarfRegNum = Opcode - DW_OP_breg0; else diff --git a/llvm/lib/Frontend/OpenMP/OMPContext.cpp b/llvm/lib/Frontend/OpenMP/OMPContext.cpp index 7c56233cfc9bc..5ff3df80c5d35 100644 --- a/llvm/lib/Frontend/OpenMP/OMPContext.cpp +++ b/llvm/lib/Frontend/OpenMP/OMPContext.cpp @@ -123,9 +123,8 @@ OMPContext::OMPContext(bool IsDeviceCompilation, Triple TargetTriple, // The discussion on the list did not seem to have come to an agreed // upon solution. - // LLVM is the "OpenMP vendor" but we could also interpret vendor as the - // target vendor. - ActiveTraits.set(unsigned(TraitProperty::implementation_vendor_llvm)); + // AMD should be the "OpenMP Compiler vendor" for Rocmcc Unified compiler. + ActiveTraits.set(unsigned(TraitProperty::implementation_vendor_amd)); // The user condition true is accepted but not false. ActiveTraits.set(unsigned(TraitProperty::user_condition_true)); diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp index 286ed039b1214..10b2608d95a9c 100644 --- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp +++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp @@ -391,7 +391,7 @@ BasicBlock *llvm::splitBBWithSuffix(IRBuilderBase &Builder, bool CreateBranch, // This function creates a fake integer value and a fake use for the integer // value. It returns the fake value created. This is useful in modeling the // extra arguments to the outlined functions. -Value *createFakeIntVal(IRBuilderBase &Builder, +Value *createFakeIntVal(IRBuilderBase &Builder, Module &M, OpenMPIRBuilder::InsertPointTy OuterAllocaIP, llvm::SmallVectorImpl &ToBeDeleted, OpenMPIRBuilder::InsertPointTy InnerAllocaIP, @@ -400,11 +400,19 @@ Value *createFakeIntVal(IRBuilderBase &Builder, Instruction *FakeVal; AllocaInst *FakeValAddr = Builder.CreateAlloca(Builder.getInt32Ty(), nullptr, Name + ".addr"); + FakeVal = FakeValAddr; + + if (M.getDataLayout().getAllocaAddrSpace() != 0) { + // Add additional casts to enforce pointers in zero address space + FakeVal = new AddrSpaceCastInst( + FakeValAddr, PointerType ::get(M.getContext(), 0), "tid.addr.ascast"); + FakeVal->insertAfter(FakeValAddr->getIterator()); + ToBeDeleted.push_back(FakeVal); + } + ToBeDeleted.push_back(FakeValAddr); - if (AsPtr) { - FakeVal = FakeValAddr; - } else { + if (!AsPtr) { FakeVal = Builder.CreateLoad(Builder.getInt32Ty(), FakeValAddr, Name + ".val"); ToBeDeleted.push_back(FakeVal); @@ -555,7 +563,7 @@ void OpenMPIRBuilder::getKernelArgsVector(TargetKernelArgs &KernelArgs, KernelArgs.RTArgs.MapTypesArray, KernelArgs.RTArgs.MapNamesArray, KernelArgs.RTArgs.MappersArray, - KernelArgs.NumIterations, + KernelArgs.TripCount, Flags, NumTeams3D, NumThreads3D, @@ -669,6 +677,28 @@ OpenMPIRBuilder::getOrCreateRuntimeFunction(Module &M, RuntimeFunction FnID) { return {FnTy, Fn}; } +FunctionCallee OpenMPIRBuilder::unsignedGetOrCreateAtomicCASRuntimeFunction( + Module &M, const StringRef &FunName, Type *RetType, Type *AddrTy, + Type *UpdateTy) { + FunctionType *FnTy = nullptr; + Function *Fn = nullptr; + + FnTy = FunctionType::get(RetType, ArrayRef{AddrTy, UpdateTy}, + /*IsVarArg=*/false); + Fn = M.getFunction(FunName); + + if (!Fn) { + Fn = Function::Create(FnTy, GlobalValue::ExternalLinkage, FunName, M); + // do we need to add attributes? + } + + assert(Fn && "Failed to create custom OpenMP atomic CAS runtime function"); + // Cast the function to the expected type if necessary + Constant *C = ConstantExpr::getBitCast( + Fn, llvm::PointerType::get(Fn->getContext(), /*AddressSpace=*/0)); + return {FnTy, C}; +} + Function *OpenMPIRBuilder::getOrCreateRuntimeFunctionPtr(RuntimeFunction FnID) { FunctionCallee RTLFn = getOrCreateRuntimeFunction(M, FnID); auto *Fn = dyn_cast(RTLFn.getCallee()); @@ -746,6 +776,8 @@ void OpenMPIRBuilder::finalize(Function *Fn) { Extractor.excludeArgFromAggregate(V); Function *OutlinedFn = Extractor.extractCodeRegion(CEAC); + if (Config.isGPU()) + OutlinedFn->addFnAttr(Attribute::AlwaysInline); // Forward target-cpu, target-features attributes to the outlined function. auto TargetCpuAttr = OuterFn->getFnAttribute("target-cpu"); @@ -1217,7 +1249,6 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::emitKernelLaunch( const LocationDescription &Loc, Value *OutlinedFnID, EmitFallbackCallbackTy EmitTargetCallFallbackCB, TargetKernelArgs &Args, Value *DeviceID, Value *RTLoc, InsertPointTy AllocaIP) { - if (!updateToLocation(Loc)) return Loc.IP; @@ -1325,7 +1356,7 @@ Error OpenMPIRBuilder::emitCancelationCheckImpl( static void targetParallelCallback( OpenMPIRBuilder *OMPIRBuilder, Function &OutlinedFn, Function *OuterFn, BasicBlock *OuterAllocaBB, Value *Ident, Value *IfCondition, - Value *NumThreads, Instruction *PrivTID, AllocaInst *PrivTIDAddr, + Value *NumThreads, Instruction *PrivTID, Value *PrivTIDAddr, Value *ThreadID, const SmallVector &ToBeDeleted) { // Add some known attributes. IRBuilder<> &Builder = OMPIRBuilder->Builder; @@ -1350,8 +1381,8 @@ static void targetParallelCallback( // Add alloca for kernel args OpenMPIRBuilder ::InsertPointTy CurrentIP = Builder.saveIP(); Builder.SetInsertPoint(OuterAllocaBB, OuterAllocaBB->getFirstInsertionPt()); - AllocaInst *ArgsAlloca = - Builder.CreateAlloca(ArrayType::get(PtrTy, NumCapturedVars)); + AllocaInst *ArgsAlloca = Builder.CreateAlloca( + ArrayType::get(PtrTy, NumCapturedVars), nullptr, "kernel_arg"); Value *Args = ArgsAlloca; // Add address space cast if array for storing arguments is not allocated // in address space 0 @@ -1412,7 +1443,7 @@ static void targetParallelCallback( static void hostParallelCallback(OpenMPIRBuilder *OMPIRBuilder, Function &OutlinedFn, Function *OuterFn, Value *Ident, Value *IfCondition, - Instruction *PrivTID, AllocaInst *PrivTIDAddr, + Instruction *PrivTID, Value *PrivTIDAddr, const SmallVector &ToBeDeleted) { IRBuilder<> &Builder = OMPIRBuilder->Builder; FunctionCallee RTLFn; @@ -1603,7 +1634,9 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createParallel( AllocaInst *PrivTIDAddr = Builder.CreateAlloca(Int32, nullptr, "tid.addr.local"); - Instruction *PrivTID = Builder.CreateLoad(Int32, PrivTIDAddr, "tid"); + Value *PrivTIDAddrAcast = Builder.CreatePointerBitCastOrAddrSpaceCast( + PrivTIDAddr, Builder.getPtrTy(), PrivTIDAddr->getName() + ".acast"); + Instruction *PrivTID = Builder.CreateLoad(Int32, PrivTIDAddrAcast, "tid"); // Add some fake uses for OpenMP provided arguments. ToBeDeleted.push_back(Builder.CreateLoad(Int32, TIDAddr, "tid.addr.use")); @@ -1642,7 +1675,7 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createParallel( OI.PostOutlineCB = [=, ToBeDeletedVec = std::move(ToBeDeleted)](Function &OutlinedFn) { targetParallelCallback(this, OutlinedFn, OuterFn, OuterAllocaBlock, Ident, - IfCondition, NumThreads, PrivTID, PrivTIDAddr, + IfCondition, NumThreads, PrivTID, PrivTIDAddrAcast, ThreadID, ToBeDeletedVec); }; } else { @@ -1650,7 +1683,7 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createParallel( OI.PostOutlineCB = [=, ToBeDeletedVec = std::move(ToBeDeleted)](Function &OutlinedFn) { hostParallelCallback(this, OutlinedFn, OuterFn, Ident, IfCondition, - PrivTID, PrivTIDAddr, ToBeDeletedVec); + PrivTID, PrivTIDAddrAcast, ToBeDeletedVec); }; } @@ -1980,7 +2013,7 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createTask( // Add the thread ID argument. SmallVector ToBeDeleted; OI.ExcludeArgsFromAggregate.push_back(createFakeIntVal( - Builder, AllocaIP, ToBeDeleted, TaskAllocaIP, "global.tid", false)); + Builder, M, AllocaIP, ToBeDeleted, TaskAllocaIP, "global.tid", false)); OI.PostOutlineCB = [this, Ident, Tied, Final, IfCondition, Dependencies, Mergeable, Priority, EventHandle, TaskAllocaBB, @@ -3932,9 +3965,9 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createReductions( Switch->addCase(Builder.getInt32(1), NonAtomicRedBlock); Switch->addCase(Builder.getInt32(2), AtomicRedBlock); - // Populate the non-atomic reduction using the elementwise reduction function. - // This loads the elements from the global and private variables and reduces - // them before storing back the result to the global variable. + // Populate the non-atomic reduction using the elementwise reduction + // function. This loads the elements from the global and private variables + // and reduces them before storing back the result to the global variable. Builder.SetInsertPoint(NonAtomicRedBlock); for (auto En : enumerate(ReductionInfos)) { const ReductionInfo &RI = En.value(); @@ -4741,7 +4774,8 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::applyStaticWorkshareLoop( Builder.CreateCall(StaticInit, Args); Value *LowerBound = Builder.CreateLoad(IVTy, PLowerBound); Value *InclusiveUpperBound = Builder.CreateLoad(IVTy, PUpperBound); - Value *TripCountMinusOne = Builder.CreateSub(InclusiveUpperBound, LowerBound); + Value *TripCountMinusOne = + Builder.CreateSub(InclusiveUpperBound, LowerBound, "trip_count_minus1"); Value *TripCount = Builder.CreateAdd(TripCountMinusOne, One); CLI->setTripCount(TripCount); @@ -6793,14 +6827,17 @@ OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::createTargetInit( assert(Kernel && "Expected the real kernel to exist"); } + // Set the grid value in the config needed for lowering later on + Config.setGridValue(getGridValue(T, Kernel)); + // Manifest the launch configuration in the metadata matching the kernel // environment. if (Attrs.MinTeams > 1 || Attrs.MaxTeams.front() > 0) writeTeamsForKernel(T, *Kernel, Attrs.MinTeams, Attrs.MaxTeams.front()); + int32_t MaxThreadsVal = Attrs.MaxThreads.front(); // If MaxThreads not set, select the maximum between the default workgroup // size and the MinThreads value. - int32_t MaxThreadsVal = Attrs.MaxThreads.front(); if (MaxThreadsVal < 0) MaxThreadsVal = std::max( int32_t(getGridValue(T, Kernel).GV_Default_WG_Size), Attrs.MinThreads); @@ -6906,7 +6943,7 @@ OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::createTargetInit( UI->eraseFromParent(); // Continue in the "user_code" block, see diagram above and in - // openmp/libomptarget/deviceRTLs/common/include/target.h . + // offload/deviceRTLs/common/include/target.h . return InsertPointTy(UserCodeEntryBB, UserCodeEntryBB->getFirstInsertionPt()); } @@ -7053,7 +7090,6 @@ Error OpenMPIRBuilder::emitTargetRegionFunction( TargetRegionEntryInfo &EntryInfo, FunctionGenCallback &GenerateFunctionCallback, bool IsOffloadEntry, Function *&OutlinedFn, Constant *&OutlinedFnID) { - SmallString<64> EntryFnName; OffloadInfoManager.getTargetRegionEntryFnName(EntryFnName, EntryInfo); @@ -7111,8 +7147,7 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createTargetData( // Disable TargetData CodeGen on Device pass. if (Config.IsTargetDevice.value_or(false)) { if (BodyGenCB) { - InsertPointOrErrorTy AfterIP = - BodyGenCB(Builder.saveIP(), BodyGenTy::NoPriv); + InsertPointOrErrorTy AfterIP = BodyGenCB(CodeGenIP, BodyGenTy::NoPriv); if (!AfterIP) return AfterIP.takeError(); Builder.restoreIP(*AfterIP); @@ -7313,6 +7348,24 @@ OpenMPIRBuilder::createForStaticInitFunction(unsigned IVSize, bool IVSigned, return getOrCreateRuntimeFunction(M, Name); } +FunctionCallee +OpenMPIRBuilder::createMDDistributeForStaticInitFunction(unsigned IVSize, + bool IVSigned) { + assert((IVSize == 32 || IVSize == 64) && + "IV size is not compatible with the omp runtime"); + RuntimeFunction Name; + Name = + IVSize == 32 + ? (IVSigned + ? omp::OMPRTL___kmpc_distribute_static_init_multi_device_4 + : omp::OMPRTL___kmpc_distribute_static_init_multi_device_4u) + : (IVSigned + ? omp::OMPRTL___kmpc_distribute_static_init_multi_device_8 + : omp::OMPRTL___kmpc_distribute_static_init_multi_device_8u); + + return getOrCreateRuntimeFunction(M, Name); +} + FunctionCallee OpenMPIRBuilder::createDispatchInitFunction(unsigned IVSize, bool IVSigned) { assert((IVSize == 32 || IVSize == 64) && @@ -7376,7 +7429,8 @@ static void FixupDebugInfoForOutlinedFunction( NewVar = llvm::DILocalVariable::get( Builder.getContext(), OldVar->getScope(), OldVar->getName(), OldVar->getFile(), OldVar->getLine(), OldVar->getType(), arg, - OldVar->getFlags(), OldVar->getAlignInBits(), OldVar->getAnnotations()); + OldVar->getFlags(), OldVar->getDWARFMemorySpace(), + OldVar->getAlignInBits(), OldVar->getAnnotations()); return NewVar; }; @@ -7390,6 +7444,53 @@ static void FixupDebugInfoForOutlinedFunction( ArgNo = std::get<1>(Iter->second) + 1; } } + + Module *M = Func->getParent(); + if ((Triple(M->getTargetTriple())).isAMDGPU()) { + // For target side, the ArgAccessorFuncCB/createDeviceArgumentAccessor + // adds following for the kenel arguments. + // %3 = alloca ptr, align 8, addrspace(5), !dbg !26 + // %4 = addrspacecast ptr addrspace(5) %3 to ptr, !dbg !26 + // store ptr %1, ptr %4, align 8, !dbg !26 + + // For arguments that are passed by ref, there is an extra load like the + // following. + // %8 = load ptr, ptr %4, align 8 + // + // The debug record at this moment may be pointing to %8 (in above + // snippet) as location of variable. The AMDGPU backend drops the debug + // info for variable in such cases. So we change the location to alloca + // instead. + if (DR->getNumVariableLocationOps() != 1u) + return; + auto Loc = DR->getVariableLocationOp(0u); + bool PassByRef = false; + if (llvm::LoadInst *Load = dyn_cast(Loc)) { + Loc = Load->getPointerOperand(); + PassByRef = true; + } + // Add DIOps based expression. Note that we generate an extra indirection + // if an argument is mapped by reference. The first reads the pointer + // from alloca and 2nd read the value of the variable from that pointer. + // We have 2 options for the variables that are mapped byRef. + // 1. Use a single indirection but change the type to the reference to the + // original type. It will show up in the debugger as + // "x=@0x7ffeec820000: 5" + // This is similar to what clang does. + // 2. Use double indirection and keep the original type. It will show up + // in debugger as "x=5". This approached is used here as it is + // consistent with the normal fortran parameters display. + if (auto AI = dyn_cast(Loc->stripPointerCasts())) { + DR->replaceVariableLocationOp(0u, AI); + llvm::DIExprBuilder ExprBuilder(Builder.getContext()); + ExprBuilder.append(0u, AI->getType()); + if (PassByRef) + ExprBuilder.append(AI->getAllocatedType()); + ExprBuilder.append(AI->getAllocatedType()); + DR->setExpression(ExprBuilder.intoExpression()); + } + } + if (ArgNo != 0) DR->setVariable(GetUpdatedDIVariable(OldVar, ArgNo)); }; @@ -7736,6 +7837,7 @@ static Function *emitTargetTaskProxyFunction( Value *SharedsSize = Builder.getInt64(M.getDataLayout().getTypeStoreSize(ArgStructType)); + LoadInst *LoadShared = loadSharedDataFromTaskDescriptor( OMPBuilder, Builder, TaskWithPrivates, TaskWithPrivatesTy); @@ -7749,7 +7851,6 @@ static Function *emitTargetTaskProxyFunction( return ProxyFn; } static Type *getOffloadingArrayType(Value *V) { - if (auto *GEP = dyn_cast(V)) return GEP->getSourceElementType(); if (auto *Alloca = dyn_cast(V)) @@ -7758,6 +7859,7 @@ static Type *getOffloadingArrayType(Value *V) { llvm_unreachable("Unhandled Instruction type"); return nullptr; } + // This function returns a struct that has at most two members. // The first member is always %struct.kmp_task_ompbuilder_t, that is the task // descriptor. The second member, if needed, is a struct containing arrays @@ -7801,7 +7903,6 @@ static Error emitTargetOutlinedFunction( SmallVectorImpl &Inputs, OpenMPIRBuilder::TargetBodyGenCallbackTy &CBFunc, OpenMPIRBuilder::TargetGenArgAccessorsCallbackTy &ArgAccessorFuncCB) { - OpenMPIRBuilder::FunctionGenCallback &&GenerateOutlinedFunction = [&](StringRef EntryFnName) { return createOutlinedFunction(OMPBuilder, Builder, DefaultAttrs, @@ -7956,8 +8057,9 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::emitTargetTask( // Add the thread ID argument. SmallVector ToBeDeleted; - OI.ExcludeArgsFromAggregate.push_back(createFakeIntVal( - Builder, AllocaIP, ToBeDeleted, TargetTaskAllocaIP, "global.tid", false)); + OI.ExcludeArgsFromAggregate.push_back( + createFakeIntVal(Builder, M, AllocaIP, ToBeDeleted, TargetTaskAllocaIP, + "global.tid", false)); // Generate the task body which will subsequently be outlined. Builder.restoreIP(TargetTaskBodyIP); @@ -8120,8 +8222,13 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::emitTargetTask( Builder.CreateStructGEP(TaskWithPrivatesTy, TaskData, 1); for (unsigned int i = 0; i < OffloadingArraysToPrivatize.size(); ++i) { Value *PtrToPrivatize = OffloadingArraysToPrivatize[i]; - [[maybe_unused]] Type *ArrayType = - getOffloadingArrayType(PtrToPrivatize); + [[maybe_unused]] Type *ArrayType = nullptr; + if (auto *GEP = dyn_cast(PtrToPrivatize)) + ArrayType = GEP->getSourceElementType(); + else if (auto *Alloca = dyn_cast(PtrToPrivatize)) + ArrayType = Alloca->getAllocatedType(); + else + llvm_unreachable("Unhandled Instruction type"); assert(ArrayType && "ArrayType cannot be nullptr"); Type *ElementType = PrivatesTy->getElementType(i); @@ -8285,7 +8392,7 @@ static void emitTargetCall( /*RTLoc=*/nullptr, AllocaIP, Dependencies, EmptyRTArgs, HasNoWait); } - return EmitTargetCallFallbackCB(Builder.saveIP()); + return EmitTargetCallFallbackCB(CodeGenIP); }()); Builder.restoreIP(AfterIP); @@ -8299,7 +8406,7 @@ static void emitTargetCall( OpenMPIRBuilder::MapInfosTy &MapInfo = GenMapInfoCB(Builder.saveIP()); OpenMPIRBuilder::TargetDataRTArgs RTArgs; if (Error Err = OMPBuilder.emitOffloadingArraysAndArgs( - AllocaIP, Builder.saveIP(), Info, RTArgs, MapInfo, CustomMapperCB, + AllocaIP, CodeGenIP, Info, RTArgs, MapInfo, CustomMapperCB, /*IsNonContiguous=*/true, /*ForEndCall=*/false)) return Err; @@ -9962,9 +10069,9 @@ OpenMPIRBuilder::createTeams(const LocationDescription &Loc, SmallVector ToBeDeleted; InsertPointTy OuterAllocaIP(&OuterAllocaBB, OuterAllocaBB.begin()); OI.ExcludeArgsFromAggregate.push_back(createFakeIntVal( - Builder, OuterAllocaIP, ToBeDeleted, AllocaIP, "gid", true)); + Builder, M, OuterAllocaIP, ToBeDeleted, AllocaIP, "gid", true)); OI.ExcludeArgsFromAggregate.push_back(createFakeIntVal( - Builder, OuterAllocaIP, ToBeDeleted, AllocaIP, "tid", true)); + Builder, M, OuterAllocaIP, ToBeDeleted, AllocaIP, "tid", true)); auto HostPostOutlineCB = [this, Ident, ToBeDeleted](Function &OutlinedFn) mutable { diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 3c222f54fd406..da1df7f2a55ef 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -1895,6 +1895,8 @@ struct MDFieldPrinter { void printEmissionKind(StringRef Name, DICompileUnit::DebugEmissionKind EK); void printNameTableKind(StringRef Name, DICompileUnit::DebugNameTableKind NTK); + void printMemorySpace(StringRef Name, dwarf::MemorySpace MS); + template void printMetadataList(StringRef Name, RangeT Range); void printFixedPointKind(StringRef Name, DIFixedPointType::FixedPointKind V); }; @@ -2040,6 +2042,20 @@ void MDFieldPrinter::printEmissionKind(StringRef Name, Out << FS << Name << ": " << DICompileUnit::emissionKindString(EK); } +void MDFieldPrinter::printMemorySpace(StringRef Name, dwarf::MemorySpace MS) { + if (MS == dwarf::DW_MSPACE_LLVM_none) + return; + + StringRef MSStr = dwarf::MemorySpaceString(MS); + + Out << FS << Name << ": "; + if (MSStr.empty()) { + Out << static_cast(MS); + } else { + Out << MSStr; + } +} + void MDFieldPrinter::printNameTableKind(StringRef Name, DICompileUnit::DebugNameTableKind NTK) { if (NTK == DICompileUnit::DebugNameTableKind::Default) @@ -2047,6 +2063,19 @@ void MDFieldPrinter::printNameTableKind(StringRef Name, Out << FS << Name << ": " << DICompileUnit::nameTableKindString(NTK); } +template +void MDFieldPrinter::printMetadataList(StringRef Name, RangeT Range) { + if (Range.begin() == Range.end()) + return; + Out << FS << Name << ": {"; + ListSeparator IFS; + for (const auto &I : Range) { + Out << IFS; + writeMetadataAsOperand(Out, I, WriterCtx); + } + Out << "}"; +} + void MDFieldPrinter::printFixedPointKind(StringRef Name, DIFixedPointType::FixedPointKind V) { Out << FS << Name << ": " << DIFixedPointType::fixedPointKindString(V); @@ -2072,15 +2101,7 @@ static void writeGenericDINode(raw_ostream &Out, const GenericDINode *N, MDFieldPrinter Printer(Out, WriterCtx); Printer.printTag(N); Printer.printString("header", N->getHeader()); - if (N->getNumDwarfOperands()) { - Out << Printer.FS << "operands: {"; - ListSeparator IFS; - for (auto &I : N->dwarf_operands()) { - Out << IFS; - writeMetadataAsOperand(Out, I, WriterCtx); - } - Out << "}"; - } + Printer.printMetadataList("operands", N->dwarf_operands()); Out << ")"; } @@ -2264,8 +2285,9 @@ static void writeDIDerivedType(raw_ostream &Out, const DIDerivedType *N, Printer.printDIFlags("flags", N->getFlags()); Printer.printMetadata("extraData", N->getRawExtraData()); if (const auto &DWARFAddressSpace = N->getDWARFAddressSpace()) - Printer.printInt("dwarfAddressSpace", *DWARFAddressSpace, + Printer.printInt("addressSpace", *DWARFAddressSpace, /* ShouldSkipZero */ false); + Printer.printMemorySpace("memorySpace", N->getDWARFMemorySpace()); Printer.printMetadata("annotations", N->getRawAnnotations()); if (auto PtrAuthData = N->getPtrAuthData()) { Printer.printInt("ptrAuthKey", PtrAuthData->key()); @@ -2563,6 +2585,7 @@ static void writeDIGlobalVariable(raw_ostream &Out, const DIGlobalVariable *N, Printer.printBool("isDefinition", N->isDefinition()); Printer.printMetadata("declaration", N->getRawStaticDataMemberDeclaration()); Printer.printMetadata("templateParams", N->getRawTemplateParams()); + Printer.printMemorySpace("memorySpace", N->getDWARFMemorySpace()); Printer.printInt("align", N->getAlignInBits()); Printer.printMetadata("annotations", N->getRawAnnotations()); Out << ")"; @@ -2579,6 +2602,7 @@ static void writeDILocalVariable(raw_ostream &Out, const DILocalVariable *N, Printer.printInt("line", N->getLine()); Printer.printMetadata("type", N->getRawType()); Printer.printDIFlags("flags", N->getFlags()); + Printer.printMemorySpace("memorySpace", N->getDWARFMemorySpace()); Printer.printInt("align", N->getAlignInBits()); Printer.printMetadata("annotations", N->getRawAnnotations()); Out << ")"; @@ -2600,9 +2624,9 @@ static void writeDILabel(raw_ostream &Out, const DILabel *N, Out << ")"; } -static void writeDIExpression(raw_ostream &Out, const DIExpression *N, - AsmWriterContext &WriterCtx) { - Out << "!DIExpression("; +static void writeDIExpressionImpl(raw_ostream &Out, const DIExpression *N, + AsmWriterContext &WriterCtx, + DIExpression::OldElementsRef) { ListSeparator FS; if (N->isValid()) { for (const DIExpression::ExprOperand &Op : N->expr_ops()) { @@ -2622,6 +2646,80 @@ static void writeDIExpression(raw_ostream &Out, const DIExpression *N, for (const auto &I : N->getElements()) Out << FS << I; } +} + +static void writeDIExpressionImpl(raw_ostream &Out, const DIExpression *N, + AsmWriterContext &WriterCtx, + DIExpression::NewElementsRef Elements) { + assert(WriterCtx.TypePrinter && "DIExpr require TypePrinting!"); + assert(!Elements.empty() && "DIOp-based DIExpression cannot be empty"); + ListSeparator FS; + for (auto Op : Elements) { + Out << FS << DIOp::getAsmName(Op) << '('; + std::visit( + makeVisitor( +#define HANDLE_OP0(NAME) [](DIOp::NAME) {}, +#include "llvm/IR/DIExprOps.def" +#undef HANDLE_OP0 + [&](DIOp::Referrer Referrer) { + WriterCtx.TypePrinter->print(Referrer.getResultType(), Out); + }, + [&](DIOp::Arg Arg) { + Out << Arg.getIndex() << ", "; + WriterCtx.TypePrinter->print(Arg.getResultType(), Out); + }, + [&](DIOp::TypeObject TypeObject) { + WriterCtx.TypePrinter->print(TypeObject.getResultType(), Out); + }, + [&](DIOp::Constant Constant) { + WriterCtx.TypePrinter->print( + Constant.getLiteralValue()->getType(), Out); + Out << ' '; + writeConstantInternal(Out, Constant.getLiteralValue(), WriterCtx); + }, + [&](DIOp::Convert Convert) { + WriterCtx.TypePrinter->print(Convert.getResultType(), Out); + }, + [&](DIOp::ZExt ZExt) { + WriterCtx.TypePrinter->print(ZExt.getResultType(), Out); + }, + [&](DIOp::SExt SExt) { + WriterCtx.TypePrinter->print(SExt.getResultType(), Out); + }, + [&](DIOp::Reinterpret Reinterpret) { + WriterCtx.TypePrinter->print(Reinterpret.getResultType(), Out); + }, + [&](DIOp::BitOffset BitOffset) { + WriterCtx.TypePrinter->print(BitOffset.getResultType(), Out); + }, + [&](DIOp::ByteOffset ByteOffset) { + WriterCtx.TypePrinter->print(ByteOffset.getResultType(), Out); + }, + [&](DIOp::Composite Composite) { + Out << Composite.getCount() << ", "; + WriterCtx.TypePrinter->print(Composite.getResultType(), Out); + }, + [&](DIOp::Extend Extend) { Out << Extend.getCount(); }, + [&](DIOp::AddrOf AddrOf) { Out << AddrOf.getAddressSpace(); }, + [&](DIOp::Deref Deref) { + WriterCtx.TypePrinter->print(Deref.getResultType(), Out); + }, + [&](DIOp::PushLane PushLane) { + WriterCtx.TypePrinter->print(PushLane.getResultType(), Out); + }, + [&](DIOp::Fragment Fragment) { + Out << Fragment.getBitOffset() << ", " << Fragment.getBitSize(); + }), + Op); + Out << ')'; + } +} + +static void writeDIExpression(raw_ostream &Out, const DIExpression *N, + AsmWriterContext &WriterCtx) { + Out << "!DIExpression("; + std::visit([&](auto E) { writeDIExpressionImpl(Out, N, WriterCtx, E); }, + N->getElementsRef()); Out << ")"; } @@ -3782,6 +3880,7 @@ static void printMetadataIdentifier(StringRef Name, } void AssemblyWriter::printNamedMDNode(const NamedMDNode *NMD) { + AsmWriterContext WriterCtx(&TypePrinter, &Machine, NMD->getParent()); Out << '!'; printMetadataIdentifier(NMD->getName(), Out); Out << " = !{"; @@ -3791,7 +3890,7 @@ void AssemblyWriter::printNamedMDNode(const NamedMDNode *NMD) { // Write DIExpressions inline. // FIXME: Ban DIExpressions in NamedMDNodes, they will serve no purpose. if (auto *Expr = dyn_cast(Op)) { - writeDIExpression(Out, Expr, AsmWriterContext::getEmpty()); + writeDIExpression(Out, Expr, WriterCtx); continue; } diff --git a/llvm/lib/IR/Attributes.cpp b/llvm/lib/IR/Attributes.cpp index 4ac2ebd55dcac..65815cbd70f32 100644 --- a/llvm/lib/IR/Attributes.cpp +++ b/llvm/lib/IR/Attributes.cpp @@ -507,6 +507,10 @@ FPClassTest Attribute::getNoFPClass() const { return static_cast(pImpl->getValueAsInt()); } +bool Attribute::isSanitizedPaddedGlobal() const { + return hasAttribute(Attribute::SanitizedPaddedGlobal); +} + const ConstantRange &Attribute::getRange() const { assert(hasAttribute(Attribute::Range) && "Trying to get range args from non-range attribute"); @@ -678,6 +682,9 @@ std::string Attribute::getAsString(bool InAttrGrp) const { return Result; } + if (hasAttribute(Attribute::SanitizedPaddedGlobal)) + return "sanitized_padded_global"; + if (hasAttribute(Attribute::Range)) { std::string Result; raw_string_ostream OS(Result); diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index b838e36c8824f..92aaac9514c89 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -5494,7 +5494,8 @@ bool llvm::UpgradeDebugInfo(Module &M) { } } - if (Version == DEBUG_METADATA_VERSION) { + bool VersionSupported = Version == DEBUG_METADATA_VERSION; + if (VersionSupported) { bool BrokenDebugInfo = false; if (verifyModule(M, &llvm::errs(), &BrokenDebugInfo)) report_fatal_error("Broken module found, compilation aborted!"); @@ -5508,7 +5509,7 @@ bool llvm::UpgradeDebugInfo(Module &M) { } } bool Modified = StripDebugInfo(M); - if (Modified && Version != DEBUG_METADATA_VERSION) { + if (Modified && !VersionSupported) { // Diagnose a version mismatch. DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); M.getContext().diagnose(DiagVersion); diff --git a/llvm/lib/IR/DIBuilder.cpp b/llvm/lib/IR/DIBuilder.cpp index 07a870f0630a5..b8fc5819730e1 100644 --- a/llvm/lib/IR/DIBuilder.cpp +++ b/llvm/lib/IR/DIBuilder.cpp @@ -322,7 +322,7 @@ DIStringType *DIBuilder::createStringType(StringRef Name, DIDerivedType *DIBuilder::createQualifiedType(unsigned Tag, DIType *FromTy) { return DIDerivedType::get(VMContext, Tag, "", nullptr, 0, nullptr, FromTy, - (uint64_t)0, 0, (uint64_t)0, std::nullopt, + (uint64_t)0, 0, (uint64_t)0, std::nullopt, dwarf::DW_MSPACE_LLVM_none, std::nullopt, DINode::FlagZero); } @@ -333,6 +333,7 @@ DIDerivedType *DIBuilder::createPtrAuthQualifiedType( return DIDerivedType::get( VMContext, dwarf::DW_TAG_LLVM_ptrauth_type, "", nullptr, 0, nullptr, FromTy, (uint64_t)0, 0, (uint64_t)0, std::nullopt, + dwarf::DW_MSPACE_LLVM_none, std::optional( std::in_place, Key, IsAddressDiscriminated, ExtraDiscriminator, IsaPointer, AuthenticatesNullValues), @@ -343,11 +344,12 @@ DIDerivedType * DIBuilder::createPointerType(DIType *PointeeTy, uint64_t SizeInBits, uint32_t AlignInBits, std::optional DWARFAddressSpace, + dwarf::MemorySpace DWARFMemorySpace, StringRef Name, DINodeArray Annotations) { // FIXME: Why is there a name here? return DIDerivedType::get(VMContext, dwarf::DW_TAG_pointer_type, Name, nullptr, 0, nullptr, PointeeTy, SizeInBits, - AlignInBits, 0, DWARFAddressSpace, std::nullopt, + AlignInBits, 0, DWARFAddressSpace, DWARFMemorySpace, std::nullopt, DINode::FlagZero, nullptr, Annotations); } @@ -358,17 +360,17 @@ DIDerivedType *DIBuilder::createMemberPointerType(DIType *PointeeTy, DINode::DIFlags Flags) { return DIDerivedType::get(VMContext, dwarf::DW_TAG_ptr_to_member_type, "", nullptr, 0, nullptr, PointeeTy, SizeInBits, - AlignInBits, 0, std::nullopt, std::nullopt, Flags, - Base); + AlignInBits, 0, std::nullopt, + dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, Base); } -DIDerivedType * -DIBuilder::createReferenceType(unsigned Tag, DIType *RTy, uint64_t SizeInBits, - uint32_t AlignInBits, - std::optional DWARFAddressSpace) { +DIDerivedType *DIBuilder::createReferenceType( + unsigned Tag, DIType *RTy, uint64_t SizeInBits, uint32_t AlignInBits, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS) { + assert(RTy && "Unable to create reference type"); return DIDerivedType::get(VMContext, Tag, "", nullptr, 0, nullptr, RTy, - SizeInBits, AlignInBits, 0, DWARFAddressSpace, {}, + SizeInBits, AlignInBits, 0, DWARFAddressSpace, MS, {}, DINode::FlagZero); } @@ -379,7 +381,7 @@ DIDerivedType *DIBuilder::createTypedef(DIType *Ty, StringRef Name, DINodeArray Annotations) { return DIDerivedType::get(VMContext, dwarf::DW_TAG_typedef, Name, File, LineNo, getNonCompileUnitScope(Context), Ty, - (uint64_t)0, AlignInBits, (uint64_t)0, std::nullopt, + (uint64_t)0, AlignInBits, (uint64_t)0, std::nullopt, dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, nullptr, Annotations); } @@ -391,6 +393,7 @@ DIBuilder::createTemplateAlias(DIType *Ty, StringRef Name, DIFile *File, return DIDerivedType::get(VMContext, dwarf::DW_TAG_template_alias, Name, File, LineNo, getNonCompileUnitScope(Context), Ty, (uint64_t)0, AlignInBits, (uint64_t)0, std::nullopt, + dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, TParams.get(), Annotations); } @@ -399,6 +402,7 @@ DIDerivedType *DIBuilder::createFriend(DIType *Ty, DIType *FriendTy) { assert(FriendTy && "Invalid friend type!"); return DIDerivedType::get(VMContext, dwarf::DW_TAG_friend, "", nullptr, 0, Ty, FriendTy, (uint64_t)0, 0, (uint64_t)0, std::nullopt, + dwarf::DW_MSPACE_LLVM_none, std::nullopt, DINode::FlagZero); } @@ -411,17 +415,17 @@ DIDerivedType *DIBuilder::createInheritance(DIType *Ty, DIType *BaseTy, ConstantInt::get(IntegerType::get(VMContext, 32), VBPtrOffset)); return DIDerivedType::get(VMContext, dwarf::DW_TAG_inheritance, "", nullptr, 0, Ty, BaseTy, 0, 0, BaseOffset, std::nullopt, - std::nullopt, Flags, ExtraData); + dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, ExtraData); } DIDerivedType *DIBuilder::createMemberType( DIScope *Scope, StringRef Name, DIFile *File, unsigned LineNumber, uint64_t SizeInBits, uint32_t AlignInBits, uint64_t OffsetInBits, DINode::DIFlags Flags, DIType *Ty, DINodeArray Annotations) { - return DIDerivedType::get(VMContext, dwarf::DW_TAG_member, Name, File, - LineNumber, getNonCompileUnitScope(Scope), Ty, - SizeInBits, AlignInBits, OffsetInBits, std::nullopt, - std::nullopt, Flags, nullptr, Annotations); + return DIDerivedType::get( + VMContext, dwarf::DW_TAG_member, Name, File, LineNumber, + getNonCompileUnitScope(Scope), Ty, SizeInBits, AlignInBits, OffsetInBits, + std::nullopt, dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, nullptr, Annotations); } DIDerivedType *DIBuilder::createMemberType( @@ -431,6 +435,7 @@ DIDerivedType *DIBuilder::createMemberType( return DIDerivedType::get(VMContext, dwarf::DW_TAG_member, Name, File, LineNumber, getNonCompileUnitScope(Scope), Ty, SizeInBits, AlignInBits, OffsetInBits, std::nullopt, + dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, nullptr, Annotations); } @@ -447,10 +452,11 @@ DIDerivedType *DIBuilder::createVariantMemberType( // "ExtraData" is overloaded for bit fields and for variants, so // make sure to disallow this. assert((Flags & DINode::FlagBitField) == 0); - return DIDerivedType::get( - VMContext, dwarf::DW_TAG_member, Name, File, LineNumber, - getNonCompileUnitScope(Scope), Ty, SizeInBits, AlignInBits, OffsetInBits, - std::nullopt, std::nullopt, Flags, getConstantOrNull(Discriminant)); + return DIDerivedType::get(VMContext, dwarf::DW_TAG_member, Name, File, + LineNumber, getNonCompileUnitScope(Scope), Ty, + SizeInBits, AlignInBits, OffsetInBits, std::nullopt, + dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, + getConstantOrNull(Discriminant)); } DIDerivedType *DIBuilder::createVariantMemberType(DIScope *Scope, @@ -475,7 +481,7 @@ DIDerivedType *DIBuilder::createBitFieldMemberType( return DIDerivedType::get( VMContext, dwarf::DW_TAG_member, Name, File, LineNumber, getNonCompileUnitScope(Scope), Ty, SizeInBits, /*AlignInBits=*/0, - OffsetInBits, std::nullopt, std::nullopt, Flags, + OffsetInBits, std::nullopt, dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, ConstantAsMetadata::get(ConstantInt::get(IntegerType::get(VMContext, 64), StorageOffsetInBits)), Annotations); @@ -489,7 +495,7 @@ DIDerivedType *DIBuilder::createBitFieldMemberType( return DIDerivedType::get( VMContext, dwarf::DW_TAG_member, Name, File, LineNumber, getNonCompileUnitScope(Scope), Ty, SizeInBits, /*AlignInBits=*/0, - OffsetInBits, std::nullopt, std::nullopt, Flags, + OffsetInBits, std::nullopt, dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, ConstantAsMetadata::get(ConstantInt::get(IntegerType::get(VMContext, 64), StorageOffsetInBits)), Annotations); @@ -504,6 +510,7 @@ DIBuilder::createStaticMemberType(DIScope *Scope, StringRef Name, DIFile *File, return DIDerivedType::get(VMContext, Tag, Name, File, LineNumber, getNonCompileUnitScope(Scope), Ty, (uint64_t)0, AlignInBits, (uint64_t)0, std::nullopt, + dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, getConstantOrNull(Val)); } @@ -515,7 +522,7 @@ DIBuilder::createObjCIVar(StringRef Name, DIFile *File, unsigned LineNumber, return DIDerivedType::get(VMContext, dwarf::DW_TAG_member, Name, File, LineNumber, getNonCompileUnitScope(File), Ty, SizeInBits, AlignInBits, OffsetInBits, std::nullopt, - std::nullopt, Flags, PropertyNode); + dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, PropertyNode); } DIObjCProperty * @@ -673,7 +680,7 @@ DIDerivedType *DIBuilder::createSetType(DIScope *Scope, StringRef Name, auto *R = DIDerivedType::get(VMContext, dwarf::DW_TAG_set_type, Name, File, LineNo, getNonCompileUnitScope(Scope), Ty, SizeInBits, AlignInBits, 0, std::nullopt, - std::nullopt, DINode::FlagZero); + dwarf::DW_MSPACE_LLVM_none, std::nullopt, DINode::FlagZero); trackIfUnresolved(R); return R; } @@ -873,17 +880,30 @@ static void checkGlobalVariableScope(DIScope *Context) { #endif } +DIGlobalVariable *DIBuilder::createGlobalVariable( + DIScope *Context, StringRef Name, StringRef LinkageName, DIFile *F, + unsigned LineNumber, DIType *Ty, bool IsLocalToUnit, bool isDefined, + MDNode *Decl, MDTuple *TemplateParams, dwarf::MemorySpace MS, + uint32_t AlignInBits, DINodeArray Annotations) { + checkGlobalVariableScope(Context); + return DIGlobalVariable::getDistinct( + VMContext, cast_or_null(Context), Name, LinkageName, F, + LineNumber, Ty, IsLocalToUnit, isDefined, + cast_or_null(Decl), TemplateParams, MS, AlignInBits, + Annotations); +} + DIGlobalVariableExpression *DIBuilder::createGlobalVariableExpression( DIScope *Context, StringRef Name, StringRef LinkageName, DIFile *F, unsigned LineNumber, DIType *Ty, bool IsLocalToUnit, bool isDefined, DIExpression *Expr, MDNode *Decl, MDTuple *TemplateParams, - uint32_t AlignInBits, DINodeArray Annotations) { + dwarf::MemorySpace MS, uint32_t AlignInBits, DINodeArray Annotations) { checkGlobalVariableScope(Context); auto *GV = DIGlobalVariable::getDistinct( VMContext, cast_or_null(Context), Name, LinkageName, F, LineNumber, Ty, IsLocalToUnit, isDefined, - cast_or_null(Decl), TemplateParams, AlignInBits, + cast_or_null(Decl), TemplateParams, MS, AlignInBits, Annotations); if (!Expr) Expr = createExpression(); @@ -895,13 +915,13 @@ DIGlobalVariableExpression *DIBuilder::createGlobalVariableExpression( DIGlobalVariable *DIBuilder::createTempGlobalVariableFwdDecl( DIScope *Context, StringRef Name, StringRef LinkageName, DIFile *F, unsigned LineNumber, DIType *Ty, bool IsLocalToUnit, MDNode *Decl, - MDTuple *TemplateParams, uint32_t AlignInBits) { + MDTuple *TemplateParams, dwarf::MemorySpace MS, uint32_t AlignInBits) { checkGlobalVariableScope(Context); return DIGlobalVariable::getTemporary( VMContext, cast_or_null(Context), Name, LinkageName, F, LineNumber, Ty, IsLocalToUnit, false, - cast_or_null(Decl), TemplateParams, AlignInBits, + cast_or_null(Decl), TemplateParams, MS, AlignInBits, nullptr) .release(); } @@ -911,12 +931,13 @@ static DILocalVariable *createLocalVariable( SmallVectorImpl &PreservedNodes, DIScope *Context, StringRef Name, unsigned ArgNo, DIFile *File, unsigned LineNo, DIType *Ty, bool AlwaysPreserve, DINode::DIFlags Flags, - uint32_t AlignInBits, DINodeArray Annotations = nullptr) { + dwarf::MemorySpace MS, uint32_t AlignInBits, + DINodeArray Annotations = nullptr) { // FIXME: Why doesn't this check for a subprogram or lexical block (AFAICT // the only valid scopes)? auto *Scope = cast(Context); auto *Node = DILocalVariable::get(VMContext, Scope, Name, File, LineNo, Ty, - ArgNo, Flags, AlignInBits, Annotations); + ArgNo, Flags, MS, AlignInBits, Annotations); if (AlwaysPreserve) { // The optimizer may remove local variables. If there is an interest // to preserve variable info in such situation then stash it in a @@ -930,24 +951,25 @@ DILocalVariable *DIBuilder::createAutoVariable(DIScope *Scope, StringRef Name, DIFile *File, unsigned LineNo, DIType *Ty, bool AlwaysPreserve, DINode::DIFlags Flags, + dwarf::MemorySpace MS, uint32_t AlignInBits) { assert(Scope && isa(Scope) && "Unexpected scope for a local variable."); return createLocalVariable( VMContext, getSubprogramNodesTrackingVector(Scope), Scope, Name, - /* ArgNo */ 0, File, LineNo, Ty, AlwaysPreserve, Flags, AlignInBits); + /* ArgNo */ 0, File, LineNo, Ty, AlwaysPreserve, Flags, MS, AlignInBits); } DILocalVariable *DIBuilder::createParameterVariable( DIScope *Scope, StringRef Name, unsigned ArgNo, DIFile *File, unsigned LineNo, DIType *Ty, bool AlwaysPreserve, DINode::DIFlags Flags, - DINodeArray Annotations) { + dwarf::MemorySpace MS, DINodeArray Annotations) { assert(ArgNo && "Expected non-zero argument number for parameter"); assert(Scope && isa(Scope) && "Unexpected scope for a local variable."); return createLocalVariable( VMContext, getSubprogramNodesTrackingVector(Scope), Scope, Name, ArgNo, - File, LineNo, Ty, AlwaysPreserve, Flags, /*AlignInBits=*/0, Annotations); + File, LineNo, Ty, AlwaysPreserve, Flags, MS, /*AlignInBits=*/0, Annotations); } DILabel *DIBuilder::createLabel(DIScope *Context, StringRef Name, DIFile *File, diff --git a/llvm/lib/IR/DIExpressionOptimizer.cpp b/llvm/lib/IR/DIExpressionOptimizer.cpp index be9e13a34235a..5e4bfab173093 100644 --- a/llvm/lib/IR/DIExpressionOptimizer.cpp +++ b/llvm/lib/IR/DIExpressionOptimizer.cpp @@ -286,6 +286,9 @@ static bool tryFoldCommutativeMathWithArgInBetween( } DIExpression *DIExpression::foldConstantMath() { + if (holdsNewElements()) + return this; + auto Elements = getElements(); SmallVector WorkingOps(Elements.begin(), Elements.end()); uint64_t Loc = 0; diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp index 58836068a4929..bf8aacc67cc10 100644 --- a/llvm/lib/IR/DebugInfo.cpp +++ b/llvm/lib/IR/DebugInfo.cpp @@ -1029,6 +1029,21 @@ static LLVMDIFlags map_to_llvmDIFlags(DINode::DIFlags Flags) { return static_cast(Flags); } +static MemorySpace map_to_llvmMSPACE(LLVMDWARFMemorySpace MS) { + switch (MS) { +#define HANDLE_DW_MSPACE(ID, NAME) \ + case ID: \ + return DW_MSPACE_LLVM_##NAME; +#include "llvm/BinaryFormat/Dwarf.def" + default: + if (MemorySpace::DW_MSPACE_LLVM_lo_user <= MS && + MS <= MemorySpace::DW_MSPACE_LLVM_hi_user) + return static_cast(MS); + break; + } + llvm_unreachable("LLVMDWARFMemorySpace out-of-range"); +} + static DISubprogram::DISPFlags pack_into_DISPFlags(bool IsLocalToUnit, bool IsDefinition, bool IsOptimized) { return DISubprogram::toSPFlags(IsLocalToUnit, IsDefinition, IsOptimized); @@ -1432,12 +1447,12 @@ LLVMDIBuilderCreateBasicType(LLVMDIBuilderRef Builder, const char *Name, } LLVMMetadataRef LLVMDIBuilderCreatePointerType( - LLVMDIBuilderRef Builder, LLVMMetadataRef PointeeTy, - uint64_t SizeInBits, uint32_t AlignInBits, unsigned AddressSpace, + LLVMDIBuilderRef Builder, LLVMMetadataRef PointeeTy, uint64_t SizeInBits, + uint32_t AlignInBits, unsigned AddressSpace, LLVMDWARFMemorySpace MS, const char *Name, size_t NameLen) { return wrap(unwrap(Builder)->createPointerType( unwrapDI(PointeeTy), SizeInBits, AlignInBits, AddressSpace, - {Name, NameLen})); + map_to_llvmMSPACE(MS), {Name, NameLen})); } LLVMMetadataRef LLVMDIBuilderCreateStructType( @@ -1571,11 +1586,13 @@ LLVMDIBuilderCreateQualifiedType(LLVMDIBuilderRef Builder, unsigned Tag, unwrapDI(Type))); } -LLVMMetadataRef -LLVMDIBuilderCreateReferenceType(LLVMDIBuilderRef Builder, unsigned Tag, - LLVMMetadataRef Type) { - return wrap(unwrap(Builder)->createReferenceType(Tag, - unwrapDI(Type))); +LLVMMetadataRef LLVMDIBuilderCreateReferenceType(LLVMDIBuilderRef Builder, + unsigned Tag, + LLVMMetadataRef Type, + unsigned AddressSpace, + LLVMDWARFMemorySpace MS) { + return wrap(unwrap(Builder)->createReferenceType( + Tag, unwrapDI(Type), 0, 0, AddressSpace, map_to_llvmMSPACE(MS))); } LLVMMetadataRef @@ -1702,12 +1719,13 @@ LLVMMetadataRef LLVMDIBuilderCreateGlobalVariableExpression( LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, const char *Linkage, size_t LinkLen, LLVMMetadataRef File, unsigned LineNo, LLVMMetadataRef Ty, LLVMBool LocalToUnit, - LLVMMetadataRef Expr, LLVMMetadataRef Decl, uint32_t AlignInBits) { + LLVMMetadataRef Expr, LLVMMetadataRef Decl, LLVMDWARFMemorySpace MS, + uint32_t AlignInBits) { return wrap(unwrap(Builder)->createGlobalVariableExpression( unwrapDI(Scope), {Name, NameLen}, {Linkage, LinkLen}, - unwrapDI(File), LineNo, unwrapDI(Ty), LocalToUnit, - true, unwrap(Expr), unwrapDI(Decl), - nullptr, AlignInBits)); + unwrapDI(File), LineNo, unwrapDI(Ty), LocalToUnit, true, + unwrap(Expr), unwrapDI(Decl), nullptr, + map_to_llvmMSPACE(MS), AlignInBits)); } LLVMMetadataRef LLVMDIGlobalVariableExpressionGetVariable(LLVMMetadataRef GVE) { @@ -1752,11 +1770,11 @@ LLVMMetadataRef LLVMDIBuilderCreateTempGlobalVariableFwdDecl( LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, const char *Linkage, size_t LnkLen, LLVMMetadataRef File, unsigned LineNo, LLVMMetadataRef Ty, LLVMBool LocalToUnit, - LLVMMetadataRef Decl, uint32_t AlignInBits) { + LLVMMetadataRef Decl, LLVMDWARFMemorySpace MS, uint32_t AlignInBits) { return wrap(unwrap(Builder)->createTempGlobalVariableFwdDecl( unwrapDI(Scope), {Name, NameLen}, {Linkage, LnkLen}, unwrapDI(File), LineNo, unwrapDI(Ty), LocalToUnit, - unwrapDI(Decl), nullptr, AlignInBits)); + unwrapDI(Decl), nullptr, map_to_llvmMSPACE(MS), AlignInBits)); } LLVMDbgRecordRef LLVMDIBuilderInsertDeclareRecordBefore( @@ -1831,11 +1849,12 @@ LLVMDbgRecordRef LLVMDIBuilderInsertDbgValueRecordAtEnd( LLVMMetadataRef LLVMDIBuilderCreateAutoVariable( LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned LineNo, LLVMMetadataRef Ty, - LLVMBool AlwaysPreserve, LLVMDIFlags Flags, uint32_t AlignInBits) { + LLVMBool AlwaysPreserve, LLVMDIFlags Flags, LLVMDWARFMemorySpace MS, + uint32_t AlignInBits) { return wrap(unwrap(Builder)->createAutoVariable( - unwrap(Scope), {Name, NameLen}, unwrap(File), - LineNo, unwrap(Ty), AlwaysPreserve, - map_from_llvmDIFlags(Flags), AlignInBits)); + unwrap(Scope), {Name, NameLen}, unwrap(File), LineNo, + unwrap(Ty), AlwaysPreserve, map_from_llvmDIFlags(Flags), + map_to_llvmMSPACE(MS), AlignInBits)); } LLVMMetadataRef LLVMDIBuilderCreateParameterVariable( diff --git a/llvm/lib/IR/DebugInfoMetadata.cpp b/llvm/lib/IR/DebugInfoMetadata.cpp index e30df88e6b56b..5ac476641ade4 100644 --- a/llvm/lib/IR/DebugInfoMetadata.cpp +++ b/llvm/lib/IR/DebugInfoMetadata.cpp @@ -992,19 +992,19 @@ DIDerivedType *DIDerivedType::getImpl( LLVMContext &Context, unsigned Tag, MDString *Name, Metadata *File, unsigned Line, Metadata *Scope, Metadata *BaseType, Metadata *SizeInBits, uint32_t AlignInBits, Metadata *OffsetInBits, - std::optional DWARFAddressSpace, + std::optional DWARFAddressSpace, dwarf::MemorySpace MS, std::optional PtrAuthData, DIFlags Flags, Metadata *ExtraData, Metadata *Annotations, StorageType Storage, bool ShouldCreate) { assert(isCanonical(Name) && "Expected canonical MDString"); DEFINE_GETIMPL_LOOKUP(DIDerivedType, (Tag, Name, File, Line, Scope, BaseType, SizeInBits, - AlignInBits, OffsetInBits, DWARFAddressSpace, + AlignInBits, OffsetInBits, DWARFAddressSpace, MS, PtrAuthData, Flags, ExtraData, Annotations)); Metadata *Ops[] = {File, Scope, Name, SizeInBits, OffsetInBits, BaseType, ExtraData, Annotations}; DEFINE_GETIMPL_STORE( DIDerivedType, - (Tag, Line, AlignInBits, DWARFAddressSpace, PtrAuthData, Flags), Ops); + (Tag, Line, AlignInBits, DWARFAddressSpace, MS, PtrAuthData, Flags), Ops); } std::optional @@ -1538,15 +1538,16 @@ DIGlobalVariable::getImpl(LLVMContext &Context, Metadata *Scope, MDString *Name, MDString *LinkageName, Metadata *File, unsigned Line, Metadata *Type, bool IsLocalToUnit, bool IsDefinition, Metadata *StaticDataMemberDeclaration, - Metadata *TemplateParams, uint32_t AlignInBits, - Metadata *Annotations, StorageType Storage, - bool ShouldCreate) { + Metadata *TemplateParams, dwarf::MemorySpace MS, + uint32_t AlignInBits, Metadata *Annotations, + StorageType Storage, bool ShouldCreate) { assert(isCanonical(Name) && "Expected canonical MDString"); assert(isCanonical(LinkageName) && "Expected canonical MDString"); - DEFINE_GETIMPL_LOOKUP( - DIGlobalVariable, - (Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, IsDefinition, - StaticDataMemberDeclaration, TemplateParams, AlignInBits, Annotations)); + DEFINE_GETIMPL_LOOKUP(DIGlobalVariable, + (Scope, Name, LinkageName, File, Line, Type, + IsLocalToUnit, IsDefinition, + StaticDataMemberDeclaration, TemplateParams, MS, + AlignInBits, Annotations)); Metadata *Ops[] = {Scope, Name, File, @@ -1557,32 +1558,36 @@ DIGlobalVariable::getImpl(LLVMContext &Context, Metadata *Scope, MDString *Name, TemplateParams, Annotations}; DEFINE_GETIMPL_STORE(DIGlobalVariable, - (Line, IsLocalToUnit, IsDefinition, AlignInBits), Ops); + (Line, IsLocalToUnit, IsDefinition, MS, AlignInBits), + Ops); } DILocalVariable * DILocalVariable::getImpl(LLVMContext &Context, Metadata *Scope, MDString *Name, Metadata *File, unsigned Line, Metadata *Type, - unsigned Arg, DIFlags Flags, uint32_t AlignInBits, - Metadata *Annotations, StorageType Storage, - bool ShouldCreate) { + unsigned Arg, DIFlags Flags, dwarf::MemorySpace MS, + uint32_t AlignInBits, Metadata *Annotations, + StorageType Storage, bool ShouldCreate) { // 64K ought to be enough for any frontend. assert(Arg <= UINT16_MAX && "Expected argument number to fit in 16-bits"); assert(Scope && "Expected scope"); assert(isCanonical(Name) && "Expected canonical MDString"); DEFINE_GETIMPL_LOOKUP(DILocalVariable, (Scope, Name, File, Line, Type, Arg, - Flags, AlignInBits, Annotations)); + Flags, MS, AlignInBits, Annotations)); Metadata *Ops[] = {Scope, Name, File, Type, Annotations}; - DEFINE_GETIMPL_STORE(DILocalVariable, (Line, Arg, Flags, AlignInBits), Ops); + DEFINE_GETIMPL_STORE(DILocalVariable, (Line, Arg, Flags, MS, AlignInBits), + Ops); } DIVariable::DIVariable(LLVMContext &C, unsigned ID, StorageType Storage, signed Line, ArrayRef Ops, - uint32_t AlignInBits) - : DINode(C, ID, Storage, dwarf::DW_TAG_variable, Ops), Line(Line) { + dwarf::MemorySpace MS, uint32_t AlignInBits) + : DINode(C, ID, Storage, dwarf::DW_TAG_variable, Ops), Line(Line), + MemorySpace(MS) { SubclassData32 = AlignInBits; } + std::optional DIVariable::getSizeInBits() const { // This is used by the Verifier so be mindful of broken types. const Metadata *RawType = getRawType(); @@ -1631,7 +1636,41 @@ DILabel *DILabel::getImpl(LLVMContext &Context, Metadata *Scope, MDString *Name, } DIExpression *DIExpression::getImpl(LLVMContext &Context, - ArrayRef Elements, + std::nullopt_t Elements, + StorageType Storage, bool ShouldCreate) { + DEFINE_GETIMPL_LOOKUP(DIExpression, (OldElementsRef{})); + DEFINE_GETIMPL_STORE_NO_OPS(DIExpression, (OldElementsRef{})); +} +DIExpression *DIExpression::getImpl(LLVMContext &Context, + OldElementsRef Elements, + StorageType Storage, bool ShouldCreate) { + // If Elements is any expression containing DW_OP_LLVM_poisoned and an + // optional fragment then canonicalize, the other ops aren't doing anything. + SmallVector CanonicalizedPoisonOps; + for (unsigned Idx = 0; Idx < Elements.size();) { + ExprOperand Op(&Elements[Idx]); + + if (CanonicalizedPoisonOps.empty()) { + if (Op.getOp() == dwarf::DW_OP_LLVM_poisoned) + CanonicalizedPoisonOps.push_back(Op.getOp()); + } else if (Op.getOp() == dwarf::DW_OP_LLVM_fragment && + Idx + 2 < Elements.size()) { + CanonicalizedPoisonOps.push_back(Op.getOp()); + CanonicalizedPoisonOps.push_back(Op.getArg(0)); + CanonicalizedPoisonOps.push_back(Op.getArg(1)); + } + + // Have to handle invalid exprs. + Idx += Op.getSize(); + } + if (!CanonicalizedPoisonOps.empty()) + Elements = CanonicalizedPoisonOps; + + DEFINE_GETIMPL_LOOKUP(DIExpression, (Elements)); + DEFINE_GETIMPL_STORE_NO_OPS(DIExpression, (Elements)); +} +DIExpression *DIExpression::getImpl(LLVMContext &Context, bool /*ignored*/, + NewElementsRef Elements, StorageType Storage, bool ShouldCreate) { DEFINE_GETIMPL_LOOKUP(DIExpression, (Elements)); DEFINE_GETIMPL_STORE_NO_OPS(DIExpression, (Elements)); @@ -1690,12 +1729,207 @@ unsigned DIExpression::ExprOperand::getSize() const { } } -bool DIExpression::isValid() const { +namespace { +/// Extends validation to include Arguments and DataLayout when available, +/// falling back to assuming the expression is valid when these are not +/// supplied. +class DIExprVerifier : public DIExprConstVisitor { + std::optional Env; + std::string ErrorMsg; + + std::optional Fragment; + +public: + DIExprVerifier(LLVMContext &Context, ArrayRef Expr, + std::optional Env) + : DIExprConstVisitor(Context, Expr), Env(Env) {} + + bool error(const Twine &Msg) { + ErrorMsg = Msg.str(); + return false; + } + + StringRef getErrorMsg() const { + assert(!ErrorMsg.empty() && "Expected error string to be present here"); + return ErrorMsg; + } + + std::optional getSizeInBits(Type *T) { + TypeSize TS = TypeSize::getFixed(0); + if (Env) + TS = Env->DL.getTypeSizeInBits(T); + else + TS = T->getPrimitiveSizeInBits(); + if (TS.isScalable() || !TS.getFixedValue()) + return std::nullopt; + return TS.getFixedValue(); + } + + bool expectSameSize(Type *T, Type *U, const Twine &ErrorMsg) { + if (T == U) + return true; + std::optional TS = getSizeInBits(T); + std::optional US = getSizeInBits(U); + // If we cannot be certain the expression is invalid, just assume it is + // valid. For example, we may not have a DataLayout to determine pointer + // sizes, depending on the caller. + if (!TS || !US) + return true; + if (*TS != *US) + return error(ErrorMsg); + return true; + } + + using DIExprConstVisitor::visit; + + bool visit(DIOp::Referrer Op, Type *ResultType, ArrayRef) { + if (!Env) + return true; + if (Env->Arguments.empty()) + return error("DIOpReferrer requires an argument"); + const Value *V = Env->Arguments[0]; + return isa(V) || + expectSameSize( + ResultType, V->getType(), + "DIOpReferrer type must be same size in bits as argument"); + } + + bool visit(DIOp::Arg Op, Type *ResultType, ArrayRef) { + if (!Env) + return true; + if (Op.getIndex() >= Env->Arguments.size()) + return error("DIOpArg index out of range"); + const Value *V = Env->Arguments[Op.getIndex()]; + return isa(V) || + expectSameSize(ResultType, V->getType(), + "DIOpArg type must be same size in bits as argument"); + } + + bool visit(DIOp::Reinterpret Op, Type *ResultType, + ArrayRef Ins) { + return expectSameSize(ResultType, Ins[0].ResultType, + "DIOpReinterpret must not alter bitsize of child"); + } + + bool visit(DIOp::Composite Op, Type *ResultType, + ArrayRef Ins) { + assert(Op.getCount() == Ins.size()); + + std::optional ResultSizeInBits = getSizeInBits(Op.getResultType()); + if (!ResultSizeInBits) + return true; + + uint64_t TotalSizeInBits = 0u; + for (auto &In : Ins) { + std::optional InSizeInBits = getSizeInBits(In.ResultType); + if (!InSizeInBits) + return true; + TotalSizeInBits += *InSizeInBits; + } + + if (TotalSizeInBits != *ResultSizeInBits) + return error( + "DIOpComposite bitsize does not match sum of child bitsizes"); + + return true; + } + + bool visit(DIOp::Convert Op, Type *ResultType, ArrayRef Ins) { + // We only currently diagnose when DIOpConvert extends one integral + // type to a larger one, so only check when both types are integral. + if (!ResultType->isIntegerTy() || !Ins[0].ResultType->isIntegerTy()) + return true; + std::optional InSizeInBits = getSizeInBits(Ins[0].ResultType); + std::optional ResultSizeInBits = getSizeInBits(ResultType); + if (!InSizeInBits || !ResultSizeInBits) + return true; + if (*ResultSizeInBits > *InSizeInBits) + return error( + Op.getAsmName() + + " on integers requires result type to be no wider than input type"); + return true; + } + + template + bool visitExt(ExtOpT Op, Type *ResultType, ArrayRef Ins) { + std::optional InSizeInBits = getSizeInBits(Ins[0].ResultType); + std::optional ResultSizeInBits = getSizeInBits(ResultType); + if (!InSizeInBits || !ResultSizeInBits) + return true; + if (*ResultSizeInBits <= *InSizeInBits) + return error(Op.getAsmName() + + " requires result type to be wider than input type"); + return true; + } + + bool visit(DIOp::ZExt Op, Type *ResultType, ArrayRef Ins) { + return visitExt(Op, ResultType, Ins); + } + + bool visit(DIOp::SExt Op, Type *ResultType, ArrayRef Ins) { + return visitExt(Op, ResultType, Ins); + } + + bool visit(DIOp::Fragment Op, Type *ResultType, ArrayRef Ins) { + if (Env) { + std::optional VariableSizeInBits = + Env->Variable->getSizeInBits(); + if (VariableSizeInBits && + Op.getBitOffset() + Op.getBitSize() > *VariableSizeInBits) + return error("DIOpFragment must be contained within variable"); + } + Fragment = Op; + return true; + } + + bool visitResult(StackEntry Result) { + // FIXME(diexpression-poison): The IR type size in bits may not correspond + // to the DIType size as calculated by Clang, for example the debug type + // for "uchar3" calls it 32-bits whereas the IR type chosen for it <3 x i8> + // will naively be only 24-bits. Until we can reconcile this issue just + // avoid failing it in the verifier. + return true; + if (!Env) + return true; + std::optional ResultSizeInBits = getSizeInBits(Result.ResultType); + std::optional VariableSizeInBits; + if (Fragment) + VariableSizeInBits = Fragment->getBitSize(); + else + VariableSizeInBits = Env->Variable->getSizeInBits(); + if (!ResultSizeInBits || !VariableSizeInBits) + return true; + if (*ResultSizeInBits < *VariableSizeInBits) + return error("DIExpression must yield a location at least as wide as the " + "variable or fragment it describes"); + return true; + } +}; +} // namespace + +bool DIExpression::isValid( + std::optional Env, + std::optional> ErrS) const { + if (auto NewElementsRef = getNewElementsRef()) { + if (NewElementsRef->empty()) { + if (ErrS) + *ErrS << "DIOp-based DIExpression cannot be empty\n"; + return false; + } + DIExprVerifier Verifier{getContext(), *NewElementsRef, Env}; + bool Result = Verifier.visitInOrder(); + if (!Result && ErrS) + *ErrS << Verifier.getErrorMsg() << '\n'; + return Result; + } for (auto I = expr_op_begin(), E = expr_op_end(); I != E; ++I) { // Check that there's space for the operand. if (I->get() + I->getSize() > E->get()) return false; + if (I->getOp() == dwarf::DW_OP_LLVM_poisoned) + return true; + uint64_t Op = I->getOp(); if ((Op >= dwarf::DW_OP_reg0 && Op <= dwarf::DW_OP_reg31) || (Op >= dwarf::DW_OP_breg0 && Op <= dwarf::DW_OP_breg31)) @@ -1746,6 +1980,7 @@ bool DIExpression::isValid() const { case dwarf::DW_OP_LLVM_tag_offset: case dwarf::DW_OP_LLVM_extract_bits_sext: case dwarf::DW_OP_LLVM_extract_bits_zext: + case dwarf::DW_OP_LLVM_poisoned: case dwarf::DW_OP_constu: case dwarf::DW_OP_plus_uconst: case dwarf::DW_OP_plus: @@ -1831,6 +2066,11 @@ bool DIExpression::isSingleLocationExpression() const { if (!isValid()) return false; + // It is simpler for these cases to always be considered variadic, as + // there are fewer paths to handle. + if (holdsNewElements() || isPoisoned()) + return false; + if (getNumElements() == 0) return true; @@ -1876,6 +2116,9 @@ DIExpression::convertToUndefExpression(const DIExpression *Expr) { const DIExpression * DIExpression::convertToVariadicExpression(const DIExpression *Expr) { + if (Expr->holdsNewElements()) + return Expr; + if (any_of(Expr->expr_ops(), [](auto ExprOp) { return ExprOp.getOp() == dwarf::DW_OP_LLVM_arg; })) @@ -1892,6 +2135,9 @@ DIExpression::convertToNonVariadicExpression(const DIExpression *Expr) { if (!Expr) return std::nullopt; + if (Expr->holdsNewElements()) + return std::nullopt; + if (auto Elts = Expr->getSingleLocationExpressionElements()) return DIExpression::get(Expr->getContext(), *Elts); @@ -1932,6 +2178,11 @@ bool DIExpression::isEqualExpression(const DIExpression *FirstExpr, bool FirstIndirect, const DIExpression *SecondExpr, bool SecondIndirect) { + if (FirstExpr->holdsNewElements() != SecondExpr->holdsNewElements()) + return false; + if (FirstExpr->holdsNewElements()) + return FirstIndirect == SecondIndirect && FirstExpr == SecondExpr; + SmallVector FirstOps; DIExpression::canonicalizeExpressionOps(FirstOps, FirstExpr, FirstIndirect); SmallVector SecondOps; @@ -1950,6 +2201,14 @@ DIExpression::getFragmentInfo(expr_op_iterator Start, expr_op_iterator End) { return std::nullopt; } +std::optional +DIExpression::getFragmentInfo(NewElementsRef E) { + for (auto Op : E) + if (auto *Fragment = std::get_if(&Op)) + return {{Fragment->getBitSize(), Fragment->getBitOffset()}}; + return std::nullopt; +} + std::optional DIExpression::getActiveBits(DIVariable *Var) { std::optional InitialActiveBits = Var->getSizeInBits(); std::optional ActiveBits = InitialActiveBits; @@ -2075,6 +2334,8 @@ bool DIExpression::hasAllLocationOps(unsigned N) const { for (auto ExprOp : expr_ops()) if (ExprOp.getOp() == dwarf::DW_OP_LLVM_arg) SeenOps.insert(ExprOp.getArg(0)); + else if (ExprOp.getOp() == dwarf::DW_OP_LLVM_poisoned) + return true; for (uint64_t Idx = 0; Idx < N; ++Idx) if (!SeenOps.contains(Idx)) return false; @@ -2127,6 +2388,10 @@ DIExpression *DIExpression::appendOpsToArg(const DIExpression *Expr, unsigned ArgNo, bool StackValue) { assert(Expr && "Can't add ops to this expression"); + // FIXME: Handle newops here? + if (Expr->isPoisoned()) + return Expr->getPoisoned(); + // Handle non-variadic intrinsics by prepending the opcodes. if (!any_of(Expr->expr_ops(), [](auto Op) { return Op.getOp() == dwarf::DW_OP_LLVM_arg; })) { @@ -2157,6 +2422,70 @@ DIExpression *DIExpression::appendOpsToArg(const DIExpression *Expr, return DIExpression::get(Expr->getContext(), NewOps); } +DIExpression *DIExpression::appendNewOpsToArg(const DIExpression *Expr, + ArrayRef Ops, + unsigned ArgNo, + Type *NewArgType) { + assert(Expr && "Can't add ops to this expression"); + + DIExprBuilder Builder(Expr->getContext()); + auto ExprOps = Expr->getNewElementsRef(); + for (auto Op : *ExprOps) { + DIOp::Arg *AsArg = std::get_if(&Op); + if (AsArg && AsArg->getIndex() == ArgNo) { + Builder.append( + AsArg->getIndex(), NewArgType ? NewArgType : AsArg->getResultType()); + Builder.insert(Builder.end(), Ops.begin(), Ops.end()); + } else { + Builder.append(Op); + } + } + + return Builder.intoExpression(); +} + +const DIExpression *DIExpression::spillArgs(const DIExpression *Expr, + SmallBitVector SpilledOpIndexes, + unsigned SpillAddrSpace) { + if (auto ExprOps = Expr->getNewElementsRef()) { + DIExprBuilder Builder(Expr->getContext()); + auto *AllocaPtrTy = PointerType::get(Expr->getContext(), SpillAddrSpace); + for (auto Op : *ExprOps) { + DIOp::Arg *AsArg = std::get_if(&Op); + if (AsArg && SpilledOpIndexes.test(AsArg->getIndex())) { + Builder.append(AsArg->getIndex(), AllocaPtrTy); + Builder.append(AsArg->getResultType()); + } else { + Builder.append(Op); + } + } + return Builder.intoExpression(); + } + + std::array Ops{{dwarf::DW_OP_deref}}; + for (unsigned OpIdx : SpilledOpIndexes.set_bits()) + Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx); + return Expr; +} + +const DIExpression * +DIExpression::foldIntrinsicIndirection(const DIExpression *Expr, + bool IsIndirect) { + if (!IsIndirect || Expr->holdsNewElements()) + return Expr; + return DIExpression::append(Expr, dwarf::DW_OP_deref); +} + +const DIExpression *DIExpression::convertForInstrRef(const DIExpression *Expr, + bool IsIndirect) { + // Immediately fold any indirectness from the LLVM-IR intrinsic into the + // expression: + Expr = DIExpression::foldIntrinsicIndirection(Expr, IsIndirect); + // If this is not already a variadic expression, it must be modified to become + // one. + return DIExpression::convertToVariadicExpression(Expr); +} + DIExpression *DIExpression::replaceArg(const DIExpression *Expr, uint64_t OldArg, uint64_t NewArg) { assert(Expr && "Can't replace args in this expression"); @@ -2216,6 +2545,9 @@ DIExpression *DIExpression::append(const DIExpression *Expr, ArrayRef Ops) { assert(Expr && !Ops.empty() && "Can't append ops to this expression"); + if (Expr->isPoisoned()) + return Expr->getPoisoned(); + // Copy Expr's current op list. SmallVector NewOps; for (auto Op : Expr->expr_ops()) { @@ -2270,8 +2602,92 @@ DIExpression *DIExpression::appendToStack(const DIExpression *Expr, return DIExpression::append(Expr, NewOps); } +template static bool isDIOpVariantOneOf(DIOp::Variant Op) { + return (std::holds_alternative(Op) || ...); +} + +/// Skip past *It and any inputs that it consumes. +template +static void skipNewDIExpressionInputs(RIter &It, RIter Last) { + if (It == Last) + return; + + unsigned NumInputs = DIOp::getNumInputs(*It++); + for (unsigned I = 0; I < NumInputs; ++I) + skipNewDIExpressionInputs(It, Last); +} + +/// Check whether the expression described by [It, Last) can be safely +/// fragmented. For example, we have to reject an expression that produces an +/// implicit location description using DIOpAdd since we can't handle carry over +/// between fragments. This is analogous to what createFragmentExpression() is +/// doing below. +/// +/// RIter is a reverse iterator over a DIOp-based DIExpression, so the +/// operations that produce the stack inputs follow the operations that consume +/// them. +template +static bool canFragmentNewDIExpression(RIter &It, RIter Last) { + if (It == Last) + return false; + + DIOp::Variant Op = *It++; + + // FIXME: The Deref could technically be a problem if it's input is an AddrOf. + if (isDIOpVariantOneOf(Op)) + return true; + + if (isDIOpVariantOneOf(Op)) + return false; + + if (isDIOpVariantOneOf(Op)) { + // Skip the offset expression and drill into the base. + skipNewDIExpressionInputs(It, Last); + return canFragmentNewDIExpression(It, Last); + } + + if (isDIOpVariantOneOf(Op)) + return canFragmentNewDIExpression(It, Last); + + // FIXME: Missing DIOpComposite, DIOpExtend, DIOpSelect. + return false; +} + +static std::optional +createNewFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, + unsigned SizeInBits) { + auto NewElems = Expr->getNewElementsRef(); + assert(NewElems && "expected DIOp expression"); + + auto Iter = NewElems->rbegin(), End = NewElems->rend(); + if (!canFragmentNewDIExpression(Iter, End)) + return std::nullopt; + + DIExprBuilder ExprBuilder(Expr->getContext()); + for (DIOp::Variant Op : *NewElems) { + if (auto *Frag = std::get_if(&Op)) { + assert((OffsetInBits + SizeInBits <= Frag->getBitSize()) && + "new fragment outside of original fragment"); + OffsetInBits += Frag->getBitOffset(); + } else { + ExprBuilder.append(Op); + } + } + + ExprBuilder.append(OffsetInBits, SizeInBits); + return ExprBuilder.intoExpression(); +} + std::optional DIExpression::createFragmentExpression( const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits) { + + if (Expr->holdsNewElements()) + return createNewFragmentExpression(Expr, OffsetInBits, SizeInBits); + SmallVector Ops; // Track whether it's safe to split the value at the top of the DWARF stack, // assuming that it'll be used as an implicit location value. @@ -2480,6 +2896,106 @@ uint64_t DIExpression::getNumLocationOperands() const { return Result; } +uint64_t DIExpression::getNewNumLocationOperands() const { + uint64_t Result = 0; + auto Ops = getNewElementsRef(); + for (DIOp::Variant Op : *Ops) + if (auto *Arg = std::get_if(&Op)) + Result = std::max(Result, static_cast(Arg->getIndex() + 1)); + return Result; +} + +/// Returns true if the expression holds NewElements or contains the +/// DW_OP_LLVM_poisoned operation. +/// +/// \warning This is intended for use in "old paths" where a new expression is +/// equivalent to a poisoned expression. These paths still need to create a +/// poison expression if this returns true, however; the underlying expression +/// may hold NewElements otherwise. +bool DIExpression::isPoisoned() const { + return any_of(expr_ops(), [](auto Op) { + return Op.getOp() == dwarf::DW_OP_LLVM_poisoned; + }); +} + +namespace { +/// Visitor specialization to find the divergent address spaces a DIOp-based +/// DIExpression produces, if any. See the header comment on +/// DIExpression::getNewDivergentAddrSpace() for more information. +class DIOpDivergentAddrSpaceFinder + : public DIExprConstVisitor { + + // Stack of dwarf stack entries with divergent address spaces. If a stack + // entry doesn't have a divergent address space, this contains std::nullopt + // for that stack element. Kept in sync with DIExprConstVisitor::Stack. + SmallVector, 8> AddrSpaceStack; + Type *ResultTy = nullptr; + + DIOpDivergentAddrSpaceFinder(LLVMContext &Ctx, ArrayRef Ops) + : DIExprConstVisitor(Ctx, Ops) {} + +public: + template + bool visit(DIOpTy Op, Type *Ty, ArrayRef Inputs) { + assert(Stack.size() == AddrSpaceStack.size() && + "stacks should never get out of sync!"); + + if (isDIOpVariantOneOf(Op)) { + // Nothing to do, Reinterpret operations don't change the divergent + // address space on the top of the stack. + } else if (isDIOpVariantOneOf(Op)) { + // If this Convert is an address space conversion, push a divergent + // address space unless we're already converting from a divergent address + // space or the conversion is a no-op. + Type *FromTy = Inputs[0].ResultType; + assert(Ty && FromTy && "failed to get operation types?"); + if (FromTy->isPointerTy() && Ty->isPointerTy()) { + if (AddrSpaceStack.back() == std::nullopt && FromTy != Ty) + AddrSpaceStack.back() = FromTy->getPointerAddressSpace(); + } else + AddrSpaceStack.back() = std::nullopt; + } else { + // No other operation can produce or maintain a divergent address space. + AddrSpaceStack.erase(AddrSpaceStack.end() - getNumInputs(Op), + AddrSpaceStack.end()); + if (Ty) + AddrSpaceStack.push_back(std::nullopt); + } + + return DIExprConstVisitor::visit(Op, Ty, Inputs); + } + + bool visitResult(StackEntry SE) { + ResultTy = SE.ResultType; + return true; + } + + static std::optional find(LLVMContext &C, + ArrayRef Ops) { + DIOpDivergentAddrSpaceFinder Finder{C, Ops}; + if (!Finder.visitInOrder()) + return std::nullopt; + assert(Finder.AddrSpaceStack.size() == 1 && + "expected one element on stack after expression!"); + if (!Finder.ResultTy || !Finder.ResultTy->isPointerTy()) + return std::nullopt; + // Only return a divergent address space when the expression produces a + // generic pointer. + unsigned DeclaredAddrSpace = Finder.ResultTy->getPointerAddressSpace(); + if (Finder.AddrSpaceStack.back() && DeclaredAddrSpace == 0) + return Finder.AddrSpaceStack.back(); + return std::nullopt; + } +}; +} // namespace + +std::optional DIExpression::getNewDivergentAddrSpace() const { + auto Elems = getNewElementsRef(); + if (!Elems || Elems->empty()) + return std::nullopt; + return DIOpDivergentAddrSpaceFinder::find(getContext(), *Elems); +} + std::optional DIExpression::isConstant() const { @@ -2521,6 +3037,117 @@ DIExpression *DIExpression::appendExt(const DIExpression *Expr, return appendToStack(Expr, getExtOps(FromSize, ToSize, Signed)); } +StringRef DIOp::getAsmName(const Variant &V) { + return std::visit(makeVisitor([](auto &&Op) { return Op.getAsmName(); }), V); +} + +unsigned DIOp::getBitcodeID(const Variant &V) { + return std::visit(makeVisitor([](auto &&Op) { return Op.getBitcodeID(); }), V); +} + +unsigned DIOp::getNumInputs(Variant V) { + // clang-format off + using R = unsigned; + return std::visit(makeVisitor( + [](DIOp::Arg) -> R { return 0; }, + [](DIOp::Constant) -> R { return 0; }, + [](DIOp::PushLane) -> R { return 0; }, + [](DIOp::Referrer) -> R { return 0; }, + [](DIOp::TypeObject) -> R { return 0; }, + [](DIOp::AddrOf) -> R { return 1; }, + [](DIOp::Convert) -> R { return 1; }, + [](DIOp::ZExt) -> R { return 1; }, + [](DIOp::SExt) -> R { return 1; }, + [](DIOp::Deref) -> R { return 1; }, + [](DIOp::Extend) -> R { return 1; }, + [](DIOp::Read) -> R { return 1; }, + [](DIOp::Reinterpret) -> R { return 1; }, + [](DIOp::Add) -> R { return 2; }, + [](DIOp::BitOffset) -> R { return 2; }, + [](DIOp::ByteOffset) -> R { return 2; }, + [](DIOp::Div) -> R { return 2; }, + [](DIOp::Mul) -> R { return 2; }, + [](DIOp::Shl) -> R { return 2; }, + [](DIOp::LShr) -> R { return 2; }, + [](DIOp::AShr) -> R { return 2; }, + [](DIOp::And) -> R { return 2; }, + [](DIOp::Or) -> R { return 2; }, + [](DIOp::Xor) -> R { return 2; }, + [](DIOp::Mod) -> R { return 2; }, + [](DIOp::Sub) -> R { return 2; }, + [](DIOp::Select) -> R { return 3; }, + [](DIOp::Composite C) -> R { return C.getCount(); }, + [](DIOp::Fragment) -> R { return 0; }), V); + // clang-format on +} + +namespace llvm { +namespace DIOp { +#define HANDLE_OP0(NAME) \ + hash_code hash_value(const NAME &O) { return llvm::hash_value(0); } +#define HANDLE_OP1(NAME, TYPE1, NAME1) \ + hash_code hash_value(const NAME &O) { \ + return llvm::hash_value(O.get##NAME1()); \ + } +#define HANDLE_OP2(NAME, TYPE1, NAME1, TYPE2, NAME2) \ + hash_code hash_value(const NAME &O) { \ + return hash_combine(O.get##NAME1(), O.get##NAME2()); \ + } +#include "llvm/IR/DIExprOps.def" +} // namespace DIOp +} // namespace llvm + +DIExprBuilder::DIExprBuilder(LLVMContext &C) : C(C) {} +DIExprBuilder::DIExprBuilder(LLVMContext &C, + std::initializer_list IL) + : C(C), Elements(IL) {} +DIExprBuilder::DIExprBuilder(LLVMContext &C, ArrayRef V) + : C(C), Elements(V) {} +DIExprBuilder::DIExprBuilder(const DIExpression &E) + : C(E.getContext()), Elements(*E.getNewElementsRef()) {} + +DIExprBuilder &DIExprBuilder::append(DIOp::Variant O) { + Elements.push_back(O); + return *this; +} + +DIExprBuilder::Iterator DIExprBuilder::insert(Iterator I, DIOp::Variant O) { + return Elements.insert(I.Op, O); +} + +DIExprBuilder::Iterator DIExprBuilder::erase(Iterator I) { + return Elements.erase(I.Op); +} + +DIExprBuilder::Iterator DIExprBuilder::erase(Iterator From, Iterator To) { + return Elements.erase(From.Op, To.Op); +} + +DIExpression *DIExprBuilder::intoExpression() { +#ifndef NDEBUG + assert(!StateIsUnspecified); + StateIsUnspecified = true; +#endif + return DIExpression::get(C, false, std::move(Elements)); +} + +DIExprBuilder &DIExprBuilder::removeReferrerIndirection(Type *PointeeType) { + for (auto &&I = begin(); I != end(); ++I) { + if (auto *ReferrerOp = std::get_if(&*I)) { + auto *ResultType = ReferrerOp->getResultType(); + assert(ResultType->isPointerTy() && + "Expected pointer type for translated alloca"); + ReferrerOp->setResultType(PointeeType); + ++I; + if (I != end() && std::holds_alternative(*I)) + I = erase(I) - 1; + else + I = insert(I, ResultType->getPointerAddressSpace()); + } + } + return *this; +} + DIGlobalVariableExpression * DIGlobalVariableExpression::getImpl(LLVMContext &Context, Metadata *Variable, Metadata *Expression, StorageType Storage, diff --git a/llvm/lib/IR/DebugProgramInstruction.cpp b/llvm/lib/IR/DebugProgramInstruction.cpp index d9357bba75510..3fc3d28ba34fd 100644 --- a/llvm/lib/IR/DebugProgramInstruction.cpp +++ b/llvm/lib/IR/DebugProgramInstruction.cpp @@ -340,10 +340,11 @@ void DbgVariableRecord::replaceVariableLocationOp(unsigned OpIdx, void DbgVariableRecord::addVariableLocationOps(ArrayRef NewValues, DIExpression *NewExpr) { - assert(NewExpr->hasAllLocationOps(getNumVariableLocationOps() + + assert(NewExpr->holdsNewElements() || + NewExpr->hasAllLocationOps(getNumVariableLocationOps() + NewValues.size()) && - "NewExpr for debug variable intrinsic does not reference every " - "location operand."); + "NewExpr for debug variable intrinsic does not reference every " + "location operand."); assert(!is_contained(NewValues, nullptr) && "New values must be non-null"); setExpression(NewExpr); SmallVector MDs; diff --git a/llvm/lib/IR/IntrinsicInst.cpp b/llvm/lib/IR/IntrinsicInst.cpp index 23a4d1b5c615e..ae9493631e81a 100644 --- a/llvm/lib/IR/IntrinsicInst.cpp +++ b/llvm/lib/IR/IntrinsicInst.cpp @@ -180,10 +180,11 @@ void DbgVariableIntrinsic::replaceVariableLocationOp(unsigned OpIdx, void DbgVariableIntrinsic::addVariableLocationOps(ArrayRef NewValues, DIExpression *NewExpr) { - assert(NewExpr->hasAllLocationOps(getNumVariableLocationOps() + + assert(NewExpr->holdsNewElements() || + NewExpr->hasAllLocationOps(getNumVariableLocationOps() + NewValues.size()) && - "NewExpr for debug variable intrinsic does not reference every " - "location operand."); + "NewExpr for debug variable intrinsic does not reference every " + "location operand."); assert(!is_contained(NewValues, nullptr) && "New values must be non-null"); setArgOperand(2, MetadataAsValue::get(getContext(), NewExpr)); SmallVector MDs; diff --git a/llvm/lib/IR/LLVMContextImpl.cpp b/llvm/lib/IR/LLVMContextImpl.cpp index 87037c3a45140..1f5e78732761d 100644 --- a/llvm/lib/IR/LLVMContextImpl.cpp +++ b/llvm/lib/IR/LLVMContextImpl.cpp @@ -69,6 +69,7 @@ LLVMContextImpl::~LLVMContextImpl() { #define HANDLE_MDNODE_LEAF_UNIQUABLE(CLASS) \ for (auto *I : CLASS##s) \ I->dropAllReferences(); +#define HANDLE_MDNODE_LEAF_UNIQUED(CLASS) HANDLE_MDNODE_LEAF_UNIQUABLE(CLASS) #include "llvm/IR/Metadata.def" // Also drop references that come from the Value bridges. @@ -93,6 +94,7 @@ LLVMContextImpl::~LLVMContextImpl() { #define HANDLE_MDNODE_LEAF_UNIQUABLE(CLASS) \ for (CLASS * I : CLASS##s) \ delete I; +#define HANDLE_MDNODE_LEAF_UNIQUED(CLASS) HANDLE_MDNODE_LEAF_UNIQUABLE(CLASS) #include "llvm/IR/Metadata.def" // Free the constants. diff --git a/llvm/lib/IR/LLVMContextImpl.h b/llvm/lib/IR/LLVMContextImpl.h index e03f993297e54..57050b4ca68b4 100644 --- a/llvm/lib/IR/LLVMContextImpl.h +++ b/llvm/lib/IR/LLVMContextImpl.h @@ -600,6 +600,7 @@ template <> struct MDNodeKeyImpl { Metadata *OffsetInBits; uint32_t AlignInBits; std::optional DWARFAddressSpace; + dwarf::MemorySpace DWARFMemorySpace; std::optional PtrAuthData; unsigned Flags; Metadata *ExtraData; @@ -609,19 +610,19 @@ template <> struct MDNodeKeyImpl { Metadata *Scope, Metadata *BaseType, Metadata *SizeInBits, uint32_t AlignInBits, Metadata *OffsetInBits, std::optional DWARFAddressSpace, - std::optional PtrAuthData, + dwarf::MemorySpace DWARFMemorySpace, std::optional PtrAuthData, unsigned Flags, Metadata *ExtraData, Metadata *Annotations) : Tag(Tag), Name(Name), File(File), Line(Line), Scope(Scope), BaseType(BaseType), SizeInBits(SizeInBits), OffsetInBits(OffsetInBits), AlignInBits(AlignInBits), DWARFAddressSpace(DWARFAddressSpace), - PtrAuthData(PtrAuthData), Flags(Flags), ExtraData(ExtraData), + DWARFMemorySpace(DWARFMemorySpace), PtrAuthData(PtrAuthData), Flags(Flags), ExtraData(ExtraData), Annotations(Annotations) {} MDNodeKeyImpl(const DIDerivedType *N) : Tag(N->getTag()), Name(N->getRawName()), File(N->getRawFile()), Line(N->getLine()), Scope(N->getRawScope()), BaseType(N->getRawBaseType()), SizeInBits(N->getRawSizeInBits()), OffsetInBits(N->getRawOffsetInBits()), AlignInBits(N->getAlignInBits()), - DWARFAddressSpace(N->getDWARFAddressSpace()), + DWARFAddressSpace(N->getDWARFAddressSpace()), DWARFMemorySpace(N->getDWARFMemorySpace()), PtrAuthData(N->getPtrAuthData()), Flags(N->getFlags()), ExtraData(N->getRawExtraData()), Annotations(N->getRawAnnotations()) {} @@ -633,8 +634,8 @@ template <> struct MDNodeKeyImpl { AlignInBits == RHS->getAlignInBits() && OffsetInBits == RHS->getRawOffsetInBits() && DWARFAddressSpace == RHS->getDWARFAddressSpace() && - PtrAuthData == RHS->getPtrAuthData() && Flags == RHS->getFlags() && - ExtraData == RHS->getRawExtraData() && + DWARFMemorySpace == RHS->getDWARFMemorySpace() && PtrAuthData == RHS->getPtrAuthData() && + Flags == RHS->getFlags() && ExtraData == RHS->getRawExtraData() && Annotations == RHS->getRawAnnotations(); } @@ -1221,6 +1222,7 @@ template <> struct MDNodeKeyImpl { bool IsDefinition; Metadata *StaticDataMemberDeclaration; Metadata *TemplateParams; + dwarf::MemorySpace MemorySpace; uint32_t AlignInBits; Metadata *Annotations; @@ -1228,13 +1230,14 @@ template <> struct MDNodeKeyImpl { Metadata *File, unsigned Line, Metadata *Type, bool IsLocalToUnit, bool IsDefinition, Metadata *StaticDataMemberDeclaration, Metadata *TemplateParams, - uint32_t AlignInBits, Metadata *Annotations) + dwarf::MemorySpace MS, uint32_t AlignInBits, + Metadata *Annotations) : Scope(Scope), Name(Name), LinkageName(LinkageName), File(File), Line(Line), Type(Type), IsLocalToUnit(IsLocalToUnit), IsDefinition(IsDefinition), StaticDataMemberDeclaration(StaticDataMemberDeclaration), - TemplateParams(TemplateParams), AlignInBits(AlignInBits), - Annotations(Annotations) {} + TemplateParams(TemplateParams), MemorySpace(MS), + AlignInBits(AlignInBits), Annotations(Annotations) {} MDNodeKeyImpl(const DIGlobalVariable *N) : Scope(N->getRawScope()), Name(N->getRawName()), LinkageName(N->getRawLinkageName()), File(N->getRawFile()), @@ -1242,7 +1245,8 @@ template <> struct MDNodeKeyImpl { IsLocalToUnit(N->isLocalToUnit()), IsDefinition(N->isDefinition()), StaticDataMemberDeclaration(N->getRawStaticDataMemberDeclaration()), TemplateParams(N->getRawTemplateParams()), - AlignInBits(N->getAlignInBits()), Annotations(N->getRawAnnotations()) {} + MemorySpace(N->getDWARFMemorySpace()), AlignInBits(N->getAlignInBits()), + Annotations(N->getRawAnnotations()) {} bool isKeyOf(const DIGlobalVariable *RHS) const { return Scope == RHS->getRawScope() && Name == RHS->getRawName() && @@ -1253,6 +1257,7 @@ template <> struct MDNodeKeyImpl { StaticDataMemberDeclaration == RHS->getRawStaticDataMemberDeclaration() && TemplateParams == RHS->getRawTemplateParams() && + MemorySpace == RHS->getDWARFMemorySpace() && AlignInBits == RHS->getAlignInBits() && Annotations == RHS->getRawAnnotations(); } @@ -1267,7 +1272,7 @@ template <> struct MDNodeKeyImpl { // TODO: make hashing work fine with such situations return hash_combine(Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, IsDefinition, /* AlignInBits, */ - StaticDataMemberDeclaration, Annotations); + StaticDataMemberDeclaration, MemorySpace, Annotations); } }; @@ -1279,25 +1284,30 @@ template <> struct MDNodeKeyImpl { Metadata *Type; unsigned Arg; unsigned Flags; + dwarf::MemorySpace MemorySpace; uint32_t AlignInBits; Metadata *Annotations; MDNodeKeyImpl(Metadata *Scope, MDString *Name, Metadata *File, unsigned Line, Metadata *Type, unsigned Arg, unsigned Flags, - uint32_t AlignInBits, Metadata *Annotations) + dwarf::MemorySpace MS, uint32_t AlignInBits, + Metadata *Annotations) : Scope(Scope), Name(Name), File(File), Line(Line), Type(Type), Arg(Arg), - Flags(Flags), AlignInBits(AlignInBits), Annotations(Annotations) {} + Flags(Flags), MemorySpace(MS), AlignInBits(AlignInBits), + Annotations(Annotations) {} MDNodeKeyImpl(const DILocalVariable *N) : Scope(N->getRawScope()), Name(N->getRawName()), File(N->getRawFile()), Line(N->getLine()), Type(N->getRawType()), Arg(N->getArg()), - Flags(N->getFlags()), AlignInBits(N->getAlignInBits()), - Annotations(N->getRawAnnotations()) {} + Flags(N->getFlags()), MemorySpace(N->getDWARFMemorySpace()), + AlignInBits(N->getAlignInBits()), Annotations(N->getRawAnnotations()) {} bool isKeyOf(const DILocalVariable *RHS) const { return Scope == RHS->getRawScope() && Name == RHS->getRawName() && File == RHS->getRawFile() && Line == RHS->getLine() && Type == RHS->getRawType() && Arg == RHS->getArg() && - Flags == RHS->getFlags() && AlignInBits == RHS->getAlignInBits() && + Flags == RHS->getFlags() && + MemorySpace == RHS->getDWARFMemorySpace() && + AlignInBits == RHS->getAlignInBits() && Annotations == RHS->getRawAnnotations(); } @@ -1309,7 +1319,8 @@ template <> struct MDNodeKeyImpl { // clang/test/CodeGen/debug-info-257-args.c is an example of this problem, // generated IR is random for each run and test fails with Align included. // TODO: make hashing work fine with such situations - return hash_combine(Scope, Name, File, Line, Type, Arg, Flags, Annotations); + return hash_combine(Scope, Name, File, Line, Type, Arg, Flags, MemorySpace, + Annotations); } }; @@ -1348,16 +1359,17 @@ template <> struct MDNodeKeyImpl { }; template <> struct MDNodeKeyImpl { - ArrayRef Elements; + DIExpression::ElementsRef Elements; + MDNodeKeyImpl(DIExpression::NewElementsRef Elements) : Elements(Elements) {} MDNodeKeyImpl(ArrayRef Elements) : Elements(Elements) {} - MDNodeKeyImpl(const DIExpression *N) : Elements(N->getElements()) {} + MDNodeKeyImpl(const DIExpression *N) : Elements(N->getElementsRef()) {} bool isKeyOf(const DIExpression *RHS) const { - return Elements == RHS->getElements(); + return Elements == RHS->getElementsRef(); } - unsigned getHashValue() const { return hash_combine_range(Elements); } + unsigned getHashValue() const { return hash_value(Elements); } }; template <> struct MDNodeKeyImpl { diff --git a/llvm/lib/IR/Metadata.cpp b/llvm/lib/IR/Metadata.cpp index 1add0c7930bc9..550dfe785b909 100644 --- a/llvm/lib/IR/Metadata.cpp +++ b/llvm/lib/IR/Metadata.cpp @@ -1964,3 +1964,15 @@ void GlobalVariable::getDebugInfo( for (MDNode *MD : MDs) GVs.push_back(cast(MD)); } + +void GlobalVariable::addDebugInfo(DIGlobalVariable *GV) { + addMetadata(LLVMContext::MD_dbg, *GV); +} + +void GlobalVariable::getDebugInfo( + SmallVectorImpl &GVs) const { + SmallVector MDs; + getMetadata(LLVMContext::MD_dbg, MDs); + for (MDNode *MD : MDs) + GVs.push_back(cast(MD)); +} diff --git a/llvm/lib/IR/Pass.cpp b/llvm/lib/IR/Pass.cpp index dec7c9a9ab18c..3afa3c72a32ea 100644 --- a/llvm/lib/IR/Pass.cpp +++ b/llvm/lib/IR/Pass.cpp @@ -310,6 +310,8 @@ const char *llvm::to_string(ThinOrFullLTOPhase Phase) { return "FullLTOPreLink"; case ThinOrFullLTOPhase::FullLTOPostLink: return "FullLTOPostLink"; + case llvm::ThinOrFullLTOPhase::CustomLTOPostLink: + return "CustomLTOPostLink"; } llvm_unreachable("invalid phase"); } diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp index 0e9535d24a4cc..8e60577bf8fb4 100644 --- a/llvm/lib/IR/Type.cpp +++ b/llvm/lib/IR/Type.cpp @@ -47,7 +47,8 @@ Type *Type::getPrimitiveType(LLVMContext &C, TypeID IDNumber) { case FP128TyID : return getFP128Ty(C); case PPC_FP128TyID : return getPPC_FP128Ty(C); case LabelTyID : return getLabelTy(C); - case MetadataTyID : return getMetadataTy(C); + case MetadataTyID: + return getMetadataTy(C); case X86_AMXTyID : return getX86_AMXTy(C); case TokenTyID : return getTokenTy(C); default: diff --git a/llvm/lib/IR/TypeFinder.cpp b/llvm/lib/IR/TypeFinder.cpp index 963f4b4806e1f..fdc501ec07be6 100644 --- a/llvm/lib/IR/TypeFinder.cpp +++ b/llvm/lib/IR/TypeFinder.cpp @@ -99,7 +99,11 @@ void TypeFinder::run(const Module &M, bool onlyNamed) { if (DVI->isDbgAssign()) { if (Value *Addr = DVI->getAddress()) incorporateValue(Addr); + if (auto *Expr = DVI->getRawAddressExpression()) + incorporateMDNode(Expr); } + if (auto *Expr = DVI->getRawExpression()) + incorporateMDNode(Expr); } } } @@ -187,6 +191,37 @@ void TypeFinder::incorporateMDNode(const MDNode *V) { if (!VisitedMetadata.insert(V).second) return; + auto incorporateDIOp = [this](DIOp::Variant Op) { + std::visit( + makeVisitor( +#define HANDLE_OP0(NAME) [](DIOp::NAME) {}, +#include "llvm/IR/DIExprOps.def" + [&](DIOp::Referrer R) { incorporateType(R.getResultType()); }, + [&](DIOp::Arg A) { incorporateType(A.getResultType()); }, + [&](DIOp::TypeObject T) { incorporateType(T.getResultType()); }, + [&](DIOp::Constant C) { incorporateValue(C.getLiteralValue()); }, + [&](DIOp::Convert C) { incorporateType(C.getResultType()); }, + [&](DIOp::ZExt C) { incorporateType(C.getResultType()); }, + [&](DIOp::SExt C) { incorporateType(C.getResultType()); }, + [&](DIOp::Reinterpret R) { incorporateType(R.getResultType()); }, + [&](DIOp::BitOffset B) { incorporateType(B.getResultType()); }, + [&](DIOp::ByteOffset B) { incorporateType(B.getResultType()); }, + [&](DIOp::Composite C) { incorporateType(C.getResultType()); }, + [&](DIOp::Extend) {}, [&](DIOp::AddrOf) {}, + [&](DIOp::Deref D) { incorporateType(D.getResultType()); }, + [&](DIOp::PushLane P) { incorporateType(P.getResultType()); }, + [&](DIOp::Fragment F) {}), + Op); + }; + + if (const auto *E = dyn_cast(V)) { + if (auto Elems = E->getNewElementsRef()) { + for (const auto &Op : *Elems) + incorporateDIOp(Op); + } + return; + } + // Look in operands for types. for (Metadata *Op : V->operands()) { if (!Op) diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index 7917712846990..6d23dad2e185b 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -911,6 +911,14 @@ void Verifier::visitGlobalVariable(const GlobalVariable &GV) { SmallVector MDs; GV.getMetadata(LLVMContext::MD_dbg, MDs); for (auto *MD : MDs) { + if (auto *GVE = dyn_cast(MD)) { + if (auto *E = dyn_cast_or_null(GVE->getRawExpression())) { + SmallVector Arguments{&GV}; + DIExpressionEnv Env{GVE->getVariable(), Arguments, DL}; + CheckDI(E->isValid(Env, dbgs()), + "invalid DIExpression in DIGlobalVariableExpression", &GV); + } + } if (auto *GVE = dyn_cast(MD)) visitDIGlobalVariableExpression(*GVE); else @@ -1359,6 +1367,14 @@ void Verifier::visitDIDerivedType(const DIDerivedType &N) { CheckDI(!Size || isa(Size) || isa(Size) || isa(Size), "SizeInBits must be a constant or DIVariable or DIExpression"); + + if (N.getDWARFMemorySpace() != dwarf::DW_MSPACE_LLVM_none) { + CheckDI(N.getTag() == dwarf::DW_TAG_pointer_type || + N.getTag() == dwarf::DW_TAG_reference_type || + N.getTag() == dwarf::DW_TAG_rvalue_reference_type, + "DWARF memory space only applies to pointer or reference types", + &N); + } } /// Detect mutually exclusive flags. @@ -5668,6 +5684,15 @@ void Verifier::visitInstruction(Instruction &I) { InstsInThisBlock.insert(&I); } +inline MDString *getMetadataValueAsString(MetadataAsValue *MDV) { + if (!MDV) + return nullptr; + auto *MD = dyn_cast(MDV->getMetadata()); + if (!MD || MD->getNumOperands() != 1) + return nullptr; + return dyn_cast(MD->getOperand(0)); +} + /// Allow intrinsics to be verified in different ways. void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) { Function *IF = Call.getCalledFunction(); @@ -6867,14 +6892,32 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) { &Call, PtrArg); // Last argument must be a MD string - auto *Op = cast(Call.getArgOperand(Call.arg_size() - 1)); - MDNode *MD = cast(Op->getMetadata()); - Check((MD->getNumOperands() == 1) && isa(MD->getOperand(0)), + auto *Op = + dyn_cast(Call.getArgOperand(Call.arg_size() - 1)); + Check(getMetadataValueAsString(Op) != nullptr, "cooperative atomic intrinsics require that the last argument is a " "metadata string", &Call, Op); break; } + case Intrinsic::amdgcn_global_load_b128: + case Intrinsic::amdgcn_global_store_b128: { + auto *Op = + dyn_cast(Call.getArgOperand(Call.arg_size() - 1)); + MDString *MDStr = getMetadataValueAsString(Op); + Check(MDStr != nullptr, + "global load/store intrinsics require that the last argument is a " + "metadata string", + &Call, Op); + + StringRef Scope = MDStr->getString(); + Check(Scope == "" || Scope == "agent" || Scope == "workgroup" || + Scope == "wavefront", + "'" + Scope + + "' is not a valid scope for global load/store intrinsics", + &Call, Op); + break; + } case Intrinsic::nvvm_setmaxnreg_inc_sync_aligned_u32: case Intrinsic::nvvm_setmaxnreg_dec_sync_aligned_u32: { Value *V = Call.getArgOperand(0); @@ -7056,6 +7099,13 @@ void Verifier::visit(DbgVariableRecord &DVR) { F); visitMDNode(*DVR.getExpression(), AreDebugLocsAllowed::No); + // This is redundant with the visitMDNode check above, but here we can include + // arguments for DIOp-based expression checking. + SmallVector Arguments{DVR.location_ops()}; + DIExpressionEnv ExprEnv{DVR.getVariable(), Arguments, DL}; + CheckDI(DVR.getExpression()->isValid(ExprEnv, dbgs()), + "invalid #dbg record expression", &DVR, DVR.getRawExpression()); + if (DVR.isDbgAssign()) { CheckDI(isa_and_nonnull(DVR.getRawAssignID()), "invalid #dbg_assign DIAssignID", &DVR, DVR.getRawAssignID(), BB, @@ -7409,6 +7459,9 @@ void Verifier::verifyFragmentExpression(const DIVariable &V, CheckDI(FragSize + FragOffset <= *VarSize, "fragment is larger than or outside of variable", Desc, &V); CheckDI(FragSize != *VarSize, "fragment covers entire variable", Desc, &V); + + auto MSpace = V.getDWARFMemorySpace(); + CheckDI(MSpace <= dwarf::DW_MSPACE_LLVM_hi_user, "invalid memory space", &V); } void Verifier::verifyFnArgs(const DbgVariableRecord &DVR) { diff --git a/llvm/lib/LTO/LTOBackend.cpp b/llvm/lib/LTO/LTOBackend.cpp index 93118becedbac..d9defe721cc18 100644 --- a/llvm/lib/LTO/LTOBackend.cpp +++ b/llvm/lib/LTO/LTOBackend.cpp @@ -42,6 +42,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/TargetParser/SubtargetFeature.h" #include "llvm/Transforms/IPO/WholeProgramDevirt.h" +#include "llvm/Transforms/Utils/Cloning.h" #include "llvm/Transforms/Utils/FunctionImportUtils.h" #include "llvm/Transforms/Utils/SplitModule.h" #include @@ -98,6 +99,10 @@ Error Config::addSaveTemps(std::string OutputFileName, bool UseInputModulePath, } } + if (SaveTempsArgs.contains("asm")) { + AsmFile = OutputFileName; + } + auto setHook = [&](std::string PathSuffix, ModuleHookFn &Hook) { // Keep track of the hook provided by the linker, which also needs to run. ModuleHookFn LinkerHook = Hook; @@ -396,7 +401,24 @@ bool lto::opt(const Config &Conf, TargetMachine *TM, unsigned Task, Module &Mod, return !Conf.PostOptModuleHook || Conf.PostOptModuleHook(Task, Mod); } -static void codegen(const Config &Conf, TargetMachine *TM, +struct CodegenConfig { + const Config &Conf; + CodeGenFileType CGFileType; + std::string DwoDir; + Config::ModuleHookFn PreCodeGenModuleHook; + std::function PreCodeGenPassesHook; + std::string SplitDwarfFile; + std::string SplitDwarfOutput; + CodegenConfig(const Config &Conf) : Conf(Conf) { + CGFileType = Conf.CGFileType; + DwoDir = Conf.DwoDir; + PreCodeGenModuleHook = Conf.PreCodeGenModuleHook; + PreCodeGenPassesHook = Conf.PreCodeGenPassesHook; + SplitDwarfFile = Conf.SplitDwarfFile; + SplitDwarfOutput = Conf.SplitDwarfOutput; + } +}; +static void codegen(const CodegenConfig &Conf, TargetMachine *TM, AddStreamFn AddStream, unsigned Task, Module &Mod, const ModuleSummaryIndex &CombinedIndex) { llvm::TimeTraceScope timeScope("codegen"); @@ -470,7 +492,7 @@ static void codegen(const Config &Conf, TargetMachine *TM, report_fatal_error(std::move(Err)); } -static void splitCodeGen(const Config &C, TargetMachine *TM, +static void splitCodeGen(const CodegenConfig &CodegenC, TargetMachine *TM, AddStreamFn AddStream, unsigned ParallelCodeGenParallelismLevel, Module &Mod, const ModuleSummaryIndex &CombinedIndex) { @@ -494,7 +516,7 @@ static void splitCodeGen(const Config &C, TargetMachine *TM, // Enqueue the task CodegenThreadPool.async( [&](const SmallString<0> &BC, unsigned ThreadId) { - LTOLLVMContext Ctx(C); + LTOLLVMContext Ctx(CodegenC.Conf); Expected> MOrErr = parseBitcodeFile(MemoryBufferRef(BC.str(), "ld-temp.o"), Ctx); if (!MOrErr) @@ -502,9 +524,9 @@ static void splitCodeGen(const Config &C, TargetMachine *TM, std::unique_ptr MPartInCtx = std::move(MOrErr.get()); std::unique_ptr TM = - createTargetMachine(C, T, *MPartInCtx); + createTargetMachine(CodegenC.Conf, T, *MPartInCtx); - codegen(C, TM.get(), AddStream, ThreadId, *MPartInCtx, + codegen(CodegenC, TM.get(), AddStream, ThreadId, *MPartInCtx, CombinedIndex); }, // Pass BC using std::move to ensure that it get moved rather than @@ -550,6 +572,34 @@ Error lto::finalizeOptimizationRemarks(LLVMRemarkFileHandle DiagOutputFile) { return Error::success(); } +static bool backendOpt( + const Config &C, std::unique_ptr &TM, Module &Mod, + ModuleSummaryIndex *ExportSummary = nullptr) { + if (C.CodeGenOnly) + return true; + return opt(C, TM.get(), 0, Mod, /*IsThinLTO=*/false, + /*ExportSummary=*/ExportSummary, /*ImportSummary=*/nullptr, + /*CmdArgs*/ std::vector()); +} + +static std::unique_ptr GenAsmFilename( + StringRef Basename, size_t Task, const Twine &ModuleName) { + int FD; + std::string AsmFilename = Basename.str(); + if (Task > 0) + AsmFilename += std::to_string(Task) + "."; + AsmFilename += "lto.s"; + + std::error_code EC; + EC = sys::fs::openFileForWrite(AsmFilename, FD, sys::fs::CD_CreateAlways); + if (EC) + report_fatal_error(Twine("Failed to create asm file ") + AsmFilename + + ": " + EC.message()); + + return std::make_unique( + std::make_unique(FD, true)); +} + Error lto::backend(const Config &C, AddStreamFn AddStream, unsigned ParallelCodeGenParallelismLevel, Module &Mod, ModuleSummaryIndex &CombinedIndex) { @@ -560,20 +610,43 @@ Error lto::backend(const Config &C, AddStreamFn AddStream, std::unique_ptr TM = createTargetMachine(C, *TOrErr, Mod); - LLVM_DEBUG(dbgs() << "Running regular LTO\n"); - if (!C.CodeGenOnly) { - if (!opt(C, TM.get(), 0, Mod, /*IsThinLTO=*/false, - /*ExportSummary=*/&CombinedIndex, /*ImportSummary=*/nullptr, - /*CmdArgs*/ std::vector())) - return Error::success(); + std::unique_ptr AsmMod; + if (C.AsmFile.size() && C.CGFileType != CodeGenFileType::AssemblyFile) { + AsmMod = CloneModule(Mod); } + LLVM_DEBUG(dbgs() << "Running regular LTO\n"); + CodegenConfig CodegenC(C); + if (!backendOpt(C, TM, Mod, &CombinedIndex)) { + return Error::success(); + } if (ParallelCodeGenParallelismLevel == 1) { - codegen(C, TM.get(), AddStream, 0, Mod, CombinedIndex); + codegen(CodegenC, TM.get(), AddStream, 0, Mod, CombinedIndex); } else { - splitCodeGen(C, TM.get(), AddStream, ParallelCodeGenParallelismLevel, Mod, - CombinedIndex); + splitCodeGen(CodegenC, TM.get(), AddStream, + ParallelCodeGenParallelismLevel, Mod, CombinedIndex); + } + + if (AsmMod) { + CodegenC.CGFileType = CodeGenFileType::AssemblyFile; + CodegenC.DwoDir.clear(); + CodegenC.SplitDwarfFile.clear(); + CodegenC.SplitDwarfOutput.clear(); + auto AddAsmFile = [&](size_t Task, const Twine &ModuleName) { + return GenAsmFilename(C.AsmFile, Task, ModuleName); + }; + + if (!backendOpt(C, TM, *AsmMod)) { + return Error::success(); + } + if (ParallelCodeGenParallelismLevel == 1) { + codegen(CodegenC, TM.get(), AddAsmFile, 0, *AsmMod, CombinedIndex); + } else { + splitCodeGen(CodegenC, TM.get(), AddAsmFile, + ParallelCodeGenParallelismLevel, *AsmMod, CombinedIndex); + } } + return Error::success(); } diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp index 885fa55b65d50..930683c447931 100644 --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -369,6 +369,21 @@ class MCAsmStreamer final : public MCStreamer { void emitCFINegateRAState(SMLoc Loc) override; void emitCFINegateRAStateWithPC(SMLoc Loc) override; void emitCFIReturnColumn(int64_t Register) override; + void emitCFILLVMRegisterPair(int64_t Register, int64_t R1, int64_t R1Size, + int64_t R2, int64_t R2Size, SMLoc Loc) override; + void emitCFILLVMVectorRegisters( + int64_t Register, + std::vector VRs, + SMLoc Loc) override; + void emitCFILLVMVectorOffset(int64_t Register, int64_t RegisterSize, + int64_t MaskRegister, int64_t MaskRegisterSize, + int64_t Offset, SMLoc Loc) override; + void emitCFILLVMVectorRegisterMask(int64_t Register, int64_t SpillRegister, + int64_t SpillRegisterLaneSizeInBits, + int64_t MaskRegister, + int64_t MaskRegisterSizeInBits, + SMLoc Loc) override; + void emitCFILabelDirective(SMLoc Loc, StringRef Name) override; void emitCFIValOffset(int64_t Register, int64_t Offset, SMLoc Loc) override; @@ -2101,6 +2116,67 @@ void MCAsmStreamer::emitCFIRegister(int64_t Register1, int64_t Register2, EmitEOL(); } +void MCAsmStreamer::emitCFILLVMRegisterPair(int64_t Register, int64_t R1, + int64_t R1Size, int64_t R2, + int64_t R2Size, SMLoc Loc) { + MCStreamer::emitCFILLVMRegisterPair(Register, R1, R1Size, R2, R2Size, Loc); + + OS << "\t.cfi_llvm_register_pair "; + EmitRegisterName(Register); + OS << ", "; + EmitRegisterName(R1); + OS << ", " << R1Size << ", "; + EmitRegisterName(R2); + OS << ", " << R2Size; + EmitEOL(); +} + +void MCAsmStreamer::emitCFILLVMVectorRegisters( + int64_t Register, std::vector VRs, + SMLoc Loc) { + MCStreamer::emitCFILLVMVectorRegisters(Register, VRs, Loc); + + OS << "\t.cfi_llvm_vector_registers "; + EmitRegisterName(Register); + for (auto [Reg, Lane, Size] : VRs) + OS << ", " << Reg << ", " << Lane << ", " << Size; + EmitEOL(); +} + +void MCAsmStreamer::emitCFILLVMVectorOffset(int64_t Register, + int64_t RegisterSize, + int64_t MaskRegister, + int64_t MaskRegisterSize, + int64_t Offset, SMLoc Loc) { + MCStreamer::emitCFILLVMVectorOffset(Register, RegisterSize, MaskRegister, + MaskRegisterSize, Offset, Loc); + + OS << "\t.cfi_llvm_vector_offset "; + EmitRegisterName(Register); + OS << ", " << RegisterSize << ", "; + EmitRegisterName(MaskRegister); + OS << ", " << MaskRegisterSize << ", " << Offset; + EmitEOL(); +} + +void MCAsmStreamer::emitCFILLVMVectorRegisterMask( + int64_t Register, int64_t SpillRegister, + int64_t SpillRegisterLaneSizeInBits, int64_t MaskRegister, + int64_t MaskRegisterSizeInBits, SMLoc Loc) { + MCStreamer::emitCFILLVMVectorRegisterMask( + Register, SpillRegister, SpillRegisterLaneSizeInBits, MaskRegister, + MaskRegisterSizeInBits, Loc); + + OS << "\t.cfi_llvm_vector_register_mask "; + EmitRegisterName(Register); + OS << ", "; + EmitRegisterName(SpillRegister); + OS << ", " << SpillRegisterLaneSizeInBits << ", "; + EmitRegisterName(MaskRegister); + OS << ", " << MaskRegisterSizeInBits; + EmitEOL(); +} + void MCAsmStreamer::emitCFIWindowSave(SMLoc Loc) { MCStreamer::emitCFIWindowSave(Loc); OS << "\t.cfi_window_save"; diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp index e8f000a584839..e80c15eb7463d 100644 --- a/llvm/lib/MC/MCDwarf.cpp +++ b/llvm/lib/MC/MCDwarf.cpp @@ -1292,6 +1292,47 @@ void MCGenDwarfLabelEntry::Make(MCSymbol *Symbol, MCStreamer *MCOS, MCGenDwarfLabelEntry(Name, FileNumber, LineNumber, Label)); } +void MCCFIInstruction::replaceRegister(unsigned FromReg, unsigned ToReg) { + auto ReplaceReg = [=](unsigned &Reg) { + if (Reg == FromReg) + Reg = ToReg; + }; + + // Replace registers in the shared fields. + if (Operation == OpRegister) { + ReplaceReg(U.RR.Register); + ReplaceReg(U.RR.Register2); + } else if (Operation == OpLLVMDefAspaceCfa) { + ReplaceReg(U.RIA.Register); + } else if (Operation == OpDefCfa || Operation == OpOffset || + Operation == OpRestore || Operation == OpUndefined || + Operation == OpSameValue || Operation == OpDefCfaRegister || + Operation == OpRelOffset || Operation == OpLLVMVectorRegisters || + Operation == OpLLVMRegisterPair || + Operation == OpLLVMVectorOffset || + Operation == OpLLVMVectorRegisterMask) { + ReplaceReg(U.RI.Register); + } + + // Replace registers in the "ExtraFields" structures. + if (Operation == OpLLVMRegisterPair) { + auto &Fields = getExtraFields(); + ReplaceReg(Fields.Reg1); + ReplaceReg(Fields.Reg2); + } else if (Operation == OpLLVMVectorRegisters) { + auto &Fields = getExtraFields(); + for (auto &VR : Fields.VectorRegisters) + ReplaceReg(VR.Register); + } else if (Operation == OpLLVMVectorOffset) { + auto &Fields = getExtraFields(); + ReplaceReg(Fields.MaskRegister); + } else if (Operation == OpLLVMVectorRegisterMask) { + auto &Fields = getExtraFields(); + ReplaceReg(Fields.SpillRegister); + ReplaceReg(Fields.MaskRegister); + } +} + static int getDataAlignmentFactor(MCStreamer &streamer) { MCContext &context = streamer.getContext(); const MCAsmInfo *asmInfo = context.getAsmInfo(); @@ -1377,6 +1418,16 @@ static void emitEncodingByte(MCObjectStreamer &Streamer, unsigned Encoding) { Streamer.emitInt8(Encoding); } +static void encodeDwarfRegisterLocation(int DwarfReg, raw_ostream &OS) { + assert(DwarfReg >= 0); + if (DwarfReg < 32) { + OS << uint8_t(dwarf::DW_OP_reg0 + DwarfReg); + } else { + OS << uint8_t(dwarf::DW_OP_regx); + encodeULEB128(DwarfReg, OS); + } +} + void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) { int dataAlignmentFactor = getDataAlignmentFactor(Streamer); auto *MRI = Streamer.getContext().getRegisterInfo(); @@ -1521,9 +1572,57 @@ void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) { case MCCFIInstruction::OpEscape: Streamer.emitBytes(Instr.getValues()); return; + case MCCFIInstruction::OpLabel: Streamer.emitLabel(Instr.getCfiLabel(), Instr.getLoc()); return; + + case MCCFIInstruction::OpLLVMRegisterPair: { + // CFI for a register spilled to a pair of SGPRs is implemented as an + // expression(E) rule where E is a composite location description with + // multiple parts each referencing SGPR register location storage with a bit + // offset of 0. In other words we generate the following DWARF: + // + // DW_CFA_expression: , + // (DW_OP_regx ) (DW_OP_piece ) + // (DW_OP_regx ) (DW_OP_piece ) + // + // The memory location description for the current CFA is pushed on the + // stack before E is evaluated, but we choose not to drop it as it would + // require a longer expression E and DWARF defines the result of the + // evaulation to be the location description on the top of the stack (i.e. + // the implictly pushed one is just ignored.) + + const auto &Fields = + Instr.getExtraFields(); + + SmallString<10> Block; + raw_svector_ostream OSBlock(Block); + encodeDwarfRegisterLocation(Fields.Reg1, OSBlock); + if (Fields.Reg1SizeInBits % 8 == 0) { + OSBlock << uint8_t(dwarf::DW_OP_piece); + encodeULEB128(Fields.Reg1SizeInBits / 8, OSBlock); + } else { + OSBlock << uint8_t(dwarf::DW_OP_bit_piece); + encodeULEB128(Fields.Reg1SizeInBits, OSBlock); + encodeULEB128(0, OSBlock); + } + encodeDwarfRegisterLocation(Fields.Reg2, OSBlock); + if (Fields.Reg2SizeInBits % 8 == 0) { + OSBlock << uint8_t(dwarf::DW_OP_piece); + encodeULEB128(Fields.Reg2SizeInBits / 8, OSBlock); + } else { + OSBlock << uint8_t(dwarf::DW_OP_bit_piece); + encodeULEB128(Fields.Reg2SizeInBits, OSBlock); + encodeULEB128(0, OSBlock); + } + + Streamer.emitInt8(dwarf::DW_CFA_expression); + Streamer.emitULEB128IntValue(Instr.getRegister()); + Streamer.emitULEB128IntValue(Block.size()); + Streamer.emitBinaryData(StringRef(&Block[0], Block.size())); + return; + } case MCCFIInstruction::OpValOffset: { unsigned Reg = Instr.getRegister(); if (!IsEH) @@ -1543,7 +1642,138 @@ void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) { } return; } + + case MCCFIInstruction::OpLLVMVectorRegisters: { + // CFI for an SGPR spilled to a multiple lanes of VGPRs is implemented as an + // expression(E) rule where E is a composite location description with + // multiple parts each referencing VGPR register location storage with a bit + // offset of the lane index multiplied by the size of a lane. In other words + // we generate the following DWARF: + // + // DW_CFA_expression: , + // (DW_OP_regx ) (DW_OP_bit_piece , *) + // (DW_OP_regx ) (DW_OP_bit_piece , *) + // ... + // (DW_OP_regx ) (DW_OP_bit_piece , *) + // + // However if we're only using a single lane then we can emit a slightly + // more optimal form: + // + // DW_CFA_expression: , + // (DW_OP_regx ) (DW_OP_LLVM_offset_uconst *) + // + // The memory location description for the current CFA is pushed on the + // stack before E is evaluated, but we choose not to drop it as it would + // require a longer expression E and DWARF defines the result of the + // evaulation to be the location description on the top of the stack (i.e. + // the implictly pushed one is just ignored.) + + const auto &VRs = + Instr.getExtraFields() + .VectorRegisters; + + SmallString<20> Block; + raw_svector_ostream OSBlock(Block); + + if (VRs.size() == 1 && VRs[0].SizeInBits % 8 == 0) { + encodeDwarfRegisterLocation(VRs[0].Register, OSBlock); + OSBlock << uint8_t(dwarf::DW_OP_LLVM_user) + << uint8_t(dwarf::DW_OP_LLVM_offset_uconst); + encodeULEB128((VRs[0].SizeInBits / 8) * VRs[0].Lane, OSBlock); + } else { + for (const auto &VR : VRs) { + // TODO: Detect when we can merge multiple adjacent pieces, or even + // reduce this to a register location description (when all pieces are + // adjacent). + encodeDwarfRegisterLocation(VR.Register, OSBlock); + OSBlock << uint8_t(dwarf::DW_OP_bit_piece); + encodeULEB128(VR.SizeInBits, OSBlock); + encodeULEB128(VR.SizeInBits * VR.Lane, OSBlock); + } + } + + Streamer.emitInt8(dwarf::DW_CFA_expression); + Streamer.emitULEB128IntValue(Instr.getRegister()); + Streamer.emitULEB128IntValue(Block.size()); + Streamer.emitBinaryData(StringRef(&Block[0], Block.size())); + return; + } + + case MCCFIInstruction::OpLLVMVectorOffset: { + // CFI for a vector register spilled to memory is implemented as an + // expression(E) rule where E is a location description. + // + // DW_CFA_expression: , + // (DW_OP_regx ) + // (DW_OP_swap) + // (DW_OP_LLVM_offset_uconst ) + // (DW_OP_LLVM_call_frame_entry_reg ) + // (DW_OP_deref_size ) + // (DW_OP_LLVM_select_bit_piece ) + + const auto &Fields = + Instr.getExtraFields(); + + SmallString<20> Block; + raw_svector_ostream OSBlock(Block); + encodeDwarfRegisterLocation(Instr.getRegister(), OSBlock); + OSBlock << uint8_t(dwarf::DW_OP_swap); + OSBlock << uint8_t(dwarf::DW_OP_LLVM_user) + << uint8_t(dwarf::DW_OP_LLVM_offset_uconst); + encodeULEB128(Instr.getOffset(), OSBlock); + OSBlock << uint8_t(dwarf::DW_OP_LLVM_user) + << uint8_t(dwarf::DW_OP_LLVM_call_frame_entry_reg); + encodeULEB128(Fields.MaskRegister, OSBlock); + OSBlock << uint8_t(dwarf::DW_OP_deref_size); + OSBlock << uint8_t(Fields.MaskRegisterSizeInBits / 8); + OSBlock << uint8_t(dwarf::DW_OP_LLVM_user) + << uint8_t(dwarf::DW_OP_LLVM_select_bit_piece); + encodeULEB128(Fields.RegisterSizeInBits, OSBlock); + encodeULEB128(Fields.MaskRegisterSizeInBits, OSBlock); + + Streamer.emitInt8(dwarf::DW_CFA_expression); + Streamer.emitULEB128IntValue(Instr.getRegister()); + Streamer.emitULEB128IntValue(Block.size()); + Streamer.emitBinaryData(StringRef(&Block[0], Block.size())); + return; + } + case MCCFIInstruction::OpLLVMVectorRegisterMask: { + // CFI for a VGPR/AGPR partially spilled to another VGPR/AGPR dependent on + // an EXEC mask is implemented as an expression(E) rule where E is a + // location description. + // + // DW_CFA_expression: , + // (DW_OP_regx ) + // (DW_OP_regx ) + // (DW_OP_LLVM_call_frame_entry_reg ) + // (DW_OP_deref_size ) + // (DW_OP_LLVM_select_bit_piece ) + + const auto Fields = + Instr.getExtraFields(); + + SmallString<20> Block; + raw_svector_ostream OSBlock(Block); + encodeDwarfRegisterLocation(Instr.getRegister(), OSBlock); + encodeDwarfRegisterLocation(Fields.SpillRegister, OSBlock); + OSBlock << uint8_t(dwarf::DW_OP_LLVM_user) + << uint8_t(dwarf::DW_OP_LLVM_call_frame_entry_reg); + encodeULEB128(Fields.MaskRegister, OSBlock); + OSBlock << uint8_t(dwarf::DW_OP_deref_size) + << uint8_t(Fields.MaskRegisterSizeInBits / 8); + OSBlock << uint8_t(dwarf::DW_OP_LLVM_user) + << uint8_t(dwarf::DW_OP_LLVM_select_bit_piece); + encodeULEB128(Fields.SpillRegisterLaneSizeInBits, OSBlock); + encodeULEB128(Fields.MaskRegisterSizeInBits, OSBlock); + + Streamer.emitInt8(dwarf::DW_CFA_expression); + Streamer.emitULEB128IntValue(Instr.getRegister()); + Streamer.emitULEB128IntValue(Block.size()); + Streamer.emitBinaryData(StringRef(&Block[0], Block.size())); + return; } + } + llvm_unreachable("Unhandled case in switch"); } @@ -1651,6 +1881,7 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) { MCContext &context = Streamer.getContext(); const MCRegisterInfo *MRI = context.getRegisterInfo(); const MCObjectFileInfo *MOFI = context.getObjectFileInfo(); + const MCAsmInfo *MAI = context.getAsmInfo(); MCSymbol *sectionStart = context.createTempSymbol(); Streamer.emitLabel(sectionStart); @@ -1680,8 +1911,8 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) { uint8_t CIEVersion = getCIEVersion(IsEH, context.getDwarfVersion()); Streamer.emitInt8(CIEVersion); + SmallString<8> Augmentation; if (IsEH) { - SmallString<8> Augmentation; Augmentation += "z"; if (Frame.Personality) Augmentation += "P"; @@ -1694,8 +1925,10 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) { Augmentation += "B"; if (Frame.IsMTETaggedFrame) Augmentation += "G"; - Streamer.emitBytes(Augmentation); } + if (MAI->supportsHeterogeneousDebuggingExtensions()) + Augmentation += "[llvm:v0.0]"; + Streamer.emitBytes(Augmentation); Streamer.emitInt8(0); if (CIEVersion >= 4) { @@ -1759,7 +1992,6 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) { // Initial Instructions - const MCAsmInfo *MAI = context.getAsmInfo(); if (!Frame.IsSimple) { const std::vector &Instructions = MAI->getInitialFrameState(); diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp index dd1bc2be5feb4..3a18e1041b726 100644 --- a/llvm/lib/MC/MCParser/AsmParser.cpp +++ b/llvm/lib/MC/MCParser/AsmParser.cpp @@ -493,6 +493,10 @@ class AsmParser : public MCAsmParser { DK_CFI_LLVM_DEF_ASPACE_CFA, DK_CFI_OFFSET, DK_CFI_REL_OFFSET, + DK_CFI_LLVM_REGISTER_PAIR, + DK_CFI_LLVM_VECTOR_REGISTERS, + DK_CFI_LLVM_VECTOR_OFFSET, + DK_CFI_LLVM_VECTOR_REGISTER_MASK, DK_CFI_PERSONALITY, DK_CFI_LSDA, DK_CFI_REMEMBER_STATE, @@ -610,6 +614,10 @@ class AsmParser : public MCAsmParser { bool parseDirectiveCFIReturnColumn(SMLoc DirectiveLoc); bool parseDirectiveCFISignalFrame(SMLoc DirectiveLoc); bool parseDirectiveCFIUndefined(SMLoc DirectiveLoc); + bool parseDirectiveCFILLVMRegisterPair(SMLoc DirectiveLoc); + bool parseDirectiveCFILLVMVectorRegisters(SMLoc DirectiveLoc); + bool parseDirectiveCFILLVMVectorOffset(SMLoc DirectiveLoc); + bool parseDirectiveCFILLVMVectorRegisterMask(SMLoc DirectiveLoc); bool parseDirectiveCFILabel(SMLoc DirectiveLoc); bool parseDirectiveCFIValOffset(SMLoc DirectiveLoc); @@ -2116,6 +2124,14 @@ bool AsmParser::parseStatement(ParseStatementInfo &Info, return parseDirectiveCFIOffset(IDLoc); case DK_CFI_REL_OFFSET: return parseDirectiveCFIRelOffset(IDLoc); + case DK_CFI_LLVM_REGISTER_PAIR: + return parseDirectiveCFILLVMRegisterPair(IDLoc); + case DK_CFI_LLVM_VECTOR_REGISTERS: + return parseDirectiveCFILLVMVectorRegisters(IDLoc); + case DK_CFI_LLVM_VECTOR_OFFSET: + return parseDirectiveCFILLVMVectorOffset(IDLoc); + case DK_CFI_LLVM_VECTOR_REGISTER_MASK: + return parseDirectiveCFILLVMVectorRegisterMask(IDLoc); case DK_CFI_PERSONALITY: return parseDirectiveCFIPersonalityOrLsda(true); case DK_CFI_LSDA: @@ -2530,28 +2546,26 @@ bool AsmParser::expandMacro(raw_svector_ostream &OS, MCAsmMacro &Macro, } } - if (!isIdentifierChar(Body[I]) || IsDarwin) { - OS << Body[I++]; - continue; - } - - const size_t Start = I; - while (++I && isIdentifierChar(Body[I])) { - } - StringRef Token(Body.data() + Start, I - Start); - if (AltMacroMode) { + if (AltMacroMode && isIdentifierChar(Body[I])) { + size_t Len = 1; + while (I + Len != End && isIdentifierChar(Body[I + Len])) + ++Len; + StringRef Argument(Body.data() + I, Len); unsigned Index = 0; for (; Index != NParameters; ++Index) - if (Parameters[Index].Name == Token) + if (Parameters[Index].Name == Argument) break; if (Index != NParameters) { expandArg(Index); + I += Len; if (I != End && Body[I] == '&') ++I; continue; } } - OS << Token; + + OS << Body[I]; + ++I; } ++Macro.Count; @@ -4410,6 +4424,91 @@ bool AsmParser::parseDirectiveCFIUndefined(SMLoc DirectiveLoc) { return false; } +/// parseDirectiveCFILLVMRegisterPair +/// ::= .cfi_llvm_register_pair reg, r1, r1size, r2, r2size +bool AsmParser::parseDirectiveCFILLVMRegisterPair(SMLoc DirectiveLoc) { + int64_t Register = 0; + int64_t R1 = 0, R2 = 0; + int64_t R1Size = 0, R2Size = 0; + + if (parseRegisterOrRegisterNumber(Register, DirectiveLoc) || parseComma() || + parseRegisterOrRegisterNumber(R1, DirectiveLoc) || parseComma() || + parseAbsoluteExpression(R1Size) || parseComma() || + parseRegisterOrRegisterNumber(R2, DirectiveLoc) || parseComma() || + parseAbsoluteExpression(R2Size) || parseEOL()) + return true; + + getStreamer().emitCFILLVMRegisterPair(Register, R1, R1Size, R2, R2Size, + DirectiveLoc); + return false; +} + +/// parseDirectiveCFILLVMVectorRegisters +/// ::= .cfi_llvm_vector_registers reg, vreg0, vlane0, vreg0size, +bool AsmParser::parseDirectiveCFILLVMVectorRegisters(SMLoc DirectiveLoc) { + int64_t Register = 0; + std::vector VRs; + + if (parseRegisterOrRegisterNumber(Register, DirectiveLoc) || parseComma()) + return true; + + do { + int64_t VectorRegister = 0; + int64_t Lane = 0; + int64_t Size = 0; + if (parseRegisterOrRegisterNumber(VectorRegister, DirectiveLoc) || + parseComma() || parseIntToken(Lane, "expected a lane number") || + parseComma() || parseAbsoluteExpression(Size)) + return true; + VRs.push_back({unsigned(VectorRegister), unsigned(Lane), unsigned(Size)}); + } while (parseOptionalToken(AsmToken::Comma)); + + if (parseEOL()) + return true; + + getStreamer().emitCFILLVMVectorRegisters(Register, std::move(VRs), + DirectiveLoc); + return false; +} + +/// parseDirectiveCFILLVMVectorOffset +/// ::= .cfi_llvm_vector_offset register, register-size, mask, mask-size, offset +bool AsmParser::parseDirectiveCFILLVMVectorOffset(SMLoc DirectiveLoc) { + int64_t Register = 0, MaskRegister = 0; + int64_t RegisterSize = 0, MaskRegisterSize = 0; + int64_t Offset = 0; + + if (parseRegisterOrRegisterNumber(Register, DirectiveLoc) || parseComma() || + parseAbsoluteExpression(RegisterSize) || parseComma() || + parseRegisterOrRegisterNumber(MaskRegister, DirectiveLoc) || + parseComma() || parseAbsoluteExpression(MaskRegisterSize) || + parseComma() || parseAbsoluteExpression(Offset) || parseEOL()) + return true; + + getStreamer().emitCFILLVMVectorOffset(Register, RegisterSize, MaskRegister, + MaskRegisterSize, Offset, DirectiveLoc); + return false; +} + +/// parseDirectiveCFILLVMVectorOffset +/// ::= .cfi_llvm_vector_register_mask register, spill-reg, spill-reg-lane-size, +/// mask-reg, mask-reg-size +bool AsmParser::parseDirectiveCFILLVMVectorRegisterMask(SMLoc DirectiveLoc) { + int64_t Register = 0, SpillReg = 0, MaskReg = 0; + int64_t SpillRegLaneSize = 0, MaskRegSize = 0; + + if (parseRegisterOrRegisterNumber(Register, DirectiveLoc) || parseComma() || + parseRegisterOrRegisterNumber(SpillReg, DirectiveLoc) || parseComma() || + parseAbsoluteExpression(SpillRegLaneSize) || parseComma() || + parseRegisterOrRegisterNumber(MaskReg, DirectiveLoc) || parseComma() || + parseAbsoluteExpression(MaskRegSize) || parseEOL()) + return true; + + getStreamer().emitCFILLVMVectorRegisterMask( + Register, SpillReg, SpillRegLaneSize, MaskReg, MaskRegSize, DirectiveLoc); + return false; +} + /// parseDirectiveCFILabel /// ::= .cfi_label label bool AsmParser::parseDirectiveCFILabel(SMLoc Loc) { @@ -5444,6 +5543,11 @@ void AsmParser::initializeDirectiveKindMap() { DirectiveKindMap[".cfi_llvm_def_aspace_cfa"] = DK_CFI_LLVM_DEF_ASPACE_CFA; DirectiveKindMap[".cfi_offset"] = DK_CFI_OFFSET; DirectiveKindMap[".cfi_rel_offset"] = DK_CFI_REL_OFFSET; + DirectiveKindMap[".cfi_llvm_register_pair"] = DK_CFI_LLVM_REGISTER_PAIR; + DirectiveKindMap[".cfi_llvm_vector_registers"] = DK_CFI_LLVM_VECTOR_REGISTERS; + DirectiveKindMap[".cfi_llvm_vector_offset"] = DK_CFI_LLVM_VECTOR_OFFSET; + DirectiveKindMap[".cfi_llvm_vector_register_mask"] = + DK_CFI_LLVM_VECTOR_REGISTER_MASK; DirectiveKindMap[".cfi_personality"] = DK_CFI_PERSONALITY; DirectiveKindMap[".cfi_lsda"] = DK_CFI_LSDA; DirectiveKindMap[".cfi_remember_state"] = DK_CFI_REMEMBER_STATE; diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp index 8a8f11122673f..23881972d973a 100644 --- a/llvm/lib/MC/MCParser/MasmParser.cpp +++ b/llvm/lib/MC/MCParser/MasmParser.cpp @@ -696,7 +696,6 @@ class MasmParser : public MCAsmParser { DK_ELSEIFIDNI, DK_ELSE, DK_ENDIF, - DK_MACRO, DK_EXITM, DK_ENDM, @@ -5275,6 +5274,10 @@ void MasmParser::initializeDirectiveKindMap() { // DirectiveKindMap[".cfi_def_cfa_register"] = DK_CFI_DEF_CFA_REGISTER; // DirectiveKindMap[".cfi_offset"] = DK_CFI_OFFSET; // DirectiveKindMap[".cfi_rel_offset"] = DK_CFI_REL_OFFSET; + // DirectiveKindMap[".cfi_llvm_register_pair"] = DK_CFI_LLVM_REGISTER_PAIR; + // DirectiveKindMap[".cfi_llvm_vector_registers"] = + // DK_CFI_LLVM_VECTOR_REGISTERS; + // DirectiveKindMap[".cfi_llvm_vector_offset"] = DK_CFI_LLVM_VECTOR_OFFSET; // DirectiveKindMap[".cfi_personality"] = DK_CFI_PERSONALITY; // DirectiveKindMap[".cfi_lsda"] = DK_CFI_LSDA; // DirectiveKindMap[".cfi_remember_state"] = DK_CFI_REMEMBER_STATE; diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp index bc7398120096e..27a87a6281340 100644 --- a/llvm/lib/MC/MCStreamer.cpp +++ b/llvm/lib/MC/MCStreamer.cpp @@ -630,6 +630,60 @@ void MCStreamer::emitCFIGnuArgsSize(int64_t Size, SMLoc Loc) { CurFrame->Instructions.push_back(std::move(Instruction)); } +void MCStreamer::emitCFILLVMRegisterPair(int64_t Register, int64_t R1, + int64_t R1Size, int64_t R2, + int64_t R2Size, SMLoc Loc) { + MCSymbol *Label = emitCFILabel(); + MCCFIInstruction Instruction = MCCFIInstruction::createLLVMRegisterPair( + Label, Register, R1, R1Size, R2, R2Size, Loc); + MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); + if (!CurFrame) + return; + CurFrame->Instructions.push_back(std::move(Instruction)); +} + +void MCStreamer::emitCFILLVMVectorRegisters( + int64_t Register, std::vector VRs, + SMLoc Loc) { + MCSymbol *Label = emitCFILabel(); + MCCFIInstruction Instruction = MCCFIInstruction::createLLVMVectorRegisters( + Label, Register, std::move(VRs), Loc); + MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); + if (!CurFrame) + return; + CurFrame->Instructions.push_back(std::move(Instruction)); +} + +void MCStreamer::emitCFILLVMVectorOffset(int64_t Register, + int64_t RegisterSizeInBits, + int64_t MaskRegister, + int64_t MaskRegisterSizeInBits, + int64_t Offset, SMLoc Loc) { + MCSymbol *Label = emitCFILabel(); + MCCFIInstruction Instruction = MCCFIInstruction::createLLVMVectorOffset( + Label, Register, RegisterSizeInBits, MaskRegister, MaskRegisterSizeInBits, + Offset, Loc); + MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); + if (!CurFrame) + return; + CurFrame->Instructions.push_back(std::move(Instruction)); +} + +void MCStreamer::emitCFILLVMVectorRegisterMask( + int64_t Register, int64_t SpillRegister, + int64_t SpillRegisterLaneSizeInBits, int64_t MaskRegister, + int64_t MaskRegisterSizeInBits, SMLoc Loc) { + + MCSymbol *Label = emitCFILabel(); + MCCFIInstruction Instruction = MCCFIInstruction::createLLVMVectorRegisterMask( + Label, Register, SpillRegister, SpillRegisterLaneSizeInBits, MaskRegister, + MaskRegisterSizeInBits, Loc); + MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); + if (!CurFrame) + return; + CurFrame->Instructions.push_back(std::move(Instruction)); +} + void MCStreamer::emitCFISignalFrame() { MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) diff --git a/llvm/lib/Object/ObjectFile.cpp b/llvm/lib/Object/ObjectFile.cpp index b0e4ea0a51ba1..c58287015a48c 100644 --- a/llvm/lib/Object/ObjectFile.cpp +++ b/llvm/lib/Object/ObjectFile.cpp @@ -214,7 +214,6 @@ ObjectFile::createObjectFile(StringRef ObjectPath) { if (std::error_code EC = FileOrErr.getError()) return errorCodeToError(EC); std::unique_ptr Buffer = std::move(FileOrErr.get()); - Expected> ObjOrErr = createObjectFile(Buffer->getMemBufferRef()); if (Error Err = ObjOrErr.takeError()) diff --git a/llvm/lib/Object/OffloadBinary.cpp b/llvm/lib/Object/OffloadBinary.cpp index 3fff6b6a09e08..e710d4eb12527 100644 --- a/llvm/lib/Object/OffloadBinary.cpp +++ b/llvm/lib/Object/OffloadBinary.cpp @@ -16,18 +16,25 @@ #include "llvm/MC/StringTableBuilder.h" #include "llvm/Object/Archive.h" #include "llvm/Object/Binary.h" +#include "llvm/Object/COFF.h" #include "llvm/Object/ELFObjectFile.h" #include "llvm/Object/Error.h" #include "llvm/Object/IRObjectFile.h" #include "llvm/Object/ObjectFile.h" #include "llvm/Support/Alignment.h" +#include "llvm/Support/BinaryStreamReader.h" #include "llvm/Support/SourceMgr.h" +#include "llvm/Support/Timer.h" using namespace llvm; using namespace llvm::object; namespace { +static llvm::TimerGroup + OffloadBundlerTimerGroup("Offload Bundler Timer Group", + "Timer group for offload bundler"); + /// Attempts to extract all the embedded device images contained inside the /// buffer \p Contents. The buffer is expected to contain a valid offloading /// binary format. diff --git a/llvm/lib/Object/OffloadBundle.cpp b/llvm/lib/Object/OffloadBundle.cpp index 046cde8640b49..82832c5539b3f 100644 --- a/llvm/lib/Object/OffloadBundle.cpp +++ b/llvm/lib/Object/OffloadBundle.cpp @@ -135,7 +135,8 @@ Error OffloadBundleFatBin::readEntries(StringRef Buffer, return Err; auto Entry = std::make_unique( - EntryOffset + SectionOffset, EntrySize, EntryIDSize, EntryID); + EntryOffset + SectionOffset, EntrySize, EntryIDSize, + std::move(EntryID.str())); Entries.push_back(*Entry); } diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp index bd03ac090721c..2875cbd480951 100644 --- a/llvm/lib/Passes/PassBuilderPipelines.cpp +++ b/llvm/lib/Passes/PassBuilderPipelines.cpp @@ -173,7 +173,7 @@ static cl::opt EnableModuleInliner("enable-module-inliner", cl::desc("Enable module inliner")); static cl::opt PerformMandatoryInliningsFirst( - "mandatory-inlining-first", cl::init(false), cl::Hidden, + "mandatory-inlining-first", cl::init(true), cl::Hidden, cl::desc("Perform mandatory inlinings module-wide, before performing " "inlining")); @@ -307,6 +307,11 @@ static cl::opt InstrumentColdFuncOnlyPath( extern cl::opt UseCtxProfile; extern cl::opt PGOInstrumentColdFunctionOnly; +static cl::opt EnableEarlyOpenMPOpt( + "enable-early-openmp-opt", cl::init(false), cl::Hidden, + cl::desc("Enable early execution of the OpenMP optimization pass" + " (default = off)")); + extern cl::opt EnableMemProfContextDisambiguation; } // namespace llvm @@ -413,7 +418,8 @@ static bool isLTOPreLink(ThinOrFullLTOPhase Phase) { // Helper to check if the current compilation phase is LTO backend static bool isLTOPostLink(ThinOrFullLTOPhase Phase) { return Phase == ThinOrFullLTOPhase::ThinLTOPostLink || - Phase == ThinOrFullLTOPhase::FullLTOPostLink; + Phase == ThinOrFullLTOPhase::FullLTOPostLink || + Phase == ThinOrFullLTOPhase::CustomLTOPostLink; } // Helper to wrap conditionally Coro passes. @@ -1109,6 +1115,10 @@ PassBuilder::buildModuleSimplificationPipeline(OptimizationLevel Level, // frontend. Not necessary with LTO post link pipelines since the pre link // pipeline already cleaned up the frontend output. if (Phase != ThinOrFullLTOPhase::ThinLTOPostLink) { + + if (EnableEarlyOpenMPOpt) + MPM.addPass(OpenMPOptPass()); + // Do basic inference of function attributes from known properties of system // libraries and other oracles. MPM.addPass(InferFunctionAttrsPass()); @@ -1272,8 +1282,6 @@ PassBuilder::buildModuleSimplificationPipeline(OptimizationLevel Level, PGOOpt->Action == PGOOptions::SampleUse)) MPM.addPass(PGOForceFunctionAttrsPass(PGOOpt->ColdOptType)); - MPM.addPass(AlwaysInlinerPass(/*InsertLifetimeIntrinsics=*/true)); - if (EnableModuleInliner) MPM.addPass(buildModuleInlinerPipeline(Level, Phase)); else @@ -1654,7 +1662,8 @@ PassBuilder::buildPerModuleDefaultPipeline(OptimizationLevel Level, // Currently this pipeline is only invoked in an LTO pre link pass or when we // are not running LTO. If that changes the below checks may need updating. - assert(isLTOPreLink(Phase) || Phase == ThinOrFullLTOPhase::None); + assert(isLTOPreLink(Phase) || Phase == ThinOrFullLTOPhase::None || + Phase == ThinOrFullLTOPhase::CustomLTOPostLink); // If we are invoking this in non-LTO mode, remove any MemProf related // attributes and metadata, as we don't know whether we are linking with diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 1853cdd45d0ee..dfc47626a1113 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -259,6 +259,13 @@ MODULE_PASS_WITH_PARAMS( return buildPerModuleDefaultPipeline(L); }, parseOptLevelParam, "O0;O1;O2;O3;Os;Oz") +MODULE_PASS_WITH_PARAMS( + "default-post-link", "", [&](OptimizationLevel L) { + setupOptionsForPipelineAlias(PTO, L); + return buildPerModuleDefaultPipeline( + L, ThinOrFullLTOPhase::CustomLTOPostLink); + }, + parseOptLevelParam, "O0;O1;O2;O3;Os;Oz") MODULE_PASS_WITH_PARAMS( "thinlto-pre-link", "", [&](OptimizationLevel L) { setupOptionsForPipelineAlias(PTO, L); diff --git a/llvm/lib/Support/Caching.cpp b/llvm/lib/Support/Caching.cpp index 40a5c44771b65..52fd0ba7d681c 100644 --- a/llvm/lib/Support/Caching.cpp +++ b/llvm/lib/Support/Caching.cpp @@ -80,6 +80,7 @@ Expected llvm::localCache(const Twine &CacheNameRef, sys::fs::TempFile TempFile; std::string ModuleName; unsigned Task; + bool Committed = false; CacheStream(std::unique_ptr OS, AddBufferFn AddBuffer, sys::fs::TempFile TempFile, std::string EntryPath, diff --git a/llvm/lib/Support/CommandLine.cpp b/llvm/lib/Support/CommandLine.cpp index 9491ec049f79d..5e5fe79f51cbf 100644 --- a/llvm/lib/Support/CommandLine.cpp +++ b/llvm/lib/Support/CommandLine.cpp @@ -2565,7 +2565,7 @@ class VersionPrinter { #ifdef PACKAGE_VENDOR OS << PACKAGE_VENDOR << " "; #else - OS << "LLVM (http://llvm.org/):\n "; + OS << "AOMP-18.0-12 (http://github.com/ROCm/aomp):\n Source ID:18.0-12-ce1873ac686bb90ddec72bb99889a4e80e2de382\n "; #endif OS << PACKAGE_NAME << " version " << PACKAGE_VERSION << "\n "; #if LLVM_IS_DEBUG_BUILD diff --git a/llvm/lib/Support/DynamicLibrary.cpp b/llvm/lib/Support/DynamicLibrary.cpp index f1c15c00cedea..3dbde46895c3f 100644 --- a/llvm/lib/Support/DynamicLibrary.cpp +++ b/llvm/lib/Support/DynamicLibrary.cpp @@ -15,6 +15,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringMap.h" #include "llvm/Config/config.h" +#include "llvm/Support/ManagedStatic.h" #include "llvm/Support/Mutex.h" #include @@ -117,6 +118,12 @@ class DynamicLibrary::HandleSet { }; namespace { +// Collection of symbol name/value pairs to be searched prior to any libraries. +static llvm::ManagedStatic> ExplicitSymbols; +// Collection of known library handles. +static llvm::ManagedStatic OpenedHandles; +// Lock for ExplicitSymbols and OpenedHandles. +static llvm::ManagedStatic> SymbolsMutex; struct Globals { // Collection of symbol name/value pairs to be searched prior to any @@ -157,18 +164,20 @@ void *SearchForAddressOfSpecialSymbol(const char *SymbolName) { } // namespace llvm void DynamicLibrary::AddSymbol(StringRef SymbolName, void *SymbolValue) { - auto &G = getGlobals(); - SmartScopedLock Lock(G.SymbolsMutex); - G.ExplicitSymbols[SymbolName] = SymbolValue; + SmartScopedLock Lock(*SymbolsMutex); + (*ExplicitSymbols)[SymbolName] = SymbolValue; } DynamicLibrary DynamicLibrary::getPermanentLibrary(const char *FileName, std::string *Err) { - auto &G = getGlobals(); + // Force OpenedHandles to be added into the ManagedStatic list before any + // ManagedStatic can be added from static constructors in HandleSet::DLOpen. + HandleSet& HS = *OpenedHandles; + void *Handle = HandleSet::DLOpen(FileName, Err); if (Handle != &Invalid) { - SmartScopedLock Lock(G.SymbolsMutex); - G.OpenedHandles.AddLibrary(Handle, /*IsProcess*/ FileName == nullptr); + SmartScopedLock Lock(*SymbolsMutex); + HS.AddLibrary(Handle, /*IsProcess*/ FileName == nullptr); } return DynamicLibrary(Handle); @@ -176,11 +185,9 @@ DynamicLibrary DynamicLibrary::getPermanentLibrary(const char *FileName, DynamicLibrary DynamicLibrary::addPermanentLibrary(void *Handle, std::string *Err) { - auto &G = getGlobals(); - SmartScopedLock Lock(G.SymbolsMutex); + SmartScopedLock Lock(*SymbolsMutex); // If we've already loaded this library, tell the caller. - if (!G.OpenedHandles.AddLibrary(Handle, /*IsProcess*/ false, - /*CanClose*/ false)) + if (!OpenedHandles->AddLibrary(Handle, /*IsProcess*/false, /*CanClose*/false)) *Err = "Library already loaded"; return DynamicLibrary(Handle); @@ -217,20 +224,21 @@ void *DynamicLibrary::getAddressOfSymbol(const char *SymbolName) { void *DynamicLibrary::SearchForAddressOfSymbol(const char *SymbolName) { { - auto &G = getGlobals(); - SmartScopedLock Lock(G.SymbolsMutex); + SmartScopedLock Lock(*SymbolsMutex); // First check symbols added via AddSymbol(). - StringMap::iterator i = G.ExplicitSymbols.find(SymbolName); + if (ExplicitSymbols.isConstructed()) { + StringMap::iterator i = ExplicitSymbols->find(SymbolName); - if (i != G.ExplicitSymbols.end()) - return i->second; + if (i != ExplicitSymbols->end()) + return i->second; + } // Now search the libraries. - if (void *Ptr = G.OpenedHandles.Lookup(SymbolName, SearchOrder)) - return Ptr; - if (void *Ptr = G.OpenedTemporaryHandles.Lookup(SymbolName, SearchOrder)) - return Ptr; + if (OpenedHandles.isConstructed()) { + if (void *Ptr = OpenedHandles->Lookup(SymbolName, SearchOrder)) + return Ptr; + } } return llvm::SearchForAddressOfSpecialSymbol(SymbolName); diff --git a/llvm/lib/Support/Windows/DynamicLibrary.inc b/llvm/lib/Support/Windows/DynamicLibrary.inc index 4f8c96e78f6ce..be3050abd589a 100644 --- a/llvm/lib/Support/Windows/DynamicLibrary.inc +++ b/llvm/lib/Support/Windows/DynamicLibrary.inc @@ -35,7 +35,7 @@ void *DynamicLibrary::HandleSet::DLOpen(const char *File, std::string *Err) { // Create the instance and return it to be the *Process* handle // simillar to dlopen(NULL, RTLD_LAZY|RTLD_GLOBAL) if (!File) - return &getGlobals().OpenedHandles; + return &(*OpenedHandles); SmallVector FileUnicode; if (std::error_code ec = windows::UTF8ToUTF16(File, FileUnicode)) { @@ -54,7 +54,9 @@ void *DynamicLibrary::HandleSet::DLOpen(const char *File, std::string *Err) { } static DynamicLibrary::HandleSet *IsOpenedHandlesInstance(void *Handle) { - DynamicLibrary::HandleSet &Inst = getGlobals().OpenedHandles; + if (!OpenedHandles.isConstructed()) + return nullptr; + DynamicLibrary::HandleSet &Inst = *OpenedHandles; return Handle == &Inst ? &Inst : nullptr; } diff --git a/llvm/lib/Support/Windows/Path.inc b/llvm/lib/Support/Windows/Path.inc index be007b7abdb51..2a58b904e5333 100644 --- a/llvm/lib/Support/Windows/Path.inc +++ b/llvm/lib/Support/Windows/Path.inc @@ -449,9 +449,8 @@ static std::error_code setDeleteDisposition(HANDLE Handle, bool Delete) { if (!IsLocal) return errc::not_supported; - // The file is on a local drive, we can safely set FILE_DISPOSITION_INFO's - // flag. - Disposition.DeleteFile = true; + // The file is on a local drive, set the DeleteFile to true. + Disposition.DeleteFile = Delete; if (!SetFileInformationByHandle(Handle, FileDispositionInfo, &Disposition, sizeof(Disposition))) return mapWindowsError(::GetLastError()); diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index ce2b4a5f6f2e9..3a4f20a3bab34 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -445,6 +445,15 @@ extern char &AMDGPUPrintfRuntimeBindingID; void initializeAMDGPUResourceUsageAnalysisWrapperPassPass(PassRegistry &); extern char &AMDGPUResourceUsageAnalysisID; +struct AMDGPUExpandFeaturePredicatesPass + : PassInfoMixin { + const AMDGPUTargetMachine &TM; + AMDGPUExpandFeaturePredicatesPass(const AMDGPUTargetMachine &ATM) : TM(ATM) {} + PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); + + static bool isRequired() { return true; } +}; + struct AMDGPUPrintfRuntimeBindingPass : PassInfoMixin { PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp index 9907c88f4dfb8..1592c72070cf2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp @@ -13,6 +13,7 @@ #include "AMDGPU.h" #include "GCNSubtarget.h" #include "Utils/AMDGPUBaseInfo.h" +#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/IR/IntrinsicsAMDGPU.h" #include "llvm/IR/IntrinsicsR600.h" #include "llvm/Target/TargetMachine.h" @@ -1592,10 +1593,16 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM, AC.IsModulePass = true; AC.DefaultInitializeLiveInternals = false; AC.IndirectCalleeSpecializationCallback = - [](Attributor &A, const AbstractAttribute &AA, CallBase &CB, - Function &Callee, unsigned NumAssumedCallees) { - return !AMDGPU::isEntryFunctionCC(Callee.getCallingConv()) && - (NumAssumedCallees <= IndirectCallSpecializationThreshold); + [&TM](Attributor &A, const AbstractAttribute &AA, CallBase &CB, + Function &Callee, unsigned NumAssumedCallees) { + if (AMDGPU::isEntryFunctionCC(Callee.getCallingConv())) + return false; + // Singleton functions can be specialized. + if (NumAssumedCallees == 1) + return true; + // Otherwise specialize uniform values. + const auto &TTI = TM.getTargetTransformInfo(*CB.getCaller()); + return TTI.isAlwaysUniform(CB.getCalledOperand()); }; AC.IPOAmendableCB = [](const Function &F) { return F.getCallingConv() == CallingConv::AMDGPU_KERNEL; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUExpandFeaturePredicates.cpp b/llvm/lib/Target/AMDGPU/AMDGPUExpandFeaturePredicates.cpp new file mode 100644 index 0000000000000..195d933203e56 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/AMDGPUExpandFeaturePredicates.cpp @@ -0,0 +1,168 @@ +//===- AMDGPUExpandFeaturePredicates.cpp - Feature Predicate Expander Pass ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// This file implements a pass that deals with expanding AMDGCN generic feature +// predicates into target specific quantities / sequences. In this context, a +// generic feature predicate is an implementation detail global variable that +// is inserted by the FE as a consequence of using either the __builtin_cpu_is +// or the __builtin_amdgcn_is_invocable special builtins on an abstract target +// (AMDGCNSPIRV). These placeholder globals are used to guide target specific +// lowering, once the concrete target is known, by way of constant folding their +// value all the way into a terminator (i.e. a controlled block) or into a no +// live use scenario. We hard fail if the folding fails, to avoid obtuse BE +// errors or opaque run time errors. This pass should run as early as possible / +// immediately after Clang CodeGen, so that the optimisation pipeline and the BE +// operate with concrete target data. +//===----------------------------------------------------------------------===// + +#include "AMDGPU.h" +#include "AMDGPUTargetMachine.h" +#include "GCNSubtarget.h" + +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Analysis/ConstantFolding.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/Module.h" +#include "llvm/Pass.h" +#include "llvm/Passes/CodeGenPassBuilder.h" +#include "llvm/Transforms/Utils/Local.h" + +#include +#include + +using namespace llvm; + +namespace { +template void collectUsers(Value *V, C &Container) { + assert(V && "Must pass an existing Value!"); + + for (auto &&U : V->users()) + if (auto *I = dyn_cast(U)) + Container.insert(Container.end(), I); +} + +inline void setPredicate(const GCNSubtarget &ST, GlobalVariable *P) { + const bool IsFeature = P->getName().starts_with("llvm.amdgcn.has"); + const size_t Offset = + IsFeature ? sizeof("llvm.amdgcn.has") : sizeof("llvm.amdgcn.is"); + + std::string PV = P->getName().substr(Offset).str(); + if (IsFeature) { + size_t Dx = PV.find(','); + while (Dx != std::string::npos) { + PV.insert(++Dx, {'+'}); + + Dx = PV.find(',', Dx); + } + PV.insert(PV.cbegin(), '+'); + } + + Type *PTy = P->getValueType(); + P->setLinkage(GlobalValue::PrivateLinkage); + P->setExternallyInitialized(false); + + if (IsFeature) + P->setInitializer(ConstantInt::getBool(PTy, ST.checkFeatures(PV))); + else + P->setInitializer(ConstantInt::getBool(PTy, PV == ST.getCPU())); +} + +std::pair +unfoldableFound(Function *Caller, GlobalVariable *P, Instruction *NoFold) { + std::string W; + raw_string_ostream OS(W); + + OS << "Impossible to constant fold feature predicate: " << *P << " used by " + << *NoFold << ", please simplify.\n"; + + Caller->getContext().diagnose( + DiagnosticInfoUnsupported(*Caller, W, NoFold->getDebugLoc(), DS_Error)); + + return {PreservedAnalyses::none(), false}; +} + +std::pair +handlePredicate(const GCNSubtarget &ST, FunctionAnalysisManager &FAM, + SmallPtrSet &Predicated, GlobalVariable *P) { + setPredicate(ST, P); + + SmallPtrSet ToFold; + collectUsers(P, ToFold); + + if (ToFold.empty()) + return {PreservedAnalyses::all(), true}; + + do { + Instruction *I = *ToFold.begin(); + ToFold.erase(I); + + I->dropDroppableUses(); + + Function *F = I->getParent()->getParent(); + auto &DT = FAM.getResult(*F); + DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Lazy); + + if (auto *C = ConstantFoldInstruction(I, P->getDataLayout())) { + collectUsers(I, ToFold); + I->replaceAllUsesWith(C); + I->eraseFromParent(); + continue; + } else if (I->isTerminator() && + ConstantFoldTerminator(I->getParent(), true, nullptr, &DTU)) { + Predicated.insert(F); + + continue; + } + + return unfoldableFound(I->getParent()->getParent(), P, I); + } while (!ToFold.empty()); + + return {PreservedAnalyses::none(), true}; +} +} // Unnamed namespace. + +PreservedAnalyses +AMDGPUExpandFeaturePredicatesPass::run(Module &M, ModuleAnalysisManager &MAM) { + if (M.empty()) + return PreservedAnalyses::all(); + + SmallVector Predicates; + for (auto &&G : M.globals()) { + if (!G.isDeclaration() || !G.hasName()) + continue; + if (G.getName().starts_with("llvm.amdgcn.")) + Predicates.push_back(&G); + } + + if (Predicates.empty()) + return PreservedAnalyses::all(); + + const auto &ST = TM.getSubtarget( + *find_if(M, [](auto &&F) { return !F.isIntrinsic(); })); + + auto &FAM = MAM.getResult(M).getManager(); + SmallPtrSet Predicated; + auto Ret = PreservedAnalyses::all(); + for (auto &&P : Predicates) { + auto R = handlePredicate(ST, FAM, Predicated, P); + + if (!R.second) + break; + + Ret.intersect(R.first); + } + + for (auto &&P : Predicates) + P->eraseFromParent(); + for (auto &&F : Predicated) + removeUnreachableBlocks(*F); + + return Ret; +} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.cpp index 84f73918bc38c..d573c48100d38 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.cpp @@ -11,6 +11,11 @@ //===----------------------------------------------------------------------===// #include "AMDGPUFrameLowering.h" +#include "GCNSubtarget.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/IR/DebugInfoMetadata.h" +#include "llvm/Target/TargetMachine.h" using namespace llvm; AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, Align StackAl, @@ -63,3 +68,39 @@ unsigned AMDGPUFrameLowering::getStackWidth(const MachineFunction &MF) const { // T1.W = stack[1].w return 1; } + +DIExpression *AMDGPUFrameLowering::lowerFIArgToFPArg(const MachineFunction &MF, + const DIExpression *Expr, + uint64_t ArgIndex, + StackOffset Offset) const { + const DataLayout &DL = MF.getDataLayout(); + LLVMContext &Context = MF.getFunction().getParent()->getContext(); + const auto &ST = MF.getSubtarget(); + DIExprBuilder Builder(*Expr); + for (auto &&I = Builder.begin(); I != Builder.end(); ++I) { + if (auto *Arg = std::get_if(&*I)) { + if (Arg->getIndex() != ArgIndex) + continue; + + Type *ResultType = Arg->getResultType(); + // Weird case: we expect a pointer but on optimized builds it may not be + // the case. + if (!ResultType->isPointerTy()) + return Expr->getPoisoned(); + + unsigned PointerSizeInBits = + DL.getPointerSizeInBits(ResultType->getPointerAddressSpace()); + auto *IntTy = IntegerType::get(Context, PointerSizeInBits); + ConstantData *WavefrontSizeLog2 = static_cast( + ConstantInt::get(IntTy, ST.getWavefrontSizeLog2(), false)); + ConstantData *C = ConstantInt::get(IntTy, Offset.getFixed(), true); + SmallVector FL = {DIOp::Reinterpret(IntTy)}; + if (!ST.enableFlatScratch()) + FL.append({DIOp::Constant(WavefrontSizeLog2), DIOp::LShr()}); + FL.append( + {DIOp::Constant(C), DIOp::Add(), DIOp::Reinterpret(ResultType)}); + I = Builder.insert(++I, FL); + } + } + return Builder.intoExpression(); +} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h index 260a18e278cf2..3e6fad4bf270b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h @@ -32,6 +32,10 @@ class AMDGPUFrameLowering : public TargetFrameLowering { /// \returns The number of 32-bit sub-registers that are used when storing /// values to the stack. unsigned getStackWidth(const MachineFunction &MF) const; + + DIExpression *lowerFIArgToFPArg(const MachineFunction &MF, + const DIExpression *Expr, uint64_t ArgIndex, + StackOffset Offset) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp index a4ef524c43466..3b8f327ec58d8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp @@ -189,6 +189,8 @@ #include "llvm/Analysis/ScopedNoAliasAA.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/IR/Constants.h" +#include "llvm/IR/DIBuilder.h" +#include "llvm/IR/DebugInfo.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Dominators.h" #include "llvm/IR/IRBuilder.h" @@ -791,7 +793,7 @@ class AMDGPULowerModuleLDS { (Twine("llvm.amdgcn.kernel.") + Func.getName() + ".lds").str(); auto Replacement = - createLDSVariableReplacement(M, VarName, KernelUsedVariables); + createLDSVariableReplacement(M, VarName, KernelUsedVariables, &Func); // If any indirect uses, create a direct use to ensure allocation // TODO: Simpler to unconditionally mark used but that regresses @@ -1290,7 +1292,8 @@ class AMDGPULowerModuleLDS { static LDSVariableReplacement createLDSVariableReplacement( Module &M, std::string VarName, - DenseSet const &LDSVarsToTransform) { + DenseSet const &LDSVarsToTransform, + Function *F = nullptr) { // Create a struct instance containing LDSVarsToTransform and map from those // variables to ConstantExprGEP // Variables may be introduced to meet alignment requirements. No aliasing @@ -1319,6 +1322,14 @@ class AMDGPULowerModuleLDS { performOptimizedStructLayout(LayoutFields); + struct DIExpressionVarInfo { + GlobalVariable *Var; + Metadata *DIVar; + DIExpression::NewElementsRef Expr; + uint64_t Offset; + }; + SmallVector DIExpressionVarInfos; + std::vector LocalVars; BitVector IsPaddingField; LocalVars.reserve(LDSVarsToTransform.size()); // will be at least this large @@ -1347,6 +1358,16 @@ class AMDGPULowerModuleLDS { CurrentOffset += Padding; } + SmallVector OriginalGVEs; + FGV->getDebugInfo(OriginalGVEs); + for (const auto *OriginalGVE : OriginalGVEs) { + if (auto NewElementsRef = + OriginalGVE->getExpression()->getNewElementsRef()) { + DIExpressionVarInfos.push_back({FGV, OriginalGVE->getRawVariable(), + *NewElementsRef, CurrentOffset}); + } + } + LocalVars.push_back(FGV); IsPaddingField.push_back(false); CurrentOffset += F.Size; @@ -1369,6 +1390,36 @@ class AMDGPULowerModuleLDS { false); SGV->setAlignment(StructAlign); + for (auto VarInfo : DIExpressionVarInfos) { + DIExprBuilder ExprBuilder(Ctx); + for (auto Op : VarInfo.Expr) { + if (auto *ArgOp = std::get_if(&Op)) { + assert(ArgOp->getIndex() == 0u && + "DIOp-based DIExpression in DIGlobalVariableExpression must " + "have only one argument"); + Type *ArgTy = SGV->getType(); + assert(isa(ArgTy)); + Type *ResultTy = VarInfo.Var->getType(); + assert(isa(ResultTy)); + assert(ArgTy->getPointerAddressSpace() == + ResultTy->getPointerAddressSpace()); + unsigned PointerSizeInBits = + DL.getPointerSizeInBits(ArgTy->getPointerAddressSpace()); + auto *IntTy = IntegerType::get(Ctx, PointerSizeInBits); + ConstantData *C = ConstantInt::get(IntTy, VarInfo.Offset, true); + ExprBuilder.append(0u, ArgTy); + ExprBuilder.append(IntTy); + ExprBuilder.append(C); + ExprBuilder.append(); + ExprBuilder.append(ResultTy); + } else { + ExprBuilder.append(Op); + } + } + SGV->addDebugInfo(DIGlobalVariableExpression::get( + Ctx, VarInfo.DIVar, ExprBuilder.intoExpression())); + } + DenseMap Map; Type *I32 = Type::getInt32Ty(Ctx); for (size_t I = 0; I < LocalVars.size(); I++) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp index 680e7eb3de6be..940c1e3c21a39 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -318,6 +318,11 @@ static void emitVGPRBlockComment(const MachineInstr *MI, const SIInstrInfo *TII, } void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) { + switch (MI->getOpcode()) { + case TargetOpcode::DBG_VALUE: + llvm_unreachable("Should be handled target independently"); + } + // FIXME: Enable feature predicate checks once all the test pass. // AMDGPU_MC::verifyInstructionPredicates(MI->getOpcode(), // getSubtargetInfo().getFeatureBits()); @@ -341,7 +346,9 @@ void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) { const MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock::const_instr_iterator I = ++MI->getIterator(); while (I != MBB->instr_end() && I->isInsideBundle()) { - emitInstruction(&*I); + bool HandledByEmitDbgComment = I->isDebugInstr() && emitDebugComment(&*I); + if(!HandledByEmitDbgComment) + emitInstruction(&*I); ++I; } } else { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def index a6074eaf78fd0..a424c45b8af1f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def +++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def @@ -16,6 +16,8 @@ #ifndef MODULE_PASS #define MODULE_PASS(NAME, CREATE_PASS) #endif +MODULE_PASS("amdgpu-expand-feature-predicates", + AMDGPUExpandFeaturePredicatesPass(*this)) MODULE_PASS("amdgpu-always-inline", AMDGPUAlwaysInlinePass()) MODULE_PASS("amdgpu-export-kernel-runtime-handles", AMDGPUExportKernelRuntimeHandlesPass()) MODULE_PASS("amdgpu-lower-buffer-fat-pointers", @@ -30,6 +32,8 @@ MODULE_PASS("amdgpu-preload-kernel-arguments", AMDGPUPreloadKernelArgumentsPass( MODULE_PASS("amdgpu-printf-runtime-binding", AMDGPUPrintfRuntimeBindingPass()) MODULE_PASS("amdgpu-remove-incompatible-functions", AMDGPURemoveIncompatibleFunctionsPass(*this)) MODULE_PASS("amdgpu-sw-lower-lds", AMDGPUSwLowerLDSPass(*this)) +MODULE_PASS("amdgpu-expand-feature-predicates", + AMDGPUExpandFeaturePredicatesPass(*this)) MODULE_PASS("amdgpu-uniform-intrinsic-combine", AMDGPUUniformIntrinsicCombinePass()) #undef MODULE_PASS diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp index ddabd25894414..350a890834951 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp @@ -335,26 +335,22 @@ bool AMDGPUPromoteAllocaImpl::run(Function &F, bool PromoteToLDS) { bool Changed = false; for (AllocaInst *AI : Allocas) { const unsigned AllocaCost = DL->getTypeSizeInBits(AI->getAllocatedType()); - // First, check if we have enough budget to vectorize this alloca. - if (AllocaCost <= VectorizationBudget) { - // If we do, attempt vectorization, otherwise, fall through and try - // promoting to LDS instead. - if (tryPromoteAllocaToVector(*AI)) { - Changed = true; - assert((VectorizationBudget - AllocaCost) < VectorizationBudget && - "Underflow!"); - VectorizationBudget -= AllocaCost; - LLVM_DEBUG(dbgs() << " Remaining vectorization budget:" - << VectorizationBudget << "\n"); - continue; - } - } else { - LLVM_DEBUG(dbgs() << "Alloca too big for vectorization (size:" - << AllocaCost << ", budget:" << VectorizationBudget - << "): " << *AI << "\n"); + if (AllocaCost > VectorizationBudget) { + LLVM_DEBUG(dbgs() << " Alloca too big for vectorization: " << *AI + << "\n"); + return Changed; } - if (PromoteToLDS && tryPromoteAllocaToLDS(*AI, SufficientLDS)) + if (tryPromoteAllocaToVector(*AI)) { + Changed = true; + assert((VectorizationBudget - AllocaCost) < VectorizationBudget && + "Underflow!"); + VectorizationBudget -= AllocaCost; + LLVM_DEBUG(dbgs() << " Remaining vectorization budget:" + << VectorizationBudget << "\n"); + if (VectorizationBudget == 0) + break; + } else if (PromoteToLDS && tryPromoteAllocaToLDS(*AI, SufficientLDS)) Changed = true; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 54ba2f8c0d519..c1ee3a2ac6a89 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -5623,6 +5623,9 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case Intrinsic::amdgcn_flat_prefetch: case Intrinsic::amdgcn_global_prefetch: return getDefaultMappingVOP(MI); + case Intrinsic::amdgcn_global_load_b128: + case Intrinsic::amdgcn_global_store_b128: + return getDefaultMappingAllVGPR(MI); default: return getInvalidInstructionMapping(); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp b/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp index 94830ba998f27..7a2d02024647b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp @@ -10,7 +10,7 @@ /// This pass should be invoked at the end of wwm-regalloc pipeline. /// It identifies the WWM regs allocated during this pipeline and add /// them to the list of reserved registers so that they won't be available for -/// per-thread VGPR allocation in the subsequent regalloc pipeline. +/// regular VGPR allocation in the subsequent regalloc pipeline. // //===----------------------------------------------------------------------===// @@ -18,6 +18,7 @@ #include "AMDGPU.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "SIMachineFunctionInfo.h" +#include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/VirtRegMap.h" diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 6214f4db87e1e..9c9ae86b9cce8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -317,6 +317,7 @@ static VGPRRegisterRegAlloc greedyRegAllocVGPR( static VGPRRegisterRegAlloc fastRegAllocVGPR( "fast", "fast register allocator", createFastVGPRRegisterAllocator); + static WWMRegisterRegAlloc basicRegAllocWWMReg("basic", "basic register allocator", createBasicWWMRegisterAllocator); @@ -846,6 +847,16 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { #define GET_PASS_REGISTRY "AMDGPUPassRegistry.def" #include "llvm/Passes/TargetPassRegistry.inc" + PB.registerPipelineStartEPCallback( + [this](ModulePassManager &PM, OptimizationLevel Level) { + PM.addPass(AMDGPUExpandFeaturePredicatesPass(*this)); + }); + + PB.registerFullLinkTimeOptimizationEarlyEPCallback( + [this](ModulePassManager &PM, OptimizationLevel Level) { + PM.addPass(AMDGPUExpandFeaturePredicatesPass(*this)); + }); + PB.registerScalarOptimizerLateEPCallback( [](FunctionPassManager &FPM, OptimizationLevel Level) { if (Level == OptimizationLevel::O0) @@ -950,6 +961,13 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { PB.registerFullLinkTimeOptimizationLastEPCallback( [this](ModulePassManager &PM, OptimizationLevel Level) { + + // Promote kernel arguments to global address space for LLVM IR + // generated by flang compiler + FunctionPassManager FPM; + FPM.addPass(AMDGPUPromoteKernelArgumentsPass()); + PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM))); + // When we are using -fgpu-rdc, we can only run accelerator code // selection after linking to prevent, otherwise we end up removing // potentially reachable symbols that were exported as external in other @@ -963,6 +981,12 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { // module is partitioned for codegen. if (EnableSwLowerLDS) PM.addPass(AMDGPUSwLowerLDSPass(*this)); + + // Most likely, adding this pass here is incorrect. Commenting out on + // ATD for now until we resolve the issue upstream. See: + // https://github.com/llvm/llvm-project/issues/122891 for the issue and + // https://ontrack-internal.amd.com/browse/SWDEV-502923?focusedId=17904500&page=com.atlassian.jira.plugin.system.issuetabpanels%3Acomment-tabpanel#comment-17904500 + // for an explanation why this is likely wrong. if (EnableLowerModuleLDS) PM.addPass(AMDGPULowerModuleLDSPass(*this)); if (Level != OptimizationLevel::O0) { @@ -1018,6 +1042,14 @@ bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, AMDGPU::isFlatGlobalAddrSpace(DestAS); } +std::optional +AMDGPUTargetMachine::mapToDWARFAddrSpace(unsigned LLVMAddrSpace) const { + int AS = AMDGPU::mapToDWARFAddrSpace(LLVMAddrSpace); + if (AS == -1) + return std::nullopt; + return static_cast(AS); +} + unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const { if (auto *Arg = dyn_cast(V); Arg && @@ -1699,7 +1731,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() { addPass(&SILowerWWMCopiesLegacyID); addPass(&AMDGPUReserveWWMRegsLegacyID); - // For allocating per-thread VGPRs. + // For allocating regular VGPRs. addPass(createVGPRAllocPass(false)); return true; @@ -1736,7 +1768,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() { addPass(createVirtRegRewriter(false)); addPass(&AMDGPUReserveWWMRegsLegacyID); - // For allocating per-thread VGPRs. + // For allocating regular VGPRs. addPass(createVGPRAllocPass(true)); addPreRewrite(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h index 06a3047196b8a..1c71cd2290b1b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -60,6 +60,9 @@ class AMDGPUTargetMachine : public CodeGenTargetMachineImpl { bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; + std::optional + mapToDWARFAddrSpace(unsigned LLVMAddrSpace) const override; + unsigned getAssumedAddrSpace(const Value *V) const override; std::pair diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index 03d16fdd54c42..100c66f77c557 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -271,6 +271,8 @@ void AMDGPUTTIImpl::getUnrollingPreferences( if (L->isInnermost() && BB->size() < UnrollMaxBlockToAnalyze) UP.MaxIterationsCountToAnalyze = 32; } + + UP.AllowExpensiveTripCount = true; } void AMDGPUTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE, diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt index a1e0e5293c706..8c0f9d01a7d30 100644 --- a/llvm/lib/Target/AMDGPU/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt @@ -57,6 +57,7 @@ add_llvm_target(AMDGPUCodeGen AMDGPUCodeGenPrepare.cpp AMDGPUCombinerHelper.cpp AMDGPUCtorDtorLowering.cpp + AMDGPUExpandFeaturePredicates.cpp AMDGPUExportClustering.cpp AMDGPUExportKernelRuntimeHandles.cpp AMDGPUFrameLowering.cpp diff --git a/llvm/lib/Target/AMDGPU/Disassembler/CMakeLists.txt b/llvm/lib/Target/AMDGPU/Disassembler/CMakeLists.txt index aa96d67c527a4..56039821aca98 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/Disassembler/CMakeLists.txt @@ -2,6 +2,7 @@ include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/ add_llvm_component_library(LLVMAMDGPUDisassembler AMDGPUDisassembler.cpp + CodeObject.cpp LINK_COMPONENTS AMDGPUDesc @@ -10,6 +11,7 @@ add_llvm_component_library(LLVMAMDGPUDisassembler CodeGenTypes MC MCDisassembler + Object Support ADD_TO_COMPONENT diff --git a/llvm/lib/Target/AMDGPU/Disassembler/CodeObject.cpp b/llvm/lib/Target/AMDGPU/Disassembler/CodeObject.cpp new file mode 100644 index 0000000000000..22235a3560667 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/Disassembler/CodeObject.cpp @@ -0,0 +1,331 @@ +//===- CodeObject.cpp - ELF object file implementation ----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the HSA Code Object file class. +// +//===----------------------------------------------------------------------===// + +#include "CodeObject.h" +#include "AMDGPUPTNote.h" + +namespace llvm { + +using namespace object; + +const ELFNote* getNext(const ELFNote &N) { + return reinterpret_cast( + N.getDesc().data() + alignTo(N.descsz, ELFNote::ALIGN)); +} + +Expected KernelSym::getAmdKernelCodeT( + const HSACodeObject *CodeObject) const { + auto TextOr = CodeObject->getTextSection(); + if (!TextOr) { + return TextOr.takeError(); + } + + return getAmdKernelCodeT(CodeObject, *TextOr); +} + +Expected KernelSym::getAmdKernelCodeT( + const HSACodeObject * CodeObject, + const object::ELF64LEObjectFile::Elf_Shdr *Text) const { + assert(Text); + + auto ArrayOr = CodeObject->getELFFile().getSectionContentsAsArray(*Text); + if (!ArrayOr) + return ArrayOr.takeError(); + + auto SectionOffsetOr = getSectionOffset(CodeObject, Text); + if (!SectionOffsetOr) + return SectionOffsetOr.takeError(); + + return reinterpret_cast((*ArrayOr).data() + *SectionOffsetOr); +} + +Expected +FunctionSym::getAddress(const HSACodeObject *CodeObject) const { + auto TextOr = CodeObject->getTextSection(); + if (!TextOr) { + return TextOr.takeError(); + } + return getAddress(CodeObject, TextOr.get()); +} + +Expected +FunctionSym::getAddress(const HSACodeObject *CodeObject, + const object::ELF64LEObjectFile::Elf_Shdr *Text) const { + assert(Text); + auto ElfHeader = CodeObject->getELFFile().getHeader(); + if (ElfHeader.e_type == ELF::ET_REL) { + return st_value + Text->sh_addr; + } + + return st_value; +} + +Expected +FunctionSym::getSectionOffset(const HSACodeObject *CodeObject) const { + auto TextOr = CodeObject->getTextSection(); + if (!TextOr) { + return TextOr.takeError(); + } + return getSectionOffset(CodeObject, TextOr.get()); +} + +Expected FunctionSym::getSectionOffset( + const HSACodeObject *CodeObject, + const object::ELF64LEObjectFile::Elf_Shdr *Text) const { + assert(Text); + + auto AddressOr = getAddress(CodeObject, Text); + if (!AddressOr) + return AddressOr.takeError(); + + return *AddressOr - Text->sh_addr; +} + +Expected FunctionSym::getCodeOffset( + const HSACodeObject *CodeObject, + const object::ELF64LEObjectFile::Elf_Shdr *Text) const { + assert(Text); + + auto SectionOffsetOr = getSectionOffset(CodeObject, Text); + if (!SectionOffsetOr) + return SectionOffsetOr.takeError(); + + return *SectionOffsetOr; +} + +Expected KernelSym::getCodeOffset( + const HSACodeObject *CodeObject, + const object::ELF64LEObjectFile::Elf_Shdr *Text) const { + assert(Text); + + auto SectionOffsetOr = getSectionOffset(CodeObject, Text); + if (!SectionOffsetOr) + return SectionOffsetOr.takeError(); + + auto KernelCodeTOr = getAmdKernelCodeT(CodeObject, Text); + if (!KernelCodeTOr) + return KernelCodeTOr.takeError(); + + return *SectionOffsetOr + (*KernelCodeTOr)->kernel_code_entry_byte_offset; +} + +Expected +FunctionSym::asFunctionSym(Expected Sym) { + if (!Sym) + return Sym.takeError(); + + if ((*Sym)->getType() != ELF::STT_FUNC && + (*Sym)->getType() != ELF::STT_AMDGPU_HSA_KERNEL) + return createError("invalid symbol type"); + + return static_cast(*Sym); +} + +Expected KernelSym::asKernelSym(const FunctionSym *Sym) { + if (Sym->getType() != ELF::STT_AMDGPU_HSA_KERNEL) + return createError("invalid symbol type"); + + return static_cast(Sym); +} + +void HSACodeObject::InitMarkers() const { + auto TextSecOr = getTextSection(); + if (!TextSecOr) + return; + auto TextSec = TextSecOr.get(); + + FunctionMarkers.push_back(TextSec->sh_size); + + for (const auto &Sym : functions()) { + auto ExpectedFunction = + FunctionSym::asFunctionSym(getSymbol(Sym.getRawDataRefImpl())); + if (!ExpectedFunction) { + consumeError(ExpectedFunction.takeError()); + report_fatal_error("invalid function symbol"); + } + auto Function = ExpectedFunction.get(); + + auto ExpectedSectionOffset = Function->getSectionOffset(this, TextSec); + if (!ExpectedSectionOffset) { + consumeError(ExpectedSectionOffset.takeError()); + report_fatal_error("invalid section offset"); + } + FunctionMarkers.push_back(*ExpectedSectionOffset); + + auto ExpectedKernel = KernelSym::asKernelSym(Function); + if (ExpectedKernel) { + auto Kernel = ExpectedKernel.get(); + + auto ExpectedCodeOffset = Kernel->getCodeOffset(this, TextSec); + if (!ExpectedCodeOffset) { + consumeError(ExpectedCodeOffset.takeError()); + report_fatal_error("invalid kernel code offset"); + } + + FunctionMarkers.push_back(*ExpectedCodeOffset); + } else { + consumeError(ExpectedKernel.takeError()); + } + } + + array_pod_sort(FunctionMarkers.begin(), FunctionMarkers.end()); +} + +HSACodeObject::note_iterator HSACodeObject::notes_begin() const { + if (auto NotesOr = getNoteSection()) { + if (auto ContentsOr = getELFFile().getSectionContentsAsArray(**NotesOr)) + return const_varsize_item_iterator(*ContentsOr); + } + + return const_varsize_item_iterator(); +} + +HSACodeObject::note_iterator HSACodeObject::notes_end() const { + return const_varsize_item_iterator(); +} + +iterator_range HSACodeObject::notes() const { + return make_range(notes_begin(), notes_end()); +} + +function_sym_iterator HSACodeObject::functions_begin() const { + auto TextIdxOr = getTextSectionIdx(); + if (!TextIdxOr) + return functions_end(); + + auto TextIdx = TextIdxOr.get(); + return function_sym_iterator(symbol_begin(), symbol_end(), + [this, TextIdx](const SymbolRef &Sym) -> bool { + auto ExpectedFunction = + FunctionSym::asFunctionSym( + getSymbol(Sym.getRawDataRefImpl())); + if (!ExpectedFunction) { + consumeError(ExpectedFunction.takeError()); + return false; + } + auto Function = ExpectedFunction.get(); + if (Function->st_shndx != TextIdx) + return false; + return true; + }); +} + +function_sym_iterator HSACodeObject::functions_end() const { + return function_sym_iterator(symbol_end(), symbol_end(), + [](const SymbolRef &) { return true; }); +} + +iterator_range HSACodeObject::functions() const { + return make_range(functions_begin(), functions_end()); +} + +Expected> +HSACodeObject::getCode(const FunctionSym *Function) const { + auto TextOr = getTextSection(); + if (!TextOr) + return TextOr.takeError(); + + auto SecBytesOr = getELFFile().getSectionContentsAsArray(**TextOr); + if (!SecBytesOr) + return SecBytesOr.takeError(); + + auto CodeStartOr = Function->getCodeOffset(this, *TextOr); + if (!CodeStartOr) + return CodeStartOr.takeError(); + uint64_t CodeStart = CodeStartOr.get(); + + auto ExpectedKernel = KernelSym::asKernelSym(Function); + if (ExpectedKernel) { + auto Kernel = ExpectedKernel.get(); + auto KernelCodeStartOr = Kernel->getCodeOffset(this, *TextOr); + if (!KernelCodeStartOr) + return KernelCodeStartOr.takeError(); + CodeStart = KernelCodeStartOr.get(); + } else { + consumeError(ExpectedKernel.takeError()); + } + + auto CodeEndI = std::upper_bound(FunctionMarkers.begin(), + FunctionMarkers.end(), CodeStart); + uint64_t CodeEnd = CodeStart; + if (CodeEndI != FunctionMarkers.end()) + CodeEnd = *CodeEndI; + + return SecBytesOr->slice(CodeStart, CodeEnd - CodeStart); +} + +Expected +HSACodeObject::getSectionByName(StringRef Name) const { + auto ELF = getELFFile(); + auto SectionsOr = ELF.sections(); + if (!SectionsOr) + return SectionsOr.takeError(); + + for (const auto &Sec : *SectionsOr) { + auto SecNameOr = ELF.getSectionName(Sec); + if (!SecNameOr) { + return SecNameOr.takeError(); + } else if (*SecNameOr == Name) { + return Expected(&Sec); + } + } + return createError("invalid section index"); +} + +Expected HSACodeObject::getSectionIdxByName(StringRef Name) const { + auto ELF = getELFFile(); + uint32_t Idx = 0; + auto SectionsOr = ELF.sections(); + if (!SectionsOr) + return SectionsOr.takeError(); + + for (const auto &Sec : *SectionsOr) { + auto SecNameOr = ELF.getSectionName(Sec); + if (!SecNameOr) { + return SecNameOr.takeError(); + } else if (*SecNameOr == Name) { + return Idx; + } + ++Idx; + } + return createError("invalid section index"); +} + +Expected HSACodeObject::getTextSectionIdx() const { + if (auto IdxOr = getSectionIdxByName(".text")) { + auto SecOr = getELFFile().getSection(*IdxOr); + if (SecOr || isSectionText(toDRI(*SecOr))) + return IdxOr; + } + return createError("invalid section index"); +} + +Expected HSACodeObject::getNoteSectionIdx() const { + return getSectionIdxByName(AMDGPU::ElfNote::SectionName); +} + +Expected HSACodeObject::getTextSection() const { + if (auto IdxOr = getTextSectionIdx()) + return getELFFile().getSection(*IdxOr); + + return createError("invalid section index"); +} + +Expected HSACodeObject::getNoteSection() const { + if (auto IdxOr = getNoteSectionIdx()) + return getELFFile().getSection(*IdxOr); + + return createError("invalid section index"); +} + +} // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/Disassembler/CodeObject.h b/llvm/lib/Target/AMDGPU/Disassembler/CodeObject.h new file mode 100644 index 0000000000000..5c065cb39430f --- /dev/null +++ b/llvm/lib/Target/AMDGPU/Disassembler/CodeObject.h @@ -0,0 +1,278 @@ +//===- CodeObject.hpp - ELF object file implementation ----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the HSA Code Object file class. +// +//===----------------------------------------------------------------------===// + +#ifndef AMDGPU_DISASSEMBLER_HSA_CODE_OBJECT_HPP +#define AMDGPU_DISASSEMBLER_HSA_CODE_OBJECT_HPP + +#include "AMDKernelCodeT.h" +#include "llvm/ADT/iterator.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Support/Endian.h" + +namespace llvm { + +//===----------------------------------------------------------------------===// +// ELFNote +//===----------------------------------------------------------------------===// + +struct amdgpu_hsa_code_object_version { + support::ulittle32_t major_version; + support::ulittle32_t minor_version; +}; + + +struct amdgpu_hsa_isa { + support::ulittle16_t vendor_name_size; + support::ulittle16_t architecture_name_size; + support::ulittle32_t major; + support::ulittle32_t minor; + support::ulittle32_t stepping; + char names[1]; + + StringRef getVendorName() const { + return StringRef(names, vendor_name_size - 1); + } + + StringRef getArchitectureName() const { + return StringRef(names + vendor_name_size, architecture_name_size - 1); + } +}; + +struct ELFNote { + support::ulittle32_t namesz; + support::ulittle32_t descsz; + support::ulittle32_t type; + + enum {ALIGN = 4}; + + ELFNote() = delete; + ELFNote(const ELFNote&) = delete; + ELFNote& operator =(const ELFNote&) = delete; + + StringRef getName() const { + return StringRef(reinterpret_cast(this) + sizeof(*this), namesz); + } + + StringRef getDesc() const { + return StringRef(getName().data() + alignTo(namesz, ALIGN), descsz); + } + + size_t getSize() const { + return sizeof(*this) + alignTo(namesz, ALIGN) + alignTo(descsz, ALIGN); + } + + template Expected as() const { + if (descsz < sizeof(D)) { + return make_error("invalid descsz", + object::object_error::parse_failed); + } + + return reinterpret_cast(getDesc().data()); + } +}; + +const ELFNote* getNext(const ELFNote &N); + +template class const_varsize_item_iterator { + using iterator_catagory = std::forward_iterator_tag; + using value_type = const Item; + using difference_type = std::ptrdiff_t; + using pointer = const Item *; + using reference = const Item &; + + ArrayRef Ref; + + const Item *item() const { + return reinterpret_cast(Ref.data()); + } + + size_t getItemPadSize() const { + assert(Ref.size() >= sizeof(Item)); + return (const uint8_t*)getNext(*item()) - (const uint8_t*)item(); + } + +public: + const_varsize_item_iterator() {} + const_varsize_item_iterator(ArrayRef Ref_) : Ref(Ref_) {} + + bool valid() const { + return Ref.size() >= sizeof(Item) && Ref.size() >= getItemPadSize(); + } + + Expected operator*() const { + if (!valid()) { + return make_error("invalid item", + object::object_error::parse_failed); + } + + return *item(); + } + + bool operator==(const const_varsize_item_iterator &Other) const { + return (Ref.size() == Other.Ref.size()) && + (Ref.empty() || Ref.data() == Other.Ref.data()); + } + + bool operator!=(const const_varsize_item_iterator &Other) const { + return !(*this == Other); + } + + const_varsize_item_iterator &operator++() { // preincrement + Ref = Ref.size() >= sizeof(Item) ? + Ref.slice((std::min)(getItemPadSize(), Ref.size())) : + decltype(Ref)(); + return *this; + } +}; + +//===----------------------------------------------------------------------===// +// FunctionSym +//===----------------------------------------------------------------------===// + +class HSACodeObject; + +class FunctionSym : public object::ELF64LEObjectFile::Elf_Sym { +public: + Expected getAddress(const HSACodeObject *CodeObject) const; + + Expected getAddress( + const HSACodeObject *CodeObject, + const object::ELF64LEObjectFile::Elf_Shdr *Text) const; + + Expected getSectionOffset(const HSACodeObject *CodeObject) const; + + Expected getSectionOffset( + const HSACodeObject *CodeObject, + const object::ELF64LEObjectFile::Elf_Shdr *Text) const; + + Expected getCodeOffset( + const HSACodeObject *CodeObject, + const object::ELF64LEObjectFile::Elf_Shdr *Text) const; + + static Expected + asFunctionSym(Expected Sym); +}; + +class KernelSym : public FunctionSym { +public: + Expected + getCodeOffset(const HSACodeObject *CodeObject, + const object::ELF64LEObjectFile::Elf_Shdr *Text) const; + + Expected + getAmdKernelCodeT(const HSACodeObject *CodeObject) const; + + Expected + getAmdKernelCodeT(const HSACodeObject *CodeObject, + const object::ELF64LEObjectFile::Elf_Shdr *Text) const; + + static Expected asKernelSym(const FunctionSym *Sym); +}; + +template +class conditional_iterator : public iterator_adaptor_base< + conditional_iterator, + BaseIterator, + std::forward_iterator_tag> { + +public: + typedef std::function< + bool(const typename conditional_iterator::iterator_adaptor_base::value_type&) + > PredicateTy; + +protected: + BaseIterator End; + PredicateTy Predicate; + +public: + + conditional_iterator(BaseIterator BI, BaseIterator E, PredicateTy P) + : conditional_iterator::iterator_adaptor_base(BI), End(E), Predicate(P) { + while (this->I != End && !Predicate(*this->I)) { + ++this->I; + } + } + + conditional_iterator &operator++() { + do { + ++this->I; + } while (this->I != End && !Predicate(*this->I)); + return *this; + } +}; + +class function_sym_iterator + : public conditional_iterator { +public: + function_sym_iterator(object::elf_symbol_iterator It, + object::elf_symbol_iterator End, PredicateTy P) + : conditional_iterator(It, End, P) {} + + const object::ELFSymbolRef &operator*() const { + return *I; + } +}; + +//===----------------------------------------------------------------------===// +// HSACodeObject +//===----------------------------------------------------------------------===// + +class HSACodeObject : public object::ELF64LEObjectFile { +private: + mutable SmallVector FunctionMarkers; + + void InitMarkers() const; + + HSACodeObject(object::ELF64LEObjectFile &&Obj) + : object::ELF64LEObjectFile(std::move(Obj)) { + InitMarkers(); + } + +public: + static Expected> + create(MemoryBufferRef Wrapper) { + auto Obj = object::ELF64LEObjectFile::create(Wrapper); + if (auto E = Obj.takeError()) + return std::move(E); + std::unique_ptr Ret(new HSACodeObject(std::move(*Obj))); + return std::move(Ret); + } + + typedef const_varsize_item_iterator note_iterator; + + note_iterator notes_begin() const; + note_iterator notes_end() const; + iterator_range notes() const; + + function_sym_iterator functions_begin() const; + function_sym_iterator functions_end() const; + iterator_range functions() const; + + Expected> getCode(const FunctionSym *Function) const; + + Expected getSectionByName(StringRef Name) const; + + Expected getSectionIdxByName(StringRef) const; + Expected getTextSectionIdx() const; + Expected getNoteSectionIdx() const; + Expected getTextSection() const; + Expected getNoteSection() const; + + friend class FunctionSym; + friend class KernelSym; +}; + +} // namespace llvm + +#endif diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 8ea64d17417f7..21b339f2c6784 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -1824,6 +1824,72 @@ multiclass GlobalFLATStorePats : PatFrag< + (ops node:$ptr, node:$cpol), + (intrin $ptr, $cpol)>; + +def wrapped_global_load_b128_intrin : GlobalLoadIntrinWrapper; + +class FlatLoadIntrinSignedPat : GCNPat < + (vt (node (GlobalOffset (i64 VReg_64:$vaddr), i32:$offset), srcvalue)), + (inst $vaddr, $offset) +>; + +class FlatLoadIntrinSaddrPat : GCNPat < + (vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset, CPol:$cpol), srcvalue)), + (inst $saddr, $voffset, $offset, $cpol) +>; + +multiclass GlobalFLATLoadIntrinPats { + def : FlatLoadIntrinSignedPat { + let AddedComplexity = 10; + let SubtargetPredicate = inst.SubtargetPredicate; + let OtherPredicates = inst.OtherPredicates; + } + + def : FlatLoadIntrinSaddrPat(!cast(inst)#"_SADDR"), node, vt> { + let AddedComplexity = 11; + let SubtargetPredicate = inst.SubtargetPredicate; + let OtherPredicates = inst.OtherPredicates; + } +} + +class GlobalStoreIntrinWrapper : PatFrag< + (ops node:$data, node:$ptr, node:$scope), + (intrin $ptr, $data, $scope)>; + +def wrapped_global_store_b128_intrin : GlobalStoreIntrinWrapper; + +class FlatStoreIntrinSignedPat : GCNPat < + (node vt:$data, (GlobalOffset i64:$vaddr, i32:$offset), srcvalue), + (inst $vaddr, getVregSrcForVT.ret:$data, $offset) +>; + +class FlatStoreIntrinSaddrPat : GCNPat < + (node vt:$data, (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset, CPol:$cpol), srcvalue), + (inst $voffset, getVregSrcForVT.ret:$data, $saddr, $offset, $cpol) +>; + +multiclass GlobalFLATStoreIntrinPats { + def : FlatStoreIntrinSignedPat { + let SubtargetPredicate = inst.SubtargetPredicate; + let OtherPredicates = inst.OtherPredicates; + let AddedComplexity = 10; + } + + def : FlatStoreIntrinSaddrPat(!cast(inst)#"_SADDR"), node, vt> { + let SubtargetPredicate = inst.SubtargetPredicate; + let OtherPredicates = inst.OtherPredicates; + let AddedComplexity = 11; + } +} + +let SubtargetPredicate = isGFX940Plus in { +defm : GlobalFLATLoadIntrinPats ; +defm : GlobalFLATStoreIntrinPats ; +} + multiclass GlobalFLATStorePats_D16_t16 { def : FlatStoreSignedPat(inst#"_t16"), node, vt> { let AddedComplexity = 10; diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp index fa0c95f54d9e7..02bcbd076e600 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp @@ -55,6 +55,7 @@ AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT, SupportsDebugInformation = true; UsesCFIWithoutEH = true; DwarfRegNumForCFI = true; + SupportsHeterogeneousDebuggingExtensions = true; UseIntegratedAssembler = false; initializeAtSpecifiers(atSpecifiers); diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index 6616b30410590..bdc32594c13a3 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -23,6 +23,11 @@ #define DEBUG_TYPE "si-fold-operands" using namespace llvm; +static cl::opt SIFoldOperandsPreheaderThreshold( + "amdgpu-si-fold-operands-preheader-threshold", cl::init(1000), + cl::desc("Threshold for operand folding hazard check. " + "Defaults to 1000 MIs, upper limit 10000.")); + namespace { /// Track a value we may want to fold into downstream users, applying @@ -1125,8 +1130,7 @@ bool SIFoldOperandsImpl::tryToFoldACImm( if (UseOpIdx >= Desc.getNumOperands()) return false; - // Filter out unhandled pseudos. - if (!AMDGPU::isSISrcOperand(Desc, UseOpIdx)) + if (!AMDGPU::isSISrcInlinableOperand(Desc, UseOpIdx)) return false; MachineOperand &UseOp = UseMI->getOperand(UseOpIdx); @@ -1454,9 +1458,9 @@ void SIFoldOperandsImpl::foldOperand( } if (OpToFold.isReg() && TRI->isSGPRReg(*MRI, OpToFold.getReg())) { - if (execMayBeModifiedBeforeUse(*MRI, - UseMI->getOperand(UseOpIdx).getReg(), - *OpToFold.DefMI, *UseMI)) + if (checkIfExecMayBeModifiedBeforeUseAcrossBB( + *MRI, UseMI->getOperand(UseOpIdx).getReg(), + *OpToFold.DefMI, *UseMI, SIFoldOperandsPreheaderThreshold)) return; // %vgpr = COPY %sgpr0 diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 5c39f7a3d6daa..f584b6a147fda 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -12,9 +12,12 @@ #include "GCNSubtarget.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "SIMachineFunctionInfo.h" +#include "llvm/BinaryFormat/Dwarf.h" #include "llvm/CodeGen/LiveRegUnits.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" +#include "llvm/Support/LEB128.h" #include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -27,6 +30,9 @@ static cl::opt EnableSpillVGPRToAGPR( cl::ReallyHidden, cl::init(true)); +static constexpr unsigned SGPRBitSize = 32; +static constexpr unsigned VGPRLaneBitSize = 32; + // Find a register matching \p RC from \p LiveUnits which is unused and // available throughout the function. On failure, returns AMDGPU::NoRegister. // TODO: Rewrite the loop here to iterate over MCRegUnits instead of @@ -43,6 +49,79 @@ static MCRegister findUnusedRegister(MachineRegisterInfo &MRI, return MCRegister(); } +static bool needsFrameMoves(const MachineFunction &MF) { + // FIXME: There are some places in the compiler which are sensitive to the CFI + // pseudos and so using MachineFunction::needsFrameMoves has the unintended + // effect of making enabling debug info affect codegen. Once we have + // identified and fixed those cases this should be replaced with + // MF.needsFrameMoves() + return true; +} + +static void encodeDwarfRegisterLocation(int DwarfReg, raw_ostream &OS) { + assert(DwarfReg >= 0); + if (DwarfReg < 32) { + OS << uint8_t(dwarf::DW_OP_reg0 + DwarfReg); + } else { + OS << uint8_t(dwarf::DW_OP_regx); + encodeULEB128(DwarfReg, OS); + } +} + +static MCCFIInstruction +createScaledCFAInPrivateWave(const GCNSubtarget &ST, + MCRegister DwarfStackPtrReg) { + assert(ST.enableFlatScratch()); + + // When flat scratch is used, the cfa is expressed in terms of private_lane + // (address space 5), but the debugger only accepts addresses in terms of + // private_wave (6). Override the cfa value using the expression + // (wave_size*cfa_reg), which is equivalent to (cfa_reg << wave_size_log2) + const unsigned WavefrontSizeLog2 = ST.getWavefrontSizeLog2(); + assert(WavefrontSizeLog2 < 32); + + SmallString<20> Block; + raw_svector_ostream OSBlock(Block); + encodeDwarfRegisterLocation(DwarfStackPtrReg, OSBlock); + OSBlock << uint8_t(dwarf::DW_OP_deref_size) << uint8_t(4) + << uint8_t(dwarf::DW_OP_lit0 + WavefrontSizeLog2) + << uint8_t(dwarf::DW_OP_shl) + << uint8_t(dwarf::DW_OP_lit0 + + dwarf::DW_ASPACE_LLVM_AMDGPU_private_wave); + OSBlock << uint8_t(dwarf::DW_OP_LLVM_user) + << uint8_t(dwarf::DW_OP_LLVM_form_aspace_address); + + SmallString<20> CFIInst; + raw_svector_ostream OSCFIInst(CFIInst); + OSCFIInst << uint8_t(dwarf::DW_CFA_def_cfa_expression); + encodeULEB128(Block.size(), OSCFIInst); + OSCFIInst << Block; + + return MCCFIInstruction::createEscape(nullptr, OSCFIInst.str()); +} + +void SIFrameLowering::emitDefCFA(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + DebugLoc const &DL, Register StackPtrReg, + bool AspaceAlreadyDefined, + MachineInstr::MIFlag Flags) const { + MachineFunction &MF = *MBB.getParent(); + const GCNSubtarget &ST = MF.getSubtarget(); + const MCRegisterInfo *MCRI = MF.getContext().getRegisterInfo(); + + MCRegister DwarfStackPtrReg = MCRI->getDwarfRegNum(StackPtrReg, false); + MCCFIInstruction CFIInst = + ST.enableFlatScratch() + ? createScaledCFAInPrivateWave(ST, DwarfStackPtrReg) + : (AspaceAlreadyDefined + ? MCCFIInstruction::createLLVMDefAspaceCfa( + nullptr, DwarfStackPtrReg, 0, + dwarf::DW_ASPACE_LLVM_AMDGPU_private_wave, SMLoc()) + : MCCFIInstruction::createDefCfaRegister(nullptr, + DwarfStackPtrReg)); + buildCFI(MBB, MBBI, DL, CFIInst, Flags); +} + // Find a scratch register that we can use in the prologue. We avoid using // callee-save registers since they may appear to be free when this is called // from canUseAsPrologue (during shrink wrapping), but then no longer be free @@ -231,6 +310,8 @@ class PrologEpilogSGPRSpillBuilder { SIMachineFunctionInfo *FuncInfo; const SIInstrInfo *TII; const SIRegisterInfo &TRI; + const MCRegisterInfo *MCRI; + const SIFrameLowering *TFI; Register SuperReg; const PrologEpilogSGPRSaveRestoreInfo SI; LiveRegUnits &LiveUnits; @@ -239,9 +320,16 @@ class PrologEpilogSGPRSpillBuilder { ArrayRef SplitParts; unsigned NumSubRegs; unsigned EltSize = 4; + bool IsFramePtrPrologSpill; + bool NeedsFrameMoves; + + bool isExec(Register Reg) const { + return Reg == AMDGPU::EXEC_LO || Reg == AMDGPU::EXEC; + } void saveToMemory(const int FI) const { MachineRegisterInfo &MRI = MF.getRegInfo(); + const GCNSubtarget &ST = MF.getSubtarget(); assert(!MFI.isDeadObjectIndex(FI)); initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MI, /*IsProlog*/ true); @@ -260,6 +348,20 @@ class PrologEpilogSGPRSpillBuilder { buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL, TmpVGPR, FI, FrameReg, DwordOff); + if (NeedsFrameMoves) { + if (isExec(SuperReg) && (I == NumSubRegs - 1)) + SubReg = AMDGPU::EXEC; + else if (IsFramePtrPrologSpill) + SubReg = FuncInfo->getFrameOffsetReg(); + + // FIXME: CFI for EXEC needs a fix by accurately computing the spill + // offset for both the low and high components. + if (SubReg != AMDGPU::EXEC_LO) + TFI->buildCFI(MBB, MI, DL, + MCCFIInstruction::createOffset( + nullptr, MCRI->getDwarfRegNum(SubReg, false), + MFI.getObjectOffset(FI) * ST.getWavefrontSize())); + } DwordOff += 4; } } @@ -281,6 +383,19 @@ class PrologEpilogSGPRSpillBuilder { .addReg(SubReg) .addImm(Spill[I].Lane) .addReg(Spill[I].VGPR, RegState::Undef); + if (NeedsFrameMoves) { + if (isExec(SuperReg)) { + if (I == NumSubRegs - 1) + TFI->buildCFIForSGPRToVGPRSpill(MBB, MI, DL, AMDGPU::EXEC, Spill); + } else if (IsFramePtrPrologSpill) { + TFI->buildCFIForSGPRToVGPRSpill(MBB, MI, DL, + FuncInfo->getFrameOffsetReg(), + Spill[I].VGPR, Spill[I].Lane); + } else { + TFI->buildCFIForSGPRToVGPRSpill(MBB, MI, DL, SubReg, Spill[I].VGPR, + Spill[I].Lane); + } + } } } @@ -288,10 +403,35 @@ class PrologEpilogSGPRSpillBuilder { BuildMI(MBB, MI, DL, TII->get(AMDGPU::COPY), DstReg) .addReg(SuperReg) .setMIFlag(MachineInstr::FrameSetup); + if (NeedsFrameMoves) { + const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(DstReg); + ArrayRef DstSplitParts = TRI.getRegSplitParts(RC, EltSize); + unsigned DstNumSubRegs = DstSplitParts.empty() ? 1 : DstSplitParts.size(); + assert(NumSubRegs == DstNumSubRegs); + for (unsigned I = 0; I < NumSubRegs; ++I) { + Register SrcSubReg = + NumSubRegs == 1 ? SuperReg + : Register(TRI.getSubReg(SuperReg, SplitParts[I])); + Register DstSubReg = + NumSubRegs == 1 ? DstReg + : Register(TRI.getSubReg(DstReg, DstSplitParts[I])); + if (isExec(SuperReg)) { + if (I == NumSubRegs - 1) + TFI->buildCFIForRegToSGPRPairSpill(MBB, MI, DL, AMDGPU::EXEC, + DstReg); + } else { + TFI->buildCFI(MBB, MI, DL, + MCCFIInstruction::createRegister( + nullptr, MCRI->getDwarfRegNum(SrcSubReg, false), + MCRI->getDwarfRegNum(DstSubReg, false))); + } + } + } } void restoreFromMemory(const int FI) { MachineRegisterInfo &MRI = MF.getRegInfo(); + const GCNSubtarget &ST = MF.getSubtarget(); initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MI, /*IsProlog*/ false); MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( @@ -343,16 +483,21 @@ class PrologEpilogSGPRSpillBuilder { MachineBasicBlock::iterator MI, const DebugLoc &DL, const SIInstrInfo *TII, const SIRegisterInfo &TRI, - LiveRegUnits &LiveUnits, Register FrameReg) + LiveRegUnits &LiveUnits, Register FrameReg, + bool IsFramePtrPrologSpill = false) : MI(MI), MBB(MBB), MF(*MBB.getParent()), ST(MF.getSubtarget()), MFI(MF.getFrameInfo()), FuncInfo(MF.getInfo()), TII(TII), TRI(TRI), - SuperReg(Reg), SI(SI), LiveUnits(LiveUnits), DL(DL), - FrameReg(FrameReg) { + MCRI(MF.getContext().getRegisterInfo()), + TFI(ST.getFrameLowering()), SuperReg(Reg), SI(SI), LiveUnits(LiveUnits), + DL(DL), FrameReg(FrameReg), + IsFramePtrPrologSpill(IsFramePtrPrologSpill) { const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); SplitParts = TRI.getRegSplitParts(RC, EltSize); NumSubRegs = SplitParts.empty() ? 1 : SplitParts.size(); + NeedsFrameMoves = needsFrameMoves(MF); + assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); } @@ -525,12 +670,21 @@ void SIFrameLowering::emitEntryFunctionFlatScratchInit( } // Note SGPRSpill stack IDs should only be used for SGPR spilling to VGPRs, not -// memory. They should have been removed by now. -static bool allStackObjectsAreDead(const MachineFrameInfo &MFI) { +// memory. They should have been removed by now, except CFI Saved Reg spills. +static bool allStackObjectsAreDead(const MachineFunction &MF) { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const SIMachineFunctionInfo *FuncInfo = MF.getInfo(); for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd(); I != E; ++I) { - if (!MFI.isDeadObjectIndex(I)) + if (!MFI.isDeadObjectIndex(I)) { + // determineCalleeSaves() might have added the SGPRSpill stack IDs for + // CFI saves into scratch VGPR, ignore them + if (MFI.getStackID(I) == TargetStackID::SGPRSpill && + FuncInfo->checkIndexInPrologEpilogSGPRSpills(I)) { + continue; + } return false; + } } return true; @@ -550,8 +704,8 @@ Register SIFrameLowering::getEntryFunctionReservedScratchRsrcReg( Register ScratchRsrcReg = MFI->getScratchRSrcReg(); - if (!ScratchRsrcReg || (!MRI.isPhysRegUsed(ScratchRsrcReg) && - allStackObjectsAreDead(MF.getFrameInfo()))) + if (!ScratchRsrcReg || + (!MRI.isPhysRegUsed(ScratchRsrcReg) && allStackObjectsAreDead(MF))) return Register(); if (ST.hasSGPRInitBug() || @@ -615,10 +769,39 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF, const SIRegisterInfo *TRI = &TII->getRegisterInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); const Function &F = MF.getFunction(); + const MCRegisterInfo *MCRI = MF.getContext().getRegisterInfo(); MachineFrameInfo &FrameInfo = MF.getFrameInfo(); assert(MFI->isEntryFunction()); + // Debug location must be unknown since the first debug location is used to + // determine the end of the prologue. + DebugLoc DL; + MachineBasicBlock::iterator I = MBB.begin(); + + const bool NeedsFrameMoves = needsFrameMoves(MF); + + if (NeedsFrameMoves) { + // On entry the SP/FP are not set up, so we need to define the CFA in terms + // of a literal location expression. + static const char CFAEncodedInstUserOpsArr[] = { + dwarf::DW_CFA_def_cfa_expression, + 4, // length + static_cast(dwarf::DW_OP_lit0), + static_cast(dwarf::DW_OP_lit0 + + dwarf::DW_ASPACE_LLVM_AMDGPU_private_wave), + static_cast(dwarf::DW_OP_LLVM_user), + static_cast(dwarf::DW_OP_LLVM_form_aspace_address)}; + static StringRef CFAEncodedInstUserOps = + StringRef(CFAEncodedInstUserOpsArr, sizeof(CFAEncodedInstUserOpsArr)); + buildCFI(MBB, I, DL, + MCCFIInstruction::createEscape(nullptr, CFAEncodedInstUserOps)); + // Unwinding halts when the return address (PC) is undefined. + buildCFI(MBB, I, DL, + MCCFIInstruction::createUndefined( + nullptr, MCRI->getDwarfRegNum(AMDGPU::PC_REG, false))); + } + Register PreloadedScratchWaveOffsetReg = MFI->getPreloadedReg( AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET); @@ -655,11 +838,6 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF, } } - // Debug location must be unknown since the first debug location is used to - // determine the end of the prologue. - DebugLoc DL; - MachineBasicBlock::iterator I = MBB.begin(); - // We found the SRSRC first because it needs four registers and has an // alignment requirement. If the SRSRC that we found is clobbering with // the scratch wave offset, which may be in a fixed SGPR or a free SGPR @@ -755,7 +933,7 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF, bool NeedsFlatScratchInit = MFI->getUserSGPRInfo().hasFlatScratchInit() && (MRI.isPhysRegUsed(AMDGPU::FLAT_SCR) || FrameInfo.hasCalls() || - (!allStackObjectsAreDead(FrameInfo) && ST.enableFlatScratch())); + (!allStackObjectsAreDead(MF) && ST.enableFlatScratch())); if ((NeedsFlatScratchInit || ScratchRsrcReg) && PreloadedScratchWaveOffsetReg && !ST.flatScratchIsArchitected()) { @@ -932,6 +1110,48 @@ bool SIFrameLowering::isSupportedStackID(TargetStackID::Value ID) const { llvm_unreachable("Invalid TargetStackID::Value"); } +void SIFrameLowering::emitPrologueEntryCFI(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL) const { + const MachineFunction &MF = *MBB.getParent(); + const MachineRegisterInfo &MRI = MF.getRegInfo(); + const MCRegisterInfo *MCRI = MF.getContext().getRegisterInfo(); + const GCNSubtarget &ST = MF.getSubtarget(); + const SIRegisterInfo &TRI = ST.getInstrInfo()->getRegisterInfo(); + Register StackPtrReg = + MF.getInfo()->getStackPtrOffsetReg(); + + emitDefCFA(MBB, MBBI, DL, StackPtrReg, /*AspaceAlreadyDefined=*/true, + MachineInstr::FrameSetup); + + buildCFIForRegToSGPRPairSpill(MBB, MBBI, DL, AMDGPU::PC_REG, + TRI.getReturnAddressReg(MF)); + + BitVector IsCalleeSaved(TRI.getNumRegs()); + const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs(); + for (unsigned I = 0; CSRegs[I]; ++I) { + IsCalleeSaved.set(CSRegs[I]); + } + auto ProcessReg = [&](MCPhysReg Reg) { + if (IsCalleeSaved.test(Reg) || !MRI.isPhysRegModified(Reg)) + return; + MCRegister DwarfReg = MCRI->getDwarfRegNum(Reg, false); + buildCFI(MBB, MBBI, DL, + MCCFIInstruction::createUndefined(nullptr, DwarfReg)); + }; + + // Emit CFI rules for caller saved Arch VGPRs which are clobbered + for_each(AMDGPU::VGPR_32RegClass.getRegisters(), ProcessReg); + + // Emit CFI rules for caller saved Accum VGPRs which are clobbered + if (ST.hasMAIInsts()) { + for_each(AMDGPU::AGPR_32RegClass.getRegisters(), ProcessReg); + } + + // Emit CFI rules for caller saved SGPRs which are clobbered + for_each(AMDGPU::SGPR_32RegClass.getRegisters(), ProcessReg); +} + // Activate only the inactive lanes when \p EnableInactiveLanes is true. // Otherwise, activate all lanes. It returns the saved exec. static Register buildScratchExecCopy(LiveRegUnits &LiveUnits, @@ -978,14 +1198,19 @@ static Register buildScratchExecCopy(LiveRegUnits &LiveUnits, return ScratchExecCopy; } -void SIFrameLowering::emitCSRSpillStores( - MachineFunction &MF, MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, DebugLoc &DL, LiveRegUnits &LiveUnits, - Register FrameReg, Register FramePtrRegScratchCopy) const { +void SIFrameLowering::emitCSRSpillStores(MachineFunction &MF, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + DebugLoc &DL, LiveRegUnits &LiveUnits, + Register FrameReg, + Register FramePtrRegScratchCopy, + const bool NeedsFrameMoves) const { SIMachineFunctionInfo *FuncInfo = MF.getInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); const GCNSubtarget &ST = MF.getSubtarget(); const SIInstrInfo *TII = ST.getInstrInfo(); const SIRegisterInfo &TRI = TII->getRegisterInfo(); + const MCRegisterInfo *MCRI = MF.getContext().getRegisterInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); const AMDGPU::LaneMaskConstants &LMC = AMDGPU::LaneMaskConstants::get(ST); @@ -1007,6 +1232,12 @@ void SIFrameLowering::emitCSRSpillStores( int FI = Reg.second; buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MBBI, DL, VGPR, FI, FrameReg); + if (NeedsFrameMoves) + // We spill the entire VGPR, so we can get away with just cfi_offset + buildCFI(MBB, MBBI, DL, + MCCFIInstruction::createOffset( + nullptr, MCRI->getDwarfRegNum(VGPR, false), + MFI.getObjectOffset(FI) * ST.getWavefrontSize())); } }; @@ -1055,13 +1286,13 @@ void SIFrameLowering::emitCSRSpillStores( // Skip if FP is saved to a scratch SGPR, the save has already been emitted. // Otherwise, FP has been moved to a temporary register and spill it // instead. - Register Reg = - Spill.first == FramePtrReg ? FramePtrRegScratchCopy : Spill.first; + bool IsFramePtrPrologSpill = Spill.first == FramePtrReg ? true : false; + Register Reg = IsFramePtrPrologSpill ? FramePtrRegScratchCopy : Spill.first; if (!Reg) continue; PrologEpilogSGPRSpillBuilder SB(Reg, Spill.second, MBB, MBBI, DL, TII, TRI, - LiveUnits, FrameReg); + LiveUnits, FrameReg, IsFramePtrPrologSpill); SB.save(); } @@ -1081,6 +1312,11 @@ void SIFrameLowering::emitCSRSpillStores( LiveUnits.addReg(Reg); } } + + // Remove the spill entry created for EXEC. It is needed only for CFISaves in + // the prologue. + if (TRI.isCFISavedRegsSpillEnabled()) + FuncInfo->removePrologEpilogSGPRSpillEntry(TRI.getExec()); } void SIFrameLowering::emitCSRSpillRestores( @@ -1229,6 +1465,11 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF, uint32_t NumBytes = MFI.getStackSize(); uint32_t RoundedSize = NumBytes; + const bool NeedsFrameMoves = needsFrameMoves(MF); + + if (NeedsFrameMoves) + emitPrologueEntryCFI(MBB, MBBI, DL); + if (TRI.hasStackRealignment(MF)) HasFP = true; @@ -1237,7 +1478,7 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF, // Emit the CSR spill stores with SP base register. emitCSRSpillStores(MF, MBB, MBBI, DL, LiveUnits, FuncInfo->isChainFunction() ? Register() : StackPtrReg, - FramePtrRegScratchCopy); + FramePtrRegScratchCopy, NeedsFrameMoves); } else { // CSR spill stores will use FP as base register. Register SGPRForFPSaveRestoreCopy = @@ -1251,7 +1492,8 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF, PrologEpilogSGPRSpillBuilder SB( FramePtrReg, FuncInfo->getPrologEpilogSGPRSaveRestoreInfo(FramePtrReg), MBB, MBBI, - DL, TII, TRI, LiveUnits, FramePtrReg); + DL, TII, TRI, LiveUnits, FramePtrReg, + /*IsFramePtrPrologSpill*/ true); SB.save(); LiveUnits.addReg(SGPRForFPSaveRestoreCopy); } else { @@ -1298,7 +1540,7 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF, // If FP is used, emit the CSR spills with FP base register. if (HasFP) { emitCSRSpillStores(MF, MBB, MBBI, DL, LiveUnits, FramePtrReg, - FramePtrRegScratchCopy); + FramePtrRegScratchCopy, NeedsFrameMoves); if (FramePtrRegScratchCopy) LiveUnits.removeReg(FramePtrRegScratchCopy); } @@ -1313,6 +1555,12 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF, .setMIFlag(MachineInstr::FrameSetup); } + if (HasFP) { + if (NeedsFrameMoves) + emitDefCFA(MBB, MBBI, DL, FramePtrReg, /*AspaceAlreadyDefined=*/false, + MachineInstr::FrameSetup); + } + if (HasFP && RoundedSize != 0) { auto Add = BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_I32), StackPtrReg) .addReg(StackPtrReg) @@ -1375,17 +1623,15 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF, const Register StackPtrReg = FuncInfo->getStackPtrOffsetReg(); Register FramePtrReg = FuncInfo->getFrameOffsetReg(); bool FPSaved = FuncInfo->hasPrologEpilogSGPRSpillEntry(FramePtrReg); - if (RoundedSize != 0) { - if (TRI.hasBasePointer(MF)) { + if (TRI.hasBasePointer(MF)) BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), StackPtrReg) .addReg(TRI.getBaseRegister()) .setMIFlag(MachineInstr::FrameDestroy); - } else if (hasFP(MF)) { + else if (hasFP(MF)) BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), StackPtrReg) .addReg(FramePtrReg) .setMIFlag(MachineInstr::FrameDestroy); - } } Register FramePtrRegScratchCopy; @@ -1412,6 +1658,13 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF, FramePtrRegScratchCopy); } + const bool NeedsFrameMoves = needsFrameMoves(MF); + if (hasFP(MF)) { + if (NeedsFrameMoves) + emitDefCFA(MBB, MBBI, DL, StackPtrReg, /*AspaceAlreadyDefined=*/false, + MachineInstr::FrameDestroy); + } + if (FPSaved) { // Insert the copy to restore FP. Register SrcReg = SGPRForFPSaveRestoreCopy ? SGPRForFPSaveRestoreCopy @@ -1545,14 +1798,14 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized( // can. Any remaining SGPR spills will go to memory, so move them back to the // default stack. bool HaveSGPRToVMemSpill = - FuncInfo->removeDeadFrameIndices(MFI, /*ResetSGPRSpillStackIDs*/ true); + FuncInfo->removeDeadFrameIndices(MF, /*ResetSGPRSpillStackIDs*/ true); assert(allSGPRSpillsAreDead(MF) && "SGPR spill should have been removed in SILowerSGPRSpills"); // FIXME: The other checks should be redundant with allStackObjectsAreDead, // but currently hasNonSpillStackObjects is set only from source // allocas. Stack temps produced from legalization are not counted currently. - if (!allStackObjectsAreDead(MFI)) { + if (!allStackObjectsAreDead(MF)) { assert(RS && "RegScavenger required if spilling"); // Add an emergency spill slot @@ -1652,6 +1905,18 @@ void SIFrameLowering::determinePrologEpilogSGPRSaves( MFI->setSGPRForEXECCopy(AMDGPU::NoRegister); } + if (TRI->isCFISavedRegsSpillEnabled()) { + Register Exec = TRI->getExec(); + assert(!MFI->hasPrologEpilogSGPRSpillEntry(Exec) && + "Re-reserving spill slot for EXEC"); + // FIXME: Machine Copy Propagation currently optimizes away the EXEC copy to + // the scratch as we emit it only in the prolog. This optimization should + // not happen for frame related instructions. Until this is fixed ignore + // copy to scratch SGPR. + getVGPRSpillLaneOrTempRegister(MF, LiveUnits, Exec, RC, + /*IncludeScratchCopy=*/false); + } + // hasFP only knows about stack objects that already exist. We're now // determining the stack slots that will be created, so we have to predict // them. Stack objects force FP usage with calls. @@ -1661,8 +1926,7 @@ void SIFrameLowering::determinePrologEpilogSGPRSaves( // // FIXME: Is this really hasReservedCallFrame? const bool WillHaveFP = - FrameInfo.hasCalls() && - (SavedVGPRs.any() || !allStackObjectsAreDead(FrameInfo)); + FrameInfo.hasCalls() && (SavedVGPRs.any() || !allStackObjectsAreDead(MF)); if (WillHaveFP || hasFP(MF)) { Register FramePtrReg = MFI->getFrameOffsetReg(); @@ -2000,17 +2264,49 @@ bool SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP( return true; } +static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB, + const TargetRegisterInfo *TRI) { + for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) { + if (MBB.isLiveIn(*R)) { + return true; + } + } + return false; +} + bool SIFrameLowering::spillCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef CSI, const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); const GCNSubtarget &ST = MF->getSubtarget(); - if (!ST.useVGPRBlockOpsForCSR()) - return false; + const SIInstrInfo *TII = ST.getInstrInfo(); + const SIRegisterInfo *SITRI = static_cast(TRI); + + if (!ST.useVGPRBlockOpsForCSR()) { + for (const CalleeSavedInfo &CS : CSI) { + // Insert the spill to the stack frame. + unsigned Reg = CS.getReg(); + + if (CS.isSpilledToReg()) { + BuildMI(MBB, MI, DebugLoc(), TII->get(TargetOpcode::COPY), + CS.getDstReg()) + .addReg(Reg, getKillRegState(true)); + } else { + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( + Reg, Reg == SITRI->getReturnAddressReg(*MF) ? MVT::i64 : MVT::i32); + // If this value was already livein, we probably have a direct use of + // the incoming register value, so don't kill at the spill point. This + // happens since we pass some special inputs (workgroup IDs) in the + // callee saved range. + const bool IsLiveIn = isLiveIntoMBB(Reg, MBB, TRI); + TII->storeRegToStackSlotCFI(MBB, MI, Reg, !IsLiveIn, CS.getFrameIdx(), + RC, TRI); + } + } + return true; + } MachineFrameInfo &FrameInfo = MF->getFrameInfo(); - SIMachineFunctionInfo *MFI = MF->getInfo(); - const SIInstrInfo *TII = ST.getInstrInfo(); SIMachineFunctionInfo *FuncInfo = MF->getInfo(); const TargetRegisterClass *BlockRegClass = @@ -2034,10 +2330,10 @@ bool SIFrameLowering::spillCalleeSavedRegisters( FrameInfo.getObjectAlign(FrameIndex)); BuildMI(MBB, MI, MI->getDebugLoc(), - TII->get(AMDGPU::SI_BLOCK_SPILL_V1024_SAVE)) + TII->get(AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE)) .addReg(Reg, getKillRegState(false)) .addFrameIndex(FrameIndex) - .addReg(MFI->getStackPtrOffsetReg()) + .addReg(FuncInfo->getStackPtrOffsetReg()) .addImm(0) .addImm(Mask) .addMemOperand(MMO); @@ -2210,3 +2506,139 @@ bool SIFrameLowering::requiresStackPointerReference( // references the SP, like variable sized stack objects. return frameTriviallyRequiresSP(MFI); } + +MachineInstr *SIFrameLowering::buildCFI(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, + const MCCFIInstruction &CFIInst, + MachineInstr::MIFlag flag) const { + MachineFunction &MF = *MBB.getParent(); + const SIInstrInfo *TII = MF.getSubtarget().getInstrInfo(); + return BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(MF.addFrameInst(CFIInst)) + .setMIFlag(flag); +} + +MachineInstr *SIFrameLowering::buildCFIForVRegToVRegSpill( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, const Register Reg, const Register RegCopy) const { + MachineFunction &MF = *MBB.getParent(); + const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo(); + const GCNSubtarget &ST = MF.getSubtarget(); + + unsigned MaskReg = MCRI.getDwarfRegNum( + ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC, false); + auto CFIInst = MCCFIInstruction::createLLVMVectorRegisterMask( + nullptr, MCRI.getDwarfRegNum(Reg, false), + MCRI.getDwarfRegNum(RegCopy, false), VGPRLaneBitSize, MaskReg, + ST.getWavefrontSize()); + return buildCFI(MBB, MBBI, DL, std::move(CFIInst)); +} + +MachineInstr *SIFrameLowering::buildCFIForSGPRToVGPRSpill( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, const Register SGPR, const Register VGPR, + const int Lane) const { + const MachineFunction &MF = *MBB.getParent(); + const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo(); + + int DwarfSGPR = MCRI.getDwarfRegNum(SGPR, false); + int DwarfVGPR = MCRI.getDwarfRegNum(VGPR, false); + assert(DwarfSGPR != -1 && DwarfVGPR != -1); + assert(Lane != -1 && "Expected a lane to be present"); + + // Build a CFI instruction that represents a SGPR spilled to a single lane of + // a VGPR. + MCCFIInstruction::VectorRegisterWithLane VR{unsigned(DwarfVGPR), + unsigned(Lane), VGPRLaneBitSize}; + auto CFIInst = + MCCFIInstruction::createLLVMVectorRegisters(nullptr, DwarfSGPR, {VR}); + return buildCFI(MBB, MBBI, DL, std::move(CFIInst)); +} + +MachineInstr *SIFrameLowering::buildCFIForSGPRToVGPRSpill( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, Register SGPR, + ArrayRef VGPRSpills) const { + const MachineFunction &MF = *MBB.getParent(); + const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo(); + + int DwarfSGPR = MCRI.getDwarfRegNum(SGPR, false); + assert(DwarfSGPR != -1); + + // Build a CFI instruction that represents a SGPR spilled to multiple lanes of + // multiple VGPRs. + + std::vector VGPRs; + for (SIRegisterInfo::SpilledReg Spill : VGPRSpills) { + int DwarfVGPR = MCRI.getDwarfRegNum(Spill.VGPR, false); + assert(DwarfVGPR != -1); + assert(Spill.hasLane() && "Expected a lane to be present"); + VGPRs.push_back( + {unsigned(DwarfVGPR), unsigned(Spill.Lane), VGPRLaneBitSize}); + } + + auto CFIInst = MCCFIInstruction::createLLVMVectorRegisters(nullptr, DwarfSGPR, + std::move(VGPRs)); + return buildCFI(MBB, MBBI, DL, std::move(CFIInst)); +} + +MachineInstr *SIFrameLowering::buildCFIForSGPRToVMEMSpill( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, unsigned SGPR, int64_t Offset) const { + MachineFunction &MF = *MBB.getParent(); + const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo(); + return buildCFI(MBB, MBBI, DL, + llvm::MCCFIInstruction::createOffset( + nullptr, MCRI.getDwarfRegNum(SGPR, false), Offset)); +} + +MachineInstr *SIFrameLowering::buildCFIForVGPRToVMEMSpill( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, unsigned VGPR, int64_t Offset) const { + const MachineFunction &MF = *MBB.getParent(); + const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo(); + const GCNSubtarget &ST = MF.getSubtarget(); + + int DwarfVGPR = MCRI.getDwarfRegNum(VGPR, false); + assert(DwarfVGPR != -1); + + unsigned MaskReg = MCRI.getDwarfRegNum( + ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC, false); + auto CFIInst = MCCFIInstruction::createLLVMVectorOffset( + nullptr, DwarfVGPR, VGPRLaneBitSize, MaskReg, ST.getWavefrontSize(), + Offset); + return buildCFI(MBB, MBBI, DL, std::move(CFIInst)); +} + +MachineInstr *SIFrameLowering::buildCFIForRegToSGPRPairSpill( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, const Register Reg, const Register SGPRPair) const { + const MachineFunction &MF = *MBB.getParent(); + const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo(); + const GCNSubtarget &ST = MF.getSubtarget(); + const SIRegisterInfo &TRI = ST.getInstrInfo()->getRegisterInfo(); + + int SGPR0 = TRI.getSubReg(SGPRPair, AMDGPU::sub0); + int SGPR1 = TRI.getSubReg(SGPRPair, AMDGPU::sub1); + + int DwarfReg = MCRI.getDwarfRegNum(Reg, false); + int DwarfSGPR0 = MCRI.getDwarfRegNum(SGPR0, false); + int DwarfSGPR1 = MCRI.getDwarfRegNum(SGPR1, false); + assert(DwarfReg != -1 && DwarfSGPR0 != 1 && DwarfSGPR1 != 1); + + auto CFIInst = MCCFIInstruction::createLLVMRegisterPair( + nullptr, DwarfReg, DwarfSGPR0, SGPRBitSize, DwarfSGPR1, SGPRBitSize); + return buildCFI(MBB, MBBI, DL, std::move(CFIInst)); +} + +MachineInstr * +SIFrameLowering::buildCFIForSameValue(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, Register Reg) const { + const MachineFunction &MF = *MBB.getParent(); + const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo(); + int DwarfReg = MCRI.getDwarfRegNum(Reg, /*isEH=*/false); + auto CFIInst = MCCFIInstruction::createSameValue(nullptr, DwarfReg); + return buildCFI(MBB, MBBI, DL, std::move(CFIInst)); +} diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.h b/llvm/lib/Target/AMDGPU/SIFrameLowering.h index a72772987262e..a64164f9eaff9 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.h +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.h @@ -39,7 +39,8 @@ class SIFrameLowering final : public AMDGPUFrameLowering { void emitCSRSpillStores(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, LiveRegUnits &LiveUnits, Register FrameReg, - Register FramePtrRegScratchCopy) const; + Register FramePtrRegScratchCopy, + const bool NeedsFrameMoves) const; void emitCSRSpillRestores(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, LiveRegUnits &LiveUnits, Register FrameReg, @@ -101,9 +102,69 @@ class SIFrameLowering final : public AMDGPUFrameLowering { Register PreloadedPrivateBufferReg, Register ScratchRsrcReg, Register ScratchWaveOffsetReg) const; + void emitPrologueEntryCFI(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL) const; + + void emitDefCFA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + DebugLoc const &DL, Register StackPtrReg, + bool AspaceAlreadyDefined, + MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const; + public: bool requiresStackPointerReference(const MachineFunction &MF) const; + /// If '-amdgpu-spill-cfi-saved-regs' is enabled, emit RA/EXEC spills to + /// a free VGPR (lanes) or memory and corresponding CFI rules. + void emitCFISavedRegSpills(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + LiveRegUnits &LiveRegs, + bool emitSpillsToMem) const; + + /// Create a CFI index for CFIInst and build a MachineInstr around it. + MachineInstr * + buildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, const MCCFIInstruction &CFIInst, + MachineInstr::MIFlag flag = MachineInstr::FrameSetup) const; + + /// Create a CFI index describing a spill of the VGPR/AGPR \p Reg to another + /// VGPR/AGPR \p RegCopy and build a MachineInstr around it. + MachineInstr *buildCFIForVRegToVRegSpill(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, + const Register Reg, + const Register RegCopy) const; + /// Create a CFI index describing a spill of an SGPR to a single lane of + /// a VGPR and build a MachineInstr around it. + MachineInstr *buildCFIForSGPRToVGPRSpill(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, const Register SGPR, + const Register VGPR, const int Lane) const; + /// Create a CFI index describing a spill of an SGPR to multiple lanes of + /// VGPRs and build a MachineInstr around it. + MachineInstr *buildCFIForSGPRToVGPRSpill( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, Register SGPR, + ArrayRef VGPRSpills) const; + /// Create a CFI index describing a spill of a SGPR to VMEM and + /// build a MachineInstr around it. + MachineInstr *buildCFIForSGPRToVMEMSpill(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, unsigned SGPR, + int64_t Offset) const; + /// Create a CFI index describing a spill of a VGPR to VMEM and + /// build a MachineInstr around it. + MachineInstr *buildCFIForVGPRToVMEMSpill(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, unsigned VGPR, + int64_t Offset) const; + MachineInstr *buildCFIForRegToSGPRPairSpill(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, Register Reg, + Register SGPRPair) const; + MachineInstr *buildCFIForSameValue(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, Register Reg) const; // Returns true if the function may need to reserve space on the stack for the // CWSR trap handler. bool mayReserveScratchForCWSR(const MachineFunction &MF) const; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index be4229155c983..69cc38c35314c 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1644,6 +1644,26 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore; return true; } + case Intrinsic::amdgcn_global_load_b128: + case Intrinsic::amdgcn_global_store_b128: { + bool IsStore = IntrID == Intrinsic::amdgcn_global_store_b128; + Info.opc = IsStore ? ISD::INTRINSIC_VOID : ISD::INTRINSIC_W_CHAIN; + Info.memVT = EVT::getIntegerVT(CI.getContext(), 128); + Info.ptrVal = CI.getArgOperand(0); + Info.flags |= + IsStore ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad; + // Pretend to be atomic so that SIMemoryLegalizer::expandStore sets cache + // flags appropriately. + Info.order = AtomicOrdering::Monotonic; + + LLVMContext &Ctx = CI.getContext(); + unsigned ScopeIdx = CI.arg_size() - 1; + MDNode *ScopeMD = cast( + cast(CI.getArgOperand(ScopeIdx))->getMetadata()); + StringRef Scope = cast(ScopeMD->getOperand(0))->getString(); + Info.ssid = Ctx.getOrInsertSyncScopeID(Scope); + return true; + } case Intrinsic::amdgcn_load_to_lds: case Intrinsic::amdgcn_global_load_lds: { Info.opc = ISD::INTRINSIC_VOID; @@ -1750,6 +1770,8 @@ bool SITargetLowering::getAddrModeArguments(const IntrinsicInst *II, case Intrinsic::amdgcn_global_store_async_from_lds_b32: case Intrinsic::amdgcn_global_store_async_from_lds_b64: case Intrinsic::amdgcn_global_store_async_from_lds_b128: + case Intrinsic::amdgcn_global_load_b128: + case Intrinsic::amdgcn_global_store_b128: Ptr = II->getArgOperand(0); break; case Intrinsic::amdgcn_load_to_lds: diff --git a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp index 0a68512668c7d..40356bf85d88c 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp @@ -175,6 +175,35 @@ class SIInsertHardClauses { SmallVector BaseOps; }; + void substituteDebugInstrNumbersToBundleHeader(MachineInstr &FirstInBundle) { + auto *MBB = FirstInBundle.getParent(); + auto *MF = MBB->getParent(); + + // Make a map from registers defined within the bundle to their defining + // debug instruction number and operand. + DenseMap> RegDefs; + for (const MachineOperand &Op : const_mi_bundle_ops(FirstInBundle)) { + const MachineInstr &MI = *Op.getParent(); + if (!MI.isBundle() && Op.isReg() && Op.isDef()) + RegDefs[Op.getReg()] = {MI.peekDebugInstrNum(), Op.getOperandNo()}; + } + + MachineInstr &BundleHeader = *std::prev(FirstInBundle.getIterator()); + for (const MachineOperand &HeaderOp : BundleHeader.operands()) { + if (!HeaderOp.isReg() || !HeaderOp.isDef() || HeaderOp.isDead()) + continue; + auto It = RegDefs.find(HeaderOp.getReg()); + if (It == RegDefs.end()) + continue; + auto [DINum, OpNum] = It->second; + if (DINum == 0) + continue; + MF->makeDebugValueSubstitution( + {DINum, OpNum}, + {BundleHeader.getDebugInstrNum(), HeaderOp.getOperandNo()}); + } + } + bool emitClause(const ClauseInfo &CI, const SIInstrInfo *SII) { if (CI.First == CI.Last) return false; @@ -182,11 +211,25 @@ class SIInsertHardClauses { "Hard clause is too long!"); auto &MBB = *CI.First->getParent(); + bool NeedDebugSubs = false; + // Move debug instructions before the bundle and check if debug + // substitutions need to be added to the bundle header. + for (auto It = CI.First->getIterator(), + E = std::next(CI.Last->getIterator()); + It != E;) { + auto MI = It++; + if (MI->isDebugInstr()) + MBB.splice(CI.First, &MBB, MI); + else if (MI->peekDebugInstrNum() != 0) + NeedDebugSubs = true; + } auto ClauseMI = BuildMI(MBB, *CI.First, DebugLoc(), SII->get(AMDGPU::S_CLAUSE)) .addImm(CI.Length - 1); finalizeBundle(MBB, ClauseMI->getIterator(), std::next(CI.Last->getIterator())); + if (NeedDebugSubs) + substituteDebugInstrNumbersToBundleHeader(*ClauseMI); return true; } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index d930a21c2d7f5..06ca84e951487 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1530,22 +1530,26 @@ SIInstrInfo::getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, return get(getIndirectVGPRWriteMovRelPseudoOpc(VecSize)); } -static unsigned getSGPRSpillSaveOpcode(unsigned Size) { +static unsigned getSGPRSpillSaveOpcode(unsigned Size, bool NeedsCFI) { switch (Size) { case 4: - return AMDGPU::SI_SPILL_S32_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_S32_CFI_SAVE : AMDGPU::SI_SPILL_S32_SAVE; case 8: - return AMDGPU::SI_SPILL_S64_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_S64_CFI_SAVE : AMDGPU::SI_SPILL_S64_SAVE; case 12: - return AMDGPU::SI_SPILL_S96_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_S96_CFI_SAVE : AMDGPU::SI_SPILL_S96_SAVE; case 16: - return AMDGPU::SI_SPILL_S128_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_S128_CFI_SAVE + : AMDGPU::SI_SPILL_S128_SAVE; case 20: - return AMDGPU::SI_SPILL_S160_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_S160_CFI_SAVE + : AMDGPU::SI_SPILL_S160_SAVE; case 24: - return AMDGPU::SI_SPILL_S192_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_S192_CFI_SAVE + : AMDGPU::SI_SPILL_S192_SAVE; case 28: - return AMDGPU::SI_SPILL_S224_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_S224_CFI_SAVE + : AMDGPU::SI_SPILL_S224_SAVE; case 32: return AMDGPU::SI_SPILL_S256_SAVE; case 36: @@ -1557,69 +1561,87 @@ static unsigned getSGPRSpillSaveOpcode(unsigned Size) { case 48: return AMDGPU::SI_SPILL_S384_SAVE; case 64: - return AMDGPU::SI_SPILL_S512_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_S512_CFI_SAVE + : AMDGPU::SI_SPILL_S512_SAVE; case 128: - return AMDGPU::SI_SPILL_S1024_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_S1024_CFI_SAVE + : AMDGPU::SI_SPILL_S1024_SAVE; default: llvm_unreachable("unknown register size"); } } -static unsigned getVGPRSpillSaveOpcode(unsigned Size) { +static unsigned getVGPRSpillSaveOpcode(unsigned Size, bool NeedsCFI) { switch (Size) { case 2: return AMDGPU::SI_SPILL_V16_SAVE; case 4: - return AMDGPU::SI_SPILL_V32_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V32_CFI_SAVE : AMDGPU::SI_SPILL_V32_SAVE; case 8: - return AMDGPU::SI_SPILL_V64_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V64_CFI_SAVE : AMDGPU::SI_SPILL_V64_SAVE; case 12: - return AMDGPU::SI_SPILL_V96_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V96_CFI_SAVE : AMDGPU::SI_SPILL_V96_SAVE; case 16: - return AMDGPU::SI_SPILL_V128_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V128_CFI_SAVE + : AMDGPU::SI_SPILL_V128_SAVE; case 20: - return AMDGPU::SI_SPILL_V160_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V160_CFI_SAVE + : AMDGPU::SI_SPILL_V160_SAVE; case 24: - return AMDGPU::SI_SPILL_V192_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V192_CFI_SAVE + : AMDGPU::SI_SPILL_V192_SAVE; case 28: - return AMDGPU::SI_SPILL_V224_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V224_CFI_SAVE + : AMDGPU::SI_SPILL_V224_SAVE; case 32: - return AMDGPU::SI_SPILL_V256_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V256_CFI_SAVE + : AMDGPU::SI_SPILL_V256_SAVE; case 36: - return AMDGPU::SI_SPILL_V288_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V288_CFI_SAVE + : AMDGPU::SI_SPILL_V288_SAVE; case 40: - return AMDGPU::SI_SPILL_V320_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V320_CFI_SAVE + : AMDGPU::SI_SPILL_V320_SAVE; case 44: - return AMDGPU::SI_SPILL_V352_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V352_CFI_SAVE + : AMDGPU::SI_SPILL_V352_SAVE; case 48: - return AMDGPU::SI_SPILL_V384_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V384_CFI_SAVE + : AMDGPU::SI_SPILL_V384_SAVE; case 64: - return AMDGPU::SI_SPILL_V512_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V512_CFI_SAVE + : AMDGPU::SI_SPILL_V512_SAVE; case 128: - return AMDGPU::SI_SPILL_V1024_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_V1024_CFI_SAVE + : AMDGPU::SI_SPILL_V1024_SAVE; default: llvm_unreachable("unknown register size"); } } -static unsigned getAVSpillSaveOpcode(unsigned Size) { +static unsigned getAVSpillSaveOpcode(unsigned Size, bool NeedsCFI) { switch (Size) { case 4: - return AMDGPU::SI_SPILL_AV32_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_AV32_CFI_SAVE : AMDGPU::SI_SPILL_AV32_SAVE; case 8: - return AMDGPU::SI_SPILL_AV64_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_AV64_CFI_SAVE : AMDGPU::SI_SPILL_AV64_SAVE; case 12: - return AMDGPU::SI_SPILL_AV96_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_AV96_CFI_SAVE : AMDGPU::SI_SPILL_AV96_SAVE; case 16: - return AMDGPU::SI_SPILL_AV128_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_AV128_CFI_SAVE + : AMDGPU::SI_SPILL_AV128_SAVE; case 20: - return AMDGPU::SI_SPILL_AV160_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_AV160_CFI_SAVE + : AMDGPU::SI_SPILL_AV160_SAVE; case 24: - return AMDGPU::SI_SPILL_AV192_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_AV192_CFI_SAVE + : AMDGPU::SI_SPILL_AV192_SAVE; case 28: - return AMDGPU::SI_SPILL_AV224_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_AV224_CFI_SAVE + : AMDGPU::SI_SPILL_AV224_SAVE; case 32: - return AMDGPU::SI_SPILL_AV256_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_AV256_CFI_SAVE + : AMDGPU::SI_SPILL_AV256_SAVE; case 36: return AMDGPU::SI_SPILL_AV288_SAVE; case 40: @@ -1629,9 +1651,11 @@ static unsigned getAVSpillSaveOpcode(unsigned Size) { case 48: return AMDGPU::SI_SPILL_AV384_SAVE; case 64: - return AMDGPU::SI_SPILL_AV512_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_AV512_CFI_SAVE + : AMDGPU::SI_SPILL_AV512_SAVE; case 128: - return AMDGPU::SI_SPILL_AV1024_SAVE; + return NeedsCFI ? AMDGPU::SI_SPILL_AV1024_CFI_SAVE + : AMDGPU::SI_SPILL_AV1024_SAVE; default: llvm_unreachable("unknown register size"); } @@ -1651,7 +1675,7 @@ static unsigned getWWMRegSpillSaveOpcode(unsigned Size, unsigned SIInstrInfo::getVectorRegSpillSaveOpcode( Register Reg, const TargetRegisterClass *RC, unsigned Size, - const SIMachineFunctionInfo &MFI) const { + const SIMachineFunctionInfo &MFI, bool NeedsCFI) const { bool IsVectorSuperClass = RI.isVectorSuperClass(RC); // Choose the right opcode if spilling a WWM register. @@ -1660,16 +1684,16 @@ unsigned SIInstrInfo::getVectorRegSpillSaveOpcode( // TODO: Check if AGPRs are available if (ST.hasMAIInsts()) - return getAVSpillSaveOpcode(Size); + return getAVSpillSaveOpcode(Size, NeedsCFI); - return getVGPRSpillSaveOpcode(Size); + return getVGPRSpillSaveOpcode(Size, NeedsCFI); } -void SIInstrInfo::storeRegToStackSlot( +void SIInstrInfo::storeRegToStackSlotImpl( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, - MachineInstr::MIFlag Flags) const { + MachineInstr::MIFlag Flags, bool NeedsCFI) const { MachineFunction *MF = MBB.getParent(); SIMachineFunctionInfo *MFI = MF->getInfo(); MachineFrameInfo &FrameInfo = MF->getFrameInfo(); @@ -1691,7 +1715,8 @@ void SIInstrInfo::storeRegToStackSlot( // We are only allowed to create one new instruction when spilling // registers, so we need to use pseudo instruction for spilling SGPRs. - const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize)); + const MCInstrDesc &OpDesc = + get(getSGPRSpillSaveOpcode(SpillSize, NeedsCFI)); // The SGPR spill/restore instructions only work on number sgprs, so we need // to make sure we are using the correct register class. @@ -1710,8 +1735,8 @@ void SIInstrInfo::storeRegToStackSlot( return; } - unsigned Opcode = - getVectorRegSpillSaveOpcode(VReg ? VReg : SrcReg, RC, SpillSize, *MFI); + unsigned Opcode = getVectorRegSpillSaveOpcode(VReg ? VReg : SrcReg, RC, + SpillSize, *MFI, NeedsCFI); MFI->setHasSpilledVGPRs(); BuildMI(MBB, MI, DL, get(Opcode)) @@ -1722,6 +1747,25 @@ void SIInstrInfo::storeRegToStackSlot( .addMemOperand(MMO); } +void SIInstrInfo::storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags) const { + storeRegToStackSlotImpl(MBB, MI, SrcReg, isKill, FrameIndex, RC, TRI, VReg, + Flags, false); +} + +void SIInstrInfo::storeRegToStackSlotCFI(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + Register SrcReg, bool isKill, + int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const { + storeRegToStackSlotImpl(MBB, MI, SrcReg, isKill, FrameIndex, RC, TRI, + Register(), MachineInstr::NoFlags, true); +} + static unsigned getSGPRSpillRestoreOpcode(unsigned Size) { switch (Size) { case 4: @@ -4794,6 +4838,7 @@ static void copyFlagsToImplicitVCC(MachineInstr &MI, MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI, unsigned Op32) const { MachineBasicBlock *MBB = MI.getParent(); + MachineFunction *MF = MBB->getParent(); const MCInstrDesc &Op32Desc = get(Op32); MachineInstrBuilder Inst32 = @@ -4805,9 +4850,16 @@ MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI, // We assume the defs of the shrunk opcode are in the same order, and the // shrunk opcode loses the last def (SGPR def, in the VOP3->VOPC case). - for (int I = 0, E = Op32Desc.getNumDefs(); I != E; ++I) + for (int I = 0, E = Op32Desc.getNumDefs(); I != E; ++I) { Inst32.add(MI.getOperand(I)); + // If this def is used by a DBG_INSTR_REF, create a substitution for the new + // instruction. + if (unsigned DINum = MI.peekDebugInstrNum()) + MF->makeDebugValueSubstitution({DINum, I}, + {Inst32->getDebugInstrNum(), I}); + } + const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); int Idx = MI.getNumExplicitDefs(); @@ -10194,6 +10246,82 @@ MachineInstr *llvm::getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, return nullptr; } +// helper function to checkIfExecMayBeModifiedBeforeUseAcrossBB and +// execMayBeModifiedBeforeUse. This checks possible EXEC register modifications +// for a straight-line sequence of instructions between BeginIterator and +// EndIterator (both inclusive) upto a pre-defined limit MaxInstScan +bool execMayBeModifiedBeforeUseUtil( + const TargetRegisterInfo *TRI, + const MachineInstrBundleIterator BeginIterator, + const MachineInstrBundleIterator EndIterator, + const int MaxInstScan) { + + int NumInst = 0; + for (auto I = BeginIterator; I != EndIterator; ++I) { + if (I->isMetaInstruction()) + continue; + + if (++NumInst > MaxInstScan) + return true; + + if (I->modifiesRegister(AMDGPU::EXEC, TRI)) + return true; + } + return false; +} + +// Variant of execMayBeModifiedBeforeUse(), where DefMI and UseMI belong to +// different basic blocks. Current code is limited to a very simple case: DefMI +// in the predecessor BB of the single BB loop where UseMI resides. +bool llvm::checkIfExecMayBeModifiedBeforeUseAcrossBB( + const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, + const MachineInstr &UseMI, const int SIFoldOperandsPreheaderThreshold) { + + assert(MRI.isSSA() && "Must be run on SSA"); + auto *TRI = MRI.getTargetRegisterInfo(); + auto *DefBB = DefMI.getParent(); + const int MaxInstScan = (SIFoldOperandsPreheaderThreshold > 10000) + ? 10000 + : SIFoldOperandsPreheaderThreshold; + + // Check whether EXEC is modified along all possible control flow between + // DefMI and UseMI, which may include loop backedge + // 1. UseBB is the only successor of DefBB + // 2. UseBB is a single basic block loop (only two predecessor blocks: DefBB + // and UseBB) + // 3. check if EXEC is modified + auto *UseBB = UseMI.getParent(); + if (UseBB != DefBB) { + if (!(DefBB->isSuccessor(UseBB) && (DefBB->succ_size() == 1))) + return true; + + if (!((UseBB->pred_size() == 2) && UseBB->isPredecessor(UseBB) && + UseBB->isPredecessor(DefBB))) + return true; + + bool canExecBeModifiedBeforeUse = execMayBeModifiedBeforeUseUtil( + TRI, UseBB->begin(), UseBB->end(), MaxInstScan); + if (canExecBeModifiedBeforeUse) + return true; + + // Stop scan at the end of the DEF basic block. + // If we are here, we know for sure that the instructions in focus are in + // the same basic block. Scan them to be safe. + canExecBeModifiedBeforeUse = execMayBeModifiedBeforeUseUtil( + TRI, std::next(DefMI.getIterator()), DefBB->end(), MaxInstScan); + if (canExecBeModifiedBeforeUse) + return true; + + } else { + // Stop scan at the use. + bool canExecBeModifiedBeforeUse = execMayBeModifiedBeforeUseUtil( + TRI, std::next(DefMI.getIterator()), UseMI.getIterator(), MaxInstScan); + if (canExecBeModifiedBeforeUse) + return true; + } + return false; +} + bool llvm::execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, @@ -10209,20 +10337,12 @@ bool llvm::execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, return true; const int MaxInstScan = 20; - int NumInst = 0; // Stop scan at the use. - auto E = UseMI.getIterator(); - for (auto I = std::next(DefMI.getIterator()); I != E; ++I) { - if (I->isDebugInstr()) - continue; - - if (++NumInst > MaxInstScan) - return true; - - if (I->modifiesRegister(AMDGPU::EXEC, TRI)) - return true; - } + bool canExecBeModifiedBeforeUse = execMayBeModifiedBeforeUseUtil( + TRI, std::next(DefMI.getIterator()), UseMI.getIterator(), MaxInstScan); + if (canExecBeModifiedBeforeUse) + return true; return false; } @@ -10259,7 +10379,7 @@ bool llvm::execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, for (auto I = std::next(DefMI.getIterator()); ; ++I) { assert(I != DefBB->end()); - if (I->isDebugInstr()) + if (I->isMetaInstruction()) continue; if (++NumInst > MaxInstScan) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index dc23a21f959ce..211642d7c4460 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -293,13 +293,29 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo { MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const; +private: + void storeRegToStackSlotImpl(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, Register SrcReg, + bool isKill, int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg, + MachineInstr::MIFlag Flags, bool NeedsCFI) const; + +public: + void storeRegToStackSlotCFI(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, Register SrcReg, + bool isKill, int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const; + bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override; unsigned getVectorRegSpillSaveOpcode(Register Reg, const TargetRegisterClass *RC, unsigned Size, - const SIMachineFunctionInfo &MFI) const; + const SIMachineFunctionInfo &MFI, + bool NeedsCFI) const; unsigned getVectorRegSpillRestoreOpcode(Register Reg, const TargetRegisterClass *RC, unsigned Size, @@ -703,6 +719,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo { static bool isBlockLoadStore(uint16_t Opcode) { switch (Opcode) { case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE: + case AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE: case AMDGPU::SI_BLOCK_SPILL_V1024_RESTORE: case AMDGPU::SCRATCH_STORE_BLOCK_SADDR: case AMDGPU::SCRATCH_LOAD_BLOCK_SADDR: @@ -1697,6 +1714,10 @@ bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, const MachineInstr &DefMI, const MachineInstr &UseMI); +bool checkIfExecMayBeModifiedBeforeUseAcrossBB( + const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, + const MachineInstr &UseMI, const int SIFoldOperandsPreheaderThreshold); + /// \brief Return false if EXEC is not changed between the def of \p VReg at \p /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to /// track between blocks. diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 6f1feb1dc2996..54b584ea66965 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1086,6 +1086,13 @@ multiclass SI_SPILL_SGPR { let mayLoad = 0; } + def _CFI_SAVE : PseudoInstSI < + (outs), + (ins sgpr_class:$data, i32imm:$addr)> { + let mayStore = 1; + let mayLoad = 0; + } + def _RESTORE : PseudoInstSI < (outs sgpr_class:$data), (ins i32imm:$addr)> { @@ -1123,6 +1130,7 @@ def SI_SPILL_S32_TO_VGPR : PseudoInstSI <(outs VGPR_32:$vdst), let hasSideEffects = 0; let mayLoad = 0; let mayStore = 0; + let VALU = 1; let hasExtraDefRegAllocReq = 1; let Constraints = "$vdst = $vdst_in"; } @@ -1134,6 +1142,7 @@ def SI_RESTORE_S32_FROM_VGPR : PseudoInstSI <(outs SReg_32:$sdst), let hasSideEffects = 0; let mayLoad = 0; let mayStore = 0; + let VALU = 1; let hasExtraSrcRegAllocReq = 1; } } // End Spill = 1, VALU = 1, isConvergent = 1 @@ -1159,6 +1168,20 @@ multiclass SI_SPILL_VGPR { + let mayStore = 1; + let mayLoad = 0; + // (2 * 4) + (8 * num_subregs) bytes maximum + int MaxSize = !add(!shl(!srl(vgpr_class.Size, 5), !add(UsesTmp, 3)), 8); + // Size field is unsigned char and cannot fit more. + let Size = !if(!le(MaxSize, 256), MaxSize, 252); + } + def _RESTORE : VPseudoInstSI < (outs vgpr_class:$vdata), !con( diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index f0d1117664983..e8a6bce317f3e 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -233,7 +233,8 @@ class SILoadStoreOptimizer { void copyToDestRegs(CombineInfo &CI, CombineInfo &Paired, MachineBasicBlock::iterator InsertBefore, - AMDGPU::OpName OpName, Register DestReg) const; + AMDGPU::OpName OpName, Register DestReg, + MachineInstr *NewMI) const; Register copyFromSrcRegs(CombineInfo &CI, CombineInfo &Paired, MachineBasicBlock::iterator InsertBefore, AMDGPU::OpName OpName) const; @@ -1368,8 +1369,9 @@ SILoadStoreOptimizer::checkAndPrepareMerge(CombineInfo &CI, void SILoadStoreOptimizer::copyToDestRegs( CombineInfo &CI, CombineInfo &Paired, MachineBasicBlock::iterator InsertBefore, AMDGPU::OpName OpName, - Register DestReg) const { + Register DestReg, MachineInstr *NewMI) const { MachineBasicBlock *MBB = CI.I->getParent(); + MachineFunction *MF = MBB->getParent(); DebugLoc DL = CI.I->getDebugLoc(); auto [SubRegIdx0, SubRegIdx1] = getSubRegIdxs(CI, Paired); @@ -1391,6 +1393,17 @@ void SILoadStoreOptimizer::copyToDestRegs( BuildMI(*MBB, InsertBefore, DL, CopyDesc) .add(*Dest1) .addReg(DestReg, RegState::Kill, SubRegIdx1); + + if (unsigned DINum = CI.I->peekDebugInstrNum()) { + unsigned NewDINum = NewMI->getDebugInstrNum(); + MF->makeDebugValueSubstitution(std::make_pair(DINum, 0), + std::make_pair(NewDINum, 0), SubRegIdx0); + } + if (unsigned DINum = Paired.I->peekDebugInstrNum()) { + unsigned NewDINum = NewMI->getDebugInstrNum(); + MF->makeDebugValueSubstitution(std::make_pair(DINum, 0), + std::make_pair(NewDINum, 0), SubRegIdx1); + } } // Return a register for the source of the merged store after copying the @@ -1484,7 +1497,8 @@ SILoadStoreOptimizer::mergeRead2Pair(CombineInfo &CI, CombineInfo &Paired, .addImm(0) // gds .cloneMergedMemRefs({&*CI.I, &*Paired.I}); - copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdst, DestReg); + copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdst, DestReg, + Read2); CI.I->eraseFromParent(); Paired.I->eraseFromParent(); @@ -1607,7 +1621,7 @@ SILoadStoreOptimizer::mergeImagePair(CombineInfo &CI, CombineInfo &Paired, MachineInstr *New = MIB.addMemOperand(combineKnownAdjacentMMOs(CI, Paired)); - copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg); + copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg, New); CI.I->eraseFromParent(); Paired.I->eraseFromParent(); @@ -1639,7 +1653,7 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeSMemLoadImmPair( New.addImm(MergedOffset); New.addImm(CI.CPol).addMemOperand(combineKnownAdjacentMMOs(CI, Paired)); - copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::sdst, DestReg); + copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::sdst, DestReg, New); CI.I->eraseFromParent(); Paired.I->eraseFromParent(); @@ -1680,7 +1694,7 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeBufferLoadPair( .addImm(0) // swz .addMemOperand(combineKnownAdjacentMMOs(CI, Paired)); - copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg); + copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg, New); CI.I->eraseFromParent(); Paired.I->eraseFromParent(); @@ -1731,7 +1745,7 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeTBufferLoadPair( .addImm(0) // swz .addMemOperand(combineKnownAdjacentMMOs(CI, Paired)); - copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg); + copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg, New); CI.I->eraseFromParent(); Paired.I->eraseFromParent(); @@ -1807,7 +1821,7 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeFlatLoadPair( .addImm(CI.CPol) .addMemOperand(combineKnownAdjacentMMOs(CI, Paired)); - copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdst, DestReg); + copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdst, DestReg, New); CI.I->eraseFromParent(); Paired.I->eraseFromParent(); diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 40eeeb8a8630d..a78e19218c315 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -100,63 +100,26 @@ INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE, char &llvm::SILowerSGPRSpillsLegacyID = SILowerSGPRSpillsLegacy::ID; -static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB, - const TargetRegisterInfo *TRI) { - for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) { - if (MBB.isLiveIn(*R)) { - return true; - } - } - return false; -} - /// Insert spill code for the callee-saved registers used in the function. -static void insertCSRSaves(MachineBasicBlock &SaveBlock, - ArrayRef CSI, SlotIndexes *Indexes, +static void insertCSRSaves(const GCNSubtarget &ST, MachineBasicBlock &SaveBlock, + ArrayRef CSI, + SlotIndexes *Indexes, LiveIntervals *LIS) { - MachineFunction &MF = *SaveBlock.getParent(); - const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); - const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); - const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); - const GCNSubtarget &ST = MF.getSubtarget(); - const SIRegisterInfo *RI = ST.getRegisterInfo(); - + const TargetFrameLowering *TFI = ST.getFrameLowering(); + const TargetRegisterInfo *TRI = ST.getRegisterInfo(); MachineBasicBlock::iterator I = SaveBlock.begin(); - if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) { - for (const CalleeSavedInfo &CS : CSI) { - // Insert the spill to the stack frame. - MCRegister Reg = CS.getReg(); - - MachineInstrSpan MIS(I, &SaveBlock); - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( - Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32); - - // If this value was already livein, we probably have a direct use of the - // incoming register value, so don't kill at the spill point. This happens - // since we pass some special inputs (workgroup IDs) in the callee saved - // range. - const bool IsLiveIn = isLiveIntoMBB(Reg, SaveBlock, TRI); - TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(), - RC, TRI, Register()); - - if (Indexes) { - assert(std::distance(MIS.begin(), I) == 1); - MachineInstr &Inst = *std::prev(I); - Indexes->insertMachineInstrInMaps(Inst); - } - - if (LIS) - LIS->removeAllRegUnitsForPhysReg(Reg); - } - } else { - // TFI doesn't update Indexes and LIS, so we have to do it separately. - if (Indexes) - Indexes->repairIndexesInRange(&SaveBlock, SaveBlock.begin(), I); - - if (LIS) - for (const CalleeSavedInfo &CS : CSI) - LIS->removeAllRegUnitsForPhysReg(CS.getReg()); - } + MachineInstrSpan MIS(I, &SaveBlock); + bool Success = TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI); + assert(Success && "spillCalleeSavedRegisters should always succeed"); + (void)Success; + + // TFI doesn't update Indexes and LIS, so we have to do it separately. + if (Indexes) + Indexes->repairIndexesInRange(&SaveBlock, SaveBlock.begin(), I); + + if (LIS) + for (const CalleeSavedInfo &CS : CSI) + LIS->removeAllRegUnitsForPhysReg(CS.getReg()); } /// Insert restore code for the callee-saved registers used in the function. @@ -268,11 +231,19 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs( std::vector CSI; const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs(); + Register RetAddrReg = TRI->getReturnAddressReg(MF); + bool SpillRetAddrReg = false; for (unsigned I = 0; CSRegs[I]; ++I) { MCRegister Reg = CSRegs[I]; if (SavedRegs.test(Reg)) { + if (Reg == TRI->getSubReg(RetAddrReg, AMDGPU::sub0) || + Reg == TRI->getSubReg(RetAddrReg, AMDGPU::sub1)) { + SpillRetAddrReg = true; + continue; + } + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, MVT::i32); int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC), @@ -283,9 +254,21 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs( } } + // Return address uses a register pair. Add the super register to the + // CSI list so that it's easier to identify the entire spill and CFI + // can be emitted appropriately. + if (SpillRetAddrReg) { + const TargetRegisterClass *RC = + TRI->getMinimalPhysRegClass(RetAddrReg, MVT::i64); + int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC), + TRI->getSpillAlign(*RC), true); + CSI.push_back(CalleeSavedInfo(RetAddrReg, JunkFI)); + CalleeSavedFIs.push_back(JunkFI); + } + if (!CSI.empty()) { for (MachineBasicBlock *SaveBlock : SaveBlocks) - insertCSRSaves(*SaveBlock, CSI, Indexes, LIS); + insertCSRSaves(ST, *SaveBlock, CSI, Indexes, LIS); // Add live ins to save blocks. assert(SaveBlocks.size() == 1 && "shrink wrapping not fully implemented"); @@ -308,7 +291,7 @@ void SILowerSGPRSpills::updateLaneVGPRDomInstr( // depth first order doesn't really help since the machine function can be in // the unstructured control flow post-SSA. For each virtual register, hence // finding the common dominator to get either the dominating spill or a block - // dominating all spills. + // dominating all spills. Is there a better way to handle it? SIMachineFunctionInfo *FuncInfo = MBB->getParent()->getInfo(); ArrayRef VGPRSpills = @@ -359,9 +342,8 @@ void SILowerSGPRSpills::determineRegsForWWMAllocation(MachineFunction &MF, BitVector NonWwmAllocMask(TRI->getNumRegs()); const GCNSubtarget &ST = MF.getSubtarget(); - // FIXME: MaxNumVGPRsForWwmAllocation might need to be adjusted in the future - // to have a balanced allocation between WWM values and per-thread vector - // register operands. + // FIXME: MaxNumVGPRsForWwmAllocation should be tuned in to have a balanced + // allocation between WWM values and other vector register operands. unsigned NumRegs = MaxNumVGPRsForWwmAllocation; NumRegs = std::min(static_cast(MFI->getSGPRSpillVGPRs().size()), NumRegs); @@ -520,8 +502,7 @@ bool SILowerSGPRSpills::run(MachineFunction &MF) { BitVector NonWwmRegMask(WwmRegMask); NonWwmRegMask.flip().clearBitsNotInMask(TRI->getAllVGPRRegMask()); - // The complement set will be the registers for non-wwm (per-thread) vgpr - // allocation. + // The complement set will be the registers for non-wwm vgpr allocation. FuncInfo->updateNonWWMRegMask(NonWwmRegMask); } @@ -549,7 +530,7 @@ bool SILowerSGPRSpills::run(MachineFunction &MF) { // free frame index ids by the later pass(es) like "stack slot coloring" // which in turn could mess-up with the book keeping of "frame index to VGPR // lane". - FuncInfo->removeDeadFrameIndices(MFI, /*ResetSGPRSpillStackIDs*/ false); + FuncInfo->removeDeadFrameIndices(MF, /*ResetSGPRSpillStackIDs*/ false); MadeChange = true; } diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index b398db4f7caff..c6dc40c0b3ef0 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -386,6 +386,9 @@ void SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange( if (RegItr != SpillPhysVGPRs.end()) { unsigned Idx = std::distance(SpillPhysVGPRs.begin(), RegItr); SpillPhysVGPRs[Idx] = NewReg; + + // For replacing registers used in the CFI instructions. + MF.replaceFrameInstRegister(Reg, NewReg); } // The generic `determineCalleeSaves` might have set the old register if it @@ -566,7 +569,8 @@ bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF, } bool SIMachineFunctionInfo::removeDeadFrameIndices( - MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) { + MachineFunction &MF, bool ResetSGPRSpillStackIDs) { + MachineFrameInfo &MFI = MF.getFrameInfo(); // Remove dead frame indices from function frame, however keep FP & BP since // spills for them haven't been inserted yet. And also make sure to remove the // frame indices from `SGPRSpillsToVirtualVGPRLanes` data structure, diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index 019c3b79e5fe5..419bf533510dd 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -752,6 +752,16 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction, }) != PrologEpilogSGPRSpills.end(); } + // Remove if an entry created for \p Reg. + void removePrologEpilogSGPRSpillEntry(Register Reg) { + auto I = find_if(PrologEpilogSGPRSpills, + [&Reg](const auto &Spill) { return Spill.first == Reg; }); + if (I == PrologEpilogSGPRSpills.end()) + return; + + PrologEpilogSGPRSpills.erase(I); + } + const PrologEpilogSGPRSaveRestoreInfo & getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const { const auto *I = find_if(PrologEpilogSGPRSpills, [&Reg](const auto &Spill) { @@ -830,7 +840,7 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction, /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill /// to the default stack. - bool removeDeadFrameIndices(MachineFrameInfo &MFI, + bool removeDeadFrameIndices(MachineFunction &MF, bool ResetSGPRSpillStackIDs); int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI); diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index d80a6f339c8f6..ce35e87c86d5b 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -35,6 +35,11 @@ static cl::opt EnableSpillSGPRToVGPR( cl::ReallyHidden, cl::init(true)); +static cl::opt EnableSpillCFISavedRegs( + "amdgpu-spill-cfi-saved-regs", + cl::desc("Enable spilling the registers required for CFI emission"), + cl::ReallyHidden, cl::init(false), cl::ZeroOrMore); + std::array, 32> SIRegisterInfo::RegSplitParts; std::array, 9> SIRegisterInfo::SubRegFromChannelTable; @@ -559,6 +564,10 @@ unsigned SIRegisterInfo::getSubRegFromChannel(unsigned Channel, return SubRegFromChannelTable[NumRegIndex - 1][Channel]; } +bool SIRegisterInfo::isCFISavedRegsSpillEnabled() const { + return EnableSpillCFISavedRegs; +} + MCRegister SIRegisterInfo::getAlignedHighSGPRForRC(const MachineFunction &MF, const unsigned Align, @@ -1109,6 +1118,16 @@ bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, SIInstrFlags::FlatScratch); } +std::optional SIRegisterInfo::getDwarfRegLaneSize(int64_t DwarfReg, + bool IsEH) const { + if (std::optional Reg = getLLVMRegNum(DwarfReg, IsEH)) { + const TargetRegisterClass *RC = getPhysRegBaseClass(*Reg); + if (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::AGPR_32RegClass) + return 4; + } + return std::nullopt; +} + const TargetRegisterClass * SIRegisterInfo::getPointerRegClass(unsigned Kind) const { // This is inaccurate. It depends on the instruction and address space. The @@ -1128,6 +1147,7 @@ static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI, unsigned Op = MI.getOpcode(); switch (Op) { case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE: + case AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE: case AMDGPU::SI_BLOCK_SPILL_V1024_RESTORE: // FIXME: This assumes the mask is statically known and not computed at // runtime. However, some ABIs may want to compute the mask dynamically and @@ -1135,21 +1155,29 @@ static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI, return llvm::popcount( (uint64_t)TII->getNamedOperand(MI, AMDGPU::OpName::mask)->getImm()); case AMDGPU::SI_SPILL_S1024_SAVE: + case AMDGPU::SI_SPILL_S1024_CFI_SAVE: case AMDGPU::SI_SPILL_S1024_RESTORE: case AMDGPU::SI_SPILL_V1024_SAVE: + case AMDGPU::SI_SPILL_V1024_CFI_SAVE: case AMDGPU::SI_SPILL_V1024_RESTORE: case AMDGPU::SI_SPILL_A1024_SAVE: + case AMDGPU::SI_SPILL_A1024_CFI_SAVE: case AMDGPU::SI_SPILL_A1024_RESTORE: case AMDGPU::SI_SPILL_AV1024_SAVE: + case AMDGPU::SI_SPILL_AV1024_CFI_SAVE: case AMDGPU::SI_SPILL_AV1024_RESTORE: return 32; case AMDGPU::SI_SPILL_S512_SAVE: + case AMDGPU::SI_SPILL_S512_CFI_SAVE: case AMDGPU::SI_SPILL_S512_RESTORE: case AMDGPU::SI_SPILL_V512_SAVE: + case AMDGPU::SI_SPILL_V512_CFI_SAVE: case AMDGPU::SI_SPILL_V512_RESTORE: case AMDGPU::SI_SPILL_A512_SAVE: + case AMDGPU::SI_SPILL_A512_CFI_SAVE: case AMDGPU::SI_SPILL_A512_RESTORE: case AMDGPU::SI_SPILL_AV512_SAVE: + case AMDGPU::SI_SPILL_AV512_CFI_SAVE: case AMDGPU::SI_SPILL_AV512_RESTORE: return 16; case AMDGPU::SI_SPILL_S384_SAVE: @@ -1189,75 +1217,107 @@ static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI, case AMDGPU::SI_SPILL_AV288_RESTORE: return 9; case AMDGPU::SI_SPILL_S256_SAVE: + case AMDGPU::SI_SPILL_S256_CFI_SAVE: case AMDGPU::SI_SPILL_S256_RESTORE: case AMDGPU::SI_SPILL_V256_SAVE: + case AMDGPU::SI_SPILL_V256_CFI_SAVE: case AMDGPU::SI_SPILL_V256_RESTORE: case AMDGPU::SI_SPILL_A256_SAVE: + case AMDGPU::SI_SPILL_A256_CFI_SAVE: case AMDGPU::SI_SPILL_A256_RESTORE: case AMDGPU::SI_SPILL_AV256_SAVE: + case AMDGPU::SI_SPILL_AV256_CFI_SAVE: case AMDGPU::SI_SPILL_AV256_RESTORE: return 8; case AMDGPU::SI_SPILL_S224_SAVE: + case AMDGPU::SI_SPILL_S224_CFI_SAVE: case AMDGPU::SI_SPILL_S224_RESTORE: case AMDGPU::SI_SPILL_V224_SAVE: + case AMDGPU::SI_SPILL_V224_CFI_SAVE: case AMDGPU::SI_SPILL_V224_RESTORE: case AMDGPU::SI_SPILL_A224_SAVE: + case AMDGPU::SI_SPILL_A224_CFI_SAVE: case AMDGPU::SI_SPILL_A224_RESTORE: case AMDGPU::SI_SPILL_AV224_SAVE: + case AMDGPU::SI_SPILL_AV224_CFI_SAVE: case AMDGPU::SI_SPILL_AV224_RESTORE: return 7; case AMDGPU::SI_SPILL_S192_SAVE: + case AMDGPU::SI_SPILL_S192_CFI_SAVE: case AMDGPU::SI_SPILL_S192_RESTORE: case AMDGPU::SI_SPILL_V192_SAVE: + case AMDGPU::SI_SPILL_V192_CFI_SAVE: case AMDGPU::SI_SPILL_V192_RESTORE: case AMDGPU::SI_SPILL_A192_SAVE: + case AMDGPU::SI_SPILL_A192_CFI_SAVE: case AMDGPU::SI_SPILL_A192_RESTORE: case AMDGPU::SI_SPILL_AV192_SAVE: + case AMDGPU::SI_SPILL_AV192_CFI_SAVE: case AMDGPU::SI_SPILL_AV192_RESTORE: return 6; case AMDGPU::SI_SPILL_S160_SAVE: + case AMDGPU::SI_SPILL_S160_CFI_SAVE: case AMDGPU::SI_SPILL_S160_RESTORE: case AMDGPU::SI_SPILL_V160_SAVE: + case AMDGPU::SI_SPILL_V160_CFI_SAVE: case AMDGPU::SI_SPILL_V160_RESTORE: case AMDGPU::SI_SPILL_A160_SAVE: + case AMDGPU::SI_SPILL_A160_CFI_SAVE: case AMDGPU::SI_SPILL_A160_RESTORE: case AMDGPU::SI_SPILL_AV160_SAVE: + case AMDGPU::SI_SPILL_AV160_CFI_SAVE: case AMDGPU::SI_SPILL_AV160_RESTORE: return 5; case AMDGPU::SI_SPILL_S128_SAVE: + case AMDGPU::SI_SPILL_S128_CFI_SAVE: case AMDGPU::SI_SPILL_S128_RESTORE: case AMDGPU::SI_SPILL_V128_SAVE: + case AMDGPU::SI_SPILL_V128_CFI_SAVE: case AMDGPU::SI_SPILL_V128_RESTORE: case AMDGPU::SI_SPILL_A128_SAVE: + case AMDGPU::SI_SPILL_A128_CFI_SAVE: case AMDGPU::SI_SPILL_A128_RESTORE: case AMDGPU::SI_SPILL_AV128_SAVE: + case AMDGPU::SI_SPILL_AV128_CFI_SAVE: case AMDGPU::SI_SPILL_AV128_RESTORE: return 4; case AMDGPU::SI_SPILL_S96_SAVE: + case AMDGPU::SI_SPILL_S96_CFI_SAVE: case AMDGPU::SI_SPILL_S96_RESTORE: case AMDGPU::SI_SPILL_V96_SAVE: + case AMDGPU::SI_SPILL_V96_CFI_SAVE: case AMDGPU::SI_SPILL_V96_RESTORE: case AMDGPU::SI_SPILL_A96_SAVE: + case AMDGPU::SI_SPILL_A96_CFI_SAVE: case AMDGPU::SI_SPILL_A96_RESTORE: case AMDGPU::SI_SPILL_AV96_SAVE: + case AMDGPU::SI_SPILL_AV96_CFI_SAVE: case AMDGPU::SI_SPILL_AV96_RESTORE: return 3; case AMDGPU::SI_SPILL_S64_SAVE: + case AMDGPU::SI_SPILL_S64_CFI_SAVE: case AMDGPU::SI_SPILL_S64_RESTORE: case AMDGPU::SI_SPILL_V64_SAVE: + case AMDGPU::SI_SPILL_V64_CFI_SAVE: case AMDGPU::SI_SPILL_V64_RESTORE: case AMDGPU::SI_SPILL_A64_SAVE: + case AMDGPU::SI_SPILL_A64_CFI_SAVE: case AMDGPU::SI_SPILL_A64_RESTORE: case AMDGPU::SI_SPILL_AV64_SAVE: + case AMDGPU::SI_SPILL_AV64_CFI_SAVE: case AMDGPU::SI_SPILL_AV64_RESTORE: return 2; case AMDGPU::SI_SPILL_S32_SAVE: + case AMDGPU::SI_SPILL_S32_CFI_SAVE: case AMDGPU::SI_SPILL_S32_RESTORE: case AMDGPU::SI_SPILL_V32_SAVE: + case AMDGPU::SI_SPILL_V32_CFI_SAVE: case AMDGPU::SI_SPILL_V32_RESTORE: case AMDGPU::SI_SPILL_A32_SAVE: + case AMDGPU::SI_SPILL_A32_CFI_SAVE: case AMDGPU::SI_SPILL_A32_RESTORE: case AMDGPU::SI_SPILL_AV32_SAVE: + case AMDGPU::SI_SPILL_AV32_CFI_SAVE: case AMDGPU::SI_SPILL_AV32_RESTORE: case AMDGPU::SI_SPILL_WWM_V32_SAVE: case AMDGPU::SI_SPILL_WWM_V32_RESTORE: @@ -1386,14 +1446,14 @@ static int getOffenMUBUFLoad(unsigned Opc) { } } -static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - int Index, unsigned Lane, - unsigned ValueReg, bool IsKill) { +static MachineInstrBuilder +spillVGPRtoAGPR(const GCNSubtarget &ST, MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, int Index, unsigned Lane, + unsigned ValueReg, bool IsKill, bool NeedsCFI) { MachineFunction *MF = MBB.getParent(); SIMachineFunctionInfo *MFI = MF->getInfo(); const SIInstrInfo *TII = ST.getInstrInfo(); + const SIFrameLowering *TFL = ST.getFrameLowering(); MCPhysReg Reg = MFI->getVGPRToAGPRSpill(Index, Lane); @@ -1416,6 +1476,8 @@ static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST, auto CopyMIB = BuildMI(MBB, MI, DL, TII->get(AMDGPU::COPY), Dst) .addReg(Src, getKillRegState(IsKill)); CopyMIB->setAsmPrinterFlag(MachineInstr::ReloadReuse); + if (NeedsCFI) + TFL->buildCFIForVRegToVRegSpill(MBB, MI, DL, Src, Dst); return CopyMIB; } unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 @@ -1424,6 +1486,8 @@ static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST, auto MIB = BuildMI(MBB, MI, DL, TII->get(Opc), Dst) .addReg(Src, getKillRegState(IsKill)); MIB->setAsmPrinterFlag(MachineInstr::ReloadReuse); + if (NeedsCFI) + TFL->buildCFIForVRegToVRegSpill(MBB, MI, DL, Src, Dst); return MIB; } @@ -1446,7 +1510,8 @@ static bool buildMUBUFOffsetLoadStore(const GCNSubtarget &ST, return false; const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); - if (spillVGPRtoAGPR(ST, *MBB, MI, Index, 0, Reg->getReg(), false).getInstr()) + if (spillVGPRtoAGPR(ST, *MBB, MI, Index, 0, Reg->getReg(), false, false) + .getInstr()) return true; MachineInstrBuilder NewMI = @@ -1511,12 +1576,13 @@ void SIRegisterInfo::buildSpillLoadStore( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, MCRegister ScratchOffsetReg, int64_t InstOffset, MachineMemOperand *MMO, - RegScavenger *RS, LiveRegUnits *LiveUnits) const { - assert((!RS || !LiveUnits) && "Only RS or LiveUnits can be set but not both"); + RegScavenger *RS, LiveRegUnits *LiveUnits, bool NeedsCFI) const { + assert((!RS || !LiveUnits) && "Only RS or LiveRegs can be set but not both"); MachineFunction *MF = MBB.getParent(); const SIInstrInfo *TII = ST.getInstrInfo(); const MachineFrameInfo &MFI = MF->getFrameInfo(); + const SIFrameLowering *TFL = ST.getFrameLowering(); const SIMachineFunctionInfo *FuncInfo = MF->getInfo(); const MCInstrDesc *Desc = &TII->get(LoadStoreOp); @@ -1548,6 +1614,7 @@ void SIRegisterInfo::buildSpillLoadStore( int64_t MaxOffset = Offset + Size + RemSize - EltSize; int64_t ScratchOffsetRegDelta = 0; + int64_t AdditionalCFIOffset = 0; if (IsFlat && EltSize > 4) { LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize); @@ -1660,6 +1727,7 @@ void SIRegisterInfo::buildSpillLoadStore( Scavenged = true; } + AdditionalCFIOffset = Offset; // We currently only support spilling VGPRs to EltSize boundaries, meaning // we can simplify the adjustment of Offset here to just scale with // WavefrontSize. @@ -1762,7 +1830,8 @@ void SIRegisterInfo::buildSpillLoadStore( Register Sub = IsSubReg ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) : ValueReg; - auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill); + auto MIB = + spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill, NeedsCFI); if (!MIB.getInstr()) break; if (NeedSuperRegDef || (IsSubReg && IsStore && Lane == LaneS && IsFirstSubReg)) { @@ -1863,6 +1932,18 @@ void SIRegisterInfo::buildSpillLoadStore( MIB.addImm(0); // swz MIB.addMemOperand(NewMMO); + if (IsStore && NeedsCFI) { + if (TII->isBlockLoadStore(LoadStoreOp)) { + assert(RegOffset == 0 && + "expected whole register block to be treated as single element"); + buildCFIForBlockCSRStore(MBB, MI, ValueReg, Offset); + } else { + TFL->buildCFIForVGPRToVMEMSpill( + MBB, MI, DebugLoc(), SubReg, + (Offset + RegOffset) * ST.getWavefrontSize() + AdditionalCFIOffset); + } + } + if (!IsAGPR && NeedSuperRegDef) MIB.addReg(ValueReg, RegState::ImplicitDefine); @@ -1938,6 +2019,31 @@ void SIRegisterInfo::addImplicitUsesForBlockCSRLoad(MachineInstrBuilder &MIB, MIB.addUse(BaseVGPR + RegOffset, RegState::Implicit); } +void SIRegisterInfo::buildCFIForBlockCSRStore(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + Register BlockReg, + int64_t Offset) const { + const MachineFunction *MF = MBB.getParent(); + const SIMachineFunctionInfo *FuncInfo = MF->getInfo(); + uint32_t Mask = FuncInfo->getMaskForVGPRBlockOps(BlockReg); + Register BaseVGPR = getSubReg(BlockReg, AMDGPU::sub0); + for (unsigned RegOffset = 0; RegOffset < 32; ++RegOffset) { + Register VGPR = BaseVGPR + RegOffset; + if (Mask & (1 << RegOffset)) { + assert(isCalleeSavedPhysReg(VGPR, *MF)); + ST.getFrameLowering()->buildCFIForVGPRToVMEMSpill( + MBB, MBBI, DebugLoc(), VGPR, + (Offset + RegOffset) * ST.getWavefrontSize()); + } else if (isCalleeSavedPhysReg(VGPR, *MF)) { + // FIXME: This is a workaround for the fact that FrameLowering's + // emitPrologueEntryCFI considers the block load to clobber all registers + // in the block. + ST.getFrameLowering()->buildCFIForSameValue(MBB, MBBI, DebugLoc(), + BaseVGPR + RegOffset); + } + } +} + void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill) const { @@ -1974,7 +2080,7 @@ void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index, RegScavenger *RS, SlotIndexes *Indexes, LiveIntervals *LIS, bool OnlyToVGPR, - bool SpillToPhysVGPRLane) const { + bool SpillToPhysVGPRLane, bool NeedsCFI) const { assert(!MI->getOperand(0).isUndef() && "undef spill should have been deleted earlier"); @@ -1987,6 +2093,8 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index, if (OnlyToVGPR && !SpillToVGPR) return false; + const SIFrameLowering *TFL = ST.getFrameLowering(); + assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() && SB.SuperReg != SB.MFI.getFrameOffsetReg())); @@ -2019,11 +2127,27 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index, .addReg(SubReg, getKillRegState(UseKill)) .addImm(Spill.Lane) .addReg(Spill.VGPR); + + MachineInstr *CFI = nullptr; + if (NeedsCFI) { + if (SB.SuperReg == SB.TRI.getReturnAddressReg(SB.MF)) { + if (i == e - 1) + CFI = TFL->buildCFIForSGPRToVGPRSpill(*SB.MBB, MI, DebugLoc(), + AMDGPU::PC_REG, VGPRSpills); + } else { + CFI = TFL->buildCFIForSGPRToVGPRSpill(*SB.MBB, MI, DebugLoc(), SubReg, + Spill.VGPR, Spill.Lane); + } + } + if (Indexes) { if (IsFirstSubreg) Indexes->replaceMachineInstrInMaps(*MI, *MIB); else Indexes->insertMachineInstrInMaps(*MIB); + + if (CFI) + Indexes->insertMachineInstrInMaps(*CFI); } if (IsFirstSubreg && SB.NumSubRegs > 1) { @@ -2088,6 +2212,18 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index, // Write out VGPR SB.readWriteTmpVGPR(Offset, /*IsLoad*/ false); + + // TODO: Implement CFI for SpillToVMEM for all scenarios. + MachineInstr *CFI = nullptr; + if (NeedsCFI && SB.SuperReg == SB.TRI.getReturnAddressReg(SB.MF)) { + int64_t CFIOffset = (Offset * SB.EltSize + + SB.MF.getFrameInfo().getObjectOffset(Index)) * + ST.getWavefrontSize(); + CFI = TFL->buildCFIForSGPRToVMEMSpill(*SB.MBB, MI, DebugLoc(), + AMDGPU::PC_REG, CFIOffset); + } + if (Indexes && CFI) + Indexes->insertMachineInstrInMaps(*CFI); } SB.restore(); @@ -2259,7 +2395,20 @@ bool SIRegisterInfo::spillEmergencySGPR(MachineBasicBlock::iterator MI, bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex( MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes, LiveIntervals *LIS, bool SpillToPhysVGPRLane) const { + bool NeedsCFI = false; switch (MI->getOpcode()) { + case AMDGPU::SI_SPILL_S1024_CFI_SAVE: + case AMDGPU::SI_SPILL_S512_CFI_SAVE: + case AMDGPU::SI_SPILL_S256_CFI_SAVE: + case AMDGPU::SI_SPILL_S224_CFI_SAVE: + case AMDGPU::SI_SPILL_S192_CFI_SAVE: + case AMDGPU::SI_SPILL_S160_CFI_SAVE: + case AMDGPU::SI_SPILL_S128_CFI_SAVE: + case AMDGPU::SI_SPILL_S96_CFI_SAVE: + case AMDGPU::SI_SPILL_S64_CFI_SAVE: + case AMDGPU::SI_SPILL_S32_CFI_SAVE: + NeedsCFI = true; + LLVM_FALLTHROUGH; case AMDGPU::SI_SPILL_S1024_SAVE: case AMDGPU::SI_SPILL_S512_SAVE: case AMDGPU::SI_SPILL_S384_SAVE: @@ -2274,7 +2423,8 @@ bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex( case AMDGPU::SI_SPILL_S96_SAVE: case AMDGPU::SI_SPILL_S64_SAVE: case AMDGPU::SI_SPILL_S32_SAVE: - return spillSGPR(MI, FI, RS, Indexes, LIS, true, SpillToPhysVGPRLane); + return spillSGPR(MI, FI, RS, Indexes, LIS, true, SpillToPhysVGPRLane, + NeedsCFI); case AMDGPU::SI_SPILL_S1024_RESTORE: case AMDGPU::SI_SPILL_S512_RESTORE: case AMDGPU::SI_SPILL_S384_RESTORE: @@ -2317,8 +2467,23 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, ? getBaseRegister() : getFrameRegister(*MF); + bool NeedsCFI = false; + switch (MI->getOpcode()) { // SGPR register spill + case AMDGPU::SI_SPILL_S1024_CFI_SAVE: + case AMDGPU::SI_SPILL_S512_CFI_SAVE: + case AMDGPU::SI_SPILL_S256_CFI_SAVE: + case AMDGPU::SI_SPILL_S224_CFI_SAVE: + case AMDGPU::SI_SPILL_S192_CFI_SAVE: + case AMDGPU::SI_SPILL_S160_CFI_SAVE: + case AMDGPU::SI_SPILL_S128_CFI_SAVE: + case AMDGPU::SI_SPILL_S96_CFI_SAVE: + case AMDGPU::SI_SPILL_S64_CFI_SAVE: + case AMDGPU::SI_SPILL_S32_CFI_SAVE: { + NeedsCFI = true; + LLVM_FALLTHROUGH; + } case AMDGPU::SI_SPILL_S1024_SAVE: case AMDGPU::SI_SPILL_S512_SAVE: case AMDGPU::SI_SPILL_S384_SAVE: @@ -2333,7 +2498,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, case AMDGPU::SI_SPILL_S96_SAVE: case AMDGPU::SI_SPILL_S64_SAVE: case AMDGPU::SI_SPILL_S32_SAVE: { - return spillSGPR(MI, Index, RS); + return spillSGPR(MI, Index, RS, nullptr, nullptr, false, false, NeedsCFI); } // SGPR register restore @@ -2355,13 +2520,40 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, } // VGPR register spill - case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE: { - // Put mask into M0. - BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), - AMDGPU::M0) - .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::mask)); - [[fallthrough]]; - } + case AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE: + case AMDGPU::SI_SPILL_V1024_CFI_SAVE: + case AMDGPU::SI_SPILL_V512_CFI_SAVE: + case AMDGPU::SI_SPILL_V256_CFI_SAVE: + case AMDGPU::SI_SPILL_V224_CFI_SAVE: + case AMDGPU::SI_SPILL_V192_CFI_SAVE: + case AMDGPU::SI_SPILL_V160_CFI_SAVE: + case AMDGPU::SI_SPILL_V128_CFI_SAVE: + case AMDGPU::SI_SPILL_V96_CFI_SAVE: + case AMDGPU::SI_SPILL_V64_CFI_SAVE: + case AMDGPU::SI_SPILL_V32_CFI_SAVE: + case AMDGPU::SI_SPILL_A1024_CFI_SAVE: + case AMDGPU::SI_SPILL_A512_CFI_SAVE: + case AMDGPU::SI_SPILL_A256_CFI_SAVE: + case AMDGPU::SI_SPILL_A224_CFI_SAVE: + case AMDGPU::SI_SPILL_A192_CFI_SAVE: + case AMDGPU::SI_SPILL_A160_CFI_SAVE: + case AMDGPU::SI_SPILL_A128_CFI_SAVE: + case AMDGPU::SI_SPILL_A96_CFI_SAVE: + case AMDGPU::SI_SPILL_A64_CFI_SAVE: + case AMDGPU::SI_SPILL_A32_CFI_SAVE: + case AMDGPU::SI_SPILL_AV1024_CFI_SAVE: + case AMDGPU::SI_SPILL_AV512_CFI_SAVE: + case AMDGPU::SI_SPILL_AV256_CFI_SAVE: + case AMDGPU::SI_SPILL_AV224_CFI_SAVE: + case AMDGPU::SI_SPILL_AV192_CFI_SAVE: + case AMDGPU::SI_SPILL_AV160_CFI_SAVE: + case AMDGPU::SI_SPILL_AV128_CFI_SAVE: + case AMDGPU::SI_SPILL_AV96_CFI_SAVE: + case AMDGPU::SI_SPILL_AV64_CFI_SAVE: + case AMDGPU::SI_SPILL_AV32_CFI_SAVE: + NeedsCFI = true; + LLVM_FALLTHROUGH; + case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE: case AMDGPU::SI_SPILL_V1024_SAVE: case AMDGPU::SI_SPILL_V512_SAVE: case AMDGPU::SI_SPILL_V384_SAVE: @@ -2407,6 +2599,16 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, case AMDGPU::SI_SPILL_AV32_SAVE: case AMDGPU::SI_SPILL_WWM_V32_SAVE: case AMDGPU::SI_SPILL_WWM_AV32_SAVE: { + assert( + MI->getOpcode() != AMDGPU::SI_BLOCK_SPILL_V1024_SAVE && + "block spill does not currenty support spilling non-CSR registers"); + + if (MI->getOpcode() == AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE) + // Put mask into M0. + BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), + AMDGPU::M0) + .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::mask)); + const MachineOperand *VData = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); if (VData->isUndef()) { @@ -2422,7 +2624,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, assert(ST.enableFlatScratch() && "Flat Scratch is not enabled!"); Opc = AMDGPU::SCRATCH_STORE_SHORT_SADDR_t16; } else { - Opc = MI->getOpcode() == AMDGPU::SI_BLOCK_SPILL_V1024_SAVE + Opc = MI->getOpcode() == AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE ? AMDGPU::SCRATCH_STORE_BLOCK_SADDR : ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR : AMDGPU::BUFFER_STORE_DWORD_OFFSET; @@ -2430,14 +2632,14 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, auto *MBB = MI->getParent(); bool IsWWMRegSpill = TII->isWWMRegSpillOpcode(MI->getOpcode()); - if (IsWWMRegSpill) { + if (IsWWMRegSpill){ TII->insertScratchExecCopy(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy(), - RS->isRegUsed(AMDGPU::SCC)); + RS->isRegUsed(AMDGPU::SCC)); } buildSpillLoadStore( *MBB, MI, DL, Opc, Index, VData->getReg(), VData->isKill(), FrameReg, TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), - *MI->memoperands_begin(), RS); + *MI->memoperands_begin(), RS, nullptr, NeedsCFI); MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(*MI, TII)); if (IsWWMRegSpill) TII->restoreExec(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy()); @@ -2515,7 +2717,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, auto *MBB = MI->getParent(); bool IsWWMRegSpill = TII->isWWMRegSpillOpcode(MI->getOpcode()); - if (IsWWMRegSpill) { + if (IsWWMRegSpill){ TII->insertScratchExecCopy(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy(), RS->isRegUsed(AMDGPU::SCC)); } diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 7b91ba7bc581f..fa0de60c11184 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -80,6 +80,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo { return SpillSGPRToVGPR; } + bool isCFISavedRegsSpillEnabled() const; + /// Return the largest available SGPR aligned to \p Align for the register /// class \p RC. MCRegister getAlignedHighSGPRForRC(const MachineFunction &MF, @@ -121,6 +123,13 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo { void addImplicitUsesForBlockCSRLoad(MachineInstrBuilder &MIB, Register BlockReg) const; + // Iterate over all VGPRs in the given BlockReg and emit CFI for each VGPR + // as-needed depending on the (statically known) mask, relative to the given + // base Offset. + void buildCFIForBlockCSRStore(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + Register BlockReg, int64_t Offset) const; + const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override; @@ -154,6 +163,9 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo { bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override; + std::optional getDwarfRegLaneSize(int64_t DwarfReg, + bool isEH) const override; + const TargetRegisterClass * getPointerRegClass(unsigned Kind = 0) const override; @@ -176,8 +188,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo { /// free VGPR lane to spill. bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr, - bool OnlyToVGPR = false, - bool SpillToPhysVGPRLane = false) const; + bool OnlyToVGPR = false, bool SpillToPhysVGPRLane = false, + bool NeedsCFI = false) const; bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr, @@ -459,8 +471,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo { unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, - RegScavenger *RS, - LiveRegUnits *LiveUnits = nullptr) const; + RegScavenger *RS, LiveRegUnits *LiveUnits = nullptr, + bool NeedsCFI = false) const; // Return alignment in register file of first register in a register tuple. unsigned getRegClassAlignmentNumBits(const TargetRegisterClass *RC) const { diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index 4ae2c1ed04dae..717030df9a4c9 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -573,16 +573,16 @@ defm V_DOT2_F32_F16 : VOP3PInst<"v_dot2_f32_f16", let OtherPredicates = [HasDot7Insts] in { defm V_DOT4_U32_U8 : VOP3PInst<"v_dot4_u32_u8", - VOP3P_Profile, int_amdgcn_udot4, 1>; + VOP3P_Profile, int_amdgcn_udot4, 1>; defm V_DOT8_U32_U4 : VOP3PInst<"v_dot8_u32_u4", - VOP3P_Profile, int_amdgcn_udot8, 1>; + VOP3P_Profile, int_amdgcn_udot8, 1>; } // End OtherPredicates = [HasDot7Insts] let OtherPredicates = [HasDot1Insts] in { defm V_DOT4_I32_I8 : VOP3PInst<"v_dot4_i32_i8", - VOP3P_Profile, int_amdgcn_sdot4, 1>; + VOP3P_Profile, int_amdgcn_sdot4, 1>; defm V_DOT8_I32_I4 : VOP3PInst<"v_dot8_i32_i4", - VOP3P_Profile, int_amdgcn_sdot8, 1>; + VOP3P_Profile, int_amdgcn_sdot8, 1>; } // End OtherPredicates = [HasDot1Insts] def DOT2_BF16_Profile @@ -601,7 +601,7 @@ defm V_DOT2_F32_BF16 : VOP3PInst<"v_dot2_f32_bf16", DOT2_BF16_Profile, multiclass VOP3PDOTIUInst { let IsDOT = 1 in - defm NAME : VOP3PInst, + defm NAME : VOP3PInst, null_frag, 1>; // Dot-iu instructions consider input as signed if imod neg bits are set. Thus // Dot-iu Intrinsics have extra operands and require separate codegen pattern. diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index 8325c628d68d6..4e63ad54bef27 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -1517,13 +1517,12 @@ class VOP3Features { bit IsMAI = MAI; } -def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; -def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; -def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; -def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; -def VOP3_PACKED_NO_OPSEL : VOP3Features<1, 0, 1, 0>; -def VOP3_MAI : VOP3Features<0, 0, 0, 1>; -def VOP3_OPSEL_ONLY : VOP3Features<0, 1, 0, 0>; +def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; +def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; +def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; +def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; +def VOP3_MAI : VOP3Features<0, 0, 0, 1>; +def VOP3_OPSEL_ONLY : VOP3Features<0, 1, 0, 0>; // Packed is misleading, but it enables the appropriate op_sel // modifiers. diff --git a/llvm/lib/Target/X86/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/X86/MCTargetDesc/CMakeLists.txt index f2e7d43fc17f6..bf741506a5447 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/CMakeLists.txt +++ b/llvm/lib/Target/X86/MCTargetDesc/CMakeLists.txt @@ -28,3 +28,4 @@ add_llvm_component_library(LLVMX86Desc ADD_TO_COMPONENT X86 ) +set_source_files_properties(X86MCCodeEmitter.cpp PROPERTIES COMPILE_FLAGS "-O2") diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index c8d193887d92f..c25f4caca914c 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -1459,11 +1459,8 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512VP2INTERSECT); - // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't - // return all 0s for invalid subleaves so check the limit. bool HasLeaf7Subleaf1 = - HasLeaf7 && EAX >= 1 && - !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); + MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512BF16); @@ -2139,11 +2136,8 @@ StringMap sys::getHostCPUFeatures() { Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save; Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave; Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave; - // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't - // return all 0s for invalid subleaves so check the limit. bool HasLeaf7Subleaf1 = - HasLeaf7 && EAX >= 1 && - !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); + MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1); Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1); Features["sm4"] = HasLeaf7Subleaf1 && ((EAX >> 2) & 1); diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp index c89af688a69ca..632b44c3cf635 100644 --- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp @@ -624,10 +624,10 @@ static DIType *solveDIType(DIBuilder &Builder, Type *Ty, // struct Node { // Node* ptr; // }; - RetType = - Builder.createPointerType(nullptr, Layout.getTypeSizeInBits(Ty), - Layout.getABITypeAlign(Ty).value() * CHAR_BIT, - /*DWARFAddressSpace=*/std::nullopt, Name); + RetType = Builder.createPointerType( + nullptr, Layout.getTypeSizeInBits(Ty), + Layout.getABITypeAlign(Ty).value() * CHAR_BIT, + /*DWARFAddressSpace=*/std::nullopt, dwarf::DW_MSPACE_LLVM_none, Name); } else if (Ty->isStructTy()) { auto *DIStruct = Builder.createStructType( Scope, Name, Scope->getFile(), LineNum, Layout.getTypeSizeInBits(Ty), diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index 50485615a9d4c..1a9df01f236aa 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -10625,14 +10625,24 @@ struct AACallEdgesCallSite : public AACallEdgesImpl { } return Change; } - +#ifndef AAIndirectCallInfo_nolonger_breaks_snap_miteams + // Process callee metadata if available. + if (auto *MD = getCtxI()->getMetadata(LLVMContext::MD_callees)) { + for (const auto &Op : MD->operands()) { + Function *Callee = mdconst::dyn_extract_or_null(Op); + if (Callee) + addCalledFunction(Callee, Change); + } + return Change; + } +#else if (CB->isIndirectCall()) if (auto *IndirectCallAA = A.getAAFor( *this, getIRPosition(), DepClassTy::OPTIONAL)) if (IndirectCallAA->foreachCallee( [&](Function *Fn) { return VisitValue(*Fn, CB); })) return Change; - +#endif // The most simple case. ProcessCalledOperand(CB->getCalledOperand(), CB); diff --git a/llvm/lib/Transforms/IPO/IROutliner.cpp b/llvm/lib/Transforms/IPO/IROutliner.cpp index fdf0c3ac8007d..e3e31befdbfd2 100644 --- a/llvm/lib/Transforms/IPO/IROutliner.cpp +++ b/llvm/lib/Transforms/IPO/IROutliner.cpp @@ -740,6 +740,9 @@ static void moveFunctionData(Function &Old, Function &New, continue; } + // From this point we are only handling call instructions. + CallInst *CI = cast(&Val); + // Edit the scope of called functions inside of outlined functions. if (DISubprogram *SP = New.getSubprogram()) { DILocation *DI = DILocation::get(New.getContext(), 0, 0, SP); diff --git a/llvm/lib/Transforms/IPO/Internalize.cpp b/llvm/lib/Transforms/IPO/Internalize.cpp index c2b8a6257ae6f..4e4a489bfdffa 100644 --- a/llvm/lib/Transforms/IPO/Internalize.cpp +++ b/llvm/lib/Transforms/IPO/Internalize.cpp @@ -232,7 +232,8 @@ bool InternalizePass::internalizeModule(Module &M) { AlwaysPreserved.insert("__stack_chk_guard"); // Preserve the RPC interface for GPU host callbacks when internalizing. - if (M.getTargetTriple().isNVPTX()) + if (M.getTargetTriple().isNVPTX() || + M.getTargetTriple().isAMDGPU()) AlwaysPreserved.insert("__llvm_rpc_client"); // Mark all functions not in the api as internal. diff --git a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp index d7eb745c81317..8b1968343416e 100644 --- a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp +++ b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp @@ -111,7 +111,7 @@ static cl::opt DisableOpenMPOptFolding( static cl::opt DisableOpenMPOptStateMachineRewrite( "openmp-opt-disable-state-machine-rewrite", cl::desc("Disable OpenMP optimizations that replace the state machine."), - cl::Hidden, cl::init(false)); + cl::Hidden, cl::init(true)); static cl::opt DisableOpenMPOptBarrierElimination( "openmp-opt-disable-barrier-elimination", @@ -4290,6 +4290,33 @@ struct AAKernelInfoFunction : AAKernelInfo { ConstantInt::get(ExecModeC->getIntegerType(), ExecModeVal | OMP_TGT_EXEC_MODE_GENERIC_SPMD)); + // The global variable needs to be set too. + GlobalVariable *ExecMode = Kernel->getParent()->getGlobalVariable( + (Kernel->getName() + "_exec_mode").str()); + + if (!ExecMode) { // likely fortran missing exec mode + auto Remark = [&](OptimizationRemark OR) { + return OR << "Could not transform generic-mode kernel to SPMD-mode. Missing mode."; + }; + A.emitRemark(KernelInitCB, "OMP122", Remark); + return false; + } + assert(ExecMode && "Kernel without exec mode?"); + assert(ExecMode->getInitializer() && "ExecMode doesn't have initializer!"); + + // Set the global exec mode flag to indicate SPMD-Generic mode. + assert(isa(ExecMode->getInitializer()) && + "ExecMode is not an integer!"); + + // Adjust the global exec mode flag that tells the runtime what mode this + // kernel is executed in. + assert(cast(ExecMode->getInitializer())->getSExtValue() == + OMP_TGT_EXEC_MODE_GENERIC && + "Initially non-SPMD kernel has SPMD exec mode!"); + ExecMode->setInitializer( + ConstantInt::get(ExecMode->getInitializer()->getType(), + ExecModeVal | OMP_TGT_EXEC_MODE_GENERIC_SPMD)); + ++NumOpenMPTargetRegionKernelsSPMD; auto Remark = [&](OptimizationRemark OR) { @@ -5575,11 +5602,13 @@ void OpenMPOpt::registerAAsForFunction(Attributor &A, const Function &F) { IRPosition::value(*LI->getPointerOperand())); continue; } +#if 0 // fixme snap2 mi-teams nest_call_par2 if (auto *CI = dyn_cast(&I)) { if (CI->isIndirectCall()) A.getOrCreateAAFor( IRPosition::callsite_function(*CI)); } +#endif if (auto *SI = dyn_cast(&I)) { A.getOrCreateAAFor(IRPosition::value(*SI)); A.getOrCreateAAFor( @@ -5788,7 +5817,8 @@ PreservedAnalyses OpenMPOptPass::run(Module &M, ModuleAnalysisManager &AM) { bool PostLink = LTOPhase == ThinOrFullLTOPhase::FullLTOPostLink || LTOPhase == ThinOrFullLTOPhase::ThinLTOPostLink || - LTOPhase == ThinOrFullLTOPhase::ThinLTOPreLink; + LTOPhase == ThinOrFullLTOPhase::ThinLTOPreLink || + LTOPhase == ThinOrFullLTOPhase::CustomLTOPostLink; OMPInformationCache InfoCache(M, AG, Allocator, /*CGSCC*/ nullptr, PostLink); unsigned MaxFixpointIterations = @@ -5866,7 +5896,8 @@ PreservedAnalyses OpenMPOptCGSCCPass::run(LazyCallGraph::SCC &C, bool PostLink = LTOPhase == ThinOrFullLTOPhase::FullLTOPostLink || LTOPhase == ThinOrFullLTOPhase::ThinLTOPostLink || - LTOPhase == ThinOrFullLTOPhase::ThinLTOPreLink; + LTOPhase == ThinOrFullLTOPhase::ThinLTOPreLink || + LTOPhase == ThinOrFullLTOPhase::CustomLTOPostLink; SetVector Functions(llvm::from_range, SCC); OMPInformationCache InfoCache(*(Functions.back()->getParent()), AG, Allocator, /*CGSCC*/ &Functions, PostLink); diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp index 7c364f86fb0e8..400efa94789d3 100644 --- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp @@ -2644,6 +2644,9 @@ void ModuleAddressSanitizer::instrumentGlobals(IRBuilder<> &IRB, // zero so we can copy the metadata over as is. NewGlobal->copyMetadata(G, 0); + // Attach "SanitizedPaddedGlobal" attribute to the new global. + NewGlobal->addAttribute(Attribute::SanitizedPaddedGlobal); + Value *Indices2[2]; Indices2[0] = IRB.getInt32(0); Indices2[1] = IRB.getInt32(0); diff --git a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp index 7795cce9d9d3c..8f96f9e8aea30 100644 --- a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp +++ b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp @@ -23,6 +23,7 @@ #include "llvm/Analysis/CFG.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/TargetLibraryInfo.h" +#include "llvm/BinaryFormat/Dwarf.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/BasicBlock.h" #include "llvm/IR/CFG.h" @@ -1718,8 +1719,8 @@ InstrLowerer::getOrCreateRegionCounters(InstrProfCntrInstBase *Inc) { SP, CounterPtr->getName(), /*LinkageName=*/StringRef(), SP->getFile(), /*LineNo=*/0, DB.createUnspecifiedType("Profile Data Type"), CounterPtr->hasLocalLinkage(), /*IsDefined=*/true, /*Expr=*/nullptr, - /*Decl=*/nullptr, /*TemplateParams=*/nullptr, /*AlignInBits=*/0, - Annotations); + /*Decl=*/nullptr, /*TemplateParams=*/nullptr, + llvm::dwarf::DW_MSPACE_LLVM_none, /*AlignInBits=*/0, Annotations); CounterPtr->addDebugInfo(DICounter); DB.finalize(); } diff --git a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp index 3ad87545953ff..9d494b049c7fb 100644 --- a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp +++ b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp @@ -174,6 +174,7 @@ class InferAddressSpaces : public FunctionPass { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); AU.addPreserved(); + AU.addRequired(); AU.addRequired(); AU.addRequired(); } @@ -261,6 +262,7 @@ INITIALIZE_PASS_BEGIN(InferAddressSpaces, DEBUG_TYPE, "Infer address spaces", false, false) INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker) INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass) +INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) INITIALIZE_PASS_END(InferAddressSpaces, DEBUG_TYPE, "Infer address spaces", false, false) @@ -871,6 +873,15 @@ Value *InferAddressSpacesImpl::cloneValueWithNewAddressSpace( NewI->setDebugLoc(I->getDebugLoc()); } } + // Move debug markers to the inferred aspace, unless they already refer + // directly to an alloca. The alloca should reflect the "true" location + // anyway, and if it is optimized out later and infer-address-spaces runs + // again we should be no worse off. + if (NewV && !isa(I)) { + Instruction *DomPoint = + isa(NewV) ? cast(NewV) : I; + replaceAllDbgUsesWith(*I, *NewV, *DomPoint, *DT); + } return NewV; } @@ -1411,10 +1422,9 @@ bool InferAddressSpaces::runOnFunction(Function &F) { if (skipFunction(F)) return false; - auto *DTWP = getAnalysisIfAvailable(); - DominatorTree *DT = DTWP ? &DTWP->getDomTree() : nullptr; return InferAddressSpacesImpl( - getAnalysis().getAssumptionCache(F), DT, + getAnalysis().getAssumptionCache(F), + &getAnalysis().getDomTree(), &getAnalysis().getTTI(F), FlatAddrSpace) .run(F); @@ -1433,7 +1443,7 @@ PreservedAnalyses InferAddressSpacesPass::run(Function &F, FunctionAnalysisManager &AM) { bool Changed = InferAddressSpacesImpl(AM.getResult(F), - AM.getCachedResult(F), + &AM.getResult(F), &AM.getResult(F), FlatAddrSpace) .run(F); if (Changed) { diff --git a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp index 2bda9d83236e8..e7c2a196243fa 100644 --- a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp +++ b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp @@ -828,7 +828,7 @@ shouldPragmaUnroll(Loop *L, const PragmaInfo &PInfo, } if (PInfo.PragmaEnableUnroll && !TripCount && MaxTripCount && - MaxTripCount <= UP.MaxUpperBound) + MaxTripCount <= UnrollMaxUpperBound) return MaxTripCount; // if didn't return until here, should continue to other priorties diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp index 5c60fad6f91aa..491685f9a032b 100644 --- a/llvm/lib/Transforms/Scalar/SROA.cpp +++ b/llvm/lib/Transforms/Scalar/SROA.cpp @@ -5444,6 +5444,15 @@ static DIExpression *createOrReplaceFragment(const DIExpression *Expr, bool HasFragment = false; bool HasBitExtract = false; + if (auto NewElems = Expr->getNewElementsRef()) { + DIExprBuilder B(Expr->getContext()); + for (DIOp::Variant Op : *NewElems) + if (!std::holds_alternative(Op)) + B.append(Op); + B.append(Frag.OffsetInBits, Frag.SizeInBits); + return B.intoExpression(); + } + for (auto &Op : Expr->expr_ops()) { if (Op.getOp() == dwarf::DW_OP_LLVM_fragment) { HasFragment = true; @@ -5553,6 +5562,19 @@ insertNewDbgInst(DIBuilder &DIB, DbgVariableRecord *Orig, AllocaInst *NewAddr, (void)NewAssign; } +static bool isNoOffsetDIOpExpr(const DIExpression *Expr) { + auto OptNewOps = Expr->getNewElementsRef(); + if (!OptNewOps) + return false; + + ArrayRef NewOps = *OptNewOps; + if (!NewOps.empty() && std::holds_alternative(NewOps.back())) + NewOps = NewOps.drop_back(); + + return NewOps.size() == 2 && std::holds_alternative(NewOps[0]) && + std::holds_alternative(NewOps[1]); +} + /// Walks the slices of an alloca and form partitions based on them, /// rewriting each of their uses. bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) { @@ -5666,7 +5688,12 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) { // that come after it. int64_t CurrentExprOffsetInBytes = 0; SmallVector PostOffsetOps; - if (!getAddressExpression(DbgVariable) + const DIExpression *NoOffsetDIOpExpr = nullptr; + if (isNoOffsetDIOpExpr(getAddressExpression(DbgVariable))) { + NoOffsetDIOpExpr = getAddressExpression(DbgVariable); + ArrayRef PoisonElems = NoOffsetDIOpExpr->getElements(); + PostOffsetOps.append(PoisonElems.begin(), PoisonElems.end()); + } else if (!getAddressExpression(DbgVariable) ->extractLeadingOffset(CurrentExprOffsetInBytes, PostOffsetOps)) return; // Couldn't interpret this DIExpression - drop the var. @@ -5727,6 +5754,8 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) { if (OffestFromNewAllocaInBits > 0) { int64_t OffsetInBytes = (OffestFromNewAllocaInBits + 7) / 8; NewExpr = DIExpression::prepend(NewExpr, /*flags=*/0, OffsetInBytes); + } else if (NoOffsetDIOpExpr && OffestFromNewAllocaInBits == 0) { + NewExpr = const_cast(NoOffsetDIOpExpr); } // Remove any existing intrinsics on the new alloca describing diff --git a/llvm/lib/Transforms/Utils/CodeExtractor.cpp b/llvm/lib/Transforms/Utils/CodeExtractor.cpp index 5ba6f95f5fae8..40de78a1d6e31 100644 --- a/llvm/lib/Transforms/Utils/CodeExtractor.cpp +++ b/llvm/lib/Transforms/Utils/CodeExtractor.cpp @@ -1324,6 +1324,7 @@ static void fixupDebugInfoPostExtraction(Function &OldFunc, Function &NewFunc, NewVar = DIB.createAutoVariable( NewScope, OldVar->getName(), OldVar->getFile(), OldVar->getLine(), OldVar->getType(), /*AlwaysPreserve=*/false, DINode::FlagZero, + OldVar->getDWARFMemorySpace(), OldVar->getAlignInBits()); } return cast(NewVar); diff --git a/llvm/lib/Transforms/Utils/Debugify.cpp b/llvm/lib/Transforms/Utils/Debugify.cpp index 2923633f29d7a..cd3afd7ba3cfa 100644 --- a/llvm/lib/Transforms/Utils/Debugify.cpp +++ b/llvm/lib/Transforms/Utils/Debugify.cpp @@ -64,6 +64,10 @@ cl::opt DebugifyLevel( "Locations and Variables")), cl::init(Level::LocationsAndVariables)); +cl::opt DebugifyDIOpDIExprs( + "debugify-diop-diexprs", + cl::desc("Generate DIOp-based DIExpressions in debugify"), cl::init(false)); + raw_ostream &dbg() { return Quiet ? nulls() : errs(); } #if LLVM_ENABLE_DEBUGLOC_TRACKING_ORIGIN @@ -195,6 +199,24 @@ bool llvm::applyDebugifyMetadata( auto LocalVar = DIB.createAutoVariable(SP, Name, File, Loc->getLine(), getCachedDIType(V->getType()), /*AlwaysPreserve=*/true); + if (DebugifyDIOpDIExprs) { + DIExprBuilder ExprBuilder(Ctx); + ExprBuilder.append(0, V->getType()); + std::optional IRSize; + if (TypeSize IRTypeSize = + M.getDataLayout().getTypeSizeInBits(V->getType())) + if (!IRTypeSize.isScalable()) + IRSize = IRTypeSize.getFixedValue(); + std::optional DISize = LocalVar->getSizeInBits(); + if (IRSize && DISize) { + assert(DISize >= IRSize); + if (DISize > IRSize) + ExprBuilder.append(IntegerType::get(Ctx, *DISize)); + } + DIB.insertDbgValueIntrinsic(V, LocalVar, ExprBuilder.intoExpression(), + Loc, InsertPt); + return; + } DIB.insertDbgValueIntrinsic(V, LocalVar, DIB.createExpression(), Loc, InsertPt); }; diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index 46f29030ddb05..40b53b97cfd64 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -1653,6 +1653,41 @@ static void insertDbgValueOrDbgVariableRecord(DIBuilder &Builder, Value *DV, Instr->getParent()->insertDbgRecordBefore(DVRec, Instr); } +// \p In is an expression that takes a pointer argument. Attempt to create an +// equivalent expression that takes a value by replacing the type field to the +// DIOpArg and adding a DIOpAddrOf after it. +static DIExpression *tryRemoveNewDIExpressionIndirection(DIExpression *In, + Type *ArgType) { + if (!In->holdsNewElements()) + return In; + + auto Elements = In->getNewElementsRef(); + DIExprBuilder ExprBuilder(In->getContext()); + unsigned NumReplacedArgs = 0; + for (auto Iter = Elements->begin(), End = Elements->end(); Iter != End; + ++Iter) { + auto *Arg = std::get_if(&*Iter); + if (!Arg) { + ExprBuilder.append(*Iter); + continue; + } + + ++NumReplacedArgs; + ExprBuilder.append(Arg->getIndex(), ArgType); + auto *PointerTy = dyn_cast(Arg->getResultType()); + if (!PointerTy) + return nullptr; + + auto Next = std::next(Iter); + if (Next == Elements->end() || !std::holds_alternative(*Next)) + ExprBuilder.append(PointerTy->getAddressSpace()); + else + Iter = Next; + } + + return NumReplacedArgs == 1 ? ExprBuilder.intoExpression() : nullptr; +} + static DIExpression *dropInitialDeref(const DIExpression *DIExpr) { int NumEltDropped = DIExpr->getElements()[0] == dwarf::DW_OP_LLVM_arg ? 3 : 1; return DIExpression::get(DIExpr->getContext(), @@ -1669,6 +1704,10 @@ void llvm::ConvertDebugDeclareToDebugValue(DbgVariableRecord *DVR, DebugLoc NewLoc = getDebugValueLoc(DVR); + DIExpr = tryRemoveNewDIExpressionIndirection(DIExpr, DV->getType()); + if (!DIExpr) + return; + // If the alloca describes the variable itself, i.e. the expression in the // dbg.declare doesn't start with a dereference, we can perform the // conversion if the value covers the entire fragment of DII. @@ -1684,6 +1723,11 @@ void llvm::ConvertDebugDeclareToDebugValue(DbgVariableRecord *DVR, bool CanConvert = DIExpr->isDeref() || (!DIExpr->startsWithDeref() && valueCoversEntireFragment(DV->getType(), DVR)); + + // There are no such limitations on new DIExpressions. + if (DIExpr->holdsNewElements()) + CanConvert = true; + if (CanConvert) { insertDbgValueOrDbgVariableRecord(Builder, DV, DIVar, DIExpr, NewLoc, SI->getIterator()); @@ -1725,7 +1769,8 @@ void llvm::ConvertDebugDeclareToDebugValue(DbgVariableRecord *DVR, LoadInst *LI, auto *DIExpr = DVR->getExpression(); assert(DIVar && "Missing variable"); - if (!valueCoversEntireFragment(LI->getType(), DVR)) { + if (!DIExpr->holdsNewElements() && + !valueCoversEntireFragment(LI->getType(), DVR)) { // FIXME: If only referring to a part of the variable described by the // dbg.declare, then we want to insert a DbgVariableRecord for the // corresponding fragment. @@ -1734,6 +1779,10 @@ void llvm::ConvertDebugDeclareToDebugValue(DbgVariableRecord *DVR, LoadInst *LI, return; } + DIExpr = tryRemoveNewDIExpressionIndirection(DIExpr, LI->getType()); + if (!DIExpr) + return; + DebugLoc NewLoc = getDebugValueLoc(DVR); // We are now tracking the loaded value instead of the address. In the @@ -1764,10 +1813,15 @@ void llvm::ConvertDebugDeclareToDebugValue(DbgVariableRecord *DVR, PHINode *APN, auto *DIExpr = DVR->getExpression(); assert(DIVar && "Missing variable"); + DIExpr = tryRemoveNewDIExpressionIndirection(DIExpr, APN->getType()); + if (!DIExpr) + return; + if (PhiHasDebugValue(DIVar, DIExpr, APN)) return; - if (!valueCoversEntireFragment(APN->getType(), DVR)) { + if (!DIExpr->holdsNewElements() && + !valueCoversEntireFragment(APN->getType(), DVR)) { // FIXME: If only referring to a part of the variable described by the // dbg.declare, then we want to insert a DbgVariableRecord for the // corresponding fragment. @@ -1850,15 +1904,29 @@ bool llvm::LowerDbgDeclare(Function &F) { // the variable by dereferencing the alloca. if (!CI->isLifetimeStartOrEnd()) { DebugLoc NewLoc = getDebugValueLoc(DDI); - auto *DerefExpr = - DIExpression::append(DDI->getExpression(), dwarf::DW_OP_deref); - insertDbgValueOrDbgVariableRecord(DIB, AI, DDI->getVariable(), - DerefExpr, NewLoc, - CI->getIterator()); + if (DDI->getExpression()->holdsNewElements()) { + // In DIOp-based DIExpressions it's okay for a dbg.value to + // produce a memory location descriptor, so there isn't any need + // to change the expression. + insertDbgValueOrDbgVariableRecord(DIB, AI, DDI->getVariable(), + DDI->getExpression(), NewLoc, + CI->getIterator()); + } else { + auto *DerefExpr = DIExpression::append(DDI->getExpression(), + dwarf::DW_OP_deref); + insertDbgValueOrDbgVariableRecord(DIB, AI, DDI->getVariable(), + DerefExpr, NewLoc, + CI->getIterator()); + } } } else if (BitCastInst *BI = dyn_cast(U)) { if (BI->getType()->isPointerTy()) WorkList.push_back(BI); + } else if (auto *ASC = dyn_cast(U)) { + // Only look through addrspacecasts if the declare uses new + // expressions (to avoid a difference with upstream). + if (DDI->getExpression()->holdsNewElements()) + WorkList.push_back(ASC); } } } @@ -2034,6 +2102,164 @@ template static void salvageDbgAssignAddress(T *Assign) { } } +/// This is a port of getSalvageOpsForBinOp() to DIOp-based DIExpressions. +static Value * +getNewSalvageOpsForBinOp(BinaryOperator *BI, uint64_t CurrentLocOps, + SmallVectorImpl &Ops, + SmallVectorImpl &AdditionalValues) { + // Handle binary operations with constant integer operands as a special case. + auto *ConstInt = dyn_cast(BI->getOperand(1)); + + if (ConstInt) { + // Values wider than 64 bits cannot be represented within a DIExpression. + if (ConstInt->getBitWidth() > 64) + return nullptr; + Ops.emplace_back(DIOp::Constant(ConstInt)); + } else { + Ops.emplace_back(DIOp::Arg(CurrentLocOps, BI->getOperand(1)->getType())); + AdditionalValues.push_back(BI->getOperand(1)); + } + + switch (BI->getOpcode()) { + default: + // FIXME: Some binary operators aren't representable in DIOp-based + // DIExpressions. + return nullptr; + case Instruction::Add: + Ops.emplace_back(DIOp::Add()); + break; + case Instruction::Sub: + Ops.emplace_back(DIOp::Sub()); + break; + case Instruction::Mul: + Ops.emplace_back(DIOp::Mul()); + break; + case Instruction::SDiv: + Ops.emplace_back(DIOp::Div()); + break; + case Instruction::Shl: + Ops.emplace_back(DIOp::Shl()); + break; + case Instruction::LShr: + Ops.emplace_back(DIOp::LShr()); + break; + case Instruction::AShr: + Ops.emplace_back(DIOp::AShr()); + break; + case Instruction::And: + Ops.emplace_back(DIOp::And()); + break; + case Instruction::Or: + Ops.emplace_back(DIOp::Or()); + break; + case Instruction::Xor: + Ops.emplace_back(DIOp::Xor()); + break; + case Instruction::SRem: + Ops.emplace_back(DIOp::Mod()); + break; + } + + return BI->getOperand(0); +} + +static bool getNewDIConversionOps(const DataLayout &DL, Type *SourceTy, + Type *DestTy, + std::optional Sign, + SmallVectorImpl &Ops); + +/// This is a port of getSalvageOpsForGEP() to DIOp-based DIExpressions. +static Value * +getNewSalvageOpsForGEP(GetElementPtrInst *GEP, const DataLayout &DL, + uint64_t CurrentLocOps, + SmallVectorImpl &Ops, + SmallVectorImpl &AdditionalValues) { + LLVMContext &Ctx = GEP->getContext(); + Type *PointerTy = GEP->getPointerOperand()->getType(); + auto *IntPtrTy = IntegerType::get(Ctx, DL.getPointerTypeSizeInBits(PointerTy)); + unsigned BitWidth = DL.getIndexSizeInBits(GEP->getPointerAddressSpace()); + + // Rewrite a GEP into a DIExpression. + SmallMapVector VariableOffsets; + APInt ConstantOffset(BitWidth, 0); + if (!GEP->collectOffset(DL, BitWidth, VariableOffsets, ConstantOffset)) + return nullptr; + + Ops.emplace_back(DIOp::Reinterpret(IntPtrTy)); + + for (const auto &Offset : VariableOffsets) { + AdditionalValues.push_back(Offset.first); + assert(Offset.second.isStrictlyPositive() && + "Expected strictly positive multiplier for offset."); + Ops.push_back(DIOp::Arg(CurrentLocOps++, Offset.first->getType())); + // Add a conversion operation if the gep offset operand has a different + // integer width than the pointer size. + if (!getNewDIConversionOps(DL, Offset.first->getType(), IntPtrTy, + DIBasicType::Signedness::Signed, Ops)) + return nullptr; + ConstantInt *ConstOffset = + ConstantInt::get(IntPtrTy, Offset.second.getZExtValue()); + Ops.push_back(DIOp::Constant(ConstOffset)); + Ops.push_back(DIOp::Mul()); + Ops.push_back(DIOp::Add()); + } + + Ops.emplace_back(DIOp::Constant( + ConstantInt::get(IntPtrTy, ConstantOffset.getZExtValue()))); + Ops.emplace_back(DIOp::Add()); + Ops.emplace_back(DIOp::Reinterpret(PointerTy)); + return GEP->getOperand(0); +} + +/// This is a port of salvageDebugInfoImpl() to DIOp-based DIExpressions. +/// +/// \param I is an instruction that's about to be deleted, used as a location op +/// to a debug intrinsic. \p Ops will be populated with DIOps that have the same +/// semantics as I. +/// \param CurrentLocOps is the number of location ops the debug intrinsic +/// currently uses. +/// \param AdditionalValues is populated with any additional location ops we +/// need to add to the intrinsic to salvage this instruction. +/// \returns a Value to replace I with in the debug intrinsic's location ops. +static Value *salvageNewDebugInfo(Instruction &I, uint64_t CurrentLocOps, + SmallVectorImpl &AdditionalValues, + SmallVectorImpl &Ops) { + auto &M = *I.getModule(); + auto &DL = M.getDataLayout(); + + if (I.getType()->isVectorTy()) + return nullptr; + + if (auto *CI = dyn_cast(&I)) { + Value *FromValue = CI->getOperand(0); + Type *Type = CI->getType(); + + if (CI->isNoopCast(DL)) + Ops.emplace_back(DIOp::Reinterpret(Type)); + // FIXME(diexpression-poison): relax restriction to integer type to match IR + // instruction + else if (isa(&I) && Type->isIntegerTy()) + Ops.emplace_back(DIOp::SExt(Type)); + // FIXME(diexpression-poison): relax restriction to integer type to match IR + // instruction + else if (isa(&I) && Type->isIntegerTy()) + Ops.emplace_back(DIOp::ZExt(Type)); + else if (isa(&I)) + Ops.emplace_back(DIOp::Convert(Type)); + else + return nullptr; + + return FromValue; + } + + if (auto *BI = dyn_cast(&I)) + return getNewSalvageOpsForBinOp(BI, CurrentLocOps, Ops, AdditionalValues); + if (auto *GEP = dyn_cast(&I)) + return getNewSalvageOpsForGEP(GEP, DL, CurrentLocOps, Ops, AdditionalValues); + + return nullptr; +} + void llvm::salvageDebugInfoForDbgValues(Instruction &I, ArrayRef DPUsers) { // These are arbitrary chosen limits on the maximum number of values and the @@ -2070,6 +2296,25 @@ void llvm::salvageDebugInfoForDbgValues(Instruction &I, Value *Op0 = nullptr; DIExpression *SalvagedExpr = DVR->getExpression(); auto LocItr = find(DVRLocation, &I); + + if (SalvagedExpr->holdsNewElements()) { + while (SalvagedExpr && LocItr != DVRLocation.end()) { + SmallVector Ops; + unsigned LocNo = std::distance(DVRLocation.begin(), LocItr); + uint64_t CurrentLocOps = SalvagedExpr->getNewNumLocationOperands(); + Op0 = salvageNewDebugInfo(I, CurrentLocOps, AdditionalValues, Ops); + if (!Op0) + break; + SalvagedExpr = DIExpression::appendNewOpsToArg(SalvagedExpr, Ops, LocNo, + Op0->getType()); + LocItr = std::find(++LocItr, DVRLocation.end(), &I); + } + // salvageDebugInfoImpl should fail on examining the first element of + // DbgUsers, or none of them. + if (!Op0) + break; + } + while (SalvagedExpr && LocItr != DVRLocation.end()) { SmallVector Ops; unsigned LocNo = std::distance(DVRLocation.begin(), LocItr); @@ -2326,7 +2571,8 @@ using DbgValReplacement = std::optional; /// possibly moving/undefing users to prevent use-before-def. Returns true if /// changes are made. static bool rewriteDebugUsers( - Instruction &From, Value &To, Instruction &DomPoint, DominatorTree &DT, + Instruction &From, Value &To, Instruction &DomPoint, + const DominatorTree &DT, function_ref RewriteDVRExpr) { // Find debug users of From. SmallVector DPUsers; @@ -2411,8 +2657,101 @@ static bool isBitCastSemanticsPreserving(const DataLayout &DL, Type *FromTy, return false; } +/// Generate new DIOps for a conversion from \param SourceTy to \param DestTy. +/// Returns true if the conversion was successful. +static bool getNewDIConversionOps(const DataLayout &DL, Type *SourceTy, + Type *DestTy, + std::optional Sign, + SmallVectorImpl &Ops) { + if (SourceTy == DestTy) + return true; // No conversion necessary. + + TypeSize SourceBits = DL.getTypeSizeInBits(SourceTy); + TypeSize DestBits = DL.getTypeSizeInBits(DestTy); + + if (SourceBits == DestBits && !DL.isNonIntegralPointerType(SourceTy) && + !DL.isNonIntegralPointerType(DestTy) && + ((SourceTy->isPointerTy() && DestTy->isIntegerTy()) || + (SourceTy->isIntegerTy() && DestTy->isPointerTy()))) { + Ops.emplace_back(DIOp::Reinterpret(DestTy)); + return true; + } + + if (SourceTy->isPointerTy() && DestTy->isPointerTy()) { + Ops.emplace_back(DIOp::Convert(DestTy)); + return true; + } + + if (!SourceTy->isIntegerTy() || !DestTy->isIntegerTy()) + return false; + + if (SourceBits < DestBits) { + if (!Sign) + return false; + + if (*Sign == DIBasicType::Signedness::Signed) + Ops.emplace_back(DIOp::SExt(DestTy)); + else + Ops.emplace_back(DIOp::ZExt(DestTy)); + return true; + } + + Ops.emplace_back(DIOp::Convert(DestTy)); + return true; +} + +/// Convert the type of all DIOpArgs that refer to \param LocOp to \param NewTy. +/// This is done by replacing the DIOpArg type and adding an appropriate +/// conversion operator back to the original type. e.g, the following +/// expression: +/// +/// DIExpression(DIOpArg(ptr), DIOpDeref(i32)) +/// +/// Becomes: +/// +/// DIExpression(DIOpArg(i64), DIOpReinterpret(ptr), DIOpDeref(i32)) +/// +/// If NewTy is i64. After this function returns, DII must be updated with a new +/// value of the correct type. +template +static std::optional +updateNewDIExpressionArgType(IntrinsicOrRecord &DII, Value *LocOp, + Type *NewTy) { + DIExpression *Expr = DII.getExpression(); + assert(Expr->holdsNewElements() && "expected a new DIExpression!"); + + // If the types are the same, then the expression is already correct. + if (LocOp->getType() == NewTy) + return Expr; + + const DataLayout &DL = DII.getModule()->getDataLayout(); + auto LocOps = DII.location_ops(); + for (auto Iter = LocOps.begin(); Iter != LocOps.end(); ++Iter) { + Value *V = *Iter; + if (V != LocOp) + continue; + + // Use the signedness of the variable to determine whether we should use + // ZExt/SExt for integer promotions. This isn't necessarily correct, but + // it's probably the best we can do given replaceAllDbgUsesWith()'s API. + SmallVector ConversionOps; + if (!getNewDIConversionOps(DL, NewTy, LocOp->getType(), + DII.getVariable()->getSignedness(), + ConversionOps)) + return std::nullopt; + + unsigned LocNo = std::distance(LocOps.begin(), Iter); + Expr = DIExpression::appendNewOpsToArg(Expr, ConversionOps, LocNo, NewTy); + if (!Expr) + return std::nullopt; + } + + return Expr; +} + bool llvm::replaceAllDbgUsesWith(Instruction &From, Value &To, - Instruction &DomPoint, DominatorTree &DT) { + Instruction &DomPoint, + const DominatorTree &DT) { // Exit early if From has no debug users. if (!From.isUsedByMetadata()) return false; @@ -2423,6 +2762,8 @@ bool llvm::replaceAllDbgUsesWith(Instruction &From, Value &To, Type *ToTy = To.getType(); auto IdentityDVR = [&](DbgVariableRecord &DVR) -> DbgValReplacement { + if (DVR.getExpression()->holdsNewElements()) + return updateNewDIExpressionArgType(DVR, &From, ToTy); return DVR.getExpression(); }; @@ -2447,6 +2788,9 @@ bool llvm::replaceAllDbgUsesWith(Instruction &From, Value &To, // The width of the result has shrunk. Use sign/zero extension to describe // the source variable's high bits. auto SignOrZeroExtDVR = [&](DbgVariableRecord &DVR) -> DbgValReplacement { + if (DVR.getExpression()->holdsNewElements()) + return updateNewDIExpressionArgType(DVR, &From, ToTy); + DILocalVariable *Var = DVR.getVariable(); // Without knowing signedness, sign/zero extension isn't possible. @@ -2461,6 +2805,17 @@ bool llvm::replaceAllDbgUsesWith(Instruction &From, Value &To, return rewriteDebugUsers(From, To, DomPoint, DT, SignOrZeroExtDVR); } + if (FromTy->isPointerTy() && ToTy->isPointerTy()) { + // Non-bitcast address space conversions are only supported on + // DIOp-DIExpressions. + auto IdentityNewDVR = [&](DbgVariableRecord &DVR) -> DbgValReplacement { + if (DVR.getExpression()->holdsNewElements()) + return updateNewDIExpressionArgType(DVR, &From, ToTy); + return std::nullopt; + }; + return rewriteDebugUsers(From, To, DomPoint, DT, IdentityNewDVR); + } + // TODO: Floating-point conversions, vectors. return false; } diff --git a/llvm/runtimes/CMakeLists.txt b/llvm/runtimes/CMakeLists.txt index d877f0b883cc4..a7b8112e27e13 100644 --- a/llvm/runtimes/CMakeLists.txt +++ b/llvm/runtimes/CMakeLists.txt @@ -507,10 +507,18 @@ if(build_runtimes) endif() # Forward user-provived system configuration to runtimes for requirement introspection. - # CMAKE_PREFIX_PATH is the search path for CMake packages. + # CMAKE_PREFIX_PATH is the search path for CMake packages. In order to pass through + # the command line interface, the CMake semicolon separator needs to be replaced + # with $ if(CMAKE_PREFIX_PATH) - list(APPEND extra_cmake_args "-DCMAKE_PREFIX_PATH=${CMAKE_PREFIX_PATH}") + string(JOIN "$" escaped_cmake_prefix_path ${CMAKE_PREFIX_PATH}) + # Some projects require access to the LLVM lib/cmake directory + if (OFFLOAD_EXTERNAL_PROJECT_UNIFIED_ROCR OR DEFINED LIBOMPTARGET_EXTERNAL_PROJECT_ROCM_DEVICE_LIBS_PATH) + string(PREPEND escaped_cmake_prefix_path "${CMAKE_BINARY_DIR}/lib/cmake$") + endif() + list(APPEND extra_cmake_args "-DCMAKE_PREFIX_PATH=${escaped_cmake_prefix_path}") endif() + # CMAKE_PROGRAM_PATH is the search path for executables such as python. if(CMAKE_PROGRAM_PATH) list(APPEND extra_cmake_args "-DCMAKE_PROGRAM_PATH=${CMAKE_PROGRAM_PATH}") @@ -537,6 +545,52 @@ if(build_runtimes) list(APPEND extra_args ENABLE_FORTRAN) endif() if("openmp" IN_LIST LLVM_ENABLE_RUNTIMES OR "offload" IN_LIST LLVM_ENABLE_RUNTIMES) + # With ROCm 6.3 the ROCr runtime and the thunk layer share a single repository. + # No need to provide a separate path for ROCt. + if (OFFLOAD_EXTERNAL_PROJECT_UNIFIED_ROCR) + if(NOT DEFINED LIBOMPTARGET_EXTERNAL_PROJECT_HSA_PATH) + message(SEND_ERROR "External ROCr requires setting LIBOMPTARGET_EXTERNAL_PROJECT_HSA_PATH") + endif() + + message(STATUS "Add external unified ROCr: ${LIBOMPTARGET_EXTERNAL_PROJECT_HSA_PATH}") + ExternalProject_Add(rocr-runtime + SOURCE_DIR ${LIBOMPTARGET_EXTERNAL_PROJECT_HSA_PATH} + DEPENDS clang llvm-link lld opt llvm-objcopy + INSTALL_COMMAND "" + CMAKE_ARGS -DBUILD_SHARED_LIBS=ON + -DIMAGE_SUPPORT=OFF + -DLLVM_RUNTIME_OPENMP=ON + ${extra_cmake_args}) + set(HSA_DEP rocr-runtime) + endif() + + # omptarget device RTL depends on device libs, leading to circular dependency in build scripts. + # Providing path to the sources enables to build them as part of compiler build, which + # removes the ciruclar dependency on the script-side. + if (DEFINED LIBOMPTARGET_EXTERNAL_PROJECT_ROCM_DEVICE_LIBS_PATH) + message(STATUS "Add external AMD device-libs: ${LIBOMPTARGET_EXTERNAL_PROJECT_ROCM_DEVICE_LIBS_PATH}") + if (NOT ${ROCM_DEVICE_LIBS_INSTALL_PREFIX_PATH} STREQUAL "") + ExternalProject_Add(rocm-device-libs + SOURCE_DIR ${LIBOMPTARGET_EXTERNAL_PROJECT_ROCM_DEVICE_LIBS_PATH} + DEPENDS clang llvm-link lld opt llvm-objcopy + CMAKE_ARGS -DCMAKE_INSTALL_PREFIX=${ROCM_DEVICE_LIBS_INSTALL_PREFIX_PATH} + -DROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_NEW=${ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC} + -DROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_OLD=amdgcn + ${extra_cmake_args}) + else() + ExternalProject_Add(rocm-device-libs + SOURCE_DIR ${LIBOMPTARGET_EXTERNAL_PROJECT_ROCM_DEVICE_LIBS_PATH} + DEPENDS clang llvm-link lld opt llvm-objcopy + INSTALL_COMMAND "" + CMAKE_ARGS -DCMAKE_PREFIX_PATH=${CMAKE_BINARY_DIR}/lib/cmake + -DROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_NEW=${ROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC} + -DROCM_DEVICE_LIBS_BITCODE_INSTALL_LOC_OLD=amdgcn) + endif() + endif() + + if("AMDGPU" IN_LIST LLVM_TARGETS_TO_BUILD) + set(AMDGPU_ARCH_DEP amdgpu-arch) + endif() if (${LLVM_TOOL_FLANG_BUILD}) message(STATUS "Configuring build of omp_lib.mod and omp_lib_kinds.mod via flang") set(LIBOMP_FORTRAN_MODULES_COMPILER "${CMAKE_BINARY_DIR}/bin/flang") @@ -548,8 +602,11 @@ if(build_runtimes) # that all .mod files are also properly build. list(APPEND extra_deps "flang" "module_files") endif() - foreach(dep opt llvm-link llvm-extract clang llvm-offload-binary clang-nvlink-wrapper) - if(TARGET ${dep}) + if (${LIBOMPTARGET_BUILD_DEVICE_FORTRT}) + set(FORTRT_DEP FortranRuntime) + endif() + foreach(dep opt llvm-link llvm-extract clang llvm-offload-binary clang-nvlink-wrapper rocm-device-libs offload-arch ${HSA_DEP} ${AMDGPU_ARCH_DEP} ${FORTRT_DEP}) + if(TARGET ${dep} AND OPENMP_ENABLE_LIBOMPTARGET) list(APPEND extra_deps ${dep}) endif() endforeach() diff --git a/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll b/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll index 8cadcae1654c9..f88dcc1b14e1f 100644 --- a/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll +++ b/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll @@ -1,5 +1,5 @@ ; REQUIRES: x86_64-linux -; + ; RUN: rm -rf %t ; RUN: split-file %s %t ; diff --git a/llvm/test/Assembler/2002-08-15-ConstantExprProblem.ll b/llvm/test/Assembler/2002-08-15-ConstantExprProblem.ll index 49fada5690fef..3a2e4f2c8249e 100644 --- a/llvm/test/Assembler/2002-08-15-ConstantExprProblem.ll +++ b/llvm/test/Assembler/2002-08-15-ConstantExprProblem.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as %s -o /dev/null -; RUN: verify-uselistorder %s +; RUN: llvm-as %s -o /dev/null +; RUN: verify-uselistorder %s @.LC0 = internal global [12 x i8] c"hello world\00" ; [#uses=1] diff --git a/llvm/test/Assembler/2002-08-15-UnresolvedGlobalReference.ll b/llvm/test/Assembler/2002-08-15-UnresolvedGlobalReference.ll index 279c3ad0ba499..952976edfd1be 100644 --- a/llvm/test/Assembler/2002-08-15-UnresolvedGlobalReference.ll +++ b/llvm/test/Assembler/2002-08-15-UnresolvedGlobalReference.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as %s -o /dev/null -; RUN: verify-uselistorder %s +; RUN: llvm-as %s -o /dev/null +; RUN: verify-uselistorder %s @.LC0 = internal global [12 x i8] c"hello world\00" ; [#uses=1] diff --git a/llvm/test/Assembler/2002-08-16-ConstExprInlined.ll b/llvm/test/Assembler/2002-08-16-ConstExprInlined.ll index 94c22794f5bc3..cb20e4923018b 100644 --- a/llvm/test/Assembler/2002-08-16-ConstExprInlined.ll +++ b/llvm/test/Assembler/2002-08-16-ConstExprInlined.ll @@ -8,8 +8,8 @@ ; reader should NEVER produce a program "successfully" with placeholders still ; around! ; -; RUN: llvm-as < %s | llvm-dis | llvm-as -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | llvm-as +; RUN: verify-uselistorder %s @.LC0 = internal global [4 x i8] c"foo\00" ; [#uses=1] @X = global ptr null ; [#uses=0] diff --git a/llvm/test/Assembler/2003-05-15-AssemblerProblem.ll b/llvm/test/Assembler/2003-05-15-AssemblerProblem.ll index 3ac580b6ab209..36593463af004 100644 --- a/llvm/test/Assembler/2003-05-15-AssemblerProblem.ll +++ b/llvm/test/Assembler/2003-05-15-AssemblerProblem.ll @@ -1,7 +1,7 @@ ; This bug was caused by two CPR's existing for the same global variable, ; colliding in the Module level CPR map. -; RUN: llvm-as %s -o /dev/null -; RUN: verify-uselistorder %s +; RUN: llvm-as %s -o /dev/null +; RUN: verify-uselistorder %s define void @test() { call void (...) @AddString( ptr null, i32 0 ) diff --git a/llvm/test/Assembler/2003-08-21-ConstantExprCast-Fold.ll b/llvm/test/Assembler/2003-08-21-ConstantExprCast-Fold.ll index de6c8933bbb5e..43cfbb2cd935e 100644 --- a/llvm/test/Assembler/2003-08-21-ConstantExprCast-Fold.ll +++ b/llvm/test/Assembler/2003-08-21-ConstantExprCast-Fold.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | not grep getelementptr -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | not grep getelementptr +; RUN: verify-uselistorder %s @A = external global { float } ; [#uses=2] @0 = global ptr @A ; :0 [#uses=0] diff --git a/llvm/test/Assembler/2007-09-10-AliasFwdRef.ll b/llvm/test/Assembler/2007-09-10-AliasFwdRef.ll index 97d97fa709de5..b994ca82bdfc0 100644 --- a/llvm/test/Assembler/2007-09-10-AliasFwdRef.ll +++ b/llvm/test/Assembler/2007-09-10-AliasFwdRef.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis +; RUN: verify-uselistorder %s ; PR1645 @__gthread_active_ptr.5335 = internal constant ptr @__gthrw_pthread_cancel diff --git a/llvm/test/Assembler/ConstantExprFold.ll b/llvm/test/Assembler/ConstantExprFold.ll index 33ee49296de0a..937d3eee8b9dd 100644 --- a/llvm/test/Assembler/ConstantExprFold.ll +++ b/llvm/test/Assembler/ConstantExprFold.ll @@ -2,9 +2,9 @@ ; This test checks to make sure that constant exprs fold in some simple ; situations -; RUN: opt -S < %s | FileCheck %s -; RUN: llvm-as < %s | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: opt -S < %s | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s @A = global i64 0 diff --git a/llvm/test/Assembler/ConstantExprFoldCast.ll b/llvm/test/Assembler/ConstantExprFoldCast.ll index 2e1782a4c34f7..03b358c6399ef 100644 --- a/llvm/test/Assembler/ConstantExprFoldCast.ll +++ b/llvm/test/Assembler/ConstantExprFoldCast.ll @@ -1,7 +1,7 @@ ; This test checks to make sure that constant exprs fold in some simple situations -; RUN: llvm-as < %s | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s ; CHECK-NOT: bitcast ; CHECK-NOT: trunc diff --git a/llvm/test/Assembler/ConstantExprNoFold.ll b/llvm/test/Assembler/ConstantExprNoFold.ll index 862e0c2814931..529aa6d3ce334 100644 --- a/llvm/test/Assembler/ConstantExprNoFold.ll +++ b/llvm/test/Assembler/ConstantExprNoFold.ll @@ -1,8 +1,8 @@ ; This test checks to make sure that constant exprs don't fold in some simple ; situations -; RUN: llvm-as < %s | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s ; Even give it a datalayout, to tempt folding as much as possible. target datalayout = "p:32:32" diff --git a/llvm/test/Assembler/DIExpressionNew.ll b/llvm/test/Assembler/DIExpressionNew.ll new file mode 100644 index 0000000000000..aea7d814a17d7 --- /dev/null +++ b/llvm/test/Assembler/DIExpressionNew.ll @@ -0,0 +1,89 @@ +; RUN: llvm-as -disable-verify < %s | llvm-dis | llvm-as -disable-verify | llvm-dis | FileCheck %s + +; CHECK: %t = type { i32, i32 } +%t = type { i32, i32 } +; CHECK: %u = type { %t, i32 } +%u = type { %t, i32 } + +; CHECK: !named = !{ +!named = !{ +; CHECK-SAME: !DIExpression(), +!DIExpression(), +; CHECK-SAME: !DIExpression(DIOpReferrer(i32)), +!DIExpression(DIOpReferrer(i32)), +; CHECK-SAME: !DIExpression(DIOpReferrer(%t)), +!DIExpression(DIOpReferrer(%t)), +; CHECK-SAME: !DIExpression(DIOpReferrer(%u)), +!DIExpression(DIOpReferrer(%u)), +; CHECK-SAME: !DIExpression(DIOpReferrer({ i16, float })), +!DIExpression(DIOpReferrer({ i16, float })), +; CHECK-SAME: !DIExpression(DIOpArg(0, i32), DIOpConvert(float)), +!DIExpression(DIOpArg(0, i32), DIOpConvert(float)), +; CHECK-SAME: !DIExpression(DIOpArg(0, %t), DIOpConvert(%u)), +!DIExpression(DIOpArg(0, %t), DIOpConvert(%u)), +; CHECK-SAME: !DIExpression(DIOpTypeObject(double)), +!DIExpression(DIOpTypeObject(double)), +; CHECK-SAME: !DIExpression(DIOpTypeObject(%t)), +!DIExpression(DIOpTypeObject(%t)), +; CHECK-SAME: !DIExpression(DIOpConstant(i8 1)), +!DIExpression(DIOpConstant(i8 1)), +; CHECK-SAME: !DIExpression(DIOpConstant(%u undef)), +!DIExpression(DIOpConstant(%u undef)), +; CHECK-SAME: !DIExpression(DIOpConvert(i16)), +!DIExpression(DIOpConvert(i16)), +; CHECK-SAME: !DIExpression(DIOpConvert(%t)), +!DIExpression(DIOpConvert(%t)), +; CHECK-SAME: !DIExpression(DIOpZExt(i32)), +!DIExpression(DIOpZExt(i32)), +; CHECK-SAME: !DIExpression(DIOpSExt(i32)), +!DIExpression(DIOpSExt(i32)), +; CHECK-SAME: !DIExpression(DIOpReinterpret(i64)), +!DIExpression(DIOpReinterpret(i64)), +; CHECK-SAME: !DIExpression(DIOpReinterpret(%t)), +!DIExpression(DIOpReinterpret(%t)), +; CHECK-SAME: !DIExpression(DIOpBitOffset(i1)), +!DIExpression(DIOpBitOffset(i1)), +; CHECK-SAME: !DIExpression(DIOpBitOffset(%u)), +!DIExpression(DIOpBitOffset(%u)), +; CHECK-SAME: !DIExpression(DIOpByteOffset(i16)), +!DIExpression(DIOpByteOffset(i16)), +; CHECK-SAME: !DIExpression(DIOpByteOffset(%t)), +!DIExpression(DIOpByteOffset(%t)), +; CHECK-SAME: !DIExpression(DIOpComposite(4, i8)), +!DIExpression(DIOpComposite(4, i8)), +; CHECK-SAME: !DIExpression(DIOpComposite(2, %u)), +!DIExpression(DIOpComposite(2, %u)), +; CHECK-SAME: !DIExpression(DIOpExtend(6)), +!DIExpression(DIOpExtend(6)), +; CHECK-SAME: !DIExpression(DIOpSelect()), +!DIExpression(DIOpSelect()), +; CHECK-SAME: !DIExpression(DIOpAddrOf(1)), +!DIExpression(DIOpAddrOf(1)), +; CHECK-SAME: !DIExpression(DIOpDeref(i32)), +!DIExpression(DIOpDeref(i32)), +; CHECK-SAME: !DIExpression(DIOpDeref(%t)), +!DIExpression(DIOpDeref(%t)), +; CHECK-SAME: !DIExpression(DIOpRead()), +!DIExpression(DIOpRead()), +; CHECK-SAME: !DIExpression(DIOpAdd()), +!DIExpression(DIOpAdd()), +; CHECK-SAME: !DIExpression(DIOpSub()), +!DIExpression(DIOpSub()), +; CHECK-SAME: !DIExpression(DIOpMul()), +!DIExpression(DIOpMul()), +; CHECK-SAME: !DIExpression(DIOpDiv()), +!DIExpression(DIOpDiv()), +; CHECK-SAME: !DIExpression(DIOpLShr()), +!DIExpression(DIOpLShr()), +; CHECK-SAME: !DIExpression(DIOpAShr()), +!DIExpression(DIOpAShr()), +; CHECK-SAME: !DIExpression(DIOpShl()), +!DIExpression(DIOpShl()), +; CHECK-SAME: !DIExpression(DIOpPushLane(i32)), +!DIExpression(DIOpPushLane(i32)), +; CHECK-SAME: !DIExpression(DIOpPushLane(%u)), +!DIExpression(DIOpPushLane(%u)), +; CHECK-SAME: !DIExpression() +!DIExpression(), +; CHECK-SAME: !DIExpression(DIOpFragment(1, 2))} +!DIExpression(DIOpFragment(1, 2))} diff --git a/llvm/test/Assembler/DIExpressionNewDebugRecords.ll b/llvm/test/Assembler/DIExpressionNewDebugRecords.ll new file mode 100644 index 0000000000000..abb7008653502 --- /dev/null +++ b/llvm/test/Assembler/DIExpressionNewDebugRecords.ll @@ -0,0 +1,28 @@ +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s + +; CHECK: %struct.S = type { i32 } +%struct.S = type { i32 } + +define dso_local i32 @f() !dbg !7 { +entry: + ; CHECK: #dbg_value(ptr null, !9, !DIExpression(DIOpArg(0, ptr), DIOpDeref(%struct.S)), !11) + #dbg_value(ptr null, !9, !DIExpression(DIOpArg(0, ptr), DIOpDeref(%struct.S)), !11) + ret i32 0, !dbg !11 +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5} +!llvm.ident = !{!6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 18.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, nameTableKind: None) +!1 = !DIFile(filename: "print.c", directory: "/tmp") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 5} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{!"clang version 18.0.0"} +!7 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 3, type: !8, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0) +!8 = !DISubroutineType(types: !2) +!9 = !DILocalVariable(name: "a", arg: 1, scope: !7, file: !1, line: 3, type: !10) +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!11 = !DILocation(line: 3, column: 15, scope: !7) diff --git a/llvm/test/Assembler/MultipleReturnValueType.ll b/llvm/test/Assembler/MultipleReturnValueType.ll index 6170e0ce4fb26..0c523f531f7ff 100644 --- a/llvm/test/Assembler/MultipleReturnValueType.ll +++ b/llvm/test/Assembler/MultipleReturnValueType.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s +; RUN: verify-uselistorder %s %struct.S_102 = type { float, float } diff --git a/llvm/test/Assembler/addrspacecast-alias.ll b/llvm/test/Assembler/addrspacecast-alias.ll index 0c5a56323f7db..c61b1ea9db32a 100644 --- a/llvm/test/Assembler/addrspacecast-alias.ll +++ b/llvm/test/Assembler/addrspacecast-alias.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s ; Test that global aliases are allowed to be constant addrspacecast diff --git a/llvm/test/Assembler/aggregate-constant-values.ll b/llvm/test/Assembler/aggregate-constant-values.ll index b208b582a4657..97d2dab7a667c 100644 --- a/llvm/test/Assembler/aggregate-constant-values.ll +++ b/llvm/test/Assembler/aggregate-constant-values.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s ; CHECK: @foo ; CHECK: store { i32, i32 } { i32 7, i32 9 }, ptr %x diff --git a/llvm/test/Assembler/align-param-attr-format.ll b/llvm/test/Assembler/align-param-attr-format.ll index cc36c0f866922..9f370a2bb85ff 100644 --- a/llvm/test/Assembler/align-param-attr-format.ll +++ b/llvm/test/Assembler/align-param-attr-format.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s ; Test that align(N) is accepted as an alternative syntax to align N diff --git a/llvm/test/Assembler/atomic.ll b/llvm/test/Assembler/atomic.ll index 6609edc2953cc..dfaf068dbc590 100644 --- a/llvm/test/Assembler/atomic.ll +++ b/llvm/test/Assembler/atomic.ll @@ -1,5 +1,5 @@ -; RUN: opt < %s | opt -S | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: opt < %s | opt -S | FileCheck %s +; RUN: verify-uselistorder %s ; Basic smoke test for atomic operations. define void @f(ptr %x) { diff --git a/llvm/test/Assembler/attribute-builtin.ll b/llvm/test/Assembler/attribute-builtin.ll index dddb3d726aa6c..d9f6f6ab2846e 100644 --- a/llvm/test/Assembler/attribute-builtin.ll +++ b/llvm/test/Assembler/attribute-builtin.ll @@ -4,10 +4,10 @@ ; ; rdar://13727199 -; RUN: llvm-as -disable-verify < %s | \ -; RUN: llvm-dis | \ -; RUN: llvm-as -disable-verify | \ -; RUN: llvm-dis | \ +; RUN: llvm-as -disable-verify < %s | \ +; RUN: llvm-dis | \ +; RUN: llvm-as -disable-verify | \ +; RUN: llvm-dis | \ ; RUN: FileCheck -check-prefix=CHECK-ASSEMBLES %s ; CHECK-ASSEMBLES: declare ptr @foo(ptr) [[NOBUILTIN:#[0-9]+]] diff --git a/llvm/test/Assembler/auto_upgrade_intrinsics.ll b/llvm/test/Assembler/auto_upgrade_intrinsics.ll index 64d4a3ba7c802..19e686da78f6a 100644 --- a/llvm/test/Assembler/auto_upgrade_intrinsics.ll +++ b/llvm/test/Assembler/auto_upgrade_intrinsics.ll @@ -1,6 +1,6 @@ ; Test to make sure intrinsics are automatically upgraded. -; RUN: llvm-as < %s | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s %0 = type opaque; diff --git a/llvm/test/Assembler/autoupgrade-thread-pointer.ll b/llvm/test/Assembler/autoupgrade-thread-pointer.ll index 178e31f50b1bf..70ecca87e3af5 100644 --- a/llvm/test/Assembler/autoupgrade-thread-pointer.ll +++ b/llvm/test/Assembler/autoupgrade-thread-pointer.ll @@ -1,5 +1,5 @@ ; Test autoupgrade of arch-specific thread pointer intrinsics -; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s declare ptr @llvm.aarch64.thread.pointer() declare ptr @llvm.arm.thread.pointer() diff --git a/llvm/test/Assembler/byval-type-attr.ll b/llvm/test/Assembler/byval-type-attr.ll index aa62997b6d089..055a1f528cf56 100644 --- a/llvm/test/Assembler/byval-type-attr.ll +++ b/llvm/test/Assembler/byval-type-attr.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s ; CHECK: define void @foo(ptr byval(i32) align 4 %0) define void @foo(ptr byval(i32) align 4 %0) { diff --git a/llvm/test/Assembler/call-nonzero-program-addrspace-2.ll b/llvm/test/Assembler/call-nonzero-program-addrspace-2.ll index bc600d56db51b..b913528effd16 100644 --- a/llvm/test/Assembler/call-nonzero-program-addrspace-2.ll +++ b/llvm/test/Assembler/call-nonzero-program-addrspace-2.ll @@ -1,5 +1,5 @@ ; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s -; RUN: llvm-as %s -data-layout=P42 -o - | llvm-dis - -o - | FileCheck %s -check-prefix PROGAS42 +; RUN: llvm-as %s -data-layout=P42 -o - | llvm-dis - -o - | FileCheck %s -check-prefix PROGAS42 ; Check that numbered variables in a nonzero program address space 200 can be used in a call instruction diff --git a/llvm/test/Assembler/call-nonzero-program-addrspace.ll b/llvm/test/Assembler/call-nonzero-program-addrspace.ll index 5f6f76e3ef9c2..b811bc56cc11a 100644 --- a/llvm/test/Assembler/call-nonzero-program-addrspace.ll +++ b/llvm/test/Assembler/call-nonzero-program-addrspace.ll @@ -1,5 +1,5 @@ ; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s -; RUN: llvm-as %s -data-layout=P42 -o - | llvm-dis - -o - | FileCheck %s -check-prefix PROGAS42 +; RUN: llvm-as %s -data-layout=P42 -o - | llvm-dis - -o - | FileCheck %s -check-prefix PROGAS42 ; Check that variables in a nonzero program address space 42 can be used in a call instruction diff --git a/llvm/test/Assembler/debug-info.ll b/llvm/test/Assembler/debug-info.ll index 09282b2114c8f..1fbbf9538a173 100644 --- a/llvm/test/Assembler/debug-info.ll +++ b/llvm/test/Assembler/debug-info.ll @@ -37,8 +37,8 @@ !13 = distinct !{} !14 = !DIFile(filename: "", directory: "") -; CHECK-NEXT: !13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !6, size: 32, align: 32, dwarfAddressSpace: 1) -!15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 32, align: 32, dwarfAddressSpace: 1) +; CHECK-NEXT: !13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !6, size: 32, align: 32, addressSpace: 1) +!15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 32, align: 32, addressSpace: 1) ; CHECK-NEXT: !14 = !DICompositeType(tag: DW_TAG_structure_type, name: "MyType", file: !10, line: 2, size: 32, align: 32, identifier: "MangledMyType") ; CHECK-NEXT: !15 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Base", scope: !14, file: !10, line: 3, size: 128, align: 32, offset: 64, flags: DIFlagPublic, elements: !16, runtimeLang: DW_LANG_C_plus_plus_11, vtableHolder: !15, templateParams: !18, identifier: "MangledBase") diff --git a/llvm/test/Assembler/fast-math-flags.ll b/llvm/test/Assembler/fast-math-flags.ll index 9c08e9da1d19e..d59e9b76524d1 100644 --- a/llvm/test/Assembler/fast-math-flags.ll +++ b/llvm/test/Assembler/fast-math-flags.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck -strict-whitespace %s -; RUN: opt -S < %s | FileCheck -strict-whitespace %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | FileCheck -strict-whitespace %s +; RUN: opt -S < %s | FileCheck -strict-whitespace %s +; RUN: verify-uselistorder %s @addr = external global i64 @select = external global i1 diff --git a/llvm/test/Assembler/flags.ll b/llvm/test/Assembler/flags.ll index b685277f4ee04..c580d2d9ecbf9 100644 --- a/llvm/test/Assembler/flags.ll +++ b/llvm/test/Assembler/flags.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s @addr = external global i64 @addr_as1 = external addrspace(1) global i64 diff --git a/llvm/test/Assembler/getelementptr.ll b/llvm/test/Assembler/getelementptr.ll index a58af2f7a9b35..3a0fcb075894a 100644 --- a/llvm/test/Assembler/getelementptr.ll +++ b/llvm/test/Assembler/getelementptr.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s @A = external global [2 x [3 x [5 x [7 x i32]]]] @B = global ptr getelementptr ([2 x [3 x [5 x [7 x i32]]]], ptr @A, i64 0, i64 0, i64 2, i64 1, i64 7523) diff --git a/llvm/test/Assembler/getelementptr_vec_ce.ll b/llvm/test/Assembler/getelementptr_vec_ce.ll index 045f8b672edf3..3756f644a2def 100644 --- a/llvm/test/Assembler/getelementptr_vec_ce.ll +++ b/llvm/test/Assembler/getelementptr_vec_ce.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s @G = global [4 x i32] zeroinitializer diff --git a/llvm/test/Assembler/global-addrspace-forwardref.ll b/llvm/test/Assembler/global-addrspace-forwardref.ll index da81bcfb17f89..71db498625e63 100644 --- a/llvm/test/Assembler/global-addrspace-forwardref.ll +++ b/llvm/test/Assembler/global-addrspace-forwardref.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s ; Make sure the address space of forward decls is preserved diff --git a/llvm/test/Assembler/globalvariable-attributes.ll b/llvm/test/Assembler/globalvariable-attributes.ll index 4882b447973c0..9a93395a7c686 100644 --- a/llvm/test/Assembler/globalvariable-attributes.ll +++ b/llvm/test/Assembler/globalvariable-attributes.ll @@ -14,8 +14,10 @@ @g12 = global i32 2, code_model "kernel" @g13 = global i32 2, code_model "medium" @g14 = global i32 2, code_model "large" +@g15 = global i32 2 #1 attributes #0 = { "string" = "value" nobuiltin norecurse } +attributes #1 = { sanitized_padded_global } ; CHECK: @g1 = global i32 7 #0 ; CHECK: @g2 = global i32 2, align 4 #1 @@ -31,9 +33,10 @@ attributes #0 = { "string" = "value" nobuiltin norecurse } ; CHECK: @g12 = global i32 2, code_model "kernel" ; CHECK: @g13 = global i32 2, code_model "medium" ; CHECK: @g14 = global i32 2, code_model "large" +; CHECK: @g15 = global i32 2 #4 ; CHECK: attributes #0 = { "key"="value" "key2"="value2" } ; CHECK: attributes #1 = { "key3"="value3" } ; CHECK: attributes #2 = { nobuiltin norecurse "string"="value" } ; CHECK: attributes #3 = { nobuiltin norecurse "key5"="value5" "string"="value" } - +; CHECK: attributes #4 = { sanitized_padded_global } diff --git a/llvm/test/Assembler/huge-array.ll b/llvm/test/Assembler/huge-array.ll index dab4a75213948..526e02187694d 100644 --- a/llvm/test/Assembler/huge-array.ll +++ b/llvm/test/Assembler/huge-array.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s ; CHECK: define ptr @foo() { ; CHECK: ret ptr null diff --git a/llvm/test/Assembler/ifunc-asm.ll b/llvm/test/Assembler/ifunc-asm.ll index e6be1897b413e..6df1317a296c7 100644 --- a/llvm/test/Assembler/ifunc-asm.ll +++ b/llvm/test/Assembler/ifunc-asm.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Assembler/ifunc-dsolocal.ll b/llvm/test/Assembler/ifunc-dsolocal.ll index 40819dc49bdfe..5b3c194768658 100644 --- a/llvm/test/Assembler/ifunc-dsolocal.ll +++ b/llvm/test/Assembler/ifunc-dsolocal.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s @foo = dso_local ifunc i32 (i32), ptr @foo_ifunc ; CHECK: @foo = dso_local ifunc i32 (i32), ptr @foo_ifunc diff --git a/llvm/test/Assembler/invalid-diarglist-outside-function.ll b/llvm/test/Assembler/invalid-diarglist-outside-function.ll new file mode 100644 index 0000000000000..15245abe58877 --- /dev/null +++ b/llvm/test/Assembler/invalid-diarglist-outside-function.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s +; XFAIL: * +; CHECK: :[[@LINE+1]]:6: error: !DIArgList cannot appear outside of a function +!0 = !DIArgList() diff --git a/llvm/test/Assembler/invoke-nonzero-program-addrspace.ll b/llvm/test/Assembler/invoke-nonzero-program-addrspace.ll index 82d2a0179f9f8..e3c2d252f9f48 100644 --- a/llvm/test/Assembler/invoke-nonzero-program-addrspace.ll +++ b/llvm/test/Assembler/invoke-nonzero-program-addrspace.ll @@ -1,5 +1,5 @@ ; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s -; RUN: llvm-as %s -data-layout=P200 -o - | llvm-dis - -o - | FileCheck %s -check-prefix PROGAS200 +; RUN: llvm-as %s -data-layout=P200 -o - | llvm-dis - -o - | FileCheck %s -check-prefix PROGAS200 ; Check that variables in a nonzero program address space 200 can be used in a invoke instruction diff --git a/llvm/test/Assembler/local-unnamed-addr.ll b/llvm/test/Assembler/local-unnamed-addr.ll index ef67cacad829b..cff6a05725f22 100644 --- a/llvm/test/Assembler/local-unnamed-addr.ll +++ b/llvm/test/Assembler/local-unnamed-addr.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s ; CHECK: @c = local_unnamed_addr constant i32 0 @c = local_unnamed_addr constant i32 0 diff --git a/llvm/test/Assembler/metadata-function-local.ll b/llvm/test/Assembler/metadata-function-local.ll index 7cb8a8a7ce76d..07900042fc082 100644 --- a/llvm/test/Assembler/metadata-function-local.ll +++ b/llvm/test/Assembler/metadata-function-local.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s declare void @llvm.metadata(metadata) diff --git a/llvm/test/Assembler/musttail.ll b/llvm/test/Assembler/musttail.ll index 625adf2cb21ff..b37cf5d2168b6 100644 --- a/llvm/test/Assembler/musttail.ll +++ b/llvm/test/Assembler/musttail.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s ; Check that the ellipsis round trips. diff --git a/llvm/test/Assembler/sret-type-attr.ll b/llvm/test/Assembler/sret-type-attr.ll index 3fd1b096fb71d..a03f8466a16dd 100644 --- a/llvm/test/Assembler/sret-type-attr.ll +++ b/llvm/test/Assembler/sret-type-attr.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s ; CHECK: define void @foo(ptr sret(i32) align 4 %0) define void @foo(ptr sret(i32) align 4 %0) { diff --git a/llvm/test/Assembler/unnamed-alias.ll b/llvm/test/Assembler/unnamed-alias.ll index 853630bbb27ce..c8518dc95e1aa 100644 --- a/llvm/test/Assembler/unnamed-alias.ll +++ b/llvm/test/Assembler/unnamed-alias.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s @0 = private constant i32 0 ; CHECK: @0 = private constant i32 0 diff --git a/llvm/test/Assembler/x86_intrcc.ll b/llvm/test/Assembler/x86_intrcc.ll index 94faca0d6154a..bb84ecbbbfffc 100644 --- a/llvm/test/Assembler/x86_intrcc.ll +++ b/llvm/test/Assembler/x86_intrcc.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s -; RUN: verify-uselistorder %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s ; Make sure no arguments is accepted ; CHECK: define x86_intrcc void @no_args() { diff --git a/llvm/test/Bindings/OCaml/debuginfo.ml b/llvm/test/Bindings/OCaml/debuginfo.ml index 6ebc7c35879a4..ea0d939797340 100644 --- a/llvm/test/Bindings/OCaml/debuginfo.ml +++ b/llvm/test/Bindings/OCaml/debuginfo.ml @@ -250,7 +250,7 @@ let test_global_variable_expression dibuilder f_di m_di = let gvexpr_di = Llvm_debuginfo.dibuild_create_global_variable_expression dibuilder ~scope:m_di ~name:"my_global" ~linkage:"" ~file:f_di ~line:5 ~ty - ~is_local_to_unit:true ~expr:cexpr_di ~decl:null_metadata ~align_in_bits:0 + ~is_local_to_unit:true ~expr:cexpr_di ~decl:null_metadata ~memory_space:DW_MSPACE_LLVM_constant ~align_in_bits:0 in insist ( Llvm_debuginfo.get_metadata_kind gvexpr_di @@ -263,7 +263,7 @@ let test_global_variable_expression dibuilder f_di m_di = ( Llvm_debuginfo.get_metadata_kind gvexpr_var_di = Llvm_debuginfo.MetadataKind.DIGlobalVariableMetadataKind ); stdout_metadata gvexpr_var_di - (* CHECK: [[GV_PTR:<0x[0-9a-f]*>]] = distinct !DIGlobalVariable(name: "my_global", scope: [[MODULE_PTR]], file: [[FILE_PTR]], line: 5, type: [[INT64TY_PTR]], isLocal: true, isDefinition: true) + (* CHECK: [[GV_PTR:<0x[0-9a-f]*>]] = distinct !DIGlobalVariable(name: "my_global", scope: [[MODULE_PTR]], file: [[FILE_PTR]], line: 5, type: [[INT64TY_PTR]], isLocal: true, isDefinition: true, memorySpace: DW_MSPACE_LLVM_constant) *) | None -> insist false ); stdout_metadata gvexpr_di; @@ -281,10 +281,10 @@ let test_variables f dibuilder file_di fun_di = let auto_var = Llvm_debuginfo.dibuild_create_auto_variable dibuilder ~scope:fun_di ~name:"my_local" ~file:file_di ~line:10 ~ty - ~always_preserve:false flags_zero ~align_in_bits:0 + ~always_preserve:false flags_zero ~memory_space:DW_MSPACE_LLVM_constant ~align_in_bits:0 in stdout_metadata auto_var; - (* CHECK: [[LOCAL_VAR_PTR:<0x[0-9a-f]*>]] = !DILocalVariable(name: "my_local", scope: <{{0x[0-9a-f]*}}>, file: <{{0x[0-9a-f]*}}>, line: 10, type: [[INT64TY_PTR]]) + (* CHECK: [[LOCAL_VAR_PTR:<0x[0-9a-f]*>]] = !DILocalVariable(name: "my_local", scope: <{{0x[0-9a-f]*}}>, file: <{{0x[0-9a-f]*}}>, line: 10, type: [[INT64TY_PTR]], memorySpace: DW_MSPACE_LLVM_constant) *) let builder = Llvm.builder_before context entry_term in let all = Llvm.build_alloca (Llvm.i64_type context) "my_alloca" builder in @@ -353,10 +353,10 @@ let test_types dibuilder file_di m_di = let structptr_di = Llvm_debuginfo.dibuild_create_pointer_type dibuilder ~pointee_ty:struct_ty_di ~size_in_bits:192 ~align_in_bits:0 - ~address_space:0 ~name:"" + ~address_space:0 ~memory_space:DW_MSPACE_LLVM_constant ~name:"" in stdout_metadata structptr_di; - (* CHECK: [[STRUCTPTR_PTR:<0x[0-9a-f]*>]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[STRUCT_PTR]], size: 192, dwarfAddressSpace: 0) + (* CHECK: [[STRUCTPTR_PTR:<0x[0-9a-f]*>]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: [[STRUCT_PTR]], size: 192, addressSpace: 0, memorySpace: DW_MSPACE_LLVM_constant) *) insist ( Llvm_debuginfo.get_metadata_kind structptr_di diff --git a/llvm/test/Bindings/llvm-c/debug_info_new_format.ll b/llvm/test/Bindings/llvm-c/debug_info_new_format.ll index 75e5fa01b14a0..b86f27482fa4c 100644 --- a/llvm/test/Bindings/llvm-c/debug_info_new_format.ll +++ b/llvm/test/Bindings/llvm-c/debug_info_new_format.ll @@ -67,7 +67,7 @@ ; CHECK-NEXT: !31 = !{!32, !33} ; CHECK-NEXT: !32 = !DIMacro(type: DW_MACINFO_define, name: "SIMPLE_DEFINE") ; CHECK-NEXT: !33 = !DIMacro(type: DW_MACINFO_define, name: "VALUE_DEFINE", value: "1") -; CHECK-NEXT: !34 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !35, size: 192, dwarfAddressSpace: 0) +; CHECK-NEXT: !34 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !35, size: 192, addressSpace: 0) ; CHECK-NEXT: !35 = !DICompositeType(tag: DW_TAG_structure_type, name: "MyStruct", scope: !4, file: !1, size: 192, elements: !36, runtimeLang: DW_LANG_C89, identifier: "MyStruct") ; CHECK-NEXT: !36 = !{!6, !6, !6} ; CHECK-NEXT: !37 = !DISubrangeType(name: "foo", scope: !1, file: !1, line: 42, size: 64, baseType: !6, lowerBound: i64 0, upperBound: i64 1, stride: i64 8, bias: i64 4) diff --git a/llvm/test/Bitcode/DIExpression-is-distinct-upgrade.ll b/llvm/test/Bitcode/DIExpression-is-distinct-upgrade.ll new file mode 100644 index 0000000000000..d888e9a9eb827 --- /dev/null +++ b/llvm/test/Bitcode/DIExpression-is-distinct-upgrade.ll @@ -0,0 +1,16 @@ +; RUN: llvm-dis -o - %s.bc | FileCheck %s + +!llvm.dbg.cu = !{!1} +!llvm.module.flags = !{!8, !9} + +!0 = distinct !DIGlobalVariable(name: "g", scope: !1, file: !2, line: 1, type: !5, isLocal: false, isDefinition: true) +!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !3, globals: !4) +!2 = !DIFile(filename: "a.c", directory: "/") +!3 = !{} +!4 = !{!7} +!5 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +; CHECK: expr: !DIExpression() +!6 = distinct !DIExpression() +!7 = !DIGlobalVariableExpression(var: !0, expr: !6) +!8 = !{i32 2, !"Dwarf Version", i32 4} +!9 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/llvm/test/Bitcode/DIExpression-is-distinct-upgrade.ll.bc b/llvm/test/Bitcode/DIExpression-is-distinct-upgrade.ll.bc new file mode 100644 index 0000000000000..088e1a4b44885 Binary files /dev/null and b/llvm/test/Bitcode/DIExpression-is-distinct-upgrade.ll.bc differ diff --git a/llvm/test/Bitcode/DILocalVariable-address-space.ll b/llvm/test/Bitcode/DILocalVariable-address-space.ll new file mode 100644 index 0000000000000..bc6ac7b8a3b64 --- /dev/null +++ b/llvm/test/Bitcode/DILocalVariable-address-space.ll @@ -0,0 +1,19 @@ +; RUN: llvm-as %s -o - | llvm-dis | FileCheck %s + +; CHECK: ![[SP:[0-9]+]] = distinct !DISubprogram(name: "foo",{{.*}} retainedNodes: ![[VARS:[0-9]+]] +; CHECK: ![[VARS]] = !{![[PARAM:[0-9]+]], ![[AUTO:[0-9]+]]} +; CHECK: ![[PARAM]] = !DILocalVariable(name: "param", arg: 1, scope: ![[SP]], memorySpace: DW_MSPACE_LLVM_group) +; CHECK: ![[AUTO]] = !DILocalVariable(name: "auto", scope: ![[SP]], memorySpace: DW_MSPACE_LLVM_private) + +!named = !{!0} + +!llvm.module.flags = !{!6} +!llvm.dbg.cu = !{!4} + +!0 = distinct !DISubprogram(name: "foo", scope: null, isLocal: false, isDefinition: true, isOptimized: false, unit: !4, retainedNodes: !1) +!1 = !{!2, !3} +!2 = !DILocalVariable(name: "param", arg: 1, scope: !0, memorySpace: DW_MSPACE_LLVM_group) +!3 = !DILocalVariable(name: "auto", scope: !0, memorySpace: DW_MSPACE_LLVM_private) +!4 = distinct !DICompileUnit(language: DW_LANG_C99, file: !5) +!5 = !DIFile(filename: "source.c", directory: "/dir") +!6 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/llvm/test/Bitcode/DIPtrRef-address-space.ll b/llvm/test/Bitcode/DIPtrRef-address-space.ll new file mode 100644 index 0000000000000..c8ffd7f9a3cc7 --- /dev/null +++ b/llvm/test/Bitcode/DIPtrRef-address-space.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as %s -o - | llvm-dis | FileCheck %s + +; CHECK-DAG: ![[BASIC:[0-9]+]] = !DIBasicType +; CHECK-DAG: !DIDerivedType(tag: DW_TAG_pointer_type, baseType: ![[BASIC]], addressSpace: 1, memorySpace: DW_MSPACE_LLVM_private) +; CHECK-DAG: !DIDerivedType(tag: DW_TAG_reference_type, baseType: ![[BASIC]], addressSpace: 1, memorySpace: DW_MSPACE_LLVM_private) + +!named = !{!0, !1} + +!0 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !2, addressSpace: 1, memorySpace: DW_MSPACE_LLVM_private) +!1 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !2, addressSpace: 1, memorySpace: 4) +!2 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) diff --git a/llvm/test/Bitcode/bcanalyzer-metadata-diexpression.ll b/llvm/test/Bitcode/bcanalyzer-metadata-diexpression.ll new file mode 100644 index 0000000000000..541ba3e751f25 --- /dev/null +++ b/llvm/test/Bitcode/bcanalyzer-metadata-diexpression.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llvm-bcanalyzer -dump | FileCheck %s + +!named = !{!0, !1} + +%t = type { i32, i32 } + +; CHECK: +!0 = !DIExpression(DIOpReferrer(%t)) +; CHECK: +!1 = !DIExpression() diff --git a/llvm/test/BugPoint/attr-crash.ll b/llvm/test/BugPoint/attr-crash.ll index c79671a00dba6..e51aa4c2f3229 100644 --- a/llvm/test/BugPoint/attr-crash.ll +++ b/llvm/test/BugPoint/attr-crash.ll @@ -1,4 +1,4 @@ -; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%pluginext %s -output-prefix %t -bugpoint-crashfuncattr 2>&1 | FileCheck %s +; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%pluginext %s -output-prefix %t -bugpoint-crashfuncattr 2>&1 | FileCheck %s ; REQUIRES: plugins ; ; ModuleID = 'attr-crash.ll' diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll index 9f398b4a9d3b1..649609fcf73e9 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extract-used-by-dbg.ll @@ -325,7 +325,7 @@ attributes #1 = { "target-cpu"="generic" } !297 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Custom", scope: !284, file: !4, size: 128, align: 64, elements: !298, templateParams: !228, identifier: "df1a28723e4e04a13efa60934df6c3a6::Custom") !298 = !{!299} !299 = !DIDerivedType(tag: DW_TAG_member, name: "__0", scope: !297, file: !4, baseType: !300, size: 64, align: 64, offset: 64) -!300 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "Box", baseType: !301, size: 64, align: 64, dwarfAddressSpace: 0) +!300 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "Box", baseType: !301, size: 64, align: 64, addressSpace: 0) !301 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Custom", scope: !46, file: !4, size: 192, align: 64, elements: !302, templateParams: !228, identifier: "91f6b80e351df08f3582a1dba78d37a4") !302 = !{!303, !304} !303 = !DIDerivedType(tag: DW_TAG_member, name: "kind", scope: !301, file: !4, baseType: !45, size: 8, align: 8, offset: 128) @@ -334,9 +334,9 @@ attributes #1 = { "target-cpu"="generic" } !306 = !DINamespace(name: "error", scope: !48) !307 = !{!308, !310} !308 = !DIDerivedType(tag: DW_TAG_member, name: "pointer", scope: !305, file: !4, baseType: !309, size: 64, align: 64, flags: DIFlagArtificial) -!309 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*mut u8", baseType: !7, size: 64, align: 64, dwarfAddressSpace: 0) +!309 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*mut u8", baseType: !7, size: 64, align: 64, addressSpace: 0) !310 = !DIDerivedType(tag: DW_TAG_member, name: "vtable", scope: !305, file: !4, baseType: !311, size: 64, align: 64, offset: 64, flags: DIFlagArtificial) -!311 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&[usize; 3]", baseType: !312, size: 64, align: 64, dwarfAddressSpace: 0) +!311 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&[usize; 3]", baseType: !312, size: 64, align: 64, addressSpace: 0) !312 = !DICompositeType(tag: DW_TAG_array_type, baseType: !313, size: 192, align: 64, elements: !314) !313 = !DIBasicType(name: "usize", size: 64, encoding: DW_ATE_unsigned) !314 = !{!315} @@ -353,7 +353,7 @@ attributes #1 = { "target-cpu"="generic" } !325 = !{!326} !326 = !DIDerivedType(tag: DW_TAG_member, name: "__0", scope: !324, file: !4, baseType: !281, size: 128, align: 64, offset: 64) !327 = !DIDerivedType(tag: DW_TAG_member, scope: !32, file: !4, baseType: !254, size: 64, align: 64, flags: DIFlagArtificial) -!328 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&std::path::Path", baseType: !329, size: 128, align: 64, dwarfAddressSpace: 0) +!328 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&std::path::Path", baseType: !329, size: 128, align: 64, addressSpace: 0) !329 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Path", scope: !84, file: !4, align: 8, elements: !330, templateParams: !228, identifier: "59d4ec63209a24516bd1bdae88116f75") !330 = !{!331} !331 = !DIDerivedType(tag: DW_TAG_member, name: "inner", scope: !329, file: !4, baseType: !332, align: 8) @@ -381,7 +381,7 @@ attributes #1 = { "target-cpu"="generic" } !353 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "alloc::boxed::Box<[u8]>", file: !4, size: 128, align: 64, elements: !354, templateParams: !358, identifier: "402fa17fda502b3dfe8af04b4513434e") !354 = !{!355, !357} !355 = !DIDerivedType(tag: DW_TAG_member, name: "data_ptr", scope: !353, file: !4, baseType: !356, size: 64, align: 64) -!356 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*const u8", baseType: !7, size: 64, align: 64, dwarfAddressSpace: 0) +!356 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*const u8", baseType: !7, size: 64, align: 64, addressSpace: 0) !357 = !DIDerivedType(tag: DW_TAG_member, name: "length", scope: !353, file: !4, baseType: !313, size: 64, align: 64, offset: 64) !358 = !{!359} !359 = !DITemplateTypeParameter(name: "T", type: !342) diff --git a/llvm/test/CodeGen/AArch64/PHIElimination-reuse-copy.mir b/llvm/test/CodeGen/AArch64/PHIElimination-reuse-copy.mir new file mode 100644 index 0000000000000..fb32b3189f4d5 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/PHIElimination-reuse-copy.mir @@ -0,0 +1,197 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -run-pass=livevars,phi-node-elimination -verify-machineinstrs -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s + +# Verify that the original COPY in bb.1 is reappropriated as the PHI source in bb.2, +# instead of creating a new COPY with the same source register. + +--- +name: copy_virtual_reg +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: copy_virtual_reg + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $nzcv, $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %a:gpr32 = COPY killed $w0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF + ; CHECK-NEXT: Bcc 8, %bb.2, implicit killed $nzcv + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %b:gpr32 = COPY killed %a + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = COPY killed %b + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: %c:gpr32 = COPY killed [[DEF]] + ; CHECK-NEXT: dead %d:gpr32 = COPY killed %c + bb.0: + liveins: $nzcv, $w0 + %a:gpr32 = COPY $w0 + Bcc 8, %bb.2, implicit $nzcv + bb.1: + %b:gpr32 = COPY %a:gpr32 + bb.2: + %c:gpr32 = PHI %b:gpr32, %bb.1, undef %undef:gpr32, %bb.0 + %d:gpr32 = COPY %c:gpr32 +... + +--- +name: copy_physical_reg +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: copy_physical_reg + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $nzcv, $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF + ; CHECK-NEXT: Bcc 8, %bb.2, implicit killed $nzcv + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = IMPLICIT_DEF implicit-def $w0 + ; CHECK-NEXT: %a:gpr32 = COPY killed $w0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = COPY killed %a + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: dead %b:gpr32 = COPY killed [[DEF]] + bb.0: + liveins: $nzcv, $w0 + Bcc 8, %bb.2, implicit $nzcv + bb.1: + $x0 = IMPLICIT_DEF + %a:gpr32 = COPY $w0 + bb.2: + %b:gpr32 = PHI %a:gpr32, %bb.1, undef %undef:gpr32, %bb.0 +... + +--- +name: copy_to_dead +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: copy_to_dead + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $wzr, $xzr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $wzr + ; CHECK-NEXT: dead [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr + ; CHECK-NEXT: TBZW killed [[COPY]], 0, %bb.2 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:gpr64 = IMPLICIT_DEF + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[DEF2:%[0-9]+]]:gpr64 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF3:%[0-9]+]]:gpr64 = IMPLICIT_DEF + ; CHECK-NEXT: B %bb.1 + bb.0: + liveins: $wzr, $xzr + + %9:gpr32 = COPY $wzr + dead %5:gpr64 = COPY $xzr + TBZW killed %9:gpr32, 0, %bb.2 + B %bb.1 + + bb.1: + successors: %bb.2(0x80000000); %bb.2(100.00%) + + dead %1:gpr64 = PHI undef %3:gpr64, %bb.2, undef %5:gpr64, %bb.0 + dead %2:gpr64 = PHI undef %4:gpr64, %bb.2, undef %5:gpr64, %bb.0 + B %bb.2 + + bb.2: + successors: %bb.1(0x80000000); %bb.1(100.00%) + + dead %3:gpr64 = PHI undef %1:gpr64, %bb.1, undef %5:gpr64, %bb.0 + dead %4:gpr64 = PHI undef %2:gpr64, %bb.1, undef %5:gpr64, %bb.0 + B %bb.1 + +... + +--- +name: update_livevars +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: update_livevars + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $w0, $w1, $nzcv + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY killed $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY killed $w1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY killed [[COPY1]] + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $nzcv + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[COPY3:%[0-9]+]]:gpr32 = COPY killed [[COPY2]] + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY4]] + ; CHECK-NEXT: Bcc 1, %bb.1, implicit $nzcv + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $nzcv + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY killed [[COPY4]] + ; CHECK-NEXT: B %bb.1 + bb.0: + successors: %bb.1 + liveins: $w0, $w1, $nzcv + + %0:gpr32 = COPY killed $w0 + %1:gpr32 = COPY killed $w1 + B %bb.1 + + bb.1: + successors: %bb.2, %bb.1 + liveins: $nzcv + + %2:gpr32 = PHI %3, %bb.2, %1, %bb.0, %3, %bb.1 + %3:gpr32 = COPY %0 + Bcc 1, %bb.1, implicit $nzcv + + bb.2: + successors: %bb.1 + liveins: $nzcv + + B %bb.1 +... + +--- +name: copy_subreg +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: copy_subreg + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY killed $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY killed [[COPY]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: dead [[COPY2:%[0-9]+]]:gpr32 = COPY killed [[COPY1]].sub_32 + bb.0: + successors: %bb.1 + liveins: $x0 + + %0:gpr64 = COPY killed $x0 + %1:gpr64 = COPY killed %0 + + bb.1: + %2:gpr32 = PHI %1.sub_32, %bb.0 +... diff --git a/llvm/test/CodeGen/AArch64/dwarf-eh-prepare-dbg.ll b/llvm/test/CodeGen/AArch64/dwarf-eh-prepare-dbg.ll index 020a10f278ed6..1c1004d846b4c 100644 --- a/llvm/test/CodeGen/AArch64/dwarf-eh-prepare-dbg.ll +++ b/llvm/test/CodeGen/AArch64/dwarf-eh-prepare-dbg.ll @@ -186,7 +186,7 @@ attributes #2 = { noreturn } !124 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "&[u8]", file: !5, size: 128, align: 64, elements: !125, templateParams: !46, identifier: "31681e0c10b314f1f33e38b2779acbb4") !125 = !{!126, !128} !126 = !DIDerivedType(tag: DW_TAG_member, name: "data_ptr", scope: !124, file: !5, baseType: !127, size: 64, align: 64) -!127 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !26, size: 64, align: 64, dwarfAddressSpace: 0) +!127 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !26, size: 64, align: 64, addressSpace: 0) !128 = !DIDerivedType(tag: DW_TAG_member, name: "length", scope: !124, file: !5, baseType: !21, size: 64, align: 64, offset: 64) !129 = !DIDerivedType(tag: DW_TAG_member, name: "endian", scope: !120, file: !5, baseType: !130, align: 8, offset: 128, flags: DIFlagPrivate) !130 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "LittleEndian", scope: !131, file: !5, align: 8, flags: DIFlagPublic, elements: !46, identifier: "3d0f5d089fd1d1e4e850cd8b54585231") @@ -608,8 +608,8 @@ attributes #2 = { noreturn } !546 = !{!547} !547 = !DIDerivedType(tag: DW_TAG_member, name: "__0", scope: !545, file: !5, baseType: !315, size: 128, align: 64, flags: DIFlagPublic) !548 = !DIDerivedType(tag: DW_TAG_member, scope: !304, file: !5, baseType: !26, size: 8, align: 8, flags: DIFlagArtificial) -!549 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&unwinding::unwinder::frame::Frame", baseType: !4, size: 64, align: 64, dwarfAddressSpace: 0) -!550 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&unwinding::unwinder::arch::aarch64::Context", baseType: !551, size: 64, align: 64, dwarfAddressSpace: 0) +!549 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&unwinding::unwinder::frame::Frame", baseType: !4, size: 64, align: 64, addressSpace: 0) +!550 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&unwinding::unwinder::arch::aarch64::Context", baseType: !551, size: 64, align: 64, addressSpace: 0) !551 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Context", scope: !552, file: !5, size: 4096, align: 64, flags: DIFlagPublic, elements: !554, templateParams: !46, identifier: "8e981de74a115bb4264fb06b8de66f0") !552 = !DINamespace(name: "aarch64", scope: !553) !553 = !DINamespace(name: "arch", scope: !7) @@ -662,7 +662,7 @@ attributes #2 = { noreturn } !600 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "::{vtable_type}", file: !5, size: 256, align: 64, flags: DIFlagArtificial, elements: !601, vtableHolder: !315, templateParams: !46, identifier: "1f97312b991e7e51c27c8ed2941b7252") !601 = !{!602, !604, !605, !606} !602 = !DIDerivedType(tag: DW_TAG_member, name: "drop_in_place", scope: !600, file: !5, baseType: !603, size: 64, align: 64) -!603 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*const ()", baseType: !246, size: 64, align: 64, dwarfAddressSpace: 0) +!603 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*const ()", baseType: !246, size: 64, align: 64, addressSpace: 0) !604 = !DIDerivedType(tag: DW_TAG_member, name: "size", scope: !600, file: !5, baseType: !21, size: 64, align: 64, offset: 64) !605 = !DIDerivedType(tag: DW_TAG_member, name: "align", scope: !600, file: !5, baseType: !21, size: 64, align: 64, offset: 128) !606 = !DIDerivedType(tag: DW_TAG_member, name: "__method3", scope: !600, file: !5, baseType: !603, size: 64, align: 64, offset: 192) @@ -1055,7 +1055,7 @@ attributes #2 = { noreturn } !993 = distinct !DILexicalBlock(scope: !874, file: !3, line: 111, column: 56) !994 = !DILocalVariable(name: "val", scope: !995, file: !3, line: 108, type: !996, align: 8) !995 = distinct !DILexicalBlock(scope: !874, file: !3, line: 108, column: 19) -!996 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&gimli::read::op::Piece, usize>", baseType: !828, size: 64, align: 64, dwarfAddressSpace: 0) +!996 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&gimli::read::op::Piece, usize>", baseType: !828, size: 64, align: 64, addressSpace: 0) !997 = !DILocalVariable(name: "address", scope: !998, file: !3, line: 114, type: !90, align: 8) !998 = distinct !DILexicalBlock(scope: !874, file: !3, line: 114, column: 17) !999 = !DILocation(line: 1102, column: 23, scope: !1000, inlinedAt: !1038) @@ -1079,7 +1079,7 @@ attributes #2 = { noreturn } !1017 = !DIDerivedType(tag: DW_TAG_member, scope: !1003, file: !5, baseType: !90, size: 64, align: 64, flags: DIFlagArtificial) !1018 = !DISubroutineType(types: !1019) !1019 = !{!614, !1003, !1020} -!1020 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&core::panic::location::Location", baseType: !1021, size: 64, align: 64, dwarfAddressSpace: 0) +!1020 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&core::panic::location::Location", baseType: !1021, size: 64, align: 64, addressSpace: 0) !1021 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Location", scope: !1022, file: !5, size: 192, align: 64, flags: DIFlagPublic, elements: !1024, templateParams: !46, identifier: "e063870a552be7101e2bcd793a8716b0") !1022 = !DINamespace(name: "location", scope: !1023) !1023 = !DINamespace(name: "panic", scope: !40) @@ -1102,7 +1102,7 @@ attributes #2 = { noreturn } !1040 = !DIFile(filename: "src/unwinder/mod.rs", directory: "/home/dev/ecosystem/unwinding", checksumkind: CSK_MD5, checksum: "0b7cd150e86dd087aeaa8e0e18bae6d9") !1041 = !DISubroutineType(types: !1042) !1042 = !{null, !1043} -!1043 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*mut unwinding::unwinder::UnwindException", baseType: !1044, size: 64, align: 64, dwarfAddressSpace: 0) +!1043 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*mut unwinding::unwinder::UnwindException", baseType: !1044, size: 64, align: 64, addressSpace: 0) !1044 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "UnwindException", scope: !7, file: !5, size: 256, align: 64, flags: DIFlagPublic, elements: !1045, templateParams: !46, identifier: "f6e359707e96b28f68e0123bb3490311") !1045 = !{!1046, !1047, !1068, !1109, !1110} !1046 = !DIDerivedType(tag: DW_TAG_member, name: "exception_class", scope: !1044, file: !5, baseType: !90, size: 64, align: 64, flags: DIFlagPublic) @@ -1115,7 +1115,7 @@ attributes #2 = { noreturn } !1053 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "None", scope: !1048, file: !5, size: 64, align: 64, flags: DIFlagPublic, elements: !46, templateParams: !1054, identifier: "5f49070303e2d908386f0a327220e7") !1054 = !{!1055} !1055 = !DITemplateTypeParameter(name: "T", type: !1056) -!1056 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "unsafe extern \22C\22 fn(unwinding::abi::UnwindReasonCode, *mut unwinding::unwinder::UnwindException)", baseType: !1057, size: 64, align: 64, dwarfAddressSpace: 0) +!1056 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "unsafe extern \22C\22 fn(unwinding::abi::UnwindReasonCode, *mut unwinding::unwinder::UnwindException)", baseType: !1057, size: 64, align: 64, addressSpace: 0) !1057 = !DISubroutineType(types: !1058) !1058 = !{null, !1059, !1043} !1059 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "UnwindReasonCode", scope: !1060, file: !5, size: 32, align: 32, flags: DIFlagPublic, elements: !1061, templateParams: !46, identifier: "78d1c20b6f4c6f13f91e6941a59e3070") @@ -1136,13 +1136,13 @@ attributes #2 = { noreturn } !1074 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "None", scope: !1069, file: !5, size: 64, align: 64, flags: DIFlagPublic, elements: !46, templateParams: !1075, identifier: "a7907e0a0f03f43538101bc2ae5b0cc9") !1075 = !{!1076} !1076 = !DITemplateTypeParameter(name: "T", type: !1077) -!1077 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "unsafe extern \22C\22 fn(i32, unwinding::abi::UnwindAction, u64, *mut unwinding::unwinder::UnwindException, &mut unwinding::unwinder::UnwindContext, *mut core::ffi::c_void) -> unwinding::abi::UnwindReasonCode", baseType: !1078, size: 64, align: 64, dwarfAddressSpace: 0) +!1077 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "unsafe extern \22C\22 fn(i32, unwinding::abi::UnwindAction, u64, *mut unwinding::unwinder::UnwindException, &mut unwinding::unwinder::UnwindContext, *mut core::ffi::c_void) -> unwinding::abi::UnwindReasonCode", baseType: !1078, size: 64, align: 64, addressSpace: 0) !1078 = !DISubroutineType(types: !1079) !1079 = !{!1059, !747, !1080, !90, !1043, !1083, !1103} !1080 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "UnwindAction", scope: !1060, file: !5, size: 32, align: 32, flags: DIFlagPublic, elements: !1081, templateParams: !46, identifier: "364c99c0f0ff127f318feffefcb3c87") !1081 = !{!1082} !1082 = !DIDerivedType(tag: DW_TAG_member, name: "__0", scope: !1080, file: !5, baseType: !747, size: 32, align: 32, flags: DIFlagPublic) -!1083 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&mut unwinding::unwinder::UnwindContext", baseType: !1084, size: 64, align: 64, dwarfAddressSpace: 0) +!1083 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&mut unwinding::unwinder::UnwindContext", baseType: !1084, size: 64, align: 64, addressSpace: 0) !1084 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "UnwindContext", scope: !7, file: !5, size: 192, align: 64, flags: DIFlagPublic, elements: !1085, templateParams: !46, identifier: "911f8c19bc1f5e24ad054a625f8be0d6") !1085 = !{!1086, !1100, !1102} !1086 = !DIDerivedType(tag: DW_TAG_member, name: "frame", scope: !1084, file: !5, baseType: !1087, size: 64, align: 64, offset: 64, flags: DIFlagPrivate) @@ -1160,9 +1160,9 @@ attributes #2 = { noreturn } !1098 = !DIDerivedType(tag: DW_TAG_member, name: "__0", scope: !1096, file: !5, baseType: !549, size: 64, align: 64, flags: DIFlagPublic) !1099 = !DIDerivedType(tag: DW_TAG_member, scope: !1087, file: !5, baseType: !90, size: 64, align: 64, flags: DIFlagArtificial) !1100 = !DIDerivedType(tag: DW_TAG_member, name: "ctx", scope: !1084, file: !5, baseType: !1101, size: 64, align: 64, flags: DIFlagPrivate) -!1101 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&mut unwinding::unwinder::arch::aarch64::Context", baseType: !551, size: 64, align: 64, dwarfAddressSpace: 0) +!1101 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&mut unwinding::unwinder::arch::aarch64::Context", baseType: !551, size: 64, align: 64, addressSpace: 0) !1102 = !DIDerivedType(tag: DW_TAG_member, name: "signal", scope: !1084, file: !5, baseType: !103, size: 8, align: 8, offset: 128, flags: DIFlagPrivate) -!1103 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*mut core::ffi::c_void", baseType: !586, size: 64, align: 64, dwarfAddressSpace: 0) +!1103 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*mut core::ffi::c_void", baseType: !586, size: 64, align: 64, addressSpace: 0) !1104 = !DIDerivedType(tag: DW_TAG_member, name: "Some", scope: !1071, file: !5, baseType: !1105, size: 64, align: 64) !1105 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Some", scope: !1069, file: !5, size: 64, align: 64, flags: DIFlagPublic, elements: !1106, templateParams: !1075, identifier: "757604dfadcc7bc333dd8afe5c3f1b07") !1106 = !{!1107} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll index b84b31cd2702c..2a5c8be7a987a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll @@ -13,20 +13,20 @@ define ptr addrspace(1) @call_assert_align() { ; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[18:19] ; CHECK-NEXT: v_writelane_b32 v40, s16, 2 -; CHECK-NEXT: s_addk_i32 s32, 0x400 ; CHECK-NEXT: v_writelane_b32 v40, s30, 0 +; CHECK-NEXT: s_addk_i32 s32, 0x400 +; CHECK-NEXT: v_writelane_b32 v40, s31, 1 ; CHECK-NEXT: s_getpc_b64 s[16:17] ; CHECK-NEXT: s_add_u32 s16, s16, ext@rel32@lo+4 ; CHECK-NEXT: s_addc_u32 s17, s17, ext@rel32@hi+12 ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0 -; CHECK-NEXT: v_writelane_b32 v40, s31, 1 ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] ; CHECK-NEXT: v_mov_b32_e32 v2, 0 +; CHECK-NEXT: v_readlane_b32 s30, v40, 0 ; CHECK-NEXT: global_store_dword v[0:1], v2, off ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: v_readlane_b32 s31, v40, 1 -; CHECK-NEXT: v_readlane_b32 s30, v40, 0 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: v_readlane_b32 s4, v40, 2 ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll index c16c8e2128c72..3e3e788b2f31d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll @@ -222,24 +222,24 @@ define void @func_caller_stack() { ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] +; MUBUF-NEXT: v_writelane_b32 v40, s4, 2 +; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 ; MUBUF-NEXT: s_addk_i32 s32, 0x400 +; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 ; MUBUF-NEXT: v_mov_b32_e32 v0, 9 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; MUBUF-NEXT: v_mov_b32_e32 v0, 10 -; MUBUF-NEXT: v_writelane_b32 v40, s4, 2 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; MUBUF-NEXT: v_mov_b32_e32 v0, 11 -; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; MUBUF-NEXT: v_mov_b32_e32 v0, 12 ; MUBUF-NEXT: s_getpc_b64 s[4:5] ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_v16i32_v16i32_v4i32@rel32@lo+4 ; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_v16i32_v16i32_v4i32@rel32@hi+12 -; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5] -; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 ; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 +; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: v_readlane_b32 s4, v40, 2 ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -257,8 +257,10 @@ define void @func_caller_stack() { ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 ; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] -; FLATSCR-NEXT: s_add_i32 s32, s32, 16 ; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2 +; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 +; FLATSCR-NEXT: s_add_i32 s32, s32, 16 +; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: s_add_u32 s0, s32, 4 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 9 ; FLATSCR-NEXT: scratch_store_dword off, v0, s0 @@ -270,15 +272,13 @@ define void @func_caller_stack() { ; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; FLATSCR-NEXT: s_add_u32 s0, s32, 16 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 12 -; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 ; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; FLATSCR-NEXT: s_getpc_b64 s[0:1] ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_v16i32_v16i32_v4i32@rel32@lo+4 ; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_v16i32_v16i32_v4i32@rel32@hi+12 -; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1] -; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 ; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 +; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: v_readlane_b32 s0, v40, 2 ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 @@ -300,15 +300,15 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) { ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] -; MUBUF-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen -; MUBUF-NEXT: buffer_load_dword v2, v0, s[0:3], 0 offen offset:4 -; MUBUF-NEXT: s_addk_i32 s32, 0x400 ; MUBUF-NEXT: v_writelane_b32 v40, s4, 2 ; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 +; MUBUF-NEXT: s_addk_i32 s32, 0x400 +; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 +; MUBUF-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen +; MUBUF-NEXT: buffer_load_dword v2, v0, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: s_getpc_b64 s[4:5] ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_byval@rel32@lo+4 ; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_byval@rel32@hi+12 -; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 ; MUBUF-NEXT: s_waitcnt vmcnt(1) ; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; MUBUF-NEXT: s_waitcnt vmcnt(1) @@ -363,8 +363,8 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) { ; MUBUF-NEXT: s_waitcnt vmcnt(1) ; MUBUF-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60 ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5] -; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 ; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 +; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: v_readlane_b32 s4, v40, 2 ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -382,14 +382,14 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) { ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 ; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] -; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off -; FLATSCR-NEXT: s_add_i32 s32, s32, 16 ; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2 ; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 +; FLATSCR-NEXT: s_add_i32 s32, s32, 16 +; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 +; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off ; FLATSCR-NEXT: s_getpc_b64 s[0:1] ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_byval@rel32@lo+4 ; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_byval@rel32@hi+12 -; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s32 ; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off offset:8 @@ -414,8 +414,8 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) { ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s32 offset:56 ; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1] -; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 ; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 +; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: v_readlane_b32 s0, v40, 2 ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll index 8cb9a5486a2de..b17324a38ada0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll @@ -363,7 +363,6 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX9-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: s_mov_b32 s33, s6 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX9-NEXT: s_add_u32 s5, s32, 0x7ff @@ -377,6 +376,7 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX9-NEXT: s_add_u32 s32, s5, s4 ; GFX9-NEXT: s_mov_b32 s32, s34 ; GFX9-NEXT: s_mov_b32 s34, s7 +; GFX9-NEXT: s_mov_b32 s33, s6 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -394,7 +394,6 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX10-NEXT: s_mov_b32 s33, s6 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_add_u32 s5, s32, 0x3ff @@ -408,6 +407,7 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX10-NEXT: s_add_u32 s32, s5, s4 ; GFX10-NEXT: s_mov_b32 s32, s34 ; GFX10-NEXT: s_mov_b32 s34, s7 +; GFX10-NEXT: s_mov_b32 s33, s6 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: func_dynamic_stackalloc_sgpr_align32: @@ -424,7 +424,6 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX11-NEXT: s_addc_u32 s1, s1, gv@gotpcrel32@hi+12 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: s_mov_b32 s33, s2 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_add_u32 s1, s32, 0x3ff @@ -439,6 +438,7 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX11-NEXT: s_add_u32 s32, s1, s0 ; GFX11-NEXT: s_mov_b32 s32, s34 ; GFX11-NEXT: s_mov_b32 s34, s3 +; GFX11-NEXT: s_mov_b32 s33, s2 ; GFX11-NEXT: s_setpc_b64 s[30:31] %n = load i32, ptr addrspace(4) @gv %alloca = alloca i32, i32 %n, align 32, addrspace(5) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir index 45a129283dfcc..9af1a8d86e907 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir @@ -21,18 +21,16 @@ body: | liveins: $sgpr0, $vgpr0 ; WAVE32-LABEL: name: class_s16_vcc_sv ; WAVE32: liveins: $sgpr0, $vgpr0 - ; WAVE32-NEXT: {{ $}} - ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec - ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] + ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec + ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] ; WAVE64-LABEL: name: class_s16_vcc_sv ; WAVE64: liveins: $sgpr0, $vgpr0 - ; WAVE64-NEXT: {{ $}} - ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec - ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] + ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec + ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] %0:sgpr(s32) = COPY $sgpr0 %1:vgpr(s32) = COPY $vgpr0 %2:sgpr(s16) = G_TRUNC %0 @@ -51,18 +49,16 @@ body: | liveins: $sgpr0, $vgpr0 ; WAVE32-LABEL: name: class_s16_vcc_vs ; WAVE32: liveins: $sgpr0, $vgpr0 - ; WAVE32-NEXT: {{ $}} - ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec - ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] + ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec + ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] ; WAVE64-LABEL: name: class_s16_vcc_vs ; WAVE64: liveins: $sgpr0, $vgpr0 - ; WAVE64-NEXT: {{ $}} - ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec - ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] + ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec + ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] %0:vgpr(s32) = COPY $vgpr0 %1:sgpr(s32) = COPY $sgpr0 %2:vgpr(s16) = G_TRUNC %0 @@ -81,18 +77,16 @@ body: | liveins: $vgpr0, $vgpr1 ; WAVE32-LABEL: name: class_s16_vcc_vv ; WAVE32: liveins: $vgpr0, $vgpr1 - ; WAVE32-NEXT: {{ $}} - ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec - ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] + ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec + ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] ; WAVE64-LABEL: name: class_s16_vcc_vv ; WAVE64: liveins: $vgpr0, $vgpr1 - ; WAVE64-NEXT: {{ $}} - ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec - ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] + ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec + ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]] %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr1 %2:vgpr(s16) = G_TRUNC %0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir index 94175c5f3037f..8258183edc60d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir @@ -17,10 +17,9 @@ body: | ; CHECK-LABEL: name: cos_s16_vs ; CHECK: liveins: $sgpr0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; CHECK-NEXT: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_COS_F16_e64_]] + ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK: S_ENDPGM 0, implicit [[V_COS_F16_e64_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1 @@ -39,10 +38,9 @@ body: | ; CHECK-LABEL: name: cos_s16_vv ; CHECK: liveins: $vgpr0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-NEXT: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_COS_F16_e64_]] + ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK: %2:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK: S_ENDPGM 0, implicit %2 %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir index 5840f6255cb29..3531ef8b3a6b7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir @@ -18,12 +18,11 @@ body: | ; GCN-LABEL: name: fmed3_s16_vvvv ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2 - ; GCN-NEXT: {{ $}} - ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GCN-NEXT: [[V_MED3_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec - ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F16_e64_]] + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GCN: %6:vgpr_32 = nofpexcept V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec + ; GCN: S_ENDPGM 0, implicit %6 %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr2 @@ -46,12 +45,11 @@ body: | ; GCN-LABEL: name: fmed3_s16_vsvv ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1 - ; GCN-NEXT: {{ $}} - ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GCN-NEXT: [[V_MED3_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec - ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F16_e64_]] + ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GCN: %6:vgpr_32 = nofpexcept V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec + ; GCN: S_ENDPGM 0, implicit %6 %0:sgpr(s32) = COPY $sgpr0 %1:vgpr(s32) = COPY $vgpr0 %2:vgpr(s32) = COPY $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir index 64c4f875e9719..cead615dd5990 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir @@ -18,10 +18,9 @@ body: | ; CHECK-LABEL: name: fract_s16_vs ; CHECK: liveins: $sgpr0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; CHECK-NEXT: [[V_FRACT_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FRACT_F16_e64_]] + ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK: %2:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK: S_ENDPGM 0, implicit %2 %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1 @@ -40,10 +39,9 @@ body: | ; CHECK-LABEL: name: fract_s16_vv ; CHECK: liveins: $vgpr0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-NEXT: [[V_FRACT_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FRACT_F16_e64_]] + ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK: %2:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK: S_ENDPGM 0, implicit %2 %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir index 1834177009c1a..fb09df6be4f37 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir @@ -17,10 +17,9 @@ body: | ; CHECK-LABEL: name: rcp_s16_vs ; CHECK: liveins: $sgpr0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; CHECK-NEXT: [[V_RCP_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RCP_F16_e64_]] + ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK: %2:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK: S_ENDPGM 0, implicit %2 %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1 @@ -39,10 +38,9 @@ body: | ; CHECK-LABEL: name: rcp_s16_vv ; CHECK: liveins: $vgpr0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-NEXT: [[V_RCP_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RCP_F16_e64_]] + ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK: %2:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK: S_ENDPGM 0, implicit %2 %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir index fce84c451847f..951010af39c01 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir @@ -17,10 +17,9 @@ body: | ; CHECK-LABEL: name: rsq_s16_vs ; CHECK: liveins: $sgpr0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; CHECK-NEXT: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]] + ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK: %2:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK: S_ENDPGM 0, implicit %2 %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1 @@ -39,10 +38,9 @@ body: | ; CHECK-LABEL: name: rsq_s16_vv ; CHECK: liveins: $vgpr0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-NEXT: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]] + ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK: %2:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK: S_ENDPGM 0, implicit %2 %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir index 7ab374f5853a3..35b602593dbe7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir @@ -17,10 +17,9 @@ body: | ; CHECK-LABEL: name: sin_s16_vs ; CHECK: liveins: $sgpr0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; CHECK-NEXT: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]] + ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1 @@ -39,10 +38,9 @@ body: | ; CHECK-LABEL: name: sin_s16_vv ; CHECK: liveins: $vgpr0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-NEXT: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]] + ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK: %2:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK: S_ENDPGM 0, implicit %2 %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir index 5c2df3904b817..bec83e3b9a6e6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir @@ -318,9 +318,9 @@ body: | ; GFX6-NEXT: {{ $}} ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65535, implicit $exec - ; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec + ; GFX6-NEXT: %2:vgpr_32, dead %4:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX6-NEXT: $m0 = S_MOV_B32 -1 - ; GFX6-NEXT: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[V_ADD_CO_U32_e64_]], 0, 0, implicit $m0, implicit $exec :: (load seq_cst (s32), addrspace 3) + ; GFX6-NEXT: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 %2, 0, 0, implicit $m0, implicit $exec :: (load seq_cst (s32), addrspace 3) ; GFX6-NEXT: $vgpr0 = COPY [[DS_READ_B32_]] ; GFX7-LABEL: name: load_atomic_local_s32_seq_cst_gep_65535 ; GFX7: liveins: $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir index 94104885748a9..83e88dc2b266e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir @@ -148,9 +148,9 @@ body: | ; GFX7-NEXT: {{ $}} ; GFX7-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4000, implicit $exec - ; GFX7-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec + ; GFX7-NEXT: %2:vgpr_32, dead %4:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX7-NEXT: $m0 = S_MOV_B32 -1 - ; GFX7-NEXT: [[DS_READ2_B64_:%[0-9]+]]:vreg_128 = DS_READ2_B64 [[V_ADD_CO_U32_e64_]], 0, 1, 0, implicit $m0, implicit $exec :: (load (<4 x s32>), align 8, addrspace 3) + ; GFX7-NEXT: [[DS_READ2_B64_:%[0-9]+]]:vreg_128 = DS_READ2_B64 %2, 0, 1, 0, implicit $m0, implicit $exec :: (load (<4 x s32>), align 8, addrspace 3) ; GFX7-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DS_READ2_B64_]] ; GFX9-LABEL: name: load_local_v4s32_align_8_offset_320 ; GFX9: liveins: $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir index 59c57a5fefbed..cab82f143bae5 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir @@ -740,9 +740,9 @@ body: | ; GFX6-NEXT: {{ $}} ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65535, implicit $exec - ; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec + ; GFX6-NEXT: %2:vgpr_32, dead %4:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX6-NEXT: $m0 = S_MOV_B32 -1 - ; GFX6-NEXT: [[DS_READ_U8_:%[0-9]+]]:vgpr_32 = DS_READ_U8 [[V_ADD_CO_U32_e64_]], 0, 0, implicit $m0, implicit $exec :: (load (s8), addrspace 3) + ; GFX6-NEXT: [[DS_READ_U8_:%[0-9]+]]:vgpr_32 = DS_READ_U8 %2, 0, 0, implicit $m0, implicit $exec :: (load (s8), addrspace 3) ; GFX6-NEXT: $vgpr0 = COPY [[DS_READ_U8_]] ; ; GFX7-LABEL: name: load_local_s32_from_1_gep_65535 @@ -849,9 +849,9 @@ body: | ; GFX6-NEXT: {{ $}} ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65536, implicit $exec - ; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec + ; GFX6-NEXT: %2:vgpr_32, dead %4:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX6-NEXT: $m0 = S_MOV_B32 -1 - ; GFX6-NEXT: [[DS_READ_U8_:%[0-9]+]]:vgpr_32 = DS_READ_U8 [[V_ADD_CO_U32_e64_]], 0, 0, implicit $m0, implicit $exec :: (load (s8), addrspace 3) + ; GFX6-NEXT: [[DS_READ_U8_:%[0-9]+]]:vgpr_32 = DS_READ_U8 %2, 0, 0, implicit $m0, implicit $exec :: (load (s8), addrspace 3) ; GFX6-NEXT: $vgpr0 = COPY [[DS_READ_U8_]] ; ; GFX7-LABEL: name: load_local_s32_from_1_gep_65536 @@ -859,9 +859,9 @@ body: | ; GFX7-NEXT: {{ $}} ; GFX7-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65536, implicit $exec - ; GFX7-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec + ; GFX7-NEXT: %2:vgpr_32, dead %4:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX7-NEXT: $m0 = S_MOV_B32 -1 - ; GFX7-NEXT: [[DS_READ_U8_:%[0-9]+]]:vgpr_32 = DS_READ_U8 [[V_ADD_CO_U32_e64_]], 0, 0, implicit $m0, implicit $exec :: (load (s8), addrspace 3) + ; GFX7-NEXT: [[DS_READ_U8_:%[0-9]+]]:vgpr_32 = DS_READ_U8 %2, 0, 0, implicit $m0, implicit $exec :: (load (s8), addrspace 3) ; GFX7-NEXT: $vgpr0 = COPY [[DS_READ_U8_]] ; ; GFX9-LABEL: name: load_local_s32_from_1_gep_65536 @@ -905,9 +905,9 @@ body: | ; GFX6-NEXT: {{ $}} ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec - ; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec + ; GFX6-NEXT: %2:vgpr_32, dead %4:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX6-NEXT: $m0 = S_MOV_B32 -1 - ; GFX6-NEXT: [[DS_READ_U8_:%[0-9]+]]:vgpr_32 = DS_READ_U8 [[V_ADD_CO_U32_e64_]], 0, 0, implicit $m0, implicit $exec :: (load (s8), addrspace 3) + ; GFX6-NEXT: [[DS_READ_U8_:%[0-9]+]]:vgpr_32 = DS_READ_U8 %2, 0, 0, implicit $m0, implicit $exec :: (load (s8), addrspace 3) ; GFX6-NEXT: $vgpr0 = COPY [[DS_READ_U8_]] ; ; GFX7-LABEL: name: load_local_s32_from_1_gep_m1 @@ -915,9 +915,9 @@ body: | ; GFX7-NEXT: {{ $}} ; GFX7-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec - ; GFX7-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec + ; GFX7-NEXT: %2:vgpr_32, dead %4:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX7-NEXT: $m0 = S_MOV_B32 -1 - ; GFX7-NEXT: [[DS_READ_U8_:%[0-9]+]]:vgpr_32 = DS_READ_U8 [[V_ADD_CO_U32_e64_]], 0, 0, implicit $m0, implicit $exec :: (load (s8), addrspace 3) + ; GFX7-NEXT: [[DS_READ_U8_:%[0-9]+]]:vgpr_32 = DS_READ_U8 %2, 0, 0, implicit $m0, implicit $exec :: (load (s8), addrspace 3) ; GFX7-NEXT: $vgpr0 = COPY [[DS_READ_U8_]] ; ; GFX9-LABEL: name: load_local_s32_from_1_gep_m1 @@ -1021,9 +1021,9 @@ body: | ; GFX7-NEXT: {{ $}} ; GFX7-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1020, implicit $exec - ; GFX7-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec + ; GFX7-NEXT: %2:vgpr_32, dead %4:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX7-NEXT: $m0 = S_MOV_B32 -1 - ; GFX7-NEXT: [[DS_READ2_B32_:%[0-9]+]]:vreg_64 = DS_READ2_B32 [[V_ADD_CO_U32_e64_]], 0, 1, 0, implicit $m0, implicit $exec :: (load (s64), align 4, addrspace 3) + ; GFX7-NEXT: [[DS_READ2_B32_:%[0-9]+]]:vreg_64 = DS_READ2_B32 %2, 0, 1, 0, implicit $m0, implicit $exec :: (load (s64), align 4, addrspace 3) ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[DS_READ2_B32_]] ; ; GFX9-LABEL: name: load_local_s64_align4_from_1_gep_1020 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir index 1b7c0fcb76714..d72b2d5e401d2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir @@ -786,11 +786,11 @@ body: | ; GFX7-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX7-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1020, implicit $exec - ; GFX7-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], 0, implicit $exec + ; GFX7-NEXT: %3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX7-NEXT: $m0 = S_MOV_B32 -1 ; GFX7-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 ; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 - ; GFX7-NEXT: DS_WRITE2_B32 [[V_ADD_CO_U32_e64_]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $m0, implicit $exec :: (store (s64), align 4, addrspace 3) + ; GFX7-NEXT: DS_WRITE2_B32 %3, [[COPY3]], [[COPY2]], 0, 1, 0, implicit $m0, implicit $exec :: (store (s64), align 4, addrspace 3) ; GFX9-LABEL: name: store_local_s64_align4_from_1_gep_1020 ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2 ; GFX9-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll new file mode 100644 index 0000000000000..3318a308af959 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll @@ -0,0 +1,55 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-enable-lower-module-lds=false -o - %s 2> %t | FileCheck --check-prefix=GFX8 %s +; RUN: FileCheck -check-prefix=ERR %s < %t + +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-enable-lower-module-lds=false -o - %s 2> %t | FileCheck --check-prefix=GFX9 %s +; RUN: FileCheck -check-prefix=ERR %s < %t + +@lds = internal addrspace(3) global float undef, align 4 + +; ERR: warning: :0:0: in function func_use_lds_global void (): local memory global used by non-kernel function +define void @func_use_lds_global() { +; GFX8-LABEL: func_use_lds_global: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: s_mov_b64 s[4:5], 0xc8 +; GFX8-NEXT: v_mov_b32_e32 v0, 0 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_trap 2 +; GFX8-NEXT: ds_write_b32 v0, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: func_use_lds_global: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_trap 2 +; GFX9-NEXT: ds_write_b32 v0, v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + store float 0.0, ptr addrspace(3) @lds, align 4 + ret void +} + +; ERR: warning: :0:0: in function func_use_lds_global_constexpr_cast void (): local memory global used by non-kernel function +define void @func_use_lds_global_constexpr_cast() { +; GFX8-LABEL: func_use_lds_global_constexpr_cast: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: s_mov_b64 s[4:5], 0xc8 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_trap 2 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: func_use_lds_global_constexpr_cast: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_trap 2 +; GFX9-NEXT: s_setpc_b64 s[30:31] + store i32 ptrtoint (ptr addrspace(3) @lds to i32), ptr addrspace(1) undef, align 4 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir index 4328d47969a1e..05e3b2b724633 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir @@ -36,7 +36,7 @@ name: and_v2i16 body: | bb.1: - liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 ; GFX7-LABEL: name: and_v2i16 ; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 @@ -55,7 +55,7 @@ body: | ; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX7-NEXT: $vgpr0 = COPY [[BITCAST]](s32) ; GFX7-NEXT: $vgpr1 = COPY [[LSHR]](s32) - ; GFX7-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 + ; GFX7-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 %3:_(s32) = COPY $vgpr0 %4:_(s32) = COPY $vgpr1 %5:_(<2 x s32>) = G_BUILD_VECTOR %3(s32), %4(s32) @@ -70,7 +70,7 @@ body: | %12:_(s32) = G_ANYEXT %14(s16) $vgpr0 = COPY %11(s32) $vgpr1 = COPY %12(s32) - SI_RETURN implicit $vgpr0, implicit $vgpr1 + S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 ... @@ -78,7 +78,7 @@ body: | name: add_v3i16 body: | bb.1: - liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31 ; GFX7-LABEL: name: add_v3i16 ; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 @@ -95,7 +95,7 @@ body: | ; GFX7-NEXT: $vgpr0 = COPY [[ADD]](s32) ; GFX7-NEXT: $vgpr1 = COPY [[ADD1]](s32) ; GFX7-NEXT: $vgpr2 = COPY [[ADD2]](s32) - ; GFX7-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; GFX7-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 %3:_(s32) = COPY $vgpr0 %4:_(s32) = COPY $vgpr1 %5:_(s32) = COPY $vgpr2 @@ -114,7 +114,7 @@ body: | $vgpr0 = COPY %13(s32) $vgpr1 = COPY %14(s32) $vgpr2 = COPY %15(s32) - SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 ... @@ -122,7 +122,7 @@ body: | name: shl_v3i16 body: | bb.1: - liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31 ; GFX7-LABEL: name: shl_v3i16 ; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 @@ -143,7 +143,7 @@ body: | ; GFX7-NEXT: $vgpr0 = COPY [[SHL]](s32) ; GFX7-NEXT: $vgpr1 = COPY [[SHL1]](s32) ; GFX7-NEXT: $vgpr2 = COPY [[SHL2]](s32) - ; GFX7-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; GFX7-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 %3:_(s32) = COPY $vgpr0 %4:_(s32) = COPY $vgpr1 %5:_(s32) = COPY $vgpr2 @@ -162,7 +162,7 @@ body: | $vgpr0 = COPY %13(s32) $vgpr1 = COPY %14(s32) $vgpr2 = COPY %15(s32) - SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 ... @@ -170,7 +170,7 @@ body: | name: fma_v4f16 body: | bb.1: - liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $sgpr30_sgpr31 ; GFX7-LABEL: name: fma_v4f16 ; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 @@ -227,7 +227,7 @@ body: | ; GFX7-NEXT: $vgpr1 = COPY [[ANYEXT1]](s32) ; GFX7-NEXT: $vgpr2 = COPY [[ANYEXT2]](s32) ; GFX7-NEXT: $vgpr3 = COPY [[ANYEXT3]](s32) - ; GFX7-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; GFX7-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 %4:_(s32) = COPY $vgpr0 %5:_(s32) = COPY $vgpr1 %6:_(s32) = COPY $vgpr2 @@ -256,7 +256,7 @@ body: | $vgpr1 = COPY %22(s32) $vgpr2 = COPY %23(s32) $vgpr3 = COPY %24(s32) - SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ... --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir index 61af5e01ed4c6..7bb3edec1240f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir @@ -37,40 +37,40 @@ name: and_v2i16 body: | bb.1: - liveins: $vgpr0, $vgpr1 + liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 ; GFX8-LABEL: name: and_v2i16 - ; GFX8: liveins: $vgpr0, $vgpr1 + ; GFX8: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 ; GFX8-NEXT: {{ $}} ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; GFX8-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[COPY1]] ; GFX8-NEXT: $vgpr0 = COPY [[AND]](<2 x s16>) - ; GFX8-NEXT: SI_RETURN implicit $vgpr0 + ; GFX8-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0 ; ; GFX9-LABEL: name: and_v2i16 - ; GFX9: liveins: $vgpr0, $vgpr1 + ; GFX9: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; GFX9-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[COPY1]] ; GFX9-NEXT: $vgpr0 = COPY [[AND]](<2 x s16>) - ; GFX9-NEXT: SI_RETURN implicit $vgpr0 + ; GFX9-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 %3:_(<2 x s16>) = G_AND %0, %1 $vgpr0 = COPY %3(<2 x s16>) - SI_RETURN implicit $vgpr0 + S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0 ... --- name: add_v3i16 body: | bb.1: - liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 ; GFX8-LABEL: name: add_v3i16 - ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 ; GFX8-NEXT: {{ $}} ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 @@ -104,10 +104,10 @@ body: | ; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST4]](<2 x s16>) ; GFX8-NEXT: $vgpr1 = COPY [[BITCAST5]](<2 x s16>) - ; GFX8-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 + ; GFX8-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 ; ; GFX9-LABEL: name: add_v3i16 - ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 @@ -117,7 +117,7 @@ body: | ; GFX9-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[COPY1]], [[COPY3]] ; GFX9-NEXT: $vgpr0 = COPY [[ADD]](<2 x s16>) ; GFX9-NEXT: $vgpr1 = COPY [[ADD1]](<2 x s16>) - ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 + ; GFX9-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 %3:_(<2 x s16>) = COPY $vgpr0 %4:_(<2 x s16>) = COPY $vgpr1 %5:_(<4 x s16>) = G_CONCAT_VECTORS %3(<2 x s16>), %4(<2 x s16>) @@ -135,17 +135,17 @@ body: | %19:_(<2 x s16>), %20:_(<2 x s16>) = G_UNMERGE_VALUES %25(<4 x s16>) $vgpr0 = COPY %19(<2 x s16>) $vgpr1 = COPY %20(<2 x s16>) - SI_RETURN implicit $vgpr0, implicit $vgpr1 + S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 ... --- name: shl_v3i16 body: | bb.1: - liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 ; GFX8-LABEL: name: shl_v3i16 - ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 ; GFX8-NEXT: {{ $}} ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 @@ -179,10 +179,10 @@ body: | ; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST4]](<2 x s16>) ; GFX8-NEXT: $vgpr1 = COPY [[BITCAST5]](<2 x s16>) - ; GFX8-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 + ; GFX8-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 ; ; GFX9-LABEL: name: shl_v3i16 - ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 @@ -198,7 +198,7 @@ body: | ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[SHL1]](s16), [[DEF]](s16) ; GFX9-NEXT: $vgpr0 = COPY [[SHL]](<2 x s16>) ; GFX9-NEXT: $vgpr1 = COPY [[BUILD_VECTOR]](<2 x s16>) - ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 + ; GFX9-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 %3:_(<2 x s16>) = COPY $vgpr0 %4:_(<2 x s16>) = COPY $vgpr1 %5:_(<4 x s16>) = G_CONCAT_VECTORS %3(<2 x s16>), %4(<2 x s16>) @@ -216,17 +216,17 @@ body: | %19:_(<2 x s16>), %20:_(<2 x s16>) = G_UNMERGE_VALUES %25(<4 x s16>) $vgpr0 = COPY %19(<2 x s16>) $vgpr1 = COPY %20(<2 x s16>) - SI_RETURN implicit $vgpr0, implicit $vgpr1 + S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 ... --- name: fma_v4f16 body: | bb.1: - liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31 ; GFX8-LABEL: name: fma_v4f16 - ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31 ; GFX8-NEXT: {{ $}} ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 @@ -275,10 +275,10 @@ body: | ; GFX8-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST6]](<2 x s16>) ; GFX8-NEXT: $vgpr1 = COPY [[BITCAST7]](<2 x s16>) - ; GFX8-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 + ; GFX8-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 ; ; GFX9-LABEL: name: fma_v4f16 - ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 @@ -290,7 +290,7 @@ body: | ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(<2 x s16>) = G_FMA [[COPY1]], [[COPY3]], [[COPY5]] ; GFX9-NEXT: $vgpr0 = COPY [[FMA]](<2 x s16>) ; GFX9-NEXT: $vgpr1 = COPY [[FMA1]](<2 x s16>) - ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 + ; GFX9-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 %4:_(<2 x s16>) = COPY $vgpr0 %5:_(<2 x s16>) = COPY $vgpr1 %0:_(<4 x s16>) = G_CONCAT_VECTORS %4(<2 x s16>), %5(<2 x s16>) @@ -304,7 +304,7 @@ body: | %12:_(<2 x s16>), %13:_(<2 x s16>) = G_UNMERGE_VALUES %10(<4 x s16>) $vgpr0 = COPY %12(<2 x s16>) $vgpr1 = COPY %13(<2 x s16>) - SI_RETURN implicit $vgpr0, implicit $vgpr1 + S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1 ... --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll index c295a662704e9..e058a3e5c332e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll @@ -235,17 +235,17 @@ define void @sink_null_insert_pt(ptr addrspace(4) %arg0) { ; GFX9-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: global_load_dword v0, v[0:1], off glc -; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_writelane_b32 v40, s16, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: global_load_dword v0, v[0:1], off glc +; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_swappc_b64 s[30:31], 0 -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll index e86f7473363f7..c037a93af124b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll @@ -13,18 +13,24 @@ define amdgpu_kernel void @system_one_as_acquire() #0 { ; GFX6-LABEL: name: system_one_as_acquire ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 3952 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: system_one_as_acquire ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 3952 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: system_one_as_acquire ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -33,6 +39,8 @@ define amdgpu_kernel void @system_one_as_acquire() #0 { ; ; GFX10CU-LABEL: name: system_one_as_acquire ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -41,6 +49,8 @@ define amdgpu_kernel void @system_one_as_acquire() #0 { ; ; GFX11WGP-LABEL: name: system_one_as_acquire ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -49,6 +59,8 @@ define amdgpu_kernel void @system_one_as_acquire() #0 { ; ; GFX11CU-LABEL: name: system_one_as_acquire ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -62,34 +74,46 @@ entry: define amdgpu_kernel void @system_one_as_release() #0 { ; GFX6-LABEL: name: system_one_as_release ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 3952 ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: system_one_as_release ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 3952 ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: system_one_as_release ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: system_one_as_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: system_one_as_release ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: system_one_as_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 @@ -101,18 +125,24 @@ entry: define amdgpu_kernel void @system_one_as_acq_rel() #0 { ; GFX6-LABEL: name: system_one_as_acq_rel ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 3952 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: system_one_as_acq_rel ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 3952 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: system_one_as_acq_rel ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -121,6 +151,8 @@ define amdgpu_kernel void @system_one_as_acq_rel() #0 { ; ; GFX10CU-LABEL: name: system_one_as_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -129,6 +161,8 @@ define amdgpu_kernel void @system_one_as_acq_rel() #0 { ; ; GFX11WGP-LABEL: name: system_one_as_acq_rel ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -137,6 +171,8 @@ define amdgpu_kernel void @system_one_as_acq_rel() #0 { ; ; GFX11CU-LABEL: name: system_one_as_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -150,18 +186,24 @@ entry: define amdgpu_kernel void @system_one_as_seq_cst() #0 { ; GFX6-LABEL: name: system_one_as_seq_cst ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 3952 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: system_one_as_seq_cst ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 3952 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: system_one_as_seq_cst ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -170,6 +212,8 @@ define amdgpu_kernel void @system_one_as_seq_cst() #0 { ; ; GFX10CU-LABEL: name: system_one_as_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -178,6 +222,8 @@ define amdgpu_kernel void @system_one_as_seq_cst() #0 { ; ; GFX11WGP-LABEL: name: system_one_as_seq_cst ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -186,6 +232,8 @@ define amdgpu_kernel void @system_one_as_seq_cst() #0 { ; ; GFX11CU-LABEL: name: system_one_as_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -199,26 +247,38 @@ entry: define amdgpu_kernel void @singlethread_one_as_acquire() #0 { ; GFX6-LABEL: name: singlethread_one_as_acquire ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: singlethread_one_as_acquire ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: singlethread_one_as_acquire ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: singlethread_one_as_acquire ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: singlethread_one_as_acquire ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: singlethread_one_as_acquire ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("singlethread-one-as") acquire @@ -228,26 +288,38 @@ entry: define amdgpu_kernel void @singlethread_one_as_release() #0 { ; GFX6-LABEL: name: singlethread_one_as_release ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: singlethread_one_as_release ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: singlethread_one_as_release ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: singlethread_one_as_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: singlethread_one_as_release ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: singlethread_one_as_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("singlethread-one-as") release @@ -257,26 +329,38 @@ entry: define amdgpu_kernel void @singlethread_one_as_acq_rel() #0 { ; GFX6-LABEL: name: singlethread_one_as_acq_rel ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: singlethread_one_as_acq_rel ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: singlethread_one_as_acq_rel ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: singlethread_one_as_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: singlethread_one_as_acq_rel ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: singlethread_one_as_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("singlethread-one-as") acq_rel @@ -286,26 +370,38 @@ entry: define amdgpu_kernel void @singlethread_one_as_seq_cst() #0 { ; GFX6-LABEL: name: singlethread_one_as_seq_cst ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: singlethread_one_as_seq_cst ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: singlethread_one_as_seq_cst ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: singlethread_one_as_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: singlethread_one_as_seq_cst ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: singlethread_one_as_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("singlethread-one-as") seq_cst @@ -315,18 +411,24 @@ entry: define amdgpu_kernel void @agent_one_as_acquire() #0 { ; GFX6-LABEL: name: agent_one_as_acquire ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 3952 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: agent_one_as_acquire ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 3952 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: agent_one_as_acquire ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -335,6 +437,8 @@ define amdgpu_kernel void @agent_one_as_acquire() #0 { ; ; GFX10CU-LABEL: name: agent_one_as_acquire ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -343,6 +447,8 @@ define amdgpu_kernel void @agent_one_as_acquire() #0 { ; ; GFX11WGP-LABEL: name: agent_one_as_acquire ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -351,6 +457,8 @@ define amdgpu_kernel void @agent_one_as_acquire() #0 { ; ; GFX11CU-LABEL: name: agent_one_as_acquire ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -364,34 +472,46 @@ entry: define amdgpu_kernel void @agent_one_as_release() #0 { ; GFX6-LABEL: name: agent_one_as_release ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 3952 ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: agent_one_as_release ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 3952 ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: agent_one_as_release ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: agent_one_as_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: agent_one_as_release ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: agent_one_as_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 @@ -403,18 +523,24 @@ entry: define amdgpu_kernel void @agent_one_as_acq_rel() #0 { ; GFX6-LABEL: name: agent_one_as_acq_rel ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 3952 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: agent_one_as_acq_rel ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 3952 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: agent_one_as_acq_rel ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -423,6 +549,8 @@ define amdgpu_kernel void @agent_one_as_acq_rel() #0 { ; ; GFX10CU-LABEL: name: agent_one_as_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -431,6 +559,8 @@ define amdgpu_kernel void @agent_one_as_acq_rel() #0 { ; ; GFX11WGP-LABEL: name: agent_one_as_acq_rel ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -439,6 +569,8 @@ define amdgpu_kernel void @agent_one_as_acq_rel() #0 { ; ; GFX11CU-LABEL: name: agent_one_as_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -452,18 +584,24 @@ entry: define amdgpu_kernel void @agent_one_as_seq_cst() #0 { ; GFX6-LABEL: name: agent_one_as_seq_cst ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 3952 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: agent_one_as_seq_cst ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 3952 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: agent_one_as_seq_cst ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -472,6 +610,8 @@ define amdgpu_kernel void @agent_one_as_seq_cst() #0 { ; ; GFX10CU-LABEL: name: agent_one_as_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -480,6 +620,8 @@ define amdgpu_kernel void @agent_one_as_seq_cst() #0 { ; ; GFX11WGP-LABEL: name: agent_one_as_seq_cst ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -488,6 +630,8 @@ define amdgpu_kernel void @agent_one_as_seq_cst() #0 { ; ; GFX11CU-LABEL: name: agent_one_as_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -501,14 +645,20 @@ entry: define amdgpu_kernel void @workgroup_one_as_acquire() #0 { ; GFX6-LABEL: name: workgroup_one_as_acquire ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: workgroup_one_as_acquire ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: workgroup_one_as_acquire ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec @@ -516,10 +666,14 @@ define amdgpu_kernel void @workgroup_one_as_acquire() #0 { ; ; GFX10CU-LABEL: name: workgroup_one_as_acquire ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: workgroup_one_as_acquire ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec @@ -527,6 +681,8 @@ define amdgpu_kernel void @workgroup_one_as_acquire() #0 { ; ; GFX11CU-LABEL: name: workgroup_one_as_acquire ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("workgroup-one-as") acquire @@ -536,14 +692,20 @@ entry: define amdgpu_kernel void @workgroup_one_as_release() #0 { ; GFX6-LABEL: name: workgroup_one_as_release ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: workgroup_one_as_release ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: workgroup_one_as_release ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_lds_direct ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -551,6 +713,8 @@ define amdgpu_kernel void @workgroup_one_as_release() #0 { ; ; GFX10CU-LABEL: name: workgroup_one_as_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_lds_direct ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -558,12 +722,16 @@ define amdgpu_kernel void @workgroup_one_as_release() #0 { ; ; GFX11WGP-LABEL: name: workgroup_one_as_release ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: workgroup_one_as_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 @@ -575,14 +743,20 @@ entry: define amdgpu_kernel void @workgroup_one_as_acq_rel() #0 { ; GFX6-LABEL: name: workgroup_one_as_acq_rel ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: workgroup_one_as_acq_rel ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: workgroup_one_as_acq_rel ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_lds_direct ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -591,6 +765,8 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel() #0 { ; ; GFX10CU-LABEL: name: workgroup_one_as_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_lds_direct ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -598,6 +774,8 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel() #0 { ; ; GFX11WGP-LABEL: name: workgroup_one_as_acq_rel ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec @@ -605,6 +783,8 @@ define amdgpu_kernel void @workgroup_one_as_acq_rel() #0 { ; ; GFX11CU-LABEL: name: workgroup_one_as_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 @@ -616,14 +796,20 @@ entry: define amdgpu_kernel void @workgroup_one_as_seq_cst() #0 { ; GFX6-LABEL: name: workgroup_one_as_seq_cst ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: workgroup_one_as_seq_cst ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: workgroup_one_as_seq_cst ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 16240 ; GFX10WGP-NEXT: S_WAITCNT_lds_direct ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -632,6 +818,8 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst() #0 { ; ; GFX10CU-LABEL: name: workgroup_one_as_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 16240 ; GFX10CU-NEXT: S_WAITCNT_lds_direct ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -639,6 +827,8 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst() #0 { ; ; GFX11WGP-LABEL: name: workgroup_one_as_seq_cst ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 1015 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec @@ -646,6 +836,8 @@ define amdgpu_kernel void @workgroup_one_as_seq_cst() #0 { ; ; GFX11CU-LABEL: name: workgroup_one_as_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 1015 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 @@ -657,26 +849,38 @@ entry: define amdgpu_kernel void @wavefront_one_as_acquire() #0 { ; GFX6-LABEL: name: wavefront_one_as_acquire ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: wavefront_one_as_acquire ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: wavefront_one_as_acquire ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: wavefront_one_as_acquire ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: wavefront_one_as_acquire ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: wavefront_one_as_acquire ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("wavefront-one-as") acquire @@ -686,26 +890,38 @@ entry: define amdgpu_kernel void @wavefront_one_as_release() #0 { ; GFX6-LABEL: name: wavefront_one_as_release ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: wavefront_one_as_release ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: wavefront_one_as_release ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: wavefront_one_as_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: wavefront_one_as_release ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: wavefront_one_as_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("wavefront-one-as") release @@ -715,26 +931,38 @@ entry: define amdgpu_kernel void @wavefront_one_as_acq_rel() #0 { ; GFX6-LABEL: name: wavefront_one_as_acq_rel ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: wavefront_one_as_acq_rel ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: wavefront_one_as_acq_rel ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: wavefront_one_as_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: wavefront_one_as_acq_rel ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: wavefront_one_as_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("wavefront-one-as") acq_rel @@ -744,26 +972,38 @@ entry: define amdgpu_kernel void @wavefront_one_as_seq_cst() #0 { ; GFX6-LABEL: name: wavefront_one_as_seq_cst ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: wavefront_one_as_seq_cst ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: wavefront_one_as_seq_cst ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: wavefront_one_as_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: wavefront_one_as_seq_cst ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: wavefront_one_as_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("wavefront-one-as") seq_cst @@ -773,18 +1013,24 @@ entry: define amdgpu_kernel void @system_acquire() #0 { ; GFX6-LABEL: name: system_acquire ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 112 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: system_acquire ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 112 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: system_acquire ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -793,6 +1039,8 @@ define amdgpu_kernel void @system_acquire() #0 { ; ; GFX10CU-LABEL: name: system_acquire ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -801,6 +1049,8 @@ define amdgpu_kernel void @system_acquire() #0 { ; ; GFX11WGP-LABEL: name: system_acquire ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -809,6 +1059,8 @@ define amdgpu_kernel void @system_acquire() #0 { ; ; GFX11CU-LABEL: name: system_acquire ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -822,34 +1074,46 @@ entry: define amdgpu_kernel void @system_release() #0 { ; GFX6-LABEL: name: system_release ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 112 ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: system_release ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 112 ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: system_release ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: system_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: system_release ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: system_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 @@ -861,18 +1125,24 @@ entry: define amdgpu_kernel void @system_acq_rel() #0 { ; GFX6-LABEL: name: system_acq_rel ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 112 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: system_acq_rel ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 112 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: system_acq_rel ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -881,6 +1151,8 @@ define amdgpu_kernel void @system_acq_rel() #0 { ; ; GFX10CU-LABEL: name: system_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -889,6 +1161,8 @@ define amdgpu_kernel void @system_acq_rel() #0 { ; ; GFX11WGP-LABEL: name: system_acq_rel ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -897,6 +1171,8 @@ define amdgpu_kernel void @system_acq_rel() #0 { ; ; GFX11CU-LABEL: name: system_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -910,18 +1186,24 @@ entry: define amdgpu_kernel void @system_seq_cst() #0 { ; GFX6-LABEL: name: system_seq_cst ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 112 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: system_seq_cst ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 112 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: system_seq_cst ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -930,6 +1212,8 @@ define amdgpu_kernel void @system_seq_cst() #0 { ; ; GFX10CU-LABEL: name: system_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -938,6 +1222,8 @@ define amdgpu_kernel void @system_seq_cst() #0 { ; ; GFX11WGP-LABEL: name: system_seq_cst ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -946,6 +1232,8 @@ define amdgpu_kernel void @system_seq_cst() #0 { ; ; GFX11CU-LABEL: name: system_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -959,26 +1247,38 @@ entry: define amdgpu_kernel void @singlethread_acquire() #0 { ; GFX6-LABEL: name: singlethread_acquire ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: singlethread_acquire ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: singlethread_acquire ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: singlethread_acquire ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: singlethread_acquire ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: singlethread_acquire ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("singlethread") acquire @@ -988,26 +1288,38 @@ entry: define amdgpu_kernel void @singlethread_release() #0 { ; GFX6-LABEL: name: singlethread_release ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: singlethread_release ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: singlethread_release ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: singlethread_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: singlethread_release ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: singlethread_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("singlethread") release @@ -1017,26 +1329,38 @@ entry: define amdgpu_kernel void @singlethread_acq_rel() #0 { ; GFX6-LABEL: name: singlethread_acq_rel ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: singlethread_acq_rel ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: singlethread_acq_rel ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: singlethread_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: singlethread_acq_rel ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: singlethread_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("singlethread") acq_rel @@ -1046,26 +1370,38 @@ entry: define amdgpu_kernel void @singlethread_seq_cst() #0 { ; GFX6-LABEL: name: singlethread_seq_cst ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: singlethread_seq_cst ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: singlethread_seq_cst ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: singlethread_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: singlethread_seq_cst ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: singlethread_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("singlethread") seq_cst @@ -1075,18 +1411,24 @@ entry: define amdgpu_kernel void @agent_acquire() #0 { ; GFX6-LABEL: name: agent_acquire ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 112 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: agent_acquire ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 112 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: agent_acquire ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -1095,6 +1437,8 @@ define amdgpu_kernel void @agent_acquire() #0 { ; ; GFX10CU-LABEL: name: agent_acquire ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -1103,6 +1447,8 @@ define amdgpu_kernel void @agent_acquire() #0 { ; ; GFX11WGP-LABEL: name: agent_acquire ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -1111,6 +1457,8 @@ define amdgpu_kernel void @agent_acquire() #0 { ; ; GFX11CU-LABEL: name: agent_acquire ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -1124,34 +1472,46 @@ entry: define amdgpu_kernel void @agent_release() #0 { ; GFX6-LABEL: name: agent_release ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 112 ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: agent_release ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 112 ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: agent_release ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: agent_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: agent_release ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: agent_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 @@ -1163,18 +1523,24 @@ entry: define amdgpu_kernel void @agent_acq_rel() #0 { ; GFX6-LABEL: name: agent_acq_rel ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 112 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: agent_acq_rel ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 112 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: agent_acq_rel ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -1183,6 +1549,8 @@ define amdgpu_kernel void @agent_acq_rel() #0 { ; ; GFX10CU-LABEL: name: agent_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -1191,6 +1559,8 @@ define amdgpu_kernel void @agent_acq_rel() #0 { ; ; GFX11WGP-LABEL: name: agent_acq_rel ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -1199,6 +1569,8 @@ define amdgpu_kernel void @agent_acq_rel() #0 { ; ; GFX11CU-LABEL: name: agent_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -1212,18 +1584,24 @@ entry: define amdgpu_kernel void @agent_seq_cst() #0 { ; GFX6-LABEL: name: agent_seq_cst ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 112 ; GFX6-NEXT: BUFFER_WBINVL1 implicit $exec ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: agent_seq_cst ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 112 ; GFX8-NEXT: BUFFER_WBINVL1_VOL implicit $exec ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: agent_seq_cst ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -1232,6 +1610,8 @@ define amdgpu_kernel void @agent_seq_cst() #0 { ; ; GFX10CU-LABEL: name: agent_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -1240,6 +1620,8 @@ define amdgpu_kernel void @agent_seq_cst() #0 { ; ; GFX11WGP-LABEL: name: agent_seq_cst ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL1_INV implicit $exec @@ -1248,6 +1630,8 @@ define amdgpu_kernel void @agent_seq_cst() #0 { ; ; GFX11CU-LABEL: name: agent_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: BUFFER_GL1_INV implicit $exec @@ -1261,16 +1645,22 @@ entry: define amdgpu_kernel void @workgroup_acquire() #0 { ; GFX6-LABEL: name: workgroup_acquire ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 127 ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: workgroup_acquire ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 127 ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: workgroup_acquire ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX10WGP-NEXT: BUFFER_GL0_INV implicit $exec @@ -1278,11 +1668,15 @@ define amdgpu_kernel void @workgroup_acquire() #0 { ; ; GFX10CU-LABEL: name: workgroup_acquire ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 49279 ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: workgroup_acquire ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec @@ -1290,6 +1684,8 @@ define amdgpu_kernel void @workgroup_acquire() #0 { ; ; GFX11CU-LABEL: name: workgroup_acquire ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 64519 ; GFX11CU-NEXT: S_ENDPGM 0 entry: @@ -1300,16 +1696,22 @@ entry: define amdgpu_kernel void @workgroup_release() #0 { ; GFX6-LABEL: name: workgroup_release ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 127 ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: workgroup_release ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 127 ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: workgroup_release ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_lds_direct ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -1317,6 +1719,8 @@ define amdgpu_kernel void @workgroup_release() #0 { ; ; GFX10CU-LABEL: name: workgroup_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_lds_direct ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -1324,12 +1728,16 @@ define amdgpu_kernel void @workgroup_release() #0 { ; ; GFX11WGP-LABEL: name: workgroup_release ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: workgroup_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 @@ -1341,16 +1749,22 @@ entry: define amdgpu_kernel void @workgroup_acq_rel() #0 { ; GFX6-LABEL: name: workgroup_acq_rel ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 127 ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: workgroup_acq_rel ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 127 ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: workgroup_acq_rel ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_lds_direct ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -1359,6 +1773,8 @@ define amdgpu_kernel void @workgroup_acq_rel() #0 { ; ; GFX10CU-LABEL: name: workgroup_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_lds_direct ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -1366,6 +1782,8 @@ define amdgpu_kernel void @workgroup_acq_rel() #0 { ; ; GFX11WGP-LABEL: name: workgroup_acq_rel ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec @@ -1373,6 +1791,8 @@ define amdgpu_kernel void @workgroup_acq_rel() #0 { ; ; GFX11CU-LABEL: name: workgroup_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 @@ -1384,16 +1804,22 @@ entry: define amdgpu_kernel void @workgroup_seq_cst() #0 { ; GFX6-LABEL: name: workgroup_seq_cst ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_WAITCNT_soft 127 ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: workgroup_seq_cst ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_WAITCNT_soft 127 ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: workgroup_seq_cst ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_WAITCNT_soft 112 ; GFX10WGP-NEXT: S_WAITCNT_lds_direct ; GFX10WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -1402,6 +1828,8 @@ define amdgpu_kernel void @workgroup_seq_cst() #0 { ; ; GFX10CU-LABEL: name: workgroup_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_WAITCNT_soft 112 ; GFX10CU-NEXT: S_WAITCNT_lds_direct ; GFX10CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 @@ -1409,6 +1837,8 @@ define amdgpu_kernel void @workgroup_seq_cst() #0 { ; ; GFX11WGP-LABEL: name: workgroup_seq_cst ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_WAITCNT_soft 7 ; GFX11WGP-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11WGP-NEXT: BUFFER_GL0_INV implicit $exec @@ -1416,6 +1846,8 @@ define amdgpu_kernel void @workgroup_seq_cst() #0 { ; ; GFX11CU-LABEL: name: workgroup_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_WAITCNT_soft 7 ; GFX11CU-NEXT: S_WAITCNT_VSCNT_soft undef $sgpr_null, 0 ; GFX11CU-NEXT: S_ENDPGM 0 @@ -1427,26 +1859,38 @@ entry: define amdgpu_kernel void @wavefront_acquire() #0 { ; GFX6-LABEL: name: wavefront_acquire ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: wavefront_acquire ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: wavefront_acquire ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: wavefront_acquire ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: wavefront_acquire ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: wavefront_acquire ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("wavefront") acquire @@ -1456,26 +1900,38 @@ entry: define amdgpu_kernel void @wavefront_release() #0 { ; GFX6-LABEL: name: wavefront_release ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: wavefront_release ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: wavefront_release ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: wavefront_release ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: wavefront_release ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: wavefront_release ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("wavefront") release @@ -1485,26 +1941,38 @@ entry: define amdgpu_kernel void @wavefront_acq_rel() #0 { ; GFX6-LABEL: name: wavefront_acq_rel ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: wavefront_acq_rel ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: wavefront_acq_rel ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: wavefront_acq_rel ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: wavefront_acq_rel ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: wavefront_acq_rel ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("wavefront") acq_rel @@ -1514,26 +1982,38 @@ entry: define amdgpu_kernel void @wavefront_seq_cst() #0 { ; GFX6-LABEL: name: wavefront_seq_cst ; GFX6: bb.0.entry: + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX6-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX8-LABEL: name: wavefront_seq_cst ; GFX8: bb.0.entry: + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: S_ENDPGM 0 ; ; GFX10WGP-LABEL: name: wavefront_seq_cst ; GFX10WGP: bb.0.entry: + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10WGP-NEXT: S_ENDPGM 0 ; ; GFX10CU-LABEL: name: wavefront_seq_cst ; GFX10CU: bb.0.entry: + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10CU-NEXT: S_ENDPGM 0 ; ; GFX11WGP-LABEL: name: wavefront_seq_cst ; GFX11WGP: bb.0.entry: + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11WGP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11WGP-NEXT: S_ENDPGM 0 ; ; GFX11CU-LABEL: name: wavefront_seq_cst ; GFX11CU: bb.0.entry: + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11CU-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11CU-NEXT: S_ENDPGM 0 entry: fence syncscope("wavefront") seq_cst diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll index 1cd9c0bfeb7e6..c1237476238ea 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll @@ -589,4 +589,3 @@ endif: ret void } - diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll index 21f459ac033ca..9839af011ecdb 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll @@ -151,8 +151,8 @@ define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i3 ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_mov_b32 s7, s33 -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GCN-NEXT: s_mov_b32 s33, s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_cbranch_execz .LBB2_3 @@ -217,9 +217,9 @@ define void @func_non_entry_block_static_alloca_align64(ptr addrspace(1) %out, i ; GCN-NEXT: s_mov_b32 s7, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0xfc0 ; GCN-NEXT: s_mov_b32 s8, s34 -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GCN-NEXT: s_and_b32 s33, s33, 0xfffff000 ; GCN-NEXT: s_mov_b32 s34, s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GCN-NEXT: s_addk_i32 s32, 0x2000 ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_cbranch_execz .LBB3_2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll index c82f7c53696d3..4d584cd73ded4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll @@ -6,6 +6,36 @@ ; Natural mapping define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) { + ; CHECK-LABEL: name: s_buffer_load_i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(s32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[AMDGPU_S_BUFFER_LOAD]](s32) + ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INT]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; GREEDY-LABEL: name: s_buffer_load_i32 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(s32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[AMDGPU_S_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32) + ; GREEDY-NEXT: $sgpr0 = COPY [[INT]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 ; GFX7-LABEL: name: s_buffer_load_i32 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 @@ -42,6 +72,44 @@ define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffse } define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v2i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load (s64), align 4) + ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x s32>) + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32) + ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INT]](s32) + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32) + ; CHECK-NEXT: [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INT1]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 + ; GREEDY-LABEL: name: s_buffer_load_v2i32 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load (s64), align 4) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x s32>) + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32) + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32) + ; GREEDY-NEXT: $sgpr0 = COPY [[INT]](s32) + ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32) + ; GREEDY-NEXT: [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32) + ; GREEDY-NEXT: $sgpr1 = COPY [[INT1]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1 ; GFX7-LABEL: name: s_buffer_load_v2i32 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 @@ -86,6 +154,50 @@ define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg } define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v3i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load (s96), align 4) + ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>) + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32) + ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INT]](s32) + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32) + ; CHECK-NEXT: [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INT1]](s32) + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[UV2]](s32) + ; CHECK-NEXT: [[INT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](s32) + ; CHECK-NEXT: $sgpr2 = COPY [[INT2]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 + ; GREEDY-LABEL: name: s_buffer_load_v3i32 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load (s96), align 4) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>) + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32) + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32) + ; GREEDY-NEXT: $sgpr0 = COPY [[INT]](s32) + ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32) + ; GREEDY-NEXT: [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32) + ; GREEDY-NEXT: $sgpr1 = COPY [[INT1]](s32) + ; GREEDY-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[UV2]](s32) + ; GREEDY-NEXT: [[INT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](s32) + ; GREEDY-NEXT: $sgpr2 = COPY [[INT2]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2 ; GFX7-LABEL: name: s_buffer_load_v3i32 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 @@ -136,6 +248,80 @@ define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg } define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v8i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load (s256), align 4) + ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x s32>) + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32) + ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INT]](s32) + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32) + ; CHECK-NEXT: [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INT1]](s32) + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[UV2]](s32) + ; CHECK-NEXT: [[INT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](s32) + ; CHECK-NEXT: $sgpr2 = COPY [[INT2]](s32) + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[UV3]](s32) + ; CHECK-NEXT: [[INT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](s32) + ; CHECK-NEXT: $sgpr3 = COPY [[INT3]](s32) + ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[UV4]](s32) + ; CHECK-NEXT: [[INT4:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](s32) + ; CHECK-NEXT: $sgpr4 = COPY [[INT4]](s32) + ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr(s32) = COPY [[UV5]](s32) + ; CHECK-NEXT: [[INT5:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](s32) + ; CHECK-NEXT: $sgpr5 = COPY [[INT5]](s32) + ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr(s32) = COPY [[UV6]](s32) + ; CHECK-NEXT: [[INT6:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](s32) + ; CHECK-NEXT: $sgpr6 = COPY [[INT6]](s32) + ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr(s32) = COPY [[UV7]](s32) + ; CHECK-NEXT: [[INT7:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](s32) + ; CHECK-NEXT: $sgpr7 = COPY [[INT7]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8i32 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load (s256), align 4) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x s32>) + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32) + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32) + ; GREEDY-NEXT: $sgpr0 = COPY [[INT]](s32) + ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32) + ; GREEDY-NEXT: [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32) + ; GREEDY-NEXT: $sgpr1 = COPY [[INT1]](s32) + ; GREEDY-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[UV2]](s32) + ; GREEDY-NEXT: [[INT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](s32) + ; GREEDY-NEXT: $sgpr2 = COPY [[INT2]](s32) + ; GREEDY-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[UV3]](s32) + ; GREEDY-NEXT: [[INT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](s32) + ; GREEDY-NEXT: $sgpr3 = COPY [[INT3]](s32) + ; GREEDY-NEXT: [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[UV4]](s32) + ; GREEDY-NEXT: [[INT4:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](s32) + ; GREEDY-NEXT: $sgpr4 = COPY [[INT4]](s32) + ; GREEDY-NEXT: [[COPY10:%[0-9]+]]:vgpr(s32) = COPY [[UV5]](s32) + ; GREEDY-NEXT: [[INT5:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](s32) + ; GREEDY-NEXT: $sgpr5 = COPY [[INT5]](s32) + ; GREEDY-NEXT: [[COPY11:%[0-9]+]]:vgpr(s32) = COPY [[UV6]](s32) + ; GREEDY-NEXT: [[INT6:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](s32) + ; GREEDY-NEXT: $sgpr6 = COPY [[INT6]](s32) + ; GREEDY-NEXT: [[COPY12:%[0-9]+]]:vgpr(s32) = COPY [[UV7]](s32) + ; GREEDY-NEXT: [[INT7:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](s32) + ; GREEDY-NEXT: $sgpr7 = COPY [[INT7]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7 ; GFX7-LABEL: name: s_buffer_load_v8i32 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 @@ -216,6 +402,128 @@ define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg } define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v16i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load (s512), align 4) + ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32), [[UV8:%[0-9]+]]:sgpr(s32), [[UV9:%[0-9]+]]:sgpr(s32), [[UV10:%[0-9]+]]:sgpr(s32), [[UV11:%[0-9]+]]:sgpr(s32), [[UV12:%[0-9]+]]:sgpr(s32), [[UV13:%[0-9]+]]:sgpr(s32), [[UV14:%[0-9]+]]:sgpr(s32), [[UV15:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x s32>) + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32) + ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INT]](s32) + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32) + ; CHECK-NEXT: [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INT1]](s32) + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[UV2]](s32) + ; CHECK-NEXT: [[INT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](s32) + ; CHECK-NEXT: $sgpr2 = COPY [[INT2]](s32) + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[UV3]](s32) + ; CHECK-NEXT: [[INT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](s32) + ; CHECK-NEXT: $sgpr3 = COPY [[INT3]](s32) + ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[UV4]](s32) + ; CHECK-NEXT: [[INT4:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](s32) + ; CHECK-NEXT: $sgpr4 = COPY [[INT4]](s32) + ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr(s32) = COPY [[UV5]](s32) + ; CHECK-NEXT: [[INT5:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](s32) + ; CHECK-NEXT: $sgpr5 = COPY [[INT5]](s32) + ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr(s32) = COPY [[UV6]](s32) + ; CHECK-NEXT: [[INT6:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](s32) + ; CHECK-NEXT: $sgpr6 = COPY [[INT6]](s32) + ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr(s32) = COPY [[UV7]](s32) + ; CHECK-NEXT: [[INT7:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](s32) + ; CHECK-NEXT: $sgpr7 = COPY [[INT7]](s32) + ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr(s32) = COPY [[UV8]](s32) + ; CHECK-NEXT: [[INT8:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY13]](s32) + ; CHECK-NEXT: $sgpr8 = COPY [[INT8]](s32) + ; CHECK-NEXT: [[COPY14:%[0-9]+]]:vgpr(s32) = COPY [[UV9]](s32) + ; CHECK-NEXT: [[INT9:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](s32) + ; CHECK-NEXT: $sgpr9 = COPY [[INT9]](s32) + ; CHECK-NEXT: [[COPY15:%[0-9]+]]:vgpr(s32) = COPY [[UV10]](s32) + ; CHECK-NEXT: [[INT10:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](s32) + ; CHECK-NEXT: $sgpr10 = COPY [[INT10]](s32) + ; CHECK-NEXT: [[COPY16:%[0-9]+]]:vgpr(s32) = COPY [[UV11]](s32) + ; CHECK-NEXT: [[INT11:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY16]](s32) + ; CHECK-NEXT: $sgpr11 = COPY [[INT11]](s32) + ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vgpr(s32) = COPY [[UV12]](s32) + ; CHECK-NEXT: [[INT12:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY17]](s32) + ; CHECK-NEXT: $sgpr12 = COPY [[INT12]](s32) + ; CHECK-NEXT: [[COPY18:%[0-9]+]]:vgpr(s32) = COPY [[UV13]](s32) + ; CHECK-NEXT: [[INT13:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY18]](s32) + ; CHECK-NEXT: $sgpr13 = COPY [[INT13]](s32) + ; CHECK-NEXT: [[COPY19:%[0-9]+]]:vgpr(s32) = COPY [[UV14]](s32) + ; CHECK-NEXT: [[INT14:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY19]](s32) + ; CHECK-NEXT: $sgpr14 = COPY [[INT14]](s32) + ; CHECK-NEXT: [[COPY20:%[0-9]+]]:vgpr(s32) = COPY [[UV15]](s32) + ; CHECK-NEXT: [[INT15:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY20]](s32) + ; CHECK-NEXT: $sgpr15 = COPY [[INT15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 + ; GREEDY-LABEL: name: s_buffer_load_v16i32 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](s32), 0 :: (dereferenceable invariant load (s512), align 4) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32), [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32), [[UV8:%[0-9]+]]:sgpr(s32), [[UV9:%[0-9]+]]:sgpr(s32), [[UV10:%[0-9]+]]:sgpr(s32), [[UV11:%[0-9]+]]:sgpr(s32), [[UV12:%[0-9]+]]:sgpr(s32), [[UV13:%[0-9]+]]:sgpr(s32), [[UV14:%[0-9]+]]:sgpr(s32), [[UV15:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x s32>) + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32) + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](s32) + ; GREEDY-NEXT: $sgpr0 = COPY [[INT]](s32) + ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[UV1]](s32) + ; GREEDY-NEXT: [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY6]](s32) + ; GREEDY-NEXT: $sgpr1 = COPY [[INT1]](s32) + ; GREEDY-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[UV2]](s32) + ; GREEDY-NEXT: [[INT2:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY7]](s32) + ; GREEDY-NEXT: $sgpr2 = COPY [[INT2]](s32) + ; GREEDY-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[UV3]](s32) + ; GREEDY-NEXT: [[INT3:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY8]](s32) + ; GREEDY-NEXT: $sgpr3 = COPY [[INT3]](s32) + ; GREEDY-NEXT: [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[UV4]](s32) + ; GREEDY-NEXT: [[INT4:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](s32) + ; GREEDY-NEXT: $sgpr4 = COPY [[INT4]](s32) + ; GREEDY-NEXT: [[COPY10:%[0-9]+]]:vgpr(s32) = COPY [[UV5]](s32) + ; GREEDY-NEXT: [[INT5:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY10]](s32) + ; GREEDY-NEXT: $sgpr5 = COPY [[INT5]](s32) + ; GREEDY-NEXT: [[COPY11:%[0-9]+]]:vgpr(s32) = COPY [[UV6]](s32) + ; GREEDY-NEXT: [[INT6:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY11]](s32) + ; GREEDY-NEXT: $sgpr6 = COPY [[INT6]](s32) + ; GREEDY-NEXT: [[COPY12:%[0-9]+]]:vgpr(s32) = COPY [[UV7]](s32) + ; GREEDY-NEXT: [[INT7:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY12]](s32) + ; GREEDY-NEXT: $sgpr7 = COPY [[INT7]](s32) + ; GREEDY-NEXT: [[COPY13:%[0-9]+]]:vgpr(s32) = COPY [[UV8]](s32) + ; GREEDY-NEXT: [[INT8:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY13]](s32) + ; GREEDY-NEXT: $sgpr8 = COPY [[INT8]](s32) + ; GREEDY-NEXT: [[COPY14:%[0-9]+]]:vgpr(s32) = COPY [[UV9]](s32) + ; GREEDY-NEXT: [[INT9:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY14]](s32) + ; GREEDY-NEXT: $sgpr9 = COPY [[INT9]](s32) + ; GREEDY-NEXT: [[COPY15:%[0-9]+]]:vgpr(s32) = COPY [[UV10]](s32) + ; GREEDY-NEXT: [[INT10:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY15]](s32) + ; GREEDY-NEXT: $sgpr10 = COPY [[INT10]](s32) + ; GREEDY-NEXT: [[COPY16:%[0-9]+]]:vgpr(s32) = COPY [[UV11]](s32) + ; GREEDY-NEXT: [[INT11:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY16]](s32) + ; GREEDY-NEXT: $sgpr11 = COPY [[INT11]](s32) + ; GREEDY-NEXT: [[COPY17:%[0-9]+]]:vgpr(s32) = COPY [[UV12]](s32) + ; GREEDY-NEXT: [[INT12:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY17]](s32) + ; GREEDY-NEXT: $sgpr12 = COPY [[INT12]](s32) + ; GREEDY-NEXT: [[COPY18:%[0-9]+]]:vgpr(s32) = COPY [[UV13]](s32) + ; GREEDY-NEXT: [[INT13:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY18]](s32) + ; GREEDY-NEXT: $sgpr13 = COPY [[INT13]](s32) + ; GREEDY-NEXT: [[COPY19:%[0-9]+]]:vgpr(s32) = COPY [[UV14]](s32) + ; GREEDY-NEXT: [[INT14:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY19]](s32) + ; GREEDY-NEXT: $sgpr14 = COPY [[INT14]](s32) + ; GREEDY-NEXT: [[COPY20:%[0-9]+]]:vgpr(s32) = COPY [[UV15]](s32) + ; GREEDY-NEXT: [[INT15:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY20]](s32) + ; GREEDY-NEXT: $sgpr15 = COPY [[INT15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15 ; GFX7-LABEL: name: s_buffer_load_v16i32 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 @@ -345,6 +653,36 @@ define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inr ; Check cases that need to be converted to MUBUF due to the offset being a VGPR. define amdgpu_ps float @s_buffer_load_f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -381,6 +719,40 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 } define amdgpu_ps <2 x float> @s_buffer_load_v2f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v2f32_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s64), align 4) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<2 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; GREEDY-LABEL: name: s_buffer_load_v2f32_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s64), align 4) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<2 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; GFX7-LABEL: name: s_buffer_load_v2f32_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -421,6 +793,42 @@ define amdgpu_ps <2 x float> @s_buffer_load_v2f32_vgpr_offset(<4 x i32> inreg %r } define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v3f32_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; GREEDY-LABEL: name: s_buffer_load_v3f32_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 ; GFX7-LABEL: name: s_buffer_load_v3f32_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -463,6 +871,44 @@ define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %r } define amdgpu_ps <4 x float> @s_buffer_load_v4f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v4f32_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; GREEDY-LABEL: name: s_buffer_load_v4f32_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; GFX7-LABEL: name: s_buffer_load_v4f32_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -507,6 +953,56 @@ define amdgpu_ps <4 x float> @s_buffer_load_v4f32_vgpr_offset(<4 x i32> inreg %r } define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -563,6 +1059,76 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %r } define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v16f32_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>), [[AMDGPU_BUFFER_LOAD2]](<4 x s32>), [[AMDGPU_BUFFER_LOAD3]](<4 x s32>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32), [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32) + ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32) + ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32) + ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32) + ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32) + ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32) + ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32) + ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; GREEDY-LABEL: name: s_buffer_load_v16f32_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>), [[AMDGPU_BUFFER_LOAD2]](<4 x s32>), [[AMDGPU_BUFFER_LOAD3]](<4 x s32>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32), [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; GREEDY-NEXT: $vgpr8 = COPY [[UV8]](s32) + ; GREEDY-NEXT: $vgpr9 = COPY [[UV9]](s32) + ; GREEDY-NEXT: $vgpr10 = COPY [[UV10]](s32) + ; GREEDY-NEXT: $vgpr11 = COPY [[UV11]](s32) + ; GREEDY-NEXT: $vgpr12 = COPY [[UV12]](s32) + ; GREEDY-NEXT: $vgpr13 = COPY [[UV13]](s32) + ; GREEDY-NEXT: $vgpr14 = COPY [[UV14]](s32) + ; GREEDY-NEXT: $vgpr15 = COPY [[UV15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -639,6 +1205,40 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg } define amdgpu_ps void @s_buffer_load_i96_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_i96_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s96) = G_TRUNC [[AMDGPU_BUFFER_LOAD]](s128) + ; CHECK-NEXT: G_STORE [[TRUNC]](s96), [[DEF]](p1) :: (store (s96) into `ptr addrspace(1) undef`, align 8, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + ; GREEDY-LABEL: name: s_buffer_load_i96_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s96) = G_TRUNC [[AMDGPU_BUFFER_LOAD]](s128) + ; GREEDY-NEXT: G_STORE [[TRUNC]](s96), [[DEF]](p1) :: (store (s96) into `ptr addrspace(1) undef`, align 8, addrspace 1) + ; GREEDY-NEXT: S_ENDPGM 0 ; GFX7-LABEL: name: s_buffer_load_i96_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -681,6 +1281,50 @@ define amdgpu_ps void @s_buffer_load_i96_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; Test split of a wide scalar define amdgpu_ps void @s_buffer_load_i256_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_i256_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s256) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s128), [[UV1:%[0-9]+]]:vgpr(s128) = G_UNMERGE_VALUES [[MV]](s256) + ; CHECK-NEXT: G_STORE [[UV]](s128), [[DEF]](p1) :: (store (s128) into `ptr addrspace(1) undef`, align 8, addrspace 1) + ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[UV1]](s128), [[PTR_ADD]](p1) :: (store (s128) into `ptr addrspace(1) undef` + 16, align 8, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + ; GREEDY-LABEL: name: s_buffer_load_i256_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[MV:%[0-9]+]]:vgpr(s256) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s128), [[UV1:%[0-9]+]]:vgpr(s128) = G_UNMERGE_VALUES [[MV]](s256) + ; GREEDY-NEXT: G_STORE [[UV]](s128), [[DEF]](p1) :: (store (s128) into `ptr addrspace(1) undef`, align 8, addrspace 1) + ; GREEDY-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; GREEDY-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; GREEDY-NEXT: G_STORE [[UV1]](s128), [[PTR_ADD]](p1) :: (store (s128) into `ptr addrspace(1) undef` + 16, align 8, addrspace 1) + ; GREEDY-NEXT: S_ENDPGM 0 ; GFX7-LABEL: name: s_buffer_load_i256_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -735,6 +1379,66 @@ define amdgpu_ps void @s_buffer_load_i256_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; Test split of a wide scalar define amdgpu_ps void @s_buffer_load_i512_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_i512_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s512) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128), [[AMDGPU_BUFFER_LOAD2]](s128), [[AMDGPU_BUFFER_LOAD3]](s128) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s128), [[UV1:%[0-9]+]]:vgpr(s128), [[UV2:%[0-9]+]]:vgpr(s128), [[UV3:%[0-9]+]]:vgpr(s128) = G_UNMERGE_VALUES [[MV]](s512) + ; CHECK-NEXT: G_STORE [[UV]](s128), [[DEF]](p1) :: (store (s128) into `ptr addrspace(1) undef`, align 8, addrspace 1) + ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[UV1]](s128), [[PTR_ADD]](p1) :: (store (s128) into `ptr addrspace(1) undef` + 16, align 8, addrspace 1) + ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C3]](s64) + ; CHECK-NEXT: G_STORE [[UV2]](s128), [[PTR_ADD1]](p1) :: (store (s128) into `ptr addrspace(1) undef` + 32, align 8, addrspace 1) + ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C4]](s64) + ; CHECK-NEXT: G_STORE [[UV3]](s128), [[PTR_ADD2]](p1) :: (store (s128) into `ptr addrspace(1) undef` + 48, align 8, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + ; GREEDY-LABEL: name: s_buffer_load_i512_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(s128) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; GREEDY-NEXT: [[MV:%[0-9]+]]:vgpr(s512) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFER_LOAD1]](s128), [[AMDGPU_BUFFER_LOAD2]](s128), [[AMDGPU_BUFFER_LOAD3]](s128) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s128), [[UV1:%[0-9]+]]:vgpr(s128), [[UV2:%[0-9]+]]:vgpr(s128), [[UV3:%[0-9]+]]:vgpr(s128) = G_UNMERGE_VALUES [[MV]](s512) + ; GREEDY-NEXT: G_STORE [[UV]](s128), [[DEF]](p1) :: (store (s128) into `ptr addrspace(1) undef`, align 8, addrspace 1) + ; GREEDY-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; GREEDY-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; GREEDY-NEXT: G_STORE [[UV1]](s128), [[PTR_ADD]](p1) :: (store (s128) into `ptr addrspace(1) undef` + 16, align 8, addrspace 1) + ; GREEDY-NEXT: [[C3:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 32 + ; GREEDY-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C3]](s64) + ; GREEDY-NEXT: G_STORE [[UV2]](s128), [[PTR_ADD1]](p1) :: (store (s128) into `ptr addrspace(1) undef` + 32, align 8, addrspace 1) + ; GREEDY-NEXT: [[C4:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 48 + ; GREEDY-NEXT: [[PTR_ADD2:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C4]](s64) + ; GREEDY-NEXT: G_STORE [[UV3]](s128), [[PTR_ADD2]](p1) :: (store (s128) into `ptr addrspace(1) undef` + 48, align 8, addrspace 1) + ; GREEDY-NEXT: S_ENDPGM 0 ; GFX7-LABEL: name: s_buffer_load_i512_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -807,6 +1511,50 @@ define amdgpu_ps void @s_buffer_load_i512_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; Test split of a vector with 16-bit elements define amdgpu_ps void @s_buffer_load_v16i16_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v16i16_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(<8 x s16>), [[UV1:%[0-9]+]]:vgpr(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s16>) + ; CHECK-NEXT: G_STORE [[UV]](<8 x s16>), [[DEF]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef`, align 32, addrspace 1) + ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[UV1]](<8 x s16>), [[PTR_ADD]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef` + 16, basealign 32, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + ; GREEDY-LABEL: name: s_buffer_load_v16i16_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(<8 x s16>), [[UV1:%[0-9]+]]:vgpr(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s16>) + ; GREEDY-NEXT: G_STORE [[UV]](<8 x s16>), [[DEF]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef`, align 32, addrspace 1) + ; GREEDY-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; GREEDY-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; GREEDY-NEXT: G_STORE [[UV1]](<8 x s16>), [[PTR_ADD]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef` + 16, basealign 32, addrspace 1) + ; GREEDY-NEXT: S_ENDPGM 0 ; GFX7-LABEL: name: s_buffer_load_v16i16_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -861,6 +1609,66 @@ define amdgpu_ps void @s_buffer_load_v16i16_vgpr_offset(<4 x i32> inreg %rsrc, i ; Test split of a vector with 16-bit elements define amdgpu_ps void @s_buffer_load_v32i16_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v32i16_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<32 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>), [[AMDGPU_BUFFER_LOAD2]](<8 x s16>), [[AMDGPU_BUFFER_LOAD3]](<8 x s16>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(<8 x s16>), [[UV1:%[0-9]+]]:vgpr(<8 x s16>), [[UV2:%[0-9]+]]:vgpr(<8 x s16>), [[UV3:%[0-9]+]]:vgpr(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<32 x s16>) + ; CHECK-NEXT: G_STORE [[UV]](<8 x s16>), [[DEF]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef`, align 64, addrspace 1) + ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[UV1]](<8 x s16>), [[PTR_ADD]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef` + 16, basealign 64, addrspace 1) + ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C3]](s64) + ; CHECK-NEXT: G_STORE [[UV2]](<8 x s16>), [[PTR_ADD1]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef` + 32, align 32, basealign 64, addrspace 1) + ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C4]](s64) + ; CHECK-NEXT: G_STORE [[UV3]](<8 x s16>), [[PTR_ADD2]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef` + 48, basealign 64, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + ; GREEDY-LABEL: name: s_buffer_load_v32i16_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<8 x s16>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<32 x s16>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<8 x s16>), [[AMDGPU_BUFFER_LOAD1]](<8 x s16>), [[AMDGPU_BUFFER_LOAD2]](<8 x s16>), [[AMDGPU_BUFFER_LOAD3]](<8 x s16>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(<8 x s16>), [[UV1:%[0-9]+]]:vgpr(<8 x s16>), [[UV2:%[0-9]+]]:vgpr(<8 x s16>), [[UV3:%[0-9]+]]:vgpr(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<32 x s16>) + ; GREEDY-NEXT: G_STORE [[UV]](<8 x s16>), [[DEF]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef`, align 64, addrspace 1) + ; GREEDY-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; GREEDY-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; GREEDY-NEXT: G_STORE [[UV1]](<8 x s16>), [[PTR_ADD]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef` + 16, basealign 64, addrspace 1) + ; GREEDY-NEXT: [[C3:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 32 + ; GREEDY-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C3]](s64) + ; GREEDY-NEXT: G_STORE [[UV2]](<8 x s16>), [[PTR_ADD1]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef` + 32, align 32, basealign 64, addrspace 1) + ; GREEDY-NEXT: [[C4:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 48 + ; GREEDY-NEXT: [[PTR_ADD2:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C4]](s64) + ; GREEDY-NEXT: G_STORE [[UV3]](<8 x s16>), [[PTR_ADD2]](p1) :: (store (<8 x s16>) into `ptr addrspace(1) undef` + 48, basealign 64, addrspace 1) + ; GREEDY-NEXT: S_ENDPGM 0 ; GFX7-LABEL: name: s_buffer_load_v32i16_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -933,6 +1741,50 @@ define amdgpu_ps void @s_buffer_load_v32i16_vgpr_offset(<4 x i32> inreg %rsrc, i ; Test split of a vector with 64-bit elements define amdgpu_ps void @s_buffer_load_v4i64_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v4i64_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(<2 x s64>), [[UV1:%[0-9]+]]:vgpr(<2 x s64>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s64>) + ; CHECK-NEXT: G_STORE [[UV]](<2 x s64>), [[DEF]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef`, align 32, addrspace 1) + ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[UV1]](<2 x s64>), [[PTR_ADD]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef` + 16, basealign 32, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + ; GREEDY-LABEL: name: s_buffer_load_v4i64_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(<2 x s64>), [[UV1:%[0-9]+]]:vgpr(<2 x s64>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s64>) + ; GREEDY-NEXT: G_STORE [[UV]](<2 x s64>), [[DEF]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef`, align 32, addrspace 1) + ; GREEDY-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; GREEDY-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; GREEDY-NEXT: G_STORE [[UV1]](<2 x s64>), [[PTR_ADD]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef` + 16, basealign 32, addrspace 1) + ; GREEDY-NEXT: S_ENDPGM 0 ; GFX7-LABEL: name: s_buffer_load_v4i64_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -987,6 +1839,66 @@ define amdgpu_ps void @s_buffer_load_v4i64_vgpr_offset(<4 x i32> inreg %rsrc, i3 ; Test split of a vector with 64-bit elements define amdgpu_ps void @s_buffer_load_v8i64_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v8i64_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>), [[AMDGPU_BUFFER_LOAD2]](<2 x s64>), [[AMDGPU_BUFFER_LOAD3]](<2 x s64>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(<2 x s64>), [[UV1:%[0-9]+]]:vgpr(<2 x s64>), [[UV2:%[0-9]+]]:vgpr(<2 x s64>), [[UV3:%[0-9]+]]:vgpr(<2 x s64>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s64>) + ; CHECK-NEXT: G_STORE [[UV]](<2 x s64>), [[DEF]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef`, align 64, addrspace 1) + ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[UV1]](<2 x s64>), [[PTR_ADD]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef` + 16, basealign 64, addrspace 1) + ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C3]](s64) + ; CHECK-NEXT: G_STORE [[UV2]](<2 x s64>), [[PTR_ADD1]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef` + 32, align 32, basealign 64, addrspace 1) + ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C4]](s64) + ; CHECK-NEXT: G_STORE [[UV3]](<2 x s64>), [[PTR_ADD2]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef` + 48, basealign 64, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + ; GREEDY-LABEL: name: s_buffer_load_v8i64_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x s64>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x s64>), [[AMDGPU_BUFFER_LOAD1]](<2 x s64>), [[AMDGPU_BUFFER_LOAD2]](<2 x s64>), [[AMDGPU_BUFFER_LOAD3]](<2 x s64>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(<2 x s64>), [[UV1:%[0-9]+]]:vgpr(<2 x s64>), [[UV2:%[0-9]+]]:vgpr(<2 x s64>), [[UV3:%[0-9]+]]:vgpr(<2 x s64>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s64>) + ; GREEDY-NEXT: G_STORE [[UV]](<2 x s64>), [[DEF]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef`, align 64, addrspace 1) + ; GREEDY-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; GREEDY-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; GREEDY-NEXT: G_STORE [[UV1]](<2 x s64>), [[PTR_ADD]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef` + 16, basealign 64, addrspace 1) + ; GREEDY-NEXT: [[C3:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 32 + ; GREEDY-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C3]](s64) + ; GREEDY-NEXT: G_STORE [[UV2]](<2 x s64>), [[PTR_ADD1]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef` + 32, align 32, basealign 64, addrspace 1) + ; GREEDY-NEXT: [[C4:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 48 + ; GREEDY-NEXT: [[PTR_ADD2:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C4]](s64) + ; GREEDY-NEXT: G_STORE [[UV3]](<2 x s64>), [[PTR_ADD2]](p1) :: (store (<2 x s64>) into `ptr addrspace(1) undef` + 48, basealign 64, addrspace 1) + ; GREEDY-NEXT: S_ENDPGM 0 ; GFX7-LABEL: name: s_buffer_load_v8i64_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -1059,6 +1971,50 @@ define amdgpu_ps void @s_buffer_load_v8i64_vgpr_offset(<4 x i32> inreg %rsrc, i3 ; Test split of a vector with 64-bit pointer elements define amdgpu_ps void @s_buffer_load_v4p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v4p1_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(<2 x p1>), [[UV1:%[0-9]+]]:vgpr(<2 x p1>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x p1>) + ; CHECK-NEXT: G_STORE [[UV]](<2 x p1>), [[DEF]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef`, align 32, addrspace 1) + ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[UV1]](<2 x p1>), [[PTR_ADD]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef` + 16, basealign 32, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + ; GREEDY-LABEL: name: s_buffer_load_v4p1_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(<2 x p1>), [[UV1:%[0-9]+]]:vgpr(<2 x p1>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x p1>) + ; GREEDY-NEXT: G_STORE [[UV]](<2 x p1>), [[DEF]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef`, align 32, addrspace 1) + ; GREEDY-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; GREEDY-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; GREEDY-NEXT: G_STORE [[UV1]](<2 x p1>), [[PTR_ADD]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef` + 16, basealign 32, addrspace 1) + ; GREEDY-NEXT: S_ENDPGM 0 ; GFX7-LABEL: name: s_buffer_load_v4p1_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -1113,6 +2069,66 @@ define amdgpu_ps void @s_buffer_load_v4p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; Test split of a vector with 64-bit pointer elements define amdgpu_ps void @s_buffer_load_v8p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) { + ; CHECK-LABEL: name: s_buffer_load_v8p1_vgpr_offset + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>), [[AMDGPU_BUFFER_LOAD2]](<2 x p1>), [[AMDGPU_BUFFER_LOAD3]](<2 x p1>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(<2 x p1>), [[UV1:%[0-9]+]]:vgpr(<2 x p1>), [[UV2:%[0-9]+]]:vgpr(<2 x p1>), [[UV3:%[0-9]+]]:vgpr(<2 x p1>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x p1>) + ; CHECK-NEXT: G_STORE [[UV]](<2 x p1>), [[DEF]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef`, align 64, addrspace 1) + ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; CHECK-NEXT: G_STORE [[UV1]](<2 x p1>), [[PTR_ADD]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef` + 16, basealign 64, addrspace 1) + ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 32 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C3]](s64) + ; CHECK-NEXT: G_STORE [[UV2]](<2 x p1>), [[PTR_ADD1]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef` + 32, align 32, basealign 64, addrspace 1) + ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C4]](s64) + ; CHECK-NEXT: G_STORE [[UV3]](<2 x p1>), [[PTR_ADD2]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef` + 48, basealign 64, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + ; GREEDY-LABEL: name: s_buffer_load_v8p1_vgpr_offset + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<2 x p1>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x p1>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<2 x p1>), [[AMDGPU_BUFFER_LOAD1]](<2 x p1>), [[AMDGPU_BUFFER_LOAD2]](<2 x p1>), [[AMDGPU_BUFFER_LOAD3]](<2 x p1>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(<2 x p1>), [[UV1:%[0-9]+]]:vgpr(<2 x p1>), [[UV2:%[0-9]+]]:vgpr(<2 x p1>), [[UV3:%[0-9]+]]:vgpr(<2 x p1>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x p1>) + ; GREEDY-NEXT: G_STORE [[UV]](<2 x p1>), [[DEF]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef`, align 64, addrspace 1) + ; GREEDY-NEXT: [[C2:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 16 + ; GREEDY-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C2]](s64) + ; GREEDY-NEXT: G_STORE [[UV1]](<2 x p1>), [[PTR_ADD]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef` + 16, basealign 64, addrspace 1) + ; GREEDY-NEXT: [[C3:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 32 + ; GREEDY-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C3]](s64) + ; GREEDY-NEXT: G_STORE [[UV2]](<2 x p1>), [[PTR_ADD1]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef` + 32, align 32, basealign 64, addrspace 1) + ; GREEDY-NEXT: [[C4:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 48 + ; GREEDY-NEXT: [[PTR_ADD2:%[0-9]+]]:sgpr(p1) = G_PTR_ADD [[DEF]], [[C4]](s64) + ; GREEDY-NEXT: G_STORE [[UV3]](<2 x p1>), [[PTR_ADD2]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) undef` + 48, basealign 64, addrspace 1) + ; GREEDY-NEXT: S_ENDPGM 0 ; GFX7-LABEL: name: s_buffer_load_v8p1_vgpr_offset ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -1184,6 +2200,42 @@ define amdgpu_ps void @s_buffer_load_v8p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 } define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg %rsrc, i32 %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4092, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4092, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -1227,6 +2279,42 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg % } define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg %rsrc, i32 %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4095 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4095, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4095 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4095, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -1270,6 +2358,40 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg % } define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg %rsrc, i32 %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -1313,6 +2435,62 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg % ; Make sure the base offset is added to each split load. define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> inreg %rsrc, i32 %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -1377,6 +2555,60 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> ; Make sure the maximum offset isn't exeeded when splitting this define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> inreg %rsrc, i32 %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -1439,6 +2671,82 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> } define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i32> inreg %rsrc, i32 %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4032 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4032, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4048, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>), [[AMDGPU_BUFFER_LOAD2]](<4 x s32>), [[AMDGPU_BUFFER_LOAD3]](<4 x s32>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32), [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32) + ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32) + ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32) + ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32) + ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32) + ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32) + ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32) + ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; GREEDY-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4032 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4032, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4048, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>), [[AMDGPU_BUFFER_LOAD2]](<4 x s32>), [[AMDGPU_BUFFER_LOAD3]](<4 x s32>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32), [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; GREEDY-NEXT: $vgpr8 = COPY [[UV8]](s32) + ; GREEDY-NEXT: $vgpr9 = COPY [[UV9]](s32) + ; GREEDY-NEXT: $vgpr10 = COPY [[UV10]](s32) + ; GREEDY-NEXT: $vgpr11 = COPY [[UV11]](s32) + ; GREEDY-NEXT: $vgpr12 = COPY [[UV12]](s32) + ; GREEDY-NEXT: $vgpr13 = COPY [[UV13]](s32) + ; GREEDY-NEXT: $vgpr14 = COPY [[UV14]](s32) + ; GREEDY-NEXT: $vgpr15 = COPY [[UV15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -1522,6 +2830,80 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i3 } define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i32> inreg %rsrc, i32 %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4036 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>), [[AMDGPU_BUFFER_LOAD2]](<4 x s32>), [[AMDGPU_BUFFER_LOAD3]](<4 x s32>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32), [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32) + ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32) + ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32) + ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32) + ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32) + ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32) + ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32) + ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 + ; GREEDY-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4036 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 32, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 16, align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 48, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 48, align 4) + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>), [[AMDGPU_BUFFER_LOAD2]](<4 x s32>), [[AMDGPU_BUFFER_LOAD3]](<4 x s32>) + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32), [[UV4:%[0-9]+]]:vgpr(s32), [[UV5:%[0-9]+]]:vgpr(s32), [[UV6:%[0-9]+]]:vgpr(s32), [[UV7:%[0-9]+]]:vgpr(s32), [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV1]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV2]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV3]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV4]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV5]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV6]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV7]](s32) + ; GREEDY-NEXT: $vgpr8 = COPY [[UV8]](s32) + ; GREEDY-NEXT: $vgpr9 = COPY [[UV9]](s32) + ; GREEDY-NEXT: $vgpr10 = COPY [[UV10]](s32) + ; GREEDY-NEXT: $vgpr11 = COPY [[UV11]](s32) + ; GREEDY-NEXT: $vgpr12 = COPY [[UV12]](s32) + ; GREEDY-NEXT: $vgpr13 = COPY [[UV13]](s32) + ; GREEDY-NEXT: $vgpr14 = COPY [[UV14]](s32) + ; GREEDY-NEXT: $vgpr15 = COPY [[UV15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15 ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 @@ -1605,6 +2987,96 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i3 ; Waterfall loop due to resource being VGPR define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %soffset) { + ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %15, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY5]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32) + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %15, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY5]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 @@ -1702,6 +3174,98 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg % ; Use the offset inside the waterfall loop define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %rsrc, i32 inreg %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %16, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[C1]], [[COPY4]], 4092, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4092 + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %16, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[C1]], [[COPY4]], 4092, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 @@ -1802,6 +3366,100 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> % ; Scalar offset exceeds MUBUF limit, keep add out of the loop define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %17, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY5]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096 + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]] + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32) + ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %17, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY5]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 @@ -1903,6 +3561,96 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> % ; Waterfall loop, but constant offset define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc) { + ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4095 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4095 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %15, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C3]](s32), [[C1]], [[C2]], 4095, 0, 0 :: (dereferenceable invariant load (s32) from unknown-address + 4095, align 1) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4095 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4095 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %15, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C3]](s32), [[C1]], [[C2]], 4095, 0, 0 :: (dereferenceable invariant load (s32) from unknown-address + 4095, align 1) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4095 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 @@ -2000,6 +3748,96 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc) ; Waterfall loop, but constant offset define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc) { + ; CHECK-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4096 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %15, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4096 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096 + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %15, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY4]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4096 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 @@ -2098,6 +3936,118 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc) ; Need a waterfall loop, but the offset is scalar. ; Make sure the base offset is added to each split load. define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %rsrc, i32 inreg %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %26, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[C1]], [[COPY4]], 4064, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[C1]], [[COPY4]], 4080, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; CHECK-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064 + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %26, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[C1]], [[COPY4]], 4064, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[C1]], [[COPY4]], 4080, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; GREEDY-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 @@ -2219,6 +4169,120 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> % ; Need a waterfall loop, but the offset is scalar. ; Make sure the maximum offset isn't exeeded when splitting this define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %rsrc, i32 inreg %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %27, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY5]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY5]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; CHECK-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4068 + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]] + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32) + ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %27, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY5]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY5]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; GREEDY-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 @@ -2339,6 +4403,120 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> % } define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) { + ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %27, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY5]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY5]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; CHECK-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4096 + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY4]], [[C]] + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32) + ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %27, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY5]], [[C1]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C2]](s32), [[COPY5]], [[C1]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; GREEDY-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 @@ -2459,6 +4637,118 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> % } define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000(<4 x i32> %rsrc, i32 %offset.base) { + ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5000 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %26, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; CHECK-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5000 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %26, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; GREEDY-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 @@ -2579,6 +4869,118 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000 } define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076(<4 x i32> %rsrc, i32 %offset.base) { + ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4076 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %26, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; CHECK-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4076 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %26, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; GREEDY-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 @@ -2699,6 +5101,118 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076 } define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080(<4 x i32> %rsrc, i32 %offset.base) { + ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4080 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %26, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; CHECK-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4080 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY5]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %26, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C1]](s32), [[COPY4]], [[C]], 16, 0, 0 :: (dereferenceable invariant load (s128), align 4) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; GREEDY-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 @@ -2819,6 +5333,116 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080 } define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4064(<4 x i32> %rsrc, i32 %offset.base) { + ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4064 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %26, %bb.3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; CHECK-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C3]](s32), [[C1]], [[C2]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 4064, align 4) + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C3]](s32), [[C1]], [[C2]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 4064, align 4) + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; CHECK-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; CHECK-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; CHECK-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; CHECK-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; CHECK-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; CHECK-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; CHECK-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; CHECK-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 + ; GREEDY-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4064 + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4064 + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF + ; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.2: + ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.1, %26, %bb.3 + ; GREEDY-NEXT: [[UV:%[0-9]+]]:vgpr_32(s32), [[UV1:%[0-9]+]]:vgpr_32(s32), [[UV2:%[0-9]+]]:vgpr_32(s32), [[UV3:%[0-9]+]]:vgpr_32(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV1]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV2]](s32), implicit $exec + ; GREEDY-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[UV3]](s32), implicit $exec + ; GREEDY-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32) + ; GREEDY-NEXT: [[UV4:%[0-9]+]]:vgpr(s64), [[UV5:%[0-9]+]]:vgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>) + ; GREEDY-NEXT: [[UV6:%[0-9]+]]:sgpr(s64), [[UV7:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>) + ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV6]](s64), [[UV4]] + ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[UV7]](s64), [[UV5]] + ; GREEDY-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] + ; GREEDY-NEXT: [[INT:%[0-9]+]]:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[AND]](s1) + ; GREEDY-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[INT]](s64), implicit-def $exec, implicit-def $scc, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.3: + ; GREEDY-NEXT: successors: %bb.4, %bb.2 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C3]](s32), [[C1]], [[C2]], 4064, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 4064, align 4) + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR1]](<4 x s32>), [[C3]](s32), [[C1]], [[C2]], 4080, 0, 0 :: (dereferenceable invariant load (s128) from unknown-address + 4064, align 4) + ; GREEDY-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc + ; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.4: + ; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: bb.5: + ; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>) + ; GREEDY-NEXT: [[UV8:%[0-9]+]]:vgpr(s32), [[UV9:%[0-9]+]]:vgpr(s32), [[UV10:%[0-9]+]]:vgpr(s32), [[UV11:%[0-9]+]]:vgpr(s32), [[UV12:%[0-9]+]]:vgpr(s32), [[UV13:%[0-9]+]]:vgpr(s32), [[UV14:%[0-9]+]]:vgpr(s32), [[UV15:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>) + ; GREEDY-NEXT: $vgpr0 = COPY [[UV8]](s32) + ; GREEDY-NEXT: $vgpr1 = COPY [[UV9]](s32) + ; GREEDY-NEXT: $vgpr2 = COPY [[UV10]](s32) + ; GREEDY-NEXT: $vgpr3 = COPY [[UV11]](s32) + ; GREEDY-NEXT: $vgpr4 = COPY [[UV12]](s32) + ; GREEDY-NEXT: $vgpr5 = COPY [[UV13]](s32) + ; GREEDY-NEXT: $vgpr6 = COPY [[UV14]](s32) + ; GREEDY-NEXT: $vgpr7 = COPY [[UV15]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7 ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4064 ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 @@ -2935,6 +5559,40 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4 } define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) { + ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]] + ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]] + ; GREEDY-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 @@ -2976,6 +5634,40 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr(<4 x i32> inreg % } define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) { + ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]] + ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]] + ; GREEDY-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 @@ -3017,6 +5709,48 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr(<4 x i32> inreg % } define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) { + ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]] + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]] + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024 + ; GREEDY-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 @@ -3067,6 +5801,48 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inr } define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) { + ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]] + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]] + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024 + ; GREEDY-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C2]](s32), [[ADD]], [[C1]], 1024, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 @@ -3118,6 +5894,44 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inr ; TODO: Ideally this would be reassociated to fold. define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) { + ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY5]], [[C]] + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[ADD]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024 + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY5]], [[C]] + ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32) + ; GREEDY-NEXT: [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY4]], [[ADD]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 @@ -3168,6 +5982,46 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inr } define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) { + ; CHECK-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]] + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[ADD]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; GREEDY-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr + ; GREEDY: bb.1 (%ir-block.0): + ; GREEDY-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GREEDY-NEXT: {{ $}} + ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4 + ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 + ; GREEDY-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6 + ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024 + ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]] + ; GREEDY-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32) + ; GREEDY-NEXT: [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]] + ; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; GREEDY-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(s32) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[ADD]], [[COPY5]], 0, 0, 0 :: (dereferenceable invariant load (s32)) + ; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32) + ; GREEDY-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr ; GFX7: bb.1 (%ir-block.0): ; GFX7-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll index 003aa049b2d1b..324d853145924 100644 --- a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll +++ b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll @@ -337,7 +337,6 @@ define void @flat_atomic_xchg_i32_ret_av_av_no_agprs(ptr %ptr) #0 { ; GFX90A-LABEL: flat_atomic_xchg_i32_ret_av_av_no_agprs: ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX90A-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse @@ -354,6 +353,7 @@ define void @flat_atomic_xchg_i32_ret_av_av_no_agprs(ptr %ptr) #0 { ; GFX90A-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse +; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def v[0:31] @@ -464,7 +464,6 @@ define void @flat_atomic_xchg_i32_ret_av_av_no_agprs(ptr %ptr) #0 { ; GFX950-LABEL: flat_atomic_xchg_i32_ret_av_av_no_agprs: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX950-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX950-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse @@ -481,6 +480,7 @@ define void @flat_atomic_xchg_i32_ret_av_av_no_agprs(ptr %ptr) #0 { ; GFX950-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX950-NEXT: v_accvgpr_write_b32 a1, v1 ; GFX950-NEXT: ;;#ASMSTART ; GFX950-NEXT: ; def v[0:31] @@ -4006,7 +4006,6 @@ define void @flat_atomic_xor_i32_ret_av_av_no_agprs(ptr %ptr) #0 { ; GFX90A-LABEL: flat_atomic_xor_i32_ret_av_av_no_agprs: ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX90A-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse @@ -4023,6 +4022,7 @@ define void @flat_atomic_xor_i32_ret_av_av_no_agprs(ptr %ptr) #0 { ; GFX90A-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse +; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def v[0:31] @@ -4131,7 +4131,6 @@ define void @flat_atomic_xor_i32_ret_av_av_no_agprs(ptr %ptr) #0 { ; GFX950-LABEL: flat_atomic_xor_i32_ret_av_av_no_agprs: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX950-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX950-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse @@ -4148,6 +4147,7 @@ define void @flat_atomic_xor_i32_ret_av_av_no_agprs(ptr %ptr) #0 { ; GFX950-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX950-NEXT: v_accvgpr_write_b32 a1, v1 ; GFX950-NEXT: ;;#ASMSTART ; GFX950-NEXT: ; def v[0:31] diff --git a/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll index 34a4899123749..e67d5b0fad14a 100644 --- a/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll +++ b/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll @@ -337,7 +337,6 @@ define void @global_atomic_xchg_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0 ; GFX90A-LABEL: global_atomic_xchg_i32_ret_av_av_no_agprs: ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX90A-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse @@ -354,6 +353,7 @@ define void @global_atomic_xchg_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse +; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def v[0:31] @@ -464,7 +464,6 @@ define void @global_atomic_xchg_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0 ; GFX950-LABEL: global_atomic_xchg_i32_ret_av_av_no_agprs: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX950-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX950-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse @@ -481,6 +480,7 @@ define void @global_atomic_xchg_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX950-NEXT: v_accvgpr_write_b32 a1, v1 ; GFX950-NEXT: ;;#ASMSTART ; GFX950-NEXT: ; def v[0:31] @@ -2985,7 +2985,6 @@ define void @global_atomic_xor_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0 ; GFX90A-LABEL: global_atomic_xor_i32_ret_av_av_no_agprs: ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX90A-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse @@ -3002,6 +3001,7 @@ define void @global_atomic_xor_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse +; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def v[0:31] @@ -3110,7 +3110,6 @@ define void @global_atomic_xor_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0 ; GFX950-LABEL: global_atomic_xor_i32_ret_av_av_no_agprs: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX950-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX950-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse @@ -3127,6 +3126,7 @@ define void @global_atomic_xor_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a0, v0 ; GFX950-NEXT: v_accvgpr_write_b32 a1, v1 ; GFX950-NEXT: ;;#ASMSTART ; GFX950-NEXT: ; def v[0:31] diff --git a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll index 3194581fa4213..2d7cfcea04124 100644 --- a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll +++ b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll @@ -23,15 +23,15 @@ define void @parent_func_missing_inputs() #0 { ; FIXEDABI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; FIXEDABI-NEXT: s_mov_b64 exec, s[18:19] ; FIXEDABI-NEXT: v_writelane_b32 v40, s16, 2 -; FIXEDABI-NEXT: s_addk_i32 s32, 0x400 ; FIXEDABI-NEXT: v_writelane_b32 v40, s30, 0 +; FIXEDABI-NEXT: s_addk_i32 s32, 0x400 +; FIXEDABI-NEXT: v_writelane_b32 v40, s31, 1 ; FIXEDABI-NEXT: s_getpc_b64 s[16:17] ; FIXEDABI-NEXT: s_add_u32 s16, s16, requires_all_inputs@rel32@lo+4 ; FIXEDABI-NEXT: s_addc_u32 s17, s17, requires_all_inputs@rel32@hi+12 -; FIXEDABI-NEXT: v_writelane_b32 v40, s31, 1 ; FIXEDABI-NEXT: s_swappc_b64 s[30:31], s[16:17] -; FIXEDABI-NEXT: v_readlane_b32 s31, v40, 1 ; FIXEDABI-NEXT: v_readlane_b32 s30, v40, 0 +; FIXEDABI-NEXT: v_readlane_b32 s31, v40, 1 ; FIXEDABI-NEXT: s_mov_b32 s32, s33 ; FIXEDABI-NEXT: v_readlane_b32 s4, v40, 2 ; FIXEDABI-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir index c1617574becc3..c8131bbdd363d 100644 --- a/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir +++ b/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir @@ -26,6 +26,1094 @@ body: | ; GFX908-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -49,230 +1137,1366 @@ body: | ; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec @@ -520,6 +2744,1094 @@ body: | ; GFX908-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-FLATSCR-NEXT: {{ $}} + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -544,230 +3856,1366 @@ body: | ; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -1044,6 +5492,1094 @@ body: | ; GFX908-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -1069,230 +6605,1366 @@ body: | ; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec @@ -1541,6 +8213,1094 @@ body: | ; GFX908-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-FLATSCR-NEXT: {{ $}} + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -1567,230 +9327,1366 @@ body: | ; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -2067,6 +10963,1094 @@ body: | ; GFX908-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -2094,230 +12078,1366 @@ body: | ; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec @@ -2567,6 +13687,1094 @@ body: | ; GFX908-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-FLATSCR-NEXT: {{ $}} + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -2595,230 +14803,1366 @@ body: | ; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -3095,6 +16439,1094 @@ body: | ; GFX908-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0 ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -3118,230 +17550,1366 @@ body: | ; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-NEXT: liveins: $agpr0, $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec @@ -3589,6 +19157,1094 @@ body: | ; GFX908-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0 ; GFX908-FLATSCR-NEXT: {{ $}} + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION 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undefined $agpr66 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -3613,230 +20269,1366 @@ body: | ; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-FLATSCR-NEXT: liveins: $agpr0, $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -4112,6 +21904,1094 @@ body: | ; GFX908-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1 ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -4137,230 +23017,1366 @@ body: | ; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec @@ -4609,6 +24625,1094 @@ body: | ; GFX908-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1 ; GFX908-FLATSCR-NEXT: {{ $}} + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -4635,230 +25739,1366 @@ body: | ; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -5133,6 +27373,1094 @@ body: | ; GFX908-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1 ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -5160,230 +28488,1366 @@ body: | ; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec @@ -5633,6 +30097,1094 @@ body: | ; GFX908-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1 ; GFX908-FLATSCR-NEXT: {{ $}} + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX908-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -5661,230 +31213,1366 @@ body: | ; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256 ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0 ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll index 37f2b8f41c22c..8b80370041363 100644 --- a/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll @@ -12,7 +12,6 @@ define void @flat_user(ptr %ptr) { ; CHECK-LABEL: {{^}}cast_alloca: ; CHECK: s_mov_b64 s[{{[0-9]+}}:[[HIREG:[0-9]+]]], src_private_base ; CHECK: v_mov_b32_e32 v1, s[[HIREG]] -; CHECK-NOT: v0 ; CHECK-NOT: v1 define void @cast_alloca() { %alloca = alloca i8, addrspace(5) @@ -27,7 +26,6 @@ define void @cast_alloca() { ; CHECK: s_mov_b64 s[{{[0-9]+}}:[[HIREG:[0-9]+]]], src_shared_base ; CHECK: v_mov_b32_e32 v0, 0 ; CHECK: v_mov_b32_e32 v1, s[[HIREG]] -; CHECK-NOT: v0 ; CHECK-NOT: v1 define amdgpu_kernel void @cast_lds_gv() { %cast = addrspacecast ptr addrspace(3) @lds to ptr diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll index ebbeab94066d6..a21db73cf3714 100644 --- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll +++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll @@ -451,6 +451,7 @@ define void @v32_asm_def_use(float %v0, float %v1) #4 { ; GFX90A-LABEL: v32_asm_def_use: ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-NEXT: v_accvgpr_read_b32 v35, a32 ; Reload Reuse ; GFX90A-NEXT: v_mov_b32_e32 v34, v0 ; GFX90A-NEXT: v_mov_b32_e32 v33, v1 ; GFX90A-NEXT: ;;#ASMSTART @@ -478,8 +479,8 @@ define void @v32_asm_def_use(float %v0, float %v1) #4 { ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; copy ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_accvgpr_read_b32 v35, a32 ; Reload Reuse ; GFX90A-NEXT: v_accvgpr_mov_b32 a32, a1 +; GFX90A-NEXT: s_nop 0 ; GFX90A-NEXT: v_mfma_f32_16x16x1f32 a[0:15], v34, v33, a[16:31] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; copy @@ -1056,6 +1057,7 @@ define void @no_free_vgprs_at_sgpr_to_agpr_copy(float %v0, float %v1) #0 { ; GFX90A-LABEL: no_free_vgprs_at_sgpr_to_agpr_copy: ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-NEXT: v_accvgpr_read_b32 v34, a32 ; Reload Reuse ; GFX90A-NEXT: v_mov_b32_e32 v33, v0 ; GFX90A-NEXT: v_mov_b32_e32 v32, v1 ; GFX90A-NEXT: ;;#ASMSTART @@ -1077,8 +1079,7 @@ define void @no_free_vgprs_at_sgpr_to_agpr_copy(float %v0, float %v1) #0 { ; GFX90A-NEXT: v_accvgpr_write_b32 a18, s2 ; GFX90A-NEXT: v_accvgpr_write_b32 a17, s1 ; GFX90A-NEXT: v_accvgpr_write_b32 a16, s0 -; GFX90A-NEXT: v_accvgpr_read_b32 v34, a32 ; Reload Reuse -; GFX90A-NEXT: s_nop 0 +; GFX90A-NEXT: s_nop 1 ; GFX90A-NEXT: v_mfma_f32_16x16x1f32 a[0:15], v33, v32, a[16:31] ; GFX90A-NEXT: s_nop 10 ; GFX90A-NEXT: buffer_store_dword a0, off, s[0:3], s32 ; 4-byte Folded Spill diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir b/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir index 1573903945a3e..7f26e413cf780 100644 --- a/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir +++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir @@ -11,6 +11,16 @@ body: | ; GFX908-LABEL: name: standard ; GFX908: liveins: $vgpr0, $vgpr1 ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa , 0, 6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 ; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec ; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec @@ -42,6 +52,14 @@ body: | ; GFX908-LABEL: name: src_is_spill ; GFX908: liveins: $vgpr0, $vgpr1 ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; GFX908-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1 @@ -66,6 +84,12 @@ body: | ; GFX908-LABEL: name: overlapping_agpr ; GFX908: liveins: $agpr0_agpr1_agpr2_agpr3 ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa , 0, 6 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 ; GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $agpr1_agpr2_agpr3_agpr4 ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 diff --git a/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir b/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir index 47d489b7f35ca..6e5f8aceaf169 100644 --- a/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir @@ -18,6 +18,54 @@ body: | ; GFX942-LABEL: name: agpr_spill_copy ; GFX942: liveins: $agpr30, $agpr31 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 ; GFX942-NEXT: renamable $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27 = IMPLICIT_DEF ; GFX942-NEXT: renamable $agpr28_agpr29 = IMPLICIT_DEF ; GFX942-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll b/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll index 356bf4b3cac28..5943fdc10c14d 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll @@ -19,24 +19,25 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr) ; DAGISEL-NEXT: s_wait_alu 0xfffe ; DAGISEL-NEXT: s_mov_b32 exec_lo, s1 ; DAGISEL-NEXT: v_writelane_b32 v42, s0, 2 +; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16 ; DAGISEL-NEXT: s_clause 0x1 ; DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v41, s33 +; DAGISEL-NEXT: v_writelane_b32 v42, s30, 0 +; DAGISEL-NEXT: v_writelane_b32 v42, s31, 1 ; DAGISEL-NEXT: v_dual_mov_b32 v41, v2 :: v_dual_mov_b32 v40, v1 ; DAGISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0 -; DAGISEL-NEXT: v_writelane_b32 v42, s30, 0 ; DAGISEL-NEXT: s_mov_b32 s1, good_callee@abs32@hi ; DAGISEL-NEXT: s_mov_b32 s0, good_callee@abs32@lo -; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16 -; DAGISEL-NEXT: v_writelane_b32 v42, s31, 1 ; DAGISEL-NEXT: s_wait_alu 0xfffe ; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] ; DAGISEL-NEXT: global_store_b32 v[40:41], v0, off ; DAGISEL-NEXT: s_clause 0x1 ; DAGISEL-NEXT: scratch_load_b32 v41, off, s33 ; DAGISEL-NEXT: scratch_load_b32 v40, off, s33 offset:4 -; DAGISEL-NEXT: v_readlane_b32 s31, v42, 1 ; DAGISEL-NEXT: v_readlane_b32 s30, v42, 0 +; DAGISEL-NEXT: v_readlane_b32 s31, v42, 1 ; DAGISEL-NEXT: s_mov_b32 s32, s33 ; DAGISEL-NEXT: v_readlane_b32 s0, v42, 2 ; DAGISEL-NEXT: s_or_saveexec_b32 s1, -1 @@ -62,24 +63,25 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr) ; GISEL-NEXT: s_wait_alu 0xfffe ; GISEL-NEXT: s_mov_b32 exec_lo, s1 ; GISEL-NEXT: v_writelane_b32 v42, s0, 2 +; GISEL-NEXT: s_add_co_i32 s32, s32, 16 ; GISEL-NEXT: s_clause 0x1 ; GISEL-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v41, s33 +; GISEL-NEXT: v_writelane_b32 v42, s30, 0 +; GISEL-NEXT: v_writelane_b32 v42, s31, 1 ; GISEL-NEXT: v_dual_mov_b32 v40, v1 :: v_dual_mov_b32 v41, v2 ; GISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0 -; GISEL-NEXT: v_writelane_b32 v42, s30, 0 ; GISEL-NEXT: s_mov_b32 s0, good_callee@abs32@lo ; GISEL-NEXT: s_mov_b32 s1, good_callee@abs32@hi -; GISEL-NEXT: s_add_co_i32 s32, s32, 16 -; GISEL-NEXT: v_writelane_b32 v42, s31, 1 ; GISEL-NEXT: s_wait_alu 0xfffe ; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GISEL-NEXT: global_store_b32 v[40:41], v0, off ; GISEL-NEXT: s_clause 0x1 ; GISEL-NEXT: scratch_load_b32 v41, off, s33 ; GISEL-NEXT: scratch_load_b32 v40, off, s33 offset:4 -; GISEL-NEXT: v_readlane_b32 s31, v42, 1 ; GISEL-NEXT: v_readlane_b32 s30, v42, 0 +; GISEL-NEXT: v_readlane_b32 s31, v42, 1 ; GISEL-NEXT: s_mov_b32 s32, s33 ; GISEL-NEXT: v_readlane_b32 s0, v42, 2 ; GISEL-NEXT: s_or_saveexec_b32 s1, -1 @@ -138,152 +140,291 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x, ; DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v6, s32 offset:24 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v7, s32 offset:28 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v8, s32 offset:32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v9, s32 offset:36 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v10, s32 offset:40 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v11, s32 offset:44 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v12, s32 offset:48 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v13, s32 offset:52 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v14, s32 offset:56 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v15, s32 offset:60 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v16, s32 offset:64 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v17, s32 offset:68 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v18, s32 offset:72 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v19, s32 offset:76 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v20, s32 offset:80 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v21, s32 offset:84 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v22, s32 offset:88 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v23, s32 offset:92 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v24, s32 offset:96 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v25, s32 offset:100 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v26, s32 offset:104 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v27, s32 offset:108 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v28, s32 offset:112 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v35, s32 offset:140 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v36, s32 offset:144 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v37, s32 offset:148 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v38, s32 offset:152 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v39, s32 offset:156 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v48, s32 offset:160 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:164 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v50, s32 offset:168 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v51, s32 offset:172 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v52, s32 offset:176 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v53, s32 offset:180 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v54, s32 offset:184 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v55, s32 offset:188 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v64, s32 offset:192 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v65, s32 offset:196 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v66, s32 offset:200 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v67, s32 offset:204 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v68, s32 offset:208 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v69, s32 offset:212 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v70, s32 offset:216 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v71, s32 offset:220 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v80, s32 offset:224 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v81, s32 offset:228 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v82, s32 offset:232 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v83, s32 offset:236 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v84, s32 offset:240 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v99, s32 offset:268 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v100, s32 offset:272 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v101, s32 offset:276 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v102, s32 offset:280 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v103, s32 offset:284 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v112, s32 offset:288 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v113, s32 offset:292 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v114, s32 offset:296 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v115, s32 offset:300 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v116, s32 offset:304 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v117, s32 offset:308 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v118, s32 offset:312 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v119, s32 offset:316 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v128, s32 offset:320 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v129, s32 offset:324 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v130, s32 offset:328 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v131, s32 offset:332 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v132, s32 offset:336 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v133, s32 offset:340 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v134, s32 offset:344 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v135, s32 offset:348 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v144, s32 offset:352 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v145, s32 offset:356 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v146, s32 offset:360 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v147, s32 offset:364 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v148, s32 offset:368 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v163, s32 offset:396 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v164, s32 offset:400 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v165, s32 offset:404 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v166, s32 offset:408 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v167, s32 offset:412 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v176, s32 offset:416 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v177, s32 offset:420 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v178, s32 offset:424 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v179, s32 offset:428 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v180, s32 offset:432 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v181, s32 offset:436 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v182, s32 offset:440 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v183, s32 offset:444 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v192, s32 offset:448 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v193, s32 offset:452 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v194, s32 offset:456 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v195, s32 offset:460 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v196, s32 offset:464 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v197, s32 offset:468 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v198, s32 offset:472 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v199, s32 offset:476 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v208, s32 offset:480 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v209, s32 offset:484 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v210, s32 offset:488 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v211, s32 offset:492 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v212, s32 offset:496 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508 ; DAGISEL-NEXT: s_clause 0xf ; DAGISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v227, s32 offset:524 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v228, s32 offset:528 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v229, s32 offset:532 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v230, s32 offset:536 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v231, s32 offset:540 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v240, s32 offset:544 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v241, s32 offset:548 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v242, s32 offset:552 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v243, s32 offset:556 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v244, s32 offset:560 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v245, s32 offset:564 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v246, s32 offset:568 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v247, s32 offset:572 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0 @@ -453,152 +594,291 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x, ; GISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v0, s32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v6, s32 offset:24 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v7, s32 offset:28 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v8, s32 offset:32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v9, s32 offset:36 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v10, s32 offset:40 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v11, s32 offset:44 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v12, s32 offset:48 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v13, s32 offset:52 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v14, s32 offset:56 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v15, s32 offset:60 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v16, s32 offset:64 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v17, s32 offset:68 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v18, s32 offset:72 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v19, s32 offset:76 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v20, s32 offset:80 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v21, s32 offset:84 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v22, s32 offset:88 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v23, s32 offset:92 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v24, s32 offset:96 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v25, s32 offset:100 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v26, s32 offset:104 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v27, s32 offset:108 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v28, s32 offset:112 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v35, s32 offset:140 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v36, s32 offset:144 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v37, s32 offset:148 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v38, s32 offset:152 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v39, s32 offset:156 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v48, s32 offset:160 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v49, s32 offset:164 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v50, s32 offset:168 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v51, s32 offset:172 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v52, s32 offset:176 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v53, s32 offset:180 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v54, s32 offset:184 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v55, s32 offset:188 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v64, s32 offset:192 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v65, s32 offset:196 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v66, s32 offset:200 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v67, s32 offset:204 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v68, s32 offset:208 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v69, s32 offset:212 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v70, s32 offset:216 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v71, s32 offset:220 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v80, s32 offset:224 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v81, s32 offset:228 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v82, s32 offset:232 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v83, s32 offset:236 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v84, s32 offset:240 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v99, s32 offset:268 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v100, s32 offset:272 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v101, s32 offset:276 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v102, s32 offset:280 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v103, s32 offset:284 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v112, s32 offset:288 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v113, s32 offset:292 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v114, s32 offset:296 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v115, s32 offset:300 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v116, s32 offset:304 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v117, s32 offset:308 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v118, s32 offset:312 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v119, s32 offset:316 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v128, s32 offset:320 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v129, s32 offset:324 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v130, s32 offset:328 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v131, s32 offset:332 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v132, s32 offset:336 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v133, s32 offset:340 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v134, s32 offset:344 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v135, s32 offset:348 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v144, s32 offset:352 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v145, s32 offset:356 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v146, s32 offset:360 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v147, s32 offset:364 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v148, s32 offset:368 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v163, s32 offset:396 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v164, s32 offset:400 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v165, s32 offset:404 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v166, s32 offset:408 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v167, s32 offset:412 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v176, s32 offset:416 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v177, s32 offset:420 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v178, s32 offset:424 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v179, s32 offset:428 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v180, s32 offset:432 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v181, s32 offset:436 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v182, s32 offset:440 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v183, s32 offset:444 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v192, s32 offset:448 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v193, s32 offset:452 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v194, s32 offset:456 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v195, s32 offset:460 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v196, s32 offset:464 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v197, s32 offset:468 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v198, s32 offset:472 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v199, s32 offset:476 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v208, s32 offset:480 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v209, s32 offset:484 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v210, s32 offset:488 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v211, s32 offset:492 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v212, s32 offset:496 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508 ; GISEL-NEXT: s_clause 0xf ; GISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v227, s32 offset:524 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v228, s32 offset:528 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v229, s32 offset:532 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v230, s32 offset:536 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v231, s32 offset:540 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v240, s32 offset:544 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v241, s32 offset:548 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v242, s32 offset:552 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v243, s32 offset:556 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v244, s32 offset:560 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v245, s32 offset:564 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v246, s32 offset:568 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v247, s32 offset:572 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0 @@ -779,16 +1059,15 @@ define amdgpu_gfx void @ret_void(i32 %x) { ; DAGISEL-NEXT: s_wait_alu 0xfffe ; DAGISEL-NEXT: s_mov_b32 exec_lo, s1 ; DAGISEL-NEXT: v_writelane_b32 v40, s0, 2 -; DAGISEL-NEXT: s_mov_b32 s1, void_callee@abs32@hi -; DAGISEL-NEXT: s_mov_b32 s0, void_callee@abs32@lo -; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16 ; DAGISEL-NEXT: v_writelane_b32 v40, s30, 0 +; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16 ; DAGISEL-NEXT: v_writelane_b32 v40, s31, 1 +; DAGISEL-NEXT: s_mov_b32 s1, void_callee@abs32@hi +; DAGISEL-NEXT: s_mov_b32 s0, void_callee@abs32@lo ; DAGISEL-NEXT: s_wait_alu 0xfffe ; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] -; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; DAGISEL-NEXT: v_readlane_b32 s31, v40, 1 ; DAGISEL-NEXT: v_readlane_b32 s30, v40, 0 +; DAGISEL-NEXT: v_readlane_b32 s31, v40, 1 ; DAGISEL-NEXT: s_mov_b32 s32, s33 ; DAGISEL-NEXT: v_readlane_b32 s0, v40, 2 ; DAGISEL-NEXT: s_or_saveexec_b32 s1, -1 @@ -814,16 +1093,15 @@ define amdgpu_gfx void @ret_void(i32 %x) { ; GISEL-NEXT: s_wait_alu 0xfffe ; GISEL-NEXT: s_mov_b32 exec_lo, s1 ; GISEL-NEXT: v_writelane_b32 v40, s0, 2 -; GISEL-NEXT: s_mov_b32 s0, void_callee@abs32@lo -; GISEL-NEXT: s_mov_b32 s1, void_callee@abs32@hi -; GISEL-NEXT: s_add_co_i32 s32, s32, 16 ; GISEL-NEXT: v_writelane_b32 v40, s30, 0 +; GISEL-NEXT: s_add_co_i32 s32, s32, 16 ; GISEL-NEXT: v_writelane_b32 v40, s31, 1 +; GISEL-NEXT: s_mov_b32 s0, void_callee@abs32@lo +; GISEL-NEXT: s_mov_b32 s1, void_callee@abs32@hi ; GISEL-NEXT: s_wait_alu 0xfffe ; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GISEL-NEXT: v_readlane_b32 s31, v40, 1 ; GISEL-NEXT: v_readlane_b32 s30, v40, 0 +; GISEL-NEXT: v_readlane_b32 s31, v40, 1 ; GISEL-NEXT: s_mov_b32 s32, s33 ; GISEL-NEXT: v_readlane_b32 s0, v40, 2 ; GISEL-NEXT: s_or_saveexec_b32 s1, -1 diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll index 74552a500ac51..7aa648f674f35 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll @@ -6757,24 +6757,43 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x13 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12 ; GFX11-FAKE16-NEXT: s_clause 0x2 ; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8 @@ -7466,42 +7485,43 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_writelane_b32 v20, s69, 21 -; SI-NEXT: v_writelane_b32 v20, s70, 22 -; SI-NEXT: v_writelane_b32 v20, s71, 23 -; SI-NEXT: v_writelane_b32 v20, s80, 24 -; SI-NEXT: v_writelane_b32 v20, s81, 25 -; SI-NEXT: v_writelane_b32 v20, s82, 26 -; SI-NEXT: v_writelane_b32 v20, s83, 27 -; SI-NEXT: v_writelane_b32 v20, s84, 28 -; SI-NEXT: v_writelane_b32 v20, s85, 29 -; SI-NEXT: v_writelane_b32 v20, s86, 30 -; SI-NEXT: v_writelane_b32 v20, s87, 31 -; SI-NEXT: v_writelane_b32 v20, s96, 32 -; SI-NEXT: v_writelane_b32 v20, s97, 33 +; SI-NEXT: v_writelane_b32 v20, s34, 0 +; SI-NEXT: v_writelane_b32 v20, s35, 1 +; SI-NEXT: v_writelane_b32 v20, s36, 2 +; SI-NEXT: v_writelane_b32 v20, s37, 3 +; SI-NEXT: v_writelane_b32 v20, s38, 4 +; SI-NEXT: v_writelane_b32 v20, s39, 5 +; SI-NEXT: v_writelane_b32 v20, s48, 6 +; SI-NEXT: v_writelane_b32 v20, s49, 7 +; SI-NEXT: v_writelane_b32 v20, s50, 8 +; SI-NEXT: v_writelane_b32 v20, s51, 9 +; SI-NEXT: v_writelane_b32 v20, s52, 10 +; SI-NEXT: v_writelane_b32 v20, s53, 11 +; SI-NEXT: v_writelane_b32 v20, s54, 12 +; SI-NEXT: v_writelane_b32 v20, s55, 13 +; SI-NEXT: v_writelane_b32 v20, s64, 14 +; SI-NEXT: v_writelane_b32 v20, s65, 15 +; SI-NEXT: v_writelane_b32 v20, s66, 16 +; SI-NEXT: v_writelane_b32 v20, s67, 17 +; SI-NEXT: v_writelane_b32 v20, s68, 18 +; SI-NEXT: v_writelane_b32 v20, s69, 19 +; SI-NEXT: v_writelane_b32 v20, s70, 20 +; SI-NEXT: v_writelane_b32 v20, s71, 21 +; SI-NEXT: v_writelane_b32 v20, s80, 22 +; SI-NEXT: v_writelane_b32 v20, s81, 23 +; SI-NEXT: v_writelane_b32 v20, s82, 24 +; SI-NEXT: v_writelane_b32 v20, s83, 25 +; SI-NEXT: v_writelane_b32 v20, s84, 26 +; SI-NEXT: v_writelane_b32 v20, s85, 27 +; SI-NEXT: v_writelane_b32 v20, s86, 28 +; SI-NEXT: v_writelane_b32 v20, s87, 29 +; SI-NEXT: v_writelane_b32 v20, s96, 30 +; SI-NEXT: v_writelane_b32 v20, s97, 31 +; SI-NEXT: v_writelane_b32 v20, s98, 32 +; SI-NEXT: v_writelane_b32 v20, s99, 33 +; SI-NEXT: v_writelane_b32 v20, s30, 34 +; SI-NEXT: v_writelane_b32 v20, s31, 35 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s98, 34 ; SI-NEXT: v_readfirstlane_b32 s44, v1 ; SI-NEXT: v_readfirstlane_b32 s45, v2 ; SI-NEXT: v_readfirstlane_b32 s42, v3 @@ -7521,7 +7541,6 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v17 ; SI-NEXT: s_and_b64 s[46:47], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v18 -; SI-NEXT: v_writelane_b32 v20, s99, 35 ; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane ; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB13_4 @@ -8391,6 +8410,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v20, 34 ; SI-NEXT: v_readlane_b32 s19, v22, 11 ; SI-NEXT: v_readlane_b32 s17, v22, 17 ; SI-NEXT: v_readlane_b32 s15, v22, 23 @@ -8398,42 +8418,41 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: v_readlane_b32 s11, v22, 35 ; SI-NEXT: v_readlane_b32 s9, v22, 41 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v20, 35 -; SI-NEXT: v_readlane_b32 s98, v20, 34 -; SI-NEXT: v_readlane_b32 s97, v20, 33 -; SI-NEXT: v_readlane_b32 s96, v20, 32 -; SI-NEXT: v_readlane_b32 s87, v20, 31 -; SI-NEXT: v_readlane_b32 s86, v20, 30 -; SI-NEXT: v_readlane_b32 s85, v20, 29 -; SI-NEXT: v_readlane_b32 s84, v20, 28 -; SI-NEXT: v_readlane_b32 s83, v20, 27 -; SI-NEXT: v_readlane_b32 s82, v20, 26 -; SI-NEXT: v_readlane_b32 s81, v20, 25 -; SI-NEXT: v_readlane_b32 s80, v20, 24 -; SI-NEXT: v_readlane_b32 s71, v20, 23 -; SI-NEXT: v_readlane_b32 s70, v20, 22 -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s31, v20, 35 +; SI-NEXT: v_readlane_b32 s99, v20, 33 +; SI-NEXT: v_readlane_b32 s98, v20, 32 +; SI-NEXT: v_readlane_b32 s97, v20, 31 +; SI-NEXT: v_readlane_b32 s96, v20, 30 +; SI-NEXT: v_readlane_b32 s87, v20, 29 +; SI-NEXT: v_readlane_b32 s86, v20, 28 +; SI-NEXT: v_readlane_b32 s85, v20, 27 +; SI-NEXT: v_readlane_b32 s84, v20, 26 +; SI-NEXT: v_readlane_b32 s83, v20, 25 +; SI-NEXT: v_readlane_b32 s82, v20, 24 +; SI-NEXT: v_readlane_b32 s81, v20, 23 +; SI-NEXT: v_readlane_b32 s80, v20, 22 +; SI-NEXT: v_readlane_b32 s71, v20, 21 +; SI-NEXT: v_readlane_b32 s70, v20, 20 +; SI-NEXT: v_readlane_b32 s69, v20, 19 +; SI-NEXT: v_readlane_b32 s68, v20, 18 +; SI-NEXT: v_readlane_b32 s67, v20, 17 +; SI-NEXT: v_readlane_b32 s66, v20, 16 +; SI-NEXT: v_readlane_b32 s65, v20, 15 +; SI-NEXT: v_readlane_b32 s64, v20, 14 +; SI-NEXT: v_readlane_b32 s55, v20, 13 +; SI-NEXT: v_readlane_b32 s54, v20, 12 +; SI-NEXT: v_readlane_b32 s53, v20, 11 +; SI-NEXT: v_readlane_b32 s52, v20, 10 +; SI-NEXT: v_readlane_b32 s51, v20, 9 +; SI-NEXT: v_readlane_b32 s50, v20, 8 +; SI-NEXT: v_readlane_b32 s49, v20, 7 +; SI-NEXT: v_readlane_b32 s48, v20, 6 +; SI-NEXT: v_readlane_b32 s39, v20, 5 +; SI-NEXT: v_readlane_b32 s38, v20, 4 +; SI-NEXT: v_readlane_b32 s37, v20, 3 +; SI-NEXT: v_readlane_b32 s36, v20, 2 +; SI-NEXT: v_readlane_b32 s35, v20, 1 +; SI-NEXT: v_readlane_b32 s34, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -8630,38 +8649,39 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v20, s30, 0 -; VI-NEXT: v_writelane_b32 v20, s31, 1 -; VI-NEXT: v_writelane_b32 v20, s34, 2 -; VI-NEXT: v_writelane_b32 v20, s35, 3 -; VI-NEXT: v_writelane_b32 v20, s36, 4 -; VI-NEXT: v_writelane_b32 v20, s37, 5 -; VI-NEXT: v_writelane_b32 v20, s38, 6 -; VI-NEXT: v_writelane_b32 v20, s39, 7 -; VI-NEXT: v_writelane_b32 v20, s48, 8 -; VI-NEXT: v_writelane_b32 v20, s49, 9 -; VI-NEXT: v_writelane_b32 v20, s50, 10 -; VI-NEXT: v_writelane_b32 v20, s51, 11 -; VI-NEXT: v_writelane_b32 v20, s52, 12 -; VI-NEXT: v_writelane_b32 v20, s53, 13 -; VI-NEXT: v_writelane_b32 v20, s54, 14 -; VI-NEXT: v_writelane_b32 v20, s55, 15 -; VI-NEXT: v_writelane_b32 v20, s64, 16 -; VI-NEXT: v_writelane_b32 v20, s65, 17 -; VI-NEXT: v_writelane_b32 v20, s66, 18 -; VI-NEXT: v_writelane_b32 v20, s67, 19 -; VI-NEXT: v_writelane_b32 v20, s68, 20 -; VI-NEXT: v_writelane_b32 v20, s69, 21 -; VI-NEXT: v_writelane_b32 v20, s70, 22 -; VI-NEXT: v_writelane_b32 v20, s71, 23 -; VI-NEXT: v_writelane_b32 v20, s80, 24 -; VI-NEXT: v_writelane_b32 v20, s81, 25 -; VI-NEXT: v_writelane_b32 v20, s82, 26 -; VI-NEXT: v_writelane_b32 v20, s83, 27 -; VI-NEXT: v_writelane_b32 v20, s84, 28 -; VI-NEXT: v_writelane_b32 v20, s85, 29 +; VI-NEXT: v_writelane_b32 v20, s34, 0 +; VI-NEXT: v_writelane_b32 v20, s35, 1 +; VI-NEXT: v_writelane_b32 v20, s36, 2 +; VI-NEXT: v_writelane_b32 v20, s37, 3 +; VI-NEXT: v_writelane_b32 v20, s38, 4 +; VI-NEXT: v_writelane_b32 v20, s39, 5 +; VI-NEXT: v_writelane_b32 v20, s48, 6 +; VI-NEXT: v_writelane_b32 v20, s49, 7 +; VI-NEXT: v_writelane_b32 v20, s50, 8 +; VI-NEXT: v_writelane_b32 v20, s51, 9 +; VI-NEXT: v_writelane_b32 v20, s52, 10 +; VI-NEXT: v_writelane_b32 v20, s53, 11 +; VI-NEXT: v_writelane_b32 v20, s54, 12 +; VI-NEXT: v_writelane_b32 v20, s55, 13 +; VI-NEXT: v_writelane_b32 v20, s64, 14 +; VI-NEXT: v_writelane_b32 v20, s65, 15 +; VI-NEXT: v_writelane_b32 v20, s66, 16 +; VI-NEXT: v_writelane_b32 v20, s67, 17 +; VI-NEXT: v_writelane_b32 v20, s68, 18 +; VI-NEXT: v_writelane_b32 v20, s69, 19 +; VI-NEXT: v_writelane_b32 v20, s70, 20 +; VI-NEXT: v_writelane_b32 v20, s71, 21 +; VI-NEXT: v_writelane_b32 v20, s80, 22 +; VI-NEXT: v_writelane_b32 v20, s81, 23 +; VI-NEXT: v_writelane_b32 v20, s82, 24 +; VI-NEXT: v_writelane_b32 v20, s83, 25 +; VI-NEXT: v_writelane_b32 v20, s84, 26 +; VI-NEXT: v_writelane_b32 v20, s85, 27 +; VI-NEXT: v_writelane_b32 v20, s86, 28 +; VI-NEXT: v_writelane_b32 v20, s87, 29 +; VI-NEXT: v_writelane_b32 v20, s30, 30 +; VI-NEXT: v_writelane_b32 v20, s31, 31 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v20, s86, 30 ; VI-NEXT: v_readfirstlane_b32 s44, v1 ; VI-NEXT: v_readfirstlane_b32 s45, v2 ; VI-NEXT: v_readfirstlane_b32 s42, v3 @@ -8681,7 +8701,6 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s4, v17 ; VI-NEXT: s_and_b64 s[46:47], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v18 -; VI-NEXT: v_writelane_b32 v20, s87, 31 ; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB13_4 ; VI-NEXT: ; %bb.1: ; %cmp.false @@ -9470,43 +9489,43 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0 ; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_readlane_b32 s30, v20, 30 ; VI-NEXT: v_readlane_b32 s15, v21, 1 ; VI-NEXT: v_readlane_b32 s13, v21, 3 ; VI-NEXT: v_readlane_b32 s11, v21, 5 ; VI-NEXT: v_readlane_b32 s9, v21, 7 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; VI-NEXT: v_readlane_b32 s87, v20, 31 -; VI-NEXT: v_readlane_b32 s86, v20, 30 -; VI-NEXT: v_readlane_b32 s85, v20, 29 -; VI-NEXT: v_readlane_b32 s84, v20, 28 -; VI-NEXT: v_readlane_b32 s83, v20, 27 -; VI-NEXT: v_readlane_b32 s82, v20, 26 -; VI-NEXT: v_readlane_b32 s81, v20, 25 -; VI-NEXT: v_readlane_b32 s80, v20, 24 -; VI-NEXT: v_readlane_b32 s71, v20, 23 -; VI-NEXT: v_readlane_b32 s70, v20, 22 -; VI-NEXT: v_readlane_b32 s69, v20, 21 -; VI-NEXT: v_readlane_b32 s68, v20, 20 -; VI-NEXT: v_readlane_b32 s67, v20, 19 -; VI-NEXT: v_readlane_b32 s66, v20, 18 -; VI-NEXT: v_readlane_b32 s65, v20, 17 -; VI-NEXT: v_readlane_b32 s64, v20, 16 -; VI-NEXT: v_readlane_b32 s55, v20, 15 -; VI-NEXT: v_readlane_b32 s54, v20, 14 -; VI-NEXT: v_readlane_b32 s53, v20, 13 -; VI-NEXT: v_readlane_b32 s52, v20, 12 -; VI-NEXT: v_readlane_b32 s51, v20, 11 -; VI-NEXT: v_readlane_b32 s50, v20, 10 -; VI-NEXT: v_readlane_b32 s49, v20, 9 -; VI-NEXT: v_readlane_b32 s48, v20, 8 -; VI-NEXT: v_readlane_b32 s39, v20, 7 -; VI-NEXT: v_readlane_b32 s38, v20, 6 -; VI-NEXT: v_readlane_b32 s37, v20, 5 -; VI-NEXT: v_readlane_b32 s36, v20, 4 -; VI-NEXT: v_readlane_b32 s35, v20, 3 -; VI-NEXT: v_readlane_b32 s34, v20, 2 -; VI-NEXT: v_readlane_b32 s31, v20, 1 -; VI-NEXT: v_readlane_b32 s30, v20, 0 +; VI-NEXT: v_readlane_b32 s31, v20, 31 +; VI-NEXT: v_readlane_b32 s87, v20, 29 +; VI-NEXT: v_readlane_b32 s86, v20, 28 +; VI-NEXT: v_readlane_b32 s85, v20, 27 +; VI-NEXT: v_readlane_b32 s84, v20, 26 +; VI-NEXT: v_readlane_b32 s83, v20, 25 +; VI-NEXT: v_readlane_b32 s82, v20, 24 +; VI-NEXT: v_readlane_b32 s81, v20, 23 +; VI-NEXT: v_readlane_b32 s80, v20, 22 +; VI-NEXT: v_readlane_b32 s71, v20, 21 +; VI-NEXT: v_readlane_b32 s70, v20, 20 +; VI-NEXT: v_readlane_b32 s69, v20, 19 +; VI-NEXT: v_readlane_b32 s68, v20, 18 +; VI-NEXT: v_readlane_b32 s67, v20, 17 +; VI-NEXT: v_readlane_b32 s66, v20, 16 +; VI-NEXT: v_readlane_b32 s65, v20, 15 +; VI-NEXT: v_readlane_b32 s64, v20, 14 +; VI-NEXT: v_readlane_b32 s55, v20, 13 +; VI-NEXT: v_readlane_b32 s54, v20, 12 +; VI-NEXT: v_readlane_b32 s53, v20, 11 +; VI-NEXT: v_readlane_b32 s52, v20, 10 +; VI-NEXT: v_readlane_b32 s51, v20, 9 +; VI-NEXT: v_readlane_b32 s50, v20, 8 +; VI-NEXT: v_readlane_b32 s49, v20, 7 +; VI-NEXT: v_readlane_b32 s48, v20, 6 +; VI-NEXT: v_readlane_b32 s39, v20, 5 +; VI-NEXT: v_readlane_b32 s38, v20, 4 +; VI-NEXT: v_readlane_b32 s37, v20, 3 +; VI-NEXT: v_readlane_b32 s36, v20, 2 +; VI-NEXT: v_readlane_b32 s35, v20, 1 +; VI-NEXT: v_readlane_b32 s34, v20, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -9679,42 +9698,43 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v20, s30, 0 -; GFX9-NEXT: v_writelane_b32 v20, s31, 1 -; GFX9-NEXT: v_writelane_b32 v20, s34, 2 -; GFX9-NEXT: v_writelane_b32 v20, s35, 3 -; GFX9-NEXT: v_writelane_b32 v20, s36, 4 -; GFX9-NEXT: v_writelane_b32 v20, s37, 5 -; GFX9-NEXT: v_writelane_b32 v20, s38, 6 -; GFX9-NEXT: v_writelane_b32 v20, s39, 7 -; GFX9-NEXT: v_writelane_b32 v20, s48, 8 -; GFX9-NEXT: v_writelane_b32 v20, s49, 9 -; GFX9-NEXT: v_writelane_b32 v20, s50, 10 -; GFX9-NEXT: v_writelane_b32 v20, s51, 11 -; GFX9-NEXT: v_writelane_b32 v20, s52, 12 -; GFX9-NEXT: v_writelane_b32 v20, s53, 13 -; GFX9-NEXT: v_writelane_b32 v20, s54, 14 -; GFX9-NEXT: v_writelane_b32 v20, s55, 15 -; GFX9-NEXT: v_writelane_b32 v20, s64, 16 -; GFX9-NEXT: v_writelane_b32 v20, s65, 17 -; GFX9-NEXT: v_writelane_b32 v20, s66, 18 -; GFX9-NEXT: v_writelane_b32 v20, s67, 19 -; GFX9-NEXT: v_writelane_b32 v20, s68, 20 -; GFX9-NEXT: v_writelane_b32 v20, s69, 21 -; GFX9-NEXT: v_writelane_b32 v20, s70, 22 -; GFX9-NEXT: v_writelane_b32 v20, s71, 23 -; GFX9-NEXT: v_writelane_b32 v20, s80, 24 -; GFX9-NEXT: v_writelane_b32 v20, s81, 25 -; GFX9-NEXT: v_writelane_b32 v20, s82, 26 -; GFX9-NEXT: v_writelane_b32 v20, s83, 27 -; GFX9-NEXT: v_writelane_b32 v20, s84, 28 -; GFX9-NEXT: v_writelane_b32 v20, s85, 29 -; GFX9-NEXT: v_writelane_b32 v20, s86, 30 -; GFX9-NEXT: v_writelane_b32 v20, s87, 31 -; GFX9-NEXT: v_writelane_b32 v20, s96, 32 -; GFX9-NEXT: v_writelane_b32 v20, s97, 33 +; GFX9-NEXT: v_writelane_b32 v20, s34, 0 +; GFX9-NEXT: v_writelane_b32 v20, s35, 1 +; GFX9-NEXT: v_writelane_b32 v20, s36, 2 +; GFX9-NEXT: v_writelane_b32 v20, s37, 3 +; GFX9-NEXT: v_writelane_b32 v20, s38, 4 +; GFX9-NEXT: v_writelane_b32 v20, s39, 5 +; GFX9-NEXT: v_writelane_b32 v20, s48, 6 +; GFX9-NEXT: v_writelane_b32 v20, s49, 7 +; GFX9-NEXT: v_writelane_b32 v20, s50, 8 +; GFX9-NEXT: v_writelane_b32 v20, s51, 9 +; GFX9-NEXT: v_writelane_b32 v20, s52, 10 +; GFX9-NEXT: v_writelane_b32 v20, s53, 11 +; GFX9-NEXT: v_writelane_b32 v20, s54, 12 +; GFX9-NEXT: v_writelane_b32 v20, s55, 13 +; GFX9-NEXT: v_writelane_b32 v20, s64, 14 +; GFX9-NEXT: v_writelane_b32 v20, s65, 15 +; GFX9-NEXT: v_writelane_b32 v20, s66, 16 +; GFX9-NEXT: v_writelane_b32 v20, s67, 17 +; GFX9-NEXT: v_writelane_b32 v20, s68, 18 +; GFX9-NEXT: v_writelane_b32 v20, s69, 19 +; GFX9-NEXT: v_writelane_b32 v20, s70, 20 +; GFX9-NEXT: v_writelane_b32 v20, s71, 21 +; GFX9-NEXT: v_writelane_b32 v20, s80, 22 +; GFX9-NEXT: v_writelane_b32 v20, s81, 23 +; GFX9-NEXT: v_writelane_b32 v20, s82, 24 +; GFX9-NEXT: v_writelane_b32 v20, s83, 25 +; GFX9-NEXT: v_writelane_b32 v20, s84, 26 +; GFX9-NEXT: v_writelane_b32 v20, s85, 27 +; GFX9-NEXT: v_writelane_b32 v20, s86, 28 +; GFX9-NEXT: v_writelane_b32 v20, s87, 29 +; GFX9-NEXT: v_writelane_b32 v20, s96, 30 +; GFX9-NEXT: v_writelane_b32 v20, s97, 31 +; GFX9-NEXT: v_writelane_b32 v20, s98, 32 +; GFX9-NEXT: v_writelane_b32 v20, s99, 33 +; GFX9-NEXT: v_writelane_b32 v20, s30, 34 +; GFX9-NEXT: v_writelane_b32 v20, s31, 35 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; GFX9-NEXT: v_writelane_b32 v20, s98, 34 ; GFX9-NEXT: v_readfirstlane_b32 s44, v1 ; GFX9-NEXT: v_readfirstlane_b32 s45, v2 ; GFX9-NEXT: v_readfirstlane_b32 s42, v3 @@ -9734,7 +9754,6 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: v_readfirstlane_b32 s4, v17 ; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v18 -; GFX9-NEXT: v_writelane_b32 v20, s99, 35 ; GFX9-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB13_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false @@ -10468,44 +10487,44 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s4, s4, s5 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_readlane_b32 s30, v20, 34 ; GFX9-NEXT: v_readlane_b32 s9, v21, 1 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124 -; GFX9-NEXT: v_readlane_b32 s99, v20, 35 -; GFX9-NEXT: v_readlane_b32 s98, v20, 34 -; GFX9-NEXT: v_readlane_b32 s97, v20, 33 -; GFX9-NEXT: v_readlane_b32 s96, v20, 32 -; GFX9-NEXT: v_readlane_b32 s87, v20, 31 -; GFX9-NEXT: v_readlane_b32 s86, v20, 30 -; GFX9-NEXT: v_readlane_b32 s85, v20, 29 -; GFX9-NEXT: v_readlane_b32 s84, v20, 28 -; GFX9-NEXT: v_readlane_b32 s83, v20, 27 -; GFX9-NEXT: v_readlane_b32 s82, v20, 26 -; GFX9-NEXT: v_readlane_b32 s81, v20, 25 -; GFX9-NEXT: v_readlane_b32 s80, v20, 24 -; GFX9-NEXT: v_readlane_b32 s71, v20, 23 -; GFX9-NEXT: v_readlane_b32 s70, v20, 22 -; GFX9-NEXT: v_readlane_b32 s69, v20, 21 -; GFX9-NEXT: v_readlane_b32 s68, v20, 20 -; GFX9-NEXT: v_readlane_b32 s67, v20, 19 -; GFX9-NEXT: v_readlane_b32 s66, v20, 18 -; GFX9-NEXT: v_readlane_b32 s65, v20, 17 -; GFX9-NEXT: v_readlane_b32 s64, v20, 16 -; GFX9-NEXT: v_readlane_b32 s55, v20, 15 -; GFX9-NEXT: v_readlane_b32 s54, v20, 14 -; GFX9-NEXT: v_readlane_b32 s53, v20, 13 -; GFX9-NEXT: v_readlane_b32 s52, v20, 12 -; GFX9-NEXT: v_readlane_b32 s51, v20, 11 -; GFX9-NEXT: v_readlane_b32 s50, v20, 10 -; GFX9-NEXT: v_readlane_b32 s49, v20, 9 -; GFX9-NEXT: v_readlane_b32 s48, v20, 8 -; GFX9-NEXT: v_readlane_b32 s39, v20, 7 -; GFX9-NEXT: v_readlane_b32 s38, v20, 6 -; GFX9-NEXT: v_readlane_b32 s37, v20, 5 -; GFX9-NEXT: v_readlane_b32 s36, v20, 4 -; GFX9-NEXT: v_readlane_b32 s35, v20, 3 -; GFX9-NEXT: v_readlane_b32 s34, v20, 2 -; GFX9-NEXT: v_readlane_b32 s31, v20, 1 -; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: v_readlane_b32 s31, v20, 35 +; GFX9-NEXT: v_readlane_b32 s99, v20, 33 +; GFX9-NEXT: v_readlane_b32 s98, v20, 32 +; GFX9-NEXT: v_readlane_b32 s97, v20, 31 +; GFX9-NEXT: v_readlane_b32 s96, v20, 30 +; GFX9-NEXT: v_readlane_b32 s87, v20, 29 +; GFX9-NEXT: v_readlane_b32 s86, v20, 28 +; GFX9-NEXT: v_readlane_b32 s85, v20, 27 +; GFX9-NEXT: v_readlane_b32 s84, v20, 26 +; GFX9-NEXT: v_readlane_b32 s83, v20, 25 +; GFX9-NEXT: v_readlane_b32 s82, v20, 24 +; GFX9-NEXT: v_readlane_b32 s81, v20, 23 +; GFX9-NEXT: v_readlane_b32 s80, v20, 22 +; GFX9-NEXT: v_readlane_b32 s71, v20, 21 +; GFX9-NEXT: v_readlane_b32 s70, v20, 20 +; GFX9-NEXT: v_readlane_b32 s69, v20, 19 +; GFX9-NEXT: v_readlane_b32 s68, v20, 18 +; GFX9-NEXT: v_readlane_b32 s67, v20, 17 +; GFX9-NEXT: v_readlane_b32 s66, v20, 16 +; GFX9-NEXT: v_readlane_b32 s65, v20, 15 +; GFX9-NEXT: v_readlane_b32 s64, v20, 14 +; GFX9-NEXT: v_readlane_b32 s55, v20, 13 +; GFX9-NEXT: v_readlane_b32 s54, v20, 12 +; GFX9-NEXT: v_readlane_b32 s53, v20, 11 +; GFX9-NEXT: v_readlane_b32 s52, v20, 10 +; GFX9-NEXT: v_readlane_b32 s51, v20, 9 +; GFX9-NEXT: v_readlane_b32 s50, v20, 8 +; GFX9-NEXT: v_readlane_b32 s49, v20, 7 +; GFX9-NEXT: v_readlane_b32 s48, v20, 6 +; GFX9-NEXT: v_readlane_b32 s39, v20, 5 +; GFX9-NEXT: v_readlane_b32 s38, v20, 4 +; GFX9-NEXT: v_readlane_b32 s37, v20, 3 +; GFX9-NEXT: v_readlane_b32 s36, v20, 2 +; GFX9-NEXT: v_readlane_b32 s35, v20, 1 +; GFX9-NEXT: v_readlane_b32 s34, v20, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -10668,70 +10687,73 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v16, s32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v17, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v18, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:12 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v16, s30, 0 -; GFX11-NEXT: v_writelane_b32 v17, s96, 0 +; GFX11-NEXT: v_writelane_b32 v16, s34, 0 +; GFX11-NEXT: v_writelane_b32 v16, s35, 1 +; GFX11-NEXT: v_writelane_b32 v16, s36, 2 +; GFX11-NEXT: v_writelane_b32 v16, s37, 3 +; GFX11-NEXT: v_writelane_b32 v16, s38, 4 +; GFX11-NEXT: v_writelane_b32 v16, s39, 5 +; GFX11-NEXT: v_writelane_b32 v16, s48, 6 +; GFX11-NEXT: v_writelane_b32 v16, s49, 7 +; GFX11-NEXT: v_writelane_b32 v16, s50, 8 +; GFX11-NEXT: v_writelane_b32 v16, s51, 9 +; GFX11-NEXT: v_writelane_b32 v16, s52, 10 +; GFX11-NEXT: v_writelane_b32 v16, s53, 11 +; GFX11-NEXT: v_writelane_b32 v16, s54, 12 +; GFX11-NEXT: v_writelane_b32 v16, s55, 13 +; GFX11-NEXT: v_writelane_b32 v16, s64, 14 +; GFX11-NEXT: v_writelane_b32 v16, s65, 15 +; GFX11-NEXT: v_writelane_b32 v16, s66, 16 +; GFX11-NEXT: v_writelane_b32 v16, s67, 17 +; GFX11-NEXT: v_writelane_b32 v16, s68, 18 +; GFX11-NEXT: v_writelane_b32 v16, s69, 19 +; GFX11-NEXT: v_writelane_b32 v16, s70, 20 +; GFX11-NEXT: v_writelane_b32 v16, s71, 21 +; GFX11-NEXT: v_writelane_b32 v16, s80, 22 +; GFX11-NEXT: v_writelane_b32 v16, s81, 23 +; GFX11-NEXT: v_writelane_b32 v16, s82, 24 +; GFX11-NEXT: v_writelane_b32 v16, s83, 25 +; GFX11-NEXT: v_writelane_b32 v16, s84, 26 +; GFX11-NEXT: v_writelane_b32 v16, s85, 27 +; GFX11-NEXT: v_writelane_b32 v16, s86, 28 +; GFX11-NEXT: v_writelane_b32 v16, s87, 29 +; GFX11-NEXT: v_writelane_b32 v16, s96, 30 +; GFX11-NEXT: v_writelane_b32 v16, s97, 31 +; GFX11-NEXT: v_writelane_b32 v17, s98, 0 +; GFX11-NEXT: v_writelane_b32 v17, s99, 1 +; GFX11-NEXT: v_writelane_b32 v17, s100, 2 +; GFX11-NEXT: v_writelane_b32 v17, s101, 3 +; GFX11-NEXT: v_writelane_b32 v17, s102, 4 +; GFX11-NEXT: v_writelane_b32 v17, s103, 5 +; GFX11-NEXT: v_writelane_b32 v17, s104, 6 +; GFX11-NEXT: v_writelane_b32 v17, s30, 7 +; GFX11-NEXT: v_writelane_b32 v17, s31, 8 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 ; GFX11-NEXT: v_readfirstlane_b32 s40, v1 ; GFX11-NEXT: v_readfirstlane_b32 s41, v2 -; GFX11-NEXT: v_writelane_b32 v16, s31, 1 -; GFX11-NEXT: v_writelane_b32 v17, s97, 1 ; GFX11-NEXT: v_readfirstlane_b32 s14, v3 ; GFX11-NEXT: v_readfirstlane_b32 s15, v4 ; GFX11-NEXT: v_readfirstlane_b32 s12, v5 -; GFX11-NEXT: v_writelane_b32 v16, s34, 2 -; GFX11-NEXT: v_writelane_b32 v17, s98, 2 ; GFX11-NEXT: v_readfirstlane_b32 s13, v6 ; GFX11-NEXT: v_readfirstlane_b32 s10, v7 ; GFX11-NEXT: v_readfirstlane_b32 s11, v8 -; GFX11-NEXT: v_writelane_b32 v16, s35, 3 -; GFX11-NEXT: v_writelane_b32 v17, s99, 3 ; GFX11-NEXT: v_readfirstlane_b32 s8, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v10 ; GFX11-NEXT: v_readfirstlane_b32 s6, v11 -; GFX11-NEXT: v_writelane_b32 v16, s36, 4 -; GFX11-NEXT: v_writelane_b32 v17, s100, 4 ; GFX11-NEXT: v_readfirstlane_b32 s7, v12 ; GFX11-NEXT: v_readfirstlane_b32 s4, v13 ; GFX11-NEXT: v_readfirstlane_b32 s5, v14 -; GFX11-NEXT: v_writelane_b32 v16, s37, 5 -; GFX11-NEXT: v_writelane_b32 v17, s101, 5 ; GFX11-NEXT: s_mov_b32 s101, 0 ; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane ; GFX11-NEXT: ; implicit-def: $vgpr18 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v16, s38, 6 -; GFX11-NEXT: v_writelane_b32 v17, s102, 6 -; GFX11-NEXT: v_writelane_b32 v16, s39, 7 -; GFX11-NEXT: v_writelane_b32 v17, s103, 7 -; GFX11-NEXT: v_writelane_b32 v16, s48, 8 -; GFX11-NEXT: v_writelane_b32 v17, s104, 8 -; GFX11-NEXT: v_writelane_b32 v16, s49, 9 -; GFX11-NEXT: v_writelane_b32 v16, s50, 10 -; GFX11-NEXT: v_writelane_b32 v16, s51, 11 -; GFX11-NEXT: v_writelane_b32 v16, s52, 12 -; GFX11-NEXT: v_writelane_b32 v16, s53, 13 -; GFX11-NEXT: v_writelane_b32 v16, s54, 14 -; GFX11-NEXT: v_writelane_b32 v16, s55, 15 -; GFX11-NEXT: v_writelane_b32 v16, s64, 16 -; GFX11-NEXT: v_writelane_b32 v16, s65, 17 -; GFX11-NEXT: v_writelane_b32 v16, s66, 18 -; GFX11-NEXT: v_writelane_b32 v16, s67, 19 -; GFX11-NEXT: v_writelane_b32 v16, s68, 20 -; GFX11-NEXT: v_writelane_b32 v16, s69, 21 -; GFX11-NEXT: v_writelane_b32 v16, s70, 22 -; GFX11-NEXT: v_writelane_b32 v16, s71, 23 -; GFX11-NEXT: v_writelane_b32 v16, s80, 24 -; GFX11-NEXT: v_writelane_b32 v16, s81, 25 -; GFX11-NEXT: v_writelane_b32 v16, s82, 26 -; GFX11-NEXT: v_writelane_b32 v16, s83, 27 -; GFX11-NEXT: v_writelane_b32 v16, s84, 28 -; GFX11-NEXT: v_writelane_b32 v16, s85, 29 -; GFX11-NEXT: v_writelane_b32 v16, s86, 30 -; GFX11-NEXT: v_writelane_b32 v16, s87, 31 ; GFX11-NEXT: s_cbranch_scc0 .LBB13_2 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s43, s25, 8 @@ -11258,9 +11280,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: s_and_b32 s1, s1, 0xffff ; GFX11-NEXT: v_readlane_b32 s17, v19, 29 ; GFX11-NEXT: s_and_b32 s16, s16, 0xff -; GFX11-NEXT: v_readlane_b32 s100, v17, 4 +; GFX11-NEXT: v_readlane_b32 s30, v17, 7 ; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: v_readlane_b32 s99, v17, 3 +; GFX11-NEXT: v_readlane_b32 s31, v17, 8 ; GFX11-NEXT: s_or_b32 s2, s2, s3 ; GFX11-NEXT: s_and_b32 s3, s18, 0xff ; GFX11-NEXT: s_lshl_b32 s2, s2, 16 @@ -11294,7 +11316,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: s_or_b32 s16, s16, s17 ; GFX11-NEXT: v_readlane_b32 s17, v19, 21 ; GFX11-NEXT: s_lshl_b32 s16, s16, 16 -; GFX11-NEXT: v_readlane_b32 s98, v17, 2 +; GFX11-NEXT: v_readlane_b32 s100, v17, 2 ; GFX11-NEXT: s_or_b32 s3, s3, s16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 @@ -11314,12 +11336,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: s_or_b32 s0, s0, s1 ; GFX11-NEXT: s_and_b32 s1, s21, 0xff ; GFX11-NEXT: s_lshl_b32 s2, s2, 8 -; GFX11-NEXT: v_readlane_b32 s86, v16, 30 +; GFX11-NEXT: v_readlane_b32 s99, v17, 1 ; GFX11-NEXT: s_or_b32 s1, s1, s2 ; GFX11-NEXT: v_readlane_b32 s2, v19, 25 ; GFX11-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-NEXT: v_readlane_b32 s31, v16, 1 -; GFX11-NEXT: v_readlane_b32 s30, v16, 0 +; GFX11-NEXT: v_readlane_b32 s98, v17, 0 +; GFX11-NEXT: v_readlane_b32 s86, v16, 28 ; GFX11-NEXT: s_and_b32 s2, s2, 0xff ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_or_b32 s2, s2, s3 @@ -11356,9 +11378,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: s_lshl_b32 s3, s88, 8 ; GFX11-NEXT: s_and_b32 s16, s69, 0xff ; GFX11-NEXT: s_and_b32 s18, s72, 0xff -; GFX11-NEXT: v_readlane_b32 s97, v17, 1 +; GFX11-NEXT: v_readlane_b32 s97, v16, 31 ; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: v_readlane_b32 s69, v16, 21 +; GFX11-NEXT: v_readlane_b32 s69, v16, 19 ; GFX11-NEXT: s_or_b32 s1, s2, s3 ; GFX11-NEXT: v_readlane_b32 s3, v19, 16 ; GFX11-NEXT: s_and_b32 s2, s25, 0xff @@ -11565,39 +11587,39 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:80 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:96 ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:112 -; GFX11-NEXT: v_readlane_b32 s104, v17, 8 -; GFX11-NEXT: v_readlane_b32 s103, v17, 7 -; GFX11-NEXT: v_readlane_b32 s102, v17, 6 -; GFX11-NEXT: v_readlane_b32 s101, v17, 5 -; GFX11-NEXT: v_readlane_b32 s96, v17, 0 -; GFX11-NEXT: v_readlane_b32 s87, v16, 31 -; GFX11-NEXT: v_readlane_b32 s85, v16, 29 -; GFX11-NEXT: v_readlane_b32 s84, v16, 28 -; GFX11-NEXT: v_readlane_b32 s83, v16, 27 -; GFX11-NEXT: v_readlane_b32 s82, v16, 26 -; GFX11-NEXT: v_readlane_b32 s81, v16, 25 -; GFX11-NEXT: v_readlane_b32 s80, v16, 24 -; GFX11-NEXT: v_readlane_b32 s71, v16, 23 -; GFX11-NEXT: v_readlane_b32 s70, v16, 22 -; GFX11-NEXT: v_readlane_b32 s68, v16, 20 -; GFX11-NEXT: v_readlane_b32 s67, v16, 19 -; GFX11-NEXT: v_readlane_b32 s66, v16, 18 -; GFX11-NEXT: v_readlane_b32 s65, v16, 17 -; GFX11-NEXT: v_readlane_b32 s64, v16, 16 -; GFX11-NEXT: v_readlane_b32 s55, v16, 15 -; GFX11-NEXT: v_readlane_b32 s54, v16, 14 -; GFX11-NEXT: v_readlane_b32 s53, v16, 13 -; GFX11-NEXT: v_readlane_b32 s52, v16, 12 -; GFX11-NEXT: v_readlane_b32 s51, v16, 11 -; GFX11-NEXT: v_readlane_b32 s50, v16, 10 -; GFX11-NEXT: v_readlane_b32 s49, v16, 9 -; GFX11-NEXT: v_readlane_b32 s48, v16, 8 -; GFX11-NEXT: v_readlane_b32 s39, v16, 7 -; GFX11-NEXT: v_readlane_b32 s38, v16, 6 -; GFX11-NEXT: v_readlane_b32 s37, v16, 5 -; GFX11-NEXT: v_readlane_b32 s36, v16, 4 -; GFX11-NEXT: v_readlane_b32 s35, v16, 3 -; GFX11-NEXT: v_readlane_b32 s34, v16, 2 +; GFX11-NEXT: v_readlane_b32 s104, v17, 6 +; GFX11-NEXT: v_readlane_b32 s103, v17, 5 +; GFX11-NEXT: v_readlane_b32 s102, v17, 4 +; GFX11-NEXT: v_readlane_b32 s101, v17, 3 +; GFX11-NEXT: v_readlane_b32 s96, v16, 30 +; GFX11-NEXT: v_readlane_b32 s87, v16, 29 +; GFX11-NEXT: v_readlane_b32 s85, v16, 27 +; GFX11-NEXT: v_readlane_b32 s84, v16, 26 +; GFX11-NEXT: v_readlane_b32 s83, v16, 25 +; GFX11-NEXT: v_readlane_b32 s82, v16, 24 +; GFX11-NEXT: v_readlane_b32 s81, v16, 23 +; GFX11-NEXT: v_readlane_b32 s80, v16, 22 +; GFX11-NEXT: v_readlane_b32 s71, v16, 21 +; GFX11-NEXT: v_readlane_b32 s70, v16, 20 +; GFX11-NEXT: v_readlane_b32 s68, v16, 18 +; GFX11-NEXT: v_readlane_b32 s67, v16, 17 +; GFX11-NEXT: v_readlane_b32 s66, v16, 16 +; GFX11-NEXT: v_readlane_b32 s65, v16, 15 +; GFX11-NEXT: v_readlane_b32 s64, v16, 14 +; GFX11-NEXT: v_readlane_b32 s55, v16, 13 +; GFX11-NEXT: v_readlane_b32 s54, v16, 12 +; GFX11-NEXT: v_readlane_b32 s53, v16, 11 +; GFX11-NEXT: v_readlane_b32 s52, v16, 10 +; GFX11-NEXT: v_readlane_b32 s51, v16, 9 +; GFX11-NEXT: v_readlane_b32 s50, v16, 8 +; GFX11-NEXT: v_readlane_b32 s49, v16, 7 +; GFX11-NEXT: v_readlane_b32 s48, v16, 6 +; GFX11-NEXT: v_readlane_b32 s39, v16, 5 +; GFX11-NEXT: v_readlane_b32 s38, v16, 4 +; GFX11-NEXT: v_readlane_b32 s37, v16, 3 +; GFX11-NEXT: v_readlane_b32 s36, v16, 2 +; GFX11-NEXT: v_readlane_b32 s35, v16, 1 +; GFX11-NEXT: v_readlane_b32 s34, v16, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_load_b32 v16, off, s32 @@ -16364,56 +16386,105 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:592 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:588 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:584 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:580 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:576 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:572 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:568 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:564 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:560 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:556 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:552 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:548 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:544 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:540 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:536 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:532 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:528 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:524 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:520 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:516 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:512 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:508 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:504 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:500 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:496 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:492 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:488 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:484 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:480 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:468 ; GFX11-FAKE16-NEXT: s_clause 0x12 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:456 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:392 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -20685,45 +20756,83 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:476 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:472 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:468 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:464 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:460 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:456 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:452 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:448 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:444 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:440 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:436 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:432 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:428 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:424 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:420 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:416 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:412 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:408 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:404 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:400 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:396 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:392 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:388 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:384 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:380 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:376 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:372 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:368 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:364 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:360 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:356 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:352 ; GFX11-TRUE16-NEXT: s_clause 0x7 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:348 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:344 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:340 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:336 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:332 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:328 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:324 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:320 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -21626,45 +21735,83 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:468 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:456 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:392 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:388 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:384 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:380 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:376 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:372 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:368 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:364 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:360 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:356 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:352 ; GFX11-FAKE16-NEXT: s_clause 0x7 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:348 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:344 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:340 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:336 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:332 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:328 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:324 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:320 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -23488,43 +23635,43 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a ; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_writelane_b32 v20, s69, 21 -; SI-NEXT: v_writelane_b32 v20, s70, 22 -; SI-NEXT: v_writelane_b32 v20, s71, 23 -; SI-NEXT: v_writelane_b32 v20, s80, 24 -; SI-NEXT: v_writelane_b32 v20, s81, 25 -; SI-NEXT: v_writelane_b32 v20, s82, 26 -; SI-NEXT: v_writelane_b32 v20, s83, 27 -; SI-NEXT: v_writelane_b32 v20, s84, 28 -; SI-NEXT: v_writelane_b32 v20, s85, 29 -; SI-NEXT: v_writelane_b32 v20, s86, 30 -; SI-NEXT: v_writelane_b32 v20, s87, 31 -; SI-NEXT: v_writelane_b32 v20, s96, 32 -; SI-NEXT: v_writelane_b32 v20, s97, 33 -; SI-NEXT: v_writelane_b32 v20, s98, 34 +; SI-NEXT: v_writelane_b32 v20, s34, 0 +; SI-NEXT: v_writelane_b32 v20, s35, 1 +; SI-NEXT: v_writelane_b32 v20, s36, 2 +; SI-NEXT: v_writelane_b32 v20, s37, 3 +; SI-NEXT: v_writelane_b32 v20, s38, 4 +; SI-NEXT: v_writelane_b32 v20, s39, 5 +; SI-NEXT: v_writelane_b32 v20, s48, 6 +; SI-NEXT: v_writelane_b32 v20, s49, 7 +; SI-NEXT: v_writelane_b32 v20, s50, 8 +; SI-NEXT: v_writelane_b32 v20, s51, 9 +; SI-NEXT: v_writelane_b32 v20, s52, 10 +; SI-NEXT: v_writelane_b32 v20, s53, 11 +; SI-NEXT: v_writelane_b32 v20, s54, 12 +; SI-NEXT: v_writelane_b32 v20, s55, 13 +; SI-NEXT: v_writelane_b32 v20, s64, 14 +; SI-NEXT: v_writelane_b32 v20, s65, 15 +; SI-NEXT: v_writelane_b32 v20, s66, 16 +; SI-NEXT: v_writelane_b32 v20, s67, 17 +; SI-NEXT: v_writelane_b32 v20, s68, 18 +; SI-NEXT: v_writelane_b32 v20, s69, 19 +; SI-NEXT: v_writelane_b32 v20, s70, 20 +; SI-NEXT: v_writelane_b32 v20, s71, 21 +; SI-NEXT: v_writelane_b32 v20, s80, 22 +; SI-NEXT: v_writelane_b32 v20, s81, 23 +; SI-NEXT: v_writelane_b32 v20, s82, 24 +; SI-NEXT: v_writelane_b32 v20, s83, 25 +; SI-NEXT: v_writelane_b32 v20, s84, 26 +; SI-NEXT: v_writelane_b32 v20, s85, 27 +; SI-NEXT: v_writelane_b32 v20, s86, 28 +; SI-NEXT: v_writelane_b32 v20, s87, 29 +; SI-NEXT: v_writelane_b32 v20, s96, 30 +; SI-NEXT: v_writelane_b32 v20, s97, 31 +; SI-NEXT: v_writelane_b32 v20, s98, 32 +; SI-NEXT: v_writelane_b32 v20, s99, 33 +; SI-NEXT: v_writelane_b32 v20, s30, 34 +; SI-NEXT: v_writelane_b32 v20, s31, 35 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s99, 35 ; SI-NEXT: v_readfirstlane_b32 s70, v1 ; SI-NEXT: v_readfirstlane_b32 s71, v2 ; SI-NEXT: v_readfirstlane_b32 s80, v3 @@ -24044,43 +24191,43 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a ; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 ; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 +; SI-NEXT: v_readlane_b32 s30, v20, 34 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v20, 35 -; SI-NEXT: v_readlane_b32 s98, v20, 34 -; SI-NEXT: v_readlane_b32 s97, v20, 33 -; SI-NEXT: v_readlane_b32 s96, v20, 32 -; SI-NEXT: v_readlane_b32 s87, v20, 31 -; SI-NEXT: v_readlane_b32 s86, v20, 30 -; SI-NEXT: v_readlane_b32 s85, v20, 29 -; SI-NEXT: v_readlane_b32 s84, v20, 28 -; SI-NEXT: v_readlane_b32 s83, v20, 27 -; SI-NEXT: v_readlane_b32 s82, v20, 26 -; SI-NEXT: v_readlane_b32 s81, v20, 25 -; SI-NEXT: v_readlane_b32 s80, v20, 24 -; SI-NEXT: v_readlane_b32 s71, v20, 23 -; SI-NEXT: v_readlane_b32 s70, v20, 22 -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s31, v20, 35 +; SI-NEXT: v_readlane_b32 s99, v20, 33 +; SI-NEXT: v_readlane_b32 s98, v20, 32 +; SI-NEXT: v_readlane_b32 s97, v20, 31 +; SI-NEXT: v_readlane_b32 s96, v20, 30 +; SI-NEXT: v_readlane_b32 s87, v20, 29 +; SI-NEXT: v_readlane_b32 s86, v20, 28 +; SI-NEXT: v_readlane_b32 s85, v20, 27 +; SI-NEXT: v_readlane_b32 s84, v20, 26 +; SI-NEXT: v_readlane_b32 s83, v20, 25 +; SI-NEXT: v_readlane_b32 s82, v20, 24 +; SI-NEXT: v_readlane_b32 s81, v20, 23 +; SI-NEXT: v_readlane_b32 s80, v20, 22 +; SI-NEXT: v_readlane_b32 s71, v20, 21 +; SI-NEXT: v_readlane_b32 s70, v20, 20 +; SI-NEXT: v_readlane_b32 s69, v20, 19 +; SI-NEXT: v_readlane_b32 s68, v20, 18 +; SI-NEXT: v_readlane_b32 s67, v20, 17 +; SI-NEXT: v_readlane_b32 s66, v20, 16 +; SI-NEXT: v_readlane_b32 s65, v20, 15 +; SI-NEXT: v_readlane_b32 s64, v20, 14 +; SI-NEXT: v_readlane_b32 s55, v20, 13 +; SI-NEXT: v_readlane_b32 s54, v20, 12 +; SI-NEXT: v_readlane_b32 s53, v20, 11 +; SI-NEXT: v_readlane_b32 s52, v20, 10 +; SI-NEXT: v_readlane_b32 s51, v20, 9 +; SI-NEXT: v_readlane_b32 s50, v20, 8 +; SI-NEXT: v_readlane_b32 s49, v20, 7 +; SI-NEXT: v_readlane_b32 s48, v20, 6 +; SI-NEXT: v_readlane_b32 s39, v20, 5 +; SI-NEXT: v_readlane_b32 s38, v20, 4 +; SI-NEXT: v_readlane_b32 s37, v20, 3 +; SI-NEXT: v_readlane_b32 s36, v20, 2 +; SI-NEXT: v_readlane_b32 s35, v20, 1 +; SI-NEXT: v_readlane_b32 s34, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -26131,20 +26278,35 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4 @@ -29180,81 +29342,149 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v32i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28 ; GFX11-TRUE16-NEXT: s_clause 0x6 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8 @@ -30154,83 +30384,153 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a ; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v32i32_scalar: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164 ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36 ; GFX11-FAKE16-NEXT: s_clause 0x8 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7 @@ -32001,12 +32301,26 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v63, s30, 0 -; SI-NEXT: v_writelane_b32 v63, s31, 1 -; SI-NEXT: v_writelane_b32 v63, s34, 2 +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_writelane_b32 v63, s34, 0 +; SI-NEXT: v_writelane_b32 v63, s35, 1 +; SI-NEXT: v_writelane_b32 v63, s30, 2 +; SI-NEXT: v_writelane_b32 v63, s31, 3 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v63, s35, 3 ; SI-NEXT: v_readfirstlane_b32 s47, v1 ; SI-NEXT: v_readfirstlane_b32 s46, v2 ; SI-NEXT: v_readfirstlane_b32 s45, v3 @@ -32026,21 +32340,6 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s6, v17 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v18 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB21_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -32282,15 +32581,15 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v61, v61 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_readlane_b32 s35, v63, 3 +; SI-NEXT: v_readlane_b32 s30, v63, 2 ; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v61 ; SI-NEXT: v_or_b32_e32 v2, v2, v61 ; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v2, v59 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: v_readlane_b32 s31, v63, 3 +; SI-NEXT: v_readlane_b32 s35, v63, 1 +; SI-NEXT: v_readlane_b32 s34, v63, 0 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; SI-NEXT: v_or_b32_e32 v1, v1, v2 ; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 @@ -34731,84 +35030,155 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i ; GFX11-LABEL: bitcast_v64f16_to_v32i32_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 ; GFX11-NEXT: s_clause 0x9 ; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v185, s32 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 ; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 ; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 @@ -35564,28 +35934,29 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 +; SI-NEXT: v_writelane_b32 v20, s34, 0 +; SI-NEXT: v_writelane_b32 v20, s35, 1 +; SI-NEXT: v_writelane_b32 v20, s36, 2 +; SI-NEXT: v_writelane_b32 v20, s37, 3 +; SI-NEXT: v_writelane_b32 v20, s38, 4 +; SI-NEXT: v_writelane_b32 v20, s39, 5 +; SI-NEXT: v_writelane_b32 v20, s48, 6 +; SI-NEXT: v_writelane_b32 v20, s49, 7 +; SI-NEXT: v_writelane_b32 v20, s50, 8 +; SI-NEXT: v_writelane_b32 v20, s51, 9 +; SI-NEXT: v_writelane_b32 v20, s52, 10 +; SI-NEXT: v_writelane_b32 v20, s53, 11 +; SI-NEXT: v_writelane_b32 v20, s54, 12 +; SI-NEXT: v_writelane_b32 v20, s55, 13 +; SI-NEXT: v_writelane_b32 v20, s64, 14 +; SI-NEXT: v_writelane_b32 v20, s65, 15 +; SI-NEXT: v_writelane_b32 v20, s66, 16 +; SI-NEXT: v_writelane_b32 v20, s67, 17 +; SI-NEXT: v_writelane_b32 v20, s68, 18 +; SI-NEXT: v_writelane_b32 v20, s69, 19 +; SI-NEXT: v_writelane_b32 v20, s30, 20 +; SI-NEXT: v_writelane_b32 v20, s31, 21 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 ; SI-NEXT: v_readfirstlane_b32 s44, v1 ; SI-NEXT: v_readfirstlane_b32 s45, v2 ; SI-NEXT: v_readfirstlane_b32 s42, v3 @@ -35605,7 +35976,6 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v17 ; SI-NEXT: s_and_b64 s[46:47], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v18 -; SI-NEXT: v_writelane_b32 v20, s69, 21 ; SI-NEXT: s_cbranch_scc0 .LBB25_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s38, s5, 16 @@ -35924,29 +36294,29 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v20, 20 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s31, v20, 21 +; SI-NEXT: v_readlane_b32 s69, v20, 19 +; SI-NEXT: v_readlane_b32 s68, v20, 18 +; SI-NEXT: v_readlane_b32 s67, v20, 17 +; SI-NEXT: v_readlane_b32 s66, v20, 16 +; SI-NEXT: v_readlane_b32 s65, v20, 15 +; SI-NEXT: v_readlane_b32 s64, v20, 14 +; SI-NEXT: v_readlane_b32 s55, v20, 13 +; SI-NEXT: v_readlane_b32 s54, v20, 12 +; SI-NEXT: v_readlane_b32 s53, v20, 11 +; SI-NEXT: v_readlane_b32 s52, v20, 10 +; SI-NEXT: v_readlane_b32 s51, v20, 9 +; SI-NEXT: v_readlane_b32 s50, v20, 8 +; SI-NEXT: v_readlane_b32 s49, v20, 7 +; SI-NEXT: v_readlane_b32 s48, v20, 6 +; SI-NEXT: v_readlane_b32 s39, v20, 5 +; SI-NEXT: v_readlane_b32 s38, v20, 4 +; SI-NEXT: v_readlane_b32 s37, v20, 3 +; SI-NEXT: v_readlane_b32 s36, v20, 2 +; SI-NEXT: v_readlane_b32 s35, v20, 1 +; SI-NEXT: v_readlane_b32 s34, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -37781,84 +38151,155 @@ define inreg <32 x i32> @bitcast_v64i16_to_v32i32_scalar(<64 x i16> inreg %a, i3 ; GFX11-LABEL: bitcast_v64i16_to_v32i32_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 ; GFX11-NEXT: s_clause 0x9 ; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v185, s32 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 ; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 ; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 @@ -43668,24 +44109,43 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x13 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12 ; GFX11-FAKE16-NEXT: s_clause 0x2 ; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8 @@ -44359,44 +44819,56 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_writelane_b32 v63, s30, 0 -; SI-NEXT: v_writelane_b32 v63, s31, 1 -; SI-NEXT: v_writelane_b32 v63, s34, 2 -; SI-NEXT: v_writelane_b32 v63, s35, 3 -; SI-NEXT: v_writelane_b32 v63, s36, 4 -; SI-NEXT: v_writelane_b32 v63, s37, 5 -; SI-NEXT: v_writelane_b32 v63, s38, 6 -; SI-NEXT: v_writelane_b32 v63, s39, 7 -; SI-NEXT: v_writelane_b32 v63, s48, 8 -; SI-NEXT: v_writelane_b32 v63, s49, 9 -; SI-NEXT: v_writelane_b32 v63, s50, 10 -; SI-NEXT: v_writelane_b32 v63, s51, 11 -; SI-NEXT: v_writelane_b32 v63, s52, 12 -; SI-NEXT: v_writelane_b32 v63, s53, 13 -; SI-NEXT: v_writelane_b32 v63, s54, 14 -; SI-NEXT: v_writelane_b32 v63, s55, 15 -; SI-NEXT: v_writelane_b32 v63, s64, 16 -; SI-NEXT: v_writelane_b32 v63, s65, 17 -; SI-NEXT: v_writelane_b32 v63, s66, 18 -; SI-NEXT: v_writelane_b32 v63, s67, 19 -; SI-NEXT: v_writelane_b32 v63, s68, 20 -; SI-NEXT: v_writelane_b32 v63, s69, 21 -; SI-NEXT: v_writelane_b32 v63, s70, 22 -; SI-NEXT: v_writelane_b32 v63, s71, 23 -; SI-NEXT: v_writelane_b32 v63, s80, 24 -; SI-NEXT: v_writelane_b32 v63, s81, 25 -; SI-NEXT: v_writelane_b32 v63, s82, 26 -; SI-NEXT: v_writelane_b32 v63, s83, 27 -; SI-NEXT: v_writelane_b32 v63, s84, 28 -; SI-NEXT: v_writelane_b32 v63, s85, 29 -; SI-NEXT: v_writelane_b32 v63, s86, 30 -; SI-NEXT: v_writelane_b32 v63, s87, 31 -; SI-NEXT: v_writelane_b32 v63, s96, 32 -; SI-NEXT: v_writelane_b32 v63, s97, 33 -; SI-NEXT: v_writelane_b32 v63, s98, 34 +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_writelane_b32 v63, s34, 0 +; SI-NEXT: v_writelane_b32 v63, s35, 1 +; SI-NEXT: v_writelane_b32 v63, s36, 2 +; SI-NEXT: v_writelane_b32 v63, s37, 3 +; SI-NEXT: v_writelane_b32 v63, s38, 4 +; SI-NEXT: v_writelane_b32 v63, s39, 5 +; SI-NEXT: v_writelane_b32 v63, s48, 6 +; SI-NEXT: v_writelane_b32 v63, s49, 7 +; SI-NEXT: v_writelane_b32 v63, s50, 8 +; SI-NEXT: v_writelane_b32 v63, s51, 9 +; SI-NEXT: v_writelane_b32 v63, s52, 10 +; SI-NEXT: v_writelane_b32 v63, s53, 11 +; SI-NEXT: v_writelane_b32 v63, s54, 12 +; SI-NEXT: v_writelane_b32 v63, s55, 13 +; SI-NEXT: v_writelane_b32 v63, s64, 14 +; SI-NEXT: v_writelane_b32 v63, s65, 15 +; SI-NEXT: v_writelane_b32 v63, s66, 16 +; SI-NEXT: v_writelane_b32 v63, s67, 17 +; SI-NEXT: v_writelane_b32 v63, s68, 18 +; SI-NEXT: v_writelane_b32 v63, s69, 19 +; SI-NEXT: v_writelane_b32 v63, s70, 20 +; SI-NEXT: v_writelane_b32 v63, s71, 21 +; SI-NEXT: v_writelane_b32 v63, s80, 22 +; SI-NEXT: v_writelane_b32 v63, s81, 23 +; SI-NEXT: v_writelane_b32 v63, s82, 24 +; SI-NEXT: v_writelane_b32 v63, s83, 25 +; SI-NEXT: v_writelane_b32 v63, s84, 26 +; SI-NEXT: v_writelane_b32 v63, s85, 27 +; SI-NEXT: v_writelane_b32 v63, s86, 28 +; SI-NEXT: v_writelane_b32 v63, s87, 29 +; SI-NEXT: v_writelane_b32 v63, s96, 30 +; SI-NEXT: v_writelane_b32 v63, s97, 31 +; SI-NEXT: v_writelane_b32 v63, s98, 32 +; SI-NEXT: v_writelane_b32 v63, s99, 33 +; SI-NEXT: v_writelane_b32 v63, s30, 34 +; SI-NEXT: v_writelane_b32 v63, s31, 35 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v63, s99, 35 ; SI-NEXT: v_readfirstlane_b32 s44, v1 ; SI-NEXT: v_readfirstlane_b32 s45, v2 ; SI-NEXT: v_readfirstlane_b32 s42, v3 @@ -44416,19 +44888,6 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; SI-NEXT: v_readfirstlane_b32 s4, v17 ; SI-NEXT: s_and_b64 s[46:47], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v18 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane ; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB37_3 @@ -45563,42 +46022,42 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; SI-NEXT: v_and_b32_e32 v6, 0xff, v6 ; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 ; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_readlane_b32 s99, v63, 35 -; SI-NEXT: v_readlane_b32 s98, v63, 34 -; SI-NEXT: v_readlane_b32 s97, v63, 33 -; SI-NEXT: v_readlane_b32 s96, v63, 32 -; SI-NEXT: v_readlane_b32 s87, v63, 31 -; SI-NEXT: v_readlane_b32 s86, v63, 30 -; SI-NEXT: v_readlane_b32 s85, v63, 29 -; SI-NEXT: v_readlane_b32 s84, v63, 28 -; SI-NEXT: v_readlane_b32 s83, v63, 27 -; SI-NEXT: v_readlane_b32 s82, v63, 26 -; SI-NEXT: v_readlane_b32 s81, v63, 25 -; SI-NEXT: v_readlane_b32 s80, v63, 24 -; SI-NEXT: v_readlane_b32 s71, v63, 23 -; SI-NEXT: v_readlane_b32 s70, v63, 22 -; SI-NEXT: v_readlane_b32 s69, v63, 21 -; SI-NEXT: v_readlane_b32 s68, v63, 20 -; SI-NEXT: v_readlane_b32 s67, v63, 19 -; SI-NEXT: v_readlane_b32 s66, v63, 18 -; SI-NEXT: v_readlane_b32 s65, v63, 17 -; SI-NEXT: v_readlane_b32 s64, v63, 16 -; SI-NEXT: v_readlane_b32 s55, v63, 15 -; SI-NEXT: v_readlane_b32 s54, v63, 14 -; SI-NEXT: v_readlane_b32 s53, v63, 13 -; SI-NEXT: v_readlane_b32 s52, v63, 12 -; SI-NEXT: v_readlane_b32 s51, v63, 11 -; SI-NEXT: v_readlane_b32 s50, v63, 10 -; SI-NEXT: v_readlane_b32 s49, v63, 9 -; SI-NEXT: v_readlane_b32 s48, v63, 8 -; SI-NEXT: v_readlane_b32 s39, v63, 7 -; SI-NEXT: v_readlane_b32 s38, v63, 6 -; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s36, v63, 4 -; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: v_readlane_b32 s30, v63, 34 +; SI-NEXT: v_readlane_b32 s31, v63, 35 +; SI-NEXT: v_readlane_b32 s99, v63, 33 +; SI-NEXT: v_readlane_b32 s98, v63, 32 +; SI-NEXT: v_readlane_b32 s97, v63, 31 +; SI-NEXT: v_readlane_b32 s96, v63, 30 +; SI-NEXT: v_readlane_b32 s87, v63, 29 +; SI-NEXT: v_readlane_b32 s86, v63, 28 +; SI-NEXT: v_readlane_b32 s85, v63, 27 +; SI-NEXT: v_readlane_b32 s84, v63, 26 +; SI-NEXT: v_readlane_b32 s83, v63, 25 +; SI-NEXT: v_readlane_b32 s82, v63, 24 +; SI-NEXT: v_readlane_b32 s81, v63, 23 +; SI-NEXT: v_readlane_b32 s80, v63, 22 +; SI-NEXT: v_readlane_b32 s71, v63, 21 +; SI-NEXT: v_readlane_b32 s70, v63, 20 +; SI-NEXT: v_readlane_b32 s69, v63, 19 +; SI-NEXT: v_readlane_b32 s68, v63, 18 +; SI-NEXT: v_readlane_b32 s67, v63, 17 +; SI-NEXT: v_readlane_b32 s66, v63, 16 +; SI-NEXT: v_readlane_b32 s65, v63, 15 +; SI-NEXT: v_readlane_b32 s64, v63, 14 +; SI-NEXT: v_readlane_b32 s55, v63, 13 +; SI-NEXT: v_readlane_b32 s54, v63, 12 +; SI-NEXT: v_readlane_b32 s53, v63, 11 +; SI-NEXT: v_readlane_b32 s52, v63, 10 +; SI-NEXT: v_readlane_b32 s51, v63, 9 +; SI-NEXT: v_readlane_b32 s50, v63, 8 +; SI-NEXT: v_readlane_b32 s49, v63, 7 +; SI-NEXT: v_readlane_b32 s48, v63, 6 +; SI-NEXT: v_readlane_b32 s39, v63, 5 +; SI-NEXT: v_readlane_b32 s38, v63, 4 +; SI-NEXT: v_readlane_b32 s37, v63, 3 +; SI-NEXT: v_readlane_b32 s36, v63, 2 +; SI-NEXT: v_readlane_b32 s35, v63, 1 +; SI-NEXT: v_readlane_b32 s34, v63, 0 ; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v22 ; SI-NEXT: v_and_b32_e32 v22, 0xff, v52 @@ -46098,39 +46557,53 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v63, s30, 0 -; VI-NEXT: v_writelane_b32 v63, s31, 1 -; VI-NEXT: v_writelane_b32 v63, s34, 2 -; VI-NEXT: v_writelane_b32 v63, s35, 3 -; VI-NEXT: v_writelane_b32 v63, s36, 4 -; VI-NEXT: v_writelane_b32 v63, s37, 5 -; VI-NEXT: v_writelane_b32 v63, s38, 6 -; VI-NEXT: v_writelane_b32 v63, s39, 7 -; VI-NEXT: v_writelane_b32 v63, s48, 8 -; VI-NEXT: v_writelane_b32 v63, s49, 9 -; VI-NEXT: v_writelane_b32 v63, s50, 10 -; VI-NEXT: v_writelane_b32 v63, s51, 11 -; VI-NEXT: v_writelane_b32 v63, s52, 12 -; VI-NEXT: v_writelane_b32 v63, s53, 13 -; VI-NEXT: v_writelane_b32 v63, s54, 14 -; VI-NEXT: v_writelane_b32 v63, s55, 15 -; VI-NEXT: v_writelane_b32 v63, s64, 16 -; VI-NEXT: v_writelane_b32 v63, s65, 17 -; VI-NEXT: v_writelane_b32 v63, s66, 18 -; VI-NEXT: v_writelane_b32 v63, s67, 19 -; VI-NEXT: v_writelane_b32 v63, s68, 20 -; VI-NEXT: v_writelane_b32 v63, s69, 21 -; VI-NEXT: v_writelane_b32 v63, s70, 22 -; VI-NEXT: v_writelane_b32 v63, s71, 23 -; VI-NEXT: v_writelane_b32 v63, s80, 24 -; VI-NEXT: v_writelane_b32 v63, s81, 25 -; VI-NEXT: v_writelane_b32 v63, s82, 26 -; VI-NEXT: v_writelane_b32 v63, s83, 27 -; VI-NEXT: v_writelane_b32 v63, s84, 28 -; VI-NEXT: v_writelane_b32 v63, s85, 29 -; VI-NEXT: v_writelane_b32 v63, s86, 30 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_writelane_b32 v63, s34, 0 +; VI-NEXT: v_writelane_b32 v63, s35, 1 +; VI-NEXT: v_writelane_b32 v63, s36, 2 +; VI-NEXT: v_writelane_b32 v63, s37, 3 +; VI-NEXT: v_writelane_b32 v63, s38, 4 +; VI-NEXT: v_writelane_b32 v63, s39, 5 +; VI-NEXT: v_writelane_b32 v63, s48, 6 +; VI-NEXT: v_writelane_b32 v63, s49, 7 +; VI-NEXT: v_writelane_b32 v63, s50, 8 +; VI-NEXT: v_writelane_b32 v63, s51, 9 +; VI-NEXT: v_writelane_b32 v63, s52, 10 +; VI-NEXT: v_writelane_b32 v63, s53, 11 +; VI-NEXT: v_writelane_b32 v63, s54, 12 +; VI-NEXT: v_writelane_b32 v63, s55, 13 +; VI-NEXT: v_writelane_b32 v63, s64, 14 +; VI-NEXT: v_writelane_b32 v63, s65, 15 +; VI-NEXT: v_writelane_b32 v63, s66, 16 +; VI-NEXT: v_writelane_b32 v63, s67, 17 +; VI-NEXT: v_writelane_b32 v63, s68, 18 +; VI-NEXT: v_writelane_b32 v63, s69, 19 +; VI-NEXT: v_writelane_b32 v63, s70, 20 +; VI-NEXT: v_writelane_b32 v63, s71, 21 +; VI-NEXT: v_writelane_b32 v63, s80, 22 +; VI-NEXT: v_writelane_b32 v63, s81, 23 +; VI-NEXT: v_writelane_b32 v63, s82, 24 +; VI-NEXT: v_writelane_b32 v63, s83, 25 +; VI-NEXT: v_writelane_b32 v63, s84, 26 +; VI-NEXT: v_writelane_b32 v63, s85, 27 +; VI-NEXT: v_writelane_b32 v63, s86, 28 +; VI-NEXT: v_writelane_b32 v63, s87, 29 +; VI-NEXT: v_writelane_b32 v63, s30, 30 +; VI-NEXT: v_writelane_b32 v63, s31, 31 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v63, s87, 31 ; VI-NEXT: v_readfirstlane_b32 s44, v1 ; VI-NEXT: v_readfirstlane_b32 s45, v2 ; VI-NEXT: v_readfirstlane_b32 s42, v3 @@ -46150,20 +46623,6 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: v_readfirstlane_b32 s4, v17 ; VI-NEXT: s_and_b64 s[46:47], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v18 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB37_3 ; VI-NEXT: ; %bb.1: ; %cmp.false @@ -47018,38 +47477,38 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: v_lshlrev_b32_e32 v23, 8, v50 ; VI-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v24, 8, v36 -; VI-NEXT: v_readlane_b32 s87, v63, 31 -; VI-NEXT: v_readlane_b32 s86, v63, 30 -; VI-NEXT: v_readlane_b32 s85, v63, 29 -; VI-NEXT: v_readlane_b32 s84, v63, 28 -; VI-NEXT: v_readlane_b32 s83, v63, 27 -; VI-NEXT: v_readlane_b32 s82, v63, 26 -; VI-NEXT: v_readlane_b32 s81, v63, 25 -; VI-NEXT: v_readlane_b32 s80, v63, 24 -; VI-NEXT: v_readlane_b32 s71, v63, 23 -; VI-NEXT: v_readlane_b32 s70, v63, 22 -; VI-NEXT: v_readlane_b32 s69, v63, 21 -; VI-NEXT: v_readlane_b32 s68, v63, 20 -; VI-NEXT: v_readlane_b32 s67, v63, 19 -; VI-NEXT: v_readlane_b32 s66, v63, 18 -; VI-NEXT: v_readlane_b32 s65, v63, 17 -; VI-NEXT: v_readlane_b32 s64, v63, 16 -; VI-NEXT: v_readlane_b32 s55, v63, 15 -; VI-NEXT: v_readlane_b32 s54, v63, 14 -; VI-NEXT: v_readlane_b32 s53, v63, 13 -; VI-NEXT: v_readlane_b32 s52, v63, 12 -; VI-NEXT: v_readlane_b32 s51, v63, 11 -; VI-NEXT: v_readlane_b32 s50, v63, 10 -; VI-NEXT: v_readlane_b32 s49, v63, 9 -; VI-NEXT: v_readlane_b32 s48, v63, 8 -; VI-NEXT: v_readlane_b32 s39, v63, 7 -; VI-NEXT: v_readlane_b32 s38, v63, 6 -; VI-NEXT: v_readlane_b32 s37, v63, 5 -; VI-NEXT: v_readlane_b32 s36, v63, 4 -; VI-NEXT: v_readlane_b32 s35, v63, 3 -; VI-NEXT: v_readlane_b32 s34, v63, 2 -; VI-NEXT: v_readlane_b32 s31, v63, 1 -; VI-NEXT: v_readlane_b32 s30, v63, 0 +; VI-NEXT: v_readlane_b32 s30, v63, 30 +; VI-NEXT: v_readlane_b32 s31, v63, 31 +; VI-NEXT: v_readlane_b32 s87, v63, 29 +; VI-NEXT: v_readlane_b32 s86, v63, 28 +; VI-NEXT: v_readlane_b32 s85, v63, 27 +; VI-NEXT: v_readlane_b32 s84, v63, 26 +; VI-NEXT: v_readlane_b32 s83, v63, 25 +; VI-NEXT: v_readlane_b32 s82, v63, 24 +; VI-NEXT: v_readlane_b32 s81, v63, 23 +; VI-NEXT: v_readlane_b32 s80, v63, 22 +; VI-NEXT: v_readlane_b32 s71, v63, 21 +; VI-NEXT: v_readlane_b32 s70, v63, 20 +; VI-NEXT: v_readlane_b32 s69, v63, 19 +; VI-NEXT: v_readlane_b32 s68, v63, 18 +; VI-NEXT: v_readlane_b32 s67, v63, 17 +; VI-NEXT: v_readlane_b32 s66, v63, 16 +; VI-NEXT: v_readlane_b32 s65, v63, 15 +; VI-NEXT: v_readlane_b32 s64, v63, 14 +; VI-NEXT: v_readlane_b32 s55, v63, 13 +; VI-NEXT: v_readlane_b32 s54, v63, 12 +; VI-NEXT: v_readlane_b32 s53, v63, 11 +; VI-NEXT: v_readlane_b32 s52, v63, 10 +; VI-NEXT: v_readlane_b32 s51, v63, 9 +; VI-NEXT: v_readlane_b32 s50, v63, 8 +; VI-NEXT: v_readlane_b32 s49, v63, 7 +; VI-NEXT: v_readlane_b32 s48, v63, 6 +; VI-NEXT: v_readlane_b32 s39, v63, 5 +; VI-NEXT: v_readlane_b32 s38, v63, 4 +; VI-NEXT: v_readlane_b32 s37, v63, 3 +; VI-NEXT: v_readlane_b32 s36, v63, 2 +; VI-NEXT: v_readlane_b32 s35, v63, 1 +; VI-NEXT: v_readlane_b32 s34, v63, 0 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD @@ -47369,43 +47828,57 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v63, s30, 0 -; GFX9-NEXT: v_writelane_b32 v63, s31, 1 -; GFX9-NEXT: v_writelane_b32 v63, s34, 2 -; GFX9-NEXT: v_writelane_b32 v63, s35, 3 -; GFX9-NEXT: v_writelane_b32 v63, s36, 4 -; GFX9-NEXT: v_writelane_b32 v63, s37, 5 -; GFX9-NEXT: v_writelane_b32 v63, s38, 6 -; GFX9-NEXT: v_writelane_b32 v63, s39, 7 -; GFX9-NEXT: v_writelane_b32 v63, s48, 8 -; GFX9-NEXT: v_writelane_b32 v63, s49, 9 -; GFX9-NEXT: v_writelane_b32 v63, s50, 10 -; GFX9-NEXT: v_writelane_b32 v63, s51, 11 -; GFX9-NEXT: v_writelane_b32 v63, s52, 12 -; GFX9-NEXT: v_writelane_b32 v63, s53, 13 -; GFX9-NEXT: v_writelane_b32 v63, s54, 14 -; GFX9-NEXT: v_writelane_b32 v63, s55, 15 -; GFX9-NEXT: v_writelane_b32 v63, s64, 16 -; GFX9-NEXT: v_writelane_b32 v63, s65, 17 -; GFX9-NEXT: v_writelane_b32 v63, s66, 18 -; GFX9-NEXT: v_writelane_b32 v63, s67, 19 -; GFX9-NEXT: v_writelane_b32 v63, s68, 20 -; GFX9-NEXT: v_writelane_b32 v63, s69, 21 -; GFX9-NEXT: v_writelane_b32 v63, s70, 22 -; GFX9-NEXT: v_writelane_b32 v63, s71, 23 -; GFX9-NEXT: v_writelane_b32 v63, s80, 24 -; GFX9-NEXT: v_writelane_b32 v63, s81, 25 -; GFX9-NEXT: v_writelane_b32 v63, s82, 26 -; GFX9-NEXT: v_writelane_b32 v63, s83, 27 -; GFX9-NEXT: v_writelane_b32 v63, s84, 28 -; GFX9-NEXT: v_writelane_b32 v63, s85, 29 -; GFX9-NEXT: v_writelane_b32 v63, s86, 30 -; GFX9-NEXT: v_writelane_b32 v63, s87, 31 -; GFX9-NEXT: v_writelane_b32 v63, s96, 32 -; GFX9-NEXT: v_writelane_b32 v63, s97, 33 -; GFX9-NEXT: v_writelane_b32 v63, s98, 34 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v63, s34, 0 +; GFX9-NEXT: v_writelane_b32 v63, s35, 1 +; GFX9-NEXT: v_writelane_b32 v63, s36, 2 +; GFX9-NEXT: v_writelane_b32 v63, s37, 3 +; GFX9-NEXT: v_writelane_b32 v63, s38, 4 +; GFX9-NEXT: v_writelane_b32 v63, s39, 5 +; GFX9-NEXT: v_writelane_b32 v63, s48, 6 +; GFX9-NEXT: v_writelane_b32 v63, s49, 7 +; GFX9-NEXT: v_writelane_b32 v63, s50, 8 +; GFX9-NEXT: v_writelane_b32 v63, s51, 9 +; GFX9-NEXT: v_writelane_b32 v63, s52, 10 +; GFX9-NEXT: v_writelane_b32 v63, s53, 11 +; GFX9-NEXT: v_writelane_b32 v63, s54, 12 +; GFX9-NEXT: v_writelane_b32 v63, s55, 13 +; GFX9-NEXT: v_writelane_b32 v63, s64, 14 +; GFX9-NEXT: v_writelane_b32 v63, s65, 15 +; GFX9-NEXT: v_writelane_b32 v63, s66, 16 +; GFX9-NEXT: v_writelane_b32 v63, s67, 17 +; GFX9-NEXT: v_writelane_b32 v63, s68, 18 +; GFX9-NEXT: v_writelane_b32 v63, s69, 19 +; GFX9-NEXT: v_writelane_b32 v63, s70, 20 +; GFX9-NEXT: v_writelane_b32 v63, s71, 21 +; GFX9-NEXT: v_writelane_b32 v63, s80, 22 +; GFX9-NEXT: v_writelane_b32 v63, s81, 23 +; GFX9-NEXT: v_writelane_b32 v63, s82, 24 +; GFX9-NEXT: v_writelane_b32 v63, s83, 25 +; GFX9-NEXT: v_writelane_b32 v63, s84, 26 +; GFX9-NEXT: v_writelane_b32 v63, s85, 27 +; GFX9-NEXT: v_writelane_b32 v63, s86, 28 +; GFX9-NEXT: v_writelane_b32 v63, s87, 29 +; GFX9-NEXT: v_writelane_b32 v63, s96, 30 +; GFX9-NEXT: v_writelane_b32 v63, s97, 31 +; GFX9-NEXT: v_writelane_b32 v63, s98, 32 +; GFX9-NEXT: v_writelane_b32 v63, s99, 33 +; GFX9-NEXT: v_writelane_b32 v63, s30, 34 +; GFX9-NEXT: v_writelane_b32 v63, s31, 35 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; GFX9-NEXT: v_writelane_b32 v63, s99, 35 ; GFX9-NEXT: v_readfirstlane_b32 s44, v1 ; GFX9-NEXT: v_readfirstlane_b32 s45, v2 ; GFX9-NEXT: v_readfirstlane_b32 s42, v3 @@ -47425,20 +47898,6 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: v_readfirstlane_b32 s4, v17 ; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v18 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB37_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false @@ -48291,42 +48750,42 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:16 ; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload ; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v49 -; GFX9-NEXT: v_readlane_b32 s99, v63, 35 -; GFX9-NEXT: v_readlane_b32 s98, v63, 34 -; GFX9-NEXT: v_readlane_b32 s97, v63, 33 -; GFX9-NEXT: v_readlane_b32 s96, v63, 32 -; GFX9-NEXT: v_readlane_b32 s87, v63, 31 -; GFX9-NEXT: v_readlane_b32 s86, v63, 30 -; GFX9-NEXT: v_readlane_b32 s85, v63, 29 -; GFX9-NEXT: v_readlane_b32 s84, v63, 28 -; GFX9-NEXT: v_readlane_b32 s83, v63, 27 -; GFX9-NEXT: v_readlane_b32 s82, v63, 26 -; GFX9-NEXT: v_readlane_b32 s81, v63, 25 -; GFX9-NEXT: v_readlane_b32 s80, v63, 24 -; GFX9-NEXT: v_readlane_b32 s71, v63, 23 -; GFX9-NEXT: v_readlane_b32 s70, v63, 22 -; GFX9-NEXT: v_readlane_b32 s69, v63, 21 -; GFX9-NEXT: v_readlane_b32 s68, v63, 20 -; GFX9-NEXT: v_readlane_b32 s67, v63, 19 -; GFX9-NEXT: v_readlane_b32 s66, v63, 18 -; GFX9-NEXT: v_readlane_b32 s65, v63, 17 -; GFX9-NEXT: v_readlane_b32 s64, v63, 16 -; GFX9-NEXT: v_readlane_b32 s55, v63, 15 -; GFX9-NEXT: v_readlane_b32 s54, v63, 14 -; GFX9-NEXT: v_readlane_b32 s53, v63, 13 -; GFX9-NEXT: v_readlane_b32 s52, v63, 12 -; GFX9-NEXT: v_readlane_b32 s51, v63, 11 -; GFX9-NEXT: v_readlane_b32 s50, v63, 10 -; GFX9-NEXT: v_readlane_b32 s49, v63, 9 -; GFX9-NEXT: v_readlane_b32 s48, v63, 8 -; GFX9-NEXT: v_readlane_b32 s39, v63, 7 -; GFX9-NEXT: v_readlane_b32 s38, v63, 6 -; GFX9-NEXT: v_readlane_b32 s37, v63, 5 -; GFX9-NEXT: v_readlane_b32 s36, v63, 4 -; GFX9-NEXT: v_readlane_b32 s35, v63, 3 -; GFX9-NEXT: v_readlane_b32 s34, v63, 2 -; GFX9-NEXT: v_readlane_b32 s31, v63, 1 -; GFX9-NEXT: v_readlane_b32 s30, v63, 0 +; GFX9-NEXT: v_readlane_b32 s30, v63, 34 +; GFX9-NEXT: v_readlane_b32 s31, v63, 35 +; GFX9-NEXT: v_readlane_b32 s99, v63, 33 +; GFX9-NEXT: v_readlane_b32 s98, v63, 32 +; GFX9-NEXT: v_readlane_b32 s97, v63, 31 +; GFX9-NEXT: v_readlane_b32 s96, v63, 30 +; GFX9-NEXT: v_readlane_b32 s87, v63, 29 +; GFX9-NEXT: v_readlane_b32 s86, v63, 28 +; GFX9-NEXT: v_readlane_b32 s85, v63, 27 +; GFX9-NEXT: v_readlane_b32 s84, v63, 26 +; GFX9-NEXT: v_readlane_b32 s83, v63, 25 +; GFX9-NEXT: v_readlane_b32 s82, v63, 24 +; GFX9-NEXT: v_readlane_b32 s81, v63, 23 +; GFX9-NEXT: v_readlane_b32 s80, v63, 22 +; GFX9-NEXT: v_readlane_b32 s71, v63, 21 +; GFX9-NEXT: v_readlane_b32 s70, v63, 20 +; GFX9-NEXT: v_readlane_b32 s69, v63, 19 +; GFX9-NEXT: v_readlane_b32 s68, v63, 18 +; GFX9-NEXT: v_readlane_b32 s67, v63, 17 +; GFX9-NEXT: v_readlane_b32 s66, v63, 16 +; GFX9-NEXT: v_readlane_b32 s65, v63, 15 +; GFX9-NEXT: v_readlane_b32 s64, v63, 14 +; GFX9-NEXT: v_readlane_b32 s55, v63, 13 +; GFX9-NEXT: v_readlane_b32 s54, v63, 12 +; GFX9-NEXT: v_readlane_b32 s53, v63, 11 +; GFX9-NEXT: v_readlane_b32 s52, v63, 10 +; GFX9-NEXT: v_readlane_b32 s51, v63, 9 +; GFX9-NEXT: v_readlane_b32 s50, v63, 8 +; GFX9-NEXT: v_readlane_b32 s49, v63, 7 +; GFX9-NEXT: v_readlane_b32 s48, v63, 6 +; GFX9-NEXT: v_readlane_b32 s39, v63, 5 +; GFX9-NEXT: v_readlane_b32 s38, v63, 4 +; GFX9-NEXT: v_readlane_b32 s37, v63, 3 +; GFX9-NEXT: v_readlane_b32 s36, v63, 2 +; GFX9-NEXT: v_readlane_b32 s35, v63, 1 +; GFX9-NEXT: v_readlane_b32 s34, v63, 0 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v15, v35, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD @@ -48648,90 +49107,111 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v75, s30, 0 -; GFX11-NEXT: v_writelane_b32 v76, s96, 0 -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_readfirstlane_b32 s40, v1 -; GFX11-NEXT: v_readfirstlane_b32 s41, v2 -; GFX11-NEXT: v_writelane_b32 v75, s31, 1 -; GFX11-NEXT: v_writelane_b32 v76, s97, 1 -; GFX11-NEXT: v_readfirstlane_b32 s14, v3 -; GFX11-NEXT: v_readfirstlane_b32 s15, v4 -; GFX11-NEXT: v_readfirstlane_b32 s4, v5 -; GFX11-NEXT: v_writelane_b32 v75, s34, 2 -; GFX11-NEXT: v_writelane_b32 v76, s98, 2 -; GFX11-NEXT: v_readfirstlane_b32 s5, v6 -; GFX11-NEXT: v_readfirstlane_b32 s6, v7 -; GFX11-NEXT: v_readfirstlane_b32 s7, v8 -; GFX11-NEXT: v_writelane_b32 v75, s35, 3 -; GFX11-NEXT: v_writelane_b32 v76, s99, 3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v9 -; GFX11-NEXT: v_readfirstlane_b32 s9, v10 -; GFX11-NEXT: v_readfirstlane_b32 s10, v11 -; GFX11-NEXT: v_writelane_b32 v75, s36, 4 -; GFX11-NEXT: v_writelane_b32 v76, s100, 4 -; GFX11-NEXT: v_readfirstlane_b32 s11, v12 -; GFX11-NEXT: v_readfirstlane_b32 s12, v13 -; GFX11-NEXT: v_readfirstlane_b32 s13, v14 -; GFX11-NEXT: v_writelane_b32 v75, s37, 5 -; GFX11-NEXT: v_writelane_b32 v76, s101, 5 -; GFX11-NEXT: s_mov_b32 vcc_hi, 0 -; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: s_clause 0x12 ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:40 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 -; GFX11-NEXT: v_writelane_b32 v75, s38, 6 -; GFX11-NEXT: v_writelane_b32 v76, s102, 6 +; GFX11-NEXT: v_writelane_b32 v75, s34, 0 +; GFX11-NEXT: v_writelane_b32 v75, s35, 1 +; GFX11-NEXT: v_writelane_b32 v75, s36, 2 +; GFX11-NEXT: v_writelane_b32 v75, s37, 3 +; GFX11-NEXT: v_writelane_b32 v75, s38, 4 +; GFX11-NEXT: v_writelane_b32 v75, s39, 5 +; GFX11-NEXT: v_writelane_b32 v75, s48, 6 +; GFX11-NEXT: v_writelane_b32 v75, s49, 7 +; GFX11-NEXT: v_writelane_b32 v75, s50, 8 +; GFX11-NEXT: v_writelane_b32 v75, s51, 9 +; GFX11-NEXT: v_writelane_b32 v75, s52, 10 +; GFX11-NEXT: v_writelane_b32 v75, s53, 11 +; GFX11-NEXT: v_writelane_b32 v75, s54, 12 +; GFX11-NEXT: v_writelane_b32 v75, s55, 13 +; GFX11-NEXT: v_writelane_b32 v75, s64, 14 +; GFX11-NEXT: v_writelane_b32 v75, s65, 15 +; GFX11-NEXT: v_writelane_b32 v75, s66, 16 +; GFX11-NEXT: v_writelane_b32 v75, s67, 17 +; GFX11-NEXT: v_writelane_b32 v75, s68, 18 +; GFX11-NEXT: v_writelane_b32 v75, s69, 19 +; GFX11-NEXT: v_writelane_b32 v75, s70, 20 +; GFX11-NEXT: v_writelane_b32 v75, s71, 21 +; GFX11-NEXT: v_writelane_b32 v75, s80, 22 +; GFX11-NEXT: v_writelane_b32 v75, s81, 23 +; GFX11-NEXT: v_writelane_b32 v75, s82, 24 +; GFX11-NEXT: v_writelane_b32 v75, s83, 25 +; GFX11-NEXT: v_writelane_b32 v75, s84, 26 +; GFX11-NEXT: v_writelane_b32 v75, s85, 27 +; GFX11-NEXT: v_writelane_b32 v75, s86, 28 +; GFX11-NEXT: v_writelane_b32 v75, s87, 29 +; GFX11-NEXT: v_writelane_b32 v75, s96, 30 +; GFX11-NEXT: v_writelane_b32 v75, s97, 31 +; GFX11-NEXT: v_writelane_b32 v76, s98, 0 +; GFX11-NEXT: v_writelane_b32 v76, s99, 1 +; GFX11-NEXT: v_writelane_b32 v76, s100, 2 +; GFX11-NEXT: v_writelane_b32 v76, s101, 3 +; GFX11-NEXT: v_writelane_b32 v76, s102, 4 +; GFX11-NEXT: v_writelane_b32 v76, s103, 5 +; GFX11-NEXT: v_writelane_b32 v76, s104, 6 +; GFX11-NEXT: v_writelane_b32 v76, s30, 7 +; GFX11-NEXT: v_writelane_b32 v76, s31, 8 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 +; GFX11-NEXT: v_readfirstlane_b32 s40, v1 +; GFX11-NEXT: v_readfirstlane_b32 s41, v2 +; GFX11-NEXT: v_readfirstlane_b32 s14, v3 +; GFX11-NEXT: v_readfirstlane_b32 s15, v4 +; GFX11-NEXT: v_readfirstlane_b32 s4, v5 +; GFX11-NEXT: v_readfirstlane_b32 s5, v6 +; GFX11-NEXT: v_readfirstlane_b32 s6, v7 +; GFX11-NEXT: v_readfirstlane_b32 s7, v8 +; GFX11-NEXT: v_readfirstlane_b32 s8, v9 +; GFX11-NEXT: v_readfirstlane_b32 s9, v10 +; GFX11-NEXT: v_readfirstlane_b32 s10, v11 +; GFX11-NEXT: v_readfirstlane_b32 s11, v12 +; GFX11-NEXT: v_readfirstlane_b32 s12, v13 +; GFX11-NEXT: v_readfirstlane_b32 s13, v14 +; GFX11-NEXT: s_mov_b32 vcc_hi, 0 +; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane ; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v75, s39, 7 -; GFX11-NEXT: v_writelane_b32 v76, s103, 7 -; GFX11-NEXT: v_writelane_b32 v75, s48, 8 -; GFX11-NEXT: v_writelane_b32 v76, s104, 8 -; GFX11-NEXT: v_writelane_b32 v75, s49, 9 -; GFX11-NEXT: v_writelane_b32 v75, s50, 10 -; GFX11-NEXT: v_writelane_b32 v75, s51, 11 -; GFX11-NEXT: v_writelane_b32 v75, s52, 12 -; GFX11-NEXT: v_writelane_b32 v75, s53, 13 -; GFX11-NEXT: v_writelane_b32 v75, s54, 14 -; GFX11-NEXT: v_writelane_b32 v75, s55, 15 -; GFX11-NEXT: v_writelane_b32 v75, s64, 16 -; GFX11-NEXT: v_writelane_b32 v75, s65, 17 -; GFX11-NEXT: v_writelane_b32 v75, s66, 18 -; GFX11-NEXT: v_writelane_b32 v75, s67, 19 -; GFX11-NEXT: v_writelane_b32 v75, s68, 20 -; GFX11-NEXT: v_writelane_b32 v75, s69, 21 -; GFX11-NEXT: v_writelane_b32 v75, s70, 22 -; GFX11-NEXT: v_writelane_b32 v75, s71, 23 -; GFX11-NEXT: v_writelane_b32 v75, s80, 24 -; GFX11-NEXT: v_writelane_b32 v75, s81, 25 -; GFX11-NEXT: v_writelane_b32 v75, s82, 26 -; GFX11-NEXT: v_writelane_b32 v75, s83, 27 -; GFX11-NEXT: v_writelane_b32 v75, s84, 28 -; GFX11-NEXT: v_writelane_b32 v75, s85, 29 -; GFX11-NEXT: v_writelane_b32 v75, s86, 30 -; GFX11-NEXT: v_writelane_b32 v75, s87, 31 ; GFX11-NEXT: s_cbranch_scc0 .LBB37_3 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s42, s13, 24 @@ -49621,47 +50101,47 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:64 ; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:68 ; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:72 -; GFX11-NEXT: v_readlane_b32 s104, v76, 8 -; GFX11-NEXT: v_readlane_b32 s103, v76, 7 -; GFX11-NEXT: v_readlane_b32 s102, v76, 6 -; GFX11-NEXT: v_readlane_b32 s101, v76, 5 -; GFX11-NEXT: v_readlane_b32 s100, v76, 4 -; GFX11-NEXT: v_readlane_b32 s99, v76, 3 -; GFX11-NEXT: v_readlane_b32 s98, v76, 2 -; GFX11-NEXT: v_readlane_b32 s97, v76, 1 -; GFX11-NEXT: v_readlane_b32 s96, v76, 0 -; GFX11-NEXT: v_readlane_b32 s87, v75, 31 -; GFX11-NEXT: v_readlane_b32 s86, v75, 30 -; GFX11-NEXT: v_readlane_b32 s85, v75, 29 -; GFX11-NEXT: v_readlane_b32 s84, v75, 28 -; GFX11-NEXT: v_readlane_b32 s83, v75, 27 -; GFX11-NEXT: v_readlane_b32 s82, v75, 26 -; GFX11-NEXT: v_readlane_b32 s81, v75, 25 -; GFX11-NEXT: v_readlane_b32 s80, v75, 24 -; GFX11-NEXT: v_readlane_b32 s71, v75, 23 -; GFX11-NEXT: v_readlane_b32 s70, v75, 22 -; GFX11-NEXT: v_readlane_b32 s69, v75, 21 -; GFX11-NEXT: v_readlane_b32 s68, v75, 20 -; GFX11-NEXT: v_readlane_b32 s67, v75, 19 -; GFX11-NEXT: v_readlane_b32 s66, v75, 18 -; GFX11-NEXT: v_readlane_b32 s65, v75, 17 -; GFX11-NEXT: v_readlane_b32 s64, v75, 16 -; GFX11-NEXT: v_readlane_b32 s55, v75, 15 -; GFX11-NEXT: v_readlane_b32 s54, v75, 14 -; GFX11-NEXT: v_readlane_b32 s53, v75, 13 -; GFX11-NEXT: v_readlane_b32 s52, v75, 12 -; GFX11-NEXT: v_readlane_b32 s51, v75, 11 -; GFX11-NEXT: v_readlane_b32 s50, v75, 10 -; GFX11-NEXT: v_readlane_b32 s49, v75, 9 -; GFX11-NEXT: v_readlane_b32 s48, v75, 8 -; GFX11-NEXT: v_readlane_b32 s39, v75, 7 -; GFX11-NEXT: v_readlane_b32 s38, v75, 6 -; GFX11-NEXT: v_readlane_b32 s37, v75, 5 -; GFX11-NEXT: v_readlane_b32 s36, v75, 4 -; GFX11-NEXT: v_readlane_b32 s35, v75, 3 -; GFX11-NEXT: v_readlane_b32 s34, v75, 2 -; GFX11-NEXT: v_readlane_b32 s31, v75, 1 -; GFX11-NEXT: v_readlane_b32 s30, v75, 0 +; GFX11-NEXT: v_readlane_b32 s30, v76, 7 +; GFX11-NEXT: v_readlane_b32 s31, v76, 8 +; GFX11-NEXT: v_readlane_b32 s104, v76, 6 +; GFX11-NEXT: v_readlane_b32 s103, v76, 5 +; GFX11-NEXT: v_readlane_b32 s102, v76, 4 +; GFX11-NEXT: v_readlane_b32 s101, v76, 3 +; GFX11-NEXT: v_readlane_b32 s100, v76, 2 +; GFX11-NEXT: v_readlane_b32 s99, v76, 1 +; GFX11-NEXT: v_readlane_b32 s98, v76, 0 +; GFX11-NEXT: v_readlane_b32 s97, v75, 31 +; GFX11-NEXT: v_readlane_b32 s96, v75, 30 +; GFX11-NEXT: v_readlane_b32 s87, v75, 29 +; GFX11-NEXT: v_readlane_b32 s86, v75, 28 +; GFX11-NEXT: v_readlane_b32 s85, v75, 27 +; GFX11-NEXT: v_readlane_b32 s84, v75, 26 +; GFX11-NEXT: v_readlane_b32 s83, v75, 25 +; GFX11-NEXT: v_readlane_b32 s82, v75, 24 +; GFX11-NEXT: v_readlane_b32 s81, v75, 23 +; GFX11-NEXT: v_readlane_b32 s80, v75, 22 +; GFX11-NEXT: v_readlane_b32 s71, v75, 21 +; GFX11-NEXT: v_readlane_b32 s70, v75, 20 +; GFX11-NEXT: v_readlane_b32 s69, v75, 19 +; GFX11-NEXT: v_readlane_b32 s68, v75, 18 +; GFX11-NEXT: v_readlane_b32 s67, v75, 17 +; GFX11-NEXT: v_readlane_b32 s66, v75, 16 +; GFX11-NEXT: v_readlane_b32 s65, v75, 15 +; GFX11-NEXT: v_readlane_b32 s64, v75, 14 +; GFX11-NEXT: v_readlane_b32 s55, v75, 13 +; GFX11-NEXT: v_readlane_b32 s54, v75, 12 +; GFX11-NEXT: v_readlane_b32 s53, v75, 11 +; GFX11-NEXT: v_readlane_b32 s52, v75, 10 +; GFX11-NEXT: v_readlane_b32 s51, v75, 9 +; GFX11-NEXT: v_readlane_b32 s50, v75, 8 +; GFX11-NEXT: v_readlane_b32 s49, v75, 7 +; GFX11-NEXT: v_readlane_b32 s48, v75, 6 +; GFX11-NEXT: v_readlane_b32 s39, v75, 5 +; GFX11-NEXT: v_readlane_b32 s38, v75, 4 +; GFX11-NEXT: v_readlane_b32 s37, v75, 3 +; GFX11-NEXT: v_readlane_b32 s36, v75, 2 +; GFX11-NEXT: v_readlane_b32 s35, v75, 1 +; GFX11-NEXT: v_readlane_b32 s34, v75, 0 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:76 @@ -54428,56 +54908,105 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:592 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:588 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:584 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:580 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:576 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:572 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:568 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:564 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:560 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:556 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:552 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:548 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:544 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:540 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:536 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:532 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:528 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:524 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:520 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:516 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:512 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:508 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:504 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:500 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:496 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:492 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:488 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:484 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:480 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:468 ; GFX11-FAKE16-NEXT: s_clause 0x12 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:456 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:392 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -58749,45 +59278,83 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a, ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:476 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:472 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:468 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:464 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:460 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:456 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:452 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:448 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:444 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:440 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:436 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:432 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:428 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:424 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:420 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:416 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:412 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:408 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:404 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:400 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:396 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:392 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:388 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:384 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:380 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:376 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:372 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:368 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:364 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:360 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:356 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:352 ; GFX11-TRUE16-NEXT: s_clause 0x7 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:348 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:344 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:340 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:336 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:332 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:328 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:324 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:320 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -59690,45 +60257,83 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a, ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:468 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:456 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:392 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:388 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:384 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:380 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:376 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:372 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:368 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:364 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:360 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:356 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:352 ; GFX11-FAKE16-NEXT: s_clause 0x7 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:348 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:344 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:340 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:336 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:332 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:328 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:324 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:320 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -61535,44 +62140,57 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_writelane_b32 v63, s30, 0 -; SI-NEXT: v_writelane_b32 v63, s31, 1 -; SI-NEXT: v_writelane_b32 v63, s34, 2 -; SI-NEXT: v_writelane_b32 v63, s35, 3 -; SI-NEXT: v_writelane_b32 v63, s36, 4 -; SI-NEXT: v_writelane_b32 v63, s37, 5 -; SI-NEXT: v_writelane_b32 v63, s38, 6 -; SI-NEXT: v_writelane_b32 v63, s39, 7 -; SI-NEXT: v_writelane_b32 v63, s48, 8 -; SI-NEXT: v_writelane_b32 v63, s49, 9 -; SI-NEXT: v_writelane_b32 v63, s50, 10 -; SI-NEXT: v_writelane_b32 v63, s51, 11 -; SI-NEXT: v_writelane_b32 v63, s52, 12 -; SI-NEXT: v_writelane_b32 v63, s53, 13 -; SI-NEXT: v_writelane_b32 v63, s54, 14 -; SI-NEXT: v_writelane_b32 v63, s55, 15 -; SI-NEXT: v_writelane_b32 v63, s64, 16 -; SI-NEXT: v_writelane_b32 v63, s65, 17 -; SI-NEXT: v_writelane_b32 v63, s66, 18 -; SI-NEXT: v_writelane_b32 v63, s67, 19 -; SI-NEXT: v_writelane_b32 v63, s68, 20 -; SI-NEXT: v_writelane_b32 v63, s69, 21 -; SI-NEXT: v_writelane_b32 v63, s70, 22 -; SI-NEXT: v_writelane_b32 v63, s71, 23 -; SI-NEXT: v_writelane_b32 v63, s80, 24 -; SI-NEXT: v_writelane_b32 v63, s81, 25 -; SI-NEXT: v_writelane_b32 v63, s82, 26 -; SI-NEXT: v_writelane_b32 v63, s83, 27 -; SI-NEXT: v_writelane_b32 v63, s84, 28 -; SI-NEXT: v_writelane_b32 v63, s85, 29 -; SI-NEXT: v_writelane_b32 v63, s86, 30 -; SI-NEXT: v_writelane_b32 v63, s87, 31 -; SI-NEXT: v_writelane_b32 v63, s96, 32 -; SI-NEXT: v_writelane_b32 v63, s97, 33 -; SI-NEXT: v_writelane_b32 v63, s98, 34 +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_writelane_b32 v63, s34, 0 +; SI-NEXT: v_writelane_b32 v63, s35, 1 +; SI-NEXT: v_writelane_b32 v63, s36, 2 +; SI-NEXT: v_writelane_b32 v63, s37, 3 +; SI-NEXT: v_writelane_b32 v63, s38, 4 +; SI-NEXT: v_writelane_b32 v63, s39, 5 +; SI-NEXT: v_writelane_b32 v63, s48, 6 +; SI-NEXT: v_writelane_b32 v63, s49, 7 +; SI-NEXT: v_writelane_b32 v63, s50, 8 +; SI-NEXT: v_writelane_b32 v63, s51, 9 +; SI-NEXT: v_writelane_b32 v63, s52, 10 +; SI-NEXT: v_writelane_b32 v63, s53, 11 +; SI-NEXT: v_writelane_b32 v63, s54, 12 +; SI-NEXT: v_writelane_b32 v63, s55, 13 +; SI-NEXT: v_writelane_b32 v63, s64, 14 +; SI-NEXT: v_writelane_b32 v63, s65, 15 +; SI-NEXT: v_writelane_b32 v63, s66, 16 +; SI-NEXT: v_writelane_b32 v63, s67, 17 +; SI-NEXT: v_writelane_b32 v63, s68, 18 +; SI-NEXT: v_writelane_b32 v63, s69, 19 +; SI-NEXT: v_writelane_b32 v63, s70, 20 +; SI-NEXT: v_writelane_b32 v63, s71, 21 +; SI-NEXT: v_writelane_b32 v63, s80, 22 +; SI-NEXT: v_writelane_b32 v63, s81, 23 +; SI-NEXT: v_writelane_b32 v63, s82, 24 +; SI-NEXT: v_writelane_b32 v63, s83, 25 +; SI-NEXT: v_writelane_b32 v63, s84, 26 +; SI-NEXT: v_writelane_b32 v63, s85, 27 +; SI-NEXT: v_writelane_b32 v63, s86, 28 +; SI-NEXT: v_writelane_b32 v63, s87, 29 +; SI-NEXT: v_writelane_b32 v63, s96, 30 +; SI-NEXT: v_writelane_b32 v63, s97, 31 +; SI-NEXT: v_writelane_b32 v63, s98, 32 +; SI-NEXT: v_writelane_b32 v63, s99, 33 +; SI-NEXT: v_writelane_b32 v63, s30, 34 +; SI-NEXT: v_writelane_b32 v63, s31, 35 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v63, s99, 35 ; SI-NEXT: v_readfirstlane_b32 s6, v1 ; SI-NEXT: v_readfirstlane_b32 s7, v2 ; SI-NEXT: v_readfirstlane_b32 s8, v3 @@ -61592,20 +62210,6 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg ; SI-NEXT: v_readfirstlane_b32 s46, v17 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s47, v18 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB41_3 ; SI-NEXT: ; %bb.1: ; %cmp.false @@ -62140,42 +62744,42 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; SI-NEXT: v_readlane_b32 s99, v63, 35 -; SI-NEXT: v_readlane_b32 s98, v63, 34 -; SI-NEXT: v_readlane_b32 s97, v63, 33 -; SI-NEXT: v_readlane_b32 s96, v63, 32 -; SI-NEXT: v_readlane_b32 s87, v63, 31 -; SI-NEXT: v_readlane_b32 s86, v63, 30 -; SI-NEXT: v_readlane_b32 s85, v63, 29 -; SI-NEXT: v_readlane_b32 s84, v63, 28 -; SI-NEXT: v_readlane_b32 s83, v63, 27 -; SI-NEXT: v_readlane_b32 s82, v63, 26 -; SI-NEXT: v_readlane_b32 s81, v63, 25 -; SI-NEXT: v_readlane_b32 s80, v63, 24 -; SI-NEXT: v_readlane_b32 s71, v63, 23 -; SI-NEXT: v_readlane_b32 s70, v63, 22 -; SI-NEXT: v_readlane_b32 s69, v63, 21 -; SI-NEXT: v_readlane_b32 s68, v63, 20 -; SI-NEXT: v_readlane_b32 s67, v63, 19 -; SI-NEXT: v_readlane_b32 s66, v63, 18 -; SI-NEXT: v_readlane_b32 s65, v63, 17 -; SI-NEXT: v_readlane_b32 s64, v63, 16 -; SI-NEXT: v_readlane_b32 s55, v63, 15 -; SI-NEXT: v_readlane_b32 s54, v63, 14 -; SI-NEXT: v_readlane_b32 s53, v63, 13 -; SI-NEXT: v_readlane_b32 s52, v63, 12 -; SI-NEXT: v_readlane_b32 s51, v63, 11 -; SI-NEXT: v_readlane_b32 s50, v63, 10 -; SI-NEXT: v_readlane_b32 s49, v63, 9 -; SI-NEXT: v_readlane_b32 s48, v63, 8 -; SI-NEXT: v_readlane_b32 s39, v63, 7 -; SI-NEXT: v_readlane_b32 s38, v63, 6 -; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s36, v63, 4 -; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: v_readlane_b32 s30, v63, 34 +; SI-NEXT: v_readlane_b32 s31, v63, 35 +; SI-NEXT: v_readlane_b32 s99, v63, 33 +; SI-NEXT: v_readlane_b32 s98, v63, 32 +; SI-NEXT: v_readlane_b32 s97, v63, 31 +; SI-NEXT: v_readlane_b32 s96, v63, 30 +; SI-NEXT: v_readlane_b32 s87, v63, 29 +; SI-NEXT: v_readlane_b32 s86, v63, 28 +; SI-NEXT: v_readlane_b32 s85, v63, 27 +; SI-NEXT: v_readlane_b32 s84, v63, 26 +; SI-NEXT: v_readlane_b32 s83, v63, 25 +; SI-NEXT: v_readlane_b32 s82, v63, 24 +; SI-NEXT: v_readlane_b32 s81, v63, 23 +; SI-NEXT: v_readlane_b32 s80, v63, 22 +; SI-NEXT: v_readlane_b32 s71, v63, 21 +; SI-NEXT: v_readlane_b32 s70, v63, 20 +; SI-NEXT: v_readlane_b32 s69, v63, 19 +; SI-NEXT: v_readlane_b32 s68, v63, 18 +; SI-NEXT: v_readlane_b32 s67, v63, 17 +; SI-NEXT: v_readlane_b32 s66, v63, 16 +; SI-NEXT: v_readlane_b32 s65, v63, 15 +; SI-NEXT: v_readlane_b32 s64, v63, 14 +; SI-NEXT: v_readlane_b32 s55, v63, 13 +; SI-NEXT: v_readlane_b32 s54, v63, 12 +; SI-NEXT: v_readlane_b32 s53, v63, 11 +; SI-NEXT: v_readlane_b32 s52, v63, 10 +; SI-NEXT: v_readlane_b32 s51, v63, 9 +; SI-NEXT: v_readlane_b32 s50, v63, 8 +; SI-NEXT: v_readlane_b32 s49, v63, 7 +; SI-NEXT: v_readlane_b32 s48, v63, 6 +; SI-NEXT: v_readlane_b32 s39, v63, 5 +; SI-NEXT: v_readlane_b32 s38, v63, 4 +; SI-NEXT: v_readlane_b32 s37, v63, 3 +; SI-NEXT: v_readlane_b32 s36, v63, 2 +; SI-NEXT: v_readlane_b32 s35, v63, 1 +; SI-NEXT: v_readlane_b32 s34, v63, 0 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 @@ -64241,20 +64845,35 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4 @@ -67290,81 +67909,149 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg ; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v32f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28 ; GFX11-TRUE16-NEXT: s_clause 0x6 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8 @@ -68264,83 +68951,153 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg ; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v32f32_scalar: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164 ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36 ; GFX11-FAKE16-NEXT: s_clause 0x8 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7 @@ -70092,6 +70849,22 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a, ; SI-LABEL: bitcast_v32f32_to_v64f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: v_readfirstlane_b32 s47, v1 ; SI-NEXT: v_readfirstlane_b32 s46, v2 @@ -70112,22 +70885,6 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a, ; SI-NEXT: v_readfirstlane_b32 s6, v17 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v18 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB45_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -72812,84 +73569,155 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a, ; GFX11-LABEL: bitcast_v64f16_to_v32f32_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 ; GFX11-NEXT: s_clause 0x9 ; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v185, s32 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 ; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 ; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 @@ -73625,22 +74453,6 @@ define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a, ; SI-LABEL: bitcast_v32f32_to_v64i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_mov_b32_e32 v31, s16 -; SI-NEXT: v_mov_b32_e32 v32, s17 -; SI-NEXT: v_mov_b32_e32 v29, s18 -; SI-NEXT: v_mov_b32_e32 v30, s19 -; SI-NEXT: v_mov_b32_e32 v27, s20 -; SI-NEXT: v_mov_b32_e32 v28, s21 -; SI-NEXT: v_mov_b32_e32 v25, s22 -; SI-NEXT: v_mov_b32_e32 v26, s23 -; SI-NEXT: v_mov_b32_e32 v23, s24 -; SI-NEXT: v_mov_b32_e32 v24, s25 -; SI-NEXT: v_mov_b32_e32 v21, s26 -; SI-NEXT: v_mov_b32_e32 v22, s27 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_mov_b32_e32 v19, s28 -; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -73657,6 +74469,22 @@ define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a, ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 +; SI-NEXT: v_mov_b32_e32 v31, s16 +; SI-NEXT: v_mov_b32_e32 v32, s17 +; SI-NEXT: v_mov_b32_e32 v29, s18 +; SI-NEXT: v_mov_b32_e32 v30, s19 +; SI-NEXT: v_mov_b32_e32 v27, s20 +; SI-NEXT: v_mov_b32_e32 v28, s21 +; SI-NEXT: v_mov_b32_e32 v25, s22 +; SI-NEXT: v_mov_b32_e32 v26, s23 +; SI-NEXT: v_mov_b32_e32 v23, s24 +; SI-NEXT: v_mov_b32_e32 v24, s25 +; SI-NEXT: v_mov_b32_e32 v21, s26 +; SI-NEXT: v_mov_b32_e32 v22, s27 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_mov_b32_e32 v19, s28 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: s_cbranch_scc0 .LBB49_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_lshr_b64 v[36:37], v[17:18], 16 @@ -75816,84 +76644,155 @@ define inreg <32 x float> @bitcast_v64i16_to_v32f32_scalar(<64 x i16> inreg %a, ; GFX11-LABEL: bitcast_v64i16_to_v32f32_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 ; GFX11-NEXT: s_clause 0x9 ; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v185, s32 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 ; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 ; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 @@ -80714,24 +81613,43 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x13 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12 ; GFX11-FAKE16-NEXT: s_clause 0x2 ; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8 @@ -81431,42 +82349,43 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_writelane_b32 v20, s69, 21 -; SI-NEXT: v_writelane_b32 v20, s70, 22 -; SI-NEXT: v_writelane_b32 v20, s71, 23 -; SI-NEXT: v_writelane_b32 v20, s80, 24 -; SI-NEXT: v_writelane_b32 v20, s81, 25 -; SI-NEXT: v_writelane_b32 v20, s82, 26 -; SI-NEXT: v_writelane_b32 v20, s83, 27 -; SI-NEXT: v_writelane_b32 v20, s84, 28 -; SI-NEXT: v_writelane_b32 v20, s85, 29 -; SI-NEXT: v_writelane_b32 v20, s86, 30 -; SI-NEXT: v_writelane_b32 v20, s87, 31 -; SI-NEXT: v_writelane_b32 v20, s96, 32 -; SI-NEXT: v_writelane_b32 v20, s97, 33 +; SI-NEXT: v_writelane_b32 v20, s34, 0 +; SI-NEXT: v_writelane_b32 v20, s35, 1 +; SI-NEXT: v_writelane_b32 v20, s36, 2 +; SI-NEXT: v_writelane_b32 v20, s37, 3 +; SI-NEXT: v_writelane_b32 v20, s38, 4 +; SI-NEXT: v_writelane_b32 v20, s39, 5 +; SI-NEXT: v_writelane_b32 v20, s48, 6 +; SI-NEXT: v_writelane_b32 v20, s49, 7 +; SI-NEXT: v_writelane_b32 v20, s50, 8 +; SI-NEXT: v_writelane_b32 v20, s51, 9 +; SI-NEXT: v_writelane_b32 v20, s52, 10 +; SI-NEXT: v_writelane_b32 v20, s53, 11 +; SI-NEXT: v_writelane_b32 v20, s54, 12 +; SI-NEXT: v_writelane_b32 v20, s55, 13 +; SI-NEXT: v_writelane_b32 v20, s64, 14 +; SI-NEXT: v_writelane_b32 v20, s65, 15 +; SI-NEXT: v_writelane_b32 v20, s66, 16 +; SI-NEXT: v_writelane_b32 v20, s67, 17 +; SI-NEXT: v_writelane_b32 v20, s68, 18 +; SI-NEXT: v_writelane_b32 v20, s69, 19 +; SI-NEXT: v_writelane_b32 v20, s70, 20 +; SI-NEXT: v_writelane_b32 v20, s71, 21 +; SI-NEXT: v_writelane_b32 v20, s80, 22 +; SI-NEXT: v_writelane_b32 v20, s81, 23 +; SI-NEXT: v_writelane_b32 v20, s82, 24 +; SI-NEXT: v_writelane_b32 v20, s83, 25 +; SI-NEXT: v_writelane_b32 v20, s84, 26 +; SI-NEXT: v_writelane_b32 v20, s85, 27 +; SI-NEXT: v_writelane_b32 v20, s86, 28 +; SI-NEXT: v_writelane_b32 v20, s87, 29 +; SI-NEXT: v_writelane_b32 v20, s96, 30 +; SI-NEXT: v_writelane_b32 v20, s97, 31 +; SI-NEXT: v_writelane_b32 v20, s98, 32 +; SI-NEXT: v_writelane_b32 v20, s99, 33 +; SI-NEXT: v_writelane_b32 v20, s30, 34 +; SI-NEXT: v_writelane_b32 v20, s31, 35 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s98, 34 ; SI-NEXT: v_readfirstlane_b32 s44, v1 ; SI-NEXT: v_readfirstlane_b32 s45, v2 ; SI-NEXT: v_readfirstlane_b32 s42, v3 @@ -81486,7 +82405,6 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v17 ; SI-NEXT: s_and_b64 s[46:47], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v18 -; SI-NEXT: v_writelane_b32 v20, s99, 35 ; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane ; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB57_4 @@ -82356,6 +83274,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v20, 34 ; SI-NEXT: v_readlane_b32 s19, v22, 11 ; SI-NEXT: v_readlane_b32 s17, v22, 17 ; SI-NEXT: v_readlane_b32 s15, v22, 23 @@ -82363,42 +83282,41 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: v_readlane_b32 s11, v22, 35 ; SI-NEXT: v_readlane_b32 s9, v22, 39 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v20, 35 -; SI-NEXT: v_readlane_b32 s98, v20, 34 -; SI-NEXT: v_readlane_b32 s97, v20, 33 -; SI-NEXT: v_readlane_b32 s96, v20, 32 -; SI-NEXT: v_readlane_b32 s87, v20, 31 -; SI-NEXT: v_readlane_b32 s86, v20, 30 -; SI-NEXT: v_readlane_b32 s85, v20, 29 -; SI-NEXT: v_readlane_b32 s84, v20, 28 -; SI-NEXT: v_readlane_b32 s83, v20, 27 -; SI-NEXT: v_readlane_b32 s82, v20, 26 -; SI-NEXT: v_readlane_b32 s81, v20, 25 -; SI-NEXT: v_readlane_b32 s80, v20, 24 -; SI-NEXT: v_readlane_b32 s71, v20, 23 -; SI-NEXT: v_readlane_b32 s70, v20, 22 -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s31, v20, 35 +; SI-NEXT: v_readlane_b32 s99, v20, 33 +; SI-NEXT: v_readlane_b32 s98, v20, 32 +; SI-NEXT: v_readlane_b32 s97, v20, 31 +; SI-NEXT: v_readlane_b32 s96, v20, 30 +; SI-NEXT: v_readlane_b32 s87, v20, 29 +; SI-NEXT: v_readlane_b32 s86, v20, 28 +; SI-NEXT: v_readlane_b32 s85, v20, 27 +; SI-NEXT: v_readlane_b32 s84, v20, 26 +; SI-NEXT: v_readlane_b32 s83, v20, 25 +; SI-NEXT: v_readlane_b32 s82, v20, 24 +; SI-NEXT: v_readlane_b32 s81, v20, 23 +; SI-NEXT: v_readlane_b32 s80, v20, 22 +; SI-NEXT: v_readlane_b32 s71, v20, 21 +; SI-NEXT: v_readlane_b32 s70, v20, 20 +; SI-NEXT: v_readlane_b32 s69, v20, 19 +; SI-NEXT: v_readlane_b32 s68, v20, 18 +; SI-NEXT: v_readlane_b32 s67, v20, 17 +; SI-NEXT: v_readlane_b32 s66, v20, 16 +; SI-NEXT: v_readlane_b32 s65, v20, 15 +; SI-NEXT: v_readlane_b32 s64, v20, 14 +; SI-NEXT: v_readlane_b32 s55, v20, 13 +; SI-NEXT: v_readlane_b32 s54, v20, 12 +; SI-NEXT: v_readlane_b32 s53, v20, 11 +; SI-NEXT: v_readlane_b32 s52, v20, 10 +; SI-NEXT: v_readlane_b32 s51, v20, 9 +; SI-NEXT: v_readlane_b32 s50, v20, 8 +; SI-NEXT: v_readlane_b32 s49, v20, 7 +; SI-NEXT: v_readlane_b32 s48, v20, 6 +; SI-NEXT: v_readlane_b32 s39, v20, 5 +; SI-NEXT: v_readlane_b32 s38, v20, 4 +; SI-NEXT: v_readlane_b32 s37, v20, 3 +; SI-NEXT: v_readlane_b32 s36, v20, 2 +; SI-NEXT: v_readlane_b32 s35, v20, 1 +; SI-NEXT: v_readlane_b32 s34, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -82595,38 +83513,39 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v20, s30, 0 -; VI-NEXT: v_writelane_b32 v20, s31, 1 -; VI-NEXT: v_writelane_b32 v20, s34, 2 -; VI-NEXT: v_writelane_b32 v20, s35, 3 -; VI-NEXT: v_writelane_b32 v20, s36, 4 -; VI-NEXT: v_writelane_b32 v20, s37, 5 -; VI-NEXT: v_writelane_b32 v20, s38, 6 -; VI-NEXT: v_writelane_b32 v20, s39, 7 -; VI-NEXT: v_writelane_b32 v20, s48, 8 -; VI-NEXT: v_writelane_b32 v20, s49, 9 -; VI-NEXT: v_writelane_b32 v20, s50, 10 -; VI-NEXT: v_writelane_b32 v20, s51, 11 -; VI-NEXT: v_writelane_b32 v20, s52, 12 -; VI-NEXT: v_writelane_b32 v20, s53, 13 -; VI-NEXT: v_writelane_b32 v20, s54, 14 -; VI-NEXT: v_writelane_b32 v20, s55, 15 -; VI-NEXT: v_writelane_b32 v20, s64, 16 -; VI-NEXT: v_writelane_b32 v20, s65, 17 -; VI-NEXT: v_writelane_b32 v20, s66, 18 -; VI-NEXT: v_writelane_b32 v20, s67, 19 -; VI-NEXT: v_writelane_b32 v20, s68, 20 -; VI-NEXT: v_writelane_b32 v20, s69, 21 -; VI-NEXT: v_writelane_b32 v20, s70, 22 -; VI-NEXT: v_writelane_b32 v20, s71, 23 -; VI-NEXT: v_writelane_b32 v20, s80, 24 -; VI-NEXT: v_writelane_b32 v20, s81, 25 -; VI-NEXT: v_writelane_b32 v20, s82, 26 -; VI-NEXT: v_writelane_b32 v20, s83, 27 -; VI-NEXT: v_writelane_b32 v20, s84, 28 -; VI-NEXT: v_writelane_b32 v20, s85, 29 +; VI-NEXT: v_writelane_b32 v20, s34, 0 +; VI-NEXT: v_writelane_b32 v20, s35, 1 +; VI-NEXT: v_writelane_b32 v20, s36, 2 +; VI-NEXT: v_writelane_b32 v20, s37, 3 +; VI-NEXT: v_writelane_b32 v20, s38, 4 +; VI-NEXT: v_writelane_b32 v20, s39, 5 +; VI-NEXT: v_writelane_b32 v20, s48, 6 +; VI-NEXT: v_writelane_b32 v20, s49, 7 +; VI-NEXT: v_writelane_b32 v20, s50, 8 +; VI-NEXT: v_writelane_b32 v20, s51, 9 +; VI-NEXT: v_writelane_b32 v20, s52, 10 +; VI-NEXT: v_writelane_b32 v20, s53, 11 +; VI-NEXT: v_writelane_b32 v20, s54, 12 +; VI-NEXT: v_writelane_b32 v20, s55, 13 +; VI-NEXT: v_writelane_b32 v20, s64, 14 +; VI-NEXT: v_writelane_b32 v20, s65, 15 +; VI-NEXT: v_writelane_b32 v20, s66, 16 +; VI-NEXT: v_writelane_b32 v20, s67, 17 +; VI-NEXT: v_writelane_b32 v20, s68, 18 +; VI-NEXT: v_writelane_b32 v20, s69, 19 +; VI-NEXT: v_writelane_b32 v20, s70, 20 +; VI-NEXT: v_writelane_b32 v20, s71, 21 +; VI-NEXT: v_writelane_b32 v20, s80, 22 +; VI-NEXT: v_writelane_b32 v20, s81, 23 +; VI-NEXT: v_writelane_b32 v20, s82, 24 +; VI-NEXT: v_writelane_b32 v20, s83, 25 +; VI-NEXT: v_writelane_b32 v20, s84, 26 +; VI-NEXT: v_writelane_b32 v20, s85, 27 +; VI-NEXT: v_writelane_b32 v20, s86, 28 +; VI-NEXT: v_writelane_b32 v20, s87, 29 +; VI-NEXT: v_writelane_b32 v20, s30, 30 +; VI-NEXT: v_writelane_b32 v20, s31, 31 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v20, s86, 30 ; VI-NEXT: v_readfirstlane_b32 s44, v1 ; VI-NEXT: v_readfirstlane_b32 s45, v2 ; VI-NEXT: v_readfirstlane_b32 s42, v3 @@ -82646,7 +83565,6 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s4, v17 ; VI-NEXT: s_and_b64 s[46:47], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v18 -; VI-NEXT: v_writelane_b32 v20, s87, 31 ; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB57_4 ; VI-NEXT: ; %bb.1: ; %cmp.false @@ -83435,43 +84353,43 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0 ; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_readlane_b32 s30, v20, 30 ; VI-NEXT: v_readlane_b32 s15, v21, 1 ; VI-NEXT: v_readlane_b32 s13, v21, 3 ; VI-NEXT: v_readlane_b32 s11, v21, 5 ; VI-NEXT: v_readlane_b32 s9, v21, 7 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; VI-NEXT: v_readlane_b32 s87, v20, 31 -; VI-NEXT: v_readlane_b32 s86, v20, 30 -; VI-NEXT: v_readlane_b32 s85, v20, 29 -; VI-NEXT: v_readlane_b32 s84, v20, 28 -; VI-NEXT: v_readlane_b32 s83, v20, 27 -; VI-NEXT: v_readlane_b32 s82, v20, 26 -; VI-NEXT: v_readlane_b32 s81, v20, 25 -; VI-NEXT: v_readlane_b32 s80, v20, 24 -; VI-NEXT: v_readlane_b32 s71, v20, 23 -; VI-NEXT: v_readlane_b32 s70, v20, 22 -; VI-NEXT: v_readlane_b32 s69, v20, 21 -; VI-NEXT: v_readlane_b32 s68, v20, 20 -; VI-NEXT: v_readlane_b32 s67, v20, 19 -; VI-NEXT: v_readlane_b32 s66, v20, 18 -; VI-NEXT: v_readlane_b32 s65, v20, 17 -; VI-NEXT: v_readlane_b32 s64, v20, 16 -; VI-NEXT: v_readlane_b32 s55, v20, 15 -; VI-NEXT: v_readlane_b32 s54, v20, 14 -; VI-NEXT: v_readlane_b32 s53, v20, 13 -; VI-NEXT: v_readlane_b32 s52, v20, 12 -; VI-NEXT: v_readlane_b32 s51, v20, 11 -; VI-NEXT: v_readlane_b32 s50, v20, 10 -; VI-NEXT: v_readlane_b32 s49, v20, 9 -; VI-NEXT: v_readlane_b32 s48, v20, 8 -; VI-NEXT: v_readlane_b32 s39, v20, 7 -; VI-NEXT: v_readlane_b32 s38, v20, 6 -; VI-NEXT: v_readlane_b32 s37, v20, 5 -; VI-NEXT: v_readlane_b32 s36, v20, 4 -; VI-NEXT: v_readlane_b32 s35, v20, 3 -; VI-NEXT: v_readlane_b32 s34, v20, 2 -; VI-NEXT: v_readlane_b32 s31, v20, 1 -; VI-NEXT: v_readlane_b32 s30, v20, 0 +; VI-NEXT: v_readlane_b32 s31, v20, 31 +; VI-NEXT: v_readlane_b32 s87, v20, 29 +; VI-NEXT: v_readlane_b32 s86, v20, 28 +; VI-NEXT: v_readlane_b32 s85, v20, 27 +; VI-NEXT: v_readlane_b32 s84, v20, 26 +; VI-NEXT: v_readlane_b32 s83, v20, 25 +; VI-NEXT: v_readlane_b32 s82, v20, 24 +; VI-NEXT: v_readlane_b32 s81, v20, 23 +; VI-NEXT: v_readlane_b32 s80, v20, 22 +; VI-NEXT: v_readlane_b32 s71, v20, 21 +; VI-NEXT: v_readlane_b32 s70, v20, 20 +; VI-NEXT: v_readlane_b32 s69, v20, 19 +; VI-NEXT: v_readlane_b32 s68, v20, 18 +; VI-NEXT: v_readlane_b32 s67, v20, 17 +; VI-NEXT: v_readlane_b32 s66, v20, 16 +; VI-NEXT: v_readlane_b32 s65, v20, 15 +; VI-NEXT: v_readlane_b32 s64, v20, 14 +; VI-NEXT: v_readlane_b32 s55, v20, 13 +; VI-NEXT: v_readlane_b32 s54, v20, 12 +; VI-NEXT: v_readlane_b32 s53, v20, 11 +; VI-NEXT: v_readlane_b32 s52, v20, 10 +; VI-NEXT: v_readlane_b32 s51, v20, 9 +; VI-NEXT: v_readlane_b32 s50, v20, 8 +; VI-NEXT: v_readlane_b32 s49, v20, 7 +; VI-NEXT: v_readlane_b32 s48, v20, 6 +; VI-NEXT: v_readlane_b32 s39, v20, 5 +; VI-NEXT: v_readlane_b32 s38, v20, 4 +; VI-NEXT: v_readlane_b32 s37, v20, 3 +; VI-NEXT: v_readlane_b32 s36, v20, 2 +; VI-NEXT: v_readlane_b32 s35, v20, 1 +; VI-NEXT: v_readlane_b32 s34, v20, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -83644,42 +84562,43 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v20, s30, 0 -; GFX9-NEXT: v_writelane_b32 v20, s31, 1 -; GFX9-NEXT: v_writelane_b32 v20, s34, 2 -; GFX9-NEXT: v_writelane_b32 v20, s35, 3 -; GFX9-NEXT: v_writelane_b32 v20, s36, 4 -; GFX9-NEXT: v_writelane_b32 v20, s37, 5 -; GFX9-NEXT: v_writelane_b32 v20, s38, 6 -; GFX9-NEXT: v_writelane_b32 v20, s39, 7 -; GFX9-NEXT: v_writelane_b32 v20, s48, 8 -; GFX9-NEXT: v_writelane_b32 v20, s49, 9 -; GFX9-NEXT: v_writelane_b32 v20, s50, 10 -; GFX9-NEXT: v_writelane_b32 v20, s51, 11 -; GFX9-NEXT: v_writelane_b32 v20, s52, 12 -; GFX9-NEXT: v_writelane_b32 v20, s53, 13 -; GFX9-NEXT: v_writelane_b32 v20, s54, 14 -; GFX9-NEXT: v_writelane_b32 v20, s55, 15 -; GFX9-NEXT: v_writelane_b32 v20, s64, 16 -; GFX9-NEXT: v_writelane_b32 v20, s65, 17 -; GFX9-NEXT: v_writelane_b32 v20, s66, 18 -; GFX9-NEXT: v_writelane_b32 v20, s67, 19 -; GFX9-NEXT: v_writelane_b32 v20, s68, 20 -; GFX9-NEXT: v_writelane_b32 v20, s69, 21 -; GFX9-NEXT: v_writelane_b32 v20, s70, 22 -; GFX9-NEXT: v_writelane_b32 v20, s71, 23 -; GFX9-NEXT: v_writelane_b32 v20, s80, 24 -; GFX9-NEXT: v_writelane_b32 v20, s81, 25 -; GFX9-NEXT: v_writelane_b32 v20, s82, 26 -; GFX9-NEXT: v_writelane_b32 v20, s83, 27 -; GFX9-NEXT: v_writelane_b32 v20, s84, 28 -; GFX9-NEXT: v_writelane_b32 v20, s85, 29 -; GFX9-NEXT: v_writelane_b32 v20, s86, 30 -; GFX9-NEXT: v_writelane_b32 v20, s87, 31 -; GFX9-NEXT: v_writelane_b32 v20, s96, 32 -; GFX9-NEXT: v_writelane_b32 v20, s97, 33 +; GFX9-NEXT: v_writelane_b32 v20, s34, 0 +; GFX9-NEXT: v_writelane_b32 v20, s35, 1 +; GFX9-NEXT: v_writelane_b32 v20, s36, 2 +; GFX9-NEXT: v_writelane_b32 v20, s37, 3 +; GFX9-NEXT: v_writelane_b32 v20, s38, 4 +; GFX9-NEXT: v_writelane_b32 v20, s39, 5 +; GFX9-NEXT: v_writelane_b32 v20, s48, 6 +; GFX9-NEXT: v_writelane_b32 v20, s49, 7 +; GFX9-NEXT: v_writelane_b32 v20, s50, 8 +; GFX9-NEXT: v_writelane_b32 v20, s51, 9 +; GFX9-NEXT: v_writelane_b32 v20, s52, 10 +; GFX9-NEXT: v_writelane_b32 v20, s53, 11 +; GFX9-NEXT: v_writelane_b32 v20, s54, 12 +; GFX9-NEXT: v_writelane_b32 v20, s55, 13 +; GFX9-NEXT: v_writelane_b32 v20, s64, 14 +; GFX9-NEXT: v_writelane_b32 v20, s65, 15 +; GFX9-NEXT: v_writelane_b32 v20, s66, 16 +; GFX9-NEXT: v_writelane_b32 v20, s67, 17 +; GFX9-NEXT: v_writelane_b32 v20, s68, 18 +; GFX9-NEXT: v_writelane_b32 v20, s69, 19 +; GFX9-NEXT: v_writelane_b32 v20, s70, 20 +; GFX9-NEXT: v_writelane_b32 v20, s71, 21 +; GFX9-NEXT: v_writelane_b32 v20, s80, 22 +; GFX9-NEXT: v_writelane_b32 v20, s81, 23 +; GFX9-NEXT: v_writelane_b32 v20, s82, 24 +; GFX9-NEXT: v_writelane_b32 v20, s83, 25 +; GFX9-NEXT: v_writelane_b32 v20, s84, 26 +; GFX9-NEXT: v_writelane_b32 v20, s85, 27 +; GFX9-NEXT: v_writelane_b32 v20, s86, 28 +; GFX9-NEXT: v_writelane_b32 v20, s87, 29 +; GFX9-NEXT: v_writelane_b32 v20, s96, 30 +; GFX9-NEXT: v_writelane_b32 v20, s97, 31 +; GFX9-NEXT: v_writelane_b32 v20, s98, 32 +; GFX9-NEXT: v_writelane_b32 v20, s99, 33 +; GFX9-NEXT: v_writelane_b32 v20, s30, 34 +; GFX9-NEXT: v_writelane_b32 v20, s31, 35 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; GFX9-NEXT: v_writelane_b32 v20, s98, 34 ; GFX9-NEXT: v_readfirstlane_b32 s44, v1 ; GFX9-NEXT: v_readfirstlane_b32 s45, v2 ; GFX9-NEXT: v_readfirstlane_b32 s42, v3 @@ -83699,7 +84618,6 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: v_readfirstlane_b32 s4, v17 ; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v18 -; GFX9-NEXT: v_writelane_b32 v20, s99, 35 ; GFX9-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB57_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false @@ -84433,44 +85351,44 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s4, s4, s5 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_readlane_b32 s30, v20, 34 ; GFX9-NEXT: v_readlane_b32 s9, v21, 1 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124 -; GFX9-NEXT: v_readlane_b32 s99, v20, 35 -; GFX9-NEXT: v_readlane_b32 s98, v20, 34 -; GFX9-NEXT: v_readlane_b32 s97, v20, 33 -; GFX9-NEXT: v_readlane_b32 s96, v20, 32 -; GFX9-NEXT: v_readlane_b32 s87, v20, 31 -; GFX9-NEXT: v_readlane_b32 s86, v20, 30 -; GFX9-NEXT: v_readlane_b32 s85, v20, 29 -; GFX9-NEXT: v_readlane_b32 s84, v20, 28 -; GFX9-NEXT: v_readlane_b32 s83, v20, 27 -; GFX9-NEXT: v_readlane_b32 s82, v20, 26 -; GFX9-NEXT: v_readlane_b32 s81, v20, 25 -; GFX9-NEXT: v_readlane_b32 s80, v20, 24 -; GFX9-NEXT: v_readlane_b32 s71, v20, 23 -; GFX9-NEXT: v_readlane_b32 s70, v20, 22 -; GFX9-NEXT: v_readlane_b32 s69, v20, 21 -; GFX9-NEXT: v_readlane_b32 s68, v20, 20 -; GFX9-NEXT: v_readlane_b32 s67, v20, 19 -; GFX9-NEXT: v_readlane_b32 s66, v20, 18 -; GFX9-NEXT: v_readlane_b32 s65, v20, 17 -; GFX9-NEXT: v_readlane_b32 s64, v20, 16 -; GFX9-NEXT: v_readlane_b32 s55, v20, 15 -; GFX9-NEXT: v_readlane_b32 s54, v20, 14 -; GFX9-NEXT: v_readlane_b32 s53, v20, 13 -; GFX9-NEXT: v_readlane_b32 s52, v20, 12 -; GFX9-NEXT: v_readlane_b32 s51, v20, 11 -; GFX9-NEXT: v_readlane_b32 s50, v20, 10 -; GFX9-NEXT: v_readlane_b32 s49, v20, 9 -; GFX9-NEXT: v_readlane_b32 s48, v20, 8 -; GFX9-NEXT: v_readlane_b32 s39, v20, 7 -; GFX9-NEXT: v_readlane_b32 s38, v20, 6 -; GFX9-NEXT: v_readlane_b32 s37, v20, 5 -; GFX9-NEXT: v_readlane_b32 s36, v20, 4 -; GFX9-NEXT: v_readlane_b32 s35, v20, 3 -; GFX9-NEXT: v_readlane_b32 s34, v20, 2 -; GFX9-NEXT: v_readlane_b32 s31, v20, 1 -; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: v_readlane_b32 s31, v20, 35 +; GFX9-NEXT: v_readlane_b32 s99, v20, 33 +; GFX9-NEXT: v_readlane_b32 s98, v20, 32 +; GFX9-NEXT: v_readlane_b32 s97, v20, 31 +; GFX9-NEXT: v_readlane_b32 s96, v20, 30 +; GFX9-NEXT: v_readlane_b32 s87, v20, 29 +; GFX9-NEXT: v_readlane_b32 s86, v20, 28 +; GFX9-NEXT: v_readlane_b32 s85, v20, 27 +; GFX9-NEXT: v_readlane_b32 s84, v20, 26 +; GFX9-NEXT: v_readlane_b32 s83, v20, 25 +; GFX9-NEXT: v_readlane_b32 s82, v20, 24 +; GFX9-NEXT: v_readlane_b32 s81, v20, 23 +; GFX9-NEXT: v_readlane_b32 s80, v20, 22 +; GFX9-NEXT: v_readlane_b32 s71, v20, 21 +; GFX9-NEXT: v_readlane_b32 s70, v20, 20 +; GFX9-NEXT: v_readlane_b32 s69, v20, 19 +; GFX9-NEXT: v_readlane_b32 s68, v20, 18 +; GFX9-NEXT: v_readlane_b32 s67, v20, 17 +; GFX9-NEXT: v_readlane_b32 s66, v20, 16 +; GFX9-NEXT: v_readlane_b32 s65, v20, 15 +; GFX9-NEXT: v_readlane_b32 s64, v20, 14 +; GFX9-NEXT: v_readlane_b32 s55, v20, 13 +; GFX9-NEXT: v_readlane_b32 s54, v20, 12 +; GFX9-NEXT: v_readlane_b32 s53, v20, 11 +; GFX9-NEXT: v_readlane_b32 s52, v20, 10 +; GFX9-NEXT: v_readlane_b32 s51, v20, 9 +; GFX9-NEXT: v_readlane_b32 s50, v20, 8 +; GFX9-NEXT: v_readlane_b32 s49, v20, 7 +; GFX9-NEXT: v_readlane_b32 s48, v20, 6 +; GFX9-NEXT: v_readlane_b32 s39, v20, 5 +; GFX9-NEXT: v_readlane_b32 s38, v20, 4 +; GFX9-NEXT: v_readlane_b32 s37, v20, 3 +; GFX9-NEXT: v_readlane_b32 s36, v20, 2 +; GFX9-NEXT: v_readlane_b32 s35, v20, 1 +; GFX9-NEXT: v_readlane_b32 s34, v20, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -84633,70 +85551,73 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v16, s32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v17, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v18, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:12 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v16, s30, 0 -; GFX11-NEXT: v_writelane_b32 v17, s96, 0 +; GFX11-NEXT: v_writelane_b32 v16, s34, 0 +; GFX11-NEXT: v_writelane_b32 v16, s35, 1 +; GFX11-NEXT: v_writelane_b32 v16, s36, 2 +; GFX11-NEXT: v_writelane_b32 v16, s37, 3 +; GFX11-NEXT: v_writelane_b32 v16, s38, 4 +; GFX11-NEXT: v_writelane_b32 v16, s39, 5 +; GFX11-NEXT: v_writelane_b32 v16, s48, 6 +; GFX11-NEXT: v_writelane_b32 v16, s49, 7 +; GFX11-NEXT: v_writelane_b32 v16, s50, 8 +; GFX11-NEXT: v_writelane_b32 v16, s51, 9 +; GFX11-NEXT: v_writelane_b32 v16, s52, 10 +; GFX11-NEXT: v_writelane_b32 v16, s53, 11 +; GFX11-NEXT: v_writelane_b32 v16, s54, 12 +; GFX11-NEXT: v_writelane_b32 v16, s55, 13 +; GFX11-NEXT: v_writelane_b32 v16, s64, 14 +; GFX11-NEXT: v_writelane_b32 v16, s65, 15 +; GFX11-NEXT: v_writelane_b32 v16, s66, 16 +; GFX11-NEXT: v_writelane_b32 v16, s67, 17 +; GFX11-NEXT: v_writelane_b32 v16, s68, 18 +; GFX11-NEXT: v_writelane_b32 v16, s69, 19 +; GFX11-NEXT: v_writelane_b32 v16, s70, 20 +; GFX11-NEXT: v_writelane_b32 v16, s71, 21 +; GFX11-NEXT: v_writelane_b32 v16, s80, 22 +; GFX11-NEXT: v_writelane_b32 v16, s81, 23 +; GFX11-NEXT: v_writelane_b32 v16, s82, 24 +; GFX11-NEXT: v_writelane_b32 v16, s83, 25 +; GFX11-NEXT: v_writelane_b32 v16, s84, 26 +; GFX11-NEXT: v_writelane_b32 v16, s85, 27 +; GFX11-NEXT: v_writelane_b32 v16, s86, 28 +; GFX11-NEXT: v_writelane_b32 v16, s87, 29 +; GFX11-NEXT: v_writelane_b32 v16, s96, 30 +; GFX11-NEXT: v_writelane_b32 v16, s97, 31 +; GFX11-NEXT: v_writelane_b32 v17, s98, 0 +; GFX11-NEXT: v_writelane_b32 v17, s99, 1 +; GFX11-NEXT: v_writelane_b32 v17, s100, 2 +; GFX11-NEXT: v_writelane_b32 v17, s101, 3 +; GFX11-NEXT: v_writelane_b32 v17, s102, 4 +; GFX11-NEXT: v_writelane_b32 v17, s103, 5 +; GFX11-NEXT: v_writelane_b32 v17, s104, 6 +; GFX11-NEXT: v_writelane_b32 v17, s30, 7 +; GFX11-NEXT: v_writelane_b32 v17, s31, 8 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 ; GFX11-NEXT: v_readfirstlane_b32 s40, v1 ; GFX11-NEXT: v_readfirstlane_b32 s41, v2 -; GFX11-NEXT: v_writelane_b32 v16, s31, 1 -; GFX11-NEXT: v_writelane_b32 v17, s97, 1 ; GFX11-NEXT: v_readfirstlane_b32 s14, v3 ; GFX11-NEXT: v_readfirstlane_b32 s15, v4 ; GFX11-NEXT: v_readfirstlane_b32 s12, v5 -; GFX11-NEXT: v_writelane_b32 v16, s34, 2 -; GFX11-NEXT: v_writelane_b32 v17, s98, 2 ; GFX11-NEXT: v_readfirstlane_b32 s13, v6 ; GFX11-NEXT: v_readfirstlane_b32 s10, v7 ; GFX11-NEXT: v_readfirstlane_b32 s11, v8 -; GFX11-NEXT: v_writelane_b32 v16, s35, 3 -; GFX11-NEXT: v_writelane_b32 v17, s99, 3 ; GFX11-NEXT: v_readfirstlane_b32 s8, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v10 ; GFX11-NEXT: v_readfirstlane_b32 s6, v11 -; GFX11-NEXT: v_writelane_b32 v16, s36, 4 -; GFX11-NEXT: v_writelane_b32 v17, s100, 4 ; GFX11-NEXT: v_readfirstlane_b32 s7, v12 ; GFX11-NEXT: v_readfirstlane_b32 s4, v13 ; GFX11-NEXT: v_readfirstlane_b32 s5, v14 -; GFX11-NEXT: v_writelane_b32 v16, s37, 5 -; GFX11-NEXT: v_writelane_b32 v17, s101, 5 ; GFX11-NEXT: s_mov_b32 s101, 0 ; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane ; GFX11-NEXT: ; implicit-def: $vgpr18 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v16, s38, 6 -; GFX11-NEXT: v_writelane_b32 v17, s102, 6 -; GFX11-NEXT: v_writelane_b32 v16, s39, 7 -; GFX11-NEXT: v_writelane_b32 v17, s103, 7 -; GFX11-NEXT: v_writelane_b32 v16, s48, 8 -; GFX11-NEXT: v_writelane_b32 v17, s104, 8 -; GFX11-NEXT: v_writelane_b32 v16, s49, 9 -; GFX11-NEXT: v_writelane_b32 v16, s50, 10 -; GFX11-NEXT: v_writelane_b32 v16, s51, 11 -; GFX11-NEXT: v_writelane_b32 v16, s52, 12 -; GFX11-NEXT: v_writelane_b32 v16, s53, 13 -; GFX11-NEXT: v_writelane_b32 v16, s54, 14 -; GFX11-NEXT: v_writelane_b32 v16, s55, 15 -; GFX11-NEXT: v_writelane_b32 v16, s64, 16 -; GFX11-NEXT: v_writelane_b32 v16, s65, 17 -; GFX11-NEXT: v_writelane_b32 v16, s66, 18 -; GFX11-NEXT: v_writelane_b32 v16, s67, 19 -; GFX11-NEXT: v_writelane_b32 v16, s68, 20 -; GFX11-NEXT: v_writelane_b32 v16, s69, 21 -; GFX11-NEXT: v_writelane_b32 v16, s70, 22 -; GFX11-NEXT: v_writelane_b32 v16, s71, 23 -; GFX11-NEXT: v_writelane_b32 v16, s80, 24 -; GFX11-NEXT: v_writelane_b32 v16, s81, 25 -; GFX11-NEXT: v_writelane_b32 v16, s82, 26 -; GFX11-NEXT: v_writelane_b32 v16, s83, 27 -; GFX11-NEXT: v_writelane_b32 v16, s84, 28 -; GFX11-NEXT: v_writelane_b32 v16, s85, 29 -; GFX11-NEXT: v_writelane_b32 v16, s86, 30 -; GFX11-NEXT: v_writelane_b32 v16, s87, 31 ; GFX11-NEXT: s_cbranch_scc0 .LBB57_2 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s43, s25, 8 @@ -85225,9 +86146,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: s_and_b32 s1, s1, 0xffff ; GFX11-NEXT: v_readlane_b32 s17, v19, 29 ; GFX11-NEXT: s_and_b32 s16, s16, 0xff -; GFX11-NEXT: v_readlane_b32 s100, v17, 4 +; GFX11-NEXT: v_readlane_b32 s30, v17, 7 ; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: v_readlane_b32 s99, v17, 3 +; GFX11-NEXT: v_readlane_b32 s31, v17, 8 ; GFX11-NEXT: s_or_b32 s2, s2, s3 ; GFX11-NEXT: s_and_b32 s3, s18, 0xff ; GFX11-NEXT: s_lshl_b32 s2, s2, 16 @@ -85261,7 +86182,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: s_or_b32 s16, s16, s17 ; GFX11-NEXT: v_readlane_b32 s17, v19, 21 ; GFX11-NEXT: s_lshl_b32 s16, s16, 16 -; GFX11-NEXT: v_readlane_b32 s98, v17, 2 +; GFX11-NEXT: v_readlane_b32 s100, v17, 2 ; GFX11-NEXT: s_or_b32 s3, s3, s16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 @@ -85281,12 +86202,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: s_or_b32 s0, s0, s1 ; GFX11-NEXT: s_and_b32 s1, s21, 0xff ; GFX11-NEXT: s_lshl_b32 s2, s2, 8 -; GFX11-NEXT: v_readlane_b32 s86, v16, 30 +; GFX11-NEXT: v_readlane_b32 s99, v17, 1 ; GFX11-NEXT: s_or_b32 s1, s1, s2 ; GFX11-NEXT: v_readlane_b32 s2, v19, 25 ; GFX11-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-NEXT: v_readlane_b32 s31, v16, 1 -; GFX11-NEXT: v_readlane_b32 s30, v16, 0 +; GFX11-NEXT: v_readlane_b32 s98, v17, 0 +; GFX11-NEXT: v_readlane_b32 s86, v16, 28 ; GFX11-NEXT: s_and_b32 s2, s2, 0xff ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_or_b32 s2, s2, s3 @@ -85323,9 +86244,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: s_lshl_b32 s3, s88, 8 ; GFX11-NEXT: s_and_b32 s16, s69, 0xff ; GFX11-NEXT: s_and_b32 s18, s72, 0xff -; GFX11-NEXT: v_readlane_b32 s97, v17, 1 +; GFX11-NEXT: v_readlane_b32 s97, v16, 31 ; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: v_readlane_b32 s69, v16, 21 +; GFX11-NEXT: v_readlane_b32 s69, v16, 19 ; GFX11-NEXT: s_or_b32 s1, s2, s3 ; GFX11-NEXT: v_readlane_b32 s3, v19, 16 ; GFX11-NEXT: s_and_b32 s2, s25, 0xff @@ -85532,39 +86453,39 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:80 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:96 ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:112 -; GFX11-NEXT: v_readlane_b32 s104, v17, 8 -; GFX11-NEXT: v_readlane_b32 s103, v17, 7 -; GFX11-NEXT: v_readlane_b32 s102, v17, 6 -; GFX11-NEXT: v_readlane_b32 s101, v17, 5 -; GFX11-NEXT: v_readlane_b32 s96, v17, 0 -; GFX11-NEXT: v_readlane_b32 s87, v16, 31 -; GFX11-NEXT: v_readlane_b32 s85, v16, 29 -; GFX11-NEXT: v_readlane_b32 s84, v16, 28 -; GFX11-NEXT: v_readlane_b32 s83, v16, 27 -; GFX11-NEXT: v_readlane_b32 s82, v16, 26 -; GFX11-NEXT: v_readlane_b32 s81, v16, 25 -; GFX11-NEXT: v_readlane_b32 s80, v16, 24 -; GFX11-NEXT: v_readlane_b32 s71, v16, 23 -; GFX11-NEXT: v_readlane_b32 s70, v16, 22 -; GFX11-NEXT: v_readlane_b32 s68, v16, 20 -; GFX11-NEXT: v_readlane_b32 s67, v16, 19 -; GFX11-NEXT: v_readlane_b32 s66, v16, 18 -; GFX11-NEXT: v_readlane_b32 s65, v16, 17 -; GFX11-NEXT: v_readlane_b32 s64, v16, 16 -; GFX11-NEXT: v_readlane_b32 s55, v16, 15 -; GFX11-NEXT: v_readlane_b32 s54, v16, 14 -; GFX11-NEXT: v_readlane_b32 s53, v16, 13 -; GFX11-NEXT: v_readlane_b32 s52, v16, 12 -; GFX11-NEXT: v_readlane_b32 s51, v16, 11 -; GFX11-NEXT: v_readlane_b32 s50, v16, 10 -; GFX11-NEXT: v_readlane_b32 s49, v16, 9 -; GFX11-NEXT: v_readlane_b32 s48, v16, 8 -; GFX11-NEXT: v_readlane_b32 s39, v16, 7 -; GFX11-NEXT: v_readlane_b32 s38, v16, 6 -; GFX11-NEXT: v_readlane_b32 s37, v16, 5 -; GFX11-NEXT: v_readlane_b32 s36, v16, 4 -; GFX11-NEXT: v_readlane_b32 s35, v16, 3 -; GFX11-NEXT: v_readlane_b32 s34, v16, 2 +; GFX11-NEXT: v_readlane_b32 s104, v17, 6 +; GFX11-NEXT: v_readlane_b32 s103, v17, 5 +; GFX11-NEXT: v_readlane_b32 s102, v17, 4 +; GFX11-NEXT: v_readlane_b32 s101, v17, 3 +; GFX11-NEXT: v_readlane_b32 s96, v16, 30 +; GFX11-NEXT: v_readlane_b32 s87, v16, 29 +; GFX11-NEXT: v_readlane_b32 s85, v16, 27 +; GFX11-NEXT: v_readlane_b32 s84, v16, 26 +; GFX11-NEXT: v_readlane_b32 s83, v16, 25 +; GFX11-NEXT: v_readlane_b32 s82, v16, 24 +; GFX11-NEXT: v_readlane_b32 s81, v16, 23 +; GFX11-NEXT: v_readlane_b32 s80, v16, 22 +; GFX11-NEXT: v_readlane_b32 s71, v16, 21 +; GFX11-NEXT: v_readlane_b32 s70, v16, 20 +; GFX11-NEXT: v_readlane_b32 s68, v16, 18 +; GFX11-NEXT: v_readlane_b32 s67, v16, 17 +; GFX11-NEXT: v_readlane_b32 s66, v16, 16 +; GFX11-NEXT: v_readlane_b32 s65, v16, 15 +; GFX11-NEXT: v_readlane_b32 s64, v16, 14 +; GFX11-NEXT: v_readlane_b32 s55, v16, 13 +; GFX11-NEXT: v_readlane_b32 s54, v16, 12 +; GFX11-NEXT: v_readlane_b32 s53, v16, 11 +; GFX11-NEXT: v_readlane_b32 s52, v16, 10 +; GFX11-NEXT: v_readlane_b32 s51, v16, 9 +; GFX11-NEXT: v_readlane_b32 s50, v16, 8 +; GFX11-NEXT: v_readlane_b32 s49, v16, 7 +; GFX11-NEXT: v_readlane_b32 s48, v16, 6 +; GFX11-NEXT: v_readlane_b32 s39, v16, 5 +; GFX11-NEXT: v_readlane_b32 s38, v16, 4 +; GFX11-NEXT: v_readlane_b32 s37, v16, 3 +; GFX11-NEXT: v_readlane_b32 s36, v16, 2 +; GFX11-NEXT: v_readlane_b32 s35, v16, 1 +; GFX11-NEXT: v_readlane_b32 s34, v16, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_load_b32 v16, off, s32 @@ -90331,56 +91252,105 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:592 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:588 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:584 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:580 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:576 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:572 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:568 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:564 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:560 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:556 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:552 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:548 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:544 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:540 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:536 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:532 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:528 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:524 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:520 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:516 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:512 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:508 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:504 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:500 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:496 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:492 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:488 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:484 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:480 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:468 ; GFX11-FAKE16-NEXT: s_clause 0x12 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:456 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:392 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -94652,45 +95622,83 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:476 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:472 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:468 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:464 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:460 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:456 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:452 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:448 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:444 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:440 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:436 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:432 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:428 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:424 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:420 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:416 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:412 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:408 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:404 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:400 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:396 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:392 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:388 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:384 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:380 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:376 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:372 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:368 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:364 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:360 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:356 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:352 ; GFX11-TRUE16-NEXT: s_clause 0x7 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:348 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:344 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:340 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:336 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:332 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:328 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:324 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:320 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -95593,45 +96601,83 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:468 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:456 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:392 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:388 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:384 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:380 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:376 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:372 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:368 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:364 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:360 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:356 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:352 ; GFX11-FAKE16-NEXT: s_clause 0x7 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:348 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:344 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:340 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:336 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:332 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:328 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:324 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:320 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -97464,43 +98510,43 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a ; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_writelane_b32 v20, s69, 21 -; SI-NEXT: v_writelane_b32 v20, s70, 22 -; SI-NEXT: v_writelane_b32 v20, s71, 23 -; SI-NEXT: v_writelane_b32 v20, s80, 24 -; SI-NEXT: v_writelane_b32 v20, s81, 25 -; SI-NEXT: v_writelane_b32 v20, s82, 26 -; SI-NEXT: v_writelane_b32 v20, s83, 27 -; SI-NEXT: v_writelane_b32 v20, s84, 28 -; SI-NEXT: v_writelane_b32 v20, s85, 29 -; SI-NEXT: v_writelane_b32 v20, s86, 30 -; SI-NEXT: v_writelane_b32 v20, s87, 31 -; SI-NEXT: v_writelane_b32 v20, s96, 32 -; SI-NEXT: v_writelane_b32 v20, s97, 33 -; SI-NEXT: v_writelane_b32 v20, s98, 34 +; SI-NEXT: v_writelane_b32 v20, s34, 0 +; SI-NEXT: v_writelane_b32 v20, s35, 1 +; SI-NEXT: v_writelane_b32 v20, s36, 2 +; SI-NEXT: v_writelane_b32 v20, s37, 3 +; SI-NEXT: v_writelane_b32 v20, s38, 4 +; SI-NEXT: v_writelane_b32 v20, s39, 5 +; SI-NEXT: v_writelane_b32 v20, s48, 6 +; SI-NEXT: v_writelane_b32 v20, s49, 7 +; SI-NEXT: v_writelane_b32 v20, s50, 8 +; SI-NEXT: v_writelane_b32 v20, s51, 9 +; SI-NEXT: v_writelane_b32 v20, s52, 10 +; SI-NEXT: v_writelane_b32 v20, s53, 11 +; SI-NEXT: v_writelane_b32 v20, s54, 12 +; SI-NEXT: v_writelane_b32 v20, s55, 13 +; SI-NEXT: v_writelane_b32 v20, s64, 14 +; SI-NEXT: v_writelane_b32 v20, s65, 15 +; SI-NEXT: v_writelane_b32 v20, s66, 16 +; SI-NEXT: v_writelane_b32 v20, s67, 17 +; SI-NEXT: v_writelane_b32 v20, s68, 18 +; SI-NEXT: v_writelane_b32 v20, s69, 19 +; SI-NEXT: v_writelane_b32 v20, s70, 20 +; SI-NEXT: v_writelane_b32 v20, s71, 21 +; SI-NEXT: v_writelane_b32 v20, s80, 22 +; SI-NEXT: v_writelane_b32 v20, s81, 23 +; SI-NEXT: v_writelane_b32 v20, s82, 24 +; SI-NEXT: v_writelane_b32 v20, s83, 25 +; SI-NEXT: v_writelane_b32 v20, s84, 26 +; SI-NEXT: v_writelane_b32 v20, s85, 27 +; SI-NEXT: v_writelane_b32 v20, s86, 28 +; SI-NEXT: v_writelane_b32 v20, s87, 29 +; SI-NEXT: v_writelane_b32 v20, s96, 30 +; SI-NEXT: v_writelane_b32 v20, s97, 31 +; SI-NEXT: v_writelane_b32 v20, s98, 32 +; SI-NEXT: v_writelane_b32 v20, s99, 33 +; SI-NEXT: v_writelane_b32 v20, s30, 34 +; SI-NEXT: v_writelane_b32 v20, s31, 35 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s99, 35 ; SI-NEXT: v_readfirstlane_b32 s70, v1 ; SI-NEXT: v_readfirstlane_b32 s71, v2 ; SI-NEXT: v_readfirstlane_b32 s80, v3 @@ -97921,43 +98967,43 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a ; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 ; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 +; SI-NEXT: v_readlane_b32 s30, v20, 34 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v20, 35 -; SI-NEXT: v_readlane_b32 s98, v20, 34 -; SI-NEXT: v_readlane_b32 s97, v20, 33 -; SI-NEXT: v_readlane_b32 s96, v20, 32 -; SI-NEXT: v_readlane_b32 s87, v20, 31 -; SI-NEXT: v_readlane_b32 s86, v20, 30 -; SI-NEXT: v_readlane_b32 s85, v20, 29 -; SI-NEXT: v_readlane_b32 s84, v20, 28 -; SI-NEXT: v_readlane_b32 s83, v20, 27 -; SI-NEXT: v_readlane_b32 s82, v20, 26 -; SI-NEXT: v_readlane_b32 s81, v20, 25 -; SI-NEXT: v_readlane_b32 s80, v20, 24 -; SI-NEXT: v_readlane_b32 s71, v20, 23 -; SI-NEXT: v_readlane_b32 s70, v20, 22 -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s31, v20, 35 +; SI-NEXT: v_readlane_b32 s99, v20, 33 +; SI-NEXT: v_readlane_b32 s98, v20, 32 +; SI-NEXT: v_readlane_b32 s97, v20, 31 +; SI-NEXT: v_readlane_b32 s96, v20, 30 +; SI-NEXT: v_readlane_b32 s87, v20, 29 +; SI-NEXT: v_readlane_b32 s86, v20, 28 +; SI-NEXT: v_readlane_b32 s85, v20, 27 +; SI-NEXT: v_readlane_b32 s84, v20, 26 +; SI-NEXT: v_readlane_b32 s83, v20, 25 +; SI-NEXT: v_readlane_b32 s82, v20, 24 +; SI-NEXT: v_readlane_b32 s81, v20, 23 +; SI-NEXT: v_readlane_b32 s80, v20, 22 +; SI-NEXT: v_readlane_b32 s71, v20, 21 +; SI-NEXT: v_readlane_b32 s70, v20, 20 +; SI-NEXT: v_readlane_b32 s69, v20, 19 +; SI-NEXT: v_readlane_b32 s68, v20, 18 +; SI-NEXT: v_readlane_b32 s67, v20, 17 +; SI-NEXT: v_readlane_b32 s66, v20, 16 +; SI-NEXT: v_readlane_b32 s65, v20, 15 +; SI-NEXT: v_readlane_b32 s64, v20, 14 +; SI-NEXT: v_readlane_b32 s55, v20, 13 +; SI-NEXT: v_readlane_b32 s54, v20, 12 +; SI-NEXT: v_readlane_b32 s53, v20, 11 +; SI-NEXT: v_readlane_b32 s52, v20, 10 +; SI-NEXT: v_readlane_b32 s51, v20, 9 +; SI-NEXT: v_readlane_b32 s50, v20, 8 +; SI-NEXT: v_readlane_b32 s49, v20, 7 +; SI-NEXT: v_readlane_b32 s48, v20, 6 +; SI-NEXT: v_readlane_b32 s39, v20, 5 +; SI-NEXT: v_readlane_b32 s38, v20, 4 +; SI-NEXT: v_readlane_b32 s37, v20, 3 +; SI-NEXT: v_readlane_b32 s36, v20, 2 +; SI-NEXT: v_readlane_b32 s35, v20, 1 +; SI-NEXT: v_readlane_b32 s34, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -100086,20 +101132,35 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4 @@ -103135,81 +104196,149 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v16i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28 ; GFX11-TRUE16-NEXT: s_clause 0x6 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8 @@ -104109,83 +105238,153 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a ; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v16i64_scalar: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164 ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36 ; GFX11-FAKE16-NEXT: s_clause 0x8 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7 @@ -105961,12 +107160,26 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v63, s30, 0 -; SI-NEXT: v_writelane_b32 v63, s31, 1 -; SI-NEXT: v_writelane_b32 v63, s34, 2 +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_writelane_b32 v63, s34, 0 +; SI-NEXT: v_writelane_b32 v63, s35, 1 +; SI-NEXT: v_writelane_b32 v63, s30, 2 +; SI-NEXT: v_writelane_b32 v63, s31, 3 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v63, s35, 3 ; SI-NEXT: v_readfirstlane_b32 s46, v1 ; SI-NEXT: v_readfirstlane_b32 s47, v2 ; SI-NEXT: v_readfirstlane_b32 s44, v3 @@ -105986,21 +107199,6 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s6, v17 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v18 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB65_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -106242,15 +107440,15 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v61, v61 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_readlane_b32 s35, v63, 3 +; SI-NEXT: v_readlane_b32 s30, v63, 2 ; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v61 ; SI-NEXT: v_or_b32_e32 v2, v2, v61 ; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v2, v59 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: v_readlane_b32 s31, v63, 3 +; SI-NEXT: v_readlane_b32 s35, v63, 1 +; SI-NEXT: v_readlane_b32 s34, v63, 0 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; SI-NEXT: v_or_b32_e32 v1, v1, v2 ; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 @@ -108699,84 +109897,155 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i ; GFX11-LABEL: bitcast_v64f16_to_v16i64_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 ; GFX11-NEXT: s_clause 0x9 ; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v185, s32 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 ; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 ; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 @@ -109538,28 +110807,29 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 +; SI-NEXT: v_writelane_b32 v20, s34, 0 +; SI-NEXT: v_writelane_b32 v20, s35, 1 +; SI-NEXT: v_writelane_b32 v20, s36, 2 +; SI-NEXT: v_writelane_b32 v20, s37, 3 +; SI-NEXT: v_writelane_b32 v20, s38, 4 +; SI-NEXT: v_writelane_b32 v20, s39, 5 +; SI-NEXT: v_writelane_b32 v20, s48, 6 +; SI-NEXT: v_writelane_b32 v20, s49, 7 +; SI-NEXT: v_writelane_b32 v20, s50, 8 +; SI-NEXT: v_writelane_b32 v20, s51, 9 +; SI-NEXT: v_writelane_b32 v20, s52, 10 +; SI-NEXT: v_writelane_b32 v20, s53, 11 +; SI-NEXT: v_writelane_b32 v20, s54, 12 +; SI-NEXT: v_writelane_b32 v20, s55, 13 +; SI-NEXT: v_writelane_b32 v20, s64, 14 +; SI-NEXT: v_writelane_b32 v20, s65, 15 +; SI-NEXT: v_writelane_b32 v20, s66, 16 +; SI-NEXT: v_writelane_b32 v20, s67, 17 +; SI-NEXT: v_writelane_b32 v20, s68, 18 +; SI-NEXT: v_writelane_b32 v20, s69, 19 +; SI-NEXT: v_writelane_b32 v20, s30, 20 +; SI-NEXT: v_writelane_b32 v20, s31, 21 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 ; SI-NEXT: v_readfirstlane_b32 s44, v1 ; SI-NEXT: v_readfirstlane_b32 s45, v2 ; SI-NEXT: v_readfirstlane_b32 s42, v3 @@ -109579,7 +110849,6 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v17 ; SI-NEXT: s_and_b64 s[46:47], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v18 -; SI-NEXT: v_writelane_b32 v20, s69, 21 ; SI-NEXT: s_cbranch_scc0 .LBB69_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s38, s5, 16 @@ -109898,29 +111167,29 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v20, 20 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s31, v20, 21 +; SI-NEXT: v_readlane_b32 s69, v20, 19 +; SI-NEXT: v_readlane_b32 s68, v20, 18 +; SI-NEXT: v_readlane_b32 s67, v20, 17 +; SI-NEXT: v_readlane_b32 s66, v20, 16 +; SI-NEXT: v_readlane_b32 s65, v20, 15 +; SI-NEXT: v_readlane_b32 s64, v20, 14 +; SI-NEXT: v_readlane_b32 s55, v20, 13 +; SI-NEXT: v_readlane_b32 s54, v20, 12 +; SI-NEXT: v_readlane_b32 s53, v20, 11 +; SI-NEXT: v_readlane_b32 s52, v20, 10 +; SI-NEXT: v_readlane_b32 s51, v20, 9 +; SI-NEXT: v_readlane_b32 s50, v20, 8 +; SI-NEXT: v_readlane_b32 s49, v20, 7 +; SI-NEXT: v_readlane_b32 s48, v20, 6 +; SI-NEXT: v_readlane_b32 s39, v20, 5 +; SI-NEXT: v_readlane_b32 s38, v20, 4 +; SI-NEXT: v_readlane_b32 s37, v20, 3 +; SI-NEXT: v_readlane_b32 s36, v20, 2 +; SI-NEXT: v_readlane_b32 s35, v20, 1 +; SI-NEXT: v_readlane_b32 s34, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -111763,84 +113032,155 @@ define inreg <16 x i64> @bitcast_v64i16_to_v16i64_scalar(<64 x i16> inreg %a, i3 ; GFX11-LABEL: bitcast_v64i16_to_v16i64_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 ; GFX11-NEXT: s_clause 0x9 ; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v185, s32 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 ; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 ; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 @@ -115630,24 +116970,43 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x13 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12 ; GFX11-FAKE16-NEXT: s_clause 0x2 ; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8 @@ -116321,44 +117680,56 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_writelane_b32 v63, s30, 0 -; SI-NEXT: v_writelane_b32 v63, s31, 1 -; SI-NEXT: v_writelane_b32 v63, s34, 2 -; SI-NEXT: v_writelane_b32 v63, s35, 3 -; SI-NEXT: v_writelane_b32 v63, s36, 4 -; SI-NEXT: v_writelane_b32 v63, s37, 5 -; SI-NEXT: v_writelane_b32 v63, s38, 6 -; SI-NEXT: v_writelane_b32 v63, s39, 7 -; SI-NEXT: v_writelane_b32 v63, s48, 8 -; SI-NEXT: v_writelane_b32 v63, s49, 9 -; SI-NEXT: v_writelane_b32 v63, s50, 10 -; SI-NEXT: v_writelane_b32 v63, s51, 11 -; SI-NEXT: v_writelane_b32 v63, s52, 12 -; SI-NEXT: v_writelane_b32 v63, s53, 13 -; SI-NEXT: v_writelane_b32 v63, s54, 14 -; SI-NEXT: v_writelane_b32 v63, s55, 15 -; SI-NEXT: v_writelane_b32 v63, s64, 16 -; SI-NEXT: v_writelane_b32 v63, s65, 17 -; SI-NEXT: v_writelane_b32 v63, s66, 18 -; SI-NEXT: v_writelane_b32 v63, s67, 19 -; SI-NEXT: v_writelane_b32 v63, s68, 20 -; SI-NEXT: v_writelane_b32 v63, s69, 21 -; SI-NEXT: v_writelane_b32 v63, s70, 22 -; SI-NEXT: v_writelane_b32 v63, s71, 23 -; SI-NEXT: v_writelane_b32 v63, s80, 24 -; SI-NEXT: v_writelane_b32 v63, s81, 25 -; SI-NEXT: v_writelane_b32 v63, s82, 26 -; SI-NEXT: v_writelane_b32 v63, s83, 27 -; SI-NEXT: v_writelane_b32 v63, s84, 28 -; SI-NEXT: v_writelane_b32 v63, s85, 29 -; SI-NEXT: v_writelane_b32 v63, s86, 30 -; SI-NEXT: v_writelane_b32 v63, s87, 31 -; SI-NEXT: v_writelane_b32 v63, s96, 32 -; SI-NEXT: v_writelane_b32 v63, s97, 33 -; SI-NEXT: v_writelane_b32 v63, s98, 34 +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_writelane_b32 v63, s34, 0 +; SI-NEXT: v_writelane_b32 v63, s35, 1 +; SI-NEXT: v_writelane_b32 v63, s36, 2 +; SI-NEXT: v_writelane_b32 v63, s37, 3 +; SI-NEXT: v_writelane_b32 v63, s38, 4 +; SI-NEXT: v_writelane_b32 v63, s39, 5 +; SI-NEXT: v_writelane_b32 v63, s48, 6 +; SI-NEXT: v_writelane_b32 v63, s49, 7 +; SI-NEXT: v_writelane_b32 v63, s50, 8 +; SI-NEXT: v_writelane_b32 v63, s51, 9 +; SI-NEXT: v_writelane_b32 v63, s52, 10 +; SI-NEXT: v_writelane_b32 v63, s53, 11 +; SI-NEXT: v_writelane_b32 v63, s54, 12 +; SI-NEXT: v_writelane_b32 v63, s55, 13 +; SI-NEXT: v_writelane_b32 v63, s64, 14 +; SI-NEXT: v_writelane_b32 v63, s65, 15 +; SI-NEXT: v_writelane_b32 v63, s66, 16 +; SI-NEXT: v_writelane_b32 v63, s67, 17 +; SI-NEXT: v_writelane_b32 v63, s68, 18 +; SI-NEXT: v_writelane_b32 v63, s69, 19 +; SI-NEXT: v_writelane_b32 v63, s70, 20 +; SI-NEXT: v_writelane_b32 v63, s71, 21 +; SI-NEXT: v_writelane_b32 v63, s80, 22 +; SI-NEXT: v_writelane_b32 v63, s81, 23 +; SI-NEXT: v_writelane_b32 v63, s82, 24 +; SI-NEXT: v_writelane_b32 v63, s83, 25 +; SI-NEXT: v_writelane_b32 v63, s84, 26 +; SI-NEXT: v_writelane_b32 v63, s85, 27 +; SI-NEXT: v_writelane_b32 v63, s86, 28 +; SI-NEXT: v_writelane_b32 v63, s87, 29 +; SI-NEXT: v_writelane_b32 v63, s96, 30 +; SI-NEXT: v_writelane_b32 v63, s97, 31 +; SI-NEXT: v_writelane_b32 v63, s98, 32 +; SI-NEXT: v_writelane_b32 v63, s99, 33 +; SI-NEXT: v_writelane_b32 v63, s30, 34 +; SI-NEXT: v_writelane_b32 v63, s31, 35 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v63, s99, 35 ; SI-NEXT: v_readfirstlane_b32 s4, v1 ; SI-NEXT: v_readfirstlane_b32 s5, v2 ; SI-NEXT: v_readfirstlane_b32 s6, v3 @@ -116378,19 +117749,6 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; SI-NEXT: v_readfirstlane_b32 s44, v17 ; SI-NEXT: s_and_b64 s[46:47], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s45, v18 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane ; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB73_3 @@ -117476,42 +118834,42 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; SI-NEXT: v_and_b32_e32 v5, 0xff, v5 ; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 ; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_readlane_b32 s99, v63, 35 -; SI-NEXT: v_readlane_b32 s98, v63, 34 -; SI-NEXT: v_readlane_b32 s97, v63, 33 -; SI-NEXT: v_readlane_b32 s96, v63, 32 -; SI-NEXT: v_readlane_b32 s87, v63, 31 -; SI-NEXT: v_readlane_b32 s86, v63, 30 -; SI-NEXT: v_readlane_b32 s85, v63, 29 -; SI-NEXT: v_readlane_b32 s84, v63, 28 -; SI-NEXT: v_readlane_b32 s83, v63, 27 -; SI-NEXT: v_readlane_b32 s82, v63, 26 -; SI-NEXT: v_readlane_b32 s81, v63, 25 -; SI-NEXT: v_readlane_b32 s80, v63, 24 -; SI-NEXT: v_readlane_b32 s71, v63, 23 -; SI-NEXT: v_readlane_b32 s70, v63, 22 -; SI-NEXT: v_readlane_b32 s69, v63, 21 -; SI-NEXT: v_readlane_b32 s68, v63, 20 -; SI-NEXT: v_readlane_b32 s67, v63, 19 -; SI-NEXT: v_readlane_b32 s66, v63, 18 -; SI-NEXT: v_readlane_b32 s65, v63, 17 -; SI-NEXT: v_readlane_b32 s64, v63, 16 -; SI-NEXT: v_readlane_b32 s55, v63, 15 -; SI-NEXT: v_readlane_b32 s54, v63, 14 -; SI-NEXT: v_readlane_b32 s53, v63, 13 -; SI-NEXT: v_readlane_b32 s52, v63, 12 -; SI-NEXT: v_readlane_b32 s51, v63, 11 -; SI-NEXT: v_readlane_b32 s50, v63, 10 -; SI-NEXT: v_readlane_b32 s49, v63, 9 -; SI-NEXT: v_readlane_b32 s48, v63, 8 -; SI-NEXT: v_readlane_b32 s39, v63, 7 -; SI-NEXT: v_readlane_b32 s38, v63, 6 -; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s36, v63, 4 -; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: v_readlane_b32 s30, v63, 34 +; SI-NEXT: v_readlane_b32 s31, v63, 35 +; SI-NEXT: v_readlane_b32 s99, v63, 33 +; SI-NEXT: v_readlane_b32 s98, v63, 32 +; SI-NEXT: v_readlane_b32 s97, v63, 31 +; SI-NEXT: v_readlane_b32 s96, v63, 30 +; SI-NEXT: v_readlane_b32 s87, v63, 29 +; SI-NEXT: v_readlane_b32 s86, v63, 28 +; SI-NEXT: v_readlane_b32 s85, v63, 27 +; SI-NEXT: v_readlane_b32 s84, v63, 26 +; SI-NEXT: v_readlane_b32 s83, v63, 25 +; SI-NEXT: v_readlane_b32 s82, v63, 24 +; SI-NEXT: v_readlane_b32 s81, v63, 23 +; SI-NEXT: v_readlane_b32 s80, v63, 22 +; SI-NEXT: v_readlane_b32 s71, v63, 21 +; SI-NEXT: v_readlane_b32 s70, v63, 20 +; SI-NEXT: v_readlane_b32 s69, v63, 19 +; SI-NEXT: v_readlane_b32 s68, v63, 18 +; SI-NEXT: v_readlane_b32 s67, v63, 17 +; SI-NEXT: v_readlane_b32 s66, v63, 16 +; SI-NEXT: v_readlane_b32 s65, v63, 15 +; SI-NEXT: v_readlane_b32 s64, v63, 14 +; SI-NEXT: v_readlane_b32 s55, v63, 13 +; SI-NEXT: v_readlane_b32 s54, v63, 12 +; SI-NEXT: v_readlane_b32 s53, v63, 11 +; SI-NEXT: v_readlane_b32 s52, v63, 10 +; SI-NEXT: v_readlane_b32 s51, v63, 9 +; SI-NEXT: v_readlane_b32 s50, v63, 8 +; SI-NEXT: v_readlane_b32 s49, v63, 7 +; SI-NEXT: v_readlane_b32 s48, v63, 6 +; SI-NEXT: v_readlane_b32 s39, v63, 5 +; SI-NEXT: v_readlane_b32 s38, v63, 4 +; SI-NEXT: v_readlane_b32 s37, v63, 3 +; SI-NEXT: v_readlane_b32 s36, v63, 2 +; SI-NEXT: v_readlane_b32 s35, v63, 1 +; SI-NEXT: v_readlane_b32 s34, v63, 0 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v26, 0xff, v26 ; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26 @@ -118039,39 +119397,53 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v63, s30, 0 -; VI-NEXT: v_writelane_b32 v63, s31, 1 -; VI-NEXT: v_writelane_b32 v63, s34, 2 -; VI-NEXT: v_writelane_b32 v63, s35, 3 -; VI-NEXT: v_writelane_b32 v63, s36, 4 -; VI-NEXT: v_writelane_b32 v63, s37, 5 -; VI-NEXT: v_writelane_b32 v63, s38, 6 -; VI-NEXT: v_writelane_b32 v63, s39, 7 -; VI-NEXT: v_writelane_b32 v63, s48, 8 -; VI-NEXT: v_writelane_b32 v63, s49, 9 -; VI-NEXT: v_writelane_b32 v63, s50, 10 -; VI-NEXT: v_writelane_b32 v63, s51, 11 -; VI-NEXT: v_writelane_b32 v63, s52, 12 -; VI-NEXT: v_writelane_b32 v63, s53, 13 -; VI-NEXT: v_writelane_b32 v63, s54, 14 -; VI-NEXT: v_writelane_b32 v63, s55, 15 -; VI-NEXT: v_writelane_b32 v63, s64, 16 -; VI-NEXT: v_writelane_b32 v63, s65, 17 -; VI-NEXT: v_writelane_b32 v63, s66, 18 -; VI-NEXT: v_writelane_b32 v63, s67, 19 -; VI-NEXT: v_writelane_b32 v63, s68, 20 -; VI-NEXT: v_writelane_b32 v63, s69, 21 -; VI-NEXT: v_writelane_b32 v63, s70, 22 -; VI-NEXT: v_writelane_b32 v63, s71, 23 -; VI-NEXT: v_writelane_b32 v63, s80, 24 -; VI-NEXT: v_writelane_b32 v63, s81, 25 -; VI-NEXT: v_writelane_b32 v63, s82, 26 -; VI-NEXT: v_writelane_b32 v63, s83, 27 -; VI-NEXT: v_writelane_b32 v63, s84, 28 -; VI-NEXT: v_writelane_b32 v63, s85, 29 -; VI-NEXT: v_writelane_b32 v63, s86, 30 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_writelane_b32 v63, s34, 0 +; VI-NEXT: v_writelane_b32 v63, s35, 1 +; VI-NEXT: v_writelane_b32 v63, s36, 2 +; VI-NEXT: v_writelane_b32 v63, s37, 3 +; VI-NEXT: v_writelane_b32 v63, s38, 4 +; VI-NEXT: v_writelane_b32 v63, s39, 5 +; VI-NEXT: v_writelane_b32 v63, s48, 6 +; VI-NEXT: v_writelane_b32 v63, s49, 7 +; VI-NEXT: v_writelane_b32 v63, s50, 8 +; VI-NEXT: v_writelane_b32 v63, s51, 9 +; VI-NEXT: v_writelane_b32 v63, s52, 10 +; VI-NEXT: v_writelane_b32 v63, s53, 11 +; VI-NEXT: v_writelane_b32 v63, s54, 12 +; VI-NEXT: v_writelane_b32 v63, s55, 13 +; VI-NEXT: v_writelane_b32 v63, s64, 14 +; VI-NEXT: v_writelane_b32 v63, s65, 15 +; VI-NEXT: v_writelane_b32 v63, s66, 16 +; VI-NEXT: v_writelane_b32 v63, s67, 17 +; VI-NEXT: v_writelane_b32 v63, s68, 18 +; VI-NEXT: v_writelane_b32 v63, s69, 19 +; VI-NEXT: v_writelane_b32 v63, s70, 20 +; VI-NEXT: v_writelane_b32 v63, s71, 21 +; VI-NEXT: v_writelane_b32 v63, s80, 22 +; VI-NEXT: v_writelane_b32 v63, s81, 23 +; VI-NEXT: v_writelane_b32 v63, s82, 24 +; VI-NEXT: v_writelane_b32 v63, s83, 25 +; VI-NEXT: v_writelane_b32 v63, s84, 26 +; VI-NEXT: v_writelane_b32 v63, s85, 27 +; VI-NEXT: v_writelane_b32 v63, s86, 28 +; VI-NEXT: v_writelane_b32 v63, s87, 29 +; VI-NEXT: v_writelane_b32 v63, s30, 30 +; VI-NEXT: v_writelane_b32 v63, s31, 31 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v63, s87, 31 ; VI-NEXT: v_readfirstlane_b32 s6, v1 ; VI-NEXT: v_readfirstlane_b32 s7, v2 ; VI-NEXT: v_readfirstlane_b32 s8, v3 @@ -118091,20 +119463,6 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; VI-NEXT: v_readfirstlane_b32 s4, v17 ; VI-NEXT: s_and_b64 s[46:47], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v18 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB73_3 ; VI-NEXT: ; %bb.1: ; %cmp.false @@ -118901,38 +120259,38 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload ; VI-NEXT: v_or_b32_sdwa v32, v32, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_readlane_b32 s87, v63, 31 -; VI-NEXT: v_readlane_b32 s86, v63, 30 -; VI-NEXT: v_readlane_b32 s85, v63, 29 -; VI-NEXT: v_readlane_b32 s84, v63, 28 -; VI-NEXT: v_readlane_b32 s83, v63, 27 -; VI-NEXT: v_readlane_b32 s82, v63, 26 -; VI-NEXT: v_readlane_b32 s81, v63, 25 -; VI-NEXT: v_readlane_b32 s80, v63, 24 -; VI-NEXT: v_readlane_b32 s71, v63, 23 -; VI-NEXT: v_readlane_b32 s70, v63, 22 -; VI-NEXT: v_readlane_b32 s69, v63, 21 -; VI-NEXT: v_readlane_b32 s68, v63, 20 -; VI-NEXT: v_readlane_b32 s67, v63, 19 -; VI-NEXT: v_readlane_b32 s66, v63, 18 -; VI-NEXT: v_readlane_b32 s65, v63, 17 -; VI-NEXT: v_readlane_b32 s64, v63, 16 -; VI-NEXT: v_readlane_b32 s55, v63, 15 -; VI-NEXT: v_readlane_b32 s54, v63, 14 -; VI-NEXT: v_readlane_b32 s53, v63, 13 -; VI-NEXT: v_readlane_b32 s52, v63, 12 -; VI-NEXT: v_readlane_b32 s51, v63, 11 -; VI-NEXT: v_readlane_b32 s50, v63, 10 -; VI-NEXT: v_readlane_b32 s49, v63, 9 -; VI-NEXT: v_readlane_b32 s48, v63, 8 -; VI-NEXT: v_readlane_b32 s39, v63, 7 -; VI-NEXT: v_readlane_b32 s38, v63, 6 -; VI-NEXT: v_readlane_b32 s37, v63, 5 -; VI-NEXT: v_readlane_b32 s36, v63, 4 -; VI-NEXT: v_readlane_b32 s35, v63, 3 -; VI-NEXT: v_readlane_b32 s34, v63, 2 -; VI-NEXT: v_readlane_b32 s31, v63, 1 -; VI-NEXT: v_readlane_b32 s30, v63, 0 +; VI-NEXT: v_readlane_b32 s30, v63, 30 +; VI-NEXT: v_readlane_b32 s31, v63, 31 +; VI-NEXT: v_readlane_b32 s87, v63, 29 +; VI-NEXT: v_readlane_b32 s86, v63, 28 +; VI-NEXT: v_readlane_b32 s85, v63, 27 +; VI-NEXT: v_readlane_b32 s84, v63, 26 +; VI-NEXT: v_readlane_b32 s83, v63, 25 +; VI-NEXT: v_readlane_b32 s82, v63, 24 +; VI-NEXT: v_readlane_b32 s81, v63, 23 +; VI-NEXT: v_readlane_b32 s80, v63, 22 +; VI-NEXT: v_readlane_b32 s71, v63, 21 +; VI-NEXT: v_readlane_b32 s70, v63, 20 +; VI-NEXT: v_readlane_b32 s69, v63, 19 +; VI-NEXT: v_readlane_b32 s68, v63, 18 +; VI-NEXT: v_readlane_b32 s67, v63, 17 +; VI-NEXT: v_readlane_b32 s66, v63, 16 +; VI-NEXT: v_readlane_b32 s65, v63, 15 +; VI-NEXT: v_readlane_b32 s64, v63, 14 +; VI-NEXT: v_readlane_b32 s55, v63, 13 +; VI-NEXT: v_readlane_b32 s54, v63, 12 +; VI-NEXT: v_readlane_b32 s53, v63, 11 +; VI-NEXT: v_readlane_b32 s52, v63, 10 +; VI-NEXT: v_readlane_b32 s51, v63, 9 +; VI-NEXT: v_readlane_b32 s50, v63, 8 +; VI-NEXT: v_readlane_b32 s49, v63, 7 +; VI-NEXT: v_readlane_b32 s48, v63, 6 +; VI-NEXT: v_readlane_b32 s39, v63, 5 +; VI-NEXT: v_readlane_b32 s38, v63, 4 +; VI-NEXT: v_readlane_b32 s37, v63, 3 +; VI-NEXT: v_readlane_b32 s36, v63, 2 +; VI-NEXT: v_readlane_b32 s35, v63, 1 +; VI-NEXT: v_readlane_b32 s34, v63, 0 ; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: v_lshlrev_b32_e32 v34, 8, v42 ; VI-NEXT: s_waitcnt vmcnt(0) @@ -119323,43 +120681,57 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v63, s30, 0 -; GFX9-NEXT: v_writelane_b32 v63, s31, 1 -; GFX9-NEXT: v_writelane_b32 v63, s34, 2 -; GFX9-NEXT: v_writelane_b32 v63, s35, 3 -; GFX9-NEXT: v_writelane_b32 v63, s36, 4 -; GFX9-NEXT: v_writelane_b32 v63, s37, 5 -; GFX9-NEXT: v_writelane_b32 v63, s38, 6 -; GFX9-NEXT: v_writelane_b32 v63, s39, 7 -; GFX9-NEXT: v_writelane_b32 v63, s48, 8 -; GFX9-NEXT: v_writelane_b32 v63, s49, 9 -; GFX9-NEXT: v_writelane_b32 v63, s50, 10 -; GFX9-NEXT: v_writelane_b32 v63, s51, 11 -; GFX9-NEXT: v_writelane_b32 v63, s52, 12 -; GFX9-NEXT: v_writelane_b32 v63, s53, 13 -; GFX9-NEXT: v_writelane_b32 v63, s54, 14 -; GFX9-NEXT: v_writelane_b32 v63, s55, 15 -; GFX9-NEXT: v_writelane_b32 v63, s64, 16 -; GFX9-NEXT: v_writelane_b32 v63, s65, 17 -; GFX9-NEXT: v_writelane_b32 v63, s66, 18 -; GFX9-NEXT: v_writelane_b32 v63, s67, 19 -; GFX9-NEXT: v_writelane_b32 v63, s68, 20 -; GFX9-NEXT: v_writelane_b32 v63, s69, 21 -; GFX9-NEXT: v_writelane_b32 v63, s70, 22 -; GFX9-NEXT: v_writelane_b32 v63, s71, 23 -; GFX9-NEXT: v_writelane_b32 v63, s80, 24 -; GFX9-NEXT: v_writelane_b32 v63, s81, 25 -; GFX9-NEXT: v_writelane_b32 v63, s82, 26 -; GFX9-NEXT: v_writelane_b32 v63, s83, 27 -; GFX9-NEXT: v_writelane_b32 v63, s84, 28 -; GFX9-NEXT: v_writelane_b32 v63, s85, 29 -; GFX9-NEXT: v_writelane_b32 v63, s86, 30 -; GFX9-NEXT: v_writelane_b32 v63, s87, 31 -; GFX9-NEXT: v_writelane_b32 v63, s96, 32 -; GFX9-NEXT: v_writelane_b32 v63, s97, 33 -; GFX9-NEXT: v_writelane_b32 v63, s98, 34 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v63, s34, 0 +; GFX9-NEXT: v_writelane_b32 v63, s35, 1 +; GFX9-NEXT: v_writelane_b32 v63, s36, 2 +; GFX9-NEXT: v_writelane_b32 v63, s37, 3 +; GFX9-NEXT: v_writelane_b32 v63, s38, 4 +; GFX9-NEXT: v_writelane_b32 v63, s39, 5 +; GFX9-NEXT: v_writelane_b32 v63, s48, 6 +; GFX9-NEXT: v_writelane_b32 v63, s49, 7 +; GFX9-NEXT: v_writelane_b32 v63, s50, 8 +; GFX9-NEXT: v_writelane_b32 v63, s51, 9 +; GFX9-NEXT: v_writelane_b32 v63, s52, 10 +; GFX9-NEXT: v_writelane_b32 v63, s53, 11 +; GFX9-NEXT: v_writelane_b32 v63, s54, 12 +; GFX9-NEXT: v_writelane_b32 v63, s55, 13 +; GFX9-NEXT: v_writelane_b32 v63, s64, 14 +; GFX9-NEXT: v_writelane_b32 v63, s65, 15 +; GFX9-NEXT: v_writelane_b32 v63, s66, 16 +; GFX9-NEXT: v_writelane_b32 v63, s67, 17 +; GFX9-NEXT: v_writelane_b32 v63, s68, 18 +; GFX9-NEXT: v_writelane_b32 v63, s69, 19 +; GFX9-NEXT: v_writelane_b32 v63, s70, 20 +; GFX9-NEXT: v_writelane_b32 v63, s71, 21 +; GFX9-NEXT: v_writelane_b32 v63, s80, 22 +; GFX9-NEXT: v_writelane_b32 v63, s81, 23 +; GFX9-NEXT: v_writelane_b32 v63, s82, 24 +; GFX9-NEXT: v_writelane_b32 v63, s83, 25 +; GFX9-NEXT: v_writelane_b32 v63, s84, 26 +; GFX9-NEXT: v_writelane_b32 v63, s85, 27 +; GFX9-NEXT: v_writelane_b32 v63, s86, 28 +; GFX9-NEXT: v_writelane_b32 v63, s87, 29 +; GFX9-NEXT: v_writelane_b32 v63, s96, 30 +; GFX9-NEXT: v_writelane_b32 v63, s97, 31 +; GFX9-NEXT: v_writelane_b32 v63, s98, 32 +; GFX9-NEXT: v_writelane_b32 v63, s99, 33 +; GFX9-NEXT: v_writelane_b32 v63, s30, 34 +; GFX9-NEXT: v_writelane_b32 v63, s31, 35 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; GFX9-NEXT: v_writelane_b32 v63, s99, 35 ; GFX9-NEXT: v_readfirstlane_b32 s6, v1 ; GFX9-NEXT: v_readfirstlane_b32 s7, v2 ; GFX9-NEXT: v_readfirstlane_b32 s8, v3 @@ -119379,20 +120751,6 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX9-NEXT: v_readfirstlane_b32 s4, v17 ; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v18 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB73_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false @@ -120215,42 +121573,42 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX9-NEXT: v_or_b32_sdwa v18, v38, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_lshlrev_b32_e32 v38, 8, v41 ; GFX9-NEXT: v_or_b32_sdwa v35, v35, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_readlane_b32 s99, v63, 35 -; GFX9-NEXT: v_readlane_b32 s98, v63, 34 -; GFX9-NEXT: v_readlane_b32 s97, v63, 33 -; GFX9-NEXT: v_readlane_b32 s96, v63, 32 -; GFX9-NEXT: v_readlane_b32 s87, v63, 31 -; GFX9-NEXT: v_readlane_b32 s86, v63, 30 -; GFX9-NEXT: v_readlane_b32 s85, v63, 29 -; GFX9-NEXT: v_readlane_b32 s84, v63, 28 -; GFX9-NEXT: v_readlane_b32 s83, v63, 27 -; GFX9-NEXT: v_readlane_b32 s82, v63, 26 -; GFX9-NEXT: v_readlane_b32 s81, v63, 25 -; GFX9-NEXT: v_readlane_b32 s80, v63, 24 -; GFX9-NEXT: v_readlane_b32 s71, v63, 23 -; GFX9-NEXT: v_readlane_b32 s70, v63, 22 -; GFX9-NEXT: v_readlane_b32 s69, v63, 21 -; GFX9-NEXT: v_readlane_b32 s68, v63, 20 -; GFX9-NEXT: v_readlane_b32 s67, v63, 19 -; GFX9-NEXT: v_readlane_b32 s66, v63, 18 -; GFX9-NEXT: v_readlane_b32 s65, v63, 17 -; GFX9-NEXT: v_readlane_b32 s64, v63, 16 -; GFX9-NEXT: v_readlane_b32 s55, v63, 15 -; GFX9-NEXT: v_readlane_b32 s54, v63, 14 -; GFX9-NEXT: v_readlane_b32 s53, v63, 13 -; GFX9-NEXT: v_readlane_b32 s52, v63, 12 -; GFX9-NEXT: v_readlane_b32 s51, v63, 11 -; GFX9-NEXT: v_readlane_b32 s50, v63, 10 -; GFX9-NEXT: v_readlane_b32 s49, v63, 9 -; GFX9-NEXT: v_readlane_b32 s48, v63, 8 -; GFX9-NEXT: v_readlane_b32 s39, v63, 7 -; GFX9-NEXT: v_readlane_b32 s38, v63, 6 -; GFX9-NEXT: v_readlane_b32 s37, v63, 5 -; GFX9-NEXT: v_readlane_b32 s36, v63, 4 -; GFX9-NEXT: v_readlane_b32 s35, v63, 3 -; GFX9-NEXT: v_readlane_b32 s34, v63, 2 -; GFX9-NEXT: v_readlane_b32 s31, v63, 1 -; GFX9-NEXT: v_readlane_b32 s30, v63, 0 +; GFX9-NEXT: v_readlane_b32 s30, v63, 34 +; GFX9-NEXT: v_readlane_b32 s31, v63, 35 +; GFX9-NEXT: v_readlane_b32 s99, v63, 33 +; GFX9-NEXT: v_readlane_b32 s98, v63, 32 +; GFX9-NEXT: v_readlane_b32 s97, v63, 31 +; GFX9-NEXT: v_readlane_b32 s96, v63, 30 +; GFX9-NEXT: v_readlane_b32 s87, v63, 29 +; GFX9-NEXT: v_readlane_b32 s86, v63, 28 +; GFX9-NEXT: v_readlane_b32 s85, v63, 27 +; GFX9-NEXT: v_readlane_b32 s84, v63, 26 +; GFX9-NEXT: v_readlane_b32 s83, v63, 25 +; GFX9-NEXT: v_readlane_b32 s82, v63, 24 +; GFX9-NEXT: v_readlane_b32 s81, v63, 23 +; GFX9-NEXT: v_readlane_b32 s80, v63, 22 +; GFX9-NEXT: v_readlane_b32 s71, v63, 21 +; GFX9-NEXT: v_readlane_b32 s70, v63, 20 +; GFX9-NEXT: v_readlane_b32 s69, v63, 19 +; GFX9-NEXT: v_readlane_b32 s68, v63, 18 +; GFX9-NEXT: v_readlane_b32 s67, v63, 17 +; GFX9-NEXT: v_readlane_b32 s66, v63, 16 +; GFX9-NEXT: v_readlane_b32 s65, v63, 15 +; GFX9-NEXT: v_readlane_b32 s64, v63, 14 +; GFX9-NEXT: v_readlane_b32 s55, v63, 13 +; GFX9-NEXT: v_readlane_b32 s54, v63, 12 +; GFX9-NEXT: v_readlane_b32 s53, v63, 11 +; GFX9-NEXT: v_readlane_b32 s52, v63, 10 +; GFX9-NEXT: v_readlane_b32 s51, v63, 9 +; GFX9-NEXT: v_readlane_b32 s50, v63, 8 +; GFX9-NEXT: v_readlane_b32 s49, v63, 7 +; GFX9-NEXT: v_readlane_b32 s48, v63, 6 +; GFX9-NEXT: v_readlane_b32 s39, v63, 5 +; GFX9-NEXT: v_readlane_b32 s38, v63, 4 +; GFX9-NEXT: v_readlane_b32 s37, v63, 3 +; GFX9-NEXT: v_readlane_b32 s36, v63, 2 +; GFX9-NEXT: v_readlane_b32 s35, v63, 1 +; GFX9-NEXT: v_readlane_b32 s34, v63, 0 ; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: v_lshlrev_b32_e32 v36, 8, v36 @@ -120601,91 +121959,113 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:92 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v76, s30, 0 -; GFX11-NEXT: v_writelane_b32 v77, s96, 0 -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_readfirstlane_b32 s4, v1 -; GFX11-NEXT: v_readfirstlane_b32 s5, v2 -; GFX11-NEXT: v_writelane_b32 v76, s31, 1 -; GFX11-NEXT: v_writelane_b32 v77, s97, 1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v3 -; GFX11-NEXT: v_readfirstlane_b32 s7, v4 -; GFX11-NEXT: v_readfirstlane_b32 s8, v5 -; GFX11-NEXT: v_writelane_b32 v76, s34, 2 -; GFX11-NEXT: v_writelane_b32 v77, s98, 2 -; GFX11-NEXT: v_readfirstlane_b32 s9, v6 -; GFX11-NEXT: v_readfirstlane_b32 s10, v7 -; GFX11-NEXT: v_readfirstlane_b32 s11, v8 -; GFX11-NEXT: v_writelane_b32 v76, s35, 3 -; GFX11-NEXT: v_writelane_b32 v77, s99, 3 -; GFX11-NEXT: v_readfirstlane_b32 s12, v9 -; GFX11-NEXT: v_readfirstlane_b32 s13, v10 -; GFX11-NEXT: v_readfirstlane_b32 s14, v11 -; GFX11-NEXT: v_writelane_b32 v76, s36, 4 -; GFX11-NEXT: v_writelane_b32 v77, s100, 4 -; GFX11-NEXT: v_readfirstlane_b32 s15, v12 -; GFX11-NEXT: v_readfirstlane_b32 s40, v13 -; GFX11-NEXT: v_readfirstlane_b32 s41, v14 -; GFX11-NEXT: v_writelane_b32 v76, s37, 5 -; GFX11-NEXT: v_writelane_b32 v77, s101, 5 -; GFX11-NEXT: s_mov_b32 vcc_hi, 0 -; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: s_clause 0x13 ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v75, s32 -; GFX11-NEXT: v_writelane_b32 v76, s38, 6 -; GFX11-NEXT: v_writelane_b32 v77, s102, 6 +; GFX11-NEXT: v_writelane_b32 v76, s34, 0 +; GFX11-NEXT: v_writelane_b32 v76, s35, 1 +; GFX11-NEXT: v_writelane_b32 v76, s36, 2 +; GFX11-NEXT: v_writelane_b32 v76, s37, 3 +; GFX11-NEXT: v_writelane_b32 v76, s38, 4 +; GFX11-NEXT: v_writelane_b32 v76, s39, 5 +; GFX11-NEXT: v_writelane_b32 v76, s48, 6 +; GFX11-NEXT: v_writelane_b32 v76, s49, 7 +; GFX11-NEXT: v_writelane_b32 v76, s50, 8 +; GFX11-NEXT: v_writelane_b32 v76, s51, 9 +; GFX11-NEXT: v_writelane_b32 v76, s52, 10 +; GFX11-NEXT: v_writelane_b32 v76, s53, 11 +; GFX11-NEXT: v_writelane_b32 v76, s54, 12 +; GFX11-NEXT: v_writelane_b32 v76, s55, 13 +; GFX11-NEXT: v_writelane_b32 v76, s64, 14 +; GFX11-NEXT: v_writelane_b32 v76, s65, 15 +; GFX11-NEXT: v_writelane_b32 v76, s66, 16 +; GFX11-NEXT: v_writelane_b32 v76, s67, 17 +; GFX11-NEXT: v_writelane_b32 v76, s68, 18 +; GFX11-NEXT: v_writelane_b32 v76, s69, 19 +; GFX11-NEXT: v_writelane_b32 v76, s70, 20 +; GFX11-NEXT: v_writelane_b32 v76, s71, 21 +; GFX11-NEXT: v_writelane_b32 v76, s80, 22 +; GFX11-NEXT: v_writelane_b32 v76, s81, 23 +; GFX11-NEXT: v_writelane_b32 v76, s82, 24 +; GFX11-NEXT: v_writelane_b32 v76, s83, 25 +; GFX11-NEXT: v_writelane_b32 v76, s84, 26 +; GFX11-NEXT: v_writelane_b32 v76, s85, 27 +; GFX11-NEXT: v_writelane_b32 v76, s86, 28 +; GFX11-NEXT: v_writelane_b32 v76, s87, 29 +; GFX11-NEXT: v_writelane_b32 v76, s96, 30 +; GFX11-NEXT: v_writelane_b32 v76, s97, 31 +; GFX11-NEXT: v_writelane_b32 v77, s98, 0 +; GFX11-NEXT: v_writelane_b32 v77, s99, 1 +; GFX11-NEXT: v_writelane_b32 v77, s100, 2 +; GFX11-NEXT: v_writelane_b32 v77, s101, 3 +; GFX11-NEXT: v_writelane_b32 v77, s102, 4 +; GFX11-NEXT: v_writelane_b32 v77, s103, 5 +; GFX11-NEXT: v_writelane_b32 v77, s104, 6 +; GFX11-NEXT: v_writelane_b32 v77, s30, 7 +; GFX11-NEXT: v_writelane_b32 v77, s31, 8 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 +; GFX11-NEXT: v_readfirstlane_b32 s4, v1 +; GFX11-NEXT: v_readfirstlane_b32 s5, v2 +; GFX11-NEXT: v_readfirstlane_b32 s6, v3 +; GFX11-NEXT: v_readfirstlane_b32 s7, v4 +; GFX11-NEXT: v_readfirstlane_b32 s8, v5 +; GFX11-NEXT: v_readfirstlane_b32 s9, v6 +; GFX11-NEXT: v_readfirstlane_b32 s10, v7 +; GFX11-NEXT: v_readfirstlane_b32 s11, v8 +; GFX11-NEXT: v_readfirstlane_b32 s12, v9 +; GFX11-NEXT: v_readfirstlane_b32 s13, v10 +; GFX11-NEXT: v_readfirstlane_b32 s14, v11 +; GFX11-NEXT: v_readfirstlane_b32 s15, v12 +; GFX11-NEXT: v_readfirstlane_b32 s40, v13 +; GFX11-NEXT: v_readfirstlane_b32 s41, v14 +; GFX11-NEXT: s_mov_b32 vcc_hi, 0 +; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane ; GFX11-NEXT: ; implicit-def: $vgpr79 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v76, s39, 7 -; GFX11-NEXT: v_writelane_b32 v77, s103, 7 -; GFX11-NEXT: v_writelane_b32 v76, s48, 8 -; GFX11-NEXT: v_writelane_b32 v77, s104, 8 -; GFX11-NEXT: v_writelane_b32 v76, s49, 9 -; GFX11-NEXT: v_writelane_b32 v76, s50, 10 -; GFX11-NEXT: v_writelane_b32 v76, s51, 11 -; GFX11-NEXT: v_writelane_b32 v76, s52, 12 -; GFX11-NEXT: v_writelane_b32 v76, s53, 13 -; GFX11-NEXT: v_writelane_b32 v76, s54, 14 -; GFX11-NEXT: v_writelane_b32 v76, s55, 15 -; GFX11-NEXT: v_writelane_b32 v76, s64, 16 -; GFX11-NEXT: v_writelane_b32 v76, s65, 17 -; GFX11-NEXT: v_writelane_b32 v76, s66, 18 -; GFX11-NEXT: v_writelane_b32 v76, s67, 19 -; GFX11-NEXT: v_writelane_b32 v76, s68, 20 -; GFX11-NEXT: v_writelane_b32 v76, s69, 21 -; GFX11-NEXT: v_writelane_b32 v76, s70, 22 -; GFX11-NEXT: v_writelane_b32 v76, s71, 23 -; GFX11-NEXT: v_writelane_b32 v76, s80, 24 -; GFX11-NEXT: v_writelane_b32 v76, s81, 25 -; GFX11-NEXT: v_writelane_b32 v76, s82, 26 -; GFX11-NEXT: v_writelane_b32 v76, s83, 27 -; GFX11-NEXT: v_writelane_b32 v76, s84, 28 -; GFX11-NEXT: v_writelane_b32 v76, s85, 29 -; GFX11-NEXT: v_writelane_b32 v76, s86, 30 -; GFX11-NEXT: v_writelane_b32 v76, s87, 31 ; GFX11-NEXT: s_cbranch_scc0 .LBB73_3 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s42, s13, 16 @@ -121563,47 +122943,47 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 ; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 ; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 -; GFX11-NEXT: v_readlane_b32 s104, v77, 8 -; GFX11-NEXT: v_readlane_b32 s103, v77, 7 -; GFX11-NEXT: v_readlane_b32 s102, v77, 6 -; GFX11-NEXT: v_readlane_b32 s101, v77, 5 -; GFX11-NEXT: v_readlane_b32 s100, v77, 4 -; GFX11-NEXT: v_readlane_b32 s99, v77, 3 -; GFX11-NEXT: v_readlane_b32 s98, v77, 2 -; GFX11-NEXT: v_readlane_b32 s97, v77, 1 -; GFX11-NEXT: v_readlane_b32 s96, v77, 0 -; GFX11-NEXT: v_readlane_b32 s87, v76, 31 -; GFX11-NEXT: v_readlane_b32 s86, v76, 30 -; GFX11-NEXT: v_readlane_b32 s85, v76, 29 -; GFX11-NEXT: v_readlane_b32 s84, v76, 28 -; GFX11-NEXT: v_readlane_b32 s83, v76, 27 -; GFX11-NEXT: v_readlane_b32 s82, v76, 26 -; GFX11-NEXT: v_readlane_b32 s81, v76, 25 -; GFX11-NEXT: v_readlane_b32 s80, v76, 24 -; GFX11-NEXT: v_readlane_b32 s71, v76, 23 -; GFX11-NEXT: v_readlane_b32 s70, v76, 22 -; GFX11-NEXT: v_readlane_b32 s69, v76, 21 -; GFX11-NEXT: v_readlane_b32 s68, v76, 20 -; GFX11-NEXT: v_readlane_b32 s67, v76, 19 -; GFX11-NEXT: v_readlane_b32 s66, v76, 18 -; GFX11-NEXT: v_readlane_b32 s65, v76, 17 -; GFX11-NEXT: v_readlane_b32 s64, v76, 16 -; GFX11-NEXT: v_readlane_b32 s55, v76, 15 -; GFX11-NEXT: v_readlane_b32 s54, v76, 14 -; GFX11-NEXT: v_readlane_b32 s53, v76, 13 -; GFX11-NEXT: v_readlane_b32 s52, v76, 12 -; GFX11-NEXT: v_readlane_b32 s51, v76, 11 -; GFX11-NEXT: v_readlane_b32 s50, v76, 10 -; GFX11-NEXT: v_readlane_b32 s49, v76, 9 -; GFX11-NEXT: v_readlane_b32 s48, v76, 8 -; GFX11-NEXT: v_readlane_b32 s39, v76, 7 -; GFX11-NEXT: v_readlane_b32 s38, v76, 6 -; GFX11-NEXT: v_readlane_b32 s37, v76, 5 -; GFX11-NEXT: v_readlane_b32 s36, v76, 4 -; GFX11-NEXT: v_readlane_b32 s35, v76, 3 -; GFX11-NEXT: v_readlane_b32 s34, v76, 2 -; GFX11-NEXT: v_readlane_b32 s31, v76, 1 -; GFX11-NEXT: v_readlane_b32 s30, v76, 0 +; GFX11-NEXT: v_readlane_b32 s30, v77, 7 +; GFX11-NEXT: v_readlane_b32 s31, v77, 8 +; GFX11-NEXT: v_readlane_b32 s104, v77, 6 +; GFX11-NEXT: v_readlane_b32 s103, v77, 5 +; GFX11-NEXT: v_readlane_b32 s102, v77, 4 +; GFX11-NEXT: v_readlane_b32 s101, v77, 3 +; GFX11-NEXT: v_readlane_b32 s100, v77, 2 +; GFX11-NEXT: v_readlane_b32 s99, v77, 1 +; GFX11-NEXT: v_readlane_b32 s98, v77, 0 +; GFX11-NEXT: v_readlane_b32 s97, v76, 31 +; GFX11-NEXT: v_readlane_b32 s96, v76, 30 +; GFX11-NEXT: v_readlane_b32 s87, v76, 29 +; GFX11-NEXT: v_readlane_b32 s86, v76, 28 +; GFX11-NEXT: v_readlane_b32 s85, v76, 27 +; GFX11-NEXT: v_readlane_b32 s84, v76, 26 +; GFX11-NEXT: v_readlane_b32 s83, v76, 25 +; GFX11-NEXT: v_readlane_b32 s82, v76, 24 +; GFX11-NEXT: v_readlane_b32 s81, v76, 23 +; GFX11-NEXT: v_readlane_b32 s80, v76, 22 +; GFX11-NEXT: v_readlane_b32 s71, v76, 21 +; GFX11-NEXT: v_readlane_b32 s70, v76, 20 +; GFX11-NEXT: v_readlane_b32 s69, v76, 19 +; GFX11-NEXT: v_readlane_b32 s68, v76, 18 +; GFX11-NEXT: v_readlane_b32 s67, v76, 17 +; GFX11-NEXT: v_readlane_b32 s66, v76, 16 +; GFX11-NEXT: v_readlane_b32 s65, v76, 15 +; GFX11-NEXT: v_readlane_b32 s64, v76, 14 +; GFX11-NEXT: v_readlane_b32 s55, v76, 13 +; GFX11-NEXT: v_readlane_b32 s54, v76, 12 +; GFX11-NEXT: v_readlane_b32 s53, v76, 11 +; GFX11-NEXT: v_readlane_b32 s52, v76, 10 +; GFX11-NEXT: v_readlane_b32 s51, v76, 9 +; GFX11-NEXT: v_readlane_b32 s50, v76, 8 +; GFX11-NEXT: v_readlane_b32 s49, v76, 7 +; GFX11-NEXT: v_readlane_b32 s48, v76, 6 +; GFX11-NEXT: v_readlane_b32 s39, v76, 5 +; GFX11-NEXT: v_readlane_b32 s38, v76, 4 +; GFX11-NEXT: v_readlane_b32 s37, v76, 3 +; GFX11-NEXT: v_readlane_b32 s36, v76, 2 +; GFX11-NEXT: v_readlane_b32 s35, v76, 1 +; GFX11-NEXT: v_readlane_b32 s34, v76, 0 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:80 @@ -126370,56 +127750,105 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:592 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:588 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:584 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:580 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:576 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:572 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:568 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:564 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:560 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:556 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:552 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:548 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:544 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:540 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:536 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:532 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:528 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:524 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:520 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:516 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:512 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:508 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:504 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:500 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:496 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:492 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:488 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:484 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:480 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:468 ; GFX11-FAKE16-NEXT: s_clause 0x12 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:456 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:392 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -130691,45 +132120,83 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a, ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:476 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:472 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:468 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:464 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:460 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:456 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:452 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:448 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:444 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:440 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:436 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:432 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:428 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:424 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:420 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:416 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:412 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:408 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:404 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:400 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:396 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:392 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:388 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:384 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:380 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:376 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:372 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:368 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:364 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:360 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:356 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:352 ; GFX11-TRUE16-NEXT: s_clause 0x7 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:348 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:344 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:340 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:336 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:332 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:328 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:324 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:320 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -131632,45 +133099,83 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a, ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:468 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:456 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:392 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:388 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:384 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:380 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:376 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:372 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:368 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:364 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:360 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:356 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:352 ; GFX11-FAKE16-NEXT: s_clause 0x7 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:348 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:344 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:340 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:336 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:332 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:328 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:324 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:320 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24 @@ -133410,44 +134915,57 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_writelane_b32 v63, s30, 0 -; SI-NEXT: v_writelane_b32 v63, s31, 1 -; SI-NEXT: v_writelane_b32 v63, s34, 2 -; SI-NEXT: v_writelane_b32 v63, s35, 3 -; SI-NEXT: v_writelane_b32 v63, s36, 4 -; SI-NEXT: v_writelane_b32 v63, s37, 5 -; SI-NEXT: v_writelane_b32 v63, s38, 6 -; SI-NEXT: v_writelane_b32 v63, s39, 7 -; SI-NEXT: v_writelane_b32 v63, s48, 8 -; SI-NEXT: v_writelane_b32 v63, s49, 9 -; SI-NEXT: v_writelane_b32 v63, s50, 10 -; SI-NEXT: v_writelane_b32 v63, s51, 11 -; SI-NEXT: v_writelane_b32 v63, s52, 12 -; SI-NEXT: v_writelane_b32 v63, s53, 13 -; SI-NEXT: v_writelane_b32 v63, s54, 14 -; SI-NEXT: v_writelane_b32 v63, s55, 15 -; SI-NEXT: v_writelane_b32 v63, s64, 16 -; SI-NEXT: v_writelane_b32 v63, s65, 17 -; SI-NEXT: v_writelane_b32 v63, s66, 18 -; SI-NEXT: v_writelane_b32 v63, s67, 19 -; SI-NEXT: v_writelane_b32 v63, s68, 20 -; SI-NEXT: v_writelane_b32 v63, s69, 21 -; SI-NEXT: v_writelane_b32 v63, s70, 22 -; SI-NEXT: v_writelane_b32 v63, s71, 23 -; SI-NEXT: v_writelane_b32 v63, s80, 24 -; SI-NEXT: v_writelane_b32 v63, s81, 25 -; SI-NEXT: v_writelane_b32 v63, s82, 26 -; SI-NEXT: v_writelane_b32 v63, s83, 27 -; SI-NEXT: v_writelane_b32 v63, s84, 28 -; SI-NEXT: v_writelane_b32 v63, s85, 29 -; SI-NEXT: v_writelane_b32 v63, s86, 30 -; SI-NEXT: v_writelane_b32 v63, s87, 31 -; SI-NEXT: v_writelane_b32 v63, s96, 32 -; SI-NEXT: v_writelane_b32 v63, s97, 33 -; SI-NEXT: v_writelane_b32 v63, s98, 34 +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_writelane_b32 v63, s34, 0 +; SI-NEXT: v_writelane_b32 v63, s35, 1 +; SI-NEXT: v_writelane_b32 v63, s36, 2 +; SI-NEXT: v_writelane_b32 v63, s37, 3 +; SI-NEXT: v_writelane_b32 v63, s38, 4 +; SI-NEXT: v_writelane_b32 v63, s39, 5 +; SI-NEXT: v_writelane_b32 v63, s48, 6 +; SI-NEXT: v_writelane_b32 v63, s49, 7 +; SI-NEXT: v_writelane_b32 v63, s50, 8 +; SI-NEXT: v_writelane_b32 v63, s51, 9 +; SI-NEXT: v_writelane_b32 v63, s52, 10 +; SI-NEXT: v_writelane_b32 v63, s53, 11 +; SI-NEXT: v_writelane_b32 v63, s54, 12 +; SI-NEXT: v_writelane_b32 v63, s55, 13 +; SI-NEXT: v_writelane_b32 v63, s64, 14 +; SI-NEXT: v_writelane_b32 v63, s65, 15 +; SI-NEXT: v_writelane_b32 v63, s66, 16 +; SI-NEXT: v_writelane_b32 v63, s67, 17 +; SI-NEXT: v_writelane_b32 v63, s68, 18 +; SI-NEXT: v_writelane_b32 v63, s69, 19 +; SI-NEXT: v_writelane_b32 v63, s70, 20 +; SI-NEXT: v_writelane_b32 v63, s71, 21 +; SI-NEXT: v_writelane_b32 v63, s80, 22 +; SI-NEXT: v_writelane_b32 v63, s81, 23 +; SI-NEXT: v_writelane_b32 v63, s82, 24 +; SI-NEXT: v_writelane_b32 v63, s83, 25 +; SI-NEXT: v_writelane_b32 v63, s84, 26 +; SI-NEXT: v_writelane_b32 v63, s85, 27 +; SI-NEXT: v_writelane_b32 v63, s86, 28 +; SI-NEXT: v_writelane_b32 v63, s87, 29 +; SI-NEXT: v_writelane_b32 v63, s96, 30 +; SI-NEXT: v_writelane_b32 v63, s97, 31 +; SI-NEXT: v_writelane_b32 v63, s98, 32 +; SI-NEXT: v_writelane_b32 v63, s99, 33 +; SI-NEXT: v_writelane_b32 v63, s30, 34 +; SI-NEXT: v_writelane_b32 v63, s31, 35 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v63, s99, 35 ; SI-NEXT: v_readfirstlane_b32 s44, v1 ; SI-NEXT: v_readfirstlane_b32 s45, v2 ; SI-NEXT: v_readfirstlane_b32 s42, v3 @@ -133467,20 +134985,6 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg ; SI-NEXT: v_readfirstlane_b32 s6, v17 ; SI-NEXT: s_and_b64 s[46:47], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s7, v18 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB77_3 ; SI-NEXT: ; %bb.1: ; %cmp.false @@ -133884,42 +135388,42 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_readlane_b32 s99, v63, 35 -; SI-NEXT: v_readlane_b32 s98, v63, 34 -; SI-NEXT: v_readlane_b32 s97, v63, 33 -; SI-NEXT: v_readlane_b32 s96, v63, 32 -; SI-NEXT: v_readlane_b32 s87, v63, 31 -; SI-NEXT: v_readlane_b32 s86, v63, 30 -; SI-NEXT: v_readlane_b32 s85, v63, 29 -; SI-NEXT: v_readlane_b32 s84, v63, 28 -; SI-NEXT: v_readlane_b32 s83, v63, 27 -; SI-NEXT: v_readlane_b32 s82, v63, 26 -; SI-NEXT: v_readlane_b32 s81, v63, 25 -; SI-NEXT: v_readlane_b32 s80, v63, 24 -; SI-NEXT: v_readlane_b32 s71, v63, 23 -; SI-NEXT: v_readlane_b32 s70, v63, 22 -; SI-NEXT: v_readlane_b32 s69, v63, 21 -; SI-NEXT: v_readlane_b32 s68, v63, 20 -; SI-NEXT: v_readlane_b32 s67, v63, 19 -; SI-NEXT: v_readlane_b32 s66, v63, 18 -; SI-NEXT: v_readlane_b32 s65, v63, 17 -; SI-NEXT: v_readlane_b32 s64, v63, 16 -; SI-NEXT: v_readlane_b32 s55, v63, 15 -; SI-NEXT: v_readlane_b32 s54, v63, 14 -; SI-NEXT: v_readlane_b32 s53, v63, 13 -; SI-NEXT: v_readlane_b32 s52, v63, 12 -; SI-NEXT: v_readlane_b32 s51, v63, 11 -; SI-NEXT: v_readlane_b32 s50, v63, 10 -; SI-NEXT: v_readlane_b32 s49, v63, 9 -; SI-NEXT: v_readlane_b32 s48, v63, 8 -; SI-NEXT: v_readlane_b32 s39, v63, 7 -; SI-NEXT: v_readlane_b32 s38, v63, 6 -; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s36, v63, 4 -; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: v_readlane_b32 s30, v63, 34 +; SI-NEXT: v_readlane_b32 s31, v63, 35 +; SI-NEXT: v_readlane_b32 s99, v63, 33 +; SI-NEXT: v_readlane_b32 s98, v63, 32 +; SI-NEXT: v_readlane_b32 s97, v63, 31 +; SI-NEXT: v_readlane_b32 s96, v63, 30 +; SI-NEXT: v_readlane_b32 s87, v63, 29 +; SI-NEXT: v_readlane_b32 s86, v63, 28 +; SI-NEXT: v_readlane_b32 s85, v63, 27 +; SI-NEXT: v_readlane_b32 s84, v63, 26 +; SI-NEXT: v_readlane_b32 s83, v63, 25 +; SI-NEXT: v_readlane_b32 s82, v63, 24 +; SI-NEXT: v_readlane_b32 s81, v63, 23 +; SI-NEXT: v_readlane_b32 s80, v63, 22 +; SI-NEXT: v_readlane_b32 s71, v63, 21 +; SI-NEXT: v_readlane_b32 s70, v63, 20 +; SI-NEXT: v_readlane_b32 s69, v63, 19 +; SI-NEXT: v_readlane_b32 s68, v63, 18 +; SI-NEXT: v_readlane_b32 s67, v63, 17 +; SI-NEXT: v_readlane_b32 s66, v63, 16 +; SI-NEXT: v_readlane_b32 s65, v63, 15 +; SI-NEXT: v_readlane_b32 s64, v63, 14 +; SI-NEXT: v_readlane_b32 s55, v63, 13 +; SI-NEXT: v_readlane_b32 s54, v63, 12 +; SI-NEXT: v_readlane_b32 s53, v63, 11 +; SI-NEXT: v_readlane_b32 s52, v63, 10 +; SI-NEXT: v_readlane_b32 s51, v63, 9 +; SI-NEXT: v_readlane_b32 s50, v63, 8 +; SI-NEXT: v_readlane_b32 s49, v63, 7 +; SI-NEXT: v_readlane_b32 s48, v63, 6 +; SI-NEXT: v_readlane_b32 s39, v63, 5 +; SI-NEXT: v_readlane_b32 s38, v63, 4 +; SI-NEXT: v_readlane_b32 s37, v63, 3 +; SI-NEXT: v_readlane_b32 s36, v63, 2 +; SI-NEXT: v_readlane_b32 s35, v63, 1 +; SI-NEXT: v_readlane_b32 s34, v63, 0 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 @@ -136073,20 +137577,35 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4 @@ -139122,81 +140641,149 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg ; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v16f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28 ; GFX11-TRUE16-NEXT: s_clause 0x6 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8 @@ -140096,83 +141683,153 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg ; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v16f64_scalar: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164 ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36 ; GFX11-FAKE16-NEXT: s_clause 0x8 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32 +; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7 @@ -141855,6 +143512,22 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a ; SI-LABEL: bitcast_v16f64_to_v64f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: v_readfirstlane_b32 s44, v1 ; SI-NEXT: v_readfirstlane_b32 s45, v2 @@ -141875,22 +143548,6 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a ; SI-NEXT: v_readfirstlane_b32 s4, v17 ; SI-NEXT: s_and_b64 s[46:47], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v18 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB81_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s46, s5, 16 @@ -144566,84 +146223,155 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a ; GFX11-LABEL: bitcast_v64f16_to_v16f64_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 ; GFX11-NEXT: s_clause 0x9 ; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v185, s32 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 ; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 ; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 @@ -145331,22 +147059,6 @@ define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a, ; SI-LABEL: bitcast_v16f64_to_v64i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_mov_b32_e32 v31, s16 -; SI-NEXT: v_mov_b32_e32 v32, s17 -; SI-NEXT: v_mov_b32_e32 v29, s18 -; SI-NEXT: v_mov_b32_e32 v30, s19 -; SI-NEXT: v_mov_b32_e32 v27, s20 -; SI-NEXT: v_mov_b32_e32 v28, s21 -; SI-NEXT: v_mov_b32_e32 v25, s22 -; SI-NEXT: v_mov_b32_e32 v26, s23 -; SI-NEXT: v_mov_b32_e32 v23, s24 -; SI-NEXT: v_mov_b32_e32 v24, s25 -; SI-NEXT: v_mov_b32_e32 v21, s26 -; SI-NEXT: v_mov_b32_e32 v22, s27 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_mov_b32_e32 v19, s28 -; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -145363,6 +147075,22 @@ define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a, ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 +; SI-NEXT: v_mov_b32_e32 v31, s16 +; SI-NEXT: v_mov_b32_e32 v32, s17 +; SI-NEXT: v_mov_b32_e32 v29, s18 +; SI-NEXT: v_mov_b32_e32 v30, s19 +; SI-NEXT: v_mov_b32_e32 v27, s20 +; SI-NEXT: v_mov_b32_e32 v28, s21 +; SI-NEXT: v_mov_b32_e32 v25, s22 +; SI-NEXT: v_mov_b32_e32 v26, s23 +; SI-NEXT: v_mov_b32_e32 v23, s24 +; SI-NEXT: v_mov_b32_e32 v24, s25 +; SI-NEXT: v_mov_b32_e32 v21, s26 +; SI-NEXT: v_mov_b32_e32 v22, s27 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_mov_b32_e32 v19, s28 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: s_cbranch_scc0 .LBB85_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v18 @@ -147474,84 +149202,155 @@ define inreg <16 x double> @bitcast_v64i16_to_v16f64_scalar(<64 x i16> inreg %a, ; GFX11-LABEL: bitcast_v64i16_to_v16f64_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 ; GFX11-NEXT: s_clause 0x9 ; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v185, s32 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 ; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 ; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 ; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 @@ -153080,53 +154879,99 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:580 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:576 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:572 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:568 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:564 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:560 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:556 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:552 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:548 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:544 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:540 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:536 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:532 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:528 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:524 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:520 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:516 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:512 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:508 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:504 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:500 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:496 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:492 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:488 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:484 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:480 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:468 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:456 ; GFX11-FAKE16-NEXT: s_clause 0xf ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:392 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26 @@ -154019,6 +155864,43 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: v_writelane_b32 v41, s34, 0 +; SI-NEXT: v_writelane_b32 v41, s35, 1 +; SI-NEXT: v_writelane_b32 v41, s36, 2 +; SI-NEXT: v_writelane_b32 v41, s37, 3 +; SI-NEXT: v_writelane_b32 v41, s38, 4 +; SI-NEXT: v_writelane_b32 v41, s39, 5 +; SI-NEXT: v_writelane_b32 v41, s48, 6 +; SI-NEXT: v_writelane_b32 v41, s49, 7 +; SI-NEXT: v_writelane_b32 v41, s50, 8 +; SI-NEXT: v_writelane_b32 v41, s51, 9 +; SI-NEXT: v_writelane_b32 v41, s52, 10 +; SI-NEXT: v_writelane_b32 v41, s53, 11 +; SI-NEXT: v_writelane_b32 v41, s54, 12 +; SI-NEXT: v_writelane_b32 v41, s55, 13 +; SI-NEXT: v_writelane_b32 v41, s64, 14 +; SI-NEXT: v_writelane_b32 v41, s65, 15 +; SI-NEXT: v_writelane_b32 v41, s66, 16 +; SI-NEXT: v_writelane_b32 v41, s67, 17 +; SI-NEXT: v_writelane_b32 v41, s68, 18 +; SI-NEXT: v_writelane_b32 v41, s69, 19 +; SI-NEXT: v_writelane_b32 v41, s70, 20 +; SI-NEXT: v_writelane_b32 v41, s71, 21 +; SI-NEXT: v_writelane_b32 v41, s80, 22 +; SI-NEXT: v_writelane_b32 v41, s81, 23 +; SI-NEXT: v_writelane_b32 v41, s82, 24 +; SI-NEXT: v_writelane_b32 v41, s83, 25 +; SI-NEXT: v_writelane_b32 v41, s84, 26 +; SI-NEXT: v_writelane_b32 v41, s85, 27 +; SI-NEXT: v_writelane_b32 v41, s86, 28 +; SI-NEXT: v_writelane_b32 v41, s87, 29 +; SI-NEXT: v_writelane_b32 v41, s96, 30 +; SI-NEXT: v_writelane_b32 v41, s97, 31 +; SI-NEXT: v_writelane_b32 v41, s98, 32 +; SI-NEXT: v_writelane_b32 v41, s99, 33 +; SI-NEXT: v_writelane_b32 v41, s30, 34 +; SI-NEXT: v_writelane_b32 v41, s31, 35 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:328 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324 @@ -154035,44 +155917,8 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: v_writelane_b32 v43, s17, 2 ; SI-NEXT: v_writelane_b32 v43, s16, 3 ; SI-NEXT: s_mov_b32 s60, s24 -; SI-NEXT: v_writelane_b32 v41, s30, 0 -; SI-NEXT: v_writelane_b32 v41, s31, 1 -; SI-NEXT: v_writelane_b32 v41, s34, 2 -; SI-NEXT: v_writelane_b32 v41, s35, 3 -; SI-NEXT: v_writelane_b32 v41, s36, 4 -; SI-NEXT: v_writelane_b32 v41, s37, 5 -; SI-NEXT: v_writelane_b32 v41, s38, 6 -; SI-NEXT: v_writelane_b32 v41, s39, 7 -; SI-NEXT: v_writelane_b32 v41, s48, 8 -; SI-NEXT: v_writelane_b32 v41, s49, 9 -; SI-NEXT: v_writelane_b32 v41, s50, 10 -; SI-NEXT: v_writelane_b32 v41, s51, 11 -; SI-NEXT: v_writelane_b32 v41, s52, 12 -; SI-NEXT: v_writelane_b32 v41, s53, 13 -; SI-NEXT: v_writelane_b32 v41, s54, 14 -; SI-NEXT: v_writelane_b32 v41, s55, 15 -; SI-NEXT: v_writelane_b32 v41, s64, 16 -; SI-NEXT: v_writelane_b32 v41, s65, 17 -; SI-NEXT: v_writelane_b32 v41, s66, 18 -; SI-NEXT: v_writelane_b32 v41, s67, 19 -; SI-NEXT: v_writelane_b32 v41, s68, 20 -; SI-NEXT: v_writelane_b32 v41, s69, 21 -; SI-NEXT: v_writelane_b32 v41, s70, 22 -; SI-NEXT: v_writelane_b32 v41, s71, 23 ; SI-NEXT: s_mov_b32 s77, s28 ; SI-NEXT: s_mov_b32 s76, s27 -; SI-NEXT: v_writelane_b32 v41, s80, 24 -; SI-NEXT: v_writelane_b32 v41, s81, 25 -; SI-NEXT: v_writelane_b32 v41, s82, 26 -; SI-NEXT: v_writelane_b32 v41, s83, 27 -; SI-NEXT: v_writelane_b32 v41, s84, 28 -; SI-NEXT: v_writelane_b32 v41, s85, 29 -; SI-NEXT: v_writelane_b32 v41, s86, 30 -; SI-NEXT: v_writelane_b32 v41, s87, 31 -; SI-NEXT: v_writelane_b32 v41, s96, 32 -; SI-NEXT: v_writelane_b32 v41, s97, 33 -; SI-NEXT: v_writelane_b32 v41, s98, 34 -; SI-NEXT: v_writelane_b32 v41, s99, 35 ; SI-NEXT: s_mov_b32 s79, s26 ; SI-NEXT: v_readfirstlane_b32 s38, v20 ; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane @@ -154102,6 +155948,17 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: v_readfirstlane_b32 s88, v4 ; SI-NEXT: v_readfirstlane_b32 s89, v3 ; SI-NEXT: v_readfirstlane_b32 s90, v9 +; SI-NEXT: v_readfirstlane_b32 s91, v10 +; SI-NEXT: v_readfirstlane_b32 s92, v8 +; SI-NEXT: v_readfirstlane_b32 s93, v7 +; SI-NEXT: v_readfirstlane_b32 s94, v13 +; SI-NEXT: v_readfirstlane_b32 s95, v14 +; SI-NEXT: v_readfirstlane_b32 s30, v17 +; SI-NEXT: v_readfirstlane_b32 s31, v18 +; SI-NEXT: v_readfirstlane_b32 s34, v16 +; SI-NEXT: v_readfirstlane_b32 s35, v15 +; SI-NEXT: v_readfirstlane_b32 s36, v21 +; SI-NEXT: v_readfirstlane_b32 s37, v22 ; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_readfirstlane_b32 s6, v31 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:300 @@ -154137,17 +155994,6 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_waitcnt vmcnt(12) ; SI-NEXT: v_readfirstlane_b32 s4, v38 ; SI-NEXT: v_writelane_b32 v43, s4, 10 -; SI-NEXT: v_readfirstlane_b32 s91, v10 -; SI-NEXT: v_readfirstlane_b32 s92, v8 -; SI-NEXT: v_readfirstlane_b32 s93, v7 -; SI-NEXT: v_readfirstlane_b32 s94, v13 -; SI-NEXT: v_readfirstlane_b32 s95, v14 -; SI-NEXT: v_readfirstlane_b32 s30, v17 -; SI-NEXT: v_readfirstlane_b32 s31, v18 -; SI-NEXT: v_readfirstlane_b32 s34, v16 -; SI-NEXT: v_readfirstlane_b32 s35, v15 -; SI-NEXT: v_readfirstlane_b32 s36, v21 -; SI-NEXT: v_readfirstlane_b32 s37, v22 ; SI-NEXT: s_waitcnt vmcnt(11) ; SI-NEXT: v_readfirstlane_b32 s4, v31 ; SI-NEXT: v_writelane_b32 v43, s4, 11 @@ -155626,42 +157472,42 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; SI-NEXT: v_readlane_b32 s99, v41, 35 -; SI-NEXT: v_readlane_b32 s98, v41, 34 -; SI-NEXT: v_readlane_b32 s97, v41, 33 -; SI-NEXT: v_readlane_b32 s96, v41, 32 -; SI-NEXT: v_readlane_b32 s87, v41, 31 -; SI-NEXT: v_readlane_b32 s86, v41, 30 -; SI-NEXT: v_readlane_b32 s85, v41, 29 -; SI-NEXT: v_readlane_b32 s84, v41, 28 -; SI-NEXT: v_readlane_b32 s83, v41, 27 -; SI-NEXT: v_readlane_b32 s82, v41, 26 -; SI-NEXT: v_readlane_b32 s81, v41, 25 -; SI-NEXT: v_readlane_b32 s80, v41, 24 -; SI-NEXT: v_readlane_b32 s71, v41, 23 -; SI-NEXT: v_readlane_b32 s70, v41, 22 -; SI-NEXT: v_readlane_b32 s69, v41, 21 -; SI-NEXT: v_readlane_b32 s68, v41, 20 -; SI-NEXT: v_readlane_b32 s67, v41, 19 -; SI-NEXT: v_readlane_b32 s66, v41, 18 -; SI-NEXT: v_readlane_b32 s65, v41, 17 -; SI-NEXT: v_readlane_b32 s64, v41, 16 -; SI-NEXT: v_readlane_b32 s55, v41, 15 -; SI-NEXT: v_readlane_b32 s54, v41, 14 -; SI-NEXT: v_readlane_b32 s53, v41, 13 -; SI-NEXT: v_readlane_b32 s52, v41, 12 -; SI-NEXT: v_readlane_b32 s51, v41, 11 -; SI-NEXT: v_readlane_b32 s50, v41, 10 -; SI-NEXT: v_readlane_b32 s49, v41, 9 -; SI-NEXT: v_readlane_b32 s48, v41, 8 -; SI-NEXT: v_readlane_b32 s39, v41, 7 -; SI-NEXT: v_readlane_b32 s38, v41, 6 -; SI-NEXT: v_readlane_b32 s37, v41, 5 -; SI-NEXT: v_readlane_b32 s36, v41, 4 -; SI-NEXT: v_readlane_b32 s35, v41, 3 -; SI-NEXT: v_readlane_b32 s34, v41, 2 -; SI-NEXT: v_readlane_b32 s31, v41, 1 -; SI-NEXT: v_readlane_b32 s30, v41, 0 +; SI-NEXT: v_readlane_b32 s30, v41, 34 +; SI-NEXT: v_readlane_b32 s31, v41, 35 +; SI-NEXT: v_readlane_b32 s99, v41, 33 +; SI-NEXT: v_readlane_b32 s98, v41, 32 +; SI-NEXT: v_readlane_b32 s97, v41, 31 +; SI-NEXT: v_readlane_b32 s96, v41, 30 +; SI-NEXT: v_readlane_b32 s87, v41, 29 +; SI-NEXT: v_readlane_b32 s86, v41, 28 +; SI-NEXT: v_readlane_b32 s85, v41, 27 +; SI-NEXT: v_readlane_b32 s84, v41, 26 +; SI-NEXT: v_readlane_b32 s83, v41, 25 +; SI-NEXT: v_readlane_b32 s82, v41, 24 +; SI-NEXT: v_readlane_b32 s81, v41, 23 +; SI-NEXT: v_readlane_b32 s80, v41, 22 +; SI-NEXT: v_readlane_b32 s71, v41, 21 +; SI-NEXT: v_readlane_b32 s70, v41, 20 +; SI-NEXT: v_readlane_b32 s69, v41, 19 +; SI-NEXT: v_readlane_b32 s68, v41, 18 +; SI-NEXT: v_readlane_b32 s67, v41, 17 +; SI-NEXT: v_readlane_b32 s66, v41, 16 +; SI-NEXT: v_readlane_b32 s65, v41, 15 +; SI-NEXT: v_readlane_b32 s64, v41, 14 +; SI-NEXT: v_readlane_b32 s55, v41, 13 +; SI-NEXT: v_readlane_b32 s54, v41, 12 +; SI-NEXT: v_readlane_b32 s53, v41, 11 +; SI-NEXT: v_readlane_b32 s52, v41, 10 +; SI-NEXT: v_readlane_b32 s51, v41, 9 +; SI-NEXT: v_readlane_b32 s50, v41, 8 +; SI-NEXT: v_readlane_b32 s49, v41, 7 +; SI-NEXT: v_readlane_b32 s48, v41, 6 +; SI-NEXT: v_readlane_b32 s39, v41, 5 +; SI-NEXT: v_readlane_b32 s38, v41, 4 +; SI-NEXT: v_readlane_b32 s37, v41, 3 +; SI-NEXT: v_readlane_b32 s36, v41, 2 +; SI-NEXT: v_readlane_b32 s35, v41, 1 +; SI-NEXT: v_readlane_b32 s34, v41, 0 ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload @@ -157861,35 +159707,65 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1e ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:440 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:436 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:432 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:428 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:424 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:420 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:416 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:412 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:408 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:404 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:400 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:396 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:392 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:388 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:384 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:380 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:376 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:372 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:368 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:364 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:360 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:356 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:352 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:348 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:344 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:340 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:336 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:332 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:328 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:324 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:320 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26 @@ -158633,35 +160509,65 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1e ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:392 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:388 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:384 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:380 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:376 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:372 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:368 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:364 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:360 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:356 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:352 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:348 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:344 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:340 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:336 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:332 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:328 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:324 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:320 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26 @@ -164681,65 +166587,123 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:124 ; GFX11-TRUE16-NEXT: s_clause 0x1b ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:12 ; GFX11-TRUE16-NEXT: s_clause 0x2 ; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:8 @@ -165848,26 +167812,47 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x15 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:96 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:92 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:36 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:12 ; GFX11-FAKE16-NEXT: s_clause 0x2 ; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8 @@ -167055,6 +169040,42 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: v_writelane_b32 v63, s34, 0 +; SI-NEXT: v_writelane_b32 v63, s35, 1 +; SI-NEXT: v_writelane_b32 v63, s36, 2 +; SI-NEXT: v_writelane_b32 v63, s37, 3 +; SI-NEXT: v_writelane_b32 v63, s38, 4 +; SI-NEXT: v_writelane_b32 v63, s39, 5 +; SI-NEXT: v_writelane_b32 v63, s48, 6 +; SI-NEXT: v_writelane_b32 v63, s49, 7 +; SI-NEXT: v_writelane_b32 v63, s50, 8 +; SI-NEXT: v_writelane_b32 v63, s51, 9 +; SI-NEXT: v_writelane_b32 v63, s52, 10 +; SI-NEXT: v_writelane_b32 v63, s53, 11 +; SI-NEXT: v_writelane_b32 v63, s54, 12 +; SI-NEXT: v_writelane_b32 v63, s55, 13 +; SI-NEXT: v_writelane_b32 v63, s64, 14 +; SI-NEXT: v_writelane_b32 v63, s65, 15 +; SI-NEXT: v_writelane_b32 v63, s66, 16 +; SI-NEXT: v_writelane_b32 v63, s67, 17 +; SI-NEXT: v_writelane_b32 v63, s68, 18 +; SI-NEXT: v_writelane_b32 v63, s69, 19 +; SI-NEXT: v_writelane_b32 v63, s70, 20 +; SI-NEXT: v_writelane_b32 v63, s71, 21 +; SI-NEXT: v_writelane_b32 v63, s80, 22 +; SI-NEXT: v_writelane_b32 v63, s81, 23 +; SI-NEXT: v_writelane_b32 v63, s82, 24 +; SI-NEXT: v_writelane_b32 v63, s83, 25 +; SI-NEXT: v_writelane_b32 v63, s84, 26 +; SI-NEXT: v_writelane_b32 v63, s85, 27 +; SI-NEXT: v_writelane_b32 v63, s86, 28 +; SI-NEXT: v_writelane_b32 v63, s87, 29 +; SI-NEXT: v_writelane_b32 v63, s96, 30 +; SI-NEXT: v_writelane_b32 v63, s97, 31 +; SI-NEXT: v_writelane_b32 v63, s98, 32 +; SI-NEXT: v_writelane_b32 v63, s99, 33 +; SI-NEXT: v_writelane_b32 v63, s30, 34 +; SI-NEXT: v_writelane_b32 v63, s31, 35 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 ; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 @@ -167076,62 +169097,26 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64 ; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76 ; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:72 -; SI-NEXT: v_writelane_b32 v63, s30, 0 -; SI-NEXT: v_writelane_b32 v63, s31, 1 -; SI-NEXT: v_writelane_b32 v63, s34, 2 -; SI-NEXT: v_writelane_b32 v63, s35, 3 -; SI-NEXT: v_writelane_b32 v63, s36, 4 -; SI-NEXT: v_writelane_b32 v63, s37, 5 -; SI-NEXT: v_writelane_b32 v63, s38, 6 -; SI-NEXT: v_writelane_b32 v63, s39, 7 -; SI-NEXT: v_writelane_b32 v63, s48, 8 -; SI-NEXT: v_writelane_b32 v63, s49, 9 -; SI-NEXT: v_writelane_b32 v63, s50, 10 -; SI-NEXT: v_writelane_b32 v63, s51, 11 -; SI-NEXT: v_writelane_b32 v63, s52, 12 -; SI-NEXT: v_writelane_b32 v63, s53, 13 -; SI-NEXT: v_writelane_b32 v63, s54, 14 -; SI-NEXT: v_writelane_b32 v63, s55, 15 -; SI-NEXT: v_writelane_b32 v63, s64, 16 -; SI-NEXT: v_writelane_b32 v63, s65, 17 -; SI-NEXT: v_writelane_b32 v63, s66, 18 -; SI-NEXT: v_writelane_b32 v63, s67, 19 -; SI-NEXT: v_writelane_b32 v63, s68, 20 -; SI-NEXT: v_writelane_b32 v63, s69, 21 -; SI-NEXT: v_writelane_b32 v63, s70, 22 -; SI-NEXT: v_writelane_b32 v63, s71, 23 -; SI-NEXT: v_writelane_b32 v63, s80, 24 -; SI-NEXT: v_writelane_b32 v63, s81, 25 -; SI-NEXT: v_writelane_b32 v63, s82, 26 -; SI-NEXT: v_writelane_b32 v63, s83, 27 ; SI-NEXT: s_waitcnt expcnt(5) ; SI-NEXT: v_mul_f32_e32 v56, 1.0, v2 ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10 -; SI-NEXT: v_writelane_b32 v63, s84, 28 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9 -; SI-NEXT: v_writelane_b32 v63, s85, 29 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14 -; SI-NEXT: v_writelane_b32 v63, s86, 30 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15 -; SI-NEXT: v_writelane_b32 v63, s87, 31 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18 -; SI-NEXT: v_writelane_b32 v63, s96, 32 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v26 -; SI-NEXT: v_writelane_b32 v63, s97, 33 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; SI-NEXT: v_writelane_b32 v63, s98, 34 ; SI-NEXT: v_mov_b32_e32 v46, v21 -; SI-NEXT: v_writelane_b32 v63, s99, 35 ; SI-NEXT: v_mul_f32_e32 v47, 1.0, v1 ; SI-NEXT: v_mul_f32_e32 v32, 1.0, v4 ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3 @@ -167141,8 +169126,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7 ; SI-NEXT: v_mul_f32_e32 v5, 1.0, v12 ; SI-NEXT: v_mul_f32_e32 v60, 1.0, v11 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13 ; SI-NEXT: v_mul_f32_e32 v21, 1.0, v16 ; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17 @@ -167150,18 +169133,29 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: v_mul_f32_e32 v12, 1.0, v19 ; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22 ; SI-NEXT: v_mul_f32_e32 v20, 1.0, v46 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v48 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill ; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24 ; SI-NEXT: v_mul_f32_e32 v46, 1.0, v23 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52 ; SI-NEXT: v_mul_f32_e32 v26, 1.0, v25 ; SI-NEXT: v_mul_f32_e32 v57, 1.0, v28 ; SI-NEXT: v_mul_f32_e32 v16, 1.0, v27 ; SI-NEXT: v_mul_f32_e32 v28, 1.0, v30 ; SI-NEXT: v_mul_f32_e32 v30, 1.0, v29 +; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16 +; SI-NEXT: v_mul_f32_e64 v3, 1.0, s19 +; SI-NEXT: v_mul_f32_e64 v4, 1.0, s18 +; SI-NEXT: v_mul_f32_e64 v14, 1.0, s21 +; SI-NEXT: v_mul_f32_e64 v15, 1.0, s20 +; SI-NEXT: v_mul_f32_e64 v7, 1.0, s23 +; SI-NEXT: v_mul_f32_e64 v6, 1.0, s22 +; SI-NEXT: v_mul_f32_e64 v18, 1.0, s25 +; SI-NEXT: v_mul_f32_e64 v19, 1.0, s24 +; SI-NEXT: v_mul_f32_e64 v10, 1.0, s27 +; SI-NEXT: v_mul_f32_e64 v8, 1.0, s26 +; SI-NEXT: v_mul_f32_e64 v23, 1.0, s29 +; SI-NEXT: v_mul_f32_e64 v25, 1.0, s28 +; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: v_mul_f32_e32 v31, 1.0, v33 ; SI-NEXT: v_mul_f32_e32 v27, 1.0, v34 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec @@ -167169,8 +169163,13 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: v_mul_f32_e32 v36, 1.0, v36 ; SI-NEXT: v_mul_f32_e32 v35, 1.0, v37 ; SI-NEXT: v_mul_f32_e32 v34, 1.0, v38 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v2, 1.0, v48 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill ; SI-NEXT: v_mul_f32_e32 v37, 1.0, v39 ; SI-NEXT: v_mul_f32_e32 v48, 1.0, v49 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52 ; SI-NEXT: v_mul_f32_e32 v39, 1.0, v50 ; SI-NEXT: v_mul_f32_e32 v33, 1.0, v51 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill @@ -167191,20 +169190,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: v_mul_f32_e32 v53, 1.0, v45 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v2, 1.0, s17 -; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16 -; SI-NEXT: v_mul_f32_e64 v3, 1.0, s19 -; SI-NEXT: v_mul_f32_e64 v4, 1.0, s18 -; SI-NEXT: v_mul_f32_e64 v14, 1.0, s21 -; SI-NEXT: v_mul_f32_e64 v15, 1.0, s20 -; SI-NEXT: v_mul_f32_e64 v7, 1.0, s23 -; SI-NEXT: v_mul_f32_e64 v6, 1.0, s22 -; SI-NEXT: v_mul_f32_e64 v18, 1.0, s25 -; SI-NEXT: v_mul_f32_e64 v19, 1.0, s24 -; SI-NEXT: v_mul_f32_e64 v10, 1.0, s27 -; SI-NEXT: v_mul_f32_e64 v8, 1.0, s26 -; SI-NEXT: v_mul_f32_e64 v23, 1.0, s29 -; SI-NEXT: v_mul_f32_e64 v25, 1.0, s28 -; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill @@ -168240,24 +170225,23 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; SI-NEXT: s_lshl_b32 s4, s4, 8 ; SI-NEXT: v_readlane_b32 s7, v62, 1 -; SI-NEXT: v_readlane_b32 s99, v63, 35 -; SI-NEXT: v_readlane_b32 s97, v63, 33 -; SI-NEXT: v_readlane_b32 s87, v63, 31 -; SI-NEXT: v_readlane_b32 s85, v63, 29 -; SI-NEXT: v_readlane_b32 s83, v63, 27 -; SI-NEXT: v_readlane_b32 s81, v63, 25 -; SI-NEXT: v_readlane_b32 s71, v63, 23 -; SI-NEXT: v_readlane_b32 s69, v63, 21 -; SI-NEXT: v_readlane_b32 s67, v63, 19 -; SI-NEXT: v_readlane_b32 s65, v63, 17 -; SI-NEXT: v_readlane_b32 s55, v63, 15 -; SI-NEXT: v_readlane_b32 s53, v63, 13 -; SI-NEXT: v_readlane_b32 s51, v63, 11 -; SI-NEXT: v_readlane_b32 s49, v63, 9 -; SI-NEXT: v_readlane_b32 s39, v63, 7 -; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s31, v63, 1 +; SI-NEXT: v_readlane_b32 s99, v63, 33 +; SI-NEXT: v_readlane_b32 s97, v63, 31 +; SI-NEXT: v_readlane_b32 s87, v63, 29 +; SI-NEXT: v_readlane_b32 s85, v63, 27 +; SI-NEXT: v_readlane_b32 s83, v63, 25 +; SI-NEXT: v_readlane_b32 s81, v63, 23 +; SI-NEXT: v_readlane_b32 s71, v63, 21 +; SI-NEXT: v_readlane_b32 s69, v63, 19 +; SI-NEXT: v_readlane_b32 s67, v63, 17 +; SI-NEXT: v_readlane_b32 s65, v63, 15 +; SI-NEXT: v_readlane_b32 s55, v63, 13 +; SI-NEXT: v_readlane_b32 s53, v63, 11 +; SI-NEXT: v_readlane_b32 s51, v63, 9 +; SI-NEXT: v_readlane_b32 s49, v63, 7 +; SI-NEXT: v_readlane_b32 s39, v63, 5 +; SI-NEXT: v_readlane_b32 s37, v63, 3 +; SI-NEXT: v_readlane_b32 s35, v63, 1 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 @@ -168467,7 +170451,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; SI-NEXT: s_lshl_b32 s5, s34, 8 ; SI-NEXT: s_lshl_b32 s6, s90, 24 -; SI-NEXT: v_readlane_b32 s34, v63, 2 +; SI-NEXT: v_readlane_b32 s34, v63, 0 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 @@ -168498,8 +170482,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; SI-NEXT: s_lshl_b32 s5, s38, 8 ; SI-NEXT: s_lshl_b32 s6, s30, 24 -; SI-NEXT: v_readlane_b32 s38, v63, 6 -; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: v_readlane_b32 s30, v63, 34 +; SI-NEXT: v_readlane_b32 s31, v63, 35 +; SI-NEXT: v_readlane_b32 s38, v63, 4 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 @@ -168527,9 +170512,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: s_lshl_b32 s5, s52, 8 ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload ; SI-NEXT: s_lshl_b32 s6, s48, 24 -; SI-NEXT: v_readlane_b32 s52, v63, 12 -; SI-NEXT: v_readlane_b32 s48, v63, 8 -; SI-NEXT: v_readlane_b32 s36, v63, 4 +; SI-NEXT: v_readlane_b32 s52, v63, 10 +; SI-NEXT: v_readlane_b32 s48, v63, 6 +; SI-NEXT: v_readlane_b32 s36, v63, 2 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 @@ -168562,9 +170547,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload ; SI-NEXT: s_lshl_b32 s5, s68, 8 ; SI-NEXT: s_lshl_b32 s6, s54, 24 -; SI-NEXT: v_readlane_b32 s68, v63, 20 -; SI-NEXT: v_readlane_b32 s54, v63, 14 -; SI-NEXT: v_readlane_b32 s50, v63, 10 +; SI-NEXT: v_readlane_b32 s68, v63, 18 +; SI-NEXT: v_readlane_b32 s54, v63, 12 +; SI-NEXT: v_readlane_b32 s50, v63, 8 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 @@ -168599,9 +170584,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; SI-NEXT: s_lshl_b32 s5, s82, 8 ; SI-NEXT: s_lshl_b32 s6, s66, 24 -; SI-NEXT: v_readlane_b32 s82, v63, 26 -; SI-NEXT: v_readlane_b32 s66, v63, 18 -; SI-NEXT: v_readlane_b32 s64, v63, 16 +; SI-NEXT: v_readlane_b32 s82, v63, 24 +; SI-NEXT: v_readlane_b32 s66, v63, 16 +; SI-NEXT: v_readlane_b32 s64, v63, 14 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 @@ -168629,9 +170614,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload ; SI-NEXT: s_lshl_b32 s5, s96, 8 ; SI-NEXT: s_lshl_b32 s6, s80, 24 -; SI-NEXT: v_readlane_b32 s96, v63, 32 -; SI-NEXT: v_readlane_b32 s80, v63, 24 -; SI-NEXT: v_readlane_b32 s70, v63, 22 +; SI-NEXT: v_readlane_b32 s96, v63, 30 +; SI-NEXT: v_readlane_b32 s80, v63, 22 +; SI-NEXT: v_readlane_b32 s70, v63, 20 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; SI-NEXT: v_or_b32_e32 v1, v1, v2 @@ -168663,8 +170648,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: v_and_b32_e32 v1, 0xff, v46 ; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload ; SI-NEXT: s_lshl_b32 s5, s86, 24 -; SI-NEXT: v_readlane_b32 s86, v63, 30 -; SI-NEXT: v_readlane_b32 s84, v63, 28 +; SI-NEXT: v_readlane_b32 s86, v63, 28 +; SI-NEXT: v_readlane_b32 s84, v63, 26 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; SI-NEXT: v_or_b32_e32 v1, v1, v2 @@ -168696,7 +170681,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xff, v38 -; SI-NEXT: v_readlane_b32 s98, v63, 34 +; SI-NEXT: v_readlane_b32 s98, v63, 32 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; SI-NEXT: v_or_b32_e32 v1, v1, v2 @@ -168736,39 +170721,53 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v63, s30, 0 -; VI-NEXT: v_writelane_b32 v63, s31, 1 -; VI-NEXT: v_writelane_b32 v63, s34, 2 -; VI-NEXT: v_writelane_b32 v63, s35, 3 -; VI-NEXT: v_writelane_b32 v63, s36, 4 -; VI-NEXT: v_writelane_b32 v63, s37, 5 -; VI-NEXT: v_writelane_b32 v63, s38, 6 -; VI-NEXT: v_writelane_b32 v63, s39, 7 -; VI-NEXT: v_writelane_b32 v63, s48, 8 -; VI-NEXT: v_writelane_b32 v63, s49, 9 -; VI-NEXT: v_writelane_b32 v63, s50, 10 -; VI-NEXT: v_writelane_b32 v63, s51, 11 -; VI-NEXT: v_writelane_b32 v63, s52, 12 -; VI-NEXT: v_writelane_b32 v63, s53, 13 -; VI-NEXT: v_writelane_b32 v63, s54, 14 -; VI-NEXT: v_writelane_b32 v63, s55, 15 -; VI-NEXT: v_writelane_b32 v63, s64, 16 -; VI-NEXT: v_writelane_b32 v63, s65, 17 -; VI-NEXT: v_writelane_b32 v63, s66, 18 -; VI-NEXT: v_writelane_b32 v63, s67, 19 -; VI-NEXT: v_writelane_b32 v63, s68, 20 -; VI-NEXT: v_writelane_b32 v63, s69, 21 -; VI-NEXT: v_writelane_b32 v63, s70, 22 -; VI-NEXT: v_writelane_b32 v63, s71, 23 -; VI-NEXT: v_writelane_b32 v63, s80, 24 -; VI-NEXT: v_writelane_b32 v63, s81, 25 -; VI-NEXT: v_writelane_b32 v63, s82, 26 -; VI-NEXT: v_writelane_b32 v63, s83, 27 -; VI-NEXT: v_writelane_b32 v63, s84, 28 -; VI-NEXT: v_writelane_b32 v63, s85, 29 -; VI-NEXT: v_writelane_b32 v63, s86, 30 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_writelane_b32 v63, s34, 0 +; VI-NEXT: v_writelane_b32 v63, s35, 1 +; VI-NEXT: v_writelane_b32 v63, s36, 2 +; VI-NEXT: v_writelane_b32 v63, s37, 3 +; VI-NEXT: v_writelane_b32 v63, s38, 4 +; VI-NEXT: v_writelane_b32 v63, s39, 5 +; VI-NEXT: v_writelane_b32 v63, s48, 6 +; VI-NEXT: v_writelane_b32 v63, s49, 7 +; VI-NEXT: v_writelane_b32 v63, s50, 8 +; VI-NEXT: v_writelane_b32 v63, s51, 9 +; VI-NEXT: v_writelane_b32 v63, s52, 10 +; VI-NEXT: v_writelane_b32 v63, s53, 11 +; VI-NEXT: v_writelane_b32 v63, s54, 12 +; VI-NEXT: v_writelane_b32 v63, s55, 13 +; VI-NEXT: v_writelane_b32 v63, s64, 14 +; VI-NEXT: v_writelane_b32 v63, s65, 15 +; VI-NEXT: v_writelane_b32 v63, s66, 16 +; VI-NEXT: v_writelane_b32 v63, s67, 17 +; VI-NEXT: v_writelane_b32 v63, s68, 18 +; VI-NEXT: v_writelane_b32 v63, s69, 19 +; VI-NEXT: v_writelane_b32 v63, s70, 20 +; VI-NEXT: v_writelane_b32 v63, s71, 21 +; VI-NEXT: v_writelane_b32 v63, s80, 22 +; VI-NEXT: v_writelane_b32 v63, s81, 23 +; VI-NEXT: v_writelane_b32 v63, s82, 24 +; VI-NEXT: v_writelane_b32 v63, s83, 25 +; VI-NEXT: v_writelane_b32 v63, s84, 26 +; VI-NEXT: v_writelane_b32 v63, s85, 27 +; VI-NEXT: v_writelane_b32 v63, s86, 28 +; VI-NEXT: v_writelane_b32 v63, s87, 29 +; VI-NEXT: v_writelane_b32 v63, s30, 30 +; VI-NEXT: v_writelane_b32 v63, s31, 31 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v63, s87, 31 ; VI-NEXT: v_readfirstlane_b32 s44, v3 ; VI-NEXT: v_readfirstlane_b32 s45, v4 ; VI-NEXT: v_readfirstlane_b32 s42, v5 @@ -168788,20 +170787,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; VI-NEXT: v_readfirstlane_b32 s4, v1 ; VI-NEXT: s_and_b64 s[46:47], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v2 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB91_3 ; VI-NEXT: ; %bb.1: ; %cmp.false @@ -170160,38 +172145,38 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; VI-NEXT: v_lshlrev_b32_e32 v36, 8, v33 ; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload ; VI-NEXT: v_or_b32_sdwa v17, v17, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_readlane_b32 s87, v63, 31 -; VI-NEXT: v_readlane_b32 s86, v63, 30 -; VI-NEXT: v_readlane_b32 s85, v63, 29 -; VI-NEXT: v_readlane_b32 s84, v63, 28 -; VI-NEXT: v_readlane_b32 s83, v63, 27 -; VI-NEXT: v_readlane_b32 s82, v63, 26 -; VI-NEXT: v_readlane_b32 s81, v63, 25 -; VI-NEXT: v_readlane_b32 s80, v63, 24 -; VI-NEXT: v_readlane_b32 s71, v63, 23 -; VI-NEXT: v_readlane_b32 s70, v63, 22 -; VI-NEXT: v_readlane_b32 s69, v63, 21 -; VI-NEXT: v_readlane_b32 s68, v63, 20 -; VI-NEXT: v_readlane_b32 s67, v63, 19 -; VI-NEXT: v_readlane_b32 s66, v63, 18 -; VI-NEXT: v_readlane_b32 s65, v63, 17 -; VI-NEXT: v_readlane_b32 s64, v63, 16 -; VI-NEXT: v_readlane_b32 s55, v63, 15 -; VI-NEXT: v_readlane_b32 s54, v63, 14 -; VI-NEXT: v_readlane_b32 s53, v63, 13 -; VI-NEXT: v_readlane_b32 s52, v63, 12 -; VI-NEXT: v_readlane_b32 s51, v63, 11 -; VI-NEXT: v_readlane_b32 s50, v63, 10 -; VI-NEXT: v_readlane_b32 s49, v63, 9 -; VI-NEXT: v_readlane_b32 s48, v63, 8 -; VI-NEXT: v_readlane_b32 s39, v63, 7 -; VI-NEXT: v_readlane_b32 s38, v63, 6 -; VI-NEXT: v_readlane_b32 s37, v63, 5 -; VI-NEXT: v_readlane_b32 s36, v63, 4 -; VI-NEXT: v_readlane_b32 s35, v63, 3 -; VI-NEXT: v_readlane_b32 s34, v63, 2 -; VI-NEXT: v_readlane_b32 s31, v63, 1 -; VI-NEXT: v_readlane_b32 s30, v63, 0 +; VI-NEXT: v_readlane_b32 s30, v63, 30 +; VI-NEXT: v_readlane_b32 s31, v63, 31 +; VI-NEXT: v_readlane_b32 s87, v63, 29 +; VI-NEXT: v_readlane_b32 s86, v63, 28 +; VI-NEXT: v_readlane_b32 s85, v63, 27 +; VI-NEXT: v_readlane_b32 s84, v63, 26 +; VI-NEXT: v_readlane_b32 s83, v63, 25 +; VI-NEXT: v_readlane_b32 s82, v63, 24 +; VI-NEXT: v_readlane_b32 s81, v63, 23 +; VI-NEXT: v_readlane_b32 s80, v63, 22 +; VI-NEXT: v_readlane_b32 s71, v63, 21 +; VI-NEXT: v_readlane_b32 s70, v63, 20 +; VI-NEXT: v_readlane_b32 s69, v63, 19 +; VI-NEXT: v_readlane_b32 s68, v63, 18 +; VI-NEXT: v_readlane_b32 s67, v63, 17 +; VI-NEXT: v_readlane_b32 s66, v63, 16 +; VI-NEXT: v_readlane_b32 s65, v63, 15 +; VI-NEXT: v_readlane_b32 s64, v63, 14 +; VI-NEXT: v_readlane_b32 s55, v63, 13 +; VI-NEXT: v_readlane_b32 s54, v63, 12 +; VI-NEXT: v_readlane_b32 s53, v63, 11 +; VI-NEXT: v_readlane_b32 s52, v63, 10 +; VI-NEXT: v_readlane_b32 s51, v63, 9 +; VI-NEXT: v_readlane_b32 s50, v63, 8 +; VI-NEXT: v_readlane_b32 s49, v63, 7 +; VI-NEXT: v_readlane_b32 s48, v63, 6 +; VI-NEXT: v_readlane_b32 s39, v63, 5 +; VI-NEXT: v_readlane_b32 s38, v63, 4 +; VI-NEXT: v_readlane_b32 s37, v63, 3 +; VI-NEXT: v_readlane_b32 s36, v63, 2 +; VI-NEXT: v_readlane_b32 s35, v63, 1 +; VI-NEXT: v_readlane_b32 s34, v63, 0 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_lshlrev_b32_e32 v36, 8, v33 ; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload @@ -170590,43 +172575,57 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v63, s30, 0 -; GFX9-NEXT: v_writelane_b32 v63, s31, 1 -; GFX9-NEXT: v_writelane_b32 v63, s34, 2 -; GFX9-NEXT: v_writelane_b32 v63, s35, 3 -; GFX9-NEXT: v_writelane_b32 v63, s36, 4 -; GFX9-NEXT: v_writelane_b32 v63, s37, 5 -; GFX9-NEXT: v_writelane_b32 v63, s38, 6 -; GFX9-NEXT: v_writelane_b32 v63, s39, 7 -; GFX9-NEXT: v_writelane_b32 v63, s48, 8 -; GFX9-NEXT: v_writelane_b32 v63, s49, 9 -; GFX9-NEXT: v_writelane_b32 v63, s50, 10 -; GFX9-NEXT: v_writelane_b32 v63, s51, 11 -; GFX9-NEXT: v_writelane_b32 v63, s52, 12 -; GFX9-NEXT: v_writelane_b32 v63, s53, 13 -; GFX9-NEXT: v_writelane_b32 v63, s54, 14 -; GFX9-NEXT: v_writelane_b32 v63, s55, 15 -; GFX9-NEXT: v_writelane_b32 v63, s64, 16 -; GFX9-NEXT: v_writelane_b32 v63, s65, 17 -; GFX9-NEXT: v_writelane_b32 v63, s66, 18 -; GFX9-NEXT: v_writelane_b32 v63, s67, 19 -; GFX9-NEXT: v_writelane_b32 v63, s68, 20 -; GFX9-NEXT: v_writelane_b32 v63, s69, 21 -; GFX9-NEXT: v_writelane_b32 v63, s70, 22 -; GFX9-NEXT: v_writelane_b32 v63, s71, 23 -; GFX9-NEXT: v_writelane_b32 v63, s80, 24 -; GFX9-NEXT: v_writelane_b32 v63, s81, 25 -; GFX9-NEXT: v_writelane_b32 v63, s82, 26 -; GFX9-NEXT: v_writelane_b32 v63, s83, 27 -; GFX9-NEXT: v_writelane_b32 v63, s84, 28 -; GFX9-NEXT: v_writelane_b32 v63, s85, 29 -; GFX9-NEXT: v_writelane_b32 v63, s86, 30 -; GFX9-NEXT: v_writelane_b32 v63, s87, 31 -; GFX9-NEXT: v_writelane_b32 v63, s96, 32 -; GFX9-NEXT: v_writelane_b32 v63, s97, 33 -; GFX9-NEXT: v_writelane_b32 v63, s98, 34 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v63, s34, 0 +; GFX9-NEXT: v_writelane_b32 v63, s35, 1 +; GFX9-NEXT: v_writelane_b32 v63, s36, 2 +; GFX9-NEXT: v_writelane_b32 v63, s37, 3 +; GFX9-NEXT: v_writelane_b32 v63, s38, 4 +; GFX9-NEXT: v_writelane_b32 v63, s39, 5 +; GFX9-NEXT: v_writelane_b32 v63, s48, 6 +; GFX9-NEXT: v_writelane_b32 v63, s49, 7 +; GFX9-NEXT: v_writelane_b32 v63, s50, 8 +; GFX9-NEXT: v_writelane_b32 v63, s51, 9 +; GFX9-NEXT: v_writelane_b32 v63, s52, 10 +; GFX9-NEXT: v_writelane_b32 v63, s53, 11 +; GFX9-NEXT: v_writelane_b32 v63, s54, 12 +; GFX9-NEXT: v_writelane_b32 v63, s55, 13 +; GFX9-NEXT: v_writelane_b32 v63, s64, 14 +; GFX9-NEXT: v_writelane_b32 v63, s65, 15 +; GFX9-NEXT: v_writelane_b32 v63, s66, 16 +; GFX9-NEXT: v_writelane_b32 v63, s67, 17 +; GFX9-NEXT: v_writelane_b32 v63, s68, 18 +; GFX9-NEXT: v_writelane_b32 v63, s69, 19 +; GFX9-NEXT: v_writelane_b32 v63, s70, 20 +; GFX9-NEXT: v_writelane_b32 v63, s71, 21 +; GFX9-NEXT: v_writelane_b32 v63, s80, 22 +; GFX9-NEXT: v_writelane_b32 v63, s81, 23 +; GFX9-NEXT: v_writelane_b32 v63, s82, 24 +; GFX9-NEXT: v_writelane_b32 v63, s83, 25 +; GFX9-NEXT: v_writelane_b32 v63, s84, 26 +; GFX9-NEXT: v_writelane_b32 v63, s85, 27 +; GFX9-NEXT: v_writelane_b32 v63, s86, 28 +; GFX9-NEXT: v_writelane_b32 v63, s87, 29 +; GFX9-NEXT: v_writelane_b32 v63, s96, 30 +; GFX9-NEXT: v_writelane_b32 v63, s97, 31 +; GFX9-NEXT: v_writelane_b32 v63, s98, 32 +; GFX9-NEXT: v_writelane_b32 v63, s99, 33 +; GFX9-NEXT: v_writelane_b32 v63, s30, 34 +; GFX9-NEXT: v_writelane_b32 v63, s31, 35 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; GFX9-NEXT: v_writelane_b32 v63, s99, 35 ; GFX9-NEXT: v_readfirstlane_b32 s76, v3 ; GFX9-NEXT: v_readfirstlane_b32 s77, v4 ; GFX9-NEXT: v_readfirstlane_b32 s74, v5 @@ -170646,20 +172645,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 ; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v2 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB91_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false @@ -172043,42 +174028,42 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX9-NEXT: v_or_b32_sdwa v2, v44, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX9-NEXT: v_or_b32_sdwa v1, v26, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_readlane_b32 s99, v63, 35 -; GFX9-NEXT: v_readlane_b32 s98, v63, 34 -; GFX9-NEXT: v_readlane_b32 s97, v63, 33 -; GFX9-NEXT: v_readlane_b32 s96, v63, 32 -; GFX9-NEXT: v_readlane_b32 s87, v63, 31 -; GFX9-NEXT: v_readlane_b32 s86, v63, 30 -; GFX9-NEXT: v_readlane_b32 s85, v63, 29 -; GFX9-NEXT: v_readlane_b32 s84, v63, 28 -; GFX9-NEXT: v_readlane_b32 s83, v63, 27 -; GFX9-NEXT: v_readlane_b32 s82, v63, 26 -; GFX9-NEXT: v_readlane_b32 s81, v63, 25 -; GFX9-NEXT: v_readlane_b32 s80, v63, 24 -; GFX9-NEXT: v_readlane_b32 s71, v63, 23 -; GFX9-NEXT: v_readlane_b32 s70, v63, 22 -; GFX9-NEXT: v_readlane_b32 s69, v63, 21 -; GFX9-NEXT: v_readlane_b32 s68, v63, 20 -; GFX9-NEXT: v_readlane_b32 s67, v63, 19 -; GFX9-NEXT: v_readlane_b32 s66, v63, 18 -; GFX9-NEXT: v_readlane_b32 s65, v63, 17 -; GFX9-NEXT: v_readlane_b32 s64, v63, 16 -; GFX9-NEXT: v_readlane_b32 s55, v63, 15 -; GFX9-NEXT: v_readlane_b32 s54, v63, 14 -; GFX9-NEXT: v_readlane_b32 s53, v63, 13 -; GFX9-NEXT: v_readlane_b32 s52, v63, 12 -; GFX9-NEXT: v_readlane_b32 s51, v63, 11 -; GFX9-NEXT: v_readlane_b32 s50, v63, 10 -; GFX9-NEXT: v_readlane_b32 s49, v63, 9 -; GFX9-NEXT: v_readlane_b32 s48, v63, 8 -; GFX9-NEXT: v_readlane_b32 s39, v63, 7 -; GFX9-NEXT: v_readlane_b32 s38, v63, 6 -; GFX9-NEXT: v_readlane_b32 s37, v63, 5 -; GFX9-NEXT: v_readlane_b32 s36, v63, 4 -; GFX9-NEXT: v_readlane_b32 s35, v63, 3 -; GFX9-NEXT: v_readlane_b32 s34, v63, 2 -; GFX9-NEXT: v_readlane_b32 s31, v63, 1 -; GFX9-NEXT: v_readlane_b32 s30, v63, 0 +; GFX9-NEXT: v_readlane_b32 s30, v63, 34 +; GFX9-NEXT: v_readlane_b32 s31, v63, 35 +; GFX9-NEXT: v_readlane_b32 s99, v63, 33 +; GFX9-NEXT: v_readlane_b32 s98, v63, 32 +; GFX9-NEXT: v_readlane_b32 s97, v63, 31 +; GFX9-NEXT: v_readlane_b32 s96, v63, 30 +; GFX9-NEXT: v_readlane_b32 s87, v63, 29 +; GFX9-NEXT: v_readlane_b32 s86, v63, 28 +; GFX9-NEXT: v_readlane_b32 s85, v63, 27 +; GFX9-NEXT: v_readlane_b32 s84, v63, 26 +; GFX9-NEXT: v_readlane_b32 s83, v63, 25 +; GFX9-NEXT: v_readlane_b32 s82, v63, 24 +; GFX9-NEXT: v_readlane_b32 s81, v63, 23 +; GFX9-NEXT: v_readlane_b32 s80, v63, 22 +; GFX9-NEXT: v_readlane_b32 s71, v63, 21 +; GFX9-NEXT: v_readlane_b32 s70, v63, 20 +; GFX9-NEXT: v_readlane_b32 s69, v63, 19 +; GFX9-NEXT: v_readlane_b32 s68, v63, 18 +; GFX9-NEXT: v_readlane_b32 s67, v63, 17 +; GFX9-NEXT: v_readlane_b32 s66, v63, 16 +; GFX9-NEXT: v_readlane_b32 s65, v63, 15 +; GFX9-NEXT: v_readlane_b32 s64, v63, 14 +; GFX9-NEXT: v_readlane_b32 s55, v63, 13 +; GFX9-NEXT: v_readlane_b32 s54, v63, 12 +; GFX9-NEXT: v_readlane_b32 s53, v63, 11 +; GFX9-NEXT: v_readlane_b32 s52, v63, 10 +; GFX9-NEXT: v_readlane_b32 s51, v63, 9 +; GFX9-NEXT: v_readlane_b32 s50, v63, 8 +; GFX9-NEXT: v_readlane_b32 s49, v63, 7 +; GFX9-NEXT: v_readlane_b32 s48, v63, 6 +; GFX9-NEXT: v_readlane_b32 s39, v63, 5 +; GFX9-NEXT: v_readlane_b32 s38, v63, 4 +; GFX9-NEXT: v_readlane_b32 s37, v63, 3 +; GFX9-NEXT: v_readlane_b32 s36, v63, 2 +; GFX9-NEXT: v_readlane_b32 s35, v63, 1 +; GFX9-NEXT: v_readlane_b32 s34, v63, 0 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_or_b32_sdwa v7, v30, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v7, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD @@ -172196,70 +174181,73 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-TRUE16-NEXT: s_clause 0x3 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:12 ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s96, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s34, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s35, 1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s36, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s37, 3 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s38, 4 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s39, 5 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s48, 6 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s49, 7 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s50, 8 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s51, 9 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s52, 10 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s53, 11 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s54, 12 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s55, 13 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s64, 14 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s65, 15 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s66, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s67, 17 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s68, 18 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s69, 19 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s70, 20 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s71, 21 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s80, 22 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s81, 23 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s82, 24 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s83, 25 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s84, 26 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s85, 27 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s86, 28 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s87, 29 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s96, 30 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s97, 31 +; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s98, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s99, 1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s100, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s101, 3 +; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s102, 4 +; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s103, 5 +; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s104, 6 +; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s30, 7 +; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s31, 8 ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v1 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v2 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s97, 1 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v3 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v4 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v5 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s34, 2 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s98, 2 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v6 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v7 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s35, 3 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s99, 3 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v9 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v10 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v11 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s36, 4 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s100, 4 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v12 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v13 ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v14 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s37, 5 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s101, 5 ; GFX11-TRUE16-NEXT: s_mov_b32 vcc_hi, 0 ; GFX11-TRUE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s38, 6 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s102, 6 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s39, 7 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s103, 7 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s48, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s104, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s49, 9 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s50, 10 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s51, 11 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s52, 12 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s53, 13 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s54, 14 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s55, 15 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s64, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s65, 17 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s66, 18 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s67, 19 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s68, 20 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s69, 21 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s70, 22 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s71, 23 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s80, 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s81, 25 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s82, 26 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s83, 27 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s84, 28 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s85, 29 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s86, 30 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s87, 31 ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB91_3 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false ; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s27, 24 @@ -173691,6 +175679,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v8, v9 +; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v41, 7 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v2 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v16, v19 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v18, v1 @@ -173702,47 +175691,46 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[4:7], off offset:80 ; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[11:14], off offset:96 ; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[15:18], off offset:112 -; GFX11-TRUE16-NEXT: v_readlane_b32 s104, v41, 8 -; GFX11-TRUE16-NEXT: v_readlane_b32 s103, v41, 7 -; GFX11-TRUE16-NEXT: v_readlane_b32 s102, v41, 6 -; GFX11-TRUE16-NEXT: v_readlane_b32 s101, v41, 5 -; GFX11-TRUE16-NEXT: v_readlane_b32 s100, v41, 4 -; GFX11-TRUE16-NEXT: v_readlane_b32 s99, v41, 3 -; GFX11-TRUE16-NEXT: v_readlane_b32 s98, v41, 2 -; GFX11-TRUE16-NEXT: v_readlane_b32 s97, v41, 1 -; GFX11-TRUE16-NEXT: v_readlane_b32 s96, v41, 0 -; GFX11-TRUE16-NEXT: v_readlane_b32 s87, v40, 31 -; GFX11-TRUE16-NEXT: v_readlane_b32 s86, v40, 30 -; GFX11-TRUE16-NEXT: v_readlane_b32 s85, v40, 29 -; GFX11-TRUE16-NEXT: v_readlane_b32 s84, v40, 28 -; GFX11-TRUE16-NEXT: v_readlane_b32 s83, v40, 27 -; GFX11-TRUE16-NEXT: v_readlane_b32 s82, v40, 26 -; GFX11-TRUE16-NEXT: v_readlane_b32 s81, v40, 25 -; GFX11-TRUE16-NEXT: v_readlane_b32 s80, v40, 24 -; GFX11-TRUE16-NEXT: v_readlane_b32 s71, v40, 23 -; GFX11-TRUE16-NEXT: v_readlane_b32 s70, v40, 22 -; GFX11-TRUE16-NEXT: v_readlane_b32 s69, v40, 21 -; GFX11-TRUE16-NEXT: v_readlane_b32 s68, v40, 20 -; GFX11-TRUE16-NEXT: v_readlane_b32 s67, v40, 19 -; GFX11-TRUE16-NEXT: v_readlane_b32 s66, v40, 18 -; GFX11-TRUE16-NEXT: v_readlane_b32 s65, v40, 17 -; GFX11-TRUE16-NEXT: v_readlane_b32 s64, v40, 16 -; GFX11-TRUE16-NEXT: v_readlane_b32 s55, v40, 15 -; GFX11-TRUE16-NEXT: v_readlane_b32 s54, v40, 14 -; GFX11-TRUE16-NEXT: v_readlane_b32 s53, v40, 13 -; GFX11-TRUE16-NEXT: v_readlane_b32 s52, v40, 12 -; GFX11-TRUE16-NEXT: v_readlane_b32 s51, v40, 11 -; GFX11-TRUE16-NEXT: v_readlane_b32 s50, v40, 10 -; GFX11-TRUE16-NEXT: v_readlane_b32 s49, v40, 9 -; GFX11-TRUE16-NEXT: v_readlane_b32 s48, v40, 8 -; GFX11-TRUE16-NEXT: v_readlane_b32 s39, v40, 7 -; GFX11-TRUE16-NEXT: v_readlane_b32 s38, v40, 6 -; GFX11-TRUE16-NEXT: v_readlane_b32 s37, v40, 5 -; GFX11-TRUE16-NEXT: v_readlane_b32 s36, v40, 4 -; GFX11-TRUE16-NEXT: v_readlane_b32 s35, v40, 3 -; GFX11-TRUE16-NEXT: v_readlane_b32 s34, v40, 2 -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 -; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v41, 8 +; GFX11-TRUE16-NEXT: v_readlane_b32 s104, v41, 6 +; GFX11-TRUE16-NEXT: v_readlane_b32 s103, v41, 5 +; GFX11-TRUE16-NEXT: v_readlane_b32 s102, v41, 4 +; GFX11-TRUE16-NEXT: v_readlane_b32 s101, v41, 3 +; GFX11-TRUE16-NEXT: v_readlane_b32 s100, v41, 2 +; GFX11-TRUE16-NEXT: v_readlane_b32 s99, v41, 1 +; GFX11-TRUE16-NEXT: v_readlane_b32 s98, v41, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s97, v40, 31 +; GFX11-TRUE16-NEXT: v_readlane_b32 s96, v40, 30 +; GFX11-TRUE16-NEXT: v_readlane_b32 s87, v40, 29 +; GFX11-TRUE16-NEXT: v_readlane_b32 s86, v40, 28 +; GFX11-TRUE16-NEXT: v_readlane_b32 s85, v40, 27 +; GFX11-TRUE16-NEXT: v_readlane_b32 s84, v40, 26 +; GFX11-TRUE16-NEXT: v_readlane_b32 s83, v40, 25 +; GFX11-TRUE16-NEXT: v_readlane_b32 s82, v40, 24 +; GFX11-TRUE16-NEXT: v_readlane_b32 s81, v40, 23 +; GFX11-TRUE16-NEXT: v_readlane_b32 s80, v40, 22 +; GFX11-TRUE16-NEXT: v_readlane_b32 s71, v40, 21 +; GFX11-TRUE16-NEXT: v_readlane_b32 s70, v40, 20 +; GFX11-TRUE16-NEXT: v_readlane_b32 s69, v40, 19 +; GFX11-TRUE16-NEXT: v_readlane_b32 s68, v40, 18 +; GFX11-TRUE16-NEXT: v_readlane_b32 s67, v40, 17 +; GFX11-TRUE16-NEXT: v_readlane_b32 s66, v40, 16 +; GFX11-TRUE16-NEXT: v_readlane_b32 s65, v40, 15 +; GFX11-TRUE16-NEXT: v_readlane_b32 s64, v40, 14 +; GFX11-TRUE16-NEXT: v_readlane_b32 s55, v40, 13 +; GFX11-TRUE16-NEXT: v_readlane_b32 s54, v40, 12 +; GFX11-TRUE16-NEXT: v_readlane_b32 s53, v40, 11 +; GFX11-TRUE16-NEXT: v_readlane_b32 s52, v40, 10 +; GFX11-TRUE16-NEXT: v_readlane_b32 s51, v40, 9 +; GFX11-TRUE16-NEXT: v_readlane_b32 s50, v40, 8 +; GFX11-TRUE16-NEXT: v_readlane_b32 s49, v40, 7 +; GFX11-TRUE16-NEXT: v_readlane_b32 s48, v40, 6 +; GFX11-TRUE16-NEXT: v_readlane_b32 s39, v40, 5 +; GFX11-TRUE16-NEXT: v_readlane_b32 s38, v40, 4 +; GFX11-TRUE16-NEXT: v_readlane_b32 s37, v40, 3 +; GFX11-TRUE16-NEXT: v_readlane_b32 s36, v40, 2 +; GFX11-TRUE16-NEXT: v_readlane_b32 s35, v40, 1 +; GFX11-TRUE16-NEXT: v_readlane_b32 s34, v40, 0 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-TRUE16-NEXT: s_clause 0x3 ; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 @@ -173759,70 +175747,73 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-FAKE16-NEXT: s_clause 0x3 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:8 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:12 ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s96, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s34, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s35, 1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s36, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s37, 3 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s38, 4 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s39, 5 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s48, 6 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s49, 7 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s50, 8 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s51, 9 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s52, 10 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s53, 11 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s54, 12 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s55, 13 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s64, 14 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s65, 15 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s66, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s67, 17 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s68, 18 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s69, 19 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s70, 20 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s71, 21 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s80, 22 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s81, 23 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s82, 24 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s83, 25 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s84, 26 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s85, 27 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s86, 28 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s87, 29 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s96, 30 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s97, 31 +; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s98, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s99, 1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s100, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s101, 3 +; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s102, 4 +; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s103, 5 +; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s104, 6 +; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s30, 7 +; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s31, 8 ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v1 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v2 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s97, 1 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v3 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v4 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v5 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s34, 2 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s98, 2 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v6 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v7 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s35, 3 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s99, 3 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v9 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v10 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v11 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s36, 4 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s100, 4 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v12 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v13 ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v14 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s37, 5 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s101, 5 ; GFX11-FAKE16-NEXT: s_mov_b32 vcc_hi, 0 ; GFX11-FAKE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s38, 6 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s102, 6 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s39, 7 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s103, 7 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s48, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s104, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s49, 9 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s50, 10 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s51, 11 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s52, 12 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s53, 13 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s54, 14 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s55, 15 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s64, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s65, 17 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s66, 18 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s67, 19 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s68, 20 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s69, 21 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s70, 22 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s71, 23 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s80, 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s81, 25 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s82, 26 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s83, 27 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s84, 28 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s85, 29 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s86, 30 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s87, 31 ; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB91_3 ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false ; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s27, 24 @@ -175261,6 +177252,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v3, v4 +; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v41, 7 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v10, v2 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v11, v18 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v17, v19 @@ -175272,47 +177264,46 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[6:9], off offset:80 ; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:96 ; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:112 -; GFX11-FAKE16-NEXT: v_readlane_b32 s104, v41, 8 -; GFX11-FAKE16-NEXT: v_readlane_b32 s103, v41, 7 -; GFX11-FAKE16-NEXT: v_readlane_b32 s102, v41, 6 -; GFX11-FAKE16-NEXT: v_readlane_b32 s101, v41, 5 -; GFX11-FAKE16-NEXT: v_readlane_b32 s100, v41, 4 -; GFX11-FAKE16-NEXT: v_readlane_b32 s99, v41, 3 -; GFX11-FAKE16-NEXT: v_readlane_b32 s98, v41, 2 -; GFX11-FAKE16-NEXT: v_readlane_b32 s97, v41, 1 -; GFX11-FAKE16-NEXT: v_readlane_b32 s96, v41, 0 -; GFX11-FAKE16-NEXT: v_readlane_b32 s87, v40, 31 -; GFX11-FAKE16-NEXT: v_readlane_b32 s86, v40, 30 -; GFX11-FAKE16-NEXT: v_readlane_b32 s85, v40, 29 -; GFX11-FAKE16-NEXT: v_readlane_b32 s84, v40, 28 -; GFX11-FAKE16-NEXT: v_readlane_b32 s83, v40, 27 -; GFX11-FAKE16-NEXT: v_readlane_b32 s82, v40, 26 -; GFX11-FAKE16-NEXT: v_readlane_b32 s81, v40, 25 -; GFX11-FAKE16-NEXT: v_readlane_b32 s80, v40, 24 -; GFX11-FAKE16-NEXT: v_readlane_b32 s71, v40, 23 -; GFX11-FAKE16-NEXT: v_readlane_b32 s70, v40, 22 -; GFX11-FAKE16-NEXT: v_readlane_b32 s69, v40, 21 -; GFX11-FAKE16-NEXT: v_readlane_b32 s68, v40, 20 -; GFX11-FAKE16-NEXT: v_readlane_b32 s67, v40, 19 -; GFX11-FAKE16-NEXT: v_readlane_b32 s66, v40, 18 -; GFX11-FAKE16-NEXT: v_readlane_b32 s65, v40, 17 -; GFX11-FAKE16-NEXT: v_readlane_b32 s64, v40, 16 -; GFX11-FAKE16-NEXT: v_readlane_b32 s55, v40, 15 -; GFX11-FAKE16-NEXT: v_readlane_b32 s54, v40, 14 -; GFX11-FAKE16-NEXT: v_readlane_b32 s53, v40, 13 -; GFX11-FAKE16-NEXT: v_readlane_b32 s52, v40, 12 -; GFX11-FAKE16-NEXT: v_readlane_b32 s51, v40, 11 -; GFX11-FAKE16-NEXT: v_readlane_b32 s50, v40, 10 -; GFX11-FAKE16-NEXT: v_readlane_b32 s49, v40, 9 -; GFX11-FAKE16-NEXT: v_readlane_b32 s48, v40, 8 -; GFX11-FAKE16-NEXT: v_readlane_b32 s39, v40, 7 -; GFX11-FAKE16-NEXT: v_readlane_b32 s38, v40, 6 -; GFX11-FAKE16-NEXT: v_readlane_b32 s37, v40, 5 -; GFX11-FAKE16-NEXT: v_readlane_b32 s36, v40, 4 -; GFX11-FAKE16-NEXT: v_readlane_b32 s35, v40, 3 -; GFX11-FAKE16-NEXT: v_readlane_b32 s34, v40, 2 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 -; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v41, 8 +; GFX11-FAKE16-NEXT: v_readlane_b32 s104, v41, 6 +; GFX11-FAKE16-NEXT: v_readlane_b32 s103, v41, 5 +; GFX11-FAKE16-NEXT: v_readlane_b32 s102, v41, 4 +; GFX11-FAKE16-NEXT: v_readlane_b32 s101, v41, 3 +; GFX11-FAKE16-NEXT: v_readlane_b32 s100, v41, 2 +; GFX11-FAKE16-NEXT: v_readlane_b32 s99, v41, 1 +; GFX11-FAKE16-NEXT: v_readlane_b32 s98, v41, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s97, v40, 31 +; GFX11-FAKE16-NEXT: v_readlane_b32 s96, v40, 30 +; GFX11-FAKE16-NEXT: v_readlane_b32 s87, v40, 29 +; GFX11-FAKE16-NEXT: v_readlane_b32 s86, v40, 28 +; GFX11-FAKE16-NEXT: v_readlane_b32 s85, v40, 27 +; GFX11-FAKE16-NEXT: v_readlane_b32 s84, v40, 26 +; GFX11-FAKE16-NEXT: v_readlane_b32 s83, v40, 25 +; GFX11-FAKE16-NEXT: v_readlane_b32 s82, v40, 24 +; GFX11-FAKE16-NEXT: v_readlane_b32 s81, v40, 23 +; GFX11-FAKE16-NEXT: v_readlane_b32 s80, v40, 22 +; GFX11-FAKE16-NEXT: v_readlane_b32 s71, v40, 21 +; GFX11-FAKE16-NEXT: v_readlane_b32 s70, v40, 20 +; GFX11-FAKE16-NEXT: v_readlane_b32 s69, v40, 19 +; GFX11-FAKE16-NEXT: v_readlane_b32 s68, v40, 18 +; GFX11-FAKE16-NEXT: v_readlane_b32 s67, v40, 17 +; GFX11-FAKE16-NEXT: v_readlane_b32 s66, v40, 16 +; GFX11-FAKE16-NEXT: v_readlane_b32 s65, v40, 15 +; GFX11-FAKE16-NEXT: v_readlane_b32 s64, v40, 14 +; GFX11-FAKE16-NEXT: v_readlane_b32 s55, v40, 13 +; GFX11-FAKE16-NEXT: v_readlane_b32 s54, v40, 12 +; GFX11-FAKE16-NEXT: v_readlane_b32 s53, v40, 11 +; GFX11-FAKE16-NEXT: v_readlane_b32 s52, v40, 10 +; GFX11-FAKE16-NEXT: v_readlane_b32 s51, v40, 9 +; GFX11-FAKE16-NEXT: v_readlane_b32 s50, v40, 8 +; GFX11-FAKE16-NEXT: v_readlane_b32 s49, v40, 7 +; GFX11-FAKE16-NEXT: v_readlane_b32 s48, v40, 6 +; GFX11-FAKE16-NEXT: v_readlane_b32 s39, v40, 5 +; GFX11-FAKE16-NEXT: v_readlane_b32 s38, v40, 4 +; GFX11-FAKE16-NEXT: v_readlane_b32 s37, v40, 3 +; GFX11-FAKE16-NEXT: v_readlane_b32 s36, v40, 2 +; GFX11-FAKE16-NEXT: v_readlane_b32 s35, v40, 1 +; GFX11-FAKE16-NEXT: v_readlane_b32 s34, v40, 0 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-FAKE16-NEXT: s_clause 0x3 ; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 @@ -180797,53 +182788,99 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:580 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:576 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:572 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:568 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:564 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:560 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:556 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:552 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:548 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:544 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:540 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:536 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:532 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:528 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:524 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:520 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:516 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:512 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:508 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:504 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:500 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:496 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:492 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:488 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:484 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:480 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:468 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:456 ; GFX11-FAKE16-NEXT: s_clause 0xf ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:392 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26 @@ -181735,60 +183772,71 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; SI-NEXT: v_writelane_b32 v63, s34, 0 +; SI-NEXT: v_writelane_b32 v63, s35, 1 +; SI-NEXT: v_writelane_b32 v63, s36, 2 +; SI-NEXT: v_writelane_b32 v63, s37, 3 +; SI-NEXT: v_writelane_b32 v63, s38, 4 +; SI-NEXT: v_writelane_b32 v63, s39, 5 +; SI-NEXT: v_writelane_b32 v63, s48, 6 +; SI-NEXT: v_writelane_b32 v63, s49, 7 +; SI-NEXT: v_writelane_b32 v63, s50, 8 +; SI-NEXT: v_writelane_b32 v63, s51, 9 +; SI-NEXT: v_writelane_b32 v63, s52, 10 +; SI-NEXT: v_writelane_b32 v63, s53, 11 +; SI-NEXT: v_writelane_b32 v63, s54, 12 +; SI-NEXT: v_writelane_b32 v63, s55, 13 +; SI-NEXT: v_writelane_b32 v63, s64, 14 +; SI-NEXT: v_writelane_b32 v63, s65, 15 +; SI-NEXT: v_writelane_b32 v63, s66, 16 +; SI-NEXT: v_writelane_b32 v63, s67, 17 +; SI-NEXT: v_writelane_b32 v63, s68, 18 +; SI-NEXT: v_writelane_b32 v63, s69, 19 +; SI-NEXT: v_writelane_b32 v63, s70, 20 +; SI-NEXT: v_writelane_b32 v63, s71, 21 +; SI-NEXT: v_writelane_b32 v63, s80, 22 +; SI-NEXT: v_writelane_b32 v63, s81, 23 +; SI-NEXT: v_writelane_b32 v63, s82, 24 +; SI-NEXT: v_writelane_b32 v63, s83, 25 +; SI-NEXT: v_writelane_b32 v63, s84, 26 +; SI-NEXT: v_writelane_b32 v63, s85, 27 +; SI-NEXT: v_writelane_b32 v63, s86, 28 +; SI-NEXT: v_writelane_b32 v63, s87, 29 +; SI-NEXT: v_writelane_b32 v63, s96, 30 +; SI-NEXT: v_writelane_b32 v63, s97, 31 +; SI-NEXT: v_writelane_b32 v63, s98, 32 +; SI-NEXT: v_writelane_b32 v63, s99, 33 +; SI-NEXT: v_writelane_b32 v63, s30, 34 +; SI-NEXT: v_writelane_b32 v63, s31, 35 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332 ; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane ; SI-NEXT: s_mov_b32 s10, s16 -; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_writelane_b32 v61, s29, 0 ; SI-NEXT: v_writelane_b32 v61, s28, 1 ; SI-NEXT: v_writelane_b32 v61, s27, 2 ; SI-NEXT: s_mov_b32 s61, s21 -; SI-NEXT: v_writelane_b32 v63, s30, 0 -; SI-NEXT: v_writelane_b32 v63, s31, 1 -; SI-NEXT: v_writelane_b32 v63, s34, 2 -; SI-NEXT: v_writelane_b32 v63, s35, 3 -; SI-NEXT: v_writelane_b32 v63, s36, 4 -; SI-NEXT: v_writelane_b32 v63, s37, 5 -; SI-NEXT: v_writelane_b32 v63, s38, 6 -; SI-NEXT: v_writelane_b32 v63, s39, 7 -; SI-NEXT: v_writelane_b32 v63, s48, 8 -; SI-NEXT: v_writelane_b32 v63, s49, 9 -; SI-NEXT: v_writelane_b32 v63, s50, 10 -; SI-NEXT: v_writelane_b32 v63, s51, 11 -; SI-NEXT: v_writelane_b32 v63, s52, 12 -; SI-NEXT: v_writelane_b32 v63, s53, 13 -; SI-NEXT: v_writelane_b32 v63, s54, 14 -; SI-NEXT: v_writelane_b32 v63, s55, 15 -; SI-NEXT: v_writelane_b32 v63, s64, 16 -; SI-NEXT: v_writelane_b32 v63, s65, 17 -; SI-NEXT: v_writelane_b32 v63, s66, 18 -; SI-NEXT: v_writelane_b32 v63, s67, 19 -; SI-NEXT: v_writelane_b32 v63, s68, 20 -; SI-NEXT: v_writelane_b32 v63, s69, 21 -; SI-NEXT: v_writelane_b32 v63, s70, 22 -; SI-NEXT: v_writelane_b32 v63, s71, 23 -; SI-NEXT: v_writelane_b32 v63, s80, 24 -; SI-NEXT: v_writelane_b32 v63, s81, 25 -; SI-NEXT: v_writelane_b32 v63, s82, 26 -; SI-NEXT: v_writelane_b32 v63, s83, 27 -; SI-NEXT: v_writelane_b32 v63, s84, 28 -; SI-NEXT: v_writelane_b32 v63, s85, 29 -; SI-NEXT: v_writelane_b32 v63, s86, 30 -; SI-NEXT: v_writelane_b32 v63, s87, 31 -; SI-NEXT: v_writelane_b32 v63, s96, 32 -; SI-NEXT: v_writelane_b32 v63, s97, 33 ; SI-NEXT: s_mov_b32 s67, s19 ; SI-NEXT: s_mov_b32 s54, s17 ; SI-NEXT: s_mov_b32 s35, s23 ; SI-NEXT: s_mov_b32 s39, s26 ; SI-NEXT: s_mov_b32 s62, s25 -; SI-NEXT: v_writelane_b32 v63, s98, 34 -; SI-NEXT: v_writelane_b32 v63, s99, 35 ; SI-NEXT: v_readfirstlane_b32 s99, v1 ; SI-NEXT: v_readfirstlane_b32 s74, v24 ; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; SI-NEXT: v_readfirstlane_b32 s6, v23 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_writelane_b32 v62, s74, 0 ; SI-NEXT: v_readfirstlane_b32 s12, v26 ; SI-NEXT: v_writelane_b32 v62, s6, 1 @@ -181819,10 +183867,6 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s42, v20 ; SI-NEXT: v_readfirstlane_b32 s43, v19 ; SI-NEXT: v_readfirstlane_b32 s44, v22 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_readfirstlane_b32 s4, v31 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:328 -; SI-NEXT: v_writelane_b32 v61, s4, 3 ; SI-NEXT: v_readfirstlane_b32 s45, v21 ; SI-NEXT: v_readfirstlane_b32 s98, v10 ; SI-NEXT: v_readfirstlane_b32 s90, v8 @@ -181830,28 +183874,19 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s91, v6 ; SI-NEXT: v_readfirstlane_b32 s93, v4 ; SI-NEXT: v_readfirstlane_b32 s55, v2 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 -; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_readfirstlane_b32 s4, v31 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:324 -; SI-NEXT: v_writelane_b32 v61, s4, 4 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:328 +; SI-NEXT: v_writelane_b32 v61, s4, 3 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_readfirstlane_b32 s4, v31 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:324 +; SI-NEXT: v_writelane_b32 v61, s4, 4 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_readfirstlane_b32 s4, v31 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:320 ; SI-NEXT: v_writelane_b32 v61, s4, 5 ; SI-NEXT: s_waitcnt vmcnt(0) @@ -182980,7 +185015,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v5, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v6, v6 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_readlane_b32 s99, v63, 35 +; SI-NEXT: v_readlane_b32 s30, v63, 34 ; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; SI-NEXT: v_or_b32_e32 v5, v6, v5 ; SI-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen @@ -182988,41 +185023,41 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i ; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_readlane_b32 s98, v63, 34 -; SI-NEXT: v_readlane_b32 s97, v63, 33 -; SI-NEXT: v_readlane_b32 s96, v63, 32 -; SI-NEXT: v_readlane_b32 s87, v63, 31 -; SI-NEXT: v_readlane_b32 s86, v63, 30 -; SI-NEXT: v_readlane_b32 s85, v63, 29 -; SI-NEXT: v_readlane_b32 s84, v63, 28 -; SI-NEXT: v_readlane_b32 s83, v63, 27 -; SI-NEXT: v_readlane_b32 s82, v63, 26 -; SI-NEXT: v_readlane_b32 s81, v63, 25 -; SI-NEXT: v_readlane_b32 s80, v63, 24 -; SI-NEXT: v_readlane_b32 s71, v63, 23 -; SI-NEXT: v_readlane_b32 s70, v63, 22 -; SI-NEXT: v_readlane_b32 s69, v63, 21 -; SI-NEXT: v_readlane_b32 s68, v63, 20 -; SI-NEXT: v_readlane_b32 s67, v63, 19 -; SI-NEXT: v_readlane_b32 s66, v63, 18 -; SI-NEXT: v_readlane_b32 s65, v63, 17 -; SI-NEXT: v_readlane_b32 s64, v63, 16 -; SI-NEXT: v_readlane_b32 s55, v63, 15 -; SI-NEXT: v_readlane_b32 s54, v63, 14 -; SI-NEXT: v_readlane_b32 s53, v63, 13 -; SI-NEXT: v_readlane_b32 s52, v63, 12 -; SI-NEXT: v_readlane_b32 s51, v63, 11 -; SI-NEXT: v_readlane_b32 s50, v63, 10 -; SI-NEXT: v_readlane_b32 s49, v63, 9 -; SI-NEXT: v_readlane_b32 s48, v63, 8 -; SI-NEXT: v_readlane_b32 s39, v63, 7 -; SI-NEXT: v_readlane_b32 s38, v63, 6 -; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s36, v63, 4 -; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: v_readlane_b32 s31, v63, 35 +; SI-NEXT: v_readlane_b32 s99, v63, 33 +; SI-NEXT: v_readlane_b32 s98, v63, 32 +; SI-NEXT: v_readlane_b32 s97, v63, 31 +; SI-NEXT: v_readlane_b32 s96, v63, 30 +; SI-NEXT: v_readlane_b32 s87, v63, 29 +; SI-NEXT: v_readlane_b32 s86, v63, 28 +; SI-NEXT: v_readlane_b32 s85, v63, 27 +; SI-NEXT: v_readlane_b32 s84, v63, 26 +; SI-NEXT: v_readlane_b32 s83, v63, 25 +; SI-NEXT: v_readlane_b32 s82, v63, 24 +; SI-NEXT: v_readlane_b32 s81, v63, 23 +; SI-NEXT: v_readlane_b32 s80, v63, 22 +; SI-NEXT: v_readlane_b32 s71, v63, 21 +; SI-NEXT: v_readlane_b32 s70, v63, 20 +; SI-NEXT: v_readlane_b32 s69, v63, 19 +; SI-NEXT: v_readlane_b32 s68, v63, 18 +; SI-NEXT: v_readlane_b32 s67, v63, 17 +; SI-NEXT: v_readlane_b32 s66, v63, 16 +; SI-NEXT: v_readlane_b32 s65, v63, 15 +; SI-NEXT: v_readlane_b32 s64, v63, 14 +; SI-NEXT: v_readlane_b32 s55, v63, 13 +; SI-NEXT: v_readlane_b32 s54, v63, 12 +; SI-NEXT: v_readlane_b32 s53, v63, 11 +; SI-NEXT: v_readlane_b32 s52, v63, 10 +; SI-NEXT: v_readlane_b32 s51, v63, 9 +; SI-NEXT: v_readlane_b32 s50, v63, 8 +; SI-NEXT: v_readlane_b32 s49, v63, 7 +; SI-NEXT: v_readlane_b32 s48, v63, 6 +; SI-NEXT: v_readlane_b32 s39, v63, 5 +; SI-NEXT: v_readlane_b32 s38, v63, 4 +; SI-NEXT: v_readlane_b32 s37, v63, 3 +; SI-NEXT: v_readlane_b32 s36, v63, 2 +; SI-NEXT: v_readlane_b32 s35, v63, 1 +; SI-NEXT: v_readlane_b32 s34, v63, 0 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_cvt_f16_f32_e32 v5, v5 ; SI-NEXT: s_waitcnt vmcnt(0) @@ -185482,35 +187517,65 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1e ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:440 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:436 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:432 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:428 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:424 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:420 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:416 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:412 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:408 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:404 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:400 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:396 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:392 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:388 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:384 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:380 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:376 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:372 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:368 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:364 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:360 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:356 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:352 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:348 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:344 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:340 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:336 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:332 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:328 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:324 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:320 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26 @@ -186254,35 +188319,65 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1e ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:392 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:388 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:384 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:380 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:376 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:372 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:368 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:364 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:360 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:356 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:352 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:348 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:344 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:340 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:336 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:332 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:328 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:324 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:320 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26 @@ -187095,7 +189190,6 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) { ; SI-LABEL: bitcast_v64f16_to_v128i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill @@ -187112,6 +189206,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 ; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:136 ; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4 ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 @@ -187140,16 +189235,16 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:80 ; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:92 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_cvt_f16_f32_e32 v33, v4 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v33, v4 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill ; SI-NEXT: v_cvt_f16_f32_e32 v31, v12 +; SI-NEXT: v_cvt_f16_f32_e32 v12, v16 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v6 -; SI-NEXT: v_cvt_f16_f32_e32 v12, v16 ; SI-NEXT: v_cvt_f16_f32_e32 v32, v8 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -187185,26 +189280,27 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v18 ; SI-NEXT: ; implicit-def: $vgpr18 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v34 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v17 -; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v10, v35 -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v34 ; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: v_cvt_f16_f32_e32 v8, v39 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v19 -; SI-NEXT: v_cvt_f16_f32_e32 v8, v39 ; SI-NEXT: ; implicit-def: $vgpr39 ; SI-NEXT: ; implicit-def: $vgpr19 ; SI-NEXT: v_cvt_f16_f32_e32 v7, v51 +; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v22 -; SI-NEXT: v_cvt_f16_f32_e32 v56, v53 ; SI-NEXT: v_cvt_f16_f32_e32 v5, v55 +; SI-NEXT: v_cvt_f16_f32_e32 v56, v53 ; SI-NEXT: v_cvt_f16_f32_e32 v47, v54 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -187217,6 +189313,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) { ; SI-NEXT: v_cvt_f16_f32_e32 v1, v23 ; SI-NEXT: v_cvt_f16_f32_e32 v62, v60 ; SI-NEXT: v_cvt_f16_f32_e32 v61, v61 +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v60, v45 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -187227,7 +189324,6 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr41 ; SI-NEXT: ; implicit-def: $vgpr54 ; SI-NEXT: ; implicit-def: $vgpr53 -; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: ; implicit-def: $vgpr26 ; SI-NEXT: ; implicit-def: $vgpr22 ; SI-NEXT: ; implicit-def: $vgpr23 @@ -187285,7 +189381,6 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v63 -; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v63, v46 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -191635,24 +193730,43 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x13 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12 ; GFX11-FAKE16-NEXT: s_clause 0x2 ; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8 @@ -192355,6 +194469,42 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: v_writelane_b32 v63, s34, 0 +; SI-NEXT: v_writelane_b32 v63, s35, 1 +; SI-NEXT: v_writelane_b32 v63, s36, 2 +; SI-NEXT: v_writelane_b32 v63, s37, 3 +; SI-NEXT: v_writelane_b32 v63, s38, 4 +; SI-NEXT: v_writelane_b32 v63, s39, 5 +; SI-NEXT: v_writelane_b32 v63, s48, 6 +; SI-NEXT: v_writelane_b32 v63, s49, 7 +; SI-NEXT: v_writelane_b32 v63, s50, 8 +; SI-NEXT: v_writelane_b32 v63, s51, 9 +; SI-NEXT: v_writelane_b32 v63, s52, 10 +; SI-NEXT: v_writelane_b32 v63, s53, 11 +; SI-NEXT: v_writelane_b32 v63, s54, 12 +; SI-NEXT: v_writelane_b32 v63, s55, 13 +; SI-NEXT: v_writelane_b32 v63, s64, 14 +; SI-NEXT: v_writelane_b32 v63, s65, 15 +; SI-NEXT: v_writelane_b32 v63, s66, 16 +; SI-NEXT: v_writelane_b32 v63, s67, 17 +; SI-NEXT: v_writelane_b32 v63, s68, 18 +; SI-NEXT: v_writelane_b32 v63, s69, 19 +; SI-NEXT: v_writelane_b32 v63, s70, 20 +; SI-NEXT: v_writelane_b32 v63, s71, 21 +; SI-NEXT: v_writelane_b32 v63, s80, 22 +; SI-NEXT: v_writelane_b32 v63, s81, 23 +; SI-NEXT: v_writelane_b32 v63, s82, 24 +; SI-NEXT: v_writelane_b32 v63, s83, 25 +; SI-NEXT: v_writelane_b32 v63, s84, 26 +; SI-NEXT: v_writelane_b32 v63, s85, 27 +; SI-NEXT: v_writelane_b32 v63, s86, 28 +; SI-NEXT: v_writelane_b32 v63, s87, 29 +; SI-NEXT: v_writelane_b32 v63, s96, 30 +; SI-NEXT: v_writelane_b32 v63, s97, 31 +; SI-NEXT: v_writelane_b32 v63, s98, 32 +; SI-NEXT: v_writelane_b32 v63, s99, 33 +; SI-NEXT: v_writelane_b32 v63, s30, 34 +; SI-NEXT: v_writelane_b32 v63, s31, 35 ; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:80 ; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4 ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 @@ -192380,92 +194530,68 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:64 ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76 ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:72 -; SI-NEXT: v_writelane_b32 v63, s30, 0 -; SI-NEXT: v_writelane_b32 v63, s31, 1 -; SI-NEXT: v_writelane_b32 v63, s34, 2 -; SI-NEXT: v_writelane_b32 v63, s35, 3 -; SI-NEXT: v_writelane_b32 v63, s36, 4 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_writelane_b32 v63, s37, 5 -; SI-NEXT: v_writelane_b32 v63, s38, 6 -; SI-NEXT: v_writelane_b32 v63, s39, 7 -; SI-NEXT: v_writelane_b32 v63, s48, 8 +; SI-NEXT: v_mov_b32_e32 v46, v29 +; SI-NEXT: v_cvt_f16_f32_e32 v47, v2 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v4 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v3 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v7 -; SI-NEXT: v_writelane_b32 v63, s49, 9 -; SI-NEXT: v_writelane_b32 v63, s50, 10 -; SI-NEXT: v_writelane_b32 v63, s51, 11 -; SI-NEXT: v_writelane_b32 v63, s52, 12 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v9 -; SI-NEXT: v_writelane_b32 v63, s53, 13 -; SI-NEXT: v_writelane_b32 v63, s54, 14 -; SI-NEXT: v_writelane_b32 v63, s55, 15 -; SI-NEXT: v_writelane_b32 v63, s64, 16 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v26 -; SI-NEXT: v_writelane_b32 v63, s65, 17 -; SI-NEXT: v_writelane_b32 v63, s66, 18 -; SI-NEXT: v_writelane_b32 v63, s67, 19 -; SI-NEXT: v_writelane_b32 v63, s68, 20 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v25 -; SI-NEXT: v_writelane_b32 v63, s69, 21 -; SI-NEXT: v_writelane_b32 v63, s70, 22 -; SI-NEXT: v_writelane_b32 v63, s71, 23 -; SI-NEXT: v_writelane_b32 v63, s80, 24 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v30 -; SI-NEXT: v_writelane_b32 v63, s81, 25 -; SI-NEXT: v_writelane_b32 v63, s82, 26 -; SI-NEXT: v_writelane_b32 v63, s83, 27 -; SI-NEXT: v_writelane_b32 v63, s84, 28 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: v_writelane_b32 v63, s85, 29 -; SI-NEXT: v_writelane_b32 v63, s86, 30 -; SI-NEXT: v_writelane_b32 v63, s87, 31 -; SI-NEXT: v_mov_b32_e32 v46, v29 -; SI-NEXT: v_writelane_b32 v63, s96, 32 -; SI-NEXT: v_cvt_f16_f32_e32 v47, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v4 ; SI-NEXT: v_cvt_f16_f32_e32 v33, v6 ; SI-NEXT: v_cvt_f16_f32_e32 v43, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v5, v8 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v3, v9 ; SI-NEXT: v_cvt_f16_f32_e32 v32, v10 ; SI-NEXT: v_cvt_f16_f32_e32 v7, v12 ; SI-NEXT: v_cvt_f16_f32_e32 v29, v11 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v3, v26 ; SI-NEXT: v_cvt_f16_f32_e32 v31, v14 ; SI-NEXT: v_cvt_f16_f32_e32 v6, v13 ; SI-NEXT: v_cvt_f16_f32_e32 v58, v16 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v3, v25 ; SI-NEXT: v_cvt_f16_f32_e32 v13, v15 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v34 ; SI-NEXT: v_cvt_f16_f32_e32 v10, v18 ; SI-NEXT: v_cvt_f16_f32_e32 v11, v17 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v37 -; SI-NEXT: v_cvt_f16_f32_e32 v34, v20 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v30 ; SI-NEXT: v_cvt_f16_f32_e32 v16, v19 ; SI-NEXT: v_cvt_f16_f32_e32 v9, v22 ; SI-NEXT: v_cvt_f16_f32_e32 v61, v21 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill ; SI-NEXT: v_cvt_f16_f32_e32 v21, v24 ; SI-NEXT: v_cvt_f16_f32_e32 v24, v23 ; SI-NEXT: v_cvt_f16_f32_e32 v44, v28 ; SI-NEXT: v_cvt_f16_f32_e32 v42, v27 ; SI-NEXT: v_cvt_f16_f32_e32 v46, v46 +; SI-NEXT: v_cvt_f16_f32_e32 v19, s17 +; SI-NEXT: v_cvt_f16_f32_e32 v18, s16 +; SI-NEXT: v_cvt_f16_f32_e32 v12, s19 +; SI-NEXT: v_cvt_f16_f32_e32 v17, s18 +; SI-NEXT: v_cvt_f16_f32_e32 v22, s22 +; SI-NEXT: v_cvt_f16_f32_e32 v15, s25 +; SI-NEXT: v_cvt_f16_f32_e32 v14, s24 +; SI-NEXT: v_cvt_f16_f32_e32 v30, s27 +; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v34 +; SI-NEXT: v_cvt_f16_f32_e32 v34, v20 ; SI-NEXT: v_cvt_f16_f32_e32 v8, v35 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v3, v37 ; SI-NEXT: v_cvt_f16_f32_e32 v23, v36 +; SI-NEXT: v_cvt_f16_f32_e32 v27, v39 +; SI-NEXT: v_cvt_f16_f32_e32 v28, v48 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v3, v38 -; SI-NEXT: v_cvt_f16_f32_e32 v27, v39 -; SI-NEXT: v_cvt_f16_f32_e32 v28, v48 ; SI-NEXT: v_cvt_f16_f32_e32 v4, v49 ; SI-NEXT: v_cvt_f16_f32_e32 v45, v45 ; SI-NEXT: v_cvt_f16_f32_e32 v36, v56 @@ -192488,25 +194614,13 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v53, v40 ; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_cvt_f16_f32_e32 v55, v41 -; SI-NEXT: v_cvt_f16_f32_e32 v19, s17 -; SI-NEXT: v_cvt_f16_f32_e32 v18, s16 -; SI-NEXT: v_cvt_f16_f32_e32 v12, s19 -; SI-NEXT: v_cvt_f16_f32_e32 v17, s18 ; SI-NEXT: v_cvt_f16_f32_e32 v38, s21 ; SI-NEXT: v_cvt_f16_f32_e32 v37, s20 ; SI-NEXT: v_cvt_f16_f32_e32 v48, s23 -; SI-NEXT: v_cvt_f16_f32_e32 v22, s22 -; SI-NEXT: v_cvt_f16_f32_e32 v15, s25 -; SI-NEXT: v_cvt_f16_f32_e32 v14, s24 -; SI-NEXT: v_cvt_f16_f32_e32 v30, s27 ; SI-NEXT: v_cvt_f16_f32_e32 v39, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v35, s29 ; SI-NEXT: v_cvt_f16_f32_e32 v20, s28 -; SI-NEXT: v_writelane_b32 v63, s97, 33 -; SI-NEXT: v_writelane_b32 v63, s98, 34 -; SI-NEXT: v_writelane_b32 v63, s99, 35 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill @@ -193994,6 +196108,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; SI-NEXT: v_readlane_b32 s30, v63, 34 ; SI-NEXT: v_readlane_b32 s45, v62, 17 ; SI-NEXT: v_readlane_b32 s43, v62, 23 ; SI-NEXT: v_readlane_b32 s41, v62, 29 @@ -194001,42 +196116,41 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; SI-NEXT: v_readlane_b32 s27, v62, 41 ; SI-NEXT: v_readlane_b32 s25, v62, 45 ; SI-NEXT: v_readlane_b32 s9, v62, 49 -; SI-NEXT: v_readlane_b32 s99, v63, 35 -; SI-NEXT: v_readlane_b32 s98, v63, 34 -; SI-NEXT: v_readlane_b32 s97, v63, 33 -; SI-NEXT: v_readlane_b32 s96, v63, 32 -; SI-NEXT: v_readlane_b32 s87, v63, 31 -; SI-NEXT: v_readlane_b32 s86, v63, 30 -; SI-NEXT: v_readlane_b32 s85, v63, 29 -; SI-NEXT: v_readlane_b32 s84, v63, 28 -; SI-NEXT: v_readlane_b32 s83, v63, 27 -; SI-NEXT: v_readlane_b32 s82, v63, 26 -; SI-NEXT: v_readlane_b32 s81, v63, 25 -; SI-NEXT: v_readlane_b32 s80, v63, 24 -; SI-NEXT: v_readlane_b32 s71, v63, 23 -; SI-NEXT: v_readlane_b32 s70, v63, 22 -; SI-NEXT: v_readlane_b32 s69, v63, 21 -; SI-NEXT: v_readlane_b32 s68, v63, 20 -; SI-NEXT: v_readlane_b32 s67, v63, 19 -; SI-NEXT: v_readlane_b32 s66, v63, 18 -; SI-NEXT: v_readlane_b32 s65, v63, 17 -; SI-NEXT: v_readlane_b32 s64, v63, 16 -; SI-NEXT: v_readlane_b32 s55, v63, 15 -; SI-NEXT: v_readlane_b32 s54, v63, 14 -; SI-NEXT: v_readlane_b32 s53, v63, 13 -; SI-NEXT: v_readlane_b32 s52, v63, 12 -; SI-NEXT: v_readlane_b32 s51, v63, 11 -; SI-NEXT: v_readlane_b32 s50, v63, 10 -; SI-NEXT: v_readlane_b32 s49, v63, 9 -; SI-NEXT: v_readlane_b32 s48, v63, 8 -; SI-NEXT: v_readlane_b32 s39, v63, 7 -; SI-NEXT: v_readlane_b32 s38, v63, 6 -; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s36, v63, 4 -; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: v_readlane_b32 s31, v63, 35 +; SI-NEXT: v_readlane_b32 s99, v63, 33 +; SI-NEXT: v_readlane_b32 s98, v63, 32 +; SI-NEXT: v_readlane_b32 s97, v63, 31 +; SI-NEXT: v_readlane_b32 s96, v63, 30 +; SI-NEXT: v_readlane_b32 s87, v63, 29 +; SI-NEXT: v_readlane_b32 s86, v63, 28 +; SI-NEXT: v_readlane_b32 s85, v63, 27 +; SI-NEXT: v_readlane_b32 s84, v63, 26 +; SI-NEXT: v_readlane_b32 s83, v63, 25 +; SI-NEXT: v_readlane_b32 s82, v63, 24 +; SI-NEXT: v_readlane_b32 s81, v63, 23 +; SI-NEXT: v_readlane_b32 s80, v63, 22 +; SI-NEXT: v_readlane_b32 s71, v63, 21 +; SI-NEXT: v_readlane_b32 s70, v63, 20 +; SI-NEXT: v_readlane_b32 s69, v63, 19 +; SI-NEXT: v_readlane_b32 s68, v63, 18 +; SI-NEXT: v_readlane_b32 s67, v63, 17 +; SI-NEXT: v_readlane_b32 s66, v63, 16 +; SI-NEXT: v_readlane_b32 s65, v63, 15 +; SI-NEXT: v_readlane_b32 s64, v63, 14 +; SI-NEXT: v_readlane_b32 s55, v63, 13 +; SI-NEXT: v_readlane_b32 s54, v63, 12 +; SI-NEXT: v_readlane_b32 s53, v63, 11 +; SI-NEXT: v_readlane_b32 s52, v63, 10 +; SI-NEXT: v_readlane_b32 s51, v63, 9 +; SI-NEXT: v_readlane_b32 s50, v63, 8 +; SI-NEXT: v_readlane_b32 s49, v63, 7 +; SI-NEXT: v_readlane_b32 s48, v63, 6 +; SI-NEXT: v_readlane_b32 s39, v63, 5 +; SI-NEXT: v_readlane_b32 s38, v63, 4 +; SI-NEXT: v_readlane_b32 s37, v63, 3 +; SI-NEXT: v_readlane_b32 s36, v63, 2 +; SI-NEXT: v_readlane_b32 s35, v63, 1 +; SI-NEXT: v_readlane_b32 s34, v63, 0 ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload @@ -194051,39 +196165,53 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v63, s30, 0 -; VI-NEXT: v_writelane_b32 v63, s31, 1 -; VI-NEXT: v_writelane_b32 v63, s34, 2 -; VI-NEXT: v_writelane_b32 v63, s35, 3 -; VI-NEXT: v_writelane_b32 v63, s36, 4 -; VI-NEXT: v_writelane_b32 v63, s37, 5 -; VI-NEXT: v_writelane_b32 v63, s38, 6 -; VI-NEXT: v_writelane_b32 v63, s39, 7 -; VI-NEXT: v_writelane_b32 v63, s48, 8 -; VI-NEXT: v_writelane_b32 v63, s49, 9 -; VI-NEXT: v_writelane_b32 v63, s50, 10 -; VI-NEXT: v_writelane_b32 v63, s51, 11 -; VI-NEXT: v_writelane_b32 v63, s52, 12 -; VI-NEXT: v_writelane_b32 v63, s53, 13 -; VI-NEXT: v_writelane_b32 v63, s54, 14 -; VI-NEXT: v_writelane_b32 v63, s55, 15 -; VI-NEXT: v_writelane_b32 v63, s64, 16 -; VI-NEXT: v_writelane_b32 v63, s65, 17 -; VI-NEXT: v_writelane_b32 v63, s66, 18 -; VI-NEXT: v_writelane_b32 v63, s67, 19 -; VI-NEXT: v_writelane_b32 v63, s68, 20 -; VI-NEXT: v_writelane_b32 v63, s69, 21 -; VI-NEXT: v_writelane_b32 v63, s70, 22 -; VI-NEXT: v_writelane_b32 v63, s71, 23 -; VI-NEXT: v_writelane_b32 v63, s80, 24 -; VI-NEXT: v_writelane_b32 v63, s81, 25 -; VI-NEXT: v_writelane_b32 v63, s82, 26 -; VI-NEXT: v_writelane_b32 v63, s83, 27 -; VI-NEXT: v_writelane_b32 v63, s84, 28 -; VI-NEXT: v_writelane_b32 v63, s85, 29 -; VI-NEXT: v_writelane_b32 v63, s86, 30 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_writelane_b32 v63, s34, 0 +; VI-NEXT: v_writelane_b32 v63, s35, 1 +; VI-NEXT: v_writelane_b32 v63, s36, 2 +; VI-NEXT: v_writelane_b32 v63, s37, 3 +; VI-NEXT: v_writelane_b32 v63, s38, 4 +; VI-NEXT: v_writelane_b32 v63, s39, 5 +; VI-NEXT: v_writelane_b32 v63, s48, 6 +; VI-NEXT: v_writelane_b32 v63, s49, 7 +; VI-NEXT: v_writelane_b32 v63, s50, 8 +; VI-NEXT: v_writelane_b32 v63, s51, 9 +; VI-NEXT: v_writelane_b32 v63, s52, 10 +; VI-NEXT: v_writelane_b32 v63, s53, 11 +; VI-NEXT: v_writelane_b32 v63, s54, 12 +; VI-NEXT: v_writelane_b32 v63, s55, 13 +; VI-NEXT: v_writelane_b32 v63, s64, 14 +; VI-NEXT: v_writelane_b32 v63, s65, 15 +; VI-NEXT: v_writelane_b32 v63, s66, 16 +; VI-NEXT: v_writelane_b32 v63, s67, 17 +; VI-NEXT: v_writelane_b32 v63, s68, 18 +; VI-NEXT: v_writelane_b32 v63, s69, 19 +; VI-NEXT: v_writelane_b32 v63, s70, 20 +; VI-NEXT: v_writelane_b32 v63, s71, 21 +; VI-NEXT: v_writelane_b32 v63, s80, 22 +; VI-NEXT: v_writelane_b32 v63, s81, 23 +; VI-NEXT: v_writelane_b32 v63, s82, 24 +; VI-NEXT: v_writelane_b32 v63, s83, 25 +; VI-NEXT: v_writelane_b32 v63, s84, 26 +; VI-NEXT: v_writelane_b32 v63, s85, 27 +; VI-NEXT: v_writelane_b32 v63, s86, 28 +; VI-NEXT: v_writelane_b32 v63, s87, 29 +; VI-NEXT: v_writelane_b32 v63, s30, 30 +; VI-NEXT: v_writelane_b32 v63, s31, 31 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v63, s87, 31 ; VI-NEXT: v_readfirstlane_b32 s44, v3 ; VI-NEXT: v_readfirstlane_b32 s45, v4 ; VI-NEXT: v_readfirstlane_b32 s42, v5 @@ -194103,20 +196231,6 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; VI-NEXT: v_readfirstlane_b32 s4, v1 ; VI-NEXT: s_and_b64 s[46:47], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v2 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB95_3 ; VI-NEXT: ; %bb.1: ; %cmp.false @@ -194998,38 +197112,38 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; VI-NEXT: v_or_b32_sdwa v1, v61, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_readlane_b32 s87, v63, 31 -; VI-NEXT: v_readlane_b32 s86, v63, 30 -; VI-NEXT: v_readlane_b32 s85, v63, 29 -; VI-NEXT: v_readlane_b32 s84, v63, 28 -; VI-NEXT: v_readlane_b32 s83, v63, 27 -; VI-NEXT: v_readlane_b32 s82, v63, 26 -; VI-NEXT: v_readlane_b32 s81, v63, 25 -; VI-NEXT: v_readlane_b32 s80, v63, 24 -; VI-NEXT: v_readlane_b32 s71, v63, 23 -; VI-NEXT: v_readlane_b32 s70, v63, 22 -; VI-NEXT: v_readlane_b32 s69, v63, 21 -; VI-NEXT: v_readlane_b32 s68, v63, 20 -; VI-NEXT: v_readlane_b32 s67, v63, 19 -; VI-NEXT: v_readlane_b32 s66, v63, 18 -; VI-NEXT: v_readlane_b32 s65, v63, 17 -; VI-NEXT: v_readlane_b32 s64, v63, 16 -; VI-NEXT: v_readlane_b32 s55, v63, 15 -; VI-NEXT: v_readlane_b32 s54, v63, 14 -; VI-NEXT: v_readlane_b32 s53, v63, 13 -; VI-NEXT: v_readlane_b32 s52, v63, 12 -; VI-NEXT: v_readlane_b32 s51, v63, 11 -; VI-NEXT: v_readlane_b32 s50, v63, 10 -; VI-NEXT: v_readlane_b32 s49, v63, 9 -; VI-NEXT: v_readlane_b32 s48, v63, 8 -; VI-NEXT: v_readlane_b32 s39, v63, 7 -; VI-NEXT: v_readlane_b32 s38, v63, 6 -; VI-NEXT: v_readlane_b32 s37, v63, 5 -; VI-NEXT: v_readlane_b32 s36, v63, 4 -; VI-NEXT: v_readlane_b32 s35, v63, 3 -; VI-NEXT: v_readlane_b32 s34, v63, 2 -; VI-NEXT: v_readlane_b32 s31, v63, 1 -; VI-NEXT: v_readlane_b32 s30, v63, 0 +; VI-NEXT: v_readlane_b32 s30, v63, 30 +; VI-NEXT: v_readlane_b32 s31, v63, 31 +; VI-NEXT: v_readlane_b32 s87, v63, 29 +; VI-NEXT: v_readlane_b32 s86, v63, 28 +; VI-NEXT: v_readlane_b32 s85, v63, 27 +; VI-NEXT: v_readlane_b32 s84, v63, 26 +; VI-NEXT: v_readlane_b32 s83, v63, 25 +; VI-NEXT: v_readlane_b32 s82, v63, 24 +; VI-NEXT: v_readlane_b32 s81, v63, 23 +; VI-NEXT: v_readlane_b32 s80, v63, 22 +; VI-NEXT: v_readlane_b32 s71, v63, 21 +; VI-NEXT: v_readlane_b32 s70, v63, 20 +; VI-NEXT: v_readlane_b32 s69, v63, 19 +; VI-NEXT: v_readlane_b32 s68, v63, 18 +; VI-NEXT: v_readlane_b32 s67, v63, 17 +; VI-NEXT: v_readlane_b32 s66, v63, 16 +; VI-NEXT: v_readlane_b32 s65, v63, 15 +; VI-NEXT: v_readlane_b32 s64, v63, 14 +; VI-NEXT: v_readlane_b32 s55, v63, 13 +; VI-NEXT: v_readlane_b32 s54, v63, 12 +; VI-NEXT: v_readlane_b32 s53, v63, 11 +; VI-NEXT: v_readlane_b32 s52, v63, 10 +; VI-NEXT: v_readlane_b32 s51, v63, 9 +; VI-NEXT: v_readlane_b32 s50, v63, 8 +; VI-NEXT: v_readlane_b32 s49, v63, 7 +; VI-NEXT: v_readlane_b32 s48, v63, 6 +; VI-NEXT: v_readlane_b32 s39, v63, 5 +; VI-NEXT: v_readlane_b32 s38, v63, 4 +; VI-NEXT: v_readlane_b32 s37, v63, 3 +; VI-NEXT: v_readlane_b32 s36, v63, 2 +; VI-NEXT: v_readlane_b32 s35, v63, 1 +; VI-NEXT: v_readlane_b32 s34, v63, 0 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v58, v23, v58 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload @@ -195410,43 +197524,57 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v63, s30, 0 -; GFX9-NEXT: v_writelane_b32 v63, s31, 1 -; GFX9-NEXT: v_writelane_b32 v63, s34, 2 -; GFX9-NEXT: v_writelane_b32 v63, s35, 3 -; GFX9-NEXT: v_writelane_b32 v63, s36, 4 -; GFX9-NEXT: v_writelane_b32 v63, s37, 5 -; GFX9-NEXT: v_writelane_b32 v63, s38, 6 -; GFX9-NEXT: v_writelane_b32 v63, s39, 7 -; GFX9-NEXT: v_writelane_b32 v63, s48, 8 -; GFX9-NEXT: v_writelane_b32 v63, s49, 9 -; GFX9-NEXT: v_writelane_b32 v63, s50, 10 -; GFX9-NEXT: v_writelane_b32 v63, s51, 11 -; GFX9-NEXT: v_writelane_b32 v63, s52, 12 -; GFX9-NEXT: v_writelane_b32 v63, s53, 13 -; GFX9-NEXT: v_writelane_b32 v63, s54, 14 -; GFX9-NEXT: v_writelane_b32 v63, s55, 15 -; GFX9-NEXT: v_writelane_b32 v63, s64, 16 -; GFX9-NEXT: v_writelane_b32 v63, s65, 17 -; GFX9-NEXT: v_writelane_b32 v63, s66, 18 -; GFX9-NEXT: v_writelane_b32 v63, s67, 19 -; GFX9-NEXT: v_writelane_b32 v63, s68, 20 -; GFX9-NEXT: v_writelane_b32 v63, s69, 21 -; GFX9-NEXT: v_writelane_b32 v63, s70, 22 -; GFX9-NEXT: v_writelane_b32 v63, s71, 23 -; GFX9-NEXT: v_writelane_b32 v63, s80, 24 -; GFX9-NEXT: v_writelane_b32 v63, s81, 25 -; GFX9-NEXT: v_writelane_b32 v63, s82, 26 -; GFX9-NEXT: v_writelane_b32 v63, s83, 27 -; GFX9-NEXT: v_writelane_b32 v63, s84, 28 -; GFX9-NEXT: v_writelane_b32 v63, s85, 29 -; GFX9-NEXT: v_writelane_b32 v63, s86, 30 -; GFX9-NEXT: v_writelane_b32 v63, s87, 31 -; GFX9-NEXT: v_writelane_b32 v63, s96, 32 -; GFX9-NEXT: v_writelane_b32 v63, s97, 33 -; GFX9-NEXT: v_writelane_b32 v63, s98, 34 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v63, s34, 0 +; GFX9-NEXT: v_writelane_b32 v63, s35, 1 +; GFX9-NEXT: v_writelane_b32 v63, s36, 2 +; GFX9-NEXT: v_writelane_b32 v63, s37, 3 +; GFX9-NEXT: v_writelane_b32 v63, s38, 4 +; GFX9-NEXT: v_writelane_b32 v63, s39, 5 +; GFX9-NEXT: v_writelane_b32 v63, s48, 6 +; GFX9-NEXT: v_writelane_b32 v63, s49, 7 +; GFX9-NEXT: v_writelane_b32 v63, s50, 8 +; GFX9-NEXT: v_writelane_b32 v63, s51, 9 +; GFX9-NEXT: v_writelane_b32 v63, s52, 10 +; GFX9-NEXT: v_writelane_b32 v63, s53, 11 +; GFX9-NEXT: v_writelane_b32 v63, s54, 12 +; GFX9-NEXT: v_writelane_b32 v63, s55, 13 +; GFX9-NEXT: v_writelane_b32 v63, s64, 14 +; GFX9-NEXT: v_writelane_b32 v63, s65, 15 +; GFX9-NEXT: v_writelane_b32 v63, s66, 16 +; GFX9-NEXT: v_writelane_b32 v63, s67, 17 +; GFX9-NEXT: v_writelane_b32 v63, s68, 18 +; GFX9-NEXT: v_writelane_b32 v63, s69, 19 +; GFX9-NEXT: v_writelane_b32 v63, s70, 20 +; GFX9-NEXT: v_writelane_b32 v63, s71, 21 +; GFX9-NEXT: v_writelane_b32 v63, s80, 22 +; GFX9-NEXT: v_writelane_b32 v63, s81, 23 +; GFX9-NEXT: v_writelane_b32 v63, s82, 24 +; GFX9-NEXT: v_writelane_b32 v63, s83, 25 +; GFX9-NEXT: v_writelane_b32 v63, s84, 26 +; GFX9-NEXT: v_writelane_b32 v63, s85, 27 +; GFX9-NEXT: v_writelane_b32 v63, s86, 28 +; GFX9-NEXT: v_writelane_b32 v63, s87, 29 +; GFX9-NEXT: v_writelane_b32 v63, s96, 30 +; GFX9-NEXT: v_writelane_b32 v63, s97, 31 +; GFX9-NEXT: v_writelane_b32 v63, s98, 32 +; GFX9-NEXT: v_writelane_b32 v63, s99, 33 +; GFX9-NEXT: v_writelane_b32 v63, s30, 34 +; GFX9-NEXT: v_writelane_b32 v63, s31, 35 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; GFX9-NEXT: v_writelane_b32 v63, s99, 35 ; GFX9-NEXT: v_readfirstlane_b32 s44, v3 ; GFX9-NEXT: v_readfirstlane_b32 s45, v4 ; GFX9-NEXT: v_readfirstlane_b32 s42, v5 @@ -195466,20 +197594,6 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 ; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v2 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB95_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false @@ -196329,42 +198443,42 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX9-NEXT: v_or_b32_sdwa v25, v25, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_lshlrev_b32_e32 v30, 8, v44 ; GFX9-NEXT: v_or_b32_sdwa v26, v26, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_readlane_b32 s99, v63, 35 -; GFX9-NEXT: v_readlane_b32 s98, v63, 34 -; GFX9-NEXT: v_readlane_b32 s97, v63, 33 -; GFX9-NEXT: v_readlane_b32 s96, v63, 32 -; GFX9-NEXT: v_readlane_b32 s87, v63, 31 -; GFX9-NEXT: v_readlane_b32 s86, v63, 30 -; GFX9-NEXT: v_readlane_b32 s85, v63, 29 -; GFX9-NEXT: v_readlane_b32 s84, v63, 28 -; GFX9-NEXT: v_readlane_b32 s83, v63, 27 -; GFX9-NEXT: v_readlane_b32 s82, v63, 26 -; GFX9-NEXT: v_readlane_b32 s81, v63, 25 -; GFX9-NEXT: v_readlane_b32 s80, v63, 24 -; GFX9-NEXT: v_readlane_b32 s71, v63, 23 -; GFX9-NEXT: v_readlane_b32 s70, v63, 22 -; GFX9-NEXT: v_readlane_b32 s69, v63, 21 -; GFX9-NEXT: v_readlane_b32 s68, v63, 20 -; GFX9-NEXT: v_readlane_b32 s67, v63, 19 -; GFX9-NEXT: v_readlane_b32 s66, v63, 18 -; GFX9-NEXT: v_readlane_b32 s65, v63, 17 -; GFX9-NEXT: v_readlane_b32 s64, v63, 16 -; GFX9-NEXT: v_readlane_b32 s55, v63, 15 -; GFX9-NEXT: v_readlane_b32 s54, v63, 14 -; GFX9-NEXT: v_readlane_b32 s53, v63, 13 -; GFX9-NEXT: v_readlane_b32 s52, v63, 12 -; GFX9-NEXT: v_readlane_b32 s51, v63, 11 -; GFX9-NEXT: v_readlane_b32 s50, v63, 10 -; GFX9-NEXT: v_readlane_b32 s49, v63, 9 -; GFX9-NEXT: v_readlane_b32 s48, v63, 8 -; GFX9-NEXT: v_readlane_b32 s39, v63, 7 -; GFX9-NEXT: v_readlane_b32 s38, v63, 6 -; GFX9-NEXT: v_readlane_b32 s37, v63, 5 -; GFX9-NEXT: v_readlane_b32 s36, v63, 4 -; GFX9-NEXT: v_readlane_b32 s35, v63, 3 -; GFX9-NEXT: v_readlane_b32 s34, v63, 2 -; GFX9-NEXT: v_readlane_b32 s31, v63, 1 -; GFX9-NEXT: v_readlane_b32 s30, v63, 0 +; GFX9-NEXT: v_readlane_b32 s30, v63, 34 +; GFX9-NEXT: v_readlane_b32 s31, v63, 35 +; GFX9-NEXT: v_readlane_b32 s99, v63, 33 +; GFX9-NEXT: v_readlane_b32 s98, v63, 32 +; GFX9-NEXT: v_readlane_b32 s97, v63, 31 +; GFX9-NEXT: v_readlane_b32 s96, v63, 30 +; GFX9-NEXT: v_readlane_b32 s87, v63, 29 +; GFX9-NEXT: v_readlane_b32 s86, v63, 28 +; GFX9-NEXT: v_readlane_b32 s85, v63, 27 +; GFX9-NEXT: v_readlane_b32 s84, v63, 26 +; GFX9-NEXT: v_readlane_b32 s83, v63, 25 +; GFX9-NEXT: v_readlane_b32 s82, v63, 24 +; GFX9-NEXT: v_readlane_b32 s81, v63, 23 +; GFX9-NEXT: v_readlane_b32 s80, v63, 22 +; GFX9-NEXT: v_readlane_b32 s71, v63, 21 +; GFX9-NEXT: v_readlane_b32 s70, v63, 20 +; GFX9-NEXT: v_readlane_b32 s69, v63, 19 +; GFX9-NEXT: v_readlane_b32 s68, v63, 18 +; GFX9-NEXT: v_readlane_b32 s67, v63, 17 +; GFX9-NEXT: v_readlane_b32 s66, v63, 16 +; GFX9-NEXT: v_readlane_b32 s65, v63, 15 +; GFX9-NEXT: v_readlane_b32 s64, v63, 14 +; GFX9-NEXT: v_readlane_b32 s55, v63, 13 +; GFX9-NEXT: v_readlane_b32 s54, v63, 12 +; GFX9-NEXT: v_readlane_b32 s53, v63, 11 +; GFX9-NEXT: v_readlane_b32 s52, v63, 10 +; GFX9-NEXT: v_readlane_b32 s51, v63, 9 +; GFX9-NEXT: v_readlane_b32 s50, v63, 8 +; GFX9-NEXT: v_readlane_b32 s49, v63, 7 +; GFX9-NEXT: v_readlane_b32 s48, v63, 6 +; GFX9-NEXT: v_readlane_b32 s39, v63, 5 +; GFX9-NEXT: v_readlane_b32 s38, v63, 4 +; GFX9-NEXT: v_readlane_b32 s37, v63, 3 +; GFX9-NEXT: v_readlane_b32 s36, v63, 2 +; GFX9-NEXT: v_readlane_b32 s35, v63, 1 +; GFX9-NEXT: v_readlane_b32 s34, v63, 0 ; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v15 ; GFX9-NEXT: v_or_b32_sdwa v15, v38, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -196717,90 +198831,111 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v75, s30, 0 -; GFX11-NEXT: v_writelane_b32 v76, s96, 0 -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_readfirstlane_b32 s40, v1 -; GFX11-NEXT: v_readfirstlane_b32 s41, v2 -; GFX11-NEXT: v_writelane_b32 v75, s31, 1 -; GFX11-NEXT: v_writelane_b32 v76, s97, 1 -; GFX11-NEXT: v_readfirstlane_b32 s14, v3 -; GFX11-NEXT: v_readfirstlane_b32 s15, v4 -; GFX11-NEXT: v_readfirstlane_b32 s12, v5 -; GFX11-NEXT: v_writelane_b32 v75, s34, 2 -; GFX11-NEXT: v_writelane_b32 v76, s98, 2 -; GFX11-NEXT: v_readfirstlane_b32 s13, v6 -; GFX11-NEXT: v_readfirstlane_b32 s10, v7 -; GFX11-NEXT: v_readfirstlane_b32 s11, v8 -; GFX11-NEXT: v_writelane_b32 v75, s35, 3 -; GFX11-NEXT: v_writelane_b32 v76, s99, 3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v9 -; GFX11-NEXT: v_readfirstlane_b32 s9, v10 -; GFX11-NEXT: v_readfirstlane_b32 s6, v11 -; GFX11-NEXT: v_writelane_b32 v75, s36, 4 -; GFX11-NEXT: v_writelane_b32 v76, s100, 4 -; GFX11-NEXT: v_readfirstlane_b32 s7, v12 -; GFX11-NEXT: v_readfirstlane_b32 s4, v13 -; GFX11-NEXT: v_readfirstlane_b32 s5, v14 -; GFX11-NEXT: v_writelane_b32 v75, s37, 5 -; GFX11-NEXT: v_writelane_b32 v76, s101, 5 -; GFX11-NEXT: s_mov_b32 s99, 0 -; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: s_clause 0x12 ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:40 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 -; GFX11-NEXT: v_writelane_b32 v75, s38, 6 -; GFX11-NEXT: v_writelane_b32 v76, s102, 6 +; GFX11-NEXT: v_writelane_b32 v75, s34, 0 +; GFX11-NEXT: v_writelane_b32 v75, s35, 1 +; GFX11-NEXT: v_writelane_b32 v75, s36, 2 +; GFX11-NEXT: v_writelane_b32 v75, s37, 3 +; GFX11-NEXT: v_writelane_b32 v75, s38, 4 +; GFX11-NEXT: v_writelane_b32 v75, s39, 5 +; GFX11-NEXT: v_writelane_b32 v75, s48, 6 +; GFX11-NEXT: v_writelane_b32 v75, s49, 7 +; GFX11-NEXT: v_writelane_b32 v75, s50, 8 +; GFX11-NEXT: v_writelane_b32 v75, s51, 9 +; GFX11-NEXT: v_writelane_b32 v75, s52, 10 +; GFX11-NEXT: v_writelane_b32 v75, s53, 11 +; GFX11-NEXT: v_writelane_b32 v75, s54, 12 +; GFX11-NEXT: v_writelane_b32 v75, s55, 13 +; GFX11-NEXT: v_writelane_b32 v75, s64, 14 +; GFX11-NEXT: v_writelane_b32 v75, s65, 15 +; GFX11-NEXT: v_writelane_b32 v75, s66, 16 +; GFX11-NEXT: v_writelane_b32 v75, s67, 17 +; GFX11-NEXT: v_writelane_b32 v75, s68, 18 +; GFX11-NEXT: v_writelane_b32 v75, s69, 19 +; GFX11-NEXT: v_writelane_b32 v75, s70, 20 +; GFX11-NEXT: v_writelane_b32 v75, s71, 21 +; GFX11-NEXT: v_writelane_b32 v75, s80, 22 +; GFX11-NEXT: v_writelane_b32 v75, s81, 23 +; GFX11-NEXT: v_writelane_b32 v75, s82, 24 +; GFX11-NEXT: v_writelane_b32 v75, s83, 25 +; GFX11-NEXT: v_writelane_b32 v75, s84, 26 +; GFX11-NEXT: v_writelane_b32 v75, s85, 27 +; GFX11-NEXT: v_writelane_b32 v75, s86, 28 +; GFX11-NEXT: v_writelane_b32 v75, s87, 29 +; GFX11-NEXT: v_writelane_b32 v75, s96, 30 +; GFX11-NEXT: v_writelane_b32 v75, s97, 31 +; GFX11-NEXT: v_writelane_b32 v76, s98, 0 +; GFX11-NEXT: v_writelane_b32 v76, s99, 1 +; GFX11-NEXT: v_writelane_b32 v76, s100, 2 +; GFX11-NEXT: v_writelane_b32 v76, s101, 3 +; GFX11-NEXT: v_writelane_b32 v76, s102, 4 +; GFX11-NEXT: v_writelane_b32 v76, s103, 5 +; GFX11-NEXT: v_writelane_b32 v76, s104, 6 +; GFX11-NEXT: v_writelane_b32 v76, s30, 7 +; GFX11-NEXT: v_writelane_b32 v76, s31, 8 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 +; GFX11-NEXT: v_readfirstlane_b32 s40, v1 +; GFX11-NEXT: v_readfirstlane_b32 s41, v2 +; GFX11-NEXT: v_readfirstlane_b32 s14, v3 +; GFX11-NEXT: v_readfirstlane_b32 s15, v4 +; GFX11-NEXT: v_readfirstlane_b32 s12, v5 +; GFX11-NEXT: v_readfirstlane_b32 s13, v6 +; GFX11-NEXT: v_readfirstlane_b32 s10, v7 +; GFX11-NEXT: v_readfirstlane_b32 s11, v8 +; GFX11-NEXT: v_readfirstlane_b32 s8, v9 +; GFX11-NEXT: v_readfirstlane_b32 s9, v10 +; GFX11-NEXT: v_readfirstlane_b32 s6, v11 +; GFX11-NEXT: v_readfirstlane_b32 s7, v12 +; GFX11-NEXT: v_readfirstlane_b32 s4, v13 +; GFX11-NEXT: v_readfirstlane_b32 s5, v14 +; GFX11-NEXT: s_mov_b32 s99, 0 +; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane ; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v75, s39, 7 -; GFX11-NEXT: v_writelane_b32 v76, s103, 7 -; GFX11-NEXT: v_writelane_b32 v75, s48, 8 -; GFX11-NEXT: v_writelane_b32 v76, s104, 8 -; GFX11-NEXT: v_writelane_b32 v75, s49, 9 -; GFX11-NEXT: v_writelane_b32 v75, s50, 10 -; GFX11-NEXT: v_writelane_b32 v75, s51, 11 -; GFX11-NEXT: v_writelane_b32 v75, s52, 12 -; GFX11-NEXT: v_writelane_b32 v75, s53, 13 -; GFX11-NEXT: v_writelane_b32 v75, s54, 14 -; GFX11-NEXT: v_writelane_b32 v75, s55, 15 -; GFX11-NEXT: v_writelane_b32 v75, s64, 16 -; GFX11-NEXT: v_writelane_b32 v75, s65, 17 -; GFX11-NEXT: v_writelane_b32 v75, s66, 18 -; GFX11-NEXT: v_writelane_b32 v75, s67, 19 -; GFX11-NEXT: v_writelane_b32 v75, s68, 20 -; GFX11-NEXT: v_writelane_b32 v75, s69, 21 -; GFX11-NEXT: v_writelane_b32 v75, s70, 22 -; GFX11-NEXT: v_writelane_b32 v75, s71, 23 -; GFX11-NEXT: v_writelane_b32 v75, s80, 24 -; GFX11-NEXT: v_writelane_b32 v75, s81, 25 -; GFX11-NEXT: v_writelane_b32 v75, s82, 26 -; GFX11-NEXT: v_writelane_b32 v75, s83, 27 -; GFX11-NEXT: v_writelane_b32 v75, s84, 28 -; GFX11-NEXT: v_writelane_b32 v75, s85, 29 -; GFX11-NEXT: v_writelane_b32 v75, s86, 30 -; GFX11-NEXT: v_writelane_b32 v75, s87, 31 ; GFX11-NEXT: s_cbranch_scc0 .LBB95_3 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s42, s27, 16 @@ -197689,47 +199824,47 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:64 ; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:68 ; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:72 -; GFX11-NEXT: v_readlane_b32 s104, v76, 8 -; GFX11-NEXT: v_readlane_b32 s103, v76, 7 -; GFX11-NEXT: v_readlane_b32 s102, v76, 6 -; GFX11-NEXT: v_readlane_b32 s101, v76, 5 -; GFX11-NEXT: v_readlane_b32 s100, v76, 4 -; GFX11-NEXT: v_readlane_b32 s99, v76, 3 -; GFX11-NEXT: v_readlane_b32 s98, v76, 2 -; GFX11-NEXT: v_readlane_b32 s97, v76, 1 -; GFX11-NEXT: v_readlane_b32 s96, v76, 0 -; GFX11-NEXT: v_readlane_b32 s87, v75, 31 -; GFX11-NEXT: v_readlane_b32 s86, v75, 30 -; GFX11-NEXT: v_readlane_b32 s85, v75, 29 -; GFX11-NEXT: v_readlane_b32 s84, v75, 28 -; GFX11-NEXT: v_readlane_b32 s83, v75, 27 -; GFX11-NEXT: v_readlane_b32 s82, v75, 26 -; GFX11-NEXT: v_readlane_b32 s81, v75, 25 -; GFX11-NEXT: v_readlane_b32 s80, v75, 24 -; GFX11-NEXT: v_readlane_b32 s71, v75, 23 -; GFX11-NEXT: v_readlane_b32 s70, v75, 22 -; GFX11-NEXT: v_readlane_b32 s69, v75, 21 -; GFX11-NEXT: v_readlane_b32 s68, v75, 20 -; GFX11-NEXT: v_readlane_b32 s67, v75, 19 -; GFX11-NEXT: v_readlane_b32 s66, v75, 18 -; GFX11-NEXT: v_readlane_b32 s65, v75, 17 -; GFX11-NEXT: v_readlane_b32 s64, v75, 16 -; GFX11-NEXT: v_readlane_b32 s55, v75, 15 -; GFX11-NEXT: v_readlane_b32 s54, v75, 14 -; GFX11-NEXT: v_readlane_b32 s53, v75, 13 -; GFX11-NEXT: v_readlane_b32 s52, v75, 12 -; GFX11-NEXT: v_readlane_b32 s51, v75, 11 -; GFX11-NEXT: v_readlane_b32 s50, v75, 10 -; GFX11-NEXT: v_readlane_b32 s49, v75, 9 -; GFX11-NEXT: v_readlane_b32 s48, v75, 8 -; GFX11-NEXT: v_readlane_b32 s39, v75, 7 -; GFX11-NEXT: v_readlane_b32 s38, v75, 6 -; GFX11-NEXT: v_readlane_b32 s37, v75, 5 -; GFX11-NEXT: v_readlane_b32 s36, v75, 4 -; GFX11-NEXT: v_readlane_b32 s35, v75, 3 -; GFX11-NEXT: v_readlane_b32 s34, v75, 2 -; GFX11-NEXT: v_readlane_b32 s31, v75, 1 -; GFX11-NEXT: v_readlane_b32 s30, v75, 0 +; GFX11-NEXT: v_readlane_b32 s30, v76, 7 +; GFX11-NEXT: v_readlane_b32 s31, v76, 8 +; GFX11-NEXT: v_readlane_b32 s104, v76, 6 +; GFX11-NEXT: v_readlane_b32 s103, v76, 5 +; GFX11-NEXT: v_readlane_b32 s102, v76, 4 +; GFX11-NEXT: v_readlane_b32 s101, v76, 3 +; GFX11-NEXT: v_readlane_b32 s100, v76, 2 +; GFX11-NEXT: v_readlane_b32 s99, v76, 1 +; GFX11-NEXT: v_readlane_b32 s98, v76, 0 +; GFX11-NEXT: v_readlane_b32 s97, v75, 31 +; GFX11-NEXT: v_readlane_b32 s96, v75, 30 +; GFX11-NEXT: v_readlane_b32 s87, v75, 29 +; GFX11-NEXT: v_readlane_b32 s86, v75, 28 +; GFX11-NEXT: v_readlane_b32 s85, v75, 27 +; GFX11-NEXT: v_readlane_b32 s84, v75, 26 +; GFX11-NEXT: v_readlane_b32 s83, v75, 25 +; GFX11-NEXT: v_readlane_b32 s82, v75, 24 +; GFX11-NEXT: v_readlane_b32 s81, v75, 23 +; GFX11-NEXT: v_readlane_b32 s80, v75, 22 +; GFX11-NEXT: v_readlane_b32 s71, v75, 21 +; GFX11-NEXT: v_readlane_b32 s70, v75, 20 +; GFX11-NEXT: v_readlane_b32 s69, v75, 19 +; GFX11-NEXT: v_readlane_b32 s68, v75, 18 +; GFX11-NEXT: v_readlane_b32 s67, v75, 17 +; GFX11-NEXT: v_readlane_b32 s66, v75, 16 +; GFX11-NEXT: v_readlane_b32 s65, v75, 15 +; GFX11-NEXT: v_readlane_b32 s64, v75, 14 +; GFX11-NEXT: v_readlane_b32 s55, v75, 13 +; GFX11-NEXT: v_readlane_b32 s54, v75, 12 +; GFX11-NEXT: v_readlane_b32 s53, v75, 11 +; GFX11-NEXT: v_readlane_b32 s52, v75, 10 +; GFX11-NEXT: v_readlane_b32 s51, v75, 9 +; GFX11-NEXT: v_readlane_b32 s50, v75, 8 +; GFX11-NEXT: v_readlane_b32 s49, v75, 7 +; GFX11-NEXT: v_readlane_b32 s48, v75, 6 +; GFX11-NEXT: v_readlane_b32 s39, v75, 5 +; GFX11-NEXT: v_readlane_b32 s38, v75, 4 +; GFX11-NEXT: v_readlane_b32 s37, v75, 3 +; GFX11-NEXT: v_readlane_b32 s36, v75, 2 +; GFX11-NEXT: v_readlane_b32 s35, v75, 1 +; GFX11-NEXT: v_readlane_b32 s34, v75, 0 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:76 @@ -203149,53 +205284,99 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1f ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:580 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:576 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:572 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:568 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:564 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:560 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:556 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:552 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:548 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:544 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:540 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:536 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:532 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:528 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:524 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:520 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:516 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:512 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:508 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:504 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:500 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:496 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:492 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:488 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:484 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:480 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:476 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:468 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:456 ; GFX11-FAKE16-NEXT: s_clause 0xf ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:392 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26 @@ -204088,6 +206269,43 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3 ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: v_writelane_b32 v41, s34, 0 +; SI-NEXT: v_writelane_b32 v41, s35, 1 +; SI-NEXT: v_writelane_b32 v41, s36, 2 +; SI-NEXT: v_writelane_b32 v41, s37, 3 +; SI-NEXT: v_writelane_b32 v41, s38, 4 +; SI-NEXT: v_writelane_b32 v41, s39, 5 +; SI-NEXT: v_writelane_b32 v41, s48, 6 +; SI-NEXT: v_writelane_b32 v41, s49, 7 +; SI-NEXT: v_writelane_b32 v41, s50, 8 +; SI-NEXT: v_writelane_b32 v41, s51, 9 +; SI-NEXT: v_writelane_b32 v41, s52, 10 +; SI-NEXT: v_writelane_b32 v41, s53, 11 +; SI-NEXT: v_writelane_b32 v41, s54, 12 +; SI-NEXT: v_writelane_b32 v41, s55, 13 +; SI-NEXT: v_writelane_b32 v41, s64, 14 +; SI-NEXT: v_writelane_b32 v41, s65, 15 +; SI-NEXT: v_writelane_b32 v41, s66, 16 +; SI-NEXT: v_writelane_b32 v41, s67, 17 +; SI-NEXT: v_writelane_b32 v41, s68, 18 +; SI-NEXT: v_writelane_b32 v41, s69, 19 +; SI-NEXT: v_writelane_b32 v41, s70, 20 +; SI-NEXT: v_writelane_b32 v41, s71, 21 +; SI-NEXT: v_writelane_b32 v41, s80, 22 +; SI-NEXT: v_writelane_b32 v41, s81, 23 +; SI-NEXT: v_writelane_b32 v41, s82, 24 +; SI-NEXT: v_writelane_b32 v41, s83, 25 +; SI-NEXT: v_writelane_b32 v41, s84, 26 +; SI-NEXT: v_writelane_b32 v41, s85, 27 +; SI-NEXT: v_writelane_b32 v41, s86, 28 +; SI-NEXT: v_writelane_b32 v41, s87, 29 +; SI-NEXT: v_writelane_b32 v41, s96, 30 +; SI-NEXT: v_writelane_b32 v41, s97, 31 +; SI-NEXT: v_writelane_b32 v41, s98, 32 +; SI-NEXT: v_writelane_b32 v41, s99, 33 +; SI-NEXT: v_writelane_b32 v41, s30, 34 +; SI-NEXT: v_writelane_b32 v41, s31, 35 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:328 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324 @@ -204097,8 +206315,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:308 ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:304 ; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_writelane_b32 v41, s30, 0 +; SI-NEXT: v_readfirstlane_b32 s39, v26 ; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_writelane_b32 v43, s29, 0 ; SI-NEXT: v_writelane_b32 v43, s28, 1 @@ -204114,41 +206331,6 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3 ; SI-NEXT: v_writelane_b32 v43, s18, 11 ; SI-NEXT: v_writelane_b32 v43, s17, 12 ; SI-NEXT: v_writelane_b32 v43, s16, 13 -; SI-NEXT: v_writelane_b32 v41, s31, 1 -; SI-NEXT: v_writelane_b32 v41, s34, 2 -; SI-NEXT: v_writelane_b32 v41, s35, 3 -; SI-NEXT: v_writelane_b32 v41, s36, 4 -; SI-NEXT: v_writelane_b32 v41, s37, 5 -; SI-NEXT: v_writelane_b32 v41, s38, 6 -; SI-NEXT: v_writelane_b32 v41, s39, 7 -; SI-NEXT: v_writelane_b32 v41, s48, 8 -; SI-NEXT: v_writelane_b32 v41, s49, 9 -; SI-NEXT: v_writelane_b32 v41, s50, 10 -; SI-NEXT: v_writelane_b32 v41, s51, 11 -; SI-NEXT: v_writelane_b32 v41, s52, 12 -; SI-NEXT: v_writelane_b32 v41, s53, 13 -; SI-NEXT: v_writelane_b32 v41, s54, 14 -; SI-NEXT: v_writelane_b32 v41, s55, 15 -; SI-NEXT: v_writelane_b32 v41, s64, 16 -; SI-NEXT: v_writelane_b32 v41, s65, 17 -; SI-NEXT: v_writelane_b32 v41, s66, 18 -; SI-NEXT: v_writelane_b32 v41, s67, 19 -; SI-NEXT: v_writelane_b32 v41, s68, 20 -; SI-NEXT: v_writelane_b32 v41, s69, 21 -; SI-NEXT: v_writelane_b32 v41, s70, 22 -; SI-NEXT: v_writelane_b32 v41, s71, 23 -; SI-NEXT: v_writelane_b32 v41, s80, 24 -; SI-NEXT: v_writelane_b32 v41, s81, 25 -; SI-NEXT: v_writelane_b32 v41, s82, 26 -; SI-NEXT: v_writelane_b32 v41, s83, 27 -; SI-NEXT: v_writelane_b32 v41, s84, 28 -; SI-NEXT: v_writelane_b32 v41, s85, 29 -; SI-NEXT: v_writelane_b32 v41, s86, 30 -; SI-NEXT: v_writelane_b32 v41, s87, 31 -; SI-NEXT: v_writelane_b32 v41, s96, 32 -; SI-NEXT: v_writelane_b32 v41, s97, 33 -; SI-NEXT: v_writelane_b32 v41, s98, 34 -; SI-NEXT: v_readfirstlane_b32 s39, v26 ; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane ; SI-NEXT: v_readfirstlane_b32 s47, v12 ; SI-NEXT: v_writelane_b32 v42, s39, 0 @@ -204172,6 +206354,18 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s11, v1 ; SI-NEXT: v_readfirstlane_b32 s12, v2 ; SI-NEXT: v_readfirstlane_b32 s13, v9 +; SI-NEXT: v_readfirstlane_b32 s14, v10 +; SI-NEXT: v_readfirstlane_b32 s15, v8 +; SI-NEXT: v_readfirstlane_b32 s18, v7 +; SI-NEXT: v_readfirstlane_b32 s21, v5 +; SI-NEXT: v_readfirstlane_b32 s22, v6 +; SI-NEXT: v_readfirstlane_b32 s40, v17 +; SI-NEXT: v_readfirstlane_b32 s41, v18 +; SI-NEXT: v_readfirstlane_b32 s42, v4 +; SI-NEXT: v_readfirstlane_b32 s43, v3 +; SI-NEXT: v_readfirstlane_b32 s76, v16 +; SI-NEXT: v_readfirstlane_b32 s77, v15 +; SI-NEXT: v_readfirstlane_b32 s38, v25 ; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_readfirstlane_b32 s4, v31 ; SI-NEXT: v_writelane_b32 v43, s4, 14 @@ -204205,19 +206399,6 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:256 ; SI-NEXT: s_waitcnt vmcnt(12) ; SI-NEXT: v_readfirstlane_b32 s6, v38 -; SI-NEXT: v_readfirstlane_b32 s14, v10 -; SI-NEXT: v_readfirstlane_b32 s15, v8 -; SI-NEXT: v_readfirstlane_b32 s18, v7 -; SI-NEXT: v_readfirstlane_b32 s21, v5 -; SI-NEXT: v_readfirstlane_b32 s22, v6 -; SI-NEXT: v_readfirstlane_b32 s40, v17 -; SI-NEXT: v_readfirstlane_b32 s41, v18 -; SI-NEXT: v_readfirstlane_b32 s42, v4 -; SI-NEXT: v_readfirstlane_b32 s43, v3 -; SI-NEXT: v_readfirstlane_b32 s76, v16 -; SI-NEXT: v_readfirstlane_b32 s77, v15 -; SI-NEXT: v_readfirstlane_b32 s38, v25 -; SI-NEXT: v_writelane_b32 v41, s99, 35 ; SI-NEXT: s_waitcnt vmcnt(11) ; SI-NEXT: v_readfirstlane_b32 s4, v31 ; SI-NEXT: v_writelane_b32 v43, s4, 19 @@ -205721,42 +207902,42 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3 ; SI-NEXT: v_mov_b32_e32 v1, s4 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; SI-NEXT: v_readlane_b32 s99, v41, 35 -; SI-NEXT: v_readlane_b32 s98, v41, 34 -; SI-NEXT: v_readlane_b32 s97, v41, 33 -; SI-NEXT: v_readlane_b32 s96, v41, 32 -; SI-NEXT: v_readlane_b32 s87, v41, 31 -; SI-NEXT: v_readlane_b32 s86, v41, 30 -; SI-NEXT: v_readlane_b32 s85, v41, 29 -; SI-NEXT: v_readlane_b32 s84, v41, 28 -; SI-NEXT: v_readlane_b32 s83, v41, 27 -; SI-NEXT: v_readlane_b32 s82, v41, 26 -; SI-NEXT: v_readlane_b32 s81, v41, 25 -; SI-NEXT: v_readlane_b32 s80, v41, 24 -; SI-NEXT: v_readlane_b32 s71, v41, 23 -; SI-NEXT: v_readlane_b32 s70, v41, 22 -; SI-NEXT: v_readlane_b32 s69, v41, 21 -; SI-NEXT: v_readlane_b32 s68, v41, 20 -; SI-NEXT: v_readlane_b32 s67, v41, 19 -; SI-NEXT: v_readlane_b32 s66, v41, 18 -; SI-NEXT: v_readlane_b32 s65, v41, 17 -; SI-NEXT: v_readlane_b32 s64, v41, 16 -; SI-NEXT: v_readlane_b32 s55, v41, 15 -; SI-NEXT: v_readlane_b32 s54, v41, 14 -; SI-NEXT: v_readlane_b32 s53, v41, 13 -; SI-NEXT: v_readlane_b32 s52, v41, 12 -; SI-NEXT: v_readlane_b32 s51, v41, 11 -; SI-NEXT: v_readlane_b32 s50, v41, 10 -; SI-NEXT: v_readlane_b32 s49, v41, 9 -; SI-NEXT: v_readlane_b32 s48, v41, 8 -; SI-NEXT: v_readlane_b32 s39, v41, 7 -; SI-NEXT: v_readlane_b32 s38, v41, 6 -; SI-NEXT: v_readlane_b32 s37, v41, 5 -; SI-NEXT: v_readlane_b32 s36, v41, 4 -; SI-NEXT: v_readlane_b32 s35, v41, 3 -; SI-NEXT: v_readlane_b32 s34, v41, 2 -; SI-NEXT: v_readlane_b32 s31, v41, 1 -; SI-NEXT: v_readlane_b32 s30, v41, 0 +; SI-NEXT: v_readlane_b32 s30, v41, 34 +; SI-NEXT: v_readlane_b32 s31, v41, 35 +; SI-NEXT: v_readlane_b32 s99, v41, 33 +; SI-NEXT: v_readlane_b32 s98, v41, 32 +; SI-NEXT: v_readlane_b32 s97, v41, 31 +; SI-NEXT: v_readlane_b32 s96, v41, 30 +; SI-NEXT: v_readlane_b32 s87, v41, 29 +; SI-NEXT: v_readlane_b32 s86, v41, 28 +; SI-NEXT: v_readlane_b32 s85, v41, 27 +; SI-NEXT: v_readlane_b32 s84, v41, 26 +; SI-NEXT: v_readlane_b32 s83, v41, 25 +; SI-NEXT: v_readlane_b32 s82, v41, 24 +; SI-NEXT: v_readlane_b32 s81, v41, 23 +; SI-NEXT: v_readlane_b32 s80, v41, 22 +; SI-NEXT: v_readlane_b32 s71, v41, 21 +; SI-NEXT: v_readlane_b32 s70, v41, 20 +; SI-NEXT: v_readlane_b32 s69, v41, 19 +; SI-NEXT: v_readlane_b32 s68, v41, 18 +; SI-NEXT: v_readlane_b32 s67, v41, 17 +; SI-NEXT: v_readlane_b32 s66, v41, 16 +; SI-NEXT: v_readlane_b32 s65, v41, 15 +; SI-NEXT: v_readlane_b32 s64, v41, 14 +; SI-NEXT: v_readlane_b32 s55, v41, 13 +; SI-NEXT: v_readlane_b32 s54, v41, 12 +; SI-NEXT: v_readlane_b32 s53, v41, 11 +; SI-NEXT: v_readlane_b32 s52, v41, 10 +; SI-NEXT: v_readlane_b32 s51, v41, 9 +; SI-NEXT: v_readlane_b32 s50, v41, 8 +; SI-NEXT: v_readlane_b32 s49, v41, 7 +; SI-NEXT: v_readlane_b32 s48, v41, 6 +; SI-NEXT: v_readlane_b32 s39, v41, 5 +; SI-NEXT: v_readlane_b32 s38, v41, 4 +; SI-NEXT: v_readlane_b32 s37, v41, 3 +; SI-NEXT: v_readlane_b32 s36, v41, 2 +; SI-NEXT: v_readlane_b32 s35, v41, 1 +; SI-NEXT: v_readlane_b32 s34, v41, 0 ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload @@ -207905,35 +210086,65 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1e ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:440 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:436 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:432 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:428 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:424 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:420 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:416 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:412 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:408 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:404 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:400 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:396 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:392 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:388 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:384 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:380 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:376 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:372 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:368 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:364 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:360 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:356 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:352 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:348 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:344 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:340 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:336 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:332 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:328 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:324 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:320 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26 @@ -208677,35 +210888,65 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1e ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:400 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:396 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:392 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:388 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:384 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:380 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:376 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:372 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:368 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:364 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:360 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:356 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:352 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:348 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:344 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:340 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:336 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:332 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:328 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:324 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:320 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26 @@ -214217,24 +216458,43 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) { ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x13 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12 ; GFX11-FAKE16-NEXT: s_clause 0x2 ; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8 @@ -214925,6 +217185,43 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: v_writelane_b32 v40, s34, 0 +; SI-NEXT: v_writelane_b32 v40, s35, 1 +; SI-NEXT: v_writelane_b32 v40, s36, 2 +; SI-NEXT: v_writelane_b32 v40, s37, 3 +; SI-NEXT: v_writelane_b32 v40, s38, 4 +; SI-NEXT: v_writelane_b32 v40, s39, 5 +; SI-NEXT: v_writelane_b32 v40, s48, 6 +; SI-NEXT: v_writelane_b32 v40, s49, 7 +; SI-NEXT: v_writelane_b32 v40, s50, 8 +; SI-NEXT: v_writelane_b32 v40, s51, 9 +; SI-NEXT: v_writelane_b32 v40, s52, 10 +; SI-NEXT: v_writelane_b32 v40, s53, 11 +; SI-NEXT: v_writelane_b32 v40, s54, 12 +; SI-NEXT: v_writelane_b32 v40, s55, 13 +; SI-NEXT: v_writelane_b32 v40, s64, 14 +; SI-NEXT: v_writelane_b32 v40, s65, 15 +; SI-NEXT: v_writelane_b32 v40, s66, 16 +; SI-NEXT: v_writelane_b32 v40, s67, 17 +; SI-NEXT: v_writelane_b32 v40, s68, 18 +; SI-NEXT: v_writelane_b32 v40, s69, 19 +; SI-NEXT: v_writelane_b32 v40, s70, 20 +; SI-NEXT: v_writelane_b32 v40, s71, 21 +; SI-NEXT: v_writelane_b32 v40, s80, 22 +; SI-NEXT: v_writelane_b32 v40, s81, 23 +; SI-NEXT: v_writelane_b32 v40, s82, 24 +; SI-NEXT: v_writelane_b32 v40, s83, 25 +; SI-NEXT: v_writelane_b32 v40, s84, 26 +; SI-NEXT: v_writelane_b32 v40, s85, 27 +; SI-NEXT: v_writelane_b32 v40, s86, 28 +; SI-NEXT: v_writelane_b32 v40, s87, 29 +; SI-NEXT: v_writelane_b32 v40, s96, 30 +; SI-NEXT: v_writelane_b32 v40, s97, 31 +; SI-NEXT: v_writelane_b32 v40, s98, 32 +; SI-NEXT: v_writelane_b32 v40, s99, 33 +; SI-NEXT: v_writelane_b32 v40, s30, 34 +; SI-NEXT: v_writelane_b32 v40, s31, 35 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68 @@ -214933,36 +217230,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52 ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_writelane_b32 v40, s30, 0 -; SI-NEXT: v_writelane_b32 v40, s31, 1 -; SI-NEXT: v_writelane_b32 v40, s34, 2 -; SI-NEXT: v_writelane_b32 v40, s35, 3 -; SI-NEXT: v_writelane_b32 v40, s36, 4 -; SI-NEXT: v_writelane_b32 v40, s37, 5 -; SI-NEXT: v_writelane_b32 v40, s38, 6 -; SI-NEXT: v_writelane_b32 v40, s39, 7 -; SI-NEXT: v_writelane_b32 v40, s48, 8 -; SI-NEXT: v_writelane_b32 v40, s49, 9 -; SI-NEXT: v_writelane_b32 v40, s50, 10 -; SI-NEXT: v_writelane_b32 v40, s51, 11 -; SI-NEXT: v_writelane_b32 v40, s52, 12 -; SI-NEXT: v_writelane_b32 v40, s53, 13 -; SI-NEXT: v_writelane_b32 v40, s54, 14 -; SI-NEXT: v_writelane_b32 v40, s55, 15 -; SI-NEXT: v_writelane_b32 v40, s64, 16 -; SI-NEXT: v_writelane_b32 v40, s65, 17 -; SI-NEXT: v_writelane_b32 v40, s66, 18 -; SI-NEXT: v_writelane_b32 v40, s67, 19 -; SI-NEXT: v_writelane_b32 v40, s68, 20 -; SI-NEXT: v_writelane_b32 v40, s69, 21 -; SI-NEXT: v_writelane_b32 v40, s70, 22 ; SI-NEXT: s_mov_b32 s88, s17 -; SI-NEXT: v_writelane_b32 v40, s71, 23 -; SI-NEXT: v_writelane_b32 v40, s80, 24 -; SI-NEXT: v_writelane_b32 v40, s81, 25 -; SI-NEXT: v_writelane_b32 v40, s82, 26 -; SI-NEXT: v_writelane_b32 v40, s83, 27 ; SI-NEXT: v_readfirstlane_b32 s6, v16 ; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane ; SI-NEXT: v_readfirstlane_b32 s7, v15 @@ -214988,14 +217256,6 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s16, v27 ; SI-NEXT: v_writelane_b32 v41, s14, 9 ; SI-NEXT: v_writelane_b32 v41, s16, 10 -; SI-NEXT: v_writelane_b32 v40, s84, 28 -; SI-NEXT: v_writelane_b32 v40, s85, 29 -; SI-NEXT: v_writelane_b32 v40, s86, 30 -; SI-NEXT: v_writelane_b32 v40, s87, 31 -; SI-NEXT: v_writelane_b32 v40, s96, 32 -; SI-NEXT: v_writelane_b32 v40, s97, 33 -; SI-NEXT: v_writelane_b32 v40, s98, 34 -; SI-NEXT: v_writelane_b32 v40, s99, 35 ; SI-NEXT: v_readfirstlane_b32 s98, v30 ; SI-NEXT: v_readfirstlane_b32 s97, v26 ; SI-NEXT: v_readfirstlane_b32 s96, v22 @@ -215008,6 +217268,15 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s85, v10 ; SI-NEXT: v_readfirstlane_b32 s51, v9 ; SI-NEXT: v_readfirstlane_b32 s53, v8 +; SI-NEXT: v_readfirstlane_b32 s65, v7 +; SI-NEXT: v_readfirstlane_b32 s84, v6 +; SI-NEXT: v_readfirstlane_b32 s31, v5 +; SI-NEXT: v_readfirstlane_b32 s37, v4 +; SI-NEXT: v_readfirstlane_b32 s49, v3 +; SI-NEXT: v_readfirstlane_b32 s78, v2 +; SI-NEXT: v_readfirstlane_b32 s39, v1 +; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane +; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane ; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_readfirstlane_b32 s89, v31 ; SI-NEXT: s_waitcnt vmcnt(6) @@ -215037,15 +217306,6 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; SI-NEXT: s_waitcnt vmcnt(12) ; SI-NEXT: v_readfirstlane_b32 s83, v38 ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:80 -; SI-NEXT: v_readfirstlane_b32 s65, v7 -; SI-NEXT: v_readfirstlane_b32 s84, v6 -; SI-NEXT: v_readfirstlane_b32 s31, v5 -; SI-NEXT: v_readfirstlane_b32 s37, v4 -; SI-NEXT: v_readfirstlane_b32 s49, v3 -; SI-NEXT: v_readfirstlane_b32 s78, v2 -; SI-NEXT: v_readfirstlane_b32 s39, v1 -; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane -; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane ; SI-NEXT: s_waitcnt vmcnt(12) ; SI-NEXT: v_readfirstlane_b32 s77, v31 ; SI-NEXT: s_waitcnt vmcnt(11) @@ -216310,6 +218570,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v40, 34 ; SI-NEXT: v_readlane_b32 s21, v41, 33 ; SI-NEXT: v_readlane_b32 s19, v41, 51 ; SI-NEXT: v_readlane_b32 s17, v41, 57 @@ -216318,42 +218579,41 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; SI-NEXT: v_readlane_b32 s11, v43, 11 ; SI-NEXT: v_readlane_b32 s9, v43, 17 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v40, 35 -; SI-NEXT: v_readlane_b32 s98, v40, 34 -; SI-NEXT: v_readlane_b32 s97, v40, 33 -; SI-NEXT: v_readlane_b32 s96, v40, 32 -; SI-NEXT: v_readlane_b32 s87, v40, 31 -; SI-NEXT: v_readlane_b32 s86, v40, 30 -; SI-NEXT: v_readlane_b32 s85, v40, 29 -; SI-NEXT: v_readlane_b32 s84, v40, 28 -; SI-NEXT: v_readlane_b32 s83, v40, 27 -; SI-NEXT: v_readlane_b32 s82, v40, 26 -; SI-NEXT: v_readlane_b32 s81, v40, 25 -; SI-NEXT: v_readlane_b32 s80, v40, 24 -; SI-NEXT: v_readlane_b32 s71, v40, 23 -; SI-NEXT: v_readlane_b32 s70, v40, 22 -; SI-NEXT: v_readlane_b32 s69, v40, 21 -; SI-NEXT: v_readlane_b32 s68, v40, 20 -; SI-NEXT: v_readlane_b32 s67, v40, 19 -; SI-NEXT: v_readlane_b32 s66, v40, 18 -; SI-NEXT: v_readlane_b32 s65, v40, 17 -; SI-NEXT: v_readlane_b32 s64, v40, 16 -; SI-NEXT: v_readlane_b32 s55, v40, 15 -; SI-NEXT: v_readlane_b32 s54, v40, 14 -; SI-NEXT: v_readlane_b32 s53, v40, 13 -; SI-NEXT: v_readlane_b32 s52, v40, 12 -; SI-NEXT: v_readlane_b32 s51, v40, 11 -; SI-NEXT: v_readlane_b32 s50, v40, 10 -; SI-NEXT: v_readlane_b32 s49, v40, 9 -; SI-NEXT: v_readlane_b32 s48, v40, 8 -; SI-NEXT: v_readlane_b32 s39, v40, 7 -; SI-NEXT: v_readlane_b32 s38, v40, 6 -; SI-NEXT: v_readlane_b32 s37, v40, 5 -; SI-NEXT: v_readlane_b32 s36, v40, 4 -; SI-NEXT: v_readlane_b32 s35, v40, 3 -; SI-NEXT: v_readlane_b32 s34, v40, 2 -; SI-NEXT: v_readlane_b32 s31, v40, 1 -; SI-NEXT: v_readlane_b32 s30, v40, 0 +; SI-NEXT: v_readlane_b32 s31, v40, 35 +; SI-NEXT: v_readlane_b32 s99, v40, 33 +; SI-NEXT: v_readlane_b32 s98, v40, 32 +; SI-NEXT: v_readlane_b32 s97, v40, 31 +; SI-NEXT: v_readlane_b32 s96, v40, 30 +; SI-NEXT: v_readlane_b32 s87, v40, 29 +; SI-NEXT: v_readlane_b32 s86, v40, 28 +; SI-NEXT: v_readlane_b32 s85, v40, 27 +; SI-NEXT: v_readlane_b32 s84, v40, 26 +; SI-NEXT: v_readlane_b32 s83, v40, 25 +; SI-NEXT: v_readlane_b32 s82, v40, 24 +; SI-NEXT: v_readlane_b32 s81, v40, 23 +; SI-NEXT: v_readlane_b32 s80, v40, 22 +; SI-NEXT: v_readlane_b32 s71, v40, 21 +; SI-NEXT: v_readlane_b32 s70, v40, 20 +; SI-NEXT: v_readlane_b32 s69, v40, 19 +; SI-NEXT: v_readlane_b32 s68, v40, 18 +; SI-NEXT: v_readlane_b32 s67, v40, 17 +; SI-NEXT: v_readlane_b32 s66, v40, 16 +; SI-NEXT: v_readlane_b32 s65, v40, 15 +; SI-NEXT: v_readlane_b32 s64, v40, 14 +; SI-NEXT: v_readlane_b32 s55, v40, 13 +; SI-NEXT: v_readlane_b32 s54, v40, 12 +; SI-NEXT: v_readlane_b32 s53, v40, 11 +; SI-NEXT: v_readlane_b32 s52, v40, 10 +; SI-NEXT: v_readlane_b32 s51, v40, 9 +; SI-NEXT: v_readlane_b32 s50, v40, 8 +; SI-NEXT: v_readlane_b32 s49, v40, 7 +; SI-NEXT: v_readlane_b32 s48, v40, 6 +; SI-NEXT: v_readlane_b32 s39, v40, 5 +; SI-NEXT: v_readlane_b32 s38, v40, 4 +; SI-NEXT: v_readlane_b32 s37, v40, 3 +; SI-NEXT: v_readlane_b32 s36, v40, 2 +; SI-NEXT: v_readlane_b32 s35, v40, 1 +; SI-NEXT: v_readlane_b32 s34, v40, 0 ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload @@ -216595,38 +218855,39 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v20, s30, 0 -; VI-NEXT: v_writelane_b32 v20, s31, 1 -; VI-NEXT: v_writelane_b32 v20, s34, 2 -; VI-NEXT: v_writelane_b32 v20, s35, 3 -; VI-NEXT: v_writelane_b32 v20, s36, 4 -; VI-NEXT: v_writelane_b32 v20, s37, 5 -; VI-NEXT: v_writelane_b32 v20, s38, 6 -; VI-NEXT: v_writelane_b32 v20, s39, 7 -; VI-NEXT: v_writelane_b32 v20, s48, 8 -; VI-NEXT: v_writelane_b32 v20, s49, 9 -; VI-NEXT: v_writelane_b32 v20, s50, 10 -; VI-NEXT: v_writelane_b32 v20, s51, 11 -; VI-NEXT: v_writelane_b32 v20, s52, 12 -; VI-NEXT: v_writelane_b32 v20, s53, 13 -; VI-NEXT: v_writelane_b32 v20, s54, 14 -; VI-NEXT: v_writelane_b32 v20, s55, 15 -; VI-NEXT: v_writelane_b32 v20, s64, 16 -; VI-NEXT: v_writelane_b32 v20, s65, 17 -; VI-NEXT: v_writelane_b32 v20, s66, 18 -; VI-NEXT: v_writelane_b32 v20, s67, 19 -; VI-NEXT: v_writelane_b32 v20, s68, 20 -; VI-NEXT: v_writelane_b32 v20, s69, 21 -; VI-NEXT: v_writelane_b32 v20, s70, 22 -; VI-NEXT: v_writelane_b32 v20, s71, 23 -; VI-NEXT: v_writelane_b32 v20, s80, 24 -; VI-NEXT: v_writelane_b32 v20, s81, 25 -; VI-NEXT: v_writelane_b32 v20, s82, 26 -; VI-NEXT: v_writelane_b32 v20, s83, 27 -; VI-NEXT: v_writelane_b32 v20, s84, 28 -; VI-NEXT: v_writelane_b32 v20, s85, 29 +; VI-NEXT: v_writelane_b32 v20, s34, 0 +; VI-NEXT: v_writelane_b32 v20, s35, 1 +; VI-NEXT: v_writelane_b32 v20, s36, 2 +; VI-NEXT: v_writelane_b32 v20, s37, 3 +; VI-NEXT: v_writelane_b32 v20, s38, 4 +; VI-NEXT: v_writelane_b32 v20, s39, 5 +; VI-NEXT: v_writelane_b32 v20, s48, 6 +; VI-NEXT: v_writelane_b32 v20, s49, 7 +; VI-NEXT: v_writelane_b32 v20, s50, 8 +; VI-NEXT: v_writelane_b32 v20, s51, 9 +; VI-NEXT: v_writelane_b32 v20, s52, 10 +; VI-NEXT: v_writelane_b32 v20, s53, 11 +; VI-NEXT: v_writelane_b32 v20, s54, 12 +; VI-NEXT: v_writelane_b32 v20, s55, 13 +; VI-NEXT: v_writelane_b32 v20, s64, 14 +; VI-NEXT: v_writelane_b32 v20, s65, 15 +; VI-NEXT: v_writelane_b32 v20, s66, 16 +; VI-NEXT: v_writelane_b32 v20, s67, 17 +; VI-NEXT: v_writelane_b32 v20, s68, 18 +; VI-NEXT: v_writelane_b32 v20, s69, 19 +; VI-NEXT: v_writelane_b32 v20, s70, 20 +; VI-NEXT: v_writelane_b32 v20, s71, 21 +; VI-NEXT: v_writelane_b32 v20, s80, 22 +; VI-NEXT: v_writelane_b32 v20, s81, 23 +; VI-NEXT: v_writelane_b32 v20, s82, 24 +; VI-NEXT: v_writelane_b32 v20, s83, 25 +; VI-NEXT: v_writelane_b32 v20, s84, 26 +; VI-NEXT: v_writelane_b32 v20, s85, 27 +; VI-NEXT: v_writelane_b32 v20, s86, 28 +; VI-NEXT: v_writelane_b32 v20, s87, 29 +; VI-NEXT: v_writelane_b32 v20, s30, 30 +; VI-NEXT: v_writelane_b32 v20, s31, 31 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v20, s86, 30 ; VI-NEXT: v_readfirstlane_b32 s42, v3 ; VI-NEXT: v_readfirstlane_b32 s43, v4 ; VI-NEXT: v_readfirstlane_b32 s40, v5 @@ -216646,7 +218907,6 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s44, v1 ; VI-NEXT: s_and_b64 s[46:47], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s45, v2 -; VI-NEXT: v_writelane_b32 v20, s87, 31 ; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB99_4 ; VI-NEXT: ; %bb.1: ; %cmp.false @@ -217561,39 +219821,39 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0 ; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_readlane_b32 s30, v20, 30 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; VI-NEXT: v_readlane_b32 s87, v20, 31 -; VI-NEXT: v_readlane_b32 s86, v20, 30 -; VI-NEXT: v_readlane_b32 s85, v20, 29 -; VI-NEXT: v_readlane_b32 s84, v20, 28 -; VI-NEXT: v_readlane_b32 s83, v20, 27 -; VI-NEXT: v_readlane_b32 s82, v20, 26 -; VI-NEXT: v_readlane_b32 s81, v20, 25 -; VI-NEXT: v_readlane_b32 s80, v20, 24 -; VI-NEXT: v_readlane_b32 s71, v20, 23 -; VI-NEXT: v_readlane_b32 s70, v20, 22 -; VI-NEXT: v_readlane_b32 s69, v20, 21 -; VI-NEXT: v_readlane_b32 s68, v20, 20 -; VI-NEXT: v_readlane_b32 s67, v20, 19 -; VI-NEXT: v_readlane_b32 s66, v20, 18 -; VI-NEXT: v_readlane_b32 s65, v20, 17 -; VI-NEXT: v_readlane_b32 s64, v20, 16 -; VI-NEXT: v_readlane_b32 s55, v20, 15 -; VI-NEXT: v_readlane_b32 s54, v20, 14 -; VI-NEXT: v_readlane_b32 s53, v20, 13 -; VI-NEXT: v_readlane_b32 s52, v20, 12 -; VI-NEXT: v_readlane_b32 s51, v20, 11 -; VI-NEXT: v_readlane_b32 s50, v20, 10 -; VI-NEXT: v_readlane_b32 s49, v20, 9 -; VI-NEXT: v_readlane_b32 s48, v20, 8 -; VI-NEXT: v_readlane_b32 s39, v20, 7 -; VI-NEXT: v_readlane_b32 s38, v20, 6 -; VI-NEXT: v_readlane_b32 s37, v20, 5 -; VI-NEXT: v_readlane_b32 s36, v20, 4 -; VI-NEXT: v_readlane_b32 s35, v20, 3 -; VI-NEXT: v_readlane_b32 s34, v20, 2 -; VI-NEXT: v_readlane_b32 s31, v20, 1 -; VI-NEXT: v_readlane_b32 s30, v20, 0 +; VI-NEXT: v_readlane_b32 s31, v20, 31 +; VI-NEXT: v_readlane_b32 s87, v20, 29 +; VI-NEXT: v_readlane_b32 s86, v20, 28 +; VI-NEXT: v_readlane_b32 s85, v20, 27 +; VI-NEXT: v_readlane_b32 s84, v20, 26 +; VI-NEXT: v_readlane_b32 s83, v20, 25 +; VI-NEXT: v_readlane_b32 s82, v20, 24 +; VI-NEXT: v_readlane_b32 s81, v20, 23 +; VI-NEXT: v_readlane_b32 s80, v20, 22 +; VI-NEXT: v_readlane_b32 s71, v20, 21 +; VI-NEXT: v_readlane_b32 s70, v20, 20 +; VI-NEXT: v_readlane_b32 s69, v20, 19 +; VI-NEXT: v_readlane_b32 s68, v20, 18 +; VI-NEXT: v_readlane_b32 s67, v20, 17 +; VI-NEXT: v_readlane_b32 s66, v20, 16 +; VI-NEXT: v_readlane_b32 s65, v20, 15 +; VI-NEXT: v_readlane_b32 s64, v20, 14 +; VI-NEXT: v_readlane_b32 s55, v20, 13 +; VI-NEXT: v_readlane_b32 s54, v20, 12 +; VI-NEXT: v_readlane_b32 s53, v20, 11 +; VI-NEXT: v_readlane_b32 s52, v20, 10 +; VI-NEXT: v_readlane_b32 s51, v20, 9 +; VI-NEXT: v_readlane_b32 s50, v20, 8 +; VI-NEXT: v_readlane_b32 s49, v20, 7 +; VI-NEXT: v_readlane_b32 s48, v20, 6 +; VI-NEXT: v_readlane_b32 s39, v20, 5 +; VI-NEXT: v_readlane_b32 s38, v20, 4 +; VI-NEXT: v_readlane_b32 s37, v20, 3 +; VI-NEXT: v_readlane_b32 s36, v20, 2 +; VI-NEXT: v_readlane_b32 s35, v20, 1 +; VI-NEXT: v_readlane_b32 s34, v20, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -217764,43 +220024,57 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v63, s30, 0 -; GFX9-NEXT: v_writelane_b32 v63, s31, 1 -; GFX9-NEXT: v_writelane_b32 v63, s34, 2 -; GFX9-NEXT: v_writelane_b32 v63, s35, 3 -; GFX9-NEXT: v_writelane_b32 v63, s36, 4 -; GFX9-NEXT: v_writelane_b32 v63, s37, 5 -; GFX9-NEXT: v_writelane_b32 v63, s38, 6 -; GFX9-NEXT: v_writelane_b32 v63, s39, 7 -; GFX9-NEXT: v_writelane_b32 v63, s48, 8 -; GFX9-NEXT: v_writelane_b32 v63, s49, 9 -; GFX9-NEXT: v_writelane_b32 v63, s50, 10 -; GFX9-NEXT: v_writelane_b32 v63, s51, 11 -; GFX9-NEXT: v_writelane_b32 v63, s52, 12 -; GFX9-NEXT: v_writelane_b32 v63, s53, 13 -; GFX9-NEXT: v_writelane_b32 v63, s54, 14 -; GFX9-NEXT: v_writelane_b32 v63, s55, 15 -; GFX9-NEXT: v_writelane_b32 v63, s64, 16 -; GFX9-NEXT: v_writelane_b32 v63, s65, 17 -; GFX9-NEXT: v_writelane_b32 v63, s66, 18 -; GFX9-NEXT: v_writelane_b32 v63, s67, 19 -; GFX9-NEXT: v_writelane_b32 v63, s68, 20 -; GFX9-NEXT: v_writelane_b32 v63, s69, 21 -; GFX9-NEXT: v_writelane_b32 v63, s70, 22 -; GFX9-NEXT: v_writelane_b32 v63, s71, 23 -; GFX9-NEXT: v_writelane_b32 v63, s80, 24 -; GFX9-NEXT: v_writelane_b32 v63, s81, 25 -; GFX9-NEXT: v_writelane_b32 v63, s82, 26 -; GFX9-NEXT: v_writelane_b32 v63, s83, 27 -; GFX9-NEXT: v_writelane_b32 v63, s84, 28 -; GFX9-NEXT: v_writelane_b32 v63, s85, 29 -; GFX9-NEXT: v_writelane_b32 v63, s86, 30 -; GFX9-NEXT: v_writelane_b32 v63, s87, 31 -; GFX9-NEXT: v_writelane_b32 v63, s96, 32 -; GFX9-NEXT: v_writelane_b32 v63, s97, 33 -; GFX9-NEXT: v_writelane_b32 v63, s98, 34 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v63, s34, 0 +; GFX9-NEXT: v_writelane_b32 v63, s35, 1 +; GFX9-NEXT: v_writelane_b32 v63, s36, 2 +; GFX9-NEXT: v_writelane_b32 v63, s37, 3 +; GFX9-NEXT: v_writelane_b32 v63, s38, 4 +; GFX9-NEXT: v_writelane_b32 v63, s39, 5 +; GFX9-NEXT: v_writelane_b32 v63, s48, 6 +; GFX9-NEXT: v_writelane_b32 v63, s49, 7 +; GFX9-NEXT: v_writelane_b32 v63, s50, 8 +; GFX9-NEXT: v_writelane_b32 v63, s51, 9 +; GFX9-NEXT: v_writelane_b32 v63, s52, 10 +; GFX9-NEXT: v_writelane_b32 v63, s53, 11 +; GFX9-NEXT: v_writelane_b32 v63, s54, 12 +; GFX9-NEXT: v_writelane_b32 v63, s55, 13 +; GFX9-NEXT: v_writelane_b32 v63, s64, 14 +; GFX9-NEXT: v_writelane_b32 v63, s65, 15 +; GFX9-NEXT: v_writelane_b32 v63, s66, 16 +; GFX9-NEXT: v_writelane_b32 v63, s67, 17 +; GFX9-NEXT: v_writelane_b32 v63, s68, 18 +; GFX9-NEXT: v_writelane_b32 v63, s69, 19 +; GFX9-NEXT: v_writelane_b32 v63, s70, 20 +; GFX9-NEXT: v_writelane_b32 v63, s71, 21 +; GFX9-NEXT: v_writelane_b32 v63, s80, 22 +; GFX9-NEXT: v_writelane_b32 v63, s81, 23 +; GFX9-NEXT: v_writelane_b32 v63, s82, 24 +; GFX9-NEXT: v_writelane_b32 v63, s83, 25 +; GFX9-NEXT: v_writelane_b32 v63, s84, 26 +; GFX9-NEXT: v_writelane_b32 v63, s85, 27 +; GFX9-NEXT: v_writelane_b32 v63, s86, 28 +; GFX9-NEXT: v_writelane_b32 v63, s87, 29 +; GFX9-NEXT: v_writelane_b32 v63, s96, 30 +; GFX9-NEXT: v_writelane_b32 v63, s97, 31 +; GFX9-NEXT: v_writelane_b32 v63, s98, 32 +; GFX9-NEXT: v_writelane_b32 v63, s99, 33 +; GFX9-NEXT: v_writelane_b32 v63, s30, 34 +; GFX9-NEXT: v_writelane_b32 v63, s31, 35 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; GFX9-NEXT: v_writelane_b32 v63, s99, 35 ; GFX9-NEXT: v_readfirstlane_b32 s44, v3 ; GFX9-NEXT: v_readfirstlane_b32 s45, v4 ; GFX9-NEXT: v_readfirstlane_b32 s42, v5 @@ -217820,20 +220094,6 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 ; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v2 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB99_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false @@ -218682,42 +220942,42 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: v_or_b32_sdwa v25, v25, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_lshlrev_b32_e32 v30, 8, v44 ; GFX9-NEXT: v_or_b32_sdwa v26, v26, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_readlane_b32 s99, v63, 35 -; GFX9-NEXT: v_readlane_b32 s98, v63, 34 -; GFX9-NEXT: v_readlane_b32 s97, v63, 33 -; GFX9-NEXT: v_readlane_b32 s96, v63, 32 -; GFX9-NEXT: v_readlane_b32 s87, v63, 31 -; GFX9-NEXT: v_readlane_b32 s86, v63, 30 -; GFX9-NEXT: v_readlane_b32 s85, v63, 29 -; GFX9-NEXT: v_readlane_b32 s84, v63, 28 -; GFX9-NEXT: v_readlane_b32 s83, v63, 27 -; GFX9-NEXT: v_readlane_b32 s82, v63, 26 -; GFX9-NEXT: v_readlane_b32 s81, v63, 25 -; GFX9-NEXT: v_readlane_b32 s80, v63, 24 -; GFX9-NEXT: v_readlane_b32 s71, v63, 23 -; GFX9-NEXT: v_readlane_b32 s70, v63, 22 -; GFX9-NEXT: v_readlane_b32 s69, v63, 21 -; GFX9-NEXT: v_readlane_b32 s68, v63, 20 -; GFX9-NEXT: v_readlane_b32 s67, v63, 19 -; GFX9-NEXT: v_readlane_b32 s66, v63, 18 -; GFX9-NEXT: v_readlane_b32 s65, v63, 17 -; GFX9-NEXT: v_readlane_b32 s64, v63, 16 -; GFX9-NEXT: v_readlane_b32 s55, v63, 15 -; GFX9-NEXT: v_readlane_b32 s54, v63, 14 -; GFX9-NEXT: v_readlane_b32 s53, v63, 13 -; GFX9-NEXT: v_readlane_b32 s52, v63, 12 -; GFX9-NEXT: v_readlane_b32 s51, v63, 11 -; GFX9-NEXT: v_readlane_b32 s50, v63, 10 -; GFX9-NEXT: v_readlane_b32 s49, v63, 9 -; GFX9-NEXT: v_readlane_b32 s48, v63, 8 -; GFX9-NEXT: v_readlane_b32 s39, v63, 7 -; GFX9-NEXT: v_readlane_b32 s38, v63, 6 -; GFX9-NEXT: v_readlane_b32 s37, v63, 5 -; GFX9-NEXT: v_readlane_b32 s36, v63, 4 -; GFX9-NEXT: v_readlane_b32 s35, v63, 3 -; GFX9-NEXT: v_readlane_b32 s34, v63, 2 -; GFX9-NEXT: v_readlane_b32 s31, v63, 1 -; GFX9-NEXT: v_readlane_b32 s30, v63, 0 +; GFX9-NEXT: v_readlane_b32 s30, v63, 34 +; GFX9-NEXT: v_readlane_b32 s31, v63, 35 +; GFX9-NEXT: v_readlane_b32 s99, v63, 33 +; GFX9-NEXT: v_readlane_b32 s98, v63, 32 +; GFX9-NEXT: v_readlane_b32 s97, v63, 31 +; GFX9-NEXT: v_readlane_b32 s96, v63, 30 +; GFX9-NEXT: v_readlane_b32 s87, v63, 29 +; GFX9-NEXT: v_readlane_b32 s86, v63, 28 +; GFX9-NEXT: v_readlane_b32 s85, v63, 27 +; GFX9-NEXT: v_readlane_b32 s84, v63, 26 +; GFX9-NEXT: v_readlane_b32 s83, v63, 25 +; GFX9-NEXT: v_readlane_b32 s82, v63, 24 +; GFX9-NEXT: v_readlane_b32 s81, v63, 23 +; GFX9-NEXT: v_readlane_b32 s80, v63, 22 +; GFX9-NEXT: v_readlane_b32 s71, v63, 21 +; GFX9-NEXT: v_readlane_b32 s70, v63, 20 +; GFX9-NEXT: v_readlane_b32 s69, v63, 19 +; GFX9-NEXT: v_readlane_b32 s68, v63, 18 +; GFX9-NEXT: v_readlane_b32 s67, v63, 17 +; GFX9-NEXT: v_readlane_b32 s66, v63, 16 +; GFX9-NEXT: v_readlane_b32 s65, v63, 15 +; GFX9-NEXT: v_readlane_b32 s64, v63, 14 +; GFX9-NEXT: v_readlane_b32 s55, v63, 13 +; GFX9-NEXT: v_readlane_b32 s54, v63, 12 +; GFX9-NEXT: v_readlane_b32 s53, v63, 11 +; GFX9-NEXT: v_readlane_b32 s52, v63, 10 +; GFX9-NEXT: v_readlane_b32 s51, v63, 9 +; GFX9-NEXT: v_readlane_b32 s50, v63, 8 +; GFX9-NEXT: v_readlane_b32 s49, v63, 7 +; GFX9-NEXT: v_readlane_b32 s48, v63, 6 +; GFX9-NEXT: v_readlane_b32 s39, v63, 5 +; GFX9-NEXT: v_readlane_b32 s38, v63, 4 +; GFX9-NEXT: v_readlane_b32 s37, v63, 3 +; GFX9-NEXT: v_readlane_b32 s36, v63, 2 +; GFX9-NEXT: v_readlane_b32 s35, v63, 1 +; GFX9-NEXT: v_readlane_b32 s34, v63, 0 ; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v15 ; GFX9-NEXT: v_or_b32_sdwa v15, v38, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -219070,90 +221330,111 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v75, s30, 0 -; GFX11-NEXT: v_writelane_b32 v76, s96, 0 -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_readfirstlane_b32 s40, v1 -; GFX11-NEXT: v_readfirstlane_b32 s41, v2 -; GFX11-NEXT: v_writelane_b32 v75, s31, 1 -; GFX11-NEXT: v_writelane_b32 v76, s97, 1 -; GFX11-NEXT: v_readfirstlane_b32 s14, v3 -; GFX11-NEXT: v_readfirstlane_b32 s15, v4 -; GFX11-NEXT: v_readfirstlane_b32 s12, v5 -; GFX11-NEXT: v_writelane_b32 v75, s34, 2 -; GFX11-NEXT: v_writelane_b32 v76, s98, 2 -; GFX11-NEXT: v_readfirstlane_b32 s13, v6 -; GFX11-NEXT: v_readfirstlane_b32 s10, v7 -; GFX11-NEXT: v_readfirstlane_b32 s11, v8 -; GFX11-NEXT: v_writelane_b32 v75, s35, 3 -; GFX11-NEXT: v_writelane_b32 v76, s99, 3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v9 -; GFX11-NEXT: v_readfirstlane_b32 s9, v10 -; GFX11-NEXT: v_readfirstlane_b32 s6, v11 -; GFX11-NEXT: v_writelane_b32 v75, s36, 4 -; GFX11-NEXT: v_writelane_b32 v76, s100, 4 -; GFX11-NEXT: v_readfirstlane_b32 s7, v12 -; GFX11-NEXT: v_readfirstlane_b32 s4, v13 -; GFX11-NEXT: v_readfirstlane_b32 s5, v14 -; GFX11-NEXT: v_writelane_b32 v75, s37, 5 -; GFX11-NEXT: v_writelane_b32 v76, s101, 5 -; GFX11-NEXT: s_mov_b32 s99, 0 -; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: s_clause 0x12 ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:40 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s32 -; GFX11-NEXT: v_writelane_b32 v75, s38, 6 -; GFX11-NEXT: v_writelane_b32 v76, s102, 6 +; GFX11-NEXT: v_writelane_b32 v75, s34, 0 +; GFX11-NEXT: v_writelane_b32 v75, s35, 1 +; GFX11-NEXT: v_writelane_b32 v75, s36, 2 +; GFX11-NEXT: v_writelane_b32 v75, s37, 3 +; GFX11-NEXT: v_writelane_b32 v75, s38, 4 +; GFX11-NEXT: v_writelane_b32 v75, s39, 5 +; GFX11-NEXT: v_writelane_b32 v75, s48, 6 +; GFX11-NEXT: v_writelane_b32 v75, s49, 7 +; GFX11-NEXT: v_writelane_b32 v75, s50, 8 +; GFX11-NEXT: v_writelane_b32 v75, s51, 9 +; GFX11-NEXT: v_writelane_b32 v75, s52, 10 +; GFX11-NEXT: v_writelane_b32 v75, s53, 11 +; GFX11-NEXT: v_writelane_b32 v75, s54, 12 +; GFX11-NEXT: v_writelane_b32 v75, s55, 13 +; GFX11-NEXT: v_writelane_b32 v75, s64, 14 +; GFX11-NEXT: v_writelane_b32 v75, s65, 15 +; GFX11-NEXT: v_writelane_b32 v75, s66, 16 +; GFX11-NEXT: v_writelane_b32 v75, s67, 17 +; GFX11-NEXT: v_writelane_b32 v75, s68, 18 +; GFX11-NEXT: v_writelane_b32 v75, s69, 19 +; GFX11-NEXT: v_writelane_b32 v75, s70, 20 +; GFX11-NEXT: v_writelane_b32 v75, s71, 21 +; GFX11-NEXT: v_writelane_b32 v75, s80, 22 +; GFX11-NEXT: v_writelane_b32 v75, s81, 23 +; GFX11-NEXT: v_writelane_b32 v75, s82, 24 +; GFX11-NEXT: v_writelane_b32 v75, s83, 25 +; GFX11-NEXT: v_writelane_b32 v75, s84, 26 +; GFX11-NEXT: v_writelane_b32 v75, s85, 27 +; GFX11-NEXT: v_writelane_b32 v75, s86, 28 +; GFX11-NEXT: v_writelane_b32 v75, s87, 29 +; GFX11-NEXT: v_writelane_b32 v75, s96, 30 +; GFX11-NEXT: v_writelane_b32 v75, s97, 31 +; GFX11-NEXT: v_writelane_b32 v76, s98, 0 +; GFX11-NEXT: v_writelane_b32 v76, s99, 1 +; GFX11-NEXT: v_writelane_b32 v76, s100, 2 +; GFX11-NEXT: v_writelane_b32 v76, s101, 3 +; GFX11-NEXT: v_writelane_b32 v76, s102, 4 +; GFX11-NEXT: v_writelane_b32 v76, s103, 5 +; GFX11-NEXT: v_writelane_b32 v76, s104, 6 +; GFX11-NEXT: v_writelane_b32 v76, s30, 7 +; GFX11-NEXT: v_writelane_b32 v76, s31, 8 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 +; GFX11-NEXT: v_readfirstlane_b32 s40, v1 +; GFX11-NEXT: v_readfirstlane_b32 s41, v2 +; GFX11-NEXT: v_readfirstlane_b32 s14, v3 +; GFX11-NEXT: v_readfirstlane_b32 s15, v4 +; GFX11-NEXT: v_readfirstlane_b32 s12, v5 +; GFX11-NEXT: v_readfirstlane_b32 s13, v6 +; GFX11-NEXT: v_readfirstlane_b32 s10, v7 +; GFX11-NEXT: v_readfirstlane_b32 s11, v8 +; GFX11-NEXT: v_readfirstlane_b32 s8, v9 +; GFX11-NEXT: v_readfirstlane_b32 s9, v10 +; GFX11-NEXT: v_readfirstlane_b32 s6, v11 +; GFX11-NEXT: v_readfirstlane_b32 s7, v12 +; GFX11-NEXT: v_readfirstlane_b32 s4, v13 +; GFX11-NEXT: v_readfirstlane_b32 s5, v14 +; GFX11-NEXT: s_mov_b32 s99, 0 +; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane ; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v75, s39, 7 -; GFX11-NEXT: v_writelane_b32 v76, s103, 7 -; GFX11-NEXT: v_writelane_b32 v75, s48, 8 -; GFX11-NEXT: v_writelane_b32 v76, s104, 8 -; GFX11-NEXT: v_writelane_b32 v75, s49, 9 -; GFX11-NEXT: v_writelane_b32 v75, s50, 10 -; GFX11-NEXT: v_writelane_b32 v75, s51, 11 -; GFX11-NEXT: v_writelane_b32 v75, s52, 12 -; GFX11-NEXT: v_writelane_b32 v75, s53, 13 -; GFX11-NEXT: v_writelane_b32 v75, s54, 14 -; GFX11-NEXT: v_writelane_b32 v75, s55, 15 -; GFX11-NEXT: v_writelane_b32 v75, s64, 16 -; GFX11-NEXT: v_writelane_b32 v75, s65, 17 -; GFX11-NEXT: v_writelane_b32 v75, s66, 18 -; GFX11-NEXT: v_writelane_b32 v75, s67, 19 -; GFX11-NEXT: v_writelane_b32 v75, s68, 20 -; GFX11-NEXT: v_writelane_b32 v75, s69, 21 -; GFX11-NEXT: v_writelane_b32 v75, s70, 22 -; GFX11-NEXT: v_writelane_b32 v75, s71, 23 -; GFX11-NEXT: v_writelane_b32 v75, s80, 24 -; GFX11-NEXT: v_writelane_b32 v75, s81, 25 -; GFX11-NEXT: v_writelane_b32 v75, s82, 26 -; GFX11-NEXT: v_writelane_b32 v75, s83, 27 -; GFX11-NEXT: v_writelane_b32 v75, s84, 28 -; GFX11-NEXT: v_writelane_b32 v75, s85, 29 -; GFX11-NEXT: v_writelane_b32 v75, s86, 30 -; GFX11-NEXT: v_writelane_b32 v75, s87, 31 ; GFX11-NEXT: s_cbranch_scc0 .LBB99_3 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s42, s27, 16 @@ -220042,47 +222323,47 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:64 ; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:68 ; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:72 -; GFX11-NEXT: v_readlane_b32 s104, v76, 8 -; GFX11-NEXT: v_readlane_b32 s103, v76, 7 -; GFX11-NEXT: v_readlane_b32 s102, v76, 6 -; GFX11-NEXT: v_readlane_b32 s101, v76, 5 -; GFX11-NEXT: v_readlane_b32 s100, v76, 4 -; GFX11-NEXT: v_readlane_b32 s99, v76, 3 -; GFX11-NEXT: v_readlane_b32 s98, v76, 2 -; GFX11-NEXT: v_readlane_b32 s97, v76, 1 -; GFX11-NEXT: v_readlane_b32 s96, v76, 0 -; GFX11-NEXT: v_readlane_b32 s87, v75, 31 -; GFX11-NEXT: v_readlane_b32 s86, v75, 30 -; GFX11-NEXT: v_readlane_b32 s85, v75, 29 -; GFX11-NEXT: v_readlane_b32 s84, v75, 28 -; GFX11-NEXT: v_readlane_b32 s83, v75, 27 -; GFX11-NEXT: v_readlane_b32 s82, v75, 26 -; GFX11-NEXT: v_readlane_b32 s81, v75, 25 -; GFX11-NEXT: v_readlane_b32 s80, v75, 24 -; GFX11-NEXT: v_readlane_b32 s71, v75, 23 -; GFX11-NEXT: v_readlane_b32 s70, v75, 22 -; GFX11-NEXT: v_readlane_b32 s69, v75, 21 -; GFX11-NEXT: v_readlane_b32 s68, v75, 20 -; GFX11-NEXT: v_readlane_b32 s67, v75, 19 -; GFX11-NEXT: v_readlane_b32 s66, v75, 18 -; GFX11-NEXT: v_readlane_b32 s65, v75, 17 -; GFX11-NEXT: v_readlane_b32 s64, v75, 16 -; GFX11-NEXT: v_readlane_b32 s55, v75, 15 -; GFX11-NEXT: v_readlane_b32 s54, v75, 14 -; GFX11-NEXT: v_readlane_b32 s53, v75, 13 -; GFX11-NEXT: v_readlane_b32 s52, v75, 12 -; GFX11-NEXT: v_readlane_b32 s51, v75, 11 -; GFX11-NEXT: v_readlane_b32 s50, v75, 10 -; GFX11-NEXT: v_readlane_b32 s49, v75, 9 -; GFX11-NEXT: v_readlane_b32 s48, v75, 8 -; GFX11-NEXT: v_readlane_b32 s39, v75, 7 -; GFX11-NEXT: v_readlane_b32 s38, v75, 6 -; GFX11-NEXT: v_readlane_b32 s37, v75, 5 -; GFX11-NEXT: v_readlane_b32 s36, v75, 4 -; GFX11-NEXT: v_readlane_b32 s35, v75, 3 -; GFX11-NEXT: v_readlane_b32 s34, v75, 2 -; GFX11-NEXT: v_readlane_b32 s31, v75, 1 -; GFX11-NEXT: v_readlane_b32 s30, v75, 0 +; GFX11-NEXT: v_readlane_b32 s30, v76, 7 +; GFX11-NEXT: v_readlane_b32 s31, v76, 8 +; GFX11-NEXT: v_readlane_b32 s104, v76, 6 +; GFX11-NEXT: v_readlane_b32 s103, v76, 5 +; GFX11-NEXT: v_readlane_b32 s102, v76, 4 +; GFX11-NEXT: v_readlane_b32 s101, v76, 3 +; GFX11-NEXT: v_readlane_b32 s100, v76, 2 +; GFX11-NEXT: v_readlane_b32 s99, v76, 1 +; GFX11-NEXT: v_readlane_b32 s98, v76, 0 +; GFX11-NEXT: v_readlane_b32 s97, v75, 31 +; GFX11-NEXT: v_readlane_b32 s96, v75, 30 +; GFX11-NEXT: v_readlane_b32 s87, v75, 29 +; GFX11-NEXT: v_readlane_b32 s86, v75, 28 +; GFX11-NEXT: v_readlane_b32 s85, v75, 27 +; GFX11-NEXT: v_readlane_b32 s84, v75, 26 +; GFX11-NEXT: v_readlane_b32 s83, v75, 25 +; GFX11-NEXT: v_readlane_b32 s82, v75, 24 +; GFX11-NEXT: v_readlane_b32 s81, v75, 23 +; GFX11-NEXT: v_readlane_b32 s80, v75, 22 +; GFX11-NEXT: v_readlane_b32 s71, v75, 21 +; GFX11-NEXT: v_readlane_b32 s70, v75, 20 +; GFX11-NEXT: v_readlane_b32 s69, v75, 19 +; GFX11-NEXT: v_readlane_b32 s68, v75, 18 +; GFX11-NEXT: v_readlane_b32 s67, v75, 17 +; GFX11-NEXT: v_readlane_b32 s66, v75, 16 +; GFX11-NEXT: v_readlane_b32 s65, v75, 15 +; GFX11-NEXT: v_readlane_b32 s64, v75, 14 +; GFX11-NEXT: v_readlane_b32 s55, v75, 13 +; GFX11-NEXT: v_readlane_b32 s54, v75, 12 +; GFX11-NEXT: v_readlane_b32 s53, v75, 11 +; GFX11-NEXT: v_readlane_b32 s52, v75, 10 +; GFX11-NEXT: v_readlane_b32 s51, v75, 9 +; GFX11-NEXT: v_readlane_b32 s50, v75, 8 +; GFX11-NEXT: v_readlane_b32 s49, v75, 7 +; GFX11-NEXT: v_readlane_b32 s48, v75, 6 +; GFX11-NEXT: v_readlane_b32 s39, v75, 5 +; GFX11-NEXT: v_readlane_b32 s38, v75, 4 +; GFX11-NEXT: v_readlane_b32 s37, v75, 3 +; GFX11-NEXT: v_readlane_b32 s36, v75, 2 +; GFX11-NEXT: v_readlane_b32 s35, v75, 1 +; GFX11-NEXT: v_readlane_b32 s34, v75, 0 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:76 @@ -222643,20 +224924,35 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v48, v16 ; GFX11-TRUE16-NEXT: s_clause 0x1 @@ -224991,9 +227287,11 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg % ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_writelane_b32 v42, s30, 0 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; VI-NEXT: v_writelane_b32 v42, s31, 1 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; VI-NEXT: v_mov_b32_e32 v31, v17 ; VI-NEXT: v_mov_b32_e32 v30, v16 ; VI-NEXT: v_mov_b32_e32 v29, v15 @@ -225013,8 +227311,6 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg % ; VI-NEXT: v_readfirstlane_b32 s30, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s31, v1 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB101_3 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB101_4 @@ -225619,9 +227915,9 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg % ; VI-NEXT: .LBB101_5: ; %end ; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: v_readlane_b32 s30, v42, 0 ; VI-NEXT: v_mov_b32_e32 v18, v32 ; VI-NEXT: v_readlane_b32 s31, v42, 1 -; VI-NEXT: v_readlane_b32 s30, v42, 0 ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -225634,9 +227930,12 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg % ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_writelane_b32 v43, s30, 0 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; GFX9-NEXT: v_writelane_b32 v43, s31, 1 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; GFX9-NEXT: v_mov_b32_e32 v31, v17 ; GFX9-NEXT: v_mov_b32_e32 v30, v16 ; GFX9-NEXT: v_mov_b32_e32 v29, v15 @@ -225656,9 +227955,6 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg % ; GFX9-NEXT: v_readfirstlane_b32 s30, v0 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s31, v1 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB101_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_cbranch_execnz .LBB101_4 @@ -226297,9 +228593,9 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg % ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX9-NEXT: v_readlane_b32 s30, v43, 0 ; GFX9-NEXT: v_mov_b32_e32 v18, v32 ; GFX9-NEXT: v_readlane_b32 s31, v43, 1 -; GFX9-NEXT: v_readlane_b32 s30, v43, 0 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -235210,9 +237506,11 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_writelane_b32 v42, s30, 0 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; VI-NEXT: v_writelane_b32 v42, s31, 1 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; VI-NEXT: v_mov_b32_e32 v31, v17 ; VI-NEXT: v_mov_b32_e32 v30, v16 ; VI-NEXT: v_mov_b32_e32 v29, v15 @@ -235232,8 +237530,6 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; VI-NEXT: v_readfirstlane_b32 s30, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s31, v1 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB105_3 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB105_4 @@ -235838,9 +238134,9 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; VI-NEXT: .LBB105_5: ; %end ; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: v_readlane_b32 s30, v42, 0 ; VI-NEXT: v_mov_b32_e32 v18, v32 ; VI-NEXT: v_readlane_b32 s31, v42, 1 -; VI-NEXT: v_readlane_b32 s30, v42, 0 ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -235853,9 +238149,12 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_writelane_b32 v43, s30, 0 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; GFX9-NEXT: v_writelane_b32 v43, s31, 1 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; GFX9-NEXT: v_mov_b32_e32 v31, v17 ; GFX9-NEXT: v_mov_b32_e32 v30, v16 ; GFX9-NEXT: v_mov_b32_e32 v29, v15 @@ -235875,9 +238174,6 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; GFX9-NEXT: v_readfirstlane_b32 s30, v0 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s31, v1 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB105_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_cbranch_execnz .LBB105_4 @@ -236484,9 +238780,9 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX9-NEXT: v_readlane_b32 s30, v43, 0 ; GFX9-NEXT: v_mov_b32_e32 v18, v32 ; GFX9-NEXT: v_readlane_b32 s31, v43, 1 -; GFX9-NEXT: v_readlane_b32 s30, v43, 0 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -238840,6 +241136,43 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_writelane_b32 v40, s34, 0 +; SI-NEXT: v_writelane_b32 v40, s35, 1 +; SI-NEXT: v_writelane_b32 v40, s36, 2 +; SI-NEXT: v_writelane_b32 v40, s37, 3 +; SI-NEXT: v_writelane_b32 v40, s38, 4 +; SI-NEXT: v_writelane_b32 v40, s39, 5 +; SI-NEXT: v_writelane_b32 v40, s48, 6 +; SI-NEXT: v_writelane_b32 v40, s49, 7 +; SI-NEXT: v_writelane_b32 v40, s50, 8 +; SI-NEXT: v_writelane_b32 v40, s51, 9 +; SI-NEXT: v_writelane_b32 v40, s52, 10 +; SI-NEXT: v_writelane_b32 v40, s53, 11 +; SI-NEXT: v_writelane_b32 v40, s54, 12 +; SI-NEXT: v_writelane_b32 v40, s55, 13 +; SI-NEXT: v_writelane_b32 v40, s64, 14 +; SI-NEXT: v_writelane_b32 v40, s65, 15 +; SI-NEXT: v_writelane_b32 v40, s66, 16 +; SI-NEXT: v_writelane_b32 v40, s67, 17 +; SI-NEXT: v_writelane_b32 v40, s68, 18 +; SI-NEXT: v_writelane_b32 v40, s69, 19 +; SI-NEXT: v_writelane_b32 v40, s70, 20 +; SI-NEXT: v_writelane_b32 v40, s71, 21 +; SI-NEXT: v_writelane_b32 v40, s80, 22 +; SI-NEXT: v_writelane_b32 v40, s81, 23 +; SI-NEXT: v_writelane_b32 v40, s82, 24 +; SI-NEXT: v_writelane_b32 v40, s83, 25 +; SI-NEXT: v_writelane_b32 v40, s84, 26 +; SI-NEXT: v_writelane_b32 v40, s85, 27 +; SI-NEXT: v_writelane_b32 v40, s86, 28 +; SI-NEXT: v_writelane_b32 v40, s87, 29 +; SI-NEXT: v_writelane_b32 v40, s96, 30 +; SI-NEXT: v_writelane_b32 v40, s97, 31 +; SI-NEXT: v_writelane_b32 v40, s98, 32 +; SI-NEXT: v_writelane_b32 v40, s99, 33 +; SI-NEXT: v_writelane_b32 v40, s30, 34 +; SI-NEXT: v_writelane_b32 v40, s31, 35 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68 @@ -238848,39 +241181,6 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52 ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_writelane_b32 v40, s30, 0 -; SI-NEXT: v_writelane_b32 v40, s31, 1 -; SI-NEXT: v_writelane_b32 v40, s34, 2 -; SI-NEXT: v_writelane_b32 v40, s35, 3 -; SI-NEXT: v_writelane_b32 v40, s36, 4 -; SI-NEXT: v_writelane_b32 v40, s37, 5 -; SI-NEXT: v_writelane_b32 v40, s38, 6 -; SI-NEXT: v_writelane_b32 v40, s39, 7 -; SI-NEXT: v_writelane_b32 v40, s48, 8 -; SI-NEXT: v_writelane_b32 v40, s49, 9 -; SI-NEXT: v_writelane_b32 v40, s50, 10 -; SI-NEXT: v_writelane_b32 v40, s51, 11 -; SI-NEXT: v_writelane_b32 v40, s52, 12 -; SI-NEXT: v_writelane_b32 v40, s53, 13 -; SI-NEXT: v_writelane_b32 v40, s54, 14 -; SI-NEXT: v_writelane_b32 v40, s55, 15 -; SI-NEXT: v_writelane_b32 v40, s64, 16 -; SI-NEXT: v_writelane_b32 v40, s65, 17 -; SI-NEXT: v_writelane_b32 v40, s66, 18 -; SI-NEXT: v_writelane_b32 v40, s67, 19 -; SI-NEXT: v_writelane_b32 v40, s68, 20 -; SI-NEXT: v_writelane_b32 v40, s69, 21 -; SI-NEXT: v_writelane_b32 v40, s70, 22 -; SI-NEXT: v_writelane_b32 v40, s71, 23 -; SI-NEXT: v_writelane_b32 v40, s80, 24 -; SI-NEXT: v_writelane_b32 v40, s81, 25 -; SI-NEXT: v_writelane_b32 v40, s82, 26 -; SI-NEXT: v_writelane_b32 v40, s83, 27 -; SI-NEXT: v_writelane_b32 v40, s84, 28 -; SI-NEXT: v_writelane_b32 v40, s85, 29 -; SI-NEXT: v_writelane_b32 v40, s86, 30 -; SI-NEXT: v_writelane_b32 v40, s87, 31 ; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane ; SI-NEXT: s_mov_b32 s60, s16 ; SI-NEXT: s_waitcnt expcnt(0) @@ -238920,9 +241220,32 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: v_writelane_b32 v41, s34, 19 ; SI-NEXT: v_readfirstlane_b32 s36, v10 ; SI-NEXT: v_writelane_b32 v41, s35, 20 -; SI-NEXT: v_writelane_b32 v40, s96, 32 ; SI-NEXT: v_readfirstlane_b32 s37, v9 ; SI-NEXT: v_writelane_b32 v41, s36, 21 +; SI-NEXT: v_readfirstlane_b32 s38, v12 +; SI-NEXT: v_writelane_b32 v41, s37, 22 +; SI-NEXT: v_readfirstlane_b32 s14, v30 +; SI-NEXT: v_readfirstlane_b32 s15, v29 +; SI-NEXT: v_readfirstlane_b32 s12, v28 +; SI-NEXT: v_readfirstlane_b32 s13, v27 +; SI-NEXT: v_readfirstlane_b32 s10, v26 +; SI-NEXT: v_readfirstlane_b32 s11, v25 +; SI-NEXT: v_readfirstlane_b32 s8, v24 +; SI-NEXT: v_readfirstlane_b32 s9, v23 +; SI-NEXT: v_readfirstlane_b32 s88, v22 +; SI-NEXT: v_readfirstlane_b32 s29, v21 +; SI-NEXT: v_readfirstlane_b32 s79, v20 +; SI-NEXT: v_readfirstlane_b32 s27, v19 +; SI-NEXT: v_readfirstlane_b32 s78, v18 +; SI-NEXT: v_readfirstlane_b32 s25, v17 +; SI-NEXT: v_readfirstlane_b32 s77, v16 +; SI-NEXT: v_readfirstlane_b32 s23, v15 +; SI-NEXT: v_readfirstlane_b32 s39, v14 +; SI-NEXT: v_readfirstlane_b32 s21, v13 +; SI-NEXT: v_readfirstlane_b32 s19, v11 +; SI-NEXT: v_readfirstlane_b32 s18, v1 +; SI-NEXT: v_writelane_b32 v41, s38, 23 +; SI-NEXT: v_writelane_b32 v41, s39, 24 ; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_readfirstlane_b32 s62, v31 ; SI-NEXT: s_waitcnt vmcnt(6) @@ -238951,33 +241274,6 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:8 ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:4 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 -; SI-NEXT: v_writelane_b32 v40, s97, 33 -; SI-NEXT: v_readfirstlane_b32 s38, v12 -; SI-NEXT: v_writelane_b32 v41, s37, 22 -; SI-NEXT: v_writelane_b32 v40, s98, 34 -; SI-NEXT: v_readfirstlane_b32 s14, v30 -; SI-NEXT: v_readfirstlane_b32 s15, v29 -; SI-NEXT: v_readfirstlane_b32 s12, v28 -; SI-NEXT: v_readfirstlane_b32 s13, v27 -; SI-NEXT: v_readfirstlane_b32 s10, v26 -; SI-NEXT: v_readfirstlane_b32 s11, v25 -; SI-NEXT: v_readfirstlane_b32 s8, v24 -; SI-NEXT: v_readfirstlane_b32 s9, v23 -; SI-NEXT: v_readfirstlane_b32 s88, v22 -; SI-NEXT: v_readfirstlane_b32 s29, v21 -; SI-NEXT: v_readfirstlane_b32 s79, v20 -; SI-NEXT: v_readfirstlane_b32 s27, v19 -; SI-NEXT: v_readfirstlane_b32 s78, v18 -; SI-NEXT: v_readfirstlane_b32 s25, v17 -; SI-NEXT: v_readfirstlane_b32 s77, v16 -; SI-NEXT: v_readfirstlane_b32 s23, v15 -; SI-NEXT: v_readfirstlane_b32 s39, v14 -; SI-NEXT: v_readfirstlane_b32 s21, v13 -; SI-NEXT: v_readfirstlane_b32 s19, v11 -; SI-NEXT: v_readfirstlane_b32 s18, v1 -; SI-NEXT: v_writelane_b32 v41, s38, 23 -; SI-NEXT: v_writelane_b32 v40, s99, 35 -; SI-NEXT: v_writelane_b32 v41, s39, 24 ; SI-NEXT: s_waitcnt vmcnt(12) ; SI-NEXT: v_readfirstlane_b32 s58, v31 ; SI-NEXT: s_waitcnt vmcnt(11) @@ -239672,43 +241968,43 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: v_mul_f32_e64 v2, 1.0, s5 ; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 +; SI-NEXT: v_readlane_b32 s30, v40, 34 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v40, 35 -; SI-NEXT: v_readlane_b32 s98, v40, 34 -; SI-NEXT: v_readlane_b32 s97, v40, 33 -; SI-NEXT: v_readlane_b32 s96, v40, 32 -; SI-NEXT: v_readlane_b32 s87, v40, 31 -; SI-NEXT: v_readlane_b32 s86, v40, 30 -; SI-NEXT: v_readlane_b32 s85, v40, 29 -; SI-NEXT: v_readlane_b32 s84, v40, 28 -; SI-NEXT: v_readlane_b32 s83, v40, 27 -; SI-NEXT: v_readlane_b32 s82, v40, 26 -; SI-NEXT: v_readlane_b32 s81, v40, 25 -; SI-NEXT: v_readlane_b32 s80, v40, 24 -; SI-NEXT: v_readlane_b32 s71, v40, 23 -; SI-NEXT: v_readlane_b32 s70, v40, 22 -; SI-NEXT: v_readlane_b32 s69, v40, 21 -; SI-NEXT: v_readlane_b32 s68, v40, 20 -; SI-NEXT: v_readlane_b32 s67, v40, 19 -; SI-NEXT: v_readlane_b32 s66, v40, 18 -; SI-NEXT: v_readlane_b32 s65, v40, 17 -; SI-NEXT: v_readlane_b32 s64, v40, 16 -; SI-NEXT: v_readlane_b32 s55, v40, 15 -; SI-NEXT: v_readlane_b32 s54, v40, 14 -; SI-NEXT: v_readlane_b32 s53, v40, 13 -; SI-NEXT: v_readlane_b32 s52, v40, 12 -; SI-NEXT: v_readlane_b32 s51, v40, 11 -; SI-NEXT: v_readlane_b32 s50, v40, 10 -; SI-NEXT: v_readlane_b32 s49, v40, 9 -; SI-NEXT: v_readlane_b32 s48, v40, 8 -; SI-NEXT: v_readlane_b32 s39, v40, 7 -; SI-NEXT: v_readlane_b32 s38, v40, 6 -; SI-NEXT: v_readlane_b32 s37, v40, 5 -; SI-NEXT: v_readlane_b32 s36, v40, 4 -; SI-NEXT: v_readlane_b32 s35, v40, 3 -; SI-NEXT: v_readlane_b32 s34, v40, 2 -; SI-NEXT: v_readlane_b32 s31, v40, 1 -; SI-NEXT: v_readlane_b32 s30, v40, 0 +; SI-NEXT: v_readlane_b32 s31, v40, 35 +; SI-NEXT: v_readlane_b32 s99, v40, 33 +; SI-NEXT: v_readlane_b32 s98, v40, 32 +; SI-NEXT: v_readlane_b32 s97, v40, 31 +; SI-NEXT: v_readlane_b32 s96, v40, 30 +; SI-NEXT: v_readlane_b32 s87, v40, 29 +; SI-NEXT: v_readlane_b32 s86, v40, 28 +; SI-NEXT: v_readlane_b32 s85, v40, 27 +; SI-NEXT: v_readlane_b32 s84, v40, 26 +; SI-NEXT: v_readlane_b32 s83, v40, 25 +; SI-NEXT: v_readlane_b32 s82, v40, 24 +; SI-NEXT: v_readlane_b32 s81, v40, 23 +; SI-NEXT: v_readlane_b32 s80, v40, 22 +; SI-NEXT: v_readlane_b32 s71, v40, 21 +; SI-NEXT: v_readlane_b32 s70, v40, 20 +; SI-NEXT: v_readlane_b32 s69, v40, 19 +; SI-NEXT: v_readlane_b32 s68, v40, 18 +; SI-NEXT: v_readlane_b32 s67, v40, 17 +; SI-NEXT: v_readlane_b32 s66, v40, 16 +; SI-NEXT: v_readlane_b32 s65, v40, 15 +; SI-NEXT: v_readlane_b32 s64, v40, 14 +; SI-NEXT: v_readlane_b32 s55, v40, 13 +; SI-NEXT: v_readlane_b32 s54, v40, 12 +; SI-NEXT: v_readlane_b32 s53, v40, 11 +; SI-NEXT: v_readlane_b32 s52, v40, 10 +; SI-NEXT: v_readlane_b32 s51, v40, 9 +; SI-NEXT: v_readlane_b32 s50, v40, 8 +; SI-NEXT: v_readlane_b32 s49, v40, 7 +; SI-NEXT: v_readlane_b32 s48, v40, 6 +; SI-NEXT: v_readlane_b32 s39, v40, 5 +; SI-NEXT: v_readlane_b32 s38, v40, 4 +; SI-NEXT: v_readlane_b32 s37, v40, 3 +; SI-NEXT: v_readlane_b32 s36, v40, 2 +; SI-NEXT: v_readlane_b32 s35, v40, 1 +; SI-NEXT: v_readlane_b32 s34, v40, 0 ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload @@ -239722,14 +242018,15 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v32, s30, 0 -; VI-NEXT: v_writelane_b32 v32, s31, 1 -; VI-NEXT: v_writelane_b32 v32, s34, 2 -; VI-NEXT: v_writelane_b32 v32, s35, 3 -; VI-NEXT: v_writelane_b32 v32, s36, 4 -; VI-NEXT: v_writelane_b32 v32, s37, 5 +; VI-NEXT: v_writelane_b32 v32, s34, 0 +; VI-NEXT: v_writelane_b32 v32, s35, 1 +; VI-NEXT: v_writelane_b32 v32, s36, 2 +; VI-NEXT: v_writelane_b32 v32, s37, 3 +; VI-NEXT: v_writelane_b32 v32, s38, 4 +; VI-NEXT: v_writelane_b32 v32, s39, 5 +; VI-NEXT: v_writelane_b32 v32, s30, 6 +; VI-NEXT: v_writelane_b32 v32, s31, 7 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 -; VI-NEXT: v_writelane_b32 v32, s38, 6 ; VI-NEXT: v_readfirstlane_b32 s47, v2 ; VI-NEXT: v_readfirstlane_b32 s46, v3 ; VI-NEXT: v_readfirstlane_b32 s45, v4 @@ -239749,7 +242046,6 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; VI-NEXT: v_readfirstlane_b32 s6, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s7, v1 -; VI-NEXT: v_writelane_b32 v32, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB107_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB107_3 @@ -239915,6 +242211,7 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; VI-NEXT: s_add_i32 s46, s46, 0x30000 ; VI-NEXT: s_add_i32 s47, s4, 0x30000 ; VI-NEXT: .LBB107_3: ; %end +; VI-NEXT: v_readlane_b32 s30, v32, 6 ; VI-NEXT: v_mov_b32_e32 v0, s16 ; VI-NEXT: v_mov_b32_e32 v1, s17 ; VI-NEXT: v_mov_b32_e32 v2, s18 @@ -239947,14 +242244,13 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; VI-NEXT: v_mov_b32_e32 v29, s10 ; VI-NEXT: v_mov_b32_e32 v30, s9 ; VI-NEXT: v_mov_b32_e32 v31, s8 -; VI-NEXT: v_readlane_b32 s39, v32, 7 -; VI-NEXT: v_readlane_b32 s38, v32, 6 -; VI-NEXT: v_readlane_b32 s37, v32, 5 -; VI-NEXT: v_readlane_b32 s36, v32, 4 -; VI-NEXT: v_readlane_b32 s35, v32, 3 -; VI-NEXT: v_readlane_b32 s34, v32, 2 -; VI-NEXT: v_readlane_b32 s31, v32, 1 -; VI-NEXT: v_readlane_b32 s30, v32, 0 +; VI-NEXT: v_readlane_b32 s31, v32, 7 +; VI-NEXT: v_readlane_b32 s39, v32, 5 +; VI-NEXT: v_readlane_b32 s38, v32, 4 +; VI-NEXT: v_readlane_b32 s37, v32, 3 +; VI-NEXT: v_readlane_b32 s36, v32, 2 +; VI-NEXT: v_readlane_b32 s35, v32, 1 +; VI-NEXT: v_readlane_b32 s34, v32, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -244357,14 +246653,15 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v32, s30, 0 -; VI-NEXT: v_writelane_b32 v32, s31, 1 -; VI-NEXT: v_writelane_b32 v32, s34, 2 -; VI-NEXT: v_writelane_b32 v32, s35, 3 -; VI-NEXT: v_writelane_b32 v32, s36, 4 -; VI-NEXT: v_writelane_b32 v32, s37, 5 +; VI-NEXT: v_writelane_b32 v32, s34, 0 +; VI-NEXT: v_writelane_b32 v32, s35, 1 +; VI-NEXT: v_writelane_b32 v32, s36, 2 +; VI-NEXT: v_writelane_b32 v32, s37, 3 +; VI-NEXT: v_writelane_b32 v32, s38, 4 +; VI-NEXT: v_writelane_b32 v32, s39, 5 +; VI-NEXT: v_writelane_b32 v32, s30, 6 +; VI-NEXT: v_writelane_b32 v32, s31, 7 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 -; VI-NEXT: v_writelane_b32 v32, s38, 6 ; VI-NEXT: v_readfirstlane_b32 s47, v2 ; VI-NEXT: v_readfirstlane_b32 s46, v3 ; VI-NEXT: v_readfirstlane_b32 s45, v4 @@ -244384,7 +246681,6 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i ; VI-NEXT: v_readfirstlane_b32 s6, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s7, v1 -; VI-NEXT: v_writelane_b32 v32, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB111_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB111_3 @@ -244550,6 +246846,7 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i ; VI-NEXT: s_add_i32 s46, s46, 0x30000 ; VI-NEXT: s_add_i32 s47, s4, 0x30000 ; VI-NEXT: .LBB111_3: ; %end +; VI-NEXT: v_readlane_b32 s30, v32, 6 ; VI-NEXT: v_mov_b32_e32 v0, s16 ; VI-NEXT: v_mov_b32_e32 v1, s17 ; VI-NEXT: v_mov_b32_e32 v2, s18 @@ -244582,14 +246879,13 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i ; VI-NEXT: v_mov_b32_e32 v29, s10 ; VI-NEXT: v_mov_b32_e32 v30, s9 ; VI-NEXT: v_mov_b32_e32 v31, s8 -; VI-NEXT: v_readlane_b32 s39, v32, 7 -; VI-NEXT: v_readlane_b32 s38, v32, 6 -; VI-NEXT: v_readlane_b32 s37, v32, 5 -; VI-NEXT: v_readlane_b32 s36, v32, 4 -; VI-NEXT: v_readlane_b32 s35, v32, 3 -; VI-NEXT: v_readlane_b32 s34, v32, 2 -; VI-NEXT: v_readlane_b32 s31, v32, 1 -; VI-NEXT: v_readlane_b32 s30, v32, 0 +; VI-NEXT: v_readlane_b32 s31, v32, 7 +; VI-NEXT: v_readlane_b32 s39, v32, 5 +; VI-NEXT: v_readlane_b32 s38, v32, 4 +; VI-NEXT: v_readlane_b32 s37, v32, 3 +; VI-NEXT: v_readlane_b32 s36, v32, 2 +; VI-NEXT: v_readlane_b32 s35, v32, 1 +; VI-NEXT: v_readlane_b32 s34, v32, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll index 01e397d629ea9..a48eb27460f7d 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll @@ -30553,14 +30553,14 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) { ; SI-LABEL: bitcast_v16i16_to_v32i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_mov_b32_e32 v48, v15 -; SI-NEXT: v_mov_b32_e32 v49, v11 -; SI-NEXT: v_mov_b32_e32 v50, v7 -; SI-NEXT: v_mov_b32_e32 v51, v3 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v48, v15 +; SI-NEXT: v_mov_b32_e32 v49, v11 +; SI-NEXT: v_mov_b32_e32 v50, v7 +; SI-NEXT: v_mov_b32_e32 v51, v3 ; SI-NEXT: v_mov_b32_e32 v32, v14 ; SI-NEXT: v_mov_b32_e32 v37, v12 ; SI-NEXT: v_mov_b32_e32 v33, v10 @@ -40102,11 +40102,11 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a, ; SI-LABEL: bitcast_v16bf16_to_v32i8_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_mul_f32_e64 v24, 1.0, s17 ; SI-NEXT: v_mul_f32_e64 v32, 1.0, s16 diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll index 9041f64cb17fb..7adaa6d3c3651 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll @@ -15733,6 +15733,10 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) { ; VI-LABEL: bitcast_v20i16_to_v40i8: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v10 ; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v9 @@ -15744,10 +15748,6 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) { ; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v3 ; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v1 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: ; implicit-def: $vgpr34 ; VI-NEXT: ; implicit-def: $vgpr40 ; VI-NEXT: ; implicit-def: $vgpr15 @@ -16525,18 +16525,18 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32 ; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v8, s30, 0 -; SI-NEXT: v_writelane_b32 v8, s31, 1 -; SI-NEXT: v_writelane_b32 v8, s34, 2 -; SI-NEXT: v_writelane_b32 v8, s35, 3 -; SI-NEXT: v_writelane_b32 v8, s36, 4 -; SI-NEXT: v_writelane_b32 v8, s37, 5 -; SI-NEXT: v_writelane_b32 v8, s38, 6 -; SI-NEXT: v_writelane_b32 v8, s39, 7 -; SI-NEXT: v_writelane_b32 v8, s48, 8 -; SI-NEXT: v_writelane_b32 v8, s49, 9 +; SI-NEXT: v_writelane_b32 v8, s34, 0 +; SI-NEXT: v_writelane_b32 v8, s35, 1 +; SI-NEXT: v_writelane_b32 v8, s36, 2 +; SI-NEXT: v_writelane_b32 v8, s37, 3 +; SI-NEXT: v_writelane_b32 v8, s38, 4 +; SI-NEXT: v_writelane_b32 v8, s39, 5 +; SI-NEXT: v_writelane_b32 v8, s48, 6 +; SI-NEXT: v_writelane_b32 v8, s49, 7 +; SI-NEXT: v_writelane_b32 v8, s50, 8 +; SI-NEXT: v_writelane_b32 v8, s30, 9 +; SI-NEXT: v_writelane_b32 v8, s31, 10 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 -; SI-NEXT: v_writelane_b32 v8, s50, 10 ; SI-NEXT: v_readfirstlane_b32 s39, v6 ; SI-NEXT: v_readfirstlane_b32 s48, v5 ; SI-NEXT: v_readfirstlane_b32 s49, v4 @@ -16815,18 +16815,18 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 36, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v8, 9 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s50, v8, 10 -; SI-NEXT: v_readlane_b32 s49, v8, 9 -; SI-NEXT: v_readlane_b32 s48, v8, 8 -; SI-NEXT: v_readlane_b32 s39, v8, 7 -; SI-NEXT: v_readlane_b32 s38, v8, 6 -; SI-NEXT: v_readlane_b32 s37, v8, 5 -; SI-NEXT: v_readlane_b32 s36, v8, 4 -; SI-NEXT: v_readlane_b32 s35, v8, 3 -; SI-NEXT: v_readlane_b32 s34, v8, 2 -; SI-NEXT: v_readlane_b32 s31, v8, 1 -; SI-NEXT: v_readlane_b32 s30, v8, 0 +; SI-NEXT: v_readlane_b32 s31, v8, 10 +; SI-NEXT: v_readlane_b32 s50, v8, 8 +; SI-NEXT: v_readlane_b32 s49, v8, 7 +; SI-NEXT: v_readlane_b32 s48, v8, 6 +; SI-NEXT: v_readlane_b32 s39, v8, 5 +; SI-NEXT: v_readlane_b32 s38, v8, 4 +; SI-NEXT: v_readlane_b32 s37, v8, 3 +; SI-NEXT: v_readlane_b32 s36, v8, 2 +; SI-NEXT: v_readlane_b32 s35, v8, 1 +; SI-NEXT: v_readlane_b32 s34, v8, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll index ee23420c2a662..de18eec1ccc79 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll @@ -6673,8 +6673,8 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a ; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v19, s30, 0 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_writelane_b32 v19, s31, 1 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_readfirstlane_b32 s30, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s31, v1 @@ -6992,8 +6992,8 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a ; VI-NEXT: v_mov_b32_e32 v14, s30 ; VI-NEXT: v_mov_b32_e32 v15, s31 ; VI-NEXT: .LBB23_5: ; %end -; VI-NEXT: v_readlane_b32 s31, v19, 1 ; VI-NEXT: v_readlane_b32 s30, v19, 0 +; VI-NEXT: v_readlane_b32 s31, v19, 1 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -7007,8 +7007,8 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a ; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: v_writelane_b32 v20, s30, 0 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_writelane_b32 v20, s31, 1 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_readfirstlane_b32 s30, v0 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s31, v1 @@ -7343,8 +7343,8 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a ; GFX9-NEXT: v_mov_b32_e32 v14, s30 ; GFX9-NEXT: v_mov_b32_e32 v15, s31 ; GFX9-NEXT: .LBB23_5: ; %end -; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -8062,8 +8062,6 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v16i32_to_v64i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: ; implicit-def: $vgpr26 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -8080,6 +8078,8 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; SI-NEXT: ; implicit-def: $vgpr26 ; SI-NEXT: ; implicit-def: $vgpr58 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr46 @@ -8481,10 +8481,6 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) { ; VI-LABEL: bitcast_v16i32_to_v64i8: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; VI-NEXT: ; implicit-def: $vgpr17 -; VI-NEXT: ; kill: killed $vgpr17 -; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -8501,6 +8497,10 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; VI-NEXT: ; implicit-def: $vgpr17 +; VI-NEXT: ; kill: killed $vgpr17 +; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: ; implicit-def: $vgpr29 ; VI-NEXT: ; implicit-def: $vgpr27 ; VI-NEXT: ; implicit-def: $vgpr22 @@ -8812,10 +8812,6 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) { ; GFX9-LABEL: bitcast_v16i32_to_v64i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; GFX9-NEXT: ; implicit-def: $vgpr17 -; GFX9-NEXT: ; kill: killed $vgpr17 -; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -8832,6 +8828,10 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; GFX9-NEXT: ; implicit-def: $vgpr17 +; GFX9-NEXT: ; kill: killed $vgpr17 +; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: ; implicit-def: $vgpr29 ; GFX9-NEXT: ; implicit-def: $vgpr27 ; GFX9-NEXT: ; implicit-def: $vgpr23 @@ -9707,40 +9707,40 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32 ; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v4, s30, 0 -; SI-NEXT: v_writelane_b32 v4, s31, 1 -; SI-NEXT: v_writelane_b32 v4, s34, 2 -; SI-NEXT: v_writelane_b32 v4, s35, 3 -; SI-NEXT: v_writelane_b32 v4, s36, 4 -; SI-NEXT: v_writelane_b32 v4, s37, 5 -; SI-NEXT: v_writelane_b32 v4, s38, 6 -; SI-NEXT: v_writelane_b32 v4, s39, 7 -; SI-NEXT: v_writelane_b32 v4, s48, 8 -; SI-NEXT: v_writelane_b32 v4, s49, 9 -; SI-NEXT: v_writelane_b32 v4, s50, 10 -; SI-NEXT: v_writelane_b32 v4, s51, 11 -; SI-NEXT: v_writelane_b32 v4, s52, 12 -; SI-NEXT: v_writelane_b32 v4, s53, 13 -; SI-NEXT: v_writelane_b32 v4, s54, 14 -; SI-NEXT: v_writelane_b32 v4, s55, 15 -; SI-NEXT: v_writelane_b32 v4, s64, 16 -; SI-NEXT: v_writelane_b32 v4, s65, 17 -; SI-NEXT: v_writelane_b32 v4, s66, 18 -; SI-NEXT: v_writelane_b32 v4, s67, 19 -; SI-NEXT: v_writelane_b32 v4, s68, 20 -; SI-NEXT: v_writelane_b32 v4, s69, 21 -; SI-NEXT: v_writelane_b32 v4, s70, 22 -; SI-NEXT: v_writelane_b32 v4, s71, 23 -; SI-NEXT: v_writelane_b32 v4, s80, 24 -; SI-NEXT: v_writelane_b32 v4, s81, 25 -; SI-NEXT: v_writelane_b32 v4, s82, 26 -; SI-NEXT: v_writelane_b32 v4, s83, 27 +; SI-NEXT: v_writelane_b32 v4, s34, 0 +; SI-NEXT: v_writelane_b32 v4, s35, 1 +; SI-NEXT: v_writelane_b32 v4, s36, 2 +; SI-NEXT: v_writelane_b32 v4, s37, 3 +; SI-NEXT: v_writelane_b32 v4, s38, 4 +; SI-NEXT: v_writelane_b32 v4, s39, 5 +; SI-NEXT: v_writelane_b32 v4, s48, 6 +; SI-NEXT: v_writelane_b32 v4, s49, 7 +; SI-NEXT: v_writelane_b32 v4, s50, 8 +; SI-NEXT: v_writelane_b32 v4, s51, 9 +; SI-NEXT: v_writelane_b32 v4, s52, 10 +; SI-NEXT: v_writelane_b32 v4, s53, 11 +; SI-NEXT: v_writelane_b32 v4, s54, 12 +; SI-NEXT: v_writelane_b32 v4, s55, 13 +; SI-NEXT: v_writelane_b32 v4, s64, 14 +; SI-NEXT: v_writelane_b32 v4, s65, 15 +; SI-NEXT: v_writelane_b32 v4, s66, 16 +; SI-NEXT: v_writelane_b32 v4, s67, 17 +; SI-NEXT: v_writelane_b32 v4, s68, 18 +; SI-NEXT: v_writelane_b32 v4, s69, 19 +; SI-NEXT: v_writelane_b32 v4, s70, 20 +; SI-NEXT: v_writelane_b32 v4, s71, 21 +; SI-NEXT: v_writelane_b32 v4, s80, 22 +; SI-NEXT: v_writelane_b32 v4, s81, 23 +; SI-NEXT: v_writelane_b32 v4, s82, 24 +; SI-NEXT: v_writelane_b32 v4, s83, 25 +; SI-NEXT: v_writelane_b32 v4, s84, 26 +; SI-NEXT: v_writelane_b32 v4, s85, 27 +; SI-NEXT: v_writelane_b32 v4, s30, 28 +; SI-NEXT: v_writelane_b32 v4, s31, 29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; SI-NEXT: v_writelane_b32 v4, s84, 28 ; SI-NEXT: v_readfirstlane_b32 s4, v1 ; SI-NEXT: s_and_b64 s[6:7], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v2 -; SI-NEXT: v_writelane_b32 v4, s85, 29 ; SI-NEXT: s_cbranch_scc0 .LBB25_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s38, s5, 24 @@ -10061,37 +10061,37 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v4, 28 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s85, v4, 29 -; SI-NEXT: v_readlane_b32 s84, v4, 28 -; SI-NEXT: v_readlane_b32 s83, v4, 27 -; SI-NEXT: v_readlane_b32 s82, v4, 26 -; SI-NEXT: v_readlane_b32 s81, v4, 25 -; SI-NEXT: v_readlane_b32 s80, v4, 24 -; SI-NEXT: v_readlane_b32 s71, v4, 23 -; SI-NEXT: v_readlane_b32 s70, v4, 22 -; SI-NEXT: v_readlane_b32 s69, v4, 21 -; SI-NEXT: v_readlane_b32 s68, v4, 20 -; SI-NEXT: v_readlane_b32 s67, v4, 19 -; SI-NEXT: v_readlane_b32 s66, v4, 18 -; SI-NEXT: v_readlane_b32 s65, v4, 17 -; SI-NEXT: v_readlane_b32 s64, v4, 16 -; SI-NEXT: v_readlane_b32 s55, v4, 15 -; SI-NEXT: v_readlane_b32 s54, v4, 14 -; SI-NEXT: v_readlane_b32 s53, v4, 13 -; SI-NEXT: v_readlane_b32 s52, v4, 12 -; SI-NEXT: v_readlane_b32 s51, v4, 11 -; SI-NEXT: v_readlane_b32 s50, v4, 10 -; SI-NEXT: v_readlane_b32 s49, v4, 9 -; SI-NEXT: v_readlane_b32 s48, v4, 8 -; SI-NEXT: v_readlane_b32 s39, v4, 7 -; SI-NEXT: v_readlane_b32 s38, v4, 6 -; SI-NEXT: v_readlane_b32 s37, v4, 5 -; SI-NEXT: v_readlane_b32 s36, v4, 4 -; SI-NEXT: v_readlane_b32 s35, v4, 3 -; SI-NEXT: v_readlane_b32 s34, v4, 2 -; SI-NEXT: v_readlane_b32 s31, v4, 1 -; SI-NEXT: v_readlane_b32 s30, v4, 0 +; SI-NEXT: v_readlane_b32 s31, v4, 29 +; SI-NEXT: v_readlane_b32 s85, v4, 27 +; SI-NEXT: v_readlane_b32 s84, v4, 26 +; SI-NEXT: v_readlane_b32 s83, v4, 25 +; SI-NEXT: v_readlane_b32 s82, v4, 24 +; SI-NEXT: v_readlane_b32 s81, v4, 23 +; SI-NEXT: v_readlane_b32 s80, v4, 22 +; SI-NEXT: v_readlane_b32 s71, v4, 21 +; SI-NEXT: v_readlane_b32 s70, v4, 20 +; SI-NEXT: v_readlane_b32 s69, v4, 19 +; SI-NEXT: v_readlane_b32 s68, v4, 18 +; SI-NEXT: v_readlane_b32 s67, v4, 17 +; SI-NEXT: v_readlane_b32 s66, v4, 16 +; SI-NEXT: v_readlane_b32 s65, v4, 15 +; SI-NEXT: v_readlane_b32 s64, v4, 14 +; SI-NEXT: v_readlane_b32 s55, v4, 13 +; SI-NEXT: v_readlane_b32 s54, v4, 12 +; SI-NEXT: v_readlane_b32 s53, v4, 11 +; SI-NEXT: v_readlane_b32 s52, v4, 10 +; SI-NEXT: v_readlane_b32 s51, v4, 9 +; SI-NEXT: v_readlane_b32 s50, v4, 8 +; SI-NEXT: v_readlane_b32 s49, v4, 7 +; SI-NEXT: v_readlane_b32 s48, v4, 6 +; SI-NEXT: v_readlane_b32 s39, v4, 5 +; SI-NEXT: v_readlane_b32 s38, v4, 4 +; SI-NEXT: v_readlane_b32 s37, v4, 3 +; SI-NEXT: v_readlane_b32 s36, v4, 2 +; SI-NEXT: v_readlane_b32 s35, v4, 1 +; SI-NEXT: v_readlane_b32 s34, v4, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -10154,30 +10154,30 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v4, s30, 0 -; VI-NEXT: v_writelane_b32 v4, s31, 1 -; VI-NEXT: v_writelane_b32 v4, s34, 2 -; VI-NEXT: v_writelane_b32 v4, s35, 3 -; VI-NEXT: v_writelane_b32 v4, s36, 4 -; VI-NEXT: v_writelane_b32 v4, s37, 5 -; VI-NEXT: v_writelane_b32 v4, s38, 6 -; VI-NEXT: v_writelane_b32 v4, s39, 7 -; VI-NEXT: v_writelane_b32 v4, s48, 8 -; VI-NEXT: v_writelane_b32 v4, s49, 9 -; VI-NEXT: v_writelane_b32 v4, s50, 10 -; VI-NEXT: v_writelane_b32 v4, s51, 11 -; VI-NEXT: v_writelane_b32 v4, s52, 12 -; VI-NEXT: v_writelane_b32 v4, s53, 13 -; VI-NEXT: v_writelane_b32 v4, s54, 14 -; VI-NEXT: v_writelane_b32 v4, s55, 15 -; VI-NEXT: v_writelane_b32 v4, s64, 16 -; VI-NEXT: v_writelane_b32 v4, s65, 17 +; VI-NEXT: v_writelane_b32 v4, s34, 0 +; VI-NEXT: v_writelane_b32 v4, s35, 1 +; VI-NEXT: v_writelane_b32 v4, s36, 2 +; VI-NEXT: v_writelane_b32 v4, s37, 3 +; VI-NEXT: v_writelane_b32 v4, s38, 4 +; VI-NEXT: v_writelane_b32 v4, s39, 5 +; VI-NEXT: v_writelane_b32 v4, s48, 6 +; VI-NEXT: v_writelane_b32 v4, s49, 7 +; VI-NEXT: v_writelane_b32 v4, s50, 8 +; VI-NEXT: v_writelane_b32 v4, s51, 9 +; VI-NEXT: v_writelane_b32 v4, s52, 10 +; VI-NEXT: v_writelane_b32 v4, s53, 11 +; VI-NEXT: v_writelane_b32 v4, s54, 12 +; VI-NEXT: v_writelane_b32 v4, s55, 13 +; VI-NEXT: v_writelane_b32 v4, s64, 14 +; VI-NEXT: v_writelane_b32 v4, s65, 15 +; VI-NEXT: v_writelane_b32 v4, s66, 16 +; VI-NEXT: v_writelane_b32 v4, s67, 17 +; VI-NEXT: v_writelane_b32 v4, s30, 18 +; VI-NEXT: v_writelane_b32 v4, s31, 19 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; VI-NEXT: v_writelane_b32 v4, s66, 18 ; VI-NEXT: v_readfirstlane_b32 s4, v1 ; VI-NEXT: s_and_b64 s[6:7], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v2 -; VI-NEXT: v_writelane_b32 v4, s67, 19 ; VI-NEXT: s_cbranch_scc0 .LBB25_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s56, s5, 24 @@ -10485,27 +10485,27 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0 ; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_readlane_b32 s30, v4, 18 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; VI-NEXT: v_readlane_b32 s67, v4, 19 -; VI-NEXT: v_readlane_b32 s66, v4, 18 -; VI-NEXT: v_readlane_b32 s65, v4, 17 -; VI-NEXT: v_readlane_b32 s64, v4, 16 -; VI-NEXT: v_readlane_b32 s55, v4, 15 -; VI-NEXT: v_readlane_b32 s54, v4, 14 -; VI-NEXT: v_readlane_b32 s53, v4, 13 -; VI-NEXT: v_readlane_b32 s52, v4, 12 -; VI-NEXT: v_readlane_b32 s51, v4, 11 -; VI-NEXT: v_readlane_b32 s50, v4, 10 -; VI-NEXT: v_readlane_b32 s49, v4, 9 -; VI-NEXT: v_readlane_b32 s48, v4, 8 -; VI-NEXT: v_readlane_b32 s39, v4, 7 -; VI-NEXT: v_readlane_b32 s38, v4, 6 -; VI-NEXT: v_readlane_b32 s37, v4, 5 -; VI-NEXT: v_readlane_b32 s36, v4, 4 -; VI-NEXT: v_readlane_b32 s35, v4, 3 -; VI-NEXT: v_readlane_b32 s34, v4, 2 -; VI-NEXT: v_readlane_b32 s31, v4, 1 -; VI-NEXT: v_readlane_b32 s30, v4, 0 +; VI-NEXT: v_readlane_b32 s31, v4, 19 +; VI-NEXT: v_readlane_b32 s67, v4, 17 +; VI-NEXT: v_readlane_b32 s66, v4, 16 +; VI-NEXT: v_readlane_b32 s65, v4, 15 +; VI-NEXT: v_readlane_b32 s64, v4, 14 +; VI-NEXT: v_readlane_b32 s55, v4, 13 +; VI-NEXT: v_readlane_b32 s54, v4, 12 +; VI-NEXT: v_readlane_b32 s53, v4, 11 +; VI-NEXT: v_readlane_b32 s52, v4, 10 +; VI-NEXT: v_readlane_b32 s51, v4, 9 +; VI-NEXT: v_readlane_b32 s50, v4, 8 +; VI-NEXT: v_readlane_b32 s49, v4, 7 +; VI-NEXT: v_readlane_b32 s48, v4, 6 +; VI-NEXT: v_readlane_b32 s39, v4, 5 +; VI-NEXT: v_readlane_b32 s38, v4, 4 +; VI-NEXT: v_readlane_b32 s37, v4, 3 +; VI-NEXT: v_readlane_b32 s36, v4, 2 +; VI-NEXT: v_readlane_b32 s35, v4, 1 +; VI-NEXT: v_readlane_b32 s34, v4, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -10568,26 +10568,26 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v4, s30, 0 -; GFX9-NEXT: v_writelane_b32 v4, s31, 1 -; GFX9-NEXT: v_writelane_b32 v4, s34, 2 -; GFX9-NEXT: v_writelane_b32 v4, s35, 3 -; GFX9-NEXT: v_writelane_b32 v4, s36, 4 -; GFX9-NEXT: v_writelane_b32 v4, s37, 5 -; GFX9-NEXT: v_writelane_b32 v4, s38, 6 -; GFX9-NEXT: v_writelane_b32 v4, s39, 7 -; GFX9-NEXT: v_writelane_b32 v4, s48, 8 -; GFX9-NEXT: v_writelane_b32 v4, s49, 9 -; GFX9-NEXT: v_writelane_b32 v4, s50, 10 -; GFX9-NEXT: v_writelane_b32 v4, s51, 11 -; GFX9-NEXT: v_writelane_b32 v4, s52, 12 -; GFX9-NEXT: v_writelane_b32 v4, s53, 13 +; GFX9-NEXT: v_writelane_b32 v4, s34, 0 +; GFX9-NEXT: v_writelane_b32 v4, s35, 1 +; GFX9-NEXT: v_writelane_b32 v4, s36, 2 +; GFX9-NEXT: v_writelane_b32 v4, s37, 3 +; GFX9-NEXT: v_writelane_b32 v4, s38, 4 +; GFX9-NEXT: v_writelane_b32 v4, s39, 5 +; GFX9-NEXT: v_writelane_b32 v4, s48, 6 +; GFX9-NEXT: v_writelane_b32 v4, s49, 7 +; GFX9-NEXT: v_writelane_b32 v4, s50, 8 +; GFX9-NEXT: v_writelane_b32 v4, s51, 9 +; GFX9-NEXT: v_writelane_b32 v4, s52, 10 +; GFX9-NEXT: v_writelane_b32 v4, s53, 11 +; GFX9-NEXT: v_writelane_b32 v4, s54, 12 +; GFX9-NEXT: v_writelane_b32 v4, s55, 13 +; GFX9-NEXT: v_writelane_b32 v4, s30, 14 +; GFX9-NEXT: v_writelane_b32 v4, s31, 15 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: v_writelane_b32 v4, s54, 14 ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 ; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v2 -; GFX9-NEXT: v_writelane_b32 v4, s55, 15 ; GFX9-NEXT: s_cbranch_scc0 .LBB25_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s56, s5, 24 @@ -10880,23 +10880,23 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32 ; GFX9-NEXT: s_or_b32 s4, s4, s5 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_readlane_b32 s30, v4, 14 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60 -; GFX9-NEXT: v_readlane_b32 s55, v4, 15 -; GFX9-NEXT: v_readlane_b32 s54, v4, 14 -; GFX9-NEXT: v_readlane_b32 s53, v4, 13 -; GFX9-NEXT: v_readlane_b32 s52, v4, 12 -; GFX9-NEXT: v_readlane_b32 s51, v4, 11 -; GFX9-NEXT: v_readlane_b32 s50, v4, 10 -; GFX9-NEXT: v_readlane_b32 s49, v4, 9 -; GFX9-NEXT: v_readlane_b32 s48, v4, 8 -; GFX9-NEXT: v_readlane_b32 s39, v4, 7 -; GFX9-NEXT: v_readlane_b32 s38, v4, 6 -; GFX9-NEXT: v_readlane_b32 s37, v4, 5 -; GFX9-NEXT: v_readlane_b32 s36, v4, 4 -; GFX9-NEXT: v_readlane_b32 s35, v4, 3 -; GFX9-NEXT: v_readlane_b32 s34, v4, 2 -; GFX9-NEXT: v_readlane_b32 s31, v4, 1 -; GFX9-NEXT: v_readlane_b32 s30, v4, 0 +; GFX9-NEXT: v_readlane_b32 s31, v4, 15 +; GFX9-NEXT: v_readlane_b32 s55, v4, 13 +; GFX9-NEXT: v_readlane_b32 s54, v4, 12 +; GFX9-NEXT: v_readlane_b32 s53, v4, 11 +; GFX9-NEXT: v_readlane_b32 s52, v4, 10 +; GFX9-NEXT: v_readlane_b32 s51, v4, 9 +; GFX9-NEXT: v_readlane_b32 s50, v4, 8 +; GFX9-NEXT: v_readlane_b32 s49, v4, 7 +; GFX9-NEXT: v_readlane_b32 s48, v4, 6 +; GFX9-NEXT: v_readlane_b32 s39, v4, 5 +; GFX9-NEXT: v_readlane_b32 s38, v4, 4 +; GFX9-NEXT: v_readlane_b32 s37, v4, 3 +; GFX9-NEXT: v_readlane_b32 s36, v4, 2 +; GFX9-NEXT: v_readlane_b32 s35, v4, 1 +; GFX9-NEXT: v_readlane_b32 s34, v4, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -10959,17 +10959,17 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32 ; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX11-NEXT: scratch_store_b32 off, v17, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v17, s30, 0 +; GFX11-NEXT: v_writelane_b32 v17, s34, 0 +; GFX11-NEXT: v_writelane_b32 v17, s35, 1 +; GFX11-NEXT: v_writelane_b32 v17, s36, 2 +; GFX11-NEXT: v_writelane_b32 v17, s37, 3 +; GFX11-NEXT: v_writelane_b32 v17, s38, 4 +; GFX11-NEXT: v_writelane_b32 v17, s39, 5 +; GFX11-NEXT: v_writelane_b32 v17, s48, 6 +; GFX11-NEXT: v_writelane_b32 v17, s30, 7 +; GFX11-NEXT: v_writelane_b32 v17, s31, 8 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_mov_b32 vcc_lo, 0 -; GFX11-NEXT: v_writelane_b32 v17, s31, 1 -; GFX11-NEXT: v_writelane_b32 v17, s34, 2 -; GFX11-NEXT: v_writelane_b32 v17, s35, 3 -; GFX11-NEXT: v_writelane_b32 v17, s36, 4 -; GFX11-NEXT: v_writelane_b32 v17, s37, 5 -; GFX11-NEXT: v_writelane_b32 v17, s38, 6 -; GFX11-NEXT: v_writelane_b32 v17, s39, 7 -; GFX11-NEXT: v_writelane_b32 v17, s48, 8 ; GFX11-NEXT: s_cbranch_scc0 .LBB25_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s42, s27, 24 @@ -11240,20 +11240,20 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32 ; GFX11-NEXT: s_or_b32 s3, s4, s5 ; GFX11-NEXT: v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v14, s1 ; GFX11-NEXT: v_dual_mov_b32 v15, s2 :: v_dual_mov_b32 v16, s3 +; GFX11-NEXT: v_readlane_b32 s30, v17, 7 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16 ; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32 ; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:48 -; GFX11-NEXT: v_readlane_b32 s48, v17, 8 -; GFX11-NEXT: v_readlane_b32 s39, v17, 7 -; GFX11-NEXT: v_readlane_b32 s38, v17, 6 -; GFX11-NEXT: v_readlane_b32 s37, v17, 5 -; GFX11-NEXT: v_readlane_b32 s36, v17, 4 -; GFX11-NEXT: v_readlane_b32 s35, v17, 3 -; GFX11-NEXT: v_readlane_b32 s34, v17, 2 -; GFX11-NEXT: v_readlane_b32 s31, v17, 1 -; GFX11-NEXT: v_readlane_b32 s30, v17, 0 +; GFX11-NEXT: v_readlane_b32 s31, v17, 8 +; GFX11-NEXT: v_readlane_b32 s48, v17, 6 +; GFX11-NEXT: v_readlane_b32 s39, v17, 5 +; GFX11-NEXT: v_readlane_b32 s38, v17, 4 +; GFX11-NEXT: v_readlane_b32 s37, v17, 3 +; GFX11-NEXT: v_readlane_b32 s36, v17, 2 +; GFX11-NEXT: v_readlane_b32 s35, v17, 1 +; GFX11-NEXT: v_readlane_b32 s34, v17, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v17, off, s32 ; 4-byte Folded Reload ; GFX11-NEXT: s_mov_b32 exec_lo, s0 @@ -21564,8 +21564,8 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg ; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v19, s30, 0 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_writelane_b32 v19, s31, 1 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_readfirstlane_b32 s30, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s31, v1 @@ -21883,8 +21883,8 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg ; VI-NEXT: v_mov_b32_e32 v14, s30 ; VI-NEXT: v_mov_b32_e32 v15, s31 ; VI-NEXT: .LBB47_5: ; %end -; VI-NEXT: v_readlane_b32 s31, v19, 1 ; VI-NEXT: v_readlane_b32 s30, v19, 0 +; VI-NEXT: v_readlane_b32 s31, v19, 1 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -21898,8 +21898,8 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg ; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: v_writelane_b32 v20, s30, 0 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_writelane_b32 v20, s31, 1 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_readfirstlane_b32 s30, v0 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s31, v1 @@ -22234,8 +22234,8 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg ; GFX9-NEXT: v_mov_b32_e32 v14, s30 ; GFX9-NEXT: v_mov_b32_e32 v15, s31 ; GFX9-NEXT: .LBB47_5: ; %end -; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -22953,8 +22953,6 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v16f32_to_v64i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: ; implicit-def: $vgpr26 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -22971,6 +22969,8 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; SI-NEXT: ; implicit-def: $vgpr26 ; SI-NEXT: ; implicit-def: $vgpr58 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr46 @@ -23372,10 +23372,6 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) { ; VI-LABEL: bitcast_v16f32_to_v64i8: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; VI-NEXT: ; implicit-def: $vgpr17 -; VI-NEXT: ; kill: killed $vgpr17 -; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -23392,6 +23388,10 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; VI-NEXT: ; implicit-def: $vgpr17 +; VI-NEXT: ; kill: killed $vgpr17 +; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: ; implicit-def: $vgpr29 ; VI-NEXT: ; implicit-def: $vgpr27 ; VI-NEXT: ; implicit-def: $vgpr22 @@ -23703,10 +23703,6 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) { ; GFX9-LABEL: bitcast_v16f32_to_v64i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; GFX9-NEXT: ; implicit-def: $vgpr17 -; GFX9-NEXT: ; kill: killed $vgpr17 -; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -23723,6 +23719,10 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; GFX9-NEXT: ; implicit-def: $vgpr17 +; GFX9-NEXT: ; kill: killed $vgpr17 +; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: ; implicit-def: $vgpr29 ; GFX9-NEXT: ; implicit-def: $vgpr27 ; GFX9-NEXT: ; implicit-def: $vgpr23 @@ -24582,40 +24582,40 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v40, s30, 0 -; SI-NEXT: v_writelane_b32 v40, s31, 1 -; SI-NEXT: v_writelane_b32 v40, s34, 2 -; SI-NEXT: v_writelane_b32 v40, s35, 3 -; SI-NEXT: v_writelane_b32 v40, s36, 4 -; SI-NEXT: v_writelane_b32 v40, s37, 5 -; SI-NEXT: v_writelane_b32 v40, s38, 6 -; SI-NEXT: v_writelane_b32 v40, s39, 7 -; SI-NEXT: v_writelane_b32 v40, s48, 8 -; SI-NEXT: v_writelane_b32 v40, s49, 9 -; SI-NEXT: v_writelane_b32 v40, s50, 10 -; SI-NEXT: v_writelane_b32 v40, s51, 11 -; SI-NEXT: v_writelane_b32 v40, s52, 12 -; SI-NEXT: v_writelane_b32 v40, s53, 13 -; SI-NEXT: v_writelane_b32 v40, s54, 14 -; SI-NEXT: v_writelane_b32 v40, s55, 15 -; SI-NEXT: v_writelane_b32 v40, s64, 16 -; SI-NEXT: v_writelane_b32 v40, s65, 17 -; SI-NEXT: v_writelane_b32 v40, s66, 18 -; SI-NEXT: v_writelane_b32 v40, s67, 19 -; SI-NEXT: v_writelane_b32 v40, s68, 20 -; SI-NEXT: v_writelane_b32 v40, s69, 21 -; SI-NEXT: v_writelane_b32 v40, s70, 22 -; SI-NEXT: v_writelane_b32 v40, s71, 23 -; SI-NEXT: v_writelane_b32 v40, s80, 24 -; SI-NEXT: v_writelane_b32 v40, s81, 25 -; SI-NEXT: v_writelane_b32 v40, s82, 26 -; SI-NEXT: v_writelane_b32 v40, s83, 27 +; SI-NEXT: v_writelane_b32 v40, s34, 0 +; SI-NEXT: v_writelane_b32 v40, s35, 1 +; SI-NEXT: v_writelane_b32 v40, s36, 2 +; SI-NEXT: v_writelane_b32 v40, s37, 3 +; SI-NEXT: v_writelane_b32 v40, s38, 4 +; SI-NEXT: v_writelane_b32 v40, s39, 5 +; SI-NEXT: v_writelane_b32 v40, s48, 6 +; SI-NEXT: v_writelane_b32 v40, s49, 7 +; SI-NEXT: v_writelane_b32 v40, s50, 8 +; SI-NEXT: v_writelane_b32 v40, s51, 9 +; SI-NEXT: v_writelane_b32 v40, s52, 10 +; SI-NEXT: v_writelane_b32 v40, s53, 11 +; SI-NEXT: v_writelane_b32 v40, s54, 12 +; SI-NEXT: v_writelane_b32 v40, s55, 13 +; SI-NEXT: v_writelane_b32 v40, s64, 14 +; SI-NEXT: v_writelane_b32 v40, s65, 15 +; SI-NEXT: v_writelane_b32 v40, s66, 16 +; SI-NEXT: v_writelane_b32 v40, s67, 17 +; SI-NEXT: v_writelane_b32 v40, s68, 18 +; SI-NEXT: v_writelane_b32 v40, s69, 19 +; SI-NEXT: v_writelane_b32 v40, s70, 20 +; SI-NEXT: v_writelane_b32 v40, s71, 21 +; SI-NEXT: v_writelane_b32 v40, s80, 22 +; SI-NEXT: v_writelane_b32 v40, s81, 23 +; SI-NEXT: v_writelane_b32 v40, s82, 24 +; SI-NEXT: v_writelane_b32 v40, s83, 25 +; SI-NEXT: v_writelane_b32 v40, s84, 26 +; SI-NEXT: v_writelane_b32 v40, s85, 27 +; SI-NEXT: v_writelane_b32 v40, s30, 28 +; SI-NEXT: v_writelane_b32 v40, s31, 29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; SI-NEXT: v_writelane_b32 v40, s84, 28 ; SI-NEXT: v_readfirstlane_b32 s36, v1 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s37, v2 -; SI-NEXT: v_writelane_b32 v40, s85, 29 ; SI-NEXT: s_cbranch_scc0 .LBB49_3 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s82, s37, 24 @@ -25030,37 +25030,37 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3 ; SI-NEXT: v_or_b32_e32 v2, v3, v2 ; SI-NEXT: v_or_b32_e32 v1, v1, v2 ; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0 +; SI-NEXT: v_readlane_b32 s30, v40, 28 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s85, v40, 29 -; SI-NEXT: v_readlane_b32 s84, v40, 28 -; SI-NEXT: v_readlane_b32 s83, v40, 27 -; SI-NEXT: v_readlane_b32 s82, v40, 26 -; SI-NEXT: v_readlane_b32 s81, v40, 25 -; SI-NEXT: v_readlane_b32 s80, v40, 24 -; SI-NEXT: v_readlane_b32 s71, v40, 23 -; SI-NEXT: v_readlane_b32 s70, v40, 22 -; SI-NEXT: v_readlane_b32 s69, v40, 21 -; SI-NEXT: v_readlane_b32 s68, v40, 20 -; SI-NEXT: v_readlane_b32 s67, v40, 19 -; SI-NEXT: v_readlane_b32 s66, v40, 18 -; SI-NEXT: v_readlane_b32 s65, v40, 17 -; SI-NEXT: v_readlane_b32 s64, v40, 16 -; SI-NEXT: v_readlane_b32 s55, v40, 15 -; SI-NEXT: v_readlane_b32 s54, v40, 14 -; SI-NEXT: v_readlane_b32 s53, v40, 13 -; SI-NEXT: v_readlane_b32 s52, v40, 12 -; SI-NEXT: v_readlane_b32 s51, v40, 11 -; SI-NEXT: v_readlane_b32 s50, v40, 10 -; SI-NEXT: v_readlane_b32 s49, v40, 9 -; SI-NEXT: v_readlane_b32 s48, v40, 8 -; SI-NEXT: v_readlane_b32 s39, v40, 7 -; SI-NEXT: v_readlane_b32 s38, v40, 6 -; SI-NEXT: v_readlane_b32 s37, v40, 5 -; SI-NEXT: v_readlane_b32 s36, v40, 4 -; SI-NEXT: v_readlane_b32 s35, v40, 3 -; SI-NEXT: v_readlane_b32 s34, v40, 2 -; SI-NEXT: v_readlane_b32 s31, v40, 1 -; SI-NEXT: v_readlane_b32 s30, v40, 0 +; SI-NEXT: v_readlane_b32 s31, v40, 29 +; SI-NEXT: v_readlane_b32 s85, v40, 27 +; SI-NEXT: v_readlane_b32 s84, v40, 26 +; SI-NEXT: v_readlane_b32 s83, v40, 25 +; SI-NEXT: v_readlane_b32 s82, v40, 24 +; SI-NEXT: v_readlane_b32 s81, v40, 23 +; SI-NEXT: v_readlane_b32 s80, v40, 22 +; SI-NEXT: v_readlane_b32 s71, v40, 21 +; SI-NEXT: v_readlane_b32 s70, v40, 20 +; SI-NEXT: v_readlane_b32 s69, v40, 19 +; SI-NEXT: v_readlane_b32 s68, v40, 18 +; SI-NEXT: v_readlane_b32 s67, v40, 17 +; SI-NEXT: v_readlane_b32 s66, v40, 16 +; SI-NEXT: v_readlane_b32 s65, v40, 15 +; SI-NEXT: v_readlane_b32 s64, v40, 14 +; SI-NEXT: v_readlane_b32 s55, v40, 13 +; SI-NEXT: v_readlane_b32 s54, v40, 12 +; SI-NEXT: v_readlane_b32 s53, v40, 11 +; SI-NEXT: v_readlane_b32 s52, v40, 10 +; SI-NEXT: v_readlane_b32 s51, v40, 9 +; SI-NEXT: v_readlane_b32 s50, v40, 8 +; SI-NEXT: v_readlane_b32 s49, v40, 7 +; SI-NEXT: v_readlane_b32 s48, v40, 6 +; SI-NEXT: v_readlane_b32 s39, v40, 5 +; SI-NEXT: v_readlane_b32 s38, v40, 4 +; SI-NEXT: v_readlane_b32 s37, v40, 3 +; SI-NEXT: v_readlane_b32 s36, v40, 2 +; SI-NEXT: v_readlane_b32 s35, v40, 1 +; SI-NEXT: v_readlane_b32 s34, v40, 0 ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -25073,30 +25073,6 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3 ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v63, s30, 0 -; VI-NEXT: v_writelane_b32 v63, s31, 1 -; VI-NEXT: v_writelane_b32 v63, s34, 2 -; VI-NEXT: v_writelane_b32 v63, s35, 3 -; VI-NEXT: v_writelane_b32 v63, s36, 4 -; VI-NEXT: v_writelane_b32 v63, s37, 5 -; VI-NEXT: v_writelane_b32 v63, s38, 6 -; VI-NEXT: v_writelane_b32 v63, s39, 7 -; VI-NEXT: v_writelane_b32 v63, s48, 8 -; VI-NEXT: v_writelane_b32 v63, s49, 9 -; VI-NEXT: v_writelane_b32 v63, s50, 10 -; VI-NEXT: v_writelane_b32 v63, s51, 11 -; VI-NEXT: v_writelane_b32 v63, s52, 12 -; VI-NEXT: v_writelane_b32 v63, s53, 13 -; VI-NEXT: v_writelane_b32 v63, s54, 14 -; VI-NEXT: v_writelane_b32 v63, s55, 15 -; VI-NEXT: v_writelane_b32 v63, s64, 16 -; VI-NEXT: v_writelane_b32 v63, s65, 17 -; VI-NEXT: v_writelane_b32 v63, s66, 18 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; VI-NEXT: v_writelane_b32 v63, s67, 19 -; VI-NEXT: v_readfirstlane_b32 s4, v1 -; VI-NEXT: s_and_b64 s[6:7], vcc, exec -; VI-NEXT: v_readfirstlane_b32 s5, v2 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -25112,6 +25088,30 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3 ; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_writelane_b32 v63, s34, 0 +; VI-NEXT: v_writelane_b32 v63, s35, 1 +; VI-NEXT: v_writelane_b32 v63, s36, 2 +; VI-NEXT: v_writelane_b32 v63, s37, 3 +; VI-NEXT: v_writelane_b32 v63, s38, 4 +; VI-NEXT: v_writelane_b32 v63, s39, 5 +; VI-NEXT: v_writelane_b32 v63, s48, 6 +; VI-NEXT: v_writelane_b32 v63, s49, 7 +; VI-NEXT: v_writelane_b32 v63, s50, 8 +; VI-NEXT: v_writelane_b32 v63, s51, 9 +; VI-NEXT: v_writelane_b32 v63, s52, 10 +; VI-NEXT: v_writelane_b32 v63, s53, 11 +; VI-NEXT: v_writelane_b32 v63, s54, 12 +; VI-NEXT: v_writelane_b32 v63, s55, 13 +; VI-NEXT: v_writelane_b32 v63, s64, 14 +; VI-NEXT: v_writelane_b32 v63, s65, 15 +; VI-NEXT: v_writelane_b32 v63, s66, 16 +; VI-NEXT: v_writelane_b32 v63, s67, 17 +; VI-NEXT: v_writelane_b32 v63, s30, 18 +; VI-NEXT: v_writelane_b32 v63, s31, 19 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; VI-NEXT: v_readfirstlane_b32 s4, v1 +; VI-NEXT: s_and_b64 s[6:7], vcc, exec +; VI-NEXT: v_readfirstlane_b32 s5, v2 ; VI-NEXT: s_cbranch_scc0 .LBB49_3 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s56, s5, 24 @@ -25440,26 +25440,26 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3 ; VI-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; VI-NEXT: v_readlane_b32 s67, v63, 19 -; VI-NEXT: v_readlane_b32 s66, v63, 18 -; VI-NEXT: v_readlane_b32 s65, v63, 17 -; VI-NEXT: v_readlane_b32 s64, v63, 16 -; VI-NEXT: v_readlane_b32 s55, v63, 15 -; VI-NEXT: v_readlane_b32 s54, v63, 14 -; VI-NEXT: v_readlane_b32 s53, v63, 13 -; VI-NEXT: v_readlane_b32 s52, v63, 12 -; VI-NEXT: v_readlane_b32 s51, v63, 11 -; VI-NEXT: v_readlane_b32 s50, v63, 10 -; VI-NEXT: v_readlane_b32 s49, v63, 9 -; VI-NEXT: v_readlane_b32 s48, v63, 8 -; VI-NEXT: v_readlane_b32 s39, v63, 7 -; VI-NEXT: v_readlane_b32 s38, v63, 6 -; VI-NEXT: v_readlane_b32 s37, v63, 5 -; VI-NEXT: v_readlane_b32 s36, v63, 4 -; VI-NEXT: v_readlane_b32 s35, v63, 3 -; VI-NEXT: v_readlane_b32 s34, v63, 2 -; VI-NEXT: v_readlane_b32 s31, v63, 1 -; VI-NEXT: v_readlane_b32 s30, v63, 0 +; VI-NEXT: v_readlane_b32 s30, v63, 18 +; VI-NEXT: v_readlane_b32 s31, v63, 19 +; VI-NEXT: v_readlane_b32 s67, v63, 17 +; VI-NEXT: v_readlane_b32 s66, v63, 16 +; VI-NEXT: v_readlane_b32 s65, v63, 15 +; VI-NEXT: v_readlane_b32 s64, v63, 14 +; VI-NEXT: v_readlane_b32 s55, v63, 13 +; VI-NEXT: v_readlane_b32 s54, v63, 12 +; VI-NEXT: v_readlane_b32 s53, v63, 11 +; VI-NEXT: v_readlane_b32 s52, v63, 10 +; VI-NEXT: v_readlane_b32 s51, v63, 9 +; VI-NEXT: v_readlane_b32 s50, v63, 8 +; VI-NEXT: v_readlane_b32 s49, v63, 7 +; VI-NEXT: v_readlane_b32 s48, v63, 6 +; VI-NEXT: v_readlane_b32 s39, v63, 5 +; VI-NEXT: v_readlane_b32 s38, v63, 4 +; VI-NEXT: v_readlane_b32 s37, v63, 3 +; VI-NEXT: v_readlane_b32 s36, v63, 2 +; VI-NEXT: v_readlane_b32 s35, v63, 1 +; VI-NEXT: v_readlane_b32 s34, v63, 0 ; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v5 ; VI-NEXT: v_or_b32_sdwa v5, v33, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -25517,26 +25517,6 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v63, s30, 0 -; GFX9-NEXT: v_writelane_b32 v63, s31, 1 -; GFX9-NEXT: v_writelane_b32 v63, s34, 2 -; GFX9-NEXT: v_writelane_b32 v63, s35, 3 -; GFX9-NEXT: v_writelane_b32 v63, s36, 4 -; GFX9-NEXT: v_writelane_b32 v63, s37, 5 -; GFX9-NEXT: v_writelane_b32 v63, s38, 6 -; GFX9-NEXT: v_writelane_b32 v63, s39, 7 -; GFX9-NEXT: v_writelane_b32 v63, s48, 8 -; GFX9-NEXT: v_writelane_b32 v63, s49, 9 -; GFX9-NEXT: v_writelane_b32 v63, s50, 10 -; GFX9-NEXT: v_writelane_b32 v63, s51, 11 -; GFX9-NEXT: v_writelane_b32 v63, s52, 12 -; GFX9-NEXT: v_writelane_b32 v63, s53, 13 -; GFX9-NEXT: v_writelane_b32 v63, s54, 14 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: v_writelane_b32 v63, s55, 15 -; GFX9-NEXT: v_readfirstlane_b32 s4, v1 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s5, v2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -25552,6 +25532,26 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v63, s34, 0 +; GFX9-NEXT: v_writelane_b32 v63, s35, 1 +; GFX9-NEXT: v_writelane_b32 v63, s36, 2 +; GFX9-NEXT: v_writelane_b32 v63, s37, 3 +; GFX9-NEXT: v_writelane_b32 v63, s38, 4 +; GFX9-NEXT: v_writelane_b32 v63, s39, 5 +; GFX9-NEXT: v_writelane_b32 v63, s48, 6 +; GFX9-NEXT: v_writelane_b32 v63, s49, 7 +; GFX9-NEXT: v_writelane_b32 v63, s50, 8 +; GFX9-NEXT: v_writelane_b32 v63, s51, 9 +; GFX9-NEXT: v_writelane_b32 v63, s52, 10 +; GFX9-NEXT: v_writelane_b32 v63, s53, 11 +; GFX9-NEXT: v_writelane_b32 v63, s54, 12 +; GFX9-NEXT: v_writelane_b32 v63, s55, 13 +; GFX9-NEXT: v_writelane_b32 v63, s30, 14 +; GFX9-NEXT: v_writelane_b32 v63, s31, 15 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v1 +; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec +; GFX9-NEXT: v_readfirstlane_b32 s5, v2 ; GFX9-NEXT: s_cbranch_scc0 .LBB49_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s56, s5, 24 @@ -25873,22 +25873,22 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3 ; GFX9-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s55, v63, 15 -; GFX9-NEXT: v_readlane_b32 s54, v63, 14 -; GFX9-NEXT: v_readlane_b32 s53, v63, 13 -; GFX9-NEXT: v_readlane_b32 s52, v63, 12 -; GFX9-NEXT: v_readlane_b32 s51, v63, 11 -; GFX9-NEXT: v_readlane_b32 s50, v63, 10 -; GFX9-NEXT: v_readlane_b32 s49, v63, 9 -; GFX9-NEXT: v_readlane_b32 s48, v63, 8 -; GFX9-NEXT: v_readlane_b32 s39, v63, 7 -; GFX9-NEXT: v_readlane_b32 s38, v63, 6 -; GFX9-NEXT: v_readlane_b32 s37, v63, 5 -; GFX9-NEXT: v_readlane_b32 s36, v63, 4 -; GFX9-NEXT: v_readlane_b32 s35, v63, 3 -; GFX9-NEXT: v_readlane_b32 s34, v63, 2 -; GFX9-NEXT: v_readlane_b32 s31, v63, 1 -; GFX9-NEXT: v_readlane_b32 s30, v63, 0 +; GFX9-NEXT: v_readlane_b32 s30, v63, 14 +; GFX9-NEXT: v_readlane_b32 s31, v63, 15 +; GFX9-NEXT: v_readlane_b32 s55, v63, 13 +; GFX9-NEXT: v_readlane_b32 s54, v63, 12 +; GFX9-NEXT: v_readlane_b32 s53, v63, 11 +; GFX9-NEXT: v_readlane_b32 s52, v63, 10 +; GFX9-NEXT: v_readlane_b32 s51, v63, 9 +; GFX9-NEXT: v_readlane_b32 s50, v63, 8 +; GFX9-NEXT: v_readlane_b32 s49, v63, 7 +; GFX9-NEXT: v_readlane_b32 s48, v63, 6 +; GFX9-NEXT: v_readlane_b32 s39, v63, 5 +; GFX9-NEXT: v_readlane_b32 s38, v63, 4 +; GFX9-NEXT: v_readlane_b32 s37, v63, 3 +; GFX9-NEXT: v_readlane_b32 s36, v63, 2 +; GFX9-NEXT: v_readlane_b32 s35, v63, 1 +; GFX9-NEXT: v_readlane_b32 s34, v63, 0 ; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5 ; GFX9-NEXT: v_or_b32_sdwa v5, v33, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -25942,18 +25942,18 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3 ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s34, 0 +; GFX11-NEXT: v_writelane_b32 v40, s35, 1 +; GFX11-NEXT: v_writelane_b32 v40, s36, 2 +; GFX11-NEXT: v_writelane_b32 v40, s37, 3 +; GFX11-NEXT: v_writelane_b32 v40, s38, 4 +; GFX11-NEXT: v_writelane_b32 v40, s39, 5 +; GFX11-NEXT: v_writelane_b32 v40, s48, 6 +; GFX11-NEXT: v_writelane_b32 v40, s49, 7 +; GFX11-NEXT: v_writelane_b32 v40, s30, 8 +; GFX11-NEXT: v_writelane_b32 v40, s31, 9 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_mov_b32 s42, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 -; GFX11-NEXT: v_writelane_b32 v40, s34, 2 -; GFX11-NEXT: v_writelane_b32 v40, s35, 3 -; GFX11-NEXT: v_writelane_b32 v40, s36, 4 -; GFX11-NEXT: v_writelane_b32 v40, s37, 5 -; GFX11-NEXT: v_writelane_b32 v40, s38, 6 -; GFX11-NEXT: v_writelane_b32 v40, s39, 7 -; GFX11-NEXT: v_writelane_b32 v40, s48, 8 -; GFX11-NEXT: v_writelane_b32 v40, s49, 9 ; GFX11-NEXT: s_cbranch_scc0 .LBB49_3 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s43, s27, 24 @@ -26301,21 +26301,21 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3 ; GFX11-NEXT: v_or_b32_e32 v2, v4, v10 ; GFX11-NEXT: v_or_b32_e32 v3, v11, v7 ; GFX11-NEXT: v_or_b32_e32 v4, v12, v8 +; GFX11-NEXT: v_readlane_b32 s30, v40, 8 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b128 v0, v[82:85], off ; GFX11-NEXT: scratch_store_b128 v0, v[23:26], off offset:16 ; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:32 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48 -; GFX11-NEXT: v_readlane_b32 s49, v40, 9 -; GFX11-NEXT: v_readlane_b32 s48, v40, 8 -; GFX11-NEXT: v_readlane_b32 s39, v40, 7 -; GFX11-NEXT: v_readlane_b32 s38, v40, 6 -; GFX11-NEXT: v_readlane_b32 s37, v40, 5 -; GFX11-NEXT: v_readlane_b32 s36, v40, 4 -; GFX11-NEXT: v_readlane_b32 s35, v40, 3 -; GFX11-NEXT: v_readlane_b32 s34, v40, 2 -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 -; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 9 +; GFX11-NEXT: v_readlane_b32 s49, v40, 7 +; GFX11-NEXT: v_readlane_b32 s48, v40, 6 +; GFX11-NEXT: v_readlane_b32 s39, v40, 5 +; GFX11-NEXT: v_readlane_b32 s38, v40, 4 +; GFX11-NEXT: v_readlane_b32 s37, v40, 3 +; GFX11-NEXT: v_readlane_b32 s36, v40, 2 +; GFX11-NEXT: v_readlane_b32 s35, v40, 1 +; GFX11-NEXT: v_readlane_b32 s34, v40, 0 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload ; GFX11-NEXT: s_mov_b32 exec_lo, s0 @@ -35963,8 +35963,8 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a, ; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v19, s30, 0 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_writelane_b32 v19, s31, 1 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_readfirstlane_b32 s30, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s31, v1 @@ -36282,8 +36282,8 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a, ; VI-NEXT: v_mov_b32_e32 v14, s30 ; VI-NEXT: v_mov_b32_e32 v15, s31 ; VI-NEXT: .LBB67_5: ; %end -; VI-NEXT: v_readlane_b32 s31, v19, 1 ; VI-NEXT: v_readlane_b32 s30, v19, 0 +; VI-NEXT: v_readlane_b32 s31, v19, 1 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -36297,8 +36297,8 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a, ; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: v_writelane_b32 v20, s30, 0 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_writelane_b32 v20, s31, 1 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_readfirstlane_b32 s30, v0 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s31, v1 @@ -36633,8 +36633,8 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a, ; GFX9-NEXT: v_mov_b32_e32 v14, s30 ; GFX9-NEXT: v_mov_b32_e32 v15, s31 ; GFX9-NEXT: .LBB67_5: ; %end -; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -37352,8 +37352,6 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v8i64_to_v64i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: ; implicit-def: $vgpr26 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -37370,6 +37368,8 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; SI-NEXT: ; implicit-def: $vgpr26 ; SI-NEXT: ; implicit-def: $vgpr58 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr46 @@ -37771,10 +37771,6 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) { ; VI-LABEL: bitcast_v8i64_to_v64i8: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; VI-NEXT: ; implicit-def: $vgpr17 -; VI-NEXT: ; kill: killed $vgpr17 -; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -37791,6 +37787,10 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; VI-NEXT: ; implicit-def: $vgpr17 +; VI-NEXT: ; kill: killed $vgpr17 +; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: ; implicit-def: $vgpr29 ; VI-NEXT: ; implicit-def: $vgpr27 ; VI-NEXT: ; implicit-def: $vgpr22 @@ -38102,10 +38102,6 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) { ; GFX9-LABEL: bitcast_v8i64_to_v64i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; GFX9-NEXT: ; implicit-def: $vgpr17 -; GFX9-NEXT: ; kill: killed $vgpr17 -; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -38122,6 +38118,10 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; GFX9-NEXT: ; implicit-def: $vgpr17 +; GFX9-NEXT: ; kill: killed $vgpr17 +; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: ; implicit-def: $vgpr29 ; GFX9-NEXT: ; implicit-def: $vgpr27 ; GFX9-NEXT: ; implicit-def: $vgpr23 @@ -39007,40 +39007,40 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in ; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v4, s30, 0 -; SI-NEXT: v_writelane_b32 v4, s31, 1 -; SI-NEXT: v_writelane_b32 v4, s34, 2 -; SI-NEXT: v_writelane_b32 v4, s35, 3 -; SI-NEXT: v_writelane_b32 v4, s36, 4 -; SI-NEXT: v_writelane_b32 v4, s37, 5 -; SI-NEXT: v_writelane_b32 v4, s38, 6 -; SI-NEXT: v_writelane_b32 v4, s39, 7 -; SI-NEXT: v_writelane_b32 v4, s48, 8 -; SI-NEXT: v_writelane_b32 v4, s49, 9 -; SI-NEXT: v_writelane_b32 v4, s50, 10 -; SI-NEXT: v_writelane_b32 v4, s51, 11 -; SI-NEXT: v_writelane_b32 v4, s52, 12 -; SI-NEXT: v_writelane_b32 v4, s53, 13 -; SI-NEXT: v_writelane_b32 v4, s54, 14 -; SI-NEXT: v_writelane_b32 v4, s55, 15 -; SI-NEXT: v_writelane_b32 v4, s64, 16 -; SI-NEXT: v_writelane_b32 v4, s65, 17 -; SI-NEXT: v_writelane_b32 v4, s66, 18 -; SI-NEXT: v_writelane_b32 v4, s67, 19 -; SI-NEXT: v_writelane_b32 v4, s68, 20 -; SI-NEXT: v_writelane_b32 v4, s69, 21 -; SI-NEXT: v_writelane_b32 v4, s70, 22 -; SI-NEXT: v_writelane_b32 v4, s71, 23 -; SI-NEXT: v_writelane_b32 v4, s80, 24 -; SI-NEXT: v_writelane_b32 v4, s81, 25 -; SI-NEXT: v_writelane_b32 v4, s82, 26 -; SI-NEXT: v_writelane_b32 v4, s83, 27 +; SI-NEXT: v_writelane_b32 v4, s34, 0 +; SI-NEXT: v_writelane_b32 v4, s35, 1 +; SI-NEXT: v_writelane_b32 v4, s36, 2 +; SI-NEXT: v_writelane_b32 v4, s37, 3 +; SI-NEXT: v_writelane_b32 v4, s38, 4 +; SI-NEXT: v_writelane_b32 v4, s39, 5 +; SI-NEXT: v_writelane_b32 v4, s48, 6 +; SI-NEXT: v_writelane_b32 v4, s49, 7 +; SI-NEXT: v_writelane_b32 v4, s50, 8 +; SI-NEXT: v_writelane_b32 v4, s51, 9 +; SI-NEXT: v_writelane_b32 v4, s52, 10 +; SI-NEXT: v_writelane_b32 v4, s53, 11 +; SI-NEXT: v_writelane_b32 v4, s54, 12 +; SI-NEXT: v_writelane_b32 v4, s55, 13 +; SI-NEXT: v_writelane_b32 v4, s64, 14 +; SI-NEXT: v_writelane_b32 v4, s65, 15 +; SI-NEXT: v_writelane_b32 v4, s66, 16 +; SI-NEXT: v_writelane_b32 v4, s67, 17 +; SI-NEXT: v_writelane_b32 v4, s68, 18 +; SI-NEXT: v_writelane_b32 v4, s69, 19 +; SI-NEXT: v_writelane_b32 v4, s70, 20 +; SI-NEXT: v_writelane_b32 v4, s71, 21 +; SI-NEXT: v_writelane_b32 v4, s80, 22 +; SI-NEXT: v_writelane_b32 v4, s81, 23 +; SI-NEXT: v_writelane_b32 v4, s82, 24 +; SI-NEXT: v_writelane_b32 v4, s83, 25 +; SI-NEXT: v_writelane_b32 v4, s84, 26 +; SI-NEXT: v_writelane_b32 v4, s85, 27 +; SI-NEXT: v_writelane_b32 v4, s30, 28 +; SI-NEXT: v_writelane_b32 v4, s31, 29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; SI-NEXT: v_writelane_b32 v4, s84, 28 ; SI-NEXT: v_readfirstlane_b32 s4, v1 ; SI-NEXT: s_and_b64 s[6:7], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v2 -; SI-NEXT: v_writelane_b32 v4, s85, 29 ; SI-NEXT: s_cbranch_scc0 .LBB69_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s38, s5, 24 @@ -39361,37 +39361,37 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v4, 28 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s85, v4, 29 -; SI-NEXT: v_readlane_b32 s84, v4, 28 -; SI-NEXT: v_readlane_b32 s83, v4, 27 -; SI-NEXT: v_readlane_b32 s82, v4, 26 -; SI-NEXT: v_readlane_b32 s81, v4, 25 -; SI-NEXT: v_readlane_b32 s80, v4, 24 -; SI-NEXT: v_readlane_b32 s71, v4, 23 -; SI-NEXT: v_readlane_b32 s70, v4, 22 -; SI-NEXT: v_readlane_b32 s69, v4, 21 -; SI-NEXT: v_readlane_b32 s68, v4, 20 -; SI-NEXT: v_readlane_b32 s67, v4, 19 -; SI-NEXT: v_readlane_b32 s66, v4, 18 -; SI-NEXT: v_readlane_b32 s65, v4, 17 -; SI-NEXT: v_readlane_b32 s64, v4, 16 -; SI-NEXT: v_readlane_b32 s55, v4, 15 -; SI-NEXT: v_readlane_b32 s54, v4, 14 -; SI-NEXT: v_readlane_b32 s53, v4, 13 -; SI-NEXT: v_readlane_b32 s52, v4, 12 -; SI-NEXT: v_readlane_b32 s51, v4, 11 -; SI-NEXT: v_readlane_b32 s50, v4, 10 -; SI-NEXT: v_readlane_b32 s49, v4, 9 -; SI-NEXT: v_readlane_b32 s48, v4, 8 -; SI-NEXT: v_readlane_b32 s39, v4, 7 -; SI-NEXT: v_readlane_b32 s38, v4, 6 -; SI-NEXT: v_readlane_b32 s37, v4, 5 -; SI-NEXT: v_readlane_b32 s36, v4, 4 -; SI-NEXT: v_readlane_b32 s35, v4, 3 -; SI-NEXT: v_readlane_b32 s34, v4, 2 -; SI-NEXT: v_readlane_b32 s31, v4, 1 -; SI-NEXT: v_readlane_b32 s30, v4, 0 +; SI-NEXT: v_readlane_b32 s31, v4, 29 +; SI-NEXT: v_readlane_b32 s85, v4, 27 +; SI-NEXT: v_readlane_b32 s84, v4, 26 +; SI-NEXT: v_readlane_b32 s83, v4, 25 +; SI-NEXT: v_readlane_b32 s82, v4, 24 +; SI-NEXT: v_readlane_b32 s81, v4, 23 +; SI-NEXT: v_readlane_b32 s80, v4, 22 +; SI-NEXT: v_readlane_b32 s71, v4, 21 +; SI-NEXT: v_readlane_b32 s70, v4, 20 +; SI-NEXT: v_readlane_b32 s69, v4, 19 +; SI-NEXT: v_readlane_b32 s68, v4, 18 +; SI-NEXT: v_readlane_b32 s67, v4, 17 +; SI-NEXT: v_readlane_b32 s66, v4, 16 +; SI-NEXT: v_readlane_b32 s65, v4, 15 +; SI-NEXT: v_readlane_b32 s64, v4, 14 +; SI-NEXT: v_readlane_b32 s55, v4, 13 +; SI-NEXT: v_readlane_b32 s54, v4, 12 +; SI-NEXT: v_readlane_b32 s53, v4, 11 +; SI-NEXT: v_readlane_b32 s52, v4, 10 +; SI-NEXT: v_readlane_b32 s51, v4, 9 +; SI-NEXT: v_readlane_b32 s50, v4, 8 +; SI-NEXT: v_readlane_b32 s49, v4, 7 +; SI-NEXT: v_readlane_b32 s48, v4, 6 +; SI-NEXT: v_readlane_b32 s39, v4, 5 +; SI-NEXT: v_readlane_b32 s38, v4, 4 +; SI-NEXT: v_readlane_b32 s37, v4, 3 +; SI-NEXT: v_readlane_b32 s36, v4, 2 +; SI-NEXT: v_readlane_b32 s35, v4, 1 +; SI-NEXT: v_readlane_b32 s34, v4, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -39454,30 +39454,30 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v4, s30, 0 -; VI-NEXT: v_writelane_b32 v4, s31, 1 -; VI-NEXT: v_writelane_b32 v4, s34, 2 -; VI-NEXT: v_writelane_b32 v4, s35, 3 -; VI-NEXT: v_writelane_b32 v4, s36, 4 -; VI-NEXT: v_writelane_b32 v4, s37, 5 -; VI-NEXT: v_writelane_b32 v4, s38, 6 -; VI-NEXT: v_writelane_b32 v4, s39, 7 -; VI-NEXT: v_writelane_b32 v4, s48, 8 -; VI-NEXT: v_writelane_b32 v4, s49, 9 -; VI-NEXT: v_writelane_b32 v4, s50, 10 -; VI-NEXT: v_writelane_b32 v4, s51, 11 -; VI-NEXT: v_writelane_b32 v4, s52, 12 -; VI-NEXT: v_writelane_b32 v4, s53, 13 -; VI-NEXT: v_writelane_b32 v4, s54, 14 -; VI-NEXT: v_writelane_b32 v4, s55, 15 -; VI-NEXT: v_writelane_b32 v4, s64, 16 -; VI-NEXT: v_writelane_b32 v4, s65, 17 +; VI-NEXT: v_writelane_b32 v4, s34, 0 +; VI-NEXT: v_writelane_b32 v4, s35, 1 +; VI-NEXT: v_writelane_b32 v4, s36, 2 +; VI-NEXT: v_writelane_b32 v4, s37, 3 +; VI-NEXT: v_writelane_b32 v4, s38, 4 +; VI-NEXT: v_writelane_b32 v4, s39, 5 +; VI-NEXT: v_writelane_b32 v4, s48, 6 +; VI-NEXT: v_writelane_b32 v4, s49, 7 +; VI-NEXT: v_writelane_b32 v4, s50, 8 +; VI-NEXT: v_writelane_b32 v4, s51, 9 +; VI-NEXT: v_writelane_b32 v4, s52, 10 +; VI-NEXT: v_writelane_b32 v4, s53, 11 +; VI-NEXT: v_writelane_b32 v4, s54, 12 +; VI-NEXT: v_writelane_b32 v4, s55, 13 +; VI-NEXT: v_writelane_b32 v4, s64, 14 +; VI-NEXT: v_writelane_b32 v4, s65, 15 +; VI-NEXT: v_writelane_b32 v4, s66, 16 +; VI-NEXT: v_writelane_b32 v4, s67, 17 +; VI-NEXT: v_writelane_b32 v4, s30, 18 +; VI-NEXT: v_writelane_b32 v4, s31, 19 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; VI-NEXT: v_writelane_b32 v4, s66, 18 ; VI-NEXT: v_readfirstlane_b32 s4, v1 ; VI-NEXT: s_and_b64 s[6:7], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v2 -; VI-NEXT: v_writelane_b32 v4, s67, 19 ; VI-NEXT: s_cbranch_scc0 .LBB69_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s56, s5, 24 @@ -39785,27 +39785,27 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0 ; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_readlane_b32 s30, v4, 18 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; VI-NEXT: v_readlane_b32 s67, v4, 19 -; VI-NEXT: v_readlane_b32 s66, v4, 18 -; VI-NEXT: v_readlane_b32 s65, v4, 17 -; VI-NEXT: v_readlane_b32 s64, v4, 16 -; VI-NEXT: v_readlane_b32 s55, v4, 15 -; VI-NEXT: v_readlane_b32 s54, v4, 14 -; VI-NEXT: v_readlane_b32 s53, v4, 13 -; VI-NEXT: v_readlane_b32 s52, v4, 12 -; VI-NEXT: v_readlane_b32 s51, v4, 11 -; VI-NEXT: v_readlane_b32 s50, v4, 10 -; VI-NEXT: v_readlane_b32 s49, v4, 9 -; VI-NEXT: v_readlane_b32 s48, v4, 8 -; VI-NEXT: v_readlane_b32 s39, v4, 7 -; VI-NEXT: v_readlane_b32 s38, v4, 6 -; VI-NEXT: v_readlane_b32 s37, v4, 5 -; VI-NEXT: v_readlane_b32 s36, v4, 4 -; VI-NEXT: v_readlane_b32 s35, v4, 3 -; VI-NEXT: v_readlane_b32 s34, v4, 2 -; VI-NEXT: v_readlane_b32 s31, v4, 1 -; VI-NEXT: v_readlane_b32 s30, v4, 0 +; VI-NEXT: v_readlane_b32 s31, v4, 19 +; VI-NEXT: v_readlane_b32 s67, v4, 17 +; VI-NEXT: v_readlane_b32 s66, v4, 16 +; VI-NEXT: v_readlane_b32 s65, v4, 15 +; VI-NEXT: v_readlane_b32 s64, v4, 14 +; VI-NEXT: v_readlane_b32 s55, v4, 13 +; VI-NEXT: v_readlane_b32 s54, v4, 12 +; VI-NEXT: v_readlane_b32 s53, v4, 11 +; VI-NEXT: v_readlane_b32 s52, v4, 10 +; VI-NEXT: v_readlane_b32 s51, v4, 9 +; VI-NEXT: v_readlane_b32 s50, v4, 8 +; VI-NEXT: v_readlane_b32 s49, v4, 7 +; VI-NEXT: v_readlane_b32 s48, v4, 6 +; VI-NEXT: v_readlane_b32 s39, v4, 5 +; VI-NEXT: v_readlane_b32 s38, v4, 4 +; VI-NEXT: v_readlane_b32 s37, v4, 3 +; VI-NEXT: v_readlane_b32 s36, v4, 2 +; VI-NEXT: v_readlane_b32 s35, v4, 1 +; VI-NEXT: v_readlane_b32 s34, v4, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -39868,26 +39868,26 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v4, s30, 0 -; GFX9-NEXT: v_writelane_b32 v4, s31, 1 -; GFX9-NEXT: v_writelane_b32 v4, s34, 2 -; GFX9-NEXT: v_writelane_b32 v4, s35, 3 -; GFX9-NEXT: v_writelane_b32 v4, s36, 4 -; GFX9-NEXT: v_writelane_b32 v4, s37, 5 -; GFX9-NEXT: v_writelane_b32 v4, s38, 6 -; GFX9-NEXT: v_writelane_b32 v4, s39, 7 -; GFX9-NEXT: v_writelane_b32 v4, s48, 8 -; GFX9-NEXT: v_writelane_b32 v4, s49, 9 -; GFX9-NEXT: v_writelane_b32 v4, s50, 10 -; GFX9-NEXT: v_writelane_b32 v4, s51, 11 -; GFX9-NEXT: v_writelane_b32 v4, s52, 12 -; GFX9-NEXT: v_writelane_b32 v4, s53, 13 +; GFX9-NEXT: v_writelane_b32 v4, s34, 0 +; GFX9-NEXT: v_writelane_b32 v4, s35, 1 +; GFX9-NEXT: v_writelane_b32 v4, s36, 2 +; GFX9-NEXT: v_writelane_b32 v4, s37, 3 +; GFX9-NEXT: v_writelane_b32 v4, s38, 4 +; GFX9-NEXT: v_writelane_b32 v4, s39, 5 +; GFX9-NEXT: v_writelane_b32 v4, s48, 6 +; GFX9-NEXT: v_writelane_b32 v4, s49, 7 +; GFX9-NEXT: v_writelane_b32 v4, s50, 8 +; GFX9-NEXT: v_writelane_b32 v4, s51, 9 +; GFX9-NEXT: v_writelane_b32 v4, s52, 10 +; GFX9-NEXT: v_writelane_b32 v4, s53, 11 +; GFX9-NEXT: v_writelane_b32 v4, s54, 12 +; GFX9-NEXT: v_writelane_b32 v4, s55, 13 +; GFX9-NEXT: v_writelane_b32 v4, s30, 14 +; GFX9-NEXT: v_writelane_b32 v4, s31, 15 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: v_writelane_b32 v4, s54, 14 ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 ; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v2 -; GFX9-NEXT: v_writelane_b32 v4, s55, 15 ; GFX9-NEXT: s_cbranch_scc0 .LBB69_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s56, s5, 24 @@ -40180,23 +40180,23 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in ; GFX9-NEXT: s_or_b32 s4, s4, s5 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_readlane_b32 s30, v4, 14 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60 -; GFX9-NEXT: v_readlane_b32 s55, v4, 15 -; GFX9-NEXT: v_readlane_b32 s54, v4, 14 -; GFX9-NEXT: v_readlane_b32 s53, v4, 13 -; GFX9-NEXT: v_readlane_b32 s52, v4, 12 -; GFX9-NEXT: v_readlane_b32 s51, v4, 11 -; GFX9-NEXT: v_readlane_b32 s50, v4, 10 -; GFX9-NEXT: v_readlane_b32 s49, v4, 9 -; GFX9-NEXT: v_readlane_b32 s48, v4, 8 -; GFX9-NEXT: v_readlane_b32 s39, v4, 7 -; GFX9-NEXT: v_readlane_b32 s38, v4, 6 -; GFX9-NEXT: v_readlane_b32 s37, v4, 5 -; GFX9-NEXT: v_readlane_b32 s36, v4, 4 -; GFX9-NEXT: v_readlane_b32 s35, v4, 3 -; GFX9-NEXT: v_readlane_b32 s34, v4, 2 -; GFX9-NEXT: v_readlane_b32 s31, v4, 1 -; GFX9-NEXT: v_readlane_b32 s30, v4, 0 +; GFX9-NEXT: v_readlane_b32 s31, v4, 15 +; GFX9-NEXT: v_readlane_b32 s55, v4, 13 +; GFX9-NEXT: v_readlane_b32 s54, v4, 12 +; GFX9-NEXT: v_readlane_b32 s53, v4, 11 +; GFX9-NEXT: v_readlane_b32 s52, v4, 10 +; GFX9-NEXT: v_readlane_b32 s51, v4, 9 +; GFX9-NEXT: v_readlane_b32 s50, v4, 8 +; GFX9-NEXT: v_readlane_b32 s49, v4, 7 +; GFX9-NEXT: v_readlane_b32 s48, v4, 6 +; GFX9-NEXT: v_readlane_b32 s39, v4, 5 +; GFX9-NEXT: v_readlane_b32 s38, v4, 4 +; GFX9-NEXT: v_readlane_b32 s37, v4, 3 +; GFX9-NEXT: v_readlane_b32 s36, v4, 2 +; GFX9-NEXT: v_readlane_b32 s35, v4, 1 +; GFX9-NEXT: v_readlane_b32 s34, v4, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -40259,17 +40259,17 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in ; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX11-NEXT: scratch_store_b32 off, v17, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v17, s30, 0 +; GFX11-NEXT: v_writelane_b32 v17, s34, 0 +; GFX11-NEXT: v_writelane_b32 v17, s35, 1 +; GFX11-NEXT: v_writelane_b32 v17, s36, 2 +; GFX11-NEXT: v_writelane_b32 v17, s37, 3 +; GFX11-NEXT: v_writelane_b32 v17, s38, 4 +; GFX11-NEXT: v_writelane_b32 v17, s39, 5 +; GFX11-NEXT: v_writelane_b32 v17, s48, 6 +; GFX11-NEXT: v_writelane_b32 v17, s30, 7 +; GFX11-NEXT: v_writelane_b32 v17, s31, 8 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_mov_b32 vcc_lo, 0 -; GFX11-NEXT: v_writelane_b32 v17, s31, 1 -; GFX11-NEXT: v_writelane_b32 v17, s34, 2 -; GFX11-NEXT: v_writelane_b32 v17, s35, 3 -; GFX11-NEXT: v_writelane_b32 v17, s36, 4 -; GFX11-NEXT: v_writelane_b32 v17, s37, 5 -; GFX11-NEXT: v_writelane_b32 v17, s38, 6 -; GFX11-NEXT: v_writelane_b32 v17, s39, 7 -; GFX11-NEXT: v_writelane_b32 v17, s48, 8 ; GFX11-NEXT: s_cbranch_scc0 .LBB69_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s42, s27, 24 @@ -40540,20 +40540,20 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in ; GFX11-NEXT: s_or_b32 s3, s4, s5 ; GFX11-NEXT: v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v14, s1 ; GFX11-NEXT: v_dual_mov_b32 v15, s2 :: v_dual_mov_b32 v16, s3 +; GFX11-NEXT: v_readlane_b32 s30, v17, 7 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16 ; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32 ; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:48 -; GFX11-NEXT: v_readlane_b32 s48, v17, 8 -; GFX11-NEXT: v_readlane_b32 s39, v17, 7 -; GFX11-NEXT: v_readlane_b32 s38, v17, 6 -; GFX11-NEXT: v_readlane_b32 s37, v17, 5 -; GFX11-NEXT: v_readlane_b32 s36, v17, 4 -; GFX11-NEXT: v_readlane_b32 s35, v17, 3 -; GFX11-NEXT: v_readlane_b32 s34, v17, 2 -; GFX11-NEXT: v_readlane_b32 s31, v17, 1 -; GFX11-NEXT: v_readlane_b32 s30, v17, 0 +; GFX11-NEXT: v_readlane_b32 s31, v17, 8 +; GFX11-NEXT: v_readlane_b32 s48, v17, 6 +; GFX11-NEXT: v_readlane_b32 s39, v17, 5 +; GFX11-NEXT: v_readlane_b32 s38, v17, 4 +; GFX11-NEXT: v_readlane_b32 s37, v17, 3 +; GFX11-NEXT: v_readlane_b32 s36, v17, 2 +; GFX11-NEXT: v_readlane_b32 s35, v17, 1 +; GFX11-NEXT: v_readlane_b32 s34, v17, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v17, off, s32 ; 4-byte Folded Reload ; GFX11-NEXT: s_mov_b32 exec_lo, s0 @@ -49422,8 +49422,8 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg % ; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v19, s30, 0 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_writelane_b32 v19, s31, 1 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_readfirstlane_b32 s30, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s31, v1 @@ -49741,8 +49741,8 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg % ; VI-NEXT: v_mov_b32_e32 v14, s30 ; VI-NEXT: v_mov_b32_e32 v15, s31 ; VI-NEXT: .LBB83_5: ; %end -; VI-NEXT: v_readlane_b32 s31, v19, 1 ; VI-NEXT: v_readlane_b32 s30, v19, 0 +; VI-NEXT: v_readlane_b32 s31, v19, 1 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -49756,8 +49756,8 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg % ; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: v_writelane_b32 v20, s30, 0 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_writelane_b32 v20, s31, 1 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_readfirstlane_b32 s30, v0 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s31, v1 @@ -50092,8 +50092,8 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg % ; GFX9-NEXT: v_mov_b32_e32 v14, s30 ; GFX9-NEXT: v_mov_b32_e32 v15, s31 ; GFX9-NEXT: .LBB83_5: ; %end -; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -50811,8 +50811,6 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v8f64_to_v64i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: ; implicit-def: $vgpr26 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -50829,6 +50827,8 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; SI-NEXT: ; implicit-def: $vgpr26 ; SI-NEXT: ; implicit-def: $vgpr58 ; SI-NEXT: ; implicit-def: $vgpr57 ; SI-NEXT: ; implicit-def: $vgpr47 @@ -51222,10 +51222,6 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) { ; VI-LABEL: bitcast_v8f64_to_v64i8: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; VI-NEXT: ; implicit-def: $vgpr17 -; VI-NEXT: ; kill: killed $vgpr17 -; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -51242,6 +51238,10 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; VI-NEXT: ; implicit-def: $vgpr17 +; VI-NEXT: ; kill: killed $vgpr17 +; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: ; implicit-def: $vgpr29 ; VI-NEXT: ; implicit-def: $vgpr27 ; VI-NEXT: ; implicit-def: $vgpr22 @@ -51545,10 +51545,6 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) { ; GFX9-LABEL: bitcast_v8f64_to_v64i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; GFX9-NEXT: ; implicit-def: $vgpr17 -; GFX9-NEXT: ; kill: killed $vgpr17 -; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -51565,6 +51561,10 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; GFX9-NEXT: ; implicit-def: $vgpr17 +; GFX9-NEXT: ; kill: killed $vgpr17 +; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: ; implicit-def: $vgpr29 ; GFX9-NEXT: ; implicit-def: $vgpr27 ; GFX9-NEXT: ; implicit-def: $vgpr23 @@ -52416,42 +52416,42 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v40, s30, 0 -; SI-NEXT: v_writelane_b32 v40, s31, 1 -; SI-NEXT: v_writelane_b32 v40, s34, 2 -; SI-NEXT: v_writelane_b32 v40, s35, 3 -; SI-NEXT: v_writelane_b32 v40, s36, 4 -; SI-NEXT: v_writelane_b32 v40, s37, 5 -; SI-NEXT: v_writelane_b32 v40, s38, 6 -; SI-NEXT: v_writelane_b32 v40, s39, 7 -; SI-NEXT: v_writelane_b32 v40, s48, 8 -; SI-NEXT: v_writelane_b32 v40, s49, 9 -; SI-NEXT: v_writelane_b32 v40, s50, 10 -; SI-NEXT: v_writelane_b32 v40, s51, 11 -; SI-NEXT: v_writelane_b32 v40, s52, 12 -; SI-NEXT: v_writelane_b32 v40, s53, 13 -; SI-NEXT: v_writelane_b32 v40, s54, 14 -; SI-NEXT: v_writelane_b32 v40, s55, 15 -; SI-NEXT: v_writelane_b32 v40, s64, 16 -; SI-NEXT: v_writelane_b32 v40, s65, 17 -; SI-NEXT: v_writelane_b32 v40, s66, 18 -; SI-NEXT: v_writelane_b32 v40, s67, 19 -; SI-NEXT: v_writelane_b32 v40, s68, 20 -; SI-NEXT: v_writelane_b32 v40, s69, 21 -; SI-NEXT: v_writelane_b32 v40, s70, 22 -; SI-NEXT: v_writelane_b32 v40, s71, 23 -; SI-NEXT: v_writelane_b32 v40, s80, 24 -; SI-NEXT: v_writelane_b32 v40, s81, 25 -; SI-NEXT: v_writelane_b32 v40, s82, 26 -; SI-NEXT: v_writelane_b32 v40, s83, 27 -; SI-NEXT: v_writelane_b32 v40, s84, 28 -; SI-NEXT: v_writelane_b32 v40, s85, 29 +; SI-NEXT: v_writelane_b32 v40, s34, 0 +; SI-NEXT: v_writelane_b32 v40, s35, 1 +; SI-NEXT: v_writelane_b32 v40, s36, 2 +; SI-NEXT: v_writelane_b32 v40, s37, 3 +; SI-NEXT: v_writelane_b32 v40, s38, 4 +; SI-NEXT: v_writelane_b32 v40, s39, 5 +; SI-NEXT: v_writelane_b32 v40, s48, 6 +; SI-NEXT: v_writelane_b32 v40, s49, 7 +; SI-NEXT: v_writelane_b32 v40, s50, 8 +; SI-NEXT: v_writelane_b32 v40, s51, 9 +; SI-NEXT: v_writelane_b32 v40, s52, 10 +; SI-NEXT: v_writelane_b32 v40, s53, 11 +; SI-NEXT: v_writelane_b32 v40, s54, 12 +; SI-NEXT: v_writelane_b32 v40, s55, 13 +; SI-NEXT: v_writelane_b32 v40, s64, 14 +; SI-NEXT: v_writelane_b32 v40, s65, 15 +; SI-NEXT: v_writelane_b32 v40, s66, 16 +; SI-NEXT: v_writelane_b32 v40, s67, 17 +; SI-NEXT: v_writelane_b32 v40, s68, 18 +; SI-NEXT: v_writelane_b32 v40, s69, 19 +; SI-NEXT: v_writelane_b32 v40, s70, 20 +; SI-NEXT: v_writelane_b32 v40, s71, 21 +; SI-NEXT: v_writelane_b32 v40, s80, 22 +; SI-NEXT: v_writelane_b32 v40, s81, 23 +; SI-NEXT: v_writelane_b32 v40, s82, 24 +; SI-NEXT: v_writelane_b32 v40, s83, 25 +; SI-NEXT: v_writelane_b32 v40, s84, 26 +; SI-NEXT: v_writelane_b32 v40, s85, 27 +; SI-NEXT: v_writelane_b32 v40, s86, 28 +; SI-NEXT: v_writelane_b32 v40, s87, 29 +; SI-NEXT: v_writelane_b32 v40, s30, 30 +; SI-NEXT: v_writelane_b32 v40, s31, 31 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; SI-NEXT: v_writelane_b32 v40, s86, 30 ; SI-NEXT: v_readfirstlane_b32 s4, v1 ; SI-NEXT: s_and_b64 s[6:7], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v2 -; SI-NEXT: v_writelane_b32 v40, s87, 31 ; SI-NEXT: s_cbranch_scc0 .LBB85_3 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s48, s5, 24 @@ -52850,39 +52850,39 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32 ; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v40, 30 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s87, v40, 31 -; SI-NEXT: v_readlane_b32 s86, v40, 30 -; SI-NEXT: v_readlane_b32 s85, v40, 29 -; SI-NEXT: v_readlane_b32 s84, v40, 28 -; SI-NEXT: v_readlane_b32 s83, v40, 27 -; SI-NEXT: v_readlane_b32 s82, v40, 26 -; SI-NEXT: v_readlane_b32 s81, v40, 25 -; SI-NEXT: v_readlane_b32 s80, v40, 24 -; SI-NEXT: v_readlane_b32 s71, v40, 23 -; SI-NEXT: v_readlane_b32 s70, v40, 22 -; SI-NEXT: v_readlane_b32 s69, v40, 21 -; SI-NEXT: v_readlane_b32 s68, v40, 20 -; SI-NEXT: v_readlane_b32 s67, v40, 19 -; SI-NEXT: v_readlane_b32 s66, v40, 18 -; SI-NEXT: v_readlane_b32 s65, v40, 17 -; SI-NEXT: v_readlane_b32 s64, v40, 16 -; SI-NEXT: v_readlane_b32 s55, v40, 15 -; SI-NEXT: v_readlane_b32 s54, v40, 14 -; SI-NEXT: v_readlane_b32 s53, v40, 13 -; SI-NEXT: v_readlane_b32 s52, v40, 12 -; SI-NEXT: v_readlane_b32 s51, v40, 11 -; SI-NEXT: v_readlane_b32 s50, v40, 10 -; SI-NEXT: v_readlane_b32 s49, v40, 9 -; SI-NEXT: v_readlane_b32 s48, v40, 8 -; SI-NEXT: v_readlane_b32 s39, v40, 7 -; SI-NEXT: v_readlane_b32 s38, v40, 6 -; SI-NEXT: v_readlane_b32 s37, v40, 5 -; SI-NEXT: v_readlane_b32 s36, v40, 4 -; SI-NEXT: v_readlane_b32 s35, v40, 3 -; SI-NEXT: v_readlane_b32 s34, v40, 2 -; SI-NEXT: v_readlane_b32 s31, v40, 1 -; SI-NEXT: v_readlane_b32 s30, v40, 0 +; SI-NEXT: v_readlane_b32 s31, v40, 31 +; SI-NEXT: v_readlane_b32 s87, v40, 29 +; SI-NEXT: v_readlane_b32 s86, v40, 28 +; SI-NEXT: v_readlane_b32 s85, v40, 27 +; SI-NEXT: v_readlane_b32 s84, v40, 26 +; SI-NEXT: v_readlane_b32 s83, v40, 25 +; SI-NEXT: v_readlane_b32 s82, v40, 24 +; SI-NEXT: v_readlane_b32 s81, v40, 23 +; SI-NEXT: v_readlane_b32 s80, v40, 22 +; SI-NEXT: v_readlane_b32 s71, v40, 21 +; SI-NEXT: v_readlane_b32 s70, v40, 20 +; SI-NEXT: v_readlane_b32 s69, v40, 19 +; SI-NEXT: v_readlane_b32 s68, v40, 18 +; SI-NEXT: v_readlane_b32 s67, v40, 17 +; SI-NEXT: v_readlane_b32 s66, v40, 16 +; SI-NEXT: v_readlane_b32 s65, v40, 15 +; SI-NEXT: v_readlane_b32 s64, v40, 14 +; SI-NEXT: v_readlane_b32 s55, v40, 13 +; SI-NEXT: v_readlane_b32 s54, v40, 12 +; SI-NEXT: v_readlane_b32 s53, v40, 11 +; SI-NEXT: v_readlane_b32 s52, v40, 10 +; SI-NEXT: v_readlane_b32 s51, v40, 9 +; SI-NEXT: v_readlane_b32 s50, v40, 8 +; SI-NEXT: v_readlane_b32 s49, v40, 7 +; SI-NEXT: v_readlane_b32 s48, v40, 6 +; SI-NEXT: v_readlane_b32 s39, v40, 5 +; SI-NEXT: v_readlane_b32 s38, v40, 4 +; SI-NEXT: v_readlane_b32 s37, v40, 3 +; SI-NEXT: v_readlane_b32 s36, v40, 2 +; SI-NEXT: v_readlane_b32 s35, v40, 1 +; SI-NEXT: v_readlane_b32 s34, v40, 0 ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -52895,30 +52895,30 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32 ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v40, s30, 0 -; VI-NEXT: v_writelane_b32 v40, s31, 1 -; VI-NEXT: v_writelane_b32 v40, s34, 2 -; VI-NEXT: v_writelane_b32 v40, s35, 3 -; VI-NEXT: v_writelane_b32 v40, s36, 4 -; VI-NEXT: v_writelane_b32 v40, s37, 5 -; VI-NEXT: v_writelane_b32 v40, s38, 6 -; VI-NEXT: v_writelane_b32 v40, s39, 7 -; VI-NEXT: v_writelane_b32 v40, s48, 8 -; VI-NEXT: v_writelane_b32 v40, s49, 9 -; VI-NEXT: v_writelane_b32 v40, s50, 10 -; VI-NEXT: v_writelane_b32 v40, s51, 11 -; VI-NEXT: v_writelane_b32 v40, s52, 12 -; VI-NEXT: v_writelane_b32 v40, s53, 13 -; VI-NEXT: v_writelane_b32 v40, s54, 14 -; VI-NEXT: v_writelane_b32 v40, s55, 15 -; VI-NEXT: v_writelane_b32 v40, s64, 16 -; VI-NEXT: v_writelane_b32 v40, s65, 17 +; VI-NEXT: v_writelane_b32 v40, s34, 0 +; VI-NEXT: v_writelane_b32 v40, s35, 1 +; VI-NEXT: v_writelane_b32 v40, s36, 2 +; VI-NEXT: v_writelane_b32 v40, s37, 3 +; VI-NEXT: v_writelane_b32 v40, s38, 4 +; VI-NEXT: v_writelane_b32 v40, s39, 5 +; VI-NEXT: v_writelane_b32 v40, s48, 6 +; VI-NEXT: v_writelane_b32 v40, s49, 7 +; VI-NEXT: v_writelane_b32 v40, s50, 8 +; VI-NEXT: v_writelane_b32 v40, s51, 9 +; VI-NEXT: v_writelane_b32 v40, s52, 10 +; VI-NEXT: v_writelane_b32 v40, s53, 11 +; VI-NEXT: v_writelane_b32 v40, s54, 12 +; VI-NEXT: v_writelane_b32 v40, s55, 13 +; VI-NEXT: v_writelane_b32 v40, s64, 14 +; VI-NEXT: v_writelane_b32 v40, s65, 15 +; VI-NEXT: v_writelane_b32 v40, s66, 16 +; VI-NEXT: v_writelane_b32 v40, s67, 17 +; VI-NEXT: v_writelane_b32 v40, s30, 18 +; VI-NEXT: v_writelane_b32 v40, s31, 19 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; VI-NEXT: v_writelane_b32 v40, s66, 18 ; VI-NEXT: v_readfirstlane_b32 s4, v1 ; VI-NEXT: s_and_b64 s[6:7], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v2 -; VI-NEXT: v_writelane_b32 v40, s67, 19 ; VI-NEXT: s_cbranch_scc0 .LBB85_3 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s56, s5, 24 @@ -53270,27 +53270,27 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0 ; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_readlane_b32 s30, v40, 18 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; VI-NEXT: v_readlane_b32 s67, v40, 19 -; VI-NEXT: v_readlane_b32 s66, v40, 18 -; VI-NEXT: v_readlane_b32 s65, v40, 17 -; VI-NEXT: v_readlane_b32 s64, v40, 16 -; VI-NEXT: v_readlane_b32 s55, v40, 15 -; VI-NEXT: v_readlane_b32 s54, v40, 14 -; VI-NEXT: v_readlane_b32 s53, v40, 13 -; VI-NEXT: v_readlane_b32 s52, v40, 12 -; VI-NEXT: v_readlane_b32 s51, v40, 11 -; VI-NEXT: v_readlane_b32 s50, v40, 10 -; VI-NEXT: v_readlane_b32 s49, v40, 9 -; VI-NEXT: v_readlane_b32 s48, v40, 8 -; VI-NEXT: v_readlane_b32 s39, v40, 7 -; VI-NEXT: v_readlane_b32 s38, v40, 6 -; VI-NEXT: v_readlane_b32 s37, v40, 5 -; VI-NEXT: v_readlane_b32 s36, v40, 4 -; VI-NEXT: v_readlane_b32 s35, v40, 3 -; VI-NEXT: v_readlane_b32 s34, v40, 2 -; VI-NEXT: v_readlane_b32 s31, v40, 1 -; VI-NEXT: v_readlane_b32 s30, v40, 0 +; VI-NEXT: v_readlane_b32 s31, v40, 19 +; VI-NEXT: v_readlane_b32 s67, v40, 17 +; VI-NEXT: v_readlane_b32 s66, v40, 16 +; VI-NEXT: v_readlane_b32 s65, v40, 15 +; VI-NEXT: v_readlane_b32 s64, v40, 14 +; VI-NEXT: v_readlane_b32 s55, v40, 13 +; VI-NEXT: v_readlane_b32 s54, v40, 12 +; VI-NEXT: v_readlane_b32 s53, v40, 11 +; VI-NEXT: v_readlane_b32 s52, v40, 10 +; VI-NEXT: v_readlane_b32 s51, v40, 9 +; VI-NEXT: v_readlane_b32 s50, v40, 8 +; VI-NEXT: v_readlane_b32 s49, v40, 7 +; VI-NEXT: v_readlane_b32 s48, v40, 6 +; VI-NEXT: v_readlane_b32 s39, v40, 5 +; VI-NEXT: v_readlane_b32 s38, v40, 4 +; VI-NEXT: v_readlane_b32 s37, v40, 3 +; VI-NEXT: v_readlane_b32 s36, v40, 2 +; VI-NEXT: v_readlane_b32 s35, v40, 1 +; VI-NEXT: v_readlane_b32 s34, v40, 0 ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -53303,26 +53303,26 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: v_writelane_b32 v40, s35, 3 -; GFX9-NEXT: v_writelane_b32 v40, s36, 4 -; GFX9-NEXT: v_writelane_b32 v40, s37, 5 -; GFX9-NEXT: v_writelane_b32 v40, s38, 6 -; GFX9-NEXT: v_writelane_b32 v40, s39, 7 -; GFX9-NEXT: v_writelane_b32 v40, s48, 8 -; GFX9-NEXT: v_writelane_b32 v40, s49, 9 -; GFX9-NEXT: v_writelane_b32 v40, s50, 10 -; GFX9-NEXT: v_writelane_b32 v40, s51, 11 -; GFX9-NEXT: v_writelane_b32 v40, s52, 12 -; GFX9-NEXT: v_writelane_b32 v40, s53, 13 +; GFX9-NEXT: v_writelane_b32 v40, s34, 0 +; GFX9-NEXT: v_writelane_b32 v40, s35, 1 +; GFX9-NEXT: v_writelane_b32 v40, s36, 2 +; GFX9-NEXT: v_writelane_b32 v40, s37, 3 +; GFX9-NEXT: v_writelane_b32 v40, s38, 4 +; GFX9-NEXT: v_writelane_b32 v40, s39, 5 +; GFX9-NEXT: v_writelane_b32 v40, s48, 6 +; GFX9-NEXT: v_writelane_b32 v40, s49, 7 +; GFX9-NEXT: v_writelane_b32 v40, s50, 8 +; GFX9-NEXT: v_writelane_b32 v40, s51, 9 +; GFX9-NEXT: v_writelane_b32 v40, s52, 10 +; GFX9-NEXT: v_writelane_b32 v40, s53, 11 +; GFX9-NEXT: v_writelane_b32 v40, s54, 12 +; GFX9-NEXT: v_writelane_b32 v40, s55, 13 +; GFX9-NEXT: v_writelane_b32 v40, s30, 14 +; GFX9-NEXT: v_writelane_b32 v40, s31, 15 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: v_writelane_b32 v40, s54, 14 ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 ; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v2 -; GFX9-NEXT: v_writelane_b32 v40, s55, 15 ; GFX9-NEXT: s_cbranch_scc0 .LBB85_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s56, s5, 24 @@ -53659,23 +53659,23 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32 ; GFX9-NEXT: s_or_b32 s4, s4, s5 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_readlane_b32 s30, v40, 14 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60 -; GFX9-NEXT: v_readlane_b32 s55, v40, 15 -; GFX9-NEXT: v_readlane_b32 s54, v40, 14 -; GFX9-NEXT: v_readlane_b32 s53, v40, 13 -; GFX9-NEXT: v_readlane_b32 s52, v40, 12 -; GFX9-NEXT: v_readlane_b32 s51, v40, 11 -; GFX9-NEXT: v_readlane_b32 s50, v40, 10 -; GFX9-NEXT: v_readlane_b32 s49, v40, 9 -; GFX9-NEXT: v_readlane_b32 s48, v40, 8 -; GFX9-NEXT: v_readlane_b32 s39, v40, 7 -; GFX9-NEXT: v_readlane_b32 s38, v40, 6 -; GFX9-NEXT: v_readlane_b32 s37, v40, 5 -; GFX9-NEXT: v_readlane_b32 s36, v40, 4 -; GFX9-NEXT: v_readlane_b32 s35, v40, 3 -; GFX9-NEXT: v_readlane_b32 s34, v40, 2 -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 -; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 15 +; GFX9-NEXT: v_readlane_b32 s55, v40, 13 +; GFX9-NEXT: v_readlane_b32 s54, v40, 12 +; GFX9-NEXT: v_readlane_b32 s53, v40, 11 +; GFX9-NEXT: v_readlane_b32 s52, v40, 10 +; GFX9-NEXT: v_readlane_b32 s51, v40, 9 +; GFX9-NEXT: v_readlane_b32 s50, v40, 8 +; GFX9-NEXT: v_readlane_b32 s49, v40, 7 +; GFX9-NEXT: v_readlane_b32 s48, v40, 6 +; GFX9-NEXT: v_readlane_b32 s39, v40, 5 +; GFX9-NEXT: v_readlane_b32 s38, v40, 4 +; GFX9-NEXT: v_readlane_b32 s37, v40, 3 +; GFX9-NEXT: v_readlane_b32 s36, v40, 2 +; GFX9-NEXT: v_readlane_b32 s35, v40, 1 +; GFX9-NEXT: v_readlane_b32 s34, v40, 0 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -53688,18 +53688,18 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32 ; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX11-NEXT: scratch_store_b32 off, v33, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v33, s30, 0 +; GFX11-NEXT: v_writelane_b32 v33, s34, 0 +; GFX11-NEXT: v_writelane_b32 v33, s35, 1 +; GFX11-NEXT: v_writelane_b32 v33, s36, 2 +; GFX11-NEXT: v_writelane_b32 v33, s37, 3 +; GFX11-NEXT: v_writelane_b32 v33, s38, 4 +; GFX11-NEXT: v_writelane_b32 v33, s39, 5 +; GFX11-NEXT: v_writelane_b32 v33, s48, 6 +; GFX11-NEXT: v_writelane_b32 v33, s49, 7 +; GFX11-NEXT: v_writelane_b32 v33, s30, 8 +; GFX11-NEXT: v_writelane_b32 v33, s31, 9 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_mov_b32 s90, 0 -; GFX11-NEXT: v_writelane_b32 v33, s31, 1 -; GFX11-NEXT: v_writelane_b32 v33, s34, 2 -; GFX11-NEXT: v_writelane_b32 v33, s35, 3 -; GFX11-NEXT: v_writelane_b32 v33, s36, 4 -; GFX11-NEXT: v_writelane_b32 v33, s37, 5 -; GFX11-NEXT: v_writelane_b32 v33, s38, 6 -; GFX11-NEXT: v_writelane_b32 v33, s39, 7 -; GFX11-NEXT: v_writelane_b32 v33, s48, 8 -; GFX11-NEXT: v_writelane_b32 v33, s49, 9 ; GFX11-NEXT: s_cbranch_scc0 .LBB85_3 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s42, s27, 24 @@ -54037,21 +54037,21 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32 ; GFX11-NEXT: v_or_b32_e32 v3, v3, v2 ; GFX11-NEXT: v_mov_b32_e32 v2, s0 ; GFX11-NEXT: v_mov_b32_e32 v4, s1 +; GFX11-NEXT: v_readlane_b32 s30, v33, 8 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b128 v0, v[22:25], off ; GFX11-NEXT: scratch_store_b128 v0, v[14:17], off offset:16 ; GFX11-NEXT: scratch_store_b128 v0, v[10:13], off offset:32 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48 -; GFX11-NEXT: v_readlane_b32 s49, v33, 9 -; GFX11-NEXT: v_readlane_b32 s48, v33, 8 -; GFX11-NEXT: v_readlane_b32 s39, v33, 7 -; GFX11-NEXT: v_readlane_b32 s38, v33, 6 -; GFX11-NEXT: v_readlane_b32 s37, v33, 5 -; GFX11-NEXT: v_readlane_b32 s36, v33, 4 -; GFX11-NEXT: v_readlane_b32 s35, v33, 3 -; GFX11-NEXT: v_readlane_b32 s34, v33, 2 -; GFX11-NEXT: v_readlane_b32 s31, v33, 1 -; GFX11-NEXT: v_readlane_b32 s30, v33, 0 +; GFX11-NEXT: v_readlane_b32 s31, v33, 9 +; GFX11-NEXT: v_readlane_b32 s49, v33, 7 +; GFX11-NEXT: v_readlane_b32 s48, v33, 6 +; GFX11-NEXT: v_readlane_b32 s39, v33, 5 +; GFX11-NEXT: v_readlane_b32 s38, v33, 4 +; GFX11-NEXT: v_readlane_b32 s37, v33, 3 +; GFX11-NEXT: v_readlane_b32 s36, v33, 2 +; GFX11-NEXT: v_readlane_b32 s35, v33, 1 +; GFX11-NEXT: v_readlane_b32 s34, v33, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v33, off, s32 ; 4-byte Folded Reload ; GFX11-NEXT: s_mov_b32 exec_lo, s0 @@ -58733,9 +58733,9 @@ define inreg <32 x half> @bitcast_v32i16_to_v32f16_scalar(<32 x i16> inreg %a, i ; SI-LABEL: bitcast_v32i16_to_v32f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; SI-NEXT: v_mov_b32_e32 v54, v17 ; SI-NEXT: v_mov_b32_e32 v53, v16 ; SI-NEXT: v_mov_b32_e32 v52, v15 @@ -61978,7 +61978,6 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a ; SI-LABEL: bitcast_v32bf16_to_v32i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -61995,6 +61994,7 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: s_waitcnt expcnt(6) ; SI-NEXT: v_mul_f32_e64 v57, 1.0, s16 @@ -62247,8 +62247,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a ; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v20, s30, 0 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_writelane_b32 v20, s31, 1 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_readfirstlane_b32 s30, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s31, v1 @@ -62566,8 +62566,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a ; VI-NEXT: v_mov_b32_e32 v14, s30 ; VI-NEXT: v_mov_b32_e32 v15, s31 ; VI-NEXT: .LBB95_5: ; %end -; VI-NEXT: v_readlane_b32 s31, v20, 1 ; VI-NEXT: v_readlane_b32 s30, v20, 0 +; VI-NEXT: v_readlane_b32 s31, v20, 1 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -62581,8 +62581,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a ; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: v_writelane_b32 v20, s30, 0 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_writelane_b32 v20, s31, 1 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_readfirstlane_b32 s30, v0 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s31, v1 @@ -62901,8 +62901,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a ; GFX9-NEXT: v_mov_b32_e32 v14, s30 ; GFX9-NEXT: v_mov_b32_e32 v15, s31 ; GFX9-NEXT: .LBB95_5: ; %end -; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -64359,8 +64359,24 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) { ; ; VI-LABEL: bitcast_v32i16_to_v64i8: ; VI: ; %bb.0: -; VI-NEXT: ; implicit-def: $vgpr19 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: ; implicit-def: $vgpr19 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 ; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: ; kill: killed $vgpr19 @@ -64381,22 +64397,6 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) { ; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: ; kill: killed $vgpr19 ; VI-NEXT: ; implicit-def: $vgpr19 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: ; implicit-def: $vgpr43 ; VI-NEXT: ; kill: killed $vgpr17 ; VI-NEXT: ; implicit-def: $vgpr17 @@ -64829,10 +64829,6 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v32i16_to_v64i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; GFX9-NEXT: ; implicit-def: $vgpr17 -; GFX9-NEXT: ; kill: killed $vgpr17 -; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -64849,6 +64845,10 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; GFX9-NEXT: ; implicit-def: $vgpr17 +; GFX9-NEXT: ; kill: killed $vgpr17 +; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: ; implicit-def: $vgpr29 ; GFX9-NEXT: ; implicit-def: $vgpr27 ; GFX9-NEXT: ; implicit-def: $vgpr23 @@ -65725,43 +65725,43 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32 ; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_writelane_b32 v20, s69, 21 -; SI-NEXT: v_writelane_b32 v20, s70, 22 -; SI-NEXT: v_writelane_b32 v20, s71, 23 -; SI-NEXT: v_writelane_b32 v20, s80, 24 -; SI-NEXT: v_writelane_b32 v20, s81, 25 -; SI-NEXT: v_writelane_b32 v20, s82, 26 -; SI-NEXT: v_writelane_b32 v20, s83, 27 -; SI-NEXT: v_writelane_b32 v20, s84, 28 -; SI-NEXT: v_writelane_b32 v20, s85, 29 -; SI-NEXT: v_writelane_b32 v20, s86, 30 -; SI-NEXT: v_writelane_b32 v20, s87, 31 -; SI-NEXT: v_writelane_b32 v20, s96, 32 -; SI-NEXT: v_writelane_b32 v20, s97, 33 -; SI-NEXT: v_writelane_b32 v20, s98, 34 +; SI-NEXT: v_writelane_b32 v20, s34, 0 +; SI-NEXT: v_writelane_b32 v20, s35, 1 +; SI-NEXT: v_writelane_b32 v20, s36, 2 +; SI-NEXT: v_writelane_b32 v20, s37, 3 +; SI-NEXT: v_writelane_b32 v20, s38, 4 +; SI-NEXT: v_writelane_b32 v20, s39, 5 +; SI-NEXT: v_writelane_b32 v20, s48, 6 +; SI-NEXT: v_writelane_b32 v20, s49, 7 +; SI-NEXT: v_writelane_b32 v20, s50, 8 +; SI-NEXT: v_writelane_b32 v20, s51, 9 +; SI-NEXT: v_writelane_b32 v20, s52, 10 +; SI-NEXT: v_writelane_b32 v20, s53, 11 +; SI-NEXT: v_writelane_b32 v20, s54, 12 +; SI-NEXT: v_writelane_b32 v20, s55, 13 +; SI-NEXT: v_writelane_b32 v20, s64, 14 +; SI-NEXT: v_writelane_b32 v20, s65, 15 +; SI-NEXT: v_writelane_b32 v20, s66, 16 +; SI-NEXT: v_writelane_b32 v20, s67, 17 +; SI-NEXT: v_writelane_b32 v20, s68, 18 +; SI-NEXT: v_writelane_b32 v20, s69, 19 +; SI-NEXT: v_writelane_b32 v20, s70, 20 +; SI-NEXT: v_writelane_b32 v20, s71, 21 +; SI-NEXT: v_writelane_b32 v20, s80, 22 +; SI-NEXT: v_writelane_b32 v20, s81, 23 +; SI-NEXT: v_writelane_b32 v20, s82, 24 +; SI-NEXT: v_writelane_b32 v20, s83, 25 +; SI-NEXT: v_writelane_b32 v20, s84, 26 +; SI-NEXT: v_writelane_b32 v20, s85, 27 +; SI-NEXT: v_writelane_b32 v20, s86, 28 +; SI-NEXT: v_writelane_b32 v20, s87, 29 +; SI-NEXT: v_writelane_b32 v20, s96, 30 +; SI-NEXT: v_writelane_b32 v20, s97, 31 +; SI-NEXT: v_writelane_b32 v20, s98, 32 +; SI-NEXT: v_writelane_b32 v20, s99, 33 +; SI-NEXT: v_writelane_b32 v20, s30, 34 +; SI-NEXT: v_writelane_b32 v20, s31, 35 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s99, 35 ; SI-NEXT: s_mov_b32 s93, s18 ; SI-NEXT: s_mov_b32 s31, s17 ; SI-NEXT: v_readfirstlane_b32 s59, v18 @@ -66280,45 +66280,45 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v20, 34 ; SI-NEXT: v_readlane_b32 s19, v21, 11 ; SI-NEXT: v_readlane_b32 s17, v21, 17 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v20, 35 -; SI-NEXT: v_readlane_b32 s98, v20, 34 -; SI-NEXT: v_readlane_b32 s97, v20, 33 -; SI-NEXT: v_readlane_b32 s96, v20, 32 -; SI-NEXT: v_readlane_b32 s87, v20, 31 -; SI-NEXT: v_readlane_b32 s86, v20, 30 -; SI-NEXT: v_readlane_b32 s85, v20, 29 -; SI-NEXT: v_readlane_b32 s84, v20, 28 -; SI-NEXT: v_readlane_b32 s83, v20, 27 -; SI-NEXT: v_readlane_b32 s82, v20, 26 -; SI-NEXT: v_readlane_b32 s81, v20, 25 -; SI-NEXT: v_readlane_b32 s80, v20, 24 -; SI-NEXT: v_readlane_b32 s71, v20, 23 -; SI-NEXT: v_readlane_b32 s70, v20, 22 -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s31, v20, 35 +; SI-NEXT: v_readlane_b32 s99, v20, 33 +; SI-NEXT: v_readlane_b32 s98, v20, 32 +; SI-NEXT: v_readlane_b32 s97, v20, 31 +; SI-NEXT: v_readlane_b32 s96, v20, 30 +; SI-NEXT: v_readlane_b32 s87, v20, 29 +; SI-NEXT: v_readlane_b32 s86, v20, 28 +; SI-NEXT: v_readlane_b32 s85, v20, 27 +; SI-NEXT: v_readlane_b32 s84, v20, 26 +; SI-NEXT: v_readlane_b32 s83, v20, 25 +; SI-NEXT: v_readlane_b32 s82, v20, 24 +; SI-NEXT: v_readlane_b32 s81, v20, 23 +; SI-NEXT: v_readlane_b32 s80, v20, 22 +; SI-NEXT: v_readlane_b32 s71, v20, 21 +; SI-NEXT: v_readlane_b32 s70, v20, 20 +; SI-NEXT: v_readlane_b32 s69, v20, 19 +; SI-NEXT: v_readlane_b32 s68, v20, 18 +; SI-NEXT: v_readlane_b32 s67, v20, 17 +; SI-NEXT: v_readlane_b32 s66, v20, 16 +; SI-NEXT: v_readlane_b32 s65, v20, 15 +; SI-NEXT: v_readlane_b32 s64, v20, 14 +; SI-NEXT: v_readlane_b32 s55, v20, 13 +; SI-NEXT: v_readlane_b32 s54, v20, 12 +; SI-NEXT: v_readlane_b32 s53, v20, 11 +; SI-NEXT: v_readlane_b32 s52, v20, 10 +; SI-NEXT: v_readlane_b32 s51, v20, 9 +; SI-NEXT: v_readlane_b32 s50, v20, 8 +; SI-NEXT: v_readlane_b32 s49, v20, 7 +; SI-NEXT: v_readlane_b32 s48, v20, 6 +; SI-NEXT: v_readlane_b32 s39, v20, 5 +; SI-NEXT: v_readlane_b32 s38, v20, 4 +; SI-NEXT: v_readlane_b32 s37, v20, 3 +; SI-NEXT: v_readlane_b32 s36, v20, 2 +; SI-NEXT: v_readlane_b32 s35, v20, 1 +; SI-NEXT: v_readlane_b32 s34, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -66409,30 +66409,30 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v4, s30, 0 -; VI-NEXT: v_writelane_b32 v4, s31, 1 -; VI-NEXT: v_writelane_b32 v4, s34, 2 -; VI-NEXT: v_writelane_b32 v4, s35, 3 -; VI-NEXT: v_writelane_b32 v4, s36, 4 -; VI-NEXT: v_writelane_b32 v4, s37, 5 -; VI-NEXT: v_writelane_b32 v4, s38, 6 -; VI-NEXT: v_writelane_b32 v4, s39, 7 -; VI-NEXT: v_writelane_b32 v4, s48, 8 -; VI-NEXT: v_writelane_b32 v4, s49, 9 -; VI-NEXT: v_writelane_b32 v4, s50, 10 -; VI-NEXT: v_writelane_b32 v4, s51, 11 -; VI-NEXT: v_writelane_b32 v4, s52, 12 -; VI-NEXT: v_writelane_b32 v4, s53, 13 -; VI-NEXT: v_writelane_b32 v4, s54, 14 -; VI-NEXT: v_writelane_b32 v4, s55, 15 -; VI-NEXT: v_writelane_b32 v4, s64, 16 -; VI-NEXT: v_writelane_b32 v4, s65, 17 +; VI-NEXT: v_writelane_b32 v4, s34, 0 +; VI-NEXT: v_writelane_b32 v4, s35, 1 +; VI-NEXT: v_writelane_b32 v4, s36, 2 +; VI-NEXT: v_writelane_b32 v4, s37, 3 +; VI-NEXT: v_writelane_b32 v4, s38, 4 +; VI-NEXT: v_writelane_b32 v4, s39, 5 +; VI-NEXT: v_writelane_b32 v4, s48, 6 +; VI-NEXT: v_writelane_b32 v4, s49, 7 +; VI-NEXT: v_writelane_b32 v4, s50, 8 +; VI-NEXT: v_writelane_b32 v4, s51, 9 +; VI-NEXT: v_writelane_b32 v4, s52, 10 +; VI-NEXT: v_writelane_b32 v4, s53, 11 +; VI-NEXT: v_writelane_b32 v4, s54, 12 +; VI-NEXT: v_writelane_b32 v4, s55, 13 +; VI-NEXT: v_writelane_b32 v4, s64, 14 +; VI-NEXT: v_writelane_b32 v4, s65, 15 +; VI-NEXT: v_writelane_b32 v4, s66, 16 +; VI-NEXT: v_writelane_b32 v4, s67, 17 +; VI-NEXT: v_writelane_b32 v4, s30, 18 +; VI-NEXT: v_writelane_b32 v4, s31, 19 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; VI-NEXT: v_writelane_b32 v4, s66, 18 ; VI-NEXT: v_readfirstlane_b32 s4, v1 ; VI-NEXT: s_and_b64 s[6:7], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v2 -; VI-NEXT: v_writelane_b32 v4, s67, 19 ; VI-NEXT: s_cbranch_scc0 .LBB97_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s56, s5, 24 @@ -66804,27 +66804,27 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0 ; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_readlane_b32 s30, v4, 18 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; VI-NEXT: v_readlane_b32 s67, v4, 19 -; VI-NEXT: v_readlane_b32 s66, v4, 18 -; VI-NEXT: v_readlane_b32 s65, v4, 17 -; VI-NEXT: v_readlane_b32 s64, v4, 16 -; VI-NEXT: v_readlane_b32 s55, v4, 15 -; VI-NEXT: v_readlane_b32 s54, v4, 14 -; VI-NEXT: v_readlane_b32 s53, v4, 13 -; VI-NEXT: v_readlane_b32 s52, v4, 12 -; VI-NEXT: v_readlane_b32 s51, v4, 11 -; VI-NEXT: v_readlane_b32 s50, v4, 10 -; VI-NEXT: v_readlane_b32 s49, v4, 9 -; VI-NEXT: v_readlane_b32 s48, v4, 8 -; VI-NEXT: v_readlane_b32 s39, v4, 7 -; VI-NEXT: v_readlane_b32 s38, v4, 6 -; VI-NEXT: v_readlane_b32 s37, v4, 5 -; VI-NEXT: v_readlane_b32 s36, v4, 4 -; VI-NEXT: v_readlane_b32 s35, v4, 3 -; VI-NEXT: v_readlane_b32 s34, v4, 2 -; VI-NEXT: v_readlane_b32 s31, v4, 1 -; VI-NEXT: v_readlane_b32 s30, v4, 0 +; VI-NEXT: v_readlane_b32 s31, v4, 19 +; VI-NEXT: v_readlane_b32 s67, v4, 17 +; VI-NEXT: v_readlane_b32 s66, v4, 16 +; VI-NEXT: v_readlane_b32 s65, v4, 15 +; VI-NEXT: v_readlane_b32 s64, v4, 14 +; VI-NEXT: v_readlane_b32 s55, v4, 13 +; VI-NEXT: v_readlane_b32 s54, v4, 12 +; VI-NEXT: v_readlane_b32 s53, v4, 11 +; VI-NEXT: v_readlane_b32 s52, v4, 10 +; VI-NEXT: v_readlane_b32 s51, v4, 9 +; VI-NEXT: v_readlane_b32 s50, v4, 8 +; VI-NEXT: v_readlane_b32 s49, v4, 7 +; VI-NEXT: v_readlane_b32 s48, v4, 6 +; VI-NEXT: v_readlane_b32 s39, v4, 5 +; VI-NEXT: v_readlane_b32 s38, v4, 4 +; VI-NEXT: v_readlane_b32 s37, v4, 3 +; VI-NEXT: v_readlane_b32 s36, v4, 2 +; VI-NEXT: v_readlane_b32 s35, v4, 1 +; VI-NEXT: v_readlane_b32 s34, v4, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -66887,26 +66887,6 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v63, s30, 0 -; GFX9-NEXT: v_writelane_b32 v63, s31, 1 -; GFX9-NEXT: v_writelane_b32 v63, s34, 2 -; GFX9-NEXT: v_writelane_b32 v63, s35, 3 -; GFX9-NEXT: v_writelane_b32 v63, s36, 4 -; GFX9-NEXT: v_writelane_b32 v63, s37, 5 -; GFX9-NEXT: v_writelane_b32 v63, s38, 6 -; GFX9-NEXT: v_writelane_b32 v63, s39, 7 -; GFX9-NEXT: v_writelane_b32 v63, s48, 8 -; GFX9-NEXT: v_writelane_b32 v63, s49, 9 -; GFX9-NEXT: v_writelane_b32 v63, s50, 10 -; GFX9-NEXT: v_writelane_b32 v63, s51, 11 -; GFX9-NEXT: v_writelane_b32 v63, s52, 12 -; GFX9-NEXT: v_writelane_b32 v63, s53, 13 -; GFX9-NEXT: v_writelane_b32 v63, s54, 14 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: v_writelane_b32 v63, s55, 15 -; GFX9-NEXT: v_readfirstlane_b32 s4, v1 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s5, v2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -66922,6 +66902,26 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32 ; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v63, s34, 0 +; GFX9-NEXT: v_writelane_b32 v63, s35, 1 +; GFX9-NEXT: v_writelane_b32 v63, s36, 2 +; GFX9-NEXT: v_writelane_b32 v63, s37, 3 +; GFX9-NEXT: v_writelane_b32 v63, s38, 4 +; GFX9-NEXT: v_writelane_b32 v63, s39, 5 +; GFX9-NEXT: v_writelane_b32 v63, s48, 6 +; GFX9-NEXT: v_writelane_b32 v63, s49, 7 +; GFX9-NEXT: v_writelane_b32 v63, s50, 8 +; GFX9-NEXT: v_writelane_b32 v63, s51, 9 +; GFX9-NEXT: v_writelane_b32 v63, s52, 10 +; GFX9-NEXT: v_writelane_b32 v63, s53, 11 +; GFX9-NEXT: v_writelane_b32 v63, s54, 12 +; GFX9-NEXT: v_writelane_b32 v63, s55, 13 +; GFX9-NEXT: v_writelane_b32 v63, s30, 14 +; GFX9-NEXT: v_writelane_b32 v63, s31, 15 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v1 +; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec +; GFX9-NEXT: v_readfirstlane_b32 s5, v2 ; GFX9-NEXT: s_cbranch_scc0 .LBB97_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s56, s5, 24 @@ -67243,22 +67243,22 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32 ; GFX9-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s55, v63, 15 -; GFX9-NEXT: v_readlane_b32 s54, v63, 14 -; GFX9-NEXT: v_readlane_b32 s53, v63, 13 -; GFX9-NEXT: v_readlane_b32 s52, v63, 12 -; GFX9-NEXT: v_readlane_b32 s51, v63, 11 -; GFX9-NEXT: v_readlane_b32 s50, v63, 10 -; GFX9-NEXT: v_readlane_b32 s49, v63, 9 -; GFX9-NEXT: v_readlane_b32 s48, v63, 8 -; GFX9-NEXT: v_readlane_b32 s39, v63, 7 -; GFX9-NEXT: v_readlane_b32 s38, v63, 6 -; GFX9-NEXT: v_readlane_b32 s37, v63, 5 -; GFX9-NEXT: v_readlane_b32 s36, v63, 4 -; GFX9-NEXT: v_readlane_b32 s35, v63, 3 -; GFX9-NEXT: v_readlane_b32 s34, v63, 2 -; GFX9-NEXT: v_readlane_b32 s31, v63, 1 -; GFX9-NEXT: v_readlane_b32 s30, v63, 0 +; GFX9-NEXT: v_readlane_b32 s30, v63, 14 +; GFX9-NEXT: v_readlane_b32 s31, v63, 15 +; GFX9-NEXT: v_readlane_b32 s55, v63, 13 +; GFX9-NEXT: v_readlane_b32 s54, v63, 12 +; GFX9-NEXT: v_readlane_b32 s53, v63, 11 +; GFX9-NEXT: v_readlane_b32 s52, v63, 10 +; GFX9-NEXT: v_readlane_b32 s51, v63, 9 +; GFX9-NEXT: v_readlane_b32 s50, v63, 8 +; GFX9-NEXT: v_readlane_b32 s49, v63, 7 +; GFX9-NEXT: v_readlane_b32 s48, v63, 6 +; GFX9-NEXT: v_readlane_b32 s39, v63, 5 +; GFX9-NEXT: v_readlane_b32 s38, v63, 4 +; GFX9-NEXT: v_readlane_b32 s37, v63, 3 +; GFX9-NEXT: v_readlane_b32 s36, v63, 2 +; GFX9-NEXT: v_readlane_b32 s35, v63, 1 +; GFX9-NEXT: v_readlane_b32 s34, v63, 0 ; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5 ; GFX9-NEXT: v_or_b32_sdwa v5, v33, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -67312,18 +67312,18 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32 ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s34, 0 +; GFX11-NEXT: v_writelane_b32 v40, s35, 1 +; GFX11-NEXT: v_writelane_b32 v40, s36, 2 +; GFX11-NEXT: v_writelane_b32 v40, s37, 3 +; GFX11-NEXT: v_writelane_b32 v40, s38, 4 +; GFX11-NEXT: v_writelane_b32 v40, s39, 5 +; GFX11-NEXT: v_writelane_b32 v40, s48, 6 +; GFX11-NEXT: v_writelane_b32 v40, s49, 7 +; GFX11-NEXT: v_writelane_b32 v40, s30, 8 +; GFX11-NEXT: v_writelane_b32 v40, s31, 9 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_mov_b32 s42, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 -; GFX11-NEXT: v_writelane_b32 v40, s34, 2 -; GFX11-NEXT: v_writelane_b32 v40, s35, 3 -; GFX11-NEXT: v_writelane_b32 v40, s36, 4 -; GFX11-NEXT: v_writelane_b32 v40, s37, 5 -; GFX11-NEXT: v_writelane_b32 v40, s38, 6 -; GFX11-NEXT: v_writelane_b32 v40, s39, 7 -; GFX11-NEXT: v_writelane_b32 v40, s48, 8 -; GFX11-NEXT: v_writelane_b32 v40, s49, 9 ; GFX11-NEXT: s_cbranch_scc0 .LBB97_3 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s43, s27, 24 @@ -67671,21 +67671,21 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32 ; GFX11-NEXT: v_or_b32_e32 v2, v4, v10 ; GFX11-NEXT: v_or_b32_e32 v3, v11, v7 ; GFX11-NEXT: v_or_b32_e32 v4, v12, v8 +; GFX11-NEXT: v_readlane_b32 s30, v40, 8 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b128 v0, v[82:85], off ; GFX11-NEXT: scratch_store_b128 v0, v[23:26], off offset:16 ; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:32 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48 -; GFX11-NEXT: v_readlane_b32 s49, v40, 9 -; GFX11-NEXT: v_readlane_b32 s48, v40, 8 -; GFX11-NEXT: v_readlane_b32 s39, v40, 7 -; GFX11-NEXT: v_readlane_b32 s38, v40, 6 -; GFX11-NEXT: v_readlane_b32 s37, v40, 5 -; GFX11-NEXT: v_readlane_b32 s36, v40, 4 -; GFX11-NEXT: v_readlane_b32 s35, v40, 3 -; GFX11-NEXT: v_readlane_b32 s34, v40, 2 -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 -; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 9 +; GFX11-NEXT: v_readlane_b32 s49, v40, 7 +; GFX11-NEXT: v_readlane_b32 s48, v40, 6 +; GFX11-NEXT: v_readlane_b32 s39, v40, 5 +; GFX11-NEXT: v_readlane_b32 s38, v40, 4 +; GFX11-NEXT: v_readlane_b32 s37, v40, 3 +; GFX11-NEXT: v_readlane_b32 s36, v40, 2 +; GFX11-NEXT: v_readlane_b32 s35, v40, 1 +; GFX11-NEXT: v_readlane_b32 s34, v40, 0 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload ; GFX11-NEXT: s_mov_b32 exec_lo, s0 @@ -74579,7 +74579,6 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg % ; SI-LABEL: bitcast_v32bf16_to_v32f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -74596,6 +74595,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg % ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_mul_f32_e64 v32, 1.0, s16 ; SI-NEXT: v_mul_f32_e64 v33, 1.0, s17 @@ -74893,8 +74893,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg % ; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v20, s30, 0 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_writelane_b32 v20, s31, 1 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; VI-NEXT: v_readfirstlane_b32 s30, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s31, v1 @@ -75212,8 +75212,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg % ; VI-NEXT: v_mov_b32_e32 v14, s30 ; VI-NEXT: v_mov_b32_e32 v15, s31 ; VI-NEXT: .LBB103_5: ; %end -; VI-NEXT: v_readlane_b32 s31, v20, 1 ; VI-NEXT: v_readlane_b32 s30, v20, 0 +; VI-NEXT: v_readlane_b32 s31, v20, 1 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -75227,8 +75227,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg % ; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: v_writelane_b32 v20, s30, 0 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_writelane_b32 v20, s31, 1 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_readfirstlane_b32 s30, v0 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s31, v1 @@ -75563,8 +75563,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg % ; GFX9-NEXT: v_mov_b32_e32 v14, s30 ; GFX9-NEXT: v_mov_b32_e32 v15, s31 ; GFX9-NEXT: .LBB103_5: ; %end -; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: v_readlane_b32 s31, v20, 1 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -77045,6 +77045,22 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) { ; VI-LABEL: bitcast_v32f16_to_v64i8: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 ; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: ; kill: killed $vgpr17 @@ -77067,22 +77083,6 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) { ; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 ; VI-NEXT: ; kill: killed $vgpr17 ; VI-NEXT: ; implicit-def: $vgpr17 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: ; implicit-def: $vgpr22 ; VI-NEXT: ; implicit-def: $vgpr24 ; VI-NEXT: ; implicit-def: $vgpr55 @@ -77397,10 +77397,6 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v32f16_to_v64i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; GFX9-NEXT: ; implicit-def: $vgpr17 -; GFX9-NEXT: ; kill: killed $vgpr17 -; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -77417,6 +77413,10 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; GFX9-NEXT: ; implicit-def: $vgpr17 +; GFX9-NEXT: ; kill: killed $vgpr17 +; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: ; implicit-def: $vgpr29 ; GFX9-NEXT: ; implicit-def: $vgpr27 ; GFX9-NEXT: ; implicit-def: $vgpr23 @@ -78293,8 +78293,12 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v40, s30, 0 -; SI-NEXT: v_writelane_b32 v40, s31, 1 +; SI-NEXT: v_writelane_b32 v40, s34, 0 +; SI-NEXT: v_writelane_b32 v40, s35, 1 +; SI-NEXT: v_writelane_b32 v40, s36, 2 +; SI-NEXT: v_writelane_b32 v40, s37, 3 +; SI-NEXT: v_writelane_b32 v40, s30, 4 +; SI-NEXT: v_writelane_b32 v40, s31, 5 ; SI-NEXT: v_cvt_f16_f32_e32 v21, s17 ; SI-NEXT: v_cvt_f16_f32_e32 v20, v2 ; SI-NEXT: v_cvt_f16_f32_e32 v22, v1 @@ -78327,12 +78331,8 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; SI-NEXT: v_cvt_f16_f32_e32 v13, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v17, s29 ; SI-NEXT: v_cvt_f16_f32_e32 v16, s28 -; SI-NEXT: v_writelane_b32 v40, s34, 2 -; SI-NEXT: v_writelane_b32 v40, s35, 3 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v40, s36, 4 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_writelane_b32 v40, s37, 5 ; SI-NEXT: s_cbranch_scc0 .LBB105_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_readfirstlane_b32 s4, v21 @@ -78833,13 +78833,13 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: v_or_b32_e32 v1, s4, v1 ; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0 +; SI-NEXT: v_readlane_b32 s30, v40, 4 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s37, v40, 5 -; SI-NEXT: v_readlane_b32 s36, v40, 4 -; SI-NEXT: v_readlane_b32 s35, v40, 3 -; SI-NEXT: v_readlane_b32 s34, v40, 2 -; SI-NEXT: v_readlane_b32 s31, v40, 1 -; SI-NEXT: v_readlane_b32 s30, v40, 0 +; SI-NEXT: v_readlane_b32 s31, v40, 5 +; SI-NEXT: v_readlane_b32 s37, v40, 3 +; SI-NEXT: v_readlane_b32 s36, v40, 2 +; SI-NEXT: v_readlane_b32 s35, v40, 1 +; SI-NEXT: v_readlane_b32 s34, v40, 0 ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -78902,30 +78902,6 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v63, s30, 0 -; VI-NEXT: v_writelane_b32 v63, s31, 1 -; VI-NEXT: v_writelane_b32 v63, s34, 2 -; VI-NEXT: v_writelane_b32 v63, s35, 3 -; VI-NEXT: v_writelane_b32 v63, s36, 4 -; VI-NEXT: v_writelane_b32 v63, s37, 5 -; VI-NEXT: v_writelane_b32 v63, s38, 6 -; VI-NEXT: v_writelane_b32 v63, s39, 7 -; VI-NEXT: v_writelane_b32 v63, s48, 8 -; VI-NEXT: v_writelane_b32 v63, s49, 9 -; VI-NEXT: v_writelane_b32 v63, s50, 10 -; VI-NEXT: v_writelane_b32 v63, s51, 11 -; VI-NEXT: v_writelane_b32 v63, s52, 12 -; VI-NEXT: v_writelane_b32 v63, s53, 13 -; VI-NEXT: v_writelane_b32 v63, s54, 14 -; VI-NEXT: v_writelane_b32 v63, s55, 15 -; VI-NEXT: v_writelane_b32 v63, s64, 16 -; VI-NEXT: v_writelane_b32 v63, s65, 17 -; VI-NEXT: v_writelane_b32 v63, s66, 18 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; VI-NEXT: v_writelane_b32 v63, s67, 19 -; VI-NEXT: v_readfirstlane_b32 s4, v1 -; VI-NEXT: s_and_b64 s[6:7], vcc, exec -; VI-NEXT: v_readfirstlane_b32 s5, v2 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -78941,6 +78917,30 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_writelane_b32 v63, s34, 0 +; VI-NEXT: v_writelane_b32 v63, s35, 1 +; VI-NEXT: v_writelane_b32 v63, s36, 2 +; VI-NEXT: v_writelane_b32 v63, s37, 3 +; VI-NEXT: v_writelane_b32 v63, s38, 4 +; VI-NEXT: v_writelane_b32 v63, s39, 5 +; VI-NEXT: v_writelane_b32 v63, s48, 6 +; VI-NEXT: v_writelane_b32 v63, s49, 7 +; VI-NEXT: v_writelane_b32 v63, s50, 8 +; VI-NEXT: v_writelane_b32 v63, s51, 9 +; VI-NEXT: v_writelane_b32 v63, s52, 10 +; VI-NEXT: v_writelane_b32 v63, s53, 11 +; VI-NEXT: v_writelane_b32 v63, s54, 12 +; VI-NEXT: v_writelane_b32 v63, s55, 13 +; VI-NEXT: v_writelane_b32 v63, s64, 14 +; VI-NEXT: v_writelane_b32 v63, s65, 15 +; VI-NEXT: v_writelane_b32 v63, s66, 16 +; VI-NEXT: v_writelane_b32 v63, s67, 17 +; VI-NEXT: v_writelane_b32 v63, s30, 18 +; VI-NEXT: v_writelane_b32 v63, s31, 19 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; VI-NEXT: v_readfirstlane_b32 s4, v1 +; VI-NEXT: s_and_b64 s[6:7], vcc, exec +; VI-NEXT: v_readfirstlane_b32 s5, v2 ; VI-NEXT: s_cbranch_scc0 .LBB105_3 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s75, s5, 24 @@ -79320,26 +79320,26 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v54 ; VI-NEXT: v_or_b32_sdwa v1, v49, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_readlane_b32 s67, v63, 19 -; VI-NEXT: v_readlane_b32 s66, v63, 18 -; VI-NEXT: v_readlane_b32 s65, v63, 17 -; VI-NEXT: v_readlane_b32 s64, v63, 16 -; VI-NEXT: v_readlane_b32 s55, v63, 15 -; VI-NEXT: v_readlane_b32 s54, v63, 14 -; VI-NEXT: v_readlane_b32 s53, v63, 13 -; VI-NEXT: v_readlane_b32 s52, v63, 12 -; VI-NEXT: v_readlane_b32 s51, v63, 11 -; VI-NEXT: v_readlane_b32 s50, v63, 10 -; VI-NEXT: v_readlane_b32 s49, v63, 9 -; VI-NEXT: v_readlane_b32 s48, v63, 8 -; VI-NEXT: v_readlane_b32 s39, v63, 7 -; VI-NEXT: v_readlane_b32 s38, v63, 6 -; VI-NEXT: v_readlane_b32 s37, v63, 5 -; VI-NEXT: v_readlane_b32 s36, v63, 4 -; VI-NEXT: v_readlane_b32 s35, v63, 3 -; VI-NEXT: v_readlane_b32 s34, v63, 2 -; VI-NEXT: v_readlane_b32 s31, v63, 1 -; VI-NEXT: v_readlane_b32 s30, v63, 0 +; VI-NEXT: v_readlane_b32 s30, v63, 18 +; VI-NEXT: v_readlane_b32 s31, v63, 19 +; VI-NEXT: v_readlane_b32 s67, v63, 17 +; VI-NEXT: v_readlane_b32 s66, v63, 16 +; VI-NEXT: v_readlane_b32 s65, v63, 15 +; VI-NEXT: v_readlane_b32 s64, v63, 14 +; VI-NEXT: v_readlane_b32 s55, v63, 13 +; VI-NEXT: v_readlane_b32 s54, v63, 12 +; VI-NEXT: v_readlane_b32 s53, v63, 11 +; VI-NEXT: v_readlane_b32 s52, v63, 10 +; VI-NEXT: v_readlane_b32 s51, v63, 9 +; VI-NEXT: v_readlane_b32 s50, v63, 8 +; VI-NEXT: v_readlane_b32 s49, v63, 7 +; VI-NEXT: v_readlane_b32 s48, v63, 6 +; VI-NEXT: v_readlane_b32 s39, v63, 5 +; VI-NEXT: v_readlane_b32 s38, v63, 4 +; VI-NEXT: v_readlane_b32 s37, v63, 3 +; VI-NEXT: v_readlane_b32 s36, v63, 2 +; VI-NEXT: v_readlane_b32 s35, v63, 1 +; VI-NEXT: v_readlane_b32 s34, v63, 0 ; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; VI-NEXT: v_or_b32_sdwa v2, v25, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -79399,26 +79399,6 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v63, s30, 0 -; GFX9-NEXT: v_writelane_b32 v63, s31, 1 -; GFX9-NEXT: v_writelane_b32 v63, s34, 2 -; GFX9-NEXT: v_writelane_b32 v63, s35, 3 -; GFX9-NEXT: v_writelane_b32 v63, s36, 4 -; GFX9-NEXT: v_writelane_b32 v63, s37, 5 -; GFX9-NEXT: v_writelane_b32 v63, s38, 6 -; GFX9-NEXT: v_writelane_b32 v63, s39, 7 -; GFX9-NEXT: v_writelane_b32 v63, s48, 8 -; GFX9-NEXT: v_writelane_b32 v63, s49, 9 -; GFX9-NEXT: v_writelane_b32 v63, s50, 10 -; GFX9-NEXT: v_writelane_b32 v63, s51, 11 -; GFX9-NEXT: v_writelane_b32 v63, s52, 12 -; GFX9-NEXT: v_writelane_b32 v63, s53, 13 -; GFX9-NEXT: v_writelane_b32 v63, s54, 14 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: v_writelane_b32 v63, s55, 15 -; GFX9-NEXT: v_readfirstlane_b32 s4, v1 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s5, v2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -79434,6 +79414,26 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v63, s34, 0 +; GFX9-NEXT: v_writelane_b32 v63, s35, 1 +; GFX9-NEXT: v_writelane_b32 v63, s36, 2 +; GFX9-NEXT: v_writelane_b32 v63, s37, 3 +; GFX9-NEXT: v_writelane_b32 v63, s38, 4 +; GFX9-NEXT: v_writelane_b32 v63, s39, 5 +; GFX9-NEXT: v_writelane_b32 v63, s48, 6 +; GFX9-NEXT: v_writelane_b32 v63, s49, 7 +; GFX9-NEXT: v_writelane_b32 v63, s50, 8 +; GFX9-NEXT: v_writelane_b32 v63, s51, 9 +; GFX9-NEXT: v_writelane_b32 v63, s52, 10 +; GFX9-NEXT: v_writelane_b32 v63, s53, 11 +; GFX9-NEXT: v_writelane_b32 v63, s54, 12 +; GFX9-NEXT: v_writelane_b32 v63, s55, 13 +; GFX9-NEXT: v_writelane_b32 v63, s30, 14 +; GFX9-NEXT: v_writelane_b32 v63, s31, 15 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v1 +; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec +; GFX9-NEXT: v_readfirstlane_b32 s5, v2 ; GFX9-NEXT: s_cbranch_scc0 .LBB105_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s56, s5, 24 @@ -79756,22 +79756,22 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; GFX9-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s55, v63, 15 -; GFX9-NEXT: v_readlane_b32 s54, v63, 14 -; GFX9-NEXT: v_readlane_b32 s53, v63, 13 -; GFX9-NEXT: v_readlane_b32 s52, v63, 12 -; GFX9-NEXT: v_readlane_b32 s51, v63, 11 -; GFX9-NEXT: v_readlane_b32 s50, v63, 10 -; GFX9-NEXT: v_readlane_b32 s49, v63, 9 -; GFX9-NEXT: v_readlane_b32 s48, v63, 8 -; GFX9-NEXT: v_readlane_b32 s39, v63, 7 -; GFX9-NEXT: v_readlane_b32 s38, v63, 6 -; GFX9-NEXT: v_readlane_b32 s37, v63, 5 -; GFX9-NEXT: v_readlane_b32 s36, v63, 4 -; GFX9-NEXT: v_readlane_b32 s35, v63, 3 -; GFX9-NEXT: v_readlane_b32 s34, v63, 2 -; GFX9-NEXT: v_readlane_b32 s31, v63, 1 -; GFX9-NEXT: v_readlane_b32 s30, v63, 0 +; GFX9-NEXT: v_readlane_b32 s30, v63, 14 +; GFX9-NEXT: v_readlane_b32 s31, v63, 15 +; GFX9-NEXT: v_readlane_b32 s55, v63, 13 +; GFX9-NEXT: v_readlane_b32 s54, v63, 12 +; GFX9-NEXT: v_readlane_b32 s53, v63, 11 +; GFX9-NEXT: v_readlane_b32 s52, v63, 10 +; GFX9-NEXT: v_readlane_b32 s51, v63, 9 +; GFX9-NEXT: v_readlane_b32 s50, v63, 8 +; GFX9-NEXT: v_readlane_b32 s49, v63, 7 +; GFX9-NEXT: v_readlane_b32 s48, v63, 6 +; GFX9-NEXT: v_readlane_b32 s39, v63, 5 +; GFX9-NEXT: v_readlane_b32 s38, v63, 4 +; GFX9-NEXT: v_readlane_b32 s37, v63, 3 +; GFX9-NEXT: v_readlane_b32 s36, v63, 2 +; GFX9-NEXT: v_readlane_b32 s35, v63, 1 +; GFX9-NEXT: v_readlane_b32 s34, v63, 0 ; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5 ; GFX9-NEXT: v_or_b32_sdwa v5, v33, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -79825,18 +79825,18 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s34, 0 +; GFX11-NEXT: v_writelane_b32 v40, s35, 1 +; GFX11-NEXT: v_writelane_b32 v40, s36, 2 +; GFX11-NEXT: v_writelane_b32 v40, s37, 3 +; GFX11-NEXT: v_writelane_b32 v40, s38, 4 +; GFX11-NEXT: v_writelane_b32 v40, s39, 5 +; GFX11-NEXT: v_writelane_b32 v40, s48, 6 +; GFX11-NEXT: v_writelane_b32 v40, s49, 7 +; GFX11-NEXT: v_writelane_b32 v40, s30, 8 +; GFX11-NEXT: v_writelane_b32 v40, s31, 9 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_mov_b32 s42, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 -; GFX11-NEXT: v_writelane_b32 v40, s34, 2 -; GFX11-NEXT: v_writelane_b32 v40, s35, 3 -; GFX11-NEXT: v_writelane_b32 v40, s36, 4 -; GFX11-NEXT: v_writelane_b32 v40, s37, 5 -; GFX11-NEXT: v_writelane_b32 v40, s38, 6 -; GFX11-NEXT: v_writelane_b32 v40, s39, 7 -; GFX11-NEXT: v_writelane_b32 v40, s48, 8 -; GFX11-NEXT: v_writelane_b32 v40, s49, 9 ; GFX11-NEXT: s_cbranch_scc0 .LBB105_3 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s43, s27, 24 @@ -80184,21 +80184,21 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 ; GFX11-NEXT: v_or_b32_e32 v2, v4, v10 ; GFX11-NEXT: v_or_b32_e32 v3, v11, v7 ; GFX11-NEXT: v_or_b32_e32 v4, v12, v8 +; GFX11-NEXT: v_readlane_b32 s30, v40, 8 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b128 v0, v[82:85], off ; GFX11-NEXT: scratch_store_b128 v0, v[23:26], off offset:16 ; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:32 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48 -; GFX11-NEXT: v_readlane_b32 s49, v40, 9 -; GFX11-NEXT: v_readlane_b32 s48, v40, 8 -; GFX11-NEXT: v_readlane_b32 s39, v40, 7 -; GFX11-NEXT: v_readlane_b32 s38, v40, 6 -; GFX11-NEXT: v_readlane_b32 s37, v40, 5 -; GFX11-NEXT: v_readlane_b32 s36, v40, 4 -; GFX11-NEXT: v_readlane_b32 s35, v40, 3 -; GFX11-NEXT: v_readlane_b32 s34, v40, 2 -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 -; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 9 +; GFX11-NEXT: v_readlane_b32 s49, v40, 7 +; GFX11-NEXT: v_readlane_b32 s48, v40, 6 +; GFX11-NEXT: v_readlane_b32 s39, v40, 5 +; GFX11-NEXT: v_readlane_b32 s38, v40, 4 +; GFX11-NEXT: v_readlane_b32 s37, v40, 3 +; GFX11-NEXT: v_readlane_b32 s36, v40, 2 +; GFX11-NEXT: v_readlane_b32 s35, v40, 1 +; GFX11-NEXT: v_readlane_b32 s34, v40, 0 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload ; GFX11-NEXT: s_mov_b32 exec_lo, s0 @@ -82605,17 +82605,17 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_writelane_b32 v32, s34, 0 +; SI-NEXT: v_writelane_b32 v32, s35, 1 +; SI-NEXT: v_writelane_b32 v32, s36, 2 +; SI-NEXT: v_writelane_b32 v32, s37, 3 +; SI-NEXT: v_writelane_b32 v32, s38, 4 +; SI-NEXT: v_writelane_b32 v32, s39, 5 +; SI-NEXT: v_writelane_b32 v32, s30, 6 +; SI-NEXT: v_writelane_b32 v32, s31, 7 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72 ; SI-NEXT: v_readfirstlane_b32 s46, v20 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v32, s30, 0 -; SI-NEXT: v_writelane_b32 v32, s31, 1 -; SI-NEXT: v_writelane_b32 v32, s34, 2 -; SI-NEXT: v_writelane_b32 v32, s35, 3 -; SI-NEXT: v_writelane_b32 v32, s36, 4 -; SI-NEXT: v_writelane_b32 v32, s37, 5 -; SI-NEXT: v_writelane_b32 v32, s38, 6 -; SI-NEXT: v_writelane_b32 v32, s39, 7 ; SI-NEXT: v_readfirstlane_b32 s74, v30 ; SI-NEXT: v_readfirstlane_b32 s61, v29 ; SI-NEXT: v_readfirstlane_b32 s63, v28 @@ -83031,14 +83031,14 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: v_cvt_f32_f16_e32 v30, s5 ; SI-NEXT: v_cvt_f32_f16_e32 v31, s4 ; SI-NEXT: .LBB107_3: ; %end -; SI-NEXT: v_readlane_b32 s39, v32, 7 -; SI-NEXT: v_readlane_b32 s38, v32, 6 -; SI-NEXT: v_readlane_b32 s37, v32, 5 -; SI-NEXT: v_readlane_b32 s36, v32, 4 -; SI-NEXT: v_readlane_b32 s35, v32, 3 -; SI-NEXT: v_readlane_b32 s34, v32, 2 -; SI-NEXT: v_readlane_b32 s31, v32, 1 -; SI-NEXT: v_readlane_b32 s30, v32, 0 +; SI-NEXT: v_readlane_b32 s30, v32, 6 +; SI-NEXT: v_readlane_b32 s31, v32, 7 +; SI-NEXT: v_readlane_b32 s39, v32, 5 +; SI-NEXT: v_readlane_b32 s38, v32, 4 +; SI-NEXT: v_readlane_b32 s37, v32, 3 +; SI-NEXT: v_readlane_b32 s36, v32, 2 +; SI-NEXT: v_readlane_b32 s35, v32, 1 +; SI-NEXT: v_readlane_b32 s34, v32, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -85271,10 +85271,6 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) { ; VI-LABEL: bitcast_v32bf16_to_v64i8: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; VI-NEXT: ; implicit-def: $vgpr17 -; VI-NEXT: ; kill: killed $vgpr17 -; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -85291,6 +85287,10 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; VI-NEXT: ; implicit-def: $vgpr17 +; VI-NEXT: ; kill: killed $vgpr17 +; VI-NEXT: ; implicit-def: $vgpr17 ; VI-NEXT: ; implicit-def: $vgpr29 ; VI-NEXT: ; implicit-def: $vgpr27 ; VI-NEXT: ; implicit-def: $vgpr22 @@ -85875,12 +85875,6 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) { ; GFX9-LABEL: bitcast_v32bf16_to_v64i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; GFX9-NEXT: ; implicit-def: $vgpr17 -; GFX9-NEXT: ; kill: killed $vgpr17 -; GFX9-NEXT: ; implicit-def: $vgpr17 -; GFX9-NEXT: ; kill: killed $vgpr17 -; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -85897,6 +85891,12 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; GFX9-NEXT: ; implicit-def: $vgpr17 +; GFX9-NEXT: ; kill: killed $vgpr17 +; GFX9-NEXT: ; implicit-def: $vgpr17 +; GFX9-NEXT: ; kill: killed $vgpr17 +; GFX9-NEXT: ; implicit-def: $vgpr17 ; GFX9-NEXT: ; implicit-def: $vgpr27 ; GFX9-NEXT: ; implicit-def: $vgpr28 ; GFX9-NEXT: ; implicit-def: $vgpr23 @@ -87562,7 +87562,6 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a, ; SI-LABEL: bitcast_v32bf16_to_v64i8_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -87579,6 +87578,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a, ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_mul_f32_e64 v19, 1.0, s17 ; SI-NEXT: v_mul_f32_e32 v33, 1.0, v2 @@ -88167,30 +88167,6 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a, ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v63, s30, 0 -; VI-NEXT: v_writelane_b32 v63, s31, 1 -; VI-NEXT: v_writelane_b32 v63, s34, 2 -; VI-NEXT: v_writelane_b32 v63, s35, 3 -; VI-NEXT: v_writelane_b32 v63, s36, 4 -; VI-NEXT: v_writelane_b32 v63, s37, 5 -; VI-NEXT: v_writelane_b32 v63, s38, 6 -; VI-NEXT: v_writelane_b32 v63, s39, 7 -; VI-NEXT: v_writelane_b32 v63, s48, 8 -; VI-NEXT: v_writelane_b32 v63, s49, 9 -; VI-NEXT: v_writelane_b32 v63, s50, 10 -; VI-NEXT: v_writelane_b32 v63, s51, 11 -; VI-NEXT: v_writelane_b32 v63, s52, 12 -; VI-NEXT: v_writelane_b32 v63, s53, 13 -; VI-NEXT: v_writelane_b32 v63, s54, 14 -; VI-NEXT: v_writelane_b32 v63, s55, 15 -; VI-NEXT: v_writelane_b32 v63, s64, 16 -; VI-NEXT: v_writelane_b32 v63, s65, 17 -; VI-NEXT: v_writelane_b32 v63, s66, 18 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; VI-NEXT: v_writelane_b32 v63, s67, 19 -; VI-NEXT: v_readfirstlane_b32 s4, v1 -; VI-NEXT: s_and_b64 s[6:7], vcc, exec -; VI-NEXT: v_readfirstlane_b32 s5, v2 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -88206,6 +88182,30 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a, ; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_writelane_b32 v63, s34, 0 +; VI-NEXT: v_writelane_b32 v63, s35, 1 +; VI-NEXT: v_writelane_b32 v63, s36, 2 +; VI-NEXT: v_writelane_b32 v63, s37, 3 +; VI-NEXT: v_writelane_b32 v63, s38, 4 +; VI-NEXT: v_writelane_b32 v63, s39, 5 +; VI-NEXT: v_writelane_b32 v63, s48, 6 +; VI-NEXT: v_writelane_b32 v63, s49, 7 +; VI-NEXT: v_writelane_b32 v63, s50, 8 +; VI-NEXT: v_writelane_b32 v63, s51, 9 +; VI-NEXT: v_writelane_b32 v63, s52, 10 +; VI-NEXT: v_writelane_b32 v63, s53, 11 +; VI-NEXT: v_writelane_b32 v63, s54, 12 +; VI-NEXT: v_writelane_b32 v63, s55, 13 +; VI-NEXT: v_writelane_b32 v63, s64, 14 +; VI-NEXT: v_writelane_b32 v63, s65, 15 +; VI-NEXT: v_writelane_b32 v63, s66, 16 +; VI-NEXT: v_writelane_b32 v63, s67, 17 +; VI-NEXT: v_writelane_b32 v63, s30, 18 +; VI-NEXT: v_writelane_b32 v63, s31, 19 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; VI-NEXT: v_readfirstlane_b32 s4, v1 +; VI-NEXT: s_and_b64 s[6:7], vcc, exec +; VI-NEXT: v_readfirstlane_b32 s5, v2 ; VI-NEXT: s_cbranch_scc0 .LBB109_3 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s56, s5, 24 @@ -88807,26 +88807,26 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a, ; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v34 ; VI-NEXT: v_or_b32_sdwa v1, v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_readlane_b32 s67, v63, 19 -; VI-NEXT: v_readlane_b32 s66, v63, 18 -; VI-NEXT: v_readlane_b32 s65, v63, 17 -; VI-NEXT: v_readlane_b32 s64, v63, 16 -; VI-NEXT: v_readlane_b32 s55, v63, 15 -; VI-NEXT: v_readlane_b32 s54, v63, 14 -; VI-NEXT: v_readlane_b32 s53, v63, 13 -; VI-NEXT: v_readlane_b32 s52, v63, 12 -; VI-NEXT: v_readlane_b32 s51, v63, 11 -; VI-NEXT: v_readlane_b32 s50, v63, 10 -; VI-NEXT: v_readlane_b32 s49, v63, 9 -; VI-NEXT: v_readlane_b32 s48, v63, 8 -; VI-NEXT: v_readlane_b32 s39, v63, 7 -; VI-NEXT: v_readlane_b32 s38, v63, 6 -; VI-NEXT: v_readlane_b32 s37, v63, 5 -; VI-NEXT: v_readlane_b32 s36, v63, 4 -; VI-NEXT: v_readlane_b32 s35, v63, 3 -; VI-NEXT: v_readlane_b32 s34, v63, 2 -; VI-NEXT: v_readlane_b32 s31, v63, 1 -; VI-NEXT: v_readlane_b32 s30, v63, 0 +; VI-NEXT: v_readlane_b32 s30, v63, 18 +; VI-NEXT: v_readlane_b32 s31, v63, 19 +; VI-NEXT: v_readlane_b32 s67, v63, 17 +; VI-NEXT: v_readlane_b32 s66, v63, 16 +; VI-NEXT: v_readlane_b32 s65, v63, 15 +; VI-NEXT: v_readlane_b32 s64, v63, 14 +; VI-NEXT: v_readlane_b32 s55, v63, 13 +; VI-NEXT: v_readlane_b32 s54, v63, 12 +; VI-NEXT: v_readlane_b32 s53, v63, 11 +; VI-NEXT: v_readlane_b32 s52, v63, 10 +; VI-NEXT: v_readlane_b32 s51, v63, 9 +; VI-NEXT: v_readlane_b32 s50, v63, 8 +; VI-NEXT: v_readlane_b32 s49, v63, 7 +; VI-NEXT: v_readlane_b32 s48, v63, 6 +; VI-NEXT: v_readlane_b32 s39, v63, 5 +; VI-NEXT: v_readlane_b32 s38, v63, 4 +; VI-NEXT: v_readlane_b32 s37, v63, 3 +; VI-NEXT: v_readlane_b32 s36, v63, 2 +; VI-NEXT: v_readlane_b32 s35, v63, 1 +; VI-NEXT: v_readlane_b32 s34, v63, 0 ; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; VI-NEXT: v_or_b32_sdwa v2, v33, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -88884,26 +88884,26 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a, ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v4, s30, 0 -; GFX9-NEXT: v_writelane_b32 v4, s31, 1 -; GFX9-NEXT: v_writelane_b32 v4, s34, 2 -; GFX9-NEXT: v_writelane_b32 v4, s35, 3 -; GFX9-NEXT: v_writelane_b32 v4, s36, 4 -; GFX9-NEXT: v_writelane_b32 v4, s37, 5 -; GFX9-NEXT: v_writelane_b32 v4, s38, 6 -; GFX9-NEXT: v_writelane_b32 v4, s39, 7 -; GFX9-NEXT: v_writelane_b32 v4, s48, 8 -; GFX9-NEXT: v_writelane_b32 v4, s49, 9 -; GFX9-NEXT: v_writelane_b32 v4, s50, 10 -; GFX9-NEXT: v_writelane_b32 v4, s51, 11 -; GFX9-NEXT: v_writelane_b32 v4, s52, 12 -; GFX9-NEXT: v_writelane_b32 v4, s53, 13 +; GFX9-NEXT: v_writelane_b32 v4, s34, 0 +; GFX9-NEXT: v_writelane_b32 v4, s35, 1 +; GFX9-NEXT: v_writelane_b32 v4, s36, 2 +; GFX9-NEXT: v_writelane_b32 v4, s37, 3 +; GFX9-NEXT: v_writelane_b32 v4, s38, 4 +; GFX9-NEXT: v_writelane_b32 v4, s39, 5 +; GFX9-NEXT: v_writelane_b32 v4, s48, 6 +; GFX9-NEXT: v_writelane_b32 v4, s49, 7 +; GFX9-NEXT: v_writelane_b32 v4, s50, 8 +; GFX9-NEXT: v_writelane_b32 v4, s51, 9 +; GFX9-NEXT: v_writelane_b32 v4, s52, 10 +; GFX9-NEXT: v_writelane_b32 v4, s53, 11 +; GFX9-NEXT: v_writelane_b32 v4, s54, 12 +; GFX9-NEXT: v_writelane_b32 v4, s55, 13 +; GFX9-NEXT: v_writelane_b32 v4, s30, 14 +; GFX9-NEXT: v_writelane_b32 v4, s31, 15 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: v_writelane_b32 v4, s54, 14 ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 ; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v2 -; GFX9-NEXT: v_writelane_b32 v4, s55, 15 ; GFX9-NEXT: s_cbranch_scc0 .LBB109_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s92, s5, 24 @@ -89541,23 +89541,23 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a, ; GFX9-NEXT: s_or_b32 s4, s4, s5 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_readlane_b32 s30, v4, 14 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60 -; GFX9-NEXT: v_readlane_b32 s55, v4, 15 -; GFX9-NEXT: v_readlane_b32 s54, v4, 14 -; GFX9-NEXT: v_readlane_b32 s53, v4, 13 -; GFX9-NEXT: v_readlane_b32 s52, v4, 12 -; GFX9-NEXT: v_readlane_b32 s51, v4, 11 -; GFX9-NEXT: v_readlane_b32 s50, v4, 10 -; GFX9-NEXT: v_readlane_b32 s49, v4, 9 -; GFX9-NEXT: v_readlane_b32 s48, v4, 8 -; GFX9-NEXT: v_readlane_b32 s39, v4, 7 -; GFX9-NEXT: v_readlane_b32 s38, v4, 6 -; GFX9-NEXT: v_readlane_b32 s37, v4, 5 -; GFX9-NEXT: v_readlane_b32 s36, v4, 4 -; GFX9-NEXT: v_readlane_b32 s35, v4, 3 -; GFX9-NEXT: v_readlane_b32 s34, v4, 2 -; GFX9-NEXT: v_readlane_b32 s31, v4, 1 -; GFX9-NEXT: v_readlane_b32 s30, v4, 0 +; GFX9-NEXT: v_readlane_b32 s31, v4, 15 +; GFX9-NEXT: v_readlane_b32 s55, v4, 13 +; GFX9-NEXT: v_readlane_b32 s54, v4, 12 +; GFX9-NEXT: v_readlane_b32 s53, v4, 11 +; GFX9-NEXT: v_readlane_b32 s52, v4, 10 +; GFX9-NEXT: v_readlane_b32 s51, v4, 9 +; GFX9-NEXT: v_readlane_b32 s50, v4, 8 +; GFX9-NEXT: v_readlane_b32 s49, v4, 7 +; GFX9-NEXT: v_readlane_b32 s48, v4, 6 +; GFX9-NEXT: v_readlane_b32 s39, v4, 5 +; GFX9-NEXT: v_readlane_b32 s38, v4, 4 +; GFX9-NEXT: v_readlane_b32 s37, v4, 3 +; GFX9-NEXT: v_readlane_b32 s36, v4, 2 +; GFX9-NEXT: v_readlane_b32 s35, v4, 1 +; GFX9-NEXT: v_readlane_b32 s34, v4, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -89620,19 +89620,19 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a, ; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX11-NEXT: scratch_store_b32 off, v17, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v17, s30, 0 +; GFX11-NEXT: v_writelane_b32 v17, s34, 0 +; GFX11-NEXT: v_writelane_b32 v17, s35, 1 +; GFX11-NEXT: v_writelane_b32 v17, s36, 2 +; GFX11-NEXT: v_writelane_b32 v17, s37, 3 +; GFX11-NEXT: v_writelane_b32 v17, s38, 4 +; GFX11-NEXT: v_writelane_b32 v17, s39, 5 +; GFX11-NEXT: v_writelane_b32 v17, s48, 6 +; GFX11-NEXT: v_writelane_b32 v17, s50, 7 +; GFX11-NEXT: v_writelane_b32 v17, s51, 8 +; GFX11-NEXT: v_writelane_b32 v17, s30, 9 +; GFX11-NEXT: v_writelane_b32 v17, s31, 10 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_mov_b32 vcc_lo, 0 -; GFX11-NEXT: v_writelane_b32 v17, s31, 1 -; GFX11-NEXT: v_writelane_b32 v17, s34, 2 -; GFX11-NEXT: v_writelane_b32 v17, s35, 3 -; GFX11-NEXT: v_writelane_b32 v17, s36, 4 -; GFX11-NEXT: v_writelane_b32 v17, s37, 5 -; GFX11-NEXT: v_writelane_b32 v17, s38, 6 -; GFX11-NEXT: v_writelane_b32 v17, s39, 7 -; GFX11-NEXT: v_writelane_b32 v17, s48, 8 -; GFX11-NEXT: v_writelane_b32 v17, s50, 9 -; GFX11-NEXT: v_writelane_b32 v17, s51, 10 ; GFX11-NEXT: s_cbranch_scc0 .LBB109_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false ; GFX11-NEXT: s_lshr_b32 s62, s27, 24 @@ -90280,22 +90280,22 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a, ; GFX11-NEXT: s_or_b32 s3, s4, s5 ; GFX11-NEXT: v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v14, s1 ; GFX11-NEXT: v_dual_mov_b32 v15, s2 :: v_dual_mov_b32 v16, s3 +; GFX11-NEXT: v_readlane_b32 s30, v17, 9 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16 ; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32 ; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:48 -; GFX11-NEXT: v_readlane_b32 s51, v17, 10 -; GFX11-NEXT: v_readlane_b32 s50, v17, 9 -; GFX11-NEXT: v_readlane_b32 s48, v17, 8 -; GFX11-NEXT: v_readlane_b32 s39, v17, 7 -; GFX11-NEXT: v_readlane_b32 s38, v17, 6 -; GFX11-NEXT: v_readlane_b32 s37, v17, 5 -; GFX11-NEXT: v_readlane_b32 s36, v17, 4 -; GFX11-NEXT: v_readlane_b32 s35, v17, 3 -; GFX11-NEXT: v_readlane_b32 s34, v17, 2 -; GFX11-NEXT: v_readlane_b32 s31, v17, 1 -; GFX11-NEXT: v_readlane_b32 s30, v17, 0 +; GFX11-NEXT: v_readlane_b32 s31, v17, 10 +; GFX11-NEXT: v_readlane_b32 s51, v17, 8 +; GFX11-NEXT: v_readlane_b32 s50, v17, 7 +; GFX11-NEXT: v_readlane_b32 s48, v17, 6 +; GFX11-NEXT: v_readlane_b32 s39, v17, 5 +; GFX11-NEXT: v_readlane_b32 s38, v17, 4 +; GFX11-NEXT: v_readlane_b32 s37, v17, 3 +; GFX11-NEXT: v_readlane_b32 s36, v17, 2 +; GFX11-NEXT: v_readlane_b32 s35, v17, 1 +; GFX11-NEXT: v_readlane_b32 s34, v17, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v17, off, s32 ; 4-byte Folded Reload ; GFX11-NEXT: s_mov_b32 exec_lo, s0 diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll index 5d4df4bde1af8..07c574944ad4e 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll @@ -656,36 +656,36 @@ define inreg <18 x i32> @bitcast_v18f32_to_v18i32_scalar(<18 x float> inreg %a, ; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v32, s36, 0 +; GFX11-NEXT: v_writelane_b32 v32, s37, 1 +; GFX11-NEXT: v_writelane_b32 v32, s38, 2 +; GFX11-NEXT: v_writelane_b32 v32, s39, 3 +; GFX11-NEXT: v_writelane_b32 v32, s48, 4 +; GFX11-NEXT: v_writelane_b32 v32, s49, 5 +; GFX11-NEXT: v_writelane_b32 v32, s50, 6 +; GFX11-NEXT: v_writelane_b32 v32, s51, 7 +; GFX11-NEXT: v_writelane_b32 v32, s52, 8 +; GFX11-NEXT: v_writelane_b32 v32, s53, 9 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: s_mov_b32 s53, s29 +; GFX11-NEXT: s_mov_b32 s52, s28 +; GFX11-NEXT: s_mov_b32 s51, s27 +; GFX11-NEXT: s_mov_b32 s50, s26 +; GFX11-NEXT: s_mov_b32 s49, s25 +; GFX11-NEXT: s_mov_b32 s48, s24 ; GFX11-NEXT: s_mov_b32 s47, s23 ; GFX11-NEXT: s_mov_b32 s46, s22 ; GFX11-NEXT: s_mov_b32 s45, s21 -; GFX11-NEXT: v_writelane_b32 v32, s37, 1 ; GFX11-NEXT: s_mov_b32 s44, s20 ; GFX11-NEXT: s_mov_b32 s43, s19 ; GFX11-NEXT: s_mov_b32 s42, s18 ; GFX11-NEXT: s_mov_b32 s41, s17 -; GFX11-NEXT: v_writelane_b32 v32, s38, 2 ; GFX11-NEXT: s_mov_b32 s40, s16 +; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s38, s2 ; GFX11-NEXT: s_mov_b32 s37, s1 ; GFX11-NEXT: s_mov_b32 s36, s0 -; GFX11-NEXT: v_writelane_b32 v32, s39, 3 -; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo -; GFX11-NEXT: v_writelane_b32 v32, s48, 4 -; GFX11-NEXT: s_mov_b32 s48, s24 -; GFX11-NEXT: v_writelane_b32 v32, s49, 5 -; GFX11-NEXT: s_mov_b32 s49, s25 -; GFX11-NEXT: v_writelane_b32 v32, s50, 6 -; GFX11-NEXT: s_mov_b32 s50, s26 -; GFX11-NEXT: v_writelane_b32 v32, s51, 7 -; GFX11-NEXT: s_mov_b32 s51, s27 -; GFX11-NEXT: v_writelane_b32 v32, s52, 8 -; GFX11-NEXT: s_mov_b32 s52, s28 -; GFX11-NEXT: v_writelane_b32 v32, s53, 9 -; GFX11-NEXT: s_mov_b32 s53, s29 ; GFX11-NEXT: s_cbranch_scc0 .LBB3_3 ; GFX11-NEXT: ; %bb.1: ; %Flow ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 @@ -2075,36 +2075,36 @@ define inreg <18 x i32> @bitcast_v9f64_to_v18i32_scalar(<9 x double> inreg %a, i ; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v32, s36, 0 +; GFX11-NEXT: v_writelane_b32 v32, s37, 1 +; GFX11-NEXT: v_writelane_b32 v32, s38, 2 +; GFX11-NEXT: v_writelane_b32 v32, s39, 3 +; GFX11-NEXT: v_writelane_b32 v32, s48, 4 +; GFX11-NEXT: v_writelane_b32 v32, s49, 5 +; GFX11-NEXT: v_writelane_b32 v32, s50, 6 +; GFX11-NEXT: v_writelane_b32 v32, s51, 7 +; GFX11-NEXT: v_writelane_b32 v32, s52, 8 +; GFX11-NEXT: v_writelane_b32 v32, s53, 9 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: s_mov_b32 s53, s29 +; GFX11-NEXT: s_mov_b32 s52, s28 +; GFX11-NEXT: s_mov_b32 s51, s27 +; GFX11-NEXT: s_mov_b32 s50, s26 +; GFX11-NEXT: s_mov_b32 s49, s25 +; GFX11-NEXT: s_mov_b32 s48, s24 ; GFX11-NEXT: s_mov_b32 s47, s23 ; GFX11-NEXT: s_mov_b32 s46, s22 ; GFX11-NEXT: s_mov_b32 s45, s21 -; GFX11-NEXT: v_writelane_b32 v32, s37, 1 ; GFX11-NEXT: s_mov_b32 s44, s20 ; GFX11-NEXT: s_mov_b32 s43, s19 ; GFX11-NEXT: s_mov_b32 s42, s18 ; GFX11-NEXT: s_mov_b32 s41, s17 -; GFX11-NEXT: v_writelane_b32 v32, s38, 2 ; GFX11-NEXT: s_mov_b32 s40, s16 +; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s38, s2 ; GFX11-NEXT: s_mov_b32 s37, s1 ; GFX11-NEXT: s_mov_b32 s36, s0 -; GFX11-NEXT: v_writelane_b32 v32, s39, 3 -; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo -; GFX11-NEXT: v_writelane_b32 v32, s48, 4 -; GFX11-NEXT: s_mov_b32 s48, s24 -; GFX11-NEXT: v_writelane_b32 v32, s49, 5 -; GFX11-NEXT: s_mov_b32 s49, s25 -; GFX11-NEXT: v_writelane_b32 v32, s50, 6 -; GFX11-NEXT: s_mov_b32 s50, s26 -; GFX11-NEXT: v_writelane_b32 v32, s51, 7 -; GFX11-NEXT: s_mov_b32 s51, s27 -; GFX11-NEXT: v_writelane_b32 v32, s52, 8 -; GFX11-NEXT: s_mov_b32 s52, s28 -; GFX11-NEXT: v_writelane_b32 v32, s53, 9 -; GFX11-NEXT: s_mov_b32 s53, s29 ; GFX11-NEXT: s_cbranch_scc0 .LBB11_3 ; GFX11-NEXT: ; %bb.1: ; %Flow ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 @@ -3806,7 +3806,6 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v36i16_to_v18i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -3823,6 +3822,7 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: v_mov_b32_e32 v33, v16 ; GFX9-NEXT: v_mov_b32_e32 v41, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -4121,13 +4121,13 @@ define inreg <18 x i32> @bitcast_v36i16_to_v18i32_scalar(<36 x i16> inreg %a, i3 ; SI-LABEL: bitcast_v36i16_to_v18i32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22 ; SI-NEXT: v_mov_b32_e32 v32, v20 ; SI-NEXT: v_mov_b32_e32 v33, v18 ; SI-NEXT: v_mov_b32_e32 v34, v16 @@ -4710,7 +4710,6 @@ define <36 x half> @bitcast_v18i32_to_v36f16(<18 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v18i32_to_v36f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill @@ -4718,6 +4717,7 @@ define <36 x half> @bitcast_v18i32_to_v36f16(<18 x i32> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: ; implicit-def: $vgpr45 ; SI-NEXT: ; implicit-def: $vgpr46 ; SI-NEXT: ; implicit-def: $vgpr43 @@ -6669,7 +6669,6 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v36f16_to_v18i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -6686,6 +6685,7 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: v_mov_b32_e32 v33, v16 ; GFX9-NEXT: v_mov_b32_e32 v41, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -7970,36 +7970,36 @@ define inreg <9 x i64> @bitcast_v18f32_to_v9i64_scalar(<18 x float> inreg %a, i3 ; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v32, s36, 0 +; GFX11-NEXT: v_writelane_b32 v32, s37, 1 +; GFX11-NEXT: v_writelane_b32 v32, s38, 2 +; GFX11-NEXT: v_writelane_b32 v32, s39, 3 +; GFX11-NEXT: v_writelane_b32 v32, s48, 4 +; GFX11-NEXT: v_writelane_b32 v32, s49, 5 +; GFX11-NEXT: v_writelane_b32 v32, s50, 6 +; GFX11-NEXT: v_writelane_b32 v32, s51, 7 +; GFX11-NEXT: v_writelane_b32 v32, s52, 8 +; GFX11-NEXT: v_writelane_b32 v32, s53, 9 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: s_mov_b32 s53, s29 +; GFX11-NEXT: s_mov_b32 s52, s28 +; GFX11-NEXT: s_mov_b32 s51, s27 +; GFX11-NEXT: s_mov_b32 s50, s26 +; GFX11-NEXT: s_mov_b32 s49, s25 +; GFX11-NEXT: s_mov_b32 s48, s24 ; GFX11-NEXT: s_mov_b32 s47, s23 ; GFX11-NEXT: s_mov_b32 s46, s22 ; GFX11-NEXT: s_mov_b32 s45, s21 -; GFX11-NEXT: v_writelane_b32 v32, s37, 1 ; GFX11-NEXT: s_mov_b32 s44, s20 ; GFX11-NEXT: s_mov_b32 s43, s19 ; GFX11-NEXT: s_mov_b32 s42, s18 ; GFX11-NEXT: s_mov_b32 s41, s17 -; GFX11-NEXT: v_writelane_b32 v32, s38, 2 ; GFX11-NEXT: s_mov_b32 s40, s16 +; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s38, s2 ; GFX11-NEXT: s_mov_b32 s37, s1 ; GFX11-NEXT: s_mov_b32 s36, s0 -; GFX11-NEXT: v_writelane_b32 v32, s39, 3 -; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo -; GFX11-NEXT: v_writelane_b32 v32, s48, 4 -; GFX11-NEXT: s_mov_b32 s48, s24 -; GFX11-NEXT: v_writelane_b32 v32, s49, 5 -; GFX11-NEXT: s_mov_b32 s49, s25 -; GFX11-NEXT: v_writelane_b32 v32, s50, 6 -; GFX11-NEXT: s_mov_b32 s50, s26 -; GFX11-NEXT: v_writelane_b32 v32, s51, 7 -; GFX11-NEXT: s_mov_b32 s51, s27 -; GFX11-NEXT: v_writelane_b32 v32, s52, 8 -; GFX11-NEXT: s_mov_b32 s52, s28 -; GFX11-NEXT: v_writelane_b32 v32, s53, 9 -; GFX11-NEXT: s_mov_b32 s53, s29 ; GFX11-NEXT: s_cbranch_scc0 .LBB21_3 ; GFX11-NEXT: ; %bb.1: ; %Flow ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 @@ -8731,36 +8731,36 @@ define inreg <9 x double> @bitcast_v18f32_to_v9f64_scalar(<18 x float> inreg %a, ; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v32, s36, 0 +; GFX11-NEXT: v_writelane_b32 v32, s37, 1 +; GFX11-NEXT: v_writelane_b32 v32, s38, 2 +; GFX11-NEXT: v_writelane_b32 v32, s39, 3 +; GFX11-NEXT: v_writelane_b32 v32, s48, 4 +; GFX11-NEXT: v_writelane_b32 v32, s49, 5 +; GFX11-NEXT: v_writelane_b32 v32, s50, 6 +; GFX11-NEXT: v_writelane_b32 v32, s51, 7 +; GFX11-NEXT: v_writelane_b32 v32, s52, 8 +; GFX11-NEXT: v_writelane_b32 v32, s53, 9 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: s_mov_b32 s53, s29 +; GFX11-NEXT: s_mov_b32 s52, s28 +; GFX11-NEXT: s_mov_b32 s51, s27 +; GFX11-NEXT: s_mov_b32 s50, s26 +; GFX11-NEXT: s_mov_b32 s49, s25 +; GFX11-NEXT: s_mov_b32 s48, s24 ; GFX11-NEXT: s_mov_b32 s47, s23 ; GFX11-NEXT: s_mov_b32 s46, s22 ; GFX11-NEXT: s_mov_b32 s45, s21 -; GFX11-NEXT: v_writelane_b32 v32, s37, 1 ; GFX11-NEXT: s_mov_b32 s44, s20 ; GFX11-NEXT: s_mov_b32 s43, s19 ; GFX11-NEXT: s_mov_b32 s42, s18 ; GFX11-NEXT: s_mov_b32 s41, s17 -; GFX11-NEXT: v_writelane_b32 v32, s38, 2 ; GFX11-NEXT: s_mov_b32 s40, s16 +; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s38, s2 ; GFX11-NEXT: s_mov_b32 s37, s1 ; GFX11-NEXT: s_mov_b32 s36, s0 -; GFX11-NEXT: v_writelane_b32 v32, s39, 3 -; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo -; GFX11-NEXT: v_writelane_b32 v32, s48, 4 -; GFX11-NEXT: s_mov_b32 s48, s24 -; GFX11-NEXT: v_writelane_b32 v32, s49, 5 -; GFX11-NEXT: s_mov_b32 s49, s25 -; GFX11-NEXT: v_writelane_b32 v32, s50, 6 -; GFX11-NEXT: s_mov_b32 s50, s26 -; GFX11-NEXT: v_writelane_b32 v32, s51, 7 -; GFX11-NEXT: s_mov_b32 s51, s27 -; GFX11-NEXT: v_writelane_b32 v32, s52, 8 -; GFX11-NEXT: s_mov_b32 s52, s28 -; GFX11-NEXT: v_writelane_b32 v32, s53, 9 -; GFX11-NEXT: s_mov_b32 s53, s29 ; GFX11-NEXT: s_cbranch_scc0 .LBB25_3 ; GFX11-NEXT: ; %bb.1: ; %Flow ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 @@ -9077,36 +9077,36 @@ define inreg <18 x float> @bitcast_v9f64_to_v18f32_scalar(<9 x double> inreg %a, ; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v32, s36, 0 +; GFX11-NEXT: v_writelane_b32 v32, s37, 1 +; GFX11-NEXT: v_writelane_b32 v32, s38, 2 +; GFX11-NEXT: v_writelane_b32 v32, s39, 3 +; GFX11-NEXT: v_writelane_b32 v32, s48, 4 +; GFX11-NEXT: v_writelane_b32 v32, s49, 5 +; GFX11-NEXT: v_writelane_b32 v32, s50, 6 +; GFX11-NEXT: v_writelane_b32 v32, s51, 7 +; GFX11-NEXT: v_writelane_b32 v32, s52, 8 +; GFX11-NEXT: v_writelane_b32 v32, s53, 9 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: s_mov_b32 s53, s29 +; GFX11-NEXT: s_mov_b32 s52, s28 +; GFX11-NEXT: s_mov_b32 s51, s27 +; GFX11-NEXT: s_mov_b32 s50, s26 +; GFX11-NEXT: s_mov_b32 s49, s25 +; GFX11-NEXT: s_mov_b32 s48, s24 ; GFX11-NEXT: s_mov_b32 s47, s23 ; GFX11-NEXT: s_mov_b32 s46, s22 ; GFX11-NEXT: s_mov_b32 s45, s21 -; GFX11-NEXT: v_writelane_b32 v32, s37, 1 ; GFX11-NEXT: s_mov_b32 s44, s20 ; GFX11-NEXT: s_mov_b32 s43, s19 ; GFX11-NEXT: s_mov_b32 s42, s18 ; GFX11-NEXT: s_mov_b32 s41, s17 -; GFX11-NEXT: v_writelane_b32 v32, s38, 2 ; GFX11-NEXT: s_mov_b32 s40, s16 +; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s38, s2 ; GFX11-NEXT: s_mov_b32 s37, s1 ; GFX11-NEXT: s_mov_b32 s36, s0 -; GFX11-NEXT: v_writelane_b32 v32, s39, 3 -; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo -; GFX11-NEXT: v_writelane_b32 v32, s48, 4 -; GFX11-NEXT: s_mov_b32 s48, s24 -; GFX11-NEXT: v_writelane_b32 v32, s49, 5 -; GFX11-NEXT: s_mov_b32 s49, s25 -; GFX11-NEXT: v_writelane_b32 v32, s50, 6 -; GFX11-NEXT: s_mov_b32 s50, s26 -; GFX11-NEXT: v_writelane_b32 v32, s51, 7 -; GFX11-NEXT: s_mov_b32 s51, s27 -; GFX11-NEXT: v_writelane_b32 v32, s52, 8 -; GFX11-NEXT: s_mov_b32 s52, s28 -; GFX11-NEXT: v_writelane_b32 v32, s53, 9 -; GFX11-NEXT: s_mov_b32 s53, s29 ; GFX11-NEXT: s_cbranch_scc0 .LBB27_3 ; GFX11-NEXT: ; %bb.1: ; %Flow ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 @@ -10939,7 +10939,6 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v36i16_to_v18f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -10956,6 +10955,7 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: v_mov_b32_e32 v33, v16 ; GFX9-NEXT: v_mov_b32_e32 v41, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -11254,13 +11254,13 @@ define inreg <18 x float> @bitcast_v36i16_to_v18f32_scalar(<36 x i16> inreg %a, ; SI-LABEL: bitcast_v36i16_to_v18f32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22 ; SI-NEXT: v_mov_b32_e32 v32, v20 ; SI-NEXT: v_mov_b32_e32 v33, v18 ; SI-NEXT: v_mov_b32_e32 v34, v16 @@ -11843,7 +11843,6 @@ define <36 x half> @bitcast_v18f32_to_v36f16(<18 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v18f32_to_v36f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill @@ -11851,6 +11850,7 @@ define <36 x half> @bitcast_v18f32_to_v36f16(<18 x float> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: ; implicit-def: $vgpr45 ; SI-NEXT: ; implicit-def: $vgpr46 ; SI-NEXT: ; implicit-def: $vgpr43 @@ -13940,7 +13940,6 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v36f16_to_v18f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -13957,6 +13956,7 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: v_mov_b32_e32 v33, v16 ; GFX9-NEXT: v_mov_b32_e32 v41, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -15547,36 +15547,36 @@ define inreg <9 x i64> @bitcast_v9f64_to_v9i64_scalar(<9 x double> inreg %a, i32 ; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v32, s36, 0 +; GFX11-NEXT: v_writelane_b32 v32, s37, 1 +; GFX11-NEXT: v_writelane_b32 v32, s38, 2 +; GFX11-NEXT: v_writelane_b32 v32, s39, 3 +; GFX11-NEXT: v_writelane_b32 v32, s48, 4 +; GFX11-NEXT: v_writelane_b32 v32, s49, 5 +; GFX11-NEXT: v_writelane_b32 v32, s50, 6 +; GFX11-NEXT: v_writelane_b32 v32, s51, 7 +; GFX11-NEXT: v_writelane_b32 v32, s52, 8 +; GFX11-NEXT: v_writelane_b32 v32, s53, 9 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: s_mov_b32 s53, s29 +; GFX11-NEXT: s_mov_b32 s52, s28 +; GFX11-NEXT: s_mov_b32 s51, s27 +; GFX11-NEXT: s_mov_b32 s50, s26 +; GFX11-NEXT: s_mov_b32 s49, s25 +; GFX11-NEXT: s_mov_b32 s48, s24 ; GFX11-NEXT: s_mov_b32 s47, s23 ; GFX11-NEXT: s_mov_b32 s46, s22 ; GFX11-NEXT: s_mov_b32 s45, s21 -; GFX11-NEXT: v_writelane_b32 v32, s37, 1 ; GFX11-NEXT: s_mov_b32 s44, s20 ; GFX11-NEXT: s_mov_b32 s43, s19 ; GFX11-NEXT: s_mov_b32 s42, s18 ; GFX11-NEXT: s_mov_b32 s41, s17 -; GFX11-NEXT: v_writelane_b32 v32, s38, 2 ; GFX11-NEXT: s_mov_b32 s40, s16 +; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s38, s2 ; GFX11-NEXT: s_mov_b32 s37, s1 ; GFX11-NEXT: s_mov_b32 s36, s0 -; GFX11-NEXT: v_writelane_b32 v32, s39, 3 -; GFX11-NEXT: s_mov_b32 s39, s3 ; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo -; GFX11-NEXT: v_writelane_b32 v32, s48, 4 -; GFX11-NEXT: s_mov_b32 s48, s24 -; GFX11-NEXT: v_writelane_b32 v32, s49, 5 -; GFX11-NEXT: s_mov_b32 s49, s25 -; GFX11-NEXT: v_writelane_b32 v32, s50, 6 -; GFX11-NEXT: s_mov_b32 s50, s26 -; GFX11-NEXT: v_writelane_b32 v32, s51, 7 -; GFX11-NEXT: s_mov_b32 s51, s27 -; GFX11-NEXT: v_writelane_b32 v32, s52, 8 -; GFX11-NEXT: s_mov_b32 s52, s28 -; GFX11-NEXT: v_writelane_b32 v32, s53, 9 -; GFX11-NEXT: s_mov_b32 s53, s29 ; GFX11-NEXT: s_cbranch_scc0 .LBB39_3 ; GFX11-NEXT: ; %bb.1: ; %Flow ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 @@ -17288,7 +17288,6 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v36i16_to_v9i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -17305,6 +17304,7 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: v_mov_b32_e32 v33, v16 ; GFX9-NEXT: v_mov_b32_e32 v41, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -17603,13 +17603,13 @@ define inreg <9 x i64> @bitcast_v36i16_to_v9i64_scalar(<36 x i16> inreg %a, i32 ; SI-LABEL: bitcast_v36i16_to_v9i64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22 ; SI-NEXT: v_mov_b32_e32 v32, v20 ; SI-NEXT: v_mov_b32_e32 v33, v18 ; SI-NEXT: v_mov_b32_e32 v34, v16 @@ -18192,7 +18192,6 @@ define <36 x half> @bitcast_v9i64_to_v36f16(<9 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v9i64_to_v36f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill @@ -18200,6 +18199,7 @@ define <36 x half> @bitcast_v9i64_to_v36f16(<9 x i64> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: ; implicit-def: $vgpr45 ; SI-NEXT: ; implicit-def: $vgpr46 ; SI-NEXT: ; implicit-def: $vgpr43 @@ -20161,7 +20161,6 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v36f16_to_v9i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -20178,6 +20177,7 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: v_mov_b32_e32 v33, v16 ; GFX9-NEXT: v_mov_b32_e32 v41, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -22864,7 +22864,6 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v36i16_to_v9f64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -22881,6 +22880,7 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: v_mov_b32_e32 v33, v16 ; GFX9-NEXT: v_mov_b32_e32 v41, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -23179,13 +23179,13 @@ define inreg <9 x double> @bitcast_v36i16_to_v9f64_scalar(<36 x i16> inreg %a, i ; SI-LABEL: bitcast_v36i16_to_v9f64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22 ; SI-NEXT: v_mov_b32_e32 v32, v20 ; SI-NEXT: v_mov_b32_e32 v33, v18 ; SI-NEXT: v_mov_b32_e32 v34, v16 @@ -23768,7 +23768,6 @@ define <36 x half> @bitcast_v9f64_to_v36f16(<9 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v9f64_to_v36f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill @@ -23776,6 +23775,7 @@ define <36 x half> @bitcast_v9f64_to_v36f16(<9 x double> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: ; implicit-def: $vgpr45 ; SI-NEXT: ; implicit-def: $vgpr46 ; SI-NEXT: ; implicit-def: $vgpr43 @@ -25787,7 +25787,6 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v36f16_to_v9f64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -25804,6 +25803,7 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v17 ; GFX9-NEXT: v_mov_b32_e32 v33, v16 ; GFX9-NEXT: v_mov_b32_e32 v41, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -27586,8 +27586,6 @@ define inreg <36 x half> @bitcast_v36i16_to_v36f16_scalar(<36 x i16> inreg %a, i ; SI-LABEL: bitcast_v36i16_to_v36f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill @@ -27599,6 +27597,8 @@ define inreg <36 x half> @bitcast_v36i16_to_v36f16_scalar(<36 x i16> inreg %a, i ; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: s_cbranch_scc0 .LBB57_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_waitcnt expcnt(4) diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll index 44cfd6c28ca6a..1648368af460a 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll @@ -4019,7 +4019,6 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v40i16_to_v20i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -4036,6 +4035,7 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: v_mov_b32_e32 v33, v18 ; GFX9-NEXT: v_mov_b32_e32 v43, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -4376,7 +4376,6 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3 ; SI-LABEL: bitcast_v40i16_to_v20i32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill @@ -4387,6 +4386,7 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3 ; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; SI-NEXT: v_mov_b32_e32 v32, v24 ; SI-NEXT: v_mov_b32_e32 v33, v22 ; SI-NEXT: v_mov_b32_e32 v34, v20 @@ -4913,85 +4913,157 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v20i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 ; GFX11-TRUE16-NEXT: s_clause 0xa ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 ; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 @@ -5289,7 +5361,6 @@ define <40 x half> @bitcast_v20i32_to_v40f16(<20 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v20i32_to_v40f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill @@ -5303,6 +5374,7 @@ define <40 x half> @bitcast_v20i32_to_v40f16(<20 x i32> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21 ; SI-NEXT: ; implicit-def: $vgpr59 ; SI-NEXT: ; implicit-def: $vgpr60 ; SI-NEXT: ; implicit-def: $vgpr57 @@ -7495,7 +7567,6 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v40f16_to_v20i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -7512,6 +7583,7 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: v_mov_b32_e32 v33, v18 ; GFX9-NEXT: v_mov_b32_e32 v43, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -8519,85 +8591,157 @@ define inreg <20 x i32> @bitcast_v40f16_to_v20i32_scalar(<40 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v20i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 ; GFX11-TRUE16-NEXT: s_clause 0xa ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 ; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 @@ -12218,7 +12362,6 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v40i16_to_v20f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -12235,6 +12378,7 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: v_mov_b32_e32 v33, v18 ; GFX9-NEXT: v_mov_b32_e32 v43, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -12575,7 +12719,6 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a, ; SI-LABEL: bitcast_v40i16_to_v20f32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill @@ -12586,6 +12729,7 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a, ; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; SI-NEXT: v_mov_b32_e32 v32, v24 ; SI-NEXT: v_mov_b32_e32 v33, v22 ; SI-NEXT: v_mov_b32_e32 v34, v20 @@ -13112,85 +13256,157 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v20f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 ; GFX11-TRUE16-NEXT: s_clause 0xa ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 ; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 @@ -13488,7 +13704,6 @@ define <40 x half> @bitcast_v20f32_to_v40f16(<20 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v20f32_to_v40f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill @@ -13502,6 +13717,7 @@ define <40 x half> @bitcast_v20f32_to_v40f16(<20 x float> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21 ; SI-NEXT: ; implicit-def: $vgpr59 ; SI-NEXT: ; implicit-def: $vgpr60 ; SI-NEXT: ; implicit-def: $vgpr57 @@ -14276,6 +14492,9 @@ define inreg <40 x half> @bitcast_v20f32_to_v40f16_scalar(<20 x float> inreg %a, ; SI-LABEL: bitcast_v20f32_to_v40f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; SI-NEXT: v_readfirstlane_b32 s11, v1 ; SI-NEXT: v_readfirstlane_b32 s10, v2 @@ -14284,9 +14503,6 @@ define inreg <40 x half> @bitcast_v20f32_to_v40f16_scalar(<20 x float> inreg %a, ; SI-NEXT: v_readfirstlane_b32 s6, v5 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v6 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB33_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -15808,7 +16024,6 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v40f16_to_v20f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -15825,6 +16040,7 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: v_mov_b32_e32 v33, v18 ; GFX9-NEXT: v_mov_b32_e32 v43, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -16832,85 +17048,157 @@ define inreg <20 x float> @bitcast_v40f16_to_v20f32_scalar(<40 x half> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v20f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 ; GFX11-TRUE16-NEXT: s_clause 0xa ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 ; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 @@ -19727,7 +20015,6 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v40i16_to_v10i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -19744,6 +20031,7 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: v_mov_b32_e32 v33, v18 ; GFX9-NEXT: v_mov_b32_e32 v43, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -20084,7 +20372,6 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3 ; SI-LABEL: bitcast_v40i16_to_v10i64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill @@ -20095,6 +20382,7 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3 ; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; SI-NEXT: v_mov_b32_e32 v32, v24 ; SI-NEXT: v_mov_b32_e32 v33, v22 ; SI-NEXT: v_mov_b32_e32 v34, v20 @@ -20621,85 +20909,157 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v10i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 ; GFX11-TRUE16-NEXT: s_clause 0xa ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 ; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 @@ -20997,7 +21357,6 @@ define <40 x half> @bitcast_v10i64_to_v40f16(<10 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v10i64_to_v40f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill @@ -21011,6 +21370,7 @@ define <40 x half> @bitcast_v10i64_to_v40f16(<10 x i64> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21 ; SI-NEXT: ; implicit-def: $vgpr59 ; SI-NEXT: ; implicit-def: $vgpr60 ; SI-NEXT: ; implicit-def: $vgpr57 @@ -23213,7 +23573,6 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v40f16_to_v10i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -23230,6 +23589,7 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: v_mov_b32_e32 v33, v18 ; GFX9-NEXT: v_mov_b32_e32 v43, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -24237,85 +24597,157 @@ define inreg <10 x i64> @bitcast_v40f16_to_v10i64_scalar(<40 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v10i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 ; GFX11-TRUE16-NEXT: s_clause 0xa ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 ; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 @@ -26466,7 +26898,6 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v40i16_to_v10f64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -26483,6 +26914,7 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: v_mov_b32_e32 v33, v18 ; GFX9-NEXT: v_mov_b32_e32 v43, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -26823,7 +27255,6 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a, ; SI-LABEL: bitcast_v40i16_to_v10f64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill @@ -26834,6 +27265,7 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a, ; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; SI-NEXT: v_mov_b32_e32 v32, v24 ; SI-NEXT: v_mov_b32_e32 v33, v22 ; SI-NEXT: v_mov_b32_e32 v34, v20 @@ -27360,85 +27792,157 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v10f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 ; GFX11-TRUE16-NEXT: s_clause 0xa ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 ; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 @@ -27736,7 +28240,6 @@ define <40 x half> @bitcast_v10f64_to_v40f16(<10 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v10f64_to_v40f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill @@ -27750,6 +28253,7 @@ define <40 x half> @bitcast_v10f64_to_v40f16(<10 x double> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21 ; SI-NEXT: ; implicit-def: $vgpr59 ; SI-NEXT: ; implicit-def: $vgpr60 ; SI-NEXT: ; implicit-def: $vgpr57 @@ -28484,6 +28988,10 @@ define inreg <40 x half> @bitcast_v10f64_to_v40f16_scalar(<10 x double> inreg %a ; SI-LABEL: bitcast_v10f64_to_v40f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; SI-NEXT: v_readfirstlane_b32 s8, v1 ; SI-NEXT: v_readfirstlane_b32 s9, v2 @@ -28492,10 +29000,6 @@ define inreg <40 x half> @bitcast_v10f64_to_v40f16_scalar(<10 x double> inreg %a ; SI-NEXT: v_readfirstlane_b32 s4, v5 ; SI-NEXT: s_and_b64 s[10:11], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v6 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB53_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s10, s5, 16 @@ -29989,7 +30493,6 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v40f16_to_v10f64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -30006,6 +30509,7 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v19 ; GFX9-NEXT: v_mov_b32_e32 v33, v18 ; GFX9-NEXT: v_mov_b32_e32 v43, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -31013,85 +31517,157 @@ define inreg <10 x double> @bitcast_v40f16_to_v10f64_scalar(<40 x half> inreg %a ; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v10f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 ; GFX11-TRUE16-NEXT: s_clause 0xa ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 ; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 @@ -32303,8 +32879,6 @@ define inreg <40 x half> @bitcast_v40i16_to_v40f16_scalar(<40 x i16> inreg %a, i ; SI-LABEL: bitcast_v40i16_to_v40f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -32321,6 +32895,8 @@ define inreg <40 x half> @bitcast_v40i16_to_v40f16_scalar(<40 x i16> inreg %a, i ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: s_cbranch_scc0 .LBB57_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_cvt_f32_f16_e32 v30, v15 diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll index 87d5157b3c340..010c7f18fa513 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll @@ -4340,7 +4340,6 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v44i16_to_v22i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -4357,6 +4356,7 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: v_mov_b32_e32 v33, v20 ; GFX9-NEXT: v_mov_b32_e32 v45, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -4739,7 +4739,6 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3 ; SI-LABEL: bitcast_v44i16_to_v22i32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -4754,6 +4753,7 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3 ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; SI-NEXT: v_mov_b32_e32 v32, v28 ; SI-NEXT: v_mov_b32_e32 v33, v26 ; SI-NEXT: v_mov_b32_e32 v34, v24 @@ -5328,87 +5328,161 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v22i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52 ; GFX11-TRUE16-NEXT: s_clause 0xc ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 @@ -5722,10 +5796,6 @@ define <44 x half> @bitcast_v22i32_to_v44f16(<22 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v22i32_to_v44f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr27 -; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -5742,6 +5812,10 @@ define <44 x half> @bitcast_v22i32_to_v44f16(<22 x i32> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23 +; SI-NEXT: ; implicit-def: $vgpr26 +; SI-NEXT: ; implicit-def: $vgpr27 +; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; implicit-def: $vgpr24 ; SI-NEXT: ; implicit-def: $vgpr25 ; SI-NEXT: ; implicit-def: $vgpr63 @@ -8182,7 +8256,6 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v44f16_to_v22i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -8199,6 +8272,7 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: v_mov_b32_e32 v33, v20 ; GFX9-NEXT: v_mov_b32_e32 v45, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -9310,87 +9384,161 @@ define inreg <22 x i32> @bitcast_v44f16_to_v22i32_scalar(<44 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v22i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52 ; GFX11-TRUE16-NEXT: s_clause 0xc ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 @@ -13303,7 +13451,6 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v44i16_to_v22f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -13320,6 +13467,7 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: v_mov_b32_e32 v33, v20 ; GFX9-NEXT: v_mov_b32_e32 v45, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -13702,7 +13850,6 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a, ; SI-LABEL: bitcast_v44i16_to_v22f32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -13717,6 +13864,7 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a, ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; SI-NEXT: v_mov_b32_e32 v32, v28 ; SI-NEXT: v_mov_b32_e32 v33, v26 ; SI-NEXT: v_mov_b32_e32 v34, v24 @@ -14291,87 +14439,161 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v22f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52 ; GFX11-TRUE16-NEXT: s_clause 0xc ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 @@ -14685,10 +14907,6 @@ define <44 x half> @bitcast_v22f32_to_v44f16(<22 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v22f32_to_v44f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr27 -; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -14705,6 +14923,10 @@ define <44 x half> @bitcast_v22f32_to_v44f16(<22 x float> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23 +; SI-NEXT: ; implicit-def: $vgpr26 +; SI-NEXT: ; implicit-def: $vgpr27 +; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; implicit-def: $vgpr24 ; SI-NEXT: ; implicit-def: $vgpr25 ; SI-NEXT: ; implicit-def: $vgpr63 @@ -15560,6 +15782,14 @@ define inreg <44 x half> @bitcast_v22f32_to_v44f16_scalar(<22 x float> inreg %a, ; SI-LABEL: bitcast_v22f32_to_v44f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 ; SI-NEXT: v_readfirstlane_b32 s13, v1 ; SI-NEXT: v_readfirstlane_b32 s12, v2 @@ -15570,14 +15800,6 @@ define inreg <44 x half> @bitcast_v22f32_to_v44f16_scalar(<22 x float> inreg %a, ; SI-NEXT: v_readfirstlane_b32 s6, v7 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v8 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB33_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -17278,7 +17500,6 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v44f16_to_v22f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -17295,6 +17516,7 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: v_mov_b32_e32 v33, v20 ; GFX9-NEXT: v_mov_b32_e32 v45, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -18406,87 +18628,161 @@ define inreg <22 x float> @bitcast_v44f16_to_v22f32_scalar(<44 x half> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v22f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52 ; GFX11-TRUE16-NEXT: s_clause 0xc ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 @@ -21552,7 +21848,6 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v44i16_to_v11i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -21569,6 +21864,7 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: v_mov_b32_e32 v33, v20 ; GFX9-NEXT: v_mov_b32_e32 v45, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -21951,7 +22247,6 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3 ; SI-LABEL: bitcast_v44i16_to_v11i64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -21966,6 +22261,7 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3 ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; SI-NEXT: v_mov_b32_e32 v32, v28 ; SI-NEXT: v_mov_b32_e32 v33, v26 ; SI-NEXT: v_mov_b32_e32 v34, v24 @@ -22540,87 +22836,161 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v11i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52 ; GFX11-TRUE16-NEXT: s_clause 0xc ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 @@ -22934,10 +23304,6 @@ define <44 x half> @bitcast_v11i64_to_v44f16(<11 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v11i64_to_v44f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr27 -; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -22954,6 +23320,10 @@ define <44 x half> @bitcast_v11i64_to_v44f16(<11 x i64> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23 +; SI-NEXT: ; implicit-def: $vgpr26 +; SI-NEXT: ; implicit-def: $vgpr27 +; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; implicit-def: $vgpr24 ; SI-NEXT: ; implicit-def: $vgpr25 ; SI-NEXT: ; implicit-def: $vgpr63 @@ -25406,7 +25776,6 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v44f16_to_v11i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -25423,6 +25792,7 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: v_mov_b32_e32 v33, v20 ; GFX9-NEXT: v_mov_b32_e32 v45, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -26534,87 +26904,161 @@ define inreg <11 x i64> @bitcast_v44f16_to_v11i64_scalar(<44 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v11i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52 ; GFX11-TRUE16-NEXT: s_clause 0xc ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 @@ -28968,7 +29412,6 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) { ; GFX9-LABEL: bitcast_v44i16_to_v11f64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -28985,6 +29428,7 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: v_mov_b32_e32 v33, v20 ; GFX9-NEXT: v_mov_b32_e32 v45, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -29367,7 +29811,6 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a, ; SI-LABEL: bitcast_v44i16_to_v11f64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -29382,6 +29825,7 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a, ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; SI-NEXT: v_mov_b32_e32 v32, v28 ; SI-NEXT: v_mov_b32_e32 v33, v26 ; SI-NEXT: v_mov_b32_e32 v34, v24 @@ -29956,87 +30400,161 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v11f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52 ; GFX11-TRUE16-NEXT: s_clause 0xc ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 @@ -30350,10 +30868,6 @@ define <44 x half> @bitcast_v11f64_to_v44f16(<11 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v11f64_to_v44f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr27 -; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -30370,6 +30884,10 @@ define <44 x half> @bitcast_v11f64_to_v44f16(<11 x double> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23 +; SI-NEXT: ; implicit-def: $vgpr26 +; SI-NEXT: ; implicit-def: $vgpr27 +; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; implicit-def: $vgpr24 ; SI-NEXT: ; implicit-def: $vgpr25 ; SI-NEXT: ; implicit-def: $vgpr63 @@ -31181,6 +31699,15 @@ define inreg <44 x half> @bitcast_v11f64_to_v44f16_scalar(<11 x double> inreg %a ; SI-LABEL: bitcast_v11f64_to_v44f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 ; SI-NEXT: v_readfirstlane_b32 s10, v1 ; SI-NEXT: v_readfirstlane_b32 s11, v2 @@ -31191,15 +31718,6 @@ define inreg <44 x half> @bitcast_v11f64_to_v44f16_scalar(<11 x double> inreg %a ; SI-NEXT: v_readfirstlane_b32 s4, v7 ; SI-NEXT: s_and_b64 s[12:13], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v8 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB53_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s12, s5, 16 @@ -32867,7 +33385,6 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) { ; GFX9-LABEL: bitcast_v44f16_to_v11f64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -32884,6 +33401,7 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v32, v21 ; GFX9-NEXT: v_mov_b32_e32 v33, v20 ; GFX9-NEXT: v_mov_b32_e32 v45, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32 @@ -33995,87 +34513,161 @@ define inreg <11 x double> @bitcast_v44f16_to_v11f64_scalar(<44 x half> inreg %a ; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v11f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52 ; GFX11-TRUE16-NEXT: s_clause 0xc ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0 ; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 @@ -35429,7 +36021,6 @@ define inreg <44 x half> @bitcast_v44i16_to_v44f16_scalar(<44 x i16> inreg %a, i ; SI-LABEL: bitcast_v44i16_to_v44f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill @@ -35446,7 +36037,8 @@ define inreg <44 x half> @bitcast_v44i16_to_v44f16_scalar(<44 x i16> inreg %a, i ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: s_cbranch_scc0 .LBB57_4 @@ -37436,7 +38028,6 @@ define inreg <44 x i16> @bitcast_v44f16_to_v44i16_scalar(<44 x half> inreg %a, i ; SI-LABEL: bitcast_v44f16_to_v44i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill @@ -37453,6 +38044,7 @@ define inreg <44 x i16> @bitcast_v44f16_to_v44i16_scalar(<44 x half> inreg %a, i ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: s_waitcnt expcnt(6) ; SI-NEXT: v_cvt_f16_f32_e32 v57, v2 ; SI-NEXT: s_waitcnt expcnt(5) @@ -37500,7 +38092,7 @@ define inreg <44 x i16> @bitcast_v44f16_to_v44i16_scalar(<44 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v38, s25 ; SI-NEXT: v_cvt_f16_f32_e32 v16, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v29, s29 -; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: s_cbranch_scc0 .LBB59_4 diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll index fb2e94fc3b87a..3fbedf74d9e3a 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll @@ -2440,8 +2440,8 @@ define <48 x i16> @bitcast_v24i32_to_v48i16(<24 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v24i32_to_v48i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 ; SI-NEXT: ; implicit-def: $vgpr53 ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr51 @@ -3193,10 +3193,11 @@ define inreg <48 x i16> @bitcast_v24i32_to_v48i16_scalar(<24 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v12, s30, 0 -; SI-NEXT: v_writelane_b32 v12, s31, 1 +; SI-NEXT: v_writelane_b32 v12, s34, 0 +; SI-NEXT: v_writelane_b32 v12, s35, 1 +; SI-NEXT: v_writelane_b32 v12, s30, 2 +; SI-NEXT: v_writelane_b32 v12, s31, 3 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 -; SI-NEXT: v_writelane_b32 v12, s34, 2 ; SI-NEXT: v_readfirstlane_b32 s12, v1 ; SI-NEXT: v_readfirstlane_b32 s13, v2 ; SI-NEXT: v_readfirstlane_b32 s10, v3 @@ -3208,7 +3209,6 @@ define inreg <48 x i16> @bitcast_v24i32_to_v48i16_scalar(<24 x i32> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v9 ; SI-NEXT: s_and_b64 s[14:15], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v10 -; SI-NEXT: v_writelane_b32 v12, s35, 3 ; SI-NEXT: s_cbranch_scc0 .LBB13_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s88, s5, 16 @@ -3449,11 +3449,11 @@ define inreg <48 x i16> @bitcast_v24i32_to_v48i16_scalar(<24 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x5c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v12, 2 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s35, v12, 3 -; SI-NEXT: v_readlane_b32 s34, v12, 2 -; SI-NEXT: v_readlane_b32 s31, v12, 1 -; SI-NEXT: v_readlane_b32 s30, v12, 0 +; SI-NEXT: v_readlane_b32 s31, v12, 3 +; SI-NEXT: v_readlane_b32 s35, v12, 1 +; SI-NEXT: v_readlane_b32 s34, v12, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -5655,6 +5655,10 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3 ; GFX9-LABEL: bitcast_v48i16_to_v24i32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v9 ; GFX9-NEXT: v_mov_b32_e32 v33, v8 ; GFX9-NEXT: v_mov_b32_e32 v34, v7 @@ -5680,10 +5684,6 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3 ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34 @@ -5805,89 +5805,165 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v24i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60 ; GFX11-TRUE16-NEXT: s_clause 0xe ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0 @@ -6216,16 +6292,7 @@ end: define <48 x half> @bitcast_v24i32_to_v48f16(<24 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v24i32_to_v48f16: ; SI: ; %bb.0: -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; kill: killed $vgpr35 -; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; kill: killed $vgpr35 -; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -6246,6 +6313,11 @@ define <48 x half> @bitcast_v24i32_to_v48f16(<24 x i32> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr34 ; SI-NEXT: ; kill: killed $vgpr35 ; SI-NEXT: ; kill: killed $vgpr34 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr33 ; SI-NEXT: ; implicit-def: $vgpr30 @@ -6290,6 +6362,10 @@ define <48 x half> @bitcast_v24i32_to_v48f16(<24 x i32> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr34 ; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; kill: killed $vgpr34 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; kill: killed $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -7211,6 +7287,7 @@ define inreg <48 x half> @bitcast_v24i32_to_v48f16_scalar(<24 x i32> inreg %a, i ; SI-LABEL: bitcast_v24i32_to_v48f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; SI-NEXT: v_readfirstlane_b32 s15, v1 ; SI-NEXT: v_readfirstlane_b32 s14, v2 @@ -7223,7 +7300,6 @@ define inreg <48 x half> @bitcast_v24i32_to_v48f16_scalar(<24 x i32> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s6, v9 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v10 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB17_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -10061,6 +10137,10 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i ; GFX9-LABEL: bitcast_v48f16_to_v24i32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v9 ; GFX9-NEXT: v_mov_b32_e32 v33, v8 ; GFX9-NEXT: v_mov_b32_e32 v34, v7 @@ -10086,10 +10166,6 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34 @@ -10213,89 +10289,165 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v24i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60 ; GFX11-TRUE16-NEXT: s_clause 0xe ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0 @@ -12185,8 +12337,8 @@ define <48 x i16> @bitcast_v24f32_to_v48i16(<24 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v24f32_to_v48i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 ; SI-NEXT: ; implicit-def: $vgpr53 ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr51 @@ -12910,6 +13062,9 @@ define inreg <48 x i16> @bitcast_v24f32_to_v48i16_scalar(<24 x float> inreg %a, ; SI-LABEL: bitcast_v24f32_to_v48i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; SI-NEXT: v_mov_b32_e32 v23, s16 ; SI-NEXT: v_mov_b32_e32 v24, s17 @@ -12926,9 +13081,6 @@ define inreg <48 x i16> @bitcast_v24f32_to_v48i16_scalar(<24 x float> inreg %a, ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_mov_b32_e32 v11, s28 ; SI-NEXT: v_mov_b32_e32 v12, s29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB29_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_lshr_b64 v[25:26], v[9:10], 16 @@ -15492,6 +15644,10 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a, ; GFX9-LABEL: bitcast_v48i16_to_v24f32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v9 ; GFX9-NEXT: v_mov_b32_e32 v33, v8 ; GFX9-NEXT: v_mov_b32_e32 v34, v7 @@ -15517,10 +15673,6 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34 @@ -15642,89 +15794,165 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v24f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60 ; GFX11-TRUE16-NEXT: s_clause 0xe ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0 @@ -16053,16 +16281,7 @@ end: define <48 x half> @bitcast_v24f32_to_v48f16(<24 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v24f32_to_v48f16: ; SI: ; %bb.0: -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; kill: killed $vgpr35 -; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; kill: killed $vgpr35 -; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -16083,6 +16302,11 @@ define <48 x half> @bitcast_v24f32_to_v48f16(<24 x float> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr34 ; SI-NEXT: ; kill: killed $vgpr35 ; SI-NEXT: ; kill: killed $vgpr34 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr33 ; SI-NEXT: ; implicit-def: $vgpr30 @@ -16127,6 +16351,10 @@ define <48 x half> @bitcast_v24f32_to_v48f16(<24 x float> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr34 ; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; kill: killed $vgpr34 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; kill: killed $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -17024,18 +17252,6 @@ define inreg <48 x half> @bitcast_v24f32_to_v48f16_scalar(<24 x float> inreg %a, ; SI-LABEL: bitcast_v24f32_to_v48f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 -; SI-NEXT: v_readfirstlane_b32 s15, v1 -; SI-NEXT: v_readfirstlane_b32 s14, v2 -; SI-NEXT: v_readfirstlane_b32 s13, v3 -; SI-NEXT: v_readfirstlane_b32 s12, v4 -; SI-NEXT: v_readfirstlane_b32 s11, v5 -; SI-NEXT: v_readfirstlane_b32 s10, v6 -; SI-NEXT: v_readfirstlane_b32 s8, v7 -; SI-NEXT: v_readfirstlane_b32 s7, v8 -; SI-NEXT: v_readfirstlane_b32 s6, v9 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s9, v10 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill @@ -17049,6 +17265,18 @@ define inreg <48 x half> @bitcast_v24f32_to_v48f16_scalar(<24 x float> inreg %a, ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 +; SI-NEXT: v_readfirstlane_b32 s15, v1 +; SI-NEXT: v_readfirstlane_b32 s14, v2 +; SI-NEXT: v_readfirstlane_b32 s13, v3 +; SI-NEXT: v_readfirstlane_b32 s12, v4 +; SI-NEXT: v_readfirstlane_b32 s11, v5 +; SI-NEXT: v_readfirstlane_b32 s10, v6 +; SI-NEXT: v_readfirstlane_b32 s8, v7 +; SI-NEXT: v_readfirstlane_b32 s7, v8 +; SI-NEXT: v_readfirstlane_b32 s6, v9 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_readfirstlane_b32 s9, v10 ; SI-NEXT: s_cbranch_scc0 .LBB33_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -20039,6 +20267,10 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a, ; GFX9-LABEL: bitcast_v48f16_to_v24f32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v9 ; GFX9-NEXT: v_mov_b32_e32 v33, v8 ; GFX9-NEXT: v_mov_b32_e32 v34, v7 @@ -20064,10 +20296,6 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34 @@ -20191,89 +20419,165 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v24f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60 ; GFX11-TRUE16-NEXT: s_clause 0xe ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0 @@ -21365,8 +21669,8 @@ define <48 x i16> @bitcast_v12i64_to_v48i16(<12 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v12i64_to_v48i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 ; SI-NEXT: ; implicit-def: $vgpr53 ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr50 @@ -22130,10 +22434,11 @@ define inreg <48 x i16> @bitcast_v12i64_to_v48i16_scalar(<12 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v12, s30, 0 -; SI-NEXT: v_writelane_b32 v12, s31, 1 +; SI-NEXT: v_writelane_b32 v12, s34, 0 +; SI-NEXT: v_writelane_b32 v12, s35, 1 +; SI-NEXT: v_writelane_b32 v12, s30, 2 +; SI-NEXT: v_writelane_b32 v12, s31, 3 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 -; SI-NEXT: v_writelane_b32 v12, s34, 2 ; SI-NEXT: v_readfirstlane_b32 s12, v1 ; SI-NEXT: v_readfirstlane_b32 s13, v2 ; SI-NEXT: v_readfirstlane_b32 s10, v3 @@ -22145,7 +22450,6 @@ define inreg <48 x i16> @bitcast_v12i64_to_v48i16_scalar(<12 x i64> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v9 ; SI-NEXT: s_and_b64 s[14:15], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v10 -; SI-NEXT: v_writelane_b32 v12, s35, 3 ; SI-NEXT: s_cbranch_scc0 .LBB41_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s88, s5, 16 @@ -22386,11 +22690,11 @@ define inreg <48 x i16> @bitcast_v12i64_to_v48i16_scalar(<12 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x5c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v12, 2 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s35, v12, 3 -; SI-NEXT: v_readlane_b32 s34, v12, 2 -; SI-NEXT: v_readlane_b32 s31, v12, 1 -; SI-NEXT: v_readlane_b32 s30, v12, 0 +; SI-NEXT: v_readlane_b32 s31, v12, 3 +; SI-NEXT: v_readlane_b32 s35, v12, 1 +; SI-NEXT: v_readlane_b32 s34, v12, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -24592,6 +24896,10 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3 ; GFX9-LABEL: bitcast_v48i16_to_v12i64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v9 ; GFX9-NEXT: v_mov_b32_e32 v33, v8 ; GFX9-NEXT: v_mov_b32_e32 v34, v7 @@ -24617,10 +24925,6 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3 ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34 @@ -24742,89 +25046,165 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v12i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60 ; GFX11-TRUE16-NEXT: s_clause 0xe ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0 @@ -25153,16 +25533,7 @@ end: define <48 x half> @bitcast_v12i64_to_v48f16(<12 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v12i64_to_v48f16: ; SI: ; %bb.0: -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; kill: killed $vgpr35 -; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; kill: killed $vgpr35 -; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -25183,6 +25554,11 @@ define <48 x half> @bitcast_v12i64_to_v48f16(<12 x i64> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr34 ; SI-NEXT: ; kill: killed $vgpr35 ; SI-NEXT: ; kill: killed $vgpr34 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr33 ; SI-NEXT: ; implicit-def: $vgpr30 @@ -25227,6 +25603,10 @@ define <48 x half> @bitcast_v12i64_to_v48f16(<12 x i64> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr34 ; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; kill: killed $vgpr34 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; kill: killed $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -26160,6 +26540,7 @@ define inreg <48 x half> @bitcast_v12i64_to_v48f16_scalar(<12 x i64> inreg %a, i ; SI-LABEL: bitcast_v12i64_to_v48f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; SI-NEXT: v_readfirstlane_b32 s14, v1 ; SI-NEXT: v_readfirstlane_b32 s15, v2 @@ -26172,7 +26553,6 @@ define inreg <48 x half> @bitcast_v12i64_to_v48f16_scalar(<12 x i64> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s6, v9 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v10 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB45_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -29010,6 +29390,10 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i ; GFX9-LABEL: bitcast_v48f16_to_v12i64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v9 ; GFX9-NEXT: v_mov_b32_e32 v33, v8 ; GFX9-NEXT: v_mov_b32_e32 v34, v7 @@ -29035,10 +29419,6 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34 @@ -29162,89 +29542,165 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v12i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60 ; GFX11-TRUE16-NEXT: s_clause 0xe ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0 @@ -29574,8 +30030,8 @@ define <48 x i16> @bitcast_v12f64_to_v48i16(<12 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v12f64_to_v48i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 ; SI-NEXT: ; implicit-def: $vgpr53 ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr50 @@ -30263,6 +30719,9 @@ define inreg <48 x i16> @bitcast_v12f64_to_v48i16_scalar(<12 x double> inreg %a, ; SI-LABEL: bitcast_v12f64_to_v48i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; SI-NEXT: v_mov_b32_e32 v23, s16 ; SI-NEXT: v_mov_b32_e32 v24, s17 @@ -30279,9 +30738,6 @@ define inreg <48 x i16> @bitcast_v12f64_to_v48i16_scalar(<12 x double> inreg %a, ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_mov_b32_e32 v11, s28 ; SI-NEXT: v_mov_b32_e32 v12, s29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB49_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_lshr_b64 v[25:26], v[9:10], 16 @@ -32809,6 +33265,10 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a, ; GFX9-LABEL: bitcast_v48i16_to_v12f64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v9 ; GFX9-NEXT: v_mov_b32_e32 v33, v8 ; GFX9-NEXT: v_mov_b32_e32 v34, v7 @@ -32834,10 +33294,6 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34 @@ -32959,89 +33415,165 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v12f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60 ; GFX11-TRUE16-NEXT: s_clause 0xe ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0 @@ -33370,16 +33902,7 @@ end: define <48 x half> @bitcast_v12f64_to_v48f16(<12 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v12f64_to_v48f16: ; SI: ; %bb.0: -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; kill: killed $vgpr35 -; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; kill: killed $vgpr35 -; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -33400,6 +33923,11 @@ define <48 x half> @bitcast_v12f64_to_v48f16(<12 x double> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr34 ; SI-NEXT: ; kill: killed $vgpr35 ; SI-NEXT: ; kill: killed $vgpr34 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; kill: killed $vgpr34 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr33 ; SI-NEXT: ; implicit-def: $vgpr30 @@ -33444,6 +33972,10 @@ define <48 x half> @bitcast_v12f64_to_v48f16(<12 x double> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr34 ; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; kill: killed $vgpr34 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; kill: killed $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -34293,18 +34825,6 @@ define inreg <48 x half> @bitcast_v12f64_to_v48f16_scalar(<12 x double> inreg %a ; SI-LABEL: bitcast_v12f64_to_v48f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 -; SI-NEXT: v_readfirstlane_b32 s12, v1 -; SI-NEXT: v_readfirstlane_b32 s13, v2 -; SI-NEXT: v_readfirstlane_b32 s10, v3 -; SI-NEXT: v_readfirstlane_b32 s11, v4 -; SI-NEXT: v_readfirstlane_b32 s8, v5 -; SI-NEXT: v_readfirstlane_b32 s9, v6 -; SI-NEXT: v_readfirstlane_b32 s6, v7 -; SI-NEXT: v_readfirstlane_b32 s7, v8 -; SI-NEXT: v_readfirstlane_b32 s4, v9 -; SI-NEXT: s_and_b64 s[14:15], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s5, v10 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -34319,6 +34839,18 @@ define inreg <48 x half> @bitcast_v12f64_to_v48f16_scalar(<12 x double> inreg %a ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 +; SI-NEXT: v_readfirstlane_b32 s12, v1 +; SI-NEXT: v_readfirstlane_b32 s13, v2 +; SI-NEXT: v_readfirstlane_b32 s10, v3 +; SI-NEXT: v_readfirstlane_b32 s11, v4 +; SI-NEXT: v_readfirstlane_b32 s8, v5 +; SI-NEXT: v_readfirstlane_b32 s9, v6 +; SI-NEXT: v_readfirstlane_b32 s6, v7 +; SI-NEXT: v_readfirstlane_b32 s7, v8 +; SI-NEXT: v_readfirstlane_b32 s4, v9 +; SI-NEXT: s_and_b64 s[14:15], vcc, exec +; SI-NEXT: v_readfirstlane_b32 s5, v10 ; SI-NEXT: s_cbranch_scc0 .LBB53_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s14, s5, 16 @@ -37274,6 +37806,10 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a ; GFX9-LABEL: bitcast_v48f16_to_v12f64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v9 ; GFX9-NEXT: v_mov_b32_e32 v33, v8 ; GFX9-NEXT: v_mov_b32_e32 v34, v7 @@ -37299,10 +37835,6 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34 @@ -37426,89 +37958,165 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a ; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v12f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60 ; GFX11-TRUE16-NEXT: s_clause 0xe ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0 diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll index 07cdbef82d892..282e7a7953de6 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll @@ -2570,12 +2570,12 @@ define <52 x i16> @bitcast_v26i32_to_v52i16(<26 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v26i32_to_v52i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: ; implicit-def: $vgpr54 @@ -2866,11 +2866,11 @@ define <52 x i16> @bitcast_v26i32_to_v52i16(<26 x i32> %a, i32 %b) { ; VI-LABEL: bitcast_v26i32_to_v52i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: ; implicit-def: $vgpr43 ; VI-NEXT: ; implicit-def: $vgpr42 ; VI-NEXT: ; implicit-def: $vgpr41 @@ -3047,11 +3047,11 @@ define <52 x i16> @bitcast_v26i32_to_v52i16(<26 x i32> %a, i32 %b) { ; GFX9-LABEL: bitcast_v26i32_to_v52i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: ; implicit-def: $vgpr43 ; GFX9-NEXT: ; implicit-def: $vgpr42 ; GFX9-NEXT: ; implicit-def: $vgpr41 @@ -3412,15 +3412,16 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v14, s30, 0 -; SI-NEXT: v_writelane_b32 v14, s31, 1 -; SI-NEXT: v_writelane_b32 v14, s34, 2 -; SI-NEXT: v_writelane_b32 v14, s35, 3 -; SI-NEXT: v_writelane_b32 v14, s36, 4 -; SI-NEXT: v_writelane_b32 v14, s37, 5 -; SI-NEXT: v_writelane_b32 v14, s38, 6 +; SI-NEXT: v_writelane_b32 v14, s34, 0 +; SI-NEXT: v_writelane_b32 v14, s35, 1 +; SI-NEXT: v_writelane_b32 v14, s36, 2 +; SI-NEXT: v_writelane_b32 v14, s37, 3 +; SI-NEXT: v_writelane_b32 v14, s38, 4 +; SI-NEXT: v_writelane_b32 v14, s39, 5 +; SI-NEXT: v_writelane_b32 v14, s48, 6 +; SI-NEXT: v_writelane_b32 v14, s30, 7 +; SI-NEXT: v_writelane_b32 v14, s31, 8 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 -; SI-NEXT: v_writelane_b32 v14, s39, 7 ; SI-NEXT: v_readfirstlane_b32 s14, v1 ; SI-NEXT: v_readfirstlane_b32 s15, v2 ; SI-NEXT: v_readfirstlane_b32 s12, v3 @@ -3434,7 +3435,6 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v11 ; SI-NEXT: s_and_b64 s[40:41], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v12 -; SI-NEXT: v_writelane_b32 v14, s48, 8 ; SI-NEXT: s_cbranch_scc0 .LBB13_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s92, s5, 16 @@ -3693,16 +3693,16 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x64, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v14, 7 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s48, v14, 8 -; SI-NEXT: v_readlane_b32 s39, v14, 7 -; SI-NEXT: v_readlane_b32 s38, v14, 6 -; SI-NEXT: v_readlane_b32 s37, v14, 5 -; SI-NEXT: v_readlane_b32 s36, v14, 4 -; SI-NEXT: v_readlane_b32 s35, v14, 3 -; SI-NEXT: v_readlane_b32 s34, v14, 2 -; SI-NEXT: v_readlane_b32 s31, v14, 1 -; SI-NEXT: v_readlane_b32 s30, v14, 0 +; SI-NEXT: v_readlane_b32 s31, v14, 8 +; SI-NEXT: v_readlane_b32 s48, v14, 6 +; SI-NEXT: v_readlane_b32 s39, v14, 5 +; SI-NEXT: v_readlane_b32 s38, v14, 4 +; SI-NEXT: v_readlane_b32 s37, v14, 3 +; SI-NEXT: v_readlane_b32 s36, v14, 2 +; SI-NEXT: v_readlane_b32 s35, v14, 1 +; SI-NEXT: v_readlane_b32 s34, v14, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -6114,6 +6114,14 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3 ; GFX9-LABEL: bitcast_v52i16_to_v26i32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v11 ; GFX9-NEXT: v_mov_b32_e32 v33, v10 ; GFX9-NEXT: v_mov_b32_e32 v34, v9 @@ -6141,14 +6149,6 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3 ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34 @@ -6286,90 +6286,167 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v26i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 @@ -6716,16 +6793,7 @@ end: define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v26i32_to_v52f16: ; SI: ; %bb.0: -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr50 -; SI-NEXT: ; kill: killed $vgpr51 -; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr50 -; SI-NEXT: ; kill: killed $vgpr51 -; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -6746,6 +6814,11 @@ define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr50 ; SI-NEXT: ; kill: killed $vgpr51 ; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: ; implicit-def: $vgpr48 ; SI-NEXT: ; implicit-def: $vgpr49 ; SI-NEXT: ; implicit-def: $vgpr38 @@ -6800,6 +6873,10 @@ define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: ; implicit-def: $vgpr50 ; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 ; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -7290,11 +7367,11 @@ define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) { ; VI-LABEL: bitcast_v26i32_to_v52f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: ; implicit-def: $vgpr43 ; VI-NEXT: ; implicit-def: $vgpr42 ; VI-NEXT: ; implicit-def: $vgpr41 @@ -7471,11 +7548,11 @@ define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) { ; GFX9-LABEL: bitcast_v26i32_to_v52f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: ; implicit-def: $vgpr43 ; GFX9-NEXT: ; implicit-def: $vgpr42 ; GFX9-NEXT: ; implicit-def: $vgpr41 @@ -7832,6 +7909,11 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; SI-LABEL: bitcast_v26i32_to_v52f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; SI-NEXT: v_readfirstlane_b32 s41, v1 ; SI-NEXT: v_readfirstlane_b32 s40, v2 @@ -7846,11 +7928,6 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s6, v11 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v12 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB17_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -10938,6 +11015,14 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; GFX9-LABEL: bitcast_v52f16_to_v26i32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v11 ; GFX9-NEXT: v_mov_b32_e32 v33, v10 ; GFX9-NEXT: v_mov_b32_e32 v34, v9 @@ -10965,14 +11050,6 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34 @@ -11112,90 +11189,167 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v26i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 @@ -13185,12 +13339,12 @@ define <52 x i16> @bitcast_v26f32_to_v52i16(<26 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v26f32_to_v52i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: ; implicit-def: $vgpr54 @@ -13481,11 +13635,11 @@ define <52 x i16> @bitcast_v26f32_to_v52i16(<26 x float> %a, i32 %b) { ; VI-LABEL: bitcast_v26f32_to_v52i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: ; implicit-def: $vgpr43 ; VI-NEXT: ; implicit-def: $vgpr42 ; VI-NEXT: ; implicit-def: $vgpr41 @@ -13662,11 +13816,11 @@ define <52 x i16> @bitcast_v26f32_to_v52i16(<26 x float> %a, i32 %b) { ; GFX9-LABEL: bitcast_v26f32_to_v52i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: ; implicit-def: $vgpr43 ; GFX9-NEXT: ; implicit-def: $vgpr42 ; GFX9-NEXT: ; implicit-def: $vgpr41 @@ -13997,6 +14151,14 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a, ; SI-LABEL: bitcast_v26f32_to_v52i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; SI-NEXT: v_mov_b32_e32 v25, s16 ; SI-NEXT: v_mov_b32_e32 v26, s17 @@ -14013,14 +14175,6 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a, ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_mov_b32_e32 v13, s28 ; SI-NEXT: v_mov_b32_e32 v14, s29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB29_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_lshr_b64 v[27:28], v[11:12], 16 @@ -14314,6 +14468,10 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a, ; VI-LABEL: bitcast_v26f32_to_v52i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; VI-NEXT: v_mov_b32_e32 v22, s16 ; VI-NEXT: v_mov_b32_e32 v20, s17 @@ -14330,10 +14488,6 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a, ; VI-NEXT: v_mov_b32_e32 v19, s27 ; VI-NEXT: v_mov_b32_e32 v12, s28 ; VI-NEXT: v_mov_b32_e32 v16, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB29_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v11 @@ -14519,6 +14673,10 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a, ; GFX9-LABEL: bitcast_v26f32_to_v52i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_mov_b32_e32 v22, s16 ; GFX9-NEXT: v_mov_b32_e32 v20, s17 @@ -14535,10 +14693,6 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a, ; GFX9-NEXT: v_mov_b32_e32 v19, s27 ; GFX9-NEXT: v_mov_b32_e32 v12, s28 ; GFX9-NEXT: v_mov_b32_e32 v16, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB29_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v11 @@ -16849,6 +17003,14 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a, ; GFX9-LABEL: bitcast_v52i16_to_v26f32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v11 ; GFX9-NEXT: v_mov_b32_e32 v33, v10 ; GFX9-NEXT: v_mov_b32_e32 v34, v9 @@ -16876,14 +17038,6 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34 @@ -17021,90 +17175,167 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v26f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 @@ -17451,16 +17682,7 @@ end: define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v26f32_to_v52f16: ; SI: ; %bb.0: -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr50 -; SI-NEXT: ; kill: killed $vgpr51 -; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr50 -; SI-NEXT: ; kill: killed $vgpr51 -; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -17481,6 +17703,11 @@ define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr50 ; SI-NEXT: ; kill: killed $vgpr51 ; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: ; implicit-def: $vgpr48 ; SI-NEXT: ; implicit-def: $vgpr49 ; SI-NEXT: ; implicit-def: $vgpr38 @@ -17535,6 +17762,10 @@ define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: ; implicit-def: $vgpr50 ; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 ; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -18025,11 +18256,11 @@ define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) { ; VI-LABEL: bitcast_v26f32_to_v52f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: ; implicit-def: $vgpr43 ; VI-NEXT: ; implicit-def: $vgpr42 ; VI-NEXT: ; implicit-def: $vgpr41 @@ -18206,11 +18437,11 @@ define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) { ; GFX9-LABEL: bitcast_v26f32_to_v52f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: ; implicit-def: $vgpr43 ; GFX9-NEXT: ; implicit-def: $vgpr42 ; GFX9-NEXT: ; implicit-def: $vgpr41 @@ -18541,20 +18772,6 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a, ; SI-LABEL: bitcast_v26f32_to_v52f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 -; SI-NEXT: v_readfirstlane_b32 s41, v1 -; SI-NEXT: v_readfirstlane_b32 s40, v2 -; SI-NEXT: v_readfirstlane_b32 s15, v3 -; SI-NEXT: v_readfirstlane_b32 s14, v4 -; SI-NEXT: v_readfirstlane_b32 s13, v5 -; SI-NEXT: v_readfirstlane_b32 s12, v6 -; SI-NEXT: v_readfirstlane_b32 s11, v7 -; SI-NEXT: v_readfirstlane_b32 s10, v8 -; SI-NEXT: v_readfirstlane_b32 s8, v9 -; SI-NEXT: v_readfirstlane_b32 s7, v10 -; SI-NEXT: v_readfirstlane_b32 s6, v11 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s9, v12 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -18571,6 +18788,20 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a, ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 +; SI-NEXT: v_readfirstlane_b32 s41, v1 +; SI-NEXT: v_readfirstlane_b32 s40, v2 +; SI-NEXT: v_readfirstlane_b32 s15, v3 +; SI-NEXT: v_readfirstlane_b32 s14, v4 +; SI-NEXT: v_readfirstlane_b32 s13, v5 +; SI-NEXT: v_readfirstlane_b32 s12, v6 +; SI-NEXT: v_readfirstlane_b32 s11, v7 +; SI-NEXT: v_readfirstlane_b32 s10, v8 +; SI-NEXT: v_readfirstlane_b32 s8, v9 +; SI-NEXT: v_readfirstlane_b32 s7, v10 +; SI-NEXT: v_readfirstlane_b32 s6, v11 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_readfirstlane_b32 s9, v12 ; SI-NEXT: s_cbranch_scc0 .LBB33_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -19022,6 +19253,10 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a, ; VI-LABEL: bitcast_v26f32_to_v52f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; VI-NEXT: v_mov_b32_e32 v22, s16 ; VI-NEXT: v_mov_b32_e32 v20, s17 @@ -19038,10 +19273,6 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a, ; VI-NEXT: v_mov_b32_e32 v19, s27 ; VI-NEXT: v_mov_b32_e32 v12, s28 ; VI-NEXT: v_mov_b32_e32 v16, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB33_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v11 @@ -19227,6 +19458,10 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a, ; GFX9-LABEL: bitcast_v26f32_to_v52f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_mov_b32_e32 v22, s16 ; GFX9-NEXT: v_mov_b32_e32 v20, s17 @@ -19243,10 +19478,6 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a, ; GFX9-NEXT: v_mov_b32_e32 v19, s27 ; GFX9-NEXT: v_mov_b32_e32 v12, s28 ; GFX9-NEXT: v_mov_b32_e32 v16, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB33_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v11 @@ -21831,6 +22062,14 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; GFX9-LABEL: bitcast_v52f16_to_v26f32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v11 ; GFX9-NEXT: v_mov_b32_e32 v33, v10 ; GFX9-NEXT: v_mov_b32_e32 v34, v9 @@ -21858,14 +22097,6 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34 @@ -22005,90 +22236,167 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v26f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 @@ -23238,12 +23546,12 @@ define <52 x i16> @bitcast_v13i64_to_v52i16(<13 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v13i64_to_v52i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: ; implicit-def: $vgpr54 @@ -23534,11 +23842,11 @@ define <52 x i16> @bitcast_v13i64_to_v52i16(<13 x i64> %a, i32 %b) { ; VI-LABEL: bitcast_v13i64_to_v52i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: ; implicit-def: $vgpr43 ; VI-NEXT: ; implicit-def: $vgpr42 ; VI-NEXT: ; implicit-def: $vgpr41 @@ -23715,11 +24023,11 @@ define <52 x i16> @bitcast_v13i64_to_v52i16(<13 x i64> %a, i32 %b) { ; GFX9-LABEL: bitcast_v13i64_to_v52i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: ; implicit-def: $vgpr43 ; GFX9-NEXT: ; implicit-def: $vgpr42 ; GFX9-NEXT: ; implicit-def: $vgpr41 @@ -24094,15 +24402,16 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v14, s30, 0 -; SI-NEXT: v_writelane_b32 v14, s31, 1 -; SI-NEXT: v_writelane_b32 v14, s34, 2 -; SI-NEXT: v_writelane_b32 v14, s35, 3 -; SI-NEXT: v_writelane_b32 v14, s36, 4 -; SI-NEXT: v_writelane_b32 v14, s37, 5 -; SI-NEXT: v_writelane_b32 v14, s38, 6 +; SI-NEXT: v_writelane_b32 v14, s34, 0 +; SI-NEXT: v_writelane_b32 v14, s35, 1 +; SI-NEXT: v_writelane_b32 v14, s36, 2 +; SI-NEXT: v_writelane_b32 v14, s37, 3 +; SI-NEXT: v_writelane_b32 v14, s38, 4 +; SI-NEXT: v_writelane_b32 v14, s39, 5 +; SI-NEXT: v_writelane_b32 v14, s48, 6 +; SI-NEXT: v_writelane_b32 v14, s30, 7 +; SI-NEXT: v_writelane_b32 v14, s31, 8 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 -; SI-NEXT: v_writelane_b32 v14, s39, 7 ; SI-NEXT: v_readfirstlane_b32 s14, v1 ; SI-NEXT: v_readfirstlane_b32 s15, v2 ; SI-NEXT: v_readfirstlane_b32 s12, v3 @@ -24116,7 +24425,6 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v11 ; SI-NEXT: s_and_b64 s[40:41], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v12 -; SI-NEXT: v_writelane_b32 v14, s48, 8 ; SI-NEXT: s_cbranch_scc0 .LBB41_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s92, s5, 16 @@ -24375,16 +24683,16 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x64, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v14, 7 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s48, v14, 8 -; SI-NEXT: v_readlane_b32 s39, v14, 7 -; SI-NEXT: v_readlane_b32 s38, v14, 6 -; SI-NEXT: v_readlane_b32 s37, v14, 5 -; SI-NEXT: v_readlane_b32 s36, v14, 4 -; SI-NEXT: v_readlane_b32 s35, v14, 3 -; SI-NEXT: v_readlane_b32 s34, v14, 2 -; SI-NEXT: v_readlane_b32 s31, v14, 1 -; SI-NEXT: v_readlane_b32 s30, v14, 0 +; SI-NEXT: v_readlane_b32 s31, v14, 8 +; SI-NEXT: v_readlane_b32 s48, v14, 6 +; SI-NEXT: v_readlane_b32 s39, v14, 5 +; SI-NEXT: v_readlane_b32 s38, v14, 4 +; SI-NEXT: v_readlane_b32 s37, v14, 3 +; SI-NEXT: v_readlane_b32 s36, v14, 2 +; SI-NEXT: v_readlane_b32 s35, v14, 1 +; SI-NEXT: v_readlane_b32 s34, v14, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -26796,6 +27104,14 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3 ; GFX9-LABEL: bitcast_v52i16_to_v13i64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v11 ; GFX9-NEXT: v_mov_b32_e32 v33, v10 ; GFX9-NEXT: v_mov_b32_e32 v34, v9 @@ -26823,14 +27139,6 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3 ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34 @@ -26968,90 +27276,167 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v13i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 @@ -27398,16 +27783,7 @@ end: define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v13i64_to_v52f16: ; SI: ; %bb.0: -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr50 -; SI-NEXT: ; kill: killed $vgpr51 -; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr50 -; SI-NEXT: ; kill: killed $vgpr51 -; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -27428,6 +27804,11 @@ define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr50 ; SI-NEXT: ; kill: killed $vgpr51 ; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: ; implicit-def: $vgpr48 ; SI-NEXT: ; implicit-def: $vgpr49 ; SI-NEXT: ; implicit-def: $vgpr38 @@ -27482,6 +27863,10 @@ define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: ; implicit-def: $vgpr50 ; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 ; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -27973,11 +28358,11 @@ define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) { ; VI-LABEL: bitcast_v13i64_to_v52f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: ; implicit-def: $vgpr43 ; VI-NEXT: ; implicit-def: $vgpr42 ; VI-NEXT: ; implicit-def: $vgpr41 @@ -28154,11 +28539,11 @@ define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) { ; GFX9-LABEL: bitcast_v13i64_to_v52f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: ; implicit-def: $vgpr43 ; GFX9-NEXT: ; implicit-def: $vgpr42 ; GFX9-NEXT: ; implicit-def: $vgpr41 @@ -28529,6 +28914,11 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; SI-LABEL: bitcast_v13i64_to_v52f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; SI-NEXT: v_readfirstlane_b32 s40, v1 ; SI-NEXT: v_readfirstlane_b32 s41, v2 @@ -28543,11 +28933,6 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s6, v11 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v12 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB45_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -31635,6 +32020,14 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; GFX9-LABEL: bitcast_v52f16_to_v13i64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v11 ; GFX9-NEXT: v_mov_b32_e32 v33, v10 ; GFX9-NEXT: v_mov_b32_e32 v34, v9 @@ -31662,14 +32055,6 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34 @@ -31809,90 +32194,167 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v13i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 @@ -32240,12 +32702,12 @@ define <52 x i16> @bitcast_v13f64_to_v52i16(<13 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v13f64_to_v52i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: ; implicit-def: $vgpr54 @@ -32523,11 +32985,11 @@ define <52 x i16> @bitcast_v13f64_to_v52i16(<13 x double> %a, i32 %b) { ; VI-LABEL: bitcast_v13f64_to_v52i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: ; implicit-def: $vgpr43 ; VI-NEXT: ; implicit-def: $vgpr42 ; VI-NEXT: ; implicit-def: $vgpr41 @@ -32691,11 +33153,11 @@ define <52 x i16> @bitcast_v13f64_to_v52i16(<13 x double> %a, i32 %b) { ; GFX9-LABEL: bitcast_v13f64_to_v52i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: ; implicit-def: $vgpr43 ; GFX9-NEXT: ; implicit-def: $vgpr42 ; GFX9-NEXT: ; implicit-def: $vgpr41 @@ -33013,6 +33475,14 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; SI-LABEL: bitcast_v13f64_to_v52i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; SI-NEXT: v_mov_b32_e32 v25, s16 ; SI-NEXT: v_mov_b32_e32 v26, s17 @@ -33029,14 +33499,6 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_mov_b32_e32 v13, s28 ; SI-NEXT: v_mov_b32_e32 v14, s29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB49_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_lshr_b64 v[27:28], v[11:12], 16 @@ -33317,6 +33779,10 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-LABEL: bitcast_v13f64_to_v52i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; VI-NEXT: v_mov_b32_e32 v21, s16 ; VI-NEXT: v_mov_b32_e32 v22, s17 @@ -33333,10 +33799,6 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_mov_b32_e32 v15, s28 ; VI-NEXT: v_mov_b32_e32 v16, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB49_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v11 @@ -33509,6 +33971,10 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-LABEL: bitcast_v13f64_to_v52i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_mov_b32_e32 v21, s16 ; GFX9-NEXT: v_mov_b32_e32 v22, s17 @@ -33525,10 +33991,6 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_mov_b32_e32 v15, s28 ; GFX9-NEXT: v_mov_b32_e32 v16, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB49_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v11 @@ -35826,6 +36288,14 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a, ; GFX9-LABEL: bitcast_v52i16_to_v13f64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v11 ; GFX9-NEXT: v_mov_b32_e32 v33, v10 ; GFX9-NEXT: v_mov_b32_e32 v34, v9 @@ -35853,14 +36323,6 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34 @@ -35998,90 +36460,167 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v13f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 @@ -36428,16 +36967,7 @@ end: define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v13f64_to_v52f16: ; SI: ; %bb.0: -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr50 -; SI-NEXT: ; kill: killed $vgpr51 -; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr50 -; SI-NEXT: ; kill: killed $vgpr51 -; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -36458,6 +36988,11 @@ define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr50 ; SI-NEXT: ; kill: killed $vgpr51 ; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: ; implicit-def: $vgpr48 ; SI-NEXT: ; implicit-def: $vgpr49 ; SI-NEXT: ; implicit-def: $vgpr38 @@ -36512,6 +37047,10 @@ define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: ; implicit-def: $vgpr50 ; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 ; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -36976,11 +37515,11 @@ define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) { ; VI-LABEL: bitcast_v13f64_to_v52f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; VI-NEXT: ; implicit-def: $vgpr43 ; VI-NEXT: ; implicit-def: $vgpr42 ; VI-NEXT: ; implicit-def: $vgpr41 @@ -37144,11 +37683,11 @@ define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) { ; GFX9-LABEL: bitcast_v13f64_to_v52f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GFX9-NEXT: ; implicit-def: $vgpr43 ; GFX9-NEXT: ; implicit-def: $vgpr42 ; GFX9-NEXT: ; implicit-def: $vgpr41 @@ -37466,20 +38005,6 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; SI-LABEL: bitcast_v13f64_to_v52f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 -; SI-NEXT: v_readfirstlane_b32 s14, v1 -; SI-NEXT: v_readfirstlane_b32 s15, v2 -; SI-NEXT: v_readfirstlane_b32 s12, v3 -; SI-NEXT: v_readfirstlane_b32 s13, v4 -; SI-NEXT: v_readfirstlane_b32 s10, v5 -; SI-NEXT: v_readfirstlane_b32 s11, v6 -; SI-NEXT: v_readfirstlane_b32 s8, v7 -; SI-NEXT: v_readfirstlane_b32 s9, v8 -; SI-NEXT: v_readfirstlane_b32 s6, v9 -; SI-NEXT: v_readfirstlane_b32 s7, v10 -; SI-NEXT: v_readfirstlane_b32 s4, v11 -; SI-NEXT: s_and_b64 s[40:41], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s5, v12 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -37496,6 +38021,20 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 +; SI-NEXT: v_readfirstlane_b32 s14, v1 +; SI-NEXT: v_readfirstlane_b32 s15, v2 +; SI-NEXT: v_readfirstlane_b32 s12, v3 +; SI-NEXT: v_readfirstlane_b32 s13, v4 +; SI-NEXT: v_readfirstlane_b32 s10, v5 +; SI-NEXT: v_readfirstlane_b32 s11, v6 +; SI-NEXT: v_readfirstlane_b32 s8, v7 +; SI-NEXT: v_readfirstlane_b32 s9, v8 +; SI-NEXT: v_readfirstlane_b32 s6, v9 +; SI-NEXT: v_readfirstlane_b32 s7, v10 +; SI-NEXT: v_readfirstlane_b32 s4, v11 +; SI-NEXT: s_and_b64 s[40:41], vcc, exec +; SI-NEXT: v_readfirstlane_b32 s5, v12 ; SI-NEXT: s_cbranch_scc0 .LBB53_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s40, s5, 16 @@ -37934,6 +38473,10 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-LABEL: bitcast_v13f64_to_v52f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; VI-NEXT: v_mov_b32_e32 v21, s16 ; VI-NEXT: v_mov_b32_e32 v22, s17 @@ -37950,10 +38493,6 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_mov_b32_e32 v15, s28 ; VI-NEXT: v_mov_b32_e32 v16, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB53_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v11 @@ -38126,6 +38665,10 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-LABEL: bitcast_v13f64_to_v52f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_mov_b32_e32 v21, s16 ; GFX9-NEXT: v_mov_b32_e32 v22, s17 @@ -38142,10 +38685,6 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_mov_b32_e32 v15, s28 ; GFX9-NEXT: v_mov_b32_e32 v16, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB53_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v11 @@ -40717,6 +41256,14 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; GFX9-LABEL: bitcast_v52f16_to_v13f64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v11 ; GFX9-NEXT: v_mov_b32_e32 v33, v10 ; GFX9-NEXT: v_mov_b32_e32 v34, v9 @@ -40744,14 +41291,6 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34 @@ -40891,90 +41430,167 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v13f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 @@ -43549,6 +44165,10 @@ define inreg <52 x half> @bitcast_v52i16_to_v52f16_scalar(<52 x i16> inreg %a, i ; GFX9-LABEL: bitcast_v52i16_to_v52f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: s_lshr_b32 s43, s29, 16 ; GFX9-NEXT: s_lshr_b32 s42, s28, 16 @@ -43577,10 +44197,6 @@ define inreg <52 x half> @bitcast_v52i16_to_v52f16_scalar(<52 x i16> inreg %a, i ; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v0 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB57_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_cbranch_execnz .LBB57_4 @@ -45783,6 +46399,10 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i ; VI-LABEL: bitcast_v52f16_to_v52i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; VI-NEXT: s_lshr_b32 s6, s29, 16 ; VI-NEXT: s_lshr_b32 s7, s28, 16 @@ -45811,10 +46431,6 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i ; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v0 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB59_3 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB59_4 @@ -45979,6 +46595,10 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i ; GFX9-LABEL: bitcast_v52f16_to_v52i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: s_lshr_b32 s43, s29, 16 ; GFX9-NEXT: s_lshr_b32 s42, s28, 16 @@ -46007,10 +46627,6 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i ; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v0 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB59_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_cbranch_execnz .LBB59_4 diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll index 8eb71e90f8504..f6ff5be918706 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll @@ -2719,7 +2719,6 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v28i32_to_v56i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill @@ -2729,6 +2728,7 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr42 @@ -3045,7 +3045,6 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) { ; VI-LABEL: bitcast_v28i32_to_v56i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -3054,6 +3053,7 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: ; implicit-def: $vgpr47 ; VI-NEXT: ; implicit-def: $vgpr46 ; VI-NEXT: ; implicit-def: $vgpr45 @@ -3246,7 +3246,6 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) { ; GFX9-LABEL: bitcast_v28i32_to_v56i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -3255,6 +3254,7 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: ; implicit-def: $vgpr47 ; GFX9-NEXT: ; implicit-def: $vgpr46 ; GFX9-NEXT: ; implicit-def: $vgpr45 @@ -3641,20 +3641,21 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v16, s30, 0 -; SI-NEXT: v_writelane_b32 v16, s31, 1 -; SI-NEXT: v_writelane_b32 v16, s34, 2 -; SI-NEXT: v_writelane_b32 v16, s35, 3 -; SI-NEXT: v_writelane_b32 v16, s36, 4 -; SI-NEXT: v_writelane_b32 v16, s37, 5 -; SI-NEXT: v_writelane_b32 v16, s38, 6 -; SI-NEXT: v_writelane_b32 v16, s39, 7 -; SI-NEXT: v_writelane_b32 v16, s48, 8 -; SI-NEXT: v_writelane_b32 v16, s49, 9 -; SI-NEXT: v_writelane_b32 v16, s50, 10 -; SI-NEXT: v_writelane_b32 v16, s51, 11 +; SI-NEXT: v_writelane_b32 v16, s34, 0 +; SI-NEXT: v_writelane_b32 v16, s35, 1 +; SI-NEXT: v_writelane_b32 v16, s36, 2 +; SI-NEXT: v_writelane_b32 v16, s37, 3 +; SI-NEXT: v_writelane_b32 v16, s38, 4 +; SI-NEXT: v_writelane_b32 v16, s39, 5 +; SI-NEXT: v_writelane_b32 v16, s48, 6 +; SI-NEXT: v_writelane_b32 v16, s49, 7 +; SI-NEXT: v_writelane_b32 v16, s50, 8 +; SI-NEXT: v_writelane_b32 v16, s51, 9 +; SI-NEXT: v_writelane_b32 v16, s52, 10 +; SI-NEXT: v_writelane_b32 v16, s53, 11 +; SI-NEXT: v_writelane_b32 v16, s30, 12 +; SI-NEXT: v_writelane_b32 v16, s31, 13 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 -; SI-NEXT: v_writelane_b32 v16, s52, 12 ; SI-NEXT: v_readfirstlane_b32 s40, v1 ; SI-NEXT: v_readfirstlane_b32 s41, v2 ; SI-NEXT: v_readfirstlane_b32 s14, v3 @@ -3670,7 +3671,6 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v13 ; SI-NEXT: s_and_b64 s[42:43], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v14 -; SI-NEXT: v_writelane_b32 v16, s53, 13 ; SI-NEXT: s_cbranch_scc0 .LBB13_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s30, s5, 16 @@ -3950,21 +3950,21 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x6c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v16, 12 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s53, v16, 13 -; SI-NEXT: v_readlane_b32 s52, v16, 12 -; SI-NEXT: v_readlane_b32 s51, v16, 11 -; SI-NEXT: v_readlane_b32 s50, v16, 10 -; SI-NEXT: v_readlane_b32 s49, v16, 9 -; SI-NEXT: v_readlane_b32 s48, v16, 8 -; SI-NEXT: v_readlane_b32 s39, v16, 7 -; SI-NEXT: v_readlane_b32 s38, v16, 6 -; SI-NEXT: v_readlane_b32 s37, v16, 5 -; SI-NEXT: v_readlane_b32 s36, v16, 4 -; SI-NEXT: v_readlane_b32 s35, v16, 3 -; SI-NEXT: v_readlane_b32 s34, v16, 2 -; SI-NEXT: v_readlane_b32 s31, v16, 1 -; SI-NEXT: v_readlane_b32 s30, v16, 0 +; SI-NEXT: v_readlane_b32 s31, v16, 13 +; SI-NEXT: v_readlane_b32 s53, v16, 11 +; SI-NEXT: v_readlane_b32 s52, v16, 10 +; SI-NEXT: v_readlane_b32 s51, v16, 9 +; SI-NEXT: v_readlane_b32 s50, v16, 8 +; SI-NEXT: v_readlane_b32 s49, v16, 7 +; SI-NEXT: v_readlane_b32 s48, v16, 6 +; SI-NEXT: v_readlane_b32 s39, v16, 5 +; SI-NEXT: v_readlane_b32 s38, v16, 4 +; SI-NEXT: v_readlane_b32 s37, v16, 3 +; SI-NEXT: v_readlane_b32 s36, v16, 2 +; SI-NEXT: v_readlane_b32 s35, v16, 1 +; SI-NEXT: v_readlane_b32 s34, v16, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -4007,10 +4007,11 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v28, s30, 0 -; VI-NEXT: v_writelane_b32 v28, s31, 1 +; VI-NEXT: v_writelane_b32 v28, s34, 0 +; VI-NEXT: v_writelane_b32 v28, s35, 1 +; VI-NEXT: v_writelane_b32 v28, s30, 2 +; VI-NEXT: v_writelane_b32 v28, s31, 3 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 -; VI-NEXT: v_writelane_b32 v28, s34, 2 ; VI-NEXT: v_readfirstlane_b32 s43, v0 ; VI-NEXT: v_readfirstlane_b32 s42, v1 ; VI-NEXT: v_readfirstlane_b32 s41, v2 @@ -4026,7 +4027,6 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s6, v12 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s7, v13 -; VI-NEXT: v_writelane_b32 v28, s35, 3 ; VI-NEXT: s_cbranch_scc0 .LBB13_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s44, s7, 16 @@ -4200,6 +4200,7 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 ; VI-NEXT: s_lshl_b32 s42, s44, 16 ; VI-NEXT: s_or_b32 s7, s7, s42 +; VI-NEXT: v_readlane_b32 s30, v28, 2 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v2, s16 @@ -4228,10 +4229,9 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3 ; VI-NEXT: v_mov_b32_e32 v25, s8 ; VI-NEXT: v_mov_b32_e32 v26, s6 ; VI-NEXT: v_mov_b32_e32 v27, s7 -; VI-NEXT: v_readlane_b32 s35, v28, 3 -; VI-NEXT: v_readlane_b32 s34, v28, 2 -; VI-NEXT: v_readlane_b32 s31, v28, 1 -; VI-NEXT: v_readlane_b32 s30, v28, 0 +; VI-NEXT: v_readlane_b32 s31, v28, 3 +; VI-NEXT: v_readlane_b32 s35, v28, 1 +; VI-NEXT: v_readlane_b32 s34, v28, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -6585,6 +6585,18 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3 ; GFX9-LABEL: bitcast_v56i16_to_v28i32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v13 ; GFX9-NEXT: v_mov_b32_e32 v33, v12 ; GFX9-NEXT: v_mov_b32_e32 v34, v11 @@ -6614,18 +6626,6 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3 ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34 @@ -6779,90 +6779,167 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v28i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3 @@ -7224,6 +7301,22 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v28i32_to_v56f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; kill: killed $vgpr29 @@ -7266,22 +7359,6 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; kill: killed $vgpr29 ; SI-NEXT: ; implicit-def: $vgpr29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr41 ; SI-NEXT: ; implicit-def: $vgpr54 @@ -7867,7 +7944,6 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) { ; VI-LABEL: bitcast_v28i32_to_v56f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -7876,6 +7952,7 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: ; implicit-def: $vgpr47 ; VI-NEXT: ; implicit-def: $vgpr46 ; VI-NEXT: ; implicit-def: $vgpr45 @@ -8068,7 +8145,6 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) { ; GFX9-LABEL: bitcast_v28i32_to_v56f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -8077,6 +8153,7 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: ; implicit-def: $vgpr47 ; GFX9-NEXT: ; implicit-def: $vgpr46 ; GFX9-NEXT: ; implicit-def: $vgpr45 @@ -8459,6 +8536,15 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i ; SI-LABEL: bitcast_v28i32_to_v56f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 ; SI-NEXT: v_readfirstlane_b32 s43, v1 ; SI-NEXT: v_readfirstlane_b32 s42, v2 @@ -8475,15 +8561,6 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s6, v13 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v14 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB17_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -8964,10 +9041,11 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v28, s30, 0 -; VI-NEXT: v_writelane_b32 v28, s31, 1 +; VI-NEXT: v_writelane_b32 v28, s34, 0 +; VI-NEXT: v_writelane_b32 v28, s35, 1 +; VI-NEXT: v_writelane_b32 v28, s30, 2 +; VI-NEXT: v_writelane_b32 v28, s31, 3 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 -; VI-NEXT: v_writelane_b32 v28, s34, 2 ; VI-NEXT: v_readfirstlane_b32 s43, v0 ; VI-NEXT: v_readfirstlane_b32 s42, v1 ; VI-NEXT: v_readfirstlane_b32 s41, v2 @@ -8983,7 +9061,6 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i ; VI-NEXT: v_readfirstlane_b32 s6, v12 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s7, v13 -; VI-NEXT: v_writelane_b32 v28, s35, 3 ; VI-NEXT: s_cbranch_scc0 .LBB17_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s44, s7, 16 @@ -9157,6 +9234,7 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i ; VI-NEXT: s_and_b32 s7, 0xffff, s7 ; VI-NEXT: s_lshl_b32 s42, s44, 16 ; VI-NEXT: s_or_b32 s7, s7, s42 +; VI-NEXT: v_readlane_b32 s30, v28, 2 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v2, s16 @@ -9185,10 +9263,9 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i ; VI-NEXT: v_mov_b32_e32 v25, s8 ; VI-NEXT: v_mov_b32_e32 v26, s6 ; VI-NEXT: v_mov_b32_e32 v27, s7 -; VI-NEXT: v_readlane_b32 s35, v28, 3 -; VI-NEXT: v_readlane_b32 s34, v28, 2 -; VI-NEXT: v_readlane_b32 s31, v28, 1 -; VI-NEXT: v_readlane_b32 s30, v28, 0 +; VI-NEXT: v_readlane_b32 s31, v28, 3 +; VI-NEXT: v_readlane_b32 s35, v28, 1 +; VI-NEXT: v_readlane_b32 s34, v28, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -11847,6 +11924,18 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i ; GFX9-LABEL: bitcast_v56f16_to_v28i32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v13 ; GFX9-NEXT: v_mov_b32_e32 v33, v12 ; GFX9-NEXT: v_mov_b32_e32 v34, v11 @@ -11876,18 +11965,6 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34 @@ -12043,90 +12120,167 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v28i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3 @@ -14225,7 +14379,6 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v28f32_to_v56i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill @@ -14235,6 +14388,7 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr42 @@ -14551,7 +14705,6 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) { ; VI-LABEL: bitcast_v28f32_to_v56i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -14560,6 +14713,7 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: ; implicit-def: $vgpr47 ; VI-NEXT: ; implicit-def: $vgpr46 ; VI-NEXT: ; implicit-def: $vgpr45 @@ -14752,7 +14906,6 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) { ; GFX9-LABEL: bitcast_v28f32_to_v56i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -14761,6 +14914,7 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: ; implicit-def: $vgpr47 ; GFX9-NEXT: ; implicit-def: $vgpr46 ; GFX9-NEXT: ; implicit-def: $vgpr45 @@ -15115,6 +15269,18 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a, ; SI-LABEL: bitcast_v28f32_to_v56i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 ; SI-NEXT: v_mov_b32_e32 v27, s16 ; SI-NEXT: v_mov_b32_e32 v28, s17 @@ -15131,18 +15297,6 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a, ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_mov_b32_e32 v15, s28 ; SI-NEXT: v_mov_b32_e32 v16, s29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB29_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_lshr_b64 v[29:30], v[13:14], 16 @@ -15460,6 +15614,14 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a, ; VI-LABEL: bitcast_v28f32_to_v56i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; VI-NEXT: v_mov_b32_e32 v20, s16 ; VI-NEXT: v_mov_b32_e32 v18, s17 @@ -15476,14 +15638,6 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a, ; VI-NEXT: v_mov_b32_e32 v21, s27 ; VI-NEXT: v_mov_b32_e32 v19, s28 ; VI-NEXT: v_mov_b32_e32 v14, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB29_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v13 @@ -15687,6 +15841,14 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a, ; GFX9-LABEL: bitcast_v28f32_to_v56i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; GFX9-NEXT: v_mov_b32_e32 v20, s16 ; GFX9-NEXT: v_mov_b32_e32 v18, s17 @@ -15703,14 +15865,6 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a, ; GFX9-NEXT: v_mov_b32_e32 v21, s27 ; GFX9-NEXT: v_mov_b32_e32 v19, s28 ; GFX9-NEXT: v_mov_b32_e32 v14, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB29_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v13 @@ -18210,6 +18364,18 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a, ; GFX9-LABEL: bitcast_v56i16_to_v28f32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v13 ; GFX9-NEXT: v_mov_b32_e32 v33, v12 ; GFX9-NEXT: v_mov_b32_e32 v34, v11 @@ -18239,18 +18405,6 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34 @@ -18404,90 +18558,167 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v28f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3 @@ -18849,6 +19080,22 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v28f32_to_v56f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; kill: killed $vgpr29 @@ -18891,22 +19138,6 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; kill: killed $vgpr29 ; SI-NEXT: ; implicit-def: $vgpr29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr41 ; SI-NEXT: ; implicit-def: $vgpr54 @@ -19492,7 +19723,6 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) { ; VI-LABEL: bitcast_v28f32_to_v56f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -19501,6 +19731,7 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: ; implicit-def: $vgpr47 ; VI-NEXT: ; implicit-def: $vgpr46 ; VI-NEXT: ; implicit-def: $vgpr45 @@ -19693,7 +19924,6 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) { ; GFX9-LABEL: bitcast_v28f32_to_v56f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -19702,6 +19932,7 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: ; implicit-def: $vgpr47 ; GFX9-NEXT: ; implicit-def: $vgpr46 ; GFX9-NEXT: ; implicit-def: $vgpr45 @@ -20056,22 +20287,6 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a, ; SI-LABEL: bitcast_v28f32_to_v56f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 -; SI-NEXT: v_readfirstlane_b32 s43, v1 -; SI-NEXT: v_readfirstlane_b32 s42, v2 -; SI-NEXT: v_readfirstlane_b32 s41, v3 -; SI-NEXT: v_readfirstlane_b32 s40, v4 -; SI-NEXT: v_readfirstlane_b32 s15, v5 -; SI-NEXT: v_readfirstlane_b32 s14, v6 -; SI-NEXT: v_readfirstlane_b32 s13, v7 -; SI-NEXT: v_readfirstlane_b32 s12, v8 -; SI-NEXT: v_readfirstlane_b32 s11, v9 -; SI-NEXT: v_readfirstlane_b32 s10, v10 -; SI-NEXT: v_readfirstlane_b32 s8, v11 -; SI-NEXT: v_readfirstlane_b32 s7, v12 -; SI-NEXT: v_readfirstlane_b32 s6, v13 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s9, v14 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -20088,6 +20303,22 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a, ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 +; SI-NEXT: v_readfirstlane_b32 s43, v1 +; SI-NEXT: v_readfirstlane_b32 s42, v2 +; SI-NEXT: v_readfirstlane_b32 s41, v3 +; SI-NEXT: v_readfirstlane_b32 s40, v4 +; SI-NEXT: v_readfirstlane_b32 s15, v5 +; SI-NEXT: v_readfirstlane_b32 s14, v6 +; SI-NEXT: v_readfirstlane_b32 s13, v7 +; SI-NEXT: v_readfirstlane_b32 s12, v8 +; SI-NEXT: v_readfirstlane_b32 s11, v9 +; SI-NEXT: v_readfirstlane_b32 s10, v10 +; SI-NEXT: v_readfirstlane_b32 s8, v11 +; SI-NEXT: v_readfirstlane_b32 s7, v12 +; SI-NEXT: v_readfirstlane_b32 s6, v13 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_readfirstlane_b32 s9, v14 ; SI-NEXT: s_cbranch_scc0 .LBB33_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -20575,6 +20806,14 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a, ; VI-LABEL: bitcast_v28f32_to_v56f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; VI-NEXT: v_mov_b32_e32 v20, s16 ; VI-NEXT: v_mov_b32_e32 v18, s17 @@ -20591,14 +20830,6 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a, ; VI-NEXT: v_mov_b32_e32 v21, s27 ; VI-NEXT: v_mov_b32_e32 v19, s28 ; VI-NEXT: v_mov_b32_e32 v14, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB33_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v13 @@ -20802,6 +21033,14 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a, ; GFX9-LABEL: bitcast_v28f32_to_v56f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; GFX9-NEXT: v_mov_b32_e32 v20, s16 ; GFX9-NEXT: v_mov_b32_e32 v18, s17 @@ -20818,14 +21057,6 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a, ; GFX9-NEXT: v_mov_b32_e32 v21, s27 ; GFX9-NEXT: v_mov_b32_e32 v19, s28 ; GFX9-NEXT: v_mov_b32_e32 v14, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB33_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v13 @@ -23630,6 +23861,18 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a, ; GFX9-LABEL: bitcast_v56f16_to_v28f32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v13 ; GFX9-NEXT: v_mov_b32_e32 v33, v12 ; GFX9-NEXT: v_mov_b32_e32 v34, v11 @@ -23659,18 +23902,6 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34 @@ -23826,90 +24057,167 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v28f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3 @@ -25120,7 +25428,6 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v14i64_to_v56i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill @@ -25130,6 +25437,7 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr42 @@ -25446,7 +25754,6 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) { ; VI-LABEL: bitcast_v14i64_to_v56i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -25455,6 +25762,7 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: ; implicit-def: $vgpr47 ; VI-NEXT: ; implicit-def: $vgpr46 ; VI-NEXT: ; implicit-def: $vgpr45 @@ -25647,7 +25955,6 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) { ; GFX9-LABEL: bitcast_v14i64_to_v56i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -25656,6 +25963,7 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: ; implicit-def: $vgpr47 ; GFX9-NEXT: ; implicit-def: $vgpr46 ; GFX9-NEXT: ; implicit-def: $vgpr45 @@ -26056,20 +26364,21 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v16, s30, 0 -; SI-NEXT: v_writelane_b32 v16, s31, 1 -; SI-NEXT: v_writelane_b32 v16, s34, 2 -; SI-NEXT: v_writelane_b32 v16, s35, 3 -; SI-NEXT: v_writelane_b32 v16, s36, 4 -; SI-NEXT: v_writelane_b32 v16, s37, 5 -; SI-NEXT: v_writelane_b32 v16, s38, 6 -; SI-NEXT: v_writelane_b32 v16, s39, 7 -; SI-NEXT: v_writelane_b32 v16, s48, 8 -; SI-NEXT: v_writelane_b32 v16, s49, 9 -; SI-NEXT: v_writelane_b32 v16, s50, 10 -; SI-NEXT: v_writelane_b32 v16, s51, 11 +; SI-NEXT: v_writelane_b32 v16, s34, 0 +; SI-NEXT: v_writelane_b32 v16, s35, 1 +; SI-NEXT: v_writelane_b32 v16, s36, 2 +; SI-NEXT: v_writelane_b32 v16, s37, 3 +; SI-NEXT: v_writelane_b32 v16, s38, 4 +; SI-NEXT: v_writelane_b32 v16, s39, 5 +; SI-NEXT: v_writelane_b32 v16, s48, 6 +; SI-NEXT: v_writelane_b32 v16, s49, 7 +; SI-NEXT: v_writelane_b32 v16, s50, 8 +; SI-NEXT: v_writelane_b32 v16, s51, 9 +; SI-NEXT: v_writelane_b32 v16, s52, 10 +; SI-NEXT: v_writelane_b32 v16, s53, 11 +; SI-NEXT: v_writelane_b32 v16, s30, 12 +; SI-NEXT: v_writelane_b32 v16, s31, 13 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 -; SI-NEXT: v_writelane_b32 v16, s52, 12 ; SI-NEXT: v_readfirstlane_b32 s40, v1 ; SI-NEXT: v_readfirstlane_b32 s41, v2 ; SI-NEXT: v_readfirstlane_b32 s14, v3 @@ -26085,7 +26394,6 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v13 ; SI-NEXT: s_and_b64 s[42:43], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v14 -; SI-NEXT: v_writelane_b32 v16, s53, 13 ; SI-NEXT: s_cbranch_scc0 .LBB41_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s30, s5, 16 @@ -26365,21 +26673,21 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x6c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v16, 12 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s53, v16, 13 -; SI-NEXT: v_readlane_b32 s52, v16, 12 -; SI-NEXT: v_readlane_b32 s51, v16, 11 -; SI-NEXT: v_readlane_b32 s50, v16, 10 -; SI-NEXT: v_readlane_b32 s49, v16, 9 -; SI-NEXT: v_readlane_b32 s48, v16, 8 -; SI-NEXT: v_readlane_b32 s39, v16, 7 -; SI-NEXT: v_readlane_b32 s38, v16, 6 -; SI-NEXT: v_readlane_b32 s37, v16, 5 -; SI-NEXT: v_readlane_b32 s36, v16, 4 -; SI-NEXT: v_readlane_b32 s35, v16, 3 -; SI-NEXT: v_readlane_b32 s34, v16, 2 -; SI-NEXT: v_readlane_b32 s31, v16, 1 -; SI-NEXT: v_readlane_b32 s30, v16, 0 +; SI-NEXT: v_readlane_b32 s31, v16, 13 +; SI-NEXT: v_readlane_b32 s53, v16, 11 +; SI-NEXT: v_readlane_b32 s52, v16, 10 +; SI-NEXT: v_readlane_b32 s51, v16, 9 +; SI-NEXT: v_readlane_b32 s50, v16, 8 +; SI-NEXT: v_readlane_b32 s49, v16, 7 +; SI-NEXT: v_readlane_b32 s48, v16, 6 +; SI-NEXT: v_readlane_b32 s39, v16, 5 +; SI-NEXT: v_readlane_b32 s38, v16, 4 +; SI-NEXT: v_readlane_b32 s37, v16, 3 +; SI-NEXT: v_readlane_b32 s36, v16, 2 +; SI-NEXT: v_readlane_b32 s35, v16, 1 +; SI-NEXT: v_readlane_b32 s34, v16, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -26422,10 +26730,11 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v28, s30, 0 -; VI-NEXT: v_writelane_b32 v28, s31, 1 +; VI-NEXT: v_writelane_b32 v28, s34, 0 +; VI-NEXT: v_writelane_b32 v28, s35, 1 +; VI-NEXT: v_writelane_b32 v28, s30, 2 +; VI-NEXT: v_writelane_b32 v28, s31, 3 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 -; VI-NEXT: v_writelane_b32 v28, s34, 2 ; VI-NEXT: v_readfirstlane_b32 s43, v0 ; VI-NEXT: v_readfirstlane_b32 s42, v1 ; VI-NEXT: v_readfirstlane_b32 s41, v2 @@ -26441,7 +26750,6 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s6, v12 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s7, v13 -; VI-NEXT: v_writelane_b32 v28, s35, 3 ; VI-NEXT: s_cbranch_scc0 .LBB41_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s44, s7, 16 @@ -26615,6 +26923,7 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 ; VI-NEXT: s_lshl_b32 s42, s44, 16 ; VI-NEXT: s_or_b32 s7, s7, s42 +; VI-NEXT: v_readlane_b32 s30, v28, 2 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v2, s16 @@ -26643,10 +26952,9 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3 ; VI-NEXT: v_mov_b32_e32 v25, s8 ; VI-NEXT: v_mov_b32_e32 v26, s6 ; VI-NEXT: v_mov_b32_e32 v27, s7 -; VI-NEXT: v_readlane_b32 s35, v28, 3 -; VI-NEXT: v_readlane_b32 s34, v28, 2 -; VI-NEXT: v_readlane_b32 s31, v28, 1 -; VI-NEXT: v_readlane_b32 s30, v28, 0 +; VI-NEXT: v_readlane_b32 s31, v28, 3 +; VI-NEXT: v_readlane_b32 s35, v28, 1 +; VI-NEXT: v_readlane_b32 s34, v28, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -29000,6 +29308,18 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3 ; GFX9-LABEL: bitcast_v56i16_to_v14i64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v13 ; GFX9-NEXT: v_mov_b32_e32 v33, v12 ; GFX9-NEXT: v_mov_b32_e32 v34, v11 @@ -29029,18 +29349,6 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3 ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34 @@ -29194,90 +29502,167 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v14i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3 @@ -29639,6 +30024,22 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v14i64_to_v56f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; kill: killed $vgpr29 @@ -29681,22 +30082,6 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; kill: killed $vgpr29 ; SI-NEXT: ; implicit-def: $vgpr29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr41 ; SI-NEXT: ; implicit-def: $vgpr54 @@ -30282,7 +30667,6 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) { ; VI-LABEL: bitcast_v14i64_to_v56f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -30291,6 +30675,7 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: ; implicit-def: $vgpr47 ; VI-NEXT: ; implicit-def: $vgpr46 ; VI-NEXT: ; implicit-def: $vgpr45 @@ -30483,7 +30868,6 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) { ; GFX9-LABEL: bitcast_v14i64_to_v56f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -30492,6 +30876,7 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: ; implicit-def: $vgpr47 ; GFX9-NEXT: ; implicit-def: $vgpr46 ; GFX9-NEXT: ; implicit-def: $vgpr45 @@ -30888,6 +31273,15 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i ; SI-LABEL: bitcast_v14i64_to_v56f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 ; SI-NEXT: v_readfirstlane_b32 s42, v1 ; SI-NEXT: v_readfirstlane_b32 s43, v2 @@ -30904,15 +31298,6 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s6, v13 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v14 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB45_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -31393,10 +31778,11 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v28, s30, 0 -; VI-NEXT: v_writelane_b32 v28, s31, 1 +; VI-NEXT: v_writelane_b32 v28, s34, 0 +; VI-NEXT: v_writelane_b32 v28, s35, 1 +; VI-NEXT: v_writelane_b32 v28, s30, 2 +; VI-NEXT: v_writelane_b32 v28, s31, 3 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 -; VI-NEXT: v_writelane_b32 v28, s34, 2 ; VI-NEXT: v_readfirstlane_b32 s43, v0 ; VI-NEXT: v_readfirstlane_b32 s42, v1 ; VI-NEXT: v_readfirstlane_b32 s41, v2 @@ -31412,7 +31798,6 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i ; VI-NEXT: v_readfirstlane_b32 s6, v12 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s7, v13 -; VI-NEXT: v_writelane_b32 v28, s35, 3 ; VI-NEXT: s_cbranch_scc0 .LBB45_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s44, s7, 16 @@ -31586,6 +31971,7 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i ; VI-NEXT: s_and_b32 s7, 0xffff, s7 ; VI-NEXT: s_lshl_b32 s42, s44, 16 ; VI-NEXT: s_or_b32 s7, s7, s42 +; VI-NEXT: v_readlane_b32 s30, v28, 2 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v2, s16 @@ -31614,10 +32000,9 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i ; VI-NEXT: v_mov_b32_e32 v25, s8 ; VI-NEXT: v_mov_b32_e32 v26, s6 ; VI-NEXT: v_mov_b32_e32 v27, s7 -; VI-NEXT: v_readlane_b32 s35, v28, 3 -; VI-NEXT: v_readlane_b32 s34, v28, 2 -; VI-NEXT: v_readlane_b32 s31, v28, 1 -; VI-NEXT: v_readlane_b32 s30, v28, 0 +; VI-NEXT: v_readlane_b32 s31, v28, 3 +; VI-NEXT: v_readlane_b32 s35, v28, 1 +; VI-NEXT: v_readlane_b32 s34, v28, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -34276,6 +34661,18 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i ; GFX9-LABEL: bitcast_v56f16_to_v14i64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v13 ; GFX9-NEXT: v_mov_b32_e32 v33, v12 ; GFX9-NEXT: v_mov_b32_e32 v34, v11 @@ -34305,18 +34702,6 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34 @@ -34472,90 +34857,167 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v14i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3 @@ -34917,7 +35379,6 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v14f64_to_v56i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill @@ -34927,6 +35388,7 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr42 @@ -35229,7 +35691,6 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) { ; VI-LABEL: bitcast_v14f64_to_v56i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -35238,6 +35699,7 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: ; implicit-def: $vgpr47 ; VI-NEXT: ; implicit-def: $vgpr46 ; VI-NEXT: ; implicit-def: $vgpr45 @@ -35416,7 +35878,6 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) { ; GFX9-LABEL: bitcast_v14f64_to_v56i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -35425,6 +35886,7 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: ; implicit-def: $vgpr47 ; GFX9-NEXT: ; implicit-def: $vgpr46 ; GFX9-NEXT: ; implicit-def: $vgpr45 @@ -35765,6 +36227,18 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a, ; SI-LABEL: bitcast_v14f64_to_v56i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 ; SI-NEXT: v_mov_b32_e32 v27, s16 ; SI-NEXT: v_mov_b32_e32 v28, s17 @@ -35781,18 +36255,6 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a, ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_mov_b32_e32 v15, s28 ; SI-NEXT: v_mov_b32_e32 v16, s29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB49_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_lshr_b64 v[29:30], v[13:14], 16 @@ -36096,6 +36558,14 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a, ; VI-LABEL: bitcast_v14f64_to_v56i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_mov_b32_e32 v20, s17 @@ -36112,14 +36582,6 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a, ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_mov_b32_e32 v17, s28 ; VI-NEXT: v_mov_b32_e32 v18, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB49_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v13 @@ -36309,6 +36771,14 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a, ; GFX9-LABEL: bitcast_v14f64_to_v56i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; GFX9-NEXT: v_mov_b32_e32 v19, s16 ; GFX9-NEXT: v_mov_b32_e32 v20, s17 @@ -36325,14 +36795,6 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a, ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_mov_b32_e32 v17, s28 ; GFX9-NEXT: v_mov_b32_e32 v18, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB49_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v13 @@ -38818,6 +39280,18 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a, ; GFX9-LABEL: bitcast_v56i16_to_v14f64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v13 ; GFX9-NEXT: v_mov_b32_e32 v33, v12 ; GFX9-NEXT: v_mov_b32_e32 v34, v11 @@ -38847,18 +39321,6 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34 @@ -39012,90 +39474,167 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v14f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3 @@ -39457,6 +39996,22 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v14f64_to_v56f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29 ; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; kill: killed $vgpr29 @@ -39499,22 +40054,6 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; kill: killed $vgpr29 ; SI-NEXT: ; implicit-def: $vgpr29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr41 ; SI-NEXT: ; implicit-def: $vgpr55 ; SI-NEXT: ; implicit-def: $vgpr40 @@ -40071,7 +40610,6 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) { ; VI-LABEL: bitcast_v14f64_to_v56f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -40080,6 +40618,7 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; VI-NEXT: ; implicit-def: $vgpr47 ; VI-NEXT: ; implicit-def: $vgpr46 ; VI-NEXT: ; implicit-def: $vgpr45 @@ -40258,7 +40797,6 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) { ; GFX9-LABEL: bitcast_v14f64_to_v56f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -40267,6 +40805,7 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28 ; GFX9-NEXT: ; implicit-def: $vgpr47 ; GFX9-NEXT: ; implicit-def: $vgpr46 ; GFX9-NEXT: ; implicit-def: $vgpr45 @@ -40607,22 +41146,6 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a ; SI-LABEL: bitcast_v14f64_to_v56f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 -; SI-NEXT: v_readfirstlane_b32 s40, v1 -; SI-NEXT: v_readfirstlane_b32 s41, v2 -; SI-NEXT: v_readfirstlane_b32 s14, v3 -; SI-NEXT: v_readfirstlane_b32 s15, v4 -; SI-NEXT: v_readfirstlane_b32 s12, v5 -; SI-NEXT: v_readfirstlane_b32 s13, v6 -; SI-NEXT: v_readfirstlane_b32 s10, v7 -; SI-NEXT: v_readfirstlane_b32 s11, v8 -; SI-NEXT: v_readfirstlane_b32 s8, v9 -; SI-NEXT: v_readfirstlane_b32 s9, v10 -; SI-NEXT: v_readfirstlane_b32 s6, v11 -; SI-NEXT: v_readfirstlane_b32 s7, v12 -; SI-NEXT: v_readfirstlane_b32 s4, v13 -; SI-NEXT: s_and_b64 s[42:43], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s5, v14 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -40639,6 +41162,22 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 +; SI-NEXT: v_readfirstlane_b32 s40, v1 +; SI-NEXT: v_readfirstlane_b32 s41, v2 +; SI-NEXT: v_readfirstlane_b32 s14, v3 +; SI-NEXT: v_readfirstlane_b32 s15, v4 +; SI-NEXT: v_readfirstlane_b32 s12, v5 +; SI-NEXT: v_readfirstlane_b32 s13, v6 +; SI-NEXT: v_readfirstlane_b32 s10, v7 +; SI-NEXT: v_readfirstlane_b32 s11, v8 +; SI-NEXT: v_readfirstlane_b32 s8, v9 +; SI-NEXT: v_readfirstlane_b32 s9, v10 +; SI-NEXT: v_readfirstlane_b32 s6, v11 +; SI-NEXT: v_readfirstlane_b32 s7, v12 +; SI-NEXT: v_readfirstlane_b32 s4, v13 +; SI-NEXT: s_and_b64 s[42:43], vcc, exec +; SI-NEXT: v_readfirstlane_b32 s5, v14 ; SI-NEXT: s_cbranch_scc0 .LBB53_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s42, s5, 16 @@ -41120,6 +41659,14 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a ; VI-LABEL: bitcast_v14f64_to_v56f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_mov_b32_e32 v20, s17 @@ -41136,14 +41683,6 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_mov_b32_e32 v17, s28 ; VI-NEXT: v_mov_b32_e32 v18, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB53_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v13 @@ -41333,6 +41872,14 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a ; GFX9-LABEL: bitcast_v14f64_to_v56f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; GFX9-NEXT: v_mov_b32_e32 v19, s16 ; GFX9-NEXT: v_mov_b32_e32 v20, s17 @@ -41349,14 +41896,6 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_mov_b32_e32 v17, s28 ; GFX9-NEXT: v_mov_b32_e32 v18, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB53_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v13 @@ -44147,6 +44686,18 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a ; GFX9-LABEL: bitcast_v56f16_to_v14f64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v13 ; GFX9-NEXT: v_mov_b32_e32 v33, v12 ; GFX9-NEXT: v_mov_b32_e32 v34, v11 @@ -44176,18 +44727,6 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34 @@ -44343,90 +44882,167 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a ; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v14f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3 @@ -47265,6 +47881,14 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i ; GFX9-LABEL: bitcast_v56i16_to_v56f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; GFX9-NEXT: s_lshr_b32 s43, s29, 16 ; GFX9-NEXT: s_lshr_b32 s42, s28, 16 @@ -47295,14 +47919,6 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i ; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v0 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB57_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_cbranch_execnz .LBB57_4 @@ -49736,6 +50352,14 @@ define inreg <56 x i16> @bitcast_v56f16_to_v56i16_scalar(<56 x half> inreg %a, i ; VI-LABEL: bitcast_v56f16_to_v56i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; VI-NEXT: s_lshr_b32 s6, s29, 16 ; VI-NEXT: s_lshr_b32 s7, s28, 16 @@ -49766,14 +50390,6 @@ define inreg <56 x i16> @bitcast_v56f16_to_v56i16_scalar(<56 x half> inreg %a, i ; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v0 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB59_3 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB59_4 @@ -49952,6 +50568,14 @@ define inreg <56 x i16> @bitcast_v56f16_to_v56i16_scalar(<56 x half> inreg %a, i ; GFX9-LABEL: bitcast_v56f16_to_v56i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 ; GFX9-NEXT: s_lshr_b32 s43, s29, 16 ; GFX9-NEXT: s_lshr_b32 s42, s28, 16 @@ -49982,14 +50606,6 @@ define inreg <56 x i16> @bitcast_v56f16_to_v56i16_scalar(<56 x half> inreg %a, i ; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v0 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB59_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_cbranch_execnz .LBB59_4 diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll index 93c11f13ce3ce..134980045bb53 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll @@ -2849,7 +2849,6 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v30i32_to_v60i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -2863,6 +2862,7 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr60 ; SI-NEXT: ; implicit-def: $vgpr46 @@ -2892,7 +2892,7 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr39 ; SI-NEXT: ; implicit-def: $vgpr37 -; SI-NEXT: s_waitcnt vmcnt(13) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -3205,7 +3205,6 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) { ; VI-LABEL: bitcast_v30i32_to_v60i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -3218,6 +3217,7 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: ; implicit-def: $vgpr59 ; VI-NEXT: ; implicit-def: $vgpr58 ; VI-NEXT: ; implicit-def: $vgpr57 @@ -3426,7 +3426,6 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) { ; GFX9-LABEL: bitcast_v30i32_to_v60i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -3439,6 +3438,7 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: ; implicit-def: $vgpr59 ; GFX9-NEXT: ; implicit-def: $vgpr58 ; GFX9-NEXT: ; implicit-def: $vgpr57 @@ -3851,23 +3851,24 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v18, s30, 0 -; SI-NEXT: v_writelane_b32 v18, s31, 1 -; SI-NEXT: v_writelane_b32 v18, s34, 2 -; SI-NEXT: v_writelane_b32 v18, s35, 3 -; SI-NEXT: v_writelane_b32 v18, s36, 4 -; SI-NEXT: v_writelane_b32 v18, s37, 5 -; SI-NEXT: v_writelane_b32 v18, s38, 6 -; SI-NEXT: v_writelane_b32 v18, s39, 7 -; SI-NEXT: v_writelane_b32 v18, s48, 8 -; SI-NEXT: v_writelane_b32 v18, s49, 9 -; SI-NEXT: v_writelane_b32 v18, s50, 10 -; SI-NEXT: v_writelane_b32 v18, s51, 11 -; SI-NEXT: v_writelane_b32 v18, s52, 12 -; SI-NEXT: v_writelane_b32 v18, s53, 13 -; SI-NEXT: v_writelane_b32 v18, s54, 14 +; SI-NEXT: v_writelane_b32 v18, s34, 0 +; SI-NEXT: v_writelane_b32 v18, s35, 1 +; SI-NEXT: v_writelane_b32 v18, s36, 2 +; SI-NEXT: v_writelane_b32 v18, s37, 3 +; SI-NEXT: v_writelane_b32 v18, s38, 4 +; SI-NEXT: v_writelane_b32 v18, s39, 5 +; SI-NEXT: v_writelane_b32 v18, s48, 6 +; SI-NEXT: v_writelane_b32 v18, s49, 7 +; SI-NEXT: v_writelane_b32 v18, s50, 8 +; SI-NEXT: v_writelane_b32 v18, s51, 9 +; SI-NEXT: v_writelane_b32 v18, s52, 10 +; SI-NEXT: v_writelane_b32 v18, s53, 11 +; SI-NEXT: v_writelane_b32 v18, s54, 12 +; SI-NEXT: v_writelane_b32 v18, s55, 13 +; SI-NEXT: v_writelane_b32 v18, s64, 14 +; SI-NEXT: v_writelane_b32 v18, s30, 15 +; SI-NEXT: v_writelane_b32 v18, s31, 16 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: v_writelane_b32 v18, s55, 15 ; SI-NEXT: v_readfirstlane_b32 s42, v1 ; SI-NEXT: v_readfirstlane_b32 s43, v2 ; SI-NEXT: v_readfirstlane_b32 s40, v3 @@ -3885,7 +3886,6 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v15 ; SI-NEXT: s_and_b64 s[44:45], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v16 -; SI-NEXT: v_writelane_b32 v18, s64, 16 ; SI-NEXT: s_cbranch_scc0 .LBB13_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s34, s5, 16 @@ -4183,24 +4183,24 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x74, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v18, 15 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s64, v18, 16 -; SI-NEXT: v_readlane_b32 s55, v18, 15 -; SI-NEXT: v_readlane_b32 s54, v18, 14 -; SI-NEXT: v_readlane_b32 s53, v18, 13 -; SI-NEXT: v_readlane_b32 s52, v18, 12 -; SI-NEXT: v_readlane_b32 s51, v18, 11 -; SI-NEXT: v_readlane_b32 s50, v18, 10 -; SI-NEXT: v_readlane_b32 s49, v18, 9 -; SI-NEXT: v_readlane_b32 s48, v18, 8 -; SI-NEXT: v_readlane_b32 s39, v18, 7 -; SI-NEXT: v_readlane_b32 s38, v18, 6 -; SI-NEXT: v_readlane_b32 s37, v18, 5 -; SI-NEXT: v_readlane_b32 s36, v18, 4 -; SI-NEXT: v_readlane_b32 s35, v18, 3 -; SI-NEXT: v_readlane_b32 s34, v18, 2 -; SI-NEXT: v_readlane_b32 s31, v18, 1 -; SI-NEXT: v_readlane_b32 s30, v18, 0 +; SI-NEXT: v_readlane_b32 s31, v18, 16 +; SI-NEXT: v_readlane_b32 s64, v18, 14 +; SI-NEXT: v_readlane_b32 s55, v18, 13 +; SI-NEXT: v_readlane_b32 s54, v18, 12 +; SI-NEXT: v_readlane_b32 s53, v18, 11 +; SI-NEXT: v_readlane_b32 s52, v18, 10 +; SI-NEXT: v_readlane_b32 s51, v18, 9 +; SI-NEXT: v_readlane_b32 s50, v18, 8 +; SI-NEXT: v_readlane_b32 s49, v18, 7 +; SI-NEXT: v_readlane_b32 s48, v18, 6 +; SI-NEXT: v_readlane_b32 s39, v18, 5 +; SI-NEXT: v_readlane_b32 s38, v18, 4 +; SI-NEXT: v_readlane_b32 s37, v18, 3 +; SI-NEXT: v_readlane_b32 s36, v18, 2 +; SI-NEXT: v_readlane_b32 s35, v18, 1 +; SI-NEXT: v_readlane_b32 s34, v18, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -4245,14 +4245,15 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v30, s30, 0 -; VI-NEXT: v_writelane_b32 v30, s31, 1 -; VI-NEXT: v_writelane_b32 v30, s34, 2 -; VI-NEXT: v_writelane_b32 v30, s35, 3 -; VI-NEXT: v_writelane_b32 v30, s36, 4 -; VI-NEXT: v_writelane_b32 v30, s37, 5 +; VI-NEXT: v_writelane_b32 v30, s34, 0 +; VI-NEXT: v_writelane_b32 v30, s35, 1 +; VI-NEXT: v_writelane_b32 v30, s36, 2 +; VI-NEXT: v_writelane_b32 v30, s37, 3 +; VI-NEXT: v_writelane_b32 v30, s38, 4 +; VI-NEXT: v_writelane_b32 v30, s39, 5 +; VI-NEXT: v_writelane_b32 v30, s30, 6 +; VI-NEXT: v_writelane_b32 v30, s31, 7 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 -; VI-NEXT: v_writelane_b32 v30, s38, 6 ; VI-NEXT: v_readfirstlane_b32 s45, v0 ; VI-NEXT: v_readfirstlane_b32 s44, v1 ; VI-NEXT: v_readfirstlane_b32 s43, v2 @@ -4270,7 +4271,6 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s6, v14 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s7, v15 -; VI-NEXT: v_writelane_b32 v30, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB13_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s46, s7, 16 @@ -4456,6 +4456,7 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 ; VI-NEXT: s_lshl_b32 s44, s46, 16 ; VI-NEXT: s_or_b32 s7, s7, s44 +; VI-NEXT: v_readlane_b32 s30, v30, 6 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v2, s16 @@ -4486,14 +4487,13 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; VI-NEXT: v_mov_b32_e32 v27, s8 ; VI-NEXT: v_mov_b32_e32 v28, s6 ; VI-NEXT: v_mov_b32_e32 v29, s7 -; VI-NEXT: v_readlane_b32 s39, v30, 7 -; VI-NEXT: v_readlane_b32 s38, v30, 6 -; VI-NEXT: v_readlane_b32 s37, v30, 5 -; VI-NEXT: v_readlane_b32 s36, v30, 4 -; VI-NEXT: v_readlane_b32 s35, v30, 3 -; VI-NEXT: v_readlane_b32 s34, v30, 2 -; VI-NEXT: v_readlane_b32 s31, v30, 1 -; VI-NEXT: v_readlane_b32 s30, v30, 0 +; VI-NEXT: v_readlane_b32 s31, v30, 7 +; VI-NEXT: v_readlane_b32 s39, v30, 5 +; VI-NEXT: v_readlane_b32 s38, v30, 4 +; VI-NEXT: v_readlane_b32 s37, v30, 3 +; VI-NEXT: v_readlane_b32 s36, v30, 2 +; VI-NEXT: v_readlane_b32 s35, v30, 1 +; VI-NEXT: v_readlane_b32 s34, v30, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -4538,10 +4538,11 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v30, s30, 0 -; GFX9-NEXT: v_writelane_b32 v30, s31, 1 +; GFX9-NEXT: v_writelane_b32 v30, s34, 0 +; GFX9-NEXT: v_writelane_b32 v30, s35, 1 +; GFX9-NEXT: v_writelane_b32 v30, s30, 2 +; GFX9-NEXT: v_writelane_b32 v30, s31, 3 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 -; GFX9-NEXT: v_writelane_b32 v30, s34, 2 ; GFX9-NEXT: v_readfirstlane_b32 s6, v0 ; GFX9-NEXT: v_readfirstlane_b32 s7, v1 ; GFX9-NEXT: v_readfirstlane_b32 s8, v2 @@ -4559,7 +4560,6 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX9-NEXT: v_readfirstlane_b32 s44, v14 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s45, v15 -; GFX9-NEXT: v_writelane_b32 v30, s35, 3 ; GFX9-NEXT: s_cbranch_scc0 .LBB13_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s46, s45, 16 @@ -4685,6 +4685,7 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX9-NEXT: s_pack_ll_b32_b16 s41, s43, s56 ; GFX9-NEXT: s_pack_ll_b32_b16 s42, s44, s47 ; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46 +; GFX9-NEXT: v_readlane_b32 s30, v30, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s16 @@ -4715,10 +4716,9 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX9-NEXT: v_mov_b32_e32 v27, s41 ; GFX9-NEXT: v_mov_b32_e32 v28, s42 ; GFX9-NEXT: v_mov_b32_e32 v29, s43 -; GFX9-NEXT: v_readlane_b32 s35, v30, 3 -; GFX9-NEXT: v_readlane_b32 s34, v30, 2 -; GFX9-NEXT: v_readlane_b32 s31, v30, 1 -; GFX9-NEXT: v_readlane_b32 s30, v30, 0 +; GFX9-NEXT: v_readlane_b32 s31, v30, 3 +; GFX9-NEXT: v_readlane_b32 s35, v30, 1 +; GFX9-NEXT: v_readlane_b32 s34, v30, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -7024,6 +7024,22 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3 ; GFX9-LABEL: bitcast_v60i16_to_v30i32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v15 ; GFX9-NEXT: v_mov_b32_e32 v33, v14 ; GFX9-NEXT: v_mov_b32_e32 v34, v13 @@ -7055,22 +7071,6 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3 ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34 @@ -7240,90 +7240,167 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v30i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 @@ -7701,6 +7778,22 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) { ; SI-LABEL: bitcast_v30i32_to_v60f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; kill: killed $vgpr32 @@ -7735,22 +7828,6 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; kill: killed $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr32 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr57 ; SI-NEXT: ; implicit-def: $vgpr46 @@ -7784,7 +7861,7 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr41 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr42 -; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: ; kill: killed $vgpr31 @@ -8414,7 +8491,6 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) { ; VI-LABEL: bitcast_v30i32_to_v60f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -8427,6 +8503,7 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: ; implicit-def: $vgpr59 ; VI-NEXT: ; implicit-def: $vgpr58 ; VI-NEXT: ; implicit-def: $vgpr57 @@ -8635,7 +8712,6 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) { ; GFX9-LABEL: bitcast_v30i32_to_v60f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -8648,6 +8724,7 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: ; implicit-def: $vgpr59 ; GFX9-NEXT: ; implicit-def: $vgpr58 ; GFX9-NEXT: ; implicit-def: $vgpr57 @@ -9056,6 +9133,19 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; SI-LABEL: bitcast_v30i32_to_v60f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 ; SI-NEXT: v_readfirstlane_b32 s45, v1 ; SI-NEXT: v_readfirstlane_b32 s44, v2 @@ -9074,19 +9164,6 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s6, v15 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v16 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB17_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -9603,14 +9680,15 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v30, s30, 0 -; VI-NEXT: v_writelane_b32 v30, s31, 1 -; VI-NEXT: v_writelane_b32 v30, s34, 2 -; VI-NEXT: v_writelane_b32 v30, s35, 3 -; VI-NEXT: v_writelane_b32 v30, s36, 4 -; VI-NEXT: v_writelane_b32 v30, s37, 5 +; VI-NEXT: v_writelane_b32 v30, s34, 0 +; VI-NEXT: v_writelane_b32 v30, s35, 1 +; VI-NEXT: v_writelane_b32 v30, s36, 2 +; VI-NEXT: v_writelane_b32 v30, s37, 3 +; VI-NEXT: v_writelane_b32 v30, s38, 4 +; VI-NEXT: v_writelane_b32 v30, s39, 5 +; VI-NEXT: v_writelane_b32 v30, s30, 6 +; VI-NEXT: v_writelane_b32 v30, s31, 7 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 -; VI-NEXT: v_writelane_b32 v30, s38, 6 ; VI-NEXT: v_readfirstlane_b32 s45, v0 ; VI-NEXT: v_readfirstlane_b32 s44, v1 ; VI-NEXT: v_readfirstlane_b32 s43, v2 @@ -9628,7 +9706,6 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; VI-NEXT: v_readfirstlane_b32 s6, v14 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s7, v15 -; VI-NEXT: v_writelane_b32 v30, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB17_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s46, s7, 16 @@ -9814,6 +9891,7 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; VI-NEXT: s_and_b32 s7, 0xffff, s7 ; VI-NEXT: s_lshl_b32 s44, s46, 16 ; VI-NEXT: s_or_b32 s7, s7, s44 +; VI-NEXT: v_readlane_b32 s30, v30, 6 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v2, s16 @@ -9844,14 +9922,13 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; VI-NEXT: v_mov_b32_e32 v27, s8 ; VI-NEXT: v_mov_b32_e32 v28, s6 ; VI-NEXT: v_mov_b32_e32 v29, s7 -; VI-NEXT: v_readlane_b32 s39, v30, 7 -; VI-NEXT: v_readlane_b32 s38, v30, 6 -; VI-NEXT: v_readlane_b32 s37, v30, 5 -; VI-NEXT: v_readlane_b32 s36, v30, 4 -; VI-NEXT: v_readlane_b32 s35, v30, 3 -; VI-NEXT: v_readlane_b32 s34, v30, 2 -; VI-NEXT: v_readlane_b32 s31, v30, 1 -; VI-NEXT: v_readlane_b32 s30, v30, 0 +; VI-NEXT: v_readlane_b32 s31, v30, 7 +; VI-NEXT: v_readlane_b32 s39, v30, 5 +; VI-NEXT: v_readlane_b32 s38, v30, 4 +; VI-NEXT: v_readlane_b32 s37, v30, 3 +; VI-NEXT: v_readlane_b32 s36, v30, 2 +; VI-NEXT: v_readlane_b32 s35, v30, 1 +; VI-NEXT: v_readlane_b32 s34, v30, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -9896,10 +9973,11 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v30, s30, 0 -; GFX9-NEXT: v_writelane_b32 v30, s31, 1 +; GFX9-NEXT: v_writelane_b32 v30, s34, 0 +; GFX9-NEXT: v_writelane_b32 v30, s35, 1 +; GFX9-NEXT: v_writelane_b32 v30, s30, 2 +; GFX9-NEXT: v_writelane_b32 v30, s31, 3 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 -; GFX9-NEXT: v_writelane_b32 v30, s34, 2 ; GFX9-NEXT: v_readfirstlane_b32 s6, v0 ; GFX9-NEXT: v_readfirstlane_b32 s7, v1 ; GFX9-NEXT: v_readfirstlane_b32 s8, v2 @@ -9917,7 +9995,6 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX9-NEXT: v_readfirstlane_b32 s44, v14 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s45, v15 -; GFX9-NEXT: v_writelane_b32 v30, s35, 3 ; GFX9-NEXT: s_cbranch_scc0 .LBB17_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s46, s45, 16 @@ -10043,6 +10120,7 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX9-NEXT: s_pack_ll_b32_b16 s41, s43, s56 ; GFX9-NEXT: s_pack_ll_b32_b16 s42, s44, s47 ; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46 +; GFX9-NEXT: v_readlane_b32 s30, v30, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s16 @@ -10073,10 +10151,9 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX9-NEXT: v_mov_b32_e32 v27, s41 ; GFX9-NEXT: v_mov_b32_e32 v28, s42 ; GFX9-NEXT: v_mov_b32_e32 v29, s43 -; GFX9-NEXT: v_readlane_b32 s35, v30, 3 -; GFX9-NEXT: v_readlane_b32 s34, v30, 2 -; GFX9-NEXT: v_readlane_b32 s31, v30, 1 -; GFX9-NEXT: v_readlane_b32 s30, v30, 0 +; GFX9-NEXT: v_readlane_b32 s31, v30, 3 +; GFX9-NEXT: v_readlane_b32 s35, v30, 1 +; GFX9-NEXT: v_readlane_b32 s34, v30, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -12774,6 +12851,22 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; GFX9-LABEL: bitcast_v60f16_to_v30i32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v15 ; GFX9-NEXT: v_mov_b32_e32 v33, v14 ; GFX9-NEXT: v_mov_b32_e32 v34, v13 @@ -12805,22 +12898,6 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34 @@ -12992,90 +13069,167 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v30i32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 @@ -15272,7 +15426,6 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v30f32_to_v60i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -15286,6 +15439,7 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr60 ; SI-NEXT: ; implicit-def: $vgpr46 @@ -15315,7 +15469,7 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr39 ; SI-NEXT: ; implicit-def: $vgpr37 -; SI-NEXT: s_waitcnt vmcnt(13) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -15628,7 +15782,6 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) { ; VI-LABEL: bitcast_v30f32_to_v60i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -15641,6 +15794,7 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: ; implicit-def: $vgpr59 ; VI-NEXT: ; implicit-def: $vgpr58 ; VI-NEXT: ; implicit-def: $vgpr57 @@ -15849,7 +16003,6 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) { ; GFX9-LABEL: bitcast_v30f32_to_v60i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -15862,6 +16015,7 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: ; implicit-def: $vgpr59 ; GFX9-NEXT: ; implicit-def: $vgpr58 ; GFX9-NEXT: ; implicit-def: $vgpr57 @@ -16240,6 +16394,21 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a, ; SI-LABEL: bitcast_v30f32_to_v60i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 ; SI-NEXT: v_mov_b32_e32 v27, s16 ; SI-NEXT: v_mov_b32_e32 v28, s17 @@ -16256,21 +16425,6 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a, ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_mov_b32_e32 v17, s28 ; SI-NEXT: v_mov_b32_e32 v18, s29 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB29_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_lshr_b64 v[31:32], v[15:16], 16 @@ -16611,6 +16765,18 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a, ; VI-LABEL: bitcast_v30f32_to_v60i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_mov_b32_e32 v18, s17 @@ -16627,18 +16793,6 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a, ; VI-NEXT: v_mov_b32_e32 v21, s27 ; VI-NEXT: v_mov_b32_e32 v20, s28 ; VI-NEXT: v_mov_b32_e32 v16, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB29_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v15 @@ -16860,6 +17014,18 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a, ; GFX9-LABEL: bitcast_v30f32_to_v60i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GFX9-NEXT: v_mov_b32_e32 v19, s16 ; GFX9-NEXT: v_mov_b32_e32 v18, s17 @@ -16876,18 +17042,6 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a, ; GFX9-NEXT: v_mov_b32_e32 v21, s27 ; GFX9-NEXT: v_mov_b32_e32 v20, s28 ; GFX9-NEXT: v_mov_b32_e32 v16, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB29_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v15 @@ -19562,6 +19716,22 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a, ; GFX9-LABEL: bitcast_v60i16_to_v30f32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v15 ; GFX9-NEXT: v_mov_b32_e32 v33, v14 ; GFX9-NEXT: v_mov_b32_e32 v34, v13 @@ -19593,22 +19763,6 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34 @@ -19778,90 +19932,167 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v30f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 @@ -20239,6 +20470,22 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) { ; SI-LABEL: bitcast_v30f32_to_v60f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; kill: killed $vgpr32 @@ -20273,22 +20520,6 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; kill: killed $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr32 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr57 ; SI-NEXT: ; implicit-def: $vgpr46 @@ -20322,7 +20553,7 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr41 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr42 -; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: ; kill: killed $vgpr31 @@ -20952,7 +21183,6 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) { ; VI-LABEL: bitcast_v30f32_to_v60f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -20965,6 +21195,7 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: ; implicit-def: $vgpr59 ; VI-NEXT: ; implicit-def: $vgpr58 ; VI-NEXT: ; implicit-def: $vgpr57 @@ -21173,7 +21404,6 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) { ; GFX9-LABEL: bitcast_v30f32_to_v60f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -21186,6 +21416,7 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: ; implicit-def: $vgpr59 ; GFX9-NEXT: ; implicit-def: $vgpr58 ; GFX9-NEXT: ; implicit-def: $vgpr57 @@ -21564,6 +21795,22 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a, ; SI-LABEL: bitcast_v30f32_to_v60f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 ; SI-NEXT: v_readfirstlane_b32 s45, v1 ; SI-NEXT: v_readfirstlane_b32 s44, v2 @@ -21582,22 +21829,6 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a, ; SI-NEXT: v_readfirstlane_b32 s6, v15 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v16 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB33_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -22130,6 +22361,18 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a, ; VI-LABEL: bitcast_v30f32_to_v60f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_mov_b32_e32 v18, s17 @@ -22146,18 +22389,6 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a, ; VI-NEXT: v_mov_b32_e32 v21, s27 ; VI-NEXT: v_mov_b32_e32 v20, s28 ; VI-NEXT: v_mov_b32_e32 v16, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB33_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v15 @@ -22379,6 +22610,18 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a, ; GFX9-LABEL: bitcast_v30f32_to_v60f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GFX9-NEXT: v_mov_b32_e32 v19, s16 ; GFX9-NEXT: v_mov_b32_e32 v18, s17 @@ -22395,18 +22638,6 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a, ; GFX9-NEXT: v_mov_b32_e32 v21, s27 ; GFX9-NEXT: v_mov_b32_e32 v20, s28 ; GFX9-NEXT: v_mov_b32_e32 v16, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB33_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v15 @@ -25473,6 +25704,22 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; GFX9-LABEL: bitcast_v60f16_to_v30f32_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v15 ; GFX9-NEXT: v_mov_b32_e32 v33, v14 ; GFX9-NEXT: v_mov_b32_e32 v34, v13 @@ -25504,22 +25751,6 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34 @@ -25691,90 +25922,167 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v30f32_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 @@ -27041,7 +27349,6 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v15i64_to_v60i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -27055,6 +27362,7 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr60 ; SI-NEXT: ; implicit-def: $vgpr46 @@ -27084,7 +27392,7 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr48 ; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: s_waitcnt vmcnt(13) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -27397,7 +27705,6 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) { ; VI-LABEL: bitcast_v15i64_to_v60i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -27410,6 +27717,7 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: ; implicit-def: $vgpr59 ; VI-NEXT: ; implicit-def: $vgpr58 ; VI-NEXT: ; implicit-def: $vgpr57 @@ -27618,7 +27926,6 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) { ; GFX9-LABEL: bitcast_v15i64_to_v60i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -27631,6 +27938,7 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: ; implicit-def: $vgpr59 ; GFX9-NEXT: ; implicit-def: $vgpr58 ; GFX9-NEXT: ; implicit-def: $vgpr57 @@ -28059,23 +28367,24 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v18, s30, 0 -; SI-NEXT: v_writelane_b32 v18, s31, 1 -; SI-NEXT: v_writelane_b32 v18, s34, 2 -; SI-NEXT: v_writelane_b32 v18, s35, 3 -; SI-NEXT: v_writelane_b32 v18, s36, 4 -; SI-NEXT: v_writelane_b32 v18, s37, 5 -; SI-NEXT: v_writelane_b32 v18, s38, 6 -; SI-NEXT: v_writelane_b32 v18, s39, 7 -; SI-NEXT: v_writelane_b32 v18, s48, 8 -; SI-NEXT: v_writelane_b32 v18, s49, 9 -; SI-NEXT: v_writelane_b32 v18, s50, 10 -; SI-NEXT: v_writelane_b32 v18, s51, 11 -; SI-NEXT: v_writelane_b32 v18, s52, 12 -; SI-NEXT: v_writelane_b32 v18, s53, 13 -; SI-NEXT: v_writelane_b32 v18, s54, 14 +; SI-NEXT: v_writelane_b32 v18, s34, 0 +; SI-NEXT: v_writelane_b32 v18, s35, 1 +; SI-NEXT: v_writelane_b32 v18, s36, 2 +; SI-NEXT: v_writelane_b32 v18, s37, 3 +; SI-NEXT: v_writelane_b32 v18, s38, 4 +; SI-NEXT: v_writelane_b32 v18, s39, 5 +; SI-NEXT: v_writelane_b32 v18, s48, 6 +; SI-NEXT: v_writelane_b32 v18, s49, 7 +; SI-NEXT: v_writelane_b32 v18, s50, 8 +; SI-NEXT: v_writelane_b32 v18, s51, 9 +; SI-NEXT: v_writelane_b32 v18, s52, 10 +; SI-NEXT: v_writelane_b32 v18, s53, 11 +; SI-NEXT: v_writelane_b32 v18, s54, 12 +; SI-NEXT: v_writelane_b32 v18, s55, 13 +; SI-NEXT: v_writelane_b32 v18, s64, 14 +; SI-NEXT: v_writelane_b32 v18, s30, 15 +; SI-NEXT: v_writelane_b32 v18, s31, 16 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: v_writelane_b32 v18, s55, 15 ; SI-NEXT: v_readfirstlane_b32 s42, v1 ; SI-NEXT: v_readfirstlane_b32 s43, v2 ; SI-NEXT: v_readfirstlane_b32 s40, v3 @@ -28093,7 +28402,6 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s4, v15 ; SI-NEXT: s_and_b64 s[44:45], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v16 -; SI-NEXT: v_writelane_b32 v18, s64, 16 ; SI-NEXT: s_cbranch_scc0 .LBB41_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s34, s5, 16 @@ -28391,24 +28699,24 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x74, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 +; SI-NEXT: v_readlane_b32 s30, v18, 15 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s64, v18, 16 -; SI-NEXT: v_readlane_b32 s55, v18, 15 -; SI-NEXT: v_readlane_b32 s54, v18, 14 -; SI-NEXT: v_readlane_b32 s53, v18, 13 -; SI-NEXT: v_readlane_b32 s52, v18, 12 -; SI-NEXT: v_readlane_b32 s51, v18, 11 -; SI-NEXT: v_readlane_b32 s50, v18, 10 -; SI-NEXT: v_readlane_b32 s49, v18, 9 -; SI-NEXT: v_readlane_b32 s48, v18, 8 -; SI-NEXT: v_readlane_b32 s39, v18, 7 -; SI-NEXT: v_readlane_b32 s38, v18, 6 -; SI-NEXT: v_readlane_b32 s37, v18, 5 -; SI-NEXT: v_readlane_b32 s36, v18, 4 -; SI-NEXT: v_readlane_b32 s35, v18, 3 -; SI-NEXT: v_readlane_b32 s34, v18, 2 -; SI-NEXT: v_readlane_b32 s31, v18, 1 -; SI-NEXT: v_readlane_b32 s30, v18, 0 +; SI-NEXT: v_readlane_b32 s31, v18, 16 +; SI-NEXT: v_readlane_b32 s64, v18, 14 +; SI-NEXT: v_readlane_b32 s55, v18, 13 +; SI-NEXT: v_readlane_b32 s54, v18, 12 +; SI-NEXT: v_readlane_b32 s53, v18, 11 +; SI-NEXT: v_readlane_b32 s52, v18, 10 +; SI-NEXT: v_readlane_b32 s51, v18, 9 +; SI-NEXT: v_readlane_b32 s50, v18, 8 +; SI-NEXT: v_readlane_b32 s49, v18, 7 +; SI-NEXT: v_readlane_b32 s48, v18, 6 +; SI-NEXT: v_readlane_b32 s39, v18, 5 +; SI-NEXT: v_readlane_b32 s38, v18, 4 +; SI-NEXT: v_readlane_b32 s37, v18, 3 +; SI-NEXT: v_readlane_b32 s36, v18, 2 +; SI-NEXT: v_readlane_b32 s35, v18, 1 +; SI-NEXT: v_readlane_b32 s34, v18, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] @@ -28453,14 +28761,15 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v30, s30, 0 -; VI-NEXT: v_writelane_b32 v30, s31, 1 -; VI-NEXT: v_writelane_b32 v30, s34, 2 -; VI-NEXT: v_writelane_b32 v30, s35, 3 -; VI-NEXT: v_writelane_b32 v30, s36, 4 -; VI-NEXT: v_writelane_b32 v30, s37, 5 +; VI-NEXT: v_writelane_b32 v30, s34, 0 +; VI-NEXT: v_writelane_b32 v30, s35, 1 +; VI-NEXT: v_writelane_b32 v30, s36, 2 +; VI-NEXT: v_writelane_b32 v30, s37, 3 +; VI-NEXT: v_writelane_b32 v30, s38, 4 +; VI-NEXT: v_writelane_b32 v30, s39, 5 +; VI-NEXT: v_writelane_b32 v30, s30, 6 +; VI-NEXT: v_writelane_b32 v30, s31, 7 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 -; VI-NEXT: v_writelane_b32 v30, s38, 6 ; VI-NEXT: v_readfirstlane_b32 s45, v0 ; VI-NEXT: v_readfirstlane_b32 s44, v1 ; VI-NEXT: v_readfirstlane_b32 s43, v2 @@ -28478,7 +28787,6 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s6, v14 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s7, v15 -; VI-NEXT: v_writelane_b32 v30, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB41_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s46, s7, 16 @@ -28664,6 +28972,7 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 ; VI-NEXT: s_lshl_b32 s44, s46, 16 ; VI-NEXT: s_or_b32 s7, s7, s44 +; VI-NEXT: v_readlane_b32 s30, v30, 6 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v2, s16 @@ -28694,14 +29003,13 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; VI-NEXT: v_mov_b32_e32 v27, s8 ; VI-NEXT: v_mov_b32_e32 v28, s6 ; VI-NEXT: v_mov_b32_e32 v29, s7 -; VI-NEXT: v_readlane_b32 s39, v30, 7 -; VI-NEXT: v_readlane_b32 s38, v30, 6 -; VI-NEXT: v_readlane_b32 s37, v30, 5 -; VI-NEXT: v_readlane_b32 s36, v30, 4 -; VI-NEXT: v_readlane_b32 s35, v30, 3 -; VI-NEXT: v_readlane_b32 s34, v30, 2 -; VI-NEXT: v_readlane_b32 s31, v30, 1 -; VI-NEXT: v_readlane_b32 s30, v30, 0 +; VI-NEXT: v_readlane_b32 s31, v30, 7 +; VI-NEXT: v_readlane_b32 s39, v30, 5 +; VI-NEXT: v_readlane_b32 s38, v30, 4 +; VI-NEXT: v_readlane_b32 s37, v30, 3 +; VI-NEXT: v_readlane_b32 s36, v30, 2 +; VI-NEXT: v_readlane_b32 s35, v30, 1 +; VI-NEXT: v_readlane_b32 s34, v30, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -28746,10 +29054,11 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v30, s30, 0 -; GFX9-NEXT: v_writelane_b32 v30, s31, 1 +; GFX9-NEXT: v_writelane_b32 v30, s34, 0 +; GFX9-NEXT: v_writelane_b32 v30, s35, 1 +; GFX9-NEXT: v_writelane_b32 v30, s30, 2 +; GFX9-NEXT: v_writelane_b32 v30, s31, 3 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 -; GFX9-NEXT: v_writelane_b32 v30, s34, 2 ; GFX9-NEXT: v_readfirstlane_b32 s6, v0 ; GFX9-NEXT: v_readfirstlane_b32 s7, v1 ; GFX9-NEXT: v_readfirstlane_b32 s8, v2 @@ -28767,7 +29076,6 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX9-NEXT: v_readfirstlane_b32 s44, v14 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s45, v15 -; GFX9-NEXT: v_writelane_b32 v30, s35, 3 ; GFX9-NEXT: s_cbranch_scc0 .LBB41_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s46, s45, 16 @@ -28893,6 +29201,7 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX9-NEXT: s_pack_ll_b32_b16 s41, s43, s56 ; GFX9-NEXT: s_pack_ll_b32_b16 s42, s44, s47 ; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46 +; GFX9-NEXT: v_readlane_b32 s30, v30, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s16 @@ -28923,10 +29232,9 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX9-NEXT: v_mov_b32_e32 v27, s41 ; GFX9-NEXT: v_mov_b32_e32 v28, s42 ; GFX9-NEXT: v_mov_b32_e32 v29, s43 -; GFX9-NEXT: v_readlane_b32 s35, v30, 3 -; GFX9-NEXT: v_readlane_b32 s34, v30, 2 -; GFX9-NEXT: v_readlane_b32 s31, v30, 1 -; GFX9-NEXT: v_readlane_b32 s30, v30, 0 +; GFX9-NEXT: v_readlane_b32 s31, v30, 3 +; GFX9-NEXT: v_readlane_b32 s35, v30, 1 +; GFX9-NEXT: v_readlane_b32 s34, v30, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -31232,6 +31540,22 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3 ; GFX9-LABEL: bitcast_v60i16_to_v15i64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v15 ; GFX9-NEXT: v_mov_b32_e32 v33, v14 ; GFX9-NEXT: v_mov_b32_e32 v34, v13 @@ -31263,22 +31587,6 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3 ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34 @@ -31448,90 +31756,167 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3 ; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v15i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 @@ -31909,6 +32294,22 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) { ; SI-LABEL: bitcast_v15i64_to_v60f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; kill: killed $vgpr32 @@ -31943,22 +32344,6 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; kill: killed $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr32 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr57 ; SI-NEXT: ; implicit-def: $vgpr46 @@ -31992,7 +32377,7 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr41 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr42 -; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: ; kill: killed $vgpr31 @@ -32623,7 +33008,6 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) { ; VI-LABEL: bitcast_v15i64_to_v60f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -32636,6 +33020,7 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: ; implicit-def: $vgpr59 ; VI-NEXT: ; implicit-def: $vgpr58 ; VI-NEXT: ; implicit-def: $vgpr57 @@ -32844,7 +33229,6 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) { ; GFX9-LABEL: bitcast_v15i64_to_v60f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -32857,6 +33241,7 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: ; implicit-def: $vgpr59 ; GFX9-NEXT: ; implicit-def: $vgpr58 ; GFX9-NEXT: ; implicit-def: $vgpr57 @@ -33281,6 +33666,19 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; SI-LABEL: bitcast_v15i64_to_v60f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 ; SI-NEXT: v_readfirstlane_b32 s44, v1 ; SI-NEXT: v_readfirstlane_b32 s45, v2 @@ -33299,19 +33697,6 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; SI-NEXT: v_readfirstlane_b32 s6, v15 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v16 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB45_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s4, s9, 16 @@ -33828,14 +34213,15 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v30, s30, 0 -; VI-NEXT: v_writelane_b32 v30, s31, 1 -; VI-NEXT: v_writelane_b32 v30, s34, 2 -; VI-NEXT: v_writelane_b32 v30, s35, 3 -; VI-NEXT: v_writelane_b32 v30, s36, 4 -; VI-NEXT: v_writelane_b32 v30, s37, 5 +; VI-NEXT: v_writelane_b32 v30, s34, 0 +; VI-NEXT: v_writelane_b32 v30, s35, 1 +; VI-NEXT: v_writelane_b32 v30, s36, 2 +; VI-NEXT: v_writelane_b32 v30, s37, 3 +; VI-NEXT: v_writelane_b32 v30, s38, 4 +; VI-NEXT: v_writelane_b32 v30, s39, 5 +; VI-NEXT: v_writelane_b32 v30, s30, 6 +; VI-NEXT: v_writelane_b32 v30, s31, 7 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 -; VI-NEXT: v_writelane_b32 v30, s38, 6 ; VI-NEXT: v_readfirstlane_b32 s45, v0 ; VI-NEXT: v_readfirstlane_b32 s44, v1 ; VI-NEXT: v_readfirstlane_b32 s43, v2 @@ -33853,7 +34239,6 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; VI-NEXT: v_readfirstlane_b32 s6, v14 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s7, v15 -; VI-NEXT: v_writelane_b32 v30, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB45_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_lshr_b32 s46, s7, 16 @@ -34039,6 +34424,7 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; VI-NEXT: s_and_b32 s7, 0xffff, s7 ; VI-NEXT: s_lshl_b32 s44, s46, 16 ; VI-NEXT: s_or_b32 s7, s7, s44 +; VI-NEXT: v_readlane_b32 s30, v30, 6 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 ; VI-NEXT: v_mov_b32_e32 v2, s16 @@ -34069,14 +34455,13 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; VI-NEXT: v_mov_b32_e32 v27, s8 ; VI-NEXT: v_mov_b32_e32 v28, s6 ; VI-NEXT: v_mov_b32_e32 v29, s7 -; VI-NEXT: v_readlane_b32 s39, v30, 7 -; VI-NEXT: v_readlane_b32 s38, v30, 6 -; VI-NEXT: v_readlane_b32 s37, v30, 5 -; VI-NEXT: v_readlane_b32 s36, v30, 4 -; VI-NEXT: v_readlane_b32 s35, v30, 3 -; VI-NEXT: v_readlane_b32 s34, v30, 2 -; VI-NEXT: v_readlane_b32 s31, v30, 1 -; VI-NEXT: v_readlane_b32 s30, v30, 0 +; VI-NEXT: v_readlane_b32 s31, v30, 7 +; VI-NEXT: v_readlane_b32 s39, v30, 5 +; VI-NEXT: v_readlane_b32 s38, v30, 4 +; VI-NEXT: v_readlane_b32 s37, v30, 3 +; VI-NEXT: v_readlane_b32 s36, v30, 2 +; VI-NEXT: v_readlane_b32 s35, v30, 1 +; VI-NEXT: v_readlane_b32 s34, v30, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] @@ -34121,10 +34506,11 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v30, s30, 0 -; GFX9-NEXT: v_writelane_b32 v30, s31, 1 +; GFX9-NEXT: v_writelane_b32 v30, s34, 0 +; GFX9-NEXT: v_writelane_b32 v30, s35, 1 +; GFX9-NEXT: v_writelane_b32 v30, s30, 2 +; GFX9-NEXT: v_writelane_b32 v30, s31, 3 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 -; GFX9-NEXT: v_writelane_b32 v30, s34, 2 ; GFX9-NEXT: v_readfirstlane_b32 s6, v0 ; GFX9-NEXT: v_readfirstlane_b32 s7, v1 ; GFX9-NEXT: v_readfirstlane_b32 s8, v2 @@ -34142,7 +34528,6 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX9-NEXT: v_readfirstlane_b32 s44, v14 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s45, v15 -; GFX9-NEXT: v_writelane_b32 v30, s35, 3 ; GFX9-NEXT: s_cbranch_scc0 .LBB45_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s46, s45, 16 @@ -34268,6 +34653,7 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX9-NEXT: s_pack_ll_b32_b16 s41, s43, s56 ; GFX9-NEXT: s_pack_ll_b32_b16 s42, s44, s47 ; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46 +; GFX9-NEXT: v_readlane_b32 s30, v30, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s16 @@ -34298,10 +34684,9 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX9-NEXT: v_mov_b32_e32 v27, s41 ; GFX9-NEXT: v_mov_b32_e32 v28, s42 ; GFX9-NEXT: v_mov_b32_e32 v29, s43 -; GFX9-NEXT: v_readlane_b32 s35, v30, 3 -; GFX9-NEXT: v_readlane_b32 s34, v30, 2 -; GFX9-NEXT: v_readlane_b32 s31, v30, 1 -; GFX9-NEXT: v_readlane_b32 s30, v30, 0 +; GFX9-NEXT: v_readlane_b32 s31, v30, 3 +; GFX9-NEXT: v_readlane_b32 s35, v30, 1 +; GFX9-NEXT: v_readlane_b32 s34, v30, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -36999,6 +37384,22 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; GFX9-LABEL: bitcast_v60f16_to_v15i64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v15 ; GFX9-NEXT: v_mov_b32_e32 v33, v14 ; GFX9-NEXT: v_mov_b32_e32 v34, v13 @@ -37030,22 +37431,6 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34 @@ -37217,90 +37602,167 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v15i64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 @@ -37678,7 +38140,6 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v15f64_to_v60i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -37692,6 +38153,7 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr60 ; SI-NEXT: ; implicit-def: $vgpr46 @@ -37721,7 +38183,7 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr48 ; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: s_waitcnt vmcnt(13) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -38019,7 +38481,6 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) { ; VI-LABEL: bitcast_v15f64_to_v60i16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -38032,6 +38493,7 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: ; implicit-def: $vgpr59 ; VI-NEXT: ; implicit-def: $vgpr58 ; VI-NEXT: ; implicit-def: $vgpr57 @@ -38225,7 +38687,6 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) { ; GFX9-LABEL: bitcast_v15f64_to_v60i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -38238,6 +38699,7 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: ; implicit-def: $vgpr59 ; GFX9-NEXT: ; implicit-def: $vgpr58 ; GFX9-NEXT: ; implicit-def: $vgpr57 @@ -38601,22 +39063,6 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a, ; SI-LABEL: bitcast_v15f64_to_v60i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: v_mov_b32_e32 v27, s16 -; SI-NEXT: v_mov_b32_e32 v28, s17 -; SI-NEXT: v_mov_b32_e32 v29, s18 -; SI-NEXT: v_mov_b32_e32 v30, s19 -; SI-NEXT: v_mov_b32_e32 v25, s20 -; SI-NEXT: v_mov_b32_e32 v26, s21 -; SI-NEXT: v_mov_b32_e32 v23, s22 -; SI-NEXT: v_mov_b32_e32 v24, s23 -; SI-NEXT: v_mov_b32_e32 v21, s24 -; SI-NEXT: v_mov_b32_e32 v22, s25 -; SI-NEXT: v_mov_b32_e32 v19, s26 -; SI-NEXT: v_mov_b32_e32 v20, s27 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_mov_b32_e32 v17, s28 -; SI-NEXT: v_mov_b32_e32 v18, s29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -38633,6 +39079,22 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a, ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 +; SI-NEXT: v_mov_b32_e32 v27, s16 +; SI-NEXT: v_mov_b32_e32 v28, s17 +; SI-NEXT: v_mov_b32_e32 v29, s18 +; SI-NEXT: v_mov_b32_e32 v30, s19 +; SI-NEXT: v_mov_b32_e32 v25, s20 +; SI-NEXT: v_mov_b32_e32 v26, s21 +; SI-NEXT: v_mov_b32_e32 v23, s22 +; SI-NEXT: v_mov_b32_e32 v24, s23 +; SI-NEXT: v_mov_b32_e32 v21, s24 +; SI-NEXT: v_mov_b32_e32 v22, s25 +; SI-NEXT: v_mov_b32_e32 v19, s26 +; SI-NEXT: v_mov_b32_e32 v20, s27 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_mov_b32_e32 v17, s28 +; SI-NEXT: v_mov_b32_e32 v18, s29 ; SI-NEXT: s_cbranch_scc0 .LBB49_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: v_lshr_b64 v[31:32], v[15:16], 16 @@ -38959,6 +39421,18 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a, ; VI-LABEL: bitcast_v15f64_to_v60i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; VI-NEXT: v_mov_b32_e32 v17, s16 ; VI-NEXT: v_mov_b32_e32 v18, s17 @@ -38975,18 +39449,6 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a, ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_mov_b32_e32 v19, s28 ; VI-NEXT: v_mov_b32_e32 v20, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB49_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v15 @@ -39193,6 +39655,18 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a, ; GFX9-LABEL: bitcast_v15f64_to_v60i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GFX9-NEXT: v_mov_b32_e32 v17, s16 ; GFX9-NEXT: v_mov_b32_e32 v18, s17 @@ -39209,18 +39683,6 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a, ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_mov_b32_e32 v19, s28 ; GFX9-NEXT: v_mov_b32_e32 v20, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB49_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v15 @@ -41880,6 +42342,22 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a, ; GFX9-LABEL: bitcast_v60i16_to_v15f64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v15 ; GFX9-NEXT: v_mov_b32_e32 v33, v14 ; GFX9-NEXT: v_mov_b32_e32 v34, v13 @@ -41911,22 +42389,6 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a, ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34 @@ -42096,90 +42558,167 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a, ; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v15f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 @@ -42557,6 +43096,22 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) { ; SI-LABEL: bitcast_v15f64_to_v60f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 ; SI-NEXT: ; implicit-def: $vgpr38 ; SI-NEXT: ; kill: killed $vgpr38 @@ -42579,22 +43134,6 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr38 ; SI-NEXT: ; kill: killed $vgpr38 ; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr41 ; SI-NEXT: ; implicit-def: $vgpr57 ; SI-NEXT: ; implicit-def: $vgpr55 @@ -42627,7 +43166,7 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) { ; SI-NEXT: ; kill: killed $vgpr38 ; SI-NEXT: ; implicit-def: $vgpr48 ; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: ; kill: killed $vgpr31 @@ -43240,7 +43779,6 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) { ; VI-LABEL: bitcast_v15f64_to_v60f16: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -43253,6 +43791,7 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) { ; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; VI-NEXT: ; implicit-def: $vgpr59 ; VI-NEXT: ; implicit-def: $vgpr58 ; VI-NEXT: ; implicit-def: $vgpr57 @@ -43446,7 +43985,6 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) { ; GFX9-LABEL: bitcast_v15f64_to_v60f16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill @@ -43459,6 +43997,7 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: ; implicit-def: $vgpr59 ; GFX9-NEXT: ; implicit-def: $vgpr58 ; GFX9-NEXT: ; implicit-def: $vgpr57 @@ -43822,6 +44361,22 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a ; SI-LABEL: bitcast_v15f64_to_v60f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 ; SI-NEXT: v_readfirstlane_b32 s42, v1 ; SI-NEXT: v_readfirstlane_b32 s43, v2 @@ -43840,22 +44395,6 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a ; SI-NEXT: v_readfirstlane_b32 s4, v15 ; SI-NEXT: s_and_b64 s[44:45], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v16 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB53_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s44, s5, 16 @@ -44378,6 +44917,18 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a ; VI-LABEL: bitcast_v15f64_to_v60f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; VI-NEXT: v_mov_b32_e32 v17, s16 ; VI-NEXT: v_mov_b32_e32 v18, s17 @@ -44394,18 +44945,6 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_mov_b32_e32 v19, s28 ; VI-NEXT: v_mov_b32_e32 v20, s29 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB53_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v15 @@ -44612,6 +45151,18 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a ; GFX9-LABEL: bitcast_v15f64_to_v60f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GFX9-NEXT: v_mov_b32_e32 v17, s16 ; GFX9-NEXT: v_mov_b32_e32 v18, s17 @@ -44628,18 +45179,6 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_mov_b32_e32 v19, s28 ; GFX9-NEXT: v_mov_b32_e32 v20, s29 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB53_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v15 @@ -47691,6 +48230,22 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; GFX9-LABEL: bitcast_v60f16_to_v15f64_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v32, v15 ; GFX9-NEXT: v_mov_b32_e32 v33, v14 ; GFX9-NEXT: v_mov_b32_e32 v34, v13 @@ -47722,22 +48277,6 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; GFX9-NEXT: s_lshr_b32 s8, s18, 16 ; GFX9-NEXT: s_lshr_b32 s7, s17, 16 ; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32 ; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33 ; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34 @@ -47909,90 +48448,167 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v15f64_scalar: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 ; GFX11-TRUE16-NEXT: s_clause 0xf ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 +; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 @@ -51092,6 +51708,18 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i ; GFX9-LABEL: bitcast_v60i16_to_v60f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GFX9-NEXT: s_lshr_b32 s43, s29, 16 ; GFX9-NEXT: s_lshr_b32 s42, s28, 16 @@ -51124,18 +51752,6 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i ; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v0 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB57_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_cbranch_execnz .LBB57_4 @@ -53772,6 +54388,18 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; VI-LABEL: bitcast_v60f16_to_v60i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; VI-NEXT: s_lshr_b32 s6, s29, 16 ; VI-NEXT: s_lshr_b32 s7, s28, 16 @@ -53804,18 +54432,6 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v0 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB59_3 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB59_4 @@ -54008,6 +54624,18 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; GFX9-LABEL: bitcast_v60f16_to_v60i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GFX9-NEXT: s_lshr_b32 s43, s29, 16 ; GFX9-NEXT: s_lshr_b32 s42, s28, 16 @@ -54040,18 +54668,6 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v0 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_cbranch_scc0 .LBB59_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_cbranch_execnz .LBB59_4 diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll new file mode 100644 index 0000000000000..68002c590f47c --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll @@ -0,0 +1,34727 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=tonga -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=VI %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s + +; This test just checks that the compiler doesn't crash. + + +define amdgpu_ps float @v32i8_to_v8i32(ptr addrspace(4) inreg) #0 { +; GCN-LABEL: v32i8_to_v8i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[0:1], 0x1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[0:1] +; GCN-NEXT: ; return to shader part epilog +; +; VI-LABEL: v32i8_to_v8i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[0:1], 0x4 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_cselect_b64 s[0:1], -1, 0 +; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[0:1] +; VI-NEXT: ; return to shader part epilog +; +; GFX9-LABEL: v32i8_to_v8i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[0:1], 0x4 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s[0:1] +; GFX9-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: v32i8_to_v8i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x4 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_cselect_b32 s0, -1, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s0 +; GFX11-NEXT: ; return to shader part epilog +entry: + %1 = load <32 x i8>, ptr addrspace(4) %0 + %2 = bitcast <32 x i8> %1 to <8 x i32> + %3 = extractelement <8 x i32> %2, i32 1 + %4 = icmp ne i32 %3, 0 + %5 = select i1 %4, float 0.0, float 1.0 + ret float %5 +} + +define amdgpu_kernel void @i8ptr_v16i8ptr(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; GCN-LABEL: i8ptr_v16i8ptr: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s7 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: i8ptr_v16i8ptr: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v0, s4 +; VI-NEXT: v_mov_b32_e32 v1, s5 +; VI-NEXT: v_mov_b32_e32 v2, s6 +; VI-NEXT: v_mov_b32_e32 v3, s7 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: i8ptr_v16i8ptr: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: i8ptr_v16i8ptr: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0 +; GFX11-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7 +; GFX11-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6 +; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1] +; GFX11-NEXT: s_endpgm +entry: + %0 = load <16 x i8>, ptr addrspace(1) %in + store <16 x i8> %0, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @f32_to_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: f32_to_v2i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dword s4, s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_add_f32_e64 v0, s4, 1.0 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, 2, v0 +; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GCN-NEXT: v_or_b32_e32 v0, v1, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x20000, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: f32_to_v2i16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dword s2, s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_add_f32_e64 v2, s2, 1.0 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 +; VI-NEXT: v_add_u32_e32 v2, vcc, 2, v2 +; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x20000, v2 +; VI-NEXT: flat_store_dword v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: f32_to_v2i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_add_f32_e64 v1, s2, 1.0 +; GFX9-NEXT: v_pk_add_u16 v1, v1, 2 op_sel_hi:[1,0] +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: f32_to_v2i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_add_f32_e64 v0, s2, 1.0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_pk_add_u16 v0, v0, 2 op_sel_hi:[1,0] +; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11-NEXT: s_endpgm + %load = load float, ptr addrspace(1) %in, align 4 + %fadd32 = fadd float %load, 1.0 + %bc = bitcast float %fadd32 to <2 x i16> + %add.bitcast = add <2 x i16> %bc, + store <2 x i16> %add.bitcast, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @v2i16_to_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v2i16_to_f32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dword s4, s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s5, s4, 0xffff0000 +; GCN-NEXT: s_add_i32 s4, s4, 2 +; GCN-NEXT: s_and_b32 s4, s4, 0xffff +; GCN-NEXT: s_or_b32 s4, s5, s4 +; GCN-NEXT: s_add_i32 s4, s4, 0x20000 +; GCN-NEXT: v_add_f32_e64 v0, s4, 1.0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v2i16_to_f32: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dword s2, s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_and_b32 s0, s2, 0xffff0000 +; VI-NEXT: s_add_i32 s2, s2, 2 +; VI-NEXT: s_and_b32 s1, s2, 0xffff +; VI-NEXT: s_or_b32 s0, s0, s1 +; VI-NEXT: s_add_i32 s0, s0, 0x20000 +; VI-NEXT: v_add_f32_e64 v2, s0, 1.0 +; VI-NEXT: flat_store_dword v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v2i16_to_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_pk_add_u16 v1, s2, 2 op_sel_hi:[1,0] +; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v2i16_to_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_pk_add_u16 v0, s2, 2 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_f32 v0, 1.0, v0 +; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <2 x i16>, ptr addrspace(1) %in, align 4 + %add.v2i16 = add <2 x i16> %load, + %bc = bitcast <2 x i16> %add.v2i16 to float + %fadd.bitcast = fadd float %bc, 1.0 + store float %fadd.bitcast, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @f32_to_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: f32_to_v2f16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dword s4, s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_add_f32_e64 v0, s4, 1.0 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GCN-NEXT: v_add_f32_e32 v0, 2.0, v0 +; GCN-NEXT: v_add_f32_e32 v1, 2.0, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_or_b32_e32 v0, v0, v1 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: f32_to_v2f16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v2, 0x4000 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dword s2, s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_add_f32_e64 v3, s2, 1.0 +; VI-NEXT: v_add_f16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v3, 2.0, v3 +; VI-NEXT: v_or_b32_e32 v2, v3, v2 +; VI-NEXT: flat_store_dword v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: f32_to_v2f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_add_f32_e64 v1, s2, 1.0 +; GFX9-NEXT: v_pk_add_f16 v1, v1, 2.0 op_sel_hi:[1,0] +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: f32_to_v2f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_add_f32_e64 v0, s2, 1.0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_pk_add_f16 v0, v0, 2.0 op_sel_hi:[1,0] +; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11-NEXT: s_endpgm + %load = load float, ptr addrspace(1) %in, align 4 + %fadd32 = fadd float %load, 1.0 + %bc = bitcast float %fadd32 to <2 x half> + %add.bitcast = fadd <2 x half> %bc, + store <2 x half> %add.bitcast, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @v2f16_to_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v2f16_to_f32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dword s4, s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v0, s4 +; GCN-NEXT: s_lshr_b32 s4, s4, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, s4 +; GCN-NEXT: v_add_f32_e32 v0, 2.0, v0 +; GCN-NEXT: v_add_f32_e32 v1, 2.0, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_or_b32_e32 v0, v0, v1 +; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v2f16_to_f32: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v2, 0x4000 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dword s2, s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_lshr_b32 s0, s2, 16 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_add_f16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_add_f16_e64 v3, s2, 2.0 +; VI-NEXT: v_or_b32_e32 v2, v3, v2 +; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; VI-NEXT: flat_store_dword v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v2f16_to_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v1, s2, 2.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v2f16_to_f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v0, s2, 2.0 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_f32 v0, 1.0, v0 +; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <2 x half>, ptr addrspace(1) %in, align 4 + %add.v2f16 = fadd <2 x half> %load, + %bc = bitcast <2 x half> %add.v2f16 to float + %fadd.bitcast = fadd float %bc, 1.0 + store float %fadd.bitcast, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @v4i8_to_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v4i8_to_i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dword s4, s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v4i8_to_i32: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dword s2, s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: flat_store_dword v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v4i8_to_i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v1, s2 +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v4i8_to_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <4 x i8>, ptr addrspace(1) %in, align 4 + %bc = bitcast <4 x i8> %load to i32 + store i32 %bc, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_kernel void @i32_to_v4i8(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: i32_to_v4i8: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dword s4, s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: i32_to_v4i8: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dword s2, s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: flat_store_dword v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: i32_to_v4i8: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v1, s2 +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: i32_to_v4i8: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_endpgm + %load = load i32, ptr addrspace(1) %in, align 4 + %bc = bitcast i32 %load to <4 x i8> + store <4 x i8> %bc, ptr addrspace(1) %out, align 4 + ret void +} + + +define amdgpu_kernel void @bitcast_v2i32_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; GCN-LABEL: bitcast_v2i32_to_f64: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s5, s5, 9 +; GCN-NEXT: s_add_i32 s4, s4, 4 +; GCN-NEXT: v_add_f64 v[0:1], s[4:5], 1.0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v2i32_to_f64: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_i32 s3, s3, 9 +; VI-NEXT: s_add_i32 s2, s2, 4 +; VI-NEXT: v_add_f64 v[0:1], s[2:3], 1.0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v2i32_to_f64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_add_i32 s3, s3, 9 +; GFX9-NEXT: s_add_i32 s2, s2, 4 +; GFX9-NEXT: v_add_f64 v[0:1], s[2:3], 1.0 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v2i32_to_f64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_add_i32 s3, s3, 9 +; GFX11-NEXT: s_add_i32 s2, s2, 4 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_add_f64 v[0:1], s[2:3], 1.0 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %val = load <2 x i32>, ptr addrspace(1) %in, align 8 + %add = add <2 x i32> %val, + %bc = bitcast <2 x i32> %add to double + %fadd.bc = fadd double %bc, 1.0 + store double %fadd.bc, ptr addrspace(1) %out, align 8 + ret void +} + + +define amdgpu_kernel void @bitcast_f64_to_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; GCN-LABEL: bitcast_f64_to_v2i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_add_f64 v[0:1], s[4:5], 4.0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_f64_to_v2i32: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_add_f64 v[0:1], s[2:3], 4.0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_f64_to_v2i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_add_f64 v[0:1], s[2:3], 4.0 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_f64_to_v2i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_add_f64 v[0:1], s[2:3], 4.0 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %val = load double, ptr addrspace(1) %in, align 8 + %add = fadd double %val, 4.0 + %bc = bitcast double %add to <2 x i32> + store <2 x i32> %bc, ptr addrspace(1) %out, align 8 + ret void +} + + +define amdgpu_kernel void @bitcast_v2i64_to_v2f64(i32 %cond, ptr addrspace(1) %out, <2 x i64> %value) { +; GCN-LABEL: bitcast_v2i64_to_v2f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s9, s[4:5], 0x9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb +; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xf +; GCN-NEXT: s_mov_b32 s8, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s9, 0 +; GCN-NEXT: s_mov_b32 s9, s8 +; GCN-NEXT: s_mov_b32 s10, s8 +; GCN-NEXT: s_mov_b32 s11, s8 +; GCN-NEXT: s_cbranch_scc1 .LBB10_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: s_mov_b32 s4, s2 +; GCN-NEXT: s_mov_b32 s5, s3 +; GCN-NEXT: s_mov_b64 s[10:11], s[6:7] +; GCN-NEXT: s_mov_b64 s[8:9], s[4:5] +; GCN-NEXT: .LBB10_2: ; %end +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mov_b32_e32 v1, s9 +; GCN-NEXT: v_mov_b32_e32 v2, s10 +; GCN-NEXT: v_mov_b32_e32 v3, s11 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v2i64_to_v2f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s11, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c +; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c +; VI-NEXT: s_mov_b32 s8, 0 +; VI-NEXT: s_mov_b32 s9, s8 +; VI-NEXT: s_mov_b32 s10, s8 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s11, 0 +; VI-NEXT: s_mov_b32 s11, s8 +; VI-NEXT: s_cbranch_scc1 .LBB10_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: s_mov_b32 s4, s2 +; VI-NEXT: s_mov_b32 s5, s3 +; VI-NEXT: s_mov_b64 s[10:11], s[6:7] +; VI-NEXT: s_mov_b64 s[8:9], s[4:5] +; VI-NEXT: .LBB10_2: ; %end +; VI-NEXT: v_mov_b32_e32 v0, s8 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v1, s9 +; VI-NEXT: v_mov_b32_e32 v2, s10 +; VI-NEXT: v_mov_b32_e32 v3, s11 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v2i64_to_v2f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s11, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c +; GFX9-NEXT: s_mov_b32 s8, 0 +; GFX9-NEXT: s_mov_b32 s9, s8 +; GFX9-NEXT: s_mov_b32 s10, s8 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s11, 0 +; GFX9-NEXT: s_mov_b32 s11, s8 +; GFX9-NEXT: s_cbranch_scc1 .LBB10_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: s_mov_b32 s4, s2 +; GFX9-NEXT: s_mov_b32 s5, s3 +; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7] +; GFX9-NEXT: s_mov_b64 s[8:9], s[4:5] +; GFX9-NEXT: .LBB10_2: ; %end +; GFX9-NEXT: v_mov_b32_e32 v0, s8 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s9 +; GFX9-NEXT: v_mov_b32_e32 v2, s10 +; GFX9-NEXT: v_mov_b32_e32 v3, s11 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v2i64_to_v2f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: s_load_b32 s11, s[4:5], 0x24 +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c +; GFX11-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c +; GFX11-NEXT: s_mov_b32 s8, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_mov_b32 s9, s8 +; GFX11-NEXT: s_mov_b32 s10, s8 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s11, 0 +; GFX11-NEXT: s_mov_b32 s11, s8 +; GFX11-NEXT: s_cbranch_scc1 .LBB10_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_mov_b32 s5, s3 +; GFX11-NEXT: s_mov_b64 s[10:11], s[6:7] +; GFX11-NEXT: s_mov_b64 s[8:9], s[4:5] +; GFX11-NEXT: .LBB10_2: ; %end +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s11 +; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s9 +; GFX11-NEXT: v_mov_b32_e32 v2, s10 +; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1] +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x i64> %value to <2 x double> + br label %end + +end: + %phi = phi <2 x double> [zeroinitializer, %entry], [%cast, %if] + store <2 x double> %phi, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @bitcast_v2f64_to_v2i64(i32 %cond, ptr addrspace(1) %out, <2 x double> %value) { +; GCN-LABEL: bitcast_v2f64_to_v2i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s9, s[4:5], 0x9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb +; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xf +; GCN-NEXT: s_mov_b32 s8, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s9, 0 +; GCN-NEXT: s_mov_b32 s9, s8 +; GCN-NEXT: s_mov_b32 s10, s8 +; GCN-NEXT: s_mov_b32 s11, s8 +; GCN-NEXT: s_cbranch_scc1 .LBB11_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: s_mov_b32 s4, s2 +; GCN-NEXT: s_mov_b32 s5, s3 +; GCN-NEXT: s_mov_b64 s[10:11], s[6:7] +; GCN-NEXT: s_mov_b64 s[8:9], s[4:5] +; GCN-NEXT: .LBB11_2: ; %end +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mov_b32_e32 v1, s9 +; GCN-NEXT: v_mov_b32_e32 v2, s10 +; GCN-NEXT: v_mov_b32_e32 v3, s11 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v2f64_to_v2i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s11, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c +; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c +; VI-NEXT: s_mov_b32 s8, 0 +; VI-NEXT: s_mov_b32 s9, s8 +; VI-NEXT: s_mov_b32 s10, s8 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s11, 0 +; VI-NEXT: s_mov_b32 s11, s8 +; VI-NEXT: s_cbranch_scc1 .LBB11_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: s_mov_b32 s4, s2 +; VI-NEXT: s_mov_b32 s5, s3 +; VI-NEXT: s_mov_b64 s[10:11], s[6:7] +; VI-NEXT: s_mov_b64 s[8:9], s[4:5] +; VI-NEXT: .LBB11_2: ; %end +; VI-NEXT: v_mov_b32_e32 v0, s8 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v1, s9 +; VI-NEXT: v_mov_b32_e32 v2, s10 +; VI-NEXT: v_mov_b32_e32 v3, s11 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v2f64_to_v2i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s11, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c +; GFX9-NEXT: s_mov_b32 s8, 0 +; GFX9-NEXT: s_mov_b32 s9, s8 +; GFX9-NEXT: s_mov_b32 s10, s8 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s11, 0 +; GFX9-NEXT: s_mov_b32 s11, s8 +; GFX9-NEXT: s_cbranch_scc1 .LBB11_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: s_mov_b32 s4, s2 +; GFX9-NEXT: s_mov_b32 s5, s3 +; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7] +; GFX9-NEXT: s_mov_b64 s[8:9], s[4:5] +; GFX9-NEXT: .LBB11_2: ; %end +; GFX9-NEXT: v_mov_b32_e32 v0, s8 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s9 +; GFX9-NEXT: v_mov_b32_e32 v2, s10 +; GFX9-NEXT: v_mov_b32_e32 v3, s11 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v2f64_to_v2i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: s_load_b32 s11, s[4:5], 0x24 +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c +; GFX11-NEXT: s_load_b64 s[6:7], s[4:5], 0x3c +; GFX11-NEXT: s_mov_b32 s8, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_mov_b32 s9, s8 +; GFX11-NEXT: s_mov_b32 s10, s8 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s11, 0 +; GFX11-NEXT: s_mov_b32 s11, s8 +; GFX11-NEXT: s_cbranch_scc1 .LBB11_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_mov_b32 s5, s3 +; GFX11-NEXT: s_mov_b64 s[10:11], s[6:7] +; GFX11-NEXT: s_mov_b64 s[8:9], s[4:5] +; GFX11-NEXT: .LBB11_2: ; %end +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s11 +; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s9 +; GFX11-NEXT: v_mov_b32_e32 v2, s10 +; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1] +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x double> %value to <2 x i64> + br label %end + +end: + %phi = phi <2 x i64> [zeroinitializer, %entry], [%cast, %if] + store <2 x i64> %phi, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v4i16_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v4i16_to_f64: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s6, s5, 0xffff0000 +; GCN-NEXT: s_add_i32 s5, s5, 4 +; GCN-NEXT: s_and_b32 s7, s4, 0xffff0000 +; GCN-NEXT: s_add_i32 s4, s4, 4 +; GCN-NEXT: s_and_b32 s5, s5, 0xffff +; GCN-NEXT: s_and_b32 s4, s4, 0xffff +; GCN-NEXT: s_or_b32 s5, s6, s5 +; GCN-NEXT: s_or_b32 s4, s7, s4 +; GCN-NEXT: s_add_i32 s5, s5, 0x40000 +; GCN-NEXT: s_add_i32 s4, s4, 0x40000 +; GCN-NEXT: v_add_f64 v[0:1], s[4:5], 1.0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v4i16_to_f64: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_and_b32 s4, s3, 0xffff0000 +; VI-NEXT: s_add_i32 s3, s3, 4 +; VI-NEXT: s_and_b32 s5, s2, 0xffff0000 +; VI-NEXT: s_add_i32 s2, s2, 4 +; VI-NEXT: s_and_b32 s3, s3, 0xffff +; VI-NEXT: s_and_b32 s2, s2, 0xffff +; VI-NEXT: s_or_b32 s3, s4, s3 +; VI-NEXT: s_or_b32 s2, s5, s2 +; VI-NEXT: s_add_i32 s3, s3, 0x40000 +; VI-NEXT: s_add_i32 s2, s2, 0x40000 +; VI-NEXT: v_add_f64 v[0:1], s[2:3], 1.0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v4i16_to_f64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_pk_add_u16 v1, s5, 4 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v0, s4, 4 op_sel_hi:[1,0] +; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v4i16_to_f64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_pk_add_u16 v1, s3, 4 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v0, s2, 4 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <4 x i16>, ptr addrspace(1) %in, align 4 + %add.v4i16 = add <4 x i16> %load, + %bc = bitcast <4 x i16> %add.v4i16 to double + %fadd.bitcast = fadd double %bc, 1.0 + store double %fadd.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v4f16_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v4f16_to_f64: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v0, s4 +; GCN-NEXT: s_lshr_b32 s4, s4, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, s5 +; GCN-NEXT: s_lshr_b32 s5, s5, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, s4 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, s5 +; GCN-NEXT: v_add_f32_e32 v1, 4.0, v1 +; GCN-NEXT: v_add_f32_e32 v0, 4.0, v0 +; GCN-NEXT: v_add_f32_e32 v3, 4.0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_add_f32_e32 v2, 4.0, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-NEXT: v_or_b32_e32 v0, v0, v2 +; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v4f16_to_f64: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v0, 0x4400 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_lshr_b32 s4, s3, 16 +; VI-NEXT: v_add_f16_e64 v1, s3, 4.0 +; VI-NEXT: s_lshr_b32 s3, s2, 16 +; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_mov_b32_e32 v4, s3 +; VI-NEXT: v_add_f16_e64 v2, s2, 4.0 +; VI-NEXT: v_add_f16_sdwa v3, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_add_f16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v1, v1, v3 +; VI-NEXT: v_or_b32_e32 v0, v2, v0 +; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v4f16_to_f64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v1, s5, 4.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v0, s4, 4.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v4f16_to_f64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v1, s3, 4.0 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_f16 v0, s2, 4.0 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <4 x half>, ptr addrspace(1) %in, align 4 + %add.v4half = fadd <4 x half> %load, + %bc = bitcast <4 x half> %add.v4half to double + %fadd.bitcast = fadd double %bc, 1.0 + store double %fadd.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @f64_to_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: f64_to_v4f16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_add_f64 v[0:1], s[4:5], 1.0 +; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GCN-NEXT: v_add_f32_e32 v1, 2.0, v1 +; GCN-NEXT: v_add_f32_e32 v0, 2.0, v0 +; GCN-NEXT: v_add_f32_e32 v2, 2.0, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_add_f32_e32 v3, 2.0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v1, v1, v2 +; GCN-NEXT: v_or_b32_e32 v0, v0, v3 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: f64_to_v4f16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v4, 0x4000 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_add_f64 v[0:1], s[2:3], 1.0 +; VI-NEXT: v_add_f16_sdwa v5, v1, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v1, 2.0, v1 +; VI-NEXT: v_add_f16_sdwa v4, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v0, 2.0, v0 +; VI-NEXT: v_or_b32_e32 v1, v1, v5 +; VI-NEXT: v_or_b32_e32 v0, v0, v4 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: f64_to_v4f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_add_f64 v[0:1], s[4:5], 1.0 +; GFX9-NEXT: v_pk_add_f16 v1, v1, 2.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v0, v0, 2.0 op_sel_hi:[1,0] +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: f64_to_v4f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_add_f64 v[0:1], s[2:3], 1.0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_pk_add_f16 v1, v1, 2.0 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_f16 v0, v0, 2.0 op_sel_hi:[1,0] +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load double, ptr addrspace(1) %in, align 4 + %fadd32 = fadd double %load, 1.0 + %bc = bitcast double %fadd32 to <4 x half> + %add.bitcast = fadd <4 x half> %bc, + store <4 x half> %add.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @f64_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: f64_to_v4i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_add_f64 v[0:1], s[4:5], 1.0 +; GCN-NEXT: v_readfirstlane_b32 s2, v0 +; GCN-NEXT: v_readfirstlane_b32 s4, v1 +; GCN-NEXT: s_and_b32 s5, s4, 0xffff0000 +; GCN-NEXT: s_add_i32 s4, s4, 2 +; GCN-NEXT: s_and_b32 s6, s2, 0xffff0000 +; GCN-NEXT: s_add_i32 s2, s2, 2 +; GCN-NEXT: s_and_b32 s4, s4, 0xffff +; GCN-NEXT: s_and_b32 s2, s2, 0xffff +; GCN-NEXT: s_or_b32 s4, s5, s4 +; GCN-NEXT: s_or_b32 s2, s6, s2 +; GCN-NEXT: s_add_i32 s4, s4, 0x20000 +; GCN-NEXT: s_add_i32 s5, s2, 0x20000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s5 +; GCN-NEXT: v_mov_b32_e32 v1, s4 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: f64_to_v4i16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_add_f64 v[0:1], s[2:3], 1.0 +; VI-NEXT: v_readfirstlane_b32 s0, v1 +; VI-NEXT: v_readfirstlane_b32 s1, v0 +; VI-NEXT: s_and_b32 s2, s0, 0xffff0000 +; VI-NEXT: s_add_i32 s0, s0, 2 +; VI-NEXT: s_and_b32 s3, s1, 0xffff0000 +; VI-NEXT: s_add_i32 s1, s1, 2 +; VI-NEXT: s_and_b32 s0, s0, 0xffff +; VI-NEXT: s_and_b32 s1, s1, 0xffff +; VI-NEXT: s_or_b32 s0, s2, s0 +; VI-NEXT: s_or_b32 s1, s3, s1 +; VI-NEXT: s_add_i32 s0, s0, 0x20000 +; VI-NEXT: s_add_i32 s1, s1, 0x20000 +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: f64_to_v4i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_add_f64 v[0:1], s[4:5], 1.0 +; GFX9-NEXT: v_pk_add_u16 v1, v1, 2 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v0, v0, 2 op_sel_hi:[1,0] +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: f64_to_v4i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_add_f64 v[0:1], s[2:3], 1.0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_pk_add_u16 v1, v1, 2 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v0, v0, 2 op_sel_hi:[1,0] +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load double, ptr addrspace(1) %in, align 4 + %fadd32 = fadd double %load, 1.0 + %bc = bitcast double %fadd32 to <4 x i16> + %add.bitcast = add <4 x i16> %bc, + store <4 x i16> %add.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v4i16_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v4i16_to_i64: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s2, s5, 0xffff0000 +; GCN-NEXT: s_add_i32 s5, s5, 4 +; GCN-NEXT: s_and_b32 s6, s4, 0xffff0000 +; GCN-NEXT: s_add_i32 s4, s4, 4 +; GCN-NEXT: s_and_b32 s5, s5, 0xffff +; GCN-NEXT: s_and_b32 s4, s4, 0xffff +; GCN-NEXT: s_or_b32 s2, s2, s5 +; GCN-NEXT: s_or_b32 s4, s6, s4 +; GCN-NEXT: s_add_i32 s2, s2, 0x40000 +; GCN-NEXT: s_add_i32 s4, s4, 0x40000 +; GCN-NEXT: s_add_u32 s4, s4, 1 +; GCN-NEXT: s_addc_u32 s5, s2, 0 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v4i16_to_i64: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_and_b32 s0, s3, 0xffff0000 +; VI-NEXT: s_add_i32 s1, s3, 4 +; VI-NEXT: s_and_b32 s3, s2, 0xffff0000 +; VI-NEXT: s_add_i32 s2, s2, 4 +; VI-NEXT: s_and_b32 s1, s1, 0xffff +; VI-NEXT: s_and_b32 s2, s2, 0xffff +; VI-NEXT: s_or_b32 s0, s0, s1 +; VI-NEXT: s_or_b32 s1, s3, s2 +; VI-NEXT: s_add_i32 s2, s0, 0x40000 +; VI-NEXT: s_add_i32 s1, s1, 0x40000 +; VI-NEXT: s_add_u32 s0, s1, 1 +; VI-NEXT: s_addc_u32 s1, s2, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v4i16_to_i64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_pk_add_u16 v0, s4, 4 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v1, s5, 4 op_sel_hi:[1,0] +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v4i16_to_i64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_pk_add_u16 v0, s2, 4 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v1, s3, 4 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 1 +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <4 x i16>, ptr addrspace(1) %in, align 4 + %add.v4i16 = add <4 x i16> %load, + %bc = bitcast <4 x i16> %add.v4i16 to i64 + %add.bitcast = add i64 %bc, 1 + store i64 %add.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v4f16_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v4f16_to_i64: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v0, s4 +; GCN-NEXT: s_lshr_b32 s4, s4, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, s5 +; GCN-NEXT: s_lshr_b32 s5, s5, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, s4 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, s5 +; GCN-NEXT: v_add_f32_e32 v1, 4.0, v1 +; GCN-NEXT: v_add_f32_e32 v0, 4.0, v0 +; GCN-NEXT: v_add_f32_e32 v3, 4.0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_add_f32_e32 v2, 4.0, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-NEXT: v_or_b32_e32 v0, v0, v2 +; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v0 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v4f16_to_i64: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v2, 0x4400 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_lshr_b32 s0, s3, 16 +; VI-NEXT: s_lshr_b32 s1, s2, 16 +; VI-NEXT: v_mov_b32_e32 v5, s0 +; VI-NEXT: v_mov_b32_e32 v6, s1 +; VI-NEXT: v_add_f16_e64 v4, s2, 4.0 +; VI-NEXT: v_add_f16_sdwa v5, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_add_f16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_add_f16_e64 v3, s3, 4.0 +; VI-NEXT: v_or_b32_e32 v2, v4, v2 +; VI-NEXT: v_or_b32_e32 v3, v3, v5 +; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v2 +; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v4f16_to_i64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v0, s4, 4.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v1, s5, 4.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v4f16_to_i64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v0, s2, 4.0 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_f16 v1, s3, 4.0 op_sel_hi:[1,0] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 1 +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <4 x half>, ptr addrspace(1) %in, align 4 + %add.v4half = fadd <4 x half> %load, + %bc = bitcast <4 x half> %add.v4half to i64 + %add.bitcast = add i64 %bc, 1 + store i64 %add.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @bitcast_i64_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; GCN-LABEL: bitcast_i64_to_v4i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_u32 s2, s4, 4 +; GCN-NEXT: s_addc_u32 s4, s5, 0 +; GCN-NEXT: s_and_b32 s5, s2, 0xffff0000 +; GCN-NEXT: s_add_i32 s2, s2, 1 +; GCN-NEXT: s_and_b32 s6, s4, 0xffff0000 +; GCN-NEXT: s_add_i32 s4, s4, 3 +; GCN-NEXT: s_and_b32 s2, s2, 0xffff +; GCN-NEXT: s_and_b32 s4, s4, 0xffff +; GCN-NEXT: s_or_b32 s2, s5, s2 +; GCN-NEXT: s_or_b32 s4, s6, s4 +; GCN-NEXT: s_add_i32 s5, s2, 0x20000 +; GCN-NEXT: s_add_i32 s4, s4, 0x40000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s5 +; GCN-NEXT: v_mov_b32_e32 v1, s4 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_i64_to_v4i16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_u32 s0, s2, 4 +; VI-NEXT: s_addc_u32 s1, s3, 0 +; VI-NEXT: s_and_b32 s2, s0, 0xffff0000 +; VI-NEXT: s_add_i32 s0, s0, 1 +; VI-NEXT: s_and_b32 s3, s1, 0xffff0000 +; VI-NEXT: s_add_i32 s1, s1, 3 +; VI-NEXT: s_and_b32 s0, s0, 0xffff +; VI-NEXT: s_and_b32 s1, s1, 0xffff +; VI-NEXT: s_or_b32 s0, s2, s0 +; VI-NEXT: s_or_b32 s1, s3, s1 +; VI-NEXT: s_add_i32 s0, s0, 0x20000 +; VI-NEXT: s_add_i32 s1, s1, 0x40000 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_i64_to_v4i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x40003 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_add_u32 s2, s2, 4 +; GFX9-NEXT: s_addc_u32 s3, s3, 0 +; GFX9-NEXT: v_pk_add_u16 v1, s3, v0 +; GFX9-NEXT: v_pk_sub_u16 v0, s2, -2 op_sel:[0,1] op_sel_hi:[1,0] +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_i64_to_v4i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_add_u32 s2, s2, 4 +; GFX11-NEXT: s_addc_u32 s3, s3, 0 +; GFX11-NEXT: v_pk_sub_u16 v0, s2, -2 op_sel:[0,1] op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v1, 0x40003, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %val = load i64, ptr addrspace(1) %in, align 8 + %add = add i64 %val, 4 + %bc = bitcast i64 %add to <4 x i16> + %add.v4i16 = add <4 x i16> %bc, + store <4 x i16> %add.v4i16, ptr addrspace(1) %out, align 8 + ret void +} + + +define amdgpu_kernel void @bitcast_i64_to_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; GCN-LABEL: bitcast_i64_to_v4f16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_u32 s4, s4, 4 +; GCN-NEXT: s_addc_u32 s5, s5, 0 +; GCN-NEXT: s_lshr_b32 s6, s4, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, s4 +; GCN-NEXT: s_lshr_b32 s4, s5, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, s6 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, s5 +; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, s4 +; GCN-NEXT: v_add_f32_e32 v2, 4.0, v2 +; GCN-NEXT: v_add_f32_e32 v1, 2.0, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_add_f32_e32 v3, 0x41000000, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v3 +; GCN-NEXT: v_or_b32_e32 v1, v2, v1 +; GCN-NEXT: v_or_b32_e32 v0, v0, v4 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_i64_to_v4f16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v2, 0x4800 +; VI-NEXT: v_mov_b32_e32 v3, 0x4000 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_u32 s0, s2, 4 +; VI-NEXT: s_addc_u32 s1, s3, 0 +; VI-NEXT: s_lshr_b32 s3, s1, 16 +; VI-NEXT: s_lshr_b32 s2, s0, 16 +; VI-NEXT: v_mov_b32_e32 v6, s3 +; VI-NEXT: v_add_f16_e64 v4, s1, 4.0 +; VI-NEXT: v_mov_b32_e32 v5, s2 +; VI-NEXT: v_add_f16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_add_f16_sdwa v5, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v3, v4, v2 +; VI-NEXT: v_add_f16_e64 v2, s0, 1.0 +; VI-NEXT: v_or_b32_e32 v2, v2, v5 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_i64_to_v4f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x48004400 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x40003c00 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_add_u32 s2, s2, 4 +; GFX9-NEXT: s_addc_u32 s3, s3, 0 +; GFX9-NEXT: v_pk_add_f16 v1, s3, v0 +; GFX9-NEXT: v_pk_add_f16 v0, s2, v3 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_i64_to_v4f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_add_u32 s2, s2, 4 +; GFX11-NEXT: s_addc_u32 s3, s3, 0 +; GFX11-NEXT: v_pk_add_f16 v0, 0x40003c00, s2 +; GFX11-NEXT: v_pk_add_f16 v1, 0x48004400, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %val = load i64, ptr addrspace(1) %in, align 8 + %add = add i64 %val, 4 + %bc = bitcast i64 %add to <4 x half> + %add.v4i16 = fadd <4 x half> %bc, + store <4 x half> %add.v4i16, ptr addrspace(1) %out, align 8 + ret void +} + + +define amdgpu_kernel void @v4i16_to_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v4i16_to_v2f32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s6, s4, 0xffff0000 +; GCN-NEXT: s_add_i32 s4, s4, 4 +; GCN-NEXT: s_and_b32 s7, s5, 0xffff0000 +; GCN-NEXT: s_add_i32 s5, s5, 4 +; GCN-NEXT: s_and_b32 s4, s4, 0xffff +; GCN-NEXT: s_and_b32 s5, s5, 0xffff +; GCN-NEXT: s_or_b32 s4, s6, s4 +; GCN-NEXT: s_or_b32 s5, s7, s5 +; GCN-NEXT: s_add_i32 s4, s4, 0x40000 +; GCN-NEXT: s_add_i32 s5, s5, 0x40000 +; GCN-NEXT: v_add_f32_e64 v1, s5, 1.0 +; GCN-NEXT: v_add_f32_e64 v0, s4, 1.0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v4i16_to_v2f32: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_and_b32 s0, s2, 0xffff0000 +; VI-NEXT: s_add_i32 s1, s2, 4 +; VI-NEXT: s_and_b32 s2, s3, 0xffff0000 +; VI-NEXT: s_add_i32 s3, s3, 4 +; VI-NEXT: s_and_b32 s1, s1, 0xffff +; VI-NEXT: s_and_b32 s3, s3, 0xffff +; VI-NEXT: s_or_b32 s0, s0, s1 +; VI-NEXT: s_or_b32 s1, s2, s3 +; VI-NEXT: s_add_i32 s0, s0, 0x40000 +; VI-NEXT: s_add_i32 s1, s1, 0x40000 +; VI-NEXT: v_add_f32_e64 v3, s1, 1.0 +; VI-NEXT: v_add_f32_e64 v2, s0, 1.0 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v4i16_to_v2f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_pk_add_u16 v0, s4, 4 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v1, s5, 4 op_sel_hi:[1,0] +; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v4i16_to_v2f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_pk_add_u16 v0, s3, 4 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v2, s2, 4 op_sel_hi:[1,0] +; GFX11-NEXT: v_mov_b32_e32 v3, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v0 :: v_dual_add_f32 v0, 1.0, v2 +; GFX11-NEXT: global_store_b64 v3, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <4 x i16>, ptr addrspace(1) %in, align 4 + %add.v4i16 = add <4 x i16> %load, + %bc = bitcast <4 x i16> %add.v4i16 to <2 x float> + %fadd.bitcast = fadd <2 x float> %bc, + store <2 x float> %fadd.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v4f16_to_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v4f16_to_v2f32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v0, s5 +; GCN-NEXT: s_lshr_b32 s5, s5, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, s4 +; GCN-NEXT: s_lshr_b32 s4, s4, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, s5 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, s4 +; GCN-NEXT: v_add_f32_e32 v1, 4.0, v1 +; GCN-NEXT: v_add_f32_e32 v0, 4.0, v0 +; GCN-NEXT: v_add_f32_e32 v3, 4.0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_add_f32_e32 v2, 4.0, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_or_b32_e32 v3, v1, v3 +; GCN-NEXT: v_or_b32_e32 v0, v0, v2 +; GCN-NEXT: v_add_f32_e32 v1, 1.0, v0 +; GCN-NEXT: v_add_f32_e32 v0, 1.0, v3 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v4f16_to_v2f32: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v2, 0x4400 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_lshr_b32 s0, s2, 16 +; VI-NEXT: s_lshr_b32 s1, s3, 16 +; VI-NEXT: v_mov_b32_e32 v5, s0 +; VI-NEXT: v_mov_b32_e32 v6, s1 +; VI-NEXT: v_add_f16_e64 v3, s2, 4.0 +; VI-NEXT: v_add_f16_e64 v4, s3, 4.0 +; VI-NEXT: v_add_f16_sdwa v5, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_add_f16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v5, v3, v5 +; VI-NEXT: v_or_b32_e32 v2, v4, v2 +; VI-NEXT: v_add_f32_e32 v3, 1.0, v2 +; VI-NEXT: v_add_f32_e32 v2, 1.0, v5 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v4f16_to_v2f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v0, s4, 4.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v1, s5, 4.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v4f16_to_v2f32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v0, s3, 4.0 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_f16 v2, s2, 4.0 op_sel_hi:[1,0] +; GFX11-NEXT: v_mov_b32_e32 v3, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v0 :: v_dual_add_f32 v0, 1.0, v2 +; GFX11-NEXT: global_store_b64 v3, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <4 x half>, ptr addrspace(1) %in, align 4 + %add.v4half = fadd <4 x half> %load, + %bc = bitcast <4 x half> %add.v4half to <2 x float> + %fadd.bitcast = fadd <2 x float> %bc, + store <2 x float> %fadd.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v2f32_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v2f32_to_v4i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_add_f32_e64 v0, s4, 2.0 +; GCN-NEXT: v_add_f32_e64 v1, s5, 4.0 +; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v1 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v1 +; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v0 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GCN-NEXT: v_or_b32_e32 v1, v2, v1 +; GCN-NEXT: v_or_b32_e32 v0, v3, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 0x40000, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x20000, v0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v2f32_to_v4i16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_add_f32_e64 v2, s2, 2.0 +; VI-NEXT: v_add_f32_e64 v3, s3, 4.0 +; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v3 +; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3 +; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v2 +; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v2 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; VI-NEXT: v_or_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x40000, v3 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x20000, v2 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v2f32_to_v4i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_mov_b32 s2, 0x40003 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_add_f32_e64 v0, s4, 2.0 +; GFX9-NEXT: v_add_f32_e64 v1, s5, 4.0 +; GFX9-NEXT: v_pk_add_u16 v1, v1, s2 +; GFX9-NEXT: v_pk_sub_u16 v0, v0, -2 op_sel:[0,1] op_sel_hi:[1,0] +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v2f32_to_v4i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v3, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_add_f32_e64 v0, s3, 4.0 +; GFX11-NEXT: v_add_f32_e64 v2, s2, 2.0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_pk_add_u16 v1, 0x40003, v0 +; GFX11-NEXT: v_pk_sub_u16 v0, v2, -2 op_sel:[0,1] op_sel_hi:[1,0] +; GFX11-NEXT: global_store_b64 v3, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <2 x float>, ptr addrspace(1) %in, align 4 + %add.v2f32 = fadd <2 x float> %load, + %bc = bitcast <2 x float> %add.v2f32 to <4 x i16> + %add.bitcast = add <4 x i16> %bc, + store <4 x i16> %add.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v2f32_to_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v2f32_to_v4f16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_add_f32_e64 v0, s5, 4.0 +; GCN-NEXT: v_add_f32_e64 v1, s4, 2.0 +; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GCN-NEXT: v_add_f32_e32 v0, 4.0, v0 +; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1 +; GCN-NEXT: v_add_f32_e32 v2, 0x41000000, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_add_f32_e32 v3, 2.0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_or_b32_e32 v1, v0, v1 +; GCN-NEXT: v_or_b32_e32 v0, v4, v2 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v2f32_to_v4f16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v2, 0x4800 +; VI-NEXT: v_mov_b32_e32 v3, 0x4000 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_add_f32_e64 v4, s2, 2.0 +; VI-NEXT: v_add_f32_e64 v5, s3, 4.0 +; VI-NEXT: v_add_f16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v5, 4.0, v5 +; VI-NEXT: v_add_f16_sdwa v6, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v4, 1.0, v4 +; VI-NEXT: v_or_b32_e32 v3, v5, v2 +; VI-NEXT: v_or_b32_e32 v2, v4, v6 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v2f32_to_v4f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_mov_b32 s2, 0x48004400 +; GFX9-NEXT: s_mov_b32 s3, 0x40003c00 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_add_f32_e64 v0, s4, 2.0 +; GFX9-NEXT: v_add_f32_e64 v1, s5, 4.0 +; GFX9-NEXT: v_pk_add_f16 v1, v1, s2 +; GFX9-NEXT: v_pk_add_f16 v0, v0, s3 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v2f32_to_v4f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v3, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_add_f32_e64 v0, s3, 4.0 +; GFX11-NEXT: v_add_f32_e64 v2, s2, 2.0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_pk_add_f16 v1, 0x48004400, v0 +; GFX11-NEXT: v_pk_add_f16 v0, 0x40003c00, v2 +; GFX11-NEXT: global_store_b64 v3, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <2 x float>, ptr addrspace(1) %in, align 4 + %add.v2f32 = fadd <2 x float> %load, + %bc = bitcast <2 x float> %add.v2f32 to <4 x half> + %add.bitcast = fadd <4 x half> %bc, + store <4 x half> %add.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v4i16_to_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v4i16_to_v2i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s2, s4, 0xffff0000 +; GCN-NEXT: s_add_i32 s4, s4, 4 +; GCN-NEXT: s_and_b32 s6, s5, 0xffff0000 +; GCN-NEXT: s_add_i32 s5, s5, 4 +; GCN-NEXT: s_and_b32 s4, s4, 0xffff +; GCN-NEXT: s_and_b32 s5, s5, 0xffff +; GCN-NEXT: s_or_b32 s2, s2, s4 +; GCN-NEXT: s_or_b32 s4, s6, s5 +; GCN-NEXT: s_add_i32 s4, s4, 0x40001 +; GCN-NEXT: s_add_i32 s5, s2, 0x40001 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s5 +; GCN-NEXT: v_mov_b32_e32 v1, s4 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v4i16_to_v2i32: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_and_b32 s0, s2, 0xffff0000 +; VI-NEXT: s_add_i32 s1, s2, 4 +; VI-NEXT: s_and_b32 s2, s3, 0xffff0000 +; VI-NEXT: s_add_i32 s3, s3, 4 +; VI-NEXT: s_and_b32 s1, s1, 0xffff +; VI-NEXT: s_and_b32 s3, s3, 0xffff +; VI-NEXT: s_or_b32 s0, s0, s1 +; VI-NEXT: s_or_b32 s1, s2, s3 +; VI-NEXT: s_add_i32 s1, s1, 0x40001 +; VI-NEXT: s_add_i32 s0, s0, 0x40001 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v4i16_to_v2i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_pk_add_u16 v0, s4, 4 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v1, s5, 4 op_sel_hi:[1,0] +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: v_add_u32_e32 v0, 1, v0 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v4i16_to_v2i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_pk_add_u16 v0, s3, 4 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v2, s2, 4 op_sel_hi:[1,0] +; GFX11-NEXT: v_mov_b32_e32 v3, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_add_nc_u32_e32 v1, 1, v0 +; GFX11-NEXT: v_add_nc_u32_e32 v0, 1, v2 +; GFX11-NEXT: global_store_b64 v3, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <4 x i16>, ptr addrspace(1) %in, align 4 + %add.v4i16 = add <4 x i16> %load, + %bc = bitcast <4 x i16> %add.v4i16 to <2 x i32> + %add.bitcast = add <2 x i32> %bc, + store <2 x i32> %add.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v4f16_to_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v4f16_to_v2i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v0, s5 +; GCN-NEXT: s_lshr_b32 s5, s5, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, s4 +; GCN-NEXT: s_lshr_b32 s4, s4, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, s5 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, s4 +; GCN-NEXT: v_add_f32_e32 v1, 4.0, v1 +; GCN-NEXT: v_add_f32_e32 v0, 4.0, v0 +; GCN-NEXT: v_add_f32_e32 v3, 4.0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_add_f32_e32 v2, 4.0, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_or_b32_e32 v3, v1, v3 +; GCN-NEXT: v_or_b32_e32 v0, v0, v2 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v3 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v4f16_to_v2i32: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v2, 0x4400 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_lshr_b32 s0, s2, 16 +; VI-NEXT: s_lshr_b32 s1, s3, 16 +; VI-NEXT: v_mov_b32_e32 v5, s0 +; VI-NEXT: v_mov_b32_e32 v6, s1 +; VI-NEXT: v_add_f16_e64 v3, s2, 4.0 +; VI-NEXT: v_add_f16_e64 v4, s3, 4.0 +; VI-NEXT: v_add_f16_sdwa v5, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_add_f16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v5, v3, v5 +; VI-NEXT: v_or_b32_e32 v2, v4, v2 +; VI-NEXT: v_add_u32_e32 v3, vcc, 1, v2 +; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v5 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v4f16_to_v2i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_pk_add_f16 v0, s4, 4.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v1, s5, 4.0 op_sel_hi:[1,0] +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: v_add_u32_e32 v0, 1, v0 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v4f16_to_v2i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_pk_add_f16 v0, s3, 4.0 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_f16 v2, s2, 4.0 op_sel_hi:[1,0] +; GFX11-NEXT: v_mov_b32_e32 v3, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_add_nc_u32_e32 v1, 1, v0 +; GFX11-NEXT: v_add_nc_u32_e32 v0, 1, v2 +; GFX11-NEXT: global_store_b64 v3, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <4 x half>, ptr addrspace(1) %in, align 4 + %add.v4half = fadd <4 x half> %load, + %bc = bitcast <4 x half> %add.v4half to <2 x i32> + %add.bitcast = add <2 x i32> %bc, + store <2 x i32> %add.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v2i32_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v2i32_to_v4i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s2, s4, 2 +; GCN-NEXT: s_add_i32 s6, s5, 4 +; GCN-NEXT: s_add_i32 s5, s5, 7 +; GCN-NEXT: s_add_i32 s4, s4, 3 +; GCN-NEXT: s_and_b32 s5, s5, 0xffff +; GCN-NEXT: s_and_b32 s6, s6, 0xffff0000 +; GCN-NEXT: s_and_b32 s4, s4, 0xffff +; GCN-NEXT: s_and_b32 s2, s2, 0xffff0000 +; GCN-NEXT: s_or_b32 s5, s6, s5 +; GCN-NEXT: s_or_b32 s2, s2, s4 +; GCN-NEXT: s_add_i32 s5, s5, 0x40000 +; GCN-NEXT: s_add_i32 s4, s2, 0x20000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v2i32_to_v4i16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_i32 s0, s2, 2 +; VI-NEXT: s_add_i32 s1, s3, 4 +; VI-NEXT: s_add_i32 s3, s3, 7 +; VI-NEXT: s_add_i32 s2, s2, 3 +; VI-NEXT: s_and_b32 s3, s3, 0xffff +; VI-NEXT: s_and_b32 s1, s1, 0xffff0000 +; VI-NEXT: s_and_b32 s2, s2, 0xffff +; VI-NEXT: s_and_b32 s0, s0, 0xffff0000 +; VI-NEXT: s_or_b32 s1, s1, s3 +; VI-NEXT: s_or_b32 s0, s0, s2 +; VI-NEXT: s_add_i32 s1, s1, 0x40000 +; VI-NEXT: s_add_i32 s0, s0, 0x20000 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v2i32_to_v4i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x40003 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_add_i32 s2, s4, 2 +; GFX9-NEXT: s_add_i32 s3, s5, 4 +; GFX9-NEXT: v_pk_add_u16 v1, s3, v0 +; GFX9-NEXT: v_pk_sub_u16 v0, s2, -2 op_sel:[0,1] op_sel_hi:[1,0] +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v2i32_to_v4i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_add_i32 s3, s3, 4 +; GFX11-NEXT: s_add_i32 s2, s2, 2 +; GFX11-NEXT: v_pk_add_u16 v1, 0x40003, s3 +; GFX11-NEXT: v_pk_sub_u16 v0, s2, -2 op_sel:[0,1] op_sel_hi:[1,0] +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <2 x i32>, ptr addrspace(1) %in, align 4 + %add.v2i32 = add <2 x i32> %load, + %bc = bitcast <2 x i32> %add.v2i32 to <4 x i16> + %add.bitcast = add <4 x i16> %bc, + store <4 x i16> %add.bitcast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @v2i32_to_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { +; GCN-LABEL: v2i32_to_v4f16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s5, s5, 4 +; GCN-NEXT: s_add_i32 s4, s4, 2 +; GCN-NEXT: s_lshr_b32 s6, s5, 16 +; GCN-NEXT: s_lshr_b32 s7, s4, 16 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, s4 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, s5 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, s7 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, s6 +; GCN-NEXT: v_add_f32_e32 v1, 4.0, v1 +; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_add_f32_e32 v3, 0x41000000, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_add_f32_e32 v2, 2.0, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-NEXT: v_or_b32_e32 v0, v0, v2 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: v2i32_to_v4f16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v2, 0x4800 +; VI-NEXT: v_mov_b32_e32 v4, 0x4000 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_i32 s1, s3, 4 +; VI-NEXT: s_add_i32 s0, s2, 2 +; VI-NEXT: s_lshr_b32 s2, s1, 16 +; VI-NEXT: v_add_f16_e64 v3, s1, 4.0 +; VI-NEXT: s_lshr_b32 s1, s0, 16 +; VI-NEXT: v_mov_b32_e32 v5, s2 +; VI-NEXT: v_mov_b32_e32 v6, s1 +; VI-NEXT: v_add_f16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v3, v3, v2 +; VI-NEXT: v_add_f16_sdwa v2, v6, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_add_f16_e64 v4, s0, 1.0 +; VI-NEXT: v_or_b32_e32 v2, v4, v2 +; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v2i32_to_v4f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x48004400 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x40003c00 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_add_i32 s2, s4, 2 +; GFX9-NEXT: s_add_i32 s3, s5, 4 +; GFX9-NEXT: v_pk_add_f16 v1, s3, v0 +; GFX9-NEXT: v_pk_add_f16 v0, s2, v3 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: v2i32_to_v4f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_add_i32 s3, s3, 4 +; GFX11-NEXT: s_add_i32 s2, s2, 2 +; GFX11-NEXT: v_pk_add_f16 v1, 0x48004400, s3 +; GFX11-NEXT: v_pk_add_f16 v0, 0x40003c00, s2 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm + %load = load <2 x i32>, ptr addrspace(1) %in, align 4 + %add.v2i32 = add <2 x i32> %load, + %bc = bitcast <2 x i32> %add.v2i32 to <4 x half> + %add.bitcast = fadd <4 x half> %bc, + store <4 x half> %add.bitcast, ptr addrspace(1) %out + ret void +} + +declare <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32>, i32, i32 immarg) + + + +define <2 x i64> @bitcast_v4f32_to_v2i64(<2 x i64> %arg) { +; GCN-LABEL: bitcast_v4f32_to_v2i64: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v5, v1 +; GCN-NEXT: v_mov_b32_e32 v4, v0 +; GCN-NEXT: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_or_b32_e32 v1, s9, v5 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[6:7], exec, s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB28_2 +; GCN-NEXT: ; %bb.1: +; GCN-NEXT: v_cvt_f32_u32_e32 v0, v4 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, v5 +; GCN-NEXT: s_mov_b32 s4, 0x4f800000 +; GCN-NEXT: s_mov_b32 s5, 0xcf800000 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v4 +; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v5, vcc +; GCN-NEXT: v_mov_b32_e32 v8, s9 +; GCN-NEXT: v_fma_f32 v0, v1, s4, v0 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_fma_f32 v0, v1, s5, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v1 +; GCN-NEXT: v_mul_lo_u32 v10, v7, v0 +; GCN-NEXT: v_mul_hi_u32 v11, v6, v0 +; GCN-NEXT: v_mul_lo_u32 v12, v6, v0 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v12 +; GCN-NEXT: v_mul_hi_u32 v13, v1, v12 +; GCN-NEXT: v_mul_lo_u32 v12, v1, v12 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 +; GCN-NEXT: v_mul_hi_u32 v10, v0, v9 +; GCN-NEXT: v_mul_lo_u32 v14, v0, v9 +; GCN-NEXT: v_mul_hi_u32 v15, v1, v9 +; GCN-NEXT: v_mul_lo_u32 v9, v1, v9 +; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v14 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc +; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v13, vcc +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v15, vcc +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v9 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v10, vcc +; GCN-NEXT: v_mul_hi_u32 v9, v6, v0 +; GCN-NEXT: v_mul_lo_u32 v7, v7, v0 +; GCN-NEXT: v_mul_lo_u32 v10, v6, v0 +; GCN-NEXT: v_mul_lo_u32 v6, v6, v1 +; GCN-NEXT: v_mul_hi_u32 v11, v1, v10 +; GCN-NEXT: v_mul_lo_u32 v12, v1, v10 +; GCN-NEXT: v_mul_hi_u32 v10, v0, v10 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; GCN-NEXT: v_mul_hi_u32 v7, v1, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v6 +; GCN-NEXT: v_mul_lo_u32 v13, v0, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v1, v6 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v13 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v12 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v6 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc +; GCN-NEXT: v_mul_hi_u32 v6, s8, v0 +; GCN-NEXT: v_mul_hi_u32 v7, s9, v0 +; GCN-NEXT: v_mul_lo_u32 v0, s9, v0 +; GCN-NEXT: v_mul_hi_u32 v9, s8, v1 +; GCN-NEXT: v_mul_lo_u32 v10, s8, v1 +; GCN-NEXT: v_mul_hi_u32 v11, s9, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s9, v1 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v6, v0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v9, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v11, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v6, vcc +; GCN-NEXT: v_mul_hi_u32 v6, v4, v0 +; GCN-NEXT: v_mul_lo_u32 v7, v5, v0 +; GCN-NEXT: v_mul_lo_u32 v9, v4, v0 +; GCN-NEXT: v_mul_lo_u32 v10, v4, v1 +; GCN-NEXT: v_add_i32_e32 v11, vcc, 2, v0 +; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v1, vcc +; GCN-NEXT: v_add_i32_e32 v13, vcc, 1, v0 +; GCN-NEXT: v_addc_u32_e32 v14, vcc, 0, v1, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; GCN-NEXT: v_sub_i32_e32 v7, vcc, s9, v6 +; GCN-NEXT: v_sub_i32_e32 v9, vcc, s8, v9 +; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v5, vcc +; GCN-NEXT: v_subb_u32_e32 v6, vcc, v8, v6, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v9, v4 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc +; GCN-NEXT: v_sub_i32_e32 v9, vcc, v9, v4 +; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v9, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v5 +; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v5 +; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v5 +; GCN-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v7, v5 +; GCN-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 +; GCN-NEXT: v_cndmask_b32_e32 v4, v14, v12, vcc +; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v4, v13, v11, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[4:5] +; GCN-NEXT: ; implicit-def: $vgpr4_vgpr5 +; GCN-NEXT: .LBB28_2: ; %Flow1 +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7] +; GCN-NEXT: s_cbranch_execz .LBB28_4 +; GCN-NEXT: ; %bb.3: +; GCN-NEXT: v_sub_i32_e32 v0, vcc, 0, v4 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, v4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_lo_u32 v0, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, v1, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s8, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v0, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v0 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v1 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, v1, v4 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v0 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: .LBB28_4: +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_or_b32_e32 v5, s11, v3 +; GCN-NEXT: v_mov_b32_e32 v4, 0 +; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; GCN-NEXT: ; implicit-def: $vgpr4_vgpr5 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[6:7], exec, s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB28_6 +; GCN-NEXT: ; %bb.5: +; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3 +; GCN-NEXT: s_mov_b32 s4, 0x4f800000 +; GCN-NEXT: s_mov_b32 s5, 0xcf800000 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2 +; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc +; GCN-NEXT: v_mov_b32_e32 v8, s11 +; GCN-NEXT: v_fma_f32 v4, v5, s4, v4 +; GCN-NEXT: v_rcp_f32_e32 v4, v4 +; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 +; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_fma_f32 v4, v5, s5, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v7, v4 +; GCN-NEXT: v_mul_hi_u32 v11, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v12, v6, v4 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9 +; GCN-NEXT: v_mul_hi_u32 v11, v4, v12 +; GCN-NEXT: v_mul_hi_u32 v13, v5, v12 +; GCN-NEXT: v_mul_lo_u32 v12, v5, v12 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 +; GCN-NEXT: v_mul_hi_u32 v10, v4, v9 +; GCN-NEXT: v_mul_lo_u32 v14, v4, v9 +; GCN-NEXT: v_mul_hi_u32 v15, v5, v9 +; GCN-NEXT: v_mul_lo_u32 v9, v5, v9 +; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v14 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc +; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v13, vcc +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v15, vcc +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v10, vcc +; GCN-NEXT: v_mul_hi_u32 v9, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v7, v7, v4 +; GCN-NEXT: v_mul_lo_u32 v10, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v6, v6, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v5, v10 +; GCN-NEXT: v_mul_lo_u32 v12, v5, v10 +; GCN-NEXT: v_mul_hi_u32 v10, v4, v10 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; GCN-NEXT: v_mul_hi_u32 v7, v5, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v6 +; GCN-NEXT: v_mul_lo_u32 v13, v4, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v5, v6 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v13 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v12 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc +; GCN-NEXT: v_mul_hi_u32 v6, s10, v4 +; GCN-NEXT: v_mul_hi_u32 v7, s11, v4 +; GCN-NEXT: v_mul_lo_u32 v4, s11, v4 +; GCN-NEXT: v_mul_hi_u32 v9, s10, v5 +; GCN-NEXT: v_mul_lo_u32 v10, s10, v5 +; GCN-NEXT: v_mul_hi_u32 v11, s11, v5 +; GCN-NEXT: v_mul_lo_u32 v5, s11, v5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v11, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc +; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v7, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v9, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 +; GCN-NEXT: v_add_i32_e32 v11, vcc, 2, v4 +; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v13, vcc, 1, v4 +; GCN-NEXT: v_addc_u32_e32 v14, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; GCN-NEXT: v_sub_i32_e32 v7, vcc, s11, v6 +; GCN-NEXT: v_sub_i32_e32 v9, vcc, s10, v9 +; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v3, vcc +; GCN-NEXT: v_subb_u32_e32 v6, vcc, v8, v6, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v9, v2 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc +; GCN-NEXT: v_sub_i32_e32 v9, vcc, v9, v2 +; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v9, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3 +; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3 +; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v3 +; GCN-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v7, v3 +; GCN-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_cndmask_b32_e32 v2, v14, v12, vcc +; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v2, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v2, v13, v11, vcc +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v2, s[4:5] +; GCN-NEXT: ; implicit-def: $vgpr2_vgpr3 +; GCN-NEXT: .LBB28_6: ; %Flow +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7] +; GCN-NEXT: s_cbranch_execz .LBB28_8 +; GCN-NEXT: ; %bb.7: +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v4 +; GCN-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GCN-NEXT: v_mul_lo_u32 v3, v3, v4 +; GCN-NEXT: v_mul_hi_u32 v3, v4, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_mul_hi_u32 v3, s10, v3 +; GCN-NEXT: v_mul_lo_u32 v4, v3, v2 +; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v3 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s10, v4 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, v4, v2 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2 +; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v3 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2 +; GCN-NEXT: v_cndmask_b32_e32 v4, v3, v5, vcc +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: .LBB28_8: +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mov_b32_e32 v2, v4 +; GCN-NEXT: v_mov_b32_e32 v3, v5 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: bitcast_v4f32_to_v2i64: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x0 +; VI-NEXT: v_mov_b32_e32 v5, v1 +; VI-NEXT: v_mov_b32_e32 v4, v0 +; VI-NEXT: v_mov_b32_e32 v0, 0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_or_b32_e32 v1, s9, v5 +; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; VI-NEXT: ; implicit-def: $vgpr0_vgpr1 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_xor_b64 s[6:7], exec, s[4:5] +; VI-NEXT: s_cbranch_execz .LBB28_2 +; VI-NEXT: ; %bb.1: +; VI-NEXT: v_cvt_f32_u32_e32 v0, v4 +; VI-NEXT: v_cvt_f32_u32_e32 v1, v5 +; VI-NEXT: v_sub_u32_e32 v10, vcc, 0, v4 +; VI-NEXT: v_subb_u32_e32 v11, vcc, 0, v5, vcc +; VI-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 +; VI-NEXT: v_rcp_f32_e32 v0, v0 +; VI-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; VI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; VI-NEXT: v_trunc_f32_e32 v1, v1 +; VI-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 +; VI-NEXT: v_cvt_u32_f32_e32 v8, v1 +; VI-NEXT: v_cvt_u32_f32_e32 v9, v0 +; VI-NEXT: v_mul_lo_u32 v6, v10, v8 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v9, 0 +; VI-NEXT: v_mul_lo_u32 v7, v11, v9 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v6 +; VI-NEXT: v_add_u32_e32 v13, vcc, v1, v7 +; VI-NEXT: v_mul_hi_u32 v12, v9, v0 +; VI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v9, v13, 0 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v0, 0 +; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v6 +; VI-NEXT: v_addc_u32_e32 v14, vcc, 0, v7, vcc +; VI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v13, 0 +; VI-NEXT: v_add_u32_e32 v0, vcc, v12, v0 +; VI-NEXT: v_addc_u32_e32 v0, vcc, v14, v1, vcc +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; VI-NEXT: v_add_u32_e32 v12, vcc, v9, v0 +; VI-NEXT: v_addc_u32_e32 v13, vcc, v8, v1, vcc +; VI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v12, 0 +; VI-NEXT: v_mul_lo_u32 v8, v10, v13 +; VI-NEXT: v_mul_lo_u32 v9, v11, v12 +; VI-NEXT: v_mul_hi_u32 v10, v12, v0 +; VI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v13, v0, 0 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v8 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v9 +; VI-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v1, 0 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v13, v1, 0 +; VI-NEXT: v_add_u32_e32 v8, vcc, v10, v8 +; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; VI-NEXT: v_add_u32_e32 v6, vcc, v8, v6 +; VI-NEXT: v_addc_u32_e32 v6, vcc, v9, v7, vcc +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, v6, v0 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; VI-NEXT: v_add_u32_e32 v6, vcc, v12, v0 +; VI-NEXT: v_addc_u32_e32 v7, vcc, v13, v1, vcc +; VI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s8, v7, 0 +; VI-NEXT: v_mul_hi_u32 v8, s8, v6 +; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v0 +; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc +; VI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s9, v6, 0 +; VI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s9, v7, 0 +; VI-NEXT: v_add_u32_e32 v0, vcc, v8, v0 +; VI-NEXT: v_addc_u32_e32 v0, vcc, v9, v1, vcc +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc +; VI-NEXT: v_add_u32_e32 v6, vcc, v0, v6 +; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc +; VI-NEXT: v_mul_lo_u32 v8, v4, v7 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v6, 0 +; VI-NEXT: v_mul_lo_u32 v9, v5, v6 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v8 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v9 +; VI-NEXT: v_sub_u32_e32 v8, vcc, s9, v1 +; VI-NEXT: v_sub_u32_e32 v0, vcc, s8, v0 +; VI-NEXT: v_subb_u32_e64 v8, s[4:5], v8, v5, vcc +; VI-NEXT: v_sub_u32_e64 v9, s[4:5], v0, v4 +; VI-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5] +; VI-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v5 +; VI-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] +; VI-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v4 +; VI-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v5 +; VI-NEXT: v_cndmask_b32_e64 v8, v10, v9, s[4:5] +; VI-NEXT: v_add_u32_e64 v9, s[4:5], 2, v6 +; VI-NEXT: v_addc_u32_e64 v10, s[4:5], 0, v7, s[4:5] +; VI-NEXT: v_add_u32_e64 v11, s[4:5], 1, v6 +; VI-NEXT: v_addc_u32_e64 v12, s[4:5], 0, v7, s[4:5] +; VI-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8 +; VI-NEXT: v_cndmask_b32_e64 v8, v12, v10, s[4:5] +; VI-NEXT: v_mov_b32_e32 v10, s9 +; VI-NEXT: v_subb_u32_e32 v1, vcc, v10, v1, vcc +; VI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5 +; VI-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc +; VI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 +; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; VI-NEXT: v_cmp_eq_u32_e32 vcc, v1, v5 +; VI-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; VI-NEXT: v_cndmask_b32_e64 v0, v11, v9, s[4:5] +; VI-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc +; VI-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; VI-NEXT: ; implicit-def: $vgpr4_vgpr5 +; VI-NEXT: .LBB28_2: ; %Flow1 +; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7] +; VI-NEXT: s_cbranch_execz .LBB28_4 +; VI-NEXT: ; %bb.3: +; VI-NEXT: v_cvt_f32_u32_e32 v0, v4 +; VI-NEXT: v_sub_u32_e32 v1, vcc, 0, v4 +; VI-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; VI-NEXT: v_cvt_u32_f32_e32 v0, v0 +; VI-NEXT: v_mul_lo_u32 v1, v1, v0 +; VI-NEXT: v_mul_hi_u32 v1, v0, v1 +; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1 +; VI-NEXT: v_mul_hi_u32 v0, s8, v0 +; VI-NEXT: v_mul_lo_u32 v1, v0, v4 +; VI-NEXT: v_add_u32_e32 v5, vcc, 1, v0 +; VI-NEXT: v_sub_u32_e32 v1, vcc, s8, v1 +; VI-NEXT: v_sub_u32_e32 v6, vcc, v1, v4 +; VI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4 +; VI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; VI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, 1, v0 +; VI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4 +; VI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; VI-NEXT: v_mov_b32_e32 v1, 0 +; VI-NEXT: .LBB28_4: +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_or_b32_e32 v5, s11, v3 +; VI-NEXT: v_mov_b32_e32 v4, 0 +; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; VI-NEXT: ; implicit-def: $vgpr4_vgpr5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_xor_b64 s[6:7], exec, s[4:5] +; VI-NEXT: s_cbranch_execz .LBB28_6 +; VI-NEXT: ; %bb.5: +; VI-NEXT: v_cvt_f32_u32_e32 v4, v2 +; VI-NEXT: v_cvt_f32_u32_e32 v5, v3 +; VI-NEXT: v_sub_u32_e32 v10, vcc, 0, v2 +; VI-NEXT: v_subb_u32_e32 v11, vcc, 0, v3, vcc +; VI-NEXT: v_madmk_f32 v4, v5, 0x4f800000, v4 +; VI-NEXT: v_rcp_f32_e32 v4, v4 +; VI-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 +; VI-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 +; VI-NEXT: v_trunc_f32_e32 v5, v5 +; VI-NEXT: v_madmk_f32 v4, v5, 0xcf800000, v4 +; VI-NEXT: v_cvt_u32_f32_e32 v8, v5 +; VI-NEXT: v_cvt_u32_f32_e32 v9, v4 +; VI-NEXT: v_mul_lo_u32 v6, v10, v8 +; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v9, 0 +; VI-NEXT: v_mul_lo_u32 v7, v11, v9 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v6 +; VI-NEXT: v_add_u32_e32 v7, vcc, v5, v7 +; VI-NEXT: v_mul_hi_u32 v12, v9, v4 +; VI-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v9, v7, 0 +; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v5 +; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v4, 0 +; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v6, vcc +; VI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v7, 0 +; VI-NEXT: v_add_u32_e32 v4, vcc, v12, v4 +; VI-NEXT: v_addc_u32_e32 v4, vcc, v13, v5, vcc +; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 +; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc +; VI-NEXT: v_add_u32_e32 v12, vcc, v9, v4 +; VI-NEXT: v_addc_u32_e32 v13, vcc, v8, v5, vcc +; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v12, 0 +; VI-NEXT: v_mul_lo_u32 v8, v10, v13 +; VI-NEXT: v_mul_lo_u32 v9, v11, v12 +; VI-NEXT: v_mul_hi_u32 v10, v12, v4 +; VI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v13, v4, 0 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v8 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v9 +; VI-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v5, 0 +; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v13, v5, 0 +; VI-NEXT: v_add_u32_e32 v8, vcc, v10, v8 +; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; VI-NEXT: v_add_u32_e32 v6, vcc, v8, v6 +; VI-NEXT: v_addc_u32_e32 v6, vcc, v9, v7, vcc +; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, v6, v4 +; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc +; VI-NEXT: v_add_u32_e32 v6, vcc, v12, v4 +; VI-NEXT: v_addc_u32_e32 v7, vcc, v13, v5, vcc +; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], s10, v7, 0 +; VI-NEXT: v_mul_hi_u32 v8, s10, v6 +; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v4 +; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], s11, v6, 0 +; VI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s11, v7, 0 +; VI-NEXT: v_add_u32_e32 v4, vcc, v8, v4 +; VI-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc +; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc +; VI-NEXT: v_add_u32_e32 v6, vcc, v4, v6 +; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc +; VI-NEXT: v_mul_lo_u32 v8, v2, v7 +; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v6, 0 +; VI-NEXT: v_mul_lo_u32 v9, v3, v6 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v8 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v9 +; VI-NEXT: v_sub_u32_e32 v8, vcc, s11, v5 +; VI-NEXT: v_sub_u32_e32 v4, vcc, s10, v4 +; VI-NEXT: v_subb_u32_e64 v8, s[4:5], v8, v3, vcc +; VI-NEXT: v_sub_u32_e64 v9, s[4:5], v4, v2 +; VI-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5] +; VI-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v3 +; VI-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] +; VI-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v2 +; VI-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v3 +; VI-NEXT: v_cndmask_b32_e64 v8, v10, v9, s[4:5] +; VI-NEXT: v_add_u32_e64 v9, s[4:5], 2, v6 +; VI-NEXT: v_addc_u32_e64 v10, s[4:5], 0, v7, s[4:5] +; VI-NEXT: v_add_u32_e64 v11, s[4:5], 1, v6 +; VI-NEXT: v_addc_u32_e64 v12, s[4:5], 0, v7, s[4:5] +; VI-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8 +; VI-NEXT: v_cndmask_b32_e64 v8, v12, v10, s[4:5] +; VI-NEXT: v_mov_b32_e32 v10, s11 +; VI-NEXT: v_subb_u32_e32 v5, vcc, v10, v5, vcc +; VI-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3 +; VI-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc +; VI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2 +; VI-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc +; VI-NEXT: v_cmp_eq_u32_e32 vcc, v5, v3 +; VI-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; VI-NEXT: v_cndmask_b32_e64 v2, v11, v9, s[4:5] +; VI-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc +; VI-NEXT: v_cndmask_b32_e32 v4, v6, v2, vcc +; VI-NEXT: ; implicit-def: $vgpr2_vgpr3 +; VI-NEXT: .LBB28_6: ; %Flow +; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7] +; VI-NEXT: s_cbranch_execz .LBB28_8 +; VI-NEXT: ; %bb.7: +; VI-NEXT: v_cvt_f32_u32_e32 v3, v2 +; VI-NEXT: v_sub_u32_e32 v4, vcc, 0, v2 +; VI-NEXT: v_rcp_iflag_f32_e32 v3, v3 +; VI-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 +; VI-NEXT: v_cvt_u32_f32_e32 v3, v3 +; VI-NEXT: v_mul_lo_u32 v4, v4, v3 +; VI-NEXT: v_mul_hi_u32 v4, v3, v4 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v4 +; VI-NEXT: v_mul_hi_u32 v3, s10, v3 +; VI-NEXT: v_mul_lo_u32 v4, v3, v2 +; VI-NEXT: v_add_u32_e32 v5, vcc, 1, v3 +; VI-NEXT: v_sub_u32_e32 v4, vcc, s10, v4 +; VI-NEXT: v_sub_u32_e32 v6, vcc, v4, v2 +; VI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2 +; VI-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, 1, v3 +; VI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2 +; VI-NEXT: v_cndmask_b32_e32 v4, v3, v5, vcc +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: .LBB28_8: +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_mov_b32_e32 v2, v4 +; VI-NEXT: v_mov_b32_e32 v3, v5 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: bitcast_v4f32_to_v2i64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v5, v1 +; GFX9-NEXT: v_mov_b32_e32 v4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_or_b32_e32 v1, s9, v5 +; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5] +; GFX9-NEXT: s_cbranch_execz .LBB28_2 +; GFX9-NEXT: ; %bb.1: +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v4 +; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v5 +; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, 0, v4 +; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, 0, v5, vcc +; GFX9-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 +; GFX9-NEXT: v_rcp_f32_e32 v0, v0 +; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GFX9-NEXT: v_trunc_f32_e32 v1, v1 +; GFX9-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 +; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v1 +; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v0 +; GFX9-NEXT: v_mul_lo_u32 v6, v10, v8 +; GFX9-NEXT: v_mul_lo_u32 v7, v11, v9 +; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v9, 0 +; GFX9-NEXT: v_add3_u32 v12, v1, v6, v7 +; GFX9-NEXT: v_mul_hi_u32 v1, v9, v0 +; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v9, v12, 0 +; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v1, v6 +; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v0, 0 +; GFX9-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v7, vcc +; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v12, 0 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v13, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v14, v1, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v9, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v8, v1, vcc +; GFX9-NEXT: v_mul_lo_u32 v6, v10, v13 +; GFX9-NEXT: v_mul_lo_u32 v7, v11, v12 +; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v12, 0 +; GFX9-NEXT: v_add3_u32 v1, v1, v6, v7 +; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v1, 0 +; GFX9-NEXT: v_mul_hi_u32 v10, v12, v0 +; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v13, v1, 0 +; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v13, v0, 0 +; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8 +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v9, v1, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v12, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v1, vcc +; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s8, v7, 0 +; GFX9-NEXT: v_mul_hi_u32 v8, s8, v6 +; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc +; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s9, v6, 0 +; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s9, v7, 0 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v9, v1, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v0, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc +; GFX9-NEXT: v_mul_lo_u32 v8, v5, v6 +; GFX9-NEXT: v_mul_lo_u32 v9, v4, v7 +; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, v6, 0 +; GFX9-NEXT: v_add3_u32 v1, v1, v9, v8 +; GFX9-NEXT: v_sub_u32_e32 v8, s9, v1 +; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s8, v0 +; GFX9-NEXT: v_subb_co_u32_e64 v8, s[4:5], v8, v5, vcc +; GFX9-NEXT: v_sub_co_u32_e64 v9, s[4:5], v0, v4 +; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[4:5], 0, v8, s[4:5] +; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] +; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v4 +; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v8, v10, v9, s[4:5] +; GFX9-NEXT: v_add_co_u32_e64 v9, s[4:5], 2, v6 +; GFX9-NEXT: v_addc_co_u32_e64 v10, s[4:5], 0, v7, s[4:5] +; GFX9-NEXT: v_add_co_u32_e64 v11, s[4:5], 1, v6 +; GFX9-NEXT: v_addc_co_u32_e64 v12, s[4:5], 0, v7, s[4:5] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8 +; GFX9-NEXT: v_cndmask_b32_e64 v8, v12, v10, s[4:5] +; GFX9-NEXT: v_mov_b32_e32 v10, s9 +; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v10, v1, vcc +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v11, v9, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5 +; GFX9-NEXT: .LBB28_2: ; %Flow1 +; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7] +; GFX9-NEXT: s_cbranch_execz .LBB28_4 +; GFX9-NEXT: ; %bb.3: +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v4 +; GFX9-NEXT: v_sub_u32_e32 v1, 0, v4 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX9-NEXT: v_mul_lo_u32 v1, v1, v0 +; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 +; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0 +; GFX9-NEXT: v_mul_lo_u32 v1, v0, v4 +; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 +; GFX9-NEXT: v_sub_u32_e32 v1, s8, v1 +; GFX9-NEXT: v_sub_u32_e32 v6, v1, v4 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; GFX9-NEXT: v_add_u32_e32 v5, 1, v0 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: .LBB28_4: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_or_b32_e32 v5, s11, v3 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5] +; GFX9-NEXT: s_cbranch_execz .LBB28_6 +; GFX9-NEXT: ; %bb.5: +; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2 +; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3 +; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, 0, v2 +; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, 0, v3, vcc +; GFX9-NEXT: v_madmk_f32 v4, v5, 0x4f800000, v4 +; GFX9-NEXT: v_rcp_f32_e32 v4, v4 +; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 +; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 +; GFX9-NEXT: v_trunc_f32_e32 v5, v5 +; GFX9-NEXT: v_madmk_f32 v4, v5, 0xcf800000, v4 +; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v5 +; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v4 +; GFX9-NEXT: v_mul_lo_u32 v6, v10, v8 +; GFX9-NEXT: v_mul_lo_u32 v7, v11, v9 +; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v9, 0 +; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7 +; GFX9-NEXT: v_mul_hi_u32 v12, v9, v4 +; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v9, v7, 0 +; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v12, v5 +; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v4, 0 +; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v6, vcc +; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v7, 0 +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v12, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v13, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc +; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v9, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v8, v5, vcc +; GFX9-NEXT: v_mul_lo_u32 v6, v10, v13 +; GFX9-NEXT: v_mul_lo_u32 v7, v11, v12 +; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v12, 0 +; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7 +; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v7, 0 +; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v12, v7, 0 +; GFX9-NEXT: v_mul_hi_u32 v11, v12, v4 +; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v4, 0 +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v11, v7 +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v9 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v10, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc +; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v12, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v5, vcc +; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], s10, v7, 0 +; GFX9-NEXT: v_mul_hi_u32 v8, s10, v6 +; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v5, vcc +; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], s11, v6, 0 +; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s11, v7, 0 +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v4, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v5, vcc +; GFX9-NEXT: v_mul_lo_u32 v8, v3, v6 +; GFX9-NEXT: v_mul_lo_u32 v9, v2, v7 +; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v2, v6, 0 +; GFX9-NEXT: v_add3_u32 v5, v5, v9, v8 +; GFX9-NEXT: v_sub_u32_e32 v8, s11, v5 +; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s10, v4 +; GFX9-NEXT: v_subb_co_u32_e64 v8, s[4:5], v8, v3, vcc +; GFX9-NEXT: v_sub_co_u32_e64 v9, s[4:5], v4, v2 +; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[4:5], 0, v8, s[4:5] +; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v3 +; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] +; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v3 +; GFX9-NEXT: v_cndmask_b32_e64 v8, v10, v9, s[4:5] +; GFX9-NEXT: v_add_co_u32_e64 v9, s[4:5], 2, v6 +; GFX9-NEXT: v_addc_co_u32_e64 v10, s[4:5], 0, v7, s[4:5] +; GFX9-NEXT: v_add_co_u32_e64 v11, s[4:5], 1, v6 +; GFX9-NEXT: v_addc_co_u32_e64 v12, s[4:5], 0, v7, s[4:5] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8 +; GFX9-NEXT: v_cndmask_b32_e64 v8, v12, v10, s[4:5] +; GFX9-NEXT: v_mov_b32_e32 v10, s11 +; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v10, v5, vcc +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3 +; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, v11, v9, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v2, vcc +; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3 +; GFX9-NEXT: .LBB28_6: ; %Flow +; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7] +; GFX9-NEXT: s_cbranch_execz .LBB28_8 +; GFX9-NEXT: ; %bb.7: +; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v2 +; GFX9-NEXT: v_sub_u32_e32 v4, 0, v2 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3 +; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 +; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GFX9-NEXT: v_mul_lo_u32 v4, v4, v3 +; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4 +; GFX9-NEXT: v_add_u32_e32 v3, v3, v4 +; GFX9-NEXT: v_mul_hi_u32 v3, s10, v3 +; GFX9-NEXT: v_mul_lo_u32 v4, v3, v2 +; GFX9-NEXT: v_add_u32_e32 v5, 1, v3 +; GFX9-NEXT: v_sub_u32_e32 v4, s10, v4 +; GFX9-NEXT: v_sub_u32_e32 v6, v4, v2 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GFX9-NEXT: v_add_u32_e32 v5, 1, v3 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v5, vcc +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: .LBB28_8: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_mov_b32_e32 v2, v4 +; GFX9-NEXT: v_mov_b32_e32 v3, v5 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: bitcast_v4f32_to_v2i64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_buffer_load_b128 s[4:7], s[0:3], 0x0 +; GFX11-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_or_b32_e32 v1, s5, v5 +; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1] +; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_xor_b32 s1, exec_lo, s0 +; GFX11-NEXT: s_cbranch_execz .LBB28_2 +; GFX11-NEXT: ; %bb.1: +; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v4 +; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v5 +; GFX11-NEXT: v_sub_co_u32 v10, vcc_lo, 0, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_sub_co_ci_u32_e64 v11, null, 0, v5, vcc_lo +; GFX11-NEXT: v_fmamk_f32 v0, v1, 0x4f800000, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_rcp_f32_e32 v0, v0 +; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GFX11-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_trunc_f32_e32 v1, v1 +; GFX11-NEXT: v_fmamk_f32 v0, v1, 0xcf800000, v0 +; GFX11-NEXT: v_cvt_u32_f32_e32 v12, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cvt_u32_f32_e32 v13, v0 +; GFX11-NEXT: v_mul_lo_u32 v6, v10, v12 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_mul_lo_u32 v7, v11, v13 +; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v10, v13, 0 +; GFX11-NEXT: v_add3_u32 v14, v1, v6, v7 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_mul_hi_u32 v15, v13, v0 +; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, v12, v0, 0 +; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v13, v14, 0 +; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v12, v14, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v15, v6 +; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, v8 +; GFX11-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v7, v9, vcc_lo +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v6, v0 +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_u32 v13, vcc_lo, v13, v0 +; GFX11-NEXT: v_add_co_ci_u32_e64 v12, null, v12, v1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_mul_lo_u32 v6, v11, v13 +; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v10, v13, 0 +; GFX11-NEXT: v_mul_lo_u32 v7, v10, v12 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_mul_hi_u32 v11, v13, v0 +; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, v12, v0, 0 +; GFX11-NEXT: v_add3_u32 v10, v1, v7, v6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v13, v10, 0 +; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v12, v10, 0 +; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v11, v6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo +; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, v8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v7, v9, vcc_lo +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v6, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v13, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e64 v10, null, v12, v1, vcc_lo +; GFX11-NEXT: v_mul_hi_u32 v11, s4, v8 +; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, s5, v8, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, s4, v10, 0 +; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, s5, v10, 0 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v11, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v0, vcc_lo, v1, v7, vcc_lo +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v9, vcc_lo +; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v0, v8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo +; GFX11-NEXT: v_mul_lo_u32 v8, v5, v6 +; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v6, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mul_lo_u32 v9, v4, v7 +; GFX11-NEXT: v_sub_co_u32 v0, vcc_lo, s4, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add3_u32 v1, v1, v9, v8 +; GFX11-NEXT: v_add_co_u32 v9, s0, v6, 2 +; GFX11-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v7, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_sub_nc_u32_e32 v8, s5, v1 +; GFX11-NEXT: v_sub_co_u32 v11, s0, v0, v4 +; GFX11-NEXT: v_sub_co_ci_u32_e64 v1, null, s5, v1, vcc_lo +; GFX11-NEXT: v_sub_co_ci_u32_e64 v8, null, v8, v5, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v11, v4 +; GFX11-NEXT: v_subrev_co_ci_u32_e64 v8, null, 0, v8, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e64 s0, v1, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v8, v5 +; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc_lo +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v4 +; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v1, v5 +; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v8, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0 +; GFX11-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc_lo +; GFX11-NEXT: v_add_co_u32 v11, vcc_lo, v6, 1 +; GFX11-NEXT: v_add_co_ci_u32_e64 v12, null, 0, v7, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 +; GFX11-NEXT: v_dual_cndmask_b32 v1, v12, v10 :: v_dual_cndmask_b32 v4, v11, v9 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_dual_cndmask_b32 v1, v7, v1 :: v_dual_cndmask_b32 v0, v6, v4 +; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5 +; GFX11-NEXT: .LBB28_2: ; %Flow1 +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s1 +; GFX11-NEXT: s_cbranch_execz .LBB28_4 +; GFX11-NEXT: ; %bb.3: +; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v4 +; GFX11-NEXT: v_sub_nc_u32_e32 v1, 0, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_mul_lo_u32 v1, v1, v0 +; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v1 +; GFX11-NEXT: v_mul_hi_u32 v0, s4, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mul_lo_u32 v1, v0, v4 +; GFX11-NEXT: v_add_nc_u32_e32 v5, 1, v0 +; GFX11-NEXT: v_sub_nc_u32_e32 v1, s4, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_sub_nc_u32_e32 v6, v1, v4 +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v1, v4 +; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v6 :: v_dual_cndmask_b32 v0, v0, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v1, v4 +; GFX11-NEXT: v_add_nc_u32_e32 v5, 1, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_cndmask_b32 v0, v0, v5 +; GFX11-NEXT: .LBB28_4: +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: v_or_b32_e32 v5, s7, v3 +; GFX11-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5] +; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5 +; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-NEXT: s_xor_b32 s1, exec_lo, s0 +; GFX11-NEXT: s_cbranch_execz .LBB28_6 +; GFX11-NEXT: ; %bb.5: +; GFX11-NEXT: v_cvt_f32_u32_e32 v4, v2 +; GFX11-NEXT: v_cvt_f32_u32_e32 v5, v3 +; GFX11-NEXT: v_sub_co_u32 v11, vcc_lo, 0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_sub_co_ci_u32_e64 v12, null, 0, v3, vcc_lo +; GFX11-NEXT: v_fmamk_f32 v4, v5, 0x4f800000, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_rcp_f32_e32 v4, v4 +; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 +; GFX11-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_trunc_f32_e32 v5, v5 +; GFX11-NEXT: v_fmamk_f32 v4, v5, 0xcf800000, v4 +; GFX11-NEXT: v_cvt_u32_f32_e32 v13, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cvt_u32_f32_e32 v14, v4 +; GFX11-NEXT: v_mul_lo_u32 v6, v11, v13 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_mul_lo_u32 v7, v12, v14 +; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, v11, v14, 0 +; GFX11-NEXT: v_add3_u32 v15, v5, v6, v7 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_mul_hi_u32 v16, v14, v4 +; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, v13, v4, 0 +; GFX11-NEXT: v_mad_u64_u32 v[5:6], null, v14, v15, 0 +; GFX11-NEXT: v_mad_u64_u32 v[9:10], null, v13, v15, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v16, v5 +; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v6, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v7 +; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v5, v8, vcc_lo +; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v9 +; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, v4 +; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, v13, v5, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_mul_lo_u32 v6, v12, v14 +; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, v11, v14, 0 +; GFX11-NEXT: v_mul_lo_u32 v7, v11, v13 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mul_hi_u32 v12, v14, v4 +; GFX11-NEXT: v_add3_u32 v11, v5, v7, v6 +; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, v13, v4, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mad_u64_u32 v[5:6], null, v14, v11, 0 +; GFX11-NEXT: v_mad_u64_u32 v[9:10], null, v13, v11, 0 +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v12, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v6, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v7 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v5, v8, vcc_lo +; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v14, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e64 v10, null, v13, v5, vcc_lo +; GFX11-NEXT: v_mul_hi_u32 v11, s6, v8 +; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, s7, v8, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, s6, v10, 0 +; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, s7, v10, 0 +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v11, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v5, v7, vcc_lo +; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo +; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v4, v8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v5, vcc_lo +; GFX11-NEXT: v_mul_lo_u32 v8, v3, v6 +; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, v2, v6, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mul_lo_u32 v9, v2, v7 +; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, s6, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add3_u32 v5, v5, v9, v8 +; GFX11-NEXT: v_add_co_u32 v9, s0, v6, 2 +; GFX11-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v7, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_sub_nc_u32_e32 v8, s7, v5 +; GFX11-NEXT: v_sub_co_u32 v11, s0, v4, v2 +; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, null, s7, v5, vcc_lo +; GFX11-NEXT: v_sub_co_ci_u32_e64 v8, null, v8, v3, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v11, v2 +; GFX11-NEXT: v_subrev_co_ci_u32_e64 v8, null, 0, v8, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e64 s0, v5, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v8, v3 +; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc_lo +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v5, v3 +; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v8, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v2, s0 +; GFX11-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc_lo +; GFX11-NEXT: v_add_co_u32 v11, vcc_lo, v6, 1 +; GFX11-NEXT: v_add_co_ci_u32_e64 v12, null, 0, v7, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 +; GFX11-NEXT: v_dual_cndmask_b32 v3, v12, v10 :: v_dual_cndmask_b32 v4, v11, v9 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_dual_cndmask_b32 v5, v7, v3 :: v_dual_cndmask_b32 v4, v6, v4 +; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3 +; GFX11-NEXT: .LBB28_6: ; %Flow +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s1 +; GFX11-NEXT: s_cbranch_execz .LBB28_8 +; GFX11-NEXT: ; %bb.7: +; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v2 +; GFX11-NEXT: v_sub_nc_u32_e32 v4, 0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3 +; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 +; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_mul_lo_u32 v4, v4, v3 +; GFX11-NEXT: v_mul_hi_u32 v4, v3, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v4 +; GFX11-NEXT: v_mul_hi_u32 v3, s6, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mul_lo_u32 v4, v3, v2 +; GFX11-NEXT: v_add_nc_u32_e32 v5, 1, v3 +; GFX11-NEXT: v_sub_nc_u32_e32 v4, s6, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_sub_nc_u32_e32 v6, v4, v2 +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v2 +; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v3, v3, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v2 +; GFX11-NEXT: v_add_nc_u32_e32 v5, 1, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_cndmask_b32 v4, v3, v5 :: v_dual_mov_b32 v5, 0 +; GFX11-NEXT: .LBB28_8: +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5 +; GFX11-NEXT: s_setpc_b64 s[30:31] + %val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> poison, i32 0, i32 0) + %cast = bitcast <4 x float> %val to <2 x i64> + %div = udiv <2 x i64> %cast, %arg + ret <2 x i64> %div +} + +declare half @llvm.canonicalize.f16(half) + + +define amdgpu_kernel void @bitcast_f32_to_v1i32(ptr addrspace(1) %out) { +; GCN-LABEL: bitcast_f32_to_v1i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, 0x387c0000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_f32_to_v1i32: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; VI-NEXT: v_mov_b32_e32 v2, 0x387c0000 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: flat_store_dword v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_f32_to_v1i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, 0x387c0000 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_f32_to_v1i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x387c0000 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_endpgm + %f16 = call arcp afn half @llvm.canonicalize.f16(half 0xH03F0) + %f32 = fpext half %f16 to float + %v = bitcast float %f32 to <1 x i32> + %v1 = extractelement <1 x i32> %v, i32 0 + store i32 %v1, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @bitcast_v4i64_to_v16i16(i32 %cond, ptr addrspace(1) %out, <4 x i64> %value) { +; GCN-LABEL: bitcast_v4i64_to_v16i16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s1, s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v4i64_to_v16i16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s9, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s9, 0 +; VI-NEXT: s_add_u32 s6, s4, 16 +; VI-NEXT: s_addc_u32 s7, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s6 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s7 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v4i64_to_v16i16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s9, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v4i64_to_v16i16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s9, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_mov_b32_e32 v6, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v8, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v8, v[4:7], s[4:5] +; GFX11-NEXT: s_cmp_lg_u32 s9, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <4 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <4 x i64> %phi_value to <16 x i16> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <16 x i16> [zeroinitializer, %entry], [%cast, %if] + store <16 x i16> %phi_cast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @bitcast_v4f64_to_v16f16(i32 %cond, ptr addrspace(1) %out, <4 x double> %value) { +; GCN-LABEL: bitcast_v4f64_to_v16f16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s7, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v7, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v8, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v9, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v10, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v11, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v12, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v13, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v14, s7 +; GCN-NEXT: v_cvt_f16_f32_e32 v15, s6 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_or_b32_e32 v0, v1, v0 +; GCN-NEXT: v_or_b32_e32 v1, v3, v2 +; GCN-NEXT: v_or_b32_e32 v2, v5, v4 +; GCN-NEXT: v_or_b32_e32 v3, v7, v6 +; GCN-NEXT: v_or_b32_e32 v4, v9, v8 +; GCN-NEXT: v_or_b32_e32 v5, v11, v10 +; GCN-NEXT: v_or_b32_e32 v6, v13, v12 +; GCN-NEXT: v_or_b32_e32 v7, v15, v14 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v4f64_to_v16f16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s9, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s9, 0 +; VI-NEXT: s_add_u32 s6, s4, 16 +; VI-NEXT: s_addc_u32 s7, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s6 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s7 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v4f64_to_v16f16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s9, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v4f64_to_v16f16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s9, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_mov_b32_e32 v6, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v8, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v8, v[4:7], s[4:5] +; GFX11-NEXT: s_cmp_lg_u32 s9, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <4 x double> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <4 x double> %phi_value to <16 x half> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <16 x half> [zeroinitializer, %entry], [%cast, %if] + store <16 x half> %phi_cast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @bitcast_v16i16_to_v4i64(i32 %cond, ptr addrspace(1) %out, <16 x i16> %value) { +; GCN-LABEL: bitcast_v16i16_to_v4i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s1, s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v16i16_to_v4i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s9, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s9, 0 +; VI-NEXT: s_add_u32 s6, s4, 16 +; VI-NEXT: s_addc_u32 s7, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s6 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s7 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v16i16_to_v4i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s9, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v16i16_to_v4i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s9, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_mov_b32_e32 v6, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v8, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v8, v[4:7], s[4:5] +; GFX11-NEXT: s_cmp_lg_u32 s9, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <16 x i16> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <16 x i16> %phi_value to <4 x i64> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <4 x i64> [zeroinitializer, %entry], [%cast, %if] + store <4 x i64> %phi_cast, ptr addrspace(1) %out + ret void +} + + +define amdgpu_kernel void @bitcast_v16f16_to_v4f64(i32 %cond, ptr addrspace(1) %out, <16 x half> %value) { +; GCN-LABEL: bitcast_v16f16_to_v4f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s1, s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v16f16_to_v4f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s9, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s9, 0 +; VI-NEXT: s_add_u32 s6, s4, 16 +; VI-NEXT: s_addc_u32 s7, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s6 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s7 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v16f16_to_v4f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s9, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v16f16_to_v4f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s9, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_mov_b32_e32 v6, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v8, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v8, v[4:7], s[4:5] +; GFX11-NEXT: s_cmp_lg_u32 s9, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <16 x half> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <16 x half> %phi_value to <4 x double> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <4 x double> [zeroinitializer, %entry], [%cast, %if] + store <4 x double> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v20f16_to_v5f64(i32 %cond, ptr addrspace(1) %out, <20 x half> %value) { +; GCN-LABEL: bitcast_v20f16_to_v5f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v20f16_to_v5f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v20f16_to_v5f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v20f16_to_v5f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <20 x half> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <20 x half> %phi_value to <5 x double> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <5 x double> [zeroinitializer, %entry], [%cast, %if] + store <5 x double> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v10f32_to_v5f64(i32 %cond, ptr addrspace(1) %out, <10 x float> %value) { +; GCN-LABEL: bitcast_v10f32_to_v5f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v10f32_to_v5f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v10f32_to_v5f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v10f32_to_v5f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <10 x float> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <10 x float> %phi_value to <5 x double> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <5 x double> [zeroinitializer, %entry], [%cast, %if] + store <5 x double> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v10i32_to_v5f64(i32 %cond, ptr addrspace(1) %out, <10 x i32> %value) { +; GCN-LABEL: bitcast_v10i32_to_v5f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v10i32_to_v5f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v10i32_to_v5f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v10i32_to_v5f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <10 x i32> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <10 x i32> %phi_value to <5 x double> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <5 x double> [zeroinitializer, %entry], [%cast, %if] + store <5 x double> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v10f32_to_v5i64(i32 %cond, ptr addrspace(1) %out, <10 x float> %value) { +; GCN-LABEL: bitcast_v10f32_to_v5i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v10f32_to_v5i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v10f32_to_v5i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v10f32_to_v5i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <10 x float> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <10 x float> %phi_value to <5 x i64> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <5 x i64> [zeroinitializer, %entry], [%cast, %if] + store <5 x i64> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v10i32_to_v5i64(i32 %cond, ptr addrspace(1) %out, <10 x i32> %value) { +; GCN-LABEL: bitcast_v10i32_to_v5i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v10i32_to_v5i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v10i32_to_v5i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v10i32_to_v5i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <10 x i32> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <10 x i32> %phi_value to <5 x i64> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <5 x i64> [zeroinitializer, %entry], [%cast, %if] + store <5 x i64> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v40i8_to_v5f64(i32 %cond, ptr addrspace(1) %out, <40 x i8> %value) { +; GCN-LABEL: bitcast_v40i8_to_v5f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v40i8_to_v5f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v40i8_to_v5f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v40i8_to_v5f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <40 x i8> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <40 x i8> %phi_value to <5 x double> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <5 x double> [zeroinitializer, %entry], [%cast, %if] + store <5 x double> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v40i8_to_v5i64(i32 %cond, ptr addrspace(1) %out, <40 x i8> %value) { +; GCN-LABEL: bitcast_v40i8_to_v5i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v40i8_to_v5i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v40i8_to_v5i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v40i8_to_v5i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <40 x i8> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <40 x i8> %phi_value to <5 x i64> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <5 x i64> [zeroinitializer, %entry], [%cast, %if] + store <5 x i64> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v5f64_to_v10f32(i32 %cond, ptr addrspace(1) %out, <5 x double> %value) { +; GCN-LABEL: bitcast_v5f64_to_v10f32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s1, s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v5f64_to_v10f32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s7, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s1, 0 +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s7, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v2, s1 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v2, s1 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v5f64_to_v10f32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s7, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s7, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v5f64_to_v10f32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s7, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_cmp_lg_u32 s7, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <5 x double> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <5 x double> %phi_value to <10 x float> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <10 x float> [zeroinitializer, %entry], [%cast, %if] + store <10 x float> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v5f64_to_v10i32(i32 %cond, ptr addrspace(1) %out, <5 x double> %value) { +; GCN-LABEL: bitcast_v5f64_to_v10i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s1, s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v5f64_to_v10i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s7, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s1, 0 +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s7, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v2, s1 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v2, s1 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v5f64_to_v10i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s7, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s7, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v5f64_to_v10i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s7, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_cmp_lg_u32 s7, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <5 x double> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <5 x double> %phi_value to <10 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <10 x i32> [zeroinitializer, %entry], [%cast, %if] + store <10 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v5i64_to_v10f32(i32 %cond, ptr addrspace(1) %out, <5 x i64> %value) { +; GCN-LABEL: bitcast_v5i64_to_v10f32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s1, s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v5i64_to_v10f32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s7, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s1, 0 +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s7, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v2, s1 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v2, s1 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v5i64_to_v10f32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s7, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s7, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v5i64_to_v10f32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s7, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_cmp_lg_u32 s7, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <5 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <5 x i64> %phi_value to <10 x float> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <10 x float> [zeroinitializer, %entry], [%cast, %if] + store <10 x float> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v5i64_to_v10i32(i32 %cond, ptr addrspace(1) %out, <5 x i64> %value) { +; GCN-LABEL: bitcast_v5i64_to_v10i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s1, s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s15, 0xf000 +; GCN-NEXT: s_mov_b32 s14, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx2 v[8:9], off, s[12:15], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v5i64_to_v10i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s7, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s1, 0 +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s7, 0 +; VI-NEXT: s_add_u32 s8, s4, 16 +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s8 +; VI-NEXT: v_mov_b32_e32 v2, s1 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v2, s1 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v5i64_to_v10i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s7, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s7, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[12:13] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[12:13] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v5i64_to_v10i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s7, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_mov_b32_e32 v8, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v10, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v10, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v10, v[8:9], s[4:5] offset:32 +; GFX11-NEXT: s_cmp_lg_u32 s7, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <5 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <5 x i64> %phi_value to <10 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <10 x i32> [zeroinitializer, %entry], [%cast, %if] + store <10 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v6f64_to_v12i32(i32 %cond, ptr addrspace(1) %out, <6 x double> %value) { +; GCN-LABEL: bitcast_v6f64_to_v12i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s1, s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s19, 0xf000 +; GCN-NEXT: s_mov_b32 s18, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: v_mov_b32_e32 v10, s0 +; GCN-NEXT: v_mov_b32_e32 v11, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[16:19], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v6f64_to_v12i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s9, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s3, 0 +; VI-NEXT: v_mov_b32_e32 v0, s3 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s9, 0 +; VI-NEXT: s_add_u32 s10, s4, 16 +; VI-NEXT: s_addc_u32 s11, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s10 +; VI-NEXT: v_mov_b32_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v5, s11 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v0, s3 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v6f64_to_v12i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s9, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v6f64_to_v12i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s9, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_mov_b32_e32 v10, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v12, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v12, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b128 v12, v[8:11], s[4:5] offset:32 +; GFX11-NEXT: s_cmp_lg_u32 s9, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <6 x double> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <6 x double> %phi_value to <12 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <12 x i32> [zeroinitializer, %entry], [%cast, %if] + store <12 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v6f64_to_v12f32(i32 %cond, ptr addrspace(1) %out, <6 x double> %value) { +; GCN-LABEL: bitcast_v6f64_to_v12f32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s1, s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s19, 0xf000 +; GCN-NEXT: s_mov_b32 s18, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: v_mov_b32_e32 v10, s0 +; GCN-NEXT: v_mov_b32_e32 v11, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[16:19], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v6f64_to_v12f32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s9, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s3, 0 +; VI-NEXT: v_mov_b32_e32 v0, s3 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s9, 0 +; VI-NEXT: s_add_u32 s10, s4, 16 +; VI-NEXT: s_addc_u32 s11, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s10 +; VI-NEXT: v_mov_b32_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v5, s11 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v0, s3 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v6f64_to_v12f32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s9, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v6f64_to_v12f32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s9, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_mov_b32_e32 v10, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v12, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v12, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b128 v12, v[8:11], s[4:5] offset:32 +; GFX11-NEXT: s_cmp_lg_u32 s9, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <6 x double> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <6 x double> %phi_value to <12 x float> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <12 x float> [zeroinitializer, %entry], [%cast, %if] + store <12 x float> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v12i32_to_v6i64(i32 %cond, ptr addrspace(1) %out, <12 x i32> %value) { +; GCN-LABEL: bitcast_v12i32_to_v6i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s19, 0xf000 +; GCN-NEXT: s_mov_b32 s18, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: v_mov_b32_e32 v10, s0 +; GCN-NEXT: v_mov_b32_e32 v11, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[16:19], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v12i32_to_v6i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s10, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s11, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s10 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s11 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v12i32_to_v6i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v12i32_to_v6i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_mov_b32_e32 v10, s0 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v12, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v12, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b128 v12, v[8:11], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <12 x i32> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <12 x i32> %phi_value to <6 x i64> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <6 x i64> [zeroinitializer, %entry], [%cast, %if] + store <6 x i64> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v12i32_to_v6f64(i32 %cond, ptr addrspace(1) %out, <12 x i32> %value) { +; GCN-LABEL: bitcast_v12i32_to_v6f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s19, 0xf000 +; GCN-NEXT: s_mov_b32 s18, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: v_mov_b32_e32 v10, s0 +; GCN-NEXT: v_mov_b32_e32 v11, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[16:19], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v12i32_to_v6f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s10, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s11, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s10 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s11 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v12i32_to_v6f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v12i32_to_v6f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_mov_b32_e32 v10, s0 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v12, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v12, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b128 v12, v[8:11], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <12 x i32> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <12 x i32> %phi_value to <6 x double> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <6 x double> [zeroinitializer, %entry], [%cast, %if] + store <6 x double> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v6i64_to_v12i32(i32 %cond, ptr addrspace(1) %out, <6 x i64> %value) { +; GCN-LABEL: bitcast_v6i64_to_v12i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s1, s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s19, 0xf000 +; GCN-NEXT: s_mov_b32 s18, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: v_mov_b32_e32 v10, s0 +; GCN-NEXT: v_mov_b32_e32 v11, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[16:19], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v6i64_to_v12i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s9, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_mov_b32 s3, 0 +; VI-NEXT: v_mov_b32_e32 v0, s3 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s9, 0 +; VI-NEXT: s_add_u32 s10, s4, 16 +; VI-NEXT: s_addc_u32 s11, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s10 +; VI-NEXT: v_mov_b32_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v5, s11 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v0, s3 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v6i64_to_v12i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s9, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x2c +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] offset:16 +; GFX9-NEXT: s_cmp_lg_u32 s9, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[14:15] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v6i64_to_v12i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s9, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_mov_b32_e32 v10, s0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b128 v12, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v12, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b128 v12, v[8:11], s[4:5] offset:32 +; GFX11-NEXT: s_cmp_lg_u32 s9, 0 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <6 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <6 x i64> %phi_value to <12 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <12 x i32> [zeroinitializer, %entry], [%cast, %if] + store <12 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v7i64_to_v14i32(i32 %cond, ptr addrspace(1) %out, <7 x i64> %value) { +; GCN-LABEL: bitcast_v7i64_to_v14i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s19, 0xf000 +; GCN-NEXT: s_mov_b32 s18, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v12, s0 +; GCN-NEXT: v_mov_b32_e32 v13, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: v_mov_b32_e32 v10, s0 +; GCN-NEXT: v_mov_b32_e32 v11, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 +; GCN-NEXT: buffer_store_dwordx2 v[12:13], off, s[16:19], 0 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[16:19], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v7i64_to_v14i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s12, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s13, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s12 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s13 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s8, s4, 48 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v2, s8 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v3, s9 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v7i64_to_v14i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17] offset:48 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v7i64_to_v14i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v13, s0 +; GFX11-NEXT: v_dual_mov_b32 v12, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_mov_b32_e32 v10, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v14, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v14, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v14, v[12:13], s[4:5] offset:48 +; GFX11-NEXT: global_store_b128 v14, v[8:11], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <7 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <7 x i64> %phi_value to <14 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <14 x i32> [zeroinitializer, %entry], [%cast, %if] + store <14 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v7f64_to_v14i32(i32 %cond, ptr addrspace(1) %out, <7 x double> %value) { +; GCN-LABEL: bitcast_v7f64_to_v14i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s0, 0 +; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s19, 0xf000 +; GCN-NEXT: s_mov_b32 s18, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_mov_b32_e32 v7, s0 +; GCN-NEXT: v_mov_b32_e32 v12, s0 +; GCN-NEXT: v_mov_b32_e32 v13, s0 +; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_mov_b32_e32 v9, s0 +; GCN-NEXT: v_mov_b32_e32 v10, s0 +; GCN-NEXT: v_mov_b32_e32 v11, s0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 +; GCN-NEXT: buffer_store_dwordx2 v[12:13], off, s[16:19], 0 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[16:19], 0 offset:32 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v7f64_to_v14i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s12, s4, 16 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s13, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s12 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s13 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s8, s4, 48 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s9, s5, 0 +; VI-NEXT: v_mov_b32_e32 v2, s8 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v3, s9 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: s_add_u32 s0, s4, 32 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v7f64_to_v14i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17] offset:48 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:32 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v7f64_to_v14i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v13, s0 +; GFX11-NEXT: v_dual_mov_b32 v12, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_mov_b32_e32 v10, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v14, v[0:3], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v14, v[4:7], s[4:5] +; GFX11-NEXT: global_store_b64 v14, v[12:13], s[4:5] offset:48 +; GFX11-NEXT: global_store_b128 v14, v[8:11], s[4:5] offset:32 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <7 x double> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <7 x double> %phi_value to <14 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <14 x i32> [zeroinitializer, %entry], [%cast, %if] + store <14 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v9i64_to_v18i32(i32 %cond, ptr addrspace(1) %out, <9 x i64> %value) { +; GCN-LABEL: bitcast_v9i64_to_v18i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: v_mov_b32_e32 v6, s6 +; GCN-NEXT: v_mov_b32_e32 v7, s6 +; GCN-NEXT: v_mov_b32_e32 v8, s6 +; GCN-NEXT: v_mov_b32_e32 v9, s6 +; GCN-NEXT: v_mov_b32_e32 v10, s6 +; GCN-NEXT: v_mov_b32_e32 v11, s6 +; GCN-NEXT: v_mov_b32_e32 v12, s6 +; GCN-NEXT: v_mov_b32_e32 v13, s6 +; GCN-NEXT: v_mov_b32_e32 v14, s6 +; GCN-NEXT: v_mov_b32_e32 v15, s6 +; GCN-NEXT: v_mov_b32_e32 v16, s6 +; GCN-NEXT: v_mov_b32_e32 v17, s6 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 +; GCN-NEXT: buffer_store_dwordx2 v[16:17], off, s[0:3], 0 offset:64 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v9i64_to_v18i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s16, s4, 48 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s17, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s16 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s17 +; VI-NEXT: s_add_u32 s12, s4, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s13, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s12 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s13 +; VI-NEXT: s_add_u32 s10, s4, 16 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s11, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s10 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s11 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_add_u32 s0, s4, 64 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v9i64_to_v18i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[20:21], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[20:21] offset:48 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[20:21] offset:32 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[20:21] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[20:21] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[20:21] offset:64 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v9i64_to_v18i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v13, s0 +; GFX11-NEXT: v_dual_mov_b32 v12, s0 :: v_dual_mov_b32 v15, s0 +; GFX11-NEXT: v_dual_mov_b32 v14, s0 :: v_dual_mov_b32 v17, s0 +; GFX11-NEXT: v_mov_b32_e32 v16, s0 +; GFX11-NEXT: s_clause 0x4 +; GFX11-NEXT: global_store_b128 v18, v[0:3], s[4:5] offset:48 +; GFX11-NEXT: global_store_b128 v18, v[4:7], s[4:5] offset:32 +; GFX11-NEXT: global_store_b128 v18, v[8:11], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v18, v[12:15], s[4:5] +; GFX11-NEXT: global_store_b64 v18, v[16:17], s[4:5] offset:64 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <9 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <9 x i64> %phi_value to <18 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <18 x i32> [zeroinitializer, %entry], [%cast, %if] + store <18 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v10i64_to_v20i32(i32 %cond, ptr addrspace(1) %out, <10 x i64> %value) { +; GCN-LABEL: bitcast_v10i64_to_v20i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: v_mov_b32_e32 v6, s6 +; GCN-NEXT: v_mov_b32_e32 v7, s6 +; GCN-NEXT: v_mov_b32_e32 v8, s6 +; GCN-NEXT: v_mov_b32_e32 v9, s6 +; GCN-NEXT: v_mov_b32_e32 v10, s6 +; GCN-NEXT: v_mov_b32_e32 v11, s6 +; GCN-NEXT: v_mov_b32_e32 v12, s6 +; GCN-NEXT: v_mov_b32_e32 v13, s6 +; GCN-NEXT: v_mov_b32_e32 v14, s6 +; GCN-NEXT: v_mov_b32_e32 v15, s6 +; GCN-NEXT: v_mov_b32_e32 v16, s6 +; GCN-NEXT: v_mov_b32_e32 v17, s6 +; GCN-NEXT: v_mov_b32_e32 v18, s6 +; GCN-NEXT: v_mov_b32_e32 v19, s6 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 +; GCN-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:64 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v10i64_to_v20i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s18, s4, 48 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s19, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s18 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s19 +; VI-NEXT: s_add_u32 s14, s4, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s15, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s14 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s15 +; VI-NEXT: s_add_u32 s14, s4, 16 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s15, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s14 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s15 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: s_add_u32 s0, s4, 64 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v10i64_to_v20i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[22:23] offset:48 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[22:23] offset:32 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[22:23] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[22:23] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[22:23] offset:64 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v10i64_to_v20i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v13, s0 +; GFX11-NEXT: v_dual_mov_b32 v12, s0 :: v_dual_mov_b32 v15, s0 +; GFX11-NEXT: v_dual_mov_b32 v14, s0 :: v_dual_mov_b32 v17, s0 +; GFX11-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v19, s0 +; GFX11-NEXT: v_mov_b32_e32 v18, s0 +; GFX11-NEXT: s_clause 0x4 +; GFX11-NEXT: global_store_b128 v20, v[0:3], s[4:5] offset:48 +; GFX11-NEXT: global_store_b128 v20, v[4:7], s[4:5] offset:32 +; GFX11-NEXT: global_store_b128 v20, v[8:11], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v20, v[12:15], s[4:5] +; GFX11-NEXT: global_store_b128 v20, v[16:19], s[4:5] offset:64 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <10 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <10 x i64> %phi_value to <20 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <20 x i32> [zeroinitializer, %entry], [%cast, %if] + store <20 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v11i64_to_v20i32(i32 %cond, ptr addrspace(1) %out, <11 x i64> %value) { +; GCN-LABEL: bitcast_v11i64_to_v20i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: v_mov_b32_e32 v6, s6 +; GCN-NEXT: v_mov_b32_e32 v7, s6 +; GCN-NEXT: v_mov_b32_e32 v8, s6 +; GCN-NEXT: v_mov_b32_e32 v9, s6 +; GCN-NEXT: v_mov_b32_e32 v10, s6 +; GCN-NEXT: v_mov_b32_e32 v11, s6 +; GCN-NEXT: v_mov_b32_e32 v12, s6 +; GCN-NEXT: v_mov_b32_e32 v13, s6 +; GCN-NEXT: v_mov_b32_e32 v14, s6 +; GCN-NEXT: v_mov_b32_e32 v15, s6 +; GCN-NEXT: v_mov_b32_e32 v16, s6 +; GCN-NEXT: v_mov_b32_e32 v17, s6 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 +; GCN-NEXT: buffer_store_dwordx2 v[16:17], off, s[0:3], 0 offset:80 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v11i64_to_v20i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s20, s4, 48 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s21, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s20 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s21 +; VI-NEXT: s_add_u32 s16, s4, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s17, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s16 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s17 +; VI-NEXT: s_add_u32 s10, s4, 16 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s11, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s10 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s11 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_mov_b32 s6, s0 +; VI-NEXT: s_mov_b32 s7, s0 +; VI-NEXT: s_mov_b32 s8, s0 +; VI-NEXT: s_mov_b32 s9, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_add_u32 s0, s4, 0x50 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: s_add_u32 s0, s4, 64 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: v_mov_b32_e32 v0, s6 +; VI-NEXT: v_mov_b32_e32 v1, s7 +; VI-NEXT: v_mov_b32_e32 v2, s8 +; VI-NEXT: v_mov_b32_e32 v3, s9 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v11i64_to_v20i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[24:25], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[24:25] offset:48 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[24:25] offset:32 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[24:25] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[24:25] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[24:25] offset:80 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[24:25] offset:64 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v11i64_to_v20i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v13, s0 +; GFX11-NEXT: v_dual_mov_b32 v12, s0 :: v_dual_mov_b32 v15, s0 +; GFX11-NEXT: v_dual_mov_b32 v14, s0 :: v_dual_mov_b32 v21, s0 +; GFX11-NEXT: v_dual_mov_b32 v20, s0 :: v_dual_mov_b32 v17, s0 +; GFX11-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v19, s0 +; GFX11-NEXT: v_mov_b32_e32 v18, s0 +; GFX11-NEXT: s_clause 0x5 +; GFX11-NEXT: global_store_b128 v22, v[0:3], s[4:5] offset:48 +; GFX11-NEXT: global_store_b128 v22, v[4:7], s[4:5] offset:32 +; GFX11-NEXT: global_store_b128 v22, v[8:11], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v22, v[12:15], s[4:5] +; GFX11-NEXT: global_store_b64 v22, v[20:21], s[4:5] offset:80 +; GFX11-NEXT: global_store_b128 v22, v[16:19], s[4:5] offset:64 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <11 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <11 x i64> %phi_value to <22 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <22 x i32> [zeroinitializer, %entry], [%cast, %if] + store <22 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v12i64_to_v22i32(i32 %cond, ptr addrspace(1) %out, <12 x i64> %value) { +; GCN-LABEL: bitcast_v12i64_to_v22i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: v_mov_b32_e32 v6, s6 +; GCN-NEXT: v_mov_b32_e32 v7, s6 +; GCN-NEXT: v_mov_b32_e32 v8, s6 +; GCN-NEXT: v_mov_b32_e32 v9, s6 +; GCN-NEXT: v_mov_b32_e32 v10, s6 +; GCN-NEXT: v_mov_b32_e32 v11, s6 +; GCN-NEXT: v_mov_b32_e32 v12, s6 +; GCN-NEXT: v_mov_b32_e32 v13, s6 +; GCN-NEXT: v_mov_b32_e32 v14, s6 +; GCN-NEXT: v_mov_b32_e32 v15, s6 +; GCN-NEXT: v_mov_b32_e32 v16, s6 +; GCN-NEXT: v_mov_b32_e32 v17, s6 +; GCN-NEXT: v_mov_b32_e32 v18, s6 +; GCN-NEXT: v_mov_b32_e32 v19, s6 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v12i64_to_v22i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s22, s4, 0x50 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s23, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s22 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s23 +; VI-NEXT: s_add_u32 s18, s4, 64 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s19, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s18 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s19 +; VI-NEXT: s_add_u32 s14, s4, 48 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s15, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s14 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s15 +; VI-NEXT: s_add_u32 s10, s4, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s11, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s10 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s11 +; VI-NEXT: s_add_u32 s6, s4, 16 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s7, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s6 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s7 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v12i64_to_v22i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[26:27], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[26:27] offset:80 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[26:27] offset:64 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[26:27] offset:48 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[26:27] offset:32 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[26:27] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[26:27] +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v12i64_to_v22i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v13, s0 +; GFX11-NEXT: v_dual_mov_b32 v12, s0 :: v_dual_mov_b32 v15, s0 +; GFX11-NEXT: v_dual_mov_b32 v14, s0 :: v_dual_mov_b32 v17, s0 +; GFX11-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v19, s0 +; GFX11-NEXT: v_dual_mov_b32 v18, s0 :: v_dual_mov_b32 v21, s0 +; GFX11-NEXT: v_dual_mov_b32 v20, s0 :: v_dual_mov_b32 v23, s0 +; GFX11-NEXT: v_mov_b32_e32 v22, s0 +; GFX11-NEXT: s_clause 0x5 +; GFX11-NEXT: global_store_b128 v24, v[0:3], s[4:5] offset:80 +; GFX11-NEXT: global_store_b128 v24, v[4:7], s[4:5] offset:64 +; GFX11-NEXT: global_store_b128 v24, v[8:11], s[4:5] offset:48 +; GFX11-NEXT: global_store_b128 v24, v[12:15], s[4:5] offset:32 +; GFX11-NEXT: global_store_b128 v24, v[16:19], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v24, v[20:23], s[4:5] +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <12 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <12 x i64> %phi_value to <24 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <24 x i32> [zeroinitializer, %entry], [%cast, %if] + store <24 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v13i64_to_v24i32(i32 %cond, ptr addrspace(1) %out, <13 x i64> %value) { +; GCN-LABEL: bitcast_v13i64_to_v24i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: v_mov_b32_e32 v6, s6 +; GCN-NEXT: v_mov_b32_e32 v7, s6 +; GCN-NEXT: v_mov_b32_e32 v8, s6 +; GCN-NEXT: v_mov_b32_e32 v9, s6 +; GCN-NEXT: v_mov_b32_e32 v10, s6 +; GCN-NEXT: v_mov_b32_e32 v11, s6 +; GCN-NEXT: v_mov_b32_e32 v12, s6 +; GCN-NEXT: v_mov_b32_e32 v13, s6 +; GCN-NEXT: v_mov_b32_e32 v14, s6 +; GCN-NEXT: v_mov_b32_e32 v15, s6 +; GCN-NEXT: v_mov_b32_e32 v16, s6 +; GCN-NEXT: v_mov_b32_e32 v17, s6 +; GCN-NEXT: v_mov_b32_e32 v18, s6 +; GCN-NEXT: v_mov_b32_e32 v19, s6 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; GCN-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:96 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v13i64_to_v24i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_add_u32 s24, s4, 0x50 +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: s_addc_u32 s25, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s24 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s25 +; VI-NEXT: s_add_u32 s20, s4, 64 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s21, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s20 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s21 +; VI-NEXT: s_add_u32 s16, s4, 48 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s17, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s16 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s17 +; VI-NEXT: s_add_u32 s12, s4, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s13, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s12 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s13 +; VI-NEXT: s_add_u32 s6, s4, 16 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s7, s5, 0 +; VI-NEXT: v_mov_b32_e32 v4, s6 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s7 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: s_add_u32 s0, s4, 0x60 +; VI-NEXT: s_addc_u32 s1, s5, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v13i64_to_v24i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[28:29], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[28:29] offset:80 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[28:29] offset:64 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[28:29] offset:48 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[28:29] offset:32 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[28:29] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[28:29] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[28:29] offset:96 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v13i64_to_v24i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v13, s0 +; GFX11-NEXT: v_dual_mov_b32 v12, s0 :: v_dual_mov_b32 v15, s0 +; GFX11-NEXT: v_dual_mov_b32 v14, s0 :: v_dual_mov_b32 v17, s0 +; GFX11-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v19, s0 +; GFX11-NEXT: v_mov_b32_e32 v18, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v20, v[0:3], s[4:5] offset:80 +; GFX11-NEXT: global_store_b128 v20, v[4:7], s[4:5] offset:64 +; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s0 +; GFX11-NEXT: v_dual_mov_b32 v3, s0 :: v_dual_mov_b32 v4, s0 +; GFX11-NEXT: v_mov_b32_e32 v5, s0 +; GFX11-NEXT: s_clause 0x4 +; GFX11-NEXT: global_store_b128 v20, v[8:11], s[4:5] offset:48 +; GFX11-NEXT: global_store_b128 v20, v[12:15], s[4:5] offset:32 +; GFX11-NEXT: global_store_b128 v20, v[16:19], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v20, v[0:3], s[4:5] +; GFX11-NEXT: global_store_b64 v20, v[4:5], s[4:5] offset:96 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <13 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <13 x i64> %phi_value to <26 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <26 x i32> [zeroinitializer, %entry], [%cast, %if] + store <26 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v14i64_to_v26i32(i32 %cond, ptr addrspace(1) %out, <14 x i64> %value) { +; GCN-LABEL: bitcast_v14i64_to_v26i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: v_mov_b32_e32 v6, s6 +; GCN-NEXT: v_mov_b32_e32 v7, s6 +; GCN-NEXT: v_mov_b32_e32 v8, s6 +; GCN-NEXT: v_mov_b32_e32 v9, s6 +; GCN-NEXT: v_mov_b32_e32 v10, s6 +; GCN-NEXT: v_mov_b32_e32 v11, s6 +; GCN-NEXT: v_mov_b32_e32 v12, s6 +; GCN-NEXT: v_mov_b32_e32 v13, s6 +; GCN-NEXT: v_mov_b32_e32 v14, s6 +; GCN-NEXT: v_mov_b32_e32 v15, s6 +; GCN-NEXT: v_mov_b32_e32 v16, s6 +; GCN-NEXT: v_mov_b32_e32 v17, s6 +; GCN-NEXT: v_mov_b32_e32 v18, s6 +; GCN-NEXT: v_mov_b32_e32 v19, s6 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: v_mov_b32_e32 v6, s6 +; GCN-NEXT: v_mov_b32_e32 v7, s6 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:96 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v14i64_to_v26i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_u32 s4, s0, 0x50 +; VI-NEXT: s_addc_u32 s5, s1, 0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s4, s0, 64 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s5, s1, 0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s4, s0, 48 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s5, s1, 0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s4, s0, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s5, s1, 0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s4, s0, 16 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s5, s1, 0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: s_add_u32 s0, s0, 0x60 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: s_addc_u32 s1, s1, 0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v14i64_to_v26i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[30:31], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[30:31] offset:80 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[30:31] offset:64 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[30:31] offset:48 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[30:31] offset:32 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[30:31] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[30:31] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[30:31] offset:96 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v14i64_to_v26i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v13, s0 +; GFX11-NEXT: v_dual_mov_b32 v12, s0 :: v_dual_mov_b32 v15, s0 +; GFX11-NEXT: v_dual_mov_b32 v14, s0 :: v_dual_mov_b32 v17, s0 +; GFX11-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v19, s0 +; GFX11-NEXT: v_mov_b32_e32 v18, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v20, v[0:3], s[4:5] offset:80 +; GFX11-NEXT: global_store_b128 v20, v[4:7], s[4:5] offset:64 +; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s0 +; GFX11-NEXT: v_dual_mov_b32 v3, s0 :: v_dual_mov_b32 v4, s0 +; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s0 +; GFX11-NEXT: v_mov_b32_e32 v7, s0 +; GFX11-NEXT: s_clause 0x4 +; GFX11-NEXT: global_store_b128 v20, v[8:11], s[4:5] offset:48 +; GFX11-NEXT: global_store_b128 v20, v[12:15], s[4:5] offset:32 +; GFX11-NEXT: global_store_b128 v20, v[16:19], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v20, v[0:3], s[4:5] +; GFX11-NEXT: global_store_b128 v20, v[4:7], s[4:5] offset:96 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <14 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <14 x i64> %phi_value to <28 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <28 x i32> [zeroinitializer, %entry], [%cast, %if] + store <28 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + + +define amdgpu_kernel void @bitcast_v15i64_to_v26i32(i32 %cond, ptr addrspace(1) %out, <15 x i64> %value) { +; GCN-LABEL: bitcast_v15i64_to_v26i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_dword s0, s[4:5], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: v_mov_b32_e32 v6, s6 +; GCN-NEXT: v_mov_b32_e32 v7, s6 +; GCN-NEXT: v_mov_b32_e32 v8, s6 +; GCN-NEXT: v_mov_b32_e32 v9, s6 +; GCN-NEXT: v_mov_b32_e32 v10, s6 +; GCN-NEXT: v_mov_b32_e32 v11, s6 +; GCN-NEXT: v_mov_b32_e32 v12, s6 +; GCN-NEXT: v_mov_b32_e32 v13, s6 +; GCN-NEXT: v_mov_b32_e32 v14, s6 +; GCN-NEXT: v_mov_b32_e32 v15, s6 +; GCN-NEXT: v_mov_b32_e32 v16, s6 +; GCN-NEXT: v_mov_b32_e32 v17, s6 +; GCN-NEXT: v_mov_b32_e32 v18, s6 +; GCN-NEXT: v_mov_b32_e32 v19, s6 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, s6 +; GCN-NEXT: v_mov_b32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64 +; GCN-NEXT: v_mov_b32_e32 v20, s6 +; GCN-NEXT: v_mov_b32_e32 v21, s6 +; GCN-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48 +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: v_mov_b32_e32 v4, s6 +; GCN-NEXT: v_mov_b32_e32 v5, s6 +; GCN-NEXT: v_mov_b32_e32 v6, s6 +; GCN-NEXT: v_mov_b32_e32 v7, s6 +; GCN-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +; GCN-NEXT: buffer_store_dwordx2 v[20:21], off, s[0:3], 0 offset:112 +; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:96 +; GCN-NEXT: s_endpgm +; +; VI-LABEL: bitcast_v15i64_to_v26i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_load_dword s0, s[4:5], 0x24 +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: s_mov_b32 s12, s2 +; VI-NEXT: s_mov_b32 s13, s2 +; VI-NEXT: s_mov_b32 s14, s2 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_add_u32 s4, s0, 0x50 +; VI-NEXT: s_addc_u32 s5, s1, 0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s4, s0, 64 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s5, s1, 0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s4, s0, 48 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s5, s1, 0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s4, s0, 32 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s5, s1, 0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_add_u32 s4, s0, 16 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_addc_u32 s5, s1, 0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: s_mov_b32 s15, s2 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: s_add_u32 s2, s0, 0x70 +; VI-NEXT: s_addc_u32 s3, s1, 0 +; VI-NEXT: s_add_u32 s0, s0, 0x60 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: s_addc_u32 s1, s1, 0 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; VI-NEXT: v_mov_b32_e32 v0, s12 +; VI-NEXT: v_mov_b32_e32 v1, s13 +; VI-NEXT: v_mov_b32_e32 v2, s14 +; VI-NEXT: v_mov_b32_e32 v3, s15 +; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: bitcast_v15i64_to_v26i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x2c +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_mov_b32 s0, 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[34:35] offset:80 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[34:35] offset:64 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[34:35] offset:48 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[34:35] offset:32 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[34:35] offset:16 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[34:35] +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[34:35] offset:112 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[34:35] offset:96 +; GFX9-NEXT: s_endpgm +; +; GFX11-LABEL: bitcast_v15i64_to_v26i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s0 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v5, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s0 +; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, s0 +; GFX11-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s0 +; GFX11-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v13, s0 +; GFX11-NEXT: v_dual_mov_b32 v12, s0 :: v_dual_mov_b32 v15, s0 +; GFX11-NEXT: v_dual_mov_b32 v14, s0 :: v_dual_mov_b32 v17, s0 +; GFX11-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v19, s0 +; GFX11-NEXT: v_mov_b32_e32 v18, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v22, v[0:3], s[4:5] offset:80 +; GFX11-NEXT: global_store_b128 v22, v[4:7], s[4:5] offset:64 +; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s0 +; GFX11-NEXT: v_dual_mov_b32 v3, s0 :: v_dual_mov_b32 v20, s0 +; GFX11-NEXT: v_dual_mov_b32 v21, s0 :: v_dual_mov_b32 v4, s0 +; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s0 +; GFX11-NEXT: v_mov_b32_e32 v7, s0 +; GFX11-NEXT: s_clause 0x5 +; GFX11-NEXT: global_store_b128 v22, v[8:11], s[4:5] offset:48 +; GFX11-NEXT: global_store_b128 v22, v[12:15], s[4:5] offset:32 +; GFX11-NEXT: global_store_b128 v22, v[16:19], s[4:5] offset:16 +; GFX11-NEXT: global_store_b128 v22, v[0:3], s[4:5] +; GFX11-NEXT: global_store_b64 v22, v[20:21], s[4:5] offset:112 +; GFX11-NEXT: global_store_b128 v22, v[4:7], s[4:5] offset:96 +; GFX11-NEXT: s_endpgm +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %phi_value = phi <15 x i64> [zeroinitializer, %entry], [%value, %if] + %cast = bitcast <15 x i64> %phi_value to <30 x i32> + %cmp1 = icmp eq i32 %cond, 1 + br i1 %cmp1, label %if, label %end + +end: + %phi_cast = phi <30 x i32> [zeroinitializer, %entry], [%cast, %if] + store <30 x i32> %phi_cast, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v2bf16_to_i32(i32 %cond, ptr addrspace(1) %out, <2 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v2bf16_to_i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB59_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v5, v0, v3, 16 +; GCN-NEXT: .LBB59_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v5, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v2bf16_to_i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v4, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v4, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dword v[1:2], v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v2bf16_to_i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v4, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dword v[1:2], v4, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v2bf16_to_i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v4, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b32 v[1:2], v4, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x bfloat> %value to i32 + br label %end + +end: + %phi = phi i32 [0, %entry], [%cast, %if] + store i32 %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v2bf16_to_v2i16(i32 %cond, ptr addrspace(1) %out, <2 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v2bf16_to_v2i16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB60_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v5, v0, v3, 16 +; GCN-NEXT: .LBB60_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v5, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v2bf16_to_v2i16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v4, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v4, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dword v[1:2], v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v2bf16_to_v2i16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v0, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dword v[1:2], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v2bf16_to_v2i16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v0, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b32 v[1:2], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x bfloat> %value to <2 x i16> + br label %end + +end: + %phi = phi <2 x i16> [zeroinitializer, %entry], [%cast, %if] + store <2 x i16> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v2bf16_to_v2f16(i32 %cond, ptr addrspace(1) %out, <2 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v2bf16_to_v2f16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB61_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v5, v3 +; GCN-NEXT: .LBB61_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_or_b32_e32 v0, v0, v3 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v2bf16_to_v2f16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v4, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v4, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dword v[1:2], v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v2bf16_to_v2f16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v0, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dword v[1:2], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v2bf16_to_v2f16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v0, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b32 v[1:2], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x bfloat> %value to <2 x half> + br label %end + +end: + %phi = phi <2 x half> [zeroinitializer, %entry], [%cast, %if] + store <2 x half> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v2bf16_to_v4i8(i32 %cond, ptr addrspace(1) %out, <2 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v2bf16_to_v4i8: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB62_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v5, v0, v3, 16 +; GCN-NEXT: .LBB62_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v5, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v2bf16_to_v4i8: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v4, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v4, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dword v[1:2], v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v2bf16_to_v4i8: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v4, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dword v[1:2], v4, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v2bf16_to_v4i8: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v4, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b32 v[1:2], v4, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x bfloat> %value to <4 x i8> + br label %end + +end: + %phi = phi <4 x i8> [zeroinitializer, %entry], [%cast, %if] + store <4 x i8> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v3bf16_to_v3i16(i32 %cond, ptr addrspace(1) %out, <3 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v3bf16_to_v3i16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, v6 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB63_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v6, v4, v3, 16 +; GCN-NEXT: .LBB63_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_short v0, v[1:2], s[4:7], 0 addr64 offset:4 +; GCN-NEXT: buffer_store_dword v6, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v3bf16_to_v3i16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_short v[3:4], v6 +; VI-NEXT: flat_store_dword v[1:2], v5 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v3bf16_to_v3i16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_short v[1:2], v6, off offset:4 +; GFX9-NEXT: global_store_dword v[1:2], v5, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v3bf16_to_v3i16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b16 v[1:2], v6, off offset:4 +; GFX11-NEXT: global_store_b32 v[1:2], v5, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <3 x bfloat> %value to <3 x i16> + br label %end + +end: + %phi = phi <3 x i16> [zeroinitializer, %entry], [%cast, %if] + store <3 x i16> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v3bf16_to_v3f16(i32 %cond, ptr addrspace(1) %out, <3 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v3bf16_to_v3f16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB64_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v6, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v7, v4 +; GCN-NEXT: .LBB64_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v7 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v6 +; GCN-NEXT: buffer_store_short v3, v[1:2], s[4:7], 0 addr64 offset:4 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_or_b32_e32 v0, v0, v3 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v3bf16_to_v3f16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_short v[3:4], v6 +; VI-NEXT: flat_store_dword v[1:2], v5 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v3bf16_to_v3f16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_short v[1:2], v6, off offset:4 +; GFX9-NEXT: global_store_dword v[1:2], v5, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v3bf16_to_v3f16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b16 v[1:2], v6, off offset:4 +; GFX11-NEXT: global_store_b32 v[1:2], v5, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <3 x bfloat> %value to <3 x half> + br label %end + +end: + %phi = phi <3 x half> [zeroinitializer, %entry], [%cast, %if] + store <3 x half> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_i32_to_v2bf16(i32 %cond, ptr addrspace(1) %out, i32 %value) { +; GCN-LABEL: v_bitcast_i32_to_v2bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v4, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB65_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v3 +; GCN-NEXT: .LBB65_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_alignbit_b32 v0, v3, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_i32_to_v2bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v4, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v4, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dword v[1:2], v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_i32_to_v2bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v0, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dword v[1:2], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_i32_to_v2bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v0, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b32 v[1:2], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast i32 %value to <2 x bfloat> + br label %end + +end: + %phi = phi <2 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <2 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v2i16_to_v2bf16(i32 %cond, ptr addrspace(1) %out, <2 x i16> %value) { +; GCN-LABEL: v_bitcast_v2i16_to_v2bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB66_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v4 +; GCN-NEXT: .LBB66_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_alignbit_b32 v0, v3, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v2i16_to_v2bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v4, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v4, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dword v[1:2], v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v2i16_to_v2bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v0, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dword v[1:2], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v2i16_to_v2bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v0, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b32 v[1:2], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x i16> %value to <2 x bfloat> + br label %end + +end: + %phi = phi <2 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <2 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v2f16_to_v2bf16(i32 %cond, ptr addrspace(1) %out, <2 x half> %value) { +; GCN-LABEL: v_bitcast_v2f16_to_v2bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB67_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GCN-NEXT: .LBB67_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_alignbit_b32 v0, v3, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v2f16_to_v2bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v4, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v4, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dword v[1:2], v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v2f16_to_v2bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v0, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dword v[1:2], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v2f16_to_v2bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v0, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b32 v[1:2], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x half> %value to <2 x bfloat> + br label %end + +end: + %phi = phi <2 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <2 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4i8_to_v2bf16(i32 %cond, ptr addrspace(1) %out, <4 x i8> %value) { +; GCN-LABEL: v_bitcast_v4i8_to_v2bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB68_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 24, v4 +; GCN-NEXT: v_and_b32_e32 v4, 0xff, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 24, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_or_b32_e32 v0, v3, v0 +; GCN-NEXT: v_or_b32_e32 v7, v5, v4 +; GCN-NEXT: .LBB68_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_alignbit_b32 v0, v3, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4i8_to_v2bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v4 +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v6 +; VI-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v7, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dword v[1:2], v7 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4i8_to_v2bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v4 +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6 +; GFX9-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dword v[1:2], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: v_bitcast_v4i8_to_v2bf16: +; GFX11-TRUE16: ; %bb.0: ; %entry +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB68_2 +; GFX11-TRUE16-NEXT: ; %bb.1: ; %if +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v4.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v6.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: .LBB68_2: ; %end +; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-TRUE16-NEXT: global_store_b32 v[1:2], v0, off +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: v_bitcast_v4i8_to_v2bf16: +; GFX11-FAKE16: ; %bb.0: ; %entry +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB68_2 +; GFX11-FAKE16-NEXT: ; %bb.1: ; %if +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v6 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: .LBB68_2: ; %end +; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-FAKE16-NEXT: global_store_b32 v[1:2], v0, off +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x i8> %value to <2 x bfloat> + br label %end + +end: + %phi = phi <2 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <2 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v3i16_to_v3bf16(i32 %cond, ptr addrspace(1) %out, <3 x i16> %value) { +; GCN-LABEL: v_bitcast_v3i16_to_v3bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB69_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GCN-NEXT: .LBB69_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: buffer_store_short v3, v[1:2], s[4:7], 0 addr64 offset:4 +; GCN-NEXT: v_alignbit_b32 v0, v4, v0, 16 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v3i16_to_v3bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_short v[3:4], v6 +; VI-NEXT: flat_store_dword v[1:2], v5 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v3i16_to_v3bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_short v[1:2], v6, off offset:4 +; GFX9-NEXT: global_store_dword v[1:2], v5, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v3i16_to_v3bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b16 v[1:2], v6, off offset:4 +; GFX11-NEXT: global_store_b32 v[1:2], v5, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <3 x i16> %value to <3 x bfloat> + br label %end + +end: + %phi = phi <3 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <3 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4bf16_to_v4f16(i32 %cond, ptr addrspace(1) %out, <4 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v4bf16_to_v4f16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB70_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v7, v4 +; GCN-NEXT: v_cvt_f32_f16_e32 v9, v5 +; GCN-NEXT: .LBB70_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v8 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v9 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_or_b32_e32 v3, v0, v3 +; GCN-NEXT: v_or_b32_e32 v4, v5, v4 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4bf16_to_v4f16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4bf16_to_v4f16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4bf16_to_v4f16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x bfloat> %value to <4 x half> + br label %end + +end: + %phi = phi <4 x half> [zeroinitializer, %entry], [%cast, %if] + store <4 x half> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4bf16_to_v4i16(i32 %cond, ptr addrspace(1) %out, <4 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v4bf16_to_v4i16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v8, v7 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB71_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v7, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v8, v4, v5, 16 +; GCN-NEXT: .LBB71_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[7:8], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4bf16_to_v4i16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4bf16_to_v4i16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4bf16_to_v4i16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x bfloat> %value to <4 x i16> + br label %end + +end: + %phi = phi <4 x i16> [zeroinitializer, %entry], [%cast, %if] + store <4 x i16> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4bf16_to_v2i32(i32 %cond, ptr addrspace(1) %out, <4 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v4bf16_to_v2i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v8, v7 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB72_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v7, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v8, v4, v5, 16 +; GCN-NEXT: .LBB72_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[7:8], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4bf16_to_v2i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4bf16_to_v2i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4bf16_to_v2i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x bfloat> %value to <2 x i32> + br label %end + +end: + %phi = phi <2 x i32> [zeroinitializer, %entry], [%cast, %if] + store <2 x i32> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4bf16_to_v2f32(i32 %cond, ptr addrspace(1) %out, <4 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v4bf16_to_v2f32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v8, v7 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB73_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v7, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v8, v4, v5, 16 +; GCN-NEXT: .LBB73_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[7:8], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4bf16_to_v2f32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4bf16_to_v2f32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4bf16_to_v2f32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x bfloat> %value to <2 x float> + br label %end + +end: + %phi = phi <2 x float> [zeroinitializer, %entry], [%cast, %if] + store <2 x float> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4bf16_to_f64(i32 %cond, ptr addrspace(1) %out, <4 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v4bf16_to_f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB74_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v7, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v8, v4, v5, 16 +; GCN-NEXT: .LBB74_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[7:8], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4bf16_to_f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_mov_b32_e32 v6, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4bf16_to_f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_mov_b32_e32 v6, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4bf16_to_f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: v_mov_b32_e32 v6, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x bfloat> %value to double + br label %end + +end: + %phi = phi double [0.0, %entry], [%cast, %if] + store double %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4bf16_to_i64(i32 %cond, ptr addrspace(1) %out, <4 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v4bf16_to_i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB75_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v7, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v8, v4, v5, 16 +; GCN-NEXT: .LBB75_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[7:8], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4bf16_to_i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_mov_b32_e32 v6, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4bf16_to_i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_mov_b32_e32 v6, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4bf16_to_i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: v_mov_b32_e32 v6, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x bfloat> %value to i64 + br label %end + +end: + %phi = phi i64 [0, %entry], [%cast, %if] + store i64 %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4bf16_to_v8i8(i32 %cond, ptr addrspace(1) %out, <4 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v4bf16_to_v8i8: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v8, v7 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB76_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v7, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v8, v4, v5, 16 +; GCN-NEXT: .LBB76_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[7:8], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4bf16_to_v8i8: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4bf16_to_v8i8: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4bf16_to_v8i8: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x bfloat> %value to <8 x i8> + br label %end + +end: + %phi = phi <8 x i8> [zeroinitializer, %entry], [%cast, %if] + store <8 x i8> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_i64_to_v4bf16(i32 %cond, ptr addrspace(1) %out, i64 %value) { +; GCN-LABEL: v_bitcast_i64_to_v4bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB77_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v4 +; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v3 +; GCN-NEXT: .LBB77_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_i64_to_v4bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_i64_to_v4bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_i64_to_v4bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast i64 %value to <4 x bfloat> + br label %end + +end: + %phi = phi <4 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <4 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v2f32_to_v4bf16(i32 %cond, ptr addrspace(1) %out, <2 x float> %value) { +; GCN-LABEL: v_bitcast_v2f32_to_v4bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB78_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v4 +; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v3 +; GCN-NEXT: .LBB78_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v2f32_to_v4bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v2f32_to_v4bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v2f32_to_v4bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x float> %value to <4 x bfloat> + br label %end + +end: + %phi = phi <4 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <4 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v2i32_to_v4bf16(i32 %cond, ptr addrspace(1) %out, <2 x i32> %value) { +; GCN-LABEL: v_bitcast_v2i32_to_v4bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB79_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v4 +; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v3 +; GCN-NEXT: .LBB79_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v2i32_to_v4bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v2i32_to_v4bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v2i32_to_v4bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x i32> %value to <4 x bfloat> + br label %end + +end: + %phi = phi <4 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <4 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4i16_to_v4bf16(i32 %cond, ptr addrspace(1) %out, <4 x i16> %value) { +; GCN-LABEL: v_bitcast_v4i16_to_v4bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB80_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v6 +; GCN-NEXT: .LBB80_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v3, v3, v0, 16 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4i16_to_v4bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4i16_to_v4bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4i16_to_v4bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x i16> %value to <4 x bfloat> + br label %end + +end: + %phi = phi <4 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <4 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4f16_to_v4bf16(i32 %cond, ptr addrspace(1) %out, <4 x half> %value) { +; GCN-LABEL: v_bitcast_v4f16_to_v4bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB81_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v4 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v5 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v5 +; GCN-NEXT: .LBB81_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v3, v3, v0, 16 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4f16_to_v4bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v5, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx2 v[1:2], v[5:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4f16_to_v4bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx2 v[1:2], v[5:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4f16_to_v4bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v6, v5 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b64 v[1:2], v[5:6], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x half> %value to <4 x bfloat> + br label %end + +end: + %phi = phi <4 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <4 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v6bf16_to_v6i16(i32 %cond, ptr addrspace(1) %out, <6 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v6bf16_to_v6i16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v10, v9 +; GCN-NEXT: v_mov_b32_e32 v0, v9 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB82_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_alignbit_b32 v9, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v10, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v0, v6, v7, 16 +; GCN-NEXT: .LBB82_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 offset:8 +; GCN-NEXT: buffer_store_dwordx2 v[9:10], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v6bf16_to_v6i16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v6, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v7, v6 +; VI-NEXT: v_mov_b32_e32 v8, v6 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v9, v6 +; VI-NEXT: v_mov_b32_e32 v8, v5 +; VI-NEXT: v_mov_b32_e32 v7, v4 +; VI-NEXT: v_mov_b32_e32 v6, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx3 v[1:2], v[6:8] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v6bf16_to_v6i16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v6, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v7, v6 +; GFX9-NEXT: v_mov_b32_e32 v8, v6 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v9, v6 +; GFX9-NEXT: v_mov_b32_e32 v8, v5 +; GFX9-NEXT: v_mov_b32_e32 v7, v4 +; GFX9-NEXT: v_mov_b32_e32 v6, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx3 v[1:2], v[6:8], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v6bf16_to_v6i16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v6, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v7, v6 +; GFX11-NEXT: v_mov_b32_e32 v8, v6 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v9, v6 +; GFX11-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v7, v4 +; GFX11-NEXT: v_mov_b32_e32 v6, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b96 v[1:2], v[6:8], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <6 x bfloat> %value to <6 x i16> + br label %end + +end: + %phi = phi <6 x i16> [zeroinitializer, %entry], [%cast, %if] + store <6 x i16> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v6bf16_to_v6f16(i32 %cond, ptr addrspace(1) %out, <6 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v6bf16_to_v6f16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v10, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB83_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_cvt_f32_f16_e32 v10, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v12, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v11, v4 +; GCN-NEXT: v_cvt_f32_f16_e32 v13, v5 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v6 +; GCN-NEXT: v_cvt_f32_f16_e32 v9, v7 +; GCN-NEXT: .LBB83_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v12 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v10 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v13 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v11 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v7, v9 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_or_b32_e32 v3, v4, v3 +; GCN-NEXT: v_or_b32_e32 v4, v6, v5 +; GCN-NEXT: v_or_b32_e32 v0, v0, v7 +; GCN-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 offset:8 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v6bf16_to_v6f16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v6, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v7, v6 +; VI-NEXT: v_mov_b32_e32 v8, v6 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v9, v6 +; VI-NEXT: v_mov_b32_e32 v8, v5 +; VI-NEXT: v_mov_b32_e32 v7, v4 +; VI-NEXT: v_mov_b32_e32 v6, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx3 v[1:2], v[6:8] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v6bf16_to_v6f16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v6, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v7, v6 +; GFX9-NEXT: v_mov_b32_e32 v8, v6 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v9, v6 +; GFX9-NEXT: v_mov_b32_e32 v8, v5 +; GFX9-NEXT: v_mov_b32_e32 v7, v4 +; GFX9-NEXT: v_mov_b32_e32 v6, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx3 v[1:2], v[6:8], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v6bf16_to_v6f16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v6, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v7, v6 +; GFX11-NEXT: v_mov_b32_e32 v8, v6 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v9, v6 +; GFX11-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v7, v4 +; GFX11-NEXT: v_mov_b32_e32 v6, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b96 v[1:2], v[6:8], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <6 x bfloat> %value to <6 x half> + br label %end + +end: + %phi = phi <6 x half> [zeroinitializer, %entry], [%cast, %if] + store <6 x half> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v6bf16_to_v12i8(i32 %cond, ptr addrspace(1) %out, <6 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v6bf16_to_v12i8: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v10, v9 +; GCN-NEXT: v_mov_b32_e32 v0, v9 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB84_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_alignbit_b32 v9, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v10, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v0, v6, v7, 16 +; GCN-NEXT: .LBB84_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 offset:8 +; GCN-NEXT: buffer_store_dwordx2 v[9:10], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v6bf16_to_v12i8: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v6, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v7, v6 +; VI-NEXT: v_mov_b32_e32 v8, v6 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v8, v5 +; VI-NEXT: v_mov_b32_e32 v7, v4 +; VI-NEXT: v_mov_b32_e32 v6, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx3 v[1:2], v[6:8] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v6bf16_to_v12i8: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v6, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v7, v6 +; GFX9-NEXT: v_mov_b32_e32 v8, v6 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v8, v5 +; GFX9-NEXT: v_mov_b32_e32 v7, v4 +; GFX9-NEXT: v_mov_b32_e32 v6, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx3 v[1:2], v[6:8], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v6bf16_to_v12i8: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v6, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v7, v6 +; GFX11-NEXT: v_mov_b32_e32 v8, v6 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v7, v4 +; GFX11-NEXT: v_mov_b32_e32 v6, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b96 v[1:2], v[6:8], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <6 x bfloat> %value to <12 x i8> + br label %end + +end: + %phi = phi <12 x i8> [zeroinitializer, %entry], [%cast, %if] + store <12 x i8> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v6f16_to_v6bf16(i32 %cond, ptr addrspace(1) %out, <6 x half> %value) { +; GCN-LABEL: v_bitcast_v6f16_to_v6bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v10, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB85_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v4 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v5 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v6 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v7 +; GCN-NEXT: v_cvt_f16_f32_e32 v7, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v7 +; GCN-NEXT: .LBB85_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v11 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v0, v7, v0, 16 +; GCN-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 offset:8 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v6f16_to_v6bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v6, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v7, v6 +; VI-NEXT: v_mov_b32_e32 v8, v6 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v9, v6 +; VI-NEXT: v_mov_b32_e32 v8, v5 +; VI-NEXT: v_mov_b32_e32 v7, v4 +; VI-NEXT: v_mov_b32_e32 v6, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx3 v[1:2], v[6:8] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v6f16_to_v6bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v6, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v7, v6 +; GFX9-NEXT: v_mov_b32_e32 v8, v6 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v9, v6 +; GFX9-NEXT: v_mov_b32_e32 v8, v5 +; GFX9-NEXT: v_mov_b32_e32 v7, v4 +; GFX9-NEXT: v_mov_b32_e32 v6, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx3 v[1:2], v[6:8], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v6f16_to_v6bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v6, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v7, v6 +; GFX11-NEXT: v_mov_b32_e32 v8, v6 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v9, v6 +; GFX11-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v7, v4 +; GFX11-NEXT: v_mov_b32_e32 v6, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b96 v[1:2], v[6:8], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <6 x half> %value to <6 x bfloat> + br label %end + +end: + %phi = phi <6 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <6 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v6i16_to_v6bf16(i32 %cond, ptr addrspace(1) %out, <6 x i16> %value) { +; GCN-LABEL: v_bitcast_v6i16_to_v6bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v10, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB86_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v8 +; GCN-NEXT: .LBB86_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v11 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v0, v7, v0, 16 +; GCN-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 offset:8 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v6i16_to_v6bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v6, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v7, v6 +; VI-NEXT: v_mov_b32_e32 v8, v6 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v9, v6 +; VI-NEXT: v_mov_b32_e32 v8, v5 +; VI-NEXT: v_mov_b32_e32 v7, v4 +; VI-NEXT: v_mov_b32_e32 v6, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx3 v[1:2], v[6:8] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v6i16_to_v6bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v6, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v7, v6 +; GFX9-NEXT: v_mov_b32_e32 v8, v6 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v9, v6 +; GFX9-NEXT: v_mov_b32_e32 v8, v5 +; GFX9-NEXT: v_mov_b32_e32 v7, v4 +; GFX9-NEXT: v_mov_b32_e32 v6, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx3 v[1:2], v[6:8], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v6i16_to_v6bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v6, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v7, v6 +; GFX11-NEXT: v_mov_b32_e32 v8, v6 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_mov_b32_e32 v9, v6 +; GFX11-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v7, v4 +; GFX11-NEXT: v_mov_b32_e32 v6, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b96 v[1:2], v[6:8], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <6 x i16> %value to <6 x bfloat> + br label %end + +end: + %phi = phi <6 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <6 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v12i8_to_v6bf16(i32 %cond, ptr addrspace(1) %out, <12 x i8> %value) { +; GCN-LABEL: v_bitcast_v12i8_to_v6bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v16, 0 +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: v_mov_b32_e32 v17, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB87_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 24, v4 +; GCN-NEXT: v_and_b32_e32 v4, 0xff, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 24, v6 +; GCN-NEXT: v_and_b32_e32 v6, 0xff, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 8, v8 +; GCN-NEXT: v_and_b32_e32 v8, 0xff, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 24, v10 +; GCN-NEXT: v_and_b32_e32 v10, 0xff, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 24, v12 +; GCN-NEXT: v_and_b32_e32 v12, 0xff, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 24, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_or_b32_e32 v6, v6, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v12 +; GCN-NEXT: v_or_b32_e32 v16, v3, v0 +; GCN-NEXT: v_or_b32_e32 v18, v5, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v6 +; GCN-NEXT: v_or_b32_e32 v19, v9, v7 +; GCN-NEXT: v_or_b32_e32 v0, v11, v8 +; GCN-NEXT: v_or_b32_e32 v15, v13, v10 +; GCN-NEXT: .LBB87_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v17 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v0, v7, v0, 16 +; GCN-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 offset:8 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v12i8_to_v6bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v15, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v16, v15 +; VI-NEXT: v_mov_b32_e32 v17, v15 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB87_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v4 +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v6 +; VI-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v15, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v8 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v10 +; VI-NEXT: v_or_b32_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v9, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v16, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v12 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v14 +; VI-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v13, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v17, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: .LBB87_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx3 v[1:2], v[15:17] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v12i8_to_v6bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v15, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v16, v15 +; GFX9-NEXT: v_mov_b32_e32 v17, v15 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB87_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v4 +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6 +; GFX9-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v15, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v8 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v10 +; GFX9-NEXT: v_or_b32_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v9, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v16, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v12 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v14 +; GFX9-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v13, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v17, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: .LBB87_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx3 v[1:2], v[15:17], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: v_bitcast_v12i8_to_v6bf16: +; GFX11-TRUE16: ; %bb.0: ; %entry +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v15, 0 +; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v16, v15 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, v15 +; GFX11-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB87_2 +; GFX11-TRUE16-NEXT: ; %bb.1: ; %if +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v4.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v7.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v8.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v9.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v10.l +; GFX11-TRUE16-NEXT: v_or_b16 v15.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v6.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v11.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v12.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v13.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v14.l +; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v17.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v17.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: .LBB87_2: ; %end +; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-TRUE16-NEXT: global_store_b96 v[1:2], v[15:17], off +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: v_bitcast_v12i8_to_v6bf16: +; GFX11-FAKE16: ; %bb.0: ; %entry +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v15, 0 +; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v16, v15 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v17, v15 +; GFX11-FAKE16-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB87_2 +; GFX11-FAKE16-NEXT: ; %bb.1: ; %if +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v6 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v10 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v12 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v12 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v0, v4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v3, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v6, v7 +; GFX11-FAKE16-NEXT: .LBB87_2: ; %end +; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-FAKE16-NEXT: global_store_b96 v[1:2], v[15:17], off +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <12 x i8> %value to <6 x bfloat> + br label %end + +end: + %phi = phi <6 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <6 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8bf16_to_v2f64(i32 %cond, ptr addrspace(1) %out, <8 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v8bf16_to_v2f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v12, v11 +; GCN-NEXT: v_mov_b32_e32 v13, v11 +; GCN-NEXT: v_mov_b32_e32 v14, v11 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB88_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_alignbit_b32 v11, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v12, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v13, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v14, v8, v9, 16 +; GCN-NEXT: .LBB88_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8bf16_to_v2f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8bf16_to_v2f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8bf16_to_v2f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x bfloat> %value to <2 x double> + br label %end + +end: + %phi = phi <2 x double> [zeroinitializer, %entry], [%cast, %if] + store <2 x double> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8bf16_to_v2i64(i32 %cond, ptr addrspace(1) %out, <8 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v8bf16_to_v2i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v12, v11 +; GCN-NEXT: v_mov_b32_e32 v13, v11 +; GCN-NEXT: v_mov_b32_e32 v14, v11 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB89_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_alignbit_b32 v11, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v12, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v13, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v14, v8, v9, 16 +; GCN-NEXT: .LBB89_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8bf16_to_v2i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8bf16_to_v2i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8bf16_to_v2i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x bfloat> %value to <2 x i64> + br label %end + +end: + %phi = phi <2 x i64> [zeroinitializer, %entry], [%cast, %if] + store <2 x i64> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8bf16_to_v4f32(i32 %cond, ptr addrspace(1) %out, <8 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v8bf16_to_v4f32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v12, v11 +; GCN-NEXT: v_mov_b32_e32 v13, v11 +; GCN-NEXT: v_mov_b32_e32 v14, v11 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB90_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_alignbit_b32 v11, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v12, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v13, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v14, v8, v9, 16 +; GCN-NEXT: .LBB90_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8bf16_to_v4f32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8bf16_to_v4f32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8bf16_to_v4f32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x bfloat> %value to <4 x float> + br label %end + +end: + %phi = phi <4 x float> [zeroinitializer, %entry], [%cast, %if] + store <4 x float> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8bf16_to_v4i32(i32 %cond, ptr addrspace(1) %out, <8 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v8bf16_to_v4i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v12, v11 +; GCN-NEXT: v_mov_b32_e32 v13, v11 +; GCN-NEXT: v_mov_b32_e32 v14, v11 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB91_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_alignbit_b32 v11, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v12, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v13, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v14, v8, v9, 16 +; GCN-NEXT: .LBB91_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8bf16_to_v4i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8bf16_to_v4i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8bf16_to_v4i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x bfloat> %value to <4 x i32> + br label %end + +end: + %phi = phi <4 x i32> [zeroinitializer, %entry], [%cast, %if] + store <4 x i32> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8bf16_to_v8f16(i32 %cond, ptr addrspace(1) %out, <8 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v8bf16_to_v8f16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v16, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v17, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB92_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v14, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v11, v4 +; GCN-NEXT: v_cvt_f32_f16_e32 v15, v5 +; GCN-NEXT: v_cvt_f32_f16_e32 v12, v6 +; GCN-NEXT: v_cvt_f32_f16_e32 v16, v7 +; GCN-NEXT: v_cvt_f32_f16_e32 v13, v8 +; GCN-NEXT: v_cvt_f32_f16_e32 v17, v9 +; GCN-NEXT: .LBB92_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v14 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v15 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v11 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v16 +; GCN-NEXT: v_cvt_f16_f32_e32 v7, v12 +; GCN-NEXT: v_cvt_f16_f32_e32 v8, v17 +; GCN-NEXT: v_cvt_f16_f32_e32 v9, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_or_b32_e32 v3, v0, v3 +; GCN-NEXT: v_or_b32_e32 v4, v5, v4 +; GCN-NEXT: v_or_b32_e32 v5, v7, v6 +; GCN-NEXT: v_or_b32_e32 v6, v9, v8 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8bf16_to_v8f16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8bf16_to_v8f16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8bf16_to_v8f16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x bfloat> %value to <8 x half> + br label %end + +end: + %phi = phi <8 x half> [zeroinitializer, %entry], [%cast, %if] + store <8 x half> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8bf16_to_v8i16(i32 %cond, ptr addrspace(1) %out, <8 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v8bf16_to_v8i16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v12, v11 +; GCN-NEXT: v_mov_b32_e32 v13, v11 +; GCN-NEXT: v_mov_b32_e32 v14, v11 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB93_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_alignbit_b32 v11, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v12, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v13, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v14, v8, v9, 16 +; GCN-NEXT: .LBB93_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8bf16_to_v8i16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8bf16_to_v8i16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8bf16_to_v8i16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x bfloat> %value to <8 x i16> + br label %end + +end: + %phi = phi <8 x i16> [zeroinitializer, %entry], [%cast, %if] + store <8 x i16> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8f16_to_v8bf16(i32 %cond, ptr addrspace(1) %out, <8 x half> %value) { +; GCN-LABEL: v_bitcast_v8f16_to_v8bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v16, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v17, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB94_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v4 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v5 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v6 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v7 +; GCN-NEXT: v_cvt_f16_f32_e32 v7, v8 +; GCN-NEXT: v_cvt_f16_f32_e32 v8, v9 +; GCN-NEXT: v_cvt_f16_f32_e32 v9, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v9 +; GCN-NEXT: .LBB94_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_alignbit_b32 v3, v3, v0, 16 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v5, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v6, v8, v9, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8f16_to_v8bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8f16_to_v8bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8f16_to_v8bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x half> %value to <8 x bfloat> + br label %end + +end: + %phi = phi <8 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <8 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8i16_to_v8bf16(i32 %cond, ptr addrspace(1) %out, <8 x i16> %value) { +; GCN-LABEL: v_bitcast_v8i16_to_v8bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v16, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v17, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB95_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v10 +; GCN-NEXT: .LBB95_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_alignbit_b32 v3, v3, v0, 16 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v5, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v6, v8, v9, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8i16_to_v8bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8i16_to_v8bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8i16_to_v8bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x i16> %value to <8 x bfloat> + br label %end + +end: + %phi = phi <8 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <8 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v16i8_to_v8bf16(i32 %cond, ptr addrspace(1) %out, <16 x i8> %value) { +; GCN-LABEL: v_bitcast_v16i8_to_v8bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB96_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 24, v4 +; GCN-NEXT: v_and_b32_e32 v4, 0xff, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 24, v6 +; GCN-NEXT: v_and_b32_e32 v6, 0xff, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 8, v8 +; GCN-NEXT: v_and_b32_e32 v8, 0xff, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 24, v10 +; GCN-NEXT: v_and_b32_e32 v10, 0xff, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 24, v12 +; GCN-NEXT: v_and_b32_e32 v12, 0xff, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 24, v14 +; GCN-NEXT: v_and_b32_e32 v14, 0xff, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 8, v16 +; GCN-NEXT: v_and_b32_e32 v16, 0xff, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v17, 24, v18 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_or_b32_e32 v6, v6, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v12 +; GCN-NEXT: v_or_b32_e32 v12, v14, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v16 +; GCN-NEXT: v_or_b32_e32 v0, v3, v0 +; GCN-NEXT: v_or_b32_e32 v22, v5, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v6 +; GCN-NEXT: v_or_b32_e32 v23, v9, v7 +; GCN-NEXT: v_or_b32_e32 v20, v11, v8 +; GCN-NEXT: v_or_b32_e32 v24, v13, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v12 +; GCN-NEXT: v_or_b32_e32 v25, v17, v14 +; GCN-NEXT: .LBB96_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v21 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_alignbit_b32 v3, v3, v0, 16 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v5, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v6, v8, v9, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v16i8_to_v8bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB96_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v4 +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v6 +; VI-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v19, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v8 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v10 +; VI-NEXT: v_or_b32_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v9, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v20, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v12 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v14 +; VI-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v13, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v21, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v16 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v18 +; VI-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v17, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v22, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: .LBB96_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v16i8_to_v8bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB96_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v4 +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6 +; GFX9-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v19, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v8 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v10 +; GFX9-NEXT: v_or_b32_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v9, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v20, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v12 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v14 +; GFX9-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v13, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v21, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v16 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v18 +; GFX9-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v17, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v22, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: .LBB96_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: v_bitcast_v16i8_to_v8bf16: +; GFX11-TRUE16: ; %bb.0: ; %entry +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_2 +; GFX11-TRUE16-NEXT: ; %bb.1: ; %if +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v4.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v6.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v7.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v8.l +; GFX11-TRUE16-NEXT: v_or_b16 v19.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v9.l +; GFX11-TRUE16-NEXT: v_or_b16 v19.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v10.l +; GFX11-TRUE16-NEXT: v_or_b16 v20.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v11.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v12.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v13.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v14.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v15.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v16.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v17.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v18.l +; GFX11-TRUE16-NEXT: v_or_b16 v20.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v21.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v21.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v22.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v22.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: .LBB96_2: ; %end +; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: v_bitcast_v16i8_to_v8bf16: +; GFX11-FAKE16: ; %bb.0: ; %entry +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-FAKE16-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB96_2 +; GFX11-FAKE16-NEXT: ; %bb.1: ; %if +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v6 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v10 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v14 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v16 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v18 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v14 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v6, v7 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v8, v9 +; GFX11-FAKE16-NEXT: .LBB96_2: ; %end +; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <16 x i8> %value to <8 x bfloat> + br label %end + +end: + %phi = phi <8 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <8 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v2i64_to_v8bf16(i32 %cond, ptr addrspace(1) %out, <2 x i64> %value) { +; GCN-LABEL: v_bitcast_v2i64_to_v8bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v10, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB97_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v6 +; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v5 +; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v4 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GCN-NEXT: .LBB97_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v9, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v7, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v2i64_to_v8bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v2i64_to_v8bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v2i64_to_v8bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x i64> %value to <8 x bfloat> + br label %end + +end: + %phi = phi <8 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <8 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v2f64_to_v8bf16(i32 %cond, ptr addrspace(1) %out, <2 x double> %value) { +; GCN-LABEL: v_bitcast_v2f64_to_v8bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v10, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB98_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v6 +; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v5 +; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v4 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GCN-NEXT: .LBB98_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v9, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v7, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v2f64_to_v8bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v2f64_to_v8bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v2f64_to_v8bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x double> %value to <8 x bfloat> + br label %end + +end: + %phi = phi <8 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <8 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4i32_to_v8bf16(i32 %cond, ptr addrspace(1) %out, <4 x i32> %value) { +; GCN-LABEL: v_bitcast_v4i32_to_v8bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v10, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB99_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v6 +; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v5 +; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v4 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GCN-NEXT: .LBB99_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v9, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v7, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4i32_to_v8bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4i32_to_v8bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4i32_to_v8bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x i32> %value to <8 x bfloat> + br label %end + +end: + %phi = phi <8 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <8 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4f32_to_v8bf16(i32 %cond, ptr addrspace(1) %out, <4 x float> %value) { +; GCN-LABEL: v_bitcast_v4f32_to_v8bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v10, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB100_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v6 +; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v5 +; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v4 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v3 +; GCN-NEXT: .LBB100_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v9, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v7, v0, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4f32_to_v8bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v10, v7 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v10, v6 +; VI-NEXT: v_mov_b32_e32 v9, v5 +; VI-NEXT: v_mov_b32_e32 v8, v4 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[7:10] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4f32_to_v8bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-NEXT: v_mov_b32_e32 v10, v7 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v10, v6 +; GFX9-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-NEXT: v_mov_b32_e32 v8, v4 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4f32_to_v8bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v7, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v8, v7 +; GFX11-NEXT: v_mov_b32_e32 v9, v7 +; GFX11-NEXT: v_mov_b32_e32 v10, v7 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5 +; GFX11-NEXT: v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: global_store_b128 v[1:2], v[7:10], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x float> %value to <8 x bfloat> + br label %end + +end: + %phi = phi <8 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <8 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v16bf16_to_v16i16(i32 %cond, ptr addrspace(1) %out, <16 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v16bf16_to_v16i16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v20, v19 +; GCN-NEXT: v_mov_b32_e32 v21, v19 +; GCN-NEXT: v_mov_b32_e32 v22, v19 +; GCN-NEXT: v_mov_b32_e32 v23, v19 +; GCN-NEXT: v_mov_b32_e32 v24, v19 +; GCN-NEXT: v_mov_b32_e32 v25, v19 +; GCN-NEXT: v_mov_b32_e32 v26, v19 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB101_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_alignbit_b32 v19, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v20, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v21, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v22, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v23, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v24, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v25, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v26, v16, v17, 16 +; GCN-NEXT: .LBB101_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[23:26], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[19:22], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v16bf16_to_v16i16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v16bf16_to_v16i16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v16bf16_to_v16i16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <16 x bfloat> %value to <16 x i16> + br label %end + +end: + %phi = phi <16 x i16> [zeroinitializer, %entry], [%cast, %if] + store <16 x i16> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v16bf16_to_v16f16(i32 %cond, ptr addrspace(1) %out, <16 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v16bf16_to_v16f16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v26, 0 +; GCN-NEXT: v_mov_b32_e32 v30, 0 +; GCN-NEXT: v_mov_b32_e32 v27, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v28, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v29, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB102_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_cvt_f32_f16_e32 v26, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v30, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v27, v4 +; GCN-NEXT: v_cvt_f32_f16_e32 v31, v5 +; GCN-NEXT: v_cvt_f32_f16_e32 v28, v6 +; GCN-NEXT: v_cvt_f32_f16_e32 v32, v7 +; GCN-NEXT: v_cvt_f32_f16_e32 v29, v8 +; GCN-NEXT: v_cvt_f32_f16_e32 v33, v9 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v10 +; GCN-NEXT: v_cvt_f32_f16_e32 v22, v11 +; GCN-NEXT: v_cvt_f32_f16_e32 v19, v12 +; GCN-NEXT: v_cvt_f32_f16_e32 v23, v13 +; GCN-NEXT: v_cvt_f32_f16_e32 v20, v14 +; GCN-NEXT: v_cvt_f32_f16_e32 v24, v15 +; GCN-NEXT: v_cvt_f32_f16_e32 v21, v16 +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v17 +; GCN-NEXT: .LBB102_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v30 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v26 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v31 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v27 +; GCN-NEXT: v_cvt_f16_f32_e32 v7, v32 +; GCN-NEXT: v_cvt_f16_f32_e32 v8, v28 +; GCN-NEXT: v_cvt_f16_f32_e32 v9, v33 +; GCN-NEXT: v_cvt_f16_f32_e32 v10, v29 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v11, v22 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v12, v23 +; GCN-NEXT: v_cvt_f16_f32_e32 v13, v19 +; GCN-NEXT: v_cvt_f16_f32_e32 v14, v24 +; GCN-NEXT: v_cvt_f16_f32_e32 v15, v20 +; GCN-NEXT: v_cvt_f16_f32_e32 v16, v25 +; GCN-NEXT: v_cvt_f16_f32_e32 v17, v21 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_or_b32_e32 v3, v4, v3 +; GCN-NEXT: v_or_b32_e32 v4, v6, v5 +; GCN-NEXT: v_or_b32_e32 v5, v8, v7 +; GCN-NEXT: v_or_b32_e32 v6, v10, v9 +; GCN-NEXT: v_or_b32_e32 v7, v0, v11 +; GCN-NEXT: v_or_b32_e32 v8, v13, v12 +; GCN-NEXT: v_or_b32_e32 v9, v15, v14 +; GCN-NEXT: v_or_b32_e32 v10, v17, v16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v16bf16_to_v16f16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v16bf16_to_v16f16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v16bf16_to_v16f16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <16 x bfloat> %value to <16 x half> + br label %end + +end: + %phi = phi <16 x half> [zeroinitializer, %entry], [%cast, %if] + store <16 x half> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v16bf16_to_v8i32(i32 %cond, ptr addrspace(1) %out, <16 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v16bf16_to_v8i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v20, v19 +; GCN-NEXT: v_mov_b32_e32 v21, v19 +; GCN-NEXT: v_mov_b32_e32 v22, v19 +; GCN-NEXT: v_mov_b32_e32 v23, v19 +; GCN-NEXT: v_mov_b32_e32 v24, v19 +; GCN-NEXT: v_mov_b32_e32 v25, v19 +; GCN-NEXT: v_mov_b32_e32 v26, v19 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB103_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_alignbit_b32 v19, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v20, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v21, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v22, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v23, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v24, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v25, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v26, v16, v17, 16 +; GCN-NEXT: .LBB103_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[23:26], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[19:22], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v16bf16_to_v8i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v16bf16_to_v8i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v16bf16_to_v8i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <16 x bfloat> %value to <8 x i32> + br label %end + +end: + %phi = phi <8 x i32> [zeroinitializer, %entry], [%cast, %if] + store <8 x i32> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v16bf16_to_v8f32(i32 %cond, ptr addrspace(1) %out, <16 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v16bf16_to_v8f32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v20, v19 +; GCN-NEXT: v_mov_b32_e32 v21, v19 +; GCN-NEXT: v_mov_b32_e32 v22, v19 +; GCN-NEXT: v_mov_b32_e32 v23, v19 +; GCN-NEXT: v_mov_b32_e32 v24, v19 +; GCN-NEXT: v_mov_b32_e32 v25, v19 +; GCN-NEXT: v_mov_b32_e32 v26, v19 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB104_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_alignbit_b32 v19, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v20, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v21, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v22, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v23, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v24, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v25, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v26, v16, v17, 16 +; GCN-NEXT: .LBB104_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[23:26], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[19:22], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v16bf16_to_v8f32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v16bf16_to_v8f32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v16bf16_to_v8f32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <16 x bfloat> %value to <8 x float> + br label %end + +end: + %phi = phi <8 x float> [zeroinitializer, %entry], [%cast, %if] + store <8 x float> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v16bf16_to_v4f64(i32 %cond, ptr addrspace(1) %out, <16 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v16bf16_to_v4f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v20, v19 +; GCN-NEXT: v_mov_b32_e32 v21, v19 +; GCN-NEXT: v_mov_b32_e32 v22, v19 +; GCN-NEXT: v_mov_b32_e32 v23, v19 +; GCN-NEXT: v_mov_b32_e32 v24, v19 +; GCN-NEXT: v_mov_b32_e32 v25, v19 +; GCN-NEXT: v_mov_b32_e32 v26, v19 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB105_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_alignbit_b32 v19, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v20, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v21, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v22, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v23, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v24, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v25, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v26, v16, v17, 16 +; GCN-NEXT: .LBB105_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[23:26], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[19:22], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v16bf16_to_v4f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v16bf16_to_v4f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v16bf16_to_v4f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <16 x bfloat> %value to <4 x double> + br label %end + +end: + %phi = phi <4 x double> [zeroinitializer, %entry], [%cast, %if] + store <4 x double> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v16bf16_to_v4i64(i32 %cond, ptr addrspace(1) %out, <16 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v16bf16_to_v4i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v20, v19 +; GCN-NEXT: v_mov_b32_e32 v21, v19 +; GCN-NEXT: v_mov_b32_e32 v22, v19 +; GCN-NEXT: v_mov_b32_e32 v23, v19 +; GCN-NEXT: v_mov_b32_e32 v24, v19 +; GCN-NEXT: v_mov_b32_e32 v25, v19 +; GCN-NEXT: v_mov_b32_e32 v26, v19 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB106_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_alignbit_b32 v19, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v20, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v21, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v22, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v23, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v24, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v25, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v26, v16, v17, 16 +; GCN-NEXT: .LBB106_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[23:26], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[19:22], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v16bf16_to_v4i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v16bf16_to_v4i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v16bf16_to_v4i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <16 x bfloat> %value to <4 x i64> + br label %end + +end: + %phi = phi <4 x i64> [zeroinitializer, %entry], [%cast, %if] + store <4 x i64> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v16bf16_to_v32i8(i32 %cond, ptr addrspace(1) %out, <16 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v16bf16_to_v32i8: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v20, v19 +; GCN-NEXT: v_mov_b32_e32 v21, v19 +; GCN-NEXT: v_mov_b32_e32 v22, v19 +; GCN-NEXT: v_mov_b32_e32 v23, v19 +; GCN-NEXT: v_mov_b32_e32 v24, v19 +; GCN-NEXT: v_mov_b32_e32 v25, v19 +; GCN-NEXT: v_mov_b32_e32 v26, v19 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB107_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_alignbit_b32 v19, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v20, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v21, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v22, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v23, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v24, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v25, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v26, v16, v17, 16 +; GCN-NEXT: .LBB107_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[23:26], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[19:22], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v16bf16_to_v32i8: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v16bf16_to_v32i8: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v16bf16_to_v32i8: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <16 x bfloat> %value to <32 x i8> + br label %end + +end: + %phi = phi <32 x i8> [zeroinitializer, %entry], [%cast, %if] + store <32 x i8> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8f32_to_v16bf16(i32 %cond, ptr addrspace(1) %out, <8 x float> %value) { +; GCN-LABEL: v_bitcast_v8f32_to_v16bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: v_mov_b32_e32 v16, 0 +; GCN-NEXT: v_mov_b32_e32 v17, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB108_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v10 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v9 +; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v8 +; GCN-NEXT: v_and_b32_e32 v17, 0xffff0000, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v7 +; GCN-NEXT: v_and_b32_e32 v19, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v6 +; GCN-NEXT: v_and_b32_e32 v21, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v5 +; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v4 +; GCN-NEXT: v_and_b32_e32 v25, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v3 +; GCN-NEXT: .LBB108_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v18 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v7, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v9, v10, 16 +; GCN-NEXT: v_alignbit_b32 v7, v17, v16, 16 +; GCN-NEXT: v_alignbit_b32 v8, v15, v14, 16 +; GCN-NEXT: v_alignbit_b32 v9, v13, v12, 16 +; GCN-NEXT: v_alignbit_b32 v10, v11, v0, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8f32_to_v16bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8f32_to_v16bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8f32_to_v16bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x float> %value to <16 x bfloat> + br label %end + +end: + %phi = phi <16 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <16 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8i32_to_v16bf16(i32 %cond, ptr addrspace(1) %out, <8 x i32> %value) { +; GCN-LABEL: v_bitcast_v8i32_to_v16bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: v_mov_b32_e32 v16, 0 +; GCN-NEXT: v_mov_b32_e32 v17, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB109_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v10 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v9 +; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v8 +; GCN-NEXT: v_and_b32_e32 v17, 0xffff0000, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v7 +; GCN-NEXT: v_and_b32_e32 v19, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v6 +; GCN-NEXT: v_and_b32_e32 v21, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v5 +; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v4 +; GCN-NEXT: v_and_b32_e32 v25, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v3 +; GCN-NEXT: .LBB109_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v18 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v7, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v9, v10, 16 +; GCN-NEXT: v_alignbit_b32 v7, v17, v16, 16 +; GCN-NEXT: v_alignbit_b32 v8, v15, v14, 16 +; GCN-NEXT: v_alignbit_b32 v9, v13, v12, 16 +; GCN-NEXT: v_alignbit_b32 v10, v11, v0, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8i32_to_v16bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8i32_to_v16bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8i32_to_v16bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x i32> %value to <16 x bfloat> + br label %end + +end: + %phi = phi <16 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <16 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4i64_to_v16bf16(i32 %cond, ptr addrspace(1) %out, <4 x i64> %value) { +; GCN-LABEL: v_bitcast_v4i64_to_v16bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: v_mov_b32_e32 v16, 0 +; GCN-NEXT: v_mov_b32_e32 v17, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB110_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v10 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v9 +; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v8 +; GCN-NEXT: v_and_b32_e32 v17, 0xffff0000, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v7 +; GCN-NEXT: v_and_b32_e32 v19, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v6 +; GCN-NEXT: v_and_b32_e32 v21, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v5 +; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v4 +; GCN-NEXT: v_and_b32_e32 v25, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v3 +; GCN-NEXT: .LBB110_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v18 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v7, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v9, v10, 16 +; GCN-NEXT: v_alignbit_b32 v7, v17, v16, 16 +; GCN-NEXT: v_alignbit_b32 v8, v15, v14, 16 +; GCN-NEXT: v_alignbit_b32 v9, v13, v12, 16 +; GCN-NEXT: v_alignbit_b32 v10, v11, v0, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4i64_to_v16bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4i64_to_v16bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4i64_to_v16bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x i64> %value to <16 x bfloat> + br label %end + +end: + %phi = phi <16 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <16 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v4f64_to_v16bf16(i32 %cond, ptr addrspace(1) %out, <4 x double> %value) { +; GCN-LABEL: v_bitcast_v4f64_to_v16bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: v_mov_b32_e32 v16, 0 +; GCN-NEXT: v_mov_b32_e32 v17, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB111_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v10 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v9 +; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v8 +; GCN-NEXT: v_and_b32_e32 v17, 0xffff0000, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v7 +; GCN-NEXT: v_and_b32_e32 v19, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v6 +; GCN-NEXT: v_and_b32_e32 v21, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v5 +; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v4 +; GCN-NEXT: v_and_b32_e32 v25, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v3 +; GCN-NEXT: .LBB111_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v18 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v7, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v9, v10, 16 +; GCN-NEXT: v_alignbit_b32 v7, v17, v16, 16 +; GCN-NEXT: v_alignbit_b32 v8, v15, v14, 16 +; GCN-NEXT: v_alignbit_b32 v9, v13, v12, 16 +; GCN-NEXT: v_alignbit_b32 v10, v11, v0, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v4f64_to_v16bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v11, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v12, v11 +; VI-NEXT: v_mov_b32_e32 v13, v11 +; VI-NEXT: v_mov_b32_e32 v14, v11 +; VI-NEXT: v_mov_b32_e32 v15, v11 +; VI-NEXT: v_mov_b32_e32 v16, v11 +; VI-NEXT: v_mov_b32_e32 v17, v11 +; VI-NEXT: v_mov_b32_e32 v18, v11 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v18, v10 +; VI-NEXT: v_mov_b32_e32 v17, v9 +; VI-NEXT: v_mov_b32_e32 v16, v8 +; VI-NEXT: v_mov_b32_e32 v15, v7 +; VI-NEXT: v_mov_b32_e32 v14, v6 +; VI-NEXT: v_mov_b32_e32 v13, v5 +; VI-NEXT: v_mov_b32_e32 v12, v4 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: ; %bb.2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[15:18] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[11:14] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v4f64_to_v16bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v11, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-NEXT: v_mov_b32_e32 v14, v11 +; GFX9-NEXT: v_mov_b32_e32 v15, v11 +; GFX9-NEXT: v_mov_b32_e32 v16, v11 +; GFX9-NEXT: v_mov_b32_e32 v17, v11 +; GFX9-NEXT: v_mov_b32_e32 v18, v11 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v18, v10 +; GFX9-NEXT: v_mov_b32_e32 v17, v9 +; GFX9-NEXT: v_mov_b32_e32 v16, v8 +; GFX9-NEXT: v_mov_b32_e32 v15, v7 +; GFX9-NEXT: v_mov_b32_e32 v14, v6 +; GFX9-NEXT: v_mov_b32_e32 v13, v5 +; GFX9-NEXT: v_mov_b32_e32 v12, v4 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: ; %bb.2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v4f64_to_v16bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v11, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v12, v11 +; GFX11-NEXT: v_mov_b32_e32 v13, v11 +; GFX11-NEXT: v_mov_b32_e32 v14, v11 +; GFX11-NEXT: v_mov_b32_e32 v15, v11 +; GFX11-NEXT: v_mov_b32_e32 v16, v11 +; GFX11-NEXT: v_mov_b32_e32 v17, v11 +; GFX11-NEXT: v_mov_b32_e32 v18, v11 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v18, v10 :: v_dual_mov_b32 v17, v9 +; GFX11-NEXT: v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7 +; GFX11-NEXT: v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5 +; GFX11-NEXT: v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v11, v3 +; GFX11-NEXT: ; %bb.2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[1:2], v[15:18], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[11:14], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <4 x double> %value to <16 x bfloat> + br label %end + +end: + %phi = phi <16 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <16 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32i8_to_v16bf16(i32 %cond, ptr addrspace(1) %out, <32 x i8> %value) { +; GCN-LABEL: v_bitcast_v32i8_to_v16bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v49, off, s[0:3], s32 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB112_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 24, v4 +; GCN-NEXT: v_and_b32_e32 v5, 0xff, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; GCN-NEXT: v_and_b32_e32 v7, 0xff, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 8, v8 +; GCN-NEXT: v_and_b32_e32 v9, 0xff, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 24, v10 +; GCN-NEXT: v_and_b32_e32 v11, 0xff, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 24, v12 +; GCN-NEXT: v_and_b32_e32 v13, 0xff, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 24, v14 +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 8, v16 +; GCN-NEXT: v_and_b32_e32 v17, 0xff, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v18, 24, v18 +; GCN-NEXT: v_and_b32_e32 v19, 0xff, v19 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 24, v20 +; GCN-NEXT: v_and_b32_e32 v21, 0xff, v21 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 24, v22 +; GCN-NEXT: v_and_b32_e32 v23, 0xff, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 8, v24 +; GCN-NEXT: v_and_b32_e32 v25, 0xff, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v26, 24, v26 +; GCN-NEXT: v_and_b32_e32 v27, 0xff, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v28, 24, v28 +; GCN-NEXT: v_and_b32_e32 v29, 0xff, v29 +; GCN-NEXT: v_lshlrev_b32_e32 v30, 24, v30 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v32, 0xff, v49 +; GCN-NEXT: v_lshlrev_b32_e32 v33, 8, v36 +; GCN-NEXT: v_and_b32_e32 v31, 0xff, v31 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 24, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_or_b32_e32 v7, v7, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v13 +; GCN-NEXT: v_or_b32_e32 v13, v15, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v19 +; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v21 +; GCN-NEXT: v_or_b32_e32 v19, v23, v24 +; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v29 +; GCN-NEXT: v_or_b32_e32 v25, v32, v33 +; GCN-NEXT: v_lshlrev_b32_e32 v27, 16, v31 +; GCN-NEXT: v_or_b32_e32 v50, v4, v3 +; GCN-NEXT: v_or_b32_e32 v54, v6, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v51, 16, v7 +; GCN-NEXT: v_or_b32_e32 v55, v10, v8 +; GCN-NEXT: v_or_b32_e32 v52, v12, v9 +; GCN-NEXT: v_or_b32_e32 v40, v14, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v53, 16, v13 +; GCN-NEXT: v_or_b32_e32 v41, v18, v15 +; GCN-NEXT: v_or_b32_e32 v32, v20, v16 +; GCN-NEXT: v_or_b32_e32 v37, v22, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v33, 16, v19 +; GCN-NEXT: v_or_b32_e32 v38, v26, v21 +; GCN-NEXT: v_or_b32_e32 v34, v28, v23 +; GCN-NEXT: v_or_b32_e32 v39, v30, v24 +; GCN-NEXT: v_lshlrev_b32_e32 v35, 16, v25 +; GCN-NEXT: v_or_b32_e32 v48, v0, v27 +; GCN-NEXT: .LBB112_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v54 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v50 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v55 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v51 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v52 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v53 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v37 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v32 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v38 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v33 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v39 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v34 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v48 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v35 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v5, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v6, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v7, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v8, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v9, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v10, v16, v17, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32i8_to_v16bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_ushort v49, off, s[0:3], s32 +; VI-NEXT: v_mov_b32_e32 v31, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v32, v31 +; VI-NEXT: v_mov_b32_e32 v33, v31 +; VI-NEXT: v_mov_b32_e32 v34, v31 +; VI-NEXT: v_mov_b32_e32 v35, v31 +; VI-NEXT: v_mov_b32_e32 v36, v31 +; VI-NEXT: v_mov_b32_e32 v37, v31 +; VI-NEXT: v_mov_b32_e32 v38, v31 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB112_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v4 +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v6 +; VI-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v31, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v8 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v10 +; VI-NEXT: v_or_b32_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v9, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v32, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v12 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v14 +; VI-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v13, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v33, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v16 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v18 +; VI-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v17, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v34, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v20 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v22 +; VI-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v21, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v35, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v24 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v26 +; VI-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v25, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v36, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v28 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v30 +; VI-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v29, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v37, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v50 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v48 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_sdwa v0, v49, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v38, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: .LBB112_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[35:38] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[31:34] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32i8_to_v16bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 +; GFX9-NEXT: v_mov_b32_e32 v31, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v32, v31 +; GFX9-NEXT: v_mov_b32_e32 v33, v31 +; GFX9-NEXT: v_mov_b32_e32 v34, v31 +; GFX9-NEXT: v_mov_b32_e32 v35, v31 +; GFX9-NEXT: v_mov_b32_e32 v36, v31 +; GFX9-NEXT: v_mov_b32_e32 v37, v31 +; GFX9-NEXT: v_mov_b32_e32 v38, v31 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB112_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v4 +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6 +; GFX9-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 +; GFX9-NEXT: v_perm_b32 v31, v3, v0, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v8 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v10 +; GFX9-NEXT: v_or_b32_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v9, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v32, v3, v0, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v12 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v14 +; GFX9-NEXT: v_or_b32_sdwa v0, v11, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v13, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v33, v3, v0, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v16 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v18 +; GFX9-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v17, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v34, v3, v0, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v20 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v22 +; GFX9-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v21, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v35, v3, v0, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v24 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v26 +; GFX9-NEXT: v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v25, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v36, v3, v0, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v28 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v30 +; GFX9-NEXT: v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v29, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v37, v3, v0, s6 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v50 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v48 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_or_b32_sdwa v0, v49, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v38, v3, v0, s6 +; GFX9-NEXT: .LBB112_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[35:38], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: v_bitcast_v32i8_to_v16bf16: +; GFX11-TRUE16: ; %bb.0: ; %entry +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_clause 0x3 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:12 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:8 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:4 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v31, 0 +; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v32, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v33, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v34, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v35, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v36, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v37, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v38, v31 +; GFX11-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB112_2 +; GFX11-TRUE16-NEXT: ; %bb.1: ; %if +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v4.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v7.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v8.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v9.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v10.l +; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v6.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v11.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v12.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v13.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v14.l +; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v32.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v33.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v33.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v15.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v16.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v17.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v18.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v19.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v20.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v21.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v22.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v23.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v24.l +; GFX11-TRUE16-NEXT: v_or_b16 v34.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v34.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v35.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v35.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v36.l, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v25.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v26.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v27.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v28.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v29.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v30.l +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v48.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v48.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v39.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v39.l +; GFX11-TRUE16-NEXT: v_or_b16 v36.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v37.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v37.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v38.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v38.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: .LBB112_2: ; %end +; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-TRUE16-NEXT: s_clause 0x1 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[35:38], off offset:16 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[31:34], off +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: v_bitcast_v32i8_to_v16bf16: +; GFX11-FAKE16: ; %bb.0: ; %entry +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_clause 0x3 +; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:12 +; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:8 +; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:4 +; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v31, 0 +; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v32, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v33, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v34, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v35, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v36, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v37, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v38, v31 +; GFX11-FAKE16-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB112_2 +; GFX11-FAKE16-NEXT: ; %bb.1: ; %if +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v6 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v10 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v12 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v12 +; GFX11-FAKE16-NEXT: v_perm_b32 v31, v4, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v15 +; GFX11-FAKE16-NEXT: v_perm_b32 v32, v5, v3, 0x5040100 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v33, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v18 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v20 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v21 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v22 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v23 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v24 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v26 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v28 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v29 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v30 +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v50 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v49 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v48 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v39 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v34, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v35, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v36, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v37, v9, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v38, v11, v10, 0x5040100 +; GFX11-FAKE16-NEXT: .LBB112_2: ; %end +; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-FAKE16-NEXT: s_clause 0x1 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[35:38], off offset:16 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[31:34], off +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x i8> %value to <16 x bfloat> + br label %end + +end: + %phi = phi <16 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <16 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32bf16_to_v8i64(i32 %cond, ptr addrspace(1) %out, <32 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v32bf16_to_v8i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(2) +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:8 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v32, v31 +; GCN-NEXT: v_mov_b32_e32 v33, v31 +; GCN-NEXT: v_mov_b32_e32 v34, v31 +; GCN-NEXT: v_mov_b32_e32 v35, v31 +; GCN-NEXT: v_mov_b32_e32 v36, v31 +; GCN-NEXT: v_mov_b32_e32 v37, v31 +; GCN-NEXT: v_mov_b32_e32 v38, v31 +; GCN-NEXT: v_mov_b32_e32 v48, v31 +; GCN-NEXT: v_mov_b32_e32 v49, v31 +; GCN-NEXT: v_mov_b32_e32 v50, v31 +; GCN-NEXT: v_mov_b32_e32 v51, v31 +; GCN-NEXT: v_mov_b32_e32 v52, v31 +; GCN-NEXT: v_mov_b32_e32 v53, v31 +; GCN-NEXT: v_mov_b32_e32 v54, v31 +; GCN-NEXT: v_mov_b32_e32 v55, v31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB113_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v42 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v31 +; GCN-NEXT: v_alignbit_b32 v31, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v32, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v33, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v34, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v35, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v36, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v37, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v38, v16, v17, 16 +; GCN-NEXT: v_alignbit_b32 v48, v18, v19, 16 +; GCN-NEXT: v_alignbit_b32 v49, v20, v21, 16 +; GCN-NEXT: v_alignbit_b32 v50, v22, v23, 16 +; GCN-NEXT: v_alignbit_b32 v51, v24, v25, 16 +; GCN-NEXT: v_alignbit_b32 v52, v26, v27, 16 +; GCN-NEXT: v_alignbit_b32 v53, v28, v29, 16 +; GCN-NEXT: v_alignbit_b32 v54, v30, v54, 16 +; GCN-NEXT: v_alignbit_b32 v55, v55, v39, 16 +; GCN-NEXT: .LBB113_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[52:55], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[48:51], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[35:38], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[31:34], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32bf16_to_v8i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB113_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB113_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32bf16_to_v8i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB113_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB113_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32bf16_to_v8i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB113_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB113_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x bfloat> %value to <8 x i64> + br label %end + +end: + %phi = phi <8 x i64> [zeroinitializer, %entry], [%cast, %if] + store <8 x i64> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32bf16_to_v8f64(i32 %cond, ptr addrspace(1) %out, <32 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v32bf16_to_v8f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(2) +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:8 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v32, v31 +; GCN-NEXT: v_mov_b32_e32 v33, v31 +; GCN-NEXT: v_mov_b32_e32 v34, v31 +; GCN-NEXT: v_mov_b32_e32 v35, v31 +; GCN-NEXT: v_mov_b32_e32 v36, v31 +; GCN-NEXT: v_mov_b32_e32 v37, v31 +; GCN-NEXT: v_mov_b32_e32 v38, v31 +; GCN-NEXT: v_mov_b32_e32 v48, v31 +; GCN-NEXT: v_mov_b32_e32 v49, v31 +; GCN-NEXT: v_mov_b32_e32 v50, v31 +; GCN-NEXT: v_mov_b32_e32 v51, v31 +; GCN-NEXT: v_mov_b32_e32 v52, v31 +; GCN-NEXT: v_mov_b32_e32 v53, v31 +; GCN-NEXT: v_mov_b32_e32 v54, v31 +; GCN-NEXT: v_mov_b32_e32 v55, v31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB114_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v42 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v31 +; GCN-NEXT: v_alignbit_b32 v31, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v32, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v33, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v34, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v35, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v36, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v37, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v38, v16, v17, 16 +; GCN-NEXT: v_alignbit_b32 v48, v18, v19, 16 +; GCN-NEXT: v_alignbit_b32 v49, v20, v21, 16 +; GCN-NEXT: v_alignbit_b32 v50, v22, v23, 16 +; GCN-NEXT: v_alignbit_b32 v51, v24, v25, 16 +; GCN-NEXT: v_alignbit_b32 v52, v26, v27, 16 +; GCN-NEXT: v_alignbit_b32 v53, v28, v29, 16 +; GCN-NEXT: v_alignbit_b32 v54, v30, v54, 16 +; GCN-NEXT: v_alignbit_b32 v55, v55, v39, 16 +; GCN-NEXT: .LBB114_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[52:55], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[48:51], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[35:38], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[31:34], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32bf16_to_v8f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB114_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB114_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32bf16_to_v8f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB114_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB114_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32bf16_to_v8f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB114_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB114_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x bfloat> %value to <8 x double> + br label %end + +end: + %phi = phi <8 x double> [zeroinitializer, %entry], [%cast, %if] + store <8 x double> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32bf16_to_v16i32(i32 %cond, ptr addrspace(1) %out, <32 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v32bf16_to_v16i32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(2) +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:8 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v32, v31 +; GCN-NEXT: v_mov_b32_e32 v33, v31 +; GCN-NEXT: v_mov_b32_e32 v34, v31 +; GCN-NEXT: v_mov_b32_e32 v35, v31 +; GCN-NEXT: v_mov_b32_e32 v36, v31 +; GCN-NEXT: v_mov_b32_e32 v37, v31 +; GCN-NEXT: v_mov_b32_e32 v38, v31 +; GCN-NEXT: v_mov_b32_e32 v48, v31 +; GCN-NEXT: v_mov_b32_e32 v49, v31 +; GCN-NEXT: v_mov_b32_e32 v50, v31 +; GCN-NEXT: v_mov_b32_e32 v51, v31 +; GCN-NEXT: v_mov_b32_e32 v52, v31 +; GCN-NEXT: v_mov_b32_e32 v53, v31 +; GCN-NEXT: v_mov_b32_e32 v54, v31 +; GCN-NEXT: v_mov_b32_e32 v55, v31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB115_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v42 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v31 +; GCN-NEXT: v_alignbit_b32 v31, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v32, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v33, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v34, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v35, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v36, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v37, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v38, v16, v17, 16 +; GCN-NEXT: v_alignbit_b32 v48, v18, v19, 16 +; GCN-NEXT: v_alignbit_b32 v49, v20, v21, 16 +; GCN-NEXT: v_alignbit_b32 v50, v22, v23, 16 +; GCN-NEXT: v_alignbit_b32 v51, v24, v25, 16 +; GCN-NEXT: v_alignbit_b32 v52, v26, v27, 16 +; GCN-NEXT: v_alignbit_b32 v53, v28, v29, 16 +; GCN-NEXT: v_alignbit_b32 v54, v30, v54, 16 +; GCN-NEXT: v_alignbit_b32 v55, v55, v39, 16 +; GCN-NEXT: .LBB115_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[52:55], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[48:51], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[35:38], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[31:34], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32bf16_to_v16i32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB115_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB115_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32bf16_to_v16i32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB115_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB115_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32bf16_to_v16i32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB115_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB115_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x bfloat> %value to <16 x i32> + br label %end + +end: + %phi = phi <16 x i32> [zeroinitializer, %entry], [%cast, %if] + store <16 x i32> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32bf16_to_v16f32(i32 %cond, ptr addrspace(1) %out, <32 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v32bf16_to_v16f32: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(2) +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:8 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v32, v31 +; GCN-NEXT: v_mov_b32_e32 v33, v31 +; GCN-NEXT: v_mov_b32_e32 v34, v31 +; GCN-NEXT: v_mov_b32_e32 v35, v31 +; GCN-NEXT: v_mov_b32_e32 v36, v31 +; GCN-NEXT: v_mov_b32_e32 v37, v31 +; GCN-NEXT: v_mov_b32_e32 v38, v31 +; GCN-NEXT: v_mov_b32_e32 v48, v31 +; GCN-NEXT: v_mov_b32_e32 v49, v31 +; GCN-NEXT: v_mov_b32_e32 v50, v31 +; GCN-NEXT: v_mov_b32_e32 v51, v31 +; GCN-NEXT: v_mov_b32_e32 v52, v31 +; GCN-NEXT: v_mov_b32_e32 v53, v31 +; GCN-NEXT: v_mov_b32_e32 v54, v31 +; GCN-NEXT: v_mov_b32_e32 v55, v31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB116_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v42 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v31 +; GCN-NEXT: v_alignbit_b32 v31, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v32, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v33, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v34, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v35, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v36, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v37, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v38, v16, v17, 16 +; GCN-NEXT: v_alignbit_b32 v48, v18, v19, 16 +; GCN-NEXT: v_alignbit_b32 v49, v20, v21, 16 +; GCN-NEXT: v_alignbit_b32 v50, v22, v23, 16 +; GCN-NEXT: v_alignbit_b32 v51, v24, v25, 16 +; GCN-NEXT: v_alignbit_b32 v52, v26, v27, 16 +; GCN-NEXT: v_alignbit_b32 v53, v28, v29, 16 +; GCN-NEXT: v_alignbit_b32 v54, v30, v54, 16 +; GCN-NEXT: v_alignbit_b32 v55, v55, v39, 16 +; GCN-NEXT: .LBB116_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[52:55], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[48:51], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[35:38], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[31:34], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32bf16_to_v16f32: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB116_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB116_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32bf16_to_v16f32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB116_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB116_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32bf16_to_v16f32: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB116_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB116_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x bfloat> %value to <16 x float> + br label %end + +end: + %phi = phi <16 x float> [zeroinitializer, %entry], [%cast, %if] + store <16 x float> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32bf16_to_v32f16(i32 %cond, ptr addrspace(1) %out, <32 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v32bf16_to_v32f16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 +; GCN-NEXT: v_mov_b32_e32 v46, 0 +; GCN-NEXT: v_mov_b32_e32 v59, 0 +; GCN-NEXT: v_mov_b32_e32 v47, 0 +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: v_mov_b32_e32 v56, 0 +; GCN-NEXT: v_mov_b32_e32 v61, 0 +; GCN-NEXT: v_mov_b32_e32 v57, 0 +; GCN-NEXT: v_mov_b32_e32 v62, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v42, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v43, 0 +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: v_mov_b32_e32 v44, 0 +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v45, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB117_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v28 +; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v28 +; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v31 +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v32, 1.0, v58 +; GCN-NEXT: v_mul_f32_e32 v33, 1.0, v63 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v35, 16, v31 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v36, 16, v32 +; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GCN-NEXT: v_cvt_f32_f16_e32 v46, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v59, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v47, v4 +; GCN-NEXT: v_cvt_f32_f16_e32 v60, v5 +; GCN-NEXT: v_cvt_f32_f16_e32 v56, v6 +; GCN-NEXT: v_cvt_f32_f16_e32 v61, v7 +; GCN-NEXT: v_cvt_f32_f16_e32 v57, v8 +; GCN-NEXT: v_cvt_f32_f16_e32 v62, v9 +; GCN-NEXT: v_cvt_f32_f16_e32 v54, v10 +; GCN-NEXT: v_cvt_f32_f16_e32 v42, v11 +; GCN-NEXT: v_cvt_f32_f16_e32 v55, v12 +; GCN-NEXT: v_cvt_f32_f16_e32 v43, v13 +; GCN-NEXT: v_cvt_f32_f16_e32 v40, v14 +; GCN-NEXT: v_cvt_f32_f16_e32 v44, v15 +; GCN-NEXT: v_cvt_f32_f16_e32 v41, v16 +; GCN-NEXT: v_cvt_f32_f16_e32 v45, v17 +; GCN-NEXT: v_cvt_f32_f16_e32 v38, v18 +; GCN-NEXT: v_cvt_f32_f16_e32 v50, v19 +; GCN-NEXT: v_cvt_f32_f16_e32 v39, v20 +; GCN-NEXT: v_cvt_f32_f16_e32 v51, v21 +; GCN-NEXT: v_cvt_f32_f16_e32 v48, v22 +; GCN-NEXT: v_cvt_f32_f16_e32 v52, v23 +; GCN-NEXT: v_cvt_f32_f16_e32 v49, v24 +; GCN-NEXT: v_cvt_f32_f16_e32 v53, v25 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v26 +; GCN-NEXT: v_cvt_f32_f16_e32 v34, v27 +; GCN-NEXT: v_cvt_f32_f16_e32 v31, v28 +; GCN-NEXT: v_cvt_f32_f16_e32 v35, v35 +; GCN-NEXT: v_cvt_f32_f16_e32 v32, v30 +; GCN-NEXT: v_cvt_f32_f16_e32 v36, v36 +; GCN-NEXT: v_cvt_f32_f16_e32 v33, v33 +; GCN-NEXT: v_cvt_f32_f16_e32 v37, v29 +; GCN-NEXT: .LBB117_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v59 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v46 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v60 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v47 +; GCN-NEXT: v_cvt_f16_f32_e32 v7, v61 +; GCN-NEXT: v_cvt_f16_f32_e32 v8, v56 +; GCN-NEXT: v_cvt_f16_f32_e32 v9, v62 +; GCN-NEXT: v_cvt_f16_f32_e32 v10, v57 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_cvt_f16_f32_e32 v11, v42 +; GCN-NEXT: v_cvt_f16_f32_e32 v12, v54 +; GCN-NEXT: v_cvt_f16_f32_e32 v13, v43 +; GCN-NEXT: v_cvt_f16_f32_e32 v14, v55 +; GCN-NEXT: v_cvt_f16_f32_e32 v15, v44 +; GCN-NEXT: v_cvt_f16_f32_e32 v16, v40 +; GCN-NEXT: v_cvt_f16_f32_e32 v17, v45 +; GCN-NEXT: v_cvt_f16_f32_e32 v18, v41 +; GCN-NEXT: v_cvt_f16_f32_e32 v19, v50 +; GCN-NEXT: v_cvt_f16_f32_e32 v20, v38 +; GCN-NEXT: v_cvt_f16_f32_e32 v21, v51 +; GCN-NEXT: v_cvt_f16_f32_e32 v22, v39 +; GCN-NEXT: v_cvt_f16_f32_e32 v23, v52 +; GCN-NEXT: v_cvt_f16_f32_e32 v24, v48 +; GCN-NEXT: v_cvt_f16_f32_e32 v25, v53 +; GCN-NEXT: v_cvt_f16_f32_e32 v26, v49 +; GCN-NEXT: v_cvt_f16_f32_e32 v27, v34 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v28, v35 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_cvt_f16_f32_e32 v29, v31 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v30, v36 +; GCN-NEXT: v_cvt_f16_f32_e32 v31, v32 +; GCN-NEXT: v_cvt_f16_f32_e32 v32, v37 +; GCN-NEXT: v_cvt_f16_f32_e32 v33, v33 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v32 +; GCN-NEXT: v_or_b32_e32 v3, v4, v3 +; GCN-NEXT: v_or_b32_e32 v4, v6, v5 +; GCN-NEXT: v_or_b32_e32 v5, v8, v7 +; GCN-NEXT: v_or_b32_e32 v6, v10, v9 +; GCN-NEXT: v_or_b32_e32 v7, v12, v11 +; GCN-NEXT: v_or_b32_e32 v8, v14, v13 +; GCN-NEXT: v_or_b32_e32 v9, v16, v15 +; GCN-NEXT: v_or_b32_e32 v10, v18, v17 +; GCN-NEXT: v_or_b32_e32 v11, v20, v19 +; GCN-NEXT: v_or_b32_e32 v12, v22, v21 +; GCN-NEXT: v_or_b32_e32 v13, v24, v23 +; GCN-NEXT: v_or_b32_e32 v14, v26, v25 +; GCN-NEXT: v_or_b32_e32 v15, v0, v27 +; GCN-NEXT: v_or_b32_e32 v16, v29, v28 +; GCN-NEXT: v_or_b32_e32 v17, v31, v30 +; GCN-NEXT: v_or_b32_e32 v18, v33, v32 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[15:18], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32bf16_to_v32f16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB117_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB117_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32bf16_to_v32f16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB117_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB117_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32bf16_to_v32f16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB117_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB117_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x bfloat> %value to <32 x half> + br label %end + +end: + %phi = phi <32 x half> [zeroinitializer, %entry], [%cast, %if] + store <32 x half> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32bf16_to_v32i16(i32 %cond, ptr addrspace(1) %out, <32 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v32bf16_to_v32i16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(2) +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:8 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v32, v31 +; GCN-NEXT: v_mov_b32_e32 v33, v31 +; GCN-NEXT: v_mov_b32_e32 v34, v31 +; GCN-NEXT: v_mov_b32_e32 v35, v31 +; GCN-NEXT: v_mov_b32_e32 v36, v31 +; GCN-NEXT: v_mov_b32_e32 v37, v31 +; GCN-NEXT: v_mov_b32_e32 v38, v31 +; GCN-NEXT: v_mov_b32_e32 v48, v31 +; GCN-NEXT: v_mov_b32_e32 v49, v31 +; GCN-NEXT: v_mov_b32_e32 v50, v31 +; GCN-NEXT: v_mov_b32_e32 v51, v31 +; GCN-NEXT: v_mov_b32_e32 v52, v31 +; GCN-NEXT: v_mov_b32_e32 v53, v31 +; GCN-NEXT: v_mov_b32_e32 v54, v31 +; GCN-NEXT: v_mov_b32_e32 v55, v31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB118_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v42 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v31 +; GCN-NEXT: v_alignbit_b32 v31, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v32, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v33, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v34, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v35, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v36, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v37, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v38, v16, v17, 16 +; GCN-NEXT: v_alignbit_b32 v48, v18, v19, 16 +; GCN-NEXT: v_alignbit_b32 v49, v20, v21, 16 +; GCN-NEXT: v_alignbit_b32 v50, v22, v23, 16 +; GCN-NEXT: v_alignbit_b32 v51, v24, v25, 16 +; GCN-NEXT: v_alignbit_b32 v52, v26, v27, 16 +; GCN-NEXT: v_alignbit_b32 v53, v28, v29, 16 +; GCN-NEXT: v_alignbit_b32 v54, v30, v54, 16 +; GCN-NEXT: v_alignbit_b32 v55, v55, v39, 16 +; GCN-NEXT: .LBB118_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[52:55], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[48:51], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[35:38], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[31:34], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32bf16_to_v32i16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB118_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB118_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32bf16_to_v32i16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB118_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB118_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32bf16_to_v32i16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB118_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB118_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x bfloat> %value to <32 x i16> + br label %end + +end: + %phi = phi <32 x i16> [zeroinitializer, %entry], [%cast, %if] + store <32 x i16> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32bf16_to_v64i8(i32 %cond, ptr addrspace(1) %out, <32 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v32bf16_to_v64i8: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(2) +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:8 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v32, v31 +; GCN-NEXT: v_mov_b32_e32 v33, v31 +; GCN-NEXT: v_mov_b32_e32 v34, v31 +; GCN-NEXT: v_mov_b32_e32 v35, v31 +; GCN-NEXT: v_mov_b32_e32 v36, v31 +; GCN-NEXT: v_mov_b32_e32 v37, v31 +; GCN-NEXT: v_mov_b32_e32 v38, v31 +; GCN-NEXT: v_mov_b32_e32 v48, v31 +; GCN-NEXT: v_mov_b32_e32 v49, v31 +; GCN-NEXT: v_mov_b32_e32 v50, v31 +; GCN-NEXT: v_mov_b32_e32 v51, v31 +; GCN-NEXT: v_mov_b32_e32 v52, v31 +; GCN-NEXT: v_mov_b32_e32 v53, v31 +; GCN-NEXT: v_mov_b32_e32 v54, v31 +; GCN-NEXT: v_mov_b32_e32 v55, v31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB119_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v42 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v31 +; GCN-NEXT: v_alignbit_b32 v31, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v32, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v33, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v34, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v35, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v36, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v37, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v38, v16, v17, 16 +; GCN-NEXT: v_alignbit_b32 v48, v18, v19, 16 +; GCN-NEXT: v_alignbit_b32 v49, v20, v21, 16 +; GCN-NEXT: v_alignbit_b32 v50, v22, v23, 16 +; GCN-NEXT: v_alignbit_b32 v51, v24, v25, 16 +; GCN-NEXT: v_alignbit_b32 v52, v26, v27, 16 +; GCN-NEXT: v_alignbit_b32 v53, v28, v29, 16 +; GCN-NEXT: v_alignbit_b32 v54, v30, v54, 16 +; GCN-NEXT: v_alignbit_b32 v55, v55, v39, 16 +; GCN-NEXT: .LBB119_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[52:55], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[48:51], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[35:38], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[31:34], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(5) +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32bf16_to_v64i8: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB119_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB119_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32bf16_to_v64i8: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB119_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB119_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32bf16_to_v64i8: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB119_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB119_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x bfloat> %value to <64 x i8> + br label %end + +end: + %phi = phi <64 x i8> [zeroinitializer, %entry], [%cast, %if] + store <64 x i8> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v64i8_to_v32bf16(i32 %cond, ptr addrspace(1) %out, <64 x i8> %value) { +; GCN-LABEL: v_bitcast_v64i8_to_v32bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:136 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:128 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:120 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:112 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:104 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:100 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:96 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:92 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:88 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:80 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:72 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:68 +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:64 +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:60 +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:56 +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:52 +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:48 +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:44 +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:40 +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:36 +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:32 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:28 +; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:24 +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 +; GCN-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:16 +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: v_mov_b32_e32 v27, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v26, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v63, 0 +; GCN-NEXT: v_mov_b32_e32 v29, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v30, 0 +; GCN-NEXT: v_mov_b32_e32 v28, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB120_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 8, v8 +; GCN-NEXT: v_or_b32_e32 v31, v0, v7 +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 8, v16 +; GCN-NEXT: v_or_b32_e32 v0, v0, v7 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: v_and_b32_e32 v7, 0xff, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 8, v24 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_or_b32_e32 v0, v7, v8 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_and_b32_e32 v8, 0xff, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 8, v44 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_or_b32_e32 v0, v8, v11 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; GCN-NEXT: v_and_b32_e32 v11, 0xff, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v49, 24, v4 +; GCN-NEXT: v_and_b32_e32 v18, 0xff, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 24, v6 +; GCN-NEXT: v_and_b32_e32 v20, 0xff, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 24, v10 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v22, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 24, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v26, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v7, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v27, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v8, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v28, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v6, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v29, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v9, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v30, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v10, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v32, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v21, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v50, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v19, 24, v0 +; GCN-NEXT: v_and_b32_e32 v12, 0xff, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 24, v43 +; GCN-NEXT: v_and_b32_e32 v13, 0xff, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v25, 24, v42 +; GCN-NEXT: v_and_b32_e32 v14, 0xff, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 24, v17 +; GCN-NEXT: v_and_b32_e32 v51, 0xff, v62 +; GCN-NEXT: v_lshlrev_b32_e32 v53, 8, v61 +; GCN-NEXT: v_and_b32_e32 v55, 0xff, v60 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v59 +; GCN-NEXT: v_and_b32_e32 v40, 0xff, v58 +; GCN-NEXT: v_lshlrev_b32_e32 v57, 24, v57 +; GCN-NEXT: v_and_b32_e32 v41, 0xff, v56 +; GCN-NEXT: v_lshlrev_b32_e32 v38, 24, v47 +; GCN-NEXT: v_and_b32_e32 v46, 0xff, v46 +; GCN-NEXT: v_lshlrev_b32_e32 v45, 8, v45 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v47, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v39, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v56, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v44, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v58, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v43, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v59, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v60, 8, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v61, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v42, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v62, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v23, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v63, 0xff, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v24, 24, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v33, 8, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v34, 0xff, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v17, 24, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v20 +; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v22 +; GCN-NEXT: v_lshlrev_b32_e32 v37, 16, v26 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v28 +; GCN-NEXT: v_lshlrev_b32_e32 v35, 16, v29 +; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v30 +; GCN-NEXT: v_lshlrev_b32_e32 v30, 16, v32 +; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v50 +; GCN-NEXT: v_lshlrev_b32_e32 v26, 16, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v27, 16, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v28, 16, v14 +; GCN-NEXT: v_or_b32_e32 v12, v51, v53 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v55 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v40 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v41 +; GCN-NEXT: v_or_b32_e32 v45, v46, v45 +; GCN-NEXT: v_lshlrev_b32_e32 v46, 16, v47 +; GCN-NEXT: v_lshlrev_b32_e32 v47, 16, v56 +; GCN-NEXT: v_lshlrev_b32_e32 v56, 16, v58 +; GCN-NEXT: v_or_b32_e32 v58, v59, v60 +; GCN-NEXT: v_lshlrev_b32_e32 v59, 16, v61 +; GCN-NEXT: v_lshlrev_b32_e32 v60, 16, v62 +; GCN-NEXT: v_lshlrev_b32_e32 v61, 16, v63 +; GCN-NEXT: v_or_b32_e32 v62, v0, v33 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v34 +; GCN-NEXT: v_or_b32_e32 v49, v49, v3 +; GCN-NEXT: v_or_b32_e32 v52, v52, v18 +; GCN-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GCN-NEXT: v_or_b32_e32 v48, v48, v4 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_or_b32_e32 v18, v0, v36 +; GCN-NEXT: v_or_b32_e32 v40, v7, v37 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v55, 16, v0 +; GCN-NEXT: v_or_b32_e32 v41, v8, v22 +; GCN-NEXT: v_or_b32_e32 v22, v6, v20 +; GCN-NEXT: v_or_b32_e32 v20, v9, v35 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v0 +; GCN-NEXT: v_or_b32_e32 v53, v10, v29 +; GCN-NEXT: v_or_b32_e32 v21, v21, v30 +; GCN-NEXT: v_or_b32_e32 v19, v19, v32 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v51, 16, v0 +; GCN-NEXT: v_or_b32_e32 v54, v54, v26 +; GCN-NEXT: v_or_b32_e32 v35, v25, v27 +; GCN-NEXT: v_or_b32_e32 v37, v15, v28 +; GCN-NEXT: v_lshlrev_b32_e32 v27, 16, v12 +; GCN-NEXT: v_or_b32_e32 v25, v16, v13 +; GCN-NEXT: v_or_b32_e32 v36, v57, v14 +; GCN-NEXT: v_or_b32_e32 v38, v38, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v26, 16, v45 +; GCN-NEXT: v_or_b32_e32 v39, v39, v46 +; GCN-NEXT: v_or_b32_e32 v0, v44, v47 +; GCN-NEXT: v_or_b32_e32 v33, v43, v56 +; GCN-NEXT: v_lshlrev_b32_e32 v63, 16, v58 +; GCN-NEXT: v_or_b32_e32 v29, v42, v59 +; GCN-NEXT: v_or_b32_e32 v32, v23, v60 +; GCN-NEXT: v_or_b32_e32 v34, v24, v61 +; GCN-NEXT: v_lshlrev_b32_e32 v30, 16, v62 +; GCN-NEXT: v_or_b32_e32 v28, v17, v11 +; GCN-NEXT: .LBB120_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v52 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v49 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v48 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v31 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v55 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v53 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v50 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v54 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v51 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v37 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v35 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v38 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v36 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v39 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v33 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v63 +; GCN-NEXT: v_mul_f32_e32 v33, 1.0, v34 +; GCN-NEXT: v_mul_f32_e32 v32, 1.0, v32 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v7, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v9, v10, 16 +; GCN-NEXT: v_alignbit_b32 v7, v11, v12, 16 +; GCN-NEXT: v_alignbit_b32 v8, v13, v14, 16 +; GCN-NEXT: v_alignbit_b32 v9, v15, v16, 16 +; GCN-NEXT: v_alignbit_b32 v10, v17, v18, 16 +; GCN-NEXT: v_alignbit_b32 v11, v19, v20, 16 +; GCN-NEXT: v_alignbit_b32 v12, v21, v22, 16 +; GCN-NEXT: v_alignbit_b32 v13, v23, v24, 16 +; GCN-NEXT: v_alignbit_b32 v14, v25, v26, 16 +; GCN-NEXT: v_alignbit_b32 v15, v27, v0, 16 +; GCN-NEXT: v_alignbit_b32 v16, v29, v31, 16 +; GCN-NEXT: v_alignbit_b32 v17, v33, v32, 16 +; GCN-NEXT: v_alignbit_b32 v18, v28, v30, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[15:18], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v64i8_to_v32bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:140 +; VI-NEXT: buffer_load_ushort v14, off, s[0:3], s32 offset:136 +; VI-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:132 +; VI-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:128 +; VI-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:124 +; VI-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:120 +; VI-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:116 +; VI-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:112 +; VI-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:108 +; VI-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:104 +; VI-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:100 +; VI-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:96 +; VI-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:92 +; VI-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:88 +; VI-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:84 +; VI-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:80 +; VI-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:76 +; VI-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:72 +; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:68 +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:64 +; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:60 +; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:56 +; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:52 +; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:48 +; VI-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:44 +; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:40 +; VI-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:36 +; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:32 +; VI-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:28 +; VI-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:24 +; VI-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:20 +; VI-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:16 +; VI-NEXT: buffer_load_ushort v15, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_ushort v13, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_ushort v16, off, s[0:3], s32 +; VI-NEXT: v_mov_b32_e32 v31, 0 +; VI-NEXT: v_mov_b32_e32 v32, v31 +; VI-NEXT: v_mov_b32_e32 v33, v31 +; VI-NEXT: v_mov_b32_e32 v34, v31 +; VI-NEXT: v_mov_b32_e32 v35, v31 +; VI-NEXT: v_mov_b32_e32 v36, v31 +; VI-NEXT: v_mov_b32_e32 v37, v31 +; VI-NEXT: v_mov_b32_e32 v38, v31 +; VI-NEXT: v_mov_b32_e32 v48, v31 +; VI-NEXT: v_mov_b32_e32 v49, v31 +; VI-NEXT: v_mov_b32_e32 v50, v31 +; VI-NEXT: v_mov_b32_e32 v51, v31 +; VI-NEXT: v_mov_b32_e32 v52, v31 +; VI-NEXT: v_mov_b32_e32 v53, v31 +; VI-NEXT: v_mov_b32_e32 v54, v31 +; VI-NEXT: v_mov_b32_e32 v55, v31 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB120_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v6 +; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v8 +; VI-NEXT: v_lshlrev_b16_e32 v6, 8, v10 +; VI-NEXT: v_or_b32_sdwa v5, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v6, v9, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v31, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; VI-NEXT: v_or_b32_sdwa v32, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v12 +; VI-NEXT: v_or_b32_sdwa v3, v11, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v33, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v34, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v35, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v36, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v37, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v13 +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v15 +; VI-NEXT: v_or_b32_sdwa v3, v16, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v4, v18, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v38, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v17 +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v19 +; VI-NEXT: v_or_b32_sdwa v3, v20, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v4, v22, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v48, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v21 +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v23 +; VI-NEXT: v_or_b32_sdwa v3, v24, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v4, v26, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v49, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v25 +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v27 +; VI-NEXT: v_or_b32_sdwa v3, v28, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v4, v30, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v50, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v29 +; VI-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v63 +; VI-NEXT: v_or_b32_sdwa v3, v62, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v51, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v61 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v59 +; VI-NEXT: v_or_b32_sdwa v0, v60, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v58, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v52, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v57 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v47 +; VI-NEXT: v_or_b32_sdwa v0, v56, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v46, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v53, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v45 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v43 +; VI-NEXT: v_or_b32_sdwa v0, v44, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v42, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v54, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v41 +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v39 +; VI-NEXT: v_or_b32_sdwa v0, v40, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v3, v14, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v55, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: .LBB120_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[52:55] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[48:51] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[35:38] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[31:34] +; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v64i8_to_v32bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:140 +; GFX9-NEXT: buffer_load_ushort v14, off, s[0:3], s32 offset:136 +; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:132 +; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:128 +; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:124 +; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:120 +; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:116 +; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:112 +; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:108 +; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:104 +; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:100 +; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:96 +; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:92 +; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:88 +; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:84 +; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:80 +; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:76 +; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:72 +; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:68 +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:64 +; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:60 +; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:56 +; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:52 +; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:48 +; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:44 +; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:40 +; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:36 +; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:32 +; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:28 +; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:24 +; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:20 +; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:16 +; GFX9-NEXT: buffer_load_ushort v15, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_ushort v13, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 +; GFX9-NEXT: v_mov_b32_e32 v31, 0 +; GFX9-NEXT: v_mov_b32_e32 v32, v31 +; GFX9-NEXT: v_mov_b32_e32 v33, v31 +; GFX9-NEXT: v_mov_b32_e32 v34, v31 +; GFX9-NEXT: v_mov_b32_e32 v35, v31 +; GFX9-NEXT: v_mov_b32_e32 v36, v31 +; GFX9-NEXT: v_mov_b32_e32 v37, v31 +; GFX9-NEXT: v_mov_b32_e32 v38, v31 +; GFX9-NEXT: v_mov_b32_e32 v48, v31 +; GFX9-NEXT: v_mov_b32_e32 v49, v31 +; GFX9-NEXT: v_mov_b32_e32 v50, v31 +; GFX9-NEXT: v_mov_b32_e32 v51, v31 +; GFX9-NEXT: v_mov_b32_e32 v52, v31 +; GFX9-NEXT: v_mov_b32_e32 v53, v31 +; GFX9-NEXT: v_mov_b32_e32 v54, v31 +; GFX9-NEXT: v_mov_b32_e32 v55, v31 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB120_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v6 +; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v8 +; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v10 +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 +; GFX9-NEXT: v_or_b32_sdwa v5, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v6, v9, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v31, v4, v3, s6 +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GFX9-NEXT: v_perm_b32 v32, v6, v5, s6 +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v12 +; GFX9-NEXT: v_or_b32_sdwa v3, v11, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v33, v4, v3, s6 +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v34, v4, v3, s6 +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v35, v4, v3, s6 +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v36, v4, v3, s6 +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v37, v4, v3, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v13 +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v15 +; GFX9-NEXT: v_or_b32_sdwa v3, v16, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v4, v18, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v38, v4, v3, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v17 +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v19 +; GFX9-NEXT: v_or_b32_sdwa v3, v20, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v4, v22, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v48, v4, v3, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v21 +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v23 +; GFX9-NEXT: v_or_b32_sdwa v3, v24, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v4, v26, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v49, v4, v3, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v25 +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v27 +; GFX9-NEXT: v_or_b32_sdwa v3, v28, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v4, v30, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v50, v4, v3, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v29 +; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v63 +; GFX9-NEXT: v_or_b32_sdwa v3, v62, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v51, v3, v0, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v61 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v59 +; GFX9-NEXT: v_or_b32_sdwa v0, v60, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v58, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v52, v3, v0, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v57 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v47 +; GFX9-NEXT: v_or_b32_sdwa v0, v56, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v46, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v53, v3, v0, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v45 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v43 +; GFX9-NEXT: v_or_b32_sdwa v0, v44, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v42, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v54, v3, v0, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v41 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v39 +; GFX9-NEXT: v_or_b32_sdwa v0, v40, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v14, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v55, v3, v0, s6 +; GFX9-NEXT: .LBB120_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[52:55], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[48:51], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[35:38], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off +; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: v_bitcast_v64i8_to_v32bf16: +; GFX11-TRUE16: ; %bb.0: ; %entry +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_clause 0x1f +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:140 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:136 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:132 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:128 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:124 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:120 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:116 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:112 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:108 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:104 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:100 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:96 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:92 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:88 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:84 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:80 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:76 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:72 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:68 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v80, off, s32 offset:64 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:60 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v81, off, s32 offset:56 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:52 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v82, off, s32 offset:48 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:44 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v83, off, s32 offset:40 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:36 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v84, off, s32 offset:32 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:28 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v85, off, s32 offset:24 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:20 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v86, off, s32 offset:16 +; GFX11-TRUE16-NEXT: s_clause 0x3 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:12 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v87, off, s32 offset:8 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:4 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v96, off, s32 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v31, 0 +; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v32, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v33, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v34, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v35, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v36, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v37, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v38, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v48, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v49, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v50, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v51, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v52, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v53, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v54, v31 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v55, v31 +; GFX11-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB120_2 +; GFX11-TRUE16-NEXT: ; %bb.1: ; %if +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v4.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v6.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v11.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v12.l +; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v7.l +; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v8.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v9.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v10.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v13.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v14.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v15.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v16.l +; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v32.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v33.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v33.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v34.l, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v17.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v18.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v19.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v20.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v21.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v22.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v23.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v24.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v25.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v26.l +; GFX11-TRUE16-NEXT: v_or_b16 v34.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v35.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v35.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v36.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v36.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v27.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v28.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v29.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v30.l +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v96.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v96.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v87.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v87.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v86.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v86.l +; GFX11-TRUE16-NEXT: v_or_b16 v37.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v37.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v38.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v38.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v48.l, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v85.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v85.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v84.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v84.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v83.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v83.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v82.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v82.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v81.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v81.l +; GFX11-TRUE16-NEXT: v_or_b16 v48.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v49.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v49.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v50.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v50.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v80.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v80.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v71.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v71.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v70.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v70.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v69.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v69.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v68.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v68.l +; GFX11-TRUE16-NEXT: v_or_b16 v51.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v51.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v52.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v52.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v53.l, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v67.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v67.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v66.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v66.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v65.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v65.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v64.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v64.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v39.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v39.l +; GFX11-TRUE16-NEXT: v_or_b16 v53.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v54.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v54.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v55.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v55.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: .LBB120_2: ; %end +; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-TRUE16-NEXT: s_clause 0x3 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[52:55], off offset:48 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[48:51], off offset:32 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[35:38], off offset:16 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[31:34], off +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: v_bitcast_v64i8_to_v32bf16: +; GFX11-FAKE16: ; %bb.0: ; %entry +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_clause 0x1f +; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:140 +; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:136 +; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:132 +; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:128 +; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:124 +; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:120 +; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:116 +; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:112 +; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:108 +; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:104 +; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:100 +; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:96 +; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:92 +; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:88 +; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:84 +; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:80 +; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:76 +; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:72 +; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:68 +; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:64 +; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:60 +; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:56 +; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:52 +; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:48 +; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:44 +; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:40 +; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:36 +; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:32 +; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:28 +; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:24 +; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:20 +; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:16 +; GFX11-FAKE16-NEXT: s_clause 0x3 +; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:12 +; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:8 +; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:4 +; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v31, 0 +; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v32, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v33, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v34, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v35, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v36, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v37, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v38, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v48, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v49, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v50, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v51, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v52, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v53, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v54, v31 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v55, v31 +; GFX11-FAKE16-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB120_2 +; GFX11-FAKE16-NEXT: ; %bb.1: ; %if +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v6 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v24 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v8 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v10 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v13 +; GFX11-FAKE16-NEXT: v_perm_b32 v31, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v12 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v15 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v16 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v18 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v20 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v21 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v22 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v23 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v26 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v32, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v33, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v34, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v35, v9, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v36, v11, v10, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v28 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v29 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v30 +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v130 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v129 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v128 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v119 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v118 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v117 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v116 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v115 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v114 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v113 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v112 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v103 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v102 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v101 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v100 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v99 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v37, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v38, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v48, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v49, v9, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v50, v11, v10, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v98 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v97 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v96 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v87 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v86 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v85 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v84 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v83 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v82 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v81 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v80 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v71 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v70 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v69 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v68 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v67 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v66 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v65 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v64 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v39 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v51, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v52, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v53, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v54, v9, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v55, v11, v10, 0x5040100 +; GFX11-FAKE16-NEXT: .LBB120_2: ; %end +; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-FAKE16-NEXT: s_clause 0x3 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[52:55], off offset:48 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[48:51], off offset:32 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[35:38], off offset:16 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[31:34], off +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <64 x i8> %value to <32 x bfloat> + br label %end + +end: + %phi = phi <32 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <32 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32i16_to_v32bf16(i32 %cond, ptr addrspace(1) %out, <32 x i16> %value) { +; GCN-LABEL: v_bitcast_v32i16_to_v32bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_waitcnt expcnt(3) +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:12 +; GCN-NEXT: s_waitcnt expcnt(2) +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 +; GCN-NEXT: v_mov_b32_e32 v46, 0 +; GCN-NEXT: v_mov_b32_e32 v58, 0 +; GCN-NEXT: v_mov_b32_e32 v47, 0 +; GCN-NEXT: v_mov_b32_e32 v59, 0 +; GCN-NEXT: v_mov_b32_e32 v56, 0 +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: v_mov_b32_e32 v57, 0 +; GCN-NEXT: v_mov_b32_e32 v61, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v42, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v43, 0 +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: v_mov_b32_e32 v44, 0 +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v45, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v29, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB121_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_lshlrev_b32_e32 v46, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v58, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v47, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v59, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v56, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v60, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v57, 16, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v61, 16, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v42, 16, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v55, 16, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v43, 16, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v40, 16, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v44, 16, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v41, 16, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v45, 16, v18 +; GCN-NEXT: v_lshlrev_b32_e32 v38, 16, v19 +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v20 +; GCN-NEXT: v_lshlrev_b32_e32 v39, 16, v21 +; GCN-NEXT: v_lshlrev_b32_e32 v51, 16, v22 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 16, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v24 +; GCN-NEXT: v_lshlrev_b32_e32 v49, 16, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v53, 16, v26 +; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v28 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v31, 16, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v35, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v30 +; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v33, 16, v63 +; GCN-NEXT: v_lshlrev_b32_e32 v37, 16, v62 +; GCN-NEXT: .LBB121_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v58 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v46 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v59 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v47 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v60 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v56 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v61 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v57 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v42 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v54 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v43 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v55 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v44 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v45 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v50 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v38 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v51 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v39 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v52 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v48 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v53 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v49 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v34 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v29 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v35 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v31 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v36 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v32 +; GCN-NEXT: v_mul_f32_e32 v32, 1.0, v37 +; GCN-NEXT: v_mul_f32_e32 v33, 1.0, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_alignbit_b32 v5, v6, v7, 16 +; GCN-NEXT: v_alignbit_b32 v6, v8, v9, 16 +; GCN-NEXT: v_alignbit_b32 v7, v10, v11, 16 +; GCN-NEXT: v_alignbit_b32 v8, v12, v13, 16 +; GCN-NEXT: v_alignbit_b32 v9, v14, v15, 16 +; GCN-NEXT: v_alignbit_b32 v10, v16, v17, 16 +; GCN-NEXT: v_alignbit_b32 v11, v18, v19, 16 +; GCN-NEXT: v_alignbit_b32 v12, v20, v21, 16 +; GCN-NEXT: v_alignbit_b32 v13, v22, v23, 16 +; GCN-NEXT: v_alignbit_b32 v14, v24, v25, 16 +; GCN-NEXT: v_alignbit_b32 v15, v26, v27, 16 +; GCN-NEXT: v_alignbit_b32 v16, v28, v29, 16 +; GCN-NEXT: v_alignbit_b32 v17, v30, v31, 16 +; GCN-NEXT: v_alignbit_b32 v18, v32, v33, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[15:18], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32i16_to_v32bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB121_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB121_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32i16_to_v32bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB121_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB121_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32i16_to_v32bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB121_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB121_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x i16> %value to <32 x bfloat> + br label %end + +end: + %phi = phi <32 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <32 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32f16_to_v32bf16(i32 %cond, ptr addrspace(1) %out, <32 x half> %value) { +; GCN-LABEL: v_bitcast_v32f16_to_v32bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 +; GCN-NEXT: v_mov_b32_e32 v46, 0 +; GCN-NEXT: v_mov_b32_e32 v58, 0 +; GCN-NEXT: v_mov_b32_e32 v47, 0 +; GCN-NEXT: v_mov_b32_e32 v59, 0 +; GCN-NEXT: v_mov_b32_e32 v56, 0 +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: v_mov_b32_e32 v57, 0 +; GCN-NEXT: v_mov_b32_e32 v61, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v42, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v43, 0 +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: v_mov_b32_e32 v44, 0 +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v45, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB122_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v4 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v5 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v6 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v7 +; GCN-NEXT: v_cvt_f16_f32_e32 v7, v8 +; GCN-NEXT: v_cvt_f16_f32_e32 v8, v9 +; GCN-NEXT: v_cvt_f16_f32_e32 v9, v10 +; GCN-NEXT: v_cvt_f16_f32_e32 v10, v11 +; GCN-NEXT: v_cvt_f16_f32_e32 v11, v12 +; GCN-NEXT: v_cvt_f16_f32_e32 v12, v13 +; GCN-NEXT: v_cvt_f16_f32_e32 v13, v14 +; GCN-NEXT: v_cvt_f16_f32_e32 v14, v15 +; GCN-NEXT: v_cvt_f16_f32_e32 v15, v16 +; GCN-NEXT: v_cvt_f16_f32_e32 v16, v17 +; GCN-NEXT: v_cvt_f16_f32_e32 v17, v18 +; GCN-NEXT: v_cvt_f16_f32_e32 v18, v19 +; GCN-NEXT: v_cvt_f16_f32_e32 v19, v20 +; GCN-NEXT: v_cvt_f16_f32_e32 v20, v21 +; GCN-NEXT: v_cvt_f16_f32_e32 v21, v22 +; GCN-NEXT: v_cvt_f16_f32_e32 v22, v23 +; GCN-NEXT: v_cvt_f16_f32_e32 v23, v24 +; GCN-NEXT: v_cvt_f16_f32_e32 v24, v25 +; GCN-NEXT: v_cvt_f16_f32_e32 v25, v26 +; GCN-NEXT: v_cvt_f16_f32_e32 v26, v27 +; GCN-NEXT: v_cvt_f16_f32_e32 v27, v28 +; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v28, v28 +; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v32, v31 +; GCN-NEXT: v_cvt_f16_f32_e32 v30, v30 +; GCN-NEXT: v_cvt_f16_f32_e32 v33, v62 +; GCN-NEXT: v_cvt_f16_f32_e32 v37, v63 +; GCN-NEXT: v_cvt_f16_f32_e32 v29, v29 +; GCN-NEXT: v_lshlrev_b32_e32 v46, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v58, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v47, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v59, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v56, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v60, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v57, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v61, 16, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v42, 16, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v55, 16, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v43, 16, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v40, 16, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v44, 16, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v41, 16, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v45, 16, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v38, 16, v18 +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v19 +; GCN-NEXT: v_lshlrev_b32_e32 v39, 16, v20 +; GCN-NEXT: v_lshlrev_b32_e32 v51, 16, v21 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 16, v22 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v49, 16, v24 +; GCN-NEXT: v_lshlrev_b32_e32 v53, 16, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v26 +; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v31, 16, v28 +; GCN-NEXT: v_lshlrev_b32_e32 v35, 16, v32 +; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v30 +; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v33 +; GCN-NEXT: v_lshlrev_b32_e32 v33, 16, v37 +; GCN-NEXT: v_lshlrev_b32_e32 v37, 16, v29 +; GCN-NEXT: .LBB122_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v58 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v46 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v59 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v47 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v60 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v56 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v61 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v57 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v42 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v54 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v43 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v55 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v44 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v45 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v50 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v38 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v51 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v39 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v52 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v48 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v53 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v49 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v34 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v35 +; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v31 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v36 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v32 +; GCN-NEXT: v_mul_f32_e32 v32, 1.0, v37 +; GCN-NEXT: v_mul_f32_e32 v33, 1.0, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v7, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v9, v10, 16 +; GCN-NEXT: v_alignbit_b32 v7, v11, v12, 16 +; GCN-NEXT: v_alignbit_b32 v8, v13, v14, 16 +; GCN-NEXT: v_alignbit_b32 v9, v15, v16, 16 +; GCN-NEXT: v_alignbit_b32 v10, v17, v18, 16 +; GCN-NEXT: v_alignbit_b32 v11, v19, v20, 16 +; GCN-NEXT: v_alignbit_b32 v12, v21, v22, 16 +; GCN-NEXT: v_alignbit_b32 v13, v23, v24, 16 +; GCN-NEXT: v_alignbit_b32 v14, v25, v26, 16 +; GCN-NEXT: v_alignbit_b32 v15, v27, v0, 16 +; GCN-NEXT: v_alignbit_b32 v16, v28, v29, 16 +; GCN-NEXT: v_alignbit_b32 v17, v30, v31, 16 +; GCN-NEXT: v_alignbit_b32 v18, v32, v33, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[15:18], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32f16_to_v32bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB122_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB122_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32f16_to_v32bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB122_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB122_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32f16_to_v32bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB122_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB122_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x half> %value to <32 x bfloat> + br label %end + +end: + %phi = phi <32 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <32 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v16i32_to_v32bf16(i32 %cond, ptr addrspace(1) %out, <16 x i32> %value) { +; GCN-LABEL: v_bitcast_v16i32_to_v32bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v30, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v28, 0 +; GCN-NEXT: v_mov_b32_e32 v29, 0 +; GCN-NEXT: v_mov_b32_e32 v26, 0 +; GCN-NEXT: v_mov_b32_e32 v27, 0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB123_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v19, 0xffff0000, v18 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v18 +; GCN-NEXT: v_and_b32_e32 v21, 0xffff0000, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v17 +; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v16 +; GCN-NEXT: v_and_b32_e32 v25, 0xffff0000, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v15 +; GCN-NEXT: v_and_b32_e32 v27, 0xffff0000, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v26, 16, v14 +; GCN-NEXT: v_and_b32_e32 v29, 0xffff0000, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v28, 16, v13 +; GCN-NEXT: v_and_b32_e32 v31, 0xffff0000, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v30, 16, v12 +; GCN-NEXT: v_and_b32_e32 v33, 0xffff0000, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GCN-NEXT: v_and_b32_e32 v35, 0xffff0000, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v10 +; GCN-NEXT: v_and_b32_e32 v37, 0xffff0000, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v9 +; GCN-NEXT: v_and_b32_e32 v39, 0xffff0000, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v38, 16, v8 +; GCN-NEXT: v_and_b32_e32 v49, 0xffff0000, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 16, v7 +; GCN-NEXT: v_and_b32_e32 v51, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v6 +; GCN-NEXT: v_and_b32_e32 v53, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v5 +; GCN-NEXT: v_and_b32_e32 v55, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v4 +; GCN-NEXT: v_and_b32_e32 v41, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v40, 16, v3 +; GCN-NEXT: .LBB123_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v55 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v54 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v53 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v52 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v51 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v50 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v49 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v48 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v39 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v38 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v37 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v36 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v35 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v34 +; GCN-NEXT: v_mul_f32_e32 v33, 1.0, v33 +; GCN-NEXT: v_mul_f32_e32 v32, 1.0, v32 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v31 +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v7, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v9, v10, 16 +; GCN-NEXT: v_alignbit_b32 v7, v11, v12, 16 +; GCN-NEXT: v_alignbit_b32 v8, v13, v14, 16 +; GCN-NEXT: v_alignbit_b32 v9, v15, v16, 16 +; GCN-NEXT: v_alignbit_b32 v10, v17, v18, 16 +; GCN-NEXT: v_alignbit_b32 v11, v33, v32, 16 +; GCN-NEXT: v_alignbit_b32 v12, v31, v30, 16 +; GCN-NEXT: v_alignbit_b32 v13, v29, v28, 16 +; GCN-NEXT: v_alignbit_b32 v14, v27, v26, 16 +; GCN-NEXT: v_alignbit_b32 v15, v25, v24, 16 +; GCN-NEXT: v_alignbit_b32 v16, v23, v22, 16 +; GCN-NEXT: v_alignbit_b32 v17, v21, v20, 16 +; GCN-NEXT: v_alignbit_b32 v18, v19, v0, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[15:18], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v16i32_to_v32bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB123_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB123_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v16i32_to_v32bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB123_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB123_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v16i32_to_v32bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB123_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB123_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <16 x i32> %value to <32 x bfloat> + br label %end + +end: + %phi = phi <32 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <32 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v16f32_to_v32bf16(i32 %cond, ptr addrspace(1) %out, <16 x float> %value) { +; GCN-LABEL: v_bitcast_v16f32_to_v32bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v30, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v28, 0 +; GCN-NEXT: v_mov_b32_e32 v29, 0 +; GCN-NEXT: v_mov_b32_e32 v26, 0 +; GCN-NEXT: v_mov_b32_e32 v27, 0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB124_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v19, 0xffff0000, v18 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v18 +; GCN-NEXT: v_and_b32_e32 v21, 0xffff0000, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v17 +; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v16 +; GCN-NEXT: v_and_b32_e32 v25, 0xffff0000, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v15 +; GCN-NEXT: v_and_b32_e32 v27, 0xffff0000, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v26, 16, v14 +; GCN-NEXT: v_and_b32_e32 v29, 0xffff0000, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v28, 16, v13 +; GCN-NEXT: v_and_b32_e32 v31, 0xffff0000, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v30, 16, v12 +; GCN-NEXT: v_and_b32_e32 v33, 0xffff0000, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GCN-NEXT: v_and_b32_e32 v35, 0xffff0000, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v10 +; GCN-NEXT: v_and_b32_e32 v37, 0xffff0000, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v9 +; GCN-NEXT: v_and_b32_e32 v39, 0xffff0000, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v38, 16, v8 +; GCN-NEXT: v_and_b32_e32 v49, 0xffff0000, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 16, v7 +; GCN-NEXT: v_and_b32_e32 v51, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v6 +; GCN-NEXT: v_and_b32_e32 v53, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v5 +; GCN-NEXT: v_and_b32_e32 v55, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v4 +; GCN-NEXT: v_and_b32_e32 v41, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v40, 16, v3 +; GCN-NEXT: .LBB124_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v55 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v54 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v53 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v52 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v51 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v50 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v49 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v48 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v39 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v38 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v37 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v36 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v35 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v34 +; GCN-NEXT: v_mul_f32_e32 v33, 1.0, v33 +; GCN-NEXT: v_mul_f32_e32 v32, 1.0, v32 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v31 +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v7, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v9, v10, 16 +; GCN-NEXT: v_alignbit_b32 v7, v11, v12, 16 +; GCN-NEXT: v_alignbit_b32 v8, v13, v14, 16 +; GCN-NEXT: v_alignbit_b32 v9, v15, v16, 16 +; GCN-NEXT: v_alignbit_b32 v10, v17, v18, 16 +; GCN-NEXT: v_alignbit_b32 v11, v33, v32, 16 +; GCN-NEXT: v_alignbit_b32 v12, v31, v30, 16 +; GCN-NEXT: v_alignbit_b32 v13, v29, v28, 16 +; GCN-NEXT: v_alignbit_b32 v14, v27, v26, 16 +; GCN-NEXT: v_alignbit_b32 v15, v25, v24, 16 +; GCN-NEXT: v_alignbit_b32 v16, v23, v22, 16 +; GCN-NEXT: v_alignbit_b32 v17, v21, v20, 16 +; GCN-NEXT: v_alignbit_b32 v18, v19, v0, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[15:18], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v16f32_to_v32bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB124_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB124_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v16f32_to_v32bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB124_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB124_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v16f32_to_v32bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB124_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB124_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <16 x float> %value to <32 x bfloat> + br label %end + +end: + %phi = phi <32 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <32 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8f64_to_v32bf16(i32 %cond, ptr addrspace(1) %out, <8 x double> %value) { +; GCN-LABEL: v_bitcast_v8f64_to_v32bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v30, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v28, 0 +; GCN-NEXT: v_mov_b32_e32 v29, 0 +; GCN-NEXT: v_mov_b32_e32 v26, 0 +; GCN-NEXT: v_mov_b32_e32 v27, 0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB125_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v19, 0xffff0000, v18 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v18 +; GCN-NEXT: v_and_b32_e32 v21, 0xffff0000, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v17 +; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v16 +; GCN-NEXT: v_and_b32_e32 v25, 0xffff0000, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v15 +; GCN-NEXT: v_and_b32_e32 v27, 0xffff0000, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v26, 16, v14 +; GCN-NEXT: v_and_b32_e32 v29, 0xffff0000, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v28, 16, v13 +; GCN-NEXT: v_and_b32_e32 v31, 0xffff0000, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v30, 16, v12 +; GCN-NEXT: v_and_b32_e32 v33, 0xffff0000, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GCN-NEXT: v_and_b32_e32 v35, 0xffff0000, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v10 +; GCN-NEXT: v_and_b32_e32 v37, 0xffff0000, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v9 +; GCN-NEXT: v_and_b32_e32 v39, 0xffff0000, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v38, 16, v8 +; GCN-NEXT: v_and_b32_e32 v49, 0xffff0000, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 16, v7 +; GCN-NEXT: v_and_b32_e32 v51, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v6 +; GCN-NEXT: v_and_b32_e32 v53, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v5 +; GCN-NEXT: v_and_b32_e32 v55, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v4 +; GCN-NEXT: v_and_b32_e32 v41, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v40, 16, v3 +; GCN-NEXT: .LBB125_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v55 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v54 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v53 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v52 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v51 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v50 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v49 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v48 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v39 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v38 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v37 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v36 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v35 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v34 +; GCN-NEXT: v_mul_f32_e32 v33, 1.0, v33 +; GCN-NEXT: v_mul_f32_e32 v32, 1.0, v32 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v31 +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v7, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v9, v10, 16 +; GCN-NEXT: v_alignbit_b32 v7, v11, v12, 16 +; GCN-NEXT: v_alignbit_b32 v8, v13, v14, 16 +; GCN-NEXT: v_alignbit_b32 v9, v15, v16, 16 +; GCN-NEXT: v_alignbit_b32 v10, v17, v18, 16 +; GCN-NEXT: v_alignbit_b32 v11, v33, v32, 16 +; GCN-NEXT: v_alignbit_b32 v12, v31, v30, 16 +; GCN-NEXT: v_alignbit_b32 v13, v29, v28, 16 +; GCN-NEXT: v_alignbit_b32 v14, v27, v26, 16 +; GCN-NEXT: v_alignbit_b32 v15, v25, v24, 16 +; GCN-NEXT: v_alignbit_b32 v16, v23, v22, 16 +; GCN-NEXT: v_alignbit_b32 v17, v21, v20, 16 +; GCN-NEXT: v_alignbit_b32 v18, v19, v0, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[15:18], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8f64_to_v32bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB125_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB125_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8f64_to_v32bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB125_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB125_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8f64_to_v32bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB125_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB125_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x double> %value to <32 x bfloat> + br label %end + +end: + %phi = phi <32 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <32 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v8i64_to_v32bf16(i32 %cond, ptr addrspace(1) %out, <8 x i64> %value) { +; GCN-LABEL: v_bitcast_v8i64_to_v32bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v30, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v28, 0 +; GCN-NEXT: v_mov_b32_e32 v29, 0 +; GCN-NEXT: v_mov_b32_e32 v26, 0 +; GCN-NEXT: v_mov_b32_e32 v27, 0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB126_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v19, 0xffff0000, v18 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v18 +; GCN-NEXT: v_and_b32_e32 v21, 0xffff0000, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v17 +; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v16 +; GCN-NEXT: v_and_b32_e32 v25, 0xffff0000, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v15 +; GCN-NEXT: v_and_b32_e32 v27, 0xffff0000, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v26, 16, v14 +; GCN-NEXT: v_and_b32_e32 v29, 0xffff0000, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v28, 16, v13 +; GCN-NEXT: v_and_b32_e32 v31, 0xffff0000, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v30, 16, v12 +; GCN-NEXT: v_and_b32_e32 v33, 0xffff0000, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v11 +; GCN-NEXT: v_and_b32_e32 v35, 0xffff0000, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v10 +; GCN-NEXT: v_and_b32_e32 v37, 0xffff0000, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v9 +; GCN-NEXT: v_and_b32_e32 v39, 0xffff0000, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v38, 16, v8 +; GCN-NEXT: v_and_b32_e32 v49, 0xffff0000, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 16, v7 +; GCN-NEXT: v_and_b32_e32 v51, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v6 +; GCN-NEXT: v_and_b32_e32 v53, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v5 +; GCN-NEXT: v_and_b32_e32 v55, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v4 +; GCN-NEXT: v_and_b32_e32 v41, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v40, 16, v3 +; GCN-NEXT: .LBB126_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v41 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v40 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v55 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v54 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v53 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v52 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v51 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v50 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v49 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v48 +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v39 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v38 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v37 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v36 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v35 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v34 +; GCN-NEXT: v_mul_f32_e32 v33, 1.0, v33 +; GCN-NEXT: v_mul_f32_e32 v32, 1.0, v32 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v31 +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v29, 1.0, v29 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_alignbit_b32 v4, v5, v6, 16 +; GCN-NEXT: v_alignbit_b32 v5, v7, v8, 16 +; GCN-NEXT: v_alignbit_b32 v6, v9, v10, 16 +; GCN-NEXT: v_alignbit_b32 v7, v11, v12, 16 +; GCN-NEXT: v_alignbit_b32 v8, v13, v14, 16 +; GCN-NEXT: v_alignbit_b32 v9, v15, v16, 16 +; GCN-NEXT: v_alignbit_b32 v10, v17, v18, 16 +; GCN-NEXT: v_alignbit_b32 v11, v33, v32, 16 +; GCN-NEXT: v_alignbit_b32 v12, v31, v30, 16 +; GCN-NEXT: v_alignbit_b32 v13, v29, v28, 16 +; GCN-NEXT: v_alignbit_b32 v14, v27, v26, 16 +; GCN-NEXT: v_alignbit_b32 v15, v25, v24, 16 +; GCN-NEXT: v_alignbit_b32 v16, v23, v22, 16 +; GCN-NEXT: v_alignbit_b32 v17, v21, v20, 16 +; GCN-NEXT: v_alignbit_b32 v18, v19, v0, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[11:14], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[15:18], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8i64_to_v32bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v19, 0 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: v_mov_b32_e32 v20, v19 +; VI-NEXT: v_mov_b32_e32 v21, v19 +; VI-NEXT: v_mov_b32_e32 v22, v19 +; VI-NEXT: v_mov_b32_e32 v23, v19 +; VI-NEXT: v_mov_b32_e32 v24, v19 +; VI-NEXT: v_mov_b32_e32 v25, v19 +; VI-NEXT: v_mov_b32_e32 v26, v19 +; VI-NEXT: v_mov_b32_e32 v27, v19 +; VI-NEXT: v_mov_b32_e32 v28, v19 +; VI-NEXT: v_mov_b32_e32 v29, v19 +; VI-NEXT: v_mov_b32_e32 v30, v19 +; VI-NEXT: v_mov_b32_e32 v31, v19 +; VI-NEXT: v_mov_b32_e32 v32, v19 +; VI-NEXT: v_mov_b32_e32 v33, v19 +; VI-NEXT: v_mov_b32_e32 v34, v19 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB126_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v34, v18 +; VI-NEXT: v_mov_b32_e32 v33, v17 +; VI-NEXT: v_mov_b32_e32 v32, v16 +; VI-NEXT: v_mov_b32_e32 v31, v15 +; VI-NEXT: v_mov_b32_e32 v30, v14 +; VI-NEXT: v_mov_b32_e32 v29, v13 +; VI-NEXT: v_mov_b32_e32 v28, v12 +; VI-NEXT: v_mov_b32_e32 v27, v11 +; VI-NEXT: v_mov_b32_e32 v26, v10 +; VI-NEXT: v_mov_b32_e32 v25, v9 +; VI-NEXT: v_mov_b32_e32 v24, v8 +; VI-NEXT: v_mov_b32_e32 v23, v7 +; VI-NEXT: v_mov_b32_e32 v22, v6 +; VI-NEXT: v_mov_b32_e32 v21, v5 +; VI-NEXT: v_mov_b32_e32 v20, v4 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: .LBB126_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[27:30] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[23:26] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[19:22] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8i64_to_v32bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v19, 0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_mov_b32_e32 v20, v19 +; GFX9-NEXT: v_mov_b32_e32 v21, v19 +; GFX9-NEXT: v_mov_b32_e32 v22, v19 +; GFX9-NEXT: v_mov_b32_e32 v23, v19 +; GFX9-NEXT: v_mov_b32_e32 v24, v19 +; GFX9-NEXT: v_mov_b32_e32 v25, v19 +; GFX9-NEXT: v_mov_b32_e32 v26, v19 +; GFX9-NEXT: v_mov_b32_e32 v27, v19 +; GFX9-NEXT: v_mov_b32_e32 v28, v19 +; GFX9-NEXT: v_mov_b32_e32 v29, v19 +; GFX9-NEXT: v_mov_b32_e32 v30, v19 +; GFX9-NEXT: v_mov_b32_e32 v31, v19 +; GFX9-NEXT: v_mov_b32_e32 v32, v19 +; GFX9-NEXT: v_mov_b32_e32 v33, v19 +; GFX9-NEXT: v_mov_b32_e32 v34, v19 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB126_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v34, v18 +; GFX9-NEXT: v_mov_b32_e32 v33, v17 +; GFX9-NEXT: v_mov_b32_e32 v32, v16 +; GFX9-NEXT: v_mov_b32_e32 v31, v15 +; GFX9-NEXT: v_mov_b32_e32 v30, v14 +; GFX9-NEXT: v_mov_b32_e32 v29, v13 +; GFX9-NEXT: v_mov_b32_e32 v28, v12 +; GFX9-NEXT: v_mov_b32_e32 v27, v11 +; GFX9-NEXT: v_mov_b32_e32 v26, v10 +; GFX9-NEXT: v_mov_b32_e32 v25, v9 +; GFX9-NEXT: v_mov_b32_e32 v24, v8 +; GFX9-NEXT: v_mov_b32_e32 v23, v7 +; GFX9-NEXT: v_mov_b32_e32 v22, v6 +; GFX9-NEXT: v_mov_b32_e32 v21, v5 +; GFX9-NEXT: v_mov_b32_e32 v20, v4 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: .LBB126_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8i64_to_v32bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v19, 0 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v20, v19 +; GFX11-NEXT: v_mov_b32_e32 v21, v19 +; GFX11-NEXT: v_mov_b32_e32 v22, v19 +; GFX11-NEXT: v_mov_b32_e32 v23, v19 +; GFX11-NEXT: v_mov_b32_e32 v24, v19 +; GFX11-NEXT: v_mov_b32_e32 v25, v19 +; GFX11-NEXT: v_mov_b32_e32 v26, v19 +; GFX11-NEXT: v_mov_b32_e32 v27, v19 +; GFX11-NEXT: v_mov_b32_e32 v28, v19 +; GFX11-NEXT: v_mov_b32_e32 v29, v19 +; GFX11-NEXT: v_mov_b32_e32 v30, v19 +; GFX11-NEXT: v_mov_b32_e32 v31, v19 +; GFX11-NEXT: v_mov_b32_e32 v32, v19 +; GFX11-NEXT: v_mov_b32_e32 v33, v19 +; GFX11-NEXT: v_mov_b32_e32 v34, v19 +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB126_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v33, v17 +; GFX11-NEXT: v_dual_mov_b32 v32, v16 :: v_dual_mov_b32 v31, v15 +; GFX11-NEXT: v_dual_mov_b32 v30, v14 :: v_dual_mov_b32 v29, v13 +; GFX11-NEXT: v_dual_mov_b32 v28, v12 :: v_dual_mov_b32 v27, v11 +; GFX11-NEXT: v_dual_mov_b32 v26, v10 :: v_dual_mov_b32 v25, v9 +; GFX11-NEXT: v_dual_mov_b32 v24, v8 :: v_dual_mov_b32 v23, v7 +; GFX11-NEXT: v_dual_mov_b32 v22, v6 :: v_dual_mov_b32 v21, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3 +; GFX11-NEXT: .LBB126_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: global_store_b128 v[1:2], v[31:34], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[27:30], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[23:26], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[19:22], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <8 x i64> %value to <32 x bfloat> + br label %end + +end: + %phi = phi <32 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <32 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + +define <32 x half> @v_bitcast_v8i64_to_v32f16(<8 x i64> %a, i32 %b) { +; GCN-LABEL: v_bitcast_v8i64_to_v32f16: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v34, v15 +; GCN-NEXT: v_mov_b32_e32 v33, v14 +; GCN-NEXT: v_mov_b32_e32 v36, v13 +; GCN-NEXT: v_mov_b32_e32 v35, v12 +; GCN-NEXT: v_mov_b32_e32 v38, v11 +; GCN-NEXT: v_mov_b32_e32 v37, v10 +; GCN-NEXT: v_mov_b32_e32 v48, v9 +; GCN-NEXT: v_mov_b32_e32 v39, v8 +; GCN-NEXT: v_mov_b32_e32 v50, v7 +; GCN-NEXT: v_mov_b32_e32 v49, v6 +; GCN-NEXT: v_mov_b32_e32 v52, v5 +; GCN-NEXT: v_mov_b32_e32 v51, v4 +; GCN-NEXT: v_mov_b32_e32 v54, v3 +; GCN-NEXT: v_mov_b32_e32 v53, v2 +; GCN-NEXT: v_mov_b32_e32 v55, v1 +; GCN-NEXT: v_mov_b32_e32 v32, v0 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GCN-NEXT: ; implicit-def: $vgpr0 +; GCN-NEXT: ; implicit-def: $vgpr1 +; GCN-NEXT: ; implicit-def: $vgpr2 +; GCN-NEXT: ; implicit-def: $vgpr3 +; GCN-NEXT: ; implicit-def: $vgpr4 +; GCN-NEXT: ; implicit-def: $vgpr5 +; GCN-NEXT: ; implicit-def: $vgpr6 +; GCN-NEXT: ; implicit-def: $vgpr7 +; GCN-NEXT: ; implicit-def: $vgpr8 +; GCN-NEXT: ; implicit-def: $vgpr9 +; GCN-NEXT: ; implicit-def: $vgpr10 +; GCN-NEXT: ; implicit-def: $vgpr11 +; GCN-NEXT: ; implicit-def: $vgpr12 +; GCN-NEXT: ; implicit-def: $vgpr13 +; GCN-NEXT: ; implicit-def: $vgpr14 +; GCN-NEXT: ; implicit-def: $vgpr15 +; GCN-NEXT: ; implicit-def: $vgpr16 +; GCN-NEXT: ; implicit-def: $vgpr17 +; GCN-NEXT: ; implicit-def: $vgpr18 +; GCN-NEXT: ; implicit-def: $vgpr19 +; GCN-NEXT: ; implicit-def: $vgpr20 +; GCN-NEXT: ; implicit-def: $vgpr21 +; GCN-NEXT: ; implicit-def: $vgpr22 +; GCN-NEXT: ; implicit-def: $vgpr23 +; GCN-NEXT: ; implicit-def: $vgpr24 +; GCN-NEXT: ; implicit-def: $vgpr25 +; GCN-NEXT: ; implicit-def: $vgpr26 +; GCN-NEXT: ; implicit-def: $vgpr27 +; GCN-NEXT: ; implicit-def: $vgpr28 +; GCN-NEXT: ; implicit-def: $vgpr29 +; GCN-NEXT: ; implicit-def: $vgpr30 +; GCN-NEXT: ; implicit-def: $vgpr31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB127_2 +; GCN-NEXT: ; %bb.1: ; %cmp.false +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v34 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v36 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v35 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v38 +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v37 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v48 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v50 +; GCN-NEXT: s_waitcnt expcnt(6) +; GCN-NEXT: v_lshrrev_b32_e32 v40, 16, v49 +; GCN-NEXT: s_waitcnt expcnt(5) +; GCN-NEXT: v_lshrrev_b32_e32 v41, 16, v52 +; GCN-NEXT: s_waitcnt expcnt(4) +; GCN-NEXT: v_lshrrev_b32_e32 v42, 16, v51 +; GCN-NEXT: s_waitcnt expcnt(3) +; GCN-NEXT: v_lshrrev_b32_e32 v43, 16, v54 +; GCN-NEXT: s_waitcnt expcnt(2) +; GCN-NEXT: v_lshrrev_b32_e32 v44, 16, v53 +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: v_lshrrev_b32_e32 v45, 16, v55 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v46, 16, v32 +; GCN-NEXT: v_cvt_f32_f16_e32 v30, v34 +; GCN-NEXT: v_cvt_f32_f16_e32 v28, v33 +; GCN-NEXT: v_cvt_f32_f16_e32 v26, v36 +; GCN-NEXT: v_cvt_f32_f16_e32 v24, v35 +; GCN-NEXT: v_cvt_f32_f16_e32 v22, v38 +; GCN-NEXT: v_cvt_f32_f16_e32 v20, v37 +; GCN-NEXT: v_cvt_f32_f16_e32 v18, v48 +; GCN-NEXT: v_cvt_f32_f16_e32 v16, v39 +; GCN-NEXT: v_cvt_f32_f16_e32 v14, v50 +; GCN-NEXT: v_cvt_f32_f16_e32 v12, v49 +; GCN-NEXT: v_cvt_f32_f16_e32 v10, v52 +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v51 +; GCN-NEXT: v_cvt_f32_f16_e32 v6, v54 +; GCN-NEXT: v_cvt_f32_f16_e32 v4, v53 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v55 +; GCN-NEXT: v_cvt_f32_f16_e32 v31, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v29, v1 +; GCN-NEXT: v_cvt_f32_f16_e32 v27, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v5 +; GCN-NEXT: v_cvt_f32_f16_e32 v23, v7 +; GCN-NEXT: v_cvt_f32_f16_e32 v21, v9 +; GCN-NEXT: v_cvt_f32_f16_e32 v19, v11 +; GCN-NEXT: v_cvt_f32_f16_e32 v17, v13 +; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15 +; GCN-NEXT: v_cvt_f32_f16_e32 v13, v40 +; GCN-NEXT: v_cvt_f32_f16_e32 v11, v41 +; GCN-NEXT: v_cvt_f32_f16_e32 v9, v42 +; GCN-NEXT: v_cvt_f32_f16_e32 v7, v43 +; GCN-NEXT: v_cvt_f32_f16_e32 v5, v44 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v45 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, v46 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v32 +; GCN-NEXT: ; implicit-def: $vgpr32 +; GCN-NEXT: ; implicit-def: $vgpr55 +; GCN-NEXT: ; implicit-def: $vgpr53 +; GCN-NEXT: ; implicit-def: $vgpr54 +; GCN-NEXT: ; implicit-def: $vgpr51 +; GCN-NEXT: ; implicit-def: $vgpr52 +; GCN-NEXT: ; implicit-def: $vgpr49 +; GCN-NEXT: ; implicit-def: $vgpr50 +; GCN-NEXT: ; implicit-def: $vgpr39 +; GCN-NEXT: ; implicit-def: $vgpr48 +; GCN-NEXT: ; implicit-def: $vgpr37 +; GCN-NEXT: ; implicit-def: $vgpr38 +; GCN-NEXT: ; implicit-def: $vgpr35 +; GCN-NEXT: ; implicit-def: $vgpr36 +; GCN-NEXT: ; implicit-def: $vgpr33 +; GCN-NEXT: ; implicit-def: $vgpr34 +; GCN-NEXT: .LBB127_2: ; %Flow +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB127_4 +; GCN-NEXT: ; %bb.3: ; %cmp.true +; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v32 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v55, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v53 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v54, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v51 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v52, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v49 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v50, vcc +; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v39 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v48, vcc +; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v37 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v38, vcc +; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v35 +; GCN-NEXT: v_addc_u32_e32 v13, vcc, 0, v36, vcc +; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v33 +; GCN-NEXT: v_addc_u32_e32 v15, vcc, 0, v34, vcc +; GCN-NEXT: v_lshrrev_b32_e32 v32, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v1 +; GCN-NEXT: v_lshrrev_b32_e32 v34, 16, v2 +; GCN-NEXT: v_lshrrev_b32_e32 v35, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v36, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v37, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v38, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v39, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v15 +; GCN-NEXT: v_cvt_f32_f16_e32 v30, v15 +; GCN-NEXT: v_cvt_f32_f16_e32 v28, v14 +; GCN-NEXT: v_cvt_f32_f16_e32 v26, v13 +; GCN-NEXT: v_cvt_f32_f16_e32 v24, v12 +; GCN-NEXT: v_cvt_f32_f16_e32 v22, v11 +; GCN-NEXT: v_cvt_f32_f16_e32 v20, v10 +; GCN-NEXT: v_cvt_f32_f16_e32 v18, v9 +; GCN-NEXT: v_cvt_f32_f16_e32 v16, v8 +; GCN-NEXT: v_cvt_f32_f16_e32 v14, v7 +; GCN-NEXT: v_cvt_f32_f16_e32 v12, v6 +; GCN-NEXT: v_cvt_f32_f16_e32 v10, v5 +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v4 +; GCN-NEXT: v_cvt_f32_f16_e32 v6, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v4, v2 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v1 +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v31, v31 +; GCN-NEXT: v_cvt_f32_f16_e32 v29, v29 +; GCN-NEXT: v_cvt_f32_f16_e32 v27, v27 +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v25 +; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23 +; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 +; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 +; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 +; GCN-NEXT: v_cvt_f32_f16_e32 v15, v39 +; GCN-NEXT: v_cvt_f32_f16_e32 v13, v38 +; GCN-NEXT: v_cvt_f32_f16_e32 v11, v37 +; GCN-NEXT: v_cvt_f32_f16_e32 v9, v36 +; GCN-NEXT: v_cvt_f32_f16_e32 v7, v35 +; GCN-NEXT: v_cvt_f32_f16_e32 v5, v34 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v33 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, v32 +; GCN-NEXT: .LBB127_4: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8i64_to_v32f16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; VI-NEXT: s_cbranch_execz .LBB127_2 +; VI-NEXT: ; %bb.1: ; %cmp.true +; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14 +; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc +; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12 +; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc +; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 +; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc +; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 +; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 +; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 +; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 +; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; VI-NEXT: .LBB127_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8i64_to_v32f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9-NEXT: s_cbranch_execz .LBB127_2 +; GFX9-NEXT: ; %bb.1: ; %cmp.true +; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14 +; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc +; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12 +; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc +; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10 +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc +; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8 +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc +; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: .LBB127_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8i64_to_v32f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16 +; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-NEXT: s_cbranch_execz .LBB127_2 +; GFX11-NEXT: ; %bb.1: ; %cmp.true +; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo +; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3 +; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo +; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo +; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3 +; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo +; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3 +; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3 +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX11-NEXT: .LBB127_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_setpc_b64 s[30:31] + %cmp = icmp eq i32 %b, 0 + br i1 %cmp, label %cmp.true, label %cmp.false +cmp.true: + %a1 = add <8 x i64> %a, splat (i64 3) + %a2 = bitcast <8 x i64> %a1 to <32 x half> + br label %end +cmp.false: + %a3 = bitcast <8 x i64> %a to <32 x half> + br label %end +end: + %phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] + ret <32 x half> %phi +} + + +define <32 x i16> @v_bitcast_v8i64_to_v32i16(<8 x i64> %a, i32 %b) { +; GCN-LABEL: v_bitcast_v8i64_to_v32i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v30, v15 +; GCN-NEXT: v_mov_b32_e32 v28, v14 +; GCN-NEXT: v_mov_b32_e32 v26, v13 +; GCN-NEXT: v_mov_b32_e32 v24, v12 +; GCN-NEXT: v_mov_b32_e32 v22, v11 +; GCN-NEXT: v_mov_b32_e32 v20, v10 +; GCN-NEXT: v_mov_b32_e32 v18, v9 +; GCN-NEXT: v_mov_b32_e32 v32, v8 +; GCN-NEXT: v_mov_b32_e32 v14, v7 +; GCN-NEXT: v_mov_b32_e32 v12, v6 +; GCN-NEXT: v_mov_b32_e32 v10, v5 +; GCN-NEXT: v_mov_b32_e32 v8, v4 +; GCN-NEXT: v_mov_b32_e32 v6, v3 +; GCN-NEXT: v_mov_b32_e32 v4, v2 +; GCN-NEXT: v_mov_b32_e32 v2, v1 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GCN-NEXT: ; implicit-def: $vgpr1 +; GCN-NEXT: ; implicit-def: $vgpr3 +; GCN-NEXT: ; implicit-def: $vgpr5 +; GCN-NEXT: ; implicit-def: $vgpr7 +; GCN-NEXT: ; implicit-def: $vgpr9 +; GCN-NEXT: ; implicit-def: $vgpr11 +; GCN-NEXT: ; implicit-def: $vgpr13 +; GCN-NEXT: ; implicit-def: $vgpr15 +; GCN-NEXT: ; implicit-def: $vgpr17 +; GCN-NEXT: ; implicit-def: $vgpr19 +; GCN-NEXT: ; implicit-def: $vgpr21 +; GCN-NEXT: ; implicit-def: $vgpr23 +; GCN-NEXT: ; implicit-def: $vgpr25 +; GCN-NEXT: ; implicit-def: $vgpr27 +; GCN-NEXT: ; implicit-def: $vgpr29 +; GCN-NEXT: ; implicit-def: $vgpr31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB128_2 +; GCN-NEXT: ; %bb.1: ; %cmp.false +; GCN-NEXT: v_alignbit_b32 v29, v30, v28, 16 +; GCN-NEXT: v_alignbit_b32 v25, v26, v24, 16 +; GCN-NEXT: v_alignbit_b32 v21, v22, v20, 16 +; GCN-NEXT: v_alignbit_b32 v17, v18, v32, 16 +; GCN-NEXT: v_alignbit_b32 v13, v14, v12, 16 +; GCN-NEXT: v_alignbit_b32 v9, v10, v8, 16 +; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 +; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GCN-NEXT: .LBB128_2: ; %Flow +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB128_4 +; GCN-NEXT: ; %bb.3: ; %cmp.true +; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc +; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc +; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v12 +; GCN-NEXT: v_addc_u32_e32 v14, vcc, 0, v14, vcc +; GCN-NEXT: v_add_i32_e32 v32, vcc, 3, v32 +; GCN-NEXT: v_addc_u32_e32 v18, vcc, 0, v18, vcc +; GCN-NEXT: v_add_i32_e32 v20, vcc, 3, v20 +; GCN-NEXT: v_addc_u32_e32 v22, vcc, 0, v22, vcc +; GCN-NEXT: v_add_i32_e32 v24, vcc, 3, v24 +; GCN-NEXT: v_addc_u32_e32 v26, vcc, 0, v26, vcc +; GCN-NEXT: v_add_i32_e32 v28, vcc, 3, v28 +; GCN-NEXT: v_addc_u32_e32 v30, vcc, 0, v30, vcc +; GCN-NEXT: v_alignbit_b32 v29, v30, v28, 16 +; GCN-NEXT: v_alignbit_b32 v25, v26, v24, 16 +; GCN-NEXT: v_alignbit_b32 v21, v22, v20, 16 +; GCN-NEXT: v_alignbit_b32 v17, v18, v32, 16 +; GCN-NEXT: v_alignbit_b32 v13, v14, v12, 16 +; GCN-NEXT: v_alignbit_b32 v9, v10, v8, 16 +; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 +; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v30 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GCN-NEXT: .LBB128_4: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mov_b32_e32 v16, v32 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8i64_to_v32i16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; VI-NEXT: s_cbranch_execz .LBB128_2 +; VI-NEXT: ; %bb.1: ; %cmp.true +; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14 +; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc +; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12 +; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc +; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 +; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc +; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 +; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 +; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 +; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 +; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; VI-NEXT: .LBB128_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8i64_to_v32i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9-NEXT: s_cbranch_execz .LBB128_2 +; GFX9-NEXT: ; %bb.1: ; %cmp.true +; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14 +; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc +; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12 +; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc +; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10 +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc +; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8 +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc +; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: .LBB128_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8i64_to_v32i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16 +; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-NEXT: s_cbranch_execz .LBB128_2 +; GFX11-NEXT: ; %bb.1: ; %cmp.true +; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo +; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3 +; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo +; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo +; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3 +; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo +; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3 +; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3 +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX11-NEXT: .LBB128_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_setpc_b64 s[30:31] + %cmp = icmp eq i32 %b, 0 + br i1 %cmp, label %cmp.true, label %cmp.false +cmp.true: + %a1 = add <8 x i64> %a, splat (i64 3) + %a2 = bitcast <8 x i64> %a1 to <32 x i16> + br label %end +cmp.false: + %a3 = bitcast <8 x i64> %a to <32 x i16> + br label %end +end: + %phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] + ret <32 x i16> %phi +} + + +define <32 x i16> @v_bitcast_v8f64_to_v32i16(<8 x double> %a, i32 %b) { +; GCN-LABEL: v_bitcast_v8f64_to_v32i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v55, v15 +; GCN-NEXT: v_mov_b32_e32 v54, v14 +; GCN-NEXT: v_mov_b32_e32 v53, v13 +; GCN-NEXT: v_mov_b32_e32 v52, v12 +; GCN-NEXT: v_mov_b32_e32 v51, v11 +; GCN-NEXT: v_mov_b32_e32 v50, v10 +; GCN-NEXT: v_mov_b32_e32 v49, v9 +; GCN-NEXT: v_mov_b32_e32 v48, v8 +; GCN-NEXT: v_mov_b32_e32 v38, v7 +; GCN-NEXT: v_mov_b32_e32 v37, v6 +; GCN-NEXT: v_mov_b32_e32 v36, v5 +; GCN-NEXT: v_mov_b32_e32 v35, v4 +; GCN-NEXT: v_mov_b32_e32 v34, v3 +; GCN-NEXT: v_mov_b32_e32 v33, v2 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GCN-NEXT: ; implicit-def: $vgpr32 +; GCN-NEXT: ; implicit-def: $vgpr3 +; GCN-NEXT: ; implicit-def: $vgpr5 +; GCN-NEXT: ; implicit-def: $vgpr7 +; GCN-NEXT: ; implicit-def: $vgpr9 +; GCN-NEXT: ; implicit-def: $vgpr11 +; GCN-NEXT: ; implicit-def: $vgpr13 +; GCN-NEXT: ; implicit-def: $vgpr15 +; GCN-NEXT: ; implicit-def: $vgpr17 +; GCN-NEXT: ; implicit-def: $vgpr19 +; GCN-NEXT: ; implicit-def: $vgpr21 +; GCN-NEXT: ; implicit-def: $vgpr23 +; GCN-NEXT: ; implicit-def: $vgpr25 +; GCN-NEXT: ; implicit-def: $vgpr27 +; GCN-NEXT: ; implicit-def: $vgpr29 +; GCN-NEXT: ; implicit-def: $vgpr31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB129_2 +; GCN-NEXT: ; %bb.1: ; %cmp.false +; GCN-NEXT: v_alignbit_b32 v29, v55, v54, 16 +; GCN-NEXT: v_alignbit_b32 v25, v53, v52, 16 +; GCN-NEXT: v_alignbit_b32 v21, v51, v50, 16 +; GCN-NEXT: v_alignbit_b32 v17, v49, v48, 16 +; GCN-NEXT: v_alignbit_b32 v13, v38, v37, 16 +; GCN-NEXT: v_alignbit_b32 v9, v36, v35, 16 +; GCN-NEXT: v_alignbit_b32 v5, v34, v33, 16 +; GCN-NEXT: v_alignbit_b32 v32, v1, v0, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v53 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v51 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v49 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v38 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v36 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v34 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GCN-NEXT: .LBB129_2: ; %Flow +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB129_4 +; GCN-NEXT: ; %bb.3: ; %cmp.true +; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GCN-NEXT: v_add_f64 v[33:34], v[33:34], 1.0 +; GCN-NEXT: v_add_f64 v[35:36], v[35:36], 1.0 +; GCN-NEXT: v_add_f64 v[37:38], v[37:38], 1.0 +; GCN-NEXT: v_add_f64 v[48:49], v[48:49], 1.0 +; GCN-NEXT: v_add_f64 v[50:51], v[50:51], 1.0 +; GCN-NEXT: v_add_f64 v[52:53], v[52:53], 1.0 +; GCN-NEXT: v_add_f64 v[54:55], v[54:55], 1.0 +; GCN-NEXT: v_alignbit_b32 v29, v55, v54, 16 +; GCN-NEXT: v_alignbit_b32 v25, v53, v52, 16 +; GCN-NEXT: v_alignbit_b32 v21, v51, v50, 16 +; GCN-NEXT: v_alignbit_b32 v17, v49, v48, 16 +; GCN-NEXT: v_alignbit_b32 v13, v38, v37, 16 +; GCN-NEXT: v_alignbit_b32 v9, v36, v35, 16 +; GCN-NEXT: v_alignbit_b32 v5, v34, v33, 16 +; GCN-NEXT: v_alignbit_b32 v32, v1, v0, 16 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v53 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v51 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v49 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v38 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v36 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v34 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GCN-NEXT: .LBB129_4: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mov_b32_e32 v2, v1 +; GCN-NEXT: v_mov_b32_e32 v4, v33 +; GCN-NEXT: v_mov_b32_e32 v6, v34 +; GCN-NEXT: v_mov_b32_e32 v8, v35 +; GCN-NEXT: v_mov_b32_e32 v10, v36 +; GCN-NEXT: v_mov_b32_e32 v12, v37 +; GCN-NEXT: v_mov_b32_e32 v14, v38 +; GCN-NEXT: v_mov_b32_e32 v16, v48 +; GCN-NEXT: v_mov_b32_e32 v18, v49 +; GCN-NEXT: v_mov_b32_e32 v20, v50 +; GCN-NEXT: v_mov_b32_e32 v22, v51 +; GCN-NEXT: v_mov_b32_e32 v24, v52 +; GCN-NEXT: v_mov_b32_e32 v26, v53 +; GCN-NEXT: v_mov_b32_e32 v28, v54 +; GCN-NEXT: v_mov_b32_e32 v30, v55 +; GCN-NEXT: v_mov_b32_e32 v1, v32 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8f64_to_v32i16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; VI-NEXT: s_cbranch_execz .LBB129_2 +; VI-NEXT: ; %bb.1: ; %cmp.true +; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0 +; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0 +; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 +; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 +; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 +; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 +; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 +; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; VI-NEXT: .LBB129_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8f64_to_v32i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9-NEXT: s_cbranch_execz .LBB129_2 +; GFX9-NEXT: ; %bb.1: ; %cmp.true +; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0 +; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0 +; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 +; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 +; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 +; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 +; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 +; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GFX9-NEXT: .LBB129_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8f64_to_v32i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16 +; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-NEXT: s_cbranch_execz .LBB129_2 +; GFX11-NEXT: ; %bb.1: ; %cmp.true +; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0 +; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0 +; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 +; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 +; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 +; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 +; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 +; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GFX11-NEXT: .LBB129_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_setpc_b64 s[30:31] + %cmp = icmp eq i32 %b, 0 + br i1 %cmp, label %cmp.true, label %cmp.false +cmp.true: + %a1 = fadd <8 x double> %a, splat (double 1.000000e+00) + %a2 = bitcast <8 x double> %a1 to <32 x i16> + br label %end +cmp.false: + %a3 = bitcast <8 x double> %a to <32 x i16> + br label %end +end: + %phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] + ret <32 x i16> %phi +} + + +define <32 x half> @v_bitcast_v8f64_to_v32f16(<8 x double> %a, i32 %b) { +; GCN-LABEL: v_bitcast_v8f64_to_v32f16: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GCN-NEXT: ; implicit-def: $vgpr39 +; GCN-NEXT: ; implicit-def: $vgpr55 +; GCN-NEXT: ; implicit-def: $vgpr32 +; GCN-NEXT: ; implicit-def: $vgpr54 +; GCN-NEXT: ; implicit-def: $vgpr33 +; GCN-NEXT: ; implicit-def: $vgpr53 +; GCN-NEXT: ; implicit-def: $vgpr34 +; GCN-NEXT: ; implicit-def: $vgpr52 +; GCN-NEXT: ; implicit-def: $vgpr35 +; GCN-NEXT: ; implicit-def: $vgpr51 +; GCN-NEXT: ; implicit-def: $vgpr36 +; GCN-NEXT: ; implicit-def: $vgpr50 +; GCN-NEXT: ; implicit-def: $vgpr37 +; GCN-NEXT: ; implicit-def: $vgpr49 +; GCN-NEXT: ; implicit-def: $vgpr38 +; GCN-NEXT: ; implicit-def: $vgpr48 +; GCN-NEXT: ; implicit-def: $vgpr16 +; GCN-NEXT: ; implicit-def: $vgpr17 +; GCN-NEXT: ; implicit-def: $vgpr18 +; GCN-NEXT: ; implicit-def: $vgpr19 +; GCN-NEXT: ; implicit-def: $vgpr20 +; GCN-NEXT: ; implicit-def: $vgpr21 +; GCN-NEXT: ; implicit-def: $vgpr22 +; GCN-NEXT: ; implicit-def: $vgpr23 +; GCN-NEXT: ; implicit-def: $vgpr24 +; GCN-NEXT: ; implicit-def: $vgpr25 +; GCN-NEXT: ; implicit-def: $vgpr26 +; GCN-NEXT: ; implicit-def: $vgpr27 +; GCN-NEXT: ; implicit-def: $vgpr28 +; GCN-NEXT: ; implicit-def: $vgpr29 +; GCN-NEXT: ; implicit-def: $vgpr30 +; GCN-NEXT: ; implicit-def: $vgpr31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB130_2 +; GCN-NEXT: ; %bb.1: ; %cmp.false +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v39, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v48, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v49, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v50, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v51, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v52, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v53, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v54, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v3 +; GCN-NEXT: s_waitcnt expcnt(2) +; GCN-NEXT: v_lshrrev_b32_e32 v40, 16, v2 +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v42, 16, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v30, v15 +; GCN-NEXT: v_cvt_f32_f16_e32 v28, v14 +; GCN-NEXT: v_cvt_f32_f16_e32 v26, v13 +; GCN-NEXT: v_cvt_f32_f16_e32 v24, v12 +; GCN-NEXT: v_cvt_f32_f16_e32 v22, v11 +; GCN-NEXT: v_cvt_f32_f16_e32 v20, v10 +; GCN-NEXT: v_cvt_f32_f16_e32 v18, v9 +; GCN-NEXT: v_cvt_f32_f16_e32 v16, v8 +; GCN-NEXT: v_cvt_f32_f16_e32 v38, v7 +; GCN-NEXT: v_cvt_f32_f16_e32 v37, v6 +; GCN-NEXT: v_cvt_f32_f16_e32 v36, v5 +; GCN-NEXT: v_cvt_f32_f16_e32 v35, v4 +; GCN-NEXT: v_cvt_f32_f16_e32 v34, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v33, v2 +; GCN-NEXT: v_cvt_f32_f16_e32 v32, v1 +; GCN-NEXT: v_cvt_f32_f16_e32 v31, v17 +; GCN-NEXT: v_cvt_f32_f16_e32 v29, v19 +; GCN-NEXT: v_cvt_f32_f16_e32 v27, v21 +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v23 +; GCN-NEXT: v_cvt_f32_f16_e32 v23, v39 +; GCN-NEXT: v_cvt_f32_f16_e32 v21, v48 +; GCN-NEXT: v_cvt_f32_f16_e32 v19, v49 +; GCN-NEXT: v_cvt_f32_f16_e32 v17, v50 +; GCN-NEXT: v_cvt_f32_f16_e32 v48, v51 +; GCN-NEXT: v_cvt_f32_f16_e32 v49, v52 +; GCN-NEXT: v_cvt_f32_f16_e32 v50, v53 +; GCN-NEXT: v_cvt_f32_f16_e32 v51, v54 +; GCN-NEXT: v_cvt_f32_f16_e32 v52, v55 +; GCN-NEXT: v_cvt_f32_f16_e32 v53, v40 +; GCN-NEXT: v_cvt_f32_f16_e32 v54, v41 +; GCN-NEXT: v_cvt_f32_f16_e32 v55, v42 +; GCN-NEXT: v_cvt_f32_f16_e32 v39, v0 +; GCN-NEXT: ; implicit-def: $vgpr0 +; GCN-NEXT: ; implicit-def: $vgpr2 +; GCN-NEXT: ; implicit-def: $vgpr4 +; GCN-NEXT: ; implicit-def: $vgpr6 +; GCN-NEXT: ; implicit-def: $vgpr8 +; GCN-NEXT: ; implicit-def: $vgpr10 +; GCN-NEXT: ; implicit-def: $vgpr12 +; GCN-NEXT: ; implicit-def: $vgpr14 +; GCN-NEXT: .LBB130_2: ; %Flow +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB130_4 +; GCN-NEXT: ; %bb.3: ; %cmp.true +; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 +; GCN-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 +; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 +; GCN-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 +; GCN-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 +; GCN-NEXT: v_add_f64 v[12:13], v[12:13], 1.0 +; GCN-NEXT: v_add_f64 v[14:15], v[14:15], 1.0 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; GCN-NEXT: v_lshrrev_b32_e32 v53, 16, v2 +; GCN-NEXT: v_lshrrev_b32_e32 v52, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v51, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v50, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v49, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v48, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v15 +; GCN-NEXT: v_cvt_f32_f16_e32 v30, v15 +; GCN-NEXT: v_cvt_f32_f16_e32 v28, v14 +; GCN-NEXT: v_cvt_f32_f16_e32 v26, v13 +; GCN-NEXT: v_cvt_f32_f16_e32 v24, v12 +; GCN-NEXT: v_cvt_f32_f16_e32 v22, v11 +; GCN-NEXT: v_cvt_f32_f16_e32 v20, v10 +; GCN-NEXT: v_cvt_f32_f16_e32 v18, v9 +; GCN-NEXT: v_cvt_f32_f16_e32 v16, v8 +; GCN-NEXT: v_cvt_f32_f16_e32 v38, v7 +; GCN-NEXT: v_cvt_f32_f16_e32 v37, v6 +; GCN-NEXT: v_cvt_f32_f16_e32 v36, v5 +; GCN-NEXT: v_cvt_f32_f16_e32 v35, v4 +; GCN-NEXT: v_cvt_f32_f16_e32 v34, v3 +; GCN-NEXT: v_cvt_f32_f16_e32 v33, v2 +; GCN-NEXT: v_cvt_f32_f16_e32 v32, v1 +; GCN-NEXT: v_cvt_f32_f16_e32 v39, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v31, v31 +; GCN-NEXT: v_cvt_f32_f16_e32 v29, v29 +; GCN-NEXT: v_cvt_f32_f16_e32 v27, v27 +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v25 +; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23 +; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 +; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 +; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 +; GCN-NEXT: v_cvt_f32_f16_e32 v48, v48 +; GCN-NEXT: v_cvt_f32_f16_e32 v49, v49 +; GCN-NEXT: v_cvt_f32_f16_e32 v50, v50 +; GCN-NEXT: v_cvt_f32_f16_e32 v51, v51 +; GCN-NEXT: v_cvt_f32_f16_e32 v52, v52 +; GCN-NEXT: v_cvt_f32_f16_e32 v53, v53 +; GCN-NEXT: v_cvt_f32_f16_e32 v54, v54 +; GCN-NEXT: v_cvt_f32_f16_e32 v55, v55 +; GCN-NEXT: .LBB130_4: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mov_b32_e32 v0, v39 +; GCN-NEXT: v_mov_b32_e32 v1, v55 +; GCN-NEXT: v_mov_b32_e32 v2, v32 +; GCN-NEXT: v_mov_b32_e32 v3, v54 +; GCN-NEXT: v_mov_b32_e32 v4, v33 +; GCN-NEXT: v_mov_b32_e32 v5, v53 +; GCN-NEXT: v_mov_b32_e32 v6, v34 +; GCN-NEXT: v_mov_b32_e32 v7, v52 +; GCN-NEXT: v_mov_b32_e32 v8, v35 +; GCN-NEXT: v_mov_b32_e32 v9, v51 +; GCN-NEXT: v_mov_b32_e32 v10, v36 +; GCN-NEXT: v_mov_b32_e32 v11, v50 +; GCN-NEXT: v_mov_b32_e32 v12, v37 +; GCN-NEXT: v_mov_b32_e32 v13, v49 +; GCN-NEXT: v_mov_b32_e32 v14, v38 +; GCN-NEXT: v_mov_b32_e32 v15, v48 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v8f64_to_v32f16: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; VI-NEXT: s_cbranch_execz .LBB130_2 +; VI-NEXT: ; %bb.1: ; %cmp.true +; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0 +; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0 +; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 +; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 +; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 +; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 +; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 +; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; VI-NEXT: .LBB130_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v8f64_to_v32f16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9-NEXT: s_cbranch_execz .LBB130_2 +; GFX9-NEXT: ; %bb.1: ; %cmp.true +; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0 +; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0 +; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 +; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 +; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 +; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 +; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 +; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GFX9-NEXT: .LBB130_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v8f64_to_v32f16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16 +; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-NEXT: s_cbranch_execz .LBB130_2 +; GFX11-NEXT: ; %bb.1: ; %cmp.true +; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0 +; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0 +; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 +; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 +; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 +; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 +; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 +; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GFX11-NEXT: .LBB130_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_setpc_b64 s[30:31] + %cmp = icmp eq i32 %b, 0 + br i1 %cmp, label %cmp.true, label %cmp.false +cmp.true: + %a1 = fadd <8 x double> %a, splat (double 1.000000e+00) + %a2 = bitcast <8 x double> %a1 to <32 x half> + br label %end +cmp.false: + %a3 = bitcast <8 x double> %a to <32 x half> + br label %end +end: + %phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] + ret <32 x half> %phi +} + + +define <8 x i64> @v_bitcast_v32f16_to_v8i64(<32 x half> %a, i32 %b) { +; GCN-LABEL: v_bitcast_v32f16_to_v8i64: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:4 +; GCN-NEXT: v_cvt_f16_f32_e32 v45, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v44, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v43, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v42, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v41, v5 +; GCN-NEXT: v_cvt_f16_f32_e32 v52, v4 +; GCN-NEXT: v_cvt_f16_f32_e32 v40, v7 +; GCN-NEXT: v_cvt_f16_f32_e32 v50, v6 +; GCN-NEXT: v_cvt_f16_f32_e32 v55, v9 +; GCN-NEXT: v_cvt_f16_f32_e32 v48, v8 +; GCN-NEXT: v_cvt_f16_f32_e32 v54, v11 +; GCN-NEXT: v_cvt_f16_f32_e32 v38, v10 +; GCN-NEXT: v_cvt_f16_f32_e32 v53, v13 +; GCN-NEXT: v_cvt_f16_f32_e32 v36, v12 +; GCN-NEXT: v_cvt_f16_f32_e32 v51, v15 +; GCN-NEXT: v_cvt_f16_f32_e32 v34, v14 +; GCN-NEXT: v_cvt_f16_f32_e32 v49, v17 +; GCN-NEXT: v_cvt_f16_f32_e32 v33, v16 +; GCN-NEXT: v_cvt_f16_f32_e32 v39, v19 +; GCN-NEXT: v_cvt_f16_f32_e32 v32, v18 +; GCN-NEXT: v_cvt_f16_f32_e32 v37, v21 +; GCN-NEXT: v_cvt_f16_f32_e32 v31, v20 +; GCN-NEXT: v_cvt_f16_f32_e32 v35, v23 +; GCN-NEXT: v_cvt_f16_f32_e32 v21, v22 +; GCN-NEXT: v_cvt_f16_f32_e32 v25, v25 +; GCN-NEXT: v_cvt_f16_f32_e32 v19, v24 +; GCN-NEXT: v_cvt_f16_f32_e32 v23, v27 +; GCN-NEXT: v_cvt_f16_f32_e32 v18, v26 +; GCN-NEXT: v_cvt_f16_f32_e32 v22, v29 +; GCN-NEXT: v_cvt_f16_f32_e32 v17, v28 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v47 +; GCN-NEXT: v_cvt_f16_f32_e32 v20, v46 +; GCN-NEXT: v_cvt_f16_f32_e32 v16, v30 +; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB131_2 +; GCN-NEXT: ; %bb.1: ; %cmp.false +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v45 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v43 +; GCN-NEXT: v_or_b32_e32 v0, v44, v0 +; GCN-NEXT: v_or_b32_e32 v1, v42, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v41 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v40 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v55 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v54 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v53 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v51 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v49 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v39 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v37 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v35 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v22 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v20 +; GCN-NEXT: v_or_b32_e32 v2, v52, v2 +; GCN-NEXT: v_or_b32_e32 v3, v50, v3 +; GCN-NEXT: v_or_b32_e32 v4, v48, v4 +; GCN-NEXT: v_or_b32_e32 v5, v38, v5 +; GCN-NEXT: v_or_b32_e32 v6, v36, v6 +; GCN-NEXT: v_or_b32_e32 v7, v34, v7 +; GCN-NEXT: v_or_b32_e32 v8, v33, v8 +; GCN-NEXT: v_or_b32_e32 v9, v32, v9 +; GCN-NEXT: v_or_b32_e32 v10, v31, v10 +; GCN-NEXT: v_or_b32_e32 v11, v21, v11 +; GCN-NEXT: v_or_b32_e32 v12, v19, v12 +; GCN-NEXT: v_or_b32_e32 v13, v18, v13 +; GCN-NEXT: v_or_b32_e32 v14, v17, v14 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: ; implicit-def: $vgpr45 +; GCN-NEXT: ; implicit-def: $vgpr44 +; GCN-NEXT: ; implicit-def: $vgpr43 +; GCN-NEXT: ; implicit-def: $vgpr42 +; GCN-NEXT: ; implicit-def: $vgpr41 +; GCN-NEXT: ; implicit-def: $vgpr52 +; GCN-NEXT: ; implicit-def: $vgpr40 +; GCN-NEXT: ; implicit-def: $vgpr50 +; GCN-NEXT: ; implicit-def: $vgpr55 +; GCN-NEXT: ; implicit-def: $vgpr48 +; GCN-NEXT: ; implicit-def: $vgpr54 +; GCN-NEXT: ; implicit-def: $vgpr38 +; GCN-NEXT: ; implicit-def: $vgpr53 +; GCN-NEXT: ; implicit-def: $vgpr36 +; GCN-NEXT: ; implicit-def: $vgpr51 +; GCN-NEXT: ; implicit-def: $vgpr34 +; GCN-NEXT: ; implicit-def: $vgpr49 +; GCN-NEXT: ; implicit-def: $vgpr33 +; GCN-NEXT: ; implicit-def: $vgpr39 +; GCN-NEXT: ; implicit-def: $vgpr32 +; GCN-NEXT: ; implicit-def: $vgpr37 +; GCN-NEXT: ; implicit-def: $vgpr31 +; GCN-NEXT: ; implicit-def: $vgpr35 +; GCN-NEXT: ; implicit-def: $vgpr21 +; GCN-NEXT: ; implicit-def: $vgpr25 +; GCN-NEXT: ; implicit-def: $vgpr19 +; GCN-NEXT: ; implicit-def: $vgpr23 +; GCN-NEXT: ; implicit-def: $vgpr18 +; GCN-NEXT: ; implicit-def: $vgpr22 +; GCN-NEXT: ; implicit-def: $vgpr17 +; GCN-NEXT: ; implicit-def: $vgpr20 +; GCN-NEXT: ; implicit-def: $vgpr16 +; GCN-NEXT: .LBB131_2: ; %Flow +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB131_4 +; GCN-NEXT: ; %bb.3: ; %cmp.true +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v45 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, v44 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v43 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v42 +; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 +; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 +; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 +; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_or_b32_e32 v0, v1, v0 +; GCN-NEXT: v_or_b32_e32 v1, v3, v2 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v41 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v52 +; GCN-NEXT: v_cvt_f32_f16_e32 v4, v40 +; GCN-NEXT: v_cvt_f32_f16_e32 v5, v50 +; GCN-NEXT: v_cvt_f32_f16_e32 v6, v55 +; GCN-NEXT: v_cvt_f32_f16_e32 v7, v48 +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v54 +; GCN-NEXT: v_cvt_f32_f16_e32 v9, v38 +; GCN-NEXT: v_cvt_f32_f16_e32 v10, v53 +; GCN-NEXT: v_cvt_f32_f16_e32 v11, v36 +; GCN-NEXT: v_cvt_f32_f16_e32 v12, v51 +; GCN-NEXT: v_cvt_f32_f16_e32 v13, v34 +; GCN-NEXT: v_cvt_f32_f16_e32 v14, v49 +; GCN-NEXT: v_cvt_f32_f16_e32 v15, v33 +; GCN-NEXT: v_cvt_f32_f16_e32 v24, v39 +; GCN-NEXT: v_cvt_f32_f16_e32 v26, v32 +; GCN-NEXT: v_cvt_f32_f16_e32 v27, v37 +; GCN-NEXT: v_cvt_f32_f16_e32 v28, v31 +; GCN-NEXT: v_cvt_f32_f16_e32 v29, v35 +; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v25 +; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 +; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23 +; GCN-NEXT: v_cvt_f32_f16_e32 v18, v18 +; GCN-NEXT: v_cvt_f32_f16_e32 v22, v22 +; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 +; GCN-NEXT: v_cvt_f32_f16_e32 v20, v20 +; GCN-NEXT: v_cvt_f32_f16_e32 v16, v16 +; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 +; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 +; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 +; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 +; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6 +; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7 +; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8 +; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9 +; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10 +; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11 +; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12 +; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13 +; GCN-NEXT: v_add_f32_e32 v14, 0x38000000, v14 +; GCN-NEXT: v_add_f32_e32 v15, 0x38000000, v15 +; GCN-NEXT: v_add_f32_e32 v24, 0x38000000, v24 +; GCN-NEXT: v_add_f32_e32 v26, 0x38000000, v26 +; GCN-NEXT: v_add_f32_e32 v27, 0x38000000, v27 +; GCN-NEXT: v_add_f32_e32 v28, 0x38000000, v28 +; GCN-NEXT: v_add_f32_e32 v29, 0x38000000, v29 +; GCN-NEXT: v_add_f32_e32 v21, 0x38000000, v21 +; GCN-NEXT: v_add_f32_e32 v25, 0x38000000, v25 +; GCN-NEXT: v_add_f32_e32 v19, 0x38000000, v19 +; GCN-NEXT: v_add_f32_e32 v23, 0x38000000, v23 +; GCN-NEXT: v_add_f32_e32 v18, 0x38000000, v18 +; GCN-NEXT: v_add_f32_e32 v22, 0x38000000, v22 +; GCN-NEXT: v_add_f32_e32 v17, 0x38000000, v17 +; GCN-NEXT: v_add_f32_e32 v20, 0x38000000, v20 +; GCN-NEXT: v_add_f32_e32 v16, 0x38000000, v16 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 +; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 +; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 +; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 +; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10 +; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11 +; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12 +; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13 +; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14 +; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15 +; GCN-NEXT: v_cvt_f16_f32_e32 v24, v24 +; GCN-NEXT: v_cvt_f16_f32_e32 v26, v26 +; GCN-NEXT: v_cvt_f16_f32_e32 v27, v27 +; GCN-NEXT: v_cvt_f16_f32_e32 v28, v28 +; GCN-NEXT: v_cvt_f16_f32_e32 v29, v29 +; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 +; GCN-NEXT: v_cvt_f16_f32_e32 v25, v25 +; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 +; GCN-NEXT: v_cvt_f16_f32_e32 v23, v23 +; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 +; GCN-NEXT: v_cvt_f16_f32_e32 v22, v22 +; GCN-NEXT: v_cvt_f16_f32_e32 v17, v17 +; GCN-NEXT: v_cvt_f16_f32_e32 v20, v20 +; GCN-NEXT: v_cvt_f16_f32_e32 v16, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v29 +; GCN-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_or_b32_e32 v2, v3, v2 +; GCN-NEXT: v_or_b32_e32 v3, v5, v4 +; GCN-NEXT: v_or_b32_e32 v4, v7, v6 +; GCN-NEXT: v_or_b32_e32 v5, v9, v8 +; GCN-NEXT: v_or_b32_e32 v6, v11, v10 +; GCN-NEXT: v_or_b32_e32 v7, v13, v12 +; GCN-NEXT: v_or_b32_e32 v8, v15, v14 +; GCN-NEXT: v_or_b32_e32 v9, v26, v24 +; GCN-NEXT: v_or_b32_e32 v10, v28, v27 +; GCN-NEXT: v_or_b32_e32 v11, v21, v29 +; GCN-NEXT: v_or_b32_e32 v12, v19, v25 +; GCN-NEXT: v_or_b32_e32 v13, v18, v23 +; GCN-NEXT: v_or_b32_e32 v14, v17, v22 +; GCN-NEXT: v_or_b32_e32 v15, v16, v20 +; GCN-NEXT: .LBB131_4: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32f16_to_v8i64: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; VI-NEXT: s_cbranch_execz .LBB131_2 +; VI-NEXT: ; %bb.1: ; %cmp.true +; VI-NEXT: v_mov_b32_e32 v16, 0x200 +; VI-NEXT: v_add_f16_sdwa v17, v15, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v15, 0x200, v15 +; VI-NEXT: v_or_b32_e32 v15, v15, v17 +; VI-NEXT: v_add_f16_sdwa v17, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v14, 0x200, v14 +; VI-NEXT: v_or_b32_e32 v14, v14, v17 +; VI-NEXT: v_add_f16_sdwa v17, v13, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v13, 0x200, v13 +; VI-NEXT: v_or_b32_e32 v13, v13, v17 +; VI-NEXT: v_add_f16_sdwa v17, v12, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v12, 0x200, v12 +; VI-NEXT: v_or_b32_e32 v12, v12, v17 +; VI-NEXT: v_add_f16_sdwa v17, v11, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v11, 0x200, v11 +; VI-NEXT: v_or_b32_e32 v11, v11, v17 +; VI-NEXT: v_add_f16_sdwa v17, v10, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v10, 0x200, v10 +; VI-NEXT: v_or_b32_e32 v10, v10, v17 +; VI-NEXT: v_add_f16_sdwa v17, v9, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v9, 0x200, v9 +; VI-NEXT: v_or_b32_e32 v9, v9, v17 +; VI-NEXT: v_add_f16_sdwa v17, v8, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v8, 0x200, v8 +; VI-NEXT: v_or_b32_e32 v8, v8, v17 +; VI-NEXT: v_add_f16_sdwa v17, v7, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v7, 0x200, v7 +; VI-NEXT: v_or_b32_e32 v7, v7, v17 +; VI-NEXT: v_add_f16_sdwa v17, v6, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v6, 0x200, v6 +; VI-NEXT: v_or_b32_e32 v6, v6, v17 +; VI-NEXT: v_add_f16_sdwa v17, v5, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v5, 0x200, v5 +; VI-NEXT: v_or_b32_e32 v5, v5, v17 +; VI-NEXT: v_add_f16_sdwa v17, v4, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v4, 0x200, v4 +; VI-NEXT: v_or_b32_e32 v4, v4, v17 +; VI-NEXT: v_add_f16_sdwa v17, v3, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v3, 0x200, v3 +; VI-NEXT: v_or_b32_e32 v3, v3, v17 +; VI-NEXT: v_add_f16_sdwa v17, v2, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v2, 0x200, v2 +; VI-NEXT: v_or_b32_e32 v2, v2, v17 +; VI-NEXT: v_add_f16_sdwa v17, v1, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 +; VI-NEXT: v_add_f16_sdwa v16, v0, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 +; VI-NEXT: v_or_b32_e32 v1, v1, v17 +; VI-NEXT: v_or_b32_e32 v0, v0, v16 +; VI-NEXT: .LBB131_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32f16_to_v8i64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9-NEXT: s_cbranch_execz .LBB131_2 +; GFX9-NEXT: ; %bb.1: ; %cmp.true +; GFX9-NEXT: s_movk_i32 s6, 0x200 +; GFX9-NEXT: v_pk_add_f16 v15, v15, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v14, v14, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] +; GFX9-NEXT: .LBB131_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32f16_to_v8i64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16 +; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-NEXT: s_cbranch_execz .LBB131_2 +; GFX11-NEXT: ; %bb.1: ; %cmp.true +; GFX11-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] +; GFX11-NEXT: .LBB131_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_setpc_b64 s[30:31] + %cmp = icmp eq i32 %b, 0 + br i1 %cmp, label %cmp.true, label %cmp.false +cmp.true: + %a1 = fadd <32 x half> %a, splat (half 0xH0200) + %a2 = bitcast <32 x half> %a1 to <8 x i64> + br label %end +cmp.false: + %a3 = bitcast <32 x half> %a to <8 x i64> + br label %end +end: + %phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ] + ret <8 x i64> %phi +} + + +define <8 x double> @v_bitcast_v32f16_to_v8f64(<32 x half> %a, i32 %b) { +; GCN-LABEL: v_bitcast_v32f16_to_v8f64: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:4 +; GCN-NEXT: v_cvt_f16_f32_e32 v45, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v44, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v43, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v42, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v41, v5 +; GCN-NEXT: v_cvt_f16_f32_e32 v52, v4 +; GCN-NEXT: v_cvt_f16_f32_e32 v40, v7 +; GCN-NEXT: v_cvt_f16_f32_e32 v50, v6 +; GCN-NEXT: v_cvt_f16_f32_e32 v55, v9 +; GCN-NEXT: v_cvt_f16_f32_e32 v48, v8 +; GCN-NEXT: v_cvt_f16_f32_e32 v54, v11 +; GCN-NEXT: v_cvt_f16_f32_e32 v38, v10 +; GCN-NEXT: v_cvt_f16_f32_e32 v53, v13 +; GCN-NEXT: v_cvt_f16_f32_e32 v36, v12 +; GCN-NEXT: v_cvt_f16_f32_e32 v51, v15 +; GCN-NEXT: v_cvt_f16_f32_e32 v34, v14 +; GCN-NEXT: v_cvt_f16_f32_e32 v49, v17 +; GCN-NEXT: v_cvt_f16_f32_e32 v33, v16 +; GCN-NEXT: v_cvt_f16_f32_e32 v39, v19 +; GCN-NEXT: v_cvt_f16_f32_e32 v32, v18 +; GCN-NEXT: v_cvt_f16_f32_e32 v37, v21 +; GCN-NEXT: v_cvt_f16_f32_e32 v31, v20 +; GCN-NEXT: v_cvt_f16_f32_e32 v35, v23 +; GCN-NEXT: v_cvt_f16_f32_e32 v21, v22 +; GCN-NEXT: v_cvt_f16_f32_e32 v25, v25 +; GCN-NEXT: v_cvt_f16_f32_e32 v19, v24 +; GCN-NEXT: v_cvt_f16_f32_e32 v23, v27 +; GCN-NEXT: v_cvt_f16_f32_e32 v18, v26 +; GCN-NEXT: v_cvt_f16_f32_e32 v22, v29 +; GCN-NEXT: v_cvt_f16_f32_e32 v17, v28 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v47 +; GCN-NEXT: v_cvt_f16_f32_e32 v20, v46 +; GCN-NEXT: v_cvt_f16_f32_e32 v16, v30 +; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB132_2 +; GCN-NEXT: ; %bb.1: ; %cmp.false +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v45 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v43 +; GCN-NEXT: v_or_b32_e32 v0, v44, v0 +; GCN-NEXT: v_or_b32_e32 v1, v42, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v41 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v40 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v55 +; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v54 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v53 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v51 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v49 +; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v39 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v37 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v35 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v22 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v20 +; GCN-NEXT: v_or_b32_e32 v2, v52, v2 +; GCN-NEXT: v_or_b32_e32 v3, v50, v3 +; GCN-NEXT: v_or_b32_e32 v4, v48, v4 +; GCN-NEXT: v_or_b32_e32 v5, v38, v5 +; GCN-NEXT: v_or_b32_e32 v6, v36, v6 +; GCN-NEXT: v_or_b32_e32 v7, v34, v7 +; GCN-NEXT: v_or_b32_e32 v8, v33, v8 +; GCN-NEXT: v_or_b32_e32 v9, v32, v9 +; GCN-NEXT: v_or_b32_e32 v10, v31, v10 +; GCN-NEXT: v_or_b32_e32 v11, v21, v11 +; GCN-NEXT: v_or_b32_e32 v12, v19, v12 +; GCN-NEXT: v_or_b32_e32 v13, v18, v13 +; GCN-NEXT: v_or_b32_e32 v14, v17, v14 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: ; implicit-def: $vgpr45 +; GCN-NEXT: ; implicit-def: $vgpr44 +; GCN-NEXT: ; implicit-def: $vgpr43 +; GCN-NEXT: ; implicit-def: $vgpr42 +; GCN-NEXT: ; implicit-def: $vgpr41 +; GCN-NEXT: ; implicit-def: $vgpr52 +; GCN-NEXT: ; implicit-def: $vgpr40 +; GCN-NEXT: ; implicit-def: $vgpr50 +; GCN-NEXT: ; implicit-def: $vgpr55 +; GCN-NEXT: ; implicit-def: $vgpr48 +; GCN-NEXT: ; implicit-def: $vgpr54 +; GCN-NEXT: ; implicit-def: $vgpr38 +; GCN-NEXT: ; implicit-def: $vgpr53 +; GCN-NEXT: ; implicit-def: $vgpr36 +; GCN-NEXT: ; implicit-def: $vgpr51 +; GCN-NEXT: ; implicit-def: $vgpr34 +; GCN-NEXT: ; implicit-def: $vgpr49 +; GCN-NEXT: ; implicit-def: $vgpr33 +; GCN-NEXT: ; implicit-def: $vgpr39 +; GCN-NEXT: ; implicit-def: $vgpr32 +; GCN-NEXT: ; implicit-def: $vgpr37 +; GCN-NEXT: ; implicit-def: $vgpr31 +; GCN-NEXT: ; implicit-def: $vgpr35 +; GCN-NEXT: ; implicit-def: $vgpr21 +; GCN-NEXT: ; implicit-def: $vgpr25 +; GCN-NEXT: ; implicit-def: $vgpr19 +; GCN-NEXT: ; implicit-def: $vgpr23 +; GCN-NEXT: ; implicit-def: $vgpr18 +; GCN-NEXT: ; implicit-def: $vgpr22 +; GCN-NEXT: ; implicit-def: $vgpr17 +; GCN-NEXT: ; implicit-def: $vgpr20 +; GCN-NEXT: ; implicit-def: $vgpr16 +; GCN-NEXT: .LBB132_2: ; %Flow +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB132_4 +; GCN-NEXT: ; %bb.3: ; %cmp.true +; GCN-NEXT: v_cvt_f32_f16_e32 v0, v45 +; GCN-NEXT: v_cvt_f32_f16_e32 v1, v44 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v43 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v42 +; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 +; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 +; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 +; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_or_b32_e32 v0, v1, v0 +; GCN-NEXT: v_or_b32_e32 v1, v3, v2 +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v41 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v52 +; GCN-NEXT: v_cvt_f32_f16_e32 v4, v40 +; GCN-NEXT: v_cvt_f32_f16_e32 v5, v50 +; GCN-NEXT: v_cvt_f32_f16_e32 v6, v55 +; GCN-NEXT: v_cvt_f32_f16_e32 v7, v48 +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v54 +; GCN-NEXT: v_cvt_f32_f16_e32 v9, v38 +; GCN-NEXT: v_cvt_f32_f16_e32 v10, v53 +; GCN-NEXT: v_cvt_f32_f16_e32 v11, v36 +; GCN-NEXT: v_cvt_f32_f16_e32 v12, v51 +; GCN-NEXT: v_cvt_f32_f16_e32 v13, v34 +; GCN-NEXT: v_cvt_f32_f16_e32 v14, v49 +; GCN-NEXT: v_cvt_f32_f16_e32 v15, v33 +; GCN-NEXT: v_cvt_f32_f16_e32 v24, v39 +; GCN-NEXT: v_cvt_f32_f16_e32 v26, v32 +; GCN-NEXT: v_cvt_f32_f16_e32 v27, v37 +; GCN-NEXT: v_cvt_f32_f16_e32 v28, v31 +; GCN-NEXT: v_cvt_f32_f16_e32 v29, v35 +; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v25 +; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 +; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23 +; GCN-NEXT: v_cvt_f32_f16_e32 v18, v18 +; GCN-NEXT: v_cvt_f32_f16_e32 v22, v22 +; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 +; GCN-NEXT: v_cvt_f32_f16_e32 v20, v20 +; GCN-NEXT: v_cvt_f32_f16_e32 v16, v16 +; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 +; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 +; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 +; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 +; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6 +; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7 +; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8 +; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9 +; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10 +; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11 +; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12 +; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13 +; GCN-NEXT: v_add_f32_e32 v14, 0x38000000, v14 +; GCN-NEXT: v_add_f32_e32 v15, 0x38000000, v15 +; GCN-NEXT: v_add_f32_e32 v24, 0x38000000, v24 +; GCN-NEXT: v_add_f32_e32 v26, 0x38000000, v26 +; GCN-NEXT: v_add_f32_e32 v27, 0x38000000, v27 +; GCN-NEXT: v_add_f32_e32 v28, 0x38000000, v28 +; GCN-NEXT: v_add_f32_e32 v29, 0x38000000, v29 +; GCN-NEXT: v_add_f32_e32 v21, 0x38000000, v21 +; GCN-NEXT: v_add_f32_e32 v25, 0x38000000, v25 +; GCN-NEXT: v_add_f32_e32 v19, 0x38000000, v19 +; GCN-NEXT: v_add_f32_e32 v23, 0x38000000, v23 +; GCN-NEXT: v_add_f32_e32 v18, 0x38000000, v18 +; GCN-NEXT: v_add_f32_e32 v22, 0x38000000, v22 +; GCN-NEXT: v_add_f32_e32 v17, 0x38000000, v17 +; GCN-NEXT: v_add_f32_e32 v20, 0x38000000, v20 +; GCN-NEXT: v_add_f32_e32 v16, 0x38000000, v16 +; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 +; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 +; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 +; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 +; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10 +; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11 +; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12 +; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13 +; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14 +; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15 +; GCN-NEXT: v_cvt_f16_f32_e32 v24, v24 +; GCN-NEXT: v_cvt_f16_f32_e32 v26, v26 +; GCN-NEXT: v_cvt_f16_f32_e32 v27, v27 +; GCN-NEXT: v_cvt_f16_f32_e32 v28, v28 +; GCN-NEXT: v_cvt_f16_f32_e32 v29, v29 +; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 +; GCN-NEXT: v_cvt_f16_f32_e32 v25, v25 +; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 +; GCN-NEXT: v_cvt_f16_f32_e32 v23, v23 +; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 +; GCN-NEXT: v_cvt_f16_f32_e32 v22, v22 +; GCN-NEXT: v_cvt_f16_f32_e32 v17, v17 +; GCN-NEXT: v_cvt_f16_f32_e32 v20, v20 +; GCN-NEXT: v_cvt_f16_f32_e32 v16, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v29 +; GCN-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_or_b32_e32 v2, v3, v2 +; GCN-NEXT: v_or_b32_e32 v3, v5, v4 +; GCN-NEXT: v_or_b32_e32 v4, v7, v6 +; GCN-NEXT: v_or_b32_e32 v5, v9, v8 +; GCN-NEXT: v_or_b32_e32 v6, v11, v10 +; GCN-NEXT: v_or_b32_e32 v7, v13, v12 +; GCN-NEXT: v_or_b32_e32 v8, v15, v14 +; GCN-NEXT: v_or_b32_e32 v9, v26, v24 +; GCN-NEXT: v_or_b32_e32 v10, v28, v27 +; GCN-NEXT: v_or_b32_e32 v11, v21, v29 +; GCN-NEXT: v_or_b32_e32 v12, v19, v25 +; GCN-NEXT: v_or_b32_e32 v13, v18, v23 +; GCN-NEXT: v_or_b32_e32 v14, v17, v22 +; GCN-NEXT: v_or_b32_e32 v15, v16, v20 +; GCN-NEXT: .LBB132_4: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32f16_to_v8f64: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; VI-NEXT: s_cbranch_execz .LBB132_2 +; VI-NEXT: ; %bb.1: ; %cmp.true +; VI-NEXT: v_mov_b32_e32 v16, 0x200 +; VI-NEXT: v_add_f16_sdwa v17, v15, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v15, 0x200, v15 +; VI-NEXT: v_or_b32_e32 v15, v15, v17 +; VI-NEXT: v_add_f16_sdwa v17, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v14, 0x200, v14 +; VI-NEXT: v_or_b32_e32 v14, v14, v17 +; VI-NEXT: v_add_f16_sdwa v17, v13, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v13, 0x200, v13 +; VI-NEXT: v_or_b32_e32 v13, v13, v17 +; VI-NEXT: v_add_f16_sdwa v17, v12, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v12, 0x200, v12 +; VI-NEXT: v_or_b32_e32 v12, v12, v17 +; VI-NEXT: v_add_f16_sdwa v17, v11, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v11, 0x200, v11 +; VI-NEXT: v_or_b32_e32 v11, v11, v17 +; VI-NEXT: v_add_f16_sdwa v17, v10, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v10, 0x200, v10 +; VI-NEXT: v_or_b32_e32 v10, v10, v17 +; VI-NEXT: v_add_f16_sdwa v17, v9, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v9, 0x200, v9 +; VI-NEXT: v_or_b32_e32 v9, v9, v17 +; VI-NEXT: v_add_f16_sdwa v17, v8, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v8, 0x200, v8 +; VI-NEXT: v_or_b32_e32 v8, v8, v17 +; VI-NEXT: v_add_f16_sdwa v17, v7, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v7, 0x200, v7 +; VI-NEXT: v_or_b32_e32 v7, v7, v17 +; VI-NEXT: v_add_f16_sdwa v17, v6, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v6, 0x200, v6 +; VI-NEXT: v_or_b32_e32 v6, v6, v17 +; VI-NEXT: v_add_f16_sdwa v17, v5, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v5, 0x200, v5 +; VI-NEXT: v_or_b32_e32 v5, v5, v17 +; VI-NEXT: v_add_f16_sdwa v17, v4, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v4, 0x200, v4 +; VI-NEXT: v_or_b32_e32 v4, v4, v17 +; VI-NEXT: v_add_f16_sdwa v17, v3, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v3, 0x200, v3 +; VI-NEXT: v_or_b32_e32 v3, v3, v17 +; VI-NEXT: v_add_f16_sdwa v17, v2, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v2, 0x200, v2 +; VI-NEXT: v_or_b32_e32 v2, v2, v17 +; VI-NEXT: v_add_f16_sdwa v17, v1, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 +; VI-NEXT: v_add_f16_sdwa v16, v0, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 +; VI-NEXT: v_or_b32_e32 v1, v1, v17 +; VI-NEXT: v_or_b32_e32 v0, v0, v16 +; VI-NEXT: .LBB132_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32f16_to_v8f64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9-NEXT: s_cbranch_execz .LBB132_2 +; GFX9-NEXT: ; %bb.1: ; %cmp.true +; GFX9-NEXT: s_movk_i32 s6, 0x200 +; GFX9-NEXT: v_pk_add_f16 v15, v15, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v14, v14, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] +; GFX9-NEXT: .LBB132_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32f16_to_v8f64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16 +; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-NEXT: s_cbranch_execz .LBB132_2 +; GFX11-NEXT: ; %bb.1: ; %cmp.true +; GFX11-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] +; GFX11-NEXT: .LBB132_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_setpc_b64 s[30:31] + %cmp = icmp eq i32 %b, 0 + br i1 %cmp, label %cmp.true, label %cmp.false +cmp.true: + %a1 = fadd <32 x half> %a, splat (half 0xH0200) + %a2 = bitcast <32 x half> %a1 to <8 x double> + br label %end +cmp.false: + %a3 = bitcast <32 x half> %a to <8 x double> + br label %end +end: + %phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ] + ret <8 x double> %phi +} + + +define <8 x i64> @v_bitcast_v32i16_to_v8i64(<32 x i16> %a, i32 %b) { +; GCN-LABEL: v_bitcast_v32i16_to_v8i64: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v38, v14 +; GCN-NEXT: v_mov_b32_e32 v37, v12 +; GCN-NEXT: v_mov_b32_e32 v36, v10 +; GCN-NEXT: v_mov_b32_e32 v35, v8 +; GCN-NEXT: v_mov_b32_e32 v34, v6 +; GCN-NEXT: v_mov_b32_e32 v33, v4 +; GCN-NEXT: v_mov_b32_e32 v32, v2 +; GCN-NEXT: v_mov_b32_e32 v31, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 +; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v55, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v39, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v49, 16, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v51, 16, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v29 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v53, 16, v0 +; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: s_cbranch_execnz .LBB133_3 +; GCN-NEXT: ; %bb.1: ; %Flow +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GCN-NEXT: s_cbranch_execnz .LBB133_4 +; GCN-NEXT: .LBB133_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-NEXT: .LBB133_3: ; %cmp.false +; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v31 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v32 +; GCN-NEXT: v_or_b32_e32 v0, v0, v54 +; GCN-NEXT: v_or_b32_e32 v1, v1, v55 +; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v33 +; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v34 +; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v35 +; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v36 +; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v37 +; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v38 +; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v16 +; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v18 +; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v20 +; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v22 +; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v24 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff, v26 +; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v28 +; GCN-NEXT: v_and_b32_e32 v15, 0xffff, v30 +; GCN-NEXT: v_or_b32_e32 v2, v2, v39 +; GCN-NEXT: v_or_b32_e32 v3, v3, v48 +; GCN-NEXT: v_or_b32_e32 v4, v4, v49 +; GCN-NEXT: v_or_b32_e32 v5, v5, v50 +; GCN-NEXT: v_or_b32_e32 v6, v6, v51 +; GCN-NEXT: v_or_b32_e32 v7, v7, v52 +; GCN-NEXT: v_or_b32_e32 v8, v8, v17 +; GCN-NEXT: v_or_b32_e32 v9, v9, v19 +; GCN-NEXT: v_or_b32_e32 v10, v10, v21 +; GCN-NEXT: v_or_b32_e32 v11, v11, v23 +; GCN-NEXT: v_or_b32_e32 v12, v12, v25 +; GCN-NEXT: v_or_b32_e32 v13, v13, v27 +; GCN-NEXT: v_or_b32_e32 v14, v14, v29 +; GCN-NEXT: v_or_b32_e32 v15, v15, v53 +; GCN-NEXT: ; implicit-def: $vgpr31 +; GCN-NEXT: ; implicit-def: $vgpr32 +; GCN-NEXT: ; implicit-def: $vgpr33 +; GCN-NEXT: ; implicit-def: $vgpr34 +; GCN-NEXT: ; implicit-def: $vgpr35 +; GCN-NEXT: ; implicit-def: $vgpr36 +; GCN-NEXT: ; implicit-def: $vgpr37 +; GCN-NEXT: ; implicit-def: $vgpr38 +; GCN-NEXT: ; implicit-def: $vgpr16 +; GCN-NEXT: ; implicit-def: $vgpr18 +; GCN-NEXT: ; implicit-def: $vgpr20 +; GCN-NEXT: ; implicit-def: $vgpr22 +; GCN-NEXT: ; implicit-def: $vgpr24 +; GCN-NEXT: ; implicit-def: $vgpr26 +; GCN-NEXT: ; implicit-def: $vgpr28 +; GCN-NEXT: ; implicit-def: $vgpr30 +; GCN-NEXT: ; implicit-def: $vgpr54 +; GCN-NEXT: ; implicit-def: $vgpr55 +; GCN-NEXT: ; implicit-def: $vgpr39 +; GCN-NEXT: ; implicit-def: $vgpr48 +; GCN-NEXT: ; implicit-def: $vgpr49 +; GCN-NEXT: ; implicit-def: $vgpr50 +; GCN-NEXT: ; implicit-def: $vgpr51 +; GCN-NEXT: ; implicit-def: $vgpr52 +; GCN-NEXT: ; implicit-def: $vgpr17 +; GCN-NEXT: ; implicit-def: $vgpr19 +; GCN-NEXT: ; implicit-def: $vgpr21 +; GCN-NEXT: ; implicit-def: $vgpr23 +; GCN-NEXT: ; implicit-def: $vgpr25 +; GCN-NEXT: ; implicit-def: $vgpr27 +; GCN-NEXT: ; implicit-def: $vgpr29 +; GCN-NEXT: ; implicit-def: $vgpr53 +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB133_2 +; GCN-NEXT: .LBB133_4: ; %cmp.true +; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v31 +; GCN-NEXT: s_mov_b32 s6, 0x30000 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v32 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v33 +; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v34 +; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v35 +; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v36 +; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v37 +; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v38 +; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v16 +; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v18 +; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v20 +; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v22 +; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v24 +; GCN-NEXT: v_add_i32_e32 v13, vcc, 3, v26 +; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v28 +; GCN-NEXT: v_add_i32_e32 v15, vcc, 3, v30 +; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5 +; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6 +; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7 +; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8 +; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v9 +; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10 +; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v11 +; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v12 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff, v13 +; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v14 +; GCN-NEXT: v_and_b32_e32 v15, 0xffff, v15 +; GCN-NEXT: v_or_b32_e32 v0, v54, v0 +; GCN-NEXT: v_or_b32_e32 v1, v55, v1 +; GCN-NEXT: v_or_b32_e32 v2, v39, v2 +; GCN-NEXT: v_or_b32_e32 v3, v48, v3 +; GCN-NEXT: v_or_b32_e32 v4, v49, v4 +; GCN-NEXT: v_or_b32_e32 v5, v50, v5 +; GCN-NEXT: v_or_b32_e32 v6, v51, v6 +; GCN-NEXT: v_or_b32_e32 v7, v52, v7 +; GCN-NEXT: v_or_b32_e32 v8, v17, v8 +; GCN-NEXT: v_or_b32_e32 v9, v19, v9 +; GCN-NEXT: v_or_b32_e32 v10, v21, v10 +; GCN-NEXT: v_or_b32_e32 v11, v23, v11 +; GCN-NEXT: v_or_b32_e32 v12, v25, v12 +; GCN-NEXT: v_or_b32_e32 v13, v27, v13 +; GCN-NEXT: v_or_b32_e32 v14, v29, v14 +; GCN-NEXT: v_or_b32_e32 v15, v53, v15 +; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, s6, v5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v6 +; GCN-NEXT: v_add_i32_e32 v7, vcc, s6, v7 +; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8 +; GCN-NEXT: v_add_i32_e32 v9, vcc, s6, v9 +; GCN-NEXT: v_add_i32_e32 v10, vcc, s6, v10 +; GCN-NEXT: v_add_i32_e32 v11, vcc, s6, v11 +; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v12 +; GCN-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13 +; GCN-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14 +; GCN-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15 +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32i16_to_v8i64: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; VI-NEXT: s_cbranch_execz .LBB133_2 +; VI-NEXT: ; %bb.1: ; %cmp.true +; VI-NEXT: v_mov_b32_e32 v17, 3 +; VI-NEXT: v_add_u16_e32 v16, 3, v15 +; VI-NEXT: v_add_u16_sdwa v15, v15, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v15, v16, v15 +; VI-NEXT: v_add_u16_e32 v16, 3, v14 +; VI-NEXT: v_add_u16_sdwa v14, v14, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v14, v16, v14 +; VI-NEXT: v_add_u16_e32 v16, 3, v13 +; VI-NEXT: v_add_u16_sdwa v13, v13, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v13, v16, v13 +; VI-NEXT: v_add_u16_e32 v16, 3, v12 +; VI-NEXT: v_add_u16_sdwa v12, v12, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v12, v16, v12 +; VI-NEXT: v_add_u16_e32 v16, 3, v11 +; VI-NEXT: v_add_u16_sdwa v11, v11, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v11, v16, v11 +; VI-NEXT: v_add_u16_e32 v16, 3, v10 +; VI-NEXT: v_add_u16_sdwa v10, v10, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v10, v16, v10 +; VI-NEXT: v_add_u16_e32 v16, 3, v9 +; VI-NEXT: v_add_u16_sdwa v9, v9, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v9, v16, v9 +; VI-NEXT: v_add_u16_e32 v16, 3, v8 +; VI-NEXT: v_add_u16_sdwa v8, v8, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v8, v16, v8 +; VI-NEXT: v_add_u16_e32 v16, 3, v7 +; VI-NEXT: v_add_u16_sdwa v7, v7, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v7, v16, v7 +; VI-NEXT: v_add_u16_e32 v16, 3, v6 +; VI-NEXT: v_add_u16_sdwa v6, v6, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v6, v16, v6 +; VI-NEXT: v_add_u16_e32 v16, 3, v5 +; VI-NEXT: v_add_u16_sdwa v5, v5, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v5, v16, v5 +; VI-NEXT: v_add_u16_e32 v16, 3, v4 +; VI-NEXT: v_add_u16_sdwa v4, v4, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v4, v16, v4 +; VI-NEXT: v_add_u16_e32 v16, 3, v3 +; VI-NEXT: v_add_u16_sdwa v3, v3, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v3, v16, v3 +; VI-NEXT: v_add_u16_e32 v16, 3, v2 +; VI-NEXT: v_add_u16_sdwa v2, v2, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v2, v16, v2 +; VI-NEXT: v_add_u16_e32 v16, 3, v1 +; VI-NEXT: v_add_u16_sdwa v1, v1, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v1, v16, v1 +; VI-NEXT: v_add_u16_e32 v16, 3, v0 +; VI-NEXT: v_add_u16_sdwa v0, v0, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v0, v16, v0 +; VI-NEXT: .LBB133_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32i16_to_v8i64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9-NEXT: s_cbranch_execz .LBB133_2 +; GFX9-NEXT: ; %bb.1: ; %cmp.true +; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] +; GFX9-NEXT: .LBB133_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32i16_to_v8i64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16 +; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-NEXT: s_cbranch_execz .LBB133_2 +; GFX11-NEXT: ; %bb.1: ; %cmp.true +; GFX11-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] +; GFX11-NEXT: .LBB133_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_setpc_b64 s[30:31] + %cmp = icmp eq i32 %b, 0 + br i1 %cmp, label %cmp.true, label %cmp.false +cmp.true: + %a1 = add <32 x i16> %a, splat (i16 3) + %a2 = bitcast <32 x i16> %a1 to <8 x i64> + br label %end +cmp.false: + %a3 = bitcast <32 x i16> %a to <8 x i64> + br label %end +end: + %phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ] + ret <8 x i64> %phi +} + + +define <8 x double> @v_bitcast_v32i16_to_v8f64(<32 x i16> %a, i32 %b) { +; GCN-LABEL: v_bitcast_v32i16_to_v8f64: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v38, v14 +; GCN-NEXT: v_mov_b32_e32 v37, v12 +; GCN-NEXT: v_mov_b32_e32 v36, v10 +; GCN-NEXT: v_mov_b32_e32 v35, v8 +; GCN-NEXT: v_mov_b32_e32 v34, v6 +; GCN-NEXT: v_mov_b32_e32 v33, v4 +; GCN-NEXT: v_mov_b32_e32 v32, v2 +; GCN-NEXT: v_mov_b32_e32 v31, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 +; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v55, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v39, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v49, 16, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v51, 16, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v29 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v53, 16, v0 +; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: s_cbranch_execnz .LBB134_3 +; GCN-NEXT: ; %bb.1: ; %Flow +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GCN-NEXT: s_cbranch_execnz .LBB134_4 +; GCN-NEXT: .LBB134_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-NEXT: .LBB134_3: ; %cmp.false +; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v31 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v32 +; GCN-NEXT: v_or_b32_e32 v0, v0, v54 +; GCN-NEXT: v_or_b32_e32 v1, v1, v55 +; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v33 +; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v34 +; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v35 +; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v36 +; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v37 +; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v38 +; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v16 +; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v18 +; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v20 +; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v22 +; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v24 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff, v26 +; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v28 +; GCN-NEXT: v_and_b32_e32 v15, 0xffff, v30 +; GCN-NEXT: v_or_b32_e32 v2, v2, v39 +; GCN-NEXT: v_or_b32_e32 v3, v3, v48 +; GCN-NEXT: v_or_b32_e32 v4, v4, v49 +; GCN-NEXT: v_or_b32_e32 v5, v5, v50 +; GCN-NEXT: v_or_b32_e32 v6, v6, v51 +; GCN-NEXT: v_or_b32_e32 v7, v7, v52 +; GCN-NEXT: v_or_b32_e32 v8, v8, v17 +; GCN-NEXT: v_or_b32_e32 v9, v9, v19 +; GCN-NEXT: v_or_b32_e32 v10, v10, v21 +; GCN-NEXT: v_or_b32_e32 v11, v11, v23 +; GCN-NEXT: v_or_b32_e32 v12, v12, v25 +; GCN-NEXT: v_or_b32_e32 v13, v13, v27 +; GCN-NEXT: v_or_b32_e32 v14, v14, v29 +; GCN-NEXT: v_or_b32_e32 v15, v15, v53 +; GCN-NEXT: ; implicit-def: $vgpr31 +; GCN-NEXT: ; implicit-def: $vgpr32 +; GCN-NEXT: ; implicit-def: $vgpr33 +; GCN-NEXT: ; implicit-def: $vgpr34 +; GCN-NEXT: ; implicit-def: $vgpr35 +; GCN-NEXT: ; implicit-def: $vgpr36 +; GCN-NEXT: ; implicit-def: $vgpr37 +; GCN-NEXT: ; implicit-def: $vgpr38 +; GCN-NEXT: ; implicit-def: $vgpr16 +; GCN-NEXT: ; implicit-def: $vgpr18 +; GCN-NEXT: ; implicit-def: $vgpr20 +; GCN-NEXT: ; implicit-def: $vgpr22 +; GCN-NEXT: ; implicit-def: $vgpr24 +; GCN-NEXT: ; implicit-def: $vgpr26 +; GCN-NEXT: ; implicit-def: $vgpr28 +; GCN-NEXT: ; implicit-def: $vgpr30 +; GCN-NEXT: ; implicit-def: $vgpr54 +; GCN-NEXT: ; implicit-def: $vgpr55 +; GCN-NEXT: ; implicit-def: $vgpr39 +; GCN-NEXT: ; implicit-def: $vgpr48 +; GCN-NEXT: ; implicit-def: $vgpr49 +; GCN-NEXT: ; implicit-def: $vgpr50 +; GCN-NEXT: ; implicit-def: $vgpr51 +; GCN-NEXT: ; implicit-def: $vgpr52 +; GCN-NEXT: ; implicit-def: $vgpr17 +; GCN-NEXT: ; implicit-def: $vgpr19 +; GCN-NEXT: ; implicit-def: $vgpr21 +; GCN-NEXT: ; implicit-def: $vgpr23 +; GCN-NEXT: ; implicit-def: $vgpr25 +; GCN-NEXT: ; implicit-def: $vgpr27 +; GCN-NEXT: ; implicit-def: $vgpr29 +; GCN-NEXT: ; implicit-def: $vgpr53 +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB134_2 +; GCN-NEXT: .LBB134_4: ; %cmp.true +; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v31 +; GCN-NEXT: s_mov_b32 s6, 0x30000 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v32 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v33 +; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v34 +; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v35 +; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v36 +; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v37 +; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v38 +; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v16 +; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v18 +; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v20 +; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v22 +; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v24 +; GCN-NEXT: v_add_i32_e32 v13, vcc, 3, v26 +; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v28 +; GCN-NEXT: v_add_i32_e32 v15, vcc, 3, v30 +; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5 +; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6 +; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7 +; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8 +; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v9 +; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10 +; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v11 +; GCN-NEXT: v_and_b32_e32 v12, 0xffff, v12 +; GCN-NEXT: v_and_b32_e32 v13, 0xffff, v13 +; GCN-NEXT: v_and_b32_e32 v14, 0xffff, v14 +; GCN-NEXT: v_and_b32_e32 v15, 0xffff, v15 +; GCN-NEXT: v_or_b32_e32 v0, v54, v0 +; GCN-NEXT: v_or_b32_e32 v1, v55, v1 +; GCN-NEXT: v_or_b32_e32 v2, v39, v2 +; GCN-NEXT: v_or_b32_e32 v3, v48, v3 +; GCN-NEXT: v_or_b32_e32 v4, v49, v4 +; GCN-NEXT: v_or_b32_e32 v5, v50, v5 +; GCN-NEXT: v_or_b32_e32 v6, v51, v6 +; GCN-NEXT: v_or_b32_e32 v7, v52, v7 +; GCN-NEXT: v_or_b32_e32 v8, v17, v8 +; GCN-NEXT: v_or_b32_e32 v9, v19, v9 +; GCN-NEXT: v_or_b32_e32 v10, v21, v10 +; GCN-NEXT: v_or_b32_e32 v11, v23, v11 +; GCN-NEXT: v_or_b32_e32 v12, v25, v12 +; GCN-NEXT: v_or_b32_e32 v13, v27, v13 +; GCN-NEXT: v_or_b32_e32 v14, v29, v14 +; GCN-NEXT: v_or_b32_e32 v15, v53, v15 +; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, s6, v5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v6 +; GCN-NEXT: v_add_i32_e32 v7, vcc, s6, v7 +; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8 +; GCN-NEXT: v_add_i32_e32 v9, vcc, s6, v9 +; GCN-NEXT: v_add_i32_e32 v10, vcc, s6, v10 +; GCN-NEXT: v_add_i32_e32 v11, vcc, s6, v11 +; GCN-NEXT: v_add_i32_e32 v12, vcc, s6, v12 +; GCN-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13 +; GCN-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14 +; GCN-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15 +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32i16_to_v8f64: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; VI-NEXT: s_cbranch_execz .LBB134_2 +; VI-NEXT: ; %bb.1: ; %cmp.true +; VI-NEXT: v_mov_b32_e32 v17, 3 +; VI-NEXT: v_add_u16_e32 v16, 3, v15 +; VI-NEXT: v_add_u16_sdwa v15, v15, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v15, v16, v15 +; VI-NEXT: v_add_u16_e32 v16, 3, v14 +; VI-NEXT: v_add_u16_sdwa v14, v14, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v14, v16, v14 +; VI-NEXT: v_add_u16_e32 v16, 3, v13 +; VI-NEXT: v_add_u16_sdwa v13, v13, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v13, v16, v13 +; VI-NEXT: v_add_u16_e32 v16, 3, v12 +; VI-NEXT: v_add_u16_sdwa v12, v12, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v12, v16, v12 +; VI-NEXT: v_add_u16_e32 v16, 3, v11 +; VI-NEXT: v_add_u16_sdwa v11, v11, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v11, v16, v11 +; VI-NEXT: v_add_u16_e32 v16, 3, v10 +; VI-NEXT: v_add_u16_sdwa v10, v10, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v10, v16, v10 +; VI-NEXT: v_add_u16_e32 v16, 3, v9 +; VI-NEXT: v_add_u16_sdwa v9, v9, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v9, v16, v9 +; VI-NEXT: v_add_u16_e32 v16, 3, v8 +; VI-NEXT: v_add_u16_sdwa v8, v8, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v8, v16, v8 +; VI-NEXT: v_add_u16_e32 v16, 3, v7 +; VI-NEXT: v_add_u16_sdwa v7, v7, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v7, v16, v7 +; VI-NEXT: v_add_u16_e32 v16, 3, v6 +; VI-NEXT: v_add_u16_sdwa v6, v6, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v6, v16, v6 +; VI-NEXT: v_add_u16_e32 v16, 3, v5 +; VI-NEXT: v_add_u16_sdwa v5, v5, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v5, v16, v5 +; VI-NEXT: v_add_u16_e32 v16, 3, v4 +; VI-NEXT: v_add_u16_sdwa v4, v4, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v4, v16, v4 +; VI-NEXT: v_add_u16_e32 v16, 3, v3 +; VI-NEXT: v_add_u16_sdwa v3, v3, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v3, v16, v3 +; VI-NEXT: v_add_u16_e32 v16, 3, v2 +; VI-NEXT: v_add_u16_sdwa v2, v2, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v2, v16, v2 +; VI-NEXT: v_add_u16_e32 v16, 3, v1 +; VI-NEXT: v_add_u16_sdwa v1, v1, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v1, v16, v1 +; VI-NEXT: v_add_u16_e32 v16, 3, v0 +; VI-NEXT: v_add_u16_sdwa v0, v0, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v0, v16, v0 +; VI-NEXT: .LBB134_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32i16_to_v8f64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9-NEXT: s_cbranch_execz .LBB134_2 +; GFX9-NEXT: ; %bb.1: ; %cmp.true +; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] +; GFX9-NEXT: .LBB134_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32i16_to_v8f64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16 +; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-NEXT: s_cbranch_execz .LBB134_2 +; GFX11-NEXT: ; %bb.1: ; %cmp.true +; GFX11-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] +; GFX11-NEXT: .LBB134_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_setpc_b64 s[30:31] + %cmp = icmp eq i32 %b, 0 + br i1 %cmp, label %cmp.true, label %cmp.false +cmp.true: + %a1 = add <32 x i16> %a, splat (i16 3) + %a2 = bitcast <32 x i16> %a1 to <8 x double> + br label %end +cmp.false: + %a3 = bitcast <32 x i16> %a to <8 x double> + br label %end +end: + %phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ] + ret <8 x double> %phi +} + + + + +define void @v_bitcast_v32f32_to_v64bf16(i32 %cond, ptr addrspace(1) %out, <32 x float> %value) { +; GCN-LABEL: v_bitcast_v32f32_to_v64bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 +; GCN-NEXT: v_mov_b32_e32 v58, 0 +; GCN-NEXT: v_mov_b32_e32 v59, 0 +; GCN-NEXT: v_mov_b32_e32 v56, 0 +; GCN-NEXT: v_mov_b32_e32 v57, 0 +; GCN-NEXT: v_mov_b32_e32 v46, 0 +; GCN-NEXT: v_mov_b32_e32 v47, 0 +; GCN-NEXT: v_mov_b32_e32 v44, 0 +; GCN-NEXT: v_mov_b32_e32 v45, 0 +; GCN-NEXT: v_mov_b32_e32 v42, 0 +; GCN-NEXT: v_mov_b32_e32 v43, 0 +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB135_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: s_waitcnt vmcnt(14) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v63 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v63 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v62 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v62 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v61 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v61 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v60 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v60 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v30 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v30 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v29 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v29 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v28 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v28 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v27 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v27 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v26 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v26 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v25 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v25 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v24 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v24 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v23 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v23 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v22 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v22 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v21 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v21 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v20 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v20 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v19 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v19 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v18 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v18 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: v_and_b32_e32 v31, 0xffff0000, v17 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v17 +; GCN-NEXT: v_and_b32_e32 v33, 0xffff0000, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v16 +; GCN-NEXT: v_and_b32_e32 v35, 0xffff0000, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v15 +; GCN-NEXT: v_and_b32_e32 v37, 0xffff0000, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v14 +; GCN-NEXT: v_and_b32_e32 v39, 0xffff0000, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v38, 16, v13 +; GCN-NEXT: v_and_b32_e32 v49, 0xffff0000, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 16, v12 +; GCN-NEXT: v_and_b32_e32 v51, 0xffff0000, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v11 +; GCN-NEXT: v_and_b32_e32 v53, 0xffff0000, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v10 +; GCN-NEXT: v_and_b32_e32 v55, 0xffff0000, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v9 +; GCN-NEXT: v_and_b32_e32 v41, 0xffff0000, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v40, 16, v8 +; GCN-NEXT: v_and_b32_e32 v43, 0xffff0000, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v42, 16, v7 +; GCN-NEXT: v_and_b32_e32 v45, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v44, 16, v6 +; GCN-NEXT: v_and_b32_e32 v47, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v46, 16, v5 +; GCN-NEXT: v_and_b32_e32 v57, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v56, 16, v4 +; GCN-NEXT: v_and_b32_e32 v59, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v58, 16, v3 +; GCN-NEXT: .LBB135_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v59 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v58 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v57 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v56 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v47 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v46 +; GCN-NEXT: v_alignbit_b32 v5, v5, v6, 16 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v45 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v44 +; GCN-NEXT: v_alignbit_b32 v6, v6, v7, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v43 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v42 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v41 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v40 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v54 +; GCN-NEXT: v_alignbit_b32 v5, v5, v6, 16 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v53 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v52 +; GCN-NEXT: v_alignbit_b32 v6, v6, v7, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v51 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v50 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v49 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v48 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v38 +; GCN-NEXT: v_alignbit_b32 v5, v5, v6, 16 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v37 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v36 +; GCN-NEXT: v_alignbit_b32 v6, v6, v7, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v35 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v34 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v32 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v31 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_alignbit_b32 v5, v5, v0, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:64 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:80 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:96 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:112 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32f32_to_v64bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; VI-NEXT: s_mov_b32 s4, 0 +; VI-NEXT: s_mov_b32 s19, s4 +; VI-NEXT: s_mov_b32 s5, s4 +; VI-NEXT: s_mov_b32 s6, s4 +; VI-NEXT: s_mov_b32 s7, s4 +; VI-NEXT: s_mov_b32 s8, s4 +; VI-NEXT: s_mov_b32 s9, s4 +; VI-NEXT: s_mov_b32 s10, s4 +; VI-NEXT: s_mov_b32 s11, s4 +; VI-NEXT: s_mov_b32 s12, s4 +; VI-NEXT: s_mov_b32 s13, s4 +; VI-NEXT: s_mov_b32 s14, s4 +; VI-NEXT: s_mov_b32 s15, s4 +; VI-NEXT: s_mov_b32 s16, s4 +; VI-NEXT: s_mov_b32 s17, s4 +; VI-NEXT: s_mov_b32 s18, s4 +; VI-NEXT: v_mov_b32_e32 v50, s19 +; VI-NEXT: v_mov_b32_e32 v49, s18 +; VI-NEXT: v_mov_b32_e32 v48, s17 +; VI-NEXT: v_mov_b32_e32 v47, s16 +; VI-NEXT: v_mov_b32_e32 v46, s15 +; VI-NEXT: v_mov_b32_e32 v45, s14 +; VI-NEXT: v_mov_b32_e32 v44, s13 +; VI-NEXT: v_mov_b32_e32 v43, s12 +; VI-NEXT: v_mov_b32_e32 v42, s11 +; VI-NEXT: v_mov_b32_e32 v41, s10 +; VI-NEXT: v_mov_b32_e32 v40, s9 +; VI-NEXT: v_mov_b32_e32 v39, s8 +; VI-NEXT: v_mov_b32_e32 v38, s7 +; VI-NEXT: v_mov_b32_e32 v37, s6 +; VI-NEXT: v_mov_b32_e32 v36, s5 +; VI-NEXT: v_mov_b32_e32 v35, s4 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB135_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v50, v18 +; VI-NEXT: v_mov_b32_e32 v49, v17 +; VI-NEXT: v_mov_b32_e32 v48, v16 +; VI-NEXT: v_mov_b32_e32 v47, v15 +; VI-NEXT: v_mov_b32_e32 v46, v14 +; VI-NEXT: v_mov_b32_e32 v45, v13 +; VI-NEXT: v_mov_b32_e32 v44, v12 +; VI-NEXT: v_mov_b32_e32 v43, v11 +; VI-NEXT: v_mov_b32_e32 v42, v10 +; VI-NEXT: v_mov_b32_e32 v41, v9 +; VI-NEXT: v_mov_b32_e32 v40, v8 +; VI-NEXT: v_mov_b32_e32 v39, v7 +; VI-NEXT: v_mov_b32_e32 v38, v6 +; VI-NEXT: v_mov_b32_e32 v37, v5 +; VI-NEXT: v_mov_b32_e32 v36, v4 +; VI-NEXT: v_mov_b32_e32 v35, v3 +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: .LBB135_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[47:50] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[43:46] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[39:42] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[35:38] +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; VI-NEXT: s_movk_i32 s4, 0x70 +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x60 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dwordx4 v[3:4], v[17:20] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x50 +; VI-NEXT: flat_store_dwordx4 v[3:4], v[13:16] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, 64, v1 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[9:12] +; VI-NEXT: flat_store_dwordx4 v[0:1], v[5:8] +; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32f32_to_v64bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GFX9-NEXT: s_mov_b32 s4, 0 +; GFX9-NEXT: s_mov_b32 s19, s4 +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_mov_b32 s6, s4 +; GFX9-NEXT: s_mov_b32 s7, s4 +; GFX9-NEXT: s_mov_b32 s8, s4 +; GFX9-NEXT: s_mov_b32 s9, s4 +; GFX9-NEXT: s_mov_b32 s10, s4 +; GFX9-NEXT: s_mov_b32 s11, s4 +; GFX9-NEXT: s_mov_b32 s12, s4 +; GFX9-NEXT: s_mov_b32 s13, s4 +; GFX9-NEXT: s_mov_b32 s14, s4 +; GFX9-NEXT: s_mov_b32 s15, s4 +; GFX9-NEXT: s_mov_b32 s16, s4 +; GFX9-NEXT: s_mov_b32 s17, s4 +; GFX9-NEXT: s_mov_b32 s18, s4 +; GFX9-NEXT: v_mov_b32_e32 v50, s19 +; GFX9-NEXT: v_mov_b32_e32 v49, s18 +; GFX9-NEXT: v_mov_b32_e32 v48, s17 +; GFX9-NEXT: v_mov_b32_e32 v47, s16 +; GFX9-NEXT: v_mov_b32_e32 v46, s15 +; GFX9-NEXT: v_mov_b32_e32 v45, s14 +; GFX9-NEXT: v_mov_b32_e32 v44, s13 +; GFX9-NEXT: v_mov_b32_e32 v43, s12 +; GFX9-NEXT: v_mov_b32_e32 v42, s11 +; GFX9-NEXT: v_mov_b32_e32 v41, s10 +; GFX9-NEXT: v_mov_b32_e32 v40, s9 +; GFX9-NEXT: v_mov_b32_e32 v39, s8 +; GFX9-NEXT: v_mov_b32_e32 v38, s7 +; GFX9-NEXT: v_mov_b32_e32 v37, s6 +; GFX9-NEXT: v_mov_b32_e32 v36, s5 +; GFX9-NEXT: v_mov_b32_e32 v35, s4 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB135_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v50, v18 +; GFX9-NEXT: v_mov_b32_e32 v49, v17 +; GFX9-NEXT: v_mov_b32_e32 v48, v16 +; GFX9-NEXT: v_mov_b32_e32 v47, v15 +; GFX9-NEXT: v_mov_b32_e32 v46, v14 +; GFX9-NEXT: v_mov_b32_e32 v45, v13 +; GFX9-NEXT: v_mov_b32_e32 v44, v12 +; GFX9-NEXT: v_mov_b32_e32 v43, v11 +; GFX9-NEXT: v_mov_b32_e32 v42, v10 +; GFX9-NEXT: v_mov_b32_e32 v41, v9 +; GFX9-NEXT: v_mov_b32_e32 v40, v8 +; GFX9-NEXT: v_mov_b32_e32 v39, v7 +; GFX9-NEXT: v_mov_b32_e32 v38, v6 +; GFX9-NEXT: v_mov_b32_e32 v37, v5 +; GFX9-NEXT: v_mov_b32_e32 v36, v4 +; GFX9-NEXT: v_mov_b32_e32 v35, v3 +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: s_waitcnt vmcnt(28) +; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: .LBB135_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[47:50], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[43:46], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[39:42], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[35:38], off +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:112 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off offset:96 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off offset:80 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[3:6], off offset:64 +; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32f32_to_v64bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_mov_b32 s15, s0 +; GFX11-NEXT: s_mov_b32 s1, s0 +; GFX11-NEXT: s_mov_b32 s2, s0 +; GFX11-NEXT: s_mov_b32 s3, s0 +; GFX11-NEXT: s_mov_b32 s4, s0 +; GFX11-NEXT: s_mov_b32 s5, s0 +; GFX11-NEXT: s_mov_b32 s6, s0 +; GFX11-NEXT: s_mov_b32 s7, s0 +; GFX11-NEXT: s_mov_b32 s8, s0 +; GFX11-NEXT: s_mov_b32 s9, s0 +; GFX11-NEXT: s_mov_b32 s10, s0 +; GFX11-NEXT: s_mov_b32 s11, s0 +; GFX11-NEXT: s_mov_b32 s12, s0 +; GFX11-NEXT: s_mov_b32 s13, s0 +; GFX11-NEXT: s_mov_b32 s14, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v66, s15 :: v_dual_mov_b32 v65, s14 +; GFX11-NEXT: v_dual_mov_b32 v52, s1 :: v_dual_mov_b32 v51, s0 +; GFX11-NEXT: v_dual_mov_b32 v64, s13 :: v_dual_mov_b32 v63, s12 +; GFX11-NEXT: v_dual_mov_b32 v62, s11 :: v_dual_mov_b32 v61, s10 +; GFX11-NEXT: v_dual_mov_b32 v60, s9 :: v_dual_mov_b32 v59, s8 +; GFX11-NEXT: v_dual_mov_b32 v58, s7 :: v_dual_mov_b32 v57, s6 +; GFX11-NEXT: v_dual_mov_b32 v56, s5 :: v_dual_mov_b32 v55, s4 +; GFX11-NEXT: v_dual_mov_b32 v54, s3 :: v_dual_mov_b32 v53, s2 +; GFX11-NEXT: v_dual_mov_b32 v35, v51 :: v_dual_mov_b32 v36, v52 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_dual_mov_b32 v39, v55 :: v_dual_mov_b32 v40, v56 +; GFX11-NEXT: v_dual_mov_b32 v37, v53 :: v_dual_mov_b32 v38, v54 +; GFX11-NEXT: v_dual_mov_b32 v41, v57 :: v_dual_mov_b32 v42, v58 +; GFX11-NEXT: v_dual_mov_b32 v43, v59 :: v_dual_mov_b32 v44, v60 +; GFX11-NEXT: v_dual_mov_b32 v45, v61 :: v_dual_mov_b32 v46, v62 +; GFX11-NEXT: v_dual_mov_b32 v47, v63 :: v_dual_mov_b32 v48, v64 +; GFX11-NEXT: v_dual_mov_b32 v49, v65 :: v_dual_mov_b32 v50, v66 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB135_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v66, v18 :: v_dual_mov_b32 v65, v17 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v50, v34 :: v_dual_mov_b32 v49, v33 +; GFX11-NEXT: v_dual_mov_b32 v64, v16 :: v_dual_mov_b32 v63, v15 +; GFX11-NEXT: v_dual_mov_b32 v62, v14 :: v_dual_mov_b32 v61, v13 +; GFX11-NEXT: v_dual_mov_b32 v60, v12 :: v_dual_mov_b32 v59, v11 +; GFX11-NEXT: v_dual_mov_b32 v58, v10 :: v_dual_mov_b32 v57, v9 +; GFX11-NEXT: v_dual_mov_b32 v56, v8 :: v_dual_mov_b32 v55, v7 +; GFX11-NEXT: v_dual_mov_b32 v54, v6 :: v_dual_mov_b32 v53, v5 +; GFX11-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v51, v3 +; GFX11-NEXT: v_dual_mov_b32 v48, v32 :: v_dual_mov_b32 v47, v31 +; GFX11-NEXT: v_dual_mov_b32 v46, v30 :: v_dual_mov_b32 v45, v29 +; GFX11-NEXT: v_dual_mov_b32 v44, v28 :: v_dual_mov_b32 v43, v27 +; GFX11-NEXT: v_dual_mov_b32 v42, v26 :: v_dual_mov_b32 v41, v25 +; GFX11-NEXT: v_dual_mov_b32 v40, v24 :: v_dual_mov_b32 v39, v23 +; GFX11-NEXT: v_dual_mov_b32 v38, v22 :: v_dual_mov_b32 v37, v21 +; GFX11-NEXT: v_dual_mov_b32 v36, v20 :: v_dual_mov_b32 v35, v19 +; GFX11-NEXT: .LBB135_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x7 +; GFX11-NEXT: global_store_b128 v[1:2], v[63:66], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[59:62], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[55:58], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[51:54], off +; GFX11-NEXT: global_store_b128 v[1:2], v[47:50], off offset:112 +; GFX11-NEXT: global_store_b128 v[1:2], v[43:46], off offset:96 +; GFX11-NEXT: global_store_b128 v[1:2], v[39:42], off offset:80 +; GFX11-NEXT: global_store_b128 v[1:2], v[35:38], off offset:64 +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64 +; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x float> %value to <64 x bfloat> + br label %end + +end: + %phi = phi <64 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <64 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v32i32_to_v64bf16(i32 %cond, ptr addrspace(1) %out, <32 x i32> %value) { +; GCN-LABEL: v_bitcast_v32i32_to_v64bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 +; GCN-NEXT: v_mov_b32_e32 v58, 0 +; GCN-NEXT: v_mov_b32_e32 v59, 0 +; GCN-NEXT: v_mov_b32_e32 v56, 0 +; GCN-NEXT: v_mov_b32_e32 v57, 0 +; GCN-NEXT: v_mov_b32_e32 v46, 0 +; GCN-NEXT: v_mov_b32_e32 v47, 0 +; GCN-NEXT: v_mov_b32_e32 v44, 0 +; GCN-NEXT: v_mov_b32_e32 v45, 0 +; GCN-NEXT: v_mov_b32_e32 v42, 0 +; GCN-NEXT: v_mov_b32_e32 v43, 0 +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v35, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB136_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: s_waitcnt vmcnt(14) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v63 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v63 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v62 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v62 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v61 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v61 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v60 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v60 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v30 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v30 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v29 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v29 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v28 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v28 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v27 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v27 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v26 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v26 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v25 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v25 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v24 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v24 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v23 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v23 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v22 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v22 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v21 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v21 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v20 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v20 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v19 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v19 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v18 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v18 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: v_and_b32_e32 v31, 0xffff0000, v17 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v17 +; GCN-NEXT: v_and_b32_e32 v33, 0xffff0000, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v16 +; GCN-NEXT: v_and_b32_e32 v35, 0xffff0000, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v15 +; GCN-NEXT: v_and_b32_e32 v37, 0xffff0000, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v14 +; GCN-NEXT: v_and_b32_e32 v39, 0xffff0000, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v38, 16, v13 +; GCN-NEXT: v_and_b32_e32 v49, 0xffff0000, v12 +; GCN-NEXT: v_lshlrev_b32_e32 v48, 16, v12 +; GCN-NEXT: v_and_b32_e32 v51, 0xffff0000, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v50, 16, v11 +; GCN-NEXT: v_and_b32_e32 v53, 0xffff0000, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v10 +; GCN-NEXT: v_and_b32_e32 v55, 0xffff0000, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v9 +; GCN-NEXT: v_and_b32_e32 v41, 0xffff0000, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v40, 16, v8 +; GCN-NEXT: v_and_b32_e32 v43, 0xffff0000, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v42, 16, v7 +; GCN-NEXT: v_and_b32_e32 v45, 0xffff0000, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v44, 16, v6 +; GCN-NEXT: v_and_b32_e32 v47, 0xffff0000, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v46, 16, v5 +; GCN-NEXT: v_and_b32_e32 v57, 0xffff0000, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v56, 16, v4 +; GCN-NEXT: v_and_b32_e32 v59, 0xffff0000, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v58, 16, v3 +; GCN-NEXT: .LBB136_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v59 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v58 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v57 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v56 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v47 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v46 +; GCN-NEXT: v_alignbit_b32 v5, v5, v6, 16 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v45 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v44 +; GCN-NEXT: v_alignbit_b32 v6, v6, v7, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v43 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v42 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v41 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v40 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v54 +; GCN-NEXT: v_alignbit_b32 v5, v5, v6, 16 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v53 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v52 +; GCN-NEXT: v_alignbit_b32 v6, v6, v7, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v51 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v50 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v49 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v48 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v38 +; GCN-NEXT: v_alignbit_b32 v5, v5, v6, 16 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v37 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v36 +; GCN-NEXT: v_alignbit_b32 v6, v6, v7, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v35 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v34 +; GCN-NEXT: v_alignbit_b32 v3, v3, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v32 +; GCN-NEXT: v_alignbit_b32 v4, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v31 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_alignbit_b32 v5, v5, v0, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:64 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:80 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:96 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:112 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v32i32_to_v64bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; VI-NEXT: s_mov_b32 s4, 0 +; VI-NEXT: s_mov_b32 s19, s4 +; VI-NEXT: s_mov_b32 s5, s4 +; VI-NEXT: s_mov_b32 s6, s4 +; VI-NEXT: s_mov_b32 s7, s4 +; VI-NEXT: s_mov_b32 s8, s4 +; VI-NEXT: s_mov_b32 s9, s4 +; VI-NEXT: s_mov_b32 s10, s4 +; VI-NEXT: s_mov_b32 s11, s4 +; VI-NEXT: s_mov_b32 s12, s4 +; VI-NEXT: s_mov_b32 s13, s4 +; VI-NEXT: s_mov_b32 s14, s4 +; VI-NEXT: s_mov_b32 s15, s4 +; VI-NEXT: s_mov_b32 s16, s4 +; VI-NEXT: s_mov_b32 s17, s4 +; VI-NEXT: s_mov_b32 s18, s4 +; VI-NEXT: v_mov_b32_e32 v50, s19 +; VI-NEXT: v_mov_b32_e32 v49, s18 +; VI-NEXT: v_mov_b32_e32 v48, s17 +; VI-NEXT: v_mov_b32_e32 v47, s16 +; VI-NEXT: v_mov_b32_e32 v46, s15 +; VI-NEXT: v_mov_b32_e32 v45, s14 +; VI-NEXT: v_mov_b32_e32 v44, s13 +; VI-NEXT: v_mov_b32_e32 v43, s12 +; VI-NEXT: v_mov_b32_e32 v42, s11 +; VI-NEXT: v_mov_b32_e32 v41, s10 +; VI-NEXT: v_mov_b32_e32 v40, s9 +; VI-NEXT: v_mov_b32_e32 v39, s8 +; VI-NEXT: v_mov_b32_e32 v38, s7 +; VI-NEXT: v_mov_b32_e32 v37, s6 +; VI-NEXT: v_mov_b32_e32 v36, s5 +; VI-NEXT: v_mov_b32_e32 v35, s4 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB136_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v50, v18 +; VI-NEXT: v_mov_b32_e32 v49, v17 +; VI-NEXT: v_mov_b32_e32 v48, v16 +; VI-NEXT: v_mov_b32_e32 v47, v15 +; VI-NEXT: v_mov_b32_e32 v46, v14 +; VI-NEXT: v_mov_b32_e32 v45, v13 +; VI-NEXT: v_mov_b32_e32 v44, v12 +; VI-NEXT: v_mov_b32_e32 v43, v11 +; VI-NEXT: v_mov_b32_e32 v42, v10 +; VI-NEXT: v_mov_b32_e32 v41, v9 +; VI-NEXT: v_mov_b32_e32 v40, v8 +; VI-NEXT: v_mov_b32_e32 v39, v7 +; VI-NEXT: v_mov_b32_e32 v38, v6 +; VI-NEXT: v_mov_b32_e32 v37, v5 +; VI-NEXT: v_mov_b32_e32 v36, v4 +; VI-NEXT: v_mov_b32_e32 v35, v3 +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: .LBB136_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[47:50] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[43:46] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[39:42] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[35:38] +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; VI-NEXT: s_movk_i32 s4, 0x70 +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x60 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dwordx4 v[3:4], v[17:20] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x50 +; VI-NEXT: flat_store_dwordx4 v[3:4], v[13:16] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, 64, v1 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[9:12] +; VI-NEXT: flat_store_dwordx4 v[0:1], v[5:8] +; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v32i32_to_v64bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GFX9-NEXT: s_mov_b32 s4, 0 +; GFX9-NEXT: s_mov_b32 s19, s4 +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_mov_b32 s6, s4 +; GFX9-NEXT: s_mov_b32 s7, s4 +; GFX9-NEXT: s_mov_b32 s8, s4 +; GFX9-NEXT: s_mov_b32 s9, s4 +; GFX9-NEXT: s_mov_b32 s10, s4 +; GFX9-NEXT: s_mov_b32 s11, s4 +; GFX9-NEXT: s_mov_b32 s12, s4 +; GFX9-NEXT: s_mov_b32 s13, s4 +; GFX9-NEXT: s_mov_b32 s14, s4 +; GFX9-NEXT: s_mov_b32 s15, s4 +; GFX9-NEXT: s_mov_b32 s16, s4 +; GFX9-NEXT: s_mov_b32 s17, s4 +; GFX9-NEXT: s_mov_b32 s18, s4 +; GFX9-NEXT: v_mov_b32_e32 v50, s19 +; GFX9-NEXT: v_mov_b32_e32 v49, s18 +; GFX9-NEXT: v_mov_b32_e32 v48, s17 +; GFX9-NEXT: v_mov_b32_e32 v47, s16 +; GFX9-NEXT: v_mov_b32_e32 v46, s15 +; GFX9-NEXT: v_mov_b32_e32 v45, s14 +; GFX9-NEXT: v_mov_b32_e32 v44, s13 +; GFX9-NEXT: v_mov_b32_e32 v43, s12 +; GFX9-NEXT: v_mov_b32_e32 v42, s11 +; GFX9-NEXT: v_mov_b32_e32 v41, s10 +; GFX9-NEXT: v_mov_b32_e32 v40, s9 +; GFX9-NEXT: v_mov_b32_e32 v39, s8 +; GFX9-NEXT: v_mov_b32_e32 v38, s7 +; GFX9-NEXT: v_mov_b32_e32 v37, s6 +; GFX9-NEXT: v_mov_b32_e32 v36, s5 +; GFX9-NEXT: v_mov_b32_e32 v35, s4 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB136_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v50, v18 +; GFX9-NEXT: v_mov_b32_e32 v49, v17 +; GFX9-NEXT: v_mov_b32_e32 v48, v16 +; GFX9-NEXT: v_mov_b32_e32 v47, v15 +; GFX9-NEXT: v_mov_b32_e32 v46, v14 +; GFX9-NEXT: v_mov_b32_e32 v45, v13 +; GFX9-NEXT: v_mov_b32_e32 v44, v12 +; GFX9-NEXT: v_mov_b32_e32 v43, v11 +; GFX9-NEXT: v_mov_b32_e32 v42, v10 +; GFX9-NEXT: v_mov_b32_e32 v41, v9 +; GFX9-NEXT: v_mov_b32_e32 v40, v8 +; GFX9-NEXT: v_mov_b32_e32 v39, v7 +; GFX9-NEXT: v_mov_b32_e32 v38, v6 +; GFX9-NEXT: v_mov_b32_e32 v37, v5 +; GFX9-NEXT: v_mov_b32_e32 v36, v4 +; GFX9-NEXT: v_mov_b32_e32 v35, v3 +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: s_waitcnt vmcnt(28) +; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: .LBB136_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[47:50], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[43:46], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[39:42], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[35:38], off +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:112 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off offset:96 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off offset:80 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[3:6], off offset:64 +; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v32i32_to_v64bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_mov_b32 s15, s0 +; GFX11-NEXT: s_mov_b32 s1, s0 +; GFX11-NEXT: s_mov_b32 s2, s0 +; GFX11-NEXT: s_mov_b32 s3, s0 +; GFX11-NEXT: s_mov_b32 s4, s0 +; GFX11-NEXT: s_mov_b32 s5, s0 +; GFX11-NEXT: s_mov_b32 s6, s0 +; GFX11-NEXT: s_mov_b32 s7, s0 +; GFX11-NEXT: s_mov_b32 s8, s0 +; GFX11-NEXT: s_mov_b32 s9, s0 +; GFX11-NEXT: s_mov_b32 s10, s0 +; GFX11-NEXT: s_mov_b32 s11, s0 +; GFX11-NEXT: s_mov_b32 s12, s0 +; GFX11-NEXT: s_mov_b32 s13, s0 +; GFX11-NEXT: s_mov_b32 s14, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v66, s15 :: v_dual_mov_b32 v65, s14 +; GFX11-NEXT: v_dual_mov_b32 v52, s1 :: v_dual_mov_b32 v51, s0 +; GFX11-NEXT: v_dual_mov_b32 v64, s13 :: v_dual_mov_b32 v63, s12 +; GFX11-NEXT: v_dual_mov_b32 v62, s11 :: v_dual_mov_b32 v61, s10 +; GFX11-NEXT: v_dual_mov_b32 v60, s9 :: v_dual_mov_b32 v59, s8 +; GFX11-NEXT: v_dual_mov_b32 v58, s7 :: v_dual_mov_b32 v57, s6 +; GFX11-NEXT: v_dual_mov_b32 v56, s5 :: v_dual_mov_b32 v55, s4 +; GFX11-NEXT: v_dual_mov_b32 v54, s3 :: v_dual_mov_b32 v53, s2 +; GFX11-NEXT: v_dual_mov_b32 v35, v51 :: v_dual_mov_b32 v36, v52 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_dual_mov_b32 v39, v55 :: v_dual_mov_b32 v40, v56 +; GFX11-NEXT: v_dual_mov_b32 v37, v53 :: v_dual_mov_b32 v38, v54 +; GFX11-NEXT: v_dual_mov_b32 v41, v57 :: v_dual_mov_b32 v42, v58 +; GFX11-NEXT: v_dual_mov_b32 v43, v59 :: v_dual_mov_b32 v44, v60 +; GFX11-NEXT: v_dual_mov_b32 v45, v61 :: v_dual_mov_b32 v46, v62 +; GFX11-NEXT: v_dual_mov_b32 v47, v63 :: v_dual_mov_b32 v48, v64 +; GFX11-NEXT: v_dual_mov_b32 v49, v65 :: v_dual_mov_b32 v50, v66 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB136_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v66, v18 :: v_dual_mov_b32 v65, v17 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v50, v34 :: v_dual_mov_b32 v49, v33 +; GFX11-NEXT: v_dual_mov_b32 v64, v16 :: v_dual_mov_b32 v63, v15 +; GFX11-NEXT: v_dual_mov_b32 v62, v14 :: v_dual_mov_b32 v61, v13 +; GFX11-NEXT: v_dual_mov_b32 v60, v12 :: v_dual_mov_b32 v59, v11 +; GFX11-NEXT: v_dual_mov_b32 v58, v10 :: v_dual_mov_b32 v57, v9 +; GFX11-NEXT: v_dual_mov_b32 v56, v8 :: v_dual_mov_b32 v55, v7 +; GFX11-NEXT: v_dual_mov_b32 v54, v6 :: v_dual_mov_b32 v53, v5 +; GFX11-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v51, v3 +; GFX11-NEXT: v_dual_mov_b32 v48, v32 :: v_dual_mov_b32 v47, v31 +; GFX11-NEXT: v_dual_mov_b32 v46, v30 :: v_dual_mov_b32 v45, v29 +; GFX11-NEXT: v_dual_mov_b32 v44, v28 :: v_dual_mov_b32 v43, v27 +; GFX11-NEXT: v_dual_mov_b32 v42, v26 :: v_dual_mov_b32 v41, v25 +; GFX11-NEXT: v_dual_mov_b32 v40, v24 :: v_dual_mov_b32 v39, v23 +; GFX11-NEXT: v_dual_mov_b32 v38, v22 :: v_dual_mov_b32 v37, v21 +; GFX11-NEXT: v_dual_mov_b32 v36, v20 :: v_dual_mov_b32 v35, v19 +; GFX11-NEXT: .LBB136_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x7 +; GFX11-NEXT: global_store_b128 v[1:2], v[63:66], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[59:62], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[55:58], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[51:54], off +; GFX11-NEXT: global_store_b128 v[1:2], v[47:50], off offset:112 +; GFX11-NEXT: global_store_b128 v[1:2], v[43:46], off offset:96 +; GFX11-NEXT: global_store_b128 v[1:2], v[39:42], off offset:80 +; GFX11-NEXT: global_store_b128 v[1:2], v[35:38], off offset:64 +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64 +; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <32 x i32> %value to <64 x bfloat> + br label %end + +end: + %phi = phi <64 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <64 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v64i16_to_v64bf16(i32 %cond, ptr addrspace(1) %out, <64 x i16> %value) { +; GCN-LABEL: v_bitcast_v64i16_to_v64bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:140 +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:136 +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:132 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:128 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124 +; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:120 +; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:116 +; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:112 +; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:108 +; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:104 +; GCN-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:100 +; GCN-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:96 +; GCN-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:92 +; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:88 +; GCN-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:84 +; GCN-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:80 +; GCN-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:76 +; GCN-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:72 +; GCN-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:68 +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:64 +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:60 +; GCN-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:56 +; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:52 +; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:48 +; GCN-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:44 +; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:40 +; GCN-NEXT: s_waitcnt expcnt(6) +; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:36 +; GCN-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:32 +; GCN-NEXT: s_waitcnt expcnt(5) +; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:28 +; GCN-NEXT: s_waitcnt expcnt(4) +; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:24 +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:20 +; GCN-NEXT: s_waitcnt expcnt(3) +; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:16 +; GCN-NEXT: s_waitcnt expcnt(2) +; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 +; GCN-NEXT: s_waitcnt expcnt(1) +; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 +; GCN-NEXT: v_mov_b32_e32 v57, 0 +; GCN-NEXT: v_mov_b32_e32 v59, 0 +; GCN-NEXT: v_mov_b32_e32 v56, 0 +; GCN-NEXT: v_mov_b32_e32 v58, 0 +; GCN-NEXT: v_mov_b32_e32 v45, 0 +; GCN-NEXT: v_mov_b32_e32 v47, 0 +; GCN-NEXT: v_mov_b32_e32 v44, 0 +; GCN-NEXT: v_mov_b32_e32 v46, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v43, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB137_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_lshlrev_b32_e32 v57, 16, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v59, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v56, 16, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v58, 16, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v45, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v47, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v44, 16, v9 +; GCN-NEXT: v_lshlrev_b32_e32 v46, 16, v10 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v11 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; GCN-NEXT: v_lshlrev_b32_e32 v43, 16, v12 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v13 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v14 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v15 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v16 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v17 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v18 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v42 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v20 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v41 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v21 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v22 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v40 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v23 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v24 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v55 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v25 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v26 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v54 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v27 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v28 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v53 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v29 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v30 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v52 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v51 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v50 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v49 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v48 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v39 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v38 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v37 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v36 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v35 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v34 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v33 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v32 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v31 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v63 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v62 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v61 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v60 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: .LBB137_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v59 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v57 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v58 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v56 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v47 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v45 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v46 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v44 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v43 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:64 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:80 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:96 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v19 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:112 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v64i16_to_v64bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; VI-NEXT: s_mov_b32 s4, 0 +; VI-NEXT: s_mov_b32 s19, s4 +; VI-NEXT: s_mov_b32 s5, s4 +; VI-NEXT: s_mov_b32 s6, s4 +; VI-NEXT: s_mov_b32 s7, s4 +; VI-NEXT: s_mov_b32 s8, s4 +; VI-NEXT: s_mov_b32 s9, s4 +; VI-NEXT: s_mov_b32 s10, s4 +; VI-NEXT: s_mov_b32 s11, s4 +; VI-NEXT: s_mov_b32 s12, s4 +; VI-NEXT: s_mov_b32 s13, s4 +; VI-NEXT: s_mov_b32 s14, s4 +; VI-NEXT: s_mov_b32 s15, s4 +; VI-NEXT: s_mov_b32 s16, s4 +; VI-NEXT: s_mov_b32 s17, s4 +; VI-NEXT: s_mov_b32 s18, s4 +; VI-NEXT: v_mov_b32_e32 v50, s19 +; VI-NEXT: v_mov_b32_e32 v49, s18 +; VI-NEXT: v_mov_b32_e32 v48, s17 +; VI-NEXT: v_mov_b32_e32 v47, s16 +; VI-NEXT: v_mov_b32_e32 v46, s15 +; VI-NEXT: v_mov_b32_e32 v45, s14 +; VI-NEXT: v_mov_b32_e32 v44, s13 +; VI-NEXT: v_mov_b32_e32 v43, s12 +; VI-NEXT: v_mov_b32_e32 v42, s11 +; VI-NEXT: v_mov_b32_e32 v41, s10 +; VI-NEXT: v_mov_b32_e32 v40, s9 +; VI-NEXT: v_mov_b32_e32 v39, s8 +; VI-NEXT: v_mov_b32_e32 v38, s7 +; VI-NEXT: v_mov_b32_e32 v37, s6 +; VI-NEXT: v_mov_b32_e32 v36, s5 +; VI-NEXT: v_mov_b32_e32 v35, s4 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB137_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v50, v18 +; VI-NEXT: v_mov_b32_e32 v49, v17 +; VI-NEXT: v_mov_b32_e32 v48, v16 +; VI-NEXT: v_mov_b32_e32 v47, v15 +; VI-NEXT: v_mov_b32_e32 v46, v14 +; VI-NEXT: v_mov_b32_e32 v45, v13 +; VI-NEXT: v_mov_b32_e32 v44, v12 +; VI-NEXT: v_mov_b32_e32 v43, v11 +; VI-NEXT: v_mov_b32_e32 v42, v10 +; VI-NEXT: v_mov_b32_e32 v41, v9 +; VI-NEXT: v_mov_b32_e32 v40, v8 +; VI-NEXT: v_mov_b32_e32 v39, v7 +; VI-NEXT: v_mov_b32_e32 v38, v6 +; VI-NEXT: v_mov_b32_e32 v37, v5 +; VI-NEXT: v_mov_b32_e32 v36, v4 +; VI-NEXT: v_mov_b32_e32 v35, v3 +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: .LBB137_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[47:50] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[43:46] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[39:42] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[35:38] +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; VI-NEXT: s_movk_i32 s4, 0x70 +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x60 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dwordx4 v[3:4], v[17:20] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x50 +; VI-NEXT: flat_store_dwordx4 v[3:4], v[13:16] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, 64, v1 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[9:12] +; VI-NEXT: flat_store_dwordx4 v[0:1], v[5:8] +; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v64i16_to_v64bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GFX9-NEXT: s_mov_b32 s4, 0 +; GFX9-NEXT: s_mov_b32 s19, s4 +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_mov_b32 s6, s4 +; GFX9-NEXT: s_mov_b32 s7, s4 +; GFX9-NEXT: s_mov_b32 s8, s4 +; GFX9-NEXT: s_mov_b32 s9, s4 +; GFX9-NEXT: s_mov_b32 s10, s4 +; GFX9-NEXT: s_mov_b32 s11, s4 +; GFX9-NEXT: s_mov_b32 s12, s4 +; GFX9-NEXT: s_mov_b32 s13, s4 +; GFX9-NEXT: s_mov_b32 s14, s4 +; GFX9-NEXT: s_mov_b32 s15, s4 +; GFX9-NEXT: s_mov_b32 s16, s4 +; GFX9-NEXT: s_mov_b32 s17, s4 +; GFX9-NEXT: s_mov_b32 s18, s4 +; GFX9-NEXT: v_mov_b32_e32 v50, s19 +; GFX9-NEXT: v_mov_b32_e32 v49, s18 +; GFX9-NEXT: v_mov_b32_e32 v48, s17 +; GFX9-NEXT: v_mov_b32_e32 v47, s16 +; GFX9-NEXT: v_mov_b32_e32 v46, s15 +; GFX9-NEXT: v_mov_b32_e32 v45, s14 +; GFX9-NEXT: v_mov_b32_e32 v44, s13 +; GFX9-NEXT: v_mov_b32_e32 v43, s12 +; GFX9-NEXT: v_mov_b32_e32 v42, s11 +; GFX9-NEXT: v_mov_b32_e32 v41, s10 +; GFX9-NEXT: v_mov_b32_e32 v40, s9 +; GFX9-NEXT: v_mov_b32_e32 v39, s8 +; GFX9-NEXT: v_mov_b32_e32 v38, s7 +; GFX9-NEXT: v_mov_b32_e32 v37, s6 +; GFX9-NEXT: v_mov_b32_e32 v36, s5 +; GFX9-NEXT: v_mov_b32_e32 v35, s4 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB137_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v50, v18 +; GFX9-NEXT: v_mov_b32_e32 v49, v17 +; GFX9-NEXT: v_mov_b32_e32 v48, v16 +; GFX9-NEXT: v_mov_b32_e32 v47, v15 +; GFX9-NEXT: v_mov_b32_e32 v46, v14 +; GFX9-NEXT: v_mov_b32_e32 v45, v13 +; GFX9-NEXT: v_mov_b32_e32 v44, v12 +; GFX9-NEXT: v_mov_b32_e32 v43, v11 +; GFX9-NEXT: v_mov_b32_e32 v42, v10 +; GFX9-NEXT: v_mov_b32_e32 v41, v9 +; GFX9-NEXT: v_mov_b32_e32 v40, v8 +; GFX9-NEXT: v_mov_b32_e32 v39, v7 +; GFX9-NEXT: v_mov_b32_e32 v38, v6 +; GFX9-NEXT: v_mov_b32_e32 v37, v5 +; GFX9-NEXT: v_mov_b32_e32 v36, v4 +; GFX9-NEXT: v_mov_b32_e32 v35, v3 +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: s_waitcnt vmcnt(28) +; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: .LBB137_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[47:50], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[43:46], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[39:42], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[35:38], off +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:112 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off offset:96 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off offset:80 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[3:6], off offset:64 +; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v64i16_to_v64bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_mov_b32 s15, s0 +; GFX11-NEXT: s_mov_b32 s1, s0 +; GFX11-NEXT: s_mov_b32 s2, s0 +; GFX11-NEXT: s_mov_b32 s3, s0 +; GFX11-NEXT: s_mov_b32 s4, s0 +; GFX11-NEXT: s_mov_b32 s5, s0 +; GFX11-NEXT: s_mov_b32 s6, s0 +; GFX11-NEXT: s_mov_b32 s7, s0 +; GFX11-NEXT: s_mov_b32 s8, s0 +; GFX11-NEXT: s_mov_b32 s9, s0 +; GFX11-NEXT: s_mov_b32 s10, s0 +; GFX11-NEXT: s_mov_b32 s11, s0 +; GFX11-NEXT: s_mov_b32 s12, s0 +; GFX11-NEXT: s_mov_b32 s13, s0 +; GFX11-NEXT: s_mov_b32 s14, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v66, s15 :: v_dual_mov_b32 v65, s14 +; GFX11-NEXT: v_dual_mov_b32 v52, s1 :: v_dual_mov_b32 v51, s0 +; GFX11-NEXT: v_dual_mov_b32 v64, s13 :: v_dual_mov_b32 v63, s12 +; GFX11-NEXT: v_dual_mov_b32 v62, s11 :: v_dual_mov_b32 v61, s10 +; GFX11-NEXT: v_dual_mov_b32 v60, s9 :: v_dual_mov_b32 v59, s8 +; GFX11-NEXT: v_dual_mov_b32 v58, s7 :: v_dual_mov_b32 v57, s6 +; GFX11-NEXT: v_dual_mov_b32 v56, s5 :: v_dual_mov_b32 v55, s4 +; GFX11-NEXT: v_dual_mov_b32 v54, s3 :: v_dual_mov_b32 v53, s2 +; GFX11-NEXT: v_dual_mov_b32 v35, v51 :: v_dual_mov_b32 v36, v52 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_dual_mov_b32 v39, v55 :: v_dual_mov_b32 v40, v56 +; GFX11-NEXT: v_dual_mov_b32 v37, v53 :: v_dual_mov_b32 v38, v54 +; GFX11-NEXT: v_dual_mov_b32 v41, v57 :: v_dual_mov_b32 v42, v58 +; GFX11-NEXT: v_dual_mov_b32 v43, v59 :: v_dual_mov_b32 v44, v60 +; GFX11-NEXT: v_dual_mov_b32 v45, v61 :: v_dual_mov_b32 v46, v62 +; GFX11-NEXT: v_dual_mov_b32 v47, v63 :: v_dual_mov_b32 v48, v64 +; GFX11-NEXT: v_dual_mov_b32 v49, v65 :: v_dual_mov_b32 v50, v66 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB137_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v66, v18 :: v_dual_mov_b32 v65, v17 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v50, v34 :: v_dual_mov_b32 v49, v33 +; GFX11-NEXT: v_dual_mov_b32 v64, v16 :: v_dual_mov_b32 v63, v15 +; GFX11-NEXT: v_dual_mov_b32 v62, v14 :: v_dual_mov_b32 v61, v13 +; GFX11-NEXT: v_dual_mov_b32 v60, v12 :: v_dual_mov_b32 v59, v11 +; GFX11-NEXT: v_dual_mov_b32 v58, v10 :: v_dual_mov_b32 v57, v9 +; GFX11-NEXT: v_dual_mov_b32 v56, v8 :: v_dual_mov_b32 v55, v7 +; GFX11-NEXT: v_dual_mov_b32 v54, v6 :: v_dual_mov_b32 v53, v5 +; GFX11-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v51, v3 +; GFX11-NEXT: v_dual_mov_b32 v48, v32 :: v_dual_mov_b32 v47, v31 +; GFX11-NEXT: v_dual_mov_b32 v46, v30 :: v_dual_mov_b32 v45, v29 +; GFX11-NEXT: v_dual_mov_b32 v44, v28 :: v_dual_mov_b32 v43, v27 +; GFX11-NEXT: v_dual_mov_b32 v42, v26 :: v_dual_mov_b32 v41, v25 +; GFX11-NEXT: v_dual_mov_b32 v40, v24 :: v_dual_mov_b32 v39, v23 +; GFX11-NEXT: v_dual_mov_b32 v38, v22 :: v_dual_mov_b32 v37, v21 +; GFX11-NEXT: v_dual_mov_b32 v36, v20 :: v_dual_mov_b32 v35, v19 +; GFX11-NEXT: .LBB137_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x7 +; GFX11-NEXT: global_store_b128 v[1:2], v[63:66], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[59:62], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[55:58], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[51:54], off +; GFX11-NEXT: global_store_b128 v[1:2], v[47:50], off offset:112 +; GFX11-NEXT: global_store_b128 v[1:2], v[43:46], off offset:96 +; GFX11-NEXT: global_store_b128 v[1:2], v[39:42], off offset:80 +; GFX11-NEXT: global_store_b128 v[1:2], v[35:38], off offset:64 +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64 +; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <64 x i16> %value to <64 x bfloat> + br label %end + +end: + %phi = phi <64 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <64 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v64f16_to_v64bf16(i32 %cond, ptr addrspace(1) %out, <64 x half> %value) { +; GCN-LABEL: v_bitcast_v64f16_to_v64bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v33, v16 +; GCN-NEXT: v_mov_b32_e32 v16, v15 +; GCN-NEXT: v_mov_b32_e32 v15, v14 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:136 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:128 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:120 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:112 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:104 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:100 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:96 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:92 +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:88 +; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:84 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:80 +; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76 +; GCN-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:72 +; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:68 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:64 +; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60 +; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:56 +; GCN-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52 +; GCN-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48 +; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44 +; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:40 +; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:36 +; GCN-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:32 +; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:28 +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:24 +; GCN-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:20 +; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:16 +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 +; GCN-NEXT: v_mov_b32_e32 v57, 0 +; GCN-NEXT: v_mov_b32_e32 v59, 0 +; GCN-NEXT: v_mov_b32_e32 v56, 0 +; GCN-NEXT: v_mov_b32_e32 v58, 0 +; GCN-NEXT: v_mov_b32_e32 v45, 0 +; GCN-NEXT: v_mov_b32_e32 v47, 0 +; GCN-NEXT: v_mov_b32_e32 v44, 0 +; GCN-NEXT: v_mov_b32_e32 v46, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v43, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v42, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v40, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB138_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_cvt_f16_f32_e32 v57, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v59, v4 +; GCN-NEXT: v_cvt_f16_f32_e32 v56, v5 +; GCN-NEXT: v_cvt_f16_f32_e32 v58, v6 +; GCN-NEXT: v_cvt_f16_f32_e32 v45, v7 +; GCN-NEXT: v_cvt_f16_f32_e32 v47, v8 +; GCN-NEXT: v_cvt_f16_f32_e32 v44, v9 +; GCN-NEXT: v_cvt_f16_f32_e32 v46, v10 +; GCN-NEXT: v_cvt_f16_f32_e32 v41, v11 +; GCN-NEXT: v_cvt_f16_f32_e32 v43, v12 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v13 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v15 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f16_f32_e32 v13, v16 +; GCN-NEXT: v_cvt_f16_f32_e32 v12, v33 +; GCN-NEXT: v_cvt_f16_f32_e32 v17, v17 +; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 +; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 +; GCN-NEXT: v_cvt_f16_f32_e32 v20, v20 +; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v51, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v11, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v33, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v4, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v52, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v5, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v34, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v7, v3 +; GCN-NEXT: v_cvt_f16_f32_e32 v22, v22 +; GCN-NEXT: v_cvt_f16_f32_e32 v30, v30 +; GCN-NEXT: v_cvt_f16_f32_e32 v50, v50 +; GCN-NEXT: v_cvt_f16_f32_e32 v61, v61 +; GCN-NEXT: v_cvt_f16_f32_e32 v23, v23 +; GCN-NEXT: v_cvt_f16_f32_e32 v49, v49 +; GCN-NEXT: v_cvt_f16_f32_e32 v60, v60 +; GCN-NEXT: v_cvt_f16_f32_e32 v24, v24 +; GCN-NEXT: v_cvt_f16_f32_e32 v48, v48 +; GCN-NEXT: v_cvt_f16_f32_e32 v39, v39 +; GCN-NEXT: v_cvt_f16_f32_e32 v25, v25 +; GCN-NEXT: v_cvt_f16_f32_e32 v32, v32 +; GCN-NEXT: v_cvt_f16_f32_e32 v38, v38 +; GCN-NEXT: v_cvt_f16_f32_e32 v37, v37 +; GCN-NEXT: v_cvt_f16_f32_e32 v26, v26 +; GCN-NEXT: v_cvt_f16_f32_e32 v31, v31 +; GCN-NEXT: v_cvt_f16_f32_e32 v3, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v27, v27 +; GCN-NEXT: v_cvt_f16_f32_e32 v36, v36 +; GCN-NEXT: v_cvt_f16_f32_e32 v28, v28 +; GCN-NEXT: v_cvt_f16_f32_e32 v63, v63 +; GCN-NEXT: v_cvt_f16_f32_e32 v35, v35 +; GCN-NEXT: v_cvt_f16_f32_e32 v29, v29 +; GCN-NEXT: v_cvt_f16_f32_e32 v62, v62 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v53, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v8, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v9, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v54, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v10, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v55, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v40, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v42, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v16, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v15, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v14, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v57, 16, v57 +; GCN-NEXT: v_lshlrev_b32_e32 v59, 16, v59 +; GCN-NEXT: v_lshlrev_b32_e32 v56, 16, v56 +; GCN-NEXT: v_lshlrev_b32_e32 v58, 16, v58 +; GCN-NEXT: v_lshlrev_b32_e32 v45, 16, v45 +; GCN-NEXT: v_lshlrev_b32_e32 v47, 16, v47 +; GCN-NEXT: v_lshlrev_b32_e32 v44, 16, v44 +; GCN-NEXT: v_lshlrev_b32_e32 v46, 16, v46 +; GCN-NEXT: v_lshlrev_b32_e32 v41, 16, v41 +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; GCN-NEXT: v_lshlrev_b32_e32 v43, 16, v43 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v41, 16, v41 +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v41, 16, v41 +; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v17 +; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v18 +; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v19 +; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v20 +; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v21 +; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v51 +; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v33 +; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v52 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v5 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v34 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v6 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v7 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v22 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v30 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v50 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v61 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v23 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v49 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v60 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v24 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v48 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v39 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v25 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v32 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v38 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v37 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v26 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v31 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v27 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v36 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v28 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v63 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v35 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v29 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v62 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v53 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v8 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v9 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v54 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: v_lshlrev_b32_e32 v54, 16, v10 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v55 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v40 +; GCN-NEXT: v_mov_b32_e32 v40, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v55, 16, v42 +; GCN-NEXT: v_mov_b32_e32 v42, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v53, 16, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GCN-NEXT: v_lshlrev_b32_e32 v51, 16, v0 +; GCN-NEXT: .LBB138_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_waitcnt vmcnt(14) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v59 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v57 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v58 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v56 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v47 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v45 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v46 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v44 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v43 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v41 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:64 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:80 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v42 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:96 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v40 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v54 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v52 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v53 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v34 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v51 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v14 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:112 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v64f16_to_v64bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; VI-NEXT: s_mov_b32 s4, 0 +; VI-NEXT: s_mov_b32 s19, s4 +; VI-NEXT: s_mov_b32 s5, s4 +; VI-NEXT: s_mov_b32 s6, s4 +; VI-NEXT: s_mov_b32 s7, s4 +; VI-NEXT: s_mov_b32 s8, s4 +; VI-NEXT: s_mov_b32 s9, s4 +; VI-NEXT: s_mov_b32 s10, s4 +; VI-NEXT: s_mov_b32 s11, s4 +; VI-NEXT: s_mov_b32 s12, s4 +; VI-NEXT: s_mov_b32 s13, s4 +; VI-NEXT: s_mov_b32 s14, s4 +; VI-NEXT: s_mov_b32 s15, s4 +; VI-NEXT: s_mov_b32 s16, s4 +; VI-NEXT: s_mov_b32 s17, s4 +; VI-NEXT: s_mov_b32 s18, s4 +; VI-NEXT: v_mov_b32_e32 v50, s19 +; VI-NEXT: v_mov_b32_e32 v49, s18 +; VI-NEXT: v_mov_b32_e32 v48, s17 +; VI-NEXT: v_mov_b32_e32 v47, s16 +; VI-NEXT: v_mov_b32_e32 v46, s15 +; VI-NEXT: v_mov_b32_e32 v45, s14 +; VI-NEXT: v_mov_b32_e32 v44, s13 +; VI-NEXT: v_mov_b32_e32 v43, s12 +; VI-NEXT: v_mov_b32_e32 v42, s11 +; VI-NEXT: v_mov_b32_e32 v41, s10 +; VI-NEXT: v_mov_b32_e32 v40, s9 +; VI-NEXT: v_mov_b32_e32 v39, s8 +; VI-NEXT: v_mov_b32_e32 v38, s7 +; VI-NEXT: v_mov_b32_e32 v37, s6 +; VI-NEXT: v_mov_b32_e32 v36, s5 +; VI-NEXT: v_mov_b32_e32 v35, s4 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB138_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v50, v18 +; VI-NEXT: v_mov_b32_e32 v49, v17 +; VI-NEXT: v_mov_b32_e32 v48, v16 +; VI-NEXT: v_mov_b32_e32 v47, v15 +; VI-NEXT: v_mov_b32_e32 v46, v14 +; VI-NEXT: v_mov_b32_e32 v45, v13 +; VI-NEXT: v_mov_b32_e32 v44, v12 +; VI-NEXT: v_mov_b32_e32 v43, v11 +; VI-NEXT: v_mov_b32_e32 v42, v10 +; VI-NEXT: v_mov_b32_e32 v41, v9 +; VI-NEXT: v_mov_b32_e32 v40, v8 +; VI-NEXT: v_mov_b32_e32 v39, v7 +; VI-NEXT: v_mov_b32_e32 v38, v6 +; VI-NEXT: v_mov_b32_e32 v37, v5 +; VI-NEXT: v_mov_b32_e32 v36, v4 +; VI-NEXT: v_mov_b32_e32 v35, v3 +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: .LBB138_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[47:50] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[43:46] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[39:42] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[35:38] +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; VI-NEXT: s_movk_i32 s4, 0x70 +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x60 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dwordx4 v[3:4], v[17:20] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x50 +; VI-NEXT: flat_store_dwordx4 v[3:4], v[13:16] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, 64, v1 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[9:12] +; VI-NEXT: flat_store_dwordx4 v[0:1], v[5:8] +; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v64f16_to_v64bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GFX9-NEXT: s_mov_b32 s4, 0 +; GFX9-NEXT: s_mov_b32 s19, s4 +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_mov_b32 s6, s4 +; GFX9-NEXT: s_mov_b32 s7, s4 +; GFX9-NEXT: s_mov_b32 s8, s4 +; GFX9-NEXT: s_mov_b32 s9, s4 +; GFX9-NEXT: s_mov_b32 s10, s4 +; GFX9-NEXT: s_mov_b32 s11, s4 +; GFX9-NEXT: s_mov_b32 s12, s4 +; GFX9-NEXT: s_mov_b32 s13, s4 +; GFX9-NEXT: s_mov_b32 s14, s4 +; GFX9-NEXT: s_mov_b32 s15, s4 +; GFX9-NEXT: s_mov_b32 s16, s4 +; GFX9-NEXT: s_mov_b32 s17, s4 +; GFX9-NEXT: s_mov_b32 s18, s4 +; GFX9-NEXT: v_mov_b32_e32 v50, s19 +; GFX9-NEXT: v_mov_b32_e32 v49, s18 +; GFX9-NEXT: v_mov_b32_e32 v48, s17 +; GFX9-NEXT: v_mov_b32_e32 v47, s16 +; GFX9-NEXT: v_mov_b32_e32 v46, s15 +; GFX9-NEXT: v_mov_b32_e32 v45, s14 +; GFX9-NEXT: v_mov_b32_e32 v44, s13 +; GFX9-NEXT: v_mov_b32_e32 v43, s12 +; GFX9-NEXT: v_mov_b32_e32 v42, s11 +; GFX9-NEXT: v_mov_b32_e32 v41, s10 +; GFX9-NEXT: v_mov_b32_e32 v40, s9 +; GFX9-NEXT: v_mov_b32_e32 v39, s8 +; GFX9-NEXT: v_mov_b32_e32 v38, s7 +; GFX9-NEXT: v_mov_b32_e32 v37, s6 +; GFX9-NEXT: v_mov_b32_e32 v36, s5 +; GFX9-NEXT: v_mov_b32_e32 v35, s4 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB138_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v50, v18 +; GFX9-NEXT: v_mov_b32_e32 v49, v17 +; GFX9-NEXT: v_mov_b32_e32 v48, v16 +; GFX9-NEXT: v_mov_b32_e32 v47, v15 +; GFX9-NEXT: v_mov_b32_e32 v46, v14 +; GFX9-NEXT: v_mov_b32_e32 v45, v13 +; GFX9-NEXT: v_mov_b32_e32 v44, v12 +; GFX9-NEXT: v_mov_b32_e32 v43, v11 +; GFX9-NEXT: v_mov_b32_e32 v42, v10 +; GFX9-NEXT: v_mov_b32_e32 v41, v9 +; GFX9-NEXT: v_mov_b32_e32 v40, v8 +; GFX9-NEXT: v_mov_b32_e32 v39, v7 +; GFX9-NEXT: v_mov_b32_e32 v38, v6 +; GFX9-NEXT: v_mov_b32_e32 v37, v5 +; GFX9-NEXT: v_mov_b32_e32 v36, v4 +; GFX9-NEXT: v_mov_b32_e32 v35, v3 +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: s_waitcnt vmcnt(28) +; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: .LBB138_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[47:50], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[43:46], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[39:42], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[35:38], off +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:112 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off offset:96 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off offset:80 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[3:6], off offset:64 +; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v64f16_to_v64bf16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_mov_b32 s15, s0 +; GFX11-NEXT: s_mov_b32 s1, s0 +; GFX11-NEXT: s_mov_b32 s2, s0 +; GFX11-NEXT: s_mov_b32 s3, s0 +; GFX11-NEXT: s_mov_b32 s4, s0 +; GFX11-NEXT: s_mov_b32 s5, s0 +; GFX11-NEXT: s_mov_b32 s6, s0 +; GFX11-NEXT: s_mov_b32 s7, s0 +; GFX11-NEXT: s_mov_b32 s8, s0 +; GFX11-NEXT: s_mov_b32 s9, s0 +; GFX11-NEXT: s_mov_b32 s10, s0 +; GFX11-NEXT: s_mov_b32 s11, s0 +; GFX11-NEXT: s_mov_b32 s12, s0 +; GFX11-NEXT: s_mov_b32 s13, s0 +; GFX11-NEXT: s_mov_b32 s14, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v66, s15 :: v_dual_mov_b32 v65, s14 +; GFX11-NEXT: v_dual_mov_b32 v52, s1 :: v_dual_mov_b32 v51, s0 +; GFX11-NEXT: v_dual_mov_b32 v64, s13 :: v_dual_mov_b32 v63, s12 +; GFX11-NEXT: v_dual_mov_b32 v62, s11 :: v_dual_mov_b32 v61, s10 +; GFX11-NEXT: v_dual_mov_b32 v60, s9 :: v_dual_mov_b32 v59, s8 +; GFX11-NEXT: v_dual_mov_b32 v58, s7 :: v_dual_mov_b32 v57, s6 +; GFX11-NEXT: v_dual_mov_b32 v56, s5 :: v_dual_mov_b32 v55, s4 +; GFX11-NEXT: v_dual_mov_b32 v54, s3 :: v_dual_mov_b32 v53, s2 +; GFX11-NEXT: v_dual_mov_b32 v35, v51 :: v_dual_mov_b32 v36, v52 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_dual_mov_b32 v39, v55 :: v_dual_mov_b32 v40, v56 +; GFX11-NEXT: v_dual_mov_b32 v37, v53 :: v_dual_mov_b32 v38, v54 +; GFX11-NEXT: v_dual_mov_b32 v41, v57 :: v_dual_mov_b32 v42, v58 +; GFX11-NEXT: v_dual_mov_b32 v43, v59 :: v_dual_mov_b32 v44, v60 +; GFX11-NEXT: v_dual_mov_b32 v45, v61 :: v_dual_mov_b32 v46, v62 +; GFX11-NEXT: v_dual_mov_b32 v47, v63 :: v_dual_mov_b32 v48, v64 +; GFX11-NEXT: v_dual_mov_b32 v49, v65 :: v_dual_mov_b32 v50, v66 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB138_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v66, v18 :: v_dual_mov_b32 v65, v17 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v50, v34 :: v_dual_mov_b32 v49, v33 +; GFX11-NEXT: v_dual_mov_b32 v64, v16 :: v_dual_mov_b32 v63, v15 +; GFX11-NEXT: v_dual_mov_b32 v62, v14 :: v_dual_mov_b32 v61, v13 +; GFX11-NEXT: v_dual_mov_b32 v60, v12 :: v_dual_mov_b32 v59, v11 +; GFX11-NEXT: v_dual_mov_b32 v58, v10 :: v_dual_mov_b32 v57, v9 +; GFX11-NEXT: v_dual_mov_b32 v56, v8 :: v_dual_mov_b32 v55, v7 +; GFX11-NEXT: v_dual_mov_b32 v54, v6 :: v_dual_mov_b32 v53, v5 +; GFX11-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v51, v3 +; GFX11-NEXT: v_dual_mov_b32 v48, v32 :: v_dual_mov_b32 v47, v31 +; GFX11-NEXT: v_dual_mov_b32 v46, v30 :: v_dual_mov_b32 v45, v29 +; GFX11-NEXT: v_dual_mov_b32 v44, v28 :: v_dual_mov_b32 v43, v27 +; GFX11-NEXT: v_dual_mov_b32 v42, v26 :: v_dual_mov_b32 v41, v25 +; GFX11-NEXT: v_dual_mov_b32 v40, v24 :: v_dual_mov_b32 v39, v23 +; GFX11-NEXT: v_dual_mov_b32 v38, v22 :: v_dual_mov_b32 v37, v21 +; GFX11-NEXT: v_dual_mov_b32 v36, v20 :: v_dual_mov_b32 v35, v19 +; GFX11-NEXT: .LBB138_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x7 +; GFX11-NEXT: global_store_b128 v[1:2], v[63:66], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[59:62], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[55:58], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[51:54], off +; GFX11-NEXT: global_store_b128 v[1:2], v[47:50], off offset:112 +; GFX11-NEXT: global_store_b128 v[1:2], v[43:46], off offset:96 +; GFX11-NEXT: global_store_b128 v[1:2], v[39:42], off offset:80 +; GFX11-NEXT: global_store_b128 v[1:2], v[35:38], off offset:64 +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64 +; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <64 x half> %value to <64 x bfloat> + br label %end + +end: + %phi = phi <64 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <64 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v128i8_to_v64bf16(i32 %cond, ptr addrspace(1) %out, <128 x i8> %value) { +; GCN-LABEL: v_bitcast_v128i8_to_v64bf16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:976 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:980 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:396 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:384 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:380 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:376 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:372 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:368 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:364 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:360 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:356 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:348 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:344 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:340 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:336 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:324 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:308 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:276 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:272 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:968 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:972 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:228 +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:224 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:196 +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:192 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:184 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:168 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:160 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:152 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:144 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:136 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:132 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:128 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:124 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:112 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:104 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 +; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:96 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:88 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:68 +; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:64 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:52 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:48 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:44 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:40 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:36 +; GCN-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:32 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:28 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:24 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:20 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:12 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 +; GCN-NEXT: v_mov_b32_e32 v44, 0 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mov_b32_e32 v16, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mov_b32_e32 v4, 0 +; GCN-NEXT: v_mov_b32_e32 v57, 0 +; GCN-NEXT: v_mov_b32_e32 v59, 0 +; GCN-NEXT: v_mov_b32_e32 v33, 0 +; GCN-NEXT: v_mov_b32_e32 v10, 0 +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: v_mov_b32_e32 v46, 0 +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: v_mov_b32_e32 v20, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: v_mov_b32_e32 v42, 0 +; GCN-NEXT: v_mov_b32_e32 v55, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v3, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v28, 0 +; GCN-NEXT: v_mov_b32_e32 v23, 0 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mov_b32_e32 v25, 0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_mov_b32_e32 v43, 0 +; GCN-NEXT: v_mov_b32_e32 v26, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v17, 0 +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v19, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: v_mov_b32_e32 v21, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v18, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v29, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v47, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB139_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v8 +; GCN-NEXT: v_or_b32_e32 v7, v3, v4 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:976 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v4 +; GCN-NEXT: v_or_b32_e32 v8, v3, v4 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v4 +; GCN-NEXT: v_or_b32_e32 v24, v3, v4 +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v27 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v38 +; GCN-NEXT: v_or_b32_e32 v23, v3, v4 +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v37 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v30 +; GCN-NEXT: v_or_b32_e32 v18, v3, v4 +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v35 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v34 +; GCN-NEXT: v_or_b32_e32 v21, v3, v4 +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v32 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v15 +; GCN-NEXT: v_or_b32_e32 v22, v3, v4 +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v62 +; GCN-NEXT: v_or_b32_e32 v29, v0, v3 +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v61 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v58 +; GCN-NEXT: v_or_b32_e32 v34, v0, v3 +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v56 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v41 +; GCN-NEXT: v_or_b32_e32 v47, v0, v3 +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v40 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v45 +; GCN-NEXT: v_or_b32_e32 v40, v0, v3 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:972 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v3 +; GCN-NEXT: v_or_b32_e32 v41, v0, v3 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v3 +; GCN-NEXT: v_or_b32_e32 v45, v0, v3 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v3 +; GCN-NEXT: v_or_b32_e32 v56, v0, v3 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v3 +; GCN-NEXT: v_or_b32_e32 v58, v0, v3 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v3 +; GCN-NEXT: v_or_b32_e32 v0, v0, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 24, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v44, v4, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 24, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v12, v4, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 24, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v14, v4, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v4, 24, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v4, v4, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v5, 24, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v57, v5, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v5, 24, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v33, v5, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v5, 24, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v10, v5, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v5, 24, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v39, v5, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v5, 24, v5 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v5, v5, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v20, v6, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v9, v6, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v55, v6, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v36, v6, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v48, v6, v3 +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v3, 0xff, v3 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v3, v6, v3 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v11, 24, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_or_b32_e32 v31, v11, v6 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v11, 24, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_or_b32_e32 v28, v11, v6 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v6, 0xff, v6 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v11, 24, v11 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_or_b32_e32 v6, v11, v6 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v11, 0xff, v11 +; GCN-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v13, 24, v13 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_or_b32_e32 v13, v13, v11 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v11, 0xff, v11 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v15, 24, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_or_b32_e32 v25, v15, v11 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v11, 0xff, v11 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v15, 24, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_or_b32_e32 v11, v15, v11 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v43, v16, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v26, v16, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v17, v16, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v19, v16, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v51, v16, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v54, v16, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v50, v16, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v15, v16, v15 +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_and_b32_e32 v15, 0xff, v63 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v16, 24, v16 +; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_or_b32_e32 v60, v16, v15 +; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v7 +; GCN-NEXT: v_lshlrev_b32_e32 v59, 16, v8 +; GCN-NEXT: v_lshlrev_b32_e32 v46, 16, v24 +; GCN-NEXT: v_lshlrev_b32_e32 v42, 16, v23 +; GCN-NEXT: v_lshlrev_b32_e32 v53, 16, v18 +; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v21 +; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v22 +; GCN-NEXT: v_lshlrev_b32_e32 v52, 16, v29 +; GCN-NEXT: v_lshlrev_b32_e32 v49, 16, v34 +; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v47 +; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v40 +; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v41 +; GCN-NEXT: v_lshlrev_b32_e32 v47, 16, v45 +; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v56 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v58 +; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill +; GCN-NEXT: .LBB139_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v44 +; GCN-NEXT: v_mov_b32_e32 v12, v60 +; GCN-NEXT: v_alignbit_b32 v60, v0, v7, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v16 +; GCN-NEXT: v_alignbit_b32 v61, v0, v7, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v57 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v62, v0, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v33 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v59 +; GCN-NEXT: v_alignbit_b32 v63, v0, v4, 16 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[60:63], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v10 +; GCN-NEXT: v_alignbit_b32 v7, v0, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v46 +; GCN-NEXT: v_alignbit_b32 v8, v0, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v20 +; GCN-NEXT: v_alignbit_b32 v9, v0, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v42 +; GCN-NEXT: v_alignbit_b32 v10, v0, v4, 16 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v48 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v36 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_alignbit_b32 v7, v0, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v53 +; GCN-NEXT: v_alignbit_b32 v8, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v31 +; GCN-NEXT: v_alignbit_b32 v9, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v23 +; GCN-NEXT: v_alignbit_b32 v10, v0, v3, 16 +; GCN-NEXT: buffer_store_dwordx4 v[7:10], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v13 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v24 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v43 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v52 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v19 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v51 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v49 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v54 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v50 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v21 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:64 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v18 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v29 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:80 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v47 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v22 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:96 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_alignbit_b32 v3, v0, v3, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v4 +; GCN-NEXT: v_alignbit_b32 v4, v0, v4, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_alignbit_b32 v5, v0, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; GCN-NEXT: v_alignbit_b32 v6, v0, v6, 16 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[1:2], s[4:7], 0 addr64 offset:112 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v128i8_to_v64bf16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:396 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill +; VI-NEXT: s_mov_b32 s4, 0 +; VI-NEXT: s_mov_b32 s19, s4 +; VI-NEXT: s_mov_b32 s5, s4 +; VI-NEXT: s_mov_b32 s6, s4 +; VI-NEXT: s_mov_b32 s7, s4 +; VI-NEXT: s_mov_b32 s8, s4 +; VI-NEXT: s_mov_b32 s9, s4 +; VI-NEXT: s_mov_b32 s10, s4 +; VI-NEXT: s_mov_b32 s11, s4 +; VI-NEXT: s_mov_b32 s12, s4 +; VI-NEXT: s_mov_b32 s13, s4 +; VI-NEXT: s_mov_b32 s14, s4 +; VI-NEXT: s_mov_b32 s15, s4 +; VI-NEXT: s_mov_b32 s16, s4 +; VI-NEXT: s_mov_b32 s17, s4 +; VI-NEXT: s_mov_b32 s18, s4 +; VI-NEXT: v_mov_b32_e32 v46, s19 +; VI-NEXT: v_mov_b32_e32 v45, s18 +; VI-NEXT: v_mov_b32_e32 v44, s17 +; VI-NEXT: v_mov_b32_e32 v43, s16 +; VI-NEXT: v_mov_b32_e32 v42, s15 +; VI-NEXT: v_mov_b32_e32 v41, s14 +; VI-NEXT: v_mov_b32_e32 v40, s13 +; VI-NEXT: v_mov_b32_e32 v39, s12 +; VI-NEXT: v_mov_b32_e32 v38, s11 +; VI-NEXT: v_mov_b32_e32 v37, s10 +; VI-NEXT: v_mov_b32_e32 v36, s9 +; VI-NEXT: v_mov_b32_e32 v35, s8 +; VI-NEXT: v_mov_b32_e32 v34, s7 +; VI-NEXT: v_mov_b32_e32 v33, s6 +; VI-NEXT: v_mov_b32_e32 v32, s5 +; VI-NEXT: v_mov_b32_e32 v31, s4 +; VI-NEXT: v_mov_b32_e32 v62, v46 +; VI-NEXT: v_mov_b32_e32 v61, v45 +; VI-NEXT: v_mov_b32_e32 v60, v44 +; VI-NEXT: v_mov_b32_e32 v59, v43 +; VI-NEXT: v_mov_b32_e32 v58, v42 +; VI-NEXT: v_mov_b32_e32 v57, v41 +; VI-NEXT: v_mov_b32_e32 v56, v40 +; VI-NEXT: v_mov_b32_e32 v55, v39 +; VI-NEXT: v_mov_b32_e32 v54, v38 +; VI-NEXT: v_mov_b32_e32 v53, v37 +; VI-NEXT: v_mov_b32_e32 v52, v36 +; VI-NEXT: v_mov_b32_e32 v51, v35 +; VI-NEXT: v_mov_b32_e32 v50, v34 +; VI-NEXT: v_mov_b32_e32 v49, v33 +; VI-NEXT: v_mov_b32_e32 v48, v32 +; VI-NEXT: v_mov_b32_e32 v47, v31 +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:392 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:388 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:384 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:380 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:376 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:372 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:368 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:364 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:360 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:356 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:352 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:348 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:344 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:340 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:336 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:332 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:328 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:324 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:320 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:316 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:312 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:308 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:304 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:296 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:288 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:276 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:272 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:268 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:264 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:260 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:256 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:252 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:236 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:228 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:216 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:212 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:200 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:196 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:192 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:188 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:184 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:180 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:176 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:172 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:168 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:164 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:160 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:156 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:152 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:148 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:144 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:140 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:136 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:132 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:128 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:124 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:120 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:116 +; VI-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:112 +; VI-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:108 +; VI-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104 +; VI-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:100 +; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:96 +; VI-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:92 +; VI-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:88 +; VI-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:84 +; VI-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:80 +; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:76 +; VI-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:72 +; VI-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:68 +; VI-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:64 +; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:60 +; VI-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:56 +; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:52 +; VI-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:48 +; VI-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:44 +; VI-NEXT: buffer_load_ushort v15, off, s[0:3], s32 offset:40 +; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:36 +; VI-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:32 +; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:28 +; VI-NEXT: buffer_load_ushort v13, off, s[0:3], s32 offset:24 +; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:20 +; VI-NEXT: buffer_load_ushort v14, off, s[0:3], s32 offset:16 +; VI-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_ushort v12, off, s[0:3], s32 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB139_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(3) +; VI-NEXT: v_lshlrev_b16_e32 v28, 8, v28 +; VI-NEXT: v_lshlrev_b16_e32 v21, 8, v21 +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_or_b32_sdwa v12, v12, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v11, v11, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(8) +; VI-NEXT: v_lshlrev_b16_e32 v31, 8, v31 +; VI-NEXT: s_waitcnt vmcnt(7) +; VI-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v32, 8, v32 +; VI-NEXT: v_or_b32_sdwa v32, v33, v32 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload +; VI-NEXT: v_or_b32_sdwa v31, v31, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v33, 8, v33 +; VI-NEXT: v_or_b32_sdwa v33, v34, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v34, 8, v34 +; VI-NEXT: v_or_b32_sdwa v34, v35, v34 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v32, v33, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v33, 8, v33 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v33, v34, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v34, 8, v34 +; VI-NEXT: v_or_b32_sdwa v34, v35, v34 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v33, v33, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b16_e32 v34, 8, v34 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_sdwa v34, v35, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v35, 8, v35 +; VI-NEXT: v_or_b32_sdwa v35, v36, v35 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v34, v34, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b16_e32 v35, 8, v35 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_sdwa v35, v36, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v36, 8, v36 +; VI-NEXT: v_or_b32_sdwa v36, v37, v36 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v35, v35, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b16_e32 v36, 8, v36 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_sdwa v36, v37, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v37, 8, v37 +; VI-NEXT: v_or_b32_sdwa v37, v38, v37 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v36, v36, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b16_e32 v37, 8, v37 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_sdwa v37, v38, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v38, 8, v38 +; VI-NEXT: v_or_b32_sdwa v38, v39, v38 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v37, v37, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v38, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v30 +; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v24 +; VI-NEXT: v_or_b32_sdwa v11, v14, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v39, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v27 +; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v23 +; VI-NEXT: v_or_b32_sdwa v11, v16, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v12, v15, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v40, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v29 +; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v26 +; VI-NEXT: v_or_b32_sdwa v11, v18, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v4, v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v41, v11, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v17 +; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v25 +; VI-NEXT: v_or_b32_sdwa v4, v6, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v42, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v20 +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v19 +; VI-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v43, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v7 +; VI-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v63 +; VI-NEXT: v_or_b32_sdwa v3, v10, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v44, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v22 +; VI-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(3) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v45, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v46, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload +; VI-NEXT: v_or_b32_sdwa v47, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v5 +; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v48, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v49, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v50, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v51, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v52, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v53, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v54, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v55, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v56, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v57, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v58, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v59, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v60, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v61, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v62, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: .LBB139_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[43:46] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[39:42] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x70 +; VI-NEXT: flat_store_dwordx4 v[3:4], v[35:38] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[31:34] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x60 +; VI-NEXT: flat_store_dwordx4 v[3:4], v[59:62] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x50 +; VI-NEXT: flat_store_dwordx4 v[3:4], v[55:58] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, 64, v1 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[51:54] +; VI-NEXT: flat_store_dwordx4 v[0:1], v[47:50] +; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v128i8_to_v64bf16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:396 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill +; GFX9-NEXT: s_mov_b32 s4, 0 +; GFX9-NEXT: s_mov_b32 s19, s4 +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_mov_b32 s6, s4 +; GFX9-NEXT: s_mov_b32 s7, s4 +; GFX9-NEXT: s_mov_b32 s8, s4 +; GFX9-NEXT: s_mov_b32 s9, s4 +; GFX9-NEXT: s_mov_b32 s10, s4 +; GFX9-NEXT: s_mov_b32 s11, s4 +; GFX9-NEXT: s_mov_b32 s12, s4 +; GFX9-NEXT: s_mov_b32 s13, s4 +; GFX9-NEXT: s_mov_b32 s14, s4 +; GFX9-NEXT: s_mov_b32 s15, s4 +; GFX9-NEXT: s_mov_b32 s16, s4 +; GFX9-NEXT: s_mov_b32 s17, s4 +; GFX9-NEXT: s_mov_b32 s18, s4 +; GFX9-NEXT: v_mov_b32_e32 v46, s19 +; GFX9-NEXT: v_mov_b32_e32 v45, s18 +; GFX9-NEXT: v_mov_b32_e32 v44, s17 +; GFX9-NEXT: v_mov_b32_e32 v43, s16 +; GFX9-NEXT: v_mov_b32_e32 v42, s15 +; GFX9-NEXT: v_mov_b32_e32 v41, s14 +; GFX9-NEXT: v_mov_b32_e32 v40, s13 +; GFX9-NEXT: v_mov_b32_e32 v39, s12 +; GFX9-NEXT: v_mov_b32_e32 v38, s11 +; GFX9-NEXT: v_mov_b32_e32 v37, s10 +; GFX9-NEXT: v_mov_b32_e32 v36, s9 +; GFX9-NEXT: v_mov_b32_e32 v35, s8 +; GFX9-NEXT: v_mov_b32_e32 v34, s7 +; GFX9-NEXT: v_mov_b32_e32 v33, s6 +; GFX9-NEXT: v_mov_b32_e32 v32, s5 +; GFX9-NEXT: v_mov_b32_e32 v31, s4 +; GFX9-NEXT: v_mov_b32_e32 v62, v46 +; GFX9-NEXT: v_mov_b32_e32 v61, v45 +; GFX9-NEXT: v_mov_b32_e32 v60, v44 +; GFX9-NEXT: v_mov_b32_e32 v59, v43 +; GFX9-NEXT: v_mov_b32_e32 v58, v42 +; GFX9-NEXT: v_mov_b32_e32 v57, v41 +; GFX9-NEXT: v_mov_b32_e32 v56, v40 +; GFX9-NEXT: v_mov_b32_e32 v55, v39 +; GFX9-NEXT: v_mov_b32_e32 v54, v38 +; GFX9-NEXT: v_mov_b32_e32 v53, v37 +; GFX9-NEXT: v_mov_b32_e32 v52, v36 +; GFX9-NEXT: v_mov_b32_e32 v51, v35 +; GFX9-NEXT: v_mov_b32_e32 v50, v34 +; GFX9-NEXT: v_mov_b32_e32 v49, v33 +; GFX9-NEXT: v_mov_b32_e32 v48, v32 +; GFX9-NEXT: v_mov_b32_e32 v47, v31 +; GFX9-NEXT: s_waitcnt vmcnt(44) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:392 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:388 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:384 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:380 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:376 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:372 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:368 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:364 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:360 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:356 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:352 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:348 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:344 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:340 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:336 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:332 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:328 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:324 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:320 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:316 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:312 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:308 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:304 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:296 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:288 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:276 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:272 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:268 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:264 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:260 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:256 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:252 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:236 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:228 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:216 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:212 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:200 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:196 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:192 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:188 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:184 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:180 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:176 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:172 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:168 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:164 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:160 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:156 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:152 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:148 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:144 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:140 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:136 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:132 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:128 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:124 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:120 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:116 +; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:112 +; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:108 +; GFX9-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104 +; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:100 +; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:96 +; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:92 +; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:88 +; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:84 +; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:80 +; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:76 +; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:72 +; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:68 +; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:64 +; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:60 +; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:56 +; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:52 +; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:48 +; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:44 +; GFX9-NEXT: buffer_load_ushort v15, off, s[0:3], s32 offset:40 +; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:36 +; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:32 +; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:28 +; GFX9-NEXT: buffer_load_ushort v13, off, s[0:3], s32 offset:24 +; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:20 +; GFX9-NEXT: buffer_load_ushort v14, off, s[0:3], s32 offset:16 +; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_ushort v12, off, s[0:3], s32 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB139_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 +; GFX9-NEXT: s_waitcnt vmcnt(3) +; GFX9-NEXT: v_lshlrev_b16_e32 v28, 8, v28 +; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21 +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_or_b32_sdwa v12, v12, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v11, v11, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(8) +; GFX9-NEXT: v_lshlrev_b16_e32 v31, 8, v31 +; GFX9-NEXT: s_waitcnt vmcnt(7) +; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v32, 8, v32 +; GFX9-NEXT: v_or_b32_sdwa v32, v33, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload +; GFX9-NEXT: v_perm_b32 v31, v32, v31, s6 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v33, 8, v33 +; GFX9-NEXT: v_or_b32_sdwa v33, v34, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v34, 8, v34 +; GFX9-NEXT: v_or_b32_sdwa v34, v35, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v32, v34, v33, s6 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v33, 8, v33 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v33, v34, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v34, 8, v34 +; GFX9-NEXT: v_or_b32_sdwa v34, v35, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v33, v34, v33, s6 +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshlrev_b16_e32 v34, 8, v34 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_or_b32_sdwa v34, v35, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v35 +; GFX9-NEXT: v_or_b32_sdwa v35, v36, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v34, v35, v34, s6 +; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v35 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_or_b32_sdwa v35, v36, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v36, 8, v36 +; GFX9-NEXT: v_or_b32_sdwa v36, v37, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v35, v36, v35, s6 +; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshlrev_b16_e32 v36, 8, v36 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_or_b32_sdwa v36, v37, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v37 +; GFX9-NEXT: v_or_b32_sdwa v37, v38, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v36, v37, v36, s6 +; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v37 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_or_b32_sdwa v37, v38, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v38 +; GFX9-NEXT: v_or_b32_sdwa v38, v39, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v37, v38, v37, s6 +; GFX9-NEXT: v_perm_b32 v38, v11, v12, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v30 +; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v24 +; GFX9-NEXT: v_or_b32_sdwa v11, v14, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v39, v12, v11, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v27 +; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v23 +; GFX9-NEXT: v_or_b32_sdwa v11, v16, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v12, v15, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v40, v12, v11, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29 +; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v26 +; GFX9-NEXT: v_or_b32_sdwa v11, v18, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v4, v4, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v41, v4, v11, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v17 +; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v25 +; GFX9-NEXT: v_or_b32_sdwa v4, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v42, v4, v3, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v20 +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v19 +; GFX9-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v43, v4, v3, s6 +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7 +; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v63 +; GFX9-NEXT: v_or_b32_sdwa v3, v10, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v44, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v22 +; GFX9-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(3) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v45, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v46, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload +; GFX9-NEXT: v_perm_b32 v47, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4 +; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v5 +; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v48, v5, v4, s6 +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v49, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v50, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v51, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v52, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v53, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v54, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v55, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v56, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v57, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v58, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v59, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v60, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v61, v3, v0, s6 +; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(2) +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_perm_b32 v62, v3, v0, s6 +; GFX9-NEXT: .LBB139_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[43:46], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[39:42], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[35:38], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[59:62], off offset:112 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[55:58], off offset:96 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[51:54], off offset:80 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[47:50], off offset:64 +; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-TRUE16-LABEL: v_bitcast_v128i8_to_v64bf16: +; GFX11-TRUE16: ; %bb.0: ; %entry +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_clause 0xe +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:456 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:452 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:448 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:444 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:440 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:436 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:432 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:428 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:424 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:420 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:416 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:412 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:408 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:404 +; GFX11-TRUE16-NEXT: ; meta instruction +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:400 +; GFX11-TRUE16-NEXT: s_clause 0x1f +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:396 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:392 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:388 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:384 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:380 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:376 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:372 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:368 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:364 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:360 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:356 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:352 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:348 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:344 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:340 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:336 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:332 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v80, off, s32 offset:328 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:324 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v81, off, s32 offset:320 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:316 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v82, off, s32 offset:312 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:308 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v83, off, s32 offset:304 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:300 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v84, off, s32 offset:296 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:292 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v85, off, s32 offset:288 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:284 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v86, off, s32 offset:280 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:276 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v87, off, s32 offset:272 +; GFX11-TRUE16-NEXT: s_clause 0x1f +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:268 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v96, off, s32 offset:264 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:260 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v97, off, s32 offset:256 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:252 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v98, off, s32 offset:248 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:244 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v99, off, s32 offset:240 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:236 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v100, off, s32 offset:232 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:228 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v101, off, s32 offset:224 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:220 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v102, off, s32 offset:216 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:212 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v103, off, s32 offset:208 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:204 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v112, off, s32 offset:200 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:196 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v113, off, s32 offset:192 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:188 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v114, off, s32 offset:184 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:180 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v115, off, s32 offset:176 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:172 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v116, off, s32 offset:168 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:164 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v117, off, s32 offset:160 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:156 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v118, off, s32 offset:152 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:148 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v119, off, s32 offset:144 +; GFX11-TRUE16-NEXT: s_clause 0x1f +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:140 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v128, off, s32 offset:136 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:132 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v129, off, s32 offset:128 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:124 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v130, off, s32 offset:120 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:116 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v131, off, s32 offset:112 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:108 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v132, off, s32 offset:104 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:100 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v133, off, s32 offset:96 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:92 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v134, off, s32 offset:88 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:84 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v135, off, s32 offset:80 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:76 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v144, off, s32 offset:72 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:68 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v145, off, s32 offset:64 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:60 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v146, off, s32 offset:56 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:52 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v147, off, s32 offset:48 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:44 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v148, off, s32 offset:40 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:36 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v149, off, s32 offset:32 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:28 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v150, off, s32 offset:24 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:20 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v151, off, s32 offset:16 +; GFX11-TRUE16-NEXT: s_clause 0x3 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:12 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v160, off, s32 offset:8 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:4 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v161, off, s32 +; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-TRUE16-NEXT: s_mov_b32 s15, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s1, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s2, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s3, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s5, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s6, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s7, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s9, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s10, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s11, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s13, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s14, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v46, s15 :: v_dual_mov_b32 v45, s14 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s13 :: v_dual_mov_b32 v43, s12 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v42, s11 :: v_dual_mov_b32 v41, s10 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v40, s9 :: v_dual_mov_b32 v39, s8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v38, s7 :: v_dual_mov_b32 v37, s6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v36, s5 :: v_dual_mov_b32 v35, s4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, s3 :: v_dual_mov_b32 v33, s2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, s1 :: v_dual_mov_b32 v31, s0 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v62, v46 :: v_dual_mov_b32 v61, v45 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v60, v44 :: v_dual_mov_b32 v59, v43 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v58, v42 :: v_dual_mov_b32 v57, v41 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v56, v40 :: v_dual_mov_b32 v55, v39 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, v38 :: v_dual_mov_b32 v53, v37 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, v36 :: v_dual_mov_b32 v51, v35 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v50, v34 :: v_dual_mov_b32 v49, v33 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v48, v32 :: v_dual_mov_b32 v47, v31 +; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX11-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB139_2 +; GFX11-TRUE16-NEXT: ; %bb.1: ; %if +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v4.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v5.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v6.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v7.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v8.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v9.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v10.l +; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v11.l +; GFX11-TRUE16-NEXT: v_or_b16 v32.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v12.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v13.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v14.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v15.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v16.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v17.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v18.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v19.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v20.l +; GFX11-TRUE16-NEXT: v_or_b16 v33.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v33.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v34.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v34.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v35.l, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v21.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v22.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v23.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v24.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v25.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v26.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v27.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v28.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v29.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v30.l +; GFX11-TRUE16-NEXT: v_or_b16 v35.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v36.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v36.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v37.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v37.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v161.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v161.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v160.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v160.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v151.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v151.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v150.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v150.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v149.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v149.l +; GFX11-TRUE16-NEXT: v_or_b16 v38.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v38.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v39.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v39.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v40.l, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v148.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v148.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v147.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v147.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v146.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v146.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v145.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v145.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v144.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v144.l +; GFX11-TRUE16-NEXT: v_or_b16 v40.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v41.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v41.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v42.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v42.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v135.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v135.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v134.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v134.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v133.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v133.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v132.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v132.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v131.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v131.l +; GFX11-TRUE16-NEXT: v_or_b16 v43.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v43.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v44.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v44.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v45.l, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v130.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v130.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v129.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v129.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v128.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v128.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v119.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v119.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v118.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v118.l +; GFX11-TRUE16-NEXT: v_or_b16 v45.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v46.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v46.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v47.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v47.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v117.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v117.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v116.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v116.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v115.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v115.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v114.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v114.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v113.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v113.l +; GFX11-TRUE16-NEXT: v_or_b16 v48.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v48.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v49.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v49.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v50.l, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v112.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v112.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v103.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v103.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v102.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v102.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v101.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v101.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v100.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v100.l +; GFX11-TRUE16-NEXT: v_or_b16 v50.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v51.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v51.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v52.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v52.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v99.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v99.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v98.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v98.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v97.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v97.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v96.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v96.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v87.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v87.l +; GFX11-TRUE16-NEXT: v_or_b16 v53.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v53.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v54.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v54.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v55.l, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v86.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v86.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v85.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v85.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v84.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v84.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v83.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v83.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v82.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v82.l +; GFX11-TRUE16-NEXT: v_or_b16 v55.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v56.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v56.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v57.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v57.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v81.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v81.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v80.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v80.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v71.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v71.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v70.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v70.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v69.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v69.l +; GFX11-TRUE16-NEXT: v_or_b16 v58.l, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v58.h, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v59.l, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v59.h, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v60.l, v6.l, v6.h +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v68.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v68.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v67.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v67.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v66.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v66.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v65.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v65.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v64.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v64.l +; GFX11-TRUE16-NEXT: v_or_b16 v60.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_or_b16 v61.l, v3.l, v3.h +; GFX11-TRUE16-NEXT: v_or_b16 v61.h, v4.l, v4.h +; GFX11-TRUE16-NEXT: v_or_b16 v62.l, v5.l, v5.h +; GFX11-TRUE16-NEXT: v_or_b16 v62.h, v6.l, v6.h +; GFX11-TRUE16-NEXT: .LBB139_2: ; %end +; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-TRUE16-NEXT: s_clause 0x7 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[43:46], off offset:48 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[39:42], off offset:32 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[35:38], off offset:16 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[31:34], off +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[59:62], off offset:112 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[55:58], off offset:96 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[51:54], off offset:80 +; GFX11-TRUE16-NEXT: global_store_b128 v[1:2], v[47:50], off offset:64 +; GFX11-TRUE16-NEXT: s_clause 0xe +; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:400 +; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:404 +; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:408 +; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:412 +; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:416 +; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:420 +; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:424 +; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:428 +; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:432 +; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:436 +; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:440 +; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:444 +; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:448 +; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:452 +; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:456 +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: v_bitcast_v128i8_to_v64bf16: +; GFX11-FAKE16: ; %bb.0: ; %entry +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_clause 0x1f +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:600 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:596 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:592 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:588 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:584 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:580 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:576 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:572 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:568 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:564 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:560 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:556 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:552 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:548 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:544 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:540 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:536 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:532 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:528 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:524 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:520 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:516 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:512 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:508 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:504 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:500 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:496 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:492 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:488 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:484 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:480 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:476 +; GFX11-FAKE16-NEXT: s_clause 0x12 +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:472 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:468 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:464 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:460 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:456 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:452 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:448 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:444 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:440 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:436 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:432 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:428 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:424 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:420 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:416 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:412 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:408 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:404 +; GFX11-FAKE16-NEXT: ; meta instruction +; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:400 +; GFX11-FAKE16-NEXT: s_clause 0x1f +; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:396 +; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:392 +; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:388 +; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:384 +; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:380 +; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:376 +; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:372 +; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:368 +; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:364 +; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:360 +; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:356 +; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:352 +; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:348 +; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:344 +; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:340 +; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:336 +; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:332 +; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:328 +; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:324 +; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:320 +; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:316 +; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:312 +; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:308 +; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:304 +; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:300 +; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:296 +; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:292 +; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:288 +; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:284 +; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:280 +; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:276 +; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:272 +; GFX11-FAKE16-NEXT: s_clause 0x1f +; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:268 +; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:264 +; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:260 +; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:256 +; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:252 +; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:248 +; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:244 +; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:240 +; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:236 +; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:232 +; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:228 +; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:224 +; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:220 +; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:216 +; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:212 +; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:208 +; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:204 +; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:200 +; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:196 +; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:192 +; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:188 +; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:184 +; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:180 +; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:176 +; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:172 +; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:168 +; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:164 +; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:160 +; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:156 +; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:152 +; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:148 +; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:144 +; GFX11-FAKE16-NEXT: s_clause 0x1f +; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:140 +; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:136 +; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:132 +; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:128 +; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:124 +; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:120 +; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:116 +; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:112 +; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:108 +; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:104 +; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:100 +; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:96 +; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:92 +; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:88 +; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:84 +; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:80 +; GFX11-FAKE16-NEXT: scratch_load_u16 v95, off, s32 offset:76 +; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:72 +; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:68 +; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:64 +; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:60 +; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:56 +; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:52 +; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:48 +; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:44 +; GFX11-FAKE16-NEXT: scratch_load_u16 v120, off, s32 offset:40 +; GFX11-FAKE16-NEXT: scratch_load_u16 v121, off, s32 offset:36 +; GFX11-FAKE16-NEXT: scratch_load_u16 v122, off, s32 offset:32 +; GFX11-FAKE16-NEXT: scratch_load_u16 v123, off, s32 offset:28 +; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32 offset:24 +; GFX11-FAKE16-NEXT: scratch_load_u16 v125, off, s32 offset:20 +; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:16 +; GFX11-FAKE16-NEXT: s_clause 0x3 +; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32 offset:12 +; GFX11-FAKE16-NEXT: scratch_load_u16 v136, off, s32 offset:8 +; GFX11-FAKE16-NEXT: scratch_load_u16 v137, off, s32 offset:4 +; GFX11-FAKE16-NEXT: scratch_load_u16 v138, off, s32 +; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-FAKE16-NEXT: s_mov_b32 s15, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s1, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s2, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s3, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s5, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s6, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s7, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s9, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s10, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s11, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s13, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s14, s0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v46, s15 :: v_dual_mov_b32 v45, s14 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v44, s13 :: v_dual_mov_b32 v43, s12 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v42, s11 :: v_dual_mov_b32 v41, s10 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v40, s9 :: v_dual_mov_b32 v39, s8 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, s7 :: v_dual_mov_b32 v37, s6 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, s5 :: v_dual_mov_b32 v35, s4 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s3 :: v_dual_mov_b32 v33, s2 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s1 :: v_dual_mov_b32 v31, s0 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v62, v46 :: v_dual_mov_b32 v61, v45 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v60, v44 :: v_dual_mov_b32 v59, v43 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v58, v42 :: v_dual_mov_b32 v57, v41 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v56, v40 :: v_dual_mov_b32 v55, v39 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v38 :: v_dual_mov_b32 v53, v37 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v36 :: v_dual_mov_b32 v51, v35 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v34 :: v_dual_mov_b32 v49, v33 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v32 :: v_dual_mov_b32 v47, v31 +; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo +; GFX11-FAKE16-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB139_2 +; GFX11-FAKE16-NEXT: ; %bb.1: ; %if +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v6 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v15 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v31, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v11 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v12 +; GFX11-FAKE16-NEXT: v_perm_b32 v32, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v13 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v14 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v18 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v20 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v21 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v22 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v23 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v24 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v25 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v26 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v28 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v29 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v30 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v33, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v34, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v35, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v36, v9, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v37, v11, v10, 0x5040100 +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v138 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v137 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v136 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v127 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v126 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v125 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v124 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v123 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v122 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v121 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v120 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v111 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v110 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v109 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v108 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v107 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v106 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v105 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v104 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v38, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v39, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v40, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v41, v9, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v42, v11, v10, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v94 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v93 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v92 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v91 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v90 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v89 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v88 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v79 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v78 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v77 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v76 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v75 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v74 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v73 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v72 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v63 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v183 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v182 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v181 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v180 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v43, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v44, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v45, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v46, v9, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v47, v11, v10, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v179 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v178 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v177 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v176 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v167 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v166 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v165 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v164 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v163 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v162 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v161 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v160 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v151 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v150 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v149 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v148 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v147 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v146 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v145 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v144 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v48, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v49, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v50, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v51, v9, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v52, v11, v10, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v135 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v134 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v133 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v132 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v131 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v130 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v129 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v128 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v119 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v118 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v117 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v116 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v115 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v114 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v113 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v103 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v102 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v101 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v100 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v53, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v54, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v55, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v56, v9, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v57, v11, v10, 0x5040100 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v99 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v98 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v97 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v96 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v87 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v86 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v85 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v84 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v83 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v82 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v81 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v80 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v71 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v70 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v69 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v68 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v67 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v66 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v65 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v64 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 +; GFX11-FAKE16-NEXT: v_perm_b32 v58, v3, v0, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v59, v5, v4, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v60, v7, v6, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v61, v9, v8, 0x5040100 +; GFX11-FAKE16-NEXT: v_perm_b32 v62, v11, v10, 0x5040100 +; GFX11-FAKE16-NEXT: .LBB139_2: ; %end +; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-FAKE16-NEXT: s_clause 0x7 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[43:46], off offset:48 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[39:42], off offset:32 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[35:38], off offset:16 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[31:34], off +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[59:62], off offset:112 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[55:58], off offset:96 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[51:54], off offset:80 +; GFX11-FAKE16-NEXT: global_store_b128 v[1:2], v[47:50], off offset:64 +; GFX11-FAKE16-NEXT: s_clause 0x1f +; GFX11-FAKE16-NEXT: scratch_load_b32 v138, off, s32 offset:400 +; GFX11-FAKE16-NEXT: scratch_load_b32 v137, off, s32 offset:404 +; GFX11-FAKE16-NEXT: scratch_load_b32 v136, off, s32 offset:408 +; GFX11-FAKE16-NEXT: scratch_load_b32 v127, off, s32 offset:412 +; GFX11-FAKE16-NEXT: scratch_load_b32 v126, off, s32 offset:416 +; GFX11-FAKE16-NEXT: scratch_load_b32 v125, off, s32 offset:420 +; GFX11-FAKE16-NEXT: scratch_load_b32 v124, off, s32 offset:424 +; GFX11-FAKE16-NEXT: scratch_load_b32 v123, off, s32 offset:428 +; GFX11-FAKE16-NEXT: scratch_load_b32 v122, off, s32 offset:432 +; GFX11-FAKE16-NEXT: scratch_load_b32 v121, off, s32 offset:436 +; GFX11-FAKE16-NEXT: scratch_load_b32 v120, off, s32 offset:440 +; GFX11-FAKE16-NEXT: scratch_load_b32 v111, off, s32 offset:444 +; GFX11-FAKE16-NEXT: scratch_load_b32 v110, off, s32 offset:448 +; GFX11-FAKE16-NEXT: scratch_load_b32 v109, off, s32 offset:452 +; GFX11-FAKE16-NEXT: scratch_load_b32 v108, off, s32 offset:456 +; GFX11-FAKE16-NEXT: scratch_load_b32 v107, off, s32 offset:460 +; GFX11-FAKE16-NEXT: scratch_load_b32 v106, off, s32 offset:464 +; GFX11-FAKE16-NEXT: scratch_load_b32 v105, off, s32 offset:468 +; GFX11-FAKE16-NEXT: scratch_load_b32 v104, off, s32 offset:472 +; GFX11-FAKE16-NEXT: scratch_load_b32 v95, off, s32 offset:476 +; GFX11-FAKE16-NEXT: scratch_load_b32 v94, off, s32 offset:480 +; GFX11-FAKE16-NEXT: scratch_load_b32 v93, off, s32 offset:484 +; GFX11-FAKE16-NEXT: scratch_load_b32 v92, off, s32 offset:488 +; GFX11-FAKE16-NEXT: scratch_load_b32 v91, off, s32 offset:492 +; GFX11-FAKE16-NEXT: scratch_load_b32 v90, off, s32 offset:496 +; GFX11-FAKE16-NEXT: scratch_load_b32 v89, off, s32 offset:500 +; GFX11-FAKE16-NEXT: scratch_load_b32 v88, off, s32 offset:504 +; GFX11-FAKE16-NEXT: scratch_load_b32 v79, off, s32 offset:508 +; GFX11-FAKE16-NEXT: scratch_load_b32 v78, off, s32 offset:512 +; GFX11-FAKE16-NEXT: scratch_load_b32 v77, off, s32 offset:516 +; GFX11-FAKE16-NEXT: scratch_load_b32 v76, off, s32 offset:520 +; GFX11-FAKE16-NEXT: scratch_load_b32 v75, off, s32 offset:524 +; GFX11-FAKE16-NEXT: s_clause 0x12 +; GFX11-FAKE16-NEXT: scratch_load_b32 v74, off, s32 offset:528 +; GFX11-FAKE16-NEXT: scratch_load_b32 v73, off, s32 offset:532 +; GFX11-FAKE16-NEXT: scratch_load_b32 v72, off, s32 offset:536 +; GFX11-FAKE16-NEXT: scratch_load_b32 v63, off, s32 offset:540 +; GFX11-FAKE16-NEXT: scratch_load_b32 v62, off, s32 offset:544 +; GFX11-FAKE16-NEXT: scratch_load_b32 v61, off, s32 offset:548 +; GFX11-FAKE16-NEXT: scratch_load_b32 v60, off, s32 offset:552 +; GFX11-FAKE16-NEXT: scratch_load_b32 v59, off, s32 offset:556 +; GFX11-FAKE16-NEXT: scratch_load_b32 v58, off, s32 offset:560 +; GFX11-FAKE16-NEXT: scratch_load_b32 v57, off, s32 offset:564 +; GFX11-FAKE16-NEXT: scratch_load_b32 v56, off, s32 offset:568 +; GFX11-FAKE16-NEXT: scratch_load_b32 v47, off, s32 offset:572 +; GFX11-FAKE16-NEXT: scratch_load_b32 v46, off, s32 offset:576 +; GFX11-FAKE16-NEXT: scratch_load_b32 v45, off, s32 offset:580 +; GFX11-FAKE16-NEXT: scratch_load_b32 v44, off, s32 offset:584 +; GFX11-FAKE16-NEXT: scratch_load_b32 v43, off, s32 offset:588 +; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s32 offset:592 +; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:596 +; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:600 +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <128 x i8> %value to <64 x bfloat> + br label %end + +end: + %phi = phi <64 x bfloat> [zeroinitializer, %entry], [%cast, %if] + store <64 x bfloat> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v64bf16_to_v64i16(i32 %cond, ptr addrspace(1) %out, <64 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v64bf16_to_v64i16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:136 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:124 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:120 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:108 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:104 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:80 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:76 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:72 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:68 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:60 +; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:56 +; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:52 +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:48 +; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:44 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 +; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:36 +; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:32 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:28 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:24 +; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:20 +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 +; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:12 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v32, v31 +; GCN-NEXT: v_mov_b32_e32 v33, v31 +; GCN-NEXT: v_mov_b32_e32 v34, v31 +; GCN-NEXT: v_mov_b32_e32 v35, v31 +; GCN-NEXT: v_mov_b32_e32 v36, v31 +; GCN-NEXT: v_mov_b32_e32 v37, v31 +; GCN-NEXT: v_mov_b32_e32 v38, v31 +; GCN-NEXT: v_mov_b32_e32 v48, v31 +; GCN-NEXT: v_mov_b32_e32 v49, v31 +; GCN-NEXT: v_mov_b32_e32 v50, v31 +; GCN-NEXT: v_mov_b32_e32 v51, v31 +; GCN-NEXT: v_mov_b32_e32 v52, v31 +; GCN-NEXT: v_mov_b32_e32 v53, v31 +; GCN-NEXT: v_mov_b32_e32 v54, v31 +; GCN-NEXT: v_mov_b32_e32 v55, v31 +; GCN-NEXT: v_mov_b32_e32 v39, v31 +; GCN-NEXT: v_mov_b32_e32 v40, v31 +; GCN-NEXT: v_mov_b32_e32 v41, v31 +; GCN-NEXT: v_mov_b32_e32 v42, v31 +; GCN-NEXT: v_mov_b32_e32 v43, v31 +; GCN-NEXT: v_mov_b32_e32 v44, v31 +; GCN-NEXT: v_mov_b32_e32 v45, v31 +; GCN-NEXT: v_mov_b32_e32 v46, v31 +; GCN-NEXT: v_mov_b32_e32 v56, v31 +; GCN-NEXT: v_mov_b32_e32 v57, v31 +; GCN-NEXT: v_mov_b32_e32 v58, v31 +; GCN-NEXT: v_mov_b32_e32 v59, v31 +; GCN-NEXT: v_mov_b32_e32 v60, v31 +; GCN-NEXT: v_mov_b32_e32 v61, v31 +; GCN-NEXT: v_mov_b32_e32 v62, v31 +; GCN-NEXT: v_mov_b32_e32 v63, v31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB140_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v31, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v32, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_alignbit_b32 v33, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_alignbit_b32 v34, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v35, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v36, v4, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v48, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v37, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v50, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v38, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v51, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v52, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v49, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v60, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v59, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v45, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v62, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v40, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v63, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v53, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v61, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v55, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v41, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v47 +; GCN-NEXT: v_mul_f32_e32 v42, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v43, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v44, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v46, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v56, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v57, 1.0, v29 +; GCN-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v10 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v58, 1.0, v11 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v12 +; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v12 +; GCN-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v13 +; GCN-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v14 +; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v14 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v16 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v16 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v17 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v18 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v18 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v19 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v48 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v50 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v51 +; GCN-NEXT: v_lshrrev_b32_e32 v50, 16, v52 +; GCN-NEXT: v_lshrrev_b32_e32 v51, 16, v60 +; GCN-NEXT: v_lshrrev_b32_e32 v52, 16, v45 +; GCN-NEXT: v_lshrrev_b32_e32 v40, 16, v40 +; GCN-NEXT: v_lshrrev_b32_e32 v53, 16, v53 +; GCN-NEXT: v_lshrrev_b32_e32 v54, 16, v54 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v41, 16, v41 +; GCN-NEXT: v_lshrrev_b32_e32 v42, 16, v42 +; GCN-NEXT: v_lshrrev_b32_e32 v43, 16, v43 +; GCN-NEXT: v_lshrrev_b32_e32 v44, 16, v44 +; GCN-NEXT: v_lshrrev_b32_e32 v45, 16, v46 +; GCN-NEXT: v_lshrrev_b32_e32 v46, 16, v56 +; GCN-NEXT: v_lshrrev_b32_e32 v47, 16, v57 +; GCN-NEXT: v_lshrrev_b32_e32 v56, 16, v58 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_alignbit_b32 v37, v22, v37, 16 +; GCN-NEXT: v_alignbit_b32 v38, v29, v38, 16 +; GCN-NEXT: v_alignbit_b32 v48, v30, v39, 16 +; GCN-NEXT: v_alignbit_b32 v49, v50, v49, 16 +; GCN-NEXT: v_alignbit_b32 v50, v51, v59, 16 +; GCN-NEXT: v_alignbit_b32 v51, v52, v62, 16 +; GCN-NEXT: v_alignbit_b32 v52, v40, v63, 16 +; GCN-NEXT: v_alignbit_b32 v53, v53, v61, 16 +; GCN-NEXT: v_alignbit_b32 v54, v54, v0, 16 +; GCN-NEXT: v_alignbit_b32 v55, v55, v3, 16 +; GCN-NEXT: v_alignbit_b32 v39, v41, v4, 16 +; GCN-NEXT: v_alignbit_b32 v40, v42, v5, 16 +; GCN-NEXT: v_alignbit_b32 v41, v43, v6, 16 +; GCN-NEXT: v_alignbit_b32 v42, v44, v7, 16 +; GCN-NEXT: v_alignbit_b32 v43, v45, v8, 16 +; GCN-NEXT: v_alignbit_b32 v44, v46, v9, 16 +; GCN-NEXT: v_alignbit_b32 v45, v47, v10, 16 +; GCN-NEXT: v_alignbit_b32 v46, v56, v11, 16 +; GCN-NEXT: v_alignbit_b32 v56, v27, v12, 16 +; GCN-NEXT: v_alignbit_b32 v57, v26, v13, 16 +; GCN-NEXT: v_alignbit_b32 v58, v25, v14, 16 +; GCN-NEXT: v_alignbit_b32 v59, v28, v15, 16 +; GCN-NEXT: v_alignbit_b32 v60, v23, v16, 16 +; GCN-NEXT: v_alignbit_b32 v61, v24, v17, 16 +; GCN-NEXT: v_alignbit_b32 v62, v20, v18, 16 +; GCN-NEXT: v_alignbit_b32 v63, v21, v19, 16 +; GCN-NEXT: .LBB140_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[60:63], v[1:2], s[4:7], 0 addr64 offset:112 +; GCN-NEXT: buffer_store_dwordx4 v[56:59], v[1:2], s[4:7], 0 addr64 offset:96 +; GCN-NEXT: buffer_store_dwordx4 v[43:46], v[1:2], s[4:7], 0 addr64 offset:80 +; GCN-NEXT: buffer_store_dwordx4 v[39:42], v[1:2], s[4:7], 0 addr64 offset:64 +; GCN-NEXT: buffer_store_dwordx4 v[52:55], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[48:51], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[35:38], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[31:34], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(6) +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(14) +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(5) +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(4) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v64bf16_to_v64i16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; VI-NEXT: s_mov_b32 s4, 0 +; VI-NEXT: s_mov_b32 s19, s4 +; VI-NEXT: s_mov_b32 s5, s4 +; VI-NEXT: s_mov_b32 s6, s4 +; VI-NEXT: s_mov_b32 s7, s4 +; VI-NEXT: s_mov_b32 s8, s4 +; VI-NEXT: s_mov_b32 s9, s4 +; VI-NEXT: s_mov_b32 s10, s4 +; VI-NEXT: s_mov_b32 s11, s4 +; VI-NEXT: s_mov_b32 s12, s4 +; VI-NEXT: s_mov_b32 s13, s4 +; VI-NEXT: s_mov_b32 s14, s4 +; VI-NEXT: s_mov_b32 s15, s4 +; VI-NEXT: s_mov_b32 s16, s4 +; VI-NEXT: s_mov_b32 s17, s4 +; VI-NEXT: s_mov_b32 s18, s4 +; VI-NEXT: v_mov_b32_e32 v50, s19 +; VI-NEXT: v_mov_b32_e32 v49, s18 +; VI-NEXT: v_mov_b32_e32 v48, s17 +; VI-NEXT: v_mov_b32_e32 v47, s16 +; VI-NEXT: v_mov_b32_e32 v46, s15 +; VI-NEXT: v_mov_b32_e32 v45, s14 +; VI-NEXT: v_mov_b32_e32 v44, s13 +; VI-NEXT: v_mov_b32_e32 v43, s12 +; VI-NEXT: v_mov_b32_e32 v42, s11 +; VI-NEXT: v_mov_b32_e32 v41, s10 +; VI-NEXT: v_mov_b32_e32 v40, s9 +; VI-NEXT: v_mov_b32_e32 v39, s8 +; VI-NEXT: v_mov_b32_e32 v38, s7 +; VI-NEXT: v_mov_b32_e32 v37, s6 +; VI-NEXT: v_mov_b32_e32 v36, s5 +; VI-NEXT: v_mov_b32_e32 v35, s4 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB140_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v50, v18 +; VI-NEXT: v_mov_b32_e32 v49, v17 +; VI-NEXT: v_mov_b32_e32 v48, v16 +; VI-NEXT: v_mov_b32_e32 v47, v15 +; VI-NEXT: v_mov_b32_e32 v46, v14 +; VI-NEXT: v_mov_b32_e32 v45, v13 +; VI-NEXT: v_mov_b32_e32 v44, v12 +; VI-NEXT: v_mov_b32_e32 v43, v11 +; VI-NEXT: v_mov_b32_e32 v42, v10 +; VI-NEXT: v_mov_b32_e32 v41, v9 +; VI-NEXT: v_mov_b32_e32 v40, v8 +; VI-NEXT: v_mov_b32_e32 v39, v7 +; VI-NEXT: v_mov_b32_e32 v38, v6 +; VI-NEXT: v_mov_b32_e32 v37, v5 +; VI-NEXT: v_mov_b32_e32 v36, v4 +; VI-NEXT: v_mov_b32_e32 v35, v3 +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: .LBB140_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[47:50] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[43:46] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[39:42] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[35:38] +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; VI-NEXT: s_movk_i32 s4, 0x70 +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x60 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dwordx4 v[3:4], v[17:20] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x50 +; VI-NEXT: flat_store_dwordx4 v[3:4], v[13:16] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, 64, v1 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[9:12] +; VI-NEXT: flat_store_dwordx4 v[0:1], v[5:8] +; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v64bf16_to_v64i16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GFX9-NEXT: s_mov_b32 s4, 0 +; GFX9-NEXT: s_mov_b32 s19, s4 +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_mov_b32 s6, s4 +; GFX9-NEXT: s_mov_b32 s7, s4 +; GFX9-NEXT: s_mov_b32 s8, s4 +; GFX9-NEXT: s_mov_b32 s9, s4 +; GFX9-NEXT: s_mov_b32 s10, s4 +; GFX9-NEXT: s_mov_b32 s11, s4 +; GFX9-NEXT: s_mov_b32 s12, s4 +; GFX9-NEXT: s_mov_b32 s13, s4 +; GFX9-NEXT: s_mov_b32 s14, s4 +; GFX9-NEXT: s_mov_b32 s15, s4 +; GFX9-NEXT: s_mov_b32 s16, s4 +; GFX9-NEXT: s_mov_b32 s17, s4 +; GFX9-NEXT: s_mov_b32 s18, s4 +; GFX9-NEXT: v_mov_b32_e32 v50, s19 +; GFX9-NEXT: v_mov_b32_e32 v49, s18 +; GFX9-NEXT: v_mov_b32_e32 v48, s17 +; GFX9-NEXT: v_mov_b32_e32 v47, s16 +; GFX9-NEXT: v_mov_b32_e32 v46, s15 +; GFX9-NEXT: v_mov_b32_e32 v45, s14 +; GFX9-NEXT: v_mov_b32_e32 v44, s13 +; GFX9-NEXT: v_mov_b32_e32 v43, s12 +; GFX9-NEXT: v_mov_b32_e32 v42, s11 +; GFX9-NEXT: v_mov_b32_e32 v41, s10 +; GFX9-NEXT: v_mov_b32_e32 v40, s9 +; GFX9-NEXT: v_mov_b32_e32 v39, s8 +; GFX9-NEXT: v_mov_b32_e32 v38, s7 +; GFX9-NEXT: v_mov_b32_e32 v37, s6 +; GFX9-NEXT: v_mov_b32_e32 v36, s5 +; GFX9-NEXT: v_mov_b32_e32 v35, s4 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB140_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v50, v18 +; GFX9-NEXT: v_mov_b32_e32 v49, v17 +; GFX9-NEXT: v_mov_b32_e32 v48, v16 +; GFX9-NEXT: v_mov_b32_e32 v47, v15 +; GFX9-NEXT: v_mov_b32_e32 v46, v14 +; GFX9-NEXT: v_mov_b32_e32 v45, v13 +; GFX9-NEXT: v_mov_b32_e32 v44, v12 +; GFX9-NEXT: v_mov_b32_e32 v43, v11 +; GFX9-NEXT: v_mov_b32_e32 v42, v10 +; GFX9-NEXT: v_mov_b32_e32 v41, v9 +; GFX9-NEXT: v_mov_b32_e32 v40, v8 +; GFX9-NEXT: v_mov_b32_e32 v39, v7 +; GFX9-NEXT: v_mov_b32_e32 v38, v6 +; GFX9-NEXT: v_mov_b32_e32 v37, v5 +; GFX9-NEXT: v_mov_b32_e32 v36, v4 +; GFX9-NEXT: v_mov_b32_e32 v35, v3 +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: s_waitcnt vmcnt(28) +; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: .LBB140_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[47:50], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[43:46], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[39:42], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[35:38], off +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:112 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off offset:96 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off offset:80 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[3:6], off offset:64 +; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v64bf16_to_v64i16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_mov_b32 s15, s0 +; GFX11-NEXT: s_mov_b32 s1, s0 +; GFX11-NEXT: s_mov_b32 s2, s0 +; GFX11-NEXT: s_mov_b32 s3, s0 +; GFX11-NEXT: s_mov_b32 s4, s0 +; GFX11-NEXT: s_mov_b32 s5, s0 +; GFX11-NEXT: s_mov_b32 s6, s0 +; GFX11-NEXT: s_mov_b32 s7, s0 +; GFX11-NEXT: s_mov_b32 s8, s0 +; GFX11-NEXT: s_mov_b32 s9, s0 +; GFX11-NEXT: s_mov_b32 s10, s0 +; GFX11-NEXT: s_mov_b32 s11, s0 +; GFX11-NEXT: s_mov_b32 s12, s0 +; GFX11-NEXT: s_mov_b32 s13, s0 +; GFX11-NEXT: s_mov_b32 s14, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v66, s15 :: v_dual_mov_b32 v65, s14 +; GFX11-NEXT: v_dual_mov_b32 v52, s1 :: v_dual_mov_b32 v51, s0 +; GFX11-NEXT: v_dual_mov_b32 v64, s13 :: v_dual_mov_b32 v63, s12 +; GFX11-NEXT: v_dual_mov_b32 v62, s11 :: v_dual_mov_b32 v61, s10 +; GFX11-NEXT: v_dual_mov_b32 v60, s9 :: v_dual_mov_b32 v59, s8 +; GFX11-NEXT: v_dual_mov_b32 v58, s7 :: v_dual_mov_b32 v57, s6 +; GFX11-NEXT: v_dual_mov_b32 v56, s5 :: v_dual_mov_b32 v55, s4 +; GFX11-NEXT: v_dual_mov_b32 v54, s3 :: v_dual_mov_b32 v53, s2 +; GFX11-NEXT: v_dual_mov_b32 v35, v51 :: v_dual_mov_b32 v36, v52 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_dual_mov_b32 v39, v55 :: v_dual_mov_b32 v40, v56 +; GFX11-NEXT: v_dual_mov_b32 v37, v53 :: v_dual_mov_b32 v38, v54 +; GFX11-NEXT: v_dual_mov_b32 v41, v57 :: v_dual_mov_b32 v42, v58 +; GFX11-NEXT: v_dual_mov_b32 v43, v59 :: v_dual_mov_b32 v44, v60 +; GFX11-NEXT: v_dual_mov_b32 v45, v61 :: v_dual_mov_b32 v46, v62 +; GFX11-NEXT: v_dual_mov_b32 v47, v63 :: v_dual_mov_b32 v48, v64 +; GFX11-NEXT: v_dual_mov_b32 v49, v65 :: v_dual_mov_b32 v50, v66 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB140_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v66, v18 :: v_dual_mov_b32 v65, v17 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v50, v34 :: v_dual_mov_b32 v49, v33 +; GFX11-NEXT: v_dual_mov_b32 v64, v16 :: v_dual_mov_b32 v63, v15 +; GFX11-NEXT: v_dual_mov_b32 v62, v14 :: v_dual_mov_b32 v61, v13 +; GFX11-NEXT: v_dual_mov_b32 v60, v12 :: v_dual_mov_b32 v59, v11 +; GFX11-NEXT: v_dual_mov_b32 v58, v10 :: v_dual_mov_b32 v57, v9 +; GFX11-NEXT: v_dual_mov_b32 v56, v8 :: v_dual_mov_b32 v55, v7 +; GFX11-NEXT: v_dual_mov_b32 v54, v6 :: v_dual_mov_b32 v53, v5 +; GFX11-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v51, v3 +; GFX11-NEXT: v_dual_mov_b32 v48, v32 :: v_dual_mov_b32 v47, v31 +; GFX11-NEXT: v_dual_mov_b32 v46, v30 :: v_dual_mov_b32 v45, v29 +; GFX11-NEXT: v_dual_mov_b32 v44, v28 :: v_dual_mov_b32 v43, v27 +; GFX11-NEXT: v_dual_mov_b32 v42, v26 :: v_dual_mov_b32 v41, v25 +; GFX11-NEXT: v_dual_mov_b32 v40, v24 :: v_dual_mov_b32 v39, v23 +; GFX11-NEXT: v_dual_mov_b32 v38, v22 :: v_dual_mov_b32 v37, v21 +; GFX11-NEXT: v_dual_mov_b32 v36, v20 :: v_dual_mov_b32 v35, v19 +; GFX11-NEXT: .LBB140_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x7 +; GFX11-NEXT: global_store_b128 v[1:2], v[63:66], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[59:62], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[55:58], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[51:54], off +; GFX11-NEXT: global_store_b128 v[1:2], v[47:50], off offset:112 +; GFX11-NEXT: global_store_b128 v[1:2], v[43:46], off offset:96 +; GFX11-NEXT: global_store_b128 v[1:2], v[39:42], off offset:80 +; GFX11-NEXT: global_store_b128 v[1:2], v[35:38], off offset:64 +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64 +; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <64 x bfloat> %value to <64 x i16> + br label %end + +end: + %phi = phi <64 x i16> [zeroinitializer, %entry], [%cast, %if] + store <64 x i16> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v64bf16_to_v64f16(i32 %cond, ptr addrspace(1) %out, <64 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v64bf16_to_v64f16: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v46, v21 +; GCN-NEXT: v_mov_b32_e32 v47, v20 +; GCN-NEXT: v_mov_b32_e32 v20, v19 +; GCN-NEXT: v_mov_b32_e32 v19, v16 +; GCN-NEXT: v_mov_b32_e32 v16, v15 +; GCN-NEXT: v_mov_b32_e32 v15, v12 +; GCN-NEXT: v_mov_b32_e32 v12, v11 +; GCN-NEXT: v_mov_b32_e32 v11, v8 +; GCN-NEXT: v_mov_b32_e32 v58, v2 +; GCN-NEXT: v_mov_b32_e32 v57, v1 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:136 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:128 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:120 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:112 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:104 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:100 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:96 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:92 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:88 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:80 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:72 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:68 +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:64 +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:60 +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:56 +; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:52 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:48 +; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44 +; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:40 +; GCN-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36 +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:32 +; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:28 +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:24 +; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:20 +; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:16 +; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:12 +; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v37, 0 +; GCN-NEXT: v_mov_b32_e32 v38, 0 +; GCN-NEXT: v_mov_b32_e32 v36, 0 +; GCN-NEXT: v_mov_b32_e32 v49, 0 +; GCN-NEXT: v_mov_b32_e32 v48, 0 +; GCN-NEXT: v_mov_b32_e32 v24, 0 +; GCN-NEXT: v_mov_b32_e32 v50, 0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: v_mov_b32_e32 v51, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v28, 0 +; GCN-NEXT: v_mov_b32_e32 v52, 0 +; GCN-NEXT: v_mov_b32_e32 v53, 0 +; GCN-NEXT: v_mov_b32_e32 v22, 0 +; GCN-NEXT: v_mov_b32_e32 v32, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v54, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v39, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v34, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v41, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v30, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v63, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v60, 0 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v59, 0 +; GCN-NEXT: v_mov_b32_e32 v62, 0 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB141_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v22, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v5 +; GCN-NEXT: v_mul_f32_e32 v31, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v32, 1.0, v7 +; GCN-NEXT: v_mul_f32_e32 v34, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v9 +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v52, 1.0, v13 +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v53, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v41, 1.0, v47 +; GCN-NEXT: v_mul_f32_e32 v46, 1.0, v46 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v30, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v40 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v61 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v27 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v33 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v23 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v26 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v42 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v25 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v56 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: v_mul_f32_e32 v47, 1.0, v55 +; GCN-NEXT: v_mul_f32_e32 v55, 1.0, v35 +; GCN-NEXT: v_mul_f32_e32 v35, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v2 +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v44 +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v29 +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v45 +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v43 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v2, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v56, 1.0, v0 +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(1) +; GCN-NEXT: v_mul_f32_e32 v57, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: v_mul_f32_e32 v58, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v59, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v60, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v61, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v62, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v63, 1.0, v0 +; GCN-NEXT: v_mov_b32_e32 v0, v1 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v36, 16, v22 +; GCN-NEXT: v_lshrrev_b32_e32 v37, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v38, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v48, 16, v31 +; GCN-NEXT: v_lshrrev_b32_e32 v49, 16, v32 +; GCN-NEXT: v_lshrrev_b32_e32 v50, 16, v34 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v10 +; GCN-NEXT: v_lshrrev_b32_e32 v51, 16, v12 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v39 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v52 +; GCN-NEXT: v_lshrrev_b32_e32 v32, 16, v14 +; GCN-NEXT: v_lshrrev_b32_e32 v52, 16, v16 +; GCN-NEXT: v_lshrrev_b32_e32 v53, 16, v53 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v54 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v18 +; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v54, 16, v41 +; GCN-NEXT: v_lshrrev_b32_e32 v39, 16, v46 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v40, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v34, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v41, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v42, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v8 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v43, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v44, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v45, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v46, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v8 +; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; GCN-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v47, 16, v47 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v35, 16, v35 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_lshrrev_b32_e32 v56, 16, v56 +; GCN-NEXT: v_lshrrev_b32_e32 v57, 16, v57 +; GCN-NEXT: v_lshrrev_b32_e32 v58, 16, v58 +; GCN-NEXT: v_lshrrev_b32_e32 v59, 16, v59 +; GCN-NEXT: v_lshrrev_b32_e32 v60, 16, v60 +; GCN-NEXT: v_lshrrev_b32_e32 v61, 16, v61 +; GCN-NEXT: v_lshrrev_b32_e32 v62, 16, v62 +; GCN-NEXT: v_lshrrev_b32_e32 v63, 16, v63 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_cvt_f32_f16_e32 v36, v36 +; GCN-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v37, v37 +; GCN-NEXT: v_cvt_f32_f16_e32 v38, v38 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v36, v48 +; GCN-NEXT: v_cvt_f32_f16_e32 v49, v49 +; GCN-NEXT: v_cvt_f32_f16_e32 v48, v50 +; GCN-NEXT: v_cvt_f32_f16_e32 v24, v24 +; GCN-NEXT: v_cvt_f32_f16_e32 v50, v31 +; GCN-NEXT: v_cvt_f32_f16_e32 v31, v51 +; GCN-NEXT: v_cvt_f32_f16_e32 v51, v28 +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v25 +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v28, v32 +; GCN-NEXT: v_cvt_f32_f16_e32 v52, v52 +; GCN-NEXT: v_cvt_f32_f16_e32 v53, v53 +; GCN-NEXT: v_cvt_f32_f16_e32 v22, v22 +; GCN-NEXT: v_cvt_f32_f16_e32 v32, v26 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v33 +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v54, v54 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v39 +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v39, v40 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v34 +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v34, v41 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v42 +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v41, v29 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v30 +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v30, v43 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v44 +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v45 +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v25, v46 +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v20, v20 +; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v18, v18 +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v16, v16 +; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v14, v14 +; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v12, v12 +; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v10, v10 +; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v9 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v47 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v55 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v35 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v27 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v23 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v21 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v19 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v17 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v15 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v11 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v8, v13 +; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 +; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6 +; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 +; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4 +; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v56 +; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v57 +; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v58 +; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v59 +; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v2, v60 +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v61 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: v_cvt_f32_f16_e32 v60, v62 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f32_f16_e32 v3, v63 +; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: v_mov_b32_e32 v63, v2 +; GCN-NEXT: v_cvt_f32_f16_e32 v59, v1 +; GCN-NEXT: v_cvt_f32_f16_e32 v62, v0 +; GCN-NEXT: .LBB141_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v37 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v3, v1, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v36 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v38 +; GCN-NEXT: v_or_b32_e32 v4, v1, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v48 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v49 +; GCN-NEXT: v_or_b32_e32 v5, v1, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v50 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v24 +; GCN-NEXT: v_or_b32_e32 v6, v1, v0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[57:58], s[4:7], 0 addr64 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v51 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v31 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_or_b32_e32 v3, v1, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v28 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v4, v1, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v53 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v52 +; GCN-NEXT: v_or_b32_e32 v5, v1, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v32 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v22 +; GCN-NEXT: v_or_b32_e32 v6, v1, v0 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[57:58], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v54 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_or_b32_e32 v3, v1, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v39 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v4, v1, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v34 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v5, v1, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v41 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v6, v1, v0 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[57:58], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v30 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_or_b32_e32 v3, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v4, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v5, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v6, v1, v0 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[57:58], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_or_b32_e32 v3, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v4, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v5, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v6, v1, v0 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[57:58], s[4:7], 0 addr64 offset:64 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_or_b32_e32 v3, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v4, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v5, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v6, v1, v0 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[57:58], s[4:7], 0 addr64 offset:80 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_or_b32_e32 v3, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v4, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v5, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: v_or_b32_e32 v6, v1, v0 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[57:58], s[4:7], 0 addr64 offset:96 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: v_or_b32_e32 v3, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v63 +; GCN-NEXT: v_or_b32_e32 v4, v1, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v1, v60 +; GCN-NEXT: v_or_b32_e32 v5, v1, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v0, v62 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_cvt_f16_f32_e32 v6, v59 +; GCN-NEXT: v_or_b32_e32 v6, v6, v0 +; GCN-NEXT: buffer_store_dwordx4 v[3:6], v[57:58], s[4:7], 0 addr64 offset:112 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v64bf16_to_v64f16: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; VI-NEXT: s_mov_b32 s4, 0 +; VI-NEXT: s_mov_b32 s19, s4 +; VI-NEXT: s_mov_b32 s5, s4 +; VI-NEXT: s_mov_b32 s6, s4 +; VI-NEXT: s_mov_b32 s7, s4 +; VI-NEXT: s_mov_b32 s8, s4 +; VI-NEXT: s_mov_b32 s9, s4 +; VI-NEXT: s_mov_b32 s10, s4 +; VI-NEXT: s_mov_b32 s11, s4 +; VI-NEXT: s_mov_b32 s12, s4 +; VI-NEXT: s_mov_b32 s13, s4 +; VI-NEXT: s_mov_b32 s14, s4 +; VI-NEXT: s_mov_b32 s15, s4 +; VI-NEXT: s_mov_b32 s16, s4 +; VI-NEXT: s_mov_b32 s17, s4 +; VI-NEXT: s_mov_b32 s18, s4 +; VI-NEXT: v_mov_b32_e32 v50, s19 +; VI-NEXT: v_mov_b32_e32 v49, s18 +; VI-NEXT: v_mov_b32_e32 v48, s17 +; VI-NEXT: v_mov_b32_e32 v47, s16 +; VI-NEXT: v_mov_b32_e32 v46, s15 +; VI-NEXT: v_mov_b32_e32 v45, s14 +; VI-NEXT: v_mov_b32_e32 v44, s13 +; VI-NEXT: v_mov_b32_e32 v43, s12 +; VI-NEXT: v_mov_b32_e32 v42, s11 +; VI-NEXT: v_mov_b32_e32 v41, s10 +; VI-NEXT: v_mov_b32_e32 v40, s9 +; VI-NEXT: v_mov_b32_e32 v39, s8 +; VI-NEXT: v_mov_b32_e32 v38, s7 +; VI-NEXT: v_mov_b32_e32 v37, s6 +; VI-NEXT: v_mov_b32_e32 v36, s5 +; VI-NEXT: v_mov_b32_e32 v35, s4 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB141_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: v_mov_b32_e32 v50, v18 +; VI-NEXT: v_mov_b32_e32 v49, v17 +; VI-NEXT: v_mov_b32_e32 v48, v16 +; VI-NEXT: v_mov_b32_e32 v47, v15 +; VI-NEXT: v_mov_b32_e32 v46, v14 +; VI-NEXT: v_mov_b32_e32 v45, v13 +; VI-NEXT: v_mov_b32_e32 v44, v12 +; VI-NEXT: v_mov_b32_e32 v43, v11 +; VI-NEXT: v_mov_b32_e32 v42, v10 +; VI-NEXT: v_mov_b32_e32 v41, v9 +; VI-NEXT: v_mov_b32_e32 v40, v8 +; VI-NEXT: v_mov_b32_e32 v39, v7 +; VI-NEXT: v_mov_b32_e32 v38, v6 +; VI-NEXT: v_mov_b32_e32 v37, v5 +; VI-NEXT: v_mov_b32_e32 v36, v4 +; VI-NEXT: v_mov_b32_e32 v35, v3 +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: .LBB141_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[47:50] +; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[43:46] +; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[39:42] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[35:38] +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; VI-NEXT: s_movk_i32 s4, 0x70 +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x60 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dwordx4 v[3:4], v[17:20] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: s_movk_i32 s4, 0x50 +; VI-NEXT: flat_store_dwordx4 v[3:4], v[13:16] +; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc +; VI-NEXT: v_add_u32_e32 v0, vcc, 64, v1 +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[3:4], v[9:12] +; VI-NEXT: flat_store_dwordx4 v[0:1], v[5:8] +; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v64bf16_to_v64f16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GFX9-NEXT: s_mov_b32 s4, 0 +; GFX9-NEXT: s_mov_b32 s19, s4 +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_mov_b32 s6, s4 +; GFX9-NEXT: s_mov_b32 s7, s4 +; GFX9-NEXT: s_mov_b32 s8, s4 +; GFX9-NEXT: s_mov_b32 s9, s4 +; GFX9-NEXT: s_mov_b32 s10, s4 +; GFX9-NEXT: s_mov_b32 s11, s4 +; GFX9-NEXT: s_mov_b32 s12, s4 +; GFX9-NEXT: s_mov_b32 s13, s4 +; GFX9-NEXT: s_mov_b32 s14, s4 +; GFX9-NEXT: s_mov_b32 s15, s4 +; GFX9-NEXT: s_mov_b32 s16, s4 +; GFX9-NEXT: s_mov_b32 s17, s4 +; GFX9-NEXT: s_mov_b32 s18, s4 +; GFX9-NEXT: v_mov_b32_e32 v50, s19 +; GFX9-NEXT: v_mov_b32_e32 v49, s18 +; GFX9-NEXT: v_mov_b32_e32 v48, s17 +; GFX9-NEXT: v_mov_b32_e32 v47, s16 +; GFX9-NEXT: v_mov_b32_e32 v46, s15 +; GFX9-NEXT: v_mov_b32_e32 v45, s14 +; GFX9-NEXT: v_mov_b32_e32 v44, s13 +; GFX9-NEXT: v_mov_b32_e32 v43, s12 +; GFX9-NEXT: v_mov_b32_e32 v42, s11 +; GFX9-NEXT: v_mov_b32_e32 v41, s10 +; GFX9-NEXT: v_mov_b32_e32 v40, s9 +; GFX9-NEXT: v_mov_b32_e32 v39, s8 +; GFX9-NEXT: v_mov_b32_e32 v38, s7 +; GFX9-NEXT: v_mov_b32_e32 v37, s6 +; GFX9-NEXT: v_mov_b32_e32 v36, s5 +; GFX9-NEXT: v_mov_b32_e32 v35, s4 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB141_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: v_mov_b32_e32 v50, v18 +; GFX9-NEXT: v_mov_b32_e32 v49, v17 +; GFX9-NEXT: v_mov_b32_e32 v48, v16 +; GFX9-NEXT: v_mov_b32_e32 v47, v15 +; GFX9-NEXT: v_mov_b32_e32 v46, v14 +; GFX9-NEXT: v_mov_b32_e32 v45, v13 +; GFX9-NEXT: v_mov_b32_e32 v44, v12 +; GFX9-NEXT: v_mov_b32_e32 v43, v11 +; GFX9-NEXT: v_mov_b32_e32 v42, v10 +; GFX9-NEXT: v_mov_b32_e32 v41, v9 +; GFX9-NEXT: v_mov_b32_e32 v40, v8 +; GFX9-NEXT: v_mov_b32_e32 v39, v7 +; GFX9-NEXT: v_mov_b32_e32 v38, v6 +; GFX9-NEXT: v_mov_b32_e32 v37, v5 +; GFX9-NEXT: v_mov_b32_e32 v36, v4 +; GFX9-NEXT: v_mov_b32_e32 v35, v3 +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: s_waitcnt vmcnt(28) +; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: .LBB141_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[47:50], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[43:46], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[39:42], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[35:38], off +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:112 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off offset:96 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off offset:80 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[3:6], off offset:64 +; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v64bf16_to_v64f16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_mov_b32 s15, s0 +; GFX11-NEXT: s_mov_b32 s1, s0 +; GFX11-NEXT: s_mov_b32 s2, s0 +; GFX11-NEXT: s_mov_b32 s3, s0 +; GFX11-NEXT: s_mov_b32 s4, s0 +; GFX11-NEXT: s_mov_b32 s5, s0 +; GFX11-NEXT: s_mov_b32 s6, s0 +; GFX11-NEXT: s_mov_b32 s7, s0 +; GFX11-NEXT: s_mov_b32 s8, s0 +; GFX11-NEXT: s_mov_b32 s9, s0 +; GFX11-NEXT: s_mov_b32 s10, s0 +; GFX11-NEXT: s_mov_b32 s11, s0 +; GFX11-NEXT: s_mov_b32 s12, s0 +; GFX11-NEXT: s_mov_b32 s13, s0 +; GFX11-NEXT: s_mov_b32 s14, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v66, s15 :: v_dual_mov_b32 v65, s14 +; GFX11-NEXT: v_dual_mov_b32 v52, s1 :: v_dual_mov_b32 v51, s0 +; GFX11-NEXT: v_dual_mov_b32 v64, s13 :: v_dual_mov_b32 v63, s12 +; GFX11-NEXT: v_dual_mov_b32 v62, s11 :: v_dual_mov_b32 v61, s10 +; GFX11-NEXT: v_dual_mov_b32 v60, s9 :: v_dual_mov_b32 v59, s8 +; GFX11-NEXT: v_dual_mov_b32 v58, s7 :: v_dual_mov_b32 v57, s6 +; GFX11-NEXT: v_dual_mov_b32 v56, s5 :: v_dual_mov_b32 v55, s4 +; GFX11-NEXT: v_dual_mov_b32 v54, s3 :: v_dual_mov_b32 v53, s2 +; GFX11-NEXT: v_dual_mov_b32 v35, v51 :: v_dual_mov_b32 v36, v52 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_dual_mov_b32 v39, v55 :: v_dual_mov_b32 v40, v56 +; GFX11-NEXT: v_dual_mov_b32 v37, v53 :: v_dual_mov_b32 v38, v54 +; GFX11-NEXT: v_dual_mov_b32 v41, v57 :: v_dual_mov_b32 v42, v58 +; GFX11-NEXT: v_dual_mov_b32 v43, v59 :: v_dual_mov_b32 v44, v60 +; GFX11-NEXT: v_dual_mov_b32 v45, v61 :: v_dual_mov_b32 v46, v62 +; GFX11-NEXT: v_dual_mov_b32 v47, v63 :: v_dual_mov_b32 v48, v64 +; GFX11-NEXT: v_dual_mov_b32 v49, v65 :: v_dual_mov_b32 v50, v66 +; GFX11-NEXT: s_mov_b32 s0, exec_lo +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB141_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: v_dual_mov_b32 v66, v18 :: v_dual_mov_b32 v65, v17 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v50, v34 :: v_dual_mov_b32 v49, v33 +; GFX11-NEXT: v_dual_mov_b32 v64, v16 :: v_dual_mov_b32 v63, v15 +; GFX11-NEXT: v_dual_mov_b32 v62, v14 :: v_dual_mov_b32 v61, v13 +; GFX11-NEXT: v_dual_mov_b32 v60, v12 :: v_dual_mov_b32 v59, v11 +; GFX11-NEXT: v_dual_mov_b32 v58, v10 :: v_dual_mov_b32 v57, v9 +; GFX11-NEXT: v_dual_mov_b32 v56, v8 :: v_dual_mov_b32 v55, v7 +; GFX11-NEXT: v_dual_mov_b32 v54, v6 :: v_dual_mov_b32 v53, v5 +; GFX11-NEXT: v_dual_mov_b32 v52, v4 :: v_dual_mov_b32 v51, v3 +; GFX11-NEXT: v_dual_mov_b32 v48, v32 :: v_dual_mov_b32 v47, v31 +; GFX11-NEXT: v_dual_mov_b32 v46, v30 :: v_dual_mov_b32 v45, v29 +; GFX11-NEXT: v_dual_mov_b32 v44, v28 :: v_dual_mov_b32 v43, v27 +; GFX11-NEXT: v_dual_mov_b32 v42, v26 :: v_dual_mov_b32 v41, v25 +; GFX11-NEXT: v_dual_mov_b32 v40, v24 :: v_dual_mov_b32 v39, v23 +; GFX11-NEXT: v_dual_mov_b32 v38, v22 :: v_dual_mov_b32 v37, v21 +; GFX11-NEXT: v_dual_mov_b32 v36, v20 :: v_dual_mov_b32 v35, v19 +; GFX11-NEXT: .LBB141_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x7 +; GFX11-NEXT: global_store_b128 v[1:2], v[63:66], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[59:62], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[55:58], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[51:54], off +; GFX11-NEXT: global_store_b128 v[1:2], v[47:50], off offset:112 +; GFX11-NEXT: global_store_b128 v[1:2], v[43:46], off offset:96 +; GFX11-NEXT: global_store_b128 v[1:2], v[39:42], off offset:80 +; GFX11-NEXT: global_store_b128 v[1:2], v[35:38], off offset:64 +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64 +; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <64 x bfloat> %value to <64 x half> + br label %end + +end: + %phi = phi <64 x half> [zeroinitializer, %entry], [%cast, %if] + store <64 x half> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v64bf16_to_v128i8(i32 %cond, ptr addrspace(1) %out, <64 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v64bf16_to_v128i8: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:136 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:124 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:120 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:108 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:104 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:80 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:76 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:72 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:68 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:60 +; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:56 +; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:52 +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:48 +; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:44 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 +; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:36 +; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:32 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:28 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:24 +; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:20 +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 +; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:12 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v32, v31 +; GCN-NEXT: v_mov_b32_e32 v33, v31 +; GCN-NEXT: v_mov_b32_e32 v34, v31 +; GCN-NEXT: v_mov_b32_e32 v35, v31 +; GCN-NEXT: v_mov_b32_e32 v36, v31 +; GCN-NEXT: v_mov_b32_e32 v37, v31 +; GCN-NEXT: v_mov_b32_e32 v38, v31 +; GCN-NEXT: v_mov_b32_e32 v48, v31 +; GCN-NEXT: v_mov_b32_e32 v49, v31 +; GCN-NEXT: v_mov_b32_e32 v50, v31 +; GCN-NEXT: v_mov_b32_e32 v51, v31 +; GCN-NEXT: v_mov_b32_e32 v52, v31 +; GCN-NEXT: v_mov_b32_e32 v53, v31 +; GCN-NEXT: v_mov_b32_e32 v54, v31 +; GCN-NEXT: v_mov_b32_e32 v55, v31 +; GCN-NEXT: v_mov_b32_e32 v39, v31 +; GCN-NEXT: v_mov_b32_e32 v40, v31 +; GCN-NEXT: v_mov_b32_e32 v41, v31 +; GCN-NEXT: v_mov_b32_e32 v42, v31 +; GCN-NEXT: v_mov_b32_e32 v43, v31 +; GCN-NEXT: v_mov_b32_e32 v44, v31 +; GCN-NEXT: v_mov_b32_e32 v45, v31 +; GCN-NEXT: v_mov_b32_e32 v46, v31 +; GCN-NEXT: v_mov_b32_e32 v56, v31 +; GCN-NEXT: v_mov_b32_e32 v57, v31 +; GCN-NEXT: v_mov_b32_e32 v58, v31 +; GCN-NEXT: v_mov_b32_e32 v59, v31 +; GCN-NEXT: v_mov_b32_e32 v60, v31 +; GCN-NEXT: v_mov_b32_e32 v61, v31 +; GCN-NEXT: v_mov_b32_e32 v62, v31 +; GCN-NEXT: v_mov_b32_e32 v63, v31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB142_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v31, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v32, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_alignbit_b32 v33, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_alignbit_b32 v34, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v35, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v36, v4, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v48, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v37, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v50, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v38, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v51, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v52, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v49, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v60, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v59, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v45, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v62, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v40, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v63, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v53, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v61, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v55, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v41, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v47 +; GCN-NEXT: v_mul_f32_e32 v42, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v43, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v44, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v46, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v56, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v57, 1.0, v29 +; GCN-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v10 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v58, 1.0, v11 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v12 +; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v12 +; GCN-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v13 +; GCN-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v14 +; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v14 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v16 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v16 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v17 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v18 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v18 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v19 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v48 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v50 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v51 +; GCN-NEXT: v_lshrrev_b32_e32 v50, 16, v52 +; GCN-NEXT: v_lshrrev_b32_e32 v51, 16, v60 +; GCN-NEXT: v_lshrrev_b32_e32 v52, 16, v45 +; GCN-NEXT: v_lshrrev_b32_e32 v40, 16, v40 +; GCN-NEXT: v_lshrrev_b32_e32 v53, 16, v53 +; GCN-NEXT: v_lshrrev_b32_e32 v54, 16, v54 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v41, 16, v41 +; GCN-NEXT: v_lshrrev_b32_e32 v42, 16, v42 +; GCN-NEXT: v_lshrrev_b32_e32 v43, 16, v43 +; GCN-NEXT: v_lshrrev_b32_e32 v44, 16, v44 +; GCN-NEXT: v_lshrrev_b32_e32 v45, 16, v46 +; GCN-NEXT: v_lshrrev_b32_e32 v46, 16, v56 +; GCN-NEXT: v_lshrrev_b32_e32 v47, 16, v57 +; GCN-NEXT: v_lshrrev_b32_e32 v56, 16, v58 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_alignbit_b32 v37, v22, v37, 16 +; GCN-NEXT: v_alignbit_b32 v38, v29, v38, 16 +; GCN-NEXT: v_alignbit_b32 v48, v30, v39, 16 +; GCN-NEXT: v_alignbit_b32 v49, v50, v49, 16 +; GCN-NEXT: v_alignbit_b32 v50, v51, v59, 16 +; GCN-NEXT: v_alignbit_b32 v51, v52, v62, 16 +; GCN-NEXT: v_alignbit_b32 v52, v40, v63, 16 +; GCN-NEXT: v_alignbit_b32 v53, v53, v61, 16 +; GCN-NEXT: v_alignbit_b32 v54, v54, v0, 16 +; GCN-NEXT: v_alignbit_b32 v55, v55, v3, 16 +; GCN-NEXT: v_alignbit_b32 v39, v41, v4, 16 +; GCN-NEXT: v_alignbit_b32 v40, v42, v5, 16 +; GCN-NEXT: v_alignbit_b32 v41, v43, v6, 16 +; GCN-NEXT: v_alignbit_b32 v42, v44, v7, 16 +; GCN-NEXT: v_alignbit_b32 v43, v45, v8, 16 +; GCN-NEXT: v_alignbit_b32 v44, v46, v9, 16 +; GCN-NEXT: v_alignbit_b32 v45, v47, v10, 16 +; GCN-NEXT: v_alignbit_b32 v46, v56, v11, 16 +; GCN-NEXT: v_alignbit_b32 v56, v27, v12, 16 +; GCN-NEXT: v_alignbit_b32 v57, v26, v13, 16 +; GCN-NEXT: v_alignbit_b32 v58, v25, v14, 16 +; GCN-NEXT: v_alignbit_b32 v59, v28, v15, 16 +; GCN-NEXT: v_alignbit_b32 v60, v23, v16, 16 +; GCN-NEXT: v_alignbit_b32 v61, v24, v17, 16 +; GCN-NEXT: v_alignbit_b32 v62, v20, v18, 16 +; GCN-NEXT: v_alignbit_b32 v63, v21, v19, 16 +; GCN-NEXT: .LBB142_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[60:63], v[1:2], s[4:7], 0 addr64 offset:112 +; GCN-NEXT: buffer_store_dwordx4 v[56:59], v[1:2], s[4:7], 0 addr64 offset:96 +; GCN-NEXT: buffer_store_dwordx4 v[43:46], v[1:2], s[4:7], 0 addr64 offset:80 +; GCN-NEXT: buffer_store_dwordx4 v[39:42], v[1:2], s[4:7], 0 addr64 offset:64 +; GCN-NEXT: buffer_store_dwordx4 v[52:55], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[48:51], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[35:38], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[31:34], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(6) +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(14) +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(5) +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(4) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v64bf16_to_v128i8: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, 0 +; VI-NEXT: v_mov_b32_e32 v4, v3 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: v_mov_b32_e32 v6, v3 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: v_mov_b32_e32 v8, v3 +; VI-NEXT: v_mov_b32_e32 v9, v3 +; VI-NEXT: v_mov_b32_e32 v10, v3 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: v_mov_b32_e32 v12, v3 +; VI-NEXT: v_mov_b32_e32 v13, v3 +; VI-NEXT: v_mov_b32_e32 v14, v3 +; VI-NEXT: v_mov_b32_e32 v15, v3 +; VI-NEXT: v_mov_b32_e32 v16, v3 +; VI-NEXT: v_mov_b32_e32 v17, v3 +; VI-NEXT: v_mov_b32_e32 v18, v3 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: v_mov_b32_e32 v20, v3 +; VI-NEXT: v_mov_b32_e32 v21, v3 +; VI-NEXT: v_mov_b32_e32 v22, v3 +; VI-NEXT: v_mov_b32_e32 v23, v3 +; VI-NEXT: v_mov_b32_e32 v24, v3 +; VI-NEXT: v_mov_b32_e32 v25, v3 +; VI-NEXT: v_mov_b32_e32 v26, v3 +; VI-NEXT: v_mov_b32_e32 v27, v3 +; VI-NEXT: v_mov_b32_e32 v28, v3 +; VI-NEXT: v_mov_b32_e32 v29, v3 +; VI-NEXT: v_mov_b32_e32 v30, v3 +; VI-NEXT: v_mov_b32_e32 v31, v3 +; VI-NEXT: v_mov_b32_e32 v32, v3 +; VI-NEXT: v_mov_b32_e32 v33, v3 +; VI-NEXT: v_mov_b32_e32 v34, v3 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB142_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; VI-NEXT: .LBB142_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v35, vcc, 0x70, v1 +; VI-NEXT: v_addc_u32_e32 v36, vcc, 0, v2, vcc +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dwordx4 v[35:36], v[31:34] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v31, vcc, 0x60, v1 +; VI-NEXT: v_addc_u32_e32 v32, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[31:32], v[27:30] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v27, vcc, 0x50, v1 +; VI-NEXT: v_addc_u32_e32 v28, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[27:28], v[23:26] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v23, vcc, 64, v1 +; VI-NEXT: v_addc_u32_e32 v24, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[23:24], v[19:22] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v19, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v20, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[19:20], v[15:18] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v15, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v16, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[15:16], v[11:14] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v11, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v12, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[11:12], v[7:10] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[3:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v64bf16_to_v128i8: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GFX9-NEXT: s_waitcnt vmcnt(28) +; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v3, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, v3 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: v_mov_b32_e32 v6, v3 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: v_mov_b32_e32 v8, v3 +; GFX9-NEXT: v_mov_b32_e32 v9, v3 +; GFX9-NEXT: v_mov_b32_e32 v10, v3 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: v_mov_b32_e32 v12, v3 +; GFX9-NEXT: v_mov_b32_e32 v13, v3 +; GFX9-NEXT: v_mov_b32_e32 v14, v3 +; GFX9-NEXT: v_mov_b32_e32 v15, v3 +; GFX9-NEXT: v_mov_b32_e32 v16, v3 +; GFX9-NEXT: v_mov_b32_e32 v17, v3 +; GFX9-NEXT: v_mov_b32_e32 v18, v3 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: v_mov_b32_e32 v20, v3 +; GFX9-NEXT: v_mov_b32_e32 v21, v3 +; GFX9-NEXT: v_mov_b32_e32 v22, v3 +; GFX9-NEXT: v_mov_b32_e32 v23, v3 +; GFX9-NEXT: v_mov_b32_e32 v24, v3 +; GFX9-NEXT: v_mov_b32_e32 v25, v3 +; GFX9-NEXT: v_mov_b32_e32 v26, v3 +; GFX9-NEXT: v_mov_b32_e32 v27, v3 +; GFX9-NEXT: v_mov_b32_e32 v28, v3 +; GFX9-NEXT: v_mov_b32_e32 v29, v3 +; GFX9-NEXT: v_mov_b32_e32 v30, v3 +; GFX9-NEXT: v_mov_b32_e32 v31, v3 +; GFX9-NEXT: v_mov_b32_e32 v32, v3 +; GFX9-NEXT: v_mov_b32_e32 v33, v3 +; GFX9-NEXT: v_mov_b32_e32 v34, v3 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB142_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; GFX9-NEXT: .LBB142_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:112 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:96 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:80 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off offset:64 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[3:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v64bf16_to_v128i8: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-NEXT: v_mov_b32_e32 v35, 0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v36, v35 +; GFX11-NEXT: v_mov_b32_e32 v37, v35 +; GFX11-NEXT: v_mov_b32_e32 v38, v35 +; GFX11-NEXT: v_mov_b32_e32 v39, v35 +; GFX11-NEXT: v_mov_b32_e32 v40, v35 +; GFX11-NEXT: v_mov_b32_e32 v41, v35 +; GFX11-NEXT: v_mov_b32_e32 v42, v35 +; GFX11-NEXT: v_mov_b32_e32 v43, v35 +; GFX11-NEXT: v_mov_b32_e32 v44, v35 +; GFX11-NEXT: v_mov_b32_e32 v45, v35 +; GFX11-NEXT: v_mov_b32_e32 v46, v35 +; GFX11-NEXT: v_mov_b32_e32 v47, v35 +; GFX11-NEXT: v_mov_b32_e32 v48, v35 +; GFX11-NEXT: v_mov_b32_e32 v49, v35 +; GFX11-NEXT: v_mov_b32_e32 v50, v35 +; GFX11-NEXT: v_mov_b32_e32 v51, v35 +; GFX11-NEXT: v_mov_b32_e32 v52, v35 +; GFX11-NEXT: v_mov_b32_e32 v53, v35 +; GFX11-NEXT: v_mov_b32_e32 v54, v35 +; GFX11-NEXT: v_mov_b32_e32 v55, v35 +; GFX11-NEXT: v_mov_b32_e32 v56, v35 +; GFX11-NEXT: v_mov_b32_e32 v57, v35 +; GFX11-NEXT: v_mov_b32_e32 v58, v35 +; GFX11-NEXT: v_mov_b32_e32 v59, v35 +; GFX11-NEXT: v_mov_b32_e32 v60, v35 +; GFX11-NEXT: v_mov_b32_e32 v61, v35 +; GFX11-NEXT: v_mov_b32_e32 v62, v35 +; GFX11-NEXT: v_mov_b32_e32 v63, v35 +; GFX11-NEXT: v_mov_b32_e32 v64, v35 +; GFX11-NEXT: v_mov_b32_e32 v65, v35 +; GFX11-NEXT: v_mov_b32_e32 v66, v35 +; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-NEXT: s_cbranch_execz .LBB142_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v66, v34 :: v_dual_mov_b32 v65, v33 +; GFX11-NEXT: v_dual_mov_b32 v64, v32 :: v_dual_mov_b32 v63, v31 +; GFX11-NEXT: v_dual_mov_b32 v62, v30 :: v_dual_mov_b32 v61, v29 +; GFX11-NEXT: v_dual_mov_b32 v60, v28 :: v_dual_mov_b32 v59, v27 +; GFX11-NEXT: v_dual_mov_b32 v58, v26 :: v_dual_mov_b32 v57, v25 +; GFX11-NEXT: v_dual_mov_b32 v56, v24 :: v_dual_mov_b32 v55, v23 +; GFX11-NEXT: v_dual_mov_b32 v54, v22 :: v_dual_mov_b32 v53, v21 +; GFX11-NEXT: v_dual_mov_b32 v52, v20 :: v_dual_mov_b32 v51, v19 +; GFX11-NEXT: v_dual_mov_b32 v50, v18 :: v_dual_mov_b32 v49, v17 +; GFX11-NEXT: v_dual_mov_b32 v48, v16 :: v_dual_mov_b32 v47, v15 +; GFX11-NEXT: v_dual_mov_b32 v46, v14 :: v_dual_mov_b32 v45, v13 +; GFX11-NEXT: v_dual_mov_b32 v44, v12 :: v_dual_mov_b32 v43, v11 +; GFX11-NEXT: v_dual_mov_b32 v42, v10 :: v_dual_mov_b32 v41, v9 +; GFX11-NEXT: v_dual_mov_b32 v40, v8 :: v_dual_mov_b32 v39, v7 +; GFX11-NEXT: v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v37, v5 +; GFX11-NEXT: v_dual_mov_b32 v36, v4 :: v_dual_mov_b32 v35, v3 +; GFX11-NEXT: .LBB142_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x7 +; GFX11-NEXT: global_store_b128 v[1:2], v[63:66], off offset:112 +; GFX11-NEXT: global_store_b128 v[1:2], v[59:62], off offset:96 +; GFX11-NEXT: global_store_b128 v[1:2], v[55:58], off offset:80 +; GFX11-NEXT: global_store_b128 v[1:2], v[51:54], off offset:64 +; GFX11-NEXT: global_store_b128 v[1:2], v[47:50], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[43:46], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[39:42], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[35:38], off +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64 +; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <64 x bfloat> %value to <128 x i8> + br label %end + +end: + %phi = phi <128 x i8> [zeroinitializer, %entry], [%cast, %if] + store <128 x i8> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v64bf16_to_v16i64(i32 %cond, ptr addrspace(1) %out, <64 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v64bf16_to_v16i64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:136 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:124 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:120 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:108 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:104 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:80 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:76 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:72 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:68 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:60 +; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:56 +; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:52 +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:48 +; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:44 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 +; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:36 +; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:32 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:28 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:24 +; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:20 +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 +; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:12 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v32, v31 +; GCN-NEXT: v_mov_b32_e32 v33, v31 +; GCN-NEXT: v_mov_b32_e32 v34, v31 +; GCN-NEXT: v_mov_b32_e32 v35, v31 +; GCN-NEXT: v_mov_b32_e32 v36, v31 +; GCN-NEXT: v_mov_b32_e32 v37, v31 +; GCN-NEXT: v_mov_b32_e32 v38, v31 +; GCN-NEXT: v_mov_b32_e32 v48, v31 +; GCN-NEXT: v_mov_b32_e32 v49, v31 +; GCN-NEXT: v_mov_b32_e32 v50, v31 +; GCN-NEXT: v_mov_b32_e32 v51, v31 +; GCN-NEXT: v_mov_b32_e32 v52, v31 +; GCN-NEXT: v_mov_b32_e32 v53, v31 +; GCN-NEXT: v_mov_b32_e32 v54, v31 +; GCN-NEXT: v_mov_b32_e32 v55, v31 +; GCN-NEXT: v_mov_b32_e32 v39, v31 +; GCN-NEXT: v_mov_b32_e32 v40, v31 +; GCN-NEXT: v_mov_b32_e32 v41, v31 +; GCN-NEXT: v_mov_b32_e32 v42, v31 +; GCN-NEXT: v_mov_b32_e32 v43, v31 +; GCN-NEXT: v_mov_b32_e32 v44, v31 +; GCN-NEXT: v_mov_b32_e32 v45, v31 +; GCN-NEXT: v_mov_b32_e32 v46, v31 +; GCN-NEXT: v_mov_b32_e32 v56, v31 +; GCN-NEXT: v_mov_b32_e32 v57, v31 +; GCN-NEXT: v_mov_b32_e32 v58, v31 +; GCN-NEXT: v_mov_b32_e32 v59, v31 +; GCN-NEXT: v_mov_b32_e32 v60, v31 +; GCN-NEXT: v_mov_b32_e32 v61, v31 +; GCN-NEXT: v_mov_b32_e32 v62, v31 +; GCN-NEXT: v_mov_b32_e32 v63, v31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB143_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v31, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v32, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_alignbit_b32 v33, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_alignbit_b32 v34, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v35, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v36, v4, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v48, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v37, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v50, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v38, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v51, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v52, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v49, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v60, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v59, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v45, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v62, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v40, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v63, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v53, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v61, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v55, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v41, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v47 +; GCN-NEXT: v_mul_f32_e32 v42, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v43, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v44, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v46, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v56, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v57, 1.0, v29 +; GCN-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v10 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v58, 1.0, v11 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v12 +; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v12 +; GCN-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v13 +; GCN-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v14 +; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v14 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v16 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v16 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v17 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v18 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v18 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v19 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v48 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v50 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v51 +; GCN-NEXT: v_lshrrev_b32_e32 v50, 16, v52 +; GCN-NEXT: v_lshrrev_b32_e32 v51, 16, v60 +; GCN-NEXT: v_lshrrev_b32_e32 v52, 16, v45 +; GCN-NEXT: v_lshrrev_b32_e32 v40, 16, v40 +; GCN-NEXT: v_lshrrev_b32_e32 v53, 16, v53 +; GCN-NEXT: v_lshrrev_b32_e32 v54, 16, v54 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v41, 16, v41 +; GCN-NEXT: v_lshrrev_b32_e32 v42, 16, v42 +; GCN-NEXT: v_lshrrev_b32_e32 v43, 16, v43 +; GCN-NEXT: v_lshrrev_b32_e32 v44, 16, v44 +; GCN-NEXT: v_lshrrev_b32_e32 v45, 16, v46 +; GCN-NEXT: v_lshrrev_b32_e32 v46, 16, v56 +; GCN-NEXT: v_lshrrev_b32_e32 v47, 16, v57 +; GCN-NEXT: v_lshrrev_b32_e32 v56, 16, v58 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_alignbit_b32 v37, v22, v37, 16 +; GCN-NEXT: v_alignbit_b32 v38, v29, v38, 16 +; GCN-NEXT: v_alignbit_b32 v48, v30, v39, 16 +; GCN-NEXT: v_alignbit_b32 v49, v50, v49, 16 +; GCN-NEXT: v_alignbit_b32 v50, v51, v59, 16 +; GCN-NEXT: v_alignbit_b32 v51, v52, v62, 16 +; GCN-NEXT: v_alignbit_b32 v52, v40, v63, 16 +; GCN-NEXT: v_alignbit_b32 v53, v53, v61, 16 +; GCN-NEXT: v_alignbit_b32 v54, v54, v0, 16 +; GCN-NEXT: v_alignbit_b32 v55, v55, v3, 16 +; GCN-NEXT: v_alignbit_b32 v39, v41, v4, 16 +; GCN-NEXT: v_alignbit_b32 v40, v42, v5, 16 +; GCN-NEXT: v_alignbit_b32 v41, v43, v6, 16 +; GCN-NEXT: v_alignbit_b32 v42, v44, v7, 16 +; GCN-NEXT: v_alignbit_b32 v43, v45, v8, 16 +; GCN-NEXT: v_alignbit_b32 v44, v46, v9, 16 +; GCN-NEXT: v_alignbit_b32 v45, v47, v10, 16 +; GCN-NEXT: v_alignbit_b32 v46, v56, v11, 16 +; GCN-NEXT: v_alignbit_b32 v56, v27, v12, 16 +; GCN-NEXT: v_alignbit_b32 v57, v26, v13, 16 +; GCN-NEXT: v_alignbit_b32 v58, v25, v14, 16 +; GCN-NEXT: v_alignbit_b32 v59, v28, v15, 16 +; GCN-NEXT: v_alignbit_b32 v60, v23, v16, 16 +; GCN-NEXT: v_alignbit_b32 v61, v24, v17, 16 +; GCN-NEXT: v_alignbit_b32 v62, v20, v18, 16 +; GCN-NEXT: v_alignbit_b32 v63, v21, v19, 16 +; GCN-NEXT: .LBB143_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[60:63], v[1:2], s[4:7], 0 addr64 offset:112 +; GCN-NEXT: buffer_store_dwordx4 v[56:59], v[1:2], s[4:7], 0 addr64 offset:96 +; GCN-NEXT: buffer_store_dwordx4 v[43:46], v[1:2], s[4:7], 0 addr64 offset:80 +; GCN-NEXT: buffer_store_dwordx4 v[39:42], v[1:2], s[4:7], 0 addr64 offset:64 +; GCN-NEXT: buffer_store_dwordx4 v[52:55], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[48:51], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[35:38], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[31:34], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(6) +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(14) +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(5) +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(4) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v64bf16_to_v16i64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, 0 +; VI-NEXT: v_mov_b32_e32 v4, v3 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: v_mov_b32_e32 v6, v3 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: v_mov_b32_e32 v8, v3 +; VI-NEXT: v_mov_b32_e32 v9, v3 +; VI-NEXT: v_mov_b32_e32 v10, v3 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: v_mov_b32_e32 v12, v3 +; VI-NEXT: v_mov_b32_e32 v13, v3 +; VI-NEXT: v_mov_b32_e32 v14, v3 +; VI-NEXT: v_mov_b32_e32 v15, v3 +; VI-NEXT: v_mov_b32_e32 v16, v3 +; VI-NEXT: v_mov_b32_e32 v17, v3 +; VI-NEXT: v_mov_b32_e32 v18, v3 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: v_mov_b32_e32 v20, v3 +; VI-NEXT: v_mov_b32_e32 v21, v3 +; VI-NEXT: v_mov_b32_e32 v22, v3 +; VI-NEXT: v_mov_b32_e32 v23, v3 +; VI-NEXT: v_mov_b32_e32 v24, v3 +; VI-NEXT: v_mov_b32_e32 v25, v3 +; VI-NEXT: v_mov_b32_e32 v26, v3 +; VI-NEXT: v_mov_b32_e32 v27, v3 +; VI-NEXT: v_mov_b32_e32 v28, v3 +; VI-NEXT: v_mov_b32_e32 v29, v3 +; VI-NEXT: v_mov_b32_e32 v30, v3 +; VI-NEXT: v_mov_b32_e32 v31, v3 +; VI-NEXT: v_mov_b32_e32 v32, v3 +; VI-NEXT: v_mov_b32_e32 v33, v3 +; VI-NEXT: v_mov_b32_e32 v34, v3 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB143_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; VI-NEXT: .LBB143_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v35, vcc, 0x70, v1 +; VI-NEXT: v_addc_u32_e32 v36, vcc, 0, v2, vcc +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dwordx4 v[35:36], v[31:34] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v31, vcc, 0x60, v1 +; VI-NEXT: v_addc_u32_e32 v32, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[31:32], v[27:30] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v27, vcc, 0x50, v1 +; VI-NEXT: v_addc_u32_e32 v28, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[27:28], v[23:26] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v23, vcc, 64, v1 +; VI-NEXT: v_addc_u32_e32 v24, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[23:24], v[19:22] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v19, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v20, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[19:20], v[15:18] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v15, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v16, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[15:16], v[11:14] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v11, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v12, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[11:12], v[7:10] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[3:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v64bf16_to_v16i64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GFX9-NEXT: s_waitcnt vmcnt(28) +; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v3, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, v3 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: v_mov_b32_e32 v6, v3 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: v_mov_b32_e32 v8, v3 +; GFX9-NEXT: v_mov_b32_e32 v9, v3 +; GFX9-NEXT: v_mov_b32_e32 v10, v3 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: v_mov_b32_e32 v12, v3 +; GFX9-NEXT: v_mov_b32_e32 v13, v3 +; GFX9-NEXT: v_mov_b32_e32 v14, v3 +; GFX9-NEXT: v_mov_b32_e32 v15, v3 +; GFX9-NEXT: v_mov_b32_e32 v16, v3 +; GFX9-NEXT: v_mov_b32_e32 v17, v3 +; GFX9-NEXT: v_mov_b32_e32 v18, v3 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: v_mov_b32_e32 v20, v3 +; GFX9-NEXT: v_mov_b32_e32 v21, v3 +; GFX9-NEXT: v_mov_b32_e32 v22, v3 +; GFX9-NEXT: v_mov_b32_e32 v23, v3 +; GFX9-NEXT: v_mov_b32_e32 v24, v3 +; GFX9-NEXT: v_mov_b32_e32 v25, v3 +; GFX9-NEXT: v_mov_b32_e32 v26, v3 +; GFX9-NEXT: v_mov_b32_e32 v27, v3 +; GFX9-NEXT: v_mov_b32_e32 v28, v3 +; GFX9-NEXT: v_mov_b32_e32 v29, v3 +; GFX9-NEXT: v_mov_b32_e32 v30, v3 +; GFX9-NEXT: v_mov_b32_e32 v31, v3 +; GFX9-NEXT: v_mov_b32_e32 v32, v3 +; GFX9-NEXT: v_mov_b32_e32 v33, v3 +; GFX9-NEXT: v_mov_b32_e32 v34, v3 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB143_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; GFX9-NEXT: .LBB143_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:112 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:96 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:80 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off offset:64 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[3:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v64bf16_to_v16i64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-NEXT: v_mov_b32_e32 v35, 0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v36, v35 +; GFX11-NEXT: v_mov_b32_e32 v37, v35 +; GFX11-NEXT: v_mov_b32_e32 v38, v35 +; GFX11-NEXT: v_mov_b32_e32 v39, v35 +; GFX11-NEXT: v_mov_b32_e32 v40, v35 +; GFX11-NEXT: v_mov_b32_e32 v41, v35 +; GFX11-NEXT: v_mov_b32_e32 v42, v35 +; GFX11-NEXT: v_mov_b32_e32 v43, v35 +; GFX11-NEXT: v_mov_b32_e32 v44, v35 +; GFX11-NEXT: v_mov_b32_e32 v45, v35 +; GFX11-NEXT: v_mov_b32_e32 v46, v35 +; GFX11-NEXT: v_mov_b32_e32 v47, v35 +; GFX11-NEXT: v_mov_b32_e32 v48, v35 +; GFX11-NEXT: v_mov_b32_e32 v49, v35 +; GFX11-NEXT: v_mov_b32_e32 v50, v35 +; GFX11-NEXT: v_mov_b32_e32 v51, v35 +; GFX11-NEXT: v_mov_b32_e32 v52, v35 +; GFX11-NEXT: v_mov_b32_e32 v53, v35 +; GFX11-NEXT: v_mov_b32_e32 v54, v35 +; GFX11-NEXT: v_mov_b32_e32 v55, v35 +; GFX11-NEXT: v_mov_b32_e32 v56, v35 +; GFX11-NEXT: v_mov_b32_e32 v57, v35 +; GFX11-NEXT: v_mov_b32_e32 v58, v35 +; GFX11-NEXT: v_mov_b32_e32 v59, v35 +; GFX11-NEXT: v_mov_b32_e32 v60, v35 +; GFX11-NEXT: v_mov_b32_e32 v61, v35 +; GFX11-NEXT: v_mov_b32_e32 v62, v35 +; GFX11-NEXT: v_mov_b32_e32 v63, v35 +; GFX11-NEXT: v_mov_b32_e32 v64, v35 +; GFX11-NEXT: v_mov_b32_e32 v65, v35 +; GFX11-NEXT: v_mov_b32_e32 v66, v35 +; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-NEXT: s_cbranch_execz .LBB143_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v66, v34 :: v_dual_mov_b32 v65, v33 +; GFX11-NEXT: v_dual_mov_b32 v64, v32 :: v_dual_mov_b32 v63, v31 +; GFX11-NEXT: v_dual_mov_b32 v62, v30 :: v_dual_mov_b32 v61, v29 +; GFX11-NEXT: v_dual_mov_b32 v60, v28 :: v_dual_mov_b32 v59, v27 +; GFX11-NEXT: v_dual_mov_b32 v58, v26 :: v_dual_mov_b32 v57, v25 +; GFX11-NEXT: v_dual_mov_b32 v56, v24 :: v_dual_mov_b32 v55, v23 +; GFX11-NEXT: v_dual_mov_b32 v54, v22 :: v_dual_mov_b32 v53, v21 +; GFX11-NEXT: v_dual_mov_b32 v52, v20 :: v_dual_mov_b32 v51, v19 +; GFX11-NEXT: v_dual_mov_b32 v50, v18 :: v_dual_mov_b32 v49, v17 +; GFX11-NEXT: v_dual_mov_b32 v48, v16 :: v_dual_mov_b32 v47, v15 +; GFX11-NEXT: v_dual_mov_b32 v46, v14 :: v_dual_mov_b32 v45, v13 +; GFX11-NEXT: v_dual_mov_b32 v44, v12 :: v_dual_mov_b32 v43, v11 +; GFX11-NEXT: v_dual_mov_b32 v42, v10 :: v_dual_mov_b32 v41, v9 +; GFX11-NEXT: v_dual_mov_b32 v40, v8 :: v_dual_mov_b32 v39, v7 +; GFX11-NEXT: v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v37, v5 +; GFX11-NEXT: v_dual_mov_b32 v36, v4 :: v_dual_mov_b32 v35, v3 +; GFX11-NEXT: .LBB143_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x7 +; GFX11-NEXT: global_store_b128 v[1:2], v[63:66], off offset:112 +; GFX11-NEXT: global_store_b128 v[1:2], v[59:62], off offset:96 +; GFX11-NEXT: global_store_b128 v[1:2], v[55:58], off offset:80 +; GFX11-NEXT: global_store_b128 v[1:2], v[51:54], off offset:64 +; GFX11-NEXT: global_store_b128 v[1:2], v[47:50], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[43:46], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[39:42], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[35:38], off +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64 +; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <64 x bfloat> %value to <16 x i64> + br label %end + +end: + %phi = phi <16 x i64> [zeroinitializer, %entry], [%cast, %if] + store <16 x i64> %phi, ptr addrspace(1) %out + ret void +} + + +define void @v_bitcast_v64bf16_to_v16f64(i32 %cond, ptr addrspace(1) %out, <64 x bfloat> %value) { +; GCN-LABEL: v_bitcast_v64bf16_to_v16f64: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:136 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:132 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:124 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:120 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:108 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:104 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:96 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:88 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:80 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:76 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:72 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:68 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:60 +; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:56 +; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:52 +; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:48 +; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:44 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40 +; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:36 +; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:32 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:28 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:24 +; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:20 +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:16 +; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:12 +; GCN-NEXT: s_waitcnt expcnt(0) +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:8 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:4 +; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s32 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_mov_b32_e32 v31, 0 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_mov_b32_e32 v32, v31 +; GCN-NEXT: v_mov_b32_e32 v33, v31 +; GCN-NEXT: v_mov_b32_e32 v34, v31 +; GCN-NEXT: v_mov_b32_e32 v35, v31 +; GCN-NEXT: v_mov_b32_e32 v36, v31 +; GCN-NEXT: v_mov_b32_e32 v37, v31 +; GCN-NEXT: v_mov_b32_e32 v38, v31 +; GCN-NEXT: v_mov_b32_e32 v48, v31 +; GCN-NEXT: v_mov_b32_e32 v49, v31 +; GCN-NEXT: v_mov_b32_e32 v50, v31 +; GCN-NEXT: v_mov_b32_e32 v51, v31 +; GCN-NEXT: v_mov_b32_e32 v52, v31 +; GCN-NEXT: v_mov_b32_e32 v53, v31 +; GCN-NEXT: v_mov_b32_e32 v54, v31 +; GCN-NEXT: v_mov_b32_e32 v55, v31 +; GCN-NEXT: v_mov_b32_e32 v39, v31 +; GCN-NEXT: v_mov_b32_e32 v40, v31 +; GCN-NEXT: v_mov_b32_e32 v41, v31 +; GCN-NEXT: v_mov_b32_e32 v42, v31 +; GCN-NEXT: v_mov_b32_e32 v43, v31 +; GCN-NEXT: v_mov_b32_e32 v44, v31 +; GCN-NEXT: v_mov_b32_e32 v45, v31 +; GCN-NEXT: v_mov_b32_e32 v46, v31 +; GCN-NEXT: v_mov_b32_e32 v56, v31 +; GCN-NEXT: v_mov_b32_e32 v57, v31 +; GCN-NEXT: v_mov_b32_e32 v58, v31 +; GCN-NEXT: v_mov_b32_e32 v59, v31 +; GCN-NEXT: v_mov_b32_e32 v60, v31 +; GCN-NEXT: v_mov_b32_e32 v61, v31 +; GCN-NEXT: v_mov_b32_e32 v62, v31 +; GCN-NEXT: v_mov_b32_e32 v63, v31 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_cbranch_execz .LBB144_2 +; GCN-NEXT: ; %bb.1: ; %if +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v4 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v6 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v5 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v31, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v32, v4, v5, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v8 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v7 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_alignbit_b32 v33, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v10 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v9 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_alignbit_b32 v34, v0, v3, 16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v12 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v11 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v14 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v13 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_alignbit_b32 v35, v0, v3, 16 +; GCN-NEXT: v_alignbit_b32 v36, v4, v5, 16 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v48, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v37, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v50, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v38, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v51, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v39, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v52, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v49, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v60, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v59, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v45, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v62, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v40, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v63, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v53, 1.0, v0 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v61, 1.0, v0 +; GCN-NEXT: v_mul_f32_e32 v54, 1.0, v16 +; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v28 +; GCN-NEXT: v_mul_f32_e32 v55, 1.0, v24 +; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v15 +; GCN-NEXT: v_mul_f32_e32 v41, 1.0, v23 +; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v47 +; GCN-NEXT: v_mul_f32_e32 v42, 1.0, v18 +; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v17 +; GCN-NEXT: v_mul_f32_e32 v43, 1.0, v27 +; GCN-NEXT: v_mul_f32_e32 v6, 1.0, v26 +; GCN-NEXT: v_mul_f32_e32 v44, 1.0, v20 +; GCN-NEXT: v_mul_f32_e32 v7, 1.0, v19 +; GCN-NEXT: v_mul_f32_e32 v46, 1.0, v25 +; GCN-NEXT: v_mul_f32_e32 v8, 1.0, v30 +; GCN-NEXT: v_mul_f32_e32 v56, 1.0, v22 +; GCN-NEXT: v_mul_f32_e32 v9, 1.0, v21 +; GCN-NEXT: v_mul_f32_e32 v57, 1.0, v29 +; GCN-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v10, 1.0, v10 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v58, 1.0, v11 +; GCN-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v11, 1.0, v11 +; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v27, 1.0, v12 +; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v12, 1.0, v12 +; GCN-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v26, 1.0, v13 +; GCN-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v13, 1.0, v13 +; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v25, 1.0, v14 +; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v14, 1.0, v14 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v28, 1.0, v15 +; GCN-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v15, 1.0, v15 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v23, 1.0, v16 +; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v16, 1.0, v16 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v24, 1.0, v17 +; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v17, 1.0, v17 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v20, 1.0, v18 +; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v18, 1.0, v18 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v21, 1.0, v19 +; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_f32_e32 v19, 1.0, v19 +; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v48 +; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v50 +; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v51 +; GCN-NEXT: v_lshrrev_b32_e32 v50, 16, v52 +; GCN-NEXT: v_lshrrev_b32_e32 v51, 16, v60 +; GCN-NEXT: v_lshrrev_b32_e32 v52, 16, v45 +; GCN-NEXT: v_lshrrev_b32_e32 v40, 16, v40 +; GCN-NEXT: v_lshrrev_b32_e32 v53, 16, v53 +; GCN-NEXT: v_lshrrev_b32_e32 v54, 16, v54 +; GCN-NEXT: v_lshrrev_b32_e32 v55, 16, v55 +; GCN-NEXT: v_lshrrev_b32_e32 v41, 16, v41 +; GCN-NEXT: v_lshrrev_b32_e32 v42, 16, v42 +; GCN-NEXT: v_lshrrev_b32_e32 v43, 16, v43 +; GCN-NEXT: v_lshrrev_b32_e32 v44, 16, v44 +; GCN-NEXT: v_lshrrev_b32_e32 v45, 16, v46 +; GCN-NEXT: v_lshrrev_b32_e32 v46, 16, v56 +; GCN-NEXT: v_lshrrev_b32_e32 v47, 16, v57 +; GCN-NEXT: v_lshrrev_b32_e32 v56, 16, v58 +; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GCN-NEXT: v_alignbit_b32 v37, v22, v37, 16 +; GCN-NEXT: v_alignbit_b32 v38, v29, v38, 16 +; GCN-NEXT: v_alignbit_b32 v48, v30, v39, 16 +; GCN-NEXT: v_alignbit_b32 v49, v50, v49, 16 +; GCN-NEXT: v_alignbit_b32 v50, v51, v59, 16 +; GCN-NEXT: v_alignbit_b32 v51, v52, v62, 16 +; GCN-NEXT: v_alignbit_b32 v52, v40, v63, 16 +; GCN-NEXT: v_alignbit_b32 v53, v53, v61, 16 +; GCN-NEXT: v_alignbit_b32 v54, v54, v0, 16 +; GCN-NEXT: v_alignbit_b32 v55, v55, v3, 16 +; GCN-NEXT: v_alignbit_b32 v39, v41, v4, 16 +; GCN-NEXT: v_alignbit_b32 v40, v42, v5, 16 +; GCN-NEXT: v_alignbit_b32 v41, v43, v6, 16 +; GCN-NEXT: v_alignbit_b32 v42, v44, v7, 16 +; GCN-NEXT: v_alignbit_b32 v43, v45, v8, 16 +; GCN-NEXT: v_alignbit_b32 v44, v46, v9, 16 +; GCN-NEXT: v_alignbit_b32 v45, v47, v10, 16 +; GCN-NEXT: v_alignbit_b32 v46, v56, v11, 16 +; GCN-NEXT: v_alignbit_b32 v56, v27, v12, 16 +; GCN-NEXT: v_alignbit_b32 v57, v26, v13, 16 +; GCN-NEXT: v_alignbit_b32 v58, v25, v14, 16 +; GCN-NEXT: v_alignbit_b32 v59, v28, v15, 16 +; GCN-NEXT: v_alignbit_b32 v60, v23, v16, 16 +; GCN-NEXT: v_alignbit_b32 v61, v24, v17, 16 +; GCN-NEXT: v_alignbit_b32 v62, v20, v18, 16 +; GCN-NEXT: v_alignbit_b32 v63, v21, v19, 16 +; GCN-NEXT: .LBB144_2: ; %end +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s6 +; GCN-NEXT: buffer_store_dwordx4 v[60:63], v[1:2], s[4:7], 0 addr64 offset:112 +; GCN-NEXT: buffer_store_dwordx4 v[56:59], v[1:2], s[4:7], 0 addr64 offset:96 +; GCN-NEXT: buffer_store_dwordx4 v[43:46], v[1:2], s[4:7], 0 addr64 offset:80 +; GCN-NEXT: buffer_store_dwordx4 v[39:42], v[1:2], s[4:7], 0 addr64 offset:64 +; GCN-NEXT: buffer_store_dwordx4 v[52:55], v[1:2], s[4:7], 0 addr64 offset:48 +; GCN-NEXT: buffer_store_dwordx4 v[48:51], v[1:2], s[4:7], 0 addr64 offset:32 +; GCN-NEXT: buffer_store_dwordx4 v[35:38], v[1:2], s[4:7], 0 addr64 offset:16 +; GCN-NEXT: buffer_store_dwordx4 v[31:34], v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(6) +; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(14) +; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(5) +; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt expcnt(4) +; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_bitcast_v64bf16_to_v16f64: +; VI: ; %bb.0: ; %entry +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(14) +; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, 0 +; VI-NEXT: v_mov_b32_e32 v4, v3 +; VI-NEXT: v_mov_b32_e32 v5, v3 +; VI-NEXT: v_mov_b32_e32 v6, v3 +; VI-NEXT: v_mov_b32_e32 v7, v3 +; VI-NEXT: v_mov_b32_e32 v8, v3 +; VI-NEXT: v_mov_b32_e32 v9, v3 +; VI-NEXT: v_mov_b32_e32 v10, v3 +; VI-NEXT: v_mov_b32_e32 v11, v3 +; VI-NEXT: v_mov_b32_e32 v12, v3 +; VI-NEXT: v_mov_b32_e32 v13, v3 +; VI-NEXT: v_mov_b32_e32 v14, v3 +; VI-NEXT: v_mov_b32_e32 v15, v3 +; VI-NEXT: v_mov_b32_e32 v16, v3 +; VI-NEXT: v_mov_b32_e32 v17, v3 +; VI-NEXT: v_mov_b32_e32 v18, v3 +; VI-NEXT: v_mov_b32_e32 v19, v3 +; VI-NEXT: v_mov_b32_e32 v20, v3 +; VI-NEXT: v_mov_b32_e32 v21, v3 +; VI-NEXT: v_mov_b32_e32 v22, v3 +; VI-NEXT: v_mov_b32_e32 v23, v3 +; VI-NEXT: v_mov_b32_e32 v24, v3 +; VI-NEXT: v_mov_b32_e32 v25, v3 +; VI-NEXT: v_mov_b32_e32 v26, v3 +; VI-NEXT: v_mov_b32_e32 v27, v3 +; VI-NEXT: v_mov_b32_e32 v28, v3 +; VI-NEXT: v_mov_b32_e32 v29, v3 +; VI-NEXT: v_mov_b32_e32 v30, v3 +; VI-NEXT: v_mov_b32_e32 v31, v3 +; VI-NEXT: v_mov_b32_e32 v32, v3 +; VI-NEXT: v_mov_b32_e32 v33, v3 +; VI-NEXT: v_mov_b32_e32 v34, v3 +; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc +; VI-NEXT: s_cbranch_execz .LBB144_2 +; VI-NEXT: ; %bb.1: ; %if +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; VI-NEXT: .LBB144_2: ; %end +; VI-NEXT: s_or_b64 exec, exec, s[4:5] +; VI-NEXT: v_add_u32_e32 v35, vcc, 0x70, v1 +; VI-NEXT: v_addc_u32_e32 v36, vcc, 0, v2, vcc +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dwordx4 v[35:36], v[31:34] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v31, vcc, 0x60, v1 +; VI-NEXT: v_addc_u32_e32 v32, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[31:32], v[27:30] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v27, vcc, 0x50, v1 +; VI-NEXT: v_addc_u32_e32 v28, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[27:28], v[23:26] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v23, vcc, 64, v1 +; VI-NEXT: v_addc_u32_e32 v24, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[23:24], v[19:22] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v19, vcc, 48, v1 +; VI-NEXT: v_addc_u32_e32 v20, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[19:20], v[15:18] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v15, vcc, 32, v1 +; VI-NEXT: v_addc_u32_e32 v16, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[15:16], v[11:14] +; VI-NEXT: s_nop 0 +; VI-NEXT: v_add_u32_e32 v11, vcc, 16, v1 +; VI-NEXT: v_addc_u32_e32 v12, vcc, 0, v2, vcc +; VI-NEXT: flat_store_dwordx4 v[11:12], v[7:10] +; VI-NEXT: flat_store_dwordx4 v[1:2], v[3:6] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_bitcast_v64bf16_to_v16f64: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GFX9-NEXT: s_waitcnt vmcnt(28) +; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v3, 0 +; GFX9-NEXT: v_mov_b32_e32 v4, v3 +; GFX9-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-NEXT: v_mov_b32_e32 v6, v3 +; GFX9-NEXT: v_mov_b32_e32 v7, v3 +; GFX9-NEXT: v_mov_b32_e32 v8, v3 +; GFX9-NEXT: v_mov_b32_e32 v9, v3 +; GFX9-NEXT: v_mov_b32_e32 v10, v3 +; GFX9-NEXT: v_mov_b32_e32 v11, v3 +; GFX9-NEXT: v_mov_b32_e32 v12, v3 +; GFX9-NEXT: v_mov_b32_e32 v13, v3 +; GFX9-NEXT: v_mov_b32_e32 v14, v3 +; GFX9-NEXT: v_mov_b32_e32 v15, v3 +; GFX9-NEXT: v_mov_b32_e32 v16, v3 +; GFX9-NEXT: v_mov_b32_e32 v17, v3 +; GFX9-NEXT: v_mov_b32_e32 v18, v3 +; GFX9-NEXT: v_mov_b32_e32 v19, v3 +; GFX9-NEXT: v_mov_b32_e32 v20, v3 +; GFX9-NEXT: v_mov_b32_e32 v21, v3 +; GFX9-NEXT: v_mov_b32_e32 v22, v3 +; GFX9-NEXT: v_mov_b32_e32 v23, v3 +; GFX9-NEXT: v_mov_b32_e32 v24, v3 +; GFX9-NEXT: v_mov_b32_e32 v25, v3 +; GFX9-NEXT: v_mov_b32_e32 v26, v3 +; GFX9-NEXT: v_mov_b32_e32 v27, v3 +; GFX9-NEXT: v_mov_b32_e32 v28, v3 +; GFX9-NEXT: v_mov_b32_e32 v29, v3 +; GFX9-NEXT: v_mov_b32_e32 v30, v3 +; GFX9-NEXT: v_mov_b32_e32 v31, v3 +; GFX9-NEXT: v_mov_b32_e32 v32, v3 +; GFX9-NEXT: v_mov_b32_e32 v33, v3 +; GFX9-NEXT: v_mov_b32_e32 v34, v3 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB144_2 +; GFX9-NEXT: ; %bb.1: ; %if +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; GFX9-NEXT: .LBB144_2: ; %end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[31:34], off offset:112 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[27:30], off offset:96 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[23:26], off offset:80 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[19:22], off offset:64 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[15:18], off offset:48 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[11:14], off offset:32 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[7:10], off offset:16 +; GFX9-NEXT: global_store_dwordx4 v[1:2], v[3:6], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_bitcast_v64bf16_to_v16f64: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 +; GFX11-NEXT: ; meta instruction +; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 +; GFX11-NEXT: s_clause 0x3 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v31, off, s32 +; GFX11-NEXT: v_mov_b32_e32 v35, 0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v36, v35 +; GFX11-NEXT: v_mov_b32_e32 v37, v35 +; GFX11-NEXT: v_mov_b32_e32 v38, v35 +; GFX11-NEXT: v_mov_b32_e32 v39, v35 +; GFX11-NEXT: v_mov_b32_e32 v40, v35 +; GFX11-NEXT: v_mov_b32_e32 v41, v35 +; GFX11-NEXT: v_mov_b32_e32 v42, v35 +; GFX11-NEXT: v_mov_b32_e32 v43, v35 +; GFX11-NEXT: v_mov_b32_e32 v44, v35 +; GFX11-NEXT: v_mov_b32_e32 v45, v35 +; GFX11-NEXT: v_mov_b32_e32 v46, v35 +; GFX11-NEXT: v_mov_b32_e32 v47, v35 +; GFX11-NEXT: v_mov_b32_e32 v48, v35 +; GFX11-NEXT: v_mov_b32_e32 v49, v35 +; GFX11-NEXT: v_mov_b32_e32 v50, v35 +; GFX11-NEXT: v_mov_b32_e32 v51, v35 +; GFX11-NEXT: v_mov_b32_e32 v52, v35 +; GFX11-NEXT: v_mov_b32_e32 v53, v35 +; GFX11-NEXT: v_mov_b32_e32 v54, v35 +; GFX11-NEXT: v_mov_b32_e32 v55, v35 +; GFX11-NEXT: v_mov_b32_e32 v56, v35 +; GFX11-NEXT: v_mov_b32_e32 v57, v35 +; GFX11-NEXT: v_mov_b32_e32 v58, v35 +; GFX11-NEXT: v_mov_b32_e32 v59, v35 +; GFX11-NEXT: v_mov_b32_e32 v60, v35 +; GFX11-NEXT: v_mov_b32_e32 v61, v35 +; GFX11-NEXT: v_mov_b32_e32 v62, v35 +; GFX11-NEXT: v_mov_b32_e32 v63, v35 +; GFX11-NEXT: v_mov_b32_e32 v64, v35 +; GFX11-NEXT: v_mov_b32_e32 v65, v35 +; GFX11-NEXT: v_mov_b32_e32 v66, v35 +; GFX11-NEXT: s_and_saveexec_b32 s0, vcc_lo +; GFX11-NEXT: s_cbranch_execz .LBB144_2 +; GFX11-NEXT: ; %bb.1: ; %if +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v66, v34 :: v_dual_mov_b32 v65, v33 +; GFX11-NEXT: v_dual_mov_b32 v64, v32 :: v_dual_mov_b32 v63, v31 +; GFX11-NEXT: v_dual_mov_b32 v62, v30 :: v_dual_mov_b32 v61, v29 +; GFX11-NEXT: v_dual_mov_b32 v60, v28 :: v_dual_mov_b32 v59, v27 +; GFX11-NEXT: v_dual_mov_b32 v58, v26 :: v_dual_mov_b32 v57, v25 +; GFX11-NEXT: v_dual_mov_b32 v56, v24 :: v_dual_mov_b32 v55, v23 +; GFX11-NEXT: v_dual_mov_b32 v54, v22 :: v_dual_mov_b32 v53, v21 +; GFX11-NEXT: v_dual_mov_b32 v52, v20 :: v_dual_mov_b32 v51, v19 +; GFX11-NEXT: v_dual_mov_b32 v50, v18 :: v_dual_mov_b32 v49, v17 +; GFX11-NEXT: v_dual_mov_b32 v48, v16 :: v_dual_mov_b32 v47, v15 +; GFX11-NEXT: v_dual_mov_b32 v46, v14 :: v_dual_mov_b32 v45, v13 +; GFX11-NEXT: v_dual_mov_b32 v44, v12 :: v_dual_mov_b32 v43, v11 +; GFX11-NEXT: v_dual_mov_b32 v42, v10 :: v_dual_mov_b32 v41, v9 +; GFX11-NEXT: v_dual_mov_b32 v40, v8 :: v_dual_mov_b32 v39, v7 +; GFX11-NEXT: v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v37, v5 +; GFX11-NEXT: v_dual_mov_b32 v36, v4 :: v_dual_mov_b32 v35, v3 +; GFX11-NEXT: .LBB144_2: ; %end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_clause 0x7 +; GFX11-NEXT: global_store_b128 v[1:2], v[63:66], off offset:112 +; GFX11-NEXT: global_store_b128 v[1:2], v[59:62], off offset:96 +; GFX11-NEXT: global_store_b128 v[1:2], v[55:58], off offset:80 +; GFX11-NEXT: global_store_b128 v[1:2], v[51:54], off offset:64 +; GFX11-NEXT: global_store_b128 v[1:2], v[47:50], off offset:48 +; GFX11-NEXT: global_store_b128 v[1:2], v[43:46], off offset:32 +; GFX11-NEXT: global_store_b128 v[1:2], v[39:42], off offset:16 +; GFX11-NEXT: global_store_b128 v[1:2], v[35:38], off +; GFX11-NEXT: s_clause 0xf +; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16 +; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20 +; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24 +; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28 +; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32 +; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36 +; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40 +; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44 +; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48 +; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52 +; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56 +; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60 +; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64 +; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 +; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 +; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <64 x bfloat> %value to <16 x double> + br label %end + +end: + %phi = phi <16 x double> [zeroinitializer, %entry], [%cast, %if] + store <16 x double> %phi, ptr addrspace(1) %out + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll index f730199e474f3..f3ad3145fd85f 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll @@ -318,19 +318,7 @@ define amdgpu_kernel void @indirect_calls_none_agpr(i1 %cond) { ; CHECK-LABEL: define amdgpu_kernel void @indirect_calls_none_agpr( ; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @empty, ptr @also_empty -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @also_empty -; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] -; CHECK: 2: -; CHECK-NEXT: call void @also_empty() -; CHECK-NEXT: br label [[TMP6:%.*]] -; CHECK: 3: -; CHECK-NEXT: br i1 true, label [[TMP4:%.*]], label [[TMP5:%.*]] -; CHECK: 4: -; CHECK-NEXT: call void @empty() -; CHECK-NEXT: br label [[TMP6]] -; CHECK: 5: -; CHECK-NEXT: unreachable -; CHECK: 6: +; CHECK-NEXT: call void [[FPTR]]() ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; @@ -961,19 +949,7 @@ define amdgpu_kernel void @knowable_indirect_call(i1 %cond) { ; CHECK-LABEL: define amdgpu_kernel void @knowable_indirect_call( ; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR22]] { ; CHECK-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @indirect_0, ptr @indirect_1 -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @indirect_1 -; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] -; CHECK: 2: -; CHECK-NEXT: call void @indirect_1() -; CHECK-NEXT: br label [[TMP6:%.*]] -; CHECK: 3: -; CHECK-NEXT: br i1 true, label [[TMP4:%.*]], label [[TMP5:%.*]] -; CHECK: 4: -; CHECK-NEXT: call void @indirect_0() -; CHECK-NEXT: br label [[TMP6]] -; CHECK: 5: -; CHECK-NEXT: unreachable -; CHECK: 6: +; CHECK-NEXT: call void [[FPTR]]() ; CHECK-NEXT: call void @use_most() ; CHECK-NEXT: ret void ; diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll index 2889f37a65d97..7f6bb85827d31 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll @@ -33,19 +33,21 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_simple_call(<4 x i32> inreg %sgpr, ; GISEL-GFX11-LABEL: amdgpu_cs_chain_simple_call: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX11-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GISEL-GFX11-NEXT: s_mov_b32 s4, use@abs32@lo ; GISEL-GFX11-NEXT: s_mov_b32 s5, use@abs32@hi -; GISEL-GFX11-NEXT: s_mov_b32 s32, 0 +; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GISEL-GFX11-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GISEL-GFX11-NEXT: s_endpgm ; ; GISEL-GFX10-LABEL: amdgpu_cs_chain_simple_call: ; GISEL-GFX10: ; %bb.0: ; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v4, v8 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v5, v9 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v6, v10 @@ -58,26 +60,27 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_simple_call(<4 x i32> inreg %sgpr, ; GISEL-GFX10-NEXT: s_mov_b32 s4, use@abs32@lo ; GISEL-GFX10-NEXT: s_mov_b32 s5, use@abs32@hi ; GISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51] -; GISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GISEL-GFX10-NEXT: s_endpgm ; ; DAGISEL-GFX11-LABEL: amdgpu_cs_chain_simple_call: ; DAGISEL-GFX11: ; %bb.0: ; DAGISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v7, v11 :: v_dual_mov_b32 v6, v10 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v4, v8 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; DAGISEL-GFX11-NEXT: s_mov_b32 s5, use@abs32@hi ; DAGISEL-GFX11-NEXT: s_mov_b32 s4, use@abs32@lo -; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 0 +; DAGISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; DAGISEL-GFX11-NEXT: s_swappc_b64 s[30:31], s[4:5] ; DAGISEL-GFX11-NEXT: s_endpgm ; ; DAGISEL-GFX10-LABEL: amdgpu_cs_chain_simple_call: ; DAGISEL-GFX10: ; %bb.0: ; DAGISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; DAGISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v7, v11 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v6, v10 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v5, v9 @@ -90,7 +93,6 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_simple_call(<4 x i32> inreg %sgpr, ; DAGISEL-GFX10-NEXT: s_mov_b32 s5, use@abs32@hi ; DAGISEL-GFX10-NEXT: s_mov_b32 s4, use@abs32@lo ; DAGISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51] -; DAGISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; DAGISEL-GFX10-NEXT: s_endpgm call amdgpu_gfx void @use(<4 x i32> %sgpr, <4 x i32> %vgpr) @@ -102,7 +104,7 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-GFX11-NEXT: s_mov_b32 s32, 0 -; GISEL-GFX11-NEXT: v_dual_mov_b32 v32, v8 :: v_dual_mov_b32 v33, v9 +; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GISEL-GFX11-NEXT: s_add_u32 s24, s32, 4 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v16, s32 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v17, s24 @@ -123,6 +125,7 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v24, s24 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v25, s25 ; GISEL-GFX11-NEXT: s_add_u32 s24, s32, 40 +; GISEL-GFX11-NEXT: v_dual_mov_b32 v32, v8 :: v_dual_mov_b32 v33, v9 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v34, v10 :: v_dual_mov_b32 v35, v11 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v36, v12 :: v_dual_mov_b32 v37, v13 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v39, v15 @@ -162,6 +165,7 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; GISEL-GFX10-LABEL: amdgpu_cs_chain_spill: ; GISEL-GFX10: ; %bb.0: ; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v32, v8 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v33, v9 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v34, v10 @@ -170,7 +174,6 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v37, v13 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v38, v14 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v39, v15 -; GISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX10-NEXT: buffer_store_dword v16, off, s[48:51], s32 ; GISEL-GFX10-NEXT: buffer_store_dword v17, off, s[48:51], s32 offset:4 ; GISEL-GFX10-NEXT: buffer_store_dword v18, off, s[48:51], s32 offset:8 @@ -230,7 +233,7 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; DAGISEL-GFX11: ; %bb.0: ; DAGISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 0 -; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v32, v15 :: v_dual_mov_b32 v33, v14 +; DAGISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; DAGISEL-GFX11-NEXT: s_add_i32 s24, s32, 60 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v16, s32 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v31, s24 @@ -251,6 +254,7 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v24, s24 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v23, s25 ; DAGISEL-GFX11-NEXT: s_add_i32 s24, s32, 24 +; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v32, v15 :: v_dual_mov_b32 v33, v14 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v34, v13 :: v_dual_mov_b32 v35, v12 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v36, v11 :: v_dual_mov_b32 v37, v10 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v38, v9 :: v_dual_mov_b32 v39, v8 @@ -290,6 +294,7 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; DAGISEL-GFX10-LABEL: amdgpu_cs_chain_spill: ; DAGISEL-GFX10: ; %bb.0: ; DAGISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; DAGISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v32, v15 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v33, v14 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v34, v13 @@ -298,7 +303,6 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v37, v10 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v38, v9 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v39, v8 -; DAGISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX10-NEXT: buffer_store_dword v16, off, s[48:51], s32 ; DAGISEL-GFX10-NEXT: buffer_store_dword v17, off, s[48:51], s32 offset:4 ; DAGISEL-GFX10-NEXT: buffer_store_dword v18, off, s[48:51], s32 offset:8 @@ -361,10 +365,10 @@ define amdgpu_cs_chain void @alloca_and_call() { ; GISEL-GFX11-LABEL: alloca_and_call: ; GISEL-GFX11: ; %bb.0: ; %.entry ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX11-NEXT: s_mov_b32 s32, 16 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 42 ; GISEL-GFX11-NEXT: s_mov_b32 s0, use@abs32@lo ; GISEL-GFX11-NEXT: s_mov_b32 s1, use@abs32@hi -; GISEL-GFX11-NEXT: s_mov_b32 s32, 16 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v0, off ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GISEL-GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -373,6 +377,7 @@ define amdgpu_cs_chain void @alloca_and_call() { ; GISEL-GFX10-LABEL: alloca_and_call: ; GISEL-GFX10: ; %bb.0: ; %.entry ; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX10-NEXT: s_movk_i32 s32, 0x200 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 42 ; GISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49] ; GISEL-GFX10-NEXT: s_mov_b32 s4, use@abs32@lo @@ -380,17 +385,16 @@ define amdgpu_cs_chain void @alloca_and_call() { ; GISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51] ; GISEL-GFX10-NEXT: buffer_store_dword v0, off, s[48:51], 0 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0 -; GISEL-GFX10-NEXT: s_movk_i32 s32, 0x200 ; GISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GISEL-GFX10-NEXT: s_endpgm ; ; DAGISEL-GFX11-LABEL: alloca_and_call: ; DAGISEL-GFX11: ; %bb.0: ; %.entry ; DAGISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 16 ; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v0, 42 ; DAGISEL-GFX11-NEXT: s_mov_b32 s1, use@abs32@hi ; DAGISEL-GFX11-NEXT: s_mov_b32 s0, use@abs32@lo -; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 16 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v0, off ; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0 ; DAGISEL-GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -399,6 +403,7 @@ define amdgpu_cs_chain void @alloca_and_call() { ; DAGISEL-GFX10-LABEL: alloca_and_call: ; DAGISEL-GFX10: ; %bb.0: ; %.entry ; DAGISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; DAGISEL-GFX10-NEXT: s_movk_i32 s32, 0x200 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v0, 42 ; DAGISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49] ; DAGISEL-GFX10-NEXT: s_mov_b32 s5, use@abs32@hi @@ -406,7 +411,6 @@ define amdgpu_cs_chain void @alloca_and_call() { ; DAGISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51] ; DAGISEL-GFX10-NEXT: buffer_store_dword v0, off, s[48:51], 0 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0 -; DAGISEL-GFX10-NEXT: s_movk_i32 s32, 0x200 ; DAGISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; DAGISEL-GFX10-NEXT: s_endpgm .entry: diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll index 36e2db0c4879d..a4882f1119e70 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll @@ -420,6 +420,7 @@ define amdgpu_cs_chain_preserve void @chain_preserve_to_chain_use_all_v0_v7(<3 x ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-GFX11-NEXT: s_clause 0x1 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v11, off offset:4 +; GISEL-GFX11-NEXT: ; meta instruction ; GISEL-GFX11-NEXT: scratch_store_b32 off, v16, off ; GISEL-GFX11-NEXT: v_mov_b32_e32 v11, v8 ; GISEL-GFX11-NEXT: s_mov_b32 s3, s0 @@ -461,6 +462,7 @@ define amdgpu_cs_chain_preserve void @chain_preserve_to_chain_use_all_v0_v7(<3 x ; DAGISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; DAGISEL-GFX11-NEXT: s_clause 0x1 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v11, off offset:4 +; DAGISEL-GFX11-NEXT: ; meta instruction ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v16, off ; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v11, v8 ; DAGISEL-GFX11-NEXT: s_mov_b32 s3, s0 diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-expand-feature-predicates-unfoldable.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-expand-feature-predicates-unfoldable.ll new file mode 100644 index 0000000000000..bfc35d8c76e37 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-expand-feature-predicates-unfoldable.ll @@ -0,0 +1,28 @@ +; REQUIRES: amdgpu-registered-target + +; RUN: not opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes='amdgpu-expand-feature-predicates' < %s 2>&1 | FileCheck %s + +; CHECK: error:{{.*}}in function kernel void (ptr addrspace(1), i32, ptr addrspace(1)): Impossible to constant fold feature predicate: @llvm.amdgcn.is.gfx803 = private addrspace(1) constant i1 false used by %call = call i1 %1(i1 zeroext false), please simplify. + +@llvm.amdgcn.is.gfx803 = external addrspace(1) externally_initialized constant i1 + +declare void @llvm.amdgcn.s.sleep(i32 immarg) #1 + +define amdgpu_kernel void @kernel(ptr addrspace(1) readnone captures(none) %p.coerce, i32 %x, ptr addrspace(1) %pfn.coerce) { +entry: + %0 = ptrtoint ptr addrspace(1) %pfn.coerce to i64 + %1 = inttoptr i64 %0 to ptr + %2 = ptrtoint ptr addrspace(1) %pfn.coerce to i64 + %3 = load i1, ptr addrspace(1) @llvm.amdgcn.is.gfx803, align 1 + %call = call i1 %1(i1 zeroext %3) + br i1 %call, label %if.gfx803, label %if.end + +if.gfx803: + call void @llvm.amdgcn.s.sleep(i32 0) + br label %if.end + +if.end: + ret void +} + +attributes #1 = { nocallback nofree nosync nounwind willreturn } diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-expand-feature-predicates.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-expand-feature-predicates.ll new file mode 100644 index 0000000000000..a16a7fc31da22 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-expand-feature-predicates.ll @@ -0,0 +1,284 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; REQUIRES: amdgpu-registered-target + +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes='amdgpu-expand-feature-predicates' %s -o - | FileCheck --check-prefix=GFX906 %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -passes='amdgpu-expand-feature-predicates' %s -o - | FileCheck --check-prefix=GFX1010 %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1101 -passes='amdgpu-expand-feature-predicates' %s -o - | FileCheck --check-prefix=GFX1101 %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1201 -passes='amdgpu-expand-feature-predicates' %s -o - | FileCheck --check-prefix=GFX1201 %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1201 -mattr=+wavefrontsize64 -passes='amdgpu-expand-feature-predicates' %s -o - | FileCheck --check-prefix=GFX1201-W64 %s + +;; The IR was derived from the following source: +;; extern "C" __global__ void kernel(int* p, int x) +;; { +;; if (__builtin_amdgcn_processor_is("gfx1201") || +;; __builtin_amdgcn_is_invocable(__builtin_amdgcn_s_sleep_var)) +;; __builtin_amdgcn_s_sleep_var(x); +;; if (!__builtin_amdgcn_processor_is("gfx906")) +;; __builtin_amdgcn_s_wait_event_export_ready(); +;; else if (__builtin_amdgcn_processor_is("gfx1010") || +;; __builtin_amdgcn_processor_is("gfx1101")) +;; __builtin_amdgcn_s_ttracedata_imm(1); +;; while (__builtin_amdgcn_processor_is("gfx1101")) *p += x; +;; do { +;; *p -= x; +;; } while (__builtin_amdgcn_processor_is("gfx1010")); +;; for (; __builtin_amdgcn_processor_is("gfx1201"); ++*p) break; +;; +;; if (__builtin_amdgcn_is_invocable(__builtin_amdgcn_s_wait_event_export_ready)) +;; __builtin_amdgcn_s_wait_event_export_ready(); +;; else if (__builtin_amdgcn_is_invocable(__builtin_amdgcn_s_ttracedata_imm)) +;; __builtin_amdgcn_s_ttracedata_imm(1); +;; +;; do { +;; *p -= x; +;; } while (__builtin_amdgcn_is_invocable(__builtin_amdgcn_global_load_tr_b64_i32)); +;; for (; __builtin_amdgcn_is_invocable(__builtin_amdgcn_permlane64); ++*p) break; +;; } + +@llvm.amdgcn.is.gfx1201 = external addrspace(1) externally_initialized constant i1 +@llvm.amdgcn.has.gfx12-insts = external addrspace(1) externally_initialized constant i1 +@llvm.amdgcn.is.gfx906 = external addrspace(1) externally_initialized constant i1 +@llvm.amdgcn.is.gfx1010 = external addrspace(1) externally_initialized constant i1 +@llvm.amdgcn.is.gfx1101 = external addrspace(1) externally_initialized constant i1 +@llvm.amdgcn.has.gfx11-insts = external addrspace(1) externally_initialized constant i1 +@llvm.amdgcn.has.gfx10-insts = external addrspace(1) externally_initialized constant i1 +@"llvm.amdgcn.has.gfx12-insts,wavefrontsize64" = external addrspace(1) externally_initialized constant i1 + +declare void @llvm.amdgcn.s.sleep.var(i32) +declare void @llvm.amdgcn.s.wait.event.export.ready() +declare void @llvm.amdgcn.s.ttracedata.imm(i16 immarg) + +define amdgpu_kernel void @kernel(ptr addrspace(1) %p.coerce, i32 %x) { +; GFX906-LABEL: define amdgpu_kernel void @kernel( +; GFX906-SAME: ptr addrspace(1) [[P_COERCE:%.*]], i32 [[X:%.*]]) #[[ATTR2:[0-9]+]] { +; GFX906-NEXT: [[ENTRY:.*:]] +; GFX906-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P_COERCE]] to i64 +; GFX906-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to ptr +; GFX906-NEXT: br label %[[IF_GFX1201_OR_GFX12_INSTS:.*]] +; GFX906: [[IF_GFX1201_OR_GFX12_INSTS]]: +; GFX906-NEXT: br label %[[IF_NOT_GFX907:.*]] +; GFX906: [[IF_NOT_GFX907]]: +; GFX906-NEXT: br label %[[IF_GFX1010_OR_GFX1101:.*]] +; GFX906: [[IF_GFX1010_OR_GFX1101]]: +; GFX906-NEXT: br label %[[LOR_NOT_GFX1010:.*]] +; GFX906: [[LOR_NOT_GFX1010]]: +; GFX906-NEXT: br label %[[FOR_COND:.*]] +; GFX906: [[FOR_COND]]: +; GFX906-NEXT: [[DOTPROMOTED:%.*]] = load i32, ptr [[TMP1]], align 4 +; GFX906-NEXT: [[SUB_PEEL:%.*]] = sub nsw i32 [[DOTPROMOTED]], [[X]] +; GFX906-NEXT: store i32 [[SUB_PEEL]], ptr [[TMP1]], align 4 +; GFX906-NEXT: br label %[[IF_GFX11_INSTS:.*]] +; GFX906: [[IF_GFX11_INSTS]]: +; GFX906-NEXT: br label %[[IF_GFX10_INSTS:.*]] +; GFX906: [[IF_GFX10_INSTS]]: +; GFX906-NEXT: call void @llvm.assume(i1 true) +; GFX906-NEXT: [[DOTPROMOTED9:%.*]] = load i32, ptr [[TMP1]], align 4 +; GFX906-NEXT: [[SUB13_PEEL:%.*]] = sub nsw i32 [[DOTPROMOTED9]], [[X]] +; GFX906-NEXT: store i32 [[SUB13_PEEL]], ptr [[TMP1]], align 4 +; GFX906-NEXT: ret void +; +; GFX1010-LABEL: define amdgpu_kernel void @kernel( +; GFX1010-SAME: ptr addrspace(1) [[P_COERCE:%.*]], i32 [[X:%.*]]) #[[ATTR2:[0-9]+]] { +; GFX1010-NEXT: [[ENTRY:.*:]] +; GFX1010-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P_COERCE]] to i64 +; GFX1010-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to ptr +; GFX1010-NEXT: br label %[[IF_GFX1201_OR_GFX12_INSTS:.*]] +; GFX1010: [[IF_GFX1201_OR_GFX12_INSTS]]: +; GFX1010-NEXT: br label %[[IF_NOT_GFX906:.*]] +; GFX1010: [[IF_NOT_GFX906]]: +; GFX1010-NEXT: br label %[[LOR_NOT_GFX1010:.*]] +; GFX1010: [[LOR_NOT_GFX1010]]: +; GFX1010-NEXT: call void @llvm.amdgcn.s.wait.event.export.ready() +; GFX1010-NEXT: br label %[[IF_END6:.*]] +; GFX1010: [[IF_END6]]: +; GFX1010-NEXT: call void @llvm.assume(i1 true) +; GFX1010-NEXT: call void @llvm.assume(i1 true) +; GFX1010-NEXT: br label %[[FOR_COND:.*]] +; GFX1010: [[FOR_COND]]: +; GFX1010-NEXT: [[DOTPROMOTED:%.*]] = load i32, ptr [[TMP1]], align 4 +; GFX1010-NEXT: [[SUB_PEEL:%.*]] = sub nsw i32 [[DOTPROMOTED]], [[X]] +; GFX1010-NEXT: store i32 [[SUB_PEEL]], ptr [[TMP1]], align 4 +; GFX1010-NEXT: br label %[[IF_GFX11_INSTS:.*]] +; GFX1010: [[IF_GFX11_INSTS]]: +; GFX1010-NEXT: br label %[[IF_GFX10_INSTS:.*]] +; GFX1010: [[IF_GFX10_INSTS]]: +; GFX1010-NEXT: call void @llvm.amdgcn.s.ttracedata.imm(i16 1) +; GFX1010-NEXT: br label %[[IF_END11:.*]] +; GFX1010: [[IF_END11]]: +; GFX1010-NEXT: call void @llvm.assume(i1 true) +; GFX1010-NEXT: [[DOTPROMOTED9:%.*]] = load i32, ptr [[TMP1]], align 4 +; GFX1010-NEXT: [[SUB13_PEEL:%.*]] = sub nsw i32 [[DOTPROMOTED9]], [[X]] +; GFX1010-NEXT: store i32 [[SUB13_PEEL]], ptr [[TMP1]], align 4 +; GFX1010-NEXT: ret void +; +; GFX1101-LABEL: define amdgpu_kernel void @kernel( +; GFX1101-SAME: ptr addrspace(1) [[P_COERCE:%.*]], i32 [[X:%.*]]) #[[ATTR2:[0-9]+]] { +; GFX1101-NEXT: [[ENTRY:.*:]] +; GFX1101-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P_COERCE]] to i64 +; GFX1101-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to ptr +; GFX1101-NEXT: br label %[[IF_GFX1201_OR_GFX12_INSTS:.*]] +; GFX1101: [[IF_GFX1201_OR_GFX12_INSTS]]: +; GFX1101-NEXT: br label %[[IF_END:.*]] +; GFX1101: [[IF_END]]: +; GFX1101-NEXT: br label %[[IF_NOT_GFX907:.*]] +; GFX1101: [[IF_NOT_GFX907]]: +; GFX1101-NEXT: call void @llvm.amdgcn.s.wait.event.export.ready() +; GFX1101-NEXT: br label %[[IF_NOT_GFX906:.*]] +; GFX1101: [[IF_NOT_GFX906]]: +; GFX1101-NEXT: call void @llvm.assume(i1 true) +; GFX1101-NEXT: call void @llvm.assume(i1 true) +; GFX1101-NEXT: br label %[[FOR_COND:.*]] +; GFX1101: [[FOR_COND]]: +; GFX1101-NEXT: [[DOTPROMOTED:%.*]] = load i32, ptr [[TMP1]], align 4 +; GFX1101-NEXT: [[SUB_PEEL:%.*]] = sub nsw i32 [[DOTPROMOTED]], [[X]] +; GFX1101-NEXT: store i32 [[SUB_PEEL]], ptr [[TMP1]], align 4 +; GFX1101-NEXT: br label %[[IF_GFX11_INSTS:.*]] +; GFX1101: [[IF_GFX11_INSTS]]: +; GFX1101-NEXT: call void @llvm.amdgcn.s.wait.event.export.ready() +; GFX1101-NEXT: br label %[[IF_ELSE8:.*]] +; GFX1101: [[IF_ELSE8]]: +; GFX1101-NEXT: call void @llvm.assume(i1 true) +; GFX1101-NEXT: [[DOTPROMOTED9:%.*]] = load i32, ptr [[TMP1]], align 4 +; GFX1101-NEXT: [[SUB13_PEEL:%.*]] = sub nsw i32 [[DOTPROMOTED9]], [[X]] +; GFX1101-NEXT: store i32 [[SUB13_PEEL]], ptr [[TMP1]], align 4 +; GFX1101-NEXT: ret void +; +; GFX1201-LABEL: define amdgpu_kernel void @kernel( +; GFX1201-SAME: ptr addrspace(1) [[P_COERCE:%.*]], i32 [[X:%.*]]) #[[ATTR2:[0-9]+]] { +; GFX1201-NEXT: [[ENTRY:.*:]] +; GFX1201-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P_COERCE]] to i64 +; GFX1201-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to ptr +; GFX1201-NEXT: br label %[[LOR_NOT_GFX1201:.*]] +; GFX1201: [[LOR_NOT_GFX1201]]: +; GFX1201-NEXT: call void @llvm.amdgcn.s.sleep.var(i32 [[X]]) +; GFX1201-NEXT: br label %[[IF_NOT_GFX906:.*]] +; GFX1201: [[IF_NOT_GFX906]]: +; GFX1201-NEXT: br label %[[IF_GFX1010_OR_GFX1101:.*]] +; GFX1201: [[IF_GFX1010_OR_GFX1101]]: +; GFX1201-NEXT: call void @llvm.amdgcn.s.wait.event.export.ready() +; GFX1201-NEXT: br label %[[IF_END6:.*]] +; GFX1201: [[IF_END6]]: +; GFX1201-NEXT: call void @llvm.assume(i1 true) +; GFX1201-NEXT: call void @llvm.assume(i1 true) +; GFX1201-NEXT: br label %[[FOR_COND:.*]] +; GFX1201: [[FOR_COND]]: +; GFX1201-NEXT: [[DOTPROMOTED:%.*]] = load i32, ptr [[TMP1]], align 4 +; GFX1201-NEXT: [[SUB_PEEL:%.*]] = sub nsw i32 [[DOTPROMOTED]], [[X]] +; GFX1201-NEXT: store i32 [[SUB_PEEL]], ptr [[TMP1]], align 4 +; GFX1201-NEXT: br label %[[IF_GFX11_INSTS:.*]] +; GFX1201: [[IF_GFX11_INSTS]]: +; GFX1201-NEXT: call void @llvm.amdgcn.s.wait.event.export.ready() +; GFX1201-NEXT: br label %[[IF_ELSE8:.*]] +; GFX1201: [[IF_ELSE8]]: +; GFX1201-NEXT: call void @llvm.assume(i1 true) +; GFX1201-NEXT: [[DOTPROMOTED9:%.*]] = load i32, ptr [[TMP1]], align 4 +; GFX1201-NEXT: [[SUB13_PEEL:%.*]] = sub nsw i32 [[DOTPROMOTED9]], [[X]] +; GFX1201-NEXT: store i32 [[SUB13_PEEL]], ptr [[TMP1]], align 4 +; GFX1201-NEXT: ret void +; +; GFX1201-W64-LABEL: define amdgpu_kernel void @kernel( +; GFX1201-W64-SAME: ptr addrspace(1) [[P_COERCE:%.*]], i32 [[X:%.*]]) #[[ATTR2:[0-9]+]] { +; GFX1201-W64-NEXT: [[ENTRY:.*:]] +; GFX1201-W64-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P_COERCE]] to i64 +; GFX1201-W64-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to ptr +; GFX1201-W64-NEXT: br label %[[LOR_NOT_GFX1201:.*]] +; GFX1201-W64: [[LOR_NOT_GFX1201]]: +; GFX1201-W64-NEXT: call void @llvm.amdgcn.s.sleep.var(i32 [[X]]) +; GFX1201-W64-NEXT: br label %[[IF_NOT_GFX906:.*]] +; GFX1201-W64: [[IF_NOT_GFX906]]: +; GFX1201-W64-NEXT: br label %[[IF_GFX1010_OR_GFX1101:.*]] +; GFX1201-W64: [[IF_GFX1010_OR_GFX1101]]: +; GFX1201-W64-NEXT: call void @llvm.amdgcn.s.wait.event.export.ready() +; GFX1201-W64-NEXT: br label %[[IF_END6:.*]] +; GFX1201-W64: [[IF_END6]]: +; GFX1201-W64-NEXT: call void @llvm.assume(i1 true) +; GFX1201-W64-NEXT: call void @llvm.assume(i1 true) +; GFX1201-W64-NEXT: br label %[[FOR_COND:.*]] +; GFX1201-W64: [[FOR_COND]]: +; GFX1201-W64-NEXT: [[DOTPROMOTED:%.*]] = load i32, ptr [[TMP1]], align 4 +; GFX1201-W64-NEXT: [[SUB_PEEL:%.*]] = sub nsw i32 [[DOTPROMOTED]], [[X]] +; GFX1201-W64-NEXT: store i32 [[SUB_PEEL]], ptr [[TMP1]], align 4 +; GFX1201-W64-NEXT: br label %[[IF_GFX11_INSTS:.*]] +; GFX1201-W64: [[IF_GFX11_INSTS]]: +; GFX1201-W64-NEXT: call void @llvm.amdgcn.s.wait.event.export.ready() +; GFX1201-W64-NEXT: br label %[[IF_ELSE8:.*]] +; GFX1201-W64: [[IF_ELSE8]]: +; GFX1201-W64-NEXT: call void @llvm.assume(i1 true) +; GFX1201-W64-NEXT: [[DOTPROMOTED9:%.*]] = load i32, ptr [[TMP1]], align 4 +; GFX1201-W64-NEXT: [[SUB13_PEEL:%.*]] = sub nsw i32 [[DOTPROMOTED9]], [[X]] +; GFX1201-W64-NEXT: store i32 [[SUB13_PEEL]], ptr [[TMP1]], align 4 +; GFX1201-W64-NEXT: ret void +; +entry: + %0 = ptrtoint ptr addrspace(1) %p.coerce to i64 + %1 = inttoptr i64 %0 to ptr + %2 = load i1, ptr addrspace(1) @llvm.amdgcn.is.gfx1201, align 1 + br i1 %2, label %if.gfx1201.or.gfx12-insts, label %lor.not.gfx1201 + +lor.not.gfx1201: + %3 = load i1, ptr addrspace(1) @llvm.amdgcn.has.gfx12-insts, align 1 + br i1 %3, label %if.gfx1201.or.gfx12-insts, label %if.end + +if.gfx1201.or.gfx12-insts: + call void @llvm.amdgcn.s.sleep.var(i32 %x) + br label %if.end + +if.end: + %4 = load i1, ptr addrspace(1) @llvm.amdgcn.is.gfx906, align 1 + br i1 %4, label %if.gfx906, label %if.not.gfx906 + +if.not.gfx906: + call void @llvm.amdgcn.s.wait.event.export.ready() + br label %if.end6 + +if.gfx906: + %5 = load i1, ptr addrspace(1) @llvm.amdgcn.is.gfx1010, align 1 + br i1 %5, label %if.gfx1010.or.gfx1101, label %lor.not.gfx1010 + +lor.not.gfx1010: + %6 = load i1, ptr addrspace(1) @llvm.amdgcn.is.gfx1101, align 1 + br i1 %6, label %if.gfx1010.or.gfx1101, label %for.cond + +if.gfx1010.or.gfx1101: + call void @llvm.amdgcn.s.ttracedata.imm(i16 1) + br label %if.end6 + +if.end6: + %.pr.pr = load i1, ptr addrspace(1) @llvm.amdgcn.is.gfx1101, align 1 + %7 = icmp ne i1 %.pr.pr, true + call void @llvm.assume(i1 %7) + %.pr6.pr = load i1, ptr addrspace(1) @llvm.amdgcn.is.gfx1010, align 1 + %8 = icmp ne i1 %.pr6.pr, true + call void @llvm.assume(i1 %8) + br label %for.cond + +for.cond: + %.promoted = load i32, ptr %1, align 4 + %sub.peel = sub nsw i32 %.promoted, %x + store i32 %sub.peel, ptr %1, align 4 + %9 = load i1, ptr addrspace(1) @llvm.amdgcn.has.gfx11-insts, align 1 + br i1 %9, label %if.gfx11-insts, label %if.else8 + +if.gfx11-insts: + call void @llvm.amdgcn.s.wait.event.export.ready() + br label %if.end11 + +if.else8: + %10 = load i1, ptr addrspace(1) @llvm.amdgcn.has.gfx10-insts, align 1 + br i1 %10, label %if.gfx10-insts, label %if.end11 + +if.gfx10-insts: + call void @llvm.amdgcn.s.ttracedata.imm(i16 1) + br label %if.end11 + +if.end11: + %.pr7 = load i1, ptr addrspace(1) @"llvm.amdgcn.has.gfx12-insts,wavefrontsize64", align 1 + %11 = icmp ne i1 %.pr7, true + call void @llvm.assume(i1 %11) + %.promoted9 = load i32, ptr %1, align 4 + %sub13.peel = sub nsw i32 %.promoted9, %x + store i32 %sub13.peel, ptr %1, align 4 + ret void +} + +declare void @llvm.assume(i1 noundef) diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll index 0329f23ea434f..954812c09d19a 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll @@ -118,32 +118,32 @@ define double @test_pow_fast_f64__integral_y(double %x, i32 %y.i) { ; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[18:19] ; CHECK-NEXT: v_writelane_b32 v43, s16, 14 -; CHECK-NEXT: v_writelane_b32 v43, s30, 0 -; CHECK-NEXT: v_writelane_b32 v43, s31, 1 -; CHECK-NEXT: v_writelane_b32 v43, s34, 2 -; CHECK-NEXT: v_writelane_b32 v43, s35, 3 -; CHECK-NEXT: v_writelane_b32 v43, s36, 4 -; CHECK-NEXT: v_writelane_b32 v43, s37, 5 -; CHECK-NEXT: v_writelane_b32 v43, s38, 6 -; CHECK-NEXT: v_writelane_b32 v43, s39, 7 ; CHECK-NEXT: s_addk_i32 s32, 0x800 -; CHECK-NEXT: v_writelane_b32 v43, s48, 8 -; CHECK-NEXT: v_writelane_b32 v43, s49, 9 +; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill +; CHECK-NEXT: v_writelane_b32 v43, s34, 0 +; CHECK-NEXT: v_writelane_b32 v43, s35, 1 +; CHECK-NEXT: v_writelane_b32 v43, s36, 2 +; CHECK-NEXT: v_writelane_b32 v43, s37, 3 +; CHECK-NEXT: v_writelane_b32 v43, s38, 4 +; CHECK-NEXT: v_writelane_b32 v43, s39, 5 +; CHECK-NEXT: v_writelane_b32 v43, s48, 6 +; CHECK-NEXT: v_writelane_b32 v43, s49, 7 +; CHECK-NEXT: v_writelane_b32 v43, s50, 8 +; CHECK-NEXT: v_writelane_b32 v43, s51, 9 +; CHECK-NEXT: v_writelane_b32 v43, s52, 10 +; CHECK-NEXT: v_writelane_b32 v43, s53, 11 +; CHECK-NEXT: v_writelane_b32 v43, s30, 12 +; CHECK-NEXT: v_writelane_b32 v43, s31, 13 ; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5] ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d@gotpcrel32@lo+4 ; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d@gotpcrel32@hi+12 ; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0 -; CHECK-NEXT: v_writelane_b32 v43, s50, 10 -; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill -; CHECK-NEXT: v_writelane_b32 v43, s51, 11 ; CHECK-NEXT: v_mov_b32_e32 v42, v1 -; CHECK-NEXT: v_writelane_b32 v43, s52, 12 ; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v42 ; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49] -; CHECK-NEXT: v_writelane_b32 v43, s53, 13 ; CHECK-NEXT: v_mov_b32_e32 v40, v31 ; CHECK-NEXT: v_mov_b32_e32 v41, v2 ; CHECK-NEXT: s_mov_b32 s50, s15 @@ -177,21 +177,21 @@ define double @test_pow_fast_f64__integral_y(double %x, i32 %y.i) { ; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload +; CHECK-NEXT: v_readlane_b32 s30, v43, 12 ; CHECK-NEXT: v_or_b32_e32 v1, v2, v1 -; CHECK-NEXT: v_readlane_b32 s53, v43, 13 -; CHECK-NEXT: v_readlane_b32 s52, v43, 12 -; CHECK-NEXT: v_readlane_b32 s51, v43, 11 -; CHECK-NEXT: v_readlane_b32 s50, v43, 10 -; CHECK-NEXT: v_readlane_b32 s49, v43, 9 -; CHECK-NEXT: v_readlane_b32 s48, v43, 8 -; CHECK-NEXT: v_readlane_b32 s39, v43, 7 -; CHECK-NEXT: v_readlane_b32 s38, v43, 6 -; CHECK-NEXT: v_readlane_b32 s37, v43, 5 -; CHECK-NEXT: v_readlane_b32 s36, v43, 4 -; CHECK-NEXT: v_readlane_b32 s35, v43, 3 -; CHECK-NEXT: v_readlane_b32 s34, v43, 2 -; CHECK-NEXT: v_readlane_b32 s31, v43, 1 -; CHECK-NEXT: v_readlane_b32 s30, v43, 0 +; CHECK-NEXT: v_readlane_b32 s31, v43, 13 +; CHECK-NEXT: v_readlane_b32 s53, v43, 11 +; CHECK-NEXT: v_readlane_b32 s52, v43, 10 +; CHECK-NEXT: v_readlane_b32 s51, v43, 9 +; CHECK-NEXT: v_readlane_b32 s50, v43, 8 +; CHECK-NEXT: v_readlane_b32 s49, v43, 7 +; CHECK-NEXT: v_readlane_b32 s48, v43, 6 +; CHECK-NEXT: v_readlane_b32 s39, v43, 5 +; CHECK-NEXT: v_readlane_b32 s38, v43, 4 +; CHECK-NEXT: v_readlane_b32 s37, v43, 3 +; CHECK-NEXT: v_readlane_b32 s36, v43, 2 +; CHECK-NEXT: v_readlane_b32 s35, v43, 1 +; CHECK-NEXT: v_readlane_b32 s34, v43, 0 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: v_readlane_b32 s4, v43, 14 ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -258,30 +258,30 @@ define double @test_powr_fast_f64(double %x, double %y) { ; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[18:19] ; CHECK-NEXT: v_writelane_b32 v43, s16, 14 -; CHECK-NEXT: v_writelane_b32 v43, s30, 0 -; CHECK-NEXT: v_writelane_b32 v43, s31, 1 -; CHECK-NEXT: v_writelane_b32 v43, s34, 2 -; CHECK-NEXT: v_writelane_b32 v43, s35, 3 -; CHECK-NEXT: v_writelane_b32 v43, s36, 4 -; CHECK-NEXT: v_writelane_b32 v43, s37, 5 -; CHECK-NEXT: v_writelane_b32 v43, s38, 6 -; CHECK-NEXT: v_writelane_b32 v43, s39, 7 ; CHECK-NEXT: s_addk_i32 s32, 0x800 -; CHECK-NEXT: v_writelane_b32 v43, s48, 8 -; CHECK-NEXT: v_writelane_b32 v43, s49, 9 +; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill +; CHECK-NEXT: v_writelane_b32 v43, s34, 0 +; CHECK-NEXT: v_writelane_b32 v43, s35, 1 +; CHECK-NEXT: v_writelane_b32 v43, s36, 2 +; CHECK-NEXT: v_writelane_b32 v43, s37, 3 +; CHECK-NEXT: v_writelane_b32 v43, s38, 4 +; CHECK-NEXT: v_writelane_b32 v43, s39, 5 +; CHECK-NEXT: v_writelane_b32 v43, s48, 6 +; CHECK-NEXT: v_writelane_b32 v43, s49, 7 +; CHECK-NEXT: v_writelane_b32 v43, s50, 8 +; CHECK-NEXT: v_writelane_b32 v43, s51, 9 +; CHECK-NEXT: v_writelane_b32 v43, s52, 10 +; CHECK-NEXT: v_writelane_b32 v43, s53, 11 +; CHECK-NEXT: v_writelane_b32 v43, s30, 12 +; CHECK-NEXT: v_writelane_b32 v43, s31, 13 ; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5] ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d@gotpcrel32@lo+4 ; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d@gotpcrel32@hi+12 ; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0 -; CHECK-NEXT: v_writelane_b32 v43, s50, 10 -; CHECK-NEXT: v_writelane_b32 v43, s51, 11 -; CHECK-NEXT: v_writelane_b32 v43, s52, 12 ; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49] -; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill -; CHECK-NEXT: v_writelane_b32 v43, s53, 13 ; CHECK-NEXT: v_mov_b32_e32 v42, v31 ; CHECK-NEXT: v_mov_b32_e32 v41, v3 ; CHECK-NEXT: v_mov_b32_e32 v40, v2 @@ -313,20 +313,20 @@ define double @test_powr_fast_f64(double %x, double %y) { ; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload -; CHECK-NEXT: v_readlane_b32 s53, v43, 13 -; CHECK-NEXT: v_readlane_b32 s52, v43, 12 -; CHECK-NEXT: v_readlane_b32 s51, v43, 11 -; CHECK-NEXT: v_readlane_b32 s50, v43, 10 -; CHECK-NEXT: v_readlane_b32 s49, v43, 9 -; CHECK-NEXT: v_readlane_b32 s48, v43, 8 -; CHECK-NEXT: v_readlane_b32 s39, v43, 7 -; CHECK-NEXT: v_readlane_b32 s38, v43, 6 -; CHECK-NEXT: v_readlane_b32 s37, v43, 5 -; CHECK-NEXT: v_readlane_b32 s36, v43, 4 -; CHECK-NEXT: v_readlane_b32 s35, v43, 3 -; CHECK-NEXT: v_readlane_b32 s34, v43, 2 -; CHECK-NEXT: v_readlane_b32 s31, v43, 1 -; CHECK-NEXT: v_readlane_b32 s30, v43, 0 +; CHECK-NEXT: v_readlane_b32 s30, v43, 12 +; CHECK-NEXT: v_readlane_b32 s31, v43, 13 +; CHECK-NEXT: v_readlane_b32 s53, v43, 11 +; CHECK-NEXT: v_readlane_b32 s52, v43, 10 +; CHECK-NEXT: v_readlane_b32 s51, v43, 9 +; CHECK-NEXT: v_readlane_b32 s50, v43, 8 +; CHECK-NEXT: v_readlane_b32 s49, v43, 7 +; CHECK-NEXT: v_readlane_b32 s48, v43, 6 +; CHECK-NEXT: v_readlane_b32 s39, v43, 5 +; CHECK-NEXT: v_readlane_b32 s38, v43, 4 +; CHECK-NEXT: v_readlane_b32 s37, v43, 3 +; CHECK-NEXT: v_readlane_b32 s36, v43, 2 +; CHECK-NEXT: v_readlane_b32 s35, v43, 1 +; CHECK-NEXT: v_readlane_b32 s34, v43, 0 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: v_readlane_b32 s4, v43, 14 ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -400,32 +400,32 @@ define double @test_pown_fast_f64(double %x, i32 %y) { ; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[18:19] ; CHECK-NEXT: v_writelane_b32 v43, s16, 14 -; CHECK-NEXT: v_writelane_b32 v43, s30, 0 -; CHECK-NEXT: v_writelane_b32 v43, s31, 1 -; CHECK-NEXT: v_writelane_b32 v43, s34, 2 -; CHECK-NEXT: v_writelane_b32 v43, s35, 3 -; CHECK-NEXT: v_writelane_b32 v43, s36, 4 -; CHECK-NEXT: v_writelane_b32 v43, s37, 5 -; CHECK-NEXT: v_writelane_b32 v43, s38, 6 -; CHECK-NEXT: v_writelane_b32 v43, s39, 7 ; CHECK-NEXT: s_addk_i32 s32, 0x800 -; CHECK-NEXT: v_writelane_b32 v43, s48, 8 -; CHECK-NEXT: v_writelane_b32 v43, s49, 9 +; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill +; CHECK-NEXT: v_writelane_b32 v43, s34, 0 +; CHECK-NEXT: v_writelane_b32 v43, s35, 1 +; CHECK-NEXT: v_writelane_b32 v43, s36, 2 +; CHECK-NEXT: v_writelane_b32 v43, s37, 3 +; CHECK-NEXT: v_writelane_b32 v43, s38, 4 +; CHECK-NEXT: v_writelane_b32 v43, s39, 5 +; CHECK-NEXT: v_writelane_b32 v43, s48, 6 +; CHECK-NEXT: v_writelane_b32 v43, s49, 7 +; CHECK-NEXT: v_writelane_b32 v43, s50, 8 +; CHECK-NEXT: v_writelane_b32 v43, s51, 9 +; CHECK-NEXT: v_writelane_b32 v43, s52, 10 +; CHECK-NEXT: v_writelane_b32 v43, s53, 11 +; CHECK-NEXT: v_writelane_b32 v43, s30, 12 +; CHECK-NEXT: v_writelane_b32 v43, s31, 13 ; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5] ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d@gotpcrel32@lo+4 ; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d@gotpcrel32@hi+12 ; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0 -; CHECK-NEXT: v_writelane_b32 v43, s50, 10 -; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill -; CHECK-NEXT: v_writelane_b32 v43, s51, 11 ; CHECK-NEXT: v_mov_b32_e32 v42, v1 -; CHECK-NEXT: v_writelane_b32 v43, s52, 12 ; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v42 ; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49] -; CHECK-NEXT: v_writelane_b32 v43, s53, 13 ; CHECK-NEXT: v_mov_b32_e32 v40, v31 ; CHECK-NEXT: v_mov_b32_e32 v41, v2 ; CHECK-NEXT: s_mov_b32 s50, s15 @@ -459,21 +459,21 @@ define double @test_pown_fast_f64(double %x, i32 %y) { ; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload +; CHECK-NEXT: v_readlane_b32 s30, v43, 12 ; CHECK-NEXT: v_or_b32_e32 v1, v2, v1 -; CHECK-NEXT: v_readlane_b32 s53, v43, 13 -; CHECK-NEXT: v_readlane_b32 s52, v43, 12 -; CHECK-NEXT: v_readlane_b32 s51, v43, 11 -; CHECK-NEXT: v_readlane_b32 s50, v43, 10 -; CHECK-NEXT: v_readlane_b32 s49, v43, 9 -; CHECK-NEXT: v_readlane_b32 s48, v43, 8 -; CHECK-NEXT: v_readlane_b32 s39, v43, 7 -; CHECK-NEXT: v_readlane_b32 s38, v43, 6 -; CHECK-NEXT: v_readlane_b32 s37, v43, 5 -; CHECK-NEXT: v_readlane_b32 s36, v43, 4 -; CHECK-NEXT: v_readlane_b32 s35, v43, 3 -; CHECK-NEXT: v_readlane_b32 s34, v43, 2 -; CHECK-NEXT: v_readlane_b32 s31, v43, 1 -; CHECK-NEXT: v_readlane_b32 s30, v43, 0 +; CHECK-NEXT: v_readlane_b32 s31, v43, 13 +; CHECK-NEXT: v_readlane_b32 s53, v43, 11 +; CHECK-NEXT: v_readlane_b32 s52, v43, 10 +; CHECK-NEXT: v_readlane_b32 s51, v43, 9 +; CHECK-NEXT: v_readlane_b32 s50, v43, 8 +; CHECK-NEXT: v_readlane_b32 s49, v43, 7 +; CHECK-NEXT: v_readlane_b32 s48, v43, 6 +; CHECK-NEXT: v_readlane_b32 s39, v43, 5 +; CHECK-NEXT: v_readlane_b32 s38, v43, 4 +; CHECK-NEXT: v_readlane_b32 s37, v43, 3 +; CHECK-NEXT: v_readlane_b32 s36, v43, 2 +; CHECK-NEXT: v_readlane_b32 s35, v43, 1 +; CHECK-NEXT: v_readlane_b32 s34, v43, 0 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: v_readlane_b32 s4, v43, 14 ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -542,30 +542,30 @@ define double @test_pown_fast_f64_known_even(double %x, i32 %y.arg) { ; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[18:19] ; CHECK-NEXT: v_writelane_b32 v42, s16, 14 -; CHECK-NEXT: v_writelane_b32 v42, s30, 0 -; CHECK-NEXT: v_writelane_b32 v42, s31, 1 -; CHECK-NEXT: v_writelane_b32 v42, s34, 2 -; CHECK-NEXT: v_writelane_b32 v42, s35, 3 -; CHECK-NEXT: v_writelane_b32 v42, s36, 4 -; CHECK-NEXT: v_writelane_b32 v42, s37, 5 -; CHECK-NEXT: v_writelane_b32 v42, s38, 6 -; CHECK-NEXT: v_writelane_b32 v42, s39, 7 ; CHECK-NEXT: s_addk_i32 s32, 0x400 -; CHECK-NEXT: v_writelane_b32 v42, s48, 8 -; CHECK-NEXT: v_writelane_b32 v42, s49, 9 +; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; CHECK-NEXT: v_writelane_b32 v42, s34, 0 +; CHECK-NEXT: v_writelane_b32 v42, s35, 1 +; CHECK-NEXT: v_writelane_b32 v42, s36, 2 +; CHECK-NEXT: v_writelane_b32 v42, s37, 3 +; CHECK-NEXT: v_writelane_b32 v42, s38, 4 +; CHECK-NEXT: v_writelane_b32 v42, s39, 5 +; CHECK-NEXT: v_writelane_b32 v42, s48, 6 +; CHECK-NEXT: v_writelane_b32 v42, s49, 7 +; CHECK-NEXT: v_writelane_b32 v42, s50, 8 +; CHECK-NEXT: v_writelane_b32 v42, s51, 9 +; CHECK-NEXT: v_writelane_b32 v42, s52, 10 +; CHECK-NEXT: v_writelane_b32 v42, s53, 11 +; CHECK-NEXT: v_writelane_b32 v42, s30, 12 +; CHECK-NEXT: v_writelane_b32 v42, s31, 13 ; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5] ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d@gotpcrel32@lo+4 ; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d@gotpcrel32@hi+12 ; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0 -; CHECK-NEXT: v_writelane_b32 v42, s50, 10 -; CHECK-NEXT: v_writelane_b32 v42, s51, 11 -; CHECK-NEXT: v_writelane_b32 v42, s52, 12 ; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 ; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49] -; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill -; CHECK-NEXT: v_writelane_b32 v42, s53, 13 ; CHECK-NEXT: v_mov_b32_e32 v40, v31 ; CHECK-NEXT: s_mov_b32 s50, s15 ; CHECK-NEXT: s_mov_b32 s51, s14 @@ -596,20 +596,20 @@ define double @test_pown_fast_f64_known_even(double %x, i32 %y.arg) { ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] ; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; CHECK-NEXT: v_readlane_b32 s53, v42, 13 -; CHECK-NEXT: v_readlane_b32 s52, v42, 12 -; CHECK-NEXT: v_readlane_b32 s51, v42, 11 -; CHECK-NEXT: v_readlane_b32 s50, v42, 10 -; CHECK-NEXT: v_readlane_b32 s49, v42, 9 -; CHECK-NEXT: v_readlane_b32 s48, v42, 8 -; CHECK-NEXT: v_readlane_b32 s39, v42, 7 -; CHECK-NEXT: v_readlane_b32 s38, v42, 6 -; CHECK-NEXT: v_readlane_b32 s37, v42, 5 -; CHECK-NEXT: v_readlane_b32 s36, v42, 4 -; CHECK-NEXT: v_readlane_b32 s35, v42, 3 -; CHECK-NEXT: v_readlane_b32 s34, v42, 2 -; CHECK-NEXT: v_readlane_b32 s31, v42, 1 -; CHECK-NEXT: v_readlane_b32 s30, v42, 0 +; CHECK-NEXT: v_readlane_b32 s30, v42, 12 +; CHECK-NEXT: v_readlane_b32 s31, v42, 13 +; CHECK-NEXT: v_readlane_b32 s53, v42, 11 +; CHECK-NEXT: v_readlane_b32 s52, v42, 10 +; CHECK-NEXT: v_readlane_b32 s51, v42, 9 +; CHECK-NEXT: v_readlane_b32 s50, v42, 8 +; CHECK-NEXT: v_readlane_b32 s49, v42, 7 +; CHECK-NEXT: v_readlane_b32 s48, v42, 6 +; CHECK-NEXT: v_readlane_b32 s39, v42, 5 +; CHECK-NEXT: v_readlane_b32 s38, v42, 4 +; CHECK-NEXT: v_readlane_b32 s37, v42, 3 +; CHECK-NEXT: v_readlane_b32 s36, v42, 2 +; CHECK-NEXT: v_readlane_b32 s35, v42, 1 +; CHECK-NEXT: v_readlane_b32 s34, v42, 0 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: v_readlane_b32 s4, v42, 14 ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -683,32 +683,32 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) { ; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[18:19] ; CHECK-NEXT: v_writelane_b32 v43, s16, 14 -; CHECK-NEXT: v_writelane_b32 v43, s30, 0 -; CHECK-NEXT: v_writelane_b32 v43, s31, 1 -; CHECK-NEXT: v_writelane_b32 v43, s34, 2 -; CHECK-NEXT: v_writelane_b32 v43, s35, 3 -; CHECK-NEXT: v_writelane_b32 v43, s36, 4 -; CHECK-NEXT: v_writelane_b32 v43, s37, 5 -; CHECK-NEXT: v_writelane_b32 v43, s38, 6 -; CHECK-NEXT: v_writelane_b32 v43, s39, 7 ; CHECK-NEXT: s_addk_i32 s32, 0x800 -; CHECK-NEXT: v_writelane_b32 v43, s48, 8 -; CHECK-NEXT: v_writelane_b32 v43, s49, 9 +; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill +; CHECK-NEXT: v_writelane_b32 v43, s34, 0 +; CHECK-NEXT: v_writelane_b32 v43, s35, 1 +; CHECK-NEXT: v_writelane_b32 v43, s36, 2 +; CHECK-NEXT: v_writelane_b32 v43, s37, 3 +; CHECK-NEXT: v_writelane_b32 v43, s38, 4 +; CHECK-NEXT: v_writelane_b32 v43, s39, 5 +; CHECK-NEXT: v_writelane_b32 v43, s48, 6 +; CHECK-NEXT: v_writelane_b32 v43, s49, 7 +; CHECK-NEXT: v_writelane_b32 v43, s50, 8 +; CHECK-NEXT: v_writelane_b32 v43, s51, 9 +; CHECK-NEXT: v_writelane_b32 v43, s52, 10 +; CHECK-NEXT: v_writelane_b32 v43, s53, 11 +; CHECK-NEXT: v_writelane_b32 v43, s30, 12 +; CHECK-NEXT: v_writelane_b32 v43, s31, 13 ; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5] ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d@gotpcrel32@lo+4 ; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d@gotpcrel32@hi+12 ; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0 -; CHECK-NEXT: v_writelane_b32 v43, s50, 10 -; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill -; CHECK-NEXT: v_writelane_b32 v43, s51, 11 ; CHECK-NEXT: v_mov_b32_e32 v41, v1 -; CHECK-NEXT: v_writelane_b32 v43, s52, 12 ; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v41 ; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49] -; CHECK-NEXT: v_writelane_b32 v43, s53, 13 ; CHECK-NEXT: v_mov_b32_e32 v40, v31 ; CHECK-NEXT: s_mov_b32 s50, s15 ; CHECK-NEXT: s_mov_b32 s51, s14 @@ -741,21 +741,21 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) { ; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload +; CHECK-NEXT: v_readlane_b32 s30, v43, 12 ; CHECK-NEXT: v_or_b32_e32 v1, v2, v1 -; CHECK-NEXT: v_readlane_b32 s53, v43, 13 -; CHECK-NEXT: v_readlane_b32 s52, v43, 12 -; CHECK-NEXT: v_readlane_b32 s51, v43, 11 -; CHECK-NEXT: v_readlane_b32 s50, v43, 10 -; CHECK-NEXT: v_readlane_b32 s49, v43, 9 -; CHECK-NEXT: v_readlane_b32 s48, v43, 8 -; CHECK-NEXT: v_readlane_b32 s39, v43, 7 -; CHECK-NEXT: v_readlane_b32 s38, v43, 6 -; CHECK-NEXT: v_readlane_b32 s37, v43, 5 -; CHECK-NEXT: v_readlane_b32 s36, v43, 4 -; CHECK-NEXT: v_readlane_b32 s35, v43, 3 -; CHECK-NEXT: v_readlane_b32 s34, v43, 2 -; CHECK-NEXT: v_readlane_b32 s31, v43, 1 -; CHECK-NEXT: v_readlane_b32 s30, v43, 0 +; CHECK-NEXT: v_readlane_b32 s31, v43, 13 +; CHECK-NEXT: v_readlane_b32 s53, v43, 11 +; CHECK-NEXT: v_readlane_b32 s52, v43, 10 +; CHECK-NEXT: v_readlane_b32 s51, v43, 9 +; CHECK-NEXT: v_readlane_b32 s50, v43, 8 +; CHECK-NEXT: v_readlane_b32 s49, v43, 7 +; CHECK-NEXT: v_readlane_b32 s48, v43, 6 +; CHECK-NEXT: v_readlane_b32 s39, v43, 5 +; CHECK-NEXT: v_readlane_b32 s38, v43, 4 +; CHECK-NEXT: v_readlane_b32 s37, v43, 3 +; CHECK-NEXT: v_readlane_b32 s36, v43, 2 +; CHECK-NEXT: v_readlane_b32 s35, v43, 1 +; CHECK-NEXT: v_readlane_b32 s34, v43, 0 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: v_readlane_b32 s4, v43, 14 ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll new file mode 100644 index 0000000000000..c804c75ae7d2c --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll @@ -0,0 +1,2556 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-spill-cfi-saved-regs -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,WAVE64 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -amdgpu-spill-cfi-saved-regs -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,WAVE32 %s + +define protected amdgpu_kernel void @kern() #0 { +; CHECK-LABEL: kern: +; CHECK: .Lfunc_begin0: +; CHECK-NEXT: .cfi_sections .debug_frame +; CHECK-NEXT: .cfi_startproc +; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: .cfi_escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 ; +; CHECK-NEXT: .cfi_undefined 16 +; CHECK-NEXT: s_endpgm +entry: + ret void +} + +define hidden void @func_saved_in_clobbered_vgpr() #0 { +; WAVE64-LABEL: func_saved_in_clobbered_vgpr: +; WAVE64: .Lfunc_begin1: +; WAVE64-NEXT: .cfi_startproc +; WAVE64-NEXT: ; %bb.0: ; %entry +; WAVE64-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE64-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE64-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_offset 2560, 0 +; WAVE64-NEXT: s_mov_b64 exec, s[4:5] +; WAVE64-NEXT: v_writelane_b32 v0, exec_lo, 0 +; WAVE64-NEXT: v_writelane_b32 v0, exec_hi, 1 +; WAVE64-NEXT: .cfi_llvm_vector_registers 17, 2560, 0, 32, 2560, 1, 32 +; WAVE64-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; WAVE64-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload +; WAVE64-NEXT: s_mov_b64 exec, s[4:5] +; WAVE64-NEXT: s_waitcnt vmcnt(0) +; WAVE64-NEXT: s_setpc_b64 s[30:31] +; +; WAVE32-LABEL: func_saved_in_clobbered_vgpr: +; WAVE32: .Lfunc_begin1: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: ; %entry +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: s_xor_saveexec_b32 s4, -1 +; WAVE32-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_offset 1536, 0 +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s4 +; WAVE32-NEXT: v_writelane_b32 v0, exec_lo, 0 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1, 1536, 0, 32 +; WAVE32-NEXT: s_xor_saveexec_b32 s4, -1 +; WAVE32-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s4 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_setpc_b64 s[30:31] +entry: + ret void +} + +; Check that the option causes a CSR VGPR to spill when needed. +define hidden void @func_saved_in_preserved_vgpr() #0 { +; WAVE64-LABEL: func_saved_in_preserved_vgpr: +; WAVE64: .Lfunc_begin2: +; WAVE64-NEXT: .cfi_startproc +; WAVE64-NEXT: ; %bb.0: ; %entry +; WAVE64-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE64-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE64-NEXT: .cfi_undefined 2560 +; WAVE64-NEXT: .cfi_undefined 2561 +; WAVE64-NEXT: .cfi_undefined 2562 +; WAVE64-NEXT: .cfi_undefined 2563 +; WAVE64-NEXT: .cfi_undefined 2564 +; WAVE64-NEXT: .cfi_undefined 2565 +; WAVE64-NEXT: .cfi_undefined 2566 +; WAVE64-NEXT: .cfi_undefined 2567 +; WAVE64-NEXT: .cfi_undefined 2568 +; WAVE64-NEXT: .cfi_undefined 2569 +; WAVE64-NEXT: .cfi_undefined 2570 +; WAVE64-NEXT: .cfi_undefined 2571 +; WAVE64-NEXT: .cfi_undefined 2572 +; WAVE64-NEXT: .cfi_undefined 2573 +; WAVE64-NEXT: .cfi_undefined 2574 +; WAVE64-NEXT: .cfi_undefined 2575 +; WAVE64-NEXT: .cfi_undefined 2576 +; WAVE64-NEXT: .cfi_undefined 2577 +; WAVE64-NEXT: .cfi_undefined 2578 +; WAVE64-NEXT: .cfi_undefined 2579 +; WAVE64-NEXT: .cfi_undefined 2580 +; WAVE64-NEXT: .cfi_undefined 2581 +; WAVE64-NEXT: .cfi_undefined 2582 +; WAVE64-NEXT: .cfi_undefined 2583 +; WAVE64-NEXT: .cfi_undefined 2584 +; WAVE64-NEXT: .cfi_undefined 2585 +; WAVE64-NEXT: .cfi_undefined 2586 +; WAVE64-NEXT: .cfi_undefined 2587 +; WAVE64-NEXT: .cfi_undefined 2588 +; WAVE64-NEXT: .cfi_undefined 2589 +; WAVE64-NEXT: .cfi_undefined 2590 +; WAVE64-NEXT: .cfi_undefined 2591 +; WAVE64-NEXT: .cfi_undefined 2592 +; WAVE64-NEXT: .cfi_undefined 2593 +; WAVE64-NEXT: .cfi_undefined 2594 +; WAVE64-NEXT: .cfi_undefined 2595 +; WAVE64-NEXT: .cfi_undefined 2596 +; WAVE64-NEXT: .cfi_undefined 2597 +; WAVE64-NEXT: .cfi_undefined 2598 +; WAVE64-NEXT: .cfi_undefined 2599 +; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE64-NEXT: s_or_saveexec_b64 s[4:5], -1 +; WAVE64-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_offset 2600, 0 +; WAVE64-NEXT: s_mov_b64 exec, s[4:5] +; WAVE64-NEXT: v_writelane_b32 v40, exec_lo, 0 +; WAVE64-NEXT: v_writelane_b32 v40, exec_hi, 1 +; WAVE64-NEXT: .cfi_llvm_vector_registers 17, 2600, 0, 32, 2600, 1, 32 +; WAVE64-NEXT: ;;#ASMSTART +; WAVE64-NEXT: ; clobber nonpreserved VGPRs +; WAVE64-NEXT: ;;#ASMEND +; WAVE64-NEXT: s_or_saveexec_b64 s[4:5], -1 +; WAVE64-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload +; WAVE64-NEXT: s_mov_b64 exec, s[4:5] +; WAVE64-NEXT: s_waitcnt vmcnt(0) +; WAVE64-NEXT: s_setpc_b64 s[30:31] +; +; WAVE32-LABEL: func_saved_in_preserved_vgpr: +; WAVE32: .Lfunc_begin2: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: ; %entry +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: .cfi_undefined 1536 +; WAVE32-NEXT: .cfi_undefined 1537 +; WAVE32-NEXT: .cfi_undefined 1538 +; WAVE32-NEXT: .cfi_undefined 1539 +; WAVE32-NEXT: .cfi_undefined 1540 +; WAVE32-NEXT: .cfi_undefined 1541 +; WAVE32-NEXT: .cfi_undefined 1542 +; WAVE32-NEXT: .cfi_undefined 1543 +; WAVE32-NEXT: .cfi_undefined 1544 +; WAVE32-NEXT: .cfi_undefined 1545 +; WAVE32-NEXT: .cfi_undefined 1546 +; WAVE32-NEXT: .cfi_undefined 1547 +; WAVE32-NEXT: .cfi_undefined 1548 +; WAVE32-NEXT: .cfi_undefined 1549 +; WAVE32-NEXT: .cfi_undefined 1550 +; WAVE32-NEXT: .cfi_undefined 1551 +; WAVE32-NEXT: .cfi_undefined 1552 +; WAVE32-NEXT: .cfi_undefined 1553 +; WAVE32-NEXT: .cfi_undefined 1554 +; WAVE32-NEXT: .cfi_undefined 1555 +; WAVE32-NEXT: .cfi_undefined 1556 +; WAVE32-NEXT: .cfi_undefined 1557 +; WAVE32-NEXT: .cfi_undefined 1558 +; WAVE32-NEXT: .cfi_undefined 1559 +; WAVE32-NEXT: .cfi_undefined 1560 +; WAVE32-NEXT: .cfi_undefined 1561 +; WAVE32-NEXT: .cfi_undefined 1562 +; WAVE32-NEXT: .cfi_undefined 1563 +; WAVE32-NEXT: .cfi_undefined 1564 +; WAVE32-NEXT: .cfi_undefined 1565 +; WAVE32-NEXT: .cfi_undefined 1566 +; WAVE32-NEXT: .cfi_undefined 1567 +; WAVE32-NEXT: .cfi_undefined 1568 +; WAVE32-NEXT: .cfi_undefined 1569 +; WAVE32-NEXT: .cfi_undefined 1570 +; WAVE32-NEXT: .cfi_undefined 1571 +; WAVE32-NEXT: .cfi_undefined 1572 +; WAVE32-NEXT: .cfi_undefined 1573 +; WAVE32-NEXT: .cfi_undefined 1574 +; WAVE32-NEXT: .cfi_undefined 1575 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: s_or_saveexec_b32 s4, -1 +; WAVE32-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_offset 1576, 0 +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s4 +; WAVE32-NEXT: v_writelane_b32 v40, exec_lo, 0 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1, 1576, 0, 32 +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber nonpreserved VGPRs +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: s_or_saveexec_b32 s4, -1 +; WAVE32-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s4 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_setpc_b64 s[30:31] +entry: + call void asm sideeffect "; clobber nonpreserved VGPRs", + "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9} + ,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19} + ,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29} + ,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38},~{v39}"() + ret void +} + +; There's no return here, so the return address live in was deleted. +define void @empty_func() { +; WAVE64-LABEL: empty_func: +; WAVE64: .Lfunc_begin3: +; WAVE64-NEXT: .cfi_startproc +; WAVE64-NEXT: ; %bb.0: +; WAVE64-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE64-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE64-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_offset 2560, 0 +; WAVE64-NEXT: s_mov_b64 exec, s[4:5] +; WAVE64-NEXT: v_writelane_b32 v0, exec_lo, 0 +; WAVE64-NEXT: v_writelane_b32 v0, exec_hi, 1 +; +; WAVE32-LABEL: empty_func: +; WAVE32: .Lfunc_begin3: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: s_xor_saveexec_b32 s4, -1 +; WAVE32-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_offset 1536, 0 +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s4 +; WAVE32-NEXT: v_writelane_b32 v0, exec_lo, 0 + unreachable +} + +; Check that the option causes RA and EXEC to be spilled to memory. +define void @no_vgprs_to_spill_into() #1 { +; WAVE64-LABEL: no_vgprs_to_spill_into: +; WAVE64: .Lfunc_begin4: +; WAVE64-NEXT: .cfi_startproc +; WAVE64-NEXT: ; %bb.0: +; WAVE64-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE64-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE64-NEXT: .cfi_undefined 2560 +; WAVE64-NEXT: .cfi_undefined 2561 +; WAVE64-NEXT: .cfi_undefined 2562 +; WAVE64-NEXT: .cfi_undefined 2563 +; WAVE64-NEXT: .cfi_undefined 2564 +; WAVE64-NEXT: .cfi_undefined 2565 +; WAVE64-NEXT: .cfi_undefined 2566 +; WAVE64-NEXT: .cfi_undefined 2567 +; WAVE64-NEXT: .cfi_undefined 2568 +; WAVE64-NEXT: .cfi_undefined 2569 +; WAVE64-NEXT: .cfi_undefined 2570 +; WAVE64-NEXT: .cfi_undefined 2571 +; WAVE64-NEXT: .cfi_undefined 2572 +; WAVE64-NEXT: .cfi_undefined 2573 +; WAVE64-NEXT: .cfi_undefined 2574 +; WAVE64-NEXT: .cfi_undefined 2575 +; WAVE64-NEXT: .cfi_undefined 2576 +; WAVE64-NEXT: .cfi_undefined 2577 +; WAVE64-NEXT: .cfi_undefined 2578 +; WAVE64-NEXT: .cfi_undefined 2579 +; WAVE64-NEXT: .cfi_undefined 2580 +; WAVE64-NEXT: .cfi_undefined 2581 +; WAVE64-NEXT: .cfi_undefined 2582 +; WAVE64-NEXT: .cfi_undefined 2583 +; WAVE64-NEXT: .cfi_undefined 2584 +; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE64-NEXT: v_mov_b32_e32 v0, exec_lo +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE64-NEXT: v_mov_b32_e32 v0, exec_hi +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_offset 17, 0 +; WAVE64-NEXT: ;;#ASMSTART +; WAVE64-NEXT: ;;#ASMEND +; WAVE64-NEXT: s_waitcnt vmcnt(0) +; WAVE64-NEXT: s_setpc_b64 s[30:31] +; +; WAVE32-LABEL: no_vgprs_to_spill_into: +; WAVE32: .Lfunc_begin4: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: .cfi_undefined 1536 +; WAVE32-NEXT: .cfi_undefined 1537 +; WAVE32-NEXT: .cfi_undefined 1538 +; WAVE32-NEXT: .cfi_undefined 1539 +; WAVE32-NEXT: .cfi_undefined 1540 +; WAVE32-NEXT: .cfi_undefined 1541 +; WAVE32-NEXT: .cfi_undefined 1542 +; WAVE32-NEXT: .cfi_undefined 1543 +; WAVE32-NEXT: .cfi_undefined 1544 +; WAVE32-NEXT: .cfi_undefined 1545 +; WAVE32-NEXT: .cfi_undefined 1546 +; WAVE32-NEXT: .cfi_undefined 1547 +; WAVE32-NEXT: .cfi_undefined 1548 +; WAVE32-NEXT: .cfi_undefined 1549 +; WAVE32-NEXT: .cfi_undefined 1550 +; WAVE32-NEXT: .cfi_undefined 1551 +; WAVE32-NEXT: .cfi_undefined 1552 +; WAVE32-NEXT: .cfi_undefined 1553 +; WAVE32-NEXT: .cfi_undefined 1554 +; WAVE32-NEXT: .cfi_undefined 1555 +; WAVE32-NEXT: .cfi_undefined 1556 +; WAVE32-NEXT: .cfi_undefined 1557 +; WAVE32-NEXT: .cfi_undefined 1558 +; WAVE32-NEXT: .cfi_undefined 1559 +; WAVE32-NEXT: .cfi_undefined 1560 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: s_xor_saveexec_b32 s4, -1 +; WAVE32-NEXT: buffer_store_dword v25, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_offset 1561, 0 +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s4 +; WAVE32-NEXT: v_writelane_b32 v25, exec_lo, 0 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1, 1561, 0, 32 +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: s_xor_saveexec_b32 s4, -1 +; WAVE32-NEXT: buffer_load_dword v25, off, s[0:3], s32 ; 4-byte Folded Reload +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s4 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_setpc_b64 s[30:31] + call void asm sideeffect "", + "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9} + ,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19} + ,~{v20},~{v21},~{v22},~{v23},~{v24}"() + + ret void +} + +; Check that the FP and EXEC needs to be spilled to memory, even though +; we have reserved VGPR but there are no available free lanes. +define void @callee_need_to_spill_fp_exec_to_memory() #2 { +; WAVE64-LABEL: callee_need_to_spill_fp_exec_to_memory: +; WAVE64: .Lfunc_begin5: +; WAVE64-NEXT: .cfi_startproc +; WAVE64-NEXT: ; %bb.0: +; WAVE64-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE64-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE64-NEXT: .cfi_undefined 2560 +; WAVE64-NEXT: .cfi_undefined 2561 +; WAVE64-NEXT: .cfi_undefined 2562 +; WAVE64-NEXT: .cfi_undefined 2563 +; WAVE64-NEXT: .cfi_undefined 2564 +; WAVE64-NEXT: .cfi_undefined 2565 +; WAVE64-NEXT: .cfi_undefined 2566 +; WAVE64-NEXT: .cfi_undefined 2567 +; WAVE64-NEXT: .cfi_undefined 2568 +; WAVE64-NEXT: .cfi_undefined 2569 +; WAVE64-NEXT: .cfi_undefined 2570 +; WAVE64-NEXT: .cfi_undefined 2571 +; WAVE64-NEXT: .cfi_undefined 2572 +; WAVE64-NEXT: .cfi_undefined 2573 +; WAVE64-NEXT: .cfi_undefined 2574 +; WAVE64-NEXT: .cfi_undefined 2575 +; WAVE64-NEXT: .cfi_undefined 2576 +; WAVE64-NEXT: .cfi_undefined 2577 +; WAVE64-NEXT: .cfi_undefined 2578 +; WAVE64-NEXT: .cfi_undefined 2579 +; WAVE64-NEXT: .cfi_undefined 2580 +; WAVE64-NEXT: .cfi_undefined 2581 +; WAVE64-NEXT: .cfi_undefined 2582 +; WAVE64-NEXT: .cfi_undefined 2583 +; WAVE64-NEXT: .cfi_undefined 2584 +; WAVE64-NEXT: .cfi_undefined 2585 +; WAVE64-NEXT: .cfi_undefined 2586 +; WAVE64-NEXT: .cfi_undefined 2587 +; WAVE64-NEXT: .cfi_undefined 2588 +; WAVE64-NEXT: .cfi_undefined 2589 +; WAVE64-NEXT: .cfi_undefined 2590 +; WAVE64-NEXT: .cfi_undefined 2591 +; WAVE64-NEXT: .cfi_undefined 2592 +; WAVE64-NEXT: .cfi_undefined 2593 +; WAVE64-NEXT: .cfi_undefined 2594 +; WAVE64-NEXT: .cfi_undefined 2595 +; WAVE64-NEXT: .cfi_undefined 2596 +; WAVE64-NEXT: .cfi_undefined 2597 +; WAVE64-NEXT: .cfi_undefined 2598 +; WAVE64-NEXT: .cfi_undefined 2599 +; WAVE64-NEXT: .cfi_undefined 2608 +; WAVE64-NEXT: .cfi_undefined 2609 +; WAVE64-NEXT: .cfi_undefined 2610 +; WAVE64-NEXT: .cfi_undefined 2611 +; WAVE64-NEXT: .cfi_undefined 2612 +; WAVE64-NEXT: .cfi_undefined 2613 +; WAVE64-NEXT: .cfi_undefined 2614 +; WAVE64-NEXT: .cfi_undefined 2615 +; WAVE64-NEXT: .cfi_undefined 2624 +; WAVE64-NEXT: .cfi_undefined 2625 +; WAVE64-NEXT: .cfi_undefined 2626 +; WAVE64-NEXT: .cfi_undefined 2627 +; WAVE64-NEXT: .cfi_undefined 2628 +; WAVE64-NEXT: .cfi_undefined 2629 +; WAVE64-NEXT: .cfi_undefined 2630 +; WAVE64-NEXT: .cfi_undefined 2631 +; WAVE64-NEXT: .cfi_undefined 2640 +; WAVE64-NEXT: .cfi_undefined 2641 +; WAVE64-NEXT: .cfi_undefined 2642 +; WAVE64-NEXT: .cfi_undefined 2643 +; WAVE64-NEXT: .cfi_undefined 2644 +; WAVE64-NEXT: .cfi_undefined 2645 +; WAVE64-NEXT: .cfi_undefined 2646 +; WAVE64-NEXT: .cfi_undefined 2647 +; WAVE64-NEXT: .cfi_undefined 2656 +; WAVE64-NEXT: .cfi_undefined 2657 +; WAVE64-NEXT: .cfi_undefined 2658 +; WAVE64-NEXT: .cfi_undefined 2659 +; WAVE64-NEXT: .cfi_undefined 2660 +; WAVE64-NEXT: .cfi_undefined 2661 +; WAVE64-NEXT: .cfi_undefined 2662 +; WAVE64-NEXT: .cfi_undefined 2663 +; WAVE64-NEXT: .cfi_undefined 2672 +; WAVE64-NEXT: .cfi_undefined 2673 +; WAVE64-NEXT: .cfi_undefined 2674 +; WAVE64-NEXT: .cfi_undefined 2675 +; WAVE64-NEXT: .cfi_undefined 2676 +; WAVE64-NEXT: .cfi_undefined 2677 +; WAVE64-NEXT: .cfi_undefined 2678 +; WAVE64-NEXT: .cfi_undefined 2679 +; WAVE64-NEXT: .cfi_undefined 2688 +; WAVE64-NEXT: .cfi_undefined 2689 +; WAVE64-NEXT: .cfi_undefined 36 +; WAVE64-NEXT: .cfi_undefined 37 +; WAVE64-NEXT: .cfi_undefined 38 +; WAVE64-NEXT: .cfi_undefined 39 +; WAVE64-NEXT: .cfi_undefined 40 +; WAVE64-NEXT: .cfi_undefined 41 +; WAVE64-NEXT: .cfi_undefined 42 +; WAVE64-NEXT: .cfi_undefined 43 +; WAVE64-NEXT: .cfi_undefined 44 +; WAVE64-NEXT: .cfi_undefined 45 +; WAVE64-NEXT: .cfi_undefined 46 +; WAVE64-NEXT: .cfi_undefined 47 +; WAVE64-NEXT: .cfi_undefined 48 +; WAVE64-NEXT: .cfi_undefined 49 +; WAVE64-NEXT: .cfi_undefined 50 +; WAVE64-NEXT: .cfi_undefined 51 +; WAVE64-NEXT: .cfi_undefined 52 +; WAVE64-NEXT: .cfi_undefined 53 +; WAVE64-NEXT: .cfi_undefined 54 +; WAVE64-NEXT: .cfi_undefined 55 +; WAVE64-NEXT: .cfi_undefined 56 +; WAVE64-NEXT: .cfi_undefined 57 +; WAVE64-NEXT: .cfi_undefined 58 +; WAVE64-NEXT: .cfi_undefined 59 +; WAVE64-NEXT: .cfi_undefined 60 +; WAVE64-NEXT: .cfi_undefined 61 +; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE64-NEXT: s_mov_b32 s40, s33 +; WAVE64-NEXT: .cfi_register 65, 72 +; WAVE64-NEXT: s_mov_b32 s33, s32 +; WAVE64-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; WAVE64-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_offset 2599, 12288 +; WAVE64-NEXT: s_mov_b64 exec, s[4:5] +; WAVE64-NEXT: v_writelane_b32 v39, exec_lo, 32 +; WAVE64-NEXT: v_writelane_b32 v39, exec_hi, 33 +; WAVE64-NEXT: .cfi_llvm_vector_registers 17, 2599, 32, 32, 2599, 33, 32 +; WAVE64-NEXT: .cfi_def_cfa_register 65 +; WAVE64-NEXT: s_addk_i32 s32, 0x3200 +; WAVE64-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 12032 +; WAVE64-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 11776 +; WAVE64-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2602, 32, 17, 64, 11520 +; WAVE64-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2603, 32, 17, 64, 11264 +; WAVE64-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2604, 32, 17, 64, 11008 +; WAVE64-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2605, 32, 17, 64, 10752 +; WAVE64-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2606, 32, 17, 64, 10496 +; WAVE64-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2607, 32, 17, 64, 10240 +; WAVE64-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2616, 32, 17, 64, 9984 +; WAVE64-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2617, 32, 17, 64, 9728 +; WAVE64-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2618, 32, 17, 64, 9472 +; WAVE64-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2619, 32, 17, 64, 9216 +; WAVE64-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2620, 32, 17, 64, 8960 +; WAVE64-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2621, 32, 17, 64, 8704 +; WAVE64-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2622, 32, 17, 64, 8448 +; WAVE64-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2623, 32, 17, 64, 8192 +; WAVE64-NEXT: buffer_store_dword v72, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2632, 32, 17, 64, 7936 +; WAVE64-NEXT: buffer_store_dword v73, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2633, 32, 17, 64, 7680 +; WAVE64-NEXT: buffer_store_dword v74, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2634, 32, 17, 64, 7424 +; WAVE64-NEXT: buffer_store_dword v75, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2635, 32, 17, 64, 7168 +; WAVE64-NEXT: buffer_store_dword v76, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2636, 32, 17, 64, 6912 +; WAVE64-NEXT: buffer_store_dword v77, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2637, 32, 17, 64, 6656 +; WAVE64-NEXT: buffer_store_dword v78, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2638, 32, 17, 64, 6400 +; WAVE64-NEXT: buffer_store_dword v79, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2639, 32, 17, 64, 6144 +; WAVE64-NEXT: buffer_store_dword v88, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2648, 32, 17, 64, 5888 +; WAVE64-NEXT: buffer_store_dword v89, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2649, 32, 17, 64, 5632 +; WAVE64-NEXT: buffer_store_dword v90, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2650, 32, 17, 64, 5376 +; WAVE64-NEXT: buffer_store_dword v91, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2651, 32, 17, 64, 5120 +; WAVE64-NEXT: buffer_store_dword v92, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2652, 32, 17, 64, 4864 +; WAVE64-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2653, 32, 17, 64, 4608 +; WAVE64-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2654, 32, 17, 64, 4352 +; WAVE64-NEXT: buffer_store_dword v95, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2655, 32, 17, 64, 4096 +; WAVE64-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2664, 32, 17, 64, 3840 +; WAVE64-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2665, 32, 17, 64, 3584 +; WAVE64-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2666, 32, 17, 64, 3328 +; WAVE64-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2667, 32, 17, 64, 3072 +; WAVE64-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2668, 32, 17, 64, 2816 +; WAVE64-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2669, 32, 17, 64, 2560 +; WAVE64-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2670, 32, 17, 64, 2304 +; WAVE64-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2671, 32, 17, 64, 2048 +; WAVE64-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2680, 32, 17, 64, 1792 +; WAVE64-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2681, 32, 17, 64, 1536 +; WAVE64-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2682, 32, 17, 64, 1280 +; WAVE64-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2683, 32, 17, 64, 1024 +; WAVE64-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2684, 32, 17, 64, 768 +; WAVE64-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2685, 32, 17, 64, 512 +; WAVE64-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2686, 32, 17, 64, 256 +; WAVE64-NEXT: buffer_store_dword v127, off, s[0:3], s33 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2687, 32, 17, 64, 0 +; WAVE64-NEXT: v_writelane_b32 v39, s34, 0 +; WAVE64-NEXT: .cfi_llvm_vector_registers 66, 2599, 0, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s35, 1 +; WAVE64-NEXT: .cfi_llvm_vector_registers 67, 2599, 1, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s36, 2 +; WAVE64-NEXT: .cfi_llvm_vector_registers 68, 2599, 2, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s37, 3 +; WAVE64-NEXT: .cfi_llvm_vector_registers 69, 2599, 3, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s38, 4 +; WAVE64-NEXT: .cfi_llvm_vector_registers 70, 2599, 4, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s39, 5 +; WAVE64-NEXT: .cfi_llvm_vector_registers 71, 2599, 5, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s48, 6 +; WAVE64-NEXT: .cfi_llvm_vector_registers 80, 2599, 6, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s49, 7 +; WAVE64-NEXT: .cfi_llvm_vector_registers 81, 2599, 7, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s50, 8 +; WAVE64-NEXT: .cfi_llvm_vector_registers 82, 2599, 8, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s51, 9 +; WAVE64-NEXT: .cfi_llvm_vector_registers 83, 2599, 9, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s52, 10 +; WAVE64-NEXT: .cfi_llvm_vector_registers 84, 2599, 10, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s53, 11 +; WAVE64-NEXT: .cfi_llvm_vector_registers 85, 2599, 11, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s54, 12 +; WAVE64-NEXT: .cfi_llvm_vector_registers 86, 2599, 12, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s55, 13 +; WAVE64-NEXT: .cfi_llvm_vector_registers 87, 2599, 13, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s64, 14 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1088, 2599, 14, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s65, 15 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1089, 2599, 15, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s66, 16 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1090, 2599, 16, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s67, 17 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1091, 2599, 17, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s68, 18 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1092, 2599, 18, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s69, 19 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1093, 2599, 19, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s70, 20 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1094, 2599, 20, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s71, 21 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1095, 2599, 21, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s80, 22 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1104, 2599, 22, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s81, 23 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1105, 2599, 23, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s82, 24 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1106, 2599, 24, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s83, 25 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1107, 2599, 25, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s84, 26 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1108, 2599, 26, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s85, 27 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1109, 2599, 27, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s86, 28 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1110, 2599, 28, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s87, 29 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1111, 2599, 29, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s96, 30 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1120, 2599, 30, 32 +; WAVE64-NEXT: v_writelane_b32 v39, s97, 31 +; WAVE64-NEXT: .cfi_llvm_vector_registers 1121, 2599, 31, 32 +; WAVE64-NEXT: ;;#ASMSTART +; WAVE64-NEXT: ; clobber nonpreserved and 32 CSR SGPRs +; WAVE64-NEXT: ;;#ASMEND +; WAVE64-NEXT: ;;#ASMSTART +; WAVE64-NEXT: ; clobber all VGPRs except v39 +; WAVE64-NEXT: ;;#ASMEND +; WAVE64-NEXT: buffer_load_dword v127, off, s[0:3], s33 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v126, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v125, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v124, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v123, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v122, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v121, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v120, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v111, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v110, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v109, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v108, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v107, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v106, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v105, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v104, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v95, off, s[0:3], s33 offset:64 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v94, off, s[0:3], s33 offset:68 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v93, off, s[0:3], s33 offset:72 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v92, off, s[0:3], s33 offset:76 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v91, off, s[0:3], s33 offset:80 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v90, off, s[0:3], s33 offset:84 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v89, off, s[0:3], s33 offset:88 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v88, off, s[0:3], s33 offset:92 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v79, off, s[0:3], s33 offset:96 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v78, off, s[0:3], s33 offset:100 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v77, off, s[0:3], s33 offset:104 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v76, off, s[0:3], s33 offset:108 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v75, off, s[0:3], s33 offset:112 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v74, off, s[0:3], s33 offset:116 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v73, off, s[0:3], s33 offset:120 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v72, off, s[0:3], s33 offset:124 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v63, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:132 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:136 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:140 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:144 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:148 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:152 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:156 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:160 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:164 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:168 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:172 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:176 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:180 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:184 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:188 ; 4-byte Folded Reload +; WAVE64-NEXT: v_readlane_b32 s97, v39, 31 +; WAVE64-NEXT: v_readlane_b32 s96, v39, 30 +; WAVE64-NEXT: v_readlane_b32 s87, v39, 29 +; WAVE64-NEXT: v_readlane_b32 s86, v39, 28 +; WAVE64-NEXT: v_readlane_b32 s85, v39, 27 +; WAVE64-NEXT: v_readlane_b32 s84, v39, 26 +; WAVE64-NEXT: v_readlane_b32 s83, v39, 25 +; WAVE64-NEXT: v_readlane_b32 s82, v39, 24 +; WAVE64-NEXT: v_readlane_b32 s81, v39, 23 +; WAVE64-NEXT: v_readlane_b32 s80, v39, 22 +; WAVE64-NEXT: v_readlane_b32 s71, v39, 21 +; WAVE64-NEXT: v_readlane_b32 s70, v39, 20 +; WAVE64-NEXT: v_readlane_b32 s69, v39, 19 +; WAVE64-NEXT: v_readlane_b32 s68, v39, 18 +; WAVE64-NEXT: v_readlane_b32 s67, v39, 17 +; WAVE64-NEXT: v_readlane_b32 s66, v39, 16 +; WAVE64-NEXT: v_readlane_b32 s65, v39, 15 +; WAVE64-NEXT: v_readlane_b32 s64, v39, 14 +; WAVE64-NEXT: v_readlane_b32 s55, v39, 13 +; WAVE64-NEXT: v_readlane_b32 s54, v39, 12 +; WAVE64-NEXT: v_readlane_b32 s53, v39, 11 +; WAVE64-NEXT: v_readlane_b32 s52, v39, 10 +; WAVE64-NEXT: v_readlane_b32 s51, v39, 9 +; WAVE64-NEXT: v_readlane_b32 s50, v39, 8 +; WAVE64-NEXT: v_readlane_b32 s49, v39, 7 +; WAVE64-NEXT: v_readlane_b32 s48, v39, 6 +; WAVE64-NEXT: v_readlane_b32 s39, v39, 5 +; WAVE64-NEXT: v_readlane_b32 s38, v39, 4 +; WAVE64-NEXT: v_readlane_b32 s37, v39, 3 +; WAVE64-NEXT: v_readlane_b32 s36, v39, 2 +; WAVE64-NEXT: v_readlane_b32 s35, v39, 1 +; WAVE64-NEXT: v_readlane_b32 s34, v39, 0 +; WAVE64-NEXT: s_mov_b32 s32, s33 +; WAVE64-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; WAVE64-NEXT: buffer_load_dword v39, off, s[0:3], s33 offset:192 ; 4-byte Folded Reload +; WAVE64-NEXT: s_mov_b64 exec, s[4:5] +; WAVE64-NEXT: .cfi_def_cfa_register 64 +; WAVE64-NEXT: s_mov_b32 s33, s40 +; WAVE64-NEXT: s_waitcnt vmcnt(0) +; WAVE64-NEXT: s_setpc_b64 s[30:31] +; +; WAVE32-LABEL: callee_need_to_spill_fp_exec_to_memory: +; WAVE32: .Lfunc_begin5: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: .cfi_undefined 1536 +; WAVE32-NEXT: .cfi_undefined 1537 +; WAVE32-NEXT: .cfi_undefined 1538 +; WAVE32-NEXT: .cfi_undefined 1539 +; WAVE32-NEXT: .cfi_undefined 1540 +; WAVE32-NEXT: .cfi_undefined 1541 +; WAVE32-NEXT: .cfi_undefined 1542 +; WAVE32-NEXT: .cfi_undefined 1543 +; WAVE32-NEXT: .cfi_undefined 1544 +; WAVE32-NEXT: .cfi_undefined 1545 +; WAVE32-NEXT: .cfi_undefined 1546 +; WAVE32-NEXT: .cfi_undefined 1547 +; WAVE32-NEXT: .cfi_undefined 1548 +; WAVE32-NEXT: .cfi_undefined 1549 +; WAVE32-NEXT: .cfi_undefined 1550 +; WAVE32-NEXT: .cfi_undefined 1551 +; WAVE32-NEXT: .cfi_undefined 1552 +; WAVE32-NEXT: .cfi_undefined 1553 +; WAVE32-NEXT: .cfi_undefined 1554 +; WAVE32-NEXT: .cfi_undefined 1555 +; WAVE32-NEXT: .cfi_undefined 1556 +; WAVE32-NEXT: .cfi_undefined 1557 +; WAVE32-NEXT: .cfi_undefined 1558 +; WAVE32-NEXT: .cfi_undefined 1559 +; WAVE32-NEXT: .cfi_undefined 1560 +; WAVE32-NEXT: .cfi_undefined 1561 +; WAVE32-NEXT: .cfi_undefined 1562 +; WAVE32-NEXT: .cfi_undefined 1563 +; WAVE32-NEXT: .cfi_undefined 1564 +; WAVE32-NEXT: .cfi_undefined 1565 +; WAVE32-NEXT: .cfi_undefined 1566 +; WAVE32-NEXT: .cfi_undefined 1567 +; WAVE32-NEXT: .cfi_undefined 1568 +; WAVE32-NEXT: .cfi_undefined 1569 +; WAVE32-NEXT: .cfi_undefined 1570 +; WAVE32-NEXT: .cfi_undefined 1571 +; WAVE32-NEXT: .cfi_undefined 1572 +; WAVE32-NEXT: .cfi_undefined 1573 +; WAVE32-NEXT: .cfi_undefined 1574 +; WAVE32-NEXT: .cfi_undefined 1575 +; WAVE32-NEXT: .cfi_undefined 1584 +; WAVE32-NEXT: .cfi_undefined 1585 +; WAVE32-NEXT: .cfi_undefined 1586 +; WAVE32-NEXT: .cfi_undefined 1587 +; WAVE32-NEXT: .cfi_undefined 1588 +; WAVE32-NEXT: .cfi_undefined 1589 +; WAVE32-NEXT: .cfi_undefined 1590 +; WAVE32-NEXT: .cfi_undefined 1591 +; WAVE32-NEXT: .cfi_undefined 1600 +; WAVE32-NEXT: .cfi_undefined 1601 +; WAVE32-NEXT: .cfi_undefined 1602 +; WAVE32-NEXT: .cfi_undefined 1603 +; WAVE32-NEXT: .cfi_undefined 1604 +; WAVE32-NEXT: .cfi_undefined 1605 +; WAVE32-NEXT: .cfi_undefined 1606 +; WAVE32-NEXT: .cfi_undefined 1607 +; WAVE32-NEXT: .cfi_undefined 1616 +; WAVE32-NEXT: .cfi_undefined 1617 +; WAVE32-NEXT: .cfi_undefined 1618 +; WAVE32-NEXT: .cfi_undefined 1619 +; WAVE32-NEXT: .cfi_undefined 1620 +; WAVE32-NEXT: .cfi_undefined 1621 +; WAVE32-NEXT: .cfi_undefined 1622 +; WAVE32-NEXT: .cfi_undefined 1623 +; WAVE32-NEXT: .cfi_undefined 1632 +; WAVE32-NEXT: .cfi_undefined 1633 +; WAVE32-NEXT: .cfi_undefined 1634 +; WAVE32-NEXT: .cfi_undefined 1635 +; WAVE32-NEXT: .cfi_undefined 1636 +; WAVE32-NEXT: .cfi_undefined 1637 +; WAVE32-NEXT: .cfi_undefined 1638 +; WAVE32-NEXT: .cfi_undefined 1639 +; WAVE32-NEXT: .cfi_undefined 1648 +; WAVE32-NEXT: .cfi_undefined 1649 +; WAVE32-NEXT: .cfi_undefined 1650 +; WAVE32-NEXT: .cfi_undefined 1651 +; WAVE32-NEXT: .cfi_undefined 1652 +; WAVE32-NEXT: .cfi_undefined 1653 +; WAVE32-NEXT: .cfi_undefined 1654 +; WAVE32-NEXT: .cfi_undefined 1655 +; WAVE32-NEXT: .cfi_undefined 1664 +; WAVE32-NEXT: .cfi_undefined 1665 +; WAVE32-NEXT: .cfi_undefined 36 +; WAVE32-NEXT: .cfi_undefined 37 +; WAVE32-NEXT: .cfi_undefined 38 +; WAVE32-NEXT: .cfi_undefined 39 +; WAVE32-NEXT: .cfi_undefined 40 +; WAVE32-NEXT: .cfi_undefined 41 +; WAVE32-NEXT: .cfi_undefined 42 +; WAVE32-NEXT: .cfi_undefined 43 +; WAVE32-NEXT: .cfi_undefined 44 +; WAVE32-NEXT: .cfi_undefined 45 +; WAVE32-NEXT: .cfi_undefined 46 +; WAVE32-NEXT: .cfi_undefined 47 +; WAVE32-NEXT: .cfi_undefined 48 +; WAVE32-NEXT: .cfi_undefined 49 +; WAVE32-NEXT: .cfi_undefined 50 +; WAVE32-NEXT: .cfi_undefined 51 +; WAVE32-NEXT: .cfi_undefined 52 +; WAVE32-NEXT: .cfi_undefined 53 +; WAVE32-NEXT: .cfi_undefined 54 +; WAVE32-NEXT: .cfi_undefined 55 +; WAVE32-NEXT: .cfi_undefined 56 +; WAVE32-NEXT: .cfi_undefined 57 +; WAVE32-NEXT: .cfi_undefined 58 +; WAVE32-NEXT: .cfi_undefined 59 +; WAVE32-NEXT: .cfi_undefined 60 +; WAVE32-NEXT: .cfi_undefined 61 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: s_mov_b32 s40, s33 +; WAVE32-NEXT: .cfi_register 65, 72 +; WAVE32-NEXT: s_mov_b32 s33, s32 +; WAVE32-NEXT: s_xor_saveexec_b32 s4, -1 +; WAVE32-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_offset 1575, 6144 +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s4 +; WAVE32-NEXT: v_mov_b32_e32 v0, exec_lo +; WAVE32-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_offset 1, 6272 +; WAVE32-NEXT: .cfi_def_cfa_register 65 +; WAVE32-NEXT: s_addk_i32 s32, 0x1980 +; WAVE32-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1576, 32, 1, 32, 6016 +; WAVE32-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1577, 32, 1, 32, 5888 +; WAVE32-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1578, 32, 1, 32, 5760 +; WAVE32-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1579, 32, 1, 32, 5632 +; WAVE32-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1580, 32, 1, 32, 5504 +; WAVE32-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1581, 32, 1, 32, 5376 +; WAVE32-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1582, 32, 1, 32, 5248 +; WAVE32-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1583, 32, 1, 32, 5120 +; WAVE32-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1592, 32, 1, 32, 4992 +; WAVE32-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1593, 32, 1, 32, 4864 +; WAVE32-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1594, 32, 1, 32, 4736 +; WAVE32-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1595, 32, 1, 32, 4608 +; WAVE32-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1596, 32, 1, 32, 4480 +; WAVE32-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1597, 32, 1, 32, 4352 +; WAVE32-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1598, 32, 1, 32, 4224 +; WAVE32-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1599, 32, 1, 32, 4096 +; WAVE32-NEXT: buffer_store_dword v72, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1608, 32, 1, 32, 3968 +; WAVE32-NEXT: buffer_store_dword v73, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1609, 32, 1, 32, 3840 +; WAVE32-NEXT: buffer_store_dword v74, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1610, 32, 1, 32, 3712 +; WAVE32-NEXT: buffer_store_dword v75, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1611, 32, 1, 32, 3584 +; WAVE32-NEXT: buffer_store_dword v76, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1612, 32, 1, 32, 3456 +; WAVE32-NEXT: buffer_store_dword v77, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1613, 32, 1, 32, 3328 +; WAVE32-NEXT: buffer_store_dword v78, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1614, 32, 1, 32, 3200 +; WAVE32-NEXT: buffer_store_dword v79, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1615, 32, 1, 32, 3072 +; WAVE32-NEXT: buffer_store_dword v88, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1624, 32, 1, 32, 2944 +; WAVE32-NEXT: buffer_store_dword v89, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1625, 32, 1, 32, 2816 +; WAVE32-NEXT: buffer_store_dword v90, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1626, 32, 1, 32, 2688 +; WAVE32-NEXT: buffer_store_dword v91, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1627, 32, 1, 32, 2560 +; WAVE32-NEXT: buffer_store_dword v92, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1628, 32, 1, 32, 2432 +; WAVE32-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1629, 32, 1, 32, 2304 +; WAVE32-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1630, 32, 1, 32, 2176 +; WAVE32-NEXT: buffer_store_dword v95, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1631, 32, 1, 32, 2048 +; WAVE32-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1640, 32, 1, 32, 1920 +; WAVE32-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1641, 32, 1, 32, 1792 +; WAVE32-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1642, 32, 1, 32, 1664 +; WAVE32-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1643, 32, 1, 32, 1536 +; WAVE32-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1644, 32, 1, 32, 1408 +; WAVE32-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1645, 32, 1, 32, 1280 +; WAVE32-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1646, 32, 1, 32, 1152 +; WAVE32-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1647, 32, 1, 32, 1024 +; WAVE32-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1656, 32, 1, 32, 896 +; WAVE32-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1657, 32, 1, 32, 768 +; WAVE32-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1658, 32, 1, 32, 640 +; WAVE32-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1659, 32, 1, 32, 512 +; WAVE32-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1660, 32, 1, 32, 384 +; WAVE32-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1661, 32, 1, 32, 256 +; WAVE32-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1662, 32, 1, 32, 128 +; WAVE32-NEXT: buffer_store_dword v127, off, s[0:3], s33 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1663, 32, 1, 32, 0 +; WAVE32-NEXT: v_writelane_b32 v39, s34, 0 +; WAVE32-NEXT: .cfi_llvm_vector_registers 66, 1575, 0, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s35, 1 +; WAVE32-NEXT: .cfi_llvm_vector_registers 67, 1575, 1, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s36, 2 +; WAVE32-NEXT: .cfi_llvm_vector_registers 68, 1575, 2, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s37, 3 +; WAVE32-NEXT: .cfi_llvm_vector_registers 69, 1575, 3, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s38, 4 +; WAVE32-NEXT: .cfi_llvm_vector_registers 70, 1575, 4, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s39, 5 +; WAVE32-NEXT: .cfi_llvm_vector_registers 71, 1575, 5, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s48, 6 +; WAVE32-NEXT: .cfi_llvm_vector_registers 80, 1575, 6, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s49, 7 +; WAVE32-NEXT: .cfi_llvm_vector_registers 81, 1575, 7, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s50, 8 +; WAVE32-NEXT: .cfi_llvm_vector_registers 82, 1575, 8, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s51, 9 +; WAVE32-NEXT: .cfi_llvm_vector_registers 83, 1575, 9, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s52, 10 +; WAVE32-NEXT: .cfi_llvm_vector_registers 84, 1575, 10, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s53, 11 +; WAVE32-NEXT: .cfi_llvm_vector_registers 85, 1575, 11, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s54, 12 +; WAVE32-NEXT: .cfi_llvm_vector_registers 86, 1575, 12, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s55, 13 +; WAVE32-NEXT: .cfi_llvm_vector_registers 87, 1575, 13, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s64, 14 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1088, 1575, 14, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s65, 15 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1089, 1575, 15, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s66, 16 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1090, 1575, 16, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s67, 17 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1091, 1575, 17, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s68, 18 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1092, 1575, 18, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s69, 19 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1093, 1575, 19, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s70, 20 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1094, 1575, 20, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s71, 21 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1095, 1575, 21, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s80, 22 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1104, 1575, 22, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s81, 23 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1105, 1575, 23, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s82, 24 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1106, 1575, 24, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s83, 25 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1107, 1575, 25, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s84, 26 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1108, 1575, 26, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s85, 27 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1109, 1575, 27, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s86, 28 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1110, 1575, 28, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s87, 29 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1111, 1575, 29, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s96, 30 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1120, 1575, 30, 32 +; WAVE32-NEXT: v_writelane_b32 v39, s97, 31 +; WAVE32-NEXT: .cfi_llvm_vector_registers 1121, 1575, 31, 32 +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber nonpreserved and 32 CSR SGPRs +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber all VGPRs except v39 +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: s_clause 0x2f +; WAVE32-NEXT: buffer_load_dword v127, off, s[0:3], s33 +; WAVE32-NEXT: buffer_load_dword v126, off, s[0:3], s33 offset:4 +; WAVE32-NEXT: buffer_load_dword v125, off, s[0:3], s33 offset:8 +; WAVE32-NEXT: buffer_load_dword v124, off, s[0:3], s33 offset:12 +; WAVE32-NEXT: buffer_load_dword v123, off, s[0:3], s33 offset:16 +; WAVE32-NEXT: buffer_load_dword v122, off, s[0:3], s33 offset:20 +; WAVE32-NEXT: buffer_load_dword v121, off, s[0:3], s33 offset:24 +; WAVE32-NEXT: buffer_load_dword v120, off, s[0:3], s33 offset:28 +; WAVE32-NEXT: buffer_load_dword v111, off, s[0:3], s33 offset:32 +; WAVE32-NEXT: buffer_load_dword v110, off, s[0:3], s33 offset:36 +; WAVE32-NEXT: buffer_load_dword v109, off, s[0:3], s33 offset:40 +; WAVE32-NEXT: buffer_load_dword v108, off, s[0:3], s33 offset:44 +; WAVE32-NEXT: buffer_load_dword v107, off, s[0:3], s33 offset:48 +; WAVE32-NEXT: buffer_load_dword v106, off, s[0:3], s33 offset:52 +; WAVE32-NEXT: buffer_load_dword v105, off, s[0:3], s33 offset:56 +; WAVE32-NEXT: buffer_load_dword v104, off, s[0:3], s33 offset:60 +; WAVE32-NEXT: buffer_load_dword v95, off, s[0:3], s33 offset:64 +; WAVE32-NEXT: buffer_load_dword v94, off, s[0:3], s33 offset:68 +; WAVE32-NEXT: buffer_load_dword v93, off, s[0:3], s33 offset:72 +; WAVE32-NEXT: buffer_load_dword v92, off, s[0:3], s33 offset:76 +; WAVE32-NEXT: buffer_load_dword v91, off, s[0:3], s33 offset:80 +; WAVE32-NEXT: buffer_load_dword v90, off, s[0:3], s33 offset:84 +; WAVE32-NEXT: buffer_load_dword v89, off, s[0:3], s33 offset:88 +; WAVE32-NEXT: buffer_load_dword v88, off, s[0:3], s33 offset:92 +; WAVE32-NEXT: buffer_load_dword v79, off, s[0:3], s33 offset:96 +; WAVE32-NEXT: buffer_load_dword v78, off, s[0:3], s33 offset:100 +; WAVE32-NEXT: buffer_load_dword v77, off, s[0:3], s33 offset:104 +; WAVE32-NEXT: buffer_load_dword v76, off, s[0:3], s33 offset:108 +; WAVE32-NEXT: buffer_load_dword v75, off, s[0:3], s33 offset:112 +; WAVE32-NEXT: buffer_load_dword v74, off, s[0:3], s33 offset:116 +; WAVE32-NEXT: buffer_load_dword v73, off, s[0:3], s33 offset:120 +; WAVE32-NEXT: buffer_load_dword v72, off, s[0:3], s33 offset:124 +; WAVE32-NEXT: buffer_load_dword v63, off, s[0:3], s33 offset:128 +; WAVE32-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:132 +; WAVE32-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:136 +; WAVE32-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:140 +; WAVE32-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:144 +; WAVE32-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:148 +; WAVE32-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:152 +; WAVE32-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:156 +; WAVE32-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:160 +; WAVE32-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:164 +; WAVE32-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:168 +; WAVE32-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:172 +; WAVE32-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:176 +; WAVE32-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:180 +; WAVE32-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:184 +; WAVE32-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:188 +; WAVE32-NEXT: v_readlane_b32 s97, v39, 31 +; WAVE32-NEXT: v_readlane_b32 s96, v39, 30 +; WAVE32-NEXT: v_readlane_b32 s87, v39, 29 +; WAVE32-NEXT: v_readlane_b32 s86, v39, 28 +; WAVE32-NEXT: v_readlane_b32 s85, v39, 27 +; WAVE32-NEXT: v_readlane_b32 s84, v39, 26 +; WAVE32-NEXT: v_readlane_b32 s83, v39, 25 +; WAVE32-NEXT: v_readlane_b32 s82, v39, 24 +; WAVE32-NEXT: v_readlane_b32 s81, v39, 23 +; WAVE32-NEXT: v_readlane_b32 s80, v39, 22 +; WAVE32-NEXT: v_readlane_b32 s71, v39, 21 +; WAVE32-NEXT: v_readlane_b32 s70, v39, 20 +; WAVE32-NEXT: v_readlane_b32 s69, v39, 19 +; WAVE32-NEXT: v_readlane_b32 s68, v39, 18 +; WAVE32-NEXT: v_readlane_b32 s67, v39, 17 +; WAVE32-NEXT: v_readlane_b32 s66, v39, 16 +; WAVE32-NEXT: v_readlane_b32 s65, v39, 15 +; WAVE32-NEXT: v_readlane_b32 s64, v39, 14 +; WAVE32-NEXT: v_readlane_b32 s55, v39, 13 +; WAVE32-NEXT: v_readlane_b32 s54, v39, 12 +; WAVE32-NEXT: v_readlane_b32 s53, v39, 11 +; WAVE32-NEXT: v_readlane_b32 s52, v39, 10 +; WAVE32-NEXT: v_readlane_b32 s51, v39, 9 +; WAVE32-NEXT: v_readlane_b32 s50, v39, 8 +; WAVE32-NEXT: v_readlane_b32 s49, v39, 7 +; WAVE32-NEXT: v_readlane_b32 s48, v39, 6 +; WAVE32-NEXT: v_readlane_b32 s39, v39, 5 +; WAVE32-NEXT: v_readlane_b32 s38, v39, 4 +; WAVE32-NEXT: v_readlane_b32 s37, v39, 3 +; WAVE32-NEXT: v_readlane_b32 s36, v39, 2 +; WAVE32-NEXT: v_readlane_b32 s35, v39, 1 +; WAVE32-NEXT: v_readlane_b32 s34, v39, 0 +; WAVE32-NEXT: s_mov_b32 s32, s33 +; WAVE32-NEXT: s_xor_saveexec_b32 s4, -1 +; WAVE32-NEXT: buffer_load_dword v39, off, s[0:3], s33 offset:192 ; 4-byte Folded Reload +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s4 +; WAVE32-NEXT: .cfi_def_cfa_register 64 +; WAVE32-NEXT: s_mov_b32 s33, s40 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_setpc_b64 s[30:31] + call void asm sideeffect "; clobber nonpreserved and 32 CSR SGPRs", + "~{s4},~{s5},~{s6},~{s7},~{s8},~{s9} + ,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19} + ,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29} + ,~{s34},~{s35},~{s36},~{s37},~{s38},~{s39} + ,~{s48},~{s49},~{s50},~{s51},~{s52},~{s53},~{s54},~{s55},~{s64},~{s65} + ,~{s66},~{s67},~{s68},~{s69},~{s70},~{s71},~{s80},~{s81},~{s82},~{s83} + ,~{s84},~{s85},~{s86},~{s87},~{s96},~{s97} + ,~{vcc}"() + + call void asm sideeffect "; clobber all VGPRs except v39", + "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9} + ,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19} + ,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29} + ,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38} + ,~{v40},~{v41},~{v42},~{v43},~{v44},~{v45},~{v46},~{v47},~{v48},~{v49} + ,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59} + ,~{v60},~{v61},~{v62},~{v63},~{v64},~{v65},~{v66},~{v67},~{v68},~{v69} + ,~{v70},~{v71},~{v72},~{v73},~{v74},~{v75},~{v76},~{v77},~{v78},~{v79} + ,~{v80},~{v81},~{v82},~{v83},~{v84},~{v85},~{v86},~{v87},~{v88},~{v89} + ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} + ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109} + ,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119} + ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}"() + ret void +} + +define internal void @caller_needs_to_spill_pc_to_memory() #3 { +; WAVE64-LABEL: caller_needs_to_spill_pc_to_memory: +; WAVE64: .Lfunc_begin6: +; WAVE64-NEXT: .cfi_startproc +; WAVE64-NEXT: ; %bb.0: +; WAVE64-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE64-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE64-NEXT: .cfi_undefined 2560 +; WAVE64-NEXT: .cfi_undefined 2561 +; WAVE64-NEXT: .cfi_undefined 2562 +; WAVE64-NEXT: .cfi_undefined 2563 +; WAVE64-NEXT: .cfi_undefined 2564 +; WAVE64-NEXT: .cfi_undefined 2565 +; WAVE64-NEXT: .cfi_undefined 2566 +; WAVE64-NEXT: .cfi_undefined 2567 +; WAVE64-NEXT: .cfi_undefined 2568 +; WAVE64-NEXT: .cfi_undefined 2569 +; WAVE64-NEXT: .cfi_undefined 2570 +; WAVE64-NEXT: .cfi_undefined 2571 +; WAVE64-NEXT: .cfi_undefined 2572 +; WAVE64-NEXT: .cfi_undefined 2573 +; WAVE64-NEXT: .cfi_undefined 2574 +; WAVE64-NEXT: .cfi_undefined 2575 +; WAVE64-NEXT: .cfi_undefined 2576 +; WAVE64-NEXT: .cfi_undefined 2577 +; WAVE64-NEXT: .cfi_undefined 2578 +; WAVE64-NEXT: .cfi_undefined 2579 +; WAVE64-NEXT: .cfi_undefined 2580 +; WAVE64-NEXT: .cfi_undefined 2581 +; WAVE64-NEXT: .cfi_undefined 2582 +; WAVE64-NEXT: .cfi_undefined 2583 +; WAVE64-NEXT: .cfi_undefined 2584 +; WAVE64-NEXT: .cfi_undefined 2585 +; WAVE64-NEXT: .cfi_undefined 2586 +; WAVE64-NEXT: .cfi_undefined 2587 +; WAVE64-NEXT: .cfi_undefined 2588 +; WAVE64-NEXT: .cfi_undefined 2589 +; WAVE64-NEXT: .cfi_undefined 2590 +; WAVE64-NEXT: .cfi_undefined 2591 +; WAVE64-NEXT: .cfi_undefined 2592 +; WAVE64-NEXT: .cfi_undefined 2593 +; WAVE64-NEXT: .cfi_undefined 2594 +; WAVE64-NEXT: .cfi_undefined 2595 +; WAVE64-NEXT: .cfi_undefined 2596 +; WAVE64-NEXT: .cfi_undefined 2597 +; WAVE64-NEXT: .cfi_undefined 2598 +; WAVE64-NEXT: .cfi_undefined 2599 +; WAVE64-NEXT: .cfi_undefined 2608 +; WAVE64-NEXT: .cfi_undefined 2609 +; WAVE64-NEXT: .cfi_undefined 2610 +; WAVE64-NEXT: .cfi_undefined 2611 +; WAVE64-NEXT: .cfi_undefined 2612 +; WAVE64-NEXT: .cfi_undefined 2613 +; WAVE64-NEXT: .cfi_undefined 2614 +; WAVE64-NEXT: .cfi_undefined 2615 +; WAVE64-NEXT: .cfi_undefined 2624 +; WAVE64-NEXT: .cfi_undefined 2625 +; WAVE64-NEXT: .cfi_undefined 2626 +; WAVE64-NEXT: .cfi_undefined 2627 +; WAVE64-NEXT: .cfi_undefined 2628 +; WAVE64-NEXT: .cfi_undefined 2629 +; WAVE64-NEXT: .cfi_undefined 2630 +; WAVE64-NEXT: .cfi_undefined 2631 +; WAVE64-NEXT: .cfi_undefined 2640 +; WAVE64-NEXT: .cfi_undefined 2641 +; WAVE64-NEXT: .cfi_undefined 2642 +; WAVE64-NEXT: .cfi_undefined 2643 +; WAVE64-NEXT: .cfi_undefined 2644 +; WAVE64-NEXT: .cfi_undefined 2645 +; WAVE64-NEXT: .cfi_undefined 2646 +; WAVE64-NEXT: .cfi_undefined 2647 +; WAVE64-NEXT: .cfi_undefined 2656 +; WAVE64-NEXT: .cfi_undefined 2657 +; WAVE64-NEXT: .cfi_undefined 2658 +; WAVE64-NEXT: .cfi_undefined 2659 +; WAVE64-NEXT: .cfi_undefined 2660 +; WAVE64-NEXT: .cfi_undefined 2661 +; WAVE64-NEXT: .cfi_undefined 2662 +; WAVE64-NEXT: .cfi_undefined 2663 +; WAVE64-NEXT: .cfi_undefined 2672 +; WAVE64-NEXT: .cfi_undefined 2673 +; WAVE64-NEXT: .cfi_undefined 2674 +; WAVE64-NEXT: .cfi_undefined 2675 +; WAVE64-NEXT: .cfi_undefined 2676 +; WAVE64-NEXT: .cfi_undefined 2677 +; WAVE64-NEXT: .cfi_undefined 2678 +; WAVE64-NEXT: .cfi_undefined 2679 +; WAVE64-NEXT: .cfi_undefined 2688 +; WAVE64-NEXT: .cfi_undefined 2689 +; WAVE64-NEXT: .cfi_undefined 2690 +; WAVE64-NEXT: .cfi_undefined 2691 +; WAVE64-NEXT: .cfi_undefined 2692 +; WAVE64-NEXT: .cfi_undefined 2693 +; WAVE64-NEXT: .cfi_undefined 2694 +; WAVE64-NEXT: .cfi_undefined 2695 +; WAVE64-NEXT: .cfi_undefined 2704 +; WAVE64-NEXT: .cfi_undefined 2705 +; WAVE64-NEXT: .cfi_undefined 2706 +; WAVE64-NEXT: .cfi_undefined 2707 +; WAVE64-NEXT: .cfi_undefined 2708 +; WAVE64-NEXT: .cfi_undefined 2709 +; WAVE64-NEXT: .cfi_undefined 2710 +; WAVE64-NEXT: .cfi_undefined 2711 +; WAVE64-NEXT: .cfi_undefined 2720 +; WAVE64-NEXT: .cfi_undefined 2721 +; WAVE64-NEXT: .cfi_undefined 2722 +; WAVE64-NEXT: .cfi_undefined 2723 +; WAVE64-NEXT: .cfi_undefined 2724 +; WAVE64-NEXT: .cfi_undefined 2725 +; WAVE64-NEXT: .cfi_undefined 2726 +; WAVE64-NEXT: .cfi_undefined 2727 +; WAVE64-NEXT: .cfi_undefined 2736 +; WAVE64-NEXT: .cfi_undefined 2737 +; WAVE64-NEXT: .cfi_undefined 2738 +; WAVE64-NEXT: .cfi_undefined 2739 +; WAVE64-NEXT: .cfi_undefined 2740 +; WAVE64-NEXT: .cfi_undefined 2741 +; WAVE64-NEXT: .cfi_undefined 2742 +; WAVE64-NEXT: .cfi_undefined 2743 +; WAVE64-NEXT: .cfi_undefined 2752 +; WAVE64-NEXT: .cfi_undefined 2753 +; WAVE64-NEXT: .cfi_undefined 2754 +; WAVE64-NEXT: .cfi_undefined 2755 +; WAVE64-NEXT: .cfi_undefined 2756 +; WAVE64-NEXT: .cfi_undefined 2757 +; WAVE64-NEXT: .cfi_undefined 2758 +; WAVE64-NEXT: .cfi_undefined 2759 +; WAVE64-NEXT: .cfi_undefined 2768 +; WAVE64-NEXT: .cfi_undefined 2769 +; WAVE64-NEXT: .cfi_undefined 2770 +; WAVE64-NEXT: .cfi_undefined 2771 +; WAVE64-NEXT: .cfi_undefined 2772 +; WAVE64-NEXT: .cfi_undefined 2773 +; WAVE64-NEXT: .cfi_undefined 2774 +; WAVE64-NEXT: .cfi_undefined 2775 +; WAVE64-NEXT: .cfi_undefined 2784 +; WAVE64-NEXT: .cfi_undefined 2785 +; WAVE64-NEXT: .cfi_undefined 2786 +; WAVE64-NEXT: .cfi_undefined 2787 +; WAVE64-NEXT: .cfi_undefined 2788 +; WAVE64-NEXT: .cfi_undefined 2789 +; WAVE64-NEXT: .cfi_undefined 2790 +; WAVE64-NEXT: .cfi_undefined 2791 +; WAVE64-NEXT: .cfi_undefined 2800 +; WAVE64-NEXT: .cfi_undefined 2801 +; WAVE64-NEXT: .cfi_undefined 2802 +; WAVE64-NEXT: .cfi_undefined 2803 +; WAVE64-NEXT: .cfi_undefined 2804 +; WAVE64-NEXT: .cfi_undefined 2805 +; WAVE64-NEXT: .cfi_undefined 2806 +; WAVE64-NEXT: .cfi_undefined 2807 +; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE64-NEXT: v_mov_b32_e32 v0, exec_lo +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE64-NEXT: v_mov_b32_e32 v0, exec_hi +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_offset 17, 0 +; WAVE64-NEXT: ;;#ASMSTART +; WAVE64-NEXT: ; clobber all VGPRs +; WAVE64-NEXT: ;;#ASMEND +; WAVE64-NEXT: s_waitcnt vmcnt(0) +; WAVE64-NEXT: s_setpc_b64 s[30:31] +; +; WAVE32-LABEL: caller_needs_to_spill_pc_to_memory: +; WAVE32: .Lfunc_begin6: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: .cfi_undefined 1536 +; WAVE32-NEXT: .cfi_undefined 1537 +; WAVE32-NEXT: .cfi_undefined 1538 +; WAVE32-NEXT: .cfi_undefined 1539 +; WAVE32-NEXT: .cfi_undefined 1540 +; WAVE32-NEXT: .cfi_undefined 1541 +; WAVE32-NEXT: .cfi_undefined 1542 +; WAVE32-NEXT: .cfi_undefined 1543 +; WAVE32-NEXT: .cfi_undefined 1544 +; WAVE32-NEXT: .cfi_undefined 1545 +; WAVE32-NEXT: .cfi_undefined 1546 +; WAVE32-NEXT: .cfi_undefined 1547 +; WAVE32-NEXT: .cfi_undefined 1548 +; WAVE32-NEXT: .cfi_undefined 1549 +; WAVE32-NEXT: .cfi_undefined 1550 +; WAVE32-NEXT: .cfi_undefined 1551 +; WAVE32-NEXT: .cfi_undefined 1552 +; WAVE32-NEXT: .cfi_undefined 1553 +; WAVE32-NEXT: .cfi_undefined 1554 +; WAVE32-NEXT: .cfi_undefined 1555 +; WAVE32-NEXT: .cfi_undefined 1556 +; WAVE32-NEXT: .cfi_undefined 1557 +; WAVE32-NEXT: .cfi_undefined 1558 +; WAVE32-NEXT: .cfi_undefined 1559 +; WAVE32-NEXT: .cfi_undefined 1560 +; WAVE32-NEXT: .cfi_undefined 1561 +; WAVE32-NEXT: .cfi_undefined 1562 +; WAVE32-NEXT: .cfi_undefined 1563 +; WAVE32-NEXT: .cfi_undefined 1564 +; WAVE32-NEXT: .cfi_undefined 1565 +; WAVE32-NEXT: .cfi_undefined 1566 +; WAVE32-NEXT: .cfi_undefined 1567 +; WAVE32-NEXT: .cfi_undefined 1568 +; WAVE32-NEXT: .cfi_undefined 1569 +; WAVE32-NEXT: .cfi_undefined 1570 +; WAVE32-NEXT: .cfi_undefined 1571 +; WAVE32-NEXT: .cfi_undefined 1572 +; WAVE32-NEXT: .cfi_undefined 1573 +; WAVE32-NEXT: .cfi_undefined 1574 +; WAVE32-NEXT: .cfi_undefined 1575 +; WAVE32-NEXT: .cfi_undefined 1584 +; WAVE32-NEXT: .cfi_undefined 1585 +; WAVE32-NEXT: .cfi_undefined 1586 +; WAVE32-NEXT: .cfi_undefined 1587 +; WAVE32-NEXT: .cfi_undefined 1588 +; WAVE32-NEXT: .cfi_undefined 1589 +; WAVE32-NEXT: .cfi_undefined 1590 +; WAVE32-NEXT: .cfi_undefined 1591 +; WAVE32-NEXT: .cfi_undefined 1600 +; WAVE32-NEXT: .cfi_undefined 1601 +; WAVE32-NEXT: .cfi_undefined 1602 +; WAVE32-NEXT: .cfi_undefined 1603 +; WAVE32-NEXT: .cfi_undefined 1604 +; WAVE32-NEXT: .cfi_undefined 1605 +; WAVE32-NEXT: .cfi_undefined 1606 +; WAVE32-NEXT: .cfi_undefined 1607 +; WAVE32-NEXT: .cfi_undefined 1616 +; WAVE32-NEXT: .cfi_undefined 1617 +; WAVE32-NEXT: .cfi_undefined 1618 +; WAVE32-NEXT: .cfi_undefined 1619 +; WAVE32-NEXT: .cfi_undefined 1620 +; WAVE32-NEXT: .cfi_undefined 1621 +; WAVE32-NEXT: .cfi_undefined 1622 +; WAVE32-NEXT: .cfi_undefined 1623 +; WAVE32-NEXT: .cfi_undefined 1632 +; WAVE32-NEXT: .cfi_undefined 1633 +; WAVE32-NEXT: .cfi_undefined 1634 +; WAVE32-NEXT: .cfi_undefined 1635 +; WAVE32-NEXT: .cfi_undefined 1636 +; WAVE32-NEXT: .cfi_undefined 1637 +; WAVE32-NEXT: .cfi_undefined 1638 +; WAVE32-NEXT: .cfi_undefined 1639 +; WAVE32-NEXT: .cfi_undefined 1648 +; WAVE32-NEXT: .cfi_undefined 1649 +; WAVE32-NEXT: .cfi_undefined 1650 +; WAVE32-NEXT: .cfi_undefined 1651 +; WAVE32-NEXT: .cfi_undefined 1652 +; WAVE32-NEXT: .cfi_undefined 1653 +; WAVE32-NEXT: .cfi_undefined 1654 +; WAVE32-NEXT: .cfi_undefined 1655 +; WAVE32-NEXT: .cfi_undefined 1664 +; WAVE32-NEXT: .cfi_undefined 1665 +; WAVE32-NEXT: .cfi_undefined 1666 +; WAVE32-NEXT: .cfi_undefined 1667 +; WAVE32-NEXT: .cfi_undefined 1668 +; WAVE32-NEXT: .cfi_undefined 1669 +; WAVE32-NEXT: .cfi_undefined 1670 +; WAVE32-NEXT: .cfi_undefined 1671 +; WAVE32-NEXT: .cfi_undefined 1680 +; WAVE32-NEXT: .cfi_undefined 1681 +; WAVE32-NEXT: .cfi_undefined 1682 +; WAVE32-NEXT: .cfi_undefined 1683 +; WAVE32-NEXT: .cfi_undefined 1684 +; WAVE32-NEXT: .cfi_undefined 1685 +; WAVE32-NEXT: .cfi_undefined 1686 +; WAVE32-NEXT: .cfi_undefined 1687 +; WAVE32-NEXT: .cfi_undefined 1696 +; WAVE32-NEXT: .cfi_undefined 1697 +; WAVE32-NEXT: .cfi_undefined 1698 +; WAVE32-NEXT: .cfi_undefined 1699 +; WAVE32-NEXT: .cfi_undefined 1700 +; WAVE32-NEXT: .cfi_undefined 1701 +; WAVE32-NEXT: .cfi_undefined 1702 +; WAVE32-NEXT: .cfi_undefined 1703 +; WAVE32-NEXT: .cfi_undefined 1712 +; WAVE32-NEXT: .cfi_undefined 1713 +; WAVE32-NEXT: .cfi_undefined 1714 +; WAVE32-NEXT: .cfi_undefined 1715 +; WAVE32-NEXT: .cfi_undefined 1716 +; WAVE32-NEXT: .cfi_undefined 1717 +; WAVE32-NEXT: .cfi_undefined 1718 +; WAVE32-NEXT: .cfi_undefined 1719 +; WAVE32-NEXT: .cfi_undefined 1728 +; WAVE32-NEXT: .cfi_undefined 1729 +; WAVE32-NEXT: .cfi_undefined 1730 +; WAVE32-NEXT: .cfi_undefined 1731 +; WAVE32-NEXT: .cfi_undefined 1732 +; WAVE32-NEXT: .cfi_undefined 1733 +; WAVE32-NEXT: .cfi_undefined 1734 +; WAVE32-NEXT: .cfi_undefined 1735 +; WAVE32-NEXT: .cfi_undefined 1744 +; WAVE32-NEXT: .cfi_undefined 1745 +; WAVE32-NEXT: .cfi_undefined 1746 +; WAVE32-NEXT: .cfi_undefined 1747 +; WAVE32-NEXT: .cfi_undefined 1748 +; WAVE32-NEXT: .cfi_undefined 1749 +; WAVE32-NEXT: .cfi_undefined 1750 +; WAVE32-NEXT: .cfi_undefined 1751 +; WAVE32-NEXT: .cfi_undefined 1760 +; WAVE32-NEXT: .cfi_undefined 1761 +; WAVE32-NEXT: .cfi_undefined 1762 +; WAVE32-NEXT: .cfi_undefined 1763 +; WAVE32-NEXT: .cfi_undefined 1764 +; WAVE32-NEXT: .cfi_undefined 1765 +; WAVE32-NEXT: .cfi_undefined 1766 +; WAVE32-NEXT: .cfi_undefined 1767 +; WAVE32-NEXT: .cfi_undefined 1776 +; WAVE32-NEXT: .cfi_undefined 1777 +; WAVE32-NEXT: .cfi_undefined 1778 +; WAVE32-NEXT: .cfi_undefined 1779 +; WAVE32-NEXT: .cfi_undefined 1780 +; WAVE32-NEXT: .cfi_undefined 1781 +; WAVE32-NEXT: .cfi_undefined 1782 +; WAVE32-NEXT: .cfi_undefined 1783 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: v_mov_b32_e32 v0, exec_lo +; WAVE32-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_offset 1, 0 +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber all VGPRs +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: s_setpc_b64 s[30:31] + call void asm sideeffect "; clobber all VGPRs", + "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9} + ,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19} + ,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29} + ,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38},~{v39} + ,~{v40},~{v41},~{v42},~{v43},~{v44},~{v45},~{v46},~{v47},~{v48},~{v49} + ,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59} + ,~{v60},~{v61},~{v62},~{v63},~{v64},~{v65},~{v66},~{v67},~{v68},~{v69} + ,~{v70},~{v71},~{v72},~{v73},~{v74},~{v75},~{v76},~{v77},~{v78},~{v79} + ,~{v80},~{v81},~{v82},~{v83},~{v84},~{v85},~{v86},~{v87},~{v88},~{v89} + ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} + ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109} + ,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119} + ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129} + ,~{v130},~{v131},~{v132},~{v133},~{v134},~{v135},~{v136},~{v137},~{v138},~{v139} + ,~{v140},~{v141},~{v142},~{v143},~{v144},~{v145},~{v146},~{v147},~{v148},~{v149} + ,~{v150},~{v151},~{v152},~{v153},~{v154},~{v155},~{v156},~{v157},~{v158},~{v159} + ,~{v160},~{v161},~{v162},~{v163},~{v164},~{v165},~{v166},~{v167},~{v168},~{v169} + ,~{v170},~{v171},~{v172},~{v173},~{v174},~{v175},~{v176},~{v177},~{v178},~{v179} + ,~{v180},~{v181},~{v182},~{v183},~{v184},~{v185},~{v186},~{v187},~{v188},~{v189} + ,~{v190},~{v191},~{v192},~{v193},~{v194},~{v195},~{v196},~{v197},~{v198},~{v199} + ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209} + ,~{v210},~{v211},~{v212},~{v213},~{v214},~{v215},~{v216},~{v217},~{v218},~{v219} + ,~{v220},~{v221},~{v222},~{v223},~{v224},~{v225},~{v226},~{v227},~{v228},~{v229} + ,~{v230},~{v231},~{v232},~{v233},~{v234},~{v235},~{v236},~{v237},~{v238},~{v239} + ,~{v240},~{v241},~{v242},~{v243},~{v244},~{v245},~{v246},~{v247},~{v248},~{v249} + ,~{v250},~{v251},~{v252},~{v253},~{v254},~{v255}" () #3 + ret void +} + +define void @need_to_spill_pc_to_mem() #3 { +; WAVE64-LABEL: need_to_spill_pc_to_mem: +; WAVE64: .Lfunc_begin7: +; WAVE64-NEXT: .cfi_startproc +; WAVE64-NEXT: ; %bb.0: +; WAVE64-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE64-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE64-NEXT: .cfi_undefined 2560 +; WAVE64-NEXT: .cfi_undefined 2561 +; WAVE64-NEXT: .cfi_undefined 2562 +; WAVE64-NEXT: .cfi_undefined 2563 +; WAVE64-NEXT: .cfi_undefined 2564 +; WAVE64-NEXT: .cfi_undefined 2565 +; WAVE64-NEXT: .cfi_undefined 2566 +; WAVE64-NEXT: .cfi_undefined 2567 +; WAVE64-NEXT: .cfi_undefined 2568 +; WAVE64-NEXT: .cfi_undefined 2569 +; WAVE64-NEXT: .cfi_undefined 2570 +; WAVE64-NEXT: .cfi_undefined 2571 +; WAVE64-NEXT: .cfi_undefined 2572 +; WAVE64-NEXT: .cfi_undefined 2573 +; WAVE64-NEXT: .cfi_undefined 2574 +; WAVE64-NEXT: .cfi_undefined 2575 +; WAVE64-NEXT: .cfi_undefined 2576 +; WAVE64-NEXT: .cfi_undefined 2577 +; WAVE64-NEXT: .cfi_undefined 2578 +; WAVE64-NEXT: .cfi_undefined 2579 +; WAVE64-NEXT: .cfi_undefined 2580 +; WAVE64-NEXT: .cfi_undefined 2581 +; WAVE64-NEXT: .cfi_undefined 2582 +; WAVE64-NEXT: .cfi_undefined 2583 +; WAVE64-NEXT: .cfi_undefined 2584 +; WAVE64-NEXT: .cfi_undefined 2585 +; WAVE64-NEXT: .cfi_undefined 2586 +; WAVE64-NEXT: .cfi_undefined 2587 +; WAVE64-NEXT: .cfi_undefined 2588 +; WAVE64-NEXT: .cfi_undefined 2589 +; WAVE64-NEXT: .cfi_undefined 2590 +; WAVE64-NEXT: .cfi_undefined 2591 +; WAVE64-NEXT: .cfi_undefined 2592 +; WAVE64-NEXT: .cfi_undefined 2593 +; WAVE64-NEXT: .cfi_undefined 2594 +; WAVE64-NEXT: .cfi_undefined 2595 +; WAVE64-NEXT: .cfi_undefined 2596 +; WAVE64-NEXT: .cfi_undefined 2597 +; WAVE64-NEXT: .cfi_undefined 2598 +; WAVE64-NEXT: .cfi_undefined 2599 +; WAVE64-NEXT: .cfi_undefined 2608 +; WAVE64-NEXT: .cfi_undefined 2609 +; WAVE64-NEXT: .cfi_undefined 2610 +; WAVE64-NEXT: .cfi_undefined 2611 +; WAVE64-NEXT: .cfi_undefined 2612 +; WAVE64-NEXT: .cfi_undefined 2613 +; WAVE64-NEXT: .cfi_undefined 2614 +; WAVE64-NEXT: .cfi_undefined 2615 +; WAVE64-NEXT: .cfi_undefined 2624 +; WAVE64-NEXT: .cfi_undefined 2625 +; WAVE64-NEXT: .cfi_undefined 2626 +; WAVE64-NEXT: .cfi_undefined 2627 +; WAVE64-NEXT: .cfi_undefined 2628 +; WAVE64-NEXT: .cfi_undefined 2629 +; WAVE64-NEXT: .cfi_undefined 2630 +; WAVE64-NEXT: .cfi_undefined 2631 +; WAVE64-NEXT: .cfi_undefined 2640 +; WAVE64-NEXT: .cfi_undefined 2641 +; WAVE64-NEXT: .cfi_undefined 2642 +; WAVE64-NEXT: .cfi_undefined 2643 +; WAVE64-NEXT: .cfi_undefined 2644 +; WAVE64-NEXT: .cfi_undefined 2645 +; WAVE64-NEXT: .cfi_undefined 2646 +; WAVE64-NEXT: .cfi_undefined 2647 +; WAVE64-NEXT: .cfi_undefined 2656 +; WAVE64-NEXT: .cfi_undefined 2657 +; WAVE64-NEXT: .cfi_undefined 2658 +; WAVE64-NEXT: .cfi_undefined 2659 +; WAVE64-NEXT: .cfi_undefined 2660 +; WAVE64-NEXT: .cfi_undefined 2661 +; WAVE64-NEXT: .cfi_undefined 2662 +; WAVE64-NEXT: .cfi_undefined 2663 +; WAVE64-NEXT: .cfi_undefined 2672 +; WAVE64-NEXT: .cfi_undefined 2673 +; WAVE64-NEXT: .cfi_undefined 2674 +; WAVE64-NEXT: .cfi_undefined 2675 +; WAVE64-NEXT: .cfi_undefined 2676 +; WAVE64-NEXT: .cfi_undefined 2677 +; WAVE64-NEXT: .cfi_undefined 2678 +; WAVE64-NEXT: .cfi_undefined 2679 +; WAVE64-NEXT: .cfi_undefined 2688 +; WAVE64-NEXT: .cfi_undefined 2689 +; WAVE64-NEXT: .cfi_undefined 2690 +; WAVE64-NEXT: .cfi_undefined 2691 +; WAVE64-NEXT: .cfi_undefined 2692 +; WAVE64-NEXT: .cfi_undefined 2693 +; WAVE64-NEXT: .cfi_undefined 2694 +; WAVE64-NEXT: .cfi_undefined 2695 +; WAVE64-NEXT: .cfi_undefined 2704 +; WAVE64-NEXT: .cfi_undefined 2705 +; WAVE64-NEXT: .cfi_undefined 2706 +; WAVE64-NEXT: .cfi_undefined 2707 +; WAVE64-NEXT: .cfi_undefined 2708 +; WAVE64-NEXT: .cfi_undefined 2709 +; WAVE64-NEXT: .cfi_undefined 2710 +; WAVE64-NEXT: .cfi_undefined 2711 +; WAVE64-NEXT: .cfi_undefined 2720 +; WAVE64-NEXT: .cfi_undefined 2721 +; WAVE64-NEXT: .cfi_undefined 2722 +; WAVE64-NEXT: .cfi_undefined 2723 +; WAVE64-NEXT: .cfi_undefined 2724 +; WAVE64-NEXT: .cfi_undefined 2725 +; WAVE64-NEXT: .cfi_undefined 2726 +; WAVE64-NEXT: .cfi_undefined 2727 +; WAVE64-NEXT: .cfi_undefined 2736 +; WAVE64-NEXT: .cfi_undefined 2737 +; WAVE64-NEXT: .cfi_undefined 2738 +; WAVE64-NEXT: .cfi_undefined 2739 +; WAVE64-NEXT: .cfi_undefined 2740 +; WAVE64-NEXT: .cfi_undefined 2741 +; WAVE64-NEXT: .cfi_undefined 2742 +; WAVE64-NEXT: .cfi_undefined 2743 +; WAVE64-NEXT: .cfi_undefined 2752 +; WAVE64-NEXT: .cfi_undefined 2753 +; WAVE64-NEXT: .cfi_undefined 2754 +; WAVE64-NEXT: .cfi_undefined 2755 +; WAVE64-NEXT: .cfi_undefined 2756 +; WAVE64-NEXT: .cfi_undefined 2757 +; WAVE64-NEXT: .cfi_undefined 2758 +; WAVE64-NEXT: .cfi_undefined 2759 +; WAVE64-NEXT: .cfi_undefined 2768 +; WAVE64-NEXT: .cfi_undefined 2769 +; WAVE64-NEXT: .cfi_undefined 2770 +; WAVE64-NEXT: .cfi_undefined 2771 +; WAVE64-NEXT: .cfi_undefined 2772 +; WAVE64-NEXT: .cfi_undefined 2773 +; WAVE64-NEXT: .cfi_undefined 2774 +; WAVE64-NEXT: .cfi_undefined 2775 +; WAVE64-NEXT: .cfi_undefined 2784 +; WAVE64-NEXT: .cfi_undefined 2785 +; WAVE64-NEXT: .cfi_undefined 2786 +; WAVE64-NEXT: .cfi_undefined 2787 +; WAVE64-NEXT: .cfi_undefined 2788 +; WAVE64-NEXT: .cfi_undefined 2789 +; WAVE64-NEXT: .cfi_undefined 2790 +; WAVE64-NEXT: .cfi_undefined 2791 +; WAVE64-NEXT: .cfi_undefined 2800 +; WAVE64-NEXT: .cfi_undefined 2801 +; WAVE64-NEXT: .cfi_undefined 2802 +; WAVE64-NEXT: .cfi_undefined 2803 +; WAVE64-NEXT: .cfi_undefined 2804 +; WAVE64-NEXT: .cfi_undefined 2805 +; WAVE64-NEXT: .cfi_undefined 2806 +; WAVE64-NEXT: .cfi_undefined 2807 +; WAVE64-NEXT: .cfi_undefined 48 +; WAVE64-NEXT: .cfi_undefined 49 +; WAVE64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE64-NEXT: s_mov_b32 s18, s33 +; WAVE64-NEXT: .cfi_register 65, 50 +; WAVE64-NEXT: s_mov_b32 s33, s32 +; WAVE64-NEXT: v_mov_b32_e32 v0, exec_lo +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:456 ; 4-byte Folded Spill +; WAVE64-NEXT: v_mov_b32_e32 v0, exec_hi +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:460 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_offset 17, 29184 +; WAVE64-NEXT: .cfi_def_cfa_register 65 +; WAVE64-NEXT: s_addk_i32 s32, 0x7800 +; WAVE64-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 28416 +; WAVE64-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 28160 +; WAVE64-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2602, 32, 17, 64, 27904 +; WAVE64-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2603, 32, 17, 64, 27648 +; WAVE64-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2604, 32, 17, 64, 27392 +; WAVE64-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2605, 32, 17, 64, 27136 +; WAVE64-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2606, 32, 17, 64, 26880 +; WAVE64-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2607, 32, 17, 64, 26624 +; WAVE64-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2616, 32, 17, 64, 26368 +; WAVE64-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2617, 32, 17, 64, 26112 +; WAVE64-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2618, 32, 17, 64, 25856 +; WAVE64-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2619, 32, 17, 64, 25600 +; WAVE64-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2620, 32, 17, 64, 25344 +; WAVE64-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2621, 32, 17, 64, 25088 +; WAVE64-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2622, 32, 17, 64, 24832 +; WAVE64-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2623, 32, 17, 64, 24576 +; WAVE64-NEXT: buffer_store_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2632, 32, 17, 64, 24320 +; WAVE64-NEXT: buffer_store_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2633, 32, 17, 64, 24064 +; WAVE64-NEXT: buffer_store_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2634, 32, 17, 64, 23808 +; WAVE64-NEXT: buffer_store_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2635, 32, 17, 64, 23552 +; WAVE64-NEXT: buffer_store_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2636, 32, 17, 64, 23296 +; WAVE64-NEXT: buffer_store_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2637, 32, 17, 64, 23040 +; WAVE64-NEXT: buffer_store_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2638, 32, 17, 64, 22784 +; WAVE64-NEXT: buffer_store_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2639, 32, 17, 64, 22528 +; WAVE64-NEXT: buffer_store_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2648, 32, 17, 64, 22272 +; WAVE64-NEXT: buffer_store_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2649, 32, 17, 64, 22016 +; WAVE64-NEXT: buffer_store_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2650, 32, 17, 64, 21760 +; WAVE64-NEXT: buffer_store_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2651, 32, 17, 64, 21504 +; WAVE64-NEXT: buffer_store_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2652, 32, 17, 64, 21248 +; WAVE64-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2653, 32, 17, 64, 20992 +; WAVE64-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2654, 32, 17, 64, 20736 +; WAVE64-NEXT: buffer_store_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2655, 32, 17, 64, 20480 +; WAVE64-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2664, 32, 17, 64, 20224 +; WAVE64-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2665, 32, 17, 64, 19968 +; WAVE64-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2666, 32, 17, 64, 19712 +; WAVE64-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2667, 32, 17, 64, 19456 +; WAVE64-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2668, 32, 17, 64, 19200 +; WAVE64-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2669, 32, 17, 64, 18944 +; WAVE64-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2670, 32, 17, 64, 18688 +; WAVE64-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2671, 32, 17, 64, 18432 +; WAVE64-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2680, 32, 17, 64, 18176 +; WAVE64-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2681, 32, 17, 64, 17920 +; WAVE64-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2682, 32, 17, 64, 17664 +; WAVE64-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2683, 32, 17, 64, 17408 +; WAVE64-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2684, 32, 17, 64, 17152 +; WAVE64-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2685, 32, 17, 64, 16896 +; WAVE64-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2686, 32, 17, 64, 16640 +; WAVE64-NEXT: buffer_store_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2687, 32, 17, 64, 16384 +; WAVE64-NEXT: buffer_store_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2696, 32, 17, 64, 16128 +; WAVE64-NEXT: buffer_store_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2697, 32, 17, 64, 15872 +; WAVE64-NEXT: buffer_store_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2698, 32, 17, 64, 15616 +; WAVE64-NEXT: buffer_store_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2699, 32, 17, 64, 15360 +; WAVE64-NEXT: buffer_store_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2700, 32, 17, 64, 15104 +; WAVE64-NEXT: buffer_store_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2701, 32, 17, 64, 14848 +; WAVE64-NEXT: buffer_store_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2702, 32, 17, 64, 14592 +; WAVE64-NEXT: buffer_store_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2703, 32, 17, 64, 14336 +; WAVE64-NEXT: buffer_store_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2712, 32, 17, 64, 14080 +; WAVE64-NEXT: buffer_store_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2713, 32, 17, 64, 13824 +; WAVE64-NEXT: buffer_store_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2714, 32, 17, 64, 13568 +; WAVE64-NEXT: buffer_store_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2715, 32, 17, 64, 13312 +; WAVE64-NEXT: buffer_store_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2716, 32, 17, 64, 13056 +; WAVE64-NEXT: buffer_store_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2717, 32, 17, 64, 12800 +; WAVE64-NEXT: buffer_store_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2718, 32, 17, 64, 12544 +; WAVE64-NEXT: buffer_store_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2719, 32, 17, 64, 12288 +; WAVE64-NEXT: buffer_store_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2728, 32, 17, 64, 12032 +; WAVE64-NEXT: buffer_store_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2729, 32, 17, 64, 11776 +; WAVE64-NEXT: buffer_store_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2730, 32, 17, 64, 11520 +; WAVE64-NEXT: buffer_store_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2731, 32, 17, 64, 11264 +; WAVE64-NEXT: buffer_store_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2732, 32, 17, 64, 11008 +; WAVE64-NEXT: buffer_store_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2733, 32, 17, 64, 10752 +; WAVE64-NEXT: buffer_store_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2734, 32, 17, 64, 10496 +; WAVE64-NEXT: buffer_store_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2735, 32, 17, 64, 10240 +; WAVE64-NEXT: buffer_store_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2744, 32, 17, 64, 9984 +; WAVE64-NEXT: buffer_store_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2745, 32, 17, 64, 9728 +; WAVE64-NEXT: buffer_store_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2746, 32, 17, 64, 9472 +; WAVE64-NEXT: buffer_store_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2747, 32, 17, 64, 9216 +; WAVE64-NEXT: buffer_store_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2748, 32, 17, 64, 8960 +; WAVE64-NEXT: buffer_store_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2749, 32, 17, 64, 8704 +; WAVE64-NEXT: buffer_store_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2750, 32, 17, 64, 8448 +; WAVE64-NEXT: buffer_store_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2751, 32, 17, 64, 8192 +; WAVE64-NEXT: buffer_store_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2760, 32, 17, 64, 7936 +; WAVE64-NEXT: buffer_store_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2761, 32, 17, 64, 7680 +; WAVE64-NEXT: buffer_store_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2762, 32, 17, 64, 7424 +; WAVE64-NEXT: buffer_store_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2763, 32, 17, 64, 7168 +; WAVE64-NEXT: buffer_store_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2764, 32, 17, 64, 6912 +; WAVE64-NEXT: buffer_store_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2765, 32, 17, 64, 6656 +; WAVE64-NEXT: buffer_store_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2766, 32, 17, 64, 6400 +; WAVE64-NEXT: buffer_store_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2767, 32, 17, 64, 6144 +; WAVE64-NEXT: buffer_store_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2776, 32, 17, 64, 5888 +; WAVE64-NEXT: buffer_store_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2777, 32, 17, 64, 5632 +; WAVE64-NEXT: buffer_store_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2778, 32, 17, 64, 5376 +; WAVE64-NEXT: buffer_store_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2779, 32, 17, 64, 5120 +; WAVE64-NEXT: buffer_store_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2780, 32, 17, 64, 4864 +; WAVE64-NEXT: buffer_store_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2781, 32, 17, 64, 4608 +; WAVE64-NEXT: buffer_store_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2782, 32, 17, 64, 4352 +; WAVE64-NEXT: buffer_store_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2783, 32, 17, 64, 4096 +; WAVE64-NEXT: buffer_store_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2792, 32, 17, 64, 3840 +; WAVE64-NEXT: buffer_store_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2793, 32, 17, 64, 3584 +; WAVE64-NEXT: buffer_store_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2794, 32, 17, 64, 3328 +; WAVE64-NEXT: buffer_store_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2795, 32, 17, 64, 3072 +; WAVE64-NEXT: buffer_store_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2796, 32, 17, 64, 2816 +; WAVE64-NEXT: buffer_store_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2797, 32, 17, 64, 2560 +; WAVE64-NEXT: buffer_store_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2798, 32, 17, 64, 2304 +; WAVE64-NEXT: buffer_store_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2799, 32, 17, 64, 2048 +; WAVE64-NEXT: buffer_store_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2808, 32, 17, 64, 1792 +; WAVE64-NEXT: buffer_store_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2809, 32, 17, 64, 1536 +; WAVE64-NEXT: buffer_store_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2810, 32, 17, 64, 1280 +; WAVE64-NEXT: buffer_store_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2811, 32, 17, 64, 1024 +; WAVE64-NEXT: buffer_store_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2812, 32, 17, 64, 768 +; WAVE64-NEXT: buffer_store_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2813, 32, 17, 64, 512 +; WAVE64-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2814, 32, 17, 64, 256 +; WAVE64-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_llvm_vector_offset 2815, 32, 17, 64, 0 +; WAVE64-NEXT: s_mov_b64 s[16:17], exec +; WAVE64-NEXT: s_mov_b64 exec, 3 +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:464 +; WAVE64-NEXT: v_writelane_b32 v0, s30, 0 +; WAVE64-NEXT: v_writelane_b32 v0, s31, 1 +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:448 ; 4-byte Folded Spill +; WAVE64-NEXT: .cfi_offset 16, 28672 +; WAVE64-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:464 +; WAVE64-NEXT: s_waitcnt vmcnt(0) +; WAVE64-NEXT: s_mov_b64 exec, s[16:17] +; WAVE64-NEXT: s_getpc_b64 s[16:17] +; WAVE64-NEXT: s_add_u32 s16, s16, caller_needs_to_spill_pc_to_memory@rel32@lo+4 +; WAVE64-NEXT: s_addc_u32 s17, s17, caller_needs_to_spill_pc_to_memory@rel32@hi+12 +; WAVE64-NEXT: s_swappc_b64 s[30:31], s[16:17] +; WAVE64-NEXT: s_mov_b64 s[4:5], exec +; WAVE64-NEXT: s_mov_b64 exec, 3 +; WAVE64-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:464 +; WAVE64-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:448 ; 4-byte Folded Reload +; WAVE64-NEXT: s_waitcnt vmcnt(0) +; WAVE64-NEXT: v_readlane_b32 s30, v0, 0 +; WAVE64-NEXT: v_readlane_b32 s31, v0, 1 +; WAVE64-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:464 +; WAVE64-NEXT: s_waitcnt vmcnt(0) +; WAVE64-NEXT: s_mov_b64 exec, s[4:5] +; WAVE64-NEXT: buffer_load_dword v255, off, s[0:3], s33 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Reload +; WAVE64-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Reload +; WAVE64-NEXT: s_mov_b32 s32, s33 +; WAVE64-NEXT: .cfi_def_cfa_register 64 +; WAVE64-NEXT: s_mov_b32 s33, s18 +; WAVE64-NEXT: s_waitcnt vmcnt(0) +; WAVE64-NEXT: s_setpc_b64 s[30:31] +; +; WAVE32-LABEL: need_to_spill_pc_to_mem: +; WAVE32: .Lfunc_begin7: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: .cfi_undefined 1536 +; WAVE32-NEXT: .cfi_undefined 1537 +; WAVE32-NEXT: .cfi_undefined 1538 +; WAVE32-NEXT: .cfi_undefined 1539 +; WAVE32-NEXT: .cfi_undefined 1540 +; WAVE32-NEXT: .cfi_undefined 1541 +; WAVE32-NEXT: .cfi_undefined 1542 +; WAVE32-NEXT: .cfi_undefined 1543 +; WAVE32-NEXT: .cfi_undefined 1544 +; WAVE32-NEXT: .cfi_undefined 1545 +; WAVE32-NEXT: .cfi_undefined 1546 +; WAVE32-NEXT: .cfi_undefined 1547 +; WAVE32-NEXT: .cfi_undefined 1548 +; WAVE32-NEXT: .cfi_undefined 1549 +; WAVE32-NEXT: .cfi_undefined 1550 +; WAVE32-NEXT: .cfi_undefined 1551 +; WAVE32-NEXT: .cfi_undefined 1552 +; WAVE32-NEXT: .cfi_undefined 1553 +; WAVE32-NEXT: .cfi_undefined 1554 +; WAVE32-NEXT: .cfi_undefined 1555 +; WAVE32-NEXT: .cfi_undefined 1556 +; WAVE32-NEXT: .cfi_undefined 1557 +; WAVE32-NEXT: .cfi_undefined 1558 +; WAVE32-NEXT: .cfi_undefined 1559 +; WAVE32-NEXT: .cfi_undefined 1560 +; WAVE32-NEXT: .cfi_undefined 1561 +; WAVE32-NEXT: .cfi_undefined 1562 +; WAVE32-NEXT: .cfi_undefined 1563 +; WAVE32-NEXT: .cfi_undefined 1564 +; WAVE32-NEXT: .cfi_undefined 1565 +; WAVE32-NEXT: .cfi_undefined 1566 +; WAVE32-NEXT: .cfi_undefined 1567 +; WAVE32-NEXT: .cfi_undefined 1568 +; WAVE32-NEXT: .cfi_undefined 1569 +; WAVE32-NEXT: .cfi_undefined 1570 +; WAVE32-NEXT: .cfi_undefined 1571 +; WAVE32-NEXT: .cfi_undefined 1572 +; WAVE32-NEXT: .cfi_undefined 1573 +; WAVE32-NEXT: .cfi_undefined 1574 +; WAVE32-NEXT: .cfi_undefined 1575 +; WAVE32-NEXT: .cfi_undefined 1584 +; WAVE32-NEXT: .cfi_undefined 1585 +; WAVE32-NEXT: .cfi_undefined 1586 +; WAVE32-NEXT: .cfi_undefined 1587 +; WAVE32-NEXT: .cfi_undefined 1588 +; WAVE32-NEXT: .cfi_undefined 1589 +; WAVE32-NEXT: .cfi_undefined 1590 +; WAVE32-NEXT: .cfi_undefined 1591 +; WAVE32-NEXT: .cfi_undefined 1600 +; WAVE32-NEXT: .cfi_undefined 1601 +; WAVE32-NEXT: .cfi_undefined 1602 +; WAVE32-NEXT: .cfi_undefined 1603 +; WAVE32-NEXT: .cfi_undefined 1604 +; WAVE32-NEXT: .cfi_undefined 1605 +; WAVE32-NEXT: .cfi_undefined 1606 +; WAVE32-NEXT: .cfi_undefined 1607 +; WAVE32-NEXT: .cfi_undefined 1616 +; WAVE32-NEXT: .cfi_undefined 1617 +; WAVE32-NEXT: .cfi_undefined 1618 +; WAVE32-NEXT: .cfi_undefined 1619 +; WAVE32-NEXT: .cfi_undefined 1620 +; WAVE32-NEXT: .cfi_undefined 1621 +; WAVE32-NEXT: .cfi_undefined 1622 +; WAVE32-NEXT: .cfi_undefined 1623 +; WAVE32-NEXT: .cfi_undefined 1632 +; WAVE32-NEXT: .cfi_undefined 1633 +; WAVE32-NEXT: .cfi_undefined 1634 +; WAVE32-NEXT: .cfi_undefined 1635 +; WAVE32-NEXT: .cfi_undefined 1636 +; WAVE32-NEXT: .cfi_undefined 1637 +; WAVE32-NEXT: .cfi_undefined 1638 +; WAVE32-NEXT: .cfi_undefined 1639 +; WAVE32-NEXT: .cfi_undefined 1648 +; WAVE32-NEXT: .cfi_undefined 1649 +; WAVE32-NEXT: .cfi_undefined 1650 +; WAVE32-NEXT: .cfi_undefined 1651 +; WAVE32-NEXT: .cfi_undefined 1652 +; WAVE32-NEXT: .cfi_undefined 1653 +; WAVE32-NEXT: .cfi_undefined 1654 +; WAVE32-NEXT: .cfi_undefined 1655 +; WAVE32-NEXT: .cfi_undefined 1664 +; WAVE32-NEXT: .cfi_undefined 1665 +; WAVE32-NEXT: .cfi_undefined 1666 +; WAVE32-NEXT: .cfi_undefined 1667 +; WAVE32-NEXT: .cfi_undefined 1668 +; WAVE32-NEXT: .cfi_undefined 1669 +; WAVE32-NEXT: .cfi_undefined 1670 +; WAVE32-NEXT: .cfi_undefined 1671 +; WAVE32-NEXT: .cfi_undefined 1680 +; WAVE32-NEXT: .cfi_undefined 1681 +; WAVE32-NEXT: .cfi_undefined 1682 +; WAVE32-NEXT: .cfi_undefined 1683 +; WAVE32-NEXT: .cfi_undefined 1684 +; WAVE32-NEXT: .cfi_undefined 1685 +; WAVE32-NEXT: .cfi_undefined 1686 +; WAVE32-NEXT: .cfi_undefined 1687 +; WAVE32-NEXT: .cfi_undefined 1696 +; WAVE32-NEXT: .cfi_undefined 1697 +; WAVE32-NEXT: .cfi_undefined 1698 +; WAVE32-NEXT: .cfi_undefined 1699 +; WAVE32-NEXT: .cfi_undefined 1700 +; WAVE32-NEXT: .cfi_undefined 1701 +; WAVE32-NEXT: .cfi_undefined 1702 +; WAVE32-NEXT: .cfi_undefined 1703 +; WAVE32-NEXT: .cfi_undefined 1712 +; WAVE32-NEXT: .cfi_undefined 1713 +; WAVE32-NEXT: .cfi_undefined 1714 +; WAVE32-NEXT: .cfi_undefined 1715 +; WAVE32-NEXT: .cfi_undefined 1716 +; WAVE32-NEXT: .cfi_undefined 1717 +; WAVE32-NEXT: .cfi_undefined 1718 +; WAVE32-NEXT: .cfi_undefined 1719 +; WAVE32-NEXT: .cfi_undefined 1728 +; WAVE32-NEXT: .cfi_undefined 1729 +; WAVE32-NEXT: .cfi_undefined 1730 +; WAVE32-NEXT: .cfi_undefined 1731 +; WAVE32-NEXT: .cfi_undefined 1732 +; WAVE32-NEXT: .cfi_undefined 1733 +; WAVE32-NEXT: .cfi_undefined 1734 +; WAVE32-NEXT: .cfi_undefined 1735 +; WAVE32-NEXT: .cfi_undefined 1744 +; WAVE32-NEXT: .cfi_undefined 1745 +; WAVE32-NEXT: .cfi_undefined 1746 +; WAVE32-NEXT: .cfi_undefined 1747 +; WAVE32-NEXT: .cfi_undefined 1748 +; WAVE32-NEXT: .cfi_undefined 1749 +; WAVE32-NEXT: .cfi_undefined 1750 +; WAVE32-NEXT: .cfi_undefined 1751 +; WAVE32-NEXT: .cfi_undefined 1760 +; WAVE32-NEXT: .cfi_undefined 1761 +; WAVE32-NEXT: .cfi_undefined 1762 +; WAVE32-NEXT: .cfi_undefined 1763 +; WAVE32-NEXT: .cfi_undefined 1764 +; WAVE32-NEXT: .cfi_undefined 1765 +; WAVE32-NEXT: .cfi_undefined 1766 +; WAVE32-NEXT: .cfi_undefined 1767 +; WAVE32-NEXT: .cfi_undefined 1776 +; WAVE32-NEXT: .cfi_undefined 1777 +; WAVE32-NEXT: .cfi_undefined 1778 +; WAVE32-NEXT: .cfi_undefined 1779 +; WAVE32-NEXT: .cfi_undefined 1780 +; WAVE32-NEXT: .cfi_undefined 1781 +; WAVE32-NEXT: .cfi_undefined 1782 +; WAVE32-NEXT: .cfi_undefined 1783 +; WAVE32-NEXT: .cfi_undefined 48 +; WAVE32-NEXT: .cfi_undefined 49 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: s_mov_b32 s18, s33 +; WAVE32-NEXT: .cfi_register 65, 50 +; WAVE32-NEXT: v_mov_b32_e32 v0, exec_lo +; WAVE32-NEXT: s_mov_b32 s33, s32 +; WAVE32-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:456 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_offset 1, 14592 +; WAVE32-NEXT: .cfi_def_cfa_register 65 +; WAVE32-NEXT: s_addk_i32 s32, 0x3a00 +; WAVE32-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1576, 32, 1, 32, 14208 +; WAVE32-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1577, 32, 1, 32, 14080 +; WAVE32-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1578, 32, 1, 32, 13952 +; WAVE32-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1579, 32, 1, 32, 13824 +; WAVE32-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1580, 32, 1, 32, 13696 +; WAVE32-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1581, 32, 1, 32, 13568 +; WAVE32-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1582, 32, 1, 32, 13440 +; WAVE32-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1583, 32, 1, 32, 13312 +; WAVE32-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1592, 32, 1, 32, 13184 +; WAVE32-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1593, 32, 1, 32, 13056 +; WAVE32-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1594, 32, 1, 32, 12928 +; WAVE32-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1595, 32, 1, 32, 12800 +; WAVE32-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1596, 32, 1, 32, 12672 +; WAVE32-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1597, 32, 1, 32, 12544 +; WAVE32-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1598, 32, 1, 32, 12416 +; WAVE32-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1599, 32, 1, 32, 12288 +; WAVE32-NEXT: buffer_store_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1608, 32, 1, 32, 12160 +; WAVE32-NEXT: buffer_store_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1609, 32, 1, 32, 12032 +; WAVE32-NEXT: buffer_store_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1610, 32, 1, 32, 11904 +; WAVE32-NEXT: buffer_store_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1611, 32, 1, 32, 11776 +; WAVE32-NEXT: buffer_store_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1612, 32, 1, 32, 11648 +; WAVE32-NEXT: buffer_store_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1613, 32, 1, 32, 11520 +; WAVE32-NEXT: buffer_store_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1614, 32, 1, 32, 11392 +; WAVE32-NEXT: buffer_store_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1615, 32, 1, 32, 11264 +; WAVE32-NEXT: buffer_store_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1624, 32, 1, 32, 11136 +; WAVE32-NEXT: buffer_store_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1625, 32, 1, 32, 11008 +; WAVE32-NEXT: buffer_store_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1626, 32, 1, 32, 10880 +; WAVE32-NEXT: buffer_store_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1627, 32, 1, 32, 10752 +; WAVE32-NEXT: buffer_store_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1628, 32, 1, 32, 10624 +; WAVE32-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1629, 32, 1, 32, 10496 +; WAVE32-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1630, 32, 1, 32, 10368 +; WAVE32-NEXT: buffer_store_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1631, 32, 1, 32, 10240 +; WAVE32-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1640, 32, 1, 32, 10112 +; WAVE32-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1641, 32, 1, 32, 9984 +; WAVE32-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1642, 32, 1, 32, 9856 +; WAVE32-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1643, 32, 1, 32, 9728 +; WAVE32-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1644, 32, 1, 32, 9600 +; WAVE32-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1645, 32, 1, 32, 9472 +; WAVE32-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1646, 32, 1, 32, 9344 +; WAVE32-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1647, 32, 1, 32, 9216 +; WAVE32-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1656, 32, 1, 32, 9088 +; WAVE32-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1657, 32, 1, 32, 8960 +; WAVE32-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1658, 32, 1, 32, 8832 +; WAVE32-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1659, 32, 1, 32, 8704 +; WAVE32-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1660, 32, 1, 32, 8576 +; WAVE32-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1661, 32, 1, 32, 8448 +; WAVE32-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1662, 32, 1, 32, 8320 +; WAVE32-NEXT: buffer_store_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1663, 32, 1, 32, 8192 +; WAVE32-NEXT: buffer_store_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1672, 32, 1, 32, 8064 +; WAVE32-NEXT: buffer_store_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1673, 32, 1, 32, 7936 +; WAVE32-NEXT: buffer_store_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1674, 32, 1, 32, 7808 +; WAVE32-NEXT: buffer_store_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1675, 32, 1, 32, 7680 +; WAVE32-NEXT: buffer_store_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1676, 32, 1, 32, 7552 +; WAVE32-NEXT: buffer_store_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1677, 32, 1, 32, 7424 +; WAVE32-NEXT: buffer_store_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1678, 32, 1, 32, 7296 +; WAVE32-NEXT: buffer_store_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1679, 32, 1, 32, 7168 +; WAVE32-NEXT: buffer_store_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1688, 32, 1, 32, 7040 +; WAVE32-NEXT: buffer_store_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1689, 32, 1, 32, 6912 +; WAVE32-NEXT: buffer_store_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1690, 32, 1, 32, 6784 +; WAVE32-NEXT: buffer_store_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1691, 32, 1, 32, 6656 +; WAVE32-NEXT: buffer_store_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1692, 32, 1, 32, 6528 +; WAVE32-NEXT: buffer_store_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1693, 32, 1, 32, 6400 +; WAVE32-NEXT: buffer_store_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1694, 32, 1, 32, 6272 +; WAVE32-NEXT: buffer_store_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1695, 32, 1, 32, 6144 +; WAVE32-NEXT: buffer_store_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1704, 32, 1, 32, 6016 +; WAVE32-NEXT: buffer_store_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1705, 32, 1, 32, 5888 +; WAVE32-NEXT: buffer_store_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1706, 32, 1, 32, 5760 +; WAVE32-NEXT: buffer_store_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1707, 32, 1, 32, 5632 +; WAVE32-NEXT: buffer_store_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1708, 32, 1, 32, 5504 +; WAVE32-NEXT: buffer_store_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1709, 32, 1, 32, 5376 +; WAVE32-NEXT: buffer_store_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1710, 32, 1, 32, 5248 +; WAVE32-NEXT: buffer_store_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1711, 32, 1, 32, 5120 +; WAVE32-NEXT: buffer_store_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1720, 32, 1, 32, 4992 +; WAVE32-NEXT: buffer_store_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1721, 32, 1, 32, 4864 +; WAVE32-NEXT: buffer_store_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1722, 32, 1, 32, 4736 +; WAVE32-NEXT: buffer_store_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1723, 32, 1, 32, 4608 +; WAVE32-NEXT: buffer_store_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1724, 32, 1, 32, 4480 +; WAVE32-NEXT: buffer_store_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1725, 32, 1, 32, 4352 +; WAVE32-NEXT: buffer_store_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1726, 32, 1, 32, 4224 +; WAVE32-NEXT: buffer_store_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1727, 32, 1, 32, 4096 +; WAVE32-NEXT: buffer_store_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1736, 32, 1, 32, 3968 +; WAVE32-NEXT: buffer_store_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1737, 32, 1, 32, 3840 +; WAVE32-NEXT: buffer_store_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1738, 32, 1, 32, 3712 +; WAVE32-NEXT: buffer_store_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1739, 32, 1, 32, 3584 +; WAVE32-NEXT: buffer_store_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1740, 32, 1, 32, 3456 +; WAVE32-NEXT: buffer_store_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1741, 32, 1, 32, 3328 +; WAVE32-NEXT: buffer_store_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1742, 32, 1, 32, 3200 +; WAVE32-NEXT: buffer_store_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1743, 32, 1, 32, 3072 +; WAVE32-NEXT: buffer_store_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1752, 32, 1, 32, 2944 +; WAVE32-NEXT: buffer_store_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1753, 32, 1, 32, 2816 +; WAVE32-NEXT: buffer_store_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1754, 32, 1, 32, 2688 +; WAVE32-NEXT: buffer_store_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1755, 32, 1, 32, 2560 +; WAVE32-NEXT: buffer_store_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1756, 32, 1, 32, 2432 +; WAVE32-NEXT: buffer_store_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1757, 32, 1, 32, 2304 +; WAVE32-NEXT: buffer_store_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1758, 32, 1, 32, 2176 +; WAVE32-NEXT: buffer_store_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1759, 32, 1, 32, 2048 +; WAVE32-NEXT: buffer_store_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1768, 32, 1, 32, 1920 +; WAVE32-NEXT: buffer_store_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1769, 32, 1, 32, 1792 +; WAVE32-NEXT: buffer_store_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1770, 32, 1, 32, 1664 +; WAVE32-NEXT: buffer_store_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1771, 32, 1, 32, 1536 +; WAVE32-NEXT: buffer_store_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1772, 32, 1, 32, 1408 +; WAVE32-NEXT: buffer_store_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1773, 32, 1, 32, 1280 +; WAVE32-NEXT: buffer_store_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1774, 32, 1, 32, 1152 +; WAVE32-NEXT: buffer_store_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1775, 32, 1, 32, 1024 +; WAVE32-NEXT: buffer_store_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1784, 32, 1, 32, 896 +; WAVE32-NEXT: buffer_store_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1785, 32, 1, 32, 768 +; WAVE32-NEXT: buffer_store_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1786, 32, 1, 32, 640 +; WAVE32-NEXT: buffer_store_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1787, 32, 1, 32, 512 +; WAVE32-NEXT: buffer_store_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1788, 32, 1, 32, 384 +; WAVE32-NEXT: buffer_store_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1789, 32, 1, 32, 256 +; WAVE32-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1790, 32, 1, 32, 128 +; WAVE32-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1791, 32, 1, 32, 0 +; WAVE32-NEXT: s_mov_b32 s16, exec_lo +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, 3 +; WAVE32-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:460 +; WAVE32-NEXT: v_writelane_b32 v0, s30, 0 +; WAVE32-NEXT: v_writelane_b32 v0, s31, 1 +; WAVE32-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:448 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_offset 16, 14336 +; WAVE32-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:460 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s16 +; WAVE32-NEXT: s_getpc_b64 s[16:17] +; WAVE32-NEXT: s_add_u32 s16, s16, caller_needs_to_spill_pc_to_memory@rel32@lo+4 +; WAVE32-NEXT: s_addc_u32 s17, s17, caller_needs_to_spill_pc_to_memory@rel32@hi+12 +; WAVE32-NEXT: s_swappc_b64 s[30:31], s[16:17] +; WAVE32-NEXT: s_mov_b32 s4, exec_lo +; WAVE32-NEXT: s_mov_b32 exec_lo, 3 +; WAVE32-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:460 +; WAVE32-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:448 ; 4-byte Folded Reload +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: v_readlane_b32 s30, v0, 0 +; WAVE32-NEXT: v_readlane_b32 s31, v0, 1 +; WAVE32-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:460 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s4 +; WAVE32-NEXT: s_clause 0x3e +; WAVE32-NEXT: buffer_load_dword v255, off, s[0:3], s33 +; WAVE32-NEXT: buffer_load_dword v254, off, s[0:3], s33 offset:4 +; WAVE32-NEXT: buffer_load_dword v253, off, s[0:3], s33 offset:8 +; WAVE32-NEXT: buffer_load_dword v252, off, s[0:3], s33 offset:12 +; WAVE32-NEXT: buffer_load_dword v251, off, s[0:3], s33 offset:16 +; WAVE32-NEXT: buffer_load_dword v250, off, s[0:3], s33 offset:20 +; WAVE32-NEXT: buffer_load_dword v249, off, s[0:3], s33 offset:24 +; WAVE32-NEXT: buffer_load_dword v248, off, s[0:3], s33 offset:28 +; WAVE32-NEXT: buffer_load_dword v239, off, s[0:3], s33 offset:32 +; WAVE32-NEXT: buffer_load_dword v238, off, s[0:3], s33 offset:36 +; WAVE32-NEXT: buffer_load_dword v237, off, s[0:3], s33 offset:40 +; WAVE32-NEXT: buffer_load_dword v236, off, s[0:3], s33 offset:44 +; WAVE32-NEXT: buffer_load_dword v235, off, s[0:3], s33 offset:48 +; WAVE32-NEXT: buffer_load_dword v234, off, s[0:3], s33 offset:52 +; WAVE32-NEXT: buffer_load_dword v233, off, s[0:3], s33 offset:56 +; WAVE32-NEXT: buffer_load_dword v232, off, s[0:3], s33 offset:60 +; WAVE32-NEXT: buffer_load_dword v223, off, s[0:3], s33 offset:64 +; WAVE32-NEXT: buffer_load_dword v222, off, s[0:3], s33 offset:68 +; WAVE32-NEXT: buffer_load_dword v221, off, s[0:3], s33 offset:72 +; WAVE32-NEXT: buffer_load_dword v220, off, s[0:3], s33 offset:76 +; WAVE32-NEXT: buffer_load_dword v219, off, s[0:3], s33 offset:80 +; WAVE32-NEXT: buffer_load_dword v218, off, s[0:3], s33 offset:84 +; WAVE32-NEXT: buffer_load_dword v217, off, s[0:3], s33 offset:88 +; WAVE32-NEXT: buffer_load_dword v216, off, s[0:3], s33 offset:92 +; WAVE32-NEXT: buffer_load_dword v207, off, s[0:3], s33 offset:96 +; WAVE32-NEXT: buffer_load_dword v206, off, s[0:3], s33 offset:100 +; WAVE32-NEXT: buffer_load_dword v205, off, s[0:3], s33 offset:104 +; WAVE32-NEXT: buffer_load_dword v204, off, s[0:3], s33 offset:108 +; WAVE32-NEXT: buffer_load_dword v203, off, s[0:3], s33 offset:112 +; WAVE32-NEXT: buffer_load_dword v202, off, s[0:3], s33 offset:116 +; WAVE32-NEXT: buffer_load_dword v201, off, s[0:3], s33 offset:120 +; WAVE32-NEXT: buffer_load_dword v200, off, s[0:3], s33 offset:124 +; WAVE32-NEXT: buffer_load_dword v191, off, s[0:3], s33 offset:128 +; WAVE32-NEXT: buffer_load_dword v190, off, s[0:3], s33 offset:132 +; WAVE32-NEXT: buffer_load_dword v189, off, s[0:3], s33 offset:136 +; WAVE32-NEXT: buffer_load_dword v188, off, s[0:3], s33 offset:140 +; WAVE32-NEXT: buffer_load_dword v187, off, s[0:3], s33 offset:144 +; WAVE32-NEXT: buffer_load_dword v186, off, s[0:3], s33 offset:148 +; WAVE32-NEXT: buffer_load_dword v185, off, s[0:3], s33 offset:152 +; WAVE32-NEXT: buffer_load_dword v184, off, s[0:3], s33 offset:156 +; WAVE32-NEXT: buffer_load_dword v175, off, s[0:3], s33 offset:160 +; WAVE32-NEXT: buffer_load_dword v174, off, s[0:3], s33 offset:164 +; WAVE32-NEXT: buffer_load_dword v173, off, s[0:3], s33 offset:168 +; WAVE32-NEXT: buffer_load_dword v172, off, s[0:3], s33 offset:172 +; WAVE32-NEXT: buffer_load_dword v171, off, s[0:3], s33 offset:176 +; WAVE32-NEXT: buffer_load_dword v170, off, s[0:3], s33 offset:180 +; WAVE32-NEXT: buffer_load_dword v169, off, s[0:3], s33 offset:184 +; WAVE32-NEXT: buffer_load_dword v168, off, s[0:3], s33 offset:188 +; WAVE32-NEXT: buffer_load_dword v159, off, s[0:3], s33 offset:192 +; WAVE32-NEXT: buffer_load_dword v158, off, s[0:3], s33 offset:196 +; WAVE32-NEXT: buffer_load_dword v157, off, s[0:3], s33 offset:200 +; WAVE32-NEXT: buffer_load_dword v156, off, s[0:3], s33 offset:204 +; WAVE32-NEXT: buffer_load_dword v155, off, s[0:3], s33 offset:208 +; WAVE32-NEXT: buffer_load_dword v154, off, s[0:3], s33 offset:212 +; WAVE32-NEXT: buffer_load_dword v153, off, s[0:3], s33 offset:216 +; WAVE32-NEXT: buffer_load_dword v152, off, s[0:3], s33 offset:220 +; WAVE32-NEXT: buffer_load_dword v143, off, s[0:3], s33 offset:224 +; WAVE32-NEXT: buffer_load_dword v142, off, s[0:3], s33 offset:228 +; WAVE32-NEXT: buffer_load_dword v141, off, s[0:3], s33 offset:232 +; WAVE32-NEXT: buffer_load_dword v140, off, s[0:3], s33 offset:236 +; WAVE32-NEXT: buffer_load_dword v139, off, s[0:3], s33 offset:240 +; WAVE32-NEXT: buffer_load_dword v138, off, s[0:3], s33 offset:244 +; WAVE32-NEXT: buffer_load_dword v137, off, s[0:3], s33 offset:248 +; WAVE32-NEXT: s_clause 0x30 +; WAVE32-NEXT: buffer_load_dword v136, off, s[0:3], s33 offset:252 +; WAVE32-NEXT: buffer_load_dword v127, off, s[0:3], s33 offset:256 +; WAVE32-NEXT: buffer_load_dword v126, off, s[0:3], s33 offset:260 +; WAVE32-NEXT: buffer_load_dword v125, off, s[0:3], s33 offset:264 +; WAVE32-NEXT: buffer_load_dword v124, off, s[0:3], s33 offset:268 +; WAVE32-NEXT: buffer_load_dword v123, off, s[0:3], s33 offset:272 +; WAVE32-NEXT: buffer_load_dword v122, off, s[0:3], s33 offset:276 +; WAVE32-NEXT: buffer_load_dword v121, off, s[0:3], s33 offset:280 +; WAVE32-NEXT: buffer_load_dword v120, off, s[0:3], s33 offset:284 +; WAVE32-NEXT: buffer_load_dword v111, off, s[0:3], s33 offset:288 +; WAVE32-NEXT: buffer_load_dword v110, off, s[0:3], s33 offset:292 +; WAVE32-NEXT: buffer_load_dword v109, off, s[0:3], s33 offset:296 +; WAVE32-NEXT: buffer_load_dword v108, off, s[0:3], s33 offset:300 +; WAVE32-NEXT: buffer_load_dword v107, off, s[0:3], s33 offset:304 +; WAVE32-NEXT: buffer_load_dword v106, off, s[0:3], s33 offset:308 +; WAVE32-NEXT: buffer_load_dword v105, off, s[0:3], s33 offset:312 +; WAVE32-NEXT: buffer_load_dword v104, off, s[0:3], s33 offset:316 +; WAVE32-NEXT: buffer_load_dword v95, off, s[0:3], s33 offset:320 +; WAVE32-NEXT: buffer_load_dword v94, off, s[0:3], s33 offset:324 +; WAVE32-NEXT: buffer_load_dword v93, off, s[0:3], s33 offset:328 +; WAVE32-NEXT: buffer_load_dword v92, off, s[0:3], s33 offset:332 +; WAVE32-NEXT: buffer_load_dword v91, off, s[0:3], s33 offset:336 +; WAVE32-NEXT: buffer_load_dword v90, off, s[0:3], s33 offset:340 +; WAVE32-NEXT: buffer_load_dword v89, off, s[0:3], s33 offset:344 +; WAVE32-NEXT: buffer_load_dword v88, off, s[0:3], s33 offset:348 +; WAVE32-NEXT: buffer_load_dword v79, off, s[0:3], s33 offset:352 +; WAVE32-NEXT: buffer_load_dword v78, off, s[0:3], s33 offset:356 +; WAVE32-NEXT: buffer_load_dword v77, off, s[0:3], s33 offset:360 +; WAVE32-NEXT: buffer_load_dword v76, off, s[0:3], s33 offset:364 +; WAVE32-NEXT: buffer_load_dword v75, off, s[0:3], s33 offset:368 +; WAVE32-NEXT: buffer_load_dword v74, off, s[0:3], s33 offset:372 +; WAVE32-NEXT: buffer_load_dword v73, off, s[0:3], s33 offset:376 +; WAVE32-NEXT: buffer_load_dword v72, off, s[0:3], s33 offset:380 +; WAVE32-NEXT: buffer_load_dword v63, off, s[0:3], s33 offset:384 +; WAVE32-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:388 +; WAVE32-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:392 +; WAVE32-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:396 +; WAVE32-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:400 +; WAVE32-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:404 +; WAVE32-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:408 +; WAVE32-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:412 +; WAVE32-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:416 +; WAVE32-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:420 +; WAVE32-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:424 +; WAVE32-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:428 +; WAVE32-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:432 +; WAVE32-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:436 +; WAVE32-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:440 +; WAVE32-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:444 +; WAVE32-NEXT: s_mov_b32 s32, s33 +; WAVE32-NEXT: .cfi_def_cfa_register 64 +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 s33, s18 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_setpc_b64 s[30:31] + call void @caller_needs_to_spill_pc_to_memory() + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind "amdgpu-waves-per-eu"="10,10" } +attributes #2 = { nounwind "frame-pointer"="all" "amdgpu-waves-per-eu"="12,12" } +attributes #3 = { nounwind norecurse } + + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, emissionKind: FullDebug) +!1 = !DIFile(filename: "filename", directory: "directory") +!2 = !{i32 7, !"Dwarf Version", i32 4} +!3 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll index 583b6fe0a81ca..d4b07768e92a2 100644 --- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll +++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll @@ -205,17 +205,17 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 { ; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX8-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[16:17] +; GFX8-NEXT: v_writelane_b32 v3, s30, 0 ; GFX8-NEXT: s_addk_i32 s32, 0x400 +; GFX8-NEXT: v_writelane_b32 v3, s31, 1 ; GFX8-NEXT: s_getpc_b64 s[16:17] ; GFX8-NEXT: s_add_u32 s16, s16, with_private_to_flat_addrspacecast@gotpcrel32@lo+4 ; GFX8-NEXT: s_addc_u32 s17, s17, with_private_to_flat_addrspacecast@gotpcrel32@hi+12 ; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX8-NEXT: v_writelane_b32 v3, s30, 0 -; GFX8-NEXT: v_writelane_b32 v3, s31, 1 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX8-NEXT: v_readlane_b32 s31, v3, 1 ; GFX8-NEXT: v_readlane_b32 s30, v3, 0 +; GFX8-NEXT: v_readlane_b32 s31, v3, 1 ; GFX8-NEXT: s_mov_b32 s32, s33 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload @@ -233,17 +233,17 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 { ; GFX8-ARCH-FLAT-NEXT: s_add_i32 s3, s33, 8 ; GFX8-ARCH-FLAT-NEXT: scratch_store_dword off, v3, s3 ; 4-byte Folded Spill ; GFX8-ARCH-FLAT-NEXT: s_mov_b64 exec, s[0:1] +; GFX8-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0 ; GFX8-ARCH-FLAT-NEXT: s_add_i32 s32, s32, 16 +; GFX8-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1 ; GFX8-ARCH-FLAT-NEXT: s_getpc_b64 s[0:1] ; GFX8-ARCH-FLAT-NEXT: s_add_u32 s0, s0, with_private_to_flat_addrspacecast@gotpcrel32@lo+4 ; GFX8-ARCH-FLAT-NEXT: s_addc_u32 s1, s1, with_private_to_flat_addrspacecast@gotpcrel32@hi+12 ; GFX8-ARCH-FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 -; GFX8-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0 -; GFX8-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1 ; GFX8-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-ARCH-FLAT-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX8-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1 ; GFX8-ARCH-FLAT-NEXT: v_readlane_b32 s30, v3, 0 +; GFX8-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1 ; GFX8-ARCH-FLAT-NEXT: s_mov_b32 s32, s33 ; GFX8-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX8-ARCH-FLAT-NEXT: s_add_i32 s3, s33, 8 @@ -261,17 +261,17 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 { ; GFX9-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[16:17] +; GFX9-NEXT: v_writelane_b32 v3, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v3, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[16:17] ; GFX9-NEXT: s_add_u32 s16, s16, with_private_to_flat_addrspacecast@gotpcrel32@lo+4 ; GFX9-NEXT: s_addc_u32 s17, s17, with_private_to_flat_addrspacecast@gotpcrel32@hi+12 ; GFX9-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX9-NEXT: v_writelane_b32 v3, s30, 0 -; GFX9-NEXT: v_writelane_b32 v3, s31, 1 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX9-NEXT: v_readlane_b32 s31, v3, 1 ; GFX9-NEXT: v_readlane_b32 s30, v3, 0 +; GFX9-NEXT: v_readlane_b32 s31, v3, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload @@ -288,17 +288,17 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 { ; GFX9-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX9-ARCH-FLAT-NEXT: scratch_store_dword off, v3, s33 ; 4-byte Folded Spill ; GFX9-ARCH-FLAT-NEXT: s_mov_b64 exec, s[0:1] +; GFX9-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0 ; GFX9-ARCH-FLAT-NEXT: s_add_i32 s32, s32, 16 +; GFX9-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1 ; GFX9-ARCH-FLAT-NEXT: s_getpc_b64 s[0:1] ; GFX9-ARCH-FLAT-NEXT: s_add_u32 s0, s0, with_private_to_flat_addrspacecast@gotpcrel32@lo+4 ; GFX9-ARCH-FLAT-NEXT: s_addc_u32 s1, s1, with_private_to_flat_addrspacecast@gotpcrel32@hi+12 ; GFX9-ARCH-FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 -; GFX9-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0 -; GFX9-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1 ; GFX9-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-ARCH-FLAT-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX9-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1 ; GFX9-ARCH-FLAT-NEXT: v_readlane_b32 s30, v3, 0 +; GFX9-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1 ; GFX9-ARCH-FLAT-NEXT: s_mov_b32 s32, s33 ; GFX9-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX9-ARCH-FLAT-NEXT: scratch_load_dword v3, off, s33 ; 4-byte Folded Reload @@ -315,17 +315,18 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 { ; GFX942-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-ARCH-FLAT-NEXT: scratch_store_dword off, v3, s33 ; 4-byte Folded Spill ; GFX942-ARCH-FLAT-NEXT: s_mov_b64 exec, s[0:1] +; GFX942-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0 ; GFX942-ARCH-FLAT-NEXT: s_add_i32 s32, s32, 16 +; GFX942-ARCH-FLAT-NEXT: s_nop 0 +; GFX942-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1 ; GFX942-ARCH-FLAT-NEXT: s_getpc_b64 s[0:1] ; GFX942-ARCH-FLAT-NEXT: s_add_u32 s0, s0, with_private_to_flat_addrspacecast@gotpcrel32@lo+4 ; GFX942-ARCH-FLAT-NEXT: s_addc_u32 s1, s1, with_private_to_flat_addrspacecast@gotpcrel32@hi+12 ; GFX942-ARCH-FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 -; GFX942-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0 -; GFX942-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1 ; GFX942-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-ARCH-FLAT-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX942-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1 ; GFX942-ARCH-FLAT-NEXT: v_readlane_b32 s30, v3, 0 +; GFX942-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1 ; GFX942-ARCH-FLAT-NEXT: s_mov_b32 s32, s33 ; GFX942-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-ARCH-FLAT-NEXT: scratch_load_dword v3, off, s33 ; 4-byte Folded Reload @@ -343,17 +344,17 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 { ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s16 +; GFX10-NEXT: v_writelane_b32 v3, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v3, s31, 1 ; GFX10-NEXT: s_getpc_b64 s[16:17] ; GFX10-NEXT: s_add_u32 s16, s16, with_private_to_flat_addrspacecast@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s17, s17, with_private_to_flat_addrspacecast@gotpcrel32@hi+12 -; GFX10-NEXT: v_writelane_b32 v3, s30, 0 ; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX10-NEXT: v_writelane_b32 v3, s31, 1 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX10-NEXT: v_readlane_b32 s31, v3, 1 ; GFX10-NEXT: v_readlane_b32 s30, v3, 0 +; GFX10-NEXT: v_readlane_b32 s31, v3, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll index c005695a35ad8..d1a9f377d2e62 100644 --- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll +++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll @@ -725,37 +725,13 @@ define amdgpu_kernel void @indirect_call_known_callees(i1 %cond) { ; GFX9-LABEL: define amdgpu_kernel void @indirect_call_known_callees( ; GFX9-SAME: i1 [[COND:%.*]]) #[[ATTR0]] { ; GFX9-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @empty, ptr @also_empty -; GFX9-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @also_empty -; GFX9-NEXT: br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]] -; GFX9: [[BB2]]: -; GFX9-NEXT: call void @also_empty() -; GFX9-NEXT: br label %[[BB6:.*]] -; GFX9: [[BB3]]: -; GFX9-NEXT: br i1 true, label %[[BB4:.*]], label %[[BB5:.*]] -; GFX9: [[BB4]]: -; GFX9-NEXT: call void @empty() -; GFX9-NEXT: br label %[[BB6]] -; GFX9: [[BB5]]: -; GFX9-NEXT: unreachable -; GFX9: [[BB6]]: +; GFX9-NEXT: call void [[FPTR]]() ; GFX9-NEXT: ret void ; ; GFX10-LABEL: define amdgpu_kernel void @indirect_call_known_callees( ; GFX10-SAME: i1 [[COND:%.*]]) #[[ATTR0]] { ; GFX10-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @empty, ptr @also_empty -; GFX10-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @also_empty -; GFX10-NEXT: br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]] -; GFX10: [[BB2]]: -; GFX10-NEXT: call void @also_empty() -; GFX10-NEXT: br label %[[BB6:.*]] -; GFX10: [[BB3]]: -; GFX10-NEXT: br i1 true, label %[[BB4:.*]], label %[[BB5:.*]] -; GFX10: [[BB4]]: -; GFX10-NEXT: call void @empty() -; GFX10-NEXT: br label %[[BB6]] -; GFX10: [[BB5]]: -; GFX10-NEXT: unreachable -; GFX10: [[BB6]]: +; GFX10-NEXT: call void [[FPTR]]() ; GFX10-NEXT: ret void ; %fptr = select i1 %cond, ptr @empty, ptr @also_empty diff --git a/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir b/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir index dfe4b8a33f396..02856a31d2fb7 100644 --- a/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir +++ b/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir @@ -21,6 +21,8 @@ body: | ; GFX908-PEI-LABEL: name: agpr-spill-to-vgpr-machine-cp ; GFX908-PEI: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33 ; GFX908-PEI-NEXT: {{ $}} + ; GFX908-PEI-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX908-PEI-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX908-PEI-NEXT: renamable $agpr0 = COPY renamable $vgpr0, implicit $exec ; GFX908-PEI-NEXT: renamable $agpr2 = COPY renamable $vgpr1, implicit $exec ; GFX908-PEI-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 @@ -31,6 +33,8 @@ body: | ; GFX908-PEI-MACHINECP-LABEL: name: agpr-spill-to-vgpr-machine-cp ; GFX908-PEI-MACHINECP: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33 ; GFX908-PEI-MACHINECP-NEXT: {{ $}} + ; GFX908-PEI-MACHINECP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX908-PEI-MACHINECP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX908-PEI-MACHINECP-NEXT: renamable $agpr0 = COPY renamable $vgpr0, implicit $exec ; GFX908-PEI-MACHINECP-NEXT: renamable $agpr2 = COPY renamable $vgpr1, implicit $exec ; GFX908-PEI-MACHINECP-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 @@ -63,6 +67,8 @@ body: | ; GFX908-PEI-LABEL: name: agpr-spill-to-vgpr-to-stack-machine-cp ; GFX908-PEI: liveins: $vgpr0, $vgpr1, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908-PEI-NEXT: {{ $}} + ; GFX908-PEI-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX908-PEI-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX908-PEI-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908-PEI-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908-PEI-NEXT: renamable $agpr0 = COPY renamable $vgpr0, implicit $exec @@ -79,6 +85,8 @@ body: | ; GFX908-PEI-MACHINECP-LABEL: name: agpr-spill-to-vgpr-to-stack-machine-cp ; GFX908-PEI-MACHINECP: liveins: $vgpr0, $vgpr1, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908-PEI-MACHINECP-NEXT: {{ $}} + ; GFX908-PEI-MACHINECP-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX908-PEI-MACHINECP-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX908-PEI-MACHINECP-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908-PEI-MACHINECP-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908-PEI-MACHINECP-NEXT: renamable $agpr0 = COPY renamable $vgpr0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir index a2ec87053a8d5..481f7969652da 100644 --- a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir +++ b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir @@ -27,21 +27,1266 @@ body: | ; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GCN-NEXT: liveins: $sgpr30, $sgpr31, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr144 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr145 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr146 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr147 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr148 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr149 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr150 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr151 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr160 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr161 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr162 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr163 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr164 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr165 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr166 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr167 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr176 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr177 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr178 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr179 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr180 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr181 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr182 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr183 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr193 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr194 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr195 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr196 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr197 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr198 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr199 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr208 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr209 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr210 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr211 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr212 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr213 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr214 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr215 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr224 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr225 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr226 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr227 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr228 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr229 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr230 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr231 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr105 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr106 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr107 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr108 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr109 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr110 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr111 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr112 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr113 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr114 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr115 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr116 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr117 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr118 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr119 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr120 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr121 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr122 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr123 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr124 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr125 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr126 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr127 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr128 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr129 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr130 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr131 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr132 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr133 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr134 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr135 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr136 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr137 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr138 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr139 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr140 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr141 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr142 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr143 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr144 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr145 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr146 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr147 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr148 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr149 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr150 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr151 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr152 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr153 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr154 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr155 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr156 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr157 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr158 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr159 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr160 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr161 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr162 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr163 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr164 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr165 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr166 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr167 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr168 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr169 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr170 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr171 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr172 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr173 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr174 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr175 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr176 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr177 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr178 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr179 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr180 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr181 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr182 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr183 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr184 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr185 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr186 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr187 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr188 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr189 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr190 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr191 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr192 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr193 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr194 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr195 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr196 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr197 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr198 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr199 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr200 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr201 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr202 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr203 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr204 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr205 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr206 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr207 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr208 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr209 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr210 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr211 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr212 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr213 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr214 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr215 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr216 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr217 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr218 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr219 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr220 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr221 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr222 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr223 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr224 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr225 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr226 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr227 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr228 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr229 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr230 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr231 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr232 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr233 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr234 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr235 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr236 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr237 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr238 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr239 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr240 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr241 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr242 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr243 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr244 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr245 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr246 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr247 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr248 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr249 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr250 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr251 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr252 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr253 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr254 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr255 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GCN-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr40, 4352 ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 2816 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 2560 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 2304 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2048 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 1792 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 1536 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1280 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1024 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 768 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 512 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 256 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 0 ; GCN-NEXT: renamable $vgpr44 = COPY $vgpr13, implicit $exec ; GCN-NEXT: renamable $vgpr43 = COPY $vgpr12, implicit $exec ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit undef $scc diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll index 30ad46d959b7e..05b24bbc4cc97 100644 --- a/llvm/test/CodeGen/AMDGPU/bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/bf16.ll @@ -4392,8 +4392,8 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) { ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GCN-NEXT: buffer_store_short v0, v1, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_readlane_b32 s31, v2, 1 ; GCN-NEXT: v_readlane_b32 s30, v2, 0 +; GCN-NEXT: v_readlane_b32 s31, v2, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4410,21 +4410,21 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) { ; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX7-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[16:17] +; GFX7-NEXT: v_writelane_b32 v2, s30, 0 ; GFX7-NEXT: s_addk_i32 s32, 0x400 +; GFX7-NEXT: v_writelane_b32 v2, s31, 1 ; GFX7-NEXT: s_getpc_b64 s[16:17] ; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store@gotpcrel32@lo+4 ; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store@gotpcrel32@hi+12 ; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX7-NEXT: v_writelane_b32 v2, s30, 0 -; GFX7-NEXT: v_writelane_b32 v2, s31, 1 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX7-NEXT: v_readlane_b32 s30, v2, 0 ; GFX7-NEXT: buffer_store_short v0, v1, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readlane_b32 s31, v2, 1 -; GFX7-NEXT: v_readlane_b32 s30, v2, 0 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX7-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4441,19 +4441,19 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) { ; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX8-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[16:17] +; GFX8-NEXT: v_writelane_b32 v2, s30, 0 ; GFX8-NEXT: s_addk_i32 s32, 0x400 +; GFX8-NEXT: v_writelane_b32 v2, s31, 1 ; GFX8-NEXT: s_getpc_b64 s[16:17] ; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store@gotpcrel32@lo+4 ; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store@gotpcrel32@hi+12 ; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX8-NEXT: v_writelane_b32 v2, s30, 0 -; GFX8-NEXT: v_writelane_b32 v2, s31, 1 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX8-NEXT: v_readlane_b32 s30, v2, 0 ; GFX8-NEXT: buffer_store_short v0, v1, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readlane_b32 s31, v2, 1 -; GFX8-NEXT: v_readlane_b32 s30, v2, 0 ; GFX8-NEXT: s_mov_b32 s32, s33 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4470,19 +4470,19 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) { ; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX900-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[16:17] +; GFX900-NEXT: v_writelane_b32 v2, s30, 0 ; GFX900-NEXT: s_addk_i32 s32, 0x400 +; GFX900-NEXT: v_writelane_b32 v2, s31, 1 ; GFX900-NEXT: s_getpc_b64 s[16:17] ; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store@gotpcrel32@lo+4 ; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store@gotpcrel32@hi+12 ; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX900-NEXT: v_writelane_b32 v2, s30, 0 -; GFX900-NEXT: v_writelane_b32 v2, s31, 1 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX900-NEXT: v_readlane_b32 s30, v2, 0 ; GFX900-NEXT: buffer_store_short v0, v1, s[0:3], 0 offen ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: v_readlane_b32 s31, v2, 1 -; GFX900-NEXT: v_readlane_b32 s30, v2, 0 ; GFX900-NEXT: s_mov_b32 s32, s33 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4499,19 +4499,20 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) { ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_store_dword off, v4, s33 ; 4-byte Folded Spill ; GFX950-NEXT: s_mov_b64 exec, s[0:1] +; GFX950-NEXT: v_writelane_b32 v4, s30, 0 ; GFX950-NEXT: s_add_i32 s32, s32, 16 +; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_writelane_b32 v4, s31, 1 ; GFX950-NEXT: s_getpc_b64 s[0:1] ; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store@gotpcrel32@lo+4 ; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store@gotpcrel32@hi+12 ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 -; GFX950-NEXT: v_writelane_b32 v4, s30, 0 -; GFX950-NEXT: v_writelane_b32 v4, s31, 1 ; GFX950-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX950-NEXT: v_readlane_b32 s30, v4, 0 ; GFX950-NEXT: scratch_store_short v1, v0, off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_readlane_b32 s31, v4, 1 -; GFX950-NEXT: v_readlane_b32 s30, v4, 0 ; GFX950-NEXT: s_mov_b32 s32, s33 ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_load_dword v4, off, s33 ; 4-byte Folded Reload @@ -4529,19 +4530,19 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) { ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s16 +; GFX10-NEXT: v_writelane_b32 v2, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v2, s31, 1 ; GFX10-NEXT: s_getpc_b64 s[16:17] ; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store@gotpcrel32@hi+12 -; GFX10-NEXT: v_writelane_b32 v2, s30, 0 ; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX10-NEXT: v_writelane_b32 v2, s31, 1 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX10-NEXT: v_readlane_b32 s30, v2, 0 ; GFX10-NEXT: buffer_store_short v0, v1, s[0:3], 0 offen ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: v_readlane_b32 s31, v2, 1 -; GFX10-NEXT: v_readlane_b32 s30, v2, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4559,19 +4560,19 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) { ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v2, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 +; GFX11-NEXT: v_writelane_b32 v2, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v2, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v2, s30, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: v_writelane_b32 v2, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: v_readlane_b32 s30, v2, 0 ; GFX11-NEXT: scratch_store_b16 v1, v0, off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: v_readlane_b32 s31, v2, 1 -; GFX11-NEXT: v_readlane_b32 s30, v2, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v2, off, s33 ; 4-byte Folded Reload @@ -4590,18 +4591,18 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: scratch_store_b32 off, v4, s33 ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 -; GFX1250-NEXT: s_get_pc_i64 s[0:1] -; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store@gotpcrel+4 ; GFX1250-NEXT: v_writelane_b32 v4, s30, 0 -; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_add_co_i32 s32, s32, 16 ; GFX1250-NEXT: v_writelane_b32 v4, s31, 1 +; GFX1250-NEXT: s_get_pc_i64 s[0:1] +; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store@gotpcrel+4 +; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1] +; GFX1250-NEXT: v_readlane_b32 s30, v4, 0 ; GFX1250-NEXT: scratch_store_b16 v1, v0, off scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_storecnt 0x0 ; GFX1250-NEXT: v_readlane_b32 s31, v4, 1 -; GFX1250-NEXT: v_readlane_b32 s30, v4, 0 ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 @@ -4645,8 +4646,8 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_store_short v0, v2, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_readlane_b32 s31, v4, 1 ; GCN-NEXT: v_readlane_b32 s30, v4, 0 +; GCN-NEXT: v_readlane_b32 s31, v4, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4663,26 +4664,26 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) { ; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX7-NEXT: buffer_store_dword v4, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[16:17] +; GFX7-NEXT: v_writelane_b32 v4, s30, 0 ; GFX7-NEXT: s_addk_i32 s32, 0x400 +; GFX7-NEXT: v_writelane_b32 v4, s31, 1 ; GFX7-NEXT: s_getpc_b64 s[16:17] ; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX7-NEXT: v_writelane_b32 v4, s30, 0 -; GFX7-NEXT: v_writelane_b32 v4, s31, 1 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v1 ; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 ; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX7-NEXT: v_add_i32_e32 v3, vcc, 2, v2 +; GFX7-NEXT: v_readlane_b32 s30, v4, 0 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX7-NEXT: buffer_store_short v1, v3, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: buffer_store_short v0, v2, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readlane_b32 s31, v4, 1 -; GFX7-NEXT: v_readlane_b32 s30, v4, 0 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX7-NEXT: buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4699,19 +4700,19 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) { ; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX8-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[16:17] +; GFX8-NEXT: v_writelane_b32 v2, s30, 0 ; GFX8-NEXT: s_addk_i32 s32, 0x400 +; GFX8-NEXT: v_writelane_b32 v2, s31, 1 ; GFX8-NEXT: s_getpc_b64 s[16:17] ; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX8-NEXT: v_writelane_b32 v2, s30, 0 -; GFX8-NEXT: v_writelane_b32 v2, s31, 1 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX8-NEXT: v_readlane_b32 s30, v2, 0 ; GFX8-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readlane_b32 s31, v2, 1 -; GFX8-NEXT: v_readlane_b32 s30, v2, 0 ; GFX8-NEXT: s_mov_b32 s32, s33 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4728,19 +4729,19 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) { ; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX900-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[16:17] +; GFX900-NEXT: v_writelane_b32 v2, s30, 0 ; GFX900-NEXT: s_addk_i32 s32, 0x400 +; GFX900-NEXT: v_writelane_b32 v2, s31, 1 ; GFX900-NEXT: s_getpc_b64 s[16:17] ; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX900-NEXT: v_writelane_b32 v2, s30, 0 -; GFX900-NEXT: v_writelane_b32 v2, s31, 1 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX900-NEXT: v_readlane_b32 s30, v2, 0 ; GFX900-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: v_readlane_b32 s31, v2, 1 -; GFX900-NEXT: v_readlane_b32 s30, v2, 0 ; GFX900-NEXT: s_mov_b32 s32, s33 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4757,19 +4758,20 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) { ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_store_dword off, v4, s33 ; 4-byte Folded Spill ; GFX950-NEXT: s_mov_b64 exec, s[0:1] +; GFX950-NEXT: v_writelane_b32 v4, s30, 0 ; GFX950-NEXT: s_add_i32 s32, s32, 16 +; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_writelane_b32 v4, s31, 1 ; GFX950-NEXT: s_getpc_b64 s[0:1] ; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 -; GFX950-NEXT: v_writelane_b32 v4, s30, 0 -; GFX950-NEXT: v_writelane_b32 v4, s31, 1 ; GFX950-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX950-NEXT: v_readlane_b32 s30, v4, 0 ; GFX950-NEXT: scratch_store_dword v1, v0, off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_readlane_b32 s31, v4, 1 -; GFX950-NEXT: v_readlane_b32 s30, v4, 0 ; GFX950-NEXT: s_mov_b32 s32, s33 ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_load_dword v4, off, s33 ; 4-byte Folded Reload @@ -4787,19 +4789,19 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) { ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s16 +; GFX10-NEXT: v_writelane_b32 v2, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v2, s31, 1 ; GFX10-NEXT: s_getpc_b64 s[16:17] ; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 -; GFX10-NEXT: v_writelane_b32 v2, s30, 0 ; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX10-NEXT: v_writelane_b32 v2, s31, 1 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX10-NEXT: v_readlane_b32 s30, v2, 0 ; GFX10-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: v_readlane_b32 s31, v2, 1 -; GFX10-NEXT: v_readlane_b32 s30, v2, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4817,19 +4819,19 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) { ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v2, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 +; GFX11-NEXT: v_writelane_b32 v2, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v2, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v2, s30, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: v_writelane_b32 v2, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: v_readlane_b32 s30, v2, 0 ; GFX11-NEXT: scratch_store_b32 v1, v0, off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: v_readlane_b32 s31, v2, 1 -; GFX11-NEXT: v_readlane_b32 s30, v2, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v2, off, s33 ; 4-byte Folded Reload @@ -4848,18 +4850,18 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: scratch_store_b32 off, v4, s33 ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 -; GFX1250-NEXT: s_get_pc_i64 s[0:1] -; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16@gotpcrel+4 ; GFX1250-NEXT: v_writelane_b32 v4, s30, 0 -; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_add_co_i32 s32, s32, 16 ; GFX1250-NEXT: v_writelane_b32 v4, s31, 1 +; GFX1250-NEXT: s_get_pc_i64 s[0:1] +; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16@gotpcrel+4 +; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1] +; GFX1250-NEXT: v_readlane_b32 s30, v4, 0 ; GFX1250-NEXT: scratch_store_b32 v1, v0, off scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_storecnt 0x0 ; GFX1250-NEXT: v_readlane_b32 s31, v4, 1 -; GFX1250-NEXT: v_readlane_b32 s30, v4, 0 ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 @@ -4905,8 +4907,8 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_store_dword v0, v3, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_readlane_b32 s31, v5, 1 ; GCN-NEXT: v_readlane_b32 s30, v5, 0 +; GCN-NEXT: v_readlane_b32 s31, v5, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4923,13 +4925,13 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX7-NEXT: buffer_store_dword v4, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[16:17] +; GFX7-NEXT: v_writelane_b32 v4, s30, 0 ; GFX7-NEXT: s_addk_i32 s32, 0x400 +; GFX7-NEXT: v_writelane_b32 v4, s31, 1 ; GFX7-NEXT: s_getpc_b64 s[16:17] ; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX7-NEXT: v_writelane_b32 v4, s30, 0 -; GFX7-NEXT: v_writelane_b32 v4, s31, 1 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v1 @@ -4939,12 +4941,12 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v2 ; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, 4, v3 +; GFX7-NEXT: v_readlane_b32 s30, v4, 0 ; GFX7-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: buffer_store_dword v0, v3, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readlane_b32 s31, v4, 1 -; GFX7-NEXT: v_readlane_b32 s30, v4, 0 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX7-NEXT: buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4961,22 +4963,22 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX8-NEXT: buffer_store_dword v4, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[16:17] +; GFX8-NEXT: v_writelane_b32 v4, s30, 0 ; GFX8-NEXT: s_addk_i32 s32, 0x400 +; GFX8-NEXT: v_writelane_b32 v4, s31, 1 ; GFX8-NEXT: s_getpc_b64 s[16:17] ; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX8-NEXT: v_writelane_b32 v4, s30, 0 -; GFX8-NEXT: v_writelane_b32 v4, s31, 1 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2 +; GFX8-NEXT: v_readlane_b32 s30, v4, 0 ; GFX8-NEXT: buffer_store_short v1, v3, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readlane_b32 s31, v4, 1 -; GFX8-NEXT: v_readlane_b32 s30, v4, 0 ; GFX8-NEXT: s_mov_b32 s32, s33 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload @@ -4993,21 +4995,21 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX900-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[16:17] +; GFX900-NEXT: v_writelane_b32 v3, s30, 0 ; GFX900-NEXT: s_addk_i32 s32, 0x400 +; GFX900-NEXT: v_writelane_b32 v3, s31, 1 ; GFX900-NEXT: s_getpc_b64 s[16:17] ; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX900-NEXT: v_writelane_b32 v3, s30, 0 -; GFX900-NEXT: v_writelane_b32 v3, s31, 1 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX900-NEXT: v_readlane_b32 s30, v3, 0 ; GFX900-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen offset:4 ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: v_readlane_b32 s31, v3, 1 -; GFX900-NEXT: v_readlane_b32 s30, v3, 0 ; GFX900-NEXT: s_mov_b32 s32, s33 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5024,22 +5026,23 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_store_dword off, v5, s33 ; 4-byte Folded Spill ; GFX950-NEXT: s_mov_b64 exec, s[0:1] +; GFX950-NEXT: v_writelane_b32 v5, s30, 0 ; GFX950-NEXT: s_add_i32 s32, s32, 16 +; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_writelane_b32 v5, s31, 1 ; GFX950-NEXT: s_getpc_b64 s[0:1] ; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 -; GFX950-NEXT: v_writelane_b32 v5, s30, 0 -; GFX950-NEXT: v_writelane_b32 v5, s31, 1 ; GFX950-NEXT: v_mov_b32_e32 v4, v2 ; GFX950-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX950-NEXT: v_readlane_b32 s30, v5, 0 ; GFX950-NEXT: scratch_store_short v4, v1, off offset:4 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: scratch_store_dword v4, v0, off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_readlane_b32 s31, v5, 1 -; GFX950-NEXT: v_readlane_b32 s30, v5, 0 ; GFX950-NEXT: s_mov_b32 s32, s33 ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_load_dword v5, off, s33 ; 4-byte Folded Reload @@ -5057,21 +5060,21 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s16 +; GFX10-NEXT: v_writelane_b32 v3, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v3, s31, 1 ; GFX10-NEXT: s_getpc_b64 s[16:17] ; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 -; GFX10-NEXT: v_writelane_b32 v3, s30, 0 ; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX10-NEXT: v_writelane_b32 v3, s31, 1 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX10-NEXT: v_readlane_b32 s30, v3, 0 ; GFX10-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen offset:4 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: v_readlane_b32 s31, v3, 1 -; GFX10-NEXT: v_readlane_b32 s30, v3, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5089,21 +5092,21 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v3, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 +; GFX11-NEXT: v_writelane_b32 v3, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v3, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v3, s30, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: v_writelane_b32 v3, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: v_readlane_b32 s30, v3, 0 ; GFX11-NEXT: scratch_store_b16 v2, v1, off offset:4 dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: scratch_store_b32 v2, v0, off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: v_readlane_b32 s31, v3, 1 -; GFX11-NEXT: v_readlane_b32 s30, v3, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v3, off, s33 ; 4-byte Folded Reload @@ -5122,21 +5125,21 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 -; GFX1250-NEXT: s_get_pc_i64 s[0:1] -; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16@gotpcrel+4 ; GFX1250-NEXT: v_writelane_b32 v5, s30, 0 -; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_add_co_i32 s32, s32, 16 -; GFX1250-NEXT: v_mov_b32_e32 v4, v2 ; GFX1250-NEXT: v_writelane_b32 v5, s31, 1 +; GFX1250-NEXT: s_get_pc_i64 s[0:1] +; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16@gotpcrel+4 +; GFX1250-NEXT: v_mov_b32_e32 v4, v2 +; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1] +; GFX1250-NEXT: v_readlane_b32 s30, v5, 0 ; GFX1250-NEXT: scratch_store_b16 v4, v1, off offset:4 scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_storecnt 0x0 ; GFX1250-NEXT: scratch_store_b32 v4, v0, off scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_storecnt 0x0 ; GFX1250-NEXT: v_readlane_b32 s31, v5, 1 -; GFX1250-NEXT: v_readlane_b32 s30, v5, 0 ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 @@ -5190,8 +5193,8 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_store_short v0, v4, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_readlane_b32 s31, v8, 1 ; GCN-NEXT: v_readlane_b32 s30, v8, 0 +; GCN-NEXT: v_readlane_b32 s31, v8, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5208,13 +5211,13 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX7-NEXT: buffer_store_dword v6, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[16:17] +; GFX7-NEXT: v_writelane_b32 v6, s30, 0 ; GFX7-NEXT: s_addk_i32 s32, 0x400 +; GFX7-NEXT: v_writelane_b32 v6, s31, 1 ; GFX7-NEXT: s_getpc_b64 s[16:17] ; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX7-NEXT: v_writelane_b32 v6, s30, 0 -; GFX7-NEXT: v_writelane_b32 v6, s31, 1 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v3 @@ -5231,13 +5234,13 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GFX7-NEXT: buffer_store_short v2, v3, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_add_i32_e32 v2, vcc, 2, v4 +; GFX7-NEXT: v_readlane_b32 s30, v6, 0 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX7-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: buffer_store_short v0, v4, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readlane_b32 s31, v6, 1 -; GFX7-NEXT: v_readlane_b32 s30, v6, 0 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX7-NEXT: buffer_load_dword v6, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5254,22 +5257,22 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX8-NEXT: buffer_store_dword v4, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[16:17] +; GFX8-NEXT: v_writelane_b32 v4, s30, 0 ; GFX8-NEXT: s_addk_i32 s32, 0x400 +; GFX8-NEXT: v_writelane_b32 v4, s31, 1 ; GFX8-NEXT: s_getpc_b64 s[16:17] ; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX8-NEXT: v_writelane_b32 v4, s30, 0 -; GFX8-NEXT: v_writelane_b32 v4, s31, 1 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2 +; GFX8-NEXT: v_readlane_b32 s30, v4, 0 ; GFX8-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readlane_b32 s31, v4, 1 -; GFX8-NEXT: v_readlane_b32 s30, v4, 0 ; GFX8-NEXT: s_mov_b32 s32, s33 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5286,21 +5289,21 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX900-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[16:17] +; GFX900-NEXT: v_writelane_b32 v3, s30, 0 ; GFX900-NEXT: s_addk_i32 s32, 0x400 +; GFX900-NEXT: v_writelane_b32 v3, s31, 1 ; GFX900-NEXT: s_getpc_b64 s[16:17] ; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX900-NEXT: v_writelane_b32 v3, s30, 0 -; GFX900-NEXT: v_writelane_b32 v3, s31, 1 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX900-NEXT: v_readlane_b32 s30, v3, 0 ; GFX900-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4 ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: v_readlane_b32 s31, v3, 1 -; GFX900-NEXT: v_readlane_b32 s30, v3, 0 ; GFX900-NEXT: s_mov_b32 s32, s33 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5317,20 +5320,21 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_store_dword off, v5, s33 ; 4-byte Folded Spill ; GFX950-NEXT: s_mov_b64 exec, s[0:1] +; GFX950-NEXT: v_writelane_b32 v5, s30, 0 ; GFX950-NEXT: s_add_i32 s32, s32, 16 +; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_writelane_b32 v5, s31, 1 ; GFX950-NEXT: s_getpc_b64 s[0:1] ; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 -; GFX950-NEXT: v_writelane_b32 v5, s30, 0 -; GFX950-NEXT: v_writelane_b32 v5, s31, 1 ; GFX950-NEXT: v_mov_b32_e32 v4, v2 ; GFX950-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX950-NEXT: v_readlane_b32 s30, v5, 0 ; GFX950-NEXT: scratch_store_dwordx2 v4, v[0:1], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_readlane_b32 s31, v5, 1 -; GFX950-NEXT: v_readlane_b32 s30, v5, 0 ; GFX950-NEXT: s_mov_b32 s32, s33 ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_load_dword v5, off, s33 ; 4-byte Folded Reload @@ -5348,21 +5352,21 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s16 +; GFX10-NEXT: v_writelane_b32 v3, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v3, s31, 1 ; GFX10-NEXT: s_getpc_b64 s[16:17] ; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 -; GFX10-NEXT: v_writelane_b32 v3, s30, 0 ; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX10-NEXT: v_writelane_b32 v3, s31, 1 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX10-NEXT: v_readlane_b32 s30, v3, 0 ; GFX10-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: v_readlane_b32 s31, v3, 1 -; GFX10-NEXT: v_readlane_b32 s30, v3, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5380,19 +5384,19 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v3, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 +; GFX11-NEXT: v_writelane_b32 v3, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v3, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v3, s30, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: v_writelane_b32 v3, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: v_readlane_b32 s30, v3, 0 ; GFX11-NEXT: scratch_store_b64 v2, v[0:1], off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: v_readlane_b32 s31, v3, 1 -; GFX11-NEXT: v_readlane_b32 s30, v3, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v3, off, s33 ; 4-byte Folded Reload @@ -5411,19 +5415,19 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 -; GFX1250-NEXT: s_get_pc_i64 s[0:1] -; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16@gotpcrel+4 ; GFX1250-NEXT: v_writelane_b32 v5, s30, 0 -; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_add_co_i32 s32, s32, 16 -; GFX1250-NEXT: v_mov_b32_e32 v4, v2 ; GFX1250-NEXT: v_writelane_b32 v5, s31, 1 +; GFX1250-NEXT: s_get_pc_i64 s[0:1] +; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16@gotpcrel+4 +; GFX1250-NEXT: v_mov_b32_e32 v4, v2 +; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1] +; GFX1250-NEXT: v_readlane_b32 s30, v5, 0 ; GFX1250-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_storecnt 0x0 ; GFX1250-NEXT: v_readlane_b32 s31, v5, 1 -; GFX1250-NEXT: v_readlane_b32 s30, v5, 0 ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 @@ -5497,8 +5501,8 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_store_short v0, v8, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_readlane_b32 s31, v16, 1 ; GCN-NEXT: v_readlane_b32 s30, v16, 0 +; GCN-NEXT: v_readlane_b32 s31, v16, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5515,13 +5519,13 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX7-NEXT: buffer_store_dword v10, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[16:17] +; GFX7-NEXT: v_writelane_b32 v10, s30, 0 ; GFX7-NEXT: s_addk_i32 s32, 0x400 +; GFX7-NEXT: v_writelane_b32 v10, s31, 1 ; GFX7-NEXT: s_getpc_b64 s[16:17] ; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX7-NEXT: v_writelane_b32 v10, s30, 0 -; GFX7-NEXT: v_writelane_b32 v10, s31, 1 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v7 @@ -5558,13 +5562,13 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX7-NEXT: buffer_store_short v2, v3, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_add_i32_e32 v2, vcc, 2, v8 +; GFX7-NEXT: v_readlane_b32 s30, v10, 0 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX7-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: buffer_store_short v0, v8, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readlane_b32 s31, v10, 1 -; GFX7-NEXT: v_readlane_b32 s30, v10, 0 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX7-NEXT: buffer_load_dword v10, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5581,13 +5585,13 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX8-NEXT: buffer_store_dword v6, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[16:17] +; GFX8-NEXT: v_writelane_b32 v6, s30, 0 ; GFX8-NEXT: s_addk_i32 s32, 0x400 +; GFX8-NEXT: v_writelane_b32 v6, s31, 1 ; GFX8-NEXT: s_getpc_b64 s[16:17] ; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX8-NEXT: v_writelane_b32 v6, s30, 0 -; GFX8-NEXT: v_writelane_b32 v6, s31, 1 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX8-NEXT: v_add_u32_e32 v5, vcc, 12, v4 @@ -5597,12 +5601,12 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX8-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v4 +; GFX8-NEXT: v_readlane_b32 s30, v6, 0 ; GFX8-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readlane_b32 s31, v6, 1 -; GFX8-NEXT: v_readlane_b32 s30, v6, 0 ; GFX8-NEXT: s_mov_b32 s32, s33 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_load_dword v6, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5619,15 +5623,16 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX900-NEXT: buffer_store_dword v5, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[16:17] +; GFX900-NEXT: v_writelane_b32 v5, s30, 0 ; GFX900-NEXT: s_addk_i32 s32, 0x400 +; GFX900-NEXT: v_writelane_b32 v5, s31, 1 ; GFX900-NEXT: s_getpc_b64 s[16:17] ; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX900-NEXT: v_writelane_b32 v5, s30, 0 -; GFX900-NEXT: v_writelane_b32 v5, s31, 1 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX900-NEXT: v_readlane_b32 s30, v5, 0 ; GFX900-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:12 ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen offset:8 @@ -5637,7 +5642,6 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX900-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: v_readlane_b32 s31, v5, 1 -; GFX900-NEXT: v_readlane_b32 s30, v5, 0 ; GFX900-NEXT: s_mov_b32 s32, s33 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v5, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5654,19 +5658,20 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_store_dword off, v5, s33 ; 4-byte Folded Spill ; GFX950-NEXT: s_mov_b64 exec, s[0:1] +; GFX950-NEXT: v_writelane_b32 v5, s30, 0 ; GFX950-NEXT: s_add_i32 s32, s32, 16 +; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_writelane_b32 v5, s31, 1 ; GFX950-NEXT: s_getpc_b64 s[0:1] ; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 -; GFX950-NEXT: v_writelane_b32 v5, s30, 0 -; GFX950-NEXT: v_writelane_b32 v5, s31, 1 ; GFX950-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX950-NEXT: v_readlane_b32 s30, v5, 0 ; GFX950-NEXT: scratch_store_dwordx4 v4, v[0:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_readlane_b32 s31, v5, 1 -; GFX950-NEXT: v_readlane_b32 s30, v5, 0 ; GFX950-NEXT: s_mov_b32 s32, s33 ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_load_dword v5, off, s33 ; 4-byte Folded Reload @@ -5684,15 +5689,16 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX10-NEXT: buffer_store_dword v5, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s16 +; GFX10-NEXT: v_writelane_b32 v5, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v5, s31, 1 ; GFX10-NEXT: s_getpc_b64 s[16:17] ; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 -; GFX10-NEXT: v_writelane_b32 v5, s30, 0 ; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX10-NEXT: v_writelane_b32 v5, s31, 1 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX10-NEXT: v_readlane_b32 s30, v5, 0 ; GFX10-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:12 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen offset:8 @@ -5702,7 +5708,6 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: v_readlane_b32 s31, v5, 1 -; GFX10-NEXT: v_readlane_b32 s30, v5, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5720,19 +5725,19 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 +; GFX11-NEXT: v_writelane_b32 v5, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v5, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v5, s30, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: v_writelane_b32 v5, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: v_readlane_b32 s30, v5, 0 ; GFX11-NEXT: scratch_store_b128 v4, v[0:3], off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: v_readlane_b32 s31, v5, 1 -; GFX11-NEXT: v_readlane_b32 s30, v5, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v5, off, s33 ; 4-byte Folded Reload @@ -5751,18 +5756,18 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 -; GFX1250-NEXT: s_get_pc_i64 s[0:1] -; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16@gotpcrel+4 ; GFX1250-NEXT: v_writelane_b32 v5, s30, 0 -; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_add_co_i32 s32, s32, 16 ; GFX1250-NEXT: v_writelane_b32 v5, s31, 1 +; GFX1250-NEXT: s_get_pc_i64 s[0:1] +; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16@gotpcrel+4 +; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1] +; GFX1250-NEXT: v_readlane_b32 s30, v5, 0 ; GFX1250-NEXT: scratch_store_b128 v4, v[0:3], off scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_storecnt 0x0 ; GFX1250-NEXT: v_readlane_b32 s31, v5, 1 -; GFX1250-NEXT: v_readlane_b32 s30, v5, 0 ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 @@ -5876,8 +5881,8 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_store_short v0, v16, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_readlane_b32 s31, v20, 1 ; GCN-NEXT: v_readlane_b32 s30, v20, 0 +; GCN-NEXT: v_readlane_b32 s31, v20, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s33 ; 4-byte Folded Reload @@ -5894,13 +5899,13 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX7-NEXT: buffer_store_dword v18, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[16:17] +; GFX7-NEXT: v_writelane_b32 v18, s30, 0 ; GFX7-NEXT: s_addk_i32 s32, 0x400 +; GFX7-NEXT: v_writelane_b32 v18, s31, 1 ; GFX7-NEXT: s_getpc_b64 s[16:17] ; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX7-NEXT: v_writelane_b32 v18, s30, 0 -; GFX7-NEXT: v_writelane_b32 v18, s31, 1 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX7-NEXT: v_mul_f32_e32 v15, 1.0, v15 @@ -5977,13 +5982,13 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX7-NEXT: buffer_store_short v2, v3, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_add_i32_e32 v2, vcc, 2, v16 +; GFX7-NEXT: v_readlane_b32 s30, v18, 0 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX7-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: buffer_store_short v0, v16, s[0:3], 0 offen ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readlane_b32 s31, v18, 1 -; GFX7-NEXT: v_readlane_b32 s30, v18, 0 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX7-NEXT: buffer_load_dword v18, off, s[0:3], s33 ; 4-byte Folded Reload @@ -6000,13 +6005,13 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX8-NEXT: buffer_store_dword v10, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[16:17] +; GFX8-NEXT: v_writelane_b32 v10, s30, 0 ; GFX8-NEXT: s_addk_i32 s32, 0x400 +; GFX8-NEXT: v_writelane_b32 v10, s31, 1 ; GFX8-NEXT: s_getpc_b64 s[16:17] ; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX8-NEXT: v_writelane_b32 v10, s30, 0 -; GFX8-NEXT: v_writelane_b32 v10, s31, 1 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX8-NEXT: v_add_u32_e32 v9, vcc, 28, v8 @@ -6028,12 +6033,12 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX8-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v8 +; GFX8-NEXT: v_readlane_b32 s30, v10, 0 ; GFX8-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: buffer_store_dword v0, v8, s[0:3], 0 offen ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readlane_b32 s31, v10, 1 -; GFX8-NEXT: v_readlane_b32 s30, v10, 0 ; GFX8-NEXT: s_mov_b32 s32, s33 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_load_dword v10, off, s[0:3], s33 ; 4-byte Folded Reload @@ -6050,15 +6055,16 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; GFX900-NEXT: buffer_store_dword v9, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[16:17] +; GFX900-NEXT: v_writelane_b32 v9, s30, 0 ; GFX900-NEXT: s_addk_i32 s32, 0x400 +; GFX900-NEXT: v_writelane_b32 v9, s31, 1 ; GFX900-NEXT: s_getpc_b64 s[16:17] ; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX900-NEXT: v_writelane_b32 v9, s30, 0 -; GFX900-NEXT: v_writelane_b32 v9, s31, 1 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX900-NEXT: v_readlane_b32 s30, v9, 0 ; GFX900-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen offset:28 ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: buffer_store_dword v6, v8, s[0:3], 0 offen offset:24 @@ -6076,7 +6082,6 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX900-NEXT: buffer_store_dword v0, v8, s[0:3], 0 offen ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: v_readlane_b32 s31, v9, 1 -; GFX900-NEXT: v_readlane_b32 s30, v9, 0 ; GFX900-NEXT: s_mov_b32 s32, s33 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v9, off, s[0:3], s33 ; 4-byte Folded Reload @@ -6093,21 +6098,22 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_store_dword off, v9, s33 ; 4-byte Folded Spill ; GFX950-NEXT: s_mov_b64 exec, s[0:1] +; GFX950-NEXT: v_writelane_b32 v9, s30, 0 ; GFX950-NEXT: s_add_i32 s32, s32, 16 +; GFX950-NEXT: s_nop 0 +; GFX950-NEXT: v_writelane_b32 v9, s31, 1 ; GFX950-NEXT: s_getpc_b64 s[0:1] ; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16@gotpcrel32@hi+12 ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 -; GFX950-NEXT: v_writelane_b32 v9, s30, 0 -; GFX950-NEXT: v_writelane_b32 v9, s31, 1 ; GFX950-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX950-NEXT: v_readlane_b32 s30, v9, 0 ; GFX950-NEXT: scratch_store_dwordx4 v8, v[4:7], off offset:16 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: scratch_store_dwordx4 v8, v[0:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_readlane_b32 s31, v9, 1 -; GFX950-NEXT: v_readlane_b32 s30, v9, 0 ; GFX950-NEXT: s_mov_b32 s32, s33 ; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX950-NEXT: scratch_load_dword v9, off, s33 ; 4-byte Folded Reload @@ -6125,15 +6131,16 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX10-NEXT: buffer_store_dword v9, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s16 +; GFX10-NEXT: v_writelane_b32 v9, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v9, s31, 1 ; GFX10-NEXT: s_getpc_b64 s[16:17] ; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16@gotpcrel32@hi+12 -; GFX10-NEXT: v_writelane_b32 v9, s30, 0 ; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX10-NEXT: v_writelane_b32 v9, s31, 1 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX10-NEXT: v_readlane_b32 s30, v9, 0 ; GFX10-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen offset:28 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: buffer_store_dword v6, v8, s[0:3], 0 offen offset:24 @@ -6151,7 +6158,6 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX10-NEXT: buffer_store_dword v0, v8, s[0:3], 0 offen ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: v_readlane_b32 s31, v9, 1 -; GFX10-NEXT: v_readlane_b32 s30, v9, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10-NEXT: buffer_load_dword v9, off, s[0:3], s33 ; 4-byte Folded Reload @@ -6169,21 +6175,21 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v9, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 +; GFX11-NEXT: v_writelane_b32 v9, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v9, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v9, s30, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: v_writelane_b32 v9, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: v_readlane_b32 s30, v9, 0 ; GFX11-NEXT: scratch_store_b128 v8, v[4:7], off offset:16 dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: scratch_store_b128 v8, v[0:3], off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: v_readlane_b32 s31, v9, 1 -; GFX11-NEXT: v_readlane_b32 s30, v9, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v9, off, s33 ; 4-byte Folded Reload @@ -6202,20 +6208,20 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: scratch_store_b32 off, v9, s33 ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 -; GFX1250-NEXT: s_get_pc_i64 s[0:1] -; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16@gotpcrel+4 ; GFX1250-NEXT: v_writelane_b32 v9, s30, 0 -; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_add_co_i32 s32, s32, 16 ; GFX1250-NEXT: v_writelane_b32 v9, s31, 1 +; GFX1250-NEXT: s_get_pc_i64 s[0:1] +; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16@gotpcrel+4 +; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1] +; GFX1250-NEXT: v_readlane_b32 s30, v9, 0 ; GFX1250-NEXT: scratch_store_b128 v8, v[4:7], off offset:16 scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_storecnt 0x0 ; GFX1250-NEXT: scratch_store_b128 v8, v[0:3], off scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_storecnt 0x0 ; GFX1250-NEXT: v_readlane_b32 s31, v9, 1 -; GFX1250-NEXT: v_readlane_b32 s30, v9, 0 ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 @@ -9518,6 +9524,17 @@ define <32 x double> @global_extload_v32bf16_to_v32f64(ptr addrspace(1) %ptr) { ; GFX8-LABEL: global_extload_v32bf16_to_v32f64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v58, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 2, v1 ; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc ; GFX8-NEXT: v_add_u32_e32 v5, vcc, 4, v1 @@ -9552,17 +9569,6 @@ define <32 x double> @global_extload_v32bf16_to_v32f64(ptr addrspace(1) %ptr) { ; GFX8-NEXT: v_addc_u32_e32 v34, vcc, 0, v2, vcc ; GFX8-NEXT: v_add_u32_e32 v35, vcc, 36, v1 ; GFX8-NEXT: v_addc_u32_e32 v36, vcc, 0, v2, vcc -; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v58, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX8-NEXT: v_add_u32_e32 v37, vcc, 38, v1 ; GFX8-NEXT: flat_load_ushort v44, v[1:2] ; GFX8-NEXT: v_addc_u32_e32 v38, vcc, 0, v2, vcc @@ -10021,16 +10027,21 @@ define <32 x double> @global_extload_v32bf16_to_v32f64(ptr addrspace(1) %ptr) { ; GFX950-LABEL: global_extload_v32bf16_to_v32f64: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX950-NEXT: v_mov_b32_e32 v3, v2 -; GFX950-NEXT: v_mov_b32_e32 v2, v1 +; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse +; GFX950-NEXT: v_mov_b32_e32 v3, v2 +; GFX950-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-NEXT: global_load_ushort v1, v[2:3], off offset:2 ; GFX950-NEXT: global_load_ushort v4, v[2:3], off offset:12 ; GFX950-NEXT: global_load_ushort v5, v[2:3], off offset:8 @@ -10063,11 +10074,6 @@ define <32 x double> @global_extload_v32bf16_to_v32f64(ptr addrspace(1) %ptr) { ; GFX950-NEXT: global_load_ushort v56, v[2:3], off offset:48 ; GFX950-NEXT: global_load_ushort v57, v[2:3], off offset:54 ; GFX950-NEXT: global_load_ushort v58, v[2:3], off offset:58 -; GFX950-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse ; GFX950-NEXT: s_waitcnt vmcnt(31) ; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX950-NEXT: s_waitcnt vmcnt(30) @@ -14251,12 +14257,12 @@ define <32 x bfloat> @v_fadd_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX950-LABEL: v_fadd_v32bf16: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse ; GFX950-NEXT: scratch_load_dword v31, off, s32 ; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v24 ; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v8 ; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24 ; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 ; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v23 ; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v7 @@ -19959,12 +19965,12 @@ define <32 x bfloat> @v_fmul_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX950-LABEL: v_fmul_v32bf16: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse ; GFX950-NEXT: scratch_load_dword v31, off, s32 ; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v24 ; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v8 ; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24 ; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 ; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v23 ; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v7 @@ -25150,12 +25156,12 @@ define <32 x bfloat> @v_minnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX950-LABEL: v_minnum_v32bf16: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse ; GFX950-NEXT: scratch_load_dword v31, off, s32 ; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v24 ; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v8 ; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24 ; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 ; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v23 ; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v7 @@ -29726,12 +29732,12 @@ define <32 x bfloat> @v_maxnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) { ; GFX950-LABEL: v_maxnum_v32bf16: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse ; GFX950-NEXT: scratch_load_dword v31, off, s32 ; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v24 ; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v8 ; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24 ; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v32, 0xffff0000, v15 ; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v23 ; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v7 @@ -48809,6 +48815,14 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_writelane_b32 v34, s34, 0 +; GFX8-NEXT: v_writelane_b32 v34, s35, 1 +; GFX8-NEXT: v_writelane_b32 v34, s36, 2 +; GFX8-NEXT: v_writelane_b32 v34, s37, 3 +; GFX8-NEXT: v_writelane_b32 v34, s38, 4 +; GFX8-NEXT: v_writelane_b32 v34, s39, 5 +; GFX8-NEXT: v_writelane_b32 v34, s30, 6 +; GFX8-NEXT: v_writelane_b32 v34, s31, 7 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v1 @@ -48860,26 +48874,18 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_and_b32_e32 v0, 1, v24 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[76:77], 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v25 -; GFX8-NEXT: v_writelane_b32 v34, s30, 0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[78:79], 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v26 -; GFX8-NEXT: v_writelane_b32 v34, s31, 1 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[88:89], 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v27 -; GFX8-NEXT: v_writelane_b32 v34, s34, 2 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[90:91], 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v28 -; GFX8-NEXT: v_writelane_b32 v34, s35, 3 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v29 -; GFX8-NEXT: v_writelane_b32 v34, s36, 4 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v30 -; GFX8-NEXT: v_writelane_b32 v34, s37, 5 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v0 ; GFX8-NEXT: buffer_load_ushort v0, off, s[0:3], s32 -; GFX8-NEXT: v_writelane_b32 v34, s38, 6 -; GFX8-NEXT: v_writelane_b32 v34, s39, 7 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v0 @@ -49005,6 +49011,7 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v28 ; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v26 ; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v24 +; GFX8-NEXT: v_readlane_b32 s30, v34, 6 ; GFX8-NEXT: v_or_b32_sdwa v8, v16, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_or_b32_sdwa v9, v18, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_or_b32_sdwa v10, v20, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD @@ -49013,14 +49020,13 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX8-NEXT: v_or_b32_sdwa v13, v29, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_or_b32_sdwa v14, v27, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_or_b32_sdwa v15, v25, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_readlane_b32 s39, v34, 7 -; GFX8-NEXT: v_readlane_b32 s38, v34, 6 -; GFX8-NEXT: v_readlane_b32 s37, v34, 5 -; GFX8-NEXT: v_readlane_b32 s36, v34, 4 -; GFX8-NEXT: v_readlane_b32 s35, v34, 3 -; GFX8-NEXT: v_readlane_b32 s34, v34, 2 -; GFX8-NEXT: v_readlane_b32 s31, v34, 1 -; GFX8-NEXT: v_readlane_b32 s30, v34, 0 +; GFX8-NEXT: v_readlane_b32 s31, v34, 7 +; GFX8-NEXT: v_readlane_b32 s39, v34, 5 +; GFX8-NEXT: v_readlane_b32 s38, v34, 4 +; GFX8-NEXT: v_readlane_b32 s37, v34, 3 +; GFX8-NEXT: v_readlane_b32 s36, v34, 2 +; GFX8-NEXT: v_readlane_b32 s35, v34, 1 +; GFX8-NEXT: v_readlane_b32 s34, v34, 0 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; GFX8-NEXT: s_mov_b64 exec, s[4:5] @@ -49033,6 +49039,10 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] +; GFX900-NEXT: v_writelane_b32 v33, s34, 0 +; GFX900-NEXT: v_writelane_b32 v33, s35, 1 +; GFX900-NEXT: v_writelane_b32 v33, s30, 2 +; GFX900-NEXT: v_writelane_b32 v33, s31, 3 ; GFX900-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX900-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0 ; GFX900-NEXT: v_and_b32_e32 v0, 1, v3 @@ -49092,11 +49102,7 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX900-NEXT: v_and_b32_e32 v0, 1, v28 ; GFX900-NEXT: v_cmp_eq_u32_e64 s[94:95], 1, v0 ; GFX900-NEXT: buffer_load_ushort v0, off, s[0:3], s32 -; GFX900-NEXT: v_writelane_b32 v33, s30, 0 -; GFX900-NEXT: v_writelane_b32 v33, s31, 1 -; GFX900-NEXT: v_writelane_b32 v33, s34, 2 ; GFX900-NEXT: v_and_b32_e32 v1, 1, v1 -; GFX900-NEXT: v_writelane_b32 v33, s35, 3 ; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: v_and_b32_e32 v0, 1, v0 @@ -49201,6 +49207,7 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX900-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 +; GFX900-NEXT: v_readlane_b32 s30, v33, 2 ; GFX900-NEXT: v_perm_b32 v0, v0, v3, s4 ; GFX900-NEXT: v_perm_b32 v1, v2, v5, s4 ; GFX900-NEXT: v_perm_b32 v2, v4, v7, s4 @@ -49217,10 +49224,9 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX900-NEXT: v_perm_b32 v13, v26, v29, s4 ; GFX900-NEXT: v_perm_b32 v14, v28, v32, s4 ; GFX900-NEXT: v_perm_b32 v15, v31, v30, s4 -; GFX900-NEXT: v_readlane_b32 s35, v33, 3 -; GFX900-NEXT: v_readlane_b32 s34, v33, 2 -; GFX900-NEXT: v_readlane_b32 s31, v33, 1 -; GFX900-NEXT: v_readlane_b32 s30, v33, 0 +; GFX900-NEXT: v_readlane_b32 s31, v33, 3 +; GFX900-NEXT: v_readlane_b32 s35, v33, 1 +; GFX900-NEXT: v_readlane_b32 s34, v33, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -49236,6 +49242,12 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX950-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse ; GFX950-NEXT: scratch_load_dword v31, off, s32 offset:60 ; GFX950-NEXT: scratch_load_dword v32, off, s32 offset:124 ; GFX950-NEXT: scratch_load_ushort v33, off, s32 @@ -49260,17 +49272,11 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX950-NEXT: scratch_load_dword v44, off, s32 offset:104 ; GFX950-NEXT: scratch_load_dword v45, off, s32 offset:40 ; GFX950-NEXT: v_and_b32_e32 v29, 1, v29 -; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse ; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v29 ; GFX950-NEXT: scratch_load_dword v29, off, s32 offset:84 ; GFX950-NEXT: scratch_load_dword v56, off, s32 offset:20 ; GFX950-NEXT: v_and_b32_e32 v28, 1, v28 -; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse ; GFX950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v28 -; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v26, 1, v26 ; GFX950-NEXT: v_and_b32_e32 v27, 1, v27 ; GFX950-NEXT: v_and_b32_e32 v24, 1, v24 @@ -54689,6 +54695,22 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf ; GFX950-LABEL: v_fma_v32bf16: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse ; GFX950-NEXT: scratch_load_dword v35, off, s32 offset:64 ; GFX950-NEXT: scratch_load_dword v36, off, s32 ; GFX950-NEXT: scratch_load_dword v38, off, s32 offset:60 @@ -54706,14 +54728,6 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf ; GFX950-NEXT: scratch_load_dword v34, off, s32 offset:16 ; GFX950-NEXT: scratch_load_dword v37, off, s32 offset:20 ; GFX950-NEXT: scratch_load_dword v55, off, s32 offset:24 -; GFX950-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v43, 0xffff0000, v14 ; GFX950-NEXT: v_lshlrev_b32_e32 v45, 16, v14 ; GFX950-NEXT: v_and_b32_e32 v46, 0xffff0000, v29 @@ -54722,20 +54736,12 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf ; GFX950-NEXT: v_lshlrev_b32_e32 v61, 16, v12 ; GFX950-NEXT: v_and_b32_e32 v62, 0xffff0000, v27 ; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v30 ; GFX950-NEXT: v_lshlrev_b32_e32 v44, 16, v30 ; GFX950-NEXT: v_and_b32_e32 v47, 0xffff0000, v13 ; GFX950-NEXT: v_lshlrev_b32_e32 v57, 16, v13 -; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v15 ; GFX950-NEXT: v_lshlrev_b32_e32 v41, 16, v15 -; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v58, 0xffff0000, v28 ; GFX950-NEXT: v_lshlrev_b32_e32 v60, 16, v28 ; GFX950-NEXT: s_waitcnt vmcnt(16) diff --git a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll index d89b39348ad9a..863177ae3d6b5 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll @@ -7,6 +7,8 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64 ; GFX90A-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr17, $sgpr12_sgpr13 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX90A-NEXT: $sgpr32 = S_MOV_B32 0 ; GFX90A-NEXT: $flat_scr_lo = S_ADD_U32 $sgpr12, $sgpr17, implicit-def $scc ; GFX90A-NEXT: $flat_scr_hi = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll index ab2ad19d0f1bf..2f6f9e45cafbf 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll @@ -902,47 +902,47 @@ define void @spill_func(ptr addrspace(1) %arg) #0 { ; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[4:5] ; CHECK-NEXT: s_waitcnt expcnt(0) -; CHECK-NEXT: v_writelane_b32 v0, s30, 0 -; CHECK-NEXT: v_writelane_b32 v0, s31, 1 -; CHECK-NEXT: v_writelane_b32 v0, s33, 2 -; CHECK-NEXT: v_writelane_b32 v0, s34, 3 -; CHECK-NEXT: v_writelane_b32 v0, s35, 4 -; CHECK-NEXT: v_writelane_b32 v0, s36, 5 -; CHECK-NEXT: v_writelane_b32 v0, s37, 6 -; CHECK-NEXT: v_writelane_b32 v0, s38, 7 -; CHECK-NEXT: v_writelane_b32 v0, s39, 8 -; CHECK-NEXT: v_writelane_b32 v0, s48, 9 -; CHECK-NEXT: v_writelane_b32 v0, s49, 10 -; CHECK-NEXT: v_writelane_b32 v0, s50, 11 -; CHECK-NEXT: v_writelane_b32 v0, s51, 12 -; CHECK-NEXT: v_writelane_b32 v0, s52, 13 -; CHECK-NEXT: v_writelane_b32 v0, s53, 14 -; CHECK-NEXT: v_writelane_b32 v0, s54, 15 -; CHECK-NEXT: v_writelane_b32 v0, s55, 16 -; CHECK-NEXT: v_writelane_b32 v0, s64, 17 -; CHECK-NEXT: v_writelane_b32 v0, s65, 18 -; CHECK-NEXT: v_writelane_b32 v0, s66, 19 -; CHECK-NEXT: v_writelane_b32 v0, s67, 20 -; CHECK-NEXT: v_writelane_b32 v0, s68, 21 -; CHECK-NEXT: v_writelane_b32 v0, s69, 22 -; CHECK-NEXT: v_writelane_b32 v0, s70, 23 -; CHECK-NEXT: v_writelane_b32 v0, s71, 24 -; CHECK-NEXT: v_writelane_b32 v0, s80, 25 -; CHECK-NEXT: v_writelane_b32 v0, s81, 26 -; CHECK-NEXT: v_writelane_b32 v0, s82, 27 -; CHECK-NEXT: v_writelane_b32 v0, s83, 28 -; CHECK-NEXT: v_writelane_b32 v0, s84, 29 -; CHECK-NEXT: v_writelane_b32 v0, s85, 30 -; CHECK-NEXT: v_writelane_b32 v0, s86, 31 -; CHECK-NEXT: v_writelane_b32 v0, s87, 32 -; CHECK-NEXT: v_writelane_b32 v0, s96, 33 -; CHECK-NEXT: v_writelane_b32 v0, s97, 34 -; CHECK-NEXT: v_writelane_b32 v0, s98, 35 -; CHECK-NEXT: v_writelane_b32 v0, s99, 36 +; CHECK-NEXT: v_writelane_b32 v0, s33, 0 +; CHECK-NEXT: v_writelane_b32 v0, s34, 1 +; CHECK-NEXT: v_writelane_b32 v0, s35, 2 +; CHECK-NEXT: v_writelane_b32 v0, s36, 3 +; CHECK-NEXT: v_writelane_b32 v0, s37, 4 +; CHECK-NEXT: v_writelane_b32 v0, s38, 5 +; CHECK-NEXT: v_writelane_b32 v0, s39, 6 +; CHECK-NEXT: v_writelane_b32 v0, s48, 7 +; CHECK-NEXT: v_writelane_b32 v0, s49, 8 +; CHECK-NEXT: v_writelane_b32 v0, s50, 9 +; CHECK-NEXT: v_writelane_b32 v0, s51, 10 +; CHECK-NEXT: v_writelane_b32 v0, s52, 11 +; CHECK-NEXT: v_writelane_b32 v0, s53, 12 +; CHECK-NEXT: v_writelane_b32 v0, s54, 13 +; CHECK-NEXT: v_writelane_b32 v0, s55, 14 +; CHECK-NEXT: v_writelane_b32 v0, s64, 15 +; CHECK-NEXT: v_writelane_b32 v0, s65, 16 +; CHECK-NEXT: v_writelane_b32 v0, s66, 17 +; CHECK-NEXT: v_writelane_b32 v0, s67, 18 +; CHECK-NEXT: v_writelane_b32 v0, s68, 19 +; CHECK-NEXT: v_writelane_b32 v0, s69, 20 +; CHECK-NEXT: v_writelane_b32 v0, s70, 21 +; CHECK-NEXT: v_writelane_b32 v0, s71, 22 +; CHECK-NEXT: v_writelane_b32 v0, s80, 23 +; CHECK-NEXT: v_writelane_b32 v0, s81, 24 +; CHECK-NEXT: v_writelane_b32 v0, s82, 25 +; CHECK-NEXT: v_writelane_b32 v0, s83, 26 +; CHECK-NEXT: v_writelane_b32 v0, s84, 27 +; CHECK-NEXT: v_writelane_b32 v0, s85, 28 +; CHECK-NEXT: v_writelane_b32 v0, s86, 29 +; CHECK-NEXT: v_writelane_b32 v0, s87, 30 +; CHECK-NEXT: v_writelane_b32 v0, s96, 31 +; CHECK-NEXT: v_writelane_b32 v0, s97, 32 +; CHECK-NEXT: v_writelane_b32 v0, s98, 33 +; CHECK-NEXT: v_writelane_b32 v0, s99, 34 +; CHECK-NEXT: v_writelane_b32 v0, s100, 35 +; CHECK-NEXT: v_writelane_b32 v0, s101, 36 +; CHECK-NEXT: v_writelane_b32 v0, s30, 37 +; CHECK-NEXT: v_writelane_b32 v0, s31, 38 ; CHECK-NEXT: s_mov_b32 s40, s12 -; CHECK-NEXT: v_writelane_b32 v0, s100, 37 ; CHECK-NEXT: s_cmp_eq_u32 s40, 0 -; CHECK-NEXT: v_writelane_b32 v0, s101, 38 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: s_mov_b32 s0, 0 ; CHECK-NEXT: ;;#ASMEND @@ -1380,6 +1380,7 @@ define void @spill_func(ptr addrspace(1) %arg) #0 { ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ; reg use s31 ; CHECK-NEXT: ;;#ASMEND +; CHECK-NEXT: v_readlane_b32 s30, v0, 37 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ; reg use s32 ; CHECK-NEXT: ;;#ASMEND @@ -1596,45 +1597,44 @@ define void @spill_func(ptr addrspace(1) %arg) #0 { ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ; reg use vcc_hi ; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: v_readlane_b32 s101, v0, 38 -; CHECK-NEXT: v_readlane_b32 s100, v0, 37 -; CHECK-NEXT: v_readlane_b32 s99, v0, 36 -; CHECK-NEXT: v_readlane_b32 s98, v0, 35 -; CHECK-NEXT: v_readlane_b32 s97, v0, 34 -; CHECK-NEXT: v_readlane_b32 s96, v0, 33 -; CHECK-NEXT: v_readlane_b32 s87, v0, 32 -; CHECK-NEXT: v_readlane_b32 s86, v0, 31 -; CHECK-NEXT: v_readlane_b32 s85, v0, 30 -; CHECK-NEXT: v_readlane_b32 s84, v0, 29 -; CHECK-NEXT: v_readlane_b32 s83, v0, 28 -; CHECK-NEXT: v_readlane_b32 s82, v0, 27 -; CHECK-NEXT: v_readlane_b32 s81, v0, 26 -; CHECK-NEXT: v_readlane_b32 s80, v0, 25 -; CHECK-NEXT: v_readlane_b32 s71, v0, 24 -; CHECK-NEXT: v_readlane_b32 s70, v0, 23 -; CHECK-NEXT: v_readlane_b32 s69, v0, 22 -; CHECK-NEXT: v_readlane_b32 s68, v0, 21 -; CHECK-NEXT: v_readlane_b32 s67, v0, 20 -; CHECK-NEXT: v_readlane_b32 s66, v0, 19 -; CHECK-NEXT: v_readlane_b32 s65, v0, 18 -; CHECK-NEXT: v_readlane_b32 s64, v0, 17 -; CHECK-NEXT: v_readlane_b32 s55, v0, 16 -; CHECK-NEXT: v_readlane_b32 s54, v0, 15 -; CHECK-NEXT: v_readlane_b32 s53, v0, 14 -; CHECK-NEXT: v_readlane_b32 s52, v0, 13 -; CHECK-NEXT: v_readlane_b32 s51, v0, 12 -; CHECK-NEXT: v_readlane_b32 s50, v0, 11 -; CHECK-NEXT: v_readlane_b32 s49, v0, 10 -; CHECK-NEXT: v_readlane_b32 s48, v0, 9 -; CHECK-NEXT: v_readlane_b32 s39, v0, 8 -; CHECK-NEXT: v_readlane_b32 s38, v0, 7 -; CHECK-NEXT: v_readlane_b32 s37, v0, 6 -; CHECK-NEXT: v_readlane_b32 s36, v0, 5 -; CHECK-NEXT: v_readlane_b32 s35, v0, 4 -; CHECK-NEXT: v_readlane_b32 s34, v0, 3 -; CHECK-NEXT: v_readlane_b32 s33, v0, 2 -; CHECK-NEXT: v_readlane_b32 s31, v0, 1 -; CHECK-NEXT: v_readlane_b32 s30, v0, 0 +; CHECK-NEXT: v_readlane_b32 s31, v0, 38 +; CHECK-NEXT: v_readlane_b32 s101, v0, 36 +; CHECK-NEXT: v_readlane_b32 s100, v0, 35 +; CHECK-NEXT: v_readlane_b32 s99, v0, 34 +; CHECK-NEXT: v_readlane_b32 s98, v0, 33 +; CHECK-NEXT: v_readlane_b32 s97, v0, 32 +; CHECK-NEXT: v_readlane_b32 s96, v0, 31 +; CHECK-NEXT: v_readlane_b32 s87, v0, 30 +; CHECK-NEXT: v_readlane_b32 s86, v0, 29 +; CHECK-NEXT: v_readlane_b32 s85, v0, 28 +; CHECK-NEXT: v_readlane_b32 s84, v0, 27 +; CHECK-NEXT: v_readlane_b32 s83, v0, 26 +; CHECK-NEXT: v_readlane_b32 s82, v0, 25 +; CHECK-NEXT: v_readlane_b32 s81, v0, 24 +; CHECK-NEXT: v_readlane_b32 s80, v0, 23 +; CHECK-NEXT: v_readlane_b32 s71, v0, 22 +; CHECK-NEXT: v_readlane_b32 s70, v0, 21 +; CHECK-NEXT: v_readlane_b32 s69, v0, 20 +; CHECK-NEXT: v_readlane_b32 s68, v0, 19 +; CHECK-NEXT: v_readlane_b32 s67, v0, 18 +; CHECK-NEXT: v_readlane_b32 s66, v0, 17 +; CHECK-NEXT: v_readlane_b32 s65, v0, 16 +; CHECK-NEXT: v_readlane_b32 s64, v0, 15 +; CHECK-NEXT: v_readlane_b32 s55, v0, 14 +; CHECK-NEXT: v_readlane_b32 s54, v0, 13 +; CHECK-NEXT: v_readlane_b32 s53, v0, 12 +; CHECK-NEXT: v_readlane_b32 s52, v0, 11 +; CHECK-NEXT: v_readlane_b32 s51, v0, 10 +; CHECK-NEXT: v_readlane_b32 s50, v0, 9 +; CHECK-NEXT: v_readlane_b32 s49, v0, 8 +; CHECK-NEXT: v_readlane_b32 s48, v0, 7 +; CHECK-NEXT: v_readlane_b32 s39, v0, 6 +; CHECK-NEXT: v_readlane_b32 s38, v0, 5 +; CHECK-NEXT: v_readlane_b32 s37, v0, 4 +; CHECK-NEXT: v_readlane_b32 s36, v0, 3 +; CHECK-NEXT: v_readlane_b32 s35, v0, 2 +; CHECK-NEXT: v_readlane_b32 s34, v0, 1 +; CHECK-NEXT: v_readlane_b32 s33, v0, 0 ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; CHECK-NEXT: s_mov_b64 exec, s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir b/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir index 7336a54ae42db..72b6b9f9ec686 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir @@ -19,11 +19,17 @@ body: | ; GCN-NEXT: successors: %bb.1(0x80000000) ; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $agpr0 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: $vgpr63 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $agpr0, 0 ; GCN-NEXT: $exec = S_MOV_B64 -1 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr62, 256 ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: renamable $vgpr62 = IMPLICIT_DEF ; GCN-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr15, 0, killed $vgpr62 diff --git a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll index d1cede64ce71d..445250d4e77e4 100644 --- a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll +++ b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll @@ -41,16 +41,16 @@ define void @test_call_external_void_func_i8_inreg(i8 inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-NEXT: v_writelane_b32 v40, s17, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_i8_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_i8_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -69,16 +69,16 @@ define void @test_call_external_void_func_i8_inreg(i8 inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i8_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i8_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -101,16 +101,16 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-NEXT: v_writelane_b32 v40, s17, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_i16_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_i16_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -129,16 +129,16 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i16_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -161,16 +161,16 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-NEXT: v_writelane_b32 v40, s17, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_i32_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_i32_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -189,16 +189,16 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i32_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -221,17 +221,17 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] ; GFX9-NEXT: v_writelane_b32 v40, s18, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_i64_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_i64_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -250,16 +250,16 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i64_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i64_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -282,17 +282,17 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] ; GFX9-NEXT: v_writelane_b32 v40, s18, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v2i32_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v2i32_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -311,16 +311,16 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2i32_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -343,18 +343,18 @@ define void @test_call_external_void_func_v3i32_inreg(<3 x i32> inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] ; GFX9-NEXT: v_writelane_b32 v40, s19, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[20:21] ; GFX9-NEXT: s_add_u32 s20, s20, external_void_func_v3i32_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s21, s21, external_void_func_v3i32_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s2, s18 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -373,16 +373,16 @@ define void @test_call_external_void_func_v3i32_inreg(<3 x i32> inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s16 ; GFX11-NEXT: v_writelane_b32 v40, s3, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[16:17] ; GFX11-NEXT: s_add_u32 s16, s16, external_void_func_v3i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s17, s17, external_void_func_v3i32_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -405,8 +405,9 @@ define void @test_call_external_void_func_v4i32_inreg(<4 x i32> inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[22:23] ; GFX9-NEXT: v_writelane_b32 v40, s20, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[20:21] ; GFX9-NEXT: s_add_u32 s20, s20, external_void_func_v4i32_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s21, s21, external_void_func_v4i32_inreg@rel32@hi+12 @@ -414,10 +415,9 @@ define void @test_call_external_void_func_v4i32_inreg(<4 x i32> inreg %arg) #0 { ; GFX9-NEXT: s_mov_b32 s2, s18 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -436,16 +436,16 @@ define void @test_call_external_void_func_v4i32_inreg(<4 x i32> inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s17 ; GFX11-NEXT: v_writelane_b32 v40, s16, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[16:17] ; GFX11-NEXT: s_add_u32 s16, s16, external_void_func_v4i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s17, s17, external_void_func_v4i32_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -468,8 +468,9 @@ define void @test_call_external_void_func_v8i32_inreg(<8 x i32> inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[26:27] ; GFX9-NEXT: v_writelane_b32 v40, s24, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[24:25] ; GFX9-NEXT: s_add_u32 s24, s24, external_void_func_v8i32_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s25, s25, external_void_func_v8i32_inreg@rel32@hi+12 @@ -481,10 +482,9 @@ define void @test_call_external_void_func_v8i32_inreg(<8 x i32> inreg %arg) #0 { ; GFX9-NEXT: s_mov_b32 s17, s21 ; GFX9-NEXT: s_mov_b32 s18, s22 ; GFX9-NEXT: s_mov_b32 s19, s23 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[24:25] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -503,16 +503,16 @@ define void @test_call_external_void_func_v8i32_inreg(<8 x i32> inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s21 ; GFX11-NEXT: v_writelane_b32 v40, s20, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[20:21] ; GFX11-NEXT: s_add_u32 s20, s20, external_void_func_v8i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s21, s21, external_void_func_v8i32_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[20:21] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -535,16 +535,16 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-NEXT: v_writelane_b32 v40, s17, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_f16_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_f16_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -563,16 +563,16 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_f16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_f16_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -595,16 +595,16 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-NEXT: v_writelane_b32 v40, s17, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_bf16_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_bf16_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -623,16 +623,16 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_bf16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_bf16_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -655,16 +655,16 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-NEXT: v_writelane_b32 v40, s17, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_f32_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_f32_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -683,16 +683,16 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_f32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_f32_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -715,17 +715,17 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] ; GFX9-NEXT: v_writelane_b32 v40, s18, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_f64_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_f64_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -744,16 +744,16 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_f64_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_f64_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -776,16 +776,16 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-NEXT: v_writelane_b32 v40, s17, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v2f16_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v2f16_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -804,16 +804,16 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2f16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2f16_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -837,16 +837,16 @@ define void @test_call_external_void_func_v2bf16_inreg(<2 x bfloat> inreg %arg) ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-NEXT: v_writelane_b32 v40, s17, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v2bf16_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v2bf16_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -865,16 +865,16 @@ define void @test_call_external_void_func_v2bf16_inreg(<2 x bfloat> inreg %arg) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2bf16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2bf16_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -897,17 +897,17 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] ; GFX9-NEXT: v_writelane_b32 v40, s18, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v3f16_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v3f16_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -926,16 +926,16 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v3f16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v3f16_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -958,17 +958,17 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] ; GFX9-NEXT: v_writelane_b32 v40, s18, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v4f16_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v4f16_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -987,16 +987,16 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v4f16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v4f16_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1019,17 +1019,17 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] ; GFX9-NEXT: v_writelane_b32 v40, s18, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_p0_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_p0_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -1048,16 +1048,16 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_p0_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_p0_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1080,17 +1080,17 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg) ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] ; GFX9-NEXT: v_writelane_b32 v40, s18, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_p1_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_p1_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -1109,16 +1109,16 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_p1_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_p1_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1141,16 +1141,16 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg) ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-NEXT: v_writelane_b32 v40, s17, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_p3_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_p3_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -1169,16 +1169,16 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_p3_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_p3_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1201,8 +1201,9 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[22:23] ; GFX9-NEXT: v_writelane_b32 v40, s20, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[20:21] ; GFX9-NEXT: s_add_u32 s20, s20, external_void_func_v2p1_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s21, s21, external_void_func_v2p1_inreg@rel32@hi+12 @@ -1210,10 +1211,9 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre ; GFX9-NEXT: s_mov_b32 s2, s18 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -1232,16 +1232,16 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s17 ; GFX11-NEXT: v_writelane_b32 v40, s16, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[16:17] ; GFX11-NEXT: s_add_u32 s16, s16, external_void_func_v2p1_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s17, s17, external_void_func_v2p1_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1264,17 +1264,17 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] ; GFX9-NEXT: v_writelane_b32 v40, s18, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[18:19] ; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v2p5_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v2p5_inreg@rel32@hi+12 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -1293,16 +1293,16 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2p5_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2p5_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1325,8 +1325,9 @@ define void @test_call_external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inre ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[22:23] ; GFX9-NEXT: v_writelane_b32 v40, s21, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[22:23] ; GFX9-NEXT: s_add_u32 s22, s22, external_void_func_i64_inreg_i32_inreg_i64_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s23, s23, external_void_func_i64_inreg_i32_inreg_i64_inreg@rel32@hi+12 @@ -1335,10 +1336,9 @@ define void @test_call_external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inre ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 ; GFX9-NEXT: s_mov_b32 s16, s20 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[22:23] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -1357,16 +1357,16 @@ define void @test_call_external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s18 ; GFX11-NEXT: v_writelane_b32 v40, s17, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[18:19] ; GFX11-NEXT: s_add_u32 s18, s18, external_void_func_i64_inreg_i32_inreg_i64_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s19, s19, external_void_func_i64_inreg_i32_inreg_i64_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1389,8 +1389,9 @@ define void @test_call_external_void_func_a15i32_inreg([13 x i32] inreg %arg0) # ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[40:41] ; GFX9-NEXT: v_writelane_b32 v40, s29, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[40:41] ; GFX9-NEXT: s_add_u32 s40, s40, external_void_func_a15i32_inreg@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s41, s41, external_void_func_a15i32_inreg@rel32@hi+12 @@ -1407,10 +1408,9 @@ define void @test_call_external_void_func_a15i32_inreg([13 x i32] inreg %arg0) # ; GFX9-NEXT: s_mov_b32 s22, s26 ; GFX9-NEXT: s_mov_b32 s23, s27 ; GFX9-NEXT: s_mov_b32 s24, s28 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[40:41] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -1429,16 +1429,16 @@ define void @test_call_external_void_func_a15i32_inreg([13 x i32] inreg %arg0) # ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s26 ; GFX11-NEXT: v_writelane_b32 v40, s25, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[26:27] ; GFX11-NEXT: s_add_u32 s26, s26, external_void_func_a15i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s27, s27, external_void_func_a15i32_inreg@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[26:27] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1463,8 +1463,9 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inre ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[22:23] ; GFX9-NEXT: v_writelane_b32 v40, s21, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[22:23] ; GFX9-NEXT: s_add_u32 s22, s22, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@lo+4 ; GFX9-NEXT: s_addc_u32 s23, s23, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@hi+12 @@ -1482,10 +1483,9 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inre ; GFX9-NEXT: s_mov_b32 s11, s18 ; GFX9-NEXT: s_mov_b32 s15, s19 ; GFX9-NEXT: s_mov_b32 s16, s20 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[22:23] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -1504,16 +1504,16 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s18 ; GFX11-NEXT: v_writelane_b32 v40, s17, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[18:19] ; GFX11-NEXT: s_add_u32 s18, s18, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s19, s19, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll index 8e12e7e03947b..4e0b16792aad4 100644 --- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll +++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll @@ -5852,7 +5852,10 @@ define void @stack_12xv3i32() #0 { ; VI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[8:9] +; VI-NEXT: v_writelane_b32 v40, s4, 2 +; VI-NEXT: v_writelane_b32 v40, s30, 0 ; VI-NEXT: s_addk_i32 s32, 0x400 +; VI-NEXT: v_writelane_b32 v40, s31, 1 ; VI-NEXT: v_mov_b32_e32 v0, 11 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; VI-NEXT: v_mov_b32_e32 v0, 12 @@ -5860,10 +5863,8 @@ define void @stack_12xv3i32() #0 { ; VI-NEXT: v_mov_b32_e32 v0, 13 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; VI-NEXT: v_mov_b32_e32 v0, 14 -; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; VI-NEXT: v_mov_b32_e32 v0, 15 -; VI-NEXT: v_writelane_b32 v40, s30, 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; VI-NEXT: s_getpc_b64 s[4:5] ; VI-NEXT: s_add_u32 s4, s4, external_void_func_12xv3i32@rel32@lo+4 @@ -5899,10 +5900,9 @@ define void @stack_12xv3i32() #0 { ; VI-NEXT: v_mov_b32_e32 v28, 9 ; VI-NEXT: v_mov_b32_e32 v29, 9 ; VI-NEXT: v_mov_b32_e32 v30, 10 -; VI-NEXT: v_writelane_b32 v40, s31, 1 ; VI-NEXT: s_swappc_b64 s[30:31], s[4:5] -; VI-NEXT: v_readlane_b32 s31, v40, 1 ; VI-NEXT: v_readlane_b32 s30, v40, 0 +; VI-NEXT: v_readlane_b32 s31, v40, 1 ; VI-NEXT: s_mov_b32 s32, s33 ; VI-NEXT: v_readlane_b32 s4, v40, 2 ; VI-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -5920,7 +5920,10 @@ define void @stack_12xv3i32() #0 { ; CI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CI-NEXT: s_mov_b64 exec, s[8:9] +; CI-NEXT: v_writelane_b32 v40, s4, 2 +; CI-NEXT: v_writelane_b32 v40, s30, 0 ; CI-NEXT: s_addk_i32 s32, 0x400 +; CI-NEXT: v_writelane_b32 v40, s31, 1 ; CI-NEXT: v_mov_b32_e32 v0, 11 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; CI-NEXT: v_mov_b32_e32 v0, 12 @@ -5928,10 +5931,8 @@ define void @stack_12xv3i32() #0 { ; CI-NEXT: v_mov_b32_e32 v0, 13 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; CI-NEXT: v_mov_b32_e32 v0, 14 -; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; CI-NEXT: v_mov_b32_e32 v0, 15 -; CI-NEXT: v_writelane_b32 v40, s30, 0 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; CI-NEXT: s_getpc_b64 s[4:5] ; CI-NEXT: s_add_u32 s4, s4, external_void_func_12xv3i32@rel32@lo+4 @@ -5967,10 +5968,9 @@ define void @stack_12xv3i32() #0 { ; CI-NEXT: v_mov_b32_e32 v28, 9 ; CI-NEXT: v_mov_b32_e32 v29, 9 ; CI-NEXT: v_mov_b32_e32 v30, 10 -; CI-NEXT: v_writelane_b32 v40, s31, 1 ; CI-NEXT: s_swappc_b64 s[30:31], s[4:5] -; CI-NEXT: v_readlane_b32 s31, v40, 1 ; CI-NEXT: v_readlane_b32 s30, v40, 0 +; CI-NEXT: v_readlane_b32 s31, v40, 1 ; CI-NEXT: s_mov_b32 s32, s33 ; CI-NEXT: v_readlane_b32 s4, v40, 2 ; CI-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -5988,7 +5988,10 @@ define void @stack_12xv3i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[8:9] +; GFX9-NEXT: v_writelane_b32 v40, s4, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 11 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX9-NEXT: v_mov_b32_e32 v0, 12 @@ -5996,10 +5999,8 @@ define void @stack_12xv3i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; GFX9-NEXT: v_mov_b32_e32 v0, 14 -; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GFX9-NEXT: v_mov_b32_e32 v0, 15 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_12xv3i32@rel32@lo+4 @@ -6035,10 +6036,9 @@ define void @stack_12xv3i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v28, 9 ; GFX9-NEXT: v_mov_b32_e32 v29, 9 ; GFX9-NEXT: v_mov_b32_e32 v30, 10 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6057,11 +6057,12 @@ define void @stack_12xv3i32() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 11 :: v_dual_mov_b32 v1, 12 ; GFX11-NEXT: v_dual_mov_b32 v2, 13 :: v_dual_mov_b32 v3, 14 ; GFX11-NEXT: v_mov_b32_e32 v4, 15 -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s0, s32, 16 ; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 ; GFX11-NEXT: scratch_store_b32 off, v4, s0 @@ -6084,11 +6085,10 @@ define void @stack_12xv3i32() #0 { ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_12xv3i32@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_12xv3i32@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -6106,7 +6106,10 @@ define void @stack_12xv3i32() #0 { ; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1 ; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; HSA-NEXT: s_mov_b64 exec, s[8:9] +; HSA-NEXT: v_writelane_b32 v40, s4, 2 +; HSA-NEXT: v_writelane_b32 v40, s30, 0 ; HSA-NEXT: s_addk_i32 s32, 0x400 +; HSA-NEXT: v_writelane_b32 v40, s31, 1 ; HSA-NEXT: v_mov_b32_e32 v0, 11 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; HSA-NEXT: v_mov_b32_e32 v0, 12 @@ -6114,10 +6117,8 @@ define void @stack_12xv3i32() #0 { ; HSA-NEXT: v_mov_b32_e32 v0, 13 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; HSA-NEXT: v_mov_b32_e32 v0, 14 -; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; HSA-NEXT: v_mov_b32_e32 v0, 15 -; HSA-NEXT: v_writelane_b32 v40, s30, 0 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; HSA-NEXT: s_getpc_b64 s[4:5] ; HSA-NEXT: s_add_u32 s4, s4, external_void_func_12xv3i32@rel32@lo+4 @@ -6153,10 +6154,9 @@ define void @stack_12xv3i32() #0 { ; HSA-NEXT: v_mov_b32_e32 v28, 9 ; HSA-NEXT: v_mov_b32_e32 v29, 9 ; HSA-NEXT: v_mov_b32_e32 v30, 10 -; HSA-NEXT: v_writelane_b32 v40, s31, 1 ; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5] -; HSA-NEXT: v_readlane_b32 s31, v40, 1 ; HSA-NEXT: v_readlane_b32 s30, v40, 0 +; HSA-NEXT: v_readlane_b32 s31, v40, 1 ; HSA-NEXT: s_mov_b32 s32, s33 ; HSA-NEXT: v_readlane_b32 s4, v40, 2 ; HSA-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6191,7 +6191,10 @@ define void @stack_12xv3f32() #0 { ; VI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[8:9] +; VI-NEXT: v_writelane_b32 v40, s4, 2 +; VI-NEXT: v_writelane_b32 v40, s30, 0 ; VI-NEXT: s_addk_i32 s32, 0x400 +; VI-NEXT: v_writelane_b32 v40, s31, 1 ; VI-NEXT: v_mov_b32_e32 v0, 0x41300000 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; VI-NEXT: v_mov_b32_e32 v0, 0x41400000 @@ -6199,10 +6202,8 @@ define void @stack_12xv3f32() #0 { ; VI-NEXT: v_mov_b32_e32 v0, 0x41500000 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; VI-NEXT: v_mov_b32_e32 v0, 0x41600000 -; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; VI-NEXT: v_mov_b32_e32 v0, 0x41700000 -; VI-NEXT: v_writelane_b32 v40, s30, 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; VI-NEXT: s_getpc_b64 s[4:5] ; VI-NEXT: s_add_u32 s4, s4, external_void_func_12xv3f32@rel32@lo+4 @@ -6238,10 +6239,9 @@ define void @stack_12xv3f32() #0 { ; VI-NEXT: v_mov_b32_e32 v28, 0x41100000 ; VI-NEXT: v_mov_b32_e32 v29, 0x41100000 ; VI-NEXT: v_mov_b32_e32 v30, 0x41200000 -; VI-NEXT: v_writelane_b32 v40, s31, 1 ; VI-NEXT: s_swappc_b64 s[30:31], s[4:5] -; VI-NEXT: v_readlane_b32 s31, v40, 1 ; VI-NEXT: v_readlane_b32 s30, v40, 0 +; VI-NEXT: v_readlane_b32 s31, v40, 1 ; VI-NEXT: s_mov_b32 s32, s33 ; VI-NEXT: v_readlane_b32 s4, v40, 2 ; VI-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6259,7 +6259,10 @@ define void @stack_12xv3f32() #0 { ; CI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CI-NEXT: s_mov_b64 exec, s[8:9] +; CI-NEXT: v_writelane_b32 v40, s4, 2 +; CI-NEXT: v_writelane_b32 v40, s30, 0 ; CI-NEXT: s_addk_i32 s32, 0x400 +; CI-NEXT: v_writelane_b32 v40, s31, 1 ; CI-NEXT: v_mov_b32_e32 v0, 0x41300000 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; CI-NEXT: v_mov_b32_e32 v0, 0x41400000 @@ -6267,10 +6270,8 @@ define void @stack_12xv3f32() #0 { ; CI-NEXT: v_mov_b32_e32 v0, 0x41500000 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; CI-NEXT: v_mov_b32_e32 v0, 0x41600000 -; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; CI-NEXT: v_mov_b32_e32 v0, 0x41700000 -; CI-NEXT: v_writelane_b32 v40, s30, 0 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; CI-NEXT: s_getpc_b64 s[4:5] ; CI-NEXT: s_add_u32 s4, s4, external_void_func_12xv3f32@rel32@lo+4 @@ -6306,10 +6307,9 @@ define void @stack_12xv3f32() #0 { ; CI-NEXT: v_mov_b32_e32 v28, 0x41100000 ; CI-NEXT: v_mov_b32_e32 v29, 0x41100000 ; CI-NEXT: v_mov_b32_e32 v30, 0x41200000 -; CI-NEXT: v_writelane_b32 v40, s31, 1 ; CI-NEXT: s_swappc_b64 s[30:31], s[4:5] -; CI-NEXT: v_readlane_b32 s31, v40, 1 ; CI-NEXT: v_readlane_b32 s30, v40, 0 +; CI-NEXT: v_readlane_b32 s31, v40, 1 ; CI-NEXT: s_mov_b32 s32, s33 ; CI-NEXT: v_readlane_b32 s4, v40, 2 ; CI-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6327,7 +6327,10 @@ define void @stack_12xv3f32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[8:9] +; GFX9-NEXT: v_writelane_b32 v40, s4, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41300000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41400000 @@ -6335,10 +6338,8 @@ define void @stack_12xv3f32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41500000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41600000 -; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41700000 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_12xv3f32@rel32@lo+4 @@ -6374,10 +6375,9 @@ define void @stack_12xv3f32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v28, 0x41100000 ; GFX9-NEXT: v_mov_b32_e32 v29, 0x41100000 ; GFX9-NEXT: v_mov_b32_e32 v30, 0x41200000 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6396,13 +6396,14 @@ define void @stack_12xv3f32() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x41300000 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x41400000 ; GFX11-NEXT: v_mov_b32_e32 v2, 0x41500000 ; GFX11-NEXT: v_mov_b32_e32 v3, 0x41600000 ; GFX11-NEXT: v_dual_mov_b32 v4, 0x41700000 :: v_dual_mov_b32 v5, 1.0 -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s0, s32, 16 ; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 ; GFX11-NEXT: scratch_store_b32 off, v4, s0 @@ -6427,11 +6428,10 @@ define void @stack_12xv3f32() #0 { ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_12xv3f32@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_12xv3f32@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -6449,7 +6449,10 @@ define void @stack_12xv3f32() #0 { ; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1 ; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; HSA-NEXT: s_mov_b64 exec, s[8:9] +; HSA-NEXT: v_writelane_b32 v40, s4, 2 +; HSA-NEXT: v_writelane_b32 v40, s30, 0 ; HSA-NEXT: s_addk_i32 s32, 0x400 +; HSA-NEXT: v_writelane_b32 v40, s31, 1 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41300000 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41400000 @@ -6457,10 +6460,8 @@ define void @stack_12xv3f32() #0 { ; HSA-NEXT: v_mov_b32_e32 v0, 0x41500000 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41600000 -; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41700000 -; HSA-NEXT: v_writelane_b32 v40, s30, 0 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; HSA-NEXT: s_getpc_b64 s[4:5] ; HSA-NEXT: s_add_u32 s4, s4, external_void_func_12xv3f32@rel32@lo+4 @@ -6496,10 +6497,9 @@ define void @stack_12xv3f32() #0 { ; HSA-NEXT: v_mov_b32_e32 v28, 0x41100000 ; HSA-NEXT: v_mov_b32_e32 v29, 0x41100000 ; HSA-NEXT: v_mov_b32_e32 v30, 0x41200000 -; HSA-NEXT: v_writelane_b32 v40, s31, 1 ; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5] -; HSA-NEXT: v_readlane_b32 s31, v40, 1 ; HSA-NEXT: v_readlane_b32 s30, v40, 0 +; HSA-NEXT: v_readlane_b32 s31, v40, 1 ; HSA-NEXT: s_mov_b32 s32, s33 ; HSA-NEXT: v_readlane_b32 s4, v40, 2 ; HSA-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6534,7 +6534,10 @@ define void @stack_8xv5i32() #0 { ; VI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[8:9] +; VI-NEXT: v_writelane_b32 v40, s4, 2 +; VI-NEXT: v_writelane_b32 v40, s30, 0 ; VI-NEXT: s_addk_i32 s32, 0x400 +; VI-NEXT: v_writelane_b32 v40, s31, 1 ; VI-NEXT: v_mov_b32_e32 v0, 7 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; VI-NEXT: v_mov_b32_e32 v0, 8 @@ -6550,10 +6553,8 @@ define void @stack_8xv5i32() #0 { ; VI-NEXT: v_mov_b32_e32 v0, 13 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; VI-NEXT: v_mov_b32_e32 v0, 14 -; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; VI-NEXT: v_mov_b32_e32 v0, 15 -; VI-NEXT: v_writelane_b32 v40, s30, 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; VI-NEXT: s_getpc_b64 s[4:5] ; VI-NEXT: s_add_u32 s4, s4, external_void_func_8xv5i32@rel32@lo+4 @@ -6589,10 +6590,9 @@ define void @stack_8xv5i32() #0 { ; VI-NEXT: v_mov_b32_e32 v28, 5 ; VI-NEXT: v_mov_b32_e32 v29, 5 ; VI-NEXT: v_mov_b32_e32 v30, 6 -; VI-NEXT: v_writelane_b32 v40, s31, 1 ; VI-NEXT: s_swappc_b64 s[30:31], s[4:5] -; VI-NEXT: v_readlane_b32 s31, v40, 1 ; VI-NEXT: v_readlane_b32 s30, v40, 0 +; VI-NEXT: v_readlane_b32 s31, v40, 1 ; VI-NEXT: s_mov_b32 s32, s33 ; VI-NEXT: v_readlane_b32 s4, v40, 2 ; VI-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6610,7 +6610,10 @@ define void @stack_8xv5i32() #0 { ; CI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CI-NEXT: s_mov_b64 exec, s[8:9] +; CI-NEXT: v_writelane_b32 v40, s4, 2 +; CI-NEXT: v_writelane_b32 v40, s30, 0 ; CI-NEXT: s_addk_i32 s32, 0x400 +; CI-NEXT: v_writelane_b32 v40, s31, 1 ; CI-NEXT: v_mov_b32_e32 v0, 7 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; CI-NEXT: v_mov_b32_e32 v0, 8 @@ -6626,10 +6629,8 @@ define void @stack_8xv5i32() #0 { ; CI-NEXT: v_mov_b32_e32 v0, 13 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; CI-NEXT: v_mov_b32_e32 v0, 14 -; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; CI-NEXT: v_mov_b32_e32 v0, 15 -; CI-NEXT: v_writelane_b32 v40, s30, 0 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; CI-NEXT: s_getpc_b64 s[4:5] ; CI-NEXT: s_add_u32 s4, s4, external_void_func_8xv5i32@rel32@lo+4 @@ -6665,10 +6666,9 @@ define void @stack_8xv5i32() #0 { ; CI-NEXT: v_mov_b32_e32 v28, 5 ; CI-NEXT: v_mov_b32_e32 v29, 5 ; CI-NEXT: v_mov_b32_e32 v30, 6 -; CI-NEXT: v_writelane_b32 v40, s31, 1 ; CI-NEXT: s_swappc_b64 s[30:31], s[4:5] -; CI-NEXT: v_readlane_b32 s31, v40, 1 ; CI-NEXT: v_readlane_b32 s30, v40, 0 +; CI-NEXT: v_readlane_b32 s31, v40, 1 ; CI-NEXT: s_mov_b32 s32, s33 ; CI-NEXT: v_readlane_b32 s4, v40, 2 ; CI-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6686,7 +6686,10 @@ define void @stack_8xv5i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[8:9] +; GFX9-NEXT: v_writelane_b32 v40, s4, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 7 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX9-NEXT: v_mov_b32_e32 v0, 8 @@ -6702,10 +6705,8 @@ define void @stack_8xv5i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; GFX9-NEXT: v_mov_b32_e32 v0, 14 -; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; GFX9-NEXT: v_mov_b32_e32 v0, 15 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_8xv5i32@rel32@lo+4 @@ -6741,10 +6742,9 @@ define void @stack_8xv5i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v28, 5 ; GFX9-NEXT: v_mov_b32_e32 v29, 5 ; GFX9-NEXT: v_mov_b32_e32 v30, 6 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6763,15 +6763,16 @@ define void @stack_8xv5i32() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 7 :: v_dual_mov_b32 v1, 8 ; GFX11-NEXT: v_dual_mov_b32 v2, 9 :: v_dual_mov_b32 v3, 10 ; GFX11-NEXT: v_dual_mov_b32 v8, 15 :: v_dual_mov_b32 v5, 12 -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_dual_mov_b32 v4, 11 :: v_dual_mov_b32 v7, 14 ; GFX11-NEXT: v_mov_b32_e32 v6, 13 ; GFX11-NEXT: s_add_i32 s0, s32, 32 ; GFX11-NEXT: s_add_i32 s1, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 @@ -6795,11 +6796,10 @@ define void @stack_8xv5i32() #0 { ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_8xv5i32@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_8xv5i32@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -6817,7 +6817,10 @@ define void @stack_8xv5i32() #0 { ; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1 ; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; HSA-NEXT: s_mov_b64 exec, s[8:9] +; HSA-NEXT: v_writelane_b32 v40, s4, 2 +; HSA-NEXT: v_writelane_b32 v40, s30, 0 ; HSA-NEXT: s_addk_i32 s32, 0x400 +; HSA-NEXT: v_writelane_b32 v40, s31, 1 ; HSA-NEXT: v_mov_b32_e32 v0, 7 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; HSA-NEXT: v_mov_b32_e32 v0, 8 @@ -6833,10 +6836,8 @@ define void @stack_8xv5i32() #0 { ; HSA-NEXT: v_mov_b32_e32 v0, 13 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; HSA-NEXT: v_mov_b32_e32 v0, 14 -; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; HSA-NEXT: v_mov_b32_e32 v0, 15 -; HSA-NEXT: v_writelane_b32 v40, s30, 0 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; HSA-NEXT: s_getpc_b64 s[4:5] ; HSA-NEXT: s_add_u32 s4, s4, external_void_func_8xv5i32@rel32@lo+4 @@ -6872,10 +6873,9 @@ define void @stack_8xv5i32() #0 { ; HSA-NEXT: v_mov_b32_e32 v28, 5 ; HSA-NEXT: v_mov_b32_e32 v29, 5 ; HSA-NEXT: v_mov_b32_e32 v30, 6 -; HSA-NEXT: v_writelane_b32 v40, s31, 1 ; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5] -; HSA-NEXT: v_readlane_b32 s31, v40, 1 ; HSA-NEXT: v_readlane_b32 s30, v40, 0 +; HSA-NEXT: v_readlane_b32 s31, v40, 1 ; HSA-NEXT: s_mov_b32 s32, s33 ; HSA-NEXT: v_readlane_b32 s4, v40, 2 ; HSA-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6906,7 +6906,10 @@ define void @stack_8xv5f32() #0 { ; VI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[8:9] +; VI-NEXT: v_writelane_b32 v40, s4, 2 +; VI-NEXT: v_writelane_b32 v40, s30, 0 ; VI-NEXT: s_addk_i32 s32, 0x400 +; VI-NEXT: v_writelane_b32 v40, s31, 1 ; VI-NEXT: v_mov_b32_e32 v0, 0x40e00000 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; VI-NEXT: v_mov_b32_e32 v0, 0x41000000 @@ -6922,10 +6925,8 @@ define void @stack_8xv5f32() #0 { ; VI-NEXT: v_mov_b32_e32 v0, 0x41500000 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; VI-NEXT: v_mov_b32_e32 v0, 0x41600000 -; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; VI-NEXT: v_mov_b32_e32 v0, 0x41700000 -; VI-NEXT: v_writelane_b32 v40, s30, 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; VI-NEXT: s_getpc_b64 s[4:5] ; VI-NEXT: s_add_u32 s4, s4, external_void_func_8xv5f32@rel32@lo+4 @@ -6961,10 +6962,9 @@ define void @stack_8xv5f32() #0 { ; VI-NEXT: v_mov_b32_e32 v28, 0x40a00000 ; VI-NEXT: v_mov_b32_e32 v29, 0x40a00000 ; VI-NEXT: v_mov_b32_e32 v30, 0x40c00000 -; VI-NEXT: v_writelane_b32 v40, s31, 1 ; VI-NEXT: s_swappc_b64 s[30:31], s[4:5] -; VI-NEXT: v_readlane_b32 s31, v40, 1 ; VI-NEXT: v_readlane_b32 s30, v40, 0 +; VI-NEXT: v_readlane_b32 s31, v40, 1 ; VI-NEXT: s_mov_b32 s32, s33 ; VI-NEXT: v_readlane_b32 s4, v40, 2 ; VI-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -6982,7 +6982,10 @@ define void @stack_8xv5f32() #0 { ; CI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CI-NEXT: s_mov_b64 exec, s[8:9] +; CI-NEXT: v_writelane_b32 v40, s4, 2 +; CI-NEXT: v_writelane_b32 v40, s30, 0 ; CI-NEXT: s_addk_i32 s32, 0x400 +; CI-NEXT: v_writelane_b32 v40, s31, 1 ; CI-NEXT: v_mov_b32_e32 v0, 0x40e00000 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; CI-NEXT: v_mov_b32_e32 v0, 0x41000000 @@ -6998,10 +7001,8 @@ define void @stack_8xv5f32() #0 { ; CI-NEXT: v_mov_b32_e32 v0, 0x41500000 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; CI-NEXT: v_mov_b32_e32 v0, 0x41600000 -; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; CI-NEXT: v_mov_b32_e32 v0, 0x41700000 -; CI-NEXT: v_writelane_b32 v40, s30, 0 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; CI-NEXT: s_getpc_b64 s[4:5] ; CI-NEXT: s_add_u32 s4, s4, external_void_func_8xv5f32@rel32@lo+4 @@ -7037,10 +7038,9 @@ define void @stack_8xv5f32() #0 { ; CI-NEXT: v_mov_b32_e32 v28, 0x40a00000 ; CI-NEXT: v_mov_b32_e32 v29, 0x40a00000 ; CI-NEXT: v_mov_b32_e32 v30, 0x40c00000 -; CI-NEXT: v_writelane_b32 v40, s31, 1 ; CI-NEXT: s_swappc_b64 s[30:31], s[4:5] -; CI-NEXT: v_readlane_b32 s31, v40, 1 ; CI-NEXT: v_readlane_b32 s30, v40, 0 +; CI-NEXT: v_readlane_b32 s31, v40, 1 ; CI-NEXT: s_mov_b32 s32, s33 ; CI-NEXT: v_readlane_b32 s4, v40, 2 ; CI-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -7058,7 +7058,10 @@ define void @stack_8xv5f32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[8:9] +; GFX9-NEXT: v_writelane_b32 v40, s4, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x40e00000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41000000 @@ -7074,10 +7077,8 @@ define void @stack_8xv5f32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41500000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41600000 -; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41700000 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_8xv5f32@rel32@lo+4 @@ -7113,10 +7114,9 @@ define void @stack_8xv5f32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v28, 0x40a00000 ; GFX9-NEXT: v_mov_b32_e32 v29, 0x40a00000 ; GFX9-NEXT: v_mov_b32_e32 v30, 0x40c00000 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -7135,19 +7135,20 @@ define void @stack_8xv5f32() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x40e00000 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x41000000 ; GFX11-NEXT: v_mov_b32_e32 v2, 0x41100000 ; GFX11-NEXT: v_mov_b32_e32 v3, 0x41200000 ; GFX11-NEXT: v_mov_b32_e32 v8, 0x41700000 -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_mov_b32_e32 v4, 0x41300000 ; GFX11-NEXT: v_mov_b32_e32 v5, 0x41400000 ; GFX11-NEXT: v_dual_mov_b32 v6, 0x41500000 :: v_dual_mov_b32 v9, 1.0 ; GFX11-NEXT: v_mov_b32_e32 v7, 0x41600000 ; GFX11-NEXT: s_add_i32 s0, s32, 32 ; GFX11-NEXT: s_add_i32 s1, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 ; GFX11-NEXT: scratch_store_b32 off, v8, s0 ; GFX11-NEXT: scratch_store_b128 off, v[4:7], s1 @@ -7170,11 +7171,10 @@ define void @stack_8xv5f32() #0 { ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_8xv5f32@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_8xv5f32@rel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -7192,7 +7192,10 @@ define void @stack_8xv5f32() #0 { ; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1 ; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; HSA-NEXT: s_mov_b64 exec, s[8:9] +; HSA-NEXT: v_writelane_b32 v40, s4, 2 +; HSA-NEXT: v_writelane_b32 v40, s30, 0 ; HSA-NEXT: s_addk_i32 s32, 0x400 +; HSA-NEXT: v_writelane_b32 v40, s31, 1 ; HSA-NEXT: v_mov_b32_e32 v0, 0x40e00000 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41000000 @@ -7208,10 +7211,8 @@ define void @stack_8xv5f32() #0 { ; HSA-NEXT: v_mov_b32_e32 v0, 0x41500000 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41600000 -; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41700000 -; HSA-NEXT: v_writelane_b32 v40, s30, 0 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; HSA-NEXT: s_getpc_b64 s[4:5] ; HSA-NEXT: s_add_u32 s4, s4, external_void_func_8xv5f32@rel32@lo+4 @@ -7247,10 +7248,9 @@ define void @stack_8xv5f32() #0 { ; HSA-NEXT: v_mov_b32_e32 v28, 0x40a00000 ; HSA-NEXT: v_mov_b32_e32 v29, 0x40a00000 ; HSA-NEXT: v_mov_b32_e32 v30, 0x40c00000 -; HSA-NEXT: v_writelane_b32 v40, s31, 1 ; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5] -; HSA-NEXT: v_readlane_b32 s31, v40, 1 ; HSA-NEXT: v_readlane_b32 s30, v40, 0 +; HSA-NEXT: v_readlane_b32 s31, v40, 1 ; HSA-NEXT: s_mov_b32 s32, s33 ; HSA-NEXT: v_readlane_b32 s4, v40, 2 ; HSA-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll b/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll index 4df10497bcd27..cdec3b6751e3a 100644 --- a/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll +++ b/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll @@ -20,8 +20,8 @@ define void @use_vcc() #1 { ; GCN: v_writelane_b32 v40, s30, 0 ; GCN: v_writelane_b32 v40, s31, 1 ; GCN: s_swappc_b64 -; GCN: v_readlane_b32 s31, v40, 1 ; GCN: v_readlane_b32 s30, v40, 0 +; GCN: v_readlane_b32 s31, v40, 1 ; GCN: v_readlane_b32 s4, v40, 2 ; GCN: s_mov_b32 s33, s4 ; GCN: s_setpc_b64 s[30:31] diff --git a/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll b/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll index 61a195f9c314f..8c0991fd32849 100644 --- a/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll +++ b/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll @@ -36,11 +36,11 @@ define void @test_func_call_external_void_func_void_clobber_s30_s31_call_externa ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] ; MUBUF-NEXT: v_writelane_b32 v40, s4, 4 -; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 -; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 ; MUBUF-NEXT: s_addk_i32 s32, 0x400 -; MUBUF-NEXT: v_writelane_b32 v40, s34, 2 -; MUBUF-NEXT: v_writelane_b32 v40, s35, 3 +; MUBUF-NEXT: v_writelane_b32 v40, s34, 0 +; MUBUF-NEXT: v_writelane_b32 v40, s35, 1 +; MUBUF-NEXT: v_writelane_b32 v40, s30, 2 +; MUBUF-NEXT: v_writelane_b32 v40, s31, 3 ; MUBUF-NEXT: s_getpc_b64 s[34:35] ; MUBUF-NEXT: s_add_u32 s34, s34, external_void_func_void@rel32@lo+4 ; MUBUF-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12 @@ -48,10 +48,10 @@ define void @test_func_call_external_void_func_void_clobber_s30_s31_call_externa ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ;;#ASMEND ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[34:35] -; MUBUF-NEXT: v_readlane_b32 s35, v40, 3 -; MUBUF-NEXT: v_readlane_b32 s34, v40, 2 -; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 -; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 +; MUBUF-NEXT: v_readlane_b32 s30, v40, 2 +; MUBUF-NEXT: v_readlane_b32 s31, v40, 3 +; MUBUF-NEXT: v_readlane_b32 s35, v40, 1 +; MUBUF-NEXT: v_readlane_b32 s34, v40, 0 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: v_readlane_b32 s4, v40, 4 ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -70,11 +70,11 @@ define void @test_func_call_external_void_func_void_clobber_s30_s31_call_externa ; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] ; FLATSCR-NEXT: v_writelane_b32 v40, s0, 4 -; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 -; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: s_add_i32 s32, s32, 16 -; FLATSCR-NEXT: v_writelane_b32 v40, s34, 2 -; FLATSCR-NEXT: v_writelane_b32 v40, s35, 3 +; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0 +; FLATSCR-NEXT: v_writelane_b32 v40, s35, 1 +; FLATSCR-NEXT: v_writelane_b32 v40, s30, 2 +; FLATSCR-NEXT: v_writelane_b32 v40, s31, 3 ; FLATSCR-NEXT: s_getpc_b64 s[34:35] ; FLATSCR-NEXT: s_add_u32 s34, s34, external_void_func_void@rel32@lo+4 ; FLATSCR-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12 @@ -82,10 +82,10 @@ define void @test_func_call_external_void_func_void_clobber_s30_s31_call_externa ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ;;#ASMEND ; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[34:35] -; FLATSCR-NEXT: v_readlane_b32 s35, v40, 3 -; FLATSCR-NEXT: v_readlane_b32 s34, v40, 2 -; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 -; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 +; FLATSCR-NEXT: v_readlane_b32 s30, v40, 2 +; FLATSCR-NEXT: v_readlane_b32 s31, v40, 3 +; FLATSCR-NEXT: v_readlane_b32 s35, v40, 1 +; FLATSCR-NEXT: v_readlane_b32 s34, v40, 0 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: v_readlane_b32 s0, v40, 4 ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 @@ -110,20 +110,20 @@ define void @test_func_call_external_void_funcx2() #0 { ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] ; MUBUF-NEXT: v_writelane_b32 v40, s4, 4 -; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 -; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 ; MUBUF-NEXT: s_addk_i32 s32, 0x400 -; MUBUF-NEXT: v_writelane_b32 v40, s34, 2 -; MUBUF-NEXT: v_writelane_b32 v40, s35, 3 +; MUBUF-NEXT: v_writelane_b32 v40, s34, 0 +; MUBUF-NEXT: v_writelane_b32 v40, s35, 1 +; MUBUF-NEXT: v_writelane_b32 v40, s30, 2 +; MUBUF-NEXT: v_writelane_b32 v40, s31, 3 ; MUBUF-NEXT: s_getpc_b64 s[34:35] ; MUBUF-NEXT: s_add_u32 s34, s34, external_void_func_void@rel32@lo+4 ; MUBUF-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12 ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[34:35] ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[34:35] -; MUBUF-NEXT: v_readlane_b32 s35, v40, 3 -; MUBUF-NEXT: v_readlane_b32 s34, v40, 2 -; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 -; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 +; MUBUF-NEXT: v_readlane_b32 s30, v40, 2 +; MUBUF-NEXT: v_readlane_b32 s31, v40, 3 +; MUBUF-NEXT: v_readlane_b32 s35, v40, 1 +; MUBUF-NEXT: v_readlane_b32 s34, v40, 0 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: v_readlane_b32 s4, v40, 4 ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -142,20 +142,20 @@ define void @test_func_call_external_void_funcx2() #0 { ; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] ; FLATSCR-NEXT: v_writelane_b32 v40, s0, 4 -; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 -; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: s_add_i32 s32, s32, 16 -; FLATSCR-NEXT: v_writelane_b32 v40, s34, 2 -; FLATSCR-NEXT: v_writelane_b32 v40, s35, 3 +; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0 +; FLATSCR-NEXT: v_writelane_b32 v40, s35, 1 +; FLATSCR-NEXT: v_writelane_b32 v40, s30, 2 +; FLATSCR-NEXT: v_writelane_b32 v40, s31, 3 ; FLATSCR-NEXT: s_getpc_b64 s[34:35] ; FLATSCR-NEXT: s_add_u32 s34, s34, external_void_func_void@rel32@lo+4 ; FLATSCR-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12 ; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[34:35] ; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[34:35] -; FLATSCR-NEXT: v_readlane_b32 s35, v40, 3 -; FLATSCR-NEXT: v_readlane_b32 s34, v40, 2 -; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 -; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 +; FLATSCR-NEXT: v_readlane_b32 s30, v40, 2 +; FLATSCR-NEXT: v_readlane_b32 s31, v40, 3 +; FLATSCR-NEXT: v_readlane_b32 s35, v40, 1 +; FLATSCR-NEXT: v_readlane_b32 s34, v40, 0 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: v_readlane_b32 s0, v40, 4 ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 @@ -181,8 +181,8 @@ define void @void_func_void_clobber_s30_s31() #2 { ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; clobber ; MUBUF-NEXT: ;;#ASMEND -; MUBUF-NEXT: v_readlane_b32 s31, v0, 1 ; MUBUF-NEXT: v_readlane_b32 s30, v0, 0 +; MUBUF-NEXT: v_readlane_b32 s31, v0, 1 ; MUBUF-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; MUBUF-NEXT: s_mov_b64 exec, s[4:5] @@ -200,8 +200,8 @@ define void @void_func_void_clobber_s30_s31() #2 { ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; clobber ; FLATSCR-NEXT: ;;#ASMEND -; FLATSCR-NEXT: v_readlane_b32 s31, v0, 1 ; FLATSCR-NEXT: v_readlane_b32 s30, v0, 0 +; FLATSCR-NEXT: v_readlane_b32 s31, v0, 1 ; FLATSCR-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; FLATSCR-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; FLATSCR-NEXT: s_mov_b64 exec, s[0:1] @@ -523,23 +523,23 @@ define void @callee_saved_sgpr_func() #2 { ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] ; MUBUF-NEXT: v_writelane_b32 v40, s4, 3 ; MUBUF-NEXT: s_addk_i32 s32, 0x400 -; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 -; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 +; MUBUF-NEXT: v_writelane_b32 v40, s34, 0 +; MUBUF-NEXT: v_writelane_b32 v40, s30, 1 +; MUBUF-NEXT: v_writelane_b32 v40, s31, 2 ; MUBUF-NEXT: s_getpc_b64 s[4:5] ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4 ; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12 -; MUBUF-NEXT: v_writelane_b32 v40, s34, 2 ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; def s40 ; MUBUF-NEXT: ;;#ASMEND ; MUBUF-NEXT: s_mov_b32 s34, s40 ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5] +; MUBUF-NEXT: v_readlane_b32 s30, v40, 1 ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; use s34 ; MUBUF-NEXT: ;;#ASMEND -; MUBUF-NEXT: v_readlane_b32 s34, v40, 2 -; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 -; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 +; MUBUF-NEXT: v_readlane_b32 s31, v40, 2 +; MUBUF-NEXT: v_readlane_b32 s34, v40, 0 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: v_readlane_b32 s4, v40, 3 ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -559,23 +559,23 @@ define void @callee_saved_sgpr_func() #2 { ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] ; FLATSCR-NEXT: v_writelane_b32 v40, s0, 3 ; FLATSCR-NEXT: s_add_i32 s32, s32, 16 -; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 -; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 +; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0 +; FLATSCR-NEXT: v_writelane_b32 v40, s30, 1 +; FLATSCR-NEXT: v_writelane_b32 v40, s31, 2 ; FLATSCR-NEXT: s_getpc_b64 s[0:1] ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void@rel32@lo+4 ; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void@rel32@hi+12 -; FLATSCR-NEXT: v_writelane_b32 v40, s34, 2 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; def s40 ; FLATSCR-NEXT: ;;#ASMEND ; FLATSCR-NEXT: s_mov_b32 s34, s40 ; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1] +; FLATSCR-NEXT: v_readlane_b32 s30, v40, 1 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; use s34 ; FLATSCR-NEXT: ;;#ASMEND -; FLATSCR-NEXT: v_readlane_b32 s34, v40, 2 -; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 -; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 +; FLATSCR-NEXT: v_readlane_b32 s31, v40, 2 +; FLATSCR-NEXT: v_readlane_b32 s34, v40, 0 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: v_readlane_b32 s0, v40, 3 ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 @@ -626,13 +626,13 @@ define void @callee_saved_sgpr_vgpr_func() #2 { ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] ; MUBUF-NEXT: v_writelane_b32 v41, s4, 3 ; MUBUF-NEXT: s_addk_i32 s32, 0x400 -; MUBUF-NEXT: v_writelane_b32 v41, s30, 0 -; MUBUF-NEXT: v_writelane_b32 v41, s31, 1 +; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; MUBUF-NEXT: v_writelane_b32 v41, s34, 0 +; MUBUF-NEXT: v_writelane_b32 v41, s30, 1 +; MUBUF-NEXT: v_writelane_b32 v41, s31, 2 ; MUBUF-NEXT: s_getpc_b64 s[4:5] ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4 ; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12 -; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; MUBUF-NEXT: v_writelane_b32 v41, s34, 2 ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; def s40 ; MUBUF-NEXT: ;;#ASMEND @@ -648,9 +648,9 @@ define void @callee_saved_sgpr_vgpr_func() #2 { ; MUBUF-NEXT: ; use v40 ; MUBUF-NEXT: ;;#ASMEND ; MUBUF-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; MUBUF-NEXT: v_readlane_b32 s34, v41, 2 -; MUBUF-NEXT: v_readlane_b32 s31, v41, 1 -; MUBUF-NEXT: v_readlane_b32 s30, v41, 0 +; MUBUF-NEXT: v_readlane_b32 s30, v41, 1 +; MUBUF-NEXT: v_readlane_b32 s31, v41, 2 +; MUBUF-NEXT: v_readlane_b32 s34, v41, 0 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: v_readlane_b32 s4, v41, 3 ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -670,13 +670,13 @@ define void @callee_saved_sgpr_vgpr_func() #2 { ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] ; FLATSCR-NEXT: v_writelane_b32 v41, s0, 3 ; FLATSCR-NEXT: s_add_i32 s32, s32, 16 -; FLATSCR-NEXT: v_writelane_b32 v41, s30, 0 -; FLATSCR-NEXT: v_writelane_b32 v41, s31, 1 +; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill +; FLATSCR-NEXT: v_writelane_b32 v41, s34, 0 +; FLATSCR-NEXT: v_writelane_b32 v41, s30, 1 +; FLATSCR-NEXT: v_writelane_b32 v41, s31, 2 ; FLATSCR-NEXT: s_getpc_b64 s[0:1] ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void@rel32@lo+4 ; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void@rel32@hi+12 -; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill -; FLATSCR-NEXT: v_writelane_b32 v41, s34, 2 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; def s40 ; FLATSCR-NEXT: ;;#ASMEND @@ -692,9 +692,9 @@ define void @callee_saved_sgpr_vgpr_func() #2 { ; FLATSCR-NEXT: ; use v40 ; FLATSCR-NEXT: ;;#ASMEND ; FLATSCR-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload -; FLATSCR-NEXT: v_readlane_b32 s34, v41, 2 -; FLATSCR-NEXT: v_readlane_b32 s31, v41, 1 -; FLATSCR-NEXT: v_readlane_b32 s30, v41, 0 +; FLATSCR-NEXT: v_readlane_b32 s30, v41, 1 +; FLATSCR-NEXT: v_readlane_b32 s31, v41, 2 +; FLATSCR-NEXT: v_readlane_b32 s34, v41, 0 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: v_readlane_b32 s0, v41, 3 ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 diff --git a/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll b/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll index e7254eb5c3465..eb3ef69848a88 100644 --- a/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll +++ b/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll @@ -122,18 +122,18 @@ define void @callee_with_stack_and_call() #0 { ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[18:19] ; MUBUF-NEXT: v_writelane_b32 v40, s16, 2 -; MUBUF-NEXT: s_addk_i32 s32, 0x400 ; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 +; MUBUF-NEXT: s_addk_i32 s32, 0x400 +; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: s_getpc_b64 s[16:17] ; MUBUF-NEXT: s_add_u32 s16, s16, external_void_func_void@rel32@lo+4 ; MUBUF-NEXT: s_addc_u32 s17, s17, external_void_func_void@rel32@hi+12 -; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[16:17] -; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 ; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 +; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: v_readlane_b32 s4, v40, 2 ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -152,18 +152,18 @@ define void @callee_with_stack_and_call() #0 { ; FLATSCR-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] ; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2 -; FLATSCR-NEXT: s_add_i32 s32, s32, 16 ; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 +; FLATSCR-NEXT: s_add_i32 s32, s32, 16 +; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: s_getpc_b64 s[0:1] ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void@rel32@lo+4 ; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void@rel32@hi+12 -; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: scratch_store_dword off, v0, s33 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1] -; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 ; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 +; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: v_readlane_b32 s0, v40, 2 ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 @@ -194,15 +194,15 @@ define void @callee_no_stack_with_call() #0 { ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[18:19] ; MUBUF-NEXT: v_writelane_b32 v40, s16, 2 -; MUBUF-NEXT: s_addk_i32 s32, 0x400 ; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 +; MUBUF-NEXT: s_addk_i32 s32, 0x400 +; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 ; MUBUF-NEXT: s_getpc_b64 s[16:17] ; MUBUF-NEXT: s_add_u32 s16, s16, external_void_func_void@rel32@lo+4 ; MUBUF-NEXT: s_addc_u32 s17, s17, external_void_func_void@rel32@hi+12 -; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[16:17] -; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 ; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 +; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: v_readlane_b32 s4, v40, 2 ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -221,15 +221,15 @@ define void @callee_no_stack_with_call() #0 { ; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] ; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2 -; FLATSCR-NEXT: s_add_i32 s32, s32, 16 ; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 +; FLATSCR-NEXT: s_add_i32 s32, s32, 16 +; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: s_getpc_b64 s[0:1] ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void@rel32@lo+4 ; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void@rel32@hi+12 -; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1] -; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 ; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 +; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: v_readlane_b32 s0, v40, 2 ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 @@ -359,24 +359,24 @@ define void @callee_func_sgpr_spill_no_calls(i32 %in) #0 { ; FLATSCR-NEXT: s_or_saveexec_b64 s[0:1], -1 ; FLATSCR-NEXT: scratch_store_dword off, v40, s32 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[0:1] -; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 -; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 -; FLATSCR-NEXT: v_writelane_b32 v40, s36, 2 -; FLATSCR-NEXT: v_writelane_b32 v40, s37, 3 -; FLATSCR-NEXT: v_writelane_b32 v40, s38, 4 -; FLATSCR-NEXT: v_writelane_b32 v40, s39, 5 -; FLATSCR-NEXT: v_writelane_b32 v40, s48, 6 -; FLATSCR-NEXT: v_writelane_b32 v40, s49, 7 -; FLATSCR-NEXT: v_writelane_b32 v40, s50, 8 -; FLATSCR-NEXT: v_writelane_b32 v40, s51, 9 -; FLATSCR-NEXT: v_writelane_b32 v40, s52, 10 -; FLATSCR-NEXT: v_writelane_b32 v40, s53, 11 -; FLATSCR-NEXT: v_writelane_b32 v40, s54, 12 -; FLATSCR-NEXT: v_writelane_b32 v40, s55, 13 -; FLATSCR-NEXT: v_writelane_b32 v40, s64, 14 -; FLATSCR-NEXT: v_writelane_b32 v40, s65, 15 -; FLATSCR-NEXT: v_writelane_b32 v40, s66, 16 -; FLATSCR-NEXT: v_writelane_b32 v40, s67, 17 +; FLATSCR-NEXT: v_writelane_b32 v40, s36, 0 +; FLATSCR-NEXT: v_writelane_b32 v40, s37, 1 +; FLATSCR-NEXT: v_writelane_b32 v40, s38, 2 +; FLATSCR-NEXT: v_writelane_b32 v40, s39, 3 +; FLATSCR-NEXT: v_writelane_b32 v40, s48, 4 +; FLATSCR-NEXT: v_writelane_b32 v40, s49, 5 +; FLATSCR-NEXT: v_writelane_b32 v40, s50, 6 +; FLATSCR-NEXT: v_writelane_b32 v40, s51, 7 +; FLATSCR-NEXT: v_writelane_b32 v40, s52, 8 +; FLATSCR-NEXT: v_writelane_b32 v40, s53, 9 +; FLATSCR-NEXT: v_writelane_b32 v40, s54, 10 +; FLATSCR-NEXT: v_writelane_b32 v40, s55, 11 +; FLATSCR-NEXT: v_writelane_b32 v40, s64, 12 +; FLATSCR-NEXT: v_writelane_b32 v40, s65, 13 +; FLATSCR-NEXT: v_writelane_b32 v40, s66, 14 +; FLATSCR-NEXT: v_writelane_b32 v40, s67, 15 +; FLATSCR-NEXT: v_writelane_b32 v40, s30, 16 +; FLATSCR-NEXT: v_writelane_b32 v40, s31, 17 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ;;#ASMEND ; FLATSCR-NEXT: ;;#ASMSTART @@ -414,6 +414,7 @@ define void @callee_func_sgpr_spill_no_calls(i32 %in) #0 { ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; use s[16:31] ; FLATSCR-NEXT: ;;#ASMEND +; FLATSCR-NEXT: v_readlane_b32 s30, v40, 16 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; use s[72:79] ; FLATSCR-NEXT: ;;#ASMEND @@ -423,24 +424,23 @@ define void @callee_func_sgpr_spill_no_calls(i32 %in) #0 { ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; use s[0:15] ; FLATSCR-NEXT: ;;#ASMEND -; FLATSCR-NEXT: v_readlane_b32 s67, v40, 17 -; FLATSCR-NEXT: v_readlane_b32 s66, v40, 16 -; FLATSCR-NEXT: v_readlane_b32 s65, v40, 15 -; FLATSCR-NEXT: v_readlane_b32 s64, v40, 14 -; FLATSCR-NEXT: v_readlane_b32 s55, v40, 13 -; FLATSCR-NEXT: v_readlane_b32 s54, v40, 12 -; FLATSCR-NEXT: v_readlane_b32 s53, v40, 11 -; FLATSCR-NEXT: v_readlane_b32 s52, v40, 10 -; FLATSCR-NEXT: v_readlane_b32 s51, v40, 9 -; FLATSCR-NEXT: v_readlane_b32 s50, v40, 8 -; FLATSCR-NEXT: v_readlane_b32 s49, v40, 7 -; FLATSCR-NEXT: v_readlane_b32 s48, v40, 6 -; FLATSCR-NEXT: v_readlane_b32 s39, v40, 5 -; FLATSCR-NEXT: v_readlane_b32 s38, v40, 4 -; FLATSCR-NEXT: v_readlane_b32 s37, v40, 3 -; FLATSCR-NEXT: v_readlane_b32 s36, v40, 2 -; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 -; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 +; FLATSCR-NEXT: v_readlane_b32 s31, v40, 17 +; FLATSCR-NEXT: v_readlane_b32 s67, v40, 15 +; FLATSCR-NEXT: v_readlane_b32 s66, v40, 14 +; FLATSCR-NEXT: v_readlane_b32 s65, v40, 13 +; FLATSCR-NEXT: v_readlane_b32 s64, v40, 12 +; FLATSCR-NEXT: v_readlane_b32 s55, v40, 11 +; FLATSCR-NEXT: v_readlane_b32 s54, v40, 10 +; FLATSCR-NEXT: v_readlane_b32 s53, v40, 9 +; FLATSCR-NEXT: v_readlane_b32 s52, v40, 8 +; FLATSCR-NEXT: v_readlane_b32 s51, v40, 7 +; FLATSCR-NEXT: v_readlane_b32 s50, v40, 6 +; FLATSCR-NEXT: v_readlane_b32 s49, v40, 5 +; FLATSCR-NEXT: v_readlane_b32 s48, v40, 4 +; FLATSCR-NEXT: v_readlane_b32 s39, v40, 3 +; FLATSCR-NEXT: v_readlane_b32 s38, v40, 2 +; FLATSCR-NEXT: v_readlane_b32 s37, v40, 1 +; FLATSCR-NEXT: v_readlane_b32 s36, v40, 0 ; FLATSCR-NEXT: s_or_saveexec_b64 s[0:1], -1 ; FLATSCR-NEXT: scratch_load_dword v40, off, s32 ; 4-byte Folded Reload ; FLATSCR-NEXT: s_mov_b64 exec, s[0:1] @@ -489,15 +489,15 @@ define void @callee_with_stack_no_fp_elim_csr_vgpr() #1 { ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MUBUF-NEXT: s_mov_b32 s4, s33 ; MUBUF-NEXT: s_mov_b32 s33, s32 -; MUBUF-NEXT: v_mov_b32_e32 v0, 0 +; MUBUF-NEXT: s_addk_i32 s32, 0x300 ; MUBUF-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; clobber v41 ; MUBUF-NEXT: ;;#ASMEND ; MUBUF-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload -; MUBUF-NEXT: s_addk_i32 s32, 0x300 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: s_mov_b32 s33, s4 ; MUBUF-NEXT: s_waitcnt vmcnt(0) @@ -508,15 +508,15 @@ define void @callee_with_stack_no_fp_elim_csr_vgpr() #1 { ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s0, s33 ; FLATSCR-NEXT: s_mov_b32 s33, s32 -; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 +; FLATSCR-NEXT: s_add_i32 s32, s32, 12 ; FLATSCR-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill +; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: scratch_store_dword off, v0, s33 offset:4 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; clobber v41 ; FLATSCR-NEXT: ;;#ASMEND ; FLATSCR-NEXT: scratch_load_dword v41, off, s33 ; 4-byte Folded Reload -; FLATSCR-NEXT: s_add_i32 s32, s32, 12 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: s_mov_b32 s33, s0 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) @@ -537,6 +537,8 @@ define void @last_lane_vgpr_for_fp_csr() #1 { ; MUBUF-NEXT: s_xor_saveexec_b64 s[6:7], -1 ; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] +; MUBUF-NEXT: s_addk_i32 s32, 0x400 +; MUBUF-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: v_writelane_b32 v1, s48, 0 ; MUBUF-NEXT: v_writelane_b32 v1, s49, 1 ; MUBUF-NEXT: v_writelane_b32 v1, s50, 2 @@ -566,19 +568,17 @@ define void @last_lane_vgpr_for_fp_csr() #1 { ; MUBUF-NEXT: v_writelane_b32 v1, s98, 26 ; MUBUF-NEXT: v_writelane_b32 v1, s99, 27 ; MUBUF-NEXT: v_writelane_b32 v1, s100, 28 -; MUBUF-NEXT: v_mov_b32_e32 v0, 0 -; MUBUF-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: v_writelane_b32 v1, s101, 29 +; MUBUF-NEXT: v_writelane_b32 v1, s102, 30 +; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; clobber v41 ; MUBUF-NEXT: ;;#ASMEND -; MUBUF-NEXT: v_writelane_b32 v1, s102, 30 ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ;;#ASMEND ; MUBUF-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload -; MUBUF-NEXT: s_addk_i32 s32, 0x400 ; MUBUF-NEXT: v_readlane_b32 s102, v1, 30 ; MUBUF-NEXT: v_readlane_b32 s101, v1, 29 ; MUBUF-NEXT: v_readlane_b32 s100, v1, 28 @@ -626,6 +626,8 @@ define void @last_lane_vgpr_for_fp_csr() #1 { ; FLATSCR-NEXT: s_xor_saveexec_b64 s[2:3], -1 ; FLATSCR-NEXT: scratch_store_dword off, v1, s33 offset:8 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] +; FLATSCR-NEXT: s_add_i32 s32, s32, 16 +; FLATSCR-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: v_writelane_b32 v1, s48, 0 ; FLATSCR-NEXT: v_writelane_b32 v1, s49, 1 ; FLATSCR-NEXT: v_writelane_b32 v1, s50, 2 @@ -655,19 +657,17 @@ define void @last_lane_vgpr_for_fp_csr() #1 { ; FLATSCR-NEXT: v_writelane_b32 v1, s98, 26 ; FLATSCR-NEXT: v_writelane_b32 v1, s99, 27 ; FLATSCR-NEXT: v_writelane_b32 v1, s100, 28 -; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 -; FLATSCR-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: v_writelane_b32 v1, s101, 29 +; FLATSCR-NEXT: v_writelane_b32 v1, s102, 30 +; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: scratch_store_dword off, v0, s33 offset:4 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; clobber v41 ; FLATSCR-NEXT: ;;#ASMEND -; FLATSCR-NEXT: v_writelane_b32 v1, s102, 30 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ;;#ASMEND ; FLATSCR-NEXT: scratch_load_dword v41, off, s33 ; 4-byte Folded Reload -; FLATSCR-NEXT: s_add_i32 s32, s32, 16 ; FLATSCR-NEXT: v_readlane_b32 s102, v1, 30 ; FLATSCR-NEXT: v_readlane_b32 s101, v1, 29 ; FLATSCR-NEXT: v_readlane_b32 s100, v1, 28 @@ -731,6 +731,8 @@ define void @no_new_vgpr_for_fp_csr() #1 { ; MUBUF-NEXT: s_xor_saveexec_b64 s[6:7], -1 ; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] +; MUBUF-NEXT: s_addk_i32 s32, 0x400 +; MUBUF-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: v_writelane_b32 v1, s39, 0 ; MUBUF-NEXT: v_writelane_b32 v1, s48, 1 ; MUBUF-NEXT: v_writelane_b32 v1, s49, 2 @@ -761,19 +763,17 @@ define void @no_new_vgpr_for_fp_csr() #1 { ; MUBUF-NEXT: v_writelane_b32 v1, s98, 27 ; MUBUF-NEXT: v_writelane_b32 v1, s99, 28 ; MUBUF-NEXT: v_writelane_b32 v1, s100, 29 -; MUBUF-NEXT: v_mov_b32_e32 v0, 0 -; MUBUF-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: v_writelane_b32 v1, s101, 30 +; MUBUF-NEXT: v_writelane_b32 v1, s102, 31 +; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; clobber v41 ; MUBUF-NEXT: ;;#ASMEND -; MUBUF-NEXT: v_writelane_b32 v1, s102, 31 ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ;;#ASMEND ; MUBUF-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload -; MUBUF-NEXT: s_addk_i32 s32, 0x400 ; MUBUF-NEXT: v_readlane_b32 s102, v1, 31 ; MUBUF-NEXT: v_readlane_b32 s101, v1, 30 ; MUBUF-NEXT: v_readlane_b32 s100, v1, 29 @@ -822,6 +822,8 @@ define void @no_new_vgpr_for_fp_csr() #1 { ; FLATSCR-NEXT: s_xor_saveexec_b64 s[2:3], -1 ; FLATSCR-NEXT: scratch_store_dword off, v1, s33 offset:8 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] +; FLATSCR-NEXT: s_add_i32 s32, s32, 16 +; FLATSCR-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: v_writelane_b32 v1, s39, 0 ; FLATSCR-NEXT: v_writelane_b32 v1, s48, 1 ; FLATSCR-NEXT: v_writelane_b32 v1, s49, 2 @@ -852,19 +854,17 @@ define void @no_new_vgpr_for_fp_csr() #1 { ; FLATSCR-NEXT: v_writelane_b32 v1, s98, 27 ; FLATSCR-NEXT: v_writelane_b32 v1, s99, 28 ; FLATSCR-NEXT: v_writelane_b32 v1, s100, 29 -; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 -; FLATSCR-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: v_writelane_b32 v1, s101, 30 +; FLATSCR-NEXT: v_writelane_b32 v1, s102, 31 +; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: scratch_store_dword off, v0, s33 offset:4 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; clobber v41 ; FLATSCR-NEXT: ;;#ASMEND -; FLATSCR-NEXT: v_writelane_b32 v1, s102, 31 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ;;#ASMEND ; FLATSCR-NEXT: scratch_load_dword v41, off, s33 ; 4-byte Folded Reload -; FLATSCR-NEXT: s_add_i32 s32, s32, 16 ; FLATSCR-NEXT: v_readlane_b32 s102, v1, 31 ; FLATSCR-NEXT: v_readlane_b32 s101, v1, 30 ; FLATSCR-NEXT: v_readlane_b32 s100, v1, 29 @@ -970,15 +970,15 @@ define void @no_unused_non_csr_sgpr_for_fp() #1 { ; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[4:5] ; MUBUF-NEXT: v_writelane_b32 v1, s30, 0 -; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: s_addk_i32 s32, 0x300 ; MUBUF-NEXT: v_writelane_b32 v1, s31, 1 +; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ;;#ASMEND -; MUBUF-NEXT: v_readlane_b32 s31, v1, 1 ; MUBUF-NEXT: v_readlane_b32 s30, v1, 0 +; MUBUF-NEXT: v_readlane_b32 s31, v1, 1 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload @@ -996,15 +996,15 @@ define void @no_unused_non_csr_sgpr_for_fp() #1 { ; FLATSCR-NEXT: scratch_store_dword off, v1, s33 offset:4 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[0:1] ; FLATSCR-NEXT: v_writelane_b32 v1, s30, 0 -; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: s_add_i32 s32, s32, 12 ; FLATSCR-NEXT: v_writelane_b32 v1, s31, 1 +; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: scratch_store_dword off, v0, s33 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ;;#ASMEND -; FLATSCR-NEXT: v_readlane_b32 s31, v1, 1 ; FLATSCR-NEXT: v_readlane_b32 s30, v1, 0 +; FLATSCR-NEXT: v_readlane_b32 s31, v1, 1 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; FLATSCR-NEXT: scratch_load_dword v1, off, s33 offset:4 ; 4-byte Folded Reload @@ -1036,18 +1036,18 @@ define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 { ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[4:5] ; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 -; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: s_addk_i32 s32, 0x300 ; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 +; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ;;#ASMEND +; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; clobber nonpreserved initial VGPRs ; MUBUF-NEXT: ;;#ASMEND ; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 -; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: s_or_saveexec_b64 s[4:5], -1 ; MUBUF-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload @@ -1065,18 +1065,18 @@ define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 { ; FLATSCR-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[0:1] ; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 -; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: s_add_i32 s32, s32, 12 ; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 +; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: scratch_store_dword off, v0, s33 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ;;#ASMEND +; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; clobber nonpreserved initial VGPRs ; FLATSCR-NEXT: ;;#ASMEND ; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 -; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: s_or_saveexec_b64 s[0:1], -1 ; FLATSCR-NEXT: scratch_load_dword v40, off, s33 offset:4 ; 4-byte Folded Reload @@ -1116,20 +1116,20 @@ define void @scratch_reg_needed_mubuf_offset(ptr addrspace(5) byval([4096 x i8]) ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s6 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[4:5] ; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 -; MUBUF-NEXT: v_mov_b32_e32 v0, 0 -; MUBUF-NEXT: v_mov_b32_e32 v1, 0x1000 ; MUBUF-NEXT: s_add_i32 s32, s32, 0x40300 ; MUBUF-NEXT: v_writelane_b32 v40, s31, 1 +; MUBUF-NEXT: v_mov_b32_e32 v0, 0 +; MUBUF-NEXT: v_mov_b32_e32 v1, 0x1000 ; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], s33 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; clobber nonpreserved SGPRs ; MUBUF-NEXT: ;;#ASMEND +; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; clobber nonpreserved VGPRs ; MUBUF-NEXT: ;;#ASMEND ; MUBUF-NEXT: v_readlane_b32 s31, v40, 1 -; MUBUF-NEXT: v_readlane_b32 s30, v40, 0 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: s_or_saveexec_b64 s[4:5], -1 ; MUBUF-NEXT: s_add_i32 s6, s33, 0x40100 @@ -1148,21 +1148,21 @@ define void @scratch_reg_needed_mubuf_offset(ptr addrspace(5) byval([4096 x i8]) ; FLATSCR-NEXT: s_add_i32 s2, s33, 0x1004 ; FLATSCR-NEXT: scratch_store_dword off, v40, s2 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[0:1] -; FLATSCR-NEXT: s_addk_i32 s32, 0x100c ; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 +; FLATSCR-NEXT: s_addk_i32 s32, 0x100c +; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: s_add_i32 s0, s33, 0x1000 -; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1 ; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; clobber nonpreserved SGPRs ; FLATSCR-NEXT: ;;#ASMEND +; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; clobber nonpreserved VGPRs ; FLATSCR-NEXT: ;;#ASMEND ; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1 -; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: s_or_saveexec_b64 s[0:1], -1 ; FLATSCR-NEXT: s_add_i32 s2, s33, 0x1004 @@ -1210,18 +1210,18 @@ define void @ipra_call_with_stack() #0 { ; MUBUF-NEXT: s_xor_saveexec_b64 s[16:17], -1 ; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[16:17] -; MUBUF-NEXT: s_addk_i32 s32, 0x400 ; MUBUF-NEXT: v_writelane_b32 v1, s30, 0 +; MUBUF-NEXT: s_addk_i32 s32, 0x400 +; MUBUF-NEXT: v_writelane_b32 v1, s31, 1 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: s_getpc_b64 s[16:17] ; MUBUF-NEXT: s_add_u32 s16, s16, local_empty_func@rel32@lo+4 ; MUBUF-NEXT: s_addc_u32 s17, s17, local_empty_func@rel32@hi+12 -; MUBUF-NEXT: v_writelane_b32 v1, s31, 1 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_swappc_b64 s[30:31], s[16:17] -; MUBUF-NEXT: v_readlane_b32 s31, v1, 1 ; MUBUF-NEXT: v_readlane_b32 s30, v1, 0 +; MUBUF-NEXT: v_readlane_b32 s31, v1, 1 ; MUBUF-NEXT: s_mov_b32 s32, s33 ; MUBUF-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload @@ -1238,18 +1238,18 @@ define void @ipra_call_with_stack() #0 { ; FLATSCR-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; FLATSCR-NEXT: scratch_store_dword off, v1, s33 offset:4 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[0:1] -; FLATSCR-NEXT: s_add_i32 s32, s32, 16 ; FLATSCR-NEXT: v_writelane_b32 v1, s30, 0 +; FLATSCR-NEXT: s_add_i32 s32, s32, 16 +; FLATSCR-NEXT: v_writelane_b32 v1, s31, 1 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: s_getpc_b64 s[0:1] ; FLATSCR-NEXT: s_add_u32 s0, s0, local_empty_func@rel32@lo+4 ; FLATSCR-NEXT: s_addc_u32 s1, s1, local_empty_func@rel32@hi+12 -; FLATSCR-NEXT: v_writelane_b32 v1, s31, 1 ; FLATSCR-NEXT: scratch_store_dword off, v0, s33 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1] -; FLATSCR-NEXT: v_readlane_b32 s31, v1, 1 ; FLATSCR-NEXT: v_readlane_b32 s30, v1, 0 +; FLATSCR-NEXT: v_readlane_b32 s31, v1, 1 ; FLATSCR-NEXT: s_mov_b32 s32, s33 ; FLATSCR-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; FLATSCR-NEXT: scratch_load_dword v1, off, s33 offset:4 ; 4-byte Folded Reload @@ -1319,6 +1319,7 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 { ; MUBUF-NEXT: buffer_store_dword v39, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] ; MUBUF-NEXT: v_writelane_b32 v39, s4, 32 +; MUBUF-NEXT: s_addk_i32 s32, 0x200 ; MUBUF-NEXT: v_writelane_b32 v39, s39, 0 ; MUBUF-NEXT: v_writelane_b32 v39, s48, 1 ; MUBUF-NEXT: v_writelane_b32 v39, s49, 2 @@ -1350,7 +1351,6 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 { ; MUBUF-NEXT: v_writelane_b32 v39, s99, 28 ; MUBUF-NEXT: v_writelane_b32 v39, s100, 29 ; MUBUF-NEXT: v_writelane_b32 v39, s101, 30 -; MUBUF-NEXT: s_addk_i32 s32, 0x200 ; MUBUF-NEXT: v_writelane_b32 v39, s102, 31 ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; clobber nonpreserved SGPRs and 64 CSRs @@ -1407,6 +1407,7 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 { ; FLATSCR-NEXT: s_xor_saveexec_b64 s[2:3], -1 ; FLATSCR-NEXT: scratch_store_dword off, v39, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] +; FLATSCR-NEXT: s_add_i32 s32, s32, 8 ; FLATSCR-NEXT: v_writelane_b32 v39, s39, 0 ; FLATSCR-NEXT: v_writelane_b32 v39, s48, 1 ; FLATSCR-NEXT: v_writelane_b32 v39, s49, 2 @@ -1438,7 +1439,6 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 { ; FLATSCR-NEXT: v_writelane_b32 v39, s99, 28 ; FLATSCR-NEXT: v_writelane_b32 v39, s100, 29 ; FLATSCR-NEXT: v_writelane_b32 v39, s101, 30 -; FLATSCR-NEXT: s_add_i32 s32, s32, 8 ; FLATSCR-NEXT: v_writelane_b32 v39, s102, 31 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; clobber nonpreserved SGPRs and 64 CSRs @@ -1519,6 +1519,7 @@ define void @callee_need_to_spill_fp_to_reg() #1 { ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] ; MUBUF-NEXT: v_writelane_b32 v40, s4, 32 +; MUBUF-NEXT: s_addk_i32 s32, 0x200 ; MUBUF-NEXT: v_writelane_b32 v40, s39, 0 ; MUBUF-NEXT: v_writelane_b32 v40, s48, 1 ; MUBUF-NEXT: v_writelane_b32 v40, s49, 2 @@ -1550,7 +1551,6 @@ define void @callee_need_to_spill_fp_to_reg() #1 { ; MUBUF-NEXT: v_writelane_b32 v40, s99, 28 ; MUBUF-NEXT: v_writelane_b32 v40, s100, 29 ; MUBUF-NEXT: v_writelane_b32 v40, s101, 30 -; MUBUF-NEXT: s_addk_i32 s32, 0x200 ; MUBUF-NEXT: v_writelane_b32 v40, s102, 31 ; MUBUF-NEXT: ;;#ASMSTART ; MUBUF-NEXT: ; clobber nonpreserved SGPRs and 64 CSRs @@ -1607,6 +1607,7 @@ define void @callee_need_to_spill_fp_to_reg() #1 { ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 ; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] +; FLATSCR-NEXT: s_add_i32 s32, s32, 8 ; FLATSCR-NEXT: v_writelane_b32 v40, s39, 0 ; FLATSCR-NEXT: v_writelane_b32 v40, s48, 1 ; FLATSCR-NEXT: v_writelane_b32 v40, s49, 2 @@ -1638,7 +1639,6 @@ define void @callee_need_to_spill_fp_to_reg() #1 { ; FLATSCR-NEXT: v_writelane_b32 v40, s99, 28 ; FLATSCR-NEXT: v_writelane_b32 v40, s100, 29 ; FLATSCR-NEXT: v_writelane_b32 v40, s101, 30 -; FLATSCR-NEXT: s_add_i32 s32, s32, 8 ; FLATSCR-NEXT: v_writelane_b32 v40, s102, 31 ; FLATSCR-NEXT: ;;#ASMSTART ; FLATSCR-NEXT: ; clobber nonpreserved SGPRs and 64 CSRs @@ -1718,6 +1718,7 @@ define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset(ptr addrspace(5) ; MUBUF-NEXT: buffer_store_dword v39, off, s[0:3], s5 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] ; MUBUF-NEXT: v_writelane_b32 v39, s4, 32 +; MUBUF-NEXT: s_add_i32 s32, s32, 0x40300 ; MUBUF-NEXT: v_writelane_b32 v39, s39, 0 ; MUBUF-NEXT: v_writelane_b32 v39, s48, 1 ; MUBUF-NEXT: v_writelane_b32 v39, s49, 2 @@ -1749,10 +1750,9 @@ define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset(ptr addrspace(5) ; MUBUF-NEXT: v_writelane_b32 v39, s99, 28 ; MUBUF-NEXT: v_writelane_b32 v39, s100, 29 ; MUBUF-NEXT: v_writelane_b32 v39, s101, 30 +; MUBUF-NEXT: v_writelane_b32 v39, s102, 31 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0x1000 -; MUBUF-NEXT: s_add_i32 s32, s32, 0x40300 -; MUBUF-NEXT: v_writelane_b32 v39, s102, 31 ; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], s33 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: ;;#ASMSTART @@ -1812,6 +1812,7 @@ define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset(ptr addrspace(5) ; FLATSCR-NEXT: s_add_i32 s1, s33, 0x1004 ; FLATSCR-NEXT: scratch_store_dword off, v39, s1 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] +; FLATSCR-NEXT: s_addk_i32 s32, 0x100c ; FLATSCR-NEXT: v_writelane_b32 v39, s39, 0 ; FLATSCR-NEXT: v_writelane_b32 v39, s48, 1 ; FLATSCR-NEXT: v_writelane_b32 v39, s49, 2 @@ -1841,12 +1842,11 @@ define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset(ptr addrspace(5) ; FLATSCR-NEXT: v_writelane_b32 v39, s97, 26 ; FLATSCR-NEXT: v_writelane_b32 v39, s98, 27 ; FLATSCR-NEXT: v_writelane_b32 v39, s99, 28 -; FLATSCR-NEXT: s_addk_i32 s32, 0x100c ; FLATSCR-NEXT: v_writelane_b32 v39, s100, 29 ; FLATSCR-NEXT: v_writelane_b32 v39, s101, 30 +; FLATSCR-NEXT: v_writelane_b32 v39, s102, 31 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: s_add_i32 s1, s33, 0x1000 -; FLATSCR-NEXT: v_writelane_b32 v39, s102, 31 ; FLATSCR-NEXT: scratch_store_dword off, v0, s1 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: ;;#ASMSTART diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll index fccee3da6d77e..a5ae429c4c10a 100644 --- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll +++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll @@ -5,90 +5,24 @@ target triple = "amdgcn-amd-amdhsa" define void @use_workitem_id_x() #1 { -; GFX7-LABEL: use_workitem_id_x: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: use_workitem_id_x: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.x() store volatile i32 %val, ptr addrspace(1) poison ret void } define void @use_workitem_id_y() #1 { -; GFX7-LABEL: use_workitem_id_y: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: use_workitem_id_y: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.y() store volatile i32 %val, ptr addrspace(1) poison ret void } define void @use_workitem_id_z() #1 { -; GFX7-LABEL: use_workitem_id_z: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: use_workitem_id_z: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.z() store volatile i32 %val, ptr addrspace(1) poison ret void } define void @use_workitem_id_xy() #1 { -; GFX7-LABEL: use_workitem_id_xy: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: use_workitem_id_xy: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] %val0 = call i32 @llvm.amdgcn.workitem.id.x() %val1 = call i32 @llvm.amdgcn.workitem.id.y() store volatile i32 %val0, ptr addrspace(1) poison @@ -97,33 +31,6 @@ define void @use_workitem_id_xy() #1 { } define void @use_workitem_id_xyz() #1 { -; GFX7-LABEL: use_workitem_id_xyz: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: use_workitem_id_xyz: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] %val0 = call i32 @llvm.amdgcn.workitem.id.x() %val1 = call i32 @llvm.amdgcn.workitem.id.y() %val2 = call i32 @llvm.amdgcn.workitem.id.z() @@ -134,27 +41,6 @@ define void @use_workitem_id_xyz() #1 { } define void @use_workitem_id_xz() #1 { -; GFX7-LABEL: use_workitem_id_xz: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: use_workitem_id_xz: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] %val0 = call i32 @llvm.amdgcn.workitem.id.x() %val1 = call i32 @llvm.amdgcn.workitem.id.z() store volatile i32 %val0, ptr addrspace(1) poison @@ -163,27 +49,6 @@ define void @use_workitem_id_xz() #1 { } define void @use_workitem_id_yz() #1 { -; GFX7-LABEL: use_workitem_id_yz: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: use_workitem_id_yz: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] %val0 = call i32 @llvm.amdgcn.workitem.id.y() %val1 = call i32 @llvm.amdgcn.workitem.id.z() store volatile i32 %val0, ptr addrspace(1) poison @@ -192,344 +57,59 @@ define void @use_workitem_id_yz() #1 { } define amdgpu_kernel void @kern_indirect_use_workitem_id_x() #1 { -; GCN-LABEL: kern_indirect_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_mov_b32_e32 v31, v0 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @use_workitem_id_x() ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 0 define amdgpu_kernel void @kern_indirect_use_workitem_id_y() #1 { -; GFX7-LABEL: kern_indirect_use_workitem_id_y: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_add_u32 s0, s0, s5 -; GFX7-NEXT: s_addc_u32 s1, s1, 0 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, use_workitem_id_y@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, use_workitem_id_y@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v31, 10, v1 -; GFX7-NEXT: s_mov_b32 s32, 0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: s_endpgm -; -; GFX90A-LABEL: kern_indirect_use_workitem_id_y: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_add_u32 s0, s0, s5 -; GFX90A-NEXT: s_addc_u32 s1, s1, 0 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, use_workitem_id_y@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, use_workitem_id_y@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: v_mov_b32_e32 v31, v0 -; GFX90A-NEXT: s_mov_b32 s32, 0 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: s_endpgm call void @use_workitem_id_y() ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 1 define amdgpu_kernel void @kern_indirect_use_workitem_id_z() #1 { -; GFX7-LABEL: kern_indirect_use_workitem_id_z: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_add_u32 s0, s0, s5 -; GFX7-NEXT: s_addc_u32 s1, s1, 0 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, use_workitem_id_z@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, use_workitem_id_z@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v31, 20, v2 -; GFX7-NEXT: s_mov_b32 s32, 0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: s_endpgm -; -; GFX90A-LABEL: kern_indirect_use_workitem_id_z: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_add_u32 s0, s0, s5 -; GFX90A-NEXT: s_addc_u32 s1, s1, 0 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, use_workitem_id_z@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, use_workitem_id_z@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: v_mov_b32_e32 v31, v0 -; GFX90A-NEXT: s_mov_b32 s32, 0 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: s_endpgm call void @use_workitem_id_z() ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 2 define amdgpu_kernel void @kern_indirect_use_workitem_id_xy() #1 { -; GFX7-LABEL: kern_indirect_use_workitem_id_xy: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_add_u32 s0, s0, s5 -; GFX7-NEXT: s_addc_u32 s1, s1, 0 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, use_workitem_id_xy@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, use_workitem_id_xy@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 10, v1 -; GFX7-NEXT: v_or_b32_e32 v31, v0, v1 -; GFX7-NEXT: s_mov_b32 s32, 0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: s_endpgm -; -; GFX90A-LABEL: kern_indirect_use_workitem_id_xy: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_add_u32 s0, s0, s5 -; GFX90A-NEXT: s_addc_u32 s1, s1, 0 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, use_workitem_id_xy@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, use_workitem_id_xy@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: v_mov_b32_e32 v31, v0 -; GFX90A-NEXT: s_mov_b32 s32, 0 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: s_endpgm call void @use_workitem_id_xy() ret void } define amdgpu_kernel void @kern_indirect_use_workitem_id_xz() #1 { -; GFX7-LABEL: kern_indirect_use_workitem_id_xz: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_add_u32 s0, s0, s5 -; GFX7-NEXT: s_addc_u32 s1, s1, 0 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, use_workitem_id_xz@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, use_workitem_id_xz@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 20, v2 -; GFX7-NEXT: v_or_b32_e32 v31, v0, v1 -; GFX7-NEXT: s_mov_b32 s32, 0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: s_endpgm -; -; GFX90A-LABEL: kern_indirect_use_workitem_id_xz: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_add_u32 s0, s0, s5 -; GFX90A-NEXT: s_addc_u32 s1, s1, 0 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, use_workitem_id_xz@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, use_workitem_id_xz@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: v_mov_b32_e32 v31, v0 -; GFX90A-NEXT: s_mov_b32 s32, 0 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: s_endpgm call void @use_workitem_id_xz() ret void } define amdgpu_kernel void @kern_indirect_use_workitem_id_yz() #1 { -; GFX7-LABEL: kern_indirect_use_workitem_id_yz: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_add_u32 s0, s0, s5 -; GFX7-NEXT: s_addc_u32 s1, s1, 0 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, use_workitem_id_yz@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, use_workitem_id_yz@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v0, 20, v2 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 10, v1 -; GFX7-NEXT: v_or_b32_e32 v31, v1, v0 -; GFX7-NEXT: s_mov_b32 s32, 0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: s_endpgm -; -; GFX90A-LABEL: kern_indirect_use_workitem_id_yz: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_add_u32 s0, s0, s5 -; GFX90A-NEXT: s_addc_u32 s1, s1, 0 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, use_workitem_id_yz@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, use_workitem_id_yz@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: v_mov_b32_e32 v31, v0 -; GFX90A-NEXT: s_mov_b32 s32, 0 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: s_endpgm call void @use_workitem_id_yz() ret void } define amdgpu_kernel void @kern_indirect_use_workitem_id_xyz() #1 { -; GFX7-LABEL: kern_indirect_use_workitem_id_xyz: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_add_u32 s0, s0, s5 -; GFX7-NEXT: s_addc_u32 s1, s1, 0 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, use_workitem_id_xyz@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, use_workitem_id_xyz@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 10, v1 -; GFX7-NEXT: v_lshlrev_b32_e32 v2, 20, v2 -; GFX7-NEXT: v_or_b32_e32 v0, v0, v1 -; GFX7-NEXT: v_or_b32_e32 v31, v0, v2 -; GFX7-NEXT: s_mov_b32 s32, 0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: s_endpgm -; -; GFX90A-LABEL: kern_indirect_use_workitem_id_xyz: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_add_u32 s0, s0, s5 -; GFX90A-NEXT: s_addc_u32 s1, s1, 0 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, use_workitem_id_xyz@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, use_workitem_id_xyz@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: v_mov_b32_e32 v31, v0 -; GFX90A-NEXT: s_mov_b32 s32, 0 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: s_endpgm call void @use_workitem_id_xyz() ret void } define void @func_indirect_use_workitem_id_x() #1 { -; GCN-LABEL: func_indirect_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] call void @use_workitem_id_x() ret void } define void @func_indirect_use_workitem_id_y() #1 { -; GCN-LABEL: func_indirect_use_workitem_id_y: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_y@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_y@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] call void @use_workitem_id_y() ret void } define void @func_indirect_use_workitem_id_z() #1 { -; GCN-LABEL: func_indirect_use_workitem_id_z: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_z@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_z@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] call void @use_workitem_id_z() ret void } define void @other_arg_use_workitem_id_x(i32 %arg0) #1 { -; GFX7-LABEL: other_arg_use_workitem_id_x: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: other_arg_use_workitem_id_x: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.x() store volatile i32 %arg0, ptr addrspace(1) poison store volatile i32 %val, ptr addrspace(1) poison @@ -537,25 +117,6 @@ define void @other_arg_use_workitem_id_x(i32 %arg0) #1 { } define void @other_arg_use_workitem_id_y(i32 %arg0) #1 { -; GFX7-LABEL: other_arg_use_workitem_id_y: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: other_arg_use_workitem_id_y: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.y() store volatile i32 %arg0, ptr addrspace(1) poison store volatile i32 %val, ptr addrspace(1) poison @@ -563,25 +124,6 @@ define void @other_arg_use_workitem_id_y(i32 %arg0) #1 { } define void @other_arg_use_workitem_id_z(i32 %arg0) #1 { -; GFX7-LABEL: other_arg_use_workitem_id_z: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: other_arg_use_workitem_id_z: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.z() store volatile i32 %arg0, ptr addrspace(1) poison store volatile i32 %val, ptr addrspace(1) poison @@ -589,241 +131,24 @@ define void @other_arg_use_workitem_id_z(i32 %arg0) #1 { } define amdgpu_kernel void @kern_indirect_other_arg_use_workitem_id_x() #1 { -; GCN-LABEL: kern_indirect_other_arg_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, other_arg_use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, other_arg_use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_mov_b32_e32 v31, v0 -; GCN-NEXT: v_mov_b32_e32 v0, 0x22b -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @other_arg_use_workitem_id_x(i32 555) ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 0 define amdgpu_kernel void @kern_indirect_other_arg_use_workitem_id_y() #1 { -; GFX7-LABEL: kern_indirect_other_arg_use_workitem_id_y: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_add_u32 s0, s0, s5 -; GFX7-NEXT: s_addc_u32 s1, s1, 0 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, other_arg_use_workitem_id_y@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, other_arg_use_workitem_id_y@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v31, 10, v1 -; GFX7-NEXT: v_mov_b32_e32 v0, 0x22b -; GFX7-NEXT: s_mov_b32 s32, 0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: s_endpgm -; -; GFX90A-LABEL: kern_indirect_other_arg_use_workitem_id_y: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_add_u32 s0, s0, s5 -; GFX90A-NEXT: s_addc_u32 s1, s1, 0 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, other_arg_use_workitem_id_y@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, other_arg_use_workitem_id_y@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: v_mov_b32_e32 v31, v0 -; GFX90A-NEXT: v_mov_b32_e32 v0, 0x22b -; GFX90A-NEXT: s_mov_b32 s32, 0 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: s_endpgm call void @other_arg_use_workitem_id_y(i32 555) ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 1 define amdgpu_kernel void @kern_indirect_other_arg_use_workitem_id_z() #1 { -; GFX7-LABEL: kern_indirect_other_arg_use_workitem_id_z: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_add_u32 s0, s0, s5 -; GFX7-NEXT: s_addc_u32 s1, s1, 0 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, other_arg_use_workitem_id_z@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, other_arg_use_workitem_id_z@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v31, 20, v2 -; GFX7-NEXT: v_mov_b32_e32 v0, 0x22b -; GFX7-NEXT: s_mov_b32 s32, 0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: s_endpgm -; -; GFX90A-LABEL: kern_indirect_other_arg_use_workitem_id_z: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_add_u32 s0, s0, s5 -; GFX90A-NEXT: s_addc_u32 s1, s1, 0 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, other_arg_use_workitem_id_z@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, other_arg_use_workitem_id_z@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: v_mov_b32_e32 v31, v0 -; GFX90A-NEXT: v_mov_b32_e32 v0, 0x22b -; GFX90A-NEXT: s_mov_b32 s32, 0 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: s_endpgm call void @other_arg_use_workitem_id_z(i32 555) ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 2 define void @too_many_args_use_workitem_id_x( -; GFX7-LABEL: too_many_args_use_workitem_id_x: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v31, 0x3ff, v31 -; GFX7-NEXT: flat_store_dword v[0:1], v31 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v1 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v2 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v3 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v4 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v5 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v6 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v7 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v8 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v9 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v10 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v11 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v12 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v13 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v14 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v15 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v16 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v17 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v18 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v19 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v20 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v21 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v22 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v23 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v24 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v25 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v26 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v27 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v28 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v29 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v30 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v31 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: too_many_args_use_workitem_id_x: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: buffer_load_dword v32, off, s[0:3], s32 -; GFX90A-NEXT: v_and_b32_e32 v31, 0x3ff, v31 -; GFX90A-NEXT: global_store_dword v[0:1], v31, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v1, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v2, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v3, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v4, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v5, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v6, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v7, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v8, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v9, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v10, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v11, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v12, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v13, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v14, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v15, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v16, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v17, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v18, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v19, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v20, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v21, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v22, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v23, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v24, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v25, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v26, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v27, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v28, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v29, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v30, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v32, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, @@ -871,52 +196,6 @@ define void @too_many_args_use_workitem_id_x( } define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x() #1 { -; GCN-LABEL: kern_call_too_many_args_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 0x140 -; GCN-NEXT: buffer_store_dword v1, off, s[0:3], s32 -; GCN-NEXT: v_mov_b32_e32 v31, v0 -; GCN-NEXT: v_mov_b32_e32 v0, 10 -; GCN-NEXT: v_mov_b32_e32 v1, 20 -; GCN-NEXT: v_mov_b32_e32 v2, 30 -; GCN-NEXT: v_mov_b32_e32 v3, 40 -; GCN-NEXT: v_mov_b32_e32 v4, 50 -; GCN-NEXT: v_mov_b32_e32 v5, 60 -; GCN-NEXT: v_mov_b32_e32 v6, 0x46 -; GCN-NEXT: v_mov_b32_e32 v7, 0x50 -; GCN-NEXT: v_mov_b32_e32 v8, 0x5a -; GCN-NEXT: v_mov_b32_e32 v9, 0x64 -; GCN-NEXT: v_mov_b32_e32 v10, 0x6e -; GCN-NEXT: v_mov_b32_e32 v11, 0x78 -; GCN-NEXT: v_mov_b32_e32 v12, 0x82 -; GCN-NEXT: v_mov_b32_e32 v13, 0x8c -; GCN-NEXT: v_mov_b32_e32 v14, 0x96 -; GCN-NEXT: v_mov_b32_e32 v15, 0xa0 -; GCN-NEXT: v_mov_b32_e32 v16, 0xaa -; GCN-NEXT: v_mov_b32_e32 v17, 0xb4 -; GCN-NEXT: v_mov_b32_e32 v18, 0xbe -; GCN-NEXT: v_mov_b32_e32 v19, 0xc8 -; GCN-NEXT: v_mov_b32_e32 v20, 0xd2 -; GCN-NEXT: v_mov_b32_e32 v21, 0xdc -; GCN-NEXT: v_mov_b32_e32 v22, 0xe6 -; GCN-NEXT: v_mov_b32_e32 v23, 0xf0 -; GCN-NEXT: v_mov_b32_e32 v24, 0xfa -; GCN-NEXT: v_mov_b32_e32 v25, 0x104 -; GCN-NEXT: v_mov_b32_e32 v26, 0x10e -; GCN-NEXT: v_mov_b32_e32 v27, 0x118 -; GCN-NEXT: v_mov_b32_e32 v28, 0x122 -; GCN-NEXT: v_mov_b32_e32 v29, 0x12c -; GCN-NEXT: v_mov_b32_e32 v30, 0x136 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @too_many_args_use_workitem_id_x( i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80, @@ -931,133 +210,6 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x() #1 { ; GCN: .amdhsa_system_vgpr_workitem_id 0 define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 { -; GFX7-LABEL: func_call_too_many_args_use_workitem_id_x: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: s_mov_b32 s4, s33 -; GFX7-NEXT: s_mov_b32 s33, s32 -; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GFX7-NEXT: s_mov_b64 exec, s[6:7] -; GFX7-NEXT: s_addk_i32 s32, 0x400 -; GFX7-NEXT: v_writelane_b32 v40, s4, 2 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v0, 0x140 -; GFX7-NEXT: v_writelane_b32 v40, s30, 0 -; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], s32 -; GFX7-NEXT: v_mov_b32_e32 v0, 10 -; GFX7-NEXT: v_mov_b32_e32 v1, 20 -; GFX7-NEXT: v_mov_b32_e32 v2, 30 -; GFX7-NEXT: v_mov_b32_e32 v3, 40 -; GFX7-NEXT: v_mov_b32_e32 v4, 50 -; GFX7-NEXT: v_mov_b32_e32 v5, 60 -; GFX7-NEXT: v_mov_b32_e32 v6, 0x46 -; GFX7-NEXT: v_mov_b32_e32 v7, 0x50 -; GFX7-NEXT: v_mov_b32_e32 v8, 0x5a -; GFX7-NEXT: v_mov_b32_e32 v9, 0x64 -; GFX7-NEXT: v_mov_b32_e32 v10, 0x6e -; GFX7-NEXT: v_mov_b32_e32 v11, 0x78 -; GFX7-NEXT: v_mov_b32_e32 v12, 0x82 -; GFX7-NEXT: v_mov_b32_e32 v13, 0x8c -; GFX7-NEXT: v_mov_b32_e32 v14, 0x96 -; GFX7-NEXT: v_mov_b32_e32 v15, 0xa0 -; GFX7-NEXT: v_mov_b32_e32 v16, 0xaa -; GFX7-NEXT: v_mov_b32_e32 v17, 0xb4 -; GFX7-NEXT: v_mov_b32_e32 v18, 0xbe -; GFX7-NEXT: v_mov_b32_e32 v19, 0xc8 -; GFX7-NEXT: v_mov_b32_e32 v20, 0xd2 -; GFX7-NEXT: v_mov_b32_e32 v21, 0xdc -; GFX7-NEXT: v_mov_b32_e32 v22, 0xe6 -; GFX7-NEXT: v_mov_b32_e32 v23, 0xf0 -; GFX7-NEXT: v_mov_b32_e32 v24, 0xfa -; GFX7-NEXT: v_mov_b32_e32 v25, 0x104 -; GFX7-NEXT: v_mov_b32_e32 v26, 0x10e -; GFX7-NEXT: v_mov_b32_e32 v27, 0x118 -; GFX7-NEXT: v_mov_b32_e32 v28, 0x122 -; GFX7-NEXT: v_mov_b32_e32 v29, 0x12c -; GFX7-NEXT: v_mov_b32_e32 v30, 0x136 -; GFX7-NEXT: v_writelane_b32 v40, s31, 1 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: v_readlane_b32 s31, v40, 1 -; GFX7-NEXT: v_readlane_b32 s30, v40, 0 -; GFX7-NEXT: s_mov_b32 s32, s33 -; GFX7-NEXT: v_readlane_b32 s4, v40, 2 -; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GFX7-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GFX7-NEXT: s_mov_b64 exec, s[6:7] -; GFX7-NEXT: s_mov_b32 s33, s4 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: func_call_too_many_args_use_workitem_id_x: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: s_mov_b32 s4, s33 -; GFX90A-NEXT: s_mov_b32 s33, s32 -; GFX90A-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GFX90A-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GFX90A-NEXT: s_mov_b64 exec, s[6:7] -; GFX90A-NEXT: s_addk_i32 s32, 0x400 -; GFX90A-NEXT: v_writelane_b32 v40, s4, 2 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_mov_b32_e32 v0, 0x140 -; GFX90A-NEXT: v_writelane_b32 v40, s30, 0 -; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 -; GFX90A-NEXT: v_mov_b32_e32 v0, 10 -; GFX90A-NEXT: v_mov_b32_e32 v1, 20 -; GFX90A-NEXT: v_mov_b32_e32 v2, 30 -; GFX90A-NEXT: v_mov_b32_e32 v3, 40 -; GFX90A-NEXT: v_mov_b32_e32 v4, 50 -; GFX90A-NEXT: v_mov_b32_e32 v5, 60 -; GFX90A-NEXT: v_mov_b32_e32 v6, 0x46 -; GFX90A-NEXT: v_mov_b32_e32 v7, 0x50 -; GFX90A-NEXT: v_mov_b32_e32 v8, 0x5a -; GFX90A-NEXT: v_mov_b32_e32 v9, 0x64 -; GFX90A-NEXT: v_mov_b32_e32 v10, 0x6e -; GFX90A-NEXT: v_mov_b32_e32 v11, 0x78 -; GFX90A-NEXT: v_mov_b32_e32 v12, 0x82 -; GFX90A-NEXT: v_mov_b32_e32 v13, 0x8c -; GFX90A-NEXT: v_mov_b32_e32 v14, 0x96 -; GFX90A-NEXT: v_mov_b32_e32 v15, 0xa0 -; GFX90A-NEXT: v_mov_b32_e32 v16, 0xaa -; GFX90A-NEXT: v_mov_b32_e32 v17, 0xb4 -; GFX90A-NEXT: v_mov_b32_e32 v18, 0xbe -; GFX90A-NEXT: v_mov_b32_e32 v19, 0xc8 -; GFX90A-NEXT: v_mov_b32_e32 v20, 0xd2 -; GFX90A-NEXT: v_mov_b32_e32 v21, 0xdc -; GFX90A-NEXT: v_mov_b32_e32 v22, 0xe6 -; GFX90A-NEXT: v_mov_b32_e32 v23, 0xf0 -; GFX90A-NEXT: v_mov_b32_e32 v24, 0xfa -; GFX90A-NEXT: v_mov_b32_e32 v25, 0x104 -; GFX90A-NEXT: v_mov_b32_e32 v26, 0x10e -; GFX90A-NEXT: v_mov_b32_e32 v27, 0x118 -; GFX90A-NEXT: v_mov_b32_e32 v28, 0x122 -; GFX90A-NEXT: v_mov_b32_e32 v29, 0x12c -; GFX90A-NEXT: v_mov_b32_e32 v30, 0x136 -; GFX90A-NEXT: v_writelane_b32 v40, s31, 1 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: v_readlane_b32 s31, v40, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v40, 0 -; GFX90A-NEXT: s_mov_b32 s32, s33 -; GFX90A-NEXT: v_readlane_b32 s4, v40, 2 -; GFX90A-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GFX90A-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GFX90A-NEXT: s_mov_b64 exec, s[6:7] -; GFX90A-NEXT: s_mov_b32 s33, s4 -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] store volatile i32 %arg0, ptr addrspace(1) poison call void @too_many_args_use_workitem_id_x( i32 10, i32 20, i32 30, i32 40, @@ -1073,37 +225,6 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 { ; Requires loading and storing to stack slot. define void @too_many_args_call_too_many_args_use_workitem_id_x( -; GCN-LABEL: too_many_args_call_too_many_args_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s33 -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, @@ -1120,155 +241,6 @@ define void @too_many_args_call_too_many_args_use_workitem_id_x( ; frame[0] = stack passed arg23 ; frame[1] = byval arg32 define void @too_many_args_use_workitem_id_x_byval( -; GFX7-LABEL: too_many_args_use_workitem_id_x_byval: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v31, 0x3ff, v31 -; GFX7-NEXT: flat_store_dword v[0:1], v31 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v1 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v2 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v3 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v4 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v5 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v6 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v7 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v8 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v9 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v10 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v11 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v12 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v13 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v14 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v15 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v16 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v17 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v18 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v19 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v20 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v21 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v22 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v23 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v24 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v25 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v26 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v27 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v28 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v29 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v30 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v31 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 glc -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: too_many_args_use_workitem_id_x_byval: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: buffer_load_dword v32, off, s[0:3], s32 -; GFX90A-NEXT: v_and_b32_e32 v31, 0x3ff, v31 -; GFX90A-NEXT: global_store_dword v[0:1], v31, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v1, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v2, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v3, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v4, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v5, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v6, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v7, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v8, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v9, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v10, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v11, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v12, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v13, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v14, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v15, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v16, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v17, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v18, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v19, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v20, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v21, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v22, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v23, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v24, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v25, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v26, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v27, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v28, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v29, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v30, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v32, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 glc -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, @@ -1319,58 +291,6 @@ define void @too_many_args_use_workitem_id_x_byval( ; sp[1] = byval ; Local stack object initialize. Offset 0 is the emergency spill slot. define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 { -; GCN-LABEL: kern_call_too_many_args_use_workitem_id_x_byval: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: v_mov_b32_e32 v31, v0 -; GCN-NEXT: v_mov_b32_e32 v0, 0x3e7 -; GCN-NEXT: s_movk_i32 s32, 0x400 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v0, 0x140 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_byval@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_byval@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_mov_b32_e32 v1, 20 -; GCN-NEXT: v_mov_b32_e32 v2, 30 -; GCN-NEXT: v_mov_b32_e32 v3, 40 -; GCN-NEXT: v_mov_b32_e32 v4, 50 -; GCN-NEXT: v_mov_b32_e32 v5, 60 -; GCN-NEXT: v_mov_b32_e32 v6, 0x46 -; GCN-NEXT: v_mov_b32_e32 v7, 0x50 -; GCN-NEXT: v_mov_b32_e32 v8, 0x5a -; GCN-NEXT: v_mov_b32_e32 v9, 0x64 -; GCN-NEXT: v_mov_b32_e32 v10, 0x6e -; GCN-NEXT: v_mov_b32_e32 v11, 0x78 -; GCN-NEXT: v_mov_b32_e32 v12, 0x82 -; GCN-NEXT: v_mov_b32_e32 v13, 0x8c -; GCN-NEXT: v_mov_b32_e32 v14, 0x96 -; GCN-NEXT: v_mov_b32_e32 v15, 0xa0 -; GCN-NEXT: v_mov_b32_e32 v16, 0xaa -; GCN-NEXT: v_mov_b32_e32 v17, 0xb4 -; GCN-NEXT: v_mov_b32_e32 v18, 0xbe -; GCN-NEXT: v_mov_b32_e32 v19, 0xc8 -; GCN-NEXT: v_mov_b32_e32 v20, 0xd2 -; GCN-NEXT: v_mov_b32_e32 v21, 0xdc -; GCN-NEXT: v_mov_b32_e32 v22, 0xe6 -; GCN-NEXT: v_mov_b32_e32 v23, 0xf0 -; GCN-NEXT: v_mov_b32_e32 v24, 0xfa -; GCN-NEXT: v_mov_b32_e32 v25, 0x104 -; GCN-NEXT: v_mov_b32_e32 v26, 0x10e -; GCN-NEXT: v_mov_b32_e32 v27, 0x118 -; GCN-NEXT: v_mov_b32_e32 v28, 0x122 -; GCN-NEXT: v_mov_b32_e32 v29, 0x12c -; GCN-NEXT: v_mov_b32_e32 v30, 0x136 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 -; GCN-NEXT: v_mov_b32_e32 v0, 10 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm %alloca = alloca i32, align 4, addrspace(5) store volatile i32 999, ptr addrspace(5) %alloca call void @too_many_args_use_workitem_id_x_byval( @@ -1388,73 +308,6 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 ; GCN: .amdhsa_system_vgpr_workitem_id 0 define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { -; GCN-LABEL: func_call_too_many_args_use_workitem_id_x_byval: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_mov_b32_e32 v0, 0x3e7 -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v0, 0x140 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_byval@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_byval@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 20 -; GCN-NEXT: v_mov_b32_e32 v2, 30 -; GCN-NEXT: v_mov_b32_e32 v3, 40 -; GCN-NEXT: v_mov_b32_e32 v4, 50 -; GCN-NEXT: v_mov_b32_e32 v5, 60 -; GCN-NEXT: v_mov_b32_e32 v6, 0x46 -; GCN-NEXT: v_mov_b32_e32 v7, 0x50 -; GCN-NEXT: v_mov_b32_e32 v8, 0x5a -; GCN-NEXT: v_mov_b32_e32 v9, 0x64 -; GCN-NEXT: v_mov_b32_e32 v10, 0x6e -; GCN-NEXT: v_mov_b32_e32 v11, 0x78 -; GCN-NEXT: v_mov_b32_e32 v12, 0x82 -; GCN-NEXT: v_mov_b32_e32 v13, 0x8c -; GCN-NEXT: v_mov_b32_e32 v14, 0x96 -; GCN-NEXT: v_mov_b32_e32 v15, 0xa0 -; GCN-NEXT: v_mov_b32_e32 v16, 0xaa -; GCN-NEXT: v_mov_b32_e32 v17, 0xb4 -; GCN-NEXT: v_mov_b32_e32 v18, 0xbe -; GCN-NEXT: v_mov_b32_e32 v19, 0xc8 -; GCN-NEXT: v_mov_b32_e32 v20, 0xd2 -; GCN-NEXT: v_mov_b32_e32 v21, 0xdc -; GCN-NEXT: v_mov_b32_e32 v22, 0xe6 -; GCN-NEXT: v_mov_b32_e32 v23, 0xf0 -; GCN-NEXT: v_mov_b32_e32 v24, 0xfa -; GCN-NEXT: v_mov_b32_e32 v25, 0x104 -; GCN-NEXT: v_mov_b32_e32 v26, 0x10e -; GCN-NEXT: v_mov_b32_e32 v27, 0x118 -; GCN-NEXT: v_mov_b32_e32 v28, 0x122 -; GCN-NEXT: v_mov_b32_e32 v29, 0x12c -; GCN-NEXT: v_mov_b32_e32 v30, 0x136 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 -; GCN-NEXT: v_mov_b32_e32 v0, 10 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %alloca = alloca i32, align 4, addrspace(5) store volatile i32 999, ptr addrspace(5) %alloca call void @too_many_args_use_workitem_id_x_byval( @@ -1471,163 +324,6 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { } define void @too_many_args_use_workitem_id_xyz( -; GFX7-LABEL: too_many_args_use_workitem_id_xyz: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v32, 0x3ff, v31 -; GFX7-NEXT: flat_store_dword v[0:1], v32 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_bfe_u32 v32, v31, 10, 10 -; GFX7-NEXT: v_bfe_u32 v31, v31, 20, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v32 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v31 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v1 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v2 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v3 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v4 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v5 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v6 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v7 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v8 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v9 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v10 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v11 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v12 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v13 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v14 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v15 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v16 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v17 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v18 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v19 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v20 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v21 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v22 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v23 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v24 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v25 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v26 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v27 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v28 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v29 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v30 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v31 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: too_many_args_use_workitem_id_xyz: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: buffer_load_dword v32, off, s[0:3], s32 -; GFX90A-NEXT: v_and_b32_e32 v33, 0x3ff, v31 -; GFX90A-NEXT: global_store_dword v[0:1], v33, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v33, v31, 10, 10 -; GFX90A-NEXT: v_bfe_u32 v31, v31, 20, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v33, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v31, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v1, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v2, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v3, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v4, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v5, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v6, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v7, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v8, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v9, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v10, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v11, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v12, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v13, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v14, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v15, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v16, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v17, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v18, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v19, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v20, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v21, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v22, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v23, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v24, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v25, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v26, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v27, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v28, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v29, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v30, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v32, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, @@ -1680,102 +376,6 @@ define void @too_many_args_use_workitem_id_xyz( ; frame[0] = ID { Z, Y, X } define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_xyz() #1 { -; GFX7-LABEL: kern_call_too_many_args_use_workitem_id_xyz: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_add_u32 s0, s0, s5 -; GFX7-NEXT: s_addc_u32 s1, s1, 0 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_xyz@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_xyz@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 10, v1 -; GFX7-NEXT: s_mov_b32 s32, 0 -; GFX7-NEXT: v_mov_b32_e32 v3, 0x140 -; GFX7-NEXT: v_lshlrev_b32_e32 v2, 20, v2 -; GFX7-NEXT: v_or_b32_e32 v0, v0, v1 -; GFX7-NEXT: buffer_store_dword v3, off, s[0:3], s32 -; GFX7-NEXT: v_or_b32_e32 v31, v0, v2 -; GFX7-NEXT: v_mov_b32_e32 v0, 10 -; GFX7-NEXT: v_mov_b32_e32 v1, 20 -; GFX7-NEXT: v_mov_b32_e32 v2, 30 -; GFX7-NEXT: v_mov_b32_e32 v3, 40 -; GFX7-NEXT: v_mov_b32_e32 v4, 50 -; GFX7-NEXT: v_mov_b32_e32 v5, 60 -; GFX7-NEXT: v_mov_b32_e32 v6, 0x46 -; GFX7-NEXT: v_mov_b32_e32 v7, 0x50 -; GFX7-NEXT: v_mov_b32_e32 v8, 0x5a -; GFX7-NEXT: v_mov_b32_e32 v9, 0x64 -; GFX7-NEXT: v_mov_b32_e32 v10, 0x6e -; GFX7-NEXT: v_mov_b32_e32 v11, 0x78 -; GFX7-NEXT: v_mov_b32_e32 v12, 0x82 -; GFX7-NEXT: v_mov_b32_e32 v13, 0x8c -; GFX7-NEXT: v_mov_b32_e32 v14, 0x96 -; GFX7-NEXT: v_mov_b32_e32 v15, 0xa0 -; GFX7-NEXT: v_mov_b32_e32 v16, 0xaa -; GFX7-NEXT: v_mov_b32_e32 v17, 0xb4 -; GFX7-NEXT: v_mov_b32_e32 v18, 0xbe -; GFX7-NEXT: v_mov_b32_e32 v19, 0xc8 -; GFX7-NEXT: v_mov_b32_e32 v20, 0xd2 -; GFX7-NEXT: v_mov_b32_e32 v21, 0xdc -; GFX7-NEXT: v_mov_b32_e32 v22, 0xe6 -; GFX7-NEXT: v_mov_b32_e32 v23, 0xf0 -; GFX7-NEXT: v_mov_b32_e32 v24, 0xfa -; GFX7-NEXT: v_mov_b32_e32 v25, 0x104 -; GFX7-NEXT: v_mov_b32_e32 v26, 0x10e -; GFX7-NEXT: v_mov_b32_e32 v27, 0x118 -; GFX7-NEXT: v_mov_b32_e32 v28, 0x122 -; GFX7-NEXT: v_mov_b32_e32 v29, 0x12c -; GFX7-NEXT: v_mov_b32_e32 v30, 0x136 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: s_endpgm -; -; GFX90A-LABEL: kern_call_too_many_args_use_workitem_id_xyz: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_add_u32 s0, s0, s5 -; GFX90A-NEXT: s_addc_u32 s1, s1, 0 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_xyz@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_xyz@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: s_mov_b32 s32, 0 -; GFX90A-NEXT: v_mov_b32_e32 v1, 0x140 -; GFX90A-NEXT: buffer_store_dword v1, off, s[0:3], s32 -; GFX90A-NEXT: v_mov_b32_e32 v31, v0 -; GFX90A-NEXT: v_mov_b32_e32 v0, 10 -; GFX90A-NEXT: v_mov_b32_e32 v1, 20 -; GFX90A-NEXT: v_mov_b32_e32 v2, 30 -; GFX90A-NEXT: v_mov_b32_e32 v3, 40 -; GFX90A-NEXT: v_mov_b32_e32 v4, 50 -; GFX90A-NEXT: v_mov_b32_e32 v5, 60 -; GFX90A-NEXT: v_mov_b32_e32 v6, 0x46 -; GFX90A-NEXT: v_mov_b32_e32 v7, 0x50 -; GFX90A-NEXT: v_mov_b32_e32 v8, 0x5a -; GFX90A-NEXT: v_mov_b32_e32 v9, 0x64 -; GFX90A-NEXT: v_mov_b32_e32 v10, 0x6e -; GFX90A-NEXT: v_mov_b32_e32 v11, 0x78 -; GFX90A-NEXT: v_mov_b32_e32 v12, 0x82 -; GFX90A-NEXT: v_mov_b32_e32 v13, 0x8c -; GFX90A-NEXT: v_mov_b32_e32 v14, 0x96 -; GFX90A-NEXT: v_mov_b32_e32 v15, 0xa0 -; GFX90A-NEXT: v_mov_b32_e32 v16, 0xaa -; GFX90A-NEXT: v_mov_b32_e32 v17, 0xb4 -; GFX90A-NEXT: v_mov_b32_e32 v18, 0xbe -; GFX90A-NEXT: v_mov_b32_e32 v19, 0xc8 -; GFX90A-NEXT: v_mov_b32_e32 v20, 0xd2 -; GFX90A-NEXT: v_mov_b32_e32 v21, 0xdc -; GFX90A-NEXT: v_mov_b32_e32 v22, 0xe6 -; GFX90A-NEXT: v_mov_b32_e32 v23, 0xf0 -; GFX90A-NEXT: v_mov_b32_e32 v24, 0xfa -; GFX90A-NEXT: v_mov_b32_e32 v25, 0x104 -; GFX90A-NEXT: v_mov_b32_e32 v26, 0x10e -; GFX90A-NEXT: v_mov_b32_e32 v27, 0x118 -; GFX90A-NEXT: v_mov_b32_e32 v28, 0x122 -; GFX90A-NEXT: v_mov_b32_e32 v29, 0x12c -; GFX90A-NEXT: v_mov_b32_e32 v30, 0x136 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: s_endpgm call void @too_many_args_use_workitem_id_xyz( i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80, @@ -1793,157 +393,6 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_xyz() #1 { ; v31 = workitem ID X ; frame[0] = workitem { Z, Y, X } define void @too_many_args_use_workitem_id_x_stack_yz( -; GFX7-LABEL: too_many_args_use_workitem_id_x_stack_yz: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v32, 0x3ff, v31 -; GFX7-NEXT: flat_store_dword v[0:1], v32 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_bfe_u32 v32, v31, 10, 10 -; GFX7-NEXT: v_bfe_u32 v31, v31, 20, 10 -; GFX7-NEXT: flat_store_dword v[0:1], v32 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v31 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v0 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v1 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v2 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v3 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v4 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v5 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v6 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v7 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v8 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v9 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v10 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v11 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v12 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v13 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v14 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v15 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v16 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v17 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v18 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v19 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v20 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v21 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v22 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v23 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v24 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v25 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v26 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v27 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v28 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v29 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: flat_store_dword v[0:1], v30 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX90A-LABEL: too_many_args_use_workitem_id_x_stack_yz: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX90A-NEXT: v_and_b32_e32 v32, 0x3ff, v31 -; GFX90A-NEXT: global_store_dword v[0:1], v32, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_bfe_u32 v32, v31, 10, 10 -; GFX90A-NEXT: v_bfe_u32 v31, v31, 20, 10 -; GFX90A-NEXT: global_store_dword v[0:1], v32, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v31, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v0, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v1, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v2, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v3, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v4, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v5, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v6, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v7, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v8, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v9, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v10, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v11, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v12, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v13, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v14, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v15, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v16, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v17, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v18, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v19, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v20, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v21, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v22, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v23, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v24, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v25, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v26, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v27, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v28, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v29, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: global_store_dword v[0:1], v30, off -; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: s_setpc_b64 s[30:31] i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, @@ -1995,98 +444,6 @@ define void @too_many_args_use_workitem_id_x_stack_yz( ; GCN: ScratchSize: 0 define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_stack_yz() #1 { -; GFX7-LABEL: kern_call_too_many_args_use_workitem_id_x_stack_yz: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_add_u32 s0, s0, s5 -; GFX7-NEXT: s_addc_u32 s1, s1, 0 -; GFX7-NEXT: s_getpc_b64 s[4:5] -; GFX7-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_stack_yz@gotpcrel32@lo+4 -; GFX7-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_stack_yz@gotpcrel32@hi+12 -; GFX7-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 10, v1 -; GFX7-NEXT: v_lshlrev_b32_e32 v2, 20, v2 -; GFX7-NEXT: v_or_b32_e32 v0, v0, v1 -; GFX7-NEXT: v_or_b32_e32 v31, v0, v2 -; GFX7-NEXT: v_mov_b32_e32 v0, 10 -; GFX7-NEXT: v_mov_b32_e32 v1, 20 -; GFX7-NEXT: v_mov_b32_e32 v2, 30 -; GFX7-NEXT: v_mov_b32_e32 v3, 40 -; GFX7-NEXT: v_mov_b32_e32 v4, 50 -; GFX7-NEXT: v_mov_b32_e32 v5, 60 -; GFX7-NEXT: v_mov_b32_e32 v6, 0x46 -; GFX7-NEXT: v_mov_b32_e32 v7, 0x50 -; GFX7-NEXT: v_mov_b32_e32 v8, 0x5a -; GFX7-NEXT: v_mov_b32_e32 v9, 0x64 -; GFX7-NEXT: v_mov_b32_e32 v10, 0x6e -; GFX7-NEXT: v_mov_b32_e32 v11, 0x78 -; GFX7-NEXT: v_mov_b32_e32 v12, 0x82 -; GFX7-NEXT: v_mov_b32_e32 v13, 0x8c -; GFX7-NEXT: v_mov_b32_e32 v14, 0x96 -; GFX7-NEXT: v_mov_b32_e32 v15, 0xa0 -; GFX7-NEXT: v_mov_b32_e32 v16, 0xaa -; GFX7-NEXT: v_mov_b32_e32 v17, 0xb4 -; GFX7-NEXT: v_mov_b32_e32 v18, 0xbe -; GFX7-NEXT: v_mov_b32_e32 v19, 0xc8 -; GFX7-NEXT: v_mov_b32_e32 v20, 0xd2 -; GFX7-NEXT: v_mov_b32_e32 v21, 0xdc -; GFX7-NEXT: v_mov_b32_e32 v22, 0xe6 -; GFX7-NEXT: v_mov_b32_e32 v23, 0xf0 -; GFX7-NEXT: v_mov_b32_e32 v24, 0xfa -; GFX7-NEXT: v_mov_b32_e32 v25, 0x104 -; GFX7-NEXT: v_mov_b32_e32 v26, 0x10e -; GFX7-NEXT: v_mov_b32_e32 v27, 0x118 -; GFX7-NEXT: v_mov_b32_e32 v28, 0x122 -; GFX7-NEXT: v_mov_b32_e32 v29, 0x12c -; GFX7-NEXT: v_mov_b32_e32 v30, 0x136 -; GFX7-NEXT: s_mov_b32 s32, 0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX7-NEXT: s_endpgm -; -; GFX90A-LABEL: kern_call_too_many_args_use_workitem_id_x_stack_yz: -; GFX90A: ; %bb.0: -; GFX90A-NEXT: s_add_u32 s0, s0, s5 -; GFX90A-NEXT: s_addc_u32 s1, s1, 0 -; GFX90A-NEXT: s_getpc_b64 s[4:5] -; GFX90A-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_stack_yz@gotpcrel32@lo+4 -; GFX90A-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_stack_yz@gotpcrel32@hi+12 -; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX90A-NEXT: v_mov_b32_e32 v31, v0 -; GFX90A-NEXT: v_mov_b32_e32 v0, 10 -; GFX90A-NEXT: v_mov_b32_e32 v1, 20 -; GFX90A-NEXT: v_mov_b32_e32 v2, 30 -; GFX90A-NEXT: v_mov_b32_e32 v3, 40 -; GFX90A-NEXT: v_mov_b32_e32 v4, 50 -; GFX90A-NEXT: v_mov_b32_e32 v5, 60 -; GFX90A-NEXT: v_mov_b32_e32 v6, 0x46 -; GFX90A-NEXT: v_mov_b32_e32 v7, 0x50 -; GFX90A-NEXT: v_mov_b32_e32 v8, 0x5a -; GFX90A-NEXT: v_mov_b32_e32 v9, 0x64 -; GFX90A-NEXT: v_mov_b32_e32 v10, 0x6e -; GFX90A-NEXT: v_mov_b32_e32 v11, 0x78 -; GFX90A-NEXT: v_mov_b32_e32 v12, 0x82 -; GFX90A-NEXT: v_mov_b32_e32 v13, 0x8c -; GFX90A-NEXT: v_mov_b32_e32 v14, 0x96 -; GFX90A-NEXT: v_mov_b32_e32 v15, 0xa0 -; GFX90A-NEXT: v_mov_b32_e32 v16, 0xaa -; GFX90A-NEXT: v_mov_b32_e32 v17, 0xb4 -; GFX90A-NEXT: v_mov_b32_e32 v18, 0xbe -; GFX90A-NEXT: v_mov_b32_e32 v19, 0xc8 -; GFX90A-NEXT: v_mov_b32_e32 v20, 0xd2 -; GFX90A-NEXT: v_mov_b32_e32 v21, 0xdc -; GFX90A-NEXT: v_mov_b32_e32 v22, 0xe6 -; GFX90A-NEXT: v_mov_b32_e32 v23, 0xf0 -; GFX90A-NEXT: v_mov_b32_e32 v24, 0xfa -; GFX90A-NEXT: v_mov_b32_e32 v25, 0x104 -; GFX90A-NEXT: v_mov_b32_e32 v26, 0x10e -; GFX90A-NEXT: v_mov_b32_e32 v27, 0x118 -; GFX90A-NEXT: v_mov_b32_e32 v28, 0x122 -; GFX90A-NEXT: v_mov_b32_e32 v29, 0x12c -; GFX90A-NEXT: v_mov_b32_e32 v30, 0x136 -; GFX90A-NEXT: s_mov_b32 s32, 0 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX90A-NEXT: s_endpgm call void @too_many_args_use_workitem_id_x_stack_yz( i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80, @@ -2106,3 +463,7 @@ declare i32 @llvm.amdgcn.workitem.id.z() #0 attributes #0 = { nounwind readnone speculatable "amdgpu-flat-work-group-size"="1,512" } attributes #1 = { nounwind noinline "amdgpu-flat-work-group-size"="1,512" } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GCN: {{.*}} +; GFX7: {{.*}} +; GFX90A: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll index bb2f06bfe83f8..462793307ab1d 100644 --- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll @@ -4,55 +4,24 @@ target triple = "amdgcn-amd-amdhsa" define void @use_workitem_id_x() #1 { -; GCN-LABEL: use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.x() store volatile i32 %val, ptr addrspace(1) poison ret void } define void @use_workitem_id_y() #1 { -; GCN-LABEL: use_workitem_id_y: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.y() store volatile i32 %val, ptr addrspace(1) poison ret void } define void @use_workitem_id_z() #1 { -; GCN-LABEL: use_workitem_id_z: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.z() store volatile i32 %val, ptr addrspace(1) poison ret void } define void @use_workitem_id_xy() #1 { -; GCN-LABEL: use_workitem_id_xy: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %val0 = call i32 @llvm.amdgcn.workitem.id.x() %val1 = call i32 @llvm.amdgcn.workitem.id.y() store volatile i32 %val0, ptr addrspace(1) poison @@ -61,19 +30,6 @@ define void @use_workitem_id_xy() #1 { } define void @use_workitem_id_xyz() #1 { -; GCN-LABEL: use_workitem_id_xyz: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %val0 = call i32 @llvm.amdgcn.workitem.id.x() %val1 = call i32 @llvm.amdgcn.workitem.id.y() %val2 = call i32 @llvm.amdgcn.workitem.id.z() @@ -84,16 +40,6 @@ define void @use_workitem_id_xyz() #1 { } define void @use_workitem_id_xz() #1 { -; GCN-LABEL: use_workitem_id_xz: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %val0 = call i32 @llvm.amdgcn.workitem.id.x() %val1 = call i32 @llvm.amdgcn.workitem.id.z() store volatile i32 %val0, ptr addrspace(1) poison @@ -102,16 +48,6 @@ define void @use_workitem_id_xz() #1 { } define void @use_workitem_id_yz() #1 { -; GCN-LABEL: use_workitem_id_yz: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %val0 = call i32 @llvm.amdgcn.workitem.id.y() %val1 = call i32 @llvm.amdgcn.workitem.id.z() store volatile i32 %val0, ptr addrspace(1) poison @@ -120,19 +56,6 @@ define void @use_workitem_id_yz() #1 { } define amdgpu_kernel void @kern_indirect_use_workitem_id_x() #1 { -; GCN-LABEL: kern_indirect_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_mov_b32_e32 v31, v0 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @use_workitem_id_x() ret void } @@ -140,231 +63,53 @@ define amdgpu_kernel void @kern_indirect_use_workitem_id_x() #1 { define amdgpu_kernel void @kern_indirect_use_workitem_id_y() #1 { -; GCN-LABEL: kern_indirect_use_workitem_id_y: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_y@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_y@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_lshlrev_b32_e32 v31, 10, v1 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @use_workitem_id_y() ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 1 define amdgpu_kernel void @kern_indirect_use_workitem_id_z() #1 { -; GCN-LABEL: kern_indirect_use_workitem_id_z: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_z@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_z@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_lshlrev_b32_e32 v31, 20, v2 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @use_workitem_id_z() ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 2 define amdgpu_kernel void @kern_indirect_use_workitem_id_xy() #1 { -; GCN-LABEL: kern_indirect_use_workitem_id_xy: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_xy@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_xy@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1 -; GCN-NEXT: v_or_b32_e32 v31, v0, v1 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @use_workitem_id_xy() ret void } define amdgpu_kernel void @kern_indirect_use_workitem_id_xz() #1 { -; GCN-LABEL: kern_indirect_use_workitem_id_xz: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_xz@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_xz@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 20, v2 -; GCN-NEXT: v_or_b32_e32 v31, v0, v1 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @use_workitem_id_xz() ret void } define amdgpu_kernel void @kern_indirect_use_workitem_id_yz() #1 { -; GCN-LABEL: kern_indirect_use_workitem_id_yz: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_yz@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_yz@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v2 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1 -; GCN-NEXT: v_or_b32_e32 v31, v1, v0 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @use_workitem_id_yz() ret void } define amdgpu_kernel void @kern_indirect_use_workitem_id_xyz() #1 { -; GCN-LABEL: kern_indirect_use_workitem_id_xyz: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_xyz@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_xyz@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1 -; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2 -; GCN-NEXT: v_or_b32_e32 v0, v0, v1 -; GCN-NEXT: v_or_b32_e32 v31, v0, v2 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @use_workitem_id_xyz() ret void } define void @func_indirect_use_workitem_id_x() #1 { -; GCN-LABEL: func_indirect_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] call void @use_workitem_id_x() ret void } define void @func_indirect_use_workitem_id_y() #1 { -; GCN-LABEL: func_indirect_use_workitem_id_y: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_y@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_y@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] call void @use_workitem_id_y() ret void } define void @func_indirect_use_workitem_id_z() #1 { -; GCN-LABEL: func_indirect_use_workitem_id_z: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_z@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_z@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] call void @use_workitem_id_z() ret void } define void @other_arg_use_workitem_id_x(i32 %arg0) #1 { -; GCN-LABEL: other_arg_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.x() store volatile i32 %arg0, ptr addrspace(1) poison store volatile i32 %val, ptr addrspace(1) poison @@ -372,15 +117,6 @@ define void @other_arg_use_workitem_id_x(i32 %arg0) #1 { } define void @other_arg_use_workitem_id_y(i32 %arg0) #1 { -; GCN-LABEL: other_arg_use_workitem_id_y: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v31, 10, 10 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.y() store volatile i32 %arg0, ptr addrspace(1) poison store volatile i32 %val, ptr addrspace(1) poison @@ -388,15 +124,6 @@ define void @other_arg_use_workitem_id_y(i32 %arg0) #1 { } define void @other_arg_use_workitem_id_z(i32 %arg0) #1 { -; GCN-LABEL: other_arg_use_workitem_id_z: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v31, 20, 10 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %val = call i32 @llvm.amdgcn.workitem.id.z() store volatile i32 %arg0, ptr addrspace(1) poison store volatile i32 %val, ptr addrspace(1) poison @@ -404,138 +131,24 @@ define void @other_arg_use_workitem_id_z(i32 %arg0) #1 { } define amdgpu_kernel void @kern_indirect_other_arg_use_workitem_id_x() #1 { -; GCN-LABEL: kern_indirect_other_arg_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, other_arg_use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, other_arg_use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_mov_b32_e32 v31, v0 -; GCN-NEXT: v_mov_b32_e32 v0, 0x22b -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @other_arg_use_workitem_id_x(i32 555) ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 0 define amdgpu_kernel void @kern_indirect_other_arg_use_workitem_id_y() #1 { -; GCN-LABEL: kern_indirect_other_arg_use_workitem_id_y: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, other_arg_use_workitem_id_y@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, other_arg_use_workitem_id_y@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_lshlrev_b32_e32 v31, 10, v1 -; GCN-NEXT: v_mov_b32_e32 v0, 0x22b -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @other_arg_use_workitem_id_y(i32 555) ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 1 define amdgpu_kernel void @kern_indirect_other_arg_use_workitem_id_z() #1 { -; GCN-LABEL: kern_indirect_other_arg_use_workitem_id_z: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, other_arg_use_workitem_id_z@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, other_arg_use_workitem_id_z@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_lshlrev_b32_e32 v31, 20, v2 -; GCN-NEXT: v_mov_b32_e32 v0, 0x22b -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @other_arg_use_workitem_id_z(i32 555) ret void } ; GCN: .amdhsa_system_vgpr_workitem_id 2 define void @too_many_args_use_workitem_id_x( -; GCN-LABEL: too_many_args_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_and_b32_e32 v31, 0x3ff, v31 -; GCN-NEXT: flat_store_dword v[0:1], v31 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v1 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v2 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v3 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v5 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v6 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v7 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v8 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v9 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v10 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v11 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v12 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v13 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v14 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v15 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v16 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v17 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v18 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v19 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v20 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v21 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v22 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v23 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v24 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v25 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v26 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v27 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v28 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v29 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v30 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v31 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, @@ -583,52 +196,6 @@ define void @too_many_args_use_workitem_id_x( } define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x() #1 { -; GCN-LABEL: kern_call_too_many_args_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 0x140 -; GCN-NEXT: buffer_store_dword v1, off, s[0:3], s32 -; GCN-NEXT: v_mov_b32_e32 v31, v0 -; GCN-NEXT: v_mov_b32_e32 v0, 10 -; GCN-NEXT: v_mov_b32_e32 v1, 20 -; GCN-NEXT: v_mov_b32_e32 v2, 30 -; GCN-NEXT: v_mov_b32_e32 v3, 40 -; GCN-NEXT: v_mov_b32_e32 v4, 50 -; GCN-NEXT: v_mov_b32_e32 v5, 60 -; GCN-NEXT: v_mov_b32_e32 v6, 0x46 -; GCN-NEXT: v_mov_b32_e32 v7, 0x50 -; GCN-NEXT: v_mov_b32_e32 v8, 0x5a -; GCN-NEXT: v_mov_b32_e32 v9, 0x64 -; GCN-NEXT: v_mov_b32_e32 v10, 0x6e -; GCN-NEXT: v_mov_b32_e32 v11, 0x78 -; GCN-NEXT: v_mov_b32_e32 v12, 0x82 -; GCN-NEXT: v_mov_b32_e32 v13, 0x8c -; GCN-NEXT: v_mov_b32_e32 v14, 0x96 -; GCN-NEXT: v_mov_b32_e32 v15, 0xa0 -; GCN-NEXT: v_mov_b32_e32 v16, 0xaa -; GCN-NEXT: v_mov_b32_e32 v17, 0xb4 -; GCN-NEXT: v_mov_b32_e32 v18, 0xbe -; GCN-NEXT: v_mov_b32_e32 v19, 0xc8 -; GCN-NEXT: v_mov_b32_e32 v20, 0xd2 -; GCN-NEXT: v_mov_b32_e32 v21, 0xdc -; GCN-NEXT: v_mov_b32_e32 v22, 0xe6 -; GCN-NEXT: v_mov_b32_e32 v23, 0xf0 -; GCN-NEXT: v_mov_b32_e32 v24, 0xfa -; GCN-NEXT: v_mov_b32_e32 v25, 0x104 -; GCN-NEXT: v_mov_b32_e32 v26, 0x10e -; GCN-NEXT: v_mov_b32_e32 v27, 0x118 -; GCN-NEXT: v_mov_b32_e32 v28, 0x122 -; GCN-NEXT: v_mov_b32_e32 v29, 0x12c -; GCN-NEXT: v_mov_b32_e32 v30, 0x136 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @too_many_args_use_workitem_id_x( i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80, @@ -643,69 +210,6 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x() #1 { ; GCN: .amdhsa_system_vgpr_workitem_id 0 define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 { -; GCN-LABEL: func_call_too_many_args_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v0, 0x140 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 -; GCN-NEXT: v_mov_b32_e32 v0, 10 -; GCN-NEXT: v_mov_b32_e32 v1, 20 -; GCN-NEXT: v_mov_b32_e32 v2, 30 -; GCN-NEXT: v_mov_b32_e32 v3, 40 -; GCN-NEXT: v_mov_b32_e32 v4, 50 -; GCN-NEXT: v_mov_b32_e32 v5, 60 -; GCN-NEXT: v_mov_b32_e32 v6, 0x46 -; GCN-NEXT: v_mov_b32_e32 v7, 0x50 -; GCN-NEXT: v_mov_b32_e32 v8, 0x5a -; GCN-NEXT: v_mov_b32_e32 v9, 0x64 -; GCN-NEXT: v_mov_b32_e32 v10, 0x6e -; GCN-NEXT: v_mov_b32_e32 v11, 0x78 -; GCN-NEXT: v_mov_b32_e32 v12, 0x82 -; GCN-NEXT: v_mov_b32_e32 v13, 0x8c -; GCN-NEXT: v_mov_b32_e32 v14, 0x96 -; GCN-NEXT: v_mov_b32_e32 v15, 0xa0 -; GCN-NEXT: v_mov_b32_e32 v16, 0xaa -; GCN-NEXT: v_mov_b32_e32 v17, 0xb4 -; GCN-NEXT: v_mov_b32_e32 v18, 0xbe -; GCN-NEXT: v_mov_b32_e32 v19, 0xc8 -; GCN-NEXT: v_mov_b32_e32 v20, 0xd2 -; GCN-NEXT: v_mov_b32_e32 v21, 0xdc -; GCN-NEXT: v_mov_b32_e32 v22, 0xe6 -; GCN-NEXT: v_mov_b32_e32 v23, 0xf0 -; GCN-NEXT: v_mov_b32_e32 v24, 0xfa -; GCN-NEXT: v_mov_b32_e32 v25, 0x104 -; GCN-NEXT: v_mov_b32_e32 v26, 0x10e -; GCN-NEXT: v_mov_b32_e32 v27, 0x118 -; GCN-NEXT: v_mov_b32_e32 v28, 0x122 -; GCN-NEXT: v_mov_b32_e32 v29, 0x12c -; GCN-NEXT: v_mov_b32_e32 v30, 0x136 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] store volatile i32 %arg0, ptr addrspace(1) poison call void @too_many_args_use_workitem_id_x( i32 10, i32 20, i32 30, i32 40, @@ -721,37 +225,6 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 { ; Requires loading and storing to stack slot. define void @too_many_args_call_too_many_args_use_workitem_id_x( -; GCN-LABEL: too_many_args_call_too_many_args_use_workitem_id_x: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s33 -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, @@ -769,80 +242,6 @@ define void @too_many_args_call_too_many_args_use_workitem_id_x( ; frame[1] = stack passed workitem ID x ; frame[2] = VGPR spill slot define void @too_many_args_use_workitem_id_x_byval( -; GCN-LABEL: too_many_args_use_workitem_id_x_byval: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_and_b32_e32 v31, 0x3ff, v31 -; GCN-NEXT: flat_store_dword v[0:1], v31 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v1 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v2 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v3 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v5 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v6 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v7 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v8 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v9 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v10 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v11 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v12 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v13 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v14 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v15 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v16 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v17 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v18 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v19 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v20 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v21 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v22 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v23 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v24 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v25 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v26 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v27 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v28 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v29 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v30 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v31 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 glc -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, @@ -894,58 +293,6 @@ define void @too_many_args_use_workitem_id_x_byval( ; sp[1] = ?? ; sp[2] = stack passed workitem ID x define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 { -; GCN-LABEL: kern_call_too_many_args_use_workitem_id_x_byval: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: v_mov_b32_e32 v31, v0 -; GCN-NEXT: v_mov_b32_e32 v0, 0x3e7 -; GCN-NEXT: s_movk_i32 s32, 0x400 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v0, 0x140 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_byval@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_byval@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_mov_b32_e32 v1, 20 -; GCN-NEXT: v_mov_b32_e32 v2, 30 -; GCN-NEXT: v_mov_b32_e32 v3, 40 -; GCN-NEXT: v_mov_b32_e32 v4, 50 -; GCN-NEXT: v_mov_b32_e32 v5, 60 -; GCN-NEXT: v_mov_b32_e32 v6, 0x46 -; GCN-NEXT: v_mov_b32_e32 v7, 0x50 -; GCN-NEXT: v_mov_b32_e32 v8, 0x5a -; GCN-NEXT: v_mov_b32_e32 v9, 0x64 -; GCN-NEXT: v_mov_b32_e32 v10, 0x6e -; GCN-NEXT: v_mov_b32_e32 v11, 0x78 -; GCN-NEXT: v_mov_b32_e32 v12, 0x82 -; GCN-NEXT: v_mov_b32_e32 v13, 0x8c -; GCN-NEXT: v_mov_b32_e32 v14, 0x96 -; GCN-NEXT: v_mov_b32_e32 v15, 0xa0 -; GCN-NEXT: v_mov_b32_e32 v16, 0xaa -; GCN-NEXT: v_mov_b32_e32 v17, 0xb4 -; GCN-NEXT: v_mov_b32_e32 v18, 0xbe -; GCN-NEXT: v_mov_b32_e32 v19, 0xc8 -; GCN-NEXT: v_mov_b32_e32 v20, 0xd2 -; GCN-NEXT: v_mov_b32_e32 v21, 0xdc -; GCN-NEXT: v_mov_b32_e32 v22, 0xe6 -; GCN-NEXT: v_mov_b32_e32 v23, 0xf0 -; GCN-NEXT: v_mov_b32_e32 v24, 0xfa -; GCN-NEXT: v_mov_b32_e32 v25, 0x104 -; GCN-NEXT: v_mov_b32_e32 v26, 0x10e -; GCN-NEXT: v_mov_b32_e32 v27, 0x118 -; GCN-NEXT: v_mov_b32_e32 v28, 0x122 -; GCN-NEXT: v_mov_b32_e32 v29, 0x12c -; GCN-NEXT: v_mov_b32_e32 v30, 0x136 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 -; GCN-NEXT: v_mov_b32_e32 v0, 10 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm %alloca = alloca i32, align 4, addrspace(5) store volatile i32 999, ptr addrspace(5) %alloca call void @too_many_args_use_workitem_id_x_byval( @@ -962,73 +309,6 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 } define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { -; GCN-LABEL: func_call_too_many_args_use_workitem_id_x_byval: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_mov_b32_e32 v0, 0x3e7 -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v0, 0x140 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 -; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_byval@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_byval@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 20 -; GCN-NEXT: v_mov_b32_e32 v2, 30 -; GCN-NEXT: v_mov_b32_e32 v3, 40 -; GCN-NEXT: v_mov_b32_e32 v4, 50 -; GCN-NEXT: v_mov_b32_e32 v5, 60 -; GCN-NEXT: v_mov_b32_e32 v6, 0x46 -; GCN-NEXT: v_mov_b32_e32 v7, 0x50 -; GCN-NEXT: v_mov_b32_e32 v8, 0x5a -; GCN-NEXT: v_mov_b32_e32 v9, 0x64 -; GCN-NEXT: v_mov_b32_e32 v10, 0x6e -; GCN-NEXT: v_mov_b32_e32 v11, 0x78 -; GCN-NEXT: v_mov_b32_e32 v12, 0x82 -; GCN-NEXT: v_mov_b32_e32 v13, 0x8c -; GCN-NEXT: v_mov_b32_e32 v14, 0x96 -; GCN-NEXT: v_mov_b32_e32 v15, 0xa0 -; GCN-NEXT: v_mov_b32_e32 v16, 0xaa -; GCN-NEXT: v_mov_b32_e32 v17, 0xb4 -; GCN-NEXT: v_mov_b32_e32 v18, 0xbe -; GCN-NEXT: v_mov_b32_e32 v19, 0xc8 -; GCN-NEXT: v_mov_b32_e32 v20, 0xd2 -; GCN-NEXT: v_mov_b32_e32 v21, 0xdc -; GCN-NEXT: v_mov_b32_e32 v22, 0xe6 -; GCN-NEXT: v_mov_b32_e32 v23, 0xf0 -; GCN-NEXT: v_mov_b32_e32 v24, 0xfa -; GCN-NEXT: v_mov_b32_e32 v25, 0x104 -; GCN-NEXT: v_mov_b32_e32 v26, 0x10e -; GCN-NEXT: v_mov_b32_e32 v27, 0x118 -; GCN-NEXT: v_mov_b32_e32 v28, 0x122 -; GCN-NEXT: v_mov_b32_e32 v29, 0x12c -; GCN-NEXT: v_mov_b32_e32 v30, 0x136 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 -; GCN-NEXT: v_mov_b32_e32 v0, 10 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] %alloca = alloca i32, align 4, addrspace(5) store volatile i32 999, ptr addrspace(5) %alloca call void @too_many_args_use_workitem_id_x_byval( @@ -1045,84 +325,6 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { } define void @too_many_args_use_workitem_id_xyz( -; GCN-LABEL: too_many_args_use_workitem_id_xyz: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_and_b32_e32 v32, 0x3ff, v31 -; GCN-NEXT: flat_store_dword v[0:1], v32 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_bfe_u32 v32, v31, 10, 10 -; GCN-NEXT: v_bfe_u32 v31, v31, 20, 10 -; GCN-NEXT: flat_store_dword v[0:1], v32 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v31 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v1 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v2 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v3 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v5 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v6 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v7 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v8 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v9 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v10 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v11 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v12 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v13 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v14 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v15 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v16 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v17 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v18 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v19 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v20 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v21 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v22 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v23 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v24 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v25 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v26 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v27 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v28 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v29 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v30 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v31 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, @@ -1174,55 +376,6 @@ define void @too_many_args_use_workitem_id_xyz( } define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_xyz() #1 { -; GCN-LABEL: kern_call_too_many_args_use_workitem_id_xyz: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_xyz@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_xyz@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: v_mov_b32_e32 v3, 0x140 -; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2 -; GCN-NEXT: v_or_b32_e32 v0, v0, v1 -; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 -; GCN-NEXT: v_or_b32_e32 v31, v0, v2 -; GCN-NEXT: v_mov_b32_e32 v0, 10 -; GCN-NEXT: v_mov_b32_e32 v1, 20 -; GCN-NEXT: v_mov_b32_e32 v2, 30 -; GCN-NEXT: v_mov_b32_e32 v3, 40 -; GCN-NEXT: v_mov_b32_e32 v4, 50 -; GCN-NEXT: v_mov_b32_e32 v5, 60 -; GCN-NEXT: v_mov_b32_e32 v6, 0x46 -; GCN-NEXT: v_mov_b32_e32 v7, 0x50 -; GCN-NEXT: v_mov_b32_e32 v8, 0x5a -; GCN-NEXT: v_mov_b32_e32 v9, 0x64 -; GCN-NEXT: v_mov_b32_e32 v10, 0x6e -; GCN-NEXT: v_mov_b32_e32 v11, 0x78 -; GCN-NEXT: v_mov_b32_e32 v12, 0x82 -; GCN-NEXT: v_mov_b32_e32 v13, 0x8c -; GCN-NEXT: v_mov_b32_e32 v14, 0x96 -; GCN-NEXT: v_mov_b32_e32 v15, 0xa0 -; GCN-NEXT: v_mov_b32_e32 v16, 0xaa -; GCN-NEXT: v_mov_b32_e32 v17, 0xb4 -; GCN-NEXT: v_mov_b32_e32 v18, 0xbe -; GCN-NEXT: v_mov_b32_e32 v19, 0xc8 -; GCN-NEXT: v_mov_b32_e32 v20, 0xd2 -; GCN-NEXT: v_mov_b32_e32 v21, 0xdc -; GCN-NEXT: v_mov_b32_e32 v22, 0xe6 -; GCN-NEXT: v_mov_b32_e32 v23, 0xf0 -; GCN-NEXT: v_mov_b32_e32 v24, 0xfa -; GCN-NEXT: v_mov_b32_e32 v25, 0x104 -; GCN-NEXT: v_mov_b32_e32 v26, 0x10e -; GCN-NEXT: v_mov_b32_e32 v27, 0x118 -; GCN-NEXT: v_mov_b32_e32 v28, 0x122 -; GCN-NEXT: v_mov_b32_e32 v29, 0x12c -; GCN-NEXT: v_mov_b32_e32 v30, 0x136 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @too_many_args_use_workitem_id_xyz( i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80, @@ -1240,81 +393,6 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_xyz() #1 { ; v31 = workitem ID X ; frame[0] = workitem { Z, Y, X } define void @too_many_args_use_workitem_id_x_stack_yz( -; GCN-LABEL: too_many_args_use_workitem_id_x_stack_yz: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_and_b32_e32 v32, 0x3ff, v31 -; GCN-NEXT: flat_store_dword v[0:1], v32 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_bfe_u32 v32, v31, 10, 10 -; GCN-NEXT: v_bfe_u32 v31, v31, 20, 10 -; GCN-NEXT: flat_store_dword v[0:1], v32 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v31 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v1 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v2 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v3 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v5 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v6 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v7 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v8 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v9 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v10 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v11 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v12 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v13 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v14 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v15 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v16 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v17 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v18 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v19 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v20 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v21 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v22 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v23 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v24 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v25 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v26 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v27 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v28 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v29 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: flat_store_dword v[0:1], v30 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, @@ -1366,53 +444,6 @@ define void @too_many_args_use_workitem_id_x_stack_yz( ; GCN: ScratchSize: 0 define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_stack_yz() #1 { -; GCN-LABEL: kern_call_too_many_args_use_workitem_id_x_stack_yz: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_u32 s0, s0, s5 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_getpc_b64 s[4:5] -; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_stack_yz@gotpcrel32@lo+4 -; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_stack_yz@gotpcrel32@hi+12 -; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1 -; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2 -; GCN-NEXT: v_or_b32_e32 v0, v0, v1 -; GCN-NEXT: v_or_b32_e32 v31, v0, v2 -; GCN-NEXT: v_mov_b32_e32 v0, 10 -; GCN-NEXT: v_mov_b32_e32 v1, 20 -; GCN-NEXT: v_mov_b32_e32 v2, 30 -; GCN-NEXT: v_mov_b32_e32 v3, 40 -; GCN-NEXT: v_mov_b32_e32 v4, 50 -; GCN-NEXT: v_mov_b32_e32 v5, 60 -; GCN-NEXT: v_mov_b32_e32 v6, 0x46 -; GCN-NEXT: v_mov_b32_e32 v7, 0x50 -; GCN-NEXT: v_mov_b32_e32 v8, 0x5a -; GCN-NEXT: v_mov_b32_e32 v9, 0x64 -; GCN-NEXT: v_mov_b32_e32 v10, 0x6e -; GCN-NEXT: v_mov_b32_e32 v11, 0x78 -; GCN-NEXT: v_mov_b32_e32 v12, 0x82 -; GCN-NEXT: v_mov_b32_e32 v13, 0x8c -; GCN-NEXT: v_mov_b32_e32 v14, 0x96 -; GCN-NEXT: v_mov_b32_e32 v15, 0xa0 -; GCN-NEXT: v_mov_b32_e32 v16, 0xaa -; GCN-NEXT: v_mov_b32_e32 v17, 0xb4 -; GCN-NEXT: v_mov_b32_e32 v18, 0xbe -; GCN-NEXT: v_mov_b32_e32 v19, 0xc8 -; GCN-NEXT: v_mov_b32_e32 v20, 0xd2 -; GCN-NEXT: v_mov_b32_e32 v21, 0xdc -; GCN-NEXT: v_mov_b32_e32 v22, 0xe6 -; GCN-NEXT: v_mov_b32_e32 v23, 0xf0 -; GCN-NEXT: v_mov_b32_e32 v24, 0xfa -; GCN-NEXT: v_mov_b32_e32 v25, 0x104 -; GCN-NEXT: v_mov_b32_e32 v26, 0x10e -; GCN-NEXT: v_mov_b32_e32 v27, 0x118 -; GCN-NEXT: v_mov_b32_e32 v28, 0x122 -; GCN-NEXT: v_mov_b32_e32 v29, 0x12c -; GCN-NEXT: v_mov_b32_e32 v30, 0x136 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: s_endpgm call void @too_many_args_use_workitem_id_x_stack_yz( i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80, @@ -1430,55 +461,11 @@ declare hidden void @extern_hint(i32) #2 ; Workitem IDs should not be passed due to the attribute define amdgpu_kernel void @kern_call_no_workitem_id_hints() #2 { -; GCN-LABEL: kern_call_no_workitem_id_hints: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_i32 s12, s12, s17 -; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 -; GCN-NEXT: s_add_u32 s0, s0, s17 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13 -; GCN-NEXT: s_mov_b32 s13, s15 -; GCN-NEXT: s_mov_b32 s12, s14 -; GCN-NEXT: s_getpc_b64 s[18:19] -; GCN-NEXT: s_add_u32 s18, s18, extern_hint@rel32@lo+4 -; GCN-NEXT: s_addc_u32 s19, s19, extern_hint@rel32@hi+12 -; GCN-NEXT: s_mov_b32 s14, s16 -; GCN-NEXT: v_mov_b32_e32 v0, 9 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GCN-NEXT: s_endpgm call void @extern_hint(i32 9) ret void } define void @func_call_no_workitem_id_hints() #2 { -; GCN-LABEL: func_call_no_workitem_id_hints: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s16, s33 -; GCN-NEXT: s_mov_b32 s33, s32 -; GCN-NEXT: s_or_saveexec_b64 s[18:19], -1 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: s_mov_b64 exec, s[18:19] -; GCN-NEXT: v_writelane_b32 v40, s16, 2 -; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: s_getpc_b64 s[16:17] -; GCN-NEXT: s_add_u32 s16, s16, extern_hint@rel32@lo+4 -; GCN-NEXT: s_addc_u32 s17, s17, extern_hint@rel32@hi+12 -; GCN-NEXT: v_mov_b32_e32 v0, 9 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 -; GCN-NEXT: s_mov_b32 s32, s33 -; GCN-NEXT: v_readlane_b32 s4, v40, 2 -; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_setpc_b64 s[30:31] call void @extern_hint(i32 9) ret void } @@ -1488,23 +475,6 @@ declare hidden void @extern_nohint(i32) ; Check that the hint is respected on the callsite, not the function ; declaration define amdgpu_kernel void @kern_callsite_workitem_id_hints() #2 { -; GCN-LABEL: kern_callsite_workitem_id_hints: -; GCN: ; %bb.0: -; GCN-NEXT: s_add_i32 s12, s12, s17 -; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 -; GCN-NEXT: s_add_u32 s0, s0, s17 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13 -; GCN-NEXT: s_mov_b32 s13, s15 -; GCN-NEXT: s_mov_b32 s12, s14 -; GCN-NEXT: s_getpc_b64 s[18:19] -; GCN-NEXT: s_add_u32 s18, s18, extern_nohint@rel32@lo+4 -; GCN-NEXT: s_addc_u32 s19, s19, extern_nohint@rel32@hi+12 -; GCN-NEXT: s_mov_b32 s14, s16 -; GCN-NEXT: v_mov_b32_e32 v0, 9 -; GCN-NEXT: s_mov_b32 s32, 0 -; GCN-NEXT: s_swappc_b64 s[30:31], s[18:19] -; GCN-NEXT: s_endpgm call void @extern_nohint(i32 9) #2 ret void } @@ -1519,3 +489,5 @@ attributes #2 = { nounwind "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" " !llvm.module.flags = !{!0} !0 = !{i32 1, !"amdhsa_code_object_version", i32 400} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GCN: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll index b96de173dc8c6..2904bdbbdda3d 100644 --- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll +++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll @@ -3058,14 +3058,14 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1250-NEXT: s_cvt_f32_u32 s5, s7 ; GFX1250-NEXT: s_sub_nc_u64 s[10:11], 0, s[6:7] ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(SALU_CYCLE_3) -; GFX1250-NEXT: s_fmac_f32 s4, s5, 0x4f800000 +; GFX1250-NEXT: s_fmamk_f32 s4, s5, 0x4f800000, s4 ; GFX1250-NEXT: v_s_rcp_f32 s4, s4 ; GFX1250-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) ; GFX1250-NEXT: s_mul_f32 s4, s4, 0x5f7ffffc ; GFX1250-NEXT: s_mul_f32 s5, s4, 0x2f800000 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3) ; GFX1250-NEXT: s_trunc_f32 s5, s5 -; GFX1250-NEXT: s_fmac_f32 s4, s5, 0xcf800000 +; GFX1250-NEXT: s_fmamk_f32 s4, s5, 0xcf800000, s4 ; GFX1250-NEXT: s_cvt_u32_f32 s9, s5 ; GFX1250-NEXT: s_mov_b32 s5, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) diff --git a/llvm/test/CodeGen/AMDGPU/cfi-pseudos.mir b/llvm/test/CodeGen/AMDGPU/cfi-pseudos.mir new file mode 100644 index 0000000000000..313daf5911d57 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/cfi-pseudos.mir @@ -0,0 +1,21 @@ +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass none -o - %s | \ +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -x=mir -run-pass none -o - | \ +# RUN: FileCheck %s + +# Verify we can parse and emit these CFI pseudos. + +# CHECK-LABEL: name: test +# CHECK: CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 +# CHECK-NEXT: CFI_INSTRUCTION llvm_vector_registers $sgpr4, $vgpr3, 0, 32 +# CHECK-NEXT: CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr62, 0, 32, $vgpr62, 1, 32 +# CHECK-NEXT: CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 100 +# CHECK-NEXT: CFI_INSTRUCTION llvm_vector_register_mask $agpr1, $vgpr1, 32, $exec, 64 + +name: test +body: | + bb.0: + CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + CFI_INSTRUCTION llvm_vector_registers $sgpr4, $vgpr3, 0, 32 + CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr62, 0, 32, $vgpr62, 1, 32 + CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 100 + CFI_INSTRUCTION llvm_vector_register_mask $agpr1, $vgpr1, 32, $exec, 64 diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir index e7177a5e7160e..fe2b0bb1ff6ae 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir +++ b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir @@ -961,25 +961,3 @@ body: | S_ENDPGM 0, implicit %2, implicit %3 ... - ---- -name: constant_v_or_b32_uses_subreg_or_0_regression -tracksRegLiveness: true -body: | - bb.0: - liveins: $vgpr0, $vgpr1 - - ; GCN-LABEL: name: constant_v_or_b32_uses_subreg_or_0_regression - ; GCN: liveins: $vgpr0, $vgpr1 - ; GCN-NEXT: {{ $}} - ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]] - ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY1]] - %0:vgpr_32 = COPY $vgpr0 - %1:vgpr_32 = COPY $vgpr1 - %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec - %3:vreg_64 = REG_SEQUENCE %2:vgpr_32, %subreg.sub0, %0:vgpr_32, %subreg.sub1 - %4:vgpr_32 = V_OR_B32_e64 %3.sub0:vreg_64, %1, implicit $exec - S_ENDPGM 0, implicit %4 - -... diff --git a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll index 38c20c7cf62d6..9335cc304c294 100644 --- a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll +++ b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll @@ -33,15 +33,15 @@ define float @call_split_type_used_outside_block_v2f32() #0 { ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 2 -; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: v_writelane_b32 v40, s30, 0 +; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, func_v2f32@rel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, func_v2f32@rel32@hi+12 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 2 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -69,15 +69,15 @@ define float @call_split_type_used_outside_block_v3f32() #0 { ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 2 -; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: v_writelane_b32 v40, s30, 0 +; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, func_v3f32@rel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, func_v3f32@rel32@hi+12 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 2 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -105,15 +105,15 @@ define half @call_split_type_used_outside_block_v4f16() #0 { ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 2 -; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: v_writelane_b32 v40, s30, 0 +; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, func_v4f16@rel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, func_v4f16@rel32@hi+12 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 2 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -141,15 +141,15 @@ define { i32, half } @call_split_type_used_outside_block_struct() #0 { ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 2 -; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: v_writelane_b32 v40, s30, 0 +; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, func_struct@rel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, func_struct@rel32@hi+12 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: v_mov_b32_e32 v1, v4 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 2 diff --git a/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir b/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir index 6504f48333485..209ac8e811456 100644 --- a/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir +++ b/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir @@ -15,6 +15,12 @@ body: | ; CHECK: bb.0: ; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 ; CHECK-NEXT: S_NOP 0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: diff --git a/llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll b/llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll index ed609f85918f9..852065ca13d76 100644 --- a/llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll +++ b/llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll @@ -8,6 +8,8 @@ define amdgpu_kernel void @_Z3fooPiiii(ptr addrspace(1) nocapture noundef writeo ; CHECK-NEXT: .cfi_sections .debug_frame ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: .cfi_escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 ; +; CHECK-NEXT: .cfi_undefined 16 ; CHECK-NEXT: .file 1 "." "a.h" ; CHECK-NEXT: .loc 1 5 12 prologue_end ; ./a.h:5:12 @[ a.hip:12:8 ] ; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x8 diff --git a/llvm/test/CodeGen/AMDGPU/debug-frame.ll b/llvm/test/CodeGen/AMDGPU/debug-frame.ll new file mode 100644 index 0000000000000..8ab18f325d1a7 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/debug-frame.ll @@ -0,0 +1,6623 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=asm -o - %s | FileCheck --check-prefixes=CHECK,GFX900 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-spill-vgpr-to-agpr=0 -filetype=asm -o - %s | FileCheck --check-prefixes=CHECK,GFX90A-V2A-DIS %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-spill-vgpr-to-agpr=1 -filetype=asm -o - %s | FileCheck --check-prefixes=CHECK,GFX90A-V2A-EN %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -filetype=asm -o - %s | FileCheck --check-prefixes=CHECK,WAVE32 %s + +define protected amdgpu_kernel void @kern1() #0 { +; CHECK-LABEL: kern1: +; CHECK: .Lfunc_begin0: +; CHECK-NEXT: .cfi_sections .debug_frame +; CHECK-NEXT: .cfi_startproc +; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: .cfi_escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 ; +; CHECK-NEXT: .cfi_undefined 16 +; CHECK-NEXT: s_endpgm +entry: + ret void +} + +define hidden void @func_no_clobber() #0 { +; CHECK-LABEL: func_no_clobber: +; CHECK: .Lfunc_begin1: +; CHECK-NEXT: .cfi_startproc +; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +entry: + ret void +} + +define void @callee_need_to_spill_fp_to_memory() #1 { +; GFX900-LABEL: callee_need_to_spill_fp_to_memory: +; GFX900: .Lfunc_begin2: +; GFX900-NEXT: .cfi_startproc +; GFX900-NEXT: ; %bb.0: +; GFX900-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX900-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX900-NEXT: .cfi_undefined 2560 +; GFX900-NEXT: .cfi_undefined 2561 +; GFX900-NEXT: .cfi_undefined 2562 +; GFX900-NEXT: .cfi_undefined 2563 +; GFX900-NEXT: .cfi_undefined 2564 +; GFX900-NEXT: .cfi_undefined 2565 +; GFX900-NEXT: .cfi_undefined 2566 +; GFX900-NEXT: .cfi_undefined 2567 +; GFX900-NEXT: .cfi_undefined 2568 +; GFX900-NEXT: .cfi_undefined 2569 +; GFX900-NEXT: .cfi_undefined 2570 +; GFX900-NEXT: .cfi_undefined 2571 +; GFX900-NEXT: .cfi_undefined 2572 +; GFX900-NEXT: .cfi_undefined 2573 +; GFX900-NEXT: .cfi_undefined 2574 +; GFX900-NEXT: .cfi_undefined 2575 +; GFX900-NEXT: .cfi_undefined 2576 +; GFX900-NEXT: .cfi_undefined 2577 +; GFX900-NEXT: .cfi_undefined 2578 +; GFX900-NEXT: .cfi_undefined 2579 +; GFX900-NEXT: .cfi_undefined 2580 +; GFX900-NEXT: .cfi_undefined 2581 +; GFX900-NEXT: .cfi_undefined 2582 +; GFX900-NEXT: .cfi_undefined 2583 +; GFX900-NEXT: .cfi_undefined 2584 +; GFX900-NEXT: .cfi_undefined 2585 +; GFX900-NEXT: .cfi_undefined 2586 +; GFX900-NEXT: .cfi_undefined 2587 +; GFX900-NEXT: .cfi_undefined 2588 +; GFX900-NEXT: .cfi_undefined 2589 +; GFX900-NEXT: .cfi_undefined 2590 +; GFX900-NEXT: .cfi_undefined 2591 +; GFX900-NEXT: .cfi_undefined 2592 +; GFX900-NEXT: .cfi_undefined 2593 +; GFX900-NEXT: .cfi_undefined 2594 +; GFX900-NEXT: .cfi_undefined 2595 +; GFX900-NEXT: .cfi_undefined 2596 +; GFX900-NEXT: .cfi_undefined 2597 +; GFX900-NEXT: .cfi_undefined 2598 +; GFX900-NEXT: .cfi_undefined 2599 +; GFX900-NEXT: .cfi_undefined 2608 +; GFX900-NEXT: .cfi_undefined 2609 +; GFX900-NEXT: .cfi_undefined 2610 +; GFX900-NEXT: .cfi_undefined 2611 +; GFX900-NEXT: .cfi_undefined 2612 +; GFX900-NEXT: .cfi_undefined 2613 +; GFX900-NEXT: .cfi_undefined 2614 +; GFX900-NEXT: .cfi_undefined 2615 +; GFX900-NEXT: .cfi_undefined 2624 +; GFX900-NEXT: .cfi_undefined 2625 +; GFX900-NEXT: .cfi_undefined 2626 +; GFX900-NEXT: .cfi_undefined 2627 +; GFX900-NEXT: .cfi_undefined 2628 +; GFX900-NEXT: .cfi_undefined 2629 +; GFX900-NEXT: .cfi_undefined 2630 +; GFX900-NEXT: .cfi_undefined 2631 +; GFX900-NEXT: .cfi_undefined 2640 +; GFX900-NEXT: .cfi_undefined 2641 +; GFX900-NEXT: .cfi_undefined 2642 +; GFX900-NEXT: .cfi_undefined 2643 +; GFX900-NEXT: .cfi_undefined 2644 +; GFX900-NEXT: .cfi_undefined 2645 +; GFX900-NEXT: .cfi_undefined 2646 +; GFX900-NEXT: .cfi_undefined 2647 +; GFX900-NEXT: .cfi_undefined 2656 +; GFX900-NEXT: .cfi_undefined 2657 +; GFX900-NEXT: .cfi_undefined 2658 +; GFX900-NEXT: .cfi_undefined 2659 +; GFX900-NEXT: .cfi_undefined 2660 +; GFX900-NEXT: .cfi_undefined 2661 +; GFX900-NEXT: .cfi_undefined 2662 +; GFX900-NEXT: .cfi_undefined 2663 +; GFX900-NEXT: .cfi_undefined 2672 +; GFX900-NEXT: .cfi_undefined 2673 +; GFX900-NEXT: .cfi_undefined 2674 +; GFX900-NEXT: .cfi_undefined 2675 +; GFX900-NEXT: .cfi_undefined 2676 +; GFX900-NEXT: .cfi_undefined 2677 +; GFX900-NEXT: .cfi_undefined 2678 +; GFX900-NEXT: .cfi_undefined 2679 +; GFX900-NEXT: .cfi_undefined 2688 +; GFX900-NEXT: .cfi_undefined 2689 +; GFX900-NEXT: .cfi_undefined 2690 +; GFX900-NEXT: .cfi_undefined 2691 +; GFX900-NEXT: .cfi_undefined 2692 +; GFX900-NEXT: .cfi_undefined 2693 +; GFX900-NEXT: .cfi_undefined 2694 +; GFX900-NEXT: .cfi_undefined 2695 +; GFX900-NEXT: .cfi_undefined 2704 +; GFX900-NEXT: .cfi_undefined 2705 +; GFX900-NEXT: .cfi_undefined 2706 +; GFX900-NEXT: .cfi_undefined 2707 +; GFX900-NEXT: .cfi_undefined 2708 +; GFX900-NEXT: .cfi_undefined 2709 +; GFX900-NEXT: .cfi_undefined 2710 +; GFX900-NEXT: .cfi_undefined 2711 +; GFX900-NEXT: .cfi_undefined 2720 +; GFX900-NEXT: .cfi_undefined 2721 +; GFX900-NEXT: .cfi_undefined 2722 +; GFX900-NEXT: .cfi_undefined 2723 +; GFX900-NEXT: .cfi_undefined 2724 +; GFX900-NEXT: .cfi_undefined 2725 +; GFX900-NEXT: .cfi_undefined 2726 +; GFX900-NEXT: .cfi_undefined 2727 +; GFX900-NEXT: .cfi_undefined 2736 +; GFX900-NEXT: .cfi_undefined 2737 +; GFX900-NEXT: .cfi_undefined 2738 +; GFX900-NEXT: .cfi_undefined 2739 +; GFX900-NEXT: .cfi_undefined 2740 +; GFX900-NEXT: .cfi_undefined 2741 +; GFX900-NEXT: .cfi_undefined 2742 +; GFX900-NEXT: .cfi_undefined 2743 +; GFX900-NEXT: .cfi_undefined 2752 +; GFX900-NEXT: .cfi_undefined 2753 +; GFX900-NEXT: .cfi_undefined 2754 +; GFX900-NEXT: .cfi_undefined 2755 +; GFX900-NEXT: .cfi_undefined 2756 +; GFX900-NEXT: .cfi_undefined 2757 +; GFX900-NEXT: .cfi_undefined 2758 +; GFX900-NEXT: .cfi_undefined 2759 +; GFX900-NEXT: .cfi_undefined 2768 +; GFX900-NEXT: .cfi_undefined 2769 +; GFX900-NEXT: .cfi_undefined 2770 +; GFX900-NEXT: .cfi_undefined 2771 +; GFX900-NEXT: .cfi_undefined 2772 +; GFX900-NEXT: .cfi_undefined 2773 +; GFX900-NEXT: .cfi_undefined 2774 +; GFX900-NEXT: .cfi_undefined 2775 +; GFX900-NEXT: .cfi_undefined 2784 +; GFX900-NEXT: .cfi_undefined 2785 +; GFX900-NEXT: .cfi_undefined 2786 +; GFX900-NEXT: .cfi_undefined 2787 +; GFX900-NEXT: .cfi_undefined 2788 +; GFX900-NEXT: .cfi_undefined 2789 +; GFX900-NEXT: .cfi_undefined 2790 +; GFX900-NEXT: .cfi_undefined 2791 +; GFX900-NEXT: .cfi_undefined 2800 +; GFX900-NEXT: .cfi_undefined 2801 +; GFX900-NEXT: .cfi_undefined 2802 +; GFX900-NEXT: .cfi_undefined 2803 +; GFX900-NEXT: .cfi_undefined 2804 +; GFX900-NEXT: .cfi_undefined 2805 +; GFX900-NEXT: .cfi_undefined 2806 +; GFX900-NEXT: .cfi_undefined 2807 +; GFX900-NEXT: .cfi_undefined 36 +; GFX900-NEXT: .cfi_undefined 37 +; GFX900-NEXT: .cfi_undefined 38 +; GFX900-NEXT: .cfi_undefined 39 +; GFX900-NEXT: .cfi_undefined 40 +; GFX900-NEXT: .cfi_undefined 41 +; GFX900-NEXT: .cfi_undefined 42 +; GFX900-NEXT: .cfi_undefined 43 +; GFX900-NEXT: .cfi_undefined 44 +; GFX900-NEXT: .cfi_undefined 45 +; GFX900-NEXT: .cfi_undefined 46 +; GFX900-NEXT: .cfi_undefined 47 +; GFX900-NEXT: .cfi_undefined 48 +; GFX900-NEXT: .cfi_undefined 49 +; GFX900-NEXT: .cfi_undefined 50 +; GFX900-NEXT: .cfi_undefined 51 +; GFX900-NEXT: .cfi_undefined 52 +; GFX900-NEXT: .cfi_undefined 53 +; GFX900-NEXT: .cfi_undefined 54 +; GFX900-NEXT: .cfi_undefined 55 +; GFX900-NEXT: .cfi_undefined 56 +; GFX900-NEXT: .cfi_undefined 57 +; GFX900-NEXT: .cfi_undefined 58 +; GFX900-NEXT: .cfi_undefined 59 +; GFX900-NEXT: .cfi_undefined 60 +; GFX900-NEXT: .cfi_undefined 61 +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: s_mov_b32 s40, s33 +; GFX900-NEXT: .cfi_register 65, 72 +; GFX900-NEXT: s_mov_b32 s33, s32 +; GFX900-NEXT: .cfi_def_cfa_register 65 +; GFX900-NEXT: s_addk_i32 s32, 0x7100 +; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 28416 +; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 28160 +; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2602, 32, 17, 64, 27904 +; GFX900-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2603, 32, 17, 64, 27648 +; GFX900-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2604, 32, 17, 64, 27392 +; GFX900-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2605, 32, 17, 64, 27136 +; GFX900-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2606, 32, 17, 64, 26880 +; GFX900-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2607, 32, 17, 64, 26624 +; GFX900-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2616, 32, 17, 64, 26368 +; GFX900-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2617, 32, 17, 64, 26112 +; GFX900-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2618, 32, 17, 64, 25856 +; GFX900-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2619, 32, 17, 64, 25600 +; GFX900-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2620, 32, 17, 64, 25344 +; GFX900-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2621, 32, 17, 64, 25088 +; GFX900-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2622, 32, 17, 64, 24832 +; GFX900-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2623, 32, 17, 64, 24576 +; GFX900-NEXT: buffer_store_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2632, 32, 17, 64, 24320 +; GFX900-NEXT: buffer_store_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2633, 32, 17, 64, 24064 +; GFX900-NEXT: buffer_store_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2634, 32, 17, 64, 23808 +; GFX900-NEXT: buffer_store_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2635, 32, 17, 64, 23552 +; GFX900-NEXT: buffer_store_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2636, 32, 17, 64, 23296 +; GFX900-NEXT: buffer_store_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2637, 32, 17, 64, 23040 +; GFX900-NEXT: buffer_store_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2638, 32, 17, 64, 22784 +; GFX900-NEXT: buffer_store_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2639, 32, 17, 64, 22528 +; GFX900-NEXT: buffer_store_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2648, 32, 17, 64, 22272 +; GFX900-NEXT: buffer_store_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2649, 32, 17, 64, 22016 +; GFX900-NEXT: buffer_store_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2650, 32, 17, 64, 21760 +; GFX900-NEXT: buffer_store_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2651, 32, 17, 64, 21504 +; GFX900-NEXT: buffer_store_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2652, 32, 17, 64, 21248 +; GFX900-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2653, 32, 17, 64, 20992 +; GFX900-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2654, 32, 17, 64, 20736 +; GFX900-NEXT: buffer_store_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2655, 32, 17, 64, 20480 +; GFX900-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2664, 32, 17, 64, 20224 +; GFX900-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2665, 32, 17, 64, 19968 +; GFX900-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2666, 32, 17, 64, 19712 +; GFX900-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2667, 32, 17, 64, 19456 +; GFX900-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2668, 32, 17, 64, 19200 +; GFX900-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2669, 32, 17, 64, 18944 +; GFX900-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2670, 32, 17, 64, 18688 +; GFX900-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2671, 32, 17, 64, 18432 +; GFX900-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2680, 32, 17, 64, 18176 +; GFX900-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2681, 32, 17, 64, 17920 +; GFX900-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2682, 32, 17, 64, 17664 +; GFX900-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2683, 32, 17, 64, 17408 +; GFX900-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2684, 32, 17, 64, 17152 +; GFX900-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2685, 32, 17, 64, 16896 +; GFX900-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2686, 32, 17, 64, 16640 +; GFX900-NEXT: buffer_store_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2687, 32, 17, 64, 16384 +; GFX900-NEXT: buffer_store_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2696, 32, 17, 64, 16128 +; GFX900-NEXT: buffer_store_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2697, 32, 17, 64, 15872 +; GFX900-NEXT: buffer_store_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2698, 32, 17, 64, 15616 +; GFX900-NEXT: buffer_store_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2699, 32, 17, 64, 15360 +; GFX900-NEXT: buffer_store_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2700, 32, 17, 64, 15104 +; GFX900-NEXT: buffer_store_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2701, 32, 17, 64, 14848 +; GFX900-NEXT: buffer_store_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2702, 32, 17, 64, 14592 +; GFX900-NEXT: buffer_store_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2703, 32, 17, 64, 14336 +; GFX900-NEXT: buffer_store_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2712, 32, 17, 64, 14080 +; GFX900-NEXT: buffer_store_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2713, 32, 17, 64, 13824 +; GFX900-NEXT: buffer_store_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2714, 32, 17, 64, 13568 +; GFX900-NEXT: buffer_store_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2715, 32, 17, 64, 13312 +; GFX900-NEXT: buffer_store_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2716, 32, 17, 64, 13056 +; GFX900-NEXT: buffer_store_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2717, 32, 17, 64, 12800 +; GFX900-NEXT: buffer_store_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2718, 32, 17, 64, 12544 +; GFX900-NEXT: buffer_store_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2719, 32, 17, 64, 12288 +; GFX900-NEXT: buffer_store_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2728, 32, 17, 64, 12032 +; GFX900-NEXT: buffer_store_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2729, 32, 17, 64, 11776 +; GFX900-NEXT: buffer_store_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2730, 32, 17, 64, 11520 +; GFX900-NEXT: buffer_store_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2731, 32, 17, 64, 11264 +; GFX900-NEXT: buffer_store_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2732, 32, 17, 64, 11008 +; GFX900-NEXT: buffer_store_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2733, 32, 17, 64, 10752 +; GFX900-NEXT: buffer_store_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2734, 32, 17, 64, 10496 +; GFX900-NEXT: buffer_store_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2735, 32, 17, 64, 10240 +; GFX900-NEXT: buffer_store_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2744, 32, 17, 64, 9984 +; GFX900-NEXT: buffer_store_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2745, 32, 17, 64, 9728 +; GFX900-NEXT: buffer_store_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2746, 32, 17, 64, 9472 +; GFX900-NEXT: buffer_store_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2747, 32, 17, 64, 9216 +; GFX900-NEXT: buffer_store_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2748, 32, 17, 64, 8960 +; GFX900-NEXT: buffer_store_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2749, 32, 17, 64, 8704 +; GFX900-NEXT: buffer_store_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2750, 32, 17, 64, 8448 +; GFX900-NEXT: buffer_store_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2751, 32, 17, 64, 8192 +; GFX900-NEXT: buffer_store_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2760, 32, 17, 64, 7936 +; GFX900-NEXT: buffer_store_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2761, 32, 17, 64, 7680 +; GFX900-NEXT: buffer_store_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2762, 32, 17, 64, 7424 +; GFX900-NEXT: buffer_store_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2763, 32, 17, 64, 7168 +; GFX900-NEXT: buffer_store_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2764, 32, 17, 64, 6912 +; GFX900-NEXT: buffer_store_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2765, 32, 17, 64, 6656 +; GFX900-NEXT: buffer_store_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2766, 32, 17, 64, 6400 +; GFX900-NEXT: buffer_store_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2767, 32, 17, 64, 6144 +; GFX900-NEXT: buffer_store_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2776, 32, 17, 64, 5888 +; GFX900-NEXT: buffer_store_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2777, 32, 17, 64, 5632 +; GFX900-NEXT: buffer_store_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2778, 32, 17, 64, 5376 +; GFX900-NEXT: buffer_store_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2779, 32, 17, 64, 5120 +; GFX900-NEXT: buffer_store_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2780, 32, 17, 64, 4864 +; GFX900-NEXT: buffer_store_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2781, 32, 17, 64, 4608 +; GFX900-NEXT: buffer_store_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2782, 32, 17, 64, 4352 +; GFX900-NEXT: buffer_store_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2783, 32, 17, 64, 4096 +; GFX900-NEXT: buffer_store_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2792, 32, 17, 64, 3840 +; GFX900-NEXT: buffer_store_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2793, 32, 17, 64, 3584 +; GFX900-NEXT: buffer_store_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2794, 32, 17, 64, 3328 +; GFX900-NEXT: buffer_store_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2795, 32, 17, 64, 3072 +; GFX900-NEXT: buffer_store_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2796, 32, 17, 64, 2816 +; GFX900-NEXT: buffer_store_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2797, 32, 17, 64, 2560 +; GFX900-NEXT: buffer_store_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2798, 32, 17, 64, 2304 +; GFX900-NEXT: buffer_store_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2799, 32, 17, 64, 2048 +; GFX900-NEXT: buffer_store_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2808, 32, 17, 64, 1792 +; GFX900-NEXT: buffer_store_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2809, 32, 17, 64, 1536 +; GFX900-NEXT: buffer_store_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2810, 32, 17, 64, 1280 +; GFX900-NEXT: buffer_store_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2811, 32, 17, 64, 1024 +; GFX900-NEXT: buffer_store_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2812, 32, 17, 64, 768 +; GFX900-NEXT: buffer_store_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2813, 32, 17, 64, 512 +; GFX900-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2814, 32, 17, 64, 256 +; GFX900-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2815, 32, 17, 64, 0 +; GFX900-NEXT: ;;#ASMSTART +; GFX900-NEXT: ; clobber nonpreserved SGPRs +; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: ;;#ASMSTART +; GFX900-NEXT: ; clobber all VGPRs +; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: buffer_load_dword v255, off, s[0:3], s33 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Reload +; GFX900-NEXT: s_mov_b32 s32, s33 +; GFX900-NEXT: .cfi_def_cfa_register 64 +; GFX900-NEXT: s_mov_b32 s33, s40 +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-V2A-DIS-LABEL: callee_need_to_spill_fp_to_memory: +; GFX90A-V2A-DIS: .Lfunc_begin2: +; GFX90A-V2A-DIS-NEXT: .cfi_startproc +; GFX90A-V2A-DIS-NEXT: ; %bb.0: +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2560 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2561 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2562 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2563 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2564 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2565 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2566 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2567 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2568 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2569 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2570 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2571 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2572 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2573 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2574 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2575 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2576 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2577 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2578 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2579 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2580 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2581 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2582 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2583 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2584 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2585 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2586 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2587 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2588 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2589 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2590 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2591 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2592 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2593 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2594 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2595 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2596 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2597 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2598 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2599 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2608 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2609 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2610 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2611 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2612 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2613 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2614 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2615 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2624 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2625 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2626 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2627 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2628 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2629 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2630 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2631 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2640 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2641 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2642 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2643 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2644 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2645 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2646 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2647 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2656 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2657 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2658 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2659 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2660 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2661 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2662 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2663 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2672 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2673 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2674 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2675 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2676 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2677 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2678 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2679 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2688 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2689 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2690 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2691 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2692 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2693 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2694 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2695 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2704 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2705 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2706 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2707 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2708 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2709 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2710 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2711 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2720 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2721 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2722 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2723 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2724 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2725 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2726 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2727 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2736 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2737 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2738 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2739 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2740 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2741 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2742 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2743 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2752 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2753 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2754 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2755 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2756 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2757 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2758 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2759 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2768 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2769 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2770 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2771 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2772 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2773 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2774 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2775 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2784 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2785 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2786 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2787 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2788 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2789 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2790 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2791 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2800 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2801 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2802 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2803 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2804 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2805 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2806 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2807 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 36 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 37 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 38 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 39 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 40 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 41 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 42 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 43 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 44 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 45 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 46 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 47 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 48 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 49 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 50 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 51 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 52 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 53 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 54 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 55 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 56 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 57 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 58 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 59 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 60 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 61 +; GFX90A-V2A-DIS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-V2A-DIS-NEXT: s_mov_b32 s40, s33 +; GFX90A-V2A-DIS-NEXT: .cfi_register 65, 72 +; GFX90A-V2A-DIS-NEXT: s_mov_b32 s33, s32 +; GFX90A-V2A-DIS-NEXT: .cfi_def_cfa_register 65 +; GFX90A-V2A-DIS-NEXT: s_addk_i32 s32, 0x7100 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 28416 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 28160 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2602, 32, 17, 64, 27904 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2603, 32, 17, 64, 27648 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2604, 32, 17, 64, 27392 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2605, 32, 17, 64, 27136 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2606, 32, 17, 64, 26880 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2607, 32, 17, 64, 26624 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2616, 32, 17, 64, 26368 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2617, 32, 17, 64, 26112 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2618, 32, 17, 64, 25856 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2619, 32, 17, 64, 25600 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2620, 32, 17, 64, 25344 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2621, 32, 17, 64, 25088 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2622, 32, 17, 64, 24832 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2623, 32, 17, 64, 24576 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2632, 32, 17, 64, 24320 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2633, 32, 17, 64, 24064 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2634, 32, 17, 64, 23808 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2635, 32, 17, 64, 23552 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2636, 32, 17, 64, 23296 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2637, 32, 17, 64, 23040 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2638, 32, 17, 64, 22784 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2639, 32, 17, 64, 22528 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2648, 32, 17, 64, 22272 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2649, 32, 17, 64, 22016 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2650, 32, 17, 64, 21760 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2651, 32, 17, 64, 21504 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2652, 32, 17, 64, 21248 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2653, 32, 17, 64, 20992 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2654, 32, 17, 64, 20736 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2655, 32, 17, 64, 20480 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2664, 32, 17, 64, 20224 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2665, 32, 17, 64, 19968 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2666, 32, 17, 64, 19712 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2667, 32, 17, 64, 19456 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2668, 32, 17, 64, 19200 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2669, 32, 17, 64, 18944 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2670, 32, 17, 64, 18688 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2671, 32, 17, 64, 18432 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2680, 32, 17, 64, 18176 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2681, 32, 17, 64, 17920 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2682, 32, 17, 64, 17664 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2683, 32, 17, 64, 17408 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2684, 32, 17, 64, 17152 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2685, 32, 17, 64, 16896 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2686, 32, 17, 64, 16640 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2687, 32, 17, 64, 16384 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2696, 32, 17, 64, 16128 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2697, 32, 17, 64, 15872 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2698, 32, 17, 64, 15616 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2699, 32, 17, 64, 15360 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2700, 32, 17, 64, 15104 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2701, 32, 17, 64, 14848 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2702, 32, 17, 64, 14592 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2703, 32, 17, 64, 14336 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2712, 32, 17, 64, 14080 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2713, 32, 17, 64, 13824 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2714, 32, 17, 64, 13568 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2715, 32, 17, 64, 13312 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2716, 32, 17, 64, 13056 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2717, 32, 17, 64, 12800 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2718, 32, 17, 64, 12544 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2719, 32, 17, 64, 12288 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2728, 32, 17, 64, 12032 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2729, 32, 17, 64, 11776 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2730, 32, 17, 64, 11520 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2731, 32, 17, 64, 11264 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2732, 32, 17, 64, 11008 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2733, 32, 17, 64, 10752 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2734, 32, 17, 64, 10496 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2735, 32, 17, 64, 10240 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2744, 32, 17, 64, 9984 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2745, 32, 17, 64, 9728 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2746, 32, 17, 64, 9472 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2747, 32, 17, 64, 9216 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2748, 32, 17, 64, 8960 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2749, 32, 17, 64, 8704 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2750, 32, 17, 64, 8448 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2751, 32, 17, 64, 8192 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2760, 32, 17, 64, 7936 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2761, 32, 17, 64, 7680 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2762, 32, 17, 64, 7424 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2763, 32, 17, 64, 7168 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2764, 32, 17, 64, 6912 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2765, 32, 17, 64, 6656 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2766, 32, 17, 64, 6400 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2767, 32, 17, 64, 6144 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2776, 32, 17, 64, 5888 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2777, 32, 17, 64, 5632 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2778, 32, 17, 64, 5376 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2779, 32, 17, 64, 5120 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2780, 32, 17, 64, 4864 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2781, 32, 17, 64, 4608 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2782, 32, 17, 64, 4352 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2783, 32, 17, 64, 4096 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2792, 32, 17, 64, 3840 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2793, 32, 17, 64, 3584 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2794, 32, 17, 64, 3328 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2795, 32, 17, 64, 3072 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2796, 32, 17, 64, 2816 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2797, 32, 17, 64, 2560 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2798, 32, 17, 64, 2304 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2799, 32, 17, 64, 2048 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2808, 32, 17, 64, 1792 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2809, 32, 17, 64, 1536 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2810, 32, 17, 64, 1280 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2811, 32, 17, 64, 1024 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2812, 32, 17, 64, 768 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2813, 32, 17, 64, 512 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2814, 32, 17, 64, 256 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2815, 32, 17, 64, 0 +; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART +; GFX90A-V2A-DIS-NEXT: ; clobber nonpreserved SGPRs +; GFX90A-V2A-DIS-NEXT: ;;#ASMEND +; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART +; GFX90A-V2A-DIS-NEXT: ; clobber all VGPRs +; GFX90A-V2A-DIS-NEXT: ;;#ASMEND +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v255, off, s[0:3], s33 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: s_mov_b32 s32, s33 +; GFX90A-V2A-DIS-NEXT: .cfi_def_cfa_register 64 +; GFX90A-V2A-DIS-NEXT: s_mov_b32 s33, s40 +; GFX90A-V2A-DIS-NEXT: s_waitcnt vmcnt(0) +; GFX90A-V2A-DIS-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-V2A-EN-LABEL: callee_need_to_spill_fp_to_memory: +; GFX90A-V2A-EN: .Lfunc_begin2: +; GFX90A-V2A-EN-NEXT: .cfi_startproc +; GFX90A-V2A-EN-NEXT: ; %bb.0: +; GFX90A-V2A-EN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX90A-V2A-EN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2560 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2561 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2562 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2563 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2564 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2565 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2566 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2567 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2568 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2569 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2570 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2571 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2572 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2573 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2574 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2575 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2576 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2577 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2578 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2579 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2580 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2581 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2582 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2583 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2584 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2585 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2586 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2587 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2588 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2589 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2590 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2591 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2592 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2593 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2594 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2595 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2596 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2597 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2598 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2599 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2608 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2609 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2610 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2611 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2612 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2613 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2614 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2615 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2624 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2625 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2626 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2627 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2628 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2629 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2630 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2631 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2640 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2641 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2642 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2643 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2644 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2645 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2646 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2647 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2656 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2657 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2658 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2659 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2660 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2661 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2662 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2663 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2672 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2673 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2674 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2675 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2676 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2677 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2678 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2679 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2688 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2689 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2690 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2691 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2692 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2693 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2694 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2695 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2704 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2705 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2706 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2707 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2708 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2709 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2710 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2711 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2720 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2721 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2722 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2723 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2724 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2725 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2726 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2727 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2736 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2737 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2738 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2739 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2740 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2741 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2742 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2743 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2752 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2753 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2754 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2755 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2756 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2757 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2758 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2759 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2768 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2769 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2770 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2771 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2772 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2773 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2774 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2775 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2784 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2785 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2786 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2787 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2788 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2789 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2790 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2791 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2800 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2801 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2802 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2803 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2804 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2805 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2806 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2807 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3072 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3073 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3074 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3075 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3076 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3077 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3078 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3079 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3080 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3081 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3082 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3083 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3084 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3085 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3086 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3087 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3088 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3089 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3090 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3091 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3092 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3093 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3094 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3095 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3096 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3097 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3098 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3099 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3100 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3101 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3102 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3103 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 36 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 37 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 38 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 39 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 40 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 41 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 42 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 43 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 44 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 45 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 46 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 47 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 48 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 49 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 50 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 51 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 52 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 53 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 54 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 55 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 56 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 57 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 58 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 59 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 60 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 61 +; GFX90A-V2A-EN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-V2A-EN-NEXT: s_mov_b32 s40, s33 +; GFX90A-V2A-EN-NEXT: .cfi_register 65, 72 +; GFX90A-V2A-EN-NEXT: s_mov_b32 s33, s32 +; GFX90A-V2A-EN-NEXT: .cfi_def_cfa_register 65 +; GFX90A-V2A-EN-NEXT: s_addk_i32 s32, 0x5100 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2600, 3072, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2601, 3073, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2602, 3074, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2603, 3075, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2604, 3076, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2605, 3077, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2606, 3078, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2607, 3079, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2616, 3080, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2617, 3081, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2618, 3082, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2619, 3083, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2620, 3084, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2621, 3085, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2622, 3086, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2623, 3087, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a16, v72 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2632, 3088, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a17, v73 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2633, 3089, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a18, v74 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2634, 3090, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a19, v75 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2635, 3091, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a20, v76 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2636, 3092, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a21, v77 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2637, 3093, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a22, v78 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2638, 3094, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a23, v79 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2639, 3095, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a24, v88 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2648, 3096, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a25, v89 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2649, 3097, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a26, v90 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2650, 3098, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a27, v91 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2651, 3099, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a28, v92 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2652, 3100, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a29, v93 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2653, 3101, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a30, v94 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2654, 3102, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a31, v95 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2655, 3103, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2664, 32, 17, 64, 20224 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2665, 32, 17, 64, 19968 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2666, 32, 17, 64, 19712 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2667, 32, 17, 64, 19456 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2668, 32, 17, 64, 19200 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2669, 32, 17, 64, 18944 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2670, 32, 17, 64, 18688 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2671, 32, 17, 64, 18432 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2680, 32, 17, 64, 18176 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2681, 32, 17, 64, 17920 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2682, 32, 17, 64, 17664 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2683, 32, 17, 64, 17408 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2684, 32, 17, 64, 17152 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2685, 32, 17, 64, 16896 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2686, 32, 17, 64, 16640 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2687, 32, 17, 64, 16384 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2696, 32, 17, 64, 16128 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2697, 32, 17, 64, 15872 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2698, 32, 17, 64, 15616 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2699, 32, 17, 64, 15360 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2700, 32, 17, 64, 15104 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2701, 32, 17, 64, 14848 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2702, 32, 17, 64, 14592 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2703, 32, 17, 64, 14336 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2712, 32, 17, 64, 14080 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2713, 32, 17, 64, 13824 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2714, 32, 17, 64, 13568 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2715, 32, 17, 64, 13312 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2716, 32, 17, 64, 13056 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2717, 32, 17, 64, 12800 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2718, 32, 17, 64, 12544 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2719, 32, 17, 64, 12288 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2728, 32, 17, 64, 12032 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2729, 32, 17, 64, 11776 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2730, 32, 17, 64, 11520 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2731, 32, 17, 64, 11264 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2732, 32, 17, 64, 11008 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2733, 32, 17, 64, 10752 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2734, 32, 17, 64, 10496 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2735, 32, 17, 64, 10240 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2744, 32, 17, 64, 9984 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2745, 32, 17, 64, 9728 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2746, 32, 17, 64, 9472 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2747, 32, 17, 64, 9216 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2748, 32, 17, 64, 8960 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2749, 32, 17, 64, 8704 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2750, 32, 17, 64, 8448 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2751, 32, 17, 64, 8192 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2760, 32, 17, 64, 7936 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2761, 32, 17, 64, 7680 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2762, 32, 17, 64, 7424 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2763, 32, 17, 64, 7168 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2764, 32, 17, 64, 6912 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2765, 32, 17, 64, 6656 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2766, 32, 17, 64, 6400 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2767, 32, 17, 64, 6144 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2776, 32, 17, 64, 5888 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2777, 32, 17, 64, 5632 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2778, 32, 17, 64, 5376 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2779, 32, 17, 64, 5120 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2780, 32, 17, 64, 4864 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2781, 32, 17, 64, 4608 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2782, 32, 17, 64, 4352 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2783, 32, 17, 64, 4096 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2792, 32, 17, 64, 3840 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2793, 32, 17, 64, 3584 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2794, 32, 17, 64, 3328 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2795, 32, 17, 64, 3072 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2796, 32, 17, 64, 2816 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2797, 32, 17, 64, 2560 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2798, 32, 17, 64, 2304 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2799, 32, 17, 64, 2048 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2808, 32, 17, 64, 1792 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2809, 32, 17, 64, 1536 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2810, 32, 17, 64, 1280 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2811, 32, 17, 64, 1024 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2812, 32, 17, 64, 768 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2813, 32, 17, 64, 512 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2814, 32, 17, 64, 256 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2815, 32, 17, 64, 0 +; GFX90A-V2A-EN-NEXT: ;;#ASMSTART +; GFX90A-V2A-EN-NEXT: ; clobber nonpreserved SGPRs +; GFX90A-V2A-EN-NEXT: ;;#ASMEND +; GFX90A-V2A-EN-NEXT: ;;#ASMSTART +; GFX90A-V2A-EN-NEXT: ; clobber all VGPRs +; GFX90A-V2A-EN-NEXT: ;;#ASMEND +; GFX90A-V2A-EN-NEXT: buffer_load_dword v255, off, s[0:3], s33 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: buffer_load_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v95, a31 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v94, a30 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v93, a29 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v92, a28 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v91, a27 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v90, a26 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v89, a25 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v88, a24 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v79, a23 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v78, a22 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v77, a21 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v76, a20 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v75, a19 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v74, a18 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v73, a17 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v72, a16 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v63, a15 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v62, a14 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v61, a13 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v60, a12 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v59, a11 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v58, a10 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v57, a9 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v56, a8 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v47, a7 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v46, a6 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v45, a5 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v44, a4 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v43, a3 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v42, a2 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v41, a1 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v40, a0 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: s_mov_b32 s32, s33 +; GFX90A-V2A-EN-NEXT: .cfi_def_cfa_register 64 +; GFX90A-V2A-EN-NEXT: s_mov_b32 s33, s40 +; GFX90A-V2A-EN-NEXT: s_waitcnt vmcnt(0) +; GFX90A-V2A-EN-NEXT: s_setpc_b64 s[30:31] +; +; WAVE32-LABEL: callee_need_to_spill_fp_to_memory: +; WAVE32: .Lfunc_begin2: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: .cfi_undefined 1536 +; WAVE32-NEXT: .cfi_undefined 1537 +; WAVE32-NEXT: .cfi_undefined 1538 +; WAVE32-NEXT: .cfi_undefined 1539 +; WAVE32-NEXT: .cfi_undefined 1540 +; WAVE32-NEXT: .cfi_undefined 1541 +; WAVE32-NEXT: .cfi_undefined 1542 +; WAVE32-NEXT: .cfi_undefined 1543 +; WAVE32-NEXT: .cfi_undefined 1544 +; WAVE32-NEXT: .cfi_undefined 1545 +; WAVE32-NEXT: .cfi_undefined 1546 +; WAVE32-NEXT: .cfi_undefined 1547 +; WAVE32-NEXT: .cfi_undefined 1548 +; WAVE32-NEXT: .cfi_undefined 1549 +; WAVE32-NEXT: .cfi_undefined 1550 +; WAVE32-NEXT: .cfi_undefined 1551 +; WAVE32-NEXT: .cfi_undefined 1552 +; WAVE32-NEXT: .cfi_undefined 1553 +; WAVE32-NEXT: .cfi_undefined 1554 +; WAVE32-NEXT: .cfi_undefined 1555 +; WAVE32-NEXT: .cfi_undefined 1556 +; WAVE32-NEXT: .cfi_undefined 1557 +; WAVE32-NEXT: .cfi_undefined 1558 +; WAVE32-NEXT: .cfi_undefined 1559 +; WAVE32-NEXT: .cfi_undefined 1560 +; WAVE32-NEXT: .cfi_undefined 1561 +; WAVE32-NEXT: .cfi_undefined 1562 +; WAVE32-NEXT: .cfi_undefined 1563 +; WAVE32-NEXT: .cfi_undefined 1564 +; WAVE32-NEXT: .cfi_undefined 1565 +; WAVE32-NEXT: .cfi_undefined 1566 +; WAVE32-NEXT: .cfi_undefined 1567 +; WAVE32-NEXT: .cfi_undefined 1568 +; WAVE32-NEXT: .cfi_undefined 1569 +; WAVE32-NEXT: .cfi_undefined 1570 +; WAVE32-NEXT: .cfi_undefined 1571 +; WAVE32-NEXT: .cfi_undefined 1572 +; WAVE32-NEXT: .cfi_undefined 1573 +; WAVE32-NEXT: .cfi_undefined 1574 +; WAVE32-NEXT: .cfi_undefined 1575 +; WAVE32-NEXT: .cfi_undefined 1584 +; WAVE32-NEXT: .cfi_undefined 1585 +; WAVE32-NEXT: .cfi_undefined 1586 +; WAVE32-NEXT: .cfi_undefined 1587 +; WAVE32-NEXT: .cfi_undefined 1588 +; WAVE32-NEXT: .cfi_undefined 1589 +; WAVE32-NEXT: .cfi_undefined 1590 +; WAVE32-NEXT: .cfi_undefined 1591 +; WAVE32-NEXT: .cfi_undefined 1600 +; WAVE32-NEXT: .cfi_undefined 1601 +; WAVE32-NEXT: .cfi_undefined 1602 +; WAVE32-NEXT: .cfi_undefined 1603 +; WAVE32-NEXT: .cfi_undefined 1604 +; WAVE32-NEXT: .cfi_undefined 1605 +; WAVE32-NEXT: .cfi_undefined 1606 +; WAVE32-NEXT: .cfi_undefined 1607 +; WAVE32-NEXT: .cfi_undefined 1616 +; WAVE32-NEXT: .cfi_undefined 1617 +; WAVE32-NEXT: .cfi_undefined 1618 +; WAVE32-NEXT: .cfi_undefined 1619 +; WAVE32-NEXT: .cfi_undefined 1620 +; WAVE32-NEXT: .cfi_undefined 1621 +; WAVE32-NEXT: .cfi_undefined 1622 +; WAVE32-NEXT: .cfi_undefined 1623 +; WAVE32-NEXT: .cfi_undefined 1632 +; WAVE32-NEXT: .cfi_undefined 1633 +; WAVE32-NEXT: .cfi_undefined 1634 +; WAVE32-NEXT: .cfi_undefined 1635 +; WAVE32-NEXT: .cfi_undefined 1636 +; WAVE32-NEXT: .cfi_undefined 1637 +; WAVE32-NEXT: .cfi_undefined 1638 +; WAVE32-NEXT: .cfi_undefined 1639 +; WAVE32-NEXT: .cfi_undefined 1648 +; WAVE32-NEXT: .cfi_undefined 1649 +; WAVE32-NEXT: .cfi_undefined 1650 +; WAVE32-NEXT: .cfi_undefined 1651 +; WAVE32-NEXT: .cfi_undefined 1652 +; WAVE32-NEXT: .cfi_undefined 1653 +; WAVE32-NEXT: .cfi_undefined 1654 +; WAVE32-NEXT: .cfi_undefined 1655 +; WAVE32-NEXT: .cfi_undefined 1664 +; WAVE32-NEXT: .cfi_undefined 1665 +; WAVE32-NEXT: .cfi_undefined 1666 +; WAVE32-NEXT: .cfi_undefined 1667 +; WAVE32-NEXT: .cfi_undefined 1668 +; WAVE32-NEXT: .cfi_undefined 1669 +; WAVE32-NEXT: .cfi_undefined 1670 +; WAVE32-NEXT: .cfi_undefined 1671 +; WAVE32-NEXT: .cfi_undefined 1680 +; WAVE32-NEXT: .cfi_undefined 1681 +; WAVE32-NEXT: .cfi_undefined 1682 +; WAVE32-NEXT: .cfi_undefined 1683 +; WAVE32-NEXT: .cfi_undefined 1684 +; WAVE32-NEXT: .cfi_undefined 1685 +; WAVE32-NEXT: .cfi_undefined 1686 +; WAVE32-NEXT: .cfi_undefined 1687 +; WAVE32-NEXT: .cfi_undefined 1696 +; WAVE32-NEXT: .cfi_undefined 1697 +; WAVE32-NEXT: .cfi_undefined 1698 +; WAVE32-NEXT: .cfi_undefined 1699 +; WAVE32-NEXT: .cfi_undefined 1700 +; WAVE32-NEXT: .cfi_undefined 1701 +; WAVE32-NEXT: .cfi_undefined 1702 +; WAVE32-NEXT: .cfi_undefined 1703 +; WAVE32-NEXT: .cfi_undefined 1712 +; WAVE32-NEXT: .cfi_undefined 1713 +; WAVE32-NEXT: .cfi_undefined 1714 +; WAVE32-NEXT: .cfi_undefined 1715 +; WAVE32-NEXT: .cfi_undefined 1716 +; WAVE32-NEXT: .cfi_undefined 1717 +; WAVE32-NEXT: .cfi_undefined 1718 +; WAVE32-NEXT: .cfi_undefined 1719 +; WAVE32-NEXT: .cfi_undefined 1728 +; WAVE32-NEXT: .cfi_undefined 1729 +; WAVE32-NEXT: .cfi_undefined 1730 +; WAVE32-NEXT: .cfi_undefined 1731 +; WAVE32-NEXT: .cfi_undefined 1732 +; WAVE32-NEXT: .cfi_undefined 1733 +; WAVE32-NEXT: .cfi_undefined 1734 +; WAVE32-NEXT: .cfi_undefined 1735 +; WAVE32-NEXT: .cfi_undefined 1744 +; WAVE32-NEXT: .cfi_undefined 1745 +; WAVE32-NEXT: .cfi_undefined 1746 +; WAVE32-NEXT: .cfi_undefined 1747 +; WAVE32-NEXT: .cfi_undefined 1748 +; WAVE32-NEXT: .cfi_undefined 1749 +; WAVE32-NEXT: .cfi_undefined 1750 +; WAVE32-NEXT: .cfi_undefined 1751 +; WAVE32-NEXT: .cfi_undefined 1760 +; WAVE32-NEXT: .cfi_undefined 1761 +; WAVE32-NEXT: .cfi_undefined 1762 +; WAVE32-NEXT: .cfi_undefined 1763 +; WAVE32-NEXT: .cfi_undefined 1764 +; WAVE32-NEXT: .cfi_undefined 1765 +; WAVE32-NEXT: .cfi_undefined 1766 +; WAVE32-NEXT: .cfi_undefined 1767 +; WAVE32-NEXT: .cfi_undefined 1776 +; WAVE32-NEXT: .cfi_undefined 1777 +; WAVE32-NEXT: .cfi_undefined 1778 +; WAVE32-NEXT: .cfi_undefined 1779 +; WAVE32-NEXT: .cfi_undefined 1780 +; WAVE32-NEXT: .cfi_undefined 1781 +; WAVE32-NEXT: .cfi_undefined 1782 +; WAVE32-NEXT: .cfi_undefined 1783 +; WAVE32-NEXT: .cfi_undefined 36 +; WAVE32-NEXT: .cfi_undefined 37 +; WAVE32-NEXT: .cfi_undefined 38 +; WAVE32-NEXT: .cfi_undefined 39 +; WAVE32-NEXT: .cfi_undefined 40 +; WAVE32-NEXT: .cfi_undefined 41 +; WAVE32-NEXT: .cfi_undefined 42 +; WAVE32-NEXT: .cfi_undefined 43 +; WAVE32-NEXT: .cfi_undefined 44 +; WAVE32-NEXT: .cfi_undefined 45 +; WAVE32-NEXT: .cfi_undefined 46 +; WAVE32-NEXT: .cfi_undefined 47 +; WAVE32-NEXT: .cfi_undefined 48 +; WAVE32-NEXT: .cfi_undefined 49 +; WAVE32-NEXT: .cfi_undefined 50 +; WAVE32-NEXT: .cfi_undefined 51 +; WAVE32-NEXT: .cfi_undefined 52 +; WAVE32-NEXT: .cfi_undefined 53 +; WAVE32-NEXT: .cfi_undefined 54 +; WAVE32-NEXT: .cfi_undefined 55 +; WAVE32-NEXT: .cfi_undefined 56 +; WAVE32-NEXT: .cfi_undefined 57 +; WAVE32-NEXT: .cfi_undefined 58 +; WAVE32-NEXT: .cfi_undefined 59 +; WAVE32-NEXT: .cfi_undefined 60 +; WAVE32-NEXT: .cfi_undefined 61 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: s_mov_b32 s40, s33 +; WAVE32-NEXT: .cfi_register 65, 72 +; WAVE32-NEXT: s_mov_b32 s33, s32 +; WAVE32-NEXT: .cfi_def_cfa_register 65 +; WAVE32-NEXT: s_addk_i32 s32, 0x3880 +; WAVE32-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1576, 32, 1, 32, 14208 +; WAVE32-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1577, 32, 1, 32, 14080 +; WAVE32-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1578, 32, 1, 32, 13952 +; WAVE32-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1579, 32, 1, 32, 13824 +; WAVE32-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1580, 32, 1, 32, 13696 +; WAVE32-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1581, 32, 1, 32, 13568 +; WAVE32-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1582, 32, 1, 32, 13440 +; WAVE32-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1583, 32, 1, 32, 13312 +; WAVE32-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1592, 32, 1, 32, 13184 +; WAVE32-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1593, 32, 1, 32, 13056 +; WAVE32-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1594, 32, 1, 32, 12928 +; WAVE32-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1595, 32, 1, 32, 12800 +; WAVE32-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1596, 32, 1, 32, 12672 +; WAVE32-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1597, 32, 1, 32, 12544 +; WAVE32-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1598, 32, 1, 32, 12416 +; WAVE32-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1599, 32, 1, 32, 12288 +; WAVE32-NEXT: buffer_store_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1608, 32, 1, 32, 12160 +; WAVE32-NEXT: buffer_store_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1609, 32, 1, 32, 12032 +; WAVE32-NEXT: buffer_store_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1610, 32, 1, 32, 11904 +; WAVE32-NEXT: buffer_store_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1611, 32, 1, 32, 11776 +; WAVE32-NEXT: buffer_store_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1612, 32, 1, 32, 11648 +; WAVE32-NEXT: buffer_store_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1613, 32, 1, 32, 11520 +; WAVE32-NEXT: buffer_store_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1614, 32, 1, 32, 11392 +; WAVE32-NEXT: buffer_store_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1615, 32, 1, 32, 11264 +; WAVE32-NEXT: buffer_store_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1624, 32, 1, 32, 11136 +; WAVE32-NEXT: buffer_store_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1625, 32, 1, 32, 11008 +; WAVE32-NEXT: buffer_store_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1626, 32, 1, 32, 10880 +; WAVE32-NEXT: buffer_store_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1627, 32, 1, 32, 10752 +; WAVE32-NEXT: buffer_store_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1628, 32, 1, 32, 10624 +; WAVE32-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1629, 32, 1, 32, 10496 +; WAVE32-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1630, 32, 1, 32, 10368 +; WAVE32-NEXT: buffer_store_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1631, 32, 1, 32, 10240 +; WAVE32-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1640, 32, 1, 32, 10112 +; WAVE32-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1641, 32, 1, 32, 9984 +; WAVE32-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1642, 32, 1, 32, 9856 +; WAVE32-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1643, 32, 1, 32, 9728 +; WAVE32-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1644, 32, 1, 32, 9600 +; WAVE32-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1645, 32, 1, 32, 9472 +; WAVE32-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1646, 32, 1, 32, 9344 +; WAVE32-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1647, 32, 1, 32, 9216 +; WAVE32-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1656, 32, 1, 32, 9088 +; WAVE32-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1657, 32, 1, 32, 8960 +; WAVE32-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1658, 32, 1, 32, 8832 +; WAVE32-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1659, 32, 1, 32, 8704 +; WAVE32-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1660, 32, 1, 32, 8576 +; WAVE32-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1661, 32, 1, 32, 8448 +; WAVE32-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1662, 32, 1, 32, 8320 +; WAVE32-NEXT: buffer_store_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1663, 32, 1, 32, 8192 +; WAVE32-NEXT: buffer_store_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1672, 32, 1, 32, 8064 +; WAVE32-NEXT: buffer_store_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1673, 32, 1, 32, 7936 +; WAVE32-NEXT: buffer_store_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1674, 32, 1, 32, 7808 +; WAVE32-NEXT: buffer_store_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1675, 32, 1, 32, 7680 +; WAVE32-NEXT: buffer_store_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1676, 32, 1, 32, 7552 +; WAVE32-NEXT: buffer_store_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1677, 32, 1, 32, 7424 +; WAVE32-NEXT: buffer_store_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1678, 32, 1, 32, 7296 +; WAVE32-NEXT: buffer_store_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1679, 32, 1, 32, 7168 +; WAVE32-NEXT: buffer_store_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1688, 32, 1, 32, 7040 +; WAVE32-NEXT: buffer_store_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1689, 32, 1, 32, 6912 +; WAVE32-NEXT: buffer_store_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1690, 32, 1, 32, 6784 +; WAVE32-NEXT: buffer_store_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1691, 32, 1, 32, 6656 +; WAVE32-NEXT: buffer_store_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1692, 32, 1, 32, 6528 +; WAVE32-NEXT: buffer_store_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1693, 32, 1, 32, 6400 +; WAVE32-NEXT: buffer_store_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1694, 32, 1, 32, 6272 +; WAVE32-NEXT: buffer_store_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1695, 32, 1, 32, 6144 +; WAVE32-NEXT: buffer_store_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1704, 32, 1, 32, 6016 +; WAVE32-NEXT: buffer_store_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1705, 32, 1, 32, 5888 +; WAVE32-NEXT: buffer_store_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1706, 32, 1, 32, 5760 +; WAVE32-NEXT: buffer_store_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1707, 32, 1, 32, 5632 +; WAVE32-NEXT: buffer_store_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1708, 32, 1, 32, 5504 +; WAVE32-NEXT: buffer_store_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1709, 32, 1, 32, 5376 +; WAVE32-NEXT: buffer_store_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1710, 32, 1, 32, 5248 +; WAVE32-NEXT: buffer_store_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1711, 32, 1, 32, 5120 +; WAVE32-NEXT: buffer_store_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1720, 32, 1, 32, 4992 +; WAVE32-NEXT: buffer_store_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1721, 32, 1, 32, 4864 +; WAVE32-NEXT: buffer_store_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1722, 32, 1, 32, 4736 +; WAVE32-NEXT: buffer_store_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1723, 32, 1, 32, 4608 +; WAVE32-NEXT: buffer_store_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1724, 32, 1, 32, 4480 +; WAVE32-NEXT: buffer_store_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1725, 32, 1, 32, 4352 +; WAVE32-NEXT: buffer_store_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1726, 32, 1, 32, 4224 +; WAVE32-NEXT: buffer_store_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1727, 32, 1, 32, 4096 +; WAVE32-NEXT: buffer_store_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1736, 32, 1, 32, 3968 +; WAVE32-NEXT: buffer_store_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1737, 32, 1, 32, 3840 +; WAVE32-NEXT: buffer_store_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1738, 32, 1, 32, 3712 +; WAVE32-NEXT: buffer_store_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1739, 32, 1, 32, 3584 +; WAVE32-NEXT: buffer_store_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1740, 32, 1, 32, 3456 +; WAVE32-NEXT: buffer_store_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1741, 32, 1, 32, 3328 +; WAVE32-NEXT: buffer_store_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1742, 32, 1, 32, 3200 +; WAVE32-NEXT: buffer_store_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1743, 32, 1, 32, 3072 +; WAVE32-NEXT: buffer_store_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1752, 32, 1, 32, 2944 +; WAVE32-NEXT: buffer_store_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1753, 32, 1, 32, 2816 +; WAVE32-NEXT: buffer_store_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1754, 32, 1, 32, 2688 +; WAVE32-NEXT: buffer_store_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1755, 32, 1, 32, 2560 +; WAVE32-NEXT: buffer_store_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1756, 32, 1, 32, 2432 +; WAVE32-NEXT: buffer_store_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1757, 32, 1, 32, 2304 +; WAVE32-NEXT: buffer_store_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1758, 32, 1, 32, 2176 +; WAVE32-NEXT: buffer_store_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1759, 32, 1, 32, 2048 +; WAVE32-NEXT: buffer_store_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1768, 32, 1, 32, 1920 +; WAVE32-NEXT: buffer_store_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1769, 32, 1, 32, 1792 +; WAVE32-NEXT: buffer_store_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1770, 32, 1, 32, 1664 +; WAVE32-NEXT: buffer_store_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1771, 32, 1, 32, 1536 +; WAVE32-NEXT: buffer_store_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1772, 32, 1, 32, 1408 +; WAVE32-NEXT: buffer_store_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1773, 32, 1, 32, 1280 +; WAVE32-NEXT: buffer_store_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1774, 32, 1, 32, 1152 +; WAVE32-NEXT: buffer_store_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1775, 32, 1, 32, 1024 +; WAVE32-NEXT: buffer_store_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1784, 32, 1, 32, 896 +; WAVE32-NEXT: buffer_store_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1785, 32, 1, 32, 768 +; WAVE32-NEXT: buffer_store_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1786, 32, 1, 32, 640 +; WAVE32-NEXT: buffer_store_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1787, 32, 1, 32, 512 +; WAVE32-NEXT: buffer_store_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1788, 32, 1, 32, 384 +; WAVE32-NEXT: buffer_store_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1789, 32, 1, 32, 256 +; WAVE32-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1790, 32, 1, 32, 128 +; WAVE32-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1791, 32, 1, 32, 0 +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber nonpreserved SGPRs +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber all VGPRs +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: s_clause 0x3e +; WAVE32-NEXT: buffer_load_dword v255, off, s[0:3], s33 +; WAVE32-NEXT: buffer_load_dword v254, off, s[0:3], s33 offset:4 +; WAVE32-NEXT: buffer_load_dword v253, off, s[0:3], s33 offset:8 +; WAVE32-NEXT: buffer_load_dword v252, off, s[0:3], s33 offset:12 +; WAVE32-NEXT: buffer_load_dword v251, off, s[0:3], s33 offset:16 +; WAVE32-NEXT: buffer_load_dword v250, off, s[0:3], s33 offset:20 +; WAVE32-NEXT: buffer_load_dword v249, off, s[0:3], s33 offset:24 +; WAVE32-NEXT: buffer_load_dword v248, off, s[0:3], s33 offset:28 +; WAVE32-NEXT: buffer_load_dword v239, off, s[0:3], s33 offset:32 +; WAVE32-NEXT: buffer_load_dword v238, off, s[0:3], s33 offset:36 +; WAVE32-NEXT: buffer_load_dword v237, off, s[0:3], s33 offset:40 +; WAVE32-NEXT: buffer_load_dword v236, off, s[0:3], s33 offset:44 +; WAVE32-NEXT: buffer_load_dword v235, off, s[0:3], s33 offset:48 +; WAVE32-NEXT: buffer_load_dword v234, off, s[0:3], s33 offset:52 +; WAVE32-NEXT: buffer_load_dword v233, off, s[0:3], s33 offset:56 +; WAVE32-NEXT: buffer_load_dword v232, off, s[0:3], s33 offset:60 +; WAVE32-NEXT: buffer_load_dword v223, off, s[0:3], s33 offset:64 +; WAVE32-NEXT: buffer_load_dword v222, off, s[0:3], s33 offset:68 +; WAVE32-NEXT: buffer_load_dword v221, off, s[0:3], s33 offset:72 +; WAVE32-NEXT: buffer_load_dword v220, off, s[0:3], s33 offset:76 +; WAVE32-NEXT: buffer_load_dword v219, off, s[0:3], s33 offset:80 +; WAVE32-NEXT: buffer_load_dword v218, off, s[0:3], s33 offset:84 +; WAVE32-NEXT: buffer_load_dword v217, off, s[0:3], s33 offset:88 +; WAVE32-NEXT: buffer_load_dword v216, off, s[0:3], s33 offset:92 +; WAVE32-NEXT: buffer_load_dword v207, off, s[0:3], s33 offset:96 +; WAVE32-NEXT: buffer_load_dword v206, off, s[0:3], s33 offset:100 +; WAVE32-NEXT: buffer_load_dword v205, off, s[0:3], s33 offset:104 +; WAVE32-NEXT: buffer_load_dword v204, off, s[0:3], s33 offset:108 +; WAVE32-NEXT: buffer_load_dword v203, off, s[0:3], s33 offset:112 +; WAVE32-NEXT: buffer_load_dword v202, off, s[0:3], s33 offset:116 +; WAVE32-NEXT: buffer_load_dword v201, off, s[0:3], s33 offset:120 +; WAVE32-NEXT: buffer_load_dword v200, off, s[0:3], s33 offset:124 +; WAVE32-NEXT: buffer_load_dword v191, off, s[0:3], s33 offset:128 +; WAVE32-NEXT: buffer_load_dword v190, off, s[0:3], s33 offset:132 +; WAVE32-NEXT: buffer_load_dword v189, off, s[0:3], s33 offset:136 +; WAVE32-NEXT: buffer_load_dword v188, off, s[0:3], s33 offset:140 +; WAVE32-NEXT: buffer_load_dword v187, off, s[0:3], s33 offset:144 +; WAVE32-NEXT: buffer_load_dword v186, off, s[0:3], s33 offset:148 +; WAVE32-NEXT: buffer_load_dword v185, off, s[0:3], s33 offset:152 +; WAVE32-NEXT: buffer_load_dword v184, off, s[0:3], s33 offset:156 +; WAVE32-NEXT: buffer_load_dword v175, off, s[0:3], s33 offset:160 +; WAVE32-NEXT: buffer_load_dword v174, off, s[0:3], s33 offset:164 +; WAVE32-NEXT: buffer_load_dword v173, off, s[0:3], s33 offset:168 +; WAVE32-NEXT: buffer_load_dword v172, off, s[0:3], s33 offset:172 +; WAVE32-NEXT: buffer_load_dword v171, off, s[0:3], s33 offset:176 +; WAVE32-NEXT: buffer_load_dword v170, off, s[0:3], s33 offset:180 +; WAVE32-NEXT: buffer_load_dword v169, off, s[0:3], s33 offset:184 +; WAVE32-NEXT: buffer_load_dword v168, off, s[0:3], s33 offset:188 +; WAVE32-NEXT: buffer_load_dword v159, off, s[0:3], s33 offset:192 +; WAVE32-NEXT: buffer_load_dword v158, off, s[0:3], s33 offset:196 +; WAVE32-NEXT: buffer_load_dword v157, off, s[0:3], s33 offset:200 +; WAVE32-NEXT: buffer_load_dword v156, off, s[0:3], s33 offset:204 +; WAVE32-NEXT: buffer_load_dword v155, off, s[0:3], s33 offset:208 +; WAVE32-NEXT: buffer_load_dword v154, off, s[0:3], s33 offset:212 +; WAVE32-NEXT: buffer_load_dword v153, off, s[0:3], s33 offset:216 +; WAVE32-NEXT: buffer_load_dword v152, off, s[0:3], s33 offset:220 +; WAVE32-NEXT: buffer_load_dword v143, off, s[0:3], s33 offset:224 +; WAVE32-NEXT: buffer_load_dword v142, off, s[0:3], s33 offset:228 +; WAVE32-NEXT: buffer_load_dword v141, off, s[0:3], s33 offset:232 +; WAVE32-NEXT: buffer_load_dword v140, off, s[0:3], s33 offset:236 +; WAVE32-NEXT: buffer_load_dword v139, off, s[0:3], s33 offset:240 +; WAVE32-NEXT: buffer_load_dword v138, off, s[0:3], s33 offset:244 +; WAVE32-NEXT: buffer_load_dword v137, off, s[0:3], s33 offset:248 +; WAVE32-NEXT: s_clause 0x30 +; WAVE32-NEXT: buffer_load_dword v136, off, s[0:3], s33 offset:252 +; WAVE32-NEXT: buffer_load_dword v127, off, s[0:3], s33 offset:256 +; WAVE32-NEXT: buffer_load_dword v126, off, s[0:3], s33 offset:260 +; WAVE32-NEXT: buffer_load_dword v125, off, s[0:3], s33 offset:264 +; WAVE32-NEXT: buffer_load_dword v124, off, s[0:3], s33 offset:268 +; WAVE32-NEXT: buffer_load_dword v123, off, s[0:3], s33 offset:272 +; WAVE32-NEXT: buffer_load_dword v122, off, s[0:3], s33 offset:276 +; WAVE32-NEXT: buffer_load_dword v121, off, s[0:3], s33 offset:280 +; WAVE32-NEXT: buffer_load_dword v120, off, s[0:3], s33 offset:284 +; WAVE32-NEXT: buffer_load_dword v111, off, s[0:3], s33 offset:288 +; WAVE32-NEXT: buffer_load_dword v110, off, s[0:3], s33 offset:292 +; WAVE32-NEXT: buffer_load_dword v109, off, s[0:3], s33 offset:296 +; WAVE32-NEXT: buffer_load_dword v108, off, s[0:3], s33 offset:300 +; WAVE32-NEXT: buffer_load_dword v107, off, s[0:3], s33 offset:304 +; WAVE32-NEXT: buffer_load_dword v106, off, s[0:3], s33 offset:308 +; WAVE32-NEXT: buffer_load_dword v105, off, s[0:3], s33 offset:312 +; WAVE32-NEXT: buffer_load_dword v104, off, s[0:3], s33 offset:316 +; WAVE32-NEXT: buffer_load_dword v95, off, s[0:3], s33 offset:320 +; WAVE32-NEXT: buffer_load_dword v94, off, s[0:3], s33 offset:324 +; WAVE32-NEXT: buffer_load_dword v93, off, s[0:3], s33 offset:328 +; WAVE32-NEXT: buffer_load_dword v92, off, s[0:3], s33 offset:332 +; WAVE32-NEXT: buffer_load_dword v91, off, s[0:3], s33 offset:336 +; WAVE32-NEXT: buffer_load_dword v90, off, s[0:3], s33 offset:340 +; WAVE32-NEXT: buffer_load_dword v89, off, s[0:3], s33 offset:344 +; WAVE32-NEXT: buffer_load_dword v88, off, s[0:3], s33 offset:348 +; WAVE32-NEXT: buffer_load_dword v79, off, s[0:3], s33 offset:352 +; WAVE32-NEXT: buffer_load_dword v78, off, s[0:3], s33 offset:356 +; WAVE32-NEXT: buffer_load_dword v77, off, s[0:3], s33 offset:360 +; WAVE32-NEXT: buffer_load_dword v76, off, s[0:3], s33 offset:364 +; WAVE32-NEXT: buffer_load_dword v75, off, s[0:3], s33 offset:368 +; WAVE32-NEXT: buffer_load_dword v74, off, s[0:3], s33 offset:372 +; WAVE32-NEXT: buffer_load_dword v73, off, s[0:3], s33 offset:376 +; WAVE32-NEXT: buffer_load_dword v72, off, s[0:3], s33 offset:380 +; WAVE32-NEXT: buffer_load_dword v63, off, s[0:3], s33 offset:384 +; WAVE32-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:388 +; WAVE32-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:392 +; WAVE32-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:396 +; WAVE32-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:400 +; WAVE32-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:404 +; WAVE32-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:408 +; WAVE32-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:412 +; WAVE32-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:416 +; WAVE32-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:420 +; WAVE32-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:424 +; WAVE32-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:428 +; WAVE32-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:432 +; WAVE32-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:436 +; WAVE32-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:440 +; WAVE32-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:444 +; WAVE32-NEXT: s_mov_b32 s32, s33 +; WAVE32-NEXT: .cfi_def_cfa_register 64 +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 s33, s40 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_setpc_b64 s[30:31] + call void asm sideeffect "; clobber nonpreserved SGPRs", + "~{s4},~{s5},~{s6},~{s7},~{s8},~{s9} + ,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19} + ,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29} + ,~{vcc}"() + + call void asm sideeffect "; clobber all VGPRs", + "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9} + ,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19} + ,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29} + ,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38},~{v39} + ,~{v40},~{v41},~{v42},~{v43},~{v44},~{v45},~{v46},~{v47},~{v48},~{v49} + ,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59} + ,~{v60},~{v61},~{v62},~{v63},~{v64},~{v65},~{v66},~{v67},~{v68},~{v69} + ,~{v70},~{v71},~{v72},~{v73},~{v74},~{v75},~{v76},~{v77},~{v78},~{v79} + ,~{v80},~{v81},~{v82},~{v83},~{v84},~{v85},~{v86},~{v87},~{v88},~{v89} + ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} + ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109} + ,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119} + ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129} + ,~{v130},~{v131},~{v132},~{v133},~{v134},~{v135},~{v136},~{v137},~{v138},~{v139} + ,~{v140},~{v141},~{v142},~{v143},~{v144},~{v145},~{v146},~{v147},~{v148},~{v149} + ,~{v150},~{v151},~{v152},~{v153},~{v154},~{v155},~{v156},~{v157},~{v158},~{v159} + ,~{v160},~{v161},~{v162},~{v163},~{v164},~{v165},~{v166},~{v167},~{v168},~{v169} + ,~{v170},~{v171},~{v172},~{v173},~{v174},~{v175},~{v176},~{v177},~{v178},~{v179} + ,~{v180},~{v181},~{v182},~{v183},~{v184},~{v185},~{v186},~{v187},~{v188},~{v189} + ,~{v190},~{v191},~{v192},~{v193},~{v194},~{v195},~{v196},~{v197},~{v198},~{v199} + ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209} + ,~{v210},~{v211},~{v212},~{v213},~{v214},~{v215},~{v216},~{v217},~{v218},~{v219} + ,~{v220},~{v221},~{v222},~{v223},~{v224},~{v225},~{v226},~{v227},~{v228},~{v229} + ,~{v230},~{v231},~{v232},~{v233},~{v234},~{v235},~{v236},~{v237},~{v238},~{v239} + ,~{v240},~{v241},~{v242},~{v243},~{v244},~{v245},~{v246},~{v247},~{v248},~{v249} + ,~{v250},~{v251},~{v252},~{v253},~{v254},~{v255}"() + ret void +} + +declare hidden void @ex() #0 + +define hidden void @func_call_clobber() #0 { +; GFX900-LABEL: func_call_clobber: +; GFX900: .Lfunc_begin3: +; GFX900-NEXT: .cfi_startproc +; GFX900-NEXT: ; %bb.0: ; %entry +; GFX900-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX900-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX900-NEXT: .cfi_undefined 2560 +; GFX900-NEXT: .cfi_undefined 2561 +; GFX900-NEXT: .cfi_undefined 2562 +; GFX900-NEXT: .cfi_undefined 2563 +; GFX900-NEXT: .cfi_undefined 2564 +; GFX900-NEXT: .cfi_undefined 2565 +; GFX900-NEXT: .cfi_undefined 2566 +; GFX900-NEXT: .cfi_undefined 2567 +; GFX900-NEXT: .cfi_undefined 2568 +; GFX900-NEXT: .cfi_undefined 2569 +; GFX900-NEXT: .cfi_undefined 2570 +; GFX900-NEXT: .cfi_undefined 2571 +; GFX900-NEXT: .cfi_undefined 2572 +; GFX900-NEXT: .cfi_undefined 2573 +; GFX900-NEXT: .cfi_undefined 2574 +; GFX900-NEXT: .cfi_undefined 2575 +; GFX900-NEXT: .cfi_undefined 2576 +; GFX900-NEXT: .cfi_undefined 2577 +; GFX900-NEXT: .cfi_undefined 2578 +; GFX900-NEXT: .cfi_undefined 2579 +; GFX900-NEXT: .cfi_undefined 2580 +; GFX900-NEXT: .cfi_undefined 2581 +; GFX900-NEXT: .cfi_undefined 2582 +; GFX900-NEXT: .cfi_undefined 2583 +; GFX900-NEXT: .cfi_undefined 2584 +; GFX900-NEXT: .cfi_undefined 2585 +; GFX900-NEXT: .cfi_undefined 2586 +; GFX900-NEXT: .cfi_undefined 2587 +; GFX900-NEXT: .cfi_undefined 2588 +; GFX900-NEXT: .cfi_undefined 2589 +; GFX900-NEXT: .cfi_undefined 2590 +; GFX900-NEXT: .cfi_undefined 2591 +; GFX900-NEXT: .cfi_undefined 2592 +; GFX900-NEXT: .cfi_undefined 2593 +; GFX900-NEXT: .cfi_undefined 2594 +; GFX900-NEXT: .cfi_undefined 2595 +; GFX900-NEXT: .cfi_undefined 2596 +; GFX900-NEXT: .cfi_undefined 2597 +; GFX900-NEXT: .cfi_undefined 2598 +; GFX900-NEXT: .cfi_undefined 2599 +; GFX900-NEXT: .cfi_undefined 2608 +; GFX900-NEXT: .cfi_undefined 2609 +; GFX900-NEXT: .cfi_undefined 2610 +; GFX900-NEXT: .cfi_undefined 2611 +; GFX900-NEXT: .cfi_undefined 2612 +; GFX900-NEXT: .cfi_undefined 2613 +; GFX900-NEXT: .cfi_undefined 2614 +; GFX900-NEXT: .cfi_undefined 2615 +; GFX900-NEXT: .cfi_undefined 2624 +; GFX900-NEXT: .cfi_undefined 2625 +; GFX900-NEXT: .cfi_undefined 2626 +; GFX900-NEXT: .cfi_undefined 2627 +; GFX900-NEXT: .cfi_undefined 2628 +; GFX900-NEXT: .cfi_undefined 2629 +; GFX900-NEXT: .cfi_undefined 2630 +; GFX900-NEXT: .cfi_undefined 2631 +; GFX900-NEXT: .cfi_undefined 2640 +; GFX900-NEXT: .cfi_undefined 2641 +; GFX900-NEXT: .cfi_undefined 2642 +; GFX900-NEXT: .cfi_undefined 2643 +; GFX900-NEXT: .cfi_undefined 2644 +; GFX900-NEXT: .cfi_undefined 2645 +; GFX900-NEXT: .cfi_undefined 2646 +; GFX900-NEXT: .cfi_undefined 2647 +; GFX900-NEXT: .cfi_undefined 2656 +; GFX900-NEXT: .cfi_undefined 2657 +; GFX900-NEXT: .cfi_undefined 2658 +; GFX900-NEXT: .cfi_undefined 2659 +; GFX900-NEXT: .cfi_undefined 2660 +; GFX900-NEXT: .cfi_undefined 2661 +; GFX900-NEXT: .cfi_undefined 2662 +; GFX900-NEXT: .cfi_undefined 2663 +; GFX900-NEXT: .cfi_undefined 2672 +; GFX900-NEXT: .cfi_undefined 2673 +; GFX900-NEXT: .cfi_undefined 2674 +; GFX900-NEXT: .cfi_undefined 2675 +; GFX900-NEXT: .cfi_undefined 2676 +; GFX900-NEXT: .cfi_undefined 2677 +; GFX900-NEXT: .cfi_undefined 2678 +; GFX900-NEXT: .cfi_undefined 2679 +; GFX900-NEXT: .cfi_undefined 2688 +; GFX900-NEXT: .cfi_undefined 2689 +; GFX900-NEXT: .cfi_undefined 2690 +; GFX900-NEXT: .cfi_undefined 2691 +; GFX900-NEXT: .cfi_undefined 2692 +; GFX900-NEXT: .cfi_undefined 2693 +; GFX900-NEXT: .cfi_undefined 2694 +; GFX900-NEXT: .cfi_undefined 2695 +; GFX900-NEXT: .cfi_undefined 2704 +; GFX900-NEXT: .cfi_undefined 2705 +; GFX900-NEXT: .cfi_undefined 2706 +; GFX900-NEXT: .cfi_undefined 2707 +; GFX900-NEXT: .cfi_undefined 2708 +; GFX900-NEXT: .cfi_undefined 2709 +; GFX900-NEXT: .cfi_undefined 2710 +; GFX900-NEXT: .cfi_undefined 2711 +; GFX900-NEXT: .cfi_undefined 2720 +; GFX900-NEXT: .cfi_undefined 2721 +; GFX900-NEXT: .cfi_undefined 2722 +; GFX900-NEXT: .cfi_undefined 2723 +; GFX900-NEXT: .cfi_undefined 2724 +; GFX900-NEXT: .cfi_undefined 2725 +; GFX900-NEXT: .cfi_undefined 2726 +; GFX900-NEXT: .cfi_undefined 2727 +; GFX900-NEXT: .cfi_undefined 2736 +; GFX900-NEXT: .cfi_undefined 2737 +; GFX900-NEXT: .cfi_undefined 2738 +; GFX900-NEXT: .cfi_undefined 2739 +; GFX900-NEXT: .cfi_undefined 2740 +; GFX900-NEXT: .cfi_undefined 2741 +; GFX900-NEXT: .cfi_undefined 2742 +; GFX900-NEXT: .cfi_undefined 2743 +; GFX900-NEXT: .cfi_undefined 2752 +; GFX900-NEXT: .cfi_undefined 2753 +; GFX900-NEXT: .cfi_undefined 2754 +; GFX900-NEXT: .cfi_undefined 2755 +; GFX900-NEXT: .cfi_undefined 2756 +; GFX900-NEXT: .cfi_undefined 2757 +; GFX900-NEXT: .cfi_undefined 2758 +; GFX900-NEXT: .cfi_undefined 2759 +; GFX900-NEXT: .cfi_undefined 2768 +; GFX900-NEXT: .cfi_undefined 2769 +; GFX900-NEXT: .cfi_undefined 2770 +; GFX900-NEXT: .cfi_undefined 2771 +; GFX900-NEXT: .cfi_undefined 2772 +; GFX900-NEXT: .cfi_undefined 2773 +; GFX900-NEXT: .cfi_undefined 2774 +; GFX900-NEXT: .cfi_undefined 2775 +; GFX900-NEXT: .cfi_undefined 2784 +; GFX900-NEXT: .cfi_undefined 2785 +; GFX900-NEXT: .cfi_undefined 2786 +; GFX900-NEXT: .cfi_undefined 2787 +; GFX900-NEXT: .cfi_undefined 2788 +; GFX900-NEXT: .cfi_undefined 2789 +; GFX900-NEXT: .cfi_undefined 2790 +; GFX900-NEXT: .cfi_undefined 2791 +; GFX900-NEXT: .cfi_undefined 2800 +; GFX900-NEXT: .cfi_undefined 2801 +; GFX900-NEXT: .cfi_undefined 2802 +; GFX900-NEXT: .cfi_undefined 2803 +; GFX900-NEXT: .cfi_undefined 2804 +; GFX900-NEXT: .cfi_undefined 2805 +; GFX900-NEXT: .cfi_undefined 2806 +; GFX900-NEXT: .cfi_undefined 2807 +; GFX900-NEXT: .cfi_undefined 2816 +; GFX900-NEXT: .cfi_undefined 2817 +; GFX900-NEXT: .cfi_undefined 2818 +; GFX900-NEXT: .cfi_undefined 2819 +; GFX900-NEXT: .cfi_undefined 2820 +; GFX900-NEXT: .cfi_undefined 2821 +; GFX900-NEXT: .cfi_undefined 2822 +; GFX900-NEXT: .cfi_undefined 2823 +; GFX900-NEXT: .cfi_undefined 2824 +; GFX900-NEXT: .cfi_undefined 2825 +; GFX900-NEXT: .cfi_undefined 2826 +; GFX900-NEXT: .cfi_undefined 2827 +; GFX900-NEXT: .cfi_undefined 2828 +; GFX900-NEXT: .cfi_undefined 2829 +; GFX900-NEXT: .cfi_undefined 2830 +; GFX900-NEXT: .cfi_undefined 2831 +; GFX900-NEXT: .cfi_undefined 2832 +; GFX900-NEXT: .cfi_undefined 2833 +; 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GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 4294967295 +; GFX900-NEXT: .cfi_undefined 32 +; GFX900-NEXT: .cfi_undefined 33 +; GFX900-NEXT: .cfi_undefined 34 +; GFX900-NEXT: .cfi_undefined 35 +; GFX900-NEXT: .cfi_undefined 36 +; GFX900-NEXT: .cfi_undefined 37 +; GFX900-NEXT: .cfi_undefined 38 +; GFX900-NEXT: .cfi_undefined 39 +; GFX900-NEXT: .cfi_undefined 40 +; GFX900-NEXT: .cfi_undefined 41 +; GFX900-NEXT: .cfi_undefined 42 +; GFX900-NEXT: .cfi_undefined 43 +; GFX900-NEXT: .cfi_undefined 44 +; GFX900-NEXT: .cfi_undefined 45 +; GFX900-NEXT: .cfi_undefined 46 +; GFX900-NEXT: .cfi_undefined 47 +; GFX900-NEXT: .cfi_undefined 48 +; GFX900-NEXT: .cfi_undefined 49 +; GFX900-NEXT: .cfi_undefined 50 +; GFX900-NEXT: .cfi_undefined 51 +; GFX900-NEXT: .cfi_undefined 52 +; GFX900-NEXT: .cfi_undefined 53 +; GFX900-NEXT: .cfi_undefined 54 +; GFX900-NEXT: .cfi_undefined 55 +; GFX900-NEXT: .cfi_undefined 56 +; GFX900-NEXT: .cfi_undefined 57 +; GFX900-NEXT: .cfi_undefined 58 +; GFX900-NEXT: .cfi_undefined 59 +; GFX900-NEXT: .cfi_undefined 60 +; GFX900-NEXT: .cfi_undefined 61 +; GFX900-NEXT: .cfi_undefined 72 +; GFX900-NEXT: .cfi_undefined 73 +; GFX900-NEXT: .cfi_undefined 74 +; GFX900-NEXT: .cfi_undefined 75 +; GFX900-NEXT: .cfi_undefined 76 +; GFX900-NEXT: .cfi_undefined 77 +; GFX900-NEXT: .cfi_undefined 78 +; GFX900-NEXT: .cfi_undefined 79 +; GFX900-NEXT: .cfi_undefined 88 +; GFX900-NEXT: .cfi_undefined 89 +; GFX900-NEXT: .cfi_undefined 90 +; GFX900-NEXT: .cfi_undefined 91 +; GFX900-NEXT: .cfi_undefined 92 +; GFX900-NEXT: .cfi_undefined 93 +; GFX900-NEXT: .cfi_undefined 94 +; GFX900-NEXT: .cfi_undefined 95 +; GFX900-NEXT: .cfi_undefined 1096 +; GFX900-NEXT: .cfi_undefined 1097 +; GFX900-NEXT: .cfi_undefined 1098 +; GFX900-NEXT: .cfi_undefined 1099 +; GFX900-NEXT: .cfi_undefined 1100 +; GFX900-NEXT: .cfi_undefined 1101 +; GFX900-NEXT: .cfi_undefined 1102 +; GFX900-NEXT: .cfi_undefined 1103 +; GFX900-NEXT: .cfi_undefined 1112 +; GFX900-NEXT: .cfi_undefined 1113 +; GFX900-NEXT: .cfi_undefined 1114 +; GFX900-NEXT: .cfi_undefined 1115 +; GFX900-NEXT: .cfi_undefined 1116 +; GFX900-NEXT: .cfi_undefined 1117 +; GFX900-NEXT: .cfi_undefined 1118 +; GFX900-NEXT: .cfi_undefined 1119 +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: s_mov_b32 s16, s33 +; GFX900-NEXT: s_mov_b32 s33, s32 +; GFX900-NEXT: s_or_saveexec_b64 s[18:19], -1 +; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_offset 2600, 0 +; GFX900-NEXT: s_mov_b64 exec, s[18:19] +; GFX900-NEXT: v_writelane_b32 v40, s16, 2 +; GFX900-NEXT: .cfi_llvm_vector_registers 65, 2600, 2, 32 +; GFX900-NEXT: .cfi_def_cfa_register 65 +; GFX900-NEXT: v_writelane_b32 v40, s30, 0 +; GFX900-NEXT: s_addk_i32 s32, 0x400 +; GFX900-NEXT: v_writelane_b32 v40, s31, 1 +; GFX900-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32 +; GFX900-NEXT: s_getpc_b64 s[16:17] +; GFX900-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4 +; GFX900-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12 +; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX900-NEXT: v_readlane_b32 s30, v40, 0 +; GFX900-NEXT: v_readlane_b32 s31, v40, 1 +; GFX900-NEXT: s_mov_b32 s32, s33 +; GFX900-NEXT: v_readlane_b32 s4, v40, 2 +; GFX900-NEXT: s_or_saveexec_b64 s[6:7], -1 +; GFX900-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload +; GFX900-NEXT: s_mov_b64 exec, s[6:7] +; GFX900-NEXT: .cfi_def_cfa_register 64 +; GFX900-NEXT: s_mov_b32 s33, s4 +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-V2A-DIS-LABEL: func_call_clobber: +; GFX90A-V2A-DIS: .Lfunc_begin3: +; GFX90A-V2A-DIS-NEXT: .cfi_startproc +; GFX90A-V2A-DIS-NEXT: ; %bb.0: ; %entry +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2560 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2561 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2562 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2563 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2564 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2565 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2566 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2567 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2568 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2569 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2570 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2571 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2572 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2573 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2574 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2575 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2576 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2577 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2578 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2579 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2580 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2581 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2582 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2583 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2584 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2585 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2586 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2587 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2588 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2589 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2590 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2591 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2592 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2593 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2594 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2595 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2596 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2597 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2598 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2599 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2608 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2609 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2610 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2611 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2612 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2613 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2614 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2615 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2624 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2625 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2626 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2627 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2628 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2629 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2630 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2631 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2640 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2641 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2642 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2643 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2644 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2645 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2646 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2647 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2656 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2657 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2658 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2659 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2660 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2661 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2662 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2663 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2672 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2673 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2674 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2675 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2676 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2677 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2678 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2679 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2688 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2689 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2690 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2691 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2692 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2693 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2694 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2695 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2704 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2705 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2706 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2707 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2708 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2709 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2710 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2711 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2720 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2721 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2722 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2723 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2724 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2725 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2726 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2727 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2736 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2737 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2738 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2739 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2740 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2741 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2742 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2743 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2752 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2753 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2754 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2755 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2756 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2757 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2758 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2759 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2768 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2769 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2770 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2771 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2772 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2773 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2774 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2775 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2784 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2785 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2786 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2787 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2788 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2789 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2790 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2791 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2800 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2801 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2802 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2803 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2804 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2805 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2806 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2807 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2816 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2817 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2818 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2819 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2820 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2821 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2822 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2823 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2824 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2825 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2826 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2827 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2828 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2829 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2830 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2831 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2832 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2833 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2834 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2835 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2836 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2837 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2838 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2839 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2840 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2841 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2842 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2843 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2844 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2845 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2846 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2847 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2848 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2849 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2850 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2851 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2852 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2853 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2854 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2855 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2856 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2857 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2858 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2859 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2860 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2861 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2862 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2863 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2864 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2865 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2866 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2867 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2868 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2869 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2870 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2871 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2872 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2873 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2874 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2875 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2876 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2877 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2878 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2879 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2880 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2881 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2882 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2883 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2884 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2885 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2886 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2887 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2888 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2889 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2890 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2891 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2892 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2893 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2894 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2895 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2896 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2897 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2898 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2899 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2900 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2901 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2902 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2903 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2904 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2905 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2906 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2907 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2908 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2909 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2910 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2911 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2912 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2913 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2914 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2915 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2916 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2917 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2918 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2919 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2920 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2921 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2922 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2923 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2924 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2925 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2926 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2927 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2928 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2929 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2930 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2931 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2932 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2933 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2934 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2935 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2936 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2937 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2938 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2939 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2940 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2941 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2942 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2943 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2944 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2945 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2946 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2947 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2948 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2949 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2950 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2951 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2952 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2953 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2954 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2955 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2956 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2957 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 2958 +; 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GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3072 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3073 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3074 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3075 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3076 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3077 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3078 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3079 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3080 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3081 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3082 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3083 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3084 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3085 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3086 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3087 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3088 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3089 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3090 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3091 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3092 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3093 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3094 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3095 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3096 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3097 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3098 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3099 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3100 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3101 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3102 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 3103 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 32 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 33 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 34 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 35 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 36 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 37 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 38 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 39 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 40 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 41 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 42 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 43 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 44 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 45 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 46 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 47 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 48 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 49 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 50 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 51 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 52 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 53 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 54 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 55 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 56 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 57 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 58 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 59 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 60 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 61 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 72 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 73 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 74 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 75 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 76 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 77 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 78 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 79 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 88 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 89 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 90 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 91 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 92 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 93 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 94 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 95 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1096 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1097 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1098 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1099 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1100 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1101 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1102 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1103 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1112 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1113 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1114 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1115 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1116 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1117 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1118 +; GFX90A-V2A-DIS-NEXT: .cfi_undefined 1119 +; GFX90A-V2A-DIS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-V2A-DIS-NEXT: s_mov_b32 s16, s33 +; GFX90A-V2A-DIS-NEXT: s_mov_b32 s33, s32 +; GFX90A-V2A-DIS-NEXT: s_or_saveexec_b64 s[18:19], -1 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_offset 2600, 0 +; GFX90A-V2A-DIS-NEXT: s_mov_b64 exec, s[18:19] +; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s16, 2 +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_registers 65, 2600, 2, 32 +; GFX90A-V2A-DIS-NEXT: .cfi_def_cfa_register 65 +; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s30, 0 +; GFX90A-V2A-DIS-NEXT: s_addk_i32 s32, 0x400 +; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s31, 1 +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32 +; GFX90A-V2A-DIS-NEXT: s_getpc_b64 s[16:17] +; GFX90A-V2A-DIS-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4 +; GFX90A-V2A-DIS-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12 +; GFX90A-V2A-DIS-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX90A-V2A-DIS-NEXT: v_readlane_b32 s30, v40, 0 +; GFX90A-V2A-DIS-NEXT: v_readlane_b32 s31, v40, 1 +; GFX90A-V2A-DIS-NEXT: s_mov_b32 s32, s33 +; GFX90A-V2A-DIS-NEXT: v_readlane_b32 s4, v40, 2 +; GFX90A-V2A-DIS-NEXT: s_or_saveexec_b64 s[6:7], -1 +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: s_mov_b64 exec, s[6:7] +; GFX90A-V2A-DIS-NEXT: .cfi_def_cfa_register 64 +; GFX90A-V2A-DIS-NEXT: s_mov_b32 s33, s4 +; GFX90A-V2A-DIS-NEXT: s_waitcnt vmcnt(0) +; GFX90A-V2A-DIS-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-V2A-EN-LABEL: func_call_clobber: +; GFX90A-V2A-EN: .Lfunc_begin3: +; GFX90A-V2A-EN-NEXT: .cfi_startproc +; GFX90A-V2A-EN-NEXT: ; %bb.0: ; %entry +; GFX90A-V2A-EN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX90A-V2A-EN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2560 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2561 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2562 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2563 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2564 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2565 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2566 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2567 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2568 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2569 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2570 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2571 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2572 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2573 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2574 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2575 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2576 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2577 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2578 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2579 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2580 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2581 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2582 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2583 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2584 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2585 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2586 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2587 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2588 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2589 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2590 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2591 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2592 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2593 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2594 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2595 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2596 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2597 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2598 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2599 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2608 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2609 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2610 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2611 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2612 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2613 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2614 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2615 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2624 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2625 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2626 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2627 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2628 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2629 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2630 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2631 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2640 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2641 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2642 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2643 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2644 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2645 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2646 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2647 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2656 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2657 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2658 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2659 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2660 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2661 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2662 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2663 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2672 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2673 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2674 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2675 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2676 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2677 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2678 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2679 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2688 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2689 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2690 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2691 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2692 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2693 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2694 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2695 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2704 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2705 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2706 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2707 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2708 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2709 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2710 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2711 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2720 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2721 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2722 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2723 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2724 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2725 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2726 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2727 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2736 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2737 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2738 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2739 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2740 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2741 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2742 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2743 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2752 +; 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GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 4294967295 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3072 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3073 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3074 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3075 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3076 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3077 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3078 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3079 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3080 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3081 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3082 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3083 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3084 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3085 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3086 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3087 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3088 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3089 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3090 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3091 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3092 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3093 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3094 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3095 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3096 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3097 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3098 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3099 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3100 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3101 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3102 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3103 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 32 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 33 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 34 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 35 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 36 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 37 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 38 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 39 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 40 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 41 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 42 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 43 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 44 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 45 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 46 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 47 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 48 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 49 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 50 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 51 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 52 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 53 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 54 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 55 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 56 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 57 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 58 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 59 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 60 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 61 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 72 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 73 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 74 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 75 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 76 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 77 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 78 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 79 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 88 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 89 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 90 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 91 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 92 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 93 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 94 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 95 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1096 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1097 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1098 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1099 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1100 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1101 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1102 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1103 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1112 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1113 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1114 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1115 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1116 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1117 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1118 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 1119 +; GFX90A-V2A-EN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-V2A-EN-NEXT: s_mov_b32 s16, s33 +; GFX90A-V2A-EN-NEXT: s_mov_b32 s33, s32 +; GFX90A-V2A-EN-NEXT: s_or_saveexec_b64 s[18:19], -1 +; GFX90A-V2A-EN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX90A-V2A-EN-NEXT: .cfi_offset 2600, 0 +; GFX90A-V2A-EN-NEXT: s_mov_b64 exec, s[18:19] +; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s16, 2 +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_registers 65, 2600, 2, 32 +; GFX90A-V2A-EN-NEXT: .cfi_def_cfa_register 65 +; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s30, 0 +; GFX90A-V2A-EN-NEXT: s_addk_i32 s32, 0x400 +; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s31, 1 +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32 +; GFX90A-V2A-EN-NEXT: s_getpc_b64 s[16:17] +; GFX90A-V2A-EN-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4 +; GFX90A-V2A-EN-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12 +; GFX90A-V2A-EN-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX90A-V2A-EN-NEXT: v_readlane_b32 s30, v40, 0 +; GFX90A-V2A-EN-NEXT: v_readlane_b32 s31, v40, 1 +; GFX90A-V2A-EN-NEXT: s_mov_b32 s32, s33 +; GFX90A-V2A-EN-NEXT: v_readlane_b32 s4, v40, 2 +; GFX90A-V2A-EN-NEXT: s_or_saveexec_b64 s[6:7], -1 +; GFX90A-V2A-EN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload +; GFX90A-V2A-EN-NEXT: s_mov_b64 exec, s[6:7] +; GFX90A-V2A-EN-NEXT: .cfi_def_cfa_register 64 +; GFX90A-V2A-EN-NEXT: s_mov_b32 s33, s4 +; GFX90A-V2A-EN-NEXT: s_waitcnt vmcnt(0) +; GFX90A-V2A-EN-NEXT: s_setpc_b64 s[30:31] +; +; WAVE32-LABEL: func_call_clobber: +; WAVE32: .Lfunc_begin3: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: ; %entry +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: .cfi_undefined 1536 +; WAVE32-NEXT: .cfi_undefined 1537 +; WAVE32-NEXT: .cfi_undefined 1538 +; WAVE32-NEXT: .cfi_undefined 1539 +; WAVE32-NEXT: .cfi_undefined 1540 +; WAVE32-NEXT: .cfi_undefined 1541 +; WAVE32-NEXT: .cfi_undefined 1542 +; WAVE32-NEXT: .cfi_undefined 1543 +; WAVE32-NEXT: .cfi_undefined 1544 +; WAVE32-NEXT: .cfi_undefined 1545 +; WAVE32-NEXT: .cfi_undefined 1546 +; WAVE32-NEXT: .cfi_undefined 1547 +; WAVE32-NEXT: .cfi_undefined 1548 +; WAVE32-NEXT: .cfi_undefined 1549 +; WAVE32-NEXT: .cfi_undefined 1550 +; WAVE32-NEXT: .cfi_undefined 1551 +; WAVE32-NEXT: .cfi_undefined 1552 +; WAVE32-NEXT: .cfi_undefined 1553 +; WAVE32-NEXT: .cfi_undefined 1554 +; WAVE32-NEXT: .cfi_undefined 1555 +; WAVE32-NEXT: .cfi_undefined 1556 +; WAVE32-NEXT: .cfi_undefined 1557 +; WAVE32-NEXT: .cfi_undefined 1558 +; WAVE32-NEXT: .cfi_undefined 1559 +; WAVE32-NEXT: .cfi_undefined 1560 +; WAVE32-NEXT: .cfi_undefined 1561 +; WAVE32-NEXT: .cfi_undefined 1562 +; WAVE32-NEXT: .cfi_undefined 1563 +; WAVE32-NEXT: .cfi_undefined 1564 +; WAVE32-NEXT: .cfi_undefined 1565 +; WAVE32-NEXT: .cfi_undefined 1566 +; WAVE32-NEXT: .cfi_undefined 1567 +; WAVE32-NEXT: .cfi_undefined 1568 +; WAVE32-NEXT: .cfi_undefined 1569 +; WAVE32-NEXT: .cfi_undefined 1570 +; WAVE32-NEXT: .cfi_undefined 1571 +; WAVE32-NEXT: .cfi_undefined 1572 +; WAVE32-NEXT: .cfi_undefined 1573 +; WAVE32-NEXT: .cfi_undefined 1574 +; WAVE32-NEXT: .cfi_undefined 1575 +; WAVE32-NEXT: .cfi_undefined 1584 +; WAVE32-NEXT: .cfi_undefined 1585 +; WAVE32-NEXT: .cfi_undefined 1586 +; WAVE32-NEXT: .cfi_undefined 1587 +; WAVE32-NEXT: .cfi_undefined 1588 +; WAVE32-NEXT: .cfi_undefined 1589 +; WAVE32-NEXT: .cfi_undefined 1590 +; WAVE32-NEXT: .cfi_undefined 1591 +; WAVE32-NEXT: .cfi_undefined 1600 +; WAVE32-NEXT: .cfi_undefined 1601 +; WAVE32-NEXT: .cfi_undefined 1602 +; WAVE32-NEXT: .cfi_undefined 1603 +; WAVE32-NEXT: .cfi_undefined 1604 +; WAVE32-NEXT: .cfi_undefined 1605 +; WAVE32-NEXT: .cfi_undefined 1606 +; WAVE32-NEXT: .cfi_undefined 1607 +; WAVE32-NEXT: .cfi_undefined 1616 +; WAVE32-NEXT: .cfi_undefined 1617 +; WAVE32-NEXT: .cfi_undefined 1618 +; WAVE32-NEXT: .cfi_undefined 1619 +; WAVE32-NEXT: .cfi_undefined 1620 +; WAVE32-NEXT: .cfi_undefined 1621 +; WAVE32-NEXT: .cfi_undefined 1622 +; WAVE32-NEXT: .cfi_undefined 1623 +; WAVE32-NEXT: .cfi_undefined 1632 +; WAVE32-NEXT: .cfi_undefined 1633 +; WAVE32-NEXT: .cfi_undefined 1634 +; WAVE32-NEXT: .cfi_undefined 1635 +; WAVE32-NEXT: .cfi_undefined 1636 +; WAVE32-NEXT: .cfi_undefined 1637 +; WAVE32-NEXT: .cfi_undefined 1638 +; WAVE32-NEXT: .cfi_undefined 1639 +; WAVE32-NEXT: .cfi_undefined 1648 +; WAVE32-NEXT: .cfi_undefined 1649 +; WAVE32-NEXT: .cfi_undefined 1650 +; WAVE32-NEXT: .cfi_undefined 1651 +; WAVE32-NEXT: .cfi_undefined 1652 +; WAVE32-NEXT: .cfi_undefined 1653 +; WAVE32-NEXT: .cfi_undefined 1654 +; WAVE32-NEXT: .cfi_undefined 1655 +; WAVE32-NEXT: .cfi_undefined 1664 +; WAVE32-NEXT: .cfi_undefined 1665 +; WAVE32-NEXT: .cfi_undefined 1666 +; WAVE32-NEXT: .cfi_undefined 1667 +; WAVE32-NEXT: .cfi_undefined 1668 +; WAVE32-NEXT: .cfi_undefined 1669 +; WAVE32-NEXT: .cfi_undefined 1670 +; WAVE32-NEXT: .cfi_undefined 1671 +; WAVE32-NEXT: .cfi_undefined 1680 +; WAVE32-NEXT: .cfi_undefined 1681 +; WAVE32-NEXT: .cfi_undefined 1682 +; WAVE32-NEXT: .cfi_undefined 1683 +; WAVE32-NEXT: .cfi_undefined 1684 +; WAVE32-NEXT: .cfi_undefined 1685 +; WAVE32-NEXT: .cfi_undefined 1686 +; WAVE32-NEXT: .cfi_undefined 1687 +; WAVE32-NEXT: .cfi_undefined 1696 +; WAVE32-NEXT: .cfi_undefined 1697 +; WAVE32-NEXT: .cfi_undefined 1698 +; WAVE32-NEXT: .cfi_undefined 1699 +; WAVE32-NEXT: .cfi_undefined 1700 +; WAVE32-NEXT: .cfi_undefined 1701 +; WAVE32-NEXT: .cfi_undefined 1702 +; WAVE32-NEXT: .cfi_undefined 1703 +; WAVE32-NEXT: .cfi_undefined 1712 +; WAVE32-NEXT: .cfi_undefined 1713 +; WAVE32-NEXT: .cfi_undefined 1714 +; WAVE32-NEXT: .cfi_undefined 1715 +; WAVE32-NEXT: .cfi_undefined 1716 +; WAVE32-NEXT: .cfi_undefined 1717 +; WAVE32-NEXT: .cfi_undefined 1718 +; WAVE32-NEXT: .cfi_undefined 1719 +; WAVE32-NEXT: .cfi_undefined 1728 +; WAVE32-NEXT: .cfi_undefined 1729 +; WAVE32-NEXT: .cfi_undefined 1730 +; WAVE32-NEXT: .cfi_undefined 1731 +; WAVE32-NEXT: .cfi_undefined 1732 +; WAVE32-NEXT: .cfi_undefined 1733 +; WAVE32-NEXT: .cfi_undefined 1734 +; WAVE32-NEXT: .cfi_undefined 1735 +; WAVE32-NEXT: .cfi_undefined 1744 +; WAVE32-NEXT: .cfi_undefined 1745 +; WAVE32-NEXT: .cfi_undefined 1746 +; WAVE32-NEXT: .cfi_undefined 1747 +; WAVE32-NEXT: .cfi_undefined 1748 +; WAVE32-NEXT: .cfi_undefined 1749 +; WAVE32-NEXT: .cfi_undefined 1750 +; WAVE32-NEXT: .cfi_undefined 1751 +; WAVE32-NEXT: .cfi_undefined 1760 +; WAVE32-NEXT: .cfi_undefined 1761 +; WAVE32-NEXT: .cfi_undefined 1762 +; WAVE32-NEXT: .cfi_undefined 1763 +; WAVE32-NEXT: .cfi_undefined 1764 +; WAVE32-NEXT: .cfi_undefined 1765 +; WAVE32-NEXT: .cfi_undefined 1766 +; WAVE32-NEXT: .cfi_undefined 1767 +; WAVE32-NEXT: .cfi_undefined 1776 +; WAVE32-NEXT: .cfi_undefined 1777 +; WAVE32-NEXT: .cfi_undefined 1778 +; WAVE32-NEXT: .cfi_undefined 1779 +; WAVE32-NEXT: .cfi_undefined 1780 +; WAVE32-NEXT: .cfi_undefined 1781 +; WAVE32-NEXT: .cfi_undefined 1782 +; WAVE32-NEXT: .cfi_undefined 1783 +; WAVE32-NEXT: .cfi_undefined 1792 +; WAVE32-NEXT: .cfi_undefined 1793 +; WAVE32-NEXT: .cfi_undefined 1794 +; WAVE32-NEXT: .cfi_undefined 1795 +; WAVE32-NEXT: .cfi_undefined 1796 +; WAVE32-NEXT: .cfi_undefined 1797 +; WAVE32-NEXT: .cfi_undefined 1798 +; WAVE32-NEXT: .cfi_undefined 1799 +; WAVE32-NEXT: .cfi_undefined 1800 +; WAVE32-NEXT: .cfi_undefined 1801 +; WAVE32-NEXT: .cfi_undefined 1802 +; WAVE32-NEXT: .cfi_undefined 1803 +; WAVE32-NEXT: .cfi_undefined 1804 +; WAVE32-NEXT: .cfi_undefined 1805 +; WAVE32-NEXT: .cfi_undefined 1806 +; WAVE32-NEXT: .cfi_undefined 1807 +; WAVE32-NEXT: .cfi_undefined 1808 +; WAVE32-NEXT: .cfi_undefined 1809 +; WAVE32-NEXT: .cfi_undefined 1810 +; WAVE32-NEXT: .cfi_undefined 1811 +; WAVE32-NEXT: .cfi_undefined 1812 +; WAVE32-NEXT: .cfi_undefined 1813 +; WAVE32-NEXT: .cfi_undefined 1814 +; WAVE32-NEXT: .cfi_undefined 1815 +; WAVE32-NEXT: .cfi_undefined 1816 +; WAVE32-NEXT: .cfi_undefined 1817 +; WAVE32-NEXT: .cfi_undefined 1818 +; WAVE32-NEXT: .cfi_undefined 1819 +; WAVE32-NEXT: .cfi_undefined 1820 +; WAVE32-NEXT: .cfi_undefined 1821 +; WAVE32-NEXT: .cfi_undefined 1822 +; WAVE32-NEXT: .cfi_undefined 1823 +; WAVE32-NEXT: .cfi_undefined 1824 +; WAVE32-NEXT: .cfi_undefined 1825 +; WAVE32-NEXT: .cfi_undefined 1826 +; WAVE32-NEXT: .cfi_undefined 1827 +; WAVE32-NEXT: .cfi_undefined 1828 +; WAVE32-NEXT: .cfi_undefined 1829 +; WAVE32-NEXT: .cfi_undefined 1830 +; WAVE32-NEXT: .cfi_undefined 1831 +; WAVE32-NEXT: .cfi_undefined 1832 +; WAVE32-NEXT: .cfi_undefined 1833 +; WAVE32-NEXT: .cfi_undefined 1834 +; WAVE32-NEXT: .cfi_undefined 1835 +; WAVE32-NEXT: .cfi_undefined 1836 +; WAVE32-NEXT: .cfi_undefined 1837 +; WAVE32-NEXT: .cfi_undefined 1838 +; WAVE32-NEXT: .cfi_undefined 1839 +; WAVE32-NEXT: .cfi_undefined 1840 +; WAVE32-NEXT: .cfi_undefined 1841 +; WAVE32-NEXT: .cfi_undefined 1842 +; WAVE32-NEXT: .cfi_undefined 1843 +; WAVE32-NEXT: .cfi_undefined 1844 +; WAVE32-NEXT: .cfi_undefined 1845 +; WAVE32-NEXT: .cfi_undefined 1846 +; WAVE32-NEXT: .cfi_undefined 1847 +; WAVE32-NEXT: .cfi_undefined 1848 +; WAVE32-NEXT: .cfi_undefined 1849 +; WAVE32-NEXT: .cfi_undefined 1850 +; WAVE32-NEXT: .cfi_undefined 1851 +; WAVE32-NEXT: .cfi_undefined 1852 +; WAVE32-NEXT: .cfi_undefined 1853 +; WAVE32-NEXT: .cfi_undefined 1854 +; WAVE32-NEXT: .cfi_undefined 1855 +; WAVE32-NEXT: .cfi_undefined 1856 +; WAVE32-NEXT: .cfi_undefined 1857 +; WAVE32-NEXT: .cfi_undefined 1858 +; WAVE32-NEXT: .cfi_undefined 1859 +; WAVE32-NEXT: .cfi_undefined 1860 +; WAVE32-NEXT: .cfi_undefined 1861 +; WAVE32-NEXT: .cfi_undefined 1862 +; WAVE32-NEXT: .cfi_undefined 1863 +; WAVE32-NEXT: .cfi_undefined 1864 +; WAVE32-NEXT: .cfi_undefined 1865 +; WAVE32-NEXT: .cfi_undefined 1866 +; WAVE32-NEXT: .cfi_undefined 1867 +; WAVE32-NEXT: .cfi_undefined 1868 +; WAVE32-NEXT: .cfi_undefined 1869 +; WAVE32-NEXT: .cfi_undefined 1870 +; WAVE32-NEXT: .cfi_undefined 1871 +; WAVE32-NEXT: .cfi_undefined 1872 +; WAVE32-NEXT: .cfi_undefined 1873 +; WAVE32-NEXT: .cfi_undefined 1874 +; WAVE32-NEXT: .cfi_undefined 1875 +; WAVE32-NEXT: .cfi_undefined 1876 +; WAVE32-NEXT: .cfi_undefined 1877 +; WAVE32-NEXT: .cfi_undefined 1878 +; WAVE32-NEXT: .cfi_undefined 1879 +; WAVE32-NEXT: .cfi_undefined 1880 +; WAVE32-NEXT: .cfi_undefined 1881 +; WAVE32-NEXT: .cfi_undefined 1882 +; WAVE32-NEXT: .cfi_undefined 1883 +; WAVE32-NEXT: .cfi_undefined 1884 +; WAVE32-NEXT: .cfi_undefined 1885 +; WAVE32-NEXT: .cfi_undefined 1886 +; WAVE32-NEXT: .cfi_undefined 1887 +; WAVE32-NEXT: .cfi_undefined 1888 +; WAVE32-NEXT: .cfi_undefined 1889 +; WAVE32-NEXT: .cfi_undefined 1890 +; WAVE32-NEXT: .cfi_undefined 1891 +; WAVE32-NEXT: .cfi_undefined 1892 +; WAVE32-NEXT: .cfi_undefined 1893 +; WAVE32-NEXT: .cfi_undefined 1894 +; WAVE32-NEXT: .cfi_undefined 1895 +; WAVE32-NEXT: .cfi_undefined 1896 +; WAVE32-NEXT: .cfi_undefined 1897 +; WAVE32-NEXT: .cfi_undefined 1898 +; WAVE32-NEXT: .cfi_undefined 1899 +; WAVE32-NEXT: .cfi_undefined 1900 +; WAVE32-NEXT: .cfi_undefined 1901 +; WAVE32-NEXT: .cfi_undefined 1902 +; WAVE32-NEXT: .cfi_undefined 1903 +; WAVE32-NEXT: .cfi_undefined 1904 +; WAVE32-NEXT: .cfi_undefined 1905 +; WAVE32-NEXT: .cfi_undefined 1906 +; WAVE32-NEXT: .cfi_undefined 1907 +; WAVE32-NEXT: .cfi_undefined 1908 +; WAVE32-NEXT: .cfi_undefined 1909 +; WAVE32-NEXT: .cfi_undefined 1910 +; WAVE32-NEXT: .cfi_undefined 1911 +; WAVE32-NEXT: .cfi_undefined 1912 +; WAVE32-NEXT: .cfi_undefined 1913 +; WAVE32-NEXT: .cfi_undefined 1914 +; WAVE32-NEXT: .cfi_undefined 1915 +; WAVE32-NEXT: .cfi_undefined 1916 +; WAVE32-NEXT: .cfi_undefined 1917 +; WAVE32-NEXT: .cfi_undefined 1918 +; WAVE32-NEXT: .cfi_undefined 1919 +; WAVE32-NEXT: .cfi_undefined 1920 +; WAVE32-NEXT: .cfi_undefined 1921 +; WAVE32-NEXT: .cfi_undefined 1922 +; WAVE32-NEXT: .cfi_undefined 1923 +; WAVE32-NEXT: .cfi_undefined 1924 +; WAVE32-NEXT: .cfi_undefined 1925 +; WAVE32-NEXT: .cfi_undefined 1926 +; WAVE32-NEXT: .cfi_undefined 1927 +; WAVE32-NEXT: .cfi_undefined 1928 +; WAVE32-NEXT: .cfi_undefined 1929 +; WAVE32-NEXT: .cfi_undefined 1930 +; WAVE32-NEXT: .cfi_undefined 1931 +; WAVE32-NEXT: .cfi_undefined 1932 +; WAVE32-NEXT: .cfi_undefined 1933 +; WAVE32-NEXT: .cfi_undefined 1934 +; WAVE32-NEXT: .cfi_undefined 1935 +; WAVE32-NEXT: .cfi_undefined 1936 +; WAVE32-NEXT: .cfi_undefined 1937 +; WAVE32-NEXT: .cfi_undefined 1938 +; WAVE32-NEXT: .cfi_undefined 1939 +; WAVE32-NEXT: .cfi_undefined 1940 +; WAVE32-NEXT: .cfi_undefined 1941 +; WAVE32-NEXT: .cfi_undefined 1942 +; WAVE32-NEXT: .cfi_undefined 1943 +; WAVE32-NEXT: .cfi_undefined 1944 +; WAVE32-NEXT: .cfi_undefined 1945 +; WAVE32-NEXT: .cfi_undefined 1946 +; WAVE32-NEXT: .cfi_undefined 1947 +; WAVE32-NEXT: .cfi_undefined 1948 +; WAVE32-NEXT: .cfi_undefined 1949 +; WAVE32-NEXT: .cfi_undefined 1950 +; WAVE32-NEXT: .cfi_undefined 1951 +; WAVE32-NEXT: .cfi_undefined 1952 +; WAVE32-NEXT: .cfi_undefined 1953 +; WAVE32-NEXT: .cfi_undefined 1954 +; WAVE32-NEXT: .cfi_undefined 1955 +; WAVE32-NEXT: .cfi_undefined 1956 +; WAVE32-NEXT: .cfi_undefined 1957 +; WAVE32-NEXT: .cfi_undefined 1958 +; WAVE32-NEXT: .cfi_undefined 1959 +; WAVE32-NEXT: .cfi_undefined 1960 +; WAVE32-NEXT: .cfi_undefined 1961 +; WAVE32-NEXT: .cfi_undefined 1962 +; WAVE32-NEXT: .cfi_undefined 1963 +; WAVE32-NEXT: .cfi_undefined 1964 +; WAVE32-NEXT: .cfi_undefined 1965 +; WAVE32-NEXT: .cfi_undefined 1966 +; WAVE32-NEXT: .cfi_undefined 1967 +; WAVE32-NEXT: .cfi_undefined 1968 +; WAVE32-NEXT: .cfi_undefined 1969 +; WAVE32-NEXT: .cfi_undefined 1970 +; WAVE32-NEXT: .cfi_undefined 1971 +; WAVE32-NEXT: .cfi_undefined 1972 +; WAVE32-NEXT: .cfi_undefined 1973 +; WAVE32-NEXT: .cfi_undefined 1974 +; WAVE32-NEXT: .cfi_undefined 1975 +; WAVE32-NEXT: .cfi_undefined 1976 +; WAVE32-NEXT: .cfi_undefined 1977 +; WAVE32-NEXT: .cfi_undefined 1978 +; WAVE32-NEXT: .cfi_undefined 1979 +; WAVE32-NEXT: .cfi_undefined 1980 +; WAVE32-NEXT: .cfi_undefined 1981 +; WAVE32-NEXT: .cfi_undefined 1982 +; WAVE32-NEXT: .cfi_undefined 1983 +; WAVE32-NEXT: .cfi_undefined 1984 +; WAVE32-NEXT: .cfi_undefined 1985 +; WAVE32-NEXT: .cfi_undefined 1986 +; WAVE32-NEXT: .cfi_undefined 1987 +; WAVE32-NEXT: .cfi_undefined 1988 +; WAVE32-NEXT: .cfi_undefined 1989 +; WAVE32-NEXT: .cfi_undefined 1990 +; WAVE32-NEXT: .cfi_undefined 1991 +; WAVE32-NEXT: .cfi_undefined 1992 +; WAVE32-NEXT: .cfi_undefined 1993 +; WAVE32-NEXT: .cfi_undefined 1994 +; WAVE32-NEXT: .cfi_undefined 1995 +; WAVE32-NEXT: .cfi_undefined 1996 +; WAVE32-NEXT: .cfi_undefined 1997 +; WAVE32-NEXT: .cfi_undefined 1998 +; WAVE32-NEXT: .cfi_undefined 1999 +; WAVE32-NEXT: .cfi_undefined 2000 +; WAVE32-NEXT: .cfi_undefined 2001 +; WAVE32-NEXT: .cfi_undefined 2002 +; WAVE32-NEXT: .cfi_undefined 2003 +; WAVE32-NEXT: .cfi_undefined 2004 +; WAVE32-NEXT: .cfi_undefined 2005 +; WAVE32-NEXT: .cfi_undefined 2006 +; WAVE32-NEXT: .cfi_undefined 2007 +; WAVE32-NEXT: .cfi_undefined 2008 +; WAVE32-NEXT: .cfi_undefined 2009 +; WAVE32-NEXT: .cfi_undefined 2010 +; WAVE32-NEXT: .cfi_undefined 2011 +; WAVE32-NEXT: .cfi_undefined 2012 +; WAVE32-NEXT: .cfi_undefined 2013 +; WAVE32-NEXT: .cfi_undefined 2014 +; WAVE32-NEXT: .cfi_undefined 2015 +; WAVE32-NEXT: .cfi_undefined 2016 +; WAVE32-NEXT: .cfi_undefined 2017 +; WAVE32-NEXT: .cfi_undefined 2018 +; WAVE32-NEXT: .cfi_undefined 2019 +; WAVE32-NEXT: .cfi_undefined 2020 +; WAVE32-NEXT: .cfi_undefined 2021 +; WAVE32-NEXT: .cfi_undefined 2022 +; WAVE32-NEXT: .cfi_undefined 2023 +; WAVE32-NEXT: .cfi_undefined 2024 +; WAVE32-NEXT: .cfi_undefined 2025 +; WAVE32-NEXT: .cfi_undefined 2026 +; WAVE32-NEXT: .cfi_undefined 2027 +; WAVE32-NEXT: .cfi_undefined 2028 +; WAVE32-NEXT: .cfi_undefined 2029 +; WAVE32-NEXT: .cfi_undefined 2030 +; WAVE32-NEXT: .cfi_undefined 2031 +; WAVE32-NEXT: .cfi_undefined 2032 +; WAVE32-NEXT: .cfi_undefined 2033 +; WAVE32-NEXT: .cfi_undefined 2034 +; WAVE32-NEXT: .cfi_undefined 2035 +; WAVE32-NEXT: .cfi_undefined 2036 +; WAVE32-NEXT: .cfi_undefined 2037 +; WAVE32-NEXT: .cfi_undefined 2038 +; WAVE32-NEXT: .cfi_undefined 2039 +; WAVE32-NEXT: .cfi_undefined 2040 +; WAVE32-NEXT: .cfi_undefined 2041 +; WAVE32-NEXT: .cfi_undefined 2042 +; WAVE32-NEXT: .cfi_undefined 2043 +; WAVE32-NEXT: .cfi_undefined 2044 +; WAVE32-NEXT: .cfi_undefined 2045 +; WAVE32-NEXT: .cfi_undefined 2046 +; WAVE32-NEXT: .cfi_undefined 2047 +; WAVE32-NEXT: .cfi_undefined 3584 +; WAVE32-NEXT: .cfi_undefined 3585 +; WAVE32-NEXT: .cfi_undefined 3586 +; WAVE32-NEXT: .cfi_undefined 3587 +; WAVE32-NEXT: .cfi_undefined 3588 +; WAVE32-NEXT: .cfi_undefined 3589 +; WAVE32-NEXT: .cfi_undefined 3590 +; WAVE32-NEXT: .cfi_undefined 3591 +; WAVE32-NEXT: .cfi_undefined 3592 +; WAVE32-NEXT: .cfi_undefined 3593 +; WAVE32-NEXT: .cfi_undefined 3594 +; WAVE32-NEXT: .cfi_undefined 3595 +; WAVE32-NEXT: .cfi_undefined 3596 +; WAVE32-NEXT: .cfi_undefined 3597 +; WAVE32-NEXT: .cfi_undefined 3598 +; WAVE32-NEXT: .cfi_undefined 3599 +; WAVE32-NEXT: .cfi_undefined 3600 +; WAVE32-NEXT: .cfi_undefined 3601 +; WAVE32-NEXT: .cfi_undefined 3602 +; WAVE32-NEXT: .cfi_undefined 3603 +; WAVE32-NEXT: .cfi_undefined 3604 +; WAVE32-NEXT: .cfi_undefined 3605 +; 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WAVE32-NEXT: .cfi_undefined 4082 +; WAVE32-NEXT: .cfi_undefined 4083 +; WAVE32-NEXT: .cfi_undefined 4084 +; WAVE32-NEXT: .cfi_undefined 4085 +; WAVE32-NEXT: .cfi_undefined 4086 +; WAVE32-NEXT: .cfi_undefined 4087 +; WAVE32-NEXT: .cfi_undefined 4088 +; WAVE32-NEXT: .cfi_undefined 4089 +; WAVE32-NEXT: .cfi_undefined 4090 +; WAVE32-NEXT: .cfi_undefined 4091 +; WAVE32-NEXT: .cfi_undefined 4092 +; WAVE32-NEXT: .cfi_undefined 4093 +; WAVE32-NEXT: .cfi_undefined 4094 +; WAVE32-NEXT: .cfi_undefined 4095 +; WAVE32-NEXT: .cfi_undefined 32 +; WAVE32-NEXT: .cfi_undefined 33 +; WAVE32-NEXT: .cfi_undefined 34 +; WAVE32-NEXT: .cfi_undefined 35 +; WAVE32-NEXT: .cfi_undefined 36 +; WAVE32-NEXT: .cfi_undefined 37 +; WAVE32-NEXT: .cfi_undefined 38 +; WAVE32-NEXT: .cfi_undefined 39 +; WAVE32-NEXT: .cfi_undefined 40 +; WAVE32-NEXT: .cfi_undefined 41 +; WAVE32-NEXT: .cfi_undefined 42 +; WAVE32-NEXT: .cfi_undefined 43 +; WAVE32-NEXT: .cfi_undefined 44 +; WAVE32-NEXT: .cfi_undefined 45 +; WAVE32-NEXT: .cfi_undefined 46 +; WAVE32-NEXT: .cfi_undefined 47 +; WAVE32-NEXT: .cfi_undefined 48 +; WAVE32-NEXT: .cfi_undefined 49 +; WAVE32-NEXT: .cfi_undefined 50 +; WAVE32-NEXT: .cfi_undefined 51 +; WAVE32-NEXT: .cfi_undefined 52 +; WAVE32-NEXT: .cfi_undefined 53 +; WAVE32-NEXT: .cfi_undefined 54 +; WAVE32-NEXT: .cfi_undefined 55 +; WAVE32-NEXT: .cfi_undefined 56 +; WAVE32-NEXT: .cfi_undefined 57 +; WAVE32-NEXT: .cfi_undefined 58 +; WAVE32-NEXT: .cfi_undefined 59 +; WAVE32-NEXT: .cfi_undefined 60 +; WAVE32-NEXT: .cfi_undefined 61 +; WAVE32-NEXT: .cfi_undefined 72 +; WAVE32-NEXT: .cfi_undefined 73 +; WAVE32-NEXT: .cfi_undefined 74 +; WAVE32-NEXT: .cfi_undefined 75 +; WAVE32-NEXT: .cfi_undefined 76 +; WAVE32-NEXT: .cfi_undefined 77 +; WAVE32-NEXT: .cfi_undefined 78 +; WAVE32-NEXT: .cfi_undefined 79 +; WAVE32-NEXT: .cfi_undefined 88 +; WAVE32-NEXT: .cfi_undefined 89 +; WAVE32-NEXT: .cfi_undefined 90 +; WAVE32-NEXT: .cfi_undefined 91 +; WAVE32-NEXT: .cfi_undefined 92 +; WAVE32-NEXT: .cfi_undefined 93 +; WAVE32-NEXT: .cfi_undefined 94 +; WAVE32-NEXT: .cfi_undefined 95 +; WAVE32-NEXT: .cfi_undefined 1096 +; WAVE32-NEXT: .cfi_undefined 1097 +; WAVE32-NEXT: .cfi_undefined 1098 +; WAVE32-NEXT: .cfi_undefined 1099 +; WAVE32-NEXT: .cfi_undefined 1100 +; WAVE32-NEXT: .cfi_undefined 1101 +; WAVE32-NEXT: .cfi_undefined 1102 +; WAVE32-NEXT: .cfi_undefined 1103 +; WAVE32-NEXT: .cfi_undefined 1112 +; WAVE32-NEXT: .cfi_undefined 1113 +; WAVE32-NEXT: .cfi_undefined 1114 +; WAVE32-NEXT: .cfi_undefined 1115 +; WAVE32-NEXT: .cfi_undefined 1116 +; WAVE32-NEXT: .cfi_undefined 1117 +; WAVE32-NEXT: .cfi_undefined 1118 +; WAVE32-NEXT: .cfi_undefined 1119 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: s_mov_b32 s16, s33 +; WAVE32-NEXT: s_mov_b32 s33, s32 +; WAVE32-NEXT: s_or_saveexec_b32 s17, -1 +; WAVE32-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_offset 1576, 0 +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s17 +; WAVE32-NEXT: v_writelane_b32 v40, s16, 2 +; WAVE32-NEXT: .cfi_llvm_vector_registers 65, 1576, 2, 32 +; WAVE32-NEXT: .cfi_def_cfa_register 65 +; WAVE32-NEXT: v_writelane_b32 v40, s30, 0 +; WAVE32-NEXT: s_addk_i32 s32, 0x200 +; WAVE32-NEXT: v_writelane_b32 v40, s31, 1 +; WAVE32-NEXT: .cfi_llvm_vector_registers 16, 1576, 0, 32, 1576, 1, 32 +; WAVE32-NEXT: s_getpc_b64 s[16:17] +; WAVE32-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4 +; WAVE32-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12 +; WAVE32-NEXT: s_swappc_b64 s[30:31], s[16:17] +; WAVE32-NEXT: v_readlane_b32 s30, v40, 0 +; WAVE32-NEXT: v_readlane_b32 s31, v40, 1 +; WAVE32-NEXT: s_mov_b32 s32, s33 +; WAVE32-NEXT: v_readlane_b32 s4, v40, 2 +; WAVE32-NEXT: s_or_saveexec_b32 s5, -1 +; WAVE32-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload +; WAVE32-NEXT: s_waitcnt_depctr 0xffe3 +; WAVE32-NEXT: s_mov_b32 exec_lo, s5 +; WAVE32-NEXT: .cfi_def_cfa_register 64 +; WAVE32-NEXT: s_mov_b32 s33, s4 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_setpc_b64 s[30:31] +entry: + call void @ex() #0 + ret void +} + +define hidden void @func_spill_vgpr_to_vmem() #0 { +; GFX900-LABEL: func_spill_vgpr_to_vmem: +; GFX900: .Lfunc_begin4: +; GFX900-NEXT: .cfi_startproc +; GFX900-NEXT: ; %bb.0: ; %entry +; GFX900-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX900-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 256 +; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 0 +; GFX900-NEXT: ;;#ASMSTART +; GFX900-NEXT: ; clobber +; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: ;;#ASMSTART +; GFX900-NEXT: ; clobber +; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: ;;#ASMSTART +; GFX900-NEXT: ; clobber +; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: ;;#ASMSTART +; GFX900-NEXT: ; clobber +; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-V2A-DIS-LABEL: func_spill_vgpr_to_vmem: +; GFX90A-V2A-DIS: .Lfunc_begin4: +; GFX90A-V2A-DIS-NEXT: .cfi_startproc +; GFX90A-V2A-DIS-NEXT: ; %bb.0: ; %entry +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX90A-V2A-DIS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 768 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 512 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword a32, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 3104, 32, 17, 64, 256 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword a33, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 3105, 32, 17, 64, 0 +; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART +; GFX90A-V2A-DIS-NEXT: ; clobber +; GFX90A-V2A-DIS-NEXT: ;;#ASMEND +; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART +; GFX90A-V2A-DIS-NEXT: ; clobber +; GFX90A-V2A-DIS-NEXT: ;;#ASMEND +; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART +; GFX90A-V2A-DIS-NEXT: ; clobber +; GFX90A-V2A-DIS-NEXT: ;;#ASMEND +; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART +; GFX90A-V2A-DIS-NEXT: ; clobber +; GFX90A-V2A-DIS-NEXT: ;;#ASMEND +; GFX90A-V2A-DIS-NEXT: buffer_load_dword a33, off, s[0:3], s32 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: s_waitcnt vmcnt(0) +; GFX90A-V2A-DIS-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-V2A-EN-LABEL: func_spill_vgpr_to_vmem: +; GFX90A-V2A-EN: .Lfunc_begin4: +; GFX90A-V2A-EN-NEXT: .cfi_startproc +; GFX90A-V2A-EN-NEXT: ; %bb.0: ; %entry +; GFX90A-V2A-EN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX90A-V2A-EN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2560 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2561 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3072 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3073 +; GFX90A-V2A-EN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2600, 3072, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2601, 3073, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v0, a32 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 3104, 2560, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v1, a33 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 3105, 2561, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: ;;#ASMSTART +; GFX90A-V2A-EN-NEXT: ; clobber +; GFX90A-V2A-EN-NEXT: ;;#ASMEND +; GFX90A-V2A-EN-NEXT: ;;#ASMSTART +; GFX90A-V2A-EN-NEXT: ; clobber +; GFX90A-V2A-EN-NEXT: ;;#ASMEND +; GFX90A-V2A-EN-NEXT: ;;#ASMSTART +; GFX90A-V2A-EN-NEXT: ; clobber +; GFX90A-V2A-EN-NEXT: ;;#ASMEND +; GFX90A-V2A-EN-NEXT: ;;#ASMSTART +; GFX90A-V2A-EN-NEXT: ; clobber +; GFX90A-V2A-EN-NEXT: ;;#ASMEND +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a33, v1 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a32, v0 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v41, a1 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v40, a0 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: s_setpc_b64 s[30:31] +; +; WAVE32-LABEL: func_spill_vgpr_to_vmem: +; WAVE32: .Lfunc_begin4: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: ; %entry +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1576, 32, 1, 32, 128 +; WAVE32-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1577, 32, 1, 32, 0 +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: s_clause 0x1 +; WAVE32-NEXT: buffer_load_dword v41, off, s[0:3], s32 +; WAVE32-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_setpc_b64 s[30:31] +entry: + call void asm sideeffect "; clobber", "~{v40}"() #0 + call void asm sideeffect "; clobber", "~{v41}"() #0 + call void asm sideeffect "; clobber", "~{a32}"() #0 + call void asm sideeffect "; clobber", "~{a33}"() #0 + ret void +} + +define hidden void @func_spill_vgpr_to_agpr() #2 { +; GFX900-LABEL: func_spill_vgpr_to_agpr: +; GFX900: .Lfunc_begin5: +; GFX900-NEXT: .cfi_startproc +; GFX900-NEXT: ; %bb.0: +; GFX900-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX900-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 256 +; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX900-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 0 +; GFX900-NEXT: ;;#ASMSTART +; GFX900-NEXT: ; clobber +; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: ;;#ASMSTART +; GFX900-NEXT: ; clobber +; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: ;;#ASMSTART +; GFX900-NEXT: ; clobber +; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: ;;#ASMSTART +; GFX900-NEXT: ; clobber +; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload +; GFX900-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-V2A-DIS-LABEL: func_spill_vgpr_to_agpr: +; GFX90A-V2A-DIS: .Lfunc_begin5: +; GFX90A-V2A-DIS-NEXT: .cfi_startproc +; GFX90A-V2A-DIS-NEXT: ; %bb.0: +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX90A-V2A-DIS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 768 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 512 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword a32, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 3104, 32, 17, 64, 256 +; GFX90A-V2A-DIS-NEXT: buffer_store_dword a33, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 3105, 32, 17, 64, 0 +; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART +; GFX90A-V2A-DIS-NEXT: ; clobber +; GFX90A-V2A-DIS-NEXT: ;;#ASMEND +; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART +; GFX90A-V2A-DIS-NEXT: ; clobber +; GFX90A-V2A-DIS-NEXT: ;;#ASMEND +; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART +; GFX90A-V2A-DIS-NEXT: ; clobber +; GFX90A-V2A-DIS-NEXT: ;;#ASMEND +; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART +; GFX90A-V2A-DIS-NEXT: ; clobber +; GFX90A-V2A-DIS-NEXT: ;;#ASMEND +; GFX90A-V2A-DIS-NEXT: buffer_load_dword a33, off, s[0:3], s32 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GFX90A-V2A-DIS-NEXT: s_waitcnt vmcnt(0) +; GFX90A-V2A-DIS-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-V2A-EN-LABEL: func_spill_vgpr_to_agpr: +; GFX90A-V2A-EN: .Lfunc_begin5: +; GFX90A-V2A-EN-NEXT: .cfi_startproc +; GFX90A-V2A-EN-NEXT: ; %bb.0: +; GFX90A-V2A-EN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GFX90A-V2A-EN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2560 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 2561 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3072 +; GFX90A-V2A-EN-NEXT: .cfi_undefined 3073 +; GFX90A-V2A-EN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2600, 3072, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2601, 3073, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v0, a32 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 3104, 2560, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v1, a33 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 3105, 2561, 32, 17, 64 +; GFX90A-V2A-EN-NEXT: ;;#ASMSTART +; GFX90A-V2A-EN-NEXT: ; clobber +; GFX90A-V2A-EN-NEXT: ;;#ASMEND +; GFX90A-V2A-EN-NEXT: ;;#ASMSTART +; GFX90A-V2A-EN-NEXT: ; clobber +; GFX90A-V2A-EN-NEXT: ;;#ASMEND +; GFX90A-V2A-EN-NEXT: ;;#ASMSTART +; GFX90A-V2A-EN-NEXT: ; clobber +; GFX90A-V2A-EN-NEXT: ;;#ASMEND +; GFX90A-V2A-EN-NEXT: ;;#ASMSTART +; GFX90A-V2A-EN-NEXT: ; clobber +; GFX90A-V2A-EN-NEXT: ;;#ASMEND +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a33, v1 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a32, v0 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v41, a1 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v40, a0 ; Reload Reuse +; GFX90A-V2A-EN-NEXT: s_setpc_b64 s[30:31] +; +; WAVE32-LABEL: func_spill_vgpr_to_agpr: +; WAVE32: .Lfunc_begin5: +; WAVE32-NEXT: .cfi_startproc +; WAVE32-NEXT: ; %bb.0: +; WAVE32-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; WAVE32-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1576, 32, 1, 32, 128 +; WAVE32-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill +; WAVE32-NEXT: .cfi_llvm_vector_offset 1577, 32, 1, 32, 0 +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: ;;#ASMSTART +; WAVE32-NEXT: ; clobber +; WAVE32-NEXT: ;;#ASMEND +; WAVE32-NEXT: s_clause 0x1 +; WAVE32-NEXT: buffer_load_dword v41, off, s[0:3], s32 +; WAVE32-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 +; WAVE32-NEXT: s_waitcnt vmcnt(0) +; WAVE32-NEXT: s_setpc_b64 s[30:31] + call void asm sideeffect "; clobber", "~{v40}"() + call void asm sideeffect "; clobber", "~{v41}"() + call void asm sideeffect "; clobber", "~{a32}"() + call void asm sideeffect "; clobber", "~{a33}"() + ret void +} + + +; NOTE: Number of VGPRs available to kernel, and in turn number of corresponding CFIs generated, +; is dependent on waves/WG size. Since the intent here is to check whether we generate the correct +; CFIs, doing it for any one set of details is sufficient which also makes the test insensitive to +; changes in those details. +attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="128,128" } +attributes #1 = { nounwind "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="128,128" "frame-pointer"="all" } +attributes #2 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, emissionKind: FullDebug) +!1 = !DIFile(filename: "filename", directory: "directory") +!2 = !{i32 7, !"Dwarf Version", i32 4} +!3 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/llvm/test/CodeGen/AMDGPU/debug-type-mutate.ll b/llvm/test/CodeGen/AMDGPU/debug-type-mutate.ll new file mode 100644 index 0000000000000..7c82cdb805c92 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/debug-type-mutate.ll @@ -0,0 +1,50 @@ +; RUN: llc -stop-after=codegenprepare < %s | FileCheck %s +target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" +target triple = "amdgcn-amd-amdhsa" + +@0 = addrspace(4) constant [16 x i8] c"AAAAAAAAAAAAAAAA", align 16 +@1 = addrspace(1) constant [16 x i8] c"AAAAAAAAAAAAAAAA", align 16 + +define void @func1(i32 %a0, i8 %a1, ptr %a2) #0 { +; CHECK: define void @func1(i32 %a0, i8 %a1, ptr %a2) #0 { +; CHECK-NEXT: %promoted = zext i32 %a0 to i64 +; CHECK-NEXT: %vl0 = lshr i64 %promoted, 12 +; CHECK-NEXT: #dbg_value(!DIArgList(i32 0, i64 %vl0), !4, !DIExpression(DIOpArg(1, i64), DIOpConvert(i32), DIOpConvert(i8), DIOpFragment(24, 8)), !9) + %vl0 = lshr i32 %a0, 12 + #dbg_value(!DIArgList(i32 0, i32 %vl0), !4, !DIExpression(DIOpArg(1, i32), DIOpConvert(i8), DIOpFragment(24, 8)), !9) + %op0 = zext nneg i32 %vl0 to i64 + %op1 = getelementptr inbounds nuw i8, ptr addrspace(4) @0, i64 %op0 + %op2 = load i8, ptr addrspace(4) %op1, align 1 + store i8 %op2, ptr %a2, align 1 + ret void +} + +define void @func2(i32 %a0, i8 %a1, ptr %a2) #0 { +; CHECK: define void @func2(i32 %a0, i8 %a1, ptr %a2) #0 { +; CHECK-NEXT: %vl0 = lshr i32 %a0, 12 +; CHECK-NEXT: #dbg_value(!DIArgList(i32 0, i32 %vl0), !4, !DIExpression(DIOpArg(1, i32), DIOpConvert(i8), DIOpFragment(24, 8)), !9) + %vl0 = lshr i32 %a0, 12 + #dbg_value(!DIArgList(i32 0, i32 %vl0), !4, !DIExpression(DIOpArg(1, i32), DIOpConvert(i8), DIOpFragment(24, 8)), !9) + %op0 = zext nneg i32 %vl0 to i64 + %op1 = getelementptr inbounds nuw i8, ptr addrspace(1) @1, i64 %op0 + %op2 = load i8, ptr addrspace(1) %op1, align 1 + store i8 %op2, ptr %a2, align 1 + ret void +} + + +attributes #0 = { "target-cpu"="gfx1201" } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) +!1 = !DIFile(filename: "-", directory: "/") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !DILocalVariable(name: "aux32", scope: !5, file: !1, line: 1757, type: !8) +!5 = distinct !DISubprogram(name: "func", scope: !1, file: !1, line: 1754, type: !6, unit: !0) +!6 = !DISubroutineType(types: !7) +!7 = !{null} +!8 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned) +!9 = !DILocation(line: 0, scope: !5) diff --git a/llvm/test/CodeGen/AMDGPU/debug-value.ll b/llvm/test/CodeGen/AMDGPU/debug-value.ll index 6b2a36c1f142d..e6c62f87a37a6 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-value.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s %struct.wombat = type { [4 x i32], [4 x i32], [4 x i32] } diff --git a/llvm/test/CodeGen/AMDGPU/debug-value2.ll b/llvm/test/CodeGen/AMDGPU/debug-value2.ll index 3454831dff663..daf092f765495 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value2.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-value2.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false < %s | FileCheck %s %struct.ShapeData = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32, i64, <4 x float>, i32, i8, i8, i16, i32, i32 } @@ -365,10 +365,10 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) !81 = !{!82} !82 = !DISubrange(count: 4) !83 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!84 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !85, size: 32, dwarfAddressSpace: 1) +!84 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !85, size: 32, addressSpace: 1) !85 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !86) !86 = !DIBasicType(name: "half", size: 16, encoding: DW_ATE_float) -!87 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !86, size: 32, dwarfAddressSpace: 1) +!87 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !86, size: 32, addressSpace: 1) !88 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !89, size: 64) !89 = !DIDerivedType(tag: DW_TAG_typedef, name: "Face", file: !4, line: 1993, baseType: !90) !90 = distinct !DICompositeType(tag: DW_TAG_structure_type, file: !4, line: 1981, size: 640, elements: !91) diff --git a/llvm/test/CodeGen/AMDGPU/disable-dwarf-locations.mir b/llvm/test/CodeGen/AMDGPU/disable-dwarf-locations.mir new file mode 100644 index 0000000000000..9db34d41384f9 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/disable-dwarf-locations.mir @@ -0,0 +1,154 @@ +# RUN: llc -disable-dwarf-locations --mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-after=livedebugvalues %s -filetype=obj -o - | llvm-dwarfdump -a - | FileCheck %s + +# XFAIL: * + +# Check that -disable-dwarf-locations inhibits emitting attributes with +# "simple" and location-list expression types (TODO: add a non-location-list +# "complex" expression), and the accompanying .debug_loc section for +# location-list expressions. +# +# Source variable "x" has a static debug location throughout the function, and +# a simple input expression. +# +# Source variable "y" requires a location-list. + +# CHECK-NOT: DW_AT_frame_base +# CHECK-NOT: DW_AT_location +# CHECK-NOT: .debug_loc + +--- | + define hidden i32 @disable_dwarf_locations(i32 %x) #0 { + entry: + %x.addr = alloca i32, align 4, addrspace(5), !amdgpu.uniform !2 + store i32 %x, i32 addrspace(5)* %x.addr, align 4 + call void @llvm.dbg.declare(metadata i32 addrspace(5)* %x.addr, metadata !14, metadata !DIExpression()) + call void @ex(i32 addrspace(5)* %x.addr) #6 + %0 = load i32, i32 addrspace(5)* %x.addr, align 4 + %and = and i32 %0, 1 + %tobool = icmp ne i32 %and, 0 + %1 = xor i1 %tobool, true + %2 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %1) + %3 = extractvalue { i1, i64 } %2, 0 + %4 = extractvalue { i1, i64 } %2, 1 + br i1 %3, label %if.else, label %if.end + + if.else: ; preds = %entry + %shr = ashr i32 %0, 1 + call void @llvm.dbg.value(metadata i32 %shr, metadata !23, metadata !DIExpression()) + br label %if.end, !amdgpu.uniform !2 + + if.end: ; preds = %if.else, %entry + %y.0 = phi i32 [ %0, %entry ], [ %shr, %if.else ] + call void @llvm.dbg.value(metadata i32 %y.0, metadata !23, metadata !DIExpression()) + ret i32 %y.0 + } + + declare hidden void @ex(i32 addrspace(5)*) #2 + declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + declare { i1, i64 } @llvm.amdgcn.if.i64(i1) #3 + + attributes #0 = { convergent noinline norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+s-memrealtime" "uniform-work-group-size"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #1 = { nounwind readnone speculatable willreturn } + attributes #2 = { convergent "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+s-memrealtime" "uniform-work-group-size"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #3 = { convergent nounwind } + attributes #4 = { convergent nounwind readnone } + attributes #5 = { nounwind } + attributes #6 = { convergent } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!3, !4, !5, !6} + !opencl.ocl.version = !{!7} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) + !1 = !DIFile(filename: "-", directory: "/") + !2 = !{} + !3 = !{i32 7, !"Dwarf Version", i32 4} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = !{i32 1, !"wchar_size", i32 4} + !6 = !{i32 7, !"PIC Level", i32 1} + !7 = !{i32 2, i32 0} + !9 = distinct !DISubprogram(name: "disable_dwarf_locations", scope: !1, file: !1, line: 2, type: !11, scopeLine: 2, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2) + !11 = !DISubroutineType(types: !12) + !12 = !{!13, !13} + !13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) + !14 = !DILocalVariable(name: "x", arg: 1, scope: !9, file: !1, line: 2, type: !13) + !15 = !DILocation(line: 2, column: 33, scope: !9) + !19 = distinct !DILexicalBlock(scope: !9, file: !1, line: 5, column: 9) + !22 = distinct !DILexicalBlock(scope: !19, file: !1, line: 7, column: 12) + !23 = !DILocalVariable(name: "y", scope: !9, file: !1, line: 4, type: !13) + +... +--- +name: disable_dwarf_locations +stack: + - { id: 0, name: x.addr, type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + local-offset: 0, debug-info-variable: '!14', debug-info-expression: '!DIExpression()' } + - { id: 2, name: '', type: spill-slot, offset: 4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '' } + - { id: 3, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, + stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '' } + - { id: 4, name: '', type: default, offset: 8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '' } +body: | + bb.0.entry: + successors: %bb.1(0x40000000) + liveins: $vgpr0, $vgpr40, $sgpr30_sgpr31 + + S_WAITCNT 0 + $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def $scc, implicit $exec + BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, 0, implicit $exec :: (store 4 into %stack.2, addrspace 5) + $exec = S_MOV_B64 killed $sgpr4_sgpr5 + $vgpr40 = V_WRITELANE_B32 $sgpr33, 2, undef $vgpr40 + $sgpr33 = S_MOV_B32 $sgpr32 + $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, undef $vgpr40 + $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, killed $vgpr40 + BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.x.addr, addrspace 5) + $sgpr32 = frame-setup S_ADD_U32 $sgpr32, 1024, implicit-def $scc + renamable $sgpr4 = S_GETREG_B32 30735, + $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec + renamable $sgpr4 = S_LSHL_B32 killed renamable $sgpr4, 16, implicit-def dead $scc, + V_CMP_NE_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec, + $vgpr1 = V_MOV_B32_e32 killed $sgpr4, implicit $exec, implicit $exec, + renamable $vgpr0 = V_CNDMASK_B32_e32 0, killed $vgpr0, implicit $vcc, implicit $exec, + renamable $vgpr1 = V_CNDMASK_B32_e32 0, killed $vgpr1, implicit killed $vcc, implicit $exec, + BUNDLE implicit-def $sgpr4_sgpr5, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $scc { + $sgpr4_sgpr5 = S_GETPC_B64 + $sgpr4 = S_ADD_U32 internal $sgpr4, target-flags(amdgpu-rel32-lo) @ex + 4, implicit-def $scc, + $sgpr5 = S_ADDC_U32 internal $sgpr5, target-flags(amdgpu-rel32-hi) @ex + 4, implicit-def $scc, implicit internal $scc, + } + dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, @ex, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $vgpr0, implicit killed $vgpr1, + renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, 0, implicit $exec, + S_WAITCNT 3952, + renamable $vgpr1 = V_AND_B32_e32 1, $vgpr0, implicit $exec, + V_CMP_EQ_U32_e32 0, killed $vgpr1, implicit-def $vcc, implicit $exec, + $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 killed $vcc, implicit-def $exec, implicit-def $scc, implicit $exec + + bb.1.if.else: + successors: %bb.2(0x80000000) + liveins: $vgpr0, $vgpr40, $sgpr4_sgpr5 + + renamable $vgpr0 = V_ASHRREV_I32_e32 1, killed $vgpr0, implicit $exec, + DBG_VALUE $vgpr0, $noreg, !23, !DIExpression(), debug-location !15 + + bb.2.if.end: + liveins: $vgpr0, $vgpr40, $sgpr4_sgpr5 + + DBG_VALUE $vgpr0, $noreg, !23, !DIExpression(), debug-location !15 + $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc + DBG_VALUE $vgpr0, $noreg, !23, !DIExpression(), debug-location !15 + $sgpr4 = V_READLANE_B32 $vgpr40, 0, implicit-def $sgpr4_sgpr5, + $sgpr5 = V_READLANE_B32 $vgpr40, 1, + $sgpr32 = frame-destroy S_SUB_U32 $sgpr32, 1024, implicit-def $scc + $sgpr33 = V_READLANE_B32 killed $vgpr40, 2 + $sgpr6_sgpr7 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def $scc, implicit $exec + $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, 0, implicit $exec :: (load 4 from %stack.2, addrspace 5) + $exec = S_MOV_B64 killed $sgpr6_sgpr7 + S_WAITCNT 3952, + S_SETPC_B64_return killed renamable $sgpr4_sgpr5, implicit killed $vgpr0, + +... diff --git a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll index 40cdfd76d6af6..f965c2780d610 100644 --- a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll @@ -15,29 +15,1282 @@ define weak_odr void @test(i32 %0) !dbg !34 { ; CHECK-NEXT: .cfi_sections .debug_frame ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; CHECK-NEXT: .cfi_undefined 2560 +; CHECK-NEXT: .cfi_undefined 2561 +; CHECK-NEXT: .cfi_undefined 2562 +; CHECK-NEXT: .cfi_undefined 2563 +; CHECK-NEXT: .cfi_undefined 2564 +; CHECK-NEXT: .cfi_undefined 2565 +; CHECK-NEXT: .cfi_undefined 2566 +; CHECK-NEXT: .cfi_undefined 2567 +; CHECK-NEXT: .cfi_undefined 2568 +; CHECK-NEXT: .cfi_undefined 2569 +; CHECK-NEXT: .cfi_undefined 2570 +; CHECK-NEXT: .cfi_undefined 2571 +; CHECK-NEXT: .cfi_undefined 2572 +; CHECK-NEXT: .cfi_undefined 2573 +; CHECK-NEXT: .cfi_undefined 2574 +; CHECK-NEXT: .cfi_undefined 2575 +; CHECK-NEXT: .cfi_undefined 2576 +; CHECK-NEXT: .cfi_undefined 2577 +; CHECK-NEXT: .cfi_undefined 2578 +; CHECK-NEXT: .cfi_undefined 2579 +; CHECK-NEXT: .cfi_undefined 2580 +; CHECK-NEXT: .cfi_undefined 2581 +; CHECK-NEXT: .cfi_undefined 2582 +; CHECK-NEXT: .cfi_undefined 2583 +; CHECK-NEXT: .cfi_undefined 2584 +; CHECK-NEXT: .cfi_undefined 2585 +; CHECK-NEXT: .cfi_undefined 2586 +; CHECK-NEXT: .cfi_undefined 2587 +; CHECK-NEXT: .cfi_undefined 2588 +; CHECK-NEXT: .cfi_undefined 2589 +; CHECK-NEXT: .cfi_undefined 2590 +; CHECK-NEXT: .cfi_undefined 2591 +; CHECK-NEXT: .cfi_undefined 2592 +; CHECK-NEXT: .cfi_undefined 2593 +; CHECK-NEXT: .cfi_undefined 2594 +; CHECK-NEXT: .cfi_undefined 2595 +; CHECK-NEXT: .cfi_undefined 2596 +; CHECK-NEXT: .cfi_undefined 2597 +; CHECK-NEXT: .cfi_undefined 2598 +; CHECK-NEXT: .cfi_undefined 2599 +; CHECK-NEXT: .cfi_undefined 2608 +; CHECK-NEXT: .cfi_undefined 2609 +; CHECK-NEXT: .cfi_undefined 2610 +; CHECK-NEXT: .cfi_undefined 2611 +; CHECK-NEXT: .cfi_undefined 2612 +; CHECK-NEXT: .cfi_undefined 2613 +; CHECK-NEXT: .cfi_undefined 2614 +; CHECK-NEXT: .cfi_undefined 2615 +; CHECK-NEXT: .cfi_undefined 2624 +; CHECK-NEXT: .cfi_undefined 2625 +; CHECK-NEXT: .cfi_undefined 2626 +; CHECK-NEXT: .cfi_undefined 2627 +; CHECK-NEXT: .cfi_undefined 2628 +; CHECK-NEXT: .cfi_undefined 2629 +; CHECK-NEXT: .cfi_undefined 2630 +; CHECK-NEXT: .cfi_undefined 2631 +; CHECK-NEXT: .cfi_undefined 2640 +; CHECK-NEXT: .cfi_undefined 2641 +; CHECK-NEXT: .cfi_undefined 2642 +; CHECK-NEXT: .cfi_undefined 2643 +; CHECK-NEXT: .cfi_undefined 2644 +; CHECK-NEXT: .cfi_undefined 2645 +; CHECK-NEXT: .cfi_undefined 2646 +; CHECK-NEXT: .cfi_undefined 2647 +; CHECK-NEXT: .cfi_undefined 2656 +; CHECK-NEXT: .cfi_undefined 2657 +; CHECK-NEXT: .cfi_undefined 2658 +; CHECK-NEXT: .cfi_undefined 2659 +; CHECK-NEXT: .cfi_undefined 2660 +; CHECK-NEXT: .cfi_undefined 2661 +; CHECK-NEXT: .cfi_undefined 2662 +; CHECK-NEXT: .cfi_undefined 2663 +; CHECK-NEXT: .cfi_undefined 2672 +; CHECK-NEXT: .cfi_undefined 2673 +; CHECK-NEXT: .cfi_undefined 2674 +; CHECK-NEXT: .cfi_undefined 2675 +; CHECK-NEXT: .cfi_undefined 2676 +; CHECK-NEXT: .cfi_undefined 2677 +; CHECK-NEXT: .cfi_undefined 2678 +; CHECK-NEXT: .cfi_undefined 2679 +; CHECK-NEXT: .cfi_undefined 2688 +; CHECK-NEXT: .cfi_undefined 2689 +; CHECK-NEXT: .cfi_undefined 2690 +; CHECK-NEXT: .cfi_undefined 2691 +; CHECK-NEXT: .cfi_undefined 2692 +; CHECK-NEXT: .cfi_undefined 2693 +; CHECK-NEXT: .cfi_undefined 2694 +; CHECK-NEXT: .cfi_undefined 2695 +; CHECK-NEXT: .cfi_undefined 2704 +; CHECK-NEXT: .cfi_undefined 2705 +; CHECK-NEXT: .cfi_undefined 2706 +; CHECK-NEXT: .cfi_undefined 2707 +; CHECK-NEXT: .cfi_undefined 2708 +; CHECK-NEXT: .cfi_undefined 2709 +; CHECK-NEXT: .cfi_undefined 2710 +; CHECK-NEXT: .cfi_undefined 2711 +; CHECK-NEXT: .cfi_undefined 2720 +; CHECK-NEXT: .cfi_undefined 2721 +; CHECK-NEXT: .cfi_undefined 2722 +; CHECK-NEXT: .cfi_undefined 2723 +; CHECK-NEXT: .cfi_undefined 2724 +; CHECK-NEXT: .cfi_undefined 2725 +; CHECK-NEXT: .cfi_undefined 2726 +; CHECK-NEXT: .cfi_undefined 2727 +; CHECK-NEXT: .cfi_undefined 2736 +; CHECK-NEXT: .cfi_undefined 2737 +; CHECK-NEXT: .cfi_undefined 2738 +; CHECK-NEXT: .cfi_undefined 2739 +; CHECK-NEXT: .cfi_undefined 2740 +; CHECK-NEXT: .cfi_undefined 2741 +; CHECK-NEXT: .cfi_undefined 2742 +; CHECK-NEXT: .cfi_undefined 2743 +; CHECK-NEXT: .cfi_undefined 2752 +; CHECK-NEXT: .cfi_undefined 2753 +; CHECK-NEXT: .cfi_undefined 2754 +; CHECK-NEXT: .cfi_undefined 2755 +; CHECK-NEXT: .cfi_undefined 2756 +; CHECK-NEXT: .cfi_undefined 2757 +; CHECK-NEXT: .cfi_undefined 2758 +; CHECK-NEXT: .cfi_undefined 2759 +; CHECK-NEXT: .cfi_undefined 2768 +; CHECK-NEXT: .cfi_undefined 2769 +; CHECK-NEXT: .cfi_undefined 2770 +; CHECK-NEXT: .cfi_undefined 2771 +; CHECK-NEXT: .cfi_undefined 2772 +; CHECK-NEXT: .cfi_undefined 2773 +; CHECK-NEXT: .cfi_undefined 2774 +; CHECK-NEXT: .cfi_undefined 2775 +; CHECK-NEXT: .cfi_undefined 2784 +; CHECK-NEXT: .cfi_undefined 2785 +; CHECK-NEXT: .cfi_undefined 2786 +; CHECK-NEXT: .cfi_undefined 2787 +; CHECK-NEXT: .cfi_undefined 2788 +; CHECK-NEXT: .cfi_undefined 2789 +; CHECK-NEXT: .cfi_undefined 2790 +; CHECK-NEXT: .cfi_undefined 2791 +; CHECK-NEXT: .cfi_undefined 2800 +; CHECK-NEXT: .cfi_undefined 2801 +; CHECK-NEXT: .cfi_undefined 2802 +; CHECK-NEXT: .cfi_undefined 2803 +; CHECK-NEXT: .cfi_undefined 2804 +; CHECK-NEXT: .cfi_undefined 2805 +; CHECK-NEXT: .cfi_undefined 2806 +; CHECK-NEXT: .cfi_undefined 2807 +; CHECK-NEXT: .cfi_undefined 2816 +; CHECK-NEXT: .cfi_undefined 2817 +; CHECK-NEXT: .cfi_undefined 2818 +; CHECK-NEXT: .cfi_undefined 2819 +; CHECK-NEXT: .cfi_undefined 2820 +; CHECK-NEXT: .cfi_undefined 2821 +; CHECK-NEXT: .cfi_undefined 2822 +; CHECK-NEXT: .cfi_undefined 2823 +; CHECK-NEXT: .cfi_undefined 2824 +; CHECK-NEXT: .cfi_undefined 2825 +; CHECK-NEXT: .cfi_undefined 2826 +; CHECK-NEXT: .cfi_undefined 2827 +; CHECK-NEXT: .cfi_undefined 2828 +; CHECK-NEXT: .cfi_undefined 2829 +; CHECK-NEXT: .cfi_undefined 2830 +; CHECK-NEXT: .cfi_undefined 2831 +; CHECK-NEXT: .cfi_undefined 2832 +; CHECK-NEXT: .cfi_undefined 2833 +; CHECK-NEXT: .cfi_undefined 2834 +; CHECK-NEXT: .cfi_undefined 2835 +; CHECK-NEXT: .cfi_undefined 2836 +; CHECK-NEXT: .cfi_undefined 2837 +; CHECK-NEXT: .cfi_undefined 2838 +; CHECK-NEXT: .cfi_undefined 2839 +; CHECK-NEXT: .cfi_undefined 2840 +; CHECK-NEXT: .cfi_undefined 2841 +; CHECK-NEXT: .cfi_undefined 2842 +; CHECK-NEXT: .cfi_undefined 2843 +; CHECK-NEXT: .cfi_undefined 2844 +; CHECK-NEXT: .cfi_undefined 2845 +; CHECK-NEXT: .cfi_undefined 2846 +; CHECK-NEXT: .cfi_undefined 2847 +; CHECK-NEXT: .cfi_undefined 2848 +; CHECK-NEXT: .cfi_undefined 2849 +; CHECK-NEXT: .cfi_undefined 2850 +; CHECK-NEXT: .cfi_undefined 2851 +; CHECK-NEXT: .cfi_undefined 2852 +; CHECK-NEXT: .cfi_undefined 2853 +; CHECK-NEXT: .cfi_undefined 2854 +; CHECK-NEXT: .cfi_undefined 2855 +; CHECK-NEXT: .cfi_undefined 2856 +; CHECK-NEXT: .cfi_undefined 2857 +; CHECK-NEXT: .cfi_undefined 2858 +; CHECK-NEXT: .cfi_undefined 2859 +; CHECK-NEXT: .cfi_undefined 2860 +; CHECK-NEXT: .cfi_undefined 2861 +; CHECK-NEXT: .cfi_undefined 2862 +; CHECK-NEXT: .cfi_undefined 2863 +; CHECK-NEXT: .cfi_undefined 2864 +; CHECK-NEXT: .cfi_undefined 2865 +; CHECK-NEXT: .cfi_undefined 2866 +; CHECK-NEXT: .cfi_undefined 2867 +; CHECK-NEXT: .cfi_undefined 2868 +; CHECK-NEXT: .cfi_undefined 2869 +; CHECK-NEXT: .cfi_undefined 2870 +; CHECK-NEXT: .cfi_undefined 2871 +; CHECK-NEXT: .cfi_undefined 2872 +; CHECK-NEXT: .cfi_undefined 2873 +; CHECK-NEXT: .cfi_undefined 2874 +; CHECK-NEXT: .cfi_undefined 2875 +; CHECK-NEXT: .cfi_undefined 2876 +; CHECK-NEXT: .cfi_undefined 2877 +; CHECK-NEXT: .cfi_undefined 2878 +; CHECK-NEXT: .cfi_undefined 2879 +; CHECK-NEXT: .cfi_undefined 2880 +; CHECK-NEXT: .cfi_undefined 2881 +; CHECK-NEXT: .cfi_undefined 2882 +; CHECK-NEXT: .cfi_undefined 2883 +; CHECK-NEXT: .cfi_undefined 2884 +; CHECK-NEXT: .cfi_undefined 2885 +; CHECK-NEXT: .cfi_undefined 2886 +; CHECK-NEXT: .cfi_undefined 2887 +; CHECK-NEXT: .cfi_undefined 2888 +; CHECK-NEXT: .cfi_undefined 2889 +; CHECK-NEXT: .cfi_undefined 2890 +; CHECK-NEXT: .cfi_undefined 2891 +; CHECK-NEXT: .cfi_undefined 2892 +; CHECK-NEXT: .cfi_undefined 2893 +; CHECK-NEXT: .cfi_undefined 2894 +; CHECK-NEXT: .cfi_undefined 2895 +; CHECK-NEXT: .cfi_undefined 2896 +; CHECK-NEXT: .cfi_undefined 2897 +; CHECK-NEXT: .cfi_undefined 2898 +; CHECK-NEXT: .cfi_undefined 2899 +; CHECK-NEXT: .cfi_undefined 2900 +; CHECK-NEXT: .cfi_undefined 2901 +; CHECK-NEXT: .cfi_undefined 2902 +; CHECK-NEXT: .cfi_undefined 2903 +; CHECK-NEXT: .cfi_undefined 2904 +; CHECK-NEXT: .cfi_undefined 2905 +; CHECK-NEXT: .cfi_undefined 2906 +; CHECK-NEXT: .cfi_undefined 2907 +; CHECK-NEXT: .cfi_undefined 2908 +; CHECK-NEXT: .cfi_undefined 2909 +; CHECK-NEXT: .cfi_undefined 2910 +; CHECK-NEXT: .cfi_undefined 2911 +; CHECK-NEXT: .cfi_undefined 2912 +; CHECK-NEXT: .cfi_undefined 2913 +; CHECK-NEXT: .cfi_undefined 2914 +; CHECK-NEXT: .cfi_undefined 2915 +; CHECK-NEXT: .cfi_undefined 2916 +; CHECK-NEXT: .cfi_undefined 2917 +; CHECK-NEXT: .cfi_undefined 2918 +; CHECK-NEXT: .cfi_undefined 2919 +; CHECK-NEXT: .cfi_undefined 2920 +; CHECK-NEXT: .cfi_undefined 2921 +; CHECK-NEXT: .cfi_undefined 2922 +; CHECK-NEXT: .cfi_undefined 2923 +; CHECK-NEXT: .cfi_undefined 2924 +; CHECK-NEXT: .cfi_undefined 2925 +; CHECK-NEXT: .cfi_undefined 2926 +; CHECK-NEXT: .cfi_undefined 2927 +; CHECK-NEXT: .cfi_undefined 2928 +; CHECK-NEXT: .cfi_undefined 2929 +; CHECK-NEXT: .cfi_undefined 2930 +; CHECK-NEXT: .cfi_undefined 2931 +; CHECK-NEXT: .cfi_undefined 2932 +; CHECK-NEXT: .cfi_undefined 2933 +; CHECK-NEXT: .cfi_undefined 2934 +; CHECK-NEXT: .cfi_undefined 2935 +; CHECK-NEXT: .cfi_undefined 2936 +; CHECK-NEXT: .cfi_undefined 2937 +; CHECK-NEXT: .cfi_undefined 2938 +; CHECK-NEXT: .cfi_undefined 2939 +; CHECK-NEXT: .cfi_undefined 2940 +; CHECK-NEXT: .cfi_undefined 2941 +; CHECK-NEXT: .cfi_undefined 2942 +; CHECK-NEXT: .cfi_undefined 2943 +; CHECK-NEXT: .cfi_undefined 2944 +; CHECK-NEXT: .cfi_undefined 2945 +; CHECK-NEXT: .cfi_undefined 2946 +; CHECK-NEXT: .cfi_undefined 2947 +; CHECK-NEXT: .cfi_undefined 2948 +; CHECK-NEXT: .cfi_undefined 2949 +; CHECK-NEXT: .cfi_undefined 2950 +; CHECK-NEXT: .cfi_undefined 2951 +; CHECK-NEXT: .cfi_undefined 2952 +; CHECK-NEXT: .cfi_undefined 2953 +; CHECK-NEXT: .cfi_undefined 2954 +; CHECK-NEXT: .cfi_undefined 2955 +; CHECK-NEXT: .cfi_undefined 2956 +; CHECK-NEXT: .cfi_undefined 2957 +; CHECK-NEXT: .cfi_undefined 2958 +; CHECK-NEXT: .cfi_undefined 2959 +; CHECK-NEXT: .cfi_undefined 2960 +; CHECK-NEXT: .cfi_undefined 2961 +; CHECK-NEXT: .cfi_undefined 2962 +; CHECK-NEXT: .cfi_undefined 2963 +; CHECK-NEXT: .cfi_undefined 2964 +; CHECK-NEXT: .cfi_undefined 2965 +; CHECK-NEXT: .cfi_undefined 2966 +; CHECK-NEXT: .cfi_undefined 2967 +; CHECK-NEXT: .cfi_undefined 2968 +; CHECK-NEXT: .cfi_undefined 2969 +; CHECK-NEXT: .cfi_undefined 2970 +; CHECK-NEXT: .cfi_undefined 2971 +; CHECK-NEXT: .cfi_undefined 2972 +; CHECK-NEXT: .cfi_undefined 2973 +; CHECK-NEXT: .cfi_undefined 2974 +; CHECK-NEXT: .cfi_undefined 2975 +; CHECK-NEXT: .cfi_undefined 2976 +; CHECK-NEXT: .cfi_undefined 2977 +; CHECK-NEXT: .cfi_undefined 2978 +; CHECK-NEXT: .cfi_undefined 2979 +; CHECK-NEXT: .cfi_undefined 2980 +; CHECK-NEXT: .cfi_undefined 2981 +; CHECK-NEXT: .cfi_undefined 2982 +; CHECK-NEXT: .cfi_undefined 2983 +; CHECK-NEXT: .cfi_undefined 2984 +; CHECK-NEXT: .cfi_undefined 2985 +; CHECK-NEXT: .cfi_undefined 2986 +; CHECK-NEXT: .cfi_undefined 2987 +; CHECK-NEXT: .cfi_undefined 2988 +; CHECK-NEXT: .cfi_undefined 2989 +; CHECK-NEXT: .cfi_undefined 2990 +; CHECK-NEXT: .cfi_undefined 2991 +; CHECK-NEXT: .cfi_undefined 2992 +; CHECK-NEXT: .cfi_undefined 2993 +; CHECK-NEXT: .cfi_undefined 2994 +; CHECK-NEXT: .cfi_undefined 2995 +; CHECK-NEXT: .cfi_undefined 2996 +; CHECK-NEXT: .cfi_undefined 2997 +; CHECK-NEXT: .cfi_undefined 2998 +; CHECK-NEXT: .cfi_undefined 2999 +; CHECK-NEXT: .cfi_undefined 3000 +; CHECK-NEXT: .cfi_undefined 3001 +; CHECK-NEXT: .cfi_undefined 3002 +; CHECK-NEXT: .cfi_undefined 3003 +; CHECK-NEXT: .cfi_undefined 3004 +; CHECK-NEXT: .cfi_undefined 3005 +; CHECK-NEXT: .cfi_undefined 3006 +; CHECK-NEXT: .cfi_undefined 3007 +; CHECK-NEXT: .cfi_undefined 3008 +; CHECK-NEXT: .cfi_undefined 3009 +; CHECK-NEXT: .cfi_undefined 3010 +; CHECK-NEXT: .cfi_undefined 3011 +; CHECK-NEXT: .cfi_undefined 3012 +; CHECK-NEXT: .cfi_undefined 3013 +; CHECK-NEXT: .cfi_undefined 3014 +; CHECK-NEXT: .cfi_undefined 3015 +; CHECK-NEXT: .cfi_undefined 3016 +; CHECK-NEXT: .cfi_undefined 3017 +; CHECK-NEXT: .cfi_undefined 3018 +; CHECK-NEXT: .cfi_undefined 3019 +; CHECK-NEXT: .cfi_undefined 3020 +; CHECK-NEXT: .cfi_undefined 3021 +; CHECK-NEXT: .cfi_undefined 3022 +; CHECK-NEXT: .cfi_undefined 3023 +; CHECK-NEXT: .cfi_undefined 3024 +; CHECK-NEXT: .cfi_undefined 3025 +; CHECK-NEXT: .cfi_undefined 3026 +; CHECK-NEXT: .cfi_undefined 3027 +; CHECK-NEXT: .cfi_undefined 3028 +; CHECK-NEXT: .cfi_undefined 3029 +; CHECK-NEXT: .cfi_undefined 3030 +; CHECK-NEXT: .cfi_undefined 3031 +; CHECK-NEXT: .cfi_undefined 3032 +; CHECK-NEXT: .cfi_undefined 3033 +; CHECK-NEXT: .cfi_undefined 3034 +; CHECK-NEXT: .cfi_undefined 3035 +; CHECK-NEXT: .cfi_undefined 3036 +; CHECK-NEXT: .cfi_undefined 3037 +; CHECK-NEXT: .cfi_undefined 3038 +; CHECK-NEXT: .cfi_undefined 3039 +; CHECK-NEXT: .cfi_undefined 3040 +; CHECK-NEXT: .cfi_undefined 3041 +; CHECK-NEXT: .cfi_undefined 3042 +; CHECK-NEXT: .cfi_undefined 3043 +; CHECK-NEXT: .cfi_undefined 3044 +; CHECK-NEXT: .cfi_undefined 3045 +; CHECK-NEXT: .cfi_undefined 3046 +; CHECK-NEXT: .cfi_undefined 3047 +; CHECK-NEXT: .cfi_undefined 3048 +; CHECK-NEXT: .cfi_undefined 3049 +; CHECK-NEXT: .cfi_undefined 3050 +; CHECK-NEXT: .cfi_undefined 3051 +; CHECK-NEXT: .cfi_undefined 3052 +; CHECK-NEXT: .cfi_undefined 3053 +; CHECK-NEXT: .cfi_undefined 3054 +; CHECK-NEXT: .cfi_undefined 3055 +; CHECK-NEXT: .cfi_undefined 3056 +; CHECK-NEXT: .cfi_undefined 3057 +; CHECK-NEXT: .cfi_undefined 3058 +; CHECK-NEXT: .cfi_undefined 3059 +; CHECK-NEXT: .cfi_undefined 3060 +; CHECK-NEXT: .cfi_undefined 3061 +; CHECK-NEXT: .cfi_undefined 3062 +; CHECK-NEXT: .cfi_undefined 3063 +; CHECK-NEXT: .cfi_undefined 3064 +; CHECK-NEXT: .cfi_undefined 3065 +; CHECK-NEXT: .cfi_undefined 3066 +; CHECK-NEXT: .cfi_undefined 3067 +; CHECK-NEXT: .cfi_undefined 3068 +; CHECK-NEXT: .cfi_undefined 3069 +; CHECK-NEXT: .cfi_undefined 3070 +; CHECK-NEXT: .cfi_undefined 3071 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 3072 +; CHECK-NEXT: .cfi_undefined 3073 +; CHECK-NEXT: .cfi_undefined 3074 +; CHECK-NEXT: .cfi_undefined 3075 +; CHECK-NEXT: .cfi_undefined 3076 +; CHECK-NEXT: .cfi_undefined 3077 +; CHECK-NEXT: .cfi_undefined 3078 +; CHECK-NEXT: .cfi_undefined 3079 +; CHECK-NEXT: .cfi_undefined 3080 +; CHECK-NEXT: .cfi_undefined 3081 +; CHECK-NEXT: .cfi_undefined 3082 +; CHECK-NEXT: .cfi_undefined 3083 +; CHECK-NEXT: .cfi_undefined 3084 +; CHECK-NEXT: .cfi_undefined 3085 +; CHECK-NEXT: .cfi_undefined 3086 +; CHECK-NEXT: .cfi_undefined 3087 +; CHECK-NEXT: .cfi_undefined 3088 +; CHECK-NEXT: .cfi_undefined 3089 +; CHECK-NEXT: .cfi_undefined 3090 +; CHECK-NEXT: .cfi_undefined 3091 +; CHECK-NEXT: .cfi_undefined 3092 +; CHECK-NEXT: .cfi_undefined 3093 +; CHECK-NEXT: .cfi_undefined 3094 +; CHECK-NEXT: .cfi_undefined 3095 +; CHECK-NEXT: .cfi_undefined 3096 +; CHECK-NEXT: .cfi_undefined 3097 +; CHECK-NEXT: .cfi_undefined 3098 +; CHECK-NEXT: .cfi_undefined 3099 +; CHECK-NEXT: .cfi_undefined 3100 +; CHECK-NEXT: .cfi_undefined 3101 +; CHECK-NEXT: .cfi_undefined 3102 +; CHECK-NEXT: .cfi_undefined 3103 +; CHECK-NEXT: .cfi_undefined 3104 +; CHECK-NEXT: .cfi_undefined 3105 +; CHECK-NEXT: .cfi_undefined 3106 +; CHECK-NEXT: .cfi_undefined 3107 +; CHECK-NEXT: .cfi_undefined 3108 +; CHECK-NEXT: .cfi_undefined 3109 +; CHECK-NEXT: .cfi_undefined 3110 +; CHECK-NEXT: .cfi_undefined 3111 +; CHECK-NEXT: .cfi_undefined 3112 +; CHECK-NEXT: .cfi_undefined 3113 +; CHECK-NEXT: .cfi_undefined 3114 +; CHECK-NEXT: .cfi_undefined 3115 +; CHECK-NEXT: .cfi_undefined 3116 +; CHECK-NEXT: .cfi_undefined 3117 +; CHECK-NEXT: .cfi_undefined 3118 +; CHECK-NEXT: .cfi_undefined 3119 +; CHECK-NEXT: .cfi_undefined 3120 +; CHECK-NEXT: .cfi_undefined 3121 +; CHECK-NEXT: .cfi_undefined 3122 +; CHECK-NEXT: .cfi_undefined 3123 +; CHECK-NEXT: .cfi_undefined 3124 +; CHECK-NEXT: .cfi_undefined 3125 +; CHECK-NEXT: .cfi_undefined 3126 +; CHECK-NEXT: .cfi_undefined 3127 +; CHECK-NEXT: .cfi_undefined 3128 +; CHECK-NEXT: .cfi_undefined 3129 +; CHECK-NEXT: .cfi_undefined 3130 +; CHECK-NEXT: .cfi_undefined 3131 +; CHECK-NEXT: .cfi_undefined 3132 +; CHECK-NEXT: .cfi_undefined 3133 +; CHECK-NEXT: .cfi_undefined 3134 +; CHECK-NEXT: .cfi_undefined 3135 +; CHECK-NEXT: .cfi_undefined 3136 +; CHECK-NEXT: .cfi_undefined 3137 +; CHECK-NEXT: .cfi_undefined 3138 +; CHECK-NEXT: .cfi_undefined 3139 +; CHECK-NEXT: .cfi_undefined 3140 +; CHECK-NEXT: .cfi_undefined 3141 +; CHECK-NEXT: .cfi_undefined 3142 +; CHECK-NEXT: .cfi_undefined 3143 +; CHECK-NEXT: .cfi_undefined 3144 +; CHECK-NEXT: .cfi_undefined 3145 +; CHECK-NEXT: .cfi_undefined 3146 +; CHECK-NEXT: .cfi_undefined 3147 +; CHECK-NEXT: .cfi_undefined 3148 +; CHECK-NEXT: .cfi_undefined 3149 +; CHECK-NEXT: .cfi_undefined 3150 +; CHECK-NEXT: .cfi_undefined 3151 +; CHECK-NEXT: .cfi_undefined 3152 +; CHECK-NEXT: .cfi_undefined 3153 +; CHECK-NEXT: .cfi_undefined 3154 +; CHECK-NEXT: .cfi_undefined 3155 +; CHECK-NEXT: .cfi_undefined 3156 +; CHECK-NEXT: .cfi_undefined 3157 +; CHECK-NEXT: .cfi_undefined 3158 +; CHECK-NEXT: .cfi_undefined 3159 +; CHECK-NEXT: .cfi_undefined 3160 +; CHECK-NEXT: .cfi_undefined 3161 +; CHECK-NEXT: .cfi_undefined 3162 +; CHECK-NEXT: .cfi_undefined 3163 +; CHECK-NEXT: .cfi_undefined 3164 +; CHECK-NEXT: .cfi_undefined 3165 +; CHECK-NEXT: .cfi_undefined 3166 +; CHECK-NEXT: .cfi_undefined 3167 +; CHECK-NEXT: .cfi_undefined 3168 +; CHECK-NEXT: .cfi_undefined 3169 +; CHECK-NEXT: .cfi_undefined 3170 +; CHECK-NEXT: .cfi_undefined 3171 +; CHECK-NEXT: .cfi_undefined 3172 +; CHECK-NEXT: .cfi_undefined 3173 +; CHECK-NEXT: .cfi_undefined 3174 +; CHECK-NEXT: .cfi_undefined 3175 +; CHECK-NEXT: .cfi_undefined 3176 +; CHECK-NEXT: .cfi_undefined 3177 +; CHECK-NEXT: .cfi_undefined 3178 +; CHECK-NEXT: .cfi_undefined 3179 +; CHECK-NEXT: .cfi_undefined 3180 +; CHECK-NEXT: .cfi_undefined 3181 +; CHECK-NEXT: .cfi_undefined 3182 +; CHECK-NEXT: .cfi_undefined 3183 +; CHECK-NEXT: .cfi_undefined 3184 +; CHECK-NEXT: .cfi_undefined 3185 +; CHECK-NEXT: .cfi_undefined 3186 +; CHECK-NEXT: .cfi_undefined 3187 +; CHECK-NEXT: .cfi_undefined 3188 +; CHECK-NEXT: .cfi_undefined 3189 +; CHECK-NEXT: .cfi_undefined 3190 +; CHECK-NEXT: .cfi_undefined 3191 +; CHECK-NEXT: .cfi_undefined 3192 +; CHECK-NEXT: .cfi_undefined 3193 +; CHECK-NEXT: .cfi_undefined 3194 +; CHECK-NEXT: .cfi_undefined 3195 +; CHECK-NEXT: .cfi_undefined 3196 +; CHECK-NEXT: .cfi_undefined 3197 +; CHECK-NEXT: .cfi_undefined 3198 +; CHECK-NEXT: .cfi_undefined 3199 +; CHECK-NEXT: .cfi_undefined 3200 +; CHECK-NEXT: .cfi_undefined 3201 +; CHECK-NEXT: .cfi_undefined 3202 +; CHECK-NEXT: .cfi_undefined 3203 +; CHECK-NEXT: .cfi_undefined 3204 +; CHECK-NEXT: .cfi_undefined 3205 +; CHECK-NEXT: .cfi_undefined 3206 +; CHECK-NEXT: .cfi_undefined 3207 +; CHECK-NEXT: .cfi_undefined 3208 +; CHECK-NEXT: .cfi_undefined 3209 +; CHECK-NEXT: .cfi_undefined 3210 +; CHECK-NEXT: .cfi_undefined 3211 +; CHECK-NEXT: .cfi_undefined 3212 +; CHECK-NEXT: .cfi_undefined 3213 +; CHECK-NEXT: .cfi_undefined 3214 +; CHECK-NEXT: .cfi_undefined 3215 +; CHECK-NEXT: .cfi_undefined 3216 +; CHECK-NEXT: .cfi_undefined 3217 +; CHECK-NEXT: .cfi_undefined 3218 +; CHECK-NEXT: .cfi_undefined 3219 +; CHECK-NEXT: .cfi_undefined 3220 +; CHECK-NEXT: .cfi_undefined 3221 +; CHECK-NEXT: .cfi_undefined 3222 +; CHECK-NEXT: .cfi_undefined 3223 +; CHECK-NEXT: .cfi_undefined 3224 +; CHECK-NEXT: .cfi_undefined 3225 +; CHECK-NEXT: .cfi_undefined 3226 +; CHECK-NEXT: .cfi_undefined 3227 +; CHECK-NEXT: .cfi_undefined 3228 +; CHECK-NEXT: .cfi_undefined 3229 +; CHECK-NEXT: .cfi_undefined 3230 +; CHECK-NEXT: .cfi_undefined 3231 +; CHECK-NEXT: .cfi_undefined 3232 +; CHECK-NEXT: .cfi_undefined 3233 +; CHECK-NEXT: .cfi_undefined 3234 +; CHECK-NEXT: .cfi_undefined 3235 +; CHECK-NEXT: .cfi_undefined 3236 +; CHECK-NEXT: .cfi_undefined 3237 +; CHECK-NEXT: .cfi_undefined 3238 +; CHECK-NEXT: .cfi_undefined 3239 +; CHECK-NEXT: .cfi_undefined 3240 +; CHECK-NEXT: .cfi_undefined 3241 +; CHECK-NEXT: .cfi_undefined 3242 +; CHECK-NEXT: .cfi_undefined 3243 +; CHECK-NEXT: .cfi_undefined 3244 +; CHECK-NEXT: .cfi_undefined 3245 +; CHECK-NEXT: .cfi_undefined 3246 +; CHECK-NEXT: .cfi_undefined 3247 +; CHECK-NEXT: .cfi_undefined 3248 +; CHECK-NEXT: .cfi_undefined 3249 +; CHECK-NEXT: .cfi_undefined 3250 +; CHECK-NEXT: .cfi_undefined 3251 +; CHECK-NEXT: .cfi_undefined 3252 +; CHECK-NEXT: .cfi_undefined 3253 +; CHECK-NEXT: .cfi_undefined 3254 +; CHECK-NEXT: .cfi_undefined 3255 +; CHECK-NEXT: .cfi_undefined 3256 +; CHECK-NEXT: .cfi_undefined 3257 +; CHECK-NEXT: .cfi_undefined 3258 +; CHECK-NEXT: .cfi_undefined 3259 +; CHECK-NEXT: .cfi_undefined 3260 +; CHECK-NEXT: .cfi_undefined 3261 +; CHECK-NEXT: .cfi_undefined 3262 +; CHECK-NEXT: .cfi_undefined 3263 +; CHECK-NEXT: .cfi_undefined 3264 +; CHECK-NEXT: .cfi_undefined 3265 +; CHECK-NEXT: .cfi_undefined 3266 +; CHECK-NEXT: .cfi_undefined 3267 +; CHECK-NEXT: .cfi_undefined 3268 +; CHECK-NEXT: .cfi_undefined 3269 +; CHECK-NEXT: .cfi_undefined 3270 +; CHECK-NEXT: .cfi_undefined 3271 +; CHECK-NEXT: .cfi_undefined 3272 +; CHECK-NEXT: .cfi_undefined 3273 +; CHECK-NEXT: .cfi_undefined 3274 +; CHECK-NEXT: .cfi_undefined 3275 +; CHECK-NEXT: .cfi_undefined 3276 +; CHECK-NEXT: .cfi_undefined 3277 +; CHECK-NEXT: .cfi_undefined 3278 +; CHECK-NEXT: .cfi_undefined 3279 +; CHECK-NEXT: .cfi_undefined 3280 +; CHECK-NEXT: .cfi_undefined 3281 +; CHECK-NEXT: .cfi_undefined 3282 +; CHECK-NEXT: .cfi_undefined 3283 +; CHECK-NEXT: .cfi_undefined 3284 +; CHECK-NEXT: .cfi_undefined 3285 +; CHECK-NEXT: .cfi_undefined 3286 +; CHECK-NEXT: .cfi_undefined 3287 +; CHECK-NEXT: .cfi_undefined 3288 +; CHECK-NEXT: .cfi_undefined 3289 +; CHECK-NEXT: .cfi_undefined 3290 +; CHECK-NEXT: .cfi_undefined 3291 +; CHECK-NEXT: .cfi_undefined 3292 +; CHECK-NEXT: .cfi_undefined 3293 +; CHECK-NEXT: .cfi_undefined 3294 +; CHECK-NEXT: .cfi_undefined 3295 +; CHECK-NEXT: .cfi_undefined 3296 +; CHECK-NEXT: .cfi_undefined 3297 +; CHECK-NEXT: .cfi_undefined 3298 +; CHECK-NEXT: .cfi_undefined 3299 +; CHECK-NEXT: .cfi_undefined 3300 +; CHECK-NEXT: .cfi_undefined 3301 +; CHECK-NEXT: .cfi_undefined 3302 +; CHECK-NEXT: .cfi_undefined 3303 +; CHECK-NEXT: .cfi_undefined 3304 +; CHECK-NEXT: .cfi_undefined 3305 +; CHECK-NEXT: .cfi_undefined 3306 +; CHECK-NEXT: .cfi_undefined 3307 +; CHECK-NEXT: .cfi_undefined 3308 +; CHECK-NEXT: .cfi_undefined 3309 +; CHECK-NEXT: .cfi_undefined 3310 +; CHECK-NEXT: .cfi_undefined 3311 +; CHECK-NEXT: .cfi_undefined 3312 +; CHECK-NEXT: .cfi_undefined 3313 +; CHECK-NEXT: .cfi_undefined 3314 +; CHECK-NEXT: .cfi_undefined 3315 +; CHECK-NEXT: .cfi_undefined 3316 +; CHECK-NEXT: .cfi_undefined 3317 +; CHECK-NEXT: .cfi_undefined 3318 +; CHECK-NEXT: .cfi_undefined 3319 +; CHECK-NEXT: .cfi_undefined 3320 +; CHECK-NEXT: .cfi_undefined 3321 +; CHECK-NEXT: .cfi_undefined 3322 +; CHECK-NEXT: .cfi_undefined 3323 +; CHECK-NEXT: .cfi_undefined 3324 +; CHECK-NEXT: .cfi_undefined 3325 +; CHECK-NEXT: .cfi_undefined 3326 +; CHECK-NEXT: .cfi_undefined 3327 +; CHECK-NEXT: .cfi_undefined 32 +; CHECK-NEXT: .cfi_undefined 33 +; CHECK-NEXT: .cfi_undefined 34 +; CHECK-NEXT: .cfi_undefined 35 +; CHECK-NEXT: .cfi_undefined 36 +; CHECK-NEXT: .cfi_undefined 37 +; CHECK-NEXT: .cfi_undefined 38 +; CHECK-NEXT: .cfi_undefined 39 +; CHECK-NEXT: .cfi_undefined 40 +; CHECK-NEXT: .cfi_undefined 41 +; CHECK-NEXT: .cfi_undefined 42 +; CHECK-NEXT: .cfi_undefined 43 +; CHECK-NEXT: .cfi_undefined 44 +; CHECK-NEXT: .cfi_undefined 45 +; CHECK-NEXT: .cfi_undefined 46 +; CHECK-NEXT: .cfi_undefined 47 +; CHECK-NEXT: .cfi_undefined 48 +; CHECK-NEXT: .cfi_undefined 49 +; CHECK-NEXT: .cfi_undefined 50 +; CHECK-NEXT: .cfi_undefined 51 +; CHECK-NEXT: .cfi_undefined 52 +; CHECK-NEXT: .cfi_undefined 53 +; CHECK-NEXT: .cfi_undefined 54 +; CHECK-NEXT: .cfi_undefined 55 +; CHECK-NEXT: .cfi_undefined 56 +; CHECK-NEXT: .cfi_undefined 57 +; CHECK-NEXT: .cfi_undefined 58 +; CHECK-NEXT: .cfi_undefined 59 +; CHECK-NEXT: .cfi_undefined 60 +; CHECK-NEXT: .cfi_undefined 61 +; CHECK-NEXT: .cfi_undefined 72 +; CHECK-NEXT: .cfi_undefined 73 +; CHECK-NEXT: .cfi_undefined 74 +; CHECK-NEXT: .cfi_undefined 75 +; CHECK-NEXT: .cfi_undefined 76 +; CHECK-NEXT: .cfi_undefined 77 +; CHECK-NEXT: .cfi_undefined 78 +; CHECK-NEXT: .cfi_undefined 79 +; CHECK-NEXT: .cfi_undefined 88 +; CHECK-NEXT: .cfi_undefined 89 +; CHECK-NEXT: .cfi_undefined 90 +; CHECK-NEXT: .cfi_undefined 91 +; CHECK-NEXT: .cfi_undefined 92 +; CHECK-NEXT: .cfi_undefined 93 +; CHECK-NEXT: .cfi_undefined 94 +; CHECK-NEXT: .cfi_undefined 95 +; CHECK-NEXT: .cfi_undefined 1096 +; CHECK-NEXT: .cfi_undefined 1097 +; CHECK-NEXT: .cfi_undefined 1098 +; CHECK-NEXT: .cfi_undefined 1099 +; CHECK-NEXT: .cfi_undefined 1100 +; CHECK-NEXT: .cfi_undefined 1101 +; CHECK-NEXT: .cfi_undefined 1102 +; CHECK-NEXT: .cfi_undefined 1103 +; CHECK-NEXT: .cfi_undefined 1112 +; CHECK-NEXT: .cfi_undefined 1113 +; CHECK-NEXT: .cfi_undefined 1114 +; CHECK-NEXT: .cfi_undefined 1115 +; CHECK-NEXT: .cfi_undefined 1116 +; CHECK-NEXT: .cfi_undefined 1117 +; CHECK-NEXT: .cfi_undefined 1118 +; CHECK-NEXT: .cfi_undefined 1119 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_mov_b32 s16, s33 ; CHECK-NEXT: s_mov_b32 s33, s32 ; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1 ; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset 2601, 256 ; CHECK-NEXT: s_mov_b64 exec, s[18:19] ; CHECK-NEXT: v_writelane_b32 v41, s16, 16 -; CHECK-NEXT: v_writelane_b32 v41, s30, 0 -; CHECK-NEXT: v_writelane_b32 v41, s31, 1 -; CHECK-NEXT: v_writelane_b32 v41, s34, 2 -; CHECK-NEXT: v_writelane_b32 v41, s35, 3 -; CHECK-NEXT: v_writelane_b32 v41, s36, 4 -; CHECK-NEXT: v_writelane_b32 v41, s37, 5 -; CHECK-NEXT: v_writelane_b32 v41, s38, 6 -; CHECK-NEXT: v_writelane_b32 v41, s39, 7 -; CHECK-NEXT: v_writelane_b32 v41, s48, 8 -; CHECK-NEXT: v_writelane_b32 v41, s49, 9 -; CHECK-NEXT: v_writelane_b32 v41, s50, 10 -; CHECK-NEXT: v_writelane_b32 v41, s51, 11 -; CHECK-NEXT: v_writelane_b32 v41, s52, 12 +; CHECK-NEXT: .cfi_llvm_vector_registers 65, 2601, 16, 32 +; CHECK-NEXT: .cfi_def_cfa_register 65 ; CHECK-NEXT: s_addk_i32 s32, 0x400 -; CHECK-NEXT: v_writelane_b32 v41, s53, 13 -; CHECK-NEXT: v_writelane_b32 v41, s54, 14 +; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; CHECK-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 0 +; CHECK-NEXT: v_writelane_b32 v41, s34, 0 +; CHECK-NEXT: .cfi_llvm_vector_registers 66, 2601, 0, 32 +; CHECK-NEXT: v_writelane_b32 v41, s35, 1 +; CHECK-NEXT: .cfi_llvm_vector_registers 67, 2601, 1, 32 +; CHECK-NEXT: v_writelane_b32 v41, s36, 2 +; CHECK-NEXT: .cfi_llvm_vector_registers 68, 2601, 2, 32 +; CHECK-NEXT: v_writelane_b32 v41, s37, 3 +; CHECK-NEXT: .cfi_llvm_vector_registers 69, 2601, 3, 32 +; CHECK-NEXT: v_writelane_b32 v41, s38, 4 +; CHECK-NEXT: .cfi_llvm_vector_registers 70, 2601, 4, 32 +; CHECK-NEXT: v_writelane_b32 v41, s39, 5 +; CHECK-NEXT: .cfi_llvm_vector_registers 71, 2601, 5, 32 +; CHECK-NEXT: v_writelane_b32 v41, s48, 6 +; CHECK-NEXT: .cfi_llvm_vector_registers 80, 2601, 6, 32 +; CHECK-NEXT: v_writelane_b32 v41, s49, 7 +; CHECK-NEXT: .cfi_llvm_vector_registers 81, 2601, 7, 32 +; CHECK-NEXT: v_writelane_b32 v41, s50, 8 +; CHECK-NEXT: .cfi_llvm_vector_registers 82, 2601, 8, 32 +; CHECK-NEXT: v_writelane_b32 v41, s51, 9 +; CHECK-NEXT: .cfi_llvm_vector_registers 83, 2601, 9, 32 +; CHECK-NEXT: v_writelane_b32 v41, s52, 10 +; CHECK-NEXT: .cfi_llvm_vector_registers 84, 2601, 10, 32 +; CHECK-NEXT: v_writelane_b32 v41, s53, 11 +; CHECK-NEXT: .cfi_llvm_vector_registers 85, 2601, 11, 32 +; CHECK-NEXT: v_writelane_b32 v41, s54, 12 +; CHECK-NEXT: .cfi_llvm_vector_registers 86, 2601, 12, 32 +; CHECK-NEXT: v_writelane_b32 v41, s55, 13 +; CHECK-NEXT: .cfi_llvm_vector_registers 87, 2601, 13, 32 +; CHECK-NEXT: v_writelane_b32 v41, s30, 14 +; CHECK-NEXT: v_writelane_b32 v41, s31, 15 +; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2601, 14, 32, 2601, 15, 32 ; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5] ; CHECK-NEXT: ;DEBUG_VALUE: dummy:dummy <- undef ; CHECK-NEXT: .Ltmp0: @@ -45,10 +1298,8 @@ define weak_odr void @test(i32 %0) !dbg !34 { ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_add_u32 s4, s4, __kmpc_alloc_shared@gotpcrel32@lo+4 ; CHECK-NEXT: s_addc_u32 s5, s5, __kmpc_alloc_shared@gotpcrel32@hi+12 -; CHECK-NEXT: v_writelane_b32 v41, s55, 15 ; CHECK-NEXT: s_load_dwordx2 s[54:55], s[4:5], 0x0 ; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49] -; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CHECK-NEXT: v_mov_b32_e32 v40, v31 ; CHECK-NEXT: s_mov_b32 s50, s15 ; CHECK-NEXT: s_mov_b32 s51, s14 @@ -70,32 +1321,33 @@ define weak_odr void @test(i32 %0) !dbg !34 { ; CHECK-NEXT: v_mov_b32_e32 v31, v40 ; CHECK-NEXT: s_swappc_b64 s[30:31], s[54:55] ; CHECK-NEXT: .Ltmp1: -; CHECK-NEXT: ;DEBUG_VALUE: dummy:dummy <- [$vgpr0_vgpr1+0] +; CHECK-NEXT: ;DEBUG_VALUE: dummy:dummy <- [DW_OP_deref] undef ; CHECK-NEXT: .loc 1 0 9 is_stmt 0 ; dummy:0:9 ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: v_mov_b32_e32 v2, 0 +; CHECK-NEXT: v_readlane_b32 s30, v41, 14 ; CHECK-NEXT: flat_store_dword v[0:1], v2 -; CHECK-NEXT: v_readlane_b32 s55, v41, 15 -; CHECK-NEXT: v_readlane_b32 s54, v41, 14 -; CHECK-NEXT: v_readlane_b32 s53, v41, 13 -; CHECK-NEXT: v_readlane_b32 s52, v41, 12 -; CHECK-NEXT: v_readlane_b32 s51, v41, 11 -; CHECK-NEXT: v_readlane_b32 s50, v41, 10 -; CHECK-NEXT: v_readlane_b32 s49, v41, 9 -; CHECK-NEXT: v_readlane_b32 s48, v41, 8 -; CHECK-NEXT: v_readlane_b32 s39, v41, 7 -; CHECK-NEXT: v_readlane_b32 s38, v41, 6 -; CHECK-NEXT: v_readlane_b32 s37, v41, 5 -; CHECK-NEXT: v_readlane_b32 s36, v41, 4 -; CHECK-NEXT: v_readlane_b32 s35, v41, 3 -; CHECK-NEXT: v_readlane_b32 s34, v41, 2 -; CHECK-NEXT: v_readlane_b32 s31, v41, 1 -; CHECK-NEXT: v_readlane_b32 s30, v41, 0 +; CHECK-NEXT: v_readlane_b32 s31, v41, 15 +; CHECK-NEXT: v_readlane_b32 s55, v41, 13 +; CHECK-NEXT: v_readlane_b32 s54, v41, 12 +; CHECK-NEXT: v_readlane_b32 s53, v41, 11 +; CHECK-NEXT: v_readlane_b32 s52, v41, 10 +; CHECK-NEXT: v_readlane_b32 s51, v41, 9 +; CHECK-NEXT: v_readlane_b32 s50, v41, 8 +; CHECK-NEXT: v_readlane_b32 s49, v41, 7 +; CHECK-NEXT: v_readlane_b32 s48, v41, 6 +; CHECK-NEXT: v_readlane_b32 s39, v41, 5 +; CHECK-NEXT: v_readlane_b32 s38, v41, 4 +; CHECK-NEXT: v_readlane_b32 s37, v41, 3 +; CHECK-NEXT: v_readlane_b32 s36, v41, 2 +; CHECK-NEXT: v_readlane_b32 s35, v41, 1 +; CHECK-NEXT: v_readlane_b32 s34, v41, 0 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: v_readlane_b32 s4, v41, 16 ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1 ; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; CHECK-NEXT: s_mov_b64 exec, s[6:7] +; CHECK-NEXT: .cfi_def_cfa_register 64 ; CHECK-NEXT: s_mov_b32 s33, s4 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll index bcccf50e3805c..a3863156b8d34 100644 --- a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll +++ b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll @@ -286,21 +286,20 @@ define amdgpu_gfx void @amdgpu_gfx() #0 { ; CHECK-TRUE16-NEXT: s_wait_alu 0xfffe ; CHECK-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; CHECK-TRUE16-NEXT: s_add_co_i32 s32, s32, 16 +; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15 ; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee@abs32@hi ; CHECK-TRUE16-NEXT: s_mov_b32 s0, callee@abs32@lo -; CHECK-TRUE16-NEXT: s_add_co_i32 s32, s32, 16 -; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0 ; CHECK-TRUE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS ; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0 ; CHECK-TRUE16-NEXT: v_mov_b32_e32 v0, 0x47 -; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; CHECK-TRUE16-NEXT: s_wait_alu 0xfffe ; CHECK-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; CHECK-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; CHECK-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; CHECK-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; CHECK-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; CHECK-TRUE16-NEXT: s_mov_b32 s32, s33 ; CHECK-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; CHECK-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -326,21 +325,20 @@ define amdgpu_gfx void @amdgpu_gfx() #0 { ; CHECK-FAKE16-NEXT: s_wait_alu 0xfffe ; CHECK-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; CHECK-FAKE16-NEXT: s_add_co_i32 s32, s32, 16 +; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15 ; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee@abs32@hi ; CHECK-FAKE16-NEXT: s_mov_b32 s0, callee@abs32@lo -; CHECK-FAKE16-NEXT: s_add_co_i32 s32, s32, 16 -; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0 ; CHECK-FAKE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS ; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0 ; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 0x47 -; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; CHECK-FAKE16-NEXT: s_wait_alu 0xfffe ; CHECK-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; CHECK-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; CHECK-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; CHECK-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; CHECK-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; CHECK-FAKE16-NEXT: s_mov_b32 s32, s33 ; CHECK-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; CHECK-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 diff --git a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll index c5db7a33f70e0..ed767aeaf112f 100644 --- a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll @@ -1049,12 +1049,12 @@ define void @test_dynamic_stackalloc_device_uniform(i32 %n) { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_uniform: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1078,12 +1078,12 @@ define void @test_dynamic_stackalloc_device_uniform(i32 %n) { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_uniform: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1107,13 +1107,14 @@ define void @test_dynamic_stackalloc_device_uniform(i32 %n) { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_uniform: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-SDAG-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1136,13 +1137,14 @@ define void @test_dynamic_stackalloc_device_uniform(i32 %n) { ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_uniform: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1171,15 +1173,15 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0x1fc0 ; GFX9-SDAG-NEXT: s_mov_b32 s10, s34 +; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 -; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xffffe000 -; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x4000 ; GFX9-SDAG-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1205,15 +1207,15 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0x1fc0 ; GFX9-GISEL-NEXT: s_mov_b32 s10, s34 +; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 -; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xffffe000 -; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x4000 ; GFX9-GISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1239,19 +1241,20 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 ; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 0x7f ; GFX11-SDAG-NEXT: s_mov_b32 s5, s34 -; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 -; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 ; GFX11-SDAG-NEXT: s_and_b32 s33, s33, 0xffffff80 ; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 ; GFX11-SDAG-NEXT: s_addk_i32 s32, 0x100 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-SDAG-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 -; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 ; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 ; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 @@ -1261,31 +1264,33 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { ; GFX11-SDAG-NEXT: s_add_i32 s1, s32, 0xfff ; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 10 ; GFX11-SDAG-NEXT: s_and_b32 s1, s1, 0xfffff000 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 ; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc ; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 ; GFX11-SDAG-NEXT: s_mov_b32 s32, s34 ; GFX11-SDAG-NEXT: s_mov_b32 s34, s5 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 ; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 0x7f ; GFX11-GISEL-NEXT: s_mov_b32 s5, s34 -; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 -; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 ; GFX11-GISEL-NEXT: s_and_b32 s33, s33, 0xffffff80 ; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 ; GFX11-GISEL-NEXT: s_addk_i32 s32, 0x100 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 ; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 ; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 @@ -1296,12 +1301,13 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { ; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 10 ; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 ; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff000 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 ; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc ; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-GISEL-NEXT: s_mov_b32 s32, s34 ; GFX11-GISEL-NEXT: s_mov_b32 s34, s5 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %alloca = alloca i32, i32 %n, align 128, addrspace(5) store volatile i32 10, ptr addrspace(5) %alloca @@ -1312,12 +1318,12 @@ define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1341,12 +1347,12 @@ define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1370,13 +1376,14 @@ define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-SDAG-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1399,13 +1406,14 @@ define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) { ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1434,13 +1442,13 @@ define void @test_dynamic_stackalloc_device_divergent() { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 -; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1464,13 +1472,13 @@ define void @test_dynamic_stackalloc_device_divergent() { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 -; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1494,14 +1502,14 @@ define void @test_dynamic_stackalloc_device_divergent() { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 -; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX11-SDAG-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 @@ -1525,14 +1533,14 @@ define void @test_dynamic_stackalloc_device_divergent() { ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 -; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 @@ -1566,6 +1574,7 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX9-SDAG-NEXT: s_mov_b32 s10, s33 ; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0x1fc0 ; GFX9-SDAG-NEXT: s_mov_b32 s11, s34 +; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xffffe000 ; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x4000 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 @@ -1575,7 +1584,6 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s7, 0 -; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xffffe000 ; GFX9-SDAG-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s8, s[4:5] ; GFX9-SDAG-NEXT: v_readlane_b32 s9, v0, s8 @@ -1598,16 +1606,16 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0x1fc0 ; GFX9-GISEL-NEXT: s_mov_b32 s10, s34 +; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 -; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xffffe000 -; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x4000 ; GFX9-GISEL-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1633,19 +1641,20 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-SDAG-NEXT: s_mov_b32 s5, s33 ; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 0x7f ; GFX11-SDAG-NEXT: s_mov_b32 s6, s34 +; GFX11-SDAG-NEXT: s_and_b32 s33, s33, 0xffffff80 ; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 -; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-SDAG-NEXT: s_addk_i32 s32, 0x100 ; GFX11-SDAG-NEXT: s_mov_b32 s2, exec_lo ; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0xfff ; GFX11-SDAG-NEXT: s_mov_b32 s1, 0 -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xfffff000 -; GFX11-SDAG-NEXT: s_and_b32 s33, s33, 0xffffff80 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX11-SDAG-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s3, s2 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1657,28 +1666,29 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX11-SDAG-NEXT: ; %bb.2: ; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0 ; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x1bc -; GFX11-SDAG-NEXT: s_mov_b32 s33, s5 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 ; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s0 dlc ; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-SDAG-NEXT: s_mov_b32 s32, s34 ; GFX11-SDAG-NEXT: s_mov_b32 s34, s6 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s5 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 ; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 0x7f ; GFX11-GISEL-NEXT: s_mov_b32 s5, s34 -; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 -; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 ; GFX11-GISEL-NEXT: s_and_b32 s33, s33, 0xffffff80 ; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 ; GFX11-GISEL-NEXT: s_addk_i32 s32, 0x100 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 @@ -1693,12 +1703,13 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x1bc ; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 ; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff000 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 ; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc ; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-GISEL-NEXT: s_mov_b32 s32, s34 ; GFX11-GISEL-NEXT: s_mov_b32 s34, s5 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %idx = call i32 @llvm.amdgcn.workitem.id.x() %alloca = alloca i32, i32 %idx, align 128, addrspace(5) @@ -1710,13 +1721,13 @@ define void @test_dynamic_stackalloc_device_divergent_under_aligned() { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 -; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1740,13 +1751,13 @@ define void @test_dynamic_stackalloc_device_divergent_under_aligned() { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 -; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1770,14 +1781,14 @@ define void @test_dynamic_stackalloc_device_divergent_under_aligned() { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 -; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX11-SDAG-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 @@ -1801,14 +1812,14 @@ define void @test_dynamic_stackalloc_device_divergent_under_aligned() { ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 -; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 @@ -1842,10 +1853,10 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) { ; GFX9-SDAG-NEXT: s_mov_b32 s13, s33 ; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0xfc0 ; GFX9-SDAG-NEXT: s_mov_b32 s14, s34 -; GFX9-SDAG-NEXT: s_mov_b32 s8, 0 -; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xfffff000 ; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 +; GFX9-SDAG-NEXT: s_mov_b32 s8, 0 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x3000 ; GFX9-SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-SDAG-NEXT: s_cbranch_execz .LBB14_6 @@ -1925,10 +1936,10 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) { ; GFX9-GISEL-NEXT: s_mov_b32 s13, s33 ; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0xfc0 ; GFX9-GISEL-NEXT: s_mov_b32 s14, s34 -; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 -; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xfffff000 ; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 +; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x3000 ; GFX9-GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-GISEL-NEXT: s_cbranch_execz .LBB14_6 @@ -2007,10 +2018,10 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) { ; GFX11-SDAG-NEXT: s_mov_b32 s7, s33 ; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 63 ; GFX11-SDAG-NEXT: s_mov_b32 s8, s34 -; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_and_not1_b32 s33, s33, 63 ; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_addk_i32 s32, 0xc0 ; GFX11-SDAG-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11-SDAG-NEXT: s_cbranch_execz .LBB14_6 @@ -2092,10 +2103,10 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) { ; GFX11-GISEL-NEXT: s_mov_b32 s7, s33 ; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 63 ; GFX11-GISEL-NEXT: s_mov_b32 s8, s34 -; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_and_not1_b32 s33, s33, 63 ; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_addk_i32 s32, 0xc0 ; GFX11-GISEL-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11-GISEL-NEXT: s_cbranch_execz .LBB14_6 @@ -2192,10 +2203,10 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) { ; GFX9-SDAG-NEXT: s_mov_b32 s11, s33 ; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0xfc0 ; GFX9-SDAG-NEXT: s_mov_b32 s12, s34 -; GFX9-SDAG-NEXT: s_mov_b32 s8, 0 -; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xfffff000 ; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 +; GFX9-SDAG-NEXT: s_mov_b32 s8, 0 +; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x2000 ; GFX9-SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-SDAG-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -2258,10 +2269,10 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) { ; GFX9-GISEL-NEXT: s_mov_b32 s11, s33 ; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0xfc0 ; GFX9-GISEL-NEXT: s_mov_b32 s12, s34 -; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 -; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xfffff000 ; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 +; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 +; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x2000 ; GFX9-GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -2324,10 +2335,10 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) { ; GFX11-SDAG-NEXT: s_mov_b32 s5, s33 ; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 63 ; GFX11-SDAG-NEXT: s_mov_b32 s6, s34 -; GFX11-SDAG-NEXT: s_mov_b32 s1, 0 -; GFX11-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX11-SDAG-NEXT: s_and_not1_b32 s33, s33, 63 ; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 +; GFX11-SDAG-NEXT: s_mov_b32 s1, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX11-SDAG-NEXT: s_addk_i32 s32, 0x80 ; GFX11-SDAG-NEXT: v_cmpx_ne_u32_e32 0, v0 ; GFX11-SDAG-NEXT: s_xor_b32 s0, exec_lo, s0 @@ -2393,10 +2404,10 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) { ; GFX11-GISEL-NEXT: s_mov_b32 s5, s33 ; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 63 ; GFX11-GISEL-NEXT: s_mov_b32 s6, s34 -; GFX11-GISEL-NEXT: s_mov_b32 s1, 0 -; GFX11-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX11-GISEL-NEXT: s_and_not1_b32 s33, s33, 63 ; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 +; GFX11-GISEL-NEXT: s_mov_b32 s1, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX11-GISEL-NEXT: s_addk_i32 s32, 0x80 ; GFX11-GISEL-NEXT: v_cmpx_ne_u32_e32 0, v0 ; GFX11-GISEL-NEXT: s_xor_b32 s0, exec_lo, s0 @@ -2476,13 +2487,13 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 -; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff0, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -2506,13 +2517,13 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 -; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -2536,15 +2547,15 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_mov_b16_e32 v1.h, 0 ; GFX11-SDAG-NEXT: v_mov_b16_e32 v1.l, v0.l -; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 -; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v1, 2, 15 ; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v1, 2, 15 ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff0, v0 ; GFX11-SDAG-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 @@ -2568,14 +2579,14 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 -; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 @@ -2605,12 +2616,12 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -2634,12 +2645,12 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -2663,13 +2674,14 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-SDAG-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -2692,13 +2704,14 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir index 49a91e6f6f33b..15ef61fd75bad 100644 --- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir +++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir @@ -21,21 +21,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32__inline_imm__fi_offset0 - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 12, $sgpr4, implicit-def dead $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7 ; ; MUBUFW32-LABEL: name: s_add_i32__inline_imm__fi_offset0 - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 12, $sgpr4, implicit-def dead $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_i32__inline_imm__fi_offset0 - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 12, $sgpr32, implicit-def dead $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 12, $sgpr32, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__inline_imm__fi_offset0 - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 12, $sgpr32, implicit-def dead $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 12, $sgpr32, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 12, %stack.0, implicit-def dead $scc SI_RETURN implicit $sgpr7 @@ -54,21 +66,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32__fi_offset0__inline_imm - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr4, 12, implicit-def dead $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7 ; ; MUBUFW32-LABEL: name: s_add_i32__fi_offset0__inline_imm - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr4, 12, implicit-def dead $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_i32__fi_offset0__inline_imm - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 $sgpr32, 12, implicit-def dead $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr32, 12, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__fi_offset0__inline_imm - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 $sgpr32, 12, implicit-def dead $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr32, 12, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 %stack.0, 12, implicit-def dead $scc SI_RETURN implicit $sgpr7 @@ -88,21 +112,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32__inline_imm___fi_offset_inline_imm - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 28, $sgpr4, implicit-def $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7 ; ; MUBUFW32-LABEL: name: s_add_i32__inline_imm___fi_offset_inline_imm - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 28, $sgpr4, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_i32__inline_imm___fi_offset_inline_imm - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 28, $sgpr32, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 28, $sgpr32, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__inline_imm___fi_offset_inline_imm - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 28, $sgpr32, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 28, $sgpr32, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 12, %stack.1, implicit-def $scc SI_RETURN implicit $sgpr7 @@ -121,21 +157,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32__literal__fi_offset0 - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 68, $sgpr4, implicit-def dead $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7 ; ; MUBUFW32-LABEL: name: s_add_i32__literal__fi_offset0 - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 68, $sgpr4, implicit-def dead $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_i32__literal__fi_offset0 - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 68, $sgpr32, implicit-def dead $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 68, $sgpr32, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__literal__fi_offset0 - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 68, $sgpr32, implicit-def dead $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 68, $sgpr32, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 68, %stack.0, implicit-def dead $scc SI_RETURN implicit $sgpr7 @@ -154,21 +202,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32__fi_offset0__literal - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr4, 68, implicit-def $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7 ; ; MUBUFW32-LABEL: name: s_add_i32__fi_offset0__literal - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr4, 68, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_i32__fi_offset0__literal - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 $sgpr32, 68, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr32, 68, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__fi_offset0__literal - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 $sgpr32, 68, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr32, 68, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 %stack.0, 68, implicit-def $scc SI_RETURN implicit $sgpr7 @@ -188,21 +248,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32__literal__fi_offset96 - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 164, $sgpr4, implicit-def $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; MUBUFW32-LABEL: name: s_add_i32__literal__fi_offset96 - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 164, $sgpr4, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW64-LABEL: name: s_add_i32__literal__fi_offset96 - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 164, $sgpr32, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 164, $sgpr32, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_add_i32__literal__fi_offset96 - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 164, $sgpr32, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 164, $sgpr32, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_ADD_I32 68, %stack.1, implicit-def $scc SI_RETURN implicit $sgpr7, implicit $scc @@ -222,21 +294,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32____fi_offset96__literal - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr4, 164, implicit-def $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; MUBUFW32-LABEL: name: s_add_i32____fi_offset96__literal - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr4, 164, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW64-LABEL: name: s_add_i32____fi_offset96__literal - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 $sgpr32, 164, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr32, 164, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_add_i32____fi_offset96__literal - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 $sgpr32, 164, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr32, 164, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_ADD_I32 %stack.1, 68, implicit-def $scc SI_RETURN implicit $sgpr7, implicit $scc @@ -258,6 +342,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__sgpr__fi_offset0 ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 @@ -266,6 +353,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__sgpr__fi_offset0 ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 @@ -274,6 +364,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__sgpr__fi_offset0 ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 @@ -281,6 +374,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__sgpr__fi_offset0 ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 @@ -304,6 +400,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__fi_offset0__sgpr ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 @@ -312,6 +411,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__fi_offset0__sgpr ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 @@ -320,6 +422,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__fi_offset0__sgpr ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 @@ -327,6 +432,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__fi_offset0__sgpr ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 @@ -351,6 +459,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__sgpr__fi_literal_offset ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 80, implicit-def dead $scc @@ -359,6 +470,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__sgpr__fi_literal_offset ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 80, implicit-def dead $scc @@ -367,6 +481,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__sgpr__fi_literal_offset ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 80, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 @@ -374,6 +491,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__sgpr__fi_literal_offset ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 80, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 @@ -398,6 +518,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__fi_literal_offset__sgpr ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 80, killed renamable $sgpr7, implicit-def $scc @@ -406,6 +529,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__fi_literal_offset__sgpr ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 80, killed renamable $sgpr7, implicit-def $scc @@ -414,6 +540,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__fi_literal_offset__sgpr ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 80, killed renamable $sgpr7, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -421,6 +550,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__fi_literal_offset__sgpr ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 80, killed renamable $sgpr7, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -445,6 +577,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__kernel__literal__fi_offset96__offset_literal ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_MOV_B32 164 @@ -453,17 +587,23 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__kernel__literal__fi_offset96__offset_literal ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_MOV_B32 164 ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_i32__kernel__literal__fi_offset96__offset_literal - ; FLATSCRW64: renamable $sgpr7 = S_MOV_B32 164 + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_MOV_B32 164 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__kernel__literal__fi_offset96__offset_literal - ; FLATSCRW32: renamable $sgpr7 = S_MOV_B32 164 + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_MOV_B32 164 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 68, %stack.1, implicit-def dead $scc SI_RETURN implicit $sgpr7 @@ -485,6 +625,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__kernel__literal__fi_offset96__offset_literal_live_scc ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 164, 0, implicit-def $scc @@ -493,17 +635,23 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__kernel__literal__fi_offset96__offset_literal_live_scc ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 164, 0, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW64-LABEL: name: s_add_i32__kernel__literal__fi_offset96__offset_literal_live_scc - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 164, 0, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 164, 0, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_add_i32__kernel__literal__fi_offset96__offset_literal_live_scc - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 164, 0, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 164, 0, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_ADD_I32 68, %stack.1, implicit-def $scc SI_RETURN implicit $sgpr7, implicit $scc @@ -525,6 +673,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__kernel__fi_offset96__offset_literal__literal ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_MOV_B32 164 @@ -533,17 +683,23 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__kernel__fi_offset96__offset_literal__literal ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_MOV_B32 164 ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_i32__kernel__fi_offset96__offset_literal__literal - ; FLATSCRW64: renamable $sgpr7 = S_MOV_B32 164 + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_MOV_B32 164 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__kernel__fi_offset96__offset_literal__literal - ; FLATSCRW32: renamable $sgpr7 = S_MOV_B32 164 + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_MOV_B32 164 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 %stack.1, 68, implicit-def dead $scc SI_RETURN implicit $sgpr7 @@ -567,6 +723,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__kernel__sgpr__fi_literal_offset ; MUBUFW64: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 96, implicit-def dead $scc @@ -575,6 +733,8 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__kernel__sgpr__fi_literal_offset ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 96, implicit-def dead $scc @@ -583,12 +743,16 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__kernel__sgpr__fi_literal_offset ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 96, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__kernel__sgpr__fi_literal_offset ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 96, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 $sgpr8, %stack.1, implicit-def dead $scc @@ -613,6 +777,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__kernel__fi_literal_offset__sgpr ; MUBUFW64: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 96, $sgpr8, implicit-def dead $scc @@ -621,6 +787,8 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__kernel__fi_literal_offset__sgpr ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 96, $sgpr8, implicit-def dead $scc @@ -629,12 +797,16 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__kernel__fi_literal_offset__sgpr ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 96, $sgpr8, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__kernel__fi_literal_offset__sgpr ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 96, $sgpr8, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 %stack.1, $sgpr8, implicit-def dead $scc @@ -658,6 +830,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__kernel__sgpr__fi_offset0__live_scc ; MUBUFW64: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 0, implicit-def $scc @@ -666,6 +840,8 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__kernel__sgpr__fi_offset0__live_scc ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 0, implicit-def $scc @@ -674,12 +850,16 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__kernel__sgpr__fi_offset0__live_scc ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 0, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_add_i32__kernel__sgpr__fi_offset0__live_scc ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 0, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_ADD_I32 $sgpr8, %stack.0, implicit-def $scc @@ -702,6 +882,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__sgpr__fi_offset0__live_scc ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 0, implicit-def $scc @@ -710,6 +893,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__sgpr__fi_offset0__live_scc ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 0, implicit-def $scc @@ -718,6 +904,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__sgpr__fi_offset0__live_scc ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 0, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -725,6 +914,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__sgpr__fi_offset0__live_scc ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 0, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -750,6 +942,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__kernel__sgpr__fi_literal_offset__live_scc ; MUBUFW64: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 96, implicit-def $scc @@ -758,6 +952,8 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__kernel__sgpr__fi_literal_offset__live_scc ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 96, implicit-def $scc @@ -766,12 +962,16 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__kernel__sgpr__fi_literal_offset__live_scc ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 96, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_add_i32__kernel__sgpr__fi_literal_offset__live_scc ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr8, 96, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_ADD_I32 $sgpr8, %stack.1, implicit-def $scc @@ -795,6 +995,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__sgpr__fi_literal_offset__live_scc ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 96, implicit-def $scc @@ -803,6 +1006,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__sgpr__fi_literal_offset__live_scc ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 96, implicit-def $scc @@ -811,6 +1017,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__sgpr__fi_literal_offset__live_scc ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 96, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -818,6 +1027,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__sgpr__fi_literal_offset__live_scc ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed renamable $sgpr7, 96, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -840,21 +1052,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32__inlineimm__fi_offset_32__total_offset_inlineimm - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 40, $sgpr4, implicit-def $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; MUBUFW32-LABEL: name: s_add_i32__inlineimm__fi_offset_32__total_offset_inlineimm - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 40, $sgpr4, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW64-LABEL: name: s_add_i32__inlineimm__fi_offset_32__total_offset_inlineimm - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 40, $sgpr32, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 40, $sgpr32, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_add_i32__inlineimm__fi_offset_32__total_offset_inlineimm - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 40, $sgpr32, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 40, $sgpr32, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_ADD_I32 8, %stack.1, implicit-def $scc SI_RETURN implicit $sgpr7, implicit $scc @@ -874,21 +1098,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32__fi_offset_32__inlineimm__total_offset_inlineimm - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr4, 40, implicit-def $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; MUBUFW32-LABEL: name: s_add_i32__fi_offset_32__inlineimm__total_offset_inlineimm - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr4, 40, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW64-LABEL: name: s_add_i32__fi_offset_32__inlineimm__total_offset_inlineimm - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 $sgpr32, 40, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr32, 40, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_add_i32__fi_offset_32__inlineimm__total_offset_inlineimm - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 $sgpr32, 40, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 $sgpr32, 40, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_ADD_I32 %stack.1, 8, implicit-def $scc SI_RETURN implicit $sgpr7, implicit $scc @@ -911,6 +1147,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__kernel_inlineimm__fi_offset_32__total_offset_inlineimm ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 40, 0, implicit-def $scc @@ -919,17 +1157,23 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__kernel_inlineimm__fi_offset_32__total_offset_inlineimm ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 40, 0, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW64-LABEL: name: s_add_i32__kernel_inlineimm__fi_offset_32__total_offset_inlineimm - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 40, 0, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 40, 0, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_add_i32__kernel_inlineimm__fi_offset_32__total_offset_inlineimm - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 40, 0, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 40, 0, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_ADD_I32 8, %stack.1, implicit-def $scc SI_RETURN implicit $sgpr7, implicit $scc @@ -952,6 +1196,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__kernel_fi_offset_32__inlineimm__total_offset_inlineimm ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 0, 40, implicit-def $scc @@ -960,17 +1206,23 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__kernel_fi_offset_32__inlineimm__total_offset_inlineimm ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 0, 40, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW64-LABEL: name: s_add_i32__kernel_fi_offset_32__inlineimm__total_offset_inlineimm - ; FLATSCRW64: renamable $sgpr7 = S_ADD_I32 0, 40, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 0, 40, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_add_i32__kernel_fi_offset_32__inlineimm__total_offset_inlineimm - ; FLATSCRW32: renamable $sgpr7 = S_ADD_I32 0, 40, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 0, 40, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_ADD_I32 %stack.1, 8, implicit-def $scc SI_RETURN implicit $sgpr7, implicit $scc @@ -989,21 +1241,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32__0__fi_offset0 - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = COPY $sgpr4 ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7 ; ; MUBUFW32-LABEL: name: s_add_i32__0__fi_offset0 - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = COPY $sgpr4 ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_i32__0__fi_offset0 - ; FLATSCRW64: renamable $sgpr7 = COPY $sgpr32 + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = COPY $sgpr32 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__0__fi_offset0 - ; FLATSCRW32: renamable $sgpr7 = COPY $sgpr32 + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = COPY $sgpr32 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 0, %stack.0, implicit-def dead $scc SI_RETURN implicit $sgpr7 @@ -1022,21 +1286,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_i32__fi_offset0__0 - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = COPY $sgpr4 ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7 ; ; MUBUFW32-LABEL: name: s_add_i32__fi_offset0__0 - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = COPY $sgpr4 ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_i32__fi_offset0__0 - ; FLATSCRW64: renamable $sgpr7 = COPY $sgpr32 + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = COPY $sgpr32 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_i32__fi_offset0__0 - ; FLATSCRW32: renamable $sgpr7 = COPY $sgpr32 + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = COPY $sgpr32 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_I32 %stack.0, 0, implicit-def dead $scc SI_RETURN implicit $sgpr7 @@ -1058,6 +1334,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__same_sgpr__fi_offset0 ; MUBUFW64: liveins: $sgpr7 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr4, $sgpr7, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 @@ -1066,6 +1345,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__same_sgpr__fi_offset0 ; MUBUFW32: liveins: $sgpr7 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr4, $sgpr7, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 @@ -1074,6 +1356,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__same_sgpr__fi_offset0 ; FLATSCRW64: liveins: $sgpr7 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr4 = S_ADD_I32 killed $sgpr32, $sgpr7, implicit-def dead $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr4 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 @@ -1081,6 +1366,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__same_sgpr__fi_offset0 ; FLATSCRW32: liveins: $sgpr7 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr4 = S_ADD_I32 killed $sgpr32, $sgpr7, implicit-def dead $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr4 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 @@ -1104,6 +1392,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__different_sgpr__fi_offset0 ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 @@ -1112,6 +1403,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__different_sgpr__fi_offset0 ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 @@ -1120,6 +1414,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__different_sgpr__fi_offset0 ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 @@ -1127,6 +1424,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__different_sgpr__fi_offset0 ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 @@ -1150,6 +1450,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__different_sgpr__fi_offset0_live_after ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 @@ -1158,6 +1461,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__different_sgpr__fi_offset0_live_after ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr7, $sgpr8, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 @@ -1166,6 +1472,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__different_sgpr__fi_offset0_live_after ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $sgpr8 @@ -1173,6 +1482,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__different_sgpr__fi_offset0_live_after ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = COPY killed renamable $sgpr7 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $sgpr8 @@ -1198,6 +1510,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__identity_sgpr__fi_offset0__kernel ; MUBUFW64: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr8 = COPY $sgpr8 @@ -1206,6 +1520,8 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__identity_sgpr__fi_offset0__kernel ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr8 = COPY $sgpr8 @@ -1214,12 +1530,16 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__identity_sgpr__fi_offset0__kernel ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $sgpr8 = COPY $sgpr8 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr8 ; ; FLATSCRW32-LABEL: name: s_add_i32__identity_sgpr__fi_offset0__kernel ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $sgpr8 = COPY $sgpr8 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr8 renamable $sgpr8 = S_ADD_I32 $sgpr8, %stack.0, implicit-def dead $scc @@ -1244,6 +1564,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__fi_offset0__identity_sgpr__kernel ; MUBUFW64: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr8 = COPY $sgpr8 @@ -1252,6 +1574,8 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__fi_offset0__identity_sgpr__kernel ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr8 = COPY $sgpr8 @@ -1260,12 +1584,16 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__fi_offset0__identity_sgpr__kernel ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $sgpr8 = COPY $sgpr8 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr8 ; ; FLATSCRW32-LABEL: name: s_add_i32__fi_offset0__identity_sgpr__kernel ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $sgpr8 = COPY $sgpr8 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr8 renamable $sgpr8 = S_ADD_I32 $sgpr8, %stack.0, implicit-def dead $scc @@ -1291,6 +1619,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__identity_sgpr__fi_offset32__kernel ; MUBUFW64: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr8 = S_ADD_I32 $sgpr8, 32, implicit-def dead $scc @@ -1299,6 +1629,8 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__identity_sgpr__fi_offset32__kernel ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr8 = S_ADD_I32 $sgpr8, 32, implicit-def dead $scc @@ -1307,12 +1639,16 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__identity_sgpr__fi_offset32__kernel ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $sgpr8 = S_ADD_I32 $sgpr8, 32, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr8 ; ; FLATSCRW32-LABEL: name: s_add_i32__identity_sgpr__fi_offset32__kernel ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $sgpr8 = S_ADD_I32 $sgpr8, 32, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr8 renamable $sgpr8 = S_ADD_I32 $sgpr8, %stack.1, implicit-def dead $scc @@ -1338,6 +1674,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__fi_offset32__identity_sgpr__kernel ; MUBUFW64: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr8 = S_ADD_I32 $sgpr8, 32, implicit-def dead $scc @@ -1346,6 +1684,8 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__fi_offset32__identity_sgpr__kernel ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr8 = S_ADD_I32 $sgpr8, 32, implicit-def dead $scc @@ -1354,12 +1694,16 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__fi_offset32__identity_sgpr__kernel ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $sgpr8 = S_ADD_I32 $sgpr8, 32, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr8 ; ; FLATSCRW32-LABEL: name: s_add_i32__fi_offset32__identity_sgpr__kernel ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $sgpr8 = S_ADD_I32 $sgpr8, 32, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr8 renamable $sgpr8 = S_ADD_I32 $sgpr8, %stack.1, implicit-def dead $scc @@ -1384,6 +1728,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__identity_sgpr__fi_offset0 ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr8 = S_ADD_I32 killed $sgpr4, $sgpr8, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr8 = COPY killed renamable $sgpr8 @@ -1392,6 +1739,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__identity_sgpr__fi_offset0 ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr8 = S_ADD_I32 killed $sgpr4, $sgpr8, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr8 = COPY killed renamable $sgpr8 @@ -1400,6 +1750,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__identity_sgpr__fi_offset0 ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 ; FLATSCRW64-NEXT: renamable $sgpr4 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW64-NEXT: renamable $sgpr8 = COPY killed renamable $sgpr4 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr8 @@ -1407,6 +1760,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__identity_sgpr__fi_offset0 ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 ; FLATSCRW32-NEXT: renamable $sgpr4 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW32-NEXT: renamable $sgpr8 = COPY killed renamable $sgpr4 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr8 @@ -1432,6 +1788,9 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32__fi_offset32__identity_sgpr ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr8 = S_ADD_I32 killed $sgpr4, $sgpr8, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr8 = S_ADD_I32 killed renamable $sgpr8, 32, implicit-def dead $scc @@ -1440,6 +1799,9 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32__fi_offset32__identity_sgpr ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr8 = S_ADD_I32 killed $sgpr4, $sgpr8, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr8 = S_ADD_I32 killed renamable $sgpr8, 32, implicit-def dead $scc @@ -1448,6 +1810,9 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32__fi_offset32__identity_sgpr ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 ; FLATSCRW64-NEXT: renamable $sgpr4 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW64-NEXT: renamable $sgpr8 = S_ADD_I32 killed renamable $sgpr4, 32, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr8 @@ -1455,6 +1820,9 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32__fi_offset32__identity_sgpr ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 ; FLATSCRW32-NEXT: renamable $sgpr4 = S_ADD_I32 killed $sgpr32, $sgpr8, implicit-def dead $scc ; FLATSCRW32-NEXT: renamable $sgpr8 = S_ADD_I32 killed renamable $sgpr4, 32, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr8 @@ -1479,6 +1847,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32_use_dst_reg_as_temp_regression ; MUBUFW64: liveins: $vcc_lo, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; MUBUFW64-NEXT: renamable $vcc_hi = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $vcc_hi = S_ADD_I32 killed $vcc_hi, renamable $vcc_lo, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $vcc_hi = COPY killed renamable $vcc_hi @@ -1487,6 +1857,8 @@ body: | ; MUBUFW32-LABEL: name: s_add_i32_use_dst_reg_as_temp_regression ; MUBUFW32: liveins: $vcc_lo, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; MUBUFW32-NEXT: renamable $vcc_hi = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $vcc_hi = S_ADD_I32 killed $vcc_hi, renamable $vcc_lo, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $vcc_hi = COPY killed renamable $vcc_hi @@ -1495,6 +1867,8 @@ body: | ; FLATSCRW64-LABEL: name: s_add_i32_use_dst_reg_as_temp_regression ; FLATSCRW64: liveins: $vcc_lo, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; FLATSCRW64-NEXT: renamable $vcc_hi = S_ADD_I32 killed $sgpr32, renamable $vcc_lo, implicit-def dead $scc ; FLATSCRW64-NEXT: renamable $vcc_hi = COPY killed renamable $vcc_hi ; FLATSCRW64-NEXT: SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29 @@ -1502,6 +1876,8 @@ body: | ; FLATSCRW32-LABEL: name: s_add_i32_use_dst_reg_as_temp_regression ; FLATSCRW32: liveins: $vcc_lo, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; FLATSCRW32-NEXT: renamable $vcc_hi = S_ADD_I32 killed $sgpr32, renamable $vcc_lo, implicit-def dead $scc ; FLATSCRW32-NEXT: renamable $vcc_hi = COPY killed renamable $vcc_hi ; FLATSCRW32-NEXT: SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29 @@ -1525,24 +1901,36 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32_frame_index_elimination_no_sgpr_dead_scc_offset_zero ; MUBUFW64: liveins: $vcc_lo, $vcc_hi, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr32, $sgpr33, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr7 = COPY renamable $sgpr7 ; MUBUFW64-NEXT: SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31, implicit $sgpr32, implicit $sgpr33, implicit $sgpr34, implicit $sgpr35, implicit $sgpr36, implicit $sgpr37, implicit $sgpr38, implicit $sgpr39, implicit $sgpr40, implicit $sgpr41, implicit $sgpr42, implicit $sgpr43, implicit $sgpr44, implicit $sgpr45, implicit $sgpr46, implicit $sgpr47, implicit $sgpr48, implicit $sgpr49, implicit $sgpr50, implicit $sgpr51, implicit $sgpr52, implicit $sgpr53, implicit $sgpr54, implicit $sgpr55, implicit $sgpr56, implicit $sgpr57, implicit $sgpr58, implicit $sgpr59, implicit $sgpr60, implicit $sgpr61, implicit $sgpr62, implicit $sgpr63, implicit $sgpr64, implicit $sgpr65, implicit $sgpr66, implicit $sgpr67, implicit $sgpr68, implicit $sgpr69, implicit $sgpr70, implicit $sgpr71, implicit $sgpr72, implicit $sgpr73, implicit $sgpr74, implicit $sgpr75, implicit $sgpr76, implicit $sgpr77, implicit $sgpr78, implicit $sgpr79, implicit $sgpr80, implicit $sgpr81, implicit $sgpr82, implicit $sgpr83, implicit $sgpr84, implicit $sgpr85, implicit $sgpr86, implicit $sgpr87, implicit $sgpr88, implicit $sgpr89, implicit $sgpr90, implicit $sgpr91, implicit $sgpr92, implicit $sgpr93, implicit $sgpr94, implicit $sgpr95 ; ; MUBUFW32-LABEL: name: s_add_i32_frame_index_elimination_no_sgpr_dead_scc_offset_zero ; MUBUFW32: liveins: $vcc_lo, $vcc_hi, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr32, $sgpr33, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr7 = COPY renamable $sgpr7 ; MUBUFW32-NEXT: SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31, implicit $sgpr32, implicit $sgpr33, implicit $sgpr34, implicit $sgpr35, implicit $sgpr36, implicit $sgpr37, implicit $sgpr38, implicit $sgpr39, implicit $sgpr40, implicit $sgpr41, implicit $sgpr42, implicit $sgpr43, implicit $sgpr44, implicit $sgpr45, implicit $sgpr46, implicit $sgpr47, implicit $sgpr48, implicit $sgpr49, implicit $sgpr50, implicit $sgpr51, implicit $sgpr52, implicit $sgpr53, implicit $sgpr54, implicit $sgpr55, implicit $sgpr56, implicit $sgpr57, implicit $sgpr58, implicit $sgpr59, implicit $sgpr60, implicit $sgpr61, implicit $sgpr62, implicit $sgpr63, implicit $sgpr64, implicit $sgpr65, implicit $sgpr66, implicit $sgpr67, implicit $sgpr68, implicit $sgpr69, implicit $sgpr70, implicit $sgpr71, implicit $sgpr72, implicit $sgpr73, implicit $sgpr74, implicit $sgpr75, implicit $sgpr76, implicit $sgpr77, implicit $sgpr78, implicit $sgpr79, implicit $sgpr80, implicit $sgpr81, implicit $sgpr82, implicit $sgpr83, implicit $sgpr84, implicit $sgpr85, implicit $sgpr86, implicit $sgpr87, implicit $sgpr88, implicit $sgpr89, implicit $sgpr90, implicit $sgpr91, implicit $sgpr92, implicit $sgpr93, implicit $sgpr94, implicit $sgpr95 ; ; FLATSCRW64-LABEL: name: s_add_i32_frame_index_elimination_no_sgpr_dead_scc_offset_zero ; FLATSCRW64: liveins: $vcc_lo, $vcc_hi, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr32, $sgpr33, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr7 = COPY renamable $sgpr7 ; FLATSCRW64-NEXT: SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31, implicit $sgpr32, implicit $sgpr33, implicit $sgpr34, implicit $sgpr35, implicit $sgpr36, implicit $sgpr37, implicit $sgpr38, implicit $sgpr39, implicit $sgpr40, implicit $sgpr41, implicit $sgpr42, implicit $sgpr43, implicit $sgpr44, implicit $sgpr45, implicit $sgpr46, implicit $sgpr47, implicit $sgpr48, implicit $sgpr49, implicit $sgpr50, implicit $sgpr51, implicit $sgpr52, implicit $sgpr53, implicit $sgpr54, implicit $sgpr55, implicit $sgpr56, implicit $sgpr57, implicit $sgpr58, implicit $sgpr59, implicit $sgpr60, implicit $sgpr61, implicit $sgpr62, implicit $sgpr63, implicit $sgpr64, implicit $sgpr65, implicit $sgpr66, implicit $sgpr67, implicit $sgpr68, implicit $sgpr69, implicit $sgpr70, implicit $sgpr71, implicit $sgpr72, implicit $sgpr73, implicit $sgpr74, implicit $sgpr75, implicit $sgpr76, implicit $sgpr77, implicit $sgpr78, implicit $sgpr79, implicit $sgpr80, implicit $sgpr81, implicit $sgpr82, implicit $sgpr83, implicit $sgpr84, implicit $sgpr85, implicit $sgpr86, implicit $sgpr87, implicit $sgpr88, implicit $sgpr89, implicit $sgpr90, implicit $sgpr91, implicit $sgpr92, implicit $sgpr93, implicit $sgpr94, implicit $sgpr95 ; ; FLATSCRW32-LABEL: name: s_add_i32_frame_index_elimination_no_sgpr_dead_scc_offset_zero ; FLATSCRW32: liveins: $vcc_lo, $vcc_hi, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr32, $sgpr33, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr7 = COPY renamable $sgpr7 ; FLATSCRW32-NEXT: SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31, implicit $sgpr32, implicit $sgpr33, implicit $sgpr34, implicit $sgpr35, implicit $sgpr36, implicit $sgpr37, implicit $sgpr38, implicit $sgpr39, implicit $sgpr40, implicit $sgpr41, implicit $sgpr42, implicit $sgpr43, implicit $sgpr44, implicit $sgpr45, implicit $sgpr46, implicit $sgpr47, implicit $sgpr48, implicit $sgpr49, implicit $sgpr50, implicit $sgpr51, implicit $sgpr52, implicit $sgpr53, implicit $sgpr54, implicit $sgpr55, implicit $sgpr56, implicit $sgpr57, implicit $sgpr58, implicit $sgpr59, implicit $sgpr60, implicit $sgpr61, implicit $sgpr62, implicit $sgpr63, implicit $sgpr64, implicit $sgpr65, implicit $sgpr66, implicit $sgpr67, implicit $sgpr68, implicit $sgpr69, implicit $sgpr70, implicit $sgpr71, implicit $sgpr72, implicit $sgpr73, implicit $sgpr74, implicit $sgpr75, implicit $sgpr76, implicit $sgpr77, implicit $sgpr78, implicit $sgpr79, implicit $sgpr80, implicit $sgpr81, implicit $sgpr82, implicit $sgpr83, implicit $sgpr84, implicit $sgpr85, implicit $sgpr86, implicit $sgpr87, implicit $sgpr88, implicit $sgpr89, implicit $sgpr90, implicit $sgpr91, implicit $sgpr92, implicit $sgpr93, implicit $sgpr94, implicit $sgpr95 renamable $sgpr7 = S_ADD_I32 renamable $sgpr7, %stack.0, implicit-def dead $scc @@ -1566,24 +1954,36 @@ body: | ; MUBUFW64-LABEL: name: s_add_i32_frame_index_elimination_no_sgpr_dead_scc_offset_non_zero ; MUBUFW64: liveins: $vcc_lo, $vcc_hi, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr32, $sgpr33, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_I32 renamable $sgpr7, 64, implicit-def dead $scc ; MUBUFW64-NEXT: SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31, implicit $sgpr32, implicit $sgpr33, implicit $sgpr34, implicit $sgpr35, implicit $sgpr36, implicit $sgpr37, implicit $sgpr38, implicit $sgpr39, implicit $sgpr40, implicit $sgpr41, implicit $sgpr42, implicit $sgpr43, implicit $sgpr44, implicit $sgpr45, implicit $sgpr46, implicit $sgpr47, implicit $sgpr48, implicit $sgpr49, implicit $sgpr50, implicit $sgpr51, implicit $sgpr52, implicit $sgpr53, implicit $sgpr54, implicit $sgpr55, implicit $sgpr56, implicit $sgpr57, implicit $sgpr58, implicit $sgpr59, implicit $sgpr60, implicit $sgpr61, implicit $sgpr62, implicit $sgpr63, implicit $sgpr64, implicit $sgpr65, implicit $sgpr66, implicit $sgpr67, implicit $sgpr68, implicit $sgpr69, implicit $sgpr70, implicit $sgpr71, implicit $sgpr72, implicit $sgpr73, implicit $sgpr74, implicit $sgpr75, implicit $sgpr76, implicit $sgpr77, implicit $sgpr78, implicit $sgpr79, implicit $sgpr80, implicit $sgpr81, implicit $sgpr82, implicit $sgpr83, implicit $sgpr84, implicit $sgpr85, implicit $sgpr86, implicit $sgpr87, implicit $sgpr88, implicit $sgpr89, implicit $sgpr90, implicit $sgpr91, implicit $sgpr92, implicit $sgpr93, implicit $sgpr94, implicit $sgpr95 ; ; MUBUFW32-LABEL: name: s_add_i32_frame_index_elimination_no_sgpr_dead_scc_offset_non_zero ; MUBUFW32: liveins: $vcc_lo, $vcc_hi, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr32, $sgpr33, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_I32 renamable $sgpr7, 64, implicit-def dead $scc ; MUBUFW32-NEXT: SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31, implicit $sgpr32, implicit $sgpr33, implicit $sgpr34, implicit $sgpr35, implicit $sgpr36, implicit $sgpr37, implicit $sgpr38, implicit $sgpr39, implicit $sgpr40, implicit $sgpr41, implicit $sgpr42, implicit $sgpr43, implicit $sgpr44, implicit $sgpr45, implicit $sgpr46, implicit $sgpr47, implicit $sgpr48, implicit $sgpr49, implicit $sgpr50, implicit $sgpr51, implicit $sgpr52, implicit $sgpr53, implicit $sgpr54, implicit $sgpr55, implicit $sgpr56, implicit $sgpr57, implicit $sgpr58, implicit $sgpr59, implicit $sgpr60, implicit $sgpr61, implicit $sgpr62, implicit $sgpr63, implicit $sgpr64, implicit $sgpr65, implicit $sgpr66, implicit $sgpr67, implicit $sgpr68, implicit $sgpr69, implicit $sgpr70, implicit $sgpr71, implicit $sgpr72, implicit $sgpr73, implicit $sgpr74, implicit $sgpr75, implicit $sgpr76, implicit $sgpr77, implicit $sgpr78, implicit $sgpr79, implicit $sgpr80, implicit $sgpr81, implicit $sgpr82, implicit $sgpr83, implicit $sgpr84, implicit $sgpr85, implicit $sgpr86, implicit $sgpr87, implicit $sgpr88, implicit $sgpr89, implicit $sgpr90, implicit $sgpr91, implicit $sgpr92, implicit $sgpr93, implicit $sgpr94, implicit $sgpr95 ; ; FLATSCRW64-LABEL: name: s_add_i32_frame_index_elimination_no_sgpr_dead_scc_offset_non_zero ; FLATSCRW64: liveins: $vcc_lo, $vcc_hi, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr32, $sgpr33, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_I32 renamable $sgpr7, 64, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31, implicit $sgpr32, implicit $sgpr33, implicit $sgpr34, implicit $sgpr35, implicit $sgpr36, implicit $sgpr37, implicit $sgpr38, implicit $sgpr39, implicit $sgpr40, implicit $sgpr41, implicit $sgpr42, implicit $sgpr43, implicit $sgpr44, implicit $sgpr45, implicit $sgpr46, implicit $sgpr47, implicit $sgpr48, implicit $sgpr49, implicit $sgpr50, implicit $sgpr51, implicit $sgpr52, implicit $sgpr53, implicit $sgpr54, implicit $sgpr55, implicit $sgpr56, implicit $sgpr57, implicit $sgpr58, implicit $sgpr59, implicit $sgpr60, implicit $sgpr61, implicit $sgpr62, implicit $sgpr63, implicit $sgpr64, implicit $sgpr65, implicit $sgpr66, implicit $sgpr67, implicit $sgpr68, implicit $sgpr69, implicit $sgpr70, implicit $sgpr71, implicit $sgpr72, implicit $sgpr73, implicit $sgpr74, implicit $sgpr75, implicit $sgpr76, implicit $sgpr77, implicit $sgpr78, implicit $sgpr79, implicit $sgpr80, implicit $sgpr81, implicit $sgpr82, implicit $sgpr83, implicit $sgpr84, implicit $sgpr85, implicit $sgpr86, implicit $sgpr87, implicit $sgpr88, implicit $sgpr89, implicit $sgpr90, implicit $sgpr91, implicit $sgpr92, implicit $sgpr93, implicit $sgpr94, implicit $sgpr95 ; ; FLATSCRW32-LABEL: name: s_add_i32_frame_index_elimination_no_sgpr_dead_scc_offset_non_zero ; FLATSCRW32: liveins: $vcc_lo, $vcc_hi, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr32, $sgpr33, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_I32 renamable $sgpr7, 64, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31, implicit $sgpr32, implicit $sgpr33, implicit $sgpr34, implicit $sgpr35, implicit $sgpr36, implicit $sgpr37, implicit $sgpr38, implicit $sgpr39, implicit $sgpr40, implicit $sgpr41, implicit $sgpr42, implicit $sgpr43, implicit $sgpr44, implicit $sgpr45, implicit $sgpr46, implicit $sgpr47, implicit $sgpr48, implicit $sgpr49, implicit $sgpr50, implicit $sgpr51, implicit $sgpr52, implicit $sgpr53, implicit $sgpr54, implicit $sgpr55, implicit $sgpr56, implicit $sgpr57, implicit $sgpr58, implicit $sgpr59, implicit $sgpr60, implicit $sgpr61, implicit $sgpr62, implicit $sgpr63, implicit $sgpr64, implicit $sgpr65, implicit $sgpr66, implicit $sgpr67, implicit $sgpr68, implicit $sgpr69, implicit $sgpr70, implicit $sgpr71, implicit $sgpr72, implicit $sgpr73, implicit $sgpr74, implicit $sgpr75, implicit $sgpr76, implicit $sgpr77, implicit $sgpr78, implicit $sgpr79, implicit $sgpr80, implicit $sgpr81, implicit $sgpr82, implicit $sgpr83, implicit $sgpr84, implicit $sgpr85, implicit $sgpr86, implicit $sgpr87, implicit $sgpr88, implicit $sgpr89, implicit $sgpr90, implicit $sgpr91, implicit $sgpr92, implicit $sgpr93, implicit $sgpr94, implicit $sgpr95 renamable $sgpr7 = S_ADD_I32 renamable $sgpr7, %stack.1, implicit-def dead $scc diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir index af61bd70f16b6..faa4975817c2c 100644 --- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir +++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir @@ -21,21 +21,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_add_u32__inline_imm__fi_offset0 - ; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_U32 12, $sgpr4, implicit-def dead $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7 ; ; MUBUFW32-LABEL: name: s_add_u32__inline_imm__fi_offset0 - ; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_U32 12, $sgpr4, implicit-def dead $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_u32__inline_imm__fi_offset0 - ; FLATSCRW64: renamable $sgpr7 = S_ADD_U32 12, $sgpr32, implicit-def dead $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_U32 12, $sgpr32, implicit-def dead $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_u32__inline_imm__fi_offset0 - ; FLATSCRW32: renamable $sgpr7 = S_ADD_U32 12, $sgpr32, implicit-def dead $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_U32 12, $sgpr32, implicit-def dead $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_U32 12, %stack.0, implicit-def dead $scc SI_RETURN implicit $sgpr7 @@ -58,6 +70,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_u32__kernel__literal__fi_offset96__offset_literal ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_MOV_B32 164 @@ -66,17 +80,23 @@ body: | ; MUBUFW32-LABEL: name: s_add_u32__kernel__literal__fi_offset96__offset_literal ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_MOV_B32 164 ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW64-LABEL: name: s_add_u32__kernel__literal__fi_offset96__offset_literal - ; FLATSCRW64: renamable $sgpr7 = S_MOV_B32 164 + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_MOV_B32 164 ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7 ; ; FLATSCRW32-LABEL: name: s_add_u32__kernel__literal__fi_offset96__offset_literal - ; FLATSCRW32: renamable $sgpr7 = S_MOV_B32 164 + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_MOV_B32 164 ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7 renamable $sgpr7 = S_ADD_U32 68, %stack.1, implicit-def dead $scc SI_RETURN implicit $sgpr7 @@ -98,6 +118,8 @@ body: | ; MUBUFW64-LABEL: name: s_add_u32__kernel__literal__fi_offset96__offset_literal_live_scc ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $sgpr7 = S_ADD_U32 164, 0, implicit-def $scc @@ -106,17 +128,23 @@ body: | ; MUBUFW32-LABEL: name: s_add_u32__kernel__literal__fi_offset96__offset_literal_live_scc ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $sgpr7 = S_ADD_U32 164, 0, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW64-LABEL: name: s_add_u32__kernel__literal__fi_offset96__offset_literal_live_scc - ; FLATSCRW64: renamable $sgpr7 = S_ADD_U32 164, 0, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_ADD_U32 164, 0, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_add_u32__kernel__literal__fi_offset96__offset_literal_live_scc - ; FLATSCRW32: renamable $sgpr7 = S_ADD_U32 164, 0, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_ADD_U32 164, 0, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_ADD_U32 68, %stack.1, implicit-def $scc SI_RETURN implicit $sgpr7, implicit $scc diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir index 7f370b2cca658..71e7b67e5b2d4 100644 --- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir +++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir @@ -33,6 +33,982 @@ body: | ; GFX8-LABEL: name: s_copy_frame_index_elimination_failure_pei ; GFX8: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr4, $vgpr31, $vgpr40, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr144 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr145 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr146 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr147 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr148 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr149 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr150 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr151 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr160 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr161 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr162 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr163 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr164 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr165 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr166 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr167 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr176 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr177 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr178 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr179 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr180 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr181 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr182 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr183 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr193 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr194 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr195 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr196 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr197 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr198 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr199 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr208 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr209 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr210 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr211 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr212 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr213 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr214 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr215 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr224 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr225 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr226 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr227 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr228 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr229 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr230 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr231 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX8-NEXT: renamable $sgpr18_sgpr19 = S_MOV_B64 $src_private_base ; GFX8-NEXT: renamable $sgpr17 = S_MOV_B32 0 ; GFX8-NEXT: undef renamable $vcc_lo = COPY undef renamable $sgpr17, implicit-def $vcc @@ -58,6 +1034,982 @@ body: | ; GFX900-LABEL: name: s_copy_frame_index_elimination_failure_pei ; GFX900: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr4, $vgpr31, $vgpr40, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr144 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr145 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr146 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr147 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr148 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr149 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr150 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr151 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr160 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr161 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr162 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr163 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr164 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr165 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr166 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr167 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr176 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr177 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr178 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr179 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr180 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr181 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr182 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr183 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr193 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr194 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr195 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr196 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr197 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr198 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr199 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr208 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr209 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr210 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr211 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr212 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr213 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr214 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr215 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr224 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr225 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr226 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr227 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr228 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr229 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr230 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr231 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX900-NEXT: renamable $sgpr18_sgpr19 = S_MOV_B64 $src_private_base ; GFX900-NEXT: renamable $sgpr17 = S_MOV_B32 0 ; GFX900-NEXT: undef renamable $vcc_lo = COPY undef renamable $sgpr17, implicit-def $vcc @@ -83,6 +2035,1014 @@ body: | ; GFX90A-LABEL: name: s_copy_frame_index_elimination_failure_pei ; GFX90A: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr4, $vgpr31, $vgpr40, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr144 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr145 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr146 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr147 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr148 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr149 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr150 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr151 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr160 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr161 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr162 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr163 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr164 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr165 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr166 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr167 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr176 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr177 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr178 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr179 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr180 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr181 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr182 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr183 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr193 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr194 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr195 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr196 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr197 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr198 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr199 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr208 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr209 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr210 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr211 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr212 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr213 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr214 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr215 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr224 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr225 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr226 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr227 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr228 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr229 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr230 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr231 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX90A-NEXT: renamable $sgpr18_sgpr19 = S_MOV_B64 $src_private_base ; GFX90A-NEXT: renamable $sgpr17 = S_MOV_B32 0 ; GFX90A-NEXT: undef renamable $vcc_lo = COPY undef renamable $sgpr17, implicit-def $vcc @@ -108,6 +3068,982 @@ body: | ; GFX1010-LABEL: name: s_copy_frame_index_elimination_failure_pei ; GFX1010: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr4, $vgpr31, $vgpr40, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31 ; GFX1010-NEXT: {{ $}} + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr144 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr145 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr146 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr147 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr148 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr149 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr150 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr151 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr160 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr161 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr162 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr163 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr164 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr165 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr166 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr167 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr176 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr177 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr178 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr179 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr180 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr181 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr182 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr183 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr193 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr194 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr195 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr196 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr197 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr198 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr199 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr208 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr209 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr210 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr211 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr212 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr213 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr214 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr215 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr224 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr225 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr226 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr227 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr228 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr229 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr230 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr231 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX1010-NEXT: renamable $sgpr18_sgpr19 = S_MOV_B64 $src_private_base ; GFX1010-NEXT: renamable $sgpr17 = S_MOV_B32 0 ; GFX1010-NEXT: undef renamable $vcc_lo = COPY undef renamable $sgpr17, implicit-def $vcc_lo @@ -133,6 +4069,982 @@ body: | ; GFX1100-LABEL: name: s_copy_frame_index_elimination_failure_pei ; GFX1100: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr4, $vgpr31, $vgpr40, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31 ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr144 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr145 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr146 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr147 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr148 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr149 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr150 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr151 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr160 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr161 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr162 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr163 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr164 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr165 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr166 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr167 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr176 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr177 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr178 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr179 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr180 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr181 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr182 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr183 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr193 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr194 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr195 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr196 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr197 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr198 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr199 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr208 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr209 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr210 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr211 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr212 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr213 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr214 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr215 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr224 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr225 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr226 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr227 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr228 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr229 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr230 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr231 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX1100-NEXT: renamable $sgpr18_sgpr19 = S_MOV_B64 $src_private_base ; GFX1100-NEXT: renamable $sgpr17 = S_MOV_B32 0 ; GFX1100-NEXT: undef renamable $vcc_lo = COPY undef renamable $sgpr17, implicit-def $vcc_lo @@ -158,6 +5070,982 @@ body: | ; GFX1200-LABEL: name: s_copy_frame_index_elimination_failure_pei ; GFX1200: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr2, $vgpr4, $vgpr31, $vgpr40, $vgpr63, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31 ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr144 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr145 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr146 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr147 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr148 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr149 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr150 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr151 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr160 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr161 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr162 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr163 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr164 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr165 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr166 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr167 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr176 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr177 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr178 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr179 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr180 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr181 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr182 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr183 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr193 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr194 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr195 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr196 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr197 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr198 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr199 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr208 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr209 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr210 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr211 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr212 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr213 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr214 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr215 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr224 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr225 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr226 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr227 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr228 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr229 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr230 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr231 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX1200-NEXT: renamable $sgpr18_sgpr19 = S_MOV_B64 $src_private_base ; GFX1200-NEXT: renamable $sgpr17 = S_MOV_B32 0 ; GFX1200-NEXT: undef renamable $vcc_lo = COPY undef renamable $sgpr17, implicit-def $vcc_lo @@ -216,6 +6104,9 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc ; GFX8: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX8-NEXT: V_CMP_EQ_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; GFX8-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec @@ -227,6 +6118,9 @@ body: | ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc ; GFX900: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX900-NEXT: V_CMP_EQ_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; GFX900-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX900-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec @@ -237,6 +6131,9 @@ body: | ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc ; GFX90A: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX90A-NEXT: V_CMP_EQ_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; GFX90A-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX90A-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec @@ -247,6 +6144,9 @@ body: | ; GFX1010-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc ; GFX1010: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX1010-NEXT: {{ $}} + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX1010-NEXT: V_CMP_EQ_U32_e32 0, killed $vgpr0, implicit-def $vcc_lo, implicit $exec ; GFX1010-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX1010-NEXT: $vgpr0 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec @@ -257,6 +6157,9 @@ body: | ; GFX1100-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc ; GFX1100: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX1100-NEXT: V_CMP_EQ_U32_e32 0, killed $vgpr0, implicit-def $vcc_lo, implicit $exec ; GFX1100-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX1100-NEXT: $sgpr0 = S_ADDC_U32 $sgpr32, 64, implicit-def $scc, implicit $scc @@ -268,6 +6171,9 @@ body: | ; GFX1200-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc ; GFX1200: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX1200-NEXT: V_CMP_EQ_U32_e32 0, killed $vgpr0, implicit-def $vcc_lo, implicit $exec ; GFX1200-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX1200-NEXT: $sgpr0 = S_ADDC_U32 $sgpr32, 64, implicit-def $scc, implicit $scc @@ -300,22 +6206,89 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX8: liveins: $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -361,22 +6334,89 @@ body: | ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX900: liveins: $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -421,22 +6461,105 @@ body: | ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX90A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr40, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr40, $agpr0, 32, $exec, 64 ; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr41, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr41, $agpr1, 32, $exec, 64 ; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr42, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr42, $agpr2, 32, $exec, 64 ; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr43, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr43, $agpr3, 32, $exec, 64 ; GFX90A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr44, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr44, $agpr4, 32, $exec, 64 ; GFX90A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr45, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr45, $agpr5, 32, $exec, 64 ; GFX90A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr46, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr46, $agpr6, 32, $exec, 64 ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr47, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr47, $agpr7, 32, $exec, 64 ; GFX90A-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr56, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr56, $agpr8, 32, $exec, 64 ; GFX90A-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr57, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr57, $agpr9, 32, $exec, 64 ; GFX90A-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr58, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr58, $agpr10, 32, $exec, 64 ; GFX90A-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr59, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr59, $agpr11, 32, $exec, 64 ; GFX90A-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr60, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr60, $agpr12, 32, $exec, 64 ; GFX90A-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr61, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr61, $agpr13, 32, $exec, 64 ; GFX90A-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr62, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr62, $agpr14, 32, $exec, 64 ; GFX90A-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr63, $agpr15, 32, $exec, 64 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -481,22 +6604,89 @@ body: | ; GFX1010-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX1010: liveins: $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX1010-NEXT: {{ $}} + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 1920 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 1792 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 1664 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 1536 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec_lo, 32, 1408 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 1280 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec_lo, 32, 1152 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec_lo, 32, 1024 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec_lo, 32, 896 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec_lo, 32, 768 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec_lo, 32, 640 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec_lo, 32, 512 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec_lo, 32, 384 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec_lo, 32, 256 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec_lo, 32, 128 ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec_lo, 32, 0 ; GFX1010-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX1010-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX1010-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -539,22 +6729,89 @@ body: | ; GFX1100-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX1100: liveins: $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 1920 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 1792 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.4, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 1664 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr43, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.5, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 1536 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.6, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec_lo, 32, 1408 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr45, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.7, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 1280 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr46, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.8, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec_lo, 32, 1152 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr47, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec_lo, 32, 1024 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr56, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.10, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec_lo, 32, 896 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr57, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.11, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec_lo, 32, 768 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr58, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.12, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec_lo, 32, 640 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr59, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.13, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec_lo, 32, 512 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr60, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.14, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec_lo, 32, 384 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr61, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.15, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec_lo, 32, 256 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr62, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.16, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec_lo, 32, 128 ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr63, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.17, addrspace 5) + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec_lo, 32, 0 ; GFX1100-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX1100-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX1100-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -598,22 +6855,89 @@ body: | ; GFX1200-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX1200: liveins: $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 1920 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 1792 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.4, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 1664 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr43, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.5, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 1536 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.6, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec_lo, 32, 1408 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr45, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.7, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 1280 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr46, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.8, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec_lo, 32, 1152 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr47, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec_lo, 32, 1024 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr56, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.10, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec_lo, 32, 896 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr57, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.11, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec_lo, 32, 768 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr58, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.12, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec_lo, 32, 640 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr59, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.13, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec_lo, 32, 512 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr60, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.14, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec_lo, 32, 384 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr61, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.15, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec_lo, 32, 256 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr62, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.16, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec_lo, 32, 128 ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr63, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.17, addrspace 5) + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec_lo, 32, 0 ; GFX1200-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX1200-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX1200-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -694,6 +7018,54 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_24_live_scc_live_vcc_no_sgpr ; GFX8: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX8-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX8-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX8-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -721,6 +7093,54 @@ body: | ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_24_live_scc_live_vcc_no_sgpr ; GFX900: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX900-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX900-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX900-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -747,6 +7167,54 @@ body: | ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_24_live_scc_live_vcc_no_sgpr ; GFX90A: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX90A-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX90A-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX90A-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -773,6 +7241,54 @@ body: | ; GFX1010-LABEL: name: materialize_fi_s_mov_b32_offset_24_live_scc_live_vcc_no_sgpr ; GFX1010: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX1010-NEXT: {{ $}} + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX1010-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX1010-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX1010-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -799,6 +7315,54 @@ body: | ; GFX1100-LABEL: name: materialize_fi_s_mov_b32_offset_24_live_scc_live_vcc_no_sgpr ; GFX1100: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX1100-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX1100-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX1100-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -826,6 +7390,54 @@ body: | ; GFX1200-LABEL: name: materialize_fi_s_mov_b32_offset_24_live_scc_live_vcc_no_sgpr ; GFX1200: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX1200-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX1200-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX1200-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -889,6 +7501,54 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_68_live_scc_no_sgpr ; GFX8: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX8-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX8-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX8-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -916,6 +7576,54 @@ body: | ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_68_live_scc_no_sgpr ; GFX900: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX900-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX900-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX900-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -942,6 +7650,54 @@ body: | ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_68_live_scc_no_sgpr ; GFX90A: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX90A-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX90A-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX90A-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -968,6 +7724,54 @@ body: | ; GFX1010-LABEL: name: materialize_fi_s_mov_b32_offset_68_live_scc_no_sgpr ; GFX1010: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX1010-NEXT: {{ $}} + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX1010-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX1010-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX1010-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -994,6 +7798,54 @@ body: | ; GFX1100-LABEL: name: materialize_fi_s_mov_b32_offset_68_live_scc_no_sgpr ; GFX1100: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX1100-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX1100-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX1100-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 @@ -1021,6 +7873,54 @@ body: | ; GFX1200-LABEL: name: materialize_fi_s_mov_b32_offset_68_live_scc_no_sgpr ; GFX1200: liveins: $sgpr4, $sgpr5, $vgpr0 ; GFX1200-NEXT: {{ $}} + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GFX1200-NEXT: S_NOP 0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GFX1200-NEXT: S_NOP 0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GFX1200-NEXT: S_NOP 0, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir index aecff1b13171d..48f1ab0ee3c30 100644 --- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir +++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir @@ -21,21 +21,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_or_b32__inline_imm__fi_offset0 - ; MUBUFW64: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_OR_B32 12, killed $sgpr4, implicit-def $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; MUBUFW32-LABEL: name: s_or_b32__inline_imm__fi_offset0 - ; MUBUFW32: $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_OR_B32 12, killed $sgpr4, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW64-LABEL: name: s_or_b32__inline_imm__fi_offset0 - ; FLATSCRW64: renamable $sgpr7 = S_OR_B32 12, $sgpr32, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: renamable $sgpr7 = S_OR_B32 12, $sgpr32, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_or_b32__inline_imm__fi_offset0 - ; FLATSCRW32: renamable $sgpr7 = S_OR_B32 12, $sgpr32, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: renamable $sgpr7 = S_OR_B32 12, $sgpr32, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_OR_B32 12, %stack.0, implicit-def $scc SI_RETURN implicit $sgpr7, implicit $scc @@ -55,24 +67,36 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: s_or_b32__literal__fi_offset96 - ; MUBUFW64: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW64-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc ; MUBUFW64-NEXT: $sgpr4 = S_ADD_I32 killed $sgpr4, 96, implicit-def $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_OR_B32 68, killed $sgpr4, implicit-def $scc ; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; MUBUFW32-LABEL: name: s_or_b32__literal__fi_offset96 - ; MUBUFW32: $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def $scc + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUFW32-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def $scc ; MUBUFW32-NEXT: $sgpr4 = S_ADD_I32 killed $sgpr4, 96, implicit-def $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_OR_B32 68, killed $sgpr4, implicit-def $scc ; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW64-LABEL: name: s_or_b32__literal__fi_offset96 - ; FLATSCRW64: $sgpr4 = S_ADD_I32 $sgpr32, 96, implicit-def $scc + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW64-NEXT: $sgpr4 = S_ADD_I32 $sgpr32, 96, implicit-def $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = S_OR_B32 68, killed $sgpr4, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc ; ; FLATSCRW32-LABEL: name: s_or_b32__literal__fi_offset96 - ; FLATSCRW32: $sgpr4 = S_ADD_I32 $sgpr32, 96, implicit-def $scc + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCRW32-NEXT: $sgpr4 = S_ADD_I32 $sgpr32, 96, implicit-def $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = S_OR_B32 68, killed $sgpr4, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc renamable $sgpr7 = S_OR_B32 68, %stack.1, implicit-def $scc @@ -96,6 +120,9 @@ body: | ; MUBUFW64-LABEL: name: s_or_b32__sgpr__fi_literal_offset ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc ; MUBUFW64-NEXT: $sgpr4 = S_ADD_I32 killed $sgpr4, 80, implicit-def $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_OR_B32 $sgpr8, killed $sgpr4, implicit-def $scc @@ -104,6 +131,9 @@ body: | ; MUBUFW32-LABEL: name: s_or_b32__sgpr__fi_literal_offset ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def $scc ; MUBUFW32-NEXT: $sgpr4 = S_ADD_I32 killed $sgpr4, 80, implicit-def $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_OR_B32 $sgpr8, killed $sgpr4, implicit-def $scc @@ -112,6 +142,9 @@ body: | ; FLATSCRW64-LABEL: name: s_or_b32__sgpr__fi_literal_offset ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: $sgpr4 = S_ADD_I32 $sgpr32, 80, implicit-def $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = S_OR_B32 $sgpr8, killed $sgpr4, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -119,6 +152,9 @@ body: | ; FLATSCRW32-LABEL: name: s_or_b32__sgpr__fi_literal_offset ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: $sgpr4 = S_ADD_I32 $sgpr32, 80, implicit-def $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = S_OR_B32 $sgpr8, killed $sgpr4, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -143,6 +179,9 @@ body: | ; MUBUFW64-LABEL: name: s_or_b32__sgpr__fi_inlineimm_offset ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc ; MUBUFW64-NEXT: $sgpr4 = S_ADD_I32 killed $sgpr4, 32, implicit-def $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_OR_B32 $sgpr8, killed $sgpr4, implicit-def $scc @@ -151,6 +190,9 @@ body: | ; MUBUFW32-LABEL: name: s_or_b32__sgpr__fi_inlineimm_offset ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def $scc ; MUBUFW32-NEXT: $sgpr4 = S_ADD_I32 killed $sgpr4, 32, implicit-def $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_OR_B32 $sgpr8, killed $sgpr4, implicit-def $scc @@ -159,6 +201,9 @@ body: | ; FLATSCRW64-LABEL: name: s_or_b32__sgpr__fi_inlineimm_offset ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: $sgpr4 = S_ADD_I32 $sgpr32, 32, implicit-def $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = S_OR_B32 $sgpr8, killed $sgpr4, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -166,6 +211,9 @@ body: | ; FLATSCRW32-LABEL: name: s_or_b32__sgpr__fi_inlineimm_offset ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: $sgpr4 = S_ADD_I32 $sgpr32, 32, implicit-def $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = S_OR_B32 $sgpr8, killed $sgpr4, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -190,6 +238,9 @@ body: | ; MUBUFW64-LABEL: name: s_and_b32__sgpr__fi_literal_offset ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW64-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc ; MUBUFW64-NEXT: $sgpr4 = S_ADD_I32 killed $sgpr4, 80, implicit-def $scc ; MUBUFW64-NEXT: renamable $sgpr7 = S_AND_B32 $sgpr8, killed $sgpr4, implicit-def $scc @@ -198,6 +249,9 @@ body: | ; MUBUFW32-LABEL: name: s_and_b32__sgpr__fi_literal_offset ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; MUBUFW32-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def $scc ; MUBUFW32-NEXT: $sgpr4 = S_ADD_I32 killed $sgpr4, 80, implicit-def $scc ; MUBUFW32-NEXT: renamable $sgpr7 = S_AND_B32 $sgpr8, killed $sgpr4, implicit-def $scc @@ -206,6 +260,9 @@ body: | ; FLATSCRW64-LABEL: name: s_and_b32__sgpr__fi_literal_offset ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW64-NEXT: $sgpr4 = S_ADD_I32 $sgpr32, 80, implicit-def $scc ; FLATSCRW64-NEXT: renamable $sgpr7 = S_AND_B32 $sgpr8, killed $sgpr4, implicit-def $scc ; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc @@ -213,6 +270,9 @@ body: | ; FLATSCRW32-LABEL: name: s_and_b32__sgpr__fi_literal_offset ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 ; FLATSCRW32-NEXT: $sgpr4 = S_ADD_I32 $sgpr32, 80, implicit-def $scc ; FLATSCRW32-NEXT: renamable $sgpr7 = S_AND_B32 $sgpr8, killed $sgpr4, implicit-def $scc ; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir index 348743644ce4f..fd296666514ad 100644 --- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir +++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir @@ -16,11 +16,17 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0 - ; MUBUFW32: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; MUBUFW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW32-NEXT: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr0 ; ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0 - ; FLATSCRW32: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW32-NEXT: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr0 renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 12, %stack.0, 0, implicit $exec SI_RETURN implicit $vgpr0, implicit $sgpr0 @@ -39,12 +45,18 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__live_vcc - ; MUBUFW32: renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; MUBUFW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW32-NEXT: renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 killed $vgpr0, 0, 0, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr0 ; ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__live_vcc - ; FLATSCRW32: renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW32-NEXT: renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 killed $vgpr0, 0, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr0 renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 12, %stack.0, 0, implicit $exec @@ -64,12 +76,18 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__clamp - ; MUBUFW32: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; MUBUFW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW32-NEXT: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 killed $vgpr0, 0, 1, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__clamp - ; FLATSCRW32: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW32-NEXT: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 killed $vgpr0, 0, 1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 12, %stack.0, 1, implicit $exec @@ -89,12 +107,18 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__live_vcc_clamp - ; MUBUFW32: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; MUBUFW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 killed $vgpr0, 0, 1, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc_lo ; ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__live_vcc_clamp - ; FLATSCRW32: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 killed $vgpr0, 0, 1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc_lo renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 12, %stack.0, 1, implicit $exec @@ -118,6 +142,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc_lo @@ -125,6 +152,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc_lo @@ -149,6 +179,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr_clamp ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 1, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc_lo @@ -156,6 +189,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr_clamp ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc_lo @@ -181,6 +217,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr ; MUBUFW32: liveins: $vgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr0, dead renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0, dead renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 @@ -188,6 +227,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr ; FLATSCRW32: liveins: $vgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0, dead renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0, dead renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 @@ -213,6 +255,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__clamp ; MUBUFW32: liveins: $vgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr0, dead renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0, dead renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 1, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 @@ -220,6 +265,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__clamp ; FLATSCRW32: liveins: $vgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0, dead renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0, dead renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 @@ -245,6 +293,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__live_vcc ; MUBUFW32: liveins: $vgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc_lo @@ -252,6 +303,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__live_vcc ; FLATSCRW32: liveins: $vgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc_lo @@ -274,11 +328,15 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset_literal__kernel__clamp - ; MUBUFW32: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 84, 0, 1, implicit $exec + ; MUBUFW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; MUBUFW32-NEXT: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 84, 0, 1, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset_literal__kernel__clamp - ; FLATSCRW32: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 84, 0, 1, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 84, 0, 1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 12, %stack.1, 1, implicit $exec SI_RETURN implicit $vgpr0 @@ -302,6 +360,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; MUBUFW32: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; MUBUFW32-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 @@ -310,6 +371,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; FLATSCRW32: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $vcc_lo = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; FLATSCRW32-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 @@ -337,12 +401,16 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__kernel_fi_offset0__other_vgpr_live_after ; MUBUFW32: liveins: $vgpr1 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: renamable $vgpr0, renamable $sgpr8 = V_ADD_CO_U32_e64 $vgpr1, 0, 0, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 ; ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__kernel_fi_offset0__other_vgpr_live_after ; FLATSCRW32: liveins: $vgpr1 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $sgpr8 = V_ADD_CO_U32_e64 $vgpr1, 0, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 renamable $vgpr0, renamable $sgpr8 = V_ADD_CO_U32_e64 renamable $vgpr1, %stack.0, 0, implicit $exec @@ -366,12 +434,16 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__kernel__other_vgpr_live_after__fi_offset0 ; MUBUFW32: liveins: $vgpr1 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: renamable $vgpr0, renamable $sgpr8 = V_ADD_CO_U32_e64 0, $vgpr1, 0, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 ; ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__kernel__other_vgpr_live_after__fi_offset0 ; FLATSCRW32: liveins: $vgpr1 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0, renamable $sgpr8 = V_ADD_CO_U32_e64 0, $vgpr1, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 renamable $vgpr0, renamable $sgpr8 = V_ADD_CO_U32_e64 %stack.0, renamable $vgpr1, 0, implicit $exec @@ -396,11 +468,15 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__identity_vgpr__fi_offset0__kernel ; MUBUFW32: liveins: $vgpr0 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__identity_vgpr__fi_offset0__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, renamable dead $vcc_lo = V_ADD_CO_U32_e64 $vgpr0, %stack.0, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -424,11 +500,15 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__fi_offset0__identity_vgpr__kernel ; MUBUFW32: liveins: $vgpr0 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__fi_offset0__identity_vgpr__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, renamable dead $vcc_lo = V_ADD_CO_U32_e64 %stack.0, $vgpr0, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -453,12 +533,16 @@ body: | ; MUBUFW32-LABEL: name: v_add_co_u32_e64__identity_vgpr__fi_offset32__kernel ; MUBUFW32: liveins: $vgpr0 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: renamable $vgpr0, dead renamable $vcc_lo = V_ADD_CO_U32_e64 $vgpr0, 32, 0, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__identity_vgpr__fi_offset32__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0, dead renamable $vcc_lo = V_ADD_CO_U32_e64 $vgpr0, 32, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, renamable dead $vcc_lo = V_ADD_CO_U32_e64 $vgpr0, %stack.1, 0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir index ade7b4266e9e6..95d9f226c4634 100644 --- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir +++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir @@ -22,12 +22,18 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e32__inline_imm__fi_offset0 - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 12, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__inline_imm__fi_offset0 - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 12, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 12, %stack.0, implicit-def dead $vcc, implicit $exec @@ -47,13 +53,19 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e32__inline_imm__fi_offset0_live_vcc - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 12, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__inline_imm__fi_offset0_live_vcc - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 12, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc @@ -75,12 +87,18 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e32__inline_imm___fi_offset_inline_imm - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 28, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__inline_imm___fi_offset_inline_imm - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 28, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 12, %stack.1, implicit-def dead $vcc, implicit $exec @@ -101,13 +119,19 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e32__inline_imm___fi_offset_inline_imm_live_vcc - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 28, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__inline_imm___fi_offset_inline_imm_live_vcc - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 28, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc @@ -128,12 +152,18 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e32__literal__fi_offset0 - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 68, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__literal__fi_offset0 - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 68, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 68, %stack.0, implicit-def dead $vcc, implicit $exec @@ -153,13 +183,19 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e32__literal__fi_offset0_live_vcc - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 68, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__literal__fi_offset0_live_vcc - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 68, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc @@ -181,12 +217,18 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e32__literal__fi_offset0__offset_inlineimm - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 100, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__literal__fi_offset0__offset_inlineimm - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 100, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 68, %stack.1, implicit-def dead $vcc, implicit $exec @@ -207,13 +249,19 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e32__literal__fi_offset0__offset_inlineimm_live_vcc - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 100, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__literal__fi_offset0__offset_inlineimm_live_vcc - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 100, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc @@ -237,6 +285,9 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__vgpr__fi_offset0 ; MUBUFW64: liveins: $vgpr1 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW64-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $vgpr1, killed $vgpr2, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 @@ -244,6 +295,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__vgpr__fi_offset0 ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr32, $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 $vgpr1, %stack.0, implicit-def dead $vcc, implicit $exec @@ -266,6 +320,9 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_offset0__vgpr ; MUBUFW64: liveins: $vgpr1 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW64-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $vgpr1, killed $vgpr2, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 @@ -273,6 +330,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__fi_offset0__vgpr ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr32, $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 %stack.0, $vgpr1, implicit-def dead $vcc, implicit $exec @@ -296,6 +356,9 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__vgpr__fi_literal_offset ; MUBUFW64: liveins: $vgpr1 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW64-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $vgpr1, killed $vgpr2, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 128, killed $vgpr0, implicit-def dead $vcc, implicit $exec @@ -304,6 +367,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__vgpr__fi_literal_offset ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr32, $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 128, killed $vgpr0, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 @@ -328,6 +394,9 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_literal_offset__vgpr ; MUBUFW64: liveins: $vgpr1 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW64-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $vgpr1, killed $vgpr2, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 128, killed $vgpr0, implicit-def dead $vcc, implicit $exec @@ -336,6 +405,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__fi_literal_offset__vgpr ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr32, $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 128, killed $vgpr0, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 @@ -360,6 +432,9 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__sgpr__fi_literal_offset ; MUBUFW64: liveins: $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr8, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 128, killed $vgpr0, implicit-def dead $vcc, implicit $exec @@ -368,6 +443,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__sgpr__fi_literal_offset ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr8, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 128, killed $vgpr0, implicit-def dead $vcc, implicit $exec @@ -389,13 +467,19 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0 - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 12, killed $vgpr1, 0, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr0, 0, 0, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0 - ; FLATSCRW64: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr0, 0, 0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 12, %stack.0, 0, implicit $exec @@ -415,13 +499,19 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__clamp - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 12, killed $vgpr1, 0, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 killed $vgpr0, 0, 1, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__clamp - ; FLATSCRW64: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 killed $vgpr0, 0, 1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 12, %stack.0, 1, implicit $exec @@ -441,13 +531,19 @@ machineFunctionInfo: body: | bb.0: ; MUBUFW64-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__live_vcc_clamp - ; MUBUFW64: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUFW64: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 12, killed $vgpr1, 0, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr0, 0, 1, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__live_vcc_clamp - ; FLATSCRW64: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, 12, 0, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr0, 0, 1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 12, %stack.0, 1, implicit $exec @@ -471,6 +567,9 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr ; GFX7: liveins: $sgpr8 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX7-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX7-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX7-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -480,6 +579,9 @@ body: | ; GFX8-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr ; GFX8: liveins: $sgpr8 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX8-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -489,6 +591,9 @@ body: | ; GFX900-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr ; GFX900: liveins: $sgpr8 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX900-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX900-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -498,6 +603,9 @@ body: | ; GFX90A-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr ; GFX90A: liveins: $sgpr8 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX90A-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -507,6 +615,9 @@ body: | ; GFX10-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr ; GFX10: liveins: $sgpr8 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec @@ -515,6 +626,9 @@ body: | ; GFX942-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr ; GFX942: liveins: $sgpr8 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX942-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -524,6 +638,9 @@ body: | ; GFX11-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr ; GFX11: liveins: $sgpr8 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX11-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; GFX11-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; GFX11-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc @@ -531,6 +648,9 @@ body: | ; GFX12-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr ; GFX12: liveins: $sgpr8 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX12-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; GFX12-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; GFX12-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc @@ -555,6 +675,9 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr_clamp ; GFX7: liveins: $sgpr8 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX7-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX7-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX7-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -564,6 +687,9 @@ body: | ; GFX8-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr_clamp ; GFX8: liveins: $sgpr8 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX8-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -573,6 +699,9 @@ body: | ; GFX900-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr_clamp ; GFX900: liveins: $sgpr8 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX900-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX900-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -582,6 +711,9 @@ body: | ; GFX90A-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr_clamp ; GFX90A: liveins: $sgpr8 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX90A-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -591,6 +723,9 @@ body: | ; GFX10-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr_clamp ; GFX10: liveins: $sgpr8 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 1, implicit $exec @@ -599,6 +734,9 @@ body: | ; GFX942-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr_clamp ; GFX942: liveins: $sgpr8 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX942-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -608,6 +746,9 @@ body: | ; GFX11-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr_clamp ; GFX11: liveins: $sgpr8 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX11-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; GFX11-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 1, implicit $exec ; GFX11-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc @@ -615,6 +756,9 @@ body: | ; GFX12-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr_clamp ; GFX12: liveins: $sgpr8 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX12-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; GFX12-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 1, implicit $exec ; GFX12-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc @@ -640,6 +784,9 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr ; GFX7: liveins: $vgpr8 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX7-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX7-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX7-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -649,6 +796,9 @@ body: | ; GFX8-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr ; GFX8: liveins: $vgpr8 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX8-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -658,6 +808,9 @@ body: | ; GFX900-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr ; GFX900: liveins: $vgpr8 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX900-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX900-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -667,6 +820,9 @@ body: | ; GFX90A-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr ; GFX90A: liveins: $vgpr8 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX90A-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -676,6 +832,9 @@ body: | ; GFX10-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr ; GFX10: liveins: $vgpr8 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX10-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX10-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec @@ -684,6 +843,9 @@ body: | ; GFX942-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr ; GFX942: liveins: $vgpr8 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX942-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; GFX942-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr1, killed $vgpr0, 0, implicit $exec @@ -692,6 +854,9 @@ body: | ; GFX11-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr ; GFX11: liveins: $vgpr8 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX11-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; GFX11-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; GFX11-NEXT: SI_RETURN implicit $vgpr0 @@ -699,6 +864,9 @@ body: | ; GFX12-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr ; GFX12: liveins: $vgpr8 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX12-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; GFX12-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; GFX12-NEXT: SI_RETURN implicit $vgpr0 @@ -724,6 +892,9 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__clamp ; GFX7: liveins: $vgpr8 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX7-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX7-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX7-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -733,6 +904,9 @@ body: | ; GFX8-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__clamp ; GFX8: liveins: $vgpr8 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX8-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -742,6 +916,9 @@ body: | ; GFX900-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__clamp ; GFX900: liveins: $vgpr8 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX900-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX900-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -751,6 +928,9 @@ body: | ; GFX90A-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__clamp ; GFX90A: liveins: $vgpr8 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX90A-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -760,6 +940,9 @@ body: | ; GFX10-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__clamp ; GFX10: liveins: $vgpr8 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX10-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX10-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 1, implicit $exec @@ -768,6 +951,9 @@ body: | ; GFX942-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__clamp ; GFX942: liveins: $vgpr8 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX942-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; GFX942-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr1, killed $vgpr0, 1, implicit $exec @@ -776,6 +962,9 @@ body: | ; GFX11-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__clamp ; GFX11: liveins: $vgpr8 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX11-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; GFX11-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 1, implicit $exec ; GFX11-NEXT: SI_RETURN implicit $vgpr0 @@ -783,6 +972,9 @@ body: | ; GFX12-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__clamp ; GFX12: liveins: $vgpr8 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX12-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; GFX12-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 1, implicit $exec ; GFX12-NEXT: SI_RETURN implicit $vgpr0 @@ -808,6 +1000,9 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__live_vcc ; GFX7: liveins: $vgpr8 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX7-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX7-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX7-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -817,6 +1012,9 @@ body: | ; GFX8-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__live_vcc ; GFX8: liveins: $vgpr8 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX8-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -826,6 +1024,9 @@ body: | ; GFX900-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__live_vcc ; GFX900: liveins: $vgpr8 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX900-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX900-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -835,6 +1036,9 @@ body: | ; GFX90A-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__live_vcc ; GFX90A: liveins: $vgpr8 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX90A-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -844,6 +1048,9 @@ body: | ; GFX10-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__live_vcc ; GFX10: liveins: $vgpr8 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec @@ -852,6 +1059,9 @@ body: | ; GFX942-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__live_vcc ; GFX942: liveins: $vgpr8 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX942-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; GFX942-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr1, killed $vgpr0, 0, implicit $exec @@ -860,6 +1070,9 @@ body: | ; GFX11-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__live_vcc ; GFX11: liveins: $vgpr8 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX11-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; GFX11-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; GFX11-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc @@ -867,6 +1080,9 @@ body: | ; GFX12-LABEL: name: v_add_co_u32_e64__fi_literal_offset__vgpr__live_vcc ; GFX12: liveins: $vgpr8 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX12-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; GFX12-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; GFX12-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc @@ -890,13 +1106,17 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__inline_imm__fi_offset0__kernel ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__inline_imm__fi_offset0__kernel - ; FLATSCRW64: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 12, %stack.0, implicit-def dead $vcc, implicit $exec SI_RETURN implicit $vgpr0 @@ -918,6 +1138,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__inline_imm__fi_offset0__kernel__live_vcc ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec @@ -925,7 +1147,9 @@ body: | ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__inline_imm__fi_offset0__kernel__live_vcc - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 0, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 12, killed $vgpr1, implicit-def $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc renamable $vgpr0 = V_ADD_CO_U32_e32 12, %stack.0, implicit-def $vcc, implicit $exec @@ -949,13 +1173,17 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__inline_imm__fi_offset_literal__kernel ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 84, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__inline_imm__fi_offset_literal__kernel - ; FLATSCRW64: renamable $vgpr0 = V_MOV_B32_e32 84, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 84, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 12, %stack.1, implicit-def dead $vcc, implicit $exec SI_RETURN implicit $vgpr0 @@ -978,6 +1206,8 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset_literal__kernel__clamp ; GFX7: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX7-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX7-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX7-NEXT: $vgpr1 = V_MOV_B32_e32 72, implicit $exec @@ -987,6 +1217,8 @@ body: | ; GFX8-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset_literal__kernel__clamp ; GFX8: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX8-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 72, implicit $exec @@ -996,6 +1228,8 @@ body: | ; GFX900-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset_literal__kernel__clamp ; GFX900: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX900-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX900-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX900-NEXT: $vgpr1 = V_MOV_B32_e32 72, implicit $exec @@ -1005,6 +1239,8 @@ body: | ; GFX90A-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset_literal__kernel__clamp ; GFX90A: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX90A-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX90A-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 72, implicit $exec @@ -1014,22 +1250,30 @@ body: | ; GFX10-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset_literal__kernel__clamp ; GFX10: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX10-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX10-NEXT: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 84, 0, 1, implicit $exec ; GFX10-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX942-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset_literal__kernel__clamp - ; GFX942: $sgpr4 = S_MOV_B32 72 + ; GFX942: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; GFX942-NEXT: $sgpr4 = S_MOV_B32 72 ; GFX942-NEXT: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 12, killed $sgpr4, 1, implicit $exec ; GFX942-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX11-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset_literal__kernel__clamp - ; GFX11: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 84, 0, 1, implicit $exec + ; GFX11: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; GFX11-NEXT: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 84, 0, 1, implicit $exec ; GFX11-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX12-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset_literal__kernel__clamp - ; GFX12: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 84, 0, 1, implicit $exec + ; GFX12: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; GFX12-NEXT: renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 84, 0, 1, implicit $exec ; GFX12-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, dead $vcc = V_ADD_CO_U32_e64 12, %stack.1, 1, implicit $exec SI_RETURN implicit $vgpr0 @@ -1053,6 +1297,9 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX7: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX7-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX7-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX7-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec @@ -1065,6 +1312,9 @@ body: | ; GFX8-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX8-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec @@ -1077,6 +1327,9 @@ body: | ; GFX900-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX900: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX900-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec @@ -1089,6 +1342,9 @@ body: | ; GFX90A-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX90A: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX90A-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec @@ -1101,6 +1357,9 @@ body: | ; GFX10-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX10: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec @@ -1112,6 +1371,9 @@ body: | ; GFX942-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX942: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX942-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX942-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec @@ -1124,6 +1386,9 @@ body: | ; GFX11-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX11: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX11-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; GFX11-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; GFX11-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 @@ -1132,6 +1397,9 @@ body: | ; GFX12-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX12: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX12-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; GFX12-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec ; GFX12-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 @@ -1160,6 +1428,9 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_literal_offset__sgpr__scavenge_spill_required ; MUBUFW64: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW64-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr8, killed $vgpr1, implicit-def dead $vcc, implicit $exec @@ -1171,6 +1442,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__fi_literal_offset__sgpr__scavenge_spill_required ; FLATSCRW64: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr8, killed $vgpr1, implicit-def dead $vcc, implicit $exec @@ -1202,6 +1476,9 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_literal_offset__vgpr__scavenge_spill_required ; MUBUFW64: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW64-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $vgpr8, killed $vgpr1, implicit-def dead $vcc, implicit $exec @@ -1213,6 +1490,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__fi_literal_offset__vgpr__scavenge_spill_required ; FLATSCRW64: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr32, $vgpr8, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 128, killed $vgpr0, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 @@ -1240,6 +1520,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__kernel_fi_offset0__other_vgpr_live_after ; MUBUFW64: liveins: $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec @@ -1248,6 +1530,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__kernel_fi_offset0__other_vgpr_live_after ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 renamable $vgpr0 = V_ADD_CO_U32_e32 renamable $vgpr1, %stack.0, implicit-def dead $vcc, implicit $exec @@ -1271,6 +1555,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e64__kernel_fi_offset0__other_vgpr_live_after ; MUBUFW64: liveins: $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 $vgpr1, 0, 0, implicit $exec @@ -1279,6 +1565,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__kernel_fi_offset0__other_vgpr_live_after ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 $vgpr1, 0, 0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 renamable $vgpr1, %stack.0, 0, implicit $exec @@ -1302,6 +1590,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e64__kernel__other_vgpr_live_after__fi_offset0 ; MUBUFW64: liveins: $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 0, $vgpr1, 0, implicit $exec @@ -1310,6 +1600,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__kernel__other_vgpr_live_after__fi_offset0 ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 0, $vgpr1, 0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 %stack.0, renamable $vgpr1, 0, implicit $exec @@ -1334,6 +1626,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__identity_vgpr__fi_offset0__kernel ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 @@ -1341,6 +1635,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__identity_vgpr__fi_offset0__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 $vgpr0, %stack.0, implicit-def dead $vcc, implicit $exec SI_RETURN implicit $vgpr0 @@ -1363,6 +1659,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_offset0__identity_vgpr__kernel ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 @@ -1370,6 +1668,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__fi_offset0__identity_vgpr__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 %stack.0, $vgpr0, implicit-def dead $vcc, implicit $exec SI_RETURN implicit $vgpr0 @@ -1393,6 +1693,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e64__identity_vgpr__fi_offset0__kernel ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 @@ -1400,6 +1702,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__identity_vgpr__fi_offset0__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, renamable dead $vcc = V_ADD_CO_U32_e64 $vgpr0, %stack.0, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -1423,6 +1727,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_offset0__identity_vgpr__kernel ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 @@ -1430,6 +1736,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__fi_offset0__identity_vgpr__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, renamable dead $vcc = V_ADD_CO_U32_e64 %stack.0, $vgpr0, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -1452,6 +1760,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_offset0__identity_vgpr__kernel_kill ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 @@ -1459,6 +1769,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__fi_offset0__identity_vgpr__kernel_kill ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 %stack.0, killed $vgpr0, implicit-def dead $vcc, implicit $exec SI_RETURN implicit $vgpr0 @@ -1481,6 +1793,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_offset0__identity_vgpr__kernel_live_vcc ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec @@ -1489,6 +1803,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__fi_offset0__identity_vgpr__kernel_live_vcc ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc renamable $vgpr0 = V_ADD_CO_U32_e32 %stack.0, $vgpr0, implicit-def $vcc, implicit $exec @@ -1514,6 +1830,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__identity_vgpr__fi_offset32__kernel ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 32, $vgpr0, implicit-def dead $vcc, implicit $exec @@ -1522,6 +1840,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__identity_vgpr__fi_offset32__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 32, $vgpr0, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 $vgpr0, %stack.1, implicit-def dead $vcc, implicit $exec @@ -1548,6 +1868,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__identity_vgpr__fi_offset72__kernel ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 72, $vgpr0, implicit-def dead $vcc, implicit $exec @@ -1556,6 +1878,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__identity_vgpr__fi_offset72__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 72, $vgpr0, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 $vgpr0, %stack.1, implicit-def dead $vcc, implicit $exec @@ -1581,6 +1905,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_offset72__identity_vgpr__kernel ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 72, $vgpr0, implicit-def dead $vcc, implicit $exec @@ -1589,6 +1915,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__fi_offset72__identity_vgpr__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 72, $vgpr0, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 %stack.1, $vgpr0, implicit-def dead $vcc, implicit $exec @@ -1614,6 +1942,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_offset32__identity_vgpr__kernel ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 32, $vgpr0, implicit-def dead $vcc, implicit $exec @@ -1622,6 +1952,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__fi_offset32__identity_vgpr__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 32, $vgpr0, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 %stack.1, $vgpr0, implicit-def dead $vcc, implicit $exec @@ -1647,6 +1979,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e64__identity_vgpr__fi_offset32__kernel ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr0, 32, 0, implicit $exec @@ -1655,6 +1989,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__identity_vgpr__fi_offset32__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $vgpr0, 32, 0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, renamable dead $vcc = V_ADD_CO_U32_e64 $vgpr0, %stack.1, 0, implicit $exec @@ -1679,6 +2015,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_sgpr_kernel ; MUBUFW64: liveins: $sgpr4, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 killed $sgpr4, implicit $exec @@ -1687,6 +2025,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__fi_sgpr_kernel ; FLATSCRW64: liveins: $sgpr4 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 killed $sgpr4, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 %stack.0, killed $sgpr4, 0, implicit $exec @@ -1710,6 +2050,11 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_sgpr_func ; MUBUFW64: liveins: $sgpr4 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 killed $sgpr4, killed $vgpr1, 0, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 @@ -1717,6 +2062,11 @@ body: | ; GFX942-LABEL: name: v_add_co_u32_e64__fi_sgpr_func ; GFX942: liveins: $sgpr4 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX942-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 killed $sgpr4, killed $vgpr1, 0, implicit $exec ; GFX942-NEXT: SI_RETURN implicit $vgpr0 @@ -1724,12 +2074,22 @@ body: | ; GFX11-LABEL: name: v_add_co_u32_e64__fi_sgpr_func ; GFX11: liveins: $sgpr4 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 ; GFX11-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 $sgpr32, killed $sgpr4, 0, implicit $exec ; GFX11-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX12-LABEL: name: v_add_co_u32_e64__fi_sgpr_func ; GFX12: liveins: $sgpr4 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 ; GFX12-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 $sgpr32, killed $sgpr4, 0, implicit $exec ; GFX12-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 %stack.0, killed $sgpr4, 0, implicit $exec @@ -1754,6 +2114,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_inc_same_vgpr_kernel ; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 @@ -1761,6 +2123,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__fi_inc_same_vgpr_kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 %stack.0, killed $vgpr0, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -1783,6 +2147,11 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_inc_same_vgpr_func ; MUBUFW64: liveins: $vgpr0 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 killed $vgpr0, killed $vgpr1, 0, implicit $exec ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 @@ -1790,6 +2159,11 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__fi_inc_same_vgpr_func ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 ; FLATSCRW64-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 $sgpr32, killed $vgpr0, 0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 %stack.0, killed $vgpr0, 0, implicit $exec @@ -1814,6 +2188,8 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_sgpr_kernel_live_co ; MUBUFW64: liveins: $sgpr4, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: {{ $}} + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW64-NEXT: renamable $vgpr0, renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 0, killed $sgpr4, 0, implicit $exec @@ -1822,6 +2198,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_co_u32_e64__fi_sgpr_kernel_live_co ; FLATSCRW64: liveins: $sgpr4 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0, renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 0, killed $sgpr4, 0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr4_sgpr5 renamable $vgpr0, renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 %stack.0, killed $sgpr4, 0, implicit $exec @@ -1846,6 +2224,8 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64_fi_sgpr_clobbered_register ; GFX7: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX7-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX7-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $noreg, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 ; GFX7-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 @@ -1858,6 +2238,8 @@ body: | ; GFX8-LABEL: name: v_add_co_u32_e64_fi_sgpr_clobbered_register ; GFX8: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX8-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $noreg, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 ; GFX8-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 @@ -1870,6 +2252,8 @@ body: | ; GFX900-LABEL: name: v_add_co_u32_e64_fi_sgpr_clobbered_register ; GFX900: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX900-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX900-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $noreg, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 ; GFX900-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 @@ -1882,6 +2266,8 @@ body: | ; GFX90A-LABEL: name: v_add_co_u32_e64_fi_sgpr_clobbered_register ; GFX90A: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX90A-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX90A-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $noreg, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 ; GFX90A-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 @@ -1894,6 +2280,8 @@ body: | ; GFX10-LABEL: name: v_add_co_u32_e64_fi_sgpr_clobbered_register ; GFX10: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10-NEXT: $sgpr96_sgpr97_sgpr98_sgpr99 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX10-NEXT: $sgpr96 = S_ADD_U32 $sgpr96, $noreg, implicit-def $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 ; GFX10-NEXT: $sgpr97 = S_ADDC_U32 $sgpr97, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 @@ -1905,6 +2293,8 @@ body: | ; GFX942-LABEL: name: v_add_co_u32_e64_fi_sgpr_clobbered_register ; GFX942: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX942-NEXT: renamable $sgpr0 = S_LSHL_B32 renamable $sgpr6, 2, implicit-def dead $scc ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 32772, implicit $exec ; GFX942-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr1, killed $sgpr0, 0, implicit $exec @@ -1914,6 +2304,8 @@ body: | ; GFX11-LABEL: name: v_add_co_u32_e64_fi_sgpr_clobbered_register ; GFX11: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11-NEXT: renamable $sgpr0 = S_LSHL_B32 renamable $sgpr6, 2, implicit-def dead $scc ; GFX11-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 32772, killed $sgpr0, 0, implicit $exec ; GFX11-NEXT: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed renamable $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, 0, 0, 0, 0, implicit $exec :: (load (s32), addrspace 5) @@ -1922,6 +2314,8 @@ body: | ; GFX12-LABEL: name: v_add_co_u32_e64_fi_sgpr_clobbered_register ; GFX12: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX12-NEXT: renamable $sgpr0 = S_LSHL_B32 renamable $sgpr6, 2, implicit-def dead $scc ; GFX12-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 32768, killed $sgpr0, 0, implicit $exec ; GFX12-NEXT: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed renamable $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, 0, 0, 0, 0, implicit $exec :: (load (s32), addrspace 5) @@ -1950,6 +2344,8 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64_sgpr_fi_clobbered_register ; GFX7: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX7-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX7-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $noreg, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 ; GFX7-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 @@ -1962,6 +2358,8 @@ body: | ; GFX8-LABEL: name: v_add_co_u32_e64_sgpr_fi_clobbered_register ; GFX8: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX8-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX8-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $noreg, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 ; GFX8-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 @@ -1974,6 +2372,8 @@ body: | ; GFX900-LABEL: name: v_add_co_u32_e64_sgpr_fi_clobbered_register ; GFX900: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX900-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX900-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $noreg, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 ; GFX900-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 @@ -1986,6 +2386,8 @@ body: | ; GFX90A-LABEL: name: v_add_co_u32_e64_sgpr_fi_clobbered_register ; GFX90A: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX90A-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX90A-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $noreg, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 ; GFX90A-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 @@ -1998,6 +2400,8 @@ body: | ; GFX10-LABEL: name: v_add_co_u32_e64_sgpr_fi_clobbered_register ; GFX10: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C, $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10-NEXT: $sgpr96_sgpr97_sgpr98_sgpr99 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX10-NEXT: $sgpr96 = S_ADD_U32 $sgpr96, $noreg, implicit-def $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 ; GFX10-NEXT: $sgpr97 = S_ADDC_U32 $sgpr97, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 @@ -2009,6 +2413,8 @@ body: | ; GFX942-LABEL: name: v_add_co_u32_e64_sgpr_fi_clobbered_register ; GFX942: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX942-NEXT: renamable $sgpr0 = S_LSHL_B32 renamable $sgpr6, 2, implicit-def dead $scc ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 32772, implicit $exec ; GFX942-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr1, killed $sgpr0, 0, implicit $exec @@ -2018,6 +2424,8 @@ body: | ; GFX11-LABEL: name: v_add_co_u32_e64_sgpr_fi_clobbered_register ; GFX11: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11-NEXT: renamable $sgpr0 = S_LSHL_B32 renamable $sgpr6, 2, implicit-def dead $scc ; GFX11-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 32772, killed $sgpr0, 0, implicit $exec ; GFX11-NEXT: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed renamable $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, 0, 0, 0, 0, implicit $exec :: (load (s32), addrspace 5) @@ -2026,6 +2434,8 @@ body: | ; GFX12-LABEL: name: v_add_co_u32_e64_sgpr_fi_clobbered_register ; GFX12: liveins: $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7:0x000000000000003C ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX12-NEXT: renamable $sgpr0 = S_LSHL_B32 renamable $sgpr6, 2, implicit-def dead $scc ; GFX12-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 32768, killed $sgpr0, 0, implicit $exec ; GFX12-NEXT: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed renamable $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, 0, 0, 0, 0, implicit $exec :: (load (s32), addrspace 5) @@ -2054,11 +2464,19 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc ; GFX7: liveins: $sgpr4, $sgpr5 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX7-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX7-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX7-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX7-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX7-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX7-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX7-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX7-NEXT: $vcc_lo = S_MOV_B32 12288 @@ -2066,17 +2484,26 @@ body: | ; GFX7-NEXT: renamable $vgpr0, dead renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX7-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX7-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX7-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX7-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX7-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX8-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc ; GFX8: liveins: $sgpr4, $sgpr5 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX8-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX8-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX8-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX8-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX8-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX8-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX8-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX8-NEXT: $vcc_lo = S_MOV_B32 12288 @@ -2084,102 +2511,157 @@ body: | ; GFX8-NEXT: renamable $vgpr0, dead renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX8-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX8-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX8-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX8-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX900-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc ; GFX900: liveins: $sgpr4, $sgpr5 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX900-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX900-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX900-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX900-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX900-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX900-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX900-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX900-NEXT: $vgpr1 = V_ADD_U32_e32 12288, killed $vgpr1, implicit $exec ; GFX900-NEXT: renamable $vgpr0, dead renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX900-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX900-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX900-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX900-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX900-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX90A-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc ; GFX90A: liveins: $sgpr4, $sgpr5 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX90A-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX90A-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX90A-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX90A-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX90A-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX90A-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX90A-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_ADD_U32_e32 12288, killed $vgpr1, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, dead renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX90A-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX90A-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX90A-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX90A-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX90A-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX10-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc ; GFX10: liveins: $sgpr4, $sgpr5 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX10-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX10-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX10-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX10-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX10-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX10-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX10-NEXT: renamable $vgpr0, dead renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 12352, killed $vgpr1, 0, implicit $exec ; GFX10-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX10-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX10-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX10-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX10-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX942-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc ; GFX942: liveins: $sgpr4, $sgpr5 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX942-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX942-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX942-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX942-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX942-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX942-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; GFX942-NEXT: $sgpr6 = S_ADD_I32 $sgpr33, 12288, implicit-def $scc ; GFX942-NEXT: renamable $vgpr0, dead renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, killed $sgpr6, 0, implicit $exec ; GFX942-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX942-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX942-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX942-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX942-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX11-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc ; GFX11: liveins: $sgpr4, $sgpr5 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX11-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX11-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX11-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX11-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX11-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX11-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; GFX11-NEXT: renamable $vgpr0, dead renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 $sgpr33, 12352, 0, implicit $exec ; GFX11-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX11-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX11-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX11-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX11-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX12-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc ; GFX12: liveins: $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX12-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX12-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX12-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX12-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX12-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX12-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24576, implicit-def dead $scc ; GFX12-NEXT: renamable $vgpr0, dead renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 $sgpr33, 4160, 0, implicit $exec ; GFX12-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX12-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX12-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX12-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX12-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, renamable dead $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, %stack.1, 0, implicit $exec @@ -2204,11 +2686,19 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc_live ; GFX7: liveins: $sgpr4, $sgpr5 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX7-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX7-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX7-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX7-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX7-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX7-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX7-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX7-NEXT: $vcc_lo = S_MOV_B32 12288 @@ -2216,17 +2706,26 @@ body: | ; GFX7-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX7-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX7-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX7-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX7-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX7-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8_sgpr9 ; ; GFX8-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc_live ; GFX8: liveins: $sgpr4, $sgpr5 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX8-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX8-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX8-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX8-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX8-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX8-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX8-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX8-NEXT: $vcc_lo = S_MOV_B32 12288 @@ -2234,105 +2733,160 @@ body: | ; GFX8-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX8-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX8-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX8-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX8-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8_sgpr9 ; ; GFX900-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc_live ; GFX900: liveins: $sgpr4, $sgpr5 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX900-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX900-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX900-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX900-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX900-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX900-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX900-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX900-NEXT: $vgpr1 = V_ADD_U32_e32 12288, killed $vgpr1, implicit $exec ; GFX900-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX900-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX900-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX900-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX900-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX900-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8_sgpr9 ; ; GFX90A-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc_live ; GFX90A: liveins: $sgpr4, $sgpr5 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX90A-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX90A-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX90A-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX90A-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX90A-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX90A-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX90A-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_ADD_U32_e32 12288, killed $vgpr1, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX90A-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX90A-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX90A-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX90A-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX90A-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8_sgpr9 ; ; GFX10-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc_live ; GFX10: liveins: $sgpr4, $sgpr5 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX10-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX10-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX10-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX10-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX10-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX10-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 12352, killed $vgpr1, 0, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 killed $vgpr0, 0, 0, implicit $exec ; GFX10-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX10-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX10-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX10-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX10-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8_sgpr9 ; ; GFX942-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc_live ; GFX942: liveins: $sgpr4, $sgpr5 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX942-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX942-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX942-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX942-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX942-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX942-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; GFX942-NEXT: $sgpr6 = S_ADD_I32 $sgpr33, 12288, implicit-def $scc ; GFX942-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, killed $sgpr6, 0, implicit $exec ; GFX942-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX942-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX942-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX942-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX942-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8_sgpr9 ; ; GFX11-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc_live ; GFX11: liveins: $sgpr4, $sgpr5 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX11-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX11-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX11-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX11-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX11-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX11-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; GFX11-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 $sgpr33, 12352, 0, implicit $exec ; GFX11-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 killed $vgpr0, 0, 0, implicit $exec ; GFX11-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX11-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX11-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX11-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX11-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8_sgpr9 ; ; GFX12-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_non_vcc_live ; GFX12: liveins: $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; GFX12-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX12-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX12-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX12-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX12-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX12-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24576, implicit-def dead $scc ; GFX12-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 $sgpr33, 4160, 0, implicit $exec ; GFX12-NEXT: renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 killed $vgpr0, 0, 0, implicit $exec ; GFX12-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX12-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX12-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX12-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX12-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8_sgpr9 renamable $vgpr0, renamable $sgpr8_sgpr9 = V_ADD_CO_U32_e64 64, %stack.1, 0, implicit $exec @@ -2357,11 +2911,17 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc ; GFX7: liveins: $sgpr4, $sgpr5 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX7-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX7-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX7-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX7-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX7-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX7-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX7-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX7-NEXT: $vcc_lo = S_MOV_B32 12288 @@ -2369,17 +2929,24 @@ body: | ; GFX7-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX7-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX7-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX7-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX7-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX7-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX8-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc ; GFX8: liveins: $sgpr4, $sgpr5 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX8-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX8-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX8-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX8-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX8-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX8-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX8-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX8-NEXT: $vcc_lo = S_MOV_B32 12288 @@ -2387,102 +2954,145 @@ body: | ; GFX8-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX8-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX8-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX8-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX8-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX900-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc ; GFX900: liveins: $sgpr4, $sgpr5 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX900-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX900-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX900-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX900-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX900-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX900-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX900-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX900-NEXT: $vgpr1 = V_ADD_U32_e32 12288, killed $vgpr1, implicit $exec ; GFX900-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX900-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX900-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX900-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX900-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX900-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX90A-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc ; GFX90A: liveins: $sgpr4, $sgpr5 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX90A-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX90A-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX90A-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX90A-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX90A-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX90A-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX90A-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_ADD_U32_e32 12288, killed $vgpr1, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX90A-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX90A-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX90A-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX90A-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX90A-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX10-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc ; GFX10: liveins: $sgpr4, $sgpr5 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX10-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX10-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX10-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX10-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX10-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX10-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX10-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 12352, killed $vgpr1, 0, implicit $exec ; GFX10-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX10-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX10-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX10-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX10-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX942-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc ; GFX942: liveins: $sgpr4, $sgpr5 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX942-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX942-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX942-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX942-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX942-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX942-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; GFX942-NEXT: $sgpr6 = S_ADD_I32 $sgpr33, 12288, implicit-def $scc ; GFX942-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 64, killed $sgpr6, 0, implicit $exec ; GFX942-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX942-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX942-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX942-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX942-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX11-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc ; GFX11: liveins: $sgpr4, $sgpr5 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX11-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX11-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX11-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX11-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX11-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX11-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; GFX11-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $sgpr33, 12352, 0, implicit $exec ; GFX11-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX11-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX11-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX11-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX11-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX12-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc ; GFX12: liveins: $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX12-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX12-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX12-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX12-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX12-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX12-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24576, implicit-def dead $scc ; GFX12-NEXT: renamable $vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 $sgpr33, 4160, 0, implicit $exec ; GFX12-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX12-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX12-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX12-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX12-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0, renamable dead $vcc = V_ADD_CO_U32_e64 64, %stack.1, 0, implicit $exec @@ -2507,11 +3117,17 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc_live ; GFX7: liveins: $sgpr4, $sgpr5 ; GFX7-NEXT: {{ $}} + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX7-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX7-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX7-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX7-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX7-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX7-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX7-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX7-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX7-NEXT: $sgpr6 = S_MOV_B32 12288 @@ -2519,17 +3135,24 @@ body: | ; GFX7-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX7-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX7-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX7-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX7-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX7-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; GFX8-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc_live ; GFX8: liveins: $sgpr4, $sgpr5 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX8-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX8-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX8-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX8-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX8-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX8-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX8-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX8-NEXT: $sgpr6 = S_MOV_B32 12288 @@ -2537,105 +3160,148 @@ body: | ; GFX8-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX8-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX8-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX8-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX8-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; GFX900-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc_live ; GFX900: liveins: $sgpr4, $sgpr5 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX900-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX900-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX900-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX900-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX900-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX900-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX900-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX900-NEXT: $vgpr1 = V_ADD_U32_e32 12288, killed $vgpr1, implicit $exec ; GFX900-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX900-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX900-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX900-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX900-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX900-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; GFX90A-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc_live ; GFX90A: liveins: $sgpr4, $sgpr5 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX90A-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX90A-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX90A-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX90A-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX90A-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX90A-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX90A-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_ADD_U32_e32 12288, killed $vgpr1, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 64, killed $vgpr1, 0, implicit $exec ; GFX90A-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX90A-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX90A-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX90A-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX90A-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; GFX10-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc_live ; GFX10: liveins: $sgpr4, $sgpr5 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX10-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX10-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX10-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX10-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX10-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX10-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 12352, killed $vgpr1, 0, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr0, 0, 0, implicit $exec ; GFX10-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX10-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX10-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX10-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX10-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; GFX942-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc_live ; GFX942: liveins: $sgpr4, $sgpr5 ; GFX942-NEXT: {{ $}} + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX942-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX942-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX942-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX942-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX942-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX942-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; GFX942-NEXT: $sgpr6 = S_ADD_I32 $sgpr33, 12288, implicit-def $scc ; GFX942-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 64, killed $sgpr6, 0, implicit $exec ; GFX942-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX942-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX942-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX942-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX942-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; GFX11-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc_live ; GFX11: liveins: $sgpr4, $sgpr5 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX11-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX11-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX11-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX11-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX11-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX11-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; GFX11-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr33, 12352, 0, implicit $exec ; GFX11-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr0, 0, 0, implicit $exec ; GFX11-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX11-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX11-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX11-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX11-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc ; ; GFX12-LABEL: name: v_add_co_u32_e64_imm_fi_vop3_literal_error_vcc_live ; GFX12: liveins: $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX12-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; GFX12-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX12-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX12-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; GFX12-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX12-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX12-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24576, implicit-def dead $scc ; GFX12-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr33, 4160, 0, implicit $exec ; GFX12-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr0, 0, 0, implicit $exec ; GFX12-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; GFX12-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; GFX12-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX12-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; GFX12-NEXT: SI_RETURN implicit $vgpr0, implicit $vcc renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 64, %stack.1, 0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir index 6a4671058dc0e..3b1ad0cf28e58 100644 --- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir +++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir @@ -18,22 +18,34 @@ machineFunctionInfo: body: | bb.0: ; MUBUF-LABEL: name: v_add_u32_e32__inline_imm__fi_offset0 - ; MUBUF: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 12, killed $vgpr1, implicit $exec ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 ; ; MUBUFW32-LABEL: name: v_add_u32_e32__inline_imm__fi_offset0 - ; MUBUFW32: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 12, killed $vgpr1, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e32__inline_imm__fi_offset0 - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 12, killed $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__inline_imm__fi_offset0 - ; FLATSCRW32: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW32-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 12, killed $vgpr1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 12, %stack.0, implicit $exec @@ -54,22 +66,34 @@ machineFunctionInfo: body: | bb.0: ; MUBUF-LABEL: name: v_add_u32_e32__inline_imm___fi_offset_inline_imm - ; MUBUF: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 28, killed $vgpr1, implicit $exec ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 ; ; MUBUFW32-LABEL: name: v_add_u32_e32__inline_imm___fi_offset_inline_imm - ; MUBUFW32: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 28, killed $vgpr1, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e32__inline_imm___fi_offset_inline_imm - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 28, killed $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__inline_imm___fi_offset_inline_imm - ; FLATSCRW32: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW32-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 28, killed $vgpr1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 12, %stack.1, implicit $exec @@ -89,22 +113,34 @@ machineFunctionInfo: body: | bb.0: ; MUBUF-LABEL: name: v_add_u32_e32__literal__fi_offset0 - ; MUBUF: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 68, killed $vgpr1, implicit $exec ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 ; ; MUBUFW32-LABEL: name: v_add_u32_e32__literal__fi_offset0 - ; MUBUFW32: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 68, killed $vgpr1, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e32__literal__fi_offset0 - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 68, killed $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__literal__fi_offset0 - ; FLATSCRW32: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW32-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 68, killed $vgpr1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 68, %stack.0, implicit $exec @@ -125,22 +161,34 @@ machineFunctionInfo: body: | bb.0: ; MUBUF-LABEL: name: v_add_u32_e32__literal__fi_offset0__offset_inlineimm - ; MUBUF: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 100, killed $vgpr1, implicit $exec ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 ; ; MUBUFW32-LABEL: name: v_add_u32_e32__literal__fi_offset0__offset_inlineimm - ; MUBUFW32: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 100, killed $vgpr1, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e32__literal__fi_offset0__offset_inlineimm - ; FLATSCRW64: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 100, killed $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__literal__fi_offset0__offset_inlineimm - ; FLATSCRW32: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW32-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 100, killed $vgpr1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 68, %stack.1, implicit $exec @@ -163,6 +211,9 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__vgpr__fi_offset0 ; MUBUF: liveins: $vgpr1 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $vgpr1, killed $vgpr2, implicit $exec ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 @@ -170,6 +221,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__vgpr__fi_offset0 ; MUBUFW32: liveins: $vgpr1 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $vgpr1, killed $vgpr2, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 @@ -177,12 +231,18 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__vgpr__fi_offset0 ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr32, $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__vgpr__fi_offset0 ; FLATSCRW32: liveins: $vgpr1 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr32, $vgpr1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 $vgpr1, %stack.0, implicit $exec @@ -205,6 +265,9 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__fi_offset0__vgpr ; MUBUF: liveins: $vgpr1 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $vgpr1, killed $vgpr2, implicit $exec ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 @@ -212,6 +275,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__fi_offset0__vgpr ; MUBUFW32: liveins: $vgpr1 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $vgpr1, killed $vgpr2, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 @@ -219,12 +285,18 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__fi_offset0__vgpr ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr32, $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__fi_offset0__vgpr ; FLATSCRW32: liveins: $vgpr1 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr32, $vgpr1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 %stack.0, $vgpr1, implicit $exec @@ -248,6 +320,9 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__vgpr__fi_literal_offset ; MUBUF: liveins: $vgpr1 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $vgpr1, killed $vgpr2, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec @@ -256,6 +331,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__vgpr__fi_literal_offset ; MUBUFW32: liveins: $vgpr1 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $vgpr1, killed $vgpr2, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec @@ -264,6 +342,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__vgpr__fi_literal_offset ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr32, $vgpr1, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 @@ -271,6 +352,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_u32_e32__vgpr__fi_literal_offset ; FLATSCRW32: liveins: $vgpr1 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr32, $vgpr1, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 @@ -295,6 +379,9 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__fi_literal_offset__vgpr ; MUBUF: liveins: $vgpr1 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $vgpr1, killed $vgpr2, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec @@ -303,6 +390,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__fi_literal_offset__vgpr ; MUBUFW32: liveins: $vgpr1 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr2 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $vgpr1, killed $vgpr2, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec @@ -311,6 +401,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__fi_literal_offset__vgpr ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr32, $vgpr1, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 @@ -318,6 +411,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_u32_e32__fi_literal_offset__vgpr ; FLATSCRW32: liveins: $vgpr1 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr32, $vgpr1, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 @@ -342,6 +438,9 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__sgpr__fi_literal_offset ; MUBUF: liveins: $sgpr8 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr8, killed $vgpr1, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec @@ -350,6 +449,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__sgpr__fi_literal_offset ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr8, killed $vgpr1, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec @@ -358,6 +460,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__sgpr__fi_literal_offset ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr8, killed $vgpr1, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec @@ -366,6 +471,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_u32_e32__sgpr__fi_literal_offset ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr8, killed $vgpr1, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec @@ -387,21 +495,33 @@ machineFunctionInfo: body: | bb.0: ; MUBUF-LABEL: name: v_add_u32_e64__inline_imm__fi_offset0 - ; MUBUF: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e64 12, killed $vgpr1, 0, implicit $exec ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 ; ; MUBUFW32-LABEL: name: v_add_u32_e64__inline_imm__fi_offset0 - ; MUBUFW32: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec + ; MUBUFW32: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 12, killed $vgpr1, 0, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e64__inline_imm__fi_offset0 - ; FLATSCRW64: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, 12, 0, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, 12, 0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e64__inline_imm__fi_offset0 - ; FLATSCRW32: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, 12, 0, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, 12, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e64 12, %stack.0, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -424,6 +544,9 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__fi_literal_offset__sgpr ; MUBUF: liveins: $sgpr8 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -433,6 +556,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__fi_literal_offset__sgpr ; MUBUFW32: liveins: $sgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 128, killed $vgpr0, 0, implicit $exec @@ -441,6 +567,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e64__fi_literal_offset__sgpr ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -450,6 +579,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_u32_e64__fi_literal_offset__sgpr ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, $sgpr8, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 128, killed $vgpr0, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 @@ -474,6 +606,9 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__vgpr__fi_literal_offset ; MUBUF: liveins: $vgpr8 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -483,6 +618,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__vgpr__fi_literal_offset ; MUBUFW32: liveins: $vgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $vgpr0, 128, 0, implicit $exec @@ -491,6 +629,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e64__vgpr__fi_literal_offset ; FLATSCRW64: liveins: $vgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $vgpr1, killed $vgpr0, 0, implicit $exec @@ -499,6 +640,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_u32_e64__vgpr__fi_literal_offset ; FLATSCRW32: liveins: $vgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $vgpr0, 128, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 @@ -523,6 +667,9 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__vgpr__fi_literal_offset__clamp ; MUBUF: liveins: $vgpr8 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -532,6 +679,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__vgpr__fi_literal_offset__clamp ; MUBUFW32: liveins: $vgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $vgpr0, 128, 1, implicit $exec @@ -540,6 +690,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e64__vgpr__fi_literal_offset__clamp ; FLATSCRW64: liveins: $vgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $vgpr1, killed $vgpr0, 1, implicit $exec @@ -548,6 +701,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_u32_e64__vgpr__fi_literal_offset__clamp ; FLATSCRW32: liveins: $vgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $vgpr0, 128, 1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 @@ -572,6 +728,9 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__fi_literal_offset__vgpr__clamp ; MUBUF: liveins: $vgpr8 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -581,6 +740,9 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__fi_literal_offset__vgpr__clamp ; MUBUFW32: liveins: $vgpr8 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr8, killed $vgpr1, 0, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 128, killed $vgpr0, 1, implicit $exec @@ -589,6 +751,9 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e64__fi_literal_offset__vgpr__clamp ; FLATSCRW64: liveins: $vgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $vgpr1, killed $vgpr0, 1, implicit $exec @@ -597,6 +762,9 @@ body: | ; FLATSCRW32-LABEL: name: v_add_u32_e64__fi_literal_offset__vgpr__clamp ; FLATSCRW32: liveins: $vgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr32, $vgpr8, 0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 128, killed $vgpr0, 1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 @@ -622,6 +790,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__fi_literal_offset__vgpr__clamp__kernel ; MUBUF: liveins: $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec @@ -631,6 +801,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__fi_literal_offset__vgpr__clamp__kernel ; MUBUFW32: liveins: $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 128, $vgpr8, 1, implicit $exec @@ -639,6 +811,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e64__fi_literal_offset__vgpr__clamp__kernel ; FLATSCRW64: liveins: $vgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $vgpr1, $vgpr8, 1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 @@ -646,6 +820,8 @@ body: | ; FLATSCRW32-LABEL: name: v_add_u32_e64__fi_literal_offset__vgpr__clamp__kernel ; FLATSCRW32: liveins: $vgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 128, $vgpr8, 1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e64 %stack.1, $vgpr8, 1, implicit $exec @@ -668,6 +844,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__inline_imm__fi_offset0__kernel ; MUBUF: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec @@ -676,17 +854,23 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__inline_imm__fi_offset0__kernel ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e32__inline_imm__fi_offset0__kernel - ; FLATSCRW64: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__inline_imm__fi_offset0__kernel - ; FLATSCRW32: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 12, %stack.0, implicit $exec SI_RETURN implicit $vgpr0 @@ -708,6 +892,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__inline_imm__fi_offset0__kernel ; MUBUF: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec @@ -716,17 +902,23 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__inline_imm__fi_offset0__kernel ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e64__inline_imm__fi_offset0__kernel - ; FLATSCRW64: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e64__inline_imm__fi_offset0__kernel - ; FLATSCRW32: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 12, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e64 12, %stack.0, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -751,6 +943,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__inline_imm__fi_literal__kernel ; MUBUF: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec @@ -759,17 +953,23 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__inline_imm__fi_literal__kernel ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e32__inline_imm__fi_literal__kernel - ; FLATSCRW64: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__inline_imm__fi_literal__kernel - ; FLATSCRW32: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 12, %stack.1, implicit $exec SI_RETURN implicit $vgpr0 @@ -792,6 +992,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__inline_imm__fi_literal__kernel ; MUBUF: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec @@ -800,17 +1002,23 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__inline_imm__fi_literal__kernel ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e64__inline_imm__fi_literal__kernel - ; FLATSCRW64: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e64__inline_imm__fi_literal__kernel - ; FLATSCRW32: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e64 12, %stack.1, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -833,6 +1041,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__fi_literal__inline_imm__kernel ; MUBUF: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec @@ -841,17 +1051,23 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__fi_literal__inline_imm__kernel ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e64__fi_literal__inline_imm__kernel - ; FLATSCRW64: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e64__fi_literal__inline_imm__kernel - ; FLATSCRW32: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 44, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e64 %stack.1, 12, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -874,6 +1090,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__inline_imm__fi_literal__kernel__clamp ; MUBUF: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e64 44, 0, 1, implicit $exec @@ -882,17 +1100,23 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__inline_imm__fi_literal__kernel__clamp ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 44, 0, 1, implicit $exec ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e64__inline_imm__fi_literal__kernel__clamp - ; FLATSCRW64: renamable $vgpr0 = V_ADD_U32_e64 44, 0, 1, implicit $exec + ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 44, 0, 1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e64__inline_imm__fi_literal__kernel__clamp - ; FLATSCRW32: renamable $vgpr0 = V_ADD_U32_e64 44, 0, 1, implicit $exec + ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 44, 0, 1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e64 12, %stack.1, 1, implicit $exec SI_RETURN implicit $vgpr0 @@ -917,6 +1141,8 @@ body: | ; MUBUF-LABEL: name: killed_reg_regression ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec @@ -930,6 +1156,8 @@ body: | ; MUBUFW32-LABEL: name: killed_reg_regression ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec @@ -943,6 +1171,8 @@ body: | ; FLATSCRW64-LABEL: name: killed_reg_regression ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr2 = V_MOV_B32_e32 15, implicit $exec @@ -954,6 +1184,8 @@ body: | ; FLATSCRW32-LABEL: name: killed_reg_regression ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr2 = V_MOV_B32_e32 15, implicit $exec @@ -987,6 +1219,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__kernel_fi_offset0__other_vgpr_live_after ; MUBUF: liveins: $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec @@ -995,6 +1229,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__kernel_fi_offset0__other_vgpr_live_after ; MUBUFW32: liveins: $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec @@ -1003,12 +1239,16 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__kernel_fi_offset0__other_vgpr_live_after ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__kernel_fi_offset0__other_vgpr_live_after ; FLATSCRW32: liveins: $vgpr1 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 renamable $vgpr0 = V_ADD_U32_e32 renamable $vgpr1, %stack.0, implicit $exec @@ -1032,6 +1272,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__kernel_other_vgpr_live_after__fi_offset0 ; MUBUF: liveins: $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec @@ -1040,6 +1282,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__kernel_other_vgpr_live_after__fi_offset0 ; MUBUFW32: liveins: $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec @@ -1048,12 +1292,16 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__kernel_other_vgpr_live_after__fi_offset0 ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__kernel_other_vgpr_live_after__fi_offset0 ; FLATSCRW32: liveins: $vgpr1 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 renamable $vgpr0 = V_ADD_U32_e32 %stack.0, renamable $vgpr1, implicit $exec @@ -1077,6 +1325,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__kernel_fi_offset0__sgpr_live_after ; MUBUF: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $sgpr8, implicit $exec @@ -1085,6 +1335,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__kernel_fi_offset0__sgpr_live_after ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $sgpr8, implicit $exec @@ -1093,12 +1345,16 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__kernel_fi_offset0__sgpr_live_after ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $sgpr8, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__kernel_fi_offset0__sgpr_live_after ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $sgpr8, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8 renamable $vgpr0 = V_ADD_U32_e32 renamable $sgpr8, %stack.0, implicit $exec @@ -1122,6 +1378,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__kernel_fi_offset0__other_vgpr_live_after ; MUBUF: liveins: $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec @@ -1130,6 +1388,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__kernel_fi_offset0__other_vgpr_live_after ; MUBUFW32: liveins: $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec @@ -1138,12 +1398,16 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e64__kernel_fi_offset0__other_vgpr_live_after ; FLATSCRW64: liveins: $vgpr1 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 ; ; FLATSCRW32-LABEL: name: v_add_u32_e64__kernel_fi_offset0__other_vgpr_live_after ; FLATSCRW32: liveins: $vgpr1 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 renamable $vgpr0 = V_ADD_U32_e64 renamable $vgpr1, %stack.0, 0, implicit $exec @@ -1168,6 +1432,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__kernel_fi_offset72__sgpr_live_after ; MUBUF: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 72, implicit $exec @@ -1177,6 +1443,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__kernel_fi_offset72__sgpr_live_after ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $vgpr1 = V_MOV_B32_e32 72, implicit $exec @@ -1186,6 +1454,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__kernel_fi_offset72__sgpr_live_after ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 72, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr8, killed $vgpr1, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8 @@ -1193,6 +1463,8 @@ body: | ; FLATSCRW32-LABEL: name: v_add_u32_e32__kernel_fi_offset72__sgpr_live_after ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: $vgpr1 = V_MOV_B32_e32 72, implicit $exec ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 $sgpr8, killed $vgpr1, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8 @@ -1218,6 +1490,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__kernel_fi_offset72__sgpr_live_after ; MUBUF: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 72, implicit $exec @@ -1227,6 +1501,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__kernel_fi_offset72__sgpr_live_after ; MUBUFW32: liveins: $sgpr8, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr8, 72, 0, implicit $exec @@ -1235,6 +1511,8 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e64__kernel_fi_offset72__sgpr_live_after ; FLATSCRW64: liveins: $sgpr8 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 72, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 killed $vgpr1, $sgpr8, 0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8 @@ -1242,6 +1520,8 @@ body: | ; FLATSCRW32-LABEL: name: v_add_u32_e64__kernel_fi_offset72__sgpr_live_after ; FLATSCRW32: liveins: $sgpr8 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $sgpr8, 72, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr8 renamable $vgpr0 = V_ADD_U32_e64 renamable $sgpr8, %stack.1, 0, implicit $exec @@ -1266,6 +1546,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset0__kernel ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 @@ -1273,6 +1555,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset0__kernel ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 @@ -1280,11 +1564,15 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset0__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset0__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 $vgpr0, %stack.0, implicit $exec SI_RETURN implicit $vgpr0 @@ -1307,6 +1595,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__fi_offset0__identity_vgpr__kernel ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 @@ -1314,6 +1604,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__fi_offset0__identity_vgpr__kernel ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 @@ -1321,11 +1613,15 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__fi_offset0__identity_vgpr__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__fi_offset0__identity_vgpr__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 %stack.0, $vgpr0, implicit $exec SI_RETURN implicit $vgpr0 @@ -1349,6 +1645,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__identity_vgpr__fi_offset0__kernel ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 @@ -1356,6 +1654,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__identity_vgpr__fi_offset0__kernel ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 @@ -1363,11 +1663,15 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e64__identity_vgpr__fi_offset0__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e64__identity_vgpr__fi_offset0__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, %stack.0, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -1391,6 +1695,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__fi_offset0__identity_vgpr__kernel ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 @@ -1398,6 +1704,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__fi_offset0__identity_vgpr__kernel ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 @@ -1405,11 +1713,15 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e64__fi_offset0__identity_vgpr__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e64__fi_offset0__identity_vgpr__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e64 %stack.0, $vgpr0, 0, implicit $exec SI_RETURN implicit $vgpr0 @@ -1432,6 +1744,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__fi_offset0__identity_vgpr__kernel_kill ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 @@ -1439,6 +1753,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__fi_offset0__identity_vgpr__kernel_kill ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 @@ -1446,11 +1762,15 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__fi_offset0__identity_vgpr__kernel_kill ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__fi_offset0__identity_vgpr__kernel_kill ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 %stack.0, killed $vgpr0, implicit $exec SI_RETURN implicit $vgpr0 @@ -1475,6 +1795,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset32__kernel ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 32, $vgpr0, implicit $exec @@ -1483,6 +1805,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset32__kernel ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 32, $vgpr0, implicit $exec @@ -1491,12 +1815,16 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset32__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 32, $vgpr0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset32__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 32, $vgpr0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 $vgpr0, %stack.1, implicit $exec @@ -1523,6 +1851,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset72__kernel ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 72, $vgpr0, implicit $exec @@ -1531,6 +1861,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset72__kernel ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 72, $vgpr0, implicit $exec @@ -1539,12 +1871,16 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset72__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 72, $vgpr0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__identity_vgpr__fi_offset72__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 72, $vgpr0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 $vgpr0, %stack.1, implicit $exec @@ -1570,6 +1906,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__fi_offset72__identity_vgpr__kernel ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 72, $vgpr0, implicit $exec @@ -1578,6 +1916,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__fi_offset72__identity_vgpr__kernel ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 72, $vgpr0, implicit $exec @@ -1586,12 +1926,16 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__fi_offset72__identity_vgpr__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 72, $vgpr0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__fi_offset72__identity_vgpr__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 72, $vgpr0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 %stack.1, $vgpr0, implicit $exec @@ -1617,6 +1961,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e32__fi_offset32__identity_vgpr__kernel ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e32 32, $vgpr0, implicit $exec @@ -1625,6 +1971,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e32__fi_offset32__identity_vgpr__kernel ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 32, $vgpr0, implicit $exec @@ -1633,12 +1981,16 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e32__fi_offset32__identity_vgpr__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e32 32, $vgpr0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e32__fi_offset32__identity_vgpr__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e32 32, $vgpr0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e32 %stack.1, $vgpr0, implicit $exec @@ -1664,6 +2016,8 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64__identity_vgpr__fi_offset32__kernel ; MUBUF: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUF-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, 32, 0, implicit $exec @@ -1672,6 +2026,8 @@ body: | ; MUBUFW32-LABEL: name: v_add_u32_e64__identity_vgpr__fi_offset32__kernel ; MUBUFW32: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; MUBUFW32-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, 32, 0, implicit $exec @@ -1680,12 +2036,16 @@ body: | ; FLATSCRW64-LABEL: name: v_add_u32_e64__identity_vgpr__fi_offset32__kernel ; FLATSCRW64: liveins: $vgpr0 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, 32, 0, implicit $exec ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW32-LABEL: name: v_add_u32_e64__identity_vgpr__fi_offset32__kernel ; FLATSCRW32: liveins: $vgpr0 ; FLATSCRW32-NEXT: {{ $}} + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; FLATSCRW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, 32, 0, implicit $exec ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, %stack.1, 0, implicit $exec @@ -1710,49 +2070,70 @@ body: | ; MUBUF-LABEL: name: v_add_u32_e64_imm_fi_vop3_literal_error ; MUBUF: liveins: $sgpr4, $sgpr5 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; MUBUF-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; MUBUF-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; MUBUF-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; MUBUF-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; MUBUF-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; MUBUF-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; MUBUF-NEXT: $vgpr1 = V_ADD_U32_e32 12288, killed $vgpr1, implicit $exec ; MUBUF-NEXT: renamable $vgpr0 = V_ADD_U32_e64 64, killed $vgpr1, 0, implicit $exec ; MUBUF-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; MUBUF-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; MUBUF-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; MUBUF-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; MUBUF-NEXT: SI_RETURN implicit $vgpr0 ; ; MUBUFW32-LABEL: name: v_add_u32_e64_imm_fi_vop3_literal_error ; MUBUFW32: liveins: $sgpr4, $sgpr5 ; MUBUFW32-NEXT: {{ $}} + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUFW32-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; MUBUFW32-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 262112, implicit-def $scc ; MUBUFW32-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294705152, implicit-def dead $scc ; MUBUFW32-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; MUBUFW32-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; MUBUFW32-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 1048576, implicit-def dead $scc ; MUBUFW32-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 5, $sgpr33, implicit $exec ; MUBUFW32-NEXT: renamable $vgpr0 = V_ADD_U32_e64 12352, killed $vgpr1, 0, implicit $exec ; MUBUFW32-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; MUBUFW32-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; MUBUFW32-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; MUBUFW32-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_u32_e64_imm_fi_vop3_literal_error ; FLATSCRW64: liveins: $sgpr4, $sgpr5 ; FLATSCRW64-NEXT: {{ $}} + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; FLATSCRW64-NEXT: $sgpr4 = frame-setup COPY $sgpr33 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr4 ; FLATSCRW64-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; FLATSCRW64-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; FLATSCRW64-NEXT: $sgpr5 = frame-setup COPY $sgpr34 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr5 ; FLATSCRW64-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; FLATSCRW64-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; FLATSCRW64-NEXT: $sgpr6 = S_ADD_I32 $sgpr33, 12288, implicit-def $scc ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_U32_e64 64, killed $sgpr6, 0, implicit $exec ; FLATSCRW64-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; FLATSCRW64-NEXT: $sgpr34 = frame-destroy COPY $sgpr5 + ; FLATSCRW64-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; FLATSCRW64-NEXT: $sgpr33 = frame-destroy COPY $sgpr4 ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_U32_e64 64, %stack.1, 0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir b/llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir new file mode 100644 index 0000000000000..984bcb209a87e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir @@ -0,0 +1,31 @@ +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=prologepilog -o - %s | FileCheck %s + +--- | + + define protected amdgpu_kernel void @kern1() { + entry: + ret void + } +... +--- +name: kern1 +alignment: 1 +tracksRegLiveness: true +frameInfo: + maxAlignment: 1 +machineFunctionInfo: + maxKernArgAlign: 1 + isEntryFunction: true + scratchRSrcReg: '$sgpr100_sgpr101_sgpr102_sgpr103' + stackPtrOffsetReg: '$sgpr32' + argumentInfo: + workGroupIDX: { reg: '$sgpr0' } + privateSegmentWaveByteOffset: { reg: '$sgpr1' } + workItemIDX: { reg: '$vgpr0' } +body: | + bb.0: + ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK: frame-setup CFI_INSTRUCTION undefined $pc_reg + S_ENDPGM 0 + +... diff --git a/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll b/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll index 76a2114a000cf..f5832e6f307fd 100644 --- a/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll +++ b/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll @@ -22,13 +22,14 @@ define void @test_stack_realign(<8 x i32> %val, i32 %idx) #0 { ; GCN-NEXT: v_writelane_b32 v42, s34, 3 ; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_addk_i32 s32, 0x3000 +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GCN-NEXT: v_writelane_b32 v42, s30, 0 +; GCN-NEXT: v_writelane_b32 v42, s31, 1 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, extern_func@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, extern_func@gotpcrel32@hi+12 ; GCN-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: v_writelane_b32 v42, s30, 0 ; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:92 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:88 @@ -46,7 +47,6 @@ define void @test_stack_realign(<8 x i32> %val, i32 %idx) #0 { ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:64 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_mov_b32_e32 v0, v8 -; GCN-NEXT: v_writelane_b32 v42, s31, 1 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMSTART @@ -55,8 +55,8 @@ define void @test_stack_realign(<8 x i32> %val, i32 %idx) #0 { ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GCN-NEXT: v_readlane_b32 s31, v42, 1 ; GCN-NEXT: v_readlane_b32 s30, v42, 0 +; GCN-NEXT: v_readlane_b32 s31, v42, 1 ; GCN-NEXT: s_mov_b32 s32, s34 ; GCN-NEXT: v_readlane_b32 s4, v42, 2 ; GCN-NEXT: v_readlane_b32 s34, v42, 3 diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll index 37cbd2d926413..141a5afc872f2 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll @@ -109,6 +109,7 @@ define amdgpu_kernel void @kernel_calls_no_stack() { ret void } +; One VGPR was left free (VGPR0) for whole-wave register allocation. define amdgpu_kernel void @test(ptr addrspace(1) %out, i32 %in) { ; GCN-LABEL: test: ; GCN: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir b/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir index 6e52cb0265bed..2492eb2982aac 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir @@ -13,7 +13,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 - ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAC_F32 1056964608, [[COPY]], [[COPY1]], implicit $mode + ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAMK_F32 [[COPY]], 1056964608, [[COPY1]], implicit $mode ; CHECK-NEXT: $sgpr0 = COPY %fma %0:sreg_32 = COPY $sgpr0 %1:sreg_32 = COPY $sgpr1 @@ -33,7 +33,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 - ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAC_F32 [[COPY]], 1056964608, [[COPY1]], implicit $mode + ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAMK_F32 [[COPY]], 1056964608, [[COPY1]], implicit $mode ; CHECK-NEXT: $sgpr0 = COPY %fma %0:sreg_32 = COPY $sgpr0 %1:sreg_32 = COPY $sgpr1 @@ -73,7 +73,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 - ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAC_F32 1234567890, [[COPY]], [[COPY1]], implicit $mode + ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAMK_F32 [[COPY]], 1234567890, [[COPY1]], implicit $mode ; CHECK-NEXT: $sgpr0 = COPY %fma %0:sreg_32 = COPY $sgpr0 %1:sreg_32 = COPY $sgpr1 @@ -93,7 +93,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 - ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAC_F32 [[COPY]], 1234567890, [[COPY1]], implicit $mode + ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAMK_F32 [[COPY]], 1234567890, [[COPY1]], implicit $mode ; CHECK-NEXT: $sgpr0 = COPY %fma %0:sreg_32 = COPY $sgpr0 %1:sreg_32 = COPY $sgpr1 @@ -212,7 +212,8 @@ body: | ; CHECK: liveins: $sgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAAK_F32 [[COPY]], 1056964608, 1234567890, implicit $mode + ; CHECK-NEXT: %noninlinable:sreg_32 = S_MOV_B32 1234567890 + ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAMK_F32 [[COPY]], 1056964608, %noninlinable, implicit $mode ; CHECK-NEXT: $sgpr0 = COPY %fma %0:sreg_32 = COPY $sgpr0 %inlinable:sreg_32 = S_MOV_B32 1056964608 @@ -231,7 +232,7 @@ body: | ; CHECK: liveins: $sgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 - ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAC_F32 1234567890, 1234567890, [[COPY]], implicit $mode + ; CHECK-NEXT: %fma:sreg_32 = nofpexcept S_FMAMK_F32 1234567890, 1234567890, [[COPY]], implicit $mode ; CHECK-NEXT: $sgpr0 = COPY %fma %0:sreg_32 = COPY $sgpr0 %noninlinable:sreg_32 = S_MOV_B32 1234567890 diff --git a/llvm/test/CodeGen/AMDGPU/fold-redundant-sgpr-vgpr-rw-across-bb.ll b/llvm/test/CodeGen/AMDGPU/fold-redundant-sgpr-vgpr-rw-across-bb.ll new file mode 100644 index 0000000000000..2ad9c0e71c5f3 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fold-redundant-sgpr-vgpr-rw-across-bb.ll @@ -0,0 +1,79 @@ +; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefix=CHECK1 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -amdgpu-si-fold-operands-preheader-threshold=10 < %s | FileCheck --check-prefix=CHECK2 %s + +define protected amdgpu_kernel void @main(ptr addrspace(1) noundef %args.coerce, ptr addrspace(1) noundef %args.coerce2, ptr addrspace(1) noundef %args.coerce4, i32 noundef %args12) { +; CHECK1-LABEL: main: +; check that non-redundant readfirstlanes are not removed +; CHECK1: v_readfirstlane_b32 +; check that all redundant readfirstlanes are removed +; CHECK1-NOT: v_readfirstlane_b32 +; CHECK1: s_endpgm + +; CHECK2-LABEL: main: +; CHECK2: v_readfirstlane_b32 +; check that all redundant readfirstlanes across basic blocks persist +; CHECK2: v_readfirstlane_b32 +; CHECK2: v_readfirstlane_b32 +; CHECK2: s_endpgm +entry: + %wid = tail call noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.x() + %div1 = lshr i32 %wid, 6 + %rfl1 = tail call noundef i32 @llvm.amdgcn.readfirstlane.i32(i32 %div1) + %sub1 = add nsw i32 %args12, 1023 + %div2 = sdiv i32 %sub1, 1024 + %rfl2 = tail call i32 @llvm.amdgcn.readfirstlane.i32(i32 %div2) + %cmp24.i = icmp sgt i32 %rfl2, 0 + br i1 %cmp24.i, label %for.body.lr.ph.i, label %add.exit + +for.body.lr.ph.i: ; preds = %entry + %pti1 = ptrtoint ptr addrspace(1) %args.coerce4 to i64 + %pti2 = ptrtoint ptr addrspace(1) %args.coerce2 to i64 + %pti3 = ptrtoint ptr addrspace(1) %args.coerce to i64 + %lshr1 = lshr i32 %rfl1, 2 + %mbl = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %mbh = tail call noundef i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbl) + %lshr2 = lshr i32 %mbh, 6 + %add8 = add i32 %lshr1, %lshr2 + %sub3 = shl i32 %rfl1, 8 + %mul2 = and i32 %sub3, 768 + %add1 = or disjoint i32 %mbh, %mul2 + %add3 = add nsw i32 %add1, %add8 + %sext1 = add i64 4294967296, 4611686014132420608 + %conv1 = lshr exact i64 64, 32 + %add4 = add nuw nsw i64 %conv1, 1 + %zext2 = zext i32 1 to i64 + %tmp.sroa = add nuw nsw i64 %zext2, 4294967295 + %sub5 = add i64 %tmp.sroa, 4294967296 + %sext2 = mul i64 %sub5, 4294967296 + %conv2 = lshr exact i64 %sext2, 32 + %add5 = add nuw nsw i64 %add4, %conv2 + %conv3 = trunc i64 %add5 to i32 + %mul4 = shl i32 %conv3, 2 + %bc1 = bitcast i64 %pti3 to <2 x i32> + %ee1 = extractelement <2 x i32> %bc1, i64 0 + %ee2 = extractelement <2 x i32> %bc1, i64 1 + br label %for.body.i + +for.body.i: ; preds = %for.body.i, %for.body.lr.ph.i + %loopi = phi i32 [ 0, %for.body.lr.ph.i ], [ %inc.i, %for.body.i ] + %tmp1 = phi i32 [ %add3, %for.body.lr.ph.i ], [ %cnt, %for.body.i ] + %rfl3 = tail call i32 @llvm.amdgcn.readfirstlane.i32(i32 %ee1) + %rfl4 = tail call i32 @llvm.amdgcn.readfirstlane.i32(i32 %ee2) + %rfl5 = tail call i32 @llvm.amdgcn.readfirstlane.i32(i32 %mul4) + %ie1 = insertelement <4 x i32> , i32 %rfl3, i64 0 + %ie2 = insertelement <4 x i32> %ie1, i32 %rfl4, i64 1 + %ie3 = insertelement <4 x i32> %ie2, i32 %rfl5, i64 2 + %mul5 = shl i32 %tmp1, 2 + %buffload1 = tail call contract noundef <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> noundef %ie2, i32 noundef %mul5, i32 noundef 0, i32 noundef 0) #6 + %add6 = add nsw i32 %tmp1, 1 + %buffload3 = tail call contract noundef <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> noundef %ie3, i32 noundef %mul5, i32 noundef 0, i32 noundef 0) #6 + %vec_add1 = fadd contract <4 x float> %buffload1, %buffload3 + tail call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> noundef %vec_add1, <4 x i32> noundef %ie3, i32 noundef %mul5, i32 noundef 0, i32 noundef 0) #6 + %cnt = add nsw i32 %tmp1, 1024 + %inc.i = add nuw nsw i32 %loopi, 1 + %exitcond.not.i = icmp eq i32 %inc.i, %rfl2 + br i1 %exitcond.not.i, label %add.exit, label %for.body.i + + add.exit: ; preds = %for.body.i, %entry + ret void +} \ No newline at end of file diff --git a/llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir b/llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir index 5f36d5403ebcf..af453d2903d66 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir @@ -12,7 +12,9 @@ machineFunctionInfo: body: | bb.0: ; CHECK-LABEL: name: merge_sgpr_spill_into_copy_from_exec_lo - ; CHECK: S_NOP 0, implicit-def $exec_lo + ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; CHECK-NEXT: S_NOP 0, implicit-def $exec_lo ; CHECK-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, $vgpr0 @@ -37,7 +39,9 @@ machineFunctionInfo: body: | bb.0: ; CHECK-LABEL: name: merge_sgpr_spill_into_copy_from_exec_hi - ; CHECK: S_NOP 0, implicit-def $exec_hi + ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; CHECK-NEXT: S_NOP 0, implicit-def $exec_hi ; CHECK-NEXT: $sgpr0 = S_MOV_B32 $exec_hi ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, $vgpr0 @@ -62,7 +66,9 @@ machineFunctionInfo: body: | bb.0: ; CHECK-LABEL: name: merge_sgpr_spill_into_copy_from_exec - ; CHECK: S_NOP 0, implicit-def $exec + ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; CHECK-NEXT: S_NOP 0, implicit-def $exec ; CHECK-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, $vgpr0, implicit-def $sgpr0_sgpr1, implicit $sgpr0_sgpr1 @@ -93,7 +99,9 @@ machineFunctionInfo: body: | bb.0: ; CHECK-LABEL: name: reload_sgpr_spill_into_copy_to_exec_lo - ; CHECK: S_NOP 0, implicit-def renamable $sgpr0, implicit-def dead renamable $sgpr1, implicit-def $exec_lo + ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; CHECK-NEXT: S_NOP 0, implicit-def renamable $sgpr0, implicit-def dead renamable $sgpr1, implicit-def $exec_lo ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, $vgpr0 ; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr0, 0 @@ -116,7 +124,9 @@ machineFunctionInfo: body: | bb.0: ; CHECK-LABEL: name: reload_sgpr_spill_into_copy_to_exec_hi - ; CHECK: S_NOP 0, implicit-def renamable $sgpr0, implicit-def dead renamable $sgpr1, implicit-def $exec_hi + ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; CHECK-NEXT: S_NOP 0, implicit-def renamable $sgpr0, implicit-def dead renamable $sgpr1, implicit-def $exec_hi ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, $vgpr0 ; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr0, 0 @@ -139,7 +149,9 @@ machineFunctionInfo: body: | bb.0: ; CHECK-LABEL: name: reload_sgpr_spill_into_copy_to_exec - ; CHECK: S_NOP 0, implicit-def renamable $sgpr0_sgpr1, implicit-def dead renamable $sgpr2_sgpr3, implicit-def $exec + ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; CHECK-NEXT: S_NOP 0, implicit-def renamable $sgpr0_sgpr1, implicit-def dead renamable $sgpr2_sgpr3, implicit-def $exec ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, $vgpr0, implicit-def $sgpr0_sgpr1, implicit $sgpr0_sgpr1 ; CHECK-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr1, 1, $vgpr0, implicit $sgpr0_sgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir b/llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir index 1c2436bd6b6cd..326cacfb375bf 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir @@ -13,7 +13,9 @@ body: | bb.0: ; CHECK-LABEL: name: merge_sgpr_spill_into_copy_from_m0 - ; CHECK: S_NOP 0, implicit-def $m0 + ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; CHECK-NEXT: S_NOP 0, implicit-def $m0 ; CHECK-NEXT: $sgpr0 = S_MOV_B32 $m0 ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, $vgpr0 @@ -43,7 +45,9 @@ body: | bb.0: ; CHECK-LABEL: name: reload_sgpr_spill_into_copy_to_m0 - ; CHECK: $vgpr0 = IMPLICIT_DEF + ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg + ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def renamable $sgpr0, implicit-def dead renamable $sgpr1, implicit-def $m0 ; CHECK-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, $vgpr0 ; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr0, 0 diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir b/llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir index 17ec6f5b37241..e861a15981186 100644 --- a/llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir +++ b/llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir @@ -21,6 +21,8 @@ body: | ; GFX11-LABEL: name: tied_operand_test ; GFX11: liveins: $sgpr0_sgpr1 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11-NEXT: renamable $vgpr0 = V_MOV_B32_e32 123, implicit $exec ; GFX11-NEXT: renamable $vgpr0 = SCRATCH_LOAD_SHORT_D16_HI_ST 0, 0, killed renamable $vgpr0, implicit $exec, implicit $flat_scr ; GFX11-NEXT: renamable $sgpr0 = S_LOAD_DWORD_IMM killed renamable $sgpr0_sgpr1, 4, 0 diff --git a/llvm/test/CodeGen/AMDGPU/frame-index.mir b/llvm/test/CodeGen/AMDGPU/frame-index.mir index 81bd8baaa0e5d..5c14af9673d1e 100644 --- a/llvm/test/CodeGen/AMDGPU/frame-index.mir +++ b/llvm/test/CodeGen/AMDGPU/frame-index.mir @@ -21,6 +21,9 @@ body: | ; GCN-LABEL: name: func_add_constant_to_fi_divergent_i32 ; GCN: liveins: $vgpr31, $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GCN-NEXT: renamable $vgpr0 = V_AND_B32_e32 1023, killed $vgpr31, implicit $exec ; GCN-NEXT: renamable $vgpr0 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec ; GCN-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec @@ -55,6 +58,10 @@ body: | ; GCN-LABEL: name: func_add_constant_to_fi_uniform_i32 ; GCN: liveins: $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GCN-NEXT: renamable $sgpr0 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; GCN-NEXT: renamable $sgpr4 = nuw S_ADD_I32 $sgpr0, 4, implicit-def dead $scc ; GCN-NEXT: renamable $vgpr0 = COPY killed renamable $sgpr4, implicit $exec @@ -91,6 +98,12 @@ body: | ; GCN-LABEL: name: func_add_constant_to_fi_uniform_SCC_clobber_i32 ; GCN: liveins: $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 ; GCN-NEXT: renamable $sgpr0 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; GCN-NEXT: renamable $sgpr4 = nuw S_ADD_U32 $sgpr0, 4, implicit-def $scc ; GCN-NEXT: renamable $sgpr5 = S_ADDC_U32 $sgpr4, 1234567, implicit-def $scc, implicit $scc @@ -132,6 +145,10 @@ body: | ; GCN-LABEL: name: func_other_fi_user_non_inline_imm_offset_i32 ; GCN: liveins: $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GCN-NEXT: renamable $vgpr0 = V_MOV_B32_e32 7, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec ; GCN-NEXT: $sgpr5 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc @@ -168,6 +185,12 @@ body: | ; GCN-LABEL: name: func_add_constant_to_fi_uniform_live_SCC_i32 ; GCN: liveins: $sgpr30_sgpr31, $sgpr10 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 ; GCN-NEXT: renamable $sgpr4 = nuw S_ADD_U32 $sgpr10, 4, implicit-def $scc ; GCN-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GCN-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec @@ -204,6 +227,9 @@ body: | ; GCN-LABEL: name: func_frame_idx_at_the_end_of_bb ; GCN: liveins: $vgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GCN-NEXT: renamable $vgpr0 = V_AND_B32_e32 1023, killed $vgpr31, implicit $exec ; GCN-NEXT: renamable $vgpr0 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec ; GCN-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec @@ -223,7 +249,10 @@ machineFunctionInfo: body: | bb.0: ; GCN-LABEL: name: materialize_fi_s_mov_b32_offset_0_dead_scc - ; GCN: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc + ; GCN: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc ; GCN-NEXT: S_ENDPGM 0, implicit $sgpr4 renamable $sgpr4 = S_MOV_B32 %stack.0 S_ENDPGM 0, implicit $sgpr4 @@ -244,6 +273,9 @@ body: | ; GCN-LABEL: name: materialize_fi_s_mov_b32_offset_0_live_scc ; GCN: liveins: $sgpr4, $sgpr5 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GCN-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GCN-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GCN-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec @@ -266,7 +298,10 @@ machineFunctionInfo: body: | bb.0: ; GCN-LABEL: name: materialize_fi_s_mov_b32_offset_64_dead_scc - ; GCN: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc + ; GCN: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc ; GCN-NEXT: $sgpr4 = S_ADD_I32 killed $sgpr4, 64, implicit-def $scc ; GCN-NEXT: S_ENDPGM 0, implicit $sgpr4 renamable $sgpr4 = S_MOV_B32 %stack.1 @@ -285,7 +320,10 @@ machineFunctionInfo: body: | bb.0: ; GCN-LABEL: name: materialize_fi_s_mov_b32_offset_68_dead_scc - ; GCN: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc + ; GCN: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc ; GCN-NEXT: $sgpr4 = S_ADD_I32 killed $sgpr4, 68, implicit-def $scc ; GCN-NEXT: S_ENDPGM 0, implicit $sgpr4 renamable $sgpr4 = S_MOV_B32 %stack.1 @@ -308,6 +346,9 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc ; GFX8: liveins: $sgpr4, $sgpr5 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX8-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: $sgpr4 = S_MOV_B32 64 @@ -318,6 +359,9 @@ body: | ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc ; GFX900: liveins: $sgpr4, $sgpr5 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX900-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX900-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: $vgpr0 = V_ADD_U32_e32 64, killed $vgpr0, implicit $exec @@ -327,6 +371,9 @@ body: | ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc ; GFX90A: liveins: $sgpr4, $sgpr5 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX90A-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX90A-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: $vgpr0 = V_ADD_U32_e32 64, killed $vgpr0, implicit $exec @@ -353,6 +400,9 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_68_live_scc ; GFX8: liveins: $sgpr4, $sgpr5 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX8-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: $sgpr4 = S_MOV_B32 68 @@ -363,6 +413,9 @@ body: | ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_68_live_scc ; GFX900: liveins: $sgpr4, $sgpr5 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX900-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX900-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: $vgpr0 = V_ADD_U32_e32 68, killed $vgpr0, implicit $exec @@ -372,6 +425,9 @@ body: | ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_68_live_scc ; GFX90A: liveins: $sgpr4, $sgpr5 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX90A-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc ; GFX90A-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: $vgpr0 = V_ADD_U32_e32 68, killed $vgpr0, implicit $exec @@ -401,22 +457,81 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_0_live_scc__no_free_vgprs ; GFX8: liveins: $sgpr4, $sgpr5, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -461,22 +576,81 @@ body: | ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_0_live_scc__no_free_vgprs ; GFX900: liveins: $sgpr4, $sgpr5, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -520,22 +694,97 @@ body: | ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_0_live_scc__no_free_vgprs ; GFX90A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $sgpr4, $sgpr5, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr40, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr40, $agpr0, 32, $exec, 64 ; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr41, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr41, $agpr1, 32, $exec, 64 ; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr42, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr42, $agpr2, 32, $exec, 64 ; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr43, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr43, $agpr3, 32, $exec, 64 ; GFX90A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr44, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr44, $agpr4, 32, $exec, 64 ; GFX90A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr45, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr45, $agpr5, 32, $exec, 64 ; GFX90A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr46, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr46, $agpr6, 32, $exec, 64 ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr47, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr47, $agpr7, 32, $exec, 64 ; GFX90A-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr56, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr56, $agpr8, 32, $exec, 64 ; GFX90A-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr57, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr57, $agpr9, 32, $exec, 64 ; GFX90A-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr58, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr58, $agpr10, 32, $exec, 64 ; GFX90A-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr59, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr59, $agpr11, 32, $exec, 64 ; GFX90A-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr60, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr60, $agpr12, 32, $exec, 64 ; GFX90A-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr61, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr61, $agpr13, 32, $exec, 64 ; GFX90A-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr62, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr62, $agpr14, 32, $exec, 64 ; GFX90A-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr63, $agpr15, 32, $exec, 64 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -615,22 +864,89 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_96_live_scc__no_free_vgprs ; GFX8: liveins: $sgpr4, $sgpr5, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256 ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -675,22 +991,89 @@ body: | ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_96_live_scc__no_free_vgprs ; GFX900: liveins: $sgpr4, $sgpr5, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX900-NEXT: {{ $}} + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256 ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -734,22 +1117,105 @@ body: | ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_96_live_scc__no_free_vgprs ; GFX90A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $sgpr4, $sgpr5, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr40, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr40, $agpr0, 32, $exec, 64 ; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr41, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr41, $agpr1, 32, $exec, 64 ; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr42, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr42, $agpr2, 32, $exec, 64 ; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr43, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr43, $agpr3, 32, $exec, 64 ; GFX90A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr44, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr44, $agpr4, 32, $exec, 64 ; GFX90A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr45, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr45, $agpr5, 32, $exec, 64 ; GFX90A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr46, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr46, $agpr6, 32, $exec, 64 ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr47, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr47, $agpr7, 32, $exec, 64 ; GFX90A-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr56, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr56, $agpr8, 32, $exec, 64 ; GFX90A-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr57, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr57, $agpr9, 32, $exec, 64 ; GFX90A-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr58, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr58, $agpr10, 32, $exec, 64 ; GFX90A-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr59, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr59, $agpr11, 32, $exec, 64 ; GFX90A-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr60, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr60, $agpr12, 32, $exec, 64 ; GFX90A-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr61, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr61, $agpr13, 32, $exec, 64 ; GFX90A-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr62, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr62, $agpr14, 32, $exec, 64 ; GFX90A-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec + ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr63, $agpr15, 32, $exec, 64 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 diff --git a/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll index 2e88da142bb41..3bd1116f5af54 100644 --- a/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll +++ b/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=true < %s | FileCheck -check-prefix=SPILL-TO-VGPR %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=false < %s | FileCheck -check-prefix=NO-SPILL-TO-VGPR %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=true -amdgpu-spill-cfi-saved-regs=false < %s | FileCheck -check-prefixes=NO-CFI-SAVES-SPILL-TO-VGPR %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=true -amdgpu-spill-cfi-saved-regs=true < %s | FileCheck -check-prefixes=CFI-SAVES-SPILL-TO-VGPR %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=false -amdgpu-spill-cfi-saved-regs=false < %s | FileCheck -check-prefixes=NO-CFI-SAVES-NO-SPILL-TO-VGPR %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-spill-sgpr-to-vgpr=false -amdgpu-spill-cfi-saved-regs=true < %s | FileCheck -check-prefixes=CFI-SAVES-NO-SPILL-TO-VGPR %s ; Check frame setup where SGPR spills to VGPRs are disabled or enabled. @@ -16,18 +18,18 @@ define void @callee_with_stack_and_call() #0 { ; SPILL-TO-VGPR-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[8:9] ; SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s4, 2 -; SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x400 ; SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s30, 0 +; SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x400 +; SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s31, 1 ; SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, 0 ; SPILL-TO-VGPR-NEXT: s_getpc_b64 s[4:5] ; SPILL-TO-VGPR-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4 ; SPILL-TO-VGPR-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12 -; SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s31, 1 ; SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 ; SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) ; SPILL-TO-VGPR-NEXT: s_swappc_b64 s[30:31], s[4:5] -; SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v40, 1 ; SPILL-TO-VGPR-NEXT: v_readlane_b32 s30, v40, 0 +; SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v40, 1 ; SPILL-TO-VGPR-NEXT: s_mov_b32 s32, s33 ; SPILL-TO-VGPR-NEXT: v_readlane_b32 s4, v40, 2 ; SPILL-TO-VGPR-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -46,21 +48,14 @@ define void @callee_with_stack_and_call() #0 { ; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; NO-SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x800 ; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec -; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1 +; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 3 ; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16 ; NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s30, 0 +; NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s31, 1 ; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16 ; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) ; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5] -; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec -; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1 -; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16 -; NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s31, 0 -; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16 -; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) -; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5] ; NO-SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, 0 ; NO-SPILL-TO-VGPR-NEXT: s_getpc_b64 s[4:5] ; NO-SPILL-TO-VGPR-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4 @@ -69,20 +64,12 @@ define void @callee_with_stack_and_call() #0 { ; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) ; NO-SPILL-TO-VGPR-NEXT: s_swappc_b64 s[30:31], s[4:5] ; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec -; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1 -; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16 -; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload -; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) -; NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v0, 0 -; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16 -; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) -; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5] -; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec -; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1 +; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 3 ; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16 ; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) ; NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s30, v0, 0 +; NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v0, 1 ; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16 ; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) ; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5] @@ -92,6 +79,153 @@ define void @callee_with_stack_and_call() #0 { ; NO-SPILL-TO-VGPR-NEXT: v_readfirstlane_b32 s4, v0 ; NO-SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s4 ; NO-SPILL-TO-VGPR-NEXT: s_setpc_b64 s[30:31] +; NO-CFI-SAVES-SPILL-TO-VGPR-LABEL: callee_with_stack_and_call: +; NO-CFI-SAVES-SPILL-TO-VGPR: ; %bb.0: +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b32 s4, s33 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s32 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_or_saveexec_b64 s[8:9], -1 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[8:9] +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s4, 2 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s30, 0 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x400 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s31, 1 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, 0 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_getpc_b64 s[4:5] +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_swappc_b64 s[30:31], s[4:5] +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: v_readlane_b32 s30, v40, 0 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v40, 1 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b32 s32, s33 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: v_readlane_b32 s4, v40, 2 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_or_saveexec_b64 s[6:7], -1 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[6:7] +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s4 +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; NO-CFI-SAVES-SPILL-TO-VGPR-NEXT: s_setpc_b64 s[30:31] +; +; CFI-SAVES-SPILL-TO-VGPR-LABEL: callee_with_stack_and_call: +; CFI-SAVES-SPILL-TO-VGPR: ; %bb.0: +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b32 s4, s33 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s32 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_or_saveexec_b64 s[8:9], -1 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[8:9] +; CFI-SAVES-SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, exec_lo, 2 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, exec_hi, 3 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s4, 4 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s30, 0 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x400 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s31, 1 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, 0 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_getpc_b64 s[4:5] +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_swappc_b64 s[30:31], s[4:5] +; CFI-SAVES-SPILL-TO-VGPR-NEXT: v_readlane_b32 s30, v40, 0 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v40, 1 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b32 s32, s33 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: v_readlane_b32 s4, v40, 4 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_or_saveexec_b64 s[6:7], -1 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[6:7] +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s4 +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; CFI-SAVES-SPILL-TO-VGPR-NEXT: s_setpc_b64 s[30:31] +; +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-LABEL: callee_with_stack_and_call: +; NO-CFI-SAVES-NO-SPILL-TO-VGPR: ; %bb.0: +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b32 s4, s33 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s32 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, s4 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x800 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 3 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s30, 0 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s31, 1 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5] +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, 0 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_getpc_b64 s[4:5] +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_swappc_b64 s[30:31], s[4:5] +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 3 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s30, v0, 0 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v0, 1 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5] +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b32 s32, s33 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_readfirstlane_b32 s4, v0 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s4 +; NO-CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_setpc_b64 s[30:31] +; +; CFI-SAVES-NO-SPILL-TO-VGPR-LABEL: callee_with_stack_and_call: +; CFI-SAVES-NO-SPILL-TO-VGPR: ; %bb.0: +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b32 s4, s33 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s32 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, exec_lo +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, exec_hi +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, s4 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x800 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 3 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:24 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s30, 0 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s31, 1 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:24 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5] +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, 0 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_getpc_b64 s[4:5] +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_swappc_b64 s[30:31], s[4:5] +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 3 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:24 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s30, v0, 0 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v0, 1 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:24 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5] +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b32 s32, s33 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0) +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: v_readfirstlane_b32 s4, v0 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s4 +; CFI-SAVES-NO-SPILL-TO-VGPR-NEXT: s_setpc_b64 s[30:31] %alloca = alloca i32, addrspace(5) store volatile i32 0, ptr addrspace(5) %alloca call void @external_void_func_void() diff --git a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll index 831d10480c51c..2a27263e16548 100644 --- a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll +++ b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll @@ -1727,21 +1727,21 @@ define void @caller_void_func_i32_v2float_inreg(i32 inreg %arg0, <2 x float> inr ; GFX9-NEXT: s_or_saveexec_b64 s[20:21], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] +; GFX9-NEXT: v_writelane_b32 v40, s19, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_getpc_b64 s[20:21] ; GFX9-NEXT: s_add_u32 s20, s20, caller_void_func_i32_v2float_inreg@gotpcrel32@lo+4 ; GFX9-NEXT: s_addc_u32 s21, s21, caller_void_func_i32_v2float_inreg@gotpcrel32@hi+12 ; GFX9-NEXT: s_load_dwordx2 s[20:21], s[20:21], 0x0 -; GFX9-NEXT: v_writelane_b32 v40, s19, 2 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s2, s18 ; GFX9-NEXT: s_mov_b32 s1, s17 ; GFX9-NEXT: s_mov_b32 s0, s16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -1759,19 +1759,18 @@ define void @caller_void_func_i32_v2float_inreg(i32 inreg %arg0, <2 x float> inr ; GFX11-NEXT: s_or_saveexec_b32 s16, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s16 +; GFX11-NEXT: v_writelane_b32 v40, s3, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[16:17] ; GFX11-NEXT: s_add_u32 s16, s16, caller_void_func_i32_v2float_inreg@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s17, s17, caller_void_func_i32_v2float_inreg@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s3, 2 ; GFX11-NEXT: s_load_b64 s[16:17], s[16:17], 0x0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -2132,21 +2131,24 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p ; GFX9-NEXT: s_or_saveexec_b64 s[40:41], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[40:41] +; GFX9-NEXT: v_writelane_b32 v40, s29, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v2, s28 ; GFX9-NEXT: global_store_dword v[0:1], v2, off offset:48 ; GFX9-NEXT: v_mov_b32_e32 v5, s27 ; GFX9-NEXT: v_mov_b32_e32 v4, s26 ; GFX9-NEXT: v_mov_b32_e32 v3, s25 ; GFX9-NEXT: v_mov_b32_e32 v2, s24 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off offset:32 -; GFX9-NEXT: v_writelane_b32 v40, s29, 2 +; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: v_mov_b32_e32 v5, s23 ; GFX9-NEXT: v_mov_b32_e32 v4, s22 ; GFX9-NEXT: v_mov_b32_e32 v3, s21 ; GFX9-NEXT: v_mov_b32_e32 v2, s20 ; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off offset:16 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: v_mov_b32_e32 v3, s17 ; GFX9-NEXT: v_mov_b32_e32 v2, s16 ; GFX9-NEXT: s_getpc_b64 s[16:17] @@ -2155,12 +2157,11 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p ; GFX9-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v5, s19 ; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -2178,7 +2179,10 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p ; GFX11-NEXT: s_or_saveexec_b32 s26, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s26 +; GFX11-NEXT: v_writelane_b32 v40, s25, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v3, s21 ; GFX11-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v9, s19 ; GFX11-NEXT: s_getpc_b64 s[20:21] @@ -2187,22 +2191,18 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p ; GFX11-NEXT: v_dual_mov_b32 v8, s18 :: v_dual_mov_b32 v7, s17 ; GFX11-NEXT: v_dual_mov_b32 v6, s16 :: v_dual_mov_b32 v13, s3 ; GFX11-NEXT: s_load_b64 s[16:17], s[20:21], 0x0 -; GFX11-NEXT: v_writelane_b32 v40, s25, 2 ; GFX11-NEXT: v_dual_mov_b32 v14, s24 :: v_dual_mov_b32 v5, s23 ; GFX11-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v10, s0 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: global_store_b32 v[0:1], v14, off offset:48 ; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off offset:32 ; GFX11-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16 ; GFX11-NEXT: global_store_b128 v[0:1], v[10:13], off -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 diff --git a/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll b/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll index 9d137fb4101e4..031f25bec26fe 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll +++ b/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll @@ -13,6 +13,7 @@ define amdgpu_gfx void @gfx_func() { ; SDAG-NEXT: s_or_saveexec_b64 s[34:35], -1 ; SDAG-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; SDAG-NEXT: s_mov_b64 exec, s[34:35] +; SDAG-NEXT: s_addk_i32 s32, 0x400 ; SDAG-NEXT: v_writelane_b32 v40, s4, 0 ; SDAG-NEXT: v_writelane_b32 v40, s5, 1 ; SDAG-NEXT: v_writelane_b32 v40, s6, 2 @@ -39,47 +40,46 @@ define amdgpu_gfx void @gfx_func() { ; SDAG-NEXT: v_writelane_b32 v40, s27, 23 ; SDAG-NEXT: v_writelane_b32 v40, s28, 24 ; SDAG-NEXT: v_writelane_b32 v40, s29, 25 -; SDAG-NEXT: v_writelane_b32 v40, s30, 26 -; SDAG-NEXT: v_writelane_b32 v40, s31, 27 -; SDAG-NEXT: v_writelane_b32 v40, s72, 28 -; SDAG-NEXT: v_writelane_b32 v40, s73, 29 -; SDAG-NEXT: v_writelane_b32 v40, s74, 30 -; SDAG-NEXT: v_writelane_b32 v40, s75, 31 -; SDAG-NEXT: v_writelane_b32 v40, s76, 32 -; SDAG-NEXT: v_writelane_b32 v40, s77, 33 -; SDAG-NEXT: v_writelane_b32 v40, s78, 34 -; SDAG-NEXT: v_writelane_b32 v40, s79, 35 -; SDAG-NEXT: v_writelane_b32 v40, s88, 36 -; SDAG-NEXT: v_writelane_b32 v40, s89, 37 -; SDAG-NEXT: v_writelane_b32 v40, s90, 38 -; SDAG-NEXT: v_writelane_b32 v40, s91, 39 -; SDAG-NEXT: v_writelane_b32 v40, s92, 40 -; SDAG-NEXT: v_writelane_b32 v40, s93, 41 -; SDAG-NEXT: v_writelane_b32 v40, s94, 42 +; SDAG-NEXT: v_writelane_b32 v40, s72, 26 +; SDAG-NEXT: v_writelane_b32 v40, s73, 27 +; SDAG-NEXT: v_writelane_b32 v40, s74, 28 +; SDAG-NEXT: v_writelane_b32 v40, s75, 29 +; SDAG-NEXT: v_writelane_b32 v40, s76, 30 +; SDAG-NEXT: v_writelane_b32 v40, s77, 31 +; SDAG-NEXT: v_writelane_b32 v40, s78, 32 +; SDAG-NEXT: v_writelane_b32 v40, s79, 33 +; SDAG-NEXT: v_writelane_b32 v40, s88, 34 +; SDAG-NEXT: v_writelane_b32 v40, s89, 35 +; SDAG-NEXT: v_writelane_b32 v40, s90, 36 +; SDAG-NEXT: v_writelane_b32 v40, s91, 37 +; SDAG-NEXT: v_writelane_b32 v40, s92, 38 +; SDAG-NEXT: v_writelane_b32 v40, s93, 39 +; SDAG-NEXT: v_writelane_b32 v40, s94, 40 +; SDAG-NEXT: v_writelane_b32 v40, s95, 41 +; SDAG-NEXT: v_writelane_b32 v40, s30, 42 +; SDAG-NEXT: v_writelane_b32 v40, s31, 43 ; SDAG-NEXT: s_mov_b32 s35, extern_c_func@abs32@hi ; SDAG-NEXT: s_mov_b32 s34, extern_c_func@abs32@lo ; SDAG-NEXT: s_mov_b64 s[8:9], 0 -; SDAG-NEXT: s_addk_i32 s32, 0x400 -; SDAG-NEXT: v_writelane_b32 v40, s95, 43 ; SDAG-NEXT: s_swappc_b64 s[30:31], s[34:35] -; SDAG-NEXT: v_readlane_b32 s95, v40, 43 -; SDAG-NEXT: v_readlane_b32 s94, v40, 42 -; SDAG-NEXT: v_readlane_b32 s93, v40, 41 -; SDAG-NEXT: v_readlane_b32 s92, v40, 40 -; SDAG-NEXT: v_readlane_b32 s91, v40, 39 -; SDAG-NEXT: v_readlane_b32 s90, v40, 38 -; SDAG-NEXT: v_readlane_b32 s89, v40, 37 -; SDAG-NEXT: v_readlane_b32 s88, v40, 36 -; SDAG-NEXT: v_readlane_b32 s79, v40, 35 -; SDAG-NEXT: v_readlane_b32 s78, v40, 34 -; SDAG-NEXT: v_readlane_b32 s77, v40, 33 -; SDAG-NEXT: v_readlane_b32 s76, v40, 32 -; SDAG-NEXT: v_readlane_b32 s75, v40, 31 -; SDAG-NEXT: v_readlane_b32 s74, v40, 30 -; SDAG-NEXT: v_readlane_b32 s73, v40, 29 -; SDAG-NEXT: v_readlane_b32 s72, v40, 28 -; SDAG-NEXT: v_readlane_b32 s31, v40, 27 -; SDAG-NEXT: v_readlane_b32 s30, v40, 26 +; SDAG-NEXT: v_readlane_b32 s30, v40, 42 +; SDAG-NEXT: v_readlane_b32 s31, v40, 43 +; SDAG-NEXT: v_readlane_b32 s95, v40, 41 +; SDAG-NEXT: v_readlane_b32 s94, v40, 40 +; SDAG-NEXT: v_readlane_b32 s93, v40, 39 +; SDAG-NEXT: v_readlane_b32 s92, v40, 38 +; SDAG-NEXT: v_readlane_b32 s91, v40, 37 +; SDAG-NEXT: v_readlane_b32 s90, v40, 36 +; SDAG-NEXT: v_readlane_b32 s89, v40, 35 +; SDAG-NEXT: v_readlane_b32 s88, v40, 34 +; SDAG-NEXT: v_readlane_b32 s79, v40, 33 +; SDAG-NEXT: v_readlane_b32 s78, v40, 32 +; SDAG-NEXT: v_readlane_b32 s77, v40, 31 +; SDAG-NEXT: v_readlane_b32 s76, v40, 30 +; SDAG-NEXT: v_readlane_b32 s75, v40, 29 +; SDAG-NEXT: v_readlane_b32 s74, v40, 28 +; SDAG-NEXT: v_readlane_b32 s73, v40, 27 +; SDAG-NEXT: v_readlane_b32 s72, v40, 26 ; SDAG-NEXT: v_readlane_b32 s29, v40, 25 ; SDAG-NEXT: v_readlane_b32 s28, v40, 24 ; SDAG-NEXT: v_readlane_b32 s27, v40, 23 @@ -122,6 +122,7 @@ define amdgpu_gfx void @gfx_func() { ; GISEL-NEXT: s_or_saveexec_b64 s[34:35], -1 ; GISEL-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GISEL-NEXT: s_mov_b64 exec, s[34:35] +; GISEL-NEXT: s_addk_i32 s32, 0x400 ; GISEL-NEXT: v_writelane_b32 v40, s4, 0 ; GISEL-NEXT: v_writelane_b32 v40, s5, 1 ; GISEL-NEXT: v_writelane_b32 v40, s6, 2 @@ -148,47 +149,46 @@ define amdgpu_gfx void @gfx_func() { ; GISEL-NEXT: v_writelane_b32 v40, s27, 23 ; GISEL-NEXT: v_writelane_b32 v40, s28, 24 ; GISEL-NEXT: v_writelane_b32 v40, s29, 25 -; GISEL-NEXT: v_writelane_b32 v40, s30, 26 -; GISEL-NEXT: v_writelane_b32 v40, s31, 27 -; GISEL-NEXT: v_writelane_b32 v40, s72, 28 -; GISEL-NEXT: v_writelane_b32 v40, s73, 29 -; GISEL-NEXT: v_writelane_b32 v40, s74, 30 -; GISEL-NEXT: v_writelane_b32 v40, s75, 31 -; GISEL-NEXT: v_writelane_b32 v40, s76, 32 -; GISEL-NEXT: v_writelane_b32 v40, s77, 33 -; GISEL-NEXT: v_writelane_b32 v40, s78, 34 -; GISEL-NEXT: v_writelane_b32 v40, s79, 35 -; GISEL-NEXT: v_writelane_b32 v40, s88, 36 -; GISEL-NEXT: v_writelane_b32 v40, s89, 37 -; GISEL-NEXT: v_writelane_b32 v40, s90, 38 -; GISEL-NEXT: v_writelane_b32 v40, s91, 39 -; GISEL-NEXT: v_writelane_b32 v40, s92, 40 -; GISEL-NEXT: v_writelane_b32 v40, s93, 41 -; GISEL-NEXT: v_writelane_b32 v40, s94, 42 +; GISEL-NEXT: v_writelane_b32 v40, s72, 26 +; GISEL-NEXT: v_writelane_b32 v40, s73, 27 +; GISEL-NEXT: v_writelane_b32 v40, s74, 28 +; GISEL-NEXT: v_writelane_b32 v40, s75, 29 +; GISEL-NEXT: v_writelane_b32 v40, s76, 30 +; GISEL-NEXT: v_writelane_b32 v40, s77, 31 +; GISEL-NEXT: v_writelane_b32 v40, s78, 32 +; GISEL-NEXT: v_writelane_b32 v40, s79, 33 +; GISEL-NEXT: v_writelane_b32 v40, s88, 34 +; GISEL-NEXT: v_writelane_b32 v40, s89, 35 +; GISEL-NEXT: v_writelane_b32 v40, s90, 36 +; GISEL-NEXT: v_writelane_b32 v40, s91, 37 +; GISEL-NEXT: v_writelane_b32 v40, s92, 38 +; GISEL-NEXT: v_writelane_b32 v40, s93, 39 +; GISEL-NEXT: v_writelane_b32 v40, s94, 40 +; GISEL-NEXT: v_writelane_b32 v40, s95, 41 +; GISEL-NEXT: v_writelane_b32 v40, s30, 42 +; GISEL-NEXT: v_writelane_b32 v40, s31, 43 ; GISEL-NEXT: s_mov_b32 s34, extern_c_func@abs32@lo ; GISEL-NEXT: s_mov_b32 s35, extern_c_func@abs32@hi ; GISEL-NEXT: s_mov_b64 s[8:9], 0 -; GISEL-NEXT: s_addk_i32 s32, 0x400 -; GISEL-NEXT: v_writelane_b32 v40, s95, 43 ; GISEL-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GISEL-NEXT: v_readlane_b32 s95, v40, 43 -; GISEL-NEXT: v_readlane_b32 s94, v40, 42 -; GISEL-NEXT: v_readlane_b32 s93, v40, 41 -; GISEL-NEXT: v_readlane_b32 s92, v40, 40 -; GISEL-NEXT: v_readlane_b32 s91, v40, 39 -; GISEL-NEXT: v_readlane_b32 s90, v40, 38 -; GISEL-NEXT: v_readlane_b32 s89, v40, 37 -; GISEL-NEXT: v_readlane_b32 s88, v40, 36 -; GISEL-NEXT: v_readlane_b32 s79, v40, 35 -; GISEL-NEXT: v_readlane_b32 s78, v40, 34 -; GISEL-NEXT: v_readlane_b32 s77, v40, 33 -; GISEL-NEXT: v_readlane_b32 s76, v40, 32 -; GISEL-NEXT: v_readlane_b32 s75, v40, 31 -; GISEL-NEXT: v_readlane_b32 s74, v40, 30 -; GISEL-NEXT: v_readlane_b32 s73, v40, 29 -; GISEL-NEXT: v_readlane_b32 s72, v40, 28 -; GISEL-NEXT: v_readlane_b32 s31, v40, 27 -; GISEL-NEXT: v_readlane_b32 s30, v40, 26 +; GISEL-NEXT: v_readlane_b32 s30, v40, 42 +; GISEL-NEXT: v_readlane_b32 s31, v40, 43 +; GISEL-NEXT: v_readlane_b32 s95, v40, 41 +; GISEL-NEXT: v_readlane_b32 s94, v40, 40 +; GISEL-NEXT: v_readlane_b32 s93, v40, 39 +; GISEL-NEXT: v_readlane_b32 s92, v40, 38 +; GISEL-NEXT: v_readlane_b32 s91, v40, 37 +; GISEL-NEXT: v_readlane_b32 s90, v40, 36 +; GISEL-NEXT: v_readlane_b32 s89, v40, 35 +; GISEL-NEXT: v_readlane_b32 s88, v40, 34 +; GISEL-NEXT: v_readlane_b32 s79, v40, 33 +; GISEL-NEXT: v_readlane_b32 s78, v40, 32 +; GISEL-NEXT: v_readlane_b32 s77, v40, 31 +; GISEL-NEXT: v_readlane_b32 s76, v40, 30 +; GISEL-NEXT: v_readlane_b32 s75, v40, 29 +; GISEL-NEXT: v_readlane_b32 s74, v40, 28 +; GISEL-NEXT: v_readlane_b32 s73, v40, 27 +; GISEL-NEXT: v_readlane_b32 s72, v40, 26 ; GISEL-NEXT: v_readlane_b32 s29, v40, 25 ; GISEL-NEXT: v_readlane_b32 s28, v40, 24 ; GISEL-NEXT: v_readlane_b32 s27, v40, 23 diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll index 234eaa8af7edf..5ada43298deb6 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll +++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll @@ -133,16 +133,16 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i1@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i1@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -162,16 +162,16 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_mov_b32_e32 v0, 1 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -191,17 +191,16 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_mov_b32_e32 v0, 1 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: v_mov_b32_e32 v0, 1 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: scratch_store_b8 off, v0, s32 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -221,16 +220,16 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -253,19 +252,19 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc -; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc +; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i1_signext@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i1_signext@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -284,19 +283,19 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_signext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_signext@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -315,19 +314,19 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_signext@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_signext@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX11-NEXT: scratch_store_b8 off, v0, s32 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -346,19 +345,19 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_signext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_signext@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -382,19 +381,19 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc -; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc +; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i1_zeroext@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i1_zeroext@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -413,19 +412,19 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_zeroext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_zeroext@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -444,19 +443,19 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_zeroext@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_zeroext@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX11-NEXT: scratch_store_b8 off, v0, s32 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -475,19 +474,19 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_zeroext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_zeroext@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -513,14 +512,14 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -540,15 +539,15 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -568,16 +567,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 { ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7b ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -596,16 +595,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 { ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -625,15 +624,15 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -656,17 +655,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_sbyte v0, v[0:1], off glc -; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_signext@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_signext@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_sbyte v0, v[0:1], off glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_signext@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_signext@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -685,17 +684,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: global_load_sbyte v0, v[0:1], off glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_signext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_signext@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -714,18 +713,18 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: global_load_d16_i8 v0, v[0:1], off glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_signext@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_signext@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -743,18 +742,18 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: global_load_i8 v0, v[0:1], off glc dlc ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_signext@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_signext@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -773,17 +772,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: global_load_sbyte v0, v[0:1], off glc dlc ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_signext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_signext@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -807,17 +806,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc -; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_zeroext@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_zeroext@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_zeroext@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_zeroext@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -836,17 +835,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_zeroext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_zeroext@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -865,18 +864,18 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -894,18 +893,18 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: global_load_u8 v0, v[0:1], off glc dlc ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -924,17 +923,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -960,14 +959,14 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -987,15 +986,15 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -1015,16 +1014,16 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 { ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7b ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 -; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -1043,16 +1042,16 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 { ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -1072,15 +1071,15 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -1103,17 +1102,17 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc -; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_signext@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_signext@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_signext@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_signext@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -1132,17 +1131,17 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_signext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_signext@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -1161,18 +1160,18 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16_signext@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16_signext@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -1190,18 +1189,18 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off glc dlc ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16_signext@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16_signext@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -1220,17 +1219,17 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off glc dlc ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_signext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_signext@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -1254,17 +1253,17 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc -; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_zeroext@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_zeroext@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_zeroext@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_zeroext@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -1283,17 +1282,17 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_zeroext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_zeroext@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -1312,18 +1311,18 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -1341,18 +1340,18 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off glc dlc ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -1371,17 +1370,17 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off glc dlc ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -1407,14 +1406,14 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 42 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -1434,15 +1433,15 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -1462,16 +1461,16 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 42 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1491,15 +1490,15 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -1524,15 +1523,15 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i64@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -1552,16 +1551,16 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i64@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -1581,16 +1580,16 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_dual_mov_b32 v0, 0x7b :: v_dual_mov_b32 v1, 0 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_i64@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_i64@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: v_dual_mov_b32 v0, 0x7b :: v_dual_mov_b32 v1, 0 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_i64@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_i64@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1610,16 +1609,16 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i64@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -1642,18 +1641,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i64@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -1672,18 +1671,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -1702,19 +1701,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1733,18 +1731,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -1770,17 +1768,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i64@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 2 ; GFX9-NEXT: v_mov_b32_e32 v2, 3 ; GFX9-NEXT: v_mov_b32_e32 v3, 4 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -1800,18 +1798,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-NEXT: v_mov_b32_e32 v3, 4 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -1831,17 +1829,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 ; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1861,18 +1859,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -1895,20 +1893,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i64@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v4, 1 ; GFX9-NEXT: v_mov_b32_e32 v5, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -1927,20 +1925,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-NEXT: v_mov_b32_e32 v5, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i64@abs32@hi -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i64@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -1959,19 +1957,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 2 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i64@abs32@lo ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1990,20 +1987,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i64@abs32@hi -; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i64@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -2029,22 +2026,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i64@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v4, 1 ; GFX9-NEXT: v_mov_b32_e32 v5, 2 ; GFX9-NEXT: v_mov_b32_e32 v6, 3 ; GFX9-NEXT: v_mov_b32_e32 v7, 4 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -2063,22 +2060,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-NEXT: v_mov_b32_e32 v5, 2 ; GFX10-NEXT: v_mov_b32_e32 v6, 3 -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v7, 4 +; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i64@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -2097,20 +2094,20 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 2 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: v_dual_mov_b32 v6, 3 :: v_dual_mov_b32 v7, 4 -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i64@abs32@hi -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i64@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -2129,22 +2126,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 3 -; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 4 +; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i64@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -2171,14 +2168,14 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_f16@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_f16@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4400 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -2198,15 +2195,15 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x4400 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_f16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_f16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -2226,16 +2223,16 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 { ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x4400 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_f16@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_f16@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -2254,16 +2251,16 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 { ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x4400 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_f16@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_f16@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -2283,15 +2280,15 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x4400 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -2316,14 +2313,14 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_f32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_f32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 4.0 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -2343,15 +2340,15 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 4.0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_f32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_f32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -2371,16 +2368,16 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 4.0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_f32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_f32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -2400,15 +2397,15 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 4.0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -2433,15 +2430,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX9-NEXT: v_mov_b32_e32 v1, 2.0 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -2461,16 +2458,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -2490,16 +2487,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f32@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f32@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f32@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f32@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -2519,16 +2516,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -2553,16 +2550,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX9-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX9-NEXT: v_mov_b32_e32 v2, 4.0 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -2582,17 +2579,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f32@abs32@hi -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -2612,17 +2609,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0 ; GFX11-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f32@abs32@hi -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -2642,17 +2639,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f32@abs32@hi -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -2677,6 +2674,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5f32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5f32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 1.0 @@ -2684,11 +2683,9 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 { ; GFX9-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX9-NEXT: v_mov_b32_e32 v3, -1.0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0.5 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -2708,19 +2705,19 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX10-NEXT: v_mov_b32_e32 v3, -1.0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0.5 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5f32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5f32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -2740,18 +2737,18 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0 ; GFX11-NEXT: v_dual_mov_b32 v2, 4.0 :: v_dual_mov_b32 v3, -1.0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v4, 0.5 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5f32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5f32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -2771,19 +2768,19 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, -1.0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0.5 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5f32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5f32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -2808,15 +2805,15 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_f64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_f64@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x40100000 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -2836,16 +2833,16 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x40100000 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_f64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_f64@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -2865,16 +2862,16 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x40100000 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_f64@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_f64@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x40100000 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_f64@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_f64@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -2894,16 +2891,16 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x40100000 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f64@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -2928,17 +2925,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f64@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0x40100000 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -2958,18 +2955,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0x40100000 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f64@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -2989,17 +2986,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 2.0 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x40100000 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f64@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -3019,18 +3016,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0x40100000 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f64@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -3055,6 +3052,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f64@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 0 @@ -3063,11 +3062,9 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 { ; GFX9-NEXT: v_mov_b32_e32 v3, 0x40100000 ; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0x40200000 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -3087,20 +3084,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0x40100000 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0x40200000 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f64@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -3120,18 +3117,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 2.0 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x40100000 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0x40200000 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f64@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -3151,20 +3148,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0x40100000 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 0x40200000 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f64@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -3187,21 +3184,21 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_ushort v0, v[0:1], off -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v1, 8 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i8@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -3220,21 +3217,21 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i8@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-NEXT: v_mov_b32_e32 v1, 8 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -3253,22 +3250,22 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v2i8@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v2i8@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -3286,22 +3283,22 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v2i8@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v2i8@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -3320,21 +3317,21 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i8@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -3358,21 +3355,21 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dword v0, v[0:1], off -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -3391,21 +3388,21 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dword v0, v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -3424,21 +3421,21 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i8@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i8@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b32 v0, v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -3457,21 +3454,21 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -3495,22 +3492,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dword v0, v[0:1], off -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i8@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -3529,22 +3526,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i8@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dword v0, v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -3563,22 +3560,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i8@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i8@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b32 v0, v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v3, 24, v0 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -3597,22 +3594,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i8@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v3, 24, v0 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -3636,15 +3633,15 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dwordx2 v[5:6], v[0:1], off -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i8@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v5 @@ -3652,8 +3649,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, v5 ; GFX9-NEXT: v_mov_b32_e32 v4, v6 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -3672,15 +3669,15 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i8@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dwordx2 v[5:6], v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v5 @@ -3688,8 +3685,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX10-NEXT: v_mov_b32_e32 v0, v5 ; GFX10-NEXT: v_mov_b32_e32 v4, v6 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -3708,15 +3705,15 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i8@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i8@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b64 v[5:6], v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v5 @@ -3724,8 +3721,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX11-NEXT: v_mov_b32_e32 v0, v5 ; GFX11-NEXT: v_mov_b32_e32 v4, v6 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -3744,15 +3741,15 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i8@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[5:6], v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v5 @@ -3760,8 +3757,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, v5 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, v6 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -3785,15 +3782,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i8@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -3804,8 +3801,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX9-NEXT: v_mov_b32_e32 v4, v1 ; GFX9-NEXT: v_mov_b32_e32 v1, v8 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -3824,15 +3821,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i8@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -3843,8 +3840,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX10-NEXT: v_mov_b32_e32 v4, v1 ; GFX10-NEXT: v_mov_b32_e32 v1, v8 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -3863,15 +3860,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i8@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i8@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshrrev_b32_e32 v8, 8, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -3881,8 +3878,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v1 ; GFX11-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v8 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -3901,15 +3898,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i8@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v8, 8, v0 ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -3920,8 +3917,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, v1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, v8 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -3945,18 +3942,18 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 16 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: global_load_dwordx4 v[16:19], v[4:5], off -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i8@abs32@hi +; GFX9-NEXT: global_load_dwordx4 v[16:19], v[4:5], off ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i8@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v0 @@ -3996,8 +3993,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX9-NEXT: v_mov_b32_e32 v18, v33 ; GFX9-NEXT: v_mov_b32_e32 v19, v34 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -4016,19 +4013,19 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 16 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i8@abs32@lo ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-NEXT: global_load_dwordx4 v[16:19], v[4:5], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: v_lshrrev_b32_e32 v35, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v0 @@ -4068,8 +4065,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX10-NEXT: v_mov_b32_e32 v18, v33 ; GFX10-NEXT: v_mov_b32_e32 v19, v34 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -4088,17 +4085,18 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16 ; GFX11-NEXT: v_mov_b32_e32 v5, 0 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i8@abs32@hi -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i8@abs32@lo +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: global_load_b128 v[16:19], v[4:5], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v0 @@ -4135,8 +4133,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX11-NEXT: v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33 ; GFX11-NEXT: v_mov_b32_e32 v19, v34 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -4155,19 +4153,19 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 16 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i8@abs32@lo ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[16:19], v[4:5], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v35, 8, v0 ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v36, 16, v0 @@ -4207,8 +4205,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v18, v33 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v19, v34 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -4233,24 +4231,24 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v42, s30, 0 +; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_ubyte v0, v[40:41], off -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 -; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_ret@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX9-NEXT: global_store_byte v[40:41], v0, off ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: v_readlane_b32 s30, v42, 0 +; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v42, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -4269,24 +4267,24 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_ret@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_ubyte v0, v[40:41], off -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: global_store_byte v[40:41], v0, off ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 -; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v42, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -4305,25 +4303,26 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_ret@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v[40:41], off -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: global_store_b8 v[40:41], v0, off ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33 ; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4 -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -4341,25 +4340,26 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_ret@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_u8 v0, v[40:41], off -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: global_store_b8 v[40:41], v0, off ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33 ; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -4378,24 +4378,24 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_ret@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[40:41], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: global_store_byte v[40:41], v0, off ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 ; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -4421,18 +4421,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v42, s30, 0 +; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_ushort v0, v[40:41], off -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v1, 8 -; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i8_ret@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -4442,8 +4442,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: v_readlane_b32 s30, v42, 0 +; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v42, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -4462,24 +4462,24 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v1, 8 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i8_ret@abs32@lo ; GFX10-NEXT: global_load_ushort v0, v[40:41], off -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1 -; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v42, 2 ; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -4503,18 +4503,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[40:41], off -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) @@ -4522,8 +4523,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 @@ -4547,18 +4548,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_u16 v0, v[40:41], off -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) @@ -4566,8 +4568,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 @@ -4591,24 +4593,24 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret@abs32@lo ; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[40:41], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2 ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -4639,17 +4641,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v42, s30, 0 +; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_dword v0, v[40:41], off -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 -; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -4663,8 +4665,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: v_readlane_b32 s30, v42, 0 +; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v42, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -4683,17 +4685,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dword v0, v[40:41], off -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -4701,8 +4703,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1 ; GFX10-NEXT: v_mov_b32_e32 v3, 2 ; GFX10-NEXT: v_mov_b32_e32 v4, 0 -; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v42, 2 @@ -4727,36 +4729,37 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_b32 v0, v[40:41], off -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 2 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0 ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: global_store_b8 v[3:4], v2, off ; GFX11-TRUE16-NEXT: global_store_b16 v[40:41], v0, off ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33 ; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4 -; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -4774,18 +4777,19 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_b32 v0, v[40:41], off -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -4795,8 +4799,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 2 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2 @@ -4822,17 +4826,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dword v0, v[40:41], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -4840,8 +4844,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2 @@ -4873,17 +4877,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v42, s30, 0 +; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_dword v0, v[40:41], off -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 -; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i8_ret@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -4898,8 +4902,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: v_readlane_b32 s30, v42, 0 +; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v42, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -4918,17 +4922,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i8_ret@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dword v0, v[40:41], off -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -4936,8 +4940,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1 ; GFX10-NEXT: v_lshlrev_b16 v3, 8, v3 -; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -4963,18 +4967,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_b32 v0, v[40:41], off -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -4985,11 +4990,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l ; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1 -; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: global_store_b32 v[40:41], v0, off ; GFX11-TRUE16-NEXT: s_clause 0x1 @@ -5011,18 +5016,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_b32 v0, v[40:41], off -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -5033,8 +5039,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3 @@ -5064,17 +5070,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dword v0, v[40:41], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -5082,8 +5088,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1 ; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v3, 8, v3 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -5116,17 +5122,17 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v42, s30, 0 +; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_dwordx2 v[5:6], v[40:41], off -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 -; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i8_ret@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v5 @@ -5146,8 +5152,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: v_readlane_b32 s30, v42, 0 +; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v42, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -5166,17 +5172,17 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i8_ret@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dwordx2 v[5:6], v[40:41], off -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v5 @@ -5186,8 +5192,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1 ; GFX10-NEXT: v_lshlrev_b16 v3, 8, v3 -; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_or_b32_sdwa v5, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -5216,18 +5222,19 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_b64 v[5:6], v[40:41], off -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v5 @@ -5242,7 +5249,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 4 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0 ; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0 ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: global_store_b8 v[2:3], v4, off @@ -5251,7 +5258,6 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33 ; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4 ; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1 -; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -5269,18 +5275,19 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_b64 v[5:6], v[40:41], off -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v5 @@ -5293,8 +5300,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3 @@ -5327,17 +5334,17 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[5:6], v[40:41], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v5 @@ -5347,8 +5354,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1 ; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v3, 8, v3 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v5, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -5384,17 +5391,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v42, s30, 0 +; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[40:41], off -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 -; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i8_ret@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -5419,8 +5426,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: v_readlane_b32 s30, v42, 0 +; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v42, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -5439,17 +5446,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i8_ret@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[40:41], off -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -5464,12 +5471,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX10-NEXT: v_lshlrev_b16 v7, 8, v7 ; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1 ; GFX10-NEXT: v_lshlrev_b16 v3, 8, v3 -; GFX10-NEXT: v_readlane_b32 s31, v42, 1 +; GFX10-NEXT: v_readlane_b32 s30, v42, 0 ; GFX10-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: v_or_b32_sdwa v5, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX10-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX10-NEXT: v_readlane_b32 s34, v42, 2 @@ -5494,18 +5501,19 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret@abs32@lo -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[40:41], off -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v0 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -5527,14 +5535,13 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v1.h, v0.h ; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v3.h, v2.h ; GFX11-TRUE16-NEXT: v_or_b16 v3.h, v2.l, v3.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0 ; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v0.l, v1.l ; GFX11-TRUE16-NEXT: global_store_b64 v[40:41], v[3:4], off ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33 ; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4 ; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1 -; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -5552,18 +5559,19 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret@abs32@lo -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_b64 v[0:1], v[40:41], off -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 8, v0 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -5585,12 +5593,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 +; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v4 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v5 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3 @@ -5617,17 +5625,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[40:41], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v8, 8, v0 ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0 @@ -5642,12 +5650,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v7, 8, v7 ; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1 ; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v3, 8, v3 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0 ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v5, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2 @@ -5679,22 +5687,22 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v44, s34, 2 +; GFX9-NEXT: s_addk_i32 s32, 0x800 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v44, s30, 0 +; GFX9-NEXT: v_writelane_b32 v44, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v42, 16 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: v_mov_b32_e32 v43, 0 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[40:41], off ; GFX9-NEXT: global_load_dwordx4 v[16:19], v[42:43], off -; GFX9-NEXT: v_writelane_b32 v44, s34, 2 -; GFX9-NEXT: v_writelane_b32 v44, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x800 -; GFX9-NEXT: v_writelane_b32 v44, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v0 @@ -5781,8 +5789,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v44, 1 ; GFX9-NEXT: v_readlane_b32 s30, v44, 0 +; GFX9-NEXT: v_readlane_b32 s31, v44, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v44, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -5801,23 +5809,23 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v44, s34, 2 +; GFX10-NEXT: s_addk_i32 s32, 0x400 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v44, s30, 0 +; GFX10-NEXT: v_writelane_b32 v44, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v42, 16 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 ; GFX10-NEXT: v_mov_b32_e32 v43, 0 -; GFX10-NEXT: v_writelane_b32 v44, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret@abs32@lo ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[40:41], off ; GFX10-NEXT: global_load_dwordx4 v[16:19], v[42:43], off -; GFX10-NEXT: v_writelane_b32 v44, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x400 -; GFX10-NEXT: v_writelane_b32 v44, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: v_lshrrev_b32_e32 v35, 8, v0 ; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v0 @@ -5904,8 +5912,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:12 -; GFX10-NEXT: v_readlane_b32 s31, v44, 1 ; GFX10-NEXT: v_readlane_b32 s30, v44, 0 +; GFX10-NEXT: v_readlane_b32 s31, v44, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v44, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -5924,22 +5932,26 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s0, 2 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 32 ; GFX11-TRUE16-NEXT: s_clause 0x3 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:12 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 offset:8 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:4 +; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s33 +; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v42, 16 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v43, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi -; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v[40:41], off ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo +; GFX11-TRUE16-NEXT: s_clause 0x1 +; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v[40:41], off ; GFX11-TRUE16-NEXT: global_load_b128 v[16:19], v[42:43], off -; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s30, 0 -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 32 -; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v0 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0 @@ -6032,8 +6044,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s33 offset:4 ; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33 offset:8 ; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:12 -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v44, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v44, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v44, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v44, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -6051,22 +6063,26 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s0, 2 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 32 ; GFX11-FAKE16-NEXT: s_clause 0x3 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:12 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 offset:8 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:4 +; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s33 +; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s31, 1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v42, 16 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v43, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi -; GFX11-FAKE16-NEXT: global_load_b128 v[0:3], v[40:41], off ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo +; GFX11-FAKE16-NEXT: s_clause 0x1 +; GFX11-FAKE16-NEXT: global_load_b128 v[0:3], v[40:41], off ; GFX11-FAKE16-NEXT: global_load_b128 v[16:19], v[42:43], off -; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s30, 0 -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 32 -; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v0 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0 @@ -6183,8 +6199,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s33 offset:4 ; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33 offset:8 ; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:12 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v44, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v44, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v44, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v44, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -6203,23 +6219,23 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v44, s33 offset:16 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s0, 2 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:12 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v43, s33 ; 4-byte Folded Spill +; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v42, 16 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v43, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[40:41], off ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[16:19], v[42:43], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v35, 8, v0 ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v36, 16, v0 @@ -6306,8 +6322,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:4 ; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 offset:8 ; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:12 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v44, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v44, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v44, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v44, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -6334,16 +6350,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -6362,16 +6378,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: global_load_dword v0, v[0:1], off ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: global_load_dword v0, v[0:1], off +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -6390,17 +6406,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: global_load_b32 v0, v[0:1], off +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -6419,16 +6435,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -6452,16 +6468,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -6480,16 +6496,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -6508,17 +6524,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -6537,16 +6553,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -6570,16 +6586,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -6598,16 +6614,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -6626,17 +6642,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -6655,16 +6671,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -6690,15 +6706,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX9-NEXT: v_mov_b32_e32 v1, 3 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -6718,16 +6734,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX10-NEXT: v_mov_b32_e32 v1, 3 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -6747,16 +6763,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_dual_mov_b32 v0, 0x20001 :: v_dual_mov_b32 v1, 3 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: v_dual_mov_b32 v0, 0x20001 :: v_dual_mov_b32 v1, 3 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -6776,16 +6792,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 3 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -6810,15 +6826,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 0x40003c00 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x4400 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -6838,16 +6854,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x40003c00 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x4400 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -6867,17 +6883,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x40003c00 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x4400 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -6897,16 +6913,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x40003c00 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x4400 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -6929,16 +6945,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -6957,16 +6973,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -6985,17 +7001,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -7014,16 +7030,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -7049,15 +7065,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x40003 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -7077,16 +7093,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x40003 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -7106,17 +7122,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x40003 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -7136,16 +7152,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x40003 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -7168,16 +7184,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -7196,16 +7212,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: global_load_dword v0, v[0:1], off ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: global_load_dword v0, v[0:1], off +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -7224,17 +7240,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: global_load_b32 v0, v[0:1], off +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -7253,16 +7269,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -7286,16 +7302,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -7314,16 +7330,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -7342,17 +7358,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -7371,16 +7387,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -7406,15 +7422,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -7434,16 +7450,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -7463,16 +7479,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -7492,16 +7508,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -7526,16 +7542,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 3 ; GFX9-NEXT: v_mov_b32_e32 v1, 4 ; GFX9-NEXT: v_mov_b32_e32 v2, 5 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -7555,17 +7571,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-NEXT: v_mov_b32_e32 v1, 4 ; GFX10-NEXT: v_mov_b32_e32 v2, 5 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32@abs32@hi -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -7585,17 +7601,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 4 ; GFX11-NEXT: v_mov_b32_e32 v2, 5 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32@abs32@hi -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -7615,17 +7631,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 4 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 5 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32@abs32@hi -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -7650,17 +7666,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 3 ; GFX9-NEXT: v_mov_b32_e32 v1, 4 ; GFX9-NEXT: v_mov_b32_e32 v2, 5 ; GFX9-NEXT: v_mov_b32_e32 v3, 6 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -7680,18 +7696,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-NEXT: v_mov_b32_e32 v1, 4 ; GFX10-NEXT: v_mov_b32_e32 v2, 5 ; GFX10-NEXT: v_mov_b32_e32 v3, 6 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -7711,17 +7727,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 4 ; GFX11-NEXT: v_dual_mov_b32 v2, 5 :: v_dual_mov_b32 v3, 6 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -7741,18 +7757,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 4 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 5 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 6 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -7775,16 +7791,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -7803,16 +7819,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -7831,17 +7847,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -7860,16 +7876,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -7895,17 +7911,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 2 ; GFX9-NEXT: v_mov_b32_e32 v2, 3 ; GFX9-NEXT: v_mov_b32_e32 v3, 4 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -7925,18 +7941,18 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-NEXT: v_mov_b32_e32 v3, 4 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -7956,17 +7972,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 ; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -7986,18 +8002,18 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -8022,6 +8038,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 1 @@ -8029,11 +8047,9 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 { ; GFX9-NEXT: v_mov_b32_e32 v2, 3 ; GFX9-NEXT: v_mov_b32_e32 v3, 4 ; GFX9-NEXT: v_mov_b32_e32 v4, 5 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -8053,19 +8069,19 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-NEXT: v_mov_b32_e32 v3, 4 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 5 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -8085,18 +8101,18 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 ; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v4, 5 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -8116,19 +8132,19 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 5 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -8152,19 +8168,19 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 -; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_dwordx4 v[0:3], v8, s[34:35] ; GFX9-NEXT: global_load_dwordx4 v[4:7], v8, s[34:35] offset:16 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i32@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -8184,20 +8200,21 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v8, s[34:35] ; GFX10-NEXT: global_load_dwordx4 v[4:7], v8, s[34:35] offset:16 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -8217,21 +8234,21 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_mov_b32_e32 v4, 0 -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: global_load_b128 v[0:3], v4, s[0:1] ; GFX11-NEXT: global_load_b128 v[4:7], v4, s[0:1] offset:16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -8251,20 +8268,21 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v8, s[0:1] ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v8, s[0:1] offset:16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -8291,6 +8309,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 1 @@ -8301,11 +8321,9 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 { ; GFX9-NEXT: v_mov_b32_e32 v5, 6 ; GFX9-NEXT: v_mov_b32_e32 v6, 7 ; GFX9-NEXT: v_mov_b32_e32 v7, 8 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -8325,22 +8343,22 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-NEXT: v_mov_b32_e32 v3, 4 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 5 ; GFX10-NEXT: v_mov_b32_e32 v5, 6 ; GFX10-NEXT: v_mov_b32_e32 v6, 7 ; GFX10-NEXT: v_mov_b32_e32 v7, 8 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -8360,19 +8378,19 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 ; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v4, 5 :: v_dual_mov_b32 v5, 6 ; GFX11-NEXT: v_dual_mov_b32 v6, 7 :: v_dual_mov_b32 v7, 8 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -8392,22 +8410,22 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 5 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 6 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 7 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 8 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -8431,10 +8449,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 -; GFX9-NEXT: v_mov_b32_e32 v16, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v16, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_dwordx4 v[0:3], v16, s[34:35] ; GFX9-NEXT: global_load_dwordx4 v[4:7], v16, s[34:35] offset:16 @@ -8442,10 +8461,9 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX9-NEXT: global_load_dwordx4 v[12:15], v16, s[34:35] offset:48 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16i32@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -8465,22 +8483,23 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v16, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x3 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v16, s[34:35] ; GFX10-NEXT: global_load_dwordx4 v[4:7], v16, s[34:35] offset:16 ; GFX10-NEXT: global_load_dwordx4 v[8:11], v16, s[34:35] offset:32 ; GFX10-NEXT: global_load_dwordx4 v[12:15], v16, s[34:35] offset:48 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16i32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -8500,23 +8519,23 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_mov_b32_e32 v12, 0 -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: global_load_b128 v[0:3], v12, s[0:1] ; GFX11-NEXT: global_load_b128 v[4:7], v12, s[0:1] offset:16 ; GFX11-NEXT: global_load_b128 v[8:11], v12, s[0:1] offset:32 ; GFX11-NEXT: global_load_b128 v[12:15], v12, s[0:1] offset:48 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16i32@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -8536,22 +8555,23 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v16, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x3 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v16, s[0:1] ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v16, s[0:1] offset:16 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[8:11], v16, s[0:1] offset:32 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[12:15], v16, s[0:1] offset:48 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16i32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -8577,10 +8597,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 -; GFX9-NEXT: v_mov_b32_e32 v28, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v28, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_dwordx4 v[0:3], v28, s[34:35] ; GFX9-NEXT: global_load_dwordx4 v[4:7], v28, s[34:35] offset:16 @@ -8593,10 +8614,9 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX9-NEXT: global_load_dwordx4 v[28:31], v28, s[34:35] offset:112 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -8616,9 +8636,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v32, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x7 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v32, s[34:35] @@ -8629,13 +8651,12 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX10-NEXT: global_load_dwordx4 v[20:23], v32, s[34:35] offset:80 ; GFX10-NEXT: global_load_dwordx4 v[24:27], v32, s[34:35] offset:96 ; GFX10-NEXT: global_load_dwordx4 v[28:31], v32, s[34:35] offset:112 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -8655,9 +8676,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_mov_b32_e32 v28, 0 -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_clause 0x7 ; GFX11-NEXT: global_load_b128 v[0:3], v28, s[0:1] @@ -8668,14 +8691,12 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX11-NEXT: global_load_b128 v[20:23], v28, s[0:1] offset:80 ; GFX11-NEXT: global_load_b128 v[24:27], v28, s[0:1] offset:96 ; GFX11-NEXT: global_load_b128 v[28:31], v28, s[0:1] offset:112 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i32@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -8695,9 +8716,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v32, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x7 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v32, s[0:1] @@ -8708,13 +8731,12 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[20:23], v32, s[0:1] offset:80 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[24:27], v32, s[0:1] offset:96 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[28:31], v32, s[0:1] offset:112 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -8740,10 +8762,12 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v28, 0 ; GFX9-NEXT: global_load_dword v32, v[0:1], off -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_dwordx4 v[0:3], v28, s[34:35] ; GFX9-NEXT: global_load_dwordx4 v[4:7], v28, s[34:35] offset:16 @@ -8754,15 +8778,13 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX9-NEXT: global_load_dwordx4 v[24:27], v28, s[34:35] offset:96 ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: global_load_dwordx4 v[28:31], v28, s[34:35] offset:112 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32_i32@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(8) ; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -8782,9 +8804,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v32, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dword v33, v[0:1], off ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x7 @@ -8796,15 +8820,14 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX10-NEXT: global_load_dwordx4 v[20:23], v32, s[34:35] offset:80 ; GFX10-NEXT: global_load_dwordx4 v[24:27], v32, s[34:35] offset:96 ; GFX10-NEXT: global_load_dwordx4 v[28:31], v32, s[34:35] offset:112 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32_i32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(8) ; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -8824,9 +8847,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_mov_b32_e32 v28, 0 -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b32 v32, v[0:1], off ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_clause 0x7 @@ -8838,15 +8863,13 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX11-NEXT: global_load_b128 v[20:23], v28, s[0:1] offset:80 ; GFX11-NEXT: global_load_b128 v[24:27], v28, s[0:1] offset:96 ; GFX11-NEXT: global_load_b128 v[28:31], v28, s[0:1] offset:112 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i32_i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i32_i32@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(8) ; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -8866,9 +8889,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v32, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dword v33, v[0:1], off ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x7 @@ -8880,15 +8905,14 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[20:23], v32, s[0:1] offset:80 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[24:27], v32, s[0:1] offset:96 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[28:31], v32, s[0:1] offset:112 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i32_i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32_i32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(8) ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v33, s32 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -8915,23 +8939,23 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v42, s34, 2 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: v_writelane_b32 v42, s30, 0 +; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v40, v0 ; GFX9-NEXT: s_mov_b32 s35, external_i32_func_i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_i32_func_i32@abs32@lo ; GFX9-NEXT: v_mov_b32_e32 v0, 42 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v41, v1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX9-NEXT: global_store_dword v[40:41], v0, off ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: v_readlane_b32 s30, v42, 0 +; GFX9-NEXT: v_readlane_b32 s31, v42, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v42, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -8951,24 +8975,24 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v42, s34, 2 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v40, v0 ; GFX10-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-NEXT: s_mov_b32 s35, external_i32_func_i32@abs32@hi -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-NEXT: s_mov_b32 s34, external_i32_func_i32@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_mov_b32_e32 v41, v1 -; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: global_store_dword v[40:41], v0, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 -; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v42, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -8988,24 +9012,26 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou ; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v42, s0, 2 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s33 +; GFX11-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v41, v1 :: v_dual_mov_b32 v40, v0 ; GFX11-NEXT: v_mov_b32_e32 v0, 42 -; GFX11-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_i32_func_i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_i32_func_i32@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v42, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: global_store_b32 v[40:41], v0, off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: scratch_load_b32 v41, off, s33 ; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:4 -; GFX11-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-NEXT: v_readlane_b32 s30, v42, 0 +; GFX11-NEXT: v_readlane_b32 s31, v42, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v42, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -9025,24 +9051,24 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, v0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_i32_func_i32@abs32@hi -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_i32_func_i32@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, v1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: global_store_dword v[40:41], v0, off ; GFX10-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 ; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -9067,19 +9093,19 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_ubyte v0, v2, s[34:35] ; GFX9-NEXT: global_load_dword v1, v2, s[34:35] offset:4 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_struct_i8_i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_struct_i8_i32@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -9099,20 +9125,21 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_ubyte v0, v2, s[34:35] ; GFX10-NEXT: global_load_dword v1, v2, s[34:35] offset:4 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_struct_i8_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_struct_i8_i32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -9132,21 +9159,21 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v1, s[0:1] ; GFX11-TRUE16-NEXT: global_load_b32 v1, v1, s[0:1] offset:4 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_struct_i8_i32@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_struct_i8_i32@abs32@lo -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -9165,21 +9192,21 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: global_load_u8 v0, v1, s[0:1] ; GFX11-FAKE16-NEXT: global_load_b32 v1, v1, s[0:1] offset:4 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_struct_i8_i32@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_struct_i8_i32@abs32@lo -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -9199,20 +9226,21 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v2, s[0:1] ; GFX10-SCRATCH-NEXT: global_load_dword v1, v2, s[0:1] offset:4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_struct_i8_i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_struct_i8_i32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -9237,20 +9265,20 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_mov_b32_e32 v0, 3 ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: v_mov_b32_e32 v0, 3 ; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s33 ; GFX9-NEXT: v_mov_b32_e32 v0, 8 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_byval_struct_i8_i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_byval_struct_i8_i32@abs32@lo ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -9270,19 +9298,19 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-NEXT: v_mov_b32_e32 v1, 8 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_byval_struct_i8_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_byval_struct_i8_i32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s33 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -9302,21 +9330,20 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 { ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 3 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 8 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_byval_struct_i8_i32@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_byval_struct_i8_i32@abs32@lo -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b8 off, v0, s33 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v1, s33 offset:4 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s33 -; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -9335,20 +9362,19 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 { ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_byval_struct_i8_i32@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_byval_struct_i8_i32@abs32@lo -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b8 off, v0, s33 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v1, s33 offset:4 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s33 -; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 @@ -9368,19 +9394,19 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_byval_struct_i8_i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_byval_struct_i8_i32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s33 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v1, s33 offset:4 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s33 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -9408,24 +9434,24 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x800 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 3 ; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s33 ; GFX9-NEXT: v_mov_b32_e32 v0, 8 -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo ; GFX9-NEXT: v_add_u32_e32 v0, 8, v0 ; GFX9-NEXT: v_lshrrev_b32_e64 v1, 6, s33 -; GFX9-NEXT: s_addk_i32 s32, 0x800 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX9-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8 ; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:12 -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_waitcnt vmcnt(0) @@ -9449,25 +9475,25 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x400 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-NEXT: v_mov_b32_e32 v1, 8 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s33 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_lshrrev_b32_e64 v1, 5, s33 -; GFX10-NEXT: s_addk_i32 s32, 0x400 ; GFX10-NEXT: v_add_nc_u32_e32 v0, 8, v0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8 ; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:12 -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -9492,24 +9518,24 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:16 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 32 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 3 ; GFX11-TRUE16-NEXT: s_add_i32 s2, s33, 8 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi +; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b8 off, v0, s33 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v1, s33 offset:4 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi -; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v0, off, s33 offset:8 ; GFX11-TRUE16-NEXT: scratch_load_b32 v1, off, s33 offset:12 -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33 ; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) @@ -9533,23 +9559,23 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:16 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 32 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8 ; GFX11-FAKE16-NEXT: s_add_i32 s2, s33, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi +; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b8 off, v0, s33 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v1, s33 offset:4 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi -; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_load_u8 v0, off, s33 offset:8 ; GFX11-FAKE16-NEXT: scratch_load_b32 v1, off, s33 offset:12 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33 ; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) @@ -9574,24 +9600,24 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32 ; GFX10-SCRATCH-NEXT: s_add_i32 s2, s33, 8 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s33 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v1, s33 offset:4 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s33 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: scratch_load_ubyte v0, off, s33 offset:8 ; GFX10-SCRATCH-NEXT: scratch_load_dword v1, off, s33 offset:12 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) @@ -9633,11 +9659,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_dwordx4 v[0:3], v0, s[34:35] ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16i8@abs32@hi @@ -9662,8 +9688,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX9-NEXT: v_mov_b32_e32 v2, v17 ; GFX9-NEXT: v_mov_b32_e32 v3, v18 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -9683,11 +9709,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 -; GFX10-NEXT: v_mov_b32_e32 v0, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: global_load_dwordx4 v[0:3], v0, s[34:35] ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 @@ -9713,8 +9739,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX10-NEXT: v_mov_b32_e32 v2, v17 ; GFX10-NEXT: v_mov_b32_e32 v3, v18 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -9734,11 +9760,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16i8@abs32@hi @@ -9761,8 +9787,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX11-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v1, v16 ; GFX11-NEXT: v_dual_mov_b32 v2, v17 :: v_dual_mov_b32 v3, v18 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -9782,11 +9808,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 -; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 +; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 @@ -9812,8 +9838,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, v17 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, v18 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -9838,49 +9864,49 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: s_addk_i32 s32, 0x800 +; GFX9-NEXT: v_writelane_b32 v40, s34, 0 +; GFX9-NEXT: v_writelane_b32 v40, s35, 1 +; GFX9-NEXT: v_writelane_b32 v40, s36, 2 +; GFX9-NEXT: v_writelane_b32 v40, s37, 3 +; GFX9-NEXT: v_writelane_b32 v40, s38, 4 +; GFX9-NEXT: v_writelane_b32 v40, s39, 5 +; GFX9-NEXT: v_writelane_b32 v40, s48, 6 +; GFX9-NEXT: v_writelane_b32 v40, s49, 7 +; GFX9-NEXT: v_writelane_b32 v40, s50, 8 +; GFX9-NEXT: v_writelane_b32 v40, s51, 9 +; GFX9-NEXT: v_writelane_b32 v40, s52, 10 +; GFX9-NEXT: v_writelane_b32 v40, s53, 11 +; GFX9-NEXT: v_writelane_b32 v40, s54, 12 +; GFX9-NEXT: v_writelane_b32 v40, s55, 13 +; GFX9-NEXT: v_writelane_b32 v40, s30, 14 +; GFX9-NEXT: v_writelane_b32 v40, s31, 15 ; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:16 ; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:20 ; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s33 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: v_writelane_b32 v40, s35, 3 -; GFX9-NEXT: v_writelane_b32 v40, s36, 4 -; GFX9-NEXT: v_writelane_b32 v40, s37, 5 -; GFX9-NEXT: v_writelane_b32 v40, s38, 6 -; GFX9-NEXT: v_writelane_b32 v40, s39, 7 -; GFX9-NEXT: v_writelane_b32 v40, s48, 8 -; GFX9-NEXT: v_writelane_b32 v40, s49, 9 -; GFX9-NEXT: v_writelane_b32 v40, s50, 10 -; GFX9-NEXT: v_writelane_b32 v40, s51, 11 -; GFX9-NEXT: v_writelane_b32 v40, s52, 12 -; GFX9-NEXT: v_writelane_b32 v40, s53, 13 -; GFX9-NEXT: s_addk_i32 s32, 0x800 -; GFX9-NEXT: v_writelane_b32 v40, s54, 14 ; GFX9-NEXT: s_mov_b32 s5, byval_align16_f64_arg@abs32@hi ; GFX9-NEXT: s_mov_b32 s4, byval_align16_f64_arg@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s55, 15 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX9-NEXT: v_readlane_b32 s55, v40, 15 -; GFX9-NEXT: v_readlane_b32 s54, v40, 14 -; GFX9-NEXT: v_readlane_b32 s53, v40, 13 -; GFX9-NEXT: v_readlane_b32 s52, v40, 12 -; GFX9-NEXT: v_readlane_b32 s51, v40, 11 -; GFX9-NEXT: v_readlane_b32 s50, v40, 10 -; GFX9-NEXT: v_readlane_b32 s49, v40, 9 -; GFX9-NEXT: v_readlane_b32 s48, v40, 8 -; GFX9-NEXT: v_readlane_b32 s39, v40, 7 -; GFX9-NEXT: v_readlane_b32 s38, v40, 6 -; GFX9-NEXT: v_readlane_b32 s37, v40, 5 -; GFX9-NEXT: v_readlane_b32 s36, v40, 4 -; GFX9-NEXT: v_readlane_b32 s35, v40, 3 -; GFX9-NEXT: v_readlane_b32 s34, v40, 2 -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 -; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s30, v40, 14 +; GFX9-NEXT: v_readlane_b32 s31, v40, 15 +; GFX9-NEXT: v_readlane_b32 s55, v40, 13 +; GFX9-NEXT: v_readlane_b32 s54, v40, 12 +; GFX9-NEXT: v_readlane_b32 s53, v40, 11 +; GFX9-NEXT: v_readlane_b32 s52, v40, 10 +; GFX9-NEXT: v_readlane_b32 s51, v40, 9 +; GFX9-NEXT: v_readlane_b32 s50, v40, 8 +; GFX9-NEXT: v_readlane_b32 s49, v40, 7 +; GFX9-NEXT: v_readlane_b32 s48, v40, 6 +; GFX9-NEXT: v_readlane_b32 s39, v40, 5 +; GFX9-NEXT: v_readlane_b32 s38, v40, 4 +; GFX9-NEXT: v_readlane_b32 s37, v40, 3 +; GFX9-NEXT: v_readlane_b32 s36, v40, 2 +; GFX9-NEXT: v_readlane_b32 s35, v40, 1 +; GFX9-NEXT: v_readlane_b32 s34, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload @@ -9898,50 +9924,50 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s4 +; GFX10-NEXT: s_addk_i32 s32, 0x400 +; GFX10-NEXT: v_writelane_b32 v40, s34, 0 +; GFX10-NEXT: v_writelane_b32 v40, s35, 1 +; GFX10-NEXT: v_writelane_b32 v40, s36, 2 +; GFX10-NEXT: v_writelane_b32 v40, s37, 3 +; GFX10-NEXT: v_writelane_b32 v40, s38, 4 +; GFX10-NEXT: v_writelane_b32 v40, s39, 5 +; GFX10-NEXT: v_writelane_b32 v40, s48, 6 +; GFX10-NEXT: v_writelane_b32 v40, s49, 7 +; GFX10-NEXT: v_writelane_b32 v40, s50, 8 +; GFX10-NEXT: v_writelane_b32 v40, s51, 9 +; GFX10-NEXT: v_writelane_b32 v40, s52, 10 +; GFX10-NEXT: v_writelane_b32 v40, s53, 11 +; GFX10-NEXT: v_writelane_b32 v40, s54, 12 +; GFX10-NEXT: v_writelane_b32 v40, s55, 13 +; GFX10-NEXT: v_writelane_b32 v40, s30, 14 +; GFX10-NEXT: v_writelane_b32 v40, s31, 15 ; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:16 ; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:20 ; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s33 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: s_addk_i32 s32, 0x400 ; GFX10-NEXT: s_mov_b32 s5, byval_align16_f64_arg@abs32@hi ; GFX10-NEXT: s_mov_b32 s4, byval_align16_f64_arg@abs32@lo ; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s35, 3 -; GFX10-NEXT: v_writelane_b32 v40, s36, 4 -; GFX10-NEXT: v_writelane_b32 v40, s37, 5 -; GFX10-NEXT: v_writelane_b32 v40, s38, 6 -; GFX10-NEXT: v_writelane_b32 v40, s39, 7 -; GFX10-NEXT: v_writelane_b32 v40, s48, 8 -; GFX10-NEXT: v_writelane_b32 v40, s49, 9 -; GFX10-NEXT: v_writelane_b32 v40, s50, 10 -; GFX10-NEXT: v_writelane_b32 v40, s51, 11 -; GFX10-NEXT: v_writelane_b32 v40, s52, 12 -; GFX10-NEXT: v_writelane_b32 v40, s53, 13 -; GFX10-NEXT: v_writelane_b32 v40, s54, 14 -; GFX10-NEXT: v_writelane_b32 v40, s55, 15 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX10-NEXT: v_readlane_b32 s55, v40, 15 -; GFX10-NEXT: v_readlane_b32 s54, v40, 14 -; GFX10-NEXT: v_readlane_b32 s53, v40, 13 -; GFX10-NEXT: v_readlane_b32 s52, v40, 12 -; GFX10-NEXT: v_readlane_b32 s51, v40, 11 -; GFX10-NEXT: v_readlane_b32 s50, v40, 10 -; GFX10-NEXT: v_readlane_b32 s49, v40, 9 -; GFX10-NEXT: v_readlane_b32 s48, v40, 8 -; GFX10-NEXT: v_readlane_b32 s39, v40, 7 -; GFX10-NEXT: v_readlane_b32 s38, v40, 6 -; GFX10-NEXT: v_readlane_b32 s37, v40, 5 -; GFX10-NEXT: v_readlane_b32 s36, v40, 4 -; GFX10-NEXT: v_readlane_b32 s35, v40, 3 -; GFX10-NEXT: v_readlane_b32 s34, v40, 2 -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 -; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s30, v40, 14 +; GFX10-NEXT: v_readlane_b32 s31, v40, 15 +; GFX10-NEXT: v_readlane_b32 s55, v40, 13 +; GFX10-NEXT: v_readlane_b32 s54, v40, 12 +; GFX10-NEXT: v_readlane_b32 s53, v40, 11 +; GFX10-NEXT: v_readlane_b32 s52, v40, 10 +; GFX10-NEXT: v_readlane_b32 s51, v40, 9 +; GFX10-NEXT: v_readlane_b32 s50, v40, 8 +; GFX10-NEXT: v_readlane_b32 s49, v40, 7 +; GFX10-NEXT: v_readlane_b32 s48, v40, 6 +; GFX10-NEXT: v_readlane_b32 s39, v40, 5 +; GFX10-NEXT: v_readlane_b32 s38, v40, 4 +; GFX10-NEXT: v_readlane_b32 s37, v40, 3 +; GFX10-NEXT: v_readlane_b32 s36, v40, 2 +; GFX10-NEXT: v_readlane_b32 s35, v40, 1 +; GFX10-NEXT: v_readlane_b32 s34, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_or_saveexec_b32 s4, -1 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload @@ -9959,47 +9985,47 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 { ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:24 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 +; GFX11-NEXT: s_add_i32 s32, s32, 32 +; GFX11-NEXT: v_writelane_b32 v40, s34, 0 +; GFX11-NEXT: v_writelane_b32 v40, s35, 1 +; GFX11-NEXT: v_writelane_b32 v40, s36, 2 +; GFX11-NEXT: v_writelane_b32 v40, s37, 3 +; GFX11-NEXT: v_writelane_b32 v40, s38, 4 +; GFX11-NEXT: v_writelane_b32 v40, s39, 5 +; GFX11-NEXT: v_writelane_b32 v40, s48, 6 +; GFX11-NEXT: v_writelane_b32 v40, s49, 7 +; GFX11-NEXT: v_writelane_b32 v40, s50, 8 +; GFX11-NEXT: v_writelane_b32 v40, s51, 9 +; GFX11-NEXT: v_writelane_b32 v40, s52, 10 +; GFX11-NEXT: v_writelane_b32 v40, s53, 11 +; GFX11-NEXT: v_writelane_b32 v40, s54, 12 +; GFX11-NEXT: v_writelane_b32 v40, s55, 13 +; GFX11-NEXT: v_writelane_b32 v40, s30, 14 +; GFX11-NEXT: v_writelane_b32 v40, s31, 15 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: scratch_load_b64 v[32:33], off, s33 offset:16 ; GFX11-NEXT: scratch_load_b32 v31, off, s33 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: s_add_i32 s32, s32, 32 ; GFX11-NEXT: s_mov_b32 s1, byval_align16_f64_arg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, byval_align16_f64_arg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 -; GFX11-NEXT: v_writelane_b32 v40, s34, 2 -; GFX11-NEXT: v_writelane_b32 v40, s35, 3 -; GFX11-NEXT: v_writelane_b32 v40, s36, 4 -; GFX11-NEXT: v_writelane_b32 v40, s37, 5 -; GFX11-NEXT: v_writelane_b32 v40, s38, 6 -; GFX11-NEXT: v_writelane_b32 v40, s39, 7 -; GFX11-NEXT: v_writelane_b32 v40, s48, 8 -; GFX11-NEXT: v_writelane_b32 v40, s49, 9 -; GFX11-NEXT: v_writelane_b32 v40, s50, 10 -; GFX11-NEXT: v_writelane_b32 v40, s51, 11 -; GFX11-NEXT: v_writelane_b32 v40, s52, 12 -; GFX11-NEXT: v_writelane_b32 v40, s53, 13 -; GFX11-NEXT: v_writelane_b32 v40, s54, 14 -; GFX11-NEXT: v_writelane_b32 v40, s55, 15 ; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: scratch_store_b64 off, v[32:33], s32 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s55, v40, 15 -; GFX11-NEXT: v_readlane_b32 s54, v40, 14 -; GFX11-NEXT: v_readlane_b32 s53, v40, 13 -; GFX11-NEXT: v_readlane_b32 s52, v40, 12 -; GFX11-NEXT: v_readlane_b32 s51, v40, 11 -; GFX11-NEXT: v_readlane_b32 s50, v40, 10 -; GFX11-NEXT: v_readlane_b32 s49, v40, 9 -; GFX11-NEXT: v_readlane_b32 s48, v40, 8 -; GFX11-NEXT: v_readlane_b32 s39, v40, 7 -; GFX11-NEXT: v_readlane_b32 s38, v40, 6 -; GFX11-NEXT: v_readlane_b32 s37, v40, 5 -; GFX11-NEXT: v_readlane_b32 s36, v40, 4 -; GFX11-NEXT: v_readlane_b32 s35, v40, 3 -; GFX11-NEXT: v_readlane_b32 s34, v40, 2 -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 -; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s30, v40, 14 +; GFX11-NEXT: v_readlane_b32 s31, v40, 15 +; GFX11-NEXT: v_readlane_b32 s55, v40, 13 +; GFX11-NEXT: v_readlane_b32 s54, v40, 12 +; GFX11-NEXT: v_readlane_b32 s53, v40, 11 +; GFX11-NEXT: v_readlane_b32 s52, v40, 10 +; GFX11-NEXT: v_readlane_b32 s51, v40, 9 +; GFX11-NEXT: v_readlane_b32 s50, v40, 8 +; GFX11-NEXT: v_readlane_b32 s49, v40, 7 +; GFX11-NEXT: v_readlane_b32 s48, v40, 6 +; GFX11-NEXT: v_readlane_b32 s39, v40, 5 +; GFX11-NEXT: v_readlane_b32 s38, v40, 4 +; GFX11-NEXT: v_readlane_b32 s37, v40, 3 +; GFX11-NEXT: v_readlane_b32 s36, v40, 2 +; GFX11-NEXT: v_readlane_b32 s35, v40, 1 +; GFX11-NEXT: v_readlane_b32 s34, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:24 ; 4-byte Folded Reload @@ -10017,47 +10043,47 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:24 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s34, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s35, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s36, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s37, 3 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s38, 4 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s39, 5 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s48, 6 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s49, 7 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s50, 8 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s51, 9 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s52, 10 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s53, 11 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s54, 12 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s55, 13 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 14 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 15 ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33 offset:16 ; GFX10-SCRATCH-NEXT: scratch_load_dword v31, off, s33 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, byval_align16_f64_arg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, byval_align16_f64_arg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s35, 3 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s36, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s37, 5 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s38, 6 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s39, 7 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s48, 8 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s49, 9 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s50, 10 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s51, 11 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s52, 12 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s53, 13 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s54, 14 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s55, 15 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1) ; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[32:33], s32 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s55, v40, 15 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s54, v40, 14 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s53, v40, 13 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s52, v40, 12 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s51, v40, 11 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s50, v40, 10 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s49, v40, 9 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s48, v40, 8 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s39, v40, 7 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s38, v40, 6 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s37, v40, 5 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s36, v40, 4 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s35, v40, 3 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s34, v40, 2 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 -; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 14 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 15 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s55, v40, 13 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s54, v40, 12 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s53, v40, 11 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s52, v40, 10 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s51, v40, 9 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s50, v40, 8 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s49, v40, 7 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s48, v40, 6 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s39, v40, 5 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s38, v40, 4 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s37, v40, 3 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s36, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s35, v40, 1 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s34, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s0, -1 ; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:24 ; 4-byte Folded Reload @@ -10083,16 +10109,16 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 1 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i1_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i1_inreg@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -10112,16 +10138,16 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_mov_b32_e32 v0, 1 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -10141,17 +10167,16 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_mov_b32_e32 v0, 1 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: v_mov_b32_e32 v0, 1 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: scratch_store_b8 off, v0, s32 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -10171,16 +10196,16 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -10204,16 +10229,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_inreg@abs32@lo ; GFX9-NEXT: s_movk_i32 s4, 0x7b -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s30, v40, 1 +; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -10234,16 +10259,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_inreg@abs32@lo +; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -10264,17 +10289,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_i8_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_i8_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_i8_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_i8_inreg@abs32@lo +; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s30, v40, 1 +; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -10295,16 +10319,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3 @@ -10329,16 +10353,16 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_inreg@abs32@lo ; GFX9-NEXT: s_movk_i32 s4, 0x7b -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s30, v40, 1 +; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -10359,16 +10383,16 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_inreg@abs32@lo +; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -10389,17 +10413,16 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_i16_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_i16_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_i16_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_i16_inreg@abs32@lo +; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s30, v40, 1 +; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -10420,16 +10443,16 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3 @@ -10454,16 +10477,16 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 42 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s30, v40, 1 +; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -10484,16 +10507,16 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_i32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_i32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 42 ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_i32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_i32_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 42 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -10514,17 +10537,16 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_i32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_i32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 42 ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_i32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_i32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 42 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s30, v40, 1 +; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -10545,16 +10567,16 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 42 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i32_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 42 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3 @@ -10579,18 +10601,18 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i64_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i64_inreg@abs32@lo ; GFX9-NEXT: s_movk_i32 s4, 0x7b ; GFX9-NEXT: s_mov_b32 s5, 0 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -10612,18 +10634,18 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_i64_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_i64_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_i64_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_i64_inreg@abs32@lo +; GFX10-NEXT: s_movk_i32 s4, 0x7b +; GFX10-NEXT: s_mov_b32 s5, 0 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -10645,19 +10667,18 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_i64_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_i64_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 0 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 ; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_i64_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_i64_inreg@abs32@lo +; GFX11-NEXT: s_movk_i32 s4, 0x7b +; GFX11-NEXT: s_mov_b32 s5, 0 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -10679,18 +10700,18 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i64_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i64_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i64_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i64_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -10716,20 +10737,20 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 6 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 -; GFX9-NEXT: s_mov_b64 s[34:35], 0 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 -; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 4 +; GFX9-NEXT: v_writelane_b32 v40, s31, 5 +; GFX9-NEXT: s_mov_b64 s[34:35], 0 +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 5 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s30, v40, 4 +; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s7, v40, 3 ; GFX9-NEXT: v_readlane_b32 s6, v40, 2 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 @@ -10753,20 +10774,20 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: s_mov_b64 s[34:35], 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 +; GFX10-NEXT: v_writelane_b32 v40, s30, 4 +; GFX10-NEXT: v_writelane_b32 v40, s31, 5 +; GFX10-NEXT: s_mov_b64 s[34:35], 0 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 4 -; GFX10-NEXT: v_writelane_b32 v40, s31, 5 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 @@ -10790,21 +10811,21 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: s_mov_b64 s[0:1], 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 +; GFX11-NEXT: v_writelane_b32 v40, s30, 4 +; GFX11-NEXT: v_writelane_b32 v40, s31, 5 +; GFX11-NEXT: s_mov_b64 s[0:1], 0 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 4 -; GFX11-NEXT: v_writelane_b32 v40, s31, 5 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s30, v40, 4 +; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s7, v40, 3 ; GFX11-NEXT: v_readlane_b32 s6, v40, 2 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 @@ -10828,20 +10849,20 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5 +; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0 ; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 @@ -10870,22 +10891,22 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 6 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 ; GFX9-NEXT: v_writelane_b32 v40, s30, 4 +; GFX9-NEXT: v_writelane_b32 v40, s31, 5 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 1 ; GFX9-NEXT: s_mov_b32 s5, 2 ; GFX9-NEXT: s_mov_b32 s6, 3 ; GFX9-NEXT: s_mov_b32 s7, 4 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 5 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s30, v40, 4 +; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s7, v40, 3 ; GFX9-NEXT: v_readlane_b32 s6, v40, 2 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 @@ -10909,22 +10930,22 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 2 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-NEXT: s_mov_b32 s6, 3 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-NEXT: s_mov_b32 s7, 4 ; GFX10-NEXT: v_writelane_b32 v40, s30, 4 ; GFX10-NEXT: v_writelane_b32 v40, s31, 5 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 1 +; GFX10-NEXT: s_mov_b32 s5, 2 +; GFX10-NEXT: s_mov_b32 s6, 3 +; GFX10-NEXT: s_mov_b32 s7, 4 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 @@ -10948,23 +10969,22 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 -; GFX11-NEXT: s_mov_b32 s6, 3 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 -; GFX11-NEXT: s_mov_b32 s7, 4 ; GFX11-NEXT: v_writelane_b32 v40, s30, 4 ; GFX11-NEXT: v_writelane_b32 v40, s31, 5 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 1 +; GFX11-NEXT: s_mov_b32 s5, 2 +; GFX11-NEXT: s_mov_b32 s6, 3 +; GFX11-NEXT: s_mov_b32 s7, 4 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s30, v40, 4 +; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s7, v40, 3 ; GFX11-NEXT: v_readlane_b32 s6, v40, 2 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 @@ -10988,22 +11008,22 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 +; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 @@ -11031,24 +11051,24 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 8 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 -; GFX9-NEXT: s_mov_b64 s[34:35], 0 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 -; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s8, 4 ; GFX9-NEXT: v_writelane_b32 v40, s9, 5 ; GFX9-NEXT: v_writelane_b32 v40, s30, 6 +; GFX9-NEXT: v_writelane_b32 v40, s31, 7 +; GFX9-NEXT: s_mov_b64 s[34:35], 0 +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i64_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i64_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s8, 1 ; GFX9-NEXT: s_mov_b32 s9, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 7 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 7 ; GFX9-NEXT: v_readlane_b32 s30, v40, 6 +; GFX9-NEXT: v_readlane_b32 s31, v40, 7 ; GFX9-NEXT: v_readlane_b32 s9, v40, 5 ; GFX9-NEXT: v_readlane_b32 s8, v40, 4 ; GFX9-NEXT: v_readlane_b32 s7, v40, 3 @@ -11074,24 +11094,24 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 8 -; GFX10-NEXT: s_mov_b64 s[34:35], 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i64_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i64_inreg@abs32@lo ; GFX10-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-NEXT: s_mov_b32 s8, 1 ; GFX10-NEXT: v_writelane_b32 v40, s9, 5 -; GFX10-NEXT: s_mov_b32 s9, 2 ; GFX10-NEXT: v_writelane_b32 v40, s30, 6 ; GFX10-NEXT: v_writelane_b32 v40, s31, 7 +; GFX10-NEXT: s_mov_b64 s[34:35], 0 +; GFX10-NEXT: s_mov_b32 s8, 1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i64_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i64_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s9, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 7 ; GFX10-NEXT: v_readlane_b32 s30, v40, 6 +; GFX10-NEXT: v_readlane_b32 s31, v40, 7 ; GFX10-NEXT: v_readlane_b32 s9, v40, 5 ; GFX10-NEXT: v_readlane_b32 s8, v40, 4 ; GFX10-NEXT: v_readlane_b32 s7, v40, 3 @@ -11117,25 +11137,24 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 8 -; GFX11-NEXT: s_mov_b64 s[0:1], 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 -; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i64_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i64_inreg@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s8, 4 -; GFX11-NEXT: s_mov_b32 s8, 1 ; GFX11-NEXT: v_writelane_b32 v40, s9, 5 -; GFX11-NEXT: s_mov_b32 s9, 2 ; GFX11-NEXT: v_writelane_b32 v40, s30, 6 ; GFX11-NEXT: v_writelane_b32 v40, s31, 7 +; GFX11-NEXT: s_mov_b64 s[0:1], 0 +; GFX11-NEXT: s_mov_b32 s8, 1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i64_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i64_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s9, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 7 ; GFX11-NEXT: v_readlane_b32 s30, v40, 6 +; GFX11-NEXT: v_readlane_b32 s31, v40, 7 ; GFX11-NEXT: v_readlane_b32 s9, v40, 5 ; GFX11-NEXT: v_readlane_b32 s8, v40, 4 ; GFX11-NEXT: v_readlane_b32 s7, v40, 3 @@ -11161,24 +11180,24 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 8 -; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i64_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i64_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s9, 5 -; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 6 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 7 +; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 1 +; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i64_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i64_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 7 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 6 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 7 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s9, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s8, v40, 4 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3 @@ -11211,28 +11230,28 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 10 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 -; GFX9-NEXT: s_mov_b64 s[34:35], 0 ; GFX9-NEXT: v_writelane_b32 v40, s8, 4 -; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s9, 5 ; GFX9-NEXT: v_writelane_b32 v40, s10, 6 ; GFX9-NEXT: v_writelane_b32 v40, s11, 7 ; GFX9-NEXT: v_writelane_b32 v40, s30, 8 +; GFX9-NEXT: v_writelane_b32 v40, s31, 9 +; GFX9-NEXT: s_mov_b64 s[34:35], 0 +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i64_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i64_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s8, 1 ; GFX9-NEXT: s_mov_b32 s9, 2 ; GFX9-NEXT: s_mov_b32 s10, 3 ; GFX9-NEXT: s_mov_b32 s11, 4 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 9 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 9 ; GFX9-NEXT: v_readlane_b32 s30, v40, 8 +; GFX9-NEXT: v_readlane_b32 s31, v40, 9 ; GFX9-NEXT: v_readlane_b32 s11, v40, 7 ; GFX9-NEXT: v_readlane_b32 s10, v40, 6 ; GFX9-NEXT: v_readlane_b32 s9, v40, 5 @@ -11260,28 +11279,28 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 10 -; GFX10-NEXT: s_mov_b64 s[34:35], 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i64_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i64_inreg@abs32@lo ; GFX10-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-NEXT: s_mov_b32 s8, 1 ; GFX10-NEXT: v_writelane_b32 v40, s9, 5 -; GFX10-NEXT: s_mov_b32 s9, 2 ; GFX10-NEXT: v_writelane_b32 v40, s10, 6 -; GFX10-NEXT: s_mov_b32 s10, 3 ; GFX10-NEXT: v_writelane_b32 v40, s11, 7 -; GFX10-NEXT: s_mov_b32 s11, 4 ; GFX10-NEXT: v_writelane_b32 v40, s30, 8 ; GFX10-NEXT: v_writelane_b32 v40, s31, 9 +; GFX10-NEXT: s_mov_b64 s[34:35], 0 +; GFX10-NEXT: s_mov_b32 s8, 1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i64_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i64_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s9, 2 +; GFX10-NEXT: s_mov_b32 s10, 3 +; GFX10-NEXT: s_mov_b32 s11, 4 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-NEXT: v_readlane_b32 s30, v40, 8 +; GFX10-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-NEXT: v_readlane_b32 s11, v40, 7 ; GFX10-NEXT: v_readlane_b32 s10, v40, 6 ; GFX10-NEXT: v_readlane_b32 s9, v40, 5 @@ -11309,29 +11328,28 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 10 -; GFX11-NEXT: s_mov_b64 s[0:1], 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 -; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i64_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i64_inreg@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s8, 4 -; GFX11-NEXT: s_mov_b32 s8, 1 ; GFX11-NEXT: v_writelane_b32 v40, s9, 5 -; GFX11-NEXT: s_mov_b32 s9, 2 ; GFX11-NEXT: v_writelane_b32 v40, s10, 6 -; GFX11-NEXT: s_mov_b32 s10, 3 ; GFX11-NEXT: v_writelane_b32 v40, s11, 7 -; GFX11-NEXT: s_mov_b32 s11, 4 ; GFX11-NEXT: v_writelane_b32 v40, s30, 8 ; GFX11-NEXT: v_writelane_b32 v40, s31, 9 +; GFX11-NEXT: s_mov_b64 s[0:1], 0 +; GFX11-NEXT: s_mov_b32 s8, 1 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i64_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i64_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s9, 2 +; GFX11-NEXT: s_mov_b32 s10, 3 +; GFX11-NEXT: s_mov_b32 s11, 4 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 9 ; GFX11-NEXT: v_readlane_b32 s30, v40, 8 +; GFX11-NEXT: v_readlane_b32 s31, v40, 9 ; GFX11-NEXT: v_readlane_b32 s11, v40, 7 ; GFX11-NEXT: v_readlane_b32 s10, v40, 6 ; GFX11-NEXT: v_readlane_b32 s9, v40, 5 @@ -11359,28 +11377,28 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10 -; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i64_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i64_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s9, 5 -; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s10, 6 -; GFX10-SCRATCH-NEXT: s_mov_b32 s10, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s11, 7 -; GFX10-SCRATCH-NEXT: s_mov_b32 s11, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9 +; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 1 +; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i64_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i64_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 2 +; GFX10-SCRATCH-NEXT: s_mov_b32 s10, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s11, 4 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 8 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s11, v40, 7 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s10, v40, 6 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s9, v40, 5 @@ -11414,16 +11432,16 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_f16_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_f16_inreg@abs32@lo ; GFX9-NEXT: s_movk_i32 s4, 0x4400 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s30, v40, 1 +; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -11444,16 +11462,16 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_f16_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_f16_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_movk_i32 s4, 0x4400 ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_f16_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_f16_inreg@abs32@lo +; GFX10-NEXT: s_movk_i32 s4, 0x4400 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -11474,17 +11492,16 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_f16_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_f16_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_movk_i32 s4, 0x4400 ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_f16_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_f16_inreg@abs32@lo +; GFX11-NEXT: s_movk_i32 s4, 0x4400 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s30, v40, 1 +; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -11505,16 +11522,16 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f16_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f16_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x4400 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f16_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f16_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x4400 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3 @@ -11539,16 +11556,16 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_f32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_f32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 4.0 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s30, v40, 1 +; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -11569,16 +11586,16 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_f32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_f32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 4.0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_f32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_f32_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 4.0 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -11599,17 +11616,16 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_f32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_f32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 4.0 ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_f32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_f32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 4.0 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s30, v40, 1 +; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -11630,16 +11646,16 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 4.0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3 @@ -11664,18 +11680,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 1.0 ; GFX9-NEXT: s_mov_b32 s5, 2.0 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -11697,18 +11713,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 1.0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f32_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 1.0 +; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -11730,19 +11746,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 1.0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 2.0 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 ; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 1.0 +; GFX11-NEXT: s_mov_b32 s5, 2.0 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -11764,18 +11779,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f32_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -11801,20 +11816,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 5 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 3 +; GFX9-NEXT: v_writelane_b32 v40, s31, 4 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 1.0 ; GFX9-NEXT: s_mov_b32 s5, 2.0 ; GFX9-NEXT: s_mov_b32 s6, 4.0 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 4 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 4 ; GFX9-NEXT: v_readlane_b32 s30, v40, 3 +; GFX9-NEXT: v_readlane_b32 s31, v40, 4 ; GFX9-NEXT: v_readlane_b32 s6, v40, 2 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 @@ -11837,20 +11852,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 5 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 1.0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-NEXT: s_mov_b32 s6, 4.0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 3 ; GFX10-NEXT: v_writelane_b32 v40, s31, 4 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f32_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 1.0 +; GFX10-NEXT: s_mov_b32 s5, 2.0 +; GFX10-NEXT: s_mov_b32 s6, 4.0 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 4 ; GFX10-NEXT: v_readlane_b32 s30, v40, 3 +; GFX10-NEXT: v_readlane_b32 s31, v40, 4 ; GFX10-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 @@ -11873,21 +11888,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 5 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 1.0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 2.0 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 -; GFX11-NEXT: s_mov_b32 s6, 4.0 ; GFX11-NEXT: v_writelane_b32 v40, s30, 3 ; GFX11-NEXT: v_writelane_b32 v40, s31, 4 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 1.0 +; GFX11-NEXT: s_mov_b32 s5, 2.0 +; GFX11-NEXT: s_mov_b32 s6, 4.0 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 4 ; GFX11-NEXT: v_readlane_b32 s30, v40, 3 +; GFX11-NEXT: v_readlane_b32 s31, v40, 4 ; GFX11-NEXT: v_readlane_b32 s6, v40, 2 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 @@ -11910,20 +11924,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 5 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 4.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 4 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f32_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 4.0 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 4 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 3 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 4 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 @@ -11950,12 +11964,14 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 7 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 ; GFX9-NEXT: v_writelane_b32 v40, s8, 4 ; GFX9-NEXT: v_writelane_b32 v40, s30, 5 +; GFX9-NEXT: v_writelane_b32 v40, s31, 6 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5f32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5f32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 1.0 @@ -11963,11 +11979,9 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 { ; GFX9-NEXT: s_mov_b32 s6, 4.0 ; GFX9-NEXT: s_mov_b32 s7, -1.0 ; GFX9-NEXT: s_mov_b32 s8, 0.5 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 6 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 6 ; GFX9-NEXT: v_readlane_b32 s30, v40, 5 +; GFX9-NEXT: v_readlane_b32 s31, v40, 6 ; GFX9-NEXT: v_readlane_b32 s8, v40, 4 ; GFX9-NEXT: v_readlane_b32 s7, v40, 3 ; GFX9-NEXT: v_readlane_b32 s6, v40, 2 @@ -11992,24 +12006,24 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 7 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5f32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5f32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 1.0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-NEXT: s_mov_b32 s6, 4.0 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-NEXT: s_mov_b32 s7, -1.0 ; GFX10-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-NEXT: s_mov_b32 s8, 0.5 ; GFX10-NEXT: v_writelane_b32 v40, s30, 5 ; GFX10-NEXT: v_writelane_b32 v40, s31, 6 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5f32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5f32_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 1.0 +; GFX10-NEXT: s_mov_b32 s5, 2.0 +; GFX10-NEXT: s_mov_b32 s6, 4.0 +; GFX10-NEXT: s_mov_b32 s7, -1.0 +; GFX10-NEXT: s_mov_b32 s8, 0.5 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 6 ; GFX10-NEXT: v_readlane_b32 s30, v40, 5 +; GFX10-NEXT: v_readlane_b32 s31, v40, 6 ; GFX10-NEXT: v_readlane_b32 s8, v40, 4 ; GFX10-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-NEXT: v_readlane_b32 s6, v40, 2 @@ -12034,25 +12048,24 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 7 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5f32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 1.0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 2.0 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 -; GFX11-NEXT: s_mov_b32 s6, 4.0 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 -; GFX11-NEXT: s_mov_b32 s7, -1.0 ; GFX11-NEXT: v_writelane_b32 v40, s8, 4 -; GFX11-NEXT: s_mov_b32 s8, 0.5 ; GFX11-NEXT: v_writelane_b32 v40, s30, 5 ; GFX11-NEXT: v_writelane_b32 v40, s31, 6 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5f32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 1.0 +; GFX11-NEXT: s_mov_b32 s5, 2.0 +; GFX11-NEXT: s_mov_b32 s6, 4.0 +; GFX11-NEXT: s_mov_b32 s7, -1.0 +; GFX11-NEXT: s_mov_b32 s8, 0.5 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 6 ; GFX11-NEXT: v_readlane_b32 s30, v40, 5 +; GFX11-NEXT: v_readlane_b32 s31, v40, 6 ; GFX11-NEXT: v_readlane_b32 s8, v40, 4 ; GFX11-NEXT: v_readlane_b32 s7, v40, 3 ; GFX11-NEXT: v_readlane_b32 s6, v40, 2 @@ -12077,24 +12090,24 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 7 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5f32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 4.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s7, -1.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 0.5 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 5 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 6 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5f32_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 4.0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s7, -1.0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 0.5 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 6 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 5 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 6 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s8, v40, 4 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2 @@ -12123,18 +12136,18 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_f64_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_f64_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-NEXT: s_mov_b32 s5, 0x40100000 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -12156,18 +12169,18 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_f64_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_f64_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 0x40100000 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_f64_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_f64_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: s_mov_b32 s5, 0x40100000 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -12189,19 +12202,18 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_f64_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_f64_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 0x40100000 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 ; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_f64_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_f64_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40100000 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -12223,18 +12235,18 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f64_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f64_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0x40100000 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f64_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f64_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0x40100000 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -12260,22 +12272,22 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 6 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 ; GFX9-NEXT: v_writelane_b32 v40, s30, 4 +; GFX9-NEXT: v_writelane_b32 v40, s31, 5 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f64_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f64_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-NEXT: s_mov_b32 s5, 2.0 ; GFX9-NEXT: s_mov_b32 s6, 0 ; GFX9-NEXT: s_mov_b32 s7, 0x40100000 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 5 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s30, v40, 4 +; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s7, v40, 3 ; GFX9-NEXT: v_readlane_b32 s6, v40, 2 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 @@ -12299,22 +12311,22 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f64_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f64_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-NEXT: s_mov_b32 s6, 0 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-NEXT: s_mov_b32 s7, 0x40100000 ; GFX10-NEXT: v_writelane_b32 v40, s30, 4 ; GFX10-NEXT: v_writelane_b32 v40, s31, 5 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f64_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f64_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: s_mov_b32 s5, 2.0 +; GFX10-NEXT: s_mov_b32 s6, 0 +; GFX10-NEXT: s_mov_b32 s7, 0x40100000 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 @@ -12338,23 +12350,22 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f64_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 2.0 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 -; GFX11-NEXT: s_mov_b32 s6, 0 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 -; GFX11-NEXT: s_mov_b32 s7, 0x40100000 ; GFX11-NEXT: v_writelane_b32 v40, s30, 4 ; GFX11-NEXT: v_writelane_b32 v40, s31, 5 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f64_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 2.0 +; GFX11-NEXT: s_mov_b32 s6, 0 +; GFX11-NEXT: s_mov_b32 s7, 0x40100000 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s30, v40, 4 +; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s7, v40, 3 ; GFX11-NEXT: v_readlane_b32 s6, v40, 2 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 @@ -12378,22 +12389,22 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f64_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 0x40100000 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f64_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 0x40100000 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 @@ -12421,6 +12432,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 8 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 @@ -12428,6 +12440,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 { ; GFX9-NEXT: v_writelane_b32 v40, s8, 4 ; GFX9-NEXT: v_writelane_b32 v40, s9, 5 ; GFX9-NEXT: v_writelane_b32 v40, s30, 6 +; GFX9-NEXT: v_writelane_b32 v40, s31, 7 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f64_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f64_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 0 @@ -12436,11 +12449,9 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 { ; GFX9-NEXT: s_mov_b32 s7, 0x40100000 ; GFX9-NEXT: s_mov_b32 s8, 0 ; GFX9-NEXT: s_mov_b32 s9, 0x40200000 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 7 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 7 ; GFX9-NEXT: v_readlane_b32 s30, v40, 6 +; GFX9-NEXT: v_readlane_b32 s31, v40, 7 ; GFX9-NEXT: v_readlane_b32 s9, v40, 5 ; GFX9-NEXT: v_readlane_b32 s8, v40, 4 ; GFX9-NEXT: v_readlane_b32 s7, v40, 3 @@ -12466,26 +12477,26 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 8 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f64_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f64_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-NEXT: s_mov_b32 s6, 0 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-NEXT: s_mov_b32 s7, 0x40100000 ; GFX10-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-NEXT: s_mov_b32 s8, 0 ; GFX10-NEXT: v_writelane_b32 v40, s9, 5 -; GFX10-NEXT: s_mov_b32 s9, 0x40200000 ; GFX10-NEXT: v_writelane_b32 v40, s30, 6 ; GFX10-NEXT: v_writelane_b32 v40, s31, 7 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f64_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f64_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: s_mov_b32 s5, 2.0 +; GFX10-NEXT: s_mov_b32 s6, 0 +; GFX10-NEXT: s_mov_b32 s7, 0x40100000 +; GFX10-NEXT: s_mov_b32 s8, 0 +; GFX10-NEXT: s_mov_b32 s9, 0x40200000 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 7 ; GFX10-NEXT: v_readlane_b32 s30, v40, 6 +; GFX10-NEXT: v_readlane_b32 s31, v40, 7 ; GFX10-NEXT: v_readlane_b32 s9, v40, 5 ; GFX10-NEXT: v_readlane_b32 s8, v40, 4 ; GFX10-NEXT: v_readlane_b32 s7, v40, 3 @@ -12511,27 +12522,26 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 8 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f64_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 +; GFX11-NEXT: v_writelane_b32 v40, s6, 2 +; GFX11-NEXT: v_writelane_b32 v40, s7, 3 +; GFX11-NEXT: v_writelane_b32 v40, s8, 4 +; GFX11-NEXT: v_writelane_b32 v40, s9, 5 +; GFX11-NEXT: v_writelane_b32 v40, s30, 6 +; GFX11-NEXT: v_writelane_b32 v40, s31, 7 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f64_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_mov_b32 s5, 2.0 -; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: s_mov_b32 s6, 0 -; GFX11-NEXT: v_writelane_b32 v40, s7, 3 ; GFX11-NEXT: s_mov_b32 s7, 0x40100000 -; GFX11-NEXT: v_writelane_b32 v40, s8, 4 ; GFX11-NEXT: s_mov_b32 s8, 0 -; GFX11-NEXT: v_writelane_b32 v40, s9, 5 ; GFX11-NEXT: s_mov_b32 s9, 0x40200000 -; GFX11-NEXT: v_writelane_b32 v40, s30, 6 -; GFX11-NEXT: v_writelane_b32 v40, s31, 7 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 7 ; GFX11-NEXT: v_readlane_b32 s30, v40, 6 +; GFX11-NEXT: v_readlane_b32 s31, v40, 7 ; GFX11-NEXT: v_readlane_b32 s9, v40, 5 ; GFX11-NEXT: v_readlane_b32 s8, v40, 4 ; GFX11-NEXT: v_readlane_b32 s7, v40, 3 @@ -12557,26 +12567,26 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 8 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f64_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 0x40100000 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s9, 5 -; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 0x40200000 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 6 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 7 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f64_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 0x40100000 +; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 0x40200000 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 7 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 6 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 7 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s9, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s8, v40, 4 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3 @@ -12606,16 +12616,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 -; GFX9-NEXT: s_load_dword s4, s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 +; GFX9-NEXT: s_load_dword s4, s[34:35], 0x0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i16_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i16_inreg@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s30, v40, 1 +; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -12638,14 +12648,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: v_writelane_b32 v40, s30, 1 +; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_load_dword s4, s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i16_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 1 -; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -12668,15 +12678,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 { ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: v_writelane_b32 v40, s30, 1 +; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i16_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 1 -; GFX11-NEXT: v_writelane_b32 v40, s31, 2 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s30, v40, 1 +; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -12699,14 +12709,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3 @@ -12732,17 +12742,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 -; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -12767,14 +12777,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 { ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 +; GFX10-NEXT: v_writelane_b32 v40, s30, 2 +; GFX10-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 2 -; GFX10-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -12799,15 +12809,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 { ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 +; GFX11-NEXT: v_writelane_b32 v40, s30, 2 +; GFX11-NEXT: v_writelane_b32 v40, s31, 3 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 2 -; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -12832,14 +12842,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -12866,17 +12876,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 -; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -12901,14 +12911,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 { ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 +; GFX10-NEXT: v_writelane_b32 v40, s30, 2 +; GFX10-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 2 -; GFX10-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -12933,15 +12943,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 { ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 +; GFX11-NEXT: v_writelane_b32 v40, s30, 2 +; GFX11-NEXT: v_writelane_b32 v40, s31, 3 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 2 -; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -12966,14 +12976,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -13000,18 +13010,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 0x20001 ; GFX9-NEXT: s_mov_b32 s5, 3 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -13033,18 +13043,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 3 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 0x20001 +; GFX10-NEXT: s_mov_b32 s5, 3 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -13066,19 +13076,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 0x20001 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 3 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 ; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 0x20001 +; GFX11-NEXT: s_mov_b32 s5, 3 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -13100,18 +13109,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 3 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -13137,18 +13146,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 0x40003c00 ; GFX9-NEXT: s_movk_i32 s5, 0x4400 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -13170,18 +13179,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 0x40003c00 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_movk_i32 s5, 0x4400 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 0x40003c00 +; GFX10-NEXT: s_movk_i32 s5, 0x4400 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -13203,19 +13212,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 0x40003c00 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_movk_i32 s5, 0x4400 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 ; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 0x40003c00 +; GFX11-NEXT: s_movk_i32 s5, 0x4400 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -13237,18 +13245,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x40003c00 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_movk_i32 s5, 0x4400 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x40003c00 +; GFX10-SCRATCH-NEXT: s_movk_i32 s5, 0x4400 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -13274,17 +13282,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 -; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -13309,14 +13317,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 { ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 +; GFX10-NEXT: v_writelane_b32 v40, s30, 2 +; GFX10-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 2 -; GFX10-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -13341,15 +13349,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 { ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 +; GFX11-NEXT: v_writelane_b32 v40, s30, 2 +; GFX11-NEXT: v_writelane_b32 v40, s31, 3 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 2 -; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -13374,14 +13382,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -13408,18 +13416,18 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 0x20001 ; GFX9-NEXT: s_mov_b32 s5, 0x40003 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -13441,18 +13449,18 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 0x40003 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 0x20001 +; GFX10-NEXT: s_mov_b32 s5, 0x40003 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -13474,19 +13482,18 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 0x20001 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 0x40003 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 ; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 0x20001 +; GFX11-NEXT: s_mov_b32 s5, 0x40003 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -13508,18 +13515,18 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0x40003 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0x40003 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -13545,16 +13552,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 -; GFX9-NEXT: s_load_dword s4, s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 +; GFX9-NEXT: s_load_dword s4, s[34:35], 0x0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f16_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f16_inreg@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s30, v40, 1 +; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -13577,14 +13584,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: v_writelane_b32 v40, s30, 1 +; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_load_dword s4, s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f16_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 1 -; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -13607,15 +13614,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 { ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: v_writelane_b32 v40, s30, 1 +; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f16_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 1 -; GFX11-NEXT: v_writelane_b32 v40, s31, 2 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s30, v40, 1 +; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -13638,14 +13645,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3 @@ -13671,17 +13678,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 -; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -13706,14 +13713,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 { ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 +; GFX10-NEXT: v_writelane_b32 v40, s30, 2 +; GFX10-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 2 -; GFX10-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -13738,15 +13745,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 { ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 +; GFX11-NEXT: v_writelane_b32 v40, s30, 2 +; GFX11-NEXT: v_writelane_b32 v40, s31, 3 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 2 -; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -13771,14 +13778,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -13805,18 +13812,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 1 ; GFX9-NEXT: s_mov_b32 s5, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -13838,18 +13845,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 2 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 1 +; GFX10-NEXT: s_mov_b32 s5, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -13871,19 +13878,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 ; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 1 +; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -13905,18 +13911,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 @@ -13942,20 +13948,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 5 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 3 +; GFX9-NEXT: v_writelane_b32 v40, s31, 4 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 3 ; GFX9-NEXT: s_mov_b32 s5, 4 ; GFX9-NEXT: s_mov_b32 s6, 5 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 4 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 4 ; GFX9-NEXT: v_readlane_b32 s30, v40, 3 +; GFX9-NEXT: v_readlane_b32 s31, v40, 4 ; GFX9-NEXT: v_readlane_b32 s6, v40, 2 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 @@ -13978,20 +13984,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 5 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 3 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 4 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-NEXT: s_mov_b32 s6, 5 ; GFX10-NEXT: v_writelane_b32 v40, s30, 3 ; GFX10-NEXT: v_writelane_b32 v40, s31, 4 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 3 +; GFX10-NEXT: s_mov_b32 s5, 4 +; GFX10-NEXT: s_mov_b32 s6, 5 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 4 ; GFX10-NEXT: v_readlane_b32 s30, v40, 3 +; GFX10-NEXT: v_readlane_b32 s31, v40, 4 ; GFX10-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 @@ -14014,21 +14020,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 5 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 3 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 4 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 -; GFX11-NEXT: s_mov_b32 s6, 5 ; GFX11-NEXT: v_writelane_b32 v40, s30, 3 ; GFX11-NEXT: v_writelane_b32 v40, s31, 4 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 3 +; GFX11-NEXT: s_mov_b32 s5, 4 +; GFX11-NEXT: s_mov_b32 s6, 5 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 4 ; GFX11-NEXT: v_readlane_b32 s30, v40, 3 +; GFX11-NEXT: v_readlane_b32 s31, v40, 4 ; GFX11-NEXT: v_readlane_b32 s6, v40, 2 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 @@ -14051,20 +14056,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 5 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 5 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 4 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 4 +; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 5 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 4 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 3 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 4 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0 @@ -14091,22 +14096,22 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 6 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 ; GFX9-NEXT: v_writelane_b32 v40, s30, 4 +; GFX9-NEXT: v_writelane_b32 v40, s31, 5 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 3 ; GFX9-NEXT: s_mov_b32 s5, 4 ; GFX9-NEXT: s_mov_b32 s6, 5 ; GFX9-NEXT: s_mov_b32 s7, 6 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 5 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s30, v40, 4 +; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s7, v40, 3 ; GFX9-NEXT: v_readlane_b32 s6, v40, 2 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 @@ -14130,22 +14135,22 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 3 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 4 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-NEXT: s_mov_b32 s6, 5 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-NEXT: s_mov_b32 s7, 6 ; GFX10-NEXT: v_writelane_b32 v40, s30, 4 ; GFX10-NEXT: v_writelane_b32 v40, s31, 5 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 3 +; GFX10-NEXT: s_mov_b32 s5, 4 +; GFX10-NEXT: s_mov_b32 s6, 5 +; GFX10-NEXT: s_mov_b32 s7, 6 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 @@ -14169,23 +14174,22 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 3 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 4 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 -; GFX11-NEXT: s_mov_b32 s6, 5 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 -; GFX11-NEXT: s_mov_b32 s7, 6 ; GFX11-NEXT: v_writelane_b32 v40, s30, 4 ; GFX11-NEXT: v_writelane_b32 v40, s31, 5 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 3 +; GFX11-NEXT: s_mov_b32 s5, 4 +; GFX11-NEXT: s_mov_b32 s6, 5 +; GFX11-NEXT: s_mov_b32 s7, 6 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s30, v40, 4 +; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s7, v40, 3 ; GFX11-NEXT: v_readlane_b32 s6, v40, 2 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 @@ -14209,22 +14213,22 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 5 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 6 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 4 +; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 5 +; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 6 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 @@ -14252,19 +14256,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 6 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 -; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 4 +; GFX9-NEXT: v_writelane_b32 v40, s31, 5 +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 5 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s30, v40, 4 +; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s7, v40, 3 ; GFX9-NEXT: v_readlane_b32 s6, v40, 2 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 @@ -14293,14 +14297,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 +; GFX10-NEXT: v_writelane_b32 v40, s30, 4 +; GFX10-NEXT: v_writelane_b32 v40, s31, 5 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 4 -; GFX10-NEXT: v_writelane_b32 v40, s31, 5 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 @@ -14329,15 +14333,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 { ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 +; GFX11-NEXT: v_writelane_b32 v40, s30, 4 +; GFX11-NEXT: v_writelane_b32 v40, s31, 5 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 4 -; GFX11-NEXT: v_writelane_b32 v40, s31, 5 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s30, v40, 4 +; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s7, v40, 3 ; GFX11-NEXT: v_readlane_b32 s6, v40, 2 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 @@ -14366,14 +14370,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5 ; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 @@ -14402,22 +14406,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 6 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 ; GFX9-NEXT: v_writelane_b32 v40, s30, 4 +; GFX9-NEXT: v_writelane_b32 v40, s31, 5 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 1 ; GFX9-NEXT: s_mov_b32 s5, 2 ; GFX9-NEXT: s_mov_b32 s6, 3 ; GFX9-NEXT: s_mov_b32 s7, 4 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 5 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s30, v40, 4 +; GFX9-NEXT: v_readlane_b32 s31, v40, 5 ; GFX9-NEXT: v_readlane_b32 s7, v40, 3 ; GFX9-NEXT: v_readlane_b32 s6, v40, 2 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 @@ -14441,22 +14445,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 2 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-NEXT: s_mov_b32 s6, 3 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-NEXT: s_mov_b32 s7, 4 ; GFX10-NEXT: v_writelane_b32 v40, s30, 4 ; GFX10-NEXT: v_writelane_b32 v40, s31, 5 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 1 +; GFX10-NEXT: s_mov_b32 s5, 2 +; GFX10-NEXT: s_mov_b32 s6, 3 +; GFX10-NEXT: s_mov_b32 s7, 4 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 @@ -14480,23 +14484,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 -; GFX11-NEXT: s_mov_b32 s6, 3 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 -; GFX11-NEXT: s_mov_b32 s7, 4 ; GFX11-NEXT: v_writelane_b32 v40, s30, 4 ; GFX11-NEXT: v_writelane_b32 v40, s31, 5 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 1 +; GFX11-NEXT: s_mov_b32 s5, 2 +; GFX11-NEXT: s_mov_b32 s6, 3 +; GFX11-NEXT: s_mov_b32 s7, 4 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s30, v40, 4 +; GFX11-NEXT: v_readlane_b32 s31, v40, 5 ; GFX11-NEXT: v_readlane_b32 s7, v40, 3 ; GFX11-NEXT: v_readlane_b32 s6, v40, 2 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 @@ -14520,22 +14523,22 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 +; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1 @@ -14563,12 +14566,14 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 7 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 ; GFX9-NEXT: v_writelane_b32 v40, s8, 4 ; GFX9-NEXT: v_writelane_b32 v40, s30, 5 +; GFX9-NEXT: v_writelane_b32 v40, s31, 6 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 1 @@ -14576,11 +14581,9 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 { ; GFX9-NEXT: s_mov_b32 s6, 3 ; GFX9-NEXT: s_mov_b32 s7, 4 ; GFX9-NEXT: s_mov_b32 s8, 5 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 6 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 6 ; GFX9-NEXT: v_readlane_b32 s30, v40, 5 +; GFX9-NEXT: v_readlane_b32 s31, v40, 6 ; GFX9-NEXT: v_readlane_b32 s8, v40, 4 ; GFX9-NEXT: v_readlane_b32 s7, v40, 3 ; GFX9-NEXT: v_readlane_b32 s6, v40, 2 @@ -14605,24 +14608,24 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 7 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: v_writelane_b32 v40, s5, 1 +; GFX10-NEXT: v_writelane_b32 v40, s6, 2 +; GFX10-NEXT: v_writelane_b32 v40, s7, 3 +; GFX10-NEXT: v_writelane_b32 v40, s8, 4 +; GFX10-NEXT: v_writelane_b32 v40, s30, 5 +; GFX10-NEXT: v_writelane_b32 v40, s31, 6 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i32_inreg@abs32@lo ; GFX10-NEXT: s_mov_b32 s4, 1 -; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2 -; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: s_mov_b32 s6, 3 -; GFX10-NEXT: v_writelane_b32 v40, s7, 3 ; GFX10-NEXT: s_mov_b32 s7, 4 -; GFX10-NEXT: v_writelane_b32 v40, s8, 4 ; GFX10-NEXT: s_mov_b32 s8, 5 -; GFX10-NEXT: v_writelane_b32 v40, s30, 5 -; GFX10-NEXT: v_writelane_b32 v40, s31, 6 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 6 ; GFX10-NEXT: v_readlane_b32 s30, v40, 5 +; GFX10-NEXT: v_readlane_b32 s31, v40, 6 ; GFX10-NEXT: v_readlane_b32 s8, v40, 4 ; GFX10-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-NEXT: v_readlane_b32 s6, v40, 2 @@ -14647,25 +14650,24 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 7 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 -; GFX11-NEXT: s_mov_b32 s6, 3 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 -; GFX11-NEXT: s_mov_b32 s7, 4 ; GFX11-NEXT: v_writelane_b32 v40, s8, 4 -; GFX11-NEXT: s_mov_b32 s8, 5 ; GFX11-NEXT: v_writelane_b32 v40, s30, 5 ; GFX11-NEXT: v_writelane_b32 v40, s31, 6 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 1 +; GFX11-NEXT: s_mov_b32 s5, 2 +; GFX11-NEXT: s_mov_b32 s6, 3 +; GFX11-NEXT: s_mov_b32 s7, 4 +; GFX11-NEXT: s_mov_b32 s8, 5 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 6 ; GFX11-NEXT: v_readlane_b32 s30, v40, 5 +; GFX11-NEXT: v_readlane_b32 s31, v40, 6 ; GFX11-NEXT: v_readlane_b32 s8, v40, 4 ; GFX11-NEXT: v_readlane_b32 s7, v40, 3 ; GFX11-NEXT: v_readlane_b32 s6, v40, 2 @@ -14690,24 +14692,24 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 7 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 5 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 5 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 6 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i32_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 +; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4 +; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 5 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 6 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 5 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 6 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s8, v40, 4 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2 @@ -14736,25 +14738,25 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 10 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 -; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s7, 3 ; GFX9-NEXT: v_writelane_b32 v40, s8, 4 ; GFX9-NEXT: v_writelane_b32 v40, s9, 5 ; GFX9-NEXT: v_writelane_b32 v40, s10, 6 ; GFX9-NEXT: v_writelane_b32 v40, s11, 7 +; GFX9-NEXT: v_writelane_b32 v40, s30, 8 +; GFX9-NEXT: v_writelane_b32 v40, s31, 9 +; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[34:35], 0x0 -; GFX9-NEXT: v_writelane_b32 v40, s30, 8 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 9 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 9 ; GFX9-NEXT: v_readlane_b32 s30, v40, 8 +; GFX9-NEXT: v_readlane_b32 s31, v40, 9 ; GFX9-NEXT: v_readlane_b32 s11, v40, 7 ; GFX9-NEXT: v_readlane_b32 s10, v40, 6 ; GFX9-NEXT: v_readlane_b32 s9, v40, 5 @@ -14782,7 +14784,6 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 10 -; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 @@ -14792,15 +14793,16 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s9, 5 ; GFX10-NEXT: v_writelane_b32 v40, s10, 6 ; GFX10-NEXT: v_writelane_b32 v40, s11, 7 +; GFX10-NEXT: v_writelane_b32 v40, s30, 8 +; GFX10-NEXT: v_writelane_b32 v40, s31, 9 +; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 8 -; GFX10-NEXT: v_writelane_b32 v40, s31, 9 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-NEXT: v_readlane_b32 s30, v40, 8 +; GFX10-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-NEXT: v_readlane_b32 s11, v40, 7 ; GFX10-NEXT: v_readlane_b32 s10, v40, 6 ; GFX10-NEXT: v_readlane_b32 s9, v40, 5 @@ -14828,7 +14830,6 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 10 -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 @@ -14838,16 +14839,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 { ; GFX11-NEXT: v_writelane_b32 v40, s9, 5 ; GFX11-NEXT: v_writelane_b32 v40, s10, 6 ; GFX11-NEXT: v_writelane_b32 v40, s11, 7 +; GFX11-NEXT: v_writelane_b32 v40, s30, 8 +; GFX11-NEXT: v_writelane_b32 v40, s31, 9 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 8 -; GFX11-NEXT: v_writelane_b32 v40, s31, 9 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 9 ; GFX11-NEXT: v_readlane_b32 s30, v40, 8 +; GFX11-NEXT: v_readlane_b32 s31, v40, 9 ; GFX11-NEXT: v_readlane_b32 s11, v40, 7 ; GFX11-NEXT: v_readlane_b32 s10, v40, 6 ; GFX11-NEXT: v_readlane_b32 s9, v40, 5 @@ -14875,7 +14877,6 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10 -; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 @@ -14885,15 +14886,16 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s9, 5 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s10, 6 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s11, 7 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9 +; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 8 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s11, v40, 7 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s10, v40, 6 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s9, v40, 5 @@ -14927,6 +14929,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 10 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 @@ -14936,6 +14939,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 { ; GFX9-NEXT: v_writelane_b32 v40, s10, 6 ; GFX9-NEXT: v_writelane_b32 v40, s11, 7 ; GFX9-NEXT: v_writelane_b32 v40, s30, 8 +; GFX9-NEXT: v_writelane_b32 v40, s31, 9 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s4, 1 @@ -14946,11 +14950,9 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 { ; GFX9-NEXT: s_mov_b32 s9, 6 ; GFX9-NEXT: s_mov_b32 s10, 7 ; GFX9-NEXT: s_mov_b32 s11, 8 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 9 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 9 ; GFX9-NEXT: v_readlane_b32 s30, v40, 8 +; GFX9-NEXT: v_readlane_b32 s31, v40, 9 ; GFX9-NEXT: v_readlane_b32 s11, v40, 7 ; GFX9-NEXT: v_readlane_b32 s10, v40, 6 ; GFX9-NEXT: v_readlane_b32 s9, v40, 5 @@ -14978,30 +14980,30 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 10 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, 2 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-NEXT: s_mov_b32 s6, 3 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-NEXT: s_mov_b32 s7, 4 ; GFX10-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-NEXT: s_mov_b32 s8, 5 ; GFX10-NEXT: v_writelane_b32 v40, s9, 5 -; GFX10-NEXT: s_mov_b32 s9, 6 ; GFX10-NEXT: v_writelane_b32 v40, s10, 6 -; GFX10-NEXT: s_mov_b32 s10, 7 ; GFX10-NEXT: v_writelane_b32 v40, s11, 7 -; GFX10-NEXT: s_mov_b32 s11, 8 ; GFX10-NEXT: v_writelane_b32 v40, s30, 8 ; GFX10-NEXT: v_writelane_b32 v40, s31, 9 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg@abs32@lo +; GFX10-NEXT: s_mov_b32 s4, 1 +; GFX10-NEXT: s_mov_b32 s5, 2 +; GFX10-NEXT: s_mov_b32 s6, 3 +; GFX10-NEXT: s_mov_b32 s7, 4 +; GFX10-NEXT: s_mov_b32 s8, 5 +; GFX10-NEXT: s_mov_b32 s9, 6 +; GFX10-NEXT: s_mov_b32 s10, 7 +; GFX10-NEXT: s_mov_b32 s11, 8 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-NEXT: v_readlane_b32 s30, v40, 8 +; GFX10-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-NEXT: v_readlane_b32 s11, v40, 7 ; GFX10-NEXT: v_readlane_b32 s10, v40, 6 ; GFX10-NEXT: v_readlane_b32 s9, v40, 5 @@ -15029,31 +15031,30 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 10 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 -; GFX11-NEXT: s_mov_b32 s6, 3 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 -; GFX11-NEXT: s_mov_b32 s7, 4 ; GFX11-NEXT: v_writelane_b32 v40, s8, 4 -; GFX11-NEXT: s_mov_b32 s8, 5 ; GFX11-NEXT: v_writelane_b32 v40, s9, 5 -; GFX11-NEXT: s_mov_b32 s9, 6 ; GFX11-NEXT: v_writelane_b32 v40, s10, 6 -; GFX11-NEXT: s_mov_b32 s10, 7 ; GFX11-NEXT: v_writelane_b32 v40, s11, 7 -; GFX11-NEXT: s_mov_b32 s11, 8 ; GFX11-NEXT: v_writelane_b32 v40, s30, 8 ; GFX11-NEXT: v_writelane_b32 v40, s31, 9 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg@abs32@lo +; GFX11-NEXT: s_mov_b32 s4, 1 +; GFX11-NEXT: s_mov_b32 s5, 2 +; GFX11-NEXT: s_mov_b32 s6, 3 +; GFX11-NEXT: s_mov_b32 s7, 4 +; GFX11-NEXT: s_mov_b32 s8, 5 +; GFX11-NEXT: s_mov_b32 s9, 6 +; GFX11-NEXT: s_mov_b32 s10, 7 +; GFX11-NEXT: s_mov_b32 s11, 8 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 9 ; GFX11-NEXT: v_readlane_b32 s30, v40, 8 +; GFX11-NEXT: v_readlane_b32 s31, v40, 9 ; GFX11-NEXT: v_readlane_b32 s11, v40, 7 ; GFX11-NEXT: v_readlane_b32 s10, v40, 6 ; GFX11-NEXT: v_readlane_b32 s9, v40, 5 @@ -15081,30 +15082,30 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 -; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4 -; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 5 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s9, 5 -; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 6 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s10, 6 -; GFX10-SCRATCH-NEXT: s_mov_b32 s10, 7 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s11, 7 -; GFX10-SCRATCH-NEXT: s_mov_b32 s11, 8 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg@abs32@lo +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 +; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3 +; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4 +; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 5 +; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 6 +; GFX10-SCRATCH-NEXT: s_mov_b32 s10, 7 +; GFX10-SCRATCH-NEXT: s_mov_b32 s11, 8 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 8 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s11, v40, 7 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s10, v40, 6 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s9, v40, 5 @@ -15136,6 +15137,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 18 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 @@ -15147,22 +15149,21 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX9-NEXT: v_writelane_b32 v40, s12, 8 ; GFX9-NEXT: v_writelane_b32 v40, s13, 9 ; GFX9-NEXT: v_writelane_b32 v40, s14, 10 -; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s15, 11 ; GFX9-NEXT: v_writelane_b32 v40, s16, 12 ; GFX9-NEXT: v_writelane_b32 v40, s17, 13 ; GFX9-NEXT: v_writelane_b32 v40, s18, 14 ; GFX9-NEXT: v_writelane_b32 v40, s19, 15 +; GFX9-NEXT: v_writelane_b32 v40, s30, 16 +; GFX9-NEXT: v_writelane_b32 v40, s31, 17 +; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0 -; GFX9-NEXT: v_writelane_b32 v40, s30, 16 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16i32_inreg@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 17 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 17 ; GFX9-NEXT: v_readlane_b32 s30, v40, 16 +; GFX9-NEXT: v_readlane_b32 s31, v40, 17 ; GFX9-NEXT: v_readlane_b32 s19, v40, 15 ; GFX9-NEXT: v_readlane_b32 s18, v40, 14 ; GFX9-NEXT: v_readlane_b32 s17, v40, 13 @@ -15198,7 +15199,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 18 -; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 @@ -15216,15 +15216,16 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s17, 13 ; GFX10-NEXT: v_writelane_b32 v40, s18, 14 ; GFX10-NEXT: v_writelane_b32 v40, s19, 15 +; GFX10-NEXT: v_writelane_b32 v40, s30, 16 +; GFX10-NEXT: v_writelane_b32 v40, s31, 17 +; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16i32_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 16 -; GFX10-NEXT: v_writelane_b32 v40, s31, 17 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 17 ; GFX10-NEXT: v_readlane_b32 s30, v40, 16 +; GFX10-NEXT: v_readlane_b32 s31, v40, 17 ; GFX10-NEXT: v_readlane_b32 s19, v40, 15 ; GFX10-NEXT: v_readlane_b32 s18, v40, 14 ; GFX10-NEXT: v_readlane_b32 s17, v40, 13 @@ -15260,7 +15261,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 18 -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 @@ -15278,16 +15278,17 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX11-NEXT: v_writelane_b32 v40, s17, 13 ; GFX11-NEXT: v_writelane_b32 v40, s18, 14 ; GFX11-NEXT: v_writelane_b32 v40, s19, 15 +; GFX11-NEXT: v_writelane_b32 v40, s30, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 17 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_load_b512 s[4:19], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16i32_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 16 -; GFX11-NEXT: v_writelane_b32 v40, s31, 17 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 17 ; GFX11-NEXT: v_readlane_b32 s30, v40, 16 +; GFX11-NEXT: v_readlane_b32 s31, v40, 17 ; GFX11-NEXT: v_readlane_b32 s19, v40, 15 ; GFX11-NEXT: v_readlane_b32 s18, v40, 14 ; GFX11-NEXT: v_readlane_b32 s17, v40, 13 @@ -15323,7 +15324,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 18 -; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 @@ -15341,15 +15341,16 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s17, 13 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s18, 14 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s19, 15 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 17 +; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 17 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 17 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 16 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 17 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s19, v40, 15 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s18, v40, 14 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s17, v40, 13 @@ -15391,6 +15392,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 28 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 @@ -15407,23 +15409,26 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX9-NEXT: v_writelane_b32 v40, s17, 13 ; GFX9-NEXT: v_writelane_b32 v40, s18, 14 ; GFX9-NEXT: v_writelane_b32 v40, s19, 15 -; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s20, 16 ; GFX9-NEXT: v_writelane_b32 v40, s21, 17 ; GFX9-NEXT: v_writelane_b32 v40, s22, 18 ; GFX9-NEXT: v_writelane_b32 v40, s23, 19 ; GFX9-NEXT: v_writelane_b32 v40, s24, 20 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_load_dwordx16 s[36:51], s[34:35], 0x40 -; GFX9-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s25, 21 ; GFX9-NEXT: v_writelane_b32 v40, s26, 22 ; GFX9-NEXT: v_writelane_b32 v40, s27, 23 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s28, 24 +; GFX9-NEXT: v_writelane_b32 v40, s29, 25 +; GFX9-NEXT: v_writelane_b32 v40, s30, 26 +; GFX9-NEXT: v_writelane_b32 v40, s31, 27 +; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dwordx16 s[36:51], s[34:35], 0x40 +; GFX9-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_inreg@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32_inreg@abs32@lo ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, s46 -; GFX9-NEXT: v_writelane_b32 v40, s29, 25 ; GFX9-NEXT: v_mov_b32_e32 v1, s47 ; GFX9-NEXT: v_mov_b32_e32 v2, s48 ; GFX9-NEXT: v_mov_b32_e32 v3, s49 @@ -15432,11 +15437,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12 ; GFX9-NEXT: v_mov_b32_e32 v0, s50 -; GFX9-NEXT: v_writelane_b32 v40, s30, 26 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; GFX9-NEXT: v_mov_b32_e32 v0, s51 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_inreg@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s20, s36 ; GFX9-NEXT: s_mov_b32 s21, s37 ; GFX9-NEXT: s_mov_b32 s22, s38 @@ -15447,11 +15449,10 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX9-NEXT: s_mov_b32 s27, s43 ; GFX9-NEXT: s_mov_b32 s28, s44 ; GFX9-NEXT: s_mov_b32 s29, s45 -; GFX9-NEXT: v_writelane_b32 v40, s31, 27 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 27 ; GFX9-NEXT: v_readlane_b32 s30, v40, 26 +; GFX9-NEXT: v_readlane_b32 s31, v40, 27 ; GFX9-NEXT: v_readlane_b32 s29, v40, 25 ; GFX9-NEXT: v_readlane_b32 s28, v40, 24 ; GFX9-NEXT: v_readlane_b32 s27, v40, 23 @@ -15497,7 +15498,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 28 -; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 @@ -15515,29 +15515,40 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s17, 13 ; GFX10-NEXT: v_writelane_b32 v40, s18, 14 ; GFX10-NEXT: v_writelane_b32 v40, s19, 15 +; GFX10-NEXT: v_writelane_b32 v40, s20, 16 +; GFX10-NEXT: v_writelane_b32 v40, s21, 17 +; GFX10-NEXT: v_writelane_b32 v40, s22, 18 +; GFX10-NEXT: v_writelane_b32 v40, s23, 19 +; GFX10-NEXT: v_writelane_b32 v40, s24, 20 +; GFX10-NEXT: v_writelane_b32 v40, s25, 21 +; GFX10-NEXT: v_writelane_b32 v40, s26, 22 +; GFX10-NEXT: v_writelane_b32 v40, s27, 23 +; GFX10-NEXT: v_writelane_b32 v40, s28, 24 +; GFX10-NEXT: v_writelane_b32 v40, s29, 25 +; GFX10-NEXT: v_writelane_b32 v40, s30, 26 +; GFX10-NEXT: v_writelane_b32 v40, s31, 27 +; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_load_dwordx16 s[36:51], s[34:35], 0x40 ; GFX10-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s20, 16 -; GFX10-NEXT: v_writelane_b32 v40, s21, 17 -; GFX10-NEXT: v_writelane_b32 v40, s22, 18 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: v_mov_b32_e32 v0, s46 -; GFX10-NEXT: v_writelane_b32 v40, s23, 19 ; GFX10-NEXT: v_mov_b32_e32 v1, s47 ; GFX10-NEXT: v_mov_b32_e32 v2, s48 ; GFX10-NEXT: v_mov_b32_e32 v3, s49 ; GFX10-NEXT: s_mov_b32 s20, s36 -; GFX10-NEXT: v_writelane_b32 v40, s24, 20 ; GFX10-NEXT: s_mov_b32 s21, s37 ; GFX10-NEXT: s_mov_b32 s22, s38 ; GFX10-NEXT: s_mov_b32 s23, s39 ; GFX10-NEXT: s_mov_b32 s24, s40 -; GFX10-NEXT: v_writelane_b32 v40, s25, 21 ; GFX10-NEXT: s_mov_b32 s25, s41 +; GFX10-NEXT: s_mov_b32 s26, s42 +; GFX10-NEXT: s_mov_b32 s27, s43 +; GFX10-NEXT: s_mov_b32 s28, s44 +; GFX10-NEXT: s_mov_b32 s29, s45 ; GFX10-NEXT: v_mov_b32_e32 v4, s50 ; GFX10-NEXT: v_mov_b32_e32 v5, s51 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -15546,19 +15557,9 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12 ; GFX10-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:16 ; GFX10-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:20 -; GFX10-NEXT: v_writelane_b32 v40, s26, 22 -; GFX10-NEXT: s_mov_b32 s26, s42 -; GFX10-NEXT: v_writelane_b32 v40, s27, 23 -; GFX10-NEXT: s_mov_b32 s27, s43 -; GFX10-NEXT: v_writelane_b32 v40, s28, 24 -; GFX10-NEXT: s_mov_b32 s28, s44 -; GFX10-NEXT: v_writelane_b32 v40, s29, 25 -; GFX10-NEXT: s_mov_b32 s29, s45 -; GFX10-NEXT: v_writelane_b32 v40, s30, 26 -; GFX10-NEXT: v_writelane_b32 v40, s31, 27 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 27 ; GFX10-NEXT: v_readlane_b32 s30, v40, 26 +; GFX10-NEXT: v_readlane_b32 s31, v40, 27 ; GFX10-NEXT: v_readlane_b32 s29, v40, 25 ; GFX10-NEXT: v_readlane_b32 s28, v40, 24 ; GFX10-NEXT: v_readlane_b32 s27, v40, 23 @@ -15604,10 +15605,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 28 -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_add_i32 s2, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -15624,44 +15622,45 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX11-NEXT: v_writelane_b32 v40, s17, 13 ; GFX11-NEXT: v_writelane_b32 v40, s18, 14 ; GFX11-NEXT: v_writelane_b32 v40, s19, 15 +; GFX11-NEXT: v_writelane_b32 v40, s20, 16 +; GFX11-NEXT: v_writelane_b32 v40, s21, 17 +; GFX11-NEXT: v_writelane_b32 v40, s22, 18 +; GFX11-NEXT: v_writelane_b32 v40, s23, 19 +; GFX11-NEXT: v_writelane_b32 v40, s24, 20 +; GFX11-NEXT: v_writelane_b32 v40, s25, 21 +; GFX11-NEXT: v_writelane_b32 v40, s26, 22 +; GFX11-NEXT: v_writelane_b32 v40, s27, 23 +; GFX11-NEXT: v_writelane_b32 v40, s28, 24 +; GFX11-NEXT: v_writelane_b32 v40, s29, 25 +; GFX11-NEXT: v_writelane_b32 v40, s30, 26 +; GFX11-NEXT: v_writelane_b32 v40, s31, 27 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: s_add_i32 s2, s32, 16 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_load_b512 s[36:51], s[0:1], 0x40 ; GFX11-NEXT: s_load_b512 s[4:19], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i32_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s20, 16 -; GFX11-NEXT: v_writelane_b32 v40, s21, 17 -; GFX11-NEXT: v_writelane_b32 v40, s22, 18 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: v_dual_mov_b32 v4, s50 :: v_dual_mov_b32 v5, s51 -; GFX11-NEXT: v_writelane_b32 v40, s23, 19 ; GFX11-NEXT: v_dual_mov_b32 v0, s46 :: v_dual_mov_b32 v1, s47 ; GFX11-NEXT: v_dual_mov_b32 v2, s48 :: v_dual_mov_b32 v3, s49 -; GFX11-NEXT: v_writelane_b32 v40, s24, 20 ; GFX11-NEXT: s_mov_b32 s20, s36 ; GFX11-NEXT: s_mov_b32 s21, s37 ; GFX11-NEXT: s_mov_b32 s22, s38 ; GFX11-NEXT: s_mov_b32 s23, s39 -; GFX11-NEXT: v_writelane_b32 v40, s25, 21 ; GFX11-NEXT: s_mov_b32 s24, s40 ; GFX11-NEXT: s_mov_b32 s25, s41 -; GFX11-NEXT: scratch_store_b64 off, v[4:5], s2 -; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 -; GFX11-NEXT: v_writelane_b32 v40, s26, 22 ; GFX11-NEXT: s_mov_b32 s26, s42 -; GFX11-NEXT: v_writelane_b32 v40, s27, 23 ; GFX11-NEXT: s_mov_b32 s27, s43 -; GFX11-NEXT: v_writelane_b32 v40, s28, 24 ; GFX11-NEXT: s_mov_b32 s28, s44 -; GFX11-NEXT: v_writelane_b32 v40, s29, 25 ; GFX11-NEXT: s_mov_b32 s29, s45 -; GFX11-NEXT: v_writelane_b32 v40, s30, 26 -; GFX11-NEXT: v_writelane_b32 v40, s31, 27 +; GFX11-NEXT: scratch_store_b64 off, v[4:5], s2 +; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 27 ; GFX11-NEXT: v_readlane_b32 s30, v40, 26 +; GFX11-NEXT: v_readlane_b32 s31, v40, 27 ; GFX11-NEXT: v_readlane_b32 s29, v40, 25 ; GFX11-NEXT: v_readlane_b32 s28, v40, 24 ; GFX11-NEXT: v_readlane_b32 s27, v40, 23 @@ -15707,9 +15706,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 28 -; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: s_add_i32 s2, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -15726,46 +15723,48 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s17, 13 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s18, 14 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s19, 15 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27 +; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 +; GFX10-SCRATCH-NEXT: s_add_i32 s2, s32, 16 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[36:51], s[0:1], 0x40 ; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, s50 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, s51 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s46 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s47 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, s48 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, s49 ; GFX10-SCRATCH-NEXT: s_mov_b32 s20, s36 ; GFX10-SCRATCH-NEXT: s_mov_b32 s21, s37 ; GFX10-SCRATCH-NEXT: s_mov_b32 s22, s38 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21 ; GFX10-SCRATCH-NEXT: s_mov_b32 s23, s39 ; GFX10-SCRATCH-NEXT: s_mov_b32 s24, s40 ; GFX10-SCRATCH-NEXT: s_mov_b32 s25, s41 -; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[4:5], s2 -; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22 ; GFX10-SCRATCH-NEXT: s_mov_b32 s26, s42 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23 ; GFX10-SCRATCH-NEXT: s_mov_b32 s27, s43 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24 ; GFX10-SCRATCH-NEXT: s_mov_b32 s28, s44 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25 ; GFX10-SCRATCH-NEXT: s_mov_b32 s29, s45 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27 +; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[4:5], s2 +; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 27 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 26 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 27 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s29, v40, 25 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s28, v40, 24 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s27, v40, 23 @@ -15817,6 +15816,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 28 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s6, 2 @@ -15832,41 +15832,41 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX9-NEXT: v_writelane_b32 v40, s16, 12 ; GFX9-NEXT: v_writelane_b32 v40, s17, 13 ; GFX9-NEXT: v_writelane_b32 v40, s18, 14 -; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX9-NEXT: v_writelane_b32 v40, s19, 15 ; GFX9-NEXT: v_writelane_b32 v40, s20, 16 ; GFX9-NEXT: v_writelane_b32 v40, s21, 17 ; GFX9-NEXT: v_writelane_b32 v40, s22, 18 ; GFX9-NEXT: v_writelane_b32 v40, s23, 19 +; GFX9-NEXT: v_writelane_b32 v40, s24, 20 +; GFX9-NEXT: v_writelane_b32 v40, s25, 21 +; GFX9-NEXT: v_writelane_b32 v40, s26, 22 +; GFX9-NEXT: v_writelane_b32 v40, s27, 23 +; GFX9-NEXT: v_writelane_b32 v40, s28, 24 +; GFX9-NEXT: v_writelane_b32 v40, s29, 25 +; GFX9-NEXT: v_writelane_b32 v40, s30, 26 +; GFX9-NEXT: v_writelane_b32 v40, s31, 27 +; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_load_dword s52, s[34:35], 0x0 ; GFX9-NEXT: ; kill: killed $sgpr34_sgpr35 ; GFX9-NEXT: ; kill: killed $sgpr34_sgpr35 ; GFX9-NEXT: s_load_dwordx16 s[36:51], s[34:35], 0x40 ; GFX9-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0 -; GFX9-NEXT: v_writelane_b32 v40, s24, 20 -; GFX9-NEXT: v_writelane_b32 v40, s25, 21 -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s26, 22 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, s52 -; GFX9-NEXT: v_writelane_b32 v40, s27, 23 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32_inreg@abs32@hi ; GFX9-NEXT: v_mov_b32_e32 v0, s46 -; GFX9-NEXT: v_writelane_b32 v40, s28, 24 ; GFX9-NEXT: v_mov_b32_e32 v1, s47 ; GFX9-NEXT: v_mov_b32_e32 v2, s48 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX9-NEXT: v_mov_b32_e32 v0, s49 -; GFX9-NEXT: v_writelane_b32 v40, s29, 25 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GFX9-NEXT: v_mov_b32_e32 v0, s50 -; GFX9-NEXT: v_writelane_b32 v40, s30, 26 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; GFX9-NEXT: v_mov_b32_e32 v0, s51 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32_inreg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32_i32_inreg@abs32@lo ; GFX9-NEXT: s_mov_b32 s20, s36 ; GFX9-NEXT: s_mov_b32 s21, s37 @@ -15878,11 +15878,10 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX9-NEXT: s_mov_b32 s27, s43 ; GFX9-NEXT: s_mov_b32 s28, s44 ; GFX9-NEXT: s_mov_b32 s29, s45 -; GFX9-NEXT: v_writelane_b32 v40, s31, 27 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 27 ; GFX9-NEXT: v_readlane_b32 s30, v40, 26 +; GFX9-NEXT: v_readlane_b32 s31, v40, 27 ; GFX9-NEXT: v_readlane_b32 s29, v40, 25 ; GFX9-NEXT: v_readlane_b32 s28, v40, 24 ; GFX9-NEXT: v_readlane_b32 s27, v40, 23 @@ -15928,7 +15927,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 28 -; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 @@ -15946,6 +15944,19 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX10-NEXT: v_writelane_b32 v40, s17, 13 ; GFX10-NEXT: v_writelane_b32 v40, s18, 14 ; GFX10-NEXT: v_writelane_b32 v40, s19, 15 +; GFX10-NEXT: v_writelane_b32 v40, s20, 16 +; GFX10-NEXT: v_writelane_b32 v40, s21, 17 +; GFX10-NEXT: v_writelane_b32 v40, s22, 18 +; GFX10-NEXT: v_writelane_b32 v40, s23, 19 +; GFX10-NEXT: v_writelane_b32 v40, s24, 20 +; GFX10-NEXT: v_writelane_b32 v40, s25, 21 +; GFX10-NEXT: v_writelane_b32 v40, s26, 22 +; GFX10-NEXT: v_writelane_b32 v40, s27, 23 +; GFX10-NEXT: v_writelane_b32 v40, s28, 24 +; GFX10-NEXT: v_writelane_b32 v40, s29, 25 +; GFX10-NEXT: v_writelane_b32 v40, s30, 26 +; GFX10-NEXT: v_writelane_b32 v40, s31, 27 +; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_load_dword s52, s[34:35], 0x0 @@ -15955,46 +15966,34 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX10-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32_i32_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s20, 16 -; GFX10-NEXT: v_writelane_b32 v40, s21, 17 -; GFX10-NEXT: v_writelane_b32 v40, s22, 18 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: v_mov_b32_e32 v0, s52 ; GFX10-NEXT: v_mov_b32_e32 v1, s47 -; GFX10-NEXT: v_writelane_b32 v40, s23, 19 +; GFX10-NEXT: v_mov_b32_e32 v2, s48 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; GFX10-NEXT: v_mov_b32_e32 v0, s46 -; GFX10-NEXT: v_mov_b32_e32 v2, s48 ; GFX10-NEXT: v_mov_b32_e32 v3, s49 -; GFX10-NEXT: v_writelane_b32 v40, s24, 20 ; GFX10-NEXT: s_mov_b32 s20, s36 ; GFX10-NEXT: s_mov_b32 s21, s37 ; GFX10-NEXT: s_mov_b32 s22, s38 ; GFX10-NEXT: s_mov_b32 s23, s39 -; GFX10-NEXT: v_writelane_b32 v40, s25, 21 ; GFX10-NEXT: s_mov_b32 s24, s40 ; GFX10-NEXT: s_mov_b32 s25, s41 +; GFX10-NEXT: s_mov_b32 s26, s42 +; GFX10-NEXT: s_mov_b32 s27, s43 +; GFX10-NEXT: s_mov_b32 s28, s44 +; GFX10-NEXT: s_mov_b32 s29, s45 ; GFX10-NEXT: v_mov_b32_e32 v4, s50 ; GFX10-NEXT: v_mov_b32_e32 v5, s51 -; GFX10-NEXT: v_writelane_b32 v40, s26, 22 -; GFX10-NEXT: s_mov_b32 s26, s42 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12 ; GFX10-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:16 ; GFX10-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:20 -; GFX10-NEXT: v_writelane_b32 v40, s27, 23 -; GFX10-NEXT: s_mov_b32 s27, s43 -; GFX10-NEXT: v_writelane_b32 v40, s28, 24 -; GFX10-NEXT: s_mov_b32 s28, s44 -; GFX10-NEXT: v_writelane_b32 v40, s29, 25 -; GFX10-NEXT: s_mov_b32 s29, s45 -; GFX10-NEXT: v_writelane_b32 v40, s30, 26 -; GFX10-NEXT: v_writelane_b32 v40, s31, 27 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 27 ; GFX10-NEXT: v_readlane_b32 s30, v40, 26 +; GFX10-NEXT: v_readlane_b32 s31, v40, 27 ; GFX10-NEXT: v_readlane_b32 s29, v40, 25 ; GFX10-NEXT: v_readlane_b32 s28, v40, 24 ; GFX10-NEXT: v_readlane_b32 s27, v40, 23 @@ -16040,10 +16039,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 28 -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_add_i32 s3, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -16060,6 +16056,20 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX11-NEXT: v_writelane_b32 v40, s17, 13 ; GFX11-NEXT: v_writelane_b32 v40, s18, 14 ; GFX11-NEXT: v_writelane_b32 v40, s19, 15 +; GFX11-NEXT: v_writelane_b32 v40, s20, 16 +; GFX11-NEXT: v_writelane_b32 v40, s21, 17 +; GFX11-NEXT: v_writelane_b32 v40, s22, 18 +; GFX11-NEXT: v_writelane_b32 v40, s23, 19 +; GFX11-NEXT: v_writelane_b32 v40, s24, 20 +; GFX11-NEXT: v_writelane_b32 v40, s25, 21 +; GFX11-NEXT: v_writelane_b32 v40, s26, 22 +; GFX11-NEXT: v_writelane_b32 v40, s27, 23 +; GFX11-NEXT: v_writelane_b32 v40, s28, 24 +; GFX11-NEXT: v_writelane_b32 v40, s29, 25 +; GFX11-NEXT: v_writelane_b32 v40, s30, 26 +; GFX11-NEXT: v_writelane_b32 v40, s31, 27 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: s_add_i32 s3, s32, 16 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_clause 0x2 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x0 @@ -16067,41 +16077,28 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX11-NEXT: s_load_b512 s[4:19], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i32_i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i32_i32_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s20, 16 -; GFX11-NEXT: v_writelane_b32 v40, s21, 17 -; GFX11-NEXT: v_writelane_b32 v40, s22, 18 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v5, s51 -; GFX11-NEXT: v_writelane_b32 v40, s23, 19 ; GFX11-NEXT: v_dual_mov_b32 v4, s50 :: v_dual_mov_b32 v1, s47 ; GFX11-NEXT: v_dual_mov_b32 v0, s46 :: v_dual_mov_b32 v3, s49 -; GFX11-NEXT: v_writelane_b32 v40, s24, 20 ; GFX11-NEXT: v_mov_b32_e32 v2, s48 ; GFX11-NEXT: s_add_i32 s2, s32, 24 ; GFX11-NEXT: s_mov_b32 s20, s36 ; GFX11-NEXT: s_mov_b32 s21, s37 -; GFX11-NEXT: v_writelane_b32 v40, s25, 21 ; GFX11-NEXT: s_mov_b32 s22, s38 ; GFX11-NEXT: s_mov_b32 s23, s39 ; GFX11-NEXT: s_mov_b32 s24, s40 ; GFX11-NEXT: s_mov_b32 s25, s41 -; GFX11-NEXT: v_writelane_b32 v40, s26, 22 ; GFX11-NEXT: s_mov_b32 s26, s42 -; GFX11-NEXT: scratch_store_b32 off, v6, s2 -; GFX11-NEXT: scratch_store_b64 off, v[4:5], s3 -; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 -; GFX11-NEXT: v_writelane_b32 v40, s27, 23 ; GFX11-NEXT: s_mov_b32 s27, s43 -; GFX11-NEXT: v_writelane_b32 v40, s28, 24 ; GFX11-NEXT: s_mov_b32 s28, s44 -; GFX11-NEXT: v_writelane_b32 v40, s29, 25 ; GFX11-NEXT: s_mov_b32 s29, s45 -; GFX11-NEXT: v_writelane_b32 v40, s30, 26 -; GFX11-NEXT: v_writelane_b32 v40, s31, 27 +; GFX11-NEXT: scratch_store_b32 off, v6, s2 +; GFX11-NEXT: scratch_store_b64 off, v[4:5], s3 +; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 27 ; GFX11-NEXT: v_readlane_b32 s30, v40, 26 +; GFX11-NEXT: v_readlane_b32 s31, v40, 27 ; GFX11-NEXT: v_readlane_b32 s29, v40, 25 ; GFX11-NEXT: v_readlane_b32 s28, v40, 24 ; GFX11-NEXT: v_readlane_b32 s27, v40, 23 @@ -16147,9 +16144,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 28 -; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: s_add_i32 s3, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -16166,6 +16161,20 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s17, 13 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s18, 14 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s19, 15 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27 +; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 +; GFX10-SCRATCH-NEXT: s_add_i32 s3, s32, 16 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x2 ; GFX10-SCRATCH-NEXT: s_load_dword s2, s[0:1], 0x0 @@ -16175,43 +16184,31 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i32_i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32_i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, s2 ; GFX10-SCRATCH-NEXT: s_add_i32 s2, s32, 24 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, s50 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, s51 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s46 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s47 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, s48 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, s49 ; GFX10-SCRATCH-NEXT: s_mov_b32 s20, s36 ; GFX10-SCRATCH-NEXT: s_mov_b32 s21, s37 ; GFX10-SCRATCH-NEXT: s_mov_b32 s22, s38 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21 ; GFX10-SCRATCH-NEXT: s_mov_b32 s23, s39 ; GFX10-SCRATCH-NEXT: s_mov_b32 s24, s40 ; GFX10-SCRATCH-NEXT: s_mov_b32 s25, s41 -; GFX10-SCRATCH-NEXT: scratch_store_dword off, v6, s2 -; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[4:5], s3 -; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22 ; GFX10-SCRATCH-NEXT: s_mov_b32 s26, s42 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23 ; GFX10-SCRATCH-NEXT: s_mov_b32 s27, s43 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24 ; GFX10-SCRATCH-NEXT: s_mov_b32 s28, s44 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25 ; GFX10-SCRATCH-NEXT: s_mov_b32 s29, s45 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27 +; GFX10-SCRATCH-NEXT: scratch_store_dword off, v6, s2 +; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[4:5], s3 +; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 27 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 26 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 27 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s29, v40, 25 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s28, v40, 24 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s27, v40, 23 @@ -16263,21 +16260,21 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s33 -; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:4 ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s33 +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:4 ; GFX9-NEXT: s_mov_b32 s35, stack_passed_f64_arg@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, stack_passed_f64_arg@abs32@lo -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -16296,22 +16293,22 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 ; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:4 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_mov_b32 s35, stack_passed_f64_arg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, stack_passed_f64_arg@abs32@lo ; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -16330,18 +16327,18 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:8 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: scratch_load_b64 v[32:33], off, s33 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: scratch_load_b64 v[32:33], off, s33 ; GFX11-NEXT: s_mov_b32 s1, stack_passed_f64_arg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, stack_passed_f64_arg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: scratch_store_b64 off, v[32:33], s32 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -16360,18 +16357,18 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, stack_passed_f64_arg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, stack_passed_f64_arg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[32:33], s32 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -16395,16 +16392,17 @@ define amdgpu_gfx void @stack_12xv3i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 12 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; GFX9-NEXT: v_mov_b32_e32 v0, 14 -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; GFX9-NEXT: v_mov_b32_e32 v0, 15 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_12xv3i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_12xv3i32@abs32@lo @@ -16440,10 +16438,9 @@ define amdgpu_gfx void @stack_12xv3i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v29, 9 ; GFX9-NEXT: v_mov_b32_e32 v30, 10 ; GFX9-NEXT: v_mov_b32_e32 v31, 11 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -16463,12 +16460,14 @@ define amdgpu_gfx void @stack_12xv3i32() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 12 ; GFX10-NEXT: v_mov_b32_e32 v1, 13 ; GFX10-NEXT: v_mov_b32_e32 v2, 14 -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_mov_b32_e32 v3, 15 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 @@ -16477,7 +16476,6 @@ define amdgpu_gfx void @stack_12xv3i32() #0 { ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 1 -; GFX10-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-NEXT: v_mov_b32_e32 v5, 1 ; GFX10-NEXT: v_mov_b32_e32 v6, 2 ; GFX10-NEXT: v_mov_b32_e32 v7, 2 @@ -16507,10 +16505,9 @@ define amdgpu_gfx void @stack_12xv3i32() #0 { ; GFX10-NEXT: v_mov_b32_e32 v31, 11 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_12xv3i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_12xv3i32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -16530,15 +16527,16 @@ define amdgpu_gfx void @stack_12xv3i32() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 12 :: v_dual_mov_b32 v1, 13 ; GFX11-NEXT: v_dual_mov_b32 v2, 14 :: v_dual_mov_b32 v3, 15 -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v4, 1 :: v_dual_mov_b32 v5, 1 +; GFX11-NEXT: v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 2 ; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 1 -; GFX11-NEXT: v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 2 ; GFX11-NEXT: v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 3 ; GFX11-NEXT: v_dual_mov_b32 v10, 3 :: v_dual_mov_b32 v11, 3 ; GFX11-NEXT: v_dual_mov_b32 v12, 4 :: v_dual_mov_b32 v13, 4 @@ -16553,11 +16551,10 @@ define amdgpu_gfx void @stack_12xv3i32() #0 { ; GFX11-NEXT: v_dual_mov_b32 v30, 10 :: v_dual_mov_b32 v31, 11 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_12xv3i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_12xv3i32@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -16577,21 +16574,22 @@ define amdgpu_gfx void @stack_12xv3i32() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 12 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 13 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 14 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 15 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 1 +; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 2 +; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 2 ; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 1 -; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 2 -; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v9, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v10, 3 @@ -16618,10 +16616,9 @@ define amdgpu_gfx void @stack_12xv3i32() #0 { ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v31, 11 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_12xv3i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_12xv3i32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -16657,7 +16654,10 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 8 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX9-NEXT: v_mov_b32_e32 v0, 9 @@ -16671,10 +16671,8 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20 ; GFX9-NEXT: v_mov_b32_e32 v0, 14 -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; GFX9-NEXT: v_mov_b32_e32 v0, 15 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_8xv5i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_8xv5i32@abs32@lo @@ -16710,10 +16708,9 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v29, 5 ; GFX9-NEXT: v_mov_b32_e32 v30, 6 ; GFX9-NEXT: v_mov_b32_e32 v31, 7 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -16732,20 +16729,22 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 8 ; GFX10-NEXT: v_mov_b32_e32 v1, 9 ; GFX10-NEXT: v_mov_b32_e32 v2, 10 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_mov_b32_e32 v3, 14 +; GFX10-NEXT: v_mov_b32_e32 v4, 15 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX10-NEXT: v_mov_b32_e32 v0, 11 ; GFX10-NEXT: v_mov_b32_e32 v1, 12 ; GFX10-NEXT: v_mov_b32_e32 v2, 13 -; GFX10-NEXT: v_mov_b32_e32 v3, 14 -; GFX10-NEXT: v_mov_b32_e32 v4, 15 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_mov_b32_e32 v5, 1 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:16 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:20 @@ -16756,7 +16755,6 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0 -; GFX10-NEXT: v_mov_b32_e32 v5, 1 ; GFX10-NEXT: v_mov_b32_e32 v6, 1 ; GFX10-NEXT: v_mov_b32_e32 v7, 1 ; GFX10-NEXT: v_mov_b32_e32 v8, 1 @@ -16785,10 +16783,9 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX10-NEXT: v_mov_b32_e32 v31, 7 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_8xv5i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_8xv5i32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -16808,12 +16805,13 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, 8 :: v_dual_mov_b32 v1, 9 ; GFX11-NEXT: v_dual_mov_b32 v2, 10 :: v_dual_mov_b32 v3, 11 ; GFX11-NEXT: v_dual_mov_b32 v4, 12 :: v_dual_mov_b32 v5, 13 ; GFX11-NEXT: v_dual_mov_b32 v6, 14 :: v_dual_mov_b32 v7, 15 -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s0, s32, 16 ; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 ; GFX11-NEXT: scratch_store_b128 off, v[4:7], s0 @@ -16835,11 +16833,10 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX11-NEXT: v_dual_mov_b32 v30, 6 :: v_dual_mov_b32 v31, 7 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_8xv5i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_8xv5i32@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -16859,6 +16856,9 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 8 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 9 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 10 @@ -16867,8 +16867,6 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 13 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 14 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 15 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s0, s32, 16 ; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 ; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[4:7], s0 @@ -16906,10 +16904,9 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v31, 7 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_8xv5i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_8xv5i32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -16941,7 +16938,10 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41000000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41100000 @@ -16955,10 +16955,8 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41500000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41600000 -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41700000 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_8xv5f32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_8xv5f32@abs32@lo @@ -16994,10 +16992,9 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v29, 0x40a00000 ; GFX9-NEXT: v_mov_b32_e32 v30, 0x40c00000 ; GFX9-NEXT: v_mov_b32_e32 v31, 0x40e00000 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -17016,20 +17013,22 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x41000000 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x41100000 ; GFX10-NEXT: v_mov_b32_e32 v2, 0x41200000 -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 +; GFX10-NEXT: v_mov_b32_e32 v3, 0x41600000 +; GFX10-NEXT: v_mov_b32_e32 v4, 0x41700000 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x41300000 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x41400000 ; GFX10-NEXT: v_mov_b32_e32 v2, 0x41500000 -; GFX10-NEXT: v_mov_b32_e32 v3, 0x41600000 -; GFX10-NEXT: v_mov_b32_e32 v4, 0x41700000 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_mov_b32_e32 v5, 1.0 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:16 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:20 @@ -17040,7 +17039,6 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0 -; GFX10-NEXT: v_mov_b32_e32 v5, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v6, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v7, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v8, 1.0 @@ -17069,10 +17067,9 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX10-NEXT: v_mov_b32_e32 v31, 0x40e00000 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_8xv5f32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_8xv5f32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -17092,6 +17089,9 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x41000000 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x41100000 ; GFX11-NEXT: v_mov_b32_e32 v2, 0x41200000 @@ -17100,8 +17100,6 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX11-NEXT: v_mov_b32_e32 v5, 0x41500000 ; GFX11-NEXT: v_mov_b32_e32 v6, 0x41600000 ; GFX11-NEXT: v_mov_b32_e32 v7, 0x41700000 -; GFX11-NEXT: s_add_i32 s32, s32, 16 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s0, s32, 16 ; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 ; GFX11-NEXT: scratch_store_b128 off, v[4:7], s0 @@ -17124,11 +17122,10 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX11-NEXT: v_mov_b32_e32 v31, 0x40e00000 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_8xv5f32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_8xv5f32@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -17148,6 +17145,9 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x41000000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x41100000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0x41200000 @@ -17156,8 +17156,6 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 0x41500000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 0x41600000 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 0x41700000 -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s0, s32, 16 ; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32 ; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[4:7], s0 @@ -17195,10 +17193,9 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v31, 0x40e00000 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_8xv5f32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_8xv5f32@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -17232,13 +17229,13 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -17258,14 +17255,14 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -17285,15 +17282,15 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -17313,14 +17310,14 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -17346,13 +17343,13 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v1bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v1bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v1bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v1bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -17372,14 +17369,14 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v1bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v1bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -17399,15 +17396,15 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -17427,14 +17424,14 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -17460,13 +17457,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -17486,14 +17483,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -17513,15 +17510,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -17541,14 +17538,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -17574,13 +17571,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -17600,14 +17597,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -17627,15 +17624,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -17655,14 +17652,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -17688,13 +17685,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -17714,14 +17711,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -17741,15 +17738,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -17769,14 +17766,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -17802,13 +17799,13 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -17828,14 +17825,14 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -17855,15 +17852,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -17883,14 +17880,14 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -17916,13 +17913,13 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0 ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -17942,14 +17939,14 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -17969,15 +17966,15 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -17997,14 +17994,14 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -18030,13 +18027,13 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg) ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -18056,14 +18053,14 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -18083,15 +18080,15 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -18111,14 +18108,14 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg) ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -18144,13 +18141,13 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v1bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v1bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v1bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v1bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -18170,14 +18167,14 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v1bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v1bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -18197,15 +18194,15 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -18225,14 +18222,14 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -18258,13 +18255,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -18284,14 +18281,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -18311,15 +18308,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -18339,14 +18336,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -18372,13 +18369,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -18398,14 +18395,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -18425,15 +18422,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -18453,14 +18450,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -18486,13 +18483,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -18512,14 +18509,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -18539,15 +18536,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -18567,14 +18564,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -18600,13 +18597,13 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -18626,14 +18623,14 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -18653,15 +18650,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -18681,14 +18678,14 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 @@ -18714,13 +18711,13 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16bf16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16bf16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16bf16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16bf16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -18740,14 +18737,14 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16bf16@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16bf16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -18767,15 +18764,15 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -18795,14 +18792,14 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi -; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi +; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2 ; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1 diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll index 124de7e00f020..576b481ca4ccf 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll +++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll @@ -15,19 +15,19 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 4 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s5, 1 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2 +; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_mov_b32 s5, external_void_func_void@abs32@hi ; GFX9-NEXT: s_mov_b32 s4, external_void_func_void@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 3 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s30, v40, 2 +; GFX9-NEXT: v_readlane_b32 s31, v40, 3 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 @@ -51,17 +51,17 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 -; GFX10-NEXT: s_mov_b32 s4, external_void_func_void@abs32@lo ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 -; GFX10-NEXT: s_mov_b32 s5, external_void_func_void@abs32@hi ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 ; GFX10-NEXT: v_writelane_b32 v40, s31, 3 +; GFX10-NEXT: s_mov_b32 s5, external_void_func_void@abs32@hi +; GFX10-NEXT: s_mov_b32 s4, external_void_func_void@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s30, v40, 2 +; GFX10-NEXT: v_readlane_b32 s31, v40, 3 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 @@ -85,18 +85,18 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 -; GFX11-NEXT: s_mov_b32 s4, external_void_func_void@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 -; GFX11-NEXT: s_mov_b32 s5, external_void_func_void@abs32@hi ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 ; GFX11-NEXT: v_writelane_b32 v40, s31, 3 +; GFX11-NEXT: s_mov_b32 s5, external_void_func_void@abs32@hi +; GFX11-NEXT: s_mov_b32 s4, external_void_func_void@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s30, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 3 ; GFX11-NEXT: v_readlane_b32 s5, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -130,8 +130,8 @@ define amdgpu_gfx void @void_func_void_clobber_s28_s29() #1 { ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; clobber ; GFX9-NEXT: ;;#ASMEND -; GFX9-NEXT: v_readlane_b32 s31, v0, 3 ; GFX9-NEXT: v_readlane_b32 s30, v0, 2 +; GFX9-NEXT: v_readlane_b32 s31, v0, 3 ; GFX9-NEXT: v_readlane_b32 s29, v0, 1 ; GFX9-NEXT: v_readlane_b32 s28, v0, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1 @@ -157,8 +157,8 @@ define amdgpu_gfx void @void_func_void_clobber_s28_s29() #1 { ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; clobber ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: v_readlane_b32 s31, v0, 3 ; GFX10-NEXT: v_readlane_b32 s30, v0, 2 +; GFX10-NEXT: v_readlane_b32 s31, v0, 3 ; GFX10-NEXT: v_readlane_b32 s29, v0, 1 ; GFX10-NEXT: v_readlane_b32 s28, v0, 0 ; GFX10-NEXT: s_xor_saveexec_b32 s34, -1 @@ -185,8 +185,8 @@ define amdgpu_gfx void @void_func_void_clobber_s28_s29() #1 { ; GFX11-NEXT: ; clobber ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v0, 3 ; GFX11-NEXT: v_readlane_b32 s30, v0, 2 +; GFX11-NEXT: v_readlane_b32 s31, v0, 3 ; GFX11-NEXT: v_readlane_b32 s29, v0, 1 ; GFX11-NEXT: v_readlane_b32 s28, v0, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 @@ -209,12 +209,12 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1) ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; def s31 ; GFX9-NEXT: ;;#ASMEND @@ -224,8 +224,8 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1) ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; use s31 ; GFX9-NEXT: ;;#ASMEND -; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s30, v40, 1 +; GFX9-NEXT: v_readlane_b32 s31, v40, 2 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -246,12 +246,12 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def s31 ; GFX10-NEXT: ;;#ASMEND @@ -261,8 +261,8 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1) ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use s31 ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s30, v40, 1 +; GFX10-NEXT: v_readlane_b32 s31, v40, 2 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -283,12 +283,12 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s31 ; GFX11-NEXT: ;;#ASMEND @@ -298,8 +298,8 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1) ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s31 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s30, v40, 1 +; GFX11-NEXT: v_readlane_b32 s31, v40, 2 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -325,12 +325,12 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1) ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v41, s34, 2 -; GFX9-NEXT: v_writelane_b32 v41, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v41, s30, 0 ; GFX9-NEXT: v_writelane_b32 v41, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; def v31 ; GFX9-NEXT: ;;#ASMEND @@ -341,8 +341,8 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1) ; GFX9-NEXT: ; use v31 ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v41, 1 ; GFX9-NEXT: v_readlane_b32 s30, v41, 0 +; GFX9-NEXT: v_readlane_b32 s31, v41, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v41, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -362,24 +362,24 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v41, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: v_writelane_b32 v41, s30, 0 +; GFX10-NEXT: v_writelane_b32 v41, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def v31 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: v_mov_b32_e32 v40, v31 -; GFX10-NEXT: v_writelane_b32 v41, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_mov_b32_e32 v31, v40 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use v31 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GFX10-NEXT: v_readlane_b32 s31, v41, 1 ; GFX10-NEXT: v_readlane_b32 s30, v41, 0 +; GFX10-NEXT: v_readlane_b32 s31, v41, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v41, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -399,25 +399,25 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1) ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v41, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: v_writelane_b32 v41, s30, 0 +; GFX11-NEXT: v_writelane_b32 v41, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def v31 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: v_mov_b32_e32 v40, v31 -; GFX11-NEXT: v_writelane_b32 v41, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v31, v40 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use v31 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload -; GFX11-NEXT: v_readlane_b32 s31, v41, 1 ; GFX11-NEXT: v_readlane_b32 s30, v41, 0 +; GFX11-NEXT: v_readlane_b32 s31, v41, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v41, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -443,23 +443,23 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1) ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; def s33 ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: s_mov_b32 s4, s33 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX9-NEXT: s_mov_b32 s33, s4 +; GFX9-NEXT: v_readlane_b32 s30, v40, 1 ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; use s33 ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: v_readlane_b32 s31, v40, 2 -; GFX9-NEXT: v_readlane_b32 s30, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -480,23 +480,23 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: v_writelane_b32 v40, s30, 1 +; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def s33 ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s4, s33 -; GFX10-NEXT: v_writelane_b32 v40, s30, 1 -; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: s_mov_b32 s33, s4 +; GFX10-NEXT: v_readlane_b32 s30, v40, 1 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use s33 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: v_readlane_b32 s31, v40, 2 -; GFX10-NEXT: v_readlane_b32 s30, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -517,24 +517,23 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: v_writelane_b32 v40, s30, 1 +; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s33 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s4, s33 -; GFX11-NEXT: v_writelane_b32 v40, s30, 1 -; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_mov_b32 s33, s4 +; GFX11-NEXT: v_readlane_b32 s30, v40, 1 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s33 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_readlane_b32 s31, v40, 2 -; GFX11-NEXT: v_readlane_b32 s30, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -560,23 +559,23 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1) ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 +; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; def s34 ; GFX9-NEXT: ;;#ASMEND -; GFX9-NEXT: v_writelane_b32 v40, s30, 1 ; GFX9-NEXT: s_mov_b32 s4, s34 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX9-NEXT: s_mov_b32 s34, s4 +; GFX9-NEXT: v_readlane_b32 s30, v40, 1 ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; use s34 ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: v_readlane_b32 s31, v40, 2 -; GFX9-NEXT: v_readlane_b32 s30, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -597,23 +596,23 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: v_writelane_b32 v40, s30, 1 +; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def s34 ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi -; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s4, s34 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s30, 1 -; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: s_mov_b32 s34, s4 +; GFX10-NEXT: v_readlane_b32 s30, v40, 1 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use s34 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: v_readlane_b32 s31, v40, 2 -; GFX10-NEXT: v_readlane_b32 s30, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -634,24 +633,23 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: v_writelane_b32 v40, s30, 1 +; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s34 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s4, s34 -; GFX11-NEXT: v_writelane_b32 v40, s30, 1 -; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: v_readlane_b32 s30, v40, 1 ; GFX11-NEXT: s_mov_b32 s34, s4 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s34 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_readlane_b32 s31, v40, 2 -; GFX11-NEXT: v_readlane_b32 s30, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -677,12 +675,12 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1) ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v41, s34, 2 -; GFX9-NEXT: v_writelane_b32 v41, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v41, s30, 0 ; GFX9-NEXT: v_writelane_b32 v41, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; def v40 ; GFX9-NEXT: ;;#ASMEND @@ -691,8 +689,8 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1) ; GFX9-NEXT: ; use v40 ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v41, 1 ; GFX9-NEXT: v_readlane_b32 s30, v41, 0 +; GFX9-NEXT: v_readlane_b32 s31, v41, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v41, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -712,22 +710,22 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v41, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: v_writelane_b32 v41, s30, 0 +; GFX10-NEXT: v_writelane_b32 v41, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def v40 ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: v_writelane_b32 v41, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use v40 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GFX10-NEXT: v_readlane_b32 s31, v41, 1 ; GFX10-NEXT: v_readlane_b32 s30, v41, 0 +; GFX10-NEXT: v_readlane_b32 s31, v41, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v41, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -747,22 +745,22 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1) ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v41, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: v_writelane_b32 v41, s30, 0 +; GFX11-NEXT: v_writelane_b32 v41, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def v40 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_writelane_b32 v41, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use v40 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload -; GFX11-NEXT: v_readlane_b32 s31, v41, 1 ; GFX11-NEXT: v_readlane_b32 s30, v41, 0 +; GFX11-NEXT: v_readlane_b32 s31, v41, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v41, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -844,13 +842,13 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, void_func_void_clobber_s33@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, void_func_void_clobber_s33@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, void_func_void_clobber_s33@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, void_func_void_clobber_s33@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -870,14 +868,14 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s33@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, void_func_void_clobber_s33@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s33@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, void_func_void_clobber_s33@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -897,15 +895,15 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, void_func_void_clobber_s33@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, void_func_void_clobber_s33@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, void_func_void_clobber_s33@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, void_func_void_clobber_s33@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -929,13 +927,13 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 { ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, void_func_void_clobber_s34@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, void_func_void_clobber_s34@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, void_func_void_clobber_s34@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, void_func_void_clobber_s34@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -955,14 +953,14 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s34@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, void_func_void_clobber_s34@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s34@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, void_func_void_clobber_s34@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 +; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 2 ; GFX10-NEXT: s_or_saveexec_b32 s35, -1 @@ -982,15 +980,15 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: s_mov_b32 s1, void_func_void_clobber_s34@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, void_func_void_clobber_s34@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, void_func_void_clobber_s34@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, void_func_void_clobber_s34@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -1013,22 +1011,22 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 { ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v40, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s4, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 1 +; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 2 ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; def s40 ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: s_mov_b32 s4, s40 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] +; GFX9-NEXT: v_readlane_b32 s30, v40, 1 ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; use s4 ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: v_readlane_b32 s31, v40, 2 -; GFX9-NEXT: v_readlane_b32 s30, v40, 1 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v40, 3 @@ -1049,22 +1047,22 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: v_writelane_b32 v40, s30, 1 +; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def s40 ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s4, s40 -; GFX10-NEXT: v_writelane_b32 v40, s30, 1 -; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] +; GFX10-NEXT: v_readlane_b32 s30, v40, 1 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use s4 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: v_readlane_b32 s31, v40, 2 -; GFX10-NEXT: v_readlane_b32 s30, v40, 1 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v40, 3 @@ -1085,23 +1083,22 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 +; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: v_writelane_b32 v40, s30, 1 +; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s40 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s4, s40 -; GFX11-NEXT: v_writelane_b32 v40, s30, 1 -; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: v_readlane_b32 s30, v40, 1 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s4 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_readlane_b32 s31, v40, 2 -; GFX11-NEXT: v_readlane_b32 s30, v40, 1 ; GFX11-NEXT: v_readlane_b32 s4, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v40, 3 @@ -1127,13 +1124,13 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-NEXT: v_writelane_b32 v41, s34, 3 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: v_writelane_b32 v41, s4, 0 ; GFX9-NEXT: v_writelane_b32 v41, s30, 1 +; GFX9-NEXT: v_writelane_b32 v41, s31, 2 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GFX9-NEXT: v_writelane_b32 v41, s31, 2 ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ; def s40 ; GFX9-NEXT: ;;#ASMEND @@ -1150,8 +1147,8 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX9-NEXT: ; use v40 ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v41, 2 ; GFX9-NEXT: v_readlane_b32 s30, v41, 1 +; GFX9-NEXT: v_readlane_b32 s31, v41, 2 ; GFX9-NEXT: v_readlane_b32 s4, v41, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s34, v41, 3 @@ -1172,11 +1169,13 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v41, s34, 3 -; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: v_writelane_b32 v41, s4, 0 +; GFX10-NEXT: v_writelane_b32 v41, s30, 1 +; GFX10-NEXT: v_writelane_b32 v41, s31, 2 +; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def s40 ; GFX10-NEXT: ;;#ASMEND @@ -1185,8 +1184,6 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX10-NEXT: ; def v32 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: v_mov_b32_e32 v40, v32 -; GFX10-NEXT: v_writelane_b32 v41, s30, 1 -; GFX10-NEXT: v_writelane_b32 v41, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use s4 @@ -1195,8 +1192,8 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX10-NEXT: ; use v40 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload -; GFX10-NEXT: v_readlane_b32 s31, v41, 2 ; GFX10-NEXT: v_readlane_b32 s30, v41, 1 +; GFX10-NEXT: v_readlane_b32 s31, v41, 2 ; GFX10-NEXT: v_readlane_b32 s4, v41, 0 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s34, v41, 3 @@ -1217,11 +1214,13 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v41, s0, 3 -; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: v_writelane_b32 v41, s4, 0 +; GFX11-NEXT: v_writelane_b32 v41, s30, 1 +; GFX11-NEXT: v_writelane_b32 v41, s31, 2 +; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s40 ; GFX11-NEXT: ;;#ASMEND @@ -1230,8 +1229,6 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX11-NEXT: ; def v32 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: v_mov_b32_e32 v40, v32 -; GFX11-NEXT: v_writelane_b32 v41, s30, 1 -; GFX11-NEXT: v_writelane_b32 v41, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s4 @@ -1240,8 +1237,8 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX11-NEXT: ; use v40 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload -; GFX11-NEXT: v_readlane_b32 s31, v41, 2 ; GFX11-NEXT: v_readlane_b32 s30, v41, 1 +; GFX11-NEXT: v_readlane_b32 s31, v41, 2 ; GFX11-NEXT: v_readlane_b32 s4, v41, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v41, 3 diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll index b750d28ffa7d3..891c6e37185d3 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll +++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll @@ -29,13 +29,13 @@ define amdgpu_gfx void @call_i1() #0 { ; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[34:35] ; GFX9-NEXT: v_writelane_b32 v1, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, return_i1@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, return_i1@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v1, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, return_i1@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, return_i1@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v1, 1 ; GFX9-NEXT: v_readlane_b32 s30, v1, 0 +; GFX9-NEXT: v_readlane_b32 s31, v1, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload @@ -54,13 +54,13 @@ define amdgpu_gfx void @call_i1() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s34 ; GFX10-NEXT: v_writelane_b32 v1, s30, 0 -; GFX10-NEXT: s_mov_b32 s35, return_i1@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, return_i1@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v1, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, return_i1@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, return_i1@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v1, 1 ; GFX10-NEXT: v_readlane_b32 s30, v1, 0 +; GFX10-NEXT: v_readlane_b32 s31, v1, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s34, -1 ; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload @@ -79,14 +79,14 @@ define amdgpu_gfx void @call_i1() #0 { ; GFX11-NEXT: scratch_store_b32 off, v1, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: v_writelane_b32 v1, s30, 0 -; GFX11-NEXT: s_mov_b32 s1, return_i1@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, return_i1@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v1, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, return_i1@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, return_i1@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v1, 1 ; GFX11-NEXT: v_readlane_b32 s30, v1, 0 +; GFX11-NEXT: v_readlane_b32 s31, v1, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v1, off, s33 ; 4-byte Folded Reload @@ -131,13 +131,13 @@ define amdgpu_gfx void @call_i16() #0 { ; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[34:35] ; GFX9-NEXT: v_writelane_b32 v1, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, return_i16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, return_i16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v1, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, return_i16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, return_i16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v1, 1 ; GFX9-NEXT: v_readlane_b32 s30, v1, 0 +; GFX9-NEXT: v_readlane_b32 s31, v1, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload @@ -156,13 +156,13 @@ define amdgpu_gfx void @call_i16() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s34 ; GFX10-NEXT: v_writelane_b32 v1, s30, 0 -; GFX10-NEXT: s_mov_b32 s35, return_i16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, return_i16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v1, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, return_i16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, return_i16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v1, 1 ; GFX10-NEXT: v_readlane_b32 s30, v1, 0 +; GFX10-NEXT: v_readlane_b32 s31, v1, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s34, -1 ; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload @@ -181,14 +181,14 @@ define amdgpu_gfx void @call_i16() #0 { ; GFX11-NEXT: scratch_store_b32 off, v1, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: v_writelane_b32 v1, s30, 0 -; GFX11-NEXT: s_mov_b32 s1, return_i16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, return_i16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v1, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, return_i16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, return_i16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v1, 1 ; GFX11-NEXT: v_readlane_b32 s30, v1, 0 +; GFX11-NEXT: v_readlane_b32 s31, v1, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v1, off, s33 ; 4-byte Folded Reload @@ -227,13 +227,13 @@ define amdgpu_gfx void @call_2xi16() #0 { ; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[34:35] ; GFX9-NEXT: v_writelane_b32 v1, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, return_2xi16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, return_2xi16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v1, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, return_2xi16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, return_2xi16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v1, 1 ; GFX9-NEXT: v_readlane_b32 s30, v1, 0 +; GFX9-NEXT: v_readlane_b32 s31, v1, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload @@ -252,13 +252,13 @@ define amdgpu_gfx void @call_2xi16() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s34 ; GFX10-NEXT: v_writelane_b32 v1, s30, 0 -; GFX10-NEXT: s_mov_b32 s35, return_2xi16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, return_2xi16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v1, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, return_2xi16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, return_2xi16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v1, 1 ; GFX10-NEXT: v_readlane_b32 s30, v1, 0 +; GFX10-NEXT: v_readlane_b32 s31, v1, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s34, -1 ; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload @@ -277,14 +277,14 @@ define amdgpu_gfx void @call_2xi16() #0 { ; GFX11-NEXT: scratch_store_b32 off, v1, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: v_writelane_b32 v1, s30, 0 -; GFX11-NEXT: s_mov_b32 s1, return_2xi16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, return_2xi16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v1, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, return_2xi16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, return_2xi16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v1, 1 ; GFX11-NEXT: v_readlane_b32 s30, v1, 0 +; GFX11-NEXT: v_readlane_b32 s31, v1, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v1, off, s33 ; 4-byte Folded Reload @@ -331,13 +331,13 @@ define amdgpu_gfx void @call_3xi16() #0 { ; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[34:35] ; GFX9-NEXT: v_writelane_b32 v2, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, return_3xi16@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, return_3xi16@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v2, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, return_3xi16@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, return_3xi16@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX9-NEXT: v_readlane_b32 s31, v2, 1 ; GFX9-NEXT: v_readlane_b32 s30, v2, 0 +; GFX9-NEXT: v_readlane_b32 s31, v2, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -356,13 +356,13 @@ define amdgpu_gfx void @call_3xi16() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s34 ; GFX10-NEXT: v_writelane_b32 v2, s30, 0 -; GFX10-NEXT: s_mov_b32 s35, return_3xi16@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, return_3xi16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v2, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, return_3xi16@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, return_3xi16@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] -; GFX10-NEXT: v_readlane_b32 s31, v2, 1 ; GFX10-NEXT: v_readlane_b32 s30, v2, 0 +; GFX10-NEXT: v_readlane_b32 s31, v2, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s34, -1 ; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -381,14 +381,14 @@ define amdgpu_gfx void @call_3xi16() #0 { ; GFX11-NEXT: scratch_store_b32 off, v2, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: v_writelane_b32 v2, s30, 0 -; GFX11-NEXT: s_mov_b32 s1, return_3xi16@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, return_3xi16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v2, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, return_3xi16@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, return_3xi16@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v2, 1 ; GFX11-NEXT: v_readlane_b32 s30, v2, 0 +; GFX11-NEXT: v_readlane_b32 s31, v2, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v2, off, s33 ; 4-byte Folded Reload @@ -680,9 +680,6 @@ define amdgpu_gfx void @call_100xi32() #0 { ; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GFX9-NEXT: buffer_store_dword v100, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[34:35] -; GFX9-NEXT: v_writelane_b32 v100, s30, 0 -; GFX9-NEXT: s_mov_b32 s35, return_100xi32@abs32@hi -; GFX9-NEXT: s_mov_b32 s34, return_100xi32@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x2400 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill @@ -716,7 +713,10 @@ define amdgpu_gfx void @call_100xi32() #0 { ; GFX9-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v95, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v100, s30, 0 ; GFX9-NEXT: v_writelane_b32 v100, s31, 1 +; GFX9-NEXT: s_mov_b32 s35, return_100xi32@abs32@hi +; GFX9-NEXT: s_mov_b32 s34, return_100xi32@abs32@lo ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX9-NEXT: buffer_load_dword v95, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v94, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload @@ -750,8 +750,8 @@ define amdgpu_gfx void @call_100xi32() #0 { ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:116 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:120 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:124 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v100, 1 ; GFX9-NEXT: v_readlane_b32 s30, v100, 0 +; GFX9-NEXT: v_readlane_b32 s31, v100, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GFX9-NEXT: buffer_load_dword v100, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload @@ -769,9 +769,6 @@ define amdgpu_gfx void @call_100xi32() #0 { ; GFX10-NEXT: buffer_store_dword v100, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s34 -; GFX10-NEXT: v_writelane_b32 v100, s30, 0 -; GFX10-NEXT: s_mov_b32 s35, return_100xi32@abs32@hi -; GFX10-NEXT: s_mov_b32 s34, return_100xi32@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x1200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill @@ -805,7 +802,10 @@ define amdgpu_gfx void @call_100xi32() #0 { ; GFX10-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v95, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v100, s30, 0 ; GFX10-NEXT: v_writelane_b32 v100, s31, 1 +; GFX10-NEXT: s_mov_b32 s35, return_100xi32@abs32@hi +; GFX10-NEXT: s_mov_b32 s34, return_100xi32@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: s_clause 0x1f ; GFX10-NEXT: buffer_load_dword v95, off, s[0:3], s33 @@ -840,8 +840,8 @@ define amdgpu_gfx void @call_100xi32() #0 { ; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:116 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:120 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:124 -; GFX10-NEXT: v_readlane_b32 s31, v100, 1 ; GFX10-NEXT: v_readlane_b32 s30, v100, 0 +; GFX10-NEXT: v_readlane_b32 s31, v100, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: s_xor_saveexec_b32 s34, -1 ; GFX10-NEXT: buffer_load_dword v100, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload @@ -859,44 +859,76 @@ define amdgpu_gfx void @call_100xi32() #0 { ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v100, s33 offset:128 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-NEXT: v_writelane_b32 v100, s30, 0 -; GFX11-NEXT: s_mov_b32 s1, return_100xi32@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, return_100xi32@abs32@lo ; GFX11-NEXT: s_addk_i32 s32, 0x90 ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:124 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:120 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:116 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s33 offset:112 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s33 offset:108 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s33 offset:104 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s33 offset:100 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s33 offset:96 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s33 offset:92 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s33 offset:88 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s33 offset:84 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s33 offset:80 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s33 offset:76 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s33 offset:72 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s33 offset:68 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s33 offset:64 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v72, s33 offset:60 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v73, s33 offset:56 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v74, s33 offset:52 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v75, s33 offset:48 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s33 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s33 offset:40 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s33 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s33 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v88, s33 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v89, s33 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v90, s33 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v91, s33 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v92, s33 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v93, s33 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v94, s33 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v95, s33 +; GFX11-NEXT: v_writelane_b32 v100, s30, 0 ; GFX11-NEXT: v_writelane_b32 v100, s31, 1 +; GFX11-NEXT: s_mov_b32 s1, return_100xi32@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, return_100xi32@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_clause 0x1f ; GFX11-NEXT: scratch_load_b32 v95, off, s33 @@ -931,8 +963,8 @@ define amdgpu_gfx void @call_100xi32() #0 { ; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:116 ; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:120 ; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:124 -; GFX11-NEXT: v_readlane_b32 s31, v100, 1 ; GFX11-NEXT: v_readlane_b32 s30, v100, 0 +; GFX11-NEXT: v_readlane_b32 s31, v100, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v100, off, s33 offset:128 ; 4-byte Folded Reload @@ -2142,17 +2174,17 @@ define amdgpu_gfx void @call_512xi32() #0 { ; GFX9-NEXT: s_xor_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:2048 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v2, s30, 0 -; GFX9-NEXT: s_mov_b32 s37, return_512xi32@abs32@hi -; GFX9-NEXT: s_mov_b32 s36, return_512xi32@abs32@lo -; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33 ; GFX9-NEXT: s_mov_b32 s38, s34 ; GFX9-NEXT: s_mov_b32 s34, s32 +; GFX9-NEXT: v_writelane_b32 v2, s30, 0 ; GFX9-NEXT: s_add_i32 s32, s32, 0x60000 ; GFX9-NEXT: v_writelane_b32 v2, s31, 1 +; GFX9-NEXT: s_mov_b32 s37, return_512xi32@abs32@hi +; GFX9-NEXT: s_mov_b32 s36, return_512xi32@abs32@lo +; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[36:37] -; GFX9-NEXT: v_readlane_b32 s31, v2, 1 ; GFX9-NEXT: v_readlane_b32 s30, v2, 0 +; GFX9-NEXT: v_readlane_b32 s31, v2, 1 ; GFX9-NEXT: s_mov_b32 s32, s34 ; GFX9-NEXT: s_mov_b32 s34, s38 ; GFX9-NEXT: s_xor_saveexec_b64 s[36:37], -1 @@ -2172,17 +2204,17 @@ define amdgpu_gfx void @call_512xi32() #0 { ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:2048 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s36 -; GFX10-NEXT: v_writelane_b32 v2, s30, 0 -; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33 -; GFX10-NEXT: s_mov_b32 s37, return_512xi32@abs32@hi -; GFX10-NEXT: s_mov_b32 s36, return_512xi32@abs32@lo ; GFX10-NEXT: s_mov_b32 s38, s34 ; GFX10-NEXT: s_mov_b32 s34, s32 +; GFX10-NEXT: v_writelane_b32 v2, s30, 0 ; GFX10-NEXT: s_add_i32 s32, s32, 0x30000 ; GFX10-NEXT: v_writelane_b32 v2, s31, 1 +; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33 +; GFX10-NEXT: s_mov_b32 s37, return_512xi32@abs32@hi +; GFX10-NEXT: s_mov_b32 s36, return_512xi32@abs32@lo ; GFX10-NEXT: s_swappc_b64 s[30:31], s[36:37] -; GFX10-NEXT: v_readlane_b32 s31, v2, 1 ; GFX10-NEXT: v_readlane_b32 s30, v2, 0 +; GFX10-NEXT: v_readlane_b32 s31, v2, 1 ; GFX10-NEXT: s_mov_b32 s32, s34 ; GFX10-NEXT: s_mov_b32 s34, s38 ; GFX10-NEXT: s_xor_saveexec_b32 s36, -1 @@ -2203,18 +2235,18 @@ define amdgpu_gfx void @call_512xi32() #0 { ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v5, s33 offset:2048 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-NEXT: v_writelane_b32 v5, s30, 0 -; GFX11-NEXT: v_mov_b32_e32 v0, s33 -; GFX11-NEXT: s_mov_b32 s1, return_512xi32@abs32@hi -; GFX11-NEXT: s_mov_b32 s0, return_512xi32@abs32@lo ; GFX11-NEXT: s_mov_b32 s36, s34 ; GFX11-NEXT: s_mov_b32 s34, s32 +; GFX11-NEXT: v_writelane_b32 v5, s30, 0 ; GFX11-NEXT: s_addk_i32 s32, 0x1800 ; GFX11-NEXT: v_writelane_b32 v5, s31, 1 +; GFX11-NEXT: v_mov_b32_e32 v0, s33 +; GFX11-NEXT: s_mov_b32 s1, return_512xi32@abs32@hi +; GFX11-NEXT: s_mov_b32 s0, return_512xi32@abs32@lo +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v5, 1 ; GFX11-NEXT: v_readlane_b32 s30, v5, 0 +; GFX11-NEXT: v_readlane_b32 s31, v5, 1 ; GFX11-NEXT: s_mov_b32 s32, s34 ; GFX11-NEXT: s_mov_b32 s34, s36 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 @@ -2520,17 +2552,29 @@ define amdgpu_gfx <72 x i32> @return_72xi32(<72 x i32> %val) #1 { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_clause 0xc ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:212 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:208 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:204 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:200 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:196 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:192 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:188 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:184 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:180 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:176 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:172 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:168 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:164 ; GFX11-NEXT: s_clause 0x11 ; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:16 @@ -2640,7 +2684,6 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX9-NEXT: s_mov_b32 s38, s34 ; GFX9-NEXT: s_mov_b32 s34, s32 ; GFX9-NEXT: s_add_i32 s32, s32, 0x28000 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill @@ -2656,6 +2699,9 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v63, s30, 0 +; GFX9-NEXT: v_writelane_b32 v63, s31, 1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 @@ -2698,7 +2744,6 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33 -; GFX9-NEXT: v_writelane_b32 v63, s30, 0 ; GFX9-NEXT: s_mov_b32 s37, return_72xi32@abs32@hi ; GFX9-NEXT: s_mov_b32 s36, return_72xi32@abs32@lo ; GFX9-NEXT: v_add_u32_e32 v0, 0x200, v0 @@ -2733,7 +2778,6 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX9-NEXT: v_mov_b32_e32 v29, 0 ; GFX9-NEXT: v_mov_b32_e32 v30, 0 ; GFX9-NEXT: v_mov_b32_e32 v31, 0 -; GFX9-NEXT: v_writelane_b32 v63, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[36:37] ; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:636 ; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:640 @@ -2889,8 +2933,8 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v63, 1 ; GFX9-NEXT: v_readlane_b32 s30, v63, 0 +; GFX9-NEXT: v_readlane_b32 s31, v63, 1 ; GFX9-NEXT: s_mov_b32 s32, s34 ; GFX9-NEXT: s_mov_b32 s34, s38 ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 @@ -2910,7 +2954,6 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX10-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:1568 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s36 -; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: s_mov_b32 s38, s34 ; GFX10-NEXT: s_mov_b32 s34, s32 ; GFX10-NEXT: s_add_i32 s32, s32, 0x14000 @@ -2929,6 +2972,13 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX10-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v62, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v63, s30, 0 +; GFX10-NEXT: v_writelane_b32 v63, s31, 1 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-NEXT: v_mov_b32_e32 v3, 0 +; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 @@ -2971,16 +3021,11 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33 -; GFX10-NEXT: v_writelane_b32 v63, s30, 0 -; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-NEXT: v_mov_b32_e32 v3, 0 -; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x200, v0 -; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0 ; GFX10-NEXT: v_mov_b32_e32 v6, 0 ; GFX10-NEXT: v_mov_b32_e32 v7, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0 +; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x200, v0 ; GFX10-NEXT: v_mov_b32_e32 v9, 0 ; GFX10-NEXT: v_mov_b32_e32 v10, 0 ; GFX10-NEXT: v_mov_b32_e32 v11, 0 @@ -3006,7 +3051,6 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX10-NEXT: v_mov_b32_e32 v31, 0 ; GFX10-NEXT: s_mov_b32 s37, return_72xi32@abs32@hi ; GFX10-NEXT: s_mov_b32 s36, return_72xi32@abs32@lo -; GFX10-NEXT: v_writelane_b32 v63, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[36:37] ; GFX10-NEXT: s_clause 0x28 ; GFX10-NEXT: buffer_load_dword v9, off, s[0:3], s33 offset:636 @@ -3167,8 +3211,8 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:48 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:52 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:56 -; GFX10-NEXT: v_readlane_b32 s31, v63, 1 ; GFX10-NEXT: v_readlane_b32 s30, v63, 0 +; GFX10-NEXT: v_readlane_b32 s31, v63, 1 ; GFX10-NEXT: s_mov_b32 s32, s34 ; GFX10-NEXT: s_mov_b32 s34, s38 ; GFX10-NEXT: s_or_saveexec_b32 s36, -1 @@ -3189,29 +3233,42 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v60, s33 offset:1600 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-NEXT: s_mov_b32 s0, 0 -; GFX11-NEXT: v_mov_b32_e32 v4, 0 -; GFX11-NEXT: s_mov_b32 s1, s0 -; GFX11-NEXT: s_mov_b32 s2, s0 -; GFX11-NEXT: s_mov_b32 s3, s0 -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-NEXT: s_mov_b32 s36, s34 ; GFX11-NEXT: s_mov_b32 s34, s32 ; GFX11-NEXT: s_addk_i32 s32, 0xa00 ; GFX11-NEXT: s_clause 0xb ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:44 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:40 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:36 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s33 offset:32 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s33 offset:28 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v45, s33 offset:24 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v46, s33 offset:20 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v47, s33 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v56, s33 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v57, s33 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v58, s33 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v59, s33 +; GFX11-NEXT: v_writelane_b32 v60, s30, 0 +; GFX11-NEXT: v_writelane_b32 v60, s31, 1 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-NEXT: s_mov_b32 s1, s0 +; GFX11-NEXT: s_mov_b32 s2, s0 +; GFX11-NEXT: s_mov_b32 s3, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-NEXT: s_add_i32 s0, s32, 0xa0 ; GFX11-NEXT: s_add_i32 s1, s32, 0x90 ; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32 @@ -3232,7 +3289,6 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX11-NEXT: s_add_i32 s0, s32, 32 ; GFX11-NEXT: s_add_i32 s1, s32, 16 ; GFX11-NEXT: s_add_i32 s2, s33, 0x200 -; GFX11-NEXT: v_writelane_b32 v60, s30, 0 ; GFX11-NEXT: scratch_store_b128 off, v[0:3], s0 ; GFX11-NEXT: scratch_store_b128 off, v[0:3], s1 ; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, 0 @@ -3253,7 +3309,7 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX11-NEXT: v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v30, 0 ; GFX11-NEXT: s_mov_b32 s1, return_72xi32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, return_72xi32@abs32@lo -; GFX11-NEXT: v_writelane_b32 v60, s31, 1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: scratch_load_b128 v[45:48], off, s33 offset:624 @@ -3365,8 +3421,8 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:36 ; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:40 ; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:44 -; GFX11-NEXT: v_readlane_b32 s31, v60, 1 ; GFX11-NEXT: v_readlane_b32 s30, v60, 0 +; GFX11-NEXT: v_readlane_b32 s31, v60, 1 ; GFX11-NEXT: s_mov_b32 s32, s34 ; GFX11-NEXT: s_mov_b32 s34, s36 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 diff --git a/llvm/test/CodeGen/AMDGPU/global-alias.ll b/llvm/test/CodeGen/AMDGPU/global-alias.ll index d8df20eb69452..4c7bef4aec091 100644 --- a/llvm/test/CodeGen/AMDGPU/global-alias.ll +++ b/llvm/test/CodeGen/AMDGPU/global-alias.ll @@ -35,8 +35,8 @@ define void @bar() { ; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] -; CHECK-NEXT: v_readlane_b32 s31, v40, 1 ; CHECK-NEXT: v_readlane_b32 s30, v40, 0 +; CHECK-NEXT: v_readlane_b32 s31, v40, 1 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: v_readlane_b32 s4, v40, 2 ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll index cd46747370ad1..de4a8502fc93d 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll @@ -1,12 +1,7 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=CHECK %s - ; CHECK: amdhsa.kernels: ; CHECK-NEXT: - .args: ; CHECK-NEXT: - .address_space: global @@ -81,7 +76,7 @@ ; CHECK-NEXT: - .offset: 136 ; CHECK-NEXT: .size: 8 ; CHECK-NEXT: .value_kind: hidden_completion_action -; CHECK: - .offset: 144 +; CHECK-NEXT: - .offset: 144 ; CHECK-NEXT: .size: 4 ; CHECK-NEXT: .value_kind: hidden_dynamic_lds_size ; CHECK: - .offset: 224 @@ -121,4 +116,3 @@ entry: !2 = !{!"2:1:8:%g\5Cn"} attributes #0 = { optnone noinline } - diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll index 2fe96975bb92e..c45a2cd47f5c5 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll @@ -1,12 +1,7 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=CHECK %s - ; CHECK: amdhsa.kernels: ; CHECK-NEXT: - .args: ; CHECK-NEXT: - .address_space: global @@ -81,7 +76,7 @@ ; CHECK-NEXT: - .offset: 136 ; CHECK-NEXT: .size: 8 ; CHECK-NEXT: .value_kind: hidden_completion_action -; CHECK: - .offset: 144 +; CHECK-NEXT: - .offset: 144 ; CHECK-NEXT: .size: 4 ; CHECK-NEXT: .value_kind: hidden_dynamic_lds_size ; CHECK: - .offset: 224 @@ -121,4 +116,3 @@ entry: !2 = !{!"2:1:8:%g\5Cn"} attributes #0 = { optnone noinline } - diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll index b3ed362052bb4..3a330ba92cfd4 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll @@ -1,12 +1,7 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=CHECK %s - ; CHECK: amdhsa.kernels: ; CHECK-NEXT: - .args: ; CHECK-NEXT: - .address_space: global @@ -87,7 +82,7 @@ ; CHECK-NEXT: - .offset: 144 ; CHECK-NEXT: .size: 8 ; CHECK-NEXT: .value_kind: hidden_completion_action -; CHECK: - .offset: 152 +; CHECK-NEXT: - .offset: 152 ; CHECK-NEXT: .size: 4 ; CHECK-NEXT: .value_kind: hidden_dynamic_lds_size ; CHECK: - .offset: 232 diff --git a/llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll b/llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll index e10f050b8e7a6..0c635e41cccac 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll @@ -81,7 +81,7 @@ ; CHECK-NEXT: - .offset: 136 ; CHECK-NEXT: .size: 8 ; CHECK-NEXT: .value_kind: hidden_completion_action -; CHECK: - .offset: 144 +; CHECK-NEXT: - .offset: 144 ; CHECK-NEXT: .size: 4 ; CHECK-NEXT: .value_kind: hidden_dynamic_lds_size ; GFX8-NEXT: - .offset: 216 @@ -121,4 +121,3 @@ entry: !2 = !{!"2:1:8:%g\5Cn"} attributes #0 = { optnone noinline } - diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll index 10d61deed71cc..424aaaea11722 100644 --- a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll +++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll @@ -9,28 +9,30 @@ define void @main(i1 %arg) #0 { ; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[4:5] -; CHECK-NEXT: v_writelane_b32 v6, s30, 0 -; CHECK-NEXT: v_writelane_b32 v6, s31, 1 -; CHECK-NEXT: v_writelane_b32 v6, s36, 2 -; CHECK-NEXT: v_writelane_b32 v6, s37, 3 -; CHECK-NEXT: v_writelane_b32 v6, s38, 4 -; CHECK-NEXT: v_writelane_b32 v6, s39, 5 -; CHECK-NEXT: v_writelane_b32 v6, s48, 6 -; CHECK-NEXT: v_writelane_b32 v6, s49, 7 -; CHECK-NEXT: v_writelane_b32 v6, s50, 8 -; CHECK-NEXT: v_writelane_b32 v6, s51, 9 -; CHECK-NEXT: v_writelane_b32 v6, s52, 10 -; CHECK-NEXT: v_writelane_b32 v6, s53, 11 -; CHECK-NEXT: v_writelane_b32 v6, s54, 12 -; CHECK-NEXT: v_writelane_b32 v6, s55, 13 -; CHECK-NEXT: v_writelane_b32 v6, s64, 14 -; CHECK-NEXT: v_writelane_b32 v6, s65, 15 -; CHECK-NEXT: v_writelane_b32 v6, s66, 16 -; CHECK-NEXT: v_writelane_b32 v6, s67, 17 -; CHECK-NEXT: v_writelane_b32 v6, s68, 18 +; CHECK-NEXT: v_writelane_b32 v6, s36, 0 +; CHECK-NEXT: v_writelane_b32 v6, s37, 1 +; CHECK-NEXT: v_writelane_b32 v6, s38, 2 +; CHECK-NEXT: v_writelane_b32 v6, s39, 3 +; CHECK-NEXT: v_writelane_b32 v6, s48, 4 +; CHECK-NEXT: v_writelane_b32 v6, s49, 5 +; CHECK-NEXT: v_writelane_b32 v6, s50, 6 +; CHECK-NEXT: v_writelane_b32 v6, s51, 7 +; CHECK-NEXT: v_writelane_b32 v6, s52, 8 +; CHECK-NEXT: v_writelane_b32 v6, s53, 9 +; CHECK-NEXT: v_writelane_b32 v6, s54, 10 +; CHECK-NEXT: v_writelane_b32 v6, s55, 11 +; CHECK-NEXT: v_writelane_b32 v6, s64, 12 +; CHECK-NEXT: v_writelane_b32 v6, s65, 13 +; CHECK-NEXT: v_writelane_b32 v6, s66, 14 +; CHECK-NEXT: v_writelane_b32 v6, s67, 15 +; CHECK-NEXT: v_writelane_b32 v6, s68, 16 +; CHECK-NEXT: v_writelane_b32 v6, s69, 17 +; CHECK-NEXT: v_writelane_b32 v6, s70, 18 +; CHECK-NEXT: v_writelane_b32 v6, s71, 19 +; CHECK-NEXT: v_writelane_b32 v6, s30, 20 +; CHECK-NEXT: v_writelane_b32 v6, s31, 21 ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_mov_b64 s[8:9], 0 -; CHECK-NEXT: v_writelane_b32 v6, s69, 19 ; CHECK-NEXT: s_mov_b32 s68, 0 ; CHECK-NEXT: s_mov_b32 s69, s4 ; CHECK-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x0 @@ -40,11 +42,11 @@ define void @main(i1 %arg) #0 { ; CHECK-NEXT: s_nop 0 ; CHECK-NEXT: s_load_dwordx16 s[8:23], s[68:69], 0x130 ; CHECK-NEXT: ; implicit-def: $vgpr7 : SGPR spill to VGPR lane -; CHECK-NEXT: v_writelane_b32 v6, s70, 20 -; CHECK-NEXT: v_writelane_b32 v6, s71, 21 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: v_mov_b32_e32 v1, s4 ; CHECK-NEXT: v_mov_b32_e32 v2, 0 +; CHECK-NEXT: s_load_dwordx16 s[36:51], s[68:69], 0x2f0 +; CHECK-NEXT: s_mov_b32 s70, s68 ; CHECK-NEXT: v_writelane_b32 v7, s8, 0 ; CHECK-NEXT: v_writelane_b32 v7, s9, 1 ; CHECK-NEXT: v_writelane_b32 v7, s10, 2 @@ -77,9 +79,7 @@ define void @main(i1 %arg) #0 { ; CHECK-NEXT: v_writelane_b32 v7, s65, 29 ; CHECK-NEXT: v_writelane_b32 v7, s66, 30 ; CHECK-NEXT: s_load_dwordx16 s[8:23], s[68:69], 0x1f0 -; CHECK-NEXT: s_load_dwordx16 s[36:51], s[68:69], 0x2f0 ; CHECK-NEXT: s_mov_b32 s69, s68 -; CHECK-NEXT: s_mov_b32 s70, s68 ; CHECK-NEXT: s_mov_b32 s71, s68 ; CHECK-NEXT: v_writelane_b32 v7, s67, 31 ; CHECK-NEXT: image_sample_lz v3, v[1:2], s[60:67], s[68:71] dmask:0x1 @@ -225,29 +225,29 @@ define void @main(i1 %arg) #0 { ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: .LBB0_10: ; %UnifiedReturnBlock ; CHECK-NEXT: s_or_b64 exec, exec, s[6:7] -; CHECK-NEXT: v_readlane_b32 s71, v6, 21 -; CHECK-NEXT: v_readlane_b32 s70, v6, 20 -; CHECK-NEXT: v_readlane_b32 s69, v6, 19 -; CHECK-NEXT: v_readlane_b32 s68, v6, 18 -; CHECK-NEXT: v_readlane_b32 s67, v6, 17 -; CHECK-NEXT: v_readlane_b32 s66, v6, 16 -; CHECK-NEXT: v_readlane_b32 s65, v6, 15 -; CHECK-NEXT: v_readlane_b32 s64, v6, 14 -; CHECK-NEXT: v_readlane_b32 s55, v6, 13 -; CHECK-NEXT: v_readlane_b32 s54, v6, 12 -; CHECK-NEXT: v_readlane_b32 s53, v6, 11 -; CHECK-NEXT: v_readlane_b32 s52, v6, 10 +; CHECK-NEXT: v_readlane_b32 s30, v6, 20 +; CHECK-NEXT: v_readlane_b32 s31, v6, 21 +; CHECK-NEXT: v_readlane_b32 s71, v6, 19 +; CHECK-NEXT: v_readlane_b32 s70, v6, 18 +; CHECK-NEXT: v_readlane_b32 s69, v6, 17 +; CHECK-NEXT: v_readlane_b32 s68, v6, 16 +; CHECK-NEXT: v_readlane_b32 s67, v6, 15 +; CHECK-NEXT: v_readlane_b32 s66, v6, 14 +; CHECK-NEXT: v_readlane_b32 s65, v6, 13 +; CHECK-NEXT: v_readlane_b32 s64, v6, 12 +; CHECK-NEXT: v_readlane_b32 s55, v6, 11 +; CHECK-NEXT: v_readlane_b32 s54, v6, 10 +; CHECK-NEXT: v_readlane_b32 s53, v6, 9 +; CHECK-NEXT: v_readlane_b32 s52, v6, 8 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: v_readlane_b32 s51, v6, 9 -; CHECK-NEXT: v_readlane_b32 s50, v6, 8 -; CHECK-NEXT: v_readlane_b32 s49, v6, 7 -; CHECK-NEXT: v_readlane_b32 s48, v6, 6 -; CHECK-NEXT: v_readlane_b32 s39, v6, 5 -; CHECK-NEXT: v_readlane_b32 s38, v6, 4 -; CHECK-NEXT: v_readlane_b32 s37, v6, 3 -; CHECK-NEXT: v_readlane_b32 s36, v6, 2 -; CHECK-NEXT: v_readlane_b32 s31, v6, 1 -; CHECK-NEXT: v_readlane_b32 s30, v6, 0 +; CHECK-NEXT: v_readlane_b32 s51, v6, 7 +; CHECK-NEXT: v_readlane_b32 s50, v6, 6 +; CHECK-NEXT: v_readlane_b32 s49, v6, 5 +; CHECK-NEXT: v_readlane_b32 s48, v6, 4 +; CHECK-NEXT: v_readlane_b32 s39, v6, 3 +; CHECK-NEXT: v_readlane_b32 s38, v6, 2 +; CHECK-NEXT: v_readlane_b32 s37, v6, 1 +; CHECK-NEXT: v_readlane_b32 s36, v6, 0 ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/indirect-call.ll b/llvm/test/CodeGen/AMDGPU/indirect-call.ll index a208cfdb197af..2aaaff1ecc407 100644 --- a/llvm/test/CodeGen/AMDGPU/indirect-call.ll +++ b/llvm/test/CodeGen/AMDGPU/indirect-call.ll @@ -128,24 +128,24 @@ define void @test_indirect_call_vgpr_ptr(ptr %fptr) { ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 18 ; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: v_writelane_b32 v40, s34, 2 -; GCN-NEXT: v_writelane_b32 v40, s35, 3 -; GCN-NEXT: v_writelane_b32 v40, s36, 4 -; GCN-NEXT: v_writelane_b32 v40, s37, 5 -; GCN-NEXT: v_writelane_b32 v40, s38, 6 -; GCN-NEXT: v_writelane_b32 v40, s39, 7 -; GCN-NEXT: v_writelane_b32 v40, s48, 8 -; GCN-NEXT: v_writelane_b32 v40, s49, 9 -; GCN-NEXT: v_writelane_b32 v40, s50, 10 -; GCN-NEXT: v_writelane_b32 v40, s51, 11 -; GCN-NEXT: v_writelane_b32 v40, s52, 12 -; GCN-NEXT: v_writelane_b32 v40, s53, 13 -; GCN-NEXT: v_writelane_b32 v40, s54, 14 -; GCN-NEXT: v_writelane_b32 v40, s55, 15 -; GCN-NEXT: v_writelane_b32 v40, s64, 16 -; GCN-NEXT: v_writelane_b32 v40, s65, 17 +; GCN-NEXT: v_writelane_b32 v40, s34, 0 +; GCN-NEXT: v_writelane_b32 v40, s35, 1 +; GCN-NEXT: v_writelane_b32 v40, s36, 2 +; GCN-NEXT: v_writelane_b32 v40, s37, 3 +; GCN-NEXT: v_writelane_b32 v40, s38, 4 +; GCN-NEXT: v_writelane_b32 v40, s39, 5 +; GCN-NEXT: v_writelane_b32 v40, s48, 6 +; GCN-NEXT: v_writelane_b32 v40, s49, 7 +; GCN-NEXT: v_writelane_b32 v40, s50, 8 +; GCN-NEXT: v_writelane_b32 v40, s51, 9 +; GCN-NEXT: v_writelane_b32 v40, s52, 10 +; GCN-NEXT: v_writelane_b32 v40, s53, 11 +; GCN-NEXT: v_writelane_b32 v40, s54, 12 +; GCN-NEXT: v_writelane_b32 v40, s55, 13 +; GCN-NEXT: v_writelane_b32 v40, s64, 14 +; GCN-NEXT: v_writelane_b32 v40, s65, 15 +; GCN-NEXT: v_writelane_b32 v40, s30, 16 +; GCN-NEXT: v_writelane_b32 v40, s31, 17 ; GCN-NEXT: s_mov_b32 s50, s15 ; GCN-NEXT: s_mov_b32 s51, s14 ; GCN-NEXT: s_mov_b32 s52, s13 @@ -175,24 +175,24 @@ define void @test_indirect_call_vgpr_ptr(ptr %fptr) { ; GCN-NEXT: s_cbranch_execnz .LBB2_1 ; GCN-NEXT: ; %bb.2: ; GCN-NEXT: s_mov_b64 exec, s[54:55] -; GCN-NEXT: v_readlane_b32 s65, v40, 17 -; GCN-NEXT: v_readlane_b32 s64, v40, 16 -; GCN-NEXT: v_readlane_b32 s55, v40, 15 -; GCN-NEXT: v_readlane_b32 s54, v40, 14 -; GCN-NEXT: v_readlane_b32 s53, v40, 13 -; GCN-NEXT: v_readlane_b32 s52, v40, 12 -; GCN-NEXT: v_readlane_b32 s51, v40, 11 -; GCN-NEXT: v_readlane_b32 s50, v40, 10 -; GCN-NEXT: v_readlane_b32 s49, v40, 9 -; GCN-NEXT: v_readlane_b32 s48, v40, 8 -; GCN-NEXT: v_readlane_b32 s39, v40, 7 -; GCN-NEXT: v_readlane_b32 s38, v40, 6 -; GCN-NEXT: v_readlane_b32 s37, v40, 5 -; GCN-NEXT: v_readlane_b32 s36, v40, 4 -; GCN-NEXT: v_readlane_b32 s35, v40, 3 -; GCN-NEXT: v_readlane_b32 s34, v40, 2 -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s30, v40, 16 +; GCN-NEXT: v_readlane_b32 s31, v40, 17 +; GCN-NEXT: v_readlane_b32 s65, v40, 15 +; GCN-NEXT: v_readlane_b32 s64, v40, 14 +; GCN-NEXT: v_readlane_b32 s55, v40, 13 +; GCN-NEXT: v_readlane_b32 s54, v40, 12 +; GCN-NEXT: v_readlane_b32 s53, v40, 11 +; GCN-NEXT: v_readlane_b32 s52, v40, 10 +; GCN-NEXT: v_readlane_b32 s51, v40, 9 +; GCN-NEXT: v_readlane_b32 s50, v40, 8 +; GCN-NEXT: v_readlane_b32 s49, v40, 7 +; GCN-NEXT: v_readlane_b32 s48, v40, 6 +; GCN-NEXT: v_readlane_b32 s39, v40, 5 +; GCN-NEXT: v_readlane_b32 s38, v40, 4 +; GCN-NEXT: v_readlane_b32 s37, v40, 3 +; GCN-NEXT: v_readlane_b32 s36, v40, 2 +; GCN-NEXT: v_readlane_b32 s35, v40, 1 +; GCN-NEXT: v_readlane_b32 s34, v40, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 18 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -212,24 +212,24 @@ define void @test_indirect_call_vgpr_ptr(ptr %fptr) { ; GISEL-NEXT: s_mov_b64 exec, s[18:19] ; GISEL-NEXT: v_writelane_b32 v40, s16, 18 ; GISEL-NEXT: s_addk_i32 s32, 0x400 -; GISEL-NEXT: v_writelane_b32 v40, s30, 0 -; GISEL-NEXT: v_writelane_b32 v40, s31, 1 -; GISEL-NEXT: v_writelane_b32 v40, s34, 2 -; GISEL-NEXT: v_writelane_b32 v40, s35, 3 -; GISEL-NEXT: v_writelane_b32 v40, s36, 4 -; GISEL-NEXT: v_writelane_b32 v40, s37, 5 -; GISEL-NEXT: v_writelane_b32 v40, s38, 6 -; GISEL-NEXT: v_writelane_b32 v40, s39, 7 -; GISEL-NEXT: v_writelane_b32 v40, s48, 8 -; GISEL-NEXT: v_writelane_b32 v40, s49, 9 -; GISEL-NEXT: v_writelane_b32 v40, s50, 10 -; GISEL-NEXT: v_writelane_b32 v40, s51, 11 -; GISEL-NEXT: v_writelane_b32 v40, s52, 12 -; GISEL-NEXT: v_writelane_b32 v40, s53, 13 -; GISEL-NEXT: v_writelane_b32 v40, s54, 14 -; GISEL-NEXT: v_writelane_b32 v40, s55, 15 -; GISEL-NEXT: v_writelane_b32 v40, s64, 16 -; GISEL-NEXT: v_writelane_b32 v40, s65, 17 +; GISEL-NEXT: v_writelane_b32 v40, s34, 0 +; GISEL-NEXT: v_writelane_b32 v40, s35, 1 +; GISEL-NEXT: v_writelane_b32 v40, s36, 2 +; GISEL-NEXT: v_writelane_b32 v40, s37, 3 +; GISEL-NEXT: v_writelane_b32 v40, s38, 4 +; GISEL-NEXT: v_writelane_b32 v40, s39, 5 +; GISEL-NEXT: v_writelane_b32 v40, s48, 6 +; GISEL-NEXT: v_writelane_b32 v40, s49, 7 +; GISEL-NEXT: v_writelane_b32 v40, s50, 8 +; GISEL-NEXT: v_writelane_b32 v40, s51, 9 +; GISEL-NEXT: v_writelane_b32 v40, s52, 10 +; GISEL-NEXT: v_writelane_b32 v40, s53, 11 +; GISEL-NEXT: v_writelane_b32 v40, s54, 12 +; GISEL-NEXT: v_writelane_b32 v40, s55, 13 +; GISEL-NEXT: v_writelane_b32 v40, s64, 14 +; GISEL-NEXT: v_writelane_b32 v40, s65, 15 +; GISEL-NEXT: v_writelane_b32 v40, s30, 16 +; GISEL-NEXT: v_writelane_b32 v40, s31, 17 ; GISEL-NEXT: s_mov_b32 s50, s15 ; GISEL-NEXT: s_mov_b32 s51, s14 ; GISEL-NEXT: s_mov_b32 s52, s13 @@ -259,24 +259,24 @@ define void @test_indirect_call_vgpr_ptr(ptr %fptr) { ; GISEL-NEXT: s_cbranch_execnz .LBB2_1 ; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: s_mov_b64 exec, s[54:55] -; GISEL-NEXT: v_readlane_b32 s65, v40, 17 -; GISEL-NEXT: v_readlane_b32 s64, v40, 16 -; GISEL-NEXT: v_readlane_b32 s55, v40, 15 -; GISEL-NEXT: v_readlane_b32 s54, v40, 14 -; GISEL-NEXT: v_readlane_b32 s53, v40, 13 -; GISEL-NEXT: v_readlane_b32 s52, v40, 12 -; GISEL-NEXT: v_readlane_b32 s51, v40, 11 -; GISEL-NEXT: v_readlane_b32 s50, v40, 10 -; GISEL-NEXT: v_readlane_b32 s49, v40, 9 -; GISEL-NEXT: v_readlane_b32 s48, v40, 8 -; GISEL-NEXT: v_readlane_b32 s39, v40, 7 -; GISEL-NEXT: v_readlane_b32 s38, v40, 6 -; GISEL-NEXT: v_readlane_b32 s37, v40, 5 -; GISEL-NEXT: v_readlane_b32 s36, v40, 4 -; GISEL-NEXT: v_readlane_b32 s35, v40, 3 -; GISEL-NEXT: v_readlane_b32 s34, v40, 2 -; GISEL-NEXT: v_readlane_b32 s31, v40, 1 -; GISEL-NEXT: v_readlane_b32 s30, v40, 0 +; GISEL-NEXT: v_readlane_b32 s30, v40, 16 +; GISEL-NEXT: v_readlane_b32 s31, v40, 17 +; GISEL-NEXT: v_readlane_b32 s65, v40, 15 +; GISEL-NEXT: v_readlane_b32 s64, v40, 14 +; GISEL-NEXT: v_readlane_b32 s55, v40, 13 +; GISEL-NEXT: v_readlane_b32 s54, v40, 12 +; GISEL-NEXT: v_readlane_b32 s53, v40, 11 +; GISEL-NEXT: v_readlane_b32 s52, v40, 10 +; GISEL-NEXT: v_readlane_b32 s51, v40, 9 +; GISEL-NEXT: v_readlane_b32 s50, v40, 8 +; GISEL-NEXT: v_readlane_b32 s49, v40, 7 +; GISEL-NEXT: v_readlane_b32 s48, v40, 6 +; GISEL-NEXT: v_readlane_b32 s39, v40, 5 +; GISEL-NEXT: v_readlane_b32 s38, v40, 4 +; GISEL-NEXT: v_readlane_b32 s37, v40, 3 +; GISEL-NEXT: v_readlane_b32 s36, v40, 2 +; GISEL-NEXT: v_readlane_b32 s35, v40, 1 +; GISEL-NEXT: v_readlane_b32 s34, v40, 0 ; GISEL-NEXT: s_mov_b32 s32, s33 ; GISEL-NEXT: v_readlane_b32 s4, v40, 18 ; GISEL-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -300,24 +300,24 @@ define void @test_indirect_call_vgpr_ptr_arg(ptr %fptr) { ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 18 ; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: v_writelane_b32 v40, s34, 2 -; GCN-NEXT: v_writelane_b32 v40, s35, 3 -; GCN-NEXT: v_writelane_b32 v40, s36, 4 -; GCN-NEXT: v_writelane_b32 v40, s37, 5 -; GCN-NEXT: v_writelane_b32 v40, s38, 6 -; GCN-NEXT: v_writelane_b32 v40, s39, 7 -; GCN-NEXT: v_writelane_b32 v40, s48, 8 -; GCN-NEXT: v_writelane_b32 v40, s49, 9 -; GCN-NEXT: v_writelane_b32 v40, s50, 10 -; GCN-NEXT: v_writelane_b32 v40, s51, 11 -; GCN-NEXT: v_writelane_b32 v40, s52, 12 -; GCN-NEXT: v_writelane_b32 v40, s53, 13 -; GCN-NEXT: v_writelane_b32 v40, s54, 14 -; GCN-NEXT: v_writelane_b32 v40, s55, 15 -; GCN-NEXT: v_writelane_b32 v40, s64, 16 -; GCN-NEXT: v_writelane_b32 v40, s65, 17 +; GCN-NEXT: v_writelane_b32 v40, s34, 0 +; GCN-NEXT: v_writelane_b32 v40, s35, 1 +; GCN-NEXT: v_writelane_b32 v40, s36, 2 +; GCN-NEXT: v_writelane_b32 v40, s37, 3 +; GCN-NEXT: v_writelane_b32 v40, s38, 4 +; GCN-NEXT: v_writelane_b32 v40, s39, 5 +; GCN-NEXT: v_writelane_b32 v40, s48, 6 +; GCN-NEXT: v_writelane_b32 v40, s49, 7 +; GCN-NEXT: v_writelane_b32 v40, s50, 8 +; GCN-NEXT: v_writelane_b32 v40, s51, 9 +; GCN-NEXT: v_writelane_b32 v40, s52, 10 +; GCN-NEXT: v_writelane_b32 v40, s53, 11 +; GCN-NEXT: v_writelane_b32 v40, s54, 12 +; GCN-NEXT: v_writelane_b32 v40, s55, 13 +; GCN-NEXT: v_writelane_b32 v40, s64, 14 +; GCN-NEXT: v_writelane_b32 v40, s65, 15 +; GCN-NEXT: v_writelane_b32 v40, s30, 16 +; GCN-NEXT: v_writelane_b32 v40, s31, 17 ; GCN-NEXT: s_mov_b32 s50, s15 ; GCN-NEXT: s_mov_b32 s51, s14 ; GCN-NEXT: s_mov_b32 s52, s13 @@ -350,24 +350,24 @@ define void @test_indirect_call_vgpr_ptr_arg(ptr %fptr) { ; GCN-NEXT: s_cbranch_execnz .LBB3_1 ; GCN-NEXT: ; %bb.2: ; GCN-NEXT: s_mov_b64 exec, s[54:55] -; GCN-NEXT: v_readlane_b32 s65, v40, 17 -; GCN-NEXT: v_readlane_b32 s64, v40, 16 -; GCN-NEXT: v_readlane_b32 s55, v40, 15 -; GCN-NEXT: v_readlane_b32 s54, v40, 14 -; GCN-NEXT: v_readlane_b32 s53, v40, 13 -; GCN-NEXT: v_readlane_b32 s52, v40, 12 -; GCN-NEXT: v_readlane_b32 s51, v40, 11 -; GCN-NEXT: v_readlane_b32 s50, v40, 10 -; GCN-NEXT: v_readlane_b32 s49, v40, 9 -; GCN-NEXT: v_readlane_b32 s48, v40, 8 -; GCN-NEXT: v_readlane_b32 s39, v40, 7 -; GCN-NEXT: v_readlane_b32 s38, v40, 6 -; GCN-NEXT: v_readlane_b32 s37, v40, 5 -; GCN-NEXT: v_readlane_b32 s36, v40, 4 -; GCN-NEXT: v_readlane_b32 s35, v40, 3 -; GCN-NEXT: v_readlane_b32 s34, v40, 2 -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s30, v40, 16 +; GCN-NEXT: v_readlane_b32 s31, v40, 17 +; GCN-NEXT: v_readlane_b32 s65, v40, 15 +; GCN-NEXT: v_readlane_b32 s64, v40, 14 +; GCN-NEXT: v_readlane_b32 s55, v40, 13 +; GCN-NEXT: v_readlane_b32 s54, v40, 12 +; GCN-NEXT: v_readlane_b32 s53, v40, 11 +; GCN-NEXT: v_readlane_b32 s52, v40, 10 +; GCN-NEXT: v_readlane_b32 s51, v40, 9 +; GCN-NEXT: v_readlane_b32 s50, v40, 8 +; GCN-NEXT: v_readlane_b32 s49, v40, 7 +; GCN-NEXT: v_readlane_b32 s48, v40, 6 +; GCN-NEXT: v_readlane_b32 s39, v40, 5 +; GCN-NEXT: v_readlane_b32 s38, v40, 4 +; GCN-NEXT: v_readlane_b32 s37, v40, 3 +; GCN-NEXT: v_readlane_b32 s36, v40, 2 +; GCN-NEXT: v_readlane_b32 s35, v40, 1 +; GCN-NEXT: v_readlane_b32 s34, v40, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 18 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -387,24 +387,24 @@ define void @test_indirect_call_vgpr_ptr_arg(ptr %fptr) { ; GISEL-NEXT: s_mov_b64 exec, s[18:19] ; GISEL-NEXT: v_writelane_b32 v40, s16, 18 ; GISEL-NEXT: s_addk_i32 s32, 0x400 -; GISEL-NEXT: v_writelane_b32 v40, s30, 0 -; GISEL-NEXT: v_writelane_b32 v40, s31, 1 -; GISEL-NEXT: v_writelane_b32 v40, s34, 2 -; GISEL-NEXT: v_writelane_b32 v40, s35, 3 -; GISEL-NEXT: v_writelane_b32 v40, s36, 4 -; GISEL-NEXT: v_writelane_b32 v40, s37, 5 -; GISEL-NEXT: v_writelane_b32 v40, s38, 6 -; GISEL-NEXT: v_writelane_b32 v40, s39, 7 -; GISEL-NEXT: v_writelane_b32 v40, s48, 8 -; GISEL-NEXT: v_writelane_b32 v40, s49, 9 -; GISEL-NEXT: v_writelane_b32 v40, s50, 10 -; GISEL-NEXT: v_writelane_b32 v40, s51, 11 -; GISEL-NEXT: v_writelane_b32 v40, s52, 12 -; GISEL-NEXT: v_writelane_b32 v40, s53, 13 -; GISEL-NEXT: v_writelane_b32 v40, s54, 14 -; GISEL-NEXT: v_writelane_b32 v40, s55, 15 -; GISEL-NEXT: v_writelane_b32 v40, s64, 16 -; GISEL-NEXT: v_writelane_b32 v40, s65, 17 +; GISEL-NEXT: v_writelane_b32 v40, s34, 0 +; GISEL-NEXT: v_writelane_b32 v40, s35, 1 +; GISEL-NEXT: v_writelane_b32 v40, s36, 2 +; GISEL-NEXT: v_writelane_b32 v40, s37, 3 +; GISEL-NEXT: v_writelane_b32 v40, s38, 4 +; GISEL-NEXT: v_writelane_b32 v40, s39, 5 +; GISEL-NEXT: v_writelane_b32 v40, s48, 6 +; GISEL-NEXT: v_writelane_b32 v40, s49, 7 +; GISEL-NEXT: v_writelane_b32 v40, s50, 8 +; GISEL-NEXT: v_writelane_b32 v40, s51, 9 +; GISEL-NEXT: v_writelane_b32 v40, s52, 10 +; GISEL-NEXT: v_writelane_b32 v40, s53, 11 +; GISEL-NEXT: v_writelane_b32 v40, s54, 12 +; GISEL-NEXT: v_writelane_b32 v40, s55, 13 +; GISEL-NEXT: v_writelane_b32 v40, s64, 14 +; GISEL-NEXT: v_writelane_b32 v40, s65, 15 +; GISEL-NEXT: v_writelane_b32 v40, s30, 16 +; GISEL-NEXT: v_writelane_b32 v40, s31, 17 ; GISEL-NEXT: s_mov_b32 s50, s15 ; GISEL-NEXT: s_mov_b32 s51, s14 ; GISEL-NEXT: s_mov_b32 s52, s13 @@ -435,24 +435,24 @@ define void @test_indirect_call_vgpr_ptr_arg(ptr %fptr) { ; GISEL-NEXT: s_cbranch_execnz .LBB3_1 ; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: s_mov_b64 exec, s[54:55] -; GISEL-NEXT: v_readlane_b32 s65, v40, 17 -; GISEL-NEXT: v_readlane_b32 s64, v40, 16 -; GISEL-NEXT: v_readlane_b32 s55, v40, 15 -; GISEL-NEXT: v_readlane_b32 s54, v40, 14 -; GISEL-NEXT: v_readlane_b32 s53, v40, 13 -; GISEL-NEXT: v_readlane_b32 s52, v40, 12 -; GISEL-NEXT: v_readlane_b32 s51, v40, 11 -; GISEL-NEXT: v_readlane_b32 s50, v40, 10 -; GISEL-NEXT: v_readlane_b32 s49, v40, 9 -; GISEL-NEXT: v_readlane_b32 s48, v40, 8 -; GISEL-NEXT: v_readlane_b32 s39, v40, 7 -; GISEL-NEXT: v_readlane_b32 s38, v40, 6 -; GISEL-NEXT: v_readlane_b32 s37, v40, 5 -; GISEL-NEXT: v_readlane_b32 s36, v40, 4 -; GISEL-NEXT: v_readlane_b32 s35, v40, 3 -; GISEL-NEXT: v_readlane_b32 s34, v40, 2 -; GISEL-NEXT: v_readlane_b32 s31, v40, 1 -; GISEL-NEXT: v_readlane_b32 s30, v40, 0 +; GISEL-NEXT: v_readlane_b32 s30, v40, 16 +; GISEL-NEXT: v_readlane_b32 s31, v40, 17 +; GISEL-NEXT: v_readlane_b32 s65, v40, 15 +; GISEL-NEXT: v_readlane_b32 s64, v40, 14 +; GISEL-NEXT: v_readlane_b32 s55, v40, 13 +; GISEL-NEXT: v_readlane_b32 s54, v40, 12 +; GISEL-NEXT: v_readlane_b32 s53, v40, 11 +; GISEL-NEXT: v_readlane_b32 s52, v40, 10 +; GISEL-NEXT: v_readlane_b32 s51, v40, 9 +; GISEL-NEXT: v_readlane_b32 s50, v40, 8 +; GISEL-NEXT: v_readlane_b32 s49, v40, 7 +; GISEL-NEXT: v_readlane_b32 s48, v40, 6 +; GISEL-NEXT: v_readlane_b32 s39, v40, 5 +; GISEL-NEXT: v_readlane_b32 s38, v40, 4 +; GISEL-NEXT: v_readlane_b32 s37, v40, 3 +; GISEL-NEXT: v_readlane_b32 s36, v40, 2 +; GISEL-NEXT: v_readlane_b32 s35, v40, 1 +; GISEL-NEXT: v_readlane_b32 s34, v40, 0 ; GISEL-NEXT: s_mov_b32 s32, s33 ; GISEL-NEXT: v_readlane_b32 s4, v40, 18 ; GISEL-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -476,24 +476,24 @@ define i32 @test_indirect_call_vgpr_ptr_ret(ptr %fptr) { ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 18 ; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: v_writelane_b32 v40, s34, 2 -; GCN-NEXT: v_writelane_b32 v40, s35, 3 -; GCN-NEXT: v_writelane_b32 v40, s36, 4 -; GCN-NEXT: v_writelane_b32 v40, s37, 5 -; GCN-NEXT: v_writelane_b32 v40, s38, 6 -; GCN-NEXT: v_writelane_b32 v40, s39, 7 -; GCN-NEXT: v_writelane_b32 v40, s48, 8 -; GCN-NEXT: v_writelane_b32 v40, s49, 9 -; GCN-NEXT: v_writelane_b32 v40, s50, 10 -; GCN-NEXT: v_writelane_b32 v40, s51, 11 -; GCN-NEXT: v_writelane_b32 v40, s52, 12 -; GCN-NEXT: v_writelane_b32 v40, s53, 13 -; GCN-NEXT: v_writelane_b32 v40, s54, 14 -; GCN-NEXT: v_writelane_b32 v40, s55, 15 -; GCN-NEXT: v_writelane_b32 v40, s64, 16 -; GCN-NEXT: v_writelane_b32 v40, s65, 17 +; GCN-NEXT: v_writelane_b32 v40, s34, 0 +; GCN-NEXT: v_writelane_b32 v40, s35, 1 +; GCN-NEXT: v_writelane_b32 v40, s36, 2 +; GCN-NEXT: v_writelane_b32 v40, s37, 3 +; GCN-NEXT: v_writelane_b32 v40, s38, 4 +; GCN-NEXT: v_writelane_b32 v40, s39, 5 +; GCN-NEXT: v_writelane_b32 v40, s48, 6 +; GCN-NEXT: v_writelane_b32 v40, s49, 7 +; GCN-NEXT: v_writelane_b32 v40, s50, 8 +; GCN-NEXT: v_writelane_b32 v40, s51, 9 +; GCN-NEXT: v_writelane_b32 v40, s52, 10 +; GCN-NEXT: v_writelane_b32 v40, s53, 11 +; GCN-NEXT: v_writelane_b32 v40, s54, 12 +; GCN-NEXT: v_writelane_b32 v40, s55, 13 +; GCN-NEXT: v_writelane_b32 v40, s64, 14 +; GCN-NEXT: v_writelane_b32 v40, s65, 15 +; GCN-NEXT: v_writelane_b32 v40, s30, 16 +; GCN-NEXT: v_writelane_b32 v40, s31, 17 ; GCN-NEXT: s_mov_b32 s50, s15 ; GCN-NEXT: s_mov_b32 s51, s14 ; GCN-NEXT: s_mov_b32 s52, s13 @@ -525,24 +525,24 @@ define i32 @test_indirect_call_vgpr_ptr_ret(ptr %fptr) { ; GCN-NEXT: ; %bb.2: ; GCN-NEXT: s_mov_b64 exec, s[54:55] ; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v2 -; GCN-NEXT: v_readlane_b32 s65, v40, 17 -; GCN-NEXT: v_readlane_b32 s64, v40, 16 -; GCN-NEXT: v_readlane_b32 s55, v40, 15 -; GCN-NEXT: v_readlane_b32 s54, v40, 14 -; GCN-NEXT: v_readlane_b32 s53, v40, 13 -; GCN-NEXT: v_readlane_b32 s52, v40, 12 -; GCN-NEXT: v_readlane_b32 s51, v40, 11 -; GCN-NEXT: v_readlane_b32 s50, v40, 10 -; GCN-NEXT: v_readlane_b32 s49, v40, 9 -; GCN-NEXT: v_readlane_b32 s48, v40, 8 -; GCN-NEXT: v_readlane_b32 s39, v40, 7 -; GCN-NEXT: v_readlane_b32 s38, v40, 6 -; GCN-NEXT: v_readlane_b32 s37, v40, 5 -; GCN-NEXT: v_readlane_b32 s36, v40, 4 -; GCN-NEXT: v_readlane_b32 s35, v40, 3 -; GCN-NEXT: v_readlane_b32 s34, v40, 2 -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s30, v40, 16 +; GCN-NEXT: v_readlane_b32 s31, v40, 17 +; GCN-NEXT: v_readlane_b32 s65, v40, 15 +; GCN-NEXT: v_readlane_b32 s64, v40, 14 +; GCN-NEXT: v_readlane_b32 s55, v40, 13 +; GCN-NEXT: v_readlane_b32 s54, v40, 12 +; GCN-NEXT: v_readlane_b32 s53, v40, 11 +; GCN-NEXT: v_readlane_b32 s52, v40, 10 +; GCN-NEXT: v_readlane_b32 s51, v40, 9 +; GCN-NEXT: v_readlane_b32 s50, v40, 8 +; GCN-NEXT: v_readlane_b32 s49, v40, 7 +; GCN-NEXT: v_readlane_b32 s48, v40, 6 +; GCN-NEXT: v_readlane_b32 s39, v40, 5 +; GCN-NEXT: v_readlane_b32 s38, v40, 4 +; GCN-NEXT: v_readlane_b32 s37, v40, 3 +; GCN-NEXT: v_readlane_b32 s36, v40, 2 +; GCN-NEXT: v_readlane_b32 s35, v40, 1 +; GCN-NEXT: v_readlane_b32 s34, v40, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 18 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -562,24 +562,24 @@ define i32 @test_indirect_call_vgpr_ptr_ret(ptr %fptr) { ; GISEL-NEXT: s_mov_b64 exec, s[18:19] ; GISEL-NEXT: v_writelane_b32 v40, s16, 18 ; GISEL-NEXT: s_addk_i32 s32, 0x400 -; GISEL-NEXT: v_writelane_b32 v40, s30, 0 -; GISEL-NEXT: v_writelane_b32 v40, s31, 1 -; GISEL-NEXT: v_writelane_b32 v40, s34, 2 -; GISEL-NEXT: v_writelane_b32 v40, s35, 3 -; GISEL-NEXT: v_writelane_b32 v40, s36, 4 -; GISEL-NEXT: v_writelane_b32 v40, s37, 5 -; GISEL-NEXT: v_writelane_b32 v40, s38, 6 -; GISEL-NEXT: v_writelane_b32 v40, s39, 7 -; GISEL-NEXT: v_writelane_b32 v40, s48, 8 -; GISEL-NEXT: v_writelane_b32 v40, s49, 9 -; GISEL-NEXT: v_writelane_b32 v40, s50, 10 -; GISEL-NEXT: v_writelane_b32 v40, s51, 11 -; GISEL-NEXT: v_writelane_b32 v40, s52, 12 -; GISEL-NEXT: v_writelane_b32 v40, s53, 13 -; GISEL-NEXT: v_writelane_b32 v40, s54, 14 -; GISEL-NEXT: v_writelane_b32 v40, s55, 15 -; GISEL-NEXT: v_writelane_b32 v40, s64, 16 -; GISEL-NEXT: v_writelane_b32 v40, s65, 17 +; GISEL-NEXT: v_writelane_b32 v40, s34, 0 +; GISEL-NEXT: v_writelane_b32 v40, s35, 1 +; GISEL-NEXT: v_writelane_b32 v40, s36, 2 +; GISEL-NEXT: v_writelane_b32 v40, s37, 3 +; GISEL-NEXT: v_writelane_b32 v40, s38, 4 +; GISEL-NEXT: v_writelane_b32 v40, s39, 5 +; GISEL-NEXT: v_writelane_b32 v40, s48, 6 +; GISEL-NEXT: v_writelane_b32 v40, s49, 7 +; GISEL-NEXT: v_writelane_b32 v40, s50, 8 +; GISEL-NEXT: v_writelane_b32 v40, s51, 9 +; GISEL-NEXT: v_writelane_b32 v40, s52, 10 +; GISEL-NEXT: v_writelane_b32 v40, s53, 11 +; GISEL-NEXT: v_writelane_b32 v40, s54, 12 +; GISEL-NEXT: v_writelane_b32 v40, s55, 13 +; GISEL-NEXT: v_writelane_b32 v40, s64, 14 +; GISEL-NEXT: v_writelane_b32 v40, s65, 15 +; GISEL-NEXT: v_writelane_b32 v40, s30, 16 +; GISEL-NEXT: v_writelane_b32 v40, s31, 17 ; GISEL-NEXT: s_mov_b32 s50, s15 ; GISEL-NEXT: s_mov_b32 s51, s14 ; GISEL-NEXT: s_mov_b32 s52, s13 @@ -611,24 +611,24 @@ define i32 @test_indirect_call_vgpr_ptr_ret(ptr %fptr) { ; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: s_mov_b64 exec, s[54:55] ; GISEL-NEXT: v_add_i32_e32 v0, vcc, 1, v1 -; GISEL-NEXT: v_readlane_b32 s65, v40, 17 -; GISEL-NEXT: v_readlane_b32 s64, v40, 16 -; GISEL-NEXT: v_readlane_b32 s55, v40, 15 -; GISEL-NEXT: v_readlane_b32 s54, v40, 14 -; GISEL-NEXT: v_readlane_b32 s53, v40, 13 -; GISEL-NEXT: v_readlane_b32 s52, v40, 12 -; GISEL-NEXT: v_readlane_b32 s51, v40, 11 -; GISEL-NEXT: v_readlane_b32 s50, v40, 10 -; GISEL-NEXT: v_readlane_b32 s49, v40, 9 -; GISEL-NEXT: v_readlane_b32 s48, v40, 8 -; GISEL-NEXT: v_readlane_b32 s39, v40, 7 -; GISEL-NEXT: v_readlane_b32 s38, v40, 6 -; GISEL-NEXT: v_readlane_b32 s37, v40, 5 -; GISEL-NEXT: v_readlane_b32 s36, v40, 4 -; GISEL-NEXT: v_readlane_b32 s35, v40, 3 -; GISEL-NEXT: v_readlane_b32 s34, v40, 2 -; GISEL-NEXT: v_readlane_b32 s31, v40, 1 -; GISEL-NEXT: v_readlane_b32 s30, v40, 0 +; GISEL-NEXT: v_readlane_b32 s30, v40, 16 +; GISEL-NEXT: v_readlane_b32 s31, v40, 17 +; GISEL-NEXT: v_readlane_b32 s65, v40, 15 +; GISEL-NEXT: v_readlane_b32 s64, v40, 14 +; GISEL-NEXT: v_readlane_b32 s55, v40, 13 +; GISEL-NEXT: v_readlane_b32 s54, v40, 12 +; GISEL-NEXT: v_readlane_b32 s53, v40, 11 +; GISEL-NEXT: v_readlane_b32 s52, v40, 10 +; GISEL-NEXT: v_readlane_b32 s51, v40, 9 +; GISEL-NEXT: v_readlane_b32 s50, v40, 8 +; GISEL-NEXT: v_readlane_b32 s49, v40, 7 +; GISEL-NEXT: v_readlane_b32 s48, v40, 6 +; GISEL-NEXT: v_readlane_b32 s39, v40, 5 +; GISEL-NEXT: v_readlane_b32 s38, v40, 4 +; GISEL-NEXT: v_readlane_b32 s37, v40, 3 +; GISEL-NEXT: v_readlane_b32 s36, v40, 2 +; GISEL-NEXT: v_readlane_b32 s35, v40, 1 +; GISEL-NEXT: v_readlane_b32 s34, v40, 0 ; GISEL-NEXT: s_mov_b32 s32, s33 ; GISEL-NEXT: v_readlane_b32 s4, v40, 18 ; GISEL-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -653,26 +653,26 @@ define void @test_indirect_call_vgpr_ptr_in_branch(ptr %fptr, i1 %cond) { ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 20 ; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: v_writelane_b32 v40, s34, 2 -; GCN-NEXT: v_writelane_b32 v40, s35, 3 -; GCN-NEXT: v_writelane_b32 v40, s36, 4 -; GCN-NEXT: v_writelane_b32 v40, s37, 5 -; GCN-NEXT: v_writelane_b32 v40, s38, 6 -; GCN-NEXT: v_writelane_b32 v40, s39, 7 -; GCN-NEXT: v_writelane_b32 v40, s48, 8 -; GCN-NEXT: v_writelane_b32 v40, s49, 9 -; GCN-NEXT: v_writelane_b32 v40, s50, 10 -; GCN-NEXT: v_writelane_b32 v40, s51, 11 -; GCN-NEXT: v_writelane_b32 v40, s52, 12 -; GCN-NEXT: v_writelane_b32 v40, s53, 13 -; GCN-NEXT: v_writelane_b32 v40, s54, 14 -; GCN-NEXT: v_writelane_b32 v40, s55, 15 -; GCN-NEXT: v_writelane_b32 v40, s64, 16 -; GCN-NEXT: v_writelane_b32 v40, s65, 17 -; GCN-NEXT: v_writelane_b32 v40, s66, 18 -; GCN-NEXT: v_writelane_b32 v40, s67, 19 +; GCN-NEXT: v_writelane_b32 v40, s34, 0 +; GCN-NEXT: v_writelane_b32 v40, s35, 1 +; GCN-NEXT: v_writelane_b32 v40, s36, 2 +; GCN-NEXT: v_writelane_b32 v40, s37, 3 +; GCN-NEXT: v_writelane_b32 v40, s38, 4 +; GCN-NEXT: v_writelane_b32 v40, s39, 5 +; GCN-NEXT: v_writelane_b32 v40, s48, 6 +; GCN-NEXT: v_writelane_b32 v40, s49, 7 +; GCN-NEXT: v_writelane_b32 v40, s50, 8 +; GCN-NEXT: v_writelane_b32 v40, s51, 9 +; GCN-NEXT: v_writelane_b32 v40, s52, 10 +; GCN-NEXT: v_writelane_b32 v40, s53, 11 +; GCN-NEXT: v_writelane_b32 v40, s54, 12 +; GCN-NEXT: v_writelane_b32 v40, s55, 13 +; GCN-NEXT: v_writelane_b32 v40, s64, 14 +; GCN-NEXT: v_writelane_b32 v40, s65, 15 +; GCN-NEXT: v_writelane_b32 v40, s66, 16 +; GCN-NEXT: v_writelane_b32 v40, s67, 17 +; GCN-NEXT: v_writelane_b32 v40, s30, 18 +; GCN-NEXT: v_writelane_b32 v40, s31, 19 ; GCN-NEXT: s_mov_b32 s50, s15 ; GCN-NEXT: s_mov_b32 s51, s14 ; GCN-NEXT: s_mov_b32 s52, s13 @@ -709,26 +709,26 @@ define void @test_indirect_call_vgpr_ptr_in_branch(ptr %fptr, i1 %cond) { ; GCN-NEXT: s_mov_b64 exec, s[64:65] ; GCN-NEXT: .LBB5_4: ; %bb2 ; GCN-NEXT: s_or_b64 exec, exec, s[54:55] -; GCN-NEXT: v_readlane_b32 s67, v40, 19 -; GCN-NEXT: v_readlane_b32 s66, v40, 18 -; GCN-NEXT: v_readlane_b32 s65, v40, 17 -; GCN-NEXT: v_readlane_b32 s64, v40, 16 -; GCN-NEXT: v_readlane_b32 s55, v40, 15 -; GCN-NEXT: v_readlane_b32 s54, v40, 14 -; GCN-NEXT: v_readlane_b32 s53, v40, 13 -; GCN-NEXT: v_readlane_b32 s52, v40, 12 -; GCN-NEXT: v_readlane_b32 s51, v40, 11 -; GCN-NEXT: v_readlane_b32 s50, v40, 10 -; GCN-NEXT: v_readlane_b32 s49, v40, 9 -; GCN-NEXT: v_readlane_b32 s48, v40, 8 -; GCN-NEXT: v_readlane_b32 s39, v40, 7 -; GCN-NEXT: v_readlane_b32 s38, v40, 6 -; GCN-NEXT: v_readlane_b32 s37, v40, 5 -; GCN-NEXT: v_readlane_b32 s36, v40, 4 -; GCN-NEXT: v_readlane_b32 s35, v40, 3 -; GCN-NEXT: v_readlane_b32 s34, v40, 2 -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s30, v40, 18 +; GCN-NEXT: v_readlane_b32 s31, v40, 19 +; GCN-NEXT: v_readlane_b32 s67, v40, 17 +; GCN-NEXT: v_readlane_b32 s66, v40, 16 +; GCN-NEXT: v_readlane_b32 s65, v40, 15 +; GCN-NEXT: v_readlane_b32 s64, v40, 14 +; GCN-NEXT: v_readlane_b32 s55, v40, 13 +; GCN-NEXT: v_readlane_b32 s54, v40, 12 +; GCN-NEXT: v_readlane_b32 s53, v40, 11 +; GCN-NEXT: v_readlane_b32 s52, v40, 10 +; GCN-NEXT: v_readlane_b32 s51, v40, 9 +; GCN-NEXT: v_readlane_b32 s50, v40, 8 +; GCN-NEXT: v_readlane_b32 s49, v40, 7 +; GCN-NEXT: v_readlane_b32 s48, v40, 6 +; GCN-NEXT: v_readlane_b32 s39, v40, 5 +; GCN-NEXT: v_readlane_b32 s38, v40, 4 +; GCN-NEXT: v_readlane_b32 s37, v40, 3 +; GCN-NEXT: v_readlane_b32 s36, v40, 2 +; GCN-NEXT: v_readlane_b32 s35, v40, 1 +; GCN-NEXT: v_readlane_b32 s34, v40, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 20 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -748,26 +748,26 @@ define void @test_indirect_call_vgpr_ptr_in_branch(ptr %fptr, i1 %cond) { ; GISEL-NEXT: s_mov_b64 exec, s[18:19] ; GISEL-NEXT: v_writelane_b32 v40, s16, 20 ; GISEL-NEXT: s_addk_i32 s32, 0x400 -; GISEL-NEXT: v_writelane_b32 v40, s30, 0 -; GISEL-NEXT: v_writelane_b32 v40, s31, 1 -; GISEL-NEXT: v_writelane_b32 v40, s34, 2 -; GISEL-NEXT: v_writelane_b32 v40, s35, 3 -; GISEL-NEXT: v_writelane_b32 v40, s36, 4 -; GISEL-NEXT: v_writelane_b32 v40, s37, 5 -; GISEL-NEXT: v_writelane_b32 v40, s38, 6 -; GISEL-NEXT: v_writelane_b32 v40, s39, 7 -; GISEL-NEXT: v_writelane_b32 v40, s48, 8 -; GISEL-NEXT: v_writelane_b32 v40, s49, 9 -; GISEL-NEXT: v_writelane_b32 v40, s50, 10 -; GISEL-NEXT: v_writelane_b32 v40, s51, 11 -; GISEL-NEXT: v_writelane_b32 v40, s52, 12 -; GISEL-NEXT: v_writelane_b32 v40, s53, 13 -; GISEL-NEXT: v_writelane_b32 v40, s54, 14 -; GISEL-NEXT: v_writelane_b32 v40, s55, 15 -; GISEL-NEXT: v_writelane_b32 v40, s64, 16 -; GISEL-NEXT: v_writelane_b32 v40, s65, 17 -; GISEL-NEXT: v_writelane_b32 v40, s66, 18 -; GISEL-NEXT: v_writelane_b32 v40, s67, 19 +; GISEL-NEXT: v_writelane_b32 v40, s34, 0 +; GISEL-NEXT: v_writelane_b32 v40, s35, 1 +; GISEL-NEXT: v_writelane_b32 v40, s36, 2 +; GISEL-NEXT: v_writelane_b32 v40, s37, 3 +; GISEL-NEXT: v_writelane_b32 v40, s38, 4 +; GISEL-NEXT: v_writelane_b32 v40, s39, 5 +; GISEL-NEXT: v_writelane_b32 v40, s48, 6 +; GISEL-NEXT: v_writelane_b32 v40, s49, 7 +; GISEL-NEXT: v_writelane_b32 v40, s50, 8 +; GISEL-NEXT: v_writelane_b32 v40, s51, 9 +; GISEL-NEXT: v_writelane_b32 v40, s52, 10 +; GISEL-NEXT: v_writelane_b32 v40, s53, 11 +; GISEL-NEXT: v_writelane_b32 v40, s54, 12 +; GISEL-NEXT: v_writelane_b32 v40, s55, 13 +; GISEL-NEXT: v_writelane_b32 v40, s64, 14 +; GISEL-NEXT: v_writelane_b32 v40, s65, 15 +; GISEL-NEXT: v_writelane_b32 v40, s66, 16 +; GISEL-NEXT: v_writelane_b32 v40, s67, 17 +; GISEL-NEXT: v_writelane_b32 v40, s30, 18 +; GISEL-NEXT: v_writelane_b32 v40, s31, 19 ; GISEL-NEXT: s_mov_b32 s50, s15 ; GISEL-NEXT: s_mov_b32 s51, s14 ; GISEL-NEXT: s_mov_b32 s52, s13 @@ -804,26 +804,26 @@ define void @test_indirect_call_vgpr_ptr_in_branch(ptr %fptr, i1 %cond) { ; GISEL-NEXT: s_mov_b64 exec, s[64:65] ; GISEL-NEXT: .LBB5_4: ; %bb2 ; GISEL-NEXT: s_or_b64 exec, exec, s[54:55] -; GISEL-NEXT: v_readlane_b32 s67, v40, 19 -; GISEL-NEXT: v_readlane_b32 s66, v40, 18 -; GISEL-NEXT: v_readlane_b32 s65, v40, 17 -; GISEL-NEXT: v_readlane_b32 s64, v40, 16 -; GISEL-NEXT: v_readlane_b32 s55, v40, 15 -; GISEL-NEXT: v_readlane_b32 s54, v40, 14 -; GISEL-NEXT: v_readlane_b32 s53, v40, 13 -; GISEL-NEXT: v_readlane_b32 s52, v40, 12 -; GISEL-NEXT: v_readlane_b32 s51, v40, 11 -; GISEL-NEXT: v_readlane_b32 s50, v40, 10 -; GISEL-NEXT: v_readlane_b32 s49, v40, 9 -; GISEL-NEXT: v_readlane_b32 s48, v40, 8 -; GISEL-NEXT: v_readlane_b32 s39, v40, 7 -; GISEL-NEXT: v_readlane_b32 s38, v40, 6 -; GISEL-NEXT: v_readlane_b32 s37, v40, 5 -; GISEL-NEXT: v_readlane_b32 s36, v40, 4 -; GISEL-NEXT: v_readlane_b32 s35, v40, 3 -; GISEL-NEXT: v_readlane_b32 s34, v40, 2 -; GISEL-NEXT: v_readlane_b32 s31, v40, 1 -; GISEL-NEXT: v_readlane_b32 s30, v40, 0 +; GISEL-NEXT: v_readlane_b32 s30, v40, 18 +; GISEL-NEXT: v_readlane_b32 s31, v40, 19 +; GISEL-NEXT: v_readlane_b32 s67, v40, 17 +; GISEL-NEXT: v_readlane_b32 s66, v40, 16 +; GISEL-NEXT: v_readlane_b32 s65, v40, 15 +; GISEL-NEXT: v_readlane_b32 s64, v40, 14 +; GISEL-NEXT: v_readlane_b32 s55, v40, 13 +; GISEL-NEXT: v_readlane_b32 s54, v40, 12 +; GISEL-NEXT: v_readlane_b32 s53, v40, 11 +; GISEL-NEXT: v_readlane_b32 s52, v40, 10 +; GISEL-NEXT: v_readlane_b32 s51, v40, 9 +; GISEL-NEXT: v_readlane_b32 s50, v40, 8 +; GISEL-NEXT: v_readlane_b32 s49, v40, 7 +; GISEL-NEXT: v_readlane_b32 s48, v40, 6 +; GISEL-NEXT: v_readlane_b32 s39, v40, 5 +; GISEL-NEXT: v_readlane_b32 s38, v40, 4 +; GISEL-NEXT: v_readlane_b32 s37, v40, 3 +; GISEL-NEXT: v_readlane_b32 s36, v40, 2 +; GISEL-NEXT: v_readlane_b32 s35, v40, 1 +; GISEL-NEXT: v_readlane_b32 s34, v40, 0 ; GISEL-NEXT: s_mov_b32 s32, s33 ; GISEL-NEXT: v_readlane_b32 s4, v40, 20 ; GISEL-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -853,22 +853,22 @@ define void @test_indirect_call_vgpr_ptr_inreg_arg(ptr %fptr) { ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] ; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: v_writelane_b32 v40, s34, 2 -; GCN-NEXT: v_writelane_b32 v40, s35, 3 -; GCN-NEXT: v_writelane_b32 v40, s36, 4 -; GCN-NEXT: v_writelane_b32 v40, s37, 5 -; GCN-NEXT: v_writelane_b32 v40, s38, 6 -; GCN-NEXT: v_writelane_b32 v40, s39, 7 -; GCN-NEXT: v_writelane_b32 v40, s48, 8 -; GCN-NEXT: v_writelane_b32 v40, s49, 9 -; GCN-NEXT: v_writelane_b32 v40, s50, 10 -; GCN-NEXT: v_writelane_b32 v40, s51, 11 -; GCN-NEXT: v_writelane_b32 v40, s52, 12 -; GCN-NEXT: v_writelane_b32 v40, s53, 13 -; GCN-NEXT: v_writelane_b32 v40, s54, 14 -; GCN-NEXT: v_writelane_b32 v40, s55, 15 +; GCN-NEXT: v_writelane_b32 v40, s34, 0 +; GCN-NEXT: v_writelane_b32 v40, s35, 1 +; GCN-NEXT: v_writelane_b32 v40, s36, 2 +; GCN-NEXT: v_writelane_b32 v40, s37, 3 +; GCN-NEXT: v_writelane_b32 v40, s38, 4 +; GCN-NEXT: v_writelane_b32 v40, s39, 5 +; GCN-NEXT: v_writelane_b32 v40, s48, 6 +; GCN-NEXT: v_writelane_b32 v40, s49, 7 +; GCN-NEXT: v_writelane_b32 v40, s50, 8 +; GCN-NEXT: v_writelane_b32 v40, s51, 9 +; GCN-NEXT: v_writelane_b32 v40, s52, 10 +; GCN-NEXT: v_writelane_b32 v40, s53, 11 +; GCN-NEXT: v_writelane_b32 v40, s54, 12 +; GCN-NEXT: v_writelane_b32 v40, s55, 13 +; GCN-NEXT: v_writelane_b32 v40, s30, 14 +; GCN-NEXT: v_writelane_b32 v40, s31, 15 ; GCN-NEXT: s_mov_b64 s[6:7], exec ; GCN-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: v_readfirstlane_b32 s8, v0 @@ -882,22 +882,22 @@ define void @test_indirect_call_vgpr_ptr_inreg_arg(ptr %fptr) { ; GCN-NEXT: s_cbranch_execnz .LBB6_1 ; GCN-NEXT: ; %bb.2: ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_readlane_b32 s55, v40, 15 -; GCN-NEXT: v_readlane_b32 s54, v40, 14 -; GCN-NEXT: v_readlane_b32 s53, v40, 13 -; GCN-NEXT: v_readlane_b32 s52, v40, 12 -; GCN-NEXT: v_readlane_b32 s51, v40, 11 -; GCN-NEXT: v_readlane_b32 s50, v40, 10 -; GCN-NEXT: v_readlane_b32 s49, v40, 9 -; GCN-NEXT: v_readlane_b32 s48, v40, 8 -; GCN-NEXT: v_readlane_b32 s39, v40, 7 -; GCN-NEXT: v_readlane_b32 s38, v40, 6 -; GCN-NEXT: v_readlane_b32 s37, v40, 5 -; GCN-NEXT: v_readlane_b32 s36, v40, 4 -; GCN-NEXT: v_readlane_b32 s35, v40, 3 -; GCN-NEXT: v_readlane_b32 s34, v40, 2 -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s30, v40, 14 +; GCN-NEXT: v_readlane_b32 s31, v40, 15 +; GCN-NEXT: v_readlane_b32 s55, v40, 13 +; GCN-NEXT: v_readlane_b32 s54, v40, 12 +; GCN-NEXT: v_readlane_b32 s53, v40, 11 +; GCN-NEXT: v_readlane_b32 s52, v40, 10 +; GCN-NEXT: v_readlane_b32 s51, v40, 9 +; GCN-NEXT: v_readlane_b32 s50, v40, 8 +; GCN-NEXT: v_readlane_b32 s49, v40, 7 +; GCN-NEXT: v_readlane_b32 s48, v40, 6 +; GCN-NEXT: v_readlane_b32 s39, v40, 5 +; GCN-NEXT: v_readlane_b32 s38, v40, 4 +; GCN-NEXT: v_readlane_b32 s37, v40, 3 +; GCN-NEXT: v_readlane_b32 s36, v40, 2 +; GCN-NEXT: v_readlane_b32 s35, v40, 1 +; GCN-NEXT: v_readlane_b32 s34, v40, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload @@ -915,22 +915,22 @@ define void @test_indirect_call_vgpr_ptr_inreg_arg(ptr %fptr) { ; GISEL-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GISEL-NEXT: s_mov_b64 exec, s[6:7] ; GISEL-NEXT: s_addk_i32 s32, 0x400 -; GISEL-NEXT: v_writelane_b32 v40, s30, 0 -; GISEL-NEXT: v_writelane_b32 v40, s31, 1 -; GISEL-NEXT: v_writelane_b32 v40, s34, 2 -; GISEL-NEXT: v_writelane_b32 v40, s35, 3 -; GISEL-NEXT: v_writelane_b32 v40, s36, 4 -; GISEL-NEXT: v_writelane_b32 v40, s37, 5 -; GISEL-NEXT: v_writelane_b32 v40, s38, 6 -; GISEL-NEXT: v_writelane_b32 v40, s39, 7 -; GISEL-NEXT: v_writelane_b32 v40, s48, 8 -; GISEL-NEXT: v_writelane_b32 v40, s49, 9 -; GISEL-NEXT: v_writelane_b32 v40, s50, 10 -; GISEL-NEXT: v_writelane_b32 v40, s51, 11 -; GISEL-NEXT: v_writelane_b32 v40, s52, 12 -; GISEL-NEXT: v_writelane_b32 v40, s53, 13 -; GISEL-NEXT: v_writelane_b32 v40, s54, 14 -; GISEL-NEXT: v_writelane_b32 v40, s55, 15 +; GISEL-NEXT: v_writelane_b32 v40, s34, 0 +; GISEL-NEXT: v_writelane_b32 v40, s35, 1 +; GISEL-NEXT: v_writelane_b32 v40, s36, 2 +; GISEL-NEXT: v_writelane_b32 v40, s37, 3 +; GISEL-NEXT: v_writelane_b32 v40, s38, 4 +; GISEL-NEXT: v_writelane_b32 v40, s39, 5 +; GISEL-NEXT: v_writelane_b32 v40, s48, 6 +; GISEL-NEXT: v_writelane_b32 v40, s49, 7 +; GISEL-NEXT: v_writelane_b32 v40, s50, 8 +; GISEL-NEXT: v_writelane_b32 v40, s51, 9 +; GISEL-NEXT: v_writelane_b32 v40, s52, 10 +; GISEL-NEXT: v_writelane_b32 v40, s53, 11 +; GISEL-NEXT: v_writelane_b32 v40, s54, 12 +; GISEL-NEXT: v_writelane_b32 v40, s55, 13 +; GISEL-NEXT: v_writelane_b32 v40, s30, 14 +; GISEL-NEXT: v_writelane_b32 v40, s31, 15 ; GISEL-NEXT: s_mov_b64 s[6:7], exec ; GISEL-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: v_readfirstlane_b32 s8, v0 @@ -944,22 +944,22 @@ define void @test_indirect_call_vgpr_ptr_inreg_arg(ptr %fptr) { ; GISEL-NEXT: s_cbranch_execnz .LBB6_1 ; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: s_mov_b64 exec, s[6:7] -; GISEL-NEXT: v_readlane_b32 s55, v40, 15 -; GISEL-NEXT: v_readlane_b32 s54, v40, 14 -; GISEL-NEXT: v_readlane_b32 s53, v40, 13 -; GISEL-NEXT: v_readlane_b32 s52, v40, 12 -; GISEL-NEXT: v_readlane_b32 s51, v40, 11 -; GISEL-NEXT: v_readlane_b32 s50, v40, 10 -; GISEL-NEXT: v_readlane_b32 s49, v40, 9 -; GISEL-NEXT: v_readlane_b32 s48, v40, 8 -; GISEL-NEXT: v_readlane_b32 s39, v40, 7 -; GISEL-NEXT: v_readlane_b32 s38, v40, 6 -; GISEL-NEXT: v_readlane_b32 s37, v40, 5 -; GISEL-NEXT: v_readlane_b32 s36, v40, 4 -; GISEL-NEXT: v_readlane_b32 s35, v40, 3 -; GISEL-NEXT: v_readlane_b32 s34, v40, 2 -; GISEL-NEXT: v_readlane_b32 s31, v40, 1 -; GISEL-NEXT: v_readlane_b32 s30, v40, 0 +; GISEL-NEXT: v_readlane_b32 s30, v40, 14 +; GISEL-NEXT: v_readlane_b32 s31, v40, 15 +; GISEL-NEXT: v_readlane_b32 s55, v40, 13 +; GISEL-NEXT: v_readlane_b32 s54, v40, 12 +; GISEL-NEXT: v_readlane_b32 s53, v40, 11 +; GISEL-NEXT: v_readlane_b32 s52, v40, 10 +; GISEL-NEXT: v_readlane_b32 s51, v40, 9 +; GISEL-NEXT: v_readlane_b32 s50, v40, 8 +; GISEL-NEXT: v_readlane_b32 s49, v40, 7 +; GISEL-NEXT: v_readlane_b32 s48, v40, 6 +; GISEL-NEXT: v_readlane_b32 s39, v40, 5 +; GISEL-NEXT: v_readlane_b32 s38, v40, 4 +; GISEL-NEXT: v_readlane_b32 s37, v40, 3 +; GISEL-NEXT: v_readlane_b32 s36, v40, 2 +; GISEL-NEXT: v_readlane_b32 s35, v40, 1 +; GISEL-NEXT: v_readlane_b32 s34, v40, 0 ; GISEL-NEXT: s_mov_b32 s32, s33 ; GISEL-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GISEL-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload @@ -982,22 +982,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_reuse(i32 %i, ptr %fptr) { ; GCN-NEXT: s_mov_b64 exec, s[4:5] ; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: v_writelane_b32 v41, s30, 0 -; GCN-NEXT: v_writelane_b32 v41, s31, 1 -; GCN-NEXT: v_writelane_b32 v41, s34, 2 -; GCN-NEXT: v_writelane_b32 v41, s35, 3 -; GCN-NEXT: v_writelane_b32 v41, s36, 4 -; GCN-NEXT: v_writelane_b32 v41, s37, 5 -; GCN-NEXT: v_writelane_b32 v41, s38, 6 -; GCN-NEXT: v_writelane_b32 v41, s39, 7 -; GCN-NEXT: v_writelane_b32 v41, s48, 8 -; GCN-NEXT: v_writelane_b32 v41, s49, 9 -; GCN-NEXT: v_writelane_b32 v41, s50, 10 -; GCN-NEXT: v_writelane_b32 v41, s51, 11 -; GCN-NEXT: v_writelane_b32 v41, s52, 12 -; GCN-NEXT: v_writelane_b32 v41, s53, 13 -; GCN-NEXT: v_writelane_b32 v41, s54, 14 -; GCN-NEXT: v_writelane_b32 v41, s55, 15 +; GCN-NEXT: v_writelane_b32 v41, s34, 0 +; GCN-NEXT: v_writelane_b32 v41, s35, 1 +; GCN-NEXT: v_writelane_b32 v41, s36, 2 +; GCN-NEXT: v_writelane_b32 v41, s37, 3 +; GCN-NEXT: v_writelane_b32 v41, s38, 4 +; GCN-NEXT: v_writelane_b32 v41, s39, 5 +; GCN-NEXT: v_writelane_b32 v41, s48, 6 +; GCN-NEXT: v_writelane_b32 v41, s49, 7 +; GCN-NEXT: v_writelane_b32 v41, s50, 8 +; GCN-NEXT: v_writelane_b32 v41, s51, 9 +; GCN-NEXT: v_writelane_b32 v41, s52, 10 +; GCN-NEXT: v_writelane_b32 v41, s53, 11 +; GCN-NEXT: v_writelane_b32 v41, s54, 12 +; GCN-NEXT: v_writelane_b32 v41, s55, 13 +; GCN-NEXT: v_writelane_b32 v41, s30, 14 +; GCN-NEXT: v_writelane_b32 v41, s31, 15 ; GCN-NEXT: v_mov_b32_e32 v40, v0 ; GCN-NEXT: s_mov_b64 s[4:5], exec ; GCN-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 @@ -1013,22 +1013,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_reuse(i32 %i, ptr %fptr) { ; GCN-NEXT: ; %bb.2: ; GCN-NEXT: s_mov_b64 exec, s[4:5] ; GCN-NEXT: v_mov_b32_e32 v0, v40 -; GCN-NEXT: v_readlane_b32 s55, v41, 15 -; GCN-NEXT: v_readlane_b32 s54, v41, 14 -; GCN-NEXT: v_readlane_b32 s53, v41, 13 -; GCN-NEXT: v_readlane_b32 s52, v41, 12 -; GCN-NEXT: v_readlane_b32 s51, v41, 11 -; GCN-NEXT: v_readlane_b32 s50, v41, 10 -; GCN-NEXT: v_readlane_b32 s49, v41, 9 -; GCN-NEXT: v_readlane_b32 s48, v41, 8 -; GCN-NEXT: v_readlane_b32 s39, v41, 7 -; GCN-NEXT: v_readlane_b32 s38, v41, 6 -; GCN-NEXT: v_readlane_b32 s37, v41, 5 -; GCN-NEXT: v_readlane_b32 s36, v41, 4 -; GCN-NEXT: v_readlane_b32 s35, v41, 3 -; GCN-NEXT: v_readlane_b32 s34, v41, 2 -; GCN-NEXT: v_readlane_b32 s31, v41, 1 -; GCN-NEXT: v_readlane_b32 s30, v41, 0 +; GCN-NEXT: v_readlane_b32 s30, v41, 14 +; GCN-NEXT: v_readlane_b32 s31, v41, 15 +; GCN-NEXT: v_readlane_b32 s55, v41, 13 +; GCN-NEXT: v_readlane_b32 s54, v41, 12 +; GCN-NEXT: v_readlane_b32 s53, v41, 11 +; GCN-NEXT: v_readlane_b32 s52, v41, 10 +; GCN-NEXT: v_readlane_b32 s51, v41, 9 +; GCN-NEXT: v_readlane_b32 s50, v41, 8 +; GCN-NEXT: v_readlane_b32 s49, v41, 7 +; GCN-NEXT: v_readlane_b32 s48, v41, 6 +; GCN-NEXT: v_readlane_b32 s39, v41, 5 +; GCN-NEXT: v_readlane_b32 s38, v41, 4 +; GCN-NEXT: v_readlane_b32 s37, v41, 3 +; GCN-NEXT: v_readlane_b32 s36, v41, 2 +; GCN-NEXT: v_readlane_b32 s35, v41, 1 +; GCN-NEXT: v_readlane_b32 s34, v41, 0 ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1 @@ -1048,22 +1048,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_reuse(i32 %i, ptr %fptr) { ; GISEL-NEXT: s_mov_b64 exec, s[4:5] ; GISEL-NEXT: s_addk_i32 s32, 0x400 ; GISEL-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GISEL-NEXT: v_writelane_b32 v41, s30, 0 -; GISEL-NEXT: v_writelane_b32 v41, s31, 1 -; GISEL-NEXT: v_writelane_b32 v41, s34, 2 -; GISEL-NEXT: v_writelane_b32 v41, s35, 3 -; GISEL-NEXT: v_writelane_b32 v41, s36, 4 -; GISEL-NEXT: v_writelane_b32 v41, s37, 5 -; GISEL-NEXT: v_writelane_b32 v41, s38, 6 -; GISEL-NEXT: v_writelane_b32 v41, s39, 7 -; GISEL-NEXT: v_writelane_b32 v41, s48, 8 -; GISEL-NEXT: v_writelane_b32 v41, s49, 9 -; GISEL-NEXT: v_writelane_b32 v41, s50, 10 -; GISEL-NEXT: v_writelane_b32 v41, s51, 11 -; GISEL-NEXT: v_writelane_b32 v41, s52, 12 -; GISEL-NEXT: v_writelane_b32 v41, s53, 13 -; GISEL-NEXT: v_writelane_b32 v41, s54, 14 -; GISEL-NEXT: v_writelane_b32 v41, s55, 15 +; GISEL-NEXT: v_writelane_b32 v41, s34, 0 +; GISEL-NEXT: v_writelane_b32 v41, s35, 1 +; GISEL-NEXT: v_writelane_b32 v41, s36, 2 +; GISEL-NEXT: v_writelane_b32 v41, s37, 3 +; GISEL-NEXT: v_writelane_b32 v41, s38, 4 +; GISEL-NEXT: v_writelane_b32 v41, s39, 5 +; GISEL-NEXT: v_writelane_b32 v41, s48, 6 +; GISEL-NEXT: v_writelane_b32 v41, s49, 7 +; GISEL-NEXT: v_writelane_b32 v41, s50, 8 +; GISEL-NEXT: v_writelane_b32 v41, s51, 9 +; GISEL-NEXT: v_writelane_b32 v41, s52, 10 +; GISEL-NEXT: v_writelane_b32 v41, s53, 11 +; GISEL-NEXT: v_writelane_b32 v41, s54, 12 +; GISEL-NEXT: v_writelane_b32 v41, s55, 13 +; GISEL-NEXT: v_writelane_b32 v41, s30, 14 +; GISEL-NEXT: v_writelane_b32 v41, s31, 15 ; GISEL-NEXT: v_mov_b32_e32 v40, v0 ; GISEL-NEXT: s_mov_b64 s[4:5], exec ; GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 @@ -1079,22 +1079,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_reuse(i32 %i, ptr %fptr) { ; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: s_mov_b64 exec, s[4:5] ; GISEL-NEXT: v_mov_b32_e32 v0, v40 -; GISEL-NEXT: v_readlane_b32 s55, v41, 15 -; GISEL-NEXT: v_readlane_b32 s54, v41, 14 -; GISEL-NEXT: v_readlane_b32 s53, v41, 13 -; GISEL-NEXT: v_readlane_b32 s52, v41, 12 -; GISEL-NEXT: v_readlane_b32 s51, v41, 11 -; GISEL-NEXT: v_readlane_b32 s50, v41, 10 -; GISEL-NEXT: v_readlane_b32 s49, v41, 9 -; GISEL-NEXT: v_readlane_b32 s48, v41, 8 -; GISEL-NEXT: v_readlane_b32 s39, v41, 7 -; GISEL-NEXT: v_readlane_b32 s38, v41, 6 -; GISEL-NEXT: v_readlane_b32 s37, v41, 5 -; GISEL-NEXT: v_readlane_b32 s36, v41, 4 -; GISEL-NEXT: v_readlane_b32 s35, v41, 3 -; GISEL-NEXT: v_readlane_b32 s34, v41, 2 -; GISEL-NEXT: v_readlane_b32 s31, v41, 1 -; GISEL-NEXT: v_readlane_b32 s30, v41, 0 +; GISEL-NEXT: v_readlane_b32 s30, v41, 14 +; GISEL-NEXT: v_readlane_b32 s31, v41, 15 +; GISEL-NEXT: v_readlane_b32 s55, v41, 13 +; GISEL-NEXT: v_readlane_b32 s54, v41, 12 +; GISEL-NEXT: v_readlane_b32 s53, v41, 11 +; GISEL-NEXT: v_readlane_b32 s52, v41, 10 +; GISEL-NEXT: v_readlane_b32 s51, v41, 9 +; GISEL-NEXT: v_readlane_b32 s50, v41, 8 +; GISEL-NEXT: v_readlane_b32 s49, v41, 7 +; GISEL-NEXT: v_readlane_b32 s48, v41, 6 +; GISEL-NEXT: v_readlane_b32 s39, v41, 5 +; GISEL-NEXT: v_readlane_b32 s38, v41, 4 +; GISEL-NEXT: v_readlane_b32 s37, v41, 3 +; GISEL-NEXT: v_readlane_b32 s36, v41, 2 +; GISEL-NEXT: v_readlane_b32 s35, v41, 1 +; GISEL-NEXT: v_readlane_b32 s34, v41, 0 ; GISEL-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload ; GISEL-NEXT: s_mov_b32 s32, s33 ; GISEL-NEXT: s_or_saveexec_b64 s[4:5], -1 @@ -1121,22 +1121,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_return(i32 %i, ptr %fptr) { ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[4:5] ; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: v_writelane_b32 v40, s34, 2 -; GCN-NEXT: v_writelane_b32 v40, s35, 3 -; GCN-NEXT: v_writelane_b32 v40, s36, 4 -; GCN-NEXT: v_writelane_b32 v40, s37, 5 -; GCN-NEXT: v_writelane_b32 v40, s38, 6 -; GCN-NEXT: v_writelane_b32 v40, s39, 7 -; GCN-NEXT: v_writelane_b32 v40, s48, 8 -; GCN-NEXT: v_writelane_b32 v40, s49, 9 -; GCN-NEXT: v_writelane_b32 v40, s50, 10 -; GCN-NEXT: v_writelane_b32 v40, s51, 11 -; GCN-NEXT: v_writelane_b32 v40, s52, 12 -; GCN-NEXT: v_writelane_b32 v40, s53, 13 -; GCN-NEXT: v_writelane_b32 v40, s54, 14 -; GCN-NEXT: v_writelane_b32 v40, s55, 15 +; GCN-NEXT: v_writelane_b32 v40, s34, 0 +; GCN-NEXT: v_writelane_b32 v40, s35, 1 +; GCN-NEXT: v_writelane_b32 v40, s36, 2 +; GCN-NEXT: v_writelane_b32 v40, s37, 3 +; GCN-NEXT: v_writelane_b32 v40, s38, 4 +; GCN-NEXT: v_writelane_b32 v40, s39, 5 +; GCN-NEXT: v_writelane_b32 v40, s48, 6 +; GCN-NEXT: v_writelane_b32 v40, s49, 7 +; GCN-NEXT: v_writelane_b32 v40, s50, 8 +; GCN-NEXT: v_writelane_b32 v40, s51, 9 +; GCN-NEXT: v_writelane_b32 v40, s52, 10 +; GCN-NEXT: v_writelane_b32 v40, s53, 11 +; GCN-NEXT: v_writelane_b32 v40, s54, 12 +; GCN-NEXT: v_writelane_b32 v40, s55, 13 +; GCN-NEXT: v_writelane_b32 v40, s30, 14 +; GCN-NEXT: v_writelane_b32 v40, s31, 15 ; GCN-NEXT: s_mov_b64 s[4:5], exec ; GCN-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: v_readfirstlane_b32 s8, v1 @@ -1152,22 +1152,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_return(i32 %i, ptr %fptr) { ; GCN-NEXT: ; %bb.2: ; GCN-NEXT: s_mov_b64 exec, s[4:5] ; GCN-NEXT: v_mov_b32_e32 v0, v3 -; GCN-NEXT: v_readlane_b32 s55, v40, 15 -; GCN-NEXT: v_readlane_b32 s54, v40, 14 -; GCN-NEXT: v_readlane_b32 s53, v40, 13 -; GCN-NEXT: v_readlane_b32 s52, v40, 12 -; GCN-NEXT: v_readlane_b32 s51, v40, 11 -; GCN-NEXT: v_readlane_b32 s50, v40, 10 -; GCN-NEXT: v_readlane_b32 s49, v40, 9 -; GCN-NEXT: v_readlane_b32 s48, v40, 8 -; GCN-NEXT: v_readlane_b32 s39, v40, 7 -; GCN-NEXT: v_readlane_b32 s38, v40, 6 -; GCN-NEXT: v_readlane_b32 s37, v40, 5 -; GCN-NEXT: v_readlane_b32 s36, v40, 4 -; GCN-NEXT: v_readlane_b32 s35, v40, 3 -; GCN-NEXT: v_readlane_b32 s34, v40, 2 -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s30, v40, 14 +; GCN-NEXT: v_readlane_b32 s31, v40, 15 +; GCN-NEXT: v_readlane_b32 s55, v40, 13 +; GCN-NEXT: v_readlane_b32 s54, v40, 12 +; GCN-NEXT: v_readlane_b32 s53, v40, 11 +; GCN-NEXT: v_readlane_b32 s52, v40, 10 +; GCN-NEXT: v_readlane_b32 s51, v40, 9 +; GCN-NEXT: v_readlane_b32 s50, v40, 8 +; GCN-NEXT: v_readlane_b32 s49, v40, 7 +; GCN-NEXT: v_readlane_b32 s48, v40, 6 +; GCN-NEXT: v_readlane_b32 s39, v40, 5 +; GCN-NEXT: v_readlane_b32 s38, v40, 4 +; GCN-NEXT: v_readlane_b32 s37, v40, 3 +; GCN-NEXT: v_readlane_b32 s36, v40, 2 +; GCN-NEXT: v_readlane_b32 s35, v40, 1 +; GCN-NEXT: v_readlane_b32 s34, v40, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload @@ -1185,22 +1185,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_return(i32 %i, ptr %fptr) { ; GISEL-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GISEL-NEXT: s_mov_b64 exec, s[4:5] ; GISEL-NEXT: s_addk_i32 s32, 0x400 -; GISEL-NEXT: v_writelane_b32 v40, s30, 0 -; GISEL-NEXT: v_writelane_b32 v40, s31, 1 -; GISEL-NEXT: v_writelane_b32 v40, s34, 2 -; GISEL-NEXT: v_writelane_b32 v40, s35, 3 -; GISEL-NEXT: v_writelane_b32 v40, s36, 4 -; GISEL-NEXT: v_writelane_b32 v40, s37, 5 -; GISEL-NEXT: v_writelane_b32 v40, s38, 6 -; GISEL-NEXT: v_writelane_b32 v40, s39, 7 -; GISEL-NEXT: v_writelane_b32 v40, s48, 8 -; GISEL-NEXT: v_writelane_b32 v40, s49, 9 -; GISEL-NEXT: v_writelane_b32 v40, s50, 10 -; GISEL-NEXT: v_writelane_b32 v40, s51, 11 -; GISEL-NEXT: v_writelane_b32 v40, s52, 12 -; GISEL-NEXT: v_writelane_b32 v40, s53, 13 -; GISEL-NEXT: v_writelane_b32 v40, s54, 14 -; GISEL-NEXT: v_writelane_b32 v40, s55, 15 +; GISEL-NEXT: v_writelane_b32 v40, s34, 0 +; GISEL-NEXT: v_writelane_b32 v40, s35, 1 +; GISEL-NEXT: v_writelane_b32 v40, s36, 2 +; GISEL-NEXT: v_writelane_b32 v40, s37, 3 +; GISEL-NEXT: v_writelane_b32 v40, s38, 4 +; GISEL-NEXT: v_writelane_b32 v40, s39, 5 +; GISEL-NEXT: v_writelane_b32 v40, s48, 6 +; GISEL-NEXT: v_writelane_b32 v40, s49, 7 +; GISEL-NEXT: v_writelane_b32 v40, s50, 8 +; GISEL-NEXT: v_writelane_b32 v40, s51, 9 +; GISEL-NEXT: v_writelane_b32 v40, s52, 10 +; GISEL-NEXT: v_writelane_b32 v40, s53, 11 +; GISEL-NEXT: v_writelane_b32 v40, s54, 12 +; GISEL-NEXT: v_writelane_b32 v40, s55, 13 +; GISEL-NEXT: v_writelane_b32 v40, s30, 14 +; GISEL-NEXT: v_writelane_b32 v40, s31, 15 ; GISEL-NEXT: s_mov_b64 s[4:5], exec ; GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: v_readfirstlane_b32 s8, v1 @@ -1216,22 +1216,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_return(i32 %i, ptr %fptr) { ; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: s_mov_b64 exec, s[4:5] ; GISEL-NEXT: v_mov_b32_e32 v0, v2 -; GISEL-NEXT: v_readlane_b32 s55, v40, 15 -; GISEL-NEXT: v_readlane_b32 s54, v40, 14 -; GISEL-NEXT: v_readlane_b32 s53, v40, 13 -; GISEL-NEXT: v_readlane_b32 s52, v40, 12 -; GISEL-NEXT: v_readlane_b32 s51, v40, 11 -; GISEL-NEXT: v_readlane_b32 s50, v40, 10 -; GISEL-NEXT: v_readlane_b32 s49, v40, 9 -; GISEL-NEXT: v_readlane_b32 s48, v40, 8 -; GISEL-NEXT: v_readlane_b32 s39, v40, 7 -; GISEL-NEXT: v_readlane_b32 s38, v40, 6 -; GISEL-NEXT: v_readlane_b32 s37, v40, 5 -; GISEL-NEXT: v_readlane_b32 s36, v40, 4 -; GISEL-NEXT: v_readlane_b32 s35, v40, 3 -; GISEL-NEXT: v_readlane_b32 s34, v40, 2 -; GISEL-NEXT: v_readlane_b32 s31, v40, 1 -; GISEL-NEXT: v_readlane_b32 s30, v40, 0 +; GISEL-NEXT: v_readlane_b32 s30, v40, 14 +; GISEL-NEXT: v_readlane_b32 s31, v40, 15 +; GISEL-NEXT: v_readlane_b32 s55, v40, 13 +; GISEL-NEXT: v_readlane_b32 s54, v40, 12 +; GISEL-NEXT: v_readlane_b32 s53, v40, 11 +; GISEL-NEXT: v_readlane_b32 s52, v40, 10 +; GISEL-NEXT: v_readlane_b32 s51, v40, 9 +; GISEL-NEXT: v_readlane_b32 s50, v40, 8 +; GISEL-NEXT: v_readlane_b32 s49, v40, 7 +; GISEL-NEXT: v_readlane_b32 s48, v40, 6 +; GISEL-NEXT: v_readlane_b32 s39, v40, 5 +; GISEL-NEXT: v_readlane_b32 s38, v40, 4 +; GISEL-NEXT: v_readlane_b32 s37, v40, 3 +; GISEL-NEXT: v_readlane_b32 s36, v40, 2 +; GISEL-NEXT: v_readlane_b32 s35, v40, 1 +; GISEL-NEXT: v_readlane_b32 s34, v40, 0 ; GISEL-NEXT: s_mov_b32 s32, s33 ; GISEL-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GISEL-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload @@ -1254,22 +1254,22 @@ define void @test_indirect_tail_call_vgpr_ptr(ptr %fptr) { ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[4:5] ; GCN-NEXT: s_addk_i32 s32, 0x400 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: v_writelane_b32 v40, s34, 2 -; GCN-NEXT: v_writelane_b32 v40, s35, 3 -; GCN-NEXT: v_writelane_b32 v40, s36, 4 -; GCN-NEXT: v_writelane_b32 v40, s37, 5 -; GCN-NEXT: v_writelane_b32 v40, s38, 6 -; GCN-NEXT: v_writelane_b32 v40, s39, 7 -; GCN-NEXT: v_writelane_b32 v40, s48, 8 -; GCN-NEXT: v_writelane_b32 v40, s49, 9 -; GCN-NEXT: v_writelane_b32 v40, s50, 10 -; GCN-NEXT: v_writelane_b32 v40, s51, 11 -; GCN-NEXT: v_writelane_b32 v40, s52, 12 -; GCN-NEXT: v_writelane_b32 v40, s53, 13 -; GCN-NEXT: v_writelane_b32 v40, s54, 14 -; GCN-NEXT: v_writelane_b32 v40, s55, 15 +; GCN-NEXT: v_writelane_b32 v40, s34, 0 +; GCN-NEXT: v_writelane_b32 v40, s35, 1 +; GCN-NEXT: v_writelane_b32 v40, s36, 2 +; GCN-NEXT: v_writelane_b32 v40, s37, 3 +; GCN-NEXT: v_writelane_b32 v40, s38, 4 +; GCN-NEXT: v_writelane_b32 v40, s39, 5 +; GCN-NEXT: v_writelane_b32 v40, s48, 6 +; GCN-NEXT: v_writelane_b32 v40, s49, 7 +; GCN-NEXT: v_writelane_b32 v40, s50, 8 +; GCN-NEXT: v_writelane_b32 v40, s51, 9 +; GCN-NEXT: v_writelane_b32 v40, s52, 10 +; GCN-NEXT: v_writelane_b32 v40, s53, 11 +; GCN-NEXT: v_writelane_b32 v40, s54, 12 +; GCN-NEXT: v_writelane_b32 v40, s55, 13 +; GCN-NEXT: v_writelane_b32 v40, s30, 14 +; GCN-NEXT: v_writelane_b32 v40, s31, 15 ; GCN-NEXT: s_mov_b64 s[4:5], exec ; GCN-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: v_readfirstlane_b32 s6, v0 @@ -1282,22 +1282,22 @@ define void @test_indirect_tail_call_vgpr_ptr(ptr %fptr) { ; GCN-NEXT: s_cbranch_execnz .LBB9_1 ; GCN-NEXT: ; %bb.2: ; GCN-NEXT: s_mov_b64 exec, s[4:5] -; GCN-NEXT: v_readlane_b32 s55, v40, 15 -; GCN-NEXT: v_readlane_b32 s54, v40, 14 -; GCN-NEXT: v_readlane_b32 s53, v40, 13 -; GCN-NEXT: v_readlane_b32 s52, v40, 12 -; GCN-NEXT: v_readlane_b32 s51, v40, 11 -; GCN-NEXT: v_readlane_b32 s50, v40, 10 -; GCN-NEXT: v_readlane_b32 s49, v40, 9 -; GCN-NEXT: v_readlane_b32 s48, v40, 8 -; GCN-NEXT: v_readlane_b32 s39, v40, 7 -; GCN-NEXT: v_readlane_b32 s38, v40, 6 -; GCN-NEXT: v_readlane_b32 s37, v40, 5 -; GCN-NEXT: v_readlane_b32 s36, v40, 4 -; GCN-NEXT: v_readlane_b32 s35, v40, 3 -; GCN-NEXT: v_readlane_b32 s34, v40, 2 -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s30, v40, 14 +; GCN-NEXT: v_readlane_b32 s31, v40, 15 +; GCN-NEXT: v_readlane_b32 s55, v40, 13 +; GCN-NEXT: v_readlane_b32 s54, v40, 12 +; GCN-NEXT: v_readlane_b32 s53, v40, 11 +; GCN-NEXT: v_readlane_b32 s52, v40, 10 +; GCN-NEXT: v_readlane_b32 s51, v40, 9 +; GCN-NEXT: v_readlane_b32 s50, v40, 8 +; GCN-NEXT: v_readlane_b32 s49, v40, 7 +; GCN-NEXT: v_readlane_b32 s48, v40, 6 +; GCN-NEXT: v_readlane_b32 s39, v40, 5 +; GCN-NEXT: v_readlane_b32 s38, v40, 4 +; GCN-NEXT: v_readlane_b32 s37, v40, 3 +; GCN-NEXT: v_readlane_b32 s36, v40, 2 +; GCN-NEXT: v_readlane_b32 s35, v40, 1 +; GCN-NEXT: v_readlane_b32 s34, v40, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload @@ -1315,22 +1315,22 @@ define void @test_indirect_tail_call_vgpr_ptr(ptr %fptr) { ; GISEL-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GISEL-NEXT: s_mov_b64 exec, s[4:5] ; GISEL-NEXT: s_addk_i32 s32, 0x400 -; GISEL-NEXT: v_writelane_b32 v40, s30, 0 -; GISEL-NEXT: v_writelane_b32 v40, s31, 1 -; GISEL-NEXT: v_writelane_b32 v40, s34, 2 -; GISEL-NEXT: v_writelane_b32 v40, s35, 3 -; GISEL-NEXT: v_writelane_b32 v40, s36, 4 -; GISEL-NEXT: v_writelane_b32 v40, s37, 5 -; GISEL-NEXT: v_writelane_b32 v40, s38, 6 -; GISEL-NEXT: v_writelane_b32 v40, s39, 7 -; GISEL-NEXT: v_writelane_b32 v40, s48, 8 -; GISEL-NEXT: v_writelane_b32 v40, s49, 9 -; GISEL-NEXT: v_writelane_b32 v40, s50, 10 -; GISEL-NEXT: v_writelane_b32 v40, s51, 11 -; GISEL-NEXT: v_writelane_b32 v40, s52, 12 -; GISEL-NEXT: v_writelane_b32 v40, s53, 13 -; GISEL-NEXT: v_writelane_b32 v40, s54, 14 -; GISEL-NEXT: v_writelane_b32 v40, s55, 15 +; GISEL-NEXT: v_writelane_b32 v40, s34, 0 +; GISEL-NEXT: v_writelane_b32 v40, s35, 1 +; GISEL-NEXT: v_writelane_b32 v40, s36, 2 +; GISEL-NEXT: v_writelane_b32 v40, s37, 3 +; GISEL-NEXT: v_writelane_b32 v40, s38, 4 +; GISEL-NEXT: v_writelane_b32 v40, s39, 5 +; GISEL-NEXT: v_writelane_b32 v40, s48, 6 +; GISEL-NEXT: v_writelane_b32 v40, s49, 7 +; GISEL-NEXT: v_writelane_b32 v40, s50, 8 +; GISEL-NEXT: v_writelane_b32 v40, s51, 9 +; GISEL-NEXT: v_writelane_b32 v40, s52, 10 +; GISEL-NEXT: v_writelane_b32 v40, s53, 11 +; GISEL-NEXT: v_writelane_b32 v40, s54, 12 +; GISEL-NEXT: v_writelane_b32 v40, s55, 13 +; GISEL-NEXT: v_writelane_b32 v40, s30, 14 +; GISEL-NEXT: v_writelane_b32 v40, s31, 15 ; GISEL-NEXT: s_mov_b64 s[4:5], exec ; GISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: v_readfirstlane_b32 s6, v0 @@ -1343,22 +1343,22 @@ define void @test_indirect_tail_call_vgpr_ptr(ptr %fptr) { ; GISEL-NEXT: s_cbranch_execnz .LBB9_1 ; GISEL-NEXT: ; %bb.2: ; GISEL-NEXT: s_mov_b64 exec, s[4:5] -; GISEL-NEXT: v_readlane_b32 s55, v40, 15 -; GISEL-NEXT: v_readlane_b32 s54, v40, 14 -; GISEL-NEXT: v_readlane_b32 s53, v40, 13 -; GISEL-NEXT: v_readlane_b32 s52, v40, 12 -; GISEL-NEXT: v_readlane_b32 s51, v40, 11 -; GISEL-NEXT: v_readlane_b32 s50, v40, 10 -; GISEL-NEXT: v_readlane_b32 s49, v40, 9 -; GISEL-NEXT: v_readlane_b32 s48, v40, 8 -; GISEL-NEXT: v_readlane_b32 s39, v40, 7 -; GISEL-NEXT: v_readlane_b32 s38, v40, 6 -; GISEL-NEXT: v_readlane_b32 s37, v40, 5 -; GISEL-NEXT: v_readlane_b32 s36, v40, 4 -; GISEL-NEXT: v_readlane_b32 s35, v40, 3 -; GISEL-NEXT: v_readlane_b32 s34, v40, 2 -; GISEL-NEXT: v_readlane_b32 s31, v40, 1 -; GISEL-NEXT: v_readlane_b32 s30, v40, 0 +; GISEL-NEXT: v_readlane_b32 s30, v40, 14 +; GISEL-NEXT: v_readlane_b32 s31, v40, 15 +; GISEL-NEXT: v_readlane_b32 s55, v40, 13 +; GISEL-NEXT: v_readlane_b32 s54, v40, 12 +; GISEL-NEXT: v_readlane_b32 s53, v40, 11 +; GISEL-NEXT: v_readlane_b32 s52, v40, 10 +; GISEL-NEXT: v_readlane_b32 s51, v40, 9 +; GISEL-NEXT: v_readlane_b32 s50, v40, 8 +; GISEL-NEXT: v_readlane_b32 s49, v40, 7 +; GISEL-NEXT: v_readlane_b32 s48, v40, 6 +; GISEL-NEXT: v_readlane_b32 s39, v40, 5 +; GISEL-NEXT: v_readlane_b32 s38, v40, 4 +; GISEL-NEXT: v_readlane_b32 s37, v40, 3 +; GISEL-NEXT: v_readlane_b32 s36, v40, 2 +; GISEL-NEXT: v_readlane_b32 s35, v40, 1 +; GISEL-NEXT: v_readlane_b32 s34, v40, 0 ; GISEL-NEXT: s_mov_b32 s32, s33 ; GISEL-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GISEL-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir b/llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir index 4d8fb8db624f8..2872cfd212273 100644 --- a/llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir +++ b/llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir @@ -19,6 +19,8 @@ body: | ; CHECK-LABEL: name: av_mov_b32_split ; CHECK: liveins: $agpr3, $agpr4, $vgpr0, $sgpr4_sgpr5 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: renamable $agpr0 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec ; CHECK-NEXT: renamable $agpr1 = V_ACCVGPR_WRITE_B32_e64 1, implicit $exec ; CHECK-NEXT: renamable $agpr2 = V_ACCVGPR_WRITE_B32_e64 2, implicit $exec @@ -68,6 +70,8 @@ body: | ; CHECK-LABEL: name: v_mov_b32_split ; CHECK: liveins: $agpr3, $agpr4, $vgpr0, $sgpr4_sgpr5 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: renamable $vgpr0 = V_MOV_B32_e32 0, implicit $exec ; CHECK-NEXT: renamable $vgpr1 = V_MOV_B32_e32 1, implicit $exec ; CHECK-NEXT: renamable $vgpr2 = V_MOV_B32_e32 2, implicit $exec @@ -120,6 +124,8 @@ body: | ; CHECK-LABEL: name: av_mov_b64_split ; CHECK: liveins: $agpr6, $agpr7, $agpr8, $agpr9, $vgpr0, $sgpr4_sgpr5 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec, implicit-def $agpr0_agpr1 ; CHECK-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec, implicit-def $agpr0_agpr1 ; CHECK-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 1, implicit $exec, implicit-def $agpr2_agpr3 diff --git a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll index c3f391786f878..3be6682bc4ffa 100644 --- a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll +++ b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll @@ -25,18 +25,17 @@ define void @f0() { ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v4, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 +; GFX11-NEXT: v_writelane_b32 v4, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v4, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, f1@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, f1@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v4, s30, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: v_writelane_b32 v4, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s31, v4, 1 ; GFX11-NEXT: v_readlane_b32 s30, v4, 0 +; GFX11-NEXT: v_readlane_b32 s31, v4, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v4, off, s33 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll index 58cd2f5bc11af..ec007af2a68b5 100644 --- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll @@ -7,16 +7,998 @@ define fastcc i32 @foo() { ; CHECK-LABEL: name: foo ; CHECK: bb.0 (%ir-block.0): ; CHECK-NEXT: successors: %bb.1(0x80000000) - ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr30, $sgpr31, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11 + ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr144 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr145 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr146 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr147 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr148 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr149 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr150 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr151 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr160 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr161 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr162 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr163 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr164 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr165 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr166 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr167 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr176 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr177 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr178 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr179 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr180 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr181 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr182 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr183 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr193 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr194 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr195 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr196 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr197 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr198 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr199 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr208 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr209 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr210 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr211 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr212 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr213 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr214 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr215 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr224 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr225 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr226 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr227 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr228 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr229 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr230 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr231 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; CHECK-NEXT: S_WAITCNT 0 ; CHECK-NEXT: $sgpr16 = S_MOV_B32 $sgpr33 ; CHECK-NEXT: $sgpr33 = S_MOV_B32 $sgpr32 ; CHECK-NEXT: $sgpr17 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr40, 0 ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr17 - ; CHECK-NEXT: $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr16, 2, undef $vgpr40 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr33, $vgpr40, 2, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 + ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31 + ; CHECK-NEXT: $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc + ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr40, 0, 32, $vgpr40, 1, 32 ; CHECK-NEXT: BUNDLE implicit-def $sgpr16_sgpr17, implicit-def $sgpr16, implicit-def $scc, implicit-def $sgpr17 { ; CHECK-NEXT: $sgpr16_sgpr17 = S_GETPC_B64 ; CHECK-NEXT: $sgpr16 = S_ADD_U32 internal $sgpr16, target-flags(amdgpu-gotprel32-lo) @bar + 4, implicit-def $scc @@ -26,8 +1008,6 @@ define fastcc i32 @foo() { ; CHECK-NEXT: BUFFER_GL1_INV implicit $exec ; CHECK-NEXT: BUFFER_GL0_INV implicit $exec ; CHECK-NEXT: renamable $sgpr16_sgpr17 = S_LOAD_DWORDX2_IMM killed renamable $sgpr16_sgpr17, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4) - ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40 - ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40 ; CHECK-NEXT: S_WAITCNT 49279 ; CHECK-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr16_sgpr17, @bar, csr_amdgpu, implicit killed $sgpr4_sgpr5, implicit killed $sgpr6_sgpr7, implicit killed $sgpr8_sgpr9, implicit killed $sgpr10_sgpr11, implicit killed $sgpr12, implicit killed $sgpr13, implicit killed $sgpr14, implicit killed $sgpr15, implicit killed $vgpr31, implicit $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $vcc_lo = S_MOV_B32 $exec_lo @@ -39,13 +1019,14 @@ define fastcc i32 @foo() { ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2.DummyReturnBlock: + ; CHECK-NEXT: $sgpr30 = V_READLANE_B32 $vgpr40, 0, implicit-def $sgpr30_sgpr31 ; CHECK-NEXT: $sgpr31 = V_READLANE_B32 $vgpr40, 1 - ; CHECK-NEXT: $sgpr30 = V_READLANE_B32 $vgpr40, 0 ; CHECK-NEXT: $sgpr32 = S_MOV_B32 $sgpr33 ; CHECK-NEXT: $sgpr4 = V_READLANE_B32 $vgpr40, 2 ; CHECK-NEXT: $sgpr5 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; CHECK-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr5 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; CHECK-NEXT: $sgpr33 = S_MOV_B32 killed $sgpr4 ; CHECK-NEXT: S_WAITCNT 16240 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit undef $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir b/llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir index 786ce40203836..e44736584767b 100644 --- a/llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir +++ b/llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir @@ -14,6 +14,8 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $sgpr0, $vgpr2 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir b/llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir index 86b6c5982b4cb..4d2fd61ac5033 100644 --- a/llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir +++ b/llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir @@ -19,6 +19,8 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $sgpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} @@ -67,6 +69,8 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $sgpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} @@ -115,6 +119,8 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $sgpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} @@ -164,6 +170,8 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $sgpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} @@ -215,6 +223,8 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $sgpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} @@ -270,8 +280,985 @@ body: | ; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: liveins: $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr144 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr145 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr146 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr147 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr148 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr149 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr150 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr151 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr160 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr161 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr162 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr163 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr164 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr165 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr166 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr167 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr176 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr177 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr178 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr179 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr180 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr181 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr182 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr183 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr193 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr194 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr195 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr196 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr197 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr198 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr199 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr208 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr209 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr210 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr211 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr212 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr213 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr214 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr215 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr224 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr225 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr226 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr227 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr228 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr229 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr230 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr231 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; CHECK-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr40, 0 ; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; CHECK-NEXT: $vgpr40 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr40 ; CHECK-NEXT: $vgpr40 = SI_SPILL_S32_TO_VGPR $sgpr31, 1, $vgpr40 diff --git a/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir b/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir index 7a913cf50ea2b..f96c3c56896c0 100644 --- a/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir +++ b/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir @@ -31,6 +31,8 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: $sgpr33 = S_MOV_B32 0 ; CHECK-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.b128.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.b128.ll new file mode 100644 index 0000000000000..1dcae2c264baa --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.b128.ll @@ -0,0 +1,2790 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX,GFX-SDAG,GFX942-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX,GFX-SDAG,GFX950-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx9-4-generic < %s | FileCheck -check-prefixes=GFX,GFX-SDAG,GFX9-4-GENERIC-SDAG %s + +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX,GFX-ISEL,GFX942-ISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX,GFX-ISEL,GFX950-ISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx9-4-generic < %s | FileCheck -check-prefixes=GFX,GFX-ISEL,GFX9-4-GENERIC-ISEL %s + + +;;============================================================================== +;; A few basic test cases +;;============================================================================== +define <4 x i32> @global_load_b128_0_00(ptr addrspace(1) %addr) { +; GFX-LABEL: global_load_b128_0_00: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !0) + ret <4 x i32> %data +} + +define <4 x i32> @global_load_b128_0_01(ptr addrspace(1) %addr) { +; GFX-LABEL: global_load_b128_0_01: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !1) + ret <4 x i32> %data +} + +define <4 x i32> @global_load_b128_0_10(ptr addrspace(1) %addr) { +; GFX-LABEL: global_load_b128_0_10: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !2) + ret <4 x i32> %data +} + +define <4 x i32> @global_load_b128_0_11(ptr addrspace(1) %addr) { +; GFX-LABEL: global_load_b128_0_11: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !3) + ret <4 x i32> %data +} + +define <4 x i32> @global_load_b128_saddr_0_00(ptr addrspace(1) inreg %addr) { +; GFX-LABEL: global_load_b128_saddr_0_00: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !0) + ret <4 x i32> %data +} + +define <4 x i32> @global_load_b128_saddr_0_01(ptr addrspace(1) inreg %addr) { +; GFX-LABEL: global_load_b128_saddr_0_01: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !1) + ret <4 x i32> %data +} + +define <4 x i32> @global_load_b128_saddr_0_02(ptr addrspace(1) inreg %addr) { +; GFX-LABEL: global_load_b128_saddr_0_02: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !2) + ret <4 x i32> %data +} + +define <4 x i32> @global_load_b128_saddr_0_03(ptr addrspace(1) inreg %addr) { +; GFX-LABEL: global_load_b128_saddr_0_03: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !3) + ret <4 x i32> %data +} + +;;============================================================================== +;; Signed offset addressing modes (derived from global-saddr-load.ll) { +;;============================================================================== +;;------------------------------------------------------------------------------ +;; No vgpr offset, constants +;;------------------------------------------------------------------------------ + +;; base only +define <4 x float> @global_load_i8_offset_0(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_0: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %sbase, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum gfx9 immediate offset +define <4 x float> @global_load_i8_offset_4095(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_4095: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4095 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum gfx9 immediate offset + 1 +define <4 x float> @global_load_i8_offset_4096(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_4096: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX-NEXT: s_nop 1 +; GFX-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4096 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum gfx9 immediate offset + 2 +define <4 x float> @global_load_i8_offset_4097(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_4097: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:1 sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_4097: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0x1001, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4097 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum negative gfx9 immediate offset +define <4 x float> @global_load_i8_offset_neg4096(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_neg4096: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-4096 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4096 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum negative gfx9 immediate offset -1 +define <4 x float> @global_load_i8_offset_neg4097(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_neg4097: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-1 sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_neg4097: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffefff, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4097 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum negative gfx9 immediate offset -2 +define <4 x float> @global_load_i8_offset_neg4098(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_neg4098: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-2 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_neg4098: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffeffe, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4098 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum gfx10 immediate offset +define <4 x float> @global_load_i8_offset_2048(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_2048: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:2048 sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 2048 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum gfx10 immediate offset + 1 +define <4 x float> @global_load_i8_offset_2049(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_2049: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:2049 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 2049 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum gfx10 immediate offset + 2 +define <4 x float> @global_load_i8_offset_2050(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_2050: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:2050 sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 2050 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum negative gfx10 immediate offset +define <4 x float> @global_load_i8_offset_neg2048(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_neg2048: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-2048 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -2048 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum negative gfx10 immediate offset - 1 +define <4 x float> @global_load_i8_offset_neg2049(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_neg2049: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-2049 sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -2049 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; base with maximum negative gfx10 immediate offset - 1 +define <4 x float> @global_load_i8_offset_neg2050(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_neg2050: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-2050 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -2050 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_0x7FFFFF(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_0x7FFFFF: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x7ff000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_0x7FFFFF: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0x7fffff, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 8388607 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_0xFFFFFF(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_0xFFFFFF: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_add_co_u32_e32 v0, vcc, 0xff800000, v0 +; GFX-NEXT: s_nop 1 +; GFX-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -8388608 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_0xFFFFFFFF(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_0xFFFFFFFF: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_0xFFFFFFFF: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, -1, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4294967295 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_0x100000000(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_0x100000000: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_0x100000000: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4294967296 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_0x100000001(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_0x100000001: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:1 sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_0x100000001: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4294967297 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_0x100000FFF(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_0x100000FFF: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_0x100000FFF: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xfff, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4294971391 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_0x100001000(ptr addrspace(1) %sbase) { +; GFX-LABEL: global_load_i8_offset_0x100001000: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX-NEXT: s_nop 1 +; GFX-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4294971392 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_neg0xFFFFFFFF(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_neg0xFFFFFFFF: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-4095 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_neg0xFFFFFFFF: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4294967295 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_neg0x100000000(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_neg0x100000000: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_neg0x100000000: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4294967296 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_neg0x100000001(ptr addrspace(1) %sbase) { +; +; GFX-SDAG-LABEL: global_load_i8_offset_neg0x100000001: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-1 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_offset_neg0x100000001: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, -1, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -2, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4294967297 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;;------------------------------------------------------------------------------ +;; Basic addressing patterns +;;------------------------------------------------------------------------------ + +;; Basic pattern, no immediate offset. +define <4 x float> @global_load_i8_zext_vgpr(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum positive offset on gfx9 +define <4 x float> @global_load_i8_zext_vgpr_offset_4095(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_4095: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_4095: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 4095 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum positive offset on gfx9 + 1 +define <4 x float> @global_load_i8_zext_vgpr_offset_4096(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_4096: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_4096: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 4096 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum negative offset on gfx9 +define <4 x float> @global_load_i8_zext_vgpr_offset_neg4096(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_neg4096: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-4096 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_neg4096: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-4096 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -4096 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum negative offset on gfx9 - 1 +define <4 x float> @global_load_i8_zext_vgpr_offset_neg4097(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_neg4097: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-1 sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_neg4097: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffefff, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -4097 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum positive offset on gfx10 +define <4 x float> @global_load_i8_zext_vgpr_offset_2047(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_2047: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:2047 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_2047: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:2047 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 2047 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum positive offset on gfx10 + 1 +define <4 x float> @global_load_i8_zext_vgpr_offset_2048(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_2048: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:2048 sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_2048: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:2048 sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 2048 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum negative offset on gfx10 +define <4 x float> @global_load_i8_zext_vgpr_offset_neg2048(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_neg2048: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-2048 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_neg2048: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-2048 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -2048 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum negative offset on gfx10 - 1 +define <4 x float> @global_load_i8_zext_vgpr_offset_neg2049(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_neg2049: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-2049 sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_neg2049: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-2049 sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -2049 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum positive offset on gfx12. +define <4 x float> @global_load_i8_zext_vgpr_offset_0x7FFFFF(ptr addrspace(1) %sbase, i32 %voffset) { %zext.offset = zext i32 %voffset to i64 +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_0x7FFFFF: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x7ff000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_0x7FFFFF: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0x7fffff, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 8388607 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Minimum offset on gfx12. +define <4 x float> @global_load_i8_zext_vgpr_offset_0xFFFFFF(ptr addrspace(1) %sbase, i32 %voffset) { %zext.offset = zext i32 %voffset to i64 +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_0xFFFFFF: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xff800000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_0xFFFFFF: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xff800000, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -8388608 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + + +;; Maximum positive offset on gfx9, and immediate needs to be moved lower. +define <4 x float> @global_load_i8_zext_vgpr_offset_4095_gep_order(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_offset_4095_gep_order: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_offset_4095_gep_order: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4095 + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; pointer addressing done in integers +define <4 x float> @global_load_i8_zext_vgpr_ptrtoint(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_ptrtoint: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_ptrtoint: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add = add i64 %sbase.as.int, %zext.offset + %dirty.gep = inttoptr i64 %add to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; zext forced to LHS of addressing expression +define <4 x float> @global_load_i8_zext_vgpr_ptrtoint_commute_add(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_ptrtoint_commute_add: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 0, v[0:1] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_ptrtoint_commute_add: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add = add i64 %zext.offset, %sbase.as.int + %dirty.gep = inttoptr i64 %add to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; zext forced to LHS of addressing expression, with immediate offset +define <4 x float> @global_load_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 0, v[0:1] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add = add i64 %zext.offset, %sbase.as.int + %add.immoffset = add i64 %add, 128 + %dirty.gep = inttoptr i64 %add.immoffset to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; zext forced to LHS of addressing expression, with immediate offset in non-canonical position +define <4 x float> @global_load_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1(ptr addrspace(1) %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add.immoffset = add i64 %sbase.as.int, 128 + %add = add i64 %zext.offset, %add.immoffset + %dirty.gep = inttoptr i64 %add to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;;------------------------------------------------------------------------------ +;; Uniformity edge cases +;;------------------------------------------------------------------------------ + +;; Both 64-bit base and 32-bit offset are scalar +define <4 x float> @global_load_i8_zext_uniform_offset(ptr addrspace(1) %sbase, i32 %soffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_uniform_offset: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_uniform_offset: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Both 64-bit base and 32-bit offset are scalar, with immediate offset. +define <4 x float> @global_load_i8_zext_uniform_offset_immoffset(ptr addrspace(1) %sbase, i32 %soffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_uniform_offset_immoffset: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-24 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_uniform_offset_immoffset: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-24 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -24 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Both components uniform, zext forced to LHS of addressing expression +define <4 x float> @global_load_i8_zext_sgpr_ptrtoint_commute_add(ptr addrspace(1) %sbase, i32 %soffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_sgpr_ptrtoint_commute_add: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 0, v[0:1] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_sgpr_ptrtoint_commute_add: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add = add i64 %zext.offset, %sbase.as.int + %dirty.gep = inttoptr i64 %add to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Both components uniform, zext forced to LHS of addressing expression, with immediate offset +define <4 x float> @global_load_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0(ptr addrspace(1) %sbase, i32 %soffset) { +; +; GFX-SDAG-LABEL: global_load_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 0, v[0:1] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add = add i64 %zext.offset, %sbase.as.int + %add.immoffset = add i64 %add, 128 + %dirty.gep = inttoptr i64 %add.immoffset to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; divergent 64-bit base, 32-bit scalar offset. +define <4 x float> @global_load_i8_vgpr64_sgpr32(ptr addrspace(1) %vbase, i32 %soffset) { +; +; GFX-SDAG-LABEL: global_load_i8_vgpr64_sgpr32: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_vgpr64_sgpr32: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %vbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; divergent 64-bit base, 32-bit scalar offset, with imm offset +define <4 x float> @global_load_i8_vgpr64_sgpr32_offset_4095(ptr addrspace(1) %vbase, i32 %soffset) { +; +; GFX-SDAG-LABEL: global_load_i8_vgpr64_sgpr32_offset_4095: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_i8_vgpr64_sgpr32_offset_4095: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %vbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 4095 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;;------------------------------------------------------------------------------ +;; Natural addressing shifts with restricted range +;;------------------------------------------------------------------------------ + +;; Cannot push the shift into 32-bits, and cannot match. +define <4 x float> @global_load_f32_natural_addressing(ptr addrspace(1) %sbase, ptr addrspace(1) %voffset.ptr) { +; GFX-LABEL: global_load_f32_natural_addressing: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dword v2, v[2:3], off +; GFX-NEXT: v_mov_b32_e32 v3, 0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1] +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr + %zext.offset = zext i32 %voffset to i64 + %gep = getelementptr inbounds float, ptr addrspace(1) %sbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Cannot push the shift into 32-bits, with an immediate offset. +define <4 x float> @global_load_f32_natural_addressing_immoffset(ptr addrspace(1) %sbase, ptr addrspace(1) %voffset.ptr) { +; +; GFX-SDAG-LABEL: global_load_f32_natural_addressing_immoffset: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: global_load_dword v2, v[2:3], off +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_f32_natural_addressing_immoffset: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: global_load_dword v2, v[2:3], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 128 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Range is sufficiently restricted to push the shift into 32-bits. +define <4 x float> @global_load_f32_zext_vgpr_range(ptr addrspace(1) %sbase, ptr addrspace(1) %voffset.ptr) { +; +; GFX-SDAG-LABEL: global_load_f32_zext_vgpr_range: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: global_load_dword v2, v[2:3], off +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v2 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_f32_zext_vgpr_range: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: global_load_dword v2, v[2:3], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v2 +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr, !range !4, !noundef !{} + %zext.offset = zext i32 %voffset to i64 + %gep = getelementptr inbounds float, ptr addrspace(1) %sbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Range is sufficiently restricted to push the shift into 32-bits, with an imm offset +define <4 x float> @global_load_f32_zext_vgpr_range_imm_offset(ptr addrspace(1) %sbase, ptr addrspace(1) %voffset.ptr) { +; +; GFX-SDAG-LABEL: global_load_f32_zext_vgpr_range_imm_offset: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: global_load_dword v2, v[2:3], off +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v2 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:400 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_f32_zext_vgpr_range_imm_offset: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: global_load_dword v2, v[2:3], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v2 +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:400 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr, !range !4, !noundef !{} + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds float, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds float, ptr addrspace(1) %gep0, i64 100 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Range is 1 beyond the limit where we can move the shift into 32-bits. +define <4 x float> @global_load_f32_zext_vgpr_range_too_large(ptr addrspace(1) %sbase, ptr addrspace(1) %voffset.ptr) { +; GFX-LABEL: global_load_f32_zext_vgpr_range_too_large: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dword v2, v[2:3], off +; GFX-NEXT: v_mov_b32_e32 v3, 0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1] +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr, !range !5, !noundef !{} + %zext.offset = zext i32 %voffset to i64 + %gep = getelementptr inbounds float, ptr addrspace(1) %sbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;;------------------------------------------------------------------------------ +;; or-with-constant as add +;;------------------------------------------------------------------------------ + +;; Check add-as-or with split 64-bit or. +define <4 x float> @global_load_i8_offset_or_i64_imm_offset_16(ptr addrspace(6) %sbase, i32 %idx) { +; +; GFX-LABEL: global_load_i8_offset_or_i64_imm_offset_16: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_or_b32_e32 v0, 16, v1 +; GFX-NEXT: v_mov_b32_e32 v1, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.idx = zext i32 %idx to i64 + %or = or i64 %zext.idx, 16 + %addr = inttoptr i64 %or to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_i8_offset_or_i64_imm_offset_4160(ptr addrspace(6) %sbase, i32 %idx) { +; +; GFX-LABEL: global_load_i8_offset_or_i64_imm_offset_4160: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_or_b32_e32 v0, 0x1040, v1 +; GFX-NEXT: v_mov_b32_e32 v1, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.idx = zext i32 %idx to i64 + %or = or i64 %zext.idx, 4160 + %addr = inttoptr i64 %or to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;;------------------------------------------------------------------------------ +;; Full 64-bit scalar add. +;;------------------------------------------------------------------------------ +define <4 x float> @global_addr_64bit_lsr_iv(ptr addrspace(1) %arg) { +; +; GFX-SDAG-LABEL: global_addr_64bit_lsr_iv: +; GFX-SDAG: ; %bb.0: ; %bb +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: s_mov_b32 s0, -1 +; GFX-SDAG-NEXT: .LBB60_1: ; %bb3 +; GFX-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX-SDAG-NEXT: s_add_i32 s0, s0, 1 +; GFX-SDAG-NEXT: s_cmpk_eq_i32 s0, 0xff +; GFX-SDAG-NEXT: s_cbranch_scc0 .LBB60_1 +; GFX-SDAG-NEXT: ; %bb.2: ; %bb2 +; GFX-SDAG-NEXT: s_mov_b32 s1, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 2, v[0:1] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_addr_64bit_lsr_iv: +; GFX-ISEL: ; %bb.0: ; %bb +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_mov_b32 s0, -1 +; GFX-ISEL-NEXT: v_mov_b32_e32 v3, 0xff +; GFX-ISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX-ISEL-NEXT: .LBB60_1: ; %bb3 +; GFX-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX-ISEL-NEXT: v_add_u32_e32 v2, 1, v2 +; GFX-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX-ISEL-NEXT: s_cbranch_vccz .LBB60_1 +; GFX-ISEL-NEXT: ; %bb.2: ; %bb2 +; GFX-ISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] +bb: + br label %bb3 + +bb2: ; preds = %bb3 + ret <4 x float> %i6 + +bb3: ; preds = %bb3, %bb + %i = phi i32 [ 0, %bb ], [ %i8, %bb3 ] + %i4 = zext i32 %i to i64 + %i5 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %i4 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %i5, metadata !0) + %i6 = bitcast <4 x i32> %load to <4 x float> + %i8 = add nuw nsw i32 %i, 1 + %i9 = icmp eq i32 %i8, 256 + br i1 %i9, label %bb2, label %bb3 +} + +;; Make sure we only have a single zero vaddr initialization. + +define <4 x float> @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) %arg, ptr addrspace(1) %arg.1, i32 %x) { +; +; GFX-SDAG-LABEL: global_addr_64bit_lsr_iv_multiload: +; GFX-SDAG: ; %bb.0: ; %bb +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: s_mov_b32 s0, -1 +; GFX-SDAG-NEXT: .LBB61_1: ; %bb5 +; GFX-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX-SDAG-NEXT: s_add_i32 s0, s0, 1 +; GFX-SDAG-NEXT: s_cmpk_eq_i32 s0, 0xff +; GFX-SDAG-NEXT: s_cbranch_scc0 .LBB61_1 +; GFX-SDAG-NEXT: ; %bb.2: ; %bb2 +; GFX-SDAG-NEXT: s_mov_b32 s1, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 2, v[0:1] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_addr_64bit_lsr_iv_multiload: +; GFX-ISEL: ; %bb.0: ; %bb +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_mov_b32 s0, -1 +; GFX-ISEL-NEXT: v_mov_b32_e32 v3, 0xff +; GFX-ISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX-ISEL-NEXT: .LBB61_1: ; %bb5 +; GFX-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX-ISEL-NEXT: v_add_u32_e32 v2, 1, v2 +; GFX-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX-ISEL-NEXT: s_cbranch_vccz .LBB61_1 +; GFX-ISEL-NEXT: ; %bb.2: ; %bb2 +; GFX-ISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] +bb: + br label %bb5 + +bb2: + %y = icmp eq i32 %x, 0 + br i1 %y, label %bb3, label %bb4 + +bb3: + ret <4 x float> %i6 + +bb4: + ret <4 x float> %i6.1 + +bb5: + %i = phi i32 [ 0, %bb ], [ %i8, %bb5 ] + %i4 = zext i32 %i to i64 + %i5 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %i4 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %i5, metadata !1) + %i6 = bitcast <4 x i32> %load to <4 x float> + %i5.1 = getelementptr inbounds float, ptr addrspace(1) %arg.1, i64 %i4 + %load.1 = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %i5, metadata !2) + %i6.1 = bitcast <4 x i32> %load to <4 x float> + %i8 = add nuw nsw i32 %i, 1 + %i9 = icmp eq i32 %i8, 256 + br i1 %i9, label %bb2, label %bb5 +} +;;============================================================================== +;; } end signed offset addressing modes +;;============================================================================== + +;;============================================================================== +;; Various saddr addressing modes (derived from global-saddr-load.ll) { +;;============================================================================== + +;;------------------------------------------------------------------------------ +;; No vgpr offset, constants +;;------------------------------------------------------------------------------ + +;; SGPR base only +define <4 x float> @global_load_saddr_i8_offset_0(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_0: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %sbase, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum gfx9 immediate offset +define <4 x float> @global_load_saddr_i8_offset_4095(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_4095: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:4095 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4095 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum gfx9 immediate offset + 1 +define <4 x float> @global_load_saddr_i8_offset_4096(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_4096: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0x1000 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4096 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum gfx9 immediate offset + 2 +define <4 x float> @global_load_saddr_i8_offset_4097(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_4097: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0x1000 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:1 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4097 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum negative gfx9 immediate offset +define <4 x float> @global_load_saddr_i8_offset_neg4096(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_neg4096: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:-4096 sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4096 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum negative gfx9 immediate offset -1 +define <4 x float> @global_load_saddr_i8_offset_neg4097(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_neg4097: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: s_add_u32 s0, s0, 0xffffefff +; GFX-NEXT: s_addc_u32 s1, s1, -1 +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4097 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum negative gfx9 immediate offset -2 +define <4 x float> @global_load_saddr_i8_offset_neg4098(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_neg4098: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: s_add_u32 s0, s0, 0xffffeffe +; GFX-NEXT: s_addc_u32 s1, s1, -1 +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4098 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum gfx10 immediate offset +define <4 x float> @global_load_saddr_i8_offset_2048(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_2048: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:2048 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 2048 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum gfx10 immediate offset + 1 +define <4 x float> @global_load_saddr_i8_offset_2049(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_2049: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:2049 sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 2049 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum gfx10 immediate offset + 2 +define <4 x float> @global_load_saddr_i8_offset_2050(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_2050: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:2050 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 2050 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum negative gfx10 immediate offset +define <4 x float> @global_load_saddr_i8_offset_neg2048(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_neg2048: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:-2048 sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -2048 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum negative gfx10 immediate offset - 1 +define <4 x float> @global_load_saddr_i8_offset_neg2049(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_neg2049: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:-2049 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -2049 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; SGPR base with maximum negative gfx10 immediate offset - 1 +define <4 x float> @global_load_saddr_i8_offset_neg2050(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_neg2050: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:-2050 sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -2050 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_0x7FFFFF(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_0x7FFFFF: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0x7ff000 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:4095 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 8388607 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_0xFFFFFF(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_0xFFFFFF: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: s_add_u32 s0, s0, 0xff800000 +; GFX-NEXT: s_addc_u32 s1, s1, -1 +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -8388608 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_0xFFFFFFFF(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_0xFFFFFFFF: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, 0xfffff000 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:4095 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4294967295 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_0x100000000(ptr addrspace(1) inreg %sbase) { +; +; GFX-SDAG-LABEL: global_load_saddr_i8_offset_0x100000000: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: s_add_i32 s1, s1, 1 +; GFX-SDAG-NEXT: v_mov_b32_e32 v0, 0 +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_offset_0x100000000: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_add_u32 s0, s0, 0 +; GFX-ISEL-NEXT: s_addc_u32 s1, s1, 1 +; GFX-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4294967296 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_0x100000001(ptr addrspace(1) inreg %sbase) { +; +; GFX-SDAG-LABEL: global_load_saddr_i8_offset_0x100000001: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX-SDAG-NEXT: v_add_co_u32_e64 v0, vcc, 0, s0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_offset_0x100000001: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_add_u32 s0, s0, 1 +; GFX-ISEL-NEXT: s_addc_u32 s1, s1, 1 +; GFX-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4294967297 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_0x100000FFF(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_0x100000FFF: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: s_add_u32 s0, s0, 0xfff +; GFX-NEXT: s_addc_u32 s1, s1, 1 +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4294971391 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_0x100001000(ptr addrspace(1) inreg %sbase) { +; GFX-LABEL: global_load_saddr_i8_offset_0x100001000: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: s_add_u32 s0, s0, 0x1000 +; GFX-NEXT: s_addc_u32 s1, s1, 1 +; GFX-NEXT: v_mov_b32_e32 v0, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4294971392 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_neg0xFFFFFFFF(ptr addrspace(1) inreg %sbase) { +; +; GFX-SDAG-LABEL: global_load_saddr_i8_offset_neg0xFFFFFFFF: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX-SDAG-NEXT: s_nop 0 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-4095 sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_offset_neg0xFFFFFFFF: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_add_u32 s0, s0, 1 +; GFX-ISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4294967295 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_neg0x100000000(ptr addrspace(1) inreg %sbase) { +; +; GFX-SDAG-LABEL: global_load_saddr_i8_offset_neg0x100000000: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: s_add_i32 s1, s1, -1 +; GFX-SDAG-NEXT: v_mov_b32_e32 v0, 0 +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_offset_neg0x100000000: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_add_u32 s0, s0, 0 +; GFX-ISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4294967296 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_neg0x100000001(ptr addrspace(1) inreg %sbase) { +; +; GFX-SDAG-LABEL: global_load_saddr_i8_offset_neg0x100000001: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX-SDAG-NEXT: v_add_co_u32_e64 v0, vcc, 0, s0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-1 sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_offset_neg0x100000001: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_add_u32 s0, s0, -1 +; GFX-ISEL-NEXT: s_addc_u32 s1, s1, -2 +; GFX-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 -4294967297 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;;------------------------------------------------------------------------------ +;; Basic addressing patterns +;;------------------------------------------------------------------------------ + +;; Basic pattern, no immediate offset. +define <4 x float> @global_load_saddr_i8_zext_vgpr(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum positive offset on gfx9 +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_4095(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:4095 sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 4095 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum positive offset on gfx9 + 1 +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_4096(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_saddr_i8_zext_vgpr_offset_4096: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_zext_vgpr_offset_4096: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 4096 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum negative offset on gfx9 +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_neg4096(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4096: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:-4096 sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -4096 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum negative offset on gfx9 - 1 +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_neg4097(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; +; GFX-SDAG-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4097: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:-1 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4097: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffefff, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -4097 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum positive offset on gfx10 +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_2047(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_offset_2047: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:2047 sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 2047 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum positive offset on gfx10 + 1 +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_2048(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_offset_2048: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:2048 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 2048 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum negative offset on gfx10 +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_neg2048(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2048: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:-2048 sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -2048 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum negative offset on gfx10 - 1 +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_neg2049(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2049: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:-2049 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -2049 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Maximum positive offset on gfx12. +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF(ptr addrspace(1) inreg %sbase, i32 %voffset) { %zext.offset = zext i32 %voffset to i64 +; +; GFX-SDAG-LABEL: global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x7ff000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0x7fffff, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 8388607 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Minimum offset on gfx12. +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF(ptr addrspace(1) inreg %sbase, i32 %voffset) { %zext.offset = zext i32 %voffset to i64 +; +; GFX-SDAG-LABEL: global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xff800000, v0 +; GFX-SDAG-NEXT: s_nop 1 +; GFX-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xff800000, v0 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -8388608 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + + +;; Maximum positive offset on gfx9, and immediate needs to be moved lower. +define <4 x float> @global_load_saddr_i8_zext_vgpr_offset_4095_gep_order(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095_gep_order: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:4095 sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 4095 + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; pointer addressing done in integers +define <4 x float> @global_load_saddr_i8_zext_vgpr_ptrtoint(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add = add i64 %sbase.as.int, %zext.offset + %dirty.gep = inttoptr i64 %add to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; zext forced to LHS of addressing expression +define <4 x float> @global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add = add i64 %zext.offset, %sbase.as.int + %dirty.gep = inttoptr i64 %add to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; zext forced to LHS of addressing expression, with immediate offset +define <4 x float> @global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:128 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add = add i64 %zext.offset, %sbase.as.int + %add.immoffset = add i64 %add, 128 + %dirty.gep = inttoptr i64 %add.immoffset to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; zext forced to LHS of addressing expression, with immediate offset in non-canonical position +define <4 x float> @global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1(ptr addrspace(1) inreg %sbase, i32 %voffset) { +; GFX-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:128 sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add.immoffset = add i64 %sbase.as.int, 128 + %add = add i64 %zext.offset, %add.immoffset + %dirty.gep = inttoptr i64 %add to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;;------------------------------------------------------------------------------ +;; Uniformity edge cases +;;------------------------------------------------------------------------------ + +;; Both 64-bit base and 32-bit offset are scalar +define <4 x float> @global_load_saddr_i8_zext_uniform_offset(ptr addrspace(1) inreg %sbase, i32 inreg %soffset) { +; GFX-LABEL: global_load_saddr_i8_zext_uniform_offset: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, s2 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Both 64-bit base and 32-bit offset are scalar, with immediate offset. +define <4 x float> @global_load_saddr_i8_zext_uniform_offset_immoffset(ptr addrspace(1) inreg %sbase, i32 inreg %soffset) { +; GFX-LABEL: global_load_saddr_i8_zext_uniform_offset_immoffset: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, s2 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:-24 sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -24 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Both components uniform, zext forced to LHS of addressing expression +define <4 x float> @global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add(ptr addrspace(1) inreg %sbase, i32 inreg %soffset) { +; GFX-LABEL: global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, s2 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add = add i64 %zext.offset, %sbase.as.int + %dirty.gep = inttoptr i64 %add to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Both components uniform, zext forced to LHS of addressing expression, with immediate offset +define <4 x float> @global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0(ptr addrspace(1) inreg %sbase, i32 inreg %soffset) { +; GFX-LABEL: global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_mov_b32_e32 v0, s2 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:128 sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %sbase.as.int = ptrtoint ptr addrspace(1) %sbase to i64 + %add = add i64 %zext.offset, %sbase.as.int + %add.immoffset = add i64 %add, 128 + %dirty.gep = inttoptr i64 %add.immoffset to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %dirty.gep, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; divergent 64-bit base, 32-bit scalar offset. +define <4 x float> @global_load_saddr_i8_vgpr64_sgpr32(ptr addrspace(1) %vbase, i32 inreg %soffset) { +; +; GFX-SDAG-LABEL: global_load_saddr_i8_vgpr64_sgpr32: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: s_mov_b32 s1, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_vgpr64_sgpr32: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_mov_b32 s1, 0 +; GFX-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %vbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep0, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; divergent 64-bit base, 32-bit scalar offset, with imm offset +define <4 x float> @global_load_saddr_i8_vgpr64_sgpr32_offset_4095(ptr addrspace(1) %vbase, i32 inreg %soffset) { +; +; GFX-SDAG-LABEL: global_load_saddr_i8_vgpr64_sgpr32_offset_4095: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: s_mov_b32 s1, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_i8_vgpr64_sgpr32_offset_4095: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_mov_b32 s1, 0 +; GFX-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4095 sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %soffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %vbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 4095 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;;------------------------------------------------------------------------------ +;; Natural addressing shifts with restricted range +;;------------------------------------------------------------------------------ + +;; Cannot push the shift into 32-bits, and cannot match. +define <4 x float> @global_load_saddr_f32_natural_addressing(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr) { +; +; GFX-SDAG-LABEL: global_load_saddr_f32_natural_addressing: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: global_load_dword v0, v[0:1], off +; GFX-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX-SDAG-NEXT: v_mov_b32_e32 v2, s0 +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, s1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_saddr_f32_natural_addressing: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: global_load_dword v0, v[0:1], off +; GFX-ISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, s[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr + %zext.offset = zext i32 %voffset to i64 + %gep = getelementptr inbounds float, ptr addrspace(1) %sbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Cannot push the shift into 32-bits, with an immediate offset. +define <4 x float> @global_load_saddr_f32_natural_addressing_immoffset(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr) { +; GFX-LABEL: global_load_saddr_f32_natural_addressing_immoffset: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dword v0, v[0:1], off +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:128 sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 128 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Range is sufficiently restricted to push the shift into 32-bits. +define <4 x float> @global_load_f32_saddr_zext_vgpr_range(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr) { +; GFX-LABEL: global_load_f32_saddr_zext_vgpr_range: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dword v0, v[0:1], off +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr, !range !4, !noundef !{} + %zext.offset = zext i32 %voffset to i64 + %gep = getelementptr inbounds float, ptr addrspace(1) %sbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Range is sufficiently restricted to push the shift into 32-bits, with an imm offset +define <4 x float> @global_load_f32_saddr_zext_vgpr_range_imm_offset(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr) { +; GFX-LABEL: global_load_f32_saddr_zext_vgpr_range_imm_offset: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dword v0, v[0:1], off +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] offset:400 sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr, !range !4, !noundef !{} + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds float, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds float, ptr addrspace(1) %gep0, i64 100 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep1, metadata !3) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;; Range is 1 beyond the limit where we can move the shift into 32-bits. +define <4 x float> @global_load_f32_saddr_zext_vgpr_range_too_large(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr) { +; +; GFX-SDAG-LABEL: global_load_f32_saddr_zext_vgpr_range_too_large: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: global_load_dword v0, v[0:1], off +; GFX-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX-SDAG-NEXT: v_mov_b32_e32 v2, s0 +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, s1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, v[2:3] +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_load_f32_saddr_zext_vgpr_range_too_large: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: global_load_dword v0, v[0:1], off +; GFX-ISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, s[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr, !range !5, !noundef !{} + %zext.offset = zext i32 %voffset to i64 + %gep = getelementptr inbounds float, ptr addrspace(1) %sbase, i64 %zext.offset + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %gep, metadata !0) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;;------------------------------------------------------------------------------ +;; or-with-constant as add +;;------------------------------------------------------------------------------ + +;; Check add-as-or with split 64-bit or. +define <4 x float> @global_load_saddr_i8_offset_or_i64_imm_offset_16(ptr addrspace(6) inreg %sbase, i32 %idx) { +; +; GFX-LABEL: global_load_saddr_i8_offset_or_i64_imm_offset_16: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_or_b32_e32 v0, 16, v0 +; GFX-NEXT: v_mov_b32_e32 v1, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.idx = zext i32 %idx to i64 + %or = or i64 %zext.idx, 16 + %addr = inttoptr i64 %or to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !1) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +define <4 x float> @global_load_saddr_i8_offset_or_i64_imm_offset_4160(ptr addrspace(6) inreg %sbase, i32 %idx) { +; +; GFX-LABEL: global_load_saddr_i8_offset_or_i64_imm_offset_4160: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: v_or_b32_e32 v0, 0x1040, v0 +; GFX-NEXT: v_mov_b32_e32 v1, 0 +; GFX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %zext.idx = zext i32 %idx to i64 + %or = or i64 %zext.idx, 4160 + %addr = inttoptr i64 %or to ptr addrspace(1) + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !2) + %cast.load = bitcast <4 x i32> %load to <4 x float> + ret <4 x float> %cast.load +} + +;;------------------------------------------------------------------------------ +;; Full 64-bit scalar add. +;;------------------------------------------------------------------------------ +define <4 x float> @global_saddr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) { +; +; GFX-SDAG-LABEL: global_saddr_64bit_lsr_iv: +; GFX-SDAG: ; %bb.0: ; %bb +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: s_mov_b32 s2, -1 +; GFX-SDAG-NEXT: .LBB114_1: ; %bb3 +; GFX-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX-SDAG-NEXT: s_add_i32 s2, s2, 1 +; GFX-SDAG-NEXT: s_cmpk_eq_i32 s2, 0xff +; GFX-SDAG-NEXT: s_cbranch_scc0 .LBB114_1 +; GFX-SDAG-NEXT: ; %bb.2: ; %bb2 +; GFX-SDAG-NEXT: s_mov_b32 s3, 0 +; GFX-SDAG-NEXT: s_lshl_b64 s[2:3], s[2:3], 2 +; GFX-SDAG-NEXT: s_add_u32 s0, s0, s2 +; GFX-SDAG-NEXT: s_addc_u32 s1, s1, s3 +; GFX-SDAG-NEXT: v_mov_b32_e32 v0, 0 +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_saddr_64bit_lsr_iv: +; GFX-ISEL: ; %bb.0: ; %bb +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_mov_b32 s2, -1 +; GFX-ISEL-NEXT: v_mov_b32_e32 v1, 0xff +; GFX-ISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX-ISEL-NEXT: .LBB114_1: ; %bb3 +; GFX-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX-ISEL-NEXT: v_add_u32_e32 v0, 1, v0 +; GFX-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1 +; GFX-ISEL-NEXT: s_cbranch_vccz .LBB114_1 +; GFX-ISEL-NEXT: ; %bb.2: ; %bb2 +; GFX-ISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, s[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] +bb: + br label %bb3 + +bb2: ; preds = %bb3 + ret <4 x float> %i6 + +bb3: ; preds = %bb3, %bb + %i = phi i32 [ 0, %bb ], [ %i8, %bb3 ] + %i4 = zext i32 %i to i64 + %i5 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %i4 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %i5, metadata !3) + %i6 = bitcast <4 x i32> %load to <4 x float> + %i8 = add nuw nsw i32 %i, 1 + %i9 = icmp eq i32 %i8, 256 + br i1 %i9, label %bb2, label %bb3 +} + +;; Make sure we only have a single zero vaddr initialization. + +define <4 x float> @global_saddr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg %arg, ptr addrspace(1) inreg %arg.1, i32 %x) { +; +; GFX-SDAG-LABEL: global_saddr_64bit_lsr_iv_multiload: +; GFX-SDAG: ; %bb.0: ; %bb +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: s_mov_b32 s2, -1 +; GFX-SDAG-NEXT: .LBB115_1: ; %bb5 +; GFX-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX-SDAG-NEXT: s_add_i32 s2, s2, 1 +; GFX-SDAG-NEXT: s_cmpk_eq_i32 s2, 0xff +; GFX-SDAG-NEXT: s_cbranch_scc0 .LBB115_1 +; GFX-SDAG-NEXT: ; %bb.2: ; %bb2 +; GFX-SDAG-NEXT: s_mov_b32 s3, 0 +; GFX-SDAG-NEXT: s_lshl_b64 s[2:3], s[2:3], 2 +; GFX-SDAG-NEXT: s_add_u32 s0, s0, s2 +; GFX-SDAG-NEXT: s_addc_u32 s1, s1, s3 +; GFX-SDAG-NEXT: v_mov_b32_e32 v0, 0 +; GFX-SDAG-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_saddr_64bit_lsr_iv_multiload: +; GFX-ISEL: ; %bb.0: ; %bb +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: s_mov_b32 s2, -1 +; GFX-ISEL-NEXT: v_mov_b32_e32 v1, 0xff +; GFX-ISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX-ISEL-NEXT: .LBB115_1: ; %bb5 +; GFX-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX-ISEL-NEXT: v_add_u32_e32 v0, 1, v0 +; GFX-ISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1 +; GFX-ISEL-NEXT: s_cbranch_vccz .LBB115_1 +; GFX-ISEL-NEXT: ; %bb.2: ; %bb2 +; GFX-ISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX-ISEL-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, s[0:1] +; GFX-ISEL-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] +bb: + br label %bb5 + +bb2: + %y = icmp eq i32 %x, 0 + br i1 %y, label %bb3, label %bb4 + +bb3: + ret <4 x float> %i6 + +bb4: + ret <4 x float> %i6.1 + +bb5: + %i = phi i32 [ 0, %bb ], [ %i8, %bb5 ] + %i4 = zext i32 %i to i64 + %i5 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %i4 + %load = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %i5, metadata !0) + %i6 = bitcast <4 x i32> %load to <4 x float> + %i5.1 = getelementptr inbounds float, ptr addrspace(1) %arg.1, i64 %i4 + %load.1 = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %i5, metadata !1) + %i6.1 = bitcast <4 x i32> %load to <4 x float> + %i8 = add nuw nsw i32 %i, 1 + %i9 = icmp eq i32 %i8, 256 + br i1 %i9, label %bb2, label %bb5 +} +;;============================================================================== +;; } End saddr addressing modes +;;============================================================================== + +!0 = !{!"wavefront"} +!1 = !{!"workgroup"} +!2 = !{!"agent"} +!3 = !{!""} + +!4 = !{i32 0, i32 1073741824} ; (1 << 30) +!5 = !{i32 0, i32 1073741825} ; (1 << 30) + 1 + +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX9-4-GENERIC-ISEL: {{.*}} +; GFX9-4-GENERIC-SDAG: {{.*}} +; GFX942-ISEL: {{.*}} +; GFX942-SDAG: {{.*}} +; GFX950-ISEL: {{.*}} +; GFX950-SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.b128.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.b128.ll new file mode 100644 index 0000000000000..5d03cb0a094db --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.b128.ll @@ -0,0 +1,385 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX,GFX-SDAG,GFX942-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX,GFX-SDAG,GFX950-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx9-4-generic < %s | FileCheck -check-prefixes=GFX,GFX-SDAG,GFX9-4-GENERIC-SDAG %s + +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX,GFX-ISEL,GFX942-ISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX,GFX-ISEL,GFX950-ISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx9-4-generic < %s | FileCheck -check-prefixes=GFX,GFX-ISEL,GFX9-4-GENERIC-ISEL %s + +;;============================================================================== +;; A few basic test cases +;;============================================================================== +define void @global_store_b128_0_00(ptr addrspace(1) %addr, <4 x i32> %data) { +; GFX-LABEL: global_store_b128_0_00: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_store_dwordx4 v[0:1], v[2:5], off +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %addr, <4 x i32> %data, metadata !0) + ret void +} + +define void @global_store_b128_0_01(ptr addrspace(1) %addr, <4 x i32> %data) { +; GFX-LABEL: global_store_b128_0_01: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_store_dwordx4 v[0:1], v[2:5], off sc0 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %addr, <4 x i32> %data, metadata !1) + ret void +} + +define void @global_store_b128_0_10(ptr addrspace(1) %addr, <4 x i32> %data) { +; GFX-LABEL: global_store_b128_0_10: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_store_dwordx4 v[0:1], v[2:5], off sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %addr, <4 x i32> %data, metadata !2) + ret void +} + +define void @global_store_b128_0_11(ptr addrspace(1) %addr, <4 x i32> %data) { +; GFX-LABEL: global_store_b128_0_11: +; GFX: ; %bb.0: ; %entry +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_store_dwordx4 v[0:1], v[2:5], off sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] +entry: + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %addr, <4 x i32> %data, metadata !3) + ret void +} + +;;============================================================================== +;; Signed offset addressing modes (derived from global-saddr-store.ll) { +;;============================================================================== + +define void @global_store_i8_zext_vgpr(ptr addrspace(1) %sbase, ptr addrspace(1) %voffset.ptr, <4 x i32> %data) { +; GFX-SDAG-LABEL: global_store_i8_zext_vgpr: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: global_load_dword v2, v[2:3], off +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_store_dwordx4 v[0:1], v[4:7], off +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_store_i8_zext_vgpr: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: global_load_dword v2, v[2:3], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %gep0, <4 x i32> %data, metadata !0) + ret void +} + +define void @global_store_v4i32_zext_vgpr_offset_neg128(ptr addrspace(1) %sbase, i32 %voffset, <4 x i32> %data) { +; GFX-SDAG-LABEL: global_store_v4i32_zext_vgpr_offset_neg128: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v7, v6 +; GFX-SDAG-NEXT: v_mov_b32_e32 v6, v5 +; GFX-SDAG-NEXT: v_mov_b32_e32 v5, v4 +; GFX-SDAG-NEXT: v_mov_b32_e32 v4, v3 +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_store_dwordx4 v[0:1], v[4:7], off offset:-128 sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_store_v4i32_zext_vgpr_offset_neg128: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: v_mov_b32_e32 v8, v3 +; GFX-ISEL-NEXT: v_mov_b32_e32 v9, v4 +; GFX-ISEL-NEXT: v_mov_b32_e32 v10, v5 +; GFX-ISEL-NEXT: v_mov_b32_e32 v11, v6 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off offset:-128 sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128 + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %gep1, <4 x i32> %data, metadata !1) + ret void +} + +;; Maximum positive offset on gfx10 +define void @global_store_i8_zext_vgpr_offset_2047(ptr addrspace(1) %sbase, ptr addrspace(1) %voffset.ptr, <4 x i32> %data) { +; GFX-SDAG-LABEL: global_store_i8_zext_vgpr_offset_2047: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: global_load_dword v2, v[2:3], off +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_store_dwordx4 v[0:1], v[4:7], off offset:2047 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_store_i8_zext_vgpr_offset_2047: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: global_load_dword v2, v[2:3], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off offset:2047 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 2047 + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %gep1, <4 x i32> %data, metadata !2) + ret void +} + +;; Maximum negative offset on gfx10 +define void @global_store_i8_zext_vgpr_offset_neg2048(ptr addrspace(1) %sbase, ptr addrspace(1) %voffset.ptr, <4 x i32> %data) { +; GFX-SDAG-LABEL: global_store_i8_zext_vgpr_offset_neg2048: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: global_load_dword v2, v[2:3], off +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, 0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX-SDAG-NEXT: global_store_dwordx4 v[0:1], v[4:7], off offset:-2048 sc0 sc1 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_store_i8_zext_vgpr_offset_neg2048: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: global_load_dword v2, v[2:3], off +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX-ISEL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off offset:-2048 sc0 sc1 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -2048 + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %gep1, <4 x i32> %data, metadata !3) + ret void +} +;;============================================================================== +;; } end signed offset addressing modes +;;============================================================================== + +;;============================================================================== +;; Various saddr addressing modes (derived from global-saddr-load.ll) { +;;============================================================================== + +define void @global_store_saddr_i8_zext_vgpr(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr, <4 x i32> %data) { +; GFX-LABEL: global_store_saddr_i8_zext_vgpr: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dword v0, v[0:1], off +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1] +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %gep0, <4 x i32> %data, metadata !0) + ret void +} + +define void @global_store_saddr_v4i32_zext_vgpr_offset_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, <4 x i32> %data) { +; GFX-SDAG-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v5, v4 +; GFX-SDAG-NEXT: v_mov_b32_e32 v4, v3 +; GFX-SDAG-NEXT: v_mov_b32_e32 v3, v2 +; GFX-SDAG-NEXT: v_mov_b32_e32 v2, v1 +; GFX-SDAG-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1] offset:-128 sc0 +; GFX-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX-ISEL-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-ISEL-NEXT: v_mov_b32_e32 v6, v1 +; GFX-ISEL-NEXT: v_mov_b32_e32 v7, v2 +; GFX-ISEL-NEXT: v_mov_b32_e32 v8, v3 +; GFX-ISEL-NEXT: v_mov_b32_e32 v9, v4 +; GFX-ISEL-NEXT: global_store_dwordx4 v0, v[6:9], s[0:1] offset:-128 sc0 +; GFX-ISEL-NEXT: s_waitcnt vmcnt(0) +; GFX-ISEL-NEXT: s_setpc_b64 s[30:31] + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128 + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %gep1, <4 x i32> %data, metadata !1) + ret void +} + +;; Maximum positive offset on gfx10 +define void @global_store_saddr_i8_zext_vgpr_offset_2047(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr, <4 x i32> %data) { +; GFX-LABEL: global_store_saddr_i8_zext_vgpr_offset_2047: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dword v0, v[0:1], off +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1] offset:2047 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 2047 + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %gep1, <4 x i32> %data, metadata !2) + ret void +} + +;; Maximum negative offset on gfx10 +define void @global_store_saddr_i8_zext_vgpr_offset_neg2048(ptr addrspace(1) inreg %sbase, ptr addrspace(1) %voffset.ptr, <4 x i32> %data) { +; GFX-LABEL: global_store_saddr_i8_zext_vgpr_offset_neg2048: +; GFX: ; %bb.0: +; GFX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX-NEXT: global_load_dword v0, v[0:1], off +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1] offset:-2048 sc0 sc1 +; GFX-NEXT: s_waitcnt vmcnt(0) +; GFX-NEXT: s_setpc_b64 s[30:31] + %voffset = load i32, ptr addrspace(1) %voffset.ptr + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -2048 + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %gep1, <4 x i32> %data, metadata !3) + ret void +} + +;;------------------------------------------------------------------------------ +;; Uniformity edge cases +;;------------------------------------------------------------------------------ + +@ptr.in.lds = internal addrspace(3) global ptr addrspace(1) poison + +;; Base pointer is uniform, but also in VGPRs +define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, <4 x i32> %data) { +; GFX-SDAG-LABEL: global_store_saddr_uniform_ptr_in_vgprs: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_load_dword s6, s[4:5], 0x24 +; GFX-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 +; GFX-SDAG-NEXT: v_mov_b32_e32 v0, 0 +; GFX-SDAG-NEXT: ds_read_b64 v[0:1], v0 +; GFX-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v2, s6 +; GFX-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[2:3] +; GFX-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[0:1] +; GFX-SDAG-NEXT: v_readfirstlane_b32 s0, v0 +; GFX-SDAG-NEXT: v_readfirstlane_b32 s1, v1 +; GFX-SDAG-NEXT: s_nop 4 +; GFX-SDAG-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1] +; GFX-SDAG-NEXT: s_endpgm +; +; GFX-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24 +; GFX-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 +; GFX-ISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX-ISEL-NEXT: ds_read_b64 v[0:1], v0 +; GFX-ISEL-NEXT: s_mov_b32 s7, 0 +; GFX-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7] +; GFX-ISEL-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc +; GFX-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX-ISEL-NEXT: global_store_dwordx4 v[4:5], v[0:3], off +; GFX-ISEL-NEXT: s_endpgm + %sbase = load ptr addrspace(1), ptr addrspace(3) @ptr.in.lds + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %gep0, <4 x i32> %data, metadata !0) + ret void +} + +;; Base pointer is uniform, but also in VGPRs, with imm offset +define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voffset, <4 x i32> %data) { +; GFX-SDAG-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset: +; GFX-SDAG: ; %bb.0: +; GFX-SDAG-NEXT: s_load_dword s6, s[4:5], 0x24 +; GFX-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 +; GFX-SDAG-NEXT: v_mov_b32_e32 v0, 0 +; GFX-SDAG-NEXT: ds_read_b64 v[0:1], v0 +; GFX-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX-SDAG-NEXT: v_mov_b32_e32 v2, s6 +; GFX-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[2:3] +; GFX-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[0:1] +; GFX-SDAG-NEXT: v_readfirstlane_b32 s0, v0 +; GFX-SDAG-NEXT: v_readfirstlane_b32 s1, v1 +; GFX-SDAG-NEXT: s_nop 4 +; GFX-SDAG-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1] offset:-120 sc0 +; GFX-SDAG-NEXT: s_endpgm +; +; GFX-ISEL-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset: +; GFX-ISEL: ; %bb.0: +; GFX-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24 +; GFX-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 +; GFX-ISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX-ISEL-NEXT: ds_read_b64 v[0:1], v0 +; GFX-ISEL-NEXT: s_mov_b32 s7, 0 +; GFX-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7] +; GFX-ISEL-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2 +; GFX-ISEL-NEXT: s_nop 1 +; GFX-ISEL-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc +; GFX-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX-ISEL-NEXT: global_store_dwordx4 v[4:5], v[0:3], off offset:-120 sc0 +; GFX-ISEL-NEXT: s_endpgm + %sbase = load ptr addrspace(1), ptr addrspace(3) @ptr.in.lds + %zext.offset = zext i32 %voffset to i64 + %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset + %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -120 + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %gep1, <4 x i32> %data, metadata !1) + ret void +} + +;;============================================================================== +;; } End saddr addressing modes +;;============================================================================== + + +!0 = !{!"wavefront"} +!1 = !{!"workgroup"} +!2 = !{!"agent"} +!3 = !{!""} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX9-4-GENERIC-ISEL: {{.*}} +; GFX9-4-GENERIC-SDAG: {{.*}} +; GFX942-ISEL: {{.*}} +; GFX942-SDAG: {{.*}} +; GFX950-ISEL: {{.*}} +; GFX950-SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll index d1ba892d7f7e1..2f4d5ee3cbce5 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll @@ -984,10 +984,6 @@ define void @test_readfirstlane_v32f32(ptr addrspace(1) %out, <32 x float> %src) ; CHECK-SDAG-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; CHECK-SDAG-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; CHECK-SDAG-NEXT: s_mov_b64 exec, s[4:5] -; CHECK-SDAG-NEXT: v_readfirstlane_b32 s61, v27 -; CHECK-SDAG-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 -; CHECK-SDAG-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 -; CHECK-SDAG-NEXT: buffer_load_dword v27, off, s[0:3], s32 ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s36, 0 ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s37, 1 ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s38, 2 @@ -1004,6 +1000,10 @@ define void @test_readfirstlane_v32f32(ptr addrspace(1) %out, <32 x float> %src) ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s65, 13 ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s66, 14 ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s67, 15 +; CHECK-SDAG-NEXT: v_readfirstlane_b32 s61, v27 +; CHECK-SDAG-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 +; CHECK-SDAG-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 +; CHECK-SDAG-NEXT: buffer_load_dword v27, off, s[0:3], s32 ; CHECK-SDAG-NEXT: v_readfirstlane_b32 s64, v30 ; CHECK-SDAG-NEXT: v_readfirstlane_b32 s55, v21 ; CHECK-SDAG-NEXT: v_readfirstlane_b32 s54, v20 @@ -1070,10 +1070,6 @@ define void @test_readfirstlane_v32f32(ptr addrspace(1) %out, <32 x float> %src) ; CHECK-GISEL-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; CHECK-GISEL-NEXT: s_mov_b64 exec, s[4:5] ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s36, 0 -; CHECK-GISEL-NEXT: v_readfirstlane_b32 s36, v2 -; CHECK-GISEL-NEXT: buffer_load_dword v0, off, s[0:3], s32 -; CHECK-GISEL-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 -; CHECK-GISEL-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8 ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s37, 1 ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s38, 2 ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s39, 3 @@ -1089,6 +1085,10 @@ define void @test_readfirstlane_v32f32(ptr addrspace(1) %out, <32 x float> %src) ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s65, 13 ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s66, 14 ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s67, 15 +; CHECK-GISEL-NEXT: v_readfirstlane_b32 s36, v2 +; CHECK-GISEL-NEXT: buffer_load_dword v0, off, s[0:3], s32 +; CHECK-GISEL-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 +; CHECK-GISEL-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8 ; CHECK-GISEL-NEXT: v_readfirstlane_b32 s37, v3 ; CHECK-GISEL-NEXT: v_readfirstlane_b32 s38, v4 ; CHECK-GISEL-NEXT: v_readfirstlane_b32 s39, v5 @@ -1429,10 +1429,6 @@ define void @test_readfirstlane_v32i32(ptr addrspace(1) %out, <32 x i32> %src) { ; CHECK-SDAG-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; CHECK-SDAG-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; CHECK-SDAG-NEXT: s_mov_b64 exec, s[4:5] -; CHECK-SDAG-NEXT: v_readfirstlane_b32 s61, v27 -; CHECK-SDAG-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 -; CHECK-SDAG-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 -; CHECK-SDAG-NEXT: buffer_load_dword v27, off, s[0:3], s32 ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s36, 0 ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s37, 1 ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s38, 2 @@ -1449,6 +1445,10 @@ define void @test_readfirstlane_v32i32(ptr addrspace(1) %out, <32 x i32> %src) { ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s65, 13 ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s66, 14 ; CHECK-SDAG-NEXT: v_writelane_b32 v31, s67, 15 +; CHECK-SDAG-NEXT: v_readfirstlane_b32 s61, v27 +; CHECK-SDAG-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 +; CHECK-SDAG-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 +; CHECK-SDAG-NEXT: buffer_load_dword v27, off, s[0:3], s32 ; CHECK-SDAG-NEXT: v_readfirstlane_b32 s64, v30 ; CHECK-SDAG-NEXT: v_readfirstlane_b32 s55, v21 ; CHECK-SDAG-NEXT: v_readfirstlane_b32 s54, v20 @@ -1515,10 +1515,6 @@ define void @test_readfirstlane_v32i32(ptr addrspace(1) %out, <32 x i32> %src) { ; CHECK-GISEL-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; CHECK-GISEL-NEXT: s_mov_b64 exec, s[4:5] ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s36, 0 -; CHECK-GISEL-NEXT: v_readfirstlane_b32 s36, v2 -; CHECK-GISEL-NEXT: buffer_load_dword v0, off, s[0:3], s32 -; CHECK-GISEL-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 -; CHECK-GISEL-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8 ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s37, 1 ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s38, 2 ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s39, 3 @@ -1534,6 +1530,10 @@ define void @test_readfirstlane_v32i32(ptr addrspace(1) %out, <32 x i32> %src) { ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s65, 13 ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s66, 14 ; CHECK-GISEL-NEXT: v_writelane_b32 v31, s67, 15 +; CHECK-GISEL-NEXT: v_readfirstlane_b32 s36, v2 +; CHECK-GISEL-NEXT: buffer_load_dword v0, off, s[0:3], s32 +; CHECK-GISEL-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 +; CHECK-GISEL-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8 ; CHECK-GISEL-NEXT: v_readfirstlane_b32 s37, v3 ; CHECK-GISEL-NEXT: v_readfirstlane_b32 s38, v4 ; CHECK-GISEL-NEXT: v_readfirstlane_b32 s39, v5 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll index 4d23fb116cd03..1a19b244690b4 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll @@ -22,6 +22,8 @@ entry: ; GCN-LABEL: {{^}}only_undef_dbg_value: ; NOOPT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- undef +; NOOPT-NEXT: .cfi_escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 +; NOOPT-NEXT: .cfi_undefined 16 ; NOOPT-NEXT: s_endpgm ; OPT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll index 18c462ffd0ff5..dd2cffd7bd161 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll @@ -77,17 +77,53 @@ define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) { ; GFX10CHECK-NEXT: global_store_dword v0, v1, s[0:1] ; GFX10CHECK-NEXT: s_endpgm ; -; GFX11CHECK-LABEL: sgpr_isnan_f16: -; GFX11CHECK: ; %bb.0: -; GFX11CHECK-NEXT: s_clause 0x1 -; GFX11CHECK-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX11CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX11CHECK-NEXT: v_mov_b32_e32 v0, 0 -; GFX11CHECK-NEXT: s_waitcnt lgkmcnt(0) -; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s2, s2, 3 -; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 -; GFX11CHECK-NEXT: global_store_b32 v0, v1, s[0:1] -; GFX11CHECK-NEXT: s_endpgm +; GFX11SELDAG-TRUE16-LABEL: sgpr_isnan_f16: +; GFX11SELDAG-TRUE16: ; %bb.0: +; GFX11SELDAG-TRUE16-NEXT: s_clause 0x1 +; GFX11SELDAG-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX11SELDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX11SELDAG-TRUE16-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 0 +; GFX11SELDAG-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, s2, v0.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo +; GFX11SELDAG-TRUE16-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11SELDAG-TRUE16-NEXT: s_endpgm +; +; GFX11SELDAG-FAKE16-LABEL: sgpr_isnan_f16: +; GFX11SELDAG-FAKE16: ; %bb.0: +; GFX11SELDAG-FAKE16-NEXT: s_clause 0x1 +; GFX11SELDAG-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX11SELDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX11SELDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX11SELDAG-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11SELDAG-FAKE16-NEXT: v_cmp_class_f16_e64 s2, s2, 3 +; GFX11SELDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 +; GFX11SELDAG-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11SELDAG-FAKE16-NEXT: s_endpgm +; +; GFX11GLISEL-TRUE16-LABEL: sgpr_isnan_f16: +; GFX11GLISEL-TRUE16: ; %bb.0: +; GFX11GLISEL-TRUE16-NEXT: s_clause 0x1 +; GFX11GLISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX11GLISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX11GLISEL-TRUE16-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 0 +; GFX11GLISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, s2, v0.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo +; GFX11GLISEL-TRUE16-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11GLISEL-TRUE16-NEXT: s_endpgm +; +; GFX11GLISEL-FAKE16-LABEL: sgpr_isnan_f16: +; GFX11GLISEL-FAKE16: ; %bb.0: +; GFX11GLISEL-FAKE16-NEXT: s_clause 0x1 +; GFX11GLISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX11GLISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX11GLISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX11GLISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11GLISEL-FAKE16-NEXT: v_cmp_class_f16_e64 s2, s2, 3 +; GFX11GLISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 +; GFX11GLISEL-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11GLISEL-FAKE16-NEXT: s_endpgm %result = call i1 @llvm.is.fpclass.f16(half %x, i32 3) %sext = sext i1 %result to i32 store i32 %sext, ptr addrspace(1) %out, align 4 @@ -212,8 +248,9 @@ define i1 @snan_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: snan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 1 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 1 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: snan_f16: @@ -226,8 +263,9 @@ define i1 @snan_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: snan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 1 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 1 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: snan_f16: @@ -285,8 +323,9 @@ define i1 @qnan_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: qnan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 2 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 2 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: qnan_f16: @@ -299,8 +338,9 @@ define i1 @qnan_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: qnan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 2 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 2 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: qnan_f16: @@ -358,8 +398,9 @@ define i1 @posinf_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: posinf_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x200 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x200 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: posinf_f16: @@ -372,8 +413,9 @@ define i1 @posinf_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: posinf_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x200 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x200 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: posinf_f16: @@ -429,8 +471,9 @@ define i1 @neginf_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: neginf_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 4 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 4 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: neginf_f16: @@ -443,8 +486,9 @@ define i1 @neginf_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: neginf_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 4 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 4 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: neginf_f16: @@ -514,8 +558,9 @@ define i1 @posnormal_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: posnormal_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x100 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x100 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: posnormal_f16: @@ -528,8 +573,9 @@ define i1 @posnormal_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: posnormal_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x100 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x100 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: posnormal_f16: @@ -597,8 +643,9 @@ define i1 @negnormal_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: negnormal_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 8 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 8 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: negnormal_f16: @@ -611,8 +658,9 @@ define i1 @negnormal_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: negnormal_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 8 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 8 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: negnormal_f16: @@ -673,8 +721,9 @@ define i1 @possubnormal_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: possubnormal_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x80 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x80 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: possubnormal_f16: @@ -687,8 +736,9 @@ define i1 @possubnormal_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: possubnormal_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x80 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x80 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: possubnormal_f16: @@ -755,8 +805,9 @@ define i1 @negsubnormal_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: negsubnormal_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 16 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 16 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: negsubnormal_f16: @@ -769,8 +820,9 @@ define i1 @negsubnormal_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: negsubnormal_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 16 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 16 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: negsubnormal_f16: @@ -824,8 +876,9 @@ define i1 @poszero_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: poszero_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 64 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 64 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: poszero_f16: @@ -838,8 +891,9 @@ define i1 @poszero_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: poszero_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 64 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 64 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: poszero_f16: @@ -895,8 +949,9 @@ define i1 @negzero_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: negzero_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 32 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 32 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: negzero_f16: @@ -909,8 +964,9 @@ define i1 @negzero_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: negzero_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 32 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 32 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: negzero_f16: @@ -968,8 +1024,9 @@ define i1 @posfinite_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: posfinite_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x1c0 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x1c0 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: posfinite_f16: @@ -982,8 +1039,9 @@ define i1 @posfinite_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: posfinite_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x1c0 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x1c0 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: posfinite_f16: @@ -1047,8 +1105,9 @@ define i1 @negfinite_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: negfinite_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 56 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 56 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: negfinite_f16: @@ -1061,8 +1120,9 @@ define i1 @negfinite_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: negfinite_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 56 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 56 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: negfinite_f16: @@ -1120,8 +1180,9 @@ define i1 @isnan_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: isnan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 3 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 3 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: isnan_f16: @@ -1134,8 +1195,9 @@ define i1 @isnan_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: isnan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 3 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 3 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isnan_f16: @@ -1195,8 +1257,9 @@ define i1 @not_isnan_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_isnan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x3fc -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x3fc +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_isnan_f16: @@ -1209,8 +1272,9 @@ define i1 @not_isnan_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_isnan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x3fc -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x3fc +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_isnan_f16: @@ -1336,11 +1400,13 @@ define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: isnan_v2f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 3 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.h, 3 +; GFX11GLISEL-TRUE16-NEXT: v_dual_mov_b32 v1, 3 :: v_dual_mov_b32 v2, 3 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.h, v3.l ; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isnan_v2f16: @@ -1499,13 +1565,17 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: isnan_v3f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 3 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0 -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.h, 3 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v1.l, 3 -; GFX11GLISEL-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 3 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 3 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v2.l +; GFX11GLISEL-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.h, v3.l +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v4 +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v1.l, v5.l +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, v3 +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isnan_v3f16: @@ -1693,16 +1763,20 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: isnan_v4f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 3 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0 -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.h, 3 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v1.l, 3 +; GFX11GLISEL-TRUE16-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 3 +; GFX11GLISEL-TRUE16-NEXT: v_dual_mov_b32 v4, 3 :: v_dual_mov_b32 v5, 3 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v2.l +; GFX11GLISEL-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l +; GFX11GLISEL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.h, v3.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v1.l, v6.l ; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v4 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v1.h, 3 +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v1.h, v7.l ; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, v5 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isnan_v4f16: @@ -1771,8 +1845,9 @@ define i1 @isnan_f16_strictfp(half %x) strictfp nounwind { ; GFX11SELDAG-TRUE16-LABEL: isnan_f16_strictfp: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 3 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 3 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: isnan_f16_strictfp: @@ -1785,8 +1860,9 @@ define i1 @isnan_f16_strictfp(half %x) strictfp nounwind { ; GFX11GLISEL-TRUE16-LABEL: isnan_f16_strictfp: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 3 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 3 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isnan_f16_strictfp: @@ -1846,8 +1922,9 @@ define i1 @isinf_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: isinf_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x204 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x204 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: isinf_f16: @@ -1860,8 +1937,9 @@ define i1 @isinf_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: isinf_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x204 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x204 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isinf_f16: @@ -1921,8 +1999,9 @@ define i1 @isfinite_f16(half %x) nounwind { ; GFX11SELDAG-TRUE16-LABEL: isfinite_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x1f8 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x1f8 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: isfinite_f16: @@ -1935,8 +2014,9 @@ define i1 @isfinite_f16(half %x) nounwind { ; GFX11GLISEL-TRUE16-LABEL: isfinite_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x1f8 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x1f8 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isfinite_f16: @@ -1994,8 +2074,9 @@ define i1 @issubnormal_or_zero_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: issubnormal_or_zero_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0xf0 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0xf0 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: issubnormal_or_zero_f16: @@ -2008,8 +2089,9 @@ define i1 @issubnormal_or_zero_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: issubnormal_or_zero_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0xf0 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0xf0 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: issubnormal_or_zero_f16: @@ -2074,8 +2156,9 @@ define i1 @not_issubnormal_or_zero_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_issubnormal_or_zero_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x30f -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x30f +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_issubnormal_or_zero_f16: @@ -2088,8 +2171,9 @@ define i1 @not_issubnormal_or_zero_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_issubnormal_or_zero_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x30f -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x30f +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_issubnormal_or_zero_f16: @@ -2153,8 +2237,9 @@ define i1 @isnormal_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: isnormal_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x108 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x108 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: isnormal_f16: @@ -2167,8 +2252,9 @@ define i1 @isnormal_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: isnormal_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x108 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x108 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isnormal_f16: @@ -2236,8 +2322,9 @@ define i1 @not_isnormal_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_isnormal_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x2f7 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x2f7 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_isnormal_f16: @@ -2250,8 +2337,9 @@ define i1 @not_isnormal_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_isnormal_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x2f7 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x2f7 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_isnormal_f16: @@ -2330,8 +2418,9 @@ define i1 @not_is_plus_normal_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_is_plus_normal_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x2ff -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x2ff +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_is_plus_normal_f16: @@ -2344,8 +2433,9 @@ define i1 @not_is_plus_normal_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_is_plus_normal_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x2ff -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x2ff +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_is_plus_normal_f16: @@ -2424,8 +2514,9 @@ define i1 @not_is_neg_normal_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_is_neg_normal_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x3f7 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x3f7 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_is_neg_normal_f16: @@ -2438,8 +2529,9 @@ define i1 @not_is_neg_normal_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_is_neg_normal_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x3f7 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x3f7 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_is_neg_normal_f16: @@ -2501,8 +2593,9 @@ define i1 @issubnormal_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: issubnormal_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x90 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x90 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: issubnormal_f16: @@ -2515,8 +2608,9 @@ define i1 @issubnormal_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: issubnormal_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x90 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x90 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: issubnormal_f16: @@ -2586,8 +2680,9 @@ define i1 @not_issubnormal_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_issubnormal_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x36f -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x36f +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_issubnormal_f16: @@ -2600,8 +2695,9 @@ define i1 @not_issubnormal_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_issubnormal_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x36f -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x36f +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_issubnormal_f16: @@ -2659,8 +2755,9 @@ define i1 @iszero_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: iszero_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x60 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x60 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: iszero_f16: @@ -2673,8 +2770,9 @@ define i1 @iszero_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: iszero_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x60 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x60 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: iszero_f16: @@ -2745,8 +2843,9 @@ define i1 @not_iszero_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_iszero_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39f -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39f +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_iszero_f16: @@ -2759,8 +2858,9 @@ define i1 @not_iszero_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_iszero_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39f -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39f +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_iszero_f16: @@ -2818,8 +2918,9 @@ define i1 @ispositive_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: ispositive_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x3c0 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x3c0 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: ispositive_f16: @@ -2832,8 +2933,9 @@ define i1 @ispositive_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: ispositive_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x3c0 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x3c0 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: ispositive_f16: @@ -2907,8 +3009,9 @@ define i1 @not_ispositive_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_ispositive_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 63 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 63 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_ispositive_f16: @@ -2921,8 +3024,9 @@ define i1 @not_ispositive_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_ispositive_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 63 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 63 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_ispositive_f16: @@ -2992,8 +3096,9 @@ define i1 @isnegative_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: isnegative_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 60 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 60 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: isnegative_f16: @@ -3006,8 +3111,9 @@ define i1 @isnegative_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: isnegative_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 60 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 60 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isnegative_f16: @@ -3074,8 +3180,9 @@ define i1 @not_isnegative_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_isnegative_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x3c3 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x3c3 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_isnegative_f16: @@ -3088,8 +3195,9 @@ define i1 @not_isnegative_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_isnegative_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x3c3 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x3c3 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_isnegative_f16: @@ -3152,8 +3260,9 @@ define i1 @iszero_or_nan_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: iszero_or_nan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x63 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x63 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: iszero_or_nan_f16: @@ -3166,8 +3275,9 @@ define i1 @iszero_or_nan_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: iszero_or_nan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x63 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x63 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: iszero_or_nan_f16: @@ -3231,8 +3341,9 @@ define i1 @iszero_or_nan_f_daz(half %x) #0 { ; GFX11SELDAG-TRUE16-LABEL: iszero_or_nan_f_daz: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x63 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x63 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: iszero_or_nan_f_daz: @@ -3245,8 +3356,9 @@ define i1 @iszero_or_nan_f_daz(half %x) #0 { ; GFX11GLISEL-TRUE16-LABEL: iszero_or_nan_f_daz: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x63 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x63 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: iszero_or_nan_f_daz: @@ -3310,8 +3422,9 @@ define i1 @iszero_or_nan_f_maybe_daz(half %x) #1 { ; GFX11SELDAG-TRUE16-LABEL: iszero_or_nan_f_maybe_daz: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x63 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x63 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: iszero_or_nan_f_maybe_daz: @@ -3324,8 +3437,9 @@ define i1 @iszero_or_nan_f_maybe_daz(half %x) #1 { ; GFX11GLISEL-TRUE16-LABEL: iszero_or_nan_f_maybe_daz: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x63 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x63 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: iszero_or_nan_f_maybe_daz: @@ -3398,8 +3512,9 @@ define i1 @not_iszero_or_nan_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_iszero_or_nan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39c -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39c +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_iszero_or_nan_f16: @@ -3412,8 +3527,9 @@ define i1 @not_iszero_or_nan_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_iszero_or_nan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39c -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39c +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_iszero_or_nan_f16: @@ -3486,8 +3602,9 @@ define i1 @not_iszero_or_nan_f_daz(half %x) #0 { ; GFX11SELDAG-TRUE16-LABEL: not_iszero_or_nan_f_daz: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39c -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39c +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_iszero_or_nan_f_daz: @@ -3500,8 +3617,9 @@ define i1 @not_iszero_or_nan_f_daz(half %x) #0 { ; GFX11GLISEL-TRUE16-LABEL: not_iszero_or_nan_f_daz: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39c -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39c +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_iszero_or_nan_f_daz: @@ -3574,8 +3692,9 @@ define i1 @not_iszero_or_nan_f_maybe_daz(half %x) #1 { ; GFX11SELDAG-TRUE16-LABEL: not_iszero_or_nan_f_maybe_daz: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39c -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39c +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_iszero_or_nan_f_maybe_daz: @@ -3588,8 +3707,9 @@ define i1 @not_iszero_or_nan_f_maybe_daz(half %x) #1 { ; GFX11GLISEL-TRUE16-LABEL: not_iszero_or_nan_f_maybe_daz: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39c -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39c +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_iszero_or_nan_f_maybe_daz: @@ -3653,8 +3773,9 @@ define i1 @iszero_or_qnan_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: iszero_or_qnan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x62 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x62 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: iszero_or_qnan_f16: @@ -3667,8 +3788,9 @@ define i1 @iszero_or_qnan_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: iszero_or_qnan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x62 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x62 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: iszero_or_qnan_f16: @@ -3737,8 +3859,9 @@ define i1 @iszero_or_snan_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: iszero_or_snan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x61 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x61 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: iszero_or_snan_f16: @@ -3751,8 +3874,9 @@ define i1 @iszero_or_snan_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: iszero_or_snan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x61 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x61 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: iszero_or_snan_f16: @@ -3841,8 +3965,9 @@ define i1 @not_iszero_or_qnan_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_iszero_or_qnan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39d -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39d +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_iszero_or_qnan_f16: @@ -3855,8 +3980,9 @@ define i1 @not_iszero_or_qnan_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_iszero_or_qnan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39d -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39d +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_iszero_or_qnan_f16: @@ -3942,8 +4068,9 @@ define i1 @not_iszero_or_snan_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_iszero_or_snan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39e -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39e +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_iszero_or_snan_f16: @@ -3956,8 +4083,9 @@ define i1 @not_iszero_or_snan_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_iszero_or_snan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x39e -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x39e +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_iszero_or_snan_f16: @@ -4018,8 +4146,9 @@ define i1 @isinf_or_nan_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: isinf_or_nan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x207 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x207 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: isinf_or_nan_f16: @@ -4032,8 +4161,9 @@ define i1 @isinf_or_nan_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: isinf_or_nan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x207 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x207 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isinf_or_nan_f16: @@ -4094,8 +4224,9 @@ define i1 @not_isinf_or_nan_f16(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_isinf_or_nan_f16: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x1f8 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x1f8 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_isinf_or_nan_f16: @@ -4108,8 +4239,9 @@ define i1 @not_isinf_or_nan_f16(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_isinf_or_nan_f16: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x1f8 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x1f8 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_isinf_or_nan_f16: @@ -4170,8 +4302,9 @@ define i1 @isfinite_or_nan_f(half %x) { ; GFX11SELDAG-TRUE16-LABEL: isfinite_or_nan_f: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x1fb -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x1fb +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: isfinite_or_nan_f: @@ -4184,8 +4317,9 @@ define i1 @isfinite_or_nan_f(half %x) { ; GFX11GLISEL-TRUE16-LABEL: isfinite_or_nan_f: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x1fb -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x1fb +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: isfinite_or_nan_f: @@ -4246,8 +4380,9 @@ define i1 @not_isfinite_or_nan_f(half %x) { ; GFX11SELDAG-TRUE16-LABEL: not_isfinite_or_nan_f: ; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry ; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x204 -; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0x204 +; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11SELDAG-FAKE16-LABEL: not_isfinite_or_nan_f: @@ -4260,8 +4395,9 @@ define i1 @not_isfinite_or_nan_f(half %x) { ; GFX11GLISEL-TRUE16-LABEL: not_isfinite_or_nan_f: ; GFX11GLISEL-TRUE16: ; %bb.0: ; %entry ; GFX11GLISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x204 -; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX11GLISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0x204 +; GFX11GLISEL-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, v0.l, v1.l +; GFX11GLISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11GLISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11GLISEL-FAKE16-LABEL: not_isfinite_or_nan_f: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll index f971080e02c5b..72c4397754ce6 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll @@ -2375,6 +2375,12 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1) ; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse ; GFX950-NEXT: scratch_load_dword v33, off, s32 offset:8 ; GFX950-NEXT: scratch_load_dword v32, off, s32 offset:4 ; GFX950-NEXT: scratch_load_dword v37, off, s32 offset:16 @@ -2402,12 +2408,6 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1) ; GFX950-NEXT: scratch_load_dword v31, off, s32 ; GFX950-NEXT: scratch_load_dword v35, off, s32 offset:104 ; GFX950-NEXT: scratch_load_dword v34, off, s32 offset:100 -; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse ; GFX950-NEXT: s_waitcnt vmcnt(25) ; GFX950-NEXT: v_max_f64 v[58:59], v[0:1], v[32:33] ; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[32:33] diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll index dfd67873c3b86..526988d1f36ac 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll @@ -2375,6 +2375,12 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1) ; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse ; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse ; GFX950-NEXT: scratch_load_dword v33, off, s32 offset:8 ; GFX950-NEXT: scratch_load_dword v32, off, s32 offset:4 ; GFX950-NEXT: scratch_load_dword v37, off, s32 offset:16 @@ -2402,12 +2408,6 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1) ; GFX950-NEXT: scratch_load_dword v31, off, s32 ; GFX950-NEXT: scratch_load_dword v35, off, s32 offset:104 ; GFX950-NEXT: scratch_load_dword v34, off, s32 offset:100 -; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse -; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse ; GFX950-NEXT: s_waitcnt vmcnt(25) ; GFX950-NEXT: v_min_f64 v[58:59], v[0:1], v[32:33] ; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[32:33] diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll index 5f0ca7bc42ae0..db80f5479d36b 100644 --- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll +++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll @@ -109,15 +109,15 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MUBUF-NEXT: s_mov_b32 s5, s33 ; MUBUF-NEXT: s_add_i32 s33, s32, 0x7ffc0 +; MUBUF-NEXT: s_mov_b32 s6, s34 ; MUBUF-NEXT: s_and_b32 s33, s33, 0xfff80000 +; MUBUF-NEXT: s_mov_b32 s34, s32 ; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33 ; MUBUF-NEXT: v_add_u32_e32 v3, 0x3000, v3 -; MUBUF-NEXT: s_mov_b32 s6, s34 ; MUBUF-NEXT: v_add_u32_e32 v2, 64, v3 ; MUBUF-NEXT: v_mov_b32_e32 v3, 0 ; MUBUF-NEXT: v_mov_b32_e32 v4, 0x2000 ; MUBUF-NEXT: s_mov_b32 s4, 0 -; MUBUF-NEXT: s_mov_b32 s34, s32 ; MUBUF-NEXT: s_add_i32 s32, s32, 0x200000 ; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], s33 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) @@ -145,11 +145,11 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_mov_b32 s32, s34 ; MUBUF-NEXT: s_mov_b32 s34, s6 -; MUBUF-NEXT: s_mov_b32 s33, s5 ; MUBUF-NEXT: v_add_co_u32_e32 v2, vcc, v4, v6 ; MUBUF-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v7, vcc ; MUBUF-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: s_mov_b32 s33, s5 ; MUBUF-NEXT: s_setpc_b64 s[30:31] ; ; FLATSCR-LABEL: func_local_stack_offset_uses_sp: @@ -157,8 +157,8 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s2, s33 ; FLATSCR-NEXT: s_add_i32 s33, s32, 0x1fff -; FLATSCR-NEXT: s_and_b32 s33, s33, 0xffffe000 ; FLATSCR-NEXT: s_mov_b32 s3, s34 +; FLATSCR-NEXT: s_and_b32 s33, s33, 0xffffe000 ; FLATSCR-NEXT: s_mov_b32 s34, s32 ; FLATSCR-NEXT: s_add_i32 s32, s32, 0x8000 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 0 @@ -186,11 +186,11 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s32, s34 ; FLATSCR-NEXT: s_mov_b32 s34, s3 -; FLATSCR-NEXT: s_mov_b32 s33, s2 ; FLATSCR-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; FLATSCR-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc ; FLATSCR-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: s_mov_b32 s33, s2 ; FLATSCR-NEXT: s_setpc_b64 s[30:31] entry: %pin.low = alloca i32, align 8192, addrspace(5) diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll index b689e1e51c2a4..4499d887617f3 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 ; RUN: opt -S -mtriple=amdgcn--amdhsa -passes=amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefix=OPT %s ; RUN: llc -mtriple=amdgcn--amdhsa < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefix=GCN %s diff --git a/llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir b/llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir index ddd8a4784ea86..fff03a8e8e07e 100644 --- a/llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir +++ b/llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir @@ -718,7 +718,7 @@ name: smfma4x4_write_vgpr_dot_write body: | bb.0: $vgpr0_vgpr1_vgpr2_vgpr3 = V_MFMA_F32_4X4X1F32_vgprcd_e64 $vgpr1, $vgpr0, $vgpr0_vgpr1_vgpr2_vgpr3, 0, 0, 0, implicit $mode, implicit $exec - $vgpr1 = V_DOT8_I32_I4 0, $vgpr4, 0, $vgpr4, 0, $vgpr4, 0, 0, 0, implicit $mode, implicit $exec + $vgpr1 = V_DOT8_I32_I4 0, $vgpr4, 0, $vgpr4, 0, $vgpr4, 0, 0, 0, 0, 0, implicit $mode, implicit $exec ... # GCN-LABEL: name: smfma4x4_read_srcc_vgpr_valu_write # GCN: V_MFMA @@ -916,7 +916,7 @@ name: dot_write_vgpr_different_dot_read_srcc body: | bb.0: $vgpr4 = V_DOT4C_I32_I8_e32 $vgpr0, $vgpr1, $vgpr4, implicit $exec - $vgpr1 = V_DOT8_I32_I4 0, $vgpr0, 0, $vgpr0, 0, $vgpr4, 0, 0, 0, implicit $mode, implicit $exec + $vgpr1 = V_DOT8_I32_I4 0, $vgpr0, 0, $vgpr0, 0, $vgpr4, 0, 0, 0, 0, 0, implicit $mode, implicit $exec ... # GCN-LABEL: name: dot_write_vgpr_different_dot_write # GCN: V_DOT @@ -926,7 +926,7 @@ name: dot_write_vgpr_different_dot_write body: | bb.0: $vgpr4 = V_DOT4C_I32_I8_e32 $vgpr0, $vgpr1, $vgpr4, implicit $exec - $vgpr4 = V_DOT8_I32_I4 0, $vgpr0, 0, $vgpr0, 0, $vgpr0, 0, 0, 0, implicit $mode, implicit $exec + $vgpr4 = V_DOT8_I32_I4 0, $vgpr0, 0, $vgpr0, 0, $vgpr0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec ... # GCN-LABEL: name: dot_write_vgpr_different_valu_read # GCN: V_DOT diff --git a/llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir b/llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir index 1ef6b4c844c93..a4b82a4d3597a 100644 --- a/llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir +++ b/llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir @@ -1023,7 +1023,7 @@ name: xdl_smfma4x4_write_vgpr_dot_write body: | bb.0: $vgpr0_vgpr1_vgpr2_vgpr3 = V_MFMA_I32_4X4X4I8_vgprcd_e64 $vgpr1, $vgpr0, $vgpr0_vgpr1_vgpr2_vgpr3, 0, 0, 0, implicit $mode, implicit $exec - $vgpr1 = V_DOT8_I32_I4 0, $vgpr4, 0, $vgpr4, 0, $vgpr4, 0, 0, 0, implicit $mode, implicit $exec + $vgpr1 = V_DOT8_I32_I4 0, $vgpr4, 0, $vgpr4, 0, $vgpr4, 0, 0, 0, 0, 0, implicit $mode, implicit $exec ... # GCN-LABEL: name: nonxdl_smfma4x4_read_srcc_vgpr_valu_write # GCN: V_MFMA @@ -1217,7 +1217,7 @@ name: dot_write_vgpr_different_dot_read_srcc body: | bb.0: $vgpr4 = V_DOT4C_I32_I8_e32 $vgpr0, $vgpr1, $vgpr4, implicit $exec - $vgpr1 = V_DOT8_I32_I4 0, $vgpr0, 0, $vgpr0, 0, $vgpr4, 0, 0, 0, implicit $mode, implicit $exec + $vgpr1 = V_DOT8_I32_I4 0, $vgpr0, 0, $vgpr0, 0, $vgpr4, 0, 0, 0, 0, 0, implicit $mode, implicit $exec ... # GCN-LABEL: name: dot_write_vgpr_different_dot_write # GCN: V_DOT @@ -1227,7 +1227,7 @@ name: dot_write_vgpr_different_dot_write body: | bb.0: $vgpr4 = V_DOT4C_I32_I8_e32 $vgpr0, $vgpr1, $vgpr4, implicit $exec - $vgpr4 = V_DOT8_I32_I4 0, $vgpr0, 0, $vgpr0, 0, $vgpr0, 0, 0, 0, implicit $mode, implicit $exec + $vgpr4 = V_DOT8_I32_I4 0, $vgpr0, 0, $vgpr0, 0, $vgpr0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec ... # GCN-LABEL: name: dot_write_vgpr_different_valu_read # GCN: V_DOT diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll index 4b5a7c207055a..52671f5d3deb4 100644 --- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll +++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll @@ -17,8 +17,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 { ; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill ; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10_1-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32 ; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0 +; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32 ; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo ; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0 ; GFX10_1-NEXT: ;;#ASMSTART @@ -46,8 +46,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 { ; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80880 ; GFX10_3-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill ; GFX10_3-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32 ; GFX10_3-NEXT: v_writelane_b32 v1, s55, 0 +; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32 ; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo ; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0 ; GFX10_3-NEXT: ;;#ASMSTART @@ -74,8 +74,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 { ; GFX11-NEXT: s_add_i32 s1, s32, 0x4044 ; GFX11-NEXT: scratch_store_b32 off, v1, s1 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-NEXT: s_add_i32 s0, s32, 64 ; GFX11-NEXT: v_writelane_b32 v1, s55, 0 +; GFX11-NEXT: s_add_i32 s0, s32, 64 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-NEXT: s_and_b32 s0, 0, exec_lo ; GFX11-NEXT: s_addc_u32 s0, s32, 0x4040 @@ -108,9 +109,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 { ; GFX12-NEXT: scratch_store_b32 off, v1, s32 offset:16388 ; 4-byte Folded Spill ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: s_mov_b32 exec_lo, s0 -; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-NEXT: s_and_b32 s0, 0, exec_lo ; GFX12-NEXT: v_writelane_b32 v1, s55, 0 +; GFX12-NEXT: s_and_b32 s0, 0, exec_lo ; GFX12-NEXT: s_add_co_ci_u32 s0, s32, 0x4000 ; GFX12-NEXT: v_mov_b32_e32 v0, s32 ; GFX12-NEXT: s_wait_alu 0xfffe @@ -139,9 +139,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 { ; GFX8-NEXT: s_add_i32 s6, s32, 0x101100 ; GFX8-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_writelane_b32 v1, s55, 0 ; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0 -; GFX8-NEXT: v_writelane_b32 v1, s55, 0 ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use alloca0 v0 ; GFX8-NEXT: ;;#ASMEND @@ -168,6 +168,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 { ; GFX900-NEXT: s_add_i32 s6, s32, 0x101100 ; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] +; GFX900-NEXT: v_writelane_b32 v1, s55, 0 ; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32 ; GFX900-NEXT: v_add_u32_e32 v0, 64, v0 ; GFX900-NEXT: ;;#ASMSTART @@ -175,7 +176,6 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 { ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32 ; GFX900-NEXT: v_add_u32_e32 v0, 0x4040, v0 -; GFX900-NEXT: v_writelane_b32 v1, s55, 0 ; GFX900-NEXT: v_readfirstlane_b32 s55, v0 ; GFX900-NEXT: s_and_b64 s[4:5], 0, exec ; GFX900-NEXT: ;;#ASMSTART @@ -196,13 +196,13 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 { ; GFX942-NEXT: s_add_i32 s2, s32, 0x4044 ; GFX942-NEXT: scratch_store_dword off, v1, s2 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] +; GFX942-NEXT: v_writelane_b32 v1, s55, 0 ; GFX942-NEXT: s_add_i32 s0, s32, 64 ; GFX942-NEXT: v_mov_b32_e32 v0, s0 ; GFX942-NEXT: s_and_b64 s[0:1], 0, exec ; GFX942-NEXT: s_addc_u32 s0, s32, 0x4040 ; GFX942-NEXT: s_bitcmp1_b32 s0, 0 ; GFX942-NEXT: s_bitset0_b32 s0, 0 -; GFX942-NEXT: v_writelane_b32 v1, s55, 0 ; GFX942-NEXT: s_mov_b32 s55, s0 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use alloca0 v0 @@ -397,10 +397,10 @@ define void @scalar_mov_materializes_frame_index_dead_scc() #0 { ; GFX942-NEXT: s_add_i32 s2, s32, 0x4044 ; GFX942-NEXT: scratch_store_dword off, v1, s2 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] +; GFX942-NEXT: v_writelane_b32 v1, s55, 0 ; GFX942-NEXT: s_add_i32 s0, s32, 64 ; GFX942-NEXT: v_mov_b32_e32 v0, s0 ; GFX942-NEXT: s_add_i32 s0, s32, 0x4040 -; GFX942-NEXT: v_writelane_b32 v1, s55, 0 ; GFX942-NEXT: s_mov_b32 s55, s0 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use alloca0 v0 @@ -433,9 +433,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 { ; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10_1-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s33 -; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0 ; GFX10_1-NEXT: s_add_i32 s32, s32, 0x81000 +; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0 +; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s33 ; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo ; GFX10_1-NEXT: s_mov_b32 s32, s33 ; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0 @@ -467,9 +467,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 { ; GFX10_3-NEXT: s_add_i32 s6, s33, 0x80880 ; GFX10_3-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX10_3-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s33 -; GFX10_3-NEXT: v_writelane_b32 v1, s55, 0 ; GFX10_3-NEXT: s_add_i32 s32, s32, 0x81000 +; GFX10_3-NEXT: v_writelane_b32 v1, s55, 0 +; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s33 ; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo ; GFX10_3-NEXT: s_mov_b32 s32, s33 ; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0 @@ -501,8 +501,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 { ; GFX11-NEXT: scratch_store_b32 off, v1, s2 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: s_addk_i32 s32, 0x4080 -; GFX11-NEXT: s_add_i32 s0, s33, 64 ; GFX11-NEXT: v_writelane_b32 v1, s55, 0 +; GFX11-NEXT: s_add_i32 s0, s33, 64 +; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-NEXT: s_and_b32 s0, 0, exec_lo ; GFX11-NEXT: s_addc_u32 s0, s33, 0x4040 @@ -511,7 +512,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 { ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_bitcmp1_b32 s0, 0 ; GFX11-NEXT: s_bitset0_b32 s0, 0 -; GFX11-NEXT: s_mov_b32 s32, s33 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_mov_b32 s55, s0 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s55, scc @@ -539,8 +540,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 { ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: s_mov_b32 exec_lo, s0 ; GFX12-NEXT: s_addk_co_i32 s32, 0x4040 -; GFX12-NEXT: s_and_b32 s0, 0, exec_lo ; GFX12-NEXT: v_writelane_b32 v1, s55, 0 +; GFX12-NEXT: s_and_b32 s0, 0, exec_lo ; GFX12-NEXT: s_add_co_ci_u32 s0, s33, 0x4000 ; GFX12-NEXT: v_mov_b32_e32 v0, s33 ; GFX12-NEXT: s_wait_alu 0xfffe @@ -574,16 +575,16 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 { ; GFX8-NEXT: s_add_i32 s7, s33, 0x101100 ; GFX8-NEXT: buffer_store_dword v1, off, s[0:3], s7 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: s_add_i32 s32, s32, 0x102000 +; GFX8-NEXT: v_writelane_b32 v1, s55, 0 ; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s33 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0 -; GFX8-NEXT: v_writelane_b32 v1, s55, 0 ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use alloca0 v0 ; GFX8-NEXT: ;;#ASMEND ; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s33 ; GFX8-NEXT: s_movk_i32 s55, 0x4040 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s55, v0 -; GFX8-NEXT: s_add_i32 s32, s32, 0x102000 ; GFX8-NEXT: v_readfirstlane_b32 s55, v0 ; GFX8-NEXT: s_and_b64 s[4:5], 0, exec ; GFX8-NEXT: ;;#ASMSTART @@ -608,6 +609,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 { ; GFX900-NEXT: s_add_i32 s7, s33, 0x101100 ; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s7 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] +; GFX900-NEXT: s_add_i32 s32, s32, 0x102000 +; GFX900-NEXT: v_writelane_b32 v1, s55, 0 ; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s33 ; GFX900-NEXT: v_add_u32_e32 v0, 64, v0 ; GFX900-NEXT: ;;#ASMSTART @@ -615,8 +618,6 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 { ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s33 ; GFX900-NEXT: v_add_u32_e32 v0, 0x4040, v0 -; GFX900-NEXT: s_add_i32 s32, s32, 0x102000 -; GFX900-NEXT: v_writelane_b32 v1, s55, 0 ; GFX900-NEXT: v_readfirstlane_b32 s55, v0 ; GFX900-NEXT: s_and_b64 s[4:5], 0, exec ; GFX900-NEXT: ;;#ASMSTART @@ -642,13 +643,13 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 { ; GFX942-NEXT: scratch_store_dword off, v1, s3 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: s_addk_i32 s32, 0x4080 +; GFX942-NEXT: v_writelane_b32 v1, s55, 0 ; GFX942-NEXT: s_add_i32 s0, s33, 64 ; GFX942-NEXT: v_mov_b32_e32 v0, s0 ; GFX942-NEXT: s_and_b64 s[0:1], 0, exec ; GFX942-NEXT: s_addc_u32 s0, s33, 0x4040 ; GFX942-NEXT: s_bitcmp1_b32 s0, 0 ; GFX942-NEXT: s_bitset0_b32 s0, 0 -; GFX942-NEXT: v_writelane_b32 v1, s55, 0 ; GFX942-NEXT: s_mov_b32 s55, s0 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use alloca0 v0 @@ -681,8 +682,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset() ; GFX10_1-NEXT: buffer_store_dword v0, off, s[0:3], s5 ; 4-byte Folded Spill ; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10_1-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s32 ; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0 +; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s32 ; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo ; GFX10_1-NEXT: v_add_nc_u32_e32 v1, 64, v1 ; GFX10_1-NEXT: v_readfirstlane_b32 s55, v1 @@ -705,8 +706,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset() ; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80800 ; GFX10_3-NEXT: buffer_store_dword v0, off, s[0:3], s5 ; 4-byte Folded Spill ; GFX10_3-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_3-NEXT: v_lshrrev_b32_e64 v1, 5, s32 ; GFX10_3-NEXT: v_writelane_b32 v0, s55, 0 +; GFX10_3-NEXT: v_lshrrev_b32_e64 v1, 5, s32 ; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo ; GFX10_3-NEXT: v_add_nc_u32_e32 v1, 64, v1 ; GFX10_3-NEXT: v_readfirstlane_b32 s55, v1 @@ -728,13 +729,12 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset() ; GFX11-NEXT: s_add_i32 s1, s32, 0x4040 ; GFX11-NEXT: scratch_store_b32 off, v0, s1 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_and_b32 s0, 0, exec_lo ; GFX11-NEXT: v_writelane_b32 v0, s55, 0 +; GFX11-NEXT: s_and_b32 s0, 0, exec_lo ; GFX11-NEXT: s_addc_u32 s0, s32, 64 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_bitcmp1_b32 s0, 0 ; GFX11-NEXT: s_bitset0_b32 s0, 0 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_mov_b32 s55, s0 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s55, scc @@ -804,9 +804,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset() ; GFX900-NEXT: s_add_i32 s6, s32, 0x101000 ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] +; GFX900-NEXT: v_writelane_b32 v0, s55, 0 ; GFX900-NEXT: v_lshrrev_b32_e64 v1, 6, s32 ; GFX900-NEXT: v_add_u32_e32 v1, 64, v1 -; GFX900-NEXT: v_writelane_b32 v0, s55, 0 ; GFX900-NEXT: v_readfirstlane_b32 s55, v1 ; GFX900-NEXT: s_and_b64 s[4:5], 0, exec ; GFX900-NEXT: ;;#ASMSTART @@ -827,11 +827,11 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset() ; GFX942-NEXT: s_add_i32 s2, s32, 0x4040 ; GFX942-NEXT: scratch_store_dword off, v0, s2 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] +; GFX942-NEXT: v_writelane_b32 v0, s55, 0 ; GFX942-NEXT: s_and_b64 s[0:1], 0, exec ; GFX942-NEXT: s_addc_u32 s0, s32, 64 ; GFX942-NEXT: s_bitcmp1_b32 s0, 0 ; GFX942-NEXT: s_bitset0_b32 s0, 0 -; GFX942-NEXT: v_writelane_b32 v0, s55, 0 ; GFX942-NEXT: s_mov_b32 s55, s0 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s55, scc @@ -989,8 +989,8 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset() #0 ; GFX942-NEXT: s_add_i32 s2, s32, 0x4040 ; GFX942-NEXT: scratch_store_dword off, v0, s2 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] -; GFX942-NEXT: s_add_i32 s0, s32, 64 ; GFX942-NEXT: v_writelane_b32 v0, s55, 0 +; GFX942-NEXT: s_add_i32 s0, s32, 64 ; GFX942-NEXT: s_mov_b32 s55, s0 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s55 @@ -1018,9 +1018,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp ; GFX10_1-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10_1-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s33 -; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0 ; GFX10_1-NEXT: s_add_i32 s32, s32, 0x81000 +; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0 +; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s33 ; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo ; GFX10_1-NEXT: s_mov_b32 s32, s33 ; GFX10_1-NEXT: v_add_nc_u32_e32 v1, 64, v1 @@ -1047,9 +1047,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp ; GFX10_3-NEXT: s_add_i32 s6, s33, 0x80800 ; GFX10_3-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX10_3-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_3-NEXT: v_lshrrev_b32_e64 v1, 5, s33 -; GFX10_3-NEXT: v_writelane_b32 v0, s55, 0 ; GFX10_3-NEXT: s_add_i32 s32, s32, 0x81000 +; GFX10_3-NEXT: v_writelane_b32 v0, s55, 0 +; GFX10_3-NEXT: v_lshrrev_b32_e64 v1, 5, s33 ; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo ; GFX10_3-NEXT: s_mov_b32 s32, s33 ; GFX10_3-NEXT: v_add_nc_u32_e32 v1, 64, v1 @@ -1076,8 +1076,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp ; GFX11-NEXT: scratch_store_b32 off, v0, s2 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: s_addk_i32 s32, 0x4080 -; GFX11-NEXT: s_and_b32 s0, 0, exec_lo ; GFX11-NEXT: v_writelane_b32 v0, s55, 0 +; GFX11-NEXT: s_and_b32 s0, 0, exec_lo ; GFX11-NEXT: s_addc_u32 s0, s33, 64 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_bitcmp1_b32 s0, 0 @@ -1109,13 +1109,14 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp ; GFX12-NEXT: scratch_store_b32 off, v0, s33 offset:16384 ; 4-byte Folded Spill ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: s_mov_b32 exec_lo, s0 -; GFX12-NEXT: v_writelane_b32 v0, s55, 0 ; GFX12-NEXT: s_addk_co_i32 s32, 0x4040 +; GFX12-NEXT: v_writelane_b32 v0, s55, 0 ; GFX12-NEXT: s_mov_b32 s55, s33 ; GFX12-NEXT: s_and_b32 s0, 0, exec_lo ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; use s55, scc ; GFX12-NEXT: ;;#ASMEND +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_readlane_b32 s55, v0, 0 ; GFX12-NEXT: s_mov_b32 s32, s33 ; GFX12-NEXT: s_xor_saveexec_b32 s0, -1 @@ -1136,11 +1137,11 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp ; GFX8-NEXT: s_add_i32 s7, s33, 0x101000 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], s7 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: s_add_i32 s32, s32, 0x102000 ; GFX8-NEXT: v_writelane_b32 v0, s55, 0 ; GFX8-NEXT: v_lshrrev_b32_e64 v1, 6, s33 ; GFX8-NEXT: s_mov_b32 s55, 64 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, s55, v1 -; GFX8-NEXT: s_add_i32 s32, s32, 0x102000 ; GFX8-NEXT: v_readfirstlane_b32 s55, v1 ; GFX8-NEXT: s_and_b64 s[4:5], 0, exec ; GFX8-NEXT: ;;#ASMSTART @@ -1165,10 +1166,10 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp ; GFX900-NEXT: s_add_i32 s7, s33, 0x101000 ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s7 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] -; GFX900-NEXT: v_lshrrev_b32_e64 v1, 6, s33 -; GFX900-NEXT: v_add_u32_e32 v1, 64, v1 ; GFX900-NEXT: s_add_i32 s32, s32, 0x102000 ; GFX900-NEXT: v_writelane_b32 v0, s55, 0 +; GFX900-NEXT: v_lshrrev_b32_e64 v1, 6, s33 +; GFX900-NEXT: v_add_u32_e32 v1, 64, v1 ; GFX900-NEXT: v_readfirstlane_b32 s55, v1 ; GFX900-NEXT: s_and_b64 s[4:5], 0, exec ; GFX900-NEXT: ;;#ASMSTART @@ -1194,11 +1195,11 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp ; GFX942-NEXT: scratch_store_dword off, v0, s3 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: s_addk_i32 s32, 0x4080 +; GFX942-NEXT: v_writelane_b32 v0, s55, 0 ; GFX942-NEXT: s_and_b64 s[0:1], 0, exec ; GFX942-NEXT: s_addc_u32 s0, s33, 64 ; GFX942-NEXT: s_bitcmp1_b32 s0, 0 ; GFX942-NEXT: s_bitset0_b32 s0, 0 -; GFX942-NEXT: v_writelane_b32 v0, s55, 0 ; GFX942-NEXT: s_mov_b32 s55, s0 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s55, scc @@ -1228,8 +1229,8 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp() ; GFX10_1-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10_1-NEXT: s_mov_b32 exec_lo, s5 -; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0 ; GFX10_1-NEXT: s_add_i32 s32, s32, 0x81000 +; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0 ; GFX10_1-NEXT: s_lshr_b32 s55, s33, 5 ; GFX10_1-NEXT: s_mov_b32 s32, s33 ; GFX10_1-NEXT: s_add_i32 s55, s55, 64 @@ -1255,8 +1256,8 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp() ; GFX10_3-NEXT: s_add_i32 s6, s33, 0x80800 ; GFX10_3-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX10_3-NEXT: s_mov_b32 exec_lo, s5 -; GFX10_3-NEXT: v_writelane_b32 v0, s55, 0 ; GFX10_3-NEXT: s_add_i32 s32, s32, 0x81000 +; GFX10_3-NEXT: v_writelane_b32 v0, s55, 0 ; GFX10_3-NEXT: s_lshr_b32 s55, s33, 5 ; GFX10_3-NEXT: s_mov_b32 s32, s33 ; GFX10_3-NEXT: s_add_i32 s55, s55, 64 @@ -1281,8 +1282,8 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp() ; GFX11-NEXT: s_add_i32 s2, s33, 0x4040 ; GFX11-NEXT: scratch_store_b32 off, v0, s2 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v0, s55, 0 ; GFX11-NEXT: s_addk_i32 s32, 0x4080 +; GFX11-NEXT: v_writelane_b32 v0, s55, 0 ; GFX11-NEXT: s_add_i32 s1, s33, 64 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: s_mov_b32 s55, s1 @@ -1311,14 +1312,15 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp() ; GFX12-NEXT: scratch_store_b32 off, v0, s33 offset:16384 ; 4-byte Folded Spill ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: s_mov_b32 exec_lo, s1 -; GFX12-NEXT: v_writelane_b32 v0, s55, 0 ; GFX12-NEXT: s_addk_co_i32 s32, 0x4040 +; GFX12-NEXT: v_writelane_b32 v0, s55, 0 ; GFX12-NEXT: s_mov_b32 s55, s33 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; use s55 ; GFX12-NEXT: ;;#ASMEND -; GFX12-NEXT: s_mov_b32 s32, s33 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_readlane_b32 s55, v0, 0 +; GFX12-NEXT: s_mov_b32 s32, s33 ; GFX12-NEXT: s_xor_saveexec_b32 s1, -1 ; GFX12-NEXT: scratch_load_b32 v0, off, s33 offset:16384 ; 4-byte Folded Reload ; GFX12-NEXT: s_wait_alu 0xfffe @@ -1390,8 +1392,8 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp() ; GFX942-NEXT: scratch_store_dword off, v0, s1 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[2:3] ; GFX942-NEXT: s_addk_i32 s32, 0x4080 -; GFX942-NEXT: s_add_i32 s1, s33, 64 ; GFX942-NEXT: v_writelane_b32 v0, s55, 0 +; GFX942-NEXT: s_add_i32 s1, s33, 64 ; GFX942-NEXT: s_mov_b32 s55, s1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s55 @@ -1529,8 +1531,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset( ; GFX8-NEXT: s_add_i32 s6, s32, 0x201000 ; GFX8-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[4:5] -; GFX8-NEXT: s_lshr_b32 s4, s32, 6 ; GFX8-NEXT: v_writelane_b32 v1, s55, 0 +; GFX8-NEXT: s_lshr_b32 s4, s32, 6 ; GFX8-NEXT: s_add_i32 s55, s4, 0x442c ; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0 @@ -1556,8 +1558,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset( ; GFX900-NEXT: s_add_i32 s6, s32, 0x201000 ; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] -; GFX900-NEXT: s_lshr_b32 s4, s32, 6 ; GFX900-NEXT: v_writelane_b32 v1, s55, 0 +; GFX900-NEXT: s_lshr_b32 s4, s32, 6 ; GFX900-NEXT: s_add_i32 s55, s4, 0x442c ; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32 ; GFX900-NEXT: v_add_u32_e32 v0, 64, v0 @@ -1677,8 +1679,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse ; GFX11-NEXT: s_add_i32 s2, s32, 0x8040 ; GFX11-NEXT: scratch_store_b32 off, v1, s2 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: s_add_i32 s1, s32, 64 ; GFX11-NEXT: v_writelane_b32 v1, s55, 0 +; GFX11-NEXT: s_add_i32 s1, s32, 64 ; GFX11-NEXT: s_lshl_b32 s0, s0, 2 ; GFX11-NEXT: v_mov_b32_e32 v0, s1 ; GFX11-NEXT: s_add_i32 s55, s32, s0 @@ -1796,8 +1798,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse ; GFX942-NEXT: s_add_i32 s1, s32, 0x8040 ; GFX942-NEXT: scratch_store_dword off, v1, s1 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[2:3] -; GFX942-NEXT: s_lshl_b32 s0, s0, 2 ; GFX942-NEXT: v_writelane_b32 v1, s55, 0 +; GFX942-NEXT: s_lshl_b32 s0, s0, 2 ; GFX942-NEXT: s_add_i32 s55, s32, s0 ; GFX942-NEXT: s_addk_i32 s55, 0x4040 ; GFX942-NEXT: s_add_i32 s0, s32, 64 diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll index 17581bcb61e99..b0fee0fe0aa19 100644 --- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll +++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll @@ -37,26 +37,26 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX7-NEXT: s_add_i32 s6, s32, 0x101100 ; GFX7-NEXT: buffer_store_dword v23, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[4:5] -; GFX7-NEXT: v_writelane_b32 v23, s30, 0 -; GFX7-NEXT: v_writelane_b32 v23, s31, 1 -; GFX7-NEXT: v_writelane_b32 v23, s33, 2 -; GFX7-NEXT: v_writelane_b32 v23, s34, 3 -; GFX7-NEXT: v_writelane_b32 v23, s35, 4 -; GFX7-NEXT: v_writelane_b32 v23, s36, 5 -; GFX7-NEXT: v_writelane_b32 v23, s37, 6 -; GFX7-NEXT: v_writelane_b32 v23, s38, 7 -; GFX7-NEXT: v_writelane_b32 v23, s39, 8 -; GFX7-NEXT: v_writelane_b32 v23, s48, 9 -; GFX7-NEXT: v_writelane_b32 v23, s49, 10 -; GFX7-NEXT: v_writelane_b32 v23, s50, 11 -; GFX7-NEXT: v_writelane_b32 v23, s51, 12 -; GFX7-NEXT: v_writelane_b32 v23, s52, 13 -; GFX7-NEXT: v_writelane_b32 v23, s53, 14 +; GFX7-NEXT: v_writelane_b32 v23, s33, 0 +; GFX7-NEXT: v_writelane_b32 v23, s34, 1 +; GFX7-NEXT: v_writelane_b32 v23, s35, 2 +; GFX7-NEXT: v_writelane_b32 v23, s36, 3 +; GFX7-NEXT: v_writelane_b32 v23, s37, 4 +; GFX7-NEXT: v_writelane_b32 v23, s38, 5 +; GFX7-NEXT: v_writelane_b32 v23, s39, 6 +; GFX7-NEXT: v_writelane_b32 v23, s48, 7 +; GFX7-NEXT: v_writelane_b32 v23, s49, 8 +; GFX7-NEXT: v_writelane_b32 v23, s50, 9 +; GFX7-NEXT: v_writelane_b32 v23, s51, 10 +; GFX7-NEXT: v_writelane_b32 v23, s52, 11 +; GFX7-NEXT: v_writelane_b32 v23, s53, 12 +; GFX7-NEXT: v_writelane_b32 v23, s54, 13 +; GFX7-NEXT: v_writelane_b32 v23, s55, 14 +; GFX7-NEXT: v_writelane_b32 v23, s30, 15 +; GFX7-NEXT: v_writelane_b32 v23, s31, 16 ; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6 -; GFX7-NEXT: v_writelane_b32 v23, s54, 15 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, 64, v0 ; GFX7-NEXT: s_and_b64 s[4:5], 0, exec -; GFX7-NEXT: v_writelane_b32 v23, s55, 16 ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; use alloca0 v0 ; GFX7-NEXT: ;;#ASMEND @@ -73,23 +73,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc ; GFX7-NEXT: ;;#ASMEND -; GFX7-NEXT: v_readlane_b32 s55, v23, 16 -; GFX7-NEXT: v_readlane_b32 s54, v23, 15 -; GFX7-NEXT: v_readlane_b32 s53, v23, 14 -; GFX7-NEXT: v_readlane_b32 s52, v23, 13 -; GFX7-NEXT: v_readlane_b32 s51, v23, 12 -; GFX7-NEXT: v_readlane_b32 s50, v23, 11 -; GFX7-NEXT: v_readlane_b32 s49, v23, 10 -; GFX7-NEXT: v_readlane_b32 s48, v23, 9 -; GFX7-NEXT: v_readlane_b32 s39, v23, 8 -; GFX7-NEXT: v_readlane_b32 s38, v23, 7 -; GFX7-NEXT: v_readlane_b32 s37, v23, 6 -; GFX7-NEXT: v_readlane_b32 s36, v23, 5 -; GFX7-NEXT: v_readlane_b32 s35, v23, 4 -; GFX7-NEXT: v_readlane_b32 s34, v23, 3 -; GFX7-NEXT: v_readlane_b32 s33, v23, 2 -; GFX7-NEXT: v_readlane_b32 s31, v23, 1 -; GFX7-NEXT: v_readlane_b32 s30, v23, 0 +; GFX7-NEXT: v_readlane_b32 s30, v23, 15 +; GFX7-NEXT: v_readlane_b32 s31, v23, 16 +; GFX7-NEXT: v_readlane_b32 s55, v23, 14 +; GFX7-NEXT: v_readlane_b32 s54, v23, 13 +; GFX7-NEXT: v_readlane_b32 s53, v23, 12 +; GFX7-NEXT: v_readlane_b32 s52, v23, 11 +; GFX7-NEXT: v_readlane_b32 s51, v23, 10 +; GFX7-NEXT: v_readlane_b32 s50, v23, 9 +; GFX7-NEXT: v_readlane_b32 s49, v23, 8 +; GFX7-NEXT: v_readlane_b32 s48, v23, 7 +; GFX7-NEXT: v_readlane_b32 s39, v23, 6 +; GFX7-NEXT: v_readlane_b32 s38, v23, 5 +; GFX7-NEXT: v_readlane_b32 s37, v23, 4 +; GFX7-NEXT: v_readlane_b32 s36, v23, 3 +; GFX7-NEXT: v_readlane_b32 s35, v23, 2 +; GFX7-NEXT: v_readlane_b32 s34, v23, 1 +; GFX7-NEXT: v_readlane_b32 s33, v23, 0 ; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX7-NEXT: s_add_i32 s6, s32, 0x101100 ; GFX7-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload @@ -104,26 +104,26 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX8-NEXT: s_add_i32 s6, s32, 0x101100 ; GFX8-NEXT: buffer_store_dword v23, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[4:5] -; GFX8-NEXT: v_writelane_b32 v23, s30, 0 -; GFX8-NEXT: v_writelane_b32 v23, s31, 1 -; GFX8-NEXT: v_writelane_b32 v23, s33, 2 -; GFX8-NEXT: v_writelane_b32 v23, s34, 3 -; GFX8-NEXT: v_writelane_b32 v23, s35, 4 -; GFX8-NEXT: v_writelane_b32 v23, s36, 5 -; GFX8-NEXT: v_writelane_b32 v23, s37, 6 -; GFX8-NEXT: v_writelane_b32 v23, s38, 7 -; GFX8-NEXT: v_writelane_b32 v23, s39, 8 -; GFX8-NEXT: v_writelane_b32 v23, s48, 9 -; GFX8-NEXT: v_writelane_b32 v23, s49, 10 -; GFX8-NEXT: v_writelane_b32 v23, s50, 11 -; GFX8-NEXT: v_writelane_b32 v23, s51, 12 -; GFX8-NEXT: v_writelane_b32 v23, s52, 13 -; GFX8-NEXT: v_writelane_b32 v23, s53, 14 +; GFX8-NEXT: v_writelane_b32 v23, s33, 0 +; GFX8-NEXT: v_writelane_b32 v23, s34, 1 +; GFX8-NEXT: v_writelane_b32 v23, s35, 2 +; GFX8-NEXT: v_writelane_b32 v23, s36, 3 +; GFX8-NEXT: v_writelane_b32 v23, s37, 4 +; GFX8-NEXT: v_writelane_b32 v23, s38, 5 +; GFX8-NEXT: v_writelane_b32 v23, s39, 6 +; GFX8-NEXT: v_writelane_b32 v23, s48, 7 +; GFX8-NEXT: v_writelane_b32 v23, s49, 8 +; GFX8-NEXT: v_writelane_b32 v23, s50, 9 +; GFX8-NEXT: v_writelane_b32 v23, s51, 10 +; GFX8-NEXT: v_writelane_b32 v23, s52, 11 +; GFX8-NEXT: v_writelane_b32 v23, s53, 12 +; GFX8-NEXT: v_writelane_b32 v23, s54, 13 +; GFX8-NEXT: v_writelane_b32 v23, s55, 14 +; GFX8-NEXT: v_writelane_b32 v23, s30, 15 +; GFX8-NEXT: v_writelane_b32 v23, s31, 16 ; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32 -; GFX8-NEXT: v_writelane_b32 v23, s54, 15 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0 ; GFX8-NEXT: s_and_b64 s[4:5], 0, exec -; GFX8-NEXT: v_writelane_b32 v23, s55, 16 ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use alloca0 v0 ; GFX8-NEXT: ;;#ASMEND @@ -141,23 +141,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc ; GFX8-NEXT: ;;#ASMEND -; GFX8-NEXT: v_readlane_b32 s55, v23, 16 -; GFX8-NEXT: v_readlane_b32 s54, v23, 15 -; GFX8-NEXT: v_readlane_b32 s53, v23, 14 -; GFX8-NEXT: v_readlane_b32 s52, v23, 13 -; GFX8-NEXT: v_readlane_b32 s51, v23, 12 -; GFX8-NEXT: v_readlane_b32 s50, v23, 11 -; GFX8-NEXT: v_readlane_b32 s49, v23, 10 -; GFX8-NEXT: v_readlane_b32 s48, v23, 9 -; GFX8-NEXT: v_readlane_b32 s39, v23, 8 -; GFX8-NEXT: v_readlane_b32 s38, v23, 7 -; GFX8-NEXT: v_readlane_b32 s37, v23, 6 -; GFX8-NEXT: v_readlane_b32 s36, v23, 5 -; GFX8-NEXT: v_readlane_b32 s35, v23, 4 -; GFX8-NEXT: v_readlane_b32 s34, v23, 3 -; GFX8-NEXT: v_readlane_b32 s33, v23, 2 -; GFX8-NEXT: v_readlane_b32 s31, v23, 1 -; GFX8-NEXT: v_readlane_b32 s30, v23, 0 +; GFX8-NEXT: v_readlane_b32 s30, v23, 15 +; GFX8-NEXT: v_readlane_b32 s31, v23, 16 +; GFX8-NEXT: v_readlane_b32 s55, v23, 14 +; GFX8-NEXT: v_readlane_b32 s54, v23, 13 +; GFX8-NEXT: v_readlane_b32 s53, v23, 12 +; GFX8-NEXT: v_readlane_b32 s52, v23, 11 +; GFX8-NEXT: v_readlane_b32 s51, v23, 10 +; GFX8-NEXT: v_readlane_b32 s50, v23, 9 +; GFX8-NEXT: v_readlane_b32 s49, v23, 8 +; GFX8-NEXT: v_readlane_b32 s48, v23, 7 +; GFX8-NEXT: v_readlane_b32 s39, v23, 6 +; GFX8-NEXT: v_readlane_b32 s38, v23, 5 +; GFX8-NEXT: v_readlane_b32 s37, v23, 4 +; GFX8-NEXT: v_readlane_b32 s36, v23, 3 +; GFX8-NEXT: v_readlane_b32 s35, v23, 2 +; GFX8-NEXT: v_readlane_b32 s34, v23, 1 +; GFX8-NEXT: v_readlane_b32 s33, v23, 0 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: s_add_i32 s6, s32, 0x101100 ; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload @@ -172,26 +172,26 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX900-NEXT: s_add_i32 s6, s32, 0x101100 ; GFX900-NEXT: buffer_store_dword v23, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] -; GFX900-NEXT: v_writelane_b32 v23, s30, 0 -; GFX900-NEXT: v_writelane_b32 v23, s31, 1 -; GFX900-NEXT: v_writelane_b32 v23, s33, 2 -; GFX900-NEXT: v_writelane_b32 v23, s34, 3 -; GFX900-NEXT: v_writelane_b32 v23, s35, 4 -; GFX900-NEXT: v_writelane_b32 v23, s36, 5 -; GFX900-NEXT: v_writelane_b32 v23, s37, 6 -; GFX900-NEXT: v_writelane_b32 v23, s38, 7 -; GFX900-NEXT: v_writelane_b32 v23, s39, 8 -; GFX900-NEXT: v_writelane_b32 v23, s48, 9 -; GFX900-NEXT: v_writelane_b32 v23, s49, 10 -; GFX900-NEXT: v_writelane_b32 v23, s50, 11 -; GFX900-NEXT: v_writelane_b32 v23, s51, 12 -; GFX900-NEXT: v_writelane_b32 v23, s52, 13 -; GFX900-NEXT: v_writelane_b32 v23, s53, 14 +; GFX900-NEXT: v_writelane_b32 v23, s33, 0 +; GFX900-NEXT: v_writelane_b32 v23, s34, 1 +; GFX900-NEXT: v_writelane_b32 v23, s35, 2 +; GFX900-NEXT: v_writelane_b32 v23, s36, 3 +; GFX900-NEXT: v_writelane_b32 v23, s37, 4 +; GFX900-NEXT: v_writelane_b32 v23, s38, 5 +; GFX900-NEXT: v_writelane_b32 v23, s39, 6 +; GFX900-NEXT: v_writelane_b32 v23, s48, 7 +; GFX900-NEXT: v_writelane_b32 v23, s49, 8 +; GFX900-NEXT: v_writelane_b32 v23, s50, 9 +; GFX900-NEXT: v_writelane_b32 v23, s51, 10 +; GFX900-NEXT: v_writelane_b32 v23, s52, 11 +; GFX900-NEXT: v_writelane_b32 v23, s53, 12 +; GFX900-NEXT: v_writelane_b32 v23, s54, 13 +; GFX900-NEXT: v_writelane_b32 v23, s55, 14 +; GFX900-NEXT: v_writelane_b32 v23, s30, 15 +; GFX900-NEXT: v_writelane_b32 v23, s31, 16 ; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32 -; GFX900-NEXT: v_writelane_b32 v23, s54, 15 ; GFX900-NEXT: v_add_u32_e32 v0, 64, v0 ; GFX900-NEXT: s_and_b64 s[4:5], 0, exec -; GFX900-NEXT: v_writelane_b32 v23, s55, 16 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use alloca0 v0 ; GFX900-NEXT: ;;#ASMEND @@ -208,23 +208,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_readlane_b32 s55, v23, 16 -; GFX900-NEXT: v_readlane_b32 s54, v23, 15 -; GFX900-NEXT: v_readlane_b32 s53, v23, 14 -; GFX900-NEXT: v_readlane_b32 s52, v23, 13 -; GFX900-NEXT: v_readlane_b32 s51, v23, 12 -; GFX900-NEXT: v_readlane_b32 s50, v23, 11 -; GFX900-NEXT: v_readlane_b32 s49, v23, 10 -; GFX900-NEXT: v_readlane_b32 s48, v23, 9 -; GFX900-NEXT: v_readlane_b32 s39, v23, 8 -; GFX900-NEXT: v_readlane_b32 s38, v23, 7 -; GFX900-NEXT: v_readlane_b32 s37, v23, 6 -; GFX900-NEXT: v_readlane_b32 s36, v23, 5 -; GFX900-NEXT: v_readlane_b32 s35, v23, 4 -; GFX900-NEXT: v_readlane_b32 s34, v23, 3 -; GFX900-NEXT: v_readlane_b32 s33, v23, 2 -; GFX900-NEXT: v_readlane_b32 s31, v23, 1 -; GFX900-NEXT: v_readlane_b32 s30, v23, 0 +; GFX900-NEXT: v_readlane_b32 s30, v23, 15 +; GFX900-NEXT: v_readlane_b32 s31, v23, 16 +; GFX900-NEXT: v_readlane_b32 s55, v23, 14 +; GFX900-NEXT: v_readlane_b32 s54, v23, 13 +; GFX900-NEXT: v_readlane_b32 s53, v23, 12 +; GFX900-NEXT: v_readlane_b32 s52, v23, 11 +; GFX900-NEXT: v_readlane_b32 s51, v23, 10 +; GFX900-NEXT: v_readlane_b32 s50, v23, 9 +; GFX900-NEXT: v_readlane_b32 s49, v23, 8 +; GFX900-NEXT: v_readlane_b32 s48, v23, 7 +; GFX900-NEXT: v_readlane_b32 s39, v23, 6 +; GFX900-NEXT: v_readlane_b32 s38, v23, 5 +; GFX900-NEXT: v_readlane_b32 s37, v23, 4 +; GFX900-NEXT: v_readlane_b32 s36, v23, 3 +; GFX900-NEXT: v_readlane_b32 s35, v23, 2 +; GFX900-NEXT: v_readlane_b32 s34, v23, 1 +; GFX900-NEXT: v_readlane_b32 s33, v23, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: s_add_i32 s6, s32, 0x101100 ; GFX900-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload @@ -239,26 +239,27 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX942-NEXT: s_add_i32 s2, s32, 0x4044 ; GFX942-NEXT: scratch_store_dword off, v23, s2 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] -; GFX942-NEXT: v_writelane_b32 v23, s30, 0 -; GFX942-NEXT: v_writelane_b32 v23, s31, 1 -; GFX942-NEXT: v_writelane_b32 v23, s33, 2 -; GFX942-NEXT: v_writelane_b32 v23, s34, 3 -; GFX942-NEXT: v_writelane_b32 v23, s35, 4 -; GFX942-NEXT: v_writelane_b32 v23, s36, 5 -; GFX942-NEXT: v_writelane_b32 v23, s37, 6 -; GFX942-NEXT: v_writelane_b32 v23, s38, 7 -; GFX942-NEXT: v_writelane_b32 v23, s39, 8 -; GFX942-NEXT: v_writelane_b32 v23, s48, 9 -; GFX942-NEXT: v_writelane_b32 v23, s49, 10 -; GFX942-NEXT: v_writelane_b32 v23, s50, 11 -; GFX942-NEXT: v_writelane_b32 v23, s51, 12 -; GFX942-NEXT: v_writelane_b32 v23, s52, 13 -; GFX942-NEXT: v_writelane_b32 v23, s53, 14 +; GFX942-NEXT: v_writelane_b32 v23, s33, 0 +; GFX942-NEXT: v_writelane_b32 v23, s34, 1 +; GFX942-NEXT: v_writelane_b32 v23, s35, 2 +; GFX942-NEXT: v_writelane_b32 v23, s36, 3 +; GFX942-NEXT: v_writelane_b32 v23, s37, 4 +; GFX942-NEXT: v_writelane_b32 v23, s38, 5 +; GFX942-NEXT: v_writelane_b32 v23, s39, 6 +; GFX942-NEXT: v_writelane_b32 v23, s48, 7 +; GFX942-NEXT: v_writelane_b32 v23, s49, 8 +; GFX942-NEXT: v_writelane_b32 v23, s50, 9 +; GFX942-NEXT: v_writelane_b32 v23, s51, 10 +; GFX942-NEXT: v_writelane_b32 v23, s52, 11 +; GFX942-NEXT: v_writelane_b32 v23, s53, 12 +; GFX942-NEXT: v_writelane_b32 v23, s54, 13 +; GFX942-NEXT: v_writelane_b32 v23, s55, 14 +; GFX942-NEXT: v_writelane_b32 v23, s30, 15 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v23, s31, 16 ; GFX942-NEXT: s_add_i32 s0, s32, 64 -; GFX942-NEXT: v_writelane_b32 v23, s54, 15 ; GFX942-NEXT: v_mov_b32_e32 v0, s0 ; GFX942-NEXT: s_and_b64 s[60:61], 0, exec -; GFX942-NEXT: v_writelane_b32 v23, s55, 16 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use alloca0 v0 ; GFX942-NEXT: ;;#ASMEND @@ -273,23 +274,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_readlane_b32 s55, v23, 16 -; GFX942-NEXT: v_readlane_b32 s54, v23, 15 -; GFX942-NEXT: v_readlane_b32 s53, v23, 14 -; GFX942-NEXT: v_readlane_b32 s52, v23, 13 -; GFX942-NEXT: v_readlane_b32 s51, v23, 12 -; GFX942-NEXT: v_readlane_b32 s50, v23, 11 -; GFX942-NEXT: v_readlane_b32 s49, v23, 10 -; GFX942-NEXT: v_readlane_b32 s48, v23, 9 -; GFX942-NEXT: v_readlane_b32 s39, v23, 8 -; GFX942-NEXT: v_readlane_b32 s38, v23, 7 -; GFX942-NEXT: v_readlane_b32 s37, v23, 6 -; GFX942-NEXT: v_readlane_b32 s36, v23, 5 -; GFX942-NEXT: v_readlane_b32 s35, v23, 4 -; GFX942-NEXT: v_readlane_b32 s34, v23, 3 -; GFX942-NEXT: v_readlane_b32 s33, v23, 2 -; GFX942-NEXT: v_readlane_b32 s31, v23, 1 -; GFX942-NEXT: v_readlane_b32 s30, v23, 0 +; GFX942-NEXT: v_readlane_b32 s30, v23, 15 +; GFX942-NEXT: v_readlane_b32 s31, v23, 16 +; GFX942-NEXT: v_readlane_b32 s55, v23, 14 +; GFX942-NEXT: v_readlane_b32 s54, v23, 13 +; GFX942-NEXT: v_readlane_b32 s53, v23, 12 +; GFX942-NEXT: v_readlane_b32 s52, v23, 11 +; GFX942-NEXT: v_readlane_b32 s51, v23, 10 +; GFX942-NEXT: v_readlane_b32 s50, v23, 9 +; GFX942-NEXT: v_readlane_b32 s49, v23, 8 +; GFX942-NEXT: v_readlane_b32 s48, v23, 7 +; GFX942-NEXT: v_readlane_b32 s39, v23, 6 +; GFX942-NEXT: v_readlane_b32 s38, v23, 5 +; GFX942-NEXT: v_readlane_b32 s37, v23, 4 +; GFX942-NEXT: v_readlane_b32 s36, v23, 3 +; GFX942-NEXT: v_readlane_b32 s35, v23, 2 +; GFX942-NEXT: v_readlane_b32 s34, v23, 1 +; GFX942-NEXT: v_readlane_b32 s33, v23, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: s_add_i32 s2, s32, 0x4044 ; GFX942-NEXT: scratch_load_dword v23, off, s2 ; 4-byte Folded Reload @@ -305,29 +306,29 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX10_1-NEXT: buffer_store_dword v23, off, s[0:3], s5 ; 4-byte Folded Spill ; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10_1-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_1-NEXT: v_writelane_b32 v23, s30, 0 +; GFX10_1-NEXT: v_writelane_b32 v23, s33, 0 +; GFX10_1-NEXT: v_writelane_b32 v23, s34, 1 +; GFX10_1-NEXT: v_writelane_b32 v23, s35, 2 +; GFX10_1-NEXT: v_writelane_b32 v23, s36, 3 +; GFX10_1-NEXT: v_writelane_b32 v23, s37, 4 +; GFX10_1-NEXT: v_writelane_b32 v23, s38, 5 +; GFX10_1-NEXT: v_writelane_b32 v23, s39, 6 +; GFX10_1-NEXT: v_writelane_b32 v23, s48, 7 +; GFX10_1-NEXT: v_writelane_b32 v23, s49, 8 +; GFX10_1-NEXT: v_writelane_b32 v23, s50, 9 +; GFX10_1-NEXT: v_writelane_b32 v23, s51, 10 +; GFX10_1-NEXT: v_writelane_b32 v23, s52, 11 +; GFX10_1-NEXT: v_writelane_b32 v23, s53, 12 +; GFX10_1-NEXT: v_writelane_b32 v23, s54, 13 +; GFX10_1-NEXT: v_writelane_b32 v23, s55, 14 +; GFX10_1-NEXT: v_writelane_b32 v23, s30, 15 +; GFX10_1-NEXT: v_writelane_b32 v23, s31, 16 ; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32 ; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo -; GFX10_1-NEXT: v_writelane_b32 v23, s31, 1 ; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0 ; GFX10_1-NEXT: ;;#ASMSTART ; GFX10_1-NEXT: ; use alloca0 v0 ; GFX10_1-NEXT: ;;#ASMEND -; GFX10_1-NEXT: v_writelane_b32 v23, s33, 2 -; GFX10_1-NEXT: v_writelane_b32 v23, s34, 3 -; GFX10_1-NEXT: v_writelane_b32 v23, s35, 4 -; GFX10_1-NEXT: v_writelane_b32 v23, s36, 5 -; GFX10_1-NEXT: v_writelane_b32 v23, s37, 6 -; GFX10_1-NEXT: v_writelane_b32 v23, s38, 7 -; GFX10_1-NEXT: v_writelane_b32 v23, s39, 8 -; GFX10_1-NEXT: v_writelane_b32 v23, s48, 9 -; GFX10_1-NEXT: v_writelane_b32 v23, s49, 10 -; GFX10_1-NEXT: v_writelane_b32 v23, s50, 11 -; GFX10_1-NEXT: v_writelane_b32 v23, s51, 12 -; GFX10_1-NEXT: v_writelane_b32 v23, s52, 13 -; GFX10_1-NEXT: v_writelane_b32 v23, s53, 14 -; GFX10_1-NEXT: v_writelane_b32 v23, s54, 15 -; GFX10_1-NEXT: v_writelane_b32 v23, s55, 16 ; GFX10_1-NEXT: ;;#ASMSTART ; GFX10_1-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc ; GFX10_1-NEXT: ;;#ASMEND @@ -338,23 +339,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX10_1-NEXT: ;;#ASMSTART ; GFX10_1-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc ; GFX10_1-NEXT: ;;#ASMEND -; GFX10_1-NEXT: v_readlane_b32 s55, v23, 16 -; GFX10_1-NEXT: v_readlane_b32 s54, v23, 15 -; GFX10_1-NEXT: v_readlane_b32 s53, v23, 14 -; GFX10_1-NEXT: v_readlane_b32 s52, v23, 13 -; GFX10_1-NEXT: v_readlane_b32 s51, v23, 12 -; GFX10_1-NEXT: v_readlane_b32 s50, v23, 11 -; GFX10_1-NEXT: v_readlane_b32 s49, v23, 10 -; GFX10_1-NEXT: v_readlane_b32 s48, v23, 9 -; GFX10_1-NEXT: v_readlane_b32 s39, v23, 8 -; GFX10_1-NEXT: v_readlane_b32 s38, v23, 7 -; GFX10_1-NEXT: v_readlane_b32 s37, v23, 6 -; GFX10_1-NEXT: v_readlane_b32 s36, v23, 5 -; GFX10_1-NEXT: v_readlane_b32 s35, v23, 4 -; GFX10_1-NEXT: v_readlane_b32 s34, v23, 3 -; GFX10_1-NEXT: v_readlane_b32 s33, v23, 2 -; GFX10_1-NEXT: v_readlane_b32 s31, v23, 1 -; GFX10_1-NEXT: v_readlane_b32 s30, v23, 0 +; GFX10_1-NEXT: v_readlane_b32 s30, v23, 15 +; GFX10_1-NEXT: v_readlane_b32 s31, v23, 16 +; GFX10_1-NEXT: v_readlane_b32 s55, v23, 14 +; GFX10_1-NEXT: v_readlane_b32 s54, v23, 13 +; GFX10_1-NEXT: v_readlane_b32 s53, v23, 12 +; GFX10_1-NEXT: v_readlane_b32 s52, v23, 11 +; GFX10_1-NEXT: v_readlane_b32 s51, v23, 10 +; GFX10_1-NEXT: v_readlane_b32 s50, v23, 9 +; GFX10_1-NEXT: v_readlane_b32 s49, v23, 8 +; GFX10_1-NEXT: v_readlane_b32 s48, v23, 7 +; GFX10_1-NEXT: v_readlane_b32 s39, v23, 6 +; GFX10_1-NEXT: v_readlane_b32 s38, v23, 5 +; GFX10_1-NEXT: v_readlane_b32 s37, v23, 4 +; GFX10_1-NEXT: v_readlane_b32 s36, v23, 3 +; GFX10_1-NEXT: v_readlane_b32 s35, v23, 2 +; GFX10_1-NEXT: v_readlane_b32 s34, v23, 1 +; GFX10_1-NEXT: v_readlane_b32 s33, v23, 0 ; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80880 ; GFX10_1-NEXT: buffer_load_dword v23, off, s[0:3], s5 ; 4-byte Folded Reload @@ -370,29 +371,29 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80880 ; GFX10_3-NEXT: buffer_store_dword v23, off, s[0:3], s5 ; 4-byte Folded Spill ; GFX10_3-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_3-NEXT: v_writelane_b32 v23, s30, 0 +; GFX10_3-NEXT: v_writelane_b32 v23, s33, 0 +; GFX10_3-NEXT: v_writelane_b32 v23, s34, 1 +; GFX10_3-NEXT: v_writelane_b32 v23, s35, 2 +; GFX10_3-NEXT: v_writelane_b32 v23, s36, 3 +; GFX10_3-NEXT: v_writelane_b32 v23, s37, 4 +; GFX10_3-NEXT: v_writelane_b32 v23, s38, 5 +; GFX10_3-NEXT: v_writelane_b32 v23, s39, 6 +; GFX10_3-NEXT: v_writelane_b32 v23, s48, 7 +; GFX10_3-NEXT: v_writelane_b32 v23, s49, 8 +; GFX10_3-NEXT: v_writelane_b32 v23, s50, 9 +; GFX10_3-NEXT: v_writelane_b32 v23, s51, 10 +; GFX10_3-NEXT: v_writelane_b32 v23, s52, 11 +; GFX10_3-NEXT: v_writelane_b32 v23, s53, 12 +; GFX10_3-NEXT: v_writelane_b32 v23, s54, 13 +; GFX10_3-NEXT: v_writelane_b32 v23, s55, 14 +; GFX10_3-NEXT: v_writelane_b32 v23, s30, 15 +; GFX10_3-NEXT: v_writelane_b32 v23, s31, 16 ; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32 ; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo -; GFX10_3-NEXT: v_writelane_b32 v23, s31, 1 ; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0 ; GFX10_3-NEXT: ;;#ASMSTART ; GFX10_3-NEXT: ; use alloca0 v0 ; GFX10_3-NEXT: ;;#ASMEND -; GFX10_3-NEXT: v_writelane_b32 v23, s33, 2 -; GFX10_3-NEXT: v_writelane_b32 v23, s34, 3 -; GFX10_3-NEXT: v_writelane_b32 v23, s35, 4 -; GFX10_3-NEXT: v_writelane_b32 v23, s36, 5 -; GFX10_3-NEXT: v_writelane_b32 v23, s37, 6 -; GFX10_3-NEXT: v_writelane_b32 v23, s38, 7 -; GFX10_3-NEXT: v_writelane_b32 v23, s39, 8 -; GFX10_3-NEXT: v_writelane_b32 v23, s48, 9 -; GFX10_3-NEXT: v_writelane_b32 v23, s49, 10 -; GFX10_3-NEXT: v_writelane_b32 v23, s50, 11 -; GFX10_3-NEXT: v_writelane_b32 v23, s51, 12 -; GFX10_3-NEXT: v_writelane_b32 v23, s52, 13 -; GFX10_3-NEXT: v_writelane_b32 v23, s53, 14 -; GFX10_3-NEXT: v_writelane_b32 v23, s54, 15 -; GFX10_3-NEXT: v_writelane_b32 v23, s55, 16 ; GFX10_3-NEXT: ;;#ASMSTART ; GFX10_3-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc ; GFX10_3-NEXT: ;;#ASMEND @@ -403,23 +404,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX10_3-NEXT: ;;#ASMSTART ; GFX10_3-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc ; GFX10_3-NEXT: ;;#ASMEND -; GFX10_3-NEXT: v_readlane_b32 s55, v23, 16 -; GFX10_3-NEXT: v_readlane_b32 s54, v23, 15 -; GFX10_3-NEXT: v_readlane_b32 s53, v23, 14 -; GFX10_3-NEXT: v_readlane_b32 s52, v23, 13 -; GFX10_3-NEXT: v_readlane_b32 s51, v23, 12 -; GFX10_3-NEXT: v_readlane_b32 s50, v23, 11 -; GFX10_3-NEXT: v_readlane_b32 s49, v23, 10 -; GFX10_3-NEXT: v_readlane_b32 s48, v23, 9 -; GFX10_3-NEXT: v_readlane_b32 s39, v23, 8 -; GFX10_3-NEXT: v_readlane_b32 s38, v23, 7 -; GFX10_3-NEXT: v_readlane_b32 s37, v23, 6 -; GFX10_3-NEXT: v_readlane_b32 s36, v23, 5 -; GFX10_3-NEXT: v_readlane_b32 s35, v23, 4 -; GFX10_3-NEXT: v_readlane_b32 s34, v23, 3 -; GFX10_3-NEXT: v_readlane_b32 s33, v23, 2 -; GFX10_3-NEXT: v_readlane_b32 s31, v23, 1 -; GFX10_3-NEXT: v_readlane_b32 s30, v23, 0 +; GFX10_3-NEXT: v_readlane_b32 s30, v23, 15 +; GFX10_3-NEXT: v_readlane_b32 s31, v23, 16 +; GFX10_3-NEXT: v_readlane_b32 s55, v23, 14 +; GFX10_3-NEXT: v_readlane_b32 s54, v23, 13 +; GFX10_3-NEXT: v_readlane_b32 s53, v23, 12 +; GFX10_3-NEXT: v_readlane_b32 s52, v23, 11 +; GFX10_3-NEXT: v_readlane_b32 s51, v23, 10 +; GFX10_3-NEXT: v_readlane_b32 s50, v23, 9 +; GFX10_3-NEXT: v_readlane_b32 s49, v23, 8 +; GFX10_3-NEXT: v_readlane_b32 s48, v23, 7 +; GFX10_3-NEXT: v_readlane_b32 s39, v23, 6 +; GFX10_3-NEXT: v_readlane_b32 s38, v23, 5 +; GFX10_3-NEXT: v_readlane_b32 s37, v23, 4 +; GFX10_3-NEXT: v_readlane_b32 s36, v23, 3 +; GFX10_3-NEXT: v_readlane_b32 s35, v23, 2 +; GFX10_3-NEXT: v_readlane_b32 s34, v23, 1 +; GFX10_3-NEXT: v_readlane_b32 s33, v23, 0 ; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80880 ; GFX10_3-NEXT: buffer_load_dword v23, off, s[0:3], s5 ; 4-byte Folded Reload @@ -434,59 +435,59 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX11-NEXT: s_add_i32 s1, s32, 0x4044 ; GFX11-NEXT: scratch_store_b32 off, v23, s1 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-NEXT: v_writelane_b32 v23, s30, 0 +; GFX11-NEXT: v_writelane_b32 v23, s33, 0 +; GFX11-NEXT: v_writelane_b32 v23, s34, 1 +; GFX11-NEXT: v_writelane_b32 v23, s35, 2 +; GFX11-NEXT: v_writelane_b32 v23, s36, 3 +; GFX11-NEXT: v_writelane_b32 v23, s37, 4 +; GFX11-NEXT: v_writelane_b32 v23, s38, 5 +; GFX11-NEXT: v_writelane_b32 v23, s39, 6 +; GFX11-NEXT: v_writelane_b32 v23, s48, 7 +; GFX11-NEXT: v_writelane_b32 v23, s49, 8 +; GFX11-NEXT: v_writelane_b32 v23, s50, 9 +; GFX11-NEXT: v_writelane_b32 v23, s51, 10 +; GFX11-NEXT: v_writelane_b32 v23, s52, 11 +; GFX11-NEXT: v_writelane_b32 v23, s53, 12 +; GFX11-NEXT: v_writelane_b32 v23, s54, 13 +; GFX11-NEXT: v_writelane_b32 v23, s55, 14 +; GFX11-NEXT: v_writelane_b32 v23, s30, 15 +; GFX11-NEXT: v_writelane_b32 v23, s31, 16 ; GFX11-NEXT: s_add_i32 s0, s32, 64 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-NEXT: s_and_b32 s0, 0, exec_lo -; GFX11-NEXT: v_writelane_b32 v23, s31, 1 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use alloca0 v0 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_writelane_b32 v23, s33, 2 -; GFX11-NEXT: v_writelane_b32 v23, s34, 3 -; GFX11-NEXT: v_writelane_b32 v23, s35, 4 -; GFX11-NEXT: v_writelane_b32 v23, s36, 5 -; GFX11-NEXT: v_writelane_b32 v23, s37, 6 -; GFX11-NEXT: v_writelane_b32 v23, s38, 7 -; GFX11-NEXT: v_writelane_b32 v23, s39, 8 -; GFX11-NEXT: v_writelane_b32 v23, s48, 9 -; GFX11-NEXT: v_writelane_b32 v23, s49, 10 -; GFX11-NEXT: v_writelane_b32 v23, s50, 11 -; GFX11-NEXT: v_writelane_b32 v23, s51, 12 -; GFX11-NEXT: v_writelane_b32 v23, s52, 13 -; GFX11-NEXT: v_writelane_b32 v23, s53, 14 -; GFX11-NEXT: v_writelane_b32 v23, s54, 15 -; GFX11-NEXT: v_writelane_b32 v23, s55, 16 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_addc_u32 s59, s32, 0x4040 ; GFX11-NEXT: ; kill: def $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 killed $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 def $sgpr54 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_bitcmp1_b32 s59, 0 ; GFX11-NEXT: s_bitset0_b32 s59, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_mov_b32 s54, s59 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_readlane_b32 s55, v23, 16 -; GFX11-NEXT: v_readlane_b32 s54, v23, 15 -; GFX11-NEXT: v_readlane_b32 s53, v23, 14 -; GFX11-NEXT: v_readlane_b32 s52, v23, 13 -; GFX11-NEXT: v_readlane_b32 s51, v23, 12 -; GFX11-NEXT: v_readlane_b32 s50, v23, 11 -; GFX11-NEXT: v_readlane_b32 s49, v23, 10 -; GFX11-NEXT: v_readlane_b32 s48, v23, 9 -; GFX11-NEXT: v_readlane_b32 s39, v23, 8 -; GFX11-NEXT: v_readlane_b32 s38, v23, 7 -; GFX11-NEXT: v_readlane_b32 s37, v23, 6 -; GFX11-NEXT: v_readlane_b32 s36, v23, 5 -; GFX11-NEXT: v_readlane_b32 s35, v23, 4 -; GFX11-NEXT: v_readlane_b32 s34, v23, 3 -; GFX11-NEXT: v_readlane_b32 s33, v23, 2 -; GFX11-NEXT: v_readlane_b32 s31, v23, 1 -; GFX11-NEXT: v_readlane_b32 s30, v23, 0 +; GFX11-NEXT: v_readlane_b32 s30, v23, 15 +; GFX11-NEXT: v_readlane_b32 s31, v23, 16 +; GFX11-NEXT: v_readlane_b32 s55, v23, 14 +; GFX11-NEXT: v_readlane_b32 s54, v23, 13 +; GFX11-NEXT: v_readlane_b32 s53, v23, 12 +; GFX11-NEXT: v_readlane_b32 s52, v23, 11 +; GFX11-NEXT: v_readlane_b32 s51, v23, 10 +; GFX11-NEXT: v_readlane_b32 s50, v23, 9 +; GFX11-NEXT: v_readlane_b32 s49, v23, 8 +; GFX11-NEXT: v_readlane_b32 s48, v23, 7 +; GFX11-NEXT: v_readlane_b32 s39, v23, 6 +; GFX11-NEXT: v_readlane_b32 s38, v23, 5 +; GFX11-NEXT: v_readlane_b32 s37, v23, 4 +; GFX11-NEXT: v_readlane_b32 s36, v23, 3 +; GFX11-NEXT: v_readlane_b32 s35, v23, 2 +; GFX11-NEXT: v_readlane_b32 s34, v23, 1 +; GFX11-NEXT: v_readlane_b32 s33, v23, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: s_add_i32 s1, s32, 0x4044 ; GFX11-NEXT: scratch_load_b32 v23, off, s1 ; 4-byte Folded Reload @@ -505,28 +506,28 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX12-NEXT: scratch_store_b32 off, v23, s32 offset:16388 ; 4-byte Folded Spill ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: s_mov_b32 exec_lo, s0 -; GFX12-NEXT: v_writelane_b32 v23, s30, 0 +; GFX12-NEXT: v_writelane_b32 v23, s33, 0 +; GFX12-NEXT: v_writelane_b32 v23, s34, 1 +; GFX12-NEXT: v_writelane_b32 v23, s35, 2 +; GFX12-NEXT: v_writelane_b32 v23, s36, 3 +; GFX12-NEXT: v_writelane_b32 v23, s37, 4 +; GFX12-NEXT: v_writelane_b32 v23, s38, 5 +; GFX12-NEXT: v_writelane_b32 v23, s39, 6 +; GFX12-NEXT: v_writelane_b32 v23, s48, 7 +; GFX12-NEXT: v_writelane_b32 v23, s49, 8 +; GFX12-NEXT: v_writelane_b32 v23, s50, 9 +; GFX12-NEXT: v_writelane_b32 v23, s51, 10 +; GFX12-NEXT: v_writelane_b32 v23, s52, 11 +; GFX12-NEXT: v_writelane_b32 v23, s53, 12 +; GFX12-NEXT: v_writelane_b32 v23, s54, 13 +; GFX12-NEXT: v_writelane_b32 v23, s55, 14 +; GFX12-NEXT: v_writelane_b32 v23, s30, 15 +; GFX12-NEXT: v_writelane_b32 v23, s31, 16 ; GFX12-NEXT: v_mov_b32_e32 v0, s32 ; GFX12-NEXT: s_and_b32 s0, 0, exec_lo ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; use alloca0 v0 ; GFX12-NEXT: ;;#ASMEND -; GFX12-NEXT: v_writelane_b32 v23, s31, 1 -; GFX12-NEXT: v_writelane_b32 v23, s33, 2 -; GFX12-NEXT: v_writelane_b32 v23, s34, 3 -; GFX12-NEXT: v_writelane_b32 v23, s35, 4 -; GFX12-NEXT: v_writelane_b32 v23, s36, 5 -; GFX12-NEXT: v_writelane_b32 v23, s37, 6 -; GFX12-NEXT: v_writelane_b32 v23, s38, 7 -; GFX12-NEXT: v_writelane_b32 v23, s39, 8 -; GFX12-NEXT: v_writelane_b32 v23, s48, 9 -; GFX12-NEXT: v_writelane_b32 v23, s49, 10 -; GFX12-NEXT: v_writelane_b32 v23, s50, 11 -; GFX12-NEXT: v_writelane_b32 v23, s51, 12 -; GFX12-NEXT: v_writelane_b32 v23, s52, 13 -; GFX12-NEXT: v_writelane_b32 v23, s53, 14 -; GFX12-NEXT: v_writelane_b32 v23, s54, 15 -; GFX12-NEXT: v_writelane_b32 v23, s55, 16 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc ; GFX12-NEXT: ;;#ASMEND @@ -540,23 +541,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc ; GFX12-NEXT: ;;#ASMEND -; GFX12-NEXT: v_readlane_b32 s55, v23, 16 -; GFX12-NEXT: v_readlane_b32 s54, v23, 15 -; GFX12-NEXT: v_readlane_b32 s53, v23, 14 -; GFX12-NEXT: v_readlane_b32 s52, v23, 13 -; GFX12-NEXT: v_readlane_b32 s51, v23, 12 -; GFX12-NEXT: v_readlane_b32 s50, v23, 11 -; GFX12-NEXT: v_readlane_b32 s49, v23, 10 -; GFX12-NEXT: v_readlane_b32 s48, v23, 9 -; GFX12-NEXT: v_readlane_b32 s39, v23, 8 -; GFX12-NEXT: v_readlane_b32 s38, v23, 7 -; GFX12-NEXT: v_readlane_b32 s37, v23, 6 -; GFX12-NEXT: v_readlane_b32 s36, v23, 5 -; GFX12-NEXT: v_readlane_b32 s35, v23, 4 -; GFX12-NEXT: v_readlane_b32 s34, v23, 3 -; GFX12-NEXT: v_readlane_b32 s33, v23, 2 -; GFX12-NEXT: v_readlane_b32 s31, v23, 1 -; GFX12-NEXT: v_readlane_b32 s30, v23, 0 +; GFX12-NEXT: v_readlane_b32 s30, v23, 15 +; GFX12-NEXT: v_readlane_b32 s31, v23, 16 +; GFX12-NEXT: v_readlane_b32 s55, v23, 14 +; GFX12-NEXT: v_readlane_b32 s54, v23, 13 +; GFX12-NEXT: v_readlane_b32 s53, v23, 12 +; GFX12-NEXT: v_readlane_b32 s52, v23, 11 +; GFX12-NEXT: v_readlane_b32 s51, v23, 10 +; GFX12-NEXT: v_readlane_b32 s50, v23, 9 +; GFX12-NEXT: v_readlane_b32 s49, v23, 8 +; GFX12-NEXT: v_readlane_b32 s48, v23, 7 +; GFX12-NEXT: v_readlane_b32 s39, v23, 6 +; GFX12-NEXT: v_readlane_b32 s38, v23, 5 +; GFX12-NEXT: v_readlane_b32 s37, v23, 4 +; GFX12-NEXT: v_readlane_b32 s36, v23, 3 +; GFX12-NEXT: v_readlane_b32 s35, v23, 2 +; GFX12-NEXT: v_readlane_b32 s34, v23, 1 +; GFX12-NEXT: v_readlane_b32 s33, v23, 0 ; GFX12-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX12-NEXT: scratch_load_b32 v23, off, s32 offset:16388 ; 4-byte Folded Reload ; GFX12-NEXT: s_wait_alu 0xfffe @@ -613,24 +614,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX7-NEXT: s_add_i32 s6, s32, 0x100400 ; GFX7-NEXT: buffer_store_dword v21, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[4:5] -; GFX7-NEXT: v_writelane_b32 v21, s30, 0 -; GFX7-NEXT: v_writelane_b32 v21, s31, 1 -; GFX7-NEXT: v_writelane_b32 v21, s33, 2 -; GFX7-NEXT: v_writelane_b32 v21, s34, 3 -; GFX7-NEXT: v_writelane_b32 v21, s35, 4 -; GFX7-NEXT: v_writelane_b32 v21, s36, 5 -; GFX7-NEXT: v_writelane_b32 v21, s37, 6 -; GFX7-NEXT: v_writelane_b32 v21, s38, 7 -; GFX7-NEXT: v_writelane_b32 v21, s39, 8 -; GFX7-NEXT: v_writelane_b32 v21, s48, 9 -; GFX7-NEXT: v_writelane_b32 v21, s49, 10 -; GFX7-NEXT: v_writelane_b32 v21, s50, 11 -; GFX7-NEXT: v_writelane_b32 v21, s51, 12 -; GFX7-NEXT: v_writelane_b32 v21, s52, 13 -; GFX7-NEXT: v_writelane_b32 v21, s53, 14 -; GFX7-NEXT: v_writelane_b32 v21, s54, 15 +; GFX7-NEXT: v_writelane_b32 v21, s33, 0 +; GFX7-NEXT: v_writelane_b32 v21, s34, 1 +; GFX7-NEXT: v_writelane_b32 v21, s35, 2 +; GFX7-NEXT: v_writelane_b32 v21, s36, 3 +; GFX7-NEXT: v_writelane_b32 v21, s37, 4 +; GFX7-NEXT: v_writelane_b32 v21, s38, 5 +; GFX7-NEXT: v_writelane_b32 v21, s39, 6 +; GFX7-NEXT: v_writelane_b32 v21, s48, 7 +; GFX7-NEXT: v_writelane_b32 v21, s49, 8 +; GFX7-NEXT: v_writelane_b32 v21, s50, 9 +; GFX7-NEXT: v_writelane_b32 v21, s51, 10 +; GFX7-NEXT: v_writelane_b32 v21, s52, 11 +; GFX7-NEXT: v_writelane_b32 v21, s53, 12 +; GFX7-NEXT: v_writelane_b32 v21, s54, 13 +; GFX7-NEXT: v_writelane_b32 v21, s55, 14 +; GFX7-NEXT: v_writelane_b32 v21, s30, 15 +; GFX7-NEXT: v_writelane_b32 v21, s31, 16 ; GFX7-NEXT: s_and_b64 s[4:5], 0, exec -; GFX7-NEXT: v_writelane_b32 v21, s55, 16 ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc ; GFX7-NEXT: ;;#ASMEND @@ -640,23 +641,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc ; GFX7-NEXT: ;;#ASMEND -; GFX7-NEXT: v_readlane_b32 s55, v21, 16 -; GFX7-NEXT: v_readlane_b32 s54, v21, 15 -; GFX7-NEXT: v_readlane_b32 s53, v21, 14 -; GFX7-NEXT: v_readlane_b32 s52, v21, 13 -; GFX7-NEXT: v_readlane_b32 s51, v21, 12 -; GFX7-NEXT: v_readlane_b32 s50, v21, 11 -; GFX7-NEXT: v_readlane_b32 s49, v21, 10 -; GFX7-NEXT: v_readlane_b32 s48, v21, 9 -; GFX7-NEXT: v_readlane_b32 s39, v21, 8 -; GFX7-NEXT: v_readlane_b32 s38, v21, 7 -; GFX7-NEXT: v_readlane_b32 s37, v21, 6 -; GFX7-NEXT: v_readlane_b32 s36, v21, 5 -; GFX7-NEXT: v_readlane_b32 s35, v21, 4 -; GFX7-NEXT: v_readlane_b32 s34, v21, 3 -; GFX7-NEXT: v_readlane_b32 s33, v21, 2 -; GFX7-NEXT: v_readlane_b32 s31, v21, 1 -; GFX7-NEXT: v_readlane_b32 s30, v21, 0 +; GFX7-NEXT: v_readlane_b32 s30, v21, 15 +; GFX7-NEXT: v_readlane_b32 s31, v21, 16 +; GFX7-NEXT: v_readlane_b32 s55, v21, 14 +; GFX7-NEXT: v_readlane_b32 s54, v21, 13 +; GFX7-NEXT: v_readlane_b32 s53, v21, 12 +; GFX7-NEXT: v_readlane_b32 s52, v21, 11 +; GFX7-NEXT: v_readlane_b32 s51, v21, 10 +; GFX7-NEXT: v_readlane_b32 s50, v21, 9 +; GFX7-NEXT: v_readlane_b32 s49, v21, 8 +; GFX7-NEXT: v_readlane_b32 s48, v21, 7 +; GFX7-NEXT: v_readlane_b32 s39, v21, 6 +; GFX7-NEXT: v_readlane_b32 s38, v21, 5 +; GFX7-NEXT: v_readlane_b32 s37, v21, 4 +; GFX7-NEXT: v_readlane_b32 s36, v21, 3 +; GFX7-NEXT: v_readlane_b32 s35, v21, 2 +; GFX7-NEXT: v_readlane_b32 s34, v21, 1 +; GFX7-NEXT: v_readlane_b32 s33, v21, 0 ; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX7-NEXT: s_add_i32 s6, s32, 0x100400 ; GFX7-NEXT: buffer_load_dword v21, off, s[0:3], s6 ; 4-byte Folded Reload @@ -671,24 +672,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX8-NEXT: s_add_i32 s6, s32, 0x100400 ; GFX8-NEXT: buffer_store_dword v21, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[4:5] -; GFX8-NEXT: v_writelane_b32 v21, s30, 0 -; GFX8-NEXT: v_writelane_b32 v21, s31, 1 -; GFX8-NEXT: v_writelane_b32 v21, s33, 2 -; GFX8-NEXT: v_writelane_b32 v21, s34, 3 -; GFX8-NEXT: v_writelane_b32 v21, s35, 4 -; GFX8-NEXT: v_writelane_b32 v21, s36, 5 -; GFX8-NEXT: v_writelane_b32 v21, s37, 6 -; GFX8-NEXT: v_writelane_b32 v21, s38, 7 -; GFX8-NEXT: v_writelane_b32 v21, s39, 8 -; GFX8-NEXT: v_writelane_b32 v21, s48, 9 -; GFX8-NEXT: v_writelane_b32 v21, s49, 10 -; GFX8-NEXT: v_writelane_b32 v21, s50, 11 -; GFX8-NEXT: v_writelane_b32 v21, s51, 12 -; GFX8-NEXT: v_writelane_b32 v21, s52, 13 -; GFX8-NEXT: v_writelane_b32 v21, s53, 14 -; GFX8-NEXT: v_writelane_b32 v21, s54, 15 +; GFX8-NEXT: v_writelane_b32 v21, s33, 0 +; GFX8-NEXT: v_writelane_b32 v21, s34, 1 +; GFX8-NEXT: v_writelane_b32 v21, s35, 2 +; GFX8-NEXT: v_writelane_b32 v21, s36, 3 +; GFX8-NEXT: v_writelane_b32 v21, s37, 4 +; GFX8-NEXT: v_writelane_b32 v21, s38, 5 +; GFX8-NEXT: v_writelane_b32 v21, s39, 6 +; GFX8-NEXT: v_writelane_b32 v21, s48, 7 +; GFX8-NEXT: v_writelane_b32 v21, s49, 8 +; GFX8-NEXT: v_writelane_b32 v21, s50, 9 +; GFX8-NEXT: v_writelane_b32 v21, s51, 10 +; GFX8-NEXT: v_writelane_b32 v21, s52, 11 +; GFX8-NEXT: v_writelane_b32 v21, s53, 12 +; GFX8-NEXT: v_writelane_b32 v21, s54, 13 +; GFX8-NEXT: v_writelane_b32 v21, s55, 14 +; GFX8-NEXT: v_writelane_b32 v21, s30, 15 +; GFX8-NEXT: v_writelane_b32 v21, s31, 16 ; GFX8-NEXT: s_and_b64 s[4:5], 0, exec -; GFX8-NEXT: v_writelane_b32 v21, s55, 16 ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc ; GFX8-NEXT: ;;#ASMEND @@ -699,23 +700,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc ; GFX8-NEXT: ;;#ASMEND -; GFX8-NEXT: v_readlane_b32 s55, v21, 16 -; GFX8-NEXT: v_readlane_b32 s54, v21, 15 -; GFX8-NEXT: v_readlane_b32 s53, v21, 14 -; GFX8-NEXT: v_readlane_b32 s52, v21, 13 -; GFX8-NEXT: v_readlane_b32 s51, v21, 12 -; GFX8-NEXT: v_readlane_b32 s50, v21, 11 -; GFX8-NEXT: v_readlane_b32 s49, v21, 10 -; GFX8-NEXT: v_readlane_b32 s48, v21, 9 -; GFX8-NEXT: v_readlane_b32 s39, v21, 8 -; GFX8-NEXT: v_readlane_b32 s38, v21, 7 -; GFX8-NEXT: v_readlane_b32 s37, v21, 6 -; GFX8-NEXT: v_readlane_b32 s36, v21, 5 -; GFX8-NEXT: v_readlane_b32 s35, v21, 4 -; GFX8-NEXT: v_readlane_b32 s34, v21, 3 -; GFX8-NEXT: v_readlane_b32 s33, v21, 2 -; GFX8-NEXT: v_readlane_b32 s31, v21, 1 -; GFX8-NEXT: v_readlane_b32 s30, v21, 0 +; GFX8-NEXT: v_readlane_b32 s30, v21, 15 +; GFX8-NEXT: v_readlane_b32 s31, v21, 16 +; GFX8-NEXT: v_readlane_b32 s55, v21, 14 +; GFX8-NEXT: v_readlane_b32 s54, v21, 13 +; GFX8-NEXT: v_readlane_b32 s53, v21, 12 +; GFX8-NEXT: v_readlane_b32 s52, v21, 11 +; GFX8-NEXT: v_readlane_b32 s51, v21, 10 +; GFX8-NEXT: v_readlane_b32 s50, v21, 9 +; GFX8-NEXT: v_readlane_b32 s49, v21, 8 +; GFX8-NEXT: v_readlane_b32 s48, v21, 7 +; GFX8-NEXT: v_readlane_b32 s39, v21, 6 +; GFX8-NEXT: v_readlane_b32 s38, v21, 5 +; GFX8-NEXT: v_readlane_b32 s37, v21, 4 +; GFX8-NEXT: v_readlane_b32 s36, v21, 3 +; GFX8-NEXT: v_readlane_b32 s35, v21, 2 +; GFX8-NEXT: v_readlane_b32 s34, v21, 1 +; GFX8-NEXT: v_readlane_b32 s33, v21, 0 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: s_add_i32 s6, s32, 0x100400 ; GFX8-NEXT: buffer_load_dword v21, off, s[0:3], s6 ; 4-byte Folded Reload @@ -730,24 +731,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX900-NEXT: s_add_i32 s6, s32, 0x100400 ; GFX900-NEXT: buffer_store_dword v21, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] -; GFX900-NEXT: v_writelane_b32 v21, s30, 0 -; GFX900-NEXT: v_writelane_b32 v21, s31, 1 -; GFX900-NEXT: v_writelane_b32 v21, s33, 2 -; GFX900-NEXT: v_writelane_b32 v21, s34, 3 -; GFX900-NEXT: v_writelane_b32 v21, s35, 4 -; GFX900-NEXT: v_writelane_b32 v21, s36, 5 -; GFX900-NEXT: v_writelane_b32 v21, s37, 6 -; GFX900-NEXT: v_writelane_b32 v21, s38, 7 -; GFX900-NEXT: v_writelane_b32 v21, s39, 8 -; GFX900-NEXT: v_writelane_b32 v21, s48, 9 -; GFX900-NEXT: v_writelane_b32 v21, s49, 10 -; GFX900-NEXT: v_writelane_b32 v21, s50, 11 -; GFX900-NEXT: v_writelane_b32 v21, s51, 12 -; GFX900-NEXT: v_writelane_b32 v21, s52, 13 -; GFX900-NEXT: v_writelane_b32 v21, s53, 14 -; GFX900-NEXT: v_writelane_b32 v21, s54, 15 +; GFX900-NEXT: v_writelane_b32 v21, s33, 0 +; GFX900-NEXT: v_writelane_b32 v21, s34, 1 +; GFX900-NEXT: v_writelane_b32 v21, s35, 2 +; GFX900-NEXT: v_writelane_b32 v21, s36, 3 +; GFX900-NEXT: v_writelane_b32 v21, s37, 4 +; GFX900-NEXT: v_writelane_b32 v21, s38, 5 +; GFX900-NEXT: v_writelane_b32 v21, s39, 6 +; GFX900-NEXT: v_writelane_b32 v21, s48, 7 +; GFX900-NEXT: v_writelane_b32 v21, s49, 8 +; GFX900-NEXT: v_writelane_b32 v21, s50, 9 +; GFX900-NEXT: v_writelane_b32 v21, s51, 10 +; GFX900-NEXT: v_writelane_b32 v21, s52, 11 +; GFX900-NEXT: v_writelane_b32 v21, s53, 12 +; GFX900-NEXT: v_writelane_b32 v21, s54, 13 +; GFX900-NEXT: v_writelane_b32 v21, s55, 14 +; GFX900-NEXT: v_writelane_b32 v21, s30, 15 +; GFX900-NEXT: v_writelane_b32 v21, s31, 16 ; GFX900-NEXT: s_and_b64 s[4:5], 0, exec -; GFX900-NEXT: v_writelane_b32 v21, s55, 16 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc ; GFX900-NEXT: ;;#ASMEND @@ -758,23 +759,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_readlane_b32 s55, v21, 16 -; GFX900-NEXT: v_readlane_b32 s54, v21, 15 -; GFX900-NEXT: v_readlane_b32 s53, v21, 14 -; GFX900-NEXT: v_readlane_b32 s52, v21, 13 -; GFX900-NEXT: v_readlane_b32 s51, v21, 12 -; GFX900-NEXT: v_readlane_b32 s50, v21, 11 -; GFX900-NEXT: v_readlane_b32 s49, v21, 10 -; GFX900-NEXT: v_readlane_b32 s48, v21, 9 -; GFX900-NEXT: v_readlane_b32 s39, v21, 8 -; GFX900-NEXT: v_readlane_b32 s38, v21, 7 -; GFX900-NEXT: v_readlane_b32 s37, v21, 6 -; GFX900-NEXT: v_readlane_b32 s36, v21, 5 -; GFX900-NEXT: v_readlane_b32 s35, v21, 4 -; GFX900-NEXT: v_readlane_b32 s34, v21, 3 -; GFX900-NEXT: v_readlane_b32 s33, v21, 2 -; GFX900-NEXT: v_readlane_b32 s31, v21, 1 -; GFX900-NEXT: v_readlane_b32 s30, v21, 0 +; GFX900-NEXT: v_readlane_b32 s30, v21, 15 +; GFX900-NEXT: v_readlane_b32 s31, v21, 16 +; GFX900-NEXT: v_readlane_b32 s55, v21, 14 +; GFX900-NEXT: v_readlane_b32 s54, v21, 13 +; GFX900-NEXT: v_readlane_b32 s53, v21, 12 +; GFX900-NEXT: v_readlane_b32 s52, v21, 11 +; GFX900-NEXT: v_readlane_b32 s51, v21, 10 +; GFX900-NEXT: v_readlane_b32 s50, v21, 9 +; GFX900-NEXT: v_readlane_b32 s49, v21, 8 +; GFX900-NEXT: v_readlane_b32 s48, v21, 7 +; GFX900-NEXT: v_readlane_b32 s39, v21, 6 +; GFX900-NEXT: v_readlane_b32 s38, v21, 5 +; GFX900-NEXT: v_readlane_b32 s37, v21, 4 +; GFX900-NEXT: v_readlane_b32 s36, v21, 3 +; GFX900-NEXT: v_readlane_b32 s35, v21, 2 +; GFX900-NEXT: v_readlane_b32 s34, v21, 1 +; GFX900-NEXT: v_readlane_b32 s33, v21, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: s_add_i32 s6, s32, 0x100400 ; GFX900-NEXT: buffer_load_dword v21, off, s[0:3], s6 ; 4-byte Folded Reload @@ -789,24 +790,25 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX942-NEXT: s_add_i32 s2, s32, 0x4010 ; GFX942-NEXT: scratch_store_dword off, v21, s2 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] -; GFX942-NEXT: v_writelane_b32 v21, s30, 0 -; GFX942-NEXT: v_writelane_b32 v21, s31, 1 -; GFX942-NEXT: v_writelane_b32 v21, s33, 2 -; GFX942-NEXT: v_writelane_b32 v21, s34, 3 -; GFX942-NEXT: v_writelane_b32 v21, s35, 4 -; GFX942-NEXT: v_writelane_b32 v21, s36, 5 -; GFX942-NEXT: v_writelane_b32 v21, s37, 6 -; GFX942-NEXT: v_writelane_b32 v21, s38, 7 -; GFX942-NEXT: v_writelane_b32 v21, s39, 8 -; GFX942-NEXT: v_writelane_b32 v21, s48, 9 -; GFX942-NEXT: v_writelane_b32 v21, s49, 10 -; GFX942-NEXT: v_writelane_b32 v21, s50, 11 -; GFX942-NEXT: v_writelane_b32 v21, s51, 12 -; GFX942-NEXT: v_writelane_b32 v21, s52, 13 -; GFX942-NEXT: v_writelane_b32 v21, s53, 14 -; GFX942-NEXT: v_writelane_b32 v21, s54, 15 +; GFX942-NEXT: v_writelane_b32 v21, s33, 0 +; GFX942-NEXT: v_writelane_b32 v21, s34, 1 +; GFX942-NEXT: v_writelane_b32 v21, s35, 2 +; GFX942-NEXT: v_writelane_b32 v21, s36, 3 +; GFX942-NEXT: v_writelane_b32 v21, s37, 4 +; GFX942-NEXT: v_writelane_b32 v21, s38, 5 +; GFX942-NEXT: v_writelane_b32 v21, s39, 6 +; GFX942-NEXT: v_writelane_b32 v21, s48, 7 +; GFX942-NEXT: v_writelane_b32 v21, s49, 8 +; GFX942-NEXT: v_writelane_b32 v21, s50, 9 +; GFX942-NEXT: v_writelane_b32 v21, s51, 10 +; GFX942-NEXT: v_writelane_b32 v21, s52, 11 +; GFX942-NEXT: v_writelane_b32 v21, s53, 12 +; GFX942-NEXT: v_writelane_b32 v21, s54, 13 +; GFX942-NEXT: v_writelane_b32 v21, s55, 14 +; GFX942-NEXT: v_writelane_b32 v21, s30, 15 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v21, s31, 16 ; GFX942-NEXT: s_and_b64 s[60:61], 0, exec -; GFX942-NEXT: v_writelane_b32 v21, s55, 16 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc ; GFX942-NEXT: ;;#ASMEND @@ -818,23 +820,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_readlane_b32 s55, v21, 16 -; GFX942-NEXT: v_readlane_b32 s54, v21, 15 -; GFX942-NEXT: v_readlane_b32 s53, v21, 14 -; GFX942-NEXT: v_readlane_b32 s52, v21, 13 -; GFX942-NEXT: v_readlane_b32 s51, v21, 12 -; GFX942-NEXT: v_readlane_b32 s50, v21, 11 -; GFX942-NEXT: v_readlane_b32 s49, v21, 10 -; GFX942-NEXT: v_readlane_b32 s48, v21, 9 -; GFX942-NEXT: v_readlane_b32 s39, v21, 8 -; GFX942-NEXT: v_readlane_b32 s38, v21, 7 -; GFX942-NEXT: v_readlane_b32 s37, v21, 6 -; GFX942-NEXT: v_readlane_b32 s36, v21, 5 -; GFX942-NEXT: v_readlane_b32 s35, v21, 4 -; GFX942-NEXT: v_readlane_b32 s34, v21, 3 -; GFX942-NEXT: v_readlane_b32 s33, v21, 2 -; GFX942-NEXT: v_readlane_b32 s31, v21, 1 -; GFX942-NEXT: v_readlane_b32 s30, v21, 0 +; GFX942-NEXT: v_readlane_b32 s30, v21, 15 +; GFX942-NEXT: v_readlane_b32 s31, v21, 16 +; GFX942-NEXT: v_readlane_b32 s55, v21, 14 +; GFX942-NEXT: v_readlane_b32 s54, v21, 13 +; GFX942-NEXT: v_readlane_b32 s53, v21, 12 +; GFX942-NEXT: v_readlane_b32 s52, v21, 11 +; GFX942-NEXT: v_readlane_b32 s51, v21, 10 +; GFX942-NEXT: v_readlane_b32 s50, v21, 9 +; GFX942-NEXT: v_readlane_b32 s49, v21, 8 +; GFX942-NEXT: v_readlane_b32 s48, v21, 7 +; GFX942-NEXT: v_readlane_b32 s39, v21, 6 +; GFX942-NEXT: v_readlane_b32 s38, v21, 5 +; GFX942-NEXT: v_readlane_b32 s37, v21, 4 +; GFX942-NEXT: v_readlane_b32 s36, v21, 3 +; GFX942-NEXT: v_readlane_b32 s35, v21, 2 +; GFX942-NEXT: v_readlane_b32 s34, v21, 1 +; GFX942-NEXT: v_readlane_b32 s33, v21, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: s_add_i32 s2, s32, 0x4010 ; GFX942-NEXT: scratch_load_dword v21, off, s2 ; 4-byte Folded Reload @@ -850,51 +852,51 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX10_1-NEXT: buffer_store_dword v21, off, s[0:3], s5 ; 4-byte Folded Spill ; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10_1-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_1-NEXT: v_writelane_b32 v21, s30, 0 -; GFX10_1-NEXT: s_and_b32 s59, 0, exec_lo -; GFX10_1-NEXT: v_writelane_b32 v21, s31, 1 -; GFX10_1-NEXT: v_writelane_b32 v21, s33, 2 -; GFX10_1-NEXT: v_writelane_b32 v21, s34, 3 -; GFX10_1-NEXT: v_writelane_b32 v21, s35, 4 -; GFX10_1-NEXT: v_writelane_b32 v21, s36, 5 -; GFX10_1-NEXT: v_writelane_b32 v21, s37, 6 -; GFX10_1-NEXT: v_writelane_b32 v21, s38, 7 -; GFX10_1-NEXT: v_writelane_b32 v21, s39, 8 -; GFX10_1-NEXT: v_writelane_b32 v21, s48, 9 -; GFX10_1-NEXT: v_writelane_b32 v21, s49, 10 -; GFX10_1-NEXT: v_writelane_b32 v21, s50, 11 -; GFX10_1-NEXT: v_writelane_b32 v21, s51, 12 -; GFX10_1-NEXT: v_writelane_b32 v21, s52, 13 -; GFX10_1-NEXT: v_writelane_b32 v21, s53, 14 -; GFX10_1-NEXT: v_writelane_b32 v21, s54, 15 -; GFX10_1-NEXT: v_writelane_b32 v21, s55, 16 +; GFX10_1-NEXT: v_writelane_b32 v21, s33, 0 +; GFX10_1-NEXT: v_writelane_b32 v21, s34, 1 +; GFX10_1-NEXT: v_writelane_b32 v21, s35, 2 +; GFX10_1-NEXT: v_writelane_b32 v21, s36, 3 +; GFX10_1-NEXT: v_writelane_b32 v21, s37, 4 +; GFX10_1-NEXT: v_writelane_b32 v21, s38, 5 +; GFX10_1-NEXT: v_writelane_b32 v21, s39, 6 +; GFX10_1-NEXT: v_writelane_b32 v21, s48, 7 +; GFX10_1-NEXT: v_writelane_b32 v21, s49, 8 +; GFX10_1-NEXT: v_writelane_b32 v21, s50, 9 +; GFX10_1-NEXT: v_writelane_b32 v21, s51, 10 +; GFX10_1-NEXT: v_writelane_b32 v21, s52, 11 +; GFX10_1-NEXT: v_writelane_b32 v21, s53, 12 +; GFX10_1-NEXT: v_writelane_b32 v21, s54, 13 +; GFX10_1-NEXT: v_writelane_b32 v21, s55, 14 +; GFX10_1-NEXT: v_writelane_b32 v21, s30, 15 +; GFX10_1-NEXT: v_writelane_b32 v21, s31, 16 ; GFX10_1-NEXT: ;;#ASMSTART ; GFX10_1-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc ; GFX10_1-NEXT: ;;#ASMEND ; GFX10_1-NEXT: v_lshrrev_b32_e64 v22, 5, s32 ; GFX10_1-NEXT: ; kill: def $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 killed $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 def $sgpr54 +; GFX10_1-NEXT: s_and_b32 s59, 0, exec_lo ; GFX10_1-NEXT: v_add_nc_u32_e32 v22, 16, v22 ; GFX10_1-NEXT: v_readfirstlane_b32 s54, v22 ; GFX10_1-NEXT: ;;#ASMSTART ; GFX10_1-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc ; GFX10_1-NEXT: ;;#ASMEND -; GFX10_1-NEXT: v_readlane_b32 s55, v21, 16 -; GFX10_1-NEXT: v_readlane_b32 s54, v21, 15 -; GFX10_1-NEXT: v_readlane_b32 s53, v21, 14 -; GFX10_1-NEXT: v_readlane_b32 s52, v21, 13 -; GFX10_1-NEXT: v_readlane_b32 s51, v21, 12 -; GFX10_1-NEXT: v_readlane_b32 s50, v21, 11 -; GFX10_1-NEXT: v_readlane_b32 s49, v21, 10 -; GFX10_1-NEXT: v_readlane_b32 s48, v21, 9 -; GFX10_1-NEXT: v_readlane_b32 s39, v21, 8 -; GFX10_1-NEXT: v_readlane_b32 s38, v21, 7 -; GFX10_1-NEXT: v_readlane_b32 s37, v21, 6 -; GFX10_1-NEXT: v_readlane_b32 s36, v21, 5 -; GFX10_1-NEXT: v_readlane_b32 s35, v21, 4 -; GFX10_1-NEXT: v_readlane_b32 s34, v21, 3 -; GFX10_1-NEXT: v_readlane_b32 s33, v21, 2 -; GFX10_1-NEXT: v_readlane_b32 s31, v21, 1 -; GFX10_1-NEXT: v_readlane_b32 s30, v21, 0 +; GFX10_1-NEXT: v_readlane_b32 s30, v21, 15 +; GFX10_1-NEXT: v_readlane_b32 s31, v21, 16 +; GFX10_1-NEXT: v_readlane_b32 s55, v21, 14 +; GFX10_1-NEXT: v_readlane_b32 s54, v21, 13 +; GFX10_1-NEXT: v_readlane_b32 s53, v21, 12 +; GFX10_1-NEXT: v_readlane_b32 s52, v21, 11 +; GFX10_1-NEXT: v_readlane_b32 s51, v21, 10 +; GFX10_1-NEXT: v_readlane_b32 s50, v21, 9 +; GFX10_1-NEXT: v_readlane_b32 s49, v21, 8 +; GFX10_1-NEXT: v_readlane_b32 s48, v21, 7 +; GFX10_1-NEXT: v_readlane_b32 s39, v21, 6 +; GFX10_1-NEXT: v_readlane_b32 s38, v21, 5 +; GFX10_1-NEXT: v_readlane_b32 s37, v21, 4 +; GFX10_1-NEXT: v_readlane_b32 s36, v21, 3 +; GFX10_1-NEXT: v_readlane_b32 s35, v21, 2 +; GFX10_1-NEXT: v_readlane_b32 s34, v21, 1 +; GFX10_1-NEXT: v_readlane_b32 s33, v21, 0 ; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80200 ; GFX10_1-NEXT: buffer_load_dword v21, off, s[0:3], s5 ; 4-byte Folded Reload @@ -910,51 +912,51 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80200 ; GFX10_3-NEXT: buffer_store_dword v21, off, s[0:3], s5 ; 4-byte Folded Spill ; GFX10_3-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_3-NEXT: v_writelane_b32 v21, s30, 0 -; GFX10_3-NEXT: s_and_b32 s59, 0, exec_lo -; GFX10_3-NEXT: v_writelane_b32 v21, s31, 1 -; GFX10_3-NEXT: v_writelane_b32 v21, s33, 2 -; GFX10_3-NEXT: v_writelane_b32 v21, s34, 3 -; GFX10_3-NEXT: v_writelane_b32 v21, s35, 4 -; GFX10_3-NEXT: v_writelane_b32 v21, s36, 5 -; GFX10_3-NEXT: v_writelane_b32 v21, s37, 6 -; GFX10_3-NEXT: v_writelane_b32 v21, s38, 7 -; GFX10_3-NEXT: v_writelane_b32 v21, s39, 8 -; GFX10_3-NEXT: v_writelane_b32 v21, s48, 9 -; GFX10_3-NEXT: v_writelane_b32 v21, s49, 10 -; GFX10_3-NEXT: v_writelane_b32 v21, s50, 11 -; GFX10_3-NEXT: v_writelane_b32 v21, s51, 12 -; GFX10_3-NEXT: v_writelane_b32 v21, s52, 13 -; GFX10_3-NEXT: v_writelane_b32 v21, s53, 14 -; GFX10_3-NEXT: v_writelane_b32 v21, s54, 15 -; GFX10_3-NEXT: v_writelane_b32 v21, s55, 16 +; GFX10_3-NEXT: v_writelane_b32 v21, s33, 0 +; GFX10_3-NEXT: v_writelane_b32 v21, s34, 1 +; GFX10_3-NEXT: v_writelane_b32 v21, s35, 2 +; GFX10_3-NEXT: v_writelane_b32 v21, s36, 3 +; GFX10_3-NEXT: v_writelane_b32 v21, s37, 4 +; GFX10_3-NEXT: v_writelane_b32 v21, s38, 5 +; GFX10_3-NEXT: v_writelane_b32 v21, s39, 6 +; GFX10_3-NEXT: v_writelane_b32 v21, s48, 7 +; GFX10_3-NEXT: v_writelane_b32 v21, s49, 8 +; GFX10_3-NEXT: v_writelane_b32 v21, s50, 9 +; GFX10_3-NEXT: v_writelane_b32 v21, s51, 10 +; GFX10_3-NEXT: v_writelane_b32 v21, s52, 11 +; GFX10_3-NEXT: v_writelane_b32 v21, s53, 12 +; GFX10_3-NEXT: v_writelane_b32 v21, s54, 13 +; GFX10_3-NEXT: v_writelane_b32 v21, s55, 14 +; GFX10_3-NEXT: v_writelane_b32 v21, s30, 15 +; GFX10_3-NEXT: v_writelane_b32 v21, s31, 16 ; GFX10_3-NEXT: ;;#ASMSTART ; GFX10_3-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc ; GFX10_3-NEXT: ;;#ASMEND ; GFX10_3-NEXT: v_lshrrev_b32_e64 v22, 5, s32 ; GFX10_3-NEXT: ; kill: def $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 killed $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 def $sgpr54 +; GFX10_3-NEXT: s_and_b32 s59, 0, exec_lo ; GFX10_3-NEXT: v_add_nc_u32_e32 v22, 16, v22 ; GFX10_3-NEXT: v_readfirstlane_b32 s54, v22 ; GFX10_3-NEXT: ;;#ASMSTART ; GFX10_3-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc ; GFX10_3-NEXT: ;;#ASMEND -; GFX10_3-NEXT: v_readlane_b32 s55, v21, 16 -; GFX10_3-NEXT: v_readlane_b32 s54, v21, 15 -; GFX10_3-NEXT: v_readlane_b32 s53, v21, 14 -; GFX10_3-NEXT: v_readlane_b32 s52, v21, 13 -; GFX10_3-NEXT: v_readlane_b32 s51, v21, 12 -; GFX10_3-NEXT: v_readlane_b32 s50, v21, 11 -; GFX10_3-NEXT: v_readlane_b32 s49, v21, 10 -; GFX10_3-NEXT: v_readlane_b32 s48, v21, 9 -; GFX10_3-NEXT: v_readlane_b32 s39, v21, 8 -; GFX10_3-NEXT: v_readlane_b32 s38, v21, 7 -; GFX10_3-NEXT: v_readlane_b32 s37, v21, 6 -; GFX10_3-NEXT: v_readlane_b32 s36, v21, 5 -; GFX10_3-NEXT: v_readlane_b32 s35, v21, 4 -; GFX10_3-NEXT: v_readlane_b32 s34, v21, 3 -; GFX10_3-NEXT: v_readlane_b32 s33, v21, 2 -; GFX10_3-NEXT: v_readlane_b32 s31, v21, 1 -; GFX10_3-NEXT: v_readlane_b32 s30, v21, 0 +; GFX10_3-NEXT: v_readlane_b32 s30, v21, 15 +; GFX10_3-NEXT: v_readlane_b32 s31, v21, 16 +; GFX10_3-NEXT: v_readlane_b32 s55, v21, 14 +; GFX10_3-NEXT: v_readlane_b32 s54, v21, 13 +; GFX10_3-NEXT: v_readlane_b32 s53, v21, 12 +; GFX10_3-NEXT: v_readlane_b32 s52, v21, 11 +; GFX10_3-NEXT: v_readlane_b32 s51, v21, 10 +; GFX10_3-NEXT: v_readlane_b32 s50, v21, 9 +; GFX10_3-NEXT: v_readlane_b32 s49, v21, 8 +; GFX10_3-NEXT: v_readlane_b32 s48, v21, 7 +; GFX10_3-NEXT: v_readlane_b32 s39, v21, 6 +; GFX10_3-NEXT: v_readlane_b32 s38, v21, 5 +; GFX10_3-NEXT: v_readlane_b32 s37, v21, 4 +; GFX10_3-NEXT: v_readlane_b32 s36, v21, 3 +; GFX10_3-NEXT: v_readlane_b32 s35, v21, 2 +; GFX10_3-NEXT: v_readlane_b32 s34, v21, 1 +; GFX10_3-NEXT: v_readlane_b32 s33, v21, 0 ; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80200 ; GFX10_3-NEXT: buffer_load_dword v21, off, s[0:3], s5 ; 4-byte Folded Reload @@ -969,24 +971,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX11-NEXT: s_add_i32 s1, s32, 0x4010 ; GFX11-NEXT: scratch_store_b32 off, v21, s1 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-NEXT: v_writelane_b32 v21, s30, 0 +; GFX11-NEXT: v_writelane_b32 v21, s33, 0 +; GFX11-NEXT: v_writelane_b32 v21, s34, 1 +; GFX11-NEXT: v_writelane_b32 v21, s35, 2 +; GFX11-NEXT: v_writelane_b32 v21, s36, 3 +; GFX11-NEXT: v_writelane_b32 v21, s37, 4 +; GFX11-NEXT: v_writelane_b32 v21, s38, 5 +; GFX11-NEXT: v_writelane_b32 v21, s39, 6 +; GFX11-NEXT: v_writelane_b32 v21, s48, 7 +; GFX11-NEXT: v_writelane_b32 v21, s49, 8 +; GFX11-NEXT: v_writelane_b32 v21, s50, 9 +; GFX11-NEXT: v_writelane_b32 v21, s51, 10 +; GFX11-NEXT: v_writelane_b32 v21, s52, 11 +; GFX11-NEXT: v_writelane_b32 v21, s53, 12 +; GFX11-NEXT: v_writelane_b32 v21, s54, 13 +; GFX11-NEXT: v_writelane_b32 v21, s55, 14 +; GFX11-NEXT: v_writelane_b32 v21, s30, 15 +; GFX11-NEXT: v_writelane_b32 v21, s31, 16 ; GFX11-NEXT: s_and_b32 s59, 0, exec_lo -; GFX11-NEXT: v_writelane_b32 v21, s31, 1 -; GFX11-NEXT: v_writelane_b32 v21, s33, 2 -; GFX11-NEXT: v_writelane_b32 v21, s34, 3 -; GFX11-NEXT: v_writelane_b32 v21, s35, 4 -; GFX11-NEXT: v_writelane_b32 v21, s36, 5 -; GFX11-NEXT: v_writelane_b32 v21, s37, 6 -; GFX11-NEXT: v_writelane_b32 v21, s38, 7 -; GFX11-NEXT: v_writelane_b32 v21, s39, 8 -; GFX11-NEXT: v_writelane_b32 v21, s48, 9 -; GFX11-NEXT: v_writelane_b32 v21, s49, 10 -; GFX11-NEXT: v_writelane_b32 v21, s50, 11 -; GFX11-NEXT: v_writelane_b32 v21, s51, 12 -; GFX11-NEXT: v_writelane_b32 v21, s52, 13 -; GFX11-NEXT: v_writelane_b32 v21, s53, 14 -; GFX11-NEXT: v_writelane_b32 v21, s54, 15 -; GFX11-NEXT: v_writelane_b32 v21, s55, 16 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc ; GFX11-NEXT: ;;#ASMEND @@ -999,23 +1001,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_readlane_b32 s55, v21, 16 -; GFX11-NEXT: v_readlane_b32 s54, v21, 15 -; GFX11-NEXT: v_readlane_b32 s53, v21, 14 -; GFX11-NEXT: v_readlane_b32 s52, v21, 13 -; GFX11-NEXT: v_readlane_b32 s51, v21, 12 -; GFX11-NEXT: v_readlane_b32 s50, v21, 11 -; GFX11-NEXT: v_readlane_b32 s49, v21, 10 -; GFX11-NEXT: v_readlane_b32 s48, v21, 9 -; GFX11-NEXT: v_readlane_b32 s39, v21, 8 -; GFX11-NEXT: v_readlane_b32 s38, v21, 7 -; GFX11-NEXT: v_readlane_b32 s37, v21, 6 -; GFX11-NEXT: v_readlane_b32 s36, v21, 5 -; GFX11-NEXT: v_readlane_b32 s35, v21, 4 -; GFX11-NEXT: v_readlane_b32 s34, v21, 3 -; GFX11-NEXT: v_readlane_b32 s33, v21, 2 -; GFX11-NEXT: v_readlane_b32 s31, v21, 1 -; GFX11-NEXT: v_readlane_b32 s30, v21, 0 +; GFX11-NEXT: v_readlane_b32 s30, v21, 15 +; GFX11-NEXT: v_readlane_b32 s31, v21, 16 +; GFX11-NEXT: v_readlane_b32 s55, v21, 14 +; GFX11-NEXT: v_readlane_b32 s54, v21, 13 +; GFX11-NEXT: v_readlane_b32 s53, v21, 12 +; GFX11-NEXT: v_readlane_b32 s52, v21, 11 +; GFX11-NEXT: v_readlane_b32 s51, v21, 10 +; GFX11-NEXT: v_readlane_b32 s50, v21, 9 +; GFX11-NEXT: v_readlane_b32 s49, v21, 8 +; GFX11-NEXT: v_readlane_b32 s48, v21, 7 +; GFX11-NEXT: v_readlane_b32 s39, v21, 6 +; GFX11-NEXT: v_readlane_b32 s38, v21, 5 +; GFX11-NEXT: v_readlane_b32 s37, v21, 4 +; GFX11-NEXT: v_readlane_b32 s36, v21, 3 +; GFX11-NEXT: v_readlane_b32 s35, v21, 2 +; GFX11-NEXT: v_readlane_b32 s34, v21, 1 +; GFX11-NEXT: v_readlane_b32 s33, v21, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: s_add_i32 s1, s32, 0x4010 ; GFX11-NEXT: scratch_load_b32 v21, off, s1 ; 4-byte Folded Reload @@ -1034,50 +1036,49 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe ; GFX12-NEXT: scratch_store_b32 off, v21, s32 offset:16384 ; 4-byte Folded Spill ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: s_mov_b32 exec_lo, s0 -; GFX12-NEXT: v_writelane_b32 v21, s30, 0 -; GFX12-NEXT: s_and_b32 s59, 0, exec_lo -; GFX12-NEXT: v_writelane_b32 v21, s31, 1 -; GFX12-NEXT: v_writelane_b32 v21, s33, 2 -; GFX12-NEXT: v_writelane_b32 v21, s34, 3 -; GFX12-NEXT: v_writelane_b32 v21, s35, 4 -; GFX12-NEXT: v_writelane_b32 v21, s36, 5 -; GFX12-NEXT: v_writelane_b32 v21, s37, 6 -; GFX12-NEXT: v_writelane_b32 v21, s38, 7 -; GFX12-NEXT: v_writelane_b32 v21, s39, 8 -; GFX12-NEXT: v_writelane_b32 v21, s48, 9 -; GFX12-NEXT: v_writelane_b32 v21, s49, 10 -; GFX12-NEXT: v_writelane_b32 v21, s50, 11 -; GFX12-NEXT: v_writelane_b32 v21, s51, 12 -; GFX12-NEXT: v_writelane_b32 v21, s52, 13 -; GFX12-NEXT: v_writelane_b32 v21, s53, 14 -; GFX12-NEXT: v_writelane_b32 v21, s54, 15 -; GFX12-NEXT: v_writelane_b32 v21, s55, 16 +; GFX12-NEXT: v_writelane_b32 v21, s33, 0 +; GFX12-NEXT: v_writelane_b32 v21, s34, 1 +; GFX12-NEXT: v_writelane_b32 v21, s35, 2 +; GFX12-NEXT: v_writelane_b32 v21, s36, 3 +; GFX12-NEXT: v_writelane_b32 v21, s37, 4 +; GFX12-NEXT: v_writelane_b32 v21, s38, 5 +; GFX12-NEXT: v_writelane_b32 v21, s39, 6 +; GFX12-NEXT: v_writelane_b32 v21, s48, 7 +; GFX12-NEXT: v_writelane_b32 v21, s49, 8 +; GFX12-NEXT: v_writelane_b32 v21, s50, 9 +; GFX12-NEXT: v_writelane_b32 v21, s51, 10 +; GFX12-NEXT: v_writelane_b32 v21, s52, 11 +; GFX12-NEXT: v_writelane_b32 v21, s53, 12 +; GFX12-NEXT: v_writelane_b32 v21, s54, 13 +; GFX12-NEXT: v_writelane_b32 v21, s55, 14 +; GFX12-NEXT: v_writelane_b32 v21, s30, 15 +; GFX12-NEXT: v_writelane_b32 v21, s31, 16 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc ; GFX12-NEXT: ;;#ASMEND ; GFX12-NEXT: ; kill: def $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 killed $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 def $sgpr54 +; GFX12-NEXT: s_and_b32 s59, 0, exec_lo ; GFX12-NEXT: s_mov_b32 s54, s32 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc ; GFX12-NEXT: ;;#ASMEND -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_readlane_b32 s55, v21, 16 -; GFX12-NEXT: v_readlane_b32 s54, v21, 15 -; GFX12-NEXT: v_readlane_b32 s53, v21, 14 -; GFX12-NEXT: v_readlane_b32 s52, v21, 13 -; GFX12-NEXT: v_readlane_b32 s51, v21, 12 -; GFX12-NEXT: v_readlane_b32 s50, v21, 11 -; GFX12-NEXT: v_readlane_b32 s49, v21, 10 -; GFX12-NEXT: v_readlane_b32 s48, v21, 9 -; GFX12-NEXT: v_readlane_b32 s39, v21, 8 -; GFX12-NEXT: v_readlane_b32 s38, v21, 7 -; GFX12-NEXT: v_readlane_b32 s37, v21, 6 -; GFX12-NEXT: v_readlane_b32 s36, v21, 5 -; GFX12-NEXT: v_readlane_b32 s35, v21, 4 -; GFX12-NEXT: v_readlane_b32 s34, v21, 3 -; GFX12-NEXT: v_readlane_b32 s33, v21, 2 -; GFX12-NEXT: v_readlane_b32 s31, v21, 1 -; GFX12-NEXT: v_readlane_b32 s30, v21, 0 +; GFX12-NEXT: v_readlane_b32 s30, v21, 15 +; GFX12-NEXT: v_readlane_b32 s31, v21, 16 +; GFX12-NEXT: v_readlane_b32 s55, v21, 14 +; GFX12-NEXT: v_readlane_b32 s54, v21, 13 +; GFX12-NEXT: v_readlane_b32 s53, v21, 12 +; GFX12-NEXT: v_readlane_b32 s52, v21, 11 +; GFX12-NEXT: v_readlane_b32 s51, v21, 10 +; GFX12-NEXT: v_readlane_b32 s50, v21, 9 +; GFX12-NEXT: v_readlane_b32 s49, v21, 8 +; GFX12-NEXT: v_readlane_b32 s48, v21, 7 +; GFX12-NEXT: v_readlane_b32 s39, v21, 6 +; GFX12-NEXT: v_readlane_b32 s38, v21, 5 +; GFX12-NEXT: v_readlane_b32 s37, v21, 4 +; GFX12-NEXT: v_readlane_b32 s36, v21, 3 +; GFX12-NEXT: v_readlane_b32 s35, v21, 2 +; GFX12-NEXT: v_readlane_b32 s34, v21, 1 +; GFX12-NEXT: v_readlane_b32 s33, v21, 0 ; GFX12-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX12-NEXT: scratch_load_b32 v21, off, s32 offset:16384 ; 4-byte Folded Reload ; GFX12-NEXT: s_wait_alu 0xfffe @@ -1135,30 +1136,30 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX7-NEXT: s_mov_b64 exec, s[4:5] ; GFX7-NEXT: v_writelane_b32 v23, s28, 17 ; GFX7-NEXT: v_writelane_b32 v23, s29, 18 -; GFX7-NEXT: v_writelane_b32 v23, s30, 0 -; GFX7-NEXT: v_writelane_b32 v23, s31, 1 -; GFX7-NEXT: v_writelane_b32 v23, s33, 2 -; GFX7-NEXT: v_writelane_b32 v23, s34, 3 -; GFX7-NEXT: v_writelane_b32 v23, s35, 4 -; GFX7-NEXT: v_writelane_b32 v23, s36, 5 -; GFX7-NEXT: v_writelane_b32 v23, s37, 6 -; GFX7-NEXT: v_writelane_b32 v23, s38, 7 -; GFX7-NEXT: v_writelane_b32 v23, s39, 8 -; GFX7-NEXT: v_writelane_b32 v23, s48, 9 -; GFX7-NEXT: v_writelane_b32 v23, s49, 10 -; GFX7-NEXT: v_writelane_b32 v23, s50, 11 -; GFX7-NEXT: v_writelane_b32 v23, s51, 12 -; GFX7-NEXT: v_writelane_b32 v23, s52, 13 +; GFX7-NEXT: v_writelane_b32 v23, s33, 0 +; GFX7-NEXT: v_writelane_b32 v23, s34, 1 +; GFX7-NEXT: v_writelane_b32 v23, s35, 2 +; GFX7-NEXT: v_writelane_b32 v23, s36, 3 +; GFX7-NEXT: v_writelane_b32 v23, s37, 4 +; GFX7-NEXT: v_writelane_b32 v23, s38, 5 +; GFX7-NEXT: v_writelane_b32 v23, s39, 6 +; GFX7-NEXT: v_writelane_b32 v23, s48, 7 +; GFX7-NEXT: v_writelane_b32 v23, s49, 8 +; GFX7-NEXT: v_writelane_b32 v23, s50, 9 +; GFX7-NEXT: v_writelane_b32 v23, s51, 10 +; GFX7-NEXT: v_writelane_b32 v23, s52, 11 +; GFX7-NEXT: v_writelane_b32 v23, s53, 12 +; GFX7-NEXT: v_writelane_b32 v23, s54, 13 +; GFX7-NEXT: v_writelane_b32 v23, s55, 14 +; GFX7-NEXT: v_writelane_b32 v23, s30, 15 +; GFX7-NEXT: v_writelane_b32 v23, s31, 16 ; GFX7-NEXT: s_lshr_b32 s5, s32, 6 -; GFX7-NEXT: v_writelane_b32 v23, s53, 14 ; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6 ; GFX7-NEXT: s_add_i32 s4, s5, 0x4240 ; GFX7-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane -; GFX7-NEXT: v_writelane_b32 v23, s54, 15 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, 64, v0 ; GFX7-NEXT: v_writelane_b32 v22, s4, 0 ; GFX7-NEXT: s_and_b64 s[4:5], 0, exec -; GFX7-NEXT: v_writelane_b32 v23, s55, 16 ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; use alloca0 v0 ; GFX7-NEXT: ;;#ASMEND @@ -1169,23 +1170,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX7-NEXT: ;;#ASMSTART ; GFX7-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc ; GFX7-NEXT: ;;#ASMEND -; GFX7-NEXT: v_readlane_b32 s55, v23, 16 -; GFX7-NEXT: v_readlane_b32 s54, v23, 15 -; GFX7-NEXT: v_readlane_b32 s53, v23, 14 -; GFX7-NEXT: v_readlane_b32 s52, v23, 13 -; GFX7-NEXT: v_readlane_b32 s51, v23, 12 -; GFX7-NEXT: v_readlane_b32 s50, v23, 11 -; GFX7-NEXT: v_readlane_b32 s49, v23, 10 -; GFX7-NEXT: v_readlane_b32 s48, v23, 9 -; GFX7-NEXT: v_readlane_b32 s39, v23, 8 -; GFX7-NEXT: v_readlane_b32 s38, v23, 7 -; GFX7-NEXT: v_readlane_b32 s37, v23, 6 -; GFX7-NEXT: v_readlane_b32 s36, v23, 5 -; GFX7-NEXT: v_readlane_b32 s35, v23, 4 -; GFX7-NEXT: v_readlane_b32 s34, v23, 3 -; GFX7-NEXT: v_readlane_b32 s33, v23, 2 -; GFX7-NEXT: v_readlane_b32 s31, v23, 1 -; GFX7-NEXT: v_readlane_b32 s30, v23, 0 +; GFX7-NEXT: v_readlane_b32 s30, v23, 15 +; GFX7-NEXT: v_readlane_b32 s31, v23, 16 +; GFX7-NEXT: v_readlane_b32 s55, v23, 14 +; GFX7-NEXT: v_readlane_b32 s54, v23, 13 +; GFX7-NEXT: v_readlane_b32 s53, v23, 12 +; GFX7-NEXT: v_readlane_b32 s52, v23, 11 +; GFX7-NEXT: v_readlane_b32 s51, v23, 10 +; GFX7-NEXT: v_readlane_b32 s50, v23, 9 +; GFX7-NEXT: v_readlane_b32 s49, v23, 8 +; GFX7-NEXT: v_readlane_b32 s48, v23, 7 +; GFX7-NEXT: v_readlane_b32 s39, v23, 6 +; GFX7-NEXT: v_readlane_b32 s38, v23, 5 +; GFX7-NEXT: v_readlane_b32 s37, v23, 4 +; GFX7-NEXT: v_readlane_b32 s36, v23, 3 +; GFX7-NEXT: v_readlane_b32 s35, v23, 2 +; GFX7-NEXT: v_readlane_b32 s34, v23, 1 +; GFX7-NEXT: v_readlane_b32 s33, v23, 0 ; GFX7-NEXT: v_readlane_b32 s28, v23, 17 ; GFX7-NEXT: v_readlane_b32 s29, v23, 18 ; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1 @@ -1206,30 +1207,30 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX8-NEXT: s_add_i32 s6, s32, 0x201100 ; GFX8-NEXT: buffer_store_dword v22, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX8-NEXT: s_mov_b64 exec, s[4:5] -; GFX8-NEXT: v_writelane_b32 v23, s30, 0 -; GFX8-NEXT: v_writelane_b32 v23, s31, 1 -; GFX8-NEXT: v_writelane_b32 v23, s33, 2 -; GFX8-NEXT: v_writelane_b32 v23, s34, 3 -; GFX8-NEXT: v_writelane_b32 v23, s35, 4 -; GFX8-NEXT: v_writelane_b32 v23, s36, 5 -; GFX8-NEXT: v_writelane_b32 v23, s37, 6 -; GFX8-NEXT: v_writelane_b32 v23, s38, 7 -; GFX8-NEXT: v_writelane_b32 v23, s39, 8 -; GFX8-NEXT: v_writelane_b32 v23, s48, 9 -; GFX8-NEXT: v_writelane_b32 v23, s49, 10 -; GFX8-NEXT: v_writelane_b32 v23, s50, 11 -; GFX8-NEXT: v_writelane_b32 v23, s51, 12 -; GFX8-NEXT: v_writelane_b32 v23, s52, 13 +; GFX8-NEXT: v_writelane_b32 v23, s33, 0 +; GFX8-NEXT: v_writelane_b32 v23, s34, 1 +; GFX8-NEXT: v_writelane_b32 v23, s35, 2 +; GFX8-NEXT: v_writelane_b32 v23, s36, 3 +; GFX8-NEXT: v_writelane_b32 v23, s37, 4 +; GFX8-NEXT: v_writelane_b32 v23, s38, 5 +; GFX8-NEXT: v_writelane_b32 v23, s39, 6 +; GFX8-NEXT: v_writelane_b32 v23, s48, 7 +; GFX8-NEXT: v_writelane_b32 v23, s49, 8 +; GFX8-NEXT: v_writelane_b32 v23, s50, 9 +; GFX8-NEXT: v_writelane_b32 v23, s51, 10 +; GFX8-NEXT: v_writelane_b32 v23, s52, 11 +; GFX8-NEXT: v_writelane_b32 v23, s53, 12 +; GFX8-NEXT: v_writelane_b32 v23, s54, 13 +; GFX8-NEXT: v_writelane_b32 v23, s55, 14 +; GFX8-NEXT: v_writelane_b32 v23, s30, 15 +; GFX8-NEXT: v_writelane_b32 v23, s31, 16 ; GFX8-NEXT: s_lshr_b32 s5, s32, 6 -; GFX8-NEXT: v_writelane_b32 v23, s53, 14 ; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32 ; GFX8-NEXT: s_add_i32 s4, s5, 0x4240 ; GFX8-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane -; GFX8-NEXT: v_writelane_b32 v23, s54, 15 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0 ; GFX8-NEXT: v_writelane_b32 v22, s4, 0 ; GFX8-NEXT: s_and_b64 s[4:5], 0, exec -; GFX8-NEXT: v_writelane_b32 v23, s55, 16 ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use alloca0 v0 ; GFX8-NEXT: ;;#ASMEND @@ -1241,23 +1242,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX8-NEXT: ;;#ASMSTART ; GFX8-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc ; GFX8-NEXT: ;;#ASMEND -; GFX8-NEXT: v_readlane_b32 s55, v23, 16 -; GFX8-NEXT: v_readlane_b32 s54, v23, 15 -; GFX8-NEXT: v_readlane_b32 s53, v23, 14 -; GFX8-NEXT: v_readlane_b32 s52, v23, 13 -; GFX8-NEXT: v_readlane_b32 s51, v23, 12 -; GFX8-NEXT: v_readlane_b32 s50, v23, 11 -; GFX8-NEXT: v_readlane_b32 s49, v23, 10 -; GFX8-NEXT: v_readlane_b32 s48, v23, 9 -; GFX8-NEXT: v_readlane_b32 s39, v23, 8 -; GFX8-NEXT: v_readlane_b32 s38, v23, 7 -; GFX8-NEXT: v_readlane_b32 s37, v23, 6 -; GFX8-NEXT: v_readlane_b32 s36, v23, 5 -; GFX8-NEXT: v_readlane_b32 s35, v23, 4 -; GFX8-NEXT: v_readlane_b32 s34, v23, 3 -; GFX8-NEXT: v_readlane_b32 s33, v23, 2 -; GFX8-NEXT: v_readlane_b32 s31, v23, 1 -; GFX8-NEXT: v_readlane_b32 s30, v23, 0 +; GFX8-NEXT: v_readlane_b32 s30, v23, 15 +; GFX8-NEXT: v_readlane_b32 s31, v23, 16 +; GFX8-NEXT: v_readlane_b32 s55, v23, 14 +; GFX8-NEXT: v_readlane_b32 s54, v23, 13 +; GFX8-NEXT: v_readlane_b32 s53, v23, 12 +; GFX8-NEXT: v_readlane_b32 s52, v23, 11 +; GFX8-NEXT: v_readlane_b32 s51, v23, 10 +; GFX8-NEXT: v_readlane_b32 s50, v23, 9 +; GFX8-NEXT: v_readlane_b32 s49, v23, 8 +; GFX8-NEXT: v_readlane_b32 s48, v23, 7 +; GFX8-NEXT: v_readlane_b32 s39, v23, 6 +; GFX8-NEXT: v_readlane_b32 s38, v23, 5 +; GFX8-NEXT: v_readlane_b32 s37, v23, 4 +; GFX8-NEXT: v_readlane_b32 s36, v23, 3 +; GFX8-NEXT: v_readlane_b32 s35, v23, 2 +; GFX8-NEXT: v_readlane_b32 s34, v23, 1 +; GFX8-NEXT: v_readlane_b32 s33, v23, 0 ; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX8-NEXT: s_add_i32 s6, s32, 0x201000 ; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload @@ -1276,30 +1277,30 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX900-NEXT: s_add_i32 s6, s32, 0x201100 ; GFX900-NEXT: buffer_store_dword v22, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] -; GFX900-NEXT: v_writelane_b32 v23, s30, 0 -; GFX900-NEXT: v_writelane_b32 v23, s31, 1 -; GFX900-NEXT: v_writelane_b32 v23, s33, 2 -; GFX900-NEXT: v_writelane_b32 v23, s34, 3 -; GFX900-NEXT: v_writelane_b32 v23, s35, 4 -; GFX900-NEXT: v_writelane_b32 v23, s36, 5 -; GFX900-NEXT: v_writelane_b32 v23, s37, 6 -; GFX900-NEXT: v_writelane_b32 v23, s38, 7 -; GFX900-NEXT: v_writelane_b32 v23, s39, 8 -; GFX900-NEXT: v_writelane_b32 v23, s48, 9 -; GFX900-NEXT: v_writelane_b32 v23, s49, 10 -; GFX900-NEXT: v_writelane_b32 v23, s50, 11 -; GFX900-NEXT: v_writelane_b32 v23, s51, 12 -; GFX900-NEXT: v_writelane_b32 v23, s52, 13 +; GFX900-NEXT: v_writelane_b32 v23, s33, 0 +; GFX900-NEXT: v_writelane_b32 v23, s34, 1 +; GFX900-NEXT: v_writelane_b32 v23, s35, 2 +; GFX900-NEXT: v_writelane_b32 v23, s36, 3 +; GFX900-NEXT: v_writelane_b32 v23, s37, 4 +; GFX900-NEXT: v_writelane_b32 v23, s38, 5 +; GFX900-NEXT: v_writelane_b32 v23, s39, 6 +; GFX900-NEXT: v_writelane_b32 v23, s48, 7 +; GFX900-NEXT: v_writelane_b32 v23, s49, 8 +; GFX900-NEXT: v_writelane_b32 v23, s50, 9 +; GFX900-NEXT: v_writelane_b32 v23, s51, 10 +; GFX900-NEXT: v_writelane_b32 v23, s52, 11 +; GFX900-NEXT: v_writelane_b32 v23, s53, 12 +; GFX900-NEXT: v_writelane_b32 v23, s54, 13 +; GFX900-NEXT: v_writelane_b32 v23, s55, 14 +; GFX900-NEXT: v_writelane_b32 v23, s30, 15 +; GFX900-NEXT: v_writelane_b32 v23, s31, 16 ; GFX900-NEXT: s_lshr_b32 s5, s32, 6 -; GFX900-NEXT: v_writelane_b32 v23, s53, 14 ; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32 ; GFX900-NEXT: s_add_i32 s4, s5, 0x4240 ; GFX900-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane -; GFX900-NEXT: v_writelane_b32 v23, s54, 15 ; GFX900-NEXT: v_add_u32_e32 v0, 64, v0 ; GFX900-NEXT: v_writelane_b32 v22, s4, 0 ; GFX900-NEXT: s_and_b64 s[4:5], 0, exec -; GFX900-NEXT: v_writelane_b32 v23, s55, 16 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use alloca0 v0 ; GFX900-NEXT: ;;#ASMEND @@ -1311,23 +1312,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_readlane_b32 s55, v23, 16 -; GFX900-NEXT: v_readlane_b32 s54, v23, 15 -; GFX900-NEXT: v_readlane_b32 s53, v23, 14 -; GFX900-NEXT: v_readlane_b32 s52, v23, 13 -; GFX900-NEXT: v_readlane_b32 s51, v23, 12 -; GFX900-NEXT: v_readlane_b32 s50, v23, 11 -; GFX900-NEXT: v_readlane_b32 s49, v23, 10 -; GFX900-NEXT: v_readlane_b32 s48, v23, 9 -; GFX900-NEXT: v_readlane_b32 s39, v23, 8 -; GFX900-NEXT: v_readlane_b32 s38, v23, 7 -; GFX900-NEXT: v_readlane_b32 s37, v23, 6 -; GFX900-NEXT: v_readlane_b32 s36, v23, 5 -; GFX900-NEXT: v_readlane_b32 s35, v23, 4 -; GFX900-NEXT: v_readlane_b32 s34, v23, 3 -; GFX900-NEXT: v_readlane_b32 s33, v23, 2 -; GFX900-NEXT: v_readlane_b32 s31, v23, 1 -; GFX900-NEXT: v_readlane_b32 s30, v23, 0 +; GFX900-NEXT: v_readlane_b32 s30, v23, 15 +; GFX900-NEXT: v_readlane_b32 s31, v23, 16 +; GFX900-NEXT: v_readlane_b32 s55, v23, 14 +; GFX900-NEXT: v_readlane_b32 s54, v23, 13 +; GFX900-NEXT: v_readlane_b32 s53, v23, 12 +; GFX900-NEXT: v_readlane_b32 s52, v23, 11 +; GFX900-NEXT: v_readlane_b32 s51, v23, 10 +; GFX900-NEXT: v_readlane_b32 s50, v23, 9 +; GFX900-NEXT: v_readlane_b32 s49, v23, 8 +; GFX900-NEXT: v_readlane_b32 s48, v23, 7 +; GFX900-NEXT: v_readlane_b32 s39, v23, 6 +; GFX900-NEXT: v_readlane_b32 s38, v23, 5 +; GFX900-NEXT: v_readlane_b32 s37, v23, 4 +; GFX900-NEXT: v_readlane_b32 s36, v23, 3 +; GFX900-NEXT: v_readlane_b32 s35, v23, 2 +; GFX900-NEXT: v_readlane_b32 s34, v23, 1 +; GFX900-NEXT: v_readlane_b32 s33, v23, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: s_add_i32 s6, s32, 0x201000 ; GFX900-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload @@ -1344,25 +1345,26 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX942-NEXT: s_add_i32 s2, s32, 0x8040 ; GFX942-NEXT: scratch_store_dword off, v22, s2 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] -; GFX942-NEXT: v_writelane_b32 v22, s30, 0 -; GFX942-NEXT: v_writelane_b32 v22, s31, 1 -; GFX942-NEXT: v_writelane_b32 v22, s33, 2 -; GFX942-NEXT: v_writelane_b32 v22, s34, 3 -; GFX942-NEXT: v_writelane_b32 v22, s35, 4 -; GFX942-NEXT: v_writelane_b32 v22, s36, 5 -; GFX942-NEXT: v_writelane_b32 v22, s37, 6 -; GFX942-NEXT: v_writelane_b32 v22, s38, 7 -; GFX942-NEXT: v_writelane_b32 v22, s39, 8 -; GFX942-NEXT: v_writelane_b32 v22, s48, 9 -; GFX942-NEXT: v_writelane_b32 v22, s49, 10 -; GFX942-NEXT: v_writelane_b32 v22, s50, 11 -; GFX942-NEXT: v_writelane_b32 v22, s51, 12 -; GFX942-NEXT: v_writelane_b32 v22, s52, 13 -; GFX942-NEXT: v_writelane_b32 v22, s53, 14 +; GFX942-NEXT: v_writelane_b32 v22, s33, 0 +; GFX942-NEXT: v_writelane_b32 v22, s34, 1 +; GFX942-NEXT: v_writelane_b32 v22, s35, 2 +; GFX942-NEXT: v_writelane_b32 v22, s36, 3 +; GFX942-NEXT: v_writelane_b32 v22, s37, 4 +; GFX942-NEXT: v_writelane_b32 v22, s38, 5 +; GFX942-NEXT: v_writelane_b32 v22, s39, 6 +; GFX942-NEXT: v_writelane_b32 v22, s48, 7 +; GFX942-NEXT: v_writelane_b32 v22, s49, 8 +; GFX942-NEXT: v_writelane_b32 v22, s50, 9 +; GFX942-NEXT: v_writelane_b32 v22, s51, 10 +; GFX942-NEXT: v_writelane_b32 v22, s52, 11 +; GFX942-NEXT: v_writelane_b32 v22, s53, 12 +; GFX942-NEXT: v_writelane_b32 v22, s54, 13 +; GFX942-NEXT: v_writelane_b32 v22, s55, 14 +; GFX942-NEXT: v_writelane_b32 v22, s30, 15 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v22, s31, 16 ; GFX942-NEXT: s_add_i32 s0, s32, 64 -; GFX942-NEXT: v_writelane_b32 v22, s54, 15 ; GFX942-NEXT: v_mov_b32_e32 v0, s0 -; GFX942-NEXT: v_writelane_b32 v22, s55, 16 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use alloca0 v0 ; GFX942-NEXT: ;;#ASMEND @@ -1376,23 +1378,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_readlane_b32 s55, v22, 16 -; GFX942-NEXT: v_readlane_b32 s54, v22, 15 -; GFX942-NEXT: v_readlane_b32 s53, v22, 14 -; GFX942-NEXT: v_readlane_b32 s52, v22, 13 -; GFX942-NEXT: v_readlane_b32 s51, v22, 12 -; GFX942-NEXT: v_readlane_b32 s50, v22, 11 -; GFX942-NEXT: v_readlane_b32 s49, v22, 10 -; GFX942-NEXT: v_readlane_b32 s48, v22, 9 -; GFX942-NEXT: v_readlane_b32 s39, v22, 8 -; GFX942-NEXT: v_readlane_b32 s38, v22, 7 -; GFX942-NEXT: v_readlane_b32 s37, v22, 6 -; GFX942-NEXT: v_readlane_b32 s36, v22, 5 -; GFX942-NEXT: v_readlane_b32 s35, v22, 4 -; GFX942-NEXT: v_readlane_b32 s34, v22, 3 -; GFX942-NEXT: v_readlane_b32 s33, v22, 2 -; GFX942-NEXT: v_readlane_b32 s31, v22, 1 -; GFX942-NEXT: v_readlane_b32 s30, v22, 0 +; GFX942-NEXT: v_readlane_b32 s30, v22, 15 +; GFX942-NEXT: v_readlane_b32 s31, v22, 16 +; GFX942-NEXT: v_readlane_b32 s55, v22, 14 +; GFX942-NEXT: v_readlane_b32 s54, v22, 13 +; GFX942-NEXT: v_readlane_b32 s53, v22, 12 +; GFX942-NEXT: v_readlane_b32 s52, v22, 11 +; GFX942-NEXT: v_readlane_b32 s51, v22, 10 +; GFX942-NEXT: v_readlane_b32 s50, v22, 9 +; GFX942-NEXT: v_readlane_b32 s49, v22, 8 +; GFX942-NEXT: v_readlane_b32 s48, v22, 7 +; GFX942-NEXT: v_readlane_b32 s39, v22, 6 +; GFX942-NEXT: v_readlane_b32 s38, v22, 5 +; GFX942-NEXT: v_readlane_b32 s37, v22, 4 +; GFX942-NEXT: v_readlane_b32 s36, v22, 3 +; GFX942-NEXT: v_readlane_b32 s35, v22, 2 +; GFX942-NEXT: v_readlane_b32 s34, v22, 1 +; GFX942-NEXT: v_readlane_b32 s33, v22, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: s_add_i32 s2, s32, 0x8040 ; GFX942-NEXT: scratch_load_dword v22, off, s2 ; 4-byte Folded Reload @@ -1408,31 +1410,31 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX10_1-NEXT: buffer_store_dword v22, off, s[0:3], s5 ; 4-byte Folded Spill ; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10_1-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_1-NEXT: v_writelane_b32 v22, s30, 0 +; GFX10_1-NEXT: v_writelane_b32 v22, s33, 0 +; GFX10_1-NEXT: v_writelane_b32 v22, s34, 1 +; GFX10_1-NEXT: v_writelane_b32 v22, s35, 2 +; GFX10_1-NEXT: v_writelane_b32 v22, s36, 3 +; GFX10_1-NEXT: v_writelane_b32 v22, s37, 4 +; GFX10_1-NEXT: v_writelane_b32 v22, s38, 5 +; GFX10_1-NEXT: v_writelane_b32 v22, s39, 6 +; GFX10_1-NEXT: v_writelane_b32 v22, s48, 7 +; GFX10_1-NEXT: v_writelane_b32 v22, s49, 8 +; GFX10_1-NEXT: v_writelane_b32 v22, s50, 9 +; GFX10_1-NEXT: v_writelane_b32 v22, s51, 10 +; GFX10_1-NEXT: v_writelane_b32 v22, s52, 11 +; GFX10_1-NEXT: v_writelane_b32 v22, s53, 12 +; GFX10_1-NEXT: v_writelane_b32 v22, s54, 13 +; GFX10_1-NEXT: v_writelane_b32 v22, s55, 14 +; GFX10_1-NEXT: v_writelane_b32 v22, s30, 15 +; GFX10_1-NEXT: v_writelane_b32 v22, s31, 16 ; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32 ; GFX10_1-NEXT: s_lshr_b32 s4, s32, 5 ; GFX10_1-NEXT: s_add_i32 s58, s4, 0x4240 -; GFX10_1-NEXT: v_writelane_b32 v22, s31, 1 -; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0 ; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo +; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0 ; GFX10_1-NEXT: ;;#ASMSTART ; GFX10_1-NEXT: ; use alloca0 v0 ; GFX10_1-NEXT: ;;#ASMEND -; GFX10_1-NEXT: v_writelane_b32 v22, s33, 2 -; GFX10_1-NEXT: v_writelane_b32 v22, s34, 3 -; GFX10_1-NEXT: v_writelane_b32 v22, s35, 4 -; GFX10_1-NEXT: v_writelane_b32 v22, s36, 5 -; GFX10_1-NEXT: v_writelane_b32 v22, s37, 6 -; GFX10_1-NEXT: v_writelane_b32 v22, s38, 7 -; GFX10_1-NEXT: v_writelane_b32 v22, s39, 8 -; GFX10_1-NEXT: v_writelane_b32 v22, s48, 9 -; GFX10_1-NEXT: v_writelane_b32 v22, s49, 10 -; GFX10_1-NEXT: v_writelane_b32 v22, s50, 11 -; GFX10_1-NEXT: v_writelane_b32 v22, s51, 12 -; GFX10_1-NEXT: v_writelane_b32 v22, s52, 13 -; GFX10_1-NEXT: v_writelane_b32 v22, s53, 14 -; GFX10_1-NEXT: v_writelane_b32 v22, s54, 15 -; GFX10_1-NEXT: v_writelane_b32 v22, s55, 16 ; GFX10_1-NEXT: ;;#ASMSTART ; GFX10_1-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc ; GFX10_1-NEXT: ;;#ASMEND @@ -1441,23 +1443,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX10_1-NEXT: ;;#ASMSTART ; GFX10_1-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc ; GFX10_1-NEXT: ;;#ASMEND -; GFX10_1-NEXT: v_readlane_b32 s55, v22, 16 -; GFX10_1-NEXT: v_readlane_b32 s54, v22, 15 -; GFX10_1-NEXT: v_readlane_b32 s53, v22, 14 -; GFX10_1-NEXT: v_readlane_b32 s52, v22, 13 -; GFX10_1-NEXT: v_readlane_b32 s51, v22, 12 -; GFX10_1-NEXT: v_readlane_b32 s50, v22, 11 -; GFX10_1-NEXT: v_readlane_b32 s49, v22, 10 -; GFX10_1-NEXT: v_readlane_b32 s48, v22, 9 -; GFX10_1-NEXT: v_readlane_b32 s39, v22, 8 -; GFX10_1-NEXT: v_readlane_b32 s38, v22, 7 -; GFX10_1-NEXT: v_readlane_b32 s37, v22, 6 -; GFX10_1-NEXT: v_readlane_b32 s36, v22, 5 -; GFX10_1-NEXT: v_readlane_b32 s35, v22, 4 -; GFX10_1-NEXT: v_readlane_b32 s34, v22, 3 -; GFX10_1-NEXT: v_readlane_b32 s33, v22, 2 -; GFX10_1-NEXT: v_readlane_b32 s31, v22, 1 -; GFX10_1-NEXT: v_readlane_b32 s30, v22, 0 +; GFX10_1-NEXT: v_readlane_b32 s30, v22, 15 +; GFX10_1-NEXT: v_readlane_b32 s31, v22, 16 +; GFX10_1-NEXT: v_readlane_b32 s55, v22, 14 +; GFX10_1-NEXT: v_readlane_b32 s54, v22, 13 +; GFX10_1-NEXT: v_readlane_b32 s53, v22, 12 +; GFX10_1-NEXT: v_readlane_b32 s52, v22, 11 +; GFX10_1-NEXT: v_readlane_b32 s51, v22, 10 +; GFX10_1-NEXT: v_readlane_b32 s50, v22, 9 +; GFX10_1-NEXT: v_readlane_b32 s49, v22, 8 +; GFX10_1-NEXT: v_readlane_b32 s48, v22, 7 +; GFX10_1-NEXT: v_readlane_b32 s39, v22, 6 +; GFX10_1-NEXT: v_readlane_b32 s38, v22, 5 +; GFX10_1-NEXT: v_readlane_b32 s37, v22, 4 +; GFX10_1-NEXT: v_readlane_b32 s36, v22, 3 +; GFX10_1-NEXT: v_readlane_b32 s35, v22, 2 +; GFX10_1-NEXT: v_readlane_b32 s34, v22, 1 +; GFX10_1-NEXT: v_readlane_b32 s33, v22, 0 ; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800 ; GFX10_1-NEXT: buffer_load_dword v22, off, s[0:3], s5 ; 4-byte Folded Reload @@ -1473,31 +1475,31 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX10_3-NEXT: s_add_i32 s5, s32, 0x100800 ; GFX10_3-NEXT: buffer_store_dword v22, off, s[0:3], s5 ; 4-byte Folded Spill ; GFX10_3-NEXT: s_mov_b32 exec_lo, s4 -; GFX10_3-NEXT: v_writelane_b32 v22, s30, 0 +; GFX10_3-NEXT: v_writelane_b32 v22, s33, 0 +; GFX10_3-NEXT: v_writelane_b32 v22, s34, 1 +; GFX10_3-NEXT: v_writelane_b32 v22, s35, 2 +; GFX10_3-NEXT: v_writelane_b32 v22, s36, 3 +; GFX10_3-NEXT: v_writelane_b32 v22, s37, 4 +; GFX10_3-NEXT: v_writelane_b32 v22, s38, 5 +; GFX10_3-NEXT: v_writelane_b32 v22, s39, 6 +; GFX10_3-NEXT: v_writelane_b32 v22, s48, 7 +; GFX10_3-NEXT: v_writelane_b32 v22, s49, 8 +; GFX10_3-NEXT: v_writelane_b32 v22, s50, 9 +; GFX10_3-NEXT: v_writelane_b32 v22, s51, 10 +; GFX10_3-NEXT: v_writelane_b32 v22, s52, 11 +; GFX10_3-NEXT: v_writelane_b32 v22, s53, 12 +; GFX10_3-NEXT: v_writelane_b32 v22, s54, 13 +; GFX10_3-NEXT: v_writelane_b32 v22, s55, 14 +; GFX10_3-NEXT: v_writelane_b32 v22, s30, 15 +; GFX10_3-NEXT: v_writelane_b32 v22, s31, 16 ; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32 ; GFX10_3-NEXT: s_lshr_b32 s4, s32, 5 ; GFX10_3-NEXT: s_add_i32 s58, s4, 0x4240 -; GFX10_3-NEXT: v_writelane_b32 v22, s31, 1 -; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0 ; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo +; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0 ; GFX10_3-NEXT: ;;#ASMSTART ; GFX10_3-NEXT: ; use alloca0 v0 ; GFX10_3-NEXT: ;;#ASMEND -; GFX10_3-NEXT: v_writelane_b32 v22, s33, 2 -; GFX10_3-NEXT: v_writelane_b32 v22, s34, 3 -; GFX10_3-NEXT: v_writelane_b32 v22, s35, 4 -; GFX10_3-NEXT: v_writelane_b32 v22, s36, 5 -; GFX10_3-NEXT: v_writelane_b32 v22, s37, 6 -; GFX10_3-NEXT: v_writelane_b32 v22, s38, 7 -; GFX10_3-NEXT: v_writelane_b32 v22, s39, 8 -; GFX10_3-NEXT: v_writelane_b32 v22, s48, 9 -; GFX10_3-NEXT: v_writelane_b32 v22, s49, 10 -; GFX10_3-NEXT: v_writelane_b32 v22, s50, 11 -; GFX10_3-NEXT: v_writelane_b32 v22, s51, 12 -; GFX10_3-NEXT: v_writelane_b32 v22, s52, 13 -; GFX10_3-NEXT: v_writelane_b32 v22, s53, 14 -; GFX10_3-NEXT: v_writelane_b32 v22, s54, 15 -; GFX10_3-NEXT: v_writelane_b32 v22, s55, 16 ; GFX10_3-NEXT: ;;#ASMSTART ; GFX10_3-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc ; GFX10_3-NEXT: ;;#ASMEND @@ -1506,23 +1508,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX10_3-NEXT: ;;#ASMSTART ; GFX10_3-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc ; GFX10_3-NEXT: ;;#ASMEND -; GFX10_3-NEXT: v_readlane_b32 s55, v22, 16 -; GFX10_3-NEXT: v_readlane_b32 s54, v22, 15 -; GFX10_3-NEXT: v_readlane_b32 s53, v22, 14 -; GFX10_3-NEXT: v_readlane_b32 s52, v22, 13 -; GFX10_3-NEXT: v_readlane_b32 s51, v22, 12 -; GFX10_3-NEXT: v_readlane_b32 s50, v22, 11 -; GFX10_3-NEXT: v_readlane_b32 s49, v22, 10 -; GFX10_3-NEXT: v_readlane_b32 s48, v22, 9 -; GFX10_3-NEXT: v_readlane_b32 s39, v22, 8 -; GFX10_3-NEXT: v_readlane_b32 s38, v22, 7 -; GFX10_3-NEXT: v_readlane_b32 s37, v22, 6 -; GFX10_3-NEXT: v_readlane_b32 s36, v22, 5 -; GFX10_3-NEXT: v_readlane_b32 s35, v22, 4 -; GFX10_3-NEXT: v_readlane_b32 s34, v22, 3 -; GFX10_3-NEXT: v_readlane_b32 s33, v22, 2 -; GFX10_3-NEXT: v_readlane_b32 s31, v22, 1 -; GFX10_3-NEXT: v_readlane_b32 s30, v22, 0 +; GFX10_3-NEXT: v_readlane_b32 s30, v22, 15 +; GFX10_3-NEXT: v_readlane_b32 s31, v22, 16 +; GFX10_3-NEXT: v_readlane_b32 s55, v22, 14 +; GFX10_3-NEXT: v_readlane_b32 s54, v22, 13 +; GFX10_3-NEXT: v_readlane_b32 s53, v22, 12 +; GFX10_3-NEXT: v_readlane_b32 s52, v22, 11 +; GFX10_3-NEXT: v_readlane_b32 s51, v22, 10 +; GFX10_3-NEXT: v_readlane_b32 s50, v22, 9 +; GFX10_3-NEXT: v_readlane_b32 s49, v22, 8 +; GFX10_3-NEXT: v_readlane_b32 s48, v22, 7 +; GFX10_3-NEXT: v_readlane_b32 s39, v22, 6 +; GFX10_3-NEXT: v_readlane_b32 s38, v22, 5 +; GFX10_3-NEXT: v_readlane_b32 s37, v22, 4 +; GFX10_3-NEXT: v_readlane_b32 s36, v22, 3 +; GFX10_3-NEXT: v_readlane_b32 s35, v22, 2 +; GFX10_3-NEXT: v_readlane_b32 s34, v22, 1 +; GFX10_3-NEXT: v_readlane_b32 s33, v22, 0 ; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX10_3-NEXT: s_add_i32 s5, s32, 0x100800 ; GFX10_3-NEXT: buffer_load_dword v22, off, s[0:3], s5 ; 4-byte Folded Reload @@ -1537,30 +1539,30 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX11-NEXT: s_add_i32 s1, s32, 0x8040 ; GFX11-NEXT: scratch_store_b32 off, v22, s1 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-NEXT: v_writelane_b32 v22, s30, 0 +; GFX11-NEXT: v_writelane_b32 v22, s33, 0 +; GFX11-NEXT: v_writelane_b32 v22, s34, 1 +; GFX11-NEXT: v_writelane_b32 v22, s35, 2 +; GFX11-NEXT: v_writelane_b32 v22, s36, 3 +; GFX11-NEXT: v_writelane_b32 v22, s37, 4 +; GFX11-NEXT: v_writelane_b32 v22, s38, 5 +; GFX11-NEXT: v_writelane_b32 v22, s39, 6 +; GFX11-NEXT: v_writelane_b32 v22, s48, 7 +; GFX11-NEXT: v_writelane_b32 v22, s49, 8 +; GFX11-NEXT: v_writelane_b32 v22, s50, 9 +; GFX11-NEXT: v_writelane_b32 v22, s51, 10 +; GFX11-NEXT: v_writelane_b32 v22, s52, 11 +; GFX11-NEXT: v_writelane_b32 v22, s53, 12 +; GFX11-NEXT: v_writelane_b32 v22, s54, 13 +; GFX11-NEXT: v_writelane_b32 v22, s55, 14 +; GFX11-NEXT: v_writelane_b32 v22, s30, 15 +; GFX11-NEXT: v_writelane_b32 v22, s31, 16 ; GFX11-NEXT: s_add_i32 s0, s32, 64 ; GFX11-NEXT: s_add_i32 s58, s32, 0x4240 ; GFX11-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-NEXT: s_and_b32 s0, 0, exec_lo -; GFX11-NEXT: v_writelane_b32 v22, s31, 1 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use alloca0 v0 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_writelane_b32 v22, s33, 2 -; GFX11-NEXT: v_writelane_b32 v22, s34, 3 -; GFX11-NEXT: v_writelane_b32 v22, s35, 4 -; GFX11-NEXT: v_writelane_b32 v22, s36, 5 -; GFX11-NEXT: v_writelane_b32 v22, s37, 6 -; GFX11-NEXT: v_writelane_b32 v22, s38, 7 -; GFX11-NEXT: v_writelane_b32 v22, s39, 8 -; GFX11-NEXT: v_writelane_b32 v22, s48, 9 -; GFX11-NEXT: v_writelane_b32 v22, s49, 10 -; GFX11-NEXT: v_writelane_b32 v22, s50, 11 -; GFX11-NEXT: v_writelane_b32 v22, s51, 12 -; GFX11-NEXT: v_writelane_b32 v22, s52, 13 -; GFX11-NEXT: v_writelane_b32 v22, s53, 14 -; GFX11-NEXT: v_writelane_b32 v22, s54, 15 -; GFX11-NEXT: v_writelane_b32 v22, s55, 16 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc ; GFX11-NEXT: ;;#ASMEND @@ -1569,24 +1571,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_readlane_b32 s55, v22, 16 -; GFX11-NEXT: v_readlane_b32 s54, v22, 15 -; GFX11-NEXT: v_readlane_b32 s53, v22, 14 -; GFX11-NEXT: v_readlane_b32 s52, v22, 13 -; GFX11-NEXT: v_readlane_b32 s51, v22, 12 -; GFX11-NEXT: v_readlane_b32 s50, v22, 11 -; GFX11-NEXT: v_readlane_b32 s49, v22, 10 -; GFX11-NEXT: v_readlane_b32 s48, v22, 9 -; GFX11-NEXT: v_readlane_b32 s39, v22, 8 -; GFX11-NEXT: v_readlane_b32 s38, v22, 7 -; GFX11-NEXT: v_readlane_b32 s37, v22, 6 -; GFX11-NEXT: v_readlane_b32 s36, v22, 5 -; GFX11-NEXT: v_readlane_b32 s35, v22, 4 -; GFX11-NEXT: v_readlane_b32 s34, v22, 3 -; GFX11-NEXT: v_readlane_b32 s33, v22, 2 -; GFX11-NEXT: v_readlane_b32 s31, v22, 1 -; GFX11-NEXT: v_readlane_b32 s30, v22, 0 +; GFX11-NEXT: v_readlane_b32 s30, v22, 15 +; GFX11-NEXT: v_readlane_b32 s31, v22, 16 +; GFX11-NEXT: v_readlane_b32 s55, v22, 14 +; GFX11-NEXT: v_readlane_b32 s54, v22, 13 +; GFX11-NEXT: v_readlane_b32 s53, v22, 12 +; GFX11-NEXT: v_readlane_b32 s52, v22, 11 +; GFX11-NEXT: v_readlane_b32 s51, v22, 10 +; GFX11-NEXT: v_readlane_b32 s50, v22, 9 +; GFX11-NEXT: v_readlane_b32 s49, v22, 8 +; GFX11-NEXT: v_readlane_b32 s48, v22, 7 +; GFX11-NEXT: v_readlane_b32 s39, v22, 6 +; GFX11-NEXT: v_readlane_b32 s38, v22, 5 +; GFX11-NEXT: v_readlane_b32 s37, v22, 4 +; GFX11-NEXT: v_readlane_b32 s36, v22, 3 +; GFX11-NEXT: v_readlane_b32 s35, v22, 2 +; GFX11-NEXT: v_readlane_b32 s34, v22, 1 +; GFX11-NEXT: v_readlane_b32 s33, v22, 0 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: s_add_i32 s1, s32, 0x8040 ; GFX11-NEXT: scratch_load_b32 v22, off, s1 ; 4-byte Folded Reload @@ -1605,29 +1606,29 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX12-NEXT: scratch_store_b32 off, v22, s32 offset:32768 ; 4-byte Folded Spill ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: s_mov_b32 exec_lo, s0 -; GFX12-NEXT: v_writelane_b32 v22, s30, 0 +; GFX12-NEXT: v_writelane_b32 v22, s33, 0 +; GFX12-NEXT: v_writelane_b32 v22, s34, 1 +; GFX12-NEXT: v_writelane_b32 v22, s35, 2 +; GFX12-NEXT: v_writelane_b32 v22, s36, 3 +; GFX12-NEXT: v_writelane_b32 v22, s37, 4 +; GFX12-NEXT: v_writelane_b32 v22, s38, 5 +; GFX12-NEXT: v_writelane_b32 v22, s39, 6 +; GFX12-NEXT: v_writelane_b32 v22, s48, 7 +; GFX12-NEXT: v_writelane_b32 v22, s49, 8 +; GFX12-NEXT: v_writelane_b32 v22, s50, 9 +; GFX12-NEXT: v_writelane_b32 v22, s51, 10 +; GFX12-NEXT: v_writelane_b32 v22, s52, 11 +; GFX12-NEXT: v_writelane_b32 v22, s53, 12 +; GFX12-NEXT: v_writelane_b32 v22, s54, 13 +; GFX12-NEXT: v_writelane_b32 v22, s55, 14 +; GFX12-NEXT: v_writelane_b32 v22, s30, 15 +; GFX12-NEXT: v_writelane_b32 v22, s31, 16 ; GFX12-NEXT: s_add_co_i32 s58, s32, 0x4200 ; GFX12-NEXT: v_mov_b32_e32 v0, s32 ; GFX12-NEXT: s_and_b32 s0, 0, exec_lo ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; use alloca0 v0 ; GFX12-NEXT: ;;#ASMEND -; GFX12-NEXT: v_writelane_b32 v22, s31, 1 -; GFX12-NEXT: v_writelane_b32 v22, s33, 2 -; GFX12-NEXT: v_writelane_b32 v22, s34, 3 -; GFX12-NEXT: v_writelane_b32 v22, s35, 4 -; GFX12-NEXT: v_writelane_b32 v22, s36, 5 -; GFX12-NEXT: v_writelane_b32 v22, s37, 6 -; GFX12-NEXT: v_writelane_b32 v22, s38, 7 -; GFX12-NEXT: v_writelane_b32 v22, s39, 8 -; GFX12-NEXT: v_writelane_b32 v22, s48, 9 -; GFX12-NEXT: v_writelane_b32 v22, s49, 10 -; GFX12-NEXT: v_writelane_b32 v22, s50, 11 -; GFX12-NEXT: v_writelane_b32 v22, s51, 12 -; GFX12-NEXT: v_writelane_b32 v22, s52, 13 -; GFX12-NEXT: v_writelane_b32 v22, s53, 14 -; GFX12-NEXT: v_writelane_b32 v22, s54, 15 -; GFX12-NEXT: v_writelane_b32 v22, s55, 16 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc ; GFX12-NEXT: ;;#ASMEND @@ -1637,23 +1638,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc ; GFX12-NEXT: ;;#ASMEND -; GFX12-NEXT: v_readlane_b32 s55, v22, 16 -; GFX12-NEXT: v_readlane_b32 s54, v22, 15 -; GFX12-NEXT: v_readlane_b32 s53, v22, 14 -; GFX12-NEXT: v_readlane_b32 s52, v22, 13 -; GFX12-NEXT: v_readlane_b32 s51, v22, 12 -; GFX12-NEXT: v_readlane_b32 s50, v22, 11 -; GFX12-NEXT: v_readlane_b32 s49, v22, 10 -; GFX12-NEXT: v_readlane_b32 s48, v22, 9 -; GFX12-NEXT: v_readlane_b32 s39, v22, 8 -; GFX12-NEXT: v_readlane_b32 s38, v22, 7 -; GFX12-NEXT: v_readlane_b32 s37, v22, 6 -; GFX12-NEXT: v_readlane_b32 s36, v22, 5 -; GFX12-NEXT: v_readlane_b32 s35, v22, 4 -; GFX12-NEXT: v_readlane_b32 s34, v22, 3 -; GFX12-NEXT: v_readlane_b32 s33, v22, 2 -; GFX12-NEXT: v_readlane_b32 s31, v22, 1 -; GFX12-NEXT: v_readlane_b32 s30, v22, 0 +; GFX12-NEXT: v_readlane_b32 s30, v22, 15 +; GFX12-NEXT: v_readlane_b32 s31, v22, 16 +; GFX12-NEXT: v_readlane_b32 s55, v22, 14 +; GFX12-NEXT: v_readlane_b32 s54, v22, 13 +; GFX12-NEXT: v_readlane_b32 s53, v22, 12 +; GFX12-NEXT: v_readlane_b32 s52, v22, 11 +; GFX12-NEXT: v_readlane_b32 s51, v22, 10 +; GFX12-NEXT: v_readlane_b32 s50, v22, 9 +; GFX12-NEXT: v_readlane_b32 s49, v22, 8 +; GFX12-NEXT: v_readlane_b32 s48, v22, 7 +; GFX12-NEXT: v_readlane_b32 s39, v22, 6 +; GFX12-NEXT: v_readlane_b32 s38, v22, 5 +; GFX12-NEXT: v_readlane_b32 s37, v22, 4 +; GFX12-NEXT: v_readlane_b32 s36, v22, 3 +; GFX12-NEXT: v_readlane_b32 s35, v22, 2 +; GFX12-NEXT: v_readlane_b32 s34, v22, 1 +; GFX12-NEXT: v_readlane_b32 s33, v22, 0 ; GFX12-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX12-NEXT: scratch_load_b32 v22, off, s32 offset:32768 ; 4-byte Folded Reload ; GFX12-NEXT: s_wait_alu 0xfffe diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll index ca16e251d51cf..c5aa8eaef2af3 100644 --- a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll @@ -1,13 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9,GFX950 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-TRUE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-FAKE16 %s define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) { ; GFX7-LABEL: v_maximumnum_bf16: @@ -8941,6 +8941,9 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-LABEL: v_maximumnum_v32bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX8-NEXT: buffer_load_dword v55, off, s[0:3], s32 ; GFX8-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 ; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v30 @@ -8989,13 +8992,10 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 ; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 ; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 -; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 ; GFX8-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 ; GFX8-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 -; GFX8-NEXT: s_waitcnt vmcnt(3) +; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v55 ; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v55 ; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc @@ -9563,6 +9563,9 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-LABEL: v_maximumnum_v32bf16: ; GFX900: ; %bb.0: ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX900-NEXT: buffer_load_dword v55, off, s[0:3], s32 ; GFX900-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 ; GFX900-NEXT: v_lshrrev_b32_e32 v34, 16, v30 @@ -9611,14 +9614,11 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 ; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 ; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 -; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 ; GFX900-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 ; GFX900-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 ; GFX900-NEXT: s_mov_b32 s4, 0x5040100 -; GFX900-NEXT: s_waitcnt vmcnt(3) +; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v55 ; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v55 ; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc @@ -10170,6 +10170,9 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-LABEL: v_maximumnum_v32bf16: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse ; GFX950-NEXT: scratch_load_dword v50, off, s32 ; GFX950-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 ; GFX950-NEXT: v_lshrrev_b32_e32 v34, 16, v30 @@ -10210,21 +10213,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v19 ; GFX950-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34 -; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse ; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 +; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 ; GFX950-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38 -; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse -; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 +; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 +; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 ; GFX950-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 ; GFX950-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 ; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse -; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 -; GFX950-NEXT: s_mov_b32 s0, 0x5040100 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v50 ; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v50 @@ -16223,7 +16223,3 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % } attributes #0 = { "amdgpu-ieee"="false" } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX11: {{.*}} -; GFX12: {{.*}} -; GFX9: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll index 02f39e25cb447..06213ef3e06ea 100644 --- a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll +++ b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll @@ -81,7 +81,6 @@ define void @memcpy_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0) ; ALIGNED-LABEL: memcpy_p0_p0_sz2048: ; ALIGNED: ; %bb.0: ; %entry ; ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; ALIGNED-NEXT: s_mov_b64 s[4:5], 0 ; ALIGNED-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -90,6 +89,7 @@ define void @memcpy_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0) ; ALIGNED-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; ALIGNED-NEXT: s_mov_b64 s[4:5], 0 ; ALIGNED-NEXT: .LBB0_1: ; %load-store-loop ; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1 ; ALIGNED-NEXT: v_add_co_u32 v24, vcc_lo, v2, s4 @@ -837,7 +837,6 @@ define void @memcpy_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1) ; ALIGNED-LABEL: memcpy_p1_p1_sz2048: ; ALIGNED: ; %bb.0: ; %entry ; ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; ALIGNED-NEXT: s_mov_b64 s[4:5], 0 ; ALIGNED-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill @@ -846,6 +845,7 @@ define void @memcpy_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1) ; ALIGNED-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill +; ALIGNED-NEXT: s_mov_b64 s[4:5], 0 ; ALIGNED-NEXT: .LBB1_1: ; %load-store-loop ; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1 ; ALIGNED-NEXT: v_add_co_u32 v24, vcc_lo, v2, s4 @@ -2340,7 +2340,6 @@ define void @memcpy_p5_p5_sz2048(ptr addrspace(5) align 1 %dst, ptr addrspace(5) ; ALIGNED-LABEL: memcpy_p5_p5_sz2048: ; ALIGNED: ; %bb.0: ; %entry ; ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; ALIGNED-NEXT: s_mov_b64 s[4:5], 0 ; ALIGNED-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill @@ -2389,6 +2388,7 @@ define void @memcpy_p5_p5_sz2048(ptr addrspace(5) align 1 %dst, ptr addrspace(5) ; ALIGNED-NEXT: buffer_store_dword v125, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v126, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; ALIGNED-NEXT: buffer_store_dword v127, off, s[0:3], s32 ; 4-byte Folded Spill +; ALIGNED-NEXT: s_mov_b64 s[4:5], 0 ; ALIGNED-NEXT: .LBB3_1: ; %load-store-loop ; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1 ; ALIGNED-NEXT: s_clause 0x34 diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll index 416a601797617..6b80da31fdce7 100644 --- a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll @@ -1,13 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9,GFX950 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-TRUE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-FAKE16 %s define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) { ; GFX7-LABEL: v_minimumnum_bf16: @@ -8980,6 +8980,9 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-LABEL: v_minimumnum_v32bf16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX8-NEXT: buffer_load_dword v55, off, s[0:3], s32 ; GFX8-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 ; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v30 @@ -9029,13 +9032,10 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 ; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 ; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 -; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 ; GFX8-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 ; GFX8-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 -; GFX8-NEXT: s_waitcnt vmcnt(3) +; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v55 ; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v55 ; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc @@ -9603,6 +9603,9 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-LABEL: v_minimumnum_v32bf16: ; GFX900: ; %bb.0: ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX900-NEXT: buffer_load_dword v55, off, s[0:3], s32 ; GFX900-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 ; GFX900-NEXT: v_lshrrev_b32_e32 v34, 16, v30 @@ -9652,13 +9655,10 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v21 ; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v20 ; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v19 -; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 ; GFX900-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 ; GFX900-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 -; GFX900-NEXT: s_waitcnt vmcnt(3) +; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v55 ; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v55 ; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc @@ -10211,6 +10211,9 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-LABEL: v_minimumnum_v32bf16: ; GFX950: ; %bb.0: ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse +; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse ; GFX950-NEXT: scratch_load_dword v50, off, s32 ; GFX950-NEXT: v_and_b32_e32 v31, 0xffff0000, v14 ; GFX950-NEXT: v_lshrrev_b32_e32 v34, 16, v30 @@ -10252,20 +10255,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) { ; GFX950-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v34 ; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v19 -; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 ; GFX950-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc ; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v38 -; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v18 -; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse +; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 +; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 ; GFX950-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc ; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39 ; GFX950-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 ; GFX950-NEXT: v_and_b32_e32 v39, 0xffff0000, v26 ; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v17 -; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse -; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v16 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v50 ; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v50 @@ -16289,7 +16289,3 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> % } attributes #0 = { "amdgpu-ieee"="false" } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX11: {{.*}} -; GFX12: {{.*}} -; GFX9: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll index 05ff5c8bb0b3a..31fb2e4088876 100644 --- a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll +++ b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll @@ -138,7 +138,7 @@ define amdgpu_kernel void @withcall() { ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX10-NEXT: s_endpgm -; + ; G_GFX9-LABEL: withcall: ; G_GFX9: ; %bb.0: ; G_GFX9-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0 diff --git a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll index 33cd598aae9b5..486a08d6ee8cd 100644 --- a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll +++ b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll @@ -194,19 +194,19 @@ define void @slsr1_1(i32 %b.arg, i32 %s.arg) #0 { ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[6:7] ; GFX9-NEXT: v_writelane_b32 v43, s4, 5 -; GFX9-NEXT: v_writelane_b32 v43, s30, 0 -; GFX9-NEXT: v_writelane_b32 v43, s31, 1 ; GFX9-NEXT: s_addk_i32 s32, 0x800 -; GFX9-NEXT: v_writelane_b32 v43, s34, 2 -; GFX9-NEXT: v_writelane_b32 v43, s36, 3 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v43, s34, 0 +; GFX9-NEXT: v_writelane_b32 v43, s36, 1 +; GFX9-NEXT: v_writelane_b32 v43, s37, 2 +; GFX9-NEXT: v_writelane_b32 v43, s30, 3 +; GFX9-NEXT: v_writelane_b32 v43, s31, 4 ; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_add_u32 s4, s4, foo@gotpcrel32@lo+4 ; GFX9-NEXT: s_addc_u32 s5, s5, foo@gotpcrel32@hi+12 -; GFX9-NEXT: v_writelane_b32 v43, s37, 4 ; GFX9-NEXT: s_load_dwordx2 s[36:37], s[4:5], 0x0 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v40, v1 ; GFX9-NEXT: v_mov_b32_e32 v41, v0 ; GFX9-NEXT: v_mul_u32_u24_e32 v0, v41, v40 @@ -224,11 +224,11 @@ define void @slsr1_1(i32 %b.arg, i32 %s.arg) #0 { ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s37, v43, 4 -; GFX9-NEXT: v_readlane_b32 s36, v43, 3 -; GFX9-NEXT: v_readlane_b32 s34, v43, 2 -; GFX9-NEXT: v_readlane_b32 s31, v43, 1 -; GFX9-NEXT: v_readlane_b32 s30, v43, 0 +; GFX9-NEXT: v_readlane_b32 s30, v43, 3 +; GFX9-NEXT: v_readlane_b32 s31, v43, 4 +; GFX9-NEXT: v_readlane_b32 s37, v43, 2 +; GFX9-NEXT: v_readlane_b32 s36, v43, 1 +; GFX9-NEXT: v_readlane_b32 s34, v43, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v43, 5 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/need-fp-from-csr-vgpr-spill.ll b/llvm/test/CodeGen/AMDGPU/need-fp-from-csr-vgpr-spill.ll new file mode 100644 index 0000000000000..4b4b3277b994c --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/need-fp-from-csr-vgpr-spill.ll @@ -0,0 +1,139 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s + +; FP is in CSR range, modified. +define hidden fastcc void @callee_has_fp() #1 { +; CHECK-LABEL: callee_has_fp: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b32 s4, s33 +; CHECK-NEXT: s_mov_b32 s33, s32 +; CHECK-NEXT: s_addk_i32 s32, 0x200 +; CHECK-NEXT: v_mov_b32_e32 v0, 1 +; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_mov_b32 s32, s33 +; CHECK-NEXT: s_mov_b32 s33, s4 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %alloca = alloca i32, addrspace(5) + store volatile i32 1, i32 addrspace(5)* %alloca + ret void +} + +; Has no stack objects, but introduces them due to the CSR spill. We +; see the FP modified in the callee with IPRA. We should not have +; redundant spills of s33 or assert. +define internal fastcc void @csr_vgpr_spill_fp_callee() #0 { +; CHECK-LABEL: csr_vgpr_spill_fp_callee: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b32 s18, s33 +; CHECK-NEXT: s_mov_b32 s33, s32 +; CHECK-NEXT: s_xor_saveexec_b64 s[16:17], -1 +; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; CHECK-NEXT: s_mov_b64 exec, s[16:17] +; CHECK-NEXT: s_addk_i32 s32, 0x400 +; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; CHECK-NEXT: v_writelane_b32 v1, s30, 0 +; CHECK-NEXT: v_writelane_b32 v1, s31, 1 +; CHECK-NEXT: s_getpc_b64 s[16:17] +; CHECK-NEXT: s_add_u32 s16, s16, callee_has_fp@rel32@lo+4 +; CHECK-NEXT: s_addc_u32 s17, s17, callee_has_fp@rel32@hi+12 +; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; clobber csr v40 +; CHECK-NEXT: ;;#ASMEND +; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload +; CHECK-NEXT: v_readlane_b32 s30, v1, 0 +; CHECK-NEXT: v_readlane_b32 s31, v1, 1 +; CHECK-NEXT: s_mov_b32 s32, s33 +; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; CHECK-NEXT: s_mov_b64 exec, s[4:5] +; CHECK-NEXT: s_mov_b32 s33, s18 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +bb: + call fastcc void @callee_has_fp() + call void asm sideeffect "; clobber csr v40", "~{v40}"() + ret void +} + +define amdgpu_kernel void @kernel_call() { +; CHECK-LABEL: kernel_call: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17 +; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0 +; CHECK-NEXT: s_add_u32 s0, s0, s17 +; CHECK-NEXT: s_addc_u32 s1, s1, 0 +; CHECK-NEXT: v_lshlrev_b32_e32 v2, 20, v2 +; CHECK-NEXT: v_lshlrev_b32_e32 v1, 10, v1 +; CHECK-NEXT: s_mov_b32 s13, s15 +; CHECK-NEXT: s_mov_b32 s12, s14 +; CHECK-NEXT: s_getpc_b64 s[18:19] +; CHECK-NEXT: s_add_u32 s18, s18, csr_vgpr_spill_fp_callee@rel32@lo+4 +; CHECK-NEXT: s_addc_u32 s19, s19, csr_vgpr_spill_fp_callee@rel32@hi+12 +; CHECK-NEXT: v_or3_b32 v31, v0, v1, v2 +; CHECK-NEXT: s_mov_b32 s14, s16 +; CHECK-NEXT: s_mov_b32 s32, 0 +; CHECK-NEXT: s_swappc_b64 s[30:31], s[18:19] +; CHECK-NEXT: s_endpgm +bb: + tail call fastcc void @csr_vgpr_spill_fp_callee() + ret void +} + +; Same, except with a tail call. +define internal fastcc void @csr_vgpr_spill_fp_tailcall_callee() #0 { +; CHECK-LABEL: csr_vgpr_spill_fp_tailcall_callee: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_xor_saveexec_b64 s[16:17], -1 +; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; CHECK-NEXT: s_mov_b64 exec, s[16:17] +; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill +; CHECK-NEXT: v_writelane_b32 v1, s33, 0 +; CHECK-NEXT: ;;#ASMSTART +; CHECK-NEXT: ; clobber csr v40 +; CHECK-NEXT: ;;#ASMEND +; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload +; CHECK-NEXT: s_getpc_b64 s[16:17] +; CHECK-NEXT: s_add_u32 s16, s16, callee_has_fp@rel32@lo+4 +; CHECK-NEXT: s_addc_u32 s17, s17, callee_has_fp@rel32@hi+12 +; CHECK-NEXT: v_readlane_b32 s33, v1, 0 +; CHECK-NEXT: s_xor_saveexec_b64 s[18:19], -1 +; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; CHECK-NEXT: s_mov_b64 exec, s[18:19] +; CHECK-NEXT: s_setpc_b64 s[16:17] +bb: + call void asm sideeffect "; clobber csr v40", "~{v40}"() + tail call fastcc void @callee_has_fp() + ret void +} + +define amdgpu_kernel void @kernel_tailcall() { +; CHECK-LABEL: kernel_tailcall: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17 +; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0 +; CHECK-NEXT: s_add_u32 s0, s0, s17 +; CHECK-NEXT: s_addc_u32 s1, s1, 0 +; CHECK-NEXT: v_lshlrev_b32_e32 v2, 20, v2 +; CHECK-NEXT: v_lshlrev_b32_e32 v1, 10, v1 +; CHECK-NEXT: s_mov_b32 s13, s15 +; CHECK-NEXT: s_mov_b32 s12, s14 +; CHECK-NEXT: s_getpc_b64 s[18:19] +; CHECK-NEXT: s_add_u32 s18, s18, csr_vgpr_spill_fp_tailcall_callee@rel32@lo+4 +; CHECK-NEXT: s_addc_u32 s19, s19, csr_vgpr_spill_fp_tailcall_callee@rel32@hi+12 +; CHECK-NEXT: v_or3_b32 v31, v0, v1, v2 +; CHECK-NEXT: s_mov_b32 s14, s16 +; CHECK-NEXT: s_mov_b32 s32, 0 +; CHECK-NEXT: s_swappc_b64 s[30:31], s[18:19] +; CHECK-NEXT: s_endpgm +bb: + tail call fastcc void @csr_vgpr_spill_fp_tailcall_callee() + ret void +} + +attributes #0 = { "frame-pointer"="none" noinline } +attributes #1 = { "frame-pointer"="all" noinline } diff --git a/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll index 65446a036c91b..878302e4865bb 100644 --- a/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll +++ b/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll @@ -47,8 +47,8 @@ define internal fastcc void @csr_vgpr_spill_fp_callee() #0 { ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ; clobber csr v40 ; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: v_readlane_b32 s31, v1, 1 ; CHECK-NEXT: v_readlane_b32 s30, v1, 0 +; CHECK-NEXT: v_readlane_b32 s31, v1, 1 ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1 @@ -190,8 +190,8 @@ define hidden i32 @caller_save_vgpr_spill_fp_tail_call() #0 { ; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21] ; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23] ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] -; CHECK-NEXT: v_readlane_b32 s31, v1, 1 ; CHECK-NEXT: v_readlane_b32 s30, v1, 0 +; CHECK-NEXT: v_readlane_b32 s31, v1, 1 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload @@ -224,8 +224,8 @@ define hidden i32 @caller_save_vgpr_spill_fp() #0 { ; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21] ; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23] ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] -; CHECK-NEXT: v_readlane_b32 s31, v2, 1 ; CHECK-NEXT: v_readlane_b32 s30, v2, 0 +; CHECK-NEXT: v_readlane_b32 s31, v2, 1 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/nested-calls.ll b/llvm/test/CodeGen/AMDGPU/nested-calls.ll index ccaf0ac5377e4..da9463b1329c7 100644 --- a/llvm/test/CodeGen/AMDGPU/nested-calls.ll +++ b/llvm/test/CodeGen/AMDGPU/nested-calls.ll @@ -18,19 +18,19 @@ define void @test_func_call_external_void_func_i32_imm() #0 { ; GCN-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] -; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: v_writelane_b32 v40, s16, 2 +; GCN-NEXT: v_writelane_b32 v40, s30, 0 +; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, external_void_func_i32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, external_void_func_i32@gotpcrel32@hi+12 ; GCN-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 42 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 2 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -52,24 +52,24 @@ define void @test_func_call_external_void_func_i32_imm_stack_use() #0 { ; GCN-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] -; GCN-NEXT: s_addk_i32 s32, 0x1400 ; GCN-NEXT: v_writelane_b32 v40, s16, 2 +; GCN-NEXT: v_writelane_b32 v40, s30, 0 +; GCN-NEXT: s_addk_i32 s32, 0x1400 +; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, external_void_func_i32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, external_void_func_i32@gotpcrel32@hi+12 ; GCN-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 ; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:64 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_mov_b32_e32 v0, 42 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 2 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll index e6243f0e41826..21e56bb286325 100644 --- a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll +++ b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll @@ -12,16 +12,996 @@ define hidden void @_ZL3barv() #0 !dbg !1644 { ; CHECK-NEXT: .cfi_sections .debug_frame ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; CHECK-NEXT: .cfi_undefined 2560 +; CHECK-NEXT: .cfi_undefined 2561 +; CHECK-NEXT: .cfi_undefined 2562 +; CHECK-NEXT: .cfi_undefined 2563 +; CHECK-NEXT: .cfi_undefined 2564 +; CHECK-NEXT: .cfi_undefined 2565 +; CHECK-NEXT: .cfi_undefined 2566 +; CHECK-NEXT: .cfi_undefined 2567 +; CHECK-NEXT: .cfi_undefined 2568 +; CHECK-NEXT: .cfi_undefined 2569 +; CHECK-NEXT: .cfi_undefined 2570 +; CHECK-NEXT: .cfi_undefined 2571 +; CHECK-NEXT: .cfi_undefined 2572 +; CHECK-NEXT: .cfi_undefined 2573 +; CHECK-NEXT: .cfi_undefined 2574 +; CHECK-NEXT: .cfi_undefined 2575 +; CHECK-NEXT: .cfi_undefined 2576 +; CHECK-NEXT: .cfi_undefined 2577 +; CHECK-NEXT: .cfi_undefined 2578 +; CHECK-NEXT: .cfi_undefined 2579 +; CHECK-NEXT: .cfi_undefined 2580 +; CHECK-NEXT: .cfi_undefined 2581 +; CHECK-NEXT: .cfi_undefined 2582 +; CHECK-NEXT: .cfi_undefined 2583 +; CHECK-NEXT: .cfi_undefined 2584 +; CHECK-NEXT: .cfi_undefined 2585 +; CHECK-NEXT: .cfi_undefined 2586 +; CHECK-NEXT: .cfi_undefined 2587 +; CHECK-NEXT: .cfi_undefined 2588 +; CHECK-NEXT: .cfi_undefined 2589 +; CHECK-NEXT: .cfi_undefined 2590 +; CHECK-NEXT: .cfi_undefined 2591 +; CHECK-NEXT: .cfi_undefined 2592 +; CHECK-NEXT: .cfi_undefined 2593 +; CHECK-NEXT: .cfi_undefined 2594 +; CHECK-NEXT: .cfi_undefined 2595 +; CHECK-NEXT: .cfi_undefined 2596 +; CHECK-NEXT: .cfi_undefined 2597 +; CHECK-NEXT: .cfi_undefined 2598 +; CHECK-NEXT: .cfi_undefined 2599 +; CHECK-NEXT: .cfi_undefined 2608 +; CHECK-NEXT: .cfi_undefined 2609 +; CHECK-NEXT: .cfi_undefined 2610 +; CHECK-NEXT: .cfi_undefined 2611 +; CHECK-NEXT: .cfi_undefined 2612 +; CHECK-NEXT: .cfi_undefined 2613 +; CHECK-NEXT: .cfi_undefined 2614 +; CHECK-NEXT: .cfi_undefined 2615 +; CHECK-NEXT: .cfi_undefined 2624 +; CHECK-NEXT: .cfi_undefined 2625 +; CHECK-NEXT: .cfi_undefined 2626 +; CHECK-NEXT: .cfi_undefined 2627 +; CHECK-NEXT: .cfi_undefined 2628 +; CHECK-NEXT: .cfi_undefined 2629 +; CHECK-NEXT: .cfi_undefined 2630 +; CHECK-NEXT: .cfi_undefined 2631 +; CHECK-NEXT: .cfi_undefined 2640 +; CHECK-NEXT: .cfi_undefined 2641 +; CHECK-NEXT: .cfi_undefined 2642 +; CHECK-NEXT: .cfi_undefined 2643 +; CHECK-NEXT: .cfi_undefined 2644 +; CHECK-NEXT: .cfi_undefined 2645 +; CHECK-NEXT: .cfi_undefined 2646 +; CHECK-NEXT: .cfi_undefined 2647 +; CHECK-NEXT: .cfi_undefined 2656 +; CHECK-NEXT: .cfi_undefined 2657 +; CHECK-NEXT: .cfi_undefined 2658 +; CHECK-NEXT: .cfi_undefined 2659 +; CHECK-NEXT: .cfi_undefined 2660 +; CHECK-NEXT: .cfi_undefined 2661 +; CHECK-NEXT: .cfi_undefined 2662 +; CHECK-NEXT: .cfi_undefined 2663 +; CHECK-NEXT: .cfi_undefined 2672 +; CHECK-NEXT: .cfi_undefined 2673 +; CHECK-NEXT: .cfi_undefined 2674 +; CHECK-NEXT: .cfi_undefined 2675 +; CHECK-NEXT: .cfi_undefined 2676 +; CHECK-NEXT: .cfi_undefined 2677 +; CHECK-NEXT: .cfi_undefined 2678 +; CHECK-NEXT: .cfi_undefined 2679 +; CHECK-NEXT: .cfi_undefined 2688 +; CHECK-NEXT: .cfi_undefined 2689 +; CHECK-NEXT: .cfi_undefined 2690 +; CHECK-NEXT: .cfi_undefined 2691 +; CHECK-NEXT: .cfi_undefined 2692 +; CHECK-NEXT: .cfi_undefined 2693 +; CHECK-NEXT: .cfi_undefined 2694 +; CHECK-NEXT: .cfi_undefined 2695 +; CHECK-NEXT: .cfi_undefined 2704 +; CHECK-NEXT: .cfi_undefined 2705 +; CHECK-NEXT: .cfi_undefined 2706 +; CHECK-NEXT: .cfi_undefined 2707 +; CHECK-NEXT: .cfi_undefined 2708 +; CHECK-NEXT: .cfi_undefined 2709 +; CHECK-NEXT: .cfi_undefined 2710 +; CHECK-NEXT: .cfi_undefined 2711 +; CHECK-NEXT: .cfi_undefined 2720 +; CHECK-NEXT: .cfi_undefined 2721 +; CHECK-NEXT: .cfi_undefined 2722 +; CHECK-NEXT: .cfi_undefined 2723 +; CHECK-NEXT: .cfi_undefined 2724 +; CHECK-NEXT: .cfi_undefined 2725 +; CHECK-NEXT: .cfi_undefined 2726 +; CHECK-NEXT: .cfi_undefined 2727 +; CHECK-NEXT: .cfi_undefined 2736 +; CHECK-NEXT: .cfi_undefined 2737 +; CHECK-NEXT: .cfi_undefined 2738 +; CHECK-NEXT: .cfi_undefined 2739 +; CHECK-NEXT: .cfi_undefined 2740 +; CHECK-NEXT: .cfi_undefined 2741 +; CHECK-NEXT: .cfi_undefined 2742 +; CHECK-NEXT: .cfi_undefined 2743 +; CHECK-NEXT: .cfi_undefined 2752 +; CHECK-NEXT: .cfi_undefined 2753 +; CHECK-NEXT: .cfi_undefined 2754 +; CHECK-NEXT: .cfi_undefined 2755 +; CHECK-NEXT: .cfi_undefined 2756 +; CHECK-NEXT: .cfi_undefined 2757 +; CHECK-NEXT: .cfi_undefined 2758 +; CHECK-NEXT: .cfi_undefined 2759 +; CHECK-NEXT: .cfi_undefined 2768 +; CHECK-NEXT: .cfi_undefined 2769 +; CHECK-NEXT: .cfi_undefined 2770 +; CHECK-NEXT: .cfi_undefined 2771 +; CHECK-NEXT: .cfi_undefined 2772 +; CHECK-NEXT: .cfi_undefined 2773 +; CHECK-NEXT: .cfi_undefined 2774 +; CHECK-NEXT: .cfi_undefined 2775 +; CHECK-NEXT: .cfi_undefined 2784 +; CHECK-NEXT: .cfi_undefined 2785 +; CHECK-NEXT: .cfi_undefined 2786 +; CHECK-NEXT: .cfi_undefined 2787 +; CHECK-NEXT: .cfi_undefined 2788 +; CHECK-NEXT: .cfi_undefined 2789 +; CHECK-NEXT: .cfi_undefined 2790 +; CHECK-NEXT: .cfi_undefined 2791 +; CHECK-NEXT: .cfi_undefined 2800 +; CHECK-NEXT: .cfi_undefined 2801 +; CHECK-NEXT: .cfi_undefined 2802 +; CHECK-NEXT: .cfi_undefined 2803 +; CHECK-NEXT: .cfi_undefined 2804 +; CHECK-NEXT: .cfi_undefined 2805 +; CHECK-NEXT: .cfi_undefined 2806 +; CHECK-NEXT: .cfi_undefined 2807 +; CHECK-NEXT: .cfi_undefined 2816 +; CHECK-NEXT: .cfi_undefined 2817 +; CHECK-NEXT: .cfi_undefined 2818 +; CHECK-NEXT: .cfi_undefined 2819 +; CHECK-NEXT: .cfi_undefined 2820 +; CHECK-NEXT: .cfi_undefined 2821 +; CHECK-NEXT: .cfi_undefined 2822 +; CHECK-NEXT: .cfi_undefined 2823 +; CHECK-NEXT: .cfi_undefined 2824 +; CHECK-NEXT: .cfi_undefined 2825 +; CHECK-NEXT: .cfi_undefined 2826 +; CHECK-NEXT: .cfi_undefined 2827 +; CHECK-NEXT: .cfi_undefined 2828 +; CHECK-NEXT: .cfi_undefined 2829 +; CHECK-NEXT: .cfi_undefined 2830 +; CHECK-NEXT: .cfi_undefined 2831 +; CHECK-NEXT: .cfi_undefined 2832 +; CHECK-NEXT: .cfi_undefined 2833 +; CHECK-NEXT: .cfi_undefined 2834 +; CHECK-NEXT: .cfi_undefined 2835 +; CHECK-NEXT: .cfi_undefined 2836 +; CHECK-NEXT: .cfi_undefined 2837 +; CHECK-NEXT: .cfi_undefined 2838 +; CHECK-NEXT: .cfi_undefined 2839 +; CHECK-NEXT: .cfi_undefined 2840 +; CHECK-NEXT: .cfi_undefined 2841 +; CHECK-NEXT: .cfi_undefined 2842 +; CHECK-NEXT: .cfi_undefined 2843 +; CHECK-NEXT: .cfi_undefined 2844 +; CHECK-NEXT: .cfi_undefined 2845 +; CHECK-NEXT: .cfi_undefined 2846 +; CHECK-NEXT: .cfi_undefined 2847 +; CHECK-NEXT: .cfi_undefined 2848 +; CHECK-NEXT: .cfi_undefined 2849 +; CHECK-NEXT: .cfi_undefined 2850 +; CHECK-NEXT: .cfi_undefined 2851 +; CHECK-NEXT: .cfi_undefined 2852 +; CHECK-NEXT: .cfi_undefined 2853 +; CHECK-NEXT: .cfi_undefined 2854 +; CHECK-NEXT: .cfi_undefined 2855 +; CHECK-NEXT: .cfi_undefined 2856 +; CHECK-NEXT: .cfi_undefined 2857 +; CHECK-NEXT: .cfi_undefined 2858 +; CHECK-NEXT: .cfi_undefined 2859 +; CHECK-NEXT: .cfi_undefined 2860 +; CHECK-NEXT: .cfi_undefined 2861 +; CHECK-NEXT: .cfi_undefined 2862 +; CHECK-NEXT: .cfi_undefined 2863 +; CHECK-NEXT: .cfi_undefined 2864 +; CHECK-NEXT: .cfi_undefined 2865 +; CHECK-NEXT: .cfi_undefined 2866 +; CHECK-NEXT: .cfi_undefined 2867 +; CHECK-NEXT: .cfi_undefined 2868 +; CHECK-NEXT: .cfi_undefined 2869 +; CHECK-NEXT: .cfi_undefined 2870 +; CHECK-NEXT: .cfi_undefined 2871 +; CHECK-NEXT: .cfi_undefined 2872 +; CHECK-NEXT: .cfi_undefined 2873 +; CHECK-NEXT: .cfi_undefined 2874 +; CHECK-NEXT: .cfi_undefined 2875 +; CHECK-NEXT: .cfi_undefined 2876 +; CHECK-NEXT: .cfi_undefined 2877 +; CHECK-NEXT: .cfi_undefined 2878 +; CHECK-NEXT: .cfi_undefined 2879 +; CHECK-NEXT: .cfi_undefined 2880 +; CHECK-NEXT: .cfi_undefined 2881 +; CHECK-NEXT: .cfi_undefined 2882 +; CHECK-NEXT: .cfi_undefined 2883 +; CHECK-NEXT: .cfi_undefined 2884 +; CHECK-NEXT: .cfi_undefined 2885 +; CHECK-NEXT: .cfi_undefined 2886 +; CHECK-NEXT: .cfi_undefined 2887 +; CHECK-NEXT: .cfi_undefined 2888 +; CHECK-NEXT: .cfi_undefined 2889 +; CHECK-NEXT: .cfi_undefined 2890 +; CHECK-NEXT: .cfi_undefined 2891 +; CHECK-NEXT: .cfi_undefined 2892 +; CHECK-NEXT: .cfi_undefined 2893 +; CHECK-NEXT: .cfi_undefined 2894 +; CHECK-NEXT: .cfi_undefined 2895 +; CHECK-NEXT: .cfi_undefined 2896 +; CHECK-NEXT: .cfi_undefined 2897 +; CHECK-NEXT: .cfi_undefined 2898 +; CHECK-NEXT: .cfi_undefined 2899 +; CHECK-NEXT: .cfi_undefined 2900 +; CHECK-NEXT: .cfi_undefined 2901 +; CHECK-NEXT: .cfi_undefined 2902 +; CHECK-NEXT: .cfi_undefined 2903 +; CHECK-NEXT: .cfi_undefined 2904 +; CHECK-NEXT: .cfi_undefined 2905 +; CHECK-NEXT: .cfi_undefined 2906 +; CHECK-NEXT: .cfi_undefined 2907 +; CHECK-NEXT: .cfi_undefined 2908 +; CHECK-NEXT: .cfi_undefined 2909 +; CHECK-NEXT: .cfi_undefined 2910 +; CHECK-NEXT: .cfi_undefined 2911 +; CHECK-NEXT: .cfi_undefined 2912 +; CHECK-NEXT: .cfi_undefined 2913 +; CHECK-NEXT: .cfi_undefined 2914 +; CHECK-NEXT: .cfi_undefined 2915 +; CHECK-NEXT: .cfi_undefined 2916 +; CHECK-NEXT: .cfi_undefined 2917 +; CHECK-NEXT: .cfi_undefined 2918 +; CHECK-NEXT: .cfi_undefined 2919 +; CHECK-NEXT: .cfi_undefined 2920 +; CHECK-NEXT: .cfi_undefined 2921 +; CHECK-NEXT: .cfi_undefined 2922 +; CHECK-NEXT: .cfi_undefined 2923 +; CHECK-NEXT: .cfi_undefined 2924 +; CHECK-NEXT: .cfi_undefined 2925 +; CHECK-NEXT: .cfi_undefined 2926 +; CHECK-NEXT: .cfi_undefined 2927 +; CHECK-NEXT: .cfi_undefined 2928 +; CHECK-NEXT: .cfi_undefined 2929 +; CHECK-NEXT: .cfi_undefined 2930 +; CHECK-NEXT: .cfi_undefined 2931 +; CHECK-NEXT: .cfi_undefined 2932 +; CHECK-NEXT: .cfi_undefined 2933 +; CHECK-NEXT: .cfi_undefined 2934 +; CHECK-NEXT: .cfi_undefined 2935 +; CHECK-NEXT: .cfi_undefined 2936 +; CHECK-NEXT: .cfi_undefined 2937 +; CHECK-NEXT: .cfi_undefined 2938 +; CHECK-NEXT: .cfi_undefined 2939 +; CHECK-NEXT: .cfi_undefined 2940 +; CHECK-NEXT: .cfi_undefined 2941 +; CHECK-NEXT: .cfi_undefined 2942 +; CHECK-NEXT: .cfi_undefined 2943 +; CHECK-NEXT: .cfi_undefined 2944 +; CHECK-NEXT: .cfi_undefined 2945 +; CHECK-NEXT: .cfi_undefined 2946 +; CHECK-NEXT: .cfi_undefined 2947 +; CHECK-NEXT: .cfi_undefined 2948 +; CHECK-NEXT: .cfi_undefined 2949 +; CHECK-NEXT: .cfi_undefined 2950 +; CHECK-NEXT: .cfi_undefined 2951 +; CHECK-NEXT: .cfi_undefined 2952 +; CHECK-NEXT: .cfi_undefined 2953 +; CHECK-NEXT: .cfi_undefined 2954 +; CHECK-NEXT: .cfi_undefined 2955 +; CHECK-NEXT: .cfi_undefined 2956 +; CHECK-NEXT: .cfi_undefined 2957 +; CHECK-NEXT: .cfi_undefined 2958 +; CHECK-NEXT: .cfi_undefined 2959 +; CHECK-NEXT: .cfi_undefined 2960 +; CHECK-NEXT: .cfi_undefined 2961 +; CHECK-NEXT: .cfi_undefined 2962 +; CHECK-NEXT: .cfi_undefined 2963 +; CHECK-NEXT: .cfi_undefined 2964 +; CHECK-NEXT: .cfi_undefined 2965 +; CHECK-NEXT: .cfi_undefined 2966 +; CHECK-NEXT: .cfi_undefined 2967 +; CHECK-NEXT: .cfi_undefined 2968 +; CHECK-NEXT: .cfi_undefined 2969 +; CHECK-NEXT: .cfi_undefined 2970 +; CHECK-NEXT: .cfi_undefined 2971 +; CHECK-NEXT: .cfi_undefined 2972 +; CHECK-NEXT: .cfi_undefined 2973 +; CHECK-NEXT: .cfi_undefined 2974 +; CHECK-NEXT: .cfi_undefined 2975 +; CHECK-NEXT: .cfi_undefined 2976 +; CHECK-NEXT: .cfi_undefined 2977 +; CHECK-NEXT: .cfi_undefined 2978 +; CHECK-NEXT: .cfi_undefined 2979 +; CHECK-NEXT: .cfi_undefined 2980 +; CHECK-NEXT: .cfi_undefined 2981 +; CHECK-NEXT: .cfi_undefined 2982 +; CHECK-NEXT: .cfi_undefined 2983 +; CHECK-NEXT: .cfi_undefined 2984 +; CHECK-NEXT: .cfi_undefined 2985 +; CHECK-NEXT: .cfi_undefined 2986 +; CHECK-NEXT: .cfi_undefined 2987 +; CHECK-NEXT: .cfi_undefined 2988 +; CHECK-NEXT: .cfi_undefined 2989 +; CHECK-NEXT: .cfi_undefined 2990 +; CHECK-NEXT: .cfi_undefined 2991 +; CHECK-NEXT: .cfi_undefined 2992 +; CHECK-NEXT: .cfi_undefined 2993 +; CHECK-NEXT: .cfi_undefined 2994 +; CHECK-NEXT: .cfi_undefined 2995 +; CHECK-NEXT: .cfi_undefined 2996 +; CHECK-NEXT: .cfi_undefined 2997 +; CHECK-NEXT: .cfi_undefined 2998 +; CHECK-NEXT: .cfi_undefined 2999 +; CHECK-NEXT: .cfi_undefined 3000 +; CHECK-NEXT: .cfi_undefined 3001 +; CHECK-NEXT: .cfi_undefined 3002 +; CHECK-NEXT: .cfi_undefined 3003 +; CHECK-NEXT: .cfi_undefined 3004 +; CHECK-NEXT: .cfi_undefined 3005 +; CHECK-NEXT: .cfi_undefined 3006 +; CHECK-NEXT: .cfi_undefined 3007 +; CHECK-NEXT: .cfi_undefined 3008 +; CHECK-NEXT: .cfi_undefined 3009 +; CHECK-NEXT: .cfi_undefined 3010 +; CHECK-NEXT: .cfi_undefined 3011 +; CHECK-NEXT: .cfi_undefined 3012 +; CHECK-NEXT: .cfi_undefined 3013 +; CHECK-NEXT: .cfi_undefined 3014 +; CHECK-NEXT: .cfi_undefined 3015 +; CHECK-NEXT: .cfi_undefined 3016 +; CHECK-NEXT: .cfi_undefined 3017 +; CHECK-NEXT: .cfi_undefined 3018 +; CHECK-NEXT: .cfi_undefined 3019 +; CHECK-NEXT: .cfi_undefined 3020 +; CHECK-NEXT: .cfi_undefined 3021 +; CHECK-NEXT: .cfi_undefined 3022 +; CHECK-NEXT: .cfi_undefined 3023 +; CHECK-NEXT: .cfi_undefined 3024 +; CHECK-NEXT: .cfi_undefined 3025 +; CHECK-NEXT: .cfi_undefined 3026 +; CHECK-NEXT: .cfi_undefined 3027 +; CHECK-NEXT: .cfi_undefined 3028 +; CHECK-NEXT: .cfi_undefined 3029 +; CHECK-NEXT: .cfi_undefined 3030 +; CHECK-NEXT: .cfi_undefined 3031 +; CHECK-NEXT: .cfi_undefined 3032 +; CHECK-NEXT: .cfi_undefined 3033 +; CHECK-NEXT: .cfi_undefined 3034 +; CHECK-NEXT: .cfi_undefined 3035 +; CHECK-NEXT: .cfi_undefined 3036 +; CHECK-NEXT: .cfi_undefined 3037 +; CHECK-NEXT: .cfi_undefined 3038 +; CHECK-NEXT: .cfi_undefined 3039 +; CHECK-NEXT: .cfi_undefined 3040 +; CHECK-NEXT: .cfi_undefined 3041 +; CHECK-NEXT: .cfi_undefined 3042 +; CHECK-NEXT: .cfi_undefined 3043 +; CHECK-NEXT: .cfi_undefined 3044 +; CHECK-NEXT: .cfi_undefined 3045 +; CHECK-NEXT: .cfi_undefined 3046 +; CHECK-NEXT: .cfi_undefined 3047 +; CHECK-NEXT: .cfi_undefined 3048 +; CHECK-NEXT: .cfi_undefined 3049 +; CHECK-NEXT: .cfi_undefined 3050 +; CHECK-NEXT: .cfi_undefined 3051 +; CHECK-NEXT: .cfi_undefined 3052 +; CHECK-NEXT: .cfi_undefined 3053 +; CHECK-NEXT: .cfi_undefined 3054 +; CHECK-NEXT: .cfi_undefined 3055 +; CHECK-NEXT: .cfi_undefined 3056 +; CHECK-NEXT: .cfi_undefined 3057 +; CHECK-NEXT: .cfi_undefined 3058 +; CHECK-NEXT: .cfi_undefined 3059 +; CHECK-NEXT: .cfi_undefined 3060 +; CHECK-NEXT: .cfi_undefined 3061 +; CHECK-NEXT: .cfi_undefined 3062 +; CHECK-NEXT: .cfi_undefined 3063 +; CHECK-NEXT: .cfi_undefined 3064 +; CHECK-NEXT: .cfi_undefined 3065 +; CHECK-NEXT: .cfi_undefined 3066 +; CHECK-NEXT: .cfi_undefined 3067 +; CHECK-NEXT: .cfi_undefined 3068 +; CHECK-NEXT: .cfi_undefined 3069 +; CHECK-NEXT: .cfi_undefined 3070 +; CHECK-NEXT: .cfi_undefined 3071 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 4294967295 +; CHECK-NEXT: .cfi_undefined 32 +; CHECK-NEXT: .cfi_undefined 33 +; CHECK-NEXT: .cfi_undefined 34 +; CHECK-NEXT: .cfi_undefined 35 +; CHECK-NEXT: .cfi_undefined 36 +; CHECK-NEXT: .cfi_undefined 37 +; CHECK-NEXT: .cfi_undefined 38 +; CHECK-NEXT: .cfi_undefined 39 +; CHECK-NEXT: .cfi_undefined 40 +; CHECK-NEXT: .cfi_undefined 41 +; CHECK-NEXT: .cfi_undefined 42 +; CHECK-NEXT: .cfi_undefined 43 +; CHECK-NEXT: .cfi_undefined 44 +; CHECK-NEXT: .cfi_undefined 45 +; CHECK-NEXT: .cfi_undefined 46 +; CHECK-NEXT: .cfi_undefined 47 +; CHECK-NEXT: .cfi_undefined 48 +; CHECK-NEXT: .cfi_undefined 49 +; CHECK-NEXT: .cfi_undefined 50 +; CHECK-NEXT: .cfi_undefined 51 +; CHECK-NEXT: .cfi_undefined 52 +; CHECK-NEXT: .cfi_undefined 53 +; CHECK-NEXT: .cfi_undefined 54 +; CHECK-NEXT: .cfi_undefined 55 +; CHECK-NEXT: .cfi_undefined 56 +; CHECK-NEXT: .cfi_undefined 57 +; CHECK-NEXT: .cfi_undefined 58 +; CHECK-NEXT: .cfi_undefined 59 +; CHECK-NEXT: .cfi_undefined 60 +; CHECK-NEXT: .cfi_undefined 61 +; CHECK-NEXT: .cfi_undefined 72 +; CHECK-NEXT: .cfi_undefined 73 +; CHECK-NEXT: .cfi_undefined 74 +; CHECK-NEXT: .cfi_undefined 75 +; CHECK-NEXT: .cfi_undefined 76 +; CHECK-NEXT: .cfi_undefined 77 +; CHECK-NEXT: .cfi_undefined 78 +; CHECK-NEXT: .cfi_undefined 79 +; CHECK-NEXT: .cfi_undefined 88 +; CHECK-NEXT: .cfi_undefined 89 +; CHECK-NEXT: .cfi_undefined 90 +; CHECK-NEXT: .cfi_undefined 91 +; CHECK-NEXT: .cfi_undefined 92 +; CHECK-NEXT: .cfi_undefined 93 +; CHECK-NEXT: .cfi_undefined 94 +; CHECK-NEXT: .cfi_undefined 95 +; CHECK-NEXT: .cfi_undefined 1096 +; CHECK-NEXT: .cfi_undefined 1097 +; CHECK-NEXT: .cfi_undefined 1098 +; CHECK-NEXT: .cfi_undefined 1099 +; CHECK-NEXT: .cfi_undefined 1100 +; CHECK-NEXT: .cfi_undefined 1101 +; CHECK-NEXT: .cfi_undefined 1102 +; CHECK-NEXT: .cfi_undefined 1103 +; CHECK-NEXT: .cfi_undefined 1112 +; CHECK-NEXT: .cfi_undefined 1113 +; CHECK-NEXT: .cfi_undefined 1114 +; CHECK-NEXT: .cfi_undefined 1115 +; CHECK-NEXT: .cfi_undefined 1116 +; CHECK-NEXT: .cfi_undefined 1117 +; CHECK-NEXT: .cfi_undefined 1118 +; CHECK-NEXT: .cfi_undefined 1119 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_mov_b32 s16, s33 ; CHECK-NEXT: s_mov_b32 s33, s32 ; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1 ; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset 2600, 0 ; CHECK-NEXT: s_mov_b64 exec, s[18:19] ; CHECK-NEXT: v_writelane_b32 v40, s16, 2 +; CHECK-NEXT: .cfi_llvm_vector_registers 65, 2600, 2, 32 +; CHECK-NEXT: .cfi_def_cfa_register 65 ; CHECK-NEXT: s_add_i32 s32, s32, 0x400 ; CHECK-NEXT: v_writelane_b32 v40, s30, 0 ; CHECK-NEXT: v_writelane_b32 v40, s31, 1 +; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32 ; CHECK-NEXT: .Ltmp0: ; CHECK-NEXT: .loc 0 31 3 prologue_end ; lane-info.cpp:31:3 ; CHECK-NEXT: s_getpc_b64 s[16:17] @@ -36,13 +1016,14 @@ define hidden void @_ZL3barv() #0 !dbg !1644 { ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] ; CHECK-NEXT: .Ltmp1: ; CHECK-NEXT: .loc 0 32 1 ; lane-info.cpp:32:1 -; CHECK-NEXT: v_readlane_b32 s31, v40, 1 ; CHECK-NEXT: v_readlane_b32 s30, v40, 0 +; CHECK-NEXT: v_readlane_b32 s31, v40, 1 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: v_readlane_b32 s4, v40, 2 ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1 ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: s_mov_b64 exec, s[6:7] +; CHECK-NEXT: .cfi_def_cfa_register 64 ; CHECK-NEXT: s_mov_b32 s33, s4 ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll index 627f4ada95dba..bac460949d579 100644 --- a/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll +++ b/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll @@ -219,8 +219,8 @@ define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i3 ; MUBUF: ; %bb.0: ; %entry ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MUBUF-NEXT: s_mov_b32 s7, s33 -; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; MUBUF-NEXT: s_mov_b32 s33, s32 +; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; MUBUF-NEXT: s_addk_i32 s32, 0x400 ; MUBUF-NEXT: s_and_saveexec_b64 s[4:5], vcc ; MUBUF-NEXT: s_cbranch_execz .LBB2_3 @@ -254,8 +254,8 @@ define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i3 ; FLATSCR: ; %bb.0: ; %entry ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s3, s33 -; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; FLATSCR-NEXT: s_mov_b32 s33, s32 +; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; FLATSCR-NEXT: s_add_i32 s32, s32, 16 ; FLATSCR-NEXT: s_and_saveexec_b64 s[0:1], vcc ; FLATSCR-NEXT: s_cbranch_execz .LBB2_3 @@ -317,9 +317,9 @@ define void @func_non_entry_block_static_alloca_align64(ptr addrspace(1) %out, i ; MUBUF-NEXT: s_mov_b32 s7, s33 ; MUBUF-NEXT: s_add_i32 s33, s32, 0xfc0 ; MUBUF-NEXT: s_mov_b32 s8, s34 -; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; MUBUF-NEXT: s_and_b32 s33, s33, 0xfffff000 ; MUBUF-NEXT: s_mov_b32 s34, s32 +; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; MUBUF-NEXT: s_addk_i32 s32, 0x2000 ; MUBUF-NEXT: s_and_saveexec_b64 s[4:5], vcc ; MUBUF-NEXT: s_cbranch_execz .LBB3_2 @@ -354,9 +354,9 @@ define void @func_non_entry_block_static_alloca_align64(ptr addrspace(1) %out, i ; FLATSCR-NEXT: s_mov_b32 s3, s33 ; FLATSCR-NEXT: s_add_i32 s33, s32, 63 ; FLATSCR-NEXT: s_mov_b32 s4, s34 -; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; FLATSCR-NEXT: s_andn2_b32 s33, s33, 63 ; FLATSCR-NEXT: s_mov_b32 s34, s32 +; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; FLATSCR-NEXT: s_addk_i32 s32, 0x80 ; FLATSCR-NEXT: s_and_saveexec_b64 s[0:1], vcc ; FLATSCR-NEXT: s_cbranch_execz .LBB3_2 diff --git a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll index 2aae26b9470a8..34dd69f966637 100644 --- a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll @@ -33,6 +33,8 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 { ; PEI-GFX908: bb.0 (%ir-block.0): ; PEI-GFX908-NEXT: liveins: $agpr4, $sgpr4_sgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9 ; PEI-GFX908-NEXT: {{ $}} + ; PEI-GFX908-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; PEI-GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; PEI-GFX908-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3 ; PEI-GFX908-NEXT: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15 ; PEI-GFX908-NEXT: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15 @@ -79,6 +81,8 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 { ; PEI-GFX90A: bb.0 (%ir-block.0): ; PEI-GFX90A-NEXT: liveins: $sgpr4_sgpr5 ; PEI-GFX90A-NEXT: {{ $}} + ; PEI-GFX90A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; PEI-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; PEI-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:AGPR_32 */, undef renamable $agpr0 ; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7929866 /* regdef:VReg_128_Align2 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3 ; PEI-GFX90A-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = COPY killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir index bb248fe0444db..99376b04b8ecf 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir @@ -36,7 +36,884 @@ body: | ; GCN-LABEL: name: preserve_active_lanes_above_args ; GCN: liveins: $sgpr0, $vgpr8, $vgpr9, $vgpr10 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: SCRATCH_STORE_DWORD_ST killed $vgpr10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr10, 32, $exec_lo, 32, 0 ; GCN-NEXT: renamable $vgpr10 = V_MOV_B32_e32 10, implicit $exec ; GCN-NEXT: $vgpr8 = COPY killed renamable $vgpr10 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc @@ -69,8 +946,893 @@ body: | ; GCN-LABEL: name: preserve_all_lanes_wwm_above_args ; GCN: liveins: $sgpr0, $sgpr35, $vgpr8, $vgpr9, $vgpr10 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: $sgpr1 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr10, 0 ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: $vgpr10 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr10 @@ -112,6 +1874,890 @@ body: | ; GCN-LABEL: name: dont_preserve_args ; GCN: liveins: $sgpr0, $vgpr8, $vgpr9 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: renamable $vgpr8 = V_MOV_B32_e32 10, implicit $exec ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc @@ -143,8 +2789,893 @@ body: | ; GCN-LABEL: name: preserve_inactive_lanes_wwm_args ; GCN: liveins: $sgpr0, $sgpr35, $vgpr8, $vgpr9, $vgpr10 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: $sgpr1 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr9, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr9, 0 ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: $vgpr8 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr8 @@ -186,6 +3717,17 @@ body: | ; GCN-LABEL: name: dont_preserve_if_no_chain_calls ; GCN: liveins: $sgpr0, $sgpr35, $vgpr0, $vgpr8, $vgpr9 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: $vgpr8 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr8 ; GCN-NEXT: $sgpr35 = S_MOV_B32 5 @@ -222,6 +3764,884 @@ body: | ; GCN-LABEL: name: dont_preserve_v0_v7 ; GCN: liveins: $sgpr0, $sgpr35, $vgpr0, $vgpr8 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr0 ; GCN-NEXT: $sgpr35 = S_MOV_B32 5 ; GCN-NEXT: $sgpr35 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0 @@ -260,6 +4680,882 @@ body: | ; GCN-LABEL: name: dont_preserve_sgpr ; GCN: liveins: $sgpr0 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: renamable $sgpr1 = S_ADD_I32 killed renamable $sgpr0, renamable $sgpr0, implicit-def dead $scc ; GCN-NEXT: $sgpr0 = COPY killed renamable $sgpr1 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc diff --git a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir index 4aea915936ffc..8cf65cd13419c 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir @@ -37,9 +37,895 @@ body: | ; GCN-LABEL: name: preserve_inactive_wwm ; GCN: liveins: $sgpr0, $sgpr35, $vgpr8, $vgpr9 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: $sgpr1 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr8, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr8, 0 ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr9, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr9, 128 ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc ; GCN-NEXT: renamable $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4) @@ -73,6 +959,18 @@ body: | ; GCN-LABEL: name: dont_preserve_wwm_if_no_chain_calls ; GCN: liveins: $sgpr35, $vgpr8 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 ; GCN-NEXT: $vgpr8 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr8 ; GCN-NEXT: $sgpr35 = S_MOV_B32 5 ; GCN-NEXT: $sgpr35 = SI_RESTORE_S32_FROM_VGPR $vgpr8, 0 @@ -106,6 +1004,882 @@ body: | ; GCN-LABEL: name: dont_preserve_wwm_if_init_whole_wave ; GCN: liveins: $sgpr0, $sgpr35 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc ; GCN-NEXT: renamable $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4) ; GCN-NEXT: SI_CS_CHAIN_TC_W32 killed renamable $sgpr4_sgpr5, @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr1 @@ -131,6 +1905,884 @@ body: | ; GCN-LABEL: name: dont_preserve_non_wwm ; GCN: liveins: $sgpr0, $sgpr35, $vgpr0, $vgpr8, $vgpr16 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: renamable $vgpr16 = V_MOV_B32_e32 16, implicit $exec ; GCN-NEXT: renamable $vgpr8 = V_MOV_B32_e32 8, implicit $exec ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc @@ -162,6 +2814,886 @@ body: | ; GCN-LABEL: name: dont_preserve_v0_v7 ; GCN: liveins: $sgpr0, $sgpr35, $vgpr0, $vgpr7, $vgpr8, $vgpr9 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr0 ; GCN-NEXT: $sgpr35 = S_MOV_B32 5 ; GCN-NEXT: $sgpr35 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0 @@ -200,6 +3732,882 @@ body: | ; GCN-LABEL: name: dont_preserve_sgpr ; GCN: liveins: $sgpr0 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: renamable $sgpr1 = S_ADD_I32 killed renamable $sgpr0, renamable $sgpr0, implicit-def dead $scc ; GCN-NEXT: $sgpr0 = COPY killed renamable $sgpr1 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir b/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir index 4b4e9f1d81ec6..fa52c2f2bba71 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir @@ -20,7 +20,10 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v1 - ; MUBUF: $vgpr0 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: $vgpr0 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 @@ -28,13 +31,20 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_v1 ; MUBUF-V2A: liveins: $agpr0 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; MUBUF-V2A-NEXT: $vgpr0 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_v1 - ; FLATSCR: $vgpr0 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: $vgpr0 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 @@ -42,13 +52,20 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_v1 ; FLATSCR-V2A: liveins: $agpr0 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; FLATSCR-V2A-NEXT: $vgpr0 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v1 - ; MUBUF-GFX90A: $vgpr0 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: $vgpr0 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 @@ -56,13 +73,20 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v1 ; MUBUF-GFX90A-V2A: liveins: $agpr0 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v1 - ; FLATSCR-GFX90A: $vgpr0 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: $vgpr0 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -70,6 +94,10 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v1 ; FLATSCR-GFX90A-V2A: liveins: $agpr0 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec @@ -93,7 +121,11 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v2 - ; MUBUF: $vgpr0_vgpr1 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) @@ -103,6 +135,12 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_v2 ; MUBUF-V2A: liveins: $agpr0, $agpr1 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1 @@ -111,7 +149,11 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_v2 - ; FLATSCR: $vgpr0_vgpr1 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 @@ -119,6 +161,12 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_v2 ; FLATSCR-V2A: liveins: $agpr0, $agpr1 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1 @@ -127,7 +175,11 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v2 - ; MUBUF-GFX90A: $vgpr0_vgpr1 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) @@ -137,6 +189,12 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v2 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 ; MUBUF-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1 @@ -145,7 +203,11 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v2 - ; FLATSCR-GFX90A: $vgpr0_vgpr1 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -153,6 +215,12 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v2 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 ; FLATSCR-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1 @@ -178,7 +246,12 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v3 - ; MUBUF: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -190,6 +263,14 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_v3 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 ; MUBUF-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -200,7 +281,12 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_v3 - ; FLATSCR: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 @@ -208,6 +294,14 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_v3 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2 @@ -218,7 +312,12 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v3 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -230,6 +329,14 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v3 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 ; MUBUF-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -240,7 +347,12 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v3 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -248,6 +360,14 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v3 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 ; FLATSCR-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2 @@ -275,7 +395,13 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v4 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -289,6 +415,16 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_v4 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -301,7 +437,13 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_v4 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 @@ -309,6 +451,16 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_v4 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 @@ -321,7 +473,13 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v4 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -335,6 +493,16 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v4 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; MUBUF-GFX90A-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -347,7 +515,13 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v4 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -355,6 +529,16 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v4 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; FLATSCR-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 @@ -384,7 +568,14 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v5 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -400,6 +591,18 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_v5 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; MUBUF-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -414,7 +617,14 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_v5 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -424,6 +634,18 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_v5 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 @@ -438,7 +660,14 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v5 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -454,6 +683,18 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v5 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; MUBUF-GFX90A-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -468,7 +709,14 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v5 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -478,6 +726,18 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v5 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; FLATSCR-GFX90A-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 @@ -509,7 +769,15 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v6 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -527,6 +795,20 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_v6 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; MUBUF-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -543,7 +825,15 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_v6 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -553,6 +843,20 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_v6 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 @@ -569,7 +873,15 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v6 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -587,6 +899,20 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v6 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; MUBUF-GFX90A-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -603,7 +929,15 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v6 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -613,6 +947,20 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v6 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-GFX90A-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 @@ -646,7 +994,16 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v7 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -666,6 +1023,22 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_v7 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 ; MUBUF-V2A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -684,7 +1057,16 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_v7 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr4_vgpr5_vgpr6, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s96) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -694,6 +1076,22 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_v7 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 ; FLATSCR-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 @@ -712,7 +1110,16 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v7 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -732,6 +1139,22 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v7 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 ; MUBUF-GFX90A-V2A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -750,7 +1173,16 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v7 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr4_vgpr5_vgpr6, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s96) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -760,6 +1192,22 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v7 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 ; FLATSCR-GFX90A-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 @@ -795,7 +1243,17 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v8 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -817,6 +1275,24 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_v8 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; MUBUF-V2A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -837,7 +1313,17 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_v8 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -847,6 +1333,24 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_v8 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; FLATSCR-V2A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 @@ -867,7 +1371,17 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v8 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -889,6 +1403,24 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v8 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; MUBUF-GFX90A-V2A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -909,7 +1441,17 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v8 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -919,6 +1461,24 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v8 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; FLATSCR-GFX90A-V2A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 @@ -956,7 +1516,25 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v16 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -994,6 +1572,40 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_v16 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; MUBUF-V2A-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -1030,7 +1642,25 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_v16 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -1044,6 +1674,40 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_v16 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; FLATSCR-V2A-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 @@ -1080,7 +1744,25 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v16 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -1118,6 +1800,40 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v16 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; MUBUF-GFX90A-V2A-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -1154,7 +1870,25 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v16 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -1168,6 +1902,40 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v16 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; FLATSCR-GFX90A-V2A-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 @@ -1221,7 +1989,41 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v32 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -1291,6 +2093,72 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_v32 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27, $agpr28, $agpr29, $agpr30, $agpr31 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; MUBUF-V2A-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -1359,7 +2227,41 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_v32 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -1381,6 +2283,72 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_v32 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27, $agpr28, $agpr29, $agpr30, $agpr31 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr28 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; FLATSCR-V2A-NEXT: $agpr29 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 @@ -1449,7 +2417,41 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v32 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -1519,6 +2521,72 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v32 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27, $agpr28, $agpr29, $agpr30, $agpr31 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; MUBUF-GFX90A-V2A-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -1587,7 +2655,41 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v32 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -1609,6 +2711,72 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v32 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27, $agpr28, $agpr29, $agpr30, $agpr31 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr28 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; FLATSCR-GFX90A-V2A-NEXT: $agpr29 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 @@ -1694,7 +2862,10 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a1 - ; MUBUF: $agpr0 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: $agpr0 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) @@ -1704,13 +2875,20 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a1 ; MUBUF-V2A: liveins: $vgpr0 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; MUBUF-V2A-NEXT: $agpr0 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a1 - ; FLATSCR: $agpr0 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: $agpr0 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) @@ -1720,13 +2898,20 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a1 ; FLATSCR-V2A: liveins: $vgpr0 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; FLATSCR-V2A-NEXT: $agpr0 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a1 - ; MUBUF-GFX90A: $agpr0 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: $agpr0 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 @@ -1734,13 +2919,20 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a1 ; MUBUF-GFX90A-V2A: liveins: $vgpr0 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; MUBUF-GFX90A-V2A-NEXT: $agpr0 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; MUBUF-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a1 - ; FLATSCR-GFX90A: $agpr0 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: $agpr0 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -1748,6 +2940,10 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a1 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec @@ -1771,7 +2967,11 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a2 - ; MUBUF: $agpr0_agpr1 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 @@ -1785,6 +2985,12 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a2 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; MUBUF-V2A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; MUBUF-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1 @@ -1793,7 +2999,11 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a2 - ; FLATSCR: $agpr0_agpr1 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 @@ -1807,6 +3017,12 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a2 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; FLATSCR-V2A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; FLATSCR-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1 @@ -1815,7 +3031,11 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a2 - ; MUBUF-GFX90A: $agpr0_agpr1 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1 :: (load (s32) from %stack.0, addrspace 5) @@ -1825,6 +3045,12 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a2 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1 @@ -1833,7 +3059,11 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a2 - ; FLATSCR-GFX90A: $agpr0_agpr1 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -1841,6 +3071,12 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a2 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit killed $agpr0_agpr1 @@ -1866,7 +3102,12 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a3 - ; MUBUF: $agpr0_agpr1_agpr2 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1884,6 +3125,14 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a3 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; MUBUF-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1894,7 +3143,12 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a3 - ; FLATSCR: $agpr0_agpr1_agpr2 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1912,6 +3166,14 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a3 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; FLATSCR-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1922,7 +3184,12 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a3 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -1934,6 +3201,14 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a3 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; MUBUF-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1944,7 +3219,12 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a3 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -1952,6 +3232,14 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a3 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2 @@ -1979,7 +3267,13 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a4 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2001,6 +3295,16 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a4 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; MUBUF-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2013,7 +3317,13 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a4 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2035,6 +3345,16 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a4 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; FLATSCR-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2047,7 +3367,13 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a4 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -2061,6 +3387,16 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a4 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; MUBUF-GFX90A-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2073,7 +3409,13 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a4 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -2081,6 +3423,16 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a4 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 @@ -2110,7 +3462,14 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a5 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2136,6 +3495,18 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a5 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; MUBUF-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2150,7 +3521,14 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a5 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2176,6 +3554,18 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a5 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; FLATSCR-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2190,7 +3580,14 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a5 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -2206,6 +3603,18 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a5 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; MUBUF-GFX90A-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2220,7 +3629,14 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a5 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -2230,6 +3646,18 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a5 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 @@ -2261,7 +3689,15 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a6 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2291,6 +3727,20 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a6 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; MUBUF-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2307,7 +3757,15 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a6 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2337,6 +3795,20 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a6 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; FLATSCR-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2353,7 +3825,15 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a6 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -2371,6 +3851,20 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a6 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; MUBUF-GFX90A-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2387,7 +3881,15 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a6 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr4_agpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -2397,6 +3899,20 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a6 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 @@ -2430,7 +3946,16 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a7 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2464,6 +3989,22 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a7 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 ; MUBUF-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2482,7 +4023,16 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a7 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2516,6 +4066,22 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a7 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 ; FLATSCR-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2534,7 +4100,16 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a7 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -2554,6 +4129,22 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a7 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 ; MUBUF-GFX90A-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2572,7 +4163,16 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a7 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr4_agpr5_agpr6, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s96) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -2582,6 +4182,22 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a7 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 @@ -2617,7 +4233,17 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a8 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2655,6 +4281,24 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a8 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; MUBUF-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2675,7 +4319,17 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a8 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2713,6 +4367,24 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a8 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; FLATSCR-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2733,7 +4405,17 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a8 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -2755,6 +4437,24 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a8 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; MUBUF-GFX90A-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2775,7 +4475,17 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a8 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -2785,6 +4495,24 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a8 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 @@ -2822,7 +4550,18 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a9 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2864,6 +4603,26 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a9 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 ; MUBUF-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2886,7 +4645,18 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a9 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2928,6 +4698,26 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a9 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 ; FLATSCR-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2950,7 +4740,18 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a9 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -2974,6 +4775,26 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a9 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 ; MUBUF-GFX90A-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2996,7 +4817,18 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a9 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr8, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0 + 32, addrspace 5) @@ -3008,6 +4840,26 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a9 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 @@ -3047,7 +4899,19 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a10 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3093,6 +4957,28 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a10 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 ; MUBUF-V2A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3117,7 +5003,19 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a10 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3163,6 +5061,28 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a10 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 ; FLATSCR-V2A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3187,7 +5107,19 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a10 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -3213,6 +5145,28 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a10 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 ; MUBUF-GFX90A-V2A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3237,7 +5191,19 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a10 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr8_agpr9, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s64) into %stack.0 + 32, align 4, addrspace 5) @@ -3249,6 +5215,28 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a10 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 @@ -3290,7 +5278,20 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a11 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3340,6 +5341,30 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a11 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 ; MUBUF-V2A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3366,7 +5391,20 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a11 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3416,6 +5454,30 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a11 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 ; FLATSCR-V2A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3442,7 +5504,20 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a11 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -3470,6 +5545,30 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a11 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 ; MUBUF-GFX90A-V2A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3496,7 +5595,20 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a11 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr8_agpr9_agpr10, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s96) into %stack.0 + 32, align 4, addrspace 5) @@ -3508,6 +5620,30 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a11 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 @@ -3551,7 +5687,21 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a12 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3605,6 +5755,32 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a12 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 ; MUBUF-V2A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3633,7 +5809,21 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a12 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3687,6 +5877,32 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a12 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 ; FLATSCR-V2A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3715,7 +5931,21 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a12 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -3745,6 +5975,32 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a12 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 ; MUBUF-GFX90A-V2A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3773,7 +6029,21 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a12 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -3785,6 +6055,32 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a12 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 @@ -3830,7 +6126,25 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a16 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3900,6 +6214,40 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a16 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; MUBUF-V2A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3936,7 +6284,25 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a16 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -4006,6 +6372,40 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a16 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; FLATSCR-V2A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -4042,7 +6442,25 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a16 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -4080,6 +6498,40 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a16 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; MUBUF-GFX90A-V2A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -4116,7 +6568,25 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a16 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -4130,6 +6600,40 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a16 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 @@ -4183,7 +6687,41 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_a32 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -4317,6 +6855,72 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_av_a32 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; MUBUF-V2A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -4385,7 +6989,41 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_av_a32 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -4519,6 +7157,72 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_av_a32 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; FLATSCR-V2A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -4587,7 +7291,41 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a32 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -4657,6 +7395,72 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a32 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; MUBUF-GFX90A-V2A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -4725,7 +7529,41 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a32 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -4747,6 +7585,72 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a32 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir b/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir index c9208bfa15c63..55914bacb0dc1 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir @@ -59,6 +59,10 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v2_partial_agpr ; MUBUF-V2A: liveins: $agpr0 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1 @@ -69,6 +73,10 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v2_partial_agpr ; FLATSCR-V2A: liveins: $agpr0 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) @@ -96,6 +104,11 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v3_partial_agpr ; MUBUF-V2A: liveins: $agpr0 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) @@ -108,6 +121,11 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v3_partial_agpr ; FLATSCR-V2A: liveins: $agpr0 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s64) into %stack.0, align 4, addrspace 5) @@ -135,6 +153,12 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v4_partial_agpr ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -149,6 +173,12 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v4_partial_agpr ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 @@ -180,6 +210,13 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v5_partial_agpr ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) @@ -196,6 +233,13 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v5_partial_agpr ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 @@ -227,6 +271,14 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v6_partial_agpr ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -245,6 +297,14 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v6_partial_agpr ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 @@ -280,6 +340,16 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v8_partial_agpr ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) @@ -302,6 +372,16 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v8_partial_agpr ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr7, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 @@ -335,6 +415,24 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v16_partial_agpr ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) @@ -373,6 +471,24 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v16_partial_agpr ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir b/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir index 2fbe08300af57..94518c6ae455f 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir @@ -20,7 +20,10 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v1 - ; MUBUF: $vgpr0 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: $vgpr0 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 @@ -28,13 +31,20 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v1 ; MUBUF-V2A: liveins: $agpr0 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; MUBUF-V2A-NEXT: $vgpr0 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_v1 - ; FLATSCR: $vgpr0 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: $vgpr0 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 @@ -42,13 +52,20 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v1 ; FLATSCR-V2A: liveins: $agpr0 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; FLATSCR-V2A-NEXT: $vgpr0 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_v1 - ; MUBUF-GFX90A: $vgpr0 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: $vgpr0 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 @@ -56,13 +73,20 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v1 ; MUBUF-GFX90A-V2A: liveins: $agpr0 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v1 - ; FLATSCR-GFX90A: $vgpr0 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: $vgpr0 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -70,6 +94,10 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v1 ; FLATSCR-GFX90A-V2A: liveins: $agpr0 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec @@ -93,7 +121,11 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v2 - ; MUBUF: $vgpr0_vgpr1 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) @@ -103,6 +135,12 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v2 ; MUBUF-V2A: liveins: $agpr0, $agpr1 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1 @@ -111,7 +149,11 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_v2 - ; FLATSCR: $vgpr0_vgpr1 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 @@ -119,6 +161,12 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v2 ; FLATSCR-V2A: liveins: $agpr0, $agpr1 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1 @@ -127,7 +175,11 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_v2 - ; MUBUF-GFX90A: $vgpr0_vgpr1 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) @@ -137,6 +189,12 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v2 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 ; MUBUF-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1 @@ -145,7 +203,11 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v2 - ; FLATSCR-GFX90A: $vgpr0_vgpr1 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -153,6 +215,12 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v2 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 ; FLATSCR-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1 @@ -178,7 +246,12 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v3 - ; MUBUF: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -190,6 +263,14 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v3 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 ; MUBUF-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -200,7 +281,12 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_v3 - ; FLATSCR: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 @@ -208,6 +294,14 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v3 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2 @@ -218,7 +312,12 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_v3 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -230,6 +329,14 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v3 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 ; MUBUF-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -240,7 +347,12 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v3 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -248,6 +360,14 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v3 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 ; FLATSCR-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2 @@ -275,7 +395,13 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v4 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -289,6 +415,16 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v4 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -301,7 +437,13 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_v4 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 @@ -309,6 +451,16 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v4 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 @@ -321,7 +473,13 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_v4 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -335,6 +493,16 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v4 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; MUBUF-GFX90A-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -347,7 +515,13 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v4 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -355,6 +529,16 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v4 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; FLATSCR-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 @@ -384,7 +568,14 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v5 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -400,6 +591,18 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v5 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; MUBUF-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -414,7 +617,14 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_v5 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -424,6 +634,18 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v5 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 @@ -438,7 +660,14 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_v5 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -454,6 +683,18 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v5 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; MUBUF-GFX90A-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -468,7 +709,14 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v5 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -478,6 +726,18 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v5 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; FLATSCR-GFX90A-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 @@ -509,7 +769,15 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v6 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -527,6 +795,20 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v6 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; MUBUF-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -543,7 +825,15 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_v6 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -553,6 +843,20 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v6 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 @@ -569,7 +873,15 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_v6 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -587,6 +899,20 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v6 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; MUBUF-GFX90A-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -603,7 +929,15 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v6 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -613,6 +947,20 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v6 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-GFX90A-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 @@ -646,7 +994,17 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v8 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -668,6 +1026,24 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v8 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; MUBUF-V2A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -688,7 +1064,17 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_v8 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -698,6 +1084,24 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v8 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; FLATSCR-V2A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 @@ -718,7 +1122,17 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_v8 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -740,6 +1154,24 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v8 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; MUBUF-GFX90A-V2A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -760,7 +1192,17 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v8 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -770,6 +1212,24 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v8 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; FLATSCR-GFX90A-V2A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 @@ -807,7 +1267,25 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v16 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -845,6 +1323,40 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v16 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; MUBUF-V2A-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -881,7 +1393,25 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_v16 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -895,6 +1425,40 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v16 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; FLATSCR-V2A-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 @@ -931,7 +1495,25 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_v16 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -969,6 +1551,40 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v16 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; MUBUF-GFX90A-V2A-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -1005,7 +1621,25 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v16 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -1019,6 +1653,40 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v16 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; FLATSCR-GFX90A-V2A-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 @@ -1072,7 +1740,41 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v32 - ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -1142,6 +1844,72 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v32 ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27, $agpr28, $agpr29, $agpr30, $agpr31 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; MUBUF-V2A-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -1210,7 +1978,41 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_v32 - ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -1232,6 +2034,72 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v32 ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27, $agpr28, $agpr29, $agpr30, $agpr31 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr28 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; FLATSCR-V2A-NEXT: $agpr29 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 @@ -1300,7 +2168,41 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_v32 - ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -1370,6 +2272,72 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v32 ; MUBUF-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27, $agpr28, $agpr29, $agpr30, $agpr31 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; MUBUF-GFX90A-V2A-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -1438,7 +2406,41 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v32 - ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -1460,6 +2462,72 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v32 ; FLATSCR-GFX90A-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27, $agpr28, $agpr29, $agpr30, $agpr31 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $agpr28 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; FLATSCR-GFX90A-V2A-NEXT: $agpr29 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 @@ -1545,7 +2613,10 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_a1 - ; MUBUF: $agpr0 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: $agpr0 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) @@ -1555,13 +2626,20 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_a1 ; MUBUF-V2A: liveins: $vgpr0 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; MUBUF-V2A-NEXT: $agpr0 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_a1 - ; FLATSCR: $agpr0 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: $agpr0 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) @@ -1571,13 +2649,20 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_a1 ; FLATSCR-V2A: liveins: $vgpr0 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; FLATSCR-V2A-NEXT: $agpr0 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_a1 - ; MUBUF-GFX90A: $agpr0 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: $agpr0 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 @@ -1585,13 +2670,20 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a1 ; MUBUF-GFX90A-V2A: liveins: $vgpr0 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; MUBUF-GFX90A-V2A-NEXT: $agpr0 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; MUBUF-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a1 - ; FLATSCR-GFX90A: $agpr0 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: $agpr0 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -1599,6 +2691,10 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a1 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; FLATSCR-GFX90A-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec @@ -1622,7 +2718,11 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_a2 - ; MUBUF: $agpr0_agpr1 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 @@ -1636,6 +2736,12 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_a2 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; MUBUF-V2A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; MUBUF-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1 @@ -1644,7 +2750,11 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_a2 - ; FLATSCR: $agpr0_agpr1 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 @@ -1658,6 +2768,12 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_a2 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; FLATSCR-V2A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; FLATSCR-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1 @@ -1666,7 +2782,11 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_a2 - ; MUBUF-GFX90A: $agpr0_agpr1 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1 :: (load (s32) from %stack.0, addrspace 5) @@ -1676,6 +2796,12 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a2 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; MUBUF-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1 @@ -1684,7 +2810,11 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a2 - ; FLATSCR-GFX90A: $agpr0_agpr1 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -1692,6 +2822,12 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a2 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit killed $agpr0_agpr1 @@ -1717,7 +2853,12 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_a3 - ; MUBUF: $agpr0_agpr1_agpr2 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1735,6 +2876,14 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_a3 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; MUBUF-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1745,7 +2894,12 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_a3 - ; FLATSCR: $agpr0_agpr1_agpr2 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1763,6 +2917,14 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_a3 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; FLATSCR-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1773,7 +2935,12 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_a3 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -1785,6 +2952,14 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a3 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; MUBUF-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1795,7 +2970,12 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a3 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -1803,6 +2983,14 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a3 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2 @@ -1830,7 +3018,13 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_a4 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1852,6 +3046,16 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_a4 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; MUBUF-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1864,7 +3068,13 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_a4 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1886,6 +3096,16 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_a4 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; FLATSCR-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1898,7 +3118,13 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_a4 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -1912,6 +3138,16 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a4 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; MUBUF-GFX90A-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1924,7 +3160,13 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a4 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 @@ -1932,6 +3174,16 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a4 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 @@ -1961,7 +3213,14 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_a5 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1987,6 +3246,18 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_a5 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; MUBUF-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2001,7 +3272,14 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_a5 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2027,6 +3305,18 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_a5 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; FLATSCR-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2041,7 +3331,14 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_a5 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -2057,6 +3354,18 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a5 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; MUBUF-GFX90A-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2071,7 +3380,14 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a5 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -2081,6 +3397,18 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a5 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 @@ -2112,7 +3440,15 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_a6 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2142,6 +3478,20 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_a6 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; MUBUF-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2158,7 +3508,15 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_a6 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2188,6 +3546,20 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_a6 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; FLATSCR-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2204,7 +3576,15 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_a6 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -2222,6 +3602,20 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a6 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; MUBUF-GFX90A-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2238,7 +3632,15 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a6 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr4_agpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -2248,6 +3650,20 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a6 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 @@ -2281,7 +3697,17 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_a8 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2319,6 +3745,24 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_a8 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; MUBUF-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2339,7 +3783,17 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_a8 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2377,6 +3831,24 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_a8 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; FLATSCR-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2397,7 +3869,17 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_a8 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -2419,6 +3901,24 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a8 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; MUBUF-GFX90A-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2439,7 +3939,17 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a8 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -2449,6 +3959,24 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a8 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 @@ -2486,7 +4014,25 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_a16 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2556,6 +4102,40 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_a16 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; MUBUF-V2A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2592,7 +4172,25 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_a16 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2662,6 +4260,40 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_a16 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; FLATSCR-V2A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2698,7 +4330,25 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_a16 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -2736,6 +4386,40 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a16 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; MUBUF-GFX90A-V2A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2772,7 +4456,25 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a16 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -2786,6 +4488,40 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a16 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 @@ -2839,7 +4575,41 @@ machineFunctionInfo: body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_a32 - ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF + ; MUBUF: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; MUBUF-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -2973,6 +4743,72 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_a32 ; MUBUF-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31 ; MUBUF-V2A-NEXT: {{ $}} + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; MUBUF-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; MUBUF-V2A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3041,7 +4877,41 @@ body: | ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-LABEL: name: test_spill_a32 - ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF + ; FLATSCR: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; FLATSCR-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3175,6 +5045,72 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_a32 ; FLATSCR-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31 ; FLATSCR-V2A-NEXT: {{ $}} + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; FLATSCR-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; FLATSCR-V2A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3243,7 +5179,41 @@ body: | ; FLATSCR-V2A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-LABEL: name: test_spill_a32 - ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF + ; MUBUF-GFX90A: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; MUBUF-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) @@ -3313,6 +5283,72 @@ body: | ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a32 ; MUBUF-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31 ; MUBUF-GFX90A-V2A-NEXT: {{ $}} + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; MUBUF-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; MUBUF-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; MUBUF-GFX90A-V2A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; MUBUF-GFX90A-V2A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -3381,7 +5417,41 @@ body: | ; MUBUF-GFX90A-V2A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a32 - ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF + ; FLATSCR-GFX90A: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) @@ -3403,6 +5473,72 @@ body: | ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a32 ; FLATSCR-GFX90A-V2A: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31 ; FLATSCR-GFX90A-V2A-NEXT: {{ $}} + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; FLATSCR-GFX90A-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; FLATSCR-GFX90A-V2A-NEXT: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; FLATSCR-GFX90A-V2A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; FLATSCR-GFX90A-V2A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 diff --git a/llvm/test/CodeGen/AMDGPU/pei-cfi-saves-bug.ll b/llvm/test/CodeGen/AMDGPU/pei-cfi-saves-bug.ll new file mode 100644 index 0000000000000..c49dff315a548 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/pei-cfi-saves-bug.ll @@ -0,0 +1,118 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-spill-cfi-saved-regs < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-cfi-saved-regs < %s | FileCheck %s + +; Function Attrs: noinline optnone +define fastcc void @tail_callee() #2 { +; CHECK-LABEL: tail_callee: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill +; CHECK-NEXT: s_mov_b64 exec, s[4:5] +; CHECK-NEXT: v_writelane_b32 v0, exec_lo, 0 +; CHECK-NEXT: v_writelane_b32 v0, exec_hi, 1 +; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload +; CHECK-NEXT: s_mov_b64 exec, s[4:5] +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] + ret void +} + +; Function Attrs: noinline +define fastcc void @callee_no_fp() #0 { +; CHECK-LABEL: callee_no_fp: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b32 s33, s32 +; CHECK-NEXT: s_xor_saveexec_b64 s[16:17], -1 +; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill +; CHECK-NEXT: s_mov_b64 exec, s[16:17] +; CHECK-NEXT: v_writelane_b32 v1, exec_lo, 2 +; CHECK-NEXT: v_writelane_b32 v1, exec_hi, 3 +; CHECK-NEXT: v_writelane_b32 v1, s30, 0 +; CHECK-NEXT: s_addk_i32 s32, 0x400 +; CHECK-NEXT: v_writelane_b32 v1, s31, 1 +; CHECK-NEXT: s_getpc_b64 s[16:17] +; CHECK-NEXT: s_add_u32 s16, s16, tail_callee@gotpcrel32@lo+4 +; CHECK-NEXT: s_addc_u32 s17, s17, tail_callee@gotpcrel32@hi+12 +; CHECK-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] +entry: + tail call fastcc void @tail_callee() #3 + unreachable +} + +define protected amdgpu_kernel void @kernel() #1 { +; CHECK-LABEL: kernel: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17 +; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0 +; CHECK-NEXT: s_add_u32 s0, s0, s17 +; CHECK-NEXT: s_addc_u32 s1, s1, 0 +; CHECK-NEXT: s_mov_b32 s32, 0 +; CHECK-NEXT: s_cbranch_scc0 .LBB2_2 +; CHECK-NEXT: ; %bb.1: ; %end +; CHECK-NEXT: s_endpgm +; CHECK-NEXT: .LBB2_2: ; %body +; CHECK-NEXT: s_getpc_b64 s[12:13] +; CHECK-NEXT: s_add_u32 s12, s12, callee_no_fp@gotpcrel32@lo+4 +; CHECK-NEXT: s_addc_u32 s13, s13, callee_no_fp@gotpcrel32@hi+12 +; CHECK-NEXT: s_load_dwordx2 s[18:19], s[12:13], 0x0 +; CHECK-NEXT: v_lshlrev_b32_e32 v2, 20, v2 +; CHECK-NEXT: v_lshlrev_b32_e32 v1, 10, v1 +; CHECK-NEXT: v_or3_b32 v31, v0, v1, v2 +; CHECK-NEXT: s_mov_b32 s12, s14 +; CHECK-NEXT: s_mov_b32 s13, s15 +; CHECK-NEXT: s_mov_b32 s14, s16 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_swappc_b64 s[30:31], s[18:19] +entry: + br i1 undef, label %end, label %body + +body: ; preds = %entry + tail call fastcc void @callee_no_fp() #3 + unreachable + +end: ; preds = %entry + ret void +} + +; When we have calls, spilling a CSR VGPR for CFI saves should force FP usage +; Function Attrs: noinline +define dso_local fastcc void @func_needs_fp() unnamed_addr #0 { +; CHECK-LABEL: func_needs_fp: +; CHECK: .Lfunc_needs_fp$local: +; CHECK-NEXT: .type .Lfunc_needs_fp$local,@function +; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b32 s16, s33 +; CHECK-NEXT: s_mov_b32 s33, s32 +; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1 +; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; CHECK-NEXT: s_mov_b64 exec, s[18:19] +; CHECK-NEXT: v_writelane_b32 v40, exec_lo, 2 +; CHECK-NEXT: v_writelane_b32 v40, exec_hi, 3 +; CHECK-NEXT: v_writelane_b32 v40, s16, 4 +; CHECK-NEXT: v_writelane_b32 v40, s30, 0 +; CHECK-NEXT: s_addk_i32 s32, 0x400 +; CHECK-NEXT: v_writelane_b32 v40, s31, 1 +; CHECK-NEXT: s_getpc_b64 s[16:17] +; CHECK-NEXT: s_add_u32 s16, s16, tail_callee_fp@rel32@lo+4 +; CHECK-NEXT: s_addc_u32 s17, s17, tail_callee_fp@rel32@hi+12 +; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] +entry: + tail call fastcc void @tail_callee_fp() #3 + unreachable +} + +; Function Attrs: noinline optnone +declare dso_local fastcc void @tail_callee_fp() unnamed_addr #2 + +attributes #0 = { noinline } +attributes #1 = { "use-soft-float"="false" } +attributes #2 = { noinline optnone } +attributes #3 = { convergent nounwind } + diff --git a/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir b/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir index aa4428f3da4eb..8027373123d61 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir @@ -27,6 +27,8 @@ body: | ; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; CHECK-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $sgpr4, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr4 = S_MOV_B32 524288 diff --git a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir index 05cbd4c2a010d..71e7ca11a86cd 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir @@ -29,11 +29,43 @@ body: | ; CHECK-LABEL: name: scavenge_sgpr_pei_no_sgprs ; CHECK: liveins: $sgpr40, $sgpr41, $vgpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 ; CHECK-NEXT: $sgpr40 = frame-setup COPY $sgpr33 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr40 ; CHECK-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; CHECK-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; CHECK-NEXT: $sgpr41 = frame-setup COPY $sgpr34 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr41 ; CHECK-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; CHECK-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc ; CHECK-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec @@ -45,6 +77,7 @@ body: | ; CHECK-NEXT: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31 ; CHECK-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; CHECK-NEXT: $sgpr34 = frame-destroy COPY $sgpr41 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; CHECK-NEXT: $sgpr33 = frame-destroy COPY $sgpr40 ; CHECK-NEXT: S_ENDPGM 0, implicit $vcc S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc @@ -77,11 +110,42 @@ body: | ; CHECK-LABEL: name: scavenge_sgpr_pei_one_sgpr ; CHECK: liveins: $sgpr29, $sgpr40, $vgpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 ; CHECK-NEXT: $sgpr29 = frame-setup COPY $sgpr33 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr29 ; CHECK-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; CHECK-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; CHECK-NEXT: $sgpr40 = frame-setup COPY $sgpr34 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr40 ; CHECK-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; CHECK-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc ; CHECK-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec @@ -93,6 +157,7 @@ body: | ; CHECK-NEXT: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr31 ; CHECK-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; CHECK-NEXT: $sgpr34 = frame-destroy COPY $sgpr40 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; CHECK-NEXT: $sgpr33 = frame-destroy COPY $sgpr29 ; CHECK-NEXT: S_ENDPGM 0, implicit $vcc S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc @@ -125,11 +190,41 @@ body: | ; CHECK-LABEL: name: scavenge_sgpr_pei_one_sgpr_64 ; CHECK: liveins: $sgpr28, $sgpr29, $vgpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 ; CHECK-NEXT: $sgpr28 = frame-setup COPY $sgpr33 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr28 ; CHECK-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; CHECK-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; CHECK-NEXT: $sgpr29 = frame-setup COPY $sgpr34 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr29 ; CHECK-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; CHECK-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc ; CHECK-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec @@ -141,6 +236,7 @@ body: | ; CHECK-NEXT: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr31 ; CHECK-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; CHECK-NEXT: $sgpr34 = frame-destroy COPY $sgpr29 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; CHECK-NEXT: $sgpr33 = frame-destroy COPY $sgpr28 ; CHECK-NEXT: S_ENDPGM 0, implicit $vcc S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc @@ -172,11 +268,41 @@ body: | ; CHECK-LABEL: name: scavenge_sgpr_pei_prefer_vcc ; CHECK: liveins: $sgpr28, $sgpr29, $vgpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 ; CHECK-NEXT: $sgpr28 = frame-setup COPY $sgpr33 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr28 ; CHECK-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; CHECK-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; CHECK-NEXT: $sgpr29 = frame-setup COPY $sgpr34 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr29 ; CHECK-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; CHECK-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr30, implicit-def $sgpr31 ; CHECK-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec @@ -188,6 +314,7 @@ body: | ; CHECK-NEXT: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr31 ; CHECK-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; CHECK-NEXT: $sgpr34 = frame-destroy COPY $sgpr29 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; CHECK-NEXT: $sgpr33 = frame-destroy COPY $sgpr28 ; CHECK-NEXT: S_ENDPGM 0 S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr30, implicit-def $sgpr31 diff --git a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir index 4f1c9a20fddc3..7c4e03fd0e6df 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir @@ -25,11 +25,43 @@ body: | ; MUBUF-LABEL: name: scavenge_sgpr_pei_no_sgprs ; MUBUF: liveins: $sgpr40, $sgpr41, $vgpr1 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 ; MUBUF-NEXT: $sgpr40 = frame-setup COPY $sgpr33 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr40 ; MUBUF-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; MUBUF-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; MUBUF-NEXT: $sgpr41 = frame-setup COPY $sgpr34 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr41 ; MUBUF-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; MUBUF-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; MUBUF-NEXT: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc ; MUBUF-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec @@ -39,17 +71,50 @@ body: | ; MUBUF-NEXT: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31 ; MUBUF-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; MUBUF-NEXT: $sgpr34 = frame-destroy COPY $sgpr41 + ; MUBUF-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; MUBUF-NEXT: $sgpr33 = frame-destroy COPY $sgpr40 ; MUBUF-NEXT: S_ENDPGM 0, implicit $vcc ; ; FLATSCR-LABEL: name: scavenge_sgpr_pei_no_sgprs ; FLATSCR: liveins: $sgpr40, $sgpr41, $vgpr1 ; FLATSCR-NEXT: {{ $}} + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 ; FLATSCR-NEXT: $sgpr40 = frame-setup COPY $sgpr33 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr40 ; FLATSCR-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; FLATSCR-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; FLATSCR-NEXT: $sgpr41 = frame-setup COPY $sgpr34 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr41 ; FLATSCR-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; FLATSCR-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; FLATSCR-NEXT: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc ; FLATSCR-NEXT: $sgpr42 = S_ADD_I32 $sgpr33, 8192, implicit-def $scc @@ -58,6 +123,7 @@ body: | ; FLATSCR-NEXT: $vgpr0 = V_OR_B32_e32 killed $sgpr42, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31 ; FLATSCR-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; FLATSCR-NEXT: $sgpr34 = frame-destroy COPY $sgpr41 + ; FLATSCR-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; FLATSCR-NEXT: $sgpr33 = frame-destroy COPY $sgpr40 ; FLATSCR-NEXT: S_ENDPGM 0, implicit $vcc S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc diff --git a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir index 480859a09a347..cd335321e2156 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir @@ -24,11 +24,43 @@ body: | ; CHECK-LABEL: name: scavenge_sgpr_pei ; CHECK: liveins: $sgpr40, $sgpr41, $vgpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 ; CHECK-NEXT: $sgpr40 = frame-setup COPY $sgpr33 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr40 ; CHECK-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 262080, implicit-def $scc ; CHECK-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294705152, implicit-def dead $scc ; CHECK-NEXT: $sgpr41 = frame-setup COPY $sgpr34 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr41 ; CHECK-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; CHECK-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 786432, implicit-def dead $scc ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc ; CHECK-NEXT: $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec @@ -37,6 +69,7 @@ body: | ; CHECK-NEXT: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31 ; CHECK-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; CHECK-NEXT: $sgpr34 = frame-destroy COPY $sgpr41 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; CHECK-NEXT: $sgpr33 = frame-destroy COPY $sgpr40 ; CHECK-NEXT: S_ENDPGM 0, implicit $vcc S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc diff --git a/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir index 63a4759d8e740..4b21c2e4fb619 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir @@ -24,18 +24,855 @@ body: | liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX8-LABEL: name: pei_scavenge_vgpr_spill - ; GFX8: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 + ; GFX8: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr2 ; GFX8-NEXT: {{ $}} + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX8-NEXT: $sgpr4 = COPY $sgpr33 ; GFX8-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX8-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX8-NEXT: $sgpr6_sgpr7 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GFX8-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 1048832, implicit-def dead $scc ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr2, 1048832 ; GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 ; GFX8-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, undef $vgpr2 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr33, $vgpr2, 0, 32 ; GFX8-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr34, 1, undef $vgpr2 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr34, $vgpr2, 1, 32 ; GFX8-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX8-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX8-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX8-NEXT: $vcc_lo = S_MOV_B32 8192 @@ -51,22 +888,860 @@ body: | ; GFX8-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 1048832, implicit-def dead $scc ; GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) ; GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 + ; GFX8-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX8-NEXT: $sgpr33 = COPY $sgpr4 ; GFX8-NEXT: S_ENDPGM 0, amdgpu_allvgprs ; ; GFX9-LABEL: name: pei_scavenge_vgpr_spill - ; GFX9: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 + ; GFX9: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr2 ; GFX9-NEXT: {{ $}} + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX9-NEXT: $sgpr4 = COPY $sgpr33 ; GFX9-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX9-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX9-NEXT: $sgpr6_sgpr7 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GFX9-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 1048832, implicit-def dead $scc ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr2, 1048832 ; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 ; GFX9-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, undef $vgpr2 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr33, $vgpr2, 0, 32 ; GFX9-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr34, 1, undef $vgpr2 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr34, $vgpr2, 1, 32 ; GFX9-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; GFX9-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc ; GFX9-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec ; GFX9-NEXT: $vgpr0 = V_ADD_U32_e32 8192, killed $vgpr0, implicit $exec @@ -80,22 +1755,860 @@ body: | ; GFX9-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 1048832, implicit-def dead $scc ; GFX9-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) ; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 + ; GFX9-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; GFX9-NEXT: $sgpr33 = COPY $sgpr4 ; GFX9-NEXT: S_ENDPGM 0, amdgpu_allvgprs ; ; GFX9-FLATSCR-LABEL: name: pei_scavenge_vgpr_spill - ; GFX9-FLATSCR: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 + ; GFX9-FLATSCR: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr2 ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX9-FLATSCR-NEXT: $sgpr4 = COPY $sgpr33 ; GFX9-FLATSCR-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX9-FLATSCR-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX9-FLATSCR-NEXT: $sgpr6_sgpr7 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GFX9-FLATSCR-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 16388, implicit-def dead $scc ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr2, killed $sgpr5, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr2, 1048832 ; GFX9-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 ; GFX9-FLATSCR-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, undef $vgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr33, $vgpr2, 0, 32 ; GFX9-FLATSCR-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr34, 1, undef $vgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr34, $vgpr2, 1, 32 ; GFX9-FLATSCR-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX9-FLATSCR-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc ; GFX9-FLATSCR-NEXT: $sgpr4 = S_ADD_I32 $sgpr33, 8192, implicit-def $scc ; GFX9-FLATSCR-NEXT: $vgpr0 = V_MOV_B32_e32 killed $sgpr4, implicit $exec @@ -108,6 +2621,7 @@ body: | ; GFX9-FLATSCR-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 16388, implicit-def dead $scc ; GFX9-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR killed $sgpr5, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.3, addrspace 5) ; GFX9-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 + ; GFX9-FLATSCR-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; GFX9-FLATSCR-NEXT: $sgpr33 = COPY $sgpr4 ; GFX9-FLATSCR-NEXT: S_ENDPGM 0, amdgpu_allvgprs $vgpr0 = V_MOV_B32_e32 %stack.0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir b/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir index bfca9331a5d25..0cfa373f125a4 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,+wavefrontsize32,-wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,W32 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,-wavefrontsize32,+wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,W64 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,+wavefrontsize32,-wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=W32 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,-wavefrontsize32,+wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=W64 --- | define void @one_block() { ret void } @@ -23,15 +23,93 @@ machineFunctionInfo: body: | bb.0: liveins: $sgpr30_sgpr31 - ; CHECK-LABEL: name: one_block - ; CHECK: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $m0 = S_MOV_B32 9 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 - ; CHECK-NEXT: $m0 = S_MOV_B32 9 - ; CHECK-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; W32-LABEL: name: one_block + ; W32: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 + ; W32-NEXT: {{ $}} + ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W32-NEXT: $m0 = S_MOV_B32 9 + ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 0 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 96 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr72 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr73 + ; W32-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 + ; W32-NEXT: $m0 = S_MOV_B32 9 + ; W32-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; + ; W64-LABEL: name: one_block + ; W64: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 + ; W64-NEXT: {{ $}} + ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W64-NEXT: $m0 = S_MOV_B32 9 + ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 0 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 192 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr72 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr73 + ; W64-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 + ; W64-NEXT: $m0 = S_MOV_B32 9 + ; W64-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 S_SETPC_B64_return $sgpr30_sgpr31 ... @@ -47,15 +125,93 @@ machineFunctionInfo: body: | bb.0: liveins: $sgpr30_sgpr31 - ; CHECK-LABEL: name: one_block_csr_only - ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $m0 = S_MOV_B32 16711935 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66 - ; CHECK-NEXT: $m0 = S_MOV_B32 16711935 - ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; W32-LABEL: name: one_block_csr_only + ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 + ; W32-NEXT: {{ $}} + ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W32-NEXT: $m0 = S_MOV_B32 16711935 + ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 0 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 64 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 96 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec_lo, 32, 128 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 160 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec_lo, 32, 192 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec_lo, 32, 224 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec_lo, 32, 512 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec_lo, 32, 544 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec_lo, 32, 576 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec_lo, 32, 608 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec_lo, 32, 640 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec_lo, 32, 672 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec_lo, 32, 704 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec_lo, 32, 736 + ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66 + ; W32-NEXT: $m0 = S_MOV_B32 16711935 + ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; + ; W64-LABEL: name: one_block_csr_only + ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 + ; W64-NEXT: {{ $}} + ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W64-NEXT: $m0 = S_MOV_B32 16711935 + ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 0 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 64 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 128 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 192 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 256 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 320 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 384 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 448 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1024 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1088 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1152 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1216 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 1280 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 1344 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 1408 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 1472 + ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66 + ; W64-NEXT: $m0 = S_MOV_B32 16711935 + ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66 S_SETPC_B64_return $sgpr30_sgpr31 ... @@ -75,23 +231,237 @@ machineFunctionInfo: body: | bb.0: liveins: $sgpr30_sgpr31 - ; CHECK-LABEL: name: multiple_blocks - ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $m0 = S_MOV_B32 3 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; CHECK-NEXT: $m0 = S_MOV_B32 65 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) - ; CHECK-NEXT: $m0 = S_MOV_B32 1 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) - ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232 - ; CHECK-NEXT: $m0 = S_MOV_B32 1 - ; CHECK-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: (load (s1024) from %stack.2, align 4, addrspace 5) - ; CHECK-NEXT: $m0 = S_MOV_B32 65 - ; CHECK-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: (load (s1024) from %stack.1, align 4, addrspace 5) - ; CHECK-NEXT: $m0 = S_MOV_B32 3 - ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; W32-LABEL: name: multiple_blocks + ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 + ; W32-NEXT: {{ $}} + ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; W32-NEXT: $m0 = S_MOV_B32 3 + ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 1024 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 1056 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 + ; W32-NEXT: $m0 = S_MOV_B32 65 + ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr104, 32, $exec_lo, 32, 128 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr105 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr106 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr107 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr108 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr109 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr110, 32, $exec_lo, 32, 320 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr111 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr120 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr121 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr122 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr123 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr124 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr125 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr126 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr127 + ; W32-NEXT: $m0 = S_MOV_B32 1 + ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr232, 32, $exec_lo, 32, 0 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr233 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr234 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr235 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr236 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr237 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr238 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr239 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr248 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr249 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr250 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr251 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr252 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr253 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr254 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr255 + ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232 + ; W32-NEXT: $m0 = S_MOV_B32 1 + ; W32-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: (load (s1024) from %stack.2, align 4, addrspace 5) + ; W32-NEXT: $m0 = S_MOV_B32 65 + ; W32-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: (load (s1024) from %stack.1, align 4, addrspace 5) + ; W32-NEXT: $m0 = S_MOV_B32 3 + ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; + ; W64-LABEL: name: multiple_blocks + ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 + ; W64-NEXT: {{ $}} + ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; W64-NEXT: $m0 = S_MOV_B32 3 + ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 2048 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 2112 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 + ; W64-NEXT: $m0 = S_MOV_B32 65 + ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr104, 32, $exec, 64, 256 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr105 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr106 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr107 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr108 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr109 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr110, 32, $exec, 64, 640 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr111 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr120 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr121 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr122 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr123 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr124 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr125 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr126 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr127 + ; W64-NEXT: $m0 = S_MOV_B32 1 + ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr232, 32, $exec, 64, 0 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr233 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr234 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr235 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr236 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr237 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr238 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr239 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr248 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr249 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr250 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr251 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr252 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr253 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr254 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr255 + ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232 + ; W64-NEXT: $m0 = S_MOV_B32 1 + ; W64-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: (load (s1024) from %stack.2, align 4, addrspace 5) + ; W64-NEXT: $m0 = S_MOV_B32 65 + ; W64-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: (load (s1024) from %stack.1, align 4, addrspace 5) + ; W64-NEXT: $m0 = S_MOV_B32 3 + ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232 S_SETPC_B64_return $sgpr30_sgpr31 ... @@ -109,19 +479,165 @@ machineFunctionInfo: body: | bb.0: liveins: $sgpr30_sgpr31 - ; CHECK-LABEL: name: reg_tuples - ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $m0 = S_MOV_B32 7 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; CHECK-NEXT: $m0 = S_MOV_B32 3 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) - ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73 - ; CHECK-NEXT: $m0 = S_MOV_B32 3 - ; CHECK-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: (load (s1024) from %stack.1, align 4, addrspace 5) - ; CHECK-NEXT: $m0 = S_MOV_B32 7 - ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; W32-LABEL: name: reg_tuples + ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 + ; W32-NEXT: {{ $}} + ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; W32-NEXT: $m0 = S_MOV_B32 7 + ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 256 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 288 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 320 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 + ; W32-NEXT: $m0 = S_MOV_B32 3 + ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr72, 32, $exec_lo, 32, 0 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr73, 32, $exec_lo, 32, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr74 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr75 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr76 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr77 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr78 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr79 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr88 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr89 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr90 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr91 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr92 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr93 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr94 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr95 + ; W32-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73 + ; W32-NEXT: $m0 = S_MOV_B32 3 + ; W32-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: (load (s1024) from %stack.1, align 4, addrspace 5) + ; W32-NEXT: $m0 = S_MOV_B32 7 + ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; + ; W64-LABEL: name: reg_tuples + ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 + ; W64-NEXT: {{ $}} + ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 + ; W64-NEXT: $m0 = S_MOV_B32 7 + ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 512 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 576 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 640 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 + ; W64-NEXT: $m0 = S_MOV_B32 3 + ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr72, 32, $exec, 64, 0 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr73, 32, $exec, 64, 64 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr74 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr75 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr76 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr77 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr78 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr79 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr88 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr89 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr90 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr91 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr92 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr93 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr94 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr95 + ; W64-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73 + ; W64-NEXT: $m0 = S_MOV_B32 3 + ; W64-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: (load (s1024) from %stack.1, align 4, addrspace 5) + ; W64-NEXT: $m0 = S_MOV_B32 7 + ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73 S_SETPC_B64_return $sgpr30_sgpr31 ... @@ -145,17 +661,97 @@ stack: body: | bb.0: liveins: $sgpr30_sgpr31, $vgpr48 - ; CHECK-LABEL: name: locals - ; CHECK: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $m0 = S_MOV_B32 1 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40 - ; CHECK-NEXT: $m0 = S_MOV_B32 1 - ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.2, align 4, addrspace 5) - ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; W32-LABEL: name: locals + ; W32: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 + ; W32-NEXT: {{ $}} + ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W32-NEXT: $m0 = S_MOV_B32 1 + ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 0 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 + ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; W32-NEXT: S_NOP 0, implicit-def $vgpr40 + ; W32-NEXT: $m0 = S_MOV_B32 1 + ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.2, align 4, addrspace 5) + ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; + ; W64-LABEL: name: locals + ; W64: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 + ; W64-NEXT: {{ $}} + ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W64-NEXT: $m0 = S_MOV_B32 1 + ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 0 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 + ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; W64-NEXT: S_NOP 0, implicit-def $vgpr40 + ; W64-NEXT: $m0 = S_MOV_B32 1 + ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.2, align 4, addrspace 5) + ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 SCRATCH_STORE_DWORD_SADDR $vgpr48, %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) SCRATCH_STORE_DWORD_SADDR $vgpr48, %stack.1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) S_NOP 0, implicit-def $vgpr40 @@ -182,13 +778,51 @@ body: | ; W32-LABEL: name: other_regs ; W32: liveins: $sgpr48, $sgpr30_sgpr31, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 ; W32-NEXT: {{ $}} + ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 ; W32-NEXT: $sgpr0 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr41, 512 ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr42, 640 ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr44, 768 ; W32-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 ; W32-NEXT: $m0 = S_MOV_B32 9 ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.4, align 4, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 0 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 96 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 ; W32-NEXT: $vgpr44 = SI_SPILL_S32_TO_VGPR $sgpr48, 0, $vgpr44 ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr43, implicit-def $sgpr22, implicit-def $sgpr48, implicit-def $m0, implicit-def $exec ; W32-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40 @@ -205,13 +839,51 @@ body: | ; W64-LABEL: name: other_regs ; W64: liveins: $sgpr48, $sgpr30_sgpr31, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 ; W64-NEXT: {{ $}} + ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 ; W64-NEXT: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr41, 1024 ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr42, 1280 ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr44, 1536 ; W64-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1 ; W64-NEXT: $m0 = S_MOV_B32 9 ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.4, align 4, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 0 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 192 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 ; W64-NEXT: $vgpr44 = SI_SPILL_S32_TO_VGPR $sgpr48, 0, $vgpr44 ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr43, implicit-def $sgpr22, implicit-def $sgpr48, implicit-def $m0, implicit-def $exec ; W64-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40 @@ -240,11 +912,27 @@ machineFunctionInfo: body: | bb.0: liveins: $sgpr30_sgpr31 - ; CHECK-LABEL: name: entry_func - ; CHECK: liveins: $sgpr30_sgpr31 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45, implicit-def $vgpr51 - ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; W32-LABEL: name: entry_func + ; W32: liveins: $sgpr30_sgpr31 + ; W32-NEXT: {{ $}} + ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr42 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr45 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W32-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45, implicit-def $vgpr51 + ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; + ; W64-LABEL: name: entry_func + ; W64: liveins: $sgpr30_sgpr31 + ; W64-NEXT: {{ $}} + ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr42 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr45 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W64-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45, implicit-def $vgpr51 + ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45, implicit-def $vgpr51 S_SETPC_B64_return $sgpr30_sgpr31 ... @@ -255,29 +943,121 @@ tracksRegLiveness: true machineFunctionInfo: stackPtrOffsetReg: $sgpr32 body: | - ; CHECK-LABEL: name: multiple_basic_blocks - ; CHECK: bb.0: - ; CHECK-NEXT: successors: %bb.1(0x80000000) - ; CHECK-NEXT: liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $m0 = S_MOV_B32 11 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 - ; CHECK-NEXT: S_BRANCH %bb.1 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: bb.1: - ; CHECK-NEXT: successors: %bb.2(0x80000000) - ; CHECK-NEXT: liveins: $vgpr44, $sgpr30_sgpr31 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr43, implicit $vgpr44 - ; CHECK-NEXT: S_BRANCH %bb.2 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: bb.2: - ; CHECK-NEXT: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $m0 = S_MOV_B32 11 - ; CHECK-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; W32-LABEL: name: multiple_basic_blocks + ; W32: bb.0: + ; W32-NEXT: successors: %bb.1(0x80000000) + ; W32-NEXT: liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 + ; W32-NEXT: {{ $}} + ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W32-NEXT: $m0 = S_MOV_B32 11 + ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 0 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 32 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 96 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr72 + ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr73 + ; W32-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 + ; W32-NEXT: S_BRANCH %bb.1 + ; W32-NEXT: {{ $}} + ; W32-NEXT: bb.1: + ; W32-NEXT: successors: %bb.2(0x80000000) + ; W32-NEXT: liveins: $vgpr44, $sgpr30_sgpr31 + ; W32-NEXT: {{ $}} + ; W32-NEXT: S_NOP 0, implicit-def $vgpr43, implicit $vgpr44 + ; W32-NEXT: S_BRANCH %bb.2 + ; W32-NEXT: {{ $}} + ; W32-NEXT: bb.2: + ; W32-NEXT: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 + ; W32-NEXT: {{ $}} + ; W32-NEXT: $m0 = S_MOV_B32 11 + ; W32-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; + ; W64-LABEL: name: multiple_basic_blocks + ; W64: bb.0: + ; W64-NEXT: successors: %bb.1(0x80000000) + ; W64-NEXT: liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 + ; W64-NEXT: {{ $}} + ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 + ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 + ; W64-NEXT: $m0 = S_MOV_B32 11 + ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 0 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 64 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44 + ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 192 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr72 + ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr73 + ; W64-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 + ; W64-NEXT: S_BRANCH %bb.1 + ; W64-NEXT: {{ $}} + ; W64-NEXT: bb.1: + ; W64-NEXT: successors: %bb.2(0x80000000) + ; W64-NEXT: liveins: $vgpr44, $sgpr30_sgpr31 + ; W64-NEXT: {{ $}} + ; W64-NEXT: S_NOP 0, implicit-def $vgpr43, implicit $vgpr44 + ; W64-NEXT: S_BRANCH %bb.2 + ; W64-NEXT: {{ $}} + ; W64-NEXT: bb.2: + ; W64-NEXT: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 + ; W64-NEXT: {{ $}} + ; W64-NEXT: $m0 = S_MOV_B32 11 + ; W64-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 bb.0: liveins: $sgpr30_sgpr31, $vgpr44 S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 diff --git a/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll b/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll index 7a290a322e9e2..ce2a9f6323834 100644 --- a/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll +++ b/llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 -experimental-debug-variable-locations=false < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; Test the behavior of the post-RA soft clause bundler in the presence ; of debug info. The debug info should not interfere with the diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll new file mode 100644 index 0000000000000..47e5ccc12b975 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll @@ -0,0 +1,287 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s + +define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg noundef %dst.coerce, ptr addrspace(1) inreg noundef %src.coerce, i64 inreg noundef %nElts, i64 inreg noundef %redOpArg, i1 inreg noundef %redOpArgIsPtr) #0 !dbg !4 { +; GFX942-LABEL: preload_block_count_x: +; GFX942: .Lfunc_begin0: +; GFX942-NEXT: .file 0 "/" "" +; GFX942-NEXT: .cfi_sections .debug_frame +; GFX942-NEXT: .cfi_startproc +; GFX942-NEXT: ; %bb.5: +; GFX942-NEXT: .loc 0 1 0 prologue_end ; :1:0 +; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 +; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8 +; GFX942-NEXT: s_load_dword s12, s[0:1], 0x28 +; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_branch .LBB0_0 +; GFX942-NEXT: .loc 0 0 0 is_stmt 0 ; :0:0 +; GFX942-NEXT: .Ltmp0: +; GFX942-NEXT: .p2align 8 +; GFX942-NEXT: ; %bb.6: +; GFX942-NEXT: .LBB0_0: ; %entry +; GFX942-NEXT: .cfi_escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 ; +; GFX942-NEXT: .cfi_undefined 16 +; GFX942-NEXT: s_mov_b32 s0, s13 +; GFX942-NEXT: .Ltmp1: +; GFX942-NEXT: ;DEBUG_VALUE: test:var <- [DW_OP_LLVM_poisoned] $sgpr2_sgpr3 +; GFX942-NEXT: .loc 0 1 0 is_stmt 1 ; :1 +; GFX942-NEXT: s_ashr_i32 s13, s12, 31 +; GFX942-NEXT: s_or_b64 s[8:9], s[6:7], s[12:13] +; GFX942-NEXT: s_mov_b32 s8, 0 +; GFX942-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX942-NEXT: s_cbranch_scc0 .LBB0_4 +; GFX942-NEXT: .Ltmp2: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: ;DEBUG_VALUE: test:var <- [DW_OP_LLVM_poisoned] $sgpr2_sgpr3 +; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s12 +; GFX942-NEXT: v_cvt_f32_u32_e32 v1, s13 +; GFX942-NEXT: s_sub_u32 s1, 0, s12 +; GFX942-NEXT: s_subb_u32 s3, 0, s13 +; GFX942-NEXT: .Ltmp3: +; GFX942-NEXT: v_fmamk_f32 v0, v1, 0x4f800000, v0 +; GFX942-NEXT: v_rcp_f32_e32 v0, v0 +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GFX942-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GFX942-NEXT: v_trunc_f32_e32 v1, v1 +; GFX942-NEXT: v_fmamk_f32 v0, v1, 0xcf800000, v0 +; GFX942-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX942-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX942-NEXT: v_readfirstlane_b32 s5, v1 +; GFX942-NEXT: v_readfirstlane_b32 s10, v0 +; GFX942-NEXT: s_mul_i32 s11, s1, s5 +; GFX942-NEXT: s_mul_hi_u32 s15, s1, s10 +; GFX942-NEXT: s_mul_i32 s14, s3, s10 +; GFX942-NEXT: s_add_i32 s11, s15, s11 +; GFX942-NEXT: s_add_i32 s11, s11, s14 +; GFX942-NEXT: s_mul_i32 s16, s1, s10 +; GFX942-NEXT: s_mul_i32 s15, s10, s11 +; GFX942-NEXT: s_mul_hi_u32 s17, s10, s16 +; GFX942-NEXT: s_mul_hi_u32 s14, s10, s11 +; GFX942-NEXT: s_add_u32 s15, s17, s15 +; GFX942-NEXT: s_addc_u32 s14, 0, s14 +; GFX942-NEXT: s_mul_hi_u32 s18, s5, s16 +; GFX942-NEXT: s_mul_i32 s16, s5, s16 +; GFX942-NEXT: s_add_u32 s15, s15, s16 +; GFX942-NEXT: s_mul_hi_u32 s17, s5, s11 +; GFX942-NEXT: s_addc_u32 s14, s14, s18 +; GFX942-NEXT: s_addc_u32 s15, s17, 0 +; GFX942-NEXT: s_mul_i32 s11, s5, s11 +; GFX942-NEXT: s_add_u32 s11, s14, s11 +; GFX942-NEXT: s_addc_u32 s14, 0, s15 +; GFX942-NEXT: s_add_u32 s10, s10, s11 +; GFX942-NEXT: s_addc_u32 s5, s5, s14 +; GFX942-NEXT: s_mul_i32 s11, s1, s5 +; GFX942-NEXT: s_mul_hi_u32 s14, s1, s10 +; GFX942-NEXT: s_add_i32 s11, s14, s11 +; GFX942-NEXT: s_mul_i32 s3, s3, s10 +; GFX942-NEXT: s_add_i32 s11, s11, s3 +; GFX942-NEXT: s_mul_i32 s1, s1, s10 +; GFX942-NEXT: s_mul_hi_u32 s14, s5, s1 +; GFX942-NEXT: s_mul_i32 s15, s5, s1 +; GFX942-NEXT: s_mul_i32 s17, s10, s11 +; GFX942-NEXT: s_mul_hi_u32 s1, s10, s1 +; GFX942-NEXT: s_mul_hi_u32 s16, s10, s11 +; GFX942-NEXT: s_add_u32 s1, s1, s17 +; GFX942-NEXT: s_addc_u32 s16, 0, s16 +; GFX942-NEXT: s_add_u32 s1, s1, s15 +; GFX942-NEXT: s_mul_hi_u32 s3, s5, s11 +; GFX942-NEXT: s_addc_u32 s1, s16, s14 +; GFX942-NEXT: s_addc_u32 s3, s3, 0 +; GFX942-NEXT: s_mul_i32 s11, s5, s11 +; GFX942-NEXT: s_add_u32 s1, s1, s11 +; GFX942-NEXT: s_addc_u32 s3, 0, s3 +; GFX942-NEXT: s_add_u32 s1, s10, s1 +; GFX942-NEXT: s_addc_u32 s3, s5, s3 +; GFX942-NEXT: s_mul_i32 s10, s6, s3 +; GFX942-NEXT: s_mul_hi_u32 s11, s6, s1 +; GFX942-NEXT: s_mul_hi_u32 s5, s6, s3 +; GFX942-NEXT: s_add_u32 s10, s11, s10 +; GFX942-NEXT: s_addc_u32 s5, 0, s5 +; GFX942-NEXT: s_mul_hi_u32 s14, s7, s1 +; GFX942-NEXT: s_mul_i32 s1, s7, s1 +; GFX942-NEXT: s_add_u32 s1, s10, s1 +; GFX942-NEXT: s_mul_hi_u32 s11, s7, s3 +; GFX942-NEXT: s_addc_u32 s1, s5, s14 +; GFX942-NEXT: s_addc_u32 s5, s11, 0 +; GFX942-NEXT: s_mul_i32 s3, s7, s3 +; GFX942-NEXT: s_add_u32 s1, s1, s3 +; GFX942-NEXT: s_addc_u32 s3, 0, s5 +; GFX942-NEXT: s_mul_i32 s5, s12, s3 +; GFX942-NEXT: s_mul_hi_u32 s10, s12, s1 +; GFX942-NEXT: s_add_i32 s5, s10, s5 +; GFX942-NEXT: s_mul_i32 s10, s13, s1 +; GFX942-NEXT: s_add_i32 s5, s5, s10 +; GFX942-NEXT: s_sub_i32 s14, s7, s5 +; GFX942-NEXT: s_mul_i32 s10, s12, s1 +; GFX942-NEXT: s_sub_u32 s15, s6, s10 +; GFX942-NEXT: s_cselect_b64 s[10:11], -1, 0 +; GFX942-NEXT: s_subb_u32 s14, s14, s13 +; GFX942-NEXT: s_sub_u32 s16, s15, s12 +; GFX942-NEXT: s_subb_u32 s14, s14, 0 +; GFX942-NEXT: s_cmp_ge_u32 s14, s13 +; GFX942-NEXT: s_cselect_b32 s17, -1, 0 +; GFX942-NEXT: s_cmp_ge_u32 s16, s12 +; GFX942-NEXT: s_cselect_b32 s16, -1, 0 +; GFX942-NEXT: s_cmp_eq_u32 s14, s13 +; GFX942-NEXT: s_cselect_b32 s14, s16, s17 +; GFX942-NEXT: s_add_u32 s16, s1, 1 +; GFX942-NEXT: s_addc_u32 s17, s3, 0 +; GFX942-NEXT: s_add_u32 s18, s1, 2 +; GFX942-NEXT: s_addc_u32 s19, s3, 0 +; GFX942-NEXT: s_cmp_lg_u32 s14, 0 +; GFX942-NEXT: s_cselect_b32 s14, s18, s16 +; GFX942-NEXT: s_cselect_b32 s16, s19, s17 +; GFX942-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX942-NEXT: s_subb_u32 s5, s7, s5 +; GFX942-NEXT: s_cmp_ge_u32 s5, s13 +; GFX942-NEXT: s_cselect_b32 s10, -1, 0 +; GFX942-NEXT: s_cmp_ge_u32 s15, s12 +; GFX942-NEXT: s_cselect_b32 s11, -1, 0 +; GFX942-NEXT: s_cmp_eq_u32 s5, s13 +; GFX942-NEXT: s_cselect_b32 s5, s11, s10 +; GFX942-NEXT: s_cmp_lg_u32 s5, 0 +; GFX942-NEXT: s_cselect_b32 s11, s16, s3 +; GFX942-NEXT: s_cselect_b32 s10, s14, s1 +; GFX942-NEXT: s_cbranch_execnz .LBB0_3 +; GFX942-NEXT: .LBB0_2: +; GFX942-NEXT: v_cvt_f32_u32_e32 v0, s12 +; GFX942-NEXT: s_sub_i32 s1, 0, s12 +; GFX942-NEXT: s_mov_b32 s11, 0 +; GFX942-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX942-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_readfirstlane_b32 s3, v0 +; GFX942-NEXT: s_mul_i32 s1, s1, s3 +; GFX942-NEXT: s_mul_hi_u32 s1, s3, s1 +; GFX942-NEXT: s_add_i32 s3, s3, s1 +; GFX942-NEXT: s_mul_hi_u32 s1, s6, s3 +; GFX942-NEXT: s_mul_i32 s5, s1, s12 +; GFX942-NEXT: s_sub_i32 s5, s6, s5 +; GFX942-NEXT: s_add_i32 s3, s1, 1 +; GFX942-NEXT: s_sub_i32 s8, s5, s12 +; GFX942-NEXT: s_cmp_ge_u32 s5, s12 +; GFX942-NEXT: s_cselect_b32 s1, s3, s1 +; GFX942-NEXT: s_cselect_b32 s5, s8, s5 +; GFX942-NEXT: s_add_i32 s3, s1, 1 +; GFX942-NEXT: s_cmp_ge_u32 s5, s12 +; GFX942-NEXT: s_cselect_b32 s10, s3, s1 +; GFX942-NEXT: .LBB0_3: +; GFX942-NEXT: s_ashr_i32 s1, s0, 31 +; GFX942-NEXT: s_add_u32 s3, s10, 15 +; GFX942-NEXT: s_addc_u32 s5, s11, 0 +; GFX942-NEXT: s_and_b32 s3, s3, -16 +; GFX942-NEXT: s_mul_i32 s1, s3, s1 +; GFX942-NEXT: s_mul_hi_u32 s8, s3, s0 +; GFX942-NEXT: s_add_i32 s1, s8, s1 +; GFX942-NEXT: s_mul_i32 s5, s5, s0 +; GFX942-NEXT: s_add_i32 s1, s1, s5 +; GFX942-NEXT: s_mul_i32 s3, s3, s0 +; GFX942-NEXT: v_cvt_f64_i32_e32 v[0:1], s1 +; GFX942-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32 +; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s3 +; GFX942-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3] +; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s7 +; GFX942-NEXT: v_ldexp_f64 v[2:3], v[2:3], 32 +; GFX942-NEXT: v_cvt_f64_u32_e32 v[4:5], s6 +; GFX942-NEXT: v_add_f64 v[2:3], v[2:3], v[4:5] +; GFX942-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GFX942-NEXT: v_trunc_f64_e32 v[0:1], v[0:1] +; GFX942-NEXT: s_movk_i32 s0, 0xffe0 +; GFX942-NEXT: v_ldexp_f64 v[2:3], v[0:1], s0 +; GFX942-NEXT: v_floor_f64_e32 v[2:3], v[2:3] +; GFX942-NEXT: v_fmac_f64_e32 v[0:1], 0xc1f00000, v[2:3] +; GFX942-NEXT: v_cvt_u32_f64_e32 v0, v[0:1] +; GFX942-NEXT: v_add_u32_e32 v1, s2, v0 +; GFX942-NEXT: v_add_u32_e32 v0, s4, v0 +; GFX942-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX942-NEXT: v_and_b32_e32 v0, 15, v0 +; GFX942-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX942-NEXT: ;;#ASMSTART +; GFX942-NEXT: ;;#ASMEND +; GFX942-NEXT: s_endpgm +; GFX942-NEXT: .Ltmp4: +; GFX942-NEXT: .LBB0_4: +; GFX942-NEXT: ;DEBUG_VALUE: test:var <- [DW_OP_LLVM_poisoned] $sgpr2_sgpr3 +; GFX942-NEXT: ; implicit-def: $sgpr10_sgpr11 +; GFX942-NEXT: .loc 0 0 0 is_stmt 0 ; :0:0 +; GFX942-NEXT: s_branch .LBB0_2 +entry: + %0 = ptrtoint ptr addrspace(1) %dst.coerce to i64 + %1 = inttoptr i64 %0 to ptr + %2 = ptrtoint ptr addrspace(1) %src.coerce to i64 + #dbg_value(ptr %1, !8, !DIExpression(DIOpArg(0, ptr)), !10) + %3 = tail call noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.x(), !dbg !10 + %4 = tail call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr(), !dbg !10 + %5 = tail call i32 @llvm.amdgcn.workgroup.id.x(), !dbg !10 + %6 = load i32, ptr addrspace(4) %4, align 4, !dbg !10 + %7 = getelementptr inbounds nuw i8, ptr addrspace(4) %4, i64 12, !dbg !10 + %8 = load i16, ptr addrspace(4) %7, align 4, !dbg !10 + %conv.i.i = zext i16 %8 to i32, !dbg !10 + %conv = sext i32 %5 to i64, !dbg !10 + %conv6 = sext i32 %6 to i64, !dbg !10 + %div = udiv i64 %nElts, %conv6, !dbg !10 + %sub.i = add i64 %div, 15, !dbg !10 + %and.i = and i64 %sub.i, -16, !dbg !10 + %mul = mul i64 %and.i, %conv, !dbg !10 + %add8 = add nsw i32 %5, 1, !dbg !10 + %conv9 = sext i32 %add8 to i64, !dbg !10 + %mul13 = mul i64 %and.i, %conv9, !dbg !10 + %conv.i = sitofp i64 %mul to double, !dbg !10 + %conv1.i = uitofp i64 %nElts to double, !dbg !10 + %9 = tail call contract noundef double @llvm.minnum.f64(double %conv.i, double %conv1.i), !dbg !10 + %conv15 = fptosi double %9 to i64, !dbg !10 + %conv.i43 = sitofp i64 %mul13 to double, !dbg !10 + %10 = tail call contract noundef double @llvm.minnum.f64(double %conv.i43, double %conv1.i), !dbg !10 + %add.ptr18 = getelementptr inbounds i8, ptr %1, i64 %conv15, !dbg !10 + %rem = and i64 %redOpArg, 1, !dbg !10 + %cmp.not = icmp eq i64 %rem, 0, !dbg !10 + %rem21 = and i64 %redOpArg, 2, !dbg !10 + %cmp22.not = icmp eq i64 %rem21, 0, !dbg !10 + %rem26 = and i64 %redOpArg, 4, !dbg !10 + %cmp27.not = icmp eq i64 %rem26, 0, !dbg !10 + %11 = inttoptr i64 %redOpArg to ptr, !dbg !10 + %12 = load i64, ptr %11, align 8, !dbg !10 + %conv17 = fptosi double %10 to i64, !dbg !10 + %sub = sub nsw i64 %conv17, %conv15, !dbg !10 + %rem.i.i5354 = and i32 %3, 63, !dbg !10 + %cmp.i.i.not = icmp eq i32 %rem.i.i5354, 0, !dbg !10 + %13 = add i64 %2, %conv15, !dbg !10 + %14 = ptrtoint ptr %add.ptr18 to i64, !dbg !10 + %15 = or i64 %13, %14, !dbg !10 + %16 = and i64 %15, 15, !dbg !10 + %and1583.i.i = icmp ne i64 %16, 0, !dbg !10 + %17 = zext i1 %and1583.i.i to i32, !dbg !10 + %18 = tail call i32 asm sideeffect "", "=v,0"(i32 %17) #9, !dbg !10 + %19 = icmp ne i32 %18, 0, !dbg !10 + %20 = tail call i64 @llvm.amdgcn.ballot.i64(i1 %19), !dbg !10 + %.not.i.i = icmp eq i64 %20, 0, !dbg !10 + %div1.i.i.i555659 = lshr i32 %3, 6, !dbg !10 + %div8.i.i.i = sdiv i64 %sub, 4096, !dbg !10 + %mul9.i.i.i = shl nsw i64 %div8.i.i.i, 12, !dbg !10 + %sub12.i.i.i = sub nsw i64 %sub, %mul9.i.i.i, !dbg !10 + %conv13.i.i.i = zext nneg i32 %div1.i.i.i555659 to i64, !dbg !10 + %sub14.i.i.i = sub nsw i64 %div8.i.i.i, %conv13.i.i.i, !dbg !10 + %cmp30399.i.i.i = icmp sgt i64 %sub14.i.i.i, 0, !dbg !10 + ret void +} + +attributes #0 = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} +!0 = distinct !DICompileUnit(language: DW_LANG_OpenCL, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug) +!1 = !DIFile(filename: "", directory: "/") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !5, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) +!5 = !DISubroutineType(cc: DW_CC_LLVM_DeviceKernel, types: !6) +!6 = !{null} +!7 = !{i32 1024, i32 1, i32 1} +!8 = !DILocalVariable(name: "var", arg: 1, scope: !4, file: !1, line: 1, type: !9) +!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 64) +!10 = !DILocation(line: 1, scope: !4) diff --git a/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir b/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir index 168d63d3a95b9..37c8788d8d691 100644 --- a/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir +++ b/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir @@ -20,6 +20,9 @@ body: | ; GCN-LABEL: name: preserve_scratch_vgpr_inactive_lanes ; GCN: liveins: $sgpr35, $vgpr0, $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr0 ; GCN-NEXT: $sgpr35 = S_MOV_B32 5 ; GCN-NEXT: $sgpr35 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0 diff --git a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll index f4a9e7e8f2759..4b03896043dbb 100644 --- a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll +++ b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll @@ -17,6 +17,13 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 { ; GFX906-NEXT: s_mov_b64 exec, -1 ; GFX906-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill ; GFX906-NEXT: s_mov_b64 exec, s[18:19] +; GFX906-NEXT: v_writelane_b32 v41, s16, 4 +; GFX906-NEXT: v_writelane_b32 v41, s34, 2 +; GFX906-NEXT: v_writelane_b32 v41, s35, 3 +; GFX906-NEXT: s_addk_i32 s32, 0x2800 +; GFX906-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX906-NEXT: v_writelane_b32 v41, s30, 0 +; GFX906-NEXT: v_writelane_b32 v41, s31, 1 ; GFX906-NEXT: s_mov_b32 s21, s15 ; GFX906-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane ; GFX906-NEXT: s_mov_b32 s22, s14 @@ -30,17 +37,10 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 { ; GFX906-NEXT: v_writelane_b32 v39, s26, 4 ; GFX906-NEXT: v_writelane_b32 v39, s27, 5 ; GFX906-NEXT: v_writelane_b32 v39, s8, 6 -; GFX906-NEXT: v_writelane_b32 v41, s16, 4 ; GFX906-NEXT: v_writelane_b32 v39, s9, 7 -; GFX906-NEXT: v_writelane_b32 v41, s34, 2 ; GFX906-NEXT: v_writelane_b32 v39, s6, 8 -; GFX906-NEXT: v_writelane_b32 v41, s35, 3 ; GFX906-NEXT: v_writelane_b32 v39, s7, 9 -; GFX906-NEXT: v_writelane_b32 v41, s30, 0 ; GFX906-NEXT: v_writelane_b32 v39, s4, 10 -; GFX906-NEXT: s_addk_i32 s32, 0x2800 -; GFX906-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GFX906-NEXT: v_writelane_b32 v41, s31, 1 ; GFX906-NEXT: v_mov_b32_e32 v32, v31 ; GFX906-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX906-NEXT: s_nop 0 @@ -338,8 +338,8 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 { ; GFX906-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:136 ; 4-byte Folded Reload ; GFX906-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:140 ; 4-byte Folded Reload ; GFX906-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:144 ; 4-byte Folded Reload -; GFX906-NEXT: v_readlane_b32 s31, v41, 1 ; GFX906-NEXT: v_readlane_b32 s30, v41, 0 +; GFX906-NEXT: v_readlane_b32 s31, v41, 1 ; GFX906-NEXT: s_mov_b32 s32, s33 ; GFX906-NEXT: v_readlane_b32 s4, v41, 4 ; GFX906-NEXT: v_readlane_b32 s34, v41, 2 @@ -388,21 +388,14 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 { ; GFX908-NEXT: s_addk_i32 s32, 0x2c00 ; GFX908-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX908-NEXT: s_mov_b64 s[16:17], exec -; GFX908-NEXT: s_mov_b64 exec, 1 +; GFX908-NEXT: s_mov_b64 exec, 3 ; GFX908-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:168 ; GFX908-NEXT: v_writelane_b32 v2, s30, 0 +; GFX908-NEXT: v_writelane_b32 v2, s31, 1 ; GFX908-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX908-NEXT: buffer_load_dword v2, off, s[0:3], s33 offset:168 ; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_mov_b64 exec, s[16:17] -; GFX908-NEXT: s_mov_b64 s[16:17], exec -; GFX908-NEXT: s_mov_b64 exec, 1 -; GFX908-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:168 -; GFX908-NEXT: v_writelane_b32 v2, s31, 0 -; GFX908-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; GFX908-NEXT: buffer_load_dword v2, off, s[0:3], s33 offset:168 -; GFX908-NEXT: s_waitcnt vmcnt(0) -; GFX908-NEXT: s_mov_b64 exec, s[16:17] ; GFX908-NEXT: s_mov_b32 s21, s15 ; GFX908-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane ; GFX908-NEXT: s_mov_b32 s22, s14 @@ -735,20 +728,12 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 { ; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: flat_store_dwordx4 v[0:1], v[2:5] ; GFX908-NEXT: s_waitcnt vmcnt(0) -; GFX908-NEXT: s_mov_b64 exec, 1 -; GFX908-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:168 -; GFX908-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload -; GFX908-NEXT: s_waitcnt vmcnt(0) -; GFX908-NEXT: v_readlane_b32 s31, v0, 0 -; GFX908-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:168 -; GFX908-NEXT: s_waitcnt vmcnt(0) -; GFX908-NEXT: s_mov_b64 exec, s[4:5] -; GFX908-NEXT: s_mov_b64 s[4:5], exec -; GFX908-NEXT: s_mov_b64 exec, 1 +; GFX908-NEXT: s_mov_b64 exec, 3 ; GFX908-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:168 ; GFX908-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: v_readlane_b32 s30, v0, 0 +; GFX908-NEXT: v_readlane_b32 s31, v0, 1 ; GFX908-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:168 ; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_mov_b64 exec, s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll b/llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll index b1fc76f457ece..93f43b274e28d 100644 --- a/llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll +++ b/llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll @@ -2,16 +2,22 @@ ; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto" -print-pipeline-passes %s -o - | FileCheck %s ; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto" -print-pipeline-passes %s -o - | FileCheck %s ; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto" -print-pipeline-passes %s -o - | FileCheck %s +; RUN: opt -mtriple=amdgcn--amdhsa -S -O0 -print-pipeline-passes %s -o - | FileCheck --check-prefix=O0 %s +; RUN: opt -mtriple=amdgcn--amdhsa -S -O1 -print-pipeline-passes %s -o - | FileCheck %s +; RUN: opt -mtriple=amdgcn--amdhsa -S -O2 -print-pipeline-passes %s -o - | FileCheck %s +; RUN: opt -mtriple=amdgcn--amdhsa -S -O3 -print-pipeline-passes %s -o - | FileCheck %s ; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto-pre-link" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s ; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto-pre-link" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s ; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto-pre-link" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s ; RUN: opt -mtriple=amdgcn--amdhsa -S -passes="lto-pre-link" -print-pipeline-passes -amdgpu-internalize-symbols %s -o - | FileCheck --check-prefix=PRE %s - +; CHECK: amdgpu-expand-feature-predicates ; CHECK: amdgpu-attributor +; O0: amdgpu-expand-feature-predicates ; O0-NOT: amdgpu-attributor +; PRE: amdgpu-expand-feature-predicates ; PRE-NOT: internalize ; PRE-NOT: amdgpu-attributor ; PRE-NOT: printfToRuntime diff --git a/llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll b/llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll index bf417b211826a..ba460fc7b4266 100644 --- a/llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll +++ b/llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll @@ -14,6 +14,8 @@ define hidden void @_Z9base_casev() #0 !dbg !6 { ; CHECK-NEXT: .cfi_sections .debug_frame ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: .Ltmp0: ; CHECK-NEXT: .loc 0 7 3 prologue_end ; file.cpp:7:3 diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll index f9bb809e76763..9c079c824acb6 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll @@ -8,9 +8,9 @@ define amdgpu_kernel void @simple_users_scores() { ; CHECK-LABEL: define amdgpu_kernel void @simple_users_scores( ; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[SIMPLEUSER:%.*]] = alloca [4 x i64], align 4, addrspace(5) ; CHECK-NEXT: [[MANYUSERS:%.*]] = alloca [64 x i64], align 4, addrspace(5) -; CHECK-NEXT: [[SIMPLEUSER:%.*]] = freeze <4 x i64> poison -; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> [[SIMPLEUSER]], i64 42, i32 0 +; CHECK-NEXT: store i64 42, ptr addrspace(5) [[SIMPLEUSER]], align 8 ; CHECK-NEXT: [[MANYUSERS_1:%.*]] = getelementptr i8, ptr addrspace(5) [[MANYUSERS]], i64 2 ; CHECK-NEXT: [[V0:%.*]] = load i8, ptr addrspace(5) [[MANYUSERS_1]], align 1 ; CHECK-NEXT: [[V0_EXT:%.*]] = zext i8 [[V0]] to i64 diff --git a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll index e29f09dcac024..54db72c802986 100644 --- a/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll +++ b/llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -experimental-debug-variable-locations=false < %s | FileCheck %s %struct.A = type { [100 x i32] } @@ -14,6 +14,9 @@ define hidden void @ptr_arg_split_subregs(ptr %arg1) #0 !dbg !9 { ; CHECK-NEXT: .cfi_sections .debug_frame ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; CHECK-NEXT: .cfi_undefined 2562 ; CHECK-NEXT: ;DEBUG_VALUE: ptr_arg_split_subregs:a <- [DW_OP_LLVM_fragment 32 32] [$vgpr1+0] ; CHECK-NEXT: ;DEBUG_VALUE: ptr_arg_split_subregs:a <- [DW_OP_LLVM_fragment 0 32] [$vgpr0+0] ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -43,6 +46,10 @@ define hidden void @ptr_arg_split_reg_mem(<30 x i32>, ptr %arg2) #0 !dbg !25 { ; CHECK-NEXT: .loc 1 10 0 ; example.cpp:10:0 ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; CHECK-NEXT: .cfi_undefined 2560 +; CHECK-NEXT: .cfi_undefined 2591 ; CHECK-NEXT: ;DEBUG_VALUE: ptr_arg_split_reg_mem:b <- [$vgpr30+0] ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 @@ -69,6 +76,11 @@ define hidden void @ptr_arg_in_memory(<32 x i32>, ptr %arg3) #0 !dbg !31 { ; CHECK-NEXT: .loc 1 15 0 ; example.cpp:15:0 ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; CHECK-NEXT: .cfi_undefined 2560 +; CHECK-NEXT: .cfi_undefined 2561 +; CHECK-NEXT: .cfi_undefined 2562 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 diff --git a/llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir b/llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir index e4cbae66d47fa..7f12571a6bdb4 100644 --- a/llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir @@ -36,6 +36,8 @@ body: | ; GFX908-LABEL: name: regalloc_introduces_s_to_a_copy ; GFX908: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47, $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63, $vgpr32_vgpr33_vgpr34_vgpr35, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr7 ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX908-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $sgpr7, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908-NEXT: renamable $vgpr34 = GLOBAL_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll b/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll index f847d669c6063..0e90648260194 100644 --- a/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll +++ b/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals --version 3 ; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-attributor,amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefixes=CHECK,TABLE %s +; this needs rework downstream ; FIXME: Work around update_test_checks bug in constant expression handling by manually deleting part of the last global pattern @function.lds = addrspace(3) global i16 poison diff --git a/llvm/test/CodeGen/AMDGPU/returnaddress_cfi.ll b/llvm/test/CodeGen/AMDGPU/returnaddress_cfi.ll new file mode 100644 index 0000000000000..dfd8604671ea8 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/returnaddress_cfi.ll @@ -0,0 +1,177 @@ +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -O0 -verify-machineinstrs < %s | FileCheck %s + +; XFAIL: * + +; Function Attrs: convergent mustprogress nounwind +define hidden void @_ZL3barv_spill_RA_to_vgpr() #0 { +; CHECK-LABEL: _ZL3barv_spill_RA_to_vgpr: +; CHECK: .Lfunc_begin0: +; CHECK-NEXT: .cfi_sections .debug_frame +; CHECK-NEXT: .cfi_startproc +; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_escape 0x10, 0x10, 0x08, 0x90, 0x3e, 0x93, 0x04, 0x90, 0x3f, 0x93, 0x04 ; +; CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_or_saveexec_b64 s[16:17], -1 +; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset 2600, 1228 + +; CHECK-NEXT: s_mov_b64 exec, s[16:17] + +; CHECK: v_writelane_b32 v40, s30, 32 +; CHECK-NEXT: v_writelane_b32 v40, s31, 33 +; CHECK-NEXT: .cfi_escape 0x10, 0x10, 0x0e, 0x90, 0xa8, 0x14, 0x9d, 0x20, 0x80, 0x08, 0x90, 0xa8, 0x14, 0x9d, 0x20, 0xa0, 0x08 ; +; CHECK: ;;#ASMSTART +; CHECK-NEXT: ; clobber nonpreserved and 32 CSR SGPRs +; CHECK-NEXT: ;;#ASMEND + +; CHECK: ;;#ASMSTART +; CHECK-NEXT: ; clobber all VGPRs except v40 +; CHECK-NEXT: ;;#ASMEND +; CHECK: s_getpc_b64 s[16:17] +; CHECK-NEXT: s_add_u32 s16, s16, _ZL13sleep_foreverv@gotpcrel32@lo+4 +; CHECK-NEXT: s_addc_u32 s17, s17, _ZL13sleep_foreverv@gotpcrel32@hi+12 +; CHECK: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] + +; CHECK-DAG: v_readlane_b32 s30, v40, 32 +; CHECK-DAG: v_readlane_b32 s31, v40, 33 + +; CHECK: s_or_saveexec_b64 s[4:5], -1 +; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; CHECK-NEXT: s_mov_b64 exec, s[4:5] +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +entry: + call void asm sideeffect "; clobber nonpreserved and 32 CSR SGPRs", + "~{s4},~{s5},~{s6},~{s7},~{s8},~{s9} + ,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19} + ,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29} + ,~{s34},~{s35},~{s36},~{s37},~{s38},~{s39} + ,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49} + ,~{s50},~{s51},~{s52},~{s53},~{s54},~{s55},~{s56},~{s57},~{s58},~{s59} + ,~{s60},~{s61},~{s62},~{s63},~{s64},~{s65} + ,~{vcc}"() + + call void asm sideeffect "; clobber all VGPRs except v40", + "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9} + ,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19} + ,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29} + ,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38},~{v39} + ,~{v41},~{v42},~{v43},~{v44},~{v45},~{v46},~{v47},~{v48},~{v49} + ,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59} + ,~{v60},~{v61},~{v62},~{v63},~{v64},~{v65},~{v66},~{v67},~{v68},~{v69} + ,~{v70},~{v71},~{v72},~{v73},~{v74},~{v75},~{v76},~{v77},~{v78},~{v79} + ,~{v80},~{v81},~{v82},~{v83},~{v84},~{v85},~{v86},~{v87},~{v88},~{v89} + ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} + ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109} + ,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119} + ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}"() + + call void @_ZL13sleep_foreverv() + ret void +} + +; Function Attrs: convergent mustprogress nounwind +define hidden void @_ZL3barv_spill_RA_to_memory() #0 { +; CHECK-LABEL: _ZL3barv_spill_RA_to_memory: +; CHECK: .Lfunc_begin1: +; CHECK-NEXT: .cfi_startproc +; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_escape 0x10, 0x10, 0x08, 0x90, 0x3e, 0x93, 0x04, 0x90, 0x3f, 0x93, 0x04 ; +; CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, s33 +; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset 65, 24320 +; CHECK-NEXT: s_mov_b32 s33, s32 +; CHECK-NEXT: .cfi_def_cfa_register 65 +; CHECK-NEXT: s_add_i32 s32, s32, 0x6400 + +; CHECK: s_waitcnt vmcnt(0) +; CHECK: s_mov_b64 exec, s[20:21] +; CHECK: s_mov_b64 s[18:19], exec +; CHECK: s_mov_b64 exec, 1 +; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:384 +; CHECK-NEXT: v_writelane_b32 v0, s14, 0 +; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset 16, 23808 +; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:384 + +; CHECK: ;;#ASMSTART +; CHECK-NEXT: ; clobber nonpreserved and 32 CSR SGPRs +; CHECK-NEXT: ;;#ASMEND + +; CHECK: ;;#ASMSTART +; CHECK-NEXT: ; clobber all VGPRs +; CHECK-NEXT: ;;#ASMEND + +; CHECK: s_getpc_b64 s[16:17] +; CHECK-NEXT: s_add_u32 s16, s16, _ZL13sleep_foreverv@gotpcrel32@lo+4 +; CHECK-NEXT: s_addc_u32 s17, s17, _ZL13sleep_foreverv@gotpcrel32@hi+12 +; CHECK-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 +; CHECK: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] + +; CHECK-NEXT: s_mov_b64 s[4:5], exec +; CHECK-NEXT: s_mov_b64 exec, 3 +; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:384 +; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:372 ; 4-byte Folded Reload +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: v_readlane_b32 s30, v0, 0 +; CHECK-NEXT: v_readlane_b32 s31, v0, 1 +; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:384 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_mov_b64 exec, s[4:5] + +; CHECK: s_add_i32 s32, s32, 0xffff9c00 +; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: v_readfirstlane_b32 s33, v0 +; CHECK-NEXT: .cfi_def_cfa_register 64 +; CHECK-NEXT: s_setpc_b64 s[30:31] +entry: + call void asm sideeffect "; clobber nonpreserved and 32 CSR SGPRs", + "~{s4},~{s5},~{s6},~{s7},~{s8},~{s9} + ,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19} + ,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29} + ,~{s34},~{s35},~{s36},~{s37},~{s38},~{s39} + ,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49} + ,~{s50},~{s51},~{s52},~{s53},~{s54},~{s55},~{s56},~{s57},~{s58},~{s59} + ,~{s60},~{s61},~{s62},~{s63},~{s64},~{s65} + ,~{vcc}"() + + call void asm sideeffect "; clobber all VGPRs", + "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9} + ,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19} + ,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29} + ,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38},~{v39} + ,~{v40},~{v41},~{v42},~{v43},~{v44},~{v45},~{v46},~{v47},~{v48},~{v49} + ,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59} + ,~{v60},~{v61},~{v62},~{v63},~{v64},~{v65},~{v66},~{v67},~{v68},~{v69} + ,~{v70},~{v71},~{v72},~{v73},~{v74},~{v75},~{v76},~{v77},~{v78},~{v79} + ,~{v80},~{v81},~{v82},~{v83},~{v84},~{v85},~{v86},~{v87},~{v88},~{v89} + ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} + ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109} + ,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119} + ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}"() + + call void @_ZL13sleep_foreverv() + ret void +} + +; Function Attrs: convergent nounwind +declare void @_ZL13sleep_foreverv() #0 + +attributes #0 = { nounwind "frame-pointer"="all" } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!1638, !1639, !1640, !1641} +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_11, file: !1, producer: "clang version 13.0.0)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "lane-info.cpp", directory: "/tmp", checksumkind: CSK_MD5, checksum: "4ab9b75a30baffdf0f6f536a80e3e382") +!371 = !DISubroutineType(types: !372) +!372 = !{null} +!1638 = !{i32 7, !"Dwarf Version", i32 5} +!1639 = !{i32 2, !"Debug Info Version", i32 3} +!1640 = !{i32 1, !"wchar_size", i32 4} +!1641 = !{i32 7, !"PIC Level", i32 1} diff --git a/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll b/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll index dba10f19eb500..1260e147fbc53 100644 --- a/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll +++ b/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll @@ -11,8 +11,8 @@ define void @test_remat_s_getpc_b64() { ; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: v_writelane_b32 v2, s30, 0 -; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: v_writelane_b32 v2, s31, 1 +; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: ;;#ASMSTART @@ -20,9 +20,9 @@ define void @test_remat_s_getpc_b64() { ; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_readlane_b32 s30, v2, 0 ; GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: v_readlane_b32 s31, v2, 1 -; GFX9-NEXT: v_readlane_b32 s30, v2, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] @@ -36,17 +36,16 @@ define void @test_remat_s_getpc_b64() { ; GFX11-NEXT: scratch_store_b32 off, v2, s32 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: v_writelane_b32 v2, s30, 0 +; GFX11-NEXT: v_writelane_b32 v2, s31, 1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_writelane_b32 v2, s31, 1 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_getpc_b64 s[0:1] -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_readlane_b32 s30, v2, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_readlane_b32 s31, v2, 1 -; GFX11-NEXT: v_readlane_b32 s30, v2, 0 ; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_load_b32 v2, off, s32 ; 4-byte Folded Reload @@ -66,21 +65,21 @@ define void @test_remat_s_getpc_b64() { ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: s_mov_b32 exec_lo, s0 ; GFX12-NEXT: v_writelane_b32 v2, s30, 0 +; GFX12-NEXT: v_writelane_b32 v2, s31, 1 ; GFX12-NEXT: s_getpc_b64 s[0:1] ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: s_sext_i32_i16 s1, s1 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ;;#ASMEND -; GFX12-NEXT: v_writelane_b32 v2, s31, 1 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ;;#ASMEND ; GFX12-NEXT: s_getpc_b64 s[0:1] +; GFX12-NEXT: v_readlane_b32 s30, v2, 0 ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: s_sext_i32_i16 s1, s1 ; GFX12-NEXT: s_wait_alu 0xfffe ; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-NEXT: v_readlane_b32 s31, v2, 1 -; GFX12-NEXT: v_readlane_b32 s30, v2, 0 ; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off ; GFX12-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX12-NEXT: scratch_load_b32 v2, off, s32 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir b/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir index 592e0f0cf0c24..9b226df530eec 100644 --- a/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir +++ b/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir @@ -15,6 +15,12 @@ body: | ; CHECK-LABEL: name: same_slot_agpr_sgpr ; CHECK: liveins: $agpr0, $agpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; CHECK-NEXT: $sgpr4_sgpr5 = IMPLICIT_DEF @@ -48,6 +54,12 @@ body: | ; CHECK-LABEL: name: diff_slot_agpr_sgpr ; CHECK: liveins: $agpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; CHECK-NEXT: $sgpr4_sgpr5 = IMPLICIT_DEF @@ -79,6 +91,10 @@ body: | ; CHECK-LABEL: name: dead_vgpr_slot ; CHECK: liveins: $agpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; CHECK-NEXT: S_ENDPGM 0 diff --git a/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll b/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll index b2770f337fdb4..4a6d7b1f50faa 100644 --- a/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll +++ b/llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll @@ -218,7 +218,7 @@ define amdgpu_ps float @_amdgpu_ps_main() { ; GFX1150-NEXT: s_mov_b32 s3, s0 ; GFX1150-NEXT: s_buffer_load_b64 s[0:1], s[0:3], 0x0 ; GFX1150-NEXT: s_waitcnt lgkmcnt(0) -; GFX1150-NEXT: s_fmac_f32 s0, s1, 4.0 +; GFX1150-NEXT: s_fmamk_f32 s0, s1, 0x40800000, s0 ; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; GFX1150-NEXT: v_mov_b32_e32 v0, s0 ; GFX1150-NEXT: ; return to shader part epilog @@ -232,7 +232,7 @@ define amdgpu_ps float @_amdgpu_ps_main() { ; GFX12-NEXT: s_mov_b32 s3, s0 ; GFX12-NEXT: s_buffer_load_b64 s[0:1], s[0:3], 0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: s_fmac_f32 s0, s1, 4.0 +; GFX12-NEXT: s_fmamk_f32 s0, s1, 0x40800000, s0 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll b/llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll index 0d25bc97ff775..63bc4f5c38445 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll +++ b/llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -amdgpu-s-branch-bits=5 -amdgpu-long-branch-factor=0 < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -amdgpu-s-branch-bits=5 -amdgpu-long-branch-factor=0 -amdgpu-use-amdgpu-trackers=1 < %s | FileCheck --check-prefix=GCN-GCNTRACKERS %s - ; CHECK-LABEL: {{^}}spill: ; GCN: NumSgprs: 104 ; GCN-GCNTRACKERS: NumSgprs: 104 diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir index 520717391b596..8b87f5be52411 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir @@ -1,4 +1,3 @@ -# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR_SPILL %s # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -verify-machineinstrs --start-before=si-lower-sgpr-spills --stop-after=prologepilog -o - %s | FileCheck -check-prefix=PEI %s # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -passes=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR_SPILL %s @@ -59,6 +58,8 @@ body: | ; PEI: bb.0: ; PEI-NEXT: successors: %bb.1(0x80000000) ; PEI-NEXT: {{ $}} + ; PEI-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; PEI-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; PEI-NEXT: renamable $sgpr10 = IMPLICIT_DEF ; PEI-NEXT: $vgpr0 = IMPLICIT_DEF ; PEI-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, killed $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir index 925984b15367d..2107c7bd527fc 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir @@ -28,86 +28,203 @@ body: | ; GCN-LABEL: name: test_main ; GCN: bb.0: ; GCN-NEXT: successors: %bb.1(0x80000000) - ; GCN-NEXT: liveins: $vcc_hi, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $sgpr102, $sgpr103, $vgpr0 + ; GCN-NEXT: liveins: $vcc_hi, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $sgpr102, $sgpr103, $vgpr0, $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GCN-NEXT: $vcc_hi = frame-setup COPY $sgpr33 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, ; GCN-NEXT: $sgpr33 = frame-setup COPY $sgpr32 ; GCN-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr5, $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr1, 0 + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr2, 128 + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr3, 256 + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr4, 384 + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr5, $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr5, 512 ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 ; GCN-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24, implicit-def dead $scc ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr4, $vgpr2, 0, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr5, $vgpr2, 1, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr6, 2, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr6, $vgpr2, 2, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr7, 3, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr7, $vgpr2, 3, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr8, 4, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr8, $vgpr2, 4, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr9, 5, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr9, $vgpr2, 5, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr10, 6, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr10, $vgpr2, 6, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr11, 7, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr11, $vgpr2, 7, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr12, 8, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr12, $vgpr2, 8, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr13, 9, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr13, $vgpr2, 9, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr14, 10, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr14, $vgpr2, 10, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr15, 11, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr15, $vgpr2, 11, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr16, 12, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr16, $vgpr2, 12, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr17, 13, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr17, $vgpr2, 13, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr18, 14, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr18, $vgpr2, 14, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr19, 15, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr19, $vgpr2, 15, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr20, 16, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr20, $vgpr2, 16, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr21, 17, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr21, $vgpr2, 17, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr22, 18, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr22, $vgpr2, 18, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr23, 19, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr23, $vgpr2, 19, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr24, 20, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr24, $vgpr2, 20, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr25, 21, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr25, $vgpr2, 21, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr26, 22, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr26, $vgpr2, 22, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr27, 23, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr27, $vgpr2, 23, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr28, 24, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr28, $vgpr2, 24, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr29, 25, $vgpr2 - ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr30, 26, $vgpr2 - ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr31, 27, $vgpr2 - ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr64, 28, $vgpr2 - ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr65, 29, $vgpr2 - ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr66, 30, $vgpr2 - ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr67, 31, $vgpr2 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr68, 0, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr69, 1, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr70, 2, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr71, 3, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr72, 4, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr73, 5, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr74, 6, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr75, 7, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr76, 8, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr77, 9, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr78, 10, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr79, 11, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr80, 12, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr81, 13, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr82, 14, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr83, 15, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr84, 16, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr85, 17, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr86, 18, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr87, 19, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr88, 20, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr89, 21, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr90, 22, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr91, 23, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr92, 24, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr93, 25, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr94, 26, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr95, 27, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr96, 28, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr97, 29, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr98, 30, $vgpr3 - ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr99, 31, $vgpr3 - ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr100, 0, $vgpr4 - ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr101, 1, $vgpr4 - ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr102, 2, $vgpr4 - ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr103, 3, $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr29, $vgpr2, 25, 32 + ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr64, 26, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr2, 26, 32 + ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr65, 27, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr2, 27, 32 + ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr66, 28, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr2, 28, 32 + ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr67, 29, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr2, 29, 32 + ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr68, 30, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr2, 30, 32 + ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr69, 31, $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr69, $vgpr2, 31, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr70, 0, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr70, $vgpr3, 0, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr71, 1, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr71, $vgpr3, 1, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr72, 2, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr72, $vgpr3, 2, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr73, 3, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr73, $vgpr3, 3, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr74, 4, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr74, $vgpr3, 4, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr75, 5, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr75, $vgpr3, 5, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr76, 6, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr76, $vgpr3, 6, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr77, 7, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr77, $vgpr3, 7, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr78, 8, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr78, $vgpr3, 8, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr79, 9, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr79, $vgpr3, 9, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr80, 10, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr80, $vgpr3, 10, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr81, 11, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr81, $vgpr3, 11, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr82, 12, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr82, $vgpr3, 12, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr83, 13, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr83, $vgpr3, 13, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr84, 14, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr84, $vgpr3, 14, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr85, 15, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr85, $vgpr3, 15, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr86, 16, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr86, $vgpr3, 16, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr87, 17, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr87, $vgpr3, 17, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr88, 18, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr88, $vgpr3, 18, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr89, 19, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr89, $vgpr3, 19, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr90, 20, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr90, $vgpr3, 20, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr91, 21, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr91, $vgpr3, 21, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr92, 22, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr92, $vgpr3, 22, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr93, 23, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr93, $vgpr3, 23, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr94, 24, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr94, $vgpr3, 24, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr95, 25, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr95, $vgpr3, 25, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr96, 26, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr96, $vgpr3, 26, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr97, 27, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr97, $vgpr3, 27, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr98, 28, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr98, $vgpr3, 28, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr99, 29, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr99, $vgpr3, 29, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr100, 30, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr100, $vgpr3, 30, 32 + ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr101, 31, $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr101, $vgpr3, 31, 32 + ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr102, 0, $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr102, $vgpr4, 0, 32 + ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr103, 1, $vgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr103, $vgpr4, 1, 32 + ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr30, 2, $vgpr4, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31 + ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr31, 3, $vgpr4, implicit $sgpr30_sgpr31 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr4, 2, 32, $vgpr4, 3, 32 ; GCN-NEXT: $sgpr22 = IMPLICIT_DEF ; GCN-NEXT: $vgpr5 = IMPLICIT_DEF ; GCN-NEXT: $vgpr5 = SI_SPILL_S32_TO_VGPR $sgpr22, 0, killed $vgpr5 @@ -130,48 +247,48 @@ body: | ; GCN-NEXT: bb.3: ; GCN-NEXT: liveins: $vcc_hi ; GCN-NEXT: {{ $}} - ; GCN-NEXT: $sgpr103 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 3 - ; GCN-NEXT: $sgpr102 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 2 - ; GCN-NEXT: $sgpr101 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 1 - ; GCN-NEXT: $sgpr100 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 0 - ; GCN-NEXT: $sgpr99 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 31 - ; GCN-NEXT: $sgpr98 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 30 - ; GCN-NEXT: $sgpr97 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 29 - ; GCN-NEXT: $sgpr96 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 28 - ; GCN-NEXT: $sgpr95 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 27 - ; GCN-NEXT: $sgpr94 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 26 - ; GCN-NEXT: $sgpr93 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 25 - ; GCN-NEXT: $sgpr92 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 24 - ; GCN-NEXT: $sgpr91 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 23 - ; GCN-NEXT: $sgpr90 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 22 - ; GCN-NEXT: $sgpr89 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 21 - ; GCN-NEXT: $sgpr88 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 20 - ; GCN-NEXT: $sgpr87 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 19 - ; GCN-NEXT: $sgpr86 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 18 - ; GCN-NEXT: $sgpr85 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 17 - ; GCN-NEXT: $sgpr84 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 16 - ; GCN-NEXT: $sgpr83 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 15 - ; GCN-NEXT: $sgpr82 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 14 - ; GCN-NEXT: $sgpr81 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 13 - ; GCN-NEXT: $sgpr80 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 12 - ; GCN-NEXT: $sgpr79 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 11 - ; GCN-NEXT: $sgpr78 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 10 - ; GCN-NEXT: $sgpr77 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 9 - ; GCN-NEXT: $sgpr76 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 8 - ; GCN-NEXT: $sgpr75 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 7 - ; GCN-NEXT: $sgpr74 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 6 - ; GCN-NEXT: $sgpr73 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 5 - ; GCN-NEXT: $sgpr72 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 4 - ; GCN-NEXT: $sgpr71 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 3 - ; GCN-NEXT: $sgpr70 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 2 - ; GCN-NEXT: $sgpr69 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 1 - ; GCN-NEXT: $sgpr68 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 0 - ; GCN-NEXT: $sgpr67 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 31 - ; GCN-NEXT: $sgpr66 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 30 - ; GCN-NEXT: $sgpr65 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 29 - ; GCN-NEXT: $sgpr64 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 28 - ; GCN-NEXT: $sgpr31 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 27 - ; GCN-NEXT: $sgpr30 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 26 + ; GCN-NEXT: $sgpr30 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 2, implicit-def $sgpr30_sgpr31 + ; GCN-NEXT: $sgpr31 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 3 + ; GCN-NEXT: $sgpr103 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 1 + ; GCN-NEXT: $sgpr102 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 0 + ; GCN-NEXT: $sgpr101 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 31 + ; GCN-NEXT: $sgpr100 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 30 + ; GCN-NEXT: $sgpr99 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 29 + ; GCN-NEXT: $sgpr98 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 28 + ; GCN-NEXT: $sgpr97 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 27 + ; GCN-NEXT: $sgpr96 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 26 + ; GCN-NEXT: $sgpr95 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 25 + ; GCN-NEXT: $sgpr94 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 24 + ; GCN-NEXT: $sgpr93 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 23 + ; GCN-NEXT: $sgpr92 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 22 + ; GCN-NEXT: $sgpr91 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 21 + ; GCN-NEXT: $sgpr90 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 20 + ; GCN-NEXT: $sgpr89 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 19 + ; GCN-NEXT: $sgpr88 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 18 + ; GCN-NEXT: $sgpr87 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 17 + ; GCN-NEXT: $sgpr86 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 16 + ; GCN-NEXT: $sgpr85 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 15 + ; GCN-NEXT: $sgpr84 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 14 + ; GCN-NEXT: $sgpr83 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 13 + ; GCN-NEXT: $sgpr82 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 12 + ; GCN-NEXT: $sgpr81 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 11 + ; GCN-NEXT: $sgpr80 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 10 + ; GCN-NEXT: $sgpr79 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 9 + ; GCN-NEXT: $sgpr78 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 8 + ; GCN-NEXT: $sgpr77 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 7 + ; GCN-NEXT: $sgpr76 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 6 + ; GCN-NEXT: $sgpr75 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 5 + ; GCN-NEXT: $sgpr74 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 4 + ; GCN-NEXT: $sgpr73 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 3 + ; GCN-NEXT: $sgpr72 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 2 + ; GCN-NEXT: $sgpr71 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 1 + ; GCN-NEXT: $sgpr70 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 0 + ; GCN-NEXT: $sgpr69 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 31 + ; GCN-NEXT: $sgpr68 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 30 + ; GCN-NEXT: $sgpr67 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 29 + ; GCN-NEXT: $sgpr66 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 28 + ; GCN-NEXT: $sgpr65 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 27 + ; GCN-NEXT: $sgpr64 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 26 ; GCN-NEXT: $sgpr29 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 25 ; GCN-NEXT: $sgpr28 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 24 ; GCN-NEXT: $sgpr27 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 23 @@ -200,12 +317,13 @@ body: | ; GCN-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 0 ; GCN-NEXT: $sgpr32 = frame-destroy COPY $sgpr33 ; GCN-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5) - ; GCN-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5) - ; GCN-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5) - ; GCN-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5) - ; GCN-NEXT: $vgpr5 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.73, addrspace 5) + ; GCN-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.68, addrspace 5) + ; GCN-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5) + ; GCN-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5) + ; GCN-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5) + ; GCN-NEXT: $vgpr5 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5) ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 + ; GCN-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 ; GCN-NEXT: $sgpr33 = frame-destroy COPY $vcc_hi ; GCN-NEXT: S_ENDPGM 0 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir index 59c4b715dd12e..bb7a28c68d3c5 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir @@ -23,6 +23,8 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $sgpr8 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 @@ -73,6 +75,8 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $sgpr8_sgpr9 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 @@ -122,6 +126,9 @@ body: | ; VMEM-GFX8: bb.0: ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 @@ -170,6 +177,10 @@ body: | ; VMEM-GFX8: bb.0: ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 @@ -220,6 +231,838 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1 @@ -273,6 +1116,838 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1 @@ -329,6 +2004,838 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8_sgpr9 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 3 @@ -383,6 +2890,838 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 3 @@ -443,6 +3782,838 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8, $sgpr9 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1 @@ -507,6 +4678,838 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1 diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir index cac9c85130a7b..a1fc683679f9d 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir @@ -25,6 +25,9 @@ body: | ; CHECK-LABEL: name: test ; CHECK: liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 ; CHECK-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; CHECK-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir index ba2e80fdc04c8..92c4249b26069 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir @@ -58,6 +58,8 @@ body: | ; GCN64-MUBUF-LABEL: name: check_spill ; GCN64-MUBUF: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr11 ; GCN64-MUBUF-NEXT: {{ $}} + ; GCN64-MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GCN64-MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GCN64-MUBUF-NEXT: $sgpr33 = S_MOV_B32 0 ; GCN64-MUBUF-NEXT: $sgpr28 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31 ; GCN64-MUBUF-NEXT: $sgpr29 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31 @@ -222,6 +224,8 @@ body: | ; GCN32-MUBUF-LABEL: name: check_spill ; GCN32-MUBUF: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr11 ; GCN32-MUBUF-NEXT: {{ $}} + ; GCN32-MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GCN32-MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GCN32-MUBUF-NEXT: $sgpr33 = S_MOV_B32 0 ; GCN32-MUBUF-NEXT: $sgpr96 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 ; GCN32-MUBUF-NEXT: $sgpr97 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 @@ -386,6 +390,8 @@ body: | ; GCN64-FLATSCR-LABEL: name: check_spill ; GCN64-FLATSCR: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr11, $sgpr0_sgpr1 ; GCN64-FLATSCR-NEXT: {{ $}} + ; GCN64-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GCN64-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GCN64-FLATSCR-NEXT: $sgpr33 = S_MOV_B32 0 ; GCN64-FLATSCR-NEXT: $flat_scr_lo = S_ADD_U32 $sgpr0, $sgpr11, implicit-def $scc ; GCN64-FLATSCR-NEXT: $flat_scr_hi = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc @@ -617,6 +623,8 @@ body: | ; GCN64-MUBUF-LABEL: name: check_reload ; GCN64-MUBUF: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr11 ; GCN64-MUBUF-NEXT: {{ $}} + ; GCN64-MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GCN64-MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GCN64-MUBUF-NEXT: $sgpr33 = S_MOV_B32 0 ; GCN64-MUBUF-NEXT: $sgpr28 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31 ; GCN64-MUBUF-NEXT: $sgpr29 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31 @@ -755,6 +763,8 @@ body: | ; GCN32-MUBUF-LABEL: name: check_reload ; GCN32-MUBUF: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr11 ; GCN32-MUBUF-NEXT: {{ $}} + ; GCN32-MUBUF-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GCN32-MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GCN32-MUBUF-NEXT: $sgpr33 = S_MOV_B32 0 ; GCN32-MUBUF-NEXT: $sgpr96 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 ; GCN32-MUBUF-NEXT: $sgpr97 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 @@ -893,6 +903,8 @@ body: | ; GCN64-FLATSCR-LABEL: name: check_reload ; GCN64-FLATSCR: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr11, $sgpr0_sgpr1 ; GCN64-FLATSCR-NEXT: {{ $}} + ; GCN64-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GCN64-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GCN64-FLATSCR-NEXT: $sgpr33 = S_MOV_B32 0 ; GCN64-FLATSCR-NEXT: $flat_scr_lo = S_ADD_U32 $sgpr0, $sgpr11, implicit-def $scc ; GCN64-FLATSCR-NEXT: $flat_scr_hi = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll b/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll index 702953c56a5cb..cb54b0ba629c3 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll @@ -152,8 +152,8 @@ define void @spill_sgpr_with_no_lower_vgpr_available() #0 { ; GCN-NEXT: s_mov_b64 s[2:3], s[22:23] ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GCN-NEXT: v_readlane_b32 s31, v255, 1 ; GCN-NEXT: v_readlane_b32 s30, v255, 0 +; GCN-NEXT: v_readlane_b32 s31, v255, 1 ; GCN-NEXT: buffer_load_dword v254, off, s[0:3], s33 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v253, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v252, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload @@ -445,8 +445,8 @@ define void @spill_to_lowest_available_vgpr() #0 { ; GCN-NEXT: s_mov_b64 s[2:3], s[22:23] ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GCN-NEXT: v_readlane_b32 s31, v254, 1 ; GCN-NEXT: v_readlane_b32 s30, v254, 0 +; GCN-NEXT: v_readlane_b32 s31, v254, 1 ; GCN-NEXT: buffer_load_dword v253, off, s[0:3], s33 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v252, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v251, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload @@ -1632,21 +1632,14 @@ define void @spill_sgpr_no_free_vgpr_ipra() #0 { ; GCN-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 s[16:17], exec -; GCN-NEXT: s_mov_b64 exec, 1 +; GCN-NEXT: s_mov_b64 exec, 3 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:456 ; GCN-NEXT: v_writelane_b32 v0, s30, 0 +; GCN-NEXT: v_writelane_b32 v0, s31, 1 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:448 ; 4-byte Folded Spill ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:456 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_mov_b64 exec, s[16:17] -; GCN-NEXT: s_mov_b64 s[16:17], exec -; GCN-NEXT: s_mov_b64 exec, 1 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:456 -; GCN-NEXT: v_writelane_b32 v0, s31, 0 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:452 ; 4-byte Folded Spill -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:456 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_mov_b64 exec, s[16:17] ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, child_function_ipra@rel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, child_function_ipra@rel32@hi+12 @@ -1656,20 +1649,12 @@ define void @spill_sgpr_no_free_vgpr_ipra() #0 { ; GCN-NEXT: s_mov_b64 s[2:3], s[22:23] ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GCN-NEXT: s_mov_b64 s[4:5], exec -; GCN-NEXT: s_mov_b64 exec, 1 -; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:456 -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:452 ; 4-byte Folded Reload -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_readlane_b32 s31, v0, 0 -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:456 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_mov_b64 exec, s[4:5] -; GCN-NEXT: s_mov_b64 s[4:5], exec -; GCN-NEXT: s_mov_b64 exec, 1 +; GCN-NEXT: s_mov_b64 exec, 3 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:456 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:448 ; 4-byte Folded Reload ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_readlane_b32 s30, v0, 0 +; GCN-NEXT: v_readlane_b32 s31, v0, 1 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:456 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_mov_b64 exec, s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll index 7ee7c83e0122d..7feef49839ed5 100644 --- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll +++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll @@ -14689,22 +14689,22 @@ define void @s_shuffle_v2i64_v8i64__15_2() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[8:23] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s8, s30 ; GFX900-NEXT: s_mov_b32 s9, s31 +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s10, s12 ; GFX900-NEXT: s_mov_b32 s11, s13 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -14718,22 +14718,22 @@ define void @s_shuffle_v2i64_v8i64__15_2() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[8:23] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s8, s30 ; GFX90A-NEXT: s_mov_b32 s9, s31 +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s10, s12 ; GFX90A-NEXT: s_mov_b32 s11, s13 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -14829,22 +14829,22 @@ define void @s_shuffle_v2i64_v8i64__15_4() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s8, s30 ; GFX900-NEXT: s_mov_b32 s9, s31 +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s10, s12 ; GFX900-NEXT: s_mov_b32 s11, s13 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -14858,22 +14858,22 @@ define void @s_shuffle_v2i64_v8i64__15_4() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s8, s30 ; GFX90A-NEXT: s_mov_b32 s9, s31 +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s10, s12 ; GFX90A-NEXT: s_mov_b32 s11, s13 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -14887,22 +14887,23 @@ define void @s_shuffle_v2i64_v8i64__15_4() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[4:19] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 +; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s30 ; GFX942-NEXT: s_mov_b32 s9, s31 -; GFX942-NEXT: s_mov_b32 s10, s12 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s11, s13 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -14923,22 +14924,22 @@ define void @s_shuffle_v2i64_v8i64__15_5() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s12, s30 ; GFX900-NEXT: s_mov_b32 s13, s31 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -14952,22 +14953,22 @@ define void @s_shuffle_v2i64_v8i64__15_5() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s12, s30 ; GFX90A-NEXT: s_mov_b32 s13, s31 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -15087,6 +15088,7 @@ define void @s_shuffle_v2i64_v8i64__15_6() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] @@ -15096,13 +15098,13 @@ define void @s_shuffle_v2i64_v8i64__15_6() { ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s30 ; GFX942-NEXT: s_mov_b32 s9, s31 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: s_mov_b32 s11, s13 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -15129,10 +15131,10 @@ define void @s_shuffle_v2i64_v8i64__15_7() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -15170,10 +15172,10 @@ define void @s_shuffle_v2i64_v8i64__15_7() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -15205,22 +15207,23 @@ define void @s_shuffle_v2i64_v8i64__15_7() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s12, s30 ; GFX942-NEXT: s_mov_b32 s13, s31 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -16255,6 +16258,7 @@ define void @s_shuffle_v2i64_v8i64__12_0() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] @@ -16263,12 +16267,12 @@ define void @s_shuffle_v2i64_v8i64__12_0() { ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s10, s16 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s11, s17 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -16978,6 +16982,7 @@ define void @s_shuffle_v2i64_v8i64__12_1() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] @@ -16986,12 +16991,12 @@ define void @s_shuffle_v2i64_v8i64__12_1() { ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s10, s18 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s11, s19 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -17562,13 +17567,14 @@ define void @s_shuffle_v2i64_v8i64__9_2() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[8:23] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s18 ; GFX900-NEXT: s_mov_b32 s9, s19 ; GFX900-NEXT: s_mov_b32 s10, s12 @@ -17577,7 +17583,6 @@ define void @s_shuffle_v2i64_v8i64__9_2() { ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -17591,13 +17596,14 @@ define void @s_shuffle_v2i64_v8i64__9_2() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[8:23] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s18 ; GFX90A-NEXT: s_mov_b32 s9, s19 ; GFX90A-NEXT: s_mov_b32 s10, s12 @@ -17606,7 +17612,6 @@ define void @s_shuffle_v2i64_v8i64__9_2() { ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -17653,13 +17658,13 @@ define void @s_shuffle_v2i64_v8i64__10_2() { ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s10, s20 ; GFX900-NEXT: s_mov_b32 s11, s21 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -17680,13 +17685,13 @@ define void @s_shuffle_v2i64_v8i64__10_2() { ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s10, s20 ; GFX90A-NEXT: s_mov_b32 s11, s21 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -17700,6 +17705,7 @@ define void @s_shuffle_v2i64_v8i64__10_2() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] @@ -17708,13 +17714,13 @@ define void @s_shuffle_v2i64_v8i64__10_2() { ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[4:19] ; GFX942-NEXT: ;;#ASMEND +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s10, s20 ; GFX942-NEXT: s_mov_b32 s11, s21 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -17735,13 +17741,14 @@ define void @s_shuffle_v2i64_v8i64__11_2() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[8:23] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s22 ; GFX900-NEXT: s_mov_b32 s9, s23 ; GFX900-NEXT: s_mov_b32 s10, s12 @@ -17750,7 +17757,6 @@ define void @s_shuffle_v2i64_v8i64__11_2() { ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -17764,13 +17770,14 @@ define void @s_shuffle_v2i64_v8i64__11_2() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[8:23] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s22 ; GFX90A-NEXT: s_mov_b32 s9, s23 ; GFX90A-NEXT: s_mov_b32 s10, s12 @@ -17779,7 +17786,6 @@ define void @s_shuffle_v2i64_v8i64__11_2() { ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -17879,13 +17885,14 @@ define void @s_shuffle_v2i64_v8i64__13_2() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[8:23] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s26 ; GFX900-NEXT: s_mov_b32 s9, s27 ; GFX900-NEXT: s_mov_b32 s10, s12 @@ -17894,7 +17901,6 @@ define void @s_shuffle_v2i64_v8i64__13_2() { ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -17908,13 +17914,14 @@ define void @s_shuffle_v2i64_v8i64__13_2() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[8:23] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s26 ; GFX90A-NEXT: s_mov_b32 s9, s27 ; GFX90A-NEXT: s_mov_b32 s10, s12 @@ -17923,7 +17930,6 @@ define void @s_shuffle_v2i64_v8i64__13_2() { ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -18403,13 +18409,13 @@ define void @s_shuffle_v2i64_v8i64__10_3() { ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s10, s22 ; GFX900-NEXT: s_mov_b32 s11, s23 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -18430,13 +18436,13 @@ define void @s_shuffle_v2i64_v8i64__10_3() { ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s10, s22 ; GFX90A-NEXT: s_mov_b32 s11, s23 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -18450,6 +18456,7 @@ define void @s_shuffle_v2i64_v8i64__10_3() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] @@ -18458,13 +18465,13 @@ define void @s_shuffle_v2i64_v8i64__10_3() { ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[4:19] ; GFX942-NEXT: ;;#ASMEND +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s10, s22 ; GFX942-NEXT: s_mov_b32 s11, s23 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -19031,13 +19038,14 @@ define void @s_shuffle_v2i64_v8i64__9_4() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s18 ; GFX900-NEXT: s_mov_b32 s9, s19 ; GFX900-NEXT: s_mov_b32 s10, s12 @@ -19046,7 +19054,6 @@ define void @s_shuffle_v2i64_v8i64__9_4() { ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -19060,13 +19067,14 @@ define void @s_shuffle_v2i64_v8i64__9_4() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s18 ; GFX90A-NEXT: s_mov_b32 s9, s19 ; GFX90A-NEXT: s_mov_b32 s10, s12 @@ -19075,7 +19083,6 @@ define void @s_shuffle_v2i64_v8i64__9_4() { ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -19089,22 +19096,23 @@ define void @s_shuffle_v2i64_v8i64__9_4() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[4:19] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 +; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s18 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s9, s19 -; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: s_mov_b32 s11, s13 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -19181,13 +19189,14 @@ define void @s_shuffle_v2i64_v8i64__11_4() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s22 ; GFX900-NEXT: s_mov_b32 s9, s23 ; GFX900-NEXT: s_mov_b32 s10, s12 @@ -19196,7 +19205,6 @@ define void @s_shuffle_v2i64_v8i64__11_4() { ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -19210,13 +19218,14 @@ define void @s_shuffle_v2i64_v8i64__11_4() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s22 ; GFX90A-NEXT: s_mov_b32 s9, s23 ; GFX90A-NEXT: s_mov_b32 s10, s12 @@ -19225,7 +19234,6 @@ define void @s_shuffle_v2i64_v8i64__11_4() { ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -19239,22 +19247,23 @@ define void @s_shuffle_v2i64_v8i64__11_4() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[4:19] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 +; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s22 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s9, s23 -; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: s_mov_b32 s11, s13 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -19275,22 +19284,22 @@ define void @s_shuffle_v2i64_v8i64__12_4() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s26, s12 ; GFX900-NEXT: s_mov_b32 s27, s13 ; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[26:27] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -19304,22 +19313,22 @@ define void @s_shuffle_v2i64_v8i64__12_4() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s26, s12 ; GFX90A-NEXT: s_mov_b32 s27, s13 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[26:27] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -19357,13 +19366,14 @@ define void @s_shuffle_v2i64_v8i64__13_4() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s26 ; GFX900-NEXT: s_mov_b32 s9, s27 ; GFX900-NEXT: s_mov_b32 s10, s12 @@ -19372,7 +19382,6 @@ define void @s_shuffle_v2i64_v8i64__13_4() { ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -19386,13 +19395,14 @@ define void @s_shuffle_v2i64_v8i64__13_4() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s26 ; GFX90A-NEXT: s_mov_b32 s9, s27 ; GFX90A-NEXT: s_mov_b32 s10, s12 @@ -19401,7 +19411,6 @@ define void @s_shuffle_v2i64_v8i64__13_4() { ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -19415,22 +19424,23 @@ define void @s_shuffle_v2i64_v8i64__13_4() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[4:19] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 +; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s26 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s9, s27 -; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: s_mov_b32 s11, s13 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -19451,10 +19461,10 @@ define void @s_shuffle_v2i64_v8i64__14_4() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND @@ -19462,11 +19472,11 @@ define void @s_shuffle_v2i64_v8i64__14_4() { ; GFX900-NEXT: s_mov_b32 s31, s13 ; GFX900-NEXT: s_mov_b64 s[8:9], s[28:29] ; GFX900-NEXT: s_mov_b64 s[10:11], s[30:31] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -19480,10 +19490,10 @@ define void @s_shuffle_v2i64_v8i64__14_4() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND @@ -19491,11 +19501,11 @@ define void @s_shuffle_v2i64_v8i64__14_4() { ; GFX90A-NEXT: s_mov_b32 s31, s13 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[28:29] ; GFX90A-NEXT: s_mov_b64 s[10:11], s[30:31] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -19952,22 +19962,22 @@ define void @s_shuffle_v2i64_v8i64__9_5() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s12, s18 ; GFX900-NEXT: s_mov_b32 s13, s19 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -19981,22 +19991,22 @@ define void @s_shuffle_v2i64_v8i64__9_5() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s12, s18 ; GFX90A-NEXT: s_mov_b32 s13, s19 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -20090,22 +20100,22 @@ define void @s_shuffle_v2i64_v8i64__11_5() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s12, s22 ; GFX900-NEXT: s_mov_b32 s13, s23 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -20119,22 +20129,22 @@ define void @s_shuffle_v2i64_v8i64__11_5() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s12, s22 ; GFX90A-NEXT: s_mov_b32 s13, s23 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -20172,22 +20182,22 @@ define void @s_shuffle_v2i64_v8i64__12_5() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s26, s14 ; GFX900-NEXT: s_mov_b32 s27, s15 ; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[26:27] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -20201,22 +20211,22 @@ define void @s_shuffle_v2i64_v8i64__12_5() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s26, s14 ; GFX90A-NEXT: s_mov_b32 s27, s15 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[26:27] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -20254,22 +20264,22 @@ define void @s_shuffle_v2i64_v8i64__13_5() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s12, s26 ; GFX900-NEXT: s_mov_b32 s13, s27 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -20283,22 +20293,22 @@ define void @s_shuffle_v2i64_v8i64__13_5() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s12, s26 ; GFX90A-NEXT: s_mov_b32 s13, s27 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -20336,10 +20346,10 @@ define void @s_shuffle_v2i64_v8i64__14_5() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND @@ -20347,11 +20357,11 @@ define void @s_shuffle_v2i64_v8i64__14_5() { ; GFX900-NEXT: s_mov_b32 s31, s15 ; GFX900-NEXT: s_mov_b64 s[8:9], s[28:29] ; GFX900-NEXT: s_mov_b64 s[10:11], s[30:31] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -20365,10 +20375,10 @@ define void @s_shuffle_v2i64_v8i64__14_5() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND @@ -20376,11 +20386,11 @@ define void @s_shuffle_v2i64_v8i64__14_5() { ; GFX90A-NEXT: s_mov_b32 s31, s15 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[28:29] ; GFX90A-NEXT: s_mov_b64 s[10:11], s[30:31] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -20934,14 +20944,16 @@ define void @s_shuffle_v2i64_v8i64__9_6() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[0:15] +; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[16:31] +; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s18 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s9, s19 ; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: s_mov_b32 s11, s13 @@ -20949,7 +20961,6 @@ define void @s_shuffle_v2i64_v8i64__9_6() { ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -21108,14 +21119,16 @@ define void @s_shuffle_v2i64_v8i64__11_6() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[0:15] +; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[16:31] +; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s22 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s9, s23 ; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: s_mov_b32 s11, s13 @@ -21123,7 +21136,6 @@ define void @s_shuffle_v2i64_v8i64__11_6() { ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -21332,14 +21344,16 @@ define void @s_shuffle_v2i64_v8i64__13_6() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[0:15] +; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[16:31] +; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s26 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s9, s27 ; GFX942-NEXT: s_mov_b32 s10, s12 ; GFX942-NEXT: s_mov_b32 s11, s13 @@ -21347,7 +21361,6 @@ define void @s_shuffle_v2i64_v8i64__13_6() { ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -21450,6 +21463,7 @@ define void @s_shuffle_v2i64_v8i64__14_6() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] @@ -21461,11 +21475,11 @@ define void @s_shuffle_v2i64_v8i64__14_6() { ; GFX942-NEXT: s_mov_b32 s31, s13 ; GFX942-NEXT: s_mov_b64 s[8:9], s[28:29] ; GFX942-NEXT: s_mov_b64 s[10:11], s[30:31] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -21918,10 +21932,10 @@ define void @s_shuffle_v2i64_v8i64__9_7() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -21959,10 +21973,10 @@ define void @s_shuffle_v2i64_v8i64__9_7() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -21994,22 +22008,23 @@ define void @s_shuffle_v2i64_v8i64__9_7() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s12, s18 ; GFX942-NEXT: s_mov_b32 s13, s19 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -22092,10 +22107,10 @@ define void @s_shuffle_v2i64_v8i64__11_7() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -22133,10 +22148,10 @@ define void @s_shuffle_v2i64_v8i64__11_7() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -22168,22 +22183,23 @@ define void @s_shuffle_v2i64_v8i64__11_7() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s12, s22 ; GFX942-NEXT: s_mov_b32 s13, s23 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -22316,10 +22332,10 @@ define void @s_shuffle_v2i64_v8i64__13_7() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -22357,10 +22373,10 @@ define void @s_shuffle_v2i64_v8i64__13_7() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -22392,22 +22408,23 @@ define void @s_shuffle_v2i64_v8i64__13_7() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s12, s26 ; GFX942-NEXT: s_mov_b32 s13, s27 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -22510,6 +22527,7 @@ define void @s_shuffle_v2i64_v8i64__14_7() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] @@ -22521,11 +22539,11 @@ define void @s_shuffle_v2i64_v8i64__14_7() { ; GFX942-NEXT: s_mov_b32 s31, s15 ; GFX942-NEXT: s_mov_b64 s[8:9], s[28:29] ; GFX942-NEXT: s_mov_b64 s[10:11], s[30:31] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -23512,22 +23530,22 @@ define void @s_shuffle_v2i64_v8i64__4_9() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s14, s18 ; GFX900-NEXT: s_mov_b32 s15, s19 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -23541,22 +23559,22 @@ define void @s_shuffle_v2i64_v8i64__4_9() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s14, s18 ; GFX90A-NEXT: s_mov_b32 s15, s19 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -23601,13 +23619,13 @@ define void @s_shuffle_v2i64_v8i64__5_9() { ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[8:23] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s26 ; GFX900-NEXT: s_mov_b32 s9, s27 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -23628,13 +23646,13 @@ define void @s_shuffle_v2i64_v8i64__5_9() { ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[8:23] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s26 ; GFX90A-NEXT: s_mov_b32 s9, s27 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -23648,6 +23666,7 @@ define void @s_shuffle_v2i64_v8i64__5_9() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] @@ -23656,13 +23675,13 @@ define void @s_shuffle_v2i64_v8i64__5_9() { ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[8:23] ; GFX942-NEXT: ;;#ASMEND +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s8, s26 ; GFX942-NEXT: s_mov_b32 s9, s27 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -23689,10 +23708,10 @@ define void @s_shuffle_v2i64_v8i64__6_9() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -23730,10 +23749,10 @@ define void @s_shuffle_v2i64_v8i64__6_9() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -23765,22 +23784,23 @@ define void @s_shuffle_v2i64_v8i64__6_9() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s14, s18 ; GFX942-NEXT: s_mov_b32 s15, s19 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -24362,22 +24382,22 @@ define void @s_shuffle_v2i64_v8i64__4_10() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s14, s20 ; GFX900-NEXT: s_mov_b32 s15, s21 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -24391,22 +24411,22 @@ define void @s_shuffle_v2i64_v8i64__4_10() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s14, s20 ; GFX90A-NEXT: s_mov_b32 s15, s21 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -24444,13 +24464,14 @@ define void @s_shuffle_v2i64_v8i64__5_10() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s14 ; GFX900-NEXT: s_mov_b32 s9, s15 ; GFX900-NEXT: s_mov_b32 s10, s20 @@ -24459,7 +24480,6 @@ define void @s_shuffle_v2i64_v8i64__5_10() { ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -24473,13 +24493,14 @@ define void @s_shuffle_v2i64_v8i64__5_10() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s14 ; GFX90A-NEXT: s_mov_b32 s9, s15 ; GFX90A-NEXT: s_mov_b32 s10, s20 @@ -24488,7 +24509,6 @@ define void @s_shuffle_v2i64_v8i64__5_10() { ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -24533,10 +24553,10 @@ define void @s_shuffle_v2i64_v8i64__6_10() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -24574,10 +24594,10 @@ define void @s_shuffle_v2i64_v8i64__6_10() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -24609,22 +24629,23 @@ define void @s_shuffle_v2i64_v8i64__6_10() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s14, s20 ; GFX942-NEXT: s_mov_b32 s15, s21 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -24727,14 +24748,16 @@ define void @s_shuffle_v2i64_v8i64__7_10() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[0:15] +; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[16:31] +; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s14 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s9, s15 ; GFX942-NEXT: s_mov_b32 s10, s20 ; GFX942-NEXT: s_mov_b32 s11, s21 @@ -24742,7 +24765,6 @@ define void @s_shuffle_v2i64_v8i64__7_10() { ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -25323,13 +25345,13 @@ define void @s_shuffle_v2i64_v8i64__3_11() { ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s22 ; GFX900-NEXT: s_mov_b32 s9, s23 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -25350,13 +25372,13 @@ define void @s_shuffle_v2i64_v8i64__3_11() { ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s22 ; GFX90A-NEXT: s_mov_b32 s9, s23 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -25370,6 +25392,7 @@ define void @s_shuffle_v2i64_v8i64__3_11() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] @@ -25378,13 +25401,13 @@ define void @s_shuffle_v2i64_v8i64__3_11() { ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[4:19] ; GFX942-NEXT: ;;#ASMEND +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s8, s22 ; GFX942-NEXT: s_mov_b32 s9, s23 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -25405,22 +25428,22 @@ define void @s_shuffle_v2i64_v8i64__4_11() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s14, s22 ; GFX900-NEXT: s_mov_b32 s15, s23 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -25434,22 +25457,22 @@ define void @s_shuffle_v2i64_v8i64__4_11() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s14, s22 ; GFX90A-NEXT: s_mov_b32 s15, s23 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -25549,10 +25572,10 @@ define void @s_shuffle_v2i64_v8i64__6_11() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -25590,10 +25613,10 @@ define void @s_shuffle_v2i64_v8i64__6_11() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -25625,22 +25648,23 @@ define void @s_shuffle_v2i64_v8i64__6_11() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s14, s22 ; GFX942-NEXT: s_mov_b32 s15, s23 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -26222,22 +26246,22 @@ define void @s_shuffle_v2i64_v8i64__4_12() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s14, s24 ; GFX900-NEXT: s_mov_b32 s15, s25 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -26251,22 +26275,22 @@ define void @s_shuffle_v2i64_v8i64__4_12() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s14, s24 ; GFX90A-NEXT: s_mov_b32 s15, s25 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -26304,13 +26328,14 @@ define void @s_shuffle_v2i64_v8i64__5_12() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s14 ; GFX900-NEXT: s_mov_b32 s9, s15 ; GFX900-NEXT: s_mov_b32 s10, s24 @@ -26319,7 +26344,6 @@ define void @s_shuffle_v2i64_v8i64__5_12() { ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -26333,13 +26357,14 @@ define void @s_shuffle_v2i64_v8i64__5_12() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s14 ; GFX90A-NEXT: s_mov_b32 s9, s15 ; GFX90A-NEXT: s_mov_b32 s10, s24 @@ -26348,7 +26373,6 @@ define void @s_shuffle_v2i64_v8i64__5_12() { ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -26393,10 +26417,10 @@ define void @s_shuffle_v2i64_v8i64__6_12() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -26434,10 +26458,10 @@ define void @s_shuffle_v2i64_v8i64__6_12() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -26469,22 +26493,23 @@ define void @s_shuffle_v2i64_v8i64__6_12() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s14, s24 ; GFX942-NEXT: s_mov_b32 s15, s25 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -26587,14 +26612,16 @@ define void @s_shuffle_v2i64_v8i64__7_12() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[0:15] +; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[16:31] +; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s14 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s9, s15 ; GFX942-NEXT: s_mov_b32 s10, s24 ; GFX942-NEXT: s_mov_b32 s11, s25 @@ -26602,7 +26629,6 @@ define void @s_shuffle_v2i64_v8i64__7_12() { ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -26968,6 +26994,7 @@ define void @s_shuffle_v2i64_v8i64__1_13() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] @@ -26976,12 +27003,12 @@ define void @s_shuffle_v2i64_v8i64__1_13() { ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s18 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s9, s19 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -27118,22 +27145,22 @@ define void @s_shuffle_v2i64_v8i64__4_13() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s14, s26 ; GFX900-NEXT: s_mov_b32 s15, s27 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -27147,22 +27174,22 @@ define void @s_shuffle_v2i64_v8i64__4_13() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s14, s26 ; GFX90A-NEXT: s_mov_b32 s15, s27 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -27200,22 +27227,22 @@ define void @s_shuffle_v2i64_v8i64__5_13() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s24, s14 ; GFX900-NEXT: s_mov_b32 s25, s15 ; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[26:27] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -27229,22 +27256,22 @@ define void @s_shuffle_v2i64_v8i64__5_13() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s24, s14 ; GFX90A-NEXT: s_mov_b32 s25, s15 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[26:27] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -27288,10 +27315,10 @@ define void @s_shuffle_v2i64_v8i64__6_13() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -27329,10 +27356,10 @@ define void @s_shuffle_v2i64_v8i64__6_13() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -27364,22 +27391,23 @@ define void @s_shuffle_v2i64_v8i64__6_13() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s14, s26 ; GFX942-NEXT: s_mov_b32 s15, s27 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -28075,22 +28103,22 @@ define void @s_shuffle_v2i64_v8i64__4_14() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s14, s28 ; GFX900-NEXT: s_mov_b32 s15, s29 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -28104,22 +28132,22 @@ define void @s_shuffle_v2i64_v8i64__4_14() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s14, s28 ; GFX90A-NEXT: s_mov_b32 s15, s29 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -28157,13 +28185,14 @@ define void @s_shuffle_v2i64_v8i64__5_14() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b32 s8, s14 ; GFX900-NEXT: s_mov_b32 s9, s15 ; GFX900-NEXT: s_mov_b32 s10, s28 @@ -28172,7 +28201,6 @@ define void @s_shuffle_v2i64_v8i64__5_14() { ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -28186,13 +28214,14 @@ define void @s_shuffle_v2i64_v8i64__5_14() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b32 s8, s14 ; GFX90A-NEXT: s_mov_b32 s9, s15 ; GFX90A-NEXT: s_mov_b32 s10, s28 @@ -28201,7 +28230,6 @@ define void @s_shuffle_v2i64_v8i64__5_14() { ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -28246,10 +28274,10 @@ define void @s_shuffle_v2i64_v8i64__6_14() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -28287,10 +28315,10 @@ define void @s_shuffle_v2i64_v8i64__6_14() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -28322,22 +28350,23 @@ define void @s_shuffle_v2i64_v8i64__6_14() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s14, s28 ; GFX942-NEXT: s_mov_b32 s15, s29 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -28440,14 +28469,16 @@ define void @s_shuffle_v2i64_v8i64__7_14() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[0:15] +; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: ;;#ASMSTART -; GFX942-NEXT: ; def s[16:31] +; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s8, s14 +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b32 s9, s15 ; GFX942-NEXT: s_mov_b32 s10, s28 ; GFX942-NEXT: s_mov_b32 s11, s29 @@ -28455,7 +28486,6 @@ define void @s_shuffle_v2i64_v8i64__7_14() { ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -29056,22 +29086,22 @@ define void @s_shuffle_v2i64_v8i64__4_15() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: s_mov_b32 s14, s30 ; GFX900-NEXT: s_mov_b32 s15, s31 ; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -29085,22 +29115,22 @@ define void @s_shuffle_v2i64_v8i64__4_15() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: s_mov_b32 s14, s30 ; GFX90A-NEXT: s_mov_b32 s15, s31 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -29138,10 +29168,10 @@ define void @s_shuffle_v2i64_v8i64__5_15() { ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX900-NEXT: s_mov_b64 exec, s[4:5] ; GFX900-NEXT: v_writelane_b32 v0, s30, 0 +; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s31, 1 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[16:31] ; GFX900-NEXT: ;;#ASMEND @@ -29149,11 +29179,11 @@ define void @s_shuffle_v2i64_v8i64__5_15() { ; GFX900-NEXT: s_mov_b32 s29, s15 ; GFX900-NEXT: s_mov_b64 s[8:9], s[28:29] ; GFX900-NEXT: s_mov_b64 s[10:11], s[30:31] +; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; use s[8:11] ; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: v_readlane_b32 s31, v0, 1 -; GFX900-NEXT: v_readlane_b32 s30, v0, 0 ; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX900-NEXT: s_mov_b64 exec, s[4:5] @@ -29167,10 +29197,10 @@ define void @s_shuffle_v2i64_v8i64__5_15() { ; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] ; GFX90A-NEXT: v_writelane_b32 v0, s30, 0 +; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s31, 1 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[16:31] ; GFX90A-NEXT: ;;#ASMEND @@ -29178,11 +29208,11 @@ define void @s_shuffle_v2i64_v8i64__5_15() { ; GFX90A-NEXT: s_mov_b32 s29, s15 ; GFX90A-NEXT: s_mov_b64 s[8:9], s[28:29] ; GFX90A-NEXT: s_mov_b64 s[10:11], s[30:31] +; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s[8:11] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v0, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v0, 0 ; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX90A-NEXT: s_mov_b64 exec, s[4:5] @@ -29228,10 +29258,10 @@ define void @s_shuffle_v2i64_v8i64__6_15() { ; GFX900-NEXT: v_writelane_b32 v0, s48, 4 ; GFX900-NEXT: v_writelane_b32 v0, s49, 5 ; GFX900-NEXT: v_writelane_b32 v0, s50, 6 +; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[4:19] ; GFX900-NEXT: ;;#ASMEND -; GFX900-NEXT: v_writelane_b32 v0, s51, 7 ; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ; def s[36:51] ; GFX900-NEXT: ;;#ASMEND @@ -29269,10 +29299,10 @@ define void @s_shuffle_v2i64_v8i64__6_15() { ; GFX90A-NEXT: v_writelane_b32 v0, s48, 4 ; GFX90A-NEXT: v_writelane_b32 v0, s49, 5 ; GFX90A-NEXT: v_writelane_b32 v0, s50, 6 +; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[4:19] ; GFX90A-NEXT: ;;#ASMEND -; GFX90A-NEXT: v_writelane_b32 v0, s51, 7 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s[36:51] ; GFX90A-NEXT: ;;#ASMEND @@ -29304,22 +29334,23 @@ define void @s_shuffle_v2i64_v8i64__6_15() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[0:15] ; GFX942-NEXT: ;;#ASMEND -; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: s_mov_b32 s14, s30 ; GFX942-NEXT: s_mov_b32 s15, s31 ; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15] ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] @@ -29422,6 +29453,7 @@ define void @s_shuffle_v2i64_v8i64__7_15() { ; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill ; GFX942-NEXT: s_mov_b64 exec, s[0:1] ; GFX942-NEXT: v_writelane_b32 v0, s30, 0 +; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_writelane_b32 v0, s31, 1 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; def s[16:31] @@ -29433,11 +29465,11 @@ define void @s_shuffle_v2i64_v8i64__7_15() { ; GFX942-NEXT: s_mov_b32 s29, s15 ; GFX942-NEXT: s_mov_b64 s[8:9], s[28:29] ; GFX942-NEXT: s_mov_b64 s[10:11], s[30:31] +; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: ;;#ASMSTART ; GFX942-NEXT: ; use s[8:11] ; GFX942-NEXT: ;;#ASMEND ; GFX942-NEXT: v_readlane_b32 s31, v0, 1 -; GFX942-NEXT: v_readlane_b32 s30, v0, 0 ; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload ; GFX942-NEXT: s_mov_b64 exec, s[0:1] diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir index 1ffef8e60d90d..9ebf4f57ed7d3 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir @@ -24,10 +24,11 @@ machineFunctionInfo: body: | bb.0: ; SGPR_SPILLED-LABEL: name: stack-slot-share-equal-sized-spills - ; SGPR_SPILLED: liveins: $sgpr30, $sgpr31, $vgpr62 + ; SGPR_SPILLED: liveins: $vgpr62, $sgpr30_sgpr31 ; SGPR_SPILLED-NEXT: {{ $}} - ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr30, 0, $vgpr62 - ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62 + ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr62, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31 + ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62, implicit killed $sgpr30_sgpr31 + ; SGPR_SPILLED-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr62, 0, 32, $vgpr62, 1, 32 ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]] ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr0, 1, [[DEF]], implicit-def $sgpr0_sgpr1, implicit $sgpr0_sgpr1 @@ -89,10 +90,11 @@ machineFunctionInfo: body: | bb.0: ; SGPR_SPILLED-LABEL: name: stack-slot-share-unequal-sized-spills-with-large-spill-first - ; SGPR_SPILLED: liveins: $sgpr30, $sgpr31, $vgpr62 + ; SGPR_SPILLED: liveins: $vgpr62, $sgpr30_sgpr31 ; SGPR_SPILLED-NEXT: {{ $}} - ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr30, 0, $vgpr62 - ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62 + ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr62, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31 + ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62, implicit killed $sgpr30_sgpr31 + ; SGPR_SPILLED-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr62, 0, 32, $vgpr62, 1, 32 ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]] ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr2, 1, [[DEF]], implicit-def $sgpr2_sgpr3, implicit $sgpr2_sgpr3 @@ -152,10 +154,11 @@ machineFunctionInfo: body: | bb.0: ; SGPR_SPILLED-LABEL: name: stack-slot-share-unequal-sized-spills-with-small-spill-first - ; SGPR_SPILLED: liveins: $sgpr30, $sgpr31, $vgpr62 + ; SGPR_SPILLED: liveins: $vgpr62, $sgpr30_sgpr31 ; SGPR_SPILLED-NEXT: {{ $}} - ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr30, 0, $vgpr62 - ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62 + ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr62, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31 + ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62, implicit killed $sgpr30_sgpr31 + ; SGPR_SPILLED-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr62, 0, 32, $vgpr62, 1, 32 ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]] ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr0, 1, [[DEF]] diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir index 2de7d86223eb2..e847256e2af8b 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir @@ -2,9 +2,13 @@ # CHECK-LABEL: name: empty_entry_block # CHECK: SI_SPILL_S32_TO_VGPR +# CHECK-NEXT: CFI_INSTRUCTION # CHECK-NEXT: SI_SPILL_S32_TO_VGPR +# CHECK-NEXT: CFI_INSTRUCTION # CHECK-NEXT: SI_SPILL_S32_TO_VGPR +# CHECK-NEXT: CFI_INSTRUCTION # CHECK-NEXT: SI_SPILL_S32_TO_VGPR +# CHECK-NEXT: CFI_INSTRUCTION # CHECK: SI_RESTORE_S32_FROM_VGPR # CHECK-NEXT: SI_RESTORE_S32_FROM_VGPR # CHECK-NEXT: SI_RESTORE_S32_FROM_VGPR diff --git a/llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.ll b/llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.ll index 761ff7786b98e..3419cb3d76320 100644 --- a/llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.ll +++ b/llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.ll @@ -9,6 +9,15 @@ define void @__omp_offloading_35_36570d3__ZN6openmc31process_advance_particle_ev ; GCN-NEXT: .cfi_sections .debug_frame ; GCN-NEXT: .cfi_startproc ; GCN-NEXT: ; %bb.0: ; %bb +; GCN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GCN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GCN-NEXT: .cfi_undefined 2560 +; GCN-NEXT: .cfi_undefined 2561 +; GCN-NEXT: .cfi_undefined 2562 +; GCN-NEXT: .cfi_undefined 2563 +; GCN-NEXT: .cfi_undefined 2564 +; GCN-NEXT: .cfi_undefined 36 +; GCN-NEXT: .cfi_undefined 37 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0 diff --git a/llvm/test/CodeGen/AMDGPU/sibling-call.ll b/llvm/test/CodeGen/AMDGPU/sibling-call.ll index 00214ef36e1f0..98048e7ace538 100644 --- a/llvm/test/CodeGen/AMDGPU/sibling-call.ll +++ b/llvm/test/CodeGen/AMDGPU/sibling-call.ll @@ -231,19 +231,19 @@ define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, pt ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; GCN-NEXT: v_writelane_b32 v40, s4, 2 -; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: v_writelane_b32 v40, s30, 0 +; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s31, 1 +; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, i32_fastcc_i32_byval_i32@rel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, i32_fastcc_i32_byval_i32@rel32@hi+12 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 2 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -382,14 +382,15 @@ define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: v_writelane_b32 v40, s4, 2 +; GCN-NEXT: v_writelane_b32 v40, s30, 0 +; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, i32_fastcc_i32_i32_a32i32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, i32_fastcc_i32_i32_a32i32@gotpcrel32@hi+12 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GCN-NEXT: v_mov_b32_e32 v2, 0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 ; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 ; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:4 ; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 @@ -422,11 +423,10 @@ define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 { ; GCN-NEXT: v_mov_b32_e32 v28, 0 ; GCN-NEXT: v_mov_b32_e32 v29, 0 ; GCN-NEXT: v_mov_b32_e32 v30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 2 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -450,16 +450,16 @@ define fastcc i32 @sibling_call_i32_fastcc_i32_i32_other_call(i32 %a, i32 %b, i3 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: v_writelane_b32 v42, s4, 2 +; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GCN-NEXT: v_writelane_b32 v42, s30, 0 +; GCN-NEXT: v_writelane_b32 v42, s31, 1 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, i32_fastcc_i32_i32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, i32_fastcc_i32_i32@gotpcrel32@hi+12 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GCN-NEXT: v_writelane_b32 v42, s30, 0 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: v_writelane_b32 v42, s31, 1 ; GCN-NEXT: v_mov_b32_e32 v40, v1 ; GCN-NEXT: v_mov_b32_e32 v41, v0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) @@ -469,11 +469,11 @@ define fastcc i32 @sibling_call_i32_fastcc_i32_i32_other_call(i32 %a, i32 %b, i3 ; GCN-NEXT: v_mov_b32_e32 v1, v40 ; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload +; GCN-NEXT: v_readlane_b32 s30, v42, 0 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, sibling_call_i32_fastcc_i32_i32@rel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, sibling_call_i32_fastcc_i32_i32@rel32@hi+12 ; GCN-NEXT: v_readlane_b32 s31, v42, 1 -; GCN-NEXT: v_readlane_b32 s30, v42, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s6, v42, 2 ; GCN-NEXT: s_or_saveexec_b64 s[8:9], -1 @@ -603,23 +603,25 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr ; FIJI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; FIJI-NEXT: s_mov_b64 exec, s[18:19] ; FIJI-NEXT: v_writelane_b32 v40, s16, 18 -; FIJI-NEXT: v_writelane_b32 v40, s30, 0 -; FIJI-NEXT: v_writelane_b32 v40, s31, 1 -; FIJI-NEXT: v_writelane_b32 v40, s34, 2 -; FIJI-NEXT: v_writelane_b32 v40, s35, 3 -; FIJI-NEXT: v_writelane_b32 v40, s36, 4 -; FIJI-NEXT: v_writelane_b32 v40, s37, 5 -; FIJI-NEXT: v_writelane_b32 v40, s38, 6 -; FIJI-NEXT: v_writelane_b32 v40, s39, 7 -; FIJI-NEXT: v_writelane_b32 v40, s48, 8 -; FIJI-NEXT: v_writelane_b32 v40, s49, 9 -; FIJI-NEXT: v_writelane_b32 v40, s50, 10 -; FIJI-NEXT: v_writelane_b32 v40, s51, 11 -; FIJI-NEXT: v_writelane_b32 v40, s52, 12 -; FIJI-NEXT: v_writelane_b32 v40, s53, 13 -; FIJI-NEXT: v_writelane_b32 v40, s54, 14 -; FIJI-NEXT: v_writelane_b32 v40, s55, 15 -; FIJI-NEXT: v_writelane_b32 v40, s64, 16 +; FIJI-NEXT: s_addk_i32 s32, 0x400 +; FIJI-NEXT: v_writelane_b32 v40, s34, 0 +; FIJI-NEXT: v_writelane_b32 v40, s35, 1 +; FIJI-NEXT: v_writelane_b32 v40, s36, 2 +; FIJI-NEXT: v_writelane_b32 v40, s37, 3 +; FIJI-NEXT: v_writelane_b32 v40, s38, 4 +; FIJI-NEXT: v_writelane_b32 v40, s39, 5 +; FIJI-NEXT: v_writelane_b32 v40, s48, 6 +; FIJI-NEXT: v_writelane_b32 v40, s49, 7 +; FIJI-NEXT: v_writelane_b32 v40, s50, 8 +; FIJI-NEXT: v_writelane_b32 v40, s51, 9 +; FIJI-NEXT: v_writelane_b32 v40, s52, 10 +; FIJI-NEXT: v_writelane_b32 v40, s53, 11 +; FIJI-NEXT: v_writelane_b32 v40, s54, 12 +; FIJI-NEXT: v_writelane_b32 v40, s55, 13 +; FIJI-NEXT: v_writelane_b32 v40, s64, 14 +; FIJI-NEXT: v_writelane_b32 v40, s65, 15 +; FIJI-NEXT: v_writelane_b32 v40, s30, 16 +; FIJI-NEXT: v_writelane_b32 v40, s31, 17 ; FIJI-NEXT: s_mov_b32 s50, s15 ; FIJI-NEXT: s_mov_b32 s51, s14 ; FIJI-NEXT: s_mov_b32 s52, s13 @@ -630,8 +632,6 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr ; FIJI-NEXT: s_mov_b64 s[48:49], s[4:5] ; FIJI-NEXT: v_add_u32_e32 v3, vcc, v3, v4 ; FIJI-NEXT: s_mov_b64 s[54:55], exec -; FIJI-NEXT: s_addk_i32 s32, 0x400 -; FIJI-NEXT: v_writelane_b32 v40, s65, 17 ; FIJI-NEXT: .LBB18_1: ; =>This Inner Loop Header: Depth=1 ; FIJI-NEXT: v_readfirstlane_b32 s16, v0 ; FIJI-NEXT: v_readfirstlane_b32 s17, v1 @@ -657,25 +657,25 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr ; FIJI-NEXT: s_cbranch_execnz .LBB18_1 ; FIJI-NEXT: ; %bb.2: ; FIJI-NEXT: s_mov_b64 exec, s[54:55] +; FIJI-NEXT: v_readlane_b32 s30, v40, 16 ; FIJI-NEXT: v_mov_b32_e32 v0, v4 -; FIJI-NEXT: v_readlane_b32 s65, v40, 17 -; FIJI-NEXT: v_readlane_b32 s64, v40, 16 -; FIJI-NEXT: v_readlane_b32 s55, v40, 15 -; FIJI-NEXT: v_readlane_b32 s54, v40, 14 -; FIJI-NEXT: v_readlane_b32 s53, v40, 13 -; FIJI-NEXT: v_readlane_b32 s52, v40, 12 -; FIJI-NEXT: v_readlane_b32 s51, v40, 11 -; FIJI-NEXT: v_readlane_b32 s50, v40, 10 -; FIJI-NEXT: v_readlane_b32 s49, v40, 9 -; FIJI-NEXT: v_readlane_b32 s48, v40, 8 -; FIJI-NEXT: v_readlane_b32 s39, v40, 7 -; FIJI-NEXT: v_readlane_b32 s38, v40, 6 -; FIJI-NEXT: v_readlane_b32 s37, v40, 5 -; FIJI-NEXT: v_readlane_b32 s36, v40, 4 -; FIJI-NEXT: v_readlane_b32 s35, v40, 3 -; FIJI-NEXT: v_readlane_b32 s34, v40, 2 -; FIJI-NEXT: v_readlane_b32 s31, v40, 1 -; FIJI-NEXT: v_readlane_b32 s30, v40, 0 +; FIJI-NEXT: v_readlane_b32 s31, v40, 17 +; FIJI-NEXT: v_readlane_b32 s65, v40, 15 +; FIJI-NEXT: v_readlane_b32 s64, v40, 14 +; FIJI-NEXT: v_readlane_b32 s55, v40, 13 +; FIJI-NEXT: v_readlane_b32 s54, v40, 12 +; FIJI-NEXT: v_readlane_b32 s53, v40, 11 +; FIJI-NEXT: v_readlane_b32 s52, v40, 10 +; FIJI-NEXT: v_readlane_b32 s51, v40, 9 +; FIJI-NEXT: v_readlane_b32 s50, v40, 8 +; FIJI-NEXT: v_readlane_b32 s49, v40, 7 +; FIJI-NEXT: v_readlane_b32 s48, v40, 6 +; FIJI-NEXT: v_readlane_b32 s39, v40, 5 +; FIJI-NEXT: v_readlane_b32 s38, v40, 4 +; FIJI-NEXT: v_readlane_b32 s37, v40, 3 +; FIJI-NEXT: v_readlane_b32 s36, v40, 2 +; FIJI-NEXT: v_readlane_b32 s35, v40, 1 +; FIJI-NEXT: v_readlane_b32 s34, v40, 0 ; FIJI-NEXT: s_mov_b32 s32, s33 ; FIJI-NEXT: v_readlane_b32 s4, v40, 18 ; FIJI-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -694,23 +694,25 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr ; HAWAII-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; HAWAII-NEXT: s_mov_b64 exec, s[18:19] ; HAWAII-NEXT: v_writelane_b32 v40, s16, 18 -; HAWAII-NEXT: v_writelane_b32 v40, s30, 0 -; HAWAII-NEXT: v_writelane_b32 v40, s31, 1 -; HAWAII-NEXT: v_writelane_b32 v40, s34, 2 -; HAWAII-NEXT: v_writelane_b32 v40, s35, 3 -; HAWAII-NEXT: v_writelane_b32 v40, s36, 4 -; HAWAII-NEXT: v_writelane_b32 v40, s37, 5 -; HAWAII-NEXT: v_writelane_b32 v40, s38, 6 -; HAWAII-NEXT: v_writelane_b32 v40, s39, 7 -; HAWAII-NEXT: v_writelane_b32 v40, s48, 8 -; HAWAII-NEXT: v_writelane_b32 v40, s49, 9 -; HAWAII-NEXT: v_writelane_b32 v40, s50, 10 -; HAWAII-NEXT: v_writelane_b32 v40, s51, 11 -; HAWAII-NEXT: v_writelane_b32 v40, s52, 12 -; HAWAII-NEXT: v_writelane_b32 v40, s53, 13 -; HAWAII-NEXT: v_writelane_b32 v40, s54, 14 -; HAWAII-NEXT: v_writelane_b32 v40, s55, 15 -; HAWAII-NEXT: v_writelane_b32 v40, s64, 16 +; HAWAII-NEXT: s_addk_i32 s32, 0x400 +; HAWAII-NEXT: v_writelane_b32 v40, s34, 0 +; HAWAII-NEXT: v_writelane_b32 v40, s35, 1 +; HAWAII-NEXT: v_writelane_b32 v40, s36, 2 +; HAWAII-NEXT: v_writelane_b32 v40, s37, 3 +; HAWAII-NEXT: v_writelane_b32 v40, s38, 4 +; HAWAII-NEXT: v_writelane_b32 v40, s39, 5 +; HAWAII-NEXT: v_writelane_b32 v40, s48, 6 +; HAWAII-NEXT: v_writelane_b32 v40, s49, 7 +; HAWAII-NEXT: v_writelane_b32 v40, s50, 8 +; HAWAII-NEXT: v_writelane_b32 v40, s51, 9 +; HAWAII-NEXT: v_writelane_b32 v40, s52, 10 +; HAWAII-NEXT: v_writelane_b32 v40, s53, 11 +; HAWAII-NEXT: v_writelane_b32 v40, s54, 12 +; HAWAII-NEXT: v_writelane_b32 v40, s55, 13 +; HAWAII-NEXT: v_writelane_b32 v40, s64, 14 +; HAWAII-NEXT: v_writelane_b32 v40, s65, 15 +; HAWAII-NEXT: v_writelane_b32 v40, s30, 16 +; HAWAII-NEXT: v_writelane_b32 v40, s31, 17 ; HAWAII-NEXT: s_mov_b32 s50, s15 ; HAWAII-NEXT: s_mov_b32 s51, s14 ; HAWAII-NEXT: s_mov_b32 s52, s13 @@ -721,8 +723,6 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr ; HAWAII-NEXT: s_mov_b64 s[48:49], s[4:5] ; HAWAII-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; HAWAII-NEXT: s_mov_b64 s[54:55], exec -; HAWAII-NEXT: s_addk_i32 s32, 0x400 -; HAWAII-NEXT: v_writelane_b32 v40, s65, 17 ; HAWAII-NEXT: .LBB18_1: ; =>This Inner Loop Header: Depth=1 ; HAWAII-NEXT: v_readfirstlane_b32 s16, v0 ; HAWAII-NEXT: v_readfirstlane_b32 s17, v1 @@ -748,25 +748,25 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr ; HAWAII-NEXT: s_cbranch_execnz .LBB18_1 ; HAWAII-NEXT: ; %bb.2: ; HAWAII-NEXT: s_mov_b64 exec, s[54:55] +; HAWAII-NEXT: v_readlane_b32 s30, v40, 16 ; HAWAII-NEXT: v_mov_b32_e32 v0, v4 -; HAWAII-NEXT: v_readlane_b32 s65, v40, 17 -; HAWAII-NEXT: v_readlane_b32 s64, v40, 16 -; HAWAII-NEXT: v_readlane_b32 s55, v40, 15 -; HAWAII-NEXT: v_readlane_b32 s54, v40, 14 -; HAWAII-NEXT: v_readlane_b32 s53, v40, 13 -; HAWAII-NEXT: v_readlane_b32 s52, v40, 12 -; HAWAII-NEXT: v_readlane_b32 s51, v40, 11 -; HAWAII-NEXT: v_readlane_b32 s50, v40, 10 -; HAWAII-NEXT: v_readlane_b32 s49, v40, 9 -; HAWAII-NEXT: v_readlane_b32 s48, v40, 8 -; HAWAII-NEXT: v_readlane_b32 s39, v40, 7 -; HAWAII-NEXT: v_readlane_b32 s38, v40, 6 -; HAWAII-NEXT: v_readlane_b32 s37, v40, 5 -; HAWAII-NEXT: v_readlane_b32 s36, v40, 4 -; HAWAII-NEXT: v_readlane_b32 s35, v40, 3 -; HAWAII-NEXT: v_readlane_b32 s34, v40, 2 -; HAWAII-NEXT: v_readlane_b32 s31, v40, 1 -; HAWAII-NEXT: v_readlane_b32 s30, v40, 0 +; HAWAII-NEXT: v_readlane_b32 s31, v40, 17 +; HAWAII-NEXT: v_readlane_b32 s65, v40, 15 +; HAWAII-NEXT: v_readlane_b32 s64, v40, 14 +; HAWAII-NEXT: v_readlane_b32 s55, v40, 13 +; HAWAII-NEXT: v_readlane_b32 s54, v40, 12 +; HAWAII-NEXT: v_readlane_b32 s53, v40, 11 +; HAWAII-NEXT: v_readlane_b32 s52, v40, 10 +; HAWAII-NEXT: v_readlane_b32 s51, v40, 9 +; HAWAII-NEXT: v_readlane_b32 s50, v40, 8 +; HAWAII-NEXT: v_readlane_b32 s49, v40, 7 +; HAWAII-NEXT: v_readlane_b32 s48, v40, 6 +; HAWAII-NEXT: v_readlane_b32 s39, v40, 5 +; HAWAII-NEXT: v_readlane_b32 s38, v40, 4 +; HAWAII-NEXT: v_readlane_b32 s37, v40, 3 +; HAWAII-NEXT: v_readlane_b32 s36, v40, 2 +; HAWAII-NEXT: v_readlane_b32 s35, v40, 1 +; HAWAII-NEXT: v_readlane_b32 s34, v40, 0 ; HAWAII-NEXT: s_mov_b32 s32, s33 ; HAWAII-NEXT: v_readlane_b32 s4, v40, 18 ; HAWAII-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -785,23 +785,25 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-NEXT: v_writelane_b32 v40, s16, 18 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 -; GFX9-NEXT: v_writelane_b32 v40, s35, 3 -; GFX9-NEXT: v_writelane_b32 v40, s36, 4 -; GFX9-NEXT: v_writelane_b32 v40, s37, 5 -; GFX9-NEXT: v_writelane_b32 v40, s38, 6 -; GFX9-NEXT: v_writelane_b32 v40, s39, 7 -; GFX9-NEXT: v_writelane_b32 v40, s48, 8 -; GFX9-NEXT: v_writelane_b32 v40, s49, 9 -; GFX9-NEXT: v_writelane_b32 v40, s50, 10 -; GFX9-NEXT: v_writelane_b32 v40, s51, 11 -; GFX9-NEXT: v_writelane_b32 v40, s52, 12 -; GFX9-NEXT: v_writelane_b32 v40, s53, 13 -; GFX9-NEXT: v_writelane_b32 v40, s54, 14 -; GFX9-NEXT: v_writelane_b32 v40, s55, 15 -; GFX9-NEXT: v_writelane_b32 v40, s64, 16 +; GFX9-NEXT: s_addk_i32 s32, 0x400 +; GFX9-NEXT: v_writelane_b32 v40, s34, 0 +; GFX9-NEXT: v_writelane_b32 v40, s35, 1 +; GFX9-NEXT: v_writelane_b32 v40, s36, 2 +; GFX9-NEXT: v_writelane_b32 v40, s37, 3 +; GFX9-NEXT: v_writelane_b32 v40, s38, 4 +; GFX9-NEXT: v_writelane_b32 v40, s39, 5 +; GFX9-NEXT: v_writelane_b32 v40, s48, 6 +; GFX9-NEXT: v_writelane_b32 v40, s49, 7 +; GFX9-NEXT: v_writelane_b32 v40, s50, 8 +; GFX9-NEXT: v_writelane_b32 v40, s51, 9 +; GFX9-NEXT: v_writelane_b32 v40, s52, 10 +; GFX9-NEXT: v_writelane_b32 v40, s53, 11 +; GFX9-NEXT: v_writelane_b32 v40, s54, 12 +; GFX9-NEXT: v_writelane_b32 v40, s55, 13 +; GFX9-NEXT: v_writelane_b32 v40, s64, 14 +; GFX9-NEXT: v_writelane_b32 v40, s65, 15 +; GFX9-NEXT: v_writelane_b32 v40, s30, 16 +; GFX9-NEXT: v_writelane_b32 v40, s31, 17 ; GFX9-NEXT: s_mov_b32 s50, s15 ; GFX9-NEXT: s_mov_b32 s51, s14 ; GFX9-NEXT: s_mov_b32 s52, s13 @@ -812,8 +814,6 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr ; GFX9-NEXT: s_mov_b64 s[48:49], s[4:5] ; GFX9-NEXT: v_add_u32_e32 v3, v3, v4 ; GFX9-NEXT: s_mov_b64 s[54:55], exec -; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s65, 17 ; GFX9-NEXT: .LBB18_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: v_readfirstlane_b32 s16, v0 ; GFX9-NEXT: v_readfirstlane_b32 s17, v1 @@ -839,25 +839,25 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr ; GFX9-NEXT: s_cbranch_execnz .LBB18_1 ; GFX9-NEXT: ; %bb.2: ; GFX9-NEXT: s_mov_b64 exec, s[54:55] +; GFX9-NEXT: v_readlane_b32 s30, v40, 16 ; GFX9-NEXT: v_mov_b32_e32 v0, v4 -; GFX9-NEXT: v_readlane_b32 s65, v40, 17 -; GFX9-NEXT: v_readlane_b32 s64, v40, 16 -; GFX9-NEXT: v_readlane_b32 s55, v40, 15 -; GFX9-NEXT: v_readlane_b32 s54, v40, 14 -; GFX9-NEXT: v_readlane_b32 s53, v40, 13 -; GFX9-NEXT: v_readlane_b32 s52, v40, 12 -; GFX9-NEXT: v_readlane_b32 s51, v40, 11 -; GFX9-NEXT: v_readlane_b32 s50, v40, 10 -; GFX9-NEXT: v_readlane_b32 s49, v40, 9 -; GFX9-NEXT: v_readlane_b32 s48, v40, 8 -; GFX9-NEXT: v_readlane_b32 s39, v40, 7 -; GFX9-NEXT: v_readlane_b32 s38, v40, 6 -; GFX9-NEXT: v_readlane_b32 s37, v40, 5 -; GFX9-NEXT: v_readlane_b32 s36, v40, 4 -; GFX9-NEXT: v_readlane_b32 s35, v40, 3 -; GFX9-NEXT: v_readlane_b32 s34, v40, 2 -; GFX9-NEXT: v_readlane_b32 s31, v40, 1 -; GFX9-NEXT: v_readlane_b32 s30, v40, 0 +; GFX9-NEXT: v_readlane_b32 s31, v40, 17 +; GFX9-NEXT: v_readlane_b32 s65, v40, 15 +; GFX9-NEXT: v_readlane_b32 s64, v40, 14 +; GFX9-NEXT: v_readlane_b32 s55, v40, 13 +; GFX9-NEXT: v_readlane_b32 s54, v40, 12 +; GFX9-NEXT: v_readlane_b32 s53, v40, 11 +; GFX9-NEXT: v_readlane_b32 s52, v40, 10 +; GFX9-NEXT: v_readlane_b32 s51, v40, 9 +; GFX9-NEXT: v_readlane_b32 s50, v40, 8 +; GFX9-NEXT: v_readlane_b32 s49, v40, 7 +; GFX9-NEXT: v_readlane_b32 s48, v40, 6 +; GFX9-NEXT: v_readlane_b32 s39, v40, 5 +; GFX9-NEXT: v_readlane_b32 s38, v40, 4 +; GFX9-NEXT: v_readlane_b32 s37, v40, 3 +; GFX9-NEXT: v_readlane_b32 s36, v40, 2 +; GFX9-NEXT: v_readlane_b32 s35, v40, 1 +; GFX9-NEXT: v_readlane_b32 s34, v40, 0 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v40, 18 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll b/llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll index 08681484c65c2..8d4657571b258 100644 --- a/llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll +++ b/llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll @@ -53,44 +53,14 @@ entry: } define amdgpu_kernel void @foo(ptr noundef %fp) { -; OW-LABEL: define {{[^@]+}}@foo -; OW-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR1:[0-9]+]] { -; OW-NEXT: entry: -; OW-NEXT: [[FP_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -; OW-NEXT: store ptr [[FP]], ptr addrspace(5) [[FP_ADDR]], align 8 -; OW-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(5) [[FP_ADDR]], align 8 -; OW-NEXT: call void [[LOAD]]() -; OW-NEXT: ret void -; -; CW-LABEL: define {{[^@]+}}@foo -; CW-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR0]] { -; CW-NEXT: entry: -; CW-NEXT: [[FP_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -; CW-NEXT: store ptr [[FP]], ptr addrspace(5) [[FP_ADDR]], align 8 -; CW-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(5) [[FP_ADDR]], align 8 -; CW-NEXT: [[TMP0:%.*]] = icmp eq ptr [[LOAD]], @bar1 -; CW-NEXT: br i1 [[TMP0]], label [[TMP1:%.*]], label [[TMP2:%.*]] -; CW: 1: -; CW-NEXT: call void @bar1() -; CW-NEXT: br label [[TMP5:%.*]] -; CW: 2: -; CW-NEXT: br i1 true, label [[TMP3:%.*]], label [[TMP4:%.*]] -; CW: 3: -; CW-NEXT: call void @bar2() -; CW-NEXT: br label [[TMP5]] -; CW: 4: -; CW-NEXT: unreachable -; CW: 5: -; CW-NEXT: ret void -; -; NO-LABEL: define {{[^@]+}}@foo -; NO-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR0]] { -; NO-NEXT: entry: -; NO-NEXT: [[FP_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -; NO-NEXT: store ptr [[FP]], ptr addrspace(5) [[FP_ADDR]], align 8 -; NO-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(5) [[FP_ADDR]], align 8 -; NO-NEXT: call void [[LOAD]](), !callees [[META0:![0-9]+]] -; NO-NEXT: ret void +; CHECK-LABEL: define {{[^@]+}}@foo +; CHECK-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[FP_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +; CHECK-NEXT: store ptr [[FP]], ptr addrspace(5) [[FP_ADDR]], align 8 +; CHECK-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(5) [[FP_ADDR]], align 8 +; CHECK-NEXT: call void [[LOAD]]() +; CHECK-NEXT: ret void ; entry: %fp.addr = alloca ptr, addrspace(5) @@ -101,12 +71,10 @@ entry: } ;. -; NO: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -;. -; OW: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; OW: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" } -;. -; CW: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -;. -; NO: [[META0]] = !{ptr @bar1, ptr @bar2} +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" } ;. +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CW: {{.*}} +; NO: {{.*}} +; OW: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/smed3.ll b/llvm/test/CodeGen/AMDGPU/smed3.ll index a9fb77904c641..fc2797cdd19b8 100644 --- a/llvm/test/CodeGen/AMDGPU/smed3.ll +++ b/llvm/test/CodeGen/AMDGPU/smed3.ll @@ -684,8 +684,8 @@ bb: ; SI: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; FIXME: VI not matching med3 -; VI: v_min_i16 -; VI: v_max_i16 +; VI-DAG: v_min_i16 +; VI-DAG: v_max_i16 ; VI: v_min_i16 ; VI: v_max_i16 diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir index 9d25df4738709..cfa0ee97e83d0 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir @@ -17,6 +17,8 @@ body: | ; CHECK-LABEL: name: spill_a64_kill ; CHECK: liveins: $agpr0_agpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 @@ -42,6 +44,8 @@ body: | ; CHECK-LABEL: name: spill_a64_undef_sub1_killed ; CHECK: liveins: $agpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 @@ -65,6 +69,8 @@ body: | ; CHECK-LABEL: name: spill_a64_undef_sub0_killed ; CHECK: liveins: $agpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 @@ -84,7 +90,9 @@ machineFunctionInfo: body: | bb.0: ; CHECK-LABEL: name: spill_a32_undef - ; CHECK: S_ENDPGM 0 + ; CHECK: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: S_ENDPGM 0 SI_SPILL_A32_SAVE undef $agpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) S_ENDPGM 0 ... @@ -101,7 +109,9 @@ machineFunctionInfo: body: | bb.0: ; CHECK-LABEL: name: spill_a64_undef - ; CHECK: S_ENDPGM 0 + ; CHECK: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: S_ENDPGM 0 SI_SPILL_A64_SAVE undef $agpr0_agpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) S_ENDPGM 0 ... diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr.mir b/llvm/test/CodeGen/AMDGPU/spill-agpr.mir index 3f6956b83ae92..d4241fb0c53f1 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-agpr.mir @@ -38,6 +38,12 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0 ; GFX908-EXPANDED-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0 @@ -82,6 +88,12 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0 ; GFX90A-EXPANDED-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0 @@ -141,6 +153,12 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1 ; GFX908-EXPANDED-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; GFX908-EXPANDED-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1 @@ -181,6 +199,12 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1 ; GFX90A-EXPANDED-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 ; GFX90A-EXPANDED-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1 @@ -253,6 +277,9 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0 ; GFX908-EXPANDED-NEXT: $vgpr63 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec ; GFX908-EXPANDED-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) @@ -319,6 +346,9 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0 ; GFX90A-EXPANDED-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ; GFX90A-EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc @@ -402,6 +432,14 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2 ; GFX908-EXPANDED-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; GFX908-EXPANDED-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -444,6 +482,14 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2 ; GFX90A-EXPANDED-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 ; GFX90A-EXPANDED-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -503,6 +549,16 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3 ; GFX908-EXPANDED-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GFX908-EXPANDED-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -547,6 +603,16 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3 ; GFX90A-EXPANDED-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GFX90A-EXPANDED-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -608,6 +674,18 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4 ; GFX908-EXPANDED-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; GFX908-EXPANDED-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -654,6 +732,18 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4 ; GFX90A-EXPANDED-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 ; GFX90A-EXPANDED-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -717,6 +807,20 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; GFX908-EXPANDED-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; GFX908-EXPANDED-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -765,6 +869,20 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; GFX90A-EXPANDED-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 ; GFX90A-EXPANDED-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -830,6 +948,24 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; GFX908-EXPANDED-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; GFX908-EXPANDED-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -882,6 +1018,24 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; GFX90A-EXPANDED-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 ; GFX90A-EXPANDED-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -951,6 +1105,26 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 ; GFX908-EXPANDED-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 ; GFX908-EXPANDED-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1005,6 +1179,26 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 ; GFX90A-EXPANDED-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 ; GFX90A-EXPANDED-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1076,6 +1270,28 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 ; GFX908-EXPANDED-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 ; GFX908-EXPANDED-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1132,6 +1348,28 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 ; GFX90A-EXPANDED-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 ; GFX90A-EXPANDED-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1205,6 +1443,30 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 ; GFX908-EXPANDED-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 ; GFX908-EXPANDED-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1263,6 +1525,30 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 ; GFX90A-EXPANDED-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 ; GFX90A-EXPANDED-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1338,6 +1624,32 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 ; GFX908-EXPANDED-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 ; GFX908-EXPANDED-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1398,6 +1710,32 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 ; GFX90A-EXPANDED-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 ; GFX90A-EXPANDED-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1475,6 +1813,40 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; GFX908-EXPANDED-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; GFX908-EXPANDED-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1543,6 +1915,40 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; GFX90A-EXPANDED-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; GFX90A-EXPANDED-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1628,6 +2034,72 @@ body: | ; GFX908-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX908-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31 ; GFX908-EXPANDED-NEXT: {{ $}} + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX908-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; GFX908-EXPANDED-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; GFX908-EXPANDED-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec @@ -1728,6 +2200,72 @@ body: | ; GFX90A-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; GFX90A-EXPANDED-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31 ; GFX90A-EXPANDED-NEXT: {{ $}} + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX90A-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; GFX90A-EXPANDED-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 ; GFX90A-EXPANDED-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir index 24c631ce5e15f..7b3402494f39f 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir @@ -16,10 +16,15 @@ body: | ; CHECK: liveins: $sgpr50, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $vgpr63, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr50, 0, $vgpr63 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr50, $vgpr63, 0, 32 ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr52, 1, $vgpr63 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr52, $vgpr63, 1, 32 ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr53, 2, $vgpr63 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr53, $vgpr63, 2, 32 ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr54, 3, $vgpr63 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr54, $vgpr63, 3, 32 ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr55, 4, $vgpr63 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr55, $vgpr63, 4, 32 ; CHECK-NEXT: S_NOP 0, implicit $sgpr50 ; CHECK-NEXT: $sgpr50 = S_MOV_B32 0 ; CHECK-NEXT: S_NOP 0, implicit $sgpr52 diff --git a/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir b/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir index f4edafd9443ab..be5295cf2affd 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir @@ -22,8 +22,17 @@ body: | ; GCN-LABEL: name: spill_sgpr128_use_subreg ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 ; GCN-NEXT: $sgpr8_sgpr9 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr0, 0 ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr8_sgpr9 ; GCN-NEXT: renamable $sgpr1 = COPY $sgpr2 ; GCN-NEXT: $vgpr0 = IMPLICIT_DEF @@ -60,8 +69,16 @@ body: | ; GCN-LABEL: name: spill_sgpr128_use_kill ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 ; GCN-NEXT: $sgpr8_sgpr9 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr0, 0 ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr8_sgpr9 ; GCN-NEXT: renamable $sgpr1 = COPY $sgpr2 ; GCN-NEXT: $vgpr0 = IMPLICIT_DEF @@ -95,6 +112,10 @@ body: | ; GCN-LABEL: name: spill_vgpr128_use_subreg ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 ; GCN-NEXT: renamable $vgpr1 = COPY $vgpr2, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr1, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) @@ -125,6 +146,9 @@ body: | ; GCN-LABEL: name: spill_vgpr128_use_kill ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 ; GCN-NEXT: renamable $vgpr1 = COPY $vgpr2, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr1, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) diff --git a/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir b/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir index bb87b6e52da89..cd9a4d07b870d 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir @@ -30,6 +30,66 @@ body: | ; GFX950-LABEL: name: full_copy ; GFX950: liveins: $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27, $agpr28, $agpr29 ; GFX950-NEXT: {{ $}} + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 ; GFX950-NEXT: renamable $agpr0_agpr1 = IMPLICIT_DEF ; GFX950-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; GFX950-NEXT: renamable $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27 = IMPLICIT_DEF @@ -136,6 +196,66 @@ body: | ; GFX950-LABEL: name: partial_copy ; GFX950: liveins: $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27 ; GFX950-NEXT: {{ $}} + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; GFX950-NEXT: renamable $agpr0_agpr1 = IMPLICIT_DEF ; GFX950-NEXT: renamable $agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; GFX950-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF @@ -241,6 +361,68 @@ body: | ; GFX950-LABEL: name: full_spill ; GFX950: liveins: $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25 ; GFX950-NEXT: {{ $}} + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; GFX950-NEXT: renamable $agpr0_agpr1 = IMPLICIT_DEF ; GFX950-NEXT: renamable $agpr26_agpr27 = IMPLICIT_DEF ; GFX950-NEXT: renamable $agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir index 85a615c3d8ae8..866ce8a0c0293 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir @@ -13,6 +13,7 @@ body: | ; CHECK: liveins: $sgpr50, $vgpr63 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr50, 0, $vgpr63 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr50, $vgpr63, 0, 32 ; CHECK-NEXT: S_NOP 0, implicit $sgpr50 ; CHECK-NEXT: $sgpr50 = S_MOV_B32 0 S_NOP 0, implicit $sgpr50 diff --git a/llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir b/llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir index fa3fd3bc6da5b..b0be5676e26a2 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir @@ -56,21 +56,37 @@ body: | ; GCN: liveins: $sgpr10, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $vgpr63, $sgpr30_sgpr31, $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71, $sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79, $sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87, $sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr64, 0, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr63, 0, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr65, 1, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr63, 1, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr66, 2, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr63, 2, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr67, 3, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr63, 3, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr68, 4, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr63, 4, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr69, 5, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr69, $vgpr63, 5, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr70, 6, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr70, $vgpr63, 6, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr71, 7, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr71, $vgpr63, 7, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr80, 8, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr80, $vgpr63, 8, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr81, 9, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr81, $vgpr63, 9, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr82, 10, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr82, $vgpr63, 10, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr83, 11, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr83, $vgpr63, 11, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr84, 12, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr84, $vgpr63, 12, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr85, 13, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr85, $vgpr63, 13, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr86, 14, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr86, $vgpr63, 14, 32 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr87, 15, $vgpr63 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr87, $vgpr63, 15, 32 ; GCN-NEXT: S_NOP 0 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]] diff --git a/llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir b/llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir index 6e8a5126ca823..cfa09c149e4c6 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir @@ -21,6 +21,12 @@ body: | ; GCN-LABEL: name: shift_back_exec_copy_reserved_reg ; GCN: liveins: $sgpr30_sgpr31, $vgpr0 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, killed $vgpr0 ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr31, 1, killed $vgpr0 ; GCN-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec @@ -58,6 +64,14 @@ body: | ; GCN-LABEL: name: spill_exec_copy_reserved_reg ; GCN: liveins: $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr30_sgpr31, $vcc, $vgpr0 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, killed $vgpr0 ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr31, 1, killed $vgpr0 ; GCN-NEXT: $sgpr40_sgpr41 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir b/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir index 639bf6a6d550c..3531b3dd75792 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir @@ -40,6 +40,8 @@ body: | ; GFX9-LABEL: name: check_vcc ; GFX9: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr9 ; GFX9-NEXT: {{ $}} + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX9-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX9-NEXT: $sgpr33 = S_MOV_B32 0 ; GFX9-NEXT: $sgpr12 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15 ; GFX9-NEXT: $sgpr13 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15 @@ -77,6 +79,8 @@ body: | ; GFX10-LABEL: name: check_vcc ; GFX10: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr9 ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX10-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX10-NEXT: $sgpr33 = S_MOV_B32 0 ; GFX10-NEXT: $sgpr96 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 ; GFX10-NEXT: $sgpr97 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 @@ -114,6 +118,8 @@ body: | ; GFX11-LABEL: name: check_vcc ; GFX11: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7 ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GFX11-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GFX11-NEXT: $sgpr33 = S_MOV_B32 0 ; GFX11-NEXT: $vcc = IMPLICIT_DEF ; GFX11-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec diff --git a/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir b/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir index beeb9b2df8b01..a5d029a532f63 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir @@ -16,6 +16,12 @@ body: | ; GCN-LABEL: name: partial_spill_v128_1_of_4 ; GCN: liveins: $agpr30, $agpr31, $agpr28_agpr29, $agpr24_agpr25_agpr26_agpr27, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s96) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr31, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 @@ -41,6 +47,12 @@ body: | ; GCN-LABEL: name: partial_spill_v128_2_of_4 ; GCN: liveins: $agpr30, $agpr31, $agpr28_agpr29, $agpr24_agpr25_agpr26_agpr27, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s64) into %stack.0, align 4, addrspace 5) @@ -68,6 +80,12 @@ body: | ; GCN-LABEL: name: partial_spill_v128_3_of_4 ; GCN: liveins: $agpr28, $agpr29, $agpr30, $agpr31, $agpr24_agpr25_agpr26_agpr27, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 ; GCN-NEXT: $agpr29 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 @@ -97,6 +115,16 @@ body: | ; GCN-LABEL: name: full_spill_v128 ; GCN: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; GCN-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 @@ -126,6 +154,12 @@ body: | ; GCN-LABEL: name: partial_spill_a128_1_of_4 ; GCN: liveins: $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr52_vgpr53, $vgpr48_vgpr49_vgpr50_vgpr51, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s96) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 @@ -151,6 +185,12 @@ body: | ; GCN-LABEL: name: partial_spill_a128_2_of_4 ; GCN: liveins: $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr52_vgpr53, $vgpr48_vgpr49_vgpr50_vgpr51, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; GCN-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s64) into %stack.0, align 4, addrspace 5) @@ -178,6 +218,12 @@ body: | ; GCN-LABEL: name: partial_spill_a128_3_of_4 ; GCN: liveins: $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr48_vgpr49_vgpr50_vgpr51, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; GCN-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 @@ -207,6 +253,16 @@ body: | ; GCN-LABEL: name: full_spill_a128 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; GCN-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 diff --git a/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll b/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll index bfadfd860edf6..94e5f936a35fd 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll +++ b/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll @@ -14,15 +14,15 @@ define i32 @non_entry_func(i32 %x) { ; CHECK-NEXT: scratch_store_b32 off, v2, s32 offset:100 ; 4-byte Folded Spill ; CHECK-NEXT: s_wait_alu 0xfffe ; CHECK-NEXT: s_mov_b32 exec_lo, s0 -; CHECK-NEXT: v_writelane_b32 v2, s48, 0 ; CHECK-NEXT: s_mov_b32 m0, 0x110003 -; CHECK-NEXT: v_mov_b32_e32 v1, v0 ; CHECK-NEXT: ; transferring at most v40 v41 v56 v60 ; 128-byte Folded Spill ; CHECK-NEXT: scratch_store_block off, v[40:71], s32 offset:4 ; CHECK-NEXT: s_mov_b32 m0, 1 -; CHECK-NEXT: v_writelane_b32 v2, s49, 1 ; CHECK-NEXT: ; transferring at most v120 ; 128-byte Folded Spill ; CHECK-NEXT: scratch_store_block off, v[120:151], s32 +; CHECK-NEXT: v_writelane_b32 v2, s48, 0 +; CHECK-NEXT: v_mov_b32_e32 v1, v0 +; CHECK-NEXT: v_writelane_b32 v2, s49, 1 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: s_nop ; CHECK-NEXT: ;;#ASMEND diff --git a/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir b/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir index 0c694d9f49e18..79a95cbf52391 100644 --- a/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir +++ b/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir @@ -16,6 +16,9 @@ body: | ; EXPANDED: bb.0: ; EXPANDED-NEXT: successors: %bb.1(0x80000000) ; EXPANDED-NEXT: {{ $}} + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) ; EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 @@ -62,6 +65,9 @@ body: | ; EXPANDED: bb.0: ; EXPANDED-NEXT: successors: %bb.1(0x80000000) ; EXPANDED-NEXT: {{ $}} + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) ; EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 @@ -110,6 +116,9 @@ body: | ; EXPANDED: bb.0: ; EXPANDED-NEXT: successors: %bb.1(0x80000000) ; EXPANDED-NEXT: {{ $}} + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) ; EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 diff --git a/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll b/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll index e962d1bad9779..1184d1a94c3dc 100644 --- a/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll @@ -142,8 +142,8 @@ define void @spill_more_than_wavesize_csr_sgprs_with_stack_object() { ; CHECK-NEXT: v_writelane_b32 v1, s99, 32 ; CHECK-NEXT: v_writelane_b32 v1, s100, 33 ; CHECK-NEXT: v_writelane_b32 v1, s101, 34 -; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_writelane_b32 v1, s102, 35 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ;;#ASMSTART diff --git a/llvm/test/CodeGen/AMDGPU/spillv16.mir b/llvm/test/CodeGen/AMDGPU/spillv16.mir index 05569bf394c43..7be0bfa3e3fc8 100644 --- a/llvm/test/CodeGen/AMDGPU/spillv16.mir +++ b/llvm/test/CodeGen/AMDGPU/spillv16.mir @@ -32,6 +32,9 @@ body: | ; EXPANDED: bb.0: ; EXPANDED-NEXT: successors: %bb.1(0x80000000) ; EXPANDED-NEXT: {{ $}} + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 2, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, addrspace 5) ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, addrspace 5) diff --git a/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll index 109c7d638f924..23f64b3353ba5 100644 --- a/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll +++ b/llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -experimental-debug-variable-locations=false < %s | FileCheck -check-prefix=GCN %s ; Make sure dbg_value reports something for argument registers when they are split into multiple registers define hidden <4 x float> @split_v4f32_arg(<4 x float> returned %arg) local_unnamed_addr #0 !dbg !7 { @@ -13,6 +13,8 @@ define hidden <4 x float> @split_v4f32_arg(<4 x float> returned %arg) local_unna ; GCN-NEXT: ;DEBUG_VALUE: split_v4f32_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 64 32] $vgpr2 ; GCN-NEXT: ;DEBUG_VALUE: split_v4f32_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 32 32] $vgpr1 ; GCN-NEXT: ;DEBUG_VALUE: split_v4f32_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 0 32] $vgpr0 +; GCN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GCN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: .Ltmp0: ; GCN-NEXT: .loc 0 4 5 prologue_end ; /tmp/dbg.cl:4:5 @@ -35,6 +37,12 @@ define hidden <4 x float> @split_v4f32_multi_arg(<4 x float> %arg0, <2 x float> ; GCN-NEXT: ;DEBUG_VALUE: split_v4f32_multi_arg:arg0 <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 64 32] $vgpr2 ; GCN-NEXT: ;DEBUG_VALUE: split_v4f32_multi_arg:arg0 <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 32 32] $vgpr1 ; GCN-NEXT: ;DEBUG_VALUE: split_v4f32_multi_arg:arg0 <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 0 32] $vgpr0 +; GCN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GCN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GCN-NEXT: .cfi_undefined 2560 +; GCN-NEXT: .cfi_undefined 2561 +; GCN-NEXT: .cfi_undefined 2562 +; GCN-NEXT: .cfi_undefined 2563 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: .Ltmp2: ; GCN-NEXT: .loc 0 8 17 prologue_end ; /tmp/dbg.cl:8:17 @@ -65,6 +73,8 @@ define hidden <4 x half> @split_v4f16_arg(<4 x half> returned %arg) local_unname ; GCN-NEXT: ; %bb.0: ; GCN-NEXT: ;DEBUG_VALUE: split_v4f16_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 32 32] $vgpr1 ; GCN-NEXT: ;DEBUG_VALUE: split_v4f16_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 0 32] $vgpr0 +; GCN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GCN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: .Ltmp8: ; GCN-NEXT: .loc 0 12 5 prologue_end ; /tmp/dbg.cl:12:5 @@ -83,6 +93,8 @@ define hidden double @split_f64_arg(double returned %arg) local_unnamed_addr #0 ; GCN-NEXT: ; %bb.0: ; GCN-NEXT: ;DEBUG_VALUE: split_f64_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 32 32] $vgpr1 ; GCN-NEXT: ;DEBUG_VALUE: split_f64_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 0 32] $vgpr0 +; GCN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GCN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: .Ltmp10: ; GCN-NEXT: .loc 0 16 5 prologue_end ; /tmp/dbg.cl:16:5 @@ -103,6 +115,8 @@ define hidden <2 x double> @split_v2f64_arg(<2 x double> returned %arg) local_un ; GCN-NEXT: ;DEBUG_VALUE: split_v2f64_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 64 32] $vgpr2 ; GCN-NEXT: ;DEBUG_VALUE: split_v2f64_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 32 32] $vgpr1 ; GCN-NEXT: ;DEBUG_VALUE: split_v2f64_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 0 32] $vgpr0 +; GCN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GCN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: .Ltmp12: ; GCN-NEXT: .loc 0 20 5 prologue_end ; /tmp/dbg.cl:20:5 @@ -121,6 +135,8 @@ define hidden i64 @split_i64_arg(i64 returned %arg) local_unnamed_addr #0 !dbg ! ; GCN-NEXT: ; %bb.0: ; GCN-NEXT: ;DEBUG_VALUE: split_i64_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 32 32] $vgpr1 ; GCN-NEXT: ;DEBUG_VALUE: split_i64_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 0 32] $vgpr0 +; GCN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GCN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: .Ltmp14: ; GCN-NEXT: .loc 0 24 5 prologue_end ; /tmp/dbg.cl:24:5 @@ -139,6 +155,8 @@ define hidden ptr addrspace(1) @split_ptr_arg(ptr addrspace(1) readnone returned ; GCN-NEXT: ; %bb.0: ; GCN-NEXT: ;DEBUG_VALUE: split_ptr_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 32 32] $vgpr1 ; GCN-NEXT: ;DEBUG_VALUE: split_ptr_arg:arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef, DW_OP_LLVM_fragment 0 32] $vgpr0 +; GCN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GCN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: .Ltmp16: ; GCN-NEXT: .loc 0 28 5 prologue_end ; /tmp/dbg.cl:28:5 diff --git a/llvm/test/CodeGen/AMDGPU/splitkit.mir b/llvm/test/CodeGen/AMDGPU/splitkit.mir index dd3abf6007854..3065fce538157 100644 --- a/llvm/test/CodeGen/AMDGPU/splitkit.mir +++ b/llvm/test/CodeGen/AMDGPU/splitkit.mir @@ -38,24 +38,22 @@ body: | # LiveRange splitting should split this into 2 intervals with the second getting # allocated to sgpr0_sgpr1 and the first to something else so we see two copies # in between for the two subregisters that are alive. +# CHECK-LABEL: name: func1 +# CHECK: [[REG0:\$sgpr[0-9]+]] = COPY $sgpr0 +# CHECK: [[REG1:\$sgpr[0-9]+]] = COPY $sgpr2 +# CHECK: S_NOP 0 +# CHECK: S_NOP 0, implicit renamable [[REG0]] +# CHECK: S_NOP 0, implicit renamable [[REG1]] +# CHECK: $sgpr0 = COPY killed renamable [[REG0]] +# CHECK: $sgpr2 = COPY renamable [[REG1]] +# CHECK: S_NOP +# CHECK: S_NOP 0, implicit renamable $sgpr0 +# CHECK: S_NOP 0, implicit killed renamable $sgpr2 name: func1 tracksRegLiveness: true body: | bb.0: liveins: $sgpr0, $sgpr1, $sgpr2 - ; CHECK-LABEL: name: func1 - ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: renamable $sgpr4 = COPY $sgpr0 - ; CHECK-NEXT: renamable $sgpr6 = COPY $sgpr2 - ; CHECK-NEXT: S_NOP 0, implicit-def dead $sgpr0, implicit-def dead $sgpr1 - ; CHECK-NEXT: S_NOP 0, implicit renamable $sgpr4 - ; CHECK-NEXT: S_NOP 0, implicit renamable $sgpr6 - ; CHECK-NEXT: renamable $sgpr0 = COPY killed renamable $sgpr4 - ; CHECK-NEXT: renamable $sgpr2 = COPY renamable $sgpr6 - ; CHECK-NEXT: S_NOP 0, implicit-def dead $sgpr4, implicit-def dead $sgpr5, implicit-def dead $sgpr6, implicit-def dead $sgpr7, implicit-def dead $sgpr8, implicit-def dead $sgpr9, implicit-def dead $sgpr10, implicit-def dead $sgpr11, implicit-def dead $sgpr12, implicit-def dead $sgpr13, implicit-def dead $sgpr14, implicit-def dead $sgpr15, implicit-def dead $vcc_lo, implicit-def dead $vcc_hi - ; CHECK-NEXT: S_NOP 0, implicit renamable $sgpr0 - ; CHECK-NEXT: S_NOP 0, implicit killed renamable $sgpr2 undef %0.sub0 : sgpr_128 = COPY $sgpr0 %0.sub2 = COPY $sgpr2 diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll index 9cb22dad86b88..d57a9ca42efa5 100644 --- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll +++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll @@ -32,7 +32,6 @@ define void @needs_align16_default_stack_align(i32 %idx) #0 { ; GCN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_setpc_b64 s[30:31] -; GCN: ; ScratchSize: 144 %alloca.align16 = alloca [8 x <4 x i32>], align 16, addrspace(5) %gep0 = getelementptr inbounds [8 x <4 x i32>], ptr addrspace(5) %alloca.align16, i32 0, i32 %idx store volatile <4 x i32> , ptr addrspace(5) %gep0, align 16 @@ -46,6 +45,8 @@ define void @needs_align16_stack_align4(i32 %idx) #2 { ; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0x3c0 ; GCN-NEXT: s_and_b32 s33, s33, 0xfffffc00 +; GCN-NEXT: s_mov_b32 s5, s34 +; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v2 @@ -58,8 +59,6 @@ define void @needs_align16_stack_align4(i32 %idx) #2 { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_or_b32_e32 v1, 8, v0 ; GCN-NEXT: v_mov_b32_e32 v2, 3 -; GCN-NEXT: s_mov_b32 s5, s34 -; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_addk_i32 s32, 0x2800 ; GCN-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) @@ -71,7 +70,6 @@ define void @needs_align16_stack_align4(i32 %idx) #2 { ; GCN-NEXT: s_mov_b32 s34, s5 ; GCN-NEXT: s_mov_b32 s33, s4 ; GCN-NEXT: s_setpc_b64 s[30:31] -; GCN: ; ScratchSize: 160 %alloca.align16 = alloca [8 x <4 x i32>], align 16, addrspace(5) %gep0 = getelementptr inbounds [8 x <4 x i32>], ptr addrspace(5) %alloca.align16, i32 0, i32 %idx store volatile <4 x i32> , ptr addrspace(5) %gep0, align 16 @@ -86,6 +84,8 @@ define void @needs_align32(i32 %idx) #0 { ; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0x7c0 ; GCN-NEXT: s_and_b32 s33, s33, 0xfffff800 +; GCN-NEXT: s_mov_b32 s5, s34 +; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v2 @@ -98,8 +98,6 @@ define void @needs_align32(i32 %idx) #0 { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_or_b32_e32 v1, 8, v0 ; GCN-NEXT: v_mov_b32_e32 v2, 3 -; GCN-NEXT: s_mov_b32 s5, s34 -; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_addk_i32 s32, 0x3000 ; GCN-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) @@ -111,7 +109,6 @@ define void @needs_align32(i32 %idx) #0 { ; GCN-NEXT: s_mov_b32 s34, s5 ; GCN-NEXT: s_mov_b32 s33, s4 ; GCN-NEXT: s_setpc_b64 s[30:31] -; GCN: ; ScratchSize: 192 %alloca.align16 = alloca [8 x <4 x i32>], align 32, addrspace(5) %gep0 = getelementptr inbounds [8 x <4 x i32>], ptr addrspace(5) %alloca.align16, i32 0, i32 %idx store volatile <4 x i32> , ptr addrspace(5) %gep0, align 32 @@ -125,10 +122,10 @@ define void @force_realign4(i32 %idx) #1 { ; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0xc0 ; GCN-NEXT: s_and_b32 s33, s33, 0xffffff00 -; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s33 ; GCN-NEXT: s_mov_b32 s5, s34 ; GCN-NEXT: s_mov_b32 s34, s32 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s33 ; GCN-NEXT: s_addk_i32 s32, 0xd00 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_mov_b32_e32 v1, 3 @@ -138,7 +135,6 @@ define void @force_realign4(i32 %idx) #1 { ; GCN-NEXT: s_mov_b32 s34, s5 ; GCN-NEXT: s_mov_b32 s33, s4 ; GCN-NEXT: s_setpc_b64 s[30:31] -; GCN: ; ScratchSize: 52 %alloca.align16 = alloca [8 x i32], align 4, addrspace(5) %gep0 = getelementptr inbounds [8 x i32], ptr addrspace(5) %alloca.align16, i32 0, i32 %idx store volatile i32 3, ptr addrspace(5) %gep0, align 4 @@ -295,28 +291,28 @@ define void @func_call_align1024_bp_gets_vgpr_spill(<32 x i32> %a, i32 %b) #0 { ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:1028 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 2 -; GCN-NEXT: v_mov_b32_e32 v32, 0 ; GCN-NEXT: v_writelane_b32 v40, s34, 3 ; GCN-NEXT: s_mov_b32 s34, s32 +; GCN-NEXT: v_writelane_b32 v40, s30, 0 +; GCN-NEXT: s_add_i32 s32, s32, 0x30000 +; GCN-NEXT: v_writelane_b32 v40, s31, 1 +; GCN-NEXT: v_mov_b32_e32 v32, 0 ; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:1024 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s34 ; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s34 offset:4 -; GCN-NEXT: s_add_i32 s32, s32, 0x30000 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, extern_func@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, extern_func@gotpcrel32@hi+12 ; GCN-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: s_waitcnt vmcnt(1) ; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; GCN-NEXT: s_waitcnt vmcnt(1) ; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-NEXT: s_mov_b32 s32, s34 ; GCN-NEXT: v_readlane_b32 s4, v40, 2 ; GCN-NEXT: v_readlane_b32 s34, v40, 3 @@ -346,8 +342,8 @@ define i32 @needs_align1024_stack_args_used_inside_loop(ptr addrspace(5) nocaptu ; GCN-NEXT: s_mov_b32 s11, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0xffc0 ; GCN-NEXT: s_mov_b32 s14, s34 -; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_and_b32 s33, s33, 0xffff0000 +; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s34 ; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: s_mov_b32 s10, 0 @@ -416,12 +412,12 @@ define void @no_free_scratch_sgpr_for_bp_copy(<32 x i32> %a, i32 %b) #0 { ; GCN-LABEL: no_free_scratch_sgpr_for_bp_copy: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s41, s34 -; GCN-NEXT: s_mov_b32 s34, s32 -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4 ; GCN-NEXT: s_mov_b32 s40, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0x1fc0 ; GCN-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GCN-NEXT: s_mov_b32 s41, s34 +; GCN-NEXT: s_mov_b32 s34, s32 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4 ; GCN-NEXT: s_addk_i32 s32, 0x6000 ; GCN-NEXT: s_mov_b32 s32, s34 ; GCN-NEXT: s_mov_b32 s34, s41 @@ -457,7 +453,7 @@ define void @no_free_regs_spill_bp_to_memory(<32 x i32> %a, i32 %b) #5 { ; GCN-NEXT: v_writelane_b32 v39, s4, 32 ; GCN-NEXT: v_writelane_b32 v39, s34, 33 ; GCN-NEXT: s_mov_b32 s34, s32 -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4 +; GCN-NEXT: s_addk_i32 s32, 0x6000 ; GCN-NEXT: v_writelane_b32 v39, s39, 0 ; GCN-NEXT: v_writelane_b32 v39, s48, 1 ; GCN-NEXT: v_writelane_b32 v39, s49, 2 @@ -489,8 +485,8 @@ define void @no_free_regs_spill_bp_to_memory(<32 x i32> %a, i32 %b) #5 { ; GCN-NEXT: v_writelane_b32 v39, s99, 28 ; GCN-NEXT: v_writelane_b32 v39, s100, 29 ; GCN-NEXT: v_writelane_b32 v39, s101, 30 -; GCN-NEXT: s_addk_i32 s32, 0x6000 ; GCN-NEXT: v_writelane_b32 v39, s102, 31 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4 ; GCN-NEXT: s_mov_b32 s32, s34 ; GCN-NEXT: v_readlane_b32 s34, v39, 33 ; GCN-NEXT: s_waitcnt vmcnt(0) @@ -580,7 +576,7 @@ define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i ; GCN-NEXT: v_writelane_b32 v39, s4, 32 ; GCN-NEXT: v_writelane_b32 v39, s34, 33 ; GCN-NEXT: s_mov_b32 s34, s32 -; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4 +; GCN-NEXT: s_add_i32 s32, s32, 0x46000 ; GCN-NEXT: v_writelane_b32 v39, s39, 0 ; GCN-NEXT: v_writelane_b32 v39, s48, 1 ; GCN-NEXT: v_writelane_b32 v39, s49, 2 @@ -612,9 +608,9 @@ define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i ; GCN-NEXT: v_writelane_b32 v39, s99, 28 ; GCN-NEXT: v_writelane_b32 v39, s100, 29 ; GCN-NEXT: v_writelane_b32 v39, s101, 30 -; GCN-NEXT: v_mov_b32_e32 v1, 0x1080 -; GCN-NEXT: s_add_i32 s32, s32, 0x46000 ; GCN-NEXT: v_writelane_b32 v39, s102, 31 +; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4 +; GCN-NEXT: v_mov_b32_e32 v1, 0x1080 ; GCN-NEXT: s_mov_b32 s32, s34 ; GCN-NEXT: v_readlane_b32 s34, v39, 33 ; GCN-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll b/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll index d2394bab82c77..70bcb99e05777 100644 --- a/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll +++ b/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll @@ -1270,24 +1270,24 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() { ; WAVE32-OPT-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill ; WAVE32-OPT-NEXT: s_mov_b32 exec_lo, s16 ; WAVE32-OPT-NEXT: v_writelane_b32 v32, s30, 0 +; WAVE32-OPT-NEXT: s_addk_i32 s32, 0x1200 +; WAVE32-OPT-NEXT: v_writelane_b32 v32, s31, 1 ; WAVE32-OPT-NEXT: v_mov_b32_e32 v0, 42 ; WAVE32-OPT-NEXT: v_mov_b32_e32 v1, 17 -; WAVE32-OPT-NEXT: s_addk_i32 s32, 0x1200 -; WAVE32-OPT-NEXT: s_mov_b32 s17, stack_passed_argument@abs32@hi ; WAVE32-OPT-NEXT: s_mov_b32 s18, s32 +; WAVE32-OPT-NEXT: s_mov_b32 s17, stack_passed_argument@abs32@hi ; WAVE32-OPT-NEXT: s_mov_b32 s16, stack_passed_argument@abs32@lo -; WAVE32-OPT-NEXT: v_writelane_b32 v32, s31, 1 ; WAVE32-OPT-NEXT: s_lshr_b32 s19, s18, 5 ; WAVE32-OPT-NEXT: buffer_store_dword v0, off, s[0:3], s33 ; WAVE32-OPT-NEXT: s_waitcnt_vscnt null, 0x0 ; WAVE32-OPT-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; WAVE32-OPT-NEXT: s_swappc_b64 s[30:31], s[16:17] ; WAVE32-OPT-NEXT: s_mov_b32 s32, s18 +; WAVE32-OPT-NEXT: v_readlane_b32 s30, v32, 0 ; WAVE32-OPT-NEXT: ;;#ASMSTART ; WAVE32-OPT-NEXT: ; use s19 ; WAVE32-OPT-NEXT: ;;#ASMEND ; WAVE32-OPT-NEXT: v_readlane_b32 s31, v32, 1 -; WAVE32-OPT-NEXT: v_readlane_b32 s30, v32, 0 ; WAVE32-OPT-NEXT: s_mov_b32 s32, s33 ; WAVE32-OPT-NEXT: s_xor_saveexec_b32 s4, -1 ; WAVE32-OPT-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload @@ -1305,24 +1305,24 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() { ; WAVE64-OPT-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill ; WAVE64-OPT-NEXT: s_mov_b64 exec, s[16:17] ; WAVE64-OPT-NEXT: v_writelane_b32 v32, s30, 0 +; WAVE64-OPT-NEXT: s_addk_i32 s32, 0x2400 +; WAVE64-OPT-NEXT: v_writelane_b32 v32, s31, 1 ; WAVE64-OPT-NEXT: v_mov_b32_e32 v0, 42 ; WAVE64-OPT-NEXT: v_mov_b32_e32 v1, 17 -; WAVE64-OPT-NEXT: s_addk_i32 s32, 0x2400 -; WAVE64-OPT-NEXT: s_mov_b32 s17, stack_passed_argument@abs32@hi ; WAVE64-OPT-NEXT: s_mov_b32 s18, s32 +; WAVE64-OPT-NEXT: s_mov_b32 s17, stack_passed_argument@abs32@hi ; WAVE64-OPT-NEXT: s_mov_b32 s16, stack_passed_argument@abs32@lo -; WAVE64-OPT-NEXT: v_writelane_b32 v32, s31, 1 ; WAVE64-OPT-NEXT: s_lshr_b32 s19, s18, 6 ; WAVE64-OPT-NEXT: buffer_store_dword v0, off, s[0:3], s33 ; WAVE64-OPT-NEXT: s_waitcnt_vscnt null, 0x0 ; WAVE64-OPT-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; WAVE64-OPT-NEXT: s_swappc_b64 s[30:31], s[16:17] ; WAVE64-OPT-NEXT: s_mov_b32 s32, s18 +; WAVE64-OPT-NEXT: v_readlane_b32 s30, v32, 0 ; WAVE64-OPT-NEXT: ;;#ASMSTART ; WAVE64-OPT-NEXT: ; use s19 ; WAVE64-OPT-NEXT: ;;#ASMEND ; WAVE64-OPT-NEXT: v_readlane_b32 s31, v32, 1 -; WAVE64-OPT-NEXT: v_readlane_b32 s30, v32, 0 ; WAVE64-OPT-NEXT: s_mov_b32 s32, s33 ; WAVE64-OPT-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; WAVE64-OPT-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload @@ -1431,8 +1431,8 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() { ; WAVE32-O0-NEXT: ; use s5 ; WAVE32-O0-NEXT: ;;#ASMEND ; WAVE32-O0-NEXT: s_mov_b32 s32, s4 -; WAVE32-O0-NEXT: v_readlane_b32 s31, v32, 1 ; WAVE32-O0-NEXT: v_readlane_b32 s30, v32, 0 +; WAVE32-O0-NEXT: v_readlane_b32 s31, v32, 1 ; WAVE32-O0-NEXT: s_mov_b32 s32, s33 ; WAVE32-O0-NEXT: s_xor_saveexec_b32 s4, -1 ; WAVE32-O0-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload @@ -1542,8 +1542,8 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() { ; WAVE64-O0-NEXT: ; use s5 ; WAVE64-O0-NEXT: ;;#ASMEND ; WAVE64-O0-NEXT: s_mov_b32 s32, s4 -; WAVE64-O0-NEXT: v_readlane_b32 s31, v32, 1 ; WAVE64-O0-NEXT: v_readlane_b32 s30, v32, 0 +; WAVE64-O0-NEXT: v_readlane_b32 s31, v32, 1 ; WAVE64-O0-NEXT: s_mov_b32 s32, s33 ; WAVE64-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; WAVE64-O0-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload @@ -1653,8 +1653,8 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() { ; WAVE32-WWM-PREALLOC-NEXT: ; use s5 ; WAVE32-WWM-PREALLOC-NEXT: ;;#ASMEND ; WAVE32-WWM-PREALLOC-NEXT: s_mov_b32 s32, s4 -; WAVE32-WWM-PREALLOC-NEXT: v_readlane_b32 s31, v33, 1 ; WAVE32-WWM-PREALLOC-NEXT: v_readlane_b32 s30, v33, 0 +; WAVE32-WWM-PREALLOC-NEXT: v_readlane_b32 s31, v33, 1 ; WAVE32-WWM-PREALLOC-NEXT: s_mov_b32 s32, s33 ; WAVE32-WWM-PREALLOC-NEXT: s_xor_saveexec_b32 s4, -1 ; WAVE32-WWM-PREALLOC-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll b/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll index ebd4bc881f2af..249d2dd85243b 100644 --- a/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll +++ b/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll @@ -184,18 +184,18 @@ define void @outgoing_f16_arg(ptr %ptr) #0 { ; GFX7-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[18:19] -; GFX7-NEXT: flat_load_ushort v0, v[0:1] ; GFX7-NEXT: v_writelane_b32 v40, s16, 2 ; GFX7-NEXT: v_writelane_b32 v40, s30, 0 -; GFX7-NEXT: s_mov_b32 s17, f16_user@abs32@hi -; GFX7-NEXT: s_mov_b32 s16, f16_user@abs32@lo ; GFX7-NEXT: s_addk_i32 s32, 0x400 ; GFX7-NEXT: v_writelane_b32 v40, s31, 1 +; GFX7-NEXT: flat_load_ushort v0, v[0:1] +; GFX7-NEXT: s_mov_b32 s17, f16_user@abs32@hi +; GFX7-NEXT: s_mov_b32 s16, f16_user@abs32@lo ; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX7-NEXT: v_readlane_b32 s31, v40, 1 ; GFX7-NEXT: v_readlane_b32 s30, v40, 0 +; GFX7-NEXT: v_readlane_b32 s31, v40, 1 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: v_readlane_b32 s4, v40, 2 ; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -218,20 +218,20 @@ define void @outgoing_v2f16_arg(ptr %ptr) #0 { ; GFX7-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[18:19] -; GFX7-NEXT: flat_load_dword v1, v[0:1] ; GFX7-NEXT: v_writelane_b32 v40, s16, 2 ; GFX7-NEXT: v_writelane_b32 v40, s30, 0 -; GFX7-NEXT: s_mov_b32 s17, v2f16_user@abs32@hi -; GFX7-NEXT: s_mov_b32 s16, v2f16_user@abs32@lo ; GFX7-NEXT: s_addk_i32 s32, 0x400 ; GFX7-NEXT: v_writelane_b32 v40, s31, 1 +; GFX7-NEXT: flat_load_dword v1, v[0:1] +; GFX7-NEXT: s_mov_b32 s17, v2f16_user@abs32@hi +; GFX7-NEXT: s_mov_b32 s16, v2f16_user@abs32@lo ; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v1 ; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX7-NEXT: v_readlane_b32 s31, v40, 1 ; GFX7-NEXT: v_readlane_b32 s30, v40, 0 +; GFX7-NEXT: v_readlane_b32 s31, v40, 1 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: v_readlane_b32 s4, v40, 2 ; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -255,19 +255,19 @@ define void @outgoing_f16_return(ptr %ptr) #0 { ; GFX7-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[18:19] ; GFX7-NEXT: v_writelane_b32 v42, s16, 2 -; GFX7-NEXT: v_writelane_b32 v42, s30, 0 -; GFX7-NEXT: s_mov_b32 s17, f16_result@abs32@hi -; GFX7-NEXT: s_mov_b32 s16, f16_result@abs32@lo ; GFX7-NEXT: s_addk_i32 s32, 0x400 ; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX7-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX7-NEXT: v_writelane_b32 v42, s30, 0 ; GFX7-NEXT: v_writelane_b32 v42, s31, 1 +; GFX7-NEXT: s_mov_b32 s17, f16_result@abs32@hi +; GFX7-NEXT: s_mov_b32 s16, f16_result@abs32@lo ; GFX7-NEXT: v_mov_b32_e32 v41, v1 ; GFX7-NEXT: v_mov_b32_e32 v40, v0 ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_readlane_b32 s31, v42, 1 ; GFX7-NEXT: v_readlane_b32 s30, v42, 0 +; GFX7-NEXT: v_readlane_b32 s31, v42, 1 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 @@ -297,20 +297,20 @@ define void @outgoing_v2f16_return(ptr %ptr) #0 { ; GFX7-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[18:19] ; GFX7-NEXT: v_writelane_b32 v42, s16, 2 -; GFX7-NEXT: v_writelane_b32 v42, s30, 0 -; GFX7-NEXT: s_mov_b32 s17, v2f16_result@abs32@hi -; GFX7-NEXT: s_mov_b32 s16, v2f16_result@abs32@lo ; GFX7-NEXT: s_addk_i32 s32, 0x400 ; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX7-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX7-NEXT: v_writelane_b32 v42, s30, 0 ; GFX7-NEXT: v_writelane_b32 v42, s31, 1 +; GFX7-NEXT: s_mov_b32 s17, v2f16_result@abs32@hi +; GFX7-NEXT: s_mov_b32 s16, v2f16_result@abs32@lo ; GFX7-NEXT: v_mov_b32_e32 v41, v1 ; GFX7-NEXT: v_mov_b32_e32 v40, v0 ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_readlane_b32 s31, v42, 1 ; GFX7-NEXT: v_readlane_b32 s30, v42, 0 +; GFX7-NEXT: v_readlane_b32 s31, v42, 1 ; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 @@ -345,13 +345,13 @@ define void @outgoing_v4f16_return(ptr %ptr) #0 { ; GFX7-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[18:19] ; GFX7-NEXT: v_writelane_b32 v42, s16, 2 -; GFX7-NEXT: v_writelane_b32 v42, s30, 0 -; GFX7-NEXT: s_mov_b32 s17, v4f16_result@abs32@hi -; GFX7-NEXT: s_mov_b32 s16, v4f16_result@abs32@lo ; GFX7-NEXT: s_addk_i32 s32, 0x400 ; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX7-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX7-NEXT: v_writelane_b32 v42, s30, 0 ; GFX7-NEXT: v_writelane_b32 v42, s31, 1 +; GFX7-NEXT: s_mov_b32 s17, v4f16_result@abs32@hi +; GFX7-NEXT: s_mov_b32 s16, v4f16_result@abs32@lo ; GFX7-NEXT: v_mov_b32_e32 v41, v1 ; GFX7-NEXT: v_mov_b32_e32 v40, v0 ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] @@ -381,8 +381,8 @@ define void @outgoing_v4f16_return(ptr %ptr) #0 { ; GFX7-NEXT: flat_store_dword v[40:41], v4 ; GFX7-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX7-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GFX7-NEXT: v_readlane_b32 s31, v42, 1 ; GFX7-NEXT: v_readlane_b32 s30, v42, 0 +; GFX7-NEXT: v_readlane_b32 s31, v42, 1 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: v_readlane_b32 s4, v42, 2 ; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -406,13 +406,13 @@ define void @outgoing_v8f16_return(ptr %ptr) #0 { ; GFX7-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[18:19] ; GFX7-NEXT: v_writelane_b32 v42, s16, 2 -; GFX7-NEXT: v_writelane_b32 v42, s30, 0 -; GFX7-NEXT: s_mov_b32 s17, v8f16_result@abs32@hi -; GFX7-NEXT: s_mov_b32 s16, v8f16_result@abs32@lo ; GFX7-NEXT: s_addk_i32 s32, 0x400 ; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX7-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX7-NEXT: v_writelane_b32 v42, s30, 0 ; GFX7-NEXT: v_writelane_b32 v42, s31, 1 +; GFX7-NEXT: s_mov_b32 s17, v8f16_result@abs32@hi +; GFX7-NEXT: s_mov_b32 s16, v8f16_result@abs32@lo ; GFX7-NEXT: v_mov_b32_e32 v41, v1 ; GFX7-NEXT: v_mov_b32_e32 v40, v0 ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] @@ -468,8 +468,8 @@ define void @outgoing_v8f16_return(ptr %ptr) #0 { ; GFX7-NEXT: flat_store_dword v[40:41], v8 ; GFX7-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX7-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GFX7-NEXT: v_readlane_b32 s31, v42, 1 ; GFX7-NEXT: v_readlane_b32 s30, v42, 0 +; GFX7-NEXT: v_readlane_b32 s31, v42, 1 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: v_readlane_b32 s4, v42, 2 ; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -494,10 +494,10 @@ define half @call_split_type_used_outside_block_v8f16() #0 { ; GFX7-NEXT: s_mov_b64 exec, s[18:19] ; GFX7-NEXT: v_writelane_b32 v40, s16, 2 ; GFX7-NEXT: v_writelane_b32 v40, s30, 0 -; GFX7-NEXT: s_mov_b32 s17, v8f16_result@abs32@hi -; GFX7-NEXT: s_mov_b32 s16, v8f16_result@abs32@lo ; GFX7-NEXT: s_addk_i32 s32, 0x400 ; GFX7-NEXT: v_writelane_b32 v40, s31, 1 +; GFX7-NEXT: s_mov_b32 s17, v8f16_result@abs32@hi +; GFX7-NEXT: s_mov_b32 s16, v8f16_result@abs32@lo ; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7 @@ -518,6 +518,7 @@ define half @call_split_type_used_outside_block_v8f16() #0 { ; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX7-NEXT: v_readlane_b32 s30, v40, 0 ; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7 ; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6 ; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5 @@ -527,7 +528,6 @@ define half @call_split_type_used_outside_block_v8f16() #0 { ; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-NEXT: v_readlane_b32 s31, v40, 1 -; GFX7-NEXT: v_readlane_b32 s30, v40, 0 ; GFX7-NEXT: s_mov_b32 s32, s33 ; GFX7-NEXT: v_readlane_b32 s4, v40, 2 ; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll index c4af66e922e8d..42dc23a55a6dc 100644 --- a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll +++ b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll @@ -10,19 +10,20 @@ define void @test_load_zext() { ; CHECK-NEXT: s_or_saveexec_b64 s[2:3], -1 ; CHECK-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[2:3] -; CHECK-NEXT: s_add_i32 s32, s32, 16 ; CHECK-NEXT: v_writelane_b32 v40, s0, 2 +; CHECK-NEXT: v_writelane_b32 v40, s30, 0 +; CHECK-NEXT: s_add_i32 s32, s32, 16 +; CHECK-NEXT: s_nop 0 +; CHECK-NEXT: v_writelane_b32 v40, s31, 1 ; CHECK-NEXT: s_getpc_b64 s[0:1] ; CHECK-NEXT: s_add_u32 s0, s0, has_spgr_args@gotpcrel32@lo+4 ; CHECK-NEXT: s_addc_u32 s1, s1, has_spgr_args@gotpcrel32@hi+12 ; CHECK-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 -; CHECK-NEXT: v_writelane_b32 v40, s30, 0 ; CHECK-NEXT: s_mov_b32 s0, DescriptorBuffer@abs32@lo -; CHECK-NEXT: v_writelane_b32 v40, s31, 1 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_swappc_b64 s[30:31], s[2:3] -; CHECK-NEXT: v_readlane_b32 s31, v40, 1 ; CHECK-NEXT: v_readlane_b32 s30, v40, 0 +; CHECK-NEXT: v_readlane_b32 s31, v40, 1 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: v_readlane_b32 s0, v40, 2 ; CHECK-NEXT: s_or_saveexec_b64 s[2:3], -1 diff --git a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll index 242b5e9aeaf42..75220397013e7 100644 --- a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll +++ b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll @@ -3,6 +3,8 @@ ; RUN: FileCheck -check-prefix=ERR %s < %t.err ; FIXME: These tests cannot be tail called, and should be executed in a waterfall loop. +; XFAIL: * + declare hidden void @void_func_i32_inreg(i32 inreg) ; ERR: error: :0:0: in function tail_call_i32_inreg_divergent void (i32): illegal VGPR to SGPR copy diff --git a/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir b/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir index cc261b0da4a8f..f4dc2aeb3e848 100644 --- a/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir +++ b/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir @@ -19,8 +19,12 @@ body: | ; GCN-LABEL: name: wwm_scratch_reg_spill_reload_of_outgoing_reg ; GCN: liveins: $sgpr20, $vgpr1 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr0, 0 ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: $vgpr0 = IMPLICIT_DEF ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr0 @@ -52,9 +56,15 @@ body: | ; GCN-LABEL: name: wwm_scratch_reg_spill_reload_of_outgoing_tuple_subreg ; GCN: liveins: $sgpr20, $sgpr21, $vgpr1 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr0, 0 ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr2, 256 ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: $vgpr0 = IMPLICIT_DEF ; GCN-NEXT: $vgpr2 = IMPLICIT_DEF @@ -91,8 +101,13 @@ body: | ; GCN-LABEL: name: wwm_scratch_reg_spill_reload_different_outgoing_reg ; GCN: liveins: $sgpr20, $vgpr1 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr2, 0 ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: $vgpr2 = IMPLICIT_DEF ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr2 @@ -123,8 +138,14 @@ body: | ; GCN-LABEL: name: wwm_csr_spill_reload ; GCN: liveins: $sgpr20, $vgpr1 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr2, 0 ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: $vgpr2 = IMPLICIT_DEF ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr2 diff --git a/llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir b/llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir index 4122a530ee861..5b330e892aa34 100644 --- a/llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir +++ b/llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir @@ -18,6 +18,9 @@ body: | ; GCN-LABEL: name: vgpr_use_after_prolog_spill ; GCN: liveins: $sgpr42, $vgpr0, $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 8192, killed $vgpr0, implicit $exec ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr42, 0, $vgpr0 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0 @@ -42,6 +45,9 @@ body: | ; GCN-LABEL: name: livein_vgpr_def_after_prolog_spill ; GCN: liveins: $sgpr42, $vgpr0, $vgpr1, $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 8192, killed $vgpr1, implicit $exec ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr42, 0, $vgpr0 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0 @@ -65,6 +71,9 @@ body: | ; GCN-NEXT: successors: %bb.1(0x80000000) ; GCN-NEXT: liveins: $sgpr42, $vgpr0, $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GCN-NEXT: S_NOP 0 ; GCN-NEXT: S_BRANCH %bb.1 ; GCN-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll b/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll index 0cf26be3ac24f..42386385a8016 100644 --- a/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll +++ b/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll @@ -7,6 +7,8 @@ define amdgpu_ps float @simple_test_return_to_epilog(float %a) #0 { ; GCN: bb.0.entry: ; GCN-NEXT: liveins: $vgpr0 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GCN-NEXT: SI_RETURN_TO_EPILOG killed $vgpr0 entry: ret float %a @@ -18,6 +20,8 @@ define amdgpu_ps float @test_return_to_epilog_into_end_block(i32 inreg %a, float ; GCN-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000) ; GCN-NEXT: liveins: $sgpr2, $vgpr0 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GCN-NEXT: S_CMP_LT_I32 killed renamable $sgpr2, 1, implicit-def $scc ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; GCN-NEXT: {{ $}} @@ -51,6 +55,8 @@ define amdgpu_ps float @test_unify_return_to_epilog_into_end_block(i32 inreg %a, ; GCN-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000) ; GCN-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GCN-NEXT: S_CMP_LT_I32 killed renamable $sgpr2, 1, implicit-def $scc ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; GCN-NEXT: {{ $}} @@ -103,6 +109,8 @@ define amdgpu_ps { <4 x float> } @test_return_to_epilog_with_optimized_kill(floa ; GCN-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; GCN-NEXT: liveins: $vgpr0 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg ; GCN-NEXT: renamable $vgpr1 = nofpexcept V_RCP_F32_e32 $vgpr0, implicit $mode, implicit $exec ; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN-NEXT: nofpexcept V_CMP_NGT_F32_e32 0, killed $vgpr1, implicit-def $vcc, implicit $mode, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/true16-fold.mir b/llvm/test/CodeGen/AMDGPU/true16-fold.mir index 9484417e63c98..26e3ed6af856e 100644 --- a/llvm/test/CodeGen/AMDGPU/true16-fold.mir +++ b/llvm/test/CodeGen/AMDGPU/true16-fold.mir @@ -48,7 +48,9 @@ body: | ; CHECK-LABEL: name: sgpr_lo16 ; CHECK: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[V_ALIGNBIT_B32_t16_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_t16_e64 0, [[DEF]], 0, killed [[DEF1]], 0, 30, 0, 0, implicit $exec + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 30 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[S_MOV_B32_]] + ; CHECK-NEXT: [[V_ALIGNBIT_B32_t16_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_t16_e64 0, [[DEF]], 0, killed [[DEF1]], 0, killed [[COPY]], 0, 0, implicit $exec ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_t16_e64_]] %0:sreg_32 = IMPLICIT_DEF %1:sreg_32 = IMPLICIT_DEF @@ -66,18 +68,6 @@ registers: body: | bb.0: liveins: $vgpr0, $vgpr1, $vgpr2 - ; CHECK-LABEL: name: fold_16bit_madmix_clamp - ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[DEF]] - ; CHECK-NEXT: [[V_FMA_MIXLO_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_FMA_MIXLO_F16 8, [[COPY2]], 8, [[COPY1]], 0, [[COPY]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_16 = COPY [[V_FMA_MIXLO_F16_]] - ; CHECK-NEXT: $vgpr0 = COPY [[V_FMA_MIXLO_F16_]] - ; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr0 %0:vgpr_32 = COPY $vgpr2 %1:vgpr_32 = COPY $vgpr1 %2:vgpr_32 = COPY $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll index d80ec6bd34945..4fae53f06f4f2 100644 --- a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll +++ b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll @@ -13,14 +13,14 @@ define internal fastcc void @widget() { ; GFX90A-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX90A-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[18:19] -; GFX90A-NEXT: s_addk_i32 s32, 0x400 ; GFX90A-NEXT: v_writelane_b32 v40, s16, 2 +; GFX90A-NEXT: v_writelane_b32 v40, s30, 0 +; GFX90A-NEXT: s_addk_i32 s32, 0x400 +; GFX90A-NEXT: v_writelane_b32 v40, s31, 1 ; GFX90A-NEXT: s_getpc_b64 s[16:17] ; GFX90A-NEXT: s_add_u32 s16, s16, wobble@gotpcrel32@lo+4 ; GFX90A-NEXT: s_addc_u32 s17, s17, wobble@gotpcrel32@hi+12 ; GFX90A-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX90A-NEXT: v_writelane_b32 v40, s30, 0 -; GFX90A-NEXT: v_writelane_b32 v40, s31, 1 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_swappc_b64 s[30:31], s[16:17] bb: diff --git a/llvm/test/CodeGen/AMDGPU/umed3.ll b/llvm/test/CodeGen/AMDGPU/umed3.ll index 9d8a45ada87aa..741da2a078497 100644 --- a/llvm/test/CodeGen/AMDGPU/umed3.ll +++ b/llvm/test/CodeGen/AMDGPU/umed3.ll @@ -705,8 +705,8 @@ bb: ; SI: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; FIXME: VI not matching med3 -; VI: v_min_u16 -; VI: v_max_u16 +; VI-DAG: v_min_u16 +; VI-DAG: v_max_u16 ; VI: v_min_u16 ; VI: v_max_u16 diff --git a/llvm/test/CodeGen/AMDGPU/uncalled-local-functions.ll b/llvm/test/CodeGen/AMDGPU/uncalled-local-functions.ll new file mode 100644 index 0000000000000..6cefcedaf02f4 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/uncalled-local-functions.ll @@ -0,0 +1,89 @@ +; RUN: llc -O0 -march=amdgcn -mcpu=gfx90a < %s | FileCheck %s +; REQUIRES: asserts + +@alias = internal alias i32, i32* @aliased_internal_func +@alias_taken = internal alias i32, i32* @aliased_taken_func + +; CHECK-NOT: internal_func +define internal i32 @internal_func() { + ret i32 0 +} + +; CHECK-NOT: private_func +define private i32 @private_func() { + ret i32 0 +} + +; CHECK-NOT: aliased_internal_func +define internal i32 @aliased_internal_func() { + ret i32 0 +} + +; CHECK-LABEL: take_alias_addr +; CHECK: Function info: +; CHECK-NEXT: codeLenInByte = 60 +; CHECK-NEXT: TotalNumSgprs: 37 +; CHECK-NEXT: NumVgprs: 1 +; CHECK-NEXT: NumAgprs: 0 +; CHECK-NEXT: TotalNumVgprs: 1 +; CHECK-NEXT: ScratchSize: 16 +; CHECK-NEXT: MemoryBound: 0 +define void @take_alias_addr() { + %addr_loc = alloca ptr, addrspace(5) + store ptr @alias_taken, ptr addrspace(5) %addr_loc + ret void +} + +; CHECK: aliased_taken_func +; CHECK: Function info: +; CHECK-NEXT: codeLenInByte = 12 +; CHECK-NEXT: TotalNumSgprs: 36 +; CHECK-NEXT: NumVgprs: 1 +; CHECK-NEXT: NumAgprs: 0 +; CHECK-NEXT: TotalNumVgprs: 1 +; CHECK-NEXT: ScratchSize: 0 +; CHECK-NEXT: MemoryBound: 0 +define internal i32 @aliased_taken_func() { + ret i32 0 +} + +; CHECK-LABEL: addr_taken +; CHECK: Function info: +; CHECK-NEXT: codeLenInByte = 12 +; CHECK-NEXT: TotalNumSgprs: 36 +; CHECK-NEXT: NumVgprs: 1 +; CHECK-NEXT: NumAgprs: 0 +; CHECK-NEXT: TotalNumVgprs: 1 +; CHECK-NEXT: ScratchSize: 0 +; CHECK-NEXT: MemoryBound: 0 +define internal i32 @addr_taken() { + ret i32 0 +} + +; CHECK-LABEL: non_local +; CHECK: Function info: +; CHECK-NEXT: codeLenInByte = 12 +; CHECK-NEXT: TotalNumSgprs: 36 +; CHECK-NEXT: NumVgprs: 1 +; CHECK-NEXT: NumAgprs: 0 +; CHECK-NEXT: TotalNumVgprs: 1 +; CHECK-NEXT: ScratchSize: 0 +; CHECK-NEXT: MemoryBound: 0 +define i32 @non_local() { + ret i32 0 +} + +; CHECK-LABEL: take_addr +; CHECK: Function info: +; CHECK-NEXT: codeLenInByte = 60 +; CHECK-NEXT: TotalNumSgprs: 37 +; CHECK-NEXT: NumVgprs: 1 +; CHECK-NEXT: NumAgprs: 0 +; CHECK-NEXT: TotalNumVgprs: 1 +; CHECK-NEXT: ScratchSize: 16 +; CHECK-NEXT: MemoryBound: 0 +define void @take_addr() { + %addr_loc = alloca ptr, addrspace(5) + store ptr @addr_taken, ptr addrspace(5) %addr_loc + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll b/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll index 321b64510c35f..c871293de7436 100644 --- a/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll +++ b/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll @@ -648,27 +648,26 @@ define i32 @s_in_multiuse_A(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg ; GCN-NEXT: s_mov_b32 exec_lo, s16 ; GCN-NEXT: v_writelane_b32 v40, s2, 4 ; GCN-NEXT: s_add_i32 s32, s32, 16 +; GCN-NEXT: v_writelane_b32 v40, s34, 0 +; GCN-NEXT: v_writelane_b32 v40, s35, 1 +; GCN-NEXT: v_writelane_b32 v40, s30, 2 +; GCN-NEXT: v_writelane_b32 v40, s31, 3 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, use32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, use32@gotpcrel32@hi+12 ; GCN-NEXT: s_xor_b32 s0, s0, s1 ; GCN-NEXT: s_load_b64 s[16:17], s[16:17], 0x0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: v_writelane_b32 v40, s34, 2 -; GCN-NEXT: s_mov_b32 s34, s1 -; GCN-NEXT: v_writelane_b32 v40, s35, 3 ; GCN-NEXT: s_and_b32 s35, s0, s3 -; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: s_mov_b32 s34, s1 ; GCN-NEXT: v_mov_b32_e32 v0, s35 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GCN-NEXT: s_xor_b32 s0, s35, s34 -; GCN-NEXT: v_readlane_b32 s35, v40, 3 +; GCN-NEXT: v_readlane_b32 s30, v40, 2 ; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: v_readlane_b32 s34, v40, 2 -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 3 +; GCN-NEXT: v_readlane_b32 s35, v40, 1 +; GCN-NEXT: v_readlane_b32 s34, v40, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s0, v40, 4 ; GCN-NEXT: s_or_saveexec_b32 s1, -1 @@ -693,29 +692,28 @@ define i32 @s_in_multiuse_B(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg ; GCN-NEXT: s_or_saveexec_b32 s16, -1 ; GCN-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b32 exec_lo, s16 +; GCN-NEXT: v_writelane_b32 v40, s2, 4 ; GCN-NEXT: s_add_i32 s32, s32, 16 +; GCN-NEXT: v_writelane_b32 v40, s34, 0 +; GCN-NEXT: v_writelane_b32 v40, s35, 1 +; GCN-NEXT: v_writelane_b32 v40, s30, 2 +; GCN-NEXT: v_writelane_b32 v40, s31, 3 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, use32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, use32@gotpcrel32@hi+12 -; GCN-NEXT: v_writelane_b32 v40, s2, 4 -; GCN-NEXT: s_load_b64 s[16:17], s[16:17], 0x0 ; GCN-NEXT: s_xor_b32 s0, s0, s1 -; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: s_load_b64 s[16:17], s[16:17], 0x0 ; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: v_writelane_b32 v40, s31, 1 -; GCN-NEXT: v_writelane_b32 v40, s34, 2 ; GCN-NEXT: s_mov_b32 s34, s1 -; GCN-NEXT: v_writelane_b32 v40, s35, 3 ; GCN-NEXT: s_and_b32 s35, s0, s3 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GCN-NEXT: s_xor_b32 s0, s35, s34 -; GCN-NEXT: v_readlane_b32 s35, v40, 3 +; GCN-NEXT: v_readlane_b32 s30, v40, 2 ; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: v_readlane_b32 s34, v40, 2 -; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-NEXT: v_readlane_b32 s31, v40, 3 +; GCN-NEXT: v_readlane_b32 s35, v40, 1 +; GCN-NEXT: v_readlane_b32 s34, v40, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s0, v40, 4 ; GCN-NEXT: s_or_saveexec_b32 s1, -1 diff --git a/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll b/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll index a81d9a458e23a..a82453ee23ee9 100644 --- a/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll +++ b/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll @@ -8,10 +8,6 @@ define void @eliminate_spill_after_mfma_rewrite(i32 %x, i32 %y, <4 x i32> %arg, ; CHECK-LABEL: eliminate_spill_after_mfma_rewrite: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CHECK-NEXT: v_accvgpr_write_b32 a3, v5 -; CHECK-NEXT: v_accvgpr_write_b32 a2, v4 -; CHECK-NEXT: v_accvgpr_write_b32 a1, v3 -; CHECK-NEXT: v_accvgpr_write_b32 a0, v2 ; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill @@ -60,6 +56,11 @@ define void @eliminate_spill_after_mfma_rewrite(i32 %x, i32 %y, <4 x i32> %arg, ; CHECK-NEXT: buffer_store_dword a61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword a62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword a63, off, s[0:3], s32 ; 4-byte Folded Spill +; CHECK-NEXT: v_accvgpr_write_b32 a3, v5 +; CHECK-NEXT: v_accvgpr_write_b32 a2, v4 +; CHECK-NEXT: v_accvgpr_write_b32 a1, v3 +; CHECK-NEXT: v_accvgpr_write_b32 a0, v2 +; CHECK-NEXT: s_nop 1 ; CHECK-NEXT: v_mfma_i32_4x4x4i8 a[0:3], v0, v1, a[0:3] ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ; def v[32:63], v[0:31] @@ -212,10 +213,6 @@ define void @eliminate_spill_after_mfma_rewrite_x2(i32 %x, i32 %y, <4 x i32> %ar ; CHECK-LABEL: eliminate_spill_after_mfma_rewrite_x2: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CHECK-NEXT: v_accvgpr_write_b32 a3, v5 -; CHECK-NEXT: v_accvgpr_write_b32 a2, v4 -; CHECK-NEXT: v_accvgpr_write_b32 a1, v3 -; CHECK-NEXT: v_accvgpr_write_b32 a0, v2 ; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill @@ -264,6 +261,11 @@ define void @eliminate_spill_after_mfma_rewrite_x2(i32 %x, i32 %y, <4 x i32> %ar ; CHECK-NEXT: buffer_store_dword a61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword a62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword a63, off, s[0:3], s32 ; 4-byte Folded Spill +; CHECK-NEXT: v_accvgpr_write_b32 a3, v5 +; CHECK-NEXT: v_accvgpr_write_b32 a2, v4 +; CHECK-NEXT: v_accvgpr_write_b32 a1, v3 +; CHECK-NEXT: v_accvgpr_write_b32 a0, v2 +; CHECK-NEXT: s_nop 1 ; CHECK-NEXT: v_mfma_i32_4x4x4i8 a[0:3], v0, v1, a[0:3] ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ; def v[32:63], v[0:31] diff --git a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll index 25e8581fb6cdd..639dcdcbf1c2a 100644 --- a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll +++ b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll @@ -14,22 +14,22 @@ define hidden void @widget() { ; GCN-NEXT: v_writelane_b32 v41, s16, 16 ; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: v_writelane_b32 v41, s30, 0 -; GCN-NEXT: v_writelane_b32 v41, s31, 1 -; GCN-NEXT: v_writelane_b32 v41, s34, 2 -; GCN-NEXT: v_writelane_b32 v41, s35, 3 -; GCN-NEXT: v_writelane_b32 v41, s36, 4 -; GCN-NEXT: v_writelane_b32 v41, s37, 5 -; GCN-NEXT: v_writelane_b32 v41, s38, 6 -; GCN-NEXT: v_writelane_b32 v41, s39, 7 -; GCN-NEXT: v_writelane_b32 v41, s48, 8 -; GCN-NEXT: v_writelane_b32 v41, s49, 9 -; GCN-NEXT: v_writelane_b32 v41, s50, 10 -; GCN-NEXT: v_writelane_b32 v41, s51, 11 -; GCN-NEXT: v_writelane_b32 v41, s52, 12 -; GCN-NEXT: v_writelane_b32 v41, s53, 13 -; GCN-NEXT: v_writelane_b32 v41, s54, 14 -; GCN-NEXT: v_writelane_b32 v41, s55, 15 +; GCN-NEXT: v_writelane_b32 v41, s34, 0 +; GCN-NEXT: v_writelane_b32 v41, s35, 1 +; GCN-NEXT: v_writelane_b32 v41, s36, 2 +; GCN-NEXT: v_writelane_b32 v41, s37, 3 +; GCN-NEXT: v_writelane_b32 v41, s38, 4 +; GCN-NEXT: v_writelane_b32 v41, s39, 5 +; GCN-NEXT: v_writelane_b32 v41, s48, 6 +; GCN-NEXT: v_writelane_b32 v41, s49, 7 +; GCN-NEXT: v_writelane_b32 v41, s50, 8 +; GCN-NEXT: v_writelane_b32 v41, s51, 9 +; GCN-NEXT: v_writelane_b32 v41, s52, 10 +; GCN-NEXT: v_writelane_b32 v41, s53, 11 +; GCN-NEXT: v_writelane_b32 v41, s54, 12 +; GCN-NEXT: v_writelane_b32 v41, s55, 13 +; GCN-NEXT: v_writelane_b32 v41, s30, 14 +; GCN-NEXT: v_writelane_b32 v41, s31, 15 ; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: flat_load_dword v0, v[0:1] @@ -93,22 +93,22 @@ define hidden void @widget() { ; GCN-NEXT: s_addc_u32 s17, s17, wibble@rel32@hi+12 ; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GCN-NEXT: .LBB0_8: ; %UnifiedReturnBlock -; GCN-NEXT: v_readlane_b32 s55, v41, 15 -; GCN-NEXT: v_readlane_b32 s54, v41, 14 -; GCN-NEXT: v_readlane_b32 s53, v41, 13 -; GCN-NEXT: v_readlane_b32 s52, v41, 12 -; GCN-NEXT: v_readlane_b32 s51, v41, 11 -; GCN-NEXT: v_readlane_b32 s50, v41, 10 -; GCN-NEXT: v_readlane_b32 s49, v41, 9 -; GCN-NEXT: v_readlane_b32 s48, v41, 8 -; GCN-NEXT: v_readlane_b32 s39, v41, 7 -; GCN-NEXT: v_readlane_b32 s38, v41, 6 -; GCN-NEXT: v_readlane_b32 s37, v41, 5 -; GCN-NEXT: v_readlane_b32 s36, v41, 4 -; GCN-NEXT: v_readlane_b32 s35, v41, 3 -; GCN-NEXT: v_readlane_b32 s34, v41, 2 -; GCN-NEXT: v_readlane_b32 s31, v41, 1 -; GCN-NEXT: v_readlane_b32 s30, v41, 0 +; GCN-NEXT: v_readlane_b32 s30, v41, 14 +; GCN-NEXT: v_readlane_b32 s31, v41, 15 +; GCN-NEXT: v_readlane_b32 s55, v41, 13 +; GCN-NEXT: v_readlane_b32 s54, v41, 12 +; GCN-NEXT: v_readlane_b32 s53, v41, 11 +; GCN-NEXT: v_readlane_b32 s52, v41, 10 +; GCN-NEXT: v_readlane_b32 s51, v41, 9 +; GCN-NEXT: v_readlane_b32 s50, v41, 8 +; GCN-NEXT: v_readlane_b32 s49, v41, 7 +; GCN-NEXT: v_readlane_b32 s48, v41, 6 +; GCN-NEXT: v_readlane_b32 s39, v41, 5 +; GCN-NEXT: v_readlane_b32 s38, v41, 4 +; GCN-NEXT: v_readlane_b32 s37, v41, 3 +; GCN-NEXT: v_readlane_b32 s36, v41, 2 +; GCN-NEXT: v_readlane_b32 s35, v41, 1 +; GCN-NEXT: v_readlane_b32 s34, v41, 0 ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v41, 16 @@ -266,32 +266,32 @@ define hidden void @blam() { ; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: v_writelane_b32 v45, s30, 0 -; GCN-NEXT: v_writelane_b32 v45, s31, 1 -; GCN-NEXT: v_writelane_b32 v45, s34, 2 -; GCN-NEXT: v_writelane_b32 v45, s35, 3 -; GCN-NEXT: v_writelane_b32 v45, s36, 4 -; GCN-NEXT: v_writelane_b32 v45, s37, 5 -; GCN-NEXT: v_writelane_b32 v45, s38, 6 -; GCN-NEXT: v_writelane_b32 v45, s39, 7 -; GCN-NEXT: v_writelane_b32 v45, s48, 8 -; GCN-NEXT: v_writelane_b32 v45, s49, 9 -; GCN-NEXT: v_writelane_b32 v45, s50, 10 -; GCN-NEXT: v_writelane_b32 v45, s51, 11 -; GCN-NEXT: v_writelane_b32 v45, s52, 12 -; GCN-NEXT: v_writelane_b32 v45, s53, 13 -; GCN-NEXT: v_writelane_b32 v45, s54, 14 -; GCN-NEXT: v_writelane_b32 v45, s55, 15 -; GCN-NEXT: v_writelane_b32 v45, s64, 16 -; GCN-NEXT: v_writelane_b32 v45, s65, 17 -; GCN-NEXT: v_writelane_b32 v45, s66, 18 -; GCN-NEXT: v_writelane_b32 v45, s67, 19 -; GCN-NEXT: v_writelane_b32 v45, s68, 20 -; GCN-NEXT: v_writelane_b32 v45, s69, 21 -; GCN-NEXT: v_writelane_b32 v45, s70, 22 -; GCN-NEXT: v_writelane_b32 v45, s71, 23 -; GCN-NEXT: v_writelane_b32 v45, s80, 24 -; GCN-NEXT: v_writelane_b32 v45, s81, 25 +; GCN-NEXT: v_writelane_b32 v45, s34, 0 +; GCN-NEXT: v_writelane_b32 v45, s35, 1 +; GCN-NEXT: v_writelane_b32 v45, s36, 2 +; GCN-NEXT: v_writelane_b32 v45, s37, 3 +; GCN-NEXT: v_writelane_b32 v45, s38, 4 +; GCN-NEXT: v_writelane_b32 v45, s39, 5 +; GCN-NEXT: v_writelane_b32 v45, s48, 6 +; GCN-NEXT: v_writelane_b32 v45, s49, 7 +; GCN-NEXT: v_writelane_b32 v45, s50, 8 +; GCN-NEXT: v_writelane_b32 v45, s51, 9 +; GCN-NEXT: v_writelane_b32 v45, s52, 10 +; GCN-NEXT: v_writelane_b32 v45, s53, 11 +; GCN-NEXT: v_writelane_b32 v45, s54, 12 +; GCN-NEXT: v_writelane_b32 v45, s55, 13 +; GCN-NEXT: v_writelane_b32 v45, s64, 14 +; GCN-NEXT: v_writelane_b32 v45, s65, 15 +; GCN-NEXT: v_writelane_b32 v45, s66, 16 +; GCN-NEXT: v_writelane_b32 v45, s67, 17 +; GCN-NEXT: v_writelane_b32 v45, s68, 18 +; GCN-NEXT: v_writelane_b32 v45, s69, 19 +; GCN-NEXT: v_writelane_b32 v45, s70, 20 +; GCN-NEXT: v_writelane_b32 v45, s71, 21 +; GCN-NEXT: v_writelane_b32 v45, s80, 22 +; GCN-NEXT: v_writelane_b32 v45, s81, 23 +; GCN-NEXT: v_writelane_b32 v45, s30, 24 +; GCN-NEXT: v_writelane_b32 v45, s31, 25 ; GCN-NEXT: v_mov_b32_e32 v40, v31 ; GCN-NEXT: s_mov_b32 s54, s15 ; GCN-NEXT: s_mov_b32 s55, s14 @@ -427,32 +427,32 @@ define hidden void @blam() { ; GCN-NEXT: s_branch .LBB1_1 ; GCN-NEXT: .LBB1_18: ; %DummyReturnBlock ; GCN-NEXT: s_or_b64 exec, exec, s[66:67] -; GCN-NEXT: v_readlane_b32 s81, v45, 25 -; GCN-NEXT: v_readlane_b32 s80, v45, 24 -; GCN-NEXT: v_readlane_b32 s71, v45, 23 -; GCN-NEXT: v_readlane_b32 s70, v45, 22 -; GCN-NEXT: v_readlane_b32 s69, v45, 21 -; GCN-NEXT: v_readlane_b32 s68, v45, 20 -; GCN-NEXT: v_readlane_b32 s67, v45, 19 -; GCN-NEXT: v_readlane_b32 s66, v45, 18 -; GCN-NEXT: v_readlane_b32 s65, v45, 17 -; GCN-NEXT: v_readlane_b32 s64, v45, 16 -; GCN-NEXT: v_readlane_b32 s55, v45, 15 -; GCN-NEXT: v_readlane_b32 s54, v45, 14 -; GCN-NEXT: v_readlane_b32 s53, v45, 13 -; GCN-NEXT: v_readlane_b32 s52, v45, 12 -; GCN-NEXT: v_readlane_b32 s51, v45, 11 -; GCN-NEXT: v_readlane_b32 s50, v45, 10 -; GCN-NEXT: v_readlane_b32 s49, v45, 9 -; GCN-NEXT: v_readlane_b32 s48, v45, 8 -; GCN-NEXT: v_readlane_b32 s39, v45, 7 -; GCN-NEXT: v_readlane_b32 s38, v45, 6 -; GCN-NEXT: v_readlane_b32 s37, v45, 5 -; GCN-NEXT: v_readlane_b32 s36, v45, 4 -; GCN-NEXT: v_readlane_b32 s35, v45, 3 -; GCN-NEXT: v_readlane_b32 s34, v45, 2 -; GCN-NEXT: v_readlane_b32 s31, v45, 1 -; GCN-NEXT: v_readlane_b32 s30, v45, 0 +; GCN-NEXT: v_readlane_b32 s30, v45, 24 +; GCN-NEXT: v_readlane_b32 s31, v45, 25 +; GCN-NEXT: v_readlane_b32 s81, v45, 23 +; GCN-NEXT: v_readlane_b32 s80, v45, 22 +; GCN-NEXT: v_readlane_b32 s71, v45, 21 +; GCN-NEXT: v_readlane_b32 s70, v45, 20 +; GCN-NEXT: v_readlane_b32 s69, v45, 19 +; GCN-NEXT: v_readlane_b32 s68, v45, 18 +; GCN-NEXT: v_readlane_b32 s67, v45, 17 +; GCN-NEXT: v_readlane_b32 s66, v45, 16 +; GCN-NEXT: v_readlane_b32 s65, v45, 15 +; GCN-NEXT: v_readlane_b32 s64, v45, 14 +; GCN-NEXT: v_readlane_b32 s55, v45, 13 +; GCN-NEXT: v_readlane_b32 s54, v45, 12 +; GCN-NEXT: v_readlane_b32 s53, v45, 11 +; GCN-NEXT: v_readlane_b32 s52, v45, 10 +; GCN-NEXT: v_readlane_b32 s51, v45, 9 +; GCN-NEXT: v_readlane_b32 s50, v45, 8 +; GCN-NEXT: v_readlane_b32 s49, v45, 7 +; GCN-NEXT: v_readlane_b32 s48, v45, 6 +; GCN-NEXT: v_readlane_b32 s39, v45, 5 +; GCN-NEXT: v_readlane_b32 s38, v45, 4 +; GCN-NEXT: v_readlane_b32 s37, v45, 3 +; GCN-NEXT: v_readlane_b32 s36, v45, 2 +; GCN-NEXT: v_readlane_b32 s35, v45, 1 +; GCN-NEXT: v_readlane_b32 s34, v45, 0 ; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/unsupported-global-load.ll b/llvm/test/CodeGen/AMDGPU/unsupported-global-load.ll new file mode 100644 index 0000000000000..c04f33056b207 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/unsupported-global-load.ll @@ -0,0 +1,32 @@ +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx9-generic < %s 2>&1 | FileCheck -check-prefixes=GFX9-GENERIC %s +; xxx: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx9-4-generic < %s 2>&1 | FileCheck -check-prefixes=GFX9-4-GENERIC %s +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx10-1-generic < %s 2>&1 | FileCheck -check-prefixes=GFX10-1-GENERIC %s +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx10-3-generic < %s 2>&1 | FileCheck -check-prefixes=GFX10-3-GENERIC %s +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx11-generic < %s 2>&1 | FileCheck -check-prefixes=GFX11-GENERIC %s +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx12-generic < %s 2>&1 | FileCheck -check-prefixes=GFX12-GENERIC %s + +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx9-generic < %s 2>&1 | FileCheck -check-prefixes=GFX9-GENERIC-GBL-ISEL %s +; xxx: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx9-4-generic < %s 2>&1 | FileCheck -check-prefixes=GFX9-4-GENERIC-GBL-ISEL %s +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx10-1-generic < %s 2>&1 | FileCheck -check-prefixes=GFX10-1-GENERIC-GBL-ISEL %s +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx10-3-generic < %s 2>&1 | FileCheck -check-prefixes=GFX10-3-GENERIC-GBL-ISEL %s +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx11-generic < %s 2>&1 | FileCheck -check-prefixes=GFX11-GENERIC-GBL-ISEL %s +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx12-generic < %s 2>&1 | FileCheck -check-prefixes=GFX12-GENERIC-GBL-ISEL %s + +define <4 x i32> @global_load_b128(ptr addrspace(1) %addr) { +; GFX9-GENERIC: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.load.b128 +; GFX10-1-GENERIC: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.load.b128 +; GFX10-3-GENERIC: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.load.b128 +; GFX11-GENERIC: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.load.b128 +; GFX12-GENERIC: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.load.b128 + +; GFX9-GENERIC-GBL-ISEL: LLVM ERROR: cannot select: {{.*}} intrinsic(@llvm.amdgcn.global.load.b128) +; GFX10-1-GENERIC-GBL-ISEL: LLVM ERROR: cannot select: {{.*}} intrinsic(@llvm.amdgcn.global.load.b128) +; GFX10-3-GENERIC-GBL-ISEL: LLVM ERROR: cannot select: {{.*}} intrinsic(@llvm.amdgcn.global.load.b128) +; GFX11-GENERIC-GBL-ISEL: LLVM ERROR: cannot select: {{.*}} intrinsic(@llvm.amdgcn.global.load.b128) +; GFX12-GENERIC-GBL-ISEL: LLVM ERROR: cannot select: {{.*}} intrinsic(@llvm.amdgcn.global.load.b128) +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !0) + ret <4 x i32> %data +} + +!0 = !{!""} diff --git a/llvm/test/CodeGen/AMDGPU/unsupported-global-store.ll b/llvm/test/CodeGen/AMDGPU/unsupported-global-store.ll new file mode 100644 index 0000000000000..8b4dde936f5fc --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/unsupported-global-store.ll @@ -0,0 +1,32 @@ +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx9-generic < %s 2>&1 | FileCheck -check-prefixes=GFX9-GENERIC %s +; xxx: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx9-4-generic < %s 2>&1 | FileCheck -check-prefixes=GFX9-4-GENERIC %s +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx10-1-generic < %s 2>&1 | FileCheck -check-prefixes=GFX10-1-GENERIC %s +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx10-3-generic < %s 2>&1 | FileCheck -check-prefixes=GFX10-3-GENERIC %s +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx11-generic < %s 2>&1 | FileCheck -check-prefixes=GFX11-GENERIC %s +; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx12-generic < %s 2>&1 | FileCheck -check-prefixes=GFX12-GENERIC %s + +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx9-generic < %s 2>&1 | FileCheck -check-prefixes=GFX9-GENERIC-GBL-ISEL %s +; xxx: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx9-4-generic < %s 2>&1 | FileCheck -check-prefixes=GFX9-4-GENERIC-GBL-ISEL %s +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx10-1-generic < %s 2>&1 | FileCheck -check-prefixes=GFX10-1-GENERIC-GBL-ISEL %s +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx10-3-generic < %s 2>&1 | FileCheck -check-prefixes=GFX10-3-GENERIC-GBL-ISEL %s +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx11-generic < %s 2>&1 | FileCheck -check-prefixes=GFX11-GENERIC-GBL-ISEL %s +; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx12-generic < %s 2>&1 | FileCheck -check-prefixes=GFX12-GENERIC-GBL-ISEL %s + +define void @global_store_b128(ptr addrspace(1) %addr, <4 x i32> %data) { +; GFX9-GENERIC: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.store.b128 +; GFX10-1-GENERIC: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.store.b128 +; GFX10-3-GENERIC: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.store.b128 +; GFX11-GENERIC: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.store.b128 +; GFX12-GENERIC: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.global.store.b128 + +; GFX9-GENERIC-GBL-ISEL: LLVM ERROR: cannot select: {{.*}} intrinsic(@llvm.amdgcn.global.store.b128) +; GFX10-1-GENERIC-GBL-ISEL: LLVM ERROR: cannot select: {{.*}} intrinsic(@llvm.amdgcn.global.store.b128) +; GFX10-3-GENERIC-GBL-ISEL: LLVM ERROR: cannot select: {{.*}} intrinsic(@llvm.amdgcn.global.store.b128) +; GFX11-GENERIC-GBL-ISEL: LLVM ERROR: cannot select: {{.*}} intrinsic(@llvm.amdgcn.global.store.b128) +; GFX12-GENERIC-GBL-ISEL: LLVM ERROR: cannot select: {{.*}} intrinsic(@llvm.amdgcn.global.store.b128) +entry: + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %addr, <4 x i32> %data, metadata !0) + ret void +} + +!0 = !{!""} diff --git a/llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir b/llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir index 1e815f76ee149..dd7d96f9d6e3c 100644 --- a/llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir +++ b/llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir @@ -39,11 +39,43 @@ body: | ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: liveins: $sgpr40, $sgpr41, $vgpr1 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 ; MUBUF-NEXT: $sgpr40 = frame-setup COPY $sgpr33 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr40 ; MUBUF-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; MUBUF-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; MUBUF-NEXT: $sgpr41 = frame-setup COPY $sgpr34 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr41 ; MUBUF-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; MUBUF-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 11010048, implicit-def dead $scc ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc @@ -66,6 +98,7 @@ body: | ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; MUBUF-NEXT: $sgpr34 = frame-destroy COPY $sgpr41 + ; MUBUF-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; MUBUF-NEXT: $sgpr33 = frame-destroy COPY $sgpr40 ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -74,11 +107,43 @@ body: | ; FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; FLATSCR-NEXT: liveins: $sgpr40, $sgpr41, $vgpr1 ; FLATSCR-NEXT: {{ $}} + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 ; FLATSCR-NEXT: $sgpr40 = frame-setup COPY $sgpr33 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, $sgpr40 ; FLATSCR-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; FLATSCR-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; FLATSCR-NEXT: $sgpr41 = frame-setup COPY $sgpr34 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION register $sgpr34, $sgpr41 ; FLATSCR-NEXT: $sgpr34 = frame-setup COPY $sgpr32 + ; FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; FLATSCR-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 172032, implicit-def dead $scc ; FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; FLATSCR-NEXT: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc @@ -104,6 +169,7 @@ body: | ; FLATSCR-NEXT: {{ $}} ; FLATSCR-NEXT: $sgpr32 = frame-destroy COPY $sgpr34 ; FLATSCR-NEXT: $sgpr34 = frame-destroy COPY $sgpr41 + ; FLATSCR-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 ; FLATSCR-NEXT: $sgpr33 = frame-destroy COPY $sgpr40 ; FLATSCR-NEXT: S_ENDPGM 0 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir b/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir index 69cf924548ed8..0316c35128087 100644 --- a/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir +++ b/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir @@ -19,6 +19,12 @@ body: | ; GCN-LABEL: name: partial_spill_a128_restore_to_v128_1_of_4 ; GCN: liveins: $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s96) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $vgpr51 = COPY $vgpr55, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51 @@ -44,6 +50,12 @@ body: | ; GCN-LABEL: name: partial_spill_a128_restore_to_v128_2_of_4 ; GCN: liveins: $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 ; GCN-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s64) into %stack.0, align 4, addrspace 5) @@ -71,6 +83,12 @@ body: | ; GCN-LABEL: name: partial_spill_a128_restore_to_v128_3_of_4 ; GCN: liveins: $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 ; GCN-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 @@ -100,6 +118,20 @@ body: | ; GCN-LABEL: name: full_spill_a128_restore_to_v128 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 ; GCN-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 @@ -129,6 +161,12 @@ body: | ; GCN-LABEL: name: partial_spill_v128_restore_to_a128_1_of_4 ; GCN: liveins: $agpr30, $agpr31, $agpr24_agpr25, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s96) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $agpr29 = COPY $agpr30, implicit-def $agpr26_agpr27_agpr28_agpr29 @@ -154,6 +192,12 @@ body: | ; GCN-LABEL: name: partial_spill_v128_restore_to_a128_2_of_4 ; GCN: liveins: $agpr30, $agpr31, $agpr24_agpr25, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s64) into %stack.0, align 4, addrspace 5) @@ -181,6 +225,12 @@ body: | ; GCN-LABEL: name: partial_spill_v128_restore_to_a128_3_of_4 ; GCN: liveins: $agpr24, $agpr25, $agpr30, $agpr31, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 ; GCN-NEXT: $agpr25 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 @@ -210,6 +260,20 @@ body: | ; GCN-LABEL: name: full_spill_v128_restore_to_a128 ; GCN: liveins: $agpr4, $agpr5, $agpr6, $agpr7, $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: {{ $}} + ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 ; GCN-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir index 572a875941b22..23d23d4196f74 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir +++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir @@ -26,6 +26,8 @@ body: | ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: liveins: $vgpr0 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) @@ -44,6 +46,8 @@ body: | ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: liveins: $vgpr0 ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec @@ -63,6 +67,8 @@ body: | ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: liveins: $vgpr0 ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) @@ -81,6 +87,8 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) @@ -125,6 +133,8 @@ body: | ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: liveins: $vgpr0_vgpr1 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.1, addrspace 5) @@ -144,6 +154,8 @@ body: | ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1 ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e32 8200, $vgpr2, implicit $exec @@ -163,6 +175,8 @@ body: | ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1 ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $vgpr0_vgpr1, killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.1, align 4, addrspace 5) @@ -181,6 +195,8 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.1, addrspace 5) @@ -224,6 +240,9 @@ body: | ; MUBUF: bb.0: ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) @@ -241,6 +260,9 @@ body: | ; GFX9-FLATSCR: bb.0: ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec @@ -259,6 +281,9 @@ body: | ; GFX10-FLATSCR: bb.0: ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec ; GFX10-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) @@ -276,6 +301,9 @@ body: | ; VMEM-GFX8: bb.0: ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) @@ -318,6 +346,10 @@ body: | ; MUBUF: bb.0: ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.1, addrspace 5) @@ -336,6 +368,10 @@ body: | ; GFX9-FLATSCR: bb.0: ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e32 8200, $vgpr2, implicit $exec @@ -354,6 +390,10 @@ body: | ; GFX10-FLATSCR: bb.0: ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec ; GFX10-FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.1, align 4, addrspace 5) @@ -371,6 +411,10 @@ body: | ; VMEM-GFX8: bb.0: ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.1, addrspace 5) @@ -415,6 +459,839 @@ body: | ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -436,6 +1313,839 @@ body: | ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -458,6 +2168,839 @@ body: | ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec @@ -479,6 +3022,839 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -527,6 +3903,840 @@ body: | ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec @@ -549,6 +4759,840 @@ body: | ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -571,6 +5615,840 @@ body: | ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec @@ -592,6 +6470,840 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec @@ -641,6 +7353,841 @@ body: | ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr3 = V_MOV_B32_e32 8200, implicit $exec @@ -664,6 +8211,841 @@ body: | ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -686,6 +9068,841 @@ body: | ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr3 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec @@ -707,6 +9924,841 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr3 = V_MOV_B32_e32 8200, implicit $exec @@ -757,6 +10809,838 @@ body: | ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -778,6 +11662,838 @@ body: | ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -800,6 +12516,838 @@ body: | ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec @@ -821,6 +13369,838 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -869,6 +14249,838 @@ body: | ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec @@ -891,6 +15103,838 @@ body: | ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -913,6 +15957,838 @@ body: | ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec @@ -934,6 +16810,838 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec @@ -983,6 +17691,838 @@ body: | ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr3 = V_MOV_B32_e32 8200, implicit $exec @@ -1006,6 +18546,838 @@ body: | ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr32, implicit $exec @@ -1028,6 +19400,838 @@ body: | ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr3 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec @@ -1049,6 +20253,838 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr3 = V_MOV_B32_e32 8200, implicit $exec @@ -1098,6 +21134,839 @@ body: | ; MUBUF: bb.0: ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) @@ -1115,6 +21984,839 @@ body: | ; GFX9-FLATSCR: bb.0: ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $sgpr4 = S_ADDC_U32 $sgpr32, 8200, implicit-def $scc, implicit $scc ; GFX9-FLATSCR-NEXT: S_BITCMP1_B32 $sgpr4, 0, implicit-def $scc @@ -1135,6 +22837,839 @@ body: | ; GFX10-FLATSCR: bb.0: ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $sgpr4 = S_ADDC_U32 $sgpr32, 8200, implicit-def $scc, implicit $scc ; GFX10-FLATSCR-NEXT: S_BITCMP1_B32 $sgpr4, 0, implicit-def $scc @@ -1155,6 +23690,839 @@ body: | ; VMEM-GFX8: bb.0: ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) @@ -1202,6 +24570,839 @@ body: | ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -1223,6 +25424,839 @@ body: | ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $sgpr4 = S_ADDC_U32 $sgpr32, 8200, implicit-def $scc, implicit $scc @@ -1247,6 +26281,839 @@ body: | ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr512 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr513 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr514 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr515 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr516 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr517 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr518 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr519 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr520 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr521 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr522 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr523 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr524 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr525 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr526 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr527 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr528 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr529 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr530 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr531 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr532 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr533 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr534 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr535 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr536 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr537 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr538 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr539 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr540 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr541 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr542 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr543 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr544 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr545 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr546 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr547 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr548 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr549 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr550 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr551 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr552 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr553 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr554 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr555 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr556 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr557 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr558 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr559 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr560 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr561 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr562 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr563 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr564 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr565 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr566 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr567 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr568 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr569 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr570 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr571 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr572 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr573 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr574 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr575 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr576 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr577 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr578 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr579 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr580 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr581 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr582 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr583 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr584 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr585 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr586 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr587 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr588 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr589 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr590 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr591 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr592 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr593 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr594 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr595 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr596 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr597 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr598 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr599 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr600 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr601 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr602 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr603 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr604 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr605 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr606 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr607 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr608 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr609 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr610 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr611 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr612 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr613 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr614 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr615 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr616 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr617 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr618 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr619 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr620 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr621 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr622 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr623 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr624 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr625 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr626 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr627 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr628 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr629 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr630 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr631 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr632 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr633 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr634 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr635 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr636 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr637 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr638 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr639 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr640 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr641 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr642 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr643 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr644 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr645 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr646 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr647 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr648 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr649 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr650 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr651 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr652 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr653 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr654 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr655 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr656 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr657 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr658 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr659 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr660 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr661 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr662 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr663 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr664 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr665 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr666 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr667 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr668 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr669 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr670 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr671 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr672 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr673 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr674 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr675 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr676 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr677 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr678 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr679 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr680 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr681 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr682 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr683 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr684 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr685 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr686 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr687 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr688 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr689 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr690 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr691 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr692 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr693 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr694 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr695 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr696 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr697 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr698 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr699 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr700 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr701 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr702 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr703 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr704 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr705 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr706 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr707 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr708 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr709 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr710 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr711 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr712 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr713 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr714 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr715 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr716 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr717 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr718 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr719 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr720 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr721 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr722 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr723 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr724 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr725 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr726 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr727 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr728 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr729 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr730 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr731 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr732 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr733 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr734 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr735 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr736 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr737 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr738 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr739 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr740 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr741 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr742 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr743 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr744 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr745 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr746 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr747 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr748 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr749 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr750 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr751 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr752 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr753 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr754 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr755 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr756 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr757 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr758 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr759 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr760 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr761 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr762 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr763 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr764 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr765 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr766 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr767 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr768 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr769 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr770 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr771 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr772 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr773 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr774 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr775 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr776 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr777 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr778 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr779 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr780 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr781 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr782 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr783 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr784 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr785 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr786 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr787 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr788 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr789 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr790 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr791 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr792 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr793 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr794 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr795 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr796 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr797 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr798 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr799 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr800 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr801 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr802 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr803 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr804 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr805 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr806 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr807 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr808 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr809 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr810 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr811 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr812 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr813 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr814 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr815 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr816 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr817 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr818 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr819 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr820 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr821 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr822 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr823 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr824 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr825 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr826 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr827 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr828 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr829 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr830 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr831 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr832 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr833 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr834 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr835 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr836 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr837 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr838 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr839 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr840 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr841 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr842 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr843 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr844 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr845 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr846 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr847 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr848 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr849 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr850 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr851 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr852 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr853 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr854 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr855 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr856 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr857 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr858 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr859 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr860 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr861 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr862 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr863 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr864 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr865 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr866 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr867 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr868 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr869 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr870 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr871 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr872 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr873 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr874 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr875 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr876 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr877 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr878 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr879 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr880 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr881 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr882 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr883 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr884 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr885 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr886 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr887 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr888 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr889 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr890 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr891 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr892 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr893 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr894 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr895 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr896 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr897 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr898 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr899 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr900 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr901 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr902 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr903 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr904 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr905 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr906 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr907 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr908 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr909 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr910 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr911 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr912 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr913 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr914 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr915 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr916 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr917 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr918 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr919 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr920 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr921 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr922 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr923 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr924 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr925 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr926 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr927 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr928 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr929 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr930 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr931 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr932 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr933 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr934 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr935 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr936 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr937 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr938 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr939 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr940 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr941 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr942 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr943 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr944 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr945 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr946 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr947 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr948 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr949 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr950 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr951 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr952 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr953 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr954 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr955 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr956 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr957 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr958 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr959 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr960 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr961 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr962 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr963 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr964 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr965 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr966 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr967 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr968 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr969 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr970 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr971 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr972 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr973 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr974 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr975 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr976 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr977 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr978 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr979 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr980 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr981 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr982 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr983 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr984 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr985 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr986 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr987 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr988 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr989 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr990 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr991 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr992 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr993 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr994 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr995 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr996 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr997 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr998 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr999 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1000 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1001 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1002 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1003 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1004 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1005 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1006 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1007 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1008 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1009 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1010 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1011 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1012 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1013 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1014 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1015 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1016 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1017 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1018 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1019 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1020 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1021 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1022 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1023 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $sgpr4 = S_ADDC_U32 $sgpr32, 8200, implicit-def $scc, implicit $scc @@ -1271,6 +27138,839 @@ body: | ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr256 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr257 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr258 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr259 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr260 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr261 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr262 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr263 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr264 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr265 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr266 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr267 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr268 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr269 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr270 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr271 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr272 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr273 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr274 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr275 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr276 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr277 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr278 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr279 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr280 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr281 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr282 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr283 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr284 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr285 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr286 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr287 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr288 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr289 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr290 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr291 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr292 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr293 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr294 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr295 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr296 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr297 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr298 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr299 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr300 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr301 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr302 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr303 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr304 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr305 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr306 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr307 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr308 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr309 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr310 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr311 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr312 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr313 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr314 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr315 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr316 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr317 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr318 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr319 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr320 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr321 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr322 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr323 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr324 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr325 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr326 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr327 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr328 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr329 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr330 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr331 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr332 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr333 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr334 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr335 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr336 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr337 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr338 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr339 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr340 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr341 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr342 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr343 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr344 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr345 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr346 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr347 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr348 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr349 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr350 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr351 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr352 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr353 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr354 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr355 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr356 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr357 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr358 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr359 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr360 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr361 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr362 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr363 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr364 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr365 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr366 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr367 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr368 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr369 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr370 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr371 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr372 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr373 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr374 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr375 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr376 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr377 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr378 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr379 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr380 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr381 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr382 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr383 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr384 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr385 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr386 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr387 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr388 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr389 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr390 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr391 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr392 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr393 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr394 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr395 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr396 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr397 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr398 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr399 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr400 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr401 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr402 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr403 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr404 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr405 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr406 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr407 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr408 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr409 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr410 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr411 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr412 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr413 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr414 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr415 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr416 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr417 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr418 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr419 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr420 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr421 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr422 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr423 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr424 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr425 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr426 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr427 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr428 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr429 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr430 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr431 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr432 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr433 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr434 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr435 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr436 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr437 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr438 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr439 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr440 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr441 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr442 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr443 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr444 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr445 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr446 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr447 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr448 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr449 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr450 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr451 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr452 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr453 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr454 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr455 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr456 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr457 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr458 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr459 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr460 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr461 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr462 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr463 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr464 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr465 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr466 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr467 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr468 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr469 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr470 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr471 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr472 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr473 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr474 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr475 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr476 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr477 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr478 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr479 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr480 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr481 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr482 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr483 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr484 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr485 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr486 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr487 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr488 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr489 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr490 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr491 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr492 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr493 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr494 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr495 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr496 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr497 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr498 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr499 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr500 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr501 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr502 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr503 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr504 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr505 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr506 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr507 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr508 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr509 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr510 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr511 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec @@ -1319,6 +28019,9 @@ body: | ; MUBUF: bb.0: ; MUBUF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; MUBUF-NEXT: {{ $}} + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUF-NEXT: $vcc_lo = S_MOV_B32 8200 @@ -1339,6 +28042,9 @@ body: | ; GFX9-FLATSCR: bb.0: ; GFX9-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX9-FLATSCR-NEXT: {{ $}} + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX9-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $sgpr4 = S_ADDC_U32 $sgpr32, 8200, implicit-def $scc, implicit $scc ; GFX9-FLATSCR-NEXT: S_BITCMP1_B32 $sgpr4, 0, implicit-def $scc @@ -1360,6 +28066,9 @@ body: | ; GFX10-FLATSCR: bb.0: ; GFX10-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; GFX10-FLATSCR-NEXT: {{ $}} + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX10-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $sgpr4 = S_ADDC_U32 $sgpr32, 8200, implicit-def $scc, implicit $scc ; GFX10-FLATSCR-NEXT: S_BITCMP1_B32 $sgpr4, 0, implicit-def $scc @@ -1381,6 +28090,9 @@ body: | ; VMEM-GFX8: bb.0: ; VMEM-GFX8-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; VMEM-GFX8-NEXT: {{ $}} + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; VMEM-GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; VMEM-GFX8-NEXT: $vcc_lo = S_MOV_B32 8200 diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir index edea344a66a3c..8f55957b8f415 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir @@ -17,6 +17,8 @@ body: | ; CHECK-LABEL: name: spill_v32 ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit $vgpr0 SI_SPILL_V32_SAVE $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) @@ -39,6 +41,8 @@ body: | ; CHECK-LABEL: name: spill_v32_kill ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ... @@ -59,6 +63,8 @@ body: | ; CHECK-LABEL: name: spill_v64 ; CHECK: liveins: $vgpr0_vgpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit $vgpr0_vgpr1 @@ -82,6 +88,8 @@ body: | ; CHECK-LABEL: name: spill_v64_kill ; CHECK: liveins: $vgpr0_vgpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) @@ -105,6 +113,8 @@ body: | ; CHECK-LABEL: name: spill_v64_undef_sub1_killed ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) @@ -126,6 +136,8 @@ body: | ; CHECK-LABEL: name: spill_v64_undef_sub0_killed ; CHECK: liveins: $vgpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) @@ -147,6 +159,8 @@ body: | ; CHECK-LABEL: name: spill_v128_kill ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll index 14f222a8c8e17..6be261c2ecb5a 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll +++ b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll @@ -16,15 +16,19 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[6:7] +; GFX9-NEXT: v_writelane_b32 v44, s4, 2 +; GFX9-NEXT: s_addk_i32 s32, 0x800 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v44, s30, 0 +; GFX9-NEXT: v_writelane_b32 v44, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v36, v16 ; GFX9-NEXT: v_mov_b32_e32 v35, v15 ; GFX9-NEXT: v_mov_b32_e32 v34, v14 ; GFX9-NEXT: v_mov_b32_e32 v33, v13 ; GFX9-NEXT: v_mov_b32_e32 v32, v12 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: ;;#ASMSTART @@ -34,14 +38,10 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX9-NEXT: ;;#ASMSTART ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: image_gather4_c_b_cl v[40:43], v[32:36], s[4:11], s[4:7] dmask:0x1 -; GFX9-NEXT: s_addk_i32 s32, 0x800 -; GFX9-NEXT: v_writelane_b32 v44, s4, 2 ; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4 ; GFX9-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX9-NEXT: v_writelane_b32 v44, s30, 0 -; GFX9-NEXT: v_writelane_b32 v44, s31, 1 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX9-NEXT: v_mov_b32_e32 v0, v40 @@ -52,8 +52,8 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v44, 1 ; GFX9-NEXT: v_readlane_b32 s30, v44, 0 +; GFX9-NEXT: v_readlane_b32 s31, v44, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v44, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -72,15 +72,19 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s5 +; GFX10-NEXT: v_writelane_b32 v44, s4, 2 +; GFX10-NEXT: s_addk_i32 s32, 0x400 +; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill +; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill +; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill +; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v44, s30, 0 +; GFX10-NEXT: v_writelane_b32 v44, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v36, v16 ; GFX10-NEXT: v_mov_b32_e32 v35, v15 ; GFX10-NEXT: v_mov_b32_e32 v34, v14 ; GFX10-NEXT: v_mov_b32_e32 v33, v13 ; GFX10-NEXT: v_mov_b32_e32 v32, v12 -; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill -; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: ;;#ASMSTART @@ -90,14 +94,11 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: image_gather4_c_b_cl v[40:43], v[32:36], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D -; GFX10-NEXT: s_addk_i32 s32, 0x400 -; GFX10-NEXT: v_writelane_b32 v44, s4, 2 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX10-NEXT: v_writelane_b32 v44, s30, 0 -; GFX10-NEXT: v_writelane_b32 v44, s31, 1 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: v_mov_b32_e32 v0, v40 @@ -109,8 +110,8 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:12 -; GFX10-NEXT: v_readlane_b32 s31, v44, 1 ; GFX10-NEXT: v_readlane_b32 s30, v44, 0 +; GFX10-NEXT: v_readlane_b32 s31, v44, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s4, v44, 2 ; GFX10-NEXT: s_or_saveexec_b32 s5, -1 @@ -129,14 +130,21 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_dual_mov_b32 v36, v16 :: v_dual_mov_b32 v35, v15 -; GFX11-NEXT: v_dual_mov_b32 v34, v14 :: v_dual_mov_b32 v33, v13 -; GFX11-NEXT: v_mov_b32_e32 v32, v12 +; GFX11-NEXT: v_writelane_b32 v44, s0, 2 +; GFX11-NEXT: s_add_i32 s32, s32, 32 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s33 +; GFX11-NEXT: v_writelane_b32 v44, s30, 0 +; GFX11-NEXT: v_writelane_b32 v44, s31, 1 +; GFX11-NEXT: v_dual_mov_b32 v36, v16 :: v_dual_mov_b32 v35, v15 +; GFX11-NEXT: v_dual_mov_b32 v34, v14 :: v_dual_mov_b32 v33, v13 +; GFX11-NEXT: v_mov_b32_e32 v32, v12 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: ;;#ASMSTART @@ -146,14 +154,10 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: image_gather4_c_b_cl v[40:43], v[32:36], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D -; GFX11-NEXT: s_add_i32 s32, s32, 32 -; GFX11-NEXT: v_writelane_b32 v44, s0, 2 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, extern_func@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, extern_func@gotpcrel32@hi+12 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: v_writelane_b32 v44, s30, 0 -; GFX11-NEXT: v_writelane_b32 v44, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: v_dual_mov_b32 v0, v40 :: v_dual_mov_b32 v1, v41 @@ -163,8 +167,8 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:4 ; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:8 ; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:12 -; GFX11-NEXT: v_readlane_b32 s31, v44, 1 ; GFX11-NEXT: v_readlane_b32 s30, v44, 0 +; GFX11-NEXT: v_readlane_b32 s31, v44, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v44, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 @@ -206,25 +210,25 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[6:7] +; GFX9-NEXT: v_writelane_b32 v45, s4, 2 +; GFX9-NEXT: s_addk_i32 s32, 0x800 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX9-NEXT: v_writelane_b32 v45, s30, 0 +; GFX9-NEXT: v_writelane_b32 v45, s31, 1 ; GFX9-NEXT: v_mov_b32_e32 v44, v16 ; GFX9-NEXT: v_mov_b32_e32 v43, v15 ; GFX9-NEXT: v_mov_b32_e32 v42, v14 ; GFX9-NEXT: v_mov_b32_e32 v41, v13 ; GFX9-NEXT: v_mov_b32_e32 v40, v12 ; GFX9-NEXT: image_gather4_c_b_cl v[0:3], v[40:44], s[4:11], s[4:7] dmask:0x1 -; GFX9-NEXT: s_addk_i32 s32, 0x800 -; GFX9-NEXT: v_writelane_b32 v45, s4, 2 ; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4 ; GFX9-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; GFX9-NEXT: v_writelane_b32 v45, s30, 0 -; GFX9-NEXT: v_writelane_b32 v45, s31, 1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GFX9-NEXT: s_waitcnt lgkmcnt(0) @@ -236,8 +240,8 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload -; GFX9-NEXT: v_readlane_b32 s31, v45, 1 ; GFX9-NEXT: v_readlane_b32 s30, v45, 0 +; GFX9-NEXT: v_readlane_b32 s31, v45, 1 ; GFX9-NEXT: s_mov_b32 s32, s33 ; GFX9-NEXT: v_readlane_b32 s4, v45, 2 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 @@ -256,25 +260,26 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX10-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s5 +; GFX10-NEXT: v_writelane_b32 v45, s4, 2 +; GFX10-NEXT: s_addk_i32 s32, 0x400 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 ; 4-byte Folded Spill +; GFX10-NEXT: v_writelane_b32 v45, s30, 0 +; GFX10-NEXT: v_writelane_b32 v45, s31, 1 ; GFX10-NEXT: image_gather4_c_b_cl v[0:3], v[12:16], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D -; GFX10-NEXT: s_addk_i32 s32, 0x400 -; GFX10-NEXT: v_writelane_b32 v45, s4, 2 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12 ; GFX10-NEXT: v_mov_b32_e32 v40, v16 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v41, v15 -; GFX10-NEXT: v_writelane_b32 v45, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v42, v14 ; GFX10-NEXT: v_mov_b32_e32 v43, v13 ; GFX10-NEXT: v_mov_b32_e32 v44, v12 -; GFX10-NEXT: v_writelane_b32 v45, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GFX10-NEXT: s_waitcnt lgkmcnt(0) @@ -286,8 +291,8 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:12 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:16 -; GFX10-NEXT: v_readlane_b32 s31, v45, 1 ; GFX10-NEXT: v_readlane_b32 s30, v45, 0 +; GFX10-NEXT: v_readlane_b32 s31, v45, 1 ; GFX10-NEXT: s_mov_b32 s32, s33 ; GFX10-NEXT: v_readlane_b32 s4, v45, 2 ; GFX10-NEXT: s_or_saveexec_b32 s5, -1 @@ -306,24 +311,28 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v45, s33 offset:20 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 +; GFX11-NEXT: v_writelane_b32 v45, s0, 2 +; GFX11-NEXT: s_add_i32 s32, s32, 32 ; GFX11-NEXT: s_clause 0x4 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:16 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:12 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:8 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v43, s33 offset:4 +; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v44, s33 +; GFX11-NEXT: v_writelane_b32 v45, s30, 0 +; GFX11-NEXT: v_writelane_b32 v45, s31, 1 ; GFX11-NEXT: image_gather4_c_b_cl v[0:3], v[12:16], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D -; GFX11-NEXT: s_add_i32 s32, s32, 32 -; GFX11-NEXT: v_writelane_b32 v45, s0, 2 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, extern_func@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, extern_func@gotpcrel32@hi+12 ; GFX11-NEXT: v_dual_mov_b32 v40, v16 :: v_dual_mov_b32 v41, v15 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 -; GFX11-NEXT: v_writelane_b32 v45, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v42, v14 :: v_dual_mov_b32 v43, v13 ; GFX11-NEXT: v_mov_b32_e32 v44, v12 -; GFX11-NEXT: v_writelane_b32 v45, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off ; GFX11-NEXT: s_waitcnt lgkmcnt(0) @@ -335,8 +344,8 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:12 ; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:16 -; GFX11-NEXT: v_readlane_b32 s31, v45, 1 ; GFX11-NEXT: v_readlane_b32 s30, v45, 0 +; GFX11-NEXT: v_readlane_b32 s31, v45, 1 ; GFX11-NEXT: s_mov_b32 s32, s33 ; GFX11-NEXT: v_readlane_b32 s0, v45, 2 ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 diff --git a/llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll b/llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll index cf2976261d3d2..7996a2dd1a4dd 100644 --- a/llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll +++ b/llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt -mtriple=amdgcn -mcpu=gfx906 -amdgpu-late-codegenprepare -S -o - %s | FileCheck --check-prefix=GFX906 %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-late-codegenprepare < %s | FileCheck --check-prefix=DEFAULT %s define amdgpu_kernel void @v3i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) { ; GFX906-LABEL: define amdgpu_kernel void @v3i8_liveout( @@ -25,6 +25,29 @@ define amdgpu_kernel void @v3i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) ; GFX906-NEXT: store <3 x i8> [[TMP3]], ptr addrspace(1) [[DST]], align 4 ; GFX906-NEXT: ret void ; +; DEFAULT-LABEL: define amdgpu_kernel void @v3i8_liveout( +; DEFAULT-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0:[0-9]+]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() +; DEFAULT-NEXT: [[GEP1:%.*]] = getelementptr <3 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC1:%.*]] = load <3 x i8>, ptr addrspace(1) [[GEP1]], align 4 +; DEFAULT-NEXT: [[TMP0:%.*]] = shufflevector <3 x i8> [[VEC1]], <3 x i8> poison, <4 x i32> +; DEFAULT-NEXT: [[VEC1_BC:%.*]] = bitcast <4 x i8> [[TMP0]] to i32 +; DEFAULT-NEXT: [[GEP2:%.*]] = getelementptr <3 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC2:%.*]] = load <3 x i8>, ptr addrspace(1) [[GEP2]], align 4 +; DEFAULT-NEXT: [[TMP1:%.*]] = shufflevector <3 x i8> [[VEC2]], <3 x i8> poison, <4 x i32> +; DEFAULT-NEXT: [[VEC2_BC:%.*]] = bitcast <4 x i8> [[TMP1]] to i32 +; DEFAULT-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15 +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_2:%.*]] +; DEFAULT: bb.1: +; DEFAULT-NEXT: br label [[BB_2]] +; DEFAULT: bb.2: +; DEFAULT-NEXT: [[PHI5_TC:%.*]] = phi i32 [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ] +; DEFAULT-NEXT: [[TMP2:%.*]] = trunc i32 [[PHI5_TC]] to i24 +; DEFAULT-NEXT: [[PHI5:%.*]] = bitcast i24 [[TMP2]] to <3 x i8> +; DEFAULT-NEXT: store <3 x i8> [[PHI5]], ptr addrspace(1) [[DST]], align 4 +; DEFAULT-NEXT: ret void +; entry: %idx = call i32 @llvm.amdgcn.workitem.id.x() %gep1 = getelementptr <3 x i8>, ptr addrspace(1) %src1, i32 %idx @@ -37,8 +60,8 @@ bb.1: br label %bb.2 bb.2: - %tmp5 = phi <3 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ] - store <3 x i8> %tmp5, ptr addrspace(1) %dst, align 4 + %phi5 = phi <3 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ] + store <3 x i8> %phi5, ptr addrspace(1) %dst, align 4 ret void } @@ -63,6 +86,26 @@ define amdgpu_kernel void @v4i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) ; GFX906-NEXT: store <4 x i8> [[TMP5_TC_BC]], ptr addrspace(1) [[DST]], align 4 ; GFX906-NEXT: ret void ; +; DEFAULT-LABEL: define amdgpu_kernel void @v4i8_liveout( +; DEFAULT-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() +; DEFAULT-NEXT: [[GEP1:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC1:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP1]], align 4 +; DEFAULT-NEXT: [[VEC1_BC:%.*]] = bitcast <4 x i8> [[VEC1]] to i32 +; DEFAULT-NEXT: [[GEP2:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC2:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP2]], align 4 +; DEFAULT-NEXT: [[VEC2_BC:%.*]] = bitcast <4 x i8> [[VEC2]] to i32 +; DEFAULT-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15 +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_2:%.*]] +; DEFAULT: bb.1: +; DEFAULT-NEXT: br label [[BB_2]] +; DEFAULT: bb.2: +; DEFAULT-NEXT: [[PHI5_TC:%.*]] = phi i32 [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ] +; DEFAULT-NEXT: [[PHI5:%.*]] = bitcast i32 [[PHI5_TC]] to <4 x i8> +; DEFAULT-NEXT: store <4 x i8> [[PHI5]], ptr addrspace(1) [[DST]], align 4 +; DEFAULT-NEXT: ret void +; entry: %idx = call i32 @llvm.amdgcn.workitem.id.x() %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx @@ -75,8 +118,8 @@ bb.1: br label %bb.2 bb.2: - %tmp5 = phi <4 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ] - store <4 x i8> %tmp5, ptr addrspace(1) %dst, align 4 + %phi5 = phi <4 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ] + store <4 x i8> %phi5, ptr addrspace(1) %dst, align 4 ret void } @@ -104,6 +147,29 @@ define amdgpu_kernel void @v5i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) ; GFX906-NEXT: store <5 x i8> [[TMP3]], ptr addrspace(1) [[DST]], align 4 ; GFX906-NEXT: ret void ; +; DEFAULT-LABEL: define amdgpu_kernel void @v5i8_liveout( +; DEFAULT-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() +; DEFAULT-NEXT: [[GEP1:%.*]] = getelementptr <5 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC1:%.*]] = load <5 x i8>, ptr addrspace(1) [[GEP1]], align 8 +; DEFAULT-NEXT: [[TMP0:%.*]] = shufflevector <5 x i8> [[VEC1]], <5 x i8> poison, <8 x i32> +; DEFAULT-NEXT: [[VEC1_BC:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +; DEFAULT-NEXT: [[GEP2:%.*]] = getelementptr <5 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC2:%.*]] = load <5 x i8>, ptr addrspace(1) [[GEP2]], align 8 +; DEFAULT-NEXT: [[TMP1:%.*]] = shufflevector <5 x i8> [[VEC2]], <5 x i8> poison, <8 x i32> +; DEFAULT-NEXT: [[VEC2_BC:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +; DEFAULT-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15 +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_2:%.*]] +; DEFAULT: bb.1: +; DEFAULT-NEXT: br label [[BB_2]] +; DEFAULT: bb.2: +; DEFAULT-NEXT: [[PHI5_TC:%.*]] = phi <2 x i32> [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ] +; DEFAULT-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[PHI5_TC]] to <8 x i8> +; DEFAULT-NEXT: [[PHI5:%.*]] = shufflevector <8 x i8> [[TMP2]], <8 x i8> poison, <5 x i32> +; DEFAULT-NEXT: store <5 x i8> [[PHI5]], ptr addrspace(1) [[DST]], align 4 +; DEFAULT-NEXT: ret void +; entry: %idx = call i32 @llvm.amdgcn.workitem.id.x() %gep1 = getelementptr <5 x i8>, ptr addrspace(1) %src1, i32 %idx @@ -116,8 +182,8 @@ bb.1: br label %bb.2 bb.2: - %tmp5 = phi <5 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ] - store <5 x i8> %tmp5, ptr addrspace(1) %dst, align 4 + %phi5 = phi <5 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ] + store <5 x i8> %phi5, ptr addrspace(1) %dst, align 4 ret void } @@ -142,6 +208,26 @@ define amdgpu_kernel void @v8i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) ; GFX906-NEXT: store <8 x i8> [[TMP5_TC_BC]], ptr addrspace(1) [[DST]], align 4 ; GFX906-NEXT: ret void ; +; DEFAULT-LABEL: define amdgpu_kernel void @v8i8_liveout( +; DEFAULT-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() +; DEFAULT-NEXT: [[GEP1:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC1:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP1]], align 8 +; DEFAULT-NEXT: [[VEC1_BC:%.*]] = bitcast <8 x i8> [[VEC1]] to <2 x i32> +; DEFAULT-NEXT: [[GEP2:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC2:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP2]], align 8 +; DEFAULT-NEXT: [[VEC2_BC:%.*]] = bitcast <8 x i8> [[VEC2]] to <2 x i32> +; DEFAULT-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15 +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_2:%.*]] +; DEFAULT: bb.1: +; DEFAULT-NEXT: br label [[BB_2]] +; DEFAULT: bb.2: +; DEFAULT-NEXT: [[PHI5_TC:%.*]] = phi <2 x i32> [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ] +; DEFAULT-NEXT: [[PHI5:%.*]] = bitcast <2 x i32> [[PHI5_TC]] to <8 x i8> +; DEFAULT-NEXT: store <8 x i8> [[PHI5]], ptr addrspace(1) [[DST]], align 4 +; DEFAULT-NEXT: ret void +; entry: %idx = call i32 @llvm.amdgcn.workitem.id.x() %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx @@ -154,8 +240,8 @@ bb.1: br label %bb.2 bb.2: - %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ] - store <8 x i8> %tmp5, ptr addrspace(1) %dst, align 4 + %phi5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ] + store <8 x i8> %phi5, ptr addrspace(1) %dst, align 4 ret void } @@ -185,6 +271,31 @@ define amdgpu_kernel void @repeat_successor(i32 %in, ptr addrspace(1) %src1, ptr ; GFX906: return: ; GFX906-NEXT: ret void ; +; DEFAULT-LABEL: define amdgpu_kernel void @repeat_successor( +; DEFAULT-SAME: i32 [[IN:%.*]], ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() +; DEFAULT-NEXT: [[GEP1:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC1:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP1]], align 4 +; DEFAULT-NEXT: [[VEC1_BC:%.*]] = bitcast <4 x i8> [[VEC1]] to i32 +; DEFAULT-NEXT: [[GEP2:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC2:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP2]], align 4 +; DEFAULT-NEXT: [[VEC2_BC:%.*]] = bitcast <4 x i8> [[VEC2]] to i32 +; DEFAULT-NEXT: switch i32 [[IN]], label [[RETURN:%.*]] [ +; DEFAULT-NEXT: i32 1, label [[RETURN_SINK_SPLIT:%.*]] +; DEFAULT-NEXT: i32 2, label [[RETURN_SINK_SPLIT]] +; DEFAULT-NEXT: i32 3, label [[SW_BB5:%.*]] +; DEFAULT-NEXT: ] +; DEFAULT: sw.bb5: +; DEFAULT-NEXT: br label [[RETURN_SINK_SPLIT]] +; DEFAULT: return.sink.split: +; DEFAULT-NEXT: [[PHI5_TC:%.*]] = phi i32 [ [[VEC2_BC]], [[SW_BB5]] ], [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC1_BC]], [[ENTRY]] ] +; DEFAULT-NEXT: [[PHI5:%.*]] = bitcast i32 [[PHI5_TC]] to <4 x i8> +; DEFAULT-NEXT: store <4 x i8> [[PHI5]], ptr addrspace(1) [[DST]], align 4 +; DEFAULT-NEXT: ret void +; DEFAULT: return: +; DEFAULT-NEXT: ret void +; entry: %idx = call i32 @llvm.amdgcn.workitem.id.x() %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx @@ -201,8 +312,8 @@ sw.bb5: br label %return.sink.split return.sink.split: - %tmp5 = phi <4 x i8> [ %vec2, %sw.bb5 ], [ %vec1, %entry ], [ %vec1, %entry ] - store <4 x i8> %tmp5, ptr addrspace(1) %dst, align 4 + %phi5 = phi <4 x i8> [ %vec2, %sw.bb5 ], [ %vec1, %entry ], [ %vec1, %entry ] + store <4 x i8> %phi5, ptr addrspace(1) %dst, align 4 ret void return: @@ -236,6 +347,32 @@ define amdgpu_kernel void @v8i8_phi_chain(ptr addrspace(1) %src1, ptr addrspace( ; GFX906-NEXT: store <8 x i8> [[TMP7_TC_BC]], ptr addrspace(1) [[DST1]], align 4 ; GFX906-NEXT: ret void ; +; DEFAULT-LABEL: define amdgpu_kernel void @v8i8_phi_chain( +; DEFAULT-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST0:%.*]], ptr addrspace(1) captures(none) [[DST1:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() +; DEFAULT-NEXT: [[GEP1:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC1:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP1]], align 8 +; DEFAULT-NEXT: [[VEC1_BC:%.*]] = bitcast <8 x i8> [[VEC1]] to <2 x i32> +; DEFAULT-NEXT: [[GEP2:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC2:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP2]], align 8 +; DEFAULT-NEXT: [[VEC2_BC:%.*]] = bitcast <8 x i8> [[VEC2]] to <2 x i32> +; DEFAULT-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15 +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_2:%.*]] +; DEFAULT: bb.1: +; DEFAULT-NEXT: [[CMP2:%.*]] = icmp ult i32 [[IDX]], 7 +; DEFAULT-NEXT: br i1 [[CMP2]], label [[BB_2]], label [[BB_3:%.*]] +; DEFAULT: bb.2: +; DEFAULT-NEXT: [[PHI5_TC:%.*]] = phi <2 x i32> [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ] +; DEFAULT-NEXT: [[PHI5:%.*]] = bitcast <2 x i32> [[PHI5_TC]] to <8 x i8> +; DEFAULT-NEXT: store <8 x i8> [[PHI5]], ptr addrspace(1) [[DST0]], align 4 +; DEFAULT-NEXT: br label [[BB_3]] +; DEFAULT: bb.3: +; DEFAULT-NEXT: [[PHI7_TC:%.*]] = phi <2 x i32> [ [[VEC2_BC]], [[BB_1]] ], [ [[PHI5_TC]], [[BB_2]] ] +; DEFAULT-NEXT: [[PHI7:%.*]] = bitcast <2 x i32> [[PHI7_TC]] to <8 x i8> +; DEFAULT-NEXT: store <8 x i8> [[PHI7]], ptr addrspace(1) [[DST1]], align 4 +; DEFAULT-NEXT: ret void +; entry: %idx = call i32 @llvm.amdgcn.workitem.id.x() %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx @@ -249,13 +386,13 @@ bb.1: br i1 %cmp2, label %bb.2, label %bb.3 bb.2: - %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ] - store <8 x i8> %tmp5, ptr addrspace(1) %dst0, align 4 + %phi5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ] + store <8 x i8> %phi5, ptr addrspace(1) %dst0, align 4 br label %bb.3 bb.3: - %tmp7 = phi <8 x i8> [ %vec2, %bb.1], [%tmp5, %bb.2] - store <8 x i8> %tmp7, ptr addrspace(1) %dst1, align 4 + %phi7 = phi <8 x i8> [ %vec2, %bb.1], [%phi5, %bb.2] + store <8 x i8> %phi7, ptr addrspace(1) %dst1, align 4 ret void } @@ -285,6 +422,31 @@ define amdgpu_kernel void @v8i8_multi_block(ptr addrspace(1) %src1, ptr addrspac ; GFX906-NEXT: store <8 x i8> [[TMP5_TC_BC]], ptr addrspace(1) [[DST1]], align 4 ; GFX906-NEXT: ret void ; +; DEFAULT-LABEL: define amdgpu_kernel void @v8i8_multi_block( +; DEFAULT-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST0:%.*]], ptr addrspace(1) captures(none) [[DST1:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() +; DEFAULT-NEXT: [[GEP1:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC1:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP1]], align 8 +; DEFAULT-NEXT: [[VEC1_BC:%.*]] = bitcast <8 x i8> [[VEC1]] to <2 x i32> +; DEFAULT-NEXT: [[GEP2:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC2:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP2]], align 8 +; DEFAULT-NEXT: [[VEC2_BC:%.*]] = bitcast <8 x i8> [[VEC2]] to <2 x i32> +; DEFAULT-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15 +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_3:%.*]] +; DEFAULT: bb.1: +; DEFAULT-NEXT: [[CMP2:%.*]] = icmp ult i32 [[IDX]], 7 +; DEFAULT-NEXT: br i1 [[CMP2]], label [[BB_2:%.*]], label [[BB_3]] +; DEFAULT: bb.2: +; DEFAULT-NEXT: [[VEC1_BC_BC:%.*]] = bitcast <2 x i32> [[VEC1_BC]] to <8 x i8> +; DEFAULT-NEXT: store <8 x i8> [[VEC1_BC_BC]], ptr addrspace(1) [[DST0]], align 4 +; DEFAULT-NEXT: br label [[BB_3]] +; DEFAULT: bb.3: +; DEFAULT-NEXT: [[PHI5_TC:%.*]] = phi <2 x i32> [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ], [ [[VEC2_BC]], [[BB_2]] ] +; DEFAULT-NEXT: [[PHI5:%.*]] = bitcast <2 x i32> [[PHI5_TC]] to <8 x i8> +; DEFAULT-NEXT: store <8 x i8> [[PHI5]], ptr addrspace(1) [[DST1]], align 4 +; DEFAULT-NEXT: ret void +; entry: %idx = call i32 @llvm.amdgcn.workitem.id.x() %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx @@ -302,8 +464,8 @@ bb.2: br label %bb.3 bb.3: - %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ], [ %vec2, %bb.2] - store <8 x i8> %tmp5, ptr addrspace(1) %dst1, align 4 + %phi5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ], [ %vec2, %bb.2] + store <8 x i8> %phi5, ptr addrspace(1) %dst1, align 4 ret void } @@ -331,6 +493,29 @@ define amdgpu_kernel void @v32i8_loop_carried(ptr addrspace(1) %src1, ptr addrsp ; GFX906-NEXT: store <4 x i8> [[VEC2_BC_BC]], ptr addrspace(1) [[DST]], align 4 ; GFX906-NEXT: ret void ; +; DEFAULT-LABEL: define amdgpu_kernel void @v32i8_loop_carried( +; DEFAULT-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() +; DEFAULT-NEXT: [[GEP1:%.*]] = getelementptr <32 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]] +; DEFAULT-NEXT: [[VEC1:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP1]], align 4 +; DEFAULT-NEXT: [[VEC1_BC:%.*]] = bitcast <4 x i8> [[VEC1]] to i32 +; DEFAULT-NEXT: br label [[BB_1:%.*]] +; DEFAULT: bb.1: +; DEFAULT-NEXT: [[TEMP_TC:%.*]] = phi i32 [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC:%.*]], [[BB_1]] ] +; DEFAULT-NEXT: [[TEMP_TC_BC:%.*]] = bitcast i32 [[TEMP_TC]] to <4 x i8> +; DEFAULT-NEXT: [[VEC1_BC_BC:%.*]] = bitcast i32 [[VEC1_BC]] to <4 x i8> +; DEFAULT-NEXT: [[VEC3:%.*]] = shufflevector <4 x i8> [[VEC1_BC_BC]], <4 x i8> [[TEMP_TC_BC]], <4 x i32> +; DEFAULT-NEXT: [[VEC2_BC]] = bitcast <4 x i8> [[VEC3]] to i32 +; DEFAULT-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15 +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_1]], label [[BB_2:%.*]] +; DEFAULT: 0: +; DEFAULT-NEXT: br label [[BB_2]] +; DEFAULT: bb.2: +; DEFAULT-NEXT: [[VEC2:%.*]] = bitcast i32 [[VEC2_BC]] to <4 x i8> +; DEFAULT-NEXT: store <4 x i8> [[VEC2]], ptr addrspace(1) [[DST]], align 4 +; DEFAULT-NEXT: ret void +; entry: %idx = call i32 @llvm.amdgcn.workitem.id.x() %gep1 = getelementptr <32 x i8>, ptr addrspace(1) %src1, i32 %idx @@ -371,6 +556,25 @@ define void @broken_phi() { ; GFX906-NEXT: [[I8]] = phi <4 x i8> [ zeroinitializer, [[BB5]] ], [ zeroinitializer, [[BB3]] ] ; GFX906-NEXT: br label [[BB1]] ; +; DEFAULT-LABEL: define void @broken_phi( +; DEFAULT-SAME: ) #[[ATTR0]] { +; DEFAULT-NEXT: bb: +; DEFAULT-NEXT: br label [[BB1:%.*]] +; DEFAULT: bb1: +; DEFAULT-NEXT: [[I:%.*]] = phi <4 x i8> [ splat (i8 1), [[BB:%.*]] ], [ [[I8:%.*]], [[BB7:%.*]] ] +; DEFAULT-NEXT: br i1 false, label [[BB3:%.*]], label [[BB2:%.*]] +; DEFAULT: bb2: +; DEFAULT-NEXT: br label [[BB3]] +; DEFAULT: bb3: +; DEFAULT-NEXT: [[I4:%.*]] = phi <4 x i8> [ zeroinitializer, [[BB2]] ], [ [[I]], [[BB1]] ] +; DEFAULT-NEXT: br i1 false, label [[BB7]], label [[BB5:%.*]] +; DEFAULT: bb5: +; DEFAULT-NEXT: [[I6:%.*]] = call <4 x i8> @llvm.smax.v4i8(<4 x i8> [[I4]], <4 x i8> zeroinitializer) +; DEFAULT-NEXT: br label [[BB7]] +; DEFAULT: bb7: +; DEFAULT-NEXT: [[I8]] = phi <4 x i8> [ zeroinitializer, [[BB5]] ], [ zeroinitializer, [[BB3]] ] +; DEFAULT-NEXT: br label [[BB1]] +; bb: br label %bb1 bb1: @@ -406,6 +610,19 @@ define amdgpu_kernel void @reuseOp() { ; GFX906-NEXT: [[VAL:%.*]] = extractelement <16 x i8> [[SEL0]], i64 0 ; GFX906-NEXT: ret void ; +; DEFAULT-LABEL: define amdgpu_kernel void @reuseOp( +; DEFAULT-SAME: ) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[VEC1:%.*]] = insertelement <16 x i8> zeroinitializer, i8 0, i64 0 +; DEFAULT-NEXT: br label [[BB_1:%.*]] +; DEFAULT: bb.1: +; DEFAULT-NEXT: [[SEL0:%.*]] = select i1 false, <16 x i8> zeroinitializer, <16 x i8> zeroinitializer +; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 false, <16 x i8> [[VEC1]], <16 x i8> [[SEL0]] +; DEFAULT-NEXT: br label [[BB_2:%.*]] +; DEFAULT: bb.2: +; DEFAULT-NEXT: [[VAL:%.*]] = extractelement <16 x i8> [[SEL0]], i64 0 +; DEFAULT-NEXT: ret void +; entry: %vec1 = insertelement <16 x i8> zeroinitializer, i8 0, i64 0 br label %bb.1 @@ -420,7 +637,6 @@ bb.2: ret void } - define amdgpu_kernel void @deletedPHI(i32 %in0, i1 %cmp, <10 x i8> %invec0) { ; GFX906-LABEL: define amdgpu_kernel void @deletedPHI( ; GFX906-SAME: i32 [[IN0:%.*]], i1 [[CMP:%.*]], <10 x i8> [[INVEC0:%.*]]) #[[ATTR0]] { @@ -458,6 +674,42 @@ define amdgpu_kernel void @deletedPHI(i32 %in0, i1 %cmp, <10 x i8> %invec0) { ; GFX906-NEXT: [[VEC1]] = shufflevector <10 x i8> [[PHI6]], <10 x i8> zeroinitializer, <10 x i32> ; GFX906-NEXT: br label [[BB_1]] ; +; DEFAULT-LABEL: define amdgpu_kernel void @deletedPHI( +; DEFAULT-SAME: i32 [[IN0:%.*]], i1 [[CMP:%.*]], <10 x i8> [[INVEC0:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: br label [[BB_1:%.*]] +; DEFAULT: bb.1: +; DEFAULT-NEXT: [[PHI0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 1, [[BB_11:%.*]] ] +; DEFAULT-NEXT: [[PHI1:%.*]] = phi <10 x i8> [ splat (i8 1), [[ENTRY]] ], [ [[VEC1:%.*]], [[BB_11]] ] +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_3:%.*]], label [[BB_2:%.*]] +; DEFAULT: bb.2: +; DEFAULT-NEXT: br label [[BB_3]] +; DEFAULT: bb.3: +; DEFAULT-NEXT: [[PHI2:%.*]] = phi <10 x i8> [ zeroinitializer, [[BB_2]] ], [ [[PHI1]], [[BB_1]] ] +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_5:%.*]], label [[BB_4:%.*]] +; DEFAULT: bb.4: +; DEFAULT-NEXT: [[VEC0:%.*]] = insertelement <10 x i8> [[PHI2]], i8 0, i64 0 +; DEFAULT-NEXT: br label [[BB_5]] +; DEFAULT: bb.5: +; DEFAULT-NEXT: [[PHI3:%.*]] = phi <10 x i8> [ [[VEC0]], [[BB_4]] ], [ [[PHI2]], [[BB_3]] ] +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_7:%.*]], label [[BB_6:%.*]] +; DEFAULT: bb.6: +; DEFAULT-NEXT: br label [[BB_7]] +; DEFAULT: bb.7: +; DEFAULT-NEXT: [[PHI4:%.*]] = phi <10 x i8> [ [[INVEC0]], [[BB_6]] ], [ [[PHI3]], [[BB_5]] ] +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_9:%.*]], label [[BB_8:%.*]] +; DEFAULT: bb.8: +; DEFAULT-NEXT: br label [[BB_9]] +; DEFAULT: bb.9: +; DEFAULT-NEXT: [[PHI5:%.*]] = phi <10 x i8> [ [[INVEC0]], [[BB_8]] ], [ [[PHI4]], [[BB_7]] ] +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_11]], label [[BB_10:%.*]] +; DEFAULT: bb.10: +; DEFAULT-NEXT: br label [[BB_11]] +; DEFAULT: bb.11: +; DEFAULT-NEXT: [[PHI6:%.*]] = phi <10 x i8> [ zeroinitializer, [[BB_10]] ], [ [[PHI5]], [[BB_9]] ] +; DEFAULT-NEXT: [[VEC1]] = shufflevector <10 x i8> [[PHI6]], <10 x i8> zeroinitializer, <10 x i32> +; DEFAULT-NEXT: br label [[BB_1]] +; entry: br label %bb.1 @@ -530,6 +782,31 @@ define amdgpu_kernel void @multiple_unwind(i1 %cmp, <10 x i8> %invec) { ; GFX906: bb.8: ; GFX906-NEXT: br label [[BB_1]] ; +; DEFAULT-LABEL: define amdgpu_kernel void @multiple_unwind( +; DEFAULT-SAME: i1 [[CMP:%.*]], <10 x i8> [[INVEC:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: br label [[BB_1:%.*]] +; DEFAULT: bb.1: +; DEFAULT-NEXT: [[PHI0:%.*]] = phi <10 x i8> [ splat (i8 1), [[ENTRY:%.*]] ], [ [[PHI3:%.*]], [[BB_8:%.*]] ] +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_3:%.*]], label [[BB_2:%.*]] +; DEFAULT: bb.2: +; DEFAULT-NEXT: br label [[BB_3]] +; DEFAULT: bb.3: +; DEFAULT-NEXT: [[PHI1:%.*]] = phi <10 x i8> [ zeroinitializer, [[BB_2]] ], [ [[PHI0]], [[BB_1]] ] +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_5:%.*]], label [[BB_4:%.*]] +; DEFAULT: bb.4: +; DEFAULT-NEXT: br label [[BB_5]] +; DEFAULT: bb.5: +; DEFAULT-NEXT: [[PHI2:%.*]] = phi <10 x i8> [ [[PHI0]], [[BB_4]] ], [ [[PHI1]], [[BB_3]] ] +; DEFAULT-NEXT: br i1 [[CMP]], label [[BB_7:%.*]], label [[BB_6:%.*]] +; DEFAULT: bb.6: +; DEFAULT-NEXT: br label [[BB_7]] +; DEFAULT: bb.7: +; DEFAULT-NEXT: [[PHI3]] = phi <10 x i8> [ [[INVEC]], [[BB_6]] ], [ [[PHI2]], [[BB_5]] ] +; DEFAULT-NEXT: br label [[BB_8]] +; DEFAULT: bb.8: +; DEFAULT-NEXT: br label [[BB_1]] +; entry: br label %bb.1 diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir index 40b768a2c2bad..147145b907994 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir @@ -1,6 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=si-insert-waitcnts -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s + --- name: waitcnt-check-inorder body: | diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll index 28c6b40554bb6..110013258bd89 100644 --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -3076,18 +3076,18 @@ define void @callee_no_stack_with_call() #1 { ; GFX1032-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_mov_b32 exec_lo, s17 -; GFX1032-NEXT: s_addk_i32 s32, 0x200 ; GFX1032-NEXT: v_writelane_b32 v40, s16, 2 +; GFX1032-NEXT: v_writelane_b32 v40, s30, 0 +; GFX1032-NEXT: s_addk_i32 s32, 0x200 +; GFX1032-NEXT: v_writelane_b32 v40, s31, 1 ; GFX1032-NEXT: s_getpc_b64 s[16:17] ; GFX1032-NEXT: s_add_u32 s16, s16, external_void_func_void@gotpcrel32@lo+4 ; GFX1032-NEXT: s_addc_u32 s17, s17, external_void_func_void@gotpcrel32@hi+12 ; GFX1032-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX1032-NEXT: v_writelane_b32 v40, s30, 0 -; GFX1032-NEXT: v_writelane_b32 v40, s31, 1 ; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX1032-NEXT: v_readlane_b32 s31, v40, 1 ; GFX1032-NEXT: v_readlane_b32 s30, v40, 0 +; GFX1032-NEXT: v_readlane_b32 s31, v40, 1 ; GFX1032-NEXT: s_mov_b32 s32, s33 ; GFX1032-NEXT: v_readlane_b32 s4, v40, 2 ; GFX1032-NEXT: s_or_saveexec_b32 s5, -1 @@ -3107,18 +3107,18 @@ define void @callee_no_stack_with_call() #1 { ; GFX1064-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_mov_b64 exec, s[18:19] -; GFX1064-NEXT: s_addk_i32 s32, 0x400 ; GFX1064-NEXT: v_writelane_b32 v40, s16, 2 +; GFX1064-NEXT: v_writelane_b32 v40, s30, 0 +; GFX1064-NEXT: s_addk_i32 s32, 0x400 +; GFX1064-NEXT: v_writelane_b32 v40, s31, 1 ; GFX1064-NEXT: s_getpc_b64 s[16:17] ; GFX1064-NEXT: s_add_u32 s16, s16, external_void_func_void@gotpcrel32@lo+4 ; GFX1064-NEXT: s_addc_u32 s17, s17, external_void_func_void@gotpcrel32@hi+12 ; GFX1064-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 -; GFX1064-NEXT: v_writelane_b32 v40, s30, 0 -; GFX1064-NEXT: v_writelane_b32 v40, s31, 1 ; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_swappc_b64 s[30:31], s[16:17] -; GFX1064-NEXT: v_readlane_b32 s31, v40, 1 ; GFX1064-NEXT: v_readlane_b32 s30, v40, 0 +; GFX1064-NEXT: v_readlane_b32 s31, v40, 1 ; GFX1064-NEXT: s_mov_b32 s32, s33 ; GFX1064-NEXT: v_readlane_b32 s4, v40, 2 ; GFX1064-NEXT: s_or_saveexec_b64 s[6:7], -1 diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir b/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir index adba762235d8c..9b4bd18b986e2 100644 --- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir +++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir @@ -26,8 +26,13 @@ body: | ; CHECK-LABEL: name: save_inactive_lanes_non_csr_vgpr ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 ; CHECK-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr0, 0 ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 14, implicit $exec ; CHECK-NEXT: $exec_lo = S_XOR_B32 $sgpr0, -1, implicit-def $scc @@ -64,8 +69,12 @@ body: | ; CHECK-LABEL: name: save_all_lanes_csr_vgpr ; CHECK: liveins: $vgpr40 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 ; CHECK-NEXT: $sgpr0 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr40, 0 ; CHECK-NEXT: $vgpr40 = V_MOV_B32_e32 14, implicit $exec ; CHECK-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 $sgpr0 @@ -101,8 +110,13 @@ body: | ; CHECK-LABEL: name: save_csr_sgpr_to_non_csr_vgpr ; CHECK: liveins: $sgpr20, $vgpr191, $vgpr192 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 ; CHECK-NEXT: $vcc_lo = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr192, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr192, 0 ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 ; CHECK-NEXT: $vgpr192 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr192 ; CHECK-NEXT: $sgpr20 = S_MOV_B32 14, implicit $exec @@ -144,8 +158,12 @@ body: | ; CHECK-LABEL: name: save_csr_sgpr_to_csr_vgpr ; CHECK: liveins: $sgpr20, $vgpr191 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 ; CHECK-NEXT: $vcc_lo = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr191, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr191, 0 ; CHECK-NEXT: $vgpr191 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr191 ; CHECK-NEXT: $sgpr20 = S_MOV_B32 14, implicit $exec ; CHECK-NEXT: $sgpr20 = SI_RESTORE_S32_FROM_VGPR $vgpr191, 0 @@ -193,11 +211,20 @@ body: | ; CHECK-LABEL: name: vgpr_and_sgpr_csr ; CHECK: liveins: $sgpr20, $vgpr0, $vgpr1, $vgpr40, $vgpr49 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 ; CHECK-NEXT: $vcc_lo = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr0, 0 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr49, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr49, 256 ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr40, 128 ; CHECK-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr0 ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $sgpr20 ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr49, implicit-def $sgpr40 @@ -250,11 +277,21 @@ body: | ; CHECK-LABEL: name: split_orig_exec ; CHECK: liveins: $sgpr20, $vgpr0, $vgpr1, $vgpr40, $vgpr49 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 ; CHECK-NEXT: $vcc_lo = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr0, 0 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr49, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr49, 256 ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr40, 128 ; CHECK-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr0 ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $sgpr20 ; CHECK-NEXT: $sgpr3 = COPY $vcc_lo @@ -300,16 +337,32 @@ body: | ; CHECK-LABEL: name: vgpr_superregs ; CHECK: liveins: $vgpr0, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr40, $vgpr41, $vgpr42 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 ; CHECK-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr0, 0 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr2, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr2, 128 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr3, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr3, 256 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr4, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr4, 384 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.4, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr5, 512 ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.5, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr40, 640 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr41, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.6, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr41, 768 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr42, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.7, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr42, 896 ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 14, implicit $exec ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr2_vgpr3_vgpr4_vgpr5, implicit-def $vgpr40_vgpr41_vgpr42 ; CHECK-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.5, addrspace 5) @@ -360,6 +413,9 @@ body: | ; CHECK-LABEL: name: dont_restore_used_vgprs ; CHECK: liveins: $vgpr0, $vgpr20, $vgpr40 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 ; CHECK-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: S_NOP 0, implicit $vgpr0, implicit $vgpr20, implicit $vgpr40 ; CHECK-NEXT: $exec_lo = S_MOV_B32 $sgpr0 @@ -398,9 +454,16 @@ body: | ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 ; CHECK-NEXT: $vcc_lo = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr0, 0 ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr1, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr1, 128 ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 ; CHECK-NEXT: $sgpr1 = S_MOV_B32 $exec_lo ; CHECK-NEXT: V_CMPX_EQ_U32_nosdst_e64 $vgpr0, $vgpr1, implicit-def $exec, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll index a42c8ac706d27..75e06aed64748 100644 --- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll @@ -20,6 +20,7 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { ; DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; DAGISEL-NEXT: s_clause 0x1 ; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: s_wait_alu 0xfffe @@ -44,6 +45,7 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { ; GISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GISEL-NEXT: s_clause 0x1 ; GISEL-NEXT: scratch_store_b32 off, v0, s32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: s_wait_alu 0xfffe @@ -68,6 +70,7 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { ; DAGISEL64-NEXT: s_xor_saveexec_b64 vcc, -1 ; DAGISEL64-NEXT: s_clause 0x1 ; DAGISEL64-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; DAGISEL64-NEXT: s_mov_b64 exec, -1 ; DAGISEL64-NEXT: s_wait_alu 0xfffe @@ -93,6 +96,7 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { ; GISEL64-NEXT: s_xor_saveexec_b64 vcc, -1 ; GISEL64-NEXT: s_clause 0x1 ; GISEL64-NEXT: scratch_store_b32 off, v0, s32 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; GISEL64-NEXT: s_mov_b64 exec, -1 ; GISEL64-NEXT: s_wait_alu 0xfffe @@ -115,6 +119,7 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x1 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 @@ -147,6 +152,7 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 % ; DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; DAGISEL-NEXT: s_clause 0x1 ; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: s_wait_alu 0xfffe @@ -171,6 +177,7 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 % ; GISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GISEL-NEXT: s_clause 0x1 ; GISEL-NEXT: scratch_store_b32 off, v0, s32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: s_wait_alu 0xfffe @@ -195,6 +202,7 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 % ; DAGISEL64-NEXT: s_xor_saveexec_b64 vcc, -1 ; DAGISEL64-NEXT: s_clause 0x1 ; DAGISEL64-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; DAGISEL64-NEXT: s_mov_b64 exec, -1 ; DAGISEL64-NEXT: s_wait_alu 0xfffe @@ -219,6 +227,7 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 % ; GISEL64-NEXT: s_xor_saveexec_b64 vcc, -1 ; GISEL64-NEXT: s_clause 0x1 ; GISEL64-NEXT: scratch_store_b32 off, v0, s32 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; GISEL64-NEXT: s_mov_b64 exec, -1 ; GISEL64-NEXT: s_wait_alu 0xfffe @@ -240,6 +249,7 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 % ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x1 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 @@ -364,15 +374,18 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) { ; DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; DAGISEL-NEXT: s_clause 0x3 ; DAGISEL-NEXT: scratch_store_b32 off, v2, s32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 offset:4 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:8 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:16 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill +; DAGISEL-NEXT: v_writelane_b32 v2, s20, 0 ; DAGISEL-NEXT: ;;#ASMSTART ; DAGISEL-NEXT: ; clobber CSR ; DAGISEL-NEXT: ;;#ASMEND -; DAGISEL-NEXT: v_writelane_b32 v2, s20, 0 ; DAGISEL-NEXT: ;;#ASMSTART ; DAGISEL-NEXT: ; clobber non-CSR ; DAGISEL-NEXT: ;;#ASMEND @@ -403,15 +416,18 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) { ; GISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GISEL-NEXT: s_clause 0x3 ; GISEL-NEXT: scratch_store_b32 off, v2, s32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v0, s32 offset:4 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:8 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v49, s32 offset:16 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill +; GISEL-NEXT: v_writelane_b32 v2, s20, 0 ; GISEL-NEXT: ;;#ASMSTART ; GISEL-NEXT: ; clobber CSR ; GISEL-NEXT: ;;#ASMEND -; GISEL-NEXT: v_writelane_b32 v2, s20, 0 ; GISEL-NEXT: ;;#ASMSTART ; GISEL-NEXT: ; clobber non-CSR ; GISEL-NEXT: ;;#ASMEND @@ -442,15 +458,18 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) { ; DAGISEL64-NEXT: s_xor_saveexec_b64 vcc, -1 ; DAGISEL64-NEXT: s_clause 0x3 ; DAGISEL64-NEXT: scratch_store_b32 off, v2, s32 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v0, s32 offset:4 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:8 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v49, s32 offset:16 ; DAGISEL64-NEXT: s_mov_b64 exec, -1 ; DAGISEL64-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill +; DAGISEL64-NEXT: v_writelane_b32 v2, s20, 0 ; DAGISEL64-NEXT: ;;#ASMSTART ; DAGISEL64-NEXT: ; clobber CSR ; DAGISEL64-NEXT: ;;#ASMEND -; DAGISEL64-NEXT: v_writelane_b32 v2, s20, 0 ; DAGISEL64-NEXT: ;;#ASMSTART ; DAGISEL64-NEXT: ; clobber non-CSR ; DAGISEL64-NEXT: ;;#ASMEND @@ -482,15 +501,18 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) { ; GISEL64-NEXT: s_xor_saveexec_b64 vcc, -1 ; GISEL64-NEXT: s_clause 0x3 ; GISEL64-NEXT: scratch_store_b32 off, v2, s32 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v0, s32 offset:4 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:8 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v49, s32 offset:16 ; GISEL64-NEXT: s_mov_b64 exec, -1 ; GISEL64-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill +; GISEL64-NEXT: v_writelane_b32 v2, s20, 0 ; GISEL64-NEXT: ;;#ASMSTART ; GISEL64-NEXT: ; clobber CSR ; GISEL64-NEXT: ;;#ASMEND -; GISEL64-NEXT: v_writelane_b32 v2, s20, 0 ; GISEL64-NEXT: ;;#ASMSTART ; GISEL64-NEXT: ; clobber non-CSR ; GISEL64-NEXT: ;;#ASMEND @@ -519,17 +541,20 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 offset:4 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:8 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:16 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill +; GFX1250-DAGISEL-NEXT: v_writelane_b32 v2, s20, 0 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: ;;#ASMSTART ; GFX1250-DAGISEL-NEXT: ; clobber CSR ; GFX1250-DAGISEL-NEXT: ;;#ASMEND -; GFX1250-DAGISEL-NEXT: v_writelane_b32 v2, s20, 0 ; GFX1250-DAGISEL-NEXT: ;;#ASMSTART ; GFX1250-DAGISEL-NEXT: ; clobber non-CSR ; GFX1250-DAGISEL-NEXT: ;;#ASMEND @@ -908,6 +933,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) { ; DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; DAGISEL-NEXT: s_clause 0x1 ; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) @@ -938,6 +964,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) { ; GISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GISEL-NEXT: s_clause 0x1 ; GISEL-NEXT: scratch_store_b32 off, v0, s32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) @@ -968,6 +995,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) { ; DAGISEL64-NEXT: s_xor_saveexec_b64 vcc, -1 ; DAGISEL64-NEXT: s_clause 0x1 ; DAGISEL64-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; DAGISEL64-NEXT: s_mov_b64 exec, -1 ; DAGISEL64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) @@ -998,6 +1026,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) { ; GISEL64-NEXT: s_xor_saveexec_b64 vcc, -1 ; GISEL64-NEXT: s_clause 0x1 ; GISEL64-NEXT: scratch_store_b32 off, v0, s32 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; GISEL64-NEXT: s_mov_b64 exec, -1 ; GISEL64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) @@ -1025,6 +1054,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x1 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 @@ -1069,8 +1099,11 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) { ; DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; DAGISEL-NEXT: s_clause 0x3 ; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: s_wait_alu 0xfffe @@ -1099,8 +1132,11 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) { ; GISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GISEL-NEXT: s_clause 0x3 ; GISEL-NEXT: scratch_store_b32 off, v0, s32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: s_wait_alu 0xfffe @@ -1129,8 +1165,11 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) { ; DAGISEL64-NEXT: s_xor_saveexec_b64 vcc, -1 ; DAGISEL64-NEXT: s_clause 0x3 ; DAGISEL64-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v3, s32 offset:12 ; DAGISEL64-NEXT: s_mov_b64 exec, -1 ; DAGISEL64-NEXT: s_wait_alu 0xfffe @@ -1161,8 +1200,11 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) { ; GISEL64-NEXT: s_xor_saveexec_b64 vcc, -1 ; GISEL64-NEXT: s_clause 0x3 ; GISEL64-NEXT: scratch_store_b32 off, v0, s32 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v3, s32 offset:12 ; GISEL64-NEXT: s_mov_b64 exec, -1 ; GISEL64-NEXT: s_wait_alu 0xfffe @@ -1190,8 +1232,11 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) { ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 @@ -1227,10 +1272,15 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i ; DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; DAGISEL-NEXT: s_clause 0x5 ; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s9 @@ -1263,10 +1313,15 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i ; GISEL-NEXT: s_xor_saveexec_b32 s34, -1 ; GISEL-NEXT: s_clause 0x5 ; GISEL-NEXT: scratch_store_b32 off, v0, s32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: s_mov_b32 s0, s5 @@ -1304,10 +1359,15 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i ; DAGISEL64-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; DAGISEL64-NEXT: s_clause 0x5 ; DAGISEL64-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v5, s32 offset:20 ; DAGISEL64-NEXT: s_mov_b64 exec, -1 ; DAGISEL64-NEXT: v_mov_b32_e32 v4, s4 @@ -1343,10 +1403,15 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i ; GISEL64-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GISEL64-NEXT: s_clause 0x5 ; GISEL64-NEXT: scratch_store_b32 off, v0, s32 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v5, s32 offset:20 ; GISEL64-NEXT: s_mov_b64 exec, -1 ; GISEL64-NEXT: s_mov_b32 s0, s5 @@ -1383,10 +1448,15 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x5 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 @@ -1431,170 +1501,308 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 ; DAGISEL-NEXT: s_xor_saveexec_b32 s4, -1 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:164 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:168 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:172 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:176 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:180 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:184 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:188 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:192 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:196 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:200 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:204 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:208 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:212 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:216 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:220 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:224 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:228 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:232 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:236 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:240 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:244 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:248 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:252 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:256 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:260 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:264 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:268 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:272 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:276 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:280 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:284 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:288 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:292 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:296 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:300 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:304 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:308 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:312 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:316 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:320 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:324 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:328 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:332 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:336 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:340 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:344 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:348 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:352 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:356 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:360 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:364 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:368 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:372 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:376 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:380 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:384 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:388 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:392 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:396 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:400 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:404 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:408 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:412 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:416 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:420 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:424 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:428 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:432 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:436 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:440 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:444 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:448 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:452 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:456 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:460 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:464 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:468 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:472 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:476 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:480 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:484 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:488 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:492 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:496 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:500 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:504 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:508 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:512 ; DAGISEL-NEXT: s_clause 0xf ; DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:516 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:520 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:524 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:528 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:532 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:536 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:540 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:544 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:548 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:552 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:556 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:560 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:564 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:568 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:572 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:576 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; DAGISEL-NEXT: s_wait_alu 0xfffe ; DAGISEL-NEXT: v_writelane_b32 v40, s0, 3 +; DAGISEL-NEXT: s_addk_co_i32 s32, 0x250 +; DAGISEL-NEXT: v_writelane_b32 v40, s4, 0 +; DAGISEL-NEXT: v_writelane_b32 v40, s30, 1 +; DAGISEL-NEXT: v_writelane_b32 v40, s31, 2 ; DAGISEL-NEXT: v_mov_b32_e32 v2, v0 ; DAGISEL-NEXT: v_swap_b32 v0, v1 ; DAGISEL-NEXT: s_mov_b32 s1, gfx_callee@abs32@hi -; DAGISEL-NEXT: v_writelane_b32 v40, s4, 0 ; DAGISEL-NEXT: s_mov_b32 s0, gfx_callee@abs32@lo -; DAGISEL-NEXT: s_addk_co_i32 s32, 0x250 -; DAGISEL-NEXT: v_writelane_b32 v40, s30, 1 -; DAGISEL-NEXT: v_writelane_b32 v40, s31, 2 ; DAGISEL-NEXT: s_wait_alu 0xfffe ; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] -; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; DAGISEL-NEXT: v_readlane_b32 s31, v40, 2 ; DAGISEL-NEXT: v_readlane_b32 s30, v40, 1 +; DAGISEL-NEXT: v_readlane_b32 s31, v40, 2 ; DAGISEL-NEXT: v_readlane_b32 s4, v40, 0 ; DAGISEL-NEXT: v_readlane_b32 s0, v40, 3 ; DAGISEL-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload @@ -1767,170 +1975,308 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 ; GISEL-NEXT: s_xor_saveexec_b32 s4, -1 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v48, s33 offset:164 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v49, s33 offset:168 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v50, s33 offset:172 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v51, s33 offset:176 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v52, s33 offset:180 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v53, s33 offset:184 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v54, s33 offset:188 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v55, s33 offset:192 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v64, s33 offset:196 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v65, s33 offset:200 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v66, s33 offset:204 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v67, s33 offset:208 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v68, s33 offset:212 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v69, s33 offset:216 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v70, s33 offset:220 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v71, s33 offset:224 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v80, s33 offset:228 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v81, s33 offset:232 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v82, s33 offset:236 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v83, s33 offset:240 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v84, s33 offset:244 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v85, s33 offset:248 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v86, s33 offset:252 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v87, s33 offset:256 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v96, s33 offset:260 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v97, s33 offset:264 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v98, s33 offset:268 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v99, s33 offset:272 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v100, s33 offset:276 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v101, s33 offset:280 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v102, s33 offset:284 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v103, s33 offset:288 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v112, s33 offset:292 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v113, s33 offset:296 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v114, s33 offset:300 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v115, s33 offset:304 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v116, s33 offset:308 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v117, s33 offset:312 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v118, s33 offset:316 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v119, s33 offset:320 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v128, s33 offset:324 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v129, s33 offset:328 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v130, s33 offset:332 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v131, s33 offset:336 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v132, s33 offset:340 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v133, s33 offset:344 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v134, s33 offset:348 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v135, s33 offset:352 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v144, s33 offset:356 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v145, s33 offset:360 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v146, s33 offset:364 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v147, s33 offset:368 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v148, s33 offset:372 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v149, s33 offset:376 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v150, s33 offset:380 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v151, s33 offset:384 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v160, s33 offset:388 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v161, s33 offset:392 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v162, s33 offset:396 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v163, s33 offset:400 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v164, s33 offset:404 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v165, s33 offset:408 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v166, s33 offset:412 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v167, s33 offset:416 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v176, s33 offset:420 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v177, s33 offset:424 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v178, s33 offset:428 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v179, s33 offset:432 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v180, s33 offset:436 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v181, s33 offset:440 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v182, s33 offset:444 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v183, s33 offset:448 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v192, s33 offset:452 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v193, s33 offset:456 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v194, s33 offset:460 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v195, s33 offset:464 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v196, s33 offset:468 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v197, s33 offset:472 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v198, s33 offset:476 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v199, s33 offset:480 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v208, s33 offset:484 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v209, s33 offset:488 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v210, s33 offset:492 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v211, s33 offset:496 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v212, s33 offset:500 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v213, s33 offset:504 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v214, s33 offset:508 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v215, s33 offset:512 ; GISEL-NEXT: s_clause 0xf ; GISEL-NEXT: scratch_store_b32 off, v224, s33 offset:516 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v225, s33 offset:520 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v226, s33 offset:524 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v227, s33 offset:528 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v228, s33 offset:532 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v229, s33 offset:536 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v230, s33 offset:540 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v231, s33 offset:544 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v240, s33 offset:548 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v241, s33 offset:552 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v242, s33 offset:556 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v243, s33 offset:560 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v244, s33 offset:564 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v245, s33 offset:568 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v246, s33 offset:572 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v247, s33 offset:576 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GISEL-NEXT: s_wait_alu 0xfffe ; GISEL-NEXT: v_writelane_b32 v40, s0, 3 +; GISEL-NEXT: s_addk_co_i32 s32, 0x250 +; GISEL-NEXT: v_writelane_b32 v40, s4, 0 +; GISEL-NEXT: v_writelane_b32 v40, s30, 1 +; GISEL-NEXT: v_writelane_b32 v40, s31, 2 ; GISEL-NEXT: v_mov_b32_e32 v2, v0 ; GISEL-NEXT: v_swap_b32 v0, v1 ; GISEL-NEXT: s_mov_b32 s0, gfx_callee@abs32@lo -; GISEL-NEXT: v_writelane_b32 v40, s4, 0 ; GISEL-NEXT: s_mov_b32 s1, gfx_callee@abs32@hi -; GISEL-NEXT: s_addk_co_i32 s32, 0x250 -; GISEL-NEXT: v_writelane_b32 v40, s30, 1 -; GISEL-NEXT: v_writelane_b32 v40, s31, 2 ; GISEL-NEXT: s_wait_alu 0xfffe ; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GISEL-NEXT: v_readlane_b32 s31, v40, 2 ; GISEL-NEXT: v_readlane_b32 s30, v40, 1 +; GISEL-NEXT: v_readlane_b32 s31, v40, 2 ; GISEL-NEXT: v_readlane_b32 s4, v40, 0 ; GISEL-NEXT: v_readlane_b32 s0, v40, 3 ; GISEL-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload @@ -2103,171 +2449,309 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 ; DAGISEL64-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v0, s33 offset:4 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v1, s33 offset:8 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v2, s33 offset:12 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v3, s33 offset:16 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v4, s33 offset:20 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v5, s33 offset:24 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v6, s33 offset:28 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v7, s33 offset:32 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v8, s33 offset:36 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v9, s33 offset:40 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v10, s33 offset:44 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v11, s33 offset:48 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v12, s33 offset:52 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v13, s33 offset:56 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v14, s33 offset:60 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v15, s33 offset:64 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v16, s33 offset:68 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v17, s33 offset:72 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v18, s33 offset:76 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v19, s33 offset:80 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v20, s33 offset:84 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v21, s33 offset:88 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v22, s33 offset:92 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v23, s33 offset:96 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v24, s33 offset:100 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v25, s33 offset:104 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v26, s33 offset:108 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v27, s33 offset:112 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v28, s33 offset:116 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v29, s33 offset:120 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v30, s33 offset:124 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v31, s33 offset:128 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v32, s33 offset:132 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v33, s33 offset:136 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v34, s33 offset:140 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v35, s33 offset:144 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v36, s33 offset:148 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v37, s33 offset:152 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v38, s33 offset:156 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v39, s33 offset:160 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v48, s33 offset:164 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v49, s33 offset:168 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v50, s33 offset:172 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v51, s33 offset:176 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v52, s33 offset:180 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v53, s33 offset:184 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v54, s33 offset:188 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v55, s33 offset:192 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v64, s33 offset:196 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v65, s33 offset:200 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v66, s33 offset:204 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v67, s33 offset:208 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v68, s33 offset:212 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v69, s33 offset:216 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v70, s33 offset:220 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v71, s33 offset:224 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v80, s33 offset:228 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v81, s33 offset:232 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v82, s33 offset:236 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v83, s33 offset:240 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v84, s33 offset:244 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v85, s33 offset:248 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v86, s33 offset:252 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v87, s33 offset:256 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v96, s33 offset:260 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v97, s33 offset:264 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v98, s33 offset:268 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v99, s33 offset:272 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v100, s33 offset:276 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v101, s33 offset:280 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v102, s33 offset:284 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v103, s33 offset:288 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v112, s33 offset:292 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v113, s33 offset:296 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v114, s33 offset:300 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v115, s33 offset:304 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v116, s33 offset:308 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v117, s33 offset:312 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v118, s33 offset:316 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v119, s33 offset:320 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v128, s33 offset:324 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v129, s33 offset:328 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v130, s33 offset:332 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v131, s33 offset:336 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v132, s33 offset:340 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v133, s33 offset:344 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v134, s33 offset:348 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v135, s33 offset:352 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v144, s33 offset:356 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v145, s33 offset:360 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v146, s33 offset:364 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v147, s33 offset:368 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v148, s33 offset:372 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v149, s33 offset:376 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v150, s33 offset:380 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v151, s33 offset:384 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v160, s33 offset:388 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v161, s33 offset:392 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v162, s33 offset:396 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v163, s33 offset:400 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v164, s33 offset:404 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v165, s33 offset:408 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v166, s33 offset:412 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v167, s33 offset:416 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v176, s33 offset:420 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v177, s33 offset:424 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v178, s33 offset:428 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v179, s33 offset:432 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v180, s33 offset:436 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v181, s33 offset:440 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v182, s33 offset:444 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v183, s33 offset:448 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v192, s33 offset:452 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v193, s33 offset:456 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v194, s33 offset:460 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v195, s33 offset:464 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v196, s33 offset:468 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v197, s33 offset:472 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v198, s33 offset:476 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v199, s33 offset:480 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v208, s33 offset:484 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v209, s33 offset:488 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v210, s33 offset:492 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v211, s33 offset:496 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v212, s33 offset:500 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v213, s33 offset:504 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v214, s33 offset:508 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v215, s33 offset:512 ; DAGISEL64-NEXT: s_clause 0xf ; DAGISEL64-NEXT: scratch_store_b32 off, v224, s33 offset:516 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v225, s33 offset:520 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v226, s33 offset:524 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v227, s33 offset:528 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v228, s33 offset:532 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v229, s33 offset:536 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v230, s33 offset:540 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v231, s33 offset:544 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v240, s33 offset:548 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v241, s33 offset:552 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v242, s33 offset:556 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v243, s33 offset:560 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v244, s33 offset:564 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v245, s33 offset:568 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v246, s33 offset:572 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v247, s33 offset:576 ; DAGISEL64-NEXT: s_mov_b64 exec, -1 ; DAGISEL64-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; DAGISEL64-NEXT: s_wait_alu 0xfffe ; DAGISEL64-NEXT: v_writelane_b32 v40, s0, 4 -; DAGISEL64-NEXT: v_mov_b32_e32 v2, v0 -; DAGISEL64-NEXT: v_swap_b32 v0, v1 -; DAGISEL64-NEXT: s_mov_b32 s1, gfx_callee@abs32@hi -; DAGISEL64-NEXT: v_writelane_b32 v40, s4, 0 -; DAGISEL64-NEXT: s_mov_b32 s0, gfx_callee@abs32@lo ; DAGISEL64-NEXT: s_addk_co_i32 s32, 0x250 +; DAGISEL64-NEXT: v_writelane_b32 v40, s4, 0 ; DAGISEL64-NEXT: v_writelane_b32 v40, s5, 1 ; DAGISEL64-NEXT: v_writelane_b32 v40, s30, 2 ; DAGISEL64-NEXT: v_writelane_b32 v40, s31, 3 +; DAGISEL64-NEXT: v_mov_b32_e32 v2, v0 +; DAGISEL64-NEXT: v_swap_b32 v0, v1 +; DAGISEL64-NEXT: s_mov_b32 s1, gfx_callee@abs32@hi +; DAGISEL64-NEXT: s_mov_b32 s0, gfx_callee@abs32@lo ; DAGISEL64-NEXT: s_wait_alu 0xfffe ; DAGISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1] -; DAGISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1) -; DAGISEL64-NEXT: v_readlane_b32 s31, v40, 3 ; DAGISEL64-NEXT: v_readlane_b32 s30, v40, 2 +; DAGISEL64-NEXT: v_readlane_b32 s31, v40, 3 ; DAGISEL64-NEXT: v_readlane_b32 s5, v40, 1 ; DAGISEL64-NEXT: v_readlane_b32 s4, v40, 0 ; DAGISEL64-NEXT: v_readlane_b32 s0, v40, 4 @@ -2441,171 +2925,309 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 ; GISEL64-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v0, s33 offset:4 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v1, s33 offset:8 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v2, s33 offset:12 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v3, s33 offset:16 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v4, s33 offset:20 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v5, s33 offset:24 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v6, s33 offset:28 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v7, s33 offset:32 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v8, s33 offset:36 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v9, s33 offset:40 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v10, s33 offset:44 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v11, s33 offset:48 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v12, s33 offset:52 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v13, s33 offset:56 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v14, s33 offset:60 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v15, s33 offset:64 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v16, s33 offset:68 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v17, s33 offset:72 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v18, s33 offset:76 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v19, s33 offset:80 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v20, s33 offset:84 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v21, s33 offset:88 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v22, s33 offset:92 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v23, s33 offset:96 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v24, s33 offset:100 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v25, s33 offset:104 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v26, s33 offset:108 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v27, s33 offset:112 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v28, s33 offset:116 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v29, s33 offset:120 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v30, s33 offset:124 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v31, s33 offset:128 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v32, s33 offset:132 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v33, s33 offset:136 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v34, s33 offset:140 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v35, s33 offset:144 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v36, s33 offset:148 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v37, s33 offset:152 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v38, s33 offset:156 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v39, s33 offset:160 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v48, s33 offset:164 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v49, s33 offset:168 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v50, s33 offset:172 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v51, s33 offset:176 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v52, s33 offset:180 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v53, s33 offset:184 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v54, s33 offset:188 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v55, s33 offset:192 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v64, s33 offset:196 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v65, s33 offset:200 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v66, s33 offset:204 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v67, s33 offset:208 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v68, s33 offset:212 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v69, s33 offset:216 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v70, s33 offset:220 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v71, s33 offset:224 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v80, s33 offset:228 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v81, s33 offset:232 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v82, s33 offset:236 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v83, s33 offset:240 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v84, s33 offset:244 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v85, s33 offset:248 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v86, s33 offset:252 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v87, s33 offset:256 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v96, s33 offset:260 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v97, s33 offset:264 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v98, s33 offset:268 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v99, s33 offset:272 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v100, s33 offset:276 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v101, s33 offset:280 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v102, s33 offset:284 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v103, s33 offset:288 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v112, s33 offset:292 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v113, s33 offset:296 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v114, s33 offset:300 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v115, s33 offset:304 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v116, s33 offset:308 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v117, s33 offset:312 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v118, s33 offset:316 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v119, s33 offset:320 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v128, s33 offset:324 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v129, s33 offset:328 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v130, s33 offset:332 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v131, s33 offset:336 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v132, s33 offset:340 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v133, s33 offset:344 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v134, s33 offset:348 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v135, s33 offset:352 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v144, s33 offset:356 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v145, s33 offset:360 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v146, s33 offset:364 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v147, s33 offset:368 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v148, s33 offset:372 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v149, s33 offset:376 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v150, s33 offset:380 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v151, s33 offset:384 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v160, s33 offset:388 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v161, s33 offset:392 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v162, s33 offset:396 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v163, s33 offset:400 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v164, s33 offset:404 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v165, s33 offset:408 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v166, s33 offset:412 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v167, s33 offset:416 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v176, s33 offset:420 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v177, s33 offset:424 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v178, s33 offset:428 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v179, s33 offset:432 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v180, s33 offset:436 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v181, s33 offset:440 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v182, s33 offset:444 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v183, s33 offset:448 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v192, s33 offset:452 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v193, s33 offset:456 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v194, s33 offset:460 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v195, s33 offset:464 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v196, s33 offset:468 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v197, s33 offset:472 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v198, s33 offset:476 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v199, s33 offset:480 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v208, s33 offset:484 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v209, s33 offset:488 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v210, s33 offset:492 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v211, s33 offset:496 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v212, s33 offset:500 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v213, s33 offset:504 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v214, s33 offset:508 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v215, s33 offset:512 ; GISEL64-NEXT: s_clause 0xf ; GISEL64-NEXT: scratch_store_b32 off, v224, s33 offset:516 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v225, s33 offset:520 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v226, s33 offset:524 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v227, s33 offset:528 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v228, s33 offset:532 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v229, s33 offset:536 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v230, s33 offset:540 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v231, s33 offset:544 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v240, s33 offset:548 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v241, s33 offset:552 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v242, s33 offset:556 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v243, s33 offset:560 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v244, s33 offset:564 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v245, s33 offset:568 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v246, s33 offset:572 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v247, s33 offset:576 ; GISEL64-NEXT: s_mov_b64 exec, -1 ; GISEL64-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GISEL64-NEXT: s_wait_alu 0xfffe ; GISEL64-NEXT: v_writelane_b32 v40, s0, 4 -; GISEL64-NEXT: v_mov_b32_e32 v2, v0 -; GISEL64-NEXT: v_swap_b32 v0, v1 -; GISEL64-NEXT: s_mov_b32 s0, gfx_callee@abs32@lo -; GISEL64-NEXT: v_writelane_b32 v40, s4, 0 -; GISEL64-NEXT: s_mov_b32 s1, gfx_callee@abs32@hi ; GISEL64-NEXT: s_addk_co_i32 s32, 0x250 +; GISEL64-NEXT: v_writelane_b32 v40, s4, 0 ; GISEL64-NEXT: v_writelane_b32 v40, s5, 1 ; GISEL64-NEXT: v_writelane_b32 v40, s30, 2 ; GISEL64-NEXT: v_writelane_b32 v40, s31, 3 +; GISEL64-NEXT: v_mov_b32_e32 v2, v0 +; GISEL64-NEXT: v_swap_b32 v0, v1 +; GISEL64-NEXT: s_mov_b32 s0, gfx_callee@abs32@lo +; GISEL64-NEXT: s_mov_b32 s1, gfx_callee@abs32@hi ; GISEL64-NEXT: s_wait_alu 0xfffe ; GISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GISEL64-NEXT: v_readlane_b32 s31, v40, 3 ; GISEL64-NEXT: v_readlane_b32 s30, v40, 2 +; GISEL64-NEXT: v_readlane_b32 s31, v40, 3 ; GISEL64-NEXT: v_readlane_b32 s5, v40, 1 ; GISEL64-NEXT: v_readlane_b32 s4, v40, 0 ; GISEL64-NEXT: v_readlane_b32 s0, v40, 4 @@ -2776,933 +3398,1830 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:252 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:260 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:268 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:276 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:504 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:512 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:520 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:528 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 4 ; msbs: dst=0 src0=0 src1=1 src2=0 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s33 offset:580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s33 offset:584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s33 offset:588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s33 offset:592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s33 offset:596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s33 offset:600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s33 offset:604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s33 offset:608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s33 offset:612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s33 offset:616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s33 offset:620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s33 offset:624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s33 offset:628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s33 offset:632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s33 offset:636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s33 offset:640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s33 offset:644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s33 offset:648 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s33 offset:652 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s33 offset:656 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s33 offset:660 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s33 offset:664 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s33 offset:668 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s33 offset:672 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s33 offset:676 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s33 offset:680 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s33 offset:684 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s33 offset:688 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s33 offset:692 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s33 offset:696 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s33 offset:700 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s33 offset:704 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s33 offset:708 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s33 offset:712 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s33 offset:716 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s33 offset:720 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s33 offset:724 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s33 offset:728 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s33 offset:732 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s33 offset:736 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s33 offset:740 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s33 offset:744 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s33 offset:748 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s33 offset:752 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s33 offset:756 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s33 offset:760 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s33 offset:764 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s33 offset:768 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s33 offset:772 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s33 offset:776 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s33 offset:780 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s33 offset:784 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s33 offset:788 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s33 offset:792 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s33 offset:796 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s33 offset:800 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s33 offset:804 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s33 offset:808 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s33 offset:812 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s33 offset:816 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s33 offset:820 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s33 offset:824 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s33 offset:828 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s33 offset:832 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s33 offset:836 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s33 offset:840 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s33 offset:844 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s33 offset:848 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s33 offset:852 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s33 offset:856 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s33 offset:860 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s33 offset:864 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s33 offset:868 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s33 offset:872 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s33 offset:876 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s33 offset:880 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s33 offset:884 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s33 offset:888 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s33 offset:892 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s33 offset:896 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s33 offset:900 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s33 offset:904 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s33 offset:908 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s33 offset:912 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s33 offset:916 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s33 offset:920 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s33 offset:924 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s33 offset:928 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s33 offset:932 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s33 offset:936 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s33 offset:940 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s33 offset:944 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s33 offset:948 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s33 offset:952 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s33 offset:956 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s33 offset:960 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s33 offset:964 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s33 offset:968 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s33 offset:972 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s33 offset:976 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s33 offset:980 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s33 offset:984 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s33 offset:988 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s33 offset:992 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s33 offset:996 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s33 offset:1000 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s33 offset:1004 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s33 offset:1008 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s33 offset:1012 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s33 offset:1016 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s33 offset:1020 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s33 offset:1024 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s33 offset:1028 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s33 offset:1032 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s33 offset:1036 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s33 offset:1040 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s33 offset:1044 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s33 offset:1048 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s33 offset:1052 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s33 offset:1056 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s33 offset:1060 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s33 offset:1064 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s33 offset:1068 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s33 offset:1072 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s33 offset:1076 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s33 offset:1080 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s33 offset:1084 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s33 offset:1088 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s33 offset:1092 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s33 offset:1096 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s33 offset:1100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s33 offset:1104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s33 offset:1108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s33 offset:1112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s33 offset:1116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s33 offset:1120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s33 offset:1124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s33 offset:1128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s33 offset:1132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s33 offset:1136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s33 offset:1140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s33 offset:1144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s33 offset:1148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s33 offset:1152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s33 offset:1156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s33 offset:1160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s33 offset:1164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s33 offset:1168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s33 offset:1172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s33 offset:1176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s33 offset:1180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s33 offset:1184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s33 offset:1188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s33 offset:1192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s33 offset:1196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s33 offset:1200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s33 offset:1204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s33 offset:1208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s33 offset:1212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s33 offset:1216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s33 offset:1220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s33 offset:1224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s33 offset:1228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s33 offset:1232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s33 offset:1236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s33 offset:1240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s33 offset:1244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s33 offset:1248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s33 offset:1252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s33 offset:1256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s33 offset:1260 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s33 offset:1264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s33 offset:1268 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s33 offset:1272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s33 offset:1276 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s33 offset:1280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s33 offset:1284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s33 offset:1288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s33 offset:1292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s33 offset:1296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s33 offset:1300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s33 offset:1304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s33 offset:1308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s33 offset:1312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s33 offset:1316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s33 offset:1320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s33 offset:1324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s33 offset:1328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s33 offset:1332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s33 offset:1336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s33 offset:1340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s33 offset:1344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s33 offset:1348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s33 offset:1352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s33 offset:1356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s33 offset:1360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s33 offset:1364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s33 offset:1368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s33 offset:1372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s33 offset:1376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s33 offset:1380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s33 offset:1384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s33 offset:1388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s33 offset:1392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s33 offset:1396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s33 offset:1400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s33 offset:1404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s33 offset:1408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s33 offset:1412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s33 offset:1416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s33 offset:1420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s33 offset:1424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s33 offset:1428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s33 offset:1432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s33 offset:1436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s33 offset:1440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s33 offset:1444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s33 offset:1448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s33 offset:1452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s33 offset:1456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s33 offset:1460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s33 offset:1464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s33 offset:1468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s33 offset:1472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s33 offset:1476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s33 offset:1480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s33 offset:1484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s33 offset:1488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s33 offset:1492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s33 offset:1496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s33 offset:1500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s33 offset:1504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s33 offset:1508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s33 offset:1512 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s33 offset:1516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s33 offset:1520 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s33 offset:1524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s33 offset:1528 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s33 offset:1532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s33 offset:1536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s33 offset:1540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s33 offset:1544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s33 offset:1548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s33 offset:1552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s33 offset:1556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s33 offset:1560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s33 offset:1564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s33 offset:1568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s33 offset:1572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s33 offset:1576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s33 offset:1580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s33 offset:1584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s33 offset:1588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s33 offset:1592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s33 offset:1596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s33 offset:1600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 8 ; msbs: dst=0 src0=0 src1=2 src2=0 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s33 offset:1604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s33 offset:1608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s33 offset:1612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s33 offset:1616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s33 offset:1620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s33 offset:1624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s33 offset:1628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s33 offset:1632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s33 offset:1636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s33 offset:1640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s33 offset:1644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s33 offset:1648 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s33 offset:1652 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s33 offset:1656 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s33 offset:1660 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s33 offset:1664 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s33 offset:1668 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s33 offset:1672 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s33 offset:1676 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s33 offset:1680 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s33 offset:1684 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s33 offset:1688 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s33 offset:1692 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s33 offset:1696 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s33 offset:1700 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s33 offset:1704 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s33 offset:1708 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s33 offset:1712 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s33 offset:1716 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s33 offset:1720 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s33 offset:1724 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s33 offset:1728 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s33 offset:1732 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s33 offset:1736 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s33 offset:1740 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s33 offset:1744 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s33 offset:1748 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s33 offset:1752 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s33 offset:1756 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s33 offset:1760 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s33 offset:1764 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s33 offset:1768 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s33 offset:1772 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s33 offset:1776 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s33 offset:1780 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s33 offset:1784 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s33 offset:1788 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s33 offset:1792 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s33 offset:1796 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s33 offset:1800 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s33 offset:1804 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s33 offset:1808 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s33 offset:1812 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s33 offset:1816 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s33 offset:1820 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s33 offset:1824 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s33 offset:1828 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s33 offset:1832 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s33 offset:1836 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s33 offset:1840 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s33 offset:1844 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s33 offset:1848 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s33 offset:1852 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s33 offset:1856 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s33 offset:1860 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s33 offset:1864 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s33 offset:1868 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s33 offset:1872 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s33 offset:1876 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s33 offset:1880 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s33 offset:1884 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s33 offset:1888 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s33 offset:1892 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s33 offset:1896 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s33 offset:1900 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s33 offset:1904 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s33 offset:1908 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s33 offset:1912 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s33 offset:1916 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s33 offset:1920 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s33 offset:1924 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s33 offset:1928 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s33 offset:1932 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s33 offset:1936 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s33 offset:1940 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s33 offset:1944 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s33 offset:1948 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s33 offset:1952 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s33 offset:1956 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s33 offset:1960 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s33 offset:1964 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s33 offset:1968 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s33 offset:1972 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s33 offset:1976 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s33 offset:1980 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s33 offset:1984 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s33 offset:1988 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s33 offset:1992 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s33 offset:1996 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s33 offset:2000 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s33 offset:2004 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s33 offset:2008 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s33 offset:2012 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s33 offset:2016 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s33 offset:2020 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s33 offset:2024 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s33 offset:2028 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s33 offset:2032 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s33 offset:2036 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s33 offset:2040 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s33 offset:2044 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s33 offset:2048 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s33 offset:2052 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s33 offset:2056 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s33 offset:2060 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s33 offset:2064 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s33 offset:2068 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s33 offset:2072 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s33 offset:2076 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s33 offset:2080 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s33 offset:2084 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s33 offset:2088 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s33 offset:2092 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s33 offset:2096 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s33 offset:2100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s33 offset:2104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s33 offset:2108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s33 offset:2112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s33 offset:2116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s33 offset:2120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s33 offset:2124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s33 offset:2128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s33 offset:2132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s33 offset:2136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s33 offset:2140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s33 offset:2144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s33 offset:2148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s33 offset:2152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s33 offset:2156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s33 offset:2160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s33 offset:2164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s33 offset:2168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s33 offset:2172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s33 offset:2176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s33 offset:2180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s33 offset:2184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s33 offset:2188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s33 offset:2192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s33 offset:2196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s33 offset:2200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s33 offset:2204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s33 offset:2208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s33 offset:2212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s33 offset:2216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s33 offset:2220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s33 offset:2224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s33 offset:2228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s33 offset:2232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s33 offset:2236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s33 offset:2240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s33 offset:2244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s33 offset:2248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s33 offset:2252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s33 offset:2256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s33 offset:2260 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s33 offset:2264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s33 offset:2268 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s33 offset:2272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s33 offset:2276 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s33 offset:2280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s33 offset:2284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s33 offset:2288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s33 offset:2292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s33 offset:2296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s33 offset:2300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s33 offset:2304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s33 offset:2308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s33 offset:2312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s33 offset:2316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s33 offset:2320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s33 offset:2324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s33 offset:2328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s33 offset:2332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s33 offset:2336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s33 offset:2340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s33 offset:2344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s33 offset:2348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s33 offset:2352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s33 offset:2356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s33 offset:2360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s33 offset:2364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s33 offset:2368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s33 offset:2372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s33 offset:2376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s33 offset:2380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s33 offset:2384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s33 offset:2388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s33 offset:2392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s33 offset:2396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s33 offset:2400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s33 offset:2404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s33 offset:2408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s33 offset:2412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s33 offset:2416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s33 offset:2420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s33 offset:2424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s33 offset:2428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s33 offset:2432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s33 offset:2436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s33 offset:2440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s33 offset:2444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s33 offset:2448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s33 offset:2452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s33 offset:2456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s33 offset:2460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s33 offset:2464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s33 offset:2468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s33 offset:2472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s33 offset:2476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s33 offset:2480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s33 offset:2484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s33 offset:2488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s33 offset:2492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s33 offset:2496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s33 offset:2500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s33 offset:2504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s33 offset:2508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s33 offset:2512 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s33 offset:2516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s33 offset:2520 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s33 offset:2524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s33 offset:2528 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s33 offset:2532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s33 offset:2536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s33 offset:2540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s33 offset:2544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s33 offset:2548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s33 offset:2552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s33 offset:2556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s33 offset:2560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s33 offset:2564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s33 offset:2568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s33 offset:2572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s33 offset:2576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s33 offset:2580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s33 offset:2584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s33 offset:2588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s33 offset:2592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s33 offset:2596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s33 offset:2600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s33 offset:2604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s33 offset:2608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s33 offset:2612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s33 offset:2616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s33 offset:2620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s33 offset:2624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 12 ; msbs: dst=0 src0=0 src1=3 src2=0 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s33 offset:2628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s33 offset:2632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s33 offset:2636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s33 offset:2640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s33 offset:2644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s33 offset:2648 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s33 offset:2652 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s33 offset:2656 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s33 offset:2660 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s33 offset:2664 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s33 offset:2668 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s33 offset:2672 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s33 offset:2676 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s33 offset:2680 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s33 offset:2684 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s33 offset:2688 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s33 offset:2692 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s33 offset:2696 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s33 offset:2700 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s33 offset:2704 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s33 offset:2708 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s33 offset:2712 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s33 offset:2716 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s33 offset:2720 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s33 offset:2724 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s33 offset:2728 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s33 offset:2732 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s33 offset:2736 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s33 offset:2740 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s33 offset:2744 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s33 offset:2748 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s33 offset:2752 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s33 offset:2756 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s33 offset:2760 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s33 offset:2764 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s33 offset:2768 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s33 offset:2772 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s33 offset:2776 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s33 offset:2780 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s33 offset:2784 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s33 offset:2788 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s33 offset:2792 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s33 offset:2796 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s33 offset:2800 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s33 offset:2804 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s33 offset:2808 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s33 offset:2812 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s33 offset:2816 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s33 offset:2820 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s33 offset:2824 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s33 offset:2828 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s33 offset:2832 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s33 offset:2836 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s33 offset:2840 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s33 offset:2844 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s33 offset:2848 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s33 offset:2852 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s33 offset:2856 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s33 offset:2860 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s33 offset:2864 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s33 offset:2868 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s33 offset:2872 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s33 offset:2876 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s33 offset:2880 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s33 offset:2884 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s33 offset:2888 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s33 offset:2892 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s33 offset:2896 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s33 offset:2900 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s33 offset:2904 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s33 offset:2908 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s33 offset:2912 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s33 offset:2916 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s33 offset:2920 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s33 offset:2924 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s33 offset:2928 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s33 offset:2932 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s33 offset:2936 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s33 offset:2940 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s33 offset:2944 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s33 offset:2948 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s33 offset:2952 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s33 offset:2956 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s33 offset:2960 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s33 offset:2964 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s33 offset:2968 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s33 offset:2972 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s33 offset:2976 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s33 offset:2980 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s33 offset:2984 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s33 offset:2988 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s33 offset:2992 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s33 offset:2996 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s33 offset:3000 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s33 offset:3004 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s33 offset:3008 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s33 offset:3012 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s33 offset:3016 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s33 offset:3020 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s33 offset:3024 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s33 offset:3028 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s33 offset:3032 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s33 offset:3036 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s33 offset:3040 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s33 offset:3044 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s33 offset:3048 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s33 offset:3052 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s33 offset:3056 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s33 offset:3060 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s33 offset:3064 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s33 offset:3068 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s33 offset:3072 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s33 offset:3076 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s33 offset:3080 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s33 offset:3084 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s33 offset:3088 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s33 offset:3092 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s33 offset:3096 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s33 offset:3100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s33 offset:3104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s33 offset:3108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s33 offset:3112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s33 offset:3116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s33 offset:3120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s33 offset:3124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s33 offset:3128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s33 offset:3132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s33 offset:3136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s33 offset:3140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s33 offset:3144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s33 offset:3148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s33 offset:3152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s33 offset:3156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s33 offset:3160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s33 offset:3164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s33 offset:3168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s33 offset:3172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s33 offset:3176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s33 offset:3180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s33 offset:3184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s33 offset:3188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s33 offset:3192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s33 offset:3196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s33 offset:3200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s33 offset:3204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s33 offset:3208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s33 offset:3212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s33 offset:3216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s33 offset:3220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s33 offset:3224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s33 offset:3228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s33 offset:3232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s33 offset:3236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s33 offset:3240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s33 offset:3244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s33 offset:3248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s33 offset:3252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s33 offset:3256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s33 offset:3260 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s33 offset:3264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s33 offset:3268 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s33 offset:3272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s33 offset:3276 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s33 offset:3280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s33 offset:3284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s33 offset:3288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s33 offset:3292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s33 offset:3296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s33 offset:3300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s33 offset:3304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s33 offset:3308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s33 offset:3312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s33 offset:3316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s33 offset:3320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s33 offset:3324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s33 offset:3328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s33 offset:3332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s33 offset:3336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s33 offset:3340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s33 offset:3344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s33 offset:3348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s33 offset:3352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s33 offset:3356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s33 offset:3360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s33 offset:3364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s33 offset:3368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s33 offset:3372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s33 offset:3376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s33 offset:3380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s33 offset:3384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s33 offset:3388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s33 offset:3392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s33 offset:3396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s33 offset:3400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s33 offset:3404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s33 offset:3408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s33 offset:3412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s33 offset:3416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s33 offset:3420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s33 offset:3424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s33 offset:3428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s33 offset:3432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s33 offset:3436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s33 offset:3440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s33 offset:3444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s33 offset:3448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s33 offset:3452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s33 offset:3456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s33 offset:3460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s33 offset:3464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s33 offset:3468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s33 offset:3472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s33 offset:3476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s33 offset:3480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s33 offset:3484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s33 offset:3488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s33 offset:3492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s33 offset:3496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s33 offset:3500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s33 offset:3504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s33 offset:3508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s33 offset:3512 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s33 offset:3516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s33 offset:3520 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s33 offset:3524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s33 offset:3528 ; GFX1250-DAGISEL-NEXT: s_clause 0x1d ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s33 offset:3532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s33 offset:3536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s33 offset:3540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s33 offset:3544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s33 offset:3548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s33 offset:3552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s33 offset:3556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s33 offset:3560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s33 offset:3564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s33 offset:3568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s33 offset:3572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s33 offset:3576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s33 offset:3580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s33 offset:3584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s33 offset:3588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s33 offset:3592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s33 offset:3596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s33 offset:3600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s33 offset:3604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s33 offset:3608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s33 offset:3612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s33 offset:3616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s33 offset:3620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s33 offset:3624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s33 offset:3628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s33 offset:3632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s33 offset:3636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s33 offset:3640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s33 offset:3644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s33 offset:3648 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 @@ -3710,17 +5229,17 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s0, 3 -; GFX1250-DAGISEL-NEXT: v_mov_b32_e32 v2, v0 -; GFX1250-DAGISEL-NEXT: v_swap_b32 v0, v1 -; GFX1250-DAGISEL-NEXT: s_mov_b64 s[0:1], gfx_callee@abs64 -; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s4, 0 ; GFX1250-DAGISEL-NEXT: s_addk_co_i32 s32, 0xe50 +; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s4, 0 ; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s30, 1 ; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s31, 2 +; GFX1250-DAGISEL-NEXT: v_mov_b32_e32 v2, v0 +; GFX1250-DAGISEL-NEXT: v_swap_b32 v0, v1 +; GFX1250-DAGISEL-NEXT: s_mov_b64 s[0:1], gfx_callee@abs64 +; GFX1250-DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-DAGISEL-NEXT: s_swap_pc_i64 s[30:31], s[0:1] -; GFX1250-DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-DAGISEL-NEXT: v_readlane_b32 s31, v40, 2 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s30, v40, 1 +; GFX1250-DAGISEL-NEXT: v_readlane_b32 s31, v40, 2 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s4, v40, 0 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s0, v40, 3 ; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload @@ -4679,152 +6198,291 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ ; DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v6, s32 offset:24 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v7, s32 offset:28 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v8, s32 offset:32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v9, s32 offset:36 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v10, s32 offset:40 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v11, s32 offset:44 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v12, s32 offset:48 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v13, s32 offset:52 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v14, s32 offset:56 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v15, s32 offset:60 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v16, s32 offset:64 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v17, s32 offset:68 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v18, s32 offset:72 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v19, s32 offset:76 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v20, s32 offset:80 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v21, s32 offset:84 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v22, s32 offset:88 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v23, s32 offset:92 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v24, s32 offset:96 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v25, s32 offset:100 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v26, s32 offset:104 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v27, s32 offset:108 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v28, s32 offset:112 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v35, s32 offset:140 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v36, s32 offset:144 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v37, s32 offset:148 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v38, s32 offset:152 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v39, s32 offset:156 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v48, s32 offset:160 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:164 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v50, s32 offset:168 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v51, s32 offset:172 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v52, s32 offset:176 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v53, s32 offset:180 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v54, s32 offset:184 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v55, s32 offset:188 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v64, s32 offset:192 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v65, s32 offset:196 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v66, s32 offset:200 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v67, s32 offset:204 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v68, s32 offset:208 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v69, s32 offset:212 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v70, s32 offset:216 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v71, s32 offset:220 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v80, s32 offset:224 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v81, s32 offset:228 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v82, s32 offset:232 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v83, s32 offset:236 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v84, s32 offset:240 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v99, s32 offset:268 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v100, s32 offset:272 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v101, s32 offset:276 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v102, s32 offset:280 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v103, s32 offset:284 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v112, s32 offset:288 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v113, s32 offset:292 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v114, s32 offset:296 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v115, s32 offset:300 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v116, s32 offset:304 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v117, s32 offset:308 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v118, s32 offset:312 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v119, s32 offset:316 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v128, s32 offset:320 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v129, s32 offset:324 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v130, s32 offset:328 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v131, s32 offset:332 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v132, s32 offset:336 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v133, s32 offset:340 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v134, s32 offset:344 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v135, s32 offset:348 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v144, s32 offset:352 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v145, s32 offset:356 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v146, s32 offset:360 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v147, s32 offset:364 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v148, s32 offset:368 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v163, s32 offset:396 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v164, s32 offset:400 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v165, s32 offset:404 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v166, s32 offset:408 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v167, s32 offset:412 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v176, s32 offset:416 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v177, s32 offset:420 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v178, s32 offset:424 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v179, s32 offset:428 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v180, s32 offset:432 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v181, s32 offset:436 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v182, s32 offset:440 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v183, s32 offset:444 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v192, s32 offset:448 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v193, s32 offset:452 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v194, s32 offset:456 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v195, s32 offset:460 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v196, s32 offset:464 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v197, s32 offset:468 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v198, s32 offset:472 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v199, s32 offset:476 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v208, s32 offset:480 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v209, s32 offset:484 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v210, s32 offset:488 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v211, s32 offset:492 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v212, s32 offset:496 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508 ; DAGISEL-NEXT: s_clause 0xf ; DAGISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v227, s32 offset:524 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v228, s32 offset:528 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v229, s32 offset:532 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v230, s32 offset:536 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v231, s32 offset:540 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v240, s32 offset:544 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v241, s32 offset:548 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v242, s32 offset:552 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v243, s32 offset:556 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v244, s32 offset:560 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v245, s32 offset:564 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v246, s32 offset:568 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v247, s32 offset:572 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: v_mov_b32_e32 v2, v0 @@ -4995,152 +6653,291 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ ; GISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v0, s32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v6, s32 offset:24 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v7, s32 offset:28 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v8, s32 offset:32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v9, s32 offset:36 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v10, s32 offset:40 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v11, s32 offset:44 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v12, s32 offset:48 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v13, s32 offset:52 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v14, s32 offset:56 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v15, s32 offset:60 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v16, s32 offset:64 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v17, s32 offset:68 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v18, s32 offset:72 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v19, s32 offset:76 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v20, s32 offset:80 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v21, s32 offset:84 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v22, s32 offset:88 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v23, s32 offset:92 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v24, s32 offset:96 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v25, s32 offset:100 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v26, s32 offset:104 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v27, s32 offset:108 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v28, s32 offset:112 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v35, s32 offset:140 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v36, s32 offset:144 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v37, s32 offset:148 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v38, s32 offset:152 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v39, s32 offset:156 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v48, s32 offset:160 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v49, s32 offset:164 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v50, s32 offset:168 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v51, s32 offset:172 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v52, s32 offset:176 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v53, s32 offset:180 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v54, s32 offset:184 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v55, s32 offset:188 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v64, s32 offset:192 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v65, s32 offset:196 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v66, s32 offset:200 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v67, s32 offset:204 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v68, s32 offset:208 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v69, s32 offset:212 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v70, s32 offset:216 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v71, s32 offset:220 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v80, s32 offset:224 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v81, s32 offset:228 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v82, s32 offset:232 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v83, s32 offset:236 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v84, s32 offset:240 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v99, s32 offset:268 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v100, s32 offset:272 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v101, s32 offset:276 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v102, s32 offset:280 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v103, s32 offset:284 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v112, s32 offset:288 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v113, s32 offset:292 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v114, s32 offset:296 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v115, s32 offset:300 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v116, s32 offset:304 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v117, s32 offset:308 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v118, s32 offset:312 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v119, s32 offset:316 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v128, s32 offset:320 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v129, s32 offset:324 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v130, s32 offset:328 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v131, s32 offset:332 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v132, s32 offset:336 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v133, s32 offset:340 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v134, s32 offset:344 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v135, s32 offset:348 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v144, s32 offset:352 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v145, s32 offset:356 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v146, s32 offset:360 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v147, s32 offset:364 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v148, s32 offset:368 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v163, s32 offset:396 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v164, s32 offset:400 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v165, s32 offset:404 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v166, s32 offset:408 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v167, s32 offset:412 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v176, s32 offset:416 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v177, s32 offset:420 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v178, s32 offset:424 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v179, s32 offset:428 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v180, s32 offset:432 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v181, s32 offset:436 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v182, s32 offset:440 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v183, s32 offset:444 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v192, s32 offset:448 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v193, s32 offset:452 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v194, s32 offset:456 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v195, s32 offset:460 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v196, s32 offset:464 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v197, s32 offset:468 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v198, s32 offset:472 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v199, s32 offset:476 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v208, s32 offset:480 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v209, s32 offset:484 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v210, s32 offset:488 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v211, s32 offset:492 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v212, s32 offset:496 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508 ; GISEL-NEXT: s_clause 0xf ; GISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v227, s32 offset:524 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v228, s32 offset:528 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v229, s32 offset:532 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v230, s32 offset:536 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v231, s32 offset:540 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v240, s32 offset:544 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v241, s32 offset:548 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v242, s32 offset:552 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v243, s32 offset:556 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v244, s32 offset:560 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v245, s32 offset:564 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v246, s32 offset:568 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v247, s32 offset:572 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: v_mov_b32_e32 v2, v0 @@ -5311,152 +7108,291 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ ; DAGISEL64-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v0, s32 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v5, s32 offset:20 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v6, s32 offset:24 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v7, s32 offset:28 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v8, s32 offset:32 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v9, s32 offset:36 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v10, s32 offset:40 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v11, s32 offset:44 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v12, s32 offset:48 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v13, s32 offset:52 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v14, s32 offset:56 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v15, s32 offset:60 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v16, s32 offset:64 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v17, s32 offset:68 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v18, s32 offset:72 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v19, s32 offset:76 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v20, s32 offset:80 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v21, s32 offset:84 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v22, s32 offset:88 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v23, s32 offset:92 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v24, s32 offset:96 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v25, s32 offset:100 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v26, s32 offset:104 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v27, s32 offset:108 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v28, s32 offset:112 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v29, s32 offset:116 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v30, s32 offset:120 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v31, s32 offset:124 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v32, s32 offset:128 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v33, s32 offset:132 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v34, s32 offset:136 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v35, s32 offset:140 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v36, s32 offset:144 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v37, s32 offset:148 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v38, s32 offset:152 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v39, s32 offset:156 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v48, s32 offset:160 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v49, s32 offset:164 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v50, s32 offset:168 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v51, s32 offset:172 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v52, s32 offset:176 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v53, s32 offset:180 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v54, s32 offset:184 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v55, s32 offset:188 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v64, s32 offset:192 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v65, s32 offset:196 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v66, s32 offset:200 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v67, s32 offset:204 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v68, s32 offset:208 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v69, s32 offset:212 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v70, s32 offset:216 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v71, s32 offset:220 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v80, s32 offset:224 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v81, s32 offset:228 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v82, s32 offset:232 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v83, s32 offset:236 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v84, s32 offset:240 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v85, s32 offset:244 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v86, s32 offset:248 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v87, s32 offset:252 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v96, s32 offset:256 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v97, s32 offset:260 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v98, s32 offset:264 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v99, s32 offset:268 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v100, s32 offset:272 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v101, s32 offset:276 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v102, s32 offset:280 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v103, s32 offset:284 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v112, s32 offset:288 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v113, s32 offset:292 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v114, s32 offset:296 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v115, s32 offset:300 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v116, s32 offset:304 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v117, s32 offset:308 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v118, s32 offset:312 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v119, s32 offset:316 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v128, s32 offset:320 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v129, s32 offset:324 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v130, s32 offset:328 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v131, s32 offset:332 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v132, s32 offset:336 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v133, s32 offset:340 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v134, s32 offset:344 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v135, s32 offset:348 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v144, s32 offset:352 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v145, s32 offset:356 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v146, s32 offset:360 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v147, s32 offset:364 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v148, s32 offset:368 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v149, s32 offset:372 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v150, s32 offset:376 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v151, s32 offset:380 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v160, s32 offset:384 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v161, s32 offset:388 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v162, s32 offset:392 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v163, s32 offset:396 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v164, s32 offset:400 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v165, s32 offset:404 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v166, s32 offset:408 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v167, s32 offset:412 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v176, s32 offset:416 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v177, s32 offset:420 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v178, s32 offset:424 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v179, s32 offset:428 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v180, s32 offset:432 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v181, s32 offset:436 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v182, s32 offset:440 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v183, s32 offset:444 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v192, s32 offset:448 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v193, s32 offset:452 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v194, s32 offset:456 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v195, s32 offset:460 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v196, s32 offset:464 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v197, s32 offset:468 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v198, s32 offset:472 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v199, s32 offset:476 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v208, s32 offset:480 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v209, s32 offset:484 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v210, s32 offset:488 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v211, s32 offset:492 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v212, s32 offset:496 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v213, s32 offset:500 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v214, s32 offset:504 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v215, s32 offset:508 ; DAGISEL64-NEXT: s_clause 0xf ; DAGISEL64-NEXT: scratch_store_b32 off, v224, s32 offset:512 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v225, s32 offset:516 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v226, s32 offset:520 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v227, s32 offset:524 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v228, s32 offset:528 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v229, s32 offset:532 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v230, s32 offset:536 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v231, s32 offset:540 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v240, s32 offset:544 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v241, s32 offset:548 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v242, s32 offset:552 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v243, s32 offset:556 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v244, s32 offset:560 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v245, s32 offset:564 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v246, s32 offset:568 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v247, s32 offset:572 ; DAGISEL64-NEXT: s_mov_b64 exec, -1 ; DAGISEL64-NEXT: v_mov_b32_e32 v2, v0 @@ -5627,152 +7563,291 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ ; GISEL64-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v0, s32 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v5, s32 offset:20 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v6, s32 offset:24 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v7, s32 offset:28 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v8, s32 offset:32 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v9, s32 offset:36 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v10, s32 offset:40 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v11, s32 offset:44 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v12, s32 offset:48 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v13, s32 offset:52 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v14, s32 offset:56 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v15, s32 offset:60 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v16, s32 offset:64 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v17, s32 offset:68 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v18, s32 offset:72 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v19, s32 offset:76 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v20, s32 offset:80 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v21, s32 offset:84 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v22, s32 offset:88 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v23, s32 offset:92 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v24, s32 offset:96 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v25, s32 offset:100 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v26, s32 offset:104 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v27, s32 offset:108 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v28, s32 offset:112 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v29, s32 offset:116 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v30, s32 offset:120 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v31, s32 offset:124 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v32, s32 offset:128 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v33, s32 offset:132 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v34, s32 offset:136 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v35, s32 offset:140 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v36, s32 offset:144 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v37, s32 offset:148 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v38, s32 offset:152 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v39, s32 offset:156 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v48, s32 offset:160 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v49, s32 offset:164 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v50, s32 offset:168 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v51, s32 offset:172 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v52, s32 offset:176 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v53, s32 offset:180 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v54, s32 offset:184 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v55, s32 offset:188 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v64, s32 offset:192 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v65, s32 offset:196 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v66, s32 offset:200 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v67, s32 offset:204 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v68, s32 offset:208 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v69, s32 offset:212 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v70, s32 offset:216 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v71, s32 offset:220 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v80, s32 offset:224 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v81, s32 offset:228 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v82, s32 offset:232 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v83, s32 offset:236 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v84, s32 offset:240 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v85, s32 offset:244 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v86, s32 offset:248 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v87, s32 offset:252 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v96, s32 offset:256 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v97, s32 offset:260 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v98, s32 offset:264 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v99, s32 offset:268 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v100, s32 offset:272 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v101, s32 offset:276 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v102, s32 offset:280 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v103, s32 offset:284 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v112, s32 offset:288 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v113, s32 offset:292 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v114, s32 offset:296 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v115, s32 offset:300 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v116, s32 offset:304 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v117, s32 offset:308 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v118, s32 offset:312 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v119, s32 offset:316 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v128, s32 offset:320 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v129, s32 offset:324 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v130, s32 offset:328 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v131, s32 offset:332 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v132, s32 offset:336 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v133, s32 offset:340 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v134, s32 offset:344 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v135, s32 offset:348 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v144, s32 offset:352 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v145, s32 offset:356 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v146, s32 offset:360 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v147, s32 offset:364 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v148, s32 offset:368 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v149, s32 offset:372 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v150, s32 offset:376 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v151, s32 offset:380 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v160, s32 offset:384 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v161, s32 offset:388 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v162, s32 offset:392 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v163, s32 offset:396 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v164, s32 offset:400 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v165, s32 offset:404 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v166, s32 offset:408 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v167, s32 offset:412 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v176, s32 offset:416 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v177, s32 offset:420 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v178, s32 offset:424 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v179, s32 offset:428 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v180, s32 offset:432 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v181, s32 offset:436 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v182, s32 offset:440 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v183, s32 offset:444 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v192, s32 offset:448 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v193, s32 offset:452 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v194, s32 offset:456 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v195, s32 offset:460 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v196, s32 offset:464 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v197, s32 offset:468 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v198, s32 offset:472 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v199, s32 offset:476 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v208, s32 offset:480 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v209, s32 offset:484 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v210, s32 offset:488 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v211, s32 offset:492 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v212, s32 offset:496 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v213, s32 offset:500 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v214, s32 offset:504 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v215, s32 offset:508 ; GISEL64-NEXT: s_clause 0xf ; GISEL64-NEXT: scratch_store_b32 off, v224, s32 offset:512 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v225, s32 offset:516 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v226, s32 offset:520 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v227, s32 offset:524 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v228, s32 offset:528 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v229, s32 offset:532 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v230, s32 offset:536 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v231, s32 offset:540 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v240, s32 offset:544 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v241, s32 offset:548 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v242, s32 offset:552 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v243, s32 offset:556 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v244, s32 offset:560 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v245, s32 offset:564 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v246, s32 offset:568 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v247, s32 offset:572 ; GISEL64-NEXT: s_mov_b64 exec, -1 ; GISEL64-NEXT: v_mov_b32_e32 v2, v0 @@ -5940,933 +8015,1830 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s32 offset:24 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s32 offset:28 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s32 offset:32 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s32 offset:36 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s32 offset:40 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s32 offset:44 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s32 offset:48 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s32 offset:52 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s32 offset:56 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s32 offset:60 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s32 offset:64 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s32 offset:68 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s32 offset:72 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s32 offset:76 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s32 offset:80 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s32 offset:84 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s32 offset:88 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s32 offset:92 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s32 offset:96 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s32 offset:100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s32 offset:104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s32 offset:108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s32 offset:112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s32 offset:140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s32 offset:144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s32 offset:148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s32 offset:152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s32 offset:156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s32 offset:160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s32 offset:168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s32 offset:172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s32 offset:176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s32 offset:180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s32 offset:184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s32 offset:188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s32 offset:192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s32 offset:196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s32 offset:200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s32 offset:204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s32 offset:208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s32 offset:212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s32 offset:216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s32 offset:220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s32 offset:224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s32 offset:228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s32 offset:232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s32 offset:236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s32 offset:240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s32 offset:268 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s32 offset:272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s32 offset:276 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s32 offset:280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s32 offset:284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s32 offset:288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s32 offset:292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s32 offset:296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s32 offset:300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s32 offset:304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s32 offset:308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s32 offset:312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s32 offset:316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s32 offset:320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s32 offset:324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s32 offset:328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s32 offset:332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s32 offset:336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s32 offset:340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s32 offset:344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s32 offset:348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s32 offset:352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s32 offset:356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s32 offset:360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s32 offset:364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s32 offset:368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s32 offset:396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s32 offset:400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s32 offset:404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s32 offset:408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s32 offset:412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s32 offset:416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s32 offset:420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s32 offset:424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s32 offset:428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s32 offset:432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s32 offset:436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s32 offset:440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s32 offset:444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s32 offset:448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s32 offset:452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s32 offset:456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s32 offset:460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s32 offset:464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s32 offset:468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s32 offset:472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s32 offset:476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s32 offset:480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s32 offset:484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s32 offset:488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s32 offset:492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s32 offset:496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s32 offset:524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s32 offset:528 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s32 offset:532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s32 offset:536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s32 offset:540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s32 offset:544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s32 offset:548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s32 offset:552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s32 offset:556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s32 offset:560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s32 offset:564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s32 offset:568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s32 offset:572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 4 ; msbs: dst=0 src0=0 src1=1 src2=0 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s32 offset:576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s32 offset:580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s32 offset:584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s32 offset:588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s32 offset:592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s32 offset:596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s32 offset:600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s32 offset:604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s32 offset:608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s32 offset:612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s32 offset:616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s32 offset:620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s32 offset:624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s32 offset:628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s32 offset:632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s32 offset:636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s32 offset:640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s32 offset:644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s32 offset:648 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s32 offset:652 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s32 offset:656 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s32 offset:660 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s32 offset:664 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s32 offset:668 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s32 offset:672 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s32 offset:676 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s32 offset:680 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s32 offset:684 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s32 offset:688 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s32 offset:692 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s32 offset:696 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s32 offset:700 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s32 offset:704 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s32 offset:708 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s32 offset:712 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s32 offset:716 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s32 offset:720 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s32 offset:724 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s32 offset:728 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s32 offset:732 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s32 offset:736 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s32 offset:740 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s32 offset:744 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s32 offset:748 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s32 offset:752 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s32 offset:756 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s32 offset:760 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s32 offset:764 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s32 offset:768 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s32 offset:772 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s32 offset:776 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s32 offset:780 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s32 offset:784 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s32 offset:788 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s32 offset:792 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s32 offset:796 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s32 offset:800 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s32 offset:804 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s32 offset:808 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s32 offset:812 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s32 offset:816 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s32 offset:820 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s32 offset:824 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s32 offset:828 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s32 offset:832 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s32 offset:836 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s32 offset:840 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s32 offset:844 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s32 offset:848 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s32 offset:852 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s32 offset:856 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s32 offset:860 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s32 offset:864 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s32 offset:868 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s32 offset:872 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s32 offset:876 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s32 offset:880 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s32 offset:884 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s32 offset:888 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s32 offset:892 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s32 offset:896 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s32 offset:900 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s32 offset:904 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s32 offset:908 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s32 offset:912 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s32 offset:916 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s32 offset:920 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s32 offset:924 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s32 offset:928 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s32 offset:932 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s32 offset:936 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s32 offset:940 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s32 offset:944 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s32 offset:948 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s32 offset:952 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s32 offset:956 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s32 offset:960 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s32 offset:964 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s32 offset:968 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s32 offset:972 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s32 offset:976 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s32 offset:980 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s32 offset:984 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s32 offset:988 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s32 offset:992 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s32 offset:996 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s32 offset:1000 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s32 offset:1004 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s32 offset:1008 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s32 offset:1012 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s32 offset:1016 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s32 offset:1020 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s32 offset:1024 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s32 offset:1028 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s32 offset:1032 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s32 offset:1036 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s32 offset:1040 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s32 offset:1044 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s32 offset:1048 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s32 offset:1052 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s32 offset:1056 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s32 offset:1060 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s32 offset:1064 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s32 offset:1068 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s32 offset:1072 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s32 offset:1076 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s32 offset:1080 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s32 offset:1084 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s32 offset:1088 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s32 offset:1092 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s32 offset:1096 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s32 offset:1100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s32 offset:1104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s32 offset:1108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s32 offset:1112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s32 offset:1116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s32 offset:1120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s32 offset:1124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s32 offset:1128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s32 offset:1132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s32 offset:1136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s32 offset:1140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s32 offset:1144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s32 offset:1148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s32 offset:1152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s32 offset:1156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s32 offset:1160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s32 offset:1164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s32 offset:1168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s32 offset:1172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s32 offset:1176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s32 offset:1180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s32 offset:1184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s32 offset:1188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s32 offset:1192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s32 offset:1196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s32 offset:1200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s32 offset:1204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s32 offset:1208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s32 offset:1212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s32 offset:1216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s32 offset:1220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s32 offset:1224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s32 offset:1228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s32 offset:1232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s32 offset:1236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s32 offset:1240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s32 offset:1244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s32 offset:1248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s32 offset:1252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s32 offset:1256 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s32 offset:1260 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s32 offset:1264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s32 offset:1268 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s32 offset:1272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s32 offset:1276 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s32 offset:1280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s32 offset:1284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s32 offset:1288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s32 offset:1292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s32 offset:1296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s32 offset:1300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s32 offset:1304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s32 offset:1308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s32 offset:1312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s32 offset:1316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s32 offset:1320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s32 offset:1324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s32 offset:1328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s32 offset:1332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s32 offset:1336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s32 offset:1340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s32 offset:1344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s32 offset:1348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s32 offset:1352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s32 offset:1356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s32 offset:1360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s32 offset:1364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s32 offset:1368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s32 offset:1372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s32 offset:1376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s32 offset:1380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s32 offset:1384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s32 offset:1388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s32 offset:1392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s32 offset:1396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s32 offset:1400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s32 offset:1404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s32 offset:1408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s32 offset:1412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s32 offset:1416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s32 offset:1420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s32 offset:1424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s32 offset:1428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s32 offset:1432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s32 offset:1436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s32 offset:1440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s32 offset:1444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s32 offset:1448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s32 offset:1452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s32 offset:1456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s32 offset:1460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s32 offset:1464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s32 offset:1468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s32 offset:1472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s32 offset:1476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s32 offset:1480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s32 offset:1484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s32 offset:1488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s32 offset:1492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s32 offset:1496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s32 offset:1500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s32 offset:1504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s32 offset:1508 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s32 offset:1512 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s32 offset:1516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s32 offset:1520 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s32 offset:1524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s32 offset:1528 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s32 offset:1532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s32 offset:1536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s32 offset:1540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s32 offset:1544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s32 offset:1548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s32 offset:1552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s32 offset:1556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s32 offset:1560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s32 offset:1564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s32 offset:1568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s32 offset:1572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s32 offset:1576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s32 offset:1580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s32 offset:1584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s32 offset:1588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s32 offset:1592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s32 offset:1596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 8 ; msbs: dst=0 src0=0 src1=2 src2=0 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s32 offset:1600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s32 offset:1604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s32 offset:1608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s32 offset:1612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s32 offset:1616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s32 offset:1620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s32 offset:1624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s32 offset:1628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s32 offset:1632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s32 offset:1636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s32 offset:1640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s32 offset:1644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s32 offset:1648 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s32 offset:1652 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s32 offset:1656 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s32 offset:1660 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s32 offset:1664 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s32 offset:1668 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s32 offset:1672 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s32 offset:1676 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s32 offset:1680 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s32 offset:1684 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s32 offset:1688 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s32 offset:1692 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s32 offset:1696 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s32 offset:1700 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s32 offset:1704 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s32 offset:1708 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s32 offset:1712 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s32 offset:1716 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s32 offset:1720 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s32 offset:1724 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s32 offset:1728 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s32 offset:1732 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s32 offset:1736 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s32 offset:1740 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s32 offset:1744 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s32 offset:1748 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s32 offset:1752 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s32 offset:1756 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s32 offset:1760 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s32 offset:1764 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s32 offset:1768 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s32 offset:1772 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s32 offset:1776 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s32 offset:1780 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s32 offset:1784 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s32 offset:1788 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s32 offset:1792 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s32 offset:1796 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s32 offset:1800 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s32 offset:1804 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s32 offset:1808 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s32 offset:1812 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s32 offset:1816 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s32 offset:1820 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s32 offset:1824 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s32 offset:1828 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s32 offset:1832 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s32 offset:1836 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s32 offset:1840 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s32 offset:1844 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s32 offset:1848 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s32 offset:1852 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s32 offset:1856 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s32 offset:1860 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s32 offset:1864 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s32 offset:1868 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s32 offset:1872 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s32 offset:1876 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s32 offset:1880 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s32 offset:1884 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s32 offset:1888 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s32 offset:1892 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s32 offset:1896 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s32 offset:1900 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s32 offset:1904 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s32 offset:1908 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s32 offset:1912 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s32 offset:1916 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s32 offset:1920 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s32 offset:1924 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s32 offset:1928 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s32 offset:1932 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s32 offset:1936 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s32 offset:1940 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s32 offset:1944 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s32 offset:1948 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s32 offset:1952 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s32 offset:1956 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s32 offset:1960 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s32 offset:1964 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s32 offset:1968 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s32 offset:1972 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s32 offset:1976 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s32 offset:1980 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s32 offset:1984 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s32 offset:1988 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s32 offset:1992 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s32 offset:1996 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s32 offset:2000 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s32 offset:2004 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s32 offset:2008 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s32 offset:2012 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s32 offset:2016 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s32 offset:2020 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s32 offset:2024 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s32 offset:2028 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s32 offset:2032 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s32 offset:2036 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s32 offset:2040 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s32 offset:2044 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s32 offset:2048 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s32 offset:2052 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s32 offset:2056 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s32 offset:2060 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s32 offset:2064 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s32 offset:2068 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s32 offset:2072 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s32 offset:2076 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s32 offset:2080 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s32 offset:2084 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s32 offset:2088 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s32 offset:2092 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s32 offset:2096 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s32 offset:2100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s32 offset:2104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s32 offset:2108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s32 offset:2112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s32 offset:2116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s32 offset:2120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s32 offset:2124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s32 offset:2128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s32 offset:2132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s32 offset:2136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s32 offset:2140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s32 offset:2144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s32 offset:2148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s32 offset:2152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s32 offset:2156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s32 offset:2160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s32 offset:2164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s32 offset:2168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s32 offset:2172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s32 offset:2176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s32 offset:2180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s32 offset:2184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s32 offset:2188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s32 offset:2192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s32 offset:2196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s32 offset:2200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s32 offset:2204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s32 offset:2208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s32 offset:2212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s32 offset:2216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s32 offset:2220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s32 offset:2224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s32 offset:2228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s32 offset:2232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s32 offset:2236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s32 offset:2240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s32 offset:2244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s32 offset:2248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s32 offset:2252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s32 offset:2256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s32 offset:2260 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s32 offset:2264 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s32 offset:2268 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s32 offset:2272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s32 offset:2276 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s32 offset:2280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s32 offset:2284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s32 offset:2288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s32 offset:2292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s32 offset:2296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s32 offset:2300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s32 offset:2304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s32 offset:2308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s32 offset:2312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s32 offset:2316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s32 offset:2320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s32 offset:2324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s32 offset:2328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s32 offset:2332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s32 offset:2336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s32 offset:2340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s32 offset:2344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s32 offset:2348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s32 offset:2352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s32 offset:2356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s32 offset:2360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s32 offset:2364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s32 offset:2368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s32 offset:2372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s32 offset:2376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s32 offset:2380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s32 offset:2384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s32 offset:2388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s32 offset:2392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s32 offset:2396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s32 offset:2400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s32 offset:2404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s32 offset:2408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s32 offset:2412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s32 offset:2416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s32 offset:2420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s32 offset:2424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s32 offset:2428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s32 offset:2432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s32 offset:2436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s32 offset:2440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s32 offset:2444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s32 offset:2448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s32 offset:2452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s32 offset:2456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s32 offset:2460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s32 offset:2464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s32 offset:2468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s32 offset:2472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s32 offset:2476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s32 offset:2480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s32 offset:2484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s32 offset:2488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s32 offset:2492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s32 offset:2496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s32 offset:2500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s32 offset:2504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s32 offset:2508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s32 offset:2512 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s32 offset:2516 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s32 offset:2520 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s32 offset:2524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s32 offset:2528 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s32 offset:2532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s32 offset:2536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s32 offset:2540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s32 offset:2544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s32 offset:2548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s32 offset:2552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s32 offset:2556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s32 offset:2560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s32 offset:2564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s32 offset:2568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s32 offset:2572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s32 offset:2576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s32 offset:2580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s32 offset:2584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s32 offset:2588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s32 offset:2592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s32 offset:2596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s32 offset:2600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s32 offset:2604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s32 offset:2608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s32 offset:2612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s32 offset:2616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s32 offset:2620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 12 ; msbs: dst=0 src0=0 src1=3 src2=0 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s32 offset:2624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s32 offset:2628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s32 offset:2632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s32 offset:2636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s32 offset:2640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s32 offset:2644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s32 offset:2648 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s32 offset:2652 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s32 offset:2656 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s32 offset:2660 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s32 offset:2664 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s32 offset:2668 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s32 offset:2672 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s32 offset:2676 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s32 offset:2680 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s32 offset:2684 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s32 offset:2688 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s32 offset:2692 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s32 offset:2696 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s32 offset:2700 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s32 offset:2704 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s32 offset:2708 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s32 offset:2712 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s32 offset:2716 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s32 offset:2720 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s32 offset:2724 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s32 offset:2728 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s32 offset:2732 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s32 offset:2736 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s32 offset:2740 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s32 offset:2744 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s32 offset:2748 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s32 offset:2752 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s32 offset:2756 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s32 offset:2760 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s32 offset:2764 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s32 offset:2768 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s32 offset:2772 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s32 offset:2776 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s32 offset:2780 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s32 offset:2784 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s32 offset:2788 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s32 offset:2792 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s32 offset:2796 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s32 offset:2800 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s32 offset:2804 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s32 offset:2808 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s32 offset:2812 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s32 offset:2816 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s32 offset:2820 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s32 offset:2824 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s32 offset:2828 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s32 offset:2832 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s32 offset:2836 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s32 offset:2840 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s32 offset:2844 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s32 offset:2848 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s32 offset:2852 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s32 offset:2856 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s32 offset:2860 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s32 offset:2864 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s32 offset:2868 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s32 offset:2872 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s32 offset:2876 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s32 offset:2880 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s32 offset:2884 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s32 offset:2888 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s32 offset:2892 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s32 offset:2896 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s32 offset:2900 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s32 offset:2904 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s32 offset:2908 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s32 offset:2912 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s32 offset:2916 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s32 offset:2920 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s32 offset:2924 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s32 offset:2928 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s32 offset:2932 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s32 offset:2936 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s32 offset:2940 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s32 offset:2944 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s32 offset:2948 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s32 offset:2952 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s32 offset:2956 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s32 offset:2960 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s32 offset:2964 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s32 offset:2968 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s32 offset:2972 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s32 offset:2976 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s32 offset:2980 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s32 offset:2984 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s32 offset:2988 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s32 offset:2992 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s32 offset:2996 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s32 offset:3000 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s32 offset:3004 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s32 offset:3008 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s32 offset:3012 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s32 offset:3016 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s32 offset:3020 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s32 offset:3024 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s32 offset:3028 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s32 offset:3032 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s32 offset:3036 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s32 offset:3040 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s32 offset:3044 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s32 offset:3048 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s32 offset:3052 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s32 offset:3056 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s32 offset:3060 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s32 offset:3064 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s32 offset:3068 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s32 offset:3072 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s32 offset:3076 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s32 offset:3080 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s32 offset:3084 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s32 offset:3088 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s32 offset:3092 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s32 offset:3096 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s32 offset:3100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s32 offset:3104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s32 offset:3108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s32 offset:3112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s32 offset:3116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s32 offset:3120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s32 offset:3124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s32 offset:3128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s32 offset:3132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s32 offset:3136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s32 offset:3140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s32 offset:3144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s32 offset:3148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s32 offset:3152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s32 offset:3156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s32 offset:3160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s32 offset:3164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s32 offset:3168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s32 offset:3172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s32 offset:3176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s32 offset:3180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s32 offset:3184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s32 offset:3188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s32 offset:3192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s32 offset:3196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s32 offset:3200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s32 offset:3204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s32 offset:3208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s32 offset:3212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s32 offset:3216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s32 offset:3220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s32 offset:3224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s32 offset:3228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s32 offset:3232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s32 offset:3236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s32 offset:3240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s32 offset:3244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s32 offset:3248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s32 offset:3252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s32 offset:3256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s32 offset:3260 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s32 offset:3264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s32 offset:3268 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s32 offset:3272 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s32 offset:3276 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s32 offset:3280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s32 offset:3284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s32 offset:3288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s32 offset:3292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s32 offset:3296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s32 offset:3300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s32 offset:3304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s32 offset:3308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s32 offset:3312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s32 offset:3316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s32 offset:3320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s32 offset:3324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s32 offset:3328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s32 offset:3332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s32 offset:3336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s32 offset:3340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s32 offset:3344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s32 offset:3348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s32 offset:3352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s32 offset:3356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s32 offset:3360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s32 offset:3364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s32 offset:3368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s32 offset:3372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s32 offset:3376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s32 offset:3380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s32 offset:3384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s32 offset:3388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s32 offset:3392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s32 offset:3396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s32 offset:3400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s32 offset:3404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s32 offset:3408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s32 offset:3412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s32 offset:3416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s32 offset:3420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s32 offset:3424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s32 offset:3428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s32 offset:3432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s32 offset:3436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s32 offset:3440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s32 offset:3444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s32 offset:3448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s32 offset:3452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s32 offset:3456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s32 offset:3460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s32 offset:3464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s32 offset:3468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s32 offset:3472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s32 offset:3476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s32 offset:3480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s32 offset:3484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s32 offset:3488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s32 offset:3492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s32 offset:3496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s32 offset:3500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s32 offset:3504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s32 offset:3508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s32 offset:3512 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s32 offset:3516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s32 offset:3520 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s32 offset:3524 ; GFX1250-DAGISEL-NEXT: s_clause 0x1d ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s32 offset:3528 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s32 offset:3532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s32 offset:3536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s32 offset:3540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s32 offset:3544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s32 offset:3548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s32 offset:3552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s32 offset:3556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s32 offset:3560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s32 offset:3564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s32 offset:3568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s32 offset:3572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s32 offset:3576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s32 offset:3580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s32 offset:3584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s32 offset:3588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s32 offset:3592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s32 offset:3596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s32 offset:3600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s32 offset:3604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s32 offset:3608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s32 offset:3612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s32 offset:3616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s32 offset:3620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s32 offset:3624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s32 offset:3628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s32 offset:3632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s32 offset:3636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s32 offset:3640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s32 offset:3644 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 @@ -7884,172 +10856,313 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float> ; DAGISEL-NEXT: s_xor_saveexec_b32 s4, -1 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:172 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:176 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:180 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:184 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:188 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:192 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:196 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:200 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:204 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:208 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:212 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:216 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:220 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:224 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:228 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:232 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:236 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:240 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:244 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:248 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:252 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:256 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:260 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:264 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:268 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:272 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:276 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:280 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:284 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:288 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:292 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:296 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:300 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:304 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:308 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:312 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:316 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:320 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:324 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:328 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:332 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:336 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:340 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:344 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:348 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:352 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:356 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:360 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:364 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:368 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:372 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:376 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:380 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:384 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:388 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:392 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:396 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:400 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:404 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:408 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:412 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:416 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:420 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:424 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:428 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:432 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:436 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:440 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:444 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:448 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:452 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:456 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:460 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:464 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:468 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:472 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:476 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:480 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:484 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:488 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:492 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:496 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:500 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:504 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:508 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:512 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:516 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:520 ; DAGISEL-NEXT: s_clause 0xf ; DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:524 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:528 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:532 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:536 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:540 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:544 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:548 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:552 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:556 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:560 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:564 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:568 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:572 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:576 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:580 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:584 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: s_clause 0x2 ; DAGISEL-NEXT: scratch_store_b32 off, v42, s33 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:164 +; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168 ; DAGISEL-NEXT: s_wait_alu 0xfffe ; DAGISEL-NEXT: v_writelane_b32 v42, s0, 3 -; DAGISEL-NEXT: s_mov_b32 s1, callee@abs32@hi -; DAGISEL-NEXT: s_mov_b32 s0, callee@abs32@lo ; DAGISEL-NEXT: s_addk_co_i32 s32, 0x250 -; DAGISEL-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8 ; DAGISEL-NEXT: v_writelane_b32 v42, s4, 0 ; DAGISEL-NEXT: v_writelane_b32 v42, s30, 1 ; DAGISEL-NEXT: v_writelane_b32 v42, s31, 2 +; DAGISEL-NEXT: s_mov_b32 s1, callee@abs32@hi +; DAGISEL-NEXT: s_mov_b32 s0, callee@abs32@lo +; DAGISEL-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8 ; DAGISEL-NEXT: s_wait_alu 0xfffe ; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] ; DAGISEL-NEXT: flat_store_b32 v[40:41], v0 -; DAGISEL-NEXT: v_readlane_b32 s31, v42, 2 ; DAGISEL-NEXT: v_readlane_b32 s30, v42, 1 +; DAGISEL-NEXT: v_readlane_b32 s31, v42, 2 ; DAGISEL-NEXT: v_readlane_b32 s4, v42, 0 ; DAGISEL-NEXT: v_readlane_b32 s0, v42, 3 ; DAGISEL-NEXT: s_clause 0x2 @@ -8225,172 +11338,313 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float> ; GISEL-NEXT: s_xor_saveexec_b32 s4, -1 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v48, s33 offset:172 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v49, s33 offset:176 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v50, s33 offset:180 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v51, s33 offset:184 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v52, s33 offset:188 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v53, s33 offset:192 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v54, s33 offset:196 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v55, s33 offset:200 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v64, s33 offset:204 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v65, s33 offset:208 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v66, s33 offset:212 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v67, s33 offset:216 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v68, s33 offset:220 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v69, s33 offset:224 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v70, s33 offset:228 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v71, s33 offset:232 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v80, s33 offset:236 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v81, s33 offset:240 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v82, s33 offset:244 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v83, s33 offset:248 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v84, s33 offset:252 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v85, s33 offset:256 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v86, s33 offset:260 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v87, s33 offset:264 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v96, s33 offset:268 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v97, s33 offset:272 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v98, s33 offset:276 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v99, s33 offset:280 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v100, s33 offset:284 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v101, s33 offset:288 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v102, s33 offset:292 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v103, s33 offset:296 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v112, s33 offset:300 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v113, s33 offset:304 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v114, s33 offset:308 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v115, s33 offset:312 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v116, s33 offset:316 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v117, s33 offset:320 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v118, s33 offset:324 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v119, s33 offset:328 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v128, s33 offset:332 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v129, s33 offset:336 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v130, s33 offset:340 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v131, s33 offset:344 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v132, s33 offset:348 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v133, s33 offset:352 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v134, s33 offset:356 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v135, s33 offset:360 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v144, s33 offset:364 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v145, s33 offset:368 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v146, s33 offset:372 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v147, s33 offset:376 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v148, s33 offset:380 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v149, s33 offset:384 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v150, s33 offset:388 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v151, s33 offset:392 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v160, s33 offset:396 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v161, s33 offset:400 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v162, s33 offset:404 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v163, s33 offset:408 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v164, s33 offset:412 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v165, s33 offset:416 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v166, s33 offset:420 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v167, s33 offset:424 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v176, s33 offset:428 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v177, s33 offset:432 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v178, s33 offset:436 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v179, s33 offset:440 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v180, s33 offset:444 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v181, s33 offset:448 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v182, s33 offset:452 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v183, s33 offset:456 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v192, s33 offset:460 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v193, s33 offset:464 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v194, s33 offset:468 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v195, s33 offset:472 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v196, s33 offset:476 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v197, s33 offset:480 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v198, s33 offset:484 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v199, s33 offset:488 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v208, s33 offset:492 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v209, s33 offset:496 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v210, s33 offset:500 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v211, s33 offset:504 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v212, s33 offset:508 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v213, s33 offset:512 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v214, s33 offset:516 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v215, s33 offset:520 ; GISEL-NEXT: s_clause 0xf ; GISEL-NEXT: scratch_store_b32 off, v224, s33 offset:524 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v225, s33 offset:528 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v226, s33 offset:532 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v227, s33 offset:536 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v228, s33 offset:540 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v229, s33 offset:544 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v230, s33 offset:548 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v231, s33 offset:552 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v240, s33 offset:556 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v241, s33 offset:560 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v242, s33 offset:564 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v243, s33 offset:568 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v244, s33 offset:572 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v245, s33 offset:576 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v246, s33 offset:580 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v247, s33 offset:584 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: s_clause 0x2 ; GISEL-NEXT: scratch_store_b32 off, v42, s33 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v40, s33 offset:164 +; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168 ; GISEL-NEXT: s_wait_alu 0xfffe ; GISEL-NEXT: v_writelane_b32 v42, s0, 3 -; GISEL-NEXT: s_mov_b32 s0, callee@abs32@lo -; GISEL-NEXT: s_mov_b32 s1, callee@abs32@hi ; GISEL-NEXT: s_addk_co_i32 s32, 0x250 -; GISEL-NEXT: v_dual_mov_b32 v40, v8 :: v_dual_mov_b32 v41, v9 ; GISEL-NEXT: v_writelane_b32 v42, s4, 0 ; GISEL-NEXT: v_writelane_b32 v42, s30, 1 ; GISEL-NEXT: v_writelane_b32 v42, s31, 2 +; GISEL-NEXT: s_mov_b32 s0, callee@abs32@lo +; GISEL-NEXT: s_mov_b32 s1, callee@abs32@hi +; GISEL-NEXT: v_dual_mov_b32 v40, v8 :: v_dual_mov_b32 v41, v9 ; GISEL-NEXT: s_wait_alu 0xfffe ; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GISEL-NEXT: flat_store_b32 v[40:41], v0 -; GISEL-NEXT: v_readlane_b32 s31, v42, 2 ; GISEL-NEXT: v_readlane_b32 s30, v42, 1 +; GISEL-NEXT: v_readlane_b32 s31, v42, 2 ; GISEL-NEXT: v_readlane_b32 s4, v42, 0 ; GISEL-NEXT: v_readlane_b32 s0, v42, 3 ; GISEL-NEXT: s_clause 0x2 @@ -8566,174 +11820,315 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float> ; DAGISEL64-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v0, s33 offset:4 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v1, s33 offset:8 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v2, s33 offset:12 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v3, s33 offset:16 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v4, s33 offset:20 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v5, s33 offset:24 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v6, s33 offset:28 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v7, s33 offset:32 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v8, s33 offset:36 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v9, s33 offset:40 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v10, s33 offset:44 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v11, s33 offset:48 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v12, s33 offset:52 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v13, s33 offset:56 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v14, s33 offset:60 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v15, s33 offset:64 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v16, s33 offset:68 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v17, s33 offset:72 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v18, s33 offset:76 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v19, s33 offset:80 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v20, s33 offset:84 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v21, s33 offset:88 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v22, s33 offset:92 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v23, s33 offset:96 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v24, s33 offset:100 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v25, s33 offset:104 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v26, s33 offset:108 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v27, s33 offset:112 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v28, s33 offset:116 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v29, s33 offset:120 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v30, s33 offset:124 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v31, s33 offset:128 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v32, s33 offset:132 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v33, s33 offset:136 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v34, s33 offset:140 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v35, s33 offset:144 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v36, s33 offset:148 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v37, s33 offset:152 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v38, s33 offset:156 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v39, s33 offset:160 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v48, s33 offset:172 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v49, s33 offset:176 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v50, s33 offset:180 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v51, s33 offset:184 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v52, s33 offset:188 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v53, s33 offset:192 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v54, s33 offset:196 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v55, s33 offset:200 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v64, s33 offset:204 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v65, s33 offset:208 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v66, s33 offset:212 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v67, s33 offset:216 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v68, s33 offset:220 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v69, s33 offset:224 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v70, s33 offset:228 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v71, s33 offset:232 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v80, s33 offset:236 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v81, s33 offset:240 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v82, s33 offset:244 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v83, s33 offset:248 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v84, s33 offset:252 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v85, s33 offset:256 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v86, s33 offset:260 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v87, s33 offset:264 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v96, s33 offset:268 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v97, s33 offset:272 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v98, s33 offset:276 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v99, s33 offset:280 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v100, s33 offset:284 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v101, s33 offset:288 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v102, s33 offset:292 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v103, s33 offset:296 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v112, s33 offset:300 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v113, s33 offset:304 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v114, s33 offset:308 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v115, s33 offset:312 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v116, s33 offset:316 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v117, s33 offset:320 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v118, s33 offset:324 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v119, s33 offset:328 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v128, s33 offset:332 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v129, s33 offset:336 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v130, s33 offset:340 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v131, s33 offset:344 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v132, s33 offset:348 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v133, s33 offset:352 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v134, s33 offset:356 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v135, s33 offset:360 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v144, s33 offset:364 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v145, s33 offset:368 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v146, s33 offset:372 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v147, s33 offset:376 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v148, s33 offset:380 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v149, s33 offset:384 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v150, s33 offset:388 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v151, s33 offset:392 ; DAGISEL64-NEXT: s_clause 0x1f ; DAGISEL64-NEXT: scratch_store_b32 off, v160, s33 offset:396 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v161, s33 offset:400 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v162, s33 offset:404 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v163, s33 offset:408 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v164, s33 offset:412 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v165, s33 offset:416 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v166, s33 offset:420 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v167, s33 offset:424 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v176, s33 offset:428 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v177, s33 offset:432 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v178, s33 offset:436 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v179, s33 offset:440 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v180, s33 offset:444 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v181, s33 offset:448 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v182, s33 offset:452 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v183, s33 offset:456 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v192, s33 offset:460 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v193, s33 offset:464 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v194, s33 offset:468 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v195, s33 offset:472 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v196, s33 offset:476 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v197, s33 offset:480 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v198, s33 offset:484 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v199, s33 offset:488 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v208, s33 offset:492 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v209, s33 offset:496 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v210, s33 offset:500 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v211, s33 offset:504 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v212, s33 offset:508 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v213, s33 offset:512 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v214, s33 offset:516 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v215, s33 offset:520 ; DAGISEL64-NEXT: s_clause 0xf ; DAGISEL64-NEXT: scratch_store_b32 off, v224, s33 offset:524 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v225, s33 offset:528 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v226, s33 offset:532 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v227, s33 offset:536 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v228, s33 offset:540 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v229, s33 offset:544 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v230, s33 offset:548 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v231, s33 offset:552 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v240, s33 offset:556 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v241, s33 offset:560 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v242, s33 offset:564 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v243, s33 offset:568 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v244, s33 offset:572 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v245, s33 offset:576 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v246, s33 offset:580 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v247, s33 offset:584 ; DAGISEL64-NEXT: s_mov_b64 exec, -1 ; DAGISEL64-NEXT: s_clause 0x2 ; DAGISEL64-NEXT: scratch_store_b32 off, v42, s33 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v40, s33 offset:164 +; DAGISEL64-NEXT: ; meta instruction ; DAGISEL64-NEXT: scratch_store_b32 off, v41, s33 offset:168 ; DAGISEL64-NEXT: s_wait_alu 0xfffe ; DAGISEL64-NEXT: v_writelane_b32 v42, s0, 4 -; DAGISEL64-NEXT: s_mov_b32 s1, callee@abs32@hi -; DAGISEL64-NEXT: s_mov_b32 s0, callee@abs32@lo ; DAGISEL64-NEXT: s_addk_co_i32 s32, 0x250 -; DAGISEL64-NEXT: v_mov_b32_e32 v41, v9 ; DAGISEL64-NEXT: v_writelane_b32 v42, s4, 0 -; DAGISEL64-NEXT: v_mov_b32_e32 v40, v8 ; DAGISEL64-NEXT: v_writelane_b32 v42, s5, 1 ; DAGISEL64-NEXT: v_writelane_b32 v42, s30, 2 ; DAGISEL64-NEXT: v_writelane_b32 v42, s31, 3 +; DAGISEL64-NEXT: s_mov_b32 s1, callee@abs32@hi +; DAGISEL64-NEXT: s_mov_b32 s0, callee@abs32@lo +; DAGISEL64-NEXT: v_mov_b32_e32 v41, v9 +; DAGISEL64-NEXT: v_mov_b32_e32 v40, v8 ; DAGISEL64-NEXT: s_wait_alu 0xfffe ; DAGISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1] ; DAGISEL64-NEXT: flat_store_b32 v[40:41], v0 -; DAGISEL64-NEXT: v_readlane_b32 s31, v42, 3 ; DAGISEL64-NEXT: v_readlane_b32 s30, v42, 2 +; DAGISEL64-NEXT: v_readlane_b32 s31, v42, 3 ; DAGISEL64-NEXT: v_readlane_b32 s5, v42, 1 ; DAGISEL64-NEXT: v_readlane_b32 s4, v42, 0 ; DAGISEL64-NEXT: v_readlane_b32 s0, v42, 4 @@ -8910,174 +12305,315 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float> ; GISEL64-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v0, s33 offset:4 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v1, s33 offset:8 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v2, s33 offset:12 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v3, s33 offset:16 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v4, s33 offset:20 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v5, s33 offset:24 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v6, s33 offset:28 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v7, s33 offset:32 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v8, s33 offset:36 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v9, s33 offset:40 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v10, s33 offset:44 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v11, s33 offset:48 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v12, s33 offset:52 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v13, s33 offset:56 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v14, s33 offset:60 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v15, s33 offset:64 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v16, s33 offset:68 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v17, s33 offset:72 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v18, s33 offset:76 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v19, s33 offset:80 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v20, s33 offset:84 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v21, s33 offset:88 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v22, s33 offset:92 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v23, s33 offset:96 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v24, s33 offset:100 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v25, s33 offset:104 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v26, s33 offset:108 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v27, s33 offset:112 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v28, s33 offset:116 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v29, s33 offset:120 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v30, s33 offset:124 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v31, s33 offset:128 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v32, s33 offset:132 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v33, s33 offset:136 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v34, s33 offset:140 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v35, s33 offset:144 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v36, s33 offset:148 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v37, s33 offset:152 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v38, s33 offset:156 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v39, s33 offset:160 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v48, s33 offset:172 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v49, s33 offset:176 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v50, s33 offset:180 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v51, s33 offset:184 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v52, s33 offset:188 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v53, s33 offset:192 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v54, s33 offset:196 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v55, s33 offset:200 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v64, s33 offset:204 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v65, s33 offset:208 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v66, s33 offset:212 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v67, s33 offset:216 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v68, s33 offset:220 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v69, s33 offset:224 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v70, s33 offset:228 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v71, s33 offset:232 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v80, s33 offset:236 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v81, s33 offset:240 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v82, s33 offset:244 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v83, s33 offset:248 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v84, s33 offset:252 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v85, s33 offset:256 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v86, s33 offset:260 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v87, s33 offset:264 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v96, s33 offset:268 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v97, s33 offset:272 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v98, s33 offset:276 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v99, s33 offset:280 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v100, s33 offset:284 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v101, s33 offset:288 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v102, s33 offset:292 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v103, s33 offset:296 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v112, s33 offset:300 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v113, s33 offset:304 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v114, s33 offset:308 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v115, s33 offset:312 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v116, s33 offset:316 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v117, s33 offset:320 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v118, s33 offset:324 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v119, s33 offset:328 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v128, s33 offset:332 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v129, s33 offset:336 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v130, s33 offset:340 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v131, s33 offset:344 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v132, s33 offset:348 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v133, s33 offset:352 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v134, s33 offset:356 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v135, s33 offset:360 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v144, s33 offset:364 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v145, s33 offset:368 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v146, s33 offset:372 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v147, s33 offset:376 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v148, s33 offset:380 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v149, s33 offset:384 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v150, s33 offset:388 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v151, s33 offset:392 ; GISEL64-NEXT: s_clause 0x1f ; GISEL64-NEXT: scratch_store_b32 off, v160, s33 offset:396 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v161, s33 offset:400 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v162, s33 offset:404 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v163, s33 offset:408 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v164, s33 offset:412 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v165, s33 offset:416 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v166, s33 offset:420 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v167, s33 offset:424 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v176, s33 offset:428 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v177, s33 offset:432 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v178, s33 offset:436 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v179, s33 offset:440 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v180, s33 offset:444 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v181, s33 offset:448 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v182, s33 offset:452 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v183, s33 offset:456 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v192, s33 offset:460 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v193, s33 offset:464 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v194, s33 offset:468 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v195, s33 offset:472 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v196, s33 offset:476 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v197, s33 offset:480 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v198, s33 offset:484 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v199, s33 offset:488 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v208, s33 offset:492 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v209, s33 offset:496 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v210, s33 offset:500 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v211, s33 offset:504 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v212, s33 offset:508 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v213, s33 offset:512 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v214, s33 offset:516 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v215, s33 offset:520 ; GISEL64-NEXT: s_clause 0xf ; GISEL64-NEXT: scratch_store_b32 off, v224, s33 offset:524 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v225, s33 offset:528 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v226, s33 offset:532 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v227, s33 offset:536 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v228, s33 offset:540 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v229, s33 offset:544 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v230, s33 offset:548 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v231, s33 offset:552 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v240, s33 offset:556 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v241, s33 offset:560 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v242, s33 offset:564 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v243, s33 offset:568 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v244, s33 offset:572 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v245, s33 offset:576 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v246, s33 offset:580 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v247, s33 offset:584 ; GISEL64-NEXT: s_mov_b64 exec, -1 ; GISEL64-NEXT: s_clause 0x2 ; GISEL64-NEXT: scratch_store_b32 off, v42, s33 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v40, s33 offset:164 +; GISEL64-NEXT: ; meta instruction ; GISEL64-NEXT: scratch_store_b32 off, v41, s33 offset:168 ; GISEL64-NEXT: s_wait_alu 0xfffe ; GISEL64-NEXT: v_writelane_b32 v42, s0, 4 -; GISEL64-NEXT: s_mov_b32 s0, callee@abs32@lo -; GISEL64-NEXT: s_mov_b32 s1, callee@abs32@hi ; GISEL64-NEXT: s_addk_co_i32 s32, 0x250 -; GISEL64-NEXT: v_mov_b32_e32 v40, v8 ; GISEL64-NEXT: v_writelane_b32 v42, s4, 0 -; GISEL64-NEXT: v_mov_b32_e32 v41, v9 ; GISEL64-NEXT: v_writelane_b32 v42, s5, 1 ; GISEL64-NEXT: v_writelane_b32 v42, s30, 2 ; GISEL64-NEXT: v_writelane_b32 v42, s31, 3 +; GISEL64-NEXT: s_mov_b32 s0, callee@abs32@lo +; GISEL64-NEXT: s_mov_b32 s1, callee@abs32@hi +; GISEL64-NEXT: v_mov_b32_e32 v40, v8 +; GISEL64-NEXT: v_mov_b32_e32 v41, v9 ; GISEL64-NEXT: s_wait_alu 0xfffe ; GISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GISEL64-NEXT: flat_store_b32 v[40:41], v0 -; GISEL64-NEXT: v_readlane_b32 s31, v42, 3 ; GISEL64-NEXT: v_readlane_b32 s30, v42, 2 +; GISEL64-NEXT: v_readlane_b32 s31, v42, 3 ; GISEL64-NEXT: v_readlane_b32 s5, v42, 1 ; GISEL64-NEXT: v_readlane_b32 s4, v42, 0 ; GISEL64-NEXT: v_readlane_b32 s0, v42, 4 @@ -9251,954 +12787,1853 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float> ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:260 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:268 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:276 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:512 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:520 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:528 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 4 ; msbs: dst=0 src0=0 src1=1 src2=0 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s33 offset:588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s33 offset:592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s33 offset:596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s33 offset:600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s33 offset:604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s33 offset:608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s33 offset:612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s33 offset:616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s33 offset:620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s33 offset:624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s33 offset:628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s33 offset:632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s33 offset:636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s33 offset:640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s33 offset:644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s33 offset:648 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s33 offset:652 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s33 offset:656 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s33 offset:660 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s33 offset:664 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s33 offset:668 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s33 offset:672 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s33 offset:676 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s33 offset:680 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s33 offset:684 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s33 offset:688 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s33 offset:692 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s33 offset:696 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s33 offset:700 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s33 offset:704 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s33 offset:708 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s33 offset:712 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s33 offset:716 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s33 offset:720 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s33 offset:724 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s33 offset:728 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s33 offset:732 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s33 offset:736 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s33 offset:740 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s33 offset:744 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s33 offset:748 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s33 offset:752 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s33 offset:756 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s33 offset:760 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s33 offset:764 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s33 offset:768 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s33 offset:772 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s33 offset:776 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s33 offset:780 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s33 offset:784 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s33 offset:788 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s33 offset:792 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s33 offset:796 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s33 offset:800 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s33 offset:804 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s33 offset:808 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s33 offset:812 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s33 offset:816 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s33 offset:820 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s33 offset:824 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s33 offset:828 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s33 offset:832 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s33 offset:836 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s33 offset:840 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s33 offset:844 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s33 offset:848 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s33 offset:852 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s33 offset:856 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s33 offset:860 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s33 offset:864 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s33 offset:868 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s33 offset:872 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s33 offset:876 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s33 offset:880 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s33 offset:884 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s33 offset:888 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s33 offset:892 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s33 offset:896 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s33 offset:900 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s33 offset:904 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s33 offset:908 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s33 offset:912 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s33 offset:916 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s33 offset:920 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s33 offset:924 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s33 offset:928 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s33 offset:932 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s33 offset:936 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s33 offset:940 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s33 offset:944 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s33 offset:948 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s33 offset:952 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s33 offset:956 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s33 offset:960 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s33 offset:964 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s33 offset:968 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s33 offset:972 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s33 offset:976 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s33 offset:980 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s33 offset:984 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s33 offset:988 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s33 offset:992 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s33 offset:996 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s33 offset:1000 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s33 offset:1004 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s33 offset:1008 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s33 offset:1012 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s33 offset:1016 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s33 offset:1020 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s33 offset:1024 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s33 offset:1028 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s33 offset:1032 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s33 offset:1036 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s33 offset:1040 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s33 offset:1044 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s33 offset:1048 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s33 offset:1052 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s33 offset:1056 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s33 offset:1060 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s33 offset:1064 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s33 offset:1068 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s33 offset:1072 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s33 offset:1076 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s33 offset:1080 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s33 offset:1084 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s33 offset:1088 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s33 offset:1092 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s33 offset:1096 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s33 offset:1100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s33 offset:1104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s33 offset:1108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s33 offset:1112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s33 offset:1116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s33 offset:1120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s33 offset:1124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s33 offset:1128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s33 offset:1132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s33 offset:1136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s33 offset:1140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s33 offset:1144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s33 offset:1148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s33 offset:1152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s33 offset:1156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s33 offset:1160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s33 offset:1164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s33 offset:1168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s33 offset:1172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s33 offset:1176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s33 offset:1180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s33 offset:1184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s33 offset:1188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s33 offset:1192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s33 offset:1196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s33 offset:1200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s33 offset:1204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s33 offset:1208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s33 offset:1212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s33 offset:1216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s33 offset:1220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s33 offset:1224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s33 offset:1228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s33 offset:1232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s33 offset:1236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s33 offset:1240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s33 offset:1244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s33 offset:1248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s33 offset:1252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s33 offset:1256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s33 offset:1260 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s33 offset:1264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s33 offset:1268 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s33 offset:1272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s33 offset:1276 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s33 offset:1280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s33 offset:1284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s33 offset:1288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s33 offset:1292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s33 offset:1296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s33 offset:1300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s33 offset:1304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s33 offset:1308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s33 offset:1312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s33 offset:1316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s33 offset:1320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s33 offset:1324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s33 offset:1328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s33 offset:1332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s33 offset:1336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s33 offset:1340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s33 offset:1344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s33 offset:1348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s33 offset:1352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s33 offset:1356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s33 offset:1360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s33 offset:1364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s33 offset:1368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s33 offset:1372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s33 offset:1376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s33 offset:1380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s33 offset:1384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s33 offset:1388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s33 offset:1392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s33 offset:1396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s33 offset:1400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s33 offset:1404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s33 offset:1408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s33 offset:1412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s33 offset:1416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s33 offset:1420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s33 offset:1424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s33 offset:1428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s33 offset:1432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s33 offset:1436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s33 offset:1440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s33 offset:1444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s33 offset:1448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s33 offset:1452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s33 offset:1456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s33 offset:1460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s33 offset:1464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s33 offset:1468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s33 offset:1472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s33 offset:1476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s33 offset:1480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s33 offset:1484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s33 offset:1488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s33 offset:1492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s33 offset:1496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s33 offset:1500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s33 offset:1504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s33 offset:1508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s33 offset:1512 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s33 offset:1516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s33 offset:1520 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s33 offset:1524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s33 offset:1528 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s33 offset:1532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s33 offset:1536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s33 offset:1540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s33 offset:1544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s33 offset:1548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s33 offset:1552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s33 offset:1556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s33 offset:1560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s33 offset:1564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s33 offset:1568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s33 offset:1572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s33 offset:1576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s33 offset:1580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s33 offset:1584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s33 offset:1588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s33 offset:1592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s33 offset:1596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s33 offset:1600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s33 offset:1604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s33 offset:1608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 8 ; msbs: dst=0 src0=0 src1=2 src2=0 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s33 offset:1612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s33 offset:1616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s33 offset:1620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s33 offset:1624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s33 offset:1628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s33 offset:1632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s33 offset:1636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s33 offset:1640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s33 offset:1644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s33 offset:1648 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s33 offset:1652 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s33 offset:1656 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s33 offset:1660 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s33 offset:1664 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s33 offset:1668 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s33 offset:1672 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s33 offset:1676 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s33 offset:1680 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s33 offset:1684 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s33 offset:1688 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s33 offset:1692 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s33 offset:1696 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s33 offset:1700 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s33 offset:1704 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s33 offset:1708 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s33 offset:1712 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s33 offset:1716 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s33 offset:1720 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s33 offset:1724 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s33 offset:1728 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s33 offset:1732 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s33 offset:1736 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s33 offset:1740 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s33 offset:1744 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s33 offset:1748 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s33 offset:1752 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s33 offset:1756 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s33 offset:1760 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s33 offset:1764 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s33 offset:1768 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s33 offset:1772 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s33 offset:1776 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s33 offset:1780 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s33 offset:1784 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s33 offset:1788 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s33 offset:1792 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s33 offset:1796 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s33 offset:1800 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s33 offset:1804 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s33 offset:1808 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s33 offset:1812 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s33 offset:1816 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s33 offset:1820 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s33 offset:1824 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s33 offset:1828 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s33 offset:1832 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s33 offset:1836 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s33 offset:1840 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s33 offset:1844 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s33 offset:1848 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s33 offset:1852 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s33 offset:1856 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s33 offset:1860 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s33 offset:1864 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s33 offset:1868 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s33 offset:1872 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s33 offset:1876 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s33 offset:1880 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s33 offset:1884 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s33 offset:1888 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s33 offset:1892 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s33 offset:1896 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s33 offset:1900 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s33 offset:1904 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s33 offset:1908 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s33 offset:1912 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s33 offset:1916 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s33 offset:1920 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s33 offset:1924 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s33 offset:1928 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s33 offset:1932 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s33 offset:1936 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s33 offset:1940 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s33 offset:1944 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s33 offset:1948 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s33 offset:1952 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s33 offset:1956 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s33 offset:1960 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s33 offset:1964 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s33 offset:1968 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s33 offset:1972 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s33 offset:1976 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s33 offset:1980 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s33 offset:1984 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s33 offset:1988 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s33 offset:1992 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s33 offset:1996 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s33 offset:2000 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s33 offset:2004 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s33 offset:2008 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s33 offset:2012 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s33 offset:2016 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s33 offset:2020 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s33 offset:2024 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s33 offset:2028 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s33 offset:2032 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s33 offset:2036 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s33 offset:2040 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s33 offset:2044 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s33 offset:2048 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s33 offset:2052 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s33 offset:2056 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s33 offset:2060 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s33 offset:2064 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s33 offset:2068 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s33 offset:2072 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s33 offset:2076 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s33 offset:2080 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s33 offset:2084 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s33 offset:2088 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s33 offset:2092 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s33 offset:2096 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s33 offset:2100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s33 offset:2104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s33 offset:2108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s33 offset:2112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s33 offset:2116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s33 offset:2120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s33 offset:2124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s33 offset:2128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s33 offset:2132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s33 offset:2136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s33 offset:2140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s33 offset:2144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s33 offset:2148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s33 offset:2152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s33 offset:2156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s33 offset:2160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s33 offset:2164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s33 offset:2168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s33 offset:2172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s33 offset:2176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s33 offset:2180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s33 offset:2184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s33 offset:2188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s33 offset:2192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s33 offset:2196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s33 offset:2200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s33 offset:2204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s33 offset:2208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s33 offset:2212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s33 offset:2216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s33 offset:2220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s33 offset:2224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s33 offset:2228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s33 offset:2232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s33 offset:2236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s33 offset:2240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s33 offset:2244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s33 offset:2248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s33 offset:2252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s33 offset:2256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s33 offset:2260 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s33 offset:2264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s33 offset:2268 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s33 offset:2272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s33 offset:2276 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s33 offset:2280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s33 offset:2284 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s33 offset:2288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s33 offset:2292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s33 offset:2296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s33 offset:2300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s33 offset:2304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s33 offset:2308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s33 offset:2312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s33 offset:2316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s33 offset:2320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s33 offset:2324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s33 offset:2328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s33 offset:2332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s33 offset:2336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s33 offset:2340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s33 offset:2344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s33 offset:2348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s33 offset:2352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s33 offset:2356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s33 offset:2360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s33 offset:2364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s33 offset:2368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s33 offset:2372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s33 offset:2376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s33 offset:2380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s33 offset:2384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s33 offset:2388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s33 offset:2392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s33 offset:2396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s33 offset:2400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s33 offset:2404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s33 offset:2408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s33 offset:2412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s33 offset:2416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s33 offset:2420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s33 offset:2424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s33 offset:2428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s33 offset:2432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s33 offset:2436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s33 offset:2440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s33 offset:2444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s33 offset:2448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s33 offset:2452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s33 offset:2456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s33 offset:2460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s33 offset:2464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s33 offset:2468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s33 offset:2472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s33 offset:2476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s33 offset:2480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s33 offset:2484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s33 offset:2488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s33 offset:2492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s33 offset:2496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s33 offset:2500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s33 offset:2504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s33 offset:2508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s33 offset:2512 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s33 offset:2516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s33 offset:2520 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s33 offset:2524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s33 offset:2528 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s33 offset:2532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s33 offset:2536 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s33 offset:2540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s33 offset:2544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s33 offset:2548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s33 offset:2552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s33 offset:2556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s33 offset:2560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s33 offset:2564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s33 offset:2568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s33 offset:2572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s33 offset:2576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s33 offset:2580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s33 offset:2584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s33 offset:2588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s33 offset:2592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s33 offset:2596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s33 offset:2600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s33 offset:2604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s33 offset:2608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s33 offset:2612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s33 offset:2616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s33 offset:2620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s33 offset:2624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s33 offset:2628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s33 offset:2632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 12 ; msbs: dst=0 src0=0 src1=3 src2=0 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s33 offset:2636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s33 offset:2640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s33 offset:2644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s33 offset:2648 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s33 offset:2652 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s33 offset:2656 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s33 offset:2660 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s33 offset:2664 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s33 offset:2668 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s33 offset:2672 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s33 offset:2676 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s33 offset:2680 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s33 offset:2684 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s33 offset:2688 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s33 offset:2692 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s33 offset:2696 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s33 offset:2700 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s33 offset:2704 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s33 offset:2708 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s33 offset:2712 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s33 offset:2716 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s33 offset:2720 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s33 offset:2724 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s33 offset:2728 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s33 offset:2732 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s33 offset:2736 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s33 offset:2740 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s33 offset:2744 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s33 offset:2748 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s33 offset:2752 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s33 offset:2756 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s33 offset:2760 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s33 offset:2764 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s33 offset:2768 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s33 offset:2772 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s33 offset:2776 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s33 offset:2780 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s33 offset:2784 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s33 offset:2788 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s33 offset:2792 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s33 offset:2796 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s33 offset:2800 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s33 offset:2804 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s33 offset:2808 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s33 offset:2812 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s33 offset:2816 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s33 offset:2820 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s33 offset:2824 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s33 offset:2828 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s33 offset:2832 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s33 offset:2836 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s33 offset:2840 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s33 offset:2844 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s33 offset:2848 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s33 offset:2852 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s33 offset:2856 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s33 offset:2860 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s33 offset:2864 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s33 offset:2868 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s33 offset:2872 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s33 offset:2876 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s33 offset:2880 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s33 offset:2884 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s33 offset:2888 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s33 offset:2892 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s33 offset:2896 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s33 offset:2900 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s33 offset:2904 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s33 offset:2908 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s33 offset:2912 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s33 offset:2916 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s33 offset:2920 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s33 offset:2924 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s33 offset:2928 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s33 offset:2932 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s33 offset:2936 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s33 offset:2940 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s33 offset:2944 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s33 offset:2948 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s33 offset:2952 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s33 offset:2956 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s33 offset:2960 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s33 offset:2964 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s33 offset:2968 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s33 offset:2972 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s33 offset:2976 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s33 offset:2980 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s33 offset:2984 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s33 offset:2988 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s33 offset:2992 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s33 offset:2996 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s33 offset:3000 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s33 offset:3004 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s33 offset:3008 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s33 offset:3012 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s33 offset:3016 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s33 offset:3020 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s33 offset:3024 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s33 offset:3028 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s33 offset:3032 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s33 offset:3036 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s33 offset:3040 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s33 offset:3044 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s33 offset:3048 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s33 offset:3052 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s33 offset:3056 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s33 offset:3060 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s33 offset:3064 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s33 offset:3068 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s33 offset:3072 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s33 offset:3076 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s33 offset:3080 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s33 offset:3084 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s33 offset:3088 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s33 offset:3092 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s33 offset:3096 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s33 offset:3100 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s33 offset:3104 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s33 offset:3108 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s33 offset:3112 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s33 offset:3116 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s33 offset:3120 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s33 offset:3124 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s33 offset:3128 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s33 offset:3132 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s33 offset:3136 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s33 offset:3140 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s33 offset:3144 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s33 offset:3148 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s33 offset:3152 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s33 offset:3156 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s33 offset:3160 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s33 offset:3164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s33 offset:3168 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s33 offset:3172 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s33 offset:3176 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s33 offset:3180 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s33 offset:3184 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s33 offset:3188 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s33 offset:3192 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s33 offset:3196 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s33 offset:3200 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s33 offset:3204 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s33 offset:3208 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s33 offset:3212 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s33 offset:3216 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s33 offset:3220 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s33 offset:3224 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s33 offset:3228 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s33 offset:3232 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s33 offset:3236 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s33 offset:3240 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s33 offset:3244 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s33 offset:3248 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s33 offset:3252 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s33 offset:3256 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s33 offset:3260 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s33 offset:3264 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s33 offset:3268 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s33 offset:3272 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s33 offset:3276 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s33 offset:3280 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s33 offset:3284 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s33 offset:3288 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s33 offset:3292 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s33 offset:3296 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s33 offset:3300 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s33 offset:3304 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s33 offset:3308 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s33 offset:3312 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s33 offset:3316 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s33 offset:3320 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s33 offset:3324 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s33 offset:3328 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s33 offset:3332 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s33 offset:3336 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s33 offset:3340 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s33 offset:3344 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s33 offset:3348 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s33 offset:3352 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s33 offset:3356 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s33 offset:3360 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s33 offset:3364 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s33 offset:3368 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s33 offset:3372 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s33 offset:3376 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s33 offset:3380 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s33 offset:3384 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s33 offset:3388 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s33 offset:3392 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s33 offset:3396 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s33 offset:3400 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s33 offset:3404 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s33 offset:3408 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s33 offset:3412 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s33 offset:3416 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s33 offset:3420 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s33 offset:3424 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s33 offset:3428 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s33 offset:3432 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s33 offset:3436 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s33 offset:3440 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s33 offset:3444 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s33 offset:3448 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s33 offset:3452 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s33 offset:3456 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s33 offset:3460 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s33 offset:3464 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s33 offset:3468 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s33 offset:3472 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s33 offset:3476 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s33 offset:3480 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s33 offset:3484 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s33 offset:3488 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s33 offset:3492 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s33 offset:3496 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s33 offset:3500 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s33 offset:3504 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s33 offset:3508 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s33 offset:3512 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s33 offset:3516 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s33 offset:3520 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s33 offset:3524 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s33 offset:3528 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s33 offset:3532 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s33 offset:3536 ; GFX1250-DAGISEL-NEXT: s_clause 0x1d ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s33 offset:3540 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s33 offset:3544 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s33 offset:3548 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s33 offset:3552 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s33 offset:3556 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s33 offset:3560 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s33 offset:3564 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s33 offset:3568 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s33 offset:3572 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s33 offset:3576 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s33 offset:3580 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s33 offset:3584 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s33 offset:3588 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s33 offset:3592 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s33 offset:3596 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s33 offset:3600 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s33 offset:3604 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s33 offset:3608 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s33 offset:3612 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s33 offset:3616 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s33 offset:3620 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s33 offset:3624 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s33 offset:3628 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s33 offset:3632 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s33 offset:3636 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s33 offset:3640 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s33 offset:3644 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s33 offset:3648 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s33 offset:3652 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s33 offset:3656 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-DAGISEL-NEXT: s_clause 0x2 ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42, s33 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:164 +; GFX1250-DAGISEL-NEXT: ; meta instruction ; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x2 ; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s0, 3 -; GFX1250-DAGISEL-NEXT: s_mov_b64 s[0:1], callee@abs64 ; GFX1250-DAGISEL-NEXT: s_addk_co_i32 s32, 0xe50 -; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 -; GFX1250-DAGISEL-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8 ; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s4, 0 ; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s30, 1 ; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s31, 2 +; GFX1250-DAGISEL-NEXT: s_mov_b64 s[0:1], callee@abs64 +; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 +; GFX1250-DAGISEL-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8 ; GFX1250-DAGISEL-NEXT: s_swap_pc_i64 s[30:31], s[0:1] ; GFX1250-DAGISEL-NEXT: flat_store_b32 v[40:41], v0 -; GFX1250-DAGISEL-NEXT: v_readlane_b32 s31, v42, 2 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s30, v42, 1 +; GFX1250-DAGISEL-NEXT: v_readlane_b32 s31, v42, 2 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s4, v42, 0 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s0, v42, 3 ; GFX1250-DAGISEL-NEXT: s_clause 0x2 diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll index 06c451869e841..9eea46172ce81 100644 --- a/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll +++ b/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll @@ -22,9 +22,9 @@ define void @vector_reg_liverange_split() #0 { ; GFX90A-NEXT: v_writelane_b32 v40, s28, 2 ; GFX90A-NEXT: v_writelane_b32 v40, s29, 3 ; GFX90A-NEXT: v_writelane_b32 v40, s30, 0 -; GFX90A-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane ; GFX90A-NEXT: s_addk_i32 s32, 0x400 ; GFX90A-NEXT: v_writelane_b32 v40, s31, 1 +; GFX90A-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; def s20 ; GFX90A-NEXT: ;;#ASMEND @@ -41,12 +41,12 @@ define void @vector_reg_liverange_split() #0 { ; GFX90A-NEXT: s_or_saveexec_b64 s[28:29], -1 ; GFX90A-NEXT: v_accvgpr_read_b32 v39, a32 ; GFX90A-NEXT: s_mov_b64 exec, s[28:29] +; GFX90A-NEXT: v_readlane_b32 s30, v40, 0 ; GFX90A-NEXT: v_readlane_b32 s20, v39, 0 ; GFX90A-NEXT: ;;#ASMSTART ; GFX90A-NEXT: ; use s20 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_readlane_b32 s31, v40, 1 -; GFX90A-NEXT: v_readlane_b32 s30, v40, 0 ; GFX90A-NEXT: s_mov_b32 s32, s33 ; GFX90A-NEXT: v_readlane_b32 s4, v40, 4 ; GFX90A-NEXT: v_readlane_b32 s28, v40, 2 diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll index 9e9fe1809c780..b3ad8880b85a9 100644 --- a/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll +++ b/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll @@ -27,9 +27,9 @@ define void @test() #0 { ; GCN-NEXT: v_writelane_b32 v40, s28, 2 ; GCN-NEXT: v_writelane_b32 v40, s29, 3 ; GCN-NEXT: v_writelane_b32 v40, s30, 0 -; GCN-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane ; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: v_writelane_b32 v40, s31, 1 +; GCN-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ; def s16 ; GCN-NEXT: ;;#ASMEND @@ -49,10 +49,10 @@ define void @test() #0 { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_readlane_b32 s4, v39, 0 ; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_readlane_b32 s30, v40, 0 ; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_readlane_b32 s31, v40, 1 -; GCN-NEXT: v_readlane_b32 s30, v40, 0 ; GCN-NEXT: s_mov_b32 s32, s33 ; GCN-NEXT: v_readlane_b32 s4, v40, 4 ; GCN-NEXT: v_readlane_b32 s28, v40, 2 @@ -111,8 +111,8 @@ define void @test() #0 { ; GCN-O0-NEXT: v_mov_b32_e32 v2, s4 ; GCN-O0-NEXT: global_store_dword v[0:1], v2, off ; GCN-O0-NEXT: s_waitcnt vmcnt(0) -; GCN-O0-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-O0-NEXT: v_readlane_b32 s30, v40, 0 +; GCN-O0-NEXT: v_readlane_b32 s31, v40, 1 ; GCN-O0-NEXT: s_mov_b32 s32, s33 ; GCN-O0-NEXT: v_readlane_b32 s4, v40, 4 ; GCN-O0-NEXT: v_readlane_b32 s28, v40, 2 diff --git a/llvm/test/CodeGen/AMDGPU/widen-vector-shift.ll b/llvm/test/CodeGen/AMDGPU/widen-vector-shift.ll new file mode 100644 index 0000000000000..1d40038abe911 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/widen-vector-shift.ll @@ -0,0 +1,24 @@ +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -O0 -print-after=legalizer %s -o /dev/null 2>&1 | FileCheck %s + +; CHECK-LABEL: widen_ashr_i4: +define amdgpu_kernel void @widen_ashr_i4( + ptr addrspace(1) %res, i4 %a, i4 %b) { +; CHECK: G_ASHR %{{[0-9]+}}:_, %{{[0-9]+}}:_(s16) +entry: + %res.val = ashr i4 %a, %b + store i4 %res.val, ptr addrspace(1) %res + ret void +} + +; CHECK-LABEL: widen_ashr_v4i1: +define amdgpu_kernel void @widen_ashr_v4i1( + ptr addrspace(1) %res, <4 x i1> %a, <4 x i1> %b) { +; CHECK: G_ASHR %{{[0-9]+}}:_, %{{[0-9]+}}:_(s16) +; CHECK: G_ASHR %{{[0-9]+}}:_, %{{[0-9]+}}:_(s16) +; CHECK: G_ASHR %{{[0-9]+}}:_, %{{[0-9]+}}:_(s16) +; CHECK: G_ASHR %{{[0-9]+}}:_, %{{[0-9]+}}:_(s16) +entry: + %res.val = ashr <4 x i1> %a, %b + store <4 x i1> %res.val, ptr addrspace(1) %res + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir b/llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir index fa3b9244c3e4a..2032b98eab979 100644 --- a/llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir +++ b/llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir @@ -833,222 +833,6 @@ body: | $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 = V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, killed $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55, killed $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33, 0, 0, 0, implicit $exec ... ---- -name: test_wmma_scale_F32_16x16x128_F8F6F4_F8_D0_overlaps_A1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale_F32_16x16x128_F8F6F4_F8_D0_overlaps_A1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale_F32_16x16x128_F8F6F4_F8_D0_overlaps_B1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale_F32_16x16x128_F8F6F4_F8_D0_overlaps_B1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale_F32_16x16x128_F8F6F4_F8_D0_overlaps_Index1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale_F32_16x16x128_F8F6F4_F8_D0_overlaps_Index1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr81, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 = V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, killed $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55, killed $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33, 0, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr81, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 = V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, killed $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55, killed $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33, 0, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale_F32_16x16x128_F8F6F4_F6F4_D0_overlaps_A1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale_F32_16x16x128_F8F6F4_F6F4_D0_overlaps_A1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale_F32_16x16x128_F8F6F4_F6F4_D0_overlaps_B1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale_F32_16x16x128_F8F6F4_F6F4_D0_overlaps_B1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale_F32_16x16x128_F8F6F4_F6F4_D0_overlaps_Index1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale_F32_16x16x128_F8F6F4_F6F4_D0_overlaps_Index1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr81, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 = V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, killed $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55, killed $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33, 0, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr81, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 = V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, killed $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55, killed $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33, 0, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale16_F3216_16x16x128_F8F6F4_F8_D0_overlaps_A1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale16_F3216_16x16x128_F8F6F4_F8_D0_overlaps_A1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40_vgpr41, killed $vgpr42_vgpr43, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40_vgpr41, killed $vgpr42_vgpr43, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale16_F32_16x16x128_F8F6F4_F8_D0_overlaps_B1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale16_F32_16x16x128_F8F6F4_F8_D0_overlaps_B1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40_vgpr41, killed $vgpr42_vgpr43, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40_vgpr41, killed $vgpr42_vgpr43, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale16_F32_16x16x128_F8F6F4_F8_D0_overlaps_Index1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale16_F32_16x16x128_F8F6F4_F8_D0_overlaps_Index1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 = V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, killed $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55, killed $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33, 0, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 1, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 = V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, killed $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55, killed $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33, 0, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale16_F3216_16x16x128_F8F6F4_F6f4_D0_overlaps_A1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale16_F3216_16x16x128_F8F6F4_F6f4_D0_overlaps_A1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40_vgpr41, killed $vgpr42_vgpr43, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40_vgpr41, killed $vgpr42_vgpr43, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale16_F32_16x16x128_F8F6F4_F6f4_D0_overlaps_B1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale16_F32_16x16x128_F8F6F4_F6f4_D0_overlaps_B1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40_vgpr41, killed $vgpr42_vgpr43, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40_vgpr41, killed $vgpr42_vgpr43, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, 8, killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, 1, 2, 0, 0, implicit $exec -... - ---- -name: test_wmma_scale16_F32_16x16x128_F8F6F4_F6f4_D0_overlaps_Index1 -body: | - bb.0: - ; GFX1250-LABEL: name: test_wmma_scale16_F32_16x16x128_F8F6F4_F6f4_D0_overlaps_Index1 - ; GFX1250: early-clobber $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: V_NOP_e32 implicit $exec - ; GFX1250-NEXT: early-clobber $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 = V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, killed $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55, killed $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33, 0, 0, 0, implicit $exec - $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, killed $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, 8, killed $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, killed $vgpr40, killed $vgpr41, 2, 2, 0, 0, 1, 1, 0, 0, 0, 0, implicit $exec - $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 = V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr killed $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, killed $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55, killed $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, killed $vgpr32_vgpr33, 0, 0, 0, implicit $exec -... - --- name: test_swmmac_f32_16x16x64_bf16_D0_overlaps_A1 body: | diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll b/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll index 74e9ab718c3d2..f28ceb4e0d8b7 100644 --- a/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll +++ b/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll @@ -387,8 +387,8 @@ define amdgpu_gfx void @strict_wwm_call(ptr addrspace(8) inreg %tmp14, i32 inreg ; GFX9-O0-NEXT: s_mov_b64 exec, s[40:41] ; GFX9-O0-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-O0-NEXT: buffer_store_dword v0, off, s[36:39], s34 offset:4 -; GFX9-O0-NEXT: v_readlane_b32 s31, v3, 1 ; GFX9-O0-NEXT: v_readlane_b32 s30, v3, 0 +; GFX9-O0-NEXT: v_readlane_b32 s31, v3, 1 ; GFX9-O0-NEXT: s_mov_b32 s32, s33 ; GFX9-O0-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload @@ -424,9 +424,9 @@ define amdgpu_gfx void @strict_wwm_call(ptr addrspace(8) inreg %tmp14, i32 inreg ; GFX9-O3-NEXT: v_add_u32_e32 v1, v1, v2 ; GFX9-O3-NEXT: s_mov_b64 exec, s[34:35] ; GFX9-O3-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-O3-NEXT: v_readlane_b32 s30, v3, 0 ; GFX9-O3-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:4 ; GFX9-O3-NEXT: v_readlane_b32 s31, v3, 1 -; GFX9-O3-NEXT: v_readlane_b32 s30, v3, 0 ; GFX9-O3-NEXT: s_mov_b32 s32, s33 ; GFX9-O3-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GFX9-O3-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -624,8 +624,8 @@ define amdgpu_gfx void @strict_wwm_call_i64(ptr addrspace(8) inreg %tmp14, i64 i ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v3 ; GFX9-O0-NEXT: s_mov_b32 s34, 0 ; GFX9-O0-NEXT: buffer_store_dwordx2 v[0:1], off, s[36:39], s34 offset:4 -; GFX9-O0-NEXT: v_readlane_b32 s31, v10, 1 ; GFX9-O0-NEXT: v_readlane_b32 s30, v10, 0 +; GFX9-O0-NEXT: v_readlane_b32 s31, v10, 1 ; GFX9-O0-NEXT: s_mov_b32 s32, s33 ; GFX9-O0-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload @@ -685,9 +685,9 @@ define amdgpu_gfx void @strict_wwm_call_i64(ptr addrspace(8) inreg %tmp14, i64 i ; GFX9-O3-NEXT: s_mov_b64 exec, s[36:37] ; GFX9-O3-NEXT: v_mov_b32_e32 v0, v2 ; GFX9-O3-NEXT: v_mov_b32_e32 v1, v3 +; GFX9-O3-NEXT: v_readlane_b32 s30, v8, 0 ; GFX9-O3-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 offset:4 ; GFX9-O3-NEXT: v_readlane_b32 s31, v8, 1 -; GFX9-O3-NEXT: v_readlane_b32 s30, v8, 0 ; GFX9-O3-NEXT: s_mov_b32 s32, s33 ; GFX9-O3-NEXT: s_xor_saveexec_b64 s[34:35], -1 ; GFX9-O3-NEXT: buffer_load_dword v6, off, s[0:3], s33 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/BPF/BTF/ptr-named.ll b/llvm/test/CodeGen/BPF/BTF/ptr-named.ll index 675c34e976abb..f081d34c2adf6 100644 --- a/llvm/test/CodeGen/BPF/BTF/ptr-named.ll +++ b/llvm/test/CodeGen/BPF/BTF/ptr-named.ll @@ -62,7 +62,7 @@ target triple = "bpfel" !5 = !DIFile(filename: "", directory: "") !6 = !{!7} !7 = !DIDerivedType(tag: DW_TAG_member, name: "ptr", scope: !4, file: !5, baseType: !8, size: 64, align: 64, flags: DIFlagPrivate) -!8 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*const u32", baseType: !9, size: 64, align: 64, dwarfAddressSpace: 0) +!8 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "*const u32", baseType: !9, size: 64, align: 64, addressSpace: 0) !9 = !DIBasicType(name: "u32", size: 32, encoding: DW_ATE_unsigned) !10 = !{} !11 = !{i32 8, !"PIC Level", i32 2} diff --git a/llvm/test/CodeGen/Generic/machine-function-splitter.ll b/llvm/test/CodeGen/Generic/machine-function-splitter.ll index 1a8c9ede8f8b7..6ecd1f59de0bd 100644 --- a/llvm/test/CodeGen/Generic/machine-function-splitter.ll +++ b/llvm/test/CodeGen/Generic/machine-function-splitter.ll @@ -184,7 +184,7 @@ define void @foo6(i1 zeroext %0) nounwind section "nosplit" !prof !14 { ret void } -define i32 @foo7(i1 zeroext %0) personality ptr @__gxx_personality_v0 !prof !14 { +define i32 @foo7(i1 zeroext %0) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !prof !14 { ;; Check that a single cold ehpad is split out. ; MFS-DEFAULTS-LABEL: foo7 ; MFS-DEFAULTS: .section .text.split.foo7,"ax",@progbits @@ -197,10 +197,10 @@ entry: to label %try.cont unwind label %lpad lpad: - %1 = landingpad { ptr, i32 } + %1 = landingpad { i8*, i32 } cleanup - catch ptr @_ZTIi - resume { ptr, i32 } %1 + catch i8* bitcast (i8** @_ZTIi to i8*) + resume { i8*, i32 } %1 try.cont: br i1 %0, label %2, label %4, !prof !17 @@ -218,7 +218,7 @@ try.cont: ret i32 %7 } -define i32 @foo8(i1 zeroext %0) personality ptr @__gxx_personality_v0 !prof !14 { +define i32 @foo8(i1 zeroext %0) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !prof !14 { ;; Check that all ehpads are treated as hot if one of them is hot. ; MFS-DEFAULTS-LABEL: foo8 ; MFS-DEFAULTS-X86: callq _Unwind_Resume@PLT @@ -241,10 +241,10 @@ entry: to label %try.cont unwind label %lpad1 lpad1: - %1 = landingpad { ptr, i32 } + %1 = landingpad { i8*, i32 } cleanup - catch ptr @_ZTIi - resume { ptr, i32 } %1 + catch i8* bitcast (i8** @_ZTIi to i8*) + resume { i8*, i32 } %1 try.cont: br i1 %0, label %hot, label %cold, !prof !17 @@ -255,10 +255,10 @@ hot: to label %exit unwind label %lpad2, !prof !21 lpad2: - %3 = landingpad { ptr, i32 } + %3 = landingpad { i8*, i32 } cleanup - catch ptr @_ZTIi - resume { ptr, i32 } %3 + catch i8* bitcast (i8** @_ZTIi to i8*) + resume { i8*, i32 } %3 cold: %4 = call i32 @baz() @@ -681,7 +681,7 @@ declare i32 @qux() declare void @_Z1fv() declare i32 @__gxx_personality_v0(...) -@_ZTIi = external constant ptr +@_ZTIi = external constant i8* !llvm.module.flags = !{!0} !0 = !{i32 1, !"ProfileSummary", !1} diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir index 0cb9bc095bc50..78c31cea028c2 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir @@ -580,7 +580,6 @@ body: | --- # ALL-LABEL: name: sgpr_for_exec_copy -# ALL: sgprForEXECCopy: '$sgpr2_sgpr3' name: sgpr_for_exec_copy machineFunctionInfo: sgprForEXECCopy: '$sgpr2_sgpr3' diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir index b54ae64032d42..6c76f6d7052b2 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir @@ -96,7 +96,7 @@ body: | ; CHECK: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub1 ; CHECK: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[COPY8]], killed [[COPY9]], 0, implicit $exec ; CHECK: $vgpr0 = COPY [[V_ADD_U32_e64_]] - ; CHECK: SI_RETURN implicit $vgpr0 + ; CHECK: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0 %3:vgpr_32 = COPY $vgpr3 %2:vgpr_32 = COPY $vgpr2 %1:vgpr_32 = COPY $vgpr1 @@ -113,7 +113,7 @@ body: | %14:vgpr_32 = COPY %11.sub1 %15:vgpr_32 = V_ADD_U32_e64 killed %13, killed %14, 0, implicit $exec $vgpr0 = COPY %15 - SI_RETURN implicit $vgpr0 + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0 ... --- @@ -147,7 +147,7 @@ body: | ; CHECK: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub1 ; CHECK: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[COPY8]], killed [[COPY9]], 0, implicit $exec ; CHECK: $vgpr0 = COPY [[V_ADD_U32_e64_]] - ; CHECK: SI_RETURN implicit $vgpr0 + ; CHECK: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0 %3:vgpr_32 = COPY $vgpr3 %2:vgpr_32 = COPY $vgpr2 %1:vgpr_32 = COPY $vgpr1 @@ -164,6 +164,6 @@ body: | %14:vgpr_32 = COPY %11.sub1 %15:vgpr_32 = V_ADD_U32_e64 killed %13, killed %14, 0, implicit $exec $vgpr0 = COPY %15 - SI_RETURN implicit $vgpr0 + S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0 ... diff --git a/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll b/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll index 51af5891c4e0f..b4360bcb2bb14 100644 --- a/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll +++ b/llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll @@ -1,4 +1,4 @@ -; REQUIRES: x86_64-linux +; REQUIRES: bogus-x86_64-linux ; RUN: rm -rf %t.rundir ; RUN: rm -rf %t.channel-basename.* ; RUN: mkdir %t.rundir diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll index 1fec0665c4ca8..7d89798a7385e 100644 --- a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll +++ b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll @@ -7,7 +7,7 @@ source_filename = "1.c" -; ASM: .file "1.c",,"LLVM{{.*}}" +; ASM: .file "1.c",,"AMD LLVM{{.*}}" ; ASM-NEXT: .csect ..text..[PR],5 ; ASM-NEXT: .rename ..text..[PR],"" ; ASM-NEXT: .machine "PWR9" @@ -28,7 +28,7 @@ source_filename = "1.c" ; OBJ32-NEXT: } ; OBJ32-NEXT: File Auxiliary Entry { ; OBJ32-NEXT: Index: 2 -; OBJ32-NEXT: Name: LLVM +; OBJ32-NEXT: Name: AMD LLVM ; OBJ32-NEXT: Type: XFT_CV (0x2) ; OBJ32-NEXT: } ; OBJ32-NEXT: } @@ -50,7 +50,7 @@ source_filename = "1.c" ; OBJ64-NEXT: } ; OBJ64-NEXT: File Auxiliary Entry { ; OBJ64-NEXT: Index: 2 -; OBJ64-NEXT: Name: LLVM +; OBJ64-NEXT: Name: AMD LLVM ; OBJ64-NEXT: Type: XFT_CV (0x2) ; OBJ64-NEXT: Auxiliary Type: AUX_FILE (0xFC) ; OBJ64-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll index 50221acc2b3ad..3cc705a347494 100644 --- a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll +++ b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll @@ -27,7 +27,7 @@ entry: ; CHECK-NEXT: } ; CHECK-NEXT: File Auxiliary Entry { ; CHECK-NEXT: Index: 2 -; CHECK-NEXT: Name: LLVM +; CHECK-NEXT: Name: {{.*}}LLVM ; CHECK-NEXT: Type: XFT_CV (0x2) ; CHECK-NEXT: } ; CHECK-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll index 63d927391936c..1b3cccf30e8e8 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll @@ -225,7 +225,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: File Auxiliary Entry { ; SYM-NEXT: Index: 2 -; SYM-NEXT: Name: LLVM +; SYM-NEXT: Name: {{.*}}LLVM ; SYM-NEXT: Type: XFT_CV (0x2) ; SYM-NEXT: } ; SYM-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll index 10b04b570fa32..468303d8d9cbc 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll @@ -225,7 +225,7 @@ ; SYMS-NEXT: } ; SYMS-NEXT: File Auxiliary Entry { ; SYMS-NEXT: Index: 2 -; SYMS-NEXT: Name: LLVM +; SYMS-NEXT: Name: {{.*}}LLVM ; SYMS-NEXT: Type: XFT_CV (0x2) ; SYMS64-NEXT: Auxiliary Type: AUX_FILE (0xFC) ; SYMS-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll index 77dd56f803117..a65d311c02f21 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll @@ -174,7 +174,7 @@ declare i32 @bar(i32) ; SYM-NEXT: } ; SYM-NEXT: File Auxiliary Entry { ; SYM-NEXT: Index: 2 -; SYM-NEXT: Name: LLVM +; SYM-NEXT: Name: {{.*}}LLVM ; SYM-NEXT: Type: XFT_CV (0x2) ; SYM64-NEXT: Auxiliary Type: AUX_FILE (0xFC) ; SYM-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/git_revision.ll b/llvm/test/CodeGen/PowerPC/git_revision.ll index 86dcc5048425e..c4003a7763750 100644 --- a/llvm/test/CodeGen/PowerPC/git_revision.ll +++ b/llvm/test/CodeGen/PowerPC/git_revision.ll @@ -1,6 +1,7 @@ ; Check that the git revision is contained in the assembly/object files ; REQUIRES: vc-rev-enabled +; REQUIRES: vanilla-revision ; RUN: llc < %s | FileCheck %s -DREVISION=git-revision ; RUN: llc -filetype=obj < %s | FileCheck %s -DREVISION=git-revision diff --git a/llvm/test/CodeGen/PowerPC/regalloc-fast-debug-spill.ll b/llvm/test/CodeGen/PowerPC/regalloc-fast-debug-spill.ll index 05df2ba040081..933aba28ba9c6 100644 --- a/llvm/test/CodeGen/PowerPC/regalloc-fast-debug-spill.ll +++ b/llvm/test/CodeGen/PowerPC/regalloc-fast-debug-spill.ll @@ -187,20 +187,20 @@ attributes #1 = { nocallback nofree nosync nounwind readnone speculatable willre !98 = !DIGlobalVariableExpression(var: !99, expr: !DIExpression()) !99 = distinct !DIGlobalVariable(name: "<&bool as core::fmt::Debug>::{vtable}", scope: null, file: !7, type: !100, isLocal: true, isDefinition: true) !100 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "<&bool as core::fmt::Debug>::{vtable_type}", file: !7, size: 256, align: 64, flags: DIFlagArtificial, elements: !3, vtableHolder: !101, templateParams: !3, identifier: "5e8d2c48c9cc79c318e2bd28b03e141a") -!101 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&bool", baseType: !89, size: 64, align: 64, dwarfAddressSpace: 0) +!101 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&bool", baseType: !89, size: 64, align: 64, addressSpace: 0) !102 = !DIGlobalVariableExpression(var: !103, expr: !DIExpression()) !103 = distinct !DIGlobalVariable(name: "<&i32 as core::fmt::Debug>::{vtable}", scope: null, file: !7, type: !104, isLocal: true, isDefinition: true) !104 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "<&i32 as core::fmt::Debug>::{vtable_type}", file: !7, size: 256, align: 64, flags: DIFlagArtificial, elements: !3, vtableHolder: !105, templateParams: !3, identifier: "d4029746615b6a868ffbc67515d99878") -!105 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&i32", baseType: !80, size: 64, align: 64, dwarfAddressSpace: 0) +!105 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&i32", baseType: !80, size: 64, align: 64, addressSpace: 0) !106 = !DIGlobalVariableExpression(var: !107, expr: !DIExpression()) !107 = distinct !DIGlobalVariable(name: "<&u32 as core::fmt::Debug>::{vtable}", scope: null, file: !7, type: !108, isLocal: true, isDefinition: true) !108 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "<&u32 as core::fmt::Debug>::{vtable_type}", file: !7, size: 256, align: 64, flags: DIFlagArtificial, elements: !3, vtableHolder: !109, templateParams: !3, identifier: "178e0e76b9d9178d686381b2d05a7777") -!109 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&u32", baseType: !110, size: 64, align: 64, dwarfAddressSpace: 0) +!109 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&u32", baseType: !110, size: 64, align: 64, addressSpace: 0) !110 = !DIBasicType(name: "u32", size: 32, encoding: DW_ATE_unsigned) !111 = !DIGlobalVariableExpression(var: !112, expr: !DIExpression()) !112 = distinct !DIGlobalVariable(name: "<&core::option::Option as core::fmt::Debug>::{vtable}", scope: null, file: !7, type: !113, isLocal: true, isDefinition: true) !113 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "<&core::option::Option as core::fmt::Debug>::{vtable_type}", file: !7, size: 256, align: 64, flags: DIFlagArtificial, elements: !3, vtableHolder: !114, templateParams: !3, identifier: "7ca8386b4d420d719587fa3255329a7a") -!114 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&core::option::Option", baseType: !115, size: 64, align: 64, dwarfAddressSpace: 0) +!114 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&core::option::Option", baseType: !115, size: 64, align: 64, addressSpace: 0) !115 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Option", scope: !116, file: !7, size: 128, align: 64, elements: !3, templateParams: !3, identifier: "ad8474e495013fa1e3af4a6b53a05f4b") !116 = !DINamespace(name: "option", scope: !17) !117 = !DIGlobalVariableExpression(var: !118, expr: !DIExpression()) diff --git a/llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll b/llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll index ec4884ff643cb..89ff755719446 100644 --- a/llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll +++ b/llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll @@ -1,4 +1,5 @@ ; RUN: llc --verify-machineinstrs --spv-emit-nonsemantic-debug-info --spirv-ext=+SPV_KHR_non_semantic_info --print-after=spirv-nonsemantic-debug-info -O0 -mtriple=spirv64-unknown-unknown %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-MIR +; XFAIL: * ; RUN: llc --verify-machineinstrs --spv-emit-nonsemantic-debug-info --spirv-ext=+SPV_KHR_non_semantic_info -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: llc --verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_non_semantic_info %s -o - | FileCheck %s --check-prefix=CHECK-OPTION ; TODO(#109287): When type is void * the spirv-val raises an error when DebugInfoNone is set as Base Type argument of DebugTypePointer. diff --git a/llvm/test/CodeGen/X86/fake-use-vector.ll b/llvm/test/CodeGen/X86/fake-use-vector.ll index 4d6ede3082704..1995b42f31cce 100644 --- a/llvm/test/CodeGen/X86/fake-use-vector.ll +++ b/llvm/test/CodeGen/X86/fake-use-vector.ll @@ -1,6 +1,5 @@ ; assert in DAGlegalizer with fake use of 1-element vectors. ; RUN: llc -stop-after=finalize-isel -mtriple=x86_64-unknown-linux -filetype=asm -o - %s | FileCheck %s -; ; ModuleID = 't2.cpp' ; source_filename = "t2.cpp" ; target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/CodeGen/X86/heterogeneous-debug.test b/llvm/test/CodeGen/X86/heterogeneous-debug.test new file mode 100644 index 0000000000000..4a63c3561b5d9 --- /dev/null +++ b/llvm/test/CodeGen/X86/heterogeneous-debug.test @@ -0,0 +1,2841 @@ +# NOTE: This file was generated by llvm/utils/gen-heterogeneous-debug-test.sh +# NOTE: Do not edit this file manually. Instead run: +# NOTE: llvm/utils/gen-heterogeneous-debug-test.sh > llvm/test/CodeGen/X86/heterogeneous-debug.test + +# RUN: split-file %s %t + +;--- ir +; RUN: llc -O0 --filetype=obj < %t/ir | llvm-dwarfdump --diff --debug-info -name Var* -regex - | FileCheck %t/ir +source_filename = "-" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1) +; CHECK-NEXT: DW_AT_name ("Var0") +define dso_local void @Fun0() #0 !dbg !5 { +entry: + %Var0 = alloca i1 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var0, metadata !9, metadata !DIExpression()), !dbg !11 + call void @Esc(ptr %Var0), !dbg !11 + ret void, !dbg !11 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var1") +define dso_local void @Fun1() #0 !dbg !12 { +entry: + %Var1 = alloca i1 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var1, metadata !16, metadata !DIExpression(DW_OP_deref)), !dbg !18 + call void @Esc(ptr %Var1), !dbg !18 + ret void, !dbg !18 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1) +; CHECK-NEXT: DW_AT_name ("Var2") +define dso_local void @Fun2() #0 !dbg !19 { +entry: + %Var2 = alloca i4 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var2, metadata !23, metadata !DIExpression()), !dbg !25 + call void @Esc(ptr %Var2), !dbg !25 + ret void, !dbg !25 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var3") +define dso_local void @Fun3() #0 !dbg !26 { +entry: + %Var3 = alloca i4 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var3, metadata !30, metadata !DIExpression(DW_OP_deref)), !dbg !32 + call void @Esc(ptr %Var3), !dbg !32 + ret void, !dbg !32 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1) +; CHECK-NEXT: DW_AT_name ("Var4") +define dso_local void @Fun4() #0 !dbg !33 { +entry: + %Var4 = alloca i8 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var4, metadata !37, metadata !DIExpression()), !dbg !39 + call void @Esc(ptr %Var4), !dbg !39 + ret void, !dbg !39 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var5") +define dso_local void @Fun5() #0 !dbg !40 { +entry: + %Var5 = alloca i8 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var5, metadata !44, metadata !DIExpression(DW_OP_deref)), !dbg !46 + call void @Esc(ptr %Var5), !dbg !46 + ret void, !dbg !46 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2) +; CHECK-NEXT: DW_AT_name ("Var6") +define dso_local void @Fun6() #0 !dbg !47 { +entry: + %Var6 = alloca i16 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var6, metadata !51, metadata !DIExpression()), !dbg !53 + call void @Esc(ptr %Var6), !dbg !53 + ret void, !dbg !53 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var7") +define dso_local void @Fun7() #0 !dbg !54 { +entry: + %Var7 = alloca i16 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var7, metadata !58, metadata !DIExpression(DW_OP_deref)), !dbg !60 + call void @Esc(ptr %Var7), !dbg !60 + ret void, !dbg !60 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4) +; CHECK-NEXT: DW_AT_name ("Var8") +define dso_local void @Fun8() #0 !dbg !61 { +entry: + %Var8 = alloca i17 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var8, metadata !65, metadata !DIExpression()), !dbg !67 + call void @Esc(ptr %Var8), !dbg !67 + ret void, !dbg !67 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var9") +define dso_local void @Fun9() #0 !dbg !68 { +entry: + %Var9 = alloca i17 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var9, metadata !72, metadata !DIExpression(DW_OP_deref)), !dbg !74 + call void @Esc(ptr %Var9), !dbg !74 + ret void, !dbg !74 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4) +; CHECK-NEXT: DW_AT_name ("Var10") +define dso_local void @Fun10() #0 !dbg !75 { +entry: + %Var10 = alloca i32 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var10, metadata !79, metadata !DIExpression()), !dbg !81 + call void @Esc(ptr %Var10), !dbg !81 + ret void, !dbg !81 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var11") +define dso_local void @Fun11() #0 !dbg !82 { +entry: + %Var11 = alloca i32 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var11, metadata !86, metadata !DIExpression(DW_OP_deref)), !dbg !88 + call void @Esc(ptr %Var11), !dbg !88 + ret void, !dbg !88 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8) +; CHECK-NEXT: DW_AT_name ("Var12") +define dso_local void @Fun12() #0 !dbg !89 { +entry: + %Var12 = alloca i64 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var12, metadata !93, metadata !DIExpression()), !dbg !95 + call void @Esc(ptr %Var12), !dbg !95 + ret void, !dbg !95 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var13") +define dso_local void @Fun13() #0 !dbg !96 { +entry: + %Var13 = alloca i64 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var13, metadata !100, metadata !DIExpression(DW_OP_deref)), !dbg !102 + call void @Esc(ptr %Var13), !dbg !102 + ret void, !dbg !102 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16) +; CHECK-NEXT: DW_AT_name ("Var14") +define dso_local void @Fun14() #0 !dbg !103 { +entry: + %Var14 = alloca i128 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var14, metadata !107, metadata !DIExpression()), !dbg !109 + call void @Esc(ptr %Var14), !dbg !109 + ret void, !dbg !109 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var15") +define dso_local void @Fun15() #0 !dbg !110 { +entry: + %Var15 = alloca i128 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var15, metadata !114, metadata !DIExpression(DW_OP_deref)), !dbg !116 + call void @Esc(ptr %Var15), !dbg !116 + ret void, !dbg !116 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2) +; CHECK-NEXT: DW_AT_name ("Var16") +define dso_local void @Fun16() #0 !dbg !117 { +entry: + %Var16 = alloca half + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var16, metadata !121, metadata !DIExpression()), !dbg !123 + call void @Esc(ptr %Var16), !dbg !123 + ret void, !dbg !123 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var17") +define dso_local void @Fun17() #0 !dbg !124 { +entry: + %Var17 = alloca half + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var17, metadata !128, metadata !DIExpression(DW_OP_deref)), !dbg !130 + call void @Esc(ptr %Var17), !dbg !130 + ret void, !dbg !130 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2) +; CHECK-NEXT: DW_AT_name ("Var18") +define dso_local void @Fun18() #0 !dbg !131 { +entry: + %Var18 = alloca bfloat + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var18, metadata !135, metadata !DIExpression()), !dbg !137 + call void @Esc(ptr %Var18), !dbg !137 + ret void, !dbg !137 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var19") +define dso_local void @Fun19() #0 !dbg !138 { +entry: + %Var19 = alloca bfloat + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var19, metadata !142, metadata !DIExpression(DW_OP_deref)), !dbg !144 + call void @Esc(ptr %Var19), !dbg !144 + ret void, !dbg !144 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4) +; CHECK-NEXT: DW_AT_name ("Var20") +define dso_local void @Fun20() #0 !dbg !145 { +entry: + %Var20 = alloca float + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var20, metadata !149, metadata !DIExpression()), !dbg !151 + call void @Esc(ptr %Var20), !dbg !151 + ret void, !dbg !151 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var21") +define dso_local void @Fun21() #0 !dbg !152 { +entry: + %Var21 = alloca float + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var21, metadata !156, metadata !DIExpression(DW_OP_deref)), !dbg !158 + call void @Esc(ptr %Var21), !dbg !158 + ret void, !dbg !158 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8) +; CHECK-NEXT: DW_AT_name ("Var22") +define dso_local void @Fun22() #0 !dbg !159 { +entry: + %Var22 = alloca double + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var22, metadata !163, metadata !DIExpression()), !dbg !165 + call void @Esc(ptr %Var22), !dbg !165 + ret void, !dbg !165 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var23") +define dso_local void @Fun23() #0 !dbg !166 { +entry: + %Var23 = alloca double + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var23, metadata !170, metadata !DIExpression(DW_OP_deref)), !dbg !172 + call void @Esc(ptr %Var23), !dbg !172 + ret void, !dbg !172 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16) +; CHECK-NEXT: DW_AT_name ("Var24") +define dso_local void @Fun24() #0 !dbg !173 { +entry: + %Var24 = alloca fp128 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var24, metadata !177, metadata !DIExpression()), !dbg !179 + call void @Esc(ptr %Var24), !dbg !179 + ret void, !dbg !179 +} +; CHECK: DW_TAG_variable +; CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16, DW_OP_deref) +; CHECK-NEXT: DW_AT_name ("Var25") +define dso_local void @Fun25() #0 !dbg !180 { +entry: + %Var25 = alloca fp128 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var25, metadata !184, metadata !DIExpression(DW_OP_deref)), !dbg !186 + call void @Esc(ptr %Var25), !dbg !186 + ret void, !dbg !186 +} + +declare void @Esc(ptr) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + +!llvm.dbg.cu = !{!1} +!llvm.module.flags = !{!3, !4} + +!1 = distinct !DICompileUnit(language: DW_LANG_C11, file: !2, producer: "clang", emissionKind: FullDebug) +!2 = !DIFile(filename: "", directory: ".") +!3 = !{i32 7, !"Dwarf Version", i32 5} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = distinct !DISubprogram(name: "Fun0", scope: !2, file: !2, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !8) +!6 = !DISubroutineType(types: !7) +!7 = !{null} +!8 = !{} +!9 = !DILocalVariable(name: "Var0", scope: !5, file: !2, line: 1, type: !10) +!10 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!11 = !DILocation(scope: !5) +!12 = distinct !DISubprogram(name: "Fun1", scope: !2, file: !2, line: 1, type: !13, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !15) +!13 = !DISubroutineType(types: !14) +!14 = !{null} +!15 = !{} +!16 = !DILocalVariable(name: "Var1", scope: !12, file: !2, line: 1, type: !17) +!17 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!18 = !DILocation(scope: !12) +!19 = distinct !DISubprogram(name: "Fun2", scope: !2, file: !2, line: 1, type: !20, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !22) +!20 = !DISubroutineType(types: !21) +!21 = !{null} +!22 = !{} +!23 = !DILocalVariable(name: "Var2", scope: !19, file: !2, line: 1, type: !24) +!24 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!25 = !DILocation(scope: !19) +!26 = distinct !DISubprogram(name: "Fun3", scope: !2, file: !2, line: 1, type: !27, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !29) +!27 = !DISubroutineType(types: !28) +!28 = !{null} +!29 = !{} +!30 = !DILocalVariable(name: "Var3", scope: !26, file: !2, line: 1, type: !31) +!31 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!32 = !DILocation(scope: !26) +!33 = distinct !DISubprogram(name: "Fun4", scope: !2, file: !2, line: 1, type: !34, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !36) +!34 = !DISubroutineType(types: !35) +!35 = !{null} +!36 = !{} +!37 = !DILocalVariable(name: "Var4", scope: !33, file: !2, line: 1, type: !38) +!38 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!39 = !DILocation(scope: !33) +!40 = distinct !DISubprogram(name: "Fun5", scope: !2, file: !2, line: 1, type: !41, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !43) +!41 = !DISubroutineType(types: !42) +!42 = !{null} +!43 = !{} +!44 = !DILocalVariable(name: "Var5", scope: !40, file: !2, line: 1, type: !45) +!45 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!46 = !DILocation(scope: !40) +!47 = distinct !DISubprogram(name: "Fun6", scope: !2, file: !2, line: 1, type: !48, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !50) +!48 = !DISubroutineType(types: !49) +!49 = !{null} +!50 = !{} +!51 = !DILocalVariable(name: "Var6", scope: !47, file: !2, line: 1, type: !52) +!52 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!53 = !DILocation(scope: !47) +!54 = distinct !DISubprogram(name: "Fun7", scope: !2, file: !2, line: 1, type: !55, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !57) +!55 = !DISubroutineType(types: !56) +!56 = !{null} +!57 = !{} +!58 = !DILocalVariable(name: "Var7", scope: !54, file: !2, line: 1, type: !59) +!59 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!60 = !DILocation(scope: !54) +!61 = distinct !DISubprogram(name: "Fun8", scope: !2, file: !2, line: 1, type: !62, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !64) +!62 = !DISubroutineType(types: !63) +!63 = !{null} +!64 = !{} +!65 = !DILocalVariable(name: "Var8", scope: !61, file: !2, line: 1, type: !66) +!66 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!67 = !DILocation(scope: !61) +!68 = distinct !DISubprogram(name: "Fun9", scope: !2, file: !2, line: 1, type: !69, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !71) +!69 = !DISubroutineType(types: !70) +!70 = !{null} +!71 = !{} +!72 = !DILocalVariable(name: "Var9", scope: !68, file: !2, line: 1, type: !73) +!73 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!74 = !DILocation(scope: !68) +!75 = distinct !DISubprogram(name: "Fun10", scope: !2, file: !2, line: 1, type: !76, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !78) +!76 = !DISubroutineType(types: !77) +!77 = !{null} +!78 = !{} +!79 = !DILocalVariable(name: "Var10", scope: !75, file: !2, line: 1, type: !80) +!80 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!81 = !DILocation(scope: !75) +!82 = distinct !DISubprogram(name: "Fun11", scope: !2, file: !2, line: 1, type: !83, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !85) +!83 = !DISubroutineType(types: !84) +!84 = !{null} +!85 = !{} +!86 = !DILocalVariable(name: "Var11", scope: !82, file: !2, line: 1, type: !87) +!87 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!88 = !DILocation(scope: !82) +!89 = distinct !DISubprogram(name: "Fun12", scope: !2, file: !2, line: 1, type: !90, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !92) +!90 = !DISubroutineType(types: !91) +!91 = !{null} +!92 = !{} +!93 = !DILocalVariable(name: "Var12", scope: !89, file: !2, line: 1, type: !94) +!94 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!95 = !DILocation(scope: !89) +!96 = distinct !DISubprogram(name: "Fun13", scope: !2, file: !2, line: 1, type: !97, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !99) +!97 = !DISubroutineType(types: !98) +!98 = !{null} +!99 = !{} +!100 = !DILocalVariable(name: "Var13", scope: !96, file: !2, line: 1, type: !101) +!101 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!102 = !DILocation(scope: !96) +!103 = distinct !DISubprogram(name: "Fun14", scope: !2, file: !2, line: 1, type: !104, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !106) +!104 = !DISubroutineType(types: !105) +!105 = !{null} +!106 = !{} +!107 = !DILocalVariable(name: "Var14", scope: !103, file: !2, line: 1, type: !108) +!108 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!109 = !DILocation(scope: !103) +!110 = distinct !DISubprogram(name: "Fun15", scope: !2, file: !2, line: 1, type: !111, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !113) +!111 = !DISubroutineType(types: !112) +!112 = !{null} +!113 = !{} +!114 = !DILocalVariable(name: "Var15", scope: !110, file: !2, line: 1, type: !115) +!115 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!116 = !DILocation(scope: !110) +!117 = distinct !DISubprogram(name: "Fun16", scope: !2, file: !2, line: 1, type: !118, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !120) +!118 = !DISubroutineType(types: !119) +!119 = !{null} +!120 = !{} +!121 = !DILocalVariable(name: "Var16", scope: !117, file: !2, line: 1, type: !122) +!122 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!123 = !DILocation(scope: !117) +!124 = distinct !DISubprogram(name: "Fun17", scope: !2, file: !2, line: 1, type: !125, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !127) +!125 = !DISubroutineType(types: !126) +!126 = !{null} +!127 = !{} +!128 = !DILocalVariable(name: "Var17", scope: !124, file: !2, line: 1, type: !129) +!129 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!130 = !DILocation(scope: !124) +!131 = distinct !DISubprogram(name: "Fun18", scope: !2, file: !2, line: 1, type: !132, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !134) +!132 = !DISubroutineType(types: !133) +!133 = !{null} +!134 = !{} +!135 = !DILocalVariable(name: "Var18", scope: !131, file: !2, line: 1, type: !136) +!136 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!137 = !DILocation(scope: !131) +!138 = distinct !DISubprogram(name: "Fun19", scope: !2, file: !2, line: 1, type: !139, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !141) +!139 = !DISubroutineType(types: !140) +!140 = !{null} +!141 = !{} +!142 = !DILocalVariable(name: "Var19", scope: !138, file: !2, line: 1, type: !143) +!143 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!144 = !DILocation(scope: !138) +!145 = distinct !DISubprogram(name: "Fun20", scope: !2, file: !2, line: 1, type: !146, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !148) +!146 = !DISubroutineType(types: !147) +!147 = !{null} +!148 = !{} +!149 = !DILocalVariable(name: "Var20", scope: !145, file: !2, line: 1, type: !150) +!150 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!151 = !DILocation(scope: !145) +!152 = distinct !DISubprogram(name: "Fun21", scope: !2, file: !2, line: 1, type: !153, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !155) +!153 = !DISubroutineType(types: !154) +!154 = !{null} +!155 = !{} +!156 = !DILocalVariable(name: "Var21", scope: !152, file: !2, line: 1, type: !157) +!157 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!158 = !DILocation(scope: !152) +!159 = distinct !DISubprogram(name: "Fun22", scope: !2, file: !2, line: 1, type: !160, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !162) +!160 = !DISubroutineType(types: !161) +!161 = !{null} +!162 = !{} +!163 = !DILocalVariable(name: "Var22", scope: !159, file: !2, line: 1, type: !164) +!164 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!165 = !DILocation(scope: !159) +!166 = distinct !DISubprogram(name: "Fun23", scope: !2, file: !2, line: 1, type: !167, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !169) +!167 = !DISubroutineType(types: !168) +!168 = !{null} +!169 = !{} +!170 = !DILocalVariable(name: "Var23", scope: !166, file: !2, line: 1, type: !171) +!171 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!172 = !DILocation(scope: !166) +!173 = distinct !DISubprogram(name: "Fun24", scope: !2, file: !2, line: 1, type: !174, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !176) +!174 = !DISubroutineType(types: !175) +!175 = !{null} +!176 = !{} +!177 = !DILocalVariable(name: "Var24", scope: !173, file: !2, line: 1, type: !178) +!178 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!179 = !DILocation(scope: !173) +!180 = distinct !DISubprogram(name: "Fun25", scope: !2, file: !2, line: 1, type: !181, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !183) +!181 = !DISubroutineType(types: !182) +!182 = !{null} +!183 = !{} +!184 = !DILocalVariable(name: "Var25", scope: !180, file: !2, line: 1, type: !185) +!185 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) +!186 = !DILocation(scope: !180) + +#--- mir +# RUN: llc -x mir -O0 -start-after=x86-isel -filetype=obj < %t/mir | llvm-dwarfdump --diff --debug-info -name Var* -regex - | FileCheck %t/mir +--- | + source_filename = "-" + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + target triple = "x86_64-unknown-linux-gnu" + + define dso_local void @Fun26() #0 !dbg !5 { + entry: + %Var26 = alloca i1 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var26, metadata !9, metadata !DIExpression()), !dbg !11 + call void @Esc(ptr %Var26), !dbg !11 + ret void, !dbg !11 + } + define dso_local void @Fun27() #0 !dbg !12 { + entry: + %Var27 = alloca i1 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var27, metadata !16, metadata !DIExpression(DW_OP_deref)), !dbg !18 + call void @Esc(ptr %Var27), !dbg !18 + ret void, !dbg !18 + } + define dso_local void @Fun28() #0 !dbg !19 { + entry: + %Var28 = alloca i1 + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var28, metadata !23, metadata !DIExpression(DW_OP_stack_value)), !dbg !25 + call void @Esc(ptr %Var28), !dbg !25 + ret void, !dbg !25 + } + define dso_local void @Fun29() #0 !dbg !26 { + entry: + %Var29 = alloca i1 + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var29, metadata !30, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !32 + call void @Esc(ptr %Var29), !dbg !32 + ret void, !dbg !32 + } + define dso_local void @Fun30() #0 !dbg !33 { + entry: + %Var30 = alloca i4 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var30, metadata !37, metadata !DIExpression()), !dbg !39 + call void @Esc(ptr %Var30), !dbg !39 + ret void, !dbg !39 + } + define dso_local void @Fun31() #0 !dbg !40 { + entry: + %Var31 = alloca i4 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var31, metadata !44, metadata !DIExpression(DW_OP_deref)), !dbg !46 + call void @Esc(ptr %Var31), !dbg !46 + ret void, !dbg !46 + } + define dso_local void @Fun32() #0 !dbg !47 { + entry: + %Var32 = alloca i4 + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var32, metadata !51, metadata !DIExpression(DW_OP_stack_value)), !dbg !53 + call void @Esc(ptr %Var32), !dbg !53 + ret void, !dbg !53 + } + define dso_local void @Fun33() #0 !dbg !54 { + entry: + %Var33 = alloca i4 + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var33, metadata !58, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !60 + call void @Esc(ptr %Var33), !dbg !60 + ret void, !dbg !60 + } + define dso_local void @Fun34() #0 !dbg !61 { + entry: + %Var34 = alloca i8 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var34, metadata !65, metadata !DIExpression()), !dbg !67 + call void @Esc(ptr %Var34), !dbg !67 + ret void, !dbg !67 + } + define dso_local void @Fun35() #0 !dbg !68 { + entry: + %Var35 = alloca i8 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var35, metadata !72, metadata !DIExpression(DW_OP_deref)), !dbg !74 + call void @Esc(ptr %Var35), !dbg !74 + ret void, !dbg !74 + } + define dso_local void @Fun36() #0 !dbg !75 { + entry: + %Var36 = alloca i8 + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var36, metadata !79, metadata !DIExpression(DW_OP_stack_value)), !dbg !81 + call void @Esc(ptr %Var36), !dbg !81 + ret void, !dbg !81 + } + define dso_local void @Fun37() #0 !dbg !82 { + entry: + %Var37 = alloca i8 + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var37, metadata !86, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !88 + call void @Esc(ptr %Var37), !dbg !88 + ret void, !dbg !88 + } + define dso_local void @Fun38() #0 !dbg !89 { + entry: + %Var38 = alloca i16 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var38, metadata !93, metadata !DIExpression()), !dbg !95 + call void @Esc(ptr %Var38), !dbg !95 + ret void, !dbg !95 + } + define dso_local void @Fun39() #0 !dbg !96 { + entry: + %Var39 = alloca i16 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var39, metadata !100, metadata !DIExpression(DW_OP_deref)), !dbg !102 + call void @Esc(ptr %Var39), !dbg !102 + ret void, !dbg !102 + } + define dso_local void @Fun40() #0 !dbg !103 { + entry: + %Var40 = alloca i16 + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var40, metadata !107, metadata !DIExpression(DW_OP_stack_value)), !dbg !109 + call void @Esc(ptr %Var40), !dbg !109 + ret void, !dbg !109 + } + define dso_local void @Fun41() #0 !dbg !110 { + entry: + %Var41 = alloca i16 + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var41, metadata !114, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !116 + call void @Esc(ptr %Var41), !dbg !116 + ret void, !dbg !116 + } + define dso_local void @Fun42() #0 !dbg !117 { + entry: + %Var42 = alloca i17 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var42, metadata !121, metadata !DIExpression()), !dbg !123 + call void @Esc(ptr %Var42), !dbg !123 + ret void, !dbg !123 + } + define dso_local void @Fun43() #0 !dbg !124 { + entry: + %Var43 = alloca i17 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var43, metadata !128, metadata !DIExpression(DW_OP_deref)), !dbg !130 + call void @Esc(ptr %Var43), !dbg !130 + ret void, !dbg !130 + } + define dso_local void @Fun44() #0 !dbg !131 { + entry: + %Var44 = alloca i17 + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var44, metadata !135, metadata !DIExpression(DW_OP_stack_value)), !dbg !137 + call void @Esc(ptr %Var44), !dbg !137 + ret void, !dbg !137 + } + define dso_local void @Fun45() #0 !dbg !138 { + entry: + %Var45 = alloca i17 + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var45, metadata !142, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !144 + call void @Esc(ptr %Var45), !dbg !144 + ret void, !dbg !144 + } + define dso_local void @Fun46() #0 !dbg !145 { + entry: + %Var46 = alloca i32 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var46, metadata !149, metadata !DIExpression()), !dbg !151 + call void @Esc(ptr %Var46), !dbg !151 + ret void, !dbg !151 + } + define dso_local void @Fun47() #0 !dbg !152 { + entry: + %Var47 = alloca i32 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var47, metadata !156, metadata !DIExpression(DW_OP_deref)), !dbg !158 + call void @Esc(ptr %Var47), !dbg !158 + ret void, !dbg !158 + } + define dso_local void @Fun48() #0 !dbg !159 { + entry: + %Var48 = alloca i32 + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var48, metadata !163, metadata !DIExpression(DW_OP_stack_value)), !dbg !165 + call void @Esc(ptr %Var48), !dbg !165 + ret void, !dbg !165 + } + define dso_local void @Fun49() #0 !dbg !166 { + entry: + %Var49 = alloca i32 + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var49, metadata !170, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !172 + call void @Esc(ptr %Var49), !dbg !172 + ret void, !dbg !172 + } + define dso_local void @Fun50() #0 !dbg !173 { + entry: + %Var50 = alloca i64 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var50, metadata !177, metadata !DIExpression()), !dbg !179 + call void @Esc(ptr %Var50), !dbg !179 + ret void, !dbg !179 + } + define dso_local void @Fun51() #0 !dbg !180 { + entry: + %Var51 = alloca i64 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var51, metadata !184, metadata !DIExpression(DW_OP_deref)), !dbg !186 + call void @Esc(ptr %Var51), !dbg !186 + ret void, !dbg !186 + } + define dso_local void @Fun52() #0 !dbg !187 { + entry: + %Var52 = alloca i64 + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var52, metadata !191, metadata !DIExpression(DW_OP_stack_value)), !dbg !193 + call void @Esc(ptr %Var52), !dbg !193 + ret void, !dbg !193 + } + define dso_local void @Fun53() #0 !dbg !194 { + entry: + %Var53 = alloca i64 + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var53, metadata !198, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !200 + call void @Esc(ptr %Var53), !dbg !200 + ret void, !dbg !200 + } + define dso_local void @Fun54() #0 !dbg !201 { + entry: + %Var54 = alloca i128 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var54, metadata !205, metadata !DIExpression()), !dbg !207 + call void @Esc(ptr %Var54), !dbg !207 + ret void, !dbg !207 + } + define dso_local void @Fun55() #0 !dbg !208 { + entry: + %Var55 = alloca i128 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var55, metadata !212, metadata !DIExpression(DW_OP_deref)), !dbg !214 + call void @Esc(ptr %Var55), !dbg !214 + ret void, !dbg !214 + } + define dso_local void @Fun56() #0 !dbg !215 { + entry: + %Var56 = alloca i128 + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var56, metadata !219, metadata !DIExpression(DW_OP_stack_value)), !dbg !221 + call void @Esc(ptr %Var56), !dbg !221 + ret void, !dbg !221 + } + define dso_local void @Fun57() #0 !dbg !222 { + entry: + %Var57 = alloca i128 + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var57, metadata !226, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !228 + call void @Esc(ptr %Var57), !dbg !228 + ret void, !dbg !228 + } + define dso_local void @Fun58() #0 !dbg !229 { + entry: + %Var58 = alloca half + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var58, metadata !233, metadata !DIExpression()), !dbg !235 + call void @Esc(ptr %Var58), !dbg !235 + ret void, !dbg !235 + } + define dso_local void @Fun59() #0 !dbg !236 { + entry: + %Var59 = alloca half + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var59, metadata !240, metadata !DIExpression(DW_OP_deref)), !dbg !242 + call void @Esc(ptr %Var59), !dbg !242 + ret void, !dbg !242 + } + define dso_local void @Fun60() #0 !dbg !243 { + entry: + %Var60 = alloca half + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var60, metadata !247, metadata !DIExpression(DW_OP_stack_value)), !dbg !249 + call void @Esc(ptr %Var60), !dbg !249 + ret void, !dbg !249 + } + define dso_local void @Fun61() #0 !dbg !250 { + entry: + %Var61 = alloca half + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var61, metadata !254, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !256 + call void @Esc(ptr %Var61), !dbg !256 + ret void, !dbg !256 + } + define dso_local void @Fun62() #0 !dbg !257 { + entry: + %Var62 = alloca bfloat + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var62, metadata !261, metadata !DIExpression()), !dbg !263 + call void @Esc(ptr %Var62), !dbg !263 + ret void, !dbg !263 + } + define dso_local void @Fun63() #0 !dbg !264 { + entry: + %Var63 = alloca bfloat + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var63, metadata !268, metadata !DIExpression(DW_OP_deref)), !dbg !270 + call void @Esc(ptr %Var63), !dbg !270 + ret void, !dbg !270 + } + define dso_local void @Fun64() #0 !dbg !271 { + entry: + %Var64 = alloca bfloat + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var64, metadata !275, metadata !DIExpression(DW_OP_stack_value)), !dbg !277 + call void @Esc(ptr %Var64), !dbg !277 + ret void, !dbg !277 + } + define dso_local void @Fun65() #0 !dbg !278 { + entry: + %Var65 = alloca bfloat + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var65, metadata !282, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !284 + call void @Esc(ptr %Var65), !dbg !284 + ret void, !dbg !284 + } + define dso_local void @Fun66() #0 !dbg !285 { + entry: + %Var66 = alloca float + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var66, metadata !289, metadata !DIExpression()), !dbg !291 + call void @Esc(ptr %Var66), !dbg !291 + ret void, !dbg !291 + } + define dso_local void @Fun67() #0 !dbg !292 { + entry: + %Var67 = alloca float + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var67, metadata !296, metadata !DIExpression(DW_OP_deref)), !dbg !298 + call void @Esc(ptr %Var67), !dbg !298 + ret void, !dbg !298 + } + define dso_local void @Fun68() #0 !dbg !299 { + entry: + %Var68 = alloca float + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var68, metadata !303, metadata !DIExpression(DW_OP_stack_value)), !dbg !305 + call void @Esc(ptr %Var68), !dbg !305 + ret void, !dbg !305 + } + define dso_local void @Fun69() #0 !dbg !306 { + entry: + %Var69 = alloca float + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var69, metadata !310, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !312 + call void @Esc(ptr %Var69), !dbg !312 + ret void, !dbg !312 + } + define dso_local void @Fun70() #0 !dbg !313 { + entry: + %Var70 = alloca double + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var70, metadata !317, metadata !DIExpression()), !dbg !319 + call void @Esc(ptr %Var70), !dbg !319 + ret void, !dbg !319 + } + define dso_local void @Fun71() #0 !dbg !320 { + entry: + %Var71 = alloca double + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var71, metadata !324, metadata !DIExpression(DW_OP_deref)), !dbg !326 + call void @Esc(ptr %Var71), !dbg !326 + ret void, !dbg !326 + } + define dso_local void @Fun72() #0 !dbg !327 { + entry: + %Var72 = alloca double + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var72, metadata !331, metadata !DIExpression(DW_OP_stack_value)), !dbg !333 + call void @Esc(ptr %Var72), !dbg !333 + ret void, !dbg !333 + } + define dso_local void @Fun73() #0 !dbg !334 { + entry: + %Var73 = alloca double + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var73, metadata !338, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !340 + call void @Esc(ptr %Var73), !dbg !340 + ret void, !dbg !340 + } + define dso_local void @Fun74() #0 !dbg !341 { + entry: + %Var74 = alloca fp128 + ; DIExpression() + call void @llvm.dbg.declare(metadata ptr %Var74, metadata !345, metadata !DIExpression()), !dbg !347 + call void @Esc(ptr %Var74), !dbg !347 + ret void, !dbg !347 + } + define dso_local void @Fun75() #0 !dbg !348 { + entry: + %Var75 = alloca fp128 + ; DIExpression(DW_OP_deref) + call void @llvm.dbg.declare(metadata ptr %Var75, metadata !352, metadata !DIExpression(DW_OP_deref)), !dbg !354 + call void @Esc(ptr %Var75), !dbg !354 + ret void, !dbg !354 + } + define dso_local void @Fun76() #0 !dbg !355 { + entry: + %Var76 = alloca fp128 + ; DIExpression(DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var76, metadata !359, metadata !DIExpression(DW_OP_stack_value)), !dbg !361 + call void @Esc(ptr %Var76), !dbg !361 + ret void, !dbg !361 + } + define dso_local void @Fun77() #0 !dbg !362 { + entry: + %Var77 = alloca fp128 + ; DIExpression(DW_OP_deref, DW_OP_stack_value) + call void @llvm.dbg.declare(metadata ptr %Var77, metadata !366, metadata !DIExpression(DW_OP_deref, DW_OP_stack_value)), !dbg !368 + call void @Esc(ptr %Var77), !dbg !368 + ret void, !dbg !368 + } + define dso_local void @Fun78() #0 !dbg !369 { + entry: + ret void, !dbg !375 + } + define dso_local void @Fun79() #0 !dbg !376 { + entry: + ret void, !dbg !382 + } + define dso_local void @Fun80() #0 !dbg !383 { + entry: + ret void, !dbg !389 + } + define dso_local void @Fun81() #0 !dbg !390 { + entry: + ret void, !dbg !396 + } + define dso_local void @Fun82() #0 !dbg !397 { + entry: + ret void, !dbg !403 + } + define dso_local void @Fun83() #0 !dbg !404 { + entry: + ret void, !dbg !410 + } + define dso_local void @Fun84() #0 !dbg !411 { + entry: + ret void, !dbg !417 + } + define dso_local void @Fun85() #0 !dbg !418 { + entry: + ret void, !dbg !424 + } + define dso_local void @Fun86() #0 !dbg !425 { + entry: + ret void, !dbg !431 + } + define dso_local void @Fun87() #0 !dbg !432 { + entry: + ret void, !dbg !438 + } + define dso_local void @Fun88() #0 !dbg !439 { + entry: + ret void, !dbg !445 + } + define dso_local void @Fun89() #0 !dbg !446 { + entry: + ret void, !dbg !452 + } + define dso_local void @Fun90() #0 !dbg !453 { + entry: + ret void, !dbg !459 + } + define dso_local void @Fun91() #0 !dbg !460 { + entry: + ret void, !dbg !466 + } + define dso_local void @Fun92() #0 !dbg !467 { + entry: + ret void, !dbg !473 + } + define dso_local void @Fun93() #0 !dbg !474 { + entry: + ret void, !dbg !480 + } + define dso_local void @Fun94() #0 !dbg !481 { + entry: + ret void, !dbg !487 + } + define dso_local void @Fun95() #0 !dbg !488 { + entry: + ret void, !dbg !494 + } + define dso_local void @Fun96() #0 !dbg !495 { + entry: + ret void, !dbg !501 + } + define dso_local void @Fun97() #0 !dbg !502 { + entry: + ret void, !dbg !508 + } + define dso_local void @Fun98() #0 !dbg !509 { + entry: + ret void, !dbg !515 + } + define dso_local void @Fun99() #0 !dbg !516 { + entry: + ret void, !dbg !522 + } + define dso_local void @Fun100() #0 !dbg !523 { + entry: + ret void, !dbg !529 + } + define dso_local void @Fun101() #0 !dbg !530 { + entry: + ret void, !dbg !536 + } + define dso_local void @Fun102() #0 !dbg !537 { + entry: + ret void, !dbg !543 + } + define dso_local void @Fun103() #0 !dbg !544 { + entry: + ret void, !dbg !550 + } + + declare void @Esc(ptr) + declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + + attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + attributes #2 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + + !llvm.dbg.cu = !{!1} + !llvm.module.flags = !{!3, !4} + + !1 = distinct !DICompileUnit(language: DW_LANG_C11, file: !2, producer: "clang", emissionKind: FullDebug) + !2 = !DIFile(filename: "", directory: ".") + !3 = !{i32 7, !"Dwarf Version", i32 5} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = distinct !DISubprogram(name: "Fun26", scope: !2, file: !2, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !8) + !6 = !DISubroutineType(types: !7) + !7 = !{null} + !8 = !{} + !9 = !DILocalVariable(name: "Var26", scope: !5, file: !2, line: 1, type: !10) + !10 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !11 = !DILocation(scope: !5) + !12 = distinct !DISubprogram(name: "Fun27", scope: !2, file: !2, line: 1, type: !13, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !15) + !13 = !DISubroutineType(types: !14) + !14 = !{null} + !15 = !{} + !16 = !DILocalVariable(name: "Var27", scope: !12, file: !2, line: 1, type: !17) + !17 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !18 = !DILocation(scope: !12) + !19 = distinct !DISubprogram(name: "Fun28", scope: !2, file: !2, line: 1, type: !20, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !22) + !20 = !DISubroutineType(types: !21) + !21 = !{null} + !22 = !{} + !23 = !DILocalVariable(name: "Var28", scope: !19, file: !2, line: 1, type: !24) + !24 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !25 = !DILocation(scope: !19) + !26 = distinct !DISubprogram(name: "Fun29", scope: !2, file: !2, line: 1, type: !27, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !29) + !27 = !DISubroutineType(types: !28) + !28 = !{null} + !29 = !{} + !30 = !DILocalVariable(name: "Var29", scope: !26, file: !2, line: 1, type: !31) + !31 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !32 = !DILocation(scope: !26) + !33 = distinct !DISubprogram(name: "Fun30", scope: !2, file: !2, line: 1, type: !34, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !36) + !34 = !DISubroutineType(types: !35) + !35 = !{null} + !36 = !{} + !37 = !DILocalVariable(name: "Var30", scope: !33, file: !2, line: 1, type: !38) + !38 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !39 = !DILocation(scope: !33) + !40 = distinct !DISubprogram(name: "Fun31", scope: !2, file: !2, line: 1, type: !41, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !43) + !41 = !DISubroutineType(types: !42) + !42 = !{null} + !43 = !{} + !44 = !DILocalVariable(name: "Var31", scope: !40, file: !2, line: 1, type: !45) + !45 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !46 = !DILocation(scope: !40) + !47 = distinct !DISubprogram(name: "Fun32", scope: !2, file: !2, line: 1, type: !48, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !50) + !48 = !DISubroutineType(types: !49) + !49 = !{null} + !50 = !{} + !51 = !DILocalVariable(name: "Var32", scope: !47, file: !2, line: 1, type: !52) + !52 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !53 = !DILocation(scope: !47) + !54 = distinct !DISubprogram(name: "Fun33", scope: !2, file: !2, line: 1, type: !55, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !57) + !55 = !DISubroutineType(types: !56) + !56 = !{null} + !57 = !{} + !58 = !DILocalVariable(name: "Var33", scope: !54, file: !2, line: 1, type: !59) + !59 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !60 = !DILocation(scope: !54) + !61 = distinct !DISubprogram(name: "Fun34", scope: !2, file: !2, line: 1, type: !62, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !64) + !62 = !DISubroutineType(types: !63) + !63 = !{null} + !64 = !{} + !65 = !DILocalVariable(name: "Var34", scope: !61, file: !2, line: 1, type: !66) + !66 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !67 = !DILocation(scope: !61) + !68 = distinct !DISubprogram(name: "Fun35", scope: !2, file: !2, line: 1, type: !69, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !71) + !69 = !DISubroutineType(types: !70) + !70 = !{null} + !71 = !{} + !72 = !DILocalVariable(name: "Var35", scope: !68, file: !2, line: 1, type: !73) + !73 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !74 = !DILocation(scope: !68) + !75 = distinct !DISubprogram(name: "Fun36", scope: !2, file: !2, line: 1, type: !76, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !78) + !76 = !DISubroutineType(types: !77) + !77 = !{null} + !78 = !{} + !79 = !DILocalVariable(name: "Var36", scope: !75, file: !2, line: 1, type: !80) + !80 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !81 = !DILocation(scope: !75) + !82 = distinct !DISubprogram(name: "Fun37", scope: !2, file: !2, line: 1, type: !83, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !85) + !83 = !DISubroutineType(types: !84) + !84 = !{null} + !85 = !{} + !86 = !DILocalVariable(name: "Var37", scope: !82, file: !2, line: 1, type: !87) + !87 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !88 = !DILocation(scope: !82) + !89 = distinct !DISubprogram(name: "Fun38", scope: !2, file: !2, line: 1, type: !90, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !92) + !90 = !DISubroutineType(types: !91) + !91 = !{null} + !92 = !{} + !93 = !DILocalVariable(name: "Var38", scope: !89, file: !2, line: 1, type: !94) + !94 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !95 = !DILocation(scope: !89) + !96 = distinct !DISubprogram(name: "Fun39", scope: !2, file: !2, line: 1, type: !97, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !99) + !97 = !DISubroutineType(types: !98) + !98 = !{null} + !99 = !{} + !100 = !DILocalVariable(name: "Var39", scope: !96, file: !2, line: 1, type: !101) + !101 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !102 = !DILocation(scope: !96) + !103 = distinct !DISubprogram(name: "Fun40", scope: !2, file: !2, line: 1, type: !104, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !106) + !104 = !DISubroutineType(types: !105) + !105 = !{null} + !106 = !{} + !107 = !DILocalVariable(name: "Var40", scope: !103, file: !2, line: 1, type: !108) + !108 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !109 = !DILocation(scope: !103) + !110 = distinct !DISubprogram(name: "Fun41", scope: !2, file: !2, line: 1, type: !111, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !113) + !111 = !DISubroutineType(types: !112) + !112 = !{null} + !113 = !{} + !114 = !DILocalVariable(name: "Var41", scope: !110, file: !2, line: 1, type: !115) + !115 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !116 = !DILocation(scope: !110) + !117 = distinct !DISubprogram(name: "Fun42", scope: !2, file: !2, line: 1, type: !118, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !120) + !118 = !DISubroutineType(types: !119) + !119 = !{null} + !120 = !{} + !121 = !DILocalVariable(name: "Var42", scope: !117, file: !2, line: 1, type: !122) + !122 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !123 = !DILocation(scope: !117) + !124 = distinct !DISubprogram(name: "Fun43", scope: !2, file: !2, line: 1, type: !125, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !127) + !125 = !DISubroutineType(types: !126) + !126 = !{null} + !127 = !{} + !128 = !DILocalVariable(name: "Var43", scope: !124, file: !2, line: 1, type: !129) + !129 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !130 = !DILocation(scope: !124) + !131 = distinct !DISubprogram(name: "Fun44", scope: !2, file: !2, line: 1, type: !132, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !134) + !132 = !DISubroutineType(types: !133) + !133 = !{null} + !134 = !{} + !135 = !DILocalVariable(name: "Var44", scope: !131, file: !2, line: 1, type: !136) + !136 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !137 = !DILocation(scope: !131) + !138 = distinct !DISubprogram(name: "Fun45", scope: !2, file: !2, line: 1, type: !139, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !141) + !139 = !DISubroutineType(types: !140) + !140 = !{null} + !141 = !{} + !142 = !DILocalVariable(name: "Var45", scope: !138, file: !2, line: 1, type: !143) + !143 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !144 = !DILocation(scope: !138) + !145 = distinct !DISubprogram(name: "Fun46", scope: !2, file: !2, line: 1, type: !146, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !148) + !146 = !DISubroutineType(types: !147) + !147 = !{null} + !148 = !{} + !149 = !DILocalVariable(name: "Var46", scope: !145, file: !2, line: 1, type: !150) + !150 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !151 = !DILocation(scope: !145) + !152 = distinct !DISubprogram(name: "Fun47", scope: !2, file: !2, line: 1, type: !153, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !155) + !153 = !DISubroutineType(types: !154) + !154 = !{null} + !155 = !{} + !156 = !DILocalVariable(name: "Var47", scope: !152, file: !2, line: 1, type: !157) + !157 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !158 = !DILocation(scope: !152) + !159 = distinct !DISubprogram(name: "Fun48", scope: !2, file: !2, line: 1, type: !160, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !162) + !160 = !DISubroutineType(types: !161) + !161 = !{null} + !162 = !{} + !163 = !DILocalVariable(name: "Var48", scope: !159, file: !2, line: 1, type: !164) + !164 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !165 = !DILocation(scope: !159) + !166 = distinct !DISubprogram(name: "Fun49", scope: !2, file: !2, line: 1, type: !167, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !169) + !167 = !DISubroutineType(types: !168) + !168 = !{null} + !169 = !{} + !170 = !DILocalVariable(name: "Var49", scope: !166, file: !2, line: 1, type: !171) + !171 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !172 = !DILocation(scope: !166) + !173 = distinct !DISubprogram(name: "Fun50", scope: !2, file: !2, line: 1, type: !174, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !176) + !174 = !DISubroutineType(types: !175) + !175 = !{null} + !176 = !{} + !177 = !DILocalVariable(name: "Var50", scope: !173, file: !2, line: 1, type: !178) + !178 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !179 = !DILocation(scope: !173) + !180 = distinct !DISubprogram(name: "Fun51", scope: !2, file: !2, line: 1, type: !181, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !183) + !181 = !DISubroutineType(types: !182) + !182 = !{null} + !183 = !{} + !184 = !DILocalVariable(name: "Var51", scope: !180, file: !2, line: 1, type: !185) + !185 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !186 = !DILocation(scope: !180) + !187 = distinct !DISubprogram(name: "Fun52", scope: !2, file: !2, line: 1, type: !188, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !190) + !188 = !DISubroutineType(types: !189) + !189 = !{null} + !190 = !{} + !191 = !DILocalVariable(name: "Var52", scope: !187, file: !2, line: 1, type: !192) + !192 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !193 = !DILocation(scope: !187) + !194 = distinct !DISubprogram(name: "Fun53", scope: !2, file: !2, line: 1, type: !195, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !197) + !195 = !DISubroutineType(types: !196) + !196 = !{null} + !197 = !{} + !198 = !DILocalVariable(name: "Var53", scope: !194, file: !2, line: 1, type: !199) + !199 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !200 = !DILocation(scope: !194) + !201 = distinct !DISubprogram(name: "Fun54", scope: !2, file: !2, line: 1, type: !202, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !204) + !202 = !DISubroutineType(types: !203) + !203 = !{null} + !204 = !{} + !205 = !DILocalVariable(name: "Var54", scope: !201, file: !2, line: 1, type: !206) + !206 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !207 = !DILocation(scope: !201) + !208 = distinct !DISubprogram(name: "Fun55", scope: !2, file: !2, line: 1, type: !209, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !211) + !209 = !DISubroutineType(types: !210) + !210 = !{null} + !211 = !{} + !212 = !DILocalVariable(name: "Var55", scope: !208, file: !2, line: 1, type: !213) + !213 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !214 = !DILocation(scope: !208) + !215 = distinct !DISubprogram(name: "Fun56", scope: !2, file: !2, line: 1, type: !216, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !218) + !216 = !DISubroutineType(types: !217) + !217 = !{null} + !218 = !{} + !219 = !DILocalVariable(name: "Var56", scope: !215, file: !2, line: 1, type: !220) + !220 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !221 = !DILocation(scope: !215) + !222 = distinct !DISubprogram(name: "Fun57", scope: !2, file: !2, line: 1, type: !223, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !225) + !223 = !DISubroutineType(types: !224) + !224 = !{null} + !225 = !{} + !226 = !DILocalVariable(name: "Var57", scope: !222, file: !2, line: 1, type: !227) + !227 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !228 = !DILocation(scope: !222) + !229 = distinct !DISubprogram(name: "Fun58", scope: !2, file: !2, line: 1, type: !230, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !232) + !230 = !DISubroutineType(types: !231) + !231 = !{null} + !232 = !{} + !233 = !DILocalVariable(name: "Var58", scope: !229, file: !2, line: 1, type: !234) + !234 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !235 = !DILocation(scope: !229) + !236 = distinct !DISubprogram(name: "Fun59", scope: !2, file: !2, line: 1, type: !237, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !239) + !237 = !DISubroutineType(types: !238) + !238 = !{null} + !239 = !{} + !240 = !DILocalVariable(name: "Var59", scope: !236, file: !2, line: 1, type: !241) + !241 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !242 = !DILocation(scope: !236) + !243 = distinct !DISubprogram(name: "Fun60", scope: !2, file: !2, line: 1, type: !244, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !246) + !244 = !DISubroutineType(types: !245) + !245 = !{null} + !246 = !{} + !247 = !DILocalVariable(name: "Var60", scope: !243, file: !2, line: 1, type: !248) + !248 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !249 = !DILocation(scope: !243) + !250 = distinct !DISubprogram(name: "Fun61", scope: !2, file: !2, line: 1, type: !251, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !253) + !251 = !DISubroutineType(types: !252) + !252 = !{null} + !253 = !{} + !254 = !DILocalVariable(name: "Var61", scope: !250, file: !2, line: 1, type: !255) + !255 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !256 = !DILocation(scope: !250) + !257 = distinct !DISubprogram(name: "Fun62", scope: !2, file: !2, line: 1, type: !258, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !260) + !258 = !DISubroutineType(types: !259) + !259 = !{null} + !260 = !{} + !261 = !DILocalVariable(name: "Var62", scope: !257, file: !2, line: 1, type: !262) + !262 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !263 = !DILocation(scope: !257) + !264 = distinct !DISubprogram(name: "Fun63", scope: !2, file: !2, line: 1, type: !265, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !267) + !265 = !DISubroutineType(types: !266) + !266 = !{null} + !267 = !{} + !268 = !DILocalVariable(name: "Var63", scope: !264, file: !2, line: 1, type: !269) + !269 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !270 = !DILocation(scope: !264) + !271 = distinct !DISubprogram(name: "Fun64", scope: !2, file: !2, line: 1, type: !272, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !274) + !272 = !DISubroutineType(types: !273) + !273 = !{null} + !274 = !{} + !275 = !DILocalVariable(name: "Var64", scope: !271, file: !2, line: 1, type: !276) + !276 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !277 = !DILocation(scope: !271) + !278 = distinct !DISubprogram(name: "Fun65", scope: !2, file: !2, line: 1, type: !279, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !281) + !279 = !DISubroutineType(types: !280) + !280 = !{null} + !281 = !{} + !282 = !DILocalVariable(name: "Var65", scope: !278, file: !2, line: 1, type: !283) + !283 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !284 = !DILocation(scope: !278) + !285 = distinct !DISubprogram(name: "Fun66", scope: !2, file: !2, line: 1, type: !286, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !288) + !286 = !DISubroutineType(types: !287) + !287 = !{null} + !288 = !{} + !289 = !DILocalVariable(name: "Var66", scope: !285, file: !2, line: 1, type: !290) + !290 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !291 = !DILocation(scope: !285) + !292 = distinct !DISubprogram(name: "Fun67", scope: !2, file: !2, line: 1, type: !293, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !295) + !293 = !DISubroutineType(types: !294) + !294 = !{null} + !295 = !{} + !296 = !DILocalVariable(name: "Var67", scope: !292, file: !2, line: 1, type: !297) + !297 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !298 = !DILocation(scope: !292) + !299 = distinct !DISubprogram(name: "Fun68", scope: !2, file: !2, line: 1, type: !300, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !302) + !300 = !DISubroutineType(types: !301) + !301 = !{null} + !302 = !{} + !303 = !DILocalVariable(name: "Var68", scope: !299, file: !2, line: 1, type: !304) + !304 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !305 = !DILocation(scope: !299) + !306 = distinct !DISubprogram(name: "Fun69", scope: !2, file: !2, line: 1, type: !307, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !309) + !307 = !DISubroutineType(types: !308) + !308 = !{null} + !309 = !{} + !310 = !DILocalVariable(name: "Var69", scope: !306, file: !2, line: 1, type: !311) + !311 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !312 = !DILocation(scope: !306) + !313 = distinct !DISubprogram(name: "Fun70", scope: !2, file: !2, line: 1, type: !314, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !316) + !314 = !DISubroutineType(types: !315) + !315 = !{null} + !316 = !{} + !317 = !DILocalVariable(name: "Var70", scope: !313, file: !2, line: 1, type: !318) + !318 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !319 = !DILocation(scope: !313) + !320 = distinct !DISubprogram(name: "Fun71", scope: !2, file: !2, line: 1, type: !321, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !323) + !321 = !DISubroutineType(types: !322) + !322 = !{null} + !323 = !{} + !324 = !DILocalVariable(name: "Var71", scope: !320, file: !2, line: 1, type: !325) + !325 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !326 = !DILocation(scope: !320) + !327 = distinct !DISubprogram(name: "Fun72", scope: !2, file: !2, line: 1, type: !328, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !330) + !328 = !DISubroutineType(types: !329) + !329 = !{null} + !330 = !{} + !331 = !DILocalVariable(name: "Var72", scope: !327, file: !2, line: 1, type: !332) + !332 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !333 = !DILocation(scope: !327) + !334 = distinct !DISubprogram(name: "Fun73", scope: !2, file: !2, line: 1, type: !335, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !337) + !335 = !DISubroutineType(types: !336) + !336 = !{null} + !337 = !{} + !338 = !DILocalVariable(name: "Var73", scope: !334, file: !2, line: 1, type: !339) + !339 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !340 = !DILocation(scope: !334) + !341 = distinct !DISubprogram(name: "Fun74", scope: !2, file: !2, line: 1, type: !342, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !344) + !342 = !DISubroutineType(types: !343) + !343 = !{null} + !344 = !{} + !345 = !DILocalVariable(name: "Var74", scope: !341, file: !2, line: 1, type: !346) + !346 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !347 = !DILocation(scope: !341) + !348 = distinct !DISubprogram(name: "Fun75", scope: !2, file: !2, line: 1, type: !349, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !351) + !349 = !DISubroutineType(types: !350) + !350 = !{null} + !351 = !{} + !352 = !DILocalVariable(name: "Var75", scope: !348, file: !2, line: 1, type: !353) + !353 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !354 = !DILocation(scope: !348) + !355 = distinct !DISubprogram(name: "Fun76", scope: !2, file: !2, line: 1, type: !356, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !358) + !356 = !DISubroutineType(types: !357) + !357 = !{null} + !358 = !{} + !359 = !DILocalVariable(name: "Var76", scope: !355, file: !2, line: 1, type: !360) + !360 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !361 = !DILocation(scope: !355) + !362 = distinct !DISubprogram(name: "Fun77", scope: !2, file: !2, line: 1, type: !363, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !365) + !363 = !DISubroutineType(types: !364) + !364 = !{null} + !365 = !{} + !366 = !DILocalVariable(name: "Var77", scope: !362, file: !2, line: 1, type: !367) + !367 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !368 = !DILocation(scope: !362) + !369 = distinct !DISubprogram(name: "Fun78", scope: !2, file: !2, line: 1, type: !370, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !372) + !370 = !DISubroutineType(types: !371) + !371 = !{null} + !372 = !{} + !373 = !DILocalVariable(name: "Var78", scope: !369, file: !2, line: 1, type: !374) + !374 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !375 = !DILocation(scope: !369) + !376 = distinct !DISubprogram(name: "Fun79", scope: !2, file: !2, line: 1, type: !377, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !379) + !377 = !DISubroutineType(types: !378) + !378 = !{null} + !379 = !{} + !380 = !DILocalVariable(name: "Var79", scope: !376, file: !2, line: 1, type: !381) + !381 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !382 = !DILocation(scope: !376) + !383 = distinct !DISubprogram(name: "Fun80", scope: !2, file: !2, line: 1, type: !384, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !386) + !384 = !DISubroutineType(types: !385) + !385 = !{null} + !386 = !{} + !387 = !DILocalVariable(name: "Var80", scope: !383, file: !2, line: 1, type: !388) + !388 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !389 = !DILocation(scope: !383) + !390 = distinct !DISubprogram(name: "Fun81", scope: !2, file: !2, line: 1, type: !391, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !393) + !391 = !DISubroutineType(types: !392) + !392 = !{null} + !393 = !{} + !394 = !DILocalVariable(name: "Var81", scope: !390, file: !2, line: 1, type: !395) + !395 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !396 = !DILocation(scope: !390) + !397 = distinct !DISubprogram(name: "Fun82", scope: !2, file: !2, line: 1, type: !398, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !400) + !398 = !DISubroutineType(types: !399) + !399 = !{null} + !400 = !{} + !401 = !DILocalVariable(name: "Var82", scope: !397, file: !2, line: 1, type: !402) + !402 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !403 = !DILocation(scope: !397) + !404 = distinct !DISubprogram(name: "Fun83", scope: !2, file: !2, line: 1, type: !405, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !407) + !405 = !DISubroutineType(types: !406) + !406 = !{null} + !407 = !{} + !408 = !DILocalVariable(name: "Var83", scope: !404, file: !2, line: 1, type: !409) + !409 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !410 = !DILocation(scope: !404) + !411 = distinct !DISubprogram(name: "Fun84", scope: !2, file: !2, line: 1, type: !412, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !414) + !412 = !DISubroutineType(types: !413) + !413 = !{null} + !414 = !{} + !415 = !DILocalVariable(name: "Var84", scope: !411, file: !2, line: 1, type: !416) + !416 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !417 = !DILocation(scope: !411) + !418 = distinct !DISubprogram(name: "Fun85", scope: !2, file: !2, line: 1, type: !419, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !421) + !419 = !DISubroutineType(types: !420) + !420 = !{null} + !421 = !{} + !422 = !DILocalVariable(name: "Var85", scope: !418, file: !2, line: 1, type: !423) + !423 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !424 = !DILocation(scope: !418) + !425 = distinct !DISubprogram(name: "Fun86", scope: !2, file: !2, line: 1, type: !426, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !428) + !426 = !DISubroutineType(types: !427) + !427 = !{null} + !428 = !{} + !429 = !DILocalVariable(name: "Var86", scope: !425, file: !2, line: 1, type: !430) + !430 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !431 = !DILocation(scope: !425) + !432 = distinct !DISubprogram(name: "Fun87", scope: !2, file: !2, line: 1, type: !433, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !435) + !433 = !DISubroutineType(types: !434) + !434 = !{null} + !435 = !{} + !436 = !DILocalVariable(name: "Var87", scope: !432, file: !2, line: 1, type: !437) + !437 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !438 = !DILocation(scope: !432) + !439 = distinct !DISubprogram(name: "Fun88", scope: !2, file: !2, line: 1, type: !440, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !442) + !440 = !DISubroutineType(types: !441) + !441 = !{null} + !442 = !{} + !443 = !DILocalVariable(name: "Var88", scope: !439, file: !2, line: 1, type: !444) + !444 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !445 = !DILocation(scope: !439) + !446 = distinct !DISubprogram(name: "Fun89", scope: !2, file: !2, line: 1, type: !447, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !449) + !447 = !DISubroutineType(types: !448) + !448 = !{null} + !449 = !{} + !450 = !DILocalVariable(name: "Var89", scope: !446, file: !2, line: 1, type: !451) + !451 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !452 = !DILocation(scope: !446) + !453 = distinct !DISubprogram(name: "Fun90", scope: !2, file: !2, line: 1, type: !454, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !456) + !454 = !DISubroutineType(types: !455) + !455 = !{null} + !456 = !{} + !457 = !DILocalVariable(name: "Var90", scope: !453, file: !2, line: 1, type: !458) + !458 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !459 = !DILocation(scope: !453) + !460 = distinct !DISubprogram(name: "Fun91", scope: !2, file: !2, line: 1, type: !461, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !463) + !461 = !DISubroutineType(types: !462) + !462 = !{null} + !463 = !{} + !464 = !DILocalVariable(name: "Var91", scope: !460, file: !2, line: 1, type: !465) + !465 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !466 = !DILocation(scope: !460) + !467 = distinct !DISubprogram(name: "Fun92", scope: !2, file: !2, line: 1, type: !468, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !470) + !468 = !DISubroutineType(types: !469) + !469 = !{null} + !470 = !{} + !471 = !DILocalVariable(name: "Var92", scope: !467, file: !2, line: 1, type: !472) + !472 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !473 = !DILocation(scope: !467) + !474 = distinct !DISubprogram(name: "Fun93", scope: !2, file: !2, line: 1, type: !475, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !477) + !475 = !DISubroutineType(types: !476) + !476 = !{null} + !477 = !{} + !478 = !DILocalVariable(name: "Var93", scope: !474, file: !2, line: 1, type: !479) + !479 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !480 = !DILocation(scope: !474) + !481 = distinct !DISubprogram(name: "Fun94", scope: !2, file: !2, line: 1, type: !482, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !484) + !482 = !DISubroutineType(types: !483) + !483 = !{null} + !484 = !{} + !485 = !DILocalVariable(name: "Var94", scope: !481, file: !2, line: 1, type: !486) + !486 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !487 = !DILocation(scope: !481) + !488 = distinct !DISubprogram(name: "Fun95", scope: !2, file: !2, line: 1, type: !489, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !491) + !489 = !DISubroutineType(types: !490) + !490 = !{null} + !491 = !{} + !492 = !DILocalVariable(name: "Var95", scope: !488, file: !2, line: 1, type: !493) + !493 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !494 = !DILocation(scope: !488) + !495 = distinct !DISubprogram(name: "Fun96", scope: !2, file: !2, line: 1, type: !496, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !498) + !496 = !DISubroutineType(types: !497) + !497 = !{null} + !498 = !{} + !499 = !DILocalVariable(name: "Var96", scope: !495, file: !2, line: 1, type: !500) + !500 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !501 = !DILocation(scope: !495) + !502 = distinct !DISubprogram(name: "Fun97", scope: !2, file: !2, line: 1, type: !503, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !505) + !503 = !DISubroutineType(types: !504) + !504 = !{null} + !505 = !{} + !506 = !DILocalVariable(name: "Var97", scope: !502, file: !2, line: 1, type: !507) + !507 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !508 = !DILocation(scope: !502) + !509 = distinct !DISubprogram(name: "Fun98", scope: !2, file: !2, line: 1, type: !510, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !512) + !510 = !DISubroutineType(types: !511) + !511 = !{null} + !512 = !{} + !513 = !DILocalVariable(name: "Var98", scope: !509, file: !2, line: 1, type: !514) + !514 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !515 = !DILocation(scope: !509) + !516 = distinct !DISubprogram(name: "Fun99", scope: !2, file: !2, line: 1, type: !517, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !519) + !517 = !DISubroutineType(types: !518) + !518 = !{null} + !519 = !{} + !520 = !DILocalVariable(name: "Var99", scope: !516, file: !2, line: 1, type: !521) + !521 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !522 = !DILocation(scope: !516) + !523 = distinct !DISubprogram(name: "Fun100", scope: !2, file: !2, line: 1, type: !524, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !526) + !524 = !DISubroutineType(types: !525) + !525 = !{null} + !526 = !{} + !527 = !DILocalVariable(name: "Var100", scope: !523, file: !2, line: 1, type: !528) + !528 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !529 = !DILocation(scope: !523) + !530 = distinct !DISubprogram(name: "Fun101", scope: !2, file: !2, line: 1, type: !531, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !533) + !531 = !DISubroutineType(types: !532) + !532 = !{null} + !533 = !{} + !534 = !DILocalVariable(name: "Var101", scope: !530, file: !2, line: 1, type: !535) + !535 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !536 = !DILocation(scope: !530) + !537 = distinct !DISubprogram(name: "Fun102", scope: !2, file: !2, line: 1, type: !538, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !540) + !538 = !DISubroutineType(types: !539) + !539 = !{null} + !540 = !{} + !541 = !DILocalVariable(name: "Var102", scope: !537, file: !2, line: 1, type: !542) + !542 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !543 = !DILocation(scope: !537) + !544 = distinct !DISubprogram(name: "Fun103", scope: !2, file: !2, line: 1, type: !545, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !547) + !545 = !DISubroutineType(types: !546) + !546 = !{null} + !547 = !{} + !548 = !DILocalVariable(name: "Var103", scope: !544, file: !2, line: 1, type: !549) + !549 = !DIBasicType(name: "int", size: 42, encoding: DW_ATE_signed) + !550 = !DILocation(scope: !544) + +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1) +# CHECK-NEXT: DW_AT_name ("Var26") +--- +name: Fun26 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var26, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!9', debug-info-expression: '!DIExpression()', + debug-info-location: '!11' } +body: | + bb.0.entry: + RET64 debug-location !11 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var27") +--- +name: Fun27 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var27, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!16', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!18' } +body: | + bb.0.entry: + RET64 debug-location !18 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var28") +--- +name: Fun28 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var28, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!23', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!25' } +body: | + bb.0.entry: + RET64 debug-location !25 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var29") +--- +name: Fun29 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var29, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!30', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!32' } +body: | + bb.0.entry: + RET64 debug-location !32 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1) +# CHECK-NEXT: DW_AT_name ("Var30") +--- +name: Fun30 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var30, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!37', debug-info-expression: '!DIExpression()', + debug-info-location: '!39' } +body: | + bb.0.entry: + RET64 debug-location !39 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var31") +--- +name: Fun31 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var31, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!44', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!46' } +body: | + bb.0.entry: + RET64 debug-location !46 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var32") +--- +name: Fun32 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var32, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!51', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!53' } +body: | + bb.0.entry: + RET64 debug-location !53 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var33") +--- +name: Fun33 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var33, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!58', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!60' } +body: | + bb.0.entry: + RET64 debug-location !60 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1) +# CHECK-NEXT: DW_AT_name ("Var34") +--- +name: Fun34 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var34, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!65', debug-info-expression: '!DIExpression()', + debug-info-location: '!67' } +body: | + bb.0.entry: + RET64 debug-location !67 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var35") +--- +name: Fun35 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var35, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!72', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!74' } +body: | + bb.0.entry: + RET64 debug-location !74 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var36") +--- +name: Fun36 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var36, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!79', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!81' } +body: | + bb.0.entry: + RET64 debug-location !81 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -1, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var37") +--- +name: Fun37 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var37, type: default, offset: 0, size: 1, alignment: 1, + debug-info-variable: '!86', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!88' } +body: | + bb.0.entry: + RET64 debug-location !88 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2) +# CHECK-NEXT: DW_AT_name ("Var38") +--- +name: Fun38 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var38, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!93', debug-info-expression: '!DIExpression()', + debug-info-location: '!95' } +body: | + bb.0.entry: + RET64 debug-location !95 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var39") +--- +name: Fun39 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var39, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!100', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!102' } +body: | + bb.0.entry: + RET64 debug-location !102 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var40") +--- +name: Fun40 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var40, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!107', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!109' } +body: | + bb.0.entry: + RET64 debug-location !109 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var41") +--- +name: Fun41 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var41, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!114', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!116' } +body: | + bb.0.entry: + RET64 debug-location !116 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4) +# CHECK-NEXT: DW_AT_name ("Var42") +--- +name: Fun42 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var42, type: default, offset: 0, size: 3, alignment: 4, + debug-info-variable: '!121', debug-info-expression: '!DIExpression()', + debug-info-location: '!123' } +body: | + bb.0.entry: + RET64 debug-location !123 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var43") +--- +name: Fun43 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var43, type: default, offset: 0, size: 3, alignment: 4, + debug-info-variable: '!128', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!130' } +body: | + bb.0.entry: + RET64 debug-location !130 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var44") +--- +name: Fun44 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var44, type: default, offset: 0, size: 3, alignment: 4, + debug-info-variable: '!135', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!137' } +body: | + bb.0.entry: + RET64 debug-location !137 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var45") +--- +name: Fun45 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var45, type: default, offset: 0, size: 3, alignment: 4, + debug-info-variable: '!142', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!144' } +body: | + bb.0.entry: + RET64 debug-location !144 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4) +# CHECK-NEXT: DW_AT_name ("Var46") +--- +name: Fun46 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var46, type: default, offset: 0, size: 4, alignment: 4, + debug-info-variable: '!149', debug-info-expression: '!DIExpression()', + debug-info-location: '!151' } +body: | + bb.0.entry: + RET64 debug-location !151 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var47") +--- +name: Fun47 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var47, type: default, offset: 0, size: 4, alignment: 4, + debug-info-variable: '!156', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!158' } +body: | + bb.0.entry: + RET64 debug-location !158 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var48") +--- +name: Fun48 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var48, type: default, offset: 0, size: 4, alignment: 4, + debug-info-variable: '!163', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!165' } +body: | + bb.0.entry: + RET64 debug-location !165 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var49") +--- +name: Fun49 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var49, type: default, offset: 0, size: 4, alignment: 4, + debug-info-variable: '!170', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!172' } +body: | + bb.0.entry: + RET64 debug-location !172 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8) +# CHECK-NEXT: DW_AT_name ("Var50") +--- +name: Fun50 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var50, type: default, offset: 0, size: 8, alignment: 8, + debug-info-variable: '!177', debug-info-expression: '!DIExpression()', + debug-info-location: '!179' } +body: | + bb.0.entry: + RET64 debug-location !179 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var51") +--- +name: Fun51 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var51, type: default, offset: 0, size: 8, alignment: 8, + debug-info-variable: '!184', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!186' } +body: | + bb.0.entry: + RET64 debug-location !186 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var52") +--- +name: Fun52 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var52, type: default, offset: 0, size: 8, alignment: 8, + debug-info-variable: '!191', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!193' } +body: | + bb.0.entry: + RET64 debug-location !193 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var53") +--- +name: Fun53 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var53, type: default, offset: 0, size: 8, alignment: 8, + debug-info-variable: '!198', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!200' } +body: | + bb.0.entry: + RET64 debug-location !200 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16) +# CHECK-NEXT: DW_AT_name ("Var54") +--- +name: Fun54 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var54, type: default, offset: 0, size: 16, alignment: 16, + debug-info-variable: '!205', debug-info-expression: '!DIExpression()', + debug-info-location: '!207' } +body: | + bb.0.entry: + RET64 debug-location !207 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var55") +--- +name: Fun55 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var55, type: default, offset: 0, size: 16, alignment: 16, + debug-info-variable: '!212', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!214' } +body: | + bb.0.entry: + RET64 debug-location !214 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var56") +--- +name: Fun56 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var56, type: default, offset: 0, size: 16, alignment: 16, + debug-info-variable: '!219', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!221' } +body: | + bb.0.entry: + RET64 debug-location !221 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var57") +--- +name: Fun57 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var57, type: default, offset: 0, size: 16, alignment: 16, + debug-info-variable: '!226', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!228' } +body: | + bb.0.entry: + RET64 debug-location !228 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2) +# CHECK-NEXT: DW_AT_name ("Var58") +--- +name: Fun58 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var58, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!233', debug-info-expression: '!DIExpression()', + debug-info-location: '!235' } +body: | + bb.0.entry: + RET64 debug-location !235 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var59") +--- +name: Fun59 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var59, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!240', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!242' } +body: | + bb.0.entry: + RET64 debug-location !242 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var60") +--- +name: Fun60 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var60, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!247', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!249' } +body: | + bb.0.entry: + RET64 debug-location !249 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var61") +--- +name: Fun61 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var61, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!254', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!256' } +body: | + bb.0.entry: + RET64 debug-location !256 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2) +# CHECK-NEXT: DW_AT_name ("Var62") +--- +name: Fun62 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var62, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!261', debug-info-expression: '!DIExpression()', + debug-info-location: '!263' } +body: | + bb.0.entry: + RET64 debug-location !263 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var63") +--- +name: Fun63 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var63, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!268', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!270' } +body: | + bb.0.entry: + RET64 debug-location !270 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var64") +--- +name: Fun64 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var64, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!275', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!277' } +body: | + bb.0.entry: + RET64 debug-location !277 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -2, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var65") +--- +name: Fun65 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var65, type: default, offset: 0, size: 2, alignment: 2, + debug-info-variable: '!282', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!284' } +body: | + bb.0.entry: + RET64 debug-location !284 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4) +# CHECK-NEXT: DW_AT_name ("Var66") +--- +name: Fun66 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var66, type: default, offset: 0, size: 4, alignment: 4, + debug-info-variable: '!289', debug-info-expression: '!DIExpression()', + debug-info-location: '!291' } +body: | + bb.0.entry: + RET64 debug-location !291 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var67") +--- +name: Fun67 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var67, type: default, offset: 0, size: 4, alignment: 4, + debug-info-variable: '!296', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!298' } +body: | + bb.0.entry: + RET64 debug-location !298 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var68") +--- +name: Fun68 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var68, type: default, offset: 0, size: 4, alignment: 4, + debug-info-variable: '!303', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!305' } +body: | + bb.0.entry: + RET64 debug-location !305 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -4, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var69") +--- +name: Fun69 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var69, type: default, offset: 0, size: 4, alignment: 4, + debug-info-variable: '!310', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!312' } +body: | + bb.0.entry: + RET64 debug-location !312 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8) +# CHECK-NEXT: DW_AT_name ("Var70") +--- +name: Fun70 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var70, type: default, offset: 0, size: 8, alignment: 8, + debug-info-variable: '!317', debug-info-expression: '!DIExpression()', + debug-info-location: '!319' } +body: | + bb.0.entry: + RET64 debug-location !319 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var71") +--- +name: Fun71 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var71, type: default, offset: 0, size: 8, alignment: 8, + debug-info-variable: '!324', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!326' } +body: | + bb.0.entry: + RET64 debug-location !326 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var72") +--- +name: Fun72 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var72, type: default, offset: 0, size: 8, alignment: 8, + debug-info-variable: '!331', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!333' } +body: | + bb.0.entry: + RET64 debug-location !333 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -8, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var73") +--- +name: Fun73 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var73, type: default, offset: 0, size: 8, alignment: 8, + debug-info-variable: '!338', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!340' } +body: | + bb.0.entry: + RET64 debug-location !340 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16) +# CHECK-NEXT: DW_AT_name ("Var74") +--- +name: Fun74 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var74, type: default, offset: 0, size: 16, alignment: 16, + debug-info-variable: '!345', debug-info-expression: '!DIExpression()', + debug-info-location: '!347' } +body: | + bb.0.entry: + RET64 debug-location !347 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var75") +--- +name: Fun75 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var75, type: default, offset: 0, size: 16, alignment: 16, + debug-info-variable: '!352', debug-info-expression: '!DIExpression(DW_OP_deref)', + debug-info-location: '!354' } +body: | + bb.0.entry: + RET64 debug-location !354 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var76") +--- +name: Fun76 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var76, type: default, offset: 0, size: 16, alignment: 16, + debug-info-variable: '!359', debug-info-expression: '!DIExpression(DW_OP_stack_value)', + debug-info-location: '!361' } +body: | + bb.0.entry: + RET64 debug-location !361 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_fbreg -16, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var77") +--- +name: Fun77 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: + - { id: 0, name: Var77, type: default, offset: 0, size: 16, alignment: 16, + debug-info-variable: '!366', debug-info-expression: '!DIExpression(DW_OP_deref, DW_OP_stack_value)', + debug-info-location: '!368' } +body: | + bb.0.entry: + RET64 debug-location !368 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_reg0 RAX) +# CHECK-NEXT: DW_AT_name ("Var78") +--- +name: Fun78 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression() + DBG_VALUE $rax, $noreg, !373, !DIExpression(), debug-location !375 + + RET64 debug-location !375 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0) +# CHECK-NEXT: DW_AT_name ("Var79") +--- +name: Fun79 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref) + DBG_VALUE $rax, $noreg, !380, !DIExpression(DW_OP_deref), debug-location !382 + + RET64 debug-location !382 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var80") +--- +name: Fun80 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_stack_value) + DBG_VALUE $rax, $noreg, !387, !DIExpression(DW_OP_stack_value), debug-location !389 + + RET64 debug-location !389 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var81") +--- +name: Fun81 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref, DW_OP_stack_value) + DBG_VALUE $rax, $noreg, !394, !DIExpression(DW_OP_deref, DW_OP_stack_value), debug-location !396 + + RET64 debug-location !396 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_reg0 RAX) +# CHECK-NEXT: DW_AT_name ("Var82") +--- +name: Fun82 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression() + DBG_VALUE $ax, $noreg, !401, !DIExpression(), debug-location !403 + + RET64 debug-location !403 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_constu 0xffff, DW_OP_and) +# CHECK-NEXT: DW_AT_name ("Var83") +--- +name: Fun83 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref) + DBG_VALUE $ax, $noreg, !408, !DIExpression(DW_OP_deref), debug-location !410 + + RET64 debug-location !410 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_constu 0xffff, DW_OP_and, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var84") +--- +name: Fun84 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_stack_value) + DBG_VALUE $ax, $noreg, !415, !DIExpression(DW_OP_stack_value), debug-location !417 + + RET64 debug-location !417 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_constu 0xffff, DW_OP_and, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var85") +--- +name: Fun85 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref, DW_OP_stack_value) + DBG_VALUE $ax, $noreg, !422, !DIExpression(DW_OP_deref, DW_OP_stack_value), debug-location !424 + + RET64 debug-location !424 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0) +# CHECK-NEXT: DW_AT_name ("Var86") +--- +name: Fun86 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression() + DBG_VALUE $ax, 0, !429, !DIExpression(), debug-location !431 + + RET64 debug-location !431 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_constu 0xffff, DW_OP_and, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var87") +--- +name: Fun87 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref) + DBG_VALUE $ax, 0, !436, !DIExpression(DW_OP_deref), debug-location !438 + + RET64 debug-location !438 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_constu 0xffff, DW_OP_and, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var88") +--- +name: Fun88 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_stack_value) + DBG_VALUE $ax, 0, !443, !DIExpression(DW_OP_stack_value), debug-location !445 + + RET64 debug-location !445 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_constu 0xffff, DW_OP_and, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var89") +--- +name: Fun89 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref, DW_OP_stack_value) + DBG_VALUE $ax, 0, !450, !DIExpression(DW_OP_deref, DW_OP_stack_value), debug-location !452 + + RET64 debug-location !452 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0) +# CHECK-NEXT: DW_AT_name ("Var90") +--- +name: Fun90 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression() + DBG_VALUE $rax, 0, !457, !DIExpression(), debug-location !459 + + RET64 debug-location !459 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_deref) +# CHECK-NEXT: DW_AT_name ("Var91") +--- +name: Fun91 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref) + DBG_VALUE $rax, 0, !464, !DIExpression(DW_OP_deref), debug-location !466 + + RET64 debug-location !466 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var92") +--- +name: Fun92 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_stack_value) + DBG_VALUE $rax, 0, !471, !DIExpression(DW_OP_stack_value), debug-location !473 + + RET64 debug-location !473 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_breg0 RAX+0, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var93") +--- +name: Fun93 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref, DW_OP_stack_value) + DBG_VALUE $rax, 0, !478, !DIExpression(DW_OP_deref, DW_OP_stack_value), debug-location !480 + + RET64 debug-location !480 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_const_value (42) +# CHECK-NEXT: DW_AT_name ("Var94") +--- +name: Fun94 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression() + DBG_VALUE 42, $noreg, !485, !DIExpression(), debug-location !487 + + RET64 debug-location !487 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_constu 0x2a) +# CHECK-NEXT: DW_AT_name ("Var95") +--- +name: Fun95 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref) + DBG_VALUE 42, $noreg, !492, !DIExpression(DW_OP_deref), debug-location !494 + + RET64 debug-location !494 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_constu 0x2a, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var96") +--- +name: Fun96 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_stack_value) + DBG_VALUE 42, $noreg, !499, !DIExpression(DW_OP_stack_value), debug-location !501 + + RET64 debug-location !501 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_constu 0x2a, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var97") +--- +name: Fun97 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref, DW_OP_stack_value) + DBG_VALUE 42, $noreg, !506, !DIExpression(DW_OP_deref, DW_OP_stack_value), debug-location !508 + + RET64 debug-location !508 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_const_value (42) +# CHECK-NEXT: DW_AT_name ("Var98") +--- +name: Fun98 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression() + DBG_VALUE 42, 0, !513, !DIExpression(), debug-location !515 + + RET64 debug-location !515 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_constu 0x2a) +# CHECK-NEXT: DW_AT_name ("Var99") +--- +name: Fun99 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref) + DBG_VALUE 42, 0, !520, !DIExpression(DW_OP_deref), debug-location !522 + + RET64 debug-location !522 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_constu 0x2a, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var100") +--- +name: Fun100 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_stack_value) + DBG_VALUE 42, 0, !527, !DIExpression(DW_OP_stack_value), debug-location !529 + + RET64 debug-location !529 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (DW_OP_constu 0x2a, DW_OP_deref, DW_OP_stack_value) +# CHECK-NEXT: DW_AT_name ("Var101") +--- +name: Fun101 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_deref, DW_OP_stack_value) + DBG_VALUE 42, 0, !534, !DIExpression(DW_OP_deref, DW_OP_stack_value), debug-location !536 + + RET64 debug-location !536 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (indexed (0x[[#%x,]]) loclist = 0x[[#%x,]]: +# CHECK-NEXT: [0x[[#%x,]], 0x[[#%x,]]): DW_OP_reg0 RAX, DW_OP_piece 0x4, DW_OP_reg3 RBX, DW_OP_piece 0x4) +# CHECK-NEXT: DW_AT_name ("Var102") +--- +name: Fun102 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_LLVM_fragment, 0, 32) + DBG_VALUE $rax, $noreg, !541, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !543 + ; !DIExpression(DW_OP_LLVM_fragment, 32, 32) + DBG_VALUE $rbx, $noreg, !541, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !543 + + RET64 debug-location !543 +... +# CHECK: DW_TAG_variable +# CHECK-NEXT: DW_AT_location (indexed (0x[[#%x,]]) loclist = 0x[[#%x,]]: +# CHECK-NEXT: [0x[[#%x,]], 0x[[#%x,]]): DW_OP_breg0 RAX+0, DW_OP_piece 0x4, DW_OP_reg3 RBX, DW_OP_piece 0x4) +# CHECK-NEXT: DW_AT_name ("Var103") +--- +name: Fun103 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64, preferred-register: '' } +stack: [] +body: | + bb.0.entry: + ; !DIExpression(DW_OP_LLVM_fragment, 0, 32) + DBG_VALUE $rax, 0, !548, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !550 + ; !DIExpression(DW_OP_LLVM_fragment, 32, 32) + DBG_VALUE $rbx, $noreg, !548, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !550 + + RET64 debug-location !550 +... + diff --git a/llvm/test/DebugInfo/AMDGPU/cfi.ll b/llvm/test/DebugInfo/AMDGPU/cfi.ll index 686cf4b654e35..63008022bbc8a 100644 --- a/llvm/test/DebugInfo/AMDGPU/cfi.ll +++ b/llvm/test/DebugInfo/AMDGPU/cfi.ll @@ -1,10 +1,10 @@ ; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - %s | llvm-dwarfdump -debug-frame - | FileCheck %s ; CHECK: .debug_frame contents: -; CHECK: 00000000 0000000c ffffffff CIE +; CHECK: 00000000 0000001c ffffffff CIE ; CHECK-NEXT: Format: DWARF32 ; CHECK-NEXT: Version: 4 -; CHECK-NEXT: Augmentation: "" +; CHECK-NEXT: Augmentation: "[llvm:v0.0]" ; CHECK-NEXT: Address size: 8 ; CHECK-NEXT: Segment desc size: 0 ; CHECK-NEXT: Code alignment factor: 4 @@ -12,9 +12,17 @@ ; CHECK-NEXT: Return address column: 16 ; CHECK-EMPTY: ; CHECK: DW_CFA_nop: +; CHECK: DW_CFA_nop: +; CHECK: DW_CFA_nop: +; CHECK: DW_CFA_nop: +; CHECK: DW_CFA_nop: +; CHECK: DW_CFA_nop: ; CHECK-EMPTY: -; CHECK: 00000010 {{[0-9]+}} 00000000 FDE cie=00000000 pc=00000000...{{[0-9]+}} +; CHECK: 00000020 {{[0-9]+}} 00000000 FDE cie=00000000 pc=00000000...{{[0-9]+}} ; CHECK-NEXT: Format: DWARF32 +; CHECK-NEXT: DW_CFA_LLVM_def_aspace_cfa: SGPR32 +0 in addrspace6 +; CHECK-NEXT: DW_CFA_expression: PC_REG DW_OP_regx SGPR30, DW_OP_piece 0x4, DW_OP_regx SGPR31, DW_OP_piece 0x4 +; CHECK-NEXT: DW_CFA_nop: ; CHECK-EMPTY: ; CHECK: .eh_frame contents: ; CHECK-NOT: CIE diff --git a/llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll b/llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll index 1f13282a1f04c..3f46ccb2f37e0 100644 --- a/llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll +++ b/llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll @@ -12,6 +12,16 @@ define void @_Z12lane_pc_testj() #0 !dbg !9 { ; GCN-NEXT: .cfi_sections .debug_frame ; GCN-NEXT: .cfi_startproc ; GCN-NEXT: ; %bb.0: +; GCN-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; GCN-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; GCN-NEXT: .cfi_undefined 1536 +; GCN-NEXT: .cfi_undefined 1537 +; GCN-NEXT: .cfi_undefined 1538 +; GCN-NEXT: .cfi_undefined 36 +; GCN-NEXT: .cfi_undefined 37 +; GCN-NEXT: .cfi_undefined 38 +; GCN-NEXT: .cfi_undefined 39 +; GCN-NEXT: .cfi_undefined 40 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: ; %bb.1: ; %lab ; GCN-NEXT: s_mov_b64 s[4:5], 0 diff --git a/llvm/test/DebugInfo/AMDGPU/dwarfdump-address-spaces.ll b/llvm/test/DebugInfo/AMDGPU/dwarfdump-address-spaces.ll new file mode 100644 index 0000000000000..06d5781b358a0 --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/dwarfdump-address-spaces.ll @@ -0,0 +1,91 @@ +; RUN: llc -mtriple=x86_64--gnu -filetype=obj --verify-machineinstrs < %s | llvm-dwarfdump - 2>&1 | FileCheck %s --check-prefixes=COMMON,X86 +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -filetype=obj --verify-machineinstrs < %s | llvm-dwarfdump - 2>&1 | FileCheck %s --check-prefixes=COMMON,AMDGPU + +; Check that the address spaces are correctly printed for AMDGPU. +; The interpretation of the address space is dependent on the target. + +;COMMON: DW_TAG_compile_unit +;COMMON: DW_TAG_subprogram +;COMMON: DW_TAG_variable +;COMMON: DW_AT_name ("A_none") +;COMMON: DW_AT_type ([[PTR_NONE:0x[0-9a-f]+]] +;COMMON: DW_TAG_variable +;COMMON: DW_AT_name ("A_generic") +;COMMON: DW_AT_type ([[PTR_FLAT:0x[0-9a-f]+]] +;COMMON: DW_TAG_variable +;COMMON: DW_AT_name ("A_region") +;COMMON: DW_AT_type ([[PTR_REGION:0x[0-9a-f]+]] +;COMMON: DW_TAG_variable +;COMMON: DW_AT_name ("A_local") +;COMMON: DW_AT_type ([[PTR_LOCAL:0x[0-9a-f]+]] +;COMMON: DW_TAG_variable +;COMMON: DW_AT_name ("A_private_lane") +;COMMON: DW_AT_type ([[PTR_PRIVATE_LANE:0x[0-9a-f]+]] +;COMMON: DW_TAG_variable +;COMMON: DW_AT_name ("A_private_wave") +;COMMON: DW_AT_type ([[PTR_PRIVATE_WAVE:0x[0-9a-f]+]] + +;COMMON: [[PTR_NONE]]: DW_TAG_pointer_type +;COMMON: DW_AT_type ([[INT:0x[0-9a-f]+]] "int") +;AMDGPU: DW_AT_LLVM_address_space (0x00000000 "DW_ASPACE_LLVM_none") +;X86: DW_AT_LLVM_address_space (0x00000000 "DW_ASPACE_LLVM_none") + +;COMMON: [[INT]]: DW_TAG_base_type +;COMMON: DW_AT_name ("int") + +;COMMON: [[PTR_FLAT]]: DW_TAG_pointer_type +;COMMON: DW_AT_type ([[INT]] "int") +;AMDGPU: DW_AT_LLVM_address_space (0x00000001 "DW_ASPACE_LLVM_AMDGPU_generic") +;X86: DW_AT_LLVM_address_space (0x00000001) + +;COMMON: [[PTR_REGION]]: DW_TAG_pointer_type +;COMMON: DW_AT_type ([[INT]] "int") +;AMDGPU: DW_AT_LLVM_address_space (0x00000002 "DW_ASPACE_LLVM_AMDGPU_region") +;X86: DW_AT_LLVM_address_space (0x00000002) + +;COMMON: [[PTR_LOCAL]]: DW_TAG_pointer_type +;COMMON: DW_AT_type ([[INT]] "int") +;AMDGPU: DW_AT_LLVM_address_space (0x00000003 "DW_ASPACE_LLVM_AMDGPU_local") +;X86: DW_AT_LLVM_address_space (0x00000003) + +;COMMON: [[PTR_PRIVATE_LANE]]: DW_TAG_pointer_type +;COMMON: DW_AT_type ([[INT]] "int") +;AMDGPU: DW_AT_LLVM_address_space (0x00000005 "DW_ASPACE_LLVM_AMDGPU_private_lane") +;X86: DW_AT_LLVM_address_space (0x00000005) + +;COMMON: [[PTR_PRIVATE_WAVE]]: DW_TAG_pointer_type +;COMMON: DW_AT_type ([[INT]] "int") +;AMDGPU: DW_AT_LLVM_address_space (0x00000006 "DW_ASPACE_LLVM_AMDGPU_private_wave") +;X86: DW_AT_LLVM_address_space (0x00000006) + +define void @kernel() !dbg !7 { +entry: + ret void, !dbg !6 +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!4, !5} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "dummy.cl", directory: "/some/random/directory") +!2 = !{} +!3 = !{!20, !21, !22, !23, !24, !25} +!4 = !{i32 2, !"Dwarf Version", i32 2} +!5 = !{i32 2, !"Debug Info Version", i32 3} +!6 = !DILocation(line: 3, column: 1, scope: !7) +!7 = distinct !DISubprogram(name: "kernel", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !3) +!8 = !DISubroutineType(types: !9) +!9 = !{null} +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!20 = !DILocalVariable(name: "A_none", scope: !7, file: !1, line: 1, type: !30) +!21 = !DILocalVariable(name: "A_generic", scope: !7, file: !1, line: 1, type: !31) +!22 = !DILocalVariable(name: "A_region", scope: !7, file: !1, line: 1, type: !32) +!23 = !DILocalVariable(name: "A_local", scope: !7, file: !1, line: 1, type: !33) +!24 = !DILocalVariable(name: "A_private_lane", scope: !7, file: !1, line: 1, type: !34) +!25 = !DILocalVariable(name: "A_private_wave", scope: !7, file: !1, line: 1, type: !35) +!30 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, addressSpace: 0) +!31 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, addressSpace: 1) +!32 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, addressSpace: 2) +!33 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, addressSpace: 3) +!34 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, addressSpace: 5) +!35 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, addressSpace: 6) diff --git a/llvm/test/DebugInfo/AMDGPU/hard-clauses.mir b/llvm/test/DebugInfo/AMDGPU/hard-clauses.mir new file mode 100644 index 0000000000000..acbd556440b51 --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/hard-clauses.mir @@ -0,0 +1,59 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s +# XFAIL: * +# CHECK-LABEL: name: debug_instrs +# CHECK-LABEL: debugValueSubstitutions: +# CHECK-NEXT: - { srcinst: 3, srcop: 0, dstinst: 4, dstop: 0, subreg: 0 } +# CHECK-NEXT: - { srcinst: 2, srcop: 0, dstinst: 4, dstop: 1, subreg: 0 } + +--- +name: debug_instrs +tracksRegLiveness: true +debugInstrRef: true +body: | + bb.0: + liveins: $sgpr0_sgpr1 + ; CHECK-LABEL: name: debug_instrs + ; CHECK: liveins: $sgpr0_sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: DBG_VALUE_LIST + ; CHECK-NEXT: DBG_PHI + ; CHECK-NEXT: DBG_INSTR_REF + ; CHECK-NEXT: BUNDLE implicit-def $sgpr3, implicit-def $sgpr2, implicit $sgpr0_sgpr1, debug-instr-number 4 { + ; CHECK-NEXT: S_CLAUSE 2 + ; CHECK-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, debug-instr-number 1 + ; CHECK-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0, debug-instr-number 2 + ; CHECK-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 3 + ; CHECK-NEXT: } + ; CHECK-NEXT: DBG_VALUE + DBG_VALUE_LIST + $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, debug-instr-number 1 + DBG_PHI + $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0, debug-instr-number 2 + DBG_INSTR_REF + $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 3 + DBG_VALUE +... + +# CHECK-LABEL: name: only_last_instr +# CHECK-LABEL: debugValueSubstitutions: +# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 1, subreg: 0 } + +--- +name: only_last_instr +tracksRegLiveness: true +debugInstrRef: true +body: | + bb.0: + liveins: $sgpr0_sgpr1 + ; CHECK-LABEL: name: only_last_instr + ; CHECK: liveins: $sgpr0_sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BUNDLE implicit-def $sgpr2, implicit-def $sgpr3, implicit $sgpr0_sgpr1, debug-instr-number 2 { + ; CHECK-NEXT: S_CLAUSE 1 + ; CHECK-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 + ; CHECK-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 1 + ; CHECK-NEXT: } + $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 + $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 1 +... diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s new file mode 100644 index 0000000000000..d742cfc49689c --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s @@ -0,0 +1,57 @@ +; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1100 -filetype=obj %s | llvm-dwarfdump -debug-frame - | FileCheck %s + +.text +.cfi_sections .debug_frame + +; CHECK-NOT: DW_CFA_expression + +register_pair: + .cfi_startproc + s_nop 2 + ; CHECK: DW_CFA_expression: PC_REG DW_OP_regx SGPR30, DW_OP_piece 0x4, DW_OP_regx SGPR31, DW_OP_piece 0x4 + .cfi_llvm_register_pair 16, 62, 32, 63, 32 + s_nop 2 + .cfi_endproc + +; CHECK-NOT: DW_CFA_expression + +vector_registers: + .cfi_startproc + s_nop 2 + ; CHECK: DW_CFA_expression: PC_REG DW_OP_regx 0x67f, DW_OP_bit_piece 0x20 0x0, DW_OP_regx 0x67f, DW_OP_bit_piece 0x20 0x20 + .cfi_llvm_vector_registers 16, 1663, 0, 32, 1663, 1, 32 + s_nop 2 + .cfi_endproc + +; CHECK-NOT: DW_CFA_expression + +vector_registers_single: + .cfi_startproc + s_nop 2 + ;; Note that 0x2c below is the offset in the VGPR, so 4 (bytes, vgpr lane size) * 11 (the lane). + ; CHECK: DW_CFA_expression: SGPR45 DW_OP_regx VGPR41, DW_OP_LLVM_user DW_OP_LLVM_offset_uconst 0x2c + .cfi_llvm_vector_registers 77, 2601, 11, 32 + s_nop 2 + .cfi_endproc + +; CHECK-NOT: DW_CFA_expression + +vector_offsets: + .cfi_startproc + s_nop 2 + ; CHECK: DW_CFA_expression: VGPR40 DW_OP_regx VGPR40, DW_OP_swap, DW_OP_LLVM_user DW_OP_LLVM_offset_uconst 0x100, DW_OP_LLVM_user DW_OP_LLVM_call_frame_entry_reg EXEC, DW_OP_deref_size 0x8, DW_OP_LLVM_user DW_OP_LLVM_select_bit_piece 0x20 0x40 + .cfi_llvm_vector_offset 2600, 32, 17, 64, 256 + s_nop 2 + .cfi_endproc + +; CHECK-NOT: DW_CFA_expression + +vector_register_mask: + .cfi_startproc + s_nop 0 + ; CHECK: DW_CFA_expression: VGPR40 DW_OP_regx VGPR40, DW_OP_regx AGPR0, DW_OP_LLVM_user DW_OP_LLVM_call_frame_entry_reg EXEC, DW_OP_deref_size 0x8, DW_OP_LLVM_user DW_OP_LLVM_select_bit_piece 0x20 0x40 + .cfi_llvm_vector_register_mask 2600, 3072, 32, 17, 64 + s_nop 0 + .cfi_endproc + +; CHECK-NOT: DW_CFA_expression diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-address-spaces.ll b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-address-spaces.ll new file mode 100644 index 0000000000000..60a055ad66b61 --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-address-spaces.ll @@ -0,0 +1,174 @@ +; RUN: llc -O0 -mcpu=gfx1030 -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-dwarfdump --debug-info - | FileCheck %s + +; CHECK-LABEL: DW_AT_name ("test_loc_single") +define void @test_loc_single(ptr addrspace(3) %ptr) #0 !dbg !9 { + ; Verify that the right address class attribute is attached to the variable's + ; type for a single location: + ; CHECK: 0x{{[0-9a-f]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (DW_OP_regx {{.*}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset) + ; CHECK-NEXT: DW_AT_name ("loc_single_ptr") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type ([[PTR_AS_3:0x[0-9a-f]+]] "int *") + + #dbg_value(ptr addrspace(3) %ptr, !13, !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpConvert(ptr)), !16) + ret void, !dbg !17 +} + +; CHECK-LABEL: DW_AT_name ("test_loc_multi") +define void @test_loc_multi(ptr addrspace(3) %loc_ptr) #0 !dbg !18 { + ; Verify that no attribute is attached to the variable type if the loclist + ; contains entries with different address spaces: + ; CHECK: 0x{{[0-9a-f]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (indexed ({{0x[0-9a-f]+}}) loclist = + ; CHECK-NEXT: [{{0x[0-9a-f]+}}, {{0x[0-9a-f]+}}):{{.*}} DW_OP_LLVM_user DW_OP_LLVM_undefined + ; CHECK-NEXT: [{{0x[0-9a-f]+}}, {{0x[0-9a-f]+}}): DW_OP_lit0, DW_OP_stack_value) + ; CHECK-NEXT: DW_AT_name ("ptr_as3_as2") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type ([[PTR_AS_NONE:0x[0-9a-f]+]] "int *") + + ; Verify that an attribute is attached to the variable type if the loclist + ; contains entries with the same address spaces: + ; CHECK: 0x{{[0-9a-f]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (indexed ({{0x[0-9a-f]+}}) loclist = + ; CHECK-NEXT: [{{0x[0-9a-f]+}}, {{0x[0-9a-f]+}}): DW_OP_regx + ; CHECK-NEXT: [{{0x[0-9a-f]+}}, {{0x[0-9a-f]+}}): DW_OP_lit0, DW_OP_stack_value) + ; CHECK-NEXT: DW_AT_name ("ptr_all_as3") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type ([[PTR_AS_3]] "int *") + + #dbg_value(ptr addrspace(3) %loc_ptr, !21, !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpConvert(ptr)), !22) + #dbg_value(ptr addrspace(3) %loc_ptr, !20, !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpConvert(ptr)), !22) + tail call void asm sideeffect "s_nop 1", ""(), !dbg !22 + #dbg_value(ptr null, !21, !DIExpression(DIOpArg(0, ptr)), !23) + #dbg_value(ptr addrspace(3) null, !20, !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpConvert(ptr)), !23) + ret void, !dbg !23 +} + +; CHECK-LABEL: DW_AT_name ("test_loc_mmi") +define void @test_loc_mmi() #0 !dbg !24 { + ; CHECK: 0x{{[0-9a-f]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (indexed ({{0x[0-9a-f]+}}) loclist = + ; CHECK-NEXT: [{{0x[0-9a-f]+}}, {{0x[0-9a-f]+}}): DW_OP_regx SGPR{{.*}}, DW_OP_deref_size 0x4, DW_OP_lit5, DW_OP_shr, DW_OP_lit0, DW_OP_plus, DW_OP_stack_value) + ; CHECK-NEXT: DW_AT_name ("ptr_as5") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type ([[PTR_AS_5:0x[0-9a-f]+]] "int *") + + %ptr = alloca i32, align 4, addrspace(5), !dbg !27 + #dbg_value(ptr addrspace(5) %ptr, !26, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpConvert(ptr)), !27) + ret void, !dbg !28 +} + +; CHECK-LABEL: DW_AT_name ("test_divergent") +define void @test_divergent(ptr addrspace(5) %p5, ptr addrspace(3) %p3) #0 !dbg !29 { + ; CHECK: 0x{{[0-9a-f]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (DW_OP_regx {{.*}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset) + ; CHECK-NEXT: DW_AT_name ("ptr_div_as5") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type ([[PTR_AS_5]] "int *") + #dbg_value(ptr addrspace(5) %p5, !31, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpConvert(ptr)), !30) + + ; CHECK: 0x{{[0-9a-f]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (DW_OP_regx {{.*}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset) + ; CHECK-NEXT: DW_AT_name ("ptr_div_as3") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type ([[PTR_AS_3]] "int *") + #dbg_value(ptr addrspace(3) %p3, !32, !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpConvert(ptr), DIOpReinterpret(i64), DIOpReinterpret(ptr)), !30) + + ; CHECK: 0x{{[0-9a-f]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location ({{.*}} DW_OP_LLVM_user DW_OP_LLVM_undefined) + ; CHECK-NEXT: DW_AT_name ("ptr_div_invalid") + #dbg_value(ptr addrspace(5) %p5, !33, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpConvert(ptr), DIOpReinterpret(i64), DIOpConstant(i64 42), DIOpAdd(), DIOpReinterpret(ptr)), !30) + + ret void, !dbg !30 +} + +; CHECK-LABEL: DW_AT_name ("test_noop_convert") +define void @test_noop_convert(ptr addrspace(1) %p1) #0 !dbg !34 { + ; Verify that a noop address space conversion doesn't produce a divergent + ; address space. + ; CHECK: 0x{{[0-9a-f]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location + ; CHECK-NEXT: DW_AT_name ("not_divergent") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type ([[PTR_AS_NONE]] "int *") + #dbg_value(ptr addrspace(1) %p1, !36, !DIExpression(DIOpArg(0, ptr addrspace(1)), DIOpConvert(ptr addrspace(1)), DIOpReinterpret(ptr)), !37) + ret void, !dbg !37 +} + +define void @test_noassert(ptr addrspace(1) %p1) #0 !dbg !38 { + ; Verify that this doesn't assert. + #dbg_value(ptr addrspace(1) %p1, !40, !DIExpression(DIOpArg(0, ptr addrspace(1)), DIOpConvert(ptr), DIOpReinterpret(i64), DIOpConstant(i64 1), DIOpAdd(), DIOpFragment(0, 32)), !41) + #dbg_value(i32 0, !40, !DIExpression(DIOpArg(0, i32), DIOpFragment(32, 16)), !41) + #dbg_value(i32 0, !40, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 48, 16), !41) + ret void, !dbg !41 +} + +attributes #0 = { "frame-pointer"="all" } + +; CHECK: [[PTR_AS_3]]: DW_TAG_pointer_type +; CHECK-NEXT: DW_AT_type +; CHECK-NEXT: DW_AT_address_class (0x00000003) +; CHECK-NEXT: DW_AT_LLVM_address_space (0x00000003 "DW_ASPACE_LLVM_AMDGPU_local") + +; CHECK: [[PTR_AS_NONE]]: DW_TAG_pointer_type +; CHECK-NEXT: DW_AT_type +; CHECK-EMPTY: + +; CHECK: [[PTR_AS_5]]: DW_TAG_pointer_type +; CHECK-NEXT: DW_AT_type +; CHECK-NEXT: DW_AT_address_class (0x00000005) +; CHECK-NEXT: DW_AT_LLVM_address_space (0x00000005 "DW_ASPACE_LLVM_AMDGPU_private_lane") + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7} +!llvm.ident = !{!8} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 19.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "t.cpp", directory: "/") +!2 = !{i32 1, !"amdhsa_code_object_version", i32 500} +!3 = !{i32 7, !"Dwarf Version", i32 5} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{i32 8, !"PIC Level", i32 2} +!7 = !{i32 7, !"frame-pointer", i32 2} +!8 = !{!"clang version 19.0.0"} +!9 = distinct !DISubprogram(name: "test_loc_single", linkageName: "test_loc_single", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !12) +!10 = !DISubroutineType(types: !11) +!11 = !{} +!12 = !{!13} +!13 = !DILocalVariable(name: "loc_single_ptr", scope: !9, file: !1, line: 1, type: !14) +!14 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !15, size: 64) +!15 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!16 = !DILocation(line: 1, column: 14, scope: !9) +!17 = !DILocation(line: 2, column: 1, scope: !9) +!18 = distinct !DISubprogram(name: "test_loc_multi", linkageName: "test_loc_multi", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !19) +!19 = !{!20, !21} +!20 = !DILocalVariable(name: "ptr_all_as3", scope: !18, file: !1, line: 1, type: !14) +!21 = !DILocalVariable(name: "ptr_as3_as2", scope: !18, file: !1, line: 1, type: !14) +!22 = !DILocation(line: 1, column: 1, scope: !18) +!23 = !DILocation(line: 2, column: 1, scope: !18) +!24 = distinct !DISubprogram(name: "test_loc_mmi", linkageName: "test_loc_mmi", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !25) +!25 = !{!26} +!26 = !DILocalVariable(name: "ptr_as5", scope: !24, file: !1, line: 1, type: !14) +!27 = !DILocation(line: 1, column: 1, scope: !24) +!28 = !DILocation(line: 2, column: 1, scope: !24) +!29 = distinct !DISubprogram(name: "test_divergent", linkageName: "test_divergent", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !19) +!30 = !DILocation(line: 1, column: 1, scope: !29) +!31 = !DILocalVariable(name: "ptr_div_as5", scope: !29, file: !1, line: 1, type: !14) +!32 = !DILocalVariable(name: "ptr_div_as3", scope: !29, file: !1, line: 1, type: !14) +!33 = !DILocalVariable(name: "ptr_div_invalid", scope: !29, file: !1, line: 1, type: !14) +!34 = distinct !DISubprogram(name: "test_noop_convert", linkageName: "test_noop_convert", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !35) +!35 = !{!36} +!36 = !DILocalVariable(name: "not_divergent", scope: !34, file: !1, line: 1, type: !14) +!37 = !DILocation(line: 1, column: 1, scope: !34) +!38 = distinct !DISubprogram(name: "test_noassert", linkageName: "test_noassert", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !39) +!39 = !{!40} +!40 = !DILocalVariable(name: "frags", scope: !38, file: !1, line: 1, type: !14) +!41 = !DILocation(line: 1, column: 1, scope: !38) diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-args.ll b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-args.ll new file mode 100644 index 0000000000000..a177f4c7f06d3 --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-args.ll @@ -0,0 +1,99 @@ +; RUN: llc -O1 -mcpu=gfx1030 -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-dwarfdump --debug-info - | FileCheck %s + +;; Verify that we produce valid debug locations for parameters of various types. + +@glob_ptr = global ptr addrspace(1) null + +; CHECK-LABEL: DW_AT_name ("int32_k") +define amdgpu_kernel void @int32_k(i32 %a) !dbg !9 { + ; CHECK: DW_AT_location + ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx SGPR{{[0-9]+}}) + #dbg_value(i32 %a, !12, !DIExpression(DIOpArg(0, i32)), !14) + store i32 %a, ptr @glob_ptr, align 4, !dbg !14 + ret void, !dbg !15 +} + +; CHECK-LABEL: DW_AT_name ("int64_k") +define amdgpu_kernel void @int64_k(i64 %a) !dbg !31 { + ; CHECK: DW_AT_location + ; CHECK-NEXT: DW_OP_regx SGPR{{[0-9a-z]+}}, DW_OP_piece 0x4, DW_OP_regx SGPR{{[0-9a-z]+}}, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end + #dbg_value(i64 %a, !32, !DIExpression(DIOpArg(0, i64)), !33) + store i64 %a, ptr @glob_ptr, align 8, !dbg !33 + ret void, !dbg !33 +} + +; CHECK-LABEL: DW_AT_name ("as1_ptr") +define void @as1_ptr(ptr addrspace(1) %ptr) !dbg !16 { + ; CHECK: DW_AT_location + ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4) + #dbg_value(ptr addrspace(1) %ptr, !17, !DIExpression(DIOpArg(0, ptr addrspace(1))), !20) + store ptr addrspace(1) %ptr, ptr @glob_ptr, align 8, !dbg !20 + ret void, !dbg !20 +} + +; CHECK-LABEL: DW_AT_name ("int64") +define void @int64(i64 %a) !dbg !21 { + ; CHECK: DW_AT_location + ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4) + #dbg_value(i64 %a, !22, !DIExpression(DIOpArg(0, i64)), !23) + store i64 %a, ptr @glob_ptr, align 8, !dbg !23 + ret void, !dbg !24 +} + +; CHECK-LABEL: DW_AT_name ("int32") +define void @int32(i32 %a) !dbg !25 { + ; CHECK: DW_AT_location (DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset) + #dbg_value(i32 %a, !26, !DIExpression(DIOpArg(0, i32)), !27) + store i32 %a, ptr @glob_ptr, align 4, !dbg !27 + ret void, !dbg !27 +} + +; CHECK-LABEL: DW_AT_name ("gen_ptr") +define void @gen_ptr(ptr %ptr) !dbg !28 { + ; CHECK: DW_AT_location + ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4) + #dbg_value(ptr %ptr, !29, !DIExpression(DIOpArg(0, ptr)), !30) + store ptr %ptr, ptr @glob_ptr, align 8, !dbg !30 + ret void, !dbg !30 +} + +declare void @llvm.dbg.value(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7} +!llvm.ident = !{!8} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 19.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "t.cpp", directory: "/") +!2 = !{i32 1, !"amdhsa_code_object_version", i32 500} +!3 = !{i32 7, !"Dwarf Version", i32 5} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{i32 8, !"PIC Level", i32 2} +!7 = !{i32 7, !"frame-pointer", i32 2} +!8 = !{!"clang version 19.0.0"} +!9 = distinct !DISubprogram(name: "int32_k", linkageName: "int32_k", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) +!10 = !DISubroutineType(types: !11) +!11 = !{} +!12 = !DILocalVariable(name: "i32", arg: 1, scope: !9, file: !1, type: !13) +!13 = !DIBasicType(name: "i32", size: 32, encoding: DW_ATE_signed) +!14 = !DILocation(line: 1, column: 1, scope: !9) +!15 = !DILocation(line: 2, column: 1, scope: !9) +!16 = distinct !DISubprogram(name: "as1_ptr", linkageName: "as1_ptr", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) +!17 = !DILocalVariable(name: "ptr", arg: 1, scope: !16, file: !1, line: 1, type: !18) +!18 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !19, size: 64) +!19 = !DIBasicType(name: "i64", size: 64, encoding: DW_ATE_signed) +!20 = !DILocation(line: 1, column: 1, scope: !16) +!21 = distinct !DISubprogram(name: "int64", linkageName: "int64", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) +!22 = !DILocalVariable(name: "i64", arg: 1, scope: !21, file: !1, type: !19) +!23 = !DILocation(line: 1, column: 1, scope: !21) +!24 = !DILocation(line: 2, column: 1, scope: !21) +!25 = distinct !DISubprogram(name: "int32", linkageName: "int32", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) +!26 = !DILocalVariable(name: "i32", arg: 1, scope: !25, file: !1, type: !13) +!27 = !DILocation(line: 1, column: 1, scope: !25) +!28 = distinct !DISubprogram(name: "gen_ptr", linkageName: "gen_ptr", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) +!29 = !DILocalVariable(name: "ptr", arg: 1, scope: !28, file: !1, type: !18) +!30 = !DILocation(line: 1, column: 1, scope: !28) +!31 = distinct !DISubprogram(name: "int64_k", linkageName: "int64_k", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) +!32 = !DILocalVariable(name: "i32", arg: 1, scope: !31, file: !1, type: !19) +!33 = !DILocation(line: 1, column: 1, scope: !31) diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-subregs.mir b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-subregs.mir new file mode 100644 index 0000000000000..7afc1ad329ade --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-subregs.mir @@ -0,0 +1,104 @@ +# RUN: llc -O0 -x mir -mcpu=gfx900 -start-after=livedebugvalues -filetype=obj < %s | llvm-dwarfdump - | FileCheck %s + +--- | + target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7" + target triple = "amdgcn-amd-amdhsa" + + define void @kern() #0 !dbg !9 { + ret void, !dbg !16 + } + attributes #0 = { noinline optnone } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!2, !3, !4, !5, !6, !7} + !llvm.ident = !{!8} + + !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 19.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) + !1 = !DIFile(filename: "t.cpp", directory: "/") + !2 = !{i32 1, !"amdhsa_code_object_version", i32 500} + !3 = !{i32 7, !"Dwarf Version", i32 5} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = !{i32 1, !"wchar_size", i32 4} + !6 = !{i32 8, !"PIC Level", i32 2} + !7 = !{i32 7, !"frame-pointer", i32 2} + !8 = !{!"clang version 19.0.0"} + !9 = distinct !DISubprogram(name: "kern", linkageName: "kern", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !12) + !10 = !DISubroutineType(types: !11) + !11 = !{} + !12 = !{!17, !18, !19} + !13 = !DIBasicType(name: "i16", size: 16, encoding: DW_ATE_signed) + !14 = !DIBasicType(name: "i32", size: 32, encoding: DW_ATE_signed) + !15 = !DIBasicType(name: "i64", size: 64, encoding: DW_ATE_signed) + !16 = !DILocation(line: 1, column: 1, scope: !9) + !17 = !DILocalVariable(name: "s_lo16", scope: !9, file: !1, line: 1, type: !13) + !18 = !DILocalVariable(name: "s_hi16", scope: !9, file: !1, line: 1, type: !13) + !19 = !DILocalVariable(name: "s_s", scope: !9, file: !1, line: 1, type: !15) + !20 = !DILocalVariable(name: "v_lo16", scope: !9, file: !1, line: 1, type: !13) + !21 = !DILocalVariable(name: "v_hi16", scope: !9, file: !1, line: 1, type: !13) + !22 = !DILocalVariable(name: "v_v", scope: !9, file: !1, line: 1, type: !15) + !23 = !DILocalVariable(name: "with_frags", scope: !9, file: !1, line: 1, type: !15) + !24 = !DILocalVariable(name: "sgpr", scope: !9, file: !1, line: 1, type: !14) + !25 = !DILocalVariable(name: "vgpr", scope: !9, file: !1, line: 1, type: !14) + !26 = !DILocalVariable(name: "vgpr_frags", scope: !9, file: !1, line: 1, type: !15) + !27 = !DILocalVariable(name: "composite", scope: !9, file: !1, line: 1, type: !15) + +... +--- +name: kern +body: | + bb.0: + + ; CHECK: DW_AT_location (DW_OP_regx SGPR42) + ; CHECK-NEXT: DW_AT_name ("s_lo16") + DBG_VALUE renamable $sgpr42_lo16, $noreg, !17, !DIExpression(DIOpArg(0, i16)), debug-location !16 + + ; CHECK: DW_AT_location (DW_OP_regx SGPR42, DW_OP_LLVM_user DW_OP_LLVM_offset_uconst 0x2) + ; CHECK-NEXT: DW_AT_name ("s_hi16") + DBG_VALUE renamable $sgpr42_hi16, $noreg, !18, !DIExpression(DIOpArg(0, i16)), debug-location !16 + + ; CHECK: DW_AT_location (DW_OP_regx SGPR42, DW_OP_piece 0x4, DW_OP_regx SGPR43, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end) + ; CHECK-NEXT: DW_AT_name ("s_s") + DBG_VALUE renamable $sgpr42_sgpr43, $noreg, !19, !DIExpression(DIOpArg(0, i64)), debug-location !16 + + ; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset) + ; CHECK-NEXT: DW_AT_name ("v_lo16") + DBG_VALUE renamable $vgpr42_lo16, $noreg, !20, !DIExpression(DIOpArg(0, i16)), debug-location !16 + + ; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_LLVM_user DW_OP_LLVM_offset_uconst 0x2) + ; CHECK-NEXT: DW_AT_name ("v_hi16") + DBG_VALUE renamable $vgpr42_hi16, $noreg, !21, !DIExpression(DIOpArg(0, i16)), debug-location !16 + + ; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR43, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end) + ; CHECK-NEXT: DW_AT_name ("v_v") + DBG_VALUE renamable $vgpr42_vgpr43, $noreg, !22, !DIExpression(DIOpArg(0, i64)), debug-location !16 + + ; CHECK: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (indexed ({{.*}}) loclist = {{.*}}: + ; CHECK-NEXT: [{{.*}}): DW_OP_lit0, DW_OP_regx SGPR50, DW_OP_piece 0x4, DW_OP_regx SGPR51, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end, DW_OP_swap, DW_OP_drop, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_regx SGPR52, DW_OP_piece 0x4, DW_OP_regx SGPR53, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end, DW_OP_swap, DW_OP_drop, DW_OP_piece 0x4) + ; CHECK-NEXT: DW_AT_name ("with_frags") + DBG_VALUE renamable $sgpr50_sgpr51, $noreg, !23, !DIExpression(DIOpArg(0, i64), DIOpFragment(0, 32)), debug-location !16 + DBG_VALUE renamable $sgpr52_sgpr53, $noreg, !23, !DIExpression(DIOpArg(0, i64), DIOpFragment(32, 32)), debug-location !16 + + ; CHECK: DW_AT_location (DW_OP_regx SGPR100) + ; CHECK-NEXT: DW_AT_name ("sgpr") + DBG_VALUE $sgpr100, $noreg, !24, !DIExpression(DIOpArg(0, i32)), debug-location !16 + + ; CHECK: DW_AT_location (DW_OP_regx VGPR100, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset) + ; CHECK-NEXT: ("vgpr") + DBG_VALUE $vgpr100, $noreg, !25, !DIExpression(DIOpArg(0, i32)), debug-location !16 + + ; CHECK: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (indexed ({{.*}}) loclist = {{.*}}: + ; CHECK-NEXT: [{{.*}}): DW_OP_lit0, DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR43, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end, DW_OP_swap, DW_OP_drop, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_regx VGPR44, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR45, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end, DW_OP_swap, DW_OP_drop, DW_OP_piece 0x4) + ; CHECK-NEXT: DW_AT_name ("vgpr_frags") + DBG_VALUE renamable $vgpr42_vgpr43, $noreg, !26, !DIExpression(DIOpArg(0, i64), DIOpFragment(0, 32)), debug-location !16 + DBG_VALUE renamable $vgpr44_vgpr45, $noreg, !26, !DIExpression(DIOpArg(0, i64), DIOpFragment(32, 32)), debug-location !16 + + ; CHECK: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (DW_OP_regx SGPR10, DW_OP_piece 0x4, DW_OP_regx SGPR11, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end) + ; CHECK-NEXT: DW_AT_name ("composite") + DBG_VALUE_LIST !27, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, i64)), $sgpr10, $sgpr11, debug-location !16 + + S_ENDPGM 0, debug-location !16 + +... diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-frags.mir b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-frags.mir new file mode 100644 index 0000000000000..fc21454e9cddb --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-frags.mir @@ -0,0 +1,87 @@ +# RUN: llc -O0 -x mir -mcpu=gfx900 -start-after=livedebugvalues -filetype=obj < %s | llvm-dwarfdump - | FileCheck %s + +--- | + target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7" + target triple = "amdgcn-amd-amdhsa" + + define void @kern() #0 !dbg !9 { + ret void, !dbg !14 + } + attributes #0 = { convergent mustprogress noinline nounwind optnone "amdgpu-stack-objects" "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst" "uniform-work-group-size"="false" } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!2, !3, !4, !5, !6, !7} + !llvm.ident = !{!8} + + !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 19.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) + !1 = !DIFile(filename: "t.cpp", directory: "/") + !2 = !{i32 1, !"amdhsa_code_object_version", i32 500} + !3 = !{i32 7, !"Dwarf Version", i32 5} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = !{i32 1, !"wchar_size", i32 4} + !6 = !{i32 8, !"PIC Level", i32 2} + !7 = !{i32 7, !"frame-pointer", i32 2} + !8 = !{!"clang version 19.0.0"} + !9 = distinct !DISubprogram(name: "kern", linkageName: "kern", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !12) + !10 = !DISubroutineType(types: !11) + !11 = !{} + !12 = !{!17, !18, !19} + !13 = !DIBasicType(name: "i64", size: 64, encoding: DW_ATE_signed) + !14 = !DILocation(line: 1, column: 1, scope: !9) + !15 = !DILocation(line: 2, column: 1, scope: !9) + !16 = !DILocation(line: 3, column: 1, scope: !9) + !17 = !DILocalVariable(name: "no_overlaps", scope: !9, file: !1, line: 1, type: !13) + !18 = !DILocalVariable(name: "overlaps", scope: !9, file: !1, line: 1, type: !13) + !19 = !DILocalVariable(name: "bits", scope: !9, file: !1, line: 1, type: !13) + !20 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S", file: !1, line: 1, size: 64, elements: !21) + !21 = !{!22, !23} + !22 = !DIBasicType(name: "i32", size: 32, encoding: DW_ATE_signed) + !23 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !20, file: !1, line: 1, baseType: !22, size: 32) + !24 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !20, file: !1, line: 1, baseType: !22, size: 32, offset: 32) + !25 = !DILocalVariable(name: "struct_var", scope: !9, file: !1, line: 1, type: !20) + +... +--- +name: kern +body: | + bb.0: + + ; CHECK: DW_AT_location + ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx SGPR40, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x2, DW_OP_regx SGPR42, DW_OP_piece 0x2) + ; CHECK-NEXT: DW_AT_name ("no_overlaps") + DBG_VALUE_LIST !17, !DIExpression(DIOpArg(0, i32), DIOpFragment(0, 32)), renamable $sgpr40, debug-location !14 + DBG_VALUE_LIST !17, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 32, 16), renamable $sgpr41, debug-location !14 + DBG_VALUE_LIST !17, !DIExpression(DIOpArg(0, i32), DIOpFragment(48, 16)), renamable $sgpr42, debug-location !14 + + + ; CHECK: DW_AT_location + ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_piece 0x2, DW_OP_regx VGPR44, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR45, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x2 + DBG_VALUE renamable $vgpr43, $noreg, !18, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 0, 32), debug-location !14 + DBG_VALUE renamable $vgpr44, $noreg, !18, !DIExpression(DIOpArg(0, i32), DIOpFragment(16, 32)), debug-location !14 + DBG_VALUE renamable $vgpr45, $noreg, !18, !DIExpression(DIOpArg(0, i32), DIOpFragment(48, 16)), debug-location !14 + S_NOP 0, debug-location !14 + + ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx VGPR46, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x1, DW_OP_piece 0x1, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x2, DW_OP_piece 0x2, DW_OP_regx VGPR45, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x2 + DBG_VALUE renamable $vgpr46, $noreg, !18, !DIExpression(DIOpArg(0, i32), DIOpFragment(0, 8)), debug-location !15 + DBG_VALUE renamable $vgpr47, $noreg, !18, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 16, 16), debug-location !15 + S_NOP 0, debug-location !15 + + ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx VGPR46, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x1, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x7 + ; CHECK-NEXT: DW_AT_name ("overlaps") + DBG_VALUE renamable $vgpr48, $noreg, !18, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 8, 56), debug-location !16 + + ; CHECK: DW_AT_location + ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_bit_piece 0x1 0x0, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_bit_piece 0x1 0x0, DW_OP_regx SGPR50, DW_OP_bit_piece 0x1e 0x0 + ; CHECK-NEXT: DW_AT_name ("bits") + DBG_VALUE renamable $sgpr49, $noreg, !19, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 1, 1), debug-location !16 + DBG_VALUE renamable $sgpr50, $noreg, !19, !DIExpression(DIOpArg(0, i64), DIOpFragment(2, 30)), debug-location !16 + + ; CHECK: DW_AT_location + ; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx SGPR51, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x4 + ; CHECK-NEXT: DW_AT_name ("struct_var") + DBG_VALUE renamable $sgpr51, $noreg, !25, !DIExpression(DIOpArg(0, i32), DIOpFragment(0, 32)), debug-location !16 + DBG_VALUE renamable $sgpr52, $noreg, !25, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 32, 32), debug-location !16 + + S_ENDPGM 0, debug-location !16 + +... diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-instruction-bundle.ll b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-instruction-bundle.ll new file mode 100644 index 0000000000000..0a17cb3876abd --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-instruction-bundle.ll @@ -0,0 +1,56 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx1030 -O1 -filetype=asm < %s -o - | FileCheck %s + +define amdgpu_kernel void @foo(ptr addrspace(1) noalias %arg_in_0, ptr addrspace(1) %arg_out) !dbg !4 { +; CHECK-LABEL: foo: +; CHECK: .Lfunc_begin0: +; CHECK-NEXT: .file 1 "/" "gdb_simple.f95" +; CHECK-NEXT: .loc 1 0 0 ; gdb_simple.f95:0:0 +; CHECK-NEXT: .cfi_sections .debug_frame +; CHECK-NEXT: .cfi_startproc +; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: .cfi_escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 ; +; CHECK-NEXT: .cfi_undefined 16 +; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; CHECK-NEXT: v_mov_b32_e32 v2, 0 +; CHECK-NEXT: .loc 1 0 0 prologue_end ; gdb_simple.f95:0:0 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: ;DEBUG_VALUE: foo:i <- 2 +; CHECK-NEXT: s_clause 0x1 +; CHECK-NEXT: s_load_dword s4, s[0:1], 0x0 +; CHECK-NEXT: s_load_dword s0, s[0:1], 0x8 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v3, s4 +; CHECK-NEXT: v_mov_b32_e32 v4, s0 +; CHECK-NEXT: global_store_dword v2, v3, s[2:3] +; CHECK-NEXT: global_store_dword v[0:1], v4, off +; CHECK-NEXT: s_endpgm + %arg_in_1 = getelementptr i8, ptr addrspace(1) %arg_in_0, i64 8 + %load0 = load float, ptr addrspace(1) %arg_in_0 + store float %load0, ptr addrspace(1) %arg_out + call void @llvm.dbg.value(metadata i32 2, metadata !7, metadata !DIExpression()), !dbg !9 + %load1 = load float, ptr addrspace(1) %arg_in_1 + store float %load1, ptr addrspace(1) null + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #0 + +attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3} + +!0 = distinct !DICompileUnit(language: DW_LANG_Fortran90, file: !1, producer: " F90 Flang - 1.5 2017-05-01", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2, nameTableKind: None) +!1 = !DIFile(filename: "gdb_simple.f95", directory: "/") +!2 = !{} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = distinct !DISubprogram(name: "foo", scope: !0, file: !1, line: 12, type: !5, spFlags: DISPFlagDefinition, unit: !0) +!5 = !DISubroutineType(types: !6) +!6 = !{null} +!7 = !DILocalVariable(name: "i", scope: !4, file: !1, type: !8) +!8 = !DIBasicType(name: "integer", size: 32, align: 32, encoding: DW_ATE_signed) +!9 = !DILocation(line: 0, scope: !4) diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-pointer-parameters-isel.ll b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-pointer-parameters-isel.ll new file mode 100644 index 0000000000000..fda178a83a11f --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-pointer-parameters-isel.ll @@ -0,0 +1,143 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx1100 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck --check-prefixes=CHECK-O0 %s +; RUN: llc -O1 -mtriple=amdgcn -mcpu=gfx1100 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck --check-prefixes=CHECK-O1 %s +target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" +target triple = "amdgcn-amd-amdhsa" + +define void @_QFPadd(ptr %0, ptr %1) #0 !dbg !12 { + ; CHECK-O0-LABEL: name: _QFPadd + ; CHECK-O0: bb.0 (%ir-block.2): + ; CHECK-O0-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-O0-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-O0-NEXT: {{ $}} + ; CHECK-O0-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; CHECK-O0-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; CHECK-O0-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-O0-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-O0-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 + ; CHECK-O0-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 + ; CHECK-O0-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]] + ; CHECK-O0-NEXT: DBG_VALUE [[COPY4]], 0, !9, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-O0-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]] + ; CHECK-O0-NEXT: DBG_VALUE [[COPY5]], 0, !7, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-O0-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], debug-location !10 + ; CHECK-O0-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY6]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.0) + ; CHECK-O0-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], debug-location !10 + ; CHECK-O0-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY7]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.1) + ; CHECK-O0-NEXT: [[V_CMP_LE_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_I32_e64 killed [[FLAT_LOAD_DWORD]], killed [[FLAT_LOAD_DWORD1]], implicit $exec, debug-location !10 + ; CHECK-O0-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, killed [[V_CMP_LE_I32_e64_]], implicit-def dead $scc, debug-location !10 + ; CHECK-O0-NEXT: $vcc_lo = COPY [[S_AND_B32_]], debug-location !10 + ; CHECK-O0-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc, debug-location !10 + ; CHECK-O0-NEXT: S_BRANCH %bb.1, debug-location !10 + ; CHECK-O0-NEXT: {{ $}} + ; CHECK-O0-NEXT: bb.1 (%ir-block.6): + ; CHECK-O0-NEXT: successors: %bb.3(0x80000000) + ; CHECK-O0-NEXT: {{ $}} + ; CHECK-O0-NEXT: [[FLAT_LOAD_DWORD2:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s32) from %ir.0) + ; CHECK-O0-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; CHECK-O0-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD2]], killed [[S_MOV_B32_]], 0, implicit $exec, debug-location !11 + ; CHECK-O0-NEXT: FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (store (s32) into %ir.1) + ; CHECK-O0-NEXT: S_BRANCH %bb.3, debug-location !10 + ; CHECK-O0-NEXT: {{ $}} + ; CHECK-O0-NEXT: bb.2 (%ir-block.9): + ; CHECK-O0-NEXT: successors: %bb.3(0x80000000) + ; CHECK-O0-NEXT: {{ $}} + ; CHECK-O0-NEXT: [[FLAT_LOAD_DWORD3:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY4]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (load (s32) from %ir.1) + ; CHECK-O0-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; CHECK-O0-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD3]], killed [[S_MOV_B32_1]], 0, implicit $exec, debug-location !12 + ; CHECK-O0-NEXT: FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_1]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (store (s32) into %ir.1) + ; CHECK-O0-NEXT: S_BRANCH %bb.3, debug-location !10 + ; CHECK-O0-NEXT: {{ $}} + ; CHECK-O0-NEXT: bb.3 (%ir-block.12): + ; CHECK-O0-NEXT: SI_RETURN debug-location !13 + ; + ; CHECK-O1-LABEL: name: _QFPadd + ; CHECK-O1: bb.0 (%ir-block.2): + ; CHECK-O1-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-O1-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-O1-NEXT: {{ $}} + ; CHECK-O1-NEXT: DBG_PHI $vgpr1, 6 + ; CHECK-O1-NEXT: DBG_PHI $vgpr0, 5 + ; CHECK-O1-NEXT: DBG_PHI $vgpr3, 3 + ; CHECK-O1-NEXT: DBG_PHI $vgpr2, 2 + ; CHECK-O1-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; CHECK-O1-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; CHECK-O1-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-O1-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-O1-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1, debug-instr-number 1 + ; CHECK-O1-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1, debug-instr-number 4 + ; CHECK-O1-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]] + ; CHECK-O1-NEXT: DBG_INSTR_REF !9, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, ptr), DIOpDeref(ptr)), dbg-instr-ref(2, 0), dbg-instr-ref(3, 0), debug-location !8 + ; CHECK-O1-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]] + ; CHECK-O1-NEXT: DBG_INSTR_REF !7, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, ptr), DIOpDeref(ptr)), dbg-instr-ref(5, 0), dbg-instr-ref(6, 0), debug-location !8 + ; CHECK-O1-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], debug-location !10 + ; CHECK-O1-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY6]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.0) + ; CHECK-O1-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], debug-location !10 + ; CHECK-O1-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY7]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.1) + ; CHECK-O1-NEXT: [[V_CMP_LE_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_I32_e64 killed [[FLAT_LOAD_DWORD]], killed [[FLAT_LOAD_DWORD1]], implicit $exec, debug-location !10 + ; CHECK-O1-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, killed [[V_CMP_LE_I32_e64_]], implicit-def dead $scc, debug-location !10 + ; CHECK-O1-NEXT: $vcc_lo = COPY [[S_AND_B32_]], debug-location !10 + ; CHECK-O1-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc, debug-location !10 + ; CHECK-O1-NEXT: S_BRANCH %bb.1, debug-location !10 + ; CHECK-O1-NEXT: {{ $}} + ; CHECK-O1-NEXT: bb.1 (%ir-block.6): + ; CHECK-O1-NEXT: successors: %bb.3(0x80000000) + ; CHECK-O1-NEXT: {{ $}} + ; CHECK-O1-NEXT: [[FLAT_LOAD_DWORD2:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s32) from %ir.0) + ; CHECK-O1-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; CHECK-O1-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD2]], killed [[S_MOV_B32_]], 0, implicit $exec, debug-location !11 + ; CHECK-O1-NEXT: FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (store (s32) into %ir.1) + ; CHECK-O1-NEXT: S_BRANCH %bb.3, debug-location !10 + ; CHECK-O1-NEXT: {{ $}} + ; CHECK-O1-NEXT: bb.2 (%ir-block.9): + ; CHECK-O1-NEXT: successors: %bb.3(0x80000000) + ; CHECK-O1-NEXT: {{ $}} + ; CHECK-O1-NEXT: [[FLAT_LOAD_DWORD3:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY4]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (load (s32) from %ir.1) + ; CHECK-O1-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; CHECK-O1-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD3]], killed [[S_MOV_B32_1]], 0, implicit $exec, debug-location !12 + ; CHECK-O1-NEXT: FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_1]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (store (s32) into %ir.1) + ; CHECK-O1-NEXT: {{ $}} + ; CHECK-O1-NEXT: bb.3 (%ir-block.12): + ; CHECK-O1-NEXT: SI_RETURN debug-location !13 + #dbg_declare(ptr %0, !17, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !18) + #dbg_declare(ptr %1, !19, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !18) + %3 = load i32, ptr %0, align 4, !dbg !20 + %4 = load i32, ptr %1, align 4, !dbg !20 + %5 = icmp sgt i32 %3, %4, !dbg !20 + br i1 %5, label %6, label %9, !dbg !20 + +6: ; preds = %2 + %7 = load i32, ptr %0, align 4, !dbg !21 + %8 = add i32 %7, 1, !dbg !21 + store i32 %8, ptr %1, align 4, !dbg !21 + br label %12, !dbg !20 + +9: ; preds = %2 + %10 = load i32, ptr %1, align 4, !dbg !22 + %11 = add i32 %10, 1, !dbg !22 + store i32 %11, ptr %1, align 4, !dbg !22 + br label %12, !dbg !20 + +12: ; preds = %9, %6 + ret void, !dbg !23 +} + + +!llvm.module.flags = !{!2} +!llvm.dbg.cu = !{!6} + +!2 = !{i32 2, !"Debug Info Version", i32 3} +!6 = distinct !DICompileUnit(language: DW_LANG_Fortran95, file: !7, producer: "flang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug) +!7 = !DIFile(filename: "target14.f90", directory: "") +!11 = !{i32 2, i32 0} +!12 = distinct !DISubprogram(name: "add", linkageName: "_QFPadd", scope: !7, file: !7, line: 16, type: !14, scopeLine: 16, spFlags: DISPFlagDefinition, unit: !6) +!14 = !DISubroutineType(cc: DW_CC_normal, types: !15) +!15 = !{null, !16, !16} +!16 = !DIBasicType(name: "integer", size: 32, encoding: DW_ATE_signed) +!17 = !DILocalVariable(name: "a", arg: 1, scope: !12, file: !7, line: 17, type: !16) +!18 = !DILocation(line: 16, column: 7, scope: !12) +!19 = !DILocalVariable(name: "b", arg: 2, scope: !12, file: !7, line: 17, type: !16) +!20 = !DILocation(line: 20, column: 7, scope: !12) +!21 = !DILocation(line: 21, column: 7, scope: !12) +!22 = !DILocation(line: 23, column: 7, scope: !12) +!23 = !DILocation(line: 25, column: 7, scope: !12) diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-pointer-parameters-regalloc-fast.mir b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-pointer-parameters-regalloc-fast.mir new file mode 100644 index 0000000000000..735596758c8f4 --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-pointer-parameters-regalloc-fast.mir @@ -0,0 +1,269 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -x mir -O0 -mtriple=amdgcn -mcpu=gfx1100 -start-before=regallocfast,0 -stop-after=virtregrewriter,2 -verify-machineinstrs < %s | FileCheck %s +--- | + define void @_QFPadd(ptr %0, ptr %1) #0 !dbg !3 { + #dbg_declare(ptr %0, !7, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !8) + #dbg_declare(ptr %1, !9, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !8) + %3 = load i32, ptr %0, align 4, !dbg !10 + %4 = load i32, ptr %1, align 4, !dbg !10 + %5 = icmp sle i32 %3, %4, !dbg !10 + %6 = call { i1, i32 } @llvm.amdgcn.if.i32(i1 %5), !dbg !10 + %7 = extractvalue { i1, i32 } %6, 0, !dbg !10 + %8 = extractvalue { i1, i32 } %6, 1, !dbg !10 + br i1 %7, label %15, label %Flow, !dbg !10 + + Flow: ; preds = %15, %2 + %9 = call { i1, i32 } @llvm.amdgcn.else.i32.i32(i32 %8) + %10 = extractvalue { i1, i32 } %9, 0 + %11 = extractvalue { i1, i32 } %9, 1 + br i1 %10, label %12, label %18 + + 12: ; preds = %Flow + %13 = load i32, ptr %0, align 4, !dbg !11 + %14 = add i32 %13, 1, !dbg !11 + store i32 %14, ptr %1, align 4, !dbg !11 + br label %18, !dbg !10, !amdgpu.uniform !12 + + 15: ; preds = %2 + %16 = load i32, ptr %1, align 4, !dbg !13 + %17 = add i32 %16, 1, !dbg !13 + store i32 %17, ptr %1, align 4, !dbg !13 + br label %Flow, !dbg !10, !amdgpu.uniform !12 + + 18: ; preds = %12, %Flow + call void @llvm.amdgcn.end.cf.i32(i32 %11) + ret void, !dbg !14 + } + + ; Function Attrs: nocallback nofree nounwind willreturn + declare { i1, i32 } @llvm.amdgcn.if.i32(i1) #1 + + ; Function Attrs: nocallback nofree nounwind willreturn + declare { i1, i32 } @llvm.amdgcn.else.i32.i32(i32) #1 + + ; Function Attrs: nocallback nofree nounwind willreturn + declare void @llvm.amdgcn.end.cf.i32(i32) #1 + + attributes #0 = { "target-cpu"="gfx1100" } + attributes #1 = { nocallback nofree nounwind willreturn } + + !llvm.module.flags = !{!0} + !llvm.dbg.cu = !{!1} + + !0 = !{i32 2, !"Debug Info Version", i32 3} + !1 = distinct !DICompileUnit(language: DW_LANG_Fortran95, file: !2, producer: "flang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug) + !2 = !DIFile(filename: "target14.f90", directory: "") + !3 = distinct !DISubprogram(name: "add", linkageName: "_QFPadd", scope: !2, file: !2, line: 16, type: !4, scopeLine: 16, spFlags: DISPFlagDefinition, unit: !1) + !4 = !DISubroutineType(cc: DW_CC_normal, types: !5) + !5 = !{null, !6, !6} + !6 = !DIBasicType(name: "integer", size: 32, encoding: DW_ATE_signed) + !7 = !DILocalVariable(name: "a", arg: 1, scope: !3, file: !2, line: 17, type: !6) + !8 = !DILocation(line: 16, column: 7, scope: !3) + !9 = !DILocalVariable(name: "b", arg: 2, scope: !3, file: !2, line: 17, type: !6) + !10 = !DILocation(line: 20, column: 7, scope: !3) + !11 = !DILocation(line: 21, column: 7, scope: !3) + !12 = !{} + !13 = !DILocation(line: 23, column: 7, scope: !3) + !14 = !DILocation(line: 25, column: 7, scope: !3) +... +--- +name: _QFPadd +tracksRegLiveness: true +noPhis: true +machineFunctionInfo: + scratchRSrcReg: '$private_rsrc_reg' + frameOffsetReg: '$sgpr33' + stackPtrOffsetReg: '$sgpr32' + sgprForEXECCopy: '$sgpr105' +body: | + ; CHECK-LABEL: name: _QFPadd + ; CHECK: bb.0 (%ir-block.2): + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 + ; CHECK-NEXT: S_WAITCNT 0 + ; CHECK-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr7, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.7, addrspace 5) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr7, 896 + ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 + ; CHECK-NEXT: $vgpr4 = V_MOV_B32_e32 killed $vgpr3, implicit $exec, implicit $exec + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr2, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.6, addrspace 5) + ; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $exec + ; CHECK-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.6, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr2, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.5, addrspace 5) + ; CHECK-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr0, implicit $exec, implicit $exec + ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.5, addrspace 5) + ; CHECK-NEXT: dead renamable $sgpr0 = IMPLICIT_DEF + ; CHECK-NEXT: dead renamable $sgpr0 = IMPLICIT_DEF + ; CHECK-NEXT: undef renamable $vgpr1 = KILL killed renamable $vgpr1, implicit-def $vgpr1_vgpr2, implicit $exec + ; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 killed $vgpr4, implicit $exec, implicit $exec + ; CHECK-NEXT: dead renamable $sgpr0 = IMPLICIT_DEF + ; CHECK-NEXT: dead renamable $sgpr0 = IMPLICIT_DEF + ; CHECK-NEXT: undef renamable $vgpr3 = KILL killed renamable $vgpr3, implicit-def $vgpr3_vgpr4, implicit $exec + ; CHECK-NEXT: S_WAITCNT 1015 + ; CHECK-NEXT: $vgpr4 = V_MOV_B32_e32 killed $vgpr0, implicit $exec, implicit $exec + ; CHECK-NEXT: $vgpr6 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr5_vgpr6, implicit $vgpr1_vgpr2 + ; CHECK-NEXT: $vgpr5 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $vgpr1_vgpr2, implicit $exec + ; CHECK-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr5_vgpr6, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.4, align 4, addrspace 5) + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !9, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 12), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: DBG_VALUE renamable $vgpr5_vgpr6, 0, !9, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: $vgpr6 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit-def $vgpr5_vgpr6, implicit $vgpr3_vgpr4 + ; CHECK-NEXT: $vgpr5 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr3_vgpr4, implicit $exec + ; CHECK-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr5_vgpr6, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (store (s64) into %stack.3, align 4, addrspace 5) + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !7, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 4), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: DBG_VALUE renamable $vgpr5_vgpr6, 0, !7, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr3_vgpr4, 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.0) + ; CHECK-NEXT: renamable $vgpr1 = FLAT_LOAD_DWORD killed renamable $vgpr1_vgpr2, 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.1) + ; CHECK-NEXT: S_WAITCNT 7, debug-location !10 + ; CHECK-NEXT: renamable $sgpr0 = V_CMP_LE_I32_e64 killed $vgpr0, killed $vgpr1, implicit $exec, debug-location !10 + ; CHECK-NEXT: $sgpr1 = S_MOV_B32 $exec_lo, implicit-def $exec_lo, debug-location !10 + ; CHECK-NEXT: renamable $sgpr0 = S_AND_B32 renamable $sgpr1, killed renamable $sgpr0, implicit-def dead $scc, debug-location !10 + ; CHECK-NEXT: renamable $sgpr1 = S_XOR_B32 renamable $sgpr0, killed renamable $sgpr1, implicit-def dead $scc, debug-location !10 + ; CHECK-NEXT: $vgpr7 = IMPLICIT_DEF debug-location !10 + ; CHECK-NEXT: $vgpr7 = V_WRITELANE_B32 killed $sgpr1, 0, $vgpr7, debug-location !10 + ; CHECK-NEXT: $sgpr3 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec, debug-location !10 + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr7, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr3, debug-location !10 + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !7, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 4), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !9, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 12), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed renamable $sgpr0, debug-location !10 + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec, debug-location !10 + ; CHECK-NEXT: S_BRANCH %bb.3, debug-location !10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.Flow: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !7, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 4), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !9, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 12), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: $sgpr3 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: $vgpr7 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr3 + ; CHECK-NEXT: S_WAITCNT 1015 + ; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr7, 0 + ; CHECK-NEXT: renamable $sgpr0 = S_OR_SAVEEXEC_B32 killed renamable $sgpr0, implicit-def $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: renamable $sgpr0 = S_AND_B32 $exec_lo, killed renamable $sgpr0, implicit-def dead $scc + ; CHECK-NEXT: $vgpr7 = V_WRITELANE_B32 $sgpr0, 1, $vgpr7 + ; CHECK-NEXT: $sgpr3 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr7, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr3 + ; CHECK-NEXT: $exec_lo = S_XOR_B32 $exec_lo, killed renamable $sgpr0, implicit-def dead $scc + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2 (%ir-block.12): + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !7, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 4), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !9, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 12), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s64) from %stack.4, align 4, addrspace 5) + ; CHECK-NEXT: $vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s64) from %stack.3, align 4, addrspace 5) + ; CHECK-NEXT: S_WAITCNT 1015, debug-location !11 + ; CHECK-NEXT: renamable $vgpr2 = FLAT_LOAD_DWORD renamable $vgpr2_vgpr3, 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s32) from %ir.0) + ; CHECK-NEXT: renamable $sgpr0 = S_MOV_B32 1 + ; CHECK-NEXT: S_WAITCNT 7, debug-location !11 + ; CHECK-NEXT: renamable $vgpr2 = V_ADD_U32_e64 killed $vgpr2, killed $sgpr0, 0, implicit $exec, debug-location !11 + ; CHECK-NEXT: FLAT_STORE_DWORD renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (store (s32) into %ir.1) + ; CHECK-NEXT: S_BRANCH %bb.4, debug-location !10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3 (%ir-block.15): + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !7, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 4), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !9, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 12), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr, debug-location !13 :: (load (s64) from %stack.4, align 4, addrspace 5) + ; CHECK-NEXT: S_WAITCNT 1015, debug-location !13 + ; CHECK-NEXT: renamable $vgpr2 = FLAT_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr, debug-location !13 :: (load (s32) from %ir.1) + ; CHECK-NEXT: renamable $sgpr0 = S_MOV_B32 1 + ; CHECK-NEXT: S_WAITCNT 7, debug-location !13 + ; CHECK-NEXT: renamable $vgpr2 = V_ADD_U32_e64 killed $vgpr2, killed $sgpr0, 0, implicit $exec, debug-location !13 + ; CHECK-NEXT: FLAT_STORE_DWORD renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, implicit $exec, implicit $flat_scr, debug-location !13 :: (store (s32) into %ir.1) + ; CHECK-NEXT: S_BRANCH %bb.1, debug-location !10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4 (%ir-block.18): + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !7, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 4), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: DBG_VALUE $sgpr32, 0, !9, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpReinterpret(i32), DIOpConstant(i32 12), DIOpAdd(), DIOpReinterpret(ptr addrspace(5)), DIOpDeref(ptr), DIOpDeref(ptr)), debug-location !8 + ; CHECK-NEXT: $sgpr3 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: $vgpr7 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr3 + ; CHECK-NEXT: S_WAITCNT 1015 + ; CHECK-NEXT: $sgpr0 = V_READLANE_B32 killed $vgpr7, 1 + ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, killed renamable $sgpr0, implicit-def dead $scc + ; CHECK-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec, debug-location !14 + ; CHECK-NEXT: $vgpr7 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr, debug-location !14 :: (load (s32) from %stack.7, addrspace 5) + ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, debug-location !14 + ; CHECK-NEXT: S_WAITCNT 7, debug-location !14 + ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, debug-location !14 + bb.0 (%ir-block.2): + successors: %bb.3(0x40000000), %bb.1(0x40000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + + %13:vgpr_32 = COPY $vgpr3 + %12:vgpr_32 = COPY $vgpr2 + %11:vgpr_32 = COPY $vgpr1 + %10:vgpr_32 = COPY $vgpr0 + dead %29:sgpr_32 = IMPLICIT_DEF + dead %30:sgpr_32 = IMPLICIT_DEF + undef %34.sub0:vreg_64 = COPY %12 + %34.sub1:vreg_64 = COPY %13 + dead %31:sgpr_32 = IMPLICIT_DEF + dead %32:sgpr_32 = IMPLICIT_DEF + undef %33.sub0:vreg_64 = COPY %10 + %33.sub1:vreg_64 = COPY %11 + %15:vreg_64 = COPY %34 + DBG_VALUE %15, 0, !9, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), debug-location !8 + %14:vreg_64 = COPY %33 + DBG_VALUE %14, 0, !7, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), debug-location !8 + %19:vreg_64 = COPY %33, debug-location !10 + %18:vgpr_32 = FLAT_LOAD_DWORD %19, 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.0) + %21:vreg_64 = COPY %34, debug-location !10 + %20:vgpr_32 = FLAT_LOAD_DWORD %21, 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.1) + %22:sreg_32 = V_CMP_LE_I32_e64 %18, %20, implicit $exec, debug-location !10 + %35:sreg_32 = COPY $exec_lo, implicit-def $exec_lo, debug-location !10 + %36:sreg_32 = S_AND_B32 %35, %22, implicit-def dead $scc, debug-location !10 + %0:sreg_32 = S_XOR_B32 %36, %35, implicit-def dead $scc, debug-location !10 + $exec_lo = S_MOV_B32_term %36, debug-location !10 + S_CBRANCH_EXECZ %bb.1, implicit $exec, debug-location !10 + S_BRANCH %bb.3, debug-location !10 + + bb.1.Flow: + successors: %bb.2(0x40000000), %bb.4(0x40000000) + + %37:sreg_32 = S_OR_SAVEEXEC_B32 %0, implicit-def $exec, implicit-def $scc, implicit $exec + %1:sreg_32 = S_AND_B32 $exec_lo, %37, implicit-def $scc + $exec_lo = S_XOR_B32_term $exec_lo, %1, implicit-def $scc + S_CBRANCH_EXECZ %bb.4, implicit $exec + S_BRANCH %bb.2 + + bb.2 (%ir-block.12): + successors: %bb.4(0x80000000) + + %26:vgpr_32 = FLAT_LOAD_DWORD %14, 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s32) from %ir.0) + %27:sreg_32 = S_MOV_B32 1 + %28:vgpr_32 = V_ADD_U32_e64 %26, %27, 0, implicit $exec, debug-location !11 + FLAT_STORE_DWORD %15, %28, 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (store (s32) into %ir.1) + S_BRANCH %bb.4, debug-location !10 + + bb.3 (%ir-block.15): + successors: %bb.1(0x80000000) + + %23:vgpr_32 = FLAT_LOAD_DWORD %15, 0, 0, implicit $exec, implicit $flat_scr, debug-location !13 :: (load (s32) from %ir.1) + %24:sreg_32 = S_MOV_B32 1 + %25:vgpr_32 = V_ADD_U32_e64 %23, %24, 0, implicit $exec, debug-location !13 + FLAT_STORE_DWORD %15, %25, 0, 0, implicit $exec, implicit $flat_scr, debug-location !13 :: (store (s32) into %ir.1) + S_BRANCH %bb.1, debug-location !10 + + bb.4 (%ir-block.18): + $exec_lo = S_OR_B32 $exec_lo, %1, implicit-def $scc + SI_RETURN debug-location !14 +... diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-pointer-parameters-regalloc-greedy.mir b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-pointer-parameters-regalloc-greedy.mir new file mode 100644 index 0000000000000..4387980de1094 --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-pointer-parameters-regalloc-greedy.mir @@ -0,0 +1,199 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -x mir -O1 -mtriple=amdgcn -mcpu=gfx1100 -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs < %s | FileCheck %s +--- | + define void @_QFPadd(ptr %0, ptr %1) #0 !dbg !3 { + #dbg_declare(ptr %0, !7, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !8) + #dbg_declare(ptr %1, !9, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !8) + %3 = load i32, ptr %0, align 4, !dbg !10 + %4 = load i32, ptr %1, align 4, !dbg !10 + %5 = icmp sle i32 %3, %4, !dbg !10 + %6 = call { i1, i32 } @llvm.amdgcn.if.i32(i1 %5), !dbg !10 + %7 = extractvalue { i1, i32 } %6, 0, !dbg !10 + %8 = extractvalue { i1, i32 } %6, 1, !dbg !10 + br i1 %7, label %15, label %Flow, !dbg !10 + + Flow: ; preds = %15, %2 + %9 = call { i1, i32 } @llvm.amdgcn.else.i32.i32(i32 %8) + %10 = extractvalue { i1, i32 } %9, 0 + %11 = extractvalue { i1, i32 } %9, 1 + br i1 %10, label %12, label %18 + + 12: ; preds = %Flow + %13 = load i32, ptr %0, align 4, !dbg !11 + %14 = add i32 %13, 1, !dbg !11 + store i32 %14, ptr %1, align 4, !dbg !11 + br label %18, !dbg !10, !amdgpu.uniform !12 + + 15: ; preds = %2 + %16 = load i32, ptr %1, align 4, !dbg !13 + %17 = add i32 %16, 1, !dbg !13 + store i32 %17, ptr %1, align 4, !dbg !13 + br label %Flow, !dbg !10, !amdgpu.uniform !12 + + 18: ; preds = %12, %Flow + call void @llvm.amdgcn.end.cf.i32(i32 %11) + ret void, !dbg !14 + } + + ; Function Attrs: nocallback nofree nounwind willreturn + declare { i1, i32 } @llvm.amdgcn.if.i32(i1) #1 + + ; Function Attrs: nocallback nofree nounwind willreturn + declare { i1, i32 } @llvm.amdgcn.else.i32.i32(i32) #1 + + ; Function Attrs: nocallback nofree nounwind willreturn + declare void @llvm.amdgcn.end.cf.i32(i32) #1 + + attributes #0 = { "target-cpu"="gfx1100" } + attributes #1 = { nocallback nofree nounwind willreturn } + + !llvm.module.flags = !{!0} + !llvm.dbg.cu = !{!1} + + !0 = !{i32 2, !"Debug Info Version", i32 3} + !1 = distinct !DICompileUnit(language: DW_LANG_Fortran95, file: !2, producer: "flang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug) + !2 = !DIFile(filename: "target14.f90", directory: "") + !3 = distinct !DISubprogram(name: "add", linkageName: "_QFPadd", scope: !2, file: !2, line: 16, type: !4, scopeLine: 16, spFlags: DISPFlagDefinition, unit: !1) + !4 = !DISubroutineType(cc: DW_CC_normal, types: !5) + !5 = !{null, !6, !6} + !6 = !DIBasicType(name: "integer", size: 32, encoding: DW_ATE_signed) + !7 = !DILocalVariable(name: "a", arg: 1, scope: !3, file: !2, line: 17, type: !6) + !8 = !DILocation(line: 16, column: 7, scope: !3) + !9 = !DILocalVariable(name: "b", arg: 2, scope: !3, file: !2, line: 17, type: !6) + !10 = !DILocation(line: 20, column: 7, scope: !3) + !11 = !DILocation(line: 21, column: 7, scope: !3) + !12 = !{} + !13 = !DILocation(line: 23, column: 7, scope: !3) + !14 = !DILocation(line: 25, column: 7, scope: !3) +... +--- +name: _QFPadd +tracksRegLiveness: true +noPhis: true +debugInstrRef: true +registers: + - { id: 10, class: vgpr_32, preferred-register: '', flags: [ ] } + - { id: 11, class: vgpr_32, preferred-register: '', flags: [ ] } + - { id: 12, class: vgpr_32, preferred-register: '', flags: [ ] } + - { id: 13, class: vgpr_32, preferred-register: '', flags: [ ] } + - { id: 22, class: sreg_32, preferred-register: '$vcc_lo', flags: [ ] } +liveins: + - { reg: '$vgpr0', virtual-reg: '%10' } + - { reg: '$vgpr1', virtual-reg: '%11' } + - { reg: '$vgpr2', virtual-reg: '%12' } + - { reg: '$vgpr3', virtual-reg: '%13' } +machineFunctionInfo: + scratchRSrcReg: '$private_rsrc_reg' + frameOffsetReg: '$sgpr33' + stackPtrOffsetReg: '$sgpr32' + sgprForEXECCopy: '$sgpr105' +body: | + ; CHECK-LABEL: name: _QFPadd + ; CHECK: bb.0 (%ir-block.2): + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: DBG_PHI $vgpr1, 6 + ; CHECK-NEXT: DBG_PHI $vgpr0, 5 + ; CHECK-NEXT: DBG_PHI $vgpr3, 3 + ; CHECK-NEXT: DBG_PHI $vgpr2, 2 + ; CHECK-NEXT: DBG_INSTR_REF !9, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, ptr), DIOpDeref(ptr)), dbg-instr-ref(2, 0), dbg-instr-ref(3, 0), debug-location !8 + ; CHECK-NEXT: DBG_INSTR_REF !7, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, ptr), DIOpDeref(ptr)), dbg-instr-ref(5, 0), dbg-instr-ref(6, 0), debug-location !8 + ; CHECK-NEXT: renamable $vgpr4 = FLAT_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.0) + ; CHECK-NEXT: renamable $vgpr5 = FLAT_LOAD_DWORD renamable $vgpr2_vgpr3, 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.1) + ; CHECK-NEXT: renamable $vcc_lo = V_CMP_LE_I32_e64 killed $vgpr4, killed $vgpr5, implicit $exec, debug-location !10 + ; CHECK-NEXT: renamable $sgpr0 = COPY $exec_lo, implicit-def $exec_lo, debug-location !10 + ; CHECK-NEXT: renamable $sgpr1 = S_AND_B32 renamable $sgpr0, killed renamable $vcc_lo, implicit-def dead $scc, debug-location !10 + ; CHECK-NEXT: renamable $sgpr0 = S_XOR_B32 renamable $sgpr1, killed renamable $sgpr0, implicit-def dead $scc, debug-location !10 + ; CHECK-NEXT: $exec_lo = S_MOV_B32_term killed renamable $sgpr1, debug-location !10 + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec, debug-location !10 + ; CHECK-NEXT: S_BRANCH %bb.3, debug-location !10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.Flow: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; CHECK-NEXT: liveins: $sgpr0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $sgpr0 = S_OR_SAVEEXEC_B32 killed renamable $sgpr0, implicit-def $exec, implicit-def $scc, implicit $exec + ; CHECK-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, renamable $sgpr0, implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2 (%ir-block.12): + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: liveins: $sgpr0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s32) from %ir.0) + ; CHECK-NEXT: renamable $vgpr0 = V_ADD_U32_e64 1, killed $vgpr0, 0, implicit $exec, debug-location !11 + ; CHECK-NEXT: FLAT_STORE_DWORD killed renamable $vgpr2_vgpr3, killed renamable $vgpr0, 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (store (s32) into %ir.1) + ; CHECK-NEXT: S_BRANCH %bb.4, debug-location !10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3 (%ir-block.15): + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $sgpr0, $vgpr2_vgpr3:0x000000000000000F + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vgpr0 = FLAT_LOAD_DWORD renamable $vgpr2_vgpr3, 0, 0, implicit $exec, implicit $flat_scr, debug-location !13 :: (load (s32) from %ir.1) + ; CHECK-NEXT: renamable $vgpr0 = V_ADD_U32_e64 1, killed $vgpr0, 0, implicit $exec, debug-location !13 + ; CHECK-NEXT: FLAT_STORE_DWORD killed renamable $vgpr2_vgpr3, killed renamable $vgpr0, 0, 0, implicit $exec, implicit $flat_scr, debug-location !13 :: (store (s32) into %ir.1) + ; CHECK-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $vgpr2_vgpr3 = IMPLICIT_DEF + ; CHECK-NEXT: S_BRANCH %bb.1, debug-location !10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4 (%ir-block.18): + ; CHECK-NEXT: liveins: $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, killed renamable $sgpr0, implicit-def $scc + ; CHECK-NEXT: SI_RETURN debug-location !14 + bb.0 (%ir-block.2): + successors: %bb.3(0x40000000), %bb.1(0x40000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + + DBG_PHI $vgpr1, 6 + DBG_PHI $vgpr0, 5 + DBG_PHI $vgpr3, 3 + DBG_PHI $vgpr2, 2 + undef %40.sub1:vreg_64 = COPY $vgpr3 + %40.sub0:vreg_64 = COPY $vgpr2 + undef %39.sub1:vreg_64 = COPY $vgpr1 + %39.sub0:vreg_64 = COPY $vgpr0 + DBG_INSTR_REF !9, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, ptr), DIOpDeref(ptr)), dbg-instr-ref(2, 0), dbg-instr-ref(3, 0), debug-location !8 + DBG_INSTR_REF !7, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, ptr), DIOpDeref(ptr)), dbg-instr-ref(5, 0), dbg-instr-ref(6, 0), debug-location !8 + %18:vgpr_32 = FLAT_LOAD_DWORD %39, 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.0) + %20:vgpr_32 = FLAT_LOAD_DWORD %40, 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.1) + %22:sreg_32 = V_CMP_LE_I32_e64 %18, %20, implicit $exec, debug-location !10 + %41:sreg_32 = COPY $exec_lo, implicit-def $exec_lo, debug-location !10 + %42:sreg_32 = S_AND_B32 %41, %22, implicit-def dead $scc, debug-location !10 + %0:sreg_32 = S_XOR_B32 %42, %41, implicit-def dead $scc, debug-location !10 + $exec_lo = S_MOV_B32_term %42, debug-location !10 + S_CBRANCH_EXECZ %bb.1, implicit $exec, debug-location !10 + S_BRANCH %bb.3, debug-location !10 + + bb.1.Flow: + successors: %bb.2(0x40000000), %bb.4(0x40000000) + + %1:sreg_32 = S_OR_SAVEEXEC_B32 %0, implicit-def $exec, implicit-def $scc, implicit $exec + $exec_lo = S_XOR_B32_term $exec_lo, %1, implicit-def $scc + S_CBRANCH_EXECZ %bb.4, implicit $exec + S_BRANCH %bb.2 + + bb.2 (%ir-block.12): + successors: %bb.4(0x80000000) + + %26:vgpr_32 = FLAT_LOAD_DWORD %39, 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s32) from %ir.0) + %28:vgpr_32 = V_ADD_U32_e64 1, %26, 0, implicit $exec, debug-location !11 + FLAT_STORE_DWORD %40, %28, 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (store (s32) into %ir.1) + S_BRANCH %bb.4, debug-location !10 + + bb.3 (%ir-block.15): + successors: %bb.1(0x80000000) + + %23:vgpr_32 = FLAT_LOAD_DWORD %40, 0, 0, implicit $exec, implicit $flat_scr, debug-location !13 :: (load (s32) from %ir.1) + %25:vgpr_32 = V_ADD_U32_e64 1, %23, 0, implicit $exec, debug-location !13 + FLAT_STORE_DWORD %40, %25, 0, 0, implicit $exec, implicit $flat_scr, debug-location !13 :: (store (s32) into %ir.1) + %39:vreg_64 = IMPLICIT_DEF + %40:vreg_64 = IMPLICIT_DEF + S_BRANCH %bb.1, debug-location !10 + + bb.4 (%ir-block.18): + $exec_lo = S_OR_B32 $exec_lo, %1, implicit-def $scc + SI_RETURN debug-location !14 +... diff --git a/llvm/test/DebugInfo/AMDGPU/lds-variable-location-info.ll b/llvm/test/DebugInfo/AMDGPU/lds-variable-location-info.ll new file mode 100644 index 0000000000000..c24eb2fdca5f0 --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/lds-variable-location-info.ll @@ -0,0 +1,55 @@ +; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s +@fun.variable_name = internal addrspace(3) global i32 undef, align 4, !dbg !0 + + +; CHECK: {{.*}}DW_TAG_variable +; CHECK-NEXT: DW_AT_name {{.*}}"variable_name" +; CHECK-NEXT: DW_AT_type +; CHECK-NEXT: DW_AT_decl_file +; CHECK-NEXT: DW_AT_decl_line +; Function Attrs: convergent noinline nounwind optnone +define protected amdgpu_kernel void @fun(i32 %in) #0 !dbg !2 !kernel_arg_addr_space !16 !kernel_arg_access_qual !17 !kernel_arg_type !18 !kernel_arg_base_type !18 !kernel_arg_type_qual !19 { +entry: + %in.addr = alloca i32, align 4, addrspace(5) + store i32 %in, i32 addrspace(5)* %in.addr, align 4 + call void @llvm.dbg.declare(metadata i32 addrspace(5)* %in.addr, metadata !20, metadata !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)), !dbg !21 + %0 = load i32, i32 addrspace(5)* %in.addr, align 4, !dbg !22 + store i32 %0, i32 addrspace(3)* @fun.variable_name, align 4, !dbg !23 + ret void, !dbg !24 +} + +; Function Attrs: nounwind readnone speculatable willreturn +declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 + +attributes #0 = { nounwind } + +!llvm.dbg.cu = !{!7} +!llvm.module.flags = !{!10, !11, !12, !13} +!opencl.ocl.version = !{!14} +!llvm.ident = !{!15} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression(DW_OP_constu, 2, DW_OP_swap, DW_OP_xderef)) +!1 = distinct !DIGlobalVariable(name: "variable_name", scope: !2, file: !3, line: 2, type: !6, isLocal: true, isDefinition: true) +!2 = distinct !DISubprogram(name: "fun", scope: !3, file: !3, line: 1, type: !4, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !7, retainedNodes: !8) +!3 = !DIFile(filename: "file", directory: "dir") +!4 = !DISubroutineType(cc: DW_CC_LLVM_DeviceKernel, types: !5) +!5 = !{null, !6} +!6 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!7 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !8, globals: !9, nameTableKind: None) +!8 = !{} +!9 = !{!0} +!10 = !{i32 2, !"Dwarf Version", i32 5} +!11 = !{i32 2, !"Debug Info Version", i32 3} +!12 = !{i32 1, !"wchar_size", i32 4} +!13 = !{i32 7, !"PIC Level", i32 1} +!14 = !{i32 2, i32 0} +!15 = !{!"clang"} +!16 = !{i32 0} +!17 = !{!"none"} +!18 = !{!"int"} +!19 = !{!""} +!20 = !DILocalVariable(name: "in", arg: 1, scope: !2, file: !3, line: 1, type: !6) +!21 = !DILocation(line: 1, column: 21, scope: !2) +!22 = !DILocation(line: 3, column: 19, scope: !2) +!23 = !DILocation(line: 3, column: 17, scope: !2) +!24 = !DILocation(line: 4, column: 1, scope: !2) diff --git a/llvm/test/DebugInfo/AMDGPU/live-debug-values-spill-tracking.mir b/llvm/test/DebugInfo/AMDGPU/live-debug-values-spill-tracking.mir new file mode 100644 index 0000000000000..b32094fcb93da --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/live-debug-values-spill-tracking.mir @@ -0,0 +1,73 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -run-pass livedebugvalues %s -o - -debug-only livedebugvalues 2>&1 | FileCheck %s + +# REQUIRES: asserts + +# Verify that spill tracking is disabled on amdgcn. + +# CHECK: Disabling InstrRefBasedLDV spill tracking for kern since target has too many potential stack slot indexes + +--- | + define void @kern() #0 !dbg !9 { + ret void, !dbg !15 + } + + attributes #0 = { noinline nounwind optnone "target-cpu"="gfx1100" } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!2, !3, !4, !5, !6, !7} + !llvm.ident = !{!8} + + !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 19.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) + !1 = !DIFile(filename: "t.cpp", directory: "/") + !2 = !{i32 1, !"amdhsa_code_object_version", i32 500} + !3 = !{i32 7, !"Dwarf Version", i32 5} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = !{i32 1, !"wchar_size", i32 4} + !6 = !{i32 8, !"PIC Level", i32 2} + !7 = !{i32 7, !"frame-pointer", i32 2} + !8 = !{!"clang version 19.0.0"} + !9 = distinct !DISubprogram(name: "kern", linkageName: "kern", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !12) + !10 = !DISubroutineType(types: !11) + !11 = !{} + !12 = !{!13} + !13 = !DILocalVariable(name: "var", scope: !9, file: !1, line: 1, type: !14) + !14 = !DIBasicType(name: "i32", size: 32, encoding: DW_ATE_signed) + !15 = !DILocation(line: 1, column: 1, scope: !9) + +... +--- +name: kern +tracksRegLiveness: true +debugInstrRef: true +stack: + - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 } +machineFunctionInfo: + scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3 + stackPtrOffsetReg: '$sgpr32' + hasSpilledVGPRs: true +body: | + bb.0: + ; CHECK-LABEL: name: kern + ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; CHECK-NEXT: DBG_INSTR_REF !13, !DIExpression(DIOpArg(0, i32)), dbg-instr-ref(1, 0), debug-location !15 + ; CHECK-NEXT: DBG_VALUE_LIST !13, !DIExpression(DIOpArg(0, i32)), $noreg, debug-location !15 + ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec, debug-instr-number 1, debug-location !15 + ; CHECK-NEXT: DBG_VALUE_LIST !13, !DIExpression(DIOpArg(0, i32)), $vgpr0, debug-location !15 + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, debug-location !15 :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: S_NOP 0, debug-location !15 + ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, debug-location !15 :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: S_ENDPGM 0, debug-location !15 + frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + frame-setup CFI_INSTRUCTION undefined $vgpr0 + DBG_INSTR_REF !13, !DIExpression(DIOpArg(0, i32)), dbg-instr-ref(1, 0), debug-location !15 + $vgpr0 = V_MOV_B32_e32 0, implicit $exec, debug-instr-number 1, debug-location !15 + SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, debug-location !15 :: (store (s32) into %stack.0, addrspace 5) + S_NOP 0, debug-location !15 + $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, debug-location !15 :: (load (s32) from %stack.0, addrspace 5) + S_ENDPGM 0, debug-location !15 + +... diff --git a/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll b/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll index f631c95e2d04b..60df8365e321e 100644 --- a/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll +++ b/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll @@ -13,26 +13,31 @@ ; } ; CHECK: DW_AT_name {{.*}}"FuncVar0" +; CHECK-NEXT: DW_AT_LLVM_memory_space [DW_FORM_data4] (DW_MSPACE_LLVM_private) ; CHECK-NEXT: DW_AT_decl_file ; CHECK-NEXT: DW_AT_decl_line ; CHECK-NEXT: DW_AT_type [DW_FORM_ref4] (cu + 0x{{[a-f0-9]+}} => {0x[[NONE:[a-f0-9]+]]} ; CHECK: DW_AT_name {{.*}}"FuncVar1" +; CHECK-NEXT: DW_AT_LLVM_memory_space [DW_FORM_data4] (DW_MSPACE_LLVM_private) ; CHECK-NEXT: DW_AT_decl_file ; CHECK-NEXT: DW_AT_decl_line ; CHECK-NEXT: DW_AT_type [DW_FORM_ref4] (cu + 0x{{[a-f0-9]+}} => {0x[[NONE]]} ; CHECK: DW_AT_name {{.*}}"FuncVar2" +; CHECK-NEXT: DW_AT_LLVM_memory_space [DW_FORM_data4] (DW_MSPACE_LLVM_private) ; CHECK-NEXT: DW_AT_decl_file ; CHECK-NEXT: DW_AT_decl_line -; CHECK-NEXT: DW_AT_type [DW_FORM_ref4] (cu + 0x{{[a-f0-9]+}} => {0x[[LOCAL:[a-f0-9]+]]} +; CHECK-NEXT: DW_AT_type [DW_FORM_ref4] (cu + 0x{{[a-f0-9]+}} => {0x[[LOCAL:[a-f0-9]+]]} ; CHECK: DW_AT_name {{.*}}"FuncVar3" +; CHECK-NEXT: DW_AT_LLVM_memory_space [DW_FORM_data4] (DW_MSPACE_LLVM_private) ; CHECK-NEXT: DW_AT_decl_file ; CHECK-NEXT: DW_AT_decl_line ; CHECK-NEXT: DW_AT_type [DW_FORM_ref4] (cu + 0x{{[a-f0-9]+}} => {0x[[PRIVATE:[a-f0-9]+]]} ; CHECK: DW_AT_name {{.*}}"FuncVar4" +; CHECK-NEXT: DW_AT_LLVM_memory_space [DW_FORM_data4] (DW_MSPACE_LLVM_private) ; CHECK-NEXT: DW_AT_decl_file ; CHECK-NEXT: DW_AT_decl_line ; CHECK-NEXT: DW_AT_type [DW_FORM_ref4] (cu + 0x{{[a-f0-9]+}} => {0x[[NONE]]} @@ -40,14 +45,20 @@ ; CHECK: 0x[[NONE]]: DW_TAG_pointer_type ; CHECK-NEXT: DW_AT_type ; CHECK-NOT: DW_AT_address_class +; CHECK-NOT: DW_AT_LLVM_address_space +; CHECK-NOT: DW_AT_LLVM_memory_space ; CHECK: 0x[[LOCAL]]: DW_TAG_pointer_type ; CHECK-NEXT: DW_AT_type ; CHECK-NEXT: DW_AT_address_class [DW_FORM_data4] (0x00000002) +; CHECK-NEXT: DW_AT_LLVM_address_space [DW_FORM_data4] (0x00000002 "DW_ASPACE_LLVM_AMDGPU_region") +; CHECK-NEXT: DW_AT_LLVM_memory_space [DW_FORM_data4] (DW_MSPACE_LLVM_group) ; CHECK: 0x[[PRIVATE]]: DW_TAG_pointer_type ; CHECK-NEXT: DW_AT_type ; CHECK-NEXT: DW_AT_address_class [DW_FORM_data4] (0x00000001) +; CHECK-NEXT: DW_AT_LLVM_address_space [DW_FORM_data4] (0x00000001 "DW_ASPACE_LLVM_AMDGPU_generic") +; CHECK-NEXT: DW_AT_LLVM_memory_space [DW_FORM_data4] (DW_MSPACE_LLVM_private) declare void @llvm.dbg.declare(metadata, metadata, metadata) @@ -86,19 +97,19 @@ entry: !7 = distinct !DISubprogram(name: "kernel1", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, isOptimized: false, unit: !0, retainedNodes: !2) !8 = !DISubroutineType(types: !9) !9 = !{null} -!10 = !DILocalVariable(name: "FuncVar0", scope: !7, file: !1, line: 2, type: !11) +!10 = !DILocalVariable(name: "FuncVar0", scope: !7, file: !1, line: 2, type: !11, memorySpace: DW_MSPACE_LLVM_private) !11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64) !12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) !13 = !DIExpression() !14 = !DILocation(line: 2, column: 15, scope: !7) -!15 = !DILocalVariable(name: "FuncVar1", scope: !7, file: !1, line: 3, type: !11) +!15 = !DILocalVariable(name: "FuncVar1", scope: !7, file: !1, line: 3, type: !11, memorySpace: DW_MSPACE_LLVM_private) !16 = !DILocation(line: 3, column: 17, scope: !7) -!17 = !DILocalVariable(name: "FuncVar2", scope: !7, file: !1, line: 4, type: !18) -!18 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 32, dwarfAddressSpace: 2) +!17 = !DILocalVariable(name: "FuncVar2", scope: !7, file: !1, line: 4, type: !18, memorySpace: DW_MSPACE_LLVM_private) +!18 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 32, addressSpace: 2, memorySpace: DW_MSPACE_LLVM_group) !19 = !DILocation(line: 4, column: 14, scope: !7) -!20 = !DILocalVariable(name: "FuncVar3", scope: !7, file: !1, line: 5, type: !21) -!21 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 32, dwarfAddressSpace: 1) +!20 = !DILocalVariable(name: "FuncVar3", scope: !7, file: !1, line: 5, type: !21, memorySpace: DW_MSPACE_LLVM_private) +!21 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 32, addressSpace: 1, memorySpace: DW_MSPACE_LLVM_private) !22 = !DILocation(line: 5, column: 16, scope: !7) -!23 = !DILocalVariable(name: "FuncVar4", scope: !7, file: !1, line: 6, type: !11) +!23 = !DILocalVariable(name: "FuncVar4", scope: !7, file: !1, line: 6, type: !11, memorySpace: DW_MSPACE_LLVM_private) !24 = !DILocation(line: 6, column: 8, scope: !7) !25 = !DILocation(line: 7, column: 1, scope: !7) diff --git a/llvm/test/DebugInfo/AMDGPU/reg-sequence-salvage.ll b/llvm/test/DebugInfo/AMDGPU/reg-sequence-salvage.ll new file mode 100644 index 0000000000000..f284a49dd9249 --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/reg-sequence-salvage.ll @@ -0,0 +1,51 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -start-before=amdgpu-isel -stop-after=amdgpu-isel %s -o - | FileCheck %s + +define i64 @test(ptr addrspace(1) %p) !dbg !11 { + ; CHECK-LABEL: name: test + ; CHECK: bb.0 (%ir-block.0): + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]] + ; CHECK-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD killed [[COPY2]], 0, 0, implicit $exec, debug-instr-number 1 :: (load (s32) from %ir.p, addrspace 1) + ; CHECK-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 31, [[GLOBAL_LOAD_DWORD]], implicit $exec, debug-instr-number 2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[V_ASHRREV_I32_e64_]] + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[GLOBAL_LOAD_DWORD]], %subreg.sub0, killed [[COPY3]], %subreg.sub1 + ; CHECK-NEXT: DBG_INSTR_REF !17, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, i64)), dbg-instr-ref(1, 0), dbg-instr-ref(2, 0), debug-location !18 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1 + ; CHECK-NEXT: $vgpr0 = COPY [[GLOBAL_LOAD_DWORD]] + ; CHECK-NEXT: $vgpr1 = COPY [[COPY4]] + ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 + %load = load i32, ptr addrspace(1) %p, align 4 + %conv = sext i32 %load to i64 + #dbg_value(i64 %conv, !17, !DIExpression(DIOpArg(0, i64)), !18) + ret i64 %conv +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7} +!opencl.ocl.version = !{!8} +!llvm.ident = !{!9, !10} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 21.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: NoDebug) +!1 = !DIFile(filename: "t.cpp", directory: "/") +!2 = !{i32 1, !"amdhsa_code_object_version", i32 600} +!3 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"} +!4 = !{i32 7, !"Dwarf Version", i32 5} +!5 = !{i32 2, !"Debug Info Version", i32 3} +!6 = !{i32 1, !"wchar_size", i32 4} +!7 = !{i32 8, !"PIC Level", i32 2} +!8 = !{i32 2, i32 0} +!9 = !{!"clang version 21.0.0"} +!10 = !{!"clang version 18.0.0"} +!11 = distinct !DISubprogram(name: "test", linkageName: "test", scope: !1, file: !1, line: 6, type: !12, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !16) +!12 = !DISubroutineType(types: !13) +!13 = !{!15, !14} +!14 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !15, size: 64) +!15 = !DIBasicType(name: "long", size: 64, encoding: DW_ATE_signed) +!16 = !{!17} +!17 = !DILocalVariable(name: "var", scope: !11, file: !1, line: 8, type: !15) +!18 = !DILocation(line: 0, scope: !11) diff --git a/llvm/test/DebugInfo/COFF/global_rust.ll b/llvm/test/DebugInfo/COFF/global_rust.ll index 526e7cf16f254..ee5fd64daa06c 100644 --- a/llvm/test/DebugInfo/COFF/global_rust.ll +++ b/llvm/test/DebugInfo/COFF/global_rust.ll @@ -104,7 +104,7 @@ attributes #2 = { nofree nosync nounwind readnone speculatable willreturn } !3 = !DICompositeType(tag: DW_TAG_structure_type, name: "impl$::vtable_type$", file: !2, size: 256, align: 64, flags: DIFlagArtificial, elements: !4, vtableHolder: !14, templateParams: !8, identifier: "4a384a40e448d9d82ef8cb395527d231") !4 = !{!5, !9, !12, !13} !5 = !DIDerivedType(tag: DW_TAG_member, name: "drop_in_place", scope: !3, file: !2, baseType: !6, size: 64, align: 64) -!6 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "ptr_const$ >", baseType: !7, size: 64, align: 64, dwarfAddressSpace: 0) +!6 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "ptr_const$ >", baseType: !7, size: 64, align: 64, addressSpace: 0) !7 = !DICompositeType(tag: DW_TAG_structure_type, name: "tuple$<>", file: !2, align: 8, elements: !8, identifier: "65e33f3994015bcf158992dbe0323c0") !8 = !{} !9 = !DIDerivedType(tag: DW_TAG_member, name: "size", scope: !3, file: !2, baseType: !10, size: 64, align: 64, offset: 64) @@ -126,7 +126,7 @@ attributes #2 = { nofree nosync nounwind readnone speculatable willreturn } !25 = !DINamespace(name: "core", scope: null) !26 = !DISubroutineType(types: !27) !27 = !{null, !28} -!28 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "ptr_mut$", baseType: !14, size: 64, align: 64, dwarfAddressSpace: 0) +!28 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "ptr_mut$", baseType: !14, size: 64, align: 64, addressSpace: 0) !29 = !{!30} !30 = !DILocalVariable(arg: 1, scope: !22, file: !23, line: 487, type: !28) !31 = !{!32} @@ -138,7 +138,7 @@ attributes #2 = { nofree nosync nounwind readnone speculatable willreturn } !37 = !DINamespace(name: "global_rust", scope: null) !38 = !DISubroutineType(types: !39) !39 = !{null, !40} -!40 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "ref$", baseType: !14, size: 64, align: 64, dwarfAddressSpace: 0) +!40 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "ref$", baseType: !14, size: 64, align: 64, addressSpace: 0) !41 = !{!42} !42 = !DILocalVariable(name: "self", arg: 1, scope: !34, file: !35, line: 3, type: !40) !43 = !{!44} @@ -150,10 +150,10 @@ attributes #2 = { nofree nosync nounwind readnone speculatable willreturn } !49 = !DICompositeType(tag: DW_TAG_structure_type, name: "ref$ >", file: !2, size: 128, align: 64, elements: !50, templateParams: !8, identifier: "2c39c7f196ba93e4e4fbfefe6e460dfb") !50 = !{!51, !54} !51 = !DIDerivedType(tag: DW_TAG_member, name: "pointer", scope: !49, file: !2, baseType: !52, size: 64, align: 64) -!52 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !53, size: 64, align: 64, dwarfAddressSpace: 0) +!52 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !53, size: 64, align: 64, addressSpace: 0) !53 = !DICompositeType(tag: DW_TAG_structure_type, name: "dyn$", file: !2, align: 8, elements: !8, identifier: "dc5af67081d01f4b3cf3420f9b3ec7fa") !54 = !DIDerivedType(tag: DW_TAG_member, name: "vtable", scope: !49, file: !2, baseType: !55, size: 64, align: 64, offset: 64) -!55 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "ref$ >", baseType: !56, size: 64, align: 64, dwarfAddressSpace: 0) +!55 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "ref$ >", baseType: !56, size: 64, align: 64, addressSpace: 0) !56 = !DICompositeType(tag: DW_TAG_array_type, baseType: !10, size: 192, align: 64, elements: !57) !57 = !{!58} !58 = !DISubrange(count: 3, lowerBound: 0) diff --git a/llvm/test/DebugInfo/Generic/address_space_rvalue.ll b/llvm/test/DebugInfo/Generic/address_space_rvalue.ll index ff39188b6419c..38798c11b5667 100644 --- a/llvm/test/DebugInfo/Generic/address_space_rvalue.ll +++ b/llvm/test/DebugInfo/Generic/address_space_rvalue.ll @@ -16,7 +16,7 @@ !0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) !1 = !DIGlobalVariable(name: "x", scope: null, file: !2, line: 2, type: !3, isLocal: false, isDefinition: true) !2 = !DIFile(filename: "test.cpp", directory: "/") -!3 = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: !4, size: 64, align: 64, dwarfAddressSpace: 1) +!3 = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: !4, size: 64, align: 64, addressSpace: 1) !4 = !DIBasicType(name: "long long unsigned int", size: 64, encoding: DW_ATE_unsigned) !5 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !2, producer: "clang version 3.5.0 ", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !6, retainedTypes: !6, globals: !7, imports: !6) !6 = !{} diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/parse-and-verify/distinct.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/parse-and-verify/distinct.ll index 8b8496d0f9783..a28dbd68b3674 100644 --- a/llvm/test/DebugInfo/Generic/assignment-tracking/parse-and-verify/distinct.ll +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/parse-and-verify/distinct.ll @@ -4,7 +4,7 @@ ;; Check that badly formed assignment tracking metadata is caught either ;; while parsing or by the verifier. -; CHECK: error: missing 'distinct', required for !DIAssignID() +; CHECK: error: missing 'distinct', required for !DIAssignID !1 = !DIAssignID() !1000 = !{i32 7, !"debug-info-assignment-tracking", i1 true} diff --git a/llvm/test/DebugInfo/Generic/structor-declaration-linkage-names.ll b/llvm/test/DebugInfo/Generic/structor-declaration-linkage-names.ll index 1096cde5f4142..7fca9c83bfef1 100644 --- a/llvm/test/DebugInfo/Generic/structor-declaration-linkage-names.ll +++ b/llvm/test/DebugInfo/Generic/structor-declaration-linkage-names.ll @@ -1,6 +1,8 @@ ; REQUIRES: aarch64-registered-target ; RUN: %llc_dwarf < %s -filetype=obj | llvm-dwarfdump -debug-info - | FileCheck %s +; REQUIRES: ci_stability + ; Make sure we attach DW_AT_linkage_name on function declarations but only ; attach it on definitions if the value is different than on the declaration. diff --git a/llvm/test/DebugInfo/Inputs/heterogeneous-strip-debug.bc b/llvm/test/DebugInfo/Inputs/heterogeneous-strip-debug.bc new file mode 100644 index 0000000000000..5352441bec0f9 Binary files /dev/null and b/llvm/test/DebugInfo/Inputs/heterogeneous-strip-debug.bc differ diff --git a/llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll b/llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll index fa42481016540..1b69d7a5ece06 100644 --- a/llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll +++ b/llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda | FileCheck %s ; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64-nvidia-cuda | %ptxas-verify %} - ; CHECK: .target sm_30, debug ; CHECK: .visible .func use_dbg_declare() diff --git a/llvm/test/DebugInfo/NVPTX/debug-info.ll b/llvm/test/DebugInfo/NVPTX/debug-info.ll index 9ce0b73a25181..0e1f57676d8be 100644 --- a/llvm/test/DebugInfo/NVPTX/debug-info.ll +++ b/llvm/test/DebugInfo/NVPTX/debug-info.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mattr=+ptx70 | FileCheck %s -; RUN: %if ptxas-isa-7.0 %{ llc < %s -mtriple=nvptx64-nvidia-cuda -mattr=+ptx70 | %ptxas-verify %} - +; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64-nvidia-cuda -mattr=+ptx70 | %ptxas-verify %} ; // Bitcode in this test case is reduced version of compiled code below: ;__device__ inline void res(float x, float y, ptr res) { *res = x + y; } ; @@ -585,12 +584,12 @@ if.end: ; preds = %if.then, %entry ; CHECK-NEXT: } ; CHECK-NEXT: .section .debug_info ; CHECK-NEXT: { -; CHECK-NEXT: .b32 2404 // Length of Unit +; CHECK-NEXT: .b32 2417 // Length of Unit ; CHECK-NEXT: .b8 2 // DWARF version number ; CHECK-NEXT: .b8 0 ; CHECK-NEXT: .b32 .debug_abbrev // Offset Into Abbrev. Section ; CHECK-NEXT: .b8 8 // Address Size (in bytes) -; CHECK-NEXT: .b8 1 // Abbrev [1] 0xb:0x95d DW_TAG_compile_unit +; CHECK-NEXT: .b8 1 // Abbrev [1] 0xb:0x96a DW_TAG_compile_unit ; CHECK-NEXT: .b8 0 // DW_AT_producer ; CHECK-NEXT: .b8 4 // DW_AT_language ; CHECK-NEXT: .b8 0 @@ -2480,7 +2479,7 @@ if.end: ; preds = %if.then, %entry ; CHECK-NEXT: .b8 4 // DW_AT_byte_size ; CHECK-NEXT: .b8 12 // Abbrev [12] 0x83d:0x5 DW_TAG_pointer_type ; CHECK-NEXT: .b32 2100 // DW_AT_type -; CHECK-NEXT: .b8 23 // Abbrev [23] 0x842:0xe5 DW_TAG_subprogram +; CHECK-NEXT: .b8 23 // Abbrev [23] 0x842:0xf2 DW_TAG_subprogram ; CHECK-NEXT: .b64 $L__func_begin0 // DW_AT_low_pc ; CHECK-NEXT: .b64 $L__func_end0 // DW_AT_high_pc ; CHECK-NEXT: .b8 1 // DW_AT_frame_base @@ -2521,7 +2520,7 @@ if.end: ; preds = %if.then, %entry ; CHECK-NEXT: .b8 0 ; CHECK-NEXT: .b8 1 // DW_AT_decl_file ; CHECK-NEXT: .b8 5 // DW_AT_decl_line -; CHECK-NEXT: .b32 2400 // DW_AT_type +; CHECK-NEXT: .b32 2413 // DW_AT_type ; CHECK-NEXT: .b8 25 // Abbrev [25] 0x87d:0xd DW_TAG_formal_parameter ; CHECK-NEXT: .b32 $L__debug_loc0 // DW_AT_location ; CHECK-NEXT: .b8 97 // DW_AT_name @@ -2563,7 +2562,7 @@ if.end: ; preds = %if.then, %entry ; CHECK-NEXT: .b8 0 ; CHECK-NEXT: .b8 1 // DW_AT_decl_file ; CHECK-NEXT: .b8 6 // DW_AT_decl_line -; CHECK-NEXT: .b32 2400 // DW_AT_type +; CHECK-NEXT: .b32 2413 // DW_AT_type ; CHECK-NEXT: .b8 27 // Abbrev [27] 0x8b9:0x18 DW_TAG_inlined_subroutine ; CHECK-NEXT: .b32 691 // DW_AT_abstract_origin ; CHECK-NEXT: .b64 $L__tmp3 // DW_AT_low_pc @@ -2585,7 +2584,7 @@ if.end: ; preds = %if.then, %entry ; CHECK-NEXT: .b8 1 // DW_AT_call_file ; CHECK-NEXT: .b8 6 // DW_AT_call_line ; CHECK-NEXT: .b8 37 // DW_AT_call_column -; CHECK-NEXT: .b8 28 // Abbrev [28] 0x901:0x25 DW_TAG_inlined_subroutine +; CHECK-NEXT: .b8 28 // Abbrev [28] 0x901:0x32 DW_TAG_inlined_subroutine ; CHECK-NEXT: .b32 2050 // DW_AT_abstract_origin ; CHECK-NEXT: .b64 $L__tmp11 // DW_AT_low_pc ; CHECK-NEXT: .b64 $L__tmp12 // DW_AT_high_pc @@ -2601,19 +2600,29 @@ if.end: ; preds = %if.then, %entry ; CHECK-NEXT: .b8 149 ; CHECK-NEXT: .b8 1 ; CHECK-NEXT: .b32 2079 // DW_AT_abstract_origin +; CHECK-NEXT: .b8 29 // Abbrev [29] 0x925:0xd DW_TAG_formal_parameter +; CHECK-NEXT: .b8 2 // DW_AT_address_class +; CHECK-NEXT: .b8 6 // DW_AT_location +; CHECK-NEXT: .b8 144 +; CHECK-NEXT: .b8 183 +; CHECK-NEXT: .b8 200 +; CHECK-NEXT: .b8 201 +; CHECK-NEXT: .b8 171 +; CHECK-NEXT: .b8 2 +; CHECK-NEXT: .b32 2088 // DW_AT_abstract_origin ; CHECK-NEXT: .b8 0 // End Of Children Mark ; CHECK-NEXT: .b8 0 // End Of Children Mark -; CHECK-NEXT: .b8 30 // Abbrev [30] 0x927:0xd DW_TAG_namespace +; CHECK-NEXT: .b8 30 // Abbrev [30] 0x934:0xd DW_TAG_namespace ; CHECK-NEXT: .b8 115 // DW_AT_name ; CHECK-NEXT: .b8 116 ; CHECK-NEXT: .b8 100 ; CHECK-NEXT: .b8 0 -; CHECK-NEXT: .b8 31 // Abbrev [31] 0x92c:0x7 DW_TAG_imported_declaration +; CHECK-NEXT: .b8 31 // Abbrev [31] 0x939:0x7 DW_TAG_imported_declaration ; CHECK-NEXT: .b8 4 // DW_AT_decl_file ; CHECK-NEXT: .b8 202 // DW_AT_decl_line -; CHECK-NEXT: .b32 2356 // DW_AT_import +; CHECK-NEXT: .b32 2369 // DW_AT_import ; CHECK-NEXT: .b8 0 // End Of Children Mark -; CHECK-NEXT: .b8 32 // Abbrev [32] 0x934:0x1b DW_TAG_subprogram +; CHECK-NEXT: .b8 32 // Abbrev [32] 0x941:0x1b DW_TAG_subprogram ; CHECK-NEXT: .b8 95 // DW_AT_MIPS_linkage_name ; CHECK-NEXT: .b8 90 ; CHECK-NEXT: .b8 76 @@ -2629,12 +2638,12 @@ if.end: ; preds = %if.then, %entry ; CHECK-NEXT: .b8 0 ; CHECK-NEXT: .b8 4 // DW_AT_decl_file ; CHECK-NEXT: .b8 44 // DW_AT_decl_line -; CHECK-NEXT: .b32 2383 // DW_AT_type +; CHECK-NEXT: .b32 2396 // DW_AT_type ; CHECK-NEXT: .b8 1 // DW_AT_declaration -; CHECK-NEXT: .b8 7 // Abbrev [7] 0x949:0x5 DW_TAG_formal_parameter -; CHECK-NEXT: .b32 2383 // DW_AT_type +; CHECK-NEXT: .b8 7 // Abbrev [7] 0x956:0x5 DW_TAG_formal_parameter +; CHECK-NEXT: .b32 2396 // DW_AT_type ; CHECK-NEXT: .b8 0 // End Of Children Mark -; CHECK-NEXT: .b8 10 // Abbrev [10] 0x94f:0x11 DW_TAG_base_type +; CHECK-NEXT: .b8 10 // Abbrev [10] 0x95c:0x11 DW_TAG_base_type ; CHECK-NEXT: .b8 108 // DW_AT_name ; CHECK-NEXT: .b8 111 ; CHECK-NEXT: .b8 110 @@ -2651,7 +2660,7 @@ if.end: ; preds = %if.then, %entry ; CHECK-NEXT: .b8 0 ; CHECK-NEXT: .b8 5 // DW_AT_encoding ; CHECK-NEXT: .b8 8 // DW_AT_byte_size -; CHECK-NEXT: .b8 10 // Abbrev [10] 0x960:0x7 DW_TAG_base_type +; CHECK-NEXT: .b8 10 // Abbrev [10] 0x96d:0x7 DW_TAG_base_type ; CHECK-NEXT: .b8 105 // DW_AT_name ; CHECK-NEXT: .b8 110 ; CHECK-NEXT: .b8 116 diff --git a/llvm/test/DebugInfo/X86/dbg-rust-valid-enum-as-scope.ll b/llvm/test/DebugInfo/X86/dbg-rust-valid-enum-as-scope.ll index 263cbeee2a01f..b50e93683bc27 100644 --- a/llvm/test/DebugInfo/X86/dbg-rust-valid-enum-as-scope.ll +++ b/llvm/test/DebugInfo/X86/dbg-rust-valid-enum-as-scope.ll @@ -69,7 +69,7 @@ attributes #1 = { nofree nosync nounwind readnone speculatable willreturn } !14 = !DIFile(filename: "a.rs", directory: "/Users/augie", checksumkind: CSK_MD5, checksum: "ab4ce84c27ef6fd0be1ef78e8131faa8") !15 = !DISubroutineType(types: !16) !16 = !{null, !17} -!17 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&E", baseType: !6, size: 64, align: 64, dwarfAddressSpace: 0) +!17 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&E", baseType: !6, size: 64, align: 64, addressSpace: 0) !18 = !{!19} !19 = !DILocalVariable(name: "self", arg: 1, scope: !13, file: !14, line: 3, type: !17) !20 = !{} diff --git a/llvm/test/DebugInfo/X86/dynamic-bitfield.ll b/llvm/test/DebugInfo/X86/dynamic-bitfield.ll index f8935977c64e7..451ec41d2fd58 100644 --- a/llvm/test/DebugInfo/X86/dynamic-bitfield.ll +++ b/llvm/test/DebugInfo/X86/dynamic-bitfield.ll @@ -1,6 +1,7 @@ ; The use of llvm-dis here tests that round-tripping the IR works ; correctly for the expression case. ; RUN: llvm-as < %s | llvm-dis | llc -mtriple=x86_64 -O0 -filetype=obj -o - | llvm-dwarfdump -v -debug-info - | FileCheck %s +; XFAIL: * ; A basic test of using a DIExpression for DW_AT_data_bit_offset and ; DW_AT_bit_size. diff --git a/llvm/test/DebugInfo/X86/stack_adjustments_trigger_cfa_frame_base.ll b/llvm/test/DebugInfo/X86/stack_adjustments_trigger_cfa_frame_base.ll index 914a7a324dfeb..f475b468dd62a 100644 --- a/llvm/test/DebugInfo/X86/stack_adjustments_trigger_cfa_frame_base.ll +++ b/llvm/test/DebugInfo/X86/stack_adjustments_trigger_cfa_frame_base.ll @@ -150,7 +150,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) !9 = !DINamespace(name: "core", scope: null) !10 = !DISubroutineType(types: !11) !11 = !{!12, !12} -!12 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&()", baseType: !13, size: 64, align: 64, dwarfAddressSpace: 0) +!12 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&()", baseType: !13, size: 64, align: 64, addressSpace: 0) !13 = !DIBasicType(name: "()", encoding: DW_ATE_unsigned) !14 = !{!15} !15 = !DILocalVariable(name: "dummy", arg: 1, scope: !6, file: !7, line: 294, type: !12) @@ -165,7 +165,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) !24 = distinct !DISubprogram(name: "black_box<&mut ()>", linkageName: "_ZN4core4hint9black_box17hff24a8f6cdc261d0E", scope: !8, file: !7, line: 294, type: !25, scopeLine: 294, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !4, templateParams: !30, retainedNodes: !28) !25 = !DISubroutineType(types: !26) !26 = !{!27, !27} -!27 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&mut ()", baseType: !13, size: 64, align: 64, dwarfAddressSpace: 0) +!27 = !DIDerivedType(tag: DW_TAG_pointer_type, name: "&mut ()", baseType: !13, size: 64, align: 64, addressSpace: 0) !28 = !{!29} !29 = !DILocalVariable(name: "dummy", arg: 1, scope: !24, file: !7, line: 294, type: !27) !30 = !{!31} diff --git a/llvm/test/DebugInfo/heterogeneous-diop-in-diexpression-conversion.ll b/llvm/test/DebugInfo/heterogeneous-diop-in-diexpression-conversion.ll new file mode 100644 index 0000000000000..95a118d0d0a15 --- /dev/null +++ b/llvm/test/DebugInfo/heterogeneous-diop-in-diexpression-conversion.ll @@ -0,0 +1,72 @@ +; RUN: llc --filetype=obj --fast-isel=true < %s | llvm-dwarfdump -debug-info - | FileCheck %s + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @main() !dbg !5 { + + ; CHECK: 0x{{[0-9a-z]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (DW_OP_constu 0xff, DW_OP_dup, DW_OP_constu 0x7, DW_OP_shr, DW_OP_lit0, DW_OP_not, DW_OP_mul, DW_OP_constu 0x8, DW_OP_shl, DW_OP_or, DW_OP_stack_value) + ; CHECK-NEXT: DW_AT_name ("sext_i8") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type (0x{{[0-9a-z]+}} "i32") + #dbg_value(i8 -1, !10, !DIExpression(DIOpArg(0, i8), DIOpSExt(i32)), !15) + + ; CHECK: 0x{{[0-9a-z]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (DW_OP_constu 0xff, DW_OP_constu 0xff, DW_OP_and, DW_OP_stack_value) + ; CHECK-NEXT: DW_AT_name ("zext_i8") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type (0x{{[0-9a-z]+}} "i32") + #dbg_value(i8 -1, !11, !DIExpression(DIOpArg(0, i8), DIOpZExt(i32)), !15) + + ; CHECK: 0x{{[0-9a-z]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (DW_OP_constu 0xfffffffffffffff6, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_stack_value) + ; CHECK-NEXT: DW_AT_name ("trunc_i64") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type (0x{{[0-9a-z]+}} "i32") + #dbg_value(i64 -10, !12, !DIExpression(DIOpArg(0, i64), DIOpConvert(i32)), !15) + + ; CHECK: 0x{{[0-9a-z]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (DW_OP_constu 0xff, DW_OP_dup, DW_OP_constu 0x7, DW_OP_shr, DW_OP_lit0, DW_OP_not, DW_OP_mul, DW_OP_constu 0x8, DW_OP_shl, DW_OP_or, DW_OP_lit1, DW_OP_plus, DW_OP_stack_value) + ; CHECK-NEXT: DW_AT_name ("add_const") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type (0x{{[0-9a-z]+}} "i32") + #dbg_value(i8 -1, !13, !DIExpression(DIOpArg(0, i8), DIOpSExt(i32), DIOpConstant(i32 1), DIOpAdd()), !15) + + ; CHECK: 0x{{[0-9a-z]+}}: DW_TAG_variable + ; CHECK-NEXT: DW_AT_location (DW_OP_constu 0x2a, DW_OP_stack_value) + ; CHECK-NEXT: DW_AT_name ("noop_convert") + ; CHECK-NEXT: DW_AT_decl_file + ; CHECK-NEXT: DW_AT_decl_line + ; CHECK-NEXT: DW_AT_type (0x{{[0-9a-z]+}} "i32") + #dbg_value(i32 42, !14, !DIExpression(DIOpArg(0, i32), DIOpConvert(i32)), !15) + + ret void, !dbg !15 +} + +declare void @llvm.dbg.value(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.debugify = !{!2, !3} +!llvm.module.flags = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) +!1 = !DIFile(filename: "t.c", directory: "/") +!2 = !{i32 8} +!3 = !{i32 7} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = distinct !DISubprogram(name: "test", linkageName: "test", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) +!6 = !DISubroutineType(types: !7) +!7 = !{} +!8 = !{!10, !11, !12, !13} +!9 = !DIBasicType(name: "i32", size: 32, encoding: DW_ATE_signed) +!10 = !DILocalVariable(name: "sext_i8", scope: !5, file: !1, line: 1, type: !9) +!11 = !DILocalVariable(name: "zext_i8", scope: !5, file: !1, line: 2, type: !9) +!12 = !DILocalVariable(name: "trunc_i64", scope: !5, file: !1, line: 3, type: !9) +!13 = !DILocalVariable(name: "add_const", scope: !5, file: !1, line: 4, type: !9) +!14 = !DILocalVariable(name: "noop_convert", scope: !5, file: !1, line: 4, type: !9) +!15 = !DILocation(line: 1, column: 1, scope: !5) diff --git a/llvm/test/DebugInfo/heterogeneous-diop-in-diexpression.ll b/llvm/test/DebugInfo/heterogeneous-diop-in-diexpression.ll new file mode 100644 index 0000000000000..c8b81bb1e90d5 --- /dev/null +++ b/llvm/test/DebugInfo/heterogeneous-diop-in-diexpression.ll @@ -0,0 +1,101 @@ +; RUN: opt -S -passes=verify < %s | FileCheck %s +; RUN: llc --filetype=obj --relocation-model=pic -fast-isel=false < %s | llvm-dwarfdump -v -debug-info - | FileCheck --check-prefix=DWARF %s +; RUN: llc --filetype=obj --relocation-model=pic -fast-isel=true < %s | llvm-dwarfdump -v -debug-info - | FileCheck --check-prefix=DWARF %s + +; TODO: Test for global isel + +; DWARF: DW_TAG_variable +; DWARF: DW_AT_name [DW_FORM_strx1] (indexed ([[#%x,]]) string = "glob") +; DWARF: DW_AT_location [DW_FORM_exprloc] (DW_OP_addrx 0x0, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address) + +; DWARF: DW_TAG_variable +; DWARF: DW_AT_name [DW_FORM_strx1] (indexed ([[#%x,]]) string = "glob_fragmented") +; DWARF: DW_AT_location [DW_FORM_exprloc] (DW_OP_addrx 0x1, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address, DW_OP_piece 0x2, DW_OP_addrx 0x2, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address, DW_OP_piece 0x2) + +; DWARF: DW_TAG_variable +; DWARF: DW_AT_location [DW_FORM_loclistx] (indexed (0x[[#%x,]]) loclist = 0x[[#%x,]]: +; DWARF: [0x[[#%x,]], 0x[[#%x,]]) ".text": DW_OP_reg6 RBP, DW_OP_deref_size 0x8, DW_OP_consts -4, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address +; DWARF: DW_AT_name [DW_FORM_strx1] (indexed ([[#%x,]]) string = "var") + +; DWARF: DW_TAG_variable +; DWARF: DW_AT_location [DW_FORM_loclistx] (indexed (0x[[#%x,]]) loclist = 0x[[#%x,]]: +; DWARF: [0x[[#%x,]], 0x[[#%x,]]) ".text": DW_OP_reg6 RBP, DW_OP_deref_size 0x8, DW_OP_consts -8, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address +; DWARF: [0x[[#%x,]], 0x[[#%x,]]) ".text": DW_OP_reg6 RBP, DW_OP_deref_size 0x8, DW_OP_consts -8, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address, DW_OP_piece 0x2, DW_OP_reg6 RBP, DW_OP_deref_size 0x8, DW_OP_consts -6, DW_OP_plus, DW_OP_stack_value, DW_OP_deref_size 0x8, DW_OP_lit0, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address, DW_OP_piece 0x2) +; DWARF: DW_AT_name [DW_FORM_strx1] (indexed ([[#%x,]]) string = "var_fragmented") + +; ModuleID = '' +source_filename = "" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +declare void @ex() + +; CHECK: @glob = {{.*}}, !dbg ![[#GLOB_GVE:]] +@glob = global i32 42, align 4, !dbg !0 + +; CHECK: @glob_fragmented.lo = {{.*}}, !dbg ![[#GLOB_FRAGMENTED_LO_GVE:]] +@glob_fragmented.lo = global i16 42, align 2, !dbg !23 +; CHECK: @glob_fragmented.hi = {{.*}}, !dbg ![[#GLOB_FRAGMENTED_HI_GVE:]] +@glob_fragmented.hi = global i16 42, align 2, !dbg !24 + +; Function Attrs: noinline nounwind optnone uwtable +define dso_local void @func() #0 !dbg !13 { +entry: + %var = alloca i32, align 4 + ; CHECK: #dbg_value(!DIArgList(ptr %var), ![[#]], !DIExpression(DIOpArg(0, ptr), DIOpFragment(1, 2), DIOpDeref(i32)), + #dbg_value(!DIArgList(ptr %var), !18, !DIExpression(DIOpArg(0, ptr), DIOpFragment(1, 2), DIOpDeref(i32)), !19) + ; CHECK: #dbg_value(ptr %var, ![[#VAR:]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), + #dbg_value(ptr %var, !18, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), !19) + %var_fragmented.lo = alloca i16, align 2 + %var_fragmented.hi = alloca i16, align 2 + ; CHECK: #dbg_value(ptr %var_fragmented.lo, ![[#VAR_FRAGMENTED:]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpFragment(0, 16)), + #dbg_value(ptr %var_fragmented.lo, !22, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpFragment(0, 16)), !19) + call void @ex() + ; CHECK: #dbg_value(ptr %var_fragmented.hi, ![[#VAR_FRAGMENTED]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpFragment(16, 16)), + #dbg_value(ptr %var_fragmented.hi, !22, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpFragment(16, 16)), !19) + ret void, !dbg !20 +} + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "target-cpu"="x86-64" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!5, !6, !7, !8, !9, !10, !11} +!llvm.ident = !{!12} + +; CHECK-DAG: ![[#GLOB_GVE]] = !DIGlobalVariableExpression(var: ![[#GLOB:]], expr: !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32))) +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32))) +; CHECK-DAG: ![[#GLOB]] = distinct !DIGlobalVariable(name: "glob", +!1 = distinct !DIGlobalVariable(name: "glob", scope: !2, file: !3, line: 1, type: !4, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C11, file: !3, producer: "clang version 19.0.0git (git@github.com:slinder1/llvm-project.git e4263955383c3e364bd752d02fc44cf5f22143ef)", isOptimized: false, runtimeVersion: 0, globals: !21, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "-", directory: "/home/slinder1/llvm-project/main", checksumkind: CSK_MD5, checksum: "9e51994790e4105fa7153a61c95a824f") +!4 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!5 = !{i32 7, !"Dwarf Version", i32 5} +!6 = !{i32 2, !"Debug Info Version", i32 3} +!7 = !{i32 1, !"wchar_size", i32 4} +!8 = !{i32 8, !"PIC Level", i32 2} +!9 = !{i32 7, !"PIE Level", i32 2} +!10 = !{i32 7, !"uwtable", i32 2} +!11 = !{i32 7, !"frame-pointer", i32 2} +!12 = !{!"clang version 19.0.0git (git@github.com:slinder1/llvm-project.git e4263955383c3e364bd752d02fc44cf5f22143ef)"} +!13 = distinct !DISubprogram(name: "func", scope: !14, file: !14, line: 15, type: !15, scopeLine: 15, spFlags: DISPFlagDefinition, unit: !2, retainedNodes: !17) +!14 = !DIFile(filename: "", directory: "/home/slinder1/llvm-project/main", checksumkind: CSK_MD5, checksum: "9e51994790e4105fa7153a61c95a824f") +!15 = !DISubroutineType(types: !16) +!16 = !{null} +!17 = !{} +; CHECK-DAG: ![[#VAR]] = !DILocalVariable(name: "var", +!18 = !DILocalVariable(name: "var", scope: !13, file: !14, line: 16, type: !4) +!19 = !DILocation(line: 16, column: 9, scope: !13) +!20 = !DILocation(line: 17, column: 1, scope: !13) +!21 = !{!0, !23, !24} +; CHECK-DAG: ![[#VAR_FRAGMENTED]] = !DILocalVariable(name: "var_fragmented", +!22 = !DILocalVariable(name: "var_fragmented", scope: !13, file: !14, line: 16, type: !4) +; CHECK-DAG: ![[#GLOB_FRAGMENTED_LO_GVE]] = !DIGlobalVariableExpression(var: ![[#GLOB_FRAGMENTED:]], expr: !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpFragment(0, 16))) +!23 = !DIGlobalVariableExpression(var: !25, expr: !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpFragment(0, 16))) +; CHECK-DAG: ![[#GLOB_FRAGMENTED_HI_GVE]] = !DIGlobalVariableExpression(var: ![[#GLOB_FRAGMENTED]], expr: !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpFragment(16, 16))) +!24 = !DIGlobalVariableExpression(var: !25, expr: !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpFragment(16, 16))) +; CHECK-DAG: ![[#GLOB_FRAGMENTED]] = distinct !DIGlobalVariable(name: "glob_fragmented", +!25 = distinct !DIGlobalVariable(name: "glob_fragmented", scope: !2, file: !3, line: 1, type: !4, isLocal: false, isDefinition: true) diff --git a/llvm/test/DebugInfo/verify-diop-based-diexpression.ll b/llvm/test/DebugInfo/verify-diop-based-diexpression.ll new file mode 100644 index 0000000000000..c44c897d311f1 --- /dev/null +++ b/llvm/test/DebugInfo/verify-diop-based-diexpression.ll @@ -0,0 +1,195 @@ +; RUN: rm -rf %t && split-file %s %t && cd %t + +;--- valid.ll +; RUN: opt valid.ll -S -passes=verify 2>&1 | FileCheck --implicit-check-not 'invalid expression' valid.ll + +source_filename = "t.c" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +declare void @llvm.dbg.declare(metadata, metadata, metadata) +declare void @llvm.dbg.value(metadata, metadata, metadata) + +%struct.type = type { ptr, ptr } + +define dso_local void @test_diexpr_eval() !dbg !17 { +entry: + %x = alloca ptr, align 8 + %i = alloca i32, align 4 + + ; CHECK: #dbg_declare(ptr %i, ![[#]], !DIExpression(DIOpArg(0, ptr), DIOpArg(0, ptr), DIOpComposite(2, %struct.type)), ![[#]]) + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, ptr), DIOpArg(0, ptr), DIOpComposite(2, %struct.type)), !22) + + ; CHECK: #dbg_declare(ptr %i, ![[#]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpFragment(16, 16)), ![[#]]) + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpFragment(16, 16)), !22) + + ; CHECK: #dbg_declare(ptr poison, ![[#]], !DIExpression(DIOpArg(0, ptr)), ![[#]]) + #dbg_declare(ptr poison, !24, !DIExpression(DIOpArg(0, ptr)), !22) + + ; CHECK: #dbg_declare(ptr %i, ![[#]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(%struct.type), DIOpConstant(i32 64), DIOpBitOffset(ptr)), ![[#]]) + #dbg_declare(ptr %i, !26, !DIExpression(DIOpArg(0, ptr), DIOpDeref(%struct.type), DIOpConstant(i32 64), DIOpBitOffset(ptr)), !22) + + ; CHECK: #dbg_declare(ptr %i, ![[#]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(%struct.type), DIOpConstant(i32 8), DIOpByteOffset(ptr)), ![[#]]) + #dbg_declare(ptr %i, !27, !DIExpression(DIOpArg(0, ptr), DIOpDeref(%struct.type), DIOpConstant(i32 8), DIOpByteOffset(ptr)), !22) + + ; CHECK: #dbg_declare(ptr %i, ![[#]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32), DIOpConstant(<2 x i32> ), DIOpConstant(<2 x i32> ), DIOpSelect()), ![[#]]) + #dbg_declare(ptr %i, !28, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32), DIOpConstant(<2 x i32> ), DIOpConstant(<2 x i32> ), DIOpSelect()), !22) + + ret void +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang version 18", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "t.c", directory: "/") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = distinct !DISubprogram(name: "test_broken_declare", scope: !1, file: !1, line: 2, type: !6, scopeLine: 2, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !8) +!6 = !DISubroutineType(types: !7) +!7 = !{null} +!8 = !{} +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!11 = !DILocation(line: 3, column: 7, scope: !5) +!12 = !DILocation(line: 4, column: 1, scope: !5) +!13 = distinct !DISubprogram(name: "test_broken_value", scope: !1, file: !1, line: 6, type: !6, scopeLine: 6, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !8) +!15 = !DILocation(line: 7, column: 7, scope: !13) +!16 = !DILocation(line: 8, column: 1, scope: !13) +!17 = distinct !DISubprogram(name: "test_diexpr_eval", scope: !1, file: !1, line: 10, type: !6, scopeLine: 10, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !8) +!18 = !DILocalVariable(name: "x", scope: !17, file: !1, line: 11, type: !19) +!19 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 64) +!20 = !DILocation(line: 11, column: 9, scope: !17) +!21 = !DILocalVariable(name: "i", scope: !17, file: !1, line: 12, type: !10) +!22 = !DILocation(line: 12, column: 7, scope: !17) +!23 = !DILocation(line: 13, column: 1, scope: !17) +!24 = !DILocalVariable(name: "j", scope: !17, file: !1, line: 12, type: !10) +!25 = !DIBasicType(name: "int64", size: 64, encoding: DW_ATE_unsigned) +!26 = !DILocalVariable(name: "k", scope: !17, file: !1, line: 12, type: !25) +!27 = !DILocalVariable(name: "l", scope: !17, file: !1, line: 12, type: !25) +!28 = !DILocalVariable(name: "m", scope: !17, file: !1, line: 12, type: !25) + +;--- invalid.ll +; RUN: opt invalid.ll -S -passes=verify 2>&1 | FileCheck invalid.ll + +source_filename = "t.c" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +declare void @llvm.dbg.declare(metadata, metadata, metadata) +declare void @llvm.dbg.value(metadata, metadata, metadata) + +define dso_local void @test_diexpr_eval() !dbg !17 { +entry: + %x = alloca ptr, align 8 + %i = alloca i32, align 4 + + ; CHECK: DIOpReferrer type must be same size in bits as argument + #dbg_declare(ptr %x, !18, !DIExpression(DIOpReferrer(i32), DIOpDeref(ptr)), !20) + + ; CHECK: DIOpArg index out of range + #dbg_declare(ptr %x, !18, !DIExpression(DIOpArg(1, ptr)), !20) + + ; CHECK: DIOpArg type must be same size in bits as argument + #dbg_declare(ptr %x, !18, !DIExpression(DIOpArg(0, i32)), !20) + + ; CHECK: DIOpReinterpret must not alter bitsize of child + #dbg_declare(ptr %x, !18, !DIExpression(DIOpArg(0, ptr), DIOpReinterpret(i32)), !20) + + ; CHECK: DIOpBitOffset requires first input be integer typed + #dbg_declare(ptr %x, !18, !DIExpression(DIOpConstant(float 0.0), DIOpArg(0, ptr), DIOpBitOffset(ptr)), !20) + + ; CHECK: DIOpByteOffset requires first input be integer typed + #dbg_declare(ptr %x, !18, !DIExpression(DIOpConstant(ptr undef), DIOpArg(0, ptr), DIOpByteOffset(ptr)), !20) + + ; CHECK: DIOpComposite bitsize does not match sum of child bitsizes + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpConstant(i8 0), DIOpComposite(2, i32)), !22) + + ; CHECK: DIOpExtend child must have integer, floating point, or ptr type + #dbg_declare(ptr %i, !21, !DIExpression(DIOpConstant(<2 x i32> ), DIOpExtend(2)), !22) + + ; CHECK: DIOpDeref requires input to be pointer typed + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32), DIOpDeref(i32)), !22) + + ; CHECK: DIOpAdd requires identical type inputs + #dbg_declare(ptr %i, !21, !DIExpression(DIOpConstant(i32 0), DIOpConstant(i8 0), DIOpAdd()), !22) + + ; CHECK: DIOpPushLane requires integer result type + #dbg_declare(ptr %i, !21, !DIExpression(DIOpPushLane(ptr)), !22) + + ; CHECK: DIOpAdd requires more inputs + #dbg_declare(ptr %i, !21, !DIExpression(DIOpConstant(i32 0), DIOpAdd()), !22) + + ; CHECK: DIOpArg type must be same size in bits as argument + #dbg_declare(!DIArgList(ptr %x, ptr %i), !21, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpAdd()), !22) + + ; CHECK: DIOpArg type must be same size in bits as argument + #dbg_declare(!DIArgList(ptr %x, ptr %i), !21, !DIExpression(DIOpArg(0, i8), DIOpArg(1, i8), DIOpAdd()), !22) + + ; CHECK: DIOp expression requires one element on stack after evaluating + #dbg_declare(!DIArgList(ptr %x, ptr %i), !21, !DIExpression(DIOpArg(0, i64), DIOpArg(1, i64)), !22) + + ; CHECK: DIOpZExt requires integer typed input + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, ptr), DIOpZExt(i64)), !22) + + ; CHECK: DIOpZExt requires result type to be wider than input type + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, i64), DIOpZExt(i64)), !22) + + ; CHECK: DIOpSExt requires integer typed input + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, ptr), DIOpSExt(i64)), !22) + + ; CHECK: DIOpSExt requires result type to be wider than input type + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, i64), DIOpSExt(i64)), !22) + + ; CHECK: DIOpLShr requires all integer inputs + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, ptr), DIOpArg(0, ptr), DIOpLShr()), !22) + + ; CHECK: DIOpAShr requires all integer inputs + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, ptr), DIOpArg(0, ptr), DIOpAShr()), !22) + + ; CHECK: DIOpShl requires all integer inputs + #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, ptr), DIOpArg(0, ptr), DIOpShl()), !22) + + ; CHECK: DIOpConvert on integers requires result type to be no wider than input type + #dbg_declare(i8 42, !21, !DIExpression(DIOpArg(0, i8), DIOpConvert(i16)), !22) + + ; FIXME(diexpression-poison): DIExpression must yield a location at least as wide as the variable or fragment it describes + ; #dbg_declare(i8 42, !21, !DIExpression(DIOpArg(0, i8)), !22) + + ; FIXME(diexpression-poison): DIExpression must yield a location at least as wide as the variable or fragment it describes + ; #dbg_declare(ptr %i, !21, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i16), DIOpConstant(i16 1), DIOpAdd()), !22) + + ; FIXME(diexpression-poison): DIExpression must yield a location at least as wide as the variable or fragment it describes + ; #dbg_declare(i8 42, !21, !DIExpression(DIOpArg(0, i8), DIOpFragment(0, 16)), !22) + + ; CHECK: DIOpFragment must be contained within variable + #dbg_declare(i16 42, !21, !DIExpression(DIOpArg(0, i16), DIOpFragment(24, 16)), !22) + + ret void +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang version 18", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "t.c", directory: "/") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = distinct !DISubprogram(name: "test_broken_declare", scope: !1, file: !1, line: 2, type: !6, scopeLine: 2, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !8) +!6 = !DISubroutineType(types: !7) +!7 = !{null} +!8 = !{} +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!11 = !DILocation(line: 3, column: 7, scope: !5) +!12 = !DILocation(line: 4, column: 1, scope: !5) +!13 = distinct !DISubprogram(name: "test_broken_value", scope: !1, file: !1, line: 6, type: !6, scopeLine: 6, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !8) +!15 = !DILocation(line: 7, column: 7, scope: !13) +!16 = !DILocation(line: 8, column: 1, scope: !13) +!17 = distinct !DISubprogram(name: "test_diexpr_eval", scope: !1, file: !1, line: 10, type: !6, scopeLine: 10, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !8) +!18 = !DILocalVariable(name: "x", scope: !17, file: !1, line: 11, type: !19) +!19 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 64) +!20 = !DILocation(line: 11, column: 9, scope: !17) +!21 = !DILocalVariable(name: "i", scope: !17, file: !1, line: 12, type: !10) +!22 = !DILocation(line: 12, column: 7, scope: !17) +!23 = !DILocation(line: 13, column: 1, scope: !17) diff --git a/llvm/test/Feature/alias2.ll b/llvm/test/Feature/alias2.ll index 7d3bca583123d..8cc0870d5df10 100644 --- a/llvm/test/Feature/alias2.ll +++ b/llvm/test/Feature/alias2.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s @v1 = global i32 0 ; CHECK: @v1 = global i32 0 diff --git a/llvm/test/Feature/comdat.ll b/llvm/test/Feature/comdat.ll index 5eb723eb6007c..e5ce234e5d97b 100644 --- a/llvm/test/Feature/comdat.ll +++ b/llvm/test/Feature/comdat.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | FileCheck %s $f = comdat any ; CHECK: $f = comdat any diff --git a/llvm/test/Feature/md_on_instruction.ll b/llvm/test/Feature/md_on_instruction.ll index 7374c99a3dbaf..16f1fa18b99de 100644 --- a/llvm/test/Feature/md_on_instruction.ll +++ b/llvm/test/Feature/md_on_instruction.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s define i32 @foo() nounwind ssp { entry: diff --git a/llvm/test/Feature/prefixdata.ll b/llvm/test/Feature/prefixdata.ll index 87cd053e64369..016d6519e84a5 100644 --- a/llvm/test/Feature/prefixdata.ll +++ b/llvm/test/Feature/prefixdata.ll @@ -1,8 +1,8 @@ -; RUN: llvm-as < %s | llvm-dis > %t1.ll +; RUN: llvm-as < %s | llvm-dis > %t1.ll ; RUN: FileCheck %s < %t1.ll -; RUN: llvm-as < %t1.ll | llvm-dis > %t2.ll +; RUN: llvm-as < %t1.ll | llvm-dis > %t2.ll ; RUN: diff %t1.ll %t2.ll -; RUN: opt -O3 -S < %t1.ll | FileCheck %s +; RUN: opt -O3 -S < %t1.ll | FileCheck %s ; CHECK: @i @i = linkonce_odr global i32 1 diff --git a/llvm/test/Feature/prologuedata.ll b/llvm/test/Feature/prologuedata.ll index f1dddda6aec71..635760b96cee7 100644 --- a/llvm/test/Feature/prologuedata.ll +++ b/llvm/test/Feature/prologuedata.ll @@ -1,8 +1,8 @@ -; RUN: llvm-as < %s | llvm-dis > %t1.ll +; RUN: llvm-as < %s | llvm-dis > %t1.ll ; RUN: FileCheck %s < %t1.ll -; RUN: llvm-as < %t1.ll | llvm-dis > %t2.ll +; RUN: llvm-as < %t1.ll | llvm-dis > %t2.ll ; RUN: diff %t1.ll %t2.ll -; RUN: opt -O3 -S < %t1.ll | FileCheck %s +; RUN: opt -O3 -S < %t1.ll | FileCheck %s ; CHECK: @i @i = linkonce_odr global i32 1 diff --git a/llvm/test/Feature/strip_names.ll b/llvm/test/Feature/strip_names.ll index dd941e45fb66a..288f6e1a6cafe 100644 --- a/llvm/test/Feature/strip_names.ll +++ b/llvm/test/Feature/strip_names.ll @@ -1,5 +1,5 @@ -; RUN: opt < %s -S | FileCheck %s -; RUN: opt < %s | opt -S -discard-value-names | FileCheck --check-prefix=NONAME %s +; RUN: opt < %s -S | FileCheck %s +; RUN: opt < %s | opt -S -discard-value-names | FileCheck --check-prefix=NONAME %s ; CHECK: @GlobalValueName diff --git a/llvm/test/Feature/undefined.ll b/llvm/test/Feature/undefined.ll index c4848161c6edb..57daae00023bc 100644 --- a/llvm/test/Feature/undefined.ll +++ b/llvm/test/Feature/undefined.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis > %t1.ll -; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll +; RUN: llvm-as < %s | llvm-dis > %t1.ll +; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll ; RUN: diff %t1.ll %t2.ll ; RUN: FileCheck %s < %t1.ll diff --git a/llvm/test/Instrumentation/AddressSanitizer/debug-info-global-var.ll b/llvm/test/Instrumentation/AddressSanitizer/debug-info-global-var.ll index 0b516e0174d6d..2815c1f04bff1 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/debug-info-global-var.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/debug-info-global-var.ll @@ -2,7 +2,7 @@ source_filename = "version.c" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.12.0" -; CHECK: @version = constant { [5 x i8], [27 x i8] } {{.*}}, !dbg ![[GV:.*]] +; CHECK: @version = constant { [5 x i8], [27 x i8] } {{.*}}, !dbg ![[GV:.*]] {{.*}} @version = constant [5 x i8] c"4.00\00", align 1, !dbg !0 diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll b/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll index cfded025dce7f..560af7c2461ef 100644 --- a/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll @@ -69,7 +69,7 @@ define dso_local i32 @standard_lifetime() local_unnamed_addr sanitize_hwaddress ; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) +; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2:![0-9]+]]) ; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -121,7 +121,7 @@ define dso_local i32 @standard_lifetime() local_unnamed_addr sanitize_hwaddress ; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) +; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2:![0-9]+]]) ; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -171,7 +171,7 @@ define dso_local i32 @standard_lifetime() local_unnamed_addr sanitize_hwaddress ; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2:![0-9]+]]) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -226,7 +226,7 @@ define dso_local i32 @standard_lifetime() local_unnamed_addr sanitize_hwaddress ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2:![0-9]+]]) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -350,7 +350,7 @@ define dso_local i32 @standard_lifetime_optnone() local_unnamed_addr optnone noi ; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -402,7 +402,7 @@ define dso_local i32 @standard_lifetime_optnone() local_unnamed_addr optnone noi ; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -452,7 +452,7 @@ define dso_local i32 @standard_lifetime_optnone() local_unnamed_addr optnone noi ; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -507,7 +507,7 @@ define dso_local i32 @standard_lifetime_optnone() local_unnamed_addr optnone noi ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -621,7 +621,7 @@ define dso_local i32 @multiple_lifetimes() local_unnamed_addr sanitize_hwaddress ; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -667,7 +667,7 @@ define dso_local i32 @multiple_lifetimes() local_unnamed_addr sanitize_hwaddress ; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -713,7 +713,7 @@ define dso_local i32 @multiple_lifetimes() local_unnamed_addr sanitize_hwaddress ; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -762,7 +762,7 @@ define dso_local i32 @multiple_lifetimes() local_unnamed_addr sanitize_hwaddress ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -881,7 +881,7 @@ define dso_local i32 @unreachable_exit() local_unnamed_addr sanitize_hwaddress { ; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -938,7 +938,7 @@ define dso_local i32 @unreachable_exit() local_unnamed_addr sanitize_hwaddress { ; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -994,7 +994,7 @@ define dso_local i32 @unreachable_exit() local_unnamed_addr sanitize_hwaddress { ; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -1054,7 +1054,7 @@ define dso_local i32 @unreachable_exit() local_unnamed_addr sanitize_hwaddress { ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -1189,7 +1189,7 @@ define dso_local i32 @diamond_lifetime() local_unnamed_addr sanitize_hwaddress { ; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -1250,7 +1250,7 @@ define dso_local i32 @diamond_lifetime() local_unnamed_addr sanitize_hwaddress { ; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -1302,7 +1302,7 @@ define dso_local i32 @diamond_lifetime() local_unnamed_addr sanitize_hwaddress { ; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 @@ -1366,7 +1366,7 @@ define dso_local i32 @diamond_lifetime() local_unnamed_addr sanitize_hwaddress { ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META2]]) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 ; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 diff --git a/llvm/test/Linker/DbgDeclare.ll b/llvm/test/Linker/DbgDeclare.ll index c16f4870c9407..9cea8d9169801 100644 --- a/llvm/test/Linker/DbgDeclare.ll +++ b/llvm/test/Linker/DbgDeclare.ll @@ -1,5 +1,5 @@ -; RUN: llvm-link %s %p/DbgDeclare2.ll -o %t.bc -; RUN: llvm-dis < %t.bc | FileCheck %s +; RUN: llvm-link %s %p/DbgDeclare2.ll -o %t.bc +; RUN: llvm-dis < %t.bc | FileCheck %s ; Test if metadata in dbg.declare is mapped properly or not. ; rdar://13089880 diff --git a/llvm/test/Linker/blockaddress.ll b/llvm/test/Linker/blockaddress.ll index 0e5f9bf37ea98..efad06e79f58f 100644 --- a/llvm/test/Linker/blockaddress.ll +++ b/llvm/test/Linker/blockaddress.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as %s -o %t.bc -; RUN: llvm-link %t.bc -S | FileCheck %s +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-link %t.bc -S | FileCheck %s declare void @f(ptr) diff --git a/llvm/test/Linker/intrinsics-with-unnamed-types.ll b/llvm/test/Linker/intrinsics-with-unnamed-types.ll index d870e7f100e05..690cb75fc3db0 100644 --- a/llvm/test/Linker/intrinsics-with-unnamed-types.ll +++ b/llvm/test/Linker/intrinsics-with-unnamed-types.ll @@ -1,8 +1,8 @@ ; RUN: split-file %s %t -; RUN: llvm-as -o %t1.bc %t/f01.ll -; RUN: llvm-as -o %t2.bc %t/f02.ll -; RUN: llvm-link %t1.bc %t2.bc -o %t3.bc -; RUN: llvm-dis -o - %t3.bc | FileCheck %s +; RUN: llvm-as -o %t1.bc %t/f01.ll +; RUN: llvm-as -o %t2.bc %t/f02.ll +; RUN: llvm-link %t1.bc %t2.bc -o %t3.bc +; RUN: llvm-dis -o - %t3.bc | FileCheck %s ; Make sure we can link files with clashing intrinsic names using unnamed types. diff --git a/llvm/test/Linker/type-unique-src-type.ll b/llvm/test/Linker/type-unique-src-type.ll index 03e890351e083..36c0b08ef85a7 100644 --- a/llvm/test/Linker/type-unique-src-type.ll +++ b/llvm/test/Linker/type-unique-src-type.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as %s -o %t.bc -; RUN: llvm-link -S %t.bc -o - | FileCheck %s -; RUN: llvm-link -S %s -o - | FileCheck %s +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-link -S %t.bc -o - | FileCheck %s +; RUN: llvm-link -S %s -o - | FileCheck %s ; Test that we don't try to map %C.0 and C and then try to map %C to a new type. ; This used to happen when lazy loading since we wouldn't then identify %C diff --git a/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s b/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s index 8bd91484d149c..205b7f007ae31 100644 --- a/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s +++ b/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s @@ -2,7 +2,7 @@ // CHECK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" buffer_load_dwordx4 v[0:3], v0, s[0:3], 0, offen offset:4092 slc -// CHECK: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4092 slc ; // CHECK-NEXT: ; // CHECK-NEXT: ; @@ -11,7 +11,7 @@ buffer_load_dwordx4 v[0:3], v0, s[0:3], 0, offen offset:4092 slc // CHECK-NEXT: ; // CHECK-NEXT: ; > buffer_store_dword v0, v1, s[0:3], 0 offen slc -// CHECK: buffer_store_b32 v0, v1, s[0:3], 0 offen slc ; // CHECK-NEXT: ; // CHECK-NEXT: ; @@ -22,7 +22,7 @@ buffer_store_dword v0, v1, s[0:3], 0 offen slc ; tbuffer ops use autogenerate asm parsers tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] offen offset:4092 slc -// CHECK: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] offen offset:4092 slc ; // CHECK-NEXT: ; // CHECK-NEXT: ; @@ -32,7 +32,7 @@ tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] offen // CHECK-NEXT: ; // CHECK-NEXT: ; > tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] offen slc -// CHECK: tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] offen slc ; // CHECK-NEXT: ; // CHECK-NEXT: ; diff --git a/llvm/test/MC/AMDGPU/dl-insts.s b/llvm/test/MC/AMDGPU/dl-insts.s index 599734aac829d..00e9bec7eb0a2 100644 --- a/llvm/test/MC/AMDGPU/dl-insts.s +++ b/llvm/test/MC/AMDGPU/dl-insts.s @@ -536,6 +536,198 @@ v_dot2_u32_u16 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] v_dot2_u32_u16 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] // CHECK: encoding: [0x00,0x18,0xa7,0xd3,0x01,0x05,0x0e,0x1c] v_dot2_u32_u16 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x40,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] +// CHECK: encoding: [0x00,0x50,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] +// CHECK: encoding: [0x00,0x48,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] +// CHECK: encoding: [0x00,0x58,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] +// CHECK: encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x04] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x14] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x0c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x04] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x14] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x0c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x04] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x14] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x0c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x04] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x14] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x0c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x04] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x14] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x0c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x40,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] +// CHECK: encoding: [0x00,0x50,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] +// CHECK: encoding: [0x00,0x48,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] +// CHECK: encoding: [0x00,0x58,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] +// CHECK: encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x04] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x14] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x0c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x04] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x14] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x0c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x04] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x14] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x0c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x04] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x14] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x0c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x04] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x14] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x0c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x40,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] +// CHECK: encoding: [0x00,0x50,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] +// CHECK: encoding: [0x00,0x48,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] +// CHECK: encoding: [0x00,0x58,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] +// CHECK: encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x04] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x14] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x0c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x04] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x14] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x0c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x04] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x14] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x0c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x04] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x14] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x0c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x04] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x14] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x0c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x40,0xab,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] +// CHECK: encoding: [0x00,0x50,0xab,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] +// CHECK: encoding: [0x00,0x48,0xab,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] +// CHECK: encoding: [0x00,0x58,0xab,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] +// CHECK: encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x04] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x14] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x0c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x04] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x14] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x0c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x04] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x14] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x0c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x04] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x14] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x0c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] +// CHECK: encoding: [0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x04] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] +// CHECK: encoding: [0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x14] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] +// CHECK: encoding: [0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x0c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] +// CHECK: encoding: [0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x1c] +v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] // // Test clamp. diff --git a/llvm/test/MC/AMDGPU/gfx1030_err.s b/llvm/test/MC/AMDGPU/gfx1030_err.s index a0565dc1e6d3c..c5a78d97bd420 100644 --- a/llvm/test/MC/AMDGPU/gfx1030_err.s +++ b/llvm/test/MC/AMDGPU/gfx1030_err.s @@ -1,4 +1,5 @@ // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1030 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s +// XFAIL: * // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1031 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1032 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1033 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_err.s deleted file mode 100644 index 451627eb93246..0000000000000 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_err.s +++ /dev/null @@ -1,219 +0,0 @@ -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s - -// op_sel not allowed in dot opcodes with 4- or 8-bit packed data - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_err.s index 5ed2091d37e43..a7d42c6b923a4 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_err.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_err.s @@ -131,221 +131,3 @@ v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_hi:[1,0,0] v_dot4_f32_bf8_bf8 v0, v1, v2, v3 neg_hi:[0,1,0] // GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid neg_hi operand - -// op_sel not allowed in dot opcodes with 4- or 8-bit packed data - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_iu8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. diff --git a/llvm/test/MC/AMDGPU/gfx908_err.s b/llvm/test/MC/AMDGPU/gfx908_err.s deleted file mode 100644 index d39e9b5068a4f..0000000000000 --- a/llvm/test/MC/AMDGPU/gfx908_err.s +++ /dev/null @@ -1,436 +0,0 @@ -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck --check-prefix=GFX908 --implicit-check-not=error: %s - -// op_sel not allowed in dot opcodes with 4- or 8-bit packed data - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - diff --git a/llvm/test/MC/AMDGPU/gfx90a_err.s b/llvm/test/MC/AMDGPU/gfx90a_err.s index ff0dfb371bbbf..6e84e9132a55d 100644 --- a/llvm/test/MC/AMDGPU/gfx90a_err.s +++ b/llvm/test/MC/AMDGPU/gfx90a_err.s @@ -239,438 +239,3 @@ scratch_load_lds_dword v2, off ds_read_b32 v0, v1 gds // GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: gds modifier is not supported on this GPU - -// op_sel not allowed in dot opcodes with 4- or 8-bit packed data - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot4c_i32_i8 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[0,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,0] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[0,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - -v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1] -// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. - diff --git a/llvm/test/MC/AsmParser/altmacro-arg.s b/llvm/test/MC/AsmParser/altmacro-arg.s index 713f5ad4aeab7..262c5eac832e0 100644 --- a/llvm/test/MC/AsmParser/altmacro-arg.s +++ b/llvm/test/MC/AsmParser/altmacro-arg.s @@ -1,30 +1,10 @@ ## Arguments can be expanded even if they are not preceded by \ -# RUN: rm -rf %t && split-file %s %t && cd %t -# RUN: llvm-mc -triple=x86_64 a.s | FileCheck %s -# RUN: llvm-mc -triple=x86_64 b.s | FileCheck %s --check-prefix=CHECK1 +# RUN: llvm-mc -triple=x86_64 %s | FileCheck %s -#--- a.s +# CHECK: 1 1 1a +# CHECK-NEXT: 1 2 1a 2b +# CHECK-NEXT: \$b \$b .altmacro -# CHECK: ja .Ltmp0 -# CHECK-NEXT: xorq %rbx, %rbx -# CHECK: .data -# CHECK-NEXT: .ascii "b cc rbx" -# CHECK-NEXT: .ascii "bcc ccx rbx raxx" -.macro gen a, ra, rax - ja 1f - xorq %rax, %rax -1: -.data - .ascii "\a \ra \rax" - .ascii "a\()ra ra\()x rax raxx" -.endm -gen b, cc, rbx - -#--- b.s -.altmacro -# CHECK1: 1 1 1a -# CHECK1-NEXT: 1 2 1a 2b -# CHECK1-NEXT: \$b \$b .irp ._a,1 .print "\._a \._a& ._a&a" .irp $b,2 @@ -33,11 +13,10 @@ gen b, cc, rbx .print "\$b \$b&" .endr -# CHECK1: 1 1& ._a&a -# CHECK1-NEXT: \$b \$b& +# CHECK: 1 1& ._a&a +# CHECK-NEXT: \$b \$b& .noaltmacro .irp ._a,1 .print "\._a \._a& ._a&a" .print "\$b \$b&" .endr -.altmacro diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx908-dl-insts.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx908-dl-insts.txt index 310e23f642e89..aa3b4c7f03837 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx908-dl-insts.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx908-dl-insts.txt @@ -778,15 +778,291 @@ # CHECK: v_dot4_i32_i8 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xa8,0xd3,0x01,0x05,0x0e,0x1c] 0x00,0x40,0xa8,0xd3,0x01,0x05,0x0e,0x1c +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x00,0x50,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x50,0xa8,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x48,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x48,0xa8,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1,0] ; encoding: [0x00,0x58,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x58,0xa8,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,1,0] ; encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel_hi:[1,1,0] ; encoding: [0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x00,0xa8,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x10,0xa8,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x08,0xa8,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot4_i32_i8 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x18,0xa8,0xd3,0x01,0x05,0x0e,0x1c + # CHECK: v_dot4_u32_u8 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xa9,0xd3,0x01,0x05,0x0e,0x1c] 0x00,0x40,0xa9,0xd3,0x01,0x05,0x0e,0x1c +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x00,0x50,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x50,0xa9,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x48,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x48,0xa9,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1,0] ; encoding: [0x00,0x58,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x58,0xa9,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,1,0] ; encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel_hi:[1,1,0] ; encoding: [0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x00,0xa9,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x10,0xa9,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x08,0xa9,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot4_u32_u8 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x18,0xa9,0xd3,0x01,0x05,0x0e,0x1c + # CHECK: v_dot8_i32_i4 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xaa,0xd3,0x01,0x05,0x0e,0x1c] 0x00,0x40,0xaa,0xd3,0x01,0x05,0x0e,0x1c +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x00,0x50,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x50,0xaa,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x48,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x48,0xaa,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1,0] ; encoding: [0x00,0x58,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x58,0xaa,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,1,0] ; encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel_hi:[1,1,0] ; encoding: [0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x00,0xaa,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x10,0xaa,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x08,0xaa,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot8_i32_i4 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x18,0xaa,0xd3,0x01,0x05,0x0e,0x1c + # CHECK: v_dot8_u32_u4 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xab,0xd3,0x01,0x05,0x0e,0x1c] 0x00,0x40,0xab,0xd3,0x01,0x05,0x0e,0x1c +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x00,0x50,0xab,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x50,0xab,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x48,0xab,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x48,0xab,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1,0] ; encoding: [0x00,0x58,0xab,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x58,0xab,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,1,0] ; encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel_hi:[1,1,0] ; encoding: [0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x00,0xab,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x10,0xab,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x08,0xab,0xd3,0x01,0x05,0x0e,0x1c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x04] +0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x04 + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[0,1,0] ; encoding: [0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x14] +0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x14 + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,0,0] ; encoding: [0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x0c] +0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x0c + +# CHECK: v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding: [0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x1c] +0x00,0x18,0xab,0xd3,0x01,0x05,0x0e,0x1c + # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 clamp ; encoding: [0x00,0xc0,0xa3,0xd3,0x01,0x05,0x0e,0x1c] 0x00,0xc0,0xa3,0xd3,0x01,0x05,0x0e,0x1c diff --git a/llvm/test/MC/Disassembler/X86/avx-vnni-int16-32.txt b/llvm/test/MC/Disassembler/X86/avx-vnni-int16-32.txt deleted file mode 100644 index 099970430ea29..0000000000000 --- a/llvm/test/MC/Disassembler/X86/avx-vnni-int16-32.txt +++ /dev/null @@ -1,339 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s --check-prefixes=ATT -# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL - -# ATT: vpdpwsud %ymm4, %ymm3, %ymm2 -# INTEL: vpdpwsud ymm2, ymm3, ymm4 -0xc4,0xe2,0x66,0xd2,0xd4 - -# ATT: vpdpwsud %xmm4, %xmm3, %xmm2 -# INTEL: vpdpwsud xmm2, xmm3, xmm4 -0xc4,0xe2,0x62,0xd2,0xd4 - -# ATT: vpdpwsud 268435456(%esp,%esi,8), %ymm3, %ymm2 -# INTEL: vpdpwsud ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x66,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwsud 291(%edi,%eax,4), %ymm3, %ymm2 -# INTEL: vpdpwsud ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x66,0xd2,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwsud (%eax), %ymm3, %ymm2 -# INTEL: vpdpwsud ymm2, ymm3, ymmword ptr [eax] -0xc4,0xe2,0x66,0xd2,0x10 - -# ATT: vpdpwsud -1024(,%ebp,2), %ymm3, %ymm2 -# INTEL: vpdpwsud ymm2, ymm3, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x66,0xd2,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwsud 4064(%ecx), %ymm3, %ymm2 -# INTEL: vpdpwsud ymm2, ymm3, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x66,0xd2,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwsud -4096(%edx), %ymm3, %ymm2 -# INTEL: vpdpwsud ymm2, ymm3, ymmword ptr [edx - 4096] -0xc4,0xe2,0x66,0xd2,0x92,0x00,0xf0,0xff,0xff - -# ATT: vpdpwsud 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vpdpwsud xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x62,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwsud 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vpdpwsud xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x62,0xd2,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwsud (%eax), %xmm3, %xmm2 -# INTEL: vpdpwsud xmm2, xmm3, xmmword ptr [eax] -0xc4,0xe2,0x62,0xd2,0x10 - -# ATT: vpdpwsud -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vpdpwsud xmm2, xmm3, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x62,0xd2,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwsud 2032(%ecx), %xmm3, %xmm2 -# INTEL: vpdpwsud xmm2, xmm3, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x62,0xd2,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwsud -2048(%edx), %xmm3, %xmm2 -# INTEL: vpdpwsud xmm2, xmm3, xmmword ptr [edx - 2048] -0xc4,0xe2,0x62,0xd2,0x92,0x00,0xf8,0xff,0xff - -# ATT: vpdpwsuds %ymm4, %ymm3, %ymm2 -# INTEL: vpdpwsuds ymm2, ymm3, ymm4 -0xc4,0xe2,0x66,0xd3,0xd4 - -# ATT: vpdpwsuds %xmm4, %xmm3, %xmm2 -# INTEL: vpdpwsuds xmm2, xmm3, xmm4 -0xc4,0xe2,0x62,0xd3,0xd4 - -# ATT: vpdpwsuds 268435456(%esp,%esi,8), %ymm3, %ymm2 -# INTEL: vpdpwsuds ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x66,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwsuds 291(%edi,%eax,4), %ymm3, %ymm2 -# INTEL: vpdpwsuds ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x66,0xd3,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwsuds (%eax), %ymm3, %ymm2 -# INTEL: vpdpwsuds ymm2, ymm3, ymmword ptr [eax] -0xc4,0xe2,0x66,0xd3,0x10 - -# ATT: vpdpwsuds -1024(,%ebp,2), %ymm3, %ymm2 -# INTEL: vpdpwsuds ymm2, ymm3, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x66,0xd3,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwsuds 4064(%ecx), %ymm3, %ymm2 -# INTEL: vpdpwsuds ymm2, ymm3, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x66,0xd3,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwsuds -4096(%edx), %ymm3, %ymm2 -# INTEL: vpdpwsuds ymm2, ymm3, ymmword ptr [edx - 4096] -0xc4,0xe2,0x66,0xd3,0x92,0x00,0xf0,0xff,0xff - -# ATT: vpdpwsuds 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vpdpwsuds xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x62,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwsuds 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vpdpwsuds xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x62,0xd3,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwsuds (%eax), %xmm3, %xmm2 -# INTEL: vpdpwsuds xmm2, xmm3, xmmword ptr [eax] -0xc4,0xe2,0x62,0xd3,0x10 - -# ATT: vpdpwsuds -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vpdpwsuds xmm2, xmm3, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x62,0xd3,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwsuds 2032(%ecx), %xmm3, %xmm2 -# INTEL: vpdpwsuds xmm2, xmm3, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x62,0xd3,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwsuds -2048(%edx), %xmm3, %xmm2 -# INTEL: vpdpwsuds xmm2, xmm3, xmmword ptr [edx - 2048] -0xc4,0xe2,0x62,0xd3,0x92,0x00,0xf8,0xff,0xff - -# ATT: vpdpwusd %ymm4, %ymm3, %ymm2 -# INTEL: vpdpwusd ymm2, ymm3, ymm4 -0xc4,0xe2,0x65,0xd2,0xd4 - -# ATT: vpdpwusd %xmm4, %xmm3, %xmm2 -# INTEL: vpdpwusd xmm2, xmm3, xmm4 -0xc4,0xe2,0x61,0xd2,0xd4 - -# ATT: vpdpwusd 268435456(%esp,%esi,8), %ymm3, %ymm2 -# INTEL: vpdpwusd ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x65,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwusd 291(%edi,%eax,4), %ymm3, %ymm2 -# INTEL: vpdpwusd ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x65,0xd2,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwusd (%eax), %ymm3, %ymm2 -# INTEL: vpdpwusd ymm2, ymm3, ymmword ptr [eax] -0xc4,0xe2,0x65,0xd2,0x10 - -# ATT: vpdpwusd -1024(,%ebp,2), %ymm3, %ymm2 -# INTEL: vpdpwusd ymm2, ymm3, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x65,0xd2,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwusd 4064(%ecx), %ymm3, %ymm2 -# INTEL: vpdpwusd ymm2, ymm3, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x65,0xd2,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwusd -4096(%edx), %ymm3, %ymm2 -# INTEL: vpdpwusd ymm2, ymm3, ymmword ptr [edx - 4096] -0xc4,0xe2,0x65,0xd2,0x92,0x00,0xf0,0xff,0xff - -# ATT: vpdpwusd 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vpdpwusd xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x61,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwusd 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vpdpwusd xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x61,0xd2,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwusd (%eax), %xmm3, %xmm2 -# INTEL: vpdpwusd xmm2, xmm3, xmmword ptr [eax] -0xc4,0xe2,0x61,0xd2,0x10 - -# ATT: vpdpwusd -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vpdpwusd xmm2, xmm3, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x61,0xd2,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwusd 2032(%ecx), %xmm3, %xmm2 -# INTEL: vpdpwusd xmm2, xmm3, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x61,0xd2,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwusd -2048(%edx), %xmm3, %xmm2 -# INTEL: vpdpwusd xmm2, xmm3, xmmword ptr [edx - 2048] -0xc4,0xe2,0x61,0xd2,0x92,0x00,0xf8,0xff,0xff - -# ATT: vpdpwusds %ymm4, %ymm3, %ymm2 -# INTEL: vpdpwusds ymm2, ymm3, ymm4 -0xc4,0xe2,0x65,0xd3,0xd4 - -# ATT: vpdpwusds %xmm4, %xmm3, %xmm2 -# INTEL: vpdpwusds xmm2, xmm3, xmm4 -0xc4,0xe2,0x61,0xd3,0xd4 - -# ATT: vpdpwusds 268435456(%esp,%esi,8), %ymm3, %ymm2 -# INTEL: vpdpwusds ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x65,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwusds 291(%edi,%eax,4), %ymm3, %ymm2 -# INTEL: vpdpwusds ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x65,0xd3,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwusds (%eax), %ymm3, %ymm2 -# INTEL: vpdpwusds ymm2, ymm3, ymmword ptr [eax] -0xc4,0xe2,0x65,0xd3,0x10 - -# ATT: vpdpwusds -1024(,%ebp,2), %ymm3, %ymm2 -# INTEL: vpdpwusds ymm2, ymm3, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x65,0xd3,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwusds 4064(%ecx), %ymm3, %ymm2 -# INTEL: vpdpwusds ymm2, ymm3, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x65,0xd3,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwusds -4096(%edx), %ymm3, %ymm2 -# INTEL: vpdpwusds ymm2, ymm3, ymmword ptr [edx - 4096] -0xc4,0xe2,0x65,0xd3,0x92,0x00,0xf0,0xff,0xff - -# ATT: vpdpwusds 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vpdpwusds xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x61,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwusds 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vpdpwusds xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x61,0xd3,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwusds (%eax), %xmm3, %xmm2 -# INTEL: vpdpwusds xmm2, xmm3, xmmword ptr [eax] -0xc4,0xe2,0x61,0xd3,0x10 - -# ATT: vpdpwusds -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vpdpwusds xmm2, xmm3, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x61,0xd3,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwusds 2032(%ecx), %xmm3, %xmm2 -# INTEL: vpdpwusds xmm2, xmm3, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x61,0xd3,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwusds -2048(%edx), %xmm3, %xmm2 -# INTEL: vpdpwusds xmm2, xmm3, xmmword ptr [edx - 2048] -0xc4,0xe2,0x61,0xd3,0x92,0x00,0xf8,0xff,0xff - -# ATT: vpdpwuud %ymm4, %ymm3, %ymm2 -# INTEL: vpdpwuud ymm2, ymm3, ymm4 -0xc4,0xe2,0x64,0xd2,0xd4 - -# ATT: vpdpwuud %xmm4, %xmm3, %xmm2 -# INTEL: vpdpwuud xmm2, xmm3, xmm4 -0xc4,0xe2,0x60,0xd2,0xd4 - -# ATT: vpdpwuud 268435456(%esp,%esi,8), %ymm3, %ymm2 -# INTEL: vpdpwuud ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x64,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwuud 291(%edi,%eax,4), %ymm3, %ymm2 -# INTEL: vpdpwuud ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x64,0xd2,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwuud (%eax), %ymm3, %ymm2 -# INTEL: vpdpwuud ymm2, ymm3, ymmword ptr [eax] -0xc4,0xe2,0x64,0xd2,0x10 - -# ATT: vpdpwuud -1024(,%ebp,2), %ymm3, %ymm2 -# INTEL: vpdpwuud ymm2, ymm3, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x64,0xd2,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwuud 4064(%ecx), %ymm3, %ymm2 -# INTEL: vpdpwuud ymm2, ymm3, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x64,0xd2,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwuud -4096(%edx), %ymm3, %ymm2 -# INTEL: vpdpwuud ymm2, ymm3, ymmword ptr [edx - 4096] -0xc4,0xe2,0x64,0xd2,0x92,0x00,0xf0,0xff,0xff - -# ATT: vpdpwuud 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vpdpwuud xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x60,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwuud 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vpdpwuud xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x60,0xd2,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwuud (%eax), %xmm3, %xmm2 -# INTEL: vpdpwuud xmm2, xmm3, xmmword ptr [eax] -0xc4,0xe2,0x60,0xd2,0x10 - -# ATT: vpdpwuud -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vpdpwuud xmm2, xmm3, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x60,0xd2,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwuud 2032(%ecx), %xmm3, %xmm2 -# INTEL: vpdpwuud xmm2, xmm3, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x60,0xd2,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwuud -2048(%edx), %xmm3, %xmm2 -# INTEL: vpdpwuud xmm2, xmm3, xmmword ptr [edx - 2048] -0xc4,0xe2,0x60,0xd2,0x92,0x00,0xf8,0xff,0xff - -# ATT: vpdpwuuds %ymm4, %ymm3, %ymm2 -# INTEL: vpdpwuuds ymm2, ymm3, ymm4 -0xc4,0xe2,0x64,0xd3,0xd4 - -# ATT: vpdpwuuds %xmm4, %xmm3, %xmm2 -# INTEL: vpdpwuuds xmm2, xmm3, xmm4 -0xc4,0xe2,0x60,0xd3,0xd4 - -# ATT: vpdpwuuds 268435456(%esp,%esi,8), %ymm3, %ymm2 -# INTEL: vpdpwuuds ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x64,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwuuds 291(%edi,%eax,4), %ymm3, %ymm2 -# INTEL: vpdpwuuds ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x64,0xd3,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwuuds (%eax), %ymm3, %ymm2 -# INTEL: vpdpwuuds ymm2, ymm3, ymmword ptr [eax] -0xc4,0xe2,0x64,0xd3,0x10 - -# ATT: vpdpwuuds -1024(,%ebp,2), %ymm3, %ymm2 -# INTEL: vpdpwuuds ymm2, ymm3, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x64,0xd3,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwuuds 4064(%ecx), %ymm3, %ymm2 -# INTEL: vpdpwuuds ymm2, ymm3, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x64,0xd3,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwuuds -4096(%edx), %ymm3, %ymm2 -# INTEL: vpdpwuuds ymm2, ymm3, ymmword ptr [edx - 4096] -0xc4,0xe2,0x64,0xd3,0x92,0x00,0xf0,0xff,0xff - -# ATT: vpdpwuuds 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vpdpwuuds xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x60,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vpdpwuuds 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vpdpwuuds xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x60,0xd3,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vpdpwuuds (%eax), %xmm3, %xmm2 -# INTEL: vpdpwuuds xmm2, xmm3, xmmword ptr [eax] -0xc4,0xe2,0x60,0xd3,0x10 - -# ATT: vpdpwuuds -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vpdpwuuds xmm2, xmm3, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x60,0xd3,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwuuds 2032(%ecx), %xmm3, %xmm2 -# INTEL: vpdpwuuds xmm2, xmm3, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x60,0xd3,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwuuds -2048(%edx), %xmm3, %xmm2 -# INTEL: vpdpwuuds xmm2, xmm3, xmmword ptr [edx - 2048] -0xc4,0xe2,0x60,0xd3,0x92,0x00,0xf8,0xff,0xff - diff --git a/llvm/test/MC/Disassembler/X86/avx-vnni-int16-64.txt b/llvm/test/MC/Disassembler/X86/avx-vnni-int16-64.txt deleted file mode 100644 index 55396db790c71..0000000000000 --- a/llvm/test/MC/Disassembler/X86/avx-vnni-int16-64.txt +++ /dev/null @@ -1,339 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT -# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL - -# ATT: vpdpwsud %ymm4, %ymm13, %ymm12 -# INTEL: vpdpwsud ymm12, ymm13, ymm4 -0xc4,0x62,0x16,0xd2,0xe4 - -# ATT: vpdpwsud %xmm4, %xmm13, %xmm12 -# INTEL: vpdpwsud xmm12, xmm13, xmm4 -0xc4,0x62,0x12,0xd2,0xe4 - -# ATT: vpdpwsud 268435456(%rbp,%r14,8), %ymm13, %ymm12 -# INTEL: vpdpwsud ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x16,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwsud 291(%r8,%rax,4), %ymm13, %ymm12 -# INTEL: vpdpwsud ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x16,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwsud (%rip), %ymm13, %ymm12 -# INTEL: vpdpwsud ymm12, ymm13, ymmword ptr [rip] -0xc4,0x62,0x16,0xd2,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwsud -1024(,%rbp,2), %ymm13, %ymm12 -# INTEL: vpdpwsud ymm12, ymm13, ymmword ptr [2*rbp - 1024] -0xc4,0x62,0x16,0xd2,0x24,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwsud 4064(%rcx), %ymm13, %ymm12 -# INTEL: vpdpwsud ymm12, ymm13, ymmword ptr [rcx + 4064] -0xc4,0x62,0x16,0xd2,0xa1,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwsud -4096(%rdx), %ymm13, %ymm12 -# INTEL: vpdpwsud ymm12, ymm13, ymmword ptr [rdx - 4096] -0xc4,0x62,0x16,0xd2,0xa2,0x00,0xf0,0xff,0xff - -# ATT: vpdpwsud 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vpdpwsud xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x12,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwsud 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vpdpwsud xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x12,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwsud (%rip), %xmm13, %xmm12 -# INTEL: vpdpwsud xmm12, xmm13, xmmword ptr [rip] -0xc4,0x62,0x12,0xd2,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwsud -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vpdpwsud xmm12, xmm13, xmmword ptr [2*rbp - 512] -0xc4,0x62,0x12,0xd2,0x24,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwsud 2032(%rcx), %xmm13, %xmm12 -# INTEL: vpdpwsud xmm12, xmm13, xmmword ptr [rcx + 2032] -0xc4,0x62,0x12,0xd2,0xa1,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwsud -2048(%rdx), %xmm13, %xmm12 -# INTEL: vpdpwsud xmm12, xmm13, xmmword ptr [rdx - 2048] -0xc4,0x62,0x12,0xd2,0xa2,0x00,0xf8,0xff,0xff - -# ATT: vpdpwsuds %ymm4, %ymm13, %ymm12 -# INTEL: vpdpwsuds ymm12, ymm13, ymm4 -0xc4,0x62,0x16,0xd3,0xe4 - -# ATT: vpdpwsuds %xmm4, %xmm13, %xmm12 -# INTEL: vpdpwsuds xmm12, xmm13, xmm4 -0xc4,0x62,0x12,0xd3,0xe4 - -# ATT: vpdpwsuds 268435456(%rbp,%r14,8), %ymm13, %ymm12 -# INTEL: vpdpwsuds ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x16,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwsuds 291(%r8,%rax,4), %ymm13, %ymm12 -# INTEL: vpdpwsuds ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x16,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwsuds (%rip), %ymm13, %ymm12 -# INTEL: vpdpwsuds ymm12, ymm13, ymmword ptr [rip] -0xc4,0x62,0x16,0xd3,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwsuds -1024(,%rbp,2), %ymm13, %ymm12 -# INTEL: vpdpwsuds ymm12, ymm13, ymmword ptr [2*rbp - 1024] -0xc4,0x62,0x16,0xd3,0x24,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwsuds 4064(%rcx), %ymm13, %ymm12 -# INTEL: vpdpwsuds ymm12, ymm13, ymmword ptr [rcx + 4064] -0xc4,0x62,0x16,0xd3,0xa1,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwsuds -4096(%rdx), %ymm13, %ymm12 -# INTEL: vpdpwsuds ymm12, ymm13, ymmword ptr [rdx - 4096] -0xc4,0x62,0x16,0xd3,0xa2,0x00,0xf0,0xff,0xff - -# ATT: vpdpwsuds 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vpdpwsuds xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x12,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwsuds 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vpdpwsuds xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x12,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwsuds (%rip), %xmm13, %xmm12 -# INTEL: vpdpwsuds xmm12, xmm13, xmmword ptr [rip] -0xc4,0x62,0x12,0xd3,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwsuds -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vpdpwsuds xmm12, xmm13, xmmword ptr [2*rbp - 512] -0xc4,0x62,0x12,0xd3,0x24,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwsuds 2032(%rcx), %xmm13, %xmm12 -# INTEL: vpdpwsuds xmm12, xmm13, xmmword ptr [rcx + 2032] -0xc4,0x62,0x12,0xd3,0xa1,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwsuds -2048(%rdx), %xmm13, %xmm12 -# INTEL: vpdpwsuds xmm12, xmm13, xmmword ptr [rdx - 2048] -0xc4,0x62,0x12,0xd3,0xa2,0x00,0xf8,0xff,0xff - -# ATT: vpdpwusd %ymm4, %ymm13, %ymm12 -# INTEL: vpdpwusd ymm12, ymm13, ymm4 -0xc4,0x62,0x15,0xd2,0xe4 - -# ATT: vpdpwusd %xmm4, %xmm13, %xmm12 -# INTEL: vpdpwusd xmm12, xmm13, xmm4 -0xc4,0x62,0x11,0xd2,0xe4 - -# ATT: vpdpwusd 268435456(%rbp,%r14,8), %ymm13, %ymm12 -# INTEL: vpdpwusd ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x15,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwusd 291(%r8,%rax,4), %ymm13, %ymm12 -# INTEL: vpdpwusd ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x15,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwusd (%rip), %ymm13, %ymm12 -# INTEL: vpdpwusd ymm12, ymm13, ymmword ptr [rip] -0xc4,0x62,0x15,0xd2,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwusd -1024(,%rbp,2), %ymm13, %ymm12 -# INTEL: vpdpwusd ymm12, ymm13, ymmword ptr [2*rbp - 1024] -0xc4,0x62,0x15,0xd2,0x24,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwusd 4064(%rcx), %ymm13, %ymm12 -# INTEL: vpdpwusd ymm12, ymm13, ymmword ptr [rcx + 4064] -0xc4,0x62,0x15,0xd2,0xa1,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwusd -4096(%rdx), %ymm13, %ymm12 -# INTEL: vpdpwusd ymm12, ymm13, ymmword ptr [rdx - 4096] -0xc4,0x62,0x15,0xd2,0xa2,0x00,0xf0,0xff,0xff - -# ATT: vpdpwusd 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vpdpwusd xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x11,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwusd 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vpdpwusd xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x11,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwusd (%rip), %xmm13, %xmm12 -# INTEL: vpdpwusd xmm12, xmm13, xmmword ptr [rip] -0xc4,0x62,0x11,0xd2,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwusd -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vpdpwusd xmm12, xmm13, xmmword ptr [2*rbp - 512] -0xc4,0x62,0x11,0xd2,0x24,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwusd 2032(%rcx), %xmm13, %xmm12 -# INTEL: vpdpwusd xmm12, xmm13, xmmword ptr [rcx + 2032] -0xc4,0x62,0x11,0xd2,0xa1,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwusd -2048(%rdx), %xmm13, %xmm12 -# INTEL: vpdpwusd xmm12, xmm13, xmmword ptr [rdx - 2048] -0xc4,0x62,0x11,0xd2,0xa2,0x00,0xf8,0xff,0xff - -# ATT: vpdpwusds %ymm4, %ymm13, %ymm12 -# INTEL: vpdpwusds ymm12, ymm13, ymm4 -0xc4,0x62,0x15,0xd3,0xe4 - -# ATT: vpdpwusds %xmm4, %xmm13, %xmm12 -# INTEL: vpdpwusds xmm12, xmm13, xmm4 -0xc4,0x62,0x11,0xd3,0xe4 - -# ATT: vpdpwusds 268435456(%rbp,%r14,8), %ymm13, %ymm12 -# INTEL: vpdpwusds ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x15,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwusds 291(%r8,%rax,4), %ymm13, %ymm12 -# INTEL: vpdpwusds ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x15,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwusds (%rip), %ymm13, %ymm12 -# INTEL: vpdpwusds ymm12, ymm13, ymmword ptr [rip] -0xc4,0x62,0x15,0xd3,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwusds -1024(,%rbp,2), %ymm13, %ymm12 -# INTEL: vpdpwusds ymm12, ymm13, ymmword ptr [2*rbp - 1024] -0xc4,0x62,0x15,0xd3,0x24,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwusds 4064(%rcx), %ymm13, %ymm12 -# INTEL: vpdpwusds ymm12, ymm13, ymmword ptr [rcx + 4064] -0xc4,0x62,0x15,0xd3,0xa1,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwusds -4096(%rdx), %ymm13, %ymm12 -# INTEL: vpdpwusds ymm12, ymm13, ymmword ptr [rdx - 4096] -0xc4,0x62,0x15,0xd3,0xa2,0x00,0xf0,0xff,0xff - -# ATT: vpdpwusds 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vpdpwusds xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x11,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwusds 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vpdpwusds xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x11,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwusds (%rip), %xmm13, %xmm12 -# INTEL: vpdpwusds xmm12, xmm13, xmmword ptr [rip] -0xc4,0x62,0x11,0xd3,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwusds -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vpdpwusds xmm12, xmm13, xmmword ptr [2*rbp - 512] -0xc4,0x62,0x11,0xd3,0x24,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwusds 2032(%rcx), %xmm13, %xmm12 -# INTEL: vpdpwusds xmm12, xmm13, xmmword ptr [rcx + 2032] -0xc4,0x62,0x11,0xd3,0xa1,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwusds -2048(%rdx), %xmm13, %xmm12 -# INTEL: vpdpwusds xmm12, xmm13, xmmword ptr [rdx - 2048] -0xc4,0x62,0x11,0xd3,0xa2,0x00,0xf8,0xff,0xff - -# ATT: vpdpwuud %ymm4, %ymm13, %ymm12 -# INTEL: vpdpwuud ymm12, ymm13, ymm4 -0xc4,0x62,0x14,0xd2,0xe4 - -# ATT: vpdpwuud %xmm4, %xmm13, %xmm12 -# INTEL: vpdpwuud xmm12, xmm13, xmm4 -0xc4,0x62,0x10,0xd2,0xe4 - -# ATT: vpdpwuud 268435456(%rbp,%r14,8), %ymm13, %ymm12 -# INTEL: vpdpwuud ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x14,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwuud 291(%r8,%rax,4), %ymm13, %ymm12 -# INTEL: vpdpwuud ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x14,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwuud (%rip), %ymm13, %ymm12 -# INTEL: vpdpwuud ymm12, ymm13, ymmword ptr [rip] -0xc4,0x62,0x14,0xd2,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwuud -1024(,%rbp,2), %ymm13, %ymm12 -# INTEL: vpdpwuud ymm12, ymm13, ymmword ptr [2*rbp - 1024] -0xc4,0x62,0x14,0xd2,0x24,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwuud 4064(%rcx), %ymm13, %ymm12 -# INTEL: vpdpwuud ymm12, ymm13, ymmword ptr [rcx + 4064] -0xc4,0x62,0x14,0xd2,0xa1,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwuud -4096(%rdx), %ymm13, %ymm12 -# INTEL: vpdpwuud ymm12, ymm13, ymmword ptr [rdx - 4096] -0xc4,0x62,0x14,0xd2,0xa2,0x00,0xf0,0xff,0xff - -# ATT: vpdpwuud 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vpdpwuud xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x10,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwuud 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vpdpwuud xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x10,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwuud (%rip), %xmm13, %xmm12 -# INTEL: vpdpwuud xmm12, xmm13, xmmword ptr [rip] -0xc4,0x62,0x10,0xd2,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwuud -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vpdpwuud xmm12, xmm13, xmmword ptr [2*rbp - 512] -0xc4,0x62,0x10,0xd2,0x24,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwuud 2032(%rcx), %xmm13, %xmm12 -# INTEL: vpdpwuud xmm12, xmm13, xmmword ptr [rcx + 2032] -0xc4,0x62,0x10,0xd2,0xa1,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwuud -2048(%rdx), %xmm13, %xmm12 -# INTEL: vpdpwuud xmm12, xmm13, xmmword ptr [rdx - 2048] -0xc4,0x62,0x10,0xd2,0xa2,0x00,0xf8,0xff,0xff - -# ATT: vpdpwuuds %ymm4, %ymm13, %ymm12 -# INTEL: vpdpwuuds ymm12, ymm13, ymm4 -0xc4,0x62,0x14,0xd3,0xe4 - -# ATT: vpdpwuuds %xmm4, %xmm13, %xmm12 -# INTEL: vpdpwuuds xmm12, xmm13, xmm4 -0xc4,0x62,0x10,0xd3,0xe4 - -# ATT: vpdpwuuds 268435456(%rbp,%r14,8), %ymm13, %ymm12 -# INTEL: vpdpwuuds ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x14,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwuuds 291(%r8,%rax,4), %ymm13, %ymm12 -# INTEL: vpdpwuuds ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x14,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwuuds (%rip), %ymm13, %ymm12 -# INTEL: vpdpwuuds ymm12, ymm13, ymmword ptr [rip] -0xc4,0x62,0x14,0xd3,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwuuds -1024(,%rbp,2), %ymm13, %ymm12 -# INTEL: vpdpwuuds ymm12, ymm13, ymmword ptr [2*rbp - 1024] -0xc4,0x62,0x14,0xd3,0x24,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vpdpwuuds 4064(%rcx), %ymm13, %ymm12 -# INTEL: vpdpwuuds ymm12, ymm13, ymmword ptr [rcx + 4064] -0xc4,0x62,0x14,0xd3,0xa1,0xe0,0x0f,0x00,0x00 - -# ATT: vpdpwuuds -4096(%rdx), %ymm13, %ymm12 -# INTEL: vpdpwuuds ymm12, ymm13, ymmword ptr [rdx - 4096] -0xc4,0x62,0x14,0xd3,0xa2,0x00,0xf0,0xff,0xff - -# ATT: vpdpwuuds 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vpdpwuuds xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x10,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vpdpwuuds 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vpdpwuuds xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x10,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vpdpwuuds (%rip), %xmm13, %xmm12 -# INTEL: vpdpwuuds xmm12, xmm13, xmmword ptr [rip] -0xc4,0x62,0x10,0xd3,0x25,0x00,0x00,0x00,0x00 - -# ATT: vpdpwuuds -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vpdpwuuds xmm12, xmm13, xmmword ptr [2*rbp - 512] -0xc4,0x62,0x10,0xd3,0x24,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vpdpwuuds 2032(%rcx), %xmm13, %xmm12 -# INTEL: vpdpwuuds xmm12, xmm13, xmmword ptr [rcx + 2032] -0xc4,0x62,0x10,0xd3,0xa1,0xf0,0x07,0x00,0x00 - -# ATT: vpdpwuuds -2048(%rdx), %xmm13, %xmm12 -# INTEL: vpdpwuuds xmm12, xmm13, xmmword ptr [rdx - 2048] -0xc4,0x62,0x10,0xd3,0xa2,0x00,0xf8,0xff,0xff - diff --git a/llvm/test/MC/Disassembler/X86/avx_ne_convert-32.txt b/llvm/test/MC/Disassembler/X86/avx_ne_convert-32.txt deleted file mode 100644 index 6dda0057fc6c5..0000000000000 --- a/llvm/test/MC/Disassembler/X86/avx_ne_convert-32.txt +++ /dev/null @@ -1,335 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s --check-prefixes=ATT -# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL - -# ATT: vbcstnebf162ps 268435456(%esp,%esi,8), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x7a,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vbcstnebf162ps 291(%edi,%eax,4), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [edi + 4*eax + 291] -0xc4,0xe2,0x7a,0xb1,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vbcstnebf162ps (%eax), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [eax] -0xc4,0xe2,0x7a,0xb1,0x10 - -# ATT: vbcstnebf162ps -64(,%ebp,2), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [2*ebp - 64] -0xc4,0xe2,0x7a,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff - -# ATT: vbcstnebf162ps 254(%ecx), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [ecx + 254] -0xc4,0xe2,0x7a,0xb1,0x91,0xfe,0x00,0x00,0x00 - -# ATT: vbcstnebf162ps -256(%edx), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [edx - 256] -0xc4,0xe2,0x7a,0xb1,0x92,0x00,0xff,0xff,0xff - -# ATT: vbcstnebf162ps 268435456(%esp,%esi,8), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x7e,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vbcstnebf162ps 291(%edi,%eax,4), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [edi + 4*eax + 291] -0xc4,0xe2,0x7e,0xb1,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vbcstnebf162ps (%eax), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [eax] -0xc4,0xe2,0x7e,0xb1,0x10 - -# ATT: vbcstnebf162ps -64(,%ebp,2), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [2*ebp - 64] -0xc4,0xe2,0x7e,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff - -# ATT: vbcstnebf162ps 254(%ecx), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [ecx + 254] -0xc4,0xe2,0x7e,0xb1,0x91,0xfe,0x00,0x00,0x00 - -# ATT: vbcstnebf162ps -256(%edx), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [edx - 256] -0xc4,0xe2,0x7e,0xb1,0x92,0x00,0xff,0xff,0xff - -# ATT: vbcstnesh2ps 268435456(%esp,%esi,8), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x79,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vbcstnesh2ps 291(%edi,%eax,4), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [edi + 4*eax + 291] -0xc4,0xe2,0x79,0xb1,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vbcstnesh2ps (%eax), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [eax] -0xc4,0xe2,0x79,0xb1,0x10 - -# ATT: vbcstnesh2ps -64(,%ebp,2), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [2*ebp - 64] -0xc4,0xe2,0x79,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff - -# ATT: vbcstnesh2ps 254(%ecx), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [ecx + 254] -0xc4,0xe2,0x79,0xb1,0x91,0xfe,0x00,0x00,0x00 - -# ATT: vbcstnesh2ps -256(%edx), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [edx - 256] -0xc4,0xe2,0x79,0xb1,0x92,0x00,0xff,0xff,0xff - -# ATT: vbcstnesh2ps 268435456(%esp,%esi,8), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x7d,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vbcstnesh2ps 291(%edi,%eax,4), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [edi + 4*eax + 291] -0xc4,0xe2,0x7d,0xb1,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vbcstnesh2ps (%eax), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [eax] -0xc4,0xe2,0x7d,0xb1,0x10 - -# ATT: vbcstnesh2ps -64(,%ebp,2), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [2*ebp - 64] -0xc4,0xe2,0x7d,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff - -# ATT: vbcstnesh2ps 254(%ecx), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [ecx + 254] -0xc4,0xe2,0x7d,0xb1,0x91,0xfe,0x00,0x00,0x00 - -# ATT: vbcstnesh2ps -256(%edx), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [edx - 256] -0xc4,0xe2,0x7d,0xb1,0x92,0x00,0xff,0xff,0xff - -# ATT: vcvtneebf162ps 268435456(%esp,%esi,8), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x7a,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vcvtneebf162ps 291(%edi,%eax,4), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x7a,0xb0,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vcvtneebf162ps (%eax), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [eax] -0xc4,0xe2,0x7a,0xb0,0x10 - -# ATT: vcvtneebf162ps -512(,%ebp,2), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x7a,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vcvtneebf162ps 2032(%ecx), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x7a,0xb0,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vcvtneebf162ps -2048(%edx), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [edx - 2048] -0xc4,0xe2,0x7a,0xb0,0x92,0x00,0xf8,0xff,0xff - -# ATT: vcvtneebf162ps 268435456(%esp,%esi,8), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x7e,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vcvtneebf162ps 291(%edi,%eax,4), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x7e,0xb0,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vcvtneebf162ps (%eax), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [eax] -0xc4,0xe2,0x7e,0xb0,0x10 - -# ATT: vcvtneebf162ps -1024(,%ebp,2), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x7e,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vcvtneebf162ps 4064(%ecx), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x7e,0xb0,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vcvtneebf162ps -4096(%edx), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [edx - 4096] -0xc4,0xe2,0x7e,0xb0,0x92,0x00,0xf0,0xff,0xff - -# ATT: vcvtneeph2ps 268435456(%esp,%esi,8), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x79,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vcvtneeph2ps 291(%edi,%eax,4), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x79,0xb0,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vcvtneeph2ps (%eax), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [eax] -0xc4,0xe2,0x79,0xb0,0x10 - -# ATT: vcvtneeph2ps -512(,%ebp,2), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x79,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vcvtneeph2ps 2032(%ecx), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x79,0xb0,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vcvtneeph2ps -2048(%edx), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [edx - 2048] -0xc4,0xe2,0x79,0xb0,0x92,0x00,0xf8,0xff,0xff - -# ATT: vcvtneeph2ps 268435456(%esp,%esi,8), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x7d,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vcvtneeph2ps 291(%edi,%eax,4), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x7d,0xb0,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vcvtneeph2ps (%eax), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [eax] -0xc4,0xe2,0x7d,0xb0,0x10 - -# ATT: vcvtneeph2ps -1024(,%ebp,2), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x7d,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vcvtneeph2ps 4064(%ecx), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x7d,0xb0,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vcvtneeph2ps -4096(%edx), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [edx - 4096] -0xc4,0xe2,0x7d,0xb0,0x92,0x00,0xf0,0xff,0xff - -# ATT: vcvtneobf162ps 268435456(%esp,%esi,8), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x7b,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vcvtneobf162ps 291(%edi,%eax,4), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x7b,0xb0,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vcvtneobf162ps (%eax), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [eax] -0xc4,0xe2,0x7b,0xb0,0x10 - -# ATT: vcvtneobf162ps -512(,%ebp,2), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x7b,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vcvtneobf162ps 2032(%ecx), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x7b,0xb0,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vcvtneobf162ps -2048(%edx), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [edx - 2048] -0xc4,0xe2,0x7b,0xb0,0x92,0x00,0xf8,0xff,0xff - -# ATT: vcvtneobf162ps 268435456(%esp,%esi,8), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x7f,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vcvtneobf162ps 291(%edi,%eax,4), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x7f,0xb0,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vcvtneobf162ps (%eax), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [eax] -0xc4,0xe2,0x7f,0xb0,0x10 - -# ATT: vcvtneobf162ps -1024(,%ebp,2), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x7f,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vcvtneobf162ps 4064(%ecx), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x7f,0xb0,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vcvtneobf162ps -4096(%edx), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [edx - 4096] -0xc4,0xe2,0x7f,0xb0,0x92,0x00,0xf0,0xff,0xff - -# ATT: vcvtneoph2ps 268435456(%esp,%esi,8), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x78,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vcvtneoph2ps 291(%edi,%eax,4), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x78,0xb0,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vcvtneoph2ps (%eax), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [eax] -0xc4,0xe2,0x78,0xb0,0x10 - -# ATT: vcvtneoph2ps -512(,%ebp,2), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x78,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vcvtneoph2ps 2032(%ecx), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x78,0xb0,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vcvtneoph2ps -2048(%edx), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [edx - 2048] -0xc4,0xe2,0x78,0xb0,0x92,0x00,0xf8,0xff,0xff - -# ATT: vcvtneoph2ps 268435456(%esp,%esi,8), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x7c,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vcvtneoph2ps 291(%edi,%eax,4), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x7c,0xb0,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vcvtneoph2ps (%eax), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [eax] -0xc4,0xe2,0x7c,0xb0,0x10 - -# ATT: vcvtneoph2ps -1024(,%ebp,2), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x7c,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vcvtneoph2ps 4064(%ecx), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x7c,0xb0,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vcvtneoph2ps -4096(%edx), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [edx - 4096] -0xc4,0xe2,0x7c,0xb0,0x92,0x00,0xf0,0xff,0xff - -# ATT: {vex} vcvtneps2bf16 %xmm3, %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmm3 -0xc4,0xe2,0x7a,0x72,0xd3 - -# ATT: {vex} vcvtneps2bf16 %ymm3, %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, ymm3 -0xc4,0xe2,0x7e,0x72,0xd3 - -# ATT: {vex} vcvtneps2bf16x 268435456(%esp,%esi,8), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x7a,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: {vex} vcvtneps2bf16x 291(%edi,%eax,4), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x7a,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: {vex} vcvtneps2bf16x (%eax), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [eax] -0xc4,0xe2,0x7a,0x72,0x10 - -# ATT: {vex} vcvtneps2bf16x -512(,%ebp,2), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x7a,0x72,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: {vex} vcvtneps2bf16x 2032(%ecx), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x7a,0x72,0x91,0xf0,0x07,0x00,0x00 - -# ATT: {vex} vcvtneps2bf16x -2048(%edx), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [edx - 2048] -0xc4,0xe2,0x7a,0x72,0x92,0x00,0xf8,0xff,0xff - -# ATT: {vex} vcvtneps2bf16y -1024(,%ebp,2), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x7e,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: {vex} vcvtneps2bf16y 4064(%ecx), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x7e,0x72,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: {vex} vcvtneps2bf16y -4096(%edx), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, ymmword ptr [edx - 4096] -0xc4,0xe2,0x7e,0x72,0x92,0x00,0xf0,0xff,0xff - diff --git a/llvm/test/MC/Disassembler/X86/avx_ne_convert-64.txt b/llvm/test/MC/Disassembler/X86/avx_ne_convert-64.txt deleted file mode 100644 index 1eadb6a3454c4..0000000000000 --- a/llvm/test/MC/Disassembler/X86/avx_ne_convert-64.txt +++ /dev/null @@ -1,335 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT -# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL - -# ATT: vbcstnebf162ps 268435456(%rbp,%r14,8), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x7a,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vbcstnebf162ps 291(%r8,%rax,4), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x7a,0xb1,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vbcstnebf162ps (%rip), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [rip] -0xc4,0xe2,0x7a,0xb1,0x15,0x00,0x00,0x00,0x00 - -# ATT: vbcstnebf162ps -64(,%rbp,2), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [2*rbp - 64] -0xc4,0xe2,0x7a,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff - -# ATT: vbcstnebf162ps 254(%rcx), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [rcx + 254] -0xc4,0xe2,0x7a,0xb1,0x91,0xfe,0x00,0x00,0x00 - -# ATT: vbcstnebf162ps -256(%rdx), %xmm2 -# INTEL: vbcstnebf162ps xmm2, word ptr [rdx - 256] -0xc4,0xe2,0x7a,0xb1,0x92,0x00,0xff,0xff,0xff - -# ATT: vbcstnebf162ps 268435456(%rbp,%r14,8), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x7e,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vbcstnebf162ps 291(%r8,%rax,4), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x7e,0xb1,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vbcstnebf162ps (%rip), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [rip] -0xc4,0xe2,0x7e,0xb1,0x15,0x00,0x00,0x00,0x00 - -# ATT: vbcstnebf162ps -64(,%rbp,2), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [2*rbp - 64] -0xc4,0xe2,0x7e,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff - -# ATT: vbcstnebf162ps 254(%rcx), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [rcx + 254] -0xc4,0xe2,0x7e,0xb1,0x91,0xfe,0x00,0x00,0x00 - -# ATT: vbcstnebf162ps -256(%rdx), %ymm2 -# INTEL: vbcstnebf162ps ymm2, word ptr [rdx - 256] -0xc4,0xe2,0x7e,0xb1,0x92,0x00,0xff,0xff,0xff - -# ATT: vbcstnesh2ps 268435456(%rbp,%r14,8), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x79,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vbcstnesh2ps 291(%r8,%rax,4), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x79,0xb1,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vbcstnesh2ps (%rip), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [rip] -0xc4,0xe2,0x79,0xb1,0x15,0x00,0x00,0x00,0x00 - -# ATT: vbcstnesh2ps -64(,%rbp,2), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [2*rbp - 64] -0xc4,0xe2,0x79,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff - -# ATT: vbcstnesh2ps 254(%rcx), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [rcx + 254] -0xc4,0xe2,0x79,0xb1,0x91,0xfe,0x00,0x00,0x00 - -# ATT: vbcstnesh2ps -256(%rdx), %xmm2 -# INTEL: vbcstnesh2ps xmm2, word ptr [rdx - 256] -0xc4,0xe2,0x79,0xb1,0x92,0x00,0xff,0xff,0xff - -# ATT: vbcstnesh2ps 268435456(%rbp,%r14,8), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x7d,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vbcstnesh2ps 291(%r8,%rax,4), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x7d,0xb1,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vbcstnesh2ps (%rip), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [rip] -0xc4,0xe2,0x7d,0xb1,0x15,0x00,0x00,0x00,0x00 - -# ATT: vbcstnesh2ps -64(,%rbp,2), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [2*rbp - 64] -0xc4,0xe2,0x7d,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff - -# ATT: vbcstnesh2ps 254(%rcx), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [rcx + 254] -0xc4,0xe2,0x7d,0xb1,0x91,0xfe,0x00,0x00,0x00 - -# ATT: vbcstnesh2ps -256(%rdx), %ymm2 -# INTEL: vbcstnesh2ps ymm2, word ptr [rdx - 256] -0xc4,0xe2,0x7d,0xb1,0x92,0x00,0xff,0xff,0xff - -# ATT: vcvtneebf162ps 268435456(%rbp,%r14,8), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x7a,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vcvtneebf162ps 291(%r8,%rax,4), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x7a,0xb0,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vcvtneebf162ps (%rip), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [rip] -0xc4,0xe2,0x7a,0xb0,0x15,0x00,0x00,0x00,0x00 - -# ATT: vcvtneebf162ps -512(,%rbp,2), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [2*rbp - 512] -0xc4,0xe2,0x7a,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vcvtneebf162ps 2032(%rcx), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [rcx + 2032] -0xc4,0xe2,0x7a,0xb0,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vcvtneebf162ps -2048(%rdx), %xmm2 -# INTEL: vcvtneebf162ps xmm2, xmmword ptr [rdx - 2048] -0xc4,0xe2,0x7a,0xb0,0x92,0x00,0xf8,0xff,0xff - -# ATT: vcvtneebf162ps 268435456(%rbp,%r14,8), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x7e,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vcvtneebf162ps 291(%r8,%rax,4), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x7e,0xb0,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vcvtneebf162ps (%rip), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [rip] -0xc4,0xe2,0x7e,0xb0,0x15,0x00,0x00,0x00,0x00 - -# ATT: vcvtneebf162ps -1024(,%rbp,2), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [2*rbp - 1024] -0xc4,0xe2,0x7e,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vcvtneebf162ps 4064(%rcx), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [rcx + 4064] -0xc4,0xe2,0x7e,0xb0,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vcvtneebf162ps -4096(%rdx), %ymm2 -# INTEL: vcvtneebf162ps ymm2, ymmword ptr [rdx - 4096] -0xc4,0xe2,0x7e,0xb0,0x92,0x00,0xf0,0xff,0xff - -# ATT: vcvtneeph2ps 268435456(%rbp,%r14,8), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x79,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vcvtneeph2ps 291(%r8,%rax,4), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x79,0xb0,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vcvtneeph2ps (%rip), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [rip] -0xc4,0xe2,0x79,0xb0,0x15,0x00,0x00,0x00,0x00 - -# ATT: vcvtneeph2ps -512(,%rbp,2), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [2*rbp - 512] -0xc4,0xe2,0x79,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vcvtneeph2ps 2032(%rcx), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [rcx + 2032] -0xc4,0xe2,0x79,0xb0,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vcvtneeph2ps -2048(%rdx), %xmm2 -# INTEL: vcvtneeph2ps xmm2, xmmword ptr [rdx - 2048] -0xc4,0xe2,0x79,0xb0,0x92,0x00,0xf8,0xff,0xff - -# ATT: vcvtneeph2ps 268435456(%rbp,%r14,8), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x7d,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vcvtneeph2ps 291(%r8,%rax,4), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x7d,0xb0,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vcvtneeph2ps (%rip), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [rip] -0xc4,0xe2,0x7d,0xb0,0x15,0x00,0x00,0x00,0x00 - -# ATT: vcvtneeph2ps -1024(,%rbp,2), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [2*rbp - 1024] -0xc4,0xe2,0x7d,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vcvtneeph2ps 4064(%rcx), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [rcx + 4064] -0xc4,0xe2,0x7d,0xb0,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vcvtneeph2ps -4096(%rdx), %ymm2 -# INTEL: vcvtneeph2ps ymm2, ymmword ptr [rdx - 4096] -0xc4,0xe2,0x7d,0xb0,0x92,0x00,0xf0,0xff,0xff - -# ATT: vcvtneobf162ps 268435456(%rbp,%r14,8), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x7b,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vcvtneobf162ps 291(%r8,%rax,4), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x7b,0xb0,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vcvtneobf162ps (%rip), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [rip] -0xc4,0xe2,0x7b,0xb0,0x15,0x00,0x00,0x00,0x00 - -# ATT: vcvtneobf162ps -512(,%rbp,2), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [2*rbp - 512] -0xc4,0xe2,0x7b,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vcvtneobf162ps 2032(%rcx), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [rcx + 2032] -0xc4,0xe2,0x7b,0xb0,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vcvtneobf162ps -2048(%rdx), %xmm2 -# INTEL: vcvtneobf162ps xmm2, xmmword ptr [rdx - 2048] -0xc4,0xe2,0x7b,0xb0,0x92,0x00,0xf8,0xff,0xff - -# ATT: vcvtneobf162ps 268435456(%rbp,%r14,8), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x7f,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vcvtneobf162ps 291(%r8,%rax,4), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x7f,0xb0,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vcvtneobf162ps (%rip), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [rip] -0xc4,0xe2,0x7f,0xb0,0x15,0x00,0x00,0x00,0x00 - -# ATT: vcvtneobf162ps -1024(,%rbp,2), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [2*rbp - 1024] -0xc4,0xe2,0x7f,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vcvtneobf162ps 4064(%rcx), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [rcx + 4064] -0xc4,0xe2,0x7f,0xb0,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vcvtneobf162ps -4096(%rdx), %ymm2 -# INTEL: vcvtneobf162ps ymm2, ymmword ptr [rdx - 4096] -0xc4,0xe2,0x7f,0xb0,0x92,0x00,0xf0,0xff,0xff - -# ATT: vcvtneoph2ps 268435456(%rbp,%r14,8), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x78,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vcvtneoph2ps 291(%r8,%rax,4), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x78,0xb0,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vcvtneoph2ps (%rip), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [rip] -0xc4,0xe2,0x78,0xb0,0x15,0x00,0x00,0x00,0x00 - -# ATT: vcvtneoph2ps -512(,%rbp,2), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [2*rbp - 512] -0xc4,0xe2,0x78,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vcvtneoph2ps 2032(%rcx), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [rcx + 2032] -0xc4,0xe2,0x78,0xb0,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vcvtneoph2ps -2048(%rdx), %xmm2 -# INTEL: vcvtneoph2ps xmm2, xmmword ptr [rdx - 2048] -0xc4,0xe2,0x78,0xb0,0x92,0x00,0xf8,0xff,0xff - -# ATT: vcvtneoph2ps 268435456(%rbp,%r14,8), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x7c,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vcvtneoph2ps 291(%r8,%rax,4), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x7c,0xb0,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: vcvtneoph2ps (%rip), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [rip] -0xc4,0xe2,0x7c,0xb0,0x15,0x00,0x00,0x00,0x00 - -# ATT: vcvtneoph2ps -1024(,%rbp,2), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [2*rbp - 1024] -0xc4,0xe2,0x7c,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vcvtneoph2ps 4064(%rcx), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [rcx + 4064] -0xc4,0xe2,0x7c,0xb0,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vcvtneoph2ps -4096(%rdx), %ymm2 -# INTEL: vcvtneoph2ps ymm2, ymmword ptr [rdx - 4096] -0xc4,0xe2,0x7c,0xb0,0x92,0x00,0xf0,0xff,0xff - -# ATT: {vex} vcvtneps2bf16 %xmm3, %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmm3 -0xc4,0xe2,0x7a,0x72,0xd3 - -# ATT: {vex} vcvtneps2bf16 %ymm3, %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, ymm3 -0xc4,0xe2,0x7e,0x72,0xd3 - -# ATT: {vex} vcvtneps2bf16x 268435456(%rbp,%r14,8), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0xa2,0x7a,0x72,0x94,0xf5,0x00,0x00,0x00,0x10 - -# ATT: {vex} vcvtneps2bf16x 291(%r8,%rax,4), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [r8 + 4*rax + 291] -0xc4,0xc2,0x7a,0x72,0x94,0x80,0x23,0x01,0x00,0x00 - -# ATT: {vex} vcvtneps2bf16x (%rip), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [rip] -0xc4,0xe2,0x7a,0x72,0x15,0x00,0x00,0x00,0x00 - -# ATT: {vex} vcvtneps2bf16x -512(,%rbp,2), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [2*rbp - 512] -0xc4,0xe2,0x7a,0x72,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: {vex} vcvtneps2bf16x 2032(%rcx), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [rcx + 2032] -0xc4,0xe2,0x7a,0x72,0x91,0xf0,0x07,0x00,0x00 - -# ATT: {vex} vcvtneps2bf16x -2048(%rdx), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, xmmword ptr [rdx - 2048] -0xc4,0xe2,0x7a,0x72,0x92,0x00,0xf8,0xff,0xff - -# ATT: {vex} vcvtneps2bf16y -1024(,%rbp,2), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, ymmword ptr [2*rbp - 1024] -0xc4,0xe2,0x7e,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: {vex} vcvtneps2bf16y 4064(%rcx), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, ymmword ptr [rcx + 4064] -0xc4,0xe2,0x7e,0x72,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: {vex} vcvtneps2bf16y -4096(%rdx), %xmm2 -# INTEL: {vex} vcvtneps2bf16 xmm2, ymmword ptr [rdx - 4096] -0xc4,0xe2,0x7e,0x72,0x92,0x00,0xf0,0xff,0xff - diff --git a/llvm/test/MC/Disassembler/X86/sha512-32.txt b/llvm/test/MC/Disassembler/X86/sha512-32.txt deleted file mode 100644 index a3b16fd18285b..0000000000000 --- a/llvm/test/MC/Disassembler/X86/sha512-32.txt +++ /dev/null @@ -1,15 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT -# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL - -# ATT: vsha512msg1 %xmm3, %ymm2 -# INTEL: vsha512msg1 ymm2, xmm3 -0xc4,0xe2,0x7f,0xcc,0xd3 - -# ATT: vsha512msg2 %ymm3, %ymm2 -# INTEL: vsha512msg2 ymm2, ymm3 -0xc4,0xe2,0x7f,0xcd,0xd3 - -# ATT: vsha512rnds2 %xmm4, %ymm3, %ymm2 -# INTEL: vsha512rnds2 ymm2, ymm3, xmm4 -0xc4,0xe2,0x67,0xcb,0xd4 - diff --git a/llvm/test/MC/Disassembler/X86/sha512-64.txt b/llvm/test/MC/Disassembler/X86/sha512-64.txt deleted file mode 100644 index 251585ec8802f..0000000000000 --- a/llvm/test/MC/Disassembler/X86/sha512-64.txt +++ /dev/null @@ -1,15 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT -# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL - -# ATT: vsha512msg1 %xmm3, %ymm12 -# INTEL: vsha512msg1 ymm12, xmm3 -0xc4,0x62,0x7f,0xcc,0xe3 - -# ATT: vsha512msg2 %ymm3, %ymm12 -# INTEL: vsha512msg2 ymm12, ymm3 -0xc4,0x62,0x7f,0xcd,0xe3 - -# ATT: vsha512rnds2 %xmm4, %ymm3, %ymm12 -# INTEL: vsha512rnds2 ymm12, ymm3, xmm4 -0xc4,0x62,0x67,0xcb,0xe4 - diff --git a/llvm/test/MC/Disassembler/X86/sm3-32.txt b/llvm/test/MC/Disassembler/X86/sm3-32.txt deleted file mode 100644 index d34a1581aa11e..0000000000000 --- a/llvm/test/MC/Disassembler/X86/sm3-32.txt +++ /dev/null @@ -1,87 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s --check-prefixes=ATT -# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL - -# ATT: vsm3msg1 %xmm4, %xmm3, %xmm2 -# INTEL: vsm3msg1 xmm2, xmm3, xmm4 -0xc4,0xe2,0x60,0xda,0xd4 - -# ATT: vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vsm3msg1 (%eax), %xmm3, %xmm2 -# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [eax] -0xc4,0xe2,0x60,0xda,0x10 - -# ATT: vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vsm3msg1 2032(%ecx), %xmm3, %xmm2 -# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vsm3msg1 -2048(%edx), %xmm3, %xmm2 -# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048] -0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff - -# ATT: vsm3msg2 %xmm4, %xmm3, %xmm2 -# INTEL: vsm3msg2 xmm2, xmm3, xmm4 -0xc4,0xe2,0x61,0xda,0xd4 - -# ATT: vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vsm3msg2 (%eax), %xmm3, %xmm2 -# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [eax] -0xc4,0xe2,0x61,0xda,0x10 - -# ATT: vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vsm3msg2 2032(%ecx), %xmm3, %xmm2 -# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vsm3msg2 -2048(%edx), %xmm3, %xmm2 -# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048] -0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff - -# ATT: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2 -# INTEL: vsm3rnds2 xmm2, xmm3, xmm4, 123 -0xc4,0xe3,0x61,0xde,0xd4,0x7b - -# ATT: vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123 -0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b - -# ATT: vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123 -0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b - -# ATT: vsm3rnds2 $123, (%eax), %xmm3, %xmm2 -# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123 -0xc4,0xe3,0x61,0xde,0x10,0x7b - -# ATT: vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123 -0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b - -# ATT: vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2 -# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123 -0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b - -# ATT: vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2 -# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123 -0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b - diff --git a/llvm/test/MC/Disassembler/X86/sm3-64.txt b/llvm/test/MC/Disassembler/X86/sm3-64.txt deleted file mode 100644 index 177b2fea10854..0000000000000 --- a/llvm/test/MC/Disassembler/X86/sm3-64.txt +++ /dev/null @@ -1,87 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT -# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL - -# ATT: vsm3msg1 %xmm4, %xmm13, %xmm12 -# INTEL: vsm3msg1 xmm12, xmm13, xmm4 -0xc4,0x62,0x10,0xda,0xe4 - -# ATT: vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vsm3msg1 (%rip), %xmm13, %xmm12 -# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rip] -0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00 - -# ATT: vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512] -0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vsm3msg1 2032(%rcx), %xmm13, %xmm12 -# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032] -0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00 - -# ATT: vsm3msg1 -2048(%rdx), %xmm13, %xmm12 -# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048] -0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff - -# ATT: vsm3msg2 %xmm4, %xmm13, %xmm12 -# INTEL: vsm3msg2 xmm12, xmm13, xmm4 -0xc4,0x62,0x11,0xda,0xe4 - -# ATT: vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vsm3msg2 (%rip), %xmm13, %xmm12 -# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rip] -0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00 - -# ATT: vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512] -0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vsm3msg2 2032(%rcx), %xmm13, %xmm12 -# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032] -0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00 - -# ATT: vsm3msg2 -2048(%rdx), %xmm13, %xmm12 -# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048] -0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff - -# ATT: vsm3rnds2 $123, %xmm4, %xmm13, %xmm12 -# INTEL: vsm3rnds2 xmm12, xmm13, xmm4, 123 -0xc4,0x63,0x11,0xde,0xe4,0x7b - -# ATT: vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123 -0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b - -# ATT: vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123 -0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b - -# ATT: vsm3rnds2 $123, (%rip), %xmm13, %xmm12 -# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123 -0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b - -# ATT: vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123 -0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b - -# ATT: vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12 -# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123 -0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b - -# ATT: vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12 -# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123 -0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b - diff --git a/llvm/test/MC/Disassembler/X86/sm4-32.txt b/llvm/test/MC/Disassembler/X86/sm4-32.txt deleted file mode 100644 index eb26ab8bbbba7..0000000000000 --- a/llvm/test/MC/Disassembler/X86/sm4-32.txt +++ /dev/null @@ -1,114 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s --check-prefixes=ATT -# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL - -# ATT: vsm4key4 %ymm4, %ymm3, %ymm2 -# INTEL: vsm4key4 ymm2, ymm3, ymm4 -0xc4,0xe2,0x66,0xda,0xd4 - -# ATT: vsm4key4 %xmm4, %xmm3, %xmm2 -# INTEL: vsm4key4 xmm2, xmm3, xmm4 -0xc4,0xe2,0x62,0xda,0xd4 - -# ATT: vsm4key4 268435456(%esp,%esi,8), %ymm3, %ymm2 -# INTEL: vsm4key4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x66,0xda,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vsm4key4 291(%edi,%eax,4), %ymm3, %ymm2 -# INTEL: vsm4key4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x66,0xda,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vsm4key4 (%eax), %ymm3, %ymm2 -# INTEL: vsm4key4 ymm2, ymm3, ymmword ptr [eax] -0xc4,0xe2,0x66,0xda,0x10 - -# ATT: vsm4key4 -1024(,%ebp,2), %ymm3, %ymm2 -# INTEL: vsm4key4 ymm2, ymm3, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x66,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vsm4key4 4064(%ecx), %ymm3, %ymm2 -# INTEL: vsm4key4 ymm2, ymm3, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x66,0xda,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vsm4key4 -4096(%edx), %ymm3, %ymm2 -# INTEL: vsm4key4 ymm2, ymm3, ymmword ptr [edx - 4096] -0xc4,0xe2,0x66,0xda,0x92,0x00,0xf0,0xff,0xff - -# ATT: vsm4key4 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vsm4key4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x62,0xda,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vsm4key4 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vsm4key4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x62,0xda,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vsm4key4 (%eax), %xmm3, %xmm2 -# INTEL: vsm4key4 xmm2, xmm3, xmmword ptr [eax] -0xc4,0xe2,0x62,0xda,0x10 - -# ATT: vsm4key4 -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vsm4key4 xmm2, xmm3, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x62,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vsm4key4 2032(%ecx), %xmm3, %xmm2 -# INTEL: vsm4key4 xmm2, xmm3, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x62,0xda,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vsm4key4 -2048(%edx), %xmm3, %xmm2 -# INTEL: vsm4key4 xmm2, xmm3, xmmword ptr [edx - 2048] -0xc4,0xe2,0x62,0xda,0x92,0x00,0xf8,0xff,0xff - -# ATT: vsm4rnds4 %ymm4, %ymm3, %ymm2 -# INTEL: vsm4rnds4 ymm2, ymm3, ymm4 -0xc4,0xe2,0x67,0xda,0xd4 - -# ATT: vsm4rnds4 %xmm4, %xmm3, %xmm2 -# INTEL: vsm4rnds4 xmm2, xmm3, xmm4 -0xc4,0xe2,0x63,0xda,0xd4 - -# ATT: vsm4rnds4 268435456(%esp,%esi,8), %ymm3, %ymm2 -# INTEL: vsm4rnds4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x67,0xda,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vsm4rnds4 291(%edi,%eax,4), %ymm3, %ymm2 -# INTEL: vsm4rnds4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x67,0xda,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vsm4rnds4 (%eax), %ymm3, %ymm2 -# INTEL: vsm4rnds4 ymm2, ymm3, ymmword ptr [eax] -0xc4,0xe2,0x67,0xda,0x10 - -# ATT: vsm4rnds4 -1024(,%ebp,2), %ymm3, %ymm2 -# INTEL: vsm4rnds4 ymm2, ymm3, ymmword ptr [2*ebp - 1024] -0xc4,0xe2,0x67,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vsm4rnds4 4064(%ecx), %ymm3, %ymm2 -# INTEL: vsm4rnds4 ymm2, ymm3, ymmword ptr [ecx + 4064] -0xc4,0xe2,0x67,0xda,0x91,0xe0,0x0f,0x00,0x00 - -# ATT: vsm4rnds4 -4096(%edx), %ymm3, %ymm2 -# INTEL: vsm4rnds4 ymm2, ymm3, ymmword ptr [edx - 4096] -0xc4,0xe2,0x67,0xda,0x92,0x00,0xf0,0xff,0xff - -# ATT: vsm4rnds4 268435456(%esp,%esi,8), %xmm3, %xmm2 -# INTEL: vsm4rnds4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0xc4,0xe2,0x63,0xda,0x94,0xf4,0x00,0x00,0x00,0x10 - -# ATT: vsm4rnds4 291(%edi,%eax,4), %xmm3, %xmm2 -# INTEL: vsm4rnds4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -0xc4,0xe2,0x63,0xda,0x94,0x87,0x23,0x01,0x00,0x00 - -# ATT: vsm4rnds4 (%eax), %xmm3, %xmm2 -# INTEL: vsm4rnds4 xmm2, xmm3, xmmword ptr [eax] -0xc4,0xe2,0x63,0xda,0x10 - -# ATT: vsm4rnds4 -512(,%ebp,2), %xmm3, %xmm2 -# INTEL: vsm4rnds4 xmm2, xmm3, xmmword ptr [2*ebp - 512] -0xc4,0xe2,0x63,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vsm4rnds4 2032(%ecx), %xmm3, %xmm2 -# INTEL: vsm4rnds4 xmm2, xmm3, xmmword ptr [ecx + 2032] -0xc4,0xe2,0x63,0xda,0x91,0xf0,0x07,0x00,0x00 - -# ATT: vsm4rnds4 -2048(%edx), %xmm3, %xmm2 -# INTEL: vsm4rnds4 xmm2, xmm3, xmmword ptr [edx - 2048] -0xc4,0xe2,0x63,0xda,0x92,0x00,0xf8,0xff,0xff diff --git a/llvm/test/MC/Disassembler/X86/sm4-64.txt b/llvm/test/MC/Disassembler/X86/sm4-64.txt deleted file mode 100644 index 3ef90d9a0bf4b..0000000000000 --- a/llvm/test/MC/Disassembler/X86/sm4-64.txt +++ /dev/null @@ -1,115 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT -# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL - -# ATT: vsm4key4 %ymm4, %ymm13, %ymm12 -# INTEL: vsm4key4 ymm12, ymm13, ymm4 -0xc4,0x62,0x16,0xda,0xe4 - -# ATT: vsm4key4 %xmm4, %xmm13, %xmm12 -# INTEL: vsm4key4 xmm12, xmm13, xmm4 -0xc4,0x62,0x12,0xda,0xe4 - -# ATT: vsm4key4 268435456(%rbp,%r14,8), %ymm13, %ymm12 -# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vsm4key4 291(%r8,%rax,4), %ymm13, %ymm12 -# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vsm4key4 (%rip), %ymm13, %ymm12 -# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [rip] -0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00 - -# ATT: vsm4key4 -1024(,%rbp,2), %ymm13, %ymm12 -# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024] -0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vsm4key4 4064(%rcx), %ymm13, %ymm12 -# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064] -0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00 - -# ATT: vsm4key4 -4096(%rdx), %ymm13, %ymm12 -# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096] -0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff - -# ATT: vsm4key4 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vsm4key4 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vsm4key4 (%rip), %xmm13, %xmm12 -# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [rip] -0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00 - -# ATT: vsm4key4 -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512] -0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vsm4key4 2032(%rcx), %xmm13, %xmm12 -# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032] -0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00 - -# ATT: vsm4key4 -2048(%rdx), %xmm13, %xmm12 -# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048] -0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff - -# ATT: vsm4rnds4 %ymm4, %ymm13, %ymm12 -# INTEL: vsm4rnds4 ymm12, ymm13, ymm4 -0xc4,0x62,0x17,0xda,0xe4 - -# ATT: vsm4rnds4 %xmm4, %xmm13, %xmm12 -# INTEL: vsm4rnds4 xmm12, xmm13, xmm4 -0xc4,0x62,0x13,0xda,0xe4 - -# ATT: vsm4rnds4 268435456(%rbp,%r14,8), %ymm13, %ymm12 -# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x17,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vsm4rnds4 291(%r8,%rax,4), %ymm13, %ymm12 -# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x17,0xda,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vsm4rnds4 (%rip), %ymm13, %ymm12 -# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [rip] -0xc4,0x62,0x17,0xda,0x25,0x00,0x00,0x00,0x00 - -# ATT: vsm4rnds4 -1024(,%rbp,2), %ymm13, %ymm12 -# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [2*rbp - 1024] -0xc4,0x62,0x17,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff - -# ATT: vsm4rnds4 4064(%rcx), %ymm13, %ymm12 -# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [rcx + 4064] -0xc4,0x62,0x17,0xda,0xa1,0xe0,0x0f,0x00,0x00 - -# ATT: vsm4rnds4 -4096(%rdx), %ymm13, %ymm12 -# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [rdx - 4096] -0xc4,0x62,0x17,0xda,0xa2,0x00,0xf0,0xff,0xff - -# ATT: vsm4rnds4 268435456(%rbp,%r14,8), %xmm13, %xmm12 -# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -0xc4,0x22,0x13,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10 - -# ATT: vsm4rnds4 291(%r8,%rax,4), %xmm13, %xmm12 -# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -0xc4,0x42,0x13,0xda,0xa4,0x80,0x23,0x01,0x00,0x00 - -# ATT: vsm4rnds4 (%rip), %xmm13, %xmm12 -# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [rip] -0xc4,0x62,0x13,0xda,0x25,0x00,0x00,0x00,0x00 - -# ATT: vsm4rnds4 -512(,%rbp,2), %xmm13, %xmm12 -# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [2*rbp - 512] -0xc4,0x62,0x13,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff - -# ATT: vsm4rnds4 2032(%rcx), %xmm13, %xmm12 -# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [rcx + 2032] -0xc4,0x62,0x13,0xda,0xa1,0xf0,0x07,0x00,0x00 - -# ATT: vsm4rnds4 -2048(%rdx), %xmm13, %xmm12 -# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [rdx - 2048] -0xc4,0x62,0x13,0xda,0xa2,0x00,0xf8,0xff,0xff - diff --git a/llvm/test/MC/ELF/AMDGPU/cfi.s b/llvm/test/MC/ELF/AMDGPU/cfi.s index 83713bbd03671..f70567f1bd9f8 100644 --- a/llvm/test/MC/ELF/AMDGPU/cfi.s +++ b/llvm/test/MC/ELF/AMDGPU/cfi.s @@ -16,14 +16,15 @@ f: # READELF: Section Headers: # READELF: Name Type Address Off Size ES Flg Lk Inf Al -# READELF: .debug_frame PROGBITS 0000000000000000 000048 000028 00 0 0 8 +# READELF: .debug_frame PROGBITS 0000000000000000 000048 000038 00 0 0 8 -# READELF: Relocation section '.rela.debug_frame' at offset 0xd0 contains 2 entries: +# READELF: Relocation section '.rela.debug_frame' at offset 0xe0 contains 2 entries: # READELF-NEXT: Offset Info Type Symbol's Value Symbol's Name + Addend -# READELF-NEXT: 0000000000000014 0000000300000006 R_AMDGPU_ABS32 0000000000000000 .debug_frame + 0 -# READELF-NEXT: 0000000000000018 0000000100000003 R_AMDGPU_ABS64 0000000000000000 .text + 0 +# READELF-NEXT: 0000000000000024 0000000300000006 R_AMDGPU_ABS32 0000000000000000 .debug_frame + 0 +# READELF-NEXT: 0000000000000028 0000000100000003 R_AMDGPU_ABS64 0000000000000000 .text + 0 # READELF: Hex dump of section '.debug_frame': -# READELF-NEXT: 0x00000000 0c000000 ffffffff 04000800 04041000 ................ -# READELF-NEXT: 0x00000010 14000000 00000000 00000000 00000000 ................ -# READELF-NEXT: 0x00000020 04000000 00000000 ........ +# READELF-NEXT: 0x00000000 1c000000 ffffffff 045b6c6c 766d3a76 .........[llvm:v +# READELF-NEXT: 0x00000010 302e305d 00080004 04100000 00000000 0.0]............ +# READELF-NEXT: 0x00000020 14000000 00000000 00000000 00000000 ................ +# READELF-NEXT: 0x00000030 04000000 00000000 ........ diff --git a/llvm/test/MC/ELF/cfi-register-pair.s b/llvm/test/MC/ELF/cfi-register-pair.s new file mode 100644 index 0000000000000..0e3d4a518b097 --- /dev/null +++ b/llvm/test/MC/ELF/cfi-register-pair.s @@ -0,0 +1,56 @@ +# RUN: llvm-mc -triple amdgcn-amd-amdhsa %s | FileCheck %s --check-prefix=ASM +# RUN: llvm-mc -filetype=obj -triple amdgcn-amd-amdhsa %s | llvm-readobj -S --sr --sd - | FileCheck %s + +# REQUIRES: amdgpu-registered-target + +# ASM: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +# ASM-NEXT: s_nop 0 + +f: + .cfi_startproc + s_nop 0 + .cfi_llvm_register_pair 16, 62, 32, 63, 32 + s_nop 0 + .cfi_endproc + +// CHECK: Section { +// CHECK: Index: +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 64 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 18000000 00000000 017A525B 6C6C766D |.........zR[llvm| +// CHECK-NEXT: 0010: 3A76302E 305D0004 0410011B 20000000 |:v0.0]...... ...| +// CHECK-NEXT: 0020: 20000000 00000000 08000000 00411010 | ............A..| +// CHECK-NEXT: 0030: 08903E93 04903F93 04000000 00000000 |..>...?.........| +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_INFO_LINK +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: +// CHECK-NEXT: Info: +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x24 R_AMDGPU_REL32 .text +// CHECK-NEXT: ] +// CHECK: } diff --git a/llvm/test/MC/ELF/cfi-vector-offset.s b/llvm/test/MC/ELF/cfi-vector-offset.s new file mode 100644 index 0000000000000..0f6c2c7634a9b --- /dev/null +++ b/llvm/test/MC/ELF/cfi-vector-offset.s @@ -0,0 +1,57 @@ +# RUN: llvm-mc -triple amdgcn-amd-amdhsa %s | FileCheck %s --check-prefix=ASM +# RUN: llvm-mc -filetype=obj -triple amdgcn-amd-amdhsa %s | llvm-readobj -S --sr --sd - | FileCheck %s + +# REQUIRES: amdgpu-registered-target + +# ASM: .cfi_llvm_vector_offset 2600, 32, 17, 64, 256 +# ASM-NEXT: s_nop 0 + +f: + .cfi_startproc + s_nop 0 + .cfi_llvm_vector_offset 2600, 32, 17, 64, 256 + s_nop 0 + .cfi_endproc + +// CHECK: Section { +// CHECK: Index: +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 72 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 18000000 00000000 017A525B 6C6C766D +// CHECK-NEXT: 0010: 3A76302E 305D0004 0410011B 28000000 +// CHECK-NEXT: 0020: 20000000 00000000 08000000 004110A8 +// CHECK-NEXT: 0030: 141190A8 1416E905 8002E907 119408E9 +// CHECK-NEXT: 0040: 0C204000 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_INFO_LINK +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: +// CHECK-NEXT: Info: +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x24 R_AMDGPU_REL32 .text +// CHECK-NEXT: ] +// CHECK: } diff --git a/llvm/test/MC/ELF/cfi-vector-register-mask.s b/llvm/test/MC/ELF/cfi-vector-register-mask.s new file mode 100644 index 0000000000000..e9dfa527a6bae --- /dev/null +++ b/llvm/test/MC/ELF/cfi-vector-register-mask.s @@ -0,0 +1,58 @@ +// RUN: llvm-mc -triple amdgcn-amd-amdhsa %s | FileCheck %s --check-prefix=ASM +// RUN: llvm-mc -filetype=obj -triple amdgcn-amd-amdhsa %s | llvm-readobj -S --sr --sd - | FileCheck %s + +// REQUIRES: amdgpu-registered-target + +// ASM: s_nop 0 +// ASM-NEXT: .cfi_llvm_vector_register_mask 3072, 2600, 32, 17, 64 +// ASM-NEXT: s_nop 0 + +f: + .cfi_startproc + s_nop 0 + .cfi_llvm_vector_register_mask 3072, 2600, 32, 17, 64 + s_nop 0 + .cfi_endproc + +// CHECK: Section { +// CHECK: Index: +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 72 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 18000000 00000000 017A525B 6C6C766D +// CHECK-NEXT: 0010: 3A76302E 305D0004 0410011B 28000000 +// CHECK-NEXT: 0020: 20000000 00000000 08000000 00411080 +// CHECK-NEXT: 0030: 180F9080 1890A814 E9071194 08E90C20 +// CHECK-NEXT: 0040: 40000000 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_INFO_LINK +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: +// CHECK-NEXT: Info: +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x24 R_AMDGPU_REL32 .text +// CHECK-NEXT: ] +// CHECK: } diff --git a/llvm/test/MC/ELF/cfi-vector-registers.s b/llvm/test/MC/ELF/cfi-vector-registers.s new file mode 100644 index 0000000000000..a45947bb71636 --- /dev/null +++ b/llvm/test/MC/ELF/cfi-vector-registers.s @@ -0,0 +1,56 @@ +# RUN: llvm-mc -triple amdgcn-amd-amdhsa %s | FileCheck %s --check-prefix=ASM +# RUN: llvm-mc -filetype=obj -triple amdgcn-amd-amdhsa -mcpu=gfx908 %s | llvm-readobj -S --sr --sd - | FileCheck %s + +# REQUIRES: amdgpu-registered-target + +# ASM: .cfi_llvm_vector_registers 16, 1663, 0, 32, 1663, 1, 32 +# ASM-NEXT: s_nop 0 + +f: + .cfi_startproc + s_nop 0 + .cfi_llvm_vector_registers 16, 1663, 0, 32, 1663, 1, 32 + s_nop 0 + .cfi_endproc + +// CHECK: Section { +// CHECK: Index: +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 64 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 18000000 00000000 017A525B 6C6C766D +// CHECK-NEXT: 0010: 3A76302E 305D0004 0410011B 20000000 +// CHECK-NEXT: 0020: 20000000 00000000 08000000 00411010 +// CHECK-NEXT: 0030: 0C90FF0C 9D200090 FF0C9D20 20000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_INFO_LINK +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: +// CHECK-NEXT: Info: +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x24 R_AMDGPU_REL32 .text +// CHECK-NEXT: ] +// CHECK: } diff --git a/llvm/test/MC/ELF/data-section-prefix.ll b/llvm/test/MC/ELF/data-section-prefix.ll index ca147035b419a..004422147a125 100644 --- a/llvm/test/MC/ELF/data-section-prefix.ll +++ b/llvm/test/MC/ELF/data-section-prefix.ll @@ -1,7 +1,7 @@ ; REQUIRES: bpf-registered-target ; RUN: llc -filetype obj -o - %s | llvm-readobj --sections - | FileCheck --check-prefix="SECTIONS" %s -; + ; SECTIONS: Name: .data.A ; SECTIONS-NEXT: Type: SHT_PROGBITS (0x1) ; SECTIONS-NEXT: Flags [ (0x3) diff --git a/llvm/test/MC/X86/avx-vnni-int16-32-att.s b/llvm/test/MC/X86/avx-vnni-int16-32-att.s deleted file mode 100644 index 63a082d213286..0000000000000 --- a/llvm/test/MC/X86/avx-vnni-int16-32-att.s +++ /dev/null @@ -1,338 +0,0 @@ -// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s - -// CHECK: vpdpwsud %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0xd4] - vpdpwsud %ymm4, %ymm3, %ymm2 - -// CHECK: vpdpwsud %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0xd4] - vpdpwsud %xmm4, %xmm3, %xmm2 - -// CHECK: vpdpwsud 268435456(%esp,%esi,8), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwsud 268435456(%esp,%esi,8), %ymm3, %ymm2 - -// CHECK: vpdpwsud 291(%edi,%eax,4), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwsud 291(%edi,%eax,4), %ymm3, %ymm2 - -// CHECK: vpdpwsud (%eax), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x10] - vpdpwsud (%eax), %ymm3, %ymm2 - -// CHECK: vpdpwsud -1024(,%ebp,2), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwsud -1024(,%ebp,2), %ymm3, %ymm2 - -// CHECK: vpdpwsud 4064(%ecx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x91,0xe0,0x0f,0x00,0x00] - vpdpwsud 4064(%ecx), %ymm3, %ymm2 - -// CHECK: vpdpwsud -4096(%edx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x92,0x00,0xf0,0xff,0xff] - vpdpwsud -4096(%edx), %ymm3, %ymm2 - -// CHECK: vpdpwsud 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwsud 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vpdpwsud 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwsud 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vpdpwsud (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x10] - vpdpwsud (%eax), %xmm3, %xmm2 - -// CHECK: vpdpwsud -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwsud -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vpdpwsud 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x91,0xf0,0x07,0x00,0x00] - vpdpwsud 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vpdpwsud -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x92,0x00,0xf8,0xff,0xff] - vpdpwsud -2048(%edx), %xmm3, %xmm2 - -// CHECK: vpdpwsuds %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0xd4] - vpdpwsuds %ymm4, %ymm3, %ymm2 - -// CHECK: vpdpwsuds %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0xd4] - vpdpwsuds %xmm4, %xmm3, %xmm2 - -// CHECK: vpdpwsuds 268435456(%esp,%esi,8), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwsuds 268435456(%esp,%esi,8), %ymm3, %ymm2 - -// CHECK: vpdpwsuds 291(%edi,%eax,4), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwsuds 291(%edi,%eax,4), %ymm3, %ymm2 - -// CHECK: vpdpwsuds (%eax), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x10] - vpdpwsuds (%eax), %ymm3, %ymm2 - -// CHECK: vpdpwsuds -1024(,%ebp,2), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwsuds -1024(,%ebp,2), %ymm3, %ymm2 - -// CHECK: vpdpwsuds 4064(%ecx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x91,0xe0,0x0f,0x00,0x00] - vpdpwsuds 4064(%ecx), %ymm3, %ymm2 - -// CHECK: vpdpwsuds -4096(%edx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x92,0x00,0xf0,0xff,0xff] - vpdpwsuds -4096(%edx), %ymm3, %ymm2 - -// CHECK: vpdpwsuds 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwsuds 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vpdpwsuds 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwsuds 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vpdpwsuds (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x10] - vpdpwsuds (%eax), %xmm3, %xmm2 - -// CHECK: vpdpwsuds -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwsuds -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vpdpwsuds 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x91,0xf0,0x07,0x00,0x00] - vpdpwsuds 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vpdpwsuds -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x92,0x00,0xf8,0xff,0xff] - vpdpwsuds -2048(%edx), %xmm3, %xmm2 - -// CHECK: vpdpwusd %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0xd4] - vpdpwusd %ymm4, %ymm3, %ymm2 - -// CHECK: vpdpwusd %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0xd4] - vpdpwusd %xmm4, %xmm3, %xmm2 - -// CHECK: vpdpwusd 268435456(%esp,%esi,8), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwusd 268435456(%esp,%esi,8), %ymm3, %ymm2 - -// CHECK: vpdpwusd 291(%edi,%eax,4), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwusd 291(%edi,%eax,4), %ymm3, %ymm2 - -// CHECK: vpdpwusd (%eax), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x10] - vpdpwusd (%eax), %ymm3, %ymm2 - -// CHECK: vpdpwusd -1024(,%ebp,2), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwusd -1024(,%ebp,2), %ymm3, %ymm2 - -// CHECK: vpdpwusd 4064(%ecx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x91,0xe0,0x0f,0x00,0x00] - vpdpwusd 4064(%ecx), %ymm3, %ymm2 - -// CHECK: vpdpwusd -4096(%edx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x92,0x00,0xf0,0xff,0xff] - vpdpwusd -4096(%edx), %ymm3, %ymm2 - -// CHECK: vpdpwusd 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwusd 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vpdpwusd 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwusd 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vpdpwusd (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x10] - vpdpwusd (%eax), %xmm3, %xmm2 - -// CHECK: vpdpwusd -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwusd -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vpdpwusd 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x91,0xf0,0x07,0x00,0x00] - vpdpwusd 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vpdpwusd -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x92,0x00,0xf8,0xff,0xff] - vpdpwusd -2048(%edx), %xmm3, %xmm2 - -// CHECK: vpdpwusds %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0xd4] - vpdpwusds %ymm4, %ymm3, %ymm2 - -// CHECK: vpdpwusds %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0xd4] - vpdpwusds %xmm4, %xmm3, %xmm2 - -// CHECK: vpdpwusds 268435456(%esp,%esi,8), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwusds 268435456(%esp,%esi,8), %ymm3, %ymm2 - -// CHECK: vpdpwusds 291(%edi,%eax,4), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwusds 291(%edi,%eax,4), %ymm3, %ymm2 - -// CHECK: vpdpwusds (%eax), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x10] - vpdpwusds (%eax), %ymm3, %ymm2 - -// CHECK: vpdpwusds -1024(,%ebp,2), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwusds -1024(,%ebp,2), %ymm3, %ymm2 - -// CHECK: vpdpwusds 4064(%ecx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x91,0xe0,0x0f,0x00,0x00] - vpdpwusds 4064(%ecx), %ymm3, %ymm2 - -// CHECK: vpdpwusds -4096(%edx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x92,0x00,0xf0,0xff,0xff] - vpdpwusds -4096(%edx), %ymm3, %ymm2 - -// CHECK: vpdpwusds 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwusds 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vpdpwusds 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwusds 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vpdpwusds (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x10] - vpdpwusds (%eax), %xmm3, %xmm2 - -// CHECK: vpdpwusds -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwusds -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vpdpwusds 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x91,0xf0,0x07,0x00,0x00] - vpdpwusds 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vpdpwusds -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x92,0x00,0xf8,0xff,0xff] - vpdpwusds -2048(%edx), %xmm3, %xmm2 - -// CHECK: vpdpwuud %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0xd4] - vpdpwuud %ymm4, %ymm3, %ymm2 - -// CHECK: vpdpwuud %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0xd4] - vpdpwuud %xmm4, %xmm3, %xmm2 - -// CHECK: vpdpwuud 268435456(%esp,%esi,8), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwuud 268435456(%esp,%esi,8), %ymm3, %ymm2 - -// CHECK: vpdpwuud 291(%edi,%eax,4), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwuud 291(%edi,%eax,4), %ymm3, %ymm2 - -// CHECK: vpdpwuud (%eax), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x10] - vpdpwuud (%eax), %ymm3, %ymm2 - -// CHECK: vpdpwuud -1024(,%ebp,2), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwuud -1024(,%ebp,2), %ymm3, %ymm2 - -// CHECK: vpdpwuud 4064(%ecx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x91,0xe0,0x0f,0x00,0x00] - vpdpwuud 4064(%ecx), %ymm3, %ymm2 - -// CHECK: vpdpwuud -4096(%edx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x92,0x00,0xf0,0xff,0xff] - vpdpwuud -4096(%edx), %ymm3, %ymm2 - -// CHECK: vpdpwuud 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwuud 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vpdpwuud 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwuud 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vpdpwuud (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x10] - vpdpwuud (%eax), %xmm3, %xmm2 - -// CHECK: vpdpwuud -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwuud -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vpdpwuud 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x91,0xf0,0x07,0x00,0x00] - vpdpwuud 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vpdpwuud -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x92,0x00,0xf8,0xff,0xff] - vpdpwuud -2048(%edx), %xmm3, %xmm2 - -// CHECK: vpdpwuuds %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0xd4] - vpdpwuuds %ymm4, %ymm3, %ymm2 - -// CHECK: vpdpwuuds %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0xd4] - vpdpwuuds %xmm4, %xmm3, %xmm2 - -// CHECK: vpdpwuuds 268435456(%esp,%esi,8), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwuuds 268435456(%esp,%esi,8), %ymm3, %ymm2 - -// CHECK: vpdpwuuds 291(%edi,%eax,4), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwuuds 291(%edi,%eax,4), %ymm3, %ymm2 - -// CHECK: vpdpwuuds (%eax), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x10] - vpdpwuuds (%eax), %ymm3, %ymm2 - -// CHECK: vpdpwuuds -1024(,%ebp,2), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwuuds -1024(,%ebp,2), %ymm3, %ymm2 - -// CHECK: vpdpwuuds 4064(%ecx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x91,0xe0,0x0f,0x00,0x00] - vpdpwuuds 4064(%ecx), %ymm3, %ymm2 - -// CHECK: vpdpwuuds -4096(%edx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x92,0x00,0xf0,0xff,0xff] - vpdpwuuds -4096(%edx), %ymm3, %ymm2 - -// CHECK: vpdpwuuds 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwuuds 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vpdpwuuds 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwuuds 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vpdpwuuds (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x10] - vpdpwuuds (%eax), %xmm3, %xmm2 - -// CHECK: vpdpwuuds -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwuuds -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vpdpwuuds 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x91,0xf0,0x07,0x00,0x00] - vpdpwuuds 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vpdpwuuds -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x92,0x00,0xf8,0xff,0xff] - vpdpwuuds -2048(%edx), %xmm3, %xmm2 - diff --git a/llvm/test/MC/X86/avx-vnni-int16-32-intel.s b/llvm/test/MC/X86/avx-vnni-int16-32-intel.s deleted file mode 100644 index 9a4b163c391f3..0000000000000 --- a/llvm/test/MC/X86/avx-vnni-int16-32-intel.s +++ /dev/null @@ -1,338 +0,0 @@ -// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vpdpwsud ymm2, ymm3, ymm4 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0xd4] - vpdpwsud ymm2, ymm3, ymm4 - -// CHECK: vpdpwsud xmm2, xmm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0xd4] - vpdpwsud xmm2, xmm3, xmm4 - -// CHECK: vpdpwsud ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwsud ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwsud ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwsud ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwsud ymm2, ymm3, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x10] - vpdpwsud ymm2, ymm3, ymmword ptr [eax] - -// CHECK: vpdpwsud ymm2, ymm3, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwsud ymm2, ymm3, ymmword ptr [2*ebp - 1024] - -// CHECK: vpdpwsud ymm2, ymm3, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x91,0xe0,0x0f,0x00,0x00] - vpdpwsud ymm2, ymm3, ymmword ptr [ecx + 4064] - -// CHECK: vpdpwsud ymm2, ymm3, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd2,0x92,0x00,0xf0,0xff,0xff] - vpdpwsud ymm2, ymm3, ymmword ptr [edx - 4096] - -// CHECK: vpdpwsud xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwsud xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwsud xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwsud xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwsud xmm2, xmm3, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x10] - vpdpwsud xmm2, xmm3, xmmword ptr [eax] - -// CHECK: vpdpwsud xmm2, xmm3, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwsud xmm2, xmm3, xmmword ptr [2*ebp - 512] - -// CHECK: vpdpwsud xmm2, xmm3, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x91,0xf0,0x07,0x00,0x00] - vpdpwsud xmm2, xmm3, xmmword ptr [ecx + 2032] - -// CHECK: vpdpwsud xmm2, xmm3, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd2,0x92,0x00,0xf8,0xff,0xff] - vpdpwsud xmm2, xmm3, xmmword ptr [edx - 2048] - -// CHECK: vpdpwsuds ymm2, ymm3, ymm4 -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0xd4] - vpdpwsuds ymm2, ymm3, ymm4 - -// CHECK: vpdpwsuds xmm2, xmm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0xd4] - vpdpwsuds xmm2, xmm3, xmm4 - -// CHECK: vpdpwsuds ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwsuds ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwsuds ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwsuds ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwsuds ymm2, ymm3, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x10] - vpdpwsuds ymm2, ymm3, ymmword ptr [eax] - -// CHECK: vpdpwsuds ymm2, ymm3, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwsuds ymm2, ymm3, ymmword ptr [2*ebp - 1024] - -// CHECK: vpdpwsuds ymm2, ymm3, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x91,0xe0,0x0f,0x00,0x00] - vpdpwsuds ymm2, ymm3, ymmword ptr [ecx + 4064] - -// CHECK: vpdpwsuds ymm2, ymm3, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x66,0xd3,0x92,0x00,0xf0,0xff,0xff] - vpdpwsuds ymm2, ymm3, ymmword ptr [edx - 4096] - -// CHECK: vpdpwsuds xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwsuds xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwsuds xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwsuds xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwsuds xmm2, xmm3, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x10] - vpdpwsuds xmm2, xmm3, xmmword ptr [eax] - -// CHECK: vpdpwsuds xmm2, xmm3, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwsuds xmm2, xmm3, xmmword ptr [2*ebp - 512] - -// CHECK: vpdpwsuds xmm2, xmm3, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x91,0xf0,0x07,0x00,0x00] - vpdpwsuds xmm2, xmm3, xmmword ptr [ecx + 2032] - -// CHECK: vpdpwsuds xmm2, xmm3, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x62,0xd3,0x92,0x00,0xf8,0xff,0xff] - vpdpwsuds xmm2, xmm3, xmmword ptr [edx - 2048] - -// CHECK: vpdpwusd ymm2, ymm3, ymm4 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0xd4] - vpdpwusd ymm2, ymm3, ymm4 - -// CHECK: vpdpwusd xmm2, xmm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0xd4] - vpdpwusd xmm2, xmm3, xmm4 - -// CHECK: vpdpwusd ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwusd ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwusd ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwusd ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwusd ymm2, ymm3, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x10] - vpdpwusd ymm2, ymm3, ymmword ptr [eax] - -// CHECK: vpdpwusd ymm2, ymm3, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwusd ymm2, ymm3, ymmword ptr [2*ebp - 1024] - -// CHECK: vpdpwusd ymm2, ymm3, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x91,0xe0,0x0f,0x00,0x00] - vpdpwusd ymm2, ymm3, ymmword ptr [ecx + 4064] - -// CHECK: vpdpwusd ymm2, ymm3, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd2,0x92,0x00,0xf0,0xff,0xff] - vpdpwusd ymm2, ymm3, ymmword ptr [edx - 4096] - -// CHECK: vpdpwusd xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwusd xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwusd xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwusd xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwusd xmm2, xmm3, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x10] - vpdpwusd xmm2, xmm3, xmmword ptr [eax] - -// CHECK: vpdpwusd xmm2, xmm3, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwusd xmm2, xmm3, xmmword ptr [2*ebp - 512] - -// CHECK: vpdpwusd xmm2, xmm3, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x91,0xf0,0x07,0x00,0x00] - vpdpwusd xmm2, xmm3, xmmword ptr [ecx + 2032] - -// CHECK: vpdpwusd xmm2, xmm3, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd2,0x92,0x00,0xf8,0xff,0xff] - vpdpwusd xmm2, xmm3, xmmword ptr [edx - 2048] - -// CHECK: vpdpwusds ymm2, ymm3, ymm4 -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0xd4] - vpdpwusds ymm2, ymm3, ymm4 - -// CHECK: vpdpwusds xmm2, xmm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0xd4] - vpdpwusds xmm2, xmm3, xmm4 - -// CHECK: vpdpwusds ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwusds ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwusds ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwusds ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwusds ymm2, ymm3, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x10] - vpdpwusds ymm2, ymm3, ymmword ptr [eax] - -// CHECK: vpdpwusds ymm2, ymm3, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwusds ymm2, ymm3, ymmword ptr [2*ebp - 1024] - -// CHECK: vpdpwusds ymm2, ymm3, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x91,0xe0,0x0f,0x00,0x00] - vpdpwusds ymm2, ymm3, ymmword ptr [ecx + 4064] - -// CHECK: vpdpwusds ymm2, ymm3, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x65,0xd3,0x92,0x00,0xf0,0xff,0xff] - vpdpwusds ymm2, ymm3, ymmword ptr [edx - 4096] - -// CHECK: vpdpwusds xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwusds xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwusds xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwusds xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwusds xmm2, xmm3, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x10] - vpdpwusds xmm2, xmm3, xmmword ptr [eax] - -// CHECK: vpdpwusds xmm2, xmm3, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwusds xmm2, xmm3, xmmword ptr [2*ebp - 512] - -// CHECK: vpdpwusds xmm2, xmm3, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x91,0xf0,0x07,0x00,0x00] - vpdpwusds xmm2, xmm3, xmmword ptr [ecx + 2032] - -// CHECK: vpdpwusds xmm2, xmm3, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x61,0xd3,0x92,0x00,0xf8,0xff,0xff] - vpdpwusds xmm2, xmm3, xmmword ptr [edx - 2048] - -// CHECK: vpdpwuud ymm2, ymm3, ymm4 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0xd4] - vpdpwuud ymm2, ymm3, ymm4 - -// CHECK: vpdpwuud xmm2, xmm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0xd4] - vpdpwuud xmm2, xmm3, xmm4 - -// CHECK: vpdpwuud ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwuud ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwuud ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwuud ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwuud ymm2, ymm3, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x10] - vpdpwuud ymm2, ymm3, ymmword ptr [eax] - -// CHECK: vpdpwuud ymm2, ymm3, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwuud ymm2, ymm3, ymmword ptr [2*ebp - 1024] - -// CHECK: vpdpwuud ymm2, ymm3, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x91,0xe0,0x0f,0x00,0x00] - vpdpwuud ymm2, ymm3, ymmword ptr [ecx + 4064] - -// CHECK: vpdpwuud ymm2, ymm3, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd2,0x92,0x00,0xf0,0xff,0xff] - vpdpwuud ymm2, ymm3, ymmword ptr [edx - 4096] - -// CHECK: vpdpwuud xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwuud xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwuud xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwuud xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwuud xmm2, xmm3, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x10] - vpdpwuud xmm2, xmm3, xmmword ptr [eax] - -// CHECK: vpdpwuud xmm2, xmm3, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwuud xmm2, xmm3, xmmword ptr [2*ebp - 512] - -// CHECK: vpdpwuud xmm2, xmm3, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x91,0xf0,0x07,0x00,0x00] - vpdpwuud xmm2, xmm3, xmmword ptr [ecx + 2032] - -// CHECK: vpdpwuud xmm2, xmm3, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd2,0x92,0x00,0xf8,0xff,0xff] - vpdpwuud xmm2, xmm3, xmmword ptr [edx - 2048] - -// CHECK: vpdpwuuds ymm2, ymm3, ymm4 -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0xd4] - vpdpwuuds ymm2, ymm3, ymm4 - -// CHECK: vpdpwuuds xmm2, xmm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0xd4] - vpdpwuuds xmm2, xmm3, xmm4 - -// CHECK: vpdpwuuds ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwuuds ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwuuds ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwuuds ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwuuds ymm2, ymm3, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x10] - vpdpwuuds ymm2, ymm3, ymmword ptr [eax] - -// CHECK: vpdpwuuds ymm2, ymm3, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x14,0x6d,0x00,0xfc,0xff,0xff] - vpdpwuuds ymm2, ymm3, ymmword ptr [2*ebp - 1024] - -// CHECK: vpdpwuuds ymm2, ymm3, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x91,0xe0,0x0f,0x00,0x00] - vpdpwuuds ymm2, ymm3, ymmword ptr [ecx + 4064] - -// CHECK: vpdpwuuds ymm2, ymm3, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x64,0xd3,0x92,0x00,0xf0,0xff,0xff] - vpdpwuuds ymm2, ymm3, ymmword ptr [edx - 4096] - -// CHECK: vpdpwuuds xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x94,0xf4,0x00,0x00,0x00,0x10] - vpdpwuuds xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vpdpwuuds xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x94,0x87,0x23,0x01,0x00,0x00] - vpdpwuuds xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vpdpwuuds xmm2, xmm3, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x10] - vpdpwuuds xmm2, xmm3, xmmword ptr [eax] - -// CHECK: vpdpwuuds xmm2, xmm3, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x14,0x6d,0x00,0xfe,0xff,0xff] - vpdpwuuds xmm2, xmm3, xmmword ptr [2*ebp - 512] - -// CHECK: vpdpwuuds xmm2, xmm3, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x91,0xf0,0x07,0x00,0x00] - vpdpwuuds xmm2, xmm3, xmmword ptr [ecx + 2032] - -// CHECK: vpdpwuuds xmm2, xmm3, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x60,0xd3,0x92,0x00,0xf8,0xff,0xff] - vpdpwuuds xmm2, xmm3, xmmword ptr [edx - 2048] - diff --git a/llvm/test/MC/X86/avx-vnni-int16-64-att.s b/llvm/test/MC/X86/avx-vnni-int16-64-att.s deleted file mode 100644 index 4616f0a5d5883..0000000000000 --- a/llvm/test/MC/X86/avx-vnni-int16-64-att.s +++ /dev/null @@ -1,338 +0,0 @@ -// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s - -// CHECK: vpdpwsud %ymm4, %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xd2,0xe4] - vpdpwsud %ymm4, %ymm13, %ymm12 - -// CHECK: vpdpwsud %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xd2,0xe4] - vpdpwsud %xmm4, %xmm13, %xmm12 - -// CHECK: vpdpwsud 268435456(%rbp,%r14,8), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x22,0x16,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwsud 268435456(%rbp,%r14,8), %ymm13, %ymm12 - -// CHECK: vpdpwsud 291(%r8,%rax,4), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x42,0x16,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwsud 291(%r8,%rax,4), %ymm13, %ymm12 - -// CHECK: vpdpwsud (%rip), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwsud (%rip), %ymm13, %ymm12 - -// CHECK: vpdpwsud -1024(,%rbp,2), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xd2,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwsud -1024(,%rbp,2), %ymm13, %ymm12 - -// CHECK: vpdpwsud 4064(%rcx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xd2,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwsud 4064(%rcx), %ymm13, %ymm12 - -// CHECK: vpdpwsud -4096(%rdx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xd2,0xa2,0x00,0xf0,0xff,0xff] - vpdpwsud -4096(%rdx), %ymm13, %ymm12 - -// CHECK: vpdpwsud 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x22,0x12,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwsud 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vpdpwsud 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x42,0x12,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwsud 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vpdpwsud (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwsud (%rip), %xmm13, %xmm12 - -// CHECK: vpdpwsud -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xd2,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwsud -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vpdpwsud 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xd2,0xa1,0xf0,0x07,0x00,0x00] - vpdpwsud 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vpdpwsud -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xd2,0xa2,0x00,0xf8,0xff,0xff] - vpdpwsud -2048(%rdx), %xmm13, %xmm12 - -// CHECK: vpdpwsuds %ymm4, %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xd3,0xe4] - vpdpwsuds %ymm4, %ymm13, %ymm12 - -// CHECK: vpdpwsuds %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xd3,0xe4] - vpdpwsuds %xmm4, %xmm13, %xmm12 - -// CHECK: vpdpwsuds 268435456(%rbp,%r14,8), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x22,0x16,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwsuds 268435456(%rbp,%r14,8), %ymm13, %ymm12 - -// CHECK: vpdpwsuds 291(%r8,%rax,4), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x42,0x16,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwsuds 291(%r8,%rax,4), %ymm13, %ymm12 - -// CHECK: vpdpwsuds (%rip), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwsuds (%rip), %ymm13, %ymm12 - -// CHECK: vpdpwsuds -1024(,%rbp,2), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xd3,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwsuds -1024(,%rbp,2), %ymm13, %ymm12 - -// CHECK: vpdpwsuds 4064(%rcx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xd3,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwsuds 4064(%rcx), %ymm13, %ymm12 - -// CHECK: vpdpwsuds -4096(%rdx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xd3,0xa2,0x00,0xf0,0xff,0xff] - vpdpwsuds -4096(%rdx), %ymm13, %ymm12 - -// CHECK: vpdpwsuds 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x22,0x12,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwsuds 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vpdpwsuds 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x42,0x12,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwsuds 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vpdpwsuds (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwsuds (%rip), %xmm13, %xmm12 - -// CHECK: vpdpwsuds -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xd3,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwsuds -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vpdpwsuds 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xd3,0xa1,0xf0,0x07,0x00,0x00] - vpdpwsuds 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vpdpwsuds -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xd3,0xa2,0x00,0xf8,0xff,0xff] - vpdpwsuds -2048(%rdx), %xmm13, %xmm12 - -// CHECK: vpdpwusd %ymm4, %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x15,0xd2,0xe4] - vpdpwusd %ymm4, %ymm13, %ymm12 - -// CHECK: vpdpwusd %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xd2,0xe4] - vpdpwusd %xmm4, %xmm13, %xmm12 - -// CHECK: vpdpwusd 268435456(%rbp,%r14,8), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x22,0x15,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwusd 268435456(%rbp,%r14,8), %ymm13, %ymm12 - -// CHECK: vpdpwusd 291(%r8,%rax,4), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x42,0x15,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwusd 291(%r8,%rax,4), %ymm13, %ymm12 - -// CHECK: vpdpwusd (%rip), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x15,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwusd (%rip), %ymm13, %ymm12 - -// CHECK: vpdpwusd -1024(,%rbp,2), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x15,0xd2,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwusd -1024(,%rbp,2), %ymm13, %ymm12 - -// CHECK: vpdpwusd 4064(%rcx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x15,0xd2,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwusd 4064(%rcx), %ymm13, %ymm12 - -// CHECK: vpdpwusd -4096(%rdx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x15,0xd2,0xa2,0x00,0xf0,0xff,0xff] - vpdpwusd -4096(%rdx), %ymm13, %ymm12 - -// CHECK: vpdpwusd 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x22,0x11,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwusd 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vpdpwusd 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x42,0x11,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwusd 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vpdpwusd (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwusd (%rip), %xmm13, %xmm12 - -// CHECK: vpdpwusd -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xd2,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwusd -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vpdpwusd 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xd2,0xa1,0xf0,0x07,0x00,0x00] - vpdpwusd 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vpdpwusd -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xd2,0xa2,0x00,0xf8,0xff,0xff] - vpdpwusd -2048(%rdx), %xmm13, %xmm12 - -// CHECK: vpdpwusds %ymm4, %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x15,0xd3,0xe4] - vpdpwusds %ymm4, %ymm13, %ymm12 - -// CHECK: vpdpwusds %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xd3,0xe4] - vpdpwusds %xmm4, %xmm13, %xmm12 - -// CHECK: vpdpwusds 268435456(%rbp,%r14,8), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x22,0x15,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwusds 268435456(%rbp,%r14,8), %ymm13, %ymm12 - -// CHECK: vpdpwusds 291(%r8,%rax,4), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x42,0x15,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwusds 291(%r8,%rax,4), %ymm13, %ymm12 - -// CHECK: vpdpwusds (%rip), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x15,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwusds (%rip), %ymm13, %ymm12 - -// CHECK: vpdpwusds -1024(,%rbp,2), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x15,0xd3,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwusds -1024(,%rbp,2), %ymm13, %ymm12 - -// CHECK: vpdpwusds 4064(%rcx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x15,0xd3,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwusds 4064(%rcx), %ymm13, %ymm12 - -// CHECK: vpdpwusds -4096(%rdx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x15,0xd3,0xa2,0x00,0xf0,0xff,0xff] - vpdpwusds -4096(%rdx), %ymm13, %ymm12 - -// CHECK: vpdpwusds 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x22,0x11,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwusds 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vpdpwusds 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x42,0x11,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwusds 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vpdpwusds (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwusds (%rip), %xmm13, %xmm12 - -// CHECK: vpdpwusds -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xd3,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwusds -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vpdpwusds 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xd3,0xa1,0xf0,0x07,0x00,0x00] - vpdpwusds 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vpdpwusds -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xd3,0xa2,0x00,0xf8,0xff,0xff] - vpdpwusds -2048(%rdx), %xmm13, %xmm12 - -// CHECK: vpdpwuud %ymm4, %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x14,0xd2,0xe4] - vpdpwuud %ymm4, %ymm13, %ymm12 - -// CHECK: vpdpwuud %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xd2,0xe4] - vpdpwuud %xmm4, %xmm13, %xmm12 - -// CHECK: vpdpwuud 268435456(%rbp,%r14,8), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x22,0x14,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwuud 268435456(%rbp,%r14,8), %ymm13, %ymm12 - -// CHECK: vpdpwuud 291(%r8,%rax,4), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x42,0x14,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwuud 291(%r8,%rax,4), %ymm13, %ymm12 - -// CHECK: vpdpwuud (%rip), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x14,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwuud (%rip), %ymm13, %ymm12 - -// CHECK: vpdpwuud -1024(,%rbp,2), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x14,0xd2,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwuud -1024(,%rbp,2), %ymm13, %ymm12 - -// CHECK: vpdpwuud 4064(%rcx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x14,0xd2,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwuud 4064(%rcx), %ymm13, %ymm12 - -// CHECK: vpdpwuud -4096(%rdx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x14,0xd2,0xa2,0x00,0xf0,0xff,0xff] - vpdpwuud -4096(%rdx), %ymm13, %ymm12 - -// CHECK: vpdpwuud 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x22,0x10,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwuud 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vpdpwuud 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x42,0x10,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwuud 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vpdpwuud (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwuud (%rip), %xmm13, %xmm12 - -// CHECK: vpdpwuud -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xd2,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwuud -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vpdpwuud 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xd2,0xa1,0xf0,0x07,0x00,0x00] - vpdpwuud 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vpdpwuud -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xd2,0xa2,0x00,0xf8,0xff,0xff] - vpdpwuud -2048(%rdx), %xmm13, %xmm12 - -// CHECK: vpdpwuuds %ymm4, %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x14,0xd3,0xe4] - vpdpwuuds %ymm4, %ymm13, %ymm12 - -// CHECK: vpdpwuuds %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xd3,0xe4] - vpdpwuuds %xmm4, %xmm13, %xmm12 - -// CHECK: vpdpwuuds 268435456(%rbp,%r14,8), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x22,0x14,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwuuds 268435456(%rbp,%r14,8), %ymm13, %ymm12 - -// CHECK: vpdpwuuds 291(%r8,%rax,4), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x42,0x14,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwuuds 291(%r8,%rax,4), %ymm13, %ymm12 - -// CHECK: vpdpwuuds (%rip), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x14,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwuuds (%rip), %ymm13, %ymm12 - -// CHECK: vpdpwuuds -1024(,%rbp,2), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x14,0xd3,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwuuds -1024(,%rbp,2), %ymm13, %ymm12 - -// CHECK: vpdpwuuds 4064(%rcx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x14,0xd3,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwuuds 4064(%rcx), %ymm13, %ymm12 - -// CHECK: vpdpwuuds -4096(%rdx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x14,0xd3,0xa2,0x00,0xf0,0xff,0xff] - vpdpwuuds -4096(%rdx), %ymm13, %ymm12 - -// CHECK: vpdpwuuds 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x22,0x10,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwuuds 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vpdpwuuds 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x42,0x10,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwuuds 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vpdpwuuds (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwuuds (%rip), %xmm13, %xmm12 - -// CHECK: vpdpwuuds -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xd3,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwuuds -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vpdpwuuds 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xd3,0xa1,0xf0,0x07,0x00,0x00] - vpdpwuuds 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vpdpwuuds -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xd3,0xa2,0x00,0xf8,0xff,0xff] - vpdpwuuds -2048(%rdx), %xmm13, %xmm12 - diff --git a/llvm/test/MC/X86/avx-vnni-int16-64-intel.s b/llvm/test/MC/X86/avx-vnni-int16-64-intel.s deleted file mode 100644 index a83a55d937b7d..0000000000000 --- a/llvm/test/MC/X86/avx-vnni-int16-64-intel.s +++ /dev/null @@ -1,338 +0,0 @@ -// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vpdpwsud ymm12, ymm13, ymm4 -// CHECK: encoding: [0xc4,0x62,0x16,0xd2,0xe4] - vpdpwsud ymm12, ymm13, ymm4 - -// CHECK: vpdpwsud xmm12, xmm13, xmm4 -// CHECK: encoding: [0xc4,0x62,0x12,0xd2,0xe4] - vpdpwsud xmm12, xmm13, xmm4 - -// CHECK: vpdpwsud ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x16,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwsud ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwsud ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x16,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwsud ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwsud ymm12, ymm13, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x16,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwsud ymm12, ymm13, ymmword ptr [rip] - -// CHECK: vpdpwsud ymm12, ymm13, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0x62,0x16,0xd2,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwsud ymm12, ymm13, ymmword ptr [2*rbp - 1024] - -// CHECK: vpdpwsud ymm12, ymm13, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0x62,0x16,0xd2,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwsud ymm12, ymm13, ymmword ptr [rcx + 4064] - -// CHECK: vpdpwsud ymm12, ymm13, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0x62,0x16,0xd2,0xa2,0x00,0xf0,0xff,0xff] - vpdpwsud ymm12, ymm13, ymmword ptr [rdx - 4096] - -// CHECK: vpdpwsud xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x12,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwsud xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwsud xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x12,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwsud xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwsud xmm12, xmm13, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x12,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwsud xmm12, xmm13, xmmword ptr [rip] - -// CHECK: vpdpwsud xmm12, xmm13, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0x62,0x12,0xd2,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwsud xmm12, xmm13, xmmword ptr [2*rbp - 512] - -// CHECK: vpdpwsud xmm12, xmm13, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0x62,0x12,0xd2,0xa1,0xf0,0x07,0x00,0x00] - vpdpwsud xmm12, xmm13, xmmword ptr [rcx + 2032] - -// CHECK: vpdpwsud xmm12, xmm13, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0x62,0x12,0xd2,0xa2,0x00,0xf8,0xff,0xff] - vpdpwsud xmm12, xmm13, xmmword ptr [rdx - 2048] - -// CHECK: vpdpwsuds ymm12, ymm13, ymm4 -// CHECK: encoding: [0xc4,0x62,0x16,0xd3,0xe4] - vpdpwsuds ymm12, ymm13, ymm4 - -// CHECK: vpdpwsuds xmm12, xmm13, xmm4 -// CHECK: encoding: [0xc4,0x62,0x12,0xd3,0xe4] - vpdpwsuds xmm12, xmm13, xmm4 - -// CHECK: vpdpwsuds ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x16,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwsuds ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwsuds ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x16,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwsuds ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwsuds ymm12, ymm13, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x16,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwsuds ymm12, ymm13, ymmword ptr [rip] - -// CHECK: vpdpwsuds ymm12, ymm13, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0x62,0x16,0xd3,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwsuds ymm12, ymm13, ymmword ptr [2*rbp - 1024] - -// CHECK: vpdpwsuds ymm12, ymm13, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0x62,0x16,0xd3,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwsuds ymm12, ymm13, ymmword ptr [rcx + 4064] - -// CHECK: vpdpwsuds ymm12, ymm13, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0x62,0x16,0xd3,0xa2,0x00,0xf0,0xff,0xff] - vpdpwsuds ymm12, ymm13, ymmword ptr [rdx - 4096] - -// CHECK: vpdpwsuds xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x12,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwsuds xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwsuds xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x12,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwsuds xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwsuds xmm12, xmm13, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x12,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwsuds xmm12, xmm13, xmmword ptr [rip] - -// CHECK: vpdpwsuds xmm12, xmm13, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0x62,0x12,0xd3,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwsuds xmm12, xmm13, xmmword ptr [2*rbp - 512] - -// CHECK: vpdpwsuds xmm12, xmm13, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0x62,0x12,0xd3,0xa1,0xf0,0x07,0x00,0x00] - vpdpwsuds xmm12, xmm13, xmmword ptr [rcx + 2032] - -// CHECK: vpdpwsuds xmm12, xmm13, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0x62,0x12,0xd3,0xa2,0x00,0xf8,0xff,0xff] - vpdpwsuds xmm12, xmm13, xmmword ptr [rdx - 2048] - -// CHECK: vpdpwusd ymm12, ymm13, ymm4 -// CHECK: encoding: [0xc4,0x62,0x15,0xd2,0xe4] - vpdpwusd ymm12, ymm13, ymm4 - -// CHECK: vpdpwusd xmm12, xmm13, xmm4 -// CHECK: encoding: [0xc4,0x62,0x11,0xd2,0xe4] - vpdpwusd xmm12, xmm13, xmm4 - -// CHECK: vpdpwusd ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x15,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwusd ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwusd ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x15,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwusd ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwusd ymm12, ymm13, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x15,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwusd ymm12, ymm13, ymmword ptr [rip] - -// CHECK: vpdpwusd ymm12, ymm13, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0x62,0x15,0xd2,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwusd ymm12, ymm13, ymmword ptr [2*rbp - 1024] - -// CHECK: vpdpwusd ymm12, ymm13, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0x62,0x15,0xd2,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwusd ymm12, ymm13, ymmword ptr [rcx + 4064] - -// CHECK: vpdpwusd ymm12, ymm13, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0x62,0x15,0xd2,0xa2,0x00,0xf0,0xff,0xff] - vpdpwusd ymm12, ymm13, ymmword ptr [rdx - 4096] - -// CHECK: vpdpwusd xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x11,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwusd xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwusd xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x11,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwusd xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwusd xmm12, xmm13, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x11,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwusd xmm12, xmm13, xmmword ptr [rip] - -// CHECK: vpdpwusd xmm12, xmm13, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0x62,0x11,0xd2,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwusd xmm12, xmm13, xmmword ptr [2*rbp - 512] - -// CHECK: vpdpwusd xmm12, xmm13, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0x62,0x11,0xd2,0xa1,0xf0,0x07,0x00,0x00] - vpdpwusd xmm12, xmm13, xmmword ptr [rcx + 2032] - -// CHECK: vpdpwusd xmm12, xmm13, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0x62,0x11,0xd2,0xa2,0x00,0xf8,0xff,0xff] - vpdpwusd xmm12, xmm13, xmmword ptr [rdx - 2048] - -// CHECK: vpdpwusds ymm12, ymm13, ymm4 -// CHECK: encoding: [0xc4,0x62,0x15,0xd3,0xe4] - vpdpwusds ymm12, ymm13, ymm4 - -// CHECK: vpdpwusds xmm12, xmm13, xmm4 -// CHECK: encoding: [0xc4,0x62,0x11,0xd3,0xe4] - vpdpwusds xmm12, xmm13, xmm4 - -// CHECK: vpdpwusds ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x15,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwusds ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwusds ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x15,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwusds ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwusds ymm12, ymm13, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x15,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwusds ymm12, ymm13, ymmword ptr [rip] - -// CHECK: vpdpwusds ymm12, ymm13, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0x62,0x15,0xd3,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwusds ymm12, ymm13, ymmword ptr [2*rbp - 1024] - -// CHECK: vpdpwusds ymm12, ymm13, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0x62,0x15,0xd3,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwusds ymm12, ymm13, ymmword ptr [rcx + 4064] - -// CHECK: vpdpwusds ymm12, ymm13, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0x62,0x15,0xd3,0xa2,0x00,0xf0,0xff,0xff] - vpdpwusds ymm12, ymm13, ymmword ptr [rdx - 4096] - -// CHECK: vpdpwusds xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x11,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwusds xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwusds xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x11,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwusds xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwusds xmm12, xmm13, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x11,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwusds xmm12, xmm13, xmmword ptr [rip] - -// CHECK: vpdpwusds xmm12, xmm13, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0x62,0x11,0xd3,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwusds xmm12, xmm13, xmmword ptr [2*rbp - 512] - -// CHECK: vpdpwusds xmm12, xmm13, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0x62,0x11,0xd3,0xa1,0xf0,0x07,0x00,0x00] - vpdpwusds xmm12, xmm13, xmmword ptr [rcx + 2032] - -// CHECK: vpdpwusds xmm12, xmm13, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0x62,0x11,0xd3,0xa2,0x00,0xf8,0xff,0xff] - vpdpwusds xmm12, xmm13, xmmword ptr [rdx - 2048] - -// CHECK: vpdpwuud ymm12, ymm13, ymm4 -// CHECK: encoding: [0xc4,0x62,0x14,0xd2,0xe4] - vpdpwuud ymm12, ymm13, ymm4 - -// CHECK: vpdpwuud xmm12, xmm13, xmm4 -// CHECK: encoding: [0xc4,0x62,0x10,0xd2,0xe4] - vpdpwuud xmm12, xmm13, xmm4 - -// CHECK: vpdpwuud ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x14,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwuud ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwuud ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x14,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwuud ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwuud ymm12, ymm13, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x14,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwuud ymm12, ymm13, ymmword ptr [rip] - -// CHECK: vpdpwuud ymm12, ymm13, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0x62,0x14,0xd2,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwuud ymm12, ymm13, ymmword ptr [2*rbp - 1024] - -// CHECK: vpdpwuud ymm12, ymm13, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0x62,0x14,0xd2,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwuud ymm12, ymm13, ymmword ptr [rcx + 4064] - -// CHECK: vpdpwuud ymm12, ymm13, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0x62,0x14,0xd2,0xa2,0x00,0xf0,0xff,0xff] - vpdpwuud ymm12, ymm13, ymmword ptr [rdx - 4096] - -// CHECK: vpdpwuud xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x10,0xd2,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwuud xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwuud xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x10,0xd2,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwuud xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwuud xmm12, xmm13, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x10,0xd2,0x25,0x00,0x00,0x00,0x00] - vpdpwuud xmm12, xmm13, xmmword ptr [rip] - -// CHECK: vpdpwuud xmm12, xmm13, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0x62,0x10,0xd2,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwuud xmm12, xmm13, xmmword ptr [2*rbp - 512] - -// CHECK: vpdpwuud xmm12, xmm13, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0x62,0x10,0xd2,0xa1,0xf0,0x07,0x00,0x00] - vpdpwuud xmm12, xmm13, xmmword ptr [rcx + 2032] - -// CHECK: vpdpwuud xmm12, xmm13, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0x62,0x10,0xd2,0xa2,0x00,0xf8,0xff,0xff] - vpdpwuud xmm12, xmm13, xmmword ptr [rdx - 2048] - -// CHECK: vpdpwuuds ymm12, ymm13, ymm4 -// CHECK: encoding: [0xc4,0x62,0x14,0xd3,0xe4] - vpdpwuuds ymm12, ymm13, ymm4 - -// CHECK: vpdpwuuds xmm12, xmm13, xmm4 -// CHECK: encoding: [0xc4,0x62,0x10,0xd3,0xe4] - vpdpwuuds xmm12, xmm13, xmm4 - -// CHECK: vpdpwuuds ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x14,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwuuds ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwuuds ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x14,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwuuds ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwuuds ymm12, ymm13, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x14,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwuuds ymm12, ymm13, ymmword ptr [rip] - -// CHECK: vpdpwuuds ymm12, ymm13, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0x62,0x14,0xd3,0x24,0x6d,0x00,0xfc,0xff,0xff] - vpdpwuuds ymm12, ymm13, ymmword ptr [2*rbp - 1024] - -// CHECK: vpdpwuuds ymm12, ymm13, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0x62,0x14,0xd3,0xa1,0xe0,0x0f,0x00,0x00] - vpdpwuuds ymm12, ymm13, ymmword ptr [rcx + 4064] - -// CHECK: vpdpwuuds ymm12, ymm13, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0x62,0x14,0xd3,0xa2,0x00,0xf0,0xff,0xff] - vpdpwuuds ymm12, ymm13, ymmword ptr [rdx - 4096] - -// CHECK: vpdpwuuds xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x10,0xd3,0xa4,0xf5,0x00,0x00,0x00,0x10] - vpdpwuuds xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vpdpwuuds xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x10,0xd3,0xa4,0x80,0x23,0x01,0x00,0x00] - vpdpwuuds xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vpdpwuuds xmm12, xmm13, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x10,0xd3,0x25,0x00,0x00,0x00,0x00] - vpdpwuuds xmm12, xmm13, xmmword ptr [rip] - -// CHECK: vpdpwuuds xmm12, xmm13, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0x62,0x10,0xd3,0x24,0x6d,0x00,0xfe,0xff,0xff] - vpdpwuuds xmm12, xmm13, xmmword ptr [2*rbp - 512] - -// CHECK: vpdpwuuds xmm12, xmm13, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0x62,0x10,0xd3,0xa1,0xf0,0x07,0x00,0x00] - vpdpwuuds xmm12, xmm13, xmmword ptr [rcx + 2032] - -// CHECK: vpdpwuuds xmm12, xmm13, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0x62,0x10,0xd3,0xa2,0x00,0xf8,0xff,0xff] - vpdpwuuds xmm12, xmm13, xmmword ptr [rdx - 2048] - diff --git a/llvm/test/MC/X86/avx_ne_convert-32-att.s b/llvm/test/MC/X86/avx_ne_convert-32-att.s deleted file mode 100644 index 023d9c0e6a1c4..0000000000000 --- a/llvm/test/MC/X86/avx_ne_convert-32-att.s +++ /dev/null @@ -1,334 +0,0 @@ -// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s - -// CHECK: vbcstnebf162ps 268435456(%esp,%esi,8), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10] - vbcstnebf162ps 268435456(%esp,%esi,8), %xmm2 - -// CHECK: vbcstnebf162ps 291(%edi,%eax,4), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x94,0x87,0x23,0x01,0x00,0x00] - vbcstnebf162ps 291(%edi,%eax,4), %xmm2 - -// CHECK: vbcstnebf162ps (%eax), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x10] - vbcstnebf162ps (%eax), %xmm2 - -// CHECK: vbcstnebf162ps -64(,%ebp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnebf162ps -64(,%ebp,2), %xmm2 - -// CHECK: vbcstnebf162ps 254(%ecx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnebf162ps 254(%ecx), %xmm2 - -// CHECK: vbcstnebf162ps -256(%edx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnebf162ps -256(%edx), %xmm2 - -// CHECK: vbcstnebf162ps 268435456(%esp,%esi,8), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10] - vbcstnebf162ps 268435456(%esp,%esi,8), %ymm2 - -// CHECK: vbcstnebf162ps 291(%edi,%eax,4), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x94,0x87,0x23,0x01,0x00,0x00] - vbcstnebf162ps 291(%edi,%eax,4), %ymm2 - -// CHECK: vbcstnebf162ps (%eax), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x10] - vbcstnebf162ps (%eax), %ymm2 - -// CHECK: vbcstnebf162ps -64(,%ebp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnebf162ps -64(,%ebp,2), %ymm2 - -// CHECK: vbcstnebf162ps 254(%ecx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnebf162ps 254(%ecx), %ymm2 - -// CHECK: vbcstnebf162ps -256(%edx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnebf162ps -256(%edx), %ymm2 - -// CHECK: vbcstnesh2ps 268435456(%esp,%esi,8), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10] - vbcstnesh2ps 268435456(%esp,%esi,8), %xmm2 - -// CHECK: vbcstnesh2ps 291(%edi,%eax,4), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x94,0x87,0x23,0x01,0x00,0x00] - vbcstnesh2ps 291(%edi,%eax,4), %xmm2 - -// CHECK: vbcstnesh2ps (%eax), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x10] - vbcstnesh2ps (%eax), %xmm2 - -// CHECK: vbcstnesh2ps -64(,%ebp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnesh2ps -64(,%ebp,2), %xmm2 - -// CHECK: vbcstnesh2ps 254(%ecx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnesh2ps 254(%ecx), %xmm2 - -// CHECK: vbcstnesh2ps -256(%edx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnesh2ps -256(%edx), %xmm2 - -// CHECK: vbcstnesh2ps 268435456(%esp,%esi,8), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10] - vbcstnesh2ps 268435456(%esp,%esi,8), %ymm2 - -// CHECK: vbcstnesh2ps 291(%edi,%eax,4), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x94,0x87,0x23,0x01,0x00,0x00] - vbcstnesh2ps 291(%edi,%eax,4), %ymm2 - -// CHECK: vbcstnesh2ps (%eax), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x10] - vbcstnesh2ps (%eax), %ymm2 - -// CHECK: vbcstnesh2ps -64(,%ebp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnesh2ps -64(,%ebp,2), %ymm2 - -// CHECK: vbcstnesh2ps 254(%ecx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnesh2ps 254(%ecx), %ymm2 - -// CHECK: vbcstnesh2ps -256(%edx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnesh2ps -256(%edx), %ymm2 - -// CHECK: vcvtneebf162ps 268435456(%esp,%esi,8), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneebf162ps 268435456(%esp,%esi,8), %xmm2 - -// CHECK: vcvtneebf162ps 291(%edi,%eax,4), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneebf162ps 291(%edi,%eax,4), %xmm2 - -// CHECK: vcvtneebf162ps (%eax), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x10] - vcvtneebf162ps (%eax), %xmm2 - -// CHECK: vcvtneebf162ps -512(,%ebp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneebf162ps -512(,%ebp,2), %xmm2 - -// CHECK: vcvtneebf162ps 2032(%ecx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneebf162ps 2032(%ecx), %xmm2 - -// CHECK: vcvtneebf162ps -2048(%edx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneebf162ps -2048(%edx), %xmm2 - -// CHECK: vcvtneebf162ps 268435456(%esp,%esi,8), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneebf162ps 268435456(%esp,%esi,8), %ymm2 - -// CHECK: vcvtneebf162ps 291(%edi,%eax,4), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneebf162ps 291(%edi,%eax,4), %ymm2 - -// CHECK: vcvtneebf162ps (%eax), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x10] - vcvtneebf162ps (%eax), %ymm2 - -// CHECK: vcvtneebf162ps -1024(,%ebp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneebf162ps -1024(,%ebp,2), %ymm2 - -// CHECK: vcvtneebf162ps 4064(%ecx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneebf162ps 4064(%ecx), %ymm2 - -// CHECK: vcvtneebf162ps -4096(%edx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneebf162ps -4096(%edx), %ymm2 - -// CHECK: vcvtneeph2ps 268435456(%esp,%esi,8), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneeph2ps 268435456(%esp,%esi,8), %xmm2 - -// CHECK: vcvtneeph2ps 291(%edi,%eax,4), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneeph2ps 291(%edi,%eax,4), %xmm2 - -// CHECK: vcvtneeph2ps (%eax), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x10] - vcvtneeph2ps (%eax), %xmm2 - -// CHECK: vcvtneeph2ps -512(,%ebp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneeph2ps -512(,%ebp,2), %xmm2 - -// CHECK: vcvtneeph2ps 2032(%ecx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneeph2ps 2032(%ecx), %xmm2 - -// CHECK: vcvtneeph2ps -2048(%edx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneeph2ps -2048(%edx), %xmm2 - -// CHECK: vcvtneeph2ps 268435456(%esp,%esi,8), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneeph2ps 268435456(%esp,%esi,8), %ymm2 - -// CHECK: vcvtneeph2ps 291(%edi,%eax,4), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneeph2ps 291(%edi,%eax,4), %ymm2 - -// CHECK: vcvtneeph2ps (%eax), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x10] - vcvtneeph2ps (%eax), %ymm2 - -// CHECK: vcvtneeph2ps -1024(,%ebp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneeph2ps -1024(,%ebp,2), %ymm2 - -// CHECK: vcvtneeph2ps 4064(%ecx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneeph2ps 4064(%ecx), %ymm2 - -// CHECK: vcvtneeph2ps -4096(%edx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneeph2ps -4096(%edx), %ymm2 - -// CHECK: vcvtneobf162ps 268435456(%esp,%esi,8), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneobf162ps 268435456(%esp,%esi,8), %xmm2 - -// CHECK: vcvtneobf162ps 291(%edi,%eax,4), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneobf162ps 291(%edi,%eax,4), %xmm2 - -// CHECK: vcvtneobf162ps (%eax), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x10] - vcvtneobf162ps (%eax), %xmm2 - -// CHECK: vcvtneobf162ps -512(,%ebp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneobf162ps -512(,%ebp,2), %xmm2 - -// CHECK: vcvtneobf162ps 2032(%ecx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneobf162ps 2032(%ecx), %xmm2 - -// CHECK: vcvtneobf162ps -2048(%edx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneobf162ps -2048(%edx), %xmm2 - -// CHECK: vcvtneobf162ps 268435456(%esp,%esi,8), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneobf162ps 268435456(%esp,%esi,8), %ymm2 - -// CHECK: vcvtneobf162ps 291(%edi,%eax,4), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneobf162ps 291(%edi,%eax,4), %ymm2 - -// CHECK: vcvtneobf162ps (%eax), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x10] - vcvtneobf162ps (%eax), %ymm2 - -// CHECK: vcvtneobf162ps -1024(,%ebp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneobf162ps -1024(,%ebp,2), %ymm2 - -// CHECK: vcvtneobf162ps 4064(%ecx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneobf162ps 4064(%ecx), %ymm2 - -// CHECK: vcvtneobf162ps -4096(%edx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneobf162ps -4096(%edx), %ymm2 - -// CHECK: vcvtneoph2ps 268435456(%esp,%esi,8), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneoph2ps 268435456(%esp,%esi,8), %xmm2 - -// CHECK: vcvtneoph2ps 291(%edi,%eax,4), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneoph2ps 291(%edi,%eax,4), %xmm2 - -// CHECK: vcvtneoph2ps (%eax), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x10] - vcvtneoph2ps (%eax), %xmm2 - -// CHECK: vcvtneoph2ps -512(,%ebp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneoph2ps -512(,%ebp,2), %xmm2 - -// CHECK: vcvtneoph2ps 2032(%ecx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneoph2ps 2032(%ecx), %xmm2 - -// CHECK: vcvtneoph2ps -2048(%edx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneoph2ps -2048(%edx), %xmm2 - -// CHECK: vcvtneoph2ps 268435456(%esp,%esi,8), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneoph2ps 268435456(%esp,%esi,8), %ymm2 - -// CHECK: vcvtneoph2ps 291(%edi,%eax,4), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneoph2ps 291(%edi,%eax,4), %ymm2 - -// CHECK: vcvtneoph2ps (%eax), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x10] - vcvtneoph2ps (%eax), %ymm2 - -// CHECK: vcvtneoph2ps -1024(,%ebp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneoph2ps -1024(,%ebp,2), %ymm2 - -// CHECK: vcvtneoph2ps 4064(%ecx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneoph2ps 4064(%ecx), %ymm2 - -// CHECK: vcvtneoph2ps -4096(%edx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneoph2ps -4096(%edx), %ymm2 - -// CHECK: {vex} vcvtneps2bf16 %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0xd3] - {vex} vcvtneps2bf16 %xmm3, %xmm2 - -// CHECK: {vex} vcvtneps2bf16 %ymm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0xd3] - {vex} vcvtneps2bf16 %ymm3, %xmm2 - -// CHECK: {vex} vcvtneps2bf16x 268435456(%esp,%esi,8), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x94,0xf4,0x00,0x00,0x00,0x10] - {vex} vcvtneps2bf16x 268435456(%esp,%esi,8), %xmm2 - -// CHECK: {vex} vcvtneps2bf16x 291(%edi,%eax,4), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x94,0x87,0x23,0x01,0x00,0x00] - {vex} vcvtneps2bf16x 291(%edi,%eax,4), %xmm2 - -// CHECK: {vex} vcvtneps2bf16x (%eax), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x10] - {vex} vcvtneps2bf16x (%eax), %xmm2 - -// CHECK: {vex} vcvtneps2bf16x -512(,%ebp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x14,0x6d,0x00,0xfe,0xff,0xff] - {vex} vcvtneps2bf16x -512(,%ebp,2), %xmm2 - -// CHECK: {vex} vcvtneps2bf16x 2032(%ecx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x91,0xf0,0x07,0x00,0x00] - {vex} vcvtneps2bf16x 2032(%ecx), %xmm2 - -// CHECK: {vex} vcvtneps2bf16x -2048(%edx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x92,0x00,0xf8,0xff,0xff] - {vex} vcvtneps2bf16x -2048(%edx), %xmm2 - -// CHECK: {vex} vcvtneps2bf16y -1024(,%ebp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff] - {vex} vcvtneps2bf16y -1024(,%ebp,2), %xmm2 - -// CHECK: {vex} vcvtneps2bf16y 4064(%ecx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x91,0xe0,0x0f,0x00,0x00] - {vex} vcvtneps2bf16y 4064(%ecx), %xmm2 - -// CHECK: {vex} vcvtneps2bf16y -4096(%edx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x92,0x00,0xf0,0xff,0xff] - {vex} vcvtneps2bf16y -4096(%edx), %xmm2 - diff --git a/llvm/test/MC/X86/avx_ne_convert-32-intel.s b/llvm/test/MC/X86/avx_ne_convert-32-intel.s deleted file mode 100644 index f92ce59750234..0000000000000 --- a/llvm/test/MC/X86/avx_ne_convert-32-intel.s +++ /dev/null @@ -1,334 +0,0 @@ -// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vbcstnebf162ps xmm2, word ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10] - vbcstnebf162ps xmm2, word ptr [esp + 8*esi + 268435456] - -// CHECK: vbcstnebf162ps xmm2, word ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x94,0x87,0x23,0x01,0x00,0x00] - vbcstnebf162ps xmm2, word ptr [edi + 4*eax + 291] - -// CHECK: vbcstnebf162ps xmm2, word ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x10] - vbcstnebf162ps xmm2, word ptr [eax] - -// CHECK: vbcstnebf162ps xmm2, word ptr [2*ebp - 64] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnebf162ps xmm2, word ptr [2*ebp - 64] - -// CHECK: vbcstnebf162ps xmm2, word ptr [ecx + 254] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnebf162ps xmm2, word ptr [ecx + 254] - -// CHECK: vbcstnebf162ps xmm2, word ptr [edx - 256] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnebf162ps xmm2, word ptr [edx - 256] - -// CHECK: vbcstnebf162ps ymm2, word ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10] - vbcstnebf162ps ymm2, word ptr [esp + 8*esi + 268435456] - -// CHECK: vbcstnebf162ps ymm2, word ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x94,0x87,0x23,0x01,0x00,0x00] - vbcstnebf162ps ymm2, word ptr [edi + 4*eax + 291] - -// CHECK: vbcstnebf162ps ymm2, word ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x10] - vbcstnebf162ps ymm2, word ptr [eax] - -// CHECK: vbcstnebf162ps ymm2, word ptr [2*ebp - 64] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnebf162ps ymm2, word ptr [2*ebp - 64] - -// CHECK: vbcstnebf162ps ymm2, word ptr [ecx + 254] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnebf162ps ymm2, word ptr [ecx + 254] - -// CHECK: vbcstnebf162ps ymm2, word ptr [edx - 256] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnebf162ps ymm2, word ptr [edx - 256] - -// CHECK: vbcstnesh2ps xmm2, word ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10] - vbcstnesh2ps xmm2, word ptr [esp + 8*esi + 268435456] - -// CHECK: vbcstnesh2ps xmm2, word ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x94,0x87,0x23,0x01,0x00,0x00] - vbcstnesh2ps xmm2, word ptr [edi + 4*eax + 291] - -// CHECK: vbcstnesh2ps xmm2, word ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x10] - vbcstnesh2ps xmm2, word ptr [eax] - -// CHECK: vbcstnesh2ps xmm2, word ptr [2*ebp - 64] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnesh2ps xmm2, word ptr [2*ebp - 64] - -// CHECK: vbcstnesh2ps xmm2, word ptr [ecx + 254] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnesh2ps xmm2, word ptr [ecx + 254] - -// CHECK: vbcstnesh2ps xmm2, word ptr [edx - 256] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnesh2ps xmm2, word ptr [edx - 256] - -// CHECK: vbcstnesh2ps ymm2, word ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x94,0xf4,0x00,0x00,0x00,0x10] - vbcstnesh2ps ymm2, word ptr [esp + 8*esi + 268435456] - -// CHECK: vbcstnesh2ps ymm2, word ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x94,0x87,0x23,0x01,0x00,0x00] - vbcstnesh2ps ymm2, word ptr [edi + 4*eax + 291] - -// CHECK: vbcstnesh2ps ymm2, word ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x10] - vbcstnesh2ps ymm2, word ptr [eax] - -// CHECK: vbcstnesh2ps ymm2, word ptr [2*ebp - 64] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnesh2ps ymm2, word ptr [2*ebp - 64] - -// CHECK: vbcstnesh2ps ymm2, word ptr [ecx + 254] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnesh2ps ymm2, word ptr [ecx + 254] - -// CHECK: vbcstnesh2ps ymm2, word ptr [edx - 256] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnesh2ps ymm2, word ptr [edx - 256] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneebf162ps xmm2, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneebf162ps xmm2, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x10] - vcvtneebf162ps xmm2, xmmword ptr [eax] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneebf162ps xmm2, xmmword ptr [2*ebp - 512] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneebf162ps xmm2, xmmword ptr [ecx + 2032] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneebf162ps xmm2, xmmword ptr [edx - 2048] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneebf162ps ymm2, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneebf162ps ymm2, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x10] - vcvtneebf162ps ymm2, ymmword ptr [eax] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneebf162ps ymm2, ymmword ptr [2*ebp - 1024] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneebf162ps ymm2, ymmword ptr [ecx + 4064] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneebf162ps ymm2, ymmword ptr [edx - 4096] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneeph2ps xmm2, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneeph2ps xmm2, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x10] - vcvtneeph2ps xmm2, xmmword ptr [eax] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneeph2ps xmm2, xmmword ptr [2*ebp - 512] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneeph2ps xmm2, xmmword ptr [ecx + 2032] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneeph2ps xmm2, xmmword ptr [edx - 2048] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneeph2ps ymm2, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneeph2ps ymm2, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x10] - vcvtneeph2ps ymm2, ymmword ptr [eax] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneeph2ps ymm2, ymmword ptr [2*ebp - 1024] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneeph2ps ymm2, ymmword ptr [ecx + 4064] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneeph2ps ymm2, ymmword ptr [edx - 4096] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneobf162ps xmm2, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneobf162ps xmm2, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x10] - vcvtneobf162ps xmm2, xmmword ptr [eax] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneobf162ps xmm2, xmmword ptr [2*ebp - 512] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneobf162ps xmm2, xmmword ptr [ecx + 2032] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneobf162ps xmm2, xmmword ptr [edx - 2048] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneobf162ps ymm2, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneobf162ps ymm2, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x10] - vcvtneobf162ps ymm2, ymmword ptr [eax] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneobf162ps ymm2, ymmword ptr [2*ebp - 1024] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneobf162ps ymm2, ymmword ptr [ecx + 4064] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneobf162ps ymm2, ymmword ptr [edx - 4096] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneoph2ps xmm2, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneoph2ps xmm2, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x10] - vcvtneoph2ps xmm2, xmmword ptr [eax] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneoph2ps xmm2, xmmword ptr [2*ebp - 512] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneoph2ps xmm2, xmmword ptr [ecx + 2032] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneoph2ps xmm2, xmmword ptr [edx - 2048] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x94,0xf4,0x00,0x00,0x00,0x10] - vcvtneoph2ps ymm2, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x94,0x87,0x23,0x01,0x00,0x00] - vcvtneoph2ps ymm2, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x10] - vcvtneoph2ps ymm2, ymmword ptr [eax] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneoph2ps ymm2, ymmword ptr [2*ebp - 1024] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneoph2ps ymm2, ymmword ptr [ecx + 4064] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneoph2ps ymm2, ymmword ptr [edx - 4096] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmm3 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0xd3] - {vex} vcvtneps2bf16 xmm2, xmm3 - -// CHECK: {vex} vcvtneps2bf16 xmm2, ymm3 -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0xd3] - {vex} vcvtneps2bf16 xmm2, ymm3 - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x94,0xf4,0x00,0x00,0x00,0x10] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x94,0x87,0x23,0x01,0x00,0x00] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [edi + 4*eax + 291] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x10] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [eax] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x14,0x6d,0x00,0xfe,0xff,0xff] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [2*ebp - 512] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x91,0xf0,0x07,0x00,0x00] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [ecx + 2032] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x92,0x00,0xf8,0xff,0xff] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [edx - 2048] - -// CHECK: {vex} vcvtneps2bf16 xmm2, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff] - {vex} vcvtneps2bf16 xmm2, ymmword ptr [2*ebp - 1024] - -// CHECK: {vex} vcvtneps2bf16 xmm2, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x91,0xe0,0x0f,0x00,0x00] - {vex} vcvtneps2bf16 xmm2, ymmword ptr [ecx + 4064] - -// CHECK: {vex} vcvtneps2bf16 xmm2, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x92,0x00,0xf0,0xff,0xff] - {vex} vcvtneps2bf16 xmm2, ymmword ptr [edx - 4096] - diff --git a/llvm/test/MC/X86/avx_ne_convert-64-att.s b/llvm/test/MC/X86/avx_ne_convert-64-att.s deleted file mode 100644 index 22cd9fedae825..0000000000000 --- a/llvm/test/MC/X86/avx_ne_convert-64-att.s +++ /dev/null @@ -1,334 +0,0 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s - -// CHECK: vbcstnebf162ps 268435456(%rbp,%r14,8), %xmm2 -// CHECK: encoding: [0xc4,0xa2,0x7a,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10] - vbcstnebf162ps 268435456(%rbp,%r14,8), %xmm2 - -// CHECK: vbcstnebf162ps 291(%r8,%rax,4), %xmm2 -// CHECK: encoding: [0xc4,0xc2,0x7a,0xb1,0x94,0x80,0x23,0x01,0x00,0x00] - vbcstnebf162ps 291(%r8,%rax,4), %xmm2 - -// CHECK: vbcstnebf162ps (%rip), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x15,0x00,0x00,0x00,0x00] - vbcstnebf162ps (%rip), %xmm2 - -// CHECK: vbcstnebf162ps -64(,%rbp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnebf162ps -64(,%rbp,2), %xmm2 - -// CHECK: vbcstnebf162ps 254(%rcx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnebf162ps 254(%rcx), %xmm2 - -// CHECK: vbcstnebf162ps -256(%rdx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnebf162ps -256(%rdx), %xmm2 - -// CHECK: vbcstnebf162ps 268435456(%rbp,%r14,8), %ymm2 -// CHECK: encoding: [0xc4,0xa2,0x7e,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10] - vbcstnebf162ps 268435456(%rbp,%r14,8), %ymm2 - -// CHECK: vbcstnebf162ps 291(%r8,%rax,4), %ymm2 -// CHECK: encoding: [0xc4,0xc2,0x7e,0xb1,0x94,0x80,0x23,0x01,0x00,0x00] - vbcstnebf162ps 291(%r8,%rax,4), %ymm2 - -// CHECK: vbcstnebf162ps (%rip), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x15,0x00,0x00,0x00,0x00] - vbcstnebf162ps (%rip), %ymm2 - -// CHECK: vbcstnebf162ps -64(,%rbp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnebf162ps -64(,%rbp,2), %ymm2 - -// CHECK: vbcstnebf162ps 254(%rcx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnebf162ps 254(%rcx), %ymm2 - -// CHECK: vbcstnebf162ps -256(%rdx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnebf162ps -256(%rdx), %ymm2 - -// CHECK: vbcstnesh2ps 268435456(%rbp,%r14,8), %xmm2 -// CHECK: encoding: [0xc4,0xa2,0x79,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10] - vbcstnesh2ps 268435456(%rbp,%r14,8), %xmm2 - -// CHECK: vbcstnesh2ps 291(%r8,%rax,4), %xmm2 -// CHECK: encoding: [0xc4,0xc2,0x79,0xb1,0x94,0x80,0x23,0x01,0x00,0x00] - vbcstnesh2ps 291(%r8,%rax,4), %xmm2 - -// CHECK: vbcstnesh2ps (%rip), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x15,0x00,0x00,0x00,0x00] - vbcstnesh2ps (%rip), %xmm2 - -// CHECK: vbcstnesh2ps -64(,%rbp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnesh2ps -64(,%rbp,2), %xmm2 - -// CHECK: vbcstnesh2ps 254(%rcx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnesh2ps 254(%rcx), %xmm2 - -// CHECK: vbcstnesh2ps -256(%rdx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnesh2ps -256(%rdx), %xmm2 - -// CHECK: vbcstnesh2ps 268435456(%rbp,%r14,8), %ymm2 -// CHECK: encoding: [0xc4,0xa2,0x7d,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10] - vbcstnesh2ps 268435456(%rbp,%r14,8), %ymm2 - -// CHECK: vbcstnesh2ps 291(%r8,%rax,4), %ymm2 -// CHECK: encoding: [0xc4,0xc2,0x7d,0xb1,0x94,0x80,0x23,0x01,0x00,0x00] - vbcstnesh2ps 291(%r8,%rax,4), %ymm2 - -// CHECK: vbcstnesh2ps (%rip), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x15,0x00,0x00,0x00,0x00] - vbcstnesh2ps (%rip), %ymm2 - -// CHECK: vbcstnesh2ps -64(,%rbp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnesh2ps -64(,%rbp,2), %ymm2 - -// CHECK: vbcstnesh2ps 254(%rcx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnesh2ps 254(%rcx), %ymm2 - -// CHECK: vbcstnesh2ps -256(%rdx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnesh2ps -256(%rdx), %ymm2 - -// CHECK: vcvtneebf162ps 268435456(%rbp,%r14,8), %xmm2 -// CHECK: encoding: [0xc4,0xa2,0x7a,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneebf162ps 268435456(%rbp,%r14,8), %xmm2 - -// CHECK: vcvtneebf162ps 291(%r8,%rax,4), %xmm2 -// CHECK: encoding: [0xc4,0xc2,0x7a,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneebf162ps 291(%r8,%rax,4), %xmm2 - -// CHECK: vcvtneebf162ps (%rip), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneebf162ps (%rip), %xmm2 - -// CHECK: vcvtneebf162ps -512(,%rbp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneebf162ps -512(,%rbp,2), %xmm2 - -// CHECK: vcvtneebf162ps 2032(%rcx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneebf162ps 2032(%rcx), %xmm2 - -// CHECK: vcvtneebf162ps -2048(%rdx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneebf162ps -2048(%rdx), %xmm2 - -// CHECK: vcvtneebf162ps 268435456(%rbp,%r14,8), %ymm2 -// CHECK: encoding: [0xc4,0xa2,0x7e,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneebf162ps 268435456(%rbp,%r14,8), %ymm2 - -// CHECK: vcvtneebf162ps 291(%r8,%rax,4), %ymm2 -// CHECK: encoding: [0xc4,0xc2,0x7e,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneebf162ps 291(%r8,%rax,4), %ymm2 - -// CHECK: vcvtneebf162ps (%rip), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneebf162ps (%rip), %ymm2 - -// CHECK: vcvtneebf162ps -1024(,%rbp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneebf162ps -1024(,%rbp,2), %ymm2 - -// CHECK: vcvtneebf162ps 4064(%rcx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneebf162ps 4064(%rcx), %ymm2 - -// CHECK: vcvtneebf162ps -4096(%rdx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneebf162ps -4096(%rdx), %ymm2 - -// CHECK: vcvtneeph2ps 268435456(%rbp,%r14,8), %xmm2 -// CHECK: encoding: [0xc4,0xa2,0x79,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneeph2ps 268435456(%rbp,%r14,8), %xmm2 - -// CHECK: vcvtneeph2ps 291(%r8,%rax,4), %xmm2 -// CHECK: encoding: [0xc4,0xc2,0x79,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneeph2ps 291(%r8,%rax,4), %xmm2 - -// CHECK: vcvtneeph2ps (%rip), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneeph2ps (%rip), %xmm2 - -// CHECK: vcvtneeph2ps -512(,%rbp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneeph2ps -512(,%rbp,2), %xmm2 - -// CHECK: vcvtneeph2ps 2032(%rcx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneeph2ps 2032(%rcx), %xmm2 - -// CHECK: vcvtneeph2ps -2048(%rdx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneeph2ps -2048(%rdx), %xmm2 - -// CHECK: vcvtneeph2ps 268435456(%rbp,%r14,8), %ymm2 -// CHECK: encoding: [0xc4,0xa2,0x7d,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneeph2ps 268435456(%rbp,%r14,8), %ymm2 - -// CHECK: vcvtneeph2ps 291(%r8,%rax,4), %ymm2 -// CHECK: encoding: [0xc4,0xc2,0x7d,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneeph2ps 291(%r8,%rax,4), %ymm2 - -// CHECK: vcvtneeph2ps (%rip), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneeph2ps (%rip), %ymm2 - -// CHECK: vcvtneeph2ps -1024(,%rbp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneeph2ps -1024(,%rbp,2), %ymm2 - -// CHECK: vcvtneeph2ps 4064(%rcx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneeph2ps 4064(%rcx), %ymm2 - -// CHECK: vcvtneeph2ps -4096(%rdx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneeph2ps -4096(%rdx), %ymm2 - -// CHECK: vcvtneobf162ps 268435456(%rbp,%r14,8), %xmm2 -// CHECK: encoding: [0xc4,0xa2,0x7b,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneobf162ps 268435456(%rbp,%r14,8), %xmm2 - -// CHECK: vcvtneobf162ps 291(%r8,%rax,4), %xmm2 -// CHECK: encoding: [0xc4,0xc2,0x7b,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneobf162ps 291(%r8,%rax,4), %xmm2 - -// CHECK: vcvtneobf162ps (%rip), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneobf162ps (%rip), %xmm2 - -// CHECK: vcvtneobf162ps -512(,%rbp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneobf162ps -512(,%rbp,2), %xmm2 - -// CHECK: vcvtneobf162ps 2032(%rcx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneobf162ps 2032(%rcx), %xmm2 - -// CHECK: vcvtneobf162ps -2048(%rdx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneobf162ps -2048(%rdx), %xmm2 - -// CHECK: vcvtneobf162ps 268435456(%rbp,%r14,8), %ymm2 -// CHECK: encoding: [0xc4,0xa2,0x7f,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneobf162ps 268435456(%rbp,%r14,8), %ymm2 - -// CHECK: vcvtneobf162ps 291(%r8,%rax,4), %ymm2 -// CHECK: encoding: [0xc4,0xc2,0x7f,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneobf162ps 291(%r8,%rax,4), %ymm2 - -// CHECK: vcvtneobf162ps (%rip), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneobf162ps (%rip), %ymm2 - -// CHECK: vcvtneobf162ps -1024(,%rbp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneobf162ps -1024(,%rbp,2), %ymm2 - -// CHECK: vcvtneobf162ps 4064(%rcx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneobf162ps 4064(%rcx), %ymm2 - -// CHECK: vcvtneobf162ps -4096(%rdx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneobf162ps -4096(%rdx), %ymm2 - -// CHECK: vcvtneoph2ps 268435456(%rbp,%r14,8), %xmm2 -// CHECK: encoding: [0xc4,0xa2,0x78,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneoph2ps 268435456(%rbp,%r14,8), %xmm2 - -// CHECK: vcvtneoph2ps 291(%r8,%rax,4), %xmm2 -// CHECK: encoding: [0xc4,0xc2,0x78,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneoph2ps 291(%r8,%rax,4), %xmm2 - -// CHECK: vcvtneoph2ps (%rip), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneoph2ps (%rip), %xmm2 - -// CHECK: vcvtneoph2ps -512(,%rbp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneoph2ps -512(,%rbp,2), %xmm2 - -// CHECK: vcvtneoph2ps 2032(%rcx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneoph2ps 2032(%rcx), %xmm2 - -// CHECK: vcvtneoph2ps -2048(%rdx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneoph2ps -2048(%rdx), %xmm2 - -// CHECK: vcvtneoph2ps 268435456(%rbp,%r14,8), %ymm2 -// CHECK: encoding: [0xc4,0xa2,0x7c,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneoph2ps 268435456(%rbp,%r14,8), %ymm2 - -// CHECK: vcvtneoph2ps 291(%r8,%rax,4), %ymm2 -// CHECK: encoding: [0xc4,0xc2,0x7c,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneoph2ps 291(%r8,%rax,4), %ymm2 - -// CHECK: vcvtneoph2ps (%rip), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneoph2ps (%rip), %ymm2 - -// CHECK: vcvtneoph2ps -1024(,%rbp,2), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneoph2ps -1024(,%rbp,2), %ymm2 - -// CHECK: vcvtneoph2ps 4064(%rcx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneoph2ps 4064(%rcx), %ymm2 - -// CHECK: vcvtneoph2ps -4096(%rdx), %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneoph2ps -4096(%rdx), %ymm2 - -// CHECK: {vex} vcvtneps2bf16 %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0xd3] - {vex} vcvtneps2bf16 %xmm3, %xmm2 - -// CHECK: {vex} vcvtneps2bf16 %ymm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0xd3] - {vex} vcvtneps2bf16 %ymm3, %xmm2 - -// CHECK: {vex} vcvtneps2bf16x 268435456(%rbp,%r14,8), %xmm2 -// CHECK: encoding: [0xc4,0xa2,0x7a,0x72,0x94,0xf5,0x00,0x00,0x00,0x10] - {vex} vcvtneps2bf16x 268435456(%rbp,%r14,8), %xmm2 - -// CHECK: {vex} vcvtneps2bf16x 291(%r8,%rax,4), %xmm2 -// CHECK: encoding: [0xc4,0xc2,0x7a,0x72,0x94,0x80,0x23,0x01,0x00,0x00] - {vex} vcvtneps2bf16x 291(%r8,%rax,4), %xmm2 - -// CHECK: {vex} vcvtneps2bf16x (%rip), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x15,0x00,0x00,0x00,0x00] - {vex} vcvtneps2bf16x (%rip), %xmm2 - -// CHECK: {vex} vcvtneps2bf16x -512(,%rbp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x14,0x6d,0x00,0xfe,0xff,0xff] - {vex} vcvtneps2bf16x -512(,%rbp,2), %xmm2 - -// CHECK: {vex} vcvtneps2bf16x 2032(%rcx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x91,0xf0,0x07,0x00,0x00] - {vex} vcvtneps2bf16x 2032(%rcx), %xmm2 - -// CHECK: {vex} vcvtneps2bf16x -2048(%rdx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x92,0x00,0xf8,0xff,0xff] - {vex} vcvtneps2bf16x -2048(%rdx), %xmm2 - -// CHECK: {vex} vcvtneps2bf16y -1024(,%rbp,2), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff] - {vex} vcvtneps2bf16y -1024(,%rbp,2), %xmm2 - -// CHECK: {vex} vcvtneps2bf16y 4064(%rcx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x91,0xe0,0x0f,0x00,0x00] - {vex} vcvtneps2bf16y 4064(%rcx), %xmm2 - -// CHECK: {vex} vcvtneps2bf16y -4096(%rdx), %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x92,0x00,0xf0,0xff,0xff] - {vex} vcvtneps2bf16y -4096(%rdx), %xmm2 - diff --git a/llvm/test/MC/X86/avx_ne_convert-64-intel.s b/llvm/test/MC/X86/avx_ne_convert-64-intel.s deleted file mode 100644 index fbe2488485af5..0000000000000 --- a/llvm/test/MC/X86/avx_ne_convert-64-intel.s +++ /dev/null @@ -1,334 +0,0 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vbcstnebf162ps xmm2, word ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x7a,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10] - vbcstnebf162ps xmm2, word ptr [rbp + 8*r14 + 268435456] - -// CHECK: vbcstnebf162ps xmm2, word ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x7a,0xb1,0x94,0x80,0x23,0x01,0x00,0x00] - vbcstnebf162ps xmm2, word ptr [r8 + 4*rax + 291] - -// CHECK: vbcstnebf162ps xmm2, word ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x15,0x00,0x00,0x00,0x00] - vbcstnebf162ps xmm2, word ptr [rip] - -// CHECK: vbcstnebf162ps xmm2, word ptr [2*rbp - 64] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnebf162ps xmm2, word ptr [2*rbp - 64] - -// CHECK: vbcstnebf162ps xmm2, word ptr [rcx + 254] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnebf162ps xmm2, word ptr [rcx + 254] - -// CHECK: vbcstnebf162ps xmm2, word ptr [rdx - 256] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnebf162ps xmm2, word ptr [rdx - 256] - -// CHECK: vbcstnebf162ps ymm2, word ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x7e,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10] - vbcstnebf162ps ymm2, word ptr [rbp + 8*r14 + 268435456] - -// CHECK: vbcstnebf162ps ymm2, word ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x7e,0xb1,0x94,0x80,0x23,0x01,0x00,0x00] - vbcstnebf162ps ymm2, word ptr [r8 + 4*rax + 291] - -// CHECK: vbcstnebf162ps ymm2, word ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x15,0x00,0x00,0x00,0x00] - vbcstnebf162ps ymm2, word ptr [rip] - -// CHECK: vbcstnebf162ps ymm2, word ptr [2*rbp - 64] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnebf162ps ymm2, word ptr [2*rbp - 64] - -// CHECK: vbcstnebf162ps ymm2, word ptr [rcx + 254] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnebf162ps ymm2, word ptr [rcx + 254] - -// CHECK: vbcstnebf162ps ymm2, word ptr [rdx - 256] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnebf162ps ymm2, word ptr [rdx - 256] - -// CHECK: vbcstnesh2ps xmm2, word ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x79,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10] - vbcstnesh2ps xmm2, word ptr [rbp + 8*r14 + 268435456] - -// CHECK: vbcstnesh2ps xmm2, word ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x79,0xb1,0x94,0x80,0x23,0x01,0x00,0x00] - vbcstnesh2ps xmm2, word ptr [r8 + 4*rax + 291] - -// CHECK: vbcstnesh2ps xmm2, word ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x15,0x00,0x00,0x00,0x00] - vbcstnesh2ps xmm2, word ptr [rip] - -// CHECK: vbcstnesh2ps xmm2, word ptr [2*rbp - 64] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnesh2ps xmm2, word ptr [2*rbp - 64] - -// CHECK: vbcstnesh2ps xmm2, word ptr [rcx + 254] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnesh2ps xmm2, word ptr [rcx + 254] - -// CHECK: vbcstnesh2ps xmm2, word ptr [rdx - 256] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnesh2ps xmm2, word ptr [rdx - 256] - -// CHECK: vbcstnesh2ps ymm2, word ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x7d,0xb1,0x94,0xf5,0x00,0x00,0x00,0x10] - vbcstnesh2ps ymm2, word ptr [rbp + 8*r14 + 268435456] - -// CHECK: vbcstnesh2ps ymm2, word ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x7d,0xb1,0x94,0x80,0x23,0x01,0x00,0x00] - vbcstnesh2ps ymm2, word ptr [r8 + 4*rax + 291] - -// CHECK: vbcstnesh2ps ymm2, word ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x15,0x00,0x00,0x00,0x00] - vbcstnesh2ps ymm2, word ptr [rip] - -// CHECK: vbcstnesh2ps ymm2, word ptr [2*rbp - 64] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x14,0x6d,0xc0,0xff,0xff,0xff] - vbcstnesh2ps ymm2, word ptr [2*rbp - 64] - -// CHECK: vbcstnesh2ps ymm2, word ptr [rcx + 254] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x91,0xfe,0x00,0x00,0x00] - vbcstnesh2ps ymm2, word ptr [rcx + 254] - -// CHECK: vbcstnesh2ps ymm2, word ptr [rdx - 256] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb1,0x92,0x00,0xff,0xff,0xff] - vbcstnesh2ps ymm2, word ptr [rdx - 256] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x7a,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneebf162ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x7a,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneebf162ps xmm2, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneebf162ps xmm2, xmmword ptr [rip] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneebf162ps xmm2, xmmword ptr [2*rbp - 512] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneebf162ps xmm2, xmmword ptr [rcx + 2032] - -// CHECK: vcvtneebf162ps xmm2, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x7a,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneebf162ps xmm2, xmmword ptr [rdx - 2048] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x7e,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneebf162ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x7e,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneebf162ps ymm2, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneebf162ps ymm2, ymmword ptr [rip] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneebf162ps ymm2, ymmword ptr [2*rbp - 1024] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneebf162ps ymm2, ymmword ptr [rcx + 4064] - -// CHECK: vcvtneebf162ps ymm2, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x7e,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneebf162ps ymm2, ymmword ptr [rdx - 4096] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x79,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneeph2ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x79,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneeph2ps xmm2, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneeph2ps xmm2, xmmword ptr [rip] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneeph2ps xmm2, xmmword ptr [2*rbp - 512] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneeph2ps xmm2, xmmword ptr [rcx + 2032] - -// CHECK: vcvtneeph2ps xmm2, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x79,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneeph2ps xmm2, xmmword ptr [rdx - 2048] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x7d,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneeph2ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x7d,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneeph2ps ymm2, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneeph2ps ymm2, ymmword ptr [rip] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneeph2ps ymm2, ymmword ptr [2*rbp - 1024] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneeph2ps ymm2, ymmword ptr [rcx + 4064] - -// CHECK: vcvtneeph2ps ymm2, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x7d,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneeph2ps ymm2, ymmword ptr [rdx - 4096] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x7b,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneobf162ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x7b,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneobf162ps xmm2, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneobf162ps xmm2, xmmword ptr [rip] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneobf162ps xmm2, xmmword ptr [2*rbp - 512] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneobf162ps xmm2, xmmword ptr [rcx + 2032] - -// CHECK: vcvtneobf162ps xmm2, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x7b,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneobf162ps xmm2, xmmword ptr [rdx - 2048] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x7f,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneobf162ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x7f,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneobf162ps ymm2, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneobf162ps ymm2, ymmword ptr [rip] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneobf162ps ymm2, ymmword ptr [2*rbp - 1024] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneobf162ps ymm2, ymmword ptr [rcx + 4064] - -// CHECK: vcvtneobf162ps ymm2, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x7f,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneobf162ps ymm2, ymmword ptr [rdx - 4096] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x78,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneoph2ps xmm2, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x78,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneoph2ps xmm2, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneoph2ps xmm2, xmmword ptr [rip] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x14,0x6d,0x00,0xfe,0xff,0xff] - vcvtneoph2ps xmm2, xmmword ptr [2*rbp - 512] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x91,0xf0,0x07,0x00,0x00] - vcvtneoph2ps xmm2, xmmword ptr [rcx + 2032] - -// CHECK: vcvtneoph2ps xmm2, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x78,0xb0,0x92,0x00,0xf8,0xff,0xff] - vcvtneoph2ps xmm2, xmmword ptr [rdx - 2048] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x7c,0xb0,0x94,0xf5,0x00,0x00,0x00,0x10] - vcvtneoph2ps ymm2, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x7c,0xb0,0x94,0x80,0x23,0x01,0x00,0x00] - vcvtneoph2ps ymm2, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x15,0x00,0x00,0x00,0x00] - vcvtneoph2ps ymm2, ymmword ptr [rip] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x14,0x6d,0x00,0xfc,0xff,0xff] - vcvtneoph2ps ymm2, ymmword ptr [2*rbp - 1024] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x91,0xe0,0x0f,0x00,0x00] - vcvtneoph2ps ymm2, ymmword ptr [rcx + 4064] - -// CHECK: vcvtneoph2ps ymm2, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x7c,0xb0,0x92,0x00,0xf0,0xff,0xff] - vcvtneoph2ps ymm2, ymmword ptr [rdx - 4096] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmm3 -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0xd3] - {vex} vcvtneps2bf16 xmm2, xmm3 - -// CHECK: {vex} vcvtneps2bf16 xmm2, ymm3 -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0xd3] - {vex} vcvtneps2bf16 xmm2, ymm3 - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0xa2,0x7a,0x72,0x94,0xf5,0x00,0x00,0x00,0x10] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0xc2,0x7a,0x72,0x94,0x80,0x23,0x01,0x00,0x00] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x15,0x00,0x00,0x00,0x00] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [rip] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x14,0x6d,0x00,0xfe,0xff,0xff] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [2*rbp - 512] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x91,0xf0,0x07,0x00,0x00] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [rcx + 2032] - -// CHECK: {vex} vcvtneps2bf16 xmm2, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x7a,0x72,0x92,0x00,0xf8,0xff,0xff] - {vex} vcvtneps2bf16 xmm2, xmmword ptr [rdx - 2048] - -// CHECK: {vex} vcvtneps2bf16 xmm2, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff] - {vex} vcvtneps2bf16 xmm2, ymmword ptr [2*rbp - 1024] - -// CHECK: {vex} vcvtneps2bf16 xmm2, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x91,0xe0,0x0f,0x00,0x00] - {vex} vcvtneps2bf16 xmm2, ymmword ptr [rcx + 4064] - -// CHECK: {vex} vcvtneps2bf16 xmm2, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x7e,0x72,0x92,0x00,0xf0,0xff,0xff] - {vex} vcvtneps2bf16 xmm2, ymmword ptr [rdx - 4096] - diff --git a/llvm/test/MC/X86/sha512-32-att.s b/llvm/test/MC/X86/sha512-32-att.s deleted file mode 100644 index 1f1247282064c..0000000000000 --- a/llvm/test/MC/X86/sha512-32-att.s +++ /dev/null @@ -1,13 +0,0 @@ -// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s - -// CHECK: vsha512msg1 %xmm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] - vsha512msg1 %xmm3, %ymm2 - -// CHECK: vsha512msg2 %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] - vsha512msg2 %ymm3, %ymm2 - -// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] - vsha512rnds2 %xmm4, %ymm3, %ymm2 diff --git a/llvm/test/MC/X86/sha512-32-intel.s b/llvm/test/MC/X86/sha512-32-intel.s deleted file mode 100644 index 19cdff5d59be9..0000000000000 --- a/llvm/test/MC/X86/sha512-32-intel.s +++ /dev/null @@ -1,13 +0,0 @@ -// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vsha512msg1 ymm2, xmm3 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3] - vsha512msg1 ymm2, xmm3 - -// CHECK: vsha512msg2 ymm2, ymm3 -// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3] - vsha512msg2 ymm2, ymm3 - -// CHECK: vsha512rnds2 ymm2, ymm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4] - vsha512rnds2 ymm2, ymm3, xmm4 diff --git a/llvm/test/MC/X86/sha512-64-att.s b/llvm/test/MC/X86/sha512-64-att.s deleted file mode 100644 index 0b82f70dfc057..0000000000000 --- a/llvm/test/MC/X86/sha512-64-att.s +++ /dev/null @@ -1,14 +0,0 @@ -// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s - -// CHECK: vsha512msg1 %xmm3, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] - vsha512msg1 %xmm3, %ymm12 - -// CHECK: vsha512msg2 %ymm3, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] - vsha512msg2 %ymm3, %ymm12 - -// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] - vsha512rnds2 %xmm4, %ymm3, %ymm12 - diff --git a/llvm/test/MC/X86/sha512-64-intel.s b/llvm/test/MC/X86/sha512-64-intel.s deleted file mode 100644 index 243d0e94e0141..0000000000000 --- a/llvm/test/MC/X86/sha512-64-intel.s +++ /dev/null @@ -1,14 +0,0 @@ -// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vsha512msg1 ymm12, xmm3 -// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3] - vsha512msg1 ymm12, xmm3 - -// CHECK: vsha512msg2 ymm12, ymm3 -// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3] - vsha512msg2 ymm12, ymm3 - -// CHECK: vsha512rnds2 ymm12, ymm3, xmm4 -// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4] - vsha512rnds2 ymm12, ymm3, xmm4 - diff --git a/llvm/test/MC/X86/sm3-att-32.s b/llvm/test/MC/X86/sm3-att-32.s deleted file mode 100644 index 19ff6ed396590..0000000000000 --- a/llvm/test/MC/X86/sm3-att-32.s +++ /dev/null @@ -1,86 +0,0 @@ -// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s - -// CHECK: vsm3msg1 %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4] - vsm3msg1 %xmm4, %xmm3, %xmm2 - -// CHECK: vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vsm3msg1 (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10] - vsm3msg1 (%eax), %xmm3, %xmm2 - -// CHECK: vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] - vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vsm3msg1 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00] - vsm3msg1 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vsm3msg1 -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff] - vsm3msg1 -2048(%edx), %xmm3, %xmm2 - -// CHECK: vsm3msg2 %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4] - vsm3msg2 %xmm4, %xmm3, %xmm2 - -// CHECK: vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vsm3msg2 (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10] - vsm3msg2 (%eax), %xmm3, %xmm2 - -// CHECK: vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] - vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vsm3msg2 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00] - vsm3msg2 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vsm3msg2 -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff] - vsm3msg2 -2048(%edx), %xmm3, %xmm2 - -// CHECK: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b] - vsm3rnds2 $123, %xmm4, %xmm3, %xmm2 - -// CHECK: vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b] - vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b] - vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vsm3rnds2 $123, (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b] - vsm3rnds2 $123, (%eax), %xmm3, %xmm2 - -// CHECK: vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b] - vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b] - vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b] - vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2 - diff --git a/llvm/test/MC/X86/sm3-att-64.s b/llvm/test/MC/X86/sm3-att-64.s deleted file mode 100644 index e9ffd489b2b5a..0000000000000 --- a/llvm/test/MC/X86/sm3-att-64.s +++ /dev/null @@ -1,86 +0,0 @@ -// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s - -// CHECK: vsm3msg1 %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4] - vsm3msg1 %xmm4, %xmm13, %xmm12 - -// CHECK: vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vsm3msg1 (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00] - vsm3msg1 (%rip), %xmm13, %xmm12 - -// CHECK: vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] - vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vsm3msg1 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00] - vsm3msg1 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vsm3msg1 -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff] - vsm3msg1 -2048(%rdx), %xmm13, %xmm12 - -// CHECK: vsm3msg2 %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4] - vsm3msg2 %xmm4, %xmm13, %xmm12 - -// CHECK: vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vsm3msg2 (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00] - vsm3msg2 (%rip), %xmm13, %xmm12 - -// CHECK: vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] - vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vsm3msg2 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00] - vsm3msg2 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vsm3msg2 -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff] - vsm3msg2 -2048(%rdx), %xmm13, %xmm12 - -// CHECK: vsm3rnds2 $123, %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b] - vsm3rnds2 $123, %xmm4, %xmm13, %xmm12 - -// CHECK: vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b] - vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b] - vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vsm3rnds2 $123, (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b] - vsm3rnds2 $123, (%rip), %xmm13, %xmm12 - -// CHECK: vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b] - vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b] - vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b] - vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12 - diff --git a/llvm/test/MC/X86/sm3-intel-32.s b/llvm/test/MC/X86/sm3-intel-32.s deleted file mode 100644 index da3818a1dc997..0000000000000 --- a/llvm/test/MC/X86/sm3-intel-32.s +++ /dev/null @@ -1,86 +0,0 @@ -// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vsm3msg1 xmm2, xmm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4] - vsm3msg1 xmm2, xmm3, xmm4 - -// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10] - vsm3msg1 xmm2, xmm3, xmmword ptr [eax] - -// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] - vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512] - -// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00] - vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032] - -// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff] - vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048] - -// CHECK: vsm3msg2 xmm2, xmm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4] - vsm3msg2 xmm2, xmm3, xmm4 - -// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10] - vsm3msg2 xmm2, xmm3, xmmword ptr [eax] - -// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] - vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512] - -// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00] - vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032] - -// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff] - vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048] - -// CHECK: vsm3rnds2 xmm2, xmm3, xmm4, 123 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b] - vsm3rnds2 xmm2, xmm3, xmm4, 123 - -// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b] - vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123 - -// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b] - vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123 - -// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b] - vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123 - -// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b] - vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123 - -// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b] - vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123 - -// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123 -// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b] - vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123 - diff --git a/llvm/test/MC/X86/sm3-intel-64.s b/llvm/test/MC/X86/sm3-intel-64.s deleted file mode 100644 index 3325544388373..0000000000000 --- a/llvm/test/MC/X86/sm3-intel-64.s +++ /dev/null @@ -1,86 +0,0 @@ -// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vsm3msg1 xmm12, xmm13, xmm4 -// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4] - vsm3msg1 xmm12, xmm13, xmm4 - -// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00] - vsm3msg1 xmm12, xmm13, xmmword ptr [rip] - -// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] - vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512] - -// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00] - vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032] - -// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff] - vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048] - -// CHECK: vsm3msg2 xmm12, xmm13, xmm4 -// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4] - vsm3msg2 xmm12, xmm13, xmm4 - -// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00] - vsm3msg2 xmm12, xmm13, xmmword ptr [rip] - -// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] - vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512] - -// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00] - vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032] - -// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff] - vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048] - -// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123 -// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b] - vsm3rnds2 xmm12, xmm13, xmm4, 123 - -// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123 -// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b] - vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123 - -// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123 -// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b] - vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123 - -// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123 -// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b] - vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123 - -// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123 -// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b] - vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123 - -// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123 -// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b] - vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123 - -// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123 -// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b] - vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123 - diff --git a/llvm/test/MC/X86/sm4-32-att.s b/llvm/test/MC/X86/sm4-32-att.s deleted file mode 100644 index 724d119d97b4e..0000000000000 --- a/llvm/test/MC/X86/sm4-32-att.s +++ /dev/null @@ -1,114 +0,0 @@ -// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s - -// CHECK: vsm4key4 %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0xd4] - vsm4key4 %ymm4, %ymm3, %ymm2 - -// CHECK: vsm4key4 %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0xd4] - vsm4key4 %xmm4, %xmm3, %xmm2 - -// CHECK: vsm4key4 268435456(%esp,%esi,8), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm4key4 268435456(%esp,%esi,8), %ymm3, %ymm2 - -// CHECK: vsm4key4 291(%edi,%eax,4), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm4key4 291(%edi,%eax,4), %ymm3, %ymm2 - -// CHECK: vsm4key4 (%eax), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x10] - vsm4key4 (%eax), %ymm3, %ymm2 - -// CHECK: vsm4key4 -1024(,%ebp,2), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff] - vsm4key4 -1024(,%ebp,2), %ymm3, %ymm2 - -// CHECK: vsm4key4 4064(%ecx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x91,0xe0,0x0f,0x00,0x00] - vsm4key4 4064(%ecx), %ymm3, %ymm2 - -// CHECK: vsm4key4 -4096(%edx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x92,0x00,0xf0,0xff,0xff] - vsm4key4 -4096(%edx), %ymm3, %ymm2 - -// CHECK: vsm4key4 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm4key4 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vsm4key4 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm4key4 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vsm4key4 (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x10] - vsm4key4 (%eax), %xmm3, %xmm2 - -// CHECK: vsm4key4 -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] - vsm4key4 -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vsm4key4 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x91,0xf0,0x07,0x00,0x00] - vsm4key4 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vsm4key4 -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x92,0x00,0xf8,0xff,0xff] - vsm4key4 -2048(%edx), %xmm3, %xmm2 - -// CHECK: vsm4rnds4 %ymm4, %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0xd4] - vsm4rnds4 %ymm4, %ymm3, %ymm2 - -// CHECK: vsm4rnds4 %xmm4, %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0xd4] - vsm4rnds4 %xmm4, %xmm3, %xmm2 - -// CHECK: vsm4rnds4 268435456(%esp,%esi,8), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm4rnds4 268435456(%esp,%esi,8), %ymm3, %ymm2 - -// CHECK: vsm4rnds4 291(%edi,%eax,4), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm4rnds4 291(%edi,%eax,4), %ymm3, %ymm2 - -// CHECK: vsm4rnds4 (%eax), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x10] - vsm4rnds4 (%eax), %ymm3, %ymm2 - -// CHECK: vsm4rnds4 -1024(,%ebp,2), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff] - vsm4rnds4 -1024(,%ebp,2), %ymm3, %ymm2 - -// CHECK: vsm4rnds4 4064(%ecx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x91,0xe0,0x0f,0x00,0x00] - vsm4rnds4 4064(%ecx), %ymm3, %ymm2 - -// CHECK: vsm4rnds4 -4096(%edx), %ymm3, %ymm2 -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x92,0x00,0xf0,0xff,0xff] - vsm4rnds4 -4096(%edx), %ymm3, %ymm2 - -// CHECK: vsm4rnds4 268435456(%esp,%esi,8), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm4rnds4 268435456(%esp,%esi,8), %xmm3, %xmm2 - -// CHECK: vsm4rnds4 291(%edi,%eax,4), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm4rnds4 291(%edi,%eax,4), %xmm3, %xmm2 - -// CHECK: vsm4rnds4 (%eax), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x10] - vsm4rnds4 (%eax), %xmm3, %xmm2 - -// CHECK: vsm4rnds4 -512(,%ebp,2), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] - vsm4rnds4 -512(,%ebp,2), %xmm3, %xmm2 - -// CHECK: vsm4rnds4 2032(%ecx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x91,0xf0,0x07,0x00,0x00] - vsm4rnds4 2032(%ecx), %xmm3, %xmm2 - -// CHECK: vsm4rnds4 -2048(%edx), %xmm3, %xmm2 -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x92,0x00,0xf8,0xff,0xff] - vsm4rnds4 -2048(%edx), %xmm3, %xmm2 - diff --git a/llvm/test/MC/X86/sm4-32-intel.s b/llvm/test/MC/X86/sm4-32-intel.s deleted file mode 100644 index 1a413afced78a..0000000000000 --- a/llvm/test/MC/X86/sm4-32-intel.s +++ /dev/null @@ -1,113 +0,0 @@ -// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vsm4key4 ymm2, ymm3, ymm4 -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0xd4] - vsm4key4 ymm2, ymm3, ymm4 - -// CHECK: vsm4key4 xmm2, xmm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0xd4] - vsm4key4 xmm2, xmm3, xmm4 - -// CHECK: vsm4key4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm4key4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vsm4key4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm4key4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vsm4key4 ymm2, ymm3, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x10] - vsm4key4 ymm2, ymm3, ymmword ptr [eax] - -// CHECK: vsm4key4 ymm2, ymm3, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff] - vsm4key4 ymm2, ymm3, ymmword ptr [2*ebp - 1024] - -// CHECK: vsm4key4 ymm2, ymm3, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x91,0xe0,0x0f,0x00,0x00] - vsm4key4 ymm2, ymm3, ymmword ptr [ecx + 4064] - -// CHECK: vsm4key4 ymm2, ymm3, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x92,0x00,0xf0,0xff,0xff] - vsm4key4 ymm2, ymm3, ymmword ptr [edx - 4096] - -// CHECK: vsm4key4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm4key4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vsm4key4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm4key4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vsm4key4 xmm2, xmm3, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x10] - vsm4key4 xmm2, xmm3, xmmword ptr [eax] - -// CHECK: vsm4key4 xmm2, xmm3, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] - vsm4key4 xmm2, xmm3, xmmword ptr [2*ebp - 512] - -// CHECK: vsm4key4 xmm2, xmm3, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x91,0xf0,0x07,0x00,0x00] - vsm4key4 xmm2, xmm3, xmmword ptr [ecx + 2032] - -// CHECK: vsm4key4 xmm2, xmm3, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x92,0x00,0xf8,0xff,0xff] - vsm4key4 xmm2, xmm3, xmmword ptr [edx - 2048] - -// CHECK: vsm4rnds4 ymm2, ymm3, ymm4 -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0xd4] - vsm4rnds4 ymm2, ymm3, ymm4 - -// CHECK: vsm4rnds4 xmm2, xmm3, xmm4 -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0xd4] - vsm4rnds4 xmm2, xmm3, xmm4 - -// CHECK: vsm4rnds4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm4rnds4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] - -// CHECK: vsm4rnds4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm4rnds4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291] - -// CHECK: vsm4rnds4 ymm2, ymm3, ymmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x10] - vsm4rnds4 ymm2, ymm3, ymmword ptr [eax] - -// CHECK: vsm4rnds4 ymm2, ymm3, ymmword ptr [2*ebp - 1024] -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff] - vsm4rnds4 ymm2, ymm3, ymmword ptr [2*ebp - 1024] - -// CHECK: vsm4rnds4 ymm2, ymm3, ymmword ptr [ecx + 4064] -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x91,0xe0,0x0f,0x00,0x00] - vsm4rnds4 ymm2, ymm3, ymmword ptr [ecx + 4064] - -// CHECK: vsm4rnds4 ymm2, ymm3, ymmword ptr [edx - 4096] -// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x92,0x00,0xf0,0xff,0xff] - vsm4rnds4 ymm2, ymm3, ymmword ptr [edx - 4096] - -// CHECK: vsm4rnds4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x94,0xf4,0x00,0x00,0x00,0x10] - vsm4rnds4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vsm4rnds4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x94,0x87,0x23,0x01,0x00,0x00] - vsm4rnds4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291] - -// CHECK: vsm4rnds4 xmm2, xmm3, xmmword ptr [eax] -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x10] - vsm4rnds4 xmm2, xmm3, xmmword ptr [eax] - -// CHECK: vsm4rnds4 xmm2, xmm3, xmmword ptr [2*ebp - 512] -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff] - vsm4rnds4 xmm2, xmm3, xmmword ptr [2*ebp - 512] - -// CHECK: vsm4rnds4 xmm2, xmm3, xmmword ptr [ecx + 2032] -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x91,0xf0,0x07,0x00,0x00] - vsm4rnds4 xmm2, xmm3, xmmword ptr [ecx + 2032] - -// CHECK: vsm4rnds4 xmm2, xmm3, xmmword ptr [edx - 2048] -// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x92,0x00,0xf8,0xff,0xff] - vsm4rnds4 xmm2, xmm3, xmmword ptr [edx - 2048] diff --git a/llvm/test/MC/X86/sm4-64-att.s b/llvm/test/MC/X86/sm4-64-att.s deleted file mode 100644 index ca496666d4318..0000000000000 --- a/llvm/test/MC/X86/sm4-64-att.s +++ /dev/null @@ -1,114 +0,0 @@ -// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s - -// CHECK: vsm4key4 %ymm4, %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xe4] - vsm4key4 %ymm4, %ymm13, %ymm12 - -// CHECK: vsm4key4 %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xe4] - vsm4key4 %xmm4, %xmm13, %xmm12 - -// CHECK: vsm4key4 268435456(%rbp,%r14,8), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm4key4 268435456(%rbp,%r14,8), %ymm13, %ymm12 - -// CHECK: vsm4key4 291(%r8,%rax,4), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm4key4 291(%r8,%rax,4), %ymm13, %ymm12 - -// CHECK: vsm4key4 (%rip), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00] - vsm4key4 (%rip), %ymm13, %ymm12 - -// CHECK: vsm4key4 -1024(,%rbp,2), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff] - vsm4key4 -1024(,%rbp,2), %ymm13, %ymm12 - -// CHECK: vsm4key4 4064(%rcx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00] - vsm4key4 4064(%rcx), %ymm13, %ymm12 - -// CHECK: vsm4key4 -4096(%rdx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff] - vsm4key4 -4096(%rdx), %ymm13, %ymm12 - -// CHECK: vsm4key4 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm4key4 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vsm4key4 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm4key4 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vsm4key4 (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00] - vsm4key4 (%rip), %xmm13, %xmm12 - -// CHECK: vsm4key4 -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] - vsm4key4 -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vsm4key4 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00] - vsm4key4 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vsm4key4 -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff] - vsm4key4 -2048(%rdx), %xmm13, %xmm12 - -// CHECK: vsm4rnds4 %ymm4, %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xe4] - vsm4rnds4 %ymm4, %ymm13, %ymm12 - -// CHECK: vsm4rnds4 %xmm4, %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xe4] - vsm4rnds4 %xmm4, %xmm13, %xmm12 - -// CHECK: vsm4rnds4 268435456(%rbp,%r14,8), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x22,0x17,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm4rnds4 268435456(%rbp,%r14,8), %ymm13, %ymm12 - -// CHECK: vsm4rnds4 291(%r8,%rax,4), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x42,0x17,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm4rnds4 291(%r8,%rax,4), %ymm13, %ymm12 - -// CHECK: vsm4rnds4 (%rip), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x25,0x00,0x00,0x00,0x00] - vsm4rnds4 (%rip), %ymm13, %ymm12 - -// CHECK: vsm4rnds4 -1024(,%rbp,2), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff] - vsm4rnds4 -1024(,%rbp,2), %ymm13, %ymm12 - -// CHECK: vsm4rnds4 4064(%rcx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xa1,0xe0,0x0f,0x00,0x00] - vsm4rnds4 4064(%rcx), %ymm13, %ymm12 - -// CHECK: vsm4rnds4 -4096(%rdx), %ymm13, %ymm12 -// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xa2,0x00,0xf0,0xff,0xff] - vsm4rnds4 -4096(%rdx), %ymm13, %ymm12 - -// CHECK: vsm4rnds4 268435456(%rbp,%r14,8), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x22,0x13,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm4rnds4 268435456(%rbp,%r14,8), %xmm13, %xmm12 - -// CHECK: vsm4rnds4 291(%r8,%rax,4), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x42,0x13,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm4rnds4 291(%r8,%rax,4), %xmm13, %xmm12 - -// CHECK: vsm4rnds4 (%rip), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x13,0xda,0x25,0x00,0x00,0x00,0x00] - vsm4rnds4 (%rip), %xmm13, %xmm12 - -// CHECK: vsm4rnds4 -512(,%rbp,2), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x13,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] - vsm4rnds4 -512(,%rbp,2), %xmm13, %xmm12 - -// CHECK: vsm4rnds4 2032(%rcx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xa1,0xf0,0x07,0x00,0x00] - vsm4rnds4 2032(%rcx), %xmm13, %xmm12 - -// CHECK: vsm4rnds4 -2048(%rdx), %xmm13, %xmm12 -// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xa2,0x00,0xf8,0xff,0xff] - vsm4rnds4 -2048(%rdx), %xmm13, %xmm12 - diff --git a/llvm/test/MC/X86/sm4-64-intel.s b/llvm/test/MC/X86/sm4-64-intel.s deleted file mode 100644 index 3fd041fdd2dc2..0000000000000 --- a/llvm/test/MC/X86/sm4-64-intel.s +++ /dev/null @@ -1,114 +0,0 @@ -// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vsm4key4 ymm12, ymm13, ymm4 -// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xe4] - vsm4key4 ymm12, ymm13, ymm4 - -// CHECK: vsm4key4 xmm12, xmm13, xmm4 -// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xe4] - vsm4key4 xmm12, xmm13, xmm4 - -// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00] - vsm4key4 ymm12, ymm13, ymmword ptr [rip] - -// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff] - vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024] - -// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00] - vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064] - -// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff] - vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096] - -// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00] - vsm4key4 xmm12, xmm13, xmmword ptr [rip] - -// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] - vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512] - -// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00] - vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032] - -// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff] - vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048] - -// CHECK: vsm4rnds4 ymm12, ymm13, ymm4 -// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xe4] - vsm4rnds4 ymm12, ymm13, ymm4 - -// CHECK: vsm4rnds4 xmm12, xmm13, xmm4 -// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xe4] - vsm4rnds4 xmm12, xmm13, xmm4 - -// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x17,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x17,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291] - -// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x25,0x00,0x00,0x00,0x00] - vsm4rnds4 ymm12, ymm13, ymmword ptr [rip] - -// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [2*rbp - 1024] -// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff] - vsm4rnds4 ymm12, ymm13, ymmword ptr [2*rbp - 1024] - -// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rcx + 4064] -// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xa1,0xe0,0x0f,0x00,0x00] - vsm4rnds4 ymm12, ymm13, ymmword ptr [rcx + 4064] - -// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rdx - 4096] -// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xa2,0x00,0xf0,0xff,0xff] - vsm4rnds4 ymm12, ymm13, ymmword ptr [rdx - 4096] - -// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0xc4,0x22,0x13,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10] - vsm4rnds4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0xc4,0x42,0x13,0xda,0xa4,0x80,0x23,0x01,0x00,0x00] - vsm4rnds4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291] - -// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [rip] -// CHECK: encoding: [0xc4,0x62,0x13,0xda,0x25,0x00,0x00,0x00,0x00] - vsm4rnds4 xmm12, xmm13, xmmword ptr [rip] - -// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [2*rbp - 512] -// CHECK: encoding: [0xc4,0x62,0x13,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff] - vsm4rnds4 xmm12, xmm13, xmmword ptr [2*rbp - 512] - -// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [rcx + 2032] -// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xa1,0xf0,0x07,0x00,0x00] - vsm4rnds4 xmm12, xmm13, xmmword ptr [rcx + 2032] - -// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [rdx - 2048] -// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xa2,0x00,0xf8,0xff,0xff] - vsm4rnds4 xmm12, xmm13, xmmword ptr [rdx - 2048] - diff --git a/llvm/test/Other/new-pm-defaults.ll b/llvm/test/Other/new-pm-defaults.ll index 65b96c8b8ef5d..3be04e1adbabb 100644 --- a/llvm/test/Other/new-pm-defaults.ll +++ b/llvm/test/Other/new-pm-defaults.ll @@ -131,8 +131,6 @@ ; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy ; CHECK-EP-PEEPHOLE-NEXT: Running pass: NoOpFunctionPass ; CHECK-O-NEXT: Running pass: SimplifyCFGPass -; CHECK-O-NEXT: Running pass: AlwaysInlinerPass -; CHECK-O-NEXT: Running analysis: ProfileSummaryAnalysis ; CHECK-O-NEXT: Running pass: ModuleInlinerWrapperPass ; CHECK-O-NEXT: Running analysis: InlineAdvisorAnalysis ; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}GlobalsAA @@ -141,12 +139,14 @@ ; CHECK-O-NEXT: Running pass: InvalidateAnalysisPass<{{.*}}AAManager ; CHECK-O-NEXT: Invalidating analysis: AAManager ; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}ProfileSummaryAnalysis +; CHECK-O-NEXT: Running analysis: ProfileSummaryAnalysis ; CHECK-O-NEXT: Running analysis: InnerAnalysisManagerProxy ; CHECK-O-NEXT: Running analysis: LazyCallGraphAnalysis ; CHECK-O-NEXT: Running analysis: FunctionAnalysisManagerCGSCCProxy ; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy<{{.*}}LazyCallGraph::SCC{{.*}}> ; CHECK-O-NEXT: Running pass: DevirtSCCRepeatedPass ; CHECK-O-NEXT: Running pass: InlinerPass +; CHECK-O-NEXT: Running pass: InlinerPass ; CHECK-O-NEXT: Running pass: PostOrderFunctionAttrsPass ; CHECK-O3-NEXT: Running pass: ArgumentPromotionPass ; CHECK-O2-NEXT: Running pass: OpenMPOptCGSCCPass on (foo) diff --git a/llvm/test/Other/new-pm-print-pipeline.ll b/llvm/test/Other/new-pm-print-pipeline.ll index 3536932f4432e..cef071fb70314 100644 --- a/llvm/test/Other/new-pm-print-pipeline.ll +++ b/llvm/test/Other/new-pm-print-pipeline.ll @@ -59,7 +59,7 @@ ; CHECK-20: cgscc(inline,inline),cgscc(inline) ; RUN: opt -disable-output -disable-verify -print-pipeline-passes -passes='scc-oz-module-inliner' < %s | FileCheck %s --match-full-lines --check-prefixes=CHECK-21 -; CHECK-21: require,function(invalidate),require,cgscc(devirt<4>(inline,{{.*}},instcombine{{.*}})) +; CHECK-21: require,function(invalidate),require,cgscc(devirt<4>(inline,inline,{{.*}},instcombine{{.*}})) ; RUN: opt -disable-output -disable-verify -print-pipeline-passes -passes='cgscc(function(no-op-function)),function(no-op-function)' < %s | FileCheck %s --match-full-lines --check-prefixes=CHECK-22 ; CHECK-22: cgscc(function(no-op-function)),function(no-op-function) diff --git a/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll index 3a0fffe426da1..57c1f87567ee0 100644 --- a/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-postlink-defaults.ll @@ -62,8 +62,6 @@ ; CHECK-O-NEXT: Running analysis: TypeBasedAA ; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy ; CHECK-O-NEXT: Running pass: SimplifyCFGPass -; CHECK-O-NEXT: Running pass: AlwaysInlinerPass -; CHECK-PRELINK-O-NEXT: Running analysis: ProfileSummaryAnalysis ; CHECK-O-NEXT: Running pass: ModuleInlinerWrapperPass ; CHECK-O-NEXT: Running analysis: InlineAdvisorAnalysis ; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}GlobalsAA @@ -78,6 +76,7 @@ ; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy ; CHECK-O-NEXT: Running pass: DevirtSCCRepeatedPass ; CHECK-O-NEXT: Running pass: InlinerPass +; CHECK-O-NEXT: Running pass: InlinerPass ; CHECK-O-NEXT: Running pass: PostOrderFunctionAttrsPass ; CHECK-O3-NEXT: Running pass: ArgumentPromotionPass ; CHECK-O2-NEXT: Running pass: OpenMPOptCGSCCPass on (foo) diff --git a/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll index 4623edcaf6656..df56a5f8063de 100644 --- a/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll @@ -51,7 +51,6 @@ ; CHECK-O-NEXT: Running analysis: LoopAnalysis on foo ; CHECK-O-NEXT: Running analysis: PostDominatorTreeAnalysis on foo ; CHECK-O-NEXT: Running pass: SimplifyCFGPass -; CHECK-O-NEXT: Running pass: AlwaysInlinerPass ; CHECK-O-NEXT: Running pass: ModuleInlinerWrapperPass ; CHECK-O-NEXT: Running analysis: InlineAdvisorAnalysis ; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}GlobalsAA @@ -66,6 +65,7 @@ ; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy<{{.*}}LazyCallGraph::SCC{{.*}}> ; CHECK-O-NEXT: Running pass: DevirtSCCRepeatedPass ; CHECK-O-NEXT: Running pass: InlinerPass +; CHECK-O-NEXT: Running pass: InlinerPass ; CHECK-O-NEXT: Running pass: PostOrderFunctionAttrsPass ; CHECK-O3-NEXT: Running pass: ArgumentPromotionPass ; CHECK-O2-NEXT: Running pass: OpenMPOptCGSCCPass diff --git a/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll index 590afd925e841..018995267faf3 100644 --- a/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll @@ -61,7 +61,6 @@ ; CHECK-O-NEXT: Running pass: SimplifyCFGPass on foo ; CHECK-O-NEXT: Running pass: PGOForceFunctionAttrsPass -; CHECK-O-NEXT: Running pass: AlwaysInlinerPass ; CHECK-O-NEXT: Running pass: ModuleInlinerWrapperPass ; CHECK-O-NEXT: Running analysis: InlineAdvisorAnalysis ; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}GlobalsAA @@ -75,6 +74,7 @@ ; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy ; CHECK-O-NEXT: Running pass: DevirtSCCRepeatedPass ; CHECK-O-NEXT: Running pass: InlinerPass +; CHECK-O-NEXT: Running pass: InlinerPass ; CHECK-O-NEXT: Running pass: PostOrderFunctionAttrsPass ; CHECK-O3-NEXT: Running pass: ArgumentPromotionPass ; CHECK-O2-NEXT: Running pass: OpenMPOptCGSCCPass diff --git a/llvm/test/Other/new-pm-thinlto-prelink-defaults.ll b/llvm/test/Other/new-pm-thinlto-prelink-defaults.ll index dd6acd2c51ee7..83aec1d1ad7f1 100644 --- a/llvm/test/Other/new-pm-thinlto-prelink-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-prelink-defaults.ll @@ -94,8 +94,6 @@ ; CHECK-O-NEXT: Running analysis: TypeBasedAA ; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy ; CHECK-O-NEXT: Running pass: SimplifyCFGPass -; CHECK-O-NEXT: Running pass: AlwaysInlinerPass -; CHECK-O-NEXT: Running analysis: ProfileSummaryAnalysis ; CHECK-O-NEXT: Running pass: ModuleInlinerWrapperPass ; CHECK-O-NEXT: Running analysis: InlineAdvisorAnalysis ; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}GlobalsAA @@ -104,12 +102,14 @@ ; CHECK-O-NEXT: Running pass: InvalidateAnalysisPass<{{.*}}AAManager ; CHECK-O-NEXT: Invalidating analysis: AAManager ; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}ProfileSummaryAnalysis +; CHECK-O-NEXT: Running analysis: ProfileSummaryAnalysis ; CHECK-O-NEXT: Running analysis: InnerAnalysisManagerProxy ; CHECK-O-NEXT: Running analysis: LazyCallGraphAnalysis ; CHECK-O-NEXT: Running analysis: FunctionAnalysisManagerCGSCCProxy ; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy ; CHECK-O-NEXT: Running pass: DevirtSCCRepeatedPass ; CHECK-O-NEXT: Running pass: InlinerPass +; CHECK-O-NEXT: Running pass: InlinerPass ; CHECK-O-NEXT: Running pass: PostOrderFunctionAttrsPass ; CHECK-O3-NEXT: Running pass: ArgumentPromotionPass ; CHECK-O2-NEXT: Running pass: OpenMPOptCGSCCPass on (foo) diff --git a/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll index ee054527e20bd..2e316342e99fe 100644 --- a/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll @@ -86,7 +86,6 @@ ; CHECK-O-NEXT: Running analysis: InnerAnalysisManagerProxy ; CHECK-O-NEXT: Running analysis: OptimizationRemarkEmitterAnalysis on foo ; CHECK-O-NEXT: Running pass: PGOForceFunctionAttrsPass -; CHECK-O-NEXT: Running pass: AlwaysInlinerPass ; CHECK-O-NEXT: Running pass: ModuleInlinerWrapperPass ; CHECK-O-NEXT: Running analysis: InlineAdvisorAnalysis ; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}GlobalsAA @@ -101,6 +100,7 @@ ; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy<{{.*}}LazyCallGraph::SCC{{.*}}> ; CHECK-O-NEXT: Running pass: DevirtSCCRepeatedPass ; CHECK-O-NEXT: Running pass: InlinerPass +; CHECK-O-NEXT: Running pass: InlinerPass ; CHECK-O-NEXT: Running pass: PostOrderFunctionAttrsPass ; CHECK-O3-NEXT: Running pass: ArgumentPromotionPass ; CHECK-O2-NEXT: Running pass: OpenMPOptCGSCCPass diff --git a/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll index fd95e94f3c8b9..b7ae2560b31c6 100644 --- a/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll @@ -66,7 +66,6 @@ ; CHECK-O-NEXT: Running analysis: PostDominatorTreeAnalysis on foo ; CHECK-O-NEXT: Running pass: SimplifyCFGPass on foo ; CHECK-O-NEXT: Running pass: PGOForceFunctionAttrsPass -; CHECK-O-NEXT: Running pass: AlwaysInlinerPass ; CHECK-O-NEXT: Running pass: ModuleInlinerWrapperPass ; CHECK-O-NEXT: Running analysis: InlineAdvisorAnalysis ; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}GlobalsAA @@ -80,6 +79,7 @@ ; CHECK-O-NEXT: Running analysis: OuterAnalysisManagerProxy<{{.*}}LazyCallGraph::SCC{{.*}}> ; CHECK-O-NEXT: Running pass: DevirtSCCRepeatedPass ; CHECK-O-NEXT: Running pass: InlinerPass +; CHECK-O-NEXT: Running pass: InlinerPass ; CHECK-O-NEXT: Running pass: PostOrderFunctionAttrsPass ; CHECK-O3-NEXT: Running pass: ArgumentPromotionPass ; CHECK-O2-NEXT: Running pass: OpenMPOptCGSCCPass diff --git a/llvm/test/Other/pipeline-alias-errors.ll b/llvm/test/Other/pipeline-alias-errors.ll index f27dd76568a56..de7ef8da7e2c9 100644 --- a/llvm/test/Other/pipeline-alias-errors.ll +++ b/llvm/test/Other/pipeline-alias-errors.ll @@ -1,5 +1,7 @@ ; RUN: not opt -passes="default" < %s 2>&1 | FileCheck %s --check-prefix=MISSING-OPT-LEVEL ; RUN: not opt -passes="default" < %s 2>&1 | FileCheck %s --check-prefix=INVALID-OPT-LEVEL +; RUN: not opt -passes="default-post-link" < %s 2>&1 | FileCheck %s --check-prefix=MISSING-OPT-LEVEL +; RUN: not opt -passes="default-post-link" < %s 2>&1 | FileCheck %s --check-prefix=INVALID-OPT-LEVEL ; RUN: not opt -passes="thinlto-pre-link" < %s 2>&1 | FileCheck %s --check-prefix=MISSING-OPT-LEVEL ; RUN: not opt -passes="thinlto-pre-link" < %s 2>&1 | FileCheck %s --check-prefix=INVALID-OPT-LEVEL ; RUN: not opt -passes="thinlto" < %s 2>&1 | FileCheck %s --check-prefix=MISSING-OPT-LEVEL diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td index e0b802447ea2a..70ed9d191294f 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td @@ -34,7 +34,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(20), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label 3*/ GIMT_Encode4([[L579:[0-9]+]]), +// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2({{[0-9]+}}), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label 3*/ GIMT_Encode4([[L579:[0-9]+]]), // CHECK-NEXT: /*TargetOpcode::COPY*//*Label 0*/ GIMT_Encode4([[L462:[0-9]+]]), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), // CHECK-NEXT: /*TargetOpcode::G_CONSTANT*//*Label 1*/ GIMT_Encode4([[L493:[0-9]+]]), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), // CHECK-NEXT: /*TargetOpcode::G_ZEXT*//*Label 2*/ GIMT_Encode4({{[0-9]+}}), diff --git a/llvm/test/TableGen/x86-auto-memfold.td b/llvm/test/TableGen/x86-auto-memfold.td new file mode 100644 index 0000000000000..8d00f6593743d --- /dev/null +++ b/llvm/test/TableGen/x86-auto-memfold.td @@ -0,0 +1,5 @@ +// waiting for upstream to fix ... +// XFAIL:* + +// RUN: llvm-tblgen -gen-x86-fold-tables -asmwriternum=1 %p/../../lib/Target/X86/X86.td -I %p/../../include -I %p/../../lib/Target/X86/ -I %p/../../include/ -I %p/../../lib/Target/ --write-if-changed -o %t1 +// RUN: cmp %p/../../lib/Target/X86/X86MemFoldTables.inc %t1 diff --git a/llvm/test/ThinLTO/AArch64/cgdata-two-rounds-caching.ll b/llvm/test/ThinLTO/AArch64/cgdata-two-rounds-caching.ll index e11903bf0f3bf..07ed0f858c7be 100644 --- a/llvm/test/ThinLTO/AArch64/cgdata-two-rounds-caching.ll +++ b/llvm/test/ThinLTO/AArch64/cgdata-two-rounds-caching.ll @@ -1,7 +1,6 @@ ; This test verifies whether we can outline a singleton instance (i.e., an instance that does not repeat) ; by running two codegen rounds. ; This test also verifies if caches for the two-round codegens are correctly working. - ; REQUIRES: asserts ; RUN: rm -rf %t ; RUN: split-file %s %t diff --git a/llvm/test/ThinLTO/X86/alias_import.ll b/llvm/test/ThinLTO/X86/alias_import.ll index bc5e3ec4c20e8..c37cf46afa2e3 100644 --- a/llvm/test/ThinLTO/X86/alias_import.ll +++ b/llvm/test/ThinLTO/X86/alias_import.ll @@ -1,8 +1,8 @@ -; RUN: opt -module-summary %s -o %t1.bc -; RUN: opt -module-summary %p/Inputs/alias_import.ll -o %t2.bc -; RUN: llvm-lto -thinlto-action=thinlink -o %t.index.bc %t1.bc %t2.bc -; RUN: llvm-lto -thinlto-action=promote -thinlto-index %t.index.bc %t2.bc -o - | llvm-dis -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=PROMOTE -; RUN: llvm-lto -thinlto-action=import -thinlto-index %t.index.bc %t1.bc -o - | llvm-dis -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=IMPORT +; RUN: opt -module-summary %s -o %t1.bc +; RUN: opt -module-summary %p/Inputs/alias_import.ll -o %t2.bc +; RUN: llvm-lto -thinlto-action=thinlink -o %t.index.bc %t1.bc %t2.bc +; RUN: llvm-lto -thinlto-action=promote -thinlto-index %t.index.bc %t2.bc -o - | llvm-dis -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=PROMOTE +; RUN: llvm-lto -thinlto-action=import -thinlto-index %t.index.bc %t1.bc -o - | llvm-dis -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=IMPORT ; Alias can't point to "available_externally", so they are implemented by ; importing the alias as an available_externally definition copied from the diff --git a/llvm/test/ThinLTO/X86/alias_resolution.ll b/llvm/test/ThinLTO/X86/alias_resolution.ll index 4bd6ede357dfd..30fa3b682742d 100644 --- a/llvm/test/ThinLTO/X86/alias_resolution.ll +++ b/llvm/test/ThinLTO/X86/alias_resolution.ll @@ -1,8 +1,8 @@ -; RUN: opt -module-summary %s -o %t1.bc -; RUN: opt -module-summary %p/Inputs/alias_resolution.ll -o %t2.bc -; RUN: llvm-lto -thinlto-action=thinlink -o %t.index.bc %t1.bc %t2.bc -; RUN: llvm-lto -thinlto-action=promote -thinlto-index %t.index.bc %t2.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=PROMOTE_MOD2 --check-prefix=NOTPROMOTED -; RUN: llvm-lto -thinlto-action=promote -thinlto-index %t.index.bc %t1.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=PROMOTE_MOD1 --check-prefix=NOTPROMOTED +; RUN: opt -module-summary %s -o %t1.bc +; RUN: opt -module-summary %p/Inputs/alias_resolution.ll -o %t2.bc +; RUN: llvm-lto -thinlto-action=thinlink -o %t.index.bc %t1.bc %t2.bc +; RUN: llvm-lto -thinlto-action=promote -thinlto-index %t.index.bc %t2.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=PROMOTE_MOD2 --check-prefix=NOTPROMOTED +; RUN: llvm-lto -thinlto-action=promote -thinlto-index %t.index.bc %t1.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=PROMOTE_MOD1 --check-prefix=NOTPROMOTED ; There is no importing going on with this IR, but let's check the ODR resolution for compile time diff --git a/llvm/test/ThinLTO/X86/devirt_promote_legacy.ll b/llvm/test/ThinLTO/X86/devirt_promote_legacy.ll index 542c1e85b6dde..2693e5b025092 100644 --- a/llvm/test/ThinLTO/X86/devirt_promote_legacy.ll +++ b/llvm/test/ThinLTO/X86/devirt_promote_legacy.ll @@ -6,17 +6,17 @@ ; update. ; Generate unsplit module with summary for ThinLTO index-based WPD. -; RUN: opt -thinlto-bc -o %t3.o %s -; RUN: opt -thinlto-bc -o %t4.o %p/Inputs/devirt_promote.ll +; RUN: opt -thinlto-bc -o %t3.o %s +; RUN: opt -thinlto-bc -o %t4.o %p/Inputs/devirt_promote.ll -; RUN: llvm-lto -thinlto-action=run %t3.o %t4.o --thinlto-save-temps=%t5. \ +; RUN: llvm-lto -thinlto-action=run %t3.o %t4.o --thinlto-save-temps=%t5. \ ; RUN: -whole-program-visibility \ ; RUN: --pass-remarks=. \ ; RUN: --exported-symbol=test \ ; RUN: --exported-symbol=test2 \ ; RUN: --exported-symbol=_ZTV1B 2>&1 | FileCheck %s --check-prefix=REMARK -; RUN: llvm-dis %t5.0.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-IR1 -; RUN: llvm-dis %t5.1.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-IR2 +; RUN: llvm-dis %t5.0.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-IR1 +; RUN: llvm-dis %t5.1.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-IR2 ; We should devirt call to _ZN1A1nEi once in importing module and once ; in original (exporting) module. diff --git a/llvm/test/ThinLTO/X86/funcimport.ll b/llvm/test/ThinLTO/X86/funcimport.ll index 3f7941bb76488..aba12b4f2b23e 100644 --- a/llvm/test/ThinLTO/X86/funcimport.ll +++ b/llvm/test/ThinLTO/X86/funcimport.ll @@ -1,14 +1,14 @@ ; Do setup work for all below tests: generate bitcode and combined index -; RUN: opt -module-summary %s -o %t.bc -; RUN: opt -module-summary %p/Inputs/funcimport.ll -o %t2.bc -; RUN: llvm-lto -thinlto-action=thinlink -o %t3.bc %t.bc %t2.bc +; RUN: opt -module-summary %s -o %t.bc +; RUN: opt -module-summary %p/Inputs/funcimport.ll -o %t2.bc +; RUN: llvm-lto -thinlto-action=thinlink -o %t3.bc %t.bc %t2.bc -; RUN: llvm-lto -thinlto-index-stats %t3.bc | FileCheck %s -check-prefix=STATS +; RUN: llvm-lto -thinlto-index-stats %t3.bc | FileCheck %s -check-prefix=STATS ; STATS: Index {{.*}} contains 24 nodes (13 functions, 3 alias, 8 globals) and 19 edges (8 refs and 11 calls) ; Ensure statics are promoted/renamed correctly from this file (all but ; constant variable need promotion). -; RUN: llvm-lto -thinlto-action=promote %t.bc -thinlto-index=%t3.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=EXPORTSTATIC +; RUN: llvm-lto -thinlto-action=promote %t.bc -thinlto-index=%t3.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=EXPORTSTATIC ; EXPORTSTATIC-DAG: @staticvar.llvm.0 = hidden global ; Eventually @staticconstvar can be exported as a copy and not promoted ; EXPORTSTATIC-DAG: @staticconstvar.llvm.0 = hidden unnamed_addr constant @@ -21,7 +21,7 @@ ; Also ensures that alias to a linkonce function is turned into a declaration ; and that the associated linkonce function is not in the output, as it is ; lazily linked and never referenced/materialized. -; RUN: llvm-lto -thinlto-action=import %t2.bc -thinlto-index=%t3.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=IMPORTGLOB1 +; RUN: llvm-lto -thinlto-action=import %t2.bc -thinlto-index=%t3.bc -o - | llvm-dis -o - | FileCheck %s --check-prefix=IMPORTGLOB1 ; IMPORTGLOB1-DAG: define available_externally void @globalfunc1 ; IMPORTGLOB1-DAG: declare void @weakalias ; IMPORTGLOB1-NOT: @linkoncealias @@ -36,11 +36,11 @@ ; OPTIMIZED: define noundef i32 @main() ; Verify that the codegen run -; RUN: llvm-lto -thinlto-action=codegen %t2.bc -o - | llvm-nm -o - | FileCheck %s --check-prefix=CODEGEN +; RUN: llvm-lto -thinlto-action=codegen %t2.bc -o - | llvm-nm -o - | FileCheck %s --check-prefix=CODEGEN ; CODEGEN: T _main ; Verify that all run together -; RUN: llvm-lto -thinlto-action=run %t2.bc %t.bc -exported-symbol=_main +; RUN: llvm-lto -thinlto-action=run %t2.bc %t.bc -exported-symbol=_main ; RUN: llvm-nm -o - < %t.bc.thinlto.o | FileCheck %s --check-prefix=ALL ; RUN: llvm-nm -o - < %t2.bc.thinlto.o | FileCheck %s --check-prefix=ALL2 ; ALL: T _callfuncptr diff --git a/llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll b/llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll index 3768549c558c5..564b1d8c32641 100644 --- a/llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll +++ b/llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll @@ -2,12 +2,12 @@ ; comdats after making it available_externally. If not we would get a ; verification error. g_internal/g_private are changed to available_externally ; as well since it is in the same comdat of g. -; RUN: opt -module-summary %s -o %t1.bc -; RUN: opt -module-summary %p/Inputs/linkonce_resolution_comdat.ll -o %t2.bc -; RUN: llvm-lto -thinlto-action=run -disable-thinlto-funcattrs=0 %t1.bc %t2.bc -exported-symbol=f -exported-symbol=g -exported-symbol=h -thinlto-save-temps=%t3. +; RUN: opt -module-summary %s -o %t1.bc +; RUN: opt -module-summary %p/Inputs/linkonce_resolution_comdat.ll -o %t2.bc +; RUN: llvm-lto -thinlto-action=run -disable-thinlto-funcattrs=0 %t1.bc %t2.bc -exported-symbol=f -exported-symbol=g -exported-symbol=h -thinlto-save-temps=%t3. -; RUN: llvm-dis %t3.0.3.imported.bc -o - | FileCheck %s --check-prefix=IMPORT1 -; RUN: llvm-dis %t3.1.3.imported.bc -o - | FileCheck %s --check-prefix=IMPORT2 +; RUN: llvm-dis %t3.0.3.imported.bc -o - | FileCheck %s --check-prefix=IMPORT1 +; RUN: llvm-dis %t3.1.3.imported.bc -o - | FileCheck %s --check-prefix=IMPORT2 ; Copy from first module is prevailing and converted to weak_odr, copy ; from second module is preempted and converted to available_externally and ; removed from comdat. diff --git a/llvm/test/Transforms/Attributor/callgraph.ll b/llvm/test/Transforms/Attributor/callgraph.ll index 84e2c54bd832d..98b1a661960bd 100644 --- a/llvm/test/Transforms/Attributor/callgraph.ll +++ b/llvm/test/Transforms/Attributor/callgraph.ll @@ -576,20 +576,9 @@ define void @func7(ptr %unknown) { ; Check there's no crash if something that isn't a function appears in !callees define void @undef_in_callees() { -; UNLIM-LABEL: @undef_in_callees( -; UNLIM-NEXT: cond.end.i: -; UNLIM-NEXT: call void undef(ptr undef, i32 undef, ptr undef), !callees [[META2:![0-9]+]] -; UNLIM-NEXT: ret void -; -; LIMI2-LABEL: @undef_in_callees( -; LIMI2-NEXT: cond.end.i: -; LIMI2-NEXT: call void undef(ptr undef, i32 undef, ptr undef), !callees [[META4:![0-9]+]] -; LIMI2-NEXT: ret void -; -; LIMI0-LABEL: @undef_in_callees( -; LIMI0-NEXT: cond.end.i: -; LIMI0-NEXT: call void undef(ptr undef, i32 undef, ptr undef), !callees [[META6:![0-9]+]] -; LIMI0-NEXT: ret void +; CHECK-LABEL: @undef_in_callees( +; CHECK-NEXT: cond.end.i: +; CHECK-NEXT: unreachable ; cond.end.i: call void undef(ptr undef, i32 undef, ptr undef), !callees !3 @@ -699,13 +688,11 @@ define void @as_cast(ptr %arg) { ;. ; OUNLM: [[META0:![0-9]+]] = !{[[META1:![0-9]+]]} ; OUNLM: [[META1]] = !{i64 0, i1 false} -; OUNLM: [[META2]] = distinct !{ptr undef, ptr null} ;. ; LIMI2: [[META0]] = !{ptr @void, ptr @retFloatTakeFloat} ; LIMI2: [[META1]] = !{ptr @void} ; LIMI2: [[META2:![0-9]+]] = !{[[META3:![0-9]+]]} ; LIMI2: [[META3]] = !{i64 0, i1 false} -; LIMI2: [[META4]] = distinct !{ptr undef, ptr null} ;. ; LIMI0: [[META0]] = !{ptr @func4, ptr @internal_good} ; LIMI0: [[META1]] = !{ptr @func3, ptr @func4} @@ -713,11 +700,9 @@ define void @as_cast(ptr %arg) { ; LIMI0: [[META3]] = !{ptr @takeI32, ptr @retI32, ptr @void} ; LIMI0: [[META4:![0-9]+]] = !{[[META5:![0-9]+]]} ; LIMI0: [[META5]] = !{i64 0, i1 false} -; LIMI0: [[META6]] = distinct !{ptr undef, ptr null} ;. ; CWRLD: [[META0:![0-9]+]] = !{[[META1:![0-9]+]]} ; CWRLD: [[META1]] = !{i64 0, i1 false} -; CWRLD: [[META2]] = distinct !{ptr undef, ptr null} ;. ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; DOT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/reduced/clear_cached_analysis_for_deleted_functions.ll b/llvm/test/Transforms/Attributor/reduced/clear_cached_analysis_for_deleted_functions.ll index 03149f2652a6e..920bfbaecda7a 100644 --- a/llvm/test/Transforms/Attributor/reduced/clear_cached_analysis_for_deleted_functions.ll +++ b/llvm/test/Transforms/Attributor/reduced/clear_cached_analysis_for_deleted_functions.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -aa-pipeline=basic-aa -passes="attributor-cgscc,argpromotion" -S < %s | FileCheck %s --check-prefix=CGSCC +; RUN: opt -aa-pipeline=basic-aa -passes="attributor-cgscc,argpromotion" -S < %s | FileCheck %s --check-prefixes=CGSCC ; This used to crash because the attributor-cgscc pass rewrote the ; flag_GetFlagValue function but did not clear the cached analysis for the diff --git a/llvm/test/Transforms/Attributor/value-simplify.ll b/llvm/test/Transforms/Attributor/value-simplify.ll index beceab7ce9ed7..463ecb3003a83 100644 --- a/llvm/test/Transforms/Attributor/value-simplify.ll +++ b/llvm/test/Transforms/Attributor/value-simplify.ll @@ -975,11 +975,11 @@ define i1 @icmp() { define void @test_callee_is_undef(ptr %fn) { ; TUNIT-LABEL: define {{[^@]+}}@test_callee_is_undef ; TUNIT-SAME: (ptr nofree captures(none) [[FN:%.*]]) { -; TUNIT-NEXT: call void @unknown_calle_arg_is_undef(ptr nofree noundef captures(none) [[FN]]) -; TUNIT-NEXT: ret void +; TUNIT-NEXT: unreachable ; ; CGSCC-LABEL: define {{[^@]+}}@test_callee_is_undef -; CGSCC-SAME: (ptr nofree noundef nonnull captures(none) [[FN:%.*]]) { +; CGSCC-SAME: (ptr nofree captures(none) [[FN:%.*]]) { +; CGSCC-NEXT: call void @callee_is_undef() ; CGSCC-NEXT: call void @unknown_calle_arg_is_undef(ptr nofree noundef nonnull captures(none) [[FN]]) ; CGSCC-NEXT: ret void ; @@ -989,9 +989,9 @@ define void @test_callee_is_undef(ptr %fn) { } define internal void @callee_is_undef(ptr %fn) { ; -; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CGSCC: Function Attrs: memory(readwrite, argmem: none) ; CGSCC-LABEL: define {{[^@]+}}@callee_is_undef -; CGSCC-SAME: () #[[ATTR1]] { +; CGSCC-SAME: () #[[ATTR2]] { ; CGSCC-NEXT: unreachable ; call void %fn() @@ -999,10 +999,10 @@ define internal void @callee_is_undef(ptr %fn) { } define internal void @unknown_calle_arg_is_undef(ptr %fn, i32 %arg) { ; -; CHECK-LABEL: define {{[^@]+}}@unknown_calle_arg_is_undef -; CHECK-SAME: (ptr nofree noundef nonnull captures(none) [[FN:%.*]]) { -; CHECK-NEXT: call void [[FN]](i32 undef) -; CHECK-NEXT: ret void +; CGSCC-LABEL: define {{[^@]+}}@unknown_calle_arg_is_undef +; CGSCC-SAME: (ptr nofree noundef nonnull captures(none) [[FN:%.*]]) { +; CGSCC-NEXT: call void [[FN]](i32 undef) +; CGSCC-NEXT: ret void ; call void %fn(i32 %arg) ret void diff --git a/llvm/test/Transforms/CanonicalizeAliases/canonicalize.ll b/llvm/test/Transforms/CanonicalizeAliases/canonicalize.ll index f3f8898737ec7..097c3efd5dab3 100644 --- a/llvm/test/Transforms/CanonicalizeAliases/canonicalize.ll +++ b/llvm/test/Transforms/CanonicalizeAliases/canonicalize.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -passes=canonicalize-aliases < %s | FileCheck %s -; RUN: opt -passes='thinlto-pre-link,require' -o - < %s | llvm-dis -o - | FileCheck %s +; RUN: opt -S -passes=canonicalize-aliases < %s | FileCheck %s +; RUN: opt -passes='thinlto-pre-link,require' -o - < %s | llvm-dis -o - | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/EarlyCSE/PowerPC/read-reg.ll b/llvm/test/Transforms/EarlyCSE/PowerPC/read-reg.ll index 757fd988d60b5..70277c80151fb 100644 --- a/llvm/test/Transforms/EarlyCSE/PowerPC/read-reg.ll +++ b/llvm/test/Transforms/EarlyCSE/PowerPC/read-reg.ll @@ -7,7 +7,7 @@ target triple = "powerpc64-unknown-linux-gnu" define i64 @f(i64 %x) #0 { entry: %0 = call i64 @llvm.read_register.i64(metadata !0) - call void @foo() + call void bitcast (void (...)* @foo to void ()*)() %1 = call i64 @llvm.read_register.i64(metadata !0) %add = add nsw i64 %0, %1 ret i64 %add diff --git a/llvm/test/Transforms/FunctionImport/cg_profile.ll b/llvm/test/Transforms/FunctionImport/cg_profile.ll index f84b4ea9482af..54cccb56ad12e 100644 --- a/llvm/test/Transforms/FunctionImport/cg_profile.ll +++ b/llvm/test/Transforms/FunctionImport/cg_profile.ll @@ -1,10 +1,10 @@ ; Check that bitcast in "CG Profile" related metadata nodes (in this test case, ; generated during function importing in IRMover's RAUW operations) are accepted ; by verifier. -; RUN: opt -passes=cg-profile -module-summary %s -o %t.bc -; RUN: opt -module-summary %p/Inputs/cg_profile.ll -o %t2.bc -; RUN: llvm-lto -thinlto -o %t3 %t.bc %t2.bc -; RUN: opt -passes=function-import -print-imports -summary-file %t3.thinlto.bc %t.bc \ +; RUN: opt -passes=cg-profile -module-summary %s -o %t.bc +; RUN: opt -module-summary %p/Inputs/cg_profile.ll -o %t2.bc +; RUN: llvm-lto -thinlto -o %t3 %t.bc %t2.bc +; RUN: opt -passes=function-import -print-imports -summary-file %t3.thinlto.bc %t.bc \ ; RUN: -S 2>&1 | FileCheck %s ; CHECK: !0 = !{i32 1, !"EnableSplitLTOUnit", i32 0} diff --git a/llvm/test/Transforms/FunctionImport/inlineasm.ll b/llvm/test/Transforms/FunctionImport/inlineasm.ll index 39c384d122969..eb6f57d912fb8 100644 --- a/llvm/test/Transforms/FunctionImport/inlineasm.ll +++ b/llvm/test/Transforms/FunctionImport/inlineasm.ll @@ -1,12 +1,12 @@ ; Do setup work for all below tests: generate bitcode and combined index -; RUN: opt -module-summary %s -o %t.bc -; RUN: opt -module-summary %p/Inputs/inlineasm.ll -o %t2.bc -; RUN: llvm-lto -thinlto -o %t3 %t.bc %t2.bc +; RUN: opt -module-summary %s -o %t.bc +; RUN: opt -module-summary %p/Inputs/inlineasm.ll -o %t2.bc +; RUN: llvm-lto -thinlto -o %t3 %t.bc %t2.bc ; Attempt the import now, ensure below that file containing inline assembly ; is not imported from. Otherwise we would need to promote its local variable ; used in the inline assembly, which would not see the rename. -; RUN: opt -passes=function-import -summary-file %t3.thinlto.bc %t.bc -S 2>&1 | FileCheck %s +; RUN: opt -passes=function-import -summary-file %t3.thinlto.bc %t.bc -S 2>&1 | FileCheck %s define i32 @main() #0 { entry: diff --git a/llvm/test/Transforms/FunctionImport/noinline.ll b/llvm/test/Transforms/FunctionImport/noinline.ll index 8687f1b3b5f7c..512e1106cdf0e 100644 --- a/llvm/test/Transforms/FunctionImport/noinline.ll +++ b/llvm/test/Transforms/FunctionImport/noinline.ll @@ -1,14 +1,14 @@ ; Do setup work for all below tests: generate bitcode and combined index -; RUN: opt -module-summary %s -o %t.main.bc -; RUN: opt -module-summary %p/Inputs/noinline.ll -o %t.inputs.noinline.bc -; RUN: llvm-lto -thinlto -o %t.summary %t.main.bc %t.inputs.noinline.bc +; RUN: opt -module-summary %s -o %t.main.bc +; RUN: opt -module-summary %p/Inputs/noinline.ll -o %t.inputs.noinline.bc +; RUN: llvm-lto -thinlto -o %t.summary %t.main.bc %t.inputs.noinline.bc ; Attempt the import now, ensure below that file containing noinline ; is not imported by default but imported with -force-import-all. -; RUN: opt -passes=function-import -summary-file %t.summary.thinlto.bc %t.main.bc -S 2>&1 \ +; RUN: opt -passes=function-import -summary-file %t.summary.thinlto.bc %t.main.bc -S 2>&1 \ ; RUN: | FileCheck -check-prefix=NOIMPORT %s -; RUN: opt -passes=function-import -force-import-all -summary-file %t.summary.thinlto.bc \ +; RUN: opt -passes=function-import -force-import-all -summary-file %t.summary.thinlto.bc \ ; RUN: %t.main.bc -S 2>&1 | FileCheck -check-prefix=IMPORT %s define i32 @main() #0 { diff --git a/llvm/test/Transforms/GlobalOpt/deadglobal-diarglist-use.ll b/llvm/test/Transforms/GlobalOpt/deadglobal-diarglist-use.ll index b10a3778cf440..0f566e5fec8d8 100644 --- a/llvm/test/Transforms/GlobalOpt/deadglobal-diarglist-use.ll +++ b/llvm/test/Transforms/GlobalOpt/deadglobal-diarglist-use.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -passes=globalopt -S | llvm-as | llvm-dis | FileCheck %s +; RUN: opt < %s -passes=globalopt -S | llvm-as | llvm-dis | FileCheck %s ; The %struct.S type would not get emitted after @s was removed, resulting in ; llvm-as failing to parse the dbg.value intrinsic using that type. However, diff --git a/llvm/test/Transforms/IndVarSimplify/deterministic-sign.ll b/llvm/test/Transforms/IndVarSimplify/deterministic-sign.ll index 1daaccd4bb5f4..103b22c69ad3c 100644 --- a/llvm/test/Transforms/IndVarSimplify/deterministic-sign.ll +++ b/llvm/test/Transforms/IndVarSimplify/deterministic-sign.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt "-passes=loop-rotate,indvars" -S < %s | FileCheck %s -; RUN: opt "-passes=loop-rotate" < %s | opt "-passes=indvars" -S - | FileCheck %s +; RUN: opt "-passes=loop-rotate,indvars" -S < %s | FileCheck %s +; RUN: opt "-passes=loop-rotate" < %s | opt "-passes=indvars" -S - | FileCheck %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/diop-diexpression.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/diop-diexpression.ll new file mode 100644 index 0000000000000..012c7a60779cb --- /dev/null +++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/diop-diexpression.ll @@ -0,0 +1,121 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -passes=infer-address-spaces < %s | FileCheck %s + +define void @test_glob(ptr addrspace(1) %global) !dbg !3 { +; CHECK-LABEL: @test_glob( +; CHECK-NEXT: [[USE_GLOB_GEN:%.*]] = load i32, ptr addrspace(1) [[GLOBAL:%.*]], align 4 +; CHECK-NEXT: #dbg_value(ptr addrspace(1) [[GLOBAL]], [[META6:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(1)), DIOpConvert(ptr)), [[META8:![0-9]+]]) +; CHECK-NEXT: #dbg_value(ptr addrspace(1) [[GLOBAL]], [[META9:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(1)), DIOpConvert(ptr), DIOpDeref(i32)), [[META8]]) +; CHECK-NEXT: #dbg_value(ptr addrspace(1) [[GLOBAL]], [[META11:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(1)), DIOpConvert(ptr), DIOpReinterpret(i64)), [[META8]]) +; CHECK-NEXT: ret void, !dbg [[META8]] +; + %glob_gen = addrspacecast ptr addrspace(1) %global to ptr + %use_glob_gen = load i32, ptr %glob_gen, align 4 + #dbg_value(ptr %glob_gen, !6, !DIExpression(DIOpArg(0, ptr)), !8) + #dbg_value(ptr %glob_gen, !9, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), !8) + #dbg_value(ptr %glob_gen, !11, !DIExpression(DIOpArg(0, ptr), DIOpReinterpret(i64)), !8) + ret void, !dbg !8 +} + +define void @test_local(ptr addrspace(3) %local) !dbg !13 { +; CHECK-LABEL: @test_local( +; CHECK-NEXT: [[USE_LOC_GEN:%.*]] = load i32, ptr addrspace(3) [[LOCAL:%.*]], align 4 +; CHECK-NEXT: #dbg_value(ptr addrspace(3) [[LOCAL]], [[META14:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpConvert(ptr)), [[META15:![0-9]+]]) +; CHECK-NEXT: #dbg_value(ptr addrspace(3) [[LOCAL]], [[META16:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpConvert(ptr), DIOpDeref(i32)), [[META15]]) +; CHECK-NEXT: #dbg_value(ptr addrspace(3) [[LOCAL]], [[META17:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(3)), DIOpConvert(ptr), DIOpReinterpret(i64)), [[META15]]) +; CHECK-NEXT: ret void +; + %loc_gen = addrspacecast ptr addrspace(3) %local to ptr + %use_loc_gen = load i32, ptr %loc_gen, align 4 + #dbg_value(ptr %loc_gen, !14, !DIExpression(DIOpArg(0, ptr)), !15) + #dbg_value(ptr %loc_gen, !16, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), !15) + #dbg_value(ptr %loc_gen, !17, !DIExpression(DIOpArg(0, ptr), DIOpReinterpret(i64)), !15) + ret void +} + +define void @test_constant(ptr addrspace(4) %constant) !dbg !18 { +; CHECK-LABEL: @test_constant( +; CHECK-NEXT: [[USE_CONST_GEN:%.*]] = load i32, ptr addrspace(4) [[CONSTANT:%.*]], align 4 +; CHECK-NEXT: #dbg_value(ptr addrspace(4) [[CONSTANT]], [[META19:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(4)), DIOpConvert(ptr)), [[META20:![0-9]+]]) +; CHECK-NEXT: #dbg_value(ptr addrspace(4) [[CONSTANT]], [[META21:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(4)), DIOpConvert(ptr), DIOpDeref(i32)), [[META20]]) +; CHECK-NEXT: #dbg_value(ptr addrspace(4) [[CONSTANT]], [[META22:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(4)), DIOpConvert(ptr), DIOpReinterpret(i64)), [[META20]]) +; CHECK-NEXT: ret void +; + %const_gen = addrspacecast ptr addrspace(4) %constant to ptr + %use_const_gen = load i32, ptr %const_gen, align 4 + #dbg_value(ptr %const_gen, !19, !DIExpression(DIOpArg(0, ptr)), !20) + #dbg_value(ptr %const_gen, !21, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), !20) + #dbg_value(ptr %const_gen, !22, !DIExpression(DIOpArg(0, ptr), DIOpReinterpret(i64)), !20) + ret void +} + +; Verify that we can update the address space regardless of whether the new +; instruction gets inserted before or after the old one. +define void @test_before_and_after(ptr addrspace(4) %constant) !dbg !23 { +; CHECK-LABEL: @test_before_and_after( +; CHECK-NEXT: [[TMP1:%.*]] = call ptr addrspace(4) @llvm.ptrmask.p4.i64(ptr addrspace(4) [[CONSTANT:%.*]], i64 -2) +; CHECK-NEXT: #dbg_value(ptr addrspace(4) [[TMP1]], [[META24:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(4)), DIOpConvert(ptr)), [[META25:![0-9]+]]) +; CHECK-NEXT: [[USE_MASK:%.*]] = load i32, ptr addrspace(4) [[TMP1]], align 4 +; CHECK-NEXT: [[BC:%.*]] = getelementptr i32, ptr addrspace(4) [[CONSTANT]], i32 42 +; CHECK-NEXT: #dbg_value(ptr addrspace(4) [[BC]], [[META26:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(4)), DIOpConvert(ptr)), [[META25]]) +; CHECK-NEXT: [[USE_BC:%.*]] = load i32, ptr addrspace(4) [[BC]], align 4 +; CHECK-NEXT: ret void +; + %const_gen = addrspacecast ptr addrspace(4) %constant to ptr + + %mask = call ptr @llvm.ptrmask.p0.i64(ptr %const_gen, i64 -2) + #dbg_value(ptr %mask, !24, !DIExpression(DIOpArg(0, ptr)), !26) + %use_mask = load i32, ptr %mask, align 4 + + %bc = getelementptr i32, ptr %const_gen, i32 42 + #dbg_value(ptr %bc, !25, !DIExpression(DIOpArg(0, ptr)), !26) + %use_bc = load i32, ptr %bc, align 4 + + ret void +} + +define void @test_no_DW_OPs(ptr addrspace(3) %local_ptr) !dbg !27 { +; CHECK-LABEL: @test_no_DW_OPs( +; CHECK-NEXT: #dbg_value(ptr poison, [[META28:![0-9]+]], !DIExpression(), [[META29:![0-9]+]]) +; CHECK-NEXT: [[USE_GEN:%.*]] = load i32, ptr addrspace(3) [[LOCAL_PTR:%.*]], align 4 +; CHECK-NEXT: ret void +; + %gen = addrspacecast ptr addrspace(3) %local_ptr to ptr + #dbg_value(ptr %gen, !28, !DIExpression(), !29) + %use_gen = load i32, ptr %gen, align 4 + ret void +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2} + +!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) +!1 = !DIFile(filename: "t.c", directory: "/") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = distinct !DISubprogram(name: "test_glob", linkageName: "test_glob", scope: null, file: !1, line: 1, type: !4, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0) +!4 = !DISubroutineType(types: !5) +!5 = !{} +!6 = !DILocalVariable(name: "ptr_var", scope: !3, file: !1, line: 1, type: !7) +!7 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 64) +!8 = !DILocation(line: 1, column: 1, scope: !3) +!9 = !DILocalVariable(name: "i32_var", scope: !3, file: !1, line: 2, type: !10) +!10 = !DIBasicType(name: "i32", size: 32, encoding: DW_ATE_signed) +!11 = !DILocalVariable(name: "i64_var", scope: !3, file: !1, line: 2, type: !12) +!12 = !DIBasicType(name: "i64", size: 64, encoding: DW_ATE_unsigned) +!13 = distinct !DISubprogram(name: "test_local", linkageName: "test_local", scope: null, file: !1, line: 1, type: !4, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0) +!14 = !DILocalVariable(name: "ptr_var", scope: !13, file: !1, line: 1, type: !7) +!15 = !DILocation(line: 1, column: 1, scope: !13) +!16 = !DILocalVariable(name: "i32_var", scope: !13, file: !1, line: 2, type: !10) +!17 = !DILocalVariable(name: "i64_var", scope: !13, file: !1, line: 2, type: !12) +!18 = distinct !DISubprogram(name: "test_constant", linkageName: "test_constant", scope: null, file: !1, line: 1, type: !4, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0) +!19 = !DILocalVariable(name: "ptr_var", scope: !18, file: !1, line: 1, type: !7) +!20 = !DILocation(line: 1, column: 1, scope: !18) +!21 = !DILocalVariable(name: "i32_var", scope: !18, file: !1, line: 2, type: !10) +!22 = !DILocalVariable(name: "i64_var", scope: !18, file: !1, line: 2, type: !12) +!23 = distinct !DISubprogram(name: "test_before_and_after", linkageName: "test_before_and_after", scope: null, file: !1, line: 1, type: !4, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0) +!24 = !DILocalVariable(name: "p1", scope: !23, file: !1, line: 1, type: !7) +!25 = !DILocalVariable(name: "p2", scope: !23, file: !1, line: 1, type: !7) +!26 = !DILocation(line: 1, column: 1, scope: !23) +!27 = distinct !DISubprogram(name: "test_no_DW_OPs", linkageName: "test_no_DW_OPs", scope: null, file: !1, line: 1, type: !4, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0) +!28 = !DILocalVariable(name: "t1", scope: !27, file: !1, line: 1, type: !7) +!29 = !DILocation(line: 1, column: 1, scope: !27) diff --git a/llvm/test/Transforms/Inline/always-inline-phase-ordering.ll b/llvm/test/Transforms/Inline/always-inline-phase-ordering.ll index defd1f4fd426b..f4e11dad0ad2e 100644 --- a/llvm/test/Transforms/Inline/always-inline-phase-ordering.ll +++ b/llvm/test/Transforms/Inline/always-inline-phase-ordering.ll @@ -2,13 +2,13 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target triple = "arm64e-apple-macosx13" -; CHECK: remark: :0:0: 'wibble' inlined into 'bar.8' with (cost=always): always inline attribute -; CHECK: remark: :0:0: 'wibble' inlined into 'pluto' with (cost=always): always inline attribute -; CHECK: remark: :0:0: 'snork' inlined into 'blam' with (cost=always): always inline attribute -; CHECK: remark: :0:0: 'wobble' inlined into 'blam' with (cost=always): always inline attribute -; CHECK: remark: :0:0: 'spam' inlined into 'blam' with (cost=65, threshold=75) +; CHECK: remark: :0:0: 'wobble' inlined into 'snork': always inline attribute +; CHECK: remark: :0:0: 'spam' inlined into 'snork' with (cost=65, threshold=75) +; CHECK: remark: :0:0: 'snork' inlined into 'blam': always inline attribute ; CHECK: remark: :0:0: 'wibble.1' inlined into 'widget' with (cost=30, threshold=75) -; CHECK: remark: :0:0: 'widget' inlined into 'bar.8' with (cost=30, threshold=75) +; CHECK: remark: :0:0: 'widget' inlined into 'wibble' with (cost=30, threshold=75) +; CHECK: remark: :0:0: 'wibble' inlined into 'bar.8': always inline attribute +; CHECK: remark: :0:0: 'wibble' inlined into 'pluto': always inline attribute ; CHECK: remark: :0:0: 'barney' inlined into 'wombat' with (cost=30, threshold=75) define linkonce_odr void @wombat(ptr %arg) #0 { diff --git a/llvm/test/Transforms/InstCombine/cast-mul-select.ll b/llvm/test/Transforms/InstCombine/cast-mul-select.ll index 8aa768cbaede5..b2940d0ca1d0a 100644 --- a/llvm/test/Transforms/InstCombine/cast-mul-select.ll +++ b/llvm/test/Transforms/InstCombine/cast-mul-select.ll @@ -2,6 +2,7 @@ ; RUN: opt < %s -passes=instcombine -S | FileCheck %s ; RUN: opt -passes=debugify,instcombine -S < %s | FileCheck %s -check-prefix DBGINFO +; RUN: opt -passes=debugify,instcombine --debugify-diop-diexprs -S < %s | FileCheck %s -check-prefix DIOP-DBGINFO target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32" @@ -20,6 +21,15 @@ define i32 @mul(i32 %x, i32 %y) { ; DBGINFO-NEXT: #dbg_value(i32 [[D]], [[META13:![0-9]+]], !DIExpression(), [[DBG18]]) ; DBGINFO-NEXT: ret i32 [[D]], !dbg [[DBG19:![0-9]+]] ; +; DIOP-DBGINFO-LABEL: @mul( +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[X:%.*]], [[META9:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpConvert(i8)), [[META15:![0-9]+]]) +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[Y:%.*]], [[META11:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpConvert(i8)), [[META16:![0-9]+]]) +; DIOP-DBGINFO-NEXT: [[C:%.*]] = mul i32 [[X]], [[Y]], !dbg [[DBG17:![0-9]+]] +; DIOP-DBGINFO-NEXT: [[D:%.*]] = and i32 [[C]], 255, !dbg [[DBG18:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[C]], [[META12:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpConvert(i8)), [[DBG17]]) +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[D]], [[META13:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[DBG18]]) +; DIOP-DBGINFO-NEXT: ret i32 [[D]], !dbg [[DBG19:![0-9]+]] +; ; Test that when zext is evaluated in different type ; we preserve the debug information in the resulting @@ -50,6 +60,18 @@ define i32 @select1(i1 %cond, i32 %x, i32 %y, i32 %z) { ; DBGINFO-NEXT: #dbg_value(i32 [[E]], [[META26:![0-9]+]], !DIExpression(), [[DBG32]]) ; DBGINFO-NEXT: #dbg_value(i32 [[F]], [[META27:![0-9]+]], !DIExpression(), [[DBG33]]) ; DBGINFO-NEXT: ret i32 [[F]], !dbg [[DBG34:![0-9]+]] +; +; DIOP-DBGINFO-LABEL: @select1( +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[X:%.*]], [[META22:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpConvert(i8)), [[META28:![0-9]+]]) +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[Y:%.*]], [[META23:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpConvert(i8)), [[META29:![0-9]+]]) +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[Z:%.*]], [[META24:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpConvert(i8)), [[META30:![0-9]+]]) +; DIOP-DBGINFO-NEXT: [[D:%.*]] = add i32 [[X]], [[Y]], !dbg [[DBG31:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(!DIArgList(i32 [[X]], i32 [[Y]]), [[META25:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpConvert(i8), DIOpArg(1, i32), DIOpConvert(i8), DIOpAdd()), [[DBG31]]) +; DIOP-DBGINFO-NEXT: [[E:%.*]] = select i1 [[COND:%.*]], i32 [[Z]], i32 [[D]], !dbg [[DBG32:![0-9]+]] +; DIOP-DBGINFO-NEXT: [[F:%.*]] = and i32 [[E]], 255, !dbg [[DBG33:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[E]], [[META26:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpConvert(i8)), [[DBG32]]) +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[F]], [[META27:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[DBG33]]) +; DIOP-DBGINFO-NEXT: ret i32 [[F]], !dbg [[DBG34:![0-9]+]] ; %A = trunc i32 %x to i8 %B = trunc i32 %y to i8 @@ -76,6 +98,17 @@ define i8 @select2(i1 %cond, i8 %x, i8 %y, i8 %z) { ; DBGINFO-NEXT: [[F:%.*]] = select i1 [[COND:%.*]], i8 [[Z]], i8 [[D]], !dbg [[META47]] ; DBGINFO-NEXT: #dbg_value(i8 [[F]], [[META42:![0-9]+]], !DIExpression(), [[META48:![0-9]+]]) ; DBGINFO-NEXT: ret i8 [[F]], !dbg [[DBG49:![0-9]+]] +; +; DIOP-DBGINFO-LABEL: @select2( +; DIOP-DBGINFO-NEXT: #dbg_value(i8 [[X:%.*]], [[META37:![0-9]+]], !DIExpression(DIOpArg(0, i8), DIOpZExt(i32)), [[META43:![0-9]+]]) +; DIOP-DBGINFO-NEXT: #dbg_value(i8 [[Y:%.*]], [[META38:![0-9]+]], !DIExpression(DIOpArg(0, i8), DIOpZExt(i32)), [[META44:![0-9]+]]) +; DIOP-DBGINFO-NEXT: #dbg_value(i8 [[Z:%.*]], [[META39:![0-9]+]], !DIExpression(DIOpArg(0, i8), DIOpZExt(i32)), [[META45:![0-9]+]]) +; DIOP-DBGINFO-NEXT: [[D:%.*]] = add i8 [[X]], [[Y]], !dbg [[DBG46:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(!DIArgList(i8 [[X]], i8 [[Y]]), [[META40:![0-9]+]], !DIExpression(DIOpArg(0, i8), DIOpZExt(i32), DIOpArg(1, i8), DIOpZExt(i32), DIOpAdd()), [[DBG46]]) +; DIOP-DBGINFO-NEXT: #dbg_value(i32 poison, [[META41:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[META47:![0-9]+]]) +; DIOP-DBGINFO-NEXT: [[F:%.*]] = select i1 [[COND:%.*]], i8 [[Z]], i8 [[D]], !dbg [[META47]] +; DIOP-DBGINFO-NEXT: #dbg_value(i8 [[F]], [[META42:![0-9]+]], !DIExpression(DIOpArg(0, i8)), [[META48:![0-9]+]]) +; DIOP-DBGINFO-NEXT: ret i8 [[F]], !dbg [[DBG49:![0-9]+]] ; %A = zext i8 %x to i32 %B = zext i8 %y to i32 @@ -107,6 +140,17 @@ define i32 @eval_trunc_multi_use_in_one_inst(i32 %x) { ; DBGINFO-NEXT: [[T:%.*]] = trunc i64 [[M]] to i32, !dbg [[DBG60:![0-9]+]] ; DBGINFO-NEXT: #dbg_value(i32 [[T]], [[META56:![0-9]+]], !DIExpression(), [[DBG60]]) ; DBGINFO-NEXT: ret i32 [[T]], !dbg [[DBG61:![0-9]+]] +; +; DIOP-DBGINFO-LABEL: @eval_trunc_multi_use_in_one_inst( +; DIOP-DBGINFO-NEXT: [[Z:%.*]] = zext i32 [[X:%.*]] to i64, !dbg [[DBG57:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i64 [[Z]], [[META52:![0-9]+]], !DIExpression(DIOpArg(0, i64)), [[DBG57]]) +; DIOP-DBGINFO-NEXT: [[A:%.*]] = add nuw nsw i64 [[Z]], 15, !dbg [[DBG58:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i64 [[A]], [[META54:![0-9]+]], !DIExpression(DIOpArg(0, i64)), [[DBG58]]) +; DIOP-DBGINFO-NEXT: [[M:%.*]] = mul i64 [[A]], [[A]], !dbg [[DBG59:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i64 [[M]], [[META55:![0-9]+]], !DIExpression(DIOpArg(0, i64)), [[DBG59]]) +; DIOP-DBGINFO-NEXT: [[T:%.*]] = trunc i64 [[M]] to i32, !dbg [[DBG60:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[T]], [[META56:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[DBG60]]) +; DIOP-DBGINFO-NEXT: ret i32 [[T]], !dbg [[DBG61:![0-9]+]] ; %z = zext i32 %x to i64 %a = add nsw nuw i64 %z, 15 @@ -133,6 +177,17 @@ define i32 @eval_zext_multi_use_in_one_inst(i32 %x) { ; DBGINFO-NEXT: [[R:%.*]] = zext nneg i16 [[M]] to i32, !dbg [[DBG72:![0-9]+]] ; DBGINFO-NEXT: #dbg_value(i32 [[R]], [[META68:![0-9]+]], !DIExpression(), [[DBG72]]) ; DBGINFO-NEXT: ret i32 [[R]], !dbg [[DBG73:![0-9]+]] +; +; DIOP-DBGINFO-LABEL: @eval_zext_multi_use_in_one_inst( +; DIOP-DBGINFO-NEXT: [[T:%.*]] = trunc i32 [[X:%.*]] to i16, !dbg [[DBG69:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i16 [[T]], [[META64:![0-9]+]], !DIExpression(DIOpArg(0, i16)), [[DBG69]]) +; DIOP-DBGINFO-NEXT: [[A:%.*]] = and i16 [[T]], 5, !dbg [[DBG70:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i16 [[A]], [[META66:![0-9]+]], !DIExpression(DIOpArg(0, i16)), [[DBG70]]) +; DIOP-DBGINFO-NEXT: [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]], !dbg [[DBG71:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i16 [[M]], [[META67:![0-9]+]], !DIExpression(DIOpArg(0, i16)), [[DBG71]]) +; DIOP-DBGINFO-NEXT: [[R:%.*]] = zext nneg i16 [[M]] to i32, !dbg [[DBG72:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[R]], [[META68:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[DBG72]]) +; DIOP-DBGINFO-NEXT: ret i32 [[R]], !dbg [[DBG73:![0-9]+]] ; %t = trunc i32 %x to i16 %a = and i16 %t, 5 @@ -162,6 +217,19 @@ define i32 @eval_sext_multi_use_in_one_inst(i32 %x) { ; DBGINFO-NEXT: [[R:%.*]] = sext i16 [[O]] to i32, !dbg [[DBG85:![0-9]+]] ; DBGINFO-NEXT: #dbg_value(i32 [[R]], [[META80:![0-9]+]], !DIExpression(), [[DBG85]]) ; DBGINFO-NEXT: ret i32 [[R]], !dbg [[DBG86:![0-9]+]] +; +; DIOP-DBGINFO-LABEL: @eval_sext_multi_use_in_one_inst( +; DIOP-DBGINFO-NEXT: [[T:%.*]] = trunc i32 [[X:%.*]] to i16, !dbg [[DBG81:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i16 [[T]], [[META76:![0-9]+]], !DIExpression(DIOpArg(0, i16)), [[DBG81]]) +; DIOP-DBGINFO-NEXT: [[A:%.*]] = and i16 [[T]], 14, !dbg [[DBG82:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i16 [[A]], [[META77:![0-9]+]], !DIExpression(DIOpArg(0, i16)), [[DBG82]]) +; DIOP-DBGINFO-NEXT: [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]], !dbg [[DBG83:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i16 [[M]], [[META78:![0-9]+]], !DIExpression(DIOpArg(0, i16)), [[DBG83]]) +; DIOP-DBGINFO-NEXT: [[O:%.*]] = or disjoint i16 [[M]], -32768, !dbg [[DBG84:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i16 [[O]], [[META79:![0-9]+]], !DIExpression(DIOpArg(0, i16)), [[DBG84]]) +; DIOP-DBGINFO-NEXT: [[R:%.*]] = sext i16 [[O]] to i32, !dbg [[DBG85:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[R]], [[META80:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[DBG85]]) +; DIOP-DBGINFO-NEXT: ret i32 [[R]], !dbg [[DBG86:![0-9]+]] ; %t = trunc i32 %x to i16 %a = and i16 %t, 14 @@ -235,6 +303,39 @@ define void @PR36225(i32 %a, i32 %b, i1 %c1, i3 %v1, i3 %v2) { ; DBGINFO: exit: ; DBGINFO-NEXT: unreachable, !dbg [[DBG105:![0-9]+]] ; +; DIOP-DBGINFO-LABEL: @PR36225( +; DIOP-DBGINFO-NEXT: entry: +; DIOP-DBGINFO-NEXT: br label [[WHILE_BODY:%.*]], !dbg [[DBG94:![0-9]+]] +; DIOP-DBGINFO: while.body: +; DIOP-DBGINFO-NEXT: #dbg_value(i1 poison, [[META89:![0-9]+]], !DIExpression(DIOpArg(0, i1), DIOpZExt(i8)), [[META95:![0-9]+]]) +; DIOP-DBGINFO-NEXT: br i1 [[C1:%.*]], label [[FOR_BODY3_US:%.*]], label [[FOR_BODY3:%.*]], !dbg [[DBG96:![0-9]+]] +; DIOP-DBGINFO: for.body3.us: +; DIOP-DBGINFO-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[B:%.*]], 0, !dbg [[META95]] +; DIOP-DBGINFO-NEXT: #dbg_value(i1 [[TOBOOL]], [[META89]], !DIExpression(DIOpArg(0, i1), DIOpZExt(i8)), [[META95]]) +; DIOP-DBGINFO-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i8 0, i8 4, !dbg [[DBG97:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i8 [[SPEC_SELECT]], [[META90:![0-9]+]], !DIExpression(DIOpArg(0, i8)), [[DBG97]]) +; DIOP-DBGINFO-NEXT: switch i3 [[V1:%.*]], label [[EXIT:%.*]] [ +; DIOP-DBGINFO-NEXT: i3 0, label [[FOR_END:%.*]] +; DIOP-DBGINFO-NEXT: i3 -1, label [[FOR_END]] +; DIOP-DBGINFO-NEXT: ], !dbg [[DBG98:![0-9]+]] +; DIOP-DBGINFO: for.body3: +; DIOP-DBGINFO-NEXT: switch i3 [[V2:%.*]], label [[EXIT]] [ +; DIOP-DBGINFO-NEXT: i3 0, label [[FOR_END]] +; DIOP-DBGINFO-NEXT: i3 -1, label [[FOR_END]] +; DIOP-DBGINFO-NEXT: ], !dbg [[DBG99:![0-9]+]] +; DIOP-DBGINFO: for.end: +; DIOP-DBGINFO-NEXT: [[H:%.*]] = phi i8 [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ 0, [[FOR_BODY3]] ], [ 0, [[FOR_BODY3]] ], !dbg [[DBG100:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i8 [[H]], [[META91:![0-9]+]], !DIExpression(DIOpArg(0, i8)), [[DBG100]]) +; DIOP-DBGINFO-NEXT: [[CONV:%.*]] = zext nneg i8 [[H]] to i32, !dbg [[DBG101:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[CONV]], [[META92:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[DBG101]]) +; DIOP-DBGINFO-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A:%.*]], [[CONV]], !dbg [[DBG102:![0-9]+]] +; DIOP-DBGINFO-NEXT: #dbg_value(i1 [[CMP]], [[META93:![0-9]+]], !DIExpression(DIOpArg(0, i1), DIOpZExt(i8)), [[DBG102]]) +; DIOP-DBGINFO-NEXT: br i1 [[CMP]], label [[EXIT]], label [[EXIT2:%.*]], !dbg [[DBG103:![0-9]+]] +; DIOP-DBGINFO: exit2: +; DIOP-DBGINFO-NEXT: unreachable, !dbg [[DBG104:![0-9]+]] +; DIOP-DBGINFO: exit: +; DIOP-DBGINFO-NEXT: unreachable, !dbg [[DBG105:![0-9]+]] +; entry: br label %while.body @@ -276,6 +377,10 @@ define i1 @foo(i1 zeroext %b) { ; DBGINFO-LABEL: @foo( ; DBGINFO-NEXT: #dbg_value(i1 [[B:%.*]], [[META108:![0-9]+]], !DIExpression(DW_OP_LLVM_convert, 1, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value), [[META109:![0-9]+]]) ; DBGINFO-NEXT: ret i1 [[B]], !dbg [[DBG110:![0-9]+]] +; +; DIOP-DBGINFO-LABEL: @foo( +; DIOP-DBGINFO-NEXT: #dbg_value(i1 [[B:%.*]], [[META108:![0-9]+]], !DIExpression(DIOpArg(0, i1), DIOpZExt(i8)), [[META109:![0-9]+]]) +; DIOP-DBGINFO-NEXT: ret i1 [[B]], !dbg [[DBG110:![0-9]+]] ; %frombool = zext i1 %b to i8 diff --git a/llvm/test/Transforms/InstCombine/debuginfo-variables.ll b/llvm/test/Transforms/InstCombine/debuginfo-variables.ll index 61c385250064c..bcfd6d2eb1e19 100644 --- a/llvm/test/Transforms/InstCombine/debuginfo-variables.ll +++ b/llvm/test/Transforms/InstCombine/debuginfo-variables.ll @@ -1,4 +1,5 @@ ; RUN: opt < %s -passes=debugify,instcombine -S | FileCheck %s +; RUN: opt < %s -passes=debugify,instcombine --debugify-diop-diexprs -S | FileCheck %s --check-prefix DIOP-DBGINFO declare void @escape32(i32) @@ -7,6 +8,11 @@ define i64 @test_sext_zext(i16 %A) { ; CHECK-NEXT: [[C2:%.*]] = zext i16 %A to i64 ; CHECK-NEXT: #dbg_value(i64 [[C2]], {{.*}}, !DIExpression(), ; CHECK-NEXT: #dbg_value(i64 [[C2]], {{.*}}, !DIExpression(), + +; DIOP-DBGINFO-LABEL: @test_sext_zext( +; DIOP-DBGINFO-NEXT: [[C2:%.*]] = zext i16 %A to i64 +; DIOP-DBGINFO-NEXT: #dbg_value(i64 [[C2]], {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConvert(i32)), +; DIOP-DBGINFO-NEXT: #dbg_value(i64 [[C2]], {{.*}}, !DIExpression(DIOpArg(0, i64)), %c1 = zext i16 %A to i32 %c2 = sext i32 %c1 to i64 ret i64 %c2 @@ -20,6 +26,14 @@ define i64 @test_used_sext_zext(i16 %A) { ; CHECK-NEXT: #dbg_value(i64 [[C2]], {{.*}}, !DIExpression(), ; CHECK-NEXT: call void @escape32(i32 %c1) ; CHECK-NEXT: ret i64 %c2 + +; DIOP-DBGINFO-LABEL: @test_used_sext_zext( +; DIOP-DBGINFO-NEXT: [[C1:%.*]] = zext i16 %A to i32 +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[C1]], {{.*}}, !DIExpression(DIOpArg(0, i32)), +; DIOP-DBGINFO-NEXT: [[C2:%.*]] = zext i16 %A to i64 +; DIOP-DBGINFO-NEXT: #dbg_value(i64 [[C2]], {{.*}}, !DIExpression(DIOpArg(0, i64)), +; DIOP-DBGINFO-NEXT: call void @escape32(i32 %c1) +; DIOP-DBGINFO-NEXT: ret i64 %c2 %c1 = zext i16 %A to i32 %c2 = sext i32 %c1 to i64 call void @escape32(i32 %c1) @@ -32,6 +46,12 @@ define i32 @test_cast_select(i1 %cond) { ; CHECK-NEXT: #dbg_value(i32 [[sel]], {{.*}}, !DIExpression(), ; CHECK-NEXT: #dbg_value(i32 [[sel]], {{.*}}, !DIExpression(), ; CHECK-NEXT: ret i32 [[sel]] + +; DIOP-DBGINFO-LABEL: @test_cast_select( +; DIOP-DBGINFO-NEXT: [[sel:%.*]] = select i1 %cond, i32 3, i32 5 +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[sel]], {{.*}}, !DIExpression(DIOpArg(0, i32), DIOpConvert(i16)), +; DIOP-DBGINFO-NEXT: #dbg_value(i32 [[sel]], {{.*}}, !DIExpression(DIOpArg(0, i32)), +; DIOP-DBGINFO-NEXT: ret i32 [[sel]] %sel = select i1 %cond, i16 3, i16 5 %cast = zext i16 %sel to i32 ret i32 %cast @@ -40,6 +60,9 @@ define i32 @test_cast_select(i1 %cond) { define void @test_or(i64 %A) { ; CHECK-LABEL: @test_or( ; CHECK-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DW_OP_constu, 256, DW_OP_or, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_or( +; DIOP-DBGINFO-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConstant(i64 256), DIOpOr()), %1 = or i64 %A, 256 ret void } @@ -47,6 +70,9 @@ define void @test_or(i64 %A) { define void @test_xor(i32 %A) { ; CHECK-LABEL: @test_xor( ; CHECK-NEXT: #dbg_value(i32 %A, {{.*}}, !DIExpression(DW_OP_constu, 1, DW_OP_xor, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_xor( +; DIOP-DBGINFO-NEXT: #dbg_value(i32 %A, {{.*}}, !DIExpression(DIOpArg(0, i32), DIOpConstant(i32 1), DIOpXor()), %1 = xor i32 %A, 1 ret void } @@ -54,6 +80,9 @@ define void @test_xor(i32 %A) { define void @test_sub_neg(i64 %A) { ; CHECK-LABEL: @test_sub_neg( ; CHECK-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_sub_neg( +; DIOP-DBGINFO-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConstant(i64 -1), DIOpSub()), %1 = sub i64 %A, -1 ret void } @@ -61,6 +90,9 @@ define void @test_sub_neg(i64 %A) { define void @test_sub_pos(i64 %A) { ; CHECK-LABEL: @test_sub_pos( ; CHECK-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DW_OP_constu, 1, DW_OP_minus, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_sub_pos( +; DIOP-DBGINFO-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConstant(i64 1), DIOpSub()), %1 = sub i64 %A, 1 ret void } @@ -68,6 +100,9 @@ define void @test_sub_pos(i64 %A) { define void @test_shl(i64 %A) { ; CHECK-LABEL: @test_shl( ; CHECK-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DW_OP_constu, 7, DW_OP_shl, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_shl( +; DIOP-DBGINFO-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConstant(i64 7), DIOpShl()), %1 = shl i64 %A, 7 ret void } @@ -75,6 +110,9 @@ define void @test_shl(i64 %A) { define void @test_lshr(i64 %A) { ; CHECK-LABEL: @test_lshr( ; CHECK-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DW_OP_constu, 7, DW_OP_shr, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_lshr( +; DIOP-DBGINFO-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConstant(i64 7), DIOpLShr()), %1 = lshr i64 %A, 7 ret void } @@ -82,6 +120,9 @@ define void @test_lshr(i64 %A) { define void @test_ashr(i64 %A) { ; CHECK-LABEL: @test_ashr( ; CHECK-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DW_OP_constu, 7, DW_OP_shra, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_ashr( +; DIOP-DBGINFO-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConstant(i64 7), DIOpAShr()), %1 = ashr i64 %A, 7 ret void } @@ -89,6 +130,9 @@ define void @test_ashr(i64 %A) { define void @test_mul(i64 %A) { ; CHECK-LABEL: @test_mul( ; CHECK-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DW_OP_constu, 7, DW_OP_mul, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_mul( +; DIOP-DBGINFO-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConstant(i64 7), DIOpMul()), %1 = mul i64 %A, 7 ret void } @@ -96,6 +140,9 @@ define void @test_mul(i64 %A) { define void @test_sdiv(i64 %A) { ; CHECK-LABEL: @test_sdiv( ; CHECK-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DW_OP_constu, 7, DW_OP_div, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_sdiv( +; DIOP-DBGINFO-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConstant(i64 7), DIOpDiv()), %1 = sdiv i64 %A, 7 ret void } @@ -103,6 +150,9 @@ define void @test_sdiv(i64 %A) { define void @test_srem(i64 %A) { ; CHECK-LABEL: @test_srem( ; CHECK-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DW_OP_constu, 7, DW_OP_mod, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_srem( +; DIOP-DBGINFO-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConstant(i64 7), DIOpMod()), %1 = srem i64 %A, 7 ret void } @@ -110,6 +160,9 @@ define void @test_srem(i64 %A) { define void @test_ptrtoint(ptr %P) { ; CHECK-LABEL: @test_ptrtoint ; CHECK-NEXT: #dbg_value(ptr %P, {{.*}}, !DIExpression(), + +; DIOP-DBGINFO-LABEL: @test_ptrtoint +; DIOP-DBGINFO-NEXT: #dbg_value(ptr %P, {{.*}}, !DIExpression(DIOpArg(0, ptr), DIOpReinterpret(i64)), %1 = ptrtoint ptr %P to i64 ret void } @@ -117,6 +170,34 @@ define void @test_ptrtoint(ptr %P) { define void @test_and(i64 %A) { ; CHECK-LABEL: @test_and( ; CHECK-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DW_OP_constu, 256, DW_OP_and, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_and( +; DIOP-DBGINFO-NEXT: #dbg_value(i64 %A, {{.*}}, !DIExpression(DIOpArg(0, i64), DIOpConstant(i64 256), DIOpAnd()), %1 = and i64 %A, 256 ret void } + +%struct.G = type { [4 x i16] } +%struct.S = type { i32, [10 x %struct.G] } + +define void @test_gep(ptr %A) { +; CHECK-LABEL: @test_gep( +; CHECK-NEXT: #dbg_value(ptr %A, {{.*}}, !DIExpression(DW_OP_plus_uconst, 4, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_gep( +; DIOP-DBGINFO-NEXT: #dbg_value(ptr %A, {{.*}}, !DIExpression(DIOpArg(0, ptr), DIOpReinterpret(i64), DIOpConstant(i64 4), DIOpAdd(), DIOpReinterpret(ptr)), + %1 = getelementptr %struct.S, ptr %A, i32 0, i32 1 + ret void +} + +define void @test_gep_var_offset(ptr %A, i64 %B, i8 %C) { +; CHECK-LABEL: @test_gep_var_offset( +; CHECK-NEXT: #dbg_value(!DIArgList(ptr %A, i64 %B, i8 %C), {{.*}}, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 8, DW_OP_mul, DW_OP_plus, DW_OP_LLVM_arg, 2, DW_OP_constu, 2, DW_OP_mul, DW_OP_plus, DW_OP_plus_uconst, 88, DW_OP_stack_value), + +; DIOP-DBGINFO-LABEL: @test_gep_var_offset( +; DIOP-DBGINFO-NEXT: #dbg_value(!DIArgList(ptr %A, i64 %B, i8 %C), {{.*}}, !DIExpression(DIOpArg(0, ptr), DIOpReinterpret(i64), DIOpArg(1, i64), DIOpConstant(i64 8), DIOpMul(), DIOpAdd(), DIOpArg(2, i8), DIOpSExt(i64), DIOpConstant(i64 2), DIOpMul(), DIOpAdd(), DIOpConstant(i64 88), DIOpAdd(), DIOpReinterpret(ptr)), + + ; This is the following expression in infix: i64(A) + B*8 + C*2 + 88 + %1 = getelementptr %struct.S, ptr %A, i32 1, i32 1, i64 %B, i32 0, i8 %C + ret void +} diff --git a/llvm/test/Transforms/InstCombine/heterogeneous-poison-dbg-rauw.ll b/llvm/test/Transforms/InstCombine/heterogeneous-poison-dbg-rauw.ll new file mode 100644 index 0000000000000..4b6f36b9a21a6 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/heterogeneous-poison-dbg-rauw.ll @@ -0,0 +1,191 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=instcombine -S | FileCheck %s + +;; Test replaceAllDbgUsesWith(). InstCombine uses this function when there is a +;; cast of a cast it can eliminate (see InstCombinerImpl::commonCastTransforms). + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +declare void @use_i32(i32) +declare void @use_i64(i32) +declare void @use_ptr(ptr) +declare void @use_ptr1(ptr addrspace(1)) +declare void @llvm.dbg.value(metadata, metadata, metadata) #0 + +define void @test_int_ptr_int(i64 %A) !dbg !5 { +; CHECK-LABEL: define void @test_int_ptr_int( +; CHECK-SAME: i64 [[A:%.*]]) !dbg [[DBG5:![0-9]+]] { +; CHECK-NEXT: #dbg_value(i64 [[A]], [[META9:![0-9]+]], !DIExpression(DIOpArg(0, i64), DIOpReinterpret(ptr)), [[META12:![0-9]+]]) +; CHECK-NEXT: call void @use_i64(i64 [[A]]) +; CHECK-NEXT: ret void +; + %1 = inttoptr i64 %A to ptr + #dbg_value(ptr %1, !9, !DIExpression(DIOpArg(0, ptr)), !12) + %2 = ptrtoint ptr %1 to i64 + call void @use_i64(i64 %2) + ret void +} + +define void @test_ptr_int_ptr(ptr %A) !dbg !13 { +; CHECK-LABEL: define void @test_ptr_int_ptr( +; CHECK-SAME: ptr [[A:%.*]]) !dbg [[DBG13:![0-9]+]] { +; CHECK-NEXT: #dbg_value(ptr [[A]], [[META15:![0-9]+]], !DIExpression(DIOpArg(0, ptr), DIOpReinterpret(i64)), [[META17:![0-9]+]]) +; CHECK-NEXT: call void @use_ptr(ptr [[A]]) +; CHECK-NEXT: ret void +; + %1 = ptrtoint ptr %A to i64 + #dbg_value(i64 %1, !15, !DIExpression(DIOpArg(0, i64)), !17) + %2 = inttoptr i64 %1 to ptr + call void @use_ptr(ptr %2) + ret void +} + +define void @test_zext_trunc(i32 %A) !dbg !18 { +; CHECK-LABEL: define void @test_zext_trunc( +; CHECK-SAME: i32 [[A:%.*]]) !dbg [[DBG18:![0-9]+]] { +; CHECK-NEXT: #dbg_value(i32 [[A]], [[META20:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpZExt(i64)), [[META23:![0-9]+]]) +; CHECK-NEXT: call void @use_i32(i32 [[A]]) +; CHECK-NEXT: ret void +; + %1 = zext i32 %A to i64 + #dbg_value(i64 %1, !20, !DIExpression(DIOpArg(0, i64)), !23) + %2 = trunc i64 %1 to i32 + call void @use_i32(i32 %2) + ret void +} + +define void @test_trunc_zext(i64 %A) !dbg !24 { +; CHECK-LABEL: define void @test_trunc_zext( +; CHECK-SAME: i64 [[A:%.*]]) !dbg [[DBG24:![0-9]+]] { +; CHECK-NEXT: #dbg_value(i64 [[A]], [[META26:![0-9]+]], !DIExpression(DIOpArg(0, i64), DIOpConvert(i32)), [[META28:![0-9]+]]) +; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[A]], 4294967295 +; CHECK-NEXT: call void @use_i64(i64 [[TMP1]]) +; CHECK-NEXT: ret void +; + %1 = trunc i64 %A to i32 + #dbg_value(i32 %1, !26, !DIExpression(DIOpArg(0, i32)), !28) + %2 = zext i32 %1 to i64 + call void @use_i64(i64 %2) + ret void +} + +define void @test_sext_trunc(i32 %A) !dbg !29 { +; CHECK-LABEL: define void @test_sext_trunc( +; CHECK-SAME: i32 [[A:%.*]]) !dbg [[DBG29:![0-9]+]] { +; CHECK-NEXT: #dbg_value(i32 [[A]], [[META31:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpSExt(i64)), [[META33:![0-9]+]]) +; CHECK-NEXT: call void @use_i32(i32 [[A]]) +; CHECK-NEXT: ret void +; + %1 = sext i32 %A to i64 + #dbg_value(i64 %1, !31, !DIExpression(DIOpArg(0, i64)), !33) + %2 = trunc i64 %1 to i32 + call void @use_i32(i32 %2) + ret void +} + +define void @test_asc_asc(ptr addrspace(1) %A, ptr %B) !dbg !34 { +; CHECK-LABEL: define void @test_asc_asc( +; CHECK-SAME: ptr addrspace(1) [[A:%.*]], ptr [[B:%.*]]) !dbg [[DBG34:![0-9]+]] { +; CHECK-NEXT: #dbg_value(ptr addrspace(4) poison, [[META36:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(4))), [[META38:![0-9]+]]) +; CHECK-NEXT: call void @use_ptr1(ptr addrspace(1) [[A]]) +; CHECK-NEXT: #dbg_value(ptr addrspace(3) poison, [[META39:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(3))), [[META38]]) +; CHECK-NEXT: call void @use_ptr(ptr [[B]]) +; CHECK-NEXT: ret void +; + %1 = addrspacecast ptr addrspace(1) %A to ptr addrspace(4) + #dbg_value(ptr addrspace(4) %1, !36, !DIExpression(DIOpArg(0, ptr addrspace(4))), !38) + %2 = addrspacecast ptr addrspace(4) %1 to ptr addrspace(1) + call void @use_ptr1(ptr addrspace(1) %2) + + %3 = addrspacecast ptr %B to ptr addrspace(3) + #dbg_value(ptr addrspace(3) %3, !39, !DIExpression(DIOpArg(0, ptr addrspace(3))), !38) + %4 = addrspacecast ptr addrspace(3) %3 to ptr + call void @use_ptr(ptr %4) + + ret void +} + +!llvm.dbg.cu = !{!0} +!llvm.debugify = !{!2, !3} +!llvm.module.flags = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) +!1 = !DIFile(filename: "t.c", directory: "/") +!2 = !{i32 16} +!3 = !{i32 8} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = distinct !DISubprogram(name: "test_int_ptr_int", linkageName: "test_int_ptr_int", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) +!6 = !DISubroutineType(types: !7) +!7 = !{} +!8 = !{!9, !11} +!9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !10) +!10 = !DIBasicType(name: "ty64", size: 64, encoding: DW_ATE_unsigned) +!11 = !DILocalVariable(name: "2", scope: !5, file: !1, line: 2, type: !10) +!12 = !DILocation(line: 1, column: 1, scope: !5) +!13 = distinct !DISubprogram(name: "test_ptr_int_ptr", linkageName: "test_ptr_int_ptr", scope: null, file: !1, line: 5, type: !6, scopeLine: 5, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !14) +!14 = !{!15, !16} +!15 = !DILocalVariable(name: "3", scope: !13, file: !1, line: 5, type: !10) +!16 = !DILocalVariable(name: "4", scope: !13, file: !1, line: 6, type: !10) +!17 = !DILocation(line: 5, column: 1, scope: !13) +!18 = distinct !DISubprogram(name: "test_zext_trunc", linkageName: "test_zext_trunc", scope: null, file: !1, line: 9, type: !6, scopeLine: 9, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !19) +!19 = !{!20, !21} +!20 = !DILocalVariable(name: "5", scope: !18, file: !1, line: 9, type: !10) +!21 = !DILocalVariable(name: "6", scope: !18, file: !1, line: 10, type: !22) +!22 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned) +!23 = !DILocation(line: 9, column: 1, scope: !18) +!24 = distinct !DISubprogram(name: "test_trunc_zext", linkageName: "test_trunc_zext", scope: null, file: !1, line: 13, type: !6, scopeLine: 13, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !25) +!25 = !{!26, !27} +!26 = !DILocalVariable(name: "7", scope: !24, file: !1, line: 13, type: !22) +!27 = !DILocalVariable(name: "8", scope: !24, file: !1, line: 14, type: !10) +!28 = !DILocation(line: 13, column: 1, scope: !24) +!29 = distinct !DISubprogram(name: "test_sext_trunc", linkageName: "test_sext_trunc", scope: null, file: !1, line: 13, type: !6, scopeLine: 13, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !30) +!30 = !{!31} +!31 = !DILocalVariable(name: "9", scope: !29, file: !1, line: 13, type: !32) +!32 = !DIBasicType(name: "tys32", size: 32, encoding: DW_ATE_signed) +!33 = !DILocation(line: 13, column: 1, scope: !29) +!34 = distinct !DISubprogram(name: "test_asc_asc", linkageName: "test_asc_asc", scope: null, file: !1, line: 13, type: !6, scopeLine: 13, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !35) +!35 = !{!36} +!36 = !DILocalVariable(name: "10", scope: !34, file: !1, line: 13, type: !37) +!37 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 64) +!38 = !DILocation(line: 13, column: 1, scope: !34) +!39 = !DILocalVariable(name: "11", scope: !34, file: !1, line: 13, type: !37) +;. +; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C, file: [[META1:![0-9]+]], producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) +; CHECK: [[META1]] = !DIFile(filename: "{{.*}}t.c", directory: {{.*}}) +; CHECK: [[DBG5]] = distinct !DISubprogram(name: "test_int_ptr_int", linkageName: "test_int_ptr_int", scope: null, file: [[META1]], line: 1, type: [[META6:![0-9]+]], scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META8:![0-9]+]]) +; CHECK: [[META6]] = !DISubroutineType(types: [[META7:![0-9]+]]) +; CHECK: [[META7]] = !{} +; CHECK: [[META8]] = !{[[META9]], [[META11:![0-9]+]]} +; CHECK: [[META9]] = !DILocalVariable(name: "1", scope: [[DBG5]], file: [[META1]], line: 1, type: [[META10:![0-9]+]]) +; CHECK: [[META10]] = !DIBasicType(name: "ty64", size: 64, encoding: DW_ATE_unsigned) +; CHECK: [[META11]] = !DILocalVariable(name: "2", scope: [[DBG5]], file: [[META1]], line: 2, type: [[META10]]) +; CHECK: [[META12]] = !DILocation(line: 1, column: 1, scope: [[DBG5]]) +; CHECK: [[DBG13]] = distinct !DISubprogram(name: "test_ptr_int_ptr", linkageName: "test_ptr_int_ptr", scope: null, file: [[META1]], line: 5, type: [[META6]], scopeLine: 5, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META14:![0-9]+]]) +; CHECK: [[META14]] = !{[[META15]], [[META16:![0-9]+]]} +; CHECK: [[META15]] = !DILocalVariable(name: "3", scope: [[DBG13]], file: [[META1]], line: 5, type: [[META10]]) +; CHECK: [[META16]] = !DILocalVariable(name: "4", scope: [[DBG13]], file: [[META1]], line: 6, type: [[META10]]) +; CHECK: [[META17]] = !DILocation(line: 5, column: 1, scope: [[DBG13]]) +; CHECK: [[DBG18]] = distinct !DISubprogram(name: "test_zext_trunc", linkageName: "test_zext_trunc", scope: null, file: [[META1]], line: 9, type: [[META6]], scopeLine: 9, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META19:![0-9]+]]) +; CHECK: [[META19]] = !{[[META20]], [[META21:![0-9]+]]} +; CHECK: [[META20]] = !DILocalVariable(name: "5", scope: [[DBG18]], file: [[META1]], line: 9, type: [[META10]]) +; CHECK: [[META21]] = !DILocalVariable(name: "6", scope: [[DBG18]], file: [[META1]], line: 10, type: [[META22:![0-9]+]]) +; CHECK: [[META22]] = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned) +; CHECK: [[META23]] = !DILocation(line: 9, column: 1, scope: [[DBG18]]) +; CHECK: [[DBG24]] = distinct !DISubprogram(name: "test_trunc_zext", linkageName: "test_trunc_zext", scope: null, file: [[META1]], line: 13, type: [[META6]], scopeLine: 13, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META25:![0-9]+]]) +; CHECK: [[META25]] = !{[[META26]], [[META27:![0-9]+]]} +; CHECK: [[META26]] = !DILocalVariable(name: "7", scope: [[DBG24]], file: [[META1]], line: 13, type: [[META22]]) +; CHECK: [[META27]] = !DILocalVariable(name: "8", scope: [[DBG24]], file: [[META1]], line: 14, type: [[META10]]) +; CHECK: [[META28]] = !DILocation(line: 13, column: 1, scope: [[DBG24]]) +; CHECK: [[DBG29]] = distinct !DISubprogram(name: "test_sext_trunc", linkageName: "test_sext_trunc", scope: null, file: [[META1]], line: 13, type: [[META6]], scopeLine: 13, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META30:![0-9]+]]) +; CHECK: [[META30]] = !{[[META31]]} +; CHECK: [[META31]] = !DILocalVariable(name: "9", scope: [[DBG29]], file: [[META1]], line: 13, type: [[META32:![0-9]+]]) +; CHECK: [[META32]] = !DIBasicType(name: "tys32", size: 32, encoding: DW_ATE_signed) +; CHECK: [[META33]] = !DILocation(line: 13, column: 1, scope: [[DBG29]]) +; CHECK: [[DBG34]] = distinct !DISubprogram(name: "test_asc_asc", linkageName: "test_asc_asc", scope: null, file: [[META1]], line: 13, type: [[META6]], scopeLine: 13, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META35:![0-9]+]]) +; CHECK: [[META35]] = !{[[META36]]} +; CHECK: [[META36]] = !DILocalVariable(name: "10", scope: [[DBG34]], file: [[META1]], line: 13, type: [[META37:![0-9]+]]) +; CHECK: [[META37]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 64) +; CHECK: [[META38]] = !DILocation(line: 13, column: 1, scope: [[DBG34]]) +; CHECK: [[META39]] = !DILocalVariable(name: "11", scope: [[DBG34]], file: [[META1]], line: 13, type: [[META37]]) +;. diff --git a/llvm/test/Transforms/InstCombine/heterogeneous-poison-lower-dbg-declare.ll b/llvm/test/Transforms/InstCombine/heterogeneous-poison-lower-dbg-declare.ll new file mode 100644 index 0000000000000..8b87e7b4abb1a --- /dev/null +++ b/llvm/test/Transforms/InstCombine/heterogeneous-poison-lower-dbg-declare.ll @@ -0,0 +1,89 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes='instcombine' -S < %s | FileCheck %s + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i32 @foo() !dbg !5 { +; CHECK-LABEL: define i32 @foo( +; CHECK-SAME: ) !dbg [[DBG5:![0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[VAR:%.*]] = alloca i32, align 4 +; CHECK-NEXT: #dbg_value(i32 42, [[META11:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[META12:![0-9]+]]) +; CHECK-NEXT: store i32 42, ptr [[VAR]], align 4 +; CHECK-NEXT: #dbg_value(ptr [[VAR]], [[META11]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), [[META12]]) +; CHECK-NEXT: call void @escape(ptr nonnull [[VAR]]) +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAR]], align 4 +; CHECK-NEXT: #dbg_value(i32 [[TMP0]], [[META11]], !DIExpression(DIOpArg(0, i32)), [[META12]]) +; CHECK-NEXT: ret i32 [[TMP0]] +; +entry: + %var = alloca i32, align 4 + #dbg_declare(ptr %var, !11, !DIExpression(DIOpArg(0, ptr), DIOpDeref(i32)), !12) + store i32 42, ptr %var, align 4 + call void @escape(ptr %var) + %0 = load i32, ptr %var, align 4 + ret i32 %0 +} + +define void @bar() !dbg !15 { +; CHECK-LABEL: define void @bar( +; CHECK-SAME: ) !dbg [[DBG13:![0-9]+]] { +; CHECK-NEXT: [[VAR:%.*]] = alloca i32, align 4, addrspace(5) +; CHECK-NEXT: [[VAR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VAR]] to ptr +; CHECK-NEXT: #dbg_value(i32 42, [[META15:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[META16:![0-9]+]]) +; CHECK-NEXT: store i32 42, ptr [[VAR_ASCAST]], align 4 +; CHECK-NEXT: #dbg_value(ptr addrspace(5) [[VAR]], [[META15]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META16]]) +; CHECK-NEXT: call void @escape(ptr nonnull [[VAR_ASCAST]]) +; CHECK-NEXT: ret void +; + %var = alloca i32, align 4, addrspace(5) + %var.ascast = addrspacecast ptr addrspace(5) %var to ptr + #dbg_declare(ptr addrspace(5) %var, !17, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), !18) + store i32 42, ptr %var.ascast, align 4 + call void @escape(ptr %var.ascast) + ret void +} + +declare void @escape(ptr) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} +!llvm.ident = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang 19.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "t.c", directory: "/") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{!"clang 19.0.0"} +!5 = distinct !DISubprogram(name: "main", scope: !6, file: !6, line: 4, type: !7, scopeLine: 4, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !10) +!6 = !DIFile(filename: "t.cpp", directory: "/") +!7 = !DISubroutineType(types: !8) +!8 = !{!9} +!9 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!10 = !{!11} +!11 = !DILocalVariable(name: "var", scope: !5, file: !6, line: 5, type: !9) +!12 = !DILocation(line: 1, column: 1, scope: !5) +!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 64) +!14 = !DILocalVariable(name: "ptr", scope: !5, file: !6, line: 5, type: !13) +!15 = distinct !DISubprogram(name: "bar", scope: !6, file: !6, line: 4, type: !7, scopeLine: 4, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !16) +!16 = !{!17} +!17 = !DILocalVariable(name: "var", scope: !15, file: !6, line: 5, type: !9) +!18 = !DILocation(line: 1, column: 1, scope: !15) + +;. +; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "clang 19.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +; CHECK: [[META1]] = !DIFile(filename: "t.c", directory: {{.*}}) +; CHECK: [[DBG5]] = distinct !DISubprogram(name: "main", scope: [[META6:![0-9]+]], file: [[META6]], line: 4, type: [[META7:![0-9]+]], scopeLine: 4, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META10:![0-9]+]]) +; CHECK: [[META6]] = !DIFile(filename: "t.cpp", directory: {{.*}}) +; CHECK: [[META7]] = !DISubroutineType(types: [[META8:![0-9]+]]) +; CHECK: [[META8]] = !{[[META9:![0-9]+]]} +; CHECK: [[META9]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +; CHECK: [[META10]] = !{[[META11]]} +; CHECK: [[META11]] = !DILocalVariable(name: "var", scope: [[DBG5]], file: [[META6]], line: 5, type: [[META9]]) +; CHECK: [[META12]] = !DILocation(line: 0, scope: [[DBG5]]) +; CHECK: [[DBG13]] = distinct !DISubprogram(name: "bar", scope: [[META6]], file: [[META6]], line: 4, type: [[META7]], scopeLine: 4, spFlags: DISPFlagDefinition, unit: [[META0]], retainedNodes: [[META14:![0-9]+]]) +; CHECK: [[META14]] = !{[[META15]]} +; CHECK: [[META15]] = !DILocalVariable(name: "var", scope: [[DBG13]], file: [[META6]], line: 5, type: [[META9]]) +; CHECK: [[META16]] = !DILocation(line: 0, scope: [[DBG13]]) +;. diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/logf128.ll b/llvm/test/Transforms/InstSimplify/ConstProp/logf128.ll index 82db5e4066cb1..a516266edf67d 100644 --- a/llvm/test/Transforms/InstSimplify/ConstProp/logf128.ll +++ b/llvm/test/Transforms/InstSimplify/ConstProp/logf128.ll @@ -72,8 +72,9 @@ define fp128 @log_e_smallest_number_larger_than_one(){ define fp128 @log_e_negative_2(){ ; CHECK-LABEL: define fp128 @log_e_negative_2() { -; CHECK-NEXT: ret fp128 0xL0000000000000000{{[7|F]}}FFF800000000000 +; CHECK-NEXT: ret fp128 0xL0000000000000000FFFF800000000000 ; + %A = call fp128 @llvm.log.f128(fp128 noundef 0xL0000000000000000C000000000000000) ret fp128 %A } @@ -104,8 +105,9 @@ define fp128 @log_e_infinity(){ define fp128 @log_e_negative_infinity(){ ; CHECK-LABEL: define fp128 @log_e_negative_infinity() { -; CHECK-NEXT: ret fp128 0xL0000000000000000{{[7|F]}}FFF800000000000 +; CHECK-NEXT: ret fp128 0xL0000000000000000FFFF800000000000 ; + %A = call fp128 @llvm.log.f128(fp128 noundef 0xL0000000000000000FFFF000000000000) ret fp128 %A } @@ -120,8 +122,9 @@ define fp128 @log_e_nan(){ define <2 x fp128> @log_e_negative_2_vector(){ ; CHECK-LABEL: define <2 x fp128> @log_e_negative_2_vector() { -; CHECK-NEXT: ret <2 x fp128> +; CHECK-NEXT: ret <2 x fp128> ; + %A = call <2 x fp128> @llvm.log.v2f128(<2 x fp128> ) ret <2 x fp128> %A } diff --git a/llvm/test/Transforms/Internalize/globs.ll b/llvm/test/Transforms/Internalize/globs.ll deleted file mode 100644 index 47a2828177dde..0000000000000 --- a/llvm/test/Transforms/Internalize/globs.ll +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: opt < %s -passes=internalize -internalize-public-api-list 'bar?,_*,*_,[ab]' -S | FileCheck %s - -; CHECK: @foo = internal global -@foo = global i32 0 - -; CHECK: @bar_ = global -@bar_ = global i32 0 - -; CHECK: @_foo = global -@_foo = global i32 0 - -; CHECK: @foo_ = global -@foo_ = global i32 0 - -; CHECK: @a = global -@a = global i32 0 - -; CHECK: @b = global -@b = global i32 0 - -; CHECK: @c = internal global -@c = global i32 0 diff --git a/llvm/test/Transforms/LoopUnroll/full-unroll-invariant.ll b/llvm/test/Transforms/LoopUnroll/full-unroll-invariant.ll index f3e1f7ede95c7..98fe2bd65d2b9 100644 --- a/llvm/test/Transforms/LoopUnroll/full-unroll-invariant.ll +++ b/llvm/test/Transforms/LoopUnroll/full-unroll-invariant.ll @@ -61,9 +61,15 @@ define i32 @test3(i8 %a) { ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: -; CHECK-NEXT: [[ZEXT_9:%.*]] = zext i8 [[A:%.*]] to i32 -; CHECK-NEXT: [[DIV_9:%.*]] = udiv i32 [[ZEXT_9]], 31 -; CHECK-NEXT: ret i32 [[DIV_9]] +; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[A:%.*]] to i32 +; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[ZEXT]], 31 +; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[PHI]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[INC]], 10 +; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_EXIT:%.*]] +; CHECK: for.exit: +; CHECK-NEXT: [[DIV_LCSSA:%.*]] = phi i32 [ [[DIV]], [[FOR_BODY]] ] +; CHECK-NEXT: ret i32 [[DIV_LCSSA]] ; entry: br label %for.body diff --git a/llvm/test/Transforms/LoopUnroll/loop-branch-folding.ll b/llvm/test/Transforms/LoopUnroll/loop-branch-folding.ll index f0a6c0a954f6a..57d7320bada5c 100644 --- a/llvm/test/Transforms/LoopUnroll/loop-branch-folding.ll +++ b/llvm/test/Transforms/LoopUnroll/loop-branch-folding.ll @@ -1,936 +1,937 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt < %s -S -passes=simplifycfg | FileCheck %s --check-prefixes=CHECK-CFG -; RUN: opt < %s -S -passes=simplifycfg,loop-unroll --unroll-max-upperbound=17 | FileCheck %s --check-prefixes=CHECK-UNROLL + ; RUN: opt < %s -S -passes=simplifycfg | FileCheck %s --check-prefixes=CHECK-CFG + ; RUN: opt < %s -S -passes=simplifycfg,loop-unroll --unroll-max-upperbound=17 | FileCheck %s --check-prefixes=CHECK-UNROLL -; This test designed to check: -; We can still unroll loop with 'pragma unroll' if loop count(trip count) was destroyed by previous optimization. -; For exmaple, in following test, loop condition "Dim < 16" was 'merged' with "Dim == Dims" in folding branches -; at simplifycfg. But if custumer mark the loop with "#pragma unroll", we can still successfully unroll it under -; unroll-max-upperbound. -; -; __device__ void func(int Idx, int *Arr[], int Dims, int *Out) { -; #pragma unroll -; for (int Dim = 0; Dim < 16; ++Dim) { -; if (Dim == Dims) { -; break; -; } -; int divmod = Arr[Dim][Idx]; -; Idx = divmod + 1; -; -; for (int arg = 0; arg < 4; arg++) { -; Out[arg] += Arr[Dim][arg]; -; bar(); -; } -; } -; } + ; This test designed to check: + ; We can still unroll loop with 'pragma unroll' if loop count(trip count) was destroyed by previous optimization. + ; For exmaple, in following test, loop condition "Dim < 16" was 'merged' with "Dim == Dims" in folding branches + ; at simplifycfg. But if custumer mark the loop with "#pragma unroll", we can still successfully unroll it under + ; unroll-max-upperbound. + ; + ; __device__ void func(int Idx, int *Arr[], int Dims, int *Out) { + ; #pragma unroll + ; for (int Dim = 0; Dim < 16; ++Dim) { + ; if (Dim == Dims) { + ; break; + ; } + ; int divmod = Arr[Dim][Idx]; + ; Idx = divmod + 1; + ; + ; for (int arg = 0; arg < 4; arg++) { + ; Out[arg] += Arr[Dim][arg]; + ; bar(); + ; } + ; } + ; } -define void @func(i32 noundef %Idx, ptr noundef %Arr, i32 noundef %Dims, ptr noundef %Out) { -; CHECK-CFG-LABEL: define void @func( -; CHECK-CFG-SAME: i32 noundef [[IDX:%.*]], ptr noundef [[ARR:%.*]], i32 noundef [[DIMS:%.*]], ptr noundef [[OUT:%.*]]) { -; CHECK-CFG-NEXT: entry: -; CHECK-CFG-NEXT: br label [[FOR_COND:%.*]] -; CHECK-CFG: for.cond: -; CHECK-CFG-NEXT: [[DIM_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC16:%.*]], [[FOR_COND_CLEANUP6:%.*]] ] -; CHECK-CFG-NEXT: [[IDX_ADDR_0:%.*]] = phi i32 [ [[IDX]], [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_COND_CLEANUP6]] ] -; CHECK-CFG-NEXT: [[CMP:%.*]] = icmp sge i32 [[DIM_0]], 16 -; CHECK-CFG-NEXT: [[CMP1:%.*]] = icmp eq i32 [[DIM_0]], [[DIMS]] -; CHECK-CFG-NEXT: [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]] -; CHECK-CFG-NEXT: br i1 [[OR_COND]], label [[CLEANUP:%.*]], label [[IF_END:%.*]] -; CHECK-CFG: if.end: -; CHECK-CFG-NEXT: [[IDXPROM:%.*]] = sext i32 [[DIM_0]] to i64 -; CHECK-CFG-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 [[IDXPROM]] -; CHECK-CFG-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8 -; CHECK-CFG-NEXT: [[IDXPROM2:%.*]] = sext i32 [[IDX_ADDR_0]] to i64 -; CHECK-CFG-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 [[IDXPROM2]] -; CHECK-CFG-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX3]], align 4 -; CHECK-CFG-NEXT: [[ADD]] = add nsw i32 [[TMP1]], 1 -; CHECK-CFG-NEXT: br label [[FOR_COND4:%.*]] -; CHECK-CFG: for.cond4: -; CHECK-CFG-NEXT: [[ARG_0:%.*]] = phi i32 [ 0, [[IF_END]] ], [ [[INC:%.*]], [[FOR_BODY7:%.*]] ] -; CHECK-CFG-NEXT: [[CMP5:%.*]] = icmp slt i32 [[ARG_0]], 4 -; CHECK-CFG-NEXT: br i1 [[CMP5]], label [[FOR_BODY7]], label [[FOR_COND_CLEANUP6]] -; CHECK-CFG: for.cond.cleanup6: -; CHECK-CFG-NEXT: [[INC16]] = add nsw i32 [[DIM_0]], 1 -; CHECK-CFG-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP0:![0-9]+]] -; CHECK-CFG: for.body7: -; CHECK-CFG-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8 -; CHECK-CFG-NEXT: [[IDXPROM10:%.*]] = sext i32 [[ARG_0]] to i64 -; CHECK-CFG-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[IDXPROM10]] -; CHECK-CFG-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 -; CHECK-CFG-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 [[IDXPROM10]] -; CHECK-CFG-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX13]], align 4 -; CHECK-CFG-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP4]], [[TMP3]] -; CHECK-CFG-NEXT: store i32 [[ADD14]], ptr [[ARRAYIDX13]], align 4 -; CHECK-CFG-NEXT: call void @_Z3barv() -; CHECK-CFG-NEXT: [[INC]] = add nsw i32 [[ARG_0]], 1 -; CHECK-CFG-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP3:![0-9]+]] -; CHECK-CFG: cleanup: -; CHECK-CFG-NEXT: ret void -; -; CHECK-UNROLL-LABEL: define void @func( -; CHECK-UNROLL-SAME: i32 noundef [[IDX:%.*]], ptr noundef [[ARR:%.*]], i32 noundef [[DIMS:%.*]], ptr noundef [[OUT:%.*]]) { -; CHECK-UNROLL-NEXT: entry: -; CHECK-UNROLL-NEXT: br label [[FOR_COND:%.*]] -; CHECK-UNROLL: for.cond: -; CHECK-UNROLL-NEXT: [[CMP1:%.*]] = icmp eq i32 0, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1]], label [[CLEANUP:%.*]], label [[IF_END:%.*]] -; CHECK-UNROLL: if.end: -; CHECK-UNROLL-NEXT: br label [[FOR_COND4:%.*]] -; CHECK-UNROLL: for.cond4: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7:%.*]] -; CHECK-UNROLL: for.cond.cleanup6: -; CHECK-UNROLL-NEXT: [[CMP1_1:%.*]] = icmp eq i32 1, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_1]], label [[CLEANUP]], label [[IF_END_1:%.*]] -; CHECK-UNROLL: if.end.1: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 1 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_1:%.*]] -; CHECK-UNROLL: for.cond4.1: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_12:%.*]] -; CHECK-UNROLL: for.body7.12: -; CHECK-UNROLL-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX_1]], align 8 -; CHECK-UNROLL-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 -; CHECK-UNROLL-NEXT: [[TMP2:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_11:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_11]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_1:%.*]] -; CHECK-UNROLL: for.body7.1.1: -; CHECK-UNROLL-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARRAYIDX_1]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_1:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX11_1_1]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_1:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX13_1_1]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_1]], ptr [[ARRAYIDX13_1_1]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_1:%.*]] -; CHECK-UNROLL: for.body7.2.1: -; CHECK-UNROLL-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX_1]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_1:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX11_2_1]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_1:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX13_2_1]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_1]], ptr [[ARRAYIDX13_2_1]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_1:%.*]] -; CHECK-UNROLL: for.body7.3.1: -; CHECK-UNROLL-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYIDX_1]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_1:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX11_3_1]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_1:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX13_3_1]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_1:%.*]] = add nsw i32 [[TMP11]], [[TMP10]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_1]], ptr [[ARRAYIDX13_3_1]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4:%.*]], label [[FOR_COND_CLEANUP6_1:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.1: -; CHECK-UNROLL-NEXT: [[CMP1_2:%.*]] = icmp eq i32 2, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_2]], label [[CLEANUP]], label [[IF_END_2:%.*]] -; CHECK-UNROLL: if.end.2: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 2 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_2:%.*]] -; CHECK-UNROLL: for.cond4.2: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_24:%.*]] -; CHECK-UNROLL: for.body7.24: -; CHECK-UNROLL-NEXT: [[TMP12:%.*]] = load ptr, ptr [[ARRAYIDX_2]], align 8 -; CHECK-UNROLL-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 -; CHECK-UNROLL-NEXT: [[TMP14:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_23:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_23]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_2:%.*]] -; CHECK-UNROLL: for.body7.1.2: -; CHECK-UNROLL-NEXT: [[TMP15:%.*]] = load ptr, ptr [[ARRAYIDX_2]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_2:%.*]] = getelementptr inbounds i32, ptr [[TMP15]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX11_1_2]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_2:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARRAYIDX13_1_2]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_2:%.*]] = add nsw i32 [[TMP17]], [[TMP16]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_2]], ptr [[ARRAYIDX13_1_2]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_2:%.*]] -; CHECK-UNROLL: for.body7.2.2: -; CHECK-UNROLL-NEXT: [[TMP18:%.*]] = load ptr, ptr [[ARRAYIDX_2]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_2:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP19:%.*]] = load i32, ptr [[ARRAYIDX11_2_2]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_2:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX13_2_2]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_2:%.*]] = add nsw i32 [[TMP20]], [[TMP19]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_2]], ptr [[ARRAYIDX13_2_2]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_2:%.*]] -; CHECK-UNROLL: for.body7.3.2: -; CHECK-UNROLL-NEXT: [[TMP21:%.*]] = load ptr, ptr [[ARRAYIDX_2]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_2:%.*]] = getelementptr inbounds i32, ptr [[TMP21]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX11_3_2]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_2:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX13_3_2]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_2:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_2]], ptr [[ARRAYIDX13_3_2]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_2:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.2: -; CHECK-UNROLL-NEXT: [[CMP1_3:%.*]] = icmp eq i32 3, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_3]], label [[CLEANUP]], label [[IF_END_3:%.*]] -; CHECK-UNROLL: if.end.3: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 3 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_3:%.*]] -; CHECK-UNROLL: for.cond4.3: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_36:%.*]] -; CHECK-UNROLL: for.body7.36: -; CHECK-UNROLL-NEXT: [[TMP24:%.*]] = load ptr, ptr [[ARRAYIDX_3]], align 8 -; CHECK-UNROLL-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4 -; CHECK-UNROLL-NEXT: [[TMP26:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_35:%.*]] = add nsw i32 [[TMP26]], [[TMP25]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_35]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_3:%.*]] -; CHECK-UNROLL: for.body7.1.3: -; CHECK-UNROLL-NEXT: [[TMP27:%.*]] = load ptr, ptr [[ARRAYIDX_3]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_3:%.*]] = getelementptr inbounds i32, ptr [[TMP27]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX11_1_3]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_3:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX13_1_3]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_3:%.*]] = add nsw i32 [[TMP29]], [[TMP28]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_3]], ptr [[ARRAYIDX13_1_3]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_3:%.*]] -; CHECK-UNROLL: for.body7.2.3: -; CHECK-UNROLL-NEXT: [[TMP30:%.*]] = load ptr, ptr [[ARRAYIDX_3]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_3:%.*]] = getelementptr inbounds i32, ptr [[TMP30]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP31:%.*]] = load i32, ptr [[ARRAYIDX11_2_3]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_3:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP32:%.*]] = load i32, ptr [[ARRAYIDX13_2_3]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_3:%.*]] = add nsw i32 [[TMP32]], [[TMP31]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_3]], ptr [[ARRAYIDX13_2_3]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_3:%.*]] -; CHECK-UNROLL: for.body7.3.3: -; CHECK-UNROLL-NEXT: [[TMP33:%.*]] = load ptr, ptr [[ARRAYIDX_3]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_3:%.*]] = getelementptr inbounds i32, ptr [[TMP33]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP34:%.*]] = load i32, ptr [[ARRAYIDX11_3_3]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_3:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP35:%.*]] = load i32, ptr [[ARRAYIDX13_3_3]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_3:%.*]] = add nsw i32 [[TMP35]], [[TMP34]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_3]], ptr [[ARRAYIDX13_3_3]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_3:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.3: -; CHECK-UNROLL-NEXT: [[CMP1_4:%.*]] = icmp eq i32 4, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_4]], label [[CLEANUP]], label [[IF_END_4:%.*]] -; CHECK-UNROLL: if.end.4: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 4 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_4:%.*]] -; CHECK-UNROLL: for.cond4.4: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_48:%.*]] -; CHECK-UNROLL: for.body7.48: -; CHECK-UNROLL-NEXT: [[TMP36:%.*]] = load ptr, ptr [[ARRAYIDX_4]], align 8 -; CHECK-UNROLL-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 -; CHECK-UNROLL-NEXT: [[TMP38:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_47:%.*]] = add nsw i32 [[TMP38]], [[TMP37]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_47]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_4:%.*]] -; CHECK-UNROLL: for.body7.1.4: -; CHECK-UNROLL-NEXT: [[TMP39:%.*]] = load ptr, ptr [[ARRAYIDX_4]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_4:%.*]] = getelementptr inbounds i32, ptr [[TMP39]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP40:%.*]] = load i32, ptr [[ARRAYIDX11_1_4]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_4:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP41:%.*]] = load i32, ptr [[ARRAYIDX13_1_4]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_4:%.*]] = add nsw i32 [[TMP41]], [[TMP40]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_4]], ptr [[ARRAYIDX13_1_4]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_4:%.*]] -; CHECK-UNROLL: for.body7.2.4: -; CHECK-UNROLL-NEXT: [[TMP42:%.*]] = load ptr, ptr [[ARRAYIDX_4]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_4:%.*]] = getelementptr inbounds i32, ptr [[TMP42]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARRAYIDX11_2_4]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_4:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP44:%.*]] = load i32, ptr [[ARRAYIDX13_2_4]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_4:%.*]] = add nsw i32 [[TMP44]], [[TMP43]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_4]], ptr [[ARRAYIDX13_2_4]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_4:%.*]] -; CHECK-UNROLL: for.body7.3.4: -; CHECK-UNROLL-NEXT: [[TMP45:%.*]] = load ptr, ptr [[ARRAYIDX_4]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_4:%.*]] = getelementptr inbounds i32, ptr [[TMP45]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP46:%.*]] = load i32, ptr [[ARRAYIDX11_3_4]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_4:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP47:%.*]] = load i32, ptr [[ARRAYIDX13_3_4]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_4:%.*]] = add nsw i32 [[TMP47]], [[TMP46]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_4]], ptr [[ARRAYIDX13_3_4]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_4:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.4: -; CHECK-UNROLL-NEXT: [[CMP1_5:%.*]] = icmp eq i32 5, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_5]], label [[CLEANUP]], label [[IF_END_5:%.*]] -; CHECK-UNROLL: if.end.5: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 5 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_5:%.*]] -; CHECK-UNROLL: for.cond4.5: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_5:%.*]] -; CHECK-UNROLL: for.body7.5: -; CHECK-UNROLL-NEXT: [[TMP48:%.*]] = load ptr, ptr [[ARRAYIDX_5]], align 8 -; CHECK-UNROLL-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP48]], align 4 -; CHECK-UNROLL-NEXT: [[TMP50:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_5:%.*]] = add nsw i32 [[TMP50]], [[TMP49]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_5]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_5:%.*]] -; CHECK-UNROLL: for.body7.1.5: -; CHECK-UNROLL-NEXT: [[TMP51:%.*]] = load ptr, ptr [[ARRAYIDX_5]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_5:%.*]] = getelementptr inbounds i32, ptr [[TMP51]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP52:%.*]] = load i32, ptr [[ARRAYIDX11_1_5]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_5:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP53:%.*]] = load i32, ptr [[ARRAYIDX13_1_5]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_5:%.*]] = add nsw i32 [[TMP53]], [[TMP52]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_5]], ptr [[ARRAYIDX13_1_5]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_5:%.*]] -; CHECK-UNROLL: for.body7.2.5: -; CHECK-UNROLL-NEXT: [[TMP54:%.*]] = load ptr, ptr [[ARRAYIDX_5]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_5:%.*]] = getelementptr inbounds i32, ptr [[TMP54]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP55:%.*]] = load i32, ptr [[ARRAYIDX11_2_5]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_5:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP56:%.*]] = load i32, ptr [[ARRAYIDX13_2_5]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_5:%.*]] = add nsw i32 [[TMP56]], [[TMP55]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_5]], ptr [[ARRAYIDX13_2_5]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_5:%.*]] -; CHECK-UNROLL: for.body7.3.5: -; CHECK-UNROLL-NEXT: [[TMP57:%.*]] = load ptr, ptr [[ARRAYIDX_5]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_5:%.*]] = getelementptr inbounds i32, ptr [[TMP57]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP58:%.*]] = load i32, ptr [[ARRAYIDX11_3_5]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_5:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP59:%.*]] = load i32, ptr [[ARRAYIDX13_3_5]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_5:%.*]] = add nsw i32 [[TMP59]], [[TMP58]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_5]], ptr [[ARRAYIDX13_3_5]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_5:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.5: -; CHECK-UNROLL-NEXT: [[CMP1_6:%.*]] = icmp eq i32 6, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_6]], label [[CLEANUP]], label [[IF_END_6:%.*]] -; CHECK-UNROLL: if.end.6: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 6 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_6:%.*]] -; CHECK-UNROLL: for.cond4.6: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_6:%.*]] -; CHECK-UNROLL: for.body7.6: -; CHECK-UNROLL-NEXT: [[TMP60:%.*]] = load ptr, ptr [[ARRAYIDX_6]], align 8 -; CHECK-UNROLL-NEXT: [[TMP61:%.*]] = load i32, ptr [[TMP60]], align 4 -; CHECK-UNROLL-NEXT: [[TMP62:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_6:%.*]] = add nsw i32 [[TMP62]], [[TMP61]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_6]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_6:%.*]] -; CHECK-UNROLL: for.body7.1.6: -; CHECK-UNROLL-NEXT: [[TMP63:%.*]] = load ptr, ptr [[ARRAYIDX_6]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_6:%.*]] = getelementptr inbounds i32, ptr [[TMP63]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP64:%.*]] = load i32, ptr [[ARRAYIDX11_1_6]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_6:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP65:%.*]] = load i32, ptr [[ARRAYIDX13_1_6]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_6:%.*]] = add nsw i32 [[TMP65]], [[TMP64]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_6]], ptr [[ARRAYIDX13_1_6]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_6:%.*]] -; CHECK-UNROLL: for.body7.2.6: -; CHECK-UNROLL-NEXT: [[TMP66:%.*]] = load ptr, ptr [[ARRAYIDX_6]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_6:%.*]] = getelementptr inbounds i32, ptr [[TMP66]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP67:%.*]] = load i32, ptr [[ARRAYIDX11_2_6]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_6:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP68:%.*]] = load i32, ptr [[ARRAYIDX13_2_6]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_6:%.*]] = add nsw i32 [[TMP68]], [[TMP67]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_6]], ptr [[ARRAYIDX13_2_6]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_6:%.*]] -; CHECK-UNROLL: for.body7.3.6: -; CHECK-UNROLL-NEXT: [[TMP69:%.*]] = load ptr, ptr [[ARRAYIDX_6]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_6:%.*]] = getelementptr inbounds i32, ptr [[TMP69]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP70:%.*]] = load i32, ptr [[ARRAYIDX11_3_6]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_6:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP71:%.*]] = load i32, ptr [[ARRAYIDX13_3_6]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_6:%.*]] = add nsw i32 [[TMP71]], [[TMP70]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_6]], ptr [[ARRAYIDX13_3_6]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_6:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.6: -; CHECK-UNROLL-NEXT: [[CMP1_7:%.*]] = icmp eq i32 7, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_7]], label [[CLEANUP]], label [[IF_END_7:%.*]] -; CHECK-UNROLL: if.end.7: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 7 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_7:%.*]] -; CHECK-UNROLL: for.cond4.7: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_7:%.*]] -; CHECK-UNROLL: for.body7.7: -; CHECK-UNROLL-NEXT: [[TMP72:%.*]] = load ptr, ptr [[ARRAYIDX_7]], align 8 -; CHECK-UNROLL-NEXT: [[TMP73:%.*]] = load i32, ptr [[TMP72]], align 4 -; CHECK-UNROLL-NEXT: [[TMP74:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_7:%.*]] = add nsw i32 [[TMP74]], [[TMP73]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_7]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_7:%.*]] -; CHECK-UNROLL: for.body7.1.7: -; CHECK-UNROLL-NEXT: [[TMP75:%.*]] = load ptr, ptr [[ARRAYIDX_7]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_7:%.*]] = getelementptr inbounds i32, ptr [[TMP75]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP76:%.*]] = load i32, ptr [[ARRAYIDX11_1_7]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_7:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP77:%.*]] = load i32, ptr [[ARRAYIDX13_1_7]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_7:%.*]] = add nsw i32 [[TMP77]], [[TMP76]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_7]], ptr [[ARRAYIDX13_1_7]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_7:%.*]] -; CHECK-UNROLL: for.body7.2.7: -; CHECK-UNROLL-NEXT: [[TMP78:%.*]] = load ptr, ptr [[ARRAYIDX_7]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_7:%.*]] = getelementptr inbounds i32, ptr [[TMP78]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP79:%.*]] = load i32, ptr [[ARRAYIDX11_2_7]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_7:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP80:%.*]] = load i32, ptr [[ARRAYIDX13_2_7]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_7:%.*]] = add nsw i32 [[TMP80]], [[TMP79]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_7]], ptr [[ARRAYIDX13_2_7]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_7:%.*]] -; CHECK-UNROLL: for.body7.3.7: -; CHECK-UNROLL-NEXT: [[TMP81:%.*]] = load ptr, ptr [[ARRAYIDX_7]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_7:%.*]] = getelementptr inbounds i32, ptr [[TMP81]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP82:%.*]] = load i32, ptr [[ARRAYIDX11_3_7]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_7:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP83:%.*]] = load i32, ptr [[ARRAYIDX13_3_7]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_7:%.*]] = add nsw i32 [[TMP83]], [[TMP82]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_7]], ptr [[ARRAYIDX13_3_7]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_7:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.7: -; CHECK-UNROLL-NEXT: [[CMP1_8:%.*]] = icmp eq i32 8, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_8]], label [[CLEANUP]], label [[IF_END_8:%.*]] -; CHECK-UNROLL: if.end.8: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_8:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 8 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_8:%.*]] -; CHECK-UNROLL: for.cond4.8: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_8:%.*]] -; CHECK-UNROLL: for.body7.8: -; CHECK-UNROLL-NEXT: [[TMP84:%.*]] = load ptr, ptr [[ARRAYIDX_8]], align 8 -; CHECK-UNROLL-NEXT: [[TMP85:%.*]] = load i32, ptr [[TMP84]], align 4 -; CHECK-UNROLL-NEXT: [[TMP86:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_8:%.*]] = add nsw i32 [[TMP86]], [[TMP85]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_8]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_8:%.*]] -; CHECK-UNROLL: for.body7.1.8: -; CHECK-UNROLL-NEXT: [[TMP87:%.*]] = load ptr, ptr [[ARRAYIDX_8]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_8:%.*]] = getelementptr inbounds i32, ptr [[TMP87]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP88:%.*]] = load i32, ptr [[ARRAYIDX11_1_8]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_8:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP89:%.*]] = load i32, ptr [[ARRAYIDX13_1_8]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_8:%.*]] = add nsw i32 [[TMP89]], [[TMP88]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_8]], ptr [[ARRAYIDX13_1_8]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_8:%.*]] -; CHECK-UNROLL: for.body7.2.8: -; CHECK-UNROLL-NEXT: [[TMP90:%.*]] = load ptr, ptr [[ARRAYIDX_8]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_8:%.*]] = getelementptr inbounds i32, ptr [[TMP90]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP91:%.*]] = load i32, ptr [[ARRAYIDX11_2_8]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_8:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP92:%.*]] = load i32, ptr [[ARRAYIDX13_2_8]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_8:%.*]] = add nsw i32 [[TMP92]], [[TMP91]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_8]], ptr [[ARRAYIDX13_2_8]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_8:%.*]] -; CHECK-UNROLL: for.body7.3.8: -; CHECK-UNROLL-NEXT: [[TMP93:%.*]] = load ptr, ptr [[ARRAYIDX_8]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_8:%.*]] = getelementptr inbounds i32, ptr [[TMP93]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP94:%.*]] = load i32, ptr [[ARRAYIDX11_3_8]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_8:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP95:%.*]] = load i32, ptr [[ARRAYIDX13_3_8]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_8:%.*]] = add nsw i32 [[TMP95]], [[TMP94]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_8]], ptr [[ARRAYIDX13_3_8]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_8:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.8: -; CHECK-UNROLL-NEXT: [[CMP1_9:%.*]] = icmp eq i32 9, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_9]], label [[CLEANUP]], label [[IF_END_9:%.*]] -; CHECK-UNROLL: if.end.9: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_9:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 9 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_9:%.*]] -; CHECK-UNROLL: for.cond4.9: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_9:%.*]] -; CHECK-UNROLL: for.body7.9: -; CHECK-UNROLL-NEXT: [[TMP96:%.*]] = load ptr, ptr [[ARRAYIDX_9]], align 8 -; CHECK-UNROLL-NEXT: [[TMP97:%.*]] = load i32, ptr [[TMP96]], align 4 -; CHECK-UNROLL-NEXT: [[TMP98:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_9:%.*]] = add nsw i32 [[TMP98]], [[TMP97]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_9]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_9:%.*]] -; CHECK-UNROLL: for.body7.1.9: -; CHECK-UNROLL-NEXT: [[TMP99:%.*]] = load ptr, ptr [[ARRAYIDX_9]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_9:%.*]] = getelementptr inbounds i32, ptr [[TMP99]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX11_1_9]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_9:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP101:%.*]] = load i32, ptr [[ARRAYIDX13_1_9]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_9:%.*]] = add nsw i32 [[TMP101]], [[TMP100]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_9]], ptr [[ARRAYIDX13_1_9]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_9:%.*]] -; CHECK-UNROLL: for.body7.2.9: -; CHECK-UNROLL-NEXT: [[TMP102:%.*]] = load ptr, ptr [[ARRAYIDX_9]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_9:%.*]] = getelementptr inbounds i32, ptr [[TMP102]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP103:%.*]] = load i32, ptr [[ARRAYIDX11_2_9]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_9:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP104:%.*]] = load i32, ptr [[ARRAYIDX13_2_9]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_9:%.*]] = add nsw i32 [[TMP104]], [[TMP103]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_9]], ptr [[ARRAYIDX13_2_9]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_9:%.*]] -; CHECK-UNROLL: for.body7.3.9: -; CHECK-UNROLL-NEXT: [[TMP105:%.*]] = load ptr, ptr [[ARRAYIDX_9]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_9:%.*]] = getelementptr inbounds i32, ptr [[TMP105]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP106:%.*]] = load i32, ptr [[ARRAYIDX11_3_9]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_9:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP107:%.*]] = load i32, ptr [[ARRAYIDX13_3_9]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_9:%.*]] = add nsw i32 [[TMP107]], [[TMP106]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_9]], ptr [[ARRAYIDX13_3_9]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_9:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.9: -; CHECK-UNROLL-NEXT: [[CMP1_10:%.*]] = icmp eq i32 10, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_10]], label [[CLEANUP]], label [[IF_END_10:%.*]] -; CHECK-UNROLL: if.end.10: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_10:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 10 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_10:%.*]] -; CHECK-UNROLL: for.cond4.10: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_10:%.*]] -; CHECK-UNROLL: for.body7.10: -; CHECK-UNROLL-NEXT: [[TMP108:%.*]] = load ptr, ptr [[ARRAYIDX_10]], align 8 -; CHECK-UNROLL-NEXT: [[TMP109:%.*]] = load i32, ptr [[TMP108]], align 4 -; CHECK-UNROLL-NEXT: [[TMP110:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_10:%.*]] = add nsw i32 [[TMP110]], [[TMP109]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_10]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_10:%.*]] -; CHECK-UNROLL: for.body7.1.10: -; CHECK-UNROLL-NEXT: [[TMP111:%.*]] = load ptr, ptr [[ARRAYIDX_10]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_10:%.*]] = getelementptr inbounds i32, ptr [[TMP111]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP112:%.*]] = load i32, ptr [[ARRAYIDX11_1_10]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_10:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP113:%.*]] = load i32, ptr [[ARRAYIDX13_1_10]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_10:%.*]] = add nsw i32 [[TMP113]], [[TMP112]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_10]], ptr [[ARRAYIDX13_1_10]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_10:%.*]] -; CHECK-UNROLL: for.body7.2.10: -; CHECK-UNROLL-NEXT: [[TMP114:%.*]] = load ptr, ptr [[ARRAYIDX_10]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_10:%.*]] = getelementptr inbounds i32, ptr [[TMP114]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP115:%.*]] = load i32, ptr [[ARRAYIDX11_2_10]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_10:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP116:%.*]] = load i32, ptr [[ARRAYIDX13_2_10]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_10:%.*]] = add nsw i32 [[TMP116]], [[TMP115]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_10]], ptr [[ARRAYIDX13_2_10]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_10:%.*]] -; CHECK-UNROLL: for.body7.3.10: -; CHECK-UNROLL-NEXT: [[TMP117:%.*]] = load ptr, ptr [[ARRAYIDX_10]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_10:%.*]] = getelementptr inbounds i32, ptr [[TMP117]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP118:%.*]] = load i32, ptr [[ARRAYIDX11_3_10]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_10:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP119:%.*]] = load i32, ptr [[ARRAYIDX13_3_10]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_10:%.*]] = add nsw i32 [[TMP119]], [[TMP118]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_10]], ptr [[ARRAYIDX13_3_10]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_10:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.10: -; CHECK-UNROLL-NEXT: [[CMP1_11:%.*]] = icmp eq i32 11, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_11]], label [[CLEANUP]], label [[IF_END_11:%.*]] -; CHECK-UNROLL: if.end.11: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_11:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 11 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_11:%.*]] -; CHECK-UNROLL: for.cond4.11: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_11:%.*]] -; CHECK-UNROLL: for.body7.11: -; CHECK-UNROLL-NEXT: [[TMP120:%.*]] = load ptr, ptr [[ARRAYIDX_11]], align 8 -; CHECK-UNROLL-NEXT: [[TMP121:%.*]] = load i32, ptr [[TMP120]], align 4 -; CHECK-UNROLL-NEXT: [[TMP122:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_119:%.*]] = add nsw i32 [[TMP122]], [[TMP121]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_119]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_11:%.*]] -; CHECK-UNROLL: for.body7.1.11: -; CHECK-UNROLL-NEXT: [[TMP123:%.*]] = load ptr, ptr [[ARRAYIDX_11]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_11:%.*]] = getelementptr inbounds i32, ptr [[TMP123]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP124:%.*]] = load i32, ptr [[ARRAYIDX11_1_11]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_11:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP125:%.*]] = load i32, ptr [[ARRAYIDX13_1_11]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_11:%.*]] = add nsw i32 [[TMP125]], [[TMP124]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_11]], ptr [[ARRAYIDX13_1_11]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_11:%.*]] -; CHECK-UNROLL: for.body7.2.11: -; CHECK-UNROLL-NEXT: [[TMP126:%.*]] = load ptr, ptr [[ARRAYIDX_11]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_11:%.*]] = getelementptr inbounds i32, ptr [[TMP126]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP127:%.*]] = load i32, ptr [[ARRAYIDX11_2_11]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_11:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP128:%.*]] = load i32, ptr [[ARRAYIDX13_2_11]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_11:%.*]] = add nsw i32 [[TMP128]], [[TMP127]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_11]], ptr [[ARRAYIDX13_2_11]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_11:%.*]] -; CHECK-UNROLL: for.body7.3.11: -; CHECK-UNROLL-NEXT: [[TMP129:%.*]] = load ptr, ptr [[ARRAYIDX_11]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_11:%.*]] = getelementptr inbounds i32, ptr [[TMP129]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP130:%.*]] = load i32, ptr [[ARRAYIDX11_3_11]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_11:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP131:%.*]] = load i32, ptr [[ARRAYIDX13_3_11]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_11:%.*]] = add nsw i32 [[TMP131]], [[TMP130]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_11]], ptr [[ARRAYIDX13_3_11]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_11:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.11: -; CHECK-UNROLL-NEXT: [[CMP1_12:%.*]] = icmp eq i32 12, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_12]], label [[CLEANUP]], label [[IF_END_12:%.*]] -; CHECK-UNROLL: if.end.12: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_12:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 12 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_12:%.*]] -; CHECK-UNROLL: for.cond4.12: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1210:%.*]] -; CHECK-UNROLL: for.body7.1210: -; CHECK-UNROLL-NEXT: [[TMP132:%.*]] = load ptr, ptr [[ARRAYIDX_12]], align 8 -; CHECK-UNROLL-NEXT: [[TMP133:%.*]] = load i32, ptr [[TMP132]], align 4 -; CHECK-UNROLL-NEXT: [[TMP134:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_12:%.*]] = add nsw i32 [[TMP134]], [[TMP133]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_12]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_12:%.*]] -; CHECK-UNROLL: for.body7.1.12: -; CHECK-UNROLL-NEXT: [[TMP135:%.*]] = load ptr, ptr [[ARRAYIDX_12]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_12:%.*]] = getelementptr inbounds i32, ptr [[TMP135]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP136:%.*]] = load i32, ptr [[ARRAYIDX11_1_12]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_12:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP137:%.*]] = load i32, ptr [[ARRAYIDX13_1_12]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_12:%.*]] = add nsw i32 [[TMP137]], [[TMP136]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_12]], ptr [[ARRAYIDX13_1_12]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_12:%.*]] -; CHECK-UNROLL: for.body7.2.12: -; CHECK-UNROLL-NEXT: [[TMP138:%.*]] = load ptr, ptr [[ARRAYIDX_12]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_12:%.*]] = getelementptr inbounds i32, ptr [[TMP138]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP139:%.*]] = load i32, ptr [[ARRAYIDX11_2_12]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_12:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP140:%.*]] = load i32, ptr [[ARRAYIDX13_2_12]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_12:%.*]] = add nsw i32 [[TMP140]], [[TMP139]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_12]], ptr [[ARRAYIDX13_2_12]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_12:%.*]] -; CHECK-UNROLL: for.body7.3.12: -; CHECK-UNROLL-NEXT: [[TMP141:%.*]] = load ptr, ptr [[ARRAYIDX_12]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_12:%.*]] = getelementptr inbounds i32, ptr [[TMP141]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP142:%.*]] = load i32, ptr [[ARRAYIDX11_3_12]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_12:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP143:%.*]] = load i32, ptr [[ARRAYIDX13_3_12]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_12:%.*]] = add nsw i32 [[TMP143]], [[TMP142]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_12]], ptr [[ARRAYIDX13_3_12]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_12:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.12: -; CHECK-UNROLL-NEXT: [[CMP1_13:%.*]] = icmp eq i32 13, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_13]], label [[CLEANUP]], label [[IF_END_13:%.*]] -; CHECK-UNROLL: if.end.13: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_13:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 13 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_13:%.*]] -; CHECK-UNROLL: for.cond4.13: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_13:%.*]] -; CHECK-UNROLL: for.body7.13: -; CHECK-UNROLL-NEXT: [[TMP144:%.*]] = load ptr, ptr [[ARRAYIDX_13]], align 8 -; CHECK-UNROLL-NEXT: [[TMP145:%.*]] = load i32, ptr [[TMP144]], align 4 -; CHECK-UNROLL-NEXT: [[TMP146:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_13:%.*]] = add nsw i32 [[TMP146]], [[TMP145]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_13]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_13:%.*]] -; CHECK-UNROLL: for.body7.1.13: -; CHECK-UNROLL-NEXT: [[TMP147:%.*]] = load ptr, ptr [[ARRAYIDX_13]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_13:%.*]] = getelementptr inbounds i32, ptr [[TMP147]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP148:%.*]] = load i32, ptr [[ARRAYIDX11_1_13]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_13:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP149:%.*]] = load i32, ptr [[ARRAYIDX13_1_13]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_13:%.*]] = add nsw i32 [[TMP149]], [[TMP148]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_13]], ptr [[ARRAYIDX13_1_13]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_13:%.*]] -; CHECK-UNROLL: for.body7.2.13: -; CHECK-UNROLL-NEXT: [[TMP150:%.*]] = load ptr, ptr [[ARRAYIDX_13]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_13:%.*]] = getelementptr inbounds i32, ptr [[TMP150]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP151:%.*]] = load i32, ptr [[ARRAYIDX11_2_13]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_13:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP152:%.*]] = load i32, ptr [[ARRAYIDX13_2_13]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_13:%.*]] = add nsw i32 [[TMP152]], [[TMP151]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_13]], ptr [[ARRAYIDX13_2_13]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_13:%.*]] -; CHECK-UNROLL: for.body7.3.13: -; CHECK-UNROLL-NEXT: [[TMP153:%.*]] = load ptr, ptr [[ARRAYIDX_13]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_13:%.*]] = getelementptr inbounds i32, ptr [[TMP153]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP154:%.*]] = load i32, ptr [[ARRAYIDX11_3_13]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_13:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP155:%.*]] = load i32, ptr [[ARRAYIDX13_3_13]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_13:%.*]] = add nsw i32 [[TMP155]], [[TMP154]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_13]], ptr [[ARRAYIDX13_3_13]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_13:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.13: -; CHECK-UNROLL-NEXT: [[CMP1_14:%.*]] = icmp eq i32 14, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_14]], label [[CLEANUP]], label [[IF_END_14:%.*]] -; CHECK-UNROLL: if.end.14: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_14:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 14 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_14:%.*]] -; CHECK-UNROLL: for.cond4.14: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_14:%.*]] -; CHECK-UNROLL: for.body7.14: -; CHECK-UNROLL-NEXT: [[TMP156:%.*]] = load ptr, ptr [[ARRAYIDX_14]], align 8 -; CHECK-UNROLL-NEXT: [[TMP157:%.*]] = load i32, ptr [[TMP156]], align 4 -; CHECK-UNROLL-NEXT: [[TMP158:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_14:%.*]] = add nsw i32 [[TMP158]], [[TMP157]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_14]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_14:%.*]] -; CHECK-UNROLL: for.body7.1.14: -; CHECK-UNROLL-NEXT: [[TMP159:%.*]] = load ptr, ptr [[ARRAYIDX_14]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_14:%.*]] = getelementptr inbounds i32, ptr [[TMP159]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP160:%.*]] = load i32, ptr [[ARRAYIDX11_1_14]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_14:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP161:%.*]] = load i32, ptr [[ARRAYIDX13_1_14]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_14:%.*]] = add nsw i32 [[TMP161]], [[TMP160]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_14]], ptr [[ARRAYIDX13_1_14]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_14:%.*]] -; CHECK-UNROLL: for.body7.2.14: -; CHECK-UNROLL-NEXT: [[TMP162:%.*]] = load ptr, ptr [[ARRAYIDX_14]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_14:%.*]] = getelementptr inbounds i32, ptr [[TMP162]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP163:%.*]] = load i32, ptr [[ARRAYIDX11_2_14]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_14:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP164:%.*]] = load i32, ptr [[ARRAYIDX13_2_14]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_14:%.*]] = add nsw i32 [[TMP164]], [[TMP163]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_14]], ptr [[ARRAYIDX13_2_14]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_14:%.*]] -; CHECK-UNROLL: for.body7.3.14: -; CHECK-UNROLL-NEXT: [[TMP165:%.*]] = load ptr, ptr [[ARRAYIDX_14]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_14:%.*]] = getelementptr inbounds i32, ptr [[TMP165]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP166:%.*]] = load i32, ptr [[ARRAYIDX11_3_14]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_14:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP167:%.*]] = load i32, ptr [[ARRAYIDX13_3_14]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_14:%.*]] = add nsw i32 [[TMP167]], [[TMP166]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_14]], ptr [[ARRAYIDX13_3_14]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_14:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.14: -; CHECK-UNROLL-NEXT: [[CMP1_15:%.*]] = icmp eq i32 15, [[DIMS]] -; CHECK-UNROLL-NEXT: br i1 [[CMP1_15]], label [[CLEANUP]], label [[IF_END_15:%.*]] -; CHECK-UNROLL: if.end.15: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_15:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 15 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_15:%.*]] -; CHECK-UNROLL: for.cond4.15: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_15:%.*]] -; CHECK-UNROLL: for.body7.15: -; CHECK-UNROLL-NEXT: [[TMP168:%.*]] = load ptr, ptr [[ARRAYIDX_15]], align 8 -; CHECK-UNROLL-NEXT: [[TMP169:%.*]] = load i32, ptr [[TMP168]], align 4 -; CHECK-UNROLL-NEXT: [[TMP170:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_15:%.*]] = add nsw i32 [[TMP170]], [[TMP169]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_15]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_15:%.*]] -; CHECK-UNROLL: for.body7.1.15: -; CHECK-UNROLL-NEXT: [[TMP171:%.*]] = load ptr, ptr [[ARRAYIDX_15]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_15:%.*]] = getelementptr inbounds i32, ptr [[TMP171]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP172:%.*]] = load i32, ptr [[ARRAYIDX11_1_15]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_15:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP173:%.*]] = load i32, ptr [[ARRAYIDX13_1_15]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_15:%.*]] = add nsw i32 [[TMP173]], [[TMP172]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_15]], ptr [[ARRAYIDX13_1_15]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_15:%.*]] -; CHECK-UNROLL: for.body7.2.15: -; CHECK-UNROLL-NEXT: [[TMP174:%.*]] = load ptr, ptr [[ARRAYIDX_15]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_15:%.*]] = getelementptr inbounds i32, ptr [[TMP174]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP175:%.*]] = load i32, ptr [[ARRAYIDX11_2_15]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_15:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP176:%.*]] = load i32, ptr [[ARRAYIDX13_2_15]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_15:%.*]] = add nsw i32 [[TMP176]], [[TMP175]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_15]], ptr [[ARRAYIDX13_2_15]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_15:%.*]] -; CHECK-UNROLL: for.body7.3.15: -; CHECK-UNROLL-NEXT: [[TMP177:%.*]] = load ptr, ptr [[ARRAYIDX_15]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_15:%.*]] = getelementptr inbounds i32, ptr [[TMP177]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP178:%.*]] = load i32, ptr [[ARRAYIDX11_3_15]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_15:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP179:%.*]] = load i32, ptr [[ARRAYIDX13_3_15]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_15:%.*]] = add nsw i32 [[TMP179]], [[TMP178]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_15]], ptr [[ARRAYIDX13_3_15]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_15:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.15: -; CHECK-UNROLL-NEXT: br i1 true, label [[CLEANUP]], label [[IF_END_16:%.*]] -; CHECK-UNROLL: if.end.16: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_16:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 16 -; CHECK-UNROLL-NEXT: br label [[FOR_COND4_16:%.*]] -; CHECK-UNROLL: for.cond4.16: -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_16:%.*]] -; CHECK-UNROLL: for.body7.16: -; CHECK-UNROLL-NEXT: [[TMP180:%.*]] = load ptr, ptr [[ARRAYIDX_16]], align 8 -; CHECK-UNROLL-NEXT: [[TMP181:%.*]] = load i32, ptr [[TMP180]], align 4 -; CHECK-UNROLL-NEXT: [[TMP182:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_16:%.*]] = add nsw i32 [[TMP182]], [[TMP181]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_16]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_16:%.*]] -; CHECK-UNROLL: for.body7.1.16: -; CHECK-UNROLL-NEXT: [[TMP183:%.*]] = load ptr, ptr [[ARRAYIDX_16]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_16:%.*]] = getelementptr inbounds i32, ptr [[TMP183]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP184:%.*]] = load i32, ptr [[ARRAYIDX11_1_16]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_16:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP185:%.*]] = load i32, ptr [[ARRAYIDX13_1_16]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1_16:%.*]] = add nsw i32 [[TMP185]], [[TMP184]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_16]], ptr [[ARRAYIDX13_1_16]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_16:%.*]] -; CHECK-UNROLL: for.body7.2.16: -; CHECK-UNROLL-NEXT: [[TMP186:%.*]] = load ptr, ptr [[ARRAYIDX_16]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_16:%.*]] = getelementptr inbounds i32, ptr [[TMP186]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP187:%.*]] = load i32, ptr [[ARRAYIDX11_2_16]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_16:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARRAYIDX13_2_16]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2_16:%.*]] = add nsw i32 [[TMP188]], [[TMP187]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_16]], ptr [[ARRAYIDX13_2_16]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_16:%.*]] -; CHECK-UNROLL: for.body7.3.16: -; CHECK-UNROLL-NEXT: [[TMP189:%.*]] = load ptr, ptr [[ARRAYIDX_16]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_16:%.*]] = getelementptr inbounds i32, ptr [[TMP189]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP190:%.*]] = load i32, ptr [[ARRAYIDX11_3_16]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_16:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP191:%.*]] = load i32, ptr [[ARRAYIDX13_3_16]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3_16:%.*]] = add nsw i32 [[TMP191]], [[TMP190]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_16]], ptr [[ARRAYIDX13_3_16]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_16:%.*]] -; CHECK-UNROLL: for.cond.cleanup6.16: -; CHECK-UNROLL-NEXT: unreachable -; CHECK-UNROLL: for.body7: -; CHECK-UNROLL-NEXT: [[TMP192:%.*]] = load ptr, ptr [[ARR]], align 8 -; CHECK-UNROLL-NEXT: [[TMP193:%.*]] = load i32, ptr [[TMP192]], align 4 -; CHECK-UNROLL-NEXT: [[TMP194:%.*]] = load i32, ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP194]], [[TMP193]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14]], ptr [[OUT]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1:%.*]] -; CHECK-UNROLL: for.body7.1: -; CHECK-UNROLL-NEXT: [[TMP195:%.*]] = load ptr, ptr [[ARR]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1:%.*]] = getelementptr inbounds i32, ptr [[TMP195]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP196:%.*]] = load i32, ptr [[ARRAYIDX11_1]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 -; CHECK-UNROLL-NEXT: [[TMP197:%.*]] = load i32, ptr [[ARRAYIDX13_1]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_1:%.*]] = add nsw i32 [[TMP197]], [[TMP196]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_1]], ptr [[ARRAYIDX13_1]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2:%.*]] -; CHECK-UNROLL: for.body7.2: -; CHECK-UNROLL-NEXT: [[TMP198:%.*]] = load ptr, ptr [[ARR]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2:%.*]] = getelementptr inbounds i32, ptr [[TMP198]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP199:%.*]] = load i32, ptr [[ARRAYIDX11_2]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 -; CHECK-UNROLL-NEXT: [[TMP200:%.*]] = load i32, ptr [[ARRAYIDX13_2]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_2:%.*]] = add nsw i32 [[TMP200]], [[TMP199]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_2]], ptr [[ARRAYIDX13_2]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3:%.*]] -; CHECK-UNROLL: for.body7.3: -; CHECK-UNROLL-NEXT: [[TMP201:%.*]] = load ptr, ptr [[ARR]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3:%.*]] = getelementptr inbounds i32, ptr [[TMP201]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP202:%.*]] = load i32, ptr [[ARRAYIDX11_3]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 -; CHECK-UNROLL-NEXT: [[TMP203:%.*]] = load i32, ptr [[ARRAYIDX13_3]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_3:%.*]] = add nsw i32 [[TMP203]], [[TMP202]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_3]], ptr [[ARRAYIDX13_3]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6:%.*]] -; CHECK-UNROLL: for.body7.4: -; CHECK-UNROLL-NEXT: [[ARRAYIDX_LCSSA:%.*]] = phi ptr [ [[ARR]], [[FOR_BODY7_3]] ], [ [[ARRAYIDX_1]], [[FOR_BODY7_3_1]] ], [ [[ARRAYIDX_2]], [[FOR_BODY7_3_2]] ], [ [[ARRAYIDX_3]], [[FOR_BODY7_3_3]] ], [ [[ARRAYIDX_4]], [[FOR_BODY7_3_4]] ], [ [[ARRAYIDX_5]], [[FOR_BODY7_3_5]] ], [ [[ARRAYIDX_6]], [[FOR_BODY7_3_6]] ], [ [[ARRAYIDX_7]], [[FOR_BODY7_3_7]] ], [ [[ARRAYIDX_8]], [[FOR_BODY7_3_8]] ], [ [[ARRAYIDX_9]], [[FOR_BODY7_3_9]] ], [ [[ARRAYIDX_10]], [[FOR_BODY7_3_10]] ], [ [[ARRAYIDX_11]], [[FOR_BODY7_3_11]] ], [ [[ARRAYIDX_12]], [[FOR_BODY7_3_12]] ], [ [[ARRAYIDX_13]], [[FOR_BODY7_3_13]] ], [ [[ARRAYIDX_14]], [[FOR_BODY7_3_14]] ], [ [[ARRAYIDX_15]], [[FOR_BODY7_3_15]] ], [ [[ARRAYIDX_16]], [[FOR_BODY7_3_16]] ] -; CHECK-UNROLL-NEXT: [[TMP204:%.*]] = load ptr, ptr [[ARRAYIDX_LCSSA]], align 8 -; CHECK-UNROLL-NEXT: [[ARRAYIDX11_4:%.*]] = getelementptr inbounds i32, ptr [[TMP204]], i64 4 -; CHECK-UNROLL-NEXT: [[TMP205:%.*]] = load i32, ptr [[ARRAYIDX11_4]], align 4 -; CHECK-UNROLL-NEXT: [[ARRAYIDX13_4:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 4 -; CHECK-UNROLL-NEXT: [[TMP206:%.*]] = load i32, ptr [[ARRAYIDX13_4]], align 4 -; CHECK-UNROLL-NEXT: [[ADD14_4:%.*]] = add nsw i32 [[TMP206]], [[TMP205]] -; CHECK-UNROLL-NEXT: store i32 [[ADD14_4]], ptr [[ARRAYIDX13_4]], align 4 -; CHECK-UNROLL-NEXT: call void @_Z3barv() -; CHECK-UNROLL-NEXT: unreachable -; CHECK-UNROLL: cleanup: -; CHECK-UNROLL-NEXT: ret void -; -entry: - br label %for.cond + define void @func(i32 noundef %Idx, ptr noundef %Arr, i32 noundef %Dims, ptr noundef %Out) { + ; CHECK-CFG-LABEL: define void @func( + ; CHECK-CFG-SAME: i32 noundef [[IDX:%.*]], ptr noundef [[ARR:%.*]], i32 noundef [[DIMS:%.*]], ptr noundef [[OUT:%.*]]) { + ; CHECK-CFG-NEXT: entry: + ; CHECK-CFG-NEXT: br label [[FOR_COND:%.*]] + ; CHECK-CFG: for.cond: + ; CHECK-CFG-NEXT: [[DIM_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC16:%.*]], [[FOR_COND_CLEANUP6:%.*]] ] + ; CHECK-CFG-NEXT: [[IDX_ADDR_0:%.*]] = phi i32 [ [[IDX]], [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_COND_CLEANUP6]] ] + ; CHECK-CFG-NEXT: [[CMP:%.*]] = icmp sge i32 [[DIM_0]], 16 + ; CHECK-CFG-NEXT: [[CMP1:%.*]] = icmp eq i32 [[DIM_0]], [[DIMS]] + ; CHECK-CFG-NEXT: [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]] + ; CHECK-CFG-NEXT: br i1 [[OR_COND]], label [[CLEANUP:%.*]], label [[IF_END:%.*]] + ; CHECK-CFG: if.end: + ; CHECK-CFG-NEXT: [[IDXPROM:%.*]] = sext i32 [[DIM_0]] to i64 + ; CHECK-CFG-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 [[IDXPROM]] + ; CHECK-CFG-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8 + ; CHECK-CFG-NEXT: [[IDXPROM2:%.*]] = sext i32 [[IDX_ADDR_0]] to i64 + ; CHECK-CFG-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 [[IDXPROM2]] + ; CHECK-CFG-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX3]], align 4 + ; CHECK-CFG-NEXT: [[ADD]] = add nsw i32 [[TMP1]], 1 + ; CHECK-CFG-NEXT: br label [[FOR_COND4:%.*]] + ; CHECK-CFG: for.cond4: + ; CHECK-CFG-NEXT: [[ARG_0:%.*]] = phi i32 [ 0, [[IF_END]] ], [ [[INC:%.*]], [[FOR_BODY7:%.*]] ] + ; CHECK-CFG-NEXT: [[CMP5:%.*]] = icmp slt i32 [[ARG_0]], 4 + ; CHECK-CFG-NEXT: br i1 [[CMP5]], label [[FOR_BODY7]], label [[FOR_COND_CLEANUP6]] + ; CHECK-CFG: for.cond.cleanup6: + ; CHECK-CFG-NEXT: [[INC16]] = add nsw i32 [[DIM_0]], 1 + ; CHECK-CFG-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP0:![0-9]+]] + ; CHECK-CFG: for.body7: + ; CHECK-CFG-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8 + ; CHECK-CFG-NEXT: [[IDXPROM10:%.*]] = sext i32 [[ARG_0]] to i64 + ; CHECK-CFG-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[IDXPROM10]] + ; CHECK-CFG-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 + ; CHECK-CFG-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 [[IDXPROM10]] + ; CHECK-CFG-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX13]], align 4 + ; CHECK-CFG-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP4]], [[TMP3]] + ; CHECK-CFG-NEXT: store i32 [[ADD14]], ptr [[ARRAYIDX13]], align 4 + ; CHECK-CFG-NEXT: call void @_Z3barv() + ; CHECK-CFG-NEXT: [[INC]] = add nsw i32 [[ARG_0]], 1 + ; CHECK-CFG-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP3:![0-9]+]] + ; CHECK-CFG: cleanup: + ; CHECK-CFG-NEXT: ret void + ; + ; CHECK-UNROLL-LABEL: define void @func( + ; CHECK-UNROLL-SAME: i32 noundef [[IDX:%.*]], ptr noundef [[ARR:%.*]], i32 noundef [[DIMS:%.*]], ptr noundef [[OUT:%.*]]) { + ; CHECK-UNROLL-NEXT: entry: + ; CHECK-UNROLL-NEXT: br label [[FOR_COND:%.*]] + ; CHECK-UNROLL: for.cond: + ; CHECK-UNROLL-NEXT: [[CMP1:%.*]] = icmp eq i32 0, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1]], label [[CLEANUP:%.*]], label [[IF_END:%.*]] + ; CHECK-UNROLL: if.end: + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4:%.*]] + ; CHECK-UNROLL: for.cond4: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6: + ; CHECK-UNROLL-NEXT: [[CMP1_1:%.*]] = icmp eq i32 1, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_1]], label [[CLEANUP]], label [[IF_END_1:%.*]] + ; CHECK-UNROLL: if.end.1: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 1 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_1:%.*]] + ; CHECK-UNROLL: for.cond4.1: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_12:%.*]] + ; CHECK-UNROLL: for.body7.12: + ; CHECK-UNROLL-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX_1]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP2:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_11:%.*]] = add nsw i32 [[TMP2]], [[TMP1]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_11]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_1:%.*]] + ; CHECK-UNROLL: for.body7.1.1: + ; CHECK-UNROLL-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARRAYIDX_1]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_1:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX11_1_1]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_1:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX13_1_1]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_1]], ptr [[ARRAYIDX13_1_1]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_1:%.*]] + ; CHECK-UNROLL: for.body7.2.1: + ; CHECK-UNROLL-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX_1]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_1:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX11_2_1]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_1:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX13_2_1]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_1]], ptr [[ARRAYIDX13_2_1]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_1:%.*]] + ; CHECK-UNROLL: for.body7.3.1: + ; CHECK-UNROLL-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYIDX_1]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_1:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX11_3_1]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_1:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX13_3_1]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_1:%.*]] = add nsw i32 [[TMP11]], [[TMP10]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_1]], ptr [[ARRAYIDX13_3_1]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4:%.*]], label [[FOR_COND_CLEANUP6_1:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.1: + ; CHECK-UNROLL-NEXT: [[CMP1_2:%.*]] = icmp eq i32 2, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_2]], label [[CLEANUP]], label [[IF_END_2:%.*]] + ; CHECK-UNROLL: if.end.2: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 2 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_2:%.*]] + ; CHECK-UNROLL: for.cond4.2: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_24:%.*]] + ; CHECK-UNROLL: for.body7.24: + ; CHECK-UNROLL-NEXT: [[TMP12:%.*]] = load ptr, ptr [[ARRAYIDX_2]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP14:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_23:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_23]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_2:%.*]] + ; CHECK-UNROLL: for.body7.1.2: + ; CHECK-UNROLL-NEXT: [[TMP15:%.*]] = load ptr, ptr [[ARRAYIDX_2]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_2:%.*]] = getelementptr inbounds i32, ptr [[TMP15]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX11_1_2]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_2:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARRAYIDX13_1_2]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_2:%.*]] = add nsw i32 [[TMP17]], [[TMP16]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_2]], ptr [[ARRAYIDX13_1_2]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_2:%.*]] + ; CHECK-UNROLL: for.body7.2.2: + ; CHECK-UNROLL-NEXT: [[TMP18:%.*]] = load ptr, ptr [[ARRAYIDX_2]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_2:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP19:%.*]] = load i32, ptr [[ARRAYIDX11_2_2]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_2:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX13_2_2]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_2:%.*]] = add nsw i32 [[TMP20]], [[TMP19]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_2]], ptr [[ARRAYIDX13_2_2]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_2:%.*]] + ; CHECK-UNROLL: for.body7.3.2: + ; CHECK-UNROLL-NEXT: [[TMP21:%.*]] = load ptr, ptr [[ARRAYIDX_2]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_2:%.*]] = getelementptr inbounds i32, ptr [[TMP21]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX11_3_2]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_2:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX13_3_2]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_2:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_2]], ptr [[ARRAYIDX13_3_2]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_2:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.2: + ; CHECK-UNROLL-NEXT: [[CMP1_3:%.*]] = icmp eq i32 3, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_3]], label [[CLEANUP]], label [[IF_END_3:%.*]] + ; CHECK-UNROLL: if.end.3: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 3 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_3:%.*]] + ; CHECK-UNROLL: for.cond4.3: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_36:%.*]] + ; CHECK-UNROLL: for.body7.36: + ; CHECK-UNROLL-NEXT: [[TMP24:%.*]] = load ptr, ptr [[ARRAYIDX_3]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP26:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_35:%.*]] = add nsw i32 [[TMP26]], [[TMP25]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_35]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_3:%.*]] + ; CHECK-UNROLL: for.body7.1.3: + ; CHECK-UNROLL-NEXT: [[TMP27:%.*]] = load ptr, ptr [[ARRAYIDX_3]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_3:%.*]] = getelementptr inbounds i32, ptr [[TMP27]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX11_1_3]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_3:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX13_1_3]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_3:%.*]] = add nsw i32 [[TMP29]], [[TMP28]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_3]], ptr [[ARRAYIDX13_1_3]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_3:%.*]] + ; CHECK-UNROLL: for.body7.2.3: + ; CHECK-UNROLL-NEXT: [[TMP30:%.*]] = load ptr, ptr [[ARRAYIDX_3]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_3:%.*]] = getelementptr inbounds i32, ptr [[TMP30]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP31:%.*]] = load i32, ptr [[ARRAYIDX11_2_3]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_3:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP32:%.*]] = load i32, ptr [[ARRAYIDX13_2_3]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_3:%.*]] = add nsw i32 [[TMP32]], [[TMP31]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_3]], ptr [[ARRAYIDX13_2_3]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_3:%.*]] + ; CHECK-UNROLL: for.body7.3.3: + ; CHECK-UNROLL-NEXT: [[TMP33:%.*]] = load ptr, ptr [[ARRAYIDX_3]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_3:%.*]] = getelementptr inbounds i32, ptr [[TMP33]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP34:%.*]] = load i32, ptr [[ARRAYIDX11_3_3]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_3:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP35:%.*]] = load i32, ptr [[ARRAYIDX13_3_3]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_3:%.*]] = add nsw i32 [[TMP35]], [[TMP34]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_3]], ptr [[ARRAYIDX13_3_3]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_3:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.3: + ; CHECK-UNROLL-NEXT: [[CMP1_4:%.*]] = icmp eq i32 4, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_4]], label [[CLEANUP]], label [[IF_END_4:%.*]] + ; CHECK-UNROLL: if.end.4: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 4 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_4:%.*]] + ; CHECK-UNROLL: for.cond4.4: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_48:%.*]] + ; CHECK-UNROLL: for.body7.48: + ; CHECK-UNROLL-NEXT: [[TMP36:%.*]] = load ptr, ptr [[ARRAYIDX_4]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP38:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_47:%.*]] = add nsw i32 [[TMP38]], [[TMP37]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_47]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_4:%.*]] + ; CHECK-UNROLL: for.body7.1.4: + ; CHECK-UNROLL-NEXT: [[TMP39:%.*]] = load ptr, ptr [[ARRAYIDX_4]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_4:%.*]] = getelementptr inbounds i32, ptr [[TMP39]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP40:%.*]] = load i32, ptr [[ARRAYIDX11_1_4]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_4:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP41:%.*]] = load i32, ptr [[ARRAYIDX13_1_4]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_4:%.*]] = add nsw i32 [[TMP41]], [[TMP40]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_4]], ptr [[ARRAYIDX13_1_4]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_4:%.*]] + ; CHECK-UNROLL: for.body7.2.4: + ; CHECK-UNROLL-NEXT: [[TMP42:%.*]] = load ptr, ptr [[ARRAYIDX_4]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_4:%.*]] = getelementptr inbounds i32, ptr [[TMP42]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARRAYIDX11_2_4]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_4:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP44:%.*]] = load i32, ptr [[ARRAYIDX13_2_4]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_4:%.*]] = add nsw i32 [[TMP44]], [[TMP43]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_4]], ptr [[ARRAYIDX13_2_4]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_4:%.*]] + ; CHECK-UNROLL: for.body7.3.4: + ; CHECK-UNROLL-NEXT: [[TMP45:%.*]] = load ptr, ptr [[ARRAYIDX_4]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_4:%.*]] = getelementptr inbounds i32, ptr [[TMP45]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP46:%.*]] = load i32, ptr [[ARRAYIDX11_3_4]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_4:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP47:%.*]] = load i32, ptr [[ARRAYIDX13_3_4]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_4:%.*]] = add nsw i32 [[TMP47]], [[TMP46]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_4]], ptr [[ARRAYIDX13_3_4]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_4:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.4: + ; CHECK-UNROLL-NEXT: [[CMP1_5:%.*]] = icmp eq i32 5, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_5]], label [[CLEANUP]], label [[IF_END_5:%.*]] + ; CHECK-UNROLL: if.end.5: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 5 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_5:%.*]] + ; CHECK-UNROLL: for.cond4.5: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_5:%.*]] + ; CHECK-UNROLL: for.body7.5: + ; CHECK-UNROLL-NEXT: [[TMP48:%.*]] = load ptr, ptr [[ARRAYIDX_5]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP48]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP50:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_5:%.*]] = add nsw i32 [[TMP50]], [[TMP49]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_5]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_5:%.*]] + ; CHECK-UNROLL: for.body7.1.5: + ; CHECK-UNROLL-NEXT: [[TMP51:%.*]] = load ptr, ptr [[ARRAYIDX_5]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_5:%.*]] = getelementptr inbounds i32, ptr [[TMP51]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP52:%.*]] = load i32, ptr [[ARRAYIDX11_1_5]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_5:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP53:%.*]] = load i32, ptr [[ARRAYIDX13_1_5]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_5:%.*]] = add nsw i32 [[TMP53]], [[TMP52]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_5]], ptr [[ARRAYIDX13_1_5]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_5:%.*]] + ; CHECK-UNROLL: for.body7.2.5: + ; CHECK-UNROLL-NEXT: [[TMP54:%.*]] = load ptr, ptr [[ARRAYIDX_5]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_5:%.*]] = getelementptr inbounds i32, ptr [[TMP54]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP55:%.*]] = load i32, ptr [[ARRAYIDX11_2_5]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_5:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP56:%.*]] = load i32, ptr [[ARRAYIDX13_2_5]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_5:%.*]] = add nsw i32 [[TMP56]], [[TMP55]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_5]], ptr [[ARRAYIDX13_2_5]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_5:%.*]] + ; CHECK-UNROLL: for.body7.3.5: + ; CHECK-UNROLL-NEXT: [[TMP57:%.*]] = load ptr, ptr [[ARRAYIDX_5]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_5:%.*]] = getelementptr inbounds i32, ptr [[TMP57]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP58:%.*]] = load i32, ptr [[ARRAYIDX11_3_5]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_5:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP59:%.*]] = load i32, ptr [[ARRAYIDX13_3_5]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_5:%.*]] = add nsw i32 [[TMP59]], [[TMP58]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_5]], ptr [[ARRAYIDX13_3_5]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_5:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.5: + ; CHECK-UNROLL-NEXT: [[CMP1_6:%.*]] = icmp eq i32 6, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_6]], label [[CLEANUP]], label [[IF_END_6:%.*]] + ; CHECK-UNROLL: if.end.6: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 6 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_6:%.*]] + ; CHECK-UNROLL: for.cond4.6: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_6:%.*]] + ; CHECK-UNROLL: for.body7.6: + ; CHECK-UNROLL-NEXT: [[TMP60:%.*]] = load ptr, ptr [[ARRAYIDX_6]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP61:%.*]] = load i32, ptr [[TMP60]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP62:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_6:%.*]] = add nsw i32 [[TMP62]], [[TMP61]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_6]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_6:%.*]] + ; CHECK-UNROLL: for.body7.1.6: + ; CHECK-UNROLL-NEXT: [[TMP63:%.*]] = load ptr, ptr [[ARRAYIDX_6]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_6:%.*]] = getelementptr inbounds i32, ptr [[TMP63]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP64:%.*]] = load i32, ptr [[ARRAYIDX11_1_6]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_6:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP65:%.*]] = load i32, ptr [[ARRAYIDX13_1_6]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_6:%.*]] = add nsw i32 [[TMP65]], [[TMP64]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_6]], ptr [[ARRAYIDX13_1_6]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_6:%.*]] + ; CHECK-UNROLL: for.body7.2.6: + ; CHECK-UNROLL-NEXT: [[TMP66:%.*]] = load ptr, ptr [[ARRAYIDX_6]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_6:%.*]] = getelementptr inbounds i32, ptr [[TMP66]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP67:%.*]] = load i32, ptr [[ARRAYIDX11_2_6]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_6:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP68:%.*]] = load i32, ptr [[ARRAYIDX13_2_6]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_6:%.*]] = add nsw i32 [[TMP68]], [[TMP67]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_6]], ptr [[ARRAYIDX13_2_6]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_6:%.*]] + ; CHECK-UNROLL: for.body7.3.6: + ; CHECK-UNROLL-NEXT: [[TMP69:%.*]] = load ptr, ptr [[ARRAYIDX_6]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_6:%.*]] = getelementptr inbounds i32, ptr [[TMP69]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP70:%.*]] = load i32, ptr [[ARRAYIDX11_3_6]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_6:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP71:%.*]] = load i32, ptr [[ARRAYIDX13_3_6]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_6:%.*]] = add nsw i32 [[TMP71]], [[TMP70]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_6]], ptr [[ARRAYIDX13_3_6]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_6:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.6: + ; CHECK-UNROLL-NEXT: [[CMP1_7:%.*]] = icmp eq i32 7, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_7]], label [[CLEANUP]], label [[IF_END_7:%.*]] + ; CHECK-UNROLL: if.end.7: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 7 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_7:%.*]] + ; CHECK-UNROLL: for.cond4.7: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_7:%.*]] + ; CHECK-UNROLL: for.body7.7: + ; CHECK-UNROLL-NEXT: [[TMP72:%.*]] = load ptr, ptr [[ARRAYIDX_7]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP73:%.*]] = load i32, ptr [[TMP72]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP74:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_7:%.*]] = add nsw i32 [[TMP74]], [[TMP73]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_7]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_7:%.*]] + ; CHECK-UNROLL: for.body7.1.7: + ; CHECK-UNROLL-NEXT: [[TMP75:%.*]] = load ptr, ptr [[ARRAYIDX_7]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_7:%.*]] = getelementptr inbounds i32, ptr [[TMP75]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP76:%.*]] = load i32, ptr [[ARRAYIDX11_1_7]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_7:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP77:%.*]] = load i32, ptr [[ARRAYIDX13_1_7]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_7:%.*]] = add nsw i32 [[TMP77]], [[TMP76]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_7]], ptr [[ARRAYIDX13_1_7]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_7:%.*]] + ; CHECK-UNROLL: for.body7.2.7: + ; CHECK-UNROLL-NEXT: [[TMP78:%.*]] = load ptr, ptr [[ARRAYIDX_7]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_7:%.*]] = getelementptr inbounds i32, ptr [[TMP78]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP79:%.*]] = load i32, ptr [[ARRAYIDX11_2_7]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_7:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP80:%.*]] = load i32, ptr [[ARRAYIDX13_2_7]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_7:%.*]] = add nsw i32 [[TMP80]], [[TMP79]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_7]], ptr [[ARRAYIDX13_2_7]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_7:%.*]] + ; CHECK-UNROLL: for.body7.3.7: + ; CHECK-UNROLL-NEXT: [[TMP81:%.*]] = load ptr, ptr [[ARRAYIDX_7]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_7:%.*]] = getelementptr inbounds i32, ptr [[TMP81]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP82:%.*]] = load i32, ptr [[ARRAYIDX11_3_7]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_7:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP83:%.*]] = load i32, ptr [[ARRAYIDX13_3_7]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_7:%.*]] = add nsw i32 [[TMP83]], [[TMP82]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_7]], ptr [[ARRAYIDX13_3_7]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_7:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.7: + ; CHECK-UNROLL-NEXT: [[CMP1_8:%.*]] = icmp eq i32 8, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_8]], label [[CLEANUP]], label [[IF_END_8:%.*]] + ; CHECK-UNROLL: if.end.8: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_8:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 8 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_8:%.*]] + ; CHECK-UNROLL: for.cond4.8: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_8:%.*]] + ; CHECK-UNROLL: for.body7.8: + ; CHECK-UNROLL-NEXT: [[TMP84:%.*]] = load ptr, ptr [[ARRAYIDX_8]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP85:%.*]] = load i32, ptr [[TMP84]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP86:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_8:%.*]] = add nsw i32 [[TMP86]], [[TMP85]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_8]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_8:%.*]] + ; CHECK-UNROLL: for.body7.1.8: + ; CHECK-UNROLL-NEXT: [[TMP87:%.*]] = load ptr, ptr [[ARRAYIDX_8]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_8:%.*]] = getelementptr inbounds i32, ptr [[TMP87]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP88:%.*]] = load i32, ptr [[ARRAYIDX11_1_8]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_8:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP89:%.*]] = load i32, ptr [[ARRAYIDX13_1_8]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_8:%.*]] = add nsw i32 [[TMP89]], [[TMP88]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_8]], ptr [[ARRAYIDX13_1_8]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_8:%.*]] + ; CHECK-UNROLL: for.body7.2.8: + ; CHECK-UNROLL-NEXT: [[TMP90:%.*]] = load ptr, ptr [[ARRAYIDX_8]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_8:%.*]] = getelementptr inbounds i32, ptr [[TMP90]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP91:%.*]] = load i32, ptr [[ARRAYIDX11_2_8]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_8:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP92:%.*]] = load i32, ptr [[ARRAYIDX13_2_8]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_8:%.*]] = add nsw i32 [[TMP92]], [[TMP91]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_8]], ptr [[ARRAYIDX13_2_8]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_8:%.*]] + ; CHECK-UNROLL: for.body7.3.8: + ; CHECK-UNROLL-NEXT: [[TMP93:%.*]] = load ptr, ptr [[ARRAYIDX_8]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_8:%.*]] = getelementptr inbounds i32, ptr [[TMP93]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP94:%.*]] = load i32, ptr [[ARRAYIDX11_3_8]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_8:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP95:%.*]] = load i32, ptr [[ARRAYIDX13_3_8]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_8:%.*]] = add nsw i32 [[TMP95]], [[TMP94]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_8]], ptr [[ARRAYIDX13_3_8]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_8:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.8: + ; CHECK-UNROLL-NEXT: [[CMP1_9:%.*]] = icmp eq i32 9, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_9]], label [[CLEANUP]], label [[IF_END_9:%.*]] + ; CHECK-UNROLL: if.end.9: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_9:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 9 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_9:%.*]] + ; CHECK-UNROLL: for.cond4.9: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_9:%.*]] + ; CHECK-UNROLL: for.body7.9: + ; CHECK-UNROLL-NEXT: [[TMP96:%.*]] = load ptr, ptr [[ARRAYIDX_9]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP97:%.*]] = load i32, ptr [[TMP96]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP98:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_9:%.*]] = add nsw i32 [[TMP98]], [[TMP97]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_9]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_9:%.*]] + ; CHECK-UNROLL: for.body7.1.9: + ; CHECK-UNROLL-NEXT: [[TMP99:%.*]] = load ptr, ptr [[ARRAYIDX_9]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_9:%.*]] = getelementptr inbounds i32, ptr [[TMP99]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX11_1_9]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_9:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP101:%.*]] = load i32, ptr [[ARRAYIDX13_1_9]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_9:%.*]] = add nsw i32 [[TMP101]], [[TMP100]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_9]], ptr [[ARRAYIDX13_1_9]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_9:%.*]] + ; CHECK-UNROLL: for.body7.2.9: + ; CHECK-UNROLL-NEXT: [[TMP102:%.*]] = load ptr, ptr [[ARRAYIDX_9]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_9:%.*]] = getelementptr inbounds i32, ptr [[TMP102]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP103:%.*]] = load i32, ptr [[ARRAYIDX11_2_9]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_9:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP104:%.*]] = load i32, ptr [[ARRAYIDX13_2_9]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_9:%.*]] = add nsw i32 [[TMP104]], [[TMP103]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_9]], ptr [[ARRAYIDX13_2_9]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_9:%.*]] + ; CHECK-UNROLL: for.body7.3.9: + ; CHECK-UNROLL-NEXT: [[TMP105:%.*]] = load ptr, ptr [[ARRAYIDX_9]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_9:%.*]] = getelementptr inbounds i32, ptr [[TMP105]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP106:%.*]] = load i32, ptr [[ARRAYIDX11_3_9]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_9:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP107:%.*]] = load i32, ptr [[ARRAYIDX13_3_9]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_9:%.*]] = add nsw i32 [[TMP107]], [[TMP106]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_9]], ptr [[ARRAYIDX13_3_9]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_9:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.9: + ; CHECK-UNROLL-NEXT: [[CMP1_10:%.*]] = icmp eq i32 10, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_10]], label [[CLEANUP]], label [[IF_END_10:%.*]] + ; CHECK-UNROLL: if.end.10: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_10:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 10 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_10:%.*]] + ; CHECK-UNROLL: for.cond4.10: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_10:%.*]] + ; CHECK-UNROLL: for.body7.10: + ; CHECK-UNROLL-NEXT: [[TMP108:%.*]] = load ptr, ptr [[ARRAYIDX_10]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP109:%.*]] = load i32, ptr [[TMP108]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP110:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_10:%.*]] = add nsw i32 [[TMP110]], [[TMP109]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_10]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_10:%.*]] + ; CHECK-UNROLL: for.body7.1.10: + ; CHECK-UNROLL-NEXT: [[TMP111:%.*]] = load ptr, ptr [[ARRAYIDX_10]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_10:%.*]] = getelementptr inbounds i32, ptr [[TMP111]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP112:%.*]] = load i32, ptr [[ARRAYIDX11_1_10]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_10:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP113:%.*]] = load i32, ptr [[ARRAYIDX13_1_10]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_10:%.*]] = add nsw i32 [[TMP113]], [[TMP112]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_10]], ptr [[ARRAYIDX13_1_10]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_10:%.*]] + ; CHECK-UNROLL: for.body7.2.10: + ; CHECK-UNROLL-NEXT: [[TMP114:%.*]] = load ptr, ptr [[ARRAYIDX_10]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_10:%.*]] = getelementptr inbounds i32, ptr [[TMP114]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP115:%.*]] = load i32, ptr [[ARRAYIDX11_2_10]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_10:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP116:%.*]] = load i32, ptr [[ARRAYIDX13_2_10]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_10:%.*]] = add nsw i32 [[TMP116]], [[TMP115]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_10]], ptr [[ARRAYIDX13_2_10]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_10:%.*]] + ; CHECK-UNROLL: for.body7.3.10: + ; CHECK-UNROLL-NEXT: [[TMP117:%.*]] = load ptr, ptr [[ARRAYIDX_10]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_10:%.*]] = getelementptr inbounds i32, ptr [[TMP117]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP118:%.*]] = load i32, ptr [[ARRAYIDX11_3_10]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_10:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP119:%.*]] = load i32, ptr [[ARRAYIDX13_3_10]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_10:%.*]] = add nsw i32 [[TMP119]], [[TMP118]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_10]], ptr [[ARRAYIDX13_3_10]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_10:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.10: + ; CHECK-UNROLL-NEXT: [[CMP1_11:%.*]] = icmp eq i32 11, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_11]], label [[CLEANUP]], label [[IF_END_11:%.*]] + ; CHECK-UNROLL: if.end.11: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_11:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 11 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_11:%.*]] + ; CHECK-UNROLL: for.cond4.11: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_11:%.*]] + ; CHECK-UNROLL: for.body7.11: + ; CHECK-UNROLL-NEXT: [[TMP120:%.*]] = load ptr, ptr [[ARRAYIDX_11]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP121:%.*]] = load i32, ptr [[TMP120]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP122:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_119:%.*]] = add nsw i32 [[TMP122]], [[TMP121]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_119]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_11:%.*]] + ; CHECK-UNROLL: for.body7.1.11: + ; CHECK-UNROLL-NEXT: [[TMP123:%.*]] = load ptr, ptr [[ARRAYIDX_11]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_11:%.*]] = getelementptr inbounds i32, ptr [[TMP123]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP124:%.*]] = load i32, ptr [[ARRAYIDX11_1_11]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_11:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP125:%.*]] = load i32, ptr [[ARRAYIDX13_1_11]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_11:%.*]] = add nsw i32 [[TMP125]], [[TMP124]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_11]], ptr [[ARRAYIDX13_1_11]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_11:%.*]] + ; CHECK-UNROLL: for.body7.2.11: + ; CHECK-UNROLL-NEXT: [[TMP126:%.*]] = load ptr, ptr [[ARRAYIDX_11]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_11:%.*]] = getelementptr inbounds i32, ptr [[TMP126]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP127:%.*]] = load i32, ptr [[ARRAYIDX11_2_11]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_11:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP128:%.*]] = load i32, ptr [[ARRAYIDX13_2_11]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_11:%.*]] = add nsw i32 [[TMP128]], [[TMP127]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_11]], ptr [[ARRAYIDX13_2_11]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_11:%.*]] + ; CHECK-UNROLL: for.body7.3.11: + ; CHECK-UNROLL-NEXT: [[TMP129:%.*]] = load ptr, ptr [[ARRAYIDX_11]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_11:%.*]] = getelementptr inbounds i32, ptr [[TMP129]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP130:%.*]] = load i32, ptr [[ARRAYIDX11_3_11]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_11:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP131:%.*]] = load i32, ptr [[ARRAYIDX13_3_11]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_11:%.*]] = add nsw i32 [[TMP131]], [[TMP130]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_11]], ptr [[ARRAYIDX13_3_11]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_11:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.11: + ; CHECK-UNROLL-NEXT: [[CMP1_12:%.*]] = icmp eq i32 12, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_12]], label [[CLEANUP]], label [[IF_END_12:%.*]] + ; CHECK-UNROLL: if.end.12: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_12:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 12 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_12:%.*]] + ; CHECK-UNROLL: for.cond4.12: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1210:%.*]] + ; CHECK-UNROLL: for.body7.1210: + ; CHECK-UNROLL-NEXT: [[TMP132:%.*]] = load ptr, ptr [[ARRAYIDX_12]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP133:%.*]] = load i32, ptr [[TMP132]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP134:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_12:%.*]] = add nsw i32 [[TMP134]], [[TMP133]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_12]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_12:%.*]] + ; CHECK-UNROLL: for.body7.1.12: + ; CHECK-UNROLL-NEXT: [[TMP135:%.*]] = load ptr, ptr [[ARRAYIDX_12]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_12:%.*]] = getelementptr inbounds i32, ptr [[TMP135]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP136:%.*]] = load i32, ptr [[ARRAYIDX11_1_12]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_12:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP137:%.*]] = load i32, ptr [[ARRAYIDX13_1_12]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_12:%.*]] = add nsw i32 [[TMP137]], [[TMP136]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_12]], ptr [[ARRAYIDX13_1_12]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_12:%.*]] + ; CHECK-UNROLL: for.body7.2.12: + ; CHECK-UNROLL-NEXT: [[TMP138:%.*]] = load ptr, ptr [[ARRAYIDX_12]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_12:%.*]] = getelementptr inbounds i32, ptr [[TMP138]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP139:%.*]] = load i32, ptr [[ARRAYIDX11_2_12]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_12:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP140:%.*]] = load i32, ptr [[ARRAYIDX13_2_12]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_12:%.*]] = add nsw i32 [[TMP140]], [[TMP139]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_12]], ptr [[ARRAYIDX13_2_12]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_12:%.*]] + ; CHECK-UNROLL: for.body7.3.12: + ; CHECK-UNROLL-NEXT: [[TMP141:%.*]] = load ptr, ptr [[ARRAYIDX_12]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_12:%.*]] = getelementptr inbounds i32, ptr [[TMP141]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP142:%.*]] = load i32, ptr [[ARRAYIDX11_3_12]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_12:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP143:%.*]] = load i32, ptr [[ARRAYIDX13_3_12]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_12:%.*]] = add nsw i32 [[TMP143]], [[TMP142]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_12]], ptr [[ARRAYIDX13_3_12]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_12:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.12: + ; CHECK-UNROLL-NEXT: [[CMP1_13:%.*]] = icmp eq i32 13, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_13]], label [[CLEANUP]], label [[IF_END_13:%.*]] + ; CHECK-UNROLL: if.end.13: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_13:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 13 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_13:%.*]] + ; CHECK-UNROLL: for.cond4.13: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_13:%.*]] + ; CHECK-UNROLL: for.body7.13: + ; CHECK-UNROLL-NEXT: [[TMP144:%.*]] = load ptr, ptr [[ARRAYIDX_13]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP145:%.*]] = load i32, ptr [[TMP144]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP146:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_13:%.*]] = add nsw i32 [[TMP146]], [[TMP145]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_13]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_13:%.*]] + ; CHECK-UNROLL: for.body7.1.13: + ; CHECK-UNROLL-NEXT: [[TMP147:%.*]] = load ptr, ptr [[ARRAYIDX_13]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_13:%.*]] = getelementptr inbounds i32, ptr [[TMP147]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP148:%.*]] = load i32, ptr [[ARRAYIDX11_1_13]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_13:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP149:%.*]] = load i32, ptr [[ARRAYIDX13_1_13]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_13:%.*]] = add nsw i32 [[TMP149]], [[TMP148]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_13]], ptr [[ARRAYIDX13_1_13]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_13:%.*]] + ; CHECK-UNROLL: for.body7.2.13: + ; CHECK-UNROLL-NEXT: [[TMP150:%.*]] = load ptr, ptr [[ARRAYIDX_13]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_13:%.*]] = getelementptr inbounds i32, ptr [[TMP150]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP151:%.*]] = load i32, ptr [[ARRAYIDX11_2_13]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_13:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP152:%.*]] = load i32, ptr [[ARRAYIDX13_2_13]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_13:%.*]] = add nsw i32 [[TMP152]], [[TMP151]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_13]], ptr [[ARRAYIDX13_2_13]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_13:%.*]] + ; CHECK-UNROLL: for.body7.3.13: + ; CHECK-UNROLL-NEXT: [[TMP153:%.*]] = load ptr, ptr [[ARRAYIDX_13]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_13:%.*]] = getelementptr inbounds i32, ptr [[TMP153]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP154:%.*]] = load i32, ptr [[ARRAYIDX11_3_13]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_13:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP155:%.*]] = load i32, ptr [[ARRAYIDX13_3_13]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_13:%.*]] = add nsw i32 [[TMP155]], [[TMP154]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_13]], ptr [[ARRAYIDX13_3_13]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_13:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.13: + ; CHECK-UNROLL-NEXT: [[CMP1_14:%.*]] = icmp eq i32 14, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_14]], label [[CLEANUP]], label [[IF_END_14:%.*]] + ; CHECK-UNROLL: if.end.14: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_14:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 14 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_14:%.*]] + ; CHECK-UNROLL: for.cond4.14: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_14:%.*]] + ; CHECK-UNROLL: for.body7.14: + ; CHECK-UNROLL-NEXT: [[TMP156:%.*]] = load ptr, ptr [[ARRAYIDX_14]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP157:%.*]] = load i32, ptr [[TMP156]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP158:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_14:%.*]] = add nsw i32 [[TMP158]], [[TMP157]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_14]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_14:%.*]] + ; CHECK-UNROLL: for.body7.1.14: + ; CHECK-UNROLL-NEXT: [[TMP159:%.*]] = load ptr, ptr [[ARRAYIDX_14]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_14:%.*]] = getelementptr inbounds i32, ptr [[TMP159]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP160:%.*]] = load i32, ptr [[ARRAYIDX11_1_14]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_14:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP161:%.*]] = load i32, ptr [[ARRAYIDX13_1_14]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_14:%.*]] = add nsw i32 [[TMP161]], [[TMP160]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_14]], ptr [[ARRAYIDX13_1_14]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_14:%.*]] + ; CHECK-UNROLL: for.body7.2.14: + ; CHECK-UNROLL-NEXT: [[TMP162:%.*]] = load ptr, ptr [[ARRAYIDX_14]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_14:%.*]] = getelementptr inbounds i32, ptr [[TMP162]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP163:%.*]] = load i32, ptr [[ARRAYIDX11_2_14]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_14:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP164:%.*]] = load i32, ptr [[ARRAYIDX13_2_14]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_14:%.*]] = add nsw i32 [[TMP164]], [[TMP163]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_14]], ptr [[ARRAYIDX13_2_14]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_14:%.*]] + ; CHECK-UNROLL: for.body7.3.14: + ; CHECK-UNROLL-NEXT: [[TMP165:%.*]] = load ptr, ptr [[ARRAYIDX_14]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_14:%.*]] = getelementptr inbounds i32, ptr [[TMP165]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP166:%.*]] = load i32, ptr [[ARRAYIDX11_3_14]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_14:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP167:%.*]] = load i32, ptr [[ARRAYIDX13_3_14]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_14:%.*]] = add nsw i32 [[TMP167]], [[TMP166]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_14]], ptr [[ARRAYIDX13_3_14]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_14:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.14: + ; CHECK-UNROLL-NEXT: [[CMP1_15:%.*]] = icmp eq i32 15, [[DIMS]] + ; CHECK-UNROLL-NEXT: br i1 [[CMP1_15]], label [[CLEANUP]], label [[IF_END_15:%.*]] + ; CHECK-UNROLL: if.end.15: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_15:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 15 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_15:%.*]] + ; CHECK-UNROLL: for.cond4.15: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_15:%.*]] + ; CHECK-UNROLL: for.body7.15: + ; CHECK-UNROLL-NEXT: [[TMP168:%.*]] = load ptr, ptr [[ARRAYIDX_15]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP169:%.*]] = load i32, ptr [[TMP168]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP170:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_15:%.*]] = add nsw i32 [[TMP170]], [[TMP169]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_15]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_15:%.*]] + ; CHECK-UNROLL: for.body7.1.15: + ; CHECK-UNROLL-NEXT: [[TMP171:%.*]] = load ptr, ptr [[ARRAYIDX_15]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_15:%.*]] = getelementptr inbounds i32, ptr [[TMP171]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP172:%.*]] = load i32, ptr [[ARRAYIDX11_1_15]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_15:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP173:%.*]] = load i32, ptr [[ARRAYIDX13_1_15]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_15:%.*]] = add nsw i32 [[TMP173]], [[TMP172]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_15]], ptr [[ARRAYIDX13_1_15]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_15:%.*]] + ; CHECK-UNROLL: for.body7.2.15: + ; CHECK-UNROLL-NEXT: [[TMP174:%.*]] = load ptr, ptr [[ARRAYIDX_15]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_15:%.*]] = getelementptr inbounds i32, ptr [[TMP174]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP175:%.*]] = load i32, ptr [[ARRAYIDX11_2_15]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_15:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP176:%.*]] = load i32, ptr [[ARRAYIDX13_2_15]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_15:%.*]] = add nsw i32 [[TMP176]], [[TMP175]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_15]], ptr [[ARRAYIDX13_2_15]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_15:%.*]] + ; CHECK-UNROLL: for.body7.3.15: + ; CHECK-UNROLL-NEXT: [[TMP177:%.*]] = load ptr, ptr [[ARRAYIDX_15]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_15:%.*]] = getelementptr inbounds i32, ptr [[TMP177]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP178:%.*]] = load i32, ptr [[ARRAYIDX11_3_15]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_15:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP179:%.*]] = load i32, ptr [[ARRAYIDX13_3_15]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_15:%.*]] = add nsw i32 [[TMP179]], [[TMP178]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_15]], ptr [[ARRAYIDX13_3_15]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_15:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.15: + ; CHECK-UNROLL-NEXT: br i1 true, label [[CLEANUP]], label [[IF_END_16:%.*]] + ; CHECK-UNROLL: if.end.16: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_16:%.*]] = getelementptr inbounds ptr, ptr [[ARR]], i64 16 + ; CHECK-UNROLL-NEXT: br label [[FOR_COND4_16:%.*]] + ; CHECK-UNROLL: for.cond4.16: + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_16:%.*]] + ; CHECK-UNROLL: for.body7.16: + ; CHECK-UNROLL-NEXT: [[TMP180:%.*]] = load ptr, ptr [[ARRAYIDX_16]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP181:%.*]] = load i32, ptr [[TMP180]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP182:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_16:%.*]] = add nsw i32 [[TMP182]], [[TMP181]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_16]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1_16:%.*]] + ; CHECK-UNROLL: for.body7.1.16: + ; CHECK-UNROLL-NEXT: [[TMP183:%.*]] = load ptr, ptr [[ARRAYIDX_16]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1_16:%.*]] = getelementptr inbounds i32, ptr [[TMP183]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP184:%.*]] = load i32, ptr [[ARRAYIDX11_1_16]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1_16:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP185:%.*]] = load i32, ptr [[ARRAYIDX13_1_16]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1_16:%.*]] = add nsw i32 [[TMP185]], [[TMP184]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1_16]], ptr [[ARRAYIDX13_1_16]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2_16:%.*]] + ; CHECK-UNROLL: for.body7.2.16: + ; CHECK-UNROLL-NEXT: [[TMP186:%.*]] = load ptr, ptr [[ARRAYIDX_16]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2_16:%.*]] = getelementptr inbounds i32, ptr [[TMP186]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP187:%.*]] = load i32, ptr [[ARRAYIDX11_2_16]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2_16:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARRAYIDX13_2_16]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2_16:%.*]] = add nsw i32 [[TMP188]], [[TMP187]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2_16]], ptr [[ARRAYIDX13_2_16]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3_16:%.*]] + ; CHECK-UNROLL: for.body7.3.16: + ; CHECK-UNROLL-NEXT: [[TMP189:%.*]] = load ptr, ptr [[ARRAYIDX_16]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3_16:%.*]] = getelementptr inbounds i32, ptr [[TMP189]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP190:%.*]] = load i32, ptr [[ARRAYIDX11_3_16]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3_16:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP191:%.*]] = load i32, ptr [[ARRAYIDX13_3_16]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3_16:%.*]] = add nsw i32 [[TMP191]], [[TMP190]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3_16]], ptr [[ARRAYIDX13_3_16]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6_16:%.*]] + ; CHECK-UNROLL: for.cond.cleanup6.16: + ; CHECK-UNROLL-NEXT: unreachable + ; CHECK-UNROLL: for.body7: + ; CHECK-UNROLL-NEXT: [[TMP192:%.*]] = load ptr, ptr [[ARR]], align 8 + ; CHECK-UNROLL-NEXT: [[TMP193:%.*]] = load i32, ptr [[TMP192]], align 4 + ; CHECK-UNROLL-NEXT: [[TMP194:%.*]] = load i32, ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP194]], [[TMP193]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14]], ptr [[OUT]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_1:%.*]] + ; CHECK-UNROLL: for.body7.1: + ; CHECK-UNROLL-NEXT: [[TMP195:%.*]] = load ptr, ptr [[ARR]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_1:%.*]] = getelementptr inbounds i32, ptr [[TMP195]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP196:%.*]] = load i32, ptr [[ARRAYIDX11_1]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_1:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 1 + ; CHECK-UNROLL-NEXT: [[TMP197:%.*]] = load i32, ptr [[ARRAYIDX13_1]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_1:%.*]] = add nsw i32 [[TMP197]], [[TMP196]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_1]], ptr [[ARRAYIDX13_1]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_2:%.*]] + ; CHECK-UNROLL: for.body7.2: + ; CHECK-UNROLL-NEXT: [[TMP198:%.*]] = load ptr, ptr [[ARR]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_2:%.*]] = getelementptr inbounds i32, ptr [[TMP198]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP199:%.*]] = load i32, ptr [[ARRAYIDX11_2]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_2:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 2 + ; CHECK-UNROLL-NEXT: [[TMP200:%.*]] = load i32, ptr [[ARRAYIDX13_2]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_2:%.*]] = add nsw i32 [[TMP200]], [[TMP199]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_2]], ptr [[ARRAYIDX13_2]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br label [[FOR_BODY7_3:%.*]] + ; CHECK-UNROLL: for.body7.3: + ; CHECK-UNROLL-NEXT: [[TMP201:%.*]] = load ptr, ptr [[ARR]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_3:%.*]] = getelementptr inbounds i32, ptr [[TMP201]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP202:%.*]] = load i32, ptr [[ARRAYIDX11_3]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_3:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 3 + ; CHECK-UNROLL-NEXT: [[TMP203:%.*]] = load i32, ptr [[ARRAYIDX13_3]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_3:%.*]] = add nsw i32 [[TMP203]], [[TMP202]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_3]], ptr [[ARRAYIDX13_3]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: br i1 false, label [[FOR_BODY7_4]], label [[FOR_COND_CLEANUP6:%.*]] + ; CHECK-UNROLL: for.body7.4: + ; CHECK-UNROLL-NEXT: [[ARRAYIDX_LCSSA:%.*]] = phi ptr [ [[ARR]], [[FOR_BODY7_3]] ], [ [[ARRAYIDX_1]], [[FOR_BODY7_3_1]] ], [ [[ARRAYIDX_2]], [[FOR_BODY7_3_2]] ], [ [[ARRAYIDX_3]], [[FOR_BODY7_3_3]] ], [ [[ARRAYIDX_4]], [[FOR_BODY7_3_4]] ], [ [[ARRAYIDX_5]], [[FOR_BODY7_3_5]] ], [ [[ARRAYIDX_6]], [[FOR_BODY7_3_6]] ], [ [[ARRAYIDX_7]], [[FOR_BODY7_3_7]] ], [ [[ARRAYIDX_8]], [[FOR_BODY7_3_8]] ], [ [[ARRAYIDX_9]], [[FOR_BODY7_3_9]] ], [ [[ARRAYIDX_10]], [[FOR_BODY7_3_10]] ], [ [[ARRAYIDX_11]], [[FOR_BODY7_3_11]] ], [ [[ARRAYIDX_12]], [[FOR_BODY7_3_12]] ], [ [[ARRAYIDX_13]], [[FOR_BODY7_3_13]] ], [ [[ARRAYIDX_14]], [[FOR_BODY7_3_14]] ], [ [[ARRAYIDX_15]], [[FOR_BODY7_3_15]] ], [ [[ARRAYIDX_16]], [[FOR_BODY7_3_16]] ] + ; CHECK-UNROLL-NEXT: [[TMP204:%.*]] = load ptr, ptr [[ARRAYIDX_LCSSA]], align 8 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX11_4:%.*]] = getelementptr inbounds i32, ptr [[TMP204]], i64 4 + ; CHECK-UNROLL-NEXT: [[TMP205:%.*]] = load i32, ptr [[ARRAYIDX11_4]], align 4 + ; CHECK-UNROLL-NEXT: [[ARRAYIDX13_4:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 4 + ; CHECK-UNROLL-NEXT: [[TMP206:%.*]] = load i32, ptr [[ARRAYIDX13_4]], align 4 + ; CHECK-UNROLL-NEXT: [[ADD14_4:%.*]] = add nsw i32 [[TMP206]], [[TMP205]] + ; CHECK-UNROLL-NEXT: store i32 [[ADD14_4]], ptr [[ARRAYIDX13_4]], align 4 + ; CHECK-UNROLL-NEXT: call void @_Z3barv() + ; CHECK-UNROLL-NEXT: unreachable + ; CHECK-UNROLL: cleanup: + ; CHECK-UNROLL-NEXT: ret void + ; + entry: + br label %for.cond -for.cond: ; preds = %for.cond.cleanup6, %entry - %Dim.0 = phi i32 [ 0, %entry ], [ %inc16, %for.cond.cleanup6 ] - %Idx.addr.0 = phi i32 [ %Idx, %entry ], [ %add, %for.cond.cleanup6 ] - %cmp = icmp slt i32 %Dim.0, 16 - br i1 %cmp, label %for.body, label %for.cond.cleanup + for.cond: ; preds = %for.cond.cleanup6, %entry + %Dim.0 = phi i32 [ 0, %entry ], [ %inc16, %for.cond.cleanup6 ] + %Idx.addr.0 = phi i32 [ %Idx, %entry ], [ %add, %for.cond.cleanup6 ] + %cmp = icmp slt i32 %Dim.0, 16 + br i1 %cmp, label %for.body, label %for.cond.cleanup -for.cond.cleanup: ; preds = %for.cond - br label %cleanup + for.cond.cleanup: ; preds = %for.cond + br label %cleanup -for.body: ; preds = %for.cond - %cmp1 = icmp eq i32 %Dim.0, %Dims - br i1 %cmp1, label %if.then, label %if.end + for.body: ; preds = %for.cond + %cmp1 = icmp eq i32 %Dim.0, %Dims + br i1 %cmp1, label %if.then, label %if.end -if.then: ; preds = %for.body - br label %cleanup + if.then: ; preds = %for.body + br label %cleanup -if.end: ; preds = %for.body - %idxprom = sext i32 %Dim.0 to i64 - %arrayidx = getelementptr inbounds ptr, ptr %Arr, i64 %idxprom - %0 = load ptr, ptr %arrayidx, align 8 - %idxprom2 = sext i32 %Idx.addr.0 to i64 - %arrayidx3 = getelementptr inbounds i32, ptr %0, i64 %idxprom2 - %1 = load i32, ptr %arrayidx3, align 4 - %add = add nsw i32 %1, 1 - br label %for.cond4 + if.end: ; preds = %for.body + %idxprom = sext i32 %Dim.0 to i64 + %arrayidx = getelementptr inbounds ptr, ptr %Arr, i64 %idxprom + %0 = load ptr, ptr %arrayidx, align 8 + %idxprom2 = sext i32 %Idx.addr.0 to i64 + %arrayidx3 = getelementptr inbounds i32, ptr %0, i64 %idxprom2 + %1 = load i32, ptr %arrayidx3, align 4 + %add = add nsw i32 %1, 1 + br label %for.cond4 -for.cond4: ; preds = %for.body7, %if.end - %arg.0 = phi i32 [ 0, %if.end ], [ %inc, %for.body7 ] - %cmp5 = icmp slt i32 %arg.0, 4 - br i1 %cmp5, label %for.body7, label %for.cond.cleanup6 + for.cond4: ; preds = %for.body7, %if.end + %arg.0 = phi i32 [ 0, %if.end ], [ %inc, %for.body7 ] + %cmp5 = icmp slt i32 %arg.0, 4 + br i1 %cmp5, label %for.body7, label %for.cond.cleanup6 -for.cond.cleanup6: ; preds = %for.cond4 - %inc16 = add nsw i32 %Dim.0, 1 - br label %for.cond, !llvm.loop !0 + for.cond.cleanup6: ; preds = %for.cond4 + %inc16 = add nsw i32 %Dim.0, 1 + br label %for.cond, !llvm.loop !0 -for.body7: ; preds = %for.cond4 - %2 = load ptr, ptr %arrayidx, align 8 - %idxprom10 = sext i32 %arg.0 to i64 - %arrayidx11 = getelementptr inbounds i32, ptr %2, i64 %idxprom10 - %3 = load i32, ptr %arrayidx11, align 4 - %arrayidx13 = getelementptr inbounds i32, ptr %Out, i64 %idxprom10 - %4 = load i32, ptr %arrayidx13, align 4 - %add14 = add nsw i32 %4, %3 - store i32 %add14, ptr %arrayidx13, align 4 - call void @_Z3barv() - %inc = add nsw i32 %arg.0, 1 - br label %for.cond4, !llvm.loop !3 + for.body7: ; preds = %for.cond4 + %2 = load ptr, ptr %arrayidx, align 8 + %idxprom10 = sext i32 %arg.0 to i64 + %arrayidx11 = getelementptr inbounds i32, ptr %2, i64 %idxprom10 + %3 = load i32, ptr %arrayidx11, align 4 + %arrayidx13 = getelementptr inbounds i32, ptr %Out, i64 %idxprom10 + %4 = load i32, ptr %arrayidx13, align 4 + %add14 = add nsw i32 %4, %3 + store i32 %add14, ptr %arrayidx13, align 4 + call void @_Z3barv() + %inc = add nsw i32 %arg.0, 1 + br label %for.cond4, !llvm.loop !3 -cleanup: ; preds = %if.then, %for.cond.cleanup - ret void -} + cleanup: ; preds = %if.then, %for.cond.cleanup + ret void + } - declare void @_Z3barv() + declare void @_Z3barv() + + !0 = distinct !{!0, !1, !2} + !1 = !{!"llvm.loop.mustprogress"} + !2 = !{!"llvm.loop.unroll.enable"} + !3 = distinct !{!3, !1} + ;. + ; CHECK-CFG: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} + ; CHECK-CFG: [[META1]] = !{!"llvm.loop.mustprogress"} + ; CHECK-CFG: [[META2]] = !{!"llvm.loop.unroll.enable"} + ; CHECK-CFG: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]} + ;. -!0 = distinct !{!0, !1, !2} -!1 = !{!"llvm.loop.mustprogress"} -!2 = !{!"llvm.loop.unroll.enable"} -!3 = distinct !{!3, !1} -;. -; CHECK-CFG: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} -; CHECK-CFG: [[META1]] = !{!"llvm.loop.mustprogress"} -; CHECK-CFG: [[META2]] = !{!"llvm.loop.unroll.enable"} -; CHECK-CFG: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]} -;. diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/assert-vplan-cost-model.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/assert-vplan-cost-model.ll new file mode 100644 index 0000000000000..b9e4d4ccfe6ff --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/assert-vplan-cost-model.ll @@ -0,0 +1,138 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=loop-vectorize < %s -S -o - | FileCheck %s + +; REQUIRES: asserts + +target triple = "amdgcn-amd-amdhsa" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind memory(argmem: readwrite) +define protected amdgpu_kernel void @func_int8(ptr addrspace(1) %p_a_grid.coerce, ptr addrspace(1) %p_b_grid.coerce, ptr addrspace(1) %p_c_grid.coerce, i32 %m, i32 %n, i32 %k, i1 %c, i32 %add, i32 %add12) { +; CHECK-LABEL: define protected amdgpu_kernel void @func_int8( +; CHECK-SAME: ptr addrspace(1) [[P_A_GRID_COERCE:%.*]], ptr addrspace(1) [[P_B_GRID_COERCE:%.*]], ptr addrspace(1) [[P_C_GRID_COERCE:%.*]], i32 [[M:%.*]], i32 [[N:%.*]], i32 [[K:%.*]], i1 [[C:%.*]], i32 [[ADD:%.*]], i32 [[ADD12:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: br i1 [[C]], label %[[FOR_COND_PREHEADER:.*]], label %[[IF_END:.*]] +; CHECK: [[FOR_COND_PREHEADER]]: +; CHECK-NEXT: [[CMP1444:%.*]] = icmp sgt i32 [[K]], 0 +; CHECK-NEXT: br i1 [[CMP1444]], label %[[FOR_BODY_LR_PH:.*]], label %[[FOR_COND_CLEANUP:.*]] +; CHECK: [[FOR_BODY_LR_PH]]: +; CHECK-NEXT: [[MUL15:%.*]] = mul nsw i32 [[ADD]], [[K]] +; CHECK-NEXT: [[MUL17:%.*]] = mul nsw i32 [[ADD12]], [[K]] +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[K]], 2 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[K]], 2 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[K]], [[N_MOD_VF]] +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[INDEX]], [[MUL15]] +; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[INDEX]], [[MUL17]] +; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP0]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[P_A_GRID_COERCE]], i64 [[TMP2]] +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr addrspace(1) [[TMP3]], align 1 +; CHECK-NEXT: [[TMP5:%.*]] = sext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[P_B_GRID_COERCE]], i64 [[TMP5]] +; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x i8>, ptr addrspace(1) [[TMP6]], align 1 +; CHECK-NEXT: [[TMP8:%.*]] = zext <2 x i8> [[WIDE_LOAD]] to <2 x i32> +; CHECK-NEXT: [[TMP9:%.*]] = zext <2 x i8> [[WIDE_LOAD1]] to <2 x i32> +; CHECK-NEXT: [[TMP10:%.*]] = mul nuw nsw <2 x i32> [[TMP9]], [[TMP8]] +; CHECK-NEXT: [[TMP11]] = add <2 x i32> [[TMP10]], [[VEC_PHI]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 +; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP11]]) +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[K]], [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_COND_CLEANUP_LOOPEXIT:.*]], label %[[SCALAR_PH]] +; CHECK: [[SCALAR_PH]]: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_LR_PH]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP13]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_LR_PH]] ] +; CHECK-NEXT: br label %[[FOR_BODY:.*]] +; CHECK: [[FOR_COND_CLEANUP_LOOPEXIT]]: +; CHECK-NEXT: [[ADD24_LCSSA:%.*]] = phi i32 [ [[ADD24:%.*]], %[[FOR_BODY]] ], [ [[TMP13]], %[[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[TMP15:%.*]] = trunc i32 [[ADD24_LCSSA]] to i8 +; CHECK-NEXT: br label %[[FOR_COND_CLEANUP]] +; CHECK: [[FOR_COND_CLEANUP]]: +; CHECK-NEXT: [[V_ACC_0_LCSSA:%.*]] = phi i8 [ 0, %[[FOR_COND_PREHEADER]] ], [ [[TMP15]], %[[FOR_COND_CLEANUP_LOOPEXIT]] ] +; CHECK-NEXT: [[MUL25:%.*]] = mul nsw i32 [[ADD]], [[N]] +; CHECK-NEXT: [[ADD26:%.*]] = add nsw i32 [[ADD12]], [[MUL25]] +; CHECK-NEXT: [[IDXPROM27:%.*]] = sext i32 [[ADD26]] to i64 +; CHECK-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[P_C_GRID_COERCE]], i64 [[IDXPROM27]] +; CHECK-NEXT: store i8 [[V_ACC_0_LCSSA]], ptr addrspace(1) [[ARRAYIDX28]], align 1 +; CHECK-NEXT: br label %[[IF_END]] +; CHECK: [[FOR_BODY]]: +; CHECK-NEXT: [[K_IDX_046:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] +; CHECK-NEXT: [[V_ACC_045:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD24]], %[[FOR_BODY]] ] +; CHECK-NEXT: [[ADD16:%.*]] = add nsw i32 [[K_IDX_046]], [[MUL15]] +; CHECK-NEXT: [[ADD18:%.*]] = add nsw i32 [[K_IDX_046]], [[MUL17]] +; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[ADD16]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[P_A_GRID_COERCE]], i64 [[IDXPROM]] +; CHECK-NEXT: [[ARRAYIDX_VAL:%.*]] = load i8, ptr addrspace(1) [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[IDXPROM19:%.*]] = sext i32 [[ADD18]] to i64 +; CHECK-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[P_B_GRID_COERCE]], i64 [[IDXPROM19]] +; CHECK-NEXT: [[ARRAYIDX20_VAL:%.*]] = load i8, ptr addrspace(1) [[ARRAYIDX20]], align 1 +; CHECK-NEXT: [[CONV_I47:%.*]] = zext i8 [[ARRAYIDX_VAL]] to i32 +; CHECK-NEXT: [[CONV_I4248:%.*]] = zext i8 [[ARRAYIDX20_VAL]] to i32 +; CHECK-NEXT: [[MUL23:%.*]] = mul nuw nsw i32 [[CONV_I4248]], [[CONV_I47]] +; CHECK-NEXT: [[ADD24]] = add i32 [[MUL23]], [[V_ACC_045]] +; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[K_IDX_046]], 1 +; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[K]] +; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] +; CHECK: [[IF_END]]: +; CHECK-NEXT: ret void +; +entry: + br i1 %c, label %for.cond.preheader, label %if.end + +for.cond.preheader: ; preds = %entry + %cmp1444 = icmp sgt i32 %k, 0 + br i1 %cmp1444, label %for.body.lr.ph, label %for.cond.cleanup + +for.body.lr.ph: ; preds = %for.cond.preheader + %mul15 = mul nsw i32 %add, %k + %mul17 = mul nsw i32 %add12, %k + br label %for.body + +for.cond.cleanup.loopexit: ; preds = %for.body + %add24.lcssa = phi i32 [ %add24, %for.body ] + %17 = trunc i32 %add24.lcssa to i8 + br label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %for.cond.preheader + %v_acc.0.lcssa = phi i8 [ 0, %for.cond.preheader ], [ %17, %for.cond.cleanup.loopexit ] + %mul25 = mul nsw i32 %add, %n + %add26 = add nsw i32 %add12, %mul25 + %idxprom27 = sext i32 %add26 to i64 + %arrayidx28 = getelementptr inbounds i8, ptr addrspace(1) %p_c_grid.coerce, i64 %idxprom27 + store i8 %v_acc.0.lcssa, ptr addrspace(1) %arrayidx28, align 1 + br label %if.end + +for.body: ; preds = %for.body, %for.body.lr.ph + %k_idx.046 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] + %v_acc.045 = phi i32 [ 0, %for.body.lr.ph ], [ %add24, %for.body ] + %add16 = add nsw i32 %k_idx.046, %mul15 + %add18 = add nsw i32 %k_idx.046, %mul17 + %idxprom = sext i32 %add16 to i64 + %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %p_a_grid.coerce, i64 %idxprom + %arrayidx.val = load i8, ptr addrspace(1) %arrayidx, align 1 + %idxprom19 = sext i32 %add18 to i64 + %arrayidx20 = getelementptr inbounds i8, ptr addrspace(1) %p_b_grid.coerce, i64 %idxprom19 + %arrayidx20.val = load i8, ptr addrspace(1) %arrayidx20, align 1 + %conv.i47 = zext i8 %arrayidx.val to i32 + %conv.i4248 = zext i8 %arrayidx20.val to i32 + %mul23 = mul nuw nsw i32 %conv.i4248, %conv.i47 + %add24 = add i32 %mul23, %v_acc.045 + %inc = add nuw nsw i32 %k_idx.046, 1 + %exitcond.not = icmp eq i32 %inc, %k + br i1 %exitcond.not, label %for.cond.cleanup.loopexit, label %for.body + +if.end: ; preds = %for.cond.cleanup, %entry + ret void +} +;. +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]} +; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]], [[META1]]} +; CHECK: [[META3]] = !{!"llvm.loop.unroll.runtime.disable"} +;. diff --git a/llvm/test/Transforms/OpenMP/always_inline_device.ll b/llvm/test/Transforms/OpenMP/always_inline_device.ll index 9c5b19f7a6c88..b3ff8b455c7cd 100644 --- a/llvm/test/Transforms/OpenMP/always_inline_device.ll +++ b/llvm/test/Transforms/OpenMP/always_inline_device.ll @@ -15,7 +15,7 @@ ; CHECK: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; CHECK: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 ; CHECK: @G = external global i8 -; CHECK: @kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; CHECK: @kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ;. define weak ptx_kernel void @__omp_offloading_fd02_c0934fc2_foo_l4(ptr %dyn) #0 { ; CHECK: Function Attrs: norecurse nounwind diff --git a/llvm/test/Transforms/OpenMP/attributor-DblComplex.ll b/llvm/test/Transforms/OpenMP/attributor-DblComplex.ll new file mode 100644 index 0000000000000..6feffe7fffa1c --- /dev/null +++ b/llvm/test/Transforms/OpenMP/attributor-DblComplex.ll @@ -0,0 +1,1678 @@ +; RUN: opt --mtriple=amdgcn-amd-amdhsa -S -passes='attributor' < %s | FileCheck %s + +; verify that the following test case does not assert in the attributor due +; to addrspace 5 to generic casts seen when compiling for amdgcn-amd-amdhsa +; +; clang++ -O2 -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx908 red-DblComplex.cpp +; +; #include +; std::complex reduce(std::complex dres[], int n) { +; std::complex dinp(0.0, 0.0); +; #pragma omp target teams distribute parallel for map(to: dres) map(tofrom:dinp) reduction(+:dinp) +; for (int i = 0; i < n; i++) { +; dinp += dres[i]; +; } +; return(dinp); +; } + +; CHECK: define internal void @_omp_reduction_shuffle_and_reduce_func + +; ModuleID = 'clang-red-DblComplex-openmp-amdgcn-amd-amdhsa-gfx908.bc' +source_filename = "clang-red-DblComplex.cpp" +target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" +target triple = "amdgcn-amd-amdhsa" + +%struct.ident_t = type { i32, i32, i32, i32, ptr } +%struct.DynamicEnvironmentTy = type { i16 } +%struct.KernelEnvironmentTy = type { %struct.ConfigurationEnvironmentTy, ptr, ptr } +%struct.ConfigurationEnvironmentTy = type { i8, i8, i8, i32, i32, i32, i32, i32, i32 } +%"struct.std::complex" = type { { double, double } } +%struct._globalized_locals_ty = type { %"struct.std::complex" } + +@__omp_plugin_enable_fast_reduction = weak addrspace(1) constant i8 0 +@__omp_rtl_debug_kind = weak_odr hidden local_unnamed_addr addrspace(1) constant i32 0 +@__omp_rtl_assume_teams_oversubscription = weak_odr hidden local_unnamed_addr addrspace(1) constant i32 0 +@__omp_rtl_assume_threads_oversubscription = weak_odr hidden local_unnamed_addr addrspace(1) constant i32 0 +@__omp_rtl_assume_no_thread_state = weak_odr hidden local_unnamed_addr addrspace(1) constant i32 0 +@__omp_rtl_assume_no_nested_parallelism = weak_odr hidden local_unnamed_addr addrspace(1) constant i32 0 +@0 = private unnamed_addr constant [23 x i8] c";unknown;unknown;0;0;;\00", align 1 +@1 = private unnamed_addr addrspace(1) constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, ptr @0 }, align 8 +@__omp_offloading_fd00_426262e_main_l15_dynamic_environment = weak_odr protected addrspace(1) global %struct.DynamicEnvironmentTy zeroinitializer +@__omp_offloading_fd00_426262e_main_l15_kernel_environment = weak_odr protected addrspace(1) constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 2, i32 1, i32 256, i32 0, i32 0, i32 16, i32 1024 }, ptr addrspacecast (ptr addrspace(1) @1 to ptr), ptr addrspacecast (ptr addrspace(1) @__omp_offloading_fd00_426262e_main_l15_dynamic_environment to ptr) } +@2 = private unnamed_addr addrspace(1) constant %struct.ident_t { i32 0, i32 2050, i32 0, i32 22, ptr @0 }, align 8 +@3 = private unnamed_addr addrspace(1) constant %struct.ident_t { i32 0, i32 514, i32 0, i32 22, ptr @0 }, align 8 +@__openmp_nvptx_data_transfer_temporary_storage = weak addrspace(3) global [64 x i32] undef +@4 = private unnamed_addr addrspace(1) constant %struct.ident_t { i32 0, i32 66, i32 0, i32 22, ptr @0 }, align 8 +@__omp_offloading_fd00_426262e_main_l15_wg_size = weak addrspace(1) constant i16 256 +@__omp_offloading_fd00_426262e_main_l15_exec_mode = weak addrspace(1) constant i8 2 +@__oclc_ABI_version = weak_odr hidden local_unnamed_addr addrspace(4) constant i32 500 +@llvm.compiler.used = appending addrspace(1) global [4 x ptr] [ptr addrspacecast (ptr addrspace(1) @__omp_offloading_fd00_426262e_main_l15_exec_mode to ptr), ptr addrspacecast (ptr addrspace(1) @__omp_offloading_fd00_426262e_main_l15_wg_size to ptr), ptr addrspacecast (ptr addrspace(1) @__omp_plugin_enable_fast_reduction to ptr), ptr addrspacecast (ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage to ptr)], section "llvm.metadata" + +; Function Attrs: alwaysinline norecurse nounwind +define weak_odr protected amdgpu_kernel void @__omp_offloading_fd00_426262e_main_l15(ptr noalias noundef %dyn_ptr, ptr noundef nonnull align 8 dereferenceable(16) %dinp, ptr noundef nonnull align 8 dereferenceable(1600) %dres) local_unnamed_addr #0 { +entry: + %dinp1.i = alloca %"struct.std::complex", align 8, addrspace(5) + %.omp.comb.lb.i = alloca i32, align 4, addrspace(5) + %.omp.comb.ub.i = alloca i32, align 4, addrspace(5) + %.omp.stride.i = alloca i32, align 4, addrspace(5) + %.omp.is_last.i = alloca i32, align 4, addrspace(5) + %captured_vars_addrs.i = alloca [4 x ptr], align 8, addrspace(5) + %.omp.reduction.red_list.i = alloca [1 x ptr], align 8, addrspace(5) + %dinp.global1 = addrspacecast ptr %dinp to ptr addrspace(1) + %0 = tail call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @__omp_offloading_fd00_426262e_main_l15_kernel_environment to ptr), ptr %dyn_ptr) #2 + %exec_user_code = icmp eq i32 %0, -1 + br i1 %exec_user_code, label %user_code.entry, label %common.ret + +common.ret: ; preds = %entry, %__omp_offloading_fd00_426262e_main_l15_omp_outlined.exit + ret void + +user_code.entry: ; preds = %entry + %1 = tail call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @1 to ptr)) #2 + call void @llvm.lifetime.start.p5(i64 32, ptr addrspace(5) %captured_vars_addrs.i) + call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) %.omp.reduction.red_list.i) + %dinp1.ascast.i = addrspacecast ptr addrspace(5) %dinp1.i to ptr + %.omp.comb.lb.ascast.i = addrspacecast ptr addrspace(5) %.omp.comb.lb.i to ptr + %.omp.comb.ub.ascast.i = addrspacecast ptr addrspace(5) %.omp.comb.ub.i to ptr + %.omp.stride.ascast.i = addrspacecast ptr addrspace(5) %.omp.stride.i to ptr + %.omp.is_last.ascast.i = addrspacecast ptr addrspace(5) %.omp.is_last.i to ptr + %captured_vars_addrs.ascast.i = addrspacecast ptr addrspace(5) %captured_vars_addrs.i to ptr + %.omp.reduction.red_list.ascast.i = addrspacecast ptr addrspace(5) %.omp.reduction.red_list.i to ptr + call void @llvm.lifetime.start.p5(i64 16, ptr addrspace(5) %dinp1.i) #13, !noalias !9 + %_M_value.imagp.i.i = getelementptr inbounds i8, ptr addrspace(5) %dinp1.i, i32 8 + store double 0.000000e+00, ptr addrspace(5) %dinp1.i, align 8, !noalias !9 + store double 0.000000e+00, ptr addrspace(5) %_M_value.imagp.i.i, align 8, !noalias !9 + call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) %.omp.comb.lb.i) #13, !noalias !9 + store i32 0, ptr addrspace(5) %.omp.comb.lb.i, align 4, !tbaa !12, !noalias !9 + call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) %.omp.comb.ub.i) #13, !noalias !9 + store i32 99, ptr addrspace(5) %.omp.comb.ub.i, align 4, !tbaa !12, !noalias !9 + call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) %.omp.stride.i) #13, !noalias !9 + store i32 1, ptr addrspace(5) %.omp.stride.i, align 4, !tbaa !12, !noalias !9 + call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) %.omp.is_last.i) #13, !noalias !9 + store i32 0, ptr addrspace(5) %.omp.is_last.i, align 4, !tbaa !12, !noalias !9 + %nvptx_num_threads.i = tail call i32 @__kmpc_get_hardware_num_threads_in_block() #2, !noalias !9 + call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @2 to ptr), i32 %1, i32 91, ptr nonnull %.omp.is_last.ascast.i, ptr nonnull %.omp.comb.lb.ascast.i, ptr nonnull %.omp.comb.ub.ascast.i, ptr nonnull %.omp.stride.ascast.i, i32 1, i32 %nvptx_num_threads.i) #2, !noalias !9 + %2 = load i32, ptr addrspace(5) %.omp.comb.ub.i, align 4, !noalias !9 + %cond.i = call i32 @llvm.smin.i32(i32 %2, i32 99) + store i32 %cond.i, ptr addrspace(5) %.omp.comb.ub.i, align 4, !tbaa !12, !noalias !9 + %.omp.iv.012.i = load i32, ptr addrspace(5) %.omp.comb.lb.i, align 4, !noalias !9 + %cmp213.i = icmp slt i32 %.omp.iv.012.i, 100 + br i1 %cmp213.i, label %omp.inner.for.body.lr.ph.i, label %omp.loop.exit.i + +omp.inner.for.body.lr.ph.i: ; preds = %user_code.entry + %3 = getelementptr inbounds i8, ptr addrspace(5) %captured_vars_addrs.i, i32 8 + %4 = getelementptr inbounds i8, ptr addrspace(5) %captured_vars_addrs.i, i32 16 + %5 = getelementptr inbounds i8, ptr addrspace(5) %captured_vars_addrs.i, i32 24 + br label %omp.inner.for.body.i + +omp.inner.for.body.i: ; preds = %omp.inner.for.body.i, %omp.inner.for.body.lr.ph.i + %.omp.iv.015.i = phi i32 [ %.omp.iv.012.i, %omp.inner.for.body.lr.ph.i ], [ %add3.i, %omp.inner.for.body.i ] + %storemerge14.i = phi i32 [ %cond.i, %omp.inner.for.body.lr.ph.i ], [ %cond9.i, %omp.inner.for.body.i ] + %6 = zext i32 %.omp.iv.015.i to i64 + %7 = zext i32 %storemerge14.i to i64 + %8 = inttoptr i64 %6 to ptr + store ptr %8, ptr addrspace(5) %captured_vars_addrs.i, align 8, !tbaa !16, !noalias !9 + %9 = inttoptr i64 %7 to ptr + store ptr %9, ptr addrspace(5) %3, align 8, !tbaa !16, !noalias !9 + store ptr %dinp1.ascast.i, ptr addrspace(5) %4, align 8, !tbaa !16, !noalias !9 + store ptr %dres, ptr addrspace(5) %5, align 8, !tbaa !16, !noalias !9 + call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @1 to ptr), i32 %1, i32 1, i32 -1, i32 -1, ptr nonnull @__omp_offloading_fd00_426262e_main_l15_omp_outlined_omp_outlined, ptr null, ptr nonnull %captured_vars_addrs.ascast.i, i64 4) #2, !noalias !9 + %10 = load i32, ptr addrspace(5) %.omp.stride.i, align 4, !tbaa !12, !noalias !9 + %11 = load i32, ptr addrspace(5) %.omp.comb.lb.i, align 4, !tbaa !12, !noalias !9 + %add3.i = add nsw i32 %11, %10 + store i32 %add3.i, ptr addrspace(5) %.omp.comb.lb.i, align 4, !tbaa !12, !noalias !9 + %12 = load i32, ptr addrspace(5) %.omp.comb.ub.i, align 4, !tbaa !12, !noalias !9 + %add4.i = add nsw i32 %12, %10 + %cond9.i = call i32 @llvm.smin.i32(i32 %add4.i, i32 99) + store i32 %cond9.i, ptr addrspace(5) %.omp.comb.ub.i, align 4, !tbaa !12, !noalias !9 + %cmp2.i = icmp slt i32 %add3.i, 100 + br i1 %cmp2.i, label %omp.inner.for.body.i, label %omp.loop.exit.i + +omp.loop.exit.i: ; preds = %omp.inner.for.body.i, %user_code.entry + call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @2 to ptr), i32 %1) #2, !noalias !9 + call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) %.omp.is_last.i) #2, !noalias !9 + call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) %.omp.stride.i) #2, !noalias !9 + call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) %.omp.comb.ub.i) #2, !noalias !9 + call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) %.omp.comb.lb.i) #2, !noalias !9 + store ptr %dinp1.ascast.i, ptr addrspace(5) %.omp.reduction.red_list.i, align 8, !noalias !9 + %"_openmp_teams_reductions_buffer_$_$ptr.i" = call ptr @__kmpc_reduction_get_fixed_buffer() #2, !noalias !9 + %13 = call i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @1 to ptr), ptr %"_openmp_teams_reductions_buffer_$_$ptr.i", i32 1024, i64 16, ptr nonnull %.omp.reduction.red_list.ascast.i, ptr nonnull @_omp_reduction_shuffle_and_reduce_func.1, ptr nonnull @_omp_reduction_inter_warp_copy_func.2, ptr nonnull @_omp_reduction_list_to_global_copy_func, ptr nonnull @_omp_reduction_list_to_global_reduce_func, ptr nonnull @_omp_reduction_global_to_list_copy_func, ptr nonnull @_omp_reduction_global_to_list_reduce_func) #2, !noalias !9 + %14 = icmp eq i32 %13, 1 + br i1 %14, label %.omp.reduction.then.i, label %__omp_offloading_fd00_426262e_main_l15_omp_outlined.exit + +.omp.reduction.then.i: ; preds = %omp.loop.exit.i + %_M_value.real.i.i.i = load double, ptr addrspace(5) %dinp1.i, align 8, !noalias !9 + %_M_value.imag.i.i.i = load double, ptr addrspace(5) %_M_value.imagp.i.i, align 8, !noalias !9 + %_M_value.real.i.i = load double, ptr addrspace(1) %dinp.global1, align 8, !noalias !9 + %_M_value.imagp.i11.i = getelementptr inbounds i8, ptr addrspace(1) %dinp.global1, i64 8 + %_M_value.imag.i.i = load double, ptr addrspace(1) %_M_value.imagp.i11.i, align 8, !noalias !9 + %add.r.i.i = fadd double %_M_value.real.i.i.i, %_M_value.real.i.i + %add.i.i.i = fadd double %_M_value.imag.i.i.i, %_M_value.imag.i.i + store double %add.r.i.i, ptr addrspace(1) %dinp.global1, align 8, !noalias !9 + store double %add.i.i.i, ptr addrspace(1) %_M_value.imagp.i11.i, align 8, !noalias !9 + br label %__omp_offloading_fd00_426262e_main_l15_omp_outlined.exit + +__omp_offloading_fd00_426262e_main_l15_omp_outlined.exit: ; preds = %omp.loop.exit.i, %.omp.reduction.then.i + call void @llvm.lifetime.end.p5(i64 16, ptr addrspace(5) %dinp1.i) #2, !noalias !9 + call void @llvm.lifetime.end.p5(i64 32, ptr addrspace(5) %captured_vars_addrs.i) + call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) %.omp.reduction.red_list.i) + call void @__kmpc_target_deinit() #2 + br label %common.ret +} + +declare i32 @__kmpc_target_init(ptr, ptr) local_unnamed_addr + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p5(i64 immarg, ptr addrspace(5) nocapture) #1 + +; Function Attrs: nounwind +declare i32 @__kmpc_get_hardware_num_threads_in_block() local_unnamed_addr #2 + +; Function Attrs: nounwind +declare void @__kmpc_distribute_static_init_4(ptr, i32, i32, ptr, ptr, ptr, ptr, i32, i32) local_unnamed_addr #2 + +; Function Attrs: alwaysinline norecurse nounwind +define internal void @__omp_offloading_fd00_426262e_main_l15_omp_outlined_omp_outlined(ptr noalias nocapture noundef readonly %.global_tid., ptr noalias nocapture readnone %.bound_tid., i64 noundef %.previous.lb., i64 noundef %.previous.ub., ptr nocapture noundef nonnull align 8 dereferenceable(16) %dinp, ptr nocapture noundef nonnull readonly align 8 dereferenceable(1600) %dres) #3 { +entry: + %.omp.lb = alloca i32, align 4, addrspace(5) + %.omp.ub = alloca i32, align 4, addrspace(5) + %.omp.stride = alloca i32, align 4, addrspace(5) + %.omp.is_last = alloca i32, align 4, addrspace(5) + %dinp2 = alloca %"struct.std::complex", align 8, addrspace(5) + %.omp.reduction.red_list = alloca [1 x ptr], align 8, addrspace(5) + %.omp.lb.ascast = addrspacecast ptr addrspace(5) %.omp.lb to ptr + %.omp.ub.ascast = addrspacecast ptr addrspace(5) %.omp.ub to ptr + %.omp.stride.ascast = addrspacecast ptr addrspace(5) %.omp.stride to ptr + %.omp.is_last.ascast = addrspacecast ptr addrspace(5) %.omp.is_last to ptr + %dinp2.ascast = addrspacecast ptr addrspace(5) %dinp2 to ptr + %.omp.reduction.red_list.ascast = addrspacecast ptr addrspace(5) %.omp.reduction.red_list to ptr + call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) %.omp.lb) #2 + call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) %.omp.ub) #2 + %conv = trunc i64 %.previous.lb. to i32 + %conv1 = trunc i64 %.previous.ub. to i32 + store i32 %conv, ptr addrspace(5) %.omp.lb, align 4, !tbaa !12 + store i32 %conv1, ptr addrspace(5) %.omp.ub, align 4, !tbaa !12 + call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) %.omp.stride) #2 + store i32 1, ptr addrspace(5) %.omp.stride, align 4, !tbaa !12 + call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) %.omp.is_last) #2 + store i32 0, ptr addrspace(5) %.omp.is_last, align 4, !tbaa !12 + call void @llvm.lifetime.start.p5(i64 16, ptr addrspace(5) %dinp2) #2 + %_M_value.imagp.i = getelementptr inbounds i8, ptr addrspace(5) %dinp2, i32 8 + %0 = load i32, ptr %.global_tid., align 4, !tbaa !12 + call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @3 to ptr), i32 %0, i32 33, ptr nonnull %.omp.is_last.ascast, ptr nonnull %.omp.lb.ascast, ptr nonnull %.omp.ub.ascast, ptr nonnull %.omp.stride.ascast, i32 1, i32 1) #2 + %1 = load i32, ptr addrspace(5) %.omp.lb, align 4, !tbaa !12 + %conv320 = sext i32 %1 to i64 + %cmp.not21 = icmp ugt i64 %conv320, %.previous.ub. + br i1 %cmp.not21, label %omp.loop.exit, label %omp.inner.for.body.lr.ph + +omp.inner.for.body.lr.ph: ; preds = %entry + %2 = load i32, ptr addrspace(5) %.omp.stride, align 4, !tbaa !12 + br label %omp.inner.for.body + +omp.inner.for.body: ; preds = %omp.inner.for.body.lr.ph, %omp.inner.for.body + %conv325 = phi i64 [ %conv320, %omp.inner.for.body.lr.ph ], [ %conv3, %omp.inner.for.body ] + %_M_value.real.i1823 = phi double [ 0.000000e+00, %omp.inner.for.body.lr.ph ], [ %add.r.i, %omp.inner.for.body ] + %add.i.i1922 = phi double [ 0.000000e+00, %omp.inner.for.body.lr.ph ], [ %add.i.i, %omp.inner.for.body ] + %indvars = trunc i64 %conv325 to i32 + %arrayidx = getelementptr inbounds [100 x %"struct.std::complex"], ptr %dres, i64 0, i64 %conv325 + %_M_value.real.i.i = load double, ptr %arrayidx, align 8 + %_M_value.imagp.i.i = getelementptr inbounds i8, ptr %arrayidx, i64 8 + %_M_value.imag.i.i = load double, ptr %_M_value.imagp.i.i, align 8 + %add.r.i = fadd double %_M_value.real.i1823, %_M_value.real.i.i + %add.i.i = fadd double %add.i.i1922, %_M_value.imag.i.i + %add4 = add nsw i32 %2, %indvars + %conv3 = sext i32 %add4 to i64 + %cmp.not = icmp ugt i64 %conv3, %.previous.ub. + br i1 %cmp.not, label %omp.loop.exit, label %omp.inner.for.body + +omp.loop.exit: ; preds = %omp.inner.for.body, %entry + %add.i.i19.lcssa = phi double [ 0.000000e+00, %entry ], [ %add.i.i, %omp.inner.for.body ] + %_M_value.real.i18.lcssa = phi double [ 0.000000e+00, %entry ], [ %add.r.i, %omp.inner.for.body ] + store double %_M_value.real.i18.lcssa, ptr addrspace(5) %dinp2, align 8 + store double %add.i.i19.lcssa, ptr addrspace(5) %_M_value.imagp.i, align 8 + call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @3 to ptr), i32 %0) #2 + store ptr %dinp2.ascast, ptr addrspace(5) %.omp.reduction.red_list, align 8 + %3 = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @1 to ptr), i64 16, ptr nonnull %.omp.reduction.red_list.ascast, ptr nonnull @_omp_reduction_shuffle_and_reduce_func, ptr nonnull @_omp_reduction_inter_warp_copy_func) #2 + %4 = icmp eq i32 %3, 1 + br i1 %4, label %.omp.reduction.then, label %.omp.reduction.done + +.omp.reduction.then: ; preds = %omp.loop.exit + %_M_value.real.i.i10 = load double, ptr addrspace(5) %dinp2, align 8 + %_M_value.imag.i.i12 = load double, ptr addrspace(5) %_M_value.imagp.i, align 8 + %_M_value.real.i13 = load double, ptr %dinp, align 8 + %_M_value.imagp.i14 = getelementptr inbounds i8, ptr %dinp, i64 8 + %_M_value.imag.i15 = load double, ptr %_M_value.imagp.i14, align 8 + %add.r.i16 = fadd double %_M_value.real.i.i10, %_M_value.real.i13 + %add.i.i17 = fadd double %_M_value.imag.i.i12, %_M_value.imag.i15 + store double %add.r.i16, ptr %dinp, align 8 + store double %add.i.i17, ptr %_M_value.imagp.i14, align 8 + br label %.omp.reduction.done + +.omp.reduction.done: ; preds = %.omp.reduction.then, %omp.loop.exit + call void @llvm.lifetime.end.p5(i64 16, ptr addrspace(5) %dinp2) #2 + call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) %.omp.is_last) #2 + call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) %.omp.stride) #2 + call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) %.omp.ub) #2 + call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) %.omp.lb) #2 + ret void +} + +; Function Attrs: nounwind +declare void @__kmpc_for_static_init_4(ptr, i32, i32, ptr, ptr, ptr, ptr, i32, i32) local_unnamed_addr #2 + +; Function Attrs: nounwind +declare void @__kmpc_for_static_fini(ptr, i32) local_unnamed_addr #2 + +; Function Attrs: norecurse nounwind +define internal void @_omp_reduction_shuffle_and_reduce_func(ptr nocapture noundef readonly %0, i16 noundef signext %1, i16 noundef signext %2, i16 noundef signext %3) #4 { +entry: + %4 = load ptr, ptr %0, align 8 + %5 = load i64, ptr %4, align 8 + %6 = tail call i32 @__kmpc_get_warp_size() #2 + %7 = trunc i32 %6 to i16 + %8 = tail call i64 @__kmpc_shuffle_int64(i64 %5, i16 %2, i16 %7) #2 + %9 = getelementptr i8, ptr %4, i64 8 + %10 = load i64, ptr %9, align 8 + %11 = tail call i32 @__kmpc_get_warp_size() #2 + %12 = trunc i32 %11 to i16 + %13 = tail call i64 @__kmpc_shuffle_int64(i64 %10, i16 %2, i16 %12) #2 + %14 = icmp eq i16 %3, 0 + %15 = icmp eq i16 %3, 1 + %16 = icmp ult i16 %1, %2 + %17 = and i1 %16, %15 + %18 = icmp eq i16 %3, 2 + %19 = and i16 %1, 1 + %20 = icmp eq i16 %19, 0 + %21 = and i1 %20, %18 + %22 = icmp sgt i16 %2, 0 + %23 = and i1 %22, %21 + %24 = or i1 %14, %17 + %25 = or i1 %24, %23 + br i1 %25, label %then, label %ifcont + +then: ; preds = %entry + %26 = bitcast i64 %13 to double + %27 = bitcast i64 %8 to double + %28 = load ptr, ptr %0, align 8 + %_M_value.real.i.i = load double, ptr %28, align 8 + %_M_value.imagp.i.i = getelementptr inbounds i8, ptr %28, i64 8 + %_M_value.imag.i.i = load double, ptr %_M_value.imagp.i.i, align 8 + %add.r.i.i = fadd double %_M_value.real.i.i, %27 + %add.i.i.i = fadd double %_M_value.imag.i.i, %26 + store double %add.r.i.i, ptr %28, align 8 + store double %add.i.i.i, ptr %_M_value.imagp.i.i, align 8 + br label %ifcont + +ifcont: ; preds = %entry, %then + %29 = icmp uge i16 %1, %2 + %30 = and i1 %29, %15 + br i1 %30, label %then4, label %ifcont6 + +then4: ; preds = %ifcont + %31 = load ptr, ptr %0, align 8 + store i64 %8, ptr %31, align 8, !tbaa.struct !18 + %.omp.reduction.element.sroa.3.0..sroa_idx = getelementptr inbounds i8, ptr %31, i64 8 + store i64 %13, ptr %.omp.reduction.element.sroa.3.0..sroa_idx, align 8, !tbaa !19 + br label %ifcont6 + +ifcont6: ; preds = %ifcont, %then4 + ret void +} + +; Function Attrs: nounwind +declare i32 @__kmpc_get_warp_size() local_unnamed_addr #2 + +declare i64 @__kmpc_shuffle_int64(i64, i16, i16) local_unnamed_addr + +; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite) +declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #5 + +; Function Attrs: convergent norecurse nounwind +define internal void @_omp_reduction_inter_warp_copy_func(ptr nocapture noundef readonly %0, i32 noundef %1) #6 { +entry: + %2 = tail call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @1 to ptr)) #2 + %3 = tail call i32 @__kmpc_get_hardware_thread_id_in_block() #2 + %4 = tail call i32 @__kmpc_get_hardware_thread_id_in_block() #2 + %nvptx_lane_id = and i32 %4, 63 + %5 = tail call i32 @__kmpc_get_hardware_thread_id_in_block() #2 + %nvptx_warp_id = ashr i32 %5, 6 + %warp_master = icmp eq i32 %nvptx_lane_id, 0 + %6 = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i32 0, i32 %nvptx_warp_id + %is_active_thread = icmp ult i32 %3, %1 + %7 = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i32 0, i32 %3 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %warp_master, label %then, label %ifcont + +then: ; preds = %entry + %8 = load ptr, ptr %0, align 8, !tbaa !16 + %9 = load i32, ptr %8, align 4 + store volatile i32 %9, ptr addrspace(3) %6, align 4 + br label %ifcont + +ifcont: ; preds = %entry, %then + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %is_active_thread, label %then2, label %ifcont4 + +then2: ; preds = %ifcont + %10 = load ptr, ptr %0, align 8, !tbaa !16 + %11 = load volatile i32, ptr addrspace(3) %7, align 4, !tbaa !12 + store i32 %11, ptr %10, align 4, !tbaa !12 + br label %ifcont4 + +ifcont4: ; preds = %ifcont, %then2 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %warp_master, label %then.1, label %ifcont.1 + +then.1: ; preds = %ifcont4 + %12 = load ptr, ptr %0, align 8, !tbaa !16 + %13 = getelementptr i8, ptr %12, i64 4 + %14 = load i32, ptr %13, align 4 + store volatile i32 %14, ptr addrspace(3) %6, align 4 + br label %ifcont.1 + +ifcont.1: ; preds = %then.1, %ifcont4 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %is_active_thread, label %then2.1, label %ifcont4.1 + +then2.1: ; preds = %ifcont.1 + %15 = load ptr, ptr %0, align 8, !tbaa !16 + %16 = getelementptr i8, ptr %15, i64 4 + %17 = load volatile i32, ptr addrspace(3) %7, align 4, !tbaa !12 + store i32 %17, ptr %16, align 4, !tbaa !12 + br label %ifcont4.1 + +ifcont4.1: ; preds = %then2.1, %ifcont.1 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %warp_master, label %then.2, label %ifcont.2 + +then.2: ; preds = %ifcont4.1 + %18 = load ptr, ptr %0, align 8, !tbaa !16 + %19 = getelementptr i8, ptr %18, i64 8 + %20 = load i32, ptr %19, align 4 + store volatile i32 %20, ptr addrspace(3) %6, align 4 + br label %ifcont.2 + +ifcont.2: ; preds = %then.2, %ifcont4.1 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %is_active_thread, label %then2.2, label %ifcont4.2 + +then2.2: ; preds = %ifcont.2 + %21 = load ptr, ptr %0, align 8, !tbaa !16 + %22 = getelementptr i8, ptr %21, i64 8 + %23 = load volatile i32, ptr addrspace(3) %7, align 4, !tbaa !12 + store i32 %23, ptr %22, align 4, !tbaa !12 + br label %ifcont4.2 + +ifcont4.2: ; preds = %then2.2, %ifcont.2 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %warp_master, label %then.3, label %ifcont.3 + +then.3: ; preds = %ifcont4.2 + %24 = load ptr, ptr %0, align 8, !tbaa !16 + %25 = getelementptr i8, ptr %24, i64 12 + %26 = load i32, ptr %25, align 4 + store volatile i32 %26, ptr addrspace(3) %6, align 4 + br label %ifcont.3 + +ifcont.3: ; preds = %then.3, %ifcont4.2 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %is_active_thread, label %then2.3, label %ifcont4.3 + +then2.3: ; preds = %ifcont.3 + %27 = load ptr, ptr %0, align 8, !tbaa !16 + %28 = getelementptr i8, ptr %27, i64 12 + %29 = load volatile i32, ptr addrspace(3) %7, align 4, !tbaa !12 + store i32 %29, ptr %28, align 4, !tbaa !12 + br label %ifcont4.3 + +ifcont4.3: ; preds = %then2.3, %ifcont.3 + ret void +} + +; Function Attrs: nounwind +declare i32 @__kmpc_get_hardware_thread_id_in_block() local_unnamed_addr #2 + +; Function Attrs: nounwind +declare i32 @__kmpc_global_thread_num(ptr) local_unnamed_addr #2 + +; Function Attrs: convergent nounwind +declare void @__kmpc_barrier(ptr, i32) local_unnamed_addr #7 + +declare i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr, i64, ptr, ptr, ptr) local_unnamed_addr + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p5(i64 immarg, ptr addrspace(5) nocapture) #1 + +; Function Attrs: alwaysinline +declare void @__kmpc_parallel_51(ptr, i32, i32, i32, i32, ptr, ptr, ptr, i64) local_unnamed_addr #8 + +; Function Attrs: nounwind +declare void @__kmpc_distribute_static_fini(ptr, i32) local_unnamed_addr #2 + +; Function Attrs: norecurse nounwind +define internal void @_omp_reduction_shuffle_and_reduce_func.1(ptr nocapture noundef readonly %0, i16 noundef signext %1, i16 noundef signext %2, i16 noundef signext %3) #4 { +entry: + %4 = load ptr, ptr %0, align 8 + %5 = load i64, ptr %4, align 8 + %6 = tail call i32 @__kmpc_get_warp_size() #2 + %7 = trunc i32 %6 to i16 + %8 = tail call i64 @__kmpc_shuffle_int64(i64 %5, i16 %2, i16 %7) #2 + %9 = getelementptr i8, ptr %4, i64 8 + %10 = load i64, ptr %9, align 8 + %11 = tail call i32 @__kmpc_get_warp_size() #2 + %12 = trunc i32 %11 to i16 + %13 = tail call i64 @__kmpc_shuffle_int64(i64 %10, i16 %2, i16 %12) #2 + %14 = icmp eq i16 %3, 0 + %15 = icmp eq i16 %3, 1 + %16 = icmp ult i16 %1, %2 + %17 = and i1 %16, %15 + %18 = icmp eq i16 %3, 2 + %19 = and i16 %1, 1 + %20 = icmp eq i16 %19, 0 + %21 = and i1 %20, %18 + %22 = icmp sgt i16 %2, 0 + %23 = and i1 %22, %21 + %24 = or i1 %14, %17 + %25 = or i1 %24, %23 + br i1 %25, label %then, label %ifcont + +then: ; preds = %entry + %26 = bitcast i64 %13 to double + %27 = bitcast i64 %8 to double + %28 = load ptr, ptr %0, align 8 + %_M_value.real.i.i = load double, ptr %28, align 8 + %_M_value.imagp.i.i = getelementptr inbounds i8, ptr %28, i64 8 + %_M_value.imag.i.i = load double, ptr %_M_value.imagp.i.i, align 8 + %add.r.i.i = fadd double %_M_value.real.i.i, %27 + %add.i.i.i = fadd double %_M_value.imag.i.i, %26 + store double %add.r.i.i, ptr %28, align 8 + store double %add.i.i.i, ptr %_M_value.imagp.i.i, align 8 + br label %ifcont + +ifcont: ; preds = %entry, %then + %29 = icmp uge i16 %1, %2 + %30 = and i1 %29, %15 + br i1 %30, label %then4, label %ifcont6 + +then4: ; preds = %ifcont + %31 = load ptr, ptr %0, align 8 + store i64 %8, ptr %31, align 8, !tbaa.struct !18 + %.omp.reduction.element.sroa.3.0..sroa_idx = getelementptr inbounds i8, ptr %31, i64 8 + store i64 %13, ptr %.omp.reduction.element.sroa.3.0..sroa_idx, align 8, !tbaa !19 + br label %ifcont6 + +ifcont6: ; preds = %ifcont, %then4 + ret void +} + +; Function Attrs: convergent norecurse nounwind +define internal void @_omp_reduction_inter_warp_copy_func.2(ptr nocapture noundef readonly %0, i32 noundef %1) #6 { +entry: + %2 = tail call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @1 to ptr)) #2 + %3 = tail call i32 @__kmpc_get_hardware_thread_id_in_block() #2 + %4 = tail call i32 @__kmpc_get_hardware_thread_id_in_block() #2 + %nvptx_lane_id = and i32 %4, 63 + %5 = tail call i32 @__kmpc_get_hardware_thread_id_in_block() #2 + %nvptx_warp_id = ashr i32 %5, 6 + %warp_master = icmp eq i32 %nvptx_lane_id, 0 + %6 = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i32 0, i32 %nvptx_warp_id + %is_active_thread = icmp ult i32 %3, %1 + %7 = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i32 0, i32 %3 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %warp_master, label %then, label %ifcont + +then: ; preds = %entry + %8 = load ptr, ptr %0, align 8, !tbaa !16 + %9 = load i32, ptr %8, align 4 + store volatile i32 %9, ptr addrspace(3) %6, align 4 + br label %ifcont + +ifcont: ; preds = %entry, %then + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %is_active_thread, label %then2, label %ifcont4 + +then2: ; preds = %ifcont + %10 = load ptr, ptr %0, align 8, !tbaa !16 + %11 = load volatile i32, ptr addrspace(3) %7, align 4, !tbaa !12 + store i32 %11, ptr %10, align 4, !tbaa !12 + br label %ifcont4 + +ifcont4: ; preds = %ifcont, %then2 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %warp_master, label %then.1, label %ifcont.1 + +then.1: ; preds = %ifcont4 + %12 = load ptr, ptr %0, align 8, !tbaa !16 + %13 = getelementptr i8, ptr %12, i64 4 + %14 = load i32, ptr %13, align 4 + store volatile i32 %14, ptr addrspace(3) %6, align 4 + br label %ifcont.1 + +ifcont.1: ; preds = %then.1, %ifcont4 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %is_active_thread, label %then2.1, label %ifcont4.1 + +then2.1: ; preds = %ifcont.1 + %15 = load ptr, ptr %0, align 8, !tbaa !16 + %16 = getelementptr i8, ptr %15, i64 4 + %17 = load volatile i32, ptr addrspace(3) %7, align 4, !tbaa !12 + store i32 %17, ptr %16, align 4, !tbaa !12 + br label %ifcont4.1 + +ifcont4.1: ; preds = %then2.1, %ifcont.1 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %warp_master, label %then.2, label %ifcont.2 + +then.2: ; preds = %ifcont4.1 + %18 = load ptr, ptr %0, align 8, !tbaa !16 + %19 = getelementptr i8, ptr %18, i64 8 + %20 = load i32, ptr %19, align 4 + store volatile i32 %20, ptr addrspace(3) %6, align 4 + br label %ifcont.2 + +ifcont.2: ; preds = %then.2, %ifcont4.1 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %is_active_thread, label %then2.2, label %ifcont4.2 + +then2.2: ; preds = %ifcont.2 + %21 = load ptr, ptr %0, align 8, !tbaa !16 + %22 = getelementptr i8, ptr %21, i64 8 + %23 = load volatile i32, ptr addrspace(3) %7, align 4, !tbaa !12 + store i32 %23, ptr %22, align 4, !tbaa !12 + br label %ifcont4.2 + +ifcont4.2: ; preds = %then2.2, %ifcont.2 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %warp_master, label %then.3, label %ifcont.3 + +then.3: ; preds = %ifcont4.2 + %24 = load ptr, ptr %0, align 8, !tbaa !16 + %25 = getelementptr i8, ptr %24, i64 12 + %26 = load i32, ptr %25, align 4 + store volatile i32 %26, ptr addrspace(3) %6, align 4 + br label %ifcont.3 + +ifcont.3: ; preds = %then.3, %ifcont4.2 + tail call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @4 to ptr), i32 %2) #2 + br i1 %is_active_thread, label %then2.3, label %ifcont4.3 + +then2.3: ; preds = %ifcont.3 + %27 = load ptr, ptr %0, align 8, !tbaa !16 + %28 = getelementptr i8, ptr %27, i64 12 + %29 = load volatile i32, ptr addrspace(3) %7, align 4, !tbaa !12 + store i32 %29, ptr %28, align 4, !tbaa !12 + br label %ifcont4.3 + +ifcont4.3: ; preds = %then2.3, %ifcont.3 + ret void +} + +; Function Attrs: nounwind +declare ptr @__kmpc_reduction_get_fixed_buffer() local_unnamed_addr #2 + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) +define internal void @_omp_reduction_list_to_global_copy_func(ptr nocapture noundef writeonly %0, i32 noundef %1, ptr nocapture noundef readonly %2) #9 { +entry: + %3 = load ptr, ptr %2, align 8, !tbaa !16 + %4 = sext i32 %1 to i64 + %5 = getelementptr inbounds %struct._globalized_locals_ty, ptr %0, i64 %4 + tail call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %5, ptr noundef nonnull align 8 dereferenceable(16) %3, i64 16, i1 false), !tbaa.struct !18 + ret void +} + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(read, argmem: readwrite, inaccessiblemem: none) +define internal void @_omp_reduction_list_to_global_reduce_func(ptr nocapture noundef %0, i32 noundef %1, ptr nocapture noundef readonly %2) #10 { +entry: + %3 = sext i32 %1 to i64 + %4 = getelementptr inbounds %struct._globalized_locals_ty, ptr %0, i64 %3 + %5 = load ptr, ptr %2, align 8 + %_M_value.real.i.i.i = load double, ptr %5, align 8 + %_M_value.imagp.i.i.i = getelementptr inbounds i8, ptr %5, i64 8 + %_M_value.imag.i.i.i = load double, ptr %_M_value.imagp.i.i.i, align 8 + %_M_value.real.i.i = load double, ptr %4, align 8 + %_M_value.imagp.i.i = getelementptr inbounds i8, ptr %4, i64 8 + %_M_value.imag.i.i = load double, ptr %_M_value.imagp.i.i, align 8 + %add.r.i.i = fadd double %_M_value.real.i.i.i, %_M_value.real.i.i + %add.i.i.i = fadd double %_M_value.imag.i.i.i, %_M_value.imag.i.i + store double %add.r.i.i, ptr %4, align 8 + store double %add.i.i.i, ptr %_M_value.imagp.i.i, align 8 + ret void +} + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) +define internal void @_omp_reduction_global_to_list_copy_func(ptr nocapture noundef readonly %0, i32 noundef %1, ptr nocapture noundef readonly %2) #9 { +entry: + %3 = load ptr, ptr %2, align 8, !tbaa !16 + %4 = sext i32 %1 to i64 + %5 = getelementptr inbounds %struct._globalized_locals_ty, ptr %0, i64 %4 + tail call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %3, ptr noundef nonnull align 8 dereferenceable(16) %5, i64 16, i1 false), !tbaa.struct !18 + ret void +} + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) +define internal void @_omp_reduction_global_to_list_reduce_func(ptr nocapture noundef readonly %0, i32 noundef %1, ptr nocapture noundef readonly %2) #9 { +entry: + %3 = sext i32 %1 to i64 + %4 = getelementptr inbounds %struct._globalized_locals_ty, ptr %0, i64 %3 + %5 = load ptr, ptr %2, align 8 + %_M_value.real.i.i.i = load double, ptr %4, align 8 + %_M_value.imagp.i.i.i = getelementptr inbounds i8, ptr %4, i64 8 + %_M_value.imag.i.i.i = load double, ptr %_M_value.imagp.i.i.i, align 8 + %_M_value.real.i.i = load double, ptr %5, align 8 + %_M_value.imagp.i.i = getelementptr inbounds i8, ptr %5, i64 8 + %_M_value.imag.i.i = load double, ptr %_M_value.imagp.i.i, align 8 + %add.r.i.i = fadd double %_M_value.real.i.i.i, %_M_value.real.i.i + %add.i.i.i = fadd double %_M_value.imag.i.i.i, %_M_value.imag.i.i + store double %add.r.i.i, ptr %5, align 8 + store double %add.i.i.i, ptr %_M_value.imagp.i.i, align 8 + ret void +} + +declare i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr, ptr, i32, i64, ptr, ptr, ptr, ptr, ptr, ptr, ptr) local_unnamed_addr + +declare void @__kmpc_target_deinit() local_unnamed_addr + +; Function Attrs: cold mustprogress noinline nounwind optsize +define weak hidden { double, double } @__muldc3(double noundef %__a, double noundef %__b, double noundef %__c, double noundef %__d) local_unnamed_addr #11 { +entry: + %mul = fmul double %__a, %__c + %mul1 = fmul double %__b, %__d + %mul2 = fmul double %__a, %__d + %mul3 = fmul double %__b, %__c + %sub = fsub double %mul, %mul1 + %add = fadd double %mul3, %mul2 + %0 = fcmp ord double %sub, 0.000000e+00 + %1 = fcmp ord double %add, 0.000000e+00 + %or.cond = or i1 %0, %1 + br i1 %or.cond, label %if.end104, label %if.then + +if.then: ; preds = %entry + %2 = tail call double @llvm.fabs.f64(double %__a) + %3 = fcmp oeq double %2, 0x7FF0000000000000 + %4 = tail call double @llvm.fabs.f64(double %__b) + %5 = fcmp oeq double %4, 0x7FF0000000000000 + %or.cond158.not = or i1 %3, %5 + br i1 %or.cond158.not, label %if.then12, label %if.end30 + +if.then12: ; preds = %if.then + %conv = uitofp i1 %3 to double + %6 = tail call noundef double @llvm.copysign.f64(double %conv, double %__a) + %conv19 = uitofp i1 %5 to double + %7 = tail call noundef double @llvm.copysign.f64(double %conv19, double %__b) + %8 = fcmp ord double %__c, 0.000000e+00 + %9 = tail call noundef double @llvm.copysign.f64(double 0.000000e+00, double %__c) + %spec.select = select i1 %8, double %__c, double %9 + %10 = fcmp ord double %__d, 0.000000e+00 + %11 = tail call noundef double @llvm.copysign.f64(double 0.000000e+00, double %__d) + %spec.select154 = select i1 %10, double %__d, double %11 + br label %if.end30 + +if.end30: ; preds = %if.then, %if.then12 + %__d.addr.1 = phi double [ %spec.select154, %if.then12 ], [ %__d, %if.then ] + %__c.addr.1 = phi double [ %spec.select, %if.then12 ], [ %__c, %if.then ] + %__b.addr.0 = phi double [ %7, %if.then12 ], [ %__b, %if.then ] + %__a.addr.0 = phi double [ %6, %if.then12 ], [ %__a, %if.then ] + %__recalc.0 = phi i32 [ 1, %if.then12 ], [ 0, %if.then ] + %12 = tail call double @llvm.fabs.f64(double %__c.addr.1) + %13 = fcmp oeq double %12, 0x7FF0000000000000 + %14 = tail call double @llvm.fabs.f64(double %__d.addr.1) + %15 = fcmp oeq double %14, 0x7FF0000000000000 + %or.cond161.not = or i1 %15, %13 + br i1 %or.cond161.not, label %if.then36, label %if.end57 + +if.then36: ; preds = %if.end30 + %conv40 = uitofp i1 %13 to double + %16 = tail call noundef double @llvm.copysign.f64(double %conv40, double %__c.addr.1) + %conv45 = uitofp i1 %15 to double + %17 = tail call noundef double @llvm.copysign.f64(double %conv45, double %__d.addr.1) + %18 = fcmp ord double %__a.addr.0, 0.000000e+00 + %19 = tail call noundef double @llvm.copysign.f64(double 0.000000e+00, double %__a.addr.0) + %spec.select152 = select i1 %18, double %__a.addr.0, double %19 + %20 = fcmp ord double %__b.addr.0, 0.000000e+00 + %21 = tail call noundef double @llvm.copysign.f64(double 0.000000e+00, double %__b.addr.0) + %spec.select155 = select i1 %20, double %__b.addr.0, double %21 + br label %if.end57 + +if.end57: ; preds = %if.end30, %if.then36 + %__d.addr.2 = phi double [ %17, %if.then36 ], [ %__d.addr.1, %if.end30 ] + %__c.addr.2 = phi double [ %16, %if.then36 ], [ %__c.addr.1, %if.end30 ] + %__b.addr.2 = phi double [ %spec.select155, %if.then36 ], [ %__b.addr.0, %if.end30 ] + %__a.addr.2 = phi double [ %spec.select152, %if.then36 ], [ %__a.addr.0, %if.end30 ] + %__recalc.1 = phi i32 [ 1, %if.then36 ], [ %__recalc.0, %if.end30 ] + %tobool58.not = icmp eq i32 %__recalc.1, 0 + br i1 %tobool58.not, label %land.lhs.true59, label %if.end92 + +land.lhs.true59: ; preds = %if.end57 + %22 = tail call double @llvm.fabs.f64(double %mul) + %23 = fcmp une double %22, 0x7FF0000000000000 + %24 = tail call double @llvm.fabs.f64(double %mul1) + %25 = fcmp une double %24, 0x7FF0000000000000 + %or.cond163 = and i1 %23, %25 + %26 = tail call double @llvm.fabs.f64(double %mul2) + %27 = fcmp une double %26, 0x7FF0000000000000 + %or.cond165 = and i1 %27, %or.cond163 + %28 = tail call double @llvm.fabs.f64(double %mul3) + %29 = fcmp une double %28, 0x7FF0000000000000 + %or.cond167 = and i1 %29, %or.cond165 + br i1 %or.cond167, label %if.end92, label %if.then71 + +if.then71: ; preds = %land.lhs.true59 + %30 = fcmp ord double %__a.addr.2, 0.000000e+00 + %31 = tail call noundef double @llvm.copysign.f64(double 0.000000e+00, double %__a.addr.2) + %spec.select153 = select i1 %30, double %__a.addr.2, double %31 + %32 = fcmp ord double %__b.addr.2, 0.000000e+00 + %33 = tail call noundef double @llvm.copysign.f64(double 0.000000e+00, double %__b.addr.2) + %__b.addr.3 = select i1 %32, double %__b.addr.2, double %33 + %34 = fcmp ord double %__c.addr.2, 0.000000e+00 + %35 = tail call noundef double @llvm.copysign.f64(double 0.000000e+00, double %__c.addr.2) + %__c.addr.3 = select i1 %34, double %__c.addr.2, double %35 + %36 = fcmp ord double %__d.addr.2, 0.000000e+00 + %37 = tail call noundef double @llvm.copysign.f64(double 0.000000e+00, double %__d.addr.2) + %spec.select156 = select i1 %36, double %__d.addr.2, double %37 + br label %if.end92 + +if.end92: ; preds = %land.lhs.true59, %if.then71, %if.end57 + %__d.addr.4 = phi double [ %__d.addr.2, %if.end57 ], [ %spec.select156, %if.then71 ], [ %__d.addr.2, %land.lhs.true59 ] + %__c.addr.4 = phi double [ %__c.addr.2, %if.end57 ], [ %__c.addr.3, %if.then71 ], [ %__c.addr.2, %land.lhs.true59 ] + %__b.addr.4 = phi double [ %__b.addr.2, %if.end57 ], [ %__b.addr.3, %if.then71 ], [ %__b.addr.2, %land.lhs.true59 ] + %__a.addr.4 = phi double [ %__a.addr.2, %if.end57 ], [ %spec.select153, %if.then71 ], [ %__a.addr.2, %land.lhs.true59 ] + %tobool93.not = phi i1 [ false, %if.end57 ], [ false, %if.then71 ], [ true, %land.lhs.true59 ] + br i1 %tobool93.not, label %if.end104, label %if.then94 + +if.then94: ; preds = %if.end92 + %38 = fneg double %__b.addr.4 + %neg = fmul double %__d.addr.4, %38 + %39 = tail call double @llvm.fmuladd.f64(double %__a.addr.4, double %__c.addr.4, double %neg) + %mul97 = fmul double %39, 0x7FF0000000000000 + %mul100 = fmul double %__c.addr.4, %__b.addr.4 + %40 = tail call double @llvm.fmuladd.f64(double %__a.addr.4, double %__d.addr.4, double %mul100) + %mul101 = fmul double %40, 0x7FF0000000000000 + br label %if.end104 + +if.end104: ; preds = %if.end92, %if.then94, %entry + %z.sroa.6.1 = phi double [ %add, %entry ], [ %mul101, %if.then94 ], [ %add, %if.end92 ] + %z.sroa.0.1 = phi double [ %sub, %entry ], [ %mul97, %if.then94 ], [ %sub, %if.end92 ] + %.fca.0.insert = insertvalue { double, double } poison, double %z.sroa.0.1, 0 + %.fca.1.insert = insertvalue { double, double } %.fca.0.insert, double %z.sroa.6.1, 1 + ret { double, double } %.fca.1.insert +} + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare double @llvm.fmuladd.f64(double, double, double) #12 + +; Function Attrs: cold mustprogress noinline nounwind optsize +define weak hidden [2 x i32] @__mulsc3(float noundef %__a, float noundef %__b, float noundef %__c, float noundef %__d) local_unnamed_addr #11 { +entry: + %mul = fmul float %__a, %__c + %mul1 = fmul float %__b, %__d + %mul2 = fmul float %__a, %__d + %mul3 = fmul float %__b, %__c + %sub = fsub float %mul, %mul1 + %add = fadd float %mul3, %mul2 + %0 = fcmp ord float %sub, 0.000000e+00 + %1 = fcmp ord float %add, 0.000000e+00 + %or.cond = or i1 %0, %1 + br i1 %or.cond, label %if.end104, label %if.then + +if.then: ; preds = %entry + %2 = tail call float @llvm.fabs.f32(float %__a) + %3 = fcmp oeq float %2, 0x7FF0000000000000 + %4 = tail call float @llvm.fabs.f32(float %__b) + %5 = fcmp oeq float %4, 0x7FF0000000000000 + %or.cond160.not = or i1 %3, %5 + br i1 %or.cond160.not, label %if.then12, label %if.end30 + +if.then12: ; preds = %if.then + %conv = uitofp i1 %3 to float + %6 = tail call noundef float @llvm.copysign.f32(float %conv, float %__a) + %conv19 = uitofp i1 %5 to float + %7 = tail call noundef float @llvm.copysign.f32(float %conv19, float %__b) + %8 = fcmp ord float %__c, 0.000000e+00 + %9 = tail call noundef float @llvm.copysign.f32(float 0.000000e+00, float %__c) + %spec.select = select i1 %8, float %__c, float %9 + %10 = fcmp ord float %__d, 0.000000e+00 + %11 = tail call noundef float @llvm.copysign.f32(float 0.000000e+00, float %__d) + %spec.select156 = select i1 %10, float %__d, float %11 + br label %if.end30 + +if.end30: ; preds = %if.then, %if.then12 + %__d.addr.1 = phi float [ %spec.select156, %if.then12 ], [ %__d, %if.then ] + %__c.addr.1 = phi float [ %spec.select, %if.then12 ], [ %__c, %if.then ] + %__b.addr.0 = phi float [ %7, %if.then12 ], [ %__b, %if.then ] + %__a.addr.0 = phi float [ %6, %if.then12 ], [ %__a, %if.then ] + %__recalc.0 = phi i32 [ 1, %if.then12 ], [ 0, %if.then ] + %12 = tail call float @llvm.fabs.f32(float %__c.addr.1) + %13 = fcmp oeq float %12, 0x7FF0000000000000 + %14 = tail call float @llvm.fabs.f32(float %__d.addr.1) + %15 = fcmp oeq float %14, 0x7FF0000000000000 + %or.cond163.not = or i1 %15, %13 + br i1 %or.cond163.not, label %if.then36, label %if.end57 + +if.then36: ; preds = %if.end30 + %conv40 = uitofp i1 %13 to float + %16 = tail call noundef float @llvm.copysign.f32(float %conv40, float %__c.addr.1) + %conv45 = uitofp i1 %15 to float + %17 = tail call noundef float @llvm.copysign.f32(float %conv45, float %__d.addr.1) + %18 = fcmp ord float %__a.addr.0, 0.000000e+00 + %19 = tail call noundef float @llvm.copysign.f32(float 0.000000e+00, float %__a.addr.0) + %spec.select152 = select i1 %18, float %__a.addr.0, float %19 + %20 = fcmp ord float %__b.addr.0, 0.000000e+00 + %21 = tail call noundef float @llvm.copysign.f32(float 0.000000e+00, float %__b.addr.0) + %spec.select157 = select i1 %20, float %__b.addr.0, float %21 + br label %if.end57 + +if.end57: ; preds = %if.end30, %if.then36 + %__d.addr.2 = phi float [ %17, %if.then36 ], [ %__d.addr.1, %if.end30 ] + %__c.addr.2 = phi float [ %16, %if.then36 ], [ %__c.addr.1, %if.end30 ] + %__b.addr.2 = phi float [ %spec.select157, %if.then36 ], [ %__b.addr.0, %if.end30 ] + %__a.addr.2 = phi float [ %spec.select152, %if.then36 ], [ %__a.addr.0, %if.end30 ] + %__recalc.1 = phi i32 [ 1, %if.then36 ], [ %__recalc.0, %if.end30 ] + %tobool58.not = icmp eq i32 %__recalc.1, 0 + br i1 %tobool58.not, label %land.lhs.true59, label %if.end92 + +land.lhs.true59: ; preds = %if.end57 + %22 = tail call float @llvm.fabs.f32(float %mul) + %23 = fcmp une float %22, 0x7FF0000000000000 + %24 = tail call float @llvm.fabs.f32(float %mul1) + %25 = fcmp une float %24, 0x7FF0000000000000 + %or.cond165 = and i1 %23, %25 + %26 = tail call float @llvm.fabs.f32(float %mul2) + %27 = fcmp une float %26, 0x7FF0000000000000 + %or.cond167 = and i1 %27, %or.cond165 + %28 = tail call float @llvm.fabs.f32(float %mul3) + %29 = fcmp une float %28, 0x7FF0000000000000 + %or.cond169 = and i1 %29, %or.cond167 + br i1 %or.cond169, label %if.end92, label %if.then71 + +if.then71: ; preds = %land.lhs.true59 + %30 = fcmp ord float %__a.addr.2, 0.000000e+00 + %31 = tail call noundef float @llvm.copysign.f32(float 0.000000e+00, float %__a.addr.2) + %spec.select153 = select i1 %30, float %__a.addr.2, float %31 + %32 = fcmp ord float %__b.addr.2, 0.000000e+00 + %33 = tail call noundef float @llvm.copysign.f32(float 0.000000e+00, float %__b.addr.2) + %__b.addr.3 = select i1 %32, float %__b.addr.2, float %33 + %34 = fcmp ord float %__c.addr.2, 0.000000e+00 + %35 = tail call noundef float @llvm.copysign.f32(float 0.000000e+00, float %__c.addr.2) + %__c.addr.3 = select i1 %34, float %__c.addr.2, float %35 + %36 = fcmp ord float %__d.addr.2, 0.000000e+00 + %37 = tail call noundef float @llvm.copysign.f32(float 0.000000e+00, float %__d.addr.2) + %spec.select158 = select i1 %36, float %__d.addr.2, float %37 + br label %if.end92 + +if.end92: ; preds = %land.lhs.true59, %if.then71, %if.end57 + %__d.addr.4 = phi float [ %__d.addr.2, %if.end57 ], [ %spec.select158, %if.then71 ], [ %__d.addr.2, %land.lhs.true59 ] + %__c.addr.4 = phi float [ %__c.addr.2, %if.end57 ], [ %__c.addr.3, %if.then71 ], [ %__c.addr.2, %land.lhs.true59 ] + %__b.addr.4 = phi float [ %__b.addr.2, %if.end57 ], [ %__b.addr.3, %if.then71 ], [ %__b.addr.2, %land.lhs.true59 ] + %__a.addr.4 = phi float [ %__a.addr.2, %if.end57 ], [ %spec.select153, %if.then71 ], [ %__a.addr.2, %land.lhs.true59 ] + %tobool93.not = phi i1 [ false, %if.end57 ], [ false, %if.then71 ], [ true, %land.lhs.true59 ] + %38 = fneg float %__b.addr.4 + %neg = fmul float %__d.addr.4, %38 + %39 = tail call float @llvm.fmuladd.f32(float %__a.addr.4, float %__c.addr.4, float %neg) + %mul97 = fmul float %39, 0x7FF0000000000000 + %mul100 = fmul float %__c.addr.4, %__b.addr.4 + %40 = tail call float @llvm.fmuladd.f32(float %__a.addr.4, float %__d.addr.4, float %mul100) + %mul101 = fmul float %40, 0x7FF0000000000000 + %spec.select154 = select i1 %tobool93.not, float %add, float %mul101 + %spec.select155 = select i1 %tobool93.not, float %sub, float %mul97 + br label %if.end104 + +if.end104: ; preds = %if.end92, %entry + %z.sroa.6.1 = phi float [ %add, %entry ], [ %spec.select154, %if.end92 ] + %z.sroa.0.1 = phi float [ %sub, %entry ], [ %spec.select155, %if.end92 ] + %41 = bitcast float %z.sroa.0.1 to i32 + %.fca.0.insert = insertvalue [2 x i32] poison, i32 %41, 0 + %42 = bitcast float %z.sroa.6.1 to i32 + %.fca.1.insert = insertvalue [2 x i32] %.fca.0.insert, i32 %42, 1 + ret [2 x i32] %.fca.1.insert +} + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare float @llvm.fmuladd.f32(float, float, float) #12 + +; Function Attrs: cold mustprogress noinline nounwind optsize +define weak hidden { double, double } @__divdc3(double noundef %__a, double noundef %__b, double noundef %__c, double noundef %__d) local_unnamed_addr #11 { +entry: + %0 = tail call noundef double @llvm.fabs.f64(double %__c) + %1 = tail call noundef double @llvm.fabs.f64(double %__d) + %2 = tail call noundef double @llvm.maxnum.f64(double %0, double %1) + %3 = tail call { double, i32 } @llvm.frexp.f64.i32(double %2) + %4 = extractvalue { double, i32 } %3, 1 + %5 = add nsw i32 %4, -1 + %6 = sitofp i32 %5 to double + %7 = fcmp one double %2, 0x7FF0000000000000 + %8 = select i1 %7, double %6, double %2 + %9 = fcmp oeq double %2, 0.000000e+00 + %10 = select i1 %9, double 0xFFF0000000000000, double %8 + %11 = tail call double @llvm.fabs.f64(double %10) + %12 = fcmp ueq double %11, 0x7FF0000000000000 + %conv = fptosi double %10 to i32 + %sub = sub nsw i32 0, %conv + %13 = tail call noundef double @llvm.ldexp.f64.i32(double %__c, i32 %sub) + %14 = tail call noundef double @llvm.ldexp.f64.i32(double %__d, i32 %sub) + %__c.addr.0 = select i1 %12, double %__c, double %13 + %__d.addr.0 = select i1 %12, double %__d, double %14 + %__ilogbw.0 = select i1 %12, i32 0, i32 %conv + %mul8 = fmul double %__d.addr.0, %__d.addr.0 + %15 = tail call double @llvm.fmuladd.f64(double %__c.addr.0, double %__c.addr.0, double %mul8) + %mul9 = fmul double %__d.addr.0, %__b + %16 = tail call double @llvm.fmuladd.f64(double %__a, double %__c.addr.0, double %mul9) + %div = fdiv double %16, %15 + %sub10 = sub nsw i32 0, %__ilogbw.0 + %17 = tail call noundef double @llvm.ldexp.f64.i32(double %div, i32 %sub10) + %18 = fneg double %__d.addr.0 + %neg = fmul double %18, %__a + %19 = tail call double @llvm.fmuladd.f64(double %__b, double %__c.addr.0, double %neg) + %div13 = fdiv double %19, %15 + %20 = tail call noundef double @llvm.ldexp.f64.i32(double %div13, i32 %sub10) + %21 = fcmp ord double %17, 0.000000e+00 + %22 = fcmp ord double %20, 0.000000e+00 + %or.cond153 = or i1 %21, %22 + br i1 %or.cond153, label %if.end94, label %if.then22 + +if.then22: ; preds = %entry + %cmp = fcmp oeq double %15, 0.000000e+00 + br i1 %cmp, label %land.lhs.true23, label %if.else + +land.lhs.true23: ; preds = %if.then22 + %23 = fcmp ord double %__a, 0.000000e+00 + %24 = fcmp ord double %__b, 0.000000e+00 + %or.cond154 = or i1 %23, %24 + br i1 %or.cond154, label %if.then28, label %if.else + +if.then28: ; preds = %land.lhs.true23 + %25 = tail call noundef double @llvm.copysign.f64(double 0x7FF0000000000000, double %__c.addr.0) + %mul = fmul double %25, %__a + %mul32 = fmul double %25, %__b + br label %if.end94 + +if.else: ; preds = %land.lhs.true23, %if.then22 + %26 = tail call double @llvm.fabs.f64(double %__a) + %27 = fcmp une double %26, 0x7FF0000000000000 + %28 = tail call double @llvm.fabs.f64(double %__b) + %29 = fcmp une double %28, 0x7FF0000000000000 + %or.cond156 = and i1 %27, %29 + %30 = tail call double @llvm.fabs.f64(double %__c.addr.0) + %31 = fcmp ueq double %30, 0x7FF0000000000000 + %or.cond158 = select i1 %or.cond156, i1 true, i1 %31 + %32 = tail call double @llvm.fabs.f64(double %__d.addr.0) + %33 = fcmp ueq double %32, 0x7FF0000000000000 + %or.cond160 = select i1 %or.cond158, i1 true, i1 %33 + br i1 %or.cond160, label %if.else62, label %if.then45 + +if.then45: ; preds = %if.else + %cond = select i1 %27, double 0.000000e+00, double 1.000000e+00 + %34 = tail call noundef double @llvm.copysign.f64(double %cond, double %__a) + %cond51 = select i1 %29, double 0.000000e+00, double 1.000000e+00 + %35 = tail call noundef double @llvm.copysign.f64(double %cond51, double %__b) + %mul54 = fmul double %35, %__d.addr.0 + %36 = tail call double @llvm.fmuladd.f64(double %34, double %__c.addr.0, double %mul54) + %mul55 = fmul double %36, 0x7FF0000000000000 + %37 = fneg double %34 + %neg59 = fmul double %__d.addr.0, %37 + %38 = tail call double @llvm.fmuladd.f64(double %35, double %__c.addr.0, double %neg59) + %mul60 = fmul double %38, 0x7FF0000000000000 + br label %if.end94 + +if.else62: ; preds = %if.else + %or.cond = fcmp une double %10, 0x7FF0000000000000 + %39 = fcmp ueq double %26, 0x7FF0000000000000 + %or.cond161 = or i1 %39, %or.cond + %40 = fcmp ueq double %28, 0x7FF0000000000000 + %or.cond163 = or i1 %40, %or.cond161 + br i1 %or.cond163, label %if.end94, label %if.then73 + +if.then73: ; preds = %if.else62 + %41 = fcmp une double %30, 0x7FF0000000000000 + %cond76 = select i1 %41, double 0.000000e+00, double 1.000000e+00 + %42 = tail call noundef double @llvm.copysign.f64(double %cond76, double %__c.addr.0) + %43 = fcmp une double %32, 0x7FF0000000000000 + %cond80 = select i1 %43, double 0.000000e+00, double 1.000000e+00 + %44 = tail call noundef double @llvm.copysign.f64(double %cond80, double %__d.addr.0) + %mul83 = fmul double %44, %__b + %45 = tail call double @llvm.fmuladd.f64(double %__a, double %42, double %mul83) + %mul84 = fmul double %45, 0.000000e+00 + %46 = fneg double %44 + %neg88 = fmul double %46, %__a + %47 = tail call double @llvm.fmuladd.f64(double %__b, double %42, double %neg88) + %mul89 = fmul double %47, 0.000000e+00 + br label %if.end94 + +if.end94: ; preds = %if.then28, %if.else62, %if.then73, %if.then45, %entry + %z.sroa.8.0 = phi double [ %mul60, %if.then45 ], [ %mul89, %if.then73 ], [ %20, %if.else62 ], [ %mul32, %if.then28 ], [ %20, %entry ] + %z.sroa.0.0 = phi double [ %mul55, %if.then45 ], [ %mul84, %if.then73 ], [ %17, %if.else62 ], [ %mul, %if.then28 ], [ %17, %entry ] + %.fca.0.insert = insertvalue { double, double } poison, double %z.sroa.0.0, 0 + %.fca.1.insert = insertvalue { double, double } %.fca.0.insert, double %z.sroa.8.0, 1 + ret { double, double } %.fca.1.insert +} + +; Function Attrs: cold mustprogress noinline nounwind optsize +define weak hidden [2 x i32] @__divsc3(float noundef %__a, float noundef %__b, float noundef %__c, float noundef %__d) local_unnamed_addr #11 { +entry: + %0 = tail call noundef float @llvm.fabs.f32(float %__c) + %1 = tail call noundef float @llvm.fabs.f32(float %__d) + %2 = tail call noundef float @llvm.maxnum.f32(float %0, float %1) + %3 = fpext float %2 to double + %4 = tail call { double, i32 } @llvm.frexp.f64.i32(double %3) + %5 = extractvalue { double, i32 } %4, 1 + %6 = add nsw i32 %5, -1 + %7 = sitofp i32 %6 to float + %8 = fcmp one float %2, 0x7FF0000000000000 + %9 = select i1 %8, float %7, float %2 + %10 = fcmp oeq float %2, 0.000000e+00 + %11 = select i1 %10, float 0xFFF0000000000000, float %9 + %12 = tail call float @llvm.fabs.f32(float %11) + %13 = fcmp ueq float %12, 0x7FF0000000000000 + %conv = fptosi float %11 to i32 + %sub = sub nsw i32 0, %conv + %14 = tail call noundef float @llvm.ldexp.f32.i32(float %__c, i32 %sub) + %15 = tail call noundef float @llvm.ldexp.f32.i32(float %__d, i32 %sub) + %__c.addr.0 = select i1 %13, float %__c, float %14 + %__d.addr.0 = select i1 %13, float %__d, float %15 + %__ilogbw.0 = select i1 %13, i32 0, i32 %conv + %mul8 = fmul float %__d.addr.0, %__d.addr.0 + %16 = tail call float @llvm.fmuladd.f32(float %__c.addr.0, float %__c.addr.0, float %mul8) + %mul9 = fmul float %__d.addr.0, %__b + %17 = tail call float @llvm.fmuladd.f32(float %__a, float %__c.addr.0, float %mul9) + %div = fdiv float %17, %16 + %sub10 = sub nsw i32 0, %__ilogbw.0 + %18 = tail call noundef float @llvm.ldexp.f32.i32(float %div, i32 %sub10) + %19 = fneg float %__d.addr.0 + %neg = fmul float %19, %__a + %20 = tail call float @llvm.fmuladd.f32(float %__b, float %__c.addr.0, float %neg) + %div13 = fdiv float %20, %16 + %21 = tail call noundef float @llvm.ldexp.f32.i32(float %div13, i32 %sub10) + %22 = fcmp ord float %18, 0.000000e+00 + %23 = fcmp ord float %21, 0.000000e+00 + %or.cond157 = or i1 %22, %23 + br i1 %or.cond157, label %if.end98, label %if.then22 + +if.then22: ; preds = %entry + %cmp = fcmp oeq float %16, 0.000000e+00 + br i1 %cmp, label %land.lhs.true23, label %if.else + +land.lhs.true23: ; preds = %if.then22 + %24 = fcmp ord float %__a, 0.000000e+00 + %25 = fcmp ord float %__b, 0.000000e+00 + %or.cond158 = or i1 %24, %25 + br i1 %or.cond158, label %if.then28, label %if.else + +if.then28: ; preds = %land.lhs.true23 + %26 = tail call noundef float @llvm.copysign.f32(float 0x7FF0000000000000, float %__c.addr.0) + %mul = fmul float %26, %__a + %mul32 = fmul float %26, %__b + br label %if.end98 + +if.else: ; preds = %land.lhs.true23, %if.then22 + %27 = tail call float @llvm.fabs.f32(float %__a) + %28 = fcmp oeq float %27, 0x7FF0000000000000 + %.not = xor i1 %28, true + %29 = tail call float @llvm.fabs.f32(float %__b) + %30 = fcmp une float %29, 0x7FF0000000000000 + %or.cond160 = and i1 %30, %.not + %31 = tail call float @llvm.fabs.f32(float %__c.addr.0) + %32 = fcmp ueq float %31, 0x7FF0000000000000 + %or.cond162 = select i1 %or.cond160, i1 true, i1 %32 + %33 = tail call float @llvm.fabs.f32(float %__d.addr.0) + %34 = fcmp ueq float %33, 0x7FF0000000000000 + %or.cond164 = select i1 %or.cond162, i1 true, i1 %34 + br i1 %or.cond164, label %if.else64, label %if.then45 + +if.then45: ; preds = %if.else + %conv48 = uitofp i1 %28 to float + %35 = tail call noundef float @llvm.copysign.f32(float %conv48, float %__a) + %36 = fcmp oeq float %29, 0x7FF0000000000000 + %conv53 = uitofp i1 %36 to float + %37 = tail call noundef float @llvm.copysign.f32(float %conv53, float %__b) + %mul56 = fmul float %37, %__d.addr.0 + %38 = tail call float @llvm.fmuladd.f32(float %35, float %__c.addr.0, float %mul56) + %mul57 = fmul float %38, 0x7FF0000000000000 + %39 = fneg float %35 + %neg61 = fmul float %__d.addr.0, %39 + %40 = tail call float @llvm.fmuladd.f32(float %37, float %__c.addr.0, float %neg61) + %mul62 = fmul float %40, 0x7FF0000000000000 + br label %if.end98 + +if.else64: ; preds = %if.else + %or.cond = fcmp une float %11, 0x7FF0000000000000 + %41 = fcmp ueq float %27, 0x7FF0000000000000 + %or.cond165 = or i1 %41, %or.cond + %42 = fcmp ueq float %29, 0x7FF0000000000000 + %or.cond167 = or i1 %42, %or.cond165 + br i1 %or.cond167, label %if.end98, label %if.then75 + +if.then75: ; preds = %if.else64 + %43 = fcmp oeq float %31, 0x7FF0000000000000 + %conv79 = uitofp i1 %43 to float + %44 = tail call noundef float @llvm.copysign.f32(float %conv79, float %__c.addr.0) + %45 = fcmp oeq float %33, 0x7FF0000000000000 + %conv84 = uitofp i1 %45 to float + %46 = tail call noundef float @llvm.copysign.f32(float %conv84, float %__d.addr.0) + %mul87 = fmul float %46, %__b + %47 = tail call float @llvm.fmuladd.f32(float %__a, float %44, float %mul87) + %mul88 = fmul float %47, 0.000000e+00 + %48 = fneg float %46 + %neg92 = fmul float %48, %__a + %49 = tail call float @llvm.fmuladd.f32(float %__b, float %44, float %neg92) + %mul93 = fmul float %49, 0.000000e+00 + br label %if.end98 + +if.end98: ; preds = %if.then28, %if.else64, %if.then75, %if.then45, %entry + %z.sroa.8.0 = phi float [ %mul62, %if.then45 ], [ %mul93, %if.then75 ], [ %21, %if.else64 ], [ %mul32, %if.then28 ], [ %21, %entry ] + %z.sroa.0.0 = phi float [ %mul57, %if.then45 ], [ %mul88, %if.then75 ], [ %18, %if.else64 ], [ %mul, %if.then28 ], [ %18, %entry ] + %50 = bitcast float %z.sroa.0.0 to i32 + %.fca.0.insert = insertvalue [2 x i32] poison, i32 %50, 0 + %51 = bitcast float %z.sroa.8.0 to i32 + %.fca.1.insert = insertvalue [2 x i32] %.fca.0.insert, i32 %51, 1 + ret [2 x i32] %.fca.1.insert +} + +; Function Attrs: cold mustprogress noinline nounwind optsize +define weak hidden { double, double } @cexp(double noundef %_a.coerce0, double noundef %_a.coerce1) local_unnamed_addr #11 { +entry: + %0 = tail call double @llvm.fabs.f64(double %_a.coerce1) #14 + %1 = fcmp olt double %0, 0x41D0000000000000 + br i1 %1, label %2, label %21 + +2: ; preds = %entry + %3 = fmul double %0, 0x3FE45F306DC9C883 + %4 = tail call double @llvm.rint.f64(double %3) + %5 = tail call double @llvm.fma.f64(double %4, double 0xBFF921FB54442D18, double %0) + %6 = tail call double @llvm.fma.f64(double %4, double 0xBC91A62633145C00, double %5) + %7 = fmul double %4, 0x3C91A62633145C00 + %8 = fneg double %7 + %9 = tail call double @llvm.fma.f64(double %4, double 0x3C91A62633145C00, double %8) + %10 = fsub double %5, %7 + %11 = fsub double %5, %10 + %12 = fsub double %11, %7 + %13 = fsub double %10, %6 + %14 = fadd double %13, %12 + %15 = fsub double %14, %9 + %16 = tail call double @llvm.fma.f64(double %4, double 0xB97B839A252049C0, double %15) + %17 = fadd double %6, %16 + %18 = fsub double %17, %6 + %19 = fsub double %16, %18 + %20 = fptosi double %4 to i32 + br label %__ocml_cexp_f64.exit + +21: ; preds = %entry + %22 = tail call double @llvm.amdgcn.trig.preop.f64(double %0, i32 0) + %23 = tail call double @llvm.amdgcn.trig.preop.f64(double %0, i32 1) + %24 = fcmp oge double %0, 0x7B00000000000000 + %25 = tail call double @llvm.ldexp.f64.i32(double %0, i32 -128) + %26 = select i1 %24, double %25, double %0 + %27 = fmul double %23, %26 + %28 = fmul double %22, %26 + %29 = fneg double %28 + %30 = tail call double @llvm.fma.f64(double %22, double %26, double %29) + %31 = fadd double %27, %30 + %32 = fadd double %28, %31 + %33 = tail call double @llvm.ldexp.f64.i32(double %32, i32 -2) + %34 = tail call double @llvm.floor.f64(double %33) + %35 = fsub double %33, %34 + %36 = tail call double @llvm.minnum.f64(double %35, double 0x3FEFFFFFFFFFFFFF) + %37 = fcmp uno double %33, 0.000000e+00 + %38 = select i1 %37, double %33, double %36 + %39 = tail call double @llvm.fabs.f64(double %33) + %40 = fcmp oeq double %39, 0x7FF0000000000000 + %41 = select i1 %40, double 0.000000e+00, double %38 + %42 = fsub double %31, %27 + %43 = fsub double %30, %42 + %44 = fsub double %31, %42 + %45 = fsub double %27, %44 + %46 = fadd double %43, %45 + %47 = fneg double %27 + %48 = tail call double @llvm.fma.f64(double %23, double %26, double %47) + %49 = tail call double @llvm.amdgcn.trig.preop.f64(double %0, i32 2) + %50 = fmul double %49, %26 + %51 = fadd double %50, %48 + %52 = fadd double %51, %46 + %53 = fsub double %32, %28 + %54 = fsub double %31, %53 + %55 = fadd double %54, %52 + %56 = fsub double %55, %54 + %57 = fsub double %52, %56 + %58 = fsub double %52, %51 + %59 = fsub double %46, %58 + %60 = fsub double %52, %58 + %61 = fsub double %51, %60 + %62 = fadd double %59, %61 + %63 = fsub double %51, %50 + %64 = fsub double %48, %63 + %65 = fsub double %51, %63 + %66 = fsub double %50, %65 + %67 = fadd double %64, %66 + %68 = fadd double %67, %62 + %69 = fneg double %50 + %70 = tail call double @llvm.fma.f64(double %49, double %26, double %69) + %71 = fadd double %70, %68 + %72 = fadd double %57, %71 + %73 = tail call double @llvm.ldexp.f64.i32(double %41, i32 2) + %74 = fadd double %55, %73 + %75 = fcmp olt double %74, 0.000000e+00 + %76 = select i1 %75, double 4.000000e+00, double 0.000000e+00 + %77 = fadd double %73, %76 + %78 = fadd double %55, %77 + %79 = fptosi double %78 to i32 + %80 = sitofp i32 %79 to double + %81 = fsub double %77, %80 + %82 = fadd double %55, %81 + %83 = fsub double %82, %81 + %84 = fsub double %55, %83 + %85 = fadd double %72, %84 + %86 = fcmp oge double %82, 5.000000e-01 + %87 = zext i1 %86 to i32 + %88 = add nsw i32 %87, %79 + %89 = select i1 %86, double 1.000000e+00, double 0.000000e+00 + %90 = fsub double %82, %89 + %91 = fadd double %90, %85 + %92 = fsub double %91, %90 + %93 = fsub double %85, %92 + %94 = fmul double %91, 0x3FF921FB54442D18 + %95 = fneg double %94 + %96 = tail call double @llvm.fma.f64(double %91, double 0x3FF921FB54442D18, double %95) + %97 = tail call double @llvm.fma.f64(double %91, double 0x3C91A62633145C07, double %96) + %98 = tail call double @llvm.fma.f64(double %93, double 0x3FF921FB54442D18, double %97) + %99 = fadd double %94, %98 + %100 = fsub double %99, %94 + %101 = fsub double %98, %100 + br label %__ocml_cexp_f64.exit + +__ocml_cexp_f64.exit: ; preds = %2, %21 + %.pn5.i.i.i = phi double [ %19, %2 ], [ %101, %21 ] + %.pn3.i.i.i = phi double [ %17, %2 ], [ %99, %21 ] + %.pn1.in.i.i.i = phi i32 [ %20, %2 ], [ %88, %21 ] + %102 = fmul double %.pn3.i.i.i, %.pn3.i.i.i + %103 = fmul double %102, 5.000000e-01 + %104 = fsub double 1.000000e+00, %103 + %105 = fsub double 1.000000e+00, %104 + %106 = fsub double %105, %103 + %107 = fmul double %102, %102 + %108 = tail call double @llvm.fma.f64(double %102, double 0xBDA907DB46CC5E42, double 0x3E21EEB69037AB78) + %109 = tail call double @llvm.fma.f64(double %102, double %108, double 0xBE927E4FA17F65F6) + %110 = tail call double @llvm.fma.f64(double %102, double %109, double 0x3EFA01A019F4EC90) + %111 = tail call double @llvm.fma.f64(double %102, double %110, double 0xBF56C16C16C16967) + %112 = tail call double @llvm.fma.f64(double %102, double %111, double 0x3FA5555555555555) + %113 = fneg double %.pn5.i.i.i + %114 = tail call double @llvm.fma.f64(double %.pn3.i.i.i, double %113, double %106) + %115 = tail call double @llvm.fma.f64(double %107, double %112, double %114) + %116 = fadd double %104, %115 + %117 = tail call double @llvm.fma.f64(double %102, double 0x3DE5E0B2F9A43BB8, double 0xBE5AE600B42FDFA7) + %118 = tail call double @llvm.fma.f64(double %102, double %117, double 0x3EC71DE3796CDE01) + %119 = tail call double @llvm.fma.f64(double %102, double %118, double 0xBF2A01A019E83E5C) + %120 = tail call double @llvm.fma.f64(double %102, double %119, double 0x3F81111111110BB3) + %121 = fneg double %102 + %122 = fmul double %.pn3.i.i.i, %121 + %123 = fmul double %.pn5.i.i.i, 5.000000e-01 + %124 = tail call double @llvm.fma.f64(double %122, double %120, double %123) + %125 = tail call double @llvm.fma.f64(double %102, double %124, double %113) + %126 = tail call double @llvm.fma.f64(double %122, double 0xBFC5555555555555, double %125) + %127 = fsub double %.pn3.i.i.i, %126 + %.pn1.i.i.i = shl i32 %.pn1.in.i.i.i, 30 + %128 = and i32 %.pn1.i.i.i, -2147483648 + %129 = and i32 %.pn1.in.i.i.i, 1 + %130 = icmp eq i32 %129, 0 + %131 = select i1 %130, double %127, double %116 + %132 = bitcast double %131 to <2 x i32> + %133 = bitcast double %_a.coerce1 to <2 x i32> + %134 = extractelement <2 x i32> %133, i64 1 + %135 = extractelement <2 x i32> %132, i64 1 + %136 = xor i32 %.pn1.i.i.i, %134 + %137 = and i32 %136, -2147483648 + %138 = xor i32 %135, %137 + %139 = insertelement <2 x i32> %132, i32 %138, i64 1 + %140 = fneg double %127 + %141 = select i1 %130, double %116, double %140 + %142 = bitcast double %141 to <2 x i32> + %143 = extractelement <2 x i32> %142, i64 1 + %144 = xor i32 %143, %128 + %145 = insertelement <2 x i32> %142, i32 %144, i64 1 + %146 = fcmp one double %0, 0x7FF0000000000000 + %147 = select i1 %146, <2 x i32> %139, <2 x i32> + %148 = select i1 %146, <2 x i32> %145, <2 x i32> + %149 = bitcast <2 x i32> %148 to double + %150 = bitcast <2 x i32> %147 to double + %151 = fcmp ogt double %_a.coerce0, 7.090000e+02 + %152 = select i1 %151, double 1.000000e+00, double 0.000000e+00 + %153 = fsub double %_a.coerce0, %152 + %154 = fmul double %153, 0x3FF71547652B82FE + %155 = tail call double @llvm.rint.f64(double %154) + %156 = fneg double %155 + %157 = tail call double @llvm.fma.f64(double %156, double 0x3FE62E42FEFA39EF, double %153) + %158 = tail call double @llvm.fma.f64(double %156, double 0x3C7ABC9E3B39803F, double %157) + %159 = tail call double @llvm.fma.f64(double %158, double 0x3E5ADE156A5DCB37, double 0x3E928AF3FCA7AB0C) + %160 = tail call double @llvm.fma.f64(double %158, double %159, double 0x3EC71DEE623FDE64) + %161 = tail call double @llvm.fma.f64(double %158, double %160, double 0x3EFA01997C89E6B0) + %162 = tail call double @llvm.fma.f64(double %158, double %161, double 0x3F2A01A014761F6E) + %163 = tail call double @llvm.fma.f64(double %158, double %162, double 0x3F56C16C1852B7B0) + %164 = tail call double @llvm.fma.f64(double %158, double %163, double 0x3F81111111122322) + %165 = tail call double @llvm.fma.f64(double %158, double %164, double 0x3FA55555555502A1) + %166 = tail call double @llvm.fma.f64(double %158, double %165, double 0x3FC5555555555511) + %167 = tail call double @llvm.fma.f64(double %158, double %166, double 0x3FE000000000000B) + %168 = tail call double @llvm.fma.f64(double %158, double %167, double 1.000000e+00) + %169 = tail call double @llvm.fma.f64(double %158, double %168, double 1.000000e+00) + %170 = fptosi double %155 to i32 + %171 = tail call double @llvm.ldexp.f64.i32(double %169, i32 %170) + %172 = fcmp ogt double %153, 1.024000e+03 + %173 = select i1 %172, double 0x7FF0000000000000, double %171 + %174 = fcmp olt double %153, -1.075000e+03 + %175 = select i1 %174, double 0.000000e+00, double %173 + %176 = fcmp uno double %_a.coerce0, 0.000000e+00 + %177 = fcmp oeq double %_a.coerce1, 0.000000e+00 + %178 = and i1 %176, %177 + %179 = fcmp oeq double %_a.coerce0, 0x7FF0000000000000 + %180 = fcmp oeq double %_a.coerce0, 0xFFF0000000000000 + %181 = select i1 %151, double 0x4005BF0A8B145769, double 1.000000e+00 + %182 = fmul double %181, %150 + %183 = fmul double %175, %182 + %184 = select i1 %146, double %183, double 0.000000e+00 + %185 = select i1 %180, double %184, double %183 + %186 = select i1 %146, double %185, double 0x7FF8000000000000 + %187 = select i1 %177, double %_a.coerce1, double %186 + %188 = select i1 %179, double %187, double %185 + %189 = select i1 %178, double %_a.coerce1, double %188 + %190 = fmul double %181, %149 + %191 = fmul double %175, %190 + %192 = select i1 %180, double 0.000000e+00, double %191 + %193 = select i1 %146, double %192, double 0x7FF0000000000000 + %194 = select i1 %179, double %193, double %192 + %.fca.0.insert = insertvalue { double, double } poison, double %194, 0 + %.fca.1.insert = insertvalue { double, double } %.fca.0.insert, double %189, 1 + ret { double, double } %.fca.1.insert +} + +; Function Attrs: cold mustprogress noinline nounwind optsize +define weak hidden [2 x i32] @cexpf([2 x i32] noundef %_a.coerce) local_unnamed_addr #11 { +entry: + %_a.coerce.fca.1.extract = extractvalue [2 x i32] %_a.coerce, 1 + %0 = bitcast i32 %_a.coerce.fca.1.extract to float + %1 = tail call float @llvm.fabs.f32(float %0) #14 + %2 = fcmp olt float %1, 1.310720e+05 + br i1 %2, label %3, label %10 + +3: ; preds = %entry + %4 = fmul float %1, 0x3FE45F3060000000 + %5 = tail call float @llvm.rint.f32(float %4) #14 + %6 = tail call float @llvm.fma.f32(float %5, float 0xBFF921FB40000000, float %1) #14 + %7 = tail call float @llvm.fma.f32(float %5, float 0xBE74442D00000000, float %6) #14 + %8 = tail call float @llvm.fma.f32(float %5, float 0xBCF8469880000000, float %7) #14 + %9 = fptosi float %5 to i32 + %.pre.i.i = bitcast float %1 to i32 + br label %__ocml_cexp_f32.exit + +10: ; preds = %entry + %11 = bitcast float %1 to i32 + %12 = lshr i32 %11, 23 + %13 = add nsw i32 %12, -120 + %14 = icmp ugt i32 %13, 63 + %15 = select i1 %14, i32 -64, i32 0 + %16 = add nsw i32 %15, %13 + %17 = icmp ugt i32 %16, 31 + %18 = select i1 %17, i32 -32, i32 0 + %19 = add nsw i32 %18, %16 + %20 = icmp ugt i32 %19, 31 + %21 = select i1 %20, i32 -32, i32 0 + %22 = add nsw i32 %21, %19 + %23 = icmp eq i32 %22, 0 + %24 = and i32 %11, 8388607 + %25 = or disjoint i32 %24, 8388608 + %26 = zext nneg i32 %25 to i64 + %27 = mul nuw nsw i64 %26, 4266746795 + %28 = lshr i64 %27, 32 + %29 = mul nuw nsw i64 %26, 1011060801 + %30 = add nuw nsw i64 %28, %29 + %31 = lshr i64 %30, 32 + %32 = mul nuw nsw i64 %26, 3680671129 + %33 = add nuw nsw i64 %31, %32 + %34 = lshr i64 %33, 32 + %35 = mul nuw nsw i64 %26, 4113882560 + %36 = add nuw nsw i64 %34, %35 + %37 = trunc i64 %36 to i32 + %38 = lshr i64 %36, 32 + %39 = mul nuw nsw i64 %26, 4230436817 + %40 = add nuw nsw i64 %38, %39 + %41 = lshr i64 %40, 32 + %42 = mul nuw nsw i64 %26, 1313084713 + %43 = add nuw nsw i64 %41, %42 + %44 = trunc i64 %43 to i32 + %45 = select i1 %14, i32 %37, i32 %44 + %46 = trunc i64 %40 to i32 + %47 = lshr i64 %43, 32 + %48 = mul nuw nsw i64 %26, 2734261102 + %49 = add nuw nsw i64 %47, %48 + %50 = trunc i64 %49 to i32 + %51 = select i1 %14, i32 %46, i32 %50 + %52 = select i1 %17, i32 %45, i32 %51 + %53 = lshr i64 %49, 32 + %54 = trunc i64 %53 to i32 + %55 = select i1 %14, i32 %44, i32 %54 + %56 = select i1 %17, i32 %51, i32 %55 + %57 = select i1 %20, i32 %52, i32 %56 + %58 = trunc i64 %33 to i32 + %59 = select i1 %14, i32 %58, i32 %46 + %60 = select i1 %17, i32 %59, i32 %45 + %61 = select i1 %20, i32 %60, i32 %52 + %62 = sub nsw i32 32, %22 + %63 = tail call i32 @llvm.fshr.i32(i32 %57, i32 %61, i32 %62) #14 + %64 = select i1 %23, i32 %57, i32 %63 + %65 = trunc i64 %30 to i32 + %66 = select i1 %14, i32 %65, i32 %37 + %67 = select i1 %17, i32 %66, i32 %59 + %68 = select i1 %20, i32 %67, i32 %60 + %69 = tail call i32 @llvm.fshr.i32(i32 %61, i32 %68, i32 %62) #14 + %70 = select i1 %23, i32 %61, i32 %69 + %71 = tail call i32 @llvm.fshl.i32(i32 %64, i32 %70, i32 2) #14 + %72 = lshr i32 %64, 29 + %73 = and i32 %72, 1 + %74 = sub nsw i32 0, %73 + %75 = xor i32 %71, %74 + %76 = trunc i64 %27 to i32 + %77 = select i1 %14, i32 %76, i32 %58 + %78 = select i1 %17, i32 %77, i32 %66 + %79 = select i1 %20, i32 %78, i32 %67 + %80 = tail call i32 @llvm.fshr.i32(i32 %68, i32 %79, i32 %62) #14 + %81 = select i1 %23, i32 %68, i32 %80 + %82 = tail call i32 @llvm.fshl.i32(i32 %70, i32 %81, i32 2) #14 + %83 = xor i32 %82, %74 + %84 = tail call i32 @llvm.ctlz.i32(i32 %75, i1 false) #14, !range !20 + %85 = sub nsw i32 31, %84 + %86 = tail call i32 @llvm.fshr.i32(i32 %75, i32 %83, i32 %85) #14 + %87 = tail call i32 @llvm.fshl.i32(i32 %81, i32 %79, i32 2) #14 + %88 = xor i32 %87, %74 + %89 = tail call i32 @llvm.fshr.i32(i32 %83, i32 %88, i32 %85) #14 + %90 = tail call i32 @llvm.fshl.i32(i32 %86, i32 %89, i32 23) #14 + %91 = tail call i32 @llvm.ctlz.i32(i32 %90, i1 false) #14, !range !20 + %92 = sub nsw i32 31, %91 + %93 = tail call i32 @llvm.fshr.i32(i32 %90, i32 %89, i32 %92) #14 + %94 = lshr i32 %93, 9 + %95 = add nuw nsw i32 %91, %84 + %96 = shl i32 %72, 31 + %97 = or disjoint i32 %96, 855638016 + %98 = shl nuw nsw i32 %95, 23 + %99 = sub nuw i32 %97, %98 + %100 = or disjoint i32 %99, %94 + %101 = bitcast i32 %100 to float + %102 = lshr i32 %86, 9 + %103 = or disjoint i32 %96, 1056964608 + %104 = shl nuw nsw i32 %84, 23 + %105 = sub nuw nsw i32 %103, %104 + %106 = or disjoint i32 %102, %105 + %107 = bitcast i32 %106 to float + %108 = fmul float %107, 0x3FF921FB40000000 + %109 = fneg float %108 + %110 = tail call float @llvm.fma.f32(float %107, float 0x3FF921FB40000000, float %109) #14 + %111 = tail call float @llvm.fma.f32(float %107, float 0x3E74442D00000000, float %110) #14 + %112 = tail call float @llvm.fma.f32(float %101, float 0x3FF921FB40000000, float %111) #14 + %113 = fadd float %108, %112 + %114 = lshr i32 %64, 30 + %115 = add nuw nsw i32 %73, %114 + br label %__ocml_cexp_f32.exit + +__ocml_cexp_f32.exit: ; preds = %3, %10 + %.pre-phi.i.i = phi i32 [ %.pre.i.i, %3 ], [ %11, %10 ] + %.pn3.in.i.i.i = phi float [ %8, %3 ], [ %113, %10 ] + %.pn1.in.i.i.i = phi i32 [ %9, %3 ], [ %115, %10 ] + %_a.coerce.fca.0.extract = extractvalue [2 x i32] %_a.coerce, 0 + %116 = bitcast i32 %_a.coerce.fca.0.extract to float + %117 = fmul float %.pn3.in.i.i.i, %.pn3.in.i.i.i + %118 = tail call noundef float @llvm.fmuladd.f32(float %117, float 0xBF29833040000000, float 0x3F81103880000000) + %119 = tail call noundef float @llvm.fmuladd.f32(float %117, float %118, float 0xBFC55553A0000000) + %120 = fmul float %117, %119 + %121 = tail call noundef float @llvm.fmuladd.f32(float %.pn3.in.i.i.i, float %120, float %.pn3.in.i.i.i) + %122 = tail call noundef float @llvm.fmuladd.f32(float %117, float 0x3EFAEA6680000000, float 0xBF56C9E760000000) + %123 = tail call noundef float @llvm.fmuladd.f32(float %117, float %122, float 0x3FA5557EE0000000) + %124 = tail call noundef float @llvm.fmuladd.f32(float %117, float %123, float 0xBFE0000080000000) + %125 = tail call noundef float @llvm.fmuladd.f32(float %117, float %124, float 1.000000e+00) + %.pn1.i.i.i = shl i32 %.pn1.in.i.i.i, 30 + %126 = and i32 %.pn1.i.i.i, -2147483648 + %127 = and i32 %.pn1.in.i.i.i, 1 + %128 = icmp eq i32 %127, 0 + %129 = select i1 %128, float %121, float %125 + %130 = bitcast float %129 to i32 + %131 = xor i32 %.pre-phi.i.i, %130 + %132 = xor i32 %131, %_a.coerce.fca.1.extract + %133 = xor i32 %132, %126 + %134 = bitcast i32 %133 to float + %135 = fneg float %121 + %136 = select i1 %128, float %125, float %135 + %137 = bitcast float %136 to i32 + %138 = xor i32 %126, %137 + %139 = bitcast i32 %138 to float + %140 = fcmp one float %1, 0x7FF0000000000000 + %141 = select i1 %140, float %139, float 0x7FF8000000000000 + %142 = select i1 %140, float %134, float 0x7FF8000000000000 + %143 = fcmp ogt float %116, 8.800000e+01 + %144 = select i1 %143, float 1.000000e+00, float 0.000000e+00 + %145 = fsub float %116, %144 + %146 = tail call noundef float @llvm.exp.f32(float %145) + %147 = fcmp uno float %116, 0.000000e+00 + %148 = fcmp oeq float %0, 0.000000e+00 + %149 = and i1 %147, %148 + %150 = fcmp oeq float %116, 0x7FF0000000000000 + %151 = fcmp oeq float %116, 0xFFF0000000000000 + %152 = select i1 %143, float 0x4005BF0A80000000, float 1.000000e+00 + %153 = fmul float %152, %142 + %154 = fmul float %146, %153 + %155 = select i1 %140, float %154, float 0.000000e+00 + %156 = select i1 %151, float %155, float %154 + %157 = select i1 %140, float %156, float 0x7FF8000000000000 + %158 = select i1 %148, float %0, float %157 + %159 = select i1 %150, float %158, float %156 + %160 = select i1 %149, float %0, float %159 + %161 = fmul float %152, %141 + %162 = fmul float %146, %161 + %163 = select i1 %151, float 0.000000e+00, float %162 + %164 = select i1 %140, float %163, float 0x7FF0000000000000 + %165 = select i1 %150, float %164, float %163 + %166 = bitcast float %165 to i32 + %.fca.0.insert = insertvalue [2 x i32] poison, i32 %166, 0 + %167 = bitcast float %160 to i32 + %.fca.1.insert = insertvalue [2 x i32] %.fca.0.insert, i32 %167, 1 + ret [2 x i32] %.fca.1.insert +} + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare double @llvm.fabs.f64(double) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare double @llvm.rint.f64(double) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare double @llvm.fma.f64(double, double, double) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare double @llvm.ldexp.f64.i32(double, i32) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare double @llvm.amdgcn.trig.preop.f64(double, i32) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare double @llvm.floor.f64(double) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare double @llvm.minnum.f64(double, double) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare float @llvm.fabs.f32(float) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare float @llvm.exp.f32(float) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare i32 @llvm.fshr.i32(i32, i32, i32) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare i32 @llvm.fshl.i32(i32, i32, i32) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare i32 @llvm.ctlz.i32(i32, i1 immarg) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare float @llvm.fma.f32(float, float, float) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare float @llvm.rint.f32(float) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare double @llvm.copysign.f64(double, double) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare float @llvm.copysign.f32(float, float) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare double @llvm.maxnum.f64(double, double) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare float @llvm.maxnum.f32(float, float) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare { double, i32 } @llvm.frexp.f64.i32(double) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare float @llvm.ldexp.f32.i32(float, i32) #12 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare i32 @llvm.smin.i32(i32, i32) #12 + +attributes #0 = { alwaysinline norecurse nounwind "amdgpu-flat-work-group-size"="1,256" "kernel" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" "uniform-work-group-size"="true" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { nounwind } +attributes #3 = { alwaysinline norecurse nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" } +attributes #4 = { norecurse nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" } +attributes #5 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) } +attributes #6 = { convergent norecurse nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" } +attributes #7 = { convergent nounwind } +attributes #8 = { alwaysinline } +attributes #9 = { mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" } +attributes #10 = { mustprogress nofree norecurse nosync nounwind willreturn memory(read, argmem: readwrite, inaccessiblemem: none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" } +attributes #11 = { cold mustprogress noinline nounwind optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64" } +attributes #12 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #13 = { nounwind memory(readwrite) } +attributes #14 = { nosync } + +!omp_offload.info = !{!0} +!nvvm.annotations = !{!1} +!llvm.module.flags = !{!2, !3, !4, !5, !6} +!opencl.ocl.version = !{!7} +!llvm.ident = !{!8} + +!0 = !{i32 0, i32 64768, i32 69609006, !"main", i32 15, i32 0, i32 0} +!1 = !{ptr @__omp_offloading_fd00_426262e_main_l15, !"kernel", i32 1} +!2 = !{i32 1, !"amdhsa_code_object_version", i32 500} +!3 = !{i32 1, !"wchar_size", i32 4} +!4 = !{i32 7, !"openmp", i32 51} +!5 = !{i32 7, !"openmp-device", i32 51} +!6 = !{i32 8, !"PIC Level", i32 2} +!7 = !{i32 2, i32 0} +!8 = !{!"AOMP_STANDALONE_19.0-0 clang version 19.0.0_AOMP_STANDALONE_19.0-0 (ssh://nicebert@gerrit-git.amd.com:29418/lightning/ec/llvm-project 4ee36e59440d581921c7e1d782a08208cf536cf0)"} +!9 = !{!10} +!10 = distinct !{!10, !11, !"__omp_offloading_fd00_426262e_main_l15_omp_outlined: %.global_tid."} +!11 = distinct !{!11, !"__omp_offloading_fd00_426262e_main_l15_omp_outlined"} +!12 = !{!13, !13, i64 0} +!13 = !{!"int", !14, i64 0} +!14 = !{!"omnipotent char", !15, i64 0} +!15 = !{!"Simple C++ TBAA"} +!16 = !{!17, !17, i64 0} +!17 = !{!"any pointer", !14, i64 0} +!18 = !{i64 0, i64 16, !19} +!19 = !{!14, !14, i64 0} +!20 = !{i32 0, i32 33} + diff --git a/llvm/test/Transforms/OpenMP/custom_state_machines.ll b/llvm/test/Transforms/OpenMP/custom_state_machines.ll index 2fe28daf304a6..27d6bcda05a42 100644 --- a/llvm/test/Transforms/OpenMP/custom_state_machines.ll +++ b/llvm/test/Transforms/OpenMP/custom_state_machines.ll @@ -1002,46 +1002,28 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU: @[[GLOB2:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8 ; AMDGPU: @G = external global i32, align 4 ; AMDGPU: @[[GLOB3:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8 -; AMDGPU: @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_outlined__2_wrapper.ID = private constant i8 undef -; AMDGPU: @__omp_outlined__3_wrapper.ID = private constant i8 undef -; AMDGPU: @__omp_outlined__5_wrapper.ID = private constant i8 undef -; AMDGPU: @__omp_outlined__7_wrapper.ID = private constant i8 undef -; AMDGPU: @__omp_outlined__8_wrapper.ID = private constant i8 undef -; AMDGPU: @__omp_outlined__10_wrapper.ID = private constant i8 undef -; AMDGPU: @__omp_outlined__11_wrapper.ID = private constant i8 undef -; AMDGPU: @__omp_outlined__13_wrapper.ID = private constant i8 undef -; AMDGPU: @__omp_outlined__14_wrapper.ID = private constant i8 undef +; AMDGPU: @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ;. ; NVPTX: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; NVPTX: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 ; NVPTX: @[[GLOB2:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8 ; NVPTX: @G = external global i32, align 4 ; NVPTX: @[[GLOB3:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8 -; NVPTX: @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_outlined__2_wrapper.ID = private constant i8 undef -; NVPTX: @__omp_outlined__3_wrapper.ID = private constant i8 undef -; NVPTX: @__omp_outlined__5_wrapper.ID = private constant i8 undef -; NVPTX: @__omp_outlined__7_wrapper.ID = private constant i8 undef -; NVPTX: @__omp_outlined__8_wrapper.ID = private constant i8 undef -; NVPTX: @__omp_outlined__10_wrapper.ID = private constant i8 undef -; NVPTX: @__omp_outlined__11_wrapper.ID = private constant i8 undef -; NVPTX: @__omp_outlined__13_wrapper.ID = private constant i8 undef -; NVPTX: @__omp_outlined__14_wrapper.ID = private constant i8 undef +; NVPTX: @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ;. ; AMDGPU-DISABLED: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; AMDGPU-DISABLED: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 @@ -1143,51 +1125,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22 ; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; AMDGPU-NEXT: entry: -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment, ptr [[DYN]]) -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: worker_state_machine.begin: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; AMDGPU: worker_state_machine.finished: -; AMDGPU-NEXT: ret void -; AMDGPU: worker_state_machine.is_active.check: -; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; AMDGPU: worker_state_machine.parallel_region.check: -; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__2_wrapper.ID -; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute: -; AMDGPU-NEXT: call void @__omp_outlined__2_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; AMDGPU: worker_state_machine.parallel_region.check1: -; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute2: -; AMDGPU-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.check3: -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.end: -; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU: worker_state_machine.done.barrier: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU: thread.user_code.check: ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; AMDGPU: user_code.entry: @@ -1208,9 +1150,9 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS1]] to ptr ; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR10]] -; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; AMDGPU-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]] -; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) +; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) ; AMDGPU-NEXT: ret void ; ; @@ -1264,57 +1206,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39 ; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; AMDGPU-NEXT: entry: -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment, ptr [[DYN]]) -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: worker_state_machine.begin: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; AMDGPU: worker_state_machine.finished: -; AMDGPU-NEXT: ret void -; AMDGPU: worker_state_machine.is_active.check: -; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; AMDGPU: worker_state_machine.parallel_region.check: -; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__17_wrapper -; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute: -; AMDGPU-NEXT: call void @__omp_outlined__17_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; AMDGPU: worker_state_machine.parallel_region.check1: -; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION4:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__5_wrapper.ID -; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION4]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute2: -; AMDGPU-NEXT: call void @__omp_outlined__5_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.check3: -; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE5:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK6:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute5: -; AMDGPU-NEXT: call void @__omp_outlined__18_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.check6: -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.end: -; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU: worker_state_machine.done.barrier: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU: thread.user_code.check: ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; AMDGPU: user_code.entry: @@ -1335,7 +1231,7 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR10]] ; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]] ; AMDGPU-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]] -; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]] ; AMDGPU-NEXT: ret void ; @@ -1411,53 +1307,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55 ; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; AMDGPU-NEXT: entry: -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment, ptr [[DYN]]) -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: worker_state_machine.begin: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; AMDGPU: worker_state_machine.finished: -; AMDGPU-NEXT: ret void -; AMDGPU: worker_state_machine.is_active.check: -; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; AMDGPU: worker_state_machine.parallel_region.check: -; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__7_wrapper.ID -; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute: -; AMDGPU-NEXT: call void @__omp_outlined__7_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; AMDGPU: worker_state_machine.parallel_region.check1: -; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION4:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__8_wrapper.ID -; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION4]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute2: -; AMDGPU-NEXT: call void @__omp_outlined__8_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.fallback.execute: -; AMDGPU-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.end: -; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU: worker_state_machine.done.barrier: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU: thread.user_code.check: ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; AMDGPU: user_code.entry: @@ -1477,9 +1331,9 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS1]] to ptr -; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; AMDGPU-NEXT: [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]] -; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) +; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) ; AMDGPU-NEXT: ret void ; ; @@ -1533,51 +1387,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66 ; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; AMDGPU-NEXT: entry: -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment, ptr [[DYN]]) -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: worker_state_machine.begin: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; AMDGPU: worker_state_machine.finished: -; AMDGPU-NEXT: ret void -; AMDGPU: worker_state_machine.is_active.check: -; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; AMDGPU: worker_state_machine.parallel_region.check: -; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__10_wrapper.ID -; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute: -; AMDGPU-NEXT: call void @__omp_outlined__10_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; AMDGPU: worker_state_machine.parallel_region.check1: -; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute2: -; AMDGPU-NEXT: call void @__omp_outlined__11_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.check3: -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.end: -; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU: worker_state_machine.done.barrier: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU: thread.user_code.check: ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; AMDGPU: user_code.entry: @@ -1597,9 +1411,9 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS1]] to ptr -; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR10]] -; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) +; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) ; AMDGPU-NEXT: ret void ; ; @@ -1653,51 +1467,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77 ; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; AMDGPU-NEXT: entry: -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment, ptr [[DYN]]) -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: worker_state_machine.begin: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; AMDGPU: worker_state_machine.finished: -; AMDGPU-NEXT: ret void -; AMDGPU: worker_state_machine.is_active.check: -; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; AMDGPU: worker_state_machine.parallel_region.check: -; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__13_wrapper.ID -; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute: -; AMDGPU-NEXT: call void @__omp_outlined__13_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; AMDGPU: worker_state_machine.parallel_region.check1: -; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]] -; AMDGPU: worker_state_machine.parallel_region.execute2: -; AMDGPU-NEXT: call void @__omp_outlined__14_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.check3: -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: worker_state_machine.parallel_region.end: -; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU: worker_state_machine.done.barrier: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU: thread.user_code.check: ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; AMDGPU: user_code.entry: @@ -1718,8 +1492,8 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS1]] to ptr ; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR10]] -; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) -; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) +; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) ; AMDGPU-NEXT: ret void ; ; @@ -1845,41 +1619,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112 ; AMDGPU-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; AMDGPU-NEXT: entry: -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment, ptr [[DYN]]) -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: worker_state_machine.begin: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; AMDGPU: worker_state_machine.finished: -; AMDGPU-NEXT: ret void -; AMDGPU: worker_state_machine.is_active.check: -; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; AMDGPU: worker_state_machine.parallel_region.fallback.execute: -; AMDGPU-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; AMDGPU: worker_state_machine.parallel_region.end: -; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU: worker_state_machine.done.barrier: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU: thread.user_code.check: ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; AMDGPU: user_code.entry: @@ -2069,50 +1813,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22 ; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; NVPTX-NEXT: entry: -; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment, ptr [[DYN]]) -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: worker_state_machine.begin: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; NVPTX: worker_state_machine.finished: -; NVPTX-NEXT: ret void -; NVPTX: worker_state_machine.is_active.check: -; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; NVPTX: worker_state_machine.parallel_region.check: -; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__2_wrapper.ID -; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute: -; NVPTX-NEXT: call void @__omp_outlined__2_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; NVPTX: worker_state_machine.parallel_region.check1: -; NVPTX-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute2: -; NVPTX-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.check3: -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.end: -; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX: worker_state_machine.done.barrier: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX: thread.user_code.check: ; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; NVPTX: user_code.entry: @@ -2133,9 +1838,9 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS1]] to ptr ; NVPTX-NEXT: call void @unknown_no_openmp() #[[ATTR10]] -; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; NVPTX-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]] -; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) +; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) ; NVPTX-NEXT: ret void ; ; @@ -2189,56 +1894,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39 ; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; NVPTX-NEXT: entry: -; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment, ptr [[DYN]]) -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: worker_state_machine.begin: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; NVPTX: worker_state_machine.finished: -; NVPTX-NEXT: ret void -; NVPTX: worker_state_machine.is_active.check: -; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; NVPTX: worker_state_machine.parallel_region.check: -; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__17_wrapper -; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute: -; NVPTX-NEXT: call void @__omp_outlined__17_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; NVPTX: worker_state_machine.parallel_region.check1: -; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION4:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__5_wrapper.ID -; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION4]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute2: -; NVPTX-NEXT: call void @__omp_outlined__5_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.check3: -; NVPTX-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE5:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK6:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute5: -; NVPTX-NEXT: call void @__omp_outlined__18_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.check6: -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.end: -; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX: worker_state_machine.done.barrier: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX: thread.user_code.check: ; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; NVPTX: user_code.entry: @@ -2259,7 +1919,7 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-NEXT: call void @unknown_no_openmp() #[[ATTR10]] ; NVPTX-NEXT: call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]] ; NVPTX-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR9]] -; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; NVPTX-NEXT: call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]] ; NVPTX-NEXT: ret void ; @@ -2335,52 +1995,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55 ; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; NVPTX-NEXT: entry: -; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment, ptr [[DYN]]) -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: worker_state_machine.begin: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; NVPTX: worker_state_machine.finished: -; NVPTX-NEXT: ret void -; NVPTX: worker_state_machine.is_active.check: -; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; NVPTX: worker_state_machine.parallel_region.check: -; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__7_wrapper.ID -; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute: -; NVPTX-NEXT: call void @__omp_outlined__7_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; NVPTX: worker_state_machine.parallel_region.check1: -; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION4:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__8_wrapper.ID -; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION4]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute2: -; NVPTX-NEXT: call void @__omp_outlined__8_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.fallback.execute: -; NVPTX-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.end: -; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX: worker_state_machine.done.barrier: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX: thread.user_code.check: ; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; NVPTX: user_code.entry: @@ -2400,9 +2019,9 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS1]] to ptr -; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; NVPTX-NEXT: [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]] -; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) +; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) ; NVPTX-NEXT: ret void ; ; @@ -2456,50 +2075,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66 ; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; NVPTX-NEXT: entry: -; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment, ptr [[DYN]]) -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: worker_state_machine.begin: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; NVPTX: worker_state_machine.finished: -; NVPTX-NEXT: ret void -; NVPTX: worker_state_machine.is_active.check: -; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; NVPTX: worker_state_machine.parallel_region.check: -; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__10_wrapper.ID -; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute: -; NVPTX-NEXT: call void @__omp_outlined__10_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; NVPTX: worker_state_machine.parallel_region.check1: -; NVPTX-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute2: -; NVPTX-NEXT: call void @__omp_outlined__11_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.check3: -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.end: -; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX: worker_state_machine.done.barrier: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX: thread.user_code.check: ; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; NVPTX: user_code.entry: @@ -2519,9 +2099,9 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS1]] to ptr -; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; NVPTX-NEXT: call void @unknown_no_openmp() #[[ATTR10]] -; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) +; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) ; NVPTX-NEXT: ret void ; ; @@ -2575,50 +2155,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77 ; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; NVPTX-NEXT: entry: -; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment, ptr [[DYN]]) -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: worker_state_machine.begin: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; NVPTX: worker_state_machine.finished: -; NVPTX-NEXT: ret void -; NVPTX: worker_state_machine.is_active.check: -; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; NVPTX: worker_state_machine.parallel_region.check: -; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__13_wrapper.ID -; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute: -; NVPTX-NEXT: call void @__omp_outlined__13_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; NVPTX: worker_state_machine.parallel_region.check1: -; NVPTX-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK3:%.*]] -; NVPTX: worker_state_machine.parallel_region.execute2: -; NVPTX-NEXT: call void @__omp_outlined__14_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.check3: -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: worker_state_machine.parallel_region.end: -; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX: worker_state_machine.done.barrier: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX: thread.user_code.check: ; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; NVPTX: user_code.entry: @@ -2639,8 +2180,8 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS1_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS1]] to ptr ; NVPTX-NEXT: call void @unknown_no_openmp() #[[ATTR10]] -; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) -; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) +; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr [[CAPTURED_VARS_ADDRS1_CAST]], i64 0) ; NVPTX-NEXT: ret void ; ; @@ -2766,40 +2307,11 @@ attributes #9 = { convergent nounwind willreturn memory(read) } ; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112 ; NVPTX-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; NVPTX-NEXT: entry: -; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment, ptr [[DYN]]) -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: worker_state_machine.begin: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; NVPTX: worker_state_machine.finished: -; NVPTX-NEXT: ret void -; NVPTX: worker_state_machine.is_active.check: -; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; NVPTX: worker_state_machine.parallel_region.fallback.execute: -; NVPTX-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; NVPTX: worker_state_machine.parallel_region.end: -; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX: worker_state_machine.done.barrier: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX: thread.user_code.check: ; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; NVPTX: user_code.entry: diff --git a/llvm/test/Transforms/OpenMP/custom_state_machines_remarks.ll b/llvm/test/Transforms/OpenMP/custom_state_machines_remarks.ll index 60969ecb683bf..9dfcbb73a67f9 100644 --- a/llvm/test/Transforms/OpenMP/custom_state_machines_remarks.ll +++ b/llvm/test/Transforms/OpenMP/custom_state_machines_remarks.ll @@ -1,3 +1,5 @@ +; XFAIL: * +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -passes=openmp-opt -pass-remarks=openmp-opt -pass-remarks-missed=openmp-opt -pass-remarks-analysis=openmp-opt -disable-output < %s 2>&1 | FileCheck %s target triple = "nvptx64" diff --git a/llvm/test/Transforms/OpenMP/gpu_state_machine_function_ptr_replacement.ll b/llvm/test/Transforms/OpenMP/gpu_state_machine_function_ptr_replacement.ll index 760c5a354a37c..a2d0bb95ed7d2 100644 --- a/llvm/test/Transforms/OpenMP/gpu_state_machine_function_ptr_replacement.ll +++ b/llvm/test/Transforms/OpenMP/gpu_state_machine_function_ptr_replacement.ll @@ -1,6 +1,9 @@ ; RUN: opt -S -passes=openmp-opt -openmp-ir-builder-optimistic-attributes -pass-remarks=openmp-opt -openmp-print-gpu-kernels < %s | FileCheck %s ; RUN: opt -S -passes=openmp-opt -pass-remarks=openmp-opt -openmp-print-gpu-kernels < %s | FileCheck %s +; fix it later +; XFAIL: * + ; C input used for this test: ; void bar(void) { diff --git a/llvm/test/Transforms/OpenMP/remove_globalization.ll b/llvm/test/Transforms/OpenMP/remove_globalization.ll index 419d3d07c2bea..fdb4500518903 100644 --- a/llvm/test/Transforms/OpenMP/remove_globalization.ll +++ b/llvm/test/Transforms/OpenMP/remove_globalization.ll @@ -21,10 +21,10 @@ ; Make it a weak definition so we will apply custom state machine rewriting but can't use the body in the reasoning. ;. ; CHECK: @S = external local_unnamed_addr global ptr -; CHECK: @kernel_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr null, ptr null } +; CHECK: @kernel_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr null, ptr null } ;. ; CHECK-DISABLED: @S = external local_unnamed_addr global ptr -; CHECK-DISABLED: @kernel_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr null, ptr null } +; CHECK-DISABLED: @kernel_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr null, ptr null } ;. define weak i32 @__kmpc_target_init(ptr %0, ptr) { ; CHECK-LABEL: define {{[^@]+}}@__kmpc_target_init diff --git a/llvm/test/Transforms/OpenMP/spmdization.ll b/llvm/test/Transforms/OpenMP/spmdization.ll index 19d447449dee4..ec193016926c2 100644 --- a/llvm/test/Transforms/OpenMP/spmdization.ll +++ b/llvm/test/Transforms/OpenMP/spmdization.ll @@ -107,45 +107,38 @@ ;. ; AMDGPU: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; AMDGPU: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 -; AMDGPU: @__omp_offloading_fd02_2044372e_sequential_loop_l5_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_fd02_2044372e_sequential_loop_l5_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ; AMDGPU: @[[GLOB2:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, ptr @[[GLOB0]] }, align 8 ; AMDGPU: @x_shared = internal addrspace(3) global [4 x i8] poison, align 4 ; AMDGPU: @x_shared.1 = internal addrspace(3) global [4 x i8] poison, align 4 -; AMDGPU: @__omp_outlined__9_wrapper.ID = private constant i8 undef ;. ; NVPTX: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; NVPTX: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 -; NVPTX: @__omp_offloading_fd02_2044372e_sequential_loop_l5_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_fd02_2044372e_sequential_loop_l5_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ; NVPTX: @[[GLOB2:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, ptr @[[GLOB0]] }, align 8 ; NVPTX: @x_shared = internal addrspace(3) global [4 x i8] poison, align 4 ; NVPTX: @x_shared1 = internal addrspace(3) global [4 x i8] poison, align 4 -; NVPTX: @__omp_outlined__9_wrapper.ID = private constant i8 undef ;. ; AMDGPU-DISABLED1: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; AMDGPU-DISABLED1: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 -; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_l5_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_l5_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU-DISABLED1: @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ; AMDGPU-DISABLED1: @x_shared = internal addrspace(3) global [4 x i8] poison, align 4 ; AMDGPU-DISABLED1: @x_shared.1 = internal addrspace(3) global [4 x i8] poison, align 4 -; AMDGPU-DISABLED1: @__omp_outlined__1_wrapper.ID = private constant i8 undef -; AMDGPU-DISABLED1: @__omp_outlined__3_wrapper.ID = private constant i8 undef -; AMDGPU-DISABLED1: @__omp_outlined__5_wrapper.ID = private constant i8 undef -; AMDGPU-DISABLED1: @__omp_outlined__7_wrapper.ID = private constant i8 undef -; AMDGPU-DISABLED1: @__omp_outlined__9_wrapper.ID = private constant i8 undef ;. ; AMDGPU-DISABLED2: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; AMDGPU-DISABLED2: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 @@ -160,19 +153,14 @@ ;. ; NVPTX-DISABLED1: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; NVPTX-DISABLED1: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 -; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_l5_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_l5_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX-DISABLED1: @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ; NVPTX-DISABLED1: @x_shared = internal addrspace(3) global [4 x i8] poison, align 4 ; NVPTX-DISABLED1: @x_shared1 = internal addrspace(3) global [4 x i8] poison, align 4 -; NVPTX-DISABLED1: @__omp_outlined__1_wrapper.ID = private constant i8 undef -; NVPTX-DISABLED1: @__omp_outlined__3_wrapper.ID = private constant i8 undef -; NVPTX-DISABLED1: @__omp_outlined__5_wrapper.ID = private constant i8 undef -; NVPTX-DISABLED1: @__omp_outlined__7_wrapper.ID = private constant i8 undef -; NVPTX-DISABLED1: @__omp_outlined__9_wrapper.ID = private constant i8 undef ;. ; NVPTX-DISABLED2: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; NVPTX-DISABLED2: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 @@ -262,45 +250,11 @@ define internal void @__omp_offloading_fd02_2044372e_sequential_loop_l5__debug() ; AMDGPU-DISABLED1-LABEL: define internal void @__omp_offloading_fd02_2044372e_sequential_loop_l5__debug( ; AMDGPU-DISABLED1-SAME: ) #[[ATTR1:[0-9]+]] { ; AMDGPU-DISABLED1-NEXT: [[ENTRY:.*:]] -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-DISABLED1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_sequential_loop_l5_kernel_environment, ptr null) -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; AMDGPU-DISABLED1: [[IS_WORKER_CHECK]]: -; AMDGPU-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; AMDGPU-DISABLED1-NEXT: ret void -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; AMDGPU-DISABLED1-NEXT: br i1 true, label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; AMDGPU-DISABLED1-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1]]: -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; AMDGPU-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; AMDGPU-DISABLED1: [[COMMON_RET]]: @@ -334,44 +288,11 @@ define internal void @__omp_offloading_fd02_2044372e_sequential_loop_l5__debug() ; NVPTX-DISABLED1-LABEL: define internal void @__omp_offloading_fd02_2044372e_sequential_loop_l5__debug( ; NVPTX-DISABLED1-SAME: ) #[[ATTR1:[0-9]+]] { ; NVPTX-DISABLED1-NEXT: [[ENTRY:.*:]] -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-DISABLED1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-DISABLED1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_sequential_loop_l5_kernel_environment, ptr null) -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; NVPTX-DISABLED1: [[IS_WORKER_CHECK]]: -; NVPTX-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; NVPTX-DISABLED1-NEXT: ret void -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; NVPTX-DISABLED1-NEXT: br i1 true, label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; NVPTX-DISABLED1-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1]]: -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; NVPTX-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; NVPTX-DISABLED1: [[COMMON_RET]]: @@ -480,7 +401,7 @@ define internal void @__omp_outlined__(ptr noalias %.global_tid., ptr noalias %. ; AMDGPU-DISABLED1: [[FOR_BODY]]: ; AMDGPU-DISABLED1-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[DOTGLOBAL_TID_]] to ptr addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4, !tbaa [[INT_TBAA12]] -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__1, ptr @__omp_outlined__1_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; AMDGPU-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__1, ptr @__omp_outlined__1_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; AMDGPU-DISABLED1-NEXT: [[INC]] = add nsw i32 [[I_0]], 1 ; AMDGPU-DISABLED1-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] ; @@ -520,7 +441,7 @@ define internal void @__omp_outlined__(ptr noalias %.global_tid., ptr noalias %. ; NVPTX-DISABLED1: [[FOR_BODY]]: ; NVPTX-DISABLED1-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[DOTGLOBAL_TID_]] to ptr addrspace(5) ; NVPTX-DISABLED1-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4, !tbaa [[INT_TBAA12]] -; NVPTX-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__1, ptr @__omp_outlined__1_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; NVPTX-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__1, ptr @__omp_outlined__1_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; NVPTX-DISABLED1-NEXT: [[INC]] = add nsw i32 [[I_0]], 1 ; NVPTX-DISABLED1-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] ; @@ -744,45 +665,11 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_s ; AMDGPU-DISABLED1-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20( ; AMDGPU-DISABLED1-SAME: ) #[[ATTR0]] { ; AMDGPU-DISABLED1-NEXT: [[ENTRY:.*:]] -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-DISABLED1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20_kernel_environment, ptr null) -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; AMDGPU-DISABLED1: [[IS_WORKER_CHECK]]: -; AMDGPU-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; AMDGPU-DISABLED1-NEXT: ret void -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; AMDGPU-DISABLED1-NEXT: br i1 true, label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; AMDGPU-DISABLED1-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1]]: -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; AMDGPU-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; AMDGPU-DISABLED1: [[COMMON_RET]]: @@ -816,44 +703,11 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_s ; NVPTX-DISABLED1-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20( ; NVPTX-DISABLED1-SAME: ) #[[ATTR0]] { ; NVPTX-DISABLED1-NEXT: [[ENTRY:.*:]] -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-DISABLED1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-DISABLED1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20_kernel_environment, ptr null) -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; NVPTX-DISABLED1: [[IS_WORKER_CHECK]]: -; NVPTX-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; NVPTX-DISABLED1-NEXT: ret void -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; NVPTX-DISABLED1-NEXT: br i1 true, label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; NVPTX-DISABLED1-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1]]: -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; NVPTX-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; NVPTX-DISABLED1: [[COMMON_RET]]: @@ -970,7 +824,7 @@ define internal void @__omp_outlined__2(ptr noalias %.global_tid., ptr noalias % ; AMDGPU-DISABLED1: [[FOR_BODY]]: ; AMDGPU-DISABLED1-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[DOTGLOBAL_TID_]] to ptr addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4, !tbaa [[INT_TBAA12]] -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; AMDGPU-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; AMDGPU-DISABLED1-NEXT: [[INC]] = add nsw i32 [[I_0]], 1 ; AMDGPU-DISABLED1-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] ; @@ -1015,7 +869,7 @@ define internal void @__omp_outlined__2(ptr noalias %.global_tid., ptr noalias % ; NVPTX-DISABLED1: [[FOR_BODY]]: ; NVPTX-DISABLED1-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[DOTGLOBAL_TID_]] to ptr addrspace(5) ; NVPTX-DISABLED1-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4, !tbaa [[INT_TBAA12]] -; NVPTX-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; NVPTX-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; NVPTX-DISABLED1-NEXT: [[INC]] = add nsw i32 [[I_0]], 1 ; NVPTX-DISABLED1-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] ; @@ -1244,45 +1098,11 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_s ; AMDGPU-DISABLED1-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35( ; AMDGPU-DISABLED1-SAME: ) #[[ATTR0]] { ; AMDGPU-DISABLED1-NEXT: [[ENTRY:.*:]] -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-DISABLED1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35_kernel_environment, ptr null) -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; AMDGPU-DISABLED1: [[IS_WORKER_CHECK]]: -; AMDGPU-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; AMDGPU-DISABLED1-NEXT: ret void -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; AMDGPU-DISABLED1-NEXT: br i1 true, label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; AMDGPU-DISABLED1-NEXT: call void @__omp_outlined__5_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1]]: -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; AMDGPU-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; AMDGPU-DISABLED1: [[COMMON_RET]]: @@ -1316,44 +1136,11 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_s ; NVPTX-DISABLED1-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35( ; NVPTX-DISABLED1-SAME: ) #[[ATTR0]] { ; NVPTX-DISABLED1-NEXT: [[ENTRY:.*:]] -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-DISABLED1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-DISABLED1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35_kernel_environment, ptr null) -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; NVPTX-DISABLED1: [[IS_WORKER_CHECK]]: -; NVPTX-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; NVPTX-DISABLED1-NEXT: ret void -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; NVPTX-DISABLED1-NEXT: br i1 true, label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; NVPTX-DISABLED1-NEXT: call void @__omp_outlined__5_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1]]: -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; NVPTX-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; NVPTX-DISABLED1: [[COMMON_RET]]: @@ -1465,7 +1252,7 @@ define internal void @__omp_outlined__4(ptr noalias %.global_tid., ptr noalias % ; AMDGPU-DISABLED1-NEXT: store ptr addrspacecast (ptr addrspace(3) @x_shared to ptr), ptr addrspace(5) [[CAPTURED_VARS_ADDRS]], align 8, !tbaa [[ANYPTR_TBAA20:![0-9]+]] ; AMDGPU-DISABLED1-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[DOTGLOBAL_TID_]] to ptr addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4, !tbaa [[INT_TBAA12]] -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 1) +; AMDGPU-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 1) ; AMDGPU-DISABLED1-NEXT: [[INC]] = add nsw i32 [[I_0]], 1 ; AMDGPU-DISABLED1-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] ; @@ -1507,7 +1294,7 @@ define internal void @__omp_outlined__4(ptr noalias %.global_tid., ptr noalias % ; NVPTX-DISABLED1-NEXT: store ptr addrspacecast (ptr addrspace(3) @x_shared to ptr), ptr addrspace(5) [[CAPTURED_VARS_ADDRS]], align 8, !tbaa [[ANYPTR_TBAA20:![0-9]+]] ; NVPTX-DISABLED1-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[DOTGLOBAL_TID_]] to ptr addrspace(5) ; NVPTX-DISABLED1-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4, !tbaa [[INT_TBAA12]] -; NVPTX-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 1) +; NVPTX-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 1) ; NVPTX-DISABLED1-NEXT: [[INC]] = add nsw i32 [[I_0]], 1 ; NVPTX-DISABLED1-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] ; @@ -1770,45 +1557,11 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_s ; AMDGPU-DISABLED1-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50( ; AMDGPU-DISABLED1-SAME: ) #[[ATTR0]] { ; AMDGPU-DISABLED1-NEXT: [[ENTRY:.*:]] -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-DISABLED1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50_kernel_environment, ptr null) -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; AMDGPU-DISABLED1: [[IS_WORKER_CHECK]]: -; AMDGPU-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; AMDGPU-DISABLED1-NEXT: ret void -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; AMDGPU-DISABLED1-NEXT: br i1 true, label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; AMDGPU-DISABLED1-NEXT: call void @__omp_outlined__7_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1]]: -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; AMDGPU-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; AMDGPU-DISABLED1: [[COMMON_RET]]: @@ -1842,44 +1595,11 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_s ; NVPTX-DISABLED1-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50( ; NVPTX-DISABLED1-SAME: ) #[[ATTR0]] { ; NVPTX-DISABLED1-NEXT: [[ENTRY:.*:]] -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-DISABLED1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-DISABLED1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50_kernel_environment, ptr null) -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; NVPTX-DISABLED1: [[IS_WORKER_CHECK]]: -; NVPTX-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; NVPTX-DISABLED1-NEXT: ret void -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; NVPTX-DISABLED1-NEXT: br i1 true, label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; NVPTX-DISABLED1-NEXT: call void @__omp_outlined__7_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1]]: -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; NVPTX-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; NVPTX-DISABLED1: [[COMMON_RET]]: @@ -2020,7 +1740,7 @@ define internal void @__omp_outlined__6(ptr noalias %.global_tid., ptr noalias % ; AMDGPU-DISABLED1-NEXT: store ptr addrspacecast (ptr addrspace(3) @x_shared.1 to ptr), ptr addrspace(5) [[CAPTURED_VARS_ADDRS]], align 8, !tbaa [[ANYPTR_TBAA20]] ; AMDGPU-DISABLED1-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[DOTGLOBAL_TID_]] to ptr addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4, !tbaa [[INT_TBAA12]] -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 1) +; AMDGPU-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 1) ; AMDGPU-DISABLED1-NEXT: [[INC]] = add nsw i32 [[I_0]], 1 ; AMDGPU-DISABLED1-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] ; @@ -2064,7 +1784,7 @@ define internal void @__omp_outlined__6(ptr noalias %.global_tid., ptr noalias % ; NVPTX-DISABLED1-NEXT: store ptr addrspacecast (ptr addrspace(3) @x_shared1 to ptr), ptr addrspace(5) [[CAPTURED_VARS_ADDRS]], align 8, !tbaa [[ANYPTR_TBAA20]] ; NVPTX-DISABLED1-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[DOTGLOBAL_TID_]] to ptr addrspace(5) ; NVPTX-DISABLED1-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4, !tbaa [[INT_TBAA12]] -; NVPTX-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 1) +; NVPTX-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 1) ; NVPTX-DISABLED1-NEXT: [[INC]] = add nsw i32 [[I_0]], 1 ; NVPTX-DISABLED1-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] ; @@ -2291,41 +2011,11 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_targe ; AMDGPU-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65( ; AMDGPU-SAME: ) #[[ATTR0]] { ; AMDGPU-NEXT: [[ENTRY:.*:]] -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment, ptr null) -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; AMDGPU: [[IS_WORKER_CHECK]]: -; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_BEGIN]]: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_FINISHED]]: -; AMDGPU-NEXT: ret void -; AMDGPU: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; AMDGPU-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU: [[THREAD_USER_CODE_CHECK]]: ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; AMDGPU: [[COMMON_RET]]: @@ -2339,40 +2029,11 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_targe ; NVPTX-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65( ; NVPTX-SAME: ) #[[ATTR0]] { ; NVPTX-NEXT: [[ENTRY:.*:]] -; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment, ptr null) -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; NVPTX: [[IS_WORKER_CHECK]]: -; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_BEGIN]]: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_FINISHED]]: -; NVPTX-NEXT: ret void -; NVPTX: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; NVPTX-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX: [[THREAD_USER_CODE_CHECK]]: ; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; NVPTX: [[COMMON_RET]]: @@ -2386,41 +2047,11 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_targe ; AMDGPU-DISABLED1-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65( ; AMDGPU-DISABLED1-SAME: ) #[[ATTR0]] { ; AMDGPU-DISABLED1-NEXT: [[ENTRY:.*:]] -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-DISABLED1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment, ptr null) -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; AMDGPU-DISABLED1: [[IS_WORKER_CHECK]]: -; AMDGPU-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; AMDGPU-DISABLED1-NEXT: ret void -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; AMDGPU-DISABLED1-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; AMDGPU-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; AMDGPU-DISABLED1: [[COMMON_RET]]: @@ -2452,40 +2083,11 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_targe ; NVPTX-DISABLED1-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65( ; NVPTX-DISABLED1-SAME: ) #[[ATTR0]] { ; NVPTX-DISABLED1-NEXT: [[ENTRY:.*:]] -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-DISABLED1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-DISABLED1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65_kernel_environment, ptr null) -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; NVPTX-DISABLED1: [[IS_WORKER_CHECK]]: -; NVPTX-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; NVPTX-DISABLED1-NEXT: ret void -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; NVPTX-DISABLED1-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; NVPTX-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; NVPTX-DISABLED1: [[COMMON_RET]]: @@ -2582,45 +2184,9 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_ ; AMDGPU-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74( ; AMDGPU-SAME: ) #[[ATTR0]] { ; AMDGPU-NEXT: [[ENTRY:.*:]] -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment, ptr null) -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; AMDGPU: [[IS_WORKER_CHECK]]: -; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_BEGIN]]: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_FINISHED]]: -; AMDGPU-NEXT: ret void -; AMDGPU: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__9_wrapper.ID -; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; AMDGPU-NEXT: call void @__omp_outlined__9_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; AMDGPU-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU: [[THREAD_USER_CODE_CHECK]]: ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; AMDGPU: [[COMMON_RET]]: @@ -2629,51 +2195,16 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_ ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR4]] ; AMDGPU-NEXT: [[TMP2:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 40, i64 0, ptr @"_omp_task_entry$") #[[ATTR4]] ; AMDGPU-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP2]]) #[[ATTR4]] -; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__9, ptr @__omp_outlined__9_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__9, ptr @__omp_outlined__9_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; AMDGPU-NEXT: call void @__kmpc_target_deinit() ; AMDGPU-NEXT: br label %[[COMMON_RET]] ; ; NVPTX-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74( ; NVPTX-SAME: ) #[[ATTR0]] { ; NVPTX-NEXT: [[ENTRY:.*:]] -; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment, ptr null) -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; NVPTX: [[IS_WORKER_CHECK]]: -; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_BEGIN]]: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_FINISHED]]: -; NVPTX-NEXT: ret void -; NVPTX: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; NVPTX-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__9_wrapper.ID -; NVPTX-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; NVPTX-NEXT: call void @__omp_outlined__9_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; NVPTX-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX: [[THREAD_USER_CODE_CHECK]]: ; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; NVPTX: [[COMMON_RET]]: @@ -2682,52 +2213,16 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_ ; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR4]] ; NVPTX-NEXT: [[TMP2:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 40, i64 0, ptr @"_omp_task_entry$") #[[ATTR4]] ; NVPTX-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP2]]) #[[ATTR4]] -; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__9, ptr @__omp_outlined__9_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__9, ptr @__omp_outlined__9_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; NVPTX-NEXT: call void @__kmpc_target_deinit() ; NVPTX-NEXT: br label %[[COMMON_RET]] ; ; AMDGPU-DISABLED1-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74( ; AMDGPU-DISABLED1-SAME: ) #[[ATTR0]] { ; AMDGPU-DISABLED1-NEXT: [[ENTRY:.*:]] -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-DISABLED1-NEXT: [[CAPTURED_VARS_ADDRS_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr ; AMDGPU-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment, ptr null) -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; AMDGPU-DISABLED1: [[IS_WORKER_CHECK]]: -; AMDGPU-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; AMDGPU-DISABLED1-NEXT: ret void -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; AMDGPU-DISABLED1-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__9_wrapper.ID -; AMDGPU-DISABLED1-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; AMDGPU-DISABLED1-NEXT: call void @__omp_outlined__9_wrapper(i16 0, i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; AMDGPU-DISABLED1-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; AMDGPU-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; AMDGPU-DISABLED1: [[COMMON_RET]]: @@ -2736,7 +2231,7 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_ ; AMDGPU-DISABLED1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR4]] ; AMDGPU-DISABLED1-NEXT: [[TMP2:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 40, i64 0, ptr @"_omp_task_entry$") #[[ATTR4]] ; AMDGPU-DISABLED1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP2]]) #[[ATTR4]] -; AMDGPU-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__9, ptr @__omp_outlined__9_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; AMDGPU-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__9, ptr @__omp_outlined__9_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; AMDGPU-DISABLED1-NEXT: call void @__kmpc_target_deinit() ; AMDGPU-DISABLED1-NEXT: br label %[[COMMON_RET]] ; @@ -2761,44 +2256,9 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_ ; NVPTX-DISABLED1-LABEL: define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74( ; NVPTX-DISABLED1-SAME: ) #[[ATTR0]] { ; NVPTX-DISABLED1-NEXT: [[ENTRY:.*:]] -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-DISABLED1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-DISABLED1-NEXT: [[CAPTURED_VARS_ADDRS_CAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr ; NVPTX-DISABLED1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74_kernel_environment, ptr null) -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; NVPTX-DISABLED1: [[IS_WORKER_CHECK]]: -; NVPTX-DISABLED1-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-DISABLED1-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-DISABLED1-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-DISABLED1-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED1-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_BEGIN]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-DISABLED1-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-DISABLED1-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_FINISHED]]: -; NVPTX-DISABLED1-NEXT: ret void -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK]]: -; NVPTX-DISABLED1-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], @__omp_outlined__9_wrapper.ID -; NVPTX-DISABLED1-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE]]: -; NVPTX-DISABLED1-NEXT: call void @__omp_outlined__9_wrapper(i16 0, i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; NVPTX-DISABLED1-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX-DISABLED1: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; NVPTX-DISABLED1-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-DISABLED1-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX-DISABLED1: [[THREAD_USER_CODE_CHECK]]: ; NVPTX-DISABLED1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-DISABLED1-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; NVPTX-DISABLED1: [[COMMON_RET]]: @@ -2807,7 +2267,7 @@ define weak ptx_kernel void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_ ; NVPTX-DISABLED1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR4]] ; NVPTX-DISABLED1-NEXT: [[TMP2:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 40, i64 0, ptr @"_omp_task_entry$") #[[ATTR4]] ; NVPTX-DISABLED1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP2]]) #[[ATTR4]] -; NVPTX-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__9, ptr @__omp_outlined__9_wrapper.ID, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) +; NVPTX-DISABLED1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__9, ptr @__omp_outlined__9_wrapper, ptr [[CAPTURED_VARS_ADDRS_CAST]], i64 0) ; NVPTX-DISABLED1-NEXT: call void @__kmpc_target_deinit() ; NVPTX-DISABLED1-NEXT: br label %[[COMMON_RET]] ; @@ -3186,7 +2646,6 @@ attributes #9 = { alwaysinline } ; AMDGPU-DISABLED1: attributes #[[ATTR8]] = { convergent } ; AMDGPU-DISABLED1: attributes #[[ATTR9:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } ; AMDGPU-DISABLED1: attributes #[[ATTR10:[0-9]+]] = { alwaysinline } -; AMDGPU-DISABLED1: attributes #[[ATTR11:[0-9]+]] = { convergent nounwind } ;. ; AMDGPU-DISABLED2: attributes #[[ATTR0]] = { alwaysinline convergent norecurse nounwind "kernel" } ; AMDGPU-DISABLED2: attributes #[[ATTR1]] = { norecurse } @@ -3211,7 +2670,6 @@ attributes #9 = { alwaysinline } ; NVPTX-DISABLED1: attributes #[[ATTR8]] = { convergent } ; NVPTX-DISABLED1: attributes #[[ATTR9:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } ; NVPTX-DISABLED1: attributes #[[ATTR10:[0-9]+]] = { alwaysinline } -; NVPTX-DISABLED1: attributes #[[ATTR11:[0-9]+]] = { convergent nounwind } ;. ; NVPTX-DISABLED2: attributes #[[ATTR0]] = { alwaysinline convergent norecurse nounwind "kernel" } ; NVPTX-DISABLED2: attributes #[[ATTR1]] = { norecurse } diff --git a/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll b/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll index 5a7d097142965..ac7383c4467b0 100644 --- a/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll +++ b/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll @@ -2,7 +2,7 @@ ; ; Verify we change it to SPMD mode but also avoid propagating the old mode (=generic) into the __kmpc_target_init function. ; -; CHECK: @__omp_offloading_20_11e3950_main_l12_kernel_environment = local_unnamed_addr addrspace(1) constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr addrspacecast (ptr addrspace(1) @1 to ptr), ptr null } +; CHECK: @__omp_offloading_20_11e3950_main_l12_kernel_environment = local_unnamed_addr addrspace(1) constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr addrspacecast (ptr addrspace(1) @1 to ptr), ptr null } ; CHECK-NOT: store i32 0, ptr addrspace(3) @IsSPMDMode ; CHECK-NOT: store i32 0, ptr addrspace(3) @IsSPMDMode ; CHECK: store i32 1, ptr addrspace(3) @IsSPMDMode diff --git a/llvm/test/Transforms/OpenMP/spmdization_guarding.ll b/llvm/test/Transforms/OpenMP/spmdization_guarding.ll index d057e5b233e87..d605a86614630 100644 --- a/llvm/test/Transforms/OpenMP/spmdization_guarding.ll +++ b/llvm/test/Transforms/OpenMP/spmdization_guarding.ll @@ -48,14 +48,13 @@ ; CHECK: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; CHECK: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 ; CHECK: @LocGlob = private unnamed_addr addrspace(5) global i32 43 -; CHECK: @__omp_offloading_2a_fbfa7a_sequential_loop_l6_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; CHECK: @__omp_offloading_2a_fbfa7a_sequential_loop_l6_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ; CHECK: @[[GLOB2:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, ptr @[[GLOB0]] }, align 8 ;. ; CHECK-DISABLED: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; CHECK-DISABLED: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 ; CHECK-DISABLED: @LocGlob = private unnamed_addr addrspace(5) global i32 43 -; CHECK-DISABLED: @__omp_offloading_2a_fbfa7a_sequential_loop_l6_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; CHECK-DISABLED: @__omp_outlined__1_wrapper.ID = private constant i8 undef +; CHECK-DISABLED: @__omp_offloading_2a_fbfa7a_sequential_loop_l6_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ;. define weak ptx_kernel void @__omp_offloading_2a_fbfa7a_sequential_loop_l6(ptr %dyn, ptr %x, i64 %N) #0 { ; CHECK-LABEL: define {{[^@]+}}@__omp_offloading_2a_fbfa7a_sequential_loop_l6 @@ -193,43 +192,10 @@ define weak ptx_kernel void @__omp_offloading_2a_fbfa7a_sequential_loop_l6(ptr % ; CHECK-DISABLED-SAME: (ptr [[DYN:%.*]], ptr [[X:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-DISABLED-NEXT: entry: ; CHECK-DISABLED-NEXT: [[HEAP2STACK_H2S:%.*]] = alloca i8, i64 8, align 8 -; CHECK-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; CHECK-DISABLED-NEXT: [[LOC:%.*]] = alloca ptr, align 8 ; CHECK-DISABLED-NEXT: [[AL32:%.*]] = alloca i32, align 4 ; CHECK-DISABLED-NEXT: [[N_ADDR_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[N]] to i32 ; CHECK-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr nonnull @__omp_offloading_2a_fbfa7a_sequential_loop_l6_kernel_environment, ptr [[DYN]]) #[[ATTR6:[0-9]+]] -; CHECK-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; CHECK-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; CHECK-DISABLED: is_worker_check: -; CHECK-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; CHECK-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; CHECK-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; CHECK-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; CHECK-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; CHECK-DISABLED: worker_state_machine.begin: -; CHECK-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; CHECK-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; CHECK-DISABLED-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; CHECK-DISABLED-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; CHECK-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; CHECK-DISABLED: worker_state_machine.finished: -; CHECK-DISABLED-NEXT: ret void -; CHECK-DISABLED: worker_state_machine.is_active.check: -; CHECK-DISABLED-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; CHECK-DISABLED: worker_state_machine.parallel_region.check: -; CHECK-DISABLED-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; CHECK-DISABLED: worker_state_machine.parallel_region.execute: -; CHECK-DISABLED-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP0]]) -; CHECK-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; CHECK-DISABLED: worker_state_machine.parallel_region.check1: -; CHECK-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; CHECK-DISABLED: worker_state_machine.parallel_region.end: -; CHECK-DISABLED-NEXT: call void @__kmpc_kernel_end_parallel() -; CHECK-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; CHECK-DISABLED: worker_state_machine.done.barrier: -; CHECK-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; CHECK-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; CHECK-DISABLED: thread.user_code.check: ; CHECK-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; CHECK-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; CHECK-DISABLED: user_code.entry: @@ -247,7 +213,7 @@ define weak ptx_kernel void @__omp_offloading_2a_fbfa7a_sequential_loop_l6(ptr % ; CHECK-DISABLED-NEXT: [[ARRAYIDX2_I:%.*]] = getelementptr inbounds i32, ptr [[X]], i64 [[IDXPROM_I]] ; CHECK-DISABLED-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[ARRAYIDX2_I]] to ptr addrspace(1) ; CHECK-DISABLED-NEXT: store i32 [[N_ADDR_SROA_0_0_EXTRACT_TRUNC]], ptr addrspace(1) [[TMP4]], align 4, !noalias [[META7]] -; CHECK-DISABLED-NEXT: call void @usei8ptr(ptr captures(none) [[HEAP2STACK_H2S]]) #[[ATTR9:[0-9]+]] +; CHECK-DISABLED-NEXT: call void @usei8ptr(ptr captures(none) [[HEAP2STACK_H2S]]) #[[ATTR8:[0-9]+]] ; CHECK-DISABLED-NEXT: br label [[FOR_COND_I:%.*]] ; CHECK-DISABLED: for.cond.i: ; CHECK-DISABLED-NEXT: [[I_0_I:%.*]] = phi i32 [ 2, [[USER_CODE_ENTRY]] ], [ [[INC_I:%.*]], [[FOR_BODY_I:%.*]] ] @@ -264,25 +230,25 @@ define weak ptx_kernel void @__omp_offloading_2a_fbfa7a_sequential_loop_l6(ptr % ; CHECK-DISABLED-NEXT: [[INC_I]] = add nuw nsw i32 [[I_0_I]], 1 ; CHECK-DISABLED-NEXT: br label [[FOR_COND_I]], !llvm.loop [[LOOP10:![0-9]+]] ; CHECK-DISABLED: __omp_outlined__.exit: -; CHECK-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr null, i32 0, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__1, ptr @__omp_outlined__1_wrapper.ID, ptr null, i64 0) -; CHECK-DISABLED-NEXT: [[CALL_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR10:[0-9]+]], !noalias [[META7]] +; CHECK-DISABLED-NEXT: call void @__kmpc_parallel_51(ptr null, i32 0, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__1, ptr @__omp_outlined__1_wrapper, ptr null, i64 0) +; CHECK-DISABLED-NEXT: [[CALL_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR9:[0-9]+]], !noalias [[META7]] ; CHECK-DISABLED-NEXT: [[IDXPROM6_I:%.*]] = sext i32 [[CALL_I]] to i64 ; CHECK-DISABLED-NEXT: [[ARRAYIDX7_I:%.*]] = getelementptr inbounds i32, ptr [[X]], i64 [[IDXPROM6_I]] ; CHECK-DISABLED-NEXT: [[TMP7:%.*]] = addrspacecast ptr [[ARRAYIDX7_I]] to ptr addrspace(1) ; CHECK-DISABLED-NEXT: store i32 [[CALL_I]], ptr addrspace(1) [[TMP7]], align 4, !noalias [[META7]] -; CHECK-DISABLED-NEXT: [[CALL8_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR10]], !noalias [[META7]] +; CHECK-DISABLED-NEXT: [[CALL8_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR9]], !noalias [[META7]] ; CHECK-DISABLED-NEXT: [[IDXPROM9_I:%.*]] = sext i32 [[CALL8_I]] to i64 ; CHECK-DISABLED-NEXT: [[ARRAYIDX10_I:%.*]] = getelementptr inbounds i32, ptr [[X]], i64 [[IDXPROM9_I]] ; CHECK-DISABLED-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[ARRAYIDX10_I]] to ptr addrspace(1) ; CHECK-DISABLED-NEXT: store i32 [[CALL8_I]], ptr addrspace(1) [[TMP8]], align 4, !noalias [[META7]] -; CHECK-DISABLED-NEXT: [[CALL11_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR10]], !noalias [[META7]] +; CHECK-DISABLED-NEXT: [[CALL11_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR9]], !noalias [[META7]] ; CHECK-DISABLED-NEXT: [[IDXPROM12_I:%.*]] = sext i32 [[CALL11_I]] to i64 ; CHECK-DISABLED-NEXT: [[ARRAYIDX13_I:%.*]] = getelementptr inbounds i32, ptr [[X]], i64 [[IDXPROM12_I]] ; CHECK-DISABLED-NEXT: [[TMP9:%.*]] = addrspacecast ptr [[ARRAYIDX13_I]] to ptr addrspace(1) ; CHECK-DISABLED-NEXT: store i32 [[CALL11_I]], ptr addrspace(1) [[TMP9]], align 4, !noalias [[META7]] -; CHECK-DISABLED-NEXT: [[CALL14_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR10]], !noalias [[META7]] -; CHECK-DISABLED-NEXT: [[CALL15_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR10]], !noalias [[META7]] -; CHECK-DISABLED-NEXT: [[CALL16_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR10]], !noalias [[META7]] +; CHECK-DISABLED-NEXT: [[CALL14_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR9]], !noalias [[META7]] +; CHECK-DISABLED-NEXT: [[CALL15_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR9]], !noalias [[META7]] +; CHECK-DISABLED-NEXT: [[CALL16_I:%.*]] = call i32 @no_openmp(ptr nonnull [[X]]) #[[ATTR9]], !noalias [[META7]] ; CHECK-DISABLED-NEXT: call void @__kmpc_target_deinit() #[[ATTR6]] ; CHECK-DISABLED-NEXT: ret void ; CHECK-DISABLED: worker.exit: @@ -455,9 +421,8 @@ attributes #5 = { convergent nounwind "llvm.assume"="omp_no_openmp,ompx_spmd_ame ; CHECK-DISABLED: attributes #[[ATTR5:[0-9]+]] = { nosync nounwind } ; CHECK-DISABLED: attributes #[[ATTR6]] = { nounwind } ; CHECK-DISABLED: attributes #[[ATTR7:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite) } -; CHECK-DISABLED: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind } -; CHECK-DISABLED: attributes #[[ATTR9]] = { nounwind willreturn "llvm.assume"="omp_no_openmp,ompx_spmd_amenable" } -; CHECK-DISABLED: attributes #[[ATTR10]] = { convergent nounwind "llvm.assume"="omp_no_openmp,ompx_spmd_amenable" } +; CHECK-DISABLED: attributes #[[ATTR8]] = { nounwind willreturn "llvm.assume"="omp_no_openmp,ompx_spmd_amenable" } +; CHECK-DISABLED: attributes #[[ATTR9]] = { convergent nounwind "llvm.assume"="omp_no_openmp,ompx_spmd_amenable" } ;. ; CHECK: [[META0:![0-9]+]] = !{i32 0, i32 42, i32 16513658, !"sequential_loop", i32 6, i32 0} ; CHECK: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} diff --git a/llvm/test/Transforms/OpenMP/spmdization_indirect.ll b/llvm/test/Transforms/OpenMP/spmdization_indirect.ll index dec6a68478f09..0bcf6d9f0d9f5 100644 --- a/llvm/test/Transforms/OpenMP/spmdization_indirect.ll +++ b/llvm/test/Transforms/OpenMP/spmdization_indirect.ll @@ -17,17 +17,17 @@ ;. ; AMDGPU: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; AMDGPU: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 -; AMDGPU: @spmd_callees_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @spmd_callees_metadata_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @spmd_and_non_spmd_callees_metadata_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; AMDGPU: @spmd_and_non_spmd_callee_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @spmd_callees_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @spmd_callees_metadata_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @spmd_and_non_spmd_callees_metadata_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; AMDGPU: @spmd_and_non_spmd_callee_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ;. ; NVPTX: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; NVPTX: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 -; NVPTX: @spmd_callees_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @spmd_callees_metadata_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @spmd_and_non_spmd_callees_metadata_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; NVPTX: @spmd_and_non_spmd_callee_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @spmd_callees_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @spmd_callees_metadata_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @spmd_and_non_spmd_callees_metadata_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; NVPTX: @spmd_and_non_spmd_callee_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ;. define weak ptx_kernel void @spmd_callees(i1 %c) #0 { ; AMDGPU-LABEL: define weak ptx_kernel void @spmd_callees( @@ -62,19 +62,7 @@ define internal void @spmd_callees__debug(i1 %c) { ; AMDGPU-NEXT: store i32 0, ptr addrspace(5) [[DOTZERO_ADDR]], align 4 ; AMDGPU-NEXT: store i32 [[TMP1]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4, !tbaa [[INT_TBAA12:![0-9]+]] ; AMDGPU-NEXT: [[FP:%.*]] = select i1 [[C]], ptr @__omp_outlined_spmd_amenable1, ptr @__omp_outlined_spmd_amenable2 -; AMDGPU-NEXT: [[TMP2:%.*]] = icmp eq ptr [[FP]], @__omp_outlined_spmd_amenable2 -; AMDGPU-NEXT: br i1 [[TMP2]], label %[[BB3:.*]], label %[[BB4:.*]] -; AMDGPU: [[BB3]]: -; AMDGPU-NEXT: call void @__omp_outlined_spmd_amenable2(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] -; AMDGPU-NEXT: br label %[[BB7:.*]] -; AMDGPU: [[BB4]]: -; AMDGPU-NEXT: br i1 true, label %[[BB5:.*]], label %[[BB6:.*]] -; AMDGPU: [[BB5]]: -; AMDGPU-NEXT: call void @__omp_outlined_spmd_amenable1(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] -; AMDGPU-NEXT: br label %[[BB7]] -; AMDGPU: [[BB6]]: -; AMDGPU-NEXT: unreachable -; AMDGPU: [[BB7]]: +; AMDGPU-NEXT: call void [[FP]](ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] ; AMDGPU-NEXT: call void @__kmpc_target_deinit() ; AMDGPU-NEXT: br label %[[COMMON_RET]] ; @@ -95,19 +83,7 @@ define internal void @spmd_callees__debug(i1 %c) { ; NVPTX-NEXT: store i32 0, ptr addrspace(5) [[DOTZERO_ADDR]], align 4 ; NVPTX-NEXT: store i32 [[TMP1]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4, !tbaa [[INT_TBAA12:![0-9]+]] ; NVPTX-NEXT: [[FP:%.*]] = select i1 [[C]], ptr @__omp_outlined_spmd_amenable1, ptr @__omp_outlined_spmd_amenable2 -; NVPTX-NEXT: [[TMP2:%.*]] = icmp eq ptr [[FP]], @__omp_outlined_spmd_amenable2 -; NVPTX-NEXT: br i1 [[TMP2]], label %[[BB3:.*]], label %[[BB4:.*]] -; NVPTX: [[BB3]]: -; NVPTX-NEXT: call void @__omp_outlined_spmd_amenable2(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] -; NVPTX-NEXT: br label %[[BB7:.*]] -; NVPTX: [[BB4]]: -; NVPTX-NEXT: br i1 true, label %[[BB5:.*]], label %[[BB6:.*]] -; NVPTX: [[BB5]]: -; NVPTX-NEXT: call void @__omp_outlined_spmd_amenable1(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] -; NVPTX-NEXT: br label %[[BB7]] -; NVPTX: [[BB6]]: -; NVPTX-NEXT: unreachable -; NVPTX: [[BB7]]: +; NVPTX-NEXT: call void [[FP]](ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] ; NVPTX-NEXT: call void @__kmpc_target_deinit() ; NVPTX-NEXT: br label %[[COMMON_RET]] ; @@ -386,41 +362,11 @@ define weak ptx_kernel void @spmd_and_non_spmd_callee(i1 %c) #0 { ; AMDGPU-LABEL: define weak ptx_kernel void @spmd_and_non_spmd_callee( ; AMDGPU-SAME: i1 [[C:%.*]]) #[[ATTR0]] { ; AMDGPU-NEXT: [[ENTRY:.*:]] -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @spmd_and_non_spmd_callee_kernel_environment, ptr null) -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; AMDGPU: [[IS_WORKER_CHECK]]: -; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_BEGIN]]: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_FINISHED]]: -; AMDGPU-NEXT: ret void -; AMDGPU: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; AMDGPU-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU: [[THREAD_USER_CODE_CHECK]]: ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; AMDGPU: [[COMMON_RET]]: @@ -430,59 +376,18 @@ define weak ptx_kernel void @spmd_and_non_spmd_callee(i1 %c) #0 { ; AMDGPU-NEXT: store i32 0, ptr addrspace(5) [[DOTZERO_ADDR]], align 4 ; AMDGPU-NEXT: store i32 [[TMP1]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4, !tbaa [[INT_TBAA12]] ; AMDGPU-NEXT: [[FP:%.*]] = select i1 [[C]], ptr @__omp_outlined_spmd_amenable3, ptr @__omp_outlined_not_spmd_amenable -; AMDGPU-NEXT: [[TMP2:%.*]] = icmp eq ptr [[FP]], @__omp_outlined_not_spmd_amenable -; AMDGPU-NEXT: br i1 [[TMP2]], label %[[BB3:.*]], label %[[BB4:.*]] -; AMDGPU: [[BB3]]: -; AMDGPU-NEXT: call void @__omp_outlined_not_spmd_amenable(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] -; AMDGPU-NEXT: br label %[[BB7:.*]] -; AMDGPU: [[BB4]]: -; AMDGPU-NEXT: br i1 true, label %[[BB5:.*]], label %[[BB6:.*]] -; AMDGPU: [[BB5]]: -; AMDGPU-NEXT: call void @__omp_outlined_spmd_amenable3(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] -; AMDGPU-NEXT: br label %[[BB7]] -; AMDGPU: [[BB6]]: -; AMDGPU-NEXT: unreachable -; AMDGPU: [[BB7]]: +; AMDGPU-NEXT: call void [[FP]](ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] ; AMDGPU-NEXT: call void @__kmpc_target_deinit() ; AMDGPU-NEXT: br label %[[COMMON_RET]] ; ; NVPTX-LABEL: define weak ptx_kernel void @spmd_and_non_spmd_callee( ; NVPTX-SAME: i1 [[C:%.*]]) #[[ATTR0]] { ; NVPTX-NEXT: [[ENTRY:.*:]] -; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @spmd_and_non_spmd_callee_kernel_environment, ptr null) -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; NVPTX: [[IS_WORKER_CHECK]]: -; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_BEGIN]]: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_FINISHED]]: -; NVPTX-NEXT: ret void -; NVPTX: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; NVPTX-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX: [[THREAD_USER_CODE_CHECK]]: ; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; NVPTX: [[COMMON_RET]]: @@ -492,19 +397,7 @@ define weak ptx_kernel void @spmd_and_non_spmd_callee(i1 %c) #0 { ; NVPTX-NEXT: store i32 0, ptr addrspace(5) [[DOTZERO_ADDR]], align 4 ; NVPTX-NEXT: store i32 [[TMP1]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4, !tbaa [[INT_TBAA12]] ; NVPTX-NEXT: [[FP:%.*]] = select i1 [[C]], ptr @__omp_outlined_spmd_amenable3, ptr @__omp_outlined_not_spmd_amenable -; NVPTX-NEXT: [[TMP2:%.*]] = icmp eq ptr [[FP]], @__omp_outlined_not_spmd_amenable -; NVPTX-NEXT: br i1 [[TMP2]], label %[[BB3:.*]], label %[[BB4:.*]] -; NVPTX: [[BB3]]: -; NVPTX-NEXT: call void @__omp_outlined_not_spmd_amenable(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] -; NVPTX-NEXT: br label %[[BB7:.*]] -; NVPTX: [[BB4]]: -; NVPTX-NEXT: br i1 true, label %[[BB5:.*]], label %[[BB6:.*]] -; NVPTX: [[BB5]]: -; NVPTX-NEXT: call void @__omp_outlined_spmd_amenable3(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] -; NVPTX-NEXT: br label %[[BB7]] -; NVPTX: [[BB6]]: -; NVPTX-NEXT: unreachable -; NVPTX: [[BB7]]: +; NVPTX-NEXT: call void [[FP]](ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) #[[ATTR10]] ; NVPTX-NEXT: call void @__kmpc_target_deinit() ; NVPTX-NEXT: br label %[[COMMON_RET]] ; @@ -692,7 +585,7 @@ define weak ptx_kernel void @spmd_callees_metadata(ptr %fp) #0 { ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR10]] ; AMDGPU-NEXT: store i32 0, ptr addrspace(5) [[DOTZERO_ADDR]], align 4 ; AMDGPU-NEXT: store i32 [[TMP1]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4, !tbaa [[INT_TBAA12]] -; AMDGPU-NEXT: call void @__omp_outlined_spmd_amenable_external(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) +; AMDGPU-NEXT: call void [[FP]](ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]), !callees [[META23:![0-9]+]] ; AMDGPU-NEXT: call void @__kmpc_target_deinit() ; AMDGPU-NEXT: br label %[[COMMON_RET]] ; @@ -712,7 +605,7 @@ define weak ptx_kernel void @spmd_callees_metadata(ptr %fp) #0 { ; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR10]] ; NVPTX-NEXT: store i32 0, ptr addrspace(5) [[DOTZERO_ADDR]], align 4 ; NVPTX-NEXT: store i32 [[TMP1]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4, !tbaa [[INT_TBAA12]] -; NVPTX-NEXT: call void @__omp_outlined_spmd_amenable_external(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) +; NVPTX-NEXT: call void [[FP]](ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]), !callees [[META23:![0-9]+]] ; NVPTX-NEXT: call void @__kmpc_target_deinit() ; NVPTX-NEXT: br label %[[COMMON_RET]] ; @@ -742,41 +635,11 @@ define weak ptx_kernel void @spmd_and_non_spmd_callees_metadata(ptr %fp) #0 { ; AMDGPU-LABEL: define weak ptx_kernel void @spmd_and_non_spmd_callees_metadata( ; AMDGPU-SAME: ptr [[FP:%.*]]) #[[ATTR0]] { ; AMDGPU-NEXT: [[ENTRY:.*:]] -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; AMDGPU-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @spmd_and_non_spmd_callees_metadata_kernel_environment, ptr null) -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; AMDGPU: [[IS_WORKER_CHECK]]: -; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_BEGIN]]: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast ptr addrspace(5) [[WORKER_WORK_FN_ADDR]] to ptr -; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR_GENERIC]]) -; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR_GENERIC]], align 8 -; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_FINISHED]]: -; AMDGPU-NEXT: ret void -; AMDGPU: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; AMDGPU-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; AMDGPU: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel() -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; AMDGPU: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; AMDGPU-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; AMDGPU: [[THREAD_USER_CODE_CHECK]]: ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; AMDGPU: [[COMMON_RET]]: @@ -785,59 +648,18 @@ define weak ptx_kernel void @spmd_and_non_spmd_callees_metadata(ptr %fp) #0 { ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR10]] ; AMDGPU-NEXT: store i32 0, ptr addrspace(5) [[DOTZERO_ADDR]], align 4 ; AMDGPU-NEXT: store i32 [[TMP1]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4, !tbaa [[INT_TBAA12]] -; AMDGPU-NEXT: [[TMP2:%.*]] = icmp eq ptr [[FP]], @__omp_outlined_spmd_amenable_external -; AMDGPU-NEXT: br i1 [[TMP2]], label %[[BB3:.*]], label %[[BB4:.*]] -; AMDGPU: [[BB3]]: -; AMDGPU-NEXT: call void @__omp_outlined_spmd_amenable_external(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) -; AMDGPU-NEXT: br label %[[BB7:.*]] -; AMDGPU: [[BB4]]: -; AMDGPU-NEXT: br i1 true, label %[[BB5:.*]], label %[[BB6:.*]] -; AMDGPU: [[BB5]]: -; AMDGPU-NEXT: call void @__omp_outlined_not_spmd_amenable_external(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) -; AMDGPU-NEXT: br label %[[BB7]] -; AMDGPU: [[BB6]]: -; AMDGPU-NEXT: unreachable -; AMDGPU: [[BB7]]: +; AMDGPU-NEXT: call void [[FP]](ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]), !callees [[META24:![0-9]+]] ; AMDGPU-NEXT: call void @__kmpc_target_deinit() ; AMDGPU-NEXT: br label %[[COMMON_RET]] ; ; NVPTX-LABEL: define weak ptx_kernel void @spmd_and_non_spmd_callees_metadata( ; NVPTX-SAME: ptr [[FP:%.*]]) #[[ATTR0]] { ; NVPTX-NEXT: [[ENTRY:.*:]] -; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTZERO_ADDR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca ptr, align 8, addrspace(5) ; NVPTX-NEXT: [[DOTTHREADID_TEMP__CAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @spmd_and_non_spmd_callees_metadata_kernel_environment, ptr null) -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label %[[IS_WORKER_CHECK:.*]], label %[[THREAD_USER_CODE_CHECK:.*]] -; NVPTX: [[IS_WORKER_CHECK]]: -; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label %[[WORKER_STATE_MACHINE_BEGIN:.*]], label %[[WORKER_STATE_MACHINE_FINISHED:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_BEGIN]]: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; NVPTX-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; NVPTX-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label %[[WORKER_STATE_MACHINE_FINISHED]], label %[[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_FINISHED]]: -; NVPTX-NEXT: ret void -; NVPTX: [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK]]: -; NVPTX-NEXT: br i1 [[WORKER_IS_ACTIVE]], label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:.*]], label %[[WORKER_STATE_MACHINE_DONE_BARRIER:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE]]: -; NVPTX-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_PARALLEL_REGION_END:.*]] -; NVPTX: [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]: -; NVPTX-NEXT: call void @__kmpc_kernel_end_parallel() -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_DONE_BARRIER]] -; NVPTX: [[WORKER_STATE_MACHINE_DONE_BARRIER]]: -; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; NVPTX-NEXT: br label %[[WORKER_STATE_MACHINE_BEGIN]] -; NVPTX: [[THREAD_USER_CODE_CHECK]]: ; NVPTX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; NVPTX-NEXT: br i1 [[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[COMMON_RET:.*]] ; NVPTX: [[COMMON_RET]]: @@ -846,19 +668,7 @@ define weak ptx_kernel void @spmd_and_non_spmd_callees_metadata(ptr %fp) #0 { ; NVPTX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR10]] ; NVPTX-NEXT: store i32 0, ptr addrspace(5) [[DOTZERO_ADDR]], align 4 ; NVPTX-NEXT: store i32 [[TMP1]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4, !tbaa [[INT_TBAA12]] -; NVPTX-NEXT: [[TMP2:%.*]] = icmp eq ptr [[FP]], @__omp_outlined_spmd_amenable_external -; NVPTX-NEXT: br i1 [[TMP2]], label %[[BB3:.*]], label %[[BB4:.*]] -; NVPTX: [[BB3]]: -; NVPTX-NEXT: call void @__omp_outlined_spmd_amenable_external(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) -; NVPTX-NEXT: br label %[[BB7:.*]] -; NVPTX: [[BB4]]: -; NVPTX-NEXT: br i1 true, label %[[BB5:.*]], label %[[BB6:.*]] -; NVPTX: [[BB5]]: -; NVPTX-NEXT: call void @__omp_outlined_not_spmd_amenable_external(ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]) -; NVPTX-NEXT: br label %[[BB7]] -; NVPTX: [[BB6]]: -; NVPTX-NEXT: unreachable -; NVPTX: [[BB7]]: +; NVPTX-NEXT: call void [[FP]](ptr [[DOTTHREADID_TEMP__CAST]], ptr [[DOTZERO_ADDR_CAST]]), !callees [[META24:![0-9]+]] ; NVPTX-NEXT: call void @__kmpc_target_deinit() ; NVPTX-NEXT: br label %[[COMMON_RET]] ; @@ -899,7 +709,7 @@ define void @__omp_outlined_spmd_amenable_external(ptr noalias %.global_tid., pt ; AMDGPU-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4, !tbaa [[INT_TBAA12]] ; AMDGPU-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr undef, i64 0) ; AMDGPU-NEXT: [[INC]] = add nsw i32 [[I_0]], 1 -; AMDGPU-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +; AMDGPU-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] ; ; NVPTX-LABEL: define void @__omp_outlined_spmd_amenable_external( ; NVPTX-SAME: ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) { @@ -916,7 +726,7 @@ define void @__omp_outlined_spmd_amenable_external(ptr noalias %.global_tid., pt ; NVPTX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4, !tbaa [[INT_TBAA12]] ; NVPTX-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr undef, i64 0) ; NVPTX-NEXT: [[INC]] = add nsw i32 [[I_0]], 1 -; NVPTX-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +; NVPTX-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] ; entry: br label %for.cond @@ -1123,7 +933,6 @@ attributes #8 = { nounwind } ; AMDGPU: attributes #[[ATTR8:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } ; AMDGPU: attributes #[[ATTR9:[0-9]+]] = { alwaysinline } ; AMDGPU: attributes #[[ATTR10]] = { nounwind } -; AMDGPU: attributes #[[ATTR11:[0-9]+]] = { convergent nounwind } ;. ; NVPTX: attributes #[[ATTR0]] = { alwaysinline convergent norecurse nounwind "kernel" } ; NVPTX: attributes #[[ATTR1]] = { norecurse } @@ -1136,7 +945,6 @@ attributes #8 = { nounwind } ; NVPTX: attributes #[[ATTR8:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } ; NVPTX: attributes #[[ATTR9:[0-9]+]] = { alwaysinline } ; NVPTX: attributes #[[ATTR10]] = { nounwind } -; NVPTX: attributes #[[ATTR11:[0-9]+]] = { convergent nounwind } ;. ; AMDGPU: [[META0:![0-9]+]] = !{i32 0, i32 64770, i32 541341486, !"", i32 74, i32 5} ; AMDGPU: [[META1:![0-9]+]] = !{i32 0, i32 64770, i32 541341486, !"sequential_loop_to_stack_var", i32 20, i32 1} @@ -1161,7 +969,9 @@ attributes #8 = { nounwind } ; AMDGPU: [[ANYPTR_TBAA20]] = !{[[META21:![0-9]+]], [[META21]], i64 0} ; AMDGPU: [[META21]] = !{!"any pointer", [[META14]], i64 0} ; AMDGPU: [[LOOP22]] = distinct !{[[LOOP22]], [[META17]], [[META18]]} -; AMDGPU: [[LOOP23]] = distinct !{[[LOOP23]], [[META17]], [[META18]]} +; AMDGPU: [[META23]] = !{ptr @__omp_outlined_spmd_amenable_external, ptr @__omp_outlined_not_spmd_amenable} +; AMDGPU: [[META24]] = !{ptr @__omp_outlined_spmd_amenable_external, ptr @__omp_outlined_not_spmd_amenable_external} +; AMDGPU: [[LOOP25]] = distinct !{[[LOOP25]], [[META17]], [[META18]]} ;. ; NVPTX: [[META0:![0-9]+]] = !{i32 0, i32 64770, i32 541341486, !"", i32 74, i32 5} ; NVPTX: [[META1:![0-9]+]] = !{i32 0, i32 64770, i32 541341486, !"sequential_loop_to_stack_var", i32 20, i32 1} @@ -1186,5 +996,7 @@ attributes #8 = { nounwind } ; NVPTX: [[ANYPTR_TBAA20]] = !{[[META21:![0-9]+]], [[META21]], i64 0} ; NVPTX: [[META21]] = !{!"any pointer", [[META14]], i64 0} ; NVPTX: [[LOOP22]] = distinct !{[[LOOP22]], [[META17]], [[META18]]} -; NVPTX: [[LOOP23]] = distinct !{[[LOOP23]], [[META17]], [[META18]]} +; NVPTX: [[META23]] = !{ptr @__omp_outlined_spmd_amenable_external, ptr @__omp_outlined_not_spmd_amenable} +; NVPTX: [[META24]] = !{ptr @__omp_outlined_spmd_amenable_external, ptr @__omp_outlined_not_spmd_amenable_external} +; NVPTX: [[LOOP25]] = distinct !{[[LOOP25]], [[META17]], [[META18]]} ;. diff --git a/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll b/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll index d3e8e98b6f510..ccf0d5b8dd97c 100644 --- a/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll +++ b/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll @@ -12,7 +12,7 @@ target triple = "amdgcn-amd-amdhsa" ;. ; AMDGPU: @IsSPMDMode = internal addrspace(3) global i32 undef -; AMDGPU: @__omp_offloading_10302_b20a40e_main_l4_kernel_environment = addrspace(1) constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy.8 { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr addrspacecast (ptr addrspace(1) null to ptr), ptr addrspacecast (ptr addrspace(1) null to ptr) } +; AMDGPU: @__omp_offloading_10302_b20a40e_main_l4_kernel_environment = addrspace(1) constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy.8 { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr addrspacecast (ptr addrspace(1) null to ptr), ptr addrspacecast (ptr addrspace(1) null to ptr) } ;. define i32 @fputs() { ; AMDGPU-LABEL: define {{[^@]+}}@fputs diff --git a/llvm/test/Transforms/OpenMP/spmdization_no_guarding_two_reaching_kernels.ll b/llvm/test/Transforms/OpenMP/spmdization_no_guarding_two_reaching_kernels.ll index 17e68030d1813..63405828c1ce4 100644 --- a/llvm/test/Transforms/OpenMP/spmdization_no_guarding_two_reaching_kernels.ll +++ b/llvm/test/Transforms/OpenMP/spmdization_no_guarding_two_reaching_kernels.ll @@ -45,16 +45,15 @@ ; CHECK: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 ; CHECK: @[[GLOB2:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8 ; CHECK: @G = external addrspace(5) global i32, align 4 -; CHECK: @__omp_offloading_2b_10393b5_spmd_l12_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; CHECK: @__omp_offloading_2b_10393b5_generic_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; CHECK: @__omp_offloading_2b_10393b5_spmd_l12_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; CHECK: @__omp_offloading_2b_10393b5_generic_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ;. ; CHECK-DISABLE-SPMDIZATION: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c" ; CHECK-DISABLE-SPMDIZATION: @[[GLOB1:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8 ; CHECK-DISABLE-SPMDIZATION: @[[GLOB2:[0-9]+]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8 ; CHECK-DISABLE-SPMDIZATION: @G = external addrspace(5) global i32, align 4 -; CHECK-DISABLE-SPMDIZATION: @__omp_offloading_2b_10393b5_spmd_l12_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; CHECK-DISABLE-SPMDIZATION: @__omp_offloading_2b_10393b5_generic_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } -; CHECK-DISABLE-SPMDIZATION: @__omp_outlined___wrapper.ID = private constant i8 undef +; CHECK-DISABLE-SPMDIZATION: @__omp_offloading_2b_10393b5_spmd_l12_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } +; CHECK-DISABLE-SPMDIZATION: @__omp_offloading_2b_10393b5_generic_l20_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr @[[GLOB1]], ptr null } ;. define weak ptx_kernel void @__omp_offloading_2b_10393b5_spmd_l12(ptr %dyn) #0 { ; CHECK-LABEL: define {{[^@]+}}@__omp_offloading_2b_10393b5_spmd_l12 @@ -73,40 +72,7 @@ define weak ptx_kernel void @__omp_offloading_2b_10393b5_spmd_l12(ptr %dyn) #0 { ; CHECK-DISABLE-SPMDIZATION-LABEL: define {{[^@]+}}@__omp_offloading_2b_10393b5_spmd_l12 ; CHECK-DISABLE-SPMDIZATION-SAME: (ptr [[DYN:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-DISABLE-SPMDIZATION-NEXT: entry: -; CHECK-DISABLE-SPMDIZATION-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; CHECK-DISABLE-SPMDIZATION-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_2b_10393b5_spmd_l12_kernel_environment, ptr [[DYN]]) -; CHECK-DISABLE-SPMDIZATION-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; CHECK-DISABLE-SPMDIZATION: is_worker_check: -; CHECK-DISABLE-SPMDIZATION-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; CHECK-DISABLE-SPMDIZATION-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; CHECK-DISABLE-SPMDIZATION-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; CHECK-DISABLE-SPMDIZATION-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.begin: -; CHECK-DISABLE-SPMDIZATION-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; CHECK-DISABLE-SPMDIZATION-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; CHECK-DISABLE-SPMDIZATION-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; CHECK-DISABLE-SPMDIZATION-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.finished: -; CHECK-DISABLE-SPMDIZATION-NEXT: ret void -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.is_active.check: -; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.parallel_region.check: -; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK1:%.*]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.parallel_region.execute: -; CHECK-DISABLE-SPMDIZATION-NEXT: call void @__omp_outlined___wrapper(i16 0, i32 [[TMP0]]) -; CHECK-DISABLE-SPMDIZATION-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.parallel_region.check1: -; CHECK-DISABLE-SPMDIZATION-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.parallel_region.end: -; CHECK-DISABLE-SPMDIZATION-NEXT: call void @__kmpc_kernel_end_parallel() -; CHECK-DISABLE-SPMDIZATION-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.done.barrier: -; CHECK-DISABLE-SPMDIZATION-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; CHECK-DISABLE-SPMDIZATION-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; CHECK-DISABLE-SPMDIZATION: thread.user_code.check: ; CHECK-DISABLE-SPMDIZATION-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; CHECK-DISABLE-SPMDIZATION: user_code.entry: @@ -150,36 +116,7 @@ define weak ptx_kernel void @__omp_offloading_2b_10393b5_generic_l20(ptr %dyn) # ; CHECK-LABEL: define {{[^@]+}}@__omp_offloading_2b_10393b5_generic_l20 ; CHECK-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; CHECK-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_2b_10393b5_generic_l20_kernel_environment, ptr [[DYN]]) -; CHECK-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; CHECK-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; CHECK: is_worker_check: -; CHECK-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; CHECK-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; CHECK-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; CHECK-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; CHECK-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; CHECK: worker_state_machine.begin: -; CHECK-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; CHECK-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; CHECK-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; CHECK-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; CHECK-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; CHECK: worker_state_machine.finished: -; CHECK-NEXT: ret void -; CHECK: worker_state_machine.is_active.check: -; CHECK-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; CHECK: worker_state_machine.parallel_region.fallback.execute: -; CHECK-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; CHECK-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; CHECK: worker_state_machine.parallel_region.end: -; CHECK-NEXT: call void @__kmpc_kernel_end_parallel() -; CHECK-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; CHECK: worker_state_machine.done.barrier: -; CHECK-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; CHECK-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; CHECK: thread.user_code.check: ; CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; CHECK: user_code.entry: @@ -192,36 +129,7 @@ define weak ptx_kernel void @__omp_offloading_2b_10393b5_generic_l20(ptr %dyn) # ; CHECK-DISABLE-SPMDIZATION-LABEL: define {{[^@]+}}@__omp_offloading_2b_10393b5_generic_l20 ; CHECK-DISABLE-SPMDIZATION-SAME: (ptr [[DYN:%.*]]) #[[ATTR0]] { ; CHECK-DISABLE-SPMDIZATION-NEXT: entry: -; CHECK-DISABLE-SPMDIZATION-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca ptr, align 8 ; CHECK-DISABLE-SPMDIZATION-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_2b_10393b5_generic_l20_kernel_environment, ptr [[DYN]]) -; CHECK-DISABLE-SPMDIZATION-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] -; CHECK-DISABLE-SPMDIZATION: is_worker_check: -; CHECK-DISABLE-SPMDIZATION-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -; CHECK-DISABLE-SPMDIZATION-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() -; CHECK-DISABLE-SPMDIZATION-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] -; CHECK-DISABLE-SPMDIZATION-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.begin: -; CHECK-DISABLE-SPMDIZATION-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; CHECK-DISABLE-SPMDIZATION-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(ptr [[WORKER_WORK_FN_ADDR]]) -; CHECK-DISABLE-SPMDIZATION-NEXT: [[WORKER_WORK_FN:%.*]] = load ptr, ptr [[WORKER_WORK_FN_ADDR]], align 8 -; CHECK-DISABLE-SPMDIZATION-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq ptr [[WORKER_WORK_FN]], null -; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.finished: -; CHECK-DISABLE-SPMDIZATION-NEXT: ret void -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.is_active.check: -; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK_EXECUTE:%.*]], label [[WORKER_STATE_MACHINE_DONE_BARRIER:%.*]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.parallel_region.fallback.execute: -; CHECK-DISABLE-SPMDIZATION-NEXT: call void [[WORKER_WORK_FN]](i16 0, i32 [[TMP0]]) -; CHECK-DISABLE-SPMDIZATION-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.parallel_region.end: -; CHECK-DISABLE-SPMDIZATION-NEXT: call void @__kmpc_kernel_end_parallel() -; CHECK-DISABLE-SPMDIZATION-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]] -; CHECK-DISABLE-SPMDIZATION: worker_state_machine.done.barrier: -; CHECK-DISABLE-SPMDIZATION-NEXT: call void @__kmpc_barrier_simple_generic(ptr @[[GLOB1]], i32 [[TMP0]]) -; CHECK-DISABLE-SPMDIZATION-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]] -; CHECK-DISABLE-SPMDIZATION: thread.user_code.check: ; CHECK-DISABLE-SPMDIZATION-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1 ; CHECK-DISABLE-SPMDIZATION-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] ; CHECK-DISABLE-SPMDIZATION: user_code.entry: @@ -262,7 +170,7 @@ define internal void @spmd_helper() #1 { ; CHECK-DISABLE-SPMDIZATION-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8 ; CHECK-DISABLE-SPMDIZATION-NEXT: call void @leaf() #[[ATTR8:[0-9]+]] ; CHECK-DISABLE-SPMDIZATION-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR4:[0-9]+]] -; CHECK-DISABLE-SPMDIZATION-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__, ptr @__omp_outlined___wrapper.ID, ptr [[CAPTURED_VARS_ADDRS]], i64 0) +; CHECK-DISABLE-SPMDIZATION-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__, ptr @__omp_outlined___wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0) ; CHECK-DISABLE-SPMDIZATION-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/OpenMP/spmdization_remarks.ll b/llvm/test/Transforms/OpenMP/spmdization_remarks.ll index f30e827694a34..4f9e2a007be3e 100644 --- a/llvm/test/Transforms/OpenMP/spmdization_remarks.ll +++ b/llvm/test/Transforms/OpenMP/spmdization_remarks.ll @@ -1,3 +1,5 @@ +; XFAIL: * +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -passes=openmp-opt -pass-remarks=openmp-opt -pass-remarks-missed=openmp-opt -pass-remarks-analysis=openmp-opt -disable-output < %s 2>&1 | FileCheck %s target triple = "nvptx64" diff --git a/llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll b/llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll index 5127b7d37f0b4..3a8b69ca9fb99 100644 --- a/llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll +++ b/llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll @@ -68,7 +68,7 @@ define void @arm_mult_q15(ptr %pSrcA, ptr %pSrcB, ptr noalias %pDst, i32 %blockS ; CHECK-NEXT: [[CONV2:%.*]] = sext i16 [[TMP11]] to i32 ; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[CONV2]], [[CONV]] ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[MUL]], 15 -; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = tail call i32 @llvm.smin.i32(i32 [[SHR]], i32 32767) +; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = tail call range(i32 -32767, 32768) i32 @llvm.smin.i32(i32 range(i32 -32767, 32769) [[SHR]], i32 32767) ; CHECK-NEXT: [[CONV3:%.*]] = trunc nsw i32 [[SPEC_SELECT_I]] to i16 ; CHECK-NEXT: [[INCDEC_PTR4]] = getelementptr inbounds nuw i8, ptr [[PDST_ADDR_04]], i32 2 ; CHECK-NEXT: store i16 [[CONV3]], ptr [[PDST_ADDR_04]], align 2 diff --git a/llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll b/llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll index 92ea2c608fe53..a13a43ce9e6ab 100644 --- a/llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll +++ b/llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll @@ -12,14 +12,12 @@ define void @pluto() #0 { ; CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 48 to ptr), align 16 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i64 [[TMP1]], 0 -; CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( zeroinitializer, zeroinitializer, i64 0) -; CHECK-NEXT: br label %[[SNORK_EXIT:.*]] -; CHECK: [[SNORK_EXIT]]: -; CHECK-NEXT: [[DOT0:%.*]] = phi [ undef, [[TMP0:%.*]] ], [ [[SPEC_SELECT:%.*]], %[[SNORK_EXIT]] ] -; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[TMP2]], [[TMP3]], [[DOT0]] -; CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[SPEC_SELECT]], i64 0) +; CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( undef, i64 0) +; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], zeroinitializer, [[TMP3]] +; CHECK-NEXT: br label %[[BB5:.*]] +; CHECK: [[BB5]]: ; CHECK-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv4f32(i32 0, zeroinitializer, zeroinitializer, zeroinitializer, [[TMP4]]) -; CHECK-NEXT: br label %[[SNORK_EXIT]] +; CHECK-NEXT: br label %[[BB5]] ; br label %1 diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll index a8d1c94d59be3..c36e156473f97 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll @@ -367,11 +367,116 @@ bb: ret <4 x i16> %ins.3 } +define <4 x i8> @uadd_sat_v4i8(<4 x i8> %arg0, <4 x i8> %arg1) { +; GFX7-LABEL: @uadd_sat_v4i8( +; GFX7-NEXT: bb: +; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <4 x i8> [[ARG0:%.*]], i64 0 +; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <4 x i8> [[ARG0]], i64 1 +; GFX7-NEXT: [[ARG0_2:%.*]] = extractelement <4 x i8> [[ARG0]], i64 2 +; GFX7-NEXT: [[ARG0_3:%.*]] = extractelement <4 x i8> [[ARG0]], i64 3 +; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <4 x i8> [[ARG1:%.*]], i64 0 +; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <4 x i8> [[ARG1]], i64 1 +; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <4 x i8> [[ARG1]], i64 2 +; GFX7-NEXT: [[ARG1_3:%.*]] = extractelement <4 x i8> [[ARG1]], i64 3 +; GFX7-NEXT: [[ADD_0:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG0_0]], i8 [[ARG1_0]]) +; GFX7-NEXT: [[ADD_1:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG0_1]], i8 [[ARG1_1]]) +; GFX7-NEXT: [[ADD_2:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG0_2]], i8 [[ARG1_2]]) +; GFX7-NEXT: [[ADD_3:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG0_3]], i8 [[ARG1_3]]) +; GFX7-NEXT: [[INS_0:%.*]] = insertelement <4 x i8> poison, i8 [[ADD_0]], i64 0 +; GFX7-NEXT: [[INS_1:%.*]] = insertelement <4 x i8> [[INS_0]], i8 [[ADD_1]], i64 1 +; GFX7-NEXT: [[INS_2:%.*]] = insertelement <4 x i8> [[INS_1]], i8 [[ADD_2]], i64 2 +; GFX7-NEXT: [[INS_3:%.*]] = insertelement <4 x i8> [[INS_2]], i8 [[ADD_3]], i64 3 +; GFX7-NEXT: ret <4 x i8> [[INS_3]] +; +; GFX8-LABEL: @uadd_sat_v4i8( +; GFX8-NEXT: bb: +; GFX8-NEXT: [[TMP0:%.*]] = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> [[ARG0:%.*]], <4 x i8> [[ARG1:%.*]]) +; GFX8-NEXT: ret <4 x i8> [[TMP0]] +; +; GFX9-LABEL: @uadd_sat_v4i8( +; GFX9-NEXT: bb: +; GFX9-NEXT: [[TMP0:%.*]] = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> [[ARG0:%.*]], <4 x i8> [[ARG1:%.*]]) +; GFX9-NEXT: ret <4 x i8> [[TMP0]] +; +bb: + %arg0.0 = extractelement <4 x i8> %arg0, i64 0 + %arg0.1 = extractelement <4 x i8> %arg0, i64 1 + %arg0.2 = extractelement <4 x i8> %arg0, i64 2 + %arg0.3 = extractelement <4 x i8> %arg0, i64 3 + %arg1.0 = extractelement <4 x i8> %arg1, i64 0 + %arg1.1 = extractelement <4 x i8> %arg1, i64 1 + %arg1.2 = extractelement <4 x i8> %arg1, i64 2 + %arg1.3 = extractelement <4 x i8> %arg1, i64 3 + %add.0 = call i8 @llvm.uadd.sat.i8(i8 %arg0.0, i8 %arg1.0) + %add.1 = call i8 @llvm.uadd.sat.i8(i8 %arg0.1, i8 %arg1.1) + %add.2 = call i8 @llvm.uadd.sat.i8(i8 %arg0.2, i8 %arg1.2) + %add.3 = call i8 @llvm.uadd.sat.i8(i8 %arg0.3, i8 %arg1.3) + %ins.0 = insertelement <4 x i8> poison, i8 %add.0, i64 0 + %ins.1 = insertelement <4 x i8> %ins.0, i8 %add.1, i64 1 + %ins.2 = insertelement <4 x i8> %ins.1, i8 %add.2, i64 2 + %ins.3 = insertelement <4 x i8> %ins.2, i8 %add.3, i64 3 + ret <4 x i8> %ins.3 +} + +define <4 x i8> @usub_sat_v4i8(<4 x i8> %arg0, <4 x i8> %arg1) { +; GFX7-LABEL: @usub_sat_v4i8( +; GFX7-NEXT: bb: +; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <4 x i8> [[ARG0:%.*]], i64 0 +; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <4 x i8> [[ARG0]], i64 1 +; GFX7-NEXT: [[ARG0_2:%.*]] = extractelement <4 x i8> [[ARG0]], i64 2 +; GFX7-NEXT: [[ARG0_3:%.*]] = extractelement <4 x i8> [[ARG0]], i64 3 +; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <4 x i8> [[ARG1:%.*]], i64 0 +; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <4 x i8> [[ARG1]], i64 1 +; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <4 x i8> [[ARG1]], i64 2 +; GFX7-NEXT: [[ARG1_3:%.*]] = extractelement <4 x i8> [[ARG1]], i64 3 +; GFX7-NEXT: [[ADD_0:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[ARG0_0]], i8 [[ARG1_0]]) +; GFX7-NEXT: [[ADD_1:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[ARG0_1]], i8 [[ARG1_1]]) +; GFX7-NEXT: [[ADD_2:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[ARG0_2]], i8 [[ARG1_2]]) +; GFX7-NEXT: [[ADD_3:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[ARG0_3]], i8 [[ARG1_3]]) +; GFX7-NEXT: [[INS_0:%.*]] = insertelement <4 x i8> poison, i8 [[ADD_0]], i64 0 +; GFX7-NEXT: [[INS_1:%.*]] = insertelement <4 x i8> [[INS_0]], i8 [[ADD_1]], i64 1 +; GFX7-NEXT: [[INS_2:%.*]] = insertelement <4 x i8> [[INS_1]], i8 [[ADD_2]], i64 2 +; GFX7-NEXT: [[INS_3:%.*]] = insertelement <4 x i8> [[INS_2]], i8 [[ADD_3]], i64 3 +; GFX7-NEXT: ret <4 x i8> [[INS_3]] +; +; GFX8-LABEL: @usub_sat_v4i8( +; GFX8-NEXT: bb: +; GFX8-NEXT: [[TMP0:%.*]] = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> [[ARG0:%.*]], <4 x i8> [[ARG1:%.*]]) +; GFX8-NEXT: ret <4 x i8> [[TMP0]] +; +; GFX9-LABEL: @usub_sat_v4i8( +; GFX9-NEXT: bb: +; GFX9-NEXT: [[TMP0:%.*]] = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> [[ARG0:%.*]], <4 x i8> [[ARG1:%.*]]) +; GFX9-NEXT: ret <4 x i8> [[TMP0]] +; +bb: + %arg0.0 = extractelement <4 x i8> %arg0, i64 0 + %arg0.1 = extractelement <4 x i8> %arg0, i64 1 + %arg0.2 = extractelement <4 x i8> %arg0, i64 2 + %arg0.3 = extractelement <4 x i8> %arg0, i64 3 + %arg1.0 = extractelement <4 x i8> %arg1, i64 0 + %arg1.1 = extractelement <4 x i8> %arg1, i64 1 + %arg1.2 = extractelement <4 x i8> %arg1, i64 2 + %arg1.3 = extractelement <4 x i8> %arg1, i64 3 + %add.0 = call i8 @llvm.usub.sat.i8(i8 %arg0.0, i8 %arg1.0) + %add.1 = call i8 @llvm.usub.sat.i8(i8 %arg0.1, i8 %arg1.1) + %add.2 = call i8 @llvm.usub.sat.i8(i8 %arg0.2, i8 %arg1.2) + %add.3 = call i8 @llvm.usub.sat.i8(i8 %arg0.3, i8 %arg1.3) + %ins.0 = insertelement <4 x i8> poison, i8 %add.0, i64 0 + %ins.1 = insertelement <4 x i8> %ins.0, i8 %add.1, i64 1 + %ins.2 = insertelement <4 x i8> %ins.1, i8 %add.2, i64 2 + %ins.3 = insertelement <4 x i8> %ins.2, i8 %add.3, i64 3 + ret <4 x i8> %ins.3 +} + declare i16 @llvm.uadd.sat.i16(i16, i16) #0 declare i16 @llvm.usub.sat.i16(i16, i16) #0 declare i16 @llvm.sadd.sat.i16(i16, i16) #0 declare i16 @llvm.ssub.sat.i16(i16, i16) #0 +declare i8 @llvm.uadd.sat.i8(i8, i8) #0 +declare i8 @llvm.usub.sat.i8(i8, i8) #0 + declare i32 @llvm.uadd.sat.i32(i32, i32) #0 declare i32 @llvm.usub.sat.i32(i32, i32) #0 declare i32 @llvm.sadd.sat.i32(i32, i32) #0 diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll index b09022e8289a1..798cc1543c023 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll @@ -367,11 +367,117 @@ bb: ret <4 x i16> %ins.3 } +define <4 x i8> @uadd_sat_v4i8(<4 x i8> %arg0, <4 x i8> %arg1, ptr addrspace(1) %dst) { +; GFX7-LABEL: @uadd_sat_v4i8( +; GFX7-NEXT: bb: +; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <4 x i8> [[ARG0:%.*]], i64 0 +; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <4 x i8> [[ARG0]], i64 1 +; GFX7-NEXT: [[ARG0_2:%.*]] = extractelement <4 x i8> [[ARG0]], i64 2 +; GFX7-NEXT: [[ARG0_3:%.*]] = extractelement <4 x i8> [[ARG0]], i64 3 +; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <4 x i8> [[ARG1:%.*]], i64 0 +; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <4 x i8> [[ARG1]], i64 1 +; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <4 x i8> [[ARG1]], i64 2 +; GFX7-NEXT: [[ARG1_3:%.*]] = extractelement <4 x i8> [[ARG1]], i64 3 +; GFX7-NEXT: [[ADD_0:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG0_0]], i8 [[ARG1_0]]) +; GFX7-NEXT: [[ADD_1:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG0_1]], i8 [[ARG1_1]]) +; GFX7-NEXT: [[ADD_2:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG0_2]], i8 [[ARG1_2]]) +; GFX7-NEXT: [[ADD_3:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG0_3]], i8 [[ARG1_3]]) +; GFX7-NEXT: [[INS_0:%.*]] = insertelement <4 x i8> undef, i8 [[ADD_0]], i64 0 +; GFX7-NEXT: [[INS_1:%.*]] = insertelement <4 x i8> [[INS_0]], i8 [[ADD_1]], i64 1 +; GFX7-NEXT: [[INS_2:%.*]] = insertelement <4 x i8> [[INS_1]], i8 [[ADD_2]], i64 2 +; GFX7-NEXT: [[INS_3:%.*]] = insertelement <4 x i8> [[INS_2]], i8 [[ADD_3]], i64 3 +; GFX7-NEXT: ret <4 x i8> [[INS_3]] +; +; GFX8-LABEL: @uadd_sat_v4i8( +; GFX8-NEXT: bb: +; GFX8-NEXT: [[TMP0:%.*]] = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> [[ARG0:%.*]], <4 x i8> [[ARG1:%.*]]) +; GFX8-NEXT: ret <4 x i8> [[TMP0]] +; +; GFX9-LABEL: @uadd_sat_v4i8( +; GFX9-NEXT: bb: +; GFX9-NEXT: [[TMP0:%.*]] = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> [[ARG0:%.*]], <4 x i8> [[ARG1:%.*]]) +; GFX9-NEXT: ret <4 x i8> [[TMP0]] +; +bb: + %arg0.0 = extractelement <4 x i8> %arg0, i64 0 + %arg0.1 = extractelement <4 x i8> %arg0, i64 1 + %arg0.2 = extractelement <4 x i8> %arg0, i64 2 + %arg0.3 = extractelement <4 x i8> %arg0, i64 3 + %arg1.0 = extractelement <4 x i8> %arg1, i64 0 + %arg1.1 = extractelement <4 x i8> %arg1, i64 1 + %arg1.2 = extractelement <4 x i8> %arg1, i64 2 + %arg1.3 = extractelement <4 x i8> %arg1, i64 3 + %add.0 = call i8 @llvm.uadd.sat.i8(i8 %arg0.0, i8 %arg1.0) + %add.1 = call i8 @llvm.uadd.sat.i8(i8 %arg0.1, i8 %arg1.1) + %add.2 = call i8 @llvm.uadd.sat.i8(i8 %arg0.2, i8 %arg1.2) + %add.3 = call i8 @llvm.uadd.sat.i8(i8 %arg0.3, i8 %arg1.3) + %ins.0 = insertelement <4 x i8> undef, i8 %add.0, i64 0 + %ins.1 = insertelement <4 x i8> %ins.0, i8 %add.1, i64 1 + %ins.2 = insertelement <4 x i8> %ins.1, i8 %add.2, i64 2 + %ins.3 = insertelement <4 x i8> %ins.2, i8 %add.3, i64 3 + ret <4 x i8> %ins.3 +} +define <4 x i8> @usub_sat_v4i8(<4 x i8> %arg0, <4 x i8> %arg1) { +; GFX7-LABEL: @usub_sat_v4i8( +; GFX7-NEXT: bb: +; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <4 x i8> [[ARG0:%.*]], i64 0 +; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <4 x i8> [[ARG0]], i64 1 +; GFX7-NEXT: [[ARG0_2:%.*]] = extractelement <4 x i8> [[ARG0]], i64 2 +; GFX7-NEXT: [[ARG0_3:%.*]] = extractelement <4 x i8> [[ARG0]], i64 3 +; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <4 x i8> [[ARG1:%.*]], i64 0 +; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <4 x i8> [[ARG1]], i64 1 +; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <4 x i8> [[ARG1]], i64 2 +; GFX7-NEXT: [[ARG1_3:%.*]] = extractelement <4 x i8> [[ARG1]], i64 3 +; GFX7-NEXT: [[ADD_0:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[ARG0_0]], i8 [[ARG1_0]]) +; GFX7-NEXT: [[ADD_1:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[ARG0_1]], i8 [[ARG1_1]]) +; GFX7-NEXT: [[ADD_2:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[ARG0_2]], i8 [[ARG1_2]]) +; GFX7-NEXT: [[ADD_3:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[ARG0_3]], i8 [[ARG1_3]]) +; GFX7-NEXT: [[INS_0:%.*]] = insertelement <4 x i8> undef, i8 [[ADD_0]], i64 0 +; GFX7-NEXT: [[INS_1:%.*]] = insertelement <4 x i8> [[INS_0]], i8 [[ADD_1]], i64 1 +; GFX7-NEXT: [[INS_2:%.*]] = insertelement <4 x i8> [[INS_1]], i8 [[ADD_2]], i64 2 +; GFX7-NEXT: [[INS_3:%.*]] = insertelement <4 x i8> [[INS_2]], i8 [[ADD_3]], i64 3 +; GFX7-NEXT: ret <4 x i8> [[INS_3]] +; +; GFX8-LABEL: @usub_sat_v4i8( +; GFX8-NEXT: bb: +; GFX8-NEXT: [[TMP0:%.*]] = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> [[ARG0:%.*]], <4 x i8> [[ARG1:%.*]]) +; GFX8-NEXT: ret <4 x i8> [[TMP0]] +; +; GFX9-LABEL: @usub_sat_v4i8( +; GFX9-NEXT: bb: +; GFX9-NEXT: [[TMP0:%.*]] = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> [[ARG0:%.*]], <4 x i8> [[ARG1:%.*]]) +; GFX9-NEXT: ret <4 x i8> [[TMP0]] +; +bb: + %arg0.0 = extractelement <4 x i8> %arg0, i64 0 + %arg0.1 = extractelement <4 x i8> %arg0, i64 1 + %arg0.2 = extractelement <4 x i8> %arg0, i64 2 + %arg0.3 = extractelement <4 x i8> %arg0, i64 3 + %arg1.0 = extractelement <4 x i8> %arg1, i64 0 + %arg1.1 = extractelement <4 x i8> %arg1, i64 1 + %arg1.2 = extractelement <4 x i8> %arg1, i64 2 + %arg1.3 = extractelement <4 x i8> %arg1, i64 3 + %add.0 = call i8 @llvm.usub.sat.i8(i8 %arg0.0, i8 %arg1.0) + %add.1 = call i8 @llvm.usub.sat.i8(i8 %arg0.1, i8 %arg1.1) + %add.2 = call i8 @llvm.usub.sat.i8(i8 %arg0.2, i8 %arg1.2) + %add.3 = call i8 @llvm.usub.sat.i8(i8 %arg0.3, i8 %arg1.3) + %ins.0 = insertelement <4 x i8> undef, i8 %add.0, i64 0 + %ins.1 = insertelement <4 x i8> %ins.0, i8 %add.1, i64 1 + %ins.2 = insertelement <4 x i8> %ins.1, i8 %add.2, i64 2 + %ins.3 = insertelement <4 x i8> %ins.2, i8 %add.3, i64 3 + ret <4 x i8> %ins.3 + +} + + declare i16 @llvm.uadd.sat.i16(i16, i16) #0 declare i16 @llvm.usub.sat.i16(i16, i16) #0 declare i16 @llvm.sadd.sat.i16(i16, i16) #0 declare i16 @llvm.ssub.sat.i16(i16, i16) #0 +declare i8 @llvm.uadd.sat.i8(i8, i8) #0 +declare i8 @llvm.usub.sat.i8(i8, i8) #0 + declare i32 @llvm.uadd.sat.i32(i32, i32) #0 declare i32 @llvm.usub.sat.i32(i32, i32) #0 declare i32 @llvm.sadd.sat.i32(i32, i32) #0 diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/i8.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/i8.ll new file mode 100644 index 0000000000000..8d518c538a2a3 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/i8.ll @@ -0,0 +1,428 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer %s | FileCheck -check-prefixes=GFX7 %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer %s | FileCheck -check-prefixes=GFX8PLUS,GFX8 %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer %s | FileCheck -check-prefixes=GFX8PLUS,GFX9 %s + +define protected amdgpu_kernel void @phi(ptr addrspace(3) %inptr0, ptr addrspace(3) %inptr1, ptr %out, ptr %out1, i32 %flag) { +; GCN-LABEL: @vectorizePHI( +; GCN-NEXT: entry: +; GCN-NEXT: [[GEP0:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0:%.*]], i32 0 +; GCN-NEXT: [[ELE0:%.*]] = load i8, ptr addrspace(3) [[GEP0]], align 8 +; GCN-NEXT: [[GEP1:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 1 +; GCN-NEXT: [[ELE1:%.*]] = load i8, ptr addrspace(3) [[GEP1]], align 1 +; GCN-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 2 +; GCN-NEXT: [[ELE2:%.*]] = load i8, ptr addrspace(3) [[GEP2]], align 2 +; GCN-NEXT: [[GEP3:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 3 +; GCN-NEXT: [[ELE3:%.*]] = load i8, ptr addrspace(3) [[GEP3]], align 1 +; GCN-NEXT: br label [[DO_BODY:%.*]] +; GCN: do.body: +; GCN-NEXT: [[PHI0:%.*]] = phi i8 [ [[ELE3]], [[ENTRY:%.*]] ], [ [[OTHERELE3:%.*]], [[DO_BODY]] ] +; GCN-NEXT: [[PHI1:%.*]] = phi i8 [ [[ELE2]], [[ENTRY]] ], [ [[OTHERELE2:%.*]], [[DO_BODY]] ] +; GCN-NEXT: [[PHI2:%.*]] = phi i8 [ [[ELE1]], [[ENTRY]] ], [ [[OTHERELE1:%.*]], [[DO_BODY]] ] +; GCN-NEXT: [[PHI3:%.*]] = phi i8 [ [[ELE0]], [[ENTRY]] ], [ [[OTHERELE0:%.*]], [[DO_BODY]] ] +; GCN-NEXT: [[OTHERELE0]] = load i8, ptr addrspace(3) [[GEP0]], align 8 +; GCN-NEXT: [[OTHERELE1]] = load i8, ptr addrspace(3) [[GEP1]], align 1 +; GCN-NEXT: [[OTHERELE2]] = load i8, ptr addrspace(3) [[GEP2]], align 2 +; GCN-NEXT: [[OTHERELE3]] = load i8, ptr addrspace(3) [[GEP3]], align 1 +; GCN-NEXT: [[VEC00:%.*]] = insertelement <16 x i8> poison, i8 [[OTHERELE0]], i64 8 +; GCN-NEXT: [[VEC01:%.*]] = insertelement <16 x i8> [[VEC00]], i8 [[OTHERELE1]], i64 9 +; GCN-NEXT: [[VEC02:%.*]] = insertelement <16 x i8> [[VEC01]], i8 [[OTHERELE2]], i64 10 +; GCN-NEXT: [[VEC03:%.*]] = insertelement <16 x i8> [[VEC02]], i8 [[OTHERELE3]], i64 11 +; GCN-NEXT: [[VEC10:%.*]] = insertelement <16 x i8> poison, i8 [[PHI3]], i64 8 +; GCN-NEXT: [[VEC11:%.*]] = insertelement <16 x i8> [[VEC10]], i8 [[PHI2]], i64 9 +; GCN-NEXT: [[VEC12:%.*]] = insertelement <16 x i8> [[VEC11]], i8 [[PHI1]], i64 10 +; GCN-NEXT: [[VEC13:%.*]] = insertelement <16 x i8> [[VEC12]], i8 [[PHI0]], i64 11 +; GCN-NEXT: store <16 x i8> [[VEC13]], ptr addrspace(3) [[INPTR1:%.*]], align 2 +; GCN-NEXT: [[CMP:%.*]] = icmp eq i32 [[FLAG:%.*]], 0 +; GCN-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[DO_BODY]] +; GCN: exit: +; GCN-NEXT: store <16 x i8> [[VEC13]], ptr [[OUT:%.*]], align 16 +; GCN-NEXT: store <16 x i8> [[VEC03]], ptr [[OUT1:%.*]], align 16 +; GCN-NEXT: ret void +; +; GFX7-LABEL: @phi( +; GFX7-NEXT: entry: +; GFX7-NEXT: [[GEP0:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0:%.*]], i32 0 +; GFX7-NEXT: [[ELE0:%.*]] = load i8, ptr addrspace(3) [[GEP0]], align 8 +; GFX7-NEXT: [[GEP1:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 1 +; GFX7-NEXT: [[ELE1:%.*]] = load i8, ptr addrspace(3) [[GEP1]], align 1 +; GFX7-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 2 +; GFX7-NEXT: [[ELE2:%.*]] = load i8, ptr addrspace(3) [[GEP2]], align 2 +; GFX7-NEXT: [[GEP3:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 3 +; GFX7-NEXT: [[ELE3:%.*]] = load i8, ptr addrspace(3) [[GEP3]], align 1 +; GFX7-NEXT: br label [[DO_BODY:%.*]] +; GFX7: do.body: +; GFX7-NEXT: [[PHI0:%.*]] = phi i8 [ [[ELE3]], [[ENTRY:%.*]] ], [ [[OTHERELE3:%.*]], [[DO_BODY]] ] +; GFX7-NEXT: [[PHI1:%.*]] = phi i8 [ [[ELE2]], [[ENTRY]] ], [ [[OTHERELE2:%.*]], [[DO_BODY]] ] +; GFX7-NEXT: [[PHI2:%.*]] = phi i8 [ [[ELE1]], [[ENTRY]] ], [ [[OTHERELE1:%.*]], [[DO_BODY]] ] +; GFX7-NEXT: [[PHI3:%.*]] = phi i8 [ [[ELE0]], [[ENTRY]] ], [ [[OTHERELE0:%.*]], [[DO_BODY]] ] +; GFX7-NEXT: [[OTHERELE0]] = load i8, ptr addrspace(3) [[GEP0]], align 8 +; GFX7-NEXT: [[OTHERELE1]] = load i8, ptr addrspace(3) [[GEP1]], align 1 +; GFX7-NEXT: [[OTHERELE2]] = load i8, ptr addrspace(3) [[GEP2]], align 2 +; GFX7-NEXT: [[OTHERELE3]] = load i8, ptr addrspace(3) [[GEP3]], align 1 +; GFX7-NEXT: [[VEC00:%.*]] = insertelement <16 x i8> poison, i8 [[OTHERELE0]], i64 8 +; GFX7-NEXT: [[VEC01:%.*]] = insertelement <16 x i8> [[VEC00]], i8 [[OTHERELE1]], i64 9 +; GFX7-NEXT: [[VEC02:%.*]] = insertelement <16 x i8> [[VEC01]], i8 [[OTHERELE2]], i64 10 +; GFX7-NEXT: [[VEC03:%.*]] = insertelement <16 x i8> [[VEC02]], i8 [[OTHERELE3]], i64 11 +; GFX7-NEXT: [[VEC10:%.*]] = insertelement <16 x i8> poison, i8 [[PHI3]], i64 8 +; GFX7-NEXT: [[VEC11:%.*]] = insertelement <16 x i8> [[VEC10]], i8 [[PHI2]], i64 9 +; GFX7-NEXT: [[VEC12:%.*]] = insertelement <16 x i8> [[VEC11]], i8 [[PHI1]], i64 10 +; GFX7-NEXT: [[VEC13:%.*]] = insertelement <16 x i8> [[VEC12]], i8 [[PHI0]], i64 11 +; GFX7-NEXT: store <16 x i8> [[VEC13]], ptr addrspace(3) [[INPTR1:%.*]], align 2 +; GFX7-NEXT: [[CMP:%.*]] = icmp eq i32 [[FLAG:%.*]], 0 +; GFX7-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[DO_BODY]] +; GFX7: exit: +; GFX7-NEXT: store <16 x i8> [[VEC13]], ptr [[OUT:%.*]], align 16 +; GFX7-NEXT: store <16 x i8> [[VEC03]], ptr [[OUT1:%.*]], align 16 +; GFX7-NEXT: ret void +; +; GFX8PLUS-LABEL: @phi( +; GFX8PLUS-NEXT: entry: +; GFX8PLUS-NEXT: [[GEP0:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0:%.*]], i32 0 +; GFX8PLUS-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr addrspace(3) [[GEP0]], align 8 +; GFX8PLUS-NEXT: br label [[DO_BODY:%.*]] +; GFX8PLUS: do.body: +; GFX8PLUS-NEXT: [[TMP1:%.*]] = phi <4 x i8> [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP2:%.*]], [[DO_BODY]] ] +; GFX8PLUS-NEXT: [[TMP2]] = load <4 x i8>, ptr addrspace(3) [[GEP0]], align 8 +; GFX8PLUS-NEXT: [[VEC03:%.*]] = shufflevector <4 x i8> [[TMP2]], <4 x i8> poison, <16 x i32> +; GFX8PLUS-NEXT: [[VEC13:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> poison, <16 x i32> +; GFX8PLUS-NEXT: store <16 x i8> [[VEC13]], ptr addrspace(3) [[INPTR1:%.*]], align 2 +; GFX8PLUS-NEXT: [[CMP:%.*]] = icmp eq i32 [[FLAG:%.*]], 0 +; GFX8PLUS-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[DO_BODY]] +; GFX8PLUS: exit: +; GFX8PLUS-NEXT: store <16 x i8> [[VEC13]], ptr [[OUT:%.*]], align 16 +; GFX8PLUS-NEXT: store <16 x i8> [[VEC03]], ptr [[OUT1:%.*]], align 16 +; GFX8PLUS-NEXT: ret void +; +entry: + %gep0 = getelementptr i8, ptr addrspace(3) %inptr0, i32 0 + %ele0 = load i8, ptr addrspace(3) %gep0, align 8 + %gep1 = getelementptr i8, ptr addrspace(3) %inptr0, i32 1 + %ele1 = load i8, ptr addrspace(3) %gep1, align 1 + %gep2 = getelementptr i8, ptr addrspace(3) %inptr0, i32 2 + %ele2 = load i8, ptr addrspace(3) %gep2, align 2 + %gep3 = getelementptr i8, ptr addrspace(3) %inptr0, i32 3 + %ele3 = load i8, ptr addrspace(3) %gep3, align 1 + br label %do.body + +do.body: + %phi0 = phi i8 [ %ele3, %entry ], [ %otherele3, %do.body ] + %phi1 = phi i8 [ %ele2, %entry ], [ %otherele2, %do.body ] + %phi2 = phi i8 [ %ele1, %entry ], [ %otherele1, %do.body ] + %phi3 = phi i8 [ %ele0, %entry ], [ %otherele0, %do.body ] + %otherele0 = load i8, ptr addrspace(3) %gep0, align 8 + %otherele1 = load i8, ptr addrspace(3) %gep1, align 1 + %otherele2 = load i8, ptr addrspace(3) %gep2, align 2 + %otherele3 = load i8, ptr addrspace(3) %gep3, align 1 + %vec00 = insertelement <16 x i8> poison, i8 %otherele0, i64 8 + %vec01 = insertelement <16 x i8> %vec00, i8 %otherele1, i64 9 + %vec02 = insertelement <16 x i8> %vec01, i8 %otherele2, i64 10 + %vec03 = insertelement <16 x i8> %vec02, i8 %otherele3, i64 11 + %vec10 = insertelement <16 x i8> poison, i8 %phi3, i64 8 + %vec11 = insertelement <16 x i8> %vec10, i8 %phi2, i64 9 + %vec12 = insertelement <16 x i8> %vec11, i8 %phi1, i64 10 + %vec13 = insertelement <16 x i8> %vec12, i8 %phi0, i64 11 + store <16 x i8> %vec13, ptr addrspace(3) %inptr1, align 2 + %cmp = icmp eq i32 %flag, 0 + br i1 %cmp, label %exit, label %do.body + +exit: + store <16 x i8> %vec13, ptr %out + store <16 x i8> %vec03, ptr %out1 + ret void +} + + +define protected amdgpu_kernel void @arith_phi(ptr addrspace(3) %inptr0, ptr %out, i32 %flag) { +; GCN-LABEL: @vectorizePHI2( +; GCN-NEXT: entry: +; GCN-NEXT: [[GEP0:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0:%.*]], i32 0 +; GCN-NEXT: [[ELE0:%.*]] = load i8, ptr addrspace(3) [[GEP0]], align 8 +; GCN-NEXT: [[GEP1:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 1 +; GCN-NEXT: [[ELE1:%.*]] = load i8, ptr addrspace(3) [[GEP1]], align 1 +; GCN-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 2 +; GCN-NEXT: [[ELE2:%.*]] = load i8, ptr addrspace(3) [[GEP2]], align 2 +; GCN-NEXT: [[GEP3:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 3 +; GCN-NEXT: [[ELE3:%.*]] = load i8, ptr addrspace(3) [[GEP3]], align 1 +; GCN-NEXT: [[CMP:%.*]] = icmp eq i32 [[FLAG:%.*]], 0 +; GCN-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[BB_1:%.*]] +; GCN: bb.1: +; GCN-NEXT: [[ADD0:%.*]] = add i8 [[ELE0]], 1 +; GCN-NEXT: [[ADD1:%.*]] = add i8 [[ELE1]], 1 +; GCN-NEXT: [[ADD2:%.*]] = add i8 [[ELE2]], 1 +; GCN-NEXT: [[ADD3:%.*]] = add i8 [[ELE3]], 1 +; GCN-NEXT: br label [[EXIT]] +; GCN: exit: +; GCN-NEXT: [[PHI0:%.*]] = phi i8 [ [[ELE3]], [[ENTRY:%.*]] ], [ [[ADD0]], [[BB_1]] ] +; GCN-NEXT: [[PHI1:%.*]] = phi i8 [ [[ELE2]], [[ENTRY]] ], [ [[ADD1]], [[BB_1]] ] +; GCN-NEXT: [[PHI2:%.*]] = phi i8 [ [[ELE1]], [[ENTRY]] ], [ [[ADD2]], [[BB_1]] ] +; GCN-NEXT: [[PHI3:%.*]] = phi i8 [ [[ELE0]], [[ENTRY]] ], [ [[ADD3]], [[BB_1]] ] +; GCN-NEXT: [[OTHERELE0:%.*]] = load i8, ptr addrspace(3) [[GEP0]], align 8 +; GCN-NEXT: [[OTHERELE1:%.*]] = load i8, ptr addrspace(3) [[GEP1]], align 1 +; GCN-NEXT: [[OTHERELE2:%.*]] = load i8, ptr addrspace(3) [[GEP2]], align 2 +; GCN-NEXT: [[OTHERELE3:%.*]] = load i8, ptr addrspace(3) [[GEP3]], align 1 +; GCN-NEXT: [[VEC10:%.*]] = insertelement <16 x i8> poison, i8 [[PHI3]], i64 8 +; GCN-NEXT: [[VEC11:%.*]] = insertelement <16 x i8> [[VEC10]], i8 [[PHI2]], i64 9 +; GCN-NEXT: [[VEC12:%.*]] = insertelement <16 x i8> [[VEC11]], i8 [[PHI1]], i64 10 +; GCN-NEXT: [[VEC13:%.*]] = insertelement <16 x i8> [[VEC12]], i8 [[PHI0]], i64 11 +; GCN-NEXT: store <16 x i8> [[VEC13]], ptr [[OUT:%.*]], align 2 +; GCN-NEXT: ret void +; +; GFX7-LABEL: @arith_phi( +; GFX7-NEXT: entry: +; GFX7-NEXT: [[GEP0:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0:%.*]], i32 0 +; GFX7-NEXT: [[ELE0:%.*]] = load i8, ptr addrspace(3) [[GEP0]], align 8 +; GFX7-NEXT: [[GEP1:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 1 +; GFX7-NEXT: [[ELE1:%.*]] = load i8, ptr addrspace(3) [[GEP1]], align 1 +; GFX7-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 2 +; GFX7-NEXT: [[ELE2:%.*]] = load i8, ptr addrspace(3) [[GEP2]], align 2 +; GFX7-NEXT: [[GEP3:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 3 +; GFX7-NEXT: [[ELE3:%.*]] = load i8, ptr addrspace(3) [[GEP3]], align 1 +; GFX7-NEXT: [[CMP:%.*]] = icmp eq i32 [[FLAG:%.*]], 0 +; GFX7-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[BB_1:%.*]] +; GFX7: bb.1: +; GFX7-NEXT: [[ADD0:%.*]] = add i8 [[ELE0]], 1 +; GFX7-NEXT: [[ADD1:%.*]] = add i8 [[ELE1]], 1 +; GFX7-NEXT: [[ADD2:%.*]] = add i8 [[ELE2]], 1 +; GFX7-NEXT: [[ADD3:%.*]] = add i8 [[ELE3]], 1 +; GFX7-NEXT: br label [[EXIT]] +; GFX7: exit: +; GFX7-NEXT: [[PHI0:%.*]] = phi i8 [ [[ELE3]], [[ENTRY:%.*]] ], [ [[ADD0]], [[BB_1]] ] +; GFX7-NEXT: [[PHI1:%.*]] = phi i8 [ [[ELE2]], [[ENTRY]] ], [ [[ADD1]], [[BB_1]] ] +; GFX7-NEXT: [[PHI2:%.*]] = phi i8 [ [[ELE1]], [[ENTRY]] ], [ [[ADD2]], [[BB_1]] ] +; GFX7-NEXT: [[PHI3:%.*]] = phi i8 [ [[ELE0]], [[ENTRY]] ], [ [[ADD3]], [[BB_1]] ] +; GFX7-NEXT: [[OTHERELE0:%.*]] = load i8, ptr addrspace(3) [[GEP0]], align 8 +; GFX7-NEXT: [[OTHERELE1:%.*]] = load i8, ptr addrspace(3) [[GEP1]], align 1 +; GFX7-NEXT: [[OTHERELE2:%.*]] = load i8, ptr addrspace(3) [[GEP2]], align 2 +; GFX7-NEXT: [[OTHERELE3:%.*]] = load i8, ptr addrspace(3) [[GEP3]], align 1 +; GFX7-NEXT: [[VEC10:%.*]] = insertelement <16 x i8> poison, i8 [[PHI3]], i64 8 +; GFX7-NEXT: [[VEC11:%.*]] = insertelement <16 x i8> [[VEC10]], i8 [[PHI2]], i64 9 +; GFX7-NEXT: [[VEC12:%.*]] = insertelement <16 x i8> [[VEC11]], i8 [[PHI1]], i64 10 +; GFX7-NEXT: [[VEC13:%.*]] = insertelement <16 x i8> [[VEC12]], i8 [[PHI0]], i64 11 +; GFX7-NEXT: store <16 x i8> [[VEC13]], ptr [[OUT:%.*]], align 2 +; GFX7-NEXT: ret void +; +; GFX8PLUS-LABEL: @arith_phi( +; GFX8PLUS-NEXT: entry: +; GFX8PLUS-NEXT: [[GEP0:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0:%.*]], i32 0 +; GFX8PLUS-NEXT: [[GEP1:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 1 +; GFX8PLUS-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 2 +; GFX8PLUS-NEXT: [[GEP3:%.*]] = getelementptr i8, ptr addrspace(3) [[INPTR0]], i32 3 +; GFX8PLUS-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr addrspace(3) [[GEP0]], align 8 +; GFX8PLUS-NEXT: [[CMP:%.*]] = icmp eq i32 [[FLAG:%.*]], 0 +; GFX8PLUS-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[BB_1:%.*]] +; GFX8PLUS: bb.1: +; GFX8PLUS-NEXT: [[TMP1:%.*]] = add <4 x i8> [[TMP0]], splat (i8 1) +; GFX8PLUS-NEXT: [[TMP2:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> poison, <4 x i32> +; GFX8PLUS-NEXT: br label [[EXIT]] +; GFX8PLUS: exit: +; GFX8PLUS-NEXT: [[TMP3:%.*]] = phi <4 x i8> [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP2]], [[BB_1]] ] +; GFX8PLUS-NEXT: [[OTHERELE0:%.*]] = load i8, ptr addrspace(3) [[GEP0]], align 8 +; GFX8PLUS-NEXT: [[OTHERELE1:%.*]] = load i8, ptr addrspace(3) [[GEP1]], align 1 +; GFX8PLUS-NEXT: [[OTHERELE2:%.*]] = load i8, ptr addrspace(3) [[GEP2]], align 2 +; GFX8PLUS-NEXT: [[OTHERELE3:%.*]] = load i8, ptr addrspace(3) [[GEP3]], align 1 +; GFX8PLUS-NEXT: [[VEC13:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <16 x i32> +; GFX8PLUS-NEXT: store <16 x i8> [[VEC13]], ptr [[OUT:%.*]], align 2 +; GFX8PLUS-NEXT: ret void +; +entry: + %gep0 = getelementptr i8, ptr addrspace(3) %inptr0, i32 0 + %ele0 = load i8, ptr addrspace(3) %gep0, align 8 + %gep1 = getelementptr i8, ptr addrspace(3) %inptr0, i32 1 + %ele1 = load i8, ptr addrspace(3) %gep1, align 1 + %gep2 = getelementptr i8, ptr addrspace(3) %inptr0, i32 2 + %ele2 = load i8, ptr addrspace(3) %gep2, align 2 + %gep3 = getelementptr i8, ptr addrspace(3) %inptr0, i32 3 + %ele3 = load i8, ptr addrspace(3) %gep3, align 1 + %cmp = icmp eq i32 %flag, 0 + br i1 %cmp, label %exit, label %bb.1 + +bb.1: + %add0 = add i8 %ele0, 1 + %add1 = add i8 %ele1, 1 + %add2 = add i8 %ele2, 1 + %add3 = add i8 %ele3, 1 + br label %exit + +exit: + %phi0 = phi i8 [ %ele3, %entry ], [ %add0, %bb.1 ] + %phi1 = phi i8 [ %ele2, %entry ], [ %add1, %bb.1 ] + %phi2 = phi i8 [ %ele1, %entry ], [ %add2, %bb.1 ] + %phi3 = phi i8 [ %ele0, %entry ], [ %add3, %bb.1 ] + %otherele0 = load i8, ptr addrspace(3) %gep0, align 8 + %otherele1 = load i8, ptr addrspace(3) %gep1, align 1 + %otherele2 = load i8, ptr addrspace(3) %gep2, align 2 + %otherele3 = load i8, ptr addrspace(3) %gep3, align 1 + %vec10 = insertelement <16 x i8> poison, i8 %phi3, i64 8 + %vec11 = insertelement <16 x i8> %vec10, i8 %phi2, i64 9 + %vec12 = insertelement <16 x i8> %vec11, i8 %phi1, i64 10 + %vec13 = insertelement <16 x i8> %vec12, i8 %phi0, i64 11 + store <16 x i8> %vec13, ptr %out, align 2 + ret void +} + +define protected amdgpu_kernel void @arith(<16 x i8> %invec, ptr %out, i32 %flag) { +; GFX7-LABEL: @arith( +; GFX7-NEXT: entry: +; GFX7-NEXT: [[EL0:%.*]] = extractelement <16 x i8> [[INVEC:%.*]], i64 0 +; GFX7-NEXT: [[EL1:%.*]] = extractelement <16 x i8> [[INVEC]], i64 1 +; GFX7-NEXT: [[EL2:%.*]] = extractelement <16 x i8> [[INVEC]], i64 2 +; GFX7-NEXT: [[EL3:%.*]] = extractelement <16 x i8> [[INVEC]], i64 3 +; GFX7-NEXT: [[EL4:%.*]] = extractelement <16 x i8> [[INVEC]], i64 4 +; GFX7-NEXT: [[EL5:%.*]] = extractelement <16 x i8> [[INVEC]], i64 5 +; GFX7-NEXT: [[EL6:%.*]] = extractelement <16 x i8> [[INVEC]], i64 6 +; GFX7-NEXT: [[EL7:%.*]] = extractelement <16 x i8> [[INVEC]], i64 7 +; GFX7-NEXT: [[EL8:%.*]] = extractelement <16 x i8> [[INVEC]], i64 8 +; GFX7-NEXT: [[EL9:%.*]] = extractelement <16 x i8> [[INVEC]], i64 9 +; GFX7-NEXT: [[EL10:%.*]] = extractelement <16 x i8> [[INVEC]], i64 10 +; GFX7-NEXT: [[EL11:%.*]] = extractelement <16 x i8> [[INVEC]], i64 11 +; GFX7-NEXT: [[EL12:%.*]] = extractelement <16 x i8> [[INVEC]], i64 12 +; GFX7-NEXT: [[EL13:%.*]] = extractelement <16 x i8> [[INVEC]], i64 13 +; GFX7-NEXT: [[EL14:%.*]] = extractelement <16 x i8> [[INVEC]], i64 14 +; GFX7-NEXT: [[EL15:%.*]] = extractelement <16 x i8> [[INVEC]], i64 15 +; GFX7-NEXT: [[MUL0:%.*]] = mul i8 [[EL0]], 1 +; GFX7-NEXT: [[MUL1:%.*]] = mul i8 [[EL1]], 1 +; GFX7-NEXT: [[MUL2:%.*]] = mul i8 [[EL2]], 1 +; GFX7-NEXT: [[MUL3:%.*]] = mul i8 [[EL3]], 1 +; GFX7-NEXT: [[MUL4:%.*]] = mul i8 [[EL4]], 1 +; GFX7-NEXT: [[MUL5:%.*]] = mul i8 [[EL5]], 1 +; GFX7-NEXT: [[MUL6:%.*]] = mul i8 [[EL6]], 1 +; GFX7-NEXT: [[MUL7:%.*]] = mul i8 [[EL7]], 1 +; GFX7-NEXT: [[MUL8:%.*]] = mul i8 [[EL8]], 1 +; GFX7-NEXT: [[MUL9:%.*]] = mul i8 [[EL9]], 1 +; GFX7-NEXT: [[MUL10:%.*]] = mul i8 [[EL10]], 1 +; GFX7-NEXT: [[MUL11:%.*]] = mul i8 [[EL11]], 1 +; GFX7-NEXT: [[MUL12:%.*]] = mul i8 [[EL12]], 1 +; GFX7-NEXT: [[MUL13:%.*]] = mul i8 [[EL13]], 1 +; GFX7-NEXT: [[MUL14:%.*]] = mul i8 [[EL14]], 1 +; GFX7-NEXT: [[MUL15:%.*]] = mul i8 [[EL15]], 1 +; GFX7-NEXT: [[ADD0:%.*]] = add i8 [[MUL0]], 1 +; GFX7-NEXT: [[ADD1:%.*]] = add i8 [[MUL1]], 1 +; GFX7-NEXT: [[ADD2:%.*]] = add i8 [[MUL2]], 1 +; GFX7-NEXT: [[ADD3:%.*]] = add i8 [[MUL3]], 1 +; GFX7-NEXT: [[ADD4:%.*]] = add i8 [[MUL4]], 1 +; GFX7-NEXT: [[ADD5:%.*]] = add i8 [[MUL5]], 1 +; GFX7-NEXT: [[ADD6:%.*]] = add i8 [[MUL6]], 1 +; GFX7-NEXT: [[ADD7:%.*]] = add i8 [[MUL7]], 1 +; GFX7-NEXT: [[ADD8:%.*]] = add i8 [[MUL8]], 1 +; GFX7-NEXT: [[ADD9:%.*]] = add i8 [[MUL9]], 1 +; GFX7-NEXT: [[ADD10:%.*]] = add i8 [[MUL10]], 1 +; GFX7-NEXT: [[ADD11:%.*]] = add i8 [[MUL11]], 1 +; GFX7-NEXT: [[ADD12:%.*]] = add i8 [[MUL12]], 1 +; GFX7-NEXT: [[ADD13:%.*]] = add i8 [[MUL13]], 1 +; GFX7-NEXT: [[ADD14:%.*]] = add i8 [[MUL14]], 1 +; GFX7-NEXT: [[ADD15:%.*]] = add i8 [[MUL15]], 1 +; GFX7-NEXT: [[VECINS0:%.*]] = insertelement <16 x i8> poison, i8 [[ADD0]], i64 0 +; GFX7-NEXT: [[VECINS1:%.*]] = insertelement <16 x i8> [[VECINS0]], i8 [[ADD1]], i64 1 +; GFX7-NEXT: [[VECINS2:%.*]] = insertelement <16 x i8> [[VECINS1]], i8 [[ADD2]], i64 2 +; GFX7-NEXT: [[VECINS3:%.*]] = insertelement <16 x i8> [[VECINS2]], i8 [[ADD3]], i64 3 +; GFX7-NEXT: [[VECINS4:%.*]] = insertelement <16 x i8> [[VECINS3]], i8 [[ADD4]], i64 4 +; GFX7-NEXT: [[VECINS5:%.*]] = insertelement <16 x i8> [[VECINS4]], i8 [[ADD5]], i64 5 +; GFX7-NEXT: [[VECINS6:%.*]] = insertelement <16 x i8> [[VECINS5]], i8 [[ADD6]], i64 6 +; GFX7-NEXT: [[VECINS7:%.*]] = insertelement <16 x i8> [[VECINS6]], i8 [[ADD7]], i64 7 +; GFX7-NEXT: [[VECINS8:%.*]] = insertelement <16 x i8> [[VECINS7]], i8 [[ADD8]], i64 8 +; GFX7-NEXT: [[VECINS9:%.*]] = insertelement <16 x i8> [[VECINS8]], i8 [[ADD9]], i64 9 +; GFX7-NEXT: [[VECINS10:%.*]] = insertelement <16 x i8> [[VECINS9]], i8 [[ADD10]], i64 10 +; GFX7-NEXT: [[VECINS11:%.*]] = insertelement <16 x i8> [[VECINS10]], i8 [[ADD11]], i64 11 +; GFX7-NEXT: [[VECINS12:%.*]] = insertelement <16 x i8> [[VECINS11]], i8 [[ADD12]], i64 12 +; GFX7-NEXT: [[VECINS13:%.*]] = insertelement <16 x i8> [[VECINS12]], i8 [[ADD13]], i64 13 +; GFX7-NEXT: [[VECINS14:%.*]] = insertelement <16 x i8> [[VECINS13]], i8 [[ADD14]], i64 14 +; GFX7-NEXT: [[VECINS15:%.*]] = insertelement <16 x i8> [[VECINS14]], i8 [[ADD15]], i64 15 +; GFX7-NEXT: store <16 x i8> [[VECINS15]], ptr [[OUT:%.*]], align 16 +; GFX7-NEXT: ret void +; +; GFX8PLUS-LABEL: @arith( +; GFX8PLUS-NEXT: entry: +; GFX8PLUS-NEXT: [[TMP0:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> poison, <4 x i32> +; GFX8PLUS-NEXT: [[TMP1:%.*]] = mul <4 x i8> [[TMP0]], splat (i8 1) +; GFX8PLUS-NEXT: [[TMP2:%.*]] = add <4 x i8> [[TMP1]], splat (i8 1) +; GFX8PLUS-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> [[INVEC]], <16 x i8> poison, <4 x i32> +; GFX8PLUS-NEXT: [[TMP4:%.*]] = mul <4 x i8> [[TMP3]], splat (i8 1) +; GFX8PLUS-NEXT: [[TMP5:%.*]] = add <4 x i8> [[TMP4]], splat (i8 1) +; GFX8PLUS-NEXT: [[TMP6:%.*]] = shufflevector <16 x i8> [[INVEC]], <16 x i8> poison, <4 x i32> +; GFX8PLUS-NEXT: [[TMP7:%.*]] = mul <4 x i8> [[TMP6]], splat (i8 1) +; GFX8PLUS-NEXT: [[TMP8:%.*]] = add <4 x i8> [[TMP7]], splat (i8 1) +; GFX8PLUS-NEXT: [[TMP9:%.*]] = shufflevector <16 x i8> [[INVEC]], <16 x i8> poison, <4 x i32> +; GFX8PLUS-NEXT: [[TMP10:%.*]] = mul <4 x i8> [[TMP9]], splat (i8 1) +; GFX8PLUS-NEXT: [[TMP11:%.*]] = add <4 x i8> [[TMP10]], splat (i8 1) +; GFX8PLUS-NEXT: [[TMP12:%.*]] = shufflevector <4 x i8> [[TMP2]], <4 x i8> poison, <16 x i32> +; GFX8PLUS-NEXT: [[TMP13:%.*]] = shufflevector <4 x i8> [[TMP5]], <4 x i8> poison, <16 x i32> +; GFX8PLUS-NEXT: [[VECINS71:%.*]] = shufflevector <16 x i8> [[TMP12]], <16 x i8> [[TMP13]], <16 x i32> +; GFX8PLUS-NEXT: [[TMP14:%.*]] = shufflevector <4 x i8> [[TMP8]], <4 x i8> poison, <16 x i32> +; GFX8PLUS-NEXT: [[VECINS112:%.*]] = shufflevector <16 x i8> [[VECINS71]], <16 x i8> [[TMP14]], <16 x i32> +; GFX8PLUS-NEXT: [[TMP15:%.*]] = shufflevector <4 x i8> [[TMP11]], <4 x i8> poison, <16 x i32> +; GFX8PLUS-NEXT: [[VECINS15:%.*]] = shufflevector <16 x i8> [[VECINS112]], <16 x i8> [[TMP15]], <16 x i32> +; GFX8PLUS-NEXT: store <16 x i8> [[VECINS15]], ptr [[OUT:%.*]], align 16 +; GFX8PLUS-NEXT: ret void +; +entry: + %el0 = extractelement <16 x i8> %invec, i64 0 + %el1 = extractelement <16 x i8> %invec, i64 1 + %el2 = extractelement <16 x i8> %invec, i64 2 + %el3 = extractelement <16 x i8> %invec, i64 3 + %el4 = extractelement <16 x i8> %invec, i64 4 + %el5 = extractelement <16 x i8> %invec, i64 5 + %el6 = extractelement <16 x i8> %invec, i64 6 + %el7 = extractelement <16 x i8> %invec, i64 7 + %el8 = extractelement <16 x i8> %invec, i64 8 + %el9 = extractelement <16 x i8> %invec, i64 9 + %el10 = extractelement <16 x i8> %invec, i64 10 + %el11 = extractelement <16 x i8> %invec, i64 11 + %el12 = extractelement <16 x i8> %invec, i64 12 + %el13 = extractelement <16 x i8> %invec, i64 13 + %el14 = extractelement <16 x i8> %invec, i64 14 + %el15 = extractelement <16 x i8> %invec, i64 15 + %mul0 = mul i8 %el0, 1 + %mul1 = mul i8 %el1, 1 + %mul2 = mul i8 %el2, 1 + %mul3 = mul i8 %el3, 1 + %mul4 = mul i8 %el4, 1 + %mul5 = mul i8 %el5, 1 + %mul6 = mul i8 %el6, 1 + %mul7 = mul i8 %el7, 1 + %mul8 = mul i8 %el8, 1 + %mul9 = mul i8 %el9, 1 + %mul10 = mul i8 %el10, 1 + %mul11 = mul i8 %el11, 1 + %mul12 = mul i8 %el12, 1 + %mul13 = mul i8 %el13, 1 + %mul14 = mul i8 %el14, 1 + %mul15 = mul i8 %el15, 1 + %add0 = add i8 %mul0, 1 + %add1 = add i8 %mul1, 1 + %add2 = add i8 %mul2, 1 + %add3 = add i8 %mul3, 1 + %add4 = add i8 %mul4, 1 + %add5 = add i8 %mul5, 1 + %add6 = add i8 %mul6, 1 + %add7 = add i8 %mul7, 1 + %add8 = add i8 %mul8, 1 + %add9 = add i8 %mul9, 1 + %add10 = add i8 %mul10, 1 + %add11 = add i8 %mul11, 1 + %add12 = add i8 %mul12, 1 + %add13 = add i8 %mul13, 1 + %add14 = add i8 %mul14, 1 + %add15 = add i8 %mul15, 1 + %vecins0 = insertelement <16 x i8> poison, i8 %add0, i64 0 + %vecins1 = insertelement <16 x i8> %vecins0, i8 %add1, i64 1 + %vecins2 = insertelement <16 x i8> %vecins1, i8 %add2, i64 2 + %vecins3 = insertelement <16 x i8> %vecins2, i8 %add3, i64 3 + %vecins4 = insertelement <16 x i8> %vecins3, i8 %add4, i64 4 + %vecins5 = insertelement <16 x i8> %vecins4, i8 %add5, i64 5 + %vecins6 = insertelement <16 x i8> %vecins5, i8 %add6, i64 6 + %vecins7 = insertelement <16 x i8> %vecins6, i8 %add7, i64 7 + %vecins8 = insertelement <16 x i8> %vecins7, i8 %add8, i64 8 + %vecins9 = insertelement <16 x i8> %vecins8, i8 %add9, i64 9 + %vecins10 = insertelement <16 x i8> %vecins9, i8 %add10, i64 10 + %vecins11 = insertelement <16 x i8> %vecins10, i8 %add11, i64 11 + %vecins12 = insertelement <16 x i8> %vecins11, i8 %add12, i64 12 + %vecins13 = insertelement <16 x i8> %vecins12, i8 %add13, i64 13 + %vecins14 = insertelement <16 x i8> %vecins13, i8 %add14, i64 14 + %vecins15 = insertelement <16 x i8> %vecins14, i8 %add15, i64 15 + store <16 x i8> %vecins15, ptr %out + ret void +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX8: {{.*}} +; GFX9: {{.*}} diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll index a3a4ab948519f..5593fe9bab6ee 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll @@ -90,3 +90,78 @@ bb1: %o3 = insertelement <4 x half> %o2, half %c3, i64 3 ret <4 x half> %o3 } + + +define <4 x i8> @phisi8(i1 %cmp1, <4 x i8> %in1, <4 x i8> %in2) { +; CHECK-LABEL: @phisi8( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 [[CMP1:%.*]], label [[BB1:%.*]], label [[BB0:%.*]] +; CHECK: bb0: +; CHECK-NEXT: br label [[BB1]] +; CHECK: bb1: +; CHECK-NEXT: [[O3:%.*]] = phi <4 x i8> [ [[IN1:%.*]], [[ENTRY:%.*]] ], [ [[IN2:%.*]], [[BB0]] ] +; CHECK-NEXT: ret <4 x i8> [[O3]] +; +entry: + %a0 = extractelement <4 x i8> %in1, i64 0 + %a1 = extractelement <4 x i8> %in1, i64 1 + %a2 = extractelement <4 x i8> %in1, i64 2 + %a3 = extractelement <4 x i8> %in1, i64 3 + br i1 %cmp1, label %bb1, label %bb0 + +bb0: + %b0 = extractelement <4 x i8> %in2, i64 0 + %b1 = extractelement <4 x i8> %in2, i64 1 + %b2 = extractelement <4 x i8> %in2, i64 2 + %b3 = extractelement <4 x i8> %in2, i64 3 + br label %bb1 + +bb1: + %c0 = phi i8 [ %a0, %entry ], [ %b0, %bb0 ] + %c1 = phi i8 [ %a1, %entry ], [ %b1, %bb0 ] + %c2 = phi i8 [ %a2, %entry ], [ %b2, %bb0 ] + %c3 = phi i8 [ %a3, %entry ], [ %b3, %bb0 ] + + %o0 = insertelement <4 x i8> undef, i8 %c0, i64 0 + %o1 = insertelement <4 x i8> %o0, i8 %c1, i64 1 + %o2 = insertelement <4 x i8> %o1, i8 %c2, i64 2 + %o3 = insertelement <4 x i8> %o2, i8 %c3, i64 3 + ret <4 x i8> %o3 +} + +define <4 x i8> @phisi8_reverse(i1 %cmp1, <4 x i8> %in1, <4 x i8> %in2) { +; CHECK-LABEL: @phisi8_reverse( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 [[CMP1:%.*]], label [[BB1:%.*]], label [[BB0:%.*]] +; CHECK: bb0: +; CHECK-NEXT: br label [[BB1]] +; CHECK: bb1: +; CHECK-NEXT: [[O3:%.*]] = phi <4 x i8> [ [[IN1:%.*]], [[ENTRY:%.*]] ], [ [[IN2:%.*]], [[BB0]] ] +; CHECK-NEXT: ret <4 x i8> [[O3]] +; +entry: + %a0 = extractelement <4 x i8> %in1, i64 0 + %a1 = extractelement <4 x i8> %in1, i64 1 + %a2 = extractelement <4 x i8> %in1, i64 2 + %a3 = extractelement <4 x i8> %in1, i64 3 + br i1 %cmp1, label %bb1, label %bb0 + +bb0: + %b0 = extractelement <4 x i8> %in2, i64 0 + %b1 = extractelement <4 x i8> %in2, i64 1 + %b2 = extractelement <4 x i8> %in2, i64 2 + %b3 = extractelement <4 x i8> %in2, i64 3 + br label %bb1 + +bb1: + %c3 = phi i8 [ %a3, %entry ], [ %b3, %bb0 ] + %c2 = phi i8 [ %a2, %entry ], [ %b2, %bb0 ] + %c1 = phi i8 [ %a1, %entry ], [ %b1, %bb0 ] + %c0 = phi i8 [ %a0, %entry ], [ %b0, %bb0 ] + + %o0 = insertelement <4 x i8> undef, i8 %c0, i64 0 + %o1 = insertelement <4 x i8> %o0, i8 %c1, i64 1 + %o2 = insertelement <4 x i8> %o1, i8 %c2, i64 2 + %o3 = insertelement <4 x i8> %o2, i8 %c3, i64 3 + ret <4 x i8> %o3 +} diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll index b2246e4f9c6c4..e899ad749bb02 100644 --- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll +++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll @@ -548,3 +548,217 @@ entry: ret float %add3 } + +define i8 @reduction_v4i8(<4 x i8> %a) { +; GCN-LABEL: @reduction_v4i8( +; GCN-NEXT: entry: +; GCN-NEXT: [[ADD3:%.*]] = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> [[A:%.*]]) +; GCN-NEXT: ret i8 [[ADD3]] +; +entry: + %elt0 = extractelement <4 x i8> %a, i64 0 + %elt1 = extractelement <4 x i8> %a, i64 1 + %elt2 = extractelement <4 x i8> %a, i64 2 + %elt3 = extractelement <4 x i8> %a, i64 3 + + %add1 = add i8 %elt1, %elt0 + %add2 = add i8 %elt2, %add1 + %add3 = add i8 %elt3, %add2 + + ret i8 %add3 +} + +define i8 @reduction_v8i8(<8 x i8> %vec8) { +; GCN-LABEL: @reduction_v8i8( +; GCN-NEXT: entry: +; GCN-NEXT: [[ADD7:%.*]] = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> [[VEC8:%.*]]) +; GCN-NEXT: ret i8 [[ADD7]] +; +entry: + %elt0 = extractelement <8 x i8> %vec8, i64 0 + %elt1 = extractelement <8 x i8> %vec8, i64 1 + %elt2 = extractelement <8 x i8> %vec8, i64 2 + %elt3 = extractelement <8 x i8> %vec8, i64 3 + %elt4 = extractelement <8 x i8> %vec8, i64 4 + %elt5 = extractelement <8 x i8> %vec8, i64 5 + %elt6 = extractelement <8 x i8> %vec8, i64 6 + %elt7 = extractelement <8 x i8> %vec8, i64 7 + + %add1 = add i8 %elt1, %elt0 + %add2 = add i8 %elt2, %add1 + %add3 = add i8 %elt3, %add2 + %add4 = add i8 %elt4, %add3 + %add5 = add i8 %elt5, %add4 + %add6 = add i8 %elt6, %add5 + %add7 = add i8 %elt7, %add6 + + ret i8 %add7 +} + +define i8 @reduction_umin_v4i8(<4 x i8> %vec4) { +; GCN-LABEL: @reduction_umin_v4i8( +; GCN-NEXT: entry: +; GCN-NEXT: [[MIN3:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[VEC4:%.*]]) +; GCN-NEXT: ret i8 [[MIN3]] +; +entry: + %elt0 = extractelement <4 x i8> %vec4, i64 0 + %elt1 = extractelement <4 x i8> %vec4, i64 1 + %elt2 = extractelement <4 x i8> %vec4, i64 2 + %elt3 = extractelement <4 x i8> %vec4, i64 3 + + %cmp1 = icmp ult i8 %elt1, %elt0 + %min1 = select i1 %cmp1, i8 %elt1, i8 %elt0 + %cmp2 = icmp ult i8 %elt2, %min1 + %min2 = select i1 %cmp2, i8 %elt2, i8 %min1 + %cmp3 = icmp ult i8 %elt3, %min2 + %min3 = select i1 %cmp3, i8 %elt3, i8 %min2 + + ret i8 %min3 +} + +define i8 @reduction_icmp_v8i8(<8 x i8> %vec8) { +; GCN-LABEL: @reduction_icmp_v8i8( +; GCN-NEXT: entry: +; GCN-NEXT: [[MIN7:%.*]] = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> [[VEC8:%.*]]) +; GCN-NEXT: ret i8 [[MIN7]] +; +entry: + %elt0 = extractelement <8 x i8> %vec8, i64 0 + %elt1 = extractelement <8 x i8> %vec8, i64 1 + %elt2 = extractelement <8 x i8> %vec8, i64 2 + %elt3 = extractelement <8 x i8> %vec8, i64 3 + %elt4 = extractelement <8 x i8> %vec8, i64 4 + %elt5 = extractelement <8 x i8> %vec8, i64 5 + %elt6 = extractelement <8 x i8> %vec8, i64 6 + %elt7 = extractelement <8 x i8> %vec8, i64 7 + + %cmp0 = icmp ult i8 %elt1, %elt0 + %min1 = select i1 %cmp0, i8 %elt1, i8 %elt0 + %cmp1 = icmp ult i8 %elt2, %min1 + %min2 = select i1 %cmp1, i8 %elt2, i8 %min1 + %cmp2 = icmp ult i8 %elt3, %min2 + %min3 = select i1 %cmp2, i8 %elt3, i8 %min2 + + %cmp3 = icmp ult i8 %elt4, %min3 + %min4 = select i1 %cmp3, i8 %elt4, i8 %min3 + %cmp4 = icmp ult i8 %elt5, %min4 + %min5 = select i1 %cmp4, i8 %elt5, i8 %min4 + + %cmp5 = icmp ult i8 %elt6, %min5 + %min6 = select i1 %cmp5, i8 %elt6, i8 %min5 + %cmp6 = icmp ult i8 %elt7, %min6 + %min7 = select i1 %cmp6, i8 %elt7, i8 %min6 + + ret i8 %min7 +} + +define i8 @reduction_smin_v16i8(<16 x i8> %vec16) { +; GCN-LABEL: @reduction_smin_v16i8( +; GCN-NEXT: entry: +; GCN-NEXT: [[MIN15:%.*]] = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> [[VEC16:%.*]]) +; GCN-NEXT: ret i8 [[MIN15]] +; +entry: + %elt0 = extractelement <16 x i8> %vec16, i64 0 + %elt1 = extractelement <16 x i8> %vec16, i64 1 + %elt2 = extractelement <16 x i8> %vec16, i64 2 + %elt3 = extractelement <16 x i8> %vec16, i64 3 + %elt4 = extractelement <16 x i8> %vec16, i64 4 + %elt5 = extractelement <16 x i8> %vec16, i64 5 + %elt6 = extractelement <16 x i8> %vec16, i64 6 + %elt7 = extractelement <16 x i8> %vec16, i64 7 + + %elt8 = extractelement <16 x i8> %vec16, i64 8 + %elt9 = extractelement <16 x i8> %vec16, i64 9 + %elt10 = extractelement <16 x i8> %vec16, i64 10 + %elt11 = extractelement <16 x i8> %vec16, i64 11 + %elt12 = extractelement <16 x i8> %vec16, i64 12 + %elt13 = extractelement <16 x i8> %vec16, i64 13 + %elt14 = extractelement <16 x i8> %vec16, i64 14 + %elt15 = extractelement <16 x i8> %vec16, i64 15 + + %cmp0 = icmp slt i8 %elt1, %elt0 + %min1 = select i1 %cmp0, i8 %elt1, i8 %elt0 + %cmp1 = icmp slt i8 %elt2, %min1 + %min2 = select i1 %cmp1, i8 %elt2, i8 %min1 + %cmp2 = icmp slt i8 %elt3, %min2 + %min3 = select i1 %cmp2, i8 %elt3, i8 %min2 + + %cmp3 = icmp slt i8 %elt4, %min3 + %min4 = select i1 %cmp3, i8 %elt4, i8 %min3 + %cmp4 = icmp slt i8 %elt5, %min4 + %min5 = select i1 %cmp4, i8 %elt5, i8 %min4 + + %cmp5 = icmp slt i8 %elt6, %min5 + %min6 = select i1 %cmp5, i8 %elt6, i8 %min5 + %cmp6 = icmp slt i8 %elt7, %min6 + %min7 = select i1 %cmp6, i8 %elt7, i8 %min6 + + %cmp7 = icmp slt i8 %elt8, %min7 + %min8 = select i1 %cmp7, i8 %elt8, i8 %min7 + %cmp8 = icmp slt i8 %elt9, %min8 + %min9 = select i1 %cmp8, i8 %elt9, i8 %min8 + + %cmp9 = icmp slt i8 %elt10, %min9 + %min10 = select i1 %cmp9, i8 %elt10, i8 %min9 + %cmp10 = icmp slt i8 %elt11, %min10 + %min11 = select i1 %cmp10, i8 %elt11, i8 %min10 + + %cmp11 = icmp slt i8 %elt12, %min11 + %min12 = select i1 %cmp11, i8 %elt12, i8 %min11 + %cmp12 = icmp slt i8 %elt13, %min12 + %min13 = select i1 %cmp12, i8 %elt13, i8 %min12 + + %cmp13 = icmp slt i8 %elt14, %min13 + %min14 = select i1 %cmp13, i8 %elt14, i8 %min13 + %cmp14 = icmp slt i8 %elt15, %min14 + %min15 = select i1 %cmp14, i8 %elt15, i8 %min14 + + + ret i8 %min15 +} + +define i8 @reduction_umax_v4i8(<4 x i8> %vec4) { +; GCN-LABEL: @reduction_umax_v4i8( +; GCN-NEXT: entry: +; GCN-NEXT: [[MAX3:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[VEC4:%.*]]) +; GCN-NEXT: ret i8 [[MAX3]] +; +entry: + %elt0 = extractelement <4 x i8> %vec4, i64 0 + %elt1 = extractelement <4 x i8> %vec4, i64 1 + %elt2 = extractelement <4 x i8> %vec4, i64 2 + %elt3 = extractelement <4 x i8> %vec4, i64 3 + + %cmp1 = icmp ugt i8 %elt1, %elt0 + %max1 = select i1 %cmp1, i8 %elt1, i8 %elt0 + %cmp2 = icmp ugt i8 %elt2, %max1 + %max2 = select i1 %cmp2, i8 %elt2, i8 %max1 + %cmp3 = icmp ugt i8 %elt3, %max2 + %max3 = select i1 %cmp3, i8 %elt3, i8 %max2 + + ret i8 %max3 +} + +define i8 @reduction_smax_v4i8(<4 x i8> %vec4) { +; GCN-LABEL: @reduction_smax_v4i8( +; GCN-NEXT: entry: +; GCN-NEXT: [[MAX3:%.*]] = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> [[VEC4:%.*]]) +; GCN-NEXT: ret i8 [[MAX3]] +; +entry: + %elt0 = extractelement <4 x i8> %vec4, i64 0 + %elt1 = extractelement <4 x i8> %vec4, i64 1 + %elt2 = extractelement <4 x i8> %vec4, i64 2 + %elt3 = extractelement <4 x i8> %vec4, i64 3 + + %cmp1 = icmp sgt i8 %elt1, %elt0 + %max1 = select i1 %cmp1, i8 %elt1, i8 %elt0 + %cmp2 = icmp sgt i8 %elt2, %max1 + %max2 = select i1 %cmp2, i8 %elt2, i8 %max1 + %cmp3 = icmp sgt i8 %elt3, %max2 + %max3 = select i1 %cmp3, i8 %elt3, i8 %max2 + + ret i8 %max3 +} diff --git a/llvm/test/Transforms/SLPVectorizer/X86/const-reduced-vals-resized.ll b/llvm/test/Transforms/SLPVectorizer/X86/const-reduced-vals-resized.ll deleted file mode 100644 index dc8c1c420bf80..0000000000000 --- a/llvm/test/Transforms/SLPVectorizer/X86/const-reduced-vals-resized.ll +++ /dev/null @@ -1,20 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux < %s | FileCheck %s - -define i32 @test() { -; CHECK-LABEL: define i32 @test() { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> zeroinitializer) -; CHECK-NEXT: ret i32 [[TMP0]] -; -entry: - %cond = zext i1 false to i32 - %cond258 = zext i1 false to i32 - %cond283 = zext i1 false to i32 - %cond308 = zext i1 false to i32 - %conv685 = or i32 %cond308, %cond - %conv710 = or i32 %conv685, %cond258 - %conv735 = or i32 %conv710, %cond283 - %conv791 = or i32 %conv735, %cond - ret i32 %conv791 -} diff --git a/llvm/test/Transforms/SROA/heterogeneous-poison.ll b/llvm/test/Transforms/SROA/heterogeneous-poison.ll new file mode 100644 index 0000000000000..b4d1e80833c11 --- /dev/null +++ b/llvm/test/Transforms/SROA/heterogeneous-poison.ll @@ -0,0 +1,231 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes='sroa' -S < %s | FileCheck %s + +source_filename = "test/Transforms/SROA/heterogeneous-poison.ll" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" + +%struct.pair = type { i32, i32 } + +define i32 @t1() !dbg !9 { +; CHECK-LABEL: define i32 @t1( +; CHECK-SAME: ) !dbg [[DBG9:![0-9]+]] { +; CHECK-NEXT: #dbg_value(i32 2, [[META13:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[META15:![0-9]+]]) +; CHECK-NEXT: ret i32 2 +; + %local = alloca i32, align 4 + #dbg_declare(ptr %local, !13, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), !15) + store i32 2, ptr %local, align 4 + %read = load i32, ptr %local, align 4 + ret i32 %read +} + +define i32 @t2(i1 %cond) !dbg !16 { +; CHECK-LABEL: define i32 @t2( +; CHECK-SAME: i1 [[COND:%.*]]) !dbg [[DBG16:![0-9]+]] { +; CHECK-NEXT: br i1 [[COND]], label [[THEN:%.*]], label [[ELSE:%.*]] +; CHECK: then: +; CHECK-NEXT: #dbg_value(i32 42, [[META17:![0-9]+]], !DIExpression(DIOpArg(0, i32)), [[META18:![0-9]+]]) +; CHECK-NEXT: br label [[JOIN:%.*]] +; CHECK: else: +; CHECK-NEXT: #dbg_value(i32 2, [[META17]], !DIExpression(DIOpArg(0, i32)), [[META18]]) +; CHECK-NEXT: br label [[JOIN]] +; CHECK: join: +; CHECK-NEXT: [[LOCAL_0:%.*]] = phi i32 [ 42, [[THEN]] ], [ 2, [[ELSE]] ] +; CHECK-NEXT: #dbg_value(i32 [[LOCAL_0]], [[META17]], !DIExpression(DIOpArg(0, i32)), [[META18]]) +; CHECK-NEXT: ret i32 [[LOCAL_0]] +; + %local = alloca i32, align 4 + #dbg_declare(ptr %local, !17, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), !18) + br i1 %cond, label %then, label %else + +then: ; preds = %0 + store i32 42, ptr %local, align 4 + br label %join + +else: ; preds = %0 + store i32 2, ptr %local, align 4 + br label %join + +join: ; preds = %else, %then + %retval = load i32, ptr %local, align 4 + ret i32 %retval +} + +define void @t3() !dbg !19 { +; CHECK-LABEL: define void @t3( +; CHECK-SAME: ) !dbg [[DBG19:![0-9]+]] { +; CHECK-NEXT: #dbg_value(i32 42, [[META20:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpFragment(0, 32)), [[META25:![0-9]+]]) +; CHECK-NEXT: #dbg_value(i32 43, [[META20]], !DIExpression(DIOpArg(0, i32), DIOpFragment(32, 32)), [[META25]]) +; CHECK-NEXT: ret void +; + %local = alloca %struct.pair, align 4 + #dbg_declare(ptr %local, !20, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(%struct.pair)), !25) + %first = getelementptr inbounds %struct.pair, ptr %local, i32 0, i32 0 + store i32 42, ptr %first, align 4 + %second = getelementptr inbounds %struct.pair, ptr %local, i32 0, i32 1 + store i32 43, ptr %second, align 4 + ret void +} + +define i32 @t4() !dbg !26 { + ;; FIXME(diexpression-poison): We could probably preserve debug info for the dbg.value here if + ;; necessary. Check that we at least do something sensible with it for now. +; CHECK-LABEL: define i32 @t4( +; CHECK-SAME: ) !dbg [[DBG26:![0-9]+]] { +; CHECK-NEXT: #dbg_value(ptr poison, [[META27:![0-9]+]], !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), [[META28:![0-9]+]]) +; CHECK-NEXT: ret i32 42 +; + %local = alloca i32, align 4 + #dbg_value(ptr %local, !27, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i32)), !28) + store i32 42, ptr %local, align 4 + %loaded = load i32, ptr %local, align 4 + ret i32 %loaded +} + +define i16 @t5(i1 %cond) !dbg !29 { + ;; Verify that we still convert if the new value doesn't cover the entire size + ;; of the variable !30. This is something that old-style DIExpressions don't + ;; support. +; CHECK-LABEL: define i16 @t5( +; CHECK-SAME: i1 [[COND:%.*]]) !dbg [[DBG29:![0-9]+]] { +; CHECK-NEXT: br i1 [[COND]], label [[THEN:%.*]], label [[ELSE:%.*]] +; CHECK: then: +; CHECK-NEXT: #dbg_value(i16 42, [[META30:![0-9]+]], !DIExpression(DIOpArg(0, i16), DIOpSExt(i32)), [[META31:![0-9]+]]) +; CHECK-NEXT: br label [[JOIN:%.*]] +; CHECK: else: +; CHECK-NEXT: #dbg_value(i16 43, [[META30]], !DIExpression(DIOpArg(0, i16), DIOpSExt(i32)), [[META31]]) +; CHECK-NEXT: br label [[JOIN]] +; CHECK: join: +; CHECK-NEXT: [[LOCAL_0:%.*]] = phi i16 [ 42, [[THEN]] ], [ 43, [[ELSE]] ] +; CHECK-NEXT: #dbg_value(i16 [[LOCAL_0]], [[META30]], !DIExpression(DIOpArg(0, i16), DIOpSExt(i32)), [[META31]]) +; CHECK-NEXT: ret i16 [[LOCAL_0]] +; + %local = alloca i16, align 4 + #dbg_declare(ptr %local, !30, !DIExpression(DIOpArg(0, ptr addrspace(5)), DIOpDeref(i16), DIOpSExt(i32)), !31) + br i1 %cond, label %then, label %else + +then: ; preds = %0 + store i16 42, ptr %local, align 4 + br label %join + +else: ; preds = %0 + store i16 43, ptr %local, align 4 + br label %join + +join: ; preds = %else, %then + %loaded = load i16, ptr %local, align 4 + ret i16 %loaded +} + +%struct.pair.pair = type { %struct.pair, %struct.pair } + +define void @t6() !dbg !32 { +; CHECK-LABEL: define void @t6( +; CHECK-SAME: ) !dbg [[DBG32:![0-9]+]] { +; CHECK-NEXT: #dbg_value(i32 0, [[META33:![0-9]+]], !DIExpression(DIOpArg(0, i32), DIOpFragment(0, 32)), [[META38:![0-9]+]]) +; CHECK-NEXT: #dbg_value(i32 1, [[META33]], !DIExpression(DIOpArg(0, i32), DIOpFragment(32, 32)), [[META38]]) +; CHECK-NEXT: #dbg_value(i32 2, [[META33]], !DIExpression(DIOpArg(0, i32), DIOpFragment(64, 32)), [[META38]]) +; CHECK-NEXT: #dbg_value(i32 3, [[META33]], !DIExpression(DIOpArg(0, i32), DIOpFragment(96, 32)), [[META38]]) +; CHECK-NEXT: ret void +; + %first = alloca %struct.pair, align 4 + %second = alloca %struct.pair, align 4 + #dbg_declare(ptr %first, !37, !DIExpression(DIOpArg(0, ptr), DIOpDeref(%struct.pair), DIOpFragment(0, 64)), !38) + #dbg_declare(ptr %second, !37, !DIExpression(DIOpArg(0, ptr), DIOpDeref(%struct.pair), DIOpFragment(64, 64)), !38) + %f0_ptr = getelementptr inbounds %struct.pair, ptr %first, i32 0, i32 0 + store i32 0, ptr %f0_ptr, align 4 + %f1_ptr = getelementptr inbounds %struct.pair, ptr %first, i32 0, i32 1 + store i32 1, ptr %f1_ptr, align 4 + %f2_ptr = getelementptr inbounds %struct.pair, ptr %second, i32 0, i32 0 + store i32 2, ptr %f2_ptr, align 4 + %f3_ptr = getelementptr inbounds %struct.pair, ptr %second, i32 0, i32 1 + store i32 3, ptr %f3_ptr, align 4 + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #0 + +attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7} +!llvm.ident = !{!8} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang 19", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "t.cpp", directory: "/") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 8, !"PIC Level", i32 2} +!6 = !{i32 7, !"PIE Level", i32 2} +!7 = !{i32 7, !"uwtable", i32 2} +!8 = !{!"clang 19"} +!9 = distinct !DISubprogram(name: "t1", linkageName: "t1", scope: !1, file: !1, line: 7, type: !10, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12) +!10 = !DISubroutineType(types: !11) +!11 = !{null} +!12 = !{!13} +!13 = !DILocalVariable(name: "local", scope: !9, file: !1, line: 8, type: !14) +!14 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!15 = !DILocation(line: 8, column: 3, scope: !9) +!16 = distinct !DISubprogram(name: "t2", linkageName: "t2", scope: !1, file: !1, line: 7, type: !10, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12) +!17 = !DILocalVariable(name: "local", scope: !16, file: !1, line: 1, type: !14) +!18 = !DILocation(line: 1, column: 1, scope: !16) +!19 = distinct !DISubprogram(name: "t3", linkageName: "t3", scope: !1, file: !1, line: 7, type: !10, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12) +!20 = !DILocalVariable(name: "local", scope: !19, file: !1, line: 1, type: !21) +!21 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "pair", file: !1, line: 2, size: 64, flags: DIFlagTypePassByValue, elements: !22, identifier: "pair") +!22 = !{!23, !24} +!23 = !DIDerivedType(tag: DW_TAG_member, name: "s1", scope: !21, file: !1, line: 3, baseType: !14, size: 32) +!24 = !DIDerivedType(tag: DW_TAG_member, name: "s2", scope: !21, file: !1, line: 4, baseType: !14, size: 32, offset: 32) +!25 = !DILocation(line: 1, column: 1, scope: !19) +!26 = distinct !DISubprogram(name: "t4", linkageName: "t4", scope: !1, file: !1, line: 7, type: !10, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12) +!27 = !DILocalVariable(name: "local", scope: !26, file: !1, line: 1, type: !14) +!28 = !DILocation(line: 1, column: 1, scope: !26) +!29 = distinct !DISubprogram(name: "t5", linkageName: "t5", scope: !1, file: !1, line: 7, type: !10, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12) +!30 = !DILocalVariable(name: "local_i16", scope: !29, file: !1, line: 1, type: !14) +!31 = !DILocation(line: 1, column: 1, scope: !29) +!32 = distinct !DISubprogram(name: "t6", linkageName: "t56", scope: !1, file: !1, line: 7, type: !10, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12) +!33 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "pair_pair", file: !1, line: 2, size: 128, flags: DIFlagTypePassByValue, elements: !36, identifier: "pair_pair") +!34 = !DIDerivedType(tag: DW_TAG_member, name: "s1", scope: !33, file: !1, line: 3, baseType: !21, size: 64) +!35 = !DIDerivedType(tag: DW_TAG_member, name: "s2", scope: !33, file: !1, line: 4, baseType: !21, size: 64, offset: 64) +!36 = !{!34, !35} +!37 = !DILocalVariable(name: "local", scope: !32, file: !1, line: 1, type: !33) +!38 = !DILocation(line: 1, column: 1, scope: !32) + +;. +; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: [[META1:![0-9]+]], producer: "clang 19", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +; CHECK: [[META1]] = !DIFile(filename: "{{.*}}t.cpp", directory: {{.*}}) +; CHECK: [[DBG9]] = distinct !DISubprogram(name: "t1", linkageName: "t1", scope: [[META1]], file: [[META1]], line: 7, type: [[META10:![0-9]+]], scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META12:![0-9]+]]) +; CHECK: [[META10]] = !DISubroutineType(types: [[META11:![0-9]+]]) +; CHECK: [[META11]] = !{null} +; CHECK: [[META12]] = !{[[META13]]} +; CHECK: [[META13]] = !DILocalVariable(name: "local", scope: [[DBG9]], file: [[META1]], line: 8, type: [[META14:![0-9]+]]) +; CHECK: [[META14]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +; CHECK: [[META15]] = !DILocation(line: 0, scope: [[DBG9]]) +; CHECK: [[DBG16]] = distinct !DISubprogram(name: "t2", linkageName: "t2", scope: [[META1]], file: [[META1]], line: 7, type: [[META10]], scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META12]]) +; CHECK: [[META17]] = !DILocalVariable(name: "local", scope: [[DBG16]], file: [[META1]], line: 1, type: [[META14]]) +; CHECK: [[META18]] = !DILocation(line: 0, scope: [[DBG16]]) +; CHECK: [[DBG19]] = distinct !DISubprogram(name: "t3", linkageName: "t3", scope: [[META1]], file: [[META1]], line: 7, type: [[META10]], scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META12]]) +; CHECK: [[META20]] = !DILocalVariable(name: "local", scope: [[DBG19]], file: [[META1]], line: 1, type: [[META21:![0-9]+]]) +; CHECK: [[META21]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "pair", file: [[META1]], line: 2, size: 64, flags: DIFlagTypePassByValue, elements: [[META22:![0-9]+]], identifier: "pair") +; CHECK: [[META22]] = !{[[META23:![0-9]+]], [[META24:![0-9]+]]} +; CHECK: [[META23]] = !DIDerivedType(tag: DW_TAG_member, name: "s1", scope: [[META21]], file: [[META1]], line: 3, baseType: [[META14]], size: 32) +; CHECK: [[META24]] = !DIDerivedType(tag: DW_TAG_member, name: "s2", scope: [[META21]], file: [[META1]], line: 4, baseType: [[META14]], size: 32, offset: 32) +; CHECK: [[META25]] = !DILocation(line: 0, scope: [[DBG19]]) +; CHECK: [[DBG26]] = distinct !DISubprogram(name: "t4", linkageName: "t4", scope: [[META1]], file: [[META1]], line: 7, type: [[META10]], scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META12]]) +; CHECK: [[META27]] = !DILocalVariable(name: "local", scope: [[DBG26]], file: [[META1]], line: 1, type: [[META14]]) +; CHECK: [[META28]] = !DILocation(line: 1, column: 1, scope: [[DBG26]]) +; CHECK: [[DBG29]] = distinct !DISubprogram(name: "t5", linkageName: "t5", scope: [[META1]], file: [[META1]], line: 7, type: [[META10]], scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META12]]) +; CHECK: [[META30]] = !DILocalVariable(name: "local_i16", scope: [[DBG29]], file: [[META1]], line: 1, type: [[META14]]) +; CHECK: [[META31]] = !DILocation(line: 0, scope: [[DBG29]]) +; CHECK: [[DBG32]] = distinct !DISubprogram(name: "t6", linkageName: "t56", scope: [[META1]], file: [[META1]], line: 7, type: [[META10]], scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META12]]) +; CHECK: [[META33]] = !DILocalVariable(name: "local", scope: [[DBG32]], file: [[META1]], line: 1, type: [[META34:![0-9]+]]) +; CHECK: [[META34]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "pair_pair", file: [[META1]], line: 2, size: 128, flags: DIFlagTypePassByValue, elements: [[META35:![0-9]+]], identifier: "pair_pair") +; CHECK: [[META35]] = !{[[META36:![0-9]+]], [[META37:![0-9]+]]} +; CHECK: [[META36]] = !DIDerivedType(tag: DW_TAG_member, name: "s1", scope: [[META34]], file: [[META1]], line: 3, baseType: [[META21]], size: 64) +; CHECK: [[META37]] = !DIDerivedType(tag: DW_TAG_member, name: "s2", scope: [[META34]], file: [[META1]], line: 4, baseType: [[META21]], size: 64, offset: 64) +; CHECK: [[META38]] = !DILocation(line: 0, scope: [[DBG32]]) +;. diff --git a/llvm/test/Transforms/ThinLTOBitcodeWriter/cfi-icall-static-inline-asm.ll b/llvm/test/Transforms/ThinLTOBitcodeWriter/cfi-icall-static-inline-asm.ll index d8ebae17d4693..e1af9e4aa6d1a 100644 --- a/llvm/test/Transforms/ThinLTOBitcodeWriter/cfi-icall-static-inline-asm.ll +++ b/llvm/test/Transforms/ThinLTOBitcodeWriter/cfi-icall-static-inline-asm.ll @@ -1,5 +1,5 @@ ; REQUIRES: x86-registered-target -; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o - %s | llvm-modextract -b -n 0 -o - | llvm-dis | FileCheck %s +; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o - %s | llvm-modextract -b -n 0 -o - | llvm-dis | FileCheck %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/ThinLTOBitcodeWriter/filter-alias.ll b/llvm/test/Transforms/ThinLTOBitcodeWriter/filter-alias.ll index dd3e1612cb2d8..31ad3061112bb 100644 --- a/llvm/test/Transforms/ThinLTOBitcodeWriter/filter-alias.ll +++ b/llvm/test/Transforms/ThinLTOBitcodeWriter/filter-alias.ll @@ -1,6 +1,6 @@ -; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s -; RUN: llvm-modextract -n 0 -o - %t | llvm-dis | FileCheck --check-prefix=CHECK0 %s -; RUN: llvm-modextract -n 1 -o - %t | llvm-dis | FileCheck --check-prefix=CHECK1 %s +; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s +; RUN: llvm-modextract -n 0 -o - %t | llvm-dis | FileCheck --check-prefix=CHECK0 %s +; RUN: llvm-modextract -n 1 -o - %t | llvm-dis | FileCheck --check-prefix=CHECK1 %s ; CHECK0-NOT: @{{.*}}anon{{.*}}= ; CHECK0: @al = external global ptr ; CHECK0-NOT: @{{.*}}anon{{.*}}= diff --git a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-dsolocal.ll b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-dsolocal.ll index 4664a6f7b15ef..50d9d6935244b 100644 --- a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-dsolocal.ll +++ b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-dsolocal.ll @@ -1,8 +1,8 @@ -; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s -; RUN: llvm-modextract -b -n 0 -o %t0.bc %t -; RUN: llvm-modextract -b -n 1 -o %t1.bc %t -; RUN: llvm-dis -o - %t0.bc | FileCheck --check-prefix=M0 %s -; RUN: llvm-dis -o - %t1.bc | FileCheck --check-prefix=M1 %s +; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s +; RUN: llvm-modextract -b -n 0 -o %t0.bc %t +; RUN: llvm-modextract -b -n 1 -o %t1.bc %t +; RUN: llvm-dis -o - %t0.bc | FileCheck --check-prefix=M0 %s +; RUN: llvm-dis -o - %t1.bc | FileCheck --check-prefix=M1 %s ; M0: @default = external constant [1 x i8] ; M0: @hidden = external hidden constant [1 x i8] diff --git a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal1.ll b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal1.ll index b9d85e988dbb0..cecd98c440682 100644 --- a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal1.ll +++ b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal1.ll @@ -1,11 +1,11 @@ -; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s -; RUN: llvm-modextract -b -n 0 -o %t0 %t -; RUN: llvm-modextract -b -n 1 -o %t1 %t +; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s +; RUN: llvm-modextract -b -n 0 -o %t0 %t +; RUN: llvm-modextract -b -n 1 -o %t1 %t ; RUN: not llvm-modextract -b -n 2 -o - %t 2>&1 | FileCheck --check-prefix=ERROR %s -; RUN: llvm-dis -o - %t0 | FileCheck --check-prefix=M0 %s -; RUN: llvm-dis -o - %t1 | FileCheck --check-prefix=M1 %s -; RUN: llvm-bcanalyzer -dump %t0 | FileCheck --check-prefix=BCA0 %s -; RUN: llvm-bcanalyzer -dump %t1 | FileCheck --check-prefix=BCA1 %s +; RUN: llvm-dis -o - %t0 | FileCheck --check-prefix=M0 %s +; RUN: llvm-dis -o - %t1 | FileCheck --check-prefix=M1 %s +; RUN: llvm-bcanalyzer -dump %t0 | FileCheck --check-prefix=BCA0 %s +; RUN: llvm-bcanalyzer -dump %t1 | FileCheck --check-prefix=BCA1 %s ; ERROR: llvm-modextract: error: module index out of range; bitcode file contains 2 module(s) diff --git a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll index df571b3a30017..e369e499c9d14 100644 --- a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll +++ b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll @@ -1,12 +1,12 @@ ; REQUIRES: x86-registered-target -; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s -; RUN: llvm-modextract -b -n 0 -o %t0 %t -; RUN: llvm-modextract -b -n 1 -o %t1 %t +; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s +; RUN: llvm-modextract -b -n 0 -o %t0 %t +; RUN: llvm-modextract -b -n 1 -o %t1 %t ; RUN: not llvm-modextract -b -n 2 -o - %t 2>&1 | FileCheck --check-prefix=ERROR %s -; RUN: llvm-dis -o - %t0 | FileCheck --check-prefix=M0 %s -; RUN: llvm-dis -o - %t1 | FileCheck --check-prefix=M1 %s -; RUN: llvm-bcanalyzer -dump %t0 | FileCheck --check-prefix=BCA0 %s -; RUN: llvm-bcanalyzer -dump %t1 | FileCheck --check-prefix=BCA1 %s +; RUN: llvm-dis -o - %t0 | FileCheck --check-prefix=M0 %s +; RUN: llvm-dis -o - %t1 | FileCheck --check-prefix=M1 %s +; RUN: llvm-bcanalyzer -dump %t0 | FileCheck --check-prefix=BCA0 %s +; RUN: llvm-bcanalyzer -dump %t1 | FileCheck --check-prefix=BCA1 %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-used.ll b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-used.ll index fbaafb3905118..16de49e9198f9 100644 --- a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-used.ll +++ b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-used.ll @@ -1,11 +1,11 @@ ; Test to ensure that @llvm[.compiler].used is cloned to the split module for ; any globals whose defs were cloned to that module. -; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s -; RUN: llvm-modextract -b -n 0 -o %t0.bc %t -; RUN: llvm-modextract -b -n 1 -o %t1.bc %t -; RUN: llvm-dis -o - %t0.bc | FileCheck --check-prefix=M0 %s -; RUN: llvm-dis -o - %t1.bc | FileCheck --check-prefix=M1 %s +; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s +; RUN: llvm-modextract -b -n 0 -o %t0.bc %t +; RUN: llvm-modextract -b -n 1 -o %t1.bc %t +; RUN: llvm-dis -o - %t0.bc | FileCheck --check-prefix=M0 %s +; RUN: llvm-dis -o - %t1.bc | FileCheck --check-prefix=M1 %s ; M0: @g1 = external global i8 ; M0: @g2 = external global i8 diff --git a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc-internal.ll b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc-internal.ll index 60fa228c73603..66a28006024f2 100644 --- a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc-internal.ll +++ b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc-internal.ll @@ -1,7 +1,7 @@ ; REQUIRES: x86-registered-target -; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s -; RUN: llvm-modextract -b -n 0 -o - %t | llvm-dis | FileCheck --check-prefix=M0 %s -; RUN: llvm-modextract -b -n 1 -o - %t | llvm-dis | FileCheck --check-prefix=M1 %s +; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s +; RUN: llvm-modextract -b -n 0 -o - %t | llvm-dis | FileCheck --check-prefix=M0 %s +; RUN: llvm-modextract -b -n 1 -o - %t | llvm-dis | FileCheck --check-prefix=M1 %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll index 47c14be85c076..ea4f9351e6016 100644 --- a/llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll +++ b/llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll @@ -1,6 +1,6 @@ -; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s -; RUN: llvm-modextract -b -n 0 -o - %t | llvm-dis | FileCheck --check-prefix=M0 %s -; RUN: llvm-modextract -b -n 1 -o - %t | llvm-dis | FileCheck --check-prefix=M1 %s +; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t %s +; RUN: llvm-modextract -b -n 0 -o - %t | llvm-dis | FileCheck --check-prefix=M0 %s +; RUN: llvm-modextract -b -n 1 -o - %t | llvm-dis | FileCheck --check-prefix=M1 %s ; M0: @g = external constant [10 x ptr]{{$}} ; M1: @g = constant [10 x ptr] diff --git a/llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll b/llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll index f4aee898ec838..7f941a3649298 100644 --- a/llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll +++ b/llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll @@ -1229,6 +1229,8 @@ define @frem_nxv1f32_allonesmask( %x, f ; NO-VEC-COMBINE-NEXT: [[TMP4:%.*]] = call @llvm.vp.fadd.nxv1f32( [[X:%.*]], [[TMP3]], [[MASK]], i32 [[EVL]]) ; NO-VEC-COMBINE-NEXT: ret [[TMP4]] ; + + %splat = insertelement poison, i1 -1, i32 0 %mask = shufflevector %splat, poison, zeroinitializer %1 = insertelement poison, float %y, i64 0 @@ -1272,6 +1274,11 @@ define @fdiv_nxv1f32_allonesmask_knownvl( @llvm.vp.fadd.nxv1f32( [[X:%.*]], [[TMP3]], [[MASK]], i32 4) ; NO-VEC-COMBINE-NEXT: ret [[TMP4]] ; + + + + + %splat = insertelement poison, i1 -1, i32 0 %mask = shufflevector %splat, poison, zeroinitializer %1 = insertelement poison, float %y, i64 0 @@ -1315,6 +1322,8 @@ define @frem_nxv1f32_allonesmask_knownvl( @llvm.vp.fadd.nxv1f32( [[X:%.*]], [[TMP3]], [[MASK]], i32 4) ; NO-VEC-COMBINE-NEXT: ret [[TMP4]] ; + + %splat = insertelement poison, i1 -1, i32 0 %mask = shufflevector %splat, poison, zeroinitializer %1 = insertelement poison, float %y, i64 0 diff --git a/llvm/test/Verifier/amdgpu-intrinsics.ll b/llvm/test/Verifier/amdgpu-intrinsics.ll new file mode 100644 index 0000000000000..b774c4cb12fbd --- /dev/null +++ b/llvm/test/Verifier/amdgpu-intrinsics.ll @@ -0,0 +1,66 @@ +; RUN: not llvm-as < %s 2>&1 | FileCheck %s + +; ---------- i32 metadata ------------------------------------------------------ +; CHECK: global load/store intrinsics require that the last argument is a metadata string +; CHECK-NEXT: call <4 x i32> @llvm.amdgcn.global.load.b128({{.*}}) +; CHECK-NEXT: metadata i32 1 +define <4 x i32> @global_load_b128_00(ptr addrspace(1) %addr) { +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !3) + ret <4 x i32> %data +} + +; CHECK: global load/store intrinsics require that the last argument is a metadata string +; CHECK-NEXT: call void @llvm.amdgcn.global.store.b128({{.*}}) +; CHECK-NEXT: metadata i32 1 +define void @global_store_b128_00(ptr addrspace(1) %addr, <4 x i32> %data) { +entry: + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %addr, <4 x i32> %data, metadata !3) + ret void +} + +; ---------- non-tuple metadata ------------------------------------------------ +; CHECK: global load/store intrinsics require that the last argument is a metadata string +; CHECK-NEXT: call <4 x i32> @llvm.amdgcn.global.load.b128({{.*}}) +; CHECK-NEXT: metadata !0 +define <4 x i32> @global_load_b128_01(ptr addrspace(1) %addr) { +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !0) + ret <4 x i32> %data +} + +; CHECK: global load/store intrinsics require that the last argument is a metadata string +; CHECK-NEXT: call void @llvm.amdgcn.global.store.b128({{.*}}) +; CHECK-NEXT: metadata !0 +define void @global_store_b128_01(ptr addrspace(1) %addr, <4 x i32> %data) { +entry: + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %addr, <4 x i32> %data, metadata !0) + ret void +} + +; ---------- invalid string metadata ------------------------------------------- +; CHECK: 'wave' is not a valid scope for global load/store intrinsics +; CHECK-NEXT: call <4 x i32> @llvm.amdgcn.global.load.b128({{.*}}) +; CHECK-NEXT: metadata !2 +define <4 x i32> @global_load_b128_02(ptr addrspace(1) %addr) { +entry: + %data = call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) %addr, metadata !2) + ret <4 x i32> %data +} + +; CHECK: 'wave' is not a valid scope for global load/store intrinsics +; CHECK-NEXT: call void @llvm.amdgcn.global.store.b128({{.*}}) +; CHECK-NEXT: metadata !2 +define void @global_store_b128_02(ptr addrspace(1) %addr, <4 x i32> %data) { +entry: + call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) %addr, <4 x i32> %data, metadata !2) + ret void +} + + +!0 = !{!1} +!1 = !{!""} + +!2 = !{!"wave"} + +!3 = !{i32 1} diff --git a/llvm/test/Verifier/diderivedtype-address-space-atomic-type.ll b/llvm/test/Verifier/diderivedtype-address-space-atomic-type.ll index f7926ed949464..6ccd691d87797 100644 --- a/llvm/test/Verifier/diderivedtype-address-space-atomic-type.ll +++ b/llvm/test/Verifier/diderivedtype-address-space-atomic-type.ll @@ -3,4 +3,4 @@ !named = !{!0, !1} !0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) ; CHECK: DWARF address space only applies to pointer or reference types -!1 = !DIDerivedType(tag: DW_TAG_atomic_type, baseType: !0, size: 32, align: 32, dwarfAddressSpace: 1) +!1 = !DIDerivedType(tag: DW_TAG_atomic_type, baseType: !0, size: 32, align: 32, addressSpace: 1) diff --git a/llvm/test/Verifier/diderivedtype-address-space-const-type.ll b/llvm/test/Verifier/diderivedtype-address-space-const-type.ll index deba639438167..ffd6c93b6f680 100644 --- a/llvm/test/Verifier/diderivedtype-address-space-const-type.ll +++ b/llvm/test/Verifier/diderivedtype-address-space-const-type.ll @@ -3,4 +3,4 @@ !named = !{!0, !1} !0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) ; CHECK: DWARF address space only applies to pointer or reference types -!1 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !0, size: 32, align: 32, dwarfAddressSpace: 1) +!1 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !0, size: 32, align: 32, addressSpace: 1) diff --git a/llvm/test/Verifier/diderivedtype-address-space-friend.ll b/llvm/test/Verifier/diderivedtype-address-space-friend.ll index d3d3df47ed282..2ff72f3bf518e 100644 --- a/llvm/test/Verifier/diderivedtype-address-space-friend.ll +++ b/llvm/test/Verifier/diderivedtype-address-space-friend.ll @@ -3,4 +3,4 @@ !named = !{!0, !1} !0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) ; CHECK: DWARF address space only applies to pointer or reference types -!1 = !DIDerivedType(tag: DW_TAG_friend, baseType: !0, size: 32, align: 32, dwarfAddressSpace: 1) +!1 = !DIDerivedType(tag: DW_TAG_friend, baseType: !0, size: 32, align: 32, addressSpace: 1) diff --git a/llvm/test/Verifier/diderivedtype-address-space-inheritance.ll b/llvm/test/Verifier/diderivedtype-address-space-inheritance.ll index 2020f030d7e87..9347e288e6008 100644 --- a/llvm/test/Verifier/diderivedtype-address-space-inheritance.ll +++ b/llvm/test/Verifier/diderivedtype-address-space-inheritance.ll @@ -3,4 +3,4 @@ !named = !{!0, !1} !0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) ; CHECK: DWARF address space only applies to pointer or reference types -!1 = !DIDerivedType(tag: DW_TAG_inheritance, baseType: !0, size: 32, align: 32, dwarfAddressSpace: 1) +!1 = !DIDerivedType(tag: DW_TAG_inheritance, baseType: !0, size: 32, align: 32, addressSpace: 1) diff --git a/llvm/test/Verifier/diderivedtype-address-space-member.ll b/llvm/test/Verifier/diderivedtype-address-space-member.ll index 366bc4896bb24..cbf0b3f90e2f1 100644 --- a/llvm/test/Verifier/diderivedtype-address-space-member.ll +++ b/llvm/test/Verifier/diderivedtype-address-space-member.ll @@ -3,4 +3,4 @@ !named = !{!0, !1} !0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) ; CHECK: DWARF address space only applies to pointer or reference types -!1 = !DIDerivedType(tag: DW_TAG_member, baseType: !0, size: 32, align: 32, dwarfAddressSpace: 1) +!1 = !DIDerivedType(tag: DW_TAG_member, baseType: !0, size: 32, align: 32, addressSpace: 1) diff --git a/llvm/test/Verifier/diderivedtype-address-space-ptr-to-member-type.ll b/llvm/test/Verifier/diderivedtype-address-space-ptr-to-member-type.ll index 0ae6539d36622..12b2b1fd13c32 100644 --- a/llvm/test/Verifier/diderivedtype-address-space-ptr-to-member-type.ll +++ b/llvm/test/Verifier/diderivedtype-address-space-ptr-to-member-type.ll @@ -3,4 +3,4 @@ !named = !{!0, !1} !0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) ; CHECK: DWARF address space only applies to pointer or reference types -!1 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, baseType: !0, size: 32, align: 32, dwarfAddressSpace: 1) +!1 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, baseType: !0, size: 32, align: 32, addressSpace: 1) diff --git a/llvm/test/Verifier/diderivedtype-address-space-restrict-type.ll b/llvm/test/Verifier/diderivedtype-address-space-restrict-type.ll index b140a9e28b40e..2aaf916661b60 100644 --- a/llvm/test/Verifier/diderivedtype-address-space-restrict-type.ll +++ b/llvm/test/Verifier/diderivedtype-address-space-restrict-type.ll @@ -3,4 +3,4 @@ !named = !{!0, !1} !0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) ; CHECK: DWARF address space only applies to pointer or reference types -!1 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !0, size: 32, align: 32, dwarfAddressSpace: 1) +!1 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !0, size: 32, align: 32, addressSpace: 1) diff --git a/llvm/test/Verifier/diderivedtype-address-space-rvalue-reference-type.ll b/llvm/test/Verifier/diderivedtype-address-space-rvalue-reference-type.ll index 1e1586efe0b94..41c70166808dd 100644 --- a/llvm/test/Verifier/diderivedtype-address-space-rvalue-reference-type.ll +++ b/llvm/test/Verifier/diderivedtype-address-space-rvalue-reference-type.ll @@ -2,5 +2,5 @@ !named = !{!0, !1} !0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) -; CHECK: !DIDerivedType(tag: DW_TAG_rvalue_reference_type, {{.*}}, dwarfAddressSpace: 1) -!1 = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: !0, size: 32, align: 32, dwarfAddressSpace: 1) +; CHECK: !DIDerivedType(tag: DW_TAG_rvalue_reference_type, {{.*}}, addressSpace: 1) +!1 = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: !0, size: 32, align: 32, addressSpace: 1) diff --git a/llvm/test/Verifier/diderivedtype-address-space-typedef.ll b/llvm/test/Verifier/diderivedtype-address-space-typedef.ll index 03a5c6af88d3f..565dc06a7a2ce 100644 --- a/llvm/test/Verifier/diderivedtype-address-space-typedef.ll +++ b/llvm/test/Verifier/diderivedtype-address-space-typedef.ll @@ -3,4 +3,4 @@ !named = !{!0, !1} !0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) ; CHECK: DWARF address space only applies to pointer or reference types -!1 = !DIDerivedType(tag: DW_TAG_typedef, baseType: !0, size: 32, align: 32, dwarfAddressSpace: 1) +!1 = !DIDerivedType(tag: DW_TAG_typedef, baseType: !0, size: 32, align: 32, addressSpace: 1) diff --git a/llvm/test/Verifier/diderivedtype-address-space-volatile-type.ll b/llvm/test/Verifier/diderivedtype-address-space-volatile-type.ll index e8e70bc7959ac..72fcb495ec3de 100644 --- a/llvm/test/Verifier/diderivedtype-address-space-volatile-type.ll +++ b/llvm/test/Verifier/diderivedtype-address-space-volatile-type.ll @@ -3,4 +3,4 @@ !named = !{!0, !1} !0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) ; CHECK: DWARF address space only applies to pointer or reference types -!1 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !0, size: 32, align: 32, dwarfAddressSpace: 1) +!1 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !0, size: 32, align: 32, addressSpace: 1) diff --git a/llvm/test/Verifier/diderivedtype-memory-space-atomic-type.ll b/llvm/test/Verifier/diderivedtype-memory-space-atomic-type.ll new file mode 100644 index 0000000000000..81c10ac3c38e2 --- /dev/null +++ b/llvm/test/Verifier/diderivedtype-memory-space-atomic-type.ll @@ -0,0 +1,6 @@ +; RUN: not opt -S < %s 2>&1 | FileCheck %s + +!named = !{!0, !1} +!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) +; CHECK: DWARF memory space only applies to pointer or reference types +!1 = !DIDerivedType(tag: DW_TAG_atomic_type, baseType: !0, size: 32, align: 32, memorySpace: DW_MSPACE_LLVM_private) diff --git a/llvm/test/Verifier/diderivedtype-memory-space-const-type.ll b/llvm/test/Verifier/diderivedtype-memory-space-const-type.ll new file mode 100644 index 0000000000000..4d05a8b75f51e --- /dev/null +++ b/llvm/test/Verifier/diderivedtype-memory-space-const-type.ll @@ -0,0 +1,6 @@ +; RUN: not opt -S < %s 2>&1 | FileCheck %s + +!named = !{!0, !1} +!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) +; CHECK: DWARF memory space only applies to pointer or reference types +!1 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !0, size: 32, align: 32, memorySpace: DW_MSPACE_LLVM_private) diff --git a/llvm/test/Verifier/diderivedtype-memory-space-friend.ll b/llvm/test/Verifier/diderivedtype-memory-space-friend.ll new file mode 100644 index 0000000000000..a3d545391577b --- /dev/null +++ b/llvm/test/Verifier/diderivedtype-memory-space-friend.ll @@ -0,0 +1,6 @@ +; RUN: not opt -S < %s 2>&1 | FileCheck %s + +!named = !{!0, !1} +!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) +; CHECK: DWARF memory space only applies to pointer or reference types +!1 = !DIDerivedType(tag: DW_TAG_friend, baseType: !0, size: 32, align: 32, memorySpace: DW_MSPACE_LLVM_private) diff --git a/llvm/test/Verifier/diderivedtype-memory-space-inheritance.ll b/llvm/test/Verifier/diderivedtype-memory-space-inheritance.ll new file mode 100644 index 0000000000000..180a5802e602c --- /dev/null +++ b/llvm/test/Verifier/diderivedtype-memory-space-inheritance.ll @@ -0,0 +1,6 @@ +; RUN: not opt -S < %s 2>&1 | FileCheck %s + +!named = !{!0, !1} +!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) +; CHECK: DWARF memory space only applies to pointer or reference types +!1 = !DIDerivedType(tag: DW_TAG_inheritance, baseType: !0, size: 32, align: 32, memorySpace: DW_MSPACE_LLVM_private) diff --git a/llvm/test/Verifier/diderivedtype-memory-space-member.ll b/llvm/test/Verifier/diderivedtype-memory-space-member.ll new file mode 100644 index 0000000000000..da8084a1fe107 --- /dev/null +++ b/llvm/test/Verifier/diderivedtype-memory-space-member.ll @@ -0,0 +1,6 @@ +; RUN: not opt -S < %s 2>&1 | FileCheck %s + +!named = !{!0, !1} +!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) +; CHECK: DWARF memory space only applies to pointer or reference types +!1 = !DIDerivedType(tag: DW_TAG_member, baseType: !0, size: 32, align: 32, memorySpace: DW_MSPACE_LLVM_private) diff --git a/llvm/test/Verifier/diderivedtype-memory-space-ptr-to-member-type.ll b/llvm/test/Verifier/diderivedtype-memory-space-ptr-to-member-type.ll new file mode 100644 index 0000000000000..1ddbd5a183b69 --- /dev/null +++ b/llvm/test/Verifier/diderivedtype-memory-space-ptr-to-member-type.ll @@ -0,0 +1,6 @@ +; RUN: not opt -S < %s 2>&1 | FileCheck %s + +!named = !{!0, !1} +!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) +; CHECK: DWARF memory space only applies to pointer or reference types +!1 = !DIDerivedType(tag: DW_TAG_ptr_to_member_type, baseType: !0, size: 32, align: 32, memorySpace: DW_MSPACE_LLVM_group) diff --git a/llvm/test/Verifier/diderivedtype-memory-space-restrict-type.ll b/llvm/test/Verifier/diderivedtype-memory-space-restrict-type.ll new file mode 100644 index 0000000000000..998791b056109 --- /dev/null +++ b/llvm/test/Verifier/diderivedtype-memory-space-restrict-type.ll @@ -0,0 +1,6 @@ +; RUN: not opt -S < %s 2>&1 | FileCheck %s + +!named = !{!0, !1} +!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) +; CHECK: DWARF memory space only applies to pointer or reference types +!1 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !0, size: 32, align: 32, memorySpace: DW_MSPACE_LLVM_constant) diff --git a/llvm/test/Verifier/diderivedtype-memory-space-rvalue-reference-type.ll b/llvm/test/Verifier/diderivedtype-memory-space-rvalue-reference-type.ll new file mode 100644 index 0000000000000..a6af02be0365d --- /dev/null +++ b/llvm/test/Verifier/diderivedtype-memory-space-rvalue-reference-type.ll @@ -0,0 +1,6 @@ +; RUN: opt -S < %s 2>&1 | FileCheck %s + +!named = !{!0, !1} +!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) +; CHECK: !DIDerivedType(tag: DW_TAG_rvalue_reference_type, {{.*}}, memorySpace: DW_MSPACE_LLVM_private) +!1 = !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType: !0, size: 32, align: 32, memorySpace: DW_MSPACE_LLVM_private) diff --git a/llvm/test/Verifier/diderivedtype-memory-space-typedef.ll b/llvm/test/Verifier/diderivedtype-memory-space-typedef.ll new file mode 100644 index 0000000000000..03800c4eb0ffb --- /dev/null +++ b/llvm/test/Verifier/diderivedtype-memory-space-typedef.ll @@ -0,0 +1,6 @@ +; RUN: not opt -S < %s 2>&1 | FileCheck %s + +!named = !{!0, !1} +!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) +; CHECK: DWARF memory space only applies to pointer or reference types +!1 = !DIDerivedType(tag: DW_TAG_typedef, baseType: !0, size: 32, align: 32, memorySpace: DW_MSPACE_LLVM_global) diff --git a/llvm/test/Verifier/diderivedtype-memory-space-volatile-type.ll b/llvm/test/Verifier/diderivedtype-memory-space-volatile-type.ll new file mode 100644 index 0000000000000..3570c44b907a9 --- /dev/null +++ b/llvm/test/Verifier/diderivedtype-memory-space-volatile-type.ll @@ -0,0 +1,6 @@ +; RUN: not opt -S < %s 2>&1 | FileCheck %s + +!named = !{!0, !1} +!0 = !DIBasicType(tag: DW_TAG_base_type, name: "name", size: 1, align: 2, encoding: DW_ATE_unsigned_char) +; CHECK: DWARF memory space only applies to pointer or reference types +!1 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !0, size: 32, align: 32, memorySpace: DW_MSPACE_LLVM_global) diff --git a/llvm/test/Verifier/diglobal-memory-space-out-of-range.ll b/llvm/test/Verifier/diglobal-memory-space-out-of-range.ll new file mode 100644 index 0000000000000..1f336af7e1edf --- /dev/null +++ b/llvm/test/Verifier/diglobal-memory-space-out-of-range.ll @@ -0,0 +1,16 @@ +; RUN: not opt -S %s -o /dev/null 2>&1 | FileCheck %s +; CHECK: value for 'memorySpace' too large, limit is + +@var = dso_local global i32 0, align 4, !dbg !0 + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!6, !7} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(name: "var", scope: !2, file: !3, line: 1, type: !5, isLocal: false, isDefinition: true, memorySpace: 65536) +!2 = distinct !DICompileUnit(language: DW_LANG_OpenCL, file: !3, producer: "clang version 16.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: !4, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "test.cl", directory: "/") +!4 = !{!0} +!5 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!6 = !{i32 7, !"Dwarf Version", i32 5} +!7 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/llvm/test/Verifier/dilocal-memory-space-out-of-range.ll b/llvm/test/Verifier/dilocal-memory-space-out-of-range.ll new file mode 100644 index 0000000000000..7d3b9788d2eb2 --- /dev/null +++ b/llvm/test/Verifier/dilocal-memory-space-out-of-range.ll @@ -0,0 +1,25 @@ +; RUN: not opt -S %s -o /dev/null 2>&1 | FileCheck %s +; CHECK: value for 'memorySpace' too large, limit is + +define dso_local i32 @foo(i32 %var) !dbg !4 { +entry: + call void @llvm.dbg.value(metadata i32 %var, metadata !9, metadata !DIExpression()), !dbg !10 + ret i32 %var +} + +declare void @llvm.dbg.value(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} + +!0 = distinct !DICompileUnit(language: DW_LANG_OpenCL, file: !1, producer: "clang version 16.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cl", directory: "/") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !5, scopeLine: 1, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) +!5 = !DISubroutineType(types: !6) +!6 = !{!7, !7} +!7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!8 = !{!9} +!9 = !DILocalVariable(name: "var", arg: 1, scope: !4, file: !1, line: 1, type: !7, memorySpace: 65536) +!10 = !DILocation(scope: !4, line: 1) diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected index a8c2531117f42..0a85133152679 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected @@ -69,9 +69,22 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: .type .Lcheck_boundaries$local,@function ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; CHECK-NEXT: .cfi_undefined 2560 +; CHECK-NEXT: .cfi_undefined 2561 +; CHECK-NEXT: .cfi_undefined 2562 +; CHECK-NEXT: .cfi_undefined 2563 +; CHECK-NEXT: .cfi_undefined 2564 +; CHECK-NEXT: .cfi_undefined 36 +; CHECK-NEXT: .cfi_undefined 37 +; CHECK-NEXT: .cfi_undefined 38 +; CHECK-NEXT: .cfi_undefined 39 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_mov_b32 s8, s33 +; CHECK-NEXT: .cfi_register 65, 40 ; CHECK-NEXT: s_mov_b32 s33, s32 +; CHECK-NEXT: .cfi_def_cfa_register 65 ; CHECK-NEXT: s_addk_i32 s32, 0x600 ; CHECK-NEXT: v_mov_b32_e32 v4, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 1 @@ -102,6 +115,7 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: s_mov_b32 s32, s33 +; CHECK-NEXT: .cfi_def_cfa_register 64 ; CHECK-NEXT: s_mov_b32 s33, s8 ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_setpc_b64 s[30:31] @@ -111,9 +125,21 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: .type .Lmain$local,@function ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; CHECK-NEXT: .cfi_undefined 2560 +; CHECK-NEXT: .cfi_undefined 2561 +; CHECK-NEXT: .cfi_undefined 2562 +; CHECK-NEXT: .cfi_undefined 2563 +; CHECK-NEXT: .cfi_undefined 2564 +; CHECK-NEXT: .cfi_undefined 2565 +; CHECK-NEXT: .cfi_undefined 36 +; CHECK-NEXT: .cfi_undefined 37 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_mov_b32 s6, s33 +; CHECK-NEXT: .cfi_register 65, 38 ; CHECK-NEXT: s_mov_b32 s33, s32 +; CHECK-NEXT: .cfi_def_cfa_register 65 ; CHECK-NEXT: s_addk_i32 s32, 0x600 ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: s_getpc_b64 s[4:5] @@ -139,6 +165,7 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:16 ; CHECK-NEXT: s_mov_b32 s32, s33 +; CHECK-NEXT: .cfi_def_cfa_register 64 ; CHECK-NEXT: s_mov_b32 s33, s6 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected index 34530f2f632e2..df156b1b2e1b4 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected @@ -10,9 +10,22 @@ define dso_local i32 @check_boundaries() #0 { ; CHECK-NEXT: .type .Lcheck_boundaries$local,@function ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; CHECK-NEXT: .cfi_undefined 2560 +; CHECK-NEXT: .cfi_undefined 2561 +; CHECK-NEXT: .cfi_undefined 2562 +; CHECK-NEXT: .cfi_undefined 2563 +; CHECK-NEXT: .cfi_undefined 2564 +; CHECK-NEXT: .cfi_undefined 36 +; CHECK-NEXT: .cfi_undefined 37 +; CHECK-NEXT: .cfi_undefined 38 +; CHECK-NEXT: .cfi_undefined 39 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_mov_b32 s8, s33 +; CHECK-NEXT: .cfi_register 65, 40 ; CHECK-NEXT: s_mov_b32 s33, s32 +; CHECK-NEXT: .cfi_def_cfa_register 65 ; CHECK-NEXT: s_addk_i32 s32, 0x600 ; CHECK-NEXT: v_mov_b32_e32 v4, 0 ; CHECK-NEXT: v_mov_b32_e32 v0, 1 @@ -43,6 +56,7 @@ define dso_local i32 @check_boundaries() #0 { ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: s_mov_b32 s32, s33 +; CHECK-NEXT: .cfi_def_cfa_register 64 ; CHECK-NEXT: s_mov_b32 s33, s8 ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_setpc_b64 s[30:31] @@ -88,9 +102,21 @@ define dso_local i32 @main() #0 { ; CHECK-NEXT: .type .Lmain$local,@function ; CHECK-NEXT: .cfi_startproc ; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: .cfi_llvm_def_aspace_cfa 64, 0, 6 +; CHECK-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32 +; CHECK-NEXT: .cfi_undefined 2560 +; CHECK-NEXT: .cfi_undefined 2561 +; CHECK-NEXT: .cfi_undefined 2562 +; CHECK-NEXT: .cfi_undefined 2563 +; CHECK-NEXT: .cfi_undefined 2564 +; CHECK-NEXT: .cfi_undefined 2565 +; CHECK-NEXT: .cfi_undefined 36 +; CHECK-NEXT: .cfi_undefined 37 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_mov_b32 s6, s33 +; CHECK-NEXT: .cfi_register 65, 38 ; CHECK-NEXT: s_mov_b32 s33, s32 +; CHECK-NEXT: .cfi_def_cfa_register 65 ; CHECK-NEXT: s_addk_i32 s32, 0x600 ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: s_getpc_b64 s[4:5] @@ -116,6 +142,7 @@ define dso_local i32 @main() #0 { ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:16 ; CHECK-NEXT: s_mov_b32 s32, s33 +; CHECK-NEXT: .cfi_def_cfa_register 64 ; CHECK-NEXT: s_mov_b32 s33, s6 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu_generated_funcs.test b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu_generated_funcs.test index 8e9d63829d534..6d96619080443 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu_generated_funcs.test +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/amdgpu_generated_funcs.test @@ -1,5 +1,4 @@ # REQUIRES: amdgpu-registered-target - ## Check that generated functions are included. # RUN: cp -f %S/Inputs/amdgpu_generated_funcs.ll %t.ll && %update_llc_test_checks --include-generated-funcs %t.ll # RUN: diff -u %t.ll %S/Inputs/amdgpu_generated_funcs.ll.generated.expected diff --git a/llvm/test/tools/llvm-dwarfdump/AArch64/ptrauth.s b/llvm/test/tools/llvm-dwarfdump/AArch64/ptrauth.s index befd0fa86ef99..24bb633cac46d 100644 --- a/llvm/test/tools/llvm-dwarfdump/AArch64/ptrauth.s +++ b/llvm/test/tools/llvm-dwarfdump/AArch64/ptrauth.s @@ -23,7 +23,7 @@ # CHECK: 0x0000004f: DW_TAG_variable # CHECK: DW_AT_name ("p3") -# CHECK: DW_AT_type (0x0000005a "void *__ptrauth(4, 1, 0x04d4, "authenticates-null-values,strip")") +# CHECK: DW_AT_type (0x0000005a "void *__ptrauth(4, 1, 0x04d4, "authenticates-null-values")") # CHECK: 0x0000005a: DW_TAG_LLVM_ptrauth_type # CHECK: DW_AT_LLVM_ptrauth_key (0x04) @@ -33,7 +33,7 @@ # CHECK: 0x00000063: DW_TAG_variable # CHECK: DW_AT_name ("p4") -# CHECK: DW_AT_type (0x0000006e "void *__ptrauth(4, 1, 0x04d5, "isa-pointer,authenticates-null-values,sign-and-strip")") +# CHECK: DW_AT_type (0x0000006e "void *__ptrauth(4, 1, 0x04d5, "isa-pointer,authenticates-null-values")") # CHECK: 0x0000006e: DW_TAG_LLVM_ptrauth_type # CHECK: DW_AT_LLVM_ptrauth_key (0x04) @@ -140,7 +140,7 @@ Lsection_abbrev: .byte 5 ; DW_FORM_data2 .ascii "\211|" ; DW_AT_LLVM_ptrauth_authenticates_null_values .byte 25 ; DW_FORM_flag_present - .ascii "\212|" ; DW_AT_LLVM_ptrauth_authentication_mode + .ascii "\217|" ; DW_AT_LLVM_ptrauth_authentication_mode .byte 11 ; DW_FORM_data1 .byte 0 ; EOM(1) .byte 0 ; EOM(2) @@ -159,7 +159,7 @@ Lsection_abbrev: .byte 25 ; DW_FORM_flag_present .ascii "\211|" ; DW_AT_LLVM_ptrauth_authenticates_null_values .byte 25 ; DW_FORM_flag_present - .ascii "\212|" ; DW_AT_LLVM_ptrauth_authentication_mode + .ascii "\217|" ; DW_AT_LLVM_ptrauth_authentication_mode .byte 11 ; DW_FORM_data1 .byte 0 ; EOM(1) .byte 0 ; EOM(2) diff --git a/llvm/test/tools/llvm-dwarfdump/AMDGPU/amdgpu-relocs.yaml b/llvm/test/tools/llvm-dwarfdump/AMDGPU/amdgpu-relocs.yaml index 669a4025ccf01..2b4e8ace54846 100644 --- a/llvm/test/tools/llvm-dwarfdump/AMDGPU/amdgpu-relocs.yaml +++ b/llvm/test/tools/llvm-dwarfdump/AMDGPU/amdgpu-relocs.yaml @@ -14,8 +14,8 @@ # RUN: yaml2obj --docnum=2 -DMACH=EF_AMDGPU_MACH_R600_R600 %s \ # RUN: | llvm-dwarfdump - 2>&1 | FileCheck --check-prefixes=R600,KNOWN %s -# UNKNOWN: -: Error in creating MCRegInfo -# KNOWN-NOT: -: Error in creating MCRegInfo +# UNKNOWN: -: Error in creating Target +# KNOWN-NOT: -: Error in creating Target # AMDGCN: -: file format elf64-amdgpu diff --git a/llvm/test/tools/llvm-dwarfdump/X86/heterogeneous_proposal.s b/llvm/test/tools/llvm-dwarfdump/X86/heterogeneous_proposal.s new file mode 100644 index 0000000000000..1d0134f89bef0 --- /dev/null +++ b/llvm/test/tools/llvm-dwarfdump/X86/heterogeneous_proposal.s @@ -0,0 +1,37 @@ +# RUN: llvm-mc %s -filetype=obj -triple=i686-pc-linux -o %t +# RUN: llvm-dwarfdump -v %t | FileCheck %s + +# Check that we can decode new ops described at +# llvm/docs/AMDGPUUsage.rst#expression-operation-encodings + +# FIXME: Is there a better approach than using `DW_CFA_expression EAX `? + +# CHECK: .eh_frame contents: +# CHECK: FDE +# CHECK: Format: DWARF32 + +foo: + .cfi_startproc + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address + .cfi_escape 0x10, 0x00, 0x02, 0xe9, 0x02 + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_push_lane + .cfi_escape 0x10, 0x00, 0x02, 0xe9, 0x03 + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_offset + .cfi_escape 0x10, 0x00, 0x02, 0xe9, 0x04 + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_offset_uconst 0x0 + .cfi_escape 0x10, 0x00, 0x03, 0xe9, 0x05, 0x00 + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_bit_offset + .cfi_escape 0x10, 0x00, 0x02, 0xe9, 0x06 + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_call_frame_entry_reg EAX + .cfi_escape 0x10, 0x00, 0x03, 0xe9, 0x07, 0x00 + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_undefined + .cfi_escape 0x10, 0x00, 0x02, 0xe9, 0x08 + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_aspace_bregx EAX+2 + .cfi_escape 0x10, 0x00, 0x04, 0xe9, 0x09, 0x0, 0x2 + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_piece_end + .cfi_escape 0x10, 0x00, 0x02, 0xe9, 0x0a + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_extend 0x0 0x0 + .cfi_escape 0x10, 0x00, 0x04, 0xe9, 0x0b, 0x0, 0x0 + # CHECK-NEXT: DW_CFA_expression: EAX DW_OP_LLVM_user DW_OP_LLVM_select_bit_piece 0x0 0x0 + .cfi_escape 0x10, 0x00, 0x04, 0xe9, 0x0c, 0x0, 0x0 + .cfi_endproc diff --git a/llvm/test/tools/llvm-ifs/fail-file-write.test b/llvm/test/tools/llvm-ifs/fail-file-write.test index f13500f226205..e95d02db33ac4 100644 --- a/llvm/test/tools/llvm-ifs/fail-file-write.test +++ b/llvm/test/tools/llvm-ifs/fail-file-write.test @@ -1,5 +1,6 @@ ## Test failing to write output file on non-windows platforms. +# REQUIRES: jenkins-permissions-issue # UNSUPPORTED: system-windows # REQUIRES: non-root-user # RUN: rm -rf %t.TestDir diff --git a/llvm/test/tools/llvm-link/remangle.test b/llvm/test/tools/llvm-link/remangle.test index e65cab3963f6d..69a2e536b2341 100644 --- a/llvm/test/tools/llvm-link/remangle.test +++ b/llvm/test/tools/llvm-link/remangle.test @@ -1,7 +1,7 @@ -# RUN: llvm-as %S/Inputs/remangle1.ll -o %t.remangle1.bc -# RUN: llvm-as %S/Inputs/remangle2.ll -o %t.remangle2.bc -# RUN: llvm-link %t.remangle1.bc %t.remangle2.bc -o %t.remangle.linked.bc -# RUN: llvm-dis %t.remangle.linked.bc -o - | FileCheck %s +# RUN: llvm-as %S/Inputs/remangle1.ll -o %t.remangle1.bc +# RUN: llvm-as %S/Inputs/remangle2.ll -o %t.remangle2.bc +# RUN: llvm-link %t.remangle1.bc %t.remangle2.bc -o %t.remangle.linked.bc +# RUN: llvm-dis %t.remangle.linked.bc -o - | FileCheck %s ; CHECK-DAG: %fum.1 = type { %aab.0, i8, [7 x i8] } ; CHECK-DAG: %aab.0 = type { %aba } diff --git a/llvm/test/tools/llvm-objdump/Offloading/fatbin.test b/llvm/test/tools/llvm-objdump/Offloading/fatbin.test index 3d3c5157b7669..40cb26896cd86 100644 --- a/llvm/test/tools/llvm-objdump/Offloading/fatbin.test +++ b/llvm/test/tools/llvm-objdump/Offloading/fatbin.test @@ -1,7 +1,6 @@ ## Test that --offloading with a fatbin works correctly # REQUIRES: target={{x86_64-.*-linux.*}} -# REQUIRES: amdgpu-registered-target # RUN: yaml2obj %s -o %t.elf # RUN: llvm-objdump --offloading %t.elf # RUN: llvm-objdump -d %t.elf.0.hipv4-amdgcn-amd-amdhsa--gfx908 | FileCheck %s diff --git a/llvm/test/tools/llvm-reduce/operands-skip.ll b/llvm/test/tools/llvm-reduce/operands-skip.ll index ba5bcf4420181..6f78ea84d97a0 100644 --- a/llvm/test/tools/llvm-reduce/operands-skip.ll +++ b/llvm/test/tools/llvm-reduce/operands-skip.ll @@ -1,11 +1,11 @@ ; RUN: llvm-reduce %s -o %t --abort-on-invalid-reduction --delta-passes=operands-skip --test FileCheck --test-arg %s --test-arg --match-full-lines --test-arg --check-prefix=INTERESTING --test-arg --input-file ; RUN: FileCheck %s --input-file %t --check-prefixes=REDUCED -; INTERESTING: store i32 43, ptr {{(%imm|%indirect)}}, align 4 -; REDUCED: store i32 43, ptr %imm, align 4 +; RUN: llvm-reduce -j 2 %s -o %t.1 --delta-passes=operands-skip --test FileCheck --test-arg %s --test-arg --match-full-lines --test-arg --check-prefix=INTERESTING --test-arg --input-file +; RUN: FileCheck %s --input-file %t.1 --check-prefixes=REDUCED -; INTERESTING: store i32 44, ptr {{(%imm|%indirect|%phi)}}, align 4 -; REDUCED: store i32 44, ptr %phi, align 4 +; RUN: llvm-reduce -j 4 %s -o %t.2 --delta-passes=operands-skip --test FileCheck --test-arg %s --test-arg --match-full-lines --test-arg --check-prefix=INTERESTING --test-arg --input-file +; RUN: FileCheck %s --input-file %t.2 --check-prefixes=REDUCED ; INTERESTING: store i32 45, ptr {{(%imm|%indirect|%phi|%val)}}, align 4 ; REDUCED: store i32 45, ptr %val, align 4 diff --git a/llvm/test/tools/llvm-split/scc-const-alias.ll b/llvm/test/tools/llvm-split/scc-const-alias.ll index 9e66f38f50843..d81e65fa24672 100644 --- a/llvm/test/tools/llvm-split/scc-const-alias.ll +++ b/llvm/test/tools/llvm-split/scc-const-alias.ll @@ -1,8 +1,8 @@ ; We should never separate alias from aliasee. -; RUN: llvm-split -j=3 -preserve-locals -o %t %s -; RUN: llvm-dis -o - %t0 | FileCheck --check-prefix=CHECK0 %s -; RUN: llvm-dis -o - %t1 | FileCheck --check-prefix=CHECK1 %s -; RUN: llvm-dis -o - %t2 | FileCheck --check-prefix=CHECK2 %s +; RUN: llvm-split -j=3 -preserve-locals -o %t %s +; RUN: llvm-dis -o - %t0 | FileCheck --check-prefix=CHECK0 %s +; RUN: llvm-dis -o - %t1 | FileCheck --check-prefix=CHECK1 %s +; RUN: llvm-dis -o - %t2 | FileCheck --check-prefix=CHECK2 %s ; Checks are not critical here - verifier will assert if we fail. ; CHECK0: @g1 = external global i32 diff --git a/llvm/test/tools/llvm-split/scc-global2global.ll b/llvm/test/tools/llvm-split/scc-global2global.ll index 4bf6713038ce7..41656e86d90ea 100644 --- a/llvm/test/tools/llvm-split/scc-global2global.ll +++ b/llvm/test/tools/llvm-split/scc-global2global.ll @@ -1,9 +1,9 @@ ; All of the functions and globals in this module must end up ; in the same partition. -; RUN: llvm-split -j=2 -preserve-locals -o %t %s -; RUN: llvm-dis -o - %t0 | FileCheck --check-prefix=CHECK1 %s -; RUN: llvm-dis -o - %t1 | FileCheck --check-prefix=CHECK0 %s +; RUN: llvm-split -j=2 -preserve-locals -o %t %s +; RUN: llvm-dis -o - %t0 | FileCheck --check-prefix=CHECK1 %s +; RUN: llvm-dis -o - %t1 | FileCheck --check-prefix=CHECK0 %s ; CHECK0: declare dso_local ptr @local0 ; CHECK0: declare dso_local ptr @local1 diff --git a/llvm/tools/llvm-c-test/debuginfo.c b/llvm/tools/llvm-c-test/debuginfo.c index 9db7aa0929aab..2e165d99717ae 100644 --- a/llvm/tools/llvm-c-test/debuginfo.c +++ b/llvm/tools/llvm-c-test/debuginfo.c @@ -71,9 +71,9 @@ int llvm_test_dibuilder(void) { LLVMMetadataRef ClassTy = declare_objc_class(DIB, File); LLVMMetadataRef GlobalClassValueExpr = LLVMDIBuilderCreateConstantValueExpression(DIB, 0); - LLVMDIBuilderCreateGlobalVariableExpression( - DIB, Module, "globalClass", 11, "", 0, File, 1, ClassTy, true, - GlobalClassValueExpr, NULL, 0); + LLVMDIBuilderCreateGlobalVariableExpression(DIB, Module, "globalClass", 11, + "", 0, File, 1, ClassTy, true, + GlobalClassValueExpr, NULL, 0, 0); LLVMMetadataRef Int64Ty = LLVMDIBuilderCreateBasicType(DIB, "Int64", 5, 64, 0, LLVMDIFlagZero); @@ -82,9 +82,9 @@ int llvm_test_dibuilder(void) { LLVMMetadataRef GlobalVarValueExpr = LLVMDIBuilderCreateConstantValueExpression(DIB, 0); - LLVMDIBuilderCreateGlobalVariableExpression( - DIB, Module, "global", 6, "", 0, File, 1, Int64TypeDef, true, - GlobalVarValueExpr, NULL, 0); + LLVMDIBuilderCreateGlobalVariableExpression(DIB, Module, "global", 6, "", 0, + File, 1, Int64TypeDef, true, + GlobalVarValueExpr, NULL, 0, 0); LLVMMetadataRef NameSpace = LLVMDIBuilderCreateNameSpace(DIB, Module, "NameSpace", 9, false); @@ -96,7 +96,7 @@ int llvm_test_dibuilder(void) { LLVMDWARFSourceLanguageC, NULL, "MyStruct", 8); LLVMMetadataRef StructDbgPtrTy = - LLVMDIBuilderCreatePointerType(DIB, StructDbgTy, 192, 0, 0, "", 0); + LLVMDIBuilderCreatePointerType(DIB, StructDbgTy, 192, 0, 0, 0, "", 0); LLVMAddNamedMetadataOperand(M, "FooType", LLVMMetadataAsValue(LLVMGetModuleContext(M), StructDbgPtrTy)); @@ -178,9 +178,8 @@ int llvm_test_dibuilder(void) { LLVMMetadataRef FooVarsLocation = LLVMDIBuilderCreateDebugLocation(LLVMGetGlobalContext(), 43, 0, FunctionMetadata, NULL); - LLVMMetadataRef FooVar1 = - LLVMDIBuilderCreateAutoVariable(DIB, FooLexicalBlock, "d", 1, File, - 43, Int64Ty, true, 0, 0); + LLVMMetadataRef FooVar1 = LLVMDIBuilderCreateAutoVariable( + DIB, FooLexicalBlock, "d", 1, File, 43, Int64Ty, true, 0, 0, 0); LLVMValueRef FooVal1 = LLVMConstInt(LLVMInt64Type(), 0, false); LLVMMetadataRef FooVarValueExpr1 = LLVMDIBuilderCreateConstantValueExpression(DIB, 0); @@ -189,7 +188,7 @@ int llvm_test_dibuilder(void) { DIB, FooVal1, FooVar1, FooVarValueExpr1, FooVarsLocation, FooVarBlock); LLVMMetadataRef FooVar2 = LLVMDIBuilderCreateAutoVariable( - DIB, FooLexicalBlock, "e", 1, File, 44, Int64Ty, true, 0, 0); + DIB, FooLexicalBlock, "e", 1, File, 44, Int64Ty, true, 0, 0, 0); LLVMValueRef FooVal2 = LLVMConstInt(LLVMInt64Type(), 1, false); LLVMMetadataRef FooVarValueExpr2 = LLVMDIBuilderCreateConstantValueExpression(DIB, 1); @@ -445,7 +444,7 @@ int llvm_add_globaldebuginfo(void) { LLVMMetadataRef GVE = LLVMDIBuilderCreateGlobalVariableExpression( Builder, File, "global", 6, "", 0, File, 1, Int64TypeDef, true, - GlobalVarValueExpr, NULL, 0); + GlobalVarValueExpr, NULL, 0, 0); LLVMTypeRef RecType = LLVMStructCreateNamed(LLVMGetModuleContext(M), "struct"); diff --git a/llvm/tools/llvm-dwarfdump/CMakeLists.txt b/llvm/tools/llvm-dwarfdump/CMakeLists.txt index aeb1b8f14d830..ab55ce55e5a56 100644 --- a/llvm/tools/llvm-dwarfdump/CMakeLists.txt +++ b/llvm/tools/llvm-dwarfdump/CMakeLists.txt @@ -3,6 +3,7 @@ set(LLVM_LINK_COMPONENTS DebugInfoDWARFLowLevel AllTargetsDescs AllTargetsInfos + BinaryFormat MC Object Support diff --git a/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp b/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp index 11eb58ea911df..4533875338919 100644 --- a/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp +++ b/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp @@ -401,15 +401,24 @@ static bool filterArch(ObjectFile &Obj) { return false; } +struct TargetCallbacks { + std::unique_ptr MCRegInfo; + std::function + GetNameForDWARFReg; + std::function GetNameForDWARFAddressSpace; +}; + using HandlerFn = std::function; /// Print only DIEs that have a certain name. -static bool filterByName( - const StringSet<> &Names, DWARFDie Die, StringRef NameRef, raw_ostream &OS, - std::function GetNameForDWARFReg) { +static bool filterByName(const StringSet<> &Names, DWARFDie Die, + StringRef NameRef, raw_ostream &OS, + TargetCallbacks &Callbacks) { DIDumpOptions DumpOpts = getDumpOpts(Die.getDwarfUnit()->getContext()); - DumpOpts.GetNameForDWARFReg = GetNameForDWARFReg; + DumpOpts.GetNameForDWARFReg = Callbacks.GetNameForDWARFReg; + DumpOpts.GetNameForDWARFAddressSpace = Callbacks.GetNameForDWARFAddressSpace; + std::string Name = (IgnoreCase && !UseRegex) ? NameRef.lower() : NameRef.str(); if (UseRegex) { @@ -435,18 +444,17 @@ static bool filterByName( } /// Print only DIEs that have a certain name. -static void filterByName( - const StringSet<> &Names, DWARFContext::unit_iterator_range CUs, - raw_ostream &OS, - std::function GetNameForDWARFReg) { +static void filterByName(const StringSet<> &Names, + DWARFContext::unit_iterator_range CUs, raw_ostream &OS, + TargetCallbacks &Callbacks) { auto filterDieNames = [&](DWARFUnit *Unit) { for (const auto &Entry : Unit->dies()) { DWARFDie Die = {Unit, &Entry}; if (const char *Name = Die.getName(DINameKind::ShortName)) - if (filterByName(Names, Die, Name, OS, GetNameForDWARFReg)) + if (filterByName(Names, Die, Name, OS, Callbacks)) continue; if (const char *Name = Die.getName(DINameKind::LinkageName)) - filterByName(Names, Die, Name, OS, GetNameForDWARFReg); + filterByName(Names, Die, Name, OS, Callbacks); } }; for (const auto &CU : CUs) { @@ -502,9 +510,8 @@ static void getDies(DWARFContext &DICtx, const DWARFDebugNames &Accel, } /// Print only DIEs that have a certain name. -static void filterByAccelName( - ArrayRef Names, DWARFContext &DICtx, raw_ostream &OS, - std::function GetNameForDWARFReg) { +static void filterByAccelName(ArrayRef Names, DWARFContext &DICtx, + raw_ostream &OS, TargetCallbacks &Callbacks) { SmallVector Dies; for (const auto &Name : Names) { getDies(DICtx, DICtx.getAppleNames(), Name, Dies); @@ -516,15 +523,15 @@ static void filterByAccelName( Dies.erase(llvm::unique(Dies), Dies.end()); DIDumpOptions DumpOpts = getDumpOpts(DICtx); - DumpOpts.GetNameForDWARFReg = GetNameForDWARFReg; + DumpOpts.GetNameForDWARFReg = Callbacks.GetNameForDWARFReg; + DumpOpts.GetNameForDWARFAddressSpace = Callbacks.GetNameForDWARFAddressSpace; for (DWARFDie Die : Dies) Die.dump(OS, 0, DumpOpts); } /// Print all DIEs in apple accelerator tables -static void findAllApple( - DWARFContext &DICtx, raw_ostream &OS, - std::function GetNameForDWARFReg) { +static void findAllApple(DWARFContext &DICtx, raw_ostream &OS, + const TargetCallbacks &Callbacks) { MapVector> NameToDies; auto PushDIEs = [&](const AppleAcceleratorTable &Accel) { @@ -543,7 +550,7 @@ static void findAllApple( PushDIEs(DICtx.getAppleTypes()); DIDumpOptions DumpOpts = getDumpOpts(DICtx); - DumpOpts.GetNameForDWARFReg = GetNameForDWARFReg; + DumpOpts.GetNameForDWARFReg = Callbacks.GetNameForDWARFReg; for (const auto &[Name, Dies] : NameToDies) { OS << llvm::formatv("\nApple accelerator entries with name = \"{0}\":\n", Name); @@ -683,24 +690,46 @@ createRegInfo(const object::ObjectFile &Obj) { return MCRegInfo; } -static bool dumpObjectFile(ObjectFile &Obj, DWARFContext &DICtx, - const Twine &Filename, raw_ostream &OS) { +static TargetCallbacks getCallbacks(ObjectFile &Obj, const Twine &Filename) { + Triple TT = Obj.makeTriple(); + + std::string TargetLookupError; + const Target *TheTarget = TargetRegistry::lookupTarget(TT, TargetLookupError); + if (!TargetLookupError.empty()) { + logAllUnhandledErrors( + createStringError(inconvertibleErrorCode(), "Error in creating Target"), + errs(), Filename.str() + ": "); + + return {}; + } - auto MCRegInfo = createRegInfo(Obj); - if (!MCRegInfo) + const MCRegisterInfo *MCRI = TheTarget->createMCRegInfo(TT); + if (!MCRI) { logAllUnhandledErrors(createStringError(inconvertibleErrorCode(), - "Error in creating MCRegInfo"), + "Error in creating MCRegisterInfo"), errs(), Filename.str() + ": "); - - auto GetRegName = [&MCRegInfo](uint64_t DwarfRegNum, bool IsEH) -> StringRef { - if (!MCRegInfo) - return {}; + return {}; + } + TargetCallbacks Callbacks; + Callbacks.MCRegInfo.reset(MCRI); + Callbacks.GetNameForDWARFReg = [MCRI](uint64_t DwarfRegNum, + bool IsEH) -> StringRef { if (std::optional LLVMRegNum = - MCRegInfo->getLLVMRegNum(DwarfRegNum, IsEH)) - if (const char *RegName = MCRegInfo->getName(*LLVMRegNum)) + MCRI->getLLVMRegNum(DwarfRegNum, IsEH)) + if (const char *RegName = MCRI->getName(*LLVMRegNum)) return StringRef(RegName); return {}; }; + Callbacks.GetNameForDWARFAddressSpace = [TT](uint64_t AS) { + return dwarf::AddressSpaceString(AS, TT); + }; + + return Callbacks; +} + +static bool dumpObjectFile(ObjectFile &Obj, DWARFContext &DICtx, + const Twine &Filename, raw_ostream &OS) { + TargetCallbacks Callbacks = getCallbacks(Obj, Filename); // The UUID dump already contains all the same information. if (!(DumpType & DIDT_UUID) || DumpType == DIDT_All) @@ -716,26 +745,27 @@ static bool dumpObjectFile(ObjectFile &Obj, DWARFContext &DICtx, for (const auto &name : Name) Names.insert((IgnoreCase && !UseRegex) ? StringRef(name).lower() : name); - filterByName(Names, DICtx.normal_units(), OS, GetRegName); - filterByName(Names, DICtx.dwo_units(), OS, GetRegName); + filterByName(Names, DICtx.normal_units(), OS, Callbacks); + filterByName(Names, DICtx.dwo_units(), OS, Callbacks); return true; } // Handle the --find option and lower it to --debug-info=. if (!Find.empty()) { - filterByAccelName(Find, DICtx, OS, GetRegName); + filterByAccelName(Find, DICtx, OS, Callbacks); return true; } // Handle the --find-all-apple option and lower it to --debug-info=. if (FindAllApple) { - findAllApple(DICtx, OS, GetRegName); + findAllApple(DICtx, OS, Callbacks); return true; } // Dump the complete DWARF structure. auto DumpOpts = getDumpOpts(DICtx); - DumpOpts.GetNameForDWARFReg = GetRegName; + DumpOpts.GetNameForDWARFReg = Callbacks.GetNameForDWARFReg; + DumpOpts.GetNameForDWARFAddressSpace = Callbacks.GetNameForDWARFAddressSpace; DICtx.dump(OS, DumpOpts, DumpOffsets); return true; } diff --git a/llvm/tools/llvm-objdump/ObjdumpOpts.td b/llvm/tools/llvm-objdump/ObjdumpOpts.td index c97e06f3ed173..c7263d4561e4b 100644 --- a/llvm/tools/llvm-objdump/ObjdumpOpts.td +++ b/llvm/tools/llvm-objdump/ObjdumpOpts.td @@ -108,6 +108,9 @@ def fault_map_section : Flag<["--"], "fault-map-section">, def offloading : Flag<["--"], "offloading">, HelpText<"Display the content of the offloading section">; +def offload_fatbin : Flag<["--"], "offload-fatbin">, + HelpText<"Display the content of the offload FatBin section">; + def file_headers : Flag<["--"], "file-headers">, HelpText<"Display the contents of the overall file header">; def : Flag<["-"], "f">, Alias, diff --git a/llvm/tools/llvm-objdump/OffloadDump.cpp b/llvm/tools/llvm-objdump/OffloadDump.cpp index a77537dd90eeb..74f0c43cd868a 100644 --- a/llvm/tools/llvm-objdump/OffloadDump.cpp +++ b/llvm/tools/llvm-objdump/OffloadDump.cpp @@ -16,6 +16,7 @@ #include "llvm/Object/ELFObjectFile.h" #include "llvm/Object/OffloadBinary.h" #include "llvm/Object/OffloadBundle.h" +#include "llvm/Support/Alignment.h" using namespace llvm; using namespace llvm::object; diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp index 3ec644a472bfc..299c51fb999c3 100644 --- a/llvm/tools/llvm-objdump/llvm-objdump.cpp +++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp @@ -57,6 +57,7 @@ #include "llvm/Object/MachO.h" #include "llvm/Object/MachOUniversal.h" #include "llvm/Object/OffloadBinary.h" +#include "llvm/Object/OffloadBundle.h" #include "llvm/Object/Wasm.h" #include "llvm/Option/Arg.h" #include "llvm/Option/ArgList.h" diff --git a/llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp b/llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp index e22d13b946651..fc0c18509bcd2 100644 --- a/llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp +++ b/llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp @@ -54,6 +54,11 @@ static cl::opt cl::desc("Write extracted files to a static archive"), cl::cat(OffloadBinaryCategory)); +static cl::opt AllowMissingPackages( + "allow-missing-packages", + cl::desc("Create empty files if packages are missing when unpackaging.\n"), + cl::init(false), cl::cat(OffloadBinaryCategory)); + /// Path of the current binary. static const char *PackagerExecutable; @@ -138,6 +143,7 @@ static Error bundleImages() { static Error unbundleImages() { ErrorOr> BufferOrErr = MemoryBuffer::getFileOrSTDIN(InputFile); + if (std::error_code EC = BufferOrErr.getError()) return createFileError(InputFile, EC); std::unique_ptr Buffer = std::move(*BufferOrErr); @@ -161,6 +167,16 @@ static Error unbundleImages() { SmallVector Extracted; for (const OffloadFile &File : Binaries) { const auto *Binary = File.getBinary(); + // If the user lists a .so file on the command line for the program + // that invokes this one (probably clang), it may contain offload + // binary sections that resemble those in an object file. However, + // there is no late binding/shared object support on the target side + // (i.e. you cannot define a target function in a shared object and + // call it from a target region in the main program), and we don't want + // to *early* bind target regions in a shared object either. So, + // ignore shared objects here. + if (identify_magic(Binary->getImage()) == file_magic::elf_shared_object) + continue; // We handle the 'file' and 'kind' identifiers differently. bool Match = llvm::all_of(Args, [&](auto &Arg) { const auto [Key, Value] = Arg; @@ -174,8 +190,13 @@ static Error unbundleImages() { Extracted.push_back(Binary); } - if (Extracted.empty()) + if (Extracted.empty()) { + if (AllowMissingPackages) + if (Error E = writeFile(Args["file"], StringRef())) + return E; + continue; + } if (CreateArchive) { if (!Args.count("file")) diff --git a/llvm/unittests/DWARFLinkerParallel/DWARFLinkerTest.cpp b/llvm/unittests/DWARFLinkerParallel/DWARFLinkerTest.cpp index 50c91396d6a1c..6439bf2cbc5f8 100644 --- a/llvm/unittests/DWARFLinkerParallel/DWARFLinkerTest.cpp +++ b/llvm/unittests/DWARFLinkerParallel/DWARFLinkerTest.cpp @@ -24,12 +24,6 @@ TEST(DWARFLinker, PathTest) { "/Platforms/MacOSX.platform/Developer/SDKs/MacOSX14.4.sdk"), DEVELOPER_DIR); EXPECT_EQ(guessDeveloperDir(DEVELOPER_DIR "/SDKs/MacOSX.sdk"), DEVELOPER_DIR); - EXPECT_TRUE( - isInToolchainDir("/Library/Developer/Toolchains/" - "swift-DEVELOPMENT-SNAPSHOT-2024-05-15-a.xctoolchain/" - "usr/lib/swift/macosx/_StringProcessing.swiftmodule/" - "arm64-apple-macos.private.swiftinterface")); - EXPECT_FALSE(isInToolchainDir("/Foo/not-an.xctoolchain/Bar/Baz")); } } // anonymous namespace diff --git a/llvm/unittests/Frontend/OpenMPContextTest.cpp b/llvm/unittests/Frontend/OpenMPContextTest.cpp index f9683ae56e933..2cb674cd9e023 100644 --- a/llvm/unittests/Frontend/OpenMPContextTest.cpp +++ b/llvm/unittests/Frontend/OpenMPContextTest.cpp @@ -96,7 +96,7 @@ TEST_F(OpenMPContextTest, ApplicabilityNonConstruct) { EXPECT_FALSE(isVariantApplicableInContext(DeviceArchArm, DeviceNVPTX)); VariantMatchInfo LLVMHostUserCondTrue; - LLVMHostUserCondTrue.addTrait(TraitProperty::implementation_vendor_llvm, ""); + LLVMHostUserCondTrue.addTrait(TraitProperty::implementation_vendor_amd, ""); LLVMHostUserCondTrue.addTrait(TraitProperty::device_kind_host, ""); LLVMHostUserCondTrue.addTrait(TraitProperty::device_kind_any, ""); LLVMHostUserCondTrue.addTrait(TraitProperty::user_condition_true, ""); @@ -182,7 +182,7 @@ TEST_F(OpenMPContextTest, ApplicabilityAllTraits) { APInt Score(32, 1000); VariantMatchInfo LLVMHostUserCondTrue; - LLVMHostUserCondTrue.addTrait(TraitProperty::implementation_vendor_llvm, + LLVMHostUserCondTrue.addTrait(TraitProperty::implementation_vendor_amd, ""); LLVMHostUserCondTrue.addTrait(TraitProperty::device_kind_host, ""); LLVMHostUserCondTrue.addTrait(TraitProperty::device_kind_any, ""); @@ -242,7 +242,7 @@ TEST_F(OpenMPContextTest, ApplicabilityAllTraits) { VariantMatchInfo LLVMHostUserCondTrueParallel; LLVMHostUserCondTrueParallel.addTrait( - TraitProperty::implementation_vendor_llvm, ""); + TraitProperty::implementation_vendor_amd, ""); LLVMHostUserCondTrueParallel.addTrait(TraitProperty::device_kind_host, ""); LLVMHostUserCondTrueParallel.addTrait(TraitProperty::device_kind_any, ""); LLVMHostUserCondTrueParallel.addTrait(TraitProperty::user_condition_true, diff --git a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp index e56872320b4ac..5b22ac31b572e 100644 --- a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp +++ b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp @@ -651,6 +651,7 @@ TEST_F(OpenMPIRBuilderTest, ParallelSimpleGPU) { "256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"); OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = true; + OMPBuilder.Config.IsGPU = true; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -763,6 +764,7 @@ TEST_F(OpenMPIRBuilderTest, ParallelSimple) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -873,6 +875,7 @@ TEST_F(OpenMPIRBuilderTest, ParallelNested) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -974,6 +977,7 @@ TEST_F(OpenMPIRBuilderTest, ParallelNested2Inner) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -1093,6 +1097,7 @@ TEST_F(OpenMPIRBuilderTest, ParallelIfCond) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -1201,6 +1206,7 @@ TEST_F(OpenMPIRBuilderTest, ParallelCancelBarrier) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -1323,6 +1329,7 @@ TEST_F(OpenMPIRBuilderTest, ParallelCancelBarrier) { TEST_F(OpenMPIRBuilderTest, ParallelForwardAsPointers) { OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -2427,14 +2434,21 @@ TEST_F(OpenMPIRBuilderTest, StaticWorkshareLoopTarget) { // Check that no variables except for loop counter are used in loop body EXPECT_EQ(Constant::getNullValue(Builder.getPtrTy()), WorkshareLoopRuntimeCall->getArgOperand(2)); - // Check loop trip count argument - EXPECT_EQ(TripCount, WorkshareLoopRuntimeCall->getArgOperand(3)); + // Check loop trip count argument. + ConstantInt *TripCountConstInt = dyn_cast(TripCount); + EXPECT_NE(TripCountConstInt, nullptr); + ConstantInt *WorkshareLoopRuntimeCallTripCount = + dyn_cast(WorkshareLoopRuntimeCall->getArgOperand(3)); + EXPECT_NE(WorkshareLoopRuntimeCallTripCount, nullptr); + EXPECT_EQ(WorkshareLoopRuntimeCallTripCount->getSExtValue(), + TripCountConstInt->getSExtValue()); } TEST_F(OpenMPIRBuilderTest, StaticWorkShareLoop) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); IRBuilder<> Builder(BB); OpenMPIRBuilder::LocationDescription Loc({Builder.saveIP(), DL}); @@ -2540,6 +2554,7 @@ TEST_P(OpenMPIRBuilderTestWithIVBits, StaticChunkedWorkshareLoop) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; BasicBlock *Body; CallInst *Call; @@ -2619,6 +2634,7 @@ TEST_P(OpenMPIRBuilderTestWithParams, DynamicWorkShareLoop) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); IRBuilder<> Builder(BB); OpenMPIRBuilder::LocationDescription Loc({Builder.saveIP(), DL}); @@ -2782,6 +2798,7 @@ TEST_F(OpenMPIRBuilderTest, DynamicWorkShareLoopOrdered) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); IRBuilder<> Builder(BB); OpenMPIRBuilder::LocationDescription Loc({Builder.saveIP(), DL}); @@ -4538,6 +4555,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTeams) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -4618,6 +4636,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTeamsWithThreadLimit) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> &Builder = OMPBuilder.Builder; @@ -4674,6 +4693,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTeamsWithNumTeamsUpper) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> &Builder = OMPBuilder.Builder; @@ -4731,6 +4751,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTeamsWithNumTeamsBoth) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> &Builder = OMPBuilder.Builder; @@ -4791,6 +4812,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTeamsWithNumTeamsAndThreadLimit) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> &Builder = OMPBuilder.Builder; @@ -4857,6 +4879,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTeamsWithIfCondition) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> &Builder = OMPBuilder.Builder; @@ -4920,6 +4943,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTeamsWithIfConditionAndNumTeams) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> &Builder = OMPBuilder.Builder; @@ -5122,6 +5146,7 @@ TEST_F(OpenMPIRBuilderTest, CreateReductions) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -5504,6 +5529,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTwoReductions) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -6511,6 +6537,12 @@ TEST_F(OpenMPIRBuilderTest, TargetRegion) { } TEST_F(OpenMPIRBuilderTest, TargetRegionDevice) { + M->setTargetTriple(Triple("amdgcn-amd-amdhsa")); + std::string oldDLStr = M->getDataLayoutStr(); + M->setDataLayout("e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:" + "32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:" + "64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-" + "v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"); OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.setConfig( OpenMPIRBuilderConfig(true, false, false, false, false, false, false)); @@ -6628,19 +6660,24 @@ TEST_F(OpenMPIRBuilderTest, TargetRegionDevice) { EXPECT_NE(Alloca1, nullptr); EXPECT_TRUE(isa(Alloca1)); - auto *Store1 = Alloca1->getNextNode(); + auto *AsCast1 = Alloca1->getNextNode(); + EXPECT_TRUE(isa(AsCast1)); + auto *Store1 = AsCast1->getNextNode(); EXPECT_TRUE(isa(Store1)); auto *Alloca2 = Store1->getNextNode(); EXPECT_TRUE(isa(Alloca2)); - auto *Store2 = Alloca2->getNextNode(); + auto *AsCast2 = Alloca2->getNextNode(); + EXPECT_TRUE(isa(AsCast2)); + auto *Store2 = AsCast2->getNextNode(); EXPECT_TRUE(isa(Store2)); auto *InitCall = dyn_cast(Store2->getNextNode()); EXPECT_NE(InitCall, nullptr); EXPECT_EQ(InitCall->getCalledFunction()->getName(), "__kmpc_target_init"); EXPECT_EQ(InitCall->arg_size(), 2U); - EXPECT_TRUE(isa(InitCall->getArgOperand(0))); - auto *KernelEnvGV = cast(InitCall->getArgOperand(0)); + EXPECT_TRUE(isa(InitCall->getArgOperand(0)->stripPointerCasts())); + auto *KernelEnvGV = + cast(InitCall->getArgOperand(0)->stripPointerCasts()); EXPECT_TRUE(isa(KernelEnvGV->getInitializer())); auto *KernelEnvC = cast(KernelEnvGV->getInitializer()); EXPECT_TRUE(isa(KernelEnvC->getAggregateElement(0U))); @@ -6696,13 +6733,14 @@ TEST_F(OpenMPIRBuilderTest, TargetRegionDevice) { EXPECT_TRUE(isa(UsedInit)); auto *UsedInitData = cast(UsedInit); EXPECT_EQ(1U, UsedInitData->getNumOperands()); - Constant *ExecMode = UsedInitData->getOperand(0); + Constant *ExecMode = UsedInitData->getOperand(0)->stripPointerCasts(); EXPECT_TRUE(isa(ExecMode)); Constant *ExecModeValue = cast(ExecMode)->getInitializer(); EXPECT_NE(ExecModeValue, nullptr); EXPECT_TRUE(isa(ExecModeValue)); EXPECT_EQ(OMP_TGT_EXEC_MODE_GENERIC, cast(ExecModeValue)->getZExtValue()); + M->setDataLayout(oldDLStr); } TEST_F(OpenMPIRBuilderTest, TargetRegionSPMD) { @@ -6809,6 +6847,7 @@ TEST_F(OpenMPIRBuilderTest, TargetRegionSPMD) { } TEST_F(OpenMPIRBuilderTest, TargetRegionDeviceSPMD) { + M->setTargetTriple(Triple("amdgcn-amd-amdgpu")); OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.setConfig( OpenMPIRBuilderConfig(/*IsTargetDevice=*/true, /*IsGPU=*/false, @@ -6905,6 +6944,12 @@ TEST_F(OpenMPIRBuilderTest, TargetRegionDeviceSPMD) { } TEST_F(OpenMPIRBuilderTest, ConstantAllocaRaise) { + M->setTargetTriple(Triple("amdgcn-amd-amdhsa")); + std::string oldDLStr = M->getDataLayoutStr(); + M->setDataLayout("e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:" + "32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:" + "64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-" + "v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"); OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.setConfig( OpenMPIRBuilderConfig(true, false, false, false, false, false, false)); @@ -7023,15 +7068,17 @@ TEST_F(OpenMPIRBuilderTest, ConstantAllocaRaise) { // inappropriately with our alloca movement. auto *Alloca2 = Alloca1->getNextNode(); EXPECT_TRUE(isa(Alloca2)); - auto *Store2 = Alloca2->getNextNode(); + auto *AsCast1 = Alloca2->getNextNode(); + EXPECT_TRUE(isa(AsCast1)); + auto *Store2 = AsCast1->getNextNode(); EXPECT_TRUE(isa(Store2)); auto *InitCall = dyn_cast(Store2->getNextNode()); EXPECT_NE(InitCall, nullptr); EXPECT_EQ(InitCall->getCalledFunction()->getName(), "__kmpc_target_init"); EXPECT_EQ(InitCall->arg_size(), 2U); - EXPECT_TRUE(isa(InitCall->getArgOperand(0))); - auto *KernelEnvGV = cast(InitCall->getArgOperand(0)); + EXPECT_TRUE(isa(InitCall->getArgOperand(0)->stripPointerCasts())); + auto *KernelEnvGV = cast(InitCall->getArgOperand(0)->stripPointerCasts()); EXPECT_TRUE(isa(KernelEnvGV->getInitializer())); auto *KernelEnvC = cast(KernelEnvGV->getInitializer()); EXPECT_TRUE(isa(KernelEnvC->getAggregateElement(0U))); @@ -7077,12 +7124,14 @@ TEST_F(OpenMPIRBuilderTest, ConstantAllocaRaise) { auto *ExitBlock = EntryBlockBranch->getSuccessor(1); EXPECT_EQ(ExitBlock->getName(), "worker.exit"); EXPECT_TRUE(isa(ExitBlock->getFirstNonPHIIt())); + M->setDataLayout(oldDLStr); } TEST_F(OpenMPIRBuilderTest, CreateTask) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -7216,6 +7265,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTaskNoArgs) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -7252,6 +7302,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTaskUntied) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -7288,6 +7339,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTaskDepend) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -7368,6 +7420,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTaskFinal) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -7426,6 +7479,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTaskIfCondition) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); @@ -7595,6 +7649,7 @@ TEST_F(OpenMPIRBuilderTest, CreateTaskgroupWithTasks) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); OMPBuilder.Config.IsTargetDevice = false; + OMPBuilder.Config.IsGPU = false; OMPBuilder.initialize(); F->setName("func"); IRBuilder<> Builder(BB); diff --git a/llvm/unittests/IR/DebugInfoTest.cpp b/llvm/unittests/IR/DebugInfoTest.cpp index 060f45d858746..3d9faf5919e32 100644 --- a/llvm/unittests/IR/DebugInfoTest.cpp +++ b/llvm/unittests/IR/DebugInfoTest.cpp @@ -473,8 +473,9 @@ TEST(DIBuilder, CreateStringType) { DINode::FlagZero, DISubprogram::SPFlagZero, nullptr); DIFile *F = DIB.createFile("main.c", "/"); StringRef StrName = "string"; - DIVariable *StringLen = DIB.createAutoVariable(Scope, StrName, F, 0, nullptr, - false, DINode::FlagZero, 0); + DIVariable *StringLen = + DIB.createAutoVariable(Scope, StrName, F, 0, nullptr, false, + DINode::FlagZero, dwarf::DW_MSPACE_LLVM_none, 0); auto getDIExpression = [&DIB](int offset) { SmallVector ops; ops.push_back(llvm::dwarf::DW_OP_push_object_address); @@ -1425,7 +1426,7 @@ TEST(DIBuilder, DynamicOffsetAndSize) { DIFile *F = DIB.createFile("main.adb", "/"); DIVariable *Len = DIB.createAutoVariable(Scope, "length", F, 0, nullptr, - false, DINode::FlagZero, 0); + false, DINode::FlagZero, dwarf::DW_MSPACE_LLVM_none, 0); DICompositeType *Struct = DIB.createStructType( Scope, "some_record", F, 18, Len, 8, DINode::FlagZero, nullptr, {}); diff --git a/llvm/unittests/IR/MetadataTest.cpp b/llvm/unittests/IR/MetadataTest.cpp index 85c79d13ae7ce..97e1f4427e183 100644 --- a/llvm/unittests/IR/MetadataTest.cpp +++ b/llvm/unittests/IR/MetadataTest.cpp @@ -10,6 +10,7 @@ #include "../lib/IR/LLVMContextImpl.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/BinaryFormat/Dwarf.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DIBuilder.h" #include "llvm/IR/DebugInfo.h" @@ -112,7 +113,8 @@ class MetadataTest : public testing::Test { DIType *getDerivedType() { return DIDerivedType::getDistinct( Context, dwarf::DW_TAG_pointer_type, "", nullptr, 0, nullptr, - getBasicType("basictype"), 1, 2, 0, std::nullopt, {}, DINode::FlagZero); + getBasicType("basictype"), 1, 2, 0, std::nullopt, + dwarf::DW_MSPACE_LLVM_none, {}, DINode::FlagZero); } Constant *getConstant() { return ConstantInt::get(Type::getInt32Ty(Context), Counter++); @@ -439,6 +441,7 @@ TEST_F(MDNodeTest, PrintTree) { DIType *Type = getDerivedType(); auto *Var = DILocalVariable::get(Context, Scope, "foo", File, /*LineNo=*/8, Type, /*ArgNo=*/2, Flags, + dwarf::DW_MSPACE_LLVM_none, /*Align=*/8, nullptr); std::string Expected; { @@ -467,11 +470,12 @@ TEST_F(MDNodeTest, PrintTree) { auto *StructTy = cast(getCompositeType()); DIType *PointerTy = DIDerivedType::getDistinct( Context, dwarf::DW_TAG_pointer_type, "", nullptr, 0, nullptr, StructTy, - 1, 2, 0, std::nullopt, {}, DINode::FlagZero); + 1, 2, 0, std::nullopt, dwarf::DW_MSPACE_LLVM_none, {}, DINode::FlagZero); StructTy->replaceElements(MDTuple::get(Context, PointerTy)); auto *Var = DILocalVariable::get(Context, Scope, "foo", File, /*LineNo=*/8, StructTy, /*ArgNo=*/2, Flags, + dwarf::DW_MSPACE_LLVM_none, /*Align=*/8, nullptr); std::string Expected; { @@ -1852,8 +1856,9 @@ TEST_F(DISubrangeTest, getVariableCount) { DIFile *File = getFile(); DIType *Type = getDerivedType(); DINode::DIFlags Flags = static_cast(7); - auto *VlaExpr = DILocalVariable::get(Context, Scope, "vla_expr", File, 8, - Type, 2, Flags, 8, nullptr); + auto *VlaExpr = + DILocalVariable::get(Context, Scope, "vla_expr", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); auto *N = DISubrange::get(Context, VlaExpr, 0); auto Count = N->getCount(); @@ -1880,8 +1885,9 @@ TEST_F(DISubrangeTest, fortranAllocatableInt) { ConstantInt::getSigned(Type::getInt64Ty(Context), 4)); auto *UIother = ConstantAsMetadata::get( ConstantInt::getSigned(Type::getInt64Ty(Context), 20)); - auto *UVother = DILocalVariable::get(Context, Scope, "ubother", File, 8, Type, - 2, Flags, 8, nullptr); + auto *UVother = + DILocalVariable::get(Context, Scope, "ubother", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); auto *UEother = DIExpression::get(Context, {5, 6}); auto *LIZero = ConstantAsMetadata::get( ConstantInt::getSigned(Type::getInt64Ty(Context), 0)); @@ -1923,17 +1929,15 @@ TEST_F(DISubrangeTest, fortranAllocatableVar) { DIFile *File = getFile(); DIType *Type = getDerivedType(); DINode::DIFlags Flags = static_cast(7); - auto *LV = - DILocalVariable::get(Context, Scope, "lb", File, 8, Type, 2, Flags, 8, - nullptr); - auto *UV = - DILocalVariable::get(Context, Scope, "ub", File, 8, Type, 2, Flags, 8, - nullptr); - auto *SV = - DILocalVariable::get(Context, Scope, "st", File, 8, Type, 2, Flags, 8, - nullptr); - auto *SVother = DILocalVariable::get(Context, Scope, "stother", File, 8, Type, - 2, Flags, 8, nullptr); + auto *LV = DILocalVariable::get(Context, Scope, "lb", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); + auto *UV = DILocalVariable::get(Context, Scope, "ub", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); + auto *SV = DILocalVariable::get(Context, Scope, "st", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); + auto *SVother = + DILocalVariable::get(Context, Scope, "stother", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); auto *SIother = ConstantAsMetadata::get( ConstantInt::getSigned(Type::getInt64Ty(Context), 20)); auto *SEother = DIExpression::get(Context, {5, 6}); @@ -1973,8 +1977,9 @@ TEST_F(DISubrangeTest, fortranAllocatableExpr) { auto *LEother = DIExpression::get(Context, {5, 6}); auto *LIother = ConstantAsMetadata::get( ConstantInt::getSigned(Type::getInt64Ty(Context), 20)); - auto *LVother = DILocalVariable::get(Context, Scope, "lbother", File, 8, Type, - 2, Flags, 8, nullptr); + auto *LVother = + DILocalVariable::get(Context, Scope, "lbother", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); auto *N = DISubrange::get(Context, nullptr, LE, UE, SE); @@ -2045,8 +2050,9 @@ TEST_F(DIGenericSubrangeTest, fortranAssumedRankInt) { auto *UI = DIExpression::get(Context, {dwarf::DW_OP_consts, 10}); auto *SI = DIExpression::get(Context, {dwarf::DW_OP_consts, 4}); auto *UIother = DIExpression::get(Context, {dwarf::DW_OP_consts, 20}); - auto *UVother = DILocalVariable::get(Context, Scope, "ubother", File, 8, Type, - 2, Flags, 8, nullptr); + auto *UVother = + DILocalVariable::get(Context, Scope, "ubother", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); auto *UEother = DIExpression::get(Context, {5, 6}); auto *LIZero = DIExpression::get(Context, {dwarf::DW_OP_consts, 0}); auto *UIZero = DIExpression::get(Context, {dwarf::DW_OP_consts, 0}); @@ -2088,17 +2094,15 @@ TEST_F(DIGenericSubrangeTest, fortranAssumedRankVar) { DIFile *File = getFile(); DIType *Type = getDerivedType(); DINode::DIFlags Flags = static_cast(7); - auto *LV = - DILocalVariable::get(Context, Scope, "lb", File, 8, Type, 2, Flags, 8, - nullptr); - auto *UV = - DILocalVariable::get(Context, Scope, "ub", File, 8, Type, 2, Flags, 8, - nullptr); - auto *SV = - DILocalVariable::get(Context, Scope, "st", File, 8, Type, 2, Flags, 8, - nullptr); - auto *SVother = DILocalVariable::get(Context, Scope, "stother", File, 8, Type, - 2, Flags, 8, nullptr); + auto *LV = DILocalVariable::get(Context, Scope, "lb", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); + auto *UV = DILocalVariable::get(Context, Scope, "ub", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); + auto *SV = DILocalVariable::get(Context, Scope, "st", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); + auto *SVother = + DILocalVariable::get(Context, Scope, "stother", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); auto *SIother = DIExpression::get( Context, {dwarf::DW_OP_consts, static_cast(-1)}); auto *SEother = DIExpression::get(Context, {5, 6}); @@ -2132,13 +2136,14 @@ TEST_F(DIGenericSubrangeTest, useDIBuilder) { DIFile *File = getFile(); DIType *Type = getDerivedType(); DINode::DIFlags Flags = static_cast(7); - auto *LV = - DILocalVariable::get(Context, Scope, "lb", File, 8, Type, 2, Flags, 8, nullptr); + auto *LV = DILocalVariable::get(Context, Scope, "lb", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); auto *UE = DIExpression::get(Context, {2, 3}); auto *SE = DIExpression::get(Context, {3, 4}); - auto *LVother = DILocalVariable::get(Context, Scope, "lbother", File, 8, Type, - 2, Flags, 8, nullptr); + auto *LVother = + DILocalVariable::get(Context, Scope, "lbother", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); auto *LIother = DIExpression::get( Context, {dwarf::DW_OP_consts, static_cast(-1)}); @@ -2306,17 +2311,20 @@ TEST_F(DIDerivedTypeTest, get) { DIType *BaseType = getBasicType("basic"); MDTuple *ExtraData = getTuple(); unsigned DWARFAddressSpace = 8; + auto DWARFMemorySpace = dwarf::DW_MSPACE_LLVM_private; DIDerivedType::PtrAuthData PtrAuthData(1, false, 1234, true, true); DIDerivedType::PtrAuthData PtrAuthData2(1, false, 1234, true, false); DINode::DIFlags Flags5 = static_cast(5); DINode::DIFlags Flags4 = static_cast(4); - auto *N = DIDerivedType::get( - Context, dwarf::DW_TAG_pointer_type, "something", File, 1, Scope, - BaseType, 2, 3, 4, DWARFAddressSpace, std::nullopt, Flags5, ExtraData); + auto *N = + DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, + 1, Scope, BaseType, 2, 3, 4, DWARFAddressSpace, + DWARFMemorySpace, std::nullopt, Flags5, ExtraData); auto *N1 = DIDerivedType::get(Context, dwarf::DW_TAG_LLVM_ptrauth_type, "", File, 1, Scope, N, 2, 3, 4, DWARFAddressSpace, - PtrAuthData, Flags5, ExtraData); + DWARFMemorySpace, PtrAuthData, Flags5, ExtraData); + EXPECT_EQ(dwarf::DW_TAG_pointer_type, N->getTag()); EXPECT_EQ("something", N->getName()); EXPECT_EQ(File, N->getFile()); @@ -2327,6 +2335,7 @@ TEST_F(DIDerivedTypeTest, get) { EXPECT_EQ(3u, N->getAlignInBits()); EXPECT_EQ(4u, N->getOffsetInBits()); EXPECT_EQ(DWARFAddressSpace, *N->getDWARFAddressSpace()); + EXPECT_EQ(dwarf::DW_MSPACE_LLVM_private, N->getDWARFMemorySpace()); EXPECT_EQ(std::nullopt, N->getPtrAuthData()); EXPECT_EQ(PtrAuthData, N1->getPtrAuthData()); EXPECT_NE(PtrAuthData2, N1->getPtrAuthData()); @@ -2334,61 +2343,61 @@ TEST_F(DIDerivedTypeTest, get) { EXPECT_EQ(ExtraData, N->getExtraData()); EXPECT_EQ(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, 1, Scope, BaseType, 2, 3, - 4, DWARFAddressSpace, std::nullopt, Flags5, - ExtraData)); + 4, DWARFAddressSpace, DWARFMemorySpace, + std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_reference_type, "something", File, 1, Scope, BaseType, 2, 3, - 4, DWARFAddressSpace, std::nullopt, Flags5, - ExtraData)); + 4, DWARFAddressSpace, DWARFMemorySpace, + std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "else", File, 1, Scope, BaseType, 2, 3, 4, - DWARFAddressSpace, std::nullopt, Flags5, + DWARFAddressSpace, DWARFMemorySpace, std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", getFile(), 1, Scope, BaseType, 2, - 3, 4, DWARFAddressSpace, std::nullopt, Flags5, - ExtraData)); + 3, 4, DWARFAddressSpace, DWARFMemorySpace, + std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, 2, Scope, BaseType, 2, 3, - 4, DWARFAddressSpace, std::nullopt, Flags5, - ExtraData)); + 4, DWARFAddressSpace, DWARFMemorySpace, + std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, 1, getSubprogram(), BaseType, 2, 3, 4, DWARFAddressSpace, - std::nullopt, Flags5, ExtraData)); + DWARFMemorySpace, std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get( Context, dwarf::DW_TAG_pointer_type, "something", File, 1, Scope, getBasicType("basic2"), 2, 3, 4, DWARFAddressSpace, - std::nullopt, Flags5, ExtraData)); + DWARFMemorySpace, std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, 1, Scope, BaseType, 3, 3, - 4, DWARFAddressSpace, std::nullopt, Flags5, - ExtraData)); + 4, DWARFAddressSpace, DWARFMemorySpace, + std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, 1, Scope, BaseType, 2, 2, - 4, DWARFAddressSpace, std::nullopt, Flags5, - ExtraData)); + 4, DWARFAddressSpace, DWARFMemorySpace, + std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, 1, Scope, BaseType, 2, 3, - 5, DWARFAddressSpace, std::nullopt, Flags5, - ExtraData)); + 5, DWARFAddressSpace, DWARFMemorySpace, + std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, 1, Scope, BaseType, 2, 3, - 4, DWARFAddressSpace + 1, std::nullopt, - Flags5, ExtraData)); - EXPECT_NE(N1, - DIDerivedType::get(Context, dwarf::DW_TAG_LLVM_ptrauth_type, "", - File, 1, Scope, N, 2, 3, 4, DWARFAddressSpace, - std::nullopt, Flags5, ExtraData)); + 4, DWARFAddressSpace + 1, DWARFMemorySpace, + std::nullopt, Flags5, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, 1, Scope, BaseType, 2, 3, - 4, DWARFAddressSpace, std::nullopt, Flags4, - ExtraData)); + 4, DWARFAddressSpace, DWARFMemorySpace, + std::nullopt, Flags4, ExtraData)); EXPECT_NE(N, DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, 1, Scope, BaseType, 2, 3, - 4, DWARFAddressSpace, std::nullopt, Flags5, - getTuple())); + 4, DWARFAddressSpace, DWARFMemorySpace, + std::nullopt, Flags5, getTuple())); + EXPECT_NE(N, DIDerivedType::get( + Context, dwarf::DW_TAG_pointer_type, "something", File, 1, + Scope, BaseType, 2, 3, 4, DWARFAddressSpace, + dwarf::DW_MSPACE_LLVM_global, std::nullopt, Flags5, ExtraData)); TempDIDerivedType Temp = N->clone(); EXPECT_EQ(N, MDNode::replaceWithUniqued(std::move(Temp))); @@ -2406,7 +2415,7 @@ TEST_F(DIDerivedTypeTest, getWithLargeValues) { auto *N = DIDerivedType::get(Context, dwarf::DW_TAG_pointer_type, "something", File, 1, Scope, BaseType, UINT64_MAX, UINT32_MAX - 1, UINT64_MAX - 2, UINT32_MAX - 3, - std::nullopt, Flags, ExtraData); + dwarf::DW_MSPACE_LLVM_none, std::nullopt, Flags, ExtraData); EXPECT_EQ(UINT64_MAX, N->getSizeInBits()); EXPECT_EQ(UINT32_MAX - 1, N->getAlignInBits()); EXPECT_EQ(UINT64_MAX - 2, N->getOffsetInBits()); @@ -2415,8 +2424,8 @@ TEST_F(DIDerivedTypeTest, getWithLargeValues) { auto *N1 = DIDerivedType::get( Context, dwarf::DW_TAG_LLVM_ptrauth_type, "", File, 1, Scope, N, UINT64_MAX, UINT32_MAX - 1, UINT64_MAX - 2, UINT32_MAX - 3, - DIDerivedType::PtrAuthData(7, true, 0xffff, true, false), Flags, - ExtraData); + dwarf::DW_MSPACE_LLVM_none, DIDerivedType::PtrAuthData(7, true, 0xffff, true, false), + Flags, ExtraData); EXPECT_EQ(7U, N1->getPtrAuthData()->key()); EXPECT_EQ(true, N1->getPtrAuthData()->isAddressDiscriminated()); EXPECT_EQ(0xffffU, N1->getPtrAuthData()->extraDiscriminator()); @@ -2687,10 +2696,12 @@ TEST_F(DICompositeTypeTest, dynamicArray) { std::optional EnumKind = 1; StringRef Identifier = "some id"; DIType *Type = getDerivedType(); - Metadata *DlVar1 = DILocalVariable::get(Context, Scope, "dl_var1", File, 8, - Type, 2, Flags, 8, nullptr); - Metadata *DlVar2 = DILocalVariable::get(Context, Scope, "dl_var2", File, 8, - Type, 2, Flags, 8, nullptr); + Metadata *DlVar1 = + DILocalVariable::get(Context, Scope, "dl_var1", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); + Metadata *DlVar2 = + DILocalVariable::get(Context, Scope, "dl_var2", File, 8, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); uint64_t Elements1[] = {dwarf::DW_OP_push_object_address, dwarf::DW_OP_deref}; Metadata *DataLocation1 = DIExpression::get(Context, Elements1); @@ -3398,13 +3409,14 @@ TEST_F(DIGlobalVariableTest, get) { MDTuple *templateParams = getTuple(); DIDerivedType *StaticDataMemberDeclaration = cast(getDerivedType()); + const auto DWARFMemorySpace = dwarf::DW_MSPACE_LLVM_none; uint32_t AlignInBits = 8; - auto *N = DIGlobalVariable::get( - Context, Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, - IsDefinition, StaticDataMemberDeclaration, templateParams, AlignInBits, - nullptr); + auto *N = DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, Line, + Type, IsLocalToUnit, IsDefinition, + StaticDataMemberDeclaration, templateParams, + DWARFMemorySpace, AlignInBits, nullptr); EXPECT_EQ(dwarf::DW_TAG_variable, N->getTag()); EXPECT_EQ(Scope, N->getScope()); @@ -3418,57 +3430,65 @@ TEST_F(DIGlobalVariableTest, get) { EXPECT_EQ(StaticDataMemberDeclaration, N->getStaticDataMemberDeclaration()); EXPECT_EQ(templateParams, N->getTemplateParams()); EXPECT_EQ(AlignInBits, N->getAlignInBits()); - EXPECT_EQ(N, DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, - Line, Type, IsLocalToUnit, IsDefinition, - StaticDataMemberDeclaration, - templateParams, AlignInBits, nullptr)); + EXPECT_EQ(DWARFMemorySpace, N->getDWARFMemorySpace()); + EXPECT_EQ(N, DIGlobalVariable::get( + Context, Scope, Name, LinkageName, File, Line, Type, + IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration, + templateParams, DWARFMemorySpace, AlignInBits, nullptr)); + EXPECT_NE(N, + DIGlobalVariable::get(Context, getSubprogram(), Name, LinkageName, + File, Line, Type, IsLocalToUnit, IsDefinition, + StaticDataMemberDeclaration, templateParams, + DWARFMemorySpace, AlignInBits, nullptr)); EXPECT_NE(N, DIGlobalVariable::get( - Context, getSubprogram(), Name, LinkageName, File, Line, - Type, IsLocalToUnit, IsDefinition, - StaticDataMemberDeclaration, templateParams, AlignInBits, - nullptr)); - EXPECT_NE(N, DIGlobalVariable::get(Context, Scope, "other", LinkageName, File, - Line, Type, IsLocalToUnit, IsDefinition, - StaticDataMemberDeclaration, - templateParams, AlignInBits, nullptr)); - EXPECT_NE(N, DIGlobalVariable::get(Context, Scope, Name, "other", File, Line, - Type, IsLocalToUnit, IsDefinition, - StaticDataMemberDeclaration, - templateParams, AlignInBits, nullptr)); - EXPECT_NE(N, DIGlobalVariable::get(Context, Scope, Name, LinkageName, - getFile(), Line, Type, IsLocalToUnit, - IsDefinition, StaticDataMemberDeclaration, - templateParams, AlignInBits, nullptr)); - EXPECT_NE(N, DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, - Line + 1, Type, IsLocalToUnit, - IsDefinition, StaticDataMemberDeclaration, - templateParams, AlignInBits, nullptr)); - EXPECT_NE(N, DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, - Line, getDerivedType(), IsLocalToUnit, - IsDefinition, StaticDataMemberDeclaration, - templateParams, AlignInBits, nullptr)); - EXPECT_NE(N, DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, - Line, Type, !IsLocalToUnit, IsDefinition, - StaticDataMemberDeclaration, - templateParams, AlignInBits, nullptr)); - EXPECT_NE(N, DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, - Line, Type, IsLocalToUnit, !IsDefinition, - StaticDataMemberDeclaration, - templateParams, AlignInBits, nullptr)); + Context, Scope, "other", LinkageName, File, Line, Type, + IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration, + templateParams, DWARFMemorySpace, AlignInBits, nullptr)); + EXPECT_NE(N, DIGlobalVariable::get( + Context, Scope, Name, "other", File, Line, Type, + IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration, + templateParams, DWARFMemorySpace, AlignInBits, nullptr)); + EXPECT_NE(N, DIGlobalVariable::get( + Context, Scope, Name, LinkageName, getFile(), Line, Type, + IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration, + templateParams, DWARFMemorySpace, AlignInBits, nullptr)); + EXPECT_NE(N, DIGlobalVariable::get( + Context, Scope, Name, LinkageName, File, Line + 1, Type, + IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration, + templateParams, DWARFMemorySpace, AlignInBits, nullptr)); + EXPECT_NE(N, + DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, Line, + getDerivedType(), IsLocalToUnit, IsDefinition, + StaticDataMemberDeclaration, templateParams, + DWARFMemorySpace, AlignInBits, nullptr)); + EXPECT_NE(N, DIGlobalVariable::get( + Context, Scope, Name, LinkageName, File, Line, Type, + !IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration, + templateParams, DWARFMemorySpace, AlignInBits, nullptr)); + EXPECT_NE(N, DIGlobalVariable::get( + Context, Scope, Name, LinkageName, File, Line, Type, + IsLocalToUnit, !IsDefinition, StaticDataMemberDeclaration, + templateParams, DWARFMemorySpace, AlignInBits, nullptr)); EXPECT_NE(N, DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, IsDefinition, cast(getDerivedType()), - templateParams, AlignInBits, nullptr)); + templateParams, DWARFMemorySpace, + AlignInBits, nullptr)); EXPECT_NE(N, DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration, nullptr, - AlignInBits, nullptr)); + DWARFMemorySpace, AlignInBits, nullptr)); EXPECT_NE(N, DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration, - templateParams, (AlignInBits << 1), - nullptr)); + templateParams, DWARFMemorySpace, + (AlignInBits << 1), nullptr)); + EXPECT_NE(N, DIGlobalVariable::get( + Context, Scope, Name, LinkageName, File, Line, Type, + IsLocalToUnit, IsDefinition, StaticDataMemberDeclaration, + templateParams, dwarf::DW_MSPACE_LLVM_constant, AlignInBits, + nullptr)); TempDIGlobalVariable Temp = N->clone(); EXPECT_EQ(N, MDNode::replaceWithUniqued(std::move(Temp))); @@ -3486,20 +3506,21 @@ TEST_F(DIGlobalVariableExpressionTest, get) { bool IsLocalToUnit = false; bool IsDefinition = true; MDTuple *templateParams = getTuple(); + const auto DWARFMemorySpace = dwarf::DW_MSPACE_LLVM_none; auto *Expr = DIExpression::get(Context, {1, 2}); auto *Expr2 = DIExpression::get(Context, {1, 2, 3}); DIDerivedType *StaticDataMemberDeclaration = cast(getDerivedType()); uint32_t AlignInBits = 8; - auto *Var = DIGlobalVariable::get( - Context, Scope, Name, LinkageName, File, Line, Type, IsLocalToUnit, - IsDefinition, StaticDataMemberDeclaration, templateParams, AlignInBits, - nullptr); + auto *Var = DIGlobalVariable::get(Context, Scope, Name, LinkageName, File, + Line, Type, IsLocalToUnit, IsDefinition, + StaticDataMemberDeclaration, templateParams, + DWARFMemorySpace, AlignInBits, nullptr); auto *Var2 = DIGlobalVariable::get( Context, Scope, "other", LinkageName, File, Line, Type, IsLocalToUnit, - IsDefinition, StaticDataMemberDeclaration, templateParams, AlignInBits, - nullptr); + IsDefinition, StaticDataMemberDeclaration, templateParams, + DWARFMemorySpace, AlignInBits, nullptr); auto *N = DIGlobalVariableExpression::get(Context, Var, Expr); EXPECT_EQ(Var, N->getVariable()); @@ -3522,11 +3543,11 @@ TEST_F(DILocalVariableTest, get) { DIType *Type = getDerivedType(); unsigned Arg = 6; DINode::DIFlags Flags = static_cast(7); + const auto DWARFMemorySpace = dwarf::DW_MSPACE_LLVM_none; uint32_t AlignInBits = 8; - auto *N = - DILocalVariable::get(Context, Scope, Name, File, Line, Type, Arg, Flags, - AlignInBits, nullptr); + auto *N = DILocalVariable::get(Context, Scope, Name, File, Line, Type, Arg, + Flags, DWARFMemorySpace, AlignInBits, nullptr); EXPECT_TRUE(N->isParameter()); EXPECT_EQ(Scope, N->getScope()); EXPECT_EQ(Name, N->getName()); @@ -3535,28 +3556,40 @@ TEST_F(DILocalVariableTest, get) { EXPECT_EQ(Type, N->getType()); EXPECT_EQ(Arg, N->getArg()); EXPECT_EQ(Flags, N->getFlags()); + EXPECT_EQ(DWARFMemorySpace, N->getDWARFMemorySpace()); EXPECT_EQ(AlignInBits, N->getAlignInBits()); EXPECT_EQ(N, DILocalVariable::get(Context, Scope, Name, File, Line, Type, Arg, - Flags, AlignInBits, nullptr)); + Flags, DWARFMemorySpace, AlignInBits, + nullptr)); - EXPECT_FALSE( - DILocalVariable::get(Context, Scope, Name, File, Line, Type, 0, Flags, - AlignInBits, nullptr)->isParameter()); + EXPECT_FALSE(DILocalVariable::get(Context, Scope, Name, File, Line, Type, 0, + Flags, DWARFMemorySpace, AlignInBits, + nullptr) + ->isParameter()); EXPECT_NE(N, DILocalVariable::get(Context, getSubprogram(), Name, File, Line, - Type, Arg, Flags, AlignInBits, nullptr)); + Type, Arg, Flags, DWARFMemorySpace, + AlignInBits, nullptr)); EXPECT_NE(N, DILocalVariable::get(Context, Scope, "other", File, Line, Type, - Arg, Flags, AlignInBits, nullptr)); + Arg, Flags, DWARFMemorySpace, AlignInBits, + nullptr)); EXPECT_NE(N, DILocalVariable::get(Context, Scope, Name, getFile(), Line, Type, - Arg, Flags, AlignInBits, nullptr)); + Arg, Flags, DWARFMemorySpace, AlignInBits, + nullptr)); EXPECT_NE(N, DILocalVariable::get(Context, Scope, Name, File, Line + 1, Type, - Arg, Flags, AlignInBits, nullptr)); - EXPECT_NE(N, DILocalVariable::get(Context, Scope, Name, File, Line, - getDerivedType(), Arg, Flags, AlignInBits, + Arg, Flags, DWARFMemorySpace, AlignInBits, nullptr)); + EXPECT_NE(N, DILocalVariable::get(Context, Scope, Name, File, Line, + getDerivedType(), Arg, Flags, + DWARFMemorySpace, AlignInBits, nullptr)); EXPECT_NE(N, DILocalVariable::get(Context, Scope, Name, File, Line, Type, - Arg + 1, Flags, AlignInBits, nullptr)); - EXPECT_NE(N, DILocalVariable::get(Context, Scope, Name, File, Line, Type, - Arg, Flags, (AlignInBits << 1), nullptr)); + Arg + 1, Flags, DWARFMemorySpace, + AlignInBits, nullptr)); + EXPECT_NE(N, DILocalVariable::get(Context, Scope, Name, File, Line, Type, Arg, + Flags, DWARFMemorySpace, (AlignInBits << 1), + nullptr)); + EXPECT_NE(N, DILocalVariable::get(Context, Scope, Name, File, Line, Type, Arg, + Flags, dwarf::DW_MSPACE_LLVM_private, + AlignInBits, nullptr)); TempDILocalVariable Temp = N->clone(); EXPECT_EQ(N, MDNode::replaceWithUniqued(std::move(Temp))); @@ -3564,21 +3597,21 @@ TEST_F(DILocalVariableTest, get) { TEST_F(DILocalVariableTest, getArg256) { EXPECT_EQ(255u, DILocalVariable::get(Context, getSubprogram(), "", getFile(), - 0, nullptr, 255, DINode::FlagZero, 0, - nullptr) + 0, nullptr, 255, DINode::FlagZero, + dwarf::DW_MSPACE_LLVM_none, 0, nullptr) ->getArg()); EXPECT_EQ(256u, DILocalVariable::get(Context, getSubprogram(), "", getFile(), - 0, nullptr, 256, DINode::FlagZero, 0, - nullptr) + 0, nullptr, 256, DINode::FlagZero, + dwarf::DW_MSPACE_LLVM_none, 0, nullptr) ->getArg()); EXPECT_EQ(257u, DILocalVariable::get(Context, getSubprogram(), "", getFile(), - 0, nullptr, 257, DINode::FlagZero, 0, - nullptr) + 0, nullptr, 257, DINode::FlagZero, + dwarf::DW_MSPACE_LLVM_none, 0, nullptr) ->getArg()); unsigned Max = UINT16_MAX; EXPECT_EQ(Max, DILocalVariable::get(Context, getSubprogram(), "", getFile(), - 0, nullptr, Max, DINode::FlagZero, 0, - nullptr) + 0, nullptr, Max, DINode::FlagZero, + dwarf::DW_MSPACE_LLVM_none, 0, nullptr) ->getArg()); } @@ -4419,6 +4452,141 @@ TEST_F(DIExpressionTest, extractLeadingOffset) { #undef OPS } +TEST_F(DIExpressionTest, createNewFragmentExpression) { +#define EXPECT_VALID_FRAGMENT(Offset, Size, ...) \ + do { \ + DIOp::Variant Elements[] = {__VA_ARGS__}; \ + DIExpression *Expression = DIExpression::get(Context, bool(), Elements); \ + EXPECT_TRUE( \ + DIExpression::createFragmentExpression(Expression, Offset, Size) \ + .has_value()); \ + } while (false) +#define EXPECT_INVALID_FRAGMENT(Offset, Size, ...) \ + do { \ + DIOp::Variant Elements[] = {__VA_ARGS__}; \ + DIExpression *Expression = DIExpression::get(Context, bool(), Elements); \ + EXPECT_FALSE( \ + DIExpression::createFragmentExpression(Expression, Offset, Size) \ + .has_value()); \ + } while (false) + + IntegerType *IntTy = Type::getInt32Ty(Context); + Type *PtrTy = PointerType::get(Context, 5); + ConstantInt *ConstInt = ConstantInt::get(IntTy, 42); + + EXPECT_VALID_FRAGMENT(0, 16, DIOp::Arg(0, IntTy)); + EXPECT_VALID_FRAGMENT(0, 16, DIOp::Constant(ConstInt)); + EXPECT_VALID_FRAGMENT(0, 16, DIOp::Arg(0, PtrTy), DIOp::Deref(IntTy), + DIOp::Constant(ConstInt), DIOp::BitOffset(IntTy)); + EXPECT_VALID_FRAGMENT(0, 16, DIOp::Arg(0, PtrTy), DIOp::Deref(IntTy), + DIOp::Constant(ConstInt), DIOp::ByteOffset(IntTy)); + EXPECT_VALID_FRAGMENT(0, 16, DIOp::Arg(0, IntTy), DIOp::Fragment(0, 32)); + EXPECT_VALID_FRAGMENT(0, 16, DIOp::Arg(0, IntTy), DIOp::AddrOf(0), + DIOp::Deref(IntTy)); + + EXPECT_VALID_FRAGMENT(8, 16, DIOp::Arg(0, IntTy), DIOp::Deref(IntTy)); + + using VarTy = DIOp::Variant; + for (auto Op : {VarTy(DIOp::Add()), VarTy(DIOp::Sub()), VarTy(DIOp::Mul()), + VarTy(DIOp::Div()), VarTy(DIOp::Shl()), VarTy(DIOp::LShr()), + VarTy(DIOp::AShr())}) { + EXPECT_INVALID_FRAGMENT(0, 16, DIOp::Arg(0, IntTy), + DIOp::Constant(ConstInt), Op); + } + + EXPECT_INVALID_FRAGMENT(0, 16, DIOp::Arg(0, PtrTy), DIOp::Deref(IntTy), + DIOp::Constant(ConstInt), DIOp::Add(), + DIOp::Constant(ConstInt), DIOp::ByteOffset(IntTy)); + + // The same as above, just with a more complicated expression to skip over. + EXPECT_INVALID_FRAGMENT( + 0, 16, DIOp::Arg(0, PtrTy), DIOp::Deref(IntTy), DIOp::Constant(ConstInt), + DIOp::Add(), DIOp::Constant(ConstInt), DIOp::Constant(ConstInt), + DIOp::Sub(), DIOp::Reinterpret(IntTy), DIOp::ByteOffset(IntTy)); + +#undef EXPECT_INVALID_FRAGMENT +#undef EXPECT_VALID_FRAGMENT + + // Verify that fragmenting a fragment work as expected. + DIOp::Variant Ops[] = {DIOp::Arg(0, PtrTy), DIOp::Deref(IntTy), + DIOp::Fragment(8, 16)}; + DIExpression *ArgDerefMid16Expr = DIExpression::get(Context, bool(), Ops); + + DIExpression *Low7Frag = + *DIExpression::createFragmentExpression(ArgDerefMid16Expr, 0, 7); + DIExpression *High9Frag = + *DIExpression::createFragmentExpression(ArgDerefMid16Expr, 7, 9); + + auto Low7FragInfo = *Low7Frag->getFragmentInfo(); + auto High9FragInfo = *High9Frag->getFragmentInfo(); + + EXPECT_EQ(Low7FragInfo.SizeInBits, 7u); + EXPECT_EQ(High9FragInfo.SizeInBits, 9u); + EXPECT_EQ(Low7FragInfo.OffsetInBits, 8u); + EXPECT_EQ(High9FragInfo.OffsetInBits, 15u); +} + +TEST_F(DIExpressionTest, DIOpisEqualExpression) { + auto *IntTy = Type::getInt32Ty(Context); + DIExpression *EmptyOld = DIExpression::get(Context, {}); + DIOp::Variant Ops[] = {DIOp::Arg(0, IntTy)}; + DIExpression *EmptyNew = DIExpression::get(Context, bool(), Ops); + + EXPECT_FALSE( + DIExpression::isEqualExpression(EmptyOld, false, EmptyNew, false)); + EXPECT_FALSE( + DIExpression::isEqualExpression(EmptyNew, true, EmptyNew, false)); + EXPECT_TRUE( + DIExpression::isEqualExpression(EmptyNew, true, EmptyNew, true)); +} + +TEST_F(DIExpressionTest, poisonedFragments) { + // Verify that we retain the fragment info when creating a poisoned expr. + DIOp::Variant Ops[] = {DIOp::Arg(0, Type::getInt32Ty(Context)), + DIOp::Fragment(8, 16)}; + DIExpression *FragDIOpExpr = DIExpression::get(Context, bool(), Ops); + auto ElemsRef = FragDIOpExpr->getElements(); + ASSERT_EQ(ElemsRef.size(), 4u); + EXPECT_EQ(ElemsRef[0], dwarf::DW_OP_LLVM_poisoned); + EXPECT_EQ(ElemsRef[1], dwarf::DW_OP_LLVM_fragment); + EXPECT_EQ(ElemsRef[2], 8u); + EXPECT_EQ(ElemsRef[3], 16u); + + // Verify that we canonicalize poisoned DIExpressions. + auto ExpectCanonical = [&](std::vector Ops, + std::vector CanonOps) { + DIExpression *Expr = DIExpression::get(Context, Ops); + DIExpression *CanonExpr = DIExpression::get(Context, CanonOps); + EXPECT_TRUE(Expr->holdsOldElements()); + EXPECT_EQ(Expr, CanonExpr); + for (unsigned I = 0; I < CanonOps.size(); ++I) + EXPECT_EQ(Expr->getElements()[I], CanonOps[I]); + }; + + ExpectCanonical( + {dwarf::DW_OP_lit0, dwarf::DW_OP_LLVM_poisoned, dwarf::DW_OP_lit1}, + {dwarf::DW_OP_LLVM_poisoned}); + ExpectCanonical( + {dwarf::DW_OP_lit0, dwarf::DW_OP_LLVM_poisoned, dwarf::DW_OP_lit1, + dwarf::DW_OP_LLVM_fragment, 1, 2}, + {dwarf::DW_OP_LLVM_poisoned, dwarf::DW_OP_LLVM_fragment, 1, 2}); + // Just avoid a crash on invalid. + ExpectCanonical({dwarf::DW_OP_LLVM_poisoned, dwarf::DW_OP_LLVM_fragment, 1}, + {dwarf::DW_OP_LLVM_poisoned}); + ExpectCanonical({dwarf::DW_OP_LLVM_fragment, 1, 2}, + {dwarf::DW_OP_LLVM_fragment, 1, 2}); + + // Verify that we handle sub-fragments of poisoned fragments correctly. + uint64_t POps[] = {dwarf::DW_OP_LLVM_poisoned, dwarf::DW_OP_LLVM_fragment, 16, + 32}; + DIExpression *PoisonedFrag = DIExpression::get(Context, POps); + DIExpression *PoisonedSubFrag = + *DIExpression::createFragmentExpression(PoisonedFrag, 8, 8); + uint64_t SubFragOps[] = {dwarf::DW_OP_LLVM_poisoned, + dwarf::DW_OP_LLVM_fragment, 24, 8}; + EXPECT_EQ(PoisonedSubFrag->getElements(), ArrayRef(SubFragOps)); +} + TEST_F(DIExpressionTest, convertToUndefExpression) { #define EXPECT_UNDEF_OPS_EQUAL(TestExpr, Expected) \ do { \ @@ -5306,9 +5474,11 @@ TEST_F(DebugVariableTest, DenseMap) { DILocation *InlinedLoc = DILocation::get(Context, 2, 7, Scope); DILocalVariable *VarA = - DILocalVariable::get(Context, Scope, "A", File, 5, Type, 2, Flags, 8, nullptr); + DILocalVariable::get(Context, Scope, "A", File, 5, Type, 2, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); DILocalVariable *VarB = - DILocalVariable::get(Context, Scope, "B", File, 7, Type, 3, Flags, 8, nullptr); + DILocalVariable::get(Context, Scope, "B", File, 7, Type, 3, Flags, + dwarf::DW_MSPACE_LLVM_none, 8, nullptr); DebugVariable DebugVariableA(VarA, std::nullopt, nullptr); DebugVariable DebugVariableInlineA(VarA, std::nullopt, InlinedLoc); diff --git a/llvm/unittests/IR/PatternMatch.cpp b/llvm/unittests/IR/PatternMatch.cpp index 972dac82d3331..e2bdc06ed5243 100644 --- a/llvm/unittests/IR/PatternMatch.cpp +++ b/llvm/unittests/IR/PatternMatch.cpp @@ -715,9 +715,9 @@ TEST_F(PatternMatchTest, CheckedInt) { CRes = nullptr; EXPECT_EQ(CheckPow2(APVal), m_CheckedInt(CheckPow2).match(C)); EXPECT_EQ(CheckPow2(APVal), m_CheckedInt(CRes, CheckPow2).match(C)); - if (CheckPow2(APVal)) + if (CheckPow2(APVal)) { EXPECT_EQ(CRes, C); - + } }; DoScalarCheck(0); diff --git a/llvm/unittests/Object/OffloadingBundleTest.cpp b/llvm/unittests/Object/OffloadingBundleTest.cpp index 68e7763a0d1eb..06d39fb33644e 100644 --- a/llvm/unittests/Object/OffloadingBundleTest.cpp +++ b/llvm/unittests/Object/OffloadingBundleTest.cpp @@ -51,6 +51,10 @@ toBinary(SmallVectorImpl &Storage, StringRef Yaml) { } TEST(OffloadingBundleTest, checkExtractOffloadBundleFatBinary) { + + // create a Memory Buffer with a fatbin offloading section + MemoryBufferRef mbuf; + StringRef FileName; SmallVector(); SmallString<0> Storage; // Expected> ObjOrErr = toBinary(Storage, R"( @@ -64,6 +68,8 @@ TEST(OffloadingBundleTest, checkExtractOffloadBundleFatBinary) { } TEST(OffloadingBundleTest, checkExtractCodeObject) { + // create a Memory Buffer with a fatbin offloading section + MemoryBufferRef mbuf; SmallVector(); SmallString<0> Storage; // Expected> ObjOrErr = toBinary(Storage, R"( diff --git a/llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp b/llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp index fb6f636e65b70..b86a243bfc383 100644 --- a/llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp +++ b/llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp @@ -10,6 +10,7 @@ #include "llvm/Config/config.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/FileSystem.h" +#include "llvm/Support/ManagedStatic.h" #include "llvm/Support/Path.h" #include "gtest/gtest.h" @@ -62,6 +63,7 @@ std::string StdString(const char *Ptr) { return Ptr ? Ptr : ""; } TEST(DynamicLibrary, Overload) { { std::string Err; + llvm_shutdown_obj Shutdown; DynamicLibrary DL = DynamicLibrary::getPermanentLibrary(LibPath().c_str(), &Err); EXPECT_TRUE(DL.isValid()); @@ -109,6 +111,68 @@ TEST(DynamicLibrary, Overload) { EXPECT_EQ(GS, &OverloadTestA); EXPECT_EQ(StdString(GS()), "OverloadCall"); } + EXPECT_TRUE(FuncPtr(DynamicLibrary::SearchForAddressOfSymbol( + "TestA")) == nullptr); + + // Check serach ordering is reset to default after call to llvm_shutdown + EXPECT_EQ(DynamicLibrary::SearchOrder, DynamicLibrary::SO_Linker); +} + +TEST(DynamicLibrary, Shutdown) { + std::string A("PipSqueak"), B, C("SecondLib"); + std::vector Order; + { + std::string Err; + llvm_shutdown_obj Shutdown; + DynamicLibrary DL = + DynamicLibrary::getPermanentLibrary(LibPath(A).c_str(), &Err); + EXPECT_TRUE(DL.isValid()); + EXPECT_TRUE(Err.empty()); + + SetStrings SS_0 = FuncPtr( + DynamicLibrary::SearchForAddressOfSymbol("SetStrings")); + EXPECT_NE(SS_0, nullptr); + + SS_0(A, B); + EXPECT_EQ(B, "Local::Local(PipSqueak)"); + + TestOrder TO_0 = FuncPtr( + DynamicLibrary::SearchForAddressOfSymbol("TestOrder")); + EXPECT_NE(TO_0, nullptr); + + DynamicLibrary DL2 = + DynamicLibrary::getPermanentLibrary(LibPath(C).c_str(), &Err); + EXPECT_TRUE(DL2.isValid()); + EXPECT_TRUE(Err.empty()); + + // Should find latest version of symbols in SecondLib + SetStrings SS_1 = FuncPtr( + DynamicLibrary::SearchForAddressOfSymbol("SetStrings")); + EXPECT_NE(SS_1, nullptr); + EXPECT_NE(SS_0, SS_1); + + TestOrder TO_1 = FuncPtr( + DynamicLibrary::SearchForAddressOfSymbol("TestOrder")); + EXPECT_NE(TO_1, nullptr); + EXPECT_NE(TO_0, TO_1); + + B.clear(); + SS_1(C, B); + EXPECT_EQ(B, "Local::Local(SecondLib)"); + + TO_0(Order); + TO_1(Order); + } + EXPECT_EQ(A, "Global::~Global"); + EXPECT_EQ(B, "Local::~Local"); + EXPECT_EQ(FuncPtr( + DynamicLibrary::SearchForAddressOfSymbol("SetStrings")), + nullptr); + + // Test unload/destruction ordering + EXPECT_EQ(Order.size(), 2UL); + EXPECT_EQ(Order.front(), "SecondLib"); + EXPECT_EQ(Order.back(), "PipSqueak"); } #else diff --git a/llvm/unittests/rocm-gdb-symbols/AsmParserTest.cpp b/llvm/unittests/rocm-gdb-symbols/AsmParserTest.cpp new file mode 100644 index 0000000000000..6a9e1b8a9c60c --- /dev/null +++ b/llvm/unittests/rocm-gdb-symbols/AsmParserTest.cpp @@ -0,0 +1,230 @@ +//===- llvm/unittest/rocm-dgb-symbols/AsmParserTest.cpp - AsmParser tests -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/AsmParser/Parser.h" +#include "llvm/IR/DIBuilder.h" +#include "llvm/IR/DebugInfo.h" +#include "llvm/IR/DebugInfoMetadata.h" +#include "llvm/IR/IntrinsicInst.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/Verifier.h" +#include "llvm/Support/SourceMgr.h" +#include "llvm/Transforms/Utils/Local.h" +#include "gtest/gtest.h" + +using namespace llvm; + +namespace { + +class DIExpressionAsmParserTest : public testing::Test { +protected: + LLVMContext Context; + Type *Int64Ty = Type::getInt64Ty(Context); + Type *Int32Ty = Type::getInt32Ty(Context); + Type *Int16Ty = Type::getInt16Ty(Context); + Type *Int8Ty = Type::getInt8Ty(Context); + Type *FloatTy = Type::getFloatTy(Context); + std::unique_ptr M; + const DIExpression *Expr; + + void parseNamedDIExpression(const char *IR) { + SMDiagnostic Err; + M = parseAssemblyString(IR, Err, Context); + if (!M) + GTEST_SKIP(); + bool BrokenDebugInfo = false; + bool HardError = verifyModule(*M, &errs(), &BrokenDebugInfo); + if (HardError || BrokenDebugInfo) + GTEST_SKIP(); + const NamedMDNode *N = M->getNamedMetadata("named"); + if (!N || N->getNumOperands() != 1u || + !isa(N->getOperand(0))) + GTEST_SKIP(); + Expr = cast(N->getOperand(0)); + } +}; + +TEST_F(DIExpressionAsmParserTest, Referrer) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpReferrer(i32))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Referrer(Int32Ty)})); +} + +TEST_F(DIExpressionAsmParserTest, Arg) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpArg(3, float))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Arg(3, FloatTy)})); +} + +TEST_F(DIExpressionAsmParserTest, TypeObject) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpTypeObject(i32))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::TypeObject(Int32Ty)})); +} + +TEST_F(DIExpressionAsmParserTest, Constant) { + parseNamedDIExpression( + R"(!named = !{!DIExpression(DIOpConstant(float 2.0))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + DIExprBuilder Builder{Context, *Expr->getNewElementsRef()}; + ASSERT_EQ(SmallVector(Builder.range()), + SmallVector( + {DIOp::Constant(ConstantFP::get(Context, APFloat(2.0f)))})); +} + +TEST_F(DIExpressionAsmParserTest, Reinterpret) { + parseNamedDIExpression( + R"(!named = !{!DIExpression(DIOpReinterpret(i32 addrspace(5)*))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector( + {DIOp::Reinterpret(PointerType::get(Context, 5))})); +} + +TEST_F(DIExpressionAsmParserTest, BitOffset) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpBitOffset(i32))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::BitOffset(Int32Ty)})); +} + +TEST_F(DIExpressionAsmParserTest, ByteOffset) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpByteOffset(i32))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::ByteOffset(Int32Ty)})); +} + +TEST_F(DIExpressionAsmParserTest, Composite) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpComposite(2, i8))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Composite(2, Int8Ty)})); +} + +TEST_F(DIExpressionAsmParserTest, Extend) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpExtend(2))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Extend(2)})); +} + +TEST_F(DIExpressionAsmParserTest, Select) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpSelect())})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Select()})); +} + +TEST_F(DIExpressionAsmParserTest, AddrOf) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpAddrOf(7))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::AddrOf(7)})); +} + +TEST_F(DIExpressionAsmParserTest, Deref) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpDeref(i32))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Deref(Int32Ty)})); +} + +TEST_F(DIExpressionAsmParserTest, Read) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpRead())})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Read()})); +} + +TEST_F(DIExpressionAsmParserTest, Add) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpAdd())})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Add()})); +} + +TEST_F(DIExpressionAsmParserTest, Sub) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpSub())})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Sub()})); +} + +TEST_F(DIExpressionAsmParserTest, Mul) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpMul())})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Mul()})); +} + +TEST_F(DIExpressionAsmParserTest, Div) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpDiv())})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Div()})); +} + +TEST_F(DIExpressionAsmParserTest, LShr) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpLShr())})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::LShr()})); +} + +TEST_F(DIExpressionAsmParserTest, AShr) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpAShr())})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::AShr()})); +} + +TEST_F(DIExpressionAsmParserTest, Shl) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpShl())})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Shl()})); +} + +TEST_F(DIExpressionAsmParserTest, PushLane) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpPushLane(i32))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::PushLane(Int32Ty)})); +} + +TEST_F(DIExpressionAsmParserTest, Fragment) { + parseNamedDIExpression(R"(!named = !{!DIExpression(DIOpFragment(0, 1))})"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector({DIOp::Fragment(0, 1)})); +} + +TEST_F(DIExpressionAsmParserTest, MultipleOps) { + parseNamedDIExpression(R"(!named = !{!DIExpression( + DIOpArg(0, i8), + DIOpArg(1, i8), + DIOpAdd(), + DIOpArg(2, i8), + DIOpComposite(2, i16), + DIOpReinterpret(i8 addrspace(1)*) + )} +)"); + ASSERT_TRUE(Expr->holdsNewElements()); + ASSERT_EQ(SmallVector(*Expr->getNewElementsRef()), + SmallVector( + {DIOp::Arg(0, Int8Ty), DIOp::Arg(1, Int8Ty), DIOp::Add(), + DIOp::Arg(2, Int8Ty), DIOp::Composite(2, Int16Ty), + DIOp::Reinterpret(PointerType::get(Int8Ty, 1))})); +} + +} // end namespace diff --git a/llvm/unittests/rocm-gdb-symbols/AsmWriterTest.cpp b/llvm/unittests/rocm-gdb-symbols/AsmWriterTest.cpp new file mode 100644 index 0000000000000..99dc9079654ab --- /dev/null +++ b/llvm/unittests/rocm-gdb-symbols/AsmWriterTest.cpp @@ -0,0 +1,163 @@ +//===- llvm/unittest/rocm-gdb-symbols/AsmWriter.cpp - AsmWriter tests -----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#include "llvm/BinaryFormat/Dwarf.h" +#include "llvm/IR/DebugInfoMetadata.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/IR/MDBuilder.h" +#include "llvm/IR/Module.h" +#include "gtest/gtest.h" + +using namespace llvm; + +namespace { + +class DIExpressionAsmWriterTest : public testing::Test { +public: + DIExpressionAsmWriterTest() : Builder(Context), OS(S) {} + +protected: + LLVMContext Context; + Type *Int32Ty = Type::getInt32Ty(Context); + Type *Int64Ty = Type::getInt64Ty(Context); + DIExprBuilder Builder; + std::string S; + raw_string_ostream OS; +}; + +TEST_F(DIExpressionAsmWriterTest, Empty) { + DIExpression *Expr = Builder.intoExpression(); + EXPECT_FALSE(Expr->isValid()); +} + +TEST_F(DIExpressionAsmWriterTest, Referrer) { + Builder.append(Int64Ty).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpReferrer(i64))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Arg) { + Builder.append(1, Int64Ty).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpArg(1, i64))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, TypeObject) { + Builder.append(Int64Ty).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpTypeObject(i64))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Constant) { + Builder + .append( + static_cast(ConstantInt::get(Int32Ty, 1))) + .intoExpression() + ->print(OS); + EXPECT_EQ("!DIExpression(DIOpConstant(i32 1))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Convert) { + Builder.append(Int64Ty).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpConvert(i64))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Reinterpret) { + Builder.append(Int64Ty).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpReinterpret(i64))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, BitOffset) { + Builder.append(Int64Ty).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpBitOffset(i64))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, ByteOffset) { + Builder.append(Int64Ty).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpByteOffset(i64))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Composite) { + Builder.append(2, Int64Ty).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpComposite(2, i64))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Extend) { + Builder.append(2).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpExtend(2))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Select) { + Builder.append().intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpSelect())", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, AddrOf) { + Builder.append(5).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpAddrOf(5))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Deref) { + Builder.append(Int64Ty).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpDeref(i64))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Read) { + Builder.append().intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpRead())", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Add) { + Builder.append().intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpAdd())", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Sub) { + Builder.append().intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpSub())", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Mul) { + Builder.append().intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpMul())", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Div) { + Builder.append().intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpDiv())", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, LShr) { + Builder.append().intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpLShr())", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, AShr) { + Builder.append().intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpAShr())", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, Shl) { + Builder.append().intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpShl())", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, PushLane) { + Builder.append(Int64Ty).intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpPushLane(i64))", OS.str()); +} + +TEST_F(DIExpressionAsmWriterTest, MultipleOps) { + Builder.insert(Builder.begin(), + {DIOp::Variant{std::in_place_type, Int32Ty}, + DIOp::Variant{std::in_place_type, Int64Ty}, + DIOp::Variant{std::in_place_type}}); + Builder.intoExpression()->print(OS); + EXPECT_EQ("!DIExpression(DIOpReferrer(i32), DIOpReferrer(i64), DIOpAdd())", + OS.str()); +} + +} // namespace diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp index 5d49715879280..17cd0930d0ec7 100644 --- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp +++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp @@ -1474,6 +1474,12 @@ Error OperandMatcher::addTypeCheckPredicate(const TypeSetByHwMode &VTy, return Error::success(); } + llvm::MVT::SimpleValueType STy = VTy.getMachineValueType().SimpleTy; + if (STy == MVT::Metadata) { + addPredicate(MachineOperand::MO_Metadata); + return Error::success(); + } + auto OpTyOrNone = MVTToLLT(VTy.getMachineValueType().SimpleTy); if (!OpTyOrNone) return failUnsupported("unsupported type"); @@ -1939,6 +1945,17 @@ bool InstructionOperandMatcher::isHigherPriorityThan( return false; } +//===- MachineOperandTypeMatcher -----------------------------------------===// + +void MachineOperandTypeMatcher::emitPredicateOpcodes(MatchTable &Table, + RuleMatcher &Rule) const { + Table << MatchTable::Opcode("GIM_CheckMachineOperandType") + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) + << MatchTable::Comment("Ty") << MatchTable::ULEB128Value(MOTy) + << MatchTable::LineBreak; +} + //===- OperandRenderer ----------------------------------------------------===// OperandRenderer::~OperandRenderer() {} diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h index 0f1241eb4d63f..87cd9617ca096 100644 --- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h +++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h @@ -23,6 +23,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGenTypes/LowLevelType.h" #include "llvm/Support/Error.h" #include "llvm/Support/SaveAndRestore.h" @@ -838,6 +839,7 @@ class PredicateMatcher { OPM_MBB, OPM_RecordNamedOperand, OPM_RecordRegType, + OPM_MOType, }; protected: @@ -1927,6 +1929,22 @@ class InstructionOperandMatcher : public OperandPredicateMatcher { } }; +class MachineOperandTypeMatcher : public OperandPredicateMatcher { + const MachineOperand::MachineOperandType MOTy; + +public: + MachineOperandTypeMatcher(unsigned InsnVarID, unsigned OpIdx, + MachineOperand::MachineOperandType MOTy) + : OperandPredicateMatcher(OPM_MOType, InsnVarID, OpIdx), MOTy(MOTy) {} + + static bool classof(const PredicateMatcher *P) { + return P->getKind() == OPM_MOType; + } + + void emitPredicateOpcodes(MatchTable &Table, + RuleMatcher &Rule) const override; +}; + //===- Actions ------------------------------------------------------------===// class OperandRenderer { public: diff --git a/llvm/utils/gen-heterogeneous-debug-test.sh b/llvm/utils/gen-heterogeneous-debug-test.sh new file mode 100755 index 0000000000000..cc812eb346533 --- /dev/null +++ b/llvm/utils/gen-heterogeneous-debug-test.sh @@ -0,0 +1,367 @@ +#!/bin/bash + +# Script to generate llvm/test/CodeGen/X86/heterogeneous-debug.test + +# shellcheck disable=SC2154 +set -u + +# This is independent of the test we are in, and is not reset in reset_per_test_state +idx=0 +inc_idx() { ((idx+=1)); } + +# Every other counter/accumulator is per-test and gets reset and the start of a new one +reset_per_test_state() { + declare -g ir_funcs='' ir_metadata='' mir_funcs='' di_version='' mdid=0 + declare_mdid unit + declare_mdid file + declare_mdid dwarf_version + declare_mdid info_version +} + +declare_mdid() { + ((mdid+=1)) + declare -g "$1=$mdid" +} +cat_generic() { declare -g "$1=${!1}$(cat)"$'\n'; } +cat_ir_funcs() { cat_generic ir_funcs; } +cat_ir_metadata() { cat_generic ir_metadata; } +cat_mir_funcs() { cat_generic mir_funcs; } + +print_ir_module() { +cat <", directory: ".") +!$dwarf_version = !{i32 7, !"Dwarf Version", i32 5} +!$info_version = !{i32 2, !"Debug Info Version", i32 $di_version} +$ir_metadata +EOF +} + +# Some read-only helper variables +bit_size_to_byte_size() { printf '%d\n' "$((($1 + 8 - 1) / 8))"; } +readonly scalar_tys=(i1 i4 i8 i16 i17 i32 i64 i128 half bfloat float double fp128) +readonly scalar_ty_bit_sizes=(1 4 8 16 17 32 64 128 16 16 32 64 128) +readonly scalar_ty_byte_sizes=($(for sz in ${scalar_ty_bit_sizes[@]}; do + bit_size_to_byte_size $sz +done)) +readonly scalar_ty_pow2_byte_sizes=($(for sz in ${scalar_ty_bit_sizes[@]}; do + next_pow2=1 + while [[ $sz -gt $next_pow2 ]]; do + next_pow2=$(($next_pow2 * 2)) + done + bit_size_to_byte_size $next_pow2 +done)) +readonly scalar_ty_bit_masks=($(for sz in ${scalar_ty_bit_sizes[@]}; do + if (($sz % 8)); then + printf '%d\n' "$(((1 << $sz) - 1))" + else + printf '0\n' + fi +done)) + +# Test generation functions + +declare_one_var_metadata() { +declare_mdid sub +declare_mdid sub_type +declare_mdid sub_type_types +declare_mdid ret +declare_mdid var +declare_mdid var_type +declare_mdid loc +# FIXME: is the size field never considered? it seems to be irrelevant what it +# is set to as far as the expression is concerned +cat_ir_metadata < llvm/test/CodeGen/X86/heterogeneous-debug.test + +# RUN: split-file %s %t + +EOF + +# BEGIN ir tests + +reset_per_test_state +di_version=3 + +for i in "${!scalar_tys[@]}"; do +add_checks_ir "DW_AT_location (DW_OP_fbreg -${scalar_ty_pow2_byte_sizes[$i]})" +gencase_ir_one_alloca "${scalar_tys[$i]}" '' + +add_checks_ir "DW_AT_location (DW_OP_fbreg -${scalar_ty_pow2_byte_sizes[$i]}, DW_OP_deref)" +gencase_ir_one_alloca "${scalar_tys[$i]}" 'DW_OP_deref' +done + +cat < $BuildDir/$Package.tar.gz + tar cf - $Package | gzip -9c -n > $BuildDir/$Package.tar.gz else tar cf - $Package | xz -9ce -T $NumJobs > $BuildDir/$Package.tar.xz fi @@ -613,7 +613,7 @@ function package_release() { cd $BuildDir/Phase3/Release mv llvmCore-$Release-$RC.install/usr/local $Package if [ "$use_gzip" = "yes" ]; then - tar cf - $Package | gzip -9c > $BuildDir/$Package.tar.gz + tar cf - $Package | gzip -9c -n > $BuildDir/$Package.tar.gz else tar cf - $Package | xz -9ce -T $NumJobs > $BuildDir/$Package.tar.xz fi diff --git a/mlir/include/mlir/Conversion/Passes.td b/mlir/include/mlir/Conversion/Passes.td index 70e3e45c225db..e0cac8b699c30 100644 --- a/mlir/include/mlir/Conversion/Passes.td +++ b/mlir/include/mlir/Conversion/Passes.td @@ -771,7 +771,7 @@ def ConvertMathToLLVMPass : Pass<"convert-math-to-llvm"> { } //===----------------------------------------------------------------------===// -// MathToLibm +// MathToROCDL //===----------------------------------------------------------------------===// def ConvertMathToROCDL : Pass<"convert-math-to-rocdl", "ModuleOp"> { diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPEnums.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPEnums.td index d9882cbcb5977..ada3a3edd8a30 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPEnums.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPEnums.td @@ -40,13 +40,15 @@ class OpenMP_EnumAttr // capture_clause enum. //===----------------------------------------------------------------------===// -def CaptureClauseTo : I32EnumAttrCase<"to", 0>; -def CaptureClauseLink : I32EnumAttrCase<"link", 1>; -def CaptureClauseEnter : I32EnumAttrCase<"enter", 2>; +def CaptureClauseNone : I32EnumAttrCase<"none", 0>; +def CaptureClauseTo : I32EnumAttrCase<"to", 1>; +def CaptureClauseLink : I32EnumAttrCase<"link", 2>; +def CaptureClauseEnter : I32EnumAttrCase<"enter", 3>; def DeclareTargetCaptureClause : OpenMP_I32EnumAttr< "DeclareTargetCaptureClause", "capture clause", [ + CaptureClauseNone, CaptureClauseTo, CaptureClauseLink, CaptureClauseEnter @@ -126,6 +128,7 @@ def ClauseMapFlagsAttachAuto : I32BitEnumAttrCaseBit<"attach_auto", 15>; def ClauseMapFlagsRefPtr : I32BitEnumAttrCaseBit<"ref_ptr", 16>; def ClauseMapFlagsRefPtee : I32BitEnumAttrCaseBit<"ref_ptee", 17>; def ClauseMapFlagsRefPtrPtee : I32BitEnumAttrCaseBit<"ref_ptr_ptee", 18>; +def ClauseMapFlagsDescriptor : I32BitEnumAttrCaseBit<"descriptor", 19>; def ClauseMapFlags : OpenMP_BitEnumAttr< "ClauseMapFlags", @@ -149,7 +152,8 @@ def ClauseMapFlags : OpenMP_BitEnumAttr< ClauseMapFlagsAttachAuto, ClauseMapFlagsRefPtr, ClauseMapFlagsRefPtee, - ClauseMapFlagsRefPtrPtee + ClauseMapFlagsRefPtrPtee, + ClauseMapFlagsDescriptor ]>; def ClauseMapFlagsAttr : OpenMP_EnumAttr forwardRefPlaceholders; - /// Operations that define the placeholders. These are kept until the end of - /// of the lifetime of the parser because some custom parsers may store - /// references to them in local state and use them after forward references - /// have been resolved. - DenseSet forwardRefOps; - /// Deffered locations: when parsing `loc(#loc42)` we add an entry to this /// map. After parsing the definition `#loc42 = ...` we'll patch back users /// of this location. @@ -855,11 +849,11 @@ OperationParser::OperationParser(ParserState &state, ModuleOp topLevelOp) } OperationParser::~OperationParser() { - for (Operation *op : forwardRefOps) { + for (auto &fwd : forwardRefPlaceholders) { // Drop all uses of undefined forward declared reference and destroy // defining operation. - op->dropAllUses(); - op->destroy(); + fwd.first.dropAllUses(); + fwd.first.getDefiningOp()->destroy(); } for (const auto &scope : forwardRef) { for (const auto &fwd : scope) { @@ -1015,6 +1009,7 @@ ParseResult OperationParser::addDefinition(UnresolvedOperand useInfo, // the actual definition instead, delete the forward ref, and remove it // from our set of forward references we track. existing.replaceAllUsesWith(value); + existing.getDefiningOp()->destroy(); forwardRefPlaceholders.erase(existing); // If a definition of the value already exists, replace it in the assembly @@ -1201,7 +1196,6 @@ Value OperationParser::createForwardRefPlaceholder(SMLoc loc, Type type) { /*attributes=*/NamedAttrList(), /*properties=*/nullptr, /*successors=*/{}, /*numRegions=*/0); forwardRefPlaceholders[op->getResult(0)] = loc; - forwardRefOps.insert(op); return op->getResult(0); } diff --git a/mlir/lib/Conversion/PDLToPDLInterp/PredicateTree.cpp b/mlir/lib/Conversion/PDLToPDLInterp/PredicateTree.cpp index 39d4815dc73b7..ac9dfc14d91bb 100644 --- a/mlir/lib/Conversion/PDLToPDLInterp/PredicateTree.cpp +++ b/mlir/lib/Conversion/PDLToPDLInterp/PredicateTree.cpp @@ -50,7 +50,7 @@ static void getTreePredicates(std::vector &predList, assert(isa(val.getType()) && "expected attribute type"); predList.emplace_back(pos, builder.getIsNotNull()); - if (auto attr = val.getDefiningOp()) { + if (auto attr = dyn_cast(val.getDefiningOp())) { // If the attribute has a type or value, add a constraint. if (Value type = attr.getValueType()) getTreePredicates(predList, type, builder, inputs, builder.getType(pos)); diff --git a/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp b/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp index e08cc6f645d71..68126fa0e80af 100644 --- a/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp +++ b/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp @@ -1321,7 +1321,7 @@ static bool isNeutralElementConst(arith::AtomicRMWKind reductionKind, return false; Attribute valueAttr = getIdentityValueAttr(reductionKind, scalarTy, state.builder, value.getLoc()); - if (auto constOp = value.getDefiningOp()) + if (auto constOp = dyn_cast_or_null(value.getDefiningOp())) return constOp.getValue() == valueAttr; return false; } diff --git a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp index 898d76ce8d9b5..1cc65c3ed7fb0 100644 --- a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp +++ b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp @@ -2505,7 +2505,7 @@ OpFoldResult arith::SelectOp::fold(FoldAdaptor adaptor) { matchPattern(adaptor.getFalseValue(), m_Zero())) return condition; - if (auto cmp = condition.getDefiningOp()) { + if (auto cmp = dyn_cast_or_null(condition.getDefiningOp())) { auto pred = cmp.getPredicate(); if (pred == arith::CmpIPredicate::eq || pred == arith::CmpIPredicate::ne) { auto cmpLhs = cmp.getLhs(); diff --git a/mlir/lib/Dialect/ArmNeon/Transforms/LowerContractToNeonPatterns.cpp b/mlir/lib/Dialect/ArmNeon/Transforms/LowerContractToNeonPatterns.cpp index 35365f2dc17ba..72c20f4aaef33 100644 --- a/mlir/lib/Dialect/ArmNeon/Transforms/LowerContractToNeonPatterns.cpp +++ b/mlir/lib/Dialect/ArmNeon/Transforms/LowerContractToNeonPatterns.cpp @@ -49,7 +49,7 @@ std::optional getExtOperand(Value v) { // If the operand is not defined by an explicit extend operation of the // accepted operation type allow for an implicit sign-extension. - auto extOp = v.getDefiningOp(); + auto extOp = dyn_cast_or_null(v.getDefiningOp()); if (!extOp) { if constexpr (std::is_same::value) { auto eltTy = cast(v.getType()).getElementType(); diff --git a/mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp b/mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp index 6cb2a56aebdd1..acf0f07bba19a 100644 --- a/mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp +++ b/mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp @@ -50,7 +50,7 @@ std::optional getExtOperand(Value v) { // If the operand is not defined by an explicit extend operation of the // accepted operation type allow for an implicit sign-extension. - auto extOp = v.getDefiningOp(); + auto extOp = dyn_cast_or_null(v.getDefiningOp()); if (!extOp) { if constexpr (std::is_same::value) { auto vTy = cast(v.getType()); diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp index 3eae67f4c1f98..af790fb2716c5 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp @@ -2741,7 +2741,7 @@ LogicalResult IFuncOp::verifySymbolUses(SymbolTableCollection &symbolTable) { while (alias) { Block &initBlock = alias.getInitializerBlock(); auto returnOp = cast(initBlock.getTerminator()); - auto addrOp = returnOp.getArg().getDefiningOp(); + auto addrOp = dyn_cast(returnOp.getArg().getDefiningOp()); // FIXME: This is a best effort solution. The AliasOp body might be more // complex and in that case we bail out with success. To completely match // the LLVM IR logic it would be necessary to implement proper alias and diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp index cbc565b0c8cbd..b664c2bc46010 100644 --- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp +++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp @@ -3782,6 +3782,7 @@ getAffineResultPositions(ArrayAttr maps) { /// Returns a list of AffineMap with the typical matmul indexing charactristic. SmallVector MatmulOp::getDefaultIndexingMaps(MLIRContext *context) { AffineExpr d0, d1, d2; +// SmallVector indexingMaps; SmallVector indexingMaps; bindDims(context, d0, d1, d2); indexingMaps.push_back(AffineMap::get(3, 0, {d0, d2}, context)); diff --git a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp index 794dda96d1dfa..0641228da60b4 100644 --- a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp +++ b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp @@ -2034,7 +2034,7 @@ transform::PackTransposeOp::apply(transform::TransformRewriter &rewriter, assert(!packOp && "packOp must be null on entry when unPackOp is not null"); OpOperand *packUse = linalgOp.getDpsInitOperand( cast(unPackOp.getSource()).getResultNumber()); - packOp = packUse->get().getDefiningOp(); + packOp = dyn_cast_or_null(packUse->get().getDefiningOp()); if (!packOp || !packOp.getResult().hasOneUse()) return emitSilenceableError() << "could not find matching pack op"; } diff --git a/mlir/lib/Dialect/Linalg/Transforms/HoistPadding.cpp b/mlir/lib/Dialect/Linalg/Transforms/HoistPadding.cpp index 9436f1c6cd9b0..e2e7a2a737ceb 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/HoistPadding.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/HoistPadding.cpp @@ -758,7 +758,8 @@ static bool tracesBackToExpectedValue(tensor::ExtractSliceOp extractSliceOp, Value source = extractSliceOp.getSource(); LLVM_DEBUG(DBGS() << "--with starting source: " << source << "\n"); while (source && source != expectedSource) { - auto destOp = source.getDefiningOp(); + auto destOp = + dyn_cast_or_null(source.getDefiningOp()); if (!destOp) break; LLVM_DEBUG(DBGS() << "--step dest op: " << destOp << "\n"); diff --git a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp index 1b069c62a8be9..172f21ff1779e 100644 --- a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp +++ b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp @@ -1745,8 +1745,9 @@ static bool mapTypeToBool(ClauseMapFlags value, ClauseMapFlags flag) { /// Parses a map_entries map type from a string format back into its numeric /// value. /// -/// map-clause = `map_clauses ( ( `(` `always, `? `implicit, `? `ompx_hold, `? -/// `close, `? `present, `? ( `to` | `from` | `delete` `)` )+ `)` ) +/// map-clause = `map_clauses ( ( `(` `attach, `? `always, `? `implicit, `? +/// `ompx_hold, `? `close, `? `present, `? ( `to` | `from` | `delete` `)` )+ `)` +/// ) static ParseResult parseMapClause(OpAsmParser &parser, ClauseMapFlagsAttr &mapType) { ClauseMapFlags mapTypeBits = ClauseMapFlags::none; @@ -1772,6 +1773,9 @@ static ParseResult parseMapClause(OpAsmParser &parser, if (mapTypeMod == "present") mapTypeBits |= ClauseMapFlags::present; + if (mapTypeMod == "descriptor") + mapTypeBits |= ClauseMapFlags::descriptor; + if (mapTypeMod == "to") mapTypeBits |= ClauseMapFlags::to; @@ -1848,6 +1852,8 @@ static void printMapClause(OpAsmPrinter &p, Operation *op, mapTypeStrs.push_back("close"); if (mapTypeToBool(mapFlags, ClauseMapFlags::present)) mapTypeStrs.push_back("present"); + if (mapTypeToBool(mapFlags, ClauseMapFlags::descriptor)) + mapTypeStrs.push_back("descriptor"); // special handling of to/from/tofrom/delete and release/alloc, release + // alloc are the abscense of one of the other flags, whereas tofrom requires @@ -2274,7 +2280,7 @@ LogicalResult TargetOp::verifyRegions() { } static Operation * -findCapturedOmpOp(Operation *rootOp, bool checkSingleMandatoryExec, +findCapturedOmpOp(Operation *rootOp, llvm::function_ref siblingAllowedFn) { assert(rootOp && "expected valid operation"); @@ -2302,19 +2308,17 @@ findCapturedOmpOp(Operation *rootOp, bool checkSingleMandatoryExec, // (i.e. its block's successors can reach it) or if it's not guaranteed to // be executed before all exits of the region (i.e. it doesn't dominate all // blocks with no successors reachable from the entry block). - if (checkSingleMandatoryExec) { - Region *parentRegion = op->getParentRegion(); - Block *parentBlock = op->getBlock(); - - for (Block *successor : parentBlock->getSuccessors()) - if (successor->isReachable(parentBlock)) - return WalkResult::interrupt(); - - for (Block &block : *parentRegion) - if (domInfo.isReachableFromEntry(&block) && block.hasNoSuccessors() && - !domInfo.dominates(parentBlock, &block)) - return WalkResult::interrupt(); - } + Region *parentRegion = op->getParentRegion(); + Block *parentBlock = op->getBlock(); + + for (Block *successor : parentBlock->getSuccessors()) + if (successor->isReachable(parentBlock)) + return WalkResult::interrupt(); + + for (Block &block : *parentRegion) + if (domInfo.isReachableFromEntry(&block) && block.hasNoSuccessors() && + !domInfo.dominates(parentBlock, &block)) + return WalkResult::interrupt(); // Don't capture this op if it has a not-allowed sibling, and stop recursing // into nested operations. @@ -2337,27 +2341,25 @@ Operation *TargetOp::getInnermostCapturedOmpOp() { // Only allow OpenMP terminators and non-OpenMP ops that have known memory // effects, but don't include a memory write effect. - return findCapturedOmpOp( - *this, /*checkSingleMandatoryExec=*/true, [&](Operation *sibling) { - if (!sibling) - return false; - - if (ompDialect == sibling->getDialect()) - return sibling->hasTrait(); - - if (auto memOp = dyn_cast(sibling)) { - SmallVector, 4> - effects; - memOp.getEffects(effects); - return !llvm::any_of( - effects, [&](MemoryEffects::EffectInstance &effect) { - return isa(effect.getEffect()) && - isa( - effect.getResource()); - }); - } - return true; + return findCapturedOmpOp(*this, [&](Operation *sibling) { + if (!sibling) + return false; + + if (ompDialect == sibling->getDialect()) + return sibling->hasTrait(); + + if (auto memOp = dyn_cast(sibling)) { + SmallVector, 4> + effects; + memOp.getEffects(effects); + return !llvm::any_of(effects, [&](MemoryEffects::EffectInstance &effect) { + return isa(effect.getEffect()) && + isa( + effect.getResource()); }); + } + return true; + }); } /// Check if we can promote SPMD kernel to No-Loop kernel. @@ -2449,33 +2451,23 @@ TargetRegionFlags TargetOp::getKernelExecFlags(Operation *capturedOp) { if (isa(innermostWrapper)) return TargetRegionFlags::spmd | TargetRegionFlags::trip_count; - // Find single immediately nested captured omp.parallel and add spmd flag - // (generic-spmd case). + // Add spmd flag if there's a nested omp.parallel (generic-spmd case). // // TODO: This shouldn't have to be done here, as it is too easy to break. // The openmp-opt pass should be updated to be able to promote kernels like // this from "Generic" to "Generic-SPMD". However, the use of the // `kmpc_distribute_static_loop` family of functions produced by the // OMPIRBuilder for these kernels prevents that from working. - Dialect *ompDialect = targetOp->getDialect(); - Operation *nestedCapture = findCapturedOmpOp( - capturedOp, /*checkSingleMandatoryExec=*/false, - [&](Operation *sibling) { - return sibling && (ompDialect != sibling->getDialect() || - sibling->hasTrait()); - }); + bool hasParallel = capturedOp + ->walk([](ParallelOp) { + return WalkResult::interrupt(); + }) + .wasInterrupted(); TargetRegionFlags result = TargetRegionFlags::generic | TargetRegionFlags::trip_count; - if (!nestedCapture) - return result; - - while (nestedCapture->getParentOp() != capturedOp) - nestedCapture = nestedCapture->getParentOp(); - - return isa(nestedCapture) ? result | TargetRegionFlags::spmd - : result; + return hasParallel ? result | TargetRegionFlags::spmd : result; } // Detect target-parallel-wsloop[-simd]. else if (isa(innermostWrapper)) { @@ -2634,9 +2626,9 @@ LogicalResult TeamsOp::verify() { // contain any statements, declarations or directives other than this // omp.teams construct. The issue is how to support the initialization of // this operation's own arguments (allow SSA values across omp.target?). - Operation *op = getOperation(); - if (!isa(op->getParentOp()) && - !opInGlobalImplicitParallelRegion(op)) + auto targetOp = dyn_cast_if_present((*this)->getParentOp()); + + if (!targetOp && !opInGlobalImplicitParallelRegion(*this)) return emitError("expected to be nested inside of omp.target or not nested " "in any OpenMP dialect operations"); diff --git a/mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp b/mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp index 51f25f755a8a6..415ee0388b7aa 100644 --- a/mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp +++ b/mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp @@ -77,7 +77,7 @@ OpFoldResult FromPtrOp::fold(FoldAdaptor adaptor) { Value ptrLike; FromPtrOp fromPtr = *this; while (fromPtr != nullptr) { - auto toPtr = fromPtr.getPtr().getDefiningOp(); + auto toPtr = dyn_cast_or_null(fromPtr.getPtr().getDefiningOp()); // Cannot fold if it's not a `to_ptr` op or the initial and final types are // different. if (!toPtr || toPtr.getPtr().getType() != fromPtr.getType()) @@ -88,12 +88,13 @@ OpFoldResult FromPtrOp::fold(FoldAdaptor adaptor) { ptrLike = toPtr.getPtr(); } else if (md) { // Fold if the metadata can be verified to be equal. - if (auto mdOp = md.getDefiningOp(); + if (auto mdOp = dyn_cast_or_null(md.getDefiningOp()); mdOp && mdOp.getPtr() == toPtr.getPtr()) ptrLike = toPtr.getPtr(); } // Check for a sequence of casts. - fromPtr = ptrLike ? ptrLike.getDefiningOp() : nullptr; + fromPtr = dyn_cast_or_null(ptrLike ? ptrLike.getDefiningOp() + : nullptr); } return ptrLike; } @@ -438,13 +439,13 @@ OpFoldResult ToPtrOp::fold(FoldAdaptor adaptor) { Value ptr; ToPtrOp toPtr = *this; while (toPtr != nullptr) { - auto fromPtr = toPtr.getPtr().getDefiningOp(); + auto fromPtr = dyn_cast_or_null(toPtr.getPtr().getDefiningOp()); // Cannot fold if it's not a `from_ptr` op. if (!fromPtr) return ptr; ptr = fromPtr.getPtr(); // Check for chains of casts. - toPtr = ptr.getDefiningOp(); + toPtr = dyn_cast_or_null(ptr.getDefiningOp()); } return ptr; } diff --git a/mlir/lib/Dialect/SCF/IR/SCF.cpp b/mlir/lib/Dialect/SCF/IR/SCF.cpp index 1ab01d86bcd10..a781d4074ebcc 100644 --- a/mlir/lib/Dialect/SCF/IR/SCF.cpp +++ b/mlir/lib/Dialect/SCF/IR/SCF.cpp @@ -640,27 +640,15 @@ ParseResult ForOp::parse(OpAsmParser &parser, OperationState &result) { else if (parser.parseType(type)) return failure(); - // Set block argument types, so that they are known when parsing the region. + // Resolve input operands. regionArgs.front().type = type; - for (auto [iterArg, type] : - llvm::zip_equal(llvm::drop_begin(regionArgs), result.types)) - iterArg.type = type; - - // Parse the body region. - Region *body = result.addRegion(); - if (parser.parseRegion(*body, regionArgs)) - return failure(); - ForOp::ensureTerminator(*body, builder, result.location); - - // Resolve input operands. This should be done after parsing the region to - // catch invalid IR where operands were defined inside of the region. if (parser.resolveOperand(lb, type, result.operands) || parser.resolveOperand(ub, type, result.operands) || parser.resolveOperand(step, type, result.operands)) return failure(); if (hasIterArgs) { - for (auto argOperandType : llvm::zip_equal(llvm::drop_begin(regionArgs), - operands, result.types)) { + for (auto argOperandType : + llvm::zip(llvm::drop_begin(regionArgs), operands, result.types)) { Type type = std::get<2>(argOperandType); std::get<0>(argOperandType).type = type; if (parser.resolveOperand(std::get<1>(argOperandType), type, @@ -669,6 +657,13 @@ ParseResult ForOp::parse(OpAsmParser &parser, OperationState &result) { } } + // Parse the body region. + Region *body = result.addRegion(); + if (parser.parseRegion(*body, regionArgs)) + return failure(); + + ForOp::ensureTerminator(*body, builder, result.location); + // Parse the optional attribute list. if (parser.parseOptionalAttrDict(result.attributes)) return failure(); diff --git a/mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp b/mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp index 081f5fb3dc8f2..84a779b90f6c2 100644 --- a/mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp +++ b/mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp @@ -100,10 +100,11 @@ mlir::scf::tileParallelLoop(ParallelOp op, ArrayRef tileSizes, op.getStep(), tileSizeConstants)) { // Collect the statically known loop bounds auto lowerBoundConstant = - lowerBound.getDefiningOp(); + dyn_cast_or_null(lowerBound.getDefiningOp()); auto upperBoundConstant = - upperBound.getDefiningOp(); - auto stepConstant = step.getDefiningOp(); + dyn_cast_or_null(upperBound.getDefiningOp()); + auto stepConstant = + dyn_cast_or_null(step.getDefiningOp()); auto tileSize = cast(tileSizeConstant.getDefiningOp()).value(); // If the loop bounds and the loop step are constant and if the number of diff --git a/mlir/lib/Dialect/Shard/Transforms/Partition.cpp b/mlir/lib/Dialect/Shard/Transforms/Partition.cpp index 335ca1a60f8f3..3095f4d648c18 100644 --- a/mlir/lib/Dialect/Shard/Transforms/Partition.cpp +++ b/mlir/lib/Dialect/Shard/Transforms/Partition.cpp @@ -647,7 +647,8 @@ partitionOperation(ShardOp shardOp, IRMapping &partitionMap, // Check if 2 shard ops are chained. If not there is no need for resharding // as the source and target shared the same sharding. - ShardOp srcShardOp = shardOp.getSrc().getDefiningOp(); + ShardOp srcShardOp = + dyn_cast_or_null(shardOp.getSrc().getDefiningOp()); if (!srcShardOp) { targetPartitionValue = partitionMap.lookup(shardOp.getSrc()); } else { diff --git a/mlir/lib/Dialect/Shard/Transforms/ShardingPropagation.cpp b/mlir/lib/Dialect/Shard/Transforms/ShardingPropagation.cpp index 3bfbf373209e3..d927fb116a711 100644 --- a/mlir/lib/Dialect/Shard/Transforms/ShardingPropagation.cpp +++ b/mlir/lib/Dialect/Shard/Transforms/ShardingPropagation.cpp @@ -167,7 +167,7 @@ ReshardingRquirementKind getReshardingRquirementKind( for (auto [operand, sharding] : llvm::zip_equal(op->getOperands(), operandShardings)) { - ShardOp shardOp = operand.getDefiningOp(); + ShardOp shardOp = llvm::dyn_cast_or_null(operand.getDefiningOp()); if (!shardOp) { continue; } @@ -374,7 +374,8 @@ struct ShardingPropagation LLVM_DEBUG( DBGS() << "print all the ops' iterator types and indexing maps in the " "block.\n"; - for (Operation &op : block.getOperations()) { + for (Operation &op + : block.getOperations()) { if (auto shardingOp = llvm::dyn_cast(&op)) shardingOp.printLoopTypesAndIndexingMaps(llvm::dbgs()); }); diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseBufferRewriting.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseBufferRewriting.cpp index ae7eef2145925..b1c3099994c72 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseBufferRewriting.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseBufferRewriting.cpp @@ -1316,7 +1316,7 @@ struct PushBackRewriter : OpRewritePattern { Value n = op.getN() ? op.getN() : constantIndex(rewriter, loc, 1); Value newSize = arith::AddIOp::create(rewriter, loc, size, n); - auto nValue = n.getDefiningOp(); + auto nValue = dyn_cast_or_null(n.getDefiningOp()); bool nIsOne = (nValue && nValue.value() == 1); if (!op.getInbounds()) { diff --git a/mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp b/mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp index 293c6af6202f4..889f4a282c455 100644 --- a/mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp +++ b/mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp @@ -520,7 +520,7 @@ struct ClampClampOptimization : public OpRewritePattern { Value input = op.getInput(); // Check the input to the CLAMP op is itself a CLAMP. - auto clampOp = input.getDefiningOp(); + auto clampOp = dyn_cast_if_present(input.getDefiningOp()); if (!clampOp) return failure(); @@ -1594,7 +1594,7 @@ OpFoldResult ConcatOp::fold(FoldAdaptor adaptor) { for (Value operand : getOperands()) { concatOperands.emplace_back(operand); - auto producer = operand.getDefiningOp(); + auto producer = dyn_cast_or_null(operand.getDefiningOp()); if (!producer) continue; diff --git a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp index ad8255a95cb4e..3459564e72318 100644 --- a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp +++ b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp @@ -2684,7 +2684,8 @@ class FromElementsToShapeCast : public OpRewritePattern { llvm::enumerate(fromElements.getElements())) { // Check that the element is from a vector.extract operation. - auto extractOp = element.getDefiningOp(); + auto extractOp = + dyn_cast_if_present(element.getDefiningOp()); if (!extractOp) { return rewriter.notifyMatchFailure(fromElements, "element not from vector.extract"); diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp index 726da1e9a3d14..e487e4162932f 100644 --- a/mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp @@ -2333,6 +2333,11 @@ void mlir::vector::populateVectorMaskMaterializationPatterns( void mlir::vector::populateDropUnitDimWithShapeCastPatterns( RewritePatternSet &patterns, PatternBenefit benefit) { + // TODO: Consider either: + // * including DropInnerMostUnitDimsTransferRead and + // DropInnerMostUnitDimsTransferWrite, or + // * better naming to distinguish this and + // populateVectorTransferCollapseInnerMostContiguousDimsPatterns. patterns.add(patterns.getContext(), benefit); } @@ -2369,7 +2374,15 @@ void mlir::vector::populateVectorReductionToContractPatterns( void mlir::vector::populateDropInnerMostUnitDimsXferOpPatterns( RewritePatternSet &patterns, PatternBenefit benefit) { - patterns.add(patterns.getContext(), + benefit); +} + +void mlir::vector:: + populateVectorTransferCollapseInnerMostContiguousDimsPatterns( + RewritePatternSet &patterns, PatternBenefit benefit) { + patterns.add(patterns.getContext(), benefit); } diff --git a/mlir/lib/IR/MLIRContext.cpp b/mlir/lib/IR/MLIRContext.cpp index 73219c6917061..8dc910552cd90 100644 --- a/mlir/lib/IR/MLIRContext.cpp +++ b/mlir/lib/IR/MLIRContext.cpp @@ -57,7 +57,8 @@ struct MLIRContextOptions { llvm::cl::opt disableThreading{ "mlir-disable-threading", llvm::cl::desc("Disable multi-threading within MLIR, overrides any " - "further call to MLIRContext::enableMultiThreading()")}; + "further call to MLIRContext::enableMultiThreading()"), + llvm::cl::init(true)}; llvm::cl::opt printOpOnDiagnostic{ "mlir-print-op-on-diagnostic", @@ -75,7 +76,7 @@ struct MLIRContextOptions { static llvm::ManagedStatic clOptions; static bool isThreadingGloballyDisabled() { -#if LLVM_ENABLE_THREADS != 0 +#if MLIR_ENABLE_THREADS != 0 return clOptions.isConstructed() && clOptions->disableThreading; #else return true; diff --git a/mlir/lib/Target/Cpp/TranslateToCpp.cpp b/mlir/lib/Target/Cpp/TranslateToCpp.cpp index 12435119b98a1..00c66773402c1 100644 --- a/mlir/lib/Target/Cpp/TranslateToCpp.cpp +++ b/mlir/lib/Target/Cpp/TranslateToCpp.cpp @@ -955,7 +955,8 @@ static LogicalResult printOperation(CppEmitter &emitter, emitc::ForOp forOp) { // inlined, and as such should be wrapped in parentheses in order to guarantee // its precedence and associativity. auto requiresParentheses = [&](Value value) { - auto expressionOp = value.getDefiningOp(); + auto expressionOp = + dyn_cast_if_present(value.getDefiningOp()); if (!expressionOp) return false; return shouldBeInlined(expressionOp); @@ -1588,7 +1589,7 @@ LogicalResult CppEmitter::emitOperand(Value value) { return success(); } - auto expressionOp = value.getDefiningOp(); + auto expressionOp = dyn_cast_if_present(value.getDefiningOp()); if (expressionOp && shouldBeInlined(expressionOp)) return emitExpression(expressionOp); diff --git a/mlir/lib/Target/LLVMIR/DebugTranslation.cpp b/mlir/lib/Target/LLVMIR/DebugTranslation.cpp index eeb87253e5eb8..060f76f135b61 100644 --- a/mlir/lib/Target/LLVMIR/DebugTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/DebugTranslation.cpp @@ -202,7 +202,7 @@ llvm::DIDerivedType *DebugTranslation::translateImpl(DIDerivedTypeAttr attr) { /*File=*/nullptr, /*Line=*/0, /*Scope=*/nullptr, translate(attr.getBaseType()), attr.getSizeInBits(), attr.getAlignInBits(), attr.getOffsetInBits(), - attr.getDwarfAddressSpace(), /*PtrAuthData=*/std::nullopt, + attr.getDwarfAddressSpace(), llvm::dwarf::DW_MSPACE_LLVM_none, /*PtrAuthData=*/std::nullopt, /*Flags=*/llvm::DINode::FlagZero, translate(attr.getExtraData())); } @@ -255,6 +255,7 @@ DebugTranslation::translateImpl(DILocalVariableAttr attr) { llvmCtx, translate(attr.getScope()), getMDStringOrNull(attr.getName()), translate(attr.getFile()), attr.getLine(), translate(attr.getType()), attr.getArg(), static_cast(attr.getFlags()), + llvm::dwarf::DW_MSPACE_LLVM_none, attr.getAlignInBits(), /*Annotations=*/nullptr); } @@ -265,7 +266,8 @@ DebugTranslation::translateImpl(DIGlobalVariableAttr attr) { llvmCtx, translate(attr.getScope()), getMDStringOrNull(attr.getName()), getMDStringOrNull(attr.getLinkageName()), translate(attr.getFile()), attr.getLine(), translate(attr.getType()), attr.getIsLocalToUnit(), - attr.getIsDefined(), nullptr, nullptr, attr.getAlignInBits(), nullptr); + attr.getIsDefined(), nullptr, nullptr, llvm::dwarf::DW_MSPACE_LLVM_none, + attr.getAlignInBits(), nullptr); } llvm::DINode * diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp index 97c6b4e25542d..87e77945b7ef2 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp @@ -31,7 +31,7 @@ using OpenACCIRBuilder = llvm::OpenMPIRBuilder; // Utility functions //===----------------------------------------------------------------------===// -/// Flag values are extracted from openmp/libomptarget/include/omptarget.h and +/// Flag values are extracted from offload/include/omptarget.h and /// mapped to corresponding OpenACC flags. static constexpr uint64_t kCreateFlag = 0x000; static constexpr uint64_t kDeviceCopyinFlag = 0x001; @@ -151,7 +151,8 @@ processDataOperands(llvm::IRBuilderBase &builder, // Copyin operands are handled as `to` call. llvm::SmallVector create, copyin; for (mlir::Value dataOp : op.getDataClauseOperands()) { - if (auto createOp = dataOp.getDefiningOp()) { + if (auto createOp = + mlir::dyn_cast_or_null(dataOp.getDefiningOp())) { create.push_back(createOp.getVarPtr()); } else if (auto copyinOp = mlir::dyn_cast_or_null( dataOp.getDefiningOp())) { diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp index f28454075f1d3..8344332c9063f 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp @@ -25,16 +25,20 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/TypeSwitch.h" #include "llvm/Frontend/OpenMP/OMPConstants.h" +#include "llvm/Frontend/OpenMP/OMPDeviceConstants.h" #include "llvm/Frontend/OpenMP/OMPIRBuilder.h" #include "llvm/IR/Constants.h" +#include "llvm/IR/DebugInfo.h" #include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/IRBuilder.h" +#include "llvm/IR/InstIterator.h" #include "llvm/IR/MDBuilder.h" #include "llvm/IR/ReplaceConstant.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/VirtualFileSystem.h" #include "llvm/TargetParser/Triple.h" +#include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/ModuleUtils.h" #include @@ -423,7 +427,6 @@ static LogicalResult checkImplementationStatus(Operation &op) { }) .Case([&](omp::WsloopOp op) { checkAllocate(op, result); - checkLinear(op, result); checkOrder(op, result); checkReduction(op, result); }) @@ -432,8 +435,14 @@ static LogicalResult checkImplementationStatus(Operation &op) { checkReduction(op, result); }) .Case([&](omp::SimdOp op) { - checkLinear(op, result); - checkReduction(op, result); + // Allow ignoring unimplemented SIMD clauses rather than emitting errors + // and stopping the compilation process. + if (!op.getLinearVars().empty() || !op.getLinearStepVars().empty()) + op.emitWarning() << "ignored clause: linear in omp.simd operation"; + + if (!op.getNontemporalVars().empty()) + op.emitWarning() + << "ignored clause: nontemporal in omp.simd operation"; }) .Case([&](auto op) { checkHint(op, result); }) @@ -1152,7 +1161,6 @@ allocReductionVars(T loop, ArrayRef reductionArgs, "allocaction is implicit for by-val reduction"); llvm::Value *var = builder.CreateAlloca( moduleTranslation.convertType(reductionDecls[i].getType())); - llvm::Type *ptrTy = builder.getPtrTy(); llvm::Value *castVar = builder.CreatePointerBitCastOrAddrSpaceCast(var, ptrTy); @@ -1257,11 +1265,6 @@ initReductionVars(OP op, ArrayRef reductionArgs, mapInitializationArgs(op, moduleTranslation, reductionDecls, reductionVariableMap, i); - // TODO In some cases (specially on the GPU), the init regions may - // contains stack alloctaions. If the region is inlined in a loop, this is - // problematic. Instead of just inlining the region, handle allocations by - // hoisting fixed length allocations to the function entry and using - // stacksave and restore for variable length ones. if (failed(inlineConvertOmpRegions(reductionDecls[i].getInitializerRegion(), "omp.reduction.neutral", builder, moduleTranslation, &phis))) @@ -1435,7 +1438,6 @@ static LogicalResult createReductionsAndCleanup( return inlineOmpRegionCleanup(reductionRegions, privateReductionVariables, moduleTranslation, builder, "omp.reduction.cleanup"); - return success(); } static ArrayRef getIsByRef(std::optional> attr) { @@ -2553,7 +2555,7 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, // Initialize linear variables and linear step LinearClauseProcessor linearClauseProcessor; - if (!wsloopOp.getLinearVars().empty()) { + if (wsloopOp.getLinearVars().size()) { for (mlir::Value linearVar : wsloopOp.getLinearVars()) linearClauseProcessor.createLinearVar(builder, moduleTranslation, linearVar); @@ -2568,9 +2570,9 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, return failure(); llvm::CanonicalLoopInfo *loopInfo = findCurrentLoopInfo(moduleTranslation); - + // Emit Initialization and Update IR for linear variables - if (!wsloopOp.getLinearVars().empty()) { + if (wsloopOp.getLinearVars().size()) { llvm::OpenMPIRBuilder::InsertPointOrErrorTy afterBarrierIP = linearClauseProcessor.initLinearVar(builder, moduleTranslation, loopInfo->getPreheader()); @@ -2617,7 +2619,7 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, return failure(); // Emit finalization and in-place rewrites for linear vars. - if (!wsloopOp.getLinearVars().empty()) { + if (wsloopOp.getLinearVars().size()) { llvm::OpenMPIRBuilder::InsertPointTy oldIP = builder.saveIP(); assert(loopInfo->getLastIter() && "`lastiter` in CanonicalLoopInfo is nullptr"); @@ -2874,8 +2876,7 @@ convertOmpSimd(Operation &opInst, llvm::IRBuilderBase &builder, .failed()) return failure(); - // No call to copyFirstPrivateVars because FIRSTPRIVATE is not allowed for - // SIMD. + // TODO: no call to copyFirstPrivateVars? assert(afterAllocas.get()->getSinglePredecessor()); if (failed(initReductionVars(simdOp, reductionArgs, builder, @@ -3589,19 +3590,14 @@ convertOmpThreadprivate(Operation &opInst, llvm::IRBuilderBase &builder, LLVM::GlobalOp global = addressOfOp.getGlobal(moduleTranslation.symbolTable()); llvm::GlobalValue *globalValue = moduleTranslation.lookupGlobal(global); - - if (!ompBuilder->Config.isTargetDevice()) { - llvm::Type *type = globalValue->getValueType(); - llvm::TypeSize typeSize = - builder.GetInsertBlock()->getModule()->getDataLayout().getTypeStoreSize( - type); - llvm::ConstantInt *size = builder.getInt64(typeSize.getFixedValue()); - llvm::Value *callInst = ompBuilder->createCachedThreadPrivate( - ompLoc, globalValue, size, global.getSymName() + ".cache"); - moduleTranslation.mapValue(opInst.getResult(0), callInst); - } else { - moduleTranslation.mapValue(opInst.getResult(0), globalValue); - } + llvm::Type *type = globalValue->getValueType(); + llvm::TypeSize typeSize = + builder.GetInsertBlock()->getModule()->getDataLayout().getTypeStoreSize( + type); + llvm::ConstantInt *size = builder.getInt64(typeSize.getFixedValue()); + llvm::Value *callInst = ompBuilder->createCachedThreadPrivate( + ompLoc, globalValue, size, global.getSymName() + ".cache"); + moduleTranslation.mapValue(opInst.getResult(0), callInst); return success(); } @@ -3632,6 +3628,8 @@ convertToCaptureClauseKind( return llvm::OffloadEntriesInfoManager::OMPTargetGlobalVarEntryLink; case mlir::omp::DeclareTargetCaptureClause::enter: return llvm::OffloadEntriesInfoManager::OMPTargetGlobalVarEntryEnter; + case mlir::omp::DeclareTargetCaptureClause::none: + return llvm::OffloadEntriesInfoManager::OMPTargetGlobalVarEntryNone; } llvm_unreachable("unhandled capture clause"); } @@ -3658,8 +3656,12 @@ getDeclareTargetRefPtrSuffix(LLVM::GlobalOp globalOp, return suffix; } -static bool isDeclareTargetLink(mlir::Value value) { - if (auto addressOfOp = value.getDefiningOp()) { +static bool isDeclareTargetLink(Value value) { + Operation *op = value.getDefiningOp(); + if (auto addrCast = llvm::dyn_cast_if_present(op)) + op = addrCast->getOperand(0).getDefiningOp(); + + if (auto addressOfOp = llvm::dyn_cast_if_present(op)) { auto modOp = addressOfOp->getParentOfType(); Operation *gOp = modOp.lookupSymbol(addressOfOp.getGlobalName()); if (auto declareTargetGlobal = @@ -3671,6 +3673,26 @@ static bool isDeclareTargetLink(mlir::Value value) { return false; } +static bool isDeclareTargetTo(Value value) { + Operation *op = value.getDefiningOp(); + if (auto addrCast = llvm::dyn_cast_if_present(op)) + op = addrCast->getOperand(0).getDefiningOp(); + + if (auto addressOfOp = llvm::dyn_cast_if_present(op)) { + auto modOp = addressOfOp->getParentOfType(); + Operation *gOp = modOp.lookupSymbol(addressOfOp.getGlobalName()); + if (auto declareTargetGlobal = + llvm::dyn_cast(gOp)) { + if (declareTargetGlobal.getDeclareTargetCaptureClause() == + mlir::omp::DeclareTargetCaptureClause::to || + declareTargetGlobal.getDeclareTargetCaptureClause() == + mlir::omp::DeclareTargetCaptureClause::enter) + return true; + } + } + return false; +} + // Returns the reference pointer generated by the lowering of the declare target // operation in cases where the link clause is used or the to clause is used in // USM mode. @@ -3756,6 +3778,30 @@ struct MapInfoData : MapInfosTy { MapInfosTy::append(CurInfo); } }; + +enum class TargetDirective : uint32_t { + None = 0, + Target = 1, + TargetData = 2, + TargetEnterData = 3, + TargetExitData = 4, + TargetUpdate = 5 +}; + +static TargetDirective getTargetDirectiveFromOp(Operation *op) { + return llvm::TypeSwitch(op) + .Case([](omp::TargetDataOp) { return TargetDirective::TargetData; }) + .Case([](omp::TargetEnterDataOp) { + return TargetDirective::TargetEnterData; + }) + .Case([&](omp::TargetExitDataOp) { + return TargetDirective::TargetExitData; + }) + .Case([&](omp::TargetUpdateOp) { return TargetDirective::TargetUpdate; }) + .Case([&](omp::TargetOp) { return TargetDirective::Target; }) + .Default([&](Operation *op) { return TargetDirective::None; }); +} + } // namespace static uint64_t getArrayElementSizeInBits(LLVM::LLVMArrayType arrTy, @@ -3819,7 +3865,8 @@ static llvm::Value *getSizeInBytes(DataLayout &dl, const mlir::Type &type, // bytes from the extent (ub - lb) * sizeInBytes. NOTE: This may need // some adjustment for members with more complex types. return builder.CreateMul(elementCount, - builder.getInt64(underlyingTypeSzInBits / 8)); + builder.getInt64(underlyingTypeSzInBits / 8), + "element_count"); } } @@ -3875,6 +3922,9 @@ convertClauseMapFlags(omp::ClauseMapFlags mlirFlags) { if (mapTypeToBool(omp::ClauseMapFlags::attach)) mapType |= llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_ATTACH; + if (mapTypeToBool(omp::ClauseMapFlags::descriptor)) + mapType |= llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_DESCRIPTOR; + return mapType; } @@ -3909,11 +3959,14 @@ static void collectMapDataFromMapOperands( mapData.OriginalValue.push_back(moduleTranslation.lookupValue(offloadPtr)); mapData.Pointers.push_back(mapData.OriginalValue.back()); + // if is declare target link OR to/enter in USM mode if (llvm::Value *refPtr = - getRefPtrIfDeclareTarget(offloadPtr, - moduleTranslation)) { // declare target + getRefPtrIfDeclareTarget(offloadPtr, moduleTranslation)) { mapData.IsDeclareTarget.push_back(true); mapData.BasePointers.push_back(refPtr); + } else if (isDeclareTargetTo(offloadPtr)) { + mapData.IsDeclareTarget.push_back(true); + mapData.BasePointers.push_back(mapData.OriginalValue.back()); } else { // regular mapped variable mapData.IsDeclareTarget.push_back(false); mapData.BasePointers.push_back(mapData.OriginalValue.back()); @@ -3940,11 +3993,18 @@ static void collectMapDataFromMapOperands( } auto findMapInfo = [&mapData](llvm::Value *val, - llvm::OpenMPIRBuilder::DeviceInfoTy devInfoTy) { + llvm::OpenMPIRBuilder::DeviceInfoTy devInfoTy, + size_t memberCount) { unsigned index = 0; bool found = false; for (llvm::Value *basePtr : mapData.OriginalValue) { - if (basePtr == val && mapData.IsAMapping[index]) { + auto mapOp = cast(mapData.MapClause[index]); + // TODO/FIXME: Currently we define an equivelant mapping as + // the same base pointer and an equivelant member count, but + // that is a loose definition, we may have to extend to check + // for other fields (varPtrPtr/invidiual members being mapped) + if (basePtr == val && mapData.IsAMapping[index] && + memberCount == mapOp.getMembers().size()) { found = true; mapData.Types[index] |= llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_RETURN_PARAM; @@ -3965,7 +4025,7 @@ static void collectMapDataFromMapOperands( llvm::Value *origValue = moduleTranslation.lookupValue(offloadPtr); // Check if map info is already present for this entry. - if (!findMapInfo(origValue, devInfoTy)) { + if (!findMapInfo(origValue, devInfoTy, mapOp.getMembers().size())) { mapData.OriginalValue.push_back(origValue); mapData.Pointers.push_back(mapData.OriginalValue.back()); mapData.IsDeclareTarget.push_back(false); @@ -4042,14 +4102,59 @@ static int getMapDataMemberIdx(MapInfoData &mapData, omp::MapInfoOp memberOp) { return std::distance(mapData.MapClause.begin(), res); } -static omp::MapInfoOp getFirstOrLastMappedMemberPtr(omp::MapInfoOp mapInfo, - bool first) { - ArrayAttr indexAttr = mapInfo.getMembersIndexAttr(); +static void sortMapIndices(llvm::SmallVector &indices, + mlir::omp::MapInfoOp mapInfo, + bool ascending = true) { + mlir::ArrayAttr indexAttr = mapInfo.getMembersIndexAttr(); + if (indexAttr.empty() || indexAttr.size() == 1 || indices.empty() || + indices.size() == 1) + return; + + llvm::sort( + indices.begin(), indices.end(), [&](const size_t a, const size_t b) { + auto memberIndicesA = mlir::cast(indexAttr[a]); + auto memberIndicesB = mlir::cast(indexAttr[b]); + + size_t smallestMember = memberIndicesA.size() < memberIndicesB.size() + ? memberIndicesA.size() + : memberIndicesB.size(); + + for (size_t i = 0; i < smallestMember; ++i) { + int64_t aIndex = + mlir::cast(memberIndicesA.getValue()[i]) + .getInt(); + int64_t bIndex = + mlir::cast(memberIndicesB.getValue()[i]) + .getInt(); + + if (aIndex == bIndex) + continue; + + if (aIndex < bIndex) + return ascending; + + if (aIndex > bIndex) + return !ascending; + } + + // Iterated up until the end of the smallest member and + // they were found to be equal up to that point, so select + // the member with the lowest index count, so the "parent" + return memberIndicesA.size() < memberIndicesB.size(); + }); +} + +static mlir::omp::MapInfoOp +getFirstOrLastMappedMemberPtr(mlir::omp::MapInfoOp mapInfo, bool first) { + mlir::ArrayAttr indexAttr = mapInfo.getMembersIndexAttr(); // Only 1 member has been mapped, we can return it. if (indexAttr.size() == 1) - return cast(mapInfo.getMembers()[0].getDefiningOp()); + if (auto mapOp = + dyn_cast(mapInfo.getMembers()[0].getDefiningOp())) + return mapOp; - llvm::SmallVector indices(indexAttr.size()); + llvm::SmallVector indices; + indices.resize(indexAttr.size()); std::iota(indices.begin(), indices.end(), 0); llvm::sort(indices, [&](const size_t a, const size_t b) { @@ -4172,6 +4277,91 @@ calculateBoundsOffset(LLVM::ModuleTranslation &moduleTranslation, return idx; } +// Gathers members that are overlapping in the parent, excluding members that +// themselves overlap, keeping the top-most (closest to parents level) map. +static void getOverlappedMembers(llvm::SmallVector &overlapMapDataIdxs, + MapInfoData &mapData, + omp::MapInfoOp parentOp) { + // No members mapped, no overlaps. + if (parentOp.getMembers().empty()) + return; + + // Single member, we can insert and return early. + if (parentOp.getMembers().size() == 1) { + overlapMapDataIdxs.push_back(0); + return; + } + + // 1) collect list of top-level overlapping members from MemberOp + llvm::SmallVector> memberByIndex; + mlir::ArrayAttr indexAttr = parentOp.getMembersIndexAttr(); + for (auto [memIndex, indicesAttr] : llvm::enumerate(indexAttr)) + memberByIndex.push_back( + std::make_pair(memIndex, mlir::cast(indicesAttr))); + + // Sort the smallest first (higher up the parent -> member chain), so that + // when we remove members, we remove as much as we can in the initial + // iterations, shortening the number of passes required. + llvm::sort(memberByIndex.begin(), memberByIndex.end(), + [&](auto a, auto b) { return a.second.size() < b.second.size(); }); + + auto getAsIntegers = [](mlir::ArrayAttr values) { + llvm::SmallVector ints; + ints.reserve(values.size()); + llvm::transform(values, std::back_inserter(ints), + [](mlir::Attribute value) { + return mlir::cast(value).getInt(); + }); + return ints; + }; + + // Remove elements from the vector if there is a parent element that + // supersedes it. i.e. if member [0] is mapped, we can remove members [0,1], + // [0,2].. etc. + for (auto v : make_early_inc_range(memberByIndex)) { + auto vArr = getAsIntegers(v.second); + memberByIndex.erase( + std::remove_if(memberByIndex.begin(), memberByIndex.end(), + [&](auto x) { + if (v == x) + return false; + + auto xArr = getAsIntegers(x.second); + return std::equal(vArr.begin(), vArr.end(), + xArr.begin()) && + xArr.size() >= vArr.size(); + }), + memberByIndex.end()); + } + + // Collect the indices from mapData that we need, as we technically need the + // base pointer etc. info, which is stored in there and primarily accessible + // via index at the moment. + for (auto v : memberByIndex) + overlapMapDataIdxs.push_back(v.first); +} + +// The intent is to verify if the mapped data being passed is a +// pointer -> pointee that requires special handling in certain cases, +// e.g. applying the OMP_MAP_PTR_AND_OBJ map type. +// +// There may be a better way to verify this, but unfortunately with +// opaque pointers we lose the ability to easily check if something is +// a pointer whilst maintaining access to the underlying type. +static bool checkIfPointerMap(omp::MapInfoOp mapOp) { + // If we have a varPtrPtr field assigned then the underlying type is a pointer + if (mapOp.getVarPtrPtr()) + return true; + + // If the map data is declare target with a link clause, then it's represented + // as a pointer when we lower it to LLVM-IR even if at the MLIR level it has + // no relation to pointers. + if (isDeclareTargetLink(mapOp.getVarPtr())) + return true; + + return false; +} + // This creates two insertions into the MapInfosTy data structure for the // "parent" of a set of members, (usually a container e.g. // class/structure/derived type) when subsequent members have also been @@ -4187,19 +4377,23 @@ calculateBoundsOffset(LLVM::ModuleTranslation &moduleTranslation, // // This function borrows a lot from Clang's emitCombinedEntry function // inside of CGOpenMPRuntime.cpp -static llvm::omp::OpenMPOffloadMappingFlags mapParentWithMembers( - LLVM::ModuleTranslation &moduleTranslation, llvm::IRBuilderBase &builder, - llvm::OpenMPIRBuilder &ompBuilder, DataLayout &dl, MapInfosTy &combinedInfo, - MapInfoData &mapData, uint64_t mapDataIndex, bool isTargetParams) { +static llvm::omp::OpenMPOffloadMappingFlags +mapParentWithMembers(LLVM::ModuleTranslation &moduleTranslation, + llvm::IRBuilderBase &builder, + llvm::OpenMPIRBuilder &ompBuilder, DataLayout &dl, + MapInfosTy &combinedInfo, MapInfoData &mapData, + uint64_t mapDataIndex, TargetDirective targetDirective) { assert(!ompBuilder.Config.isTargetDevice() && "function only supported for host device codegen"); + const size_t parentIndex = combinedInfo.Types.size(); // Map the first segment of the parent. If a user-defined mapper is attached, // include the parent's to/from-style bits (and common modifiers) in this // base entry so the mapper receives correct copy semantics via its 'type' // parameter. Also keep TARGET_PARAM when required for kernel arguments. llvm::omp::OpenMPOffloadMappingFlags baseFlag = - isTargetParams + (targetDirective == TargetDirective::Target && + !mapData.IsDeclareTarget[mapDataIndex]) ? llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_TARGET_PARAM : llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_NONE; @@ -4266,7 +4460,7 @@ static llvm::omp::OpenMPOffloadMappingFlags mapParentWithMembers( combinedInfo.Sizes.push_back(size); llvm::omp::OpenMPOffloadMappingFlags memberOfFlag = - ompBuilder.getMemberOfFlag(combinedInfo.BasePointers.size() - 1); + ompBuilder.getMemberOfFlag(parentIndex); // This creates the initial MEMBER_OF mapping that consists of // the parent/top level container (same as above effectively, except @@ -4280,39 +4474,84 @@ static llvm::omp::OpenMPOffloadMappingFlags mapParentWithMembers( // further case specific flag modifications). For the moment, it handles // what we support as expected. llvm::omp::OpenMPOffloadMappingFlags mapFlag = mapData.Types[mapDataIndex]; + bool hasMapClose = (llvm::omp::OpenMPOffloadMappingFlags(mapFlag) & + llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_CLOSE) == + llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_CLOSE; ompBuilder.setCorrectMemberOfFlag(mapFlag, memberOfFlag); - combinedInfo.Types.emplace_back(mapFlag); - combinedInfo.DevicePointers.emplace_back( - llvm::OpenMPIRBuilder::DeviceInfoTy::None); - combinedInfo.Mappers.emplace_back(nullptr); - combinedInfo.Names.emplace_back(LLVM::createMappingInformation( - mapData.MapClause[mapDataIndex]->getLoc(), ompBuilder)); - combinedInfo.BasePointers.emplace_back(mapData.BasePointers[mapDataIndex]); - combinedInfo.Pointers.emplace_back(mapData.Pointers[mapDataIndex]); - combinedInfo.Sizes.emplace_back(mapData.Sizes[mapDataIndex]); - } - return memberOfFlag; -} -// The intent is to verify if the mapped data being passed is a -// pointer -> pointee that requires special handling in certain cases, -// e.g. applying the OMP_MAP_PTR_AND_OBJ map type. -// -// There may be a better way to verify this, but unfortunately with -// opaque pointers we lose the ability to easily check if something is -// a pointer whilst maintaining access to the underlying type. -static bool checkIfPointerMap(omp::MapInfoOp mapOp) { - // If we have a varPtrPtr field assigned then the underlying type is a pointer - if (mapOp.getVarPtrPtr()) - return true; - - // If the map data is declare target with a link clause, then it's represented - // as a pointer when we lower it to LLVM-IR even if at the MLIR level it has - // no relation to pointers. - if (isDeclareTargetLink(mapOp.getVarPtr())) - return true; + if (targetDirective == TargetDirective::TargetUpdate || hasMapClose) { + combinedInfo.Types.emplace_back(mapFlag); + combinedInfo.DevicePointers.emplace_back( + mapData.DevicePointers[mapDataIndex]); + combinedInfo.Mappers.emplace_back(mapData.Mappers[mapDataIndex]); + combinedInfo.Names.emplace_back(LLVM::createMappingInformation( + mapData.MapClause[mapDataIndex]->getLoc(), ompBuilder)); + combinedInfo.BasePointers.emplace_back( + mapData.BasePointers[mapDataIndex]); + combinedInfo.Pointers.emplace_back(mapData.Pointers[mapDataIndex]); + combinedInfo.Sizes.emplace_back(mapData.Sizes[mapDataIndex]); + } else { + llvm::SmallVector overlapIdxs; + // Find all of the members that "overlap", i.e. occlude other members that + // were mapped alongside the parent, e.g. member [0], occludes + getOverlappedMembers(overlapIdxs, mapData, parentClause); + // We need to make sure the overlapped members are sorted in order of + // lowest address to highest address + sortMapIndices(overlapIdxs, parentClause); + + lowAddr = builder.CreatePointerCast(mapData.Pointers[mapDataIndex], + builder.getPtrTy()); + highAddr = builder.CreatePointerCast( + builder.CreateConstGEP1_32(mapData.BaseType[mapDataIndex], + mapData.Pointers[mapDataIndex], 1), + builder.getPtrTy()); + + // TODO: We may want to skip arrays/array sections in this as Clang does + // so it appears to be an optimisation rather than a neccessity though, + // but this requires further investigation. However, we would have to make + // sure to not exclude maps with bounds that ARE pointers, as these are + // processed as seperate components, i.e. pointer + data. + for (auto v : overlapIdxs) { + auto mapDataOverlapIdx = getMapDataMemberIdx( + mapData, + cast(parentClause.getMembers()[v].getDefiningOp())); + combinedInfo.Types.emplace_back(mapFlag); + combinedInfo.DevicePointers.emplace_back( + mapData.DevicePointers[mapDataOverlapIdx]); + combinedInfo.Mappers.emplace_back(mapData.Mappers[mapDataOverlapIdx]); + combinedInfo.Names.emplace_back(LLVM::createMappingInformation( + mapData.MapClause[mapDataIndex]->getLoc(), ompBuilder)); + combinedInfo.BasePointers.emplace_back( + mapData.BasePointers[mapDataIndex]); + combinedInfo.Pointers.emplace_back(lowAddr); + combinedInfo.Sizes.emplace_back(builder.CreateIntCast( + builder.CreatePtrDiff(builder.getInt8Ty(), + mapData.OriginalValue[mapDataOverlapIdx], + lowAddr), + builder.getInt64Ty(), /*isSigned=*/true)); + lowAddr = builder.CreateConstGEP1_32( + checkIfPointerMap(llvm::cast( + mapData.MapClause[mapDataOverlapIdx])) + ? builder.getPtrTy() + : mapData.BaseType[mapDataOverlapIdx], + mapData.BasePointers[mapDataOverlapIdx], 1); + } - return false; + combinedInfo.Types.emplace_back(mapFlag); + combinedInfo.DevicePointers.emplace_back( + mapData.DevicePointers[mapDataIndex]); + combinedInfo.Mappers.emplace_back(mapData.Mappers[mapDataIndex]); + combinedInfo.Names.emplace_back(LLVM::createMappingInformation( + mapData.MapClause[mapDataIndex]->getLoc(), ompBuilder)); + combinedInfo.BasePointers.emplace_back( + mapData.BasePointers[mapDataIndex]); + combinedInfo.Pointers.emplace_back(lowAddr); + combinedInfo.Sizes.emplace_back(builder.CreateIntCast( + builder.CreatePtrDiff(builder.getInt8Ty(), highAddr, lowAddr), + builder.getInt64Ty(), true)); + } + } + return memberOfFlag; } // This function is intended to add explicit mappings of members @@ -4320,7 +4559,8 @@ static void processMapMembersWithParent( LLVM::ModuleTranslation &moduleTranslation, llvm::IRBuilderBase &builder, llvm::OpenMPIRBuilder &ompBuilder, DataLayout &dl, MapInfosTy &combinedInfo, MapInfoData &mapData, uint64_t mapDataIndex, - llvm::omp::OpenMPOffloadMappingFlags memberOfFlag) { + llvm::omp::OpenMPOffloadMappingFlags memberOfFlag, + TargetDirective targetDirective) { assert(!ompBuilder.Config.isTargetDevice() && "function only supported for host device codegen"); @@ -4342,7 +4582,14 @@ static void processMapMembersWithParent( // in part as we currently have substantially less information on the data // being mapped at this stage. if (checkIfPointerMap(memberClause)) { - auto mapFlag = convertClauseMapFlags(memberClause.getMapType()); + auto mapFlag = + llvm::omp::OpenMPOffloadMappingFlags(mapData.Types[memberDataIdx]); + // We wish to remove user specified always, as the pointer is a + // seperate implementation detail/entity. And tagging it with + // always can cause the data to be overwritten. It is likely + // debateable if we should carry over any user speicifed map types + // to the pointer, but we can evaluate on a case by case basis. + mapFlag &= ~llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_ALWAYS; mapFlag &= ~llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_TARGET_PARAM; mapFlag |= llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_MEMBER_OF; ompBuilder.setCorrectMemberOfFlag(mapFlag, memberOfFlag); @@ -4361,17 +4608,25 @@ static void processMapMembersWithParent( // Same MemberOfFlag to indicate its link with parent and other members // of. - auto mapFlag = convertClauseMapFlags(memberClause.getMapType()); + auto mapFlag = + llvm::omp::OpenMPOffloadMappingFlags(mapData.Types[memberDataIdx]); mapFlag &= ~llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_TARGET_PARAM; mapFlag |= llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_MEMBER_OF; ompBuilder.setCorrectMemberOfFlag(mapFlag, memberOfFlag); - if (checkIfPointerMap(memberClause)) + bool isDeclTarTo = isDeclareTargetTo(parentClause.getVarPtr() + ? parentClause.getVarPtr() + : parentClause.getVarPtrPtr()); + if (checkIfPointerMap(memberClause) && + (!isDeclTarTo || + (isDeclTarTo && targetDirective != TargetDirective::TargetUpdate && + targetDirective != TargetDirective::TargetData))) { mapFlag |= llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_PTR_AND_OBJ; + } combinedInfo.Types.emplace_back(mapFlag); combinedInfo.DevicePointers.emplace_back( - mapData.DevicePointers[memberDataIdx]); - combinedInfo.Mappers.emplace_back(mapData.Mappers[memberDataIdx]); + llvm::OpenMPIRBuilder::DeviceInfoTy::None); + combinedInfo.Mappers.emplace_back(nullptr); combinedInfo.Names.emplace_back( LLVM::createMappingInformation(memberClause.getLoc(), ompBuilder)); uint64_t basePointerIndex = @@ -4392,7 +4647,8 @@ static void processMapMembersWithParent( } static void processIndividualMap(MapInfoData &mapData, size_t mapDataIdx, - MapInfosTy &combinedInfo, bool isTargetParams, + MapInfosTy &combinedInfo, + TargetDirective targetDirective, int mapDataParentIdx = -1) { // Declare Target Mappings are excluded from being marked as // OMP_MAP_TARGET_PARAM as they are not passed as parameters, they're @@ -4404,7 +4660,8 @@ static void processIndividualMap(MapInfoData &mapData, size_t mapDataIdx, if (isPtrTy) mapFlag |= llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_PTR_AND_OBJ; - if (isTargetParams && !mapData.IsDeclareTarget[mapDataIdx]) + if (targetDirective == TargetDirective::Target && + !mapData.IsDeclareTarget[mapDataIdx]) mapFlag |= llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_TARGET_PARAM; if (mapInfoOp.getMapCaptureType() == omp::VariableCaptureKind::ByCopy && @@ -4433,7 +4690,7 @@ static void processMapWithMembersOf(LLVM::ModuleTranslation &moduleTranslation, llvm::OpenMPIRBuilder &ompBuilder, DataLayout &dl, MapInfosTy &combinedInfo, MapInfoData &mapData, uint64_t mapDataIndex, - bool isTargetParams) { + TargetDirective targetDirective) { assert(!ompBuilder.Config.isTargetDevice() && "function only supported for host device codegen"); @@ -4457,17 +4714,18 @@ static void processMapWithMembersOf(LLVM::ModuleTranslation &moduleTranslation, // Clang maps array without bounds as pointers (which we do not // currently do), whereas we treat them as arrays in all cases // currently. - processIndividualMap(mapData, memberDataIdx, combinedInfo, isTargetParams, + processIndividualMap(mapData, memberDataIdx, combinedInfo, targetDirective, mapDataIndex); return; } llvm::omp::OpenMPOffloadMappingFlags memberOfParentFlag = mapParentWithMembers(moduleTranslation, builder, ompBuilder, dl, - combinedInfo, mapData, mapDataIndex, isTargetParams); + combinedInfo, mapData, mapDataIndex, + targetDirective); processMapMembersWithParent(moduleTranslation, builder, ompBuilder, dl, combinedInfo, mapData, mapDataIndex, - memberOfParentFlag); + memberOfParentFlag, targetDirective); } // This is a variation on Clang's GenerateOpenMPCapturedVars, which @@ -4545,7 +4803,7 @@ createAlteredByCaptureMap(MapInfoData &mapData, static void genMapInfos(llvm::IRBuilderBase &builder, LLVM::ModuleTranslation &moduleTranslation, DataLayout &dl, MapInfosTy &combinedInfo, - MapInfoData &mapData, bool isTargetParams = false) { + MapInfoData &mapData, TargetDirective targetDirective) { assert(!moduleTranslation.getOpenMPBuilder()->Config.isTargetDevice() && "function only supported for host device codegen"); @@ -4578,11 +4836,11 @@ static void genMapInfos(llvm::IRBuilderBase &builder, auto mapInfoOp = dyn_cast(mapData.MapClause[i]); if (!mapInfoOp.getMembers().empty()) { processMapWithMembersOf(moduleTranslation, builder, *ompBuilder, dl, - combinedInfo, mapData, i, isTargetParams); + combinedInfo, mapData, i, targetDirective); continue; } - processIndividualMap(mapData, i, combinedInfo, isTargetParams); + processIndividualMap(mapData, i, combinedInfo, targetDirective); } } @@ -4639,7 +4897,8 @@ emitUserDefinedMapper(Operation *op, llvm::IRBuilderBase &builder, MapInfoData mapData; collectMapDataFromMapOperands(mapData, mapVars, moduleTranslation, dl, builder); - genMapInfos(builder, moduleTranslation, dl, combinedInfo, mapData); + genMapInfos(builder, moduleTranslation, dl, combinedInfo, mapData, + TargetDirective::None); // Drop the mapping that is no longer necessary so that the same region can // be processed multiple times. @@ -4672,6 +4931,7 @@ convertOmpTargetData(Operation *op, llvm::IRBuilderBase &builder, SmallVector useDeviceAddrVars; llvm::omp::RuntimeFunction RTLFn; DataLayout DL = DataLayout(op->getParentOfType()); + TargetDirective targetDirective = getTargetDirectiveFromOp(op); llvm::OpenMPIRBuilder *ompBuilder = moduleTranslation.getOpenMPBuilder(); llvm::OpenMPIRBuilder::TargetDataInfo info(/*RequiresDevicePointerInfo=*/true, @@ -4690,7 +4950,8 @@ convertOmpTargetData(Operation *op, llvm::IRBuilderBase &builder, ifCond = moduleTranslation.lookupValue(ifVar); if (auto devId = dataOp.getDevice()) - if (auto constOp = devId.getDefiningOp()) + if (auto constOp = + dyn_cast(devId.getDefiningOp())) if (auto intAttr = dyn_cast(constOp.getValue())) deviceID = intAttr.getInt(); @@ -4707,7 +4968,8 @@ convertOmpTargetData(Operation *op, llvm::IRBuilderBase &builder, ifCond = moduleTranslation.lookupValue(ifVar); if (auto devId = enterDataOp.getDevice()) - if (auto constOp = devId.getDefiningOp()) + if (auto constOp = + dyn_cast(devId.getDefiningOp())) if (auto intAttr = dyn_cast(constOp.getValue())) deviceID = intAttr.getInt(); RTLFn = @@ -4726,7 +4988,8 @@ convertOmpTargetData(Operation *op, llvm::IRBuilderBase &builder, ifCond = moduleTranslation.lookupValue(ifVar); if (auto devId = exitDataOp.getDevice()) - if (auto constOp = devId.getDefiningOp()) + if (auto constOp = + dyn_cast(devId.getDefiningOp())) if (auto intAttr = dyn_cast(constOp.getValue())) deviceID = intAttr.getInt(); @@ -4745,7 +5008,8 @@ convertOmpTargetData(Operation *op, llvm::IRBuilderBase &builder, ifCond = moduleTranslation.lookupValue(ifVar); if (auto devId = updateDataOp.getDevice()) - if (auto constOp = devId.getDefiningOp()) + if (auto constOp = + dyn_cast(devId.getDefiningOp())) if (auto intAttr = dyn_cast(constOp.getValue())) deviceID = intAttr.getInt(); @@ -4774,7 +5038,8 @@ convertOmpTargetData(Operation *op, llvm::IRBuilderBase &builder, MapInfosTy combinedInfo; auto genMapInfoCB = [&](InsertPointTy codeGenIP) -> MapInfosTy & { builder.restoreIP(codeGenIP); - genMapInfos(builder, moduleTranslation, DL, combinedInfo, mapData); + genMapInfos(builder, moduleTranslation, DL, combinedInfo, mapData, + targetDirective); return combinedInfo; }; @@ -4842,9 +5107,14 @@ convertOmpTargetData(Operation *op, llvm::IRBuilderBase &builder, return info.DevicePtrInfoMap[basePointer].second; }); - if (failed(inlineConvertOmpRegions(region, "omp.data.region", builder, - moduleTranslation))) - return llvm::make_error(); + SmallVector phis; + llvm::Expected continuationBlock = + convertOmpOpRegions(region, "omp.data.region", builder, + moduleTranslation, &phis); + if (!continuationBlock) + return continuationBlock.takeError(); + builder.SetInsertPoint(*continuationBlock, + (*continuationBlock)->getFirstInsertionPt()); } break; case BodyGenTy::DupNoPriv: @@ -4875,9 +5145,14 @@ convertOmpTargetData(Operation *op, llvm::IRBuilderBase &builder, useDevicePtrVars, mapData); } - if (failed(inlineConvertOmpRegions(region, "omp.data.region", builder, - moduleTranslation))) - return llvm::make_error(); + SmallVector phis; + llvm::Expected continuationBlock = + convertOmpOpRegions(region, "omp.data.region", builder, + moduleTranslation, &phis); + if (!continuationBlock) + return continuationBlock.takeError(); + builder.SetInsertPoint(*continuationBlock, + (*continuationBlock)->getFirstInsertionPt()); } break; } @@ -5131,35 +5406,44 @@ handleDeclareTargetMapVar(MapInfoData &mapData, // function to link the two variables in the runtime and then both the // reference pointer and the pointer are assigned in the kernel argument // structure for the host. - if (mapData.IsDeclareTarget[i]) { - // If the original map value is a constant, then we have to make sure all - // of it's uses within the current kernel/function that we are going to - // rewrite are converted to instructions, as we will be altering the old - // use (OriginalValue) from a constant to an instruction, which will be - // illegal and ICE the compiler if the user is a constant expression of - // some kind e.g. a constant GEP. - if (auto *constant = dyn_cast(mapData.OriginalValue[i])) - convertUsersOfConstantsToInstructions(constant, func, false); - - // The users iterator will get invalidated if we modify an element, - // so we populate this vector of uses to alter each user on an - // individual basis to emit its own load (rather than one load for - // all). - llvm::SmallVector userVec; - for (llvm::User *user : mapData.OriginalValue[i]->users()) - userVec.push_back(user); - - for (llvm::User *user : userVec) { - if (auto *insn = dyn_cast(user)) { - if (insn->getFunction() == func) { - builder.SetCurrentDebugLocation(insn->getDebugLoc()); - auto *load = builder.CreateLoad(mapData.BasePointers[i]->getType(), - mapData.BasePointers[i]); - load->moveBefore(insn->getIterator()); - user->replaceUsesOfWith(mapData.OriginalValue[i], load); - } - } + if (!mapData.IsDeclareTarget[i]) + continue; + // If the original map value is a constant, then we have to make sure all + // of it's uses within the current kernel/function that we are going to + // rewrite are converted to instructions, as we will be altering the old + // use (OriginalValue) from a constant to an instruction, which will be + // illegal and ICE the compiler if the user is a constant expression of + // some kind e.g. a constant GEP. + if (auto *constant = dyn_cast(mapData.OriginalValue[i])) + convertUsersOfConstantsToInstructions(constant, func, false); + + // The users iterator will get invalidated if we modify an element, + // so we populate this vector of uses to alter each user on an + // individual basis to emit its own load (rather than one load for + // all). + llvm::SmallVector userVec; + for (llvm::User *user : mapData.OriginalValue[i]->users()) + userVec.push_back(user); + + for (llvm::User *user : userVec) { + auto *insn = dyn_cast(user); + if (!insn || insn->getFunction() != func) + continue; + auto mapOp = cast(mapData.MapClause[i]); + llvm::Value *substitute = mapData.BasePointers[i]; + if (isDeclareTargetLink(mapOp.getVarPtrPtr() ? mapOp.getVarPtrPtr() + : mapOp.getVarPtr()) || + (isDeclareTargetTo(mapOp.getVarPtrPtr() ? mapOp.getVarPtrPtr() + : mapOp.getVarPtr()) && + moduleTranslation.getOpenMPBuilder() + ->Config.hasRequiresUnifiedSharedMemory())) { + builder.SetCurrentDebugLocation(insn->getDebugLoc()); + auto *load = builder.CreateLoad(mapData.BasePointers[i]->getType(), + mapData.BasePointers[i]); + load->moveBefore(insn); + substitute = load; } + user->replaceUsesOfWith(mapData.OriginalValue[i], substitute); } } } @@ -5235,7 +5519,7 @@ createDeviceArgumentAccessor(MapInfoData &mapData, llvm::Argument &arg, ompBuilder.M.getDataLayout().getProgramAddressSpace(); // Create the alloca for the argument the current point. - llvm::Value *v = builder.CreateAlloca(arg.getType(), allocaAS); + llvm::Value *v = builder.CreateAlloca(arg.getType(), allocaAS, nullptr); if (allocaAS != defaultAS && arg.getType()->isPointerTy()) v = builder.CreateAddrSpaceCast(v, builder.getPtrTy(defaultAS)); @@ -5382,7 +5666,8 @@ static std::optional extractConstInteger(Value value) { if (!value) return std::nullopt; - if (auto constOp = value.getDefiningOp()) + if (auto constOp = + dyn_cast_if_present(value.getDefiningOp())) if (auto constAttr = dyn_cast(constOp.getValue())) return constAttr.getInt(); @@ -5658,6 +5943,7 @@ convertOmpTarget(Operation &opInst, llvm::IRBuilderBase &builder, ArrayRef mapBlockArgs = argIface.getMapBlockArgs(); ArrayRef hdaBlockArgs = argIface.getHasDeviceAddrBlockArgs(); llvm::Function *llvmOutlinedFn = nullptr; + TargetDirective targetDirective = getTargetDirectiveFromOp(&opInst); // TODO: It can also be false if a compile-time constant `false` IF clause is // specified. @@ -5819,7 +6105,8 @@ convertOmpTarget(Operation &opInst, llvm::IRBuilderBase &builder, auto genMapInfoCB = [&](llvm::OpenMPIRBuilder::InsertPointTy codeGenIP) -> MapInfosTy & { builder.restoreIP(codeGenIP); - genMapInfos(builder, moduleTranslation, dl, combinedInfos, mapData, true); + genMapInfos(builder, moduleTranslation, dl, combinedInfos, mapData, + targetDirective); return combinedInfos; }; @@ -5926,6 +6213,78 @@ convertOmpTarget(Operation &opInst, llvm::IRBuilderBase &builder, return success(); } +// Add DIOp based expression in the declare target variables for AMDGPU target. +static void updateDebugInfoForDeclareTargetVariables( + LLVM::GlobalOp globalOp, LLVM::ModuleTranslation &moduleTranslation) { + llvm::Module *M = moduleTranslation.getLLVMModule(); + if (!llvm::Triple(M->getTargetTriple()).isAMDGPU()) + return; + + llvm::GlobalVariable *GV = M->getGlobalVariable(globalOp.getSymName()); + if (GV) { + llvm::SmallVector GVEs; + GV->getDebugInfo(GVEs); + GV->eraseMetadata(llvm::LLVMContext::MD_dbg); + llvm::DIExprBuilder ExprBuilder(M->getContext()); + unsigned int globalAS = M->getDataLayout().getDefaultGlobalsAddressSpace(); + auto ptrTy = llvm::PointerType::get(M->getContext(), globalAS); + ExprBuilder.append(0u, ptrTy); + ExprBuilder.append(GV->getType()); + for (auto *GVE : GVEs) { + llvm::DIExpression *Old = GVE->getExpression(); + assert((Old == nullptr) || (Old->getNumElements() == 0)); + auto *newGVE = llvm::DIGlobalVariableExpression::get( + M->getContext(), GVE->getVariable(), ExprBuilder.intoExpression()); + GV->addDebugInfo(newGVE); + } + } +} + +// This function Add DIOp based expressions to the debug records in the +// declare target functions. + +static void updateDebugInfoForDeclareTargetFunctions( + llvm::Function *Fn, LLVM::ModuleTranslation &moduleTranslation) { + llvm::OpenMPIRBuilder *ompBuilder = moduleTranslation.getOpenMPBuilder(); + llvm::Module &M = ompBuilder->M; + + if (!llvm::Triple(M.getTargetTriple()).isAMDGPU()) + return; + + auto AddExpression = [&](auto *DR) { + llvm::DIExpression *Old = DR->getExpression(); + // Skip if an expression is already present. + if ((Old != nullptr) && (Old->getNumElements() != 0)) + return; + // Skip if the there are multiple inputs. + // FIXME: Could this be an assert? More to the point, can we do this at the + // point of generating the intrinsics to begin with, rather than fixing them + // up here? + if (DR->getNumVariableLocationOps() != 1u) + return; + auto Loc = DR->getVariableLocationOp(0u); + llvm::DIExprBuilder EB(Fn->getContext()); + if (auto AI = dyn_cast(Loc->stripPointerCasts())) { + DR->replaceVariableLocationOp(0u, AI); + EB.append(0u, AI->getType()); + EB.append(AI->getAllocatedType()); + } else if (Loc->getType()->isPointerTy()) { + EB.append(0u, Loc->getType()); + EB.append(Loc->getType()); + } else + EB.append(0u, Loc->getType()); + DR->setExpression(EB.intoExpression()); + }; + + for (llvm::Instruction &I : instructions(Fn)) { + if (auto *DDI = dyn_cast(&I)) + AddExpression(DDI); + + for (llvm::DbgVariableRecord &DVR : filterDbgVars(I.getDbgRecordRange())) + AddExpression(&DVR); + } +} + static LogicalResult convertDeclareTargetAttr(Operation *op, mlir::omp::DeclareTargetAttr attribute, LLVM::ModuleTranslation &moduleTranslation) { @@ -5945,18 +6304,20 @@ convertDeclareTargetAttr(Operation *op, mlir::omp::DeclareTargetAttr attribute, omp::DeclareTargetDeviceType declareType = attribute.getDeviceType().getValue(); + llvm::Function *llvmFunc = + moduleTranslation.lookupFunction(funcOp.getName()); if (declareType == omp::DeclareTargetDeviceType::host) { - llvm::Function *llvmFunc = - moduleTranslation.lookupFunction(funcOp.getName()); llvmFunc->dropAllReferences(); llvmFunc->eraseFromParent(); - } + } else + updateDebugInfoForDeclareTargetFunctions(llvmFunc, moduleTranslation); } return success(); } if (LLVM::GlobalOp gOp = dyn_cast(op)) { llvm::Module *llvmModule = moduleTranslation.getLLVMModule(); + updateDebugInfoForDeclareTargetVariables(gOp, moduleTranslation); if (auto *gVal = llvmModule->getNamedValue(gOp.getSymName())) { llvm::OpenMPIRBuilder *ompBuilder = moduleTranslation.getOpenMPBuilder(); bool isDeclaration = gOp.isDeclaration(); @@ -6002,15 +6363,19 @@ convertDeclareTargetAttr(Operation *op, mlir::omp::DeclareTargetAttr attribute, gVal->getType(), gVal); if (ompBuilder->Config.isTargetDevice() && - (attribute.getCaptureClause().getValue() != - mlir::omp::DeclareTargetCaptureClause::to || + ((attribute.getCaptureClause().getValue() != + mlir::omp::DeclareTargetCaptureClause::to && + attribute.getCaptureClause().getValue() != + mlir::omp::DeclareTargetCaptureClause::enter) || ompBuilder->Config.hasRequiresUnifiedSharedMemory())) { + llvm::Type *ptrTy = gVal->getType(); + if (ompBuilder->Config.hasRequiresUnifiedSharedMemory()) + ptrTy = llvm::PointerType::get(llvmModule->getContext(), 0); ompBuilder->getAddrOfDeclareTargetVar( captureClause, deviceClause, isDeclaration, isExternallyVisible, ompBuilder->getTargetEntryUniqueInfo(fileInfoCallBack, *vfs), mangledName, generatedRefs, /*OpenMPSimd*/ false, targetTriple, - gVal->getType(), /*GlobalInitializer*/ nullptr, - /*VariableLinkage*/ nullptr); + ptrTy, /*GlobalInitializer*/ nullptr, /*VariableLinkage*/ nullptr); } } } @@ -6018,33 +6383,159 @@ convertDeclareTargetAttr(Operation *op, mlir::omp::DeclareTargetAttr attribute, return success(); } -// Returns true if the operation is inside a TargetOp or -// is part of a declare target function. -static bool isTargetDeviceOp(Operation *op) { +namespace { + +/// Implementation of the dialect interface that converts operations belonging +/// to the OpenMP dialect to LLVM IR. +class OpenMPDialectLLVMIRTranslationInterface + : public LLVMTranslationDialectInterface { +public: + using LLVMTranslationDialectInterface::LLVMTranslationDialectInterface; + + /// Translates the given operation to LLVM IR using the provided IR builder + /// and saving the state in `moduleTranslation`. + LogicalResult + convertOperation(Operation *op, llvm::IRBuilderBase &builder, + LLVM::ModuleTranslation &moduleTranslation) const final; + + /// Given an OpenMP MLIR attribute, create the corresponding LLVM-IR, + /// runtime calls, or operation amendments + LogicalResult + amendOperation(Operation *op, ArrayRef instructions, + NamedAttribute attribute, + LLVM::ModuleTranslation &moduleTranslation) const final; +}; + +} // namespace + +LogicalResult OpenMPDialectLLVMIRTranslationInterface::amendOperation( + Operation *op, ArrayRef instructions, + NamedAttribute attribute, + LLVM::ModuleTranslation &moduleTranslation) const { + return llvm::StringSwitch>( + attribute.getName()) + .Case("omp.is_target_device", + [&](Attribute attr) { + if (auto deviceAttr = dyn_cast(attr)) { + llvm::OpenMPIRBuilderConfig &config = + moduleTranslation.getOpenMPBuilder()->Config; + config.setIsTargetDevice(deviceAttr.getValue()); + return success(); + } + return failure(); + }) + .Case("omp.is_gpu", + [&](Attribute attr) { + if (auto gpuAttr = dyn_cast(attr)) { + llvm::OpenMPIRBuilderConfig &config = + moduleTranslation.getOpenMPBuilder()->Config; + config.setIsGPU(gpuAttr.getValue()); + return success(); + } + return failure(); + }) + .Case("omp.host_ir_filepath", + [&](Attribute attr) { + if (auto filepathAttr = dyn_cast(attr)) { + llvm::OpenMPIRBuilder *ompBuilder = + moduleTranslation.getOpenMPBuilder(); + auto VFS = llvm::vfs::getRealFileSystem(); + ompBuilder->loadOffloadInfoMetadata(*VFS, filepathAttr.getValue()); + return success(); + } + return failure(); + }) + .Case("omp.flags", + [&](Attribute attr) { + if (auto rtlAttr = dyn_cast(attr)) + return convertFlagsAttr(op, rtlAttr, moduleTranslation); + return failure(); + }) + .Case("omp.version", + [&](Attribute attr) { + if (auto versionAttr = dyn_cast(attr)) { + llvm::OpenMPIRBuilder *ompBuilder = + moduleTranslation.getOpenMPBuilder(); + ompBuilder->M.addModuleFlag(llvm::Module::Max, "openmp", + versionAttr.getVersion()); + return success(); + } + return failure(); + }) + .Case("omp.declare_target", + [&](Attribute attr) { + if (auto declareTargetAttr = + dyn_cast(attr)) + return convertDeclareTargetAttr(op, declareTargetAttr, + moduleTranslation); + return failure(); + }) + .Case("omp.requires", + [&](Attribute attr) { + if (auto requiresAttr = dyn_cast(attr)) { + using Requires = omp::ClauseRequires; + Requires flags = requiresAttr.getValue(); + llvm::OpenMPIRBuilderConfig &config = + moduleTranslation.getOpenMPBuilder()->Config; + config.setHasRequiresReverseOffload( + bitEnumContainsAll(flags, Requires::reverse_offload)); + config.setHasRequiresUnifiedAddress( + bitEnumContainsAll(flags, Requires::unified_address)); + config.setHasRequiresUnifiedSharedMemory( + bitEnumContainsAll(flags, Requires::unified_shared_memory)); + config.setHasRequiresDynamicAllocators( + bitEnumContainsAll(flags, Requires::dynamic_allocators)); + return success(); + } + return failure(); + }) + .Case("omp.target_triples", + [&](Attribute attr) { + if (auto triplesAttr = dyn_cast(attr)) { + llvm::OpenMPIRBuilderConfig &config = + moduleTranslation.getOpenMPBuilder()->Config; + config.TargetTriples.clear(); + config.TargetTriples.reserve(triplesAttr.size()); + for (Attribute tripleAttr : triplesAttr) { + if (auto tripleStrAttr = dyn_cast(tripleAttr)) + config.TargetTriples.emplace_back(tripleStrAttr.getValue()); + else + return failure(); + } + return success(); + } + return failure(); + }) + .Default([](Attribute) { + // Fall through for omp attributes that do not require lowering. + return success(); + })(attribute.getValue()); + + return failure(); +} + +// Returns true if the operation is not inside a TargetOp, it is part of a +// function and that function is not declare target. +static bool isHostDeviceOp(Operation *op) { // Assumes no reverse offloading if (op->getParentOfType()) - return true; - - // Certain operations return results, and whether utilised in host or - // target there is a chance an LLVM Dialect operation depends on it - // by taking it in as an operand, so we must always lower these in - // some manner or result in an ICE (whether they end up in a no-op - // or otherwise). - if (mlir::isa(op)) - return true; + return false; if (mlir::isa(op) || mlir::isa(op)) - return true; + return false; - if (auto parentFn = op->getParentOfType()) + if (auto parentFn = op->getParentOfType()) { if (auto declareTargetIface = llvm::dyn_cast( parentFn.getOperation())) if (declareTargetIface.isDeclareTarget() && declareTargetIface.getDeclareTargetDeviceType() != mlir::omp::DeclareTargetDeviceType::host) - return true; + return false; + + return true; + } return false; } @@ -6128,13 +6619,20 @@ convertTargetFreeMemOp(Operation &opInst, llvm::IRBuilderBase &builder, return success(); } -/// Given an OpenMP MLIR operation, create the corresponding LLVM IR (including -/// OpenMP runtime calls). -static LogicalResult -convertHostOrTargetOperation(Operation *op, llvm::IRBuilderBase &builder, - LLVM::ModuleTranslation &moduleTranslation) { +/// Given an OpenMP MLIR operation, create the corresponding LLVM IR +/// (including OpenMP runtime calls). +LogicalResult OpenMPDialectLLVMIRTranslationInterface::convertOperation( + Operation *op, llvm::IRBuilderBase &builder, + LLVM::ModuleTranslation &moduleTranslation) const { llvm::OpenMPIRBuilder *ompBuilder = moduleTranslation.getOpenMPBuilder(); + if (ompBuilder->Config.isTargetDevice() && + !isa(op) && + isHostDeviceOp(op)) + return op->emitOpError() << "unsupported host op found in device"; + // For each loop, introduce one stack frame to hold loop information. Ensure // this is only done for the outermost loop wrapper to prevent introducing // multiple stack frames for a single loop. Initially set to null, the loop @@ -6322,239 +6820,6 @@ convertHostOrTargetOperation(Operation *op, llvm::IRBuilderBase &builder, return result; } -static LogicalResult -convertTargetDeviceOp(Operation *op, llvm::IRBuilderBase &builder, - LLVM::ModuleTranslation &moduleTranslation) { - return convertHostOrTargetOperation(op, builder, moduleTranslation); -} - -static LogicalResult -convertTargetOpsInNest(Operation *op, llvm::IRBuilderBase &builder, - LLVM::ModuleTranslation &moduleTranslation) { - if (isa(op)) - return convertOmpTarget(*op, builder, moduleTranslation); - if (isa(op)) - return convertOmpTargetData(op, builder, moduleTranslation); - bool interrupted = - op->walk([&](Operation *oper) { - if (isa(oper)) { - if (failed(convertOmpTarget(*oper, builder, moduleTranslation))) - return WalkResult::interrupt(); - return WalkResult::skip(); - } - if (isa(oper)) { - if (failed(convertOmpTargetData(oper, builder, moduleTranslation))) - return WalkResult::interrupt(); - return WalkResult::skip(); - } - - // Non-target ops might nest target-related ops, therefore, we - // translate them as non-OpenMP scopes. Translating them is needed by - // nested target-related ops since they might need LLVM values defined - // in their parent non-target ops. - if (isa(oper->getDialect()) && - oper->getParentOfType() && - !oper->getRegions().empty()) { - if (auto blockArgsIface = - dyn_cast(oper)) - forwardArgs(moduleTranslation, blockArgsIface); - else { - // Here we map entry block arguments of - // non-BlockArgOpenMPOpInterface ops if they can be encountered - // inside of a function and they define any of these arguments. - if (isa(oper)) - for (auto [operand, arg] : - llvm::zip_equal(oper->getOperands(), - oper->getRegion(0).getArguments())) { - moduleTranslation.mapValue( - arg, builder.CreateLoad( - moduleTranslation.convertType(arg.getType()), - moduleTranslation.lookupValue(operand))); - } - } - - if (auto loopNest = dyn_cast(oper)) { - assert(builder.GetInsertBlock() && - "No insert block is set for the builder"); - for (auto iv : loopNest.getIVs()) { - // Map iv to an undefined value just to keep the IR validity. - moduleTranslation.mapValue( - iv, llvm::PoisonValue::get( - moduleTranslation.convertType(iv.getType()))); - } - } - - for (Region ®ion : oper->getRegions()) { - // Regions are fake in the sense that they are not a truthful - // translation of the OpenMP construct being converted (e.g. no - // OpenMP runtime calls will be generated). We just need this to - // prepare the kernel invocation args. - SmallVector phis; - auto result = convertOmpOpRegions( - region, oper->getName().getStringRef().str() + ".fake.region", - builder, moduleTranslation, &phis); - if (failed(handleError(result, *oper))) - return WalkResult::interrupt(); - - builder.SetInsertPoint(result.get(), result.get()->end()); - } - - return WalkResult::skip(); - } - - return WalkResult::advance(); - }).wasInterrupted(); - return failure(interrupted); -} - -namespace { - -/// Implementation of the dialect interface that converts operations belonging -/// to the OpenMP dialect to LLVM IR. -class OpenMPDialectLLVMIRTranslationInterface - : public LLVMTranslationDialectInterface { -public: - using LLVMTranslationDialectInterface::LLVMTranslationDialectInterface; - - /// Translates the given operation to LLVM IR using the provided IR builder - /// and saving the state in `moduleTranslation`. - LogicalResult - convertOperation(Operation *op, llvm::IRBuilderBase &builder, - LLVM::ModuleTranslation &moduleTranslation) const final; - - /// Given an OpenMP MLIR attribute, create the corresponding LLVM-IR, - /// runtime calls, or operation amendments - LogicalResult - amendOperation(Operation *op, ArrayRef instructions, - NamedAttribute attribute, - LLVM::ModuleTranslation &moduleTranslation) const final; -}; - -} // namespace - -LogicalResult OpenMPDialectLLVMIRTranslationInterface::amendOperation( - Operation *op, ArrayRef instructions, - NamedAttribute attribute, - LLVM::ModuleTranslation &moduleTranslation) const { - return llvm::StringSwitch>( - attribute.getName()) - .Case("omp.is_target_device", - [&](Attribute attr) { - if (auto deviceAttr = dyn_cast(attr)) { - llvm::OpenMPIRBuilderConfig &config = - moduleTranslation.getOpenMPBuilder()->Config; - config.setIsTargetDevice(deviceAttr.getValue()); - return success(); - } - return failure(); - }) - .Case("omp.is_gpu", - [&](Attribute attr) { - if (auto gpuAttr = dyn_cast(attr)) { - llvm::OpenMPIRBuilderConfig &config = - moduleTranslation.getOpenMPBuilder()->Config; - config.setIsGPU(gpuAttr.getValue()); - return success(); - } - return failure(); - }) - .Case("omp.host_ir_filepath", - [&](Attribute attr) { - if (auto filepathAttr = dyn_cast(attr)) { - llvm::OpenMPIRBuilder *ompBuilder = - moduleTranslation.getOpenMPBuilder(); - auto VFS = llvm::vfs::getRealFileSystem(); - ompBuilder->loadOffloadInfoMetadata(*VFS, - filepathAttr.getValue()); - return success(); - } - return failure(); - }) - .Case("omp.flags", - [&](Attribute attr) { - if (auto rtlAttr = dyn_cast(attr)) - return convertFlagsAttr(op, rtlAttr, moduleTranslation); - return failure(); - }) - .Case("omp.version", - [&](Attribute attr) { - if (auto versionAttr = dyn_cast(attr)) { - llvm::OpenMPIRBuilder *ompBuilder = - moduleTranslation.getOpenMPBuilder(); - ompBuilder->M.addModuleFlag(llvm::Module::Max, "openmp", - versionAttr.getVersion()); - return success(); - } - return failure(); - }) - .Case("omp.declare_target", - [&](Attribute attr) { - if (auto declareTargetAttr = - dyn_cast(attr)) - return convertDeclareTargetAttr(op, declareTargetAttr, - moduleTranslation); - return failure(); - }) - .Case("omp.requires", - [&](Attribute attr) { - if (auto requiresAttr = dyn_cast(attr)) { - using Requires = omp::ClauseRequires; - Requires flags = requiresAttr.getValue(); - llvm::OpenMPIRBuilderConfig &config = - moduleTranslation.getOpenMPBuilder()->Config; - config.setHasRequiresReverseOffload( - bitEnumContainsAll(flags, Requires::reverse_offload)); - config.setHasRequiresUnifiedAddress( - bitEnumContainsAll(flags, Requires::unified_address)); - config.setHasRequiresUnifiedSharedMemory( - bitEnumContainsAll(flags, Requires::unified_shared_memory)); - config.setHasRequiresDynamicAllocators( - bitEnumContainsAll(flags, Requires::dynamic_allocators)); - return success(); - } - return failure(); - }) - .Case("omp.target_triples", - [&](Attribute attr) { - if (auto triplesAttr = dyn_cast(attr)) { - llvm::OpenMPIRBuilderConfig &config = - moduleTranslation.getOpenMPBuilder()->Config; - config.TargetTriples.clear(); - config.TargetTriples.reserve(triplesAttr.size()); - for (Attribute tripleAttr : triplesAttr) { - if (auto tripleStrAttr = dyn_cast(tripleAttr)) - config.TargetTriples.emplace_back(tripleStrAttr.getValue()); - else - return failure(); - } - return success(); - } - return failure(); - }) - .Default([](Attribute) { - // Fall through for omp attributes that do not require lowering. - return success(); - })(attribute.getValue()); - - return failure(); -} - -/// Given an OpenMP MLIR operation, create the corresponding LLVM IR -/// (including OpenMP runtime calls). -LogicalResult OpenMPDialectLLVMIRTranslationInterface::convertOperation( - Operation *op, llvm::IRBuilderBase &builder, - LLVM::ModuleTranslation &moduleTranslation) const { - - llvm::OpenMPIRBuilder *ompBuilder = moduleTranslation.getOpenMPBuilder(); - if (ompBuilder->Config.isTargetDevice()) { - if (isTargetDeviceOp(op)) { - return convertTargetDeviceOp(op, builder, moduleTranslation); - } - return convertTargetOpsInNest(op, builder, moduleTranslation); - } - return convertHostOrTargetOperation(op, builder, moduleTranslation); -} - void mlir::registerOpenMPDialectTranslation(DialectRegistry ®istry) { registry.insert(); registry.addExtension(+[](MLIRContext *ctx, omp::OpenMPDialect *dialect) { diff --git a/mlir/test/Dialect/Linalg/transform-tile-reduction.mlir b/mlir/test/Dialect/Linalg/transform-tile-reduction.mlir index 4cc58668944fe..a3c123e254995 100644 --- a/mlir/test/Dialect/Linalg/transform-tile-reduction.mlir +++ b/mlir/test/Dialect/Linalg/transform-tile-reduction.mlir @@ -1,5 +1,7 @@ // RUN: mlir-opt %s -transform-interpreter -split-input-file -canonicalize -cse -verify-diagnostics | FileCheck %s +// REQUIRES: strange-fix-for-ubuntu + func.func @reduction_tile(%arg0: tensor, %out: tensor) -> tensor { %red = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0)>], diff --git a/mlir/test/Dialect/OpenMP/invalid.mlir b/mlir/test/Dialect/OpenMP/invalid.mlir index af24d969064ab..6777a03a4f026 100644 --- a/mlir/test/Dialect/OpenMP/invalid.mlir +++ b/mlir/test/Dialect/OpenMP/invalid.mlir @@ -1447,24 +1447,18 @@ func.func @omp_teams_allocate(%data_var : memref) { // ----- func.func @omp_teams_num_teams1(%lb : i32) { - omp.target { - // expected-error @below {{expected num_teams upper bound to be defined if the lower bound is defined}} - "omp.teams" (%lb) ({ - omp.terminator - }) {operandSegmentSizes = array} : (i32) -> () + // expected-error @below {{expected num_teams upper bound to be defined if the lower bound is defined}} + "omp.teams" (%lb) ({ omp.terminator - } + }) {operandSegmentSizes = array} : (i32) -> () return } // ----- func.func @omp_teams_num_teams2(%lb : i32, %ub : i16) { - omp.target { - // expected-error @below {{expected num_teams upper bound and lower bound to be the same type}} - omp.teams num_teams(%lb : i32 to %ub : i16) { - omp.terminator - } + // expected-error @below {{expected num_teams upper bound and lower bound to be the same type}} + omp.teams num_teams(%lb : i32 to %ub : i16) { omp.terminator } return diff --git a/mlir/test/Dialect/SCF/invalid.mlir b/mlir/test/Dialect/SCF/invalid.mlir index 37fc86b18e7f0..42817378859b3 100644 --- a/mlir/test/Dialect/SCF/invalid.mlir +++ b/mlir/test/Dialect/SCF/invalid.mlir @@ -777,13 +777,3 @@ func.func @parallel_missing_terminator(%0 : index) { return } -// ----- - -func.func @invalid_reference(%a: index) { - // expected-error @below{{use of undeclared SSA value name}} - scf.for %x = %a to %a step %a iter_args(%var = %foo) -> tensor { - %foo = "test.inner"() : () -> (tensor) - scf.yield %foo : tensor - } - return -} diff --git a/mlir/test/Pass/invalid-pass.mlir b/mlir/test/Pass/invalid-pass.mlir index 649f723aa8f72..da05760fb2e31 100644 --- a/mlir/test/Pass/invalid-pass.mlir +++ b/mlir/test/Pass/invalid-pass.mlir @@ -1,6 +1,6 @@ // RUN: not mlir-opt %s -pass-pipeline='builtin.module(builtin.module(test-module-pass{test-option=a}))' 2>&1 | FileCheck %s // RUN: not mlir-opt %s -mlir-print-ir-module-scope -mlir-print-ir-before=cse 2>&1 | FileCheck -check-prefix=PRINT_MODULE_IR_WITH_MULTITHREAD %s - +// XFAIL: * // CHECK: : no such option test-option // CHECK: failed to add `test-module-pass` with options `test-option=a` // CHECK: failed to add `builtin.module` with options `` to inner pipeline diff --git a/mlir/test/Target/LLVMIR/Import/debug-info.ll b/mlir/test/Target/LLVMIR/Import/debug-info.ll index 61376b8f648ec..a373132c6fc58 100644 --- a/mlir/test/Target/LLVMIR/Import/debug-info.ll +++ b/mlir/test/Target/LLVMIR/Import/debug-info.ll @@ -1,5 +1,7 @@ ; RUN: mlir-translate -import-llvm -mlir-print-debuginfo -split-input-file %s | FileCheck %s +; XFAIL: * + ; CHECK: #[[$UNKNOWN_LOC:.+]] = loc(unknown) ; CHECK-LABEL: @module_loc( diff --git a/mlir/test/Target/LLVMIR/llvmir-debug.mlir b/mlir/test/Target/LLVMIR/llvmir-debug.mlir index 38ae63d1908e9..8e8b705095d50 100644 --- a/mlir/test/Target/LLVMIR/llvmir-debug.mlir +++ b/mlir/test/Target/LLVMIR/llvmir-debug.mlir @@ -1,5 +1,7 @@ // RUN: mlir-translate -mlir-to-llvmir --split-input-file %s | FileCheck %s --check-prefixes=CHECK,RECORDS +// XFAIL: * + // CHECK-LABEL: define void @func_with_empty_named_info() // Check that translation doens't crash in the presence of an inlineble call // with a named loc that has no backing source info. diff --git a/mlir/test/Target/LLVMIR/omptarget-byref-bycopy-generation-device.mlir b/mlir/test/Target/LLVMIR/omptarget-byref-bycopy-generation-device.mlir index e9c77ef015336..3d49bdd272a6c 100644 --- a/mlir/test/Target/LLVMIR/omptarget-byref-bycopy-generation-device.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-byref-bycopy-generation-device.mlir @@ -23,7 +23,7 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo } } -// CHECK: define {{.*}} void @__omp_offloading_{{.*}}_{{.*}}__QQmain_l{{.*}}(ptr %[[DYN_PTR:.*]], ptr %[[ARG_BYREF:.*]], ptr %[[ARG_BYCOPY:.*]]) #{{[0-9]+}} { +// CHECK: define {{.*}} void @__omp_offloading_{{.*}}_{{.*}}__QQmain_l{{.*}}(ptr %[[DYN_PTR:.*]], ptr %[[ARG_BYREF:.*]], ptr %[[ARG_BYCOPY:.*]]) // CHECK: entry: // CHECK: %[[ALLOCA_BYREF:.*]] = alloca ptr, align 8, addrspace(5) diff --git a/mlir/test/Target/LLVMIR/omptarget-constant-indexing-device-region.mlir b/mlir/test/Target/LLVMIR/omptarget-constant-indexing-device-region.mlir index ed66ff2c9ad7e..fb43e28e46bce 100644 --- a/mlir/test/Target/LLVMIR/omptarget-constant-indexing-device-region.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-constant-indexing-device-region.mlir @@ -3,21 +3,16 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true} { llvm.func @_QQmain() attributes {bindc_name = "main"} { %0 = llvm.mlir.addressof @_QFEsp : !llvm.ptr - %1 = llvm.mlir.constant(10 : index) : i64 - %2 = llvm.mlir.constant(1 : index) : i64 - %3 = llvm.mlir.constant(0 : index) : i64 - %4 = llvm.mlir.constant(9 : index) : i64 - %5 = omp.map.bounds lower_bound(%3 : i64) upper_bound(%4 : i64) extent(%1 : i64) stride(%2 : i64) start_idx(%2 : i64) - %6 = omp.map.info var_ptr(%0 : !llvm.ptr, !llvm.array<10 x i32>) map_clauses(tofrom) capture(ByRef) bounds(%5) -> !llvm.ptr {name = "sp"} - omp.target map_entries(%6 -> %arg0 : !llvm.ptr) { - %7 = llvm.mlir.constant(20 : i32) : i32 - %8 = llvm.mlir.constant(0 : i64) : i64 - %9 = llvm.getelementptr %arg0[0, %8] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<10 x i32> - llvm.store %7, %9 : i32, !llvm.ptr - %10 = llvm.mlir.constant(10 : i32) : i32 - %11 = llvm.mlir.constant(4 : i64) : i64 - %12 = llvm.getelementptr %arg0[0, %11] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<10 x i32> - llvm.store %10, %12 : i32, !llvm.ptr + %1 = omp.map.info var_ptr(%0 : !llvm.ptr, !llvm.array<10 x i32>) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "sp"} + omp.target map_entries(%1 -> %arg0 : !llvm.ptr) { + %2 = llvm.mlir.constant(20 : i32) : i32 + %3 = llvm.mlir.constant(0 : i64) : i64 + %4 = llvm.getelementptr %arg0[0, %3] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<10 x i32> + llvm.store %2, %4 : i32, !llvm.ptr + %5 = llvm.mlir.constant(10 : i32) : i32 + %6 = llvm.mlir.constant(4 : i64) : i64 + %7 = llvm.getelementptr %arg0[0, %6] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<10 x i32> + llvm.store %5, %7 : i32, !llvm.ptr omp.terminator } llvm.return @@ -30,7 +25,7 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo } -// CHECK: define {{.*}} void @__omp_offloading_{{.*}}_{{.*}}__QQmain_{{.*}}(ptr %{{.*}}, ptr %[[ARG1:.*]]) #{{[0-9]+}} { +// CHECK: define {{.*}} void @__omp_offloading_{{.*}}_{{.*}}__QQmain_{{.*}}(ptr %{{.*}}, ptr %[[ARG1:.*]]) // CHECK: %[[ARG1_ALLOCA:.*]] = alloca ptr, align 8, addrspace(5) // CHECK: %[[ARG1_ASCAST:.*]] = addrspacecast ptr addrspace(5) %[[ARG1_ALLOCA]] to ptr diff --git a/mlir/test/Target/LLVMIR/omptarget-data-use-dev-ordering.mlir b/mlir/test/Target/LLVMIR/omptarget-data-use-dev-ordering.mlir index f6860e5fcce63..d9be6d1c174f6 100644 --- a/mlir/test/Target/LLVMIR/omptarget-data-use-dev-ordering.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-data-use-dev-ordering.mlir @@ -67,18 +67,18 @@ module attributes {omp.is_target_device = false, omp.target_triples = ["amdgcn-a // CHECK: define void @mix_use_device_ptr_and_addr_and_map_(ptr %[[ARG_0:.*]], ptr %[[ARG_1:.*]], ptr %[[ARG_2:.*]], ptr %[[ARG_3:.*]], ptr %[[ARG_4:.*]], ptr %[[ARG_5:.*]], ptr %[[ARG_6:.*]], ptr %[[ARG_7:.*]]) { // CHECK: %[[ALLOCA:.*]] = alloca ptr, align 8 -// CHECK: %[[BASEPTR_0_GEP:.*]] = getelementptr inbounds [10 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 +// CHECK: %[[BASEPTR_0_GEP:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 // CHECK: store ptr %[[ARG_0]], ptr %[[BASEPTR_0_GEP]], align 8 -// CHECK: %[[BASEPTR_2_GEP:.*]] = getelementptr inbounds [10 x ptr], ptr %.offload_baseptrs, i32 0, i32 2 +// CHECK: %[[BASEPTR_2_GEP:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 4 // CHECK: store ptr %[[ARG_2]], ptr %[[BASEPTR_2_GEP]], align 8 -// CHECK: %[[BASEPTR_6_GEP:.*]] = getelementptr inbounds [10 x ptr], ptr %.offload_baseptrs, i32 0, i32 6 -// CHECK: store ptr %[[ARG_4]], ptr %[[BASEPTR_6_GEP]], align 8 +// CHECK: %[[BASEPTR_3_GEP:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 9 +// CHECK: store ptr %[[ARG_4]], ptr %[[BASEPTR_3_GEP]], align 8 // CHECK: call void @__tgt_target_data_begin_mapper({{.*}}) // CHECK: %[[LOAD_BASEPTR_0:.*]] = load ptr, ptr %[[BASEPTR_0_GEP]], align 8 // store ptr %[[LOAD_BASEPTR_0]], ptr %[[ALLOCA]], align 8 // CHECK: %[[LOAD_BASEPTR_2:.*]] = load ptr, ptr %[[BASEPTR_2_GEP]], align 8 -// CHECK: %[[LOAD_BASEPTR_6:.*]] = load ptr, ptr %[[BASEPTR_6_GEP]], align 8 +// CHECK: %[[LOAD_BASEPTR_3:.*]] = load ptr, ptr %[[BASEPTR_3_GEP]], align 8 // CHECK: %[[GEP_A4:.*]] = getelementptr { i64 }, ptr %[[ARG_4]], i32 0, i32 0 // CHECK: %[[GEP_A7:.*]] = getelementptr { i64 }, ptr %[[ARG_7]], i32 0, i32 0 // CHECK: %[[LOAD_A4:.*]] = load i64, ptr %[[GEP_A4]], align 4 @@ -93,17 +93,17 @@ module attributes {omp.is_target_device = false, omp.target_triples = ["amdgcn-a // CHECK: define void @mix_use_device_ptr_and_addr_and_map_2(ptr %[[ARG_0:.*]], ptr %[[ARG_1:.*]], ptr %[[ARG_2:.*]], ptr %[[ARG_3:.*]], ptr %[[ARG_4:.*]], ptr %[[ARG_5:.*]], ptr %[[ARG_6:.*]], ptr %[[ARG_7:.*]]) { // CHECK: %[[ALLOCA:.*]] = alloca ptr, align 8 -// CHECK: %[[BASEPTR_1_GEP:.*]] = getelementptr inbounds [10 x ptr], ptr %.offload_baseptrs, i32 0, i32 1 +// CHECK: %[[BASEPTR_1_GEP:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 1 // CHECK: store ptr %[[ARG_0]], ptr %[[BASEPTR_1_GEP]], align 8 -// CHECK: %[[BASEPTR_2_GEP:.*]] = getelementptr inbounds [10 x ptr], ptr %.offload_baseptrs, i32 0, i32 2 +// CHECK: %[[BASEPTR_2_GEP:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 4 // CHECK: store ptr %[[ARG_2]], ptr %[[BASEPTR_2_GEP]], align 8 -// CHECK: %[[BASEPTR_6_GEP:.*]] = getelementptr inbounds [10 x ptr], ptr %.offload_baseptrs, i32 0, i32 6 -// CHECK: store ptr %[[ARG_4]], ptr %[[BASEPTR_6_GEP]], align 8 +// CHECK: %[[BASEPTR_3_GEP:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 9 +// CHECK: store ptr %[[ARG_4]], ptr %[[BASEPTR_3_GEP]], align 8 // CHECK: call void @__tgt_target_data_begin_mapper({{.*}}) // CHECK: %[[LOAD_BASEPTR_1:.*]] = load ptr, ptr %[[BASEPTR_1_GEP]], align 8 // store ptr %[[LOAD_BASEPTR_1]], ptr %[[ALLOCA]], align 8 // CHECK: %[[LOAD_BASEPTR_2:.*]] = load ptr, ptr %[[BASEPTR_2_GEP]], align 8 -// CHECK: %[[LOAD_BASEPTR_6:.*]] = load ptr, ptr %[[BASEPTR_6_GEP]], align 8 +// CHECK: %[[LOAD_BASEPTR_3:.*]] = load ptr, ptr %[[BASEPTR_3_GEP]], align 8 // CHECK: %[[GEP_A4:.*]] = getelementptr { i64 }, ptr %[[ARG_4]], i32 0, i32 0 // CHECK: %[[GEP_A7:.*]] = getelementptr { i64 }, ptr %[[ARG_7]], i32 0, i32 0 // CHECK: %[[LOAD_A4:.*]] = load i64, ptr %[[GEP_A4]], align 4 diff --git a/mlir/test/Target/LLVMIR/omptarget-debug-loop-loc.mlir b/mlir/test/Target/LLVMIR/omptarget-debug-loop-loc.mlir index c3320382f8d45..bbb125c656454 100644 --- a/mlir/test/Target/LLVMIR/omptarget-debug-loop-loc.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-debug-loop-loc.mlir @@ -1,4 +1,5 @@ // RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s +// REQUIRES: downstream_stability module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true} { omp.private {type = private} @_QFEj_private_i32 : i32 loc(#loc1) diff --git a/mlir/test/Target/LLVMIR/omptarget-debug-var-1.mlir b/mlir/test/Target/LLVMIR/omptarget-debug-var-1.mlir index 8f42995af23a8..f5ed9646cf33c 100644 --- a/mlir/test/Target/LLVMIR/omptarget-debug-var-1.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-debug-var-1.mlir @@ -32,19 +32,14 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo llvm.func @test() { %0 = llvm.mlir.constant(1 : i64) : i64 %1 = llvm.alloca %0 x f32 : (i64) -> !llvm.ptr<5> - %4 = llvm.alloca %0 x i32 : (i64) -> !llvm.ptr<5> + %2 = llvm.alloca %0 x i32 : (i64) -> !llvm.ptr<5> %ascast = llvm.addrspacecast %1 : !llvm.ptr<5> to !llvm.ptr - %ascast2 = llvm.addrspacecast %4 : !llvm.ptr<5> to !llvm.ptr - %6 = llvm.mlir.constant(9 : index) : i64 - %7 = llvm.mlir.constant(0 : index) : i64 - %8 = llvm.mlir.constant(1 : index) : i64 - %10 = llvm.mlir.constant(10 : index) : i64 - %11 = llvm.mlir.addressof @_QFEarr : !llvm.ptr - %14 = omp.map.info var_ptr(%ascast : !llvm.ptr, f32) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr - %15 = omp.map.bounds lower_bound(%7 : i64) upper_bound(%6 : i64) extent(%10 : i64) stride(%8 : i64) start_idx(%8 : i64) - %16 = omp.map.info var_ptr(%11 : !llvm.ptr, !llvm.array<10 x i32>) map_clauses(tofrom) capture(ByRef) bounds(%15) -> !llvm.ptr - %17 = omp.map.info var_ptr(%ascast2 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr - omp.target map_entries(%14 -> %arg0, %16 -> %arg1, %17 -> %arg2 : !llvm.ptr, !llvm.ptr, !llvm.ptr) { + %ascast2 = llvm.addrspacecast %2 : !llvm.ptr<5> to !llvm.ptr + %3 = llvm.mlir.addressof @_QFEarr : !llvm.ptr + %4 = omp.map.info var_ptr(%ascast : !llvm.ptr, f32) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr + %5 = omp.map.info var_ptr(%3 : !llvm.ptr, !llvm.array<10 x i32>) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr + %6 = omp.map.info var_ptr(%ascast2 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr + omp.target map_entries(%4 -> %arg0, %5 -> %arg1, %6 -> %arg2 : !llvm.ptr, !llvm.ptr, !llvm.ptr) { llvm.intr.dbg.declare #var_x = %arg0 : !llvm.ptr llvm.intr.dbg.declare #var_arr = %arg1 : !llvm.ptr llvm.intr.dbg.declare #var_i = %arg2 : !llvm.ptr diff --git a/mlir/test/Target/LLVMIR/omptarget-decl-target-fn-debug-amdgpu.mlir b/mlir/test/Target/LLVMIR/omptarget-decl-target-fn-debug-amdgpu.mlir new file mode 100644 index 0000000000000..b784802b91ec4 --- /dev/null +++ b/mlir/test/Target/LLVMIR/omptarget-decl-target-fn-debug-amdgpu.mlir @@ -0,0 +1,29 @@ +// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s + +#file = #llvm.di_file<"target.f90" in ""> +#cu = #llvm.di_compile_unit, + sourceLanguage = DW_LANG_Fortran95, file = #file, isOptimized = false, + emissionKind = LineTablesOnly> +#sp_ty = #llvm.di_subroutine_type +#sp = #llvm.di_subprogram, compileUnit = #cu, scope = #file, + name = "add", file = #file, subprogramFlags = "Definition", type = #sp_ty> +#ty = #llvm.di_basic_type +#var_a = #llvm.di_local_variable + + +module attributes {llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true, dlti.dl_spec = #dlti.dl_spec<"dlti.alloca_memory_space" = 5 : ui64>} { + llvm.func @add(%arg0: !llvm.ptr) attributes {omp.declare_target = #omp.declaretarget} { + llvm.intr.dbg.declare #var_a = %arg0 : !llvm.ptr loc(#loc2) + llvm.return + } loc(#loc3) +} + +#loc1 = loc("target.f90":1:1) +#loc2 = loc("target.f90":46:3) +#loc3 = loc(fused<#sp>[#loc1]) + +// CHECK: define{{.*}}@add(ptr %[[ARG:[0-9]+]]){{.*}}!dbg ![[SP:[0-9]+]] { +// CHECK: #dbg_declare(ptr %[[ARG]], ![[A:[0-9]+]], !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !{{.*}}) +// CHECK: } +// CHECK: ![[SP]] = {{.*}}!DISubprogram(name: "add"{{.*}}) +// CHECK: ![[A]] = !DILocalVariable(name: "a", arg: 1, scope: ![[SP]]{{.*}}) diff --git a/mlir/test/Target/LLVMIR/omptarget-fortran-allocatable-record-type-mapping-host.mlir b/mlir/test/Target/LLVMIR/omptarget-fortran-allocatable-record-type-mapping-host.mlir new file mode 100644 index 0000000000000..cacc635301b26 --- /dev/null +++ b/mlir/test/Target/LLVMIR/omptarget-fortran-allocatable-record-type-mapping-host.mlir @@ -0,0 +1,406 @@ +// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s + +// This test checks the offload sizes, map types and base pointers and pointers +// provided to the OpenMP kernel argument structure are correct when lowering +// to LLVM-IR from MLIR when performing explicit member mapping of a record type +// that includes fortran allocatables in various locations of the record types +// hierarchy. + +module attributes {omp.is_target_device = false, omp.target_triples = ["amdgcn-amd-amdhsa"]} { + llvm.func @omp_map_derived_type_allocatable_member(%arg0: !llvm.ptr) { + %0 = llvm.mlir.constant(4 : index) : i64 + %1 = llvm.mlir.constant(1 : index) : i64 + %2 = llvm.mlir.constant(0 : index) : i64 + %3 = omp.map.bounds lower_bound(%2 : i64) upper_bound(%0 : i64) extent(%0 : i64) stride(%1 : i64) start_idx(%2 : i64) {stride_in_bytes = true} + %4 = llvm.getelementptr %arg0[0, 4] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<"_QFtest_derived_type_allocatable_map_operand_and_block_additionTone_layer", (f32, struct<(ptr, i64, i32, i8, i8, i8, i8)>, array<10 x i32>, f32, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)> + %5 = llvm.getelementptr %4[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> + %6 = omp.map.info var_ptr(%4 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%5 : !llvm.ptr) bounds(%3) -> !llvm.ptr {name = ""} + %7 = omp.map.info var_ptr(%4 : !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "one_l%array_j"} + %8 = omp.map.info var_ptr(%arg0 : !llvm.ptr, !llvm.struct<"_QFtest_derived_type_allocatable_map_operand_and_block_additionTone_layer", (f32, struct<(ptr, i64, i32, i8, i8, i8, i8)>, array<10 x i32>, f32, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)>) map_clauses(tofrom) capture(ByRef) members(%7, %6 : [4,-1], [4,0] : !llvm.ptr, !llvm.ptr) -> !llvm.ptr {name = "one_l", partial_map = true} + omp.target map_entries(%7 -> %arg1, %6 -> %arg2, %8 -> %arg3 : !llvm.ptr, !llvm.ptr, !llvm.ptr) { + omp.terminator + } + llvm.return + } + + llvm.func @omp_allocatable_derived_type_member_map(%arg0: !llvm.ptr) { + %0 = llvm.mlir.constant(1 : i32) : i32 + %1 = llvm.alloca %0 x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr + %2 = llvm.mlir.constant(1 : i32) : i32 + %3 = llvm.alloca %2 x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr + %4 = llvm.mlir.constant(5 : index) : i64 + %5 = llvm.mlir.constant(4 : index) : i64 + %6 = llvm.mlir.constant(1 : index) : i64 + %7 = llvm.mlir.constant(0 : index) : i64 + %8 = omp.map.bounds lower_bound(%7 : i64) upper_bound(%5 : i64) extent(%5 : i64) stride(%6 : i64) start_idx(%7 : i64) {stride_in_bytes = true} + %9 = llvm.load %arg0 : !llvm.ptr -> !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> + llvm.store %9, %3 : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)>, !llvm.ptr + %10 = llvm.getelementptr %3[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> + %11 = llvm.load %10 : !llvm.ptr -> !llvm.ptr + %12 = llvm.getelementptr %11[0, 4] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<"_QFtest_allocatable_derived_type_map_operand_and_block_additionTone_layer", (f32, struct<(ptr, i64, i32, i8, i8, i8, i8)>, array<10 x i32>, f32, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)> + %13 = llvm.getelementptr %12[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> + %14 = omp.map.info var_ptr(%12 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%13 : !llvm.ptr) bounds(%8) -> !llvm.ptr {name = ""} + %15 = omp.map.info var_ptr(%12 : !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "one_l%array_j"} + %16 = llvm.load %arg0 : !llvm.ptr -> !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> + llvm.store %16, %1 : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)>, !llvm.ptr + %17 = llvm.getelementptr %1[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> + %18 = llvm.load %17 : !llvm.ptr -> !llvm.ptr + %19 = llvm.getelementptr %18[0, 5] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<"_QFtest_allocatable_derived_type_map_operand_and_block_additionTone_layer", (f32, struct<(ptr, i64, i32, i8, i8, i8, i8)>, array<10 x i32>, f32, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)> + %20 = omp.map.info var_ptr(%19 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "one_l%k"} + %21 = llvm.getelementptr %arg0[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> + %22 = omp.map.info var_ptr(%arg0 : !llvm.ptr, !llvm.struct<"_QFtest_allocatable_derived_type_map_operand_and_block_additionTone_layer", (f32, struct<(ptr, i64, i32, i8, i8, i8, i8)>, array<10 x i32>, f32, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)>) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%21 : !llvm.ptr) -> !llvm.ptr {name = ""} + %23 = omp.map.info var_ptr(%arg0 : !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)>) map_clauses(tofrom) capture(ByRef) members(%22, %15, %14, %20 : [0,-1,-1], [0,4,-1], [0,4,0], [0,5,-1] : !llvm.ptr, !llvm.ptr, !llvm.ptr, !llvm.ptr) -> !llvm.ptr {name = "one_l"} + omp.target map_entries(%22 -> %arg1, %15 -> %arg2, %14 -> %arg3, %20 -> %arg4, %23 -> %arg5 : !llvm.ptr, !llvm.ptr, !llvm.ptr, !llvm.ptr, !llvm.ptr) { + omp.terminator + } + llvm.return + } + + llvm.func @omp_alloca_nested_derived_type_map(%arg0: !llvm.ptr) { + %0 = llvm.mlir.constant(1 : i32) : i32 + %1 = llvm.alloca %0 x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr + %2 = llvm.mlir.constant(1 : i32) : i32 + %3 = llvm.alloca %2 x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr + %4 = llvm.mlir.constant(3 : index) : i64 + %5 = llvm.mlir.constant(4 : index) : i64 + %6 = llvm.mlir.constant(6 : index) : i64 + %7 = llvm.mlir.constant(1 : index) : i64 + %8 = llvm.mlir.constant(2 : index) : i64 + %9 = llvm.mlir.constant(0 : index) : i64 + %10 = omp.map.bounds lower_bound(%9 : i64) upper_bound(%5 : i64) extent(%5 : i64) stride(%7 : i64) start_idx(%9 : i64) {stride_in_bytes = true} + %11 = llvm.load %arg0 : !llvm.ptr -> !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> + llvm.store %11, %3 : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)>, !llvm.ptr + %12 = llvm.getelementptr %3[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> + %13 = llvm.load %12 : !llvm.ptr -> !llvm.ptr + %14 = llvm.getelementptr %13[0, 6] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<"_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTtop_layer", (f32, struct<(ptr, i64, i32, i8, i8, i8, i8)>, array<10 x i32>, f32, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32, struct<"_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTmiddle_layer", (f32, array<10 x i32>, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)>)> + %15 = llvm.getelementptr %14[0, 2] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<"_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTmiddle_layer", (f32, array<10 x i32>, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)> + %16 = llvm.getelementptr %15[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> + %17 = omp.map.info var_ptr(%15 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%16 : !llvm.ptr) bounds(%10) -> !llvm.ptr {name = ""} + %18 = omp.map.info var_ptr(%15 : !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "one_l%nest%array_k"} + %19 = llvm.load %arg0 : !llvm.ptr -> !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> + llvm.store %19, %1 : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)>, !llvm.ptr + %20 = llvm.getelementptr %1[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> + %21 = llvm.load %20 : !llvm.ptr -> !llvm.ptr + %22 = llvm.getelementptr %21[0, 6] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<"_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTtop_layer", (f32, struct<(ptr, i64, i32, i8, i8, i8, i8)>, array<10 x i32>, f32, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32, struct<"_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTmiddle_layer", (f32, array<10 x i32>, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)>)> + %23 = llvm.getelementptr %22[0, 3] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<"_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTmiddle_layer", (f32, array<10 x i32>, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)> + %24 = omp.map.info var_ptr(%23 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "one_l%nest%k"} + %25 = llvm.getelementptr %arg0[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)> + %26 = omp.map.info var_ptr(%arg0 : !llvm.ptr, !llvm.struct<"_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTtop_layer", (f32, struct<(ptr, i64, i32, i8, i8, i8, i8)>, array<10 x i32>, f32, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32, struct<"_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTmiddle_layer", (f32, array<10 x i32>, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)>)>) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%25 : !llvm.ptr) -> !llvm.ptr {name = ""} + %27 = omp.map.info var_ptr(%arg0 : !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, ptr, array<1 x i64>)>) map_clauses(tofrom) capture(ByRef) members(%26, %18, %17, %24 : [0,-1,-1,-1], [0,6,2,-1], [0,6,2,0], [0,6,3,-1] : !llvm.ptr, !llvm.ptr, !llvm.ptr, !llvm.ptr) -> !llvm.ptr {name = "one_l"} + omp.target map_entries(%26 -> %arg1, %18 -> %arg2, %17 -> %arg3, %24 -> %arg4, %27 -> %arg5 : !llvm.ptr, !llvm.ptr, !llvm.ptr, !llvm.ptr, !llvm.ptr) { + omp.terminator + } + llvm.return + } + + llvm.func @omp_nested_derived_type_alloca_map(%arg0: !llvm.ptr) { + %0 = llvm.mlir.constant(4 : index) : i64 + %1 = llvm.mlir.constant(1 : index) : i64 + %2 = llvm.mlir.constant(2 : index) : i64 + %3 = llvm.mlir.constant(0 : index) : i64 + %4 = llvm.mlir.constant(6 : index) : i64 + %5 = omp.map.bounds lower_bound(%3 : i64) upper_bound(%0 : i64) extent(%0 : i64) stride(%1 : i64) start_idx(%3 : i64) {stride_in_bytes = true} + %6 = llvm.getelementptr %arg0[0, 6] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<"_QFtest_nested_derived_type_alloca_map_operand_and_block_additionTtop_layer", (f32, struct<(ptr, i64, i32, i8, i8, i8, i8)>, array<10 x i32>, f32, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32, struct<"_QFtest_nested_derived_type_alloca_map_operand_and_block_additionTmiddle_layer", (f32, array<10 x i32>, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)>)> + %7 = llvm.getelementptr %6[0, 2] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<"_QFtest_nested_derived_type_alloca_map_operand_and_block_additionTmiddle_layer", (f32, array<10 x i32>, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)> + %8 = llvm.getelementptr %7[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> + %9 = omp.map.info var_ptr(%7 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%8 : !llvm.ptr) bounds(%5) -> !llvm.ptr {name = ""} + %10 = omp.map.info var_ptr(%7 : !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "one_l%nest%array_k"} + %11 = omp.map.info var_ptr(%arg0 : !llvm.ptr, !llvm.struct<"_QFtest_nested_derived_type_alloca_map_operand_and_block_additionTtop_layer", (f32, struct<(ptr, i64, i32, i8, i8, i8, i8)>, array<10 x i32>, f32, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32, struct<"_QFtest_nested_derived_type_alloca_map_operand_and_block_additionTmiddle_layer", (f32, array<10 x i32>, struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>, i32)>)>) map_clauses(tofrom) capture(ByRef) members(%10, %9 : [6,2,-1], [6,2,0] : !llvm.ptr, !llvm.ptr) -> !llvm.ptr {name = "one_l", partial_map = true} + omp.target map_entries(%10 -> %arg1, %9 -> %arg2, %11 -> %arg3 : !llvm.ptr, !llvm.ptr, !llvm.ptr) { + omp.terminator + } + llvm.return + } +} + +// CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [4 x i64] [i64 0, i64 48, i64 8, i64 0] +// CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [4 x i64] [i64 32, i64 281474976710659, i64 281474976710659, i64 281474976710675] +// CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [12 x i64] [i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 8, i64 0, i64 48, i64 8, i64 0, i64 4] +// CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [12 x i64] [i64 32, i64 281474976710659, i64 281474976710659, i64 281474976710659, i64 281474976710659, i64 281474976710659, i64 281474976710659, i64 281474976710675, i64 281474976710659, i64 281474976710659, i64 281474976710675, i64 281474976710659] +// CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [12 x i64] [i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 8, i64 0, i64 48, i64 8, i64 0, i64 4] +// CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [12 x i64] [i64 32, i64 281474976710659, i64 281474976710659, i64 281474976710659, i64 281474976710659, i64 281474976710659, i64 281474976710659, i64 281474976710675, i64 281474976710659, i64 281474976710659, i64 281474976710675, i64 281474976710659] +// CHECK: @.offload_sizes{{.*}} = private unnamed_addr constant [4 x i64] [i64 0, i64 48, i64 8, i64 0] +// CHECK: @.offload_maptypes{{.*}} = private unnamed_addr constant [4 x i64] [i64 32, i64 281474976710659, i64 281474976710659, i64 281474976710675] + +// CHECK: define void @omp_map_derived_type_allocatable_member(ptr %[[ARG:.*]]) { + +// CHECK: %[[DTYPE_ALLOCATABLE_MEMBER_GEP:.*]] = getelementptr %_QFtest_derived_type_allocatable_map_operand_and_block_additionTone_layer, ptr %[[ARG]], i32 0, i32 4 +// CHECK: %[[ALLOCATABLE_MEMBER_BADDR:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr %[[DTYPE_ALLOCATABLE_MEMBER_GEP]], i32 0, i32 0 + +// CHECK: %[[LOAD_ALLOCATABLE_MEMBER_BADDR:.*]] = load ptr, ptr %[[ALLOCATABLE_MEMBER_BADDR]], align 8 +// CHECK: %[[ARR_OFFSET:.*]] = getelementptr inbounds i32, ptr %[[LOAD_ALLOCATABLE_MEMBER_BADDR]], i64 0 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_1:.*]] = getelementptr i32, ptr %[[ARR_OFFSET]], i64 1 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_SIZE_SEGMENT_CALC_1]] to i64 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_3:.*]] = ptrtoint ptr %[[DTYPE_ALLOCATABLE_MEMBER_GEP]] to i64 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_4:.*]] = sub i64 %[[DTYPE_SIZE_SEGMENT_CALC_2]], %[[DTYPE_SIZE_SEGMENT_CALC_3]] +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_5:.*]] = sdiv exact i64 %[[DTYPE_SIZE_SEGMENT_CALC_4]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) + +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_ptrs, i32 0, i32 0 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_MEMBER_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [4 x i64], ptr %.offload_sizes, i32 0, i32 0 +// CHECK: store i64 %[[DTYPE_SIZE_SEGMENT_CALC_5]], ptr %[[OFFLOAD_SIZES]], align 8 + +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_baseptrs, i32 0, i32 1 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_ptrs, i32 0, i32 1 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_MEMBER_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 + +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_baseptrs, i32 0, i32 2 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_ptrs, i32 0, i32 2 +// CHECK: store ptr %[[ALLOCATABLE_MEMBER_BADDR]], ptr %[[OFFLOAD_PTRS]], align 8 + +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_baseptrs, i32 0, i32 3 +// CHECK: store ptr %[[ALLOCATABLE_MEMBER_BADDR]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_ptrs, i32 0, i32 3 +// CHECK: store ptr %[[ARR_OFFSET]], ptr %[[OFFLOAD_PTRS]], align 8 + +// CHECK: define void @omp_allocatable_derived_type_member_map(ptr %[[ARG:.*]]) { + +// CHECK: %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA_2:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, align 8 +// CHECK: %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, align 8 +// CHECK: %[[LOAD_DTYPE_ALLOCATABLE_ARG:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG]], align 8 +// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[LOAD_DTYPE_ALLOCATABLE_ARG]], ptr %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA]], align 8 +// CHECK: %[[DTYPE_ALLOCATABLE_BADDR_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA]], i32 0, i32 0 +// CHECK: %[[DTYPE_ALLOCATABLE_BADDR_LOAD:.*]] = load ptr, ptr %[[DTYPE_ALLOCATABLE_BADDR_GEP]], align 8 +// CHECK: %[[DTYPE_ALLOCATABLE_MEMBER_ACCESS:.*]] = getelementptr %_QFtest_allocatable_derived_type_map_operand_and_block_additionTone_layer, ptr %[[DTYPE_ALLOCATABLE_BADDR_LOAD]], i32 0, i32 4 +// CHECK: %[[DTYPE_ALLOCATABLE_MEMBER_BADDR:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr %[[DTYPE_ALLOCATABLE_MEMBER_ACCESS]], i32 0, i32 0 +// CHECK: %[[LOAD_DTYPE_ALLOCATABLE_ARG:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG]], align 8 +// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[LOAD_DTYPE_ALLOCATABLE_ARG]], ptr %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA_2]], align 8 +// CHECK: %[[DTYPE_ALLOCATABLE_BADDR_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA_2]], i32 0, i32 0 +// CHECK: %[[DTYPE_ALLOCATABLE_BADDR_LOAD:.*]] = load ptr, ptr %[[DTYPE_ALLOCATABLE_BADDR_GEP]], align 8 +// CHECK: %[[DTYPE_REGULAR_MEMBER_ACCESS:.*]] = getelementptr %_QFtest_allocatable_derived_type_map_operand_and_block_additionTone_layer, ptr %[[DTYPE_ALLOCATABLE_BADDR_LOAD]], i32 0, i32 5 +// CHECK: %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_2:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG]], i32 0, i32 0 +// CHECK: %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_2_LOAD:.*]] = load ptr, ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_2]], align 8 +// CHECK: %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_LOAD:.*]] = load ptr, ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR]], align 8 +// CHECK: %[[ARR_OFFSET:.*]] = getelementptr inbounds i32, ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_LOAD]], i64 0 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_1:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG]], i32 1 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_SIZE_SEGMENT_CALC_1]] to i64 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_3:.*]] = ptrtoint ptr %[[ARG]] to i64 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_4:.*]] = sub i64 %[[DTYPE_SIZE_SEGMENT_CALC_2]], %[[DTYPE_SIZE_SEGMENT_CALC_3]] +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_5:.*]] = sdiv exact i64 %[[DTYPE_SIZE_SEGMENT_CALC_4]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) +// CHECK: %[[DTYPE_SIZE5_SEGMENT_CALC:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG]], i32 1 +// CHECK: %[[DTYPE_OFFLOAD_PTR_1:.*]] = getelementptr ptr, ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_2]], i32 1 +// CHECK: %[[DTYPE_SIZE2_SEGMENT_CALC:.*]] = ptrtoint ptr %[[DTYPE_ALLOCATABLE_MEMBER_ACCESS]] to i64 +// CHECK: %[[DTYPE_SIZE2_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_OFFLOAD_PTR_1]] to i64 +// CHECK: %[[DTYPE_SIZE2_SEGMENT_CALC_3:.*]] = sub i64 %[[DTYPE_SIZE2_SEGMENT_CALC]], %[[DTYPE_SIZE2_SEGMENT_CALC_2]] +// CHECK: %[[DTYPE_SIZE2_SEGMENT_CALC_4:.*]] = sdiv exact i64 %[[DTYPE_SIZE2_SEGMENT_CALC_3]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) +// CHECK: %[[DTYPE_OFFLOAD_PTR_2:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr %[[DTYPE_ALLOCATABLE_MEMBER_ACCESS]], i32 1 +// CHECK: %[[DTYPE_SIZE3_SEGMENT_CALC:.*]] = ptrtoint ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR]] to i64 +// CHECK: %[[DTYPE_SIZE3_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_OFFLOAD_PTR_2]] to i64 +// CHECK: %[[DTYPE_SIZE3_SEGMENT_CALC_3:.*]] = sub i64 %[[DTYPE_SIZE3_SEGMENT_CALC]], %[[DTYPE_SIZE3_SEGMENT_CALC_2]] +// CHECK: %[[DTYPE_SIZE3_SEGMENT_CALC_4:.*]] = sdiv exact i64 %[[DTYPE_SIZE3_SEGMENT_CALC_3]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) +// CHECK: %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_GEP:.*]] = getelementptr ptr, ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR]], i32 1 +// CHECK: %[[DTYPE_SIZE4_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_REGULAR_MEMBER_ACCESS]] to i64 +// CHECK: %[[DTYPE_SIZE4_SEGMENT_CALC_3:.*]] = ptrtoint ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_GEP]] to i64 +// CHECK: %[[DTYPE_SIZE4_SEGMENT_CALC_4:.*]] = sub i64 %[[DTYPE_SIZE4_SEGMENT_CALC_2]], %[[DTYPE_SIZE4_SEGMENT_CALC_3]] +// CHECK: %[[DTYPE_SIZE4_SEGMENT_CALC_5:.*]] = sdiv exact i64 %[[DTYPE_SIZE4_SEGMENT_CALC_4]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) +// CHECK: %[[DTYPE_OFFLOAD_PTR_3:.*]] = getelementptr i32, ptr %[[DTYPE_REGULAR_MEMBER_ACCESS]], i32 1 +// CHECK: %[[DTYPE_SIZE5_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_SIZE5_SEGMENT_CALC]] to i64 +// CHECK: %[[DTYPE_SIZE5_SEGMENT_CALC_3:.*]] = ptrtoint ptr %[[DTYPE_OFFLOAD_PTR_3]] to i64 +// CHECK: %[[DTYPE_SIZE5_SEGMENT_CALC_4:.*]] = sub i64 %[[DTYPE_SIZE5_SEGMENT_CALC_2]], %[[DTYPE_SIZE5_SEGMENT_CALC_3]] +// CHECK: %[[DTYPE_SIZE5_SEGMENT_CALC_5:.*]] = sdiv exact i64 %[[DTYPE_SIZE5_SEGMENT_CALC_4]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) + +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 0 +// CHECK: store ptr %[[ARG]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [12 x i64], ptr %.offload_sizes, i32 0, i32 0 +// CHECK: store i64 %[[DTYPE_SIZE_SEGMENT_CALC_5]], ptr %[[OFFLOAD_SIZES]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 1 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 1 +// CHECK: store ptr %[[ARG]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 2 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 2 +// CHECK: store ptr %[[DTYPE_OFFLOAD_PTR_1]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [12 x i64], ptr %.offload_sizes, i32 0, i32 2 +// CHECK: store i64 %[[DTYPE_SIZE2_SEGMENT_CALC_4]], ptr %[[OFFLOAD_SIZES]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 3 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 3 +// CHECK: store ptr %[[DTYPE_OFFLOAD_PTR_2]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [12 x i64], ptr %.offload_sizes, i32 0, i32 3 +// CHECK: store i64 %[[DTYPE_SIZE3_SEGMENT_CALC_4]], ptr %[[OFFLOAD_SIZES]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 4 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 4 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [12 x i64], ptr %.offload_sizes, i32 0, i32 4 +// CHECK: store i64 %[[DTYPE_SIZE4_SEGMENT_CALC_5]], ptr %[[OFFLOAD_SIZES]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 5 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 5 +// CHECK: store ptr %[[DTYPE_OFFLOAD_PTR_3]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [12 x i64], ptr %.offload_sizes, i32 0, i32 5 +// CHECK: store i64 %[[DTYPE_SIZE5_SEGMENT_CALC_5]], ptr %[[OFFLOAD_SIZES]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 6 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 6 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_2]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 7 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_2]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 7 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_2_LOAD]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 8 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 8 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_MEMBER_ACCESS]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 9 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 9 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 10 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 10 +// CHECK: store ptr %[[ARR_OFFSET]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 11 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 11 +// CHECK: store ptr %[[DTYPE_REGULAR_MEMBER_ACCESS]], ptr %[[OFFLOAD_PTRS]], align 8 + + +// CHECK: define void @omp_alloca_nested_derived_type_map(ptr %[[ARG:.*]]) { + +// CHECK: %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA_2:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, align 8 +// CHECK: %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, align 8 +// CHECK: %[[LOAD_DTYPE_ALLOCATABLE_ARG:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG]], align 8 +// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[LOAD_DTYPE_ALLOCATABLE_ARG]], ptr %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA]], align 8 +// CHECK: %[[DTYPE_BADDR_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA]], i32 0, i32 0 +// CHECK: %[[DTYPE_BADDR_LOAD:.*]] = load ptr, ptr %[[DTYPE_BADDR_GEP]], align 8 +// CHECK: %[[DTYPE_NESTED_DTYPE_MEMBER_GEP:.*]] = getelementptr %_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTtop_layer, ptr %[[DTYPE_BADDR_LOAD]], i32 0, i32 6 +// CHECK: %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_GEP:.*]] = getelementptr %_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTmiddle_layer, ptr %[[DTYPE_NESTED_DTYPE_MEMBER_GEP]], i32 0, i32 2 +// CHECK: %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_BADDR_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_GEP]], i32 0, i32 0 +// CHECK: %[[LOAD_DTYPE_ALLOCATABLE_ARG:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG]], align 8 +// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[LOAD_DTYPE_ALLOCATABLE_ARG]], ptr %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA_2]], align 8 +// CHECK: %[[DTYPE_BADDR_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[LOCAL_ALLOCATABLE_DTYPE_ALLOCA_2]], i32 0, i32 0 +// CHECK: %[[DTYPE_BADDR_LOAD:.*]] = load ptr, ptr %[[DTYPE_BADDR_GEP]], align 8 +// CHECK: %[[DTYPE_NESTED_DTYPE_MEMBER_GEP:.*]] = getelementptr %_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTtop_layer, ptr %[[DTYPE_BADDR_LOAD]], i32 0, i32 6 +// CHECK: %[[DTYPE_NESTED_REGULAR_MEMBER_GEP:.*]] = getelementptr %_QFtest_alloca_nested_derived_type_map_operand_and_block_additionTmiddle_layer, ptr %[[DTYPE_NESTED_DTYPE_MEMBER_GEP]], i32 0, i32 3 +// CHECK: %[[DTYPE_ALLOCATABLE_BADDR_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG]], i32 0, i32 0 +// CHECK: %[[DTYPE_ALLOCATABLE_BADDR_LOAD:.*]] = load ptr, ptr %[[DTYPE_ALLOCATABLE_BADDR_GEP]], align 8 +// CHECK: %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_BADDR_LOAD:.*]] = load ptr, ptr %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_BADDR_GEP]], align 8 +// CHECK: %[[ARR_OFFSET:.*]] = getelementptr inbounds i32, ptr %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_BADDR_LOAD]], i64 0 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_1:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG]], i32 1 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_SIZE_SEGMENT_CALC_1]] to i64 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_3:.*]] = ptrtoint ptr %[[ARG]] to i64 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_4:.*]] = sub i64 %[[DTYPE_SIZE_SEGMENT_CALC_2]], %[[DTYPE_SIZE_SEGMENT_CALC_3]] +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_5:.*]] = sdiv exact i64 %[[DTYPE_SIZE_SEGMENT_CALC_4]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) +// CHECK: %[[DTYPE_SIZE5_SEGMENT_CALC_1:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG]], i32 1 +// CHECK: %[[DTYPE_OFFLOAD_PTR_1:.*]] = getelementptr ptr, ptr %[[DTYPE_ALLOCATABLE_BADDR_GEP]], i32 1 +// CHECK: %[[DTYPE_SIZE2_SEGMENT_CALC:.*]] = ptrtoint ptr %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_GEP]] to i64 +// CHECK: %[[DTYPE_SIZE2_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_OFFLOAD_PTR_1]] to i64 +// CHECK: %[[DTYPE_SIZE2_SEGMENT_CALC_3:.*]] = sub i64 %[[DTYPE_SIZE2_SEGMENT_CALC]], %[[DTYPE_SIZE2_SEGMENT_CALC_2]] +// CHECK: %[[DTYPE_SIZE2_SEGMENT_CALC_4:.*]] = sdiv exact i64 %[[DTYPE_SIZE2_SEGMENT_CALC_3]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) +// CHECK: %[[DTYPE_OFFLOAD_PTR_2:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_GEP]], i32 1 +// CHECK: %[[DTYPE_SIZE3_SEGMENT_CALC:.*]] = ptrtoint ptr %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_BADDR_GEP]] to i64 +// CHECK: %[[DTYPE_SIZE3_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_OFFLOAD_PTR_2]] to i64 +// CHECK: %[[DTYPE_SIZE3_SEGMENT_CALC_3:.*]] = sub i64 %[[DTYPE_SIZE3_SEGMENT_CALC]], %[[DTYPE_SIZE3_SEGMENT_CALC_2]] +// CHECK: %[[DTYPE_SIZE3_SEGMENT_CALC_4:.*]] = sdiv exact i64 %[[DTYPE_SIZE3_SEGMENT_CALC_3]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) +// CHECK: %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_GEP:.*]] = getelementptr ptr, ptr %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_BADDR_GEP]], i32 1 +// CHECK: %[[DTYPE_SIZE4_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_NESTED_REGULAR_MEMBER_GEP]] to i64 +// CHECK: %[[DTYPE_SIZE4_SEGMENT_CALC_3:.*]] = ptrtoint ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_GEP]] to i64 +// CHECK: %[[DTYPE_SIZE4_SEGMENT_CALC_4:.*]] = sub i64 %[[DTYPE_SIZE4_SEGMENT_CALC_2]], %[[DTYPE_SIZE4_SEGMENT_CALC_3]] +// CHECK: %[[DTYPE_SIZE4_SEGMENT_CALC_5:.*]] = sdiv exact i64 %[[DTYPE_SIZE4_SEGMENT_CALC_4]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) +// CHECK: %[[DTYPE_OFFLOAD_PTR_3:.*]] = getelementptr i32, ptr %[[DTYPE_NESTED_REGULAR_MEMBER_GEP]], i32 1 +// CHECK: %[[DTYPE_SIZE5_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_SIZE5_SEGMENT_CALC_1]] to i64 +// CHECK: %[[DTYPE_SIZE5_SEGMENT_CALC_3:.*]] = ptrtoint ptr %[[DTYPE_OFFLOAD_PTR_3]] to i64 +// CHECK: %[[DTYPE_SIZE5_SEGMENT_CALC_4:.*]] = sub i64 %[[DTYPE_SIZE5_SEGMENT_CALC_2]], %[[DTYPE_SIZE5_SEGMENT_CALC_3]] +// CHECK: %[[DTYPE_SIZE5_SEGMENT_CALC_5:.*]] = sdiv exact i64 %[[DTYPE_SIZE5_SEGMENT_CALC_4]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) + +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 0 +// CHECK: store ptr %[[ARG]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [12 x i64], ptr %.offload_sizes, i32 0, i32 0 +// CHECK: store i64 %[[DTYPE_SIZE_SEGMENT_CALC_5]], ptr %[[OFFLOAD_SIZES]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 1 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 1 +// CHECK: store ptr %[[ARG]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 2 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 2 +// CHECK: store ptr %[[DTYPE_OFFLOAD_PTR_1]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [12 x i64], ptr %.offload_sizes, i32 0, i32 2 +// CHECK: store i64 %[[DTYPE_SIZE2_SEGMENT_CALC_4]], ptr %[[OFFLOAD_SIZES]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 3 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 3 +// CHECK: store ptr %[[DTYPE_OFFLOAD_PTR_2]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [12 x i64], ptr %.offload_sizes, i32 0, i32 3 +// CHECK: store i64 %[[DTYPE_SIZE3_SEGMENT_CALC_4]], ptr %[[OFFLOAD_SIZES]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 4 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 4 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_MEMBER_BADDR_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [12 x i64], ptr %.offload_sizes, i32 0, i32 4 +// CHECK: store i64 %[[DTYPE_SIZE4_SEGMENT_CALC_5]], ptr %[[OFFLOAD_SIZES]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 5 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 5 +// CHECK: store ptr %[[DTYPE_OFFLOAD_PTR_3]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [12 x i64], ptr %.offload_sizes, i32 0, i32 5 +// CHECK: store i64 %[[DTYPE_SIZE5_SEGMENT_CALC_5]], ptr %[[OFFLOAD_SIZES]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 6 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 6 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_BADDR_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 7 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_BADDR_GEP]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 7 +// CHECK: store ptr %[[DTYPE_ALLOCATABLE_BADDR_LOAD]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 8 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 8 +// CHECK: store ptr %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 9 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 9 +// CHECK: store ptr %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_BADDR_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 10 +// CHECK: store ptr %[[DTYPE_NESTED_ALLOCATABLE_MEMBER_BADDR_GEP]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 10 +// CHECK: store ptr %[[ARR_OFFSET]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_baseptrs, i32 0, i32 11 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [12 x ptr], ptr %.offload_ptrs, i32 0, i32 11 +// CHECK: store ptr %[[DTYPE_NESTED_REGULAR_MEMBER_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 + +// CHECK: define void @omp_nested_derived_type_alloca_map(ptr %[[ARG:.*]]) { + +// CHECK: %[[NESTED_DTYPE_MEMBER_GEP:.*]] = getelementptr %_QFtest_nested_derived_type_alloca_map_operand_and_block_additionTtop_layer, ptr %[[ARG]], i32 0, i32 6 +// CHECK: %[[NESTED_ALLOCATABLE_MEMBER_GEP:.*]] = getelementptr %_QFtest_nested_derived_type_alloca_map_operand_and_block_additionTmiddle_layer, ptr %[[NESTED_DTYPE_MEMBER_GEP]], i32 0, i32 2 +// CHECK: %[[NESTED_ALLOCATABLE_MEMBER_BADDR_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr %[[NESTED_ALLOCATABLE_MEMBER_GEP]], i32 0, i32 0 +// CHECK: %[[NESTED_ALLOCATABLE_MEMBER_BADDR_LOAD:.*]] = load ptr, ptr %[[NESTED_ALLOCATABLE_MEMBER_BADDR_GEP]], align 8 +// CHECK: %[[ARR_OFFSET:.*]] = getelementptr inbounds i32, ptr %[[NESTED_ALLOCATABLE_MEMBER_BADDR_LOAD]], i64 0 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_1:.*]] = getelementptr i32, ptr %[[ARR_OFFSET]], i64 1 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_2:.*]] = ptrtoint ptr %[[DTYPE_SIZE_SEGMENT_CALC_1]] to i64 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_3:.*]] = ptrtoint ptr %[[NESTED_ALLOCATABLE_MEMBER_GEP]] to i64 +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_4:.*]] = sub i64 %[[DTYPE_SIZE_SEGMENT_CALC_2]], %[[DTYPE_SIZE_SEGMENT_CALC_3]] +// CHECK: %[[DTYPE_SIZE_SEGMENT_CALC_5:.*]] = sdiv exact i64 %[[DTYPE_SIZE_SEGMENT_CALC_4]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) + +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_baseptrs, i32 0, i32 0 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_ptrs, i32 0, i32 0 +// CHECK: store ptr %[[NESTED_ALLOCATABLE_MEMBER_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 +// CHECK: %[[OFFLOAD_SIZES:.*]] = getelementptr inbounds [4 x i64], ptr %.offload_sizes, i32 0, i32 0 +// CHECK: store i64 %[[DTYPE_SIZE_SEGMENT_CALC_5]], ptr %[[OFFLOAD_SIZES]], align 8 + +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_baseptrs, i32 0, i32 1 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_ptrs, i32 0, i32 1 +// CHECK: store ptr %[[NESTED_ALLOCATABLE_MEMBER_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 + +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_baseptrs, i32 0, i32 2 +// CHECK: store ptr %[[ARG]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_ptrs, i32 0, i32 2 +// CHECK: store ptr %[[NESTED_ALLOCATABLE_MEMBER_BADDR_GEP]], ptr %[[OFFLOAD_PTRS]], align 8 + +// CHECK: %[[BASE_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_baseptrs, i32 0, i32 3 +// CHECK: store ptr %[[NESTED_ALLOCATABLE_MEMBER_BADDR_GEP]], ptr %[[BASE_PTRS]], align 8 +// CHECK: %[[OFFLOAD_PTRS:.*]] = getelementptr inbounds [4 x ptr], ptr %.offload_ptrs, i32 0, i32 3 +// CHECK: store ptr %[[ARR_OFFSET]], ptr %[[OFFLOAD_PTRS]], align 8 diff --git a/mlir/test/Target/LLVMIR/omptarget-host-eval.mlir b/mlir/test/Target/LLVMIR/omptarget-host-eval.mlir new file mode 100644 index 0000000000000..a6494f3347471 --- /dev/null +++ b/mlir/test/Target/LLVMIR/omptarget-host-eval.mlir @@ -0,0 +1,46 @@ +// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s + +module attributes {omp.is_target_device = false, omp.target_triples = ["amdgcn-amd-amdhsa"]} { + llvm.func @omp_target_region_() { + %out_teams = llvm.mlir.constant(1000 : i32) : i32 + %out_threads = llvm.mlir.constant(2000 : i32) : i32 + %out_lb = llvm.mlir.constant(0 : i32) : i32 + %out_ub = llvm.mlir.constant(3000 : i32) : i32 + %out_step = llvm.mlir.constant(1 : i32) : i32 + + omp.target + host_eval(%out_teams -> %teams, %out_threads -> %threads, + %out_lb -> %lb, %out_ub -> %ub, %out_step -> %step : + i32, i32, i32, i32, i32) { + omp.teams num_teams(to %teams : i32) thread_limit(%threads : i32) { + omp.parallel { + omp.distribute { + omp.wsloop { + omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) { + omp.yield + } + } {omp.composite} + } {omp.composite} + omp.terminator + } {omp.composite} + omp.terminator + } + omp.terminator + } + llvm.return + } +} + +// CHECK-LABEL: define void @omp_target_region_ +// CHECK: %[[ARGS:.*]] = alloca %struct.__tgt_kernel_arguments + +// CHECK: %[[TRIPCOUNT_ADDR:.*]] = getelementptr inbounds nuw %struct.__tgt_kernel_arguments, ptr %[[ARGS]], i32 0, i32 8 +// CHECK: store i64 3000, ptr %[[TRIPCOUNT_ADDR]] + +// CHECK: %[[TEAMS_ADDR:.*]] = getelementptr inbounds nuw %struct.__tgt_kernel_arguments, ptr %[[ARGS]], i32 0, i32 10 +// CHECK: store [3 x i32] [i32 1000, i32 0, i32 0], ptr %[[TEAMS_ADDR]] + +// CHECK: %[[THREADS_ADDR:.*]] = getelementptr inbounds nuw %struct.__tgt_kernel_arguments, ptr %[[ARGS]], i32 0, i32 11 +// CHECK: store [3 x i32] [i32 2000, i32 0, i32 0], ptr %[[THREADS_ADDR]] + +// CHECK: call i32 @__tgt_target_kernel(ptr @{{.*}}, i64 {{.*}}, i32 1000, i32 2000, ptr @{{.*}}, ptr %[[ARGS]]) diff --git a/mlir/test/Target/LLVMIR/omptarget-memcpy-align-metadata.mlir b/mlir/test/Target/LLVMIR/omptarget-memcpy-align-metadata.mlir index 13c18401cafab..ce9a4dcbd55be 100644 --- a/mlir/test/Target/LLVMIR/omptarget-memcpy-align-metadata.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-memcpy-align-metadata.mlir @@ -7,49 +7,36 @@ module attributes {llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9", llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true, omp.is_target_device = true} { omp.private {type = private} @_QFEk_private_i32 : i32 llvm.func @_QQmain() { - %0 = llvm.mlir.constant(1 : i32) : i32 - %7 = llvm.alloca %0 x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr<5> - %8 = llvm.addrspacecast %7 : !llvm.ptr<5> to !llvm.ptr - %12 = llvm.mlir.constant(1 : i64) : i64 - %13 = llvm.alloca %12 x i32 {bindc_name = "k"} : (i64) -> !llvm.ptr<5> - %14 = llvm.addrspacecast %13 : !llvm.ptr<5> to !llvm.ptr - %15 = llvm.mlir.constant(1 : i64) : i64 - %16 = llvm.alloca %15 x i32 {bindc_name = "b"} : (i64) -> !llvm.ptr<5> - %17 = llvm.addrspacecast %16 : !llvm.ptr<5> to !llvm.ptr - %19 = llvm.mlir.constant(1 : index) : i64 - %20 = llvm.mlir.constant(0 : index) : i64 - %22 = llvm.mlir.addressof @_QFEa : !llvm.ptr - %25 = llvm.mlir.addressof @_QFECnz : !llvm.ptr - %60 = llvm.getelementptr %8[0, 7, %20, 0] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> - %61 = llvm.load %60 : !llvm.ptr -> i64 - %62 = llvm.getelementptr %8[0, 7, %20, 1] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> - %63 = llvm.load %62 : !llvm.ptr -> i64 - %64 = llvm.getelementptr %8[0, 7, %20, 2] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> - %65 = llvm.load %64 : !llvm.ptr -> i64 - %66 = llvm.sub %63, %19 : i64 - %67 = omp.map.bounds lower_bound(%20 : i64) upper_bound(%66 : i64) extent(%63 : i64) stride(%65 : i64) start_idx(%61 : i64) {stride_in_bytes = true} - %68 = llvm.getelementptr %22[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> - %69 = omp.map.info var_ptr(%22 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%68 : !llvm.ptr) bounds(%67) -> !llvm.ptr {name = ""} - %70 = omp.map.info var_ptr(%22 : !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>) map_clauses(to) capture(ByRef) members(%69 : [0] : !llvm.ptr) -> !llvm.ptr {name = "a"} - %71 = omp.map.info var_ptr(%17 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "b"} - %72 = omp.map.info var_ptr(%14 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr {name = "k"} - %73 = omp.map.info var_ptr(%25 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr {name = "nz"} - omp.target map_entries(%70 -> %arg0, %71 -> %arg1, %72 -> %arg2, %73 -> %arg3, %69 -> %arg4 : !llvm.ptr, !llvm.ptr, !llvm.ptr, !llvm.ptr, !llvm.ptr) { - %106 = llvm.mlir.constant(0 : index) : i64 - %107 = llvm.mlir.constant(13 : i32) : i32 - %108 = llvm.mlir.constant(1000 : i32) : i32 - %109 = llvm.mlir.constant(1 : i32) : i32 + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x i32 {bindc_name = "k"} : (i64) -> !llvm.ptr<5> + %2 = llvm.addrspacecast %1 : !llvm.ptr<5> to !llvm.ptr + %3 = llvm.mlir.constant(1 : i64) : i64 + %4 = llvm.alloca %3 x i32 {bindc_name = "b"} : (i64) -> !llvm.ptr<5> + %5 = llvm.addrspacecast %4 : !llvm.ptr<5> to !llvm.ptr + %6 = llvm.mlir.addressof @_QFEa : !llvm.ptr + %7 = llvm.mlir.addressof @_QFECnz : !llvm.ptr + %8 = llvm.getelementptr %6[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> + %9 = omp.map.info var_ptr(%6 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) var_ptr_ptr(%8 : !llvm.ptr) -> !llvm.ptr {name = ""} + %10 = omp.map.info var_ptr(%6 : !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>) map_clauses(to) capture(ByRef) members(%9 : [0] : !llvm.ptr) -> !llvm.ptr {name = "a"} + %11 = omp.map.info var_ptr(%5 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "b"} + %12 = omp.map.info var_ptr(%2 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr {name = "k"} + %13 = omp.map.info var_ptr(%7 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr {name = "nz"} + omp.target map_entries(%10 -> %arg0, %11 -> %arg1, %12 -> %arg2, %13 -> %arg3, %9 -> %arg4 : !llvm.ptr, !llvm.ptr, !llvm.ptr, !llvm.ptr, !llvm.ptr) { + %14 = llvm.mlir.constant(0 : index) : i64 + %15 = llvm.mlir.constant(13 : i32) : i32 + %16 = llvm.mlir.constant(1000 : i32) : i32 + %17 = llvm.mlir.constant(1 : i32) : i32 omp.teams { omp.parallel private(@_QFEk_private_i32 %arg2 -> %arg5 : !llvm.ptr) { - %110 = llvm.mlir.constant(1 : i32) : i32 - %111 = llvm.alloca %110 x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr<5> - %112 = llvm.addrspacecast %111 : !llvm.ptr<5> to !llvm.ptr + %18 = llvm.mlir.constant(1 : i32) : i32 + %19 = llvm.alloca %18 x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr<5> + %20 = llvm.addrspacecast %19 : !llvm.ptr<5> to !llvm.ptr omp.distribute { omp.wsloop { - omp.loop_nest (%arg6) : i32 = (%109) to (%108) inclusive step (%109) { + omp.loop_nest (%arg6) : i32 = (%17) to (%16) inclusive step (%17) { llvm.store %arg6, %arg5 : i32, !llvm.ptr %115 = llvm.mlir.constant(48 : i32) : i32 - "llvm.intr.memcpy"(%112, %arg0, %115) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () + "llvm.intr.memcpy"(%20, %arg0, %115) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () omp.yield } } {omp.composite} diff --git a/mlir/test/Target/LLVMIR/omptarget-multi-block-reduction.mlir b/mlir/test/Target/LLVMIR/omptarget-multi-block-reduction.mlir index 87ff0ba786648..3fb700fe5606f 100644 --- a/mlir/test/Target/LLVMIR/omptarget-multi-block-reduction.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-multi-block-reduction.mlir @@ -52,7 +52,7 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<"dlti.alloca_memory_space" = 5 : } // CHECK: call void @__kmpc_parallel_51({{.*}}, i32 1, i32 -1, i32 -1, -// CHECK-SAME: ptr @[[PAR_OUTLINED:.*]], ptr null, ptr %2, i64 1) +// CHECK-SAME: ptr @[[PAR_OUTLINED:.*]], ptr null, ptr %{{.*}}, i64 1) // CHECK: define internal void @[[PAR_OUTLINED]]{{.*}} { // CHECK: .omp.reduction.then: diff --git a/mlir/test/Target/LLVMIR/omptarget-nowait.mlir b/mlir/test/Target/LLVMIR/omptarget-nowait.mlir index 19333c44322f1..e26f6016b8dd4 100644 --- a/mlir/test/Target/LLVMIR/omptarget-nowait.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-nowait.mlir @@ -25,34 +25,34 @@ module attributes {omp.target_triples = ["amdgcn-amd-amdhsa"]} { // CHECK: %struct.[[TSK_WTH_PRVTS:.*]] = type { %struct.kmp_task_ompbuilder_t, %struct.[[PRVTS:.*]] } // CHECK: %struct.kmp_task_ompbuilder_t = type { ptr, ptr, i32, ptr, ptr } -// CHECK: %struct.[[PRVTS]] = type { [5 x ptr], [5 x ptr], [5 x i64] } +// CHECK: %struct.[[PRVTS]] = type { [6 x ptr], [6 x ptr], [6 x i64] } // CHECK: define void @launch_(ptr captures(none) %0) // CHECK: %[[STRUCTARG:.*]] = alloca { ptr, ptr }, align 8 -// CHECK: %[[BASEPTRS:.*]] = alloca [5 x ptr], align 8 -// CHECK: %[[PTRS:.*]] = alloca [5 x ptr], align 8 -// CHECK: %[[MAPPERS:.*]] = alloca [5 x ptr], align 8 -// CHECK: %[[SIZES:.*]] = alloca [5 x i64], align 4 +// CHECK: %[[BASEPTRS:.*]] = alloca [6 x ptr], align 8 +// CHECK: %[[PTRS:.*]] = alloca [6 x ptr], align 8 +// CHECK: %[[MAPPERS:.*]] = alloca [6 x ptr], align 8 +// CHECK: %[[SIZES:.*]] = alloca [6 x i64], align 4 -// CHECK: %[[VAL_20:.*]] = getelementptr inbounds [5 x ptr], ptr %[[BASEPTRS]], i32 0, i32 0 -// CHECK: %[[BASEPTRS_GEP:.*]] = getelementptr inbounds [5 x ptr], ptr %[[BASEPTRS]], i32 0, i32 0 -// CHECK: %[[PTRS_GEP:.*]] = getelementptr inbounds [5 x ptr], ptr %[[PTRS]], i32 0, i32 0 -// CHECK: %[[SIZES_GEP:.*]] = getelementptr inbounds [5 x i64], ptr %[[SIZES]], i32 0, i32 0 +// CHECK: %[[VAL_20:.*]] = getelementptr inbounds [6 x ptr], ptr %[[BASEPTRS]], i32 0, i32 0 +// CHECK: %[[BASEPTRS_GEP:.*]] = getelementptr inbounds [6 x ptr], ptr %[[BASEPTRS]], i32 0, i32 0 +// CHECK: %[[PTRS_GEP:.*]] = getelementptr inbounds [6 x ptr], ptr %[[PTRS]], i32 0, i32 0 +// CHECK: %[[SIZES_GEP:.*]] = getelementptr inbounds [6 x i64], ptr %[[SIZES]], i32 0, i32 0 // CHECK: %[[GL_THRD_NUM:.*]] = call i32 @__kmpc_global_thread_num -// CHECK: %[[TASK_DESC:.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @4, i32 {{.*}}, i32 0, i64 160, i64 16, ptr [[TGT_TSK_PRXY_FNC:.*]], i64 -1) +// CHECK: %[[TASK_DESC:.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @4, i32 {{.*}}, i32 0, i64 184, i64 16, ptr [[TGT_TSK_PRXY_FNC:.*]], i64 -1) // CHECK: %[[TSK_PTR:.*]] = getelementptr inbounds nuw %struct.[[TSK_WTH_PRVTS]], ptr %[[TASK_DESC]], i32 0, i32 0 // CHECK: %[[SHAREDS:.*]] = getelementptr inbounds nuw %struct.kmp_task_ompbuilder_t, ptr %[[TSK_PTR]], i32 0, i32 0 // CHECK: %[[SHAREDS_PTR:.*]] = load ptr, ptr %[[SHAREDS]], align 8 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[SHAREDS_PTR]], ptr align 1 %[[STRUCTARG]], i64 16, i1 false) // CHECK: %[[VAL_50:.*]] = getelementptr inbounds nuw %struct.[[TSK_WTH_PRVTS]], ptr %[[TASK_DESC]], i32 0, i32 1 // CHECK: %[[VAL_51:.*]] = getelementptr inbounds nuw %struct.[[PRVTS]], ptr %[[VAL_50]], i32 0, i32 0 -// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[VAL_51]], ptr align 1 %[[BASEPTRS_GEP]], i64 40, i1 false) +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[VAL_51]], ptr align 1 %[[BASEPTRS_GEP]], i64 48, i1 false) // CHECK: %[[VAL_53:.*]] = getelementptr inbounds nuw %struct.[[PRVTS]], ptr %[[VAL_50]], i32 0, i32 1 -// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[VAL_53]], ptr align 1 %[[PTRS_GEP]], i64 40, i1 false) +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[VAL_53]], ptr align 1 %[[PTRS_GEP]], i64 48, i1 false) // CHECK: %[[VAL_54:.*]] = getelementptr inbounds nuw %struct.[[PRVTS]], ptr %[[VAL_50]], i32 0, i32 2 -// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[VAL_54]], ptr align 1 %[[SIZES_GEP]], i64 40, i1 false) +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[VAL_54]], ptr align 1 %[[SIZES_GEP]], i64 48, i1 false) // CHECK: %[[VAL_55:.*]] = call i32 @__kmpc_omp_task(ptr @4, i32 %[[GL_THRD_NUM]], ptr %[[TASK_DESC]]) // CHECK: define internal void @[[WORKER:.*]](i32 {{.*}}, ptr {{.*}}, ptr {{.*}}, ptr {{.*}}, ptr {{.*}}) { diff --git a/mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir b/mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir index 60c6fa4dd8f1e..424e948fac750 100644 --- a/mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir @@ -1,5 +1,5 @@ // RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s - +// XFAIL: * // The aim of the test is to check the LLVM IR codegen for the device // for omp target parallel construct @@ -66,8 +66,8 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo // CHECK: br i1 %[[EXEC_USER_CODE]], label %[[USER_CODE_ENTRY:.*]], label %[[WORKER_EXIT:.*]] // CHECK: %[[TMP6:.*]] = load ptr, ptr %[[TMP4]], align 8 // CHECK: %[[OMP_GLOBAL_THREAD_NUM:.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) -// CHECK: %[[GEP_:.*]] = getelementptr { ptr }, ptr addrspace(5) %[[STRUCTARG]], i32 0, i32 0 -// CHECK: store ptr %[[TMP6]], ptr addrspace(5) %[[GEP_]], align 8 +// CHECK: %[[GEP_:.*]] = getelementptr { ptr }, ptr %[[STRUCTARG_ASCAST]], i32 0, i32 0 +// CHECK: store ptr %[[TMP6]], ptr %[[GEP_]], align 8 // CHECK: %[[TMP7:.*]] = getelementptr inbounds [1 x ptr], ptr %[[TMP2]], i64 0, i64 0 // CHECK: store ptr %[[STRUCTARG_ASCAST]], ptr %[[TMP7]], align 8 // CHECK: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 %[[OMP_GLOBAL_THREAD_NUM]], i32 1, i32 -1, i32 -1, ptr @[[FUNC1:.*]], ptr null, ptr %[[TMP2]], i64 1) diff --git a/mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir b/mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir index 5d2861a5d0f35..2df2b8db0e5f7 100644 --- a/mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir @@ -3,11 +3,12 @@ // The aim of the test is to check the GPU LLVM IR codegen // for nested omp do loop inside omp target region -module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8", llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true, omp.is_target_device = true } { - llvm.func @target_parallel_wsloop(%arg0: !llvm.ptr) attributes {omp.declare_target = #omp.declaretarget, +module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8", llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true, omp.is_target_device = true } { + llvm.func @target_parallel_wsloop(%arg0: !llvm.ptr) attributes { target_cpu = "gfx90a", - target_features = #llvm.target_features<["+gfx9-insts", "+wavefrontsize64"]>} - { + target_features = #llvm.target_features<["+gfx9-insts", "+wavefrontsize64"]>, + omp.declare_target = #omp.declaretarget + } { omp.parallel { %loop_ub = llvm.mlir.constant(9 : i32) : i32 %loop_lb = llvm.mlir.constant(0 : i32) : i32 @@ -41,9 +42,9 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo // CHECK: define internal void @[[LOOP_BODY_FUNC]](i32 %[[CNT:.*]], ptr %[[LOOP_BODY_ARG_PTR:.*]]) #[[ATTRS2:[0-9]+]] { -// CHECK: attributes #[[ATTRS2]] = { +// CHECK: attributes #[[ATTRS1]] = { // CHECK-SAME: "target-cpu"="gfx90a" // CHECK-SAME: "target-features"="+gfx9-insts,+wavefrontsize64" -// CHECK: attributes #[[ATTRS1]] = { +// CHECK: attributes #[[ATTRS2]] = { // CHECK-SAME: "target-cpu"="gfx90a" // CHECK-SAME: "target-features"="+gfx9-insts,+wavefrontsize64" diff --git a/mlir/test/Target/LLVMIR/omptarget-record-type-with-ptr-member-host.mlir b/mlir/test/Target/LLVMIR/omptarget-record-type-with-ptr-member-host.mlir index a1e415c35e4b6..6d1f8f5f6c3ee 100644 --- a/mlir/test/Target/LLVMIR/omptarget-record-type-with-ptr-member-host.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-record-type-with-ptr-member-host.mlir @@ -1,5 +1,5 @@ // RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s - +// XFAIL: * // This test checks the offload sizes, map types and base pointers and pointers // provided to the OpenMP kernel argument structure are correct when lowering // to LLVM-IR from MLIR when a structure with a pointer member type is provided diff --git a/mlir/test/Target/LLVMIR/omptarget-target-inside-task.mlir b/mlir/test/Target/LLVMIR/omptarget-target-inside-task.mlir deleted file mode 100644 index 16be0773bd14b..0000000000000 --- a/mlir/test/Target/LLVMIR/omptarget-target-inside-task.mlir +++ /dev/null @@ -1,43 +0,0 @@ -// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s - -module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true, omp.is_gpu = true} { - llvm.func @omp_target_region_() { - %0 = llvm.mlir.constant(20 : i32) : i32 - %1 = llvm.mlir.constant(10 : i32) : i32 - %2 = llvm.mlir.constant(1 : i64) : i64 - %3 = llvm.alloca %2 x i32 {bindc_name = "a", in_type = i32, operandSegmentSizes = array, uniq_name = "_QFomp_target_regionEa"} : (i64) -> !llvm.ptr<5> - %ascast = llvm.addrspacecast %3 : !llvm.ptr<5> to !llvm.ptr - %4 = llvm.mlir.constant(1 : i64) : i64 - %5 = llvm.alloca %4 x i32 {bindc_name = "b", in_type = i32, operandSegmentSizes = array, uniq_name = "_QFomp_target_regionEb"} : (i64) -> !llvm.ptr<5> - %ascast2 = llvm.addrspacecast %5 : !llvm.ptr<5> to !llvm.ptr - %6 = llvm.mlir.constant(1 : i64) : i64 - %7 = llvm.alloca %6 x i32 {bindc_name = "c", in_type = i32, operandSegmentSizes = array, uniq_name = "_QFomp_target_regionEc"} : (i64) -> !llvm.ptr<5> - %ascast3 = llvm.addrspacecast %7 : !llvm.ptr<5> to !llvm.ptr - llvm.store %1, %ascast : i32, !llvm.ptr - llvm.store %0, %ascast2 : i32, !llvm.ptr - omp.task { - %map1 = omp.map.info var_ptr(%ascast : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = ""} - %map2 = omp.map.info var_ptr(%ascast2 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = ""} - %map3 = omp.map.info var_ptr(%ascast3 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = ""} - omp.target map_entries(%map1 -> %arg0, %map2 -> %arg1, %map3 -> %arg2 : !llvm.ptr, !llvm.ptr, !llvm.ptr) { - %8 = llvm.load %arg0 : !llvm.ptr -> i32 - %9 = llvm.load %arg1 : !llvm.ptr -> i32 - %10 = llvm.add %8, %9 : i32 - llvm.store %10, %arg2 : i32, !llvm.ptr - omp.terminator - } - omp.terminator - } - llvm.return - } - - llvm.func @omp_target_no_map() { - omp.target { - omp.terminator - } - llvm.return - } -} - -// CHECK: define weak_odr protected amdgpu_kernel void @__omp_offloading_{{.*}}_{{.*}}_omp_target_region__l22 -// CHECK: ret void diff --git a/mlir/test/Target/LLVMIR/omptarget-teams-llvm.mlir b/mlir/test/Target/LLVMIR/omptarget-teams-llvm.mlir index c5f89eb2c3274..421d2fa80584c 100644 --- a/mlir/test/Target/LLVMIR/omptarget-teams-llvm.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-teams-llvm.mlir @@ -5,7 +5,9 @@ module attributes {omp.is_target_device = true} { llvm.func @foo(i32) - llvm.func @omp_target_teams_shared_simple(%arg0 : i32) attributes {omp.declare_target = #omp.declaretarget} { + llvm.func @omp_target_teams_shared_simple(%arg0 : i32) attributes { + omp.declare_target = #omp.declaretarget + } { omp.teams { llvm.call @foo(%arg0) : (i32) -> () omp.terminator diff --git a/mlir/test/Target/LLVMIR/omptarget-threadprivate-device-lowering.mlir b/mlir/test/Target/LLVMIR/omptarget-threadprivate-device-lowering.mlir deleted file mode 100644 index ba182374a9e3b..0000000000000 --- a/mlir/test/Target/LLVMIR/omptarget-threadprivate-device-lowering.mlir +++ /dev/null @@ -1,31 +0,0 @@ -// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s - -// Not intended to be a functional example, the aim of this test is to verify -// omp.threadprivate does not crash on lowering during the OpenMP target device -// pass when used in conjunction with target code in the same module. - -module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true } { - llvm.func @func() attributes {omp.declare_target = #omp.declaretarget} { - %0 = llvm.mlir.addressof @_QFEpointer2 : !llvm.ptr - %1 = omp.threadprivate %0 : !llvm.ptr -> !llvm.ptr - %2 = omp.map.info var_ptr(%1 : !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)>) map_clauses(implicit, to) capture(ByRef) -> !llvm.ptr - omp.target map_entries(%2 -> %arg0 : !llvm.ptr) { - %3 = llvm.mlir.constant(1 : i32) : i32 - %4 = llvm.getelementptr %arg0[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> - llvm.store %3, %4 : i32, !llvm.ptr - omp.terminator - } - llvm.return - } - llvm.mlir.global internal @_QFEpointer2() {addr_space = 0 : i32} : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> { - %0 = llvm.mlir.undef : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> - llvm.return %0 : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> - } -} - -// CHECK: define weak_odr protected amdgpu_kernel void @{{.*}}(ptr %{{.*}}, ptr %[[ARG1:.*]]) #{{[0-9]+}} { -// CHECK: %[[ALLOCA:.*]] = alloca ptr, align 8, addrspace(5) -// CHECK: %[[ALLOCA_ASCAST:.*]] = addrspacecast ptr addrspace(5) %[[ALLOCA]] to ptr -// CHECK: store ptr %[[ARG1]], ptr %[[ALLOCA_ASCAST]], align 8 -// CHECK: %[[LOAD_ALLOCA:.*]] = load ptr, ptr %[[ALLOCA_ASCAST]], align 8 -// CHECK: store i32 1, ptr %[[LOAD_ALLOCA]], align 4 diff --git a/mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir b/mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir index d84641ff9c99b..b53412b60982f 100644 --- a/mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir @@ -3,8 +3,10 @@ // The aim of the test is to check the GPU LLVM IR codegen // for nested omp do loop with collapse clause inside omp target region -module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8", llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true, omp.is_target_device = true } { - llvm.func @target_collapsed_wsloop(%arg0: !llvm.ptr) attributes {omp.declare_target = #omp.declaretarget} { +module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8", llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true, omp.is_target_device = true } { + llvm.func @target_collapsed_wsloop(%arg0: !llvm.ptr) attributes { + omp.declare_target = #omp.declaretarget + } { %loop_ub = llvm.mlir.constant(99 : i32) : i32 %loop_lb = llvm.mlir.constant(0 : i32) : i32 %loop_step = llvm.mlir.constant(1 : index) : i32 diff --git a/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir b/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir index 7be635f46111b..6079310677581 100644 --- a/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir @@ -1,10 +1,12 @@ // RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s - +// XFAIL: * // The aim of the test is to check the GPU LLVM IR codegen // for nested omp do loop inside omp target region -module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8", llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true, omp.is_target_device = true } { - llvm.func @target_wsloop(%arg0: !llvm.ptr ) attributes {omp.declare_target = #omp.declaretarget} { +module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8", llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true, omp.is_target_device = true } { + llvm.func @target_wsloop(%arg0: !llvm.ptr) attributes { + omp.declare_target = #omp.declaretarget + } { %loop_ub = llvm.mlir.constant(9 : i32) : i32 %loop_lb = llvm.mlir.constant(0 : i32) : i32 %loop_step = llvm.mlir.constant(1 : i32) : i32 @@ -18,7 +20,9 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo llvm.return } - llvm.func @target_empty_wsloop() attributes {omp.declare_target = #omp.declaretarget} { + llvm.func @target_empty_wsloop() attributes { + omp.declare_target = #omp.declaretarget + } { %loop_ub = llvm.mlir.constant(9 : i32) : i32 %loop_lb = llvm.mlir.constant(0 : i32) : i32 %loop_step = llvm.mlir.constant(1 : i32) : i32 @@ -34,8 +38,12 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo // CHECK: define void @[[FUNC0:.*]](ptr %[[ARG0:.*]]) // CHECK: %[[STRUCTARG:.*]] = alloca { ptr }, align 8, addrspace(5) // CHECK: %[[STRUCTARG_ASCAST:.*]] = addrspacecast ptr addrspace(5) %[[STRUCTARG]] to ptr -// CHECK: %[[GEP:.*]] = getelementptr { ptr }, ptr addrspace(5) %[[STRUCTARG]], i32 0, i32 0 -// CHECK: store ptr %[[ARG0]], ptr addrspace(5) %[[GEP]], align 8 +// CHECK: %[[AL:[0-9]+]] = alloca{{.*}} +// CHECK: %[[CAST:[0-9]+]] = addrspacecast ptr addrspace(5) %[[AL]] +// CHECK: store ptr %[[ARG0]], ptr %[[CAST]]{{.*}} +// CHECK: %[[LOAD:[0-9]+]] = load ptr, ptr %[[CAST]]{{.*}} +// CHECK: %[[GEP:.*]] = getelementptr { ptr }, ptr %[[STRUCTARG_ASCAST]], i32 0, i32 0 +// CHECK: store ptr %[[LOAD]], ptr %[[GEP]], align 8 // CHECK: %[[NUM_THREADS:.*]] = call i32 @omp_get_num_threads() // CHECK: call void @__kmpc_for_static_loop_4u(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr), ptr @[[LOOP_BODY_FN:.*]], ptr %[[STRUCTARG_ASCAST]], i32 10, i32 %[[NUM_THREADS]], i32 0, i8 0) diff --git a/mlir/test/Target/LLVMIR/openmp-cancel.mlir b/mlir/test/Target/LLVMIR/openmp-cancel.mlir index 21241702ad569..e1abb15fbb476 100644 --- a/mlir/test/Target/LLVMIR/openmp-cancel.mlir +++ b/mlir/test/Target/LLVMIR/openmp-cancel.mlir @@ -1,4 +1,5 @@ // RUN: mlir-translate --mlir-to-llvmir %s | FileCheck %s +// XFAIL: * llvm.func @cancel_parallel() { omp.parallel { @@ -127,16 +128,16 @@ llvm.func @cancel_sections_if(%cond : i1) { // CHECK: br label %[[VAL_25:.*]] // CHECK: omp.section.region: ; preds = %[[VAL_24]] // CHECK: br i1 %[[VAL_26:.*]], label %[[VAL_27:.*]], label %[[VAL_28:.*]] -// CHECK: 9: ; preds = %[[VAL_25]] +// CHECK: 8: ; preds = %[[VAL_25]] // CHECK: %[[VAL_29:.*]] = call i32 @__kmpc_global_thread_num(ptr @1) // CHECK: %[[VAL_30:.*]] = call i32 @__kmpc_cancel(ptr @1, i32 %[[VAL_29]], i32 3) // CHECK: %[[VAL_31:.*]] = icmp eq i32 %[[VAL_30]], 0 // CHECK: br i1 %[[VAL_31]], label %[[VAL_32:.*]], label %[[VAL_33:.*]] // CHECK: .split: ; preds = %[[VAL_27]] // CHECK: br label %[[VAL_34:.*]] -// CHECK: 12: ; preds = %[[VAL_25]] +// CHECK: 11: ; preds = %[[VAL_25]] // CHECK: br label %[[VAL_34]] -// CHECK: 13: ; preds = %[[VAL_28]], %[[VAL_32]] +// CHECK: 12: ; preds = %[[VAL_28]], %[[VAL_32]] // CHECK: br label %[[VAL_35:.*]] // CHECK: omp.region.cont: ; preds = %[[VAL_34]] // CHECK: br label %[[VAL_23]] diff --git a/mlir/test/Target/LLVMIR/openmp-llvm-invalid.mlir b/mlir/test/Target/LLVMIR/openmp-llvm-invalid.mlir index 41bc5c4ba525f..1efea084d0dcf 100644 --- a/mlir/test/Target/LLVMIR/openmp-llvm-invalid.mlir +++ b/mlir/test/Target/LLVMIR/openmp-llvm-invalid.mlir @@ -89,3 +89,48 @@ llvm.func @omp_threadprivate() { llvm.store %3, %5 : i32, !llvm.ptr llvm.return } + +// ----- + +module attributes {llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true} { + llvm.func @host_op_in_device(%arg0 : !llvm.ptr) { + // expected-error @below {{unsupported host op found in device}} + // expected-error @below {{LLVM Translation failed for operation: omp.threadprivate}} + %0 = omp.threadprivate %arg0 : !llvm.ptr -> !llvm.ptr + llvm.return + } +} + +// ----- + +module attributes {llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true} { + llvm.func @host_op_in_device_nested_target(%arg0 : !llvm.ptr) { + // expected-error @below {{unsupported host op found in device}} + // expected-error @below {{LLVM Translation failed for operation: omp.parallel}} + omp.parallel { + omp.target { + omp.terminator + } + omp.terminator + } + llvm.return + } +} + +// ----- + +module attributes {llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true} { + llvm.func @host_op_in_device_sibling_target(%x: !llvm.ptr, %expr: i32) { + omp.target { + omp.terminator + } + // expected-error @below {{unsupported host op found in device}} + // expected-error @below {{LLVM Translation failed for operation: omp.atomic.update}} + omp.atomic.update %x : !llvm.ptr { + ^bb0(%xval: i32): + %newval = llvm.add %xval, %expr : i32 + omp.yield(%newval : i32) + } + llvm.return + } +} diff --git a/mlir/test/Target/LLVMIR/openmp-llvm.mlir b/mlir/test/Target/LLVMIR/openmp-llvm.mlir index 8bd33a382197e..d482ee146f428 100644 --- a/mlir/test/Target/LLVMIR/openmp-llvm.mlir +++ b/mlir/test/Target/LLVMIR/openmp-llvm.mlir @@ -358,6 +358,94 @@ llvm.func @wsloop_simple(%arg0: !llvm.ptr) { // ----- +// CHECK-LABEL: wsloop_linear + +// CHECK: {{.*}} = alloca i32, i64 1, align 4 +// CHECK: %[[Y:.*]] = alloca i32, i64 1, align 4 +// CHECK: %[[X:.*]] = alloca i32, i64 1, align 4 + +// CHECK: entry: +// CHECK: %[[LINEAR_VAR:.*]] = alloca i32, align 4 +// CHECK: %[[LINEAR_RESULT:.*]] = alloca i32, align 4 +// CHECK: br label %omp_loop.preheader + +// CHECK: omp_loop.preheader: +// CHECK: %[[LOAD:.*]] = load i32, ptr %[[X]], align 4 +// CHECK: store i32 %[[LOAD]], ptr %[[LINEAR_VAR]], align 4 +// CHECK: %omp_global_thread_num = call i32 @__kmpc_global_thread_num(ptr @2) +// CHECK: call void @__kmpc_barrier(ptr @1, i32 %omp_global_thread_num) + +// CHECK: omp_loop.body: +// CHECK: %[[LOOP_IV:.*]] = add i32 %omp_loop.iv, {{.*}} +// CHECK: %[[LINEAR_LOAD:.*]] = load i32, ptr %[[LINEAR_VAR]], align 4 +// CHECK: %[[MUL:.*]] = mul i32 %[[LOOP_IV]], 1 +// CHECK: %[[ADD:.*]] = add i32 %[[LINEAR_LOAD]], %[[MUL]] +// CHECK: store i32 %[[ADD]], ptr %[[LINEAR_RESULT]], align 4 +// CHECK: br label %omp.loop_nest.region + +// CHECK: omp.loop_nest.region: +// CHECK: %[[LINEAR_LOAD:.*]] = load i32, ptr %[[LINEAR_RESULT]], align 4 +// CHECK: %[[ADD:.*]] = add i32 %[[LINEAR_LOAD]], 2 +// CHECK: store i32 %[[ADD]], ptr %[[Y]], align 4 + +// CHECK: omp_loop.exit: +// CHECK: call void @__kmpc_for_static_fini(ptr @2, i32 %omp_global_thread_num4) +// CHECK: %omp_global_thread_num5 = call i32 @__kmpc_global_thread_num(ptr @2) +// CHECK: call void @__kmpc_barrier(ptr @3, i32 %omp_global_thread_num5) +// CHECK: br label %omp_loop.linear_finalization + +// CHECK: omp_loop.linear_finalization: +// CHECK: %[[LAST_ITER:.*]] = load i32, ptr %p.lastiter, align 4 +// CHECK: %[[CMP:.*]] = icmp ne i32 %[[LAST_ITER]], 0 +// CHECK: br i1 %[[CMP]], label %omp_loop.linear_lastiter_exit, label %omp_loop.linear_exit + +// CHECK: omp_loop.linear_lastiter_exit: +// CHECK: %[[LINEAR_RESULT_LOAD:.*]] = load i32, ptr %[[LINEAR_RESULT]], align 4 +// CHECK: store i32 %[[LINEAR_RESULT_LOAD]], ptr %[[X]], align 4 +// CHECK: br label %omp_loop.linear_exit + +// CHECK: omp_loop.linear_exit: +// CHECK: %omp_global_thread_num6 = call i32 @__kmpc_global_thread_num(ptr @2) +// CHECK: call void @__kmpc_barrier(ptr @1, i32 %omp_global_thread_num6) +// CHECK: br label %omp_loop.after + +llvm.func @wsloop_linear() { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x i32 {bindc_name = "i", pinned} : (i64) -> !llvm.ptr + %2 = llvm.mlir.constant(1 : i64) : i64 + %3 = llvm.alloca %2 x i32 {bindc_name = "y"} : (i64) -> !llvm.ptr + %4 = llvm.mlir.constant(1 : i64) : i64 + %5 = llvm.alloca %4 x i32 {bindc_name = "x"} : (i64) -> !llvm.ptr + %6 = llvm.mlir.constant(1 : i64) : i64 + %7 = llvm.alloca %6 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr + %8 = llvm.mlir.constant(2 : i32) : i32 + %9 = llvm.mlir.constant(10 : i32) : i32 + %10 = llvm.mlir.constant(1 : i32) : i32 + %11 = llvm.mlir.constant(1 : i64) : i64 + %12 = llvm.mlir.constant(1 : i64) : i64 + %13 = llvm.mlir.constant(1 : i64) : i64 + %14 = llvm.mlir.constant(1 : i64) : i64 + omp.wsloop linear(%5 = %10 : !llvm.ptr) { + omp.loop_nest (%arg0) : i32 = (%10) to (%9) inclusive step (%10) { + llvm.store %arg0, %1 : i32, !llvm.ptr + %15 = llvm.load %5 : !llvm.ptr -> i32 + %16 = llvm.add %15, %8 : i32 + llvm.store %16, %3 : i32, !llvm.ptr + %17 = llvm.add %arg0, %10 : i32 + %18 = llvm.icmp "sgt" %17, %9 : i32 + llvm.cond_br %18, ^bb1, ^bb2 + ^bb1: // pred: ^bb0 + llvm.store %17, %1 : i32, !llvm.ptr + llvm.br ^bb2 + ^bb2: // 2 preds: ^bb0, ^bb1 + omp.yield + } + } + llvm.return +} + +// ----- + // CHECK-LABEL: @wsloop_inclusive_1 llvm.func @wsloop_inclusive_1(%arg0: !llvm.ptr) { %0 = llvm.mlir.constant(42 : index) : i64 @@ -2427,7 +2515,7 @@ llvm.func @omp_sections(%arg0 : i32, %arg1 : i32, %arg2 : !llvm.ptr) -> () { // CHECK: [[SECTION3]]: // CHECK: br label %[[REGION3:[^ ,]*]] // CHECK: [[REGION3]]: - // CHECK: %11 = add i32 %{{.*}}, %{{.*}} + // CHECK: %{{.*}} = add i32 %{{.*}}, %{{.*}} %add = llvm.add %arg0, %arg1 : i32 // CHECK: store i32 %{{.*}}, ptr %{{.*}}, align 4 // CHECK: br label %{{.*}} diff --git a/mlir/test/Target/LLVMIR/openmp-target-launch-device.mlir b/mlir/test/Target/LLVMIR/openmp-target-launch-device.mlir index c7f1490240182..e3b7cde7bf9a3 100644 --- a/mlir/test/Target/LLVMIR/openmp-target-launch-device.mlir +++ b/mlir/test/Target/LLVMIR/openmp-target-launch-device.mlir @@ -12,6 +12,13 @@ // CHECK-SAME: %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 [[EXEC_MODE2:1]], i32 [[MIN_THREADS2:1]], i32 [[MAX_THREADS2:30]], i32 [[MIN_TEAMS2:40]], i32 [[MAX_TEAMS2:40]], i32 0, i32 0 }, // CHECK-SAME: ptr @{{.*}}, ptr @{{.*}} } +// CHECK: @[[EXEC_MODE3:.*]] = weak protected constant i8 1 +// CHECK: @llvm.compiler.used{{.*}} = appending global [1 x ptr] [ptr @[[EXEC_MODE3]]], section "llvm.metadata" +// CHECK: @[[KERNEL3_ENV:.*_kernel_environment]] = weak_odr protected constant %struct.KernelEnvironmentTy { +// CHECK-SAME: %struct.ConfigurationEnvironmentTy { i8 1, i8 1, i8 [[EXEC_MODE3:1]], i32 [[MIN_THREADS3:1]], i32 [[MAX_THREADS3:[0-9]+]], i32 [[MIN_TEAMS3:50]], i32 [[MAX_TEAMS3:50]], i32 0, i32 0 }, +// CHECK-SAME: ptr @{{.*}}, ptr @{{.*}} } + + module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true, omp.is_gpu = true} { llvm.func @main(%num_teams : !llvm.ptr) { // CHECK: define weak_odr protected amdgpu_kernel void @__omp_offloading_{{.*}}_main_l{{[0-9]+}}(ptr %[[KERNEL_ARGS:.*]], ptr %[[NUM_TEAMS_ARG:.*]]) #[[ATTRS1:[0-9]+]] @@ -37,9 +44,21 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo } omp.terminator } + + // CHECK: define weak_odr protected amdgpu_kernel void @__omp_offloading_{{.*}}_main_l{{[0-9]+}}(ptr %[[KERNEL_ARGS:.*]]) #[[ATTRS3:[0-9]+]] + // CHECK: %{{.*}} = call i32 @__kmpc_target_init(ptr @[[KERNEL3_ENV]], ptr %[[KERNEL_ARGS]]) + omp.target { + %num_teams3 = llvm.mlir.constant(50) : i32 + omp.teams num_teams(to %num_teams3 : i32) { + omp.terminator + } + omp.terminator + } + llvm.return } } // CHECK: attributes #[[ATTRS1]] = { "amdgpu-flat-work-group-size"="[[MIN_THREADS1]],[[MAX_THREADS1]]" "omp_target_thread_limit"="[[MAX_THREADS1]]" } // CHECK: attributes #[[ATTRS2]] = { "amdgpu-flat-work-group-size"="[[MIN_THREADS2]],[[MAX_THREADS2]]" "amdgpu-max-num-workgroups"="[[MIN_TEAMS2]],1,1" "omp_target_num_teams"="[[MIN_TEAMS2]]" "omp_target_thread_limit"="[[MAX_THREADS2]]" } +// CHECK: attributes #[[ATTRS3]] = { "amdgpu-flat-work-group-size"="[[MIN_THREADS3]],[[MAX_THREADS3]]" "amdgpu-max-num-workgroups"="[[MIN_TEAMS3]],1,1" "omp_target_num_teams"="[[MIN_TEAMS3]]" "omp_target_thread_limit"="[[MAX_THREADS3]]" } diff --git a/mlir/test/Target/LLVMIR/openmp-target-nesting-in-host-ops.mlir b/mlir/test/Target/LLVMIR/openmp-target-nesting-in-host-ops.mlir deleted file mode 100644 index cbf273b887bc7..0000000000000 --- a/mlir/test/Target/LLVMIR/openmp-target-nesting-in-host-ops.mlir +++ /dev/null @@ -1,160 +0,0 @@ -// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s - -module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true, omp.is_target_device = true} { - - omp.private {type = private} @i32_privatizer : i32 - - llvm.func @test_nested_target_in_parallel(%arg0: !llvm.ptr) { - omp.parallel { - %0 = llvm.mlir.constant(4 : index) : i64 - %1 = llvm.mlir.constant(1 : index) : i64 - %4 = omp.map.bounds lower_bound(%1 : i64) upper_bound(%0 : i64) stride(%1 : i64) start_idx(%1 : i64) - %mapv1 = omp.map.info var_ptr(%arg0 : !llvm.ptr, !llvm.array<10 x i32>) map_clauses(tofrom) capture(ByRef) bounds(%4) -> !llvm.ptr {name = ""} - omp.target map_entries(%mapv1 -> %map_arg : !llvm.ptr) { - omp.terminator - } - omp.terminator - } - llvm.return - } - -// CHECK-LABEL: define void @test_nested_target_in_parallel({{.*}}) { -// CHECK-NEXT: br label %omp.parallel.fake.region -// CHECK: omp.parallel.fake.region: -// CHECK-NEXT: br label %omp.region.cont -// CHECK: omp.region.cont: -// CHECK-NEXT: ret void -// CHECK-NEXT: } - - llvm.func @test_nested_target_in_wsloop(%arg0: !llvm.ptr) { - %8 = llvm.mlir.constant(1 : i64) : i64 - %9 = llvm.alloca %8 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr<5> - %ascast = llvm.addrspacecast %9 : !llvm.ptr<5> to !llvm.ptr - %16 = llvm.mlir.constant(10 : i32) : i32 - %17 = llvm.mlir.constant(1 : i32) : i32 - omp.wsloop private(@i32_privatizer %ascast -> %loop_arg : !llvm.ptr) { - omp.loop_nest (%arg1) : i32 = (%17) to (%16) inclusive step (%17) { - llvm.store %arg1, %loop_arg : i32, !llvm.ptr - %0 = llvm.mlir.constant(4 : index) : i64 - %1 = llvm.mlir.constant(1 : index) : i64 - %4 = omp.map.bounds lower_bound(%1 : i64) upper_bound(%0 : i64) stride(%1 : i64) start_idx(%1 : i64) - %mapv1 = omp.map.info var_ptr(%arg0 : !llvm.ptr, !llvm.array<10 x i32>) map_clauses(tofrom) capture(ByRef) bounds(%4) -> !llvm.ptr {name = ""} - omp.target map_entries(%mapv1 -> %map_arg : !llvm.ptr) { - omp.terminator - } - omp.yield - } - } - llvm.return - } - -// CHECK-LABEL: define void @test_nested_target_in_wsloop(ptr %0) { -// CHECK-NEXT: %{{.*}} = alloca i32, i64 1, align 4, addrspace(5) -// CHECK-NEXT: %{{.*}} = addrspacecast ptr addrspace(5) %{{.*}} to ptr -// CHECK-NEXT: br label %omp.wsloop.fake.region -// CHECK: omp.wsloop.fake.region: -// CHECK-NEXT: br label %omp.loop_nest.fake.region -// CHECK: omp.loop_nest.fake.region: -// CHECK-NEXT: store i32 poison, ptr %{{.*}} -// CHECK-NEXT: br label %omp.region.cont1 -// CHECK: omp.region.cont1: -// CHECK-NEXT: br label %omp.region.cont -// CHECK: omp.region.cont: -// CHECK-NEXT: ret void -// CHECK-NEXT: } - - llvm.func @test_nested_target_in_parallel_with_private(%arg0: !llvm.ptr) { - %8 = llvm.mlir.constant(1 : i64) : i64 - %9 = llvm.alloca %8 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr<5> - %ascast = llvm.addrspacecast %9 : !llvm.ptr<5> to !llvm.ptr - omp.parallel private(@i32_privatizer %ascast -> %i_priv_arg : !llvm.ptr) { - %1 = llvm.mlir.constant(1 : index) : i64 - // Use the private clause from omp.parallel to make sure block arguments - // are handled. - %i_val = llvm.load %i_priv_arg : !llvm.ptr -> i64 - %4 = omp.map.bounds lower_bound(%1 : i64) upper_bound(%i_val : i64) stride(%1 : i64) start_idx(%1 : i64) - %mapv1 = omp.map.info var_ptr(%arg0 : !llvm.ptr, !llvm.array<10 x i32>) map_clauses(tofrom) capture(ByRef) bounds(%4) -> !llvm.ptr {name = ""} - omp.target map_entries(%mapv1 -> %map_arg : !llvm.ptr) { - omp.terminator - } - omp.terminator - } - llvm.return - } - - llvm.func @test_nested_target_in_task_with_private(%arg0: !llvm.ptr) { - %8 = llvm.mlir.constant(1 : i64) : i64 - %9 = llvm.alloca %8 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr<5> - %ascast = llvm.addrspacecast %9 : !llvm.ptr<5> to !llvm.ptr - omp.task private(@i32_privatizer %ascast -> %i_priv_arg : !llvm.ptr) { - %1 = llvm.mlir.constant(1 : index) : i64 - // Use the private clause from omp.task to make sure block arguments - // are handled. - %i_val = llvm.load %i_priv_arg : !llvm.ptr -> i64 - %4 = omp.map.bounds lower_bound(%1 : i64) upper_bound(%i_val : i64) stride(%1 : i64) start_idx(%1 : i64) - %mapv1 = omp.map.info var_ptr(%arg0 : !llvm.ptr, !llvm.array<10 x i32>) map_clauses(tofrom) capture(ByRef) bounds(%4) -> !llvm.ptr {name = ""} - omp.target map_entries(%mapv1 -> %map_arg : !llvm.ptr) { - omp.terminator - } - omp.terminator - } - llvm.return - } - - llvm.func @test_target_and_atomic_update(%x: !llvm.ptr, %expr : i32) { - omp.target { - omp.terminator - } - - omp.atomic.update %x : !llvm.ptr { - ^bb0(%xval: i32): - %newval = llvm.add %xval, %expr : i32 - omp.yield(%newval : i32) - } - - llvm.return - } - -// CHECK-LABEL: define void @test_nested_target_in_parallel_with_private({{.*}}) { -// CHECK: br label %omp.parallel.fake.region -// CHECK: omp.parallel.fake.region: -// CHECK: br label %omp.region.cont -// CHECK: omp.region.cont: -// CHECK-NEXT: ret void -// CHECK-NEXT: } - -// CHECK-LABEL: define {{.*}} amdgpu_kernel void @__omp_offloading_{{.*}}_nested_target_in_parallel_{{.*}} { -// CHECK: call i32 @__kmpc_target_init -// CHECK: user_code.entry: -// CHECK: call void @__kmpc_target_deinit() -// CHECK: ret void -// CHECK: } - -// CHECK-LABEL: define {{.*}} amdgpu_kernel void @__omp_offloading_{{.*}}_test_nested_target_in_wsloop_{{.*}} { -// CHECK: call i32 @__kmpc_target_init -// CHECK: user_code.entry: -// CHECK: call void @__kmpc_target_deinit() -// CHECK: ret void -// CHECK: } - -// CHECK-LABEL: define {{.*}} amdgpu_kernel void @__omp_offloading_{{.*}}_test_nested_target_in_parallel_with_private_{{.*}} { -// CHECK: call i32 @__kmpc_target_init -// CHECK: user_code.entry: -// CHECK: call void @__kmpc_target_deinit() -// CHECK: ret void -// CHECK: } - -// CHECK-LABEL: define {{.*}} amdgpu_kernel void @__omp_offloading_{{.*}}_test_nested_target_in_task_with_private_{{.*}} { -// CHECK: call i32 @__kmpc_target_init -// CHECK: user_code.entry: -// CHECK: call void @__kmpc_target_deinit() -// CHECK: ret void -// CHECK: } - -// CHECK-LABEL: define {{.*}} amdgpu_kernel void @__omp_offloading_{{.*}}_test_target_and_atomic_update_{{.*}} { -// CHECK: call i32 @__kmpc_target_init -// CHECK: user_code.entry: -// CHECK: call void @__kmpc_target_deinit() -// CHECK: ret void -// CHECK: } -} diff --git a/mlir/test/Target/LLVMIR/openmp-target-simd-on_device.mlir b/mlir/test/Target/LLVMIR/openmp-target-simd-on_device.mlir index 5c971206731e4..92a5961081f92 100644 --- a/mlir/test/Target/LLVMIR/openmp-target-simd-on_device.mlir +++ b/mlir/test/Target/LLVMIR/openmp-target-simd-on_device.mlir @@ -1,6 +1,6 @@ // RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s -module attributes {omp.is_target_device = true} { +module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true} { omp.private {type = private} @simd_privatizer : !llvm.ptr init { ^bb0(%arg0: !llvm.ptr, %arg1: !llvm.ptr): omp.yield(%arg0 : !llvm.ptr) @@ -9,8 +9,8 @@ module attributes {omp.is_target_device = true} { llvm.func @test_target_simd() { omp.target { %5 = llvm.mlir.constant(1 : i32) : i32 - %x = llvm.alloca %5 x i32 {bindc_name = "x"} : (i32) -> !llvm.ptr - omp.simd private(@simd_privatizer %x -> %arg1 : !llvm.ptr) { + %x = llvm.alloca %5 x i32 {bindc_name = "x"} : (i32) -> !llvm.ptr<5> + omp.simd private(@simd_privatizer %x -> %arg1 : !llvm.ptr<5>) { omp.loop_nest (%arg2) : i32 = (%5) to (%5) inclusive step (%5) { omp.yield } diff --git a/mlir/test/Target/LLVMIR/openmp-task-target-device.mlir b/mlir/test/Target/LLVMIR/openmp-task-target-device.mlir deleted file mode 100644 index 2ce2424cf9541..0000000000000 --- a/mlir/test/Target/LLVMIR/openmp-task-target-device.mlir +++ /dev/null @@ -1,26 +0,0 @@ -// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s - -// This tests the fix for https://github.com/llvm/llvm-project/issues/84606 -// We are only interested in ensuring that the -mlir-to-llmvir pass doesn't crash. -// CHECK: {{.*}} = add i32 {{.*}}, 5 -module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memory_space", 5 : ui32>>, llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_target_device = true} { - llvm.func @_QQmain() attributes {fir.bindc_name = "main", omp.declare_target = #omp.declaretarget} { - %0 = llvm.mlir.constant(0 : i32) : i32 - %1 = llvm.mlir.constant(1 : i64) : i64 - %2 = llvm.alloca %1 x i32 {bindc_name = "a"} : (i64) -> !llvm.ptr<5> - %3 = llvm.addrspacecast %2 : !llvm.ptr<5> to !llvm.ptr - omp.task { - llvm.store %0, %3 : i32, !llvm.ptr - omp.terminator - } - %4 = omp.map.info var_ptr(%3 : !llvm.ptr, i32) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "a"} - omp.target map_entries(%4 -> %arg0 : !llvm.ptr) { - %5 = llvm.mlir.constant(5 : i32) : i32 - %6 = llvm.load %arg0 : !llvm.ptr -> i32 - %7 = llvm.add %6, %5 : i32 - llvm.store %7, %arg0 : i32, !llvm.ptr - omp.terminator - } - llvm.return - } -} diff --git a/mlir/test/Target/LLVMIR/openmp-todo.mlir b/mlir/test/Target/LLVMIR/openmp-todo.mlir index af6d254cfd3c3..3fa982e0ed321 100644 --- a/mlir/test/Target/LLVMIR/openmp-todo.mlir +++ b/mlir/test/Target/LLVMIR/openmp-todo.mlir @@ -1,6 +1,5 @@ // RUN: mlir-translate -mlir-to-llvmir -split-input-file -verify-diagnostics %s - llvm.func @atomic_hint(%v : !llvm.ptr, %x : !llvm.ptr, %expr : i32) { // expected-warning@below {{hint clause discarded}} omp.atomic.capture hint(uncontended) { @@ -113,12 +112,10 @@ llvm.func @sections_private(%x : !llvm.ptr) { llvm.return } - // ----- llvm.func @simd_linear(%lb : i32, %ub : i32, %step : i32, %x : !llvm.ptr) { - // expected-error@below {{not yet implemented: Unhandled clause linear in omp.simd operation}} - // expected-error@below {{LLVM Translation failed for operation: omp.simd}} + // expected-warning@below {{ignored clause: linear in omp.simd operation}} omp.simd linear(%x = %step : !llvm.ptr) { omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) { omp.yield @@ -449,18 +446,6 @@ llvm.func @wsloop_allocate(%lb : i32, %ub : i32, %step : i32, %x : !llvm.ptr) { // ----- -llvm.func @wsloop_linear(%lb : i32, %ub : i32, %step : i32, %x : !llvm.ptr) { - // expected-error@below {{not yet implemented: Unhandled clause linear in omp.wsloop operation}} - // expected-error@below {{LLVM Translation failed for operation: omp.wsloop}} - omp.wsloop linear(%x = %step : !llvm.ptr) { - omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) { - omp.yield - } - } - llvm.return -} - -// ----- llvm.func @wsloop_order(%lb : i32, %ub : i32, %step : i32) { // expected-error@below {{not yet implemented: Unhandled clause order in omp.wsloop operation}} // expected-error@below {{LLVM Translation failed for operation: omp.wsloop}} diff --git a/mlir/test/Target/LLVMIR/ptr.mlir b/mlir/test/Target/LLVMIR/ptr.mlir index 473ac0598e9ce..94b6628772634 100644 --- a/mlir/test/Target/LLVMIR/ptr.mlir +++ b/mlir/test/Target/LLVMIR/ptr.mlir @@ -284,8 +284,8 @@ llvm.func @ptr_add_cst() -> !ptr.ptr<#llvm.address_space<0>> { // CHECK-LABEL: define i64 @ptr_diff_scalar // CHECK-SAME: (ptr %[[PTR1:.*]], ptr %[[PTR2:.*]]) { -// CHECK-NEXT: %[[P1INT:.*]] = ptrtoint ptr %[[PTR1]] to i64 -// CHECK-NEXT: %[[P2INT:.*]] = ptrtoint ptr %[[PTR2]] to i64 +// CHECK-NEXT: %[[P1INT:.*]] = ptrtoaddr ptr %[[PTR1]] to i64 +// CHECK-NEXT: %[[P2INT:.*]] = ptrtoaddr ptr %[[PTR2]] to i64 // CHECK-NEXT: %[[DIFF:.*]] = sub i64 %[[P1INT]], %[[P2INT]] // CHECK-NEXT: ret i64 %[[DIFF]] // CHECK-NEXT: } @@ -296,8 +296,8 @@ llvm.func @ptr_diff_scalar(%ptr1: !ptr.ptr<#llvm.address_space<0>>, %ptr2: !ptr. // CHECK-LABEL: define i32 @ptr_diff_scalar_i32 // CHECK-SAME: (ptr %[[PTR1:.*]], ptr %[[PTR2:.*]]) { -// CHECK-NEXT: %[[P1INT:.*]] = ptrtoint ptr %[[PTR1]] to i64 -// CHECK-NEXT: %[[P2INT:.*]] = ptrtoint ptr %[[PTR2]] to i64 +// CHECK-NEXT: %[[P1INT:.*]] = ptrtoaddr ptr %[[PTR1]] to i64 +// CHECK-NEXT: %[[P2INT:.*]] = ptrtoaddr ptr %[[PTR2]] to i64 // CHECK-NEXT: %[[DIFF:.*]] = sub i64 %[[P1INT]], %[[P2INT]] // CHECK-NEXT: %[[TRUNC:.*]] = trunc i64 %[[DIFF]] to i32 // CHECK-NEXT: ret i32 %[[TRUNC]] @@ -309,8 +309,8 @@ llvm.func @ptr_diff_scalar_i32(%ptr1: !ptr.ptr<#llvm.address_space<0>>, %ptr2: ! // CHECK-LABEL: define <4 x i64> @ptr_diff_vector // CHECK-SAME: (<4 x ptr> %[[PTRS1:.*]], <4 x ptr> %[[PTRS2:.*]]) { -// CHECK-NEXT: %[[P1INT:.*]] = ptrtoint <4 x ptr> %[[PTRS1]] to <4 x i64> -// CHECK-NEXT: %[[P2INT:.*]] = ptrtoint <4 x ptr> %[[PTRS2]] to <4 x i64> +// CHECK-NEXT: %[[P1INT:.*]] = ptrtoaddr <4 x ptr> %[[PTRS1]] to <4 x i64> +// CHECK-NEXT: %[[P2INT:.*]] = ptrtoaddr <4 x ptr> %[[PTRS2]] to <4 x i64> // CHECK-NEXT: %[[DIFF:.*]] = sub <4 x i64> %[[P1INT]], %[[P2INT]] // CHECK-NEXT: ret <4 x i64> %[[DIFF]] // CHECK-NEXT: } @@ -321,8 +321,8 @@ llvm.func @ptr_diff_vector(%ptrs1: vector<4x!ptr.ptr<#llvm.address_space<0>>>, % // CHECK-LABEL: define <8 x i32> @ptr_diff_vector_i32 // CHECK-SAME: (<8 x ptr> %[[PTRS1:.*]], <8 x ptr> %[[PTRS2:.*]]) { -// CHECK-NEXT: %[[P1INT:.*]] = ptrtoint <8 x ptr> %[[PTRS1]] to <8 x i64> -// CHECK-NEXT: %[[P2INT:.*]] = ptrtoint <8 x ptr> %[[PTRS2]] to <8 x i64> +// CHECK-NEXT: %[[P1INT:.*]] = ptrtoaddr <8 x ptr> %[[PTRS1]] to <8 x i64> +// CHECK-NEXT: %[[P2INT:.*]] = ptrtoaddr <8 x ptr> %[[PTRS2]] to <8 x i64> // CHECK-NEXT: %[[DIFF:.*]] = sub <8 x i64> %[[P1INT]], %[[P2INT]] // CHECK-NEXT: %[[TRUNC:.*]] = trunc <8 x i64> %[[DIFF]] to <8 x i32> // CHECK-NEXT: ret <8 x i32> %[[TRUNC]] @@ -344,8 +344,8 @@ llvm.func @ptr_diff_with_constants() -> i64 { // CHECK-LABEL: define i64 @ptr_diff_with_flags_nsw // CHECK-SAME: (ptr %[[PTR1:.*]], ptr %[[PTR2:.*]]) { -// CHECK-NEXT: %[[P1INT:.*]] = ptrtoint ptr %[[PTR1]] to i64 -// CHECK-NEXT: %[[P2INT:.*]] = ptrtoint ptr %[[PTR2]] to i64 +// CHECK-NEXT: %[[P1INT:.*]] = ptrtoaddr ptr %[[PTR1]] to i64 +// CHECK-NEXT: %[[P2INT:.*]] = ptrtoaddr ptr %[[PTR2]] to i64 // CHECK-NEXT: %[[DIFF:.*]] = sub nsw i64 %[[P1INT]], %[[P2INT]] // CHECK-NEXT: ret i64 %[[DIFF]] // CHECK-NEXT: } @@ -356,8 +356,8 @@ llvm.func @ptr_diff_with_flags_nsw(%ptr1: !ptr.ptr<#llvm.address_space<0>>, %ptr // CHECK-LABEL: define i64 @ptr_diff_with_flags_nuw // CHECK-SAME: (ptr %[[PTR1:.*]], ptr %[[PTR2:.*]]) { -// CHECK-NEXT: %[[P1INT:.*]] = ptrtoint ptr %[[PTR1]] to i64 -// CHECK-NEXT: %[[P2INT:.*]] = ptrtoint ptr %[[PTR2]] to i64 +// CHECK-NEXT: %[[P1INT:.*]] = ptrtoaddr ptr %[[PTR1]] to i64 +// CHECK-NEXT: %[[P2INT:.*]] = ptrtoaddr ptr %[[PTR2]] to i64 // CHECK-NEXT: %[[DIFF:.*]] = sub nuw i64 %[[P1INT]], %[[P2INT]] // CHECK-NEXT: ret i64 %[[DIFF]] // CHECK-NEXT: } @@ -368,8 +368,8 @@ llvm.func @ptr_diff_with_flags_nuw(%ptr1: !ptr.ptr<#llvm.address_space<0>>, %ptr // CHECK-LABEL: define i64 @ptr_diff_with_flags_nsw_nuw // CHECK-SAME: (ptr %[[PTR1:.*]], ptr %[[PTR2:.*]]) { -// CHECK-NEXT: %[[P1INT:.*]] = ptrtoint ptr %[[PTR1]] to i64 -// CHECK-NEXT: %[[P2INT:.*]] = ptrtoint ptr %[[PTR2]] to i64 +// CHECK-NEXT: %[[P1INT:.*]] = ptrtoaddr ptr %[[PTR1]] to i64 +// CHECK-NEXT: %[[P2INT:.*]] = ptrtoaddr ptr %[[PTR2]] to i64 // CHECK-NEXT: %[[DIFF:.*]] = sub nuw nsw i64 %[[P1INT]], %[[P2INT]] // CHECK-NEXT: ret i64 %[[DIFF]] // CHECK-NEXT: } diff --git a/mlir/test/lib/Dialect/Test/TestPatterns.cpp b/mlir/test/lib/Dialect/Test/TestPatterns.cpp index efbdbfb65d65b..4f858e6d532cd 100644 --- a/mlir/test/lib/Dialect/Test/TestPatterns.cpp +++ b/mlir/test/lib/Dialect/Test/TestPatterns.cpp @@ -153,7 +153,8 @@ struct FolderCommutativeOp2WithConstant LogicalResult matchAndRewrite(TestCommutative2Op op, PatternRewriter &rewriter) const override { - auto operand = op->getOperand(0).getDefiningOp(); + auto operand = + dyn_cast_or_null(op->getOperand(0).getDefiningOp()); if (!operand) return failure(); Attribute constInput; diff --git a/mlir/test/mlir-opt/local-reproducer-with-threading.mlir b/mlir/test/mlir-opt/local-reproducer-with-threading.mlir index 8e94f4edb91bf..391e78aa1a8d1 100644 --- a/mlir/test/mlir-opt/local-reproducer-with-threading.mlir +++ b/mlir/test/mlir-opt/local-reproducer-with-threading.mlir @@ -1,6 +1,6 @@ // Test that attempting to create a local crash reproducer without disabling threading // prints an error from the pass manager (as opposed to crashing with a stack trace). - +// XFAIL: * // RUN: mlir-opt --verify-diagnostics --mlir-pass-pipeline-local-reproducer \ // RUN: --mlir-pass-pipeline-crash-reproducer=%t %s diff --git a/offload/CMakeLists.txt b/offload/CMakeLists.txt index b277380783500..82ebdf84019a5 100644 --- a/offload/CMakeLists.txt +++ b/offload/CMakeLists.txt @@ -4,6 +4,14 @@ cmake_minimum_required(VERSION 3.20.0) set(LLVM_SUBPROJECT_TITLE "liboffload") +if(DEFINED LIBOMP_SHARED_LINKER_FLAGS) + set(CMAKE_SHARED_LINKER_FLAGS "${LIBOMP_SHARED_LINKER_FLAGS}") +endif() + +if(DEFINED LIBOMP_INSTALL_RPATH) + set(CMAKE_INSTALL_RPATH "${LIBOMP_INSTALL_RPATH}") +endif() + # Permit redefining OPENMP_STANDALONE_BUILD when doing a runtimes build. if (OPENMP_STANDALONE_BUILD OR "${CMAKE_SOURCE_DIR}" STREQUAL "${CMAKE_CURRENT_SOURCE_DIR}") set(OPENMP_STANDALONE_BUILD TRUE) @@ -12,6 +20,10 @@ else() set(OPENMP_STANDALONE_BUILD FALSE) endif() +if(LIBOMPTARGET_NO_SANITIZER_AMDGPU) + set(SANITIZER_AMDGPU FALSE) +endif() + # Check that the library can actually be built. if(APPLE OR WIN32 OR WASM) message(WARNING "libomptarget cannot be built on Windows and MacOS X!") @@ -31,7 +43,11 @@ if(OPENMP_STANDALONE_BUILD) "Suffix of lib installation directory, e.g. 64 => lib64") set(OFFLOAD_INSTALL_LIBDIR "lib${OFFLOAD_LIBDIR_SUFFIX}" CACHE STRING "Path where built offload libraries should be installed.") + include(GNUInstallDirs) + set(LIBOMP_HEADERS_INSTALL_PATH "${CMAKE_INSTALL_INCLUDEDIR}") else() + include(GetClangResourceDir) + get_clang_resource_dir(LIBOMP_HEADERS_INSTALL_PATH SUBDIR include) # When building in tree we install the runtime according to the LLVM settings. if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR AND NOT APPLE) set(OFFLOAD_INSTALL_LIBDIR lib${LLVM_LIBDIR_SUFFIX}/${LLVM_DEFAULT_TARGET_TRIPLE} CACHE STRING @@ -118,6 +134,14 @@ else() set(CMAKE_CXX_EXTENSIONS NO) endif() +# Emit a warning for people who haven't updated their build. +if(NOT "openmp" IN_LIST RUNTIMES_amdgcn-amd-amdhsa_LLVM_ENABLE_RUNTIMES AND + NOT "openmp" IN_LIST RUNTIMES_nvptx64-nvidia-cuda_LLVM_ENABLE_RUNTIMES) + message(WARNING "Building the offloading runtime with no device library. See " + "https://openmp.llvm.org/SupportAndFAQ.html#q-how-to-build-an-openmp-gpu-offload-capable-compiler.html " + "for more information.") +endif() + # Set the path of all resulting libraries to a unified location so that it can # be used for testing. set(LIBOMPTARGET_LIBRARY_DIR ${CMAKE_CURRENT_BINARY_DIR}) @@ -197,15 +221,20 @@ include_directories(${LIBOMPTARGET_LLVM_INCLUDE_DIRS}) # This is a list of all the targets that are supported/tested right now. set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} aarch64-unknown-linux-gnu") +set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} aarch64-unknown-linux-gnu-oldDriver") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} aarch64-unknown-linux-gnu-LTO") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} amdgcn-amd-amdhsa") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} powerpc64le-ibm-linux-gnu") +set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} powerpc64le-ibm-linux-gnu-oldDriver") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} powerpc64le-ibm-linux-gnu-LTO") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} powerpc64-ibm-linux-gnu") +set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} powerpc64-ibm-linux-gnu-oldDriver") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} powerpc64-ibm-linux-gnu-LTO") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} x86_64-unknown-linux-gnu") +set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} x86_64-unknown-linux-gnu-oldDriver") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} x86_64-unknown-linux-gnu-LTO") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} nvptx64-nvidia-cuda") +set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} nvptx64-nvidia-cuda-oldDriver") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} nvptx64-nvidia-cuda-LTO") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} nvptx64-nvidia-cuda-JIT-LTO") set (LIBOMPTARGET_ALL_TARGETS "${LIBOMPTARGET_ALL_TARGETS} s390x-ibm-linux-gnu") @@ -226,6 +255,7 @@ set (LIBOMPTARGET_TESTED_PLUGINS "") string( TOLOWER "${CMAKE_BUILD_TYPE}" LIBOMPTARGET_CMAKE_BUILD_TYPE) if(LIBOMPTARGET_CMAKE_BUILD_TYPE MATCHES debug) option(LIBOMPTARGET_ENABLE_DEBUG "Allow debug output with the environment variable LIBOMPTARGET_DEBUG=1" ON) + add_definitions(-DDEBUG) else() option(LIBOMPTARGET_ENABLE_DEBUG "Allow debug output with the environment variable LIBOMPTARGET_DEBUG=1" OFF) endif() @@ -233,13 +263,19 @@ if(LIBOMPTARGET_ENABLE_DEBUG) add_definitions(-DOMPTARGET_DEBUG) endif() +# OMPD support for libomptarget (currently only with cuda) +set(LIBOMPTARGET_OMPD_SUPPORT FALSE CACHE BOOL "OMPD-support?") +if (LIBOMPTARGET_OMPD_SUPPORT) + add_definitions(-DOMPD_SUPPORT=1) +endif() + # No exceptions and no RTTI, except if requested. set(offload_compile_flags -fno-exceptions) if(NOT LLVM_ENABLE_RTTI) set(offload_compile_flags ${offload_compile_flags} -fno-rtti) endif() if(OFFLOAD_HAVE_WERROR_CTOR) - list(APPEND offload_compile_flags -Werror=global-constructors) +# list(APPEND offload_compile_flags -Werror=global-constructors) endif() # TODO: Consider enabling LTO by default if supported. @@ -327,17 +363,25 @@ else() endif() endmacro() +if(OPENMP_STANDALONE_BUILD OR TARGET omp) + # Check LIBOMP_HAVE_VERSION_SCRIPT_FLAG + include(LLVMCheckCompilerLinkerFlag) + if(NOT APPLE) + llvm_check_compiler_linker_flag(C "-Wl,--version-script=${CMAKE_CURRENT_LIST_DIR}/../openmp/runtime/src/exports_test_so.txt" LIBOMP_HAVE_VERSION_SCRIPT_FLAG) + endif() +endif() + # OMPT support for libomptarget # Follow host OMPT support and check if host support has been requested. # LIBOMP_HAVE_OMPT_SUPPORT indicates whether host OMPT support has been implemented. # LIBOMP_OMPT_SUPPORT indicates whether host OMPT support has been requested (default is ON). # LIBOMPTARGET_OMPT_SUPPORT indicates whether target OMPT support has been requested (default is ON). set(OMPT_TARGET_DEFAULT FALSE) -if ((LIBOMP_HAVE_OMPT_SUPPORT) AND (LIBOMP_OMPT_SUPPORT) AND (NOT WIN32)) +if ((LIBOMP_HAVE_OMPT_SUPPORT) AND (NOT WIN32)) set (OMPT_TARGET_DEFAULT TRUE) endif() set(LIBOMPTARGET_OMPT_SUPPORT ${OMPT_TARGET_DEFAULT} CACHE BOOL "OMPT-target-support?") -if ((OMPT_TARGET_DEFAULT) AND (LIBOMPTARGET_OMPT_SUPPORT)) +if (LIBOMPTARGET_OMPT_SUPPORT) add_definitions(-DOMPT_SUPPORT=1) message(STATUS "OMPT target enabled") else() @@ -345,6 +389,7 @@ else() message(STATUS "OMPT target disabled") endif() +include_directories(include) pythonize_bool(LIBOMPTARGET_OMPT_SUPPORT) if(${LLVM_LIBC_GPU_BUILD}) @@ -357,6 +402,33 @@ set(LIBOMPTARGET_GPU_LIBC_SUPPORT ${LIBOMPTARGET_HAS_LIBC} CACHE BOOL pythonize_bool(LIBOMPTARGET_GPU_LIBC_SUPPORT) set(LIBOMPTARGET_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/include) + +# Various LLVM_TOOLS are needed to build libomptarget +find_package(LLVM QUIET CONFIG PATHS + ${LLVM_INSTALL_PREFIX} + ${LIBOMPTARGET_NVPTX_CUDA_COMPILER_DIR} + ${LIBOMPTARGET_NVPTX_CUDA_LINKER_DIR} + ${CMAKE_CXX_COMPILER_DIR} + NO_DEFAULT_PATH) +if(LLVM_DIR) + message(" -- LLVM found at ${LLVM_DIR}") + find_program(CLANG_TOOL clang PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH) + find_program(CLANG_OFFLOAD_BUNDLER_TOOL clang-offload-bundler PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH) + find_program(AR_TOOL llvm-ar PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH) + find_program(LINK_TOOL llvm-link PATHS ${LLVM_TOOLS_BINARY_DIR} + NO_DEFAULT_PATH) + find_program(OPT_TOOL opt PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH) +elseif (LLVM_TOOL_CLANG_BUILD AND NOT CMAKE_CROSSCOMPILING AND NOT OPENMP_STANDALONE_BUILD) + # LLVM in-tree builds may use CMake target names to discover the tools. + set(CLANG_TOOL $) + set(CLANG_OFFLOAD_BUNDLER_TOOL $) + set(AR_TOOL $) + set(LINK_TOOL $) + set(OPT_TOOL $) +else() + message(" ====== WARNING! no LLVM found! some libomptarget components may be skipped") +endif() + set(LIBOMPTARGET_BINARY_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/include) message(STATUS "OpenMP tools dir in libomptarget: ${LIBOMP_OMP_TOOLS_INCLUDE_DIR}") if(LIBOMP_OMP_TOOLS_INCLUDE_DIR) @@ -368,6 +440,24 @@ set(LIBOMPTARGET_LLVM_LIBRARY_DIR "${LLVM_LIBRARY_DIR}" CACHE STRING set(LIBOMPTARGET_LLVM_LIBRARY_INTDIR "${LIBOMPTARGET_INTDIR}" CACHE STRING "Path to folder where intermediate libraries will be output") +if(SANITIZER_AMDGPU) + add_definitions(-DSANITIZER_AMDGPU=1) + # Check for COMGr package , ASan requires COMGr with minimum version 2.4 + find_package(amd_comgr QUIET 2.4.0 HINTS ${CMAKE_INSTALL_PREFIX} PATHS /opt/rocm) +endif() + +# An Emissary API is a subset of Host APIs that are executed from Offload devices +# using the offload RPC mechanism such as FORTRAN IO runtime and MPI. +option(OFFLOAD_ENABLE_EMISSARY_APIS "Enable build of GPU Emissary APIs" ON) +if(OFFLOAD_ENABLE_EMISSARY_APIS) + # Header install location + add_definitions(-DOFFLOAD_ENABLE_EMISSARY_APIS) + install(FILES ${CMAKE_CURRENT_SOURCE_DIR}/../openmp/device/include/EmissaryIds.h + DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH}) + install(FILES ${CMAKE_CURRENT_SOURCE_DIR}/../openmp/device/include/EmissaryMPI.h + DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH}) +endif() + add_subdirectory(tools/offload-tblgen) # Build offloading plugins and device RTLs if they are available. diff --git a/offload/EnableOffloadRuntime b/offload/EnableOffloadRuntime new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/offload/cmake/Modules/LibomptargetGetDependencies.cmake b/offload/cmake/Modules/LibomptargetGetDependencies.cmake index 2a8bdebf2c1dd..456e926e68dc3 100644 --- a/offload/cmake/Modules/LibomptargetGetDependencies.cmake +++ b/offload/cmake/Modules/LibomptargetGetDependencies.cmake @@ -58,11 +58,12 @@ if(LIBOMPTARGET_NVPTX_ARCH) execute_process(COMMAND ${LIBOMPTARGET_NVPTX_ARCH} OUTPUT_VARIABLE LIBOMPTARGET_NVPTX_ARCH_OUTPUT OUTPUT_STRIP_TRAILING_WHITESPACE) - string(REPLACE "\n" ";" nvptx_arch_list "${LIBOMPTARGET_NVPTX_ARCH_OUTPUT}") - if(nvptx_arch_list) + string(FIND "${LIBOMPTARGET_NVPTX_ARCH_OUTPUT}" "\n" first_arch_string) + string(SUBSTRING "${LIBOMPTARGET_NVPTX_ARCH_OUTPUT}" 0 ${first_arch_string} + arch_string) + if(arch_string) set(LIBOMPTARGET_FOUND_NVIDIA_GPU TRUE) - set(LIBOMPTARGET_NVPTX_DETECTED_ARCH_LIST "${nvptx_arch_list}") - list(GET nvptx_arch_list 0 LIBOMPTARGET_DEP_CUDA_ARCH) + set(LIBOMPTARGET_DEP_CUDA_ARCH "${arch_string}") endif() endif() diff --git a/offload/cmake/OpenMPTesting.cmake b/offload/cmake/OpenMPTesting.cmake index ef8cf34ba0c85..f8c892870a3d5 100644 --- a/offload/cmake/OpenMPTesting.cmake +++ b/offload/cmake/OpenMPTesting.cmake @@ -37,6 +37,17 @@ function(find_standalone_test_dependencies) return() endif() + find_program(OFFLOAD_TBLGEN_EXECUTABLE + NAMES offload-tblgen + PATHS ${OPENMP_LLVM_TOOLS_DIR}) + if (NOT OFFLOAD_TBLGEN_EXECUTABLE) + message(STATUS "Cannot find 'offload-tblgen'.") + message(STATUS "Please put 'not' in your PATH, set OFFLOAD_TBLGEN_EXECUTABLE to its full path, or point OPENMP_LLVM_TOOLS_DIR to its directory.") + message(WARNING "The check targets will not be available!") + set(ENABLE_CHECK_TARGETS FALSE PARENT_SCOPE) + return() + endif() + find_program(OPENMP_NOT_EXECUTABLE NAMES not PATHS ${OPENMP_LLVM_TOOLS_DIR}) diff --git a/offload/include/DeviceEnvironment.h b/offload/include/DeviceEnvironment.h new file mode 100644 index 0000000000000..4260002a1f036 --- /dev/null +++ b/offload/include/DeviceEnvironment.h @@ -0,0 +1,26 @@ +//===---- device_environment.h - OpenMP GPU device environment ---- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Global device environment +// +//===----------------------------------------------------------------------===// + +#ifndef _OMPTARGET_DEVICE_ENVIRONMENT_H_ +#define _OMPTARGET_DEVICE_ENVIRONMENT_H_ + +// deviceRTL uses and DeviceRTL uses explicit definitions + +struct DeviceEnvironmentTy { + uint32_t DebugKind; + uint32_t NumDevices; + uint32_t DeviceNum; + uint32_t DynamicMemSize; + uint64_t ClockFrequency; +}; + +#endif diff --git a/offload/include/OpenMP/Mapping.h b/offload/include/OpenMP/Mapping.h index 45bd9c6e7da8b..bd074648a1ed0 100644 --- a/offload/include/OpenMP/Mapping.h +++ b/offload/include/OpenMP/Mapping.h @@ -105,6 +105,7 @@ struct HostDataToTargetTy { const uintptr_t HstPtrBegin; const uintptr_t HstPtrEnd; // non-inclusive. const map_var_info_t HstPtrName; // Optional source name of mapped variable. + const int32_t AllocKind; const uintptr_t TgtAllocBegin; // allocated target memory const uintptr_t TgtPtrBegin; // mapped target memory = TgtAllocBegin + padding @@ -161,10 +162,11 @@ struct HostDataToTargetTy { public: HostDataToTargetTy(uintptr_t BP, uintptr_t B, uintptr_t E, uintptr_t TgtAllocBegin, uintptr_t TgtPtrBegin, - bool UseHoldRefCount, map_var_info_t Name = nullptr, - bool IsINF = false) + bool UseHoldRefCount, int32_t AllocKind, + map_var_info_t Name = nullptr, bool IsINF = false) : HstPtrBase(BP), HstPtrBegin(B), HstPtrEnd(E), HstPtrName(Name), - TgtAllocBegin(TgtAllocBegin), TgtPtrBegin(TgtPtrBegin), + AllocKind(AllocKind), TgtAllocBegin(TgtAllocBegin), + TgtPtrBegin(TgtPtrBegin), States(std::make_unique(UseHoldRefCount ? 0 : IsINF ? INFRefCount : 1, @@ -568,11 +570,11 @@ struct MappingInfoTy { /// - Data transfer issue fails. TargetPointerResultTy getTargetPointer( HDTTMapAccessorTy &HDTTMap, void *HstPtrBegin, void *HstPtrBase, - int64_t TgtPadding, int64_t Size, map_var_info_t HstPtrName, - bool HasFlagTo, bool HasFlagAlways, bool IsImplicit, bool UpdateRefCount, - bool HasCloseModifier, bool HasPresentModifier, bool HasHoldModifier, - AsyncInfoTy &AsyncInfo, HostDataToTargetTy *OwnedTPR = nullptr, - bool ReleaseHDTTMap = true); + int64_t TgtPadding, int64_t Size, int64_t TypeFlags, + map_var_info_t HstPtrName, bool HasFlagTo, bool HasFlagAlways, + bool IsImplicit, bool UpdateRefCount, bool HasCloseModifier, + bool HasPresentModifier, bool HasHoldModifier, AsyncInfoTy &AsyncInfo, + HostDataToTargetTy *OwnedTPR = nullptr, bool ReleaseHDTTMap = true); /// Return the target pointer for \p HstPtrBegin in \p HDTTMap. The accessor /// ensures exclusive access to the HDTT map. diff --git a/offload/include/OpenMP/OMPT/Callback.h b/offload/include/OpenMP/OMPT/Callback.h index 9d545c643223f..7aff68ced0d79 100644 --- a/offload/include/OpenMP/OMPT/Callback.h +++ b/offload/include/OpenMP/OMPT/Callback.h @@ -16,34 +16,12 @@ #ifdef OMPT_SUPPORT -#include "omp-tools.h" +#include "OmptCommonDefs.h" #pragma push_macro("DEBUG_PREFIX") #undef DEBUG_PREFIX #define DEBUG_PREFIX "OMPT" -#define FOREACH_OMPT_TARGET_CALLBACK(macro) \ - FOREACH_OMPT_DEVICE_EVENT(macro) \ - FOREACH_OMPT_NOEMI_EVENT(macro) \ - FOREACH_OMPT_EMI_EVENT(macro) - -#define performIfOmptInitialized(stmt) \ - do { \ - if (llvm::omp::target::ompt::Initialized) { \ - stmt; \ - } \ - } while (0) - -#define performOmptCallback(CallbackName, ...) \ - do { \ - if (ompt_callback_##CallbackName##_fn) \ - ompt_callback_##CallbackName##_fn(__VA_ARGS__); \ - } while (0) - -/// Function type def used for maintaining unique target region, target -/// operations ids -typedef uint64_t (*IdInterfaceTy)(); - namespace llvm { namespace omp { namespace target { @@ -98,8 +76,6 @@ extern bool Initialized; #pragma pop_macro("DEBUG_PREFIX") -#else -#define performIfOmptInitialized(stmt) #endif // OMPT_SUPPORT #endif // OFFLOAD_INCLUDE_OPENMP_OMPT_CALLBACK_H diff --git a/offload/include/OpenMP/OMPT/Connector.h b/offload/include/OpenMP/OMPT/Connector.h index c7b37740d5642..137a616d83c30 100644 --- a/offload/include/OpenMP/OMPT/Connector.h +++ b/offload/include/OpenMP/OMPT/Connector.h @@ -17,6 +17,10 @@ #ifdef OMPT_SUPPORT +#include "Shared/Debug.h" +#include "omp-tools.h" +#include "omptarget.h" + #include "llvm/Support/DynamicLibrary.h" #include @@ -76,7 +80,7 @@ class OmptLibraryConnectorTy { std::string LibName = LibIdent; LibName += ".so"; - DP("OMPT: Trying to load library %s\n", LibName.c_str()); + DP("Trying to load library %s\n", LibName.c_str()); auto DynLibHandle = std::make_unique( llvm::sys::DynamicLibrary::getPermanentLibrary(LibName.c_str(), &ErrMsg)); @@ -85,12 +89,12 @@ class OmptLibraryConnectorTy { LibConnHandle = nullptr; } else { auto LibConnRtn = "ompt_" + LibIdent + "_connect"; - DP("OMPT: Trying to get address of connection routine %s\n", + DP("Trying to get address of connection routine %s\n", LibConnRtn.c_str()); LibConnHandle = reinterpret_cast( DynLibHandle->getAddressOfSymbol(LibConnRtn.c_str())); } - DP("OMPT: Library connection handle = %p\n", LibConnHandle); + DP("Library connection handle = %p\n", LibConnHandle); IsInitialized = true; } diff --git a/offload/include/OpenMP/OMPT/Interface.h b/offload/include/OpenMP/OMPT/Interface.h index 43fb193bc75a6..3df552a133217 100644 --- a/offload/include/OpenMP/OMPT/Interface.h +++ b/offload/include/OpenMP/OMPT/Interface.h @@ -16,14 +16,21 @@ // Only provide functionality if target OMPT support is enabled #ifdef OMPT_SUPPORT #include "Callback.h" +#include "OmptEventInfoTy.h" +#include "Shared/APITypes.h" +#include "Shared/Debug.h" #include "omp-tools.h" +#include "GenericProfiler.h" + #include "llvm/Support/ErrorHandling.h" #include #include -#define OMPT_IF_BUILT(stmt) stmt +#pragma push_macro("DEBUG_PREFIX") +#undef DEBUG_PREFIX +#define DEBUG_PREFIX "OMPT" /// Callbacks for target regions require task_data representing the /// encountering task. @@ -31,6 +38,7 @@ /// target_task_data representing the target task region. typedef ompt_data_t *(*ompt_get_task_data_t)(); typedef ompt_data_t *(*ompt_get_target_task_data_t)(); +typedef int (*ompt_set_frame_enter_t)(void *Address, int Flags, int State); namespace llvm { namespace omp { @@ -41,10 +49,19 @@ namespace ompt { /// target_task_data. static ompt_get_task_data_t ompt_get_task_data_fn; static ompt_get_target_task_data_t ompt_get_target_task_data_fn; +static ompt_set_frame_enter_t ompt_set_frame_enter_fn; + +/// OMPT global tracing status. Indicates if at least one device is traced. +extern bool TracingActive; + +/// Check if this device traces the given event type +extern bool isTracingEnabled(int DeviceId, unsigned int EventTy); /// Used to maintain execution state for this thread class Interface { public: + // Target data callbacks + /// Top-level function for invoking callback before device data allocation void beginTargetDataAlloc(int64_t DeviceId, void *HstPtrBegin, void **TgtPtrBegin, size_t Size, void *Code); @@ -134,6 +151,85 @@ class Interface { /// Top-level function for invoking callback after target construct void endTarget(int64_t DeviceId, void *Code); + // Target data tracing + + /// Top-level function for starting trace before device data allocation + void startTargetDataAllocTrace(int64_t DeviceId, void *HstPtrBegin, + void **TgtPtrBegin, size_t Size, void *Code); + + /// Top-level function for stopping trace after device data allocation + ompt_record_ompt_t *stopTargetDataAllocTrace(int64_t DeviceId, + void *HstPtrBegin, + void **TgtPtrBegin, size_t Size, + void *Code); + + /// Top-level function for starting trace before data submit + ompt_record_ompt_t *startTargetDataSubmitTrace(int64_t SrcDeviceId, + void *SrcPtrBegin, + int64_t DstDeviceId, + void *DstPtrBegin, size_t Size, + void *Code); + + /// Top-level function for starting trace before device data deallocation + void startTargetDataDeleteTrace(int64_t DeviceId, void *TgtPtrBegin, + void *Code); + + /// Top-level function for stopping trace after device data deallocation + ompt_record_ompt_t *stopTargetDataDeleteTrace(int64_t DeviceId, + void *TgtPtrBegin, void *Code); + + /// Top-level function for starting trace before data retrieve + ompt_record_ompt_t *startTargetDataRetrieveTrace(int64_t SrcDeviceId, + void *SrcPtrBegin, + int64_t DstDeviceId, + void *DstPtrBegin, + size_t Size, void *Code); + + ompt_record_ompt_t * + stopTargetDataMovementTraceAsync(ompt_record_ompt_t *DataPtr, + uint64_t NanosStart, uint64_t NanosEnd); + + /// Top-level function for starting trace before kernel dispatch + ompt_record_ompt_t *startTargetSubmitTrace(int64_t DeviceId, + unsigned int NumTeams = 1); + + ompt_record_ompt_t *stopTargetSubmitTraceAsync(ompt_record_ompt_t *DataPtr, + unsigned int NumTeams, + uint64_t NanosStart, + uint64_t NanosStop); + + // Target region tracing + + /// Top-level function for starting trace before target enter data + /// construct + ompt_record_ompt_t *startTargetDataEnterTrace(int64_t DeviceId, void *Code); + + /// Top-level function for stopping trace after target enter data + /// construct + ompt_record_ompt_t *stopTargetDataEnterTrace(int64_t DeviceId, void *Code); + + /// Top-level function for starting trace before target exit data + /// construct + ompt_record_ompt_t *startTargetDataExitTrace(int64_t DeviceId, void *Code); + + /// Top-level function for stopping trace after target exit data + /// construct + ompt_record_ompt_t *stopTargetDataExitTrace(int64_t DeviceId, void *Code); + + /// Top-level function for starting trace before target update construct + ompt_record_ompt_t *startTargetUpdateTrace(int64_t DeviceId, void *Code); + + /// Top-level function for stopping trace after target update construct + ompt_record_ompt_t *stopTargetUpdateTrace(int64_t DeviceId, void *Code); + + // Target kernel tracing + + /// Top-level function for starting trace before target construct + ompt_record_ompt_t *startTargetTrace(int64_t DeviceId, void *Code); + + /// Top-level function for stopping trace after target construct + ompt_record_ompt_t *stopTargetTrace(int64_t DeviceId, void *Code); + // Callback getter: Target data operations template auto getCallbacks() { if constexpr (OpType == ompt_target_data_alloc || @@ -204,6 +300,69 @@ class Interface { llvm_unreachable("Unhandled target operation!"); } + // Callback getter: Target data operations + template auto getTraceGenerators() { + if constexpr (OpType == ompt_target_data_alloc || + OpType == ompt_target_data_alloc_async) + return std::make_pair(std::mem_fn(&Interface::startTargetDataAllocTrace), + std::mem_fn(&Interface::stopTargetDataAllocTrace)); + + if constexpr (OpType == ompt_target_data_delete || + OpType == ompt_target_data_delete_async) + return std::make_pair(std::mem_fn(&Interface::startTargetDataDeleteTrace), + std::mem_fn(&Interface::stopTargetDataDeleteTrace)); + + if constexpr (OpType == ompt_target_data_transfer_to_device || + OpType == ompt_target_data_transfer_to_device_async) + return std::make_pair( + std::mem_fn(&Interface::startTargetDataSubmitTrace), + std::mem_fn(&Interface::stopTargetDataMovementTraceAsync)); + + if constexpr (OpType == ompt_target_data_transfer_from_device || + OpType == ompt_target_data_transfer_from_device_async) + return std::make_pair( + std::mem_fn(&Interface::startTargetDataRetrieveTrace), + std::mem_fn(&Interface::stopTargetDataMovementTraceAsync)); + + llvm_unreachable("Unhandled target data operation type!"); + } + + // Callback getter: Target region operations + template auto getTraceGenerators() { + if constexpr (OpType == ompt_target_enter_data || + OpType == ompt_target_enter_data_nowait) + return std::make_pair(std::mem_fn(&Interface::startTargetDataEnterTrace), + std::mem_fn(&Interface::stopTargetDataEnterTrace)); + + if constexpr (OpType == ompt_target_exit_data || + OpType == ompt_target_exit_data_nowait) + return std::make_pair(std::mem_fn(&Interface::startTargetDataExitTrace), + std::mem_fn(&Interface::stopTargetDataExitTrace)); + + if constexpr (OpType == ompt_target_update || + OpType == ompt_target_update_nowait) + return std::make_pair(std::mem_fn(&Interface::startTargetUpdateTrace), + std::mem_fn(&Interface::stopTargetUpdateTrace)); + + if constexpr (OpType == ompt_target || OpType == ompt_target_nowait) + return std::make_pair(std::mem_fn(&Interface::startTargetTrace), + std::mem_fn(&Interface::stopTargetTrace)); + + llvm_unreachable("Unknown target region operation type!"); + } + + // Callback getter: Kernel launch operation + template auto getTraceGenerators() { + // We use 'ompt_callbacks_t', because no other enum is currently available + // to model a kernel launch / target submit operation. + if constexpr (OpType == ompt_callback_target_submit) + return std::make_pair( + std::mem_fn(&Interface::startTargetSubmitTrace), + std::mem_fn(&Interface::stopTargetSubmitTraceAsync)); + + llvm_unreachable("Unhandled target operation!"); + } + /// Setters for target region and target operation correlation ids void setTargetDataValue(uint64_t DataValue) { TargetData.value = DataValue; } void setTargetDataPtr(void *DataPtr) { TargetData.ptr = DataPtr; } @@ -227,6 +386,9 @@ class Interface { /// Target task data representing the target task region ompt_data_t *TargetTaskData = nullptr; + /// Used for marking begin of a data operation + void announceTargetRegion(const char *RegionName); + /// Used for marking begin of a data operation void beginTargetDataOperation(); @@ -238,6 +400,23 @@ class Interface { /// Used for marking end of a target region void endTargetRegion(); + + // Called by all trace generation routines + void setTraceRecordCommon(ompt_record_ompt_t *DataPtr, + ompt_callbacks_t CallbackType); + // Type specific helpers + void setTraceRecordTargetDataOp(ompt_record_target_data_op_t *Record, + ompt_target_data_op_t DataOpType, + void *SrcAddr, int64_t SrcDeviceNum, + void *DstAddr, int64_t DstDeviceNum, + size_t Bytes, void *CodePtr); + + void setTraceRecordTargetKernel(ompt_record_target_kernel_t *Record, + unsigned int NumTeams); + + void setTraceRecordTarget(ompt_record_target_t *Record, int64_t DeviceId, + ompt_target_t TargetKind, + ompt_scope_endpoint_t Endpoint, void *CodePtr); }; /// Thread local state for target region and associated metadata @@ -249,14 +428,14 @@ extern thread_local Interface RegionInterface; extern thread_local void *ReturnAddress; template -void InvokeInterfaceFunction(FuncTy Func, ArgsTy Args, +auto InvokeInterfaceFunction(FuncTy Func, ArgsTy Args, std::index_sequence) { - std::invoke(Func, RegionInterface, std::get(Args)...); + return std::invoke(Func, RegionInterface, std::get(Args)...); } -template class InterfaceRAII { +template class InterfaceRAII { public: - InterfaceRAII(CallbackPairTy Callbacks, ArgsTy... Args) + InterfaceRAII(FunctionPairTy Callbacks, ArgsTy... Args) : Arguments(Args...), beginFunction(std::get<0>(Callbacks)), endFunction(std::get<1>(Callbacks)) { performIfOmptInitialized(begin()); @@ -277,14 +456,66 @@ template class InterfaceRAII { } std::tuple Arguments; - typename CallbackPairTy::first_type beginFunction; - typename CallbackPairTy::second_type endFunction; + typename FunctionPairTy::first_type beginFunction; + typename FunctionPairTy::second_type endFunction; }; // InterfaceRAII's class template argument deduction guide -template -InterfaceRAII(CallbackPairTy Callbacks, ArgsTy... Args) - -> InterfaceRAII; +template +InterfaceRAII(FunctionPairTy Callbacks, ArgsTy... Args) + -> InterfaceRAII; + +/// Similar to the original InterfaceRAII this class is used for tracing and +/// extends the original with async capabilities. That is: It takes an +/// additional AsyncInfo reference as argument to populate the relevant fields. +/// The AsyncInfoTy propagates the info into the RTL / plugins. +/// TracedDeviceId represents the trace record's device affinity. EventType is +/// the callback type that needs to be enabled via ompt_set_trace_ompt. +template +class TracerInterfaceRAII { +public: + TracerInterfaceRAII(FunctionPairTy Callbacks, AsyncInfoTy &AsyncInfo, + plugin::GenericProfilerTy *Prof, int TracedDeviceId, + ompt_callbacks_t EventType, ArgsTy... Args) + : Arguments(Args...), beginFunction(std::get<0>(Callbacks)) { + __tgt_async_info *AI = AsyncInfo; + if (isTracingEnabled(TracedDeviceId, EventType)) { + auto Record = begin(); + + // The Profiler can allocate specific data to be used to pass information + // from here to lower parts of the runtime system. + // NOTE: It is the responsibility of the programmer to ensure type + // compatibility and correct usage of the data. The profiler, however, + // OWNS the pointer and frees it at an appropriate time. + OmptEventInfoTy *ProfilerData = + reinterpret_cast(Prof->getProfilerSpecificData()); + ProfilerData->TraceRecord = Record; + ProfilerData->NumTeams = 0; + + // Allows to pass down into the plugins via AsyncInfoTy + AI->ProfilerData = ProfilerData; + } else { + // Actively prevent further tracing of this event + AI->ProfilerData = nullptr; + } + } + +private: + auto begin() { + auto IndexSequence = + std::make_index_sequence>{}; + return InvokeInterfaceFunction(beginFunction, Arguments, IndexSequence); + } + + std::tuple Arguments; + typename FunctionPairTy::first_type beginFunction; + /// No end-function here, since the end is called asynchronously from the + /// plugins, once the operation has completed. +}; + +template +TracerInterfaceRAII(FunctionPairTy Callbacks, ArgsTy... Args) + -> TracerInterfaceRAII; /// Used to set and reset the thread-local return address. The RAII is expected /// to be created at a runtime entry point when the return address should be @@ -322,8 +553,8 @@ class ReturnAddressSetterRAII { // The getter returns the address stored in the thread local variable. #define OMPT_GET_RETURN_ADDRESS llvm::omp::target::ompt::ReturnAddress -#else -#define OMPT_IF_BUILT(stmt) -#endif +#pragma pop_macro("DEBUG_PREFIX") + +#endif // OMPT_SUPPORT #endif // OFFLOAD_INCLUDE_OPENMP_OMPT_INTERFACE_H diff --git a/offload/include/OpenMP/OMPT/OmptCommonDefs.h b/offload/include/OpenMP/OMPT/OmptCommonDefs.h new file mode 100644 index 0000000000000..5391658e80262 --- /dev/null +++ b/offload/include/OpenMP/OMPT/OmptCommonDefs.h @@ -0,0 +1,127 @@ +//===------ OmptCommonDefs.h - Common definitions for OMPT --*- C++ -*-----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Common defines and typedefs for OMPT callback and tracing functionality. +// +//===----------------------------------------------------------------------===// + +#ifndef OFFLOAD_INCLUDE_OMPTCOMMONDEFS_H +#define OFFLOAD_INCLUDE_OMPTCOMMONDEFS_H + +#ifdef OMPT_SUPPORT + +#include "omp-tools.h" + +#pragma push_macro("DEBUG_PREFIX") +#undef DEBUG_PREFIX +#define DEBUG_PREFIX "OMPT" + +#define FUNCPTR_TO_PTR(x) ((void *)(uint64_t)x) + +#define FOREACH_OMPT_TARGET_CALLBACK(macro) \ + FOREACH_OMPT_DEVICE_EVENT(macro) \ + FOREACH_OMPT_NOEMI_EVENT(macro) \ + FOREACH_OMPT_EMI_EVENT(macro) + +// Common device tracing functions +#define FOREACH_OMPT_DEVICE_TRACING_FN_COMMON(macro) \ + macro(ompt_set_trace_ompt) macro(ompt_start_trace) macro(ompt_flush_trace) \ + macro(ompt_stop_trace) macro(ompt_advance_buffer_cursor) \ + macro(ompt_get_record_type) + +// Supported device tracing entry points +#define FOREACH_OMPT_DEVICE_TRACING_FN(macro) \ + FOREACH_OMPT_DEVICE_TRACING_FN_COMMON(macro) \ + macro(ompt_get_record_ompt) macro(ompt_get_device_time) \ + macro(ompt_translate_time) + +// Device tracing functionalities, which are also e.g. coupled to mutexes +#define FOREACH_OMPT_DEVICE_TRACING_FN_IMPLEMENTAIONS(macro) \ + FOREACH_OMPT_DEVICE_TRACING_FN_COMMON(macro) \ + macro(ompt_set_timestamp) macro(ompt_set_granted_teams) + +#define OMPT_API_ROUTINE static + +#define OMPT_CALLBACK_AVAILABLE(fn) (llvm::omp::target::ompt::Initialized && fn) + +#define OMPT_IF_BUILT(stmt) stmt + +#define OMPT_IF_ENABLED(stmts) \ + do { \ + if (llvm::omp::target::ompt::Initialized) { \ + stmts \ + } \ + } while (0) + +#define OMPT_IF_TRACING_ENABLED(stmts) \ + do { \ + if (llvm::omp::target::ompt::TracingActive) { \ + stmts \ + } \ + } while (0) + +#define OMPT_FRAME_FLAGS (ompt_frame_runtime | OMPT_FRAME_POSITION_DEFAULT) + +#if (__PPC64__ | __arm__) +#define OMPT_GET_FRAME_ADDRESS(level) __builtin_frame_address(level) +#define OMPT_FRAME_POSITION_DEFAULT ompt_frame_cfa +#else +#define OMPT_GET_FRAME_ADDRESS(level) __builtin_frame_address(level) +#define OMPT_FRAME_POSITION_DEFAULT ompt_frame_framepointer +#endif + +#define OMPT_PTR_UNKNOWN ((void *)0) + +#define performIfOmptInitialized(stmt) \ + do { \ + if (llvm::omp::target::ompt::Initialized) { \ + stmt; \ + } \ + } while (0) + +#define performOmptCallback(CallbackName, ...) \ + do { \ + if (ompt_callback_##CallbackName##_fn) \ + ompt_callback_##CallbackName##_fn(__VA_ARGS__); \ + } while (0) + +typedef ompt_set_result_t (*libomptarget_ompt_set_trace_ompt_t)( + int Device, unsigned int Enable, unsigned int EventTy); +typedef int (*libomptarget_ompt_start_trace_t)(int, + ompt_callback_buffer_request_t, + ompt_callback_buffer_complete_t); +typedef int (*libomptarget_ompt_flush_trace_t)(int); +typedef int (*libomptarget_ompt_stop_trace_t)(int); +typedef int (*libomptarget_ompt_advance_buffer_cursor_t)( + ompt_device_t *, ompt_buffer_t *, size_t, ompt_buffer_cursor_t, + ompt_buffer_cursor_t *); +typedef ompt_get_record_ompt_t libomptarget_ompt_get_record_ompt_t; +typedef ompt_device_time_t (*libomptarget_ompt_get_device_time_t)( + ompt_device_t *); +typedef ompt_translate_time_t libomptarget_ompt_translate_time_t; +typedef ompt_device_time_t (*libomptarget_ompt_get_device_time_t)( + ompt_device_t *); +typedef ompt_record_t (*libomptarget_ompt_get_record_type_t)( + ompt_buffer_t *, ompt_buffer_cursor_t); +typedef void (*libomptarget_ompt_set_timestamp_t)(uint64_t start, uint64_t end); +typedef void (*libomptarget_ompt_set_granted_teams_t)(uint32_t); + +/// Function type def used for maintaining unique target region, target +/// operations ids +typedef uint64_t (*IdInterfaceTy)(); + +#pragma pop_macro("DEBUG_PREFIX") + +#else +#define performIfOmptInitialized(stmt) +#define OMPT_IF_BUILT(stmt) +#define OMPT_IF_ENABLED(stmts) +#define OMPT_IF_TRACING_ENABLED(stmts) +#endif // OMPT_SUPPORT + +#endif // OFFLOAD_INCLUDE_OMPTCOMMONDEFS_H diff --git a/offload/include/OpenMP/OMPT/OmptEventInfoTy.h b/offload/include/OpenMP/OMPT/OmptEventInfoTy.h new file mode 100644 index 0000000000000..7124b3a3ff501 --- /dev/null +++ b/offload/include/OpenMP/OMPT/OmptEventInfoTy.h @@ -0,0 +1,39 @@ +//===- OmptEventInfoTy.h - OMPT specific trace record data ------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Data structure used to communicate OMPT specific profiler data from the +// high-level libomptarget into the vendor-specific plugins +// +//===----------------------------------------------------------------------===// + +#ifndef OFFLOAD_INCLUDE_OPENMP_OMPT_OMPTEVENTINFOTY_H +#define OFFLOAD_INCLUDE_OPENMP_OMPT_OMPTEVENTINFOTY_H + +#include "Shared/Debug.h" + +struct ompt_record_ompt_t; + +namespace llvm { +namespace omp { +namespace target { +namespace ompt { + +/// Holds info needed to fill asynchronous trace records +struct OmptEventInfoTy { + /// The granted number of teams at runtime + uint64_t NumTeams; + /// Pointer to the actual buffer storage location + ompt_record_ompt_t *TraceRecord; +}; + +} // namespace ompt +} // namespace target +} // namespace omp +} // namespace llvm + +#endif // OFFLOAD_INCLUDE_OPENMP_OMPT_OMPTEVENTINFOTY_H diff --git a/offload/include/OpenMP/OMPT/OmptTracing.h b/offload/include/OpenMP/OMPT/OmptTracing.h new file mode 100644 index 0000000000000..2a892582923d5 --- /dev/null +++ b/offload/include/OpenMP/OMPT/OmptTracing.h @@ -0,0 +1,154 @@ +//===---- OmptTracing.h - Target independent OMPT callbacks --*- C++ -*----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Interface used by target-independent runtimes to coordinate registration and +// invocation of OMPT tracing functionality. +// +//===----------------------------------------------------------------------===// + +#ifndef OPENMP_LIBOMPTARGET_INCLUDE_OMPTTRACING_H +#define OPENMP_LIBOMPTARGET_INCLUDE_OMPTTRACING_H + +#ifdef OMPT_SUPPORT + +#include + +#include "OmptCommonDefs.h" +#include "OmptTracingBuffer.h" + +#pragma push_macro("DEBUG_PREFIX") +#undef DEBUG_PREFIX +#define DEBUG_PREFIX "OMPT" + +namespace llvm { +namespace omp { +namespace target { +namespace ompt { + +/// After a timestamp has been read, reset it. +void resetTimestamp(uint64_t *T); + +/// A tool may register unique buffer-request and buffer-completion +/// callback functions for a device. The following are utility functions to +/// manage those functions. + +/// Given a device-id, return the corresponding buffer-request callback +/// function. +ompt_callback_buffer_request_t getBufferRequestFn(int DeviceId); + +/// Give a device-id, return the corresponding buffer-completion callback +/// function. +ompt_callback_buffer_complete_t getBufferCompleteFn(int DeviceId); + +/// Given a device-id, set the corresponding buffer-request and +/// buffer-completion callback functions. +void setBufferManagementFns(int DeviceId, ompt_callback_buffer_request_t ReqFn, + ompt_callback_buffer_complete_t CmpltFn); + +/// Given a device-id, remove the corresponding buffer-request and +/// buffer-completion callback functions. +void removeBufferManagementFns(int DeviceId); + +/// Is device tracing stopped for all devices? +bool isAllDeviceTracingStopped(); + +/// Invoke callback function for buffer request events +void ompt_callback_buffer_request(int DeviceId, ompt_buffer_t **BufferPtr, + size_t *Bytes); + +/// Invoke callback function for buffer complete events +void ompt_callback_buffer_complete(int DeviceId, ompt_buffer_t *Buffer, + size_t Bytes, + ompt_buffer_cursor_t BeginCursor, + int BufferOwned); + +/// Set 'start' and 'stop' for the current trace record +void setOmptTimestamp(uint64_t StartTime, uint64_t EndTime); + +/// Set the linear function correlation between host and device clocks +void setOmptHostToDeviceRate(double Slope, double Offset); + +/// Set / store the number of granted teams +void setOmptGrantedNumTeams(uint64_t NumTeams); + +/// Check if (1) tracing is globally active (2) the given device is actively +/// traced and (3) the given event type is traced on the device +bool isTracingEnabled(int DeviceId, unsigned int EventTy); + +/// Check if the given device is actively traced +bool isTracedDevice(int DeviceId); + +/// Check if the given device is monitoring the provided tracing type +bool isTracingTypeEnabled(int DeviceId, unsigned int EventTy); + +/// Check if the given device is monitoring the provided tracing type 'group' +/// Where group means we will check for both: EMI and non-EMI event types +bool isTracingTypeGroupEnabled(int DeviceId, unsigned int EventTy); + +/// Set whether the given tracing type should be monitored (or not) on the +/// device +void setTracingTypeEnabled(uint64_t &TracedEventTy, bool Enable, + unsigned int EventTy); + +/// Set / reset the given tracing types (EventTy = 0 corresponds to 'all') +ompt_set_result_t setTraceEventTy(int DeviceId, unsigned int Enable, + unsigned int EventTy); + +/// Return thread id +uint64_t getThreadId(); + +/// See TracedDevices in OmptDeviceTracing.h +extern std::map TracedDevices; +/// Activate tracing on the given device +void enableDeviceTracing(int DeviceId); +/// Deactivate tracing on the given device +void disableDeviceTracing(int DeviceId); + +/// Mutexes to serialize invocation of device registration and checks +extern std::mutex DeviceAccessMutex; + +/// Mutexes to serialize invocation of device-independent entry points +extern std::mutex TraceAccessMutex; +extern std::mutex TraceControlMutex; + +/// Ensure serialization of calls to std::hash +extern std::mutex TraceHashThreadMutex; + +/// Protect map from device-id to the corresponding buffer-request and +/// buffer-completion callback functions. +extern std::mutex BufferManagementFnMutex; + +/// Map from device-id to the corresponding buffer-request and buffer-completion +/// callback functions. +extern std::unordered_map> + BufferManagementFns; + +/// Thread local variables used by the plugin to communicate OMPT information +/// that are then used to populate trace records. This method assumes a +/// synchronous implementation, otherwise it won't work. +extern thread_local uint32_t TraceRecordNumGrantedTeams; +extern thread_local uint64_t TraceRecordStartTime; +extern thread_local uint64_t TraceRecordStopTime; + +/// Thread local thread-id. +extern thread_local uint64_t ThreadId; + +/// OMPT global tracing status. Indicates if at least one device is traced. +extern bool TracingActive; + +} // namespace ompt +} // namespace target +} // namespace omp +} // namespace llvm + +#pragma pop_macro("DEBUG_PREFIX") + +#endif // OMPT_SUPPORT + +#endif // OPENMP_LIBOMPTARGET_INCLUDE_OMPTTRACING_H diff --git a/offload/include/OpenMP/OMPT/OmptTracingBuffer.h b/offload/include/OpenMP/OMPT/OmptTracingBuffer.h new file mode 100644 index 0000000000000..5c9f4bf33dae8 --- /dev/null +++ b/offload/include/OpenMP/OMPT/OmptTracingBuffer.h @@ -0,0 +1,412 @@ +//===- OmptTracingBuffer.h - Target independent OpenMP target RTL -- C++ *-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Interface to be used for generating and flushing OMPT device trace records. +// +//===----------------------------------------------------------------------===// + +#ifndef OPENMP_LIBOMPTARGET_OMPTTRACINGBUFFER_H +#define OPENMP_LIBOMPTARGET_OMPTTRACINGBUFFER_H + +#ifdef OMPT_SUPPORT + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "Shared/EnvironmentVar.h" + +// Maximum number of devices supported in device tracing. No device tracing +// will be performed for any device-id larger than 1023. +#define MAX_NUM_DEVICES 1024 + +// TODO Start with 1 helper thread and add dynamically if required +// Number of helper threads must not execeed 32 since the +// thread-wait-tracker is 32 bits in length. +#define OMPT_NUM_HELPER_THREADS 1 + +/* + * Buffer manager for trace records generated by OpenMP master and + * worker threads. During device init, a tool may register a + * buffer-request and a buffer-completion callback. The buffer-request + * callback should be used to allocate new buffers as required. The + * buffer-complete callback should be used to return trace records to + * the tool. + * + * In addition to trace records, this class manages the helper threads + * for dispatching a range of trace records to the tool. + */ +class OmptTracingBufferMgr { +public: + /* + * A trace record (TR) holds the trace data. Its type + * can be ompt or native. Currently, only ompt type is implemented. + */ + + /* + * A TR can be in the following states: + * TR_init: initial state + * TR_ready: An OpenMP thread marks a TR ready when it is done + * populating the TR + * TR_released: A helper thread marks a TR released after it has + * completed returning the TR to the tool + */ + enum TRStatus { TR_init, TR_ready, TR_released }; + + /* + * Metadata capturing the state of a buffer of trace records. Once a + * buffer is allocated by an OpenMP worker thread, trace records are + * carved out from that buffer by that same OpenMP thread alone. Thus + * the allocated buffer is thread-specific from the allocation/population + * standpoint. But it may be manipulated by helper threads. + * + * Id, DeviceId, Start, and TotalBytes are not changed once set. + * RemainingBytes could be written multiple times but only by the same + * thread. But Cursor and IsFull may be read/written by an OpenMP worker + * thread and read by helper threads. Hence, accesses of + * this 2nd set of locations need to be atomic or synchronized. + */ + struct Buffer { + uint64_t Id; // Unique identifier of the buffer + int64_t DeviceId; // Device for which this buffer is allocated + void *Start; // Start of allocated space for trace records + size_t TotalBytes; // Total number of bytes in the allocated space + size_t RemainingBytes; // Total number of unused bytes + // corresponding to Cursor + std::atomic Cursor; // Address of the last trace record carved out + std::atomic IsFull; // true if no more trace records can be + // accomodated, otherwise false + Buffer(uint64_t BufId, int64_t DevId, void *S, size_t Bytes, size_t Rem, + void *C, bool F) + : Id(BufId), DeviceId(DevId), Start(S), TotalBytes(Bytes), + RemainingBytes(Rem), Cursor(C), IsFull(F) {} + Buffer() = delete; + Buffer(const Buffer &) = delete; + Buffer &operator=(const Buffer &) = delete; + }; + using BufPtr = std::shared_ptr; + +private: + /// Envar to control whether a buffer should be flushed when it gets full. + BoolEnvar OMPX_FlushOnBufferFull; + + /// Envar to control whether all buffers should be flushed during shutdown. + BoolEnvar OMPX_FlushOnShutdown; + + // Internal variable for tracking threads to wait for flush + uint32_t ThreadFlushTracker; + + // Internal variable for tracking threads shutting down + uint32_t ThreadShutdownTracker; + + using MapId2Buf = std::map; + + // Map from id to corresponding buffer. The ids are assigned in + // increasing order of creation. + MapId2Buf Id2BufferMap; + + // Trace record. We currently support OMPT data type only. The state + // (TRStatus type) is maintained inline in the trace record. The + // tool is expected to access only the OMPT record. + struct TraceRecord { + ompt_record_ompt_t TR; + std::atomic TRState; + }; + + // Thread-specific array of pointers to a buffer. The buffer pointed to + // is the last one allocated by this thread for a given device. The ith + // element points to the buffer for the ith device. At most MAX_NUM_DEVICES + // devices are supported. + static thread_local BufPtr ArrayOfBufPtr[MAX_NUM_DEVICES]; + + /* + * A buffer is flushed when it fills up or when the tool invokes + * flush_trace. So it's possible that the same buffer may be flushed + * more than once. When a buffer is flushed the first time, a unique + * id (flush-id) is generated and assigned to that buffer. Even if + * it is flushed again, the previously assigned id is maintained for + * that buffer. This id is loosely used to determine the order in + * which the buffers are processed and the corresponding trace + * records released to the tool. + */ + + struct FlushInfo { + uint64_t FlushId; + void *FlushCursor; + BufPtr FlushBuf; + FlushInfo() = default; + FlushInfo(uint64_t Id, void *CR, BufPtr Buf) + : FlushId{Id}, FlushCursor{CR}, FlushBuf{Buf} {} + }; + + /* + * A buffer may be in the following states: + * Flush_waiting: when a buffer is flushed, either because it is + * full or because the tool invokes ompt_flush_trace + * Flush_processing: when a helper thread claims the waiting buffer + * and is in the process of dispatching buffer-completion callbacks + * on an associated range of trace records. If all trace records are + * not released, the state may be reset to Flush_waiting after the + * buffer-completion callbacks return + */ + enum BufferFlushStatus { Flush_waiting, Flush_processing }; + struct FlushMd { + void *FlushCursor; + BufPtr FlushBuf; + BufferFlushStatus FlushStatus; + FlushMd(void *CR, BufPtr Buf, BufferFlushStatus Status) + : FlushCursor{CR}, FlushBuf{Buf}, FlushStatus{Status} {} + FlushMd() = delete; + }; + + using MapId2Md = std::map; + + /* + * A map from a flush-id to metadata containing the current + * cursor. the corresponding buffer, and its flushed status. If a + * buffer is flushed multiple times, the cursor is updated to the + * furthest one + */ + MapId2Md Id2FlushMdMap; + + using UMapBufPtr2Id = std::unordered_map; + + // A hash map from a buffer address to the corresponding flush-id + UMapBufPtr2Id FlushBufPtr2IdMap; + + using USetCursor = std::unordered_set; + + USetCursor LastCursors; + + using UMapThd2Id = std::unordered_map; + + // A hash map from a helper thread id to an integer + UMapThd2Id HelperThreadIdMap; + + // Mutex to protect Id2BufferMap and Cursor2BufMdMap + std::mutex BufferMgrMutex; + + // Mutex to protect FlushBufPtr2IdMap and Id2FlushMdMap + std::mutex FlushMutex; + + // Mutex to protect metadata tracking last cursors of buffer-completion + // callbacks + std::mutex LastCursorMutex; + + // Condition variable used by helper thread to signal that flush is requested + std::condition_variable FlushCv; + + // Condition variable used while waiting for flushing to complete + std::condition_variable ThreadFlushCv; + + // Condition variable used while waiting for threads to shutdown + std::condition_variable ThreadShutdownCv; + + // TODO Separate out the helper thread into its own class + std::vector CompletionThreads; + + /// Called when a buffer \p Buf may be flushed with \p Cursor as the + /// last allocated trace record in the buffer. + /// triggerFlushOnBufferFull should be called without holding any lock. + void triggerFlushOnBufferFull(void *Cursor, BufPtr Buf); + + // Called to dispatch buffer-completion callbacks for the trace records in + // this buffer + void flushBuffer(FlushInfo); + + // Dispatch a buffer-completion callback with a range of trace records + void dispatchCallback(int64_t DeviceId, void *Buffer, void *FirstCursor, + void *LastCursor); + + // Add a last cursor + void addLastCursor(void *Cursor) { + std::unique_lock Lock(LastCursorMutex); + LastCursors.emplace(Cursor); + } + + // Remove a last cursor + void removeLastCursor(void *Cursor) { + std::unique_lock Lock(LastCursorMutex); + assert(LastCursors.find(Cursor) != LastCursors.end()); + LastCursors.erase(Cursor); + } + + // Given a trace record pointer, initialize its metadata + void initTraceRecordMetaData(void *Rec); + + // Given a device-id, get/set a pointer to the last allocated buffer metadata. + BufPtr getDeviceSpecificBuffer(int64_t DevId); + void setDeviceSpecificBuffer(int64_t DevId, BufPtr Buf); + + // Reserve a candidate buffer for flushing, preventing other helper threads + // from accessing it + FlushInfo findAndReserveFlushedBuf(uint64_t FlushId); + + // Unreserve a buffer so that other helper threads can process it + void unreserveFlushedBuf(const FlushInfo &); + + // All done with this buffer, so the buffer and its metadata can be removed + void destroyFlushedBuf(const FlushInfo &); + + // Add a new buffer by an OpenMP thread so that a helper thread can process it + uint64_t addNewFlushEntry(BufPtr Buf, void *Cursor); + + // Get the next trace record + void *getNextTR(void *TR); + + // Given a buffer, return the latest cursor + void *getBufferCursor(BufPtr); + + // Is no more space remaining for trace records in this buffer? + bool isBufferFull(const FlushInfo &); + + // Have all trace records in this buffer been returned to the tool? + bool isBufferOwned(const FlushInfo &); + + // Dispatch a buffer-completion callback and indicate that the buffer can be + // deallocated + void dispatchBufferOwnedCallback(const FlushInfo &); + + // Main entry point for a helper thread + void driveCompletion(); + + // Examine the flushed buffers and dispatch buffer-completion callbacks + void invokeCallbacks(); + + // The caller does not hold a lock while calling this method + void waitForFlushCompletion(); + + // Given a thread number, set the corresponding bit in the flush + // tracker. The caller must hold the flush lock. + void setThreadFlush(uint32_t ThreadNum) { + ThreadFlushTracker |= (1 << ThreadNum); + } + + // Reset this thread's flush bit. The caller must hold the flush lock + void resetThisThreadFlush() { + std::thread::id ID = std::this_thread::get_id(); + assert(HelperThreadIdMap.find(ID) != HelperThreadIdMap.end()); + ThreadFlushTracker &= ~(1 << HelperThreadIdMap[ID]); + } + + // Given a thread number, set the corresponding bit in the shutdown + // tracker. The caller must hold the flush lock. + void setThreadShutdown(uint32_t ThreadNum) { + ThreadShutdownTracker |= (1 << ThreadNum); + } + + // Reset this thread's shutdown bit. The caller must hold the flush + // lock + void resetThisThreadShutdown() { + std::thread::id ID = std::this_thread::get_id(); + assert(HelperThreadIdMap.find(ID) != HelperThreadIdMap.end()); + ThreadShutdownTracker &= ~(1 << HelperThreadIdMap[ID]); + } + + // Return true if this thread's flush bit is set. The caller must + // hold the flush lock + bool isThisThreadFlushWaitedUpon() { + std::thread::id ID = std::this_thread::get_id(); + assert(HelperThreadIdMap.find(ID) != HelperThreadIdMap.end()); + return (ThreadFlushTracker & (1 << HelperThreadIdMap[ID])) != 0; + } + + // Return true if this thread's shutdown bit is set. The caller must + // hold the flush lock + bool isThisThreadShutdownWaitedUpon() { + std::thread::id ID = std::this_thread::get_id(); + assert(HelperThreadIdMap.find(ID) != HelperThreadIdMap.end()); + return (ThreadShutdownTracker & (1 << HelperThreadIdMap[ID])) != 0; + } + + // The caller must not hold the flush lock + bool amIHelperThread() { + std::unique_lock flush_lock(FlushMutex); + if (HelperThreadIdMap.find(std::this_thread::get_id()) != + HelperThreadIdMap.end()) + return true; + return false; + } + + // The caller must not hold the flush lock + bool areHelperThreadsAvailable(); + + // The caller must hold the appropriate lock + void init(); + + // The caller must hold the flush lock + void createHelperThreads(); + + // The caller must hold the flush lock + void destroyHelperThreads(); + +public: + OmptTracingBufferMgr() + : OMPX_FlushOnBufferFull("LIBOMPTARGET_OMPT_FLUSH_ON_BUFFER_FULL", true), + OMPX_FlushOnShutdown("LIBOMPTARGET_OMPT_FLUSH_ON_SHUTDOWN", true) { + // no need to hold locks for init() since object is getting constructed + // here. + init(); + } + + OmptTracingBufferMgr(const OmptTracingBufferMgr &) = delete; + OmptTracingBufferMgr &operator=(const OmptTracingBufferMgr &) = delete; + + // The caller must not hold the flush lock + void startHelperThreads(); + + // The caller must not hold the flush lock. The helper threads are shut down + // without flushing any outstanding trace records. + void shutdownHelperThreads(); + + // The caller must not hold the flush lock. The helper threads are shut down + // after flushing all outstanding trace records for all devices. + void flushAndShutdownHelperThreads(); + + // Assign a cursor for a new trace record. This will assign a trace record + // for the provided device-id, allocating a new buffer if required. + void *assignCursor(ompt_callbacks_t Type, int64_t DeviceId); + + // Get the size of a trace record + size_t getTRSize() { return sizeof(TraceRecord); } + + // Get the status of a trace record. This function does not acquire + // a lock. If locking is required, the caller must hold a lock. + TRStatus getTRStatus(void *Rec); + + // Set the status of a trace record. This function does not acquire + // a lock. If locking is required, the caller must hold a lock. + void setTRStatus(void *Rec, TRStatus); + + // Is this a last cursor of a buffer completion callback? + bool isLastCursor(void *Cursor) { + std::unique_lock Lock(LastCursorMutex); + return LastCursors.find(Cursor) != LastCursors.end(); + } + + // Called for flushing outstanding buffers for the provided device-id. + int flushAllBuffers(int DeviceId); +}; + +#else +class OmptTracingBufferMgr {}; +#endif // OMPT_SUPPORT + +#endif // OPENMP_LIBOMPTARGET_OMPTTRACINGBUFFER_H diff --git a/offload/include/PluginManager.h b/offload/include/PluginManager.h index 6c6fdebe76dff..882dab0fa5a97 100644 --- a/offload/include/PluginManager.h +++ b/offload/include/PluginManager.h @@ -13,6 +13,7 @@ #ifndef OMPTARGET_PLUGIN_MANAGER_H #define OMPTARGET_PLUGIN_MANAGER_H +#include "OpenMP/OMPT/OmptTracingBuffer.h" #include "PluginInterface.h" #include "DeviceImage.h" @@ -48,7 +49,7 @@ struct PluginManager { /// Exclusive accessor type for the device container. using ExclusiveDevicesAccessorTy = Accessor; - PluginManager() {} + PluginManager() : TraceRecordManager(nullptr) {} void init(); @@ -150,6 +151,13 @@ struct PluginManager { return count; } + auto getTraceRecordManager() const { + // Must be called after runtime is initialized. Since the runtime init + // allocates TraceRecordManager, we assert below. + assert(TraceRecordManager && "Trace record manager not initialized"); + return TraceRecordManager; + } + private: bool RTLsLoaded = false; llvm::SmallVector<__tgt_bin_desc *> DelayedBinDesc; @@ -176,6 +184,8 @@ struct PluginManager { /// Devices associated with plugins, accesses to the container are exclusive. ProtectedObj Devices; + OmptTracingBufferMgr *TraceRecordManager; + /// References to upgraded legacy offloading entries. std::list> LegacyEntries; std::list> LegacyImages; diff --git a/offload/include/Shared/APITypes.h b/offload/include/Shared/APITypes.h index 8c150b6bfc2d4..c7d223ffe14c2 100644 --- a/offload/include/Shared/APITypes.h +++ b/offload/include/Shared/APITypes.h @@ -21,6 +21,13 @@ #include #include +#include +#include + +#ifdef OMPT_SUPPORT +#include "OpenMP/OMPT/OmptEventInfoTy.h" +#include +#endif #include extern "C" { @@ -84,6 +91,11 @@ struct __tgt_async_info { /// ensure it is a valid location while the transfer to the device is /// happening. KernelLaunchEnvironmentTy KernelLaunchEnvironment; + + /// Use for sync interface. When false => synchronous execution + bool ExecAsync = true; + /// Maintain the actal data for OMPT. + void *ProfilerData = nullptr; }; /// This struct contains all of the arguments to a target kernel region launch. diff --git a/offload/include/Shared/Debug.h b/offload/include/Shared/Debug.h index 7c3db8dbf119f..71651d61a59d8 100644 --- a/offload/include/Shared/Debug.h +++ b/offload/include/Shared/Debug.h @@ -41,6 +41,8 @@ #include #include #include +#include +#include /// 32-Bit field data attributes controlling information presented to the user. enum OpenMPInfoType : uint32_t { @@ -56,8 +58,15 @@ enum OpenMPInfoType : uint32_t { OMP_INFOTYPE_PLUGIN_KERNEL = 0x0010, // Print whenever data is transferred to the device OMP_INFOTYPE_DATA_TRANSFER = 0x0020, + // AMD-only flag values (at least for now) + // Show kernel launches + OMP_INFOTYPE_AMD_KERNEL_TRACE = 0x1000, + // Enable also API-level tracing + OMP_INFOTYPE_AMD_API_TRACE = 0x200, // Print whenever data does not have a viable device counterpart. OMP_INFOTYPE_EMPTY_MAPPING = 0x0040, + // Print diagnostic information for users. + OMP_INFOTYPE_USER_DIAGNOSTIC = 0x0080, // Enable every flag. OMP_INFOTYPE_ALL = 0xffffffff, }; @@ -70,6 +79,25 @@ inline std::atomic &getInfoLevelInternal() { InfoLevel.store(std::stoi(EnvStr)); }); + static std::once_flag KTFlag{}; + std::call_once(KTFlag, []() { + if (char *EnvStr = getenv("LIBOMPTARGET_KERNEL_TRACE")) { + auto V = std::stoi(EnvStr); + // Match the LIBOMPTARGET_KERNEL_TRACE values and set InfoLevel to the + // enum values to keep backward-compatibility for + // LIBOMPTARGET_KERNEL_TRACE + if (V == 1) + InfoLevel.store(OMP_INFOTYPE_AMD_KERNEL_TRACE); + if (V == 2) + InfoLevel.store(OMP_INFOTYPE_AMD_API_TRACE | + /*OMP_INFOTYPE_API_TRACE=*/0xff000000); + if (V == 3) + InfoLevel.store(OMP_INFOTYPE_AMD_KERNEL_TRACE | + OMP_INFOTYPE_AMD_API_TRACE | + /*OMP_INFOTYPE_API_TRACE=*/0xff000000); + } + }); + return InfoLevel; } diff --git a/offload/include/Shared/RPCOpcodes.h b/offload/include/Shared/RPCOpcodes.h index beee29df1f707..7d70aae016f95 100644 --- a/offload/include/Shared/RPCOpcodes.h +++ b/offload/include/Shared/RPCOpcodes.h @@ -18,6 +18,11 @@ typedef enum { OFFLOAD_HOST_CALL = LLVM_OFFLOAD_OPCODE(0), + OFFLOAD_EMISSARY = LLVM_OFFLOAD_OPCODE(1), + EMISSARY_PREMALLOC = LLVM_OFFLOAD_OPCODE(2), + EMISSARY_FREE = LLVM_OFFLOAD_OPCODE(3), + ALT_LIBC_MALLOC = LLVM_OFFLOAD_OPCODE(4), + ALT_LIBC_FREE = LLVM_OFFLOAD_OPCODE(5), } offload_opcode_t; #undef LLVM_OFFLOAD_OPCODE diff --git a/offload/include/Shared/Requirements.h b/offload/include/Shared/Requirements.h index b16a1650f0c40..887e121b625cd 100644 --- a/offload/include/Shared/Requirements.h +++ b/offload/include/Shared/Requirements.h @@ -38,7 +38,17 @@ enum OpenMPOffloadingRequiresDirFlags : int64_t { /// when running on an APU, the GPU plugin may decide to /// run in zero-copy even though the user did not program /// their application with unified_shared_memory requirement. - OMPX_REQ_AUTO_ZERO_COPY = 0x020 + OMPX_REQ_AUTO_ZERO_COPY = 0x020, + /// Eager Maps is an extension of auto zero-copy and + /// unified shared memory. Selected using an environment + /// varible OMPX_EAGER_ZERO_COPY_MAPS, it makes memory mapping + /// issue a GPU TLB prefaulting action. This allows applications + /// using unified memory to run with unified memory support disabled + /// (if possible on the target device). + OMPX_REQ_EAGER_ZERO_COPY_MAPS = 0x040, + /// Flag which signals whether Multi-Device kernels are enabled in + /// the runtime. + OMPX_REQ_MULTI_DEVICE_ENABLED = 0x080 }; class RequirementCollection { @@ -70,11 +80,30 @@ class RequirementCollection { return; } - // Auto zero-copy is only valid when no other requirement has been set - // and it is computed at device initialization time, after the requirement - // flag has already been set to OMP_REQ_NONE. - if (SetFlags == OMP_REQ_NONE && NewFlags == OMPX_REQ_AUTO_ZERO_COPY) { - SetFlags = NewFlags; + // Eager maps can happen on top of previous requirements: + if (NewFlags == OMPX_REQ_EAGER_ZERO_COPY_MAPS) { + if (SetFlags == OMP_REQ_NONE) + SetFlags = NewFlags; + else + SetFlags |= OMPX_REQ_EAGER_ZERO_COPY_MAPS; + return; + } + + // Auto zero-copy is only valid when either no other requirement has been + // set or eager maps mode has been enabled. It is computed at device + // initialization time, after the requirement flag has already been set to + // OMP_REQ_NONE. + if (NewFlags == OMPX_REQ_AUTO_ZERO_COPY) { + if (SetFlags == OMP_REQ_NONE) + SetFlags = NewFlags; + else if (SetFlags == OMPX_REQ_EAGER_ZERO_COPY_MAPS) + SetFlags |= OMPX_REQ_AUTO_ZERO_COPY; + return; + } + + // Ensure that the Multi-device mode is activated. + if (NewFlags == OMPX_REQ_MULTI_DEVICE_ENABLED) { + SetFlags |= OMPX_REQ_MULTI_DEVICE_ENABLED; return; } diff --git a/offload/include/device.h b/offload/include/device.h index 4e27943d1dbc1..9b707dd8d20fb 100644 --- a/offload/include/device.h +++ b/offload/include/device.h @@ -46,6 +46,16 @@ struct DeviceTy { int32_t DeviceID; GenericPluginTy *RTL; int32_t RTLDeviceID; + /// The physical number of processors that may concurrently execute a team + /// For cuda, this is number of SMs, for amdgcn, this is number of CUs. + /// This field is used by ompx_get_team_procs(devid). + int32_t TeamProcs; + + + /// Flag to force synchronous data transfers + /// Controlled via environment flag OMPX_FORCE_SYNC_REGIONS + bool ForceSynchronousTargetRegions = false; + DeviceTy(GenericPluginTy *RTL, int32_t DeviceID, int32_t RTLDeviceID); // DeviceTy is not copyable @@ -150,6 +160,9 @@ struct DeviceTy { /// Destroy the event. int32_t destroyEvent(void *Event); + + void setTeamProcs(int32_t num_team_procs) { TeamProcs = num_team_procs; } + int32_t getTeamProcs() { return TeamProcs; } /// } /// Print all offload entries to stderr. @@ -158,6 +171,19 @@ struct DeviceTy { /// Ask the device whether the runtime should use auto zero-copy. bool useAutoZeroCopy(); + /// Ask the device whether it is an APU. + bool checkIfAPU(); + + bool checkIfGFX90a(); + + bool checkIfMI300x(); + + /// Ask the device whether it supports unified memory. + bool supportsUnifiedMemory(); + + /// Ask the device to perform sanity checks for zero-copy configurations. + void zeroCopySanityChecksAndDiag(bool isUnifiedSharedMemory, + bool isAutoZeroCopy, bool isEagerMaps); /// Ask the device whether the storage is accessible. bool isAccessiblePtr(const void *Ptr, size_t Size); @@ -167,6 +193,12 @@ struct DeviceTy { /// Indicate that there are pending images for this device or not. void setHasPendingImages(bool V) { HasPendingImages = V; } + /// Get number of devices used for multi-device kernels + uint32_t getNumMultiDevices() const; + + /// Check if the kernel is multi device + bool isMultiDeviceKernel(void *TgtEntryPtr); + private: /// Deinitialize the device (and plugin). void deinit(); diff --git a/offload/include/omptarget.h b/offload/include/omptarget.h index 89aa468689eaf..6ab0c54738c0d 100644 --- a/offload/include/omptarget.h +++ b/offload/include/omptarget.h @@ -33,6 +33,8 @@ #define OFFLOAD_DEVICE_DEFAULT -1 +#define HOST_DEVICE -10 + /// return flags of __tgt_target_XXX public APIs enum __tgt_target_return_t : int { /// successful offload executed on a target device @@ -77,9 +79,11 @@ enum tgt_map_type { // the structured region // This is an OpenMP extension for the sake of OpenACC support. OMP_TGT_MAPTYPE_OMPX_HOLD = 0x2000, + // mapping is for a descriptor (a.k.a. dope vector) + OMP_TGT_MAPTYPE_DESCRIPTOR = 0x4000, // Attach pointer and pointee, after processing all other maps. // Applicable to map-entering directives. Does not change ref-count. - OMP_TGT_MAPTYPE_ATTACH = 0x4000, + OMP_TGT_MAPTYPE_ATTACH = 0x8000, // descriptor for non-contiguous target-update OMP_TGT_MAPTYPE_NON_CONTIG = 0x100000000000, // member of struct, member given by [16 MSBs] - 1 @@ -271,6 +275,7 @@ struct __tgt_target_non_contig { extern "C" { #endif +int ompx_get_team_procs(int device_num); void ompx_dump_mapping_tables(void); int omp_get_num_devices(void); int omp_get_device_num(void); @@ -295,6 +300,8 @@ int omp_target_disassociate_ptr(const void *HostPtr, int DeviceNum); /// Explicit target memory allocators /// Using the llvm_ prefix until they become part of the OpenMP standard. +void *llvm_omp_target_lock_mem(void *ptr, size_t size, int device_num); +void llvm_omp_target_unlock_mem(void *ptr, int device_num); void *llvm_omp_target_alloc_device(size_t Size, int DeviceNum); void *llvm_omp_target_alloc_host(size_t Size, int DeviceNum); void *llvm_omp_target_alloc_shared(size_t Size, int DeviceNum); diff --git a/offload/liboffload/CMakeLists.txt b/offload/liboffload/CMakeLists.txt index 62480dad1cac8..efb800f2495f9 100644 --- a/offload/liboffload/CMakeLists.txt +++ b/offload/liboffload/CMakeLists.txt @@ -18,8 +18,8 @@ foreach(plugin IN LISTS LIBOMPTARGET_PLUGINS_TO_BUILD) target_link_libraries(LLVMOffload PRIVATE omptarget.rtl.${plugin}) endforeach() -if(LLVM_HAVE_LINK_VERSION_SCRIPT) - target_link_libraries(LLVMOffload PRIVATE "-Wl,--version-script=${CMAKE_CURRENT_SOURCE_DIR}/exports") +if(LIBOMP_HAVE_VERSION_SCRIPT_FLAG) + target_link_libraries(LLVMOffload PRIVATE "-Wl,--version-script=${CMAKE_CURRENT_SOURCE_DIR}/exports") endif() target_include_directories(LLVMOffload PUBLIC diff --git a/offload/libomptarget/CMakeLists.txt b/offload/libomptarget/CMakeLists.txt index 93e684e53bf17..7e632306de9bd 100644 --- a/offload/libomptarget/CMakeLists.txt +++ b/offload/libomptarget/CMakeLists.txt @@ -21,6 +21,8 @@ add_llvm_library(omptarget OpenMP/Mapping.cpp OpenMP/InteropAPI.cpp OpenMP/OMPT/Callback.cpp + OpenMP/OMPT/OmptTracing.cpp + OpenMP/OMPT/OmptTracingBuffer.cpp KernelLanguage/API.cpp @@ -44,10 +46,33 @@ target_include_directories(omptarget PRIVATE ${LIBOMPTARGET_INCLUDE_DIR} ${LIBOMPTARGET_BINARY_INCLUDE_DIR} ) -if(LLVM_HAVE_LINK_VERSION_SCRIPT) - target_link_libraries(omptarget PRIVATE "-Wl,--version-script=${CMAKE_CURRENT_SOURCE_DIR}/exports") +if (LIBOMP_HAVE_VERSION_SCRIPT_FLAG) + target_link_libraries(omptarget PRIVATE + "-Wl,--version-script=${CMAKE_CURRENT_SOURCE_DIR}/exports") endif() +# Don't override an externally defined RPATH +if(NOT DEFINED CMAKE_INSTALL_RPATH) + set_target_properties(omptarget PROPERTIES INSTALL_RPATH "$ORIGIN:$ORIGIN/../lib:$ORIGIN/../../lib" BUILD_RPATH "$ORIGIN") +else() + set_target_properties(omptarget PROPERTIES INSTALL_RPATH ${CMAKE_INSTALL_RPATH} BUILD_RPATH ${CMAKE_INSTALL_RPATH}) +endif() +if (OPENMP_ENABLE_LIBOMPTARGET_PROFILING) + # Add LLVMSupport dependency if profiling is enabled. + # Linking with LLVM component libraries also requires + # aligning the compile flags. + llvm_update_compile_flags(omptarget) + target_compile_definitions(omptarget PUBLIC OMPTARGET_PROFILE_ENABLED) + target_link_libraries(omptarget PRIVATE LLVMSupport) +endif() + +target_include_directories(omptarget PRIVATE ${LIBOMPTARGET_INCLUDE_DIR}) + +target_link_libraries( + omptarget + PRIVATE + ${CMAKE_DL_LIBS} + "-Wl,--no-allow-shlib-undefined") # Define the TARGET_NAME and DEBUG_PREFIX. target_compile_definitions(omptarget PRIVATE TARGET_NAME=omptarget @@ -60,11 +85,99 @@ endforeach() target_compile_options(omptarget PRIVATE ${offload_compile_flags}) target_link_options(omptarget PRIVATE ${offload_link_flags}) +if (OMPT_TARGET_DEFAULT AND LIBOMPTARGET_OMPT_SUPPORT) + target_link_libraries(omptarget PRIVATE PluginOmpt) +endif() + +macro(check_plugin_target target) +if (TARGET omptarget.rtl.${target}) + list(APPEND LIBOMPTARGET_PLUGINS_TO_LOAD ${target}) +endif() +endmacro() + +set(LIBOMPTARGET_PLUGINS_TO_LOAD "" CACHE STRING + "Comma separated list of plugin names to look for at runtime") +if (NOT LIBOMPTARGET_PLUGINS_TO_LOAD) + check_plugin_target(amdgpu) + check_plugin_target(host) + check_plugin_target(cuda) +endif() + +list(TRANSFORM LIBOMPTARGET_PLUGINS_TO_LOAD PREPEND "\"libomptarget.rtl.") +list(TRANSFORM LIBOMPTARGET_PLUGINS_TO_LOAD APPEND "\"") +list(JOIN LIBOMPTARGET_PLUGINS_TO_LOAD "," ENABLED_OFFLOAD_PLUGINS) +target_compile_definitions(omptarget PRIVATE ENABLED_OFFLOAD_PLUGINS=${ENABLED_OFFLOAD_PLUGINS}) + +if(NOT DEFINED CMAKE_INSTALL_RPATH) + set_target_properties(omptarget PROPERTIES INSTALL_RPATH "$ORIGIN") +endif() + # libomptarget.so needs to be aware of where the plugins live as they # are now separated in the build directory. set_target_properties(omptarget PROPERTIES POSITION_INDEPENDENT_CODE ON - INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/..") install(TARGETS omptarget LIBRARY COMPONENT omptarget DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") + +#=============================================================================== +# Ensure that omptarget does not contain a mixture of static and dynamically +# linked LLVM libs. +#=============================================================================== +if (LLVM_LINK_LLVM_DYLIB) + if(LLVM_AVAILABLE_LIBS) + set(llvm_libs ${LLVM_AVAILABLE_LIBS}) + else() + # Inside LLVM itself available libs are in a global property. + get_property(llvm_libs GLOBAL PROPERTY LLVM_LIBS) + endif() + + #----------------------------------------------------------------------------- + # Helper function to recursively get the llvm targets that 'tgt' links against + #----------------------------------------------------------------------------- + function(get_llvm_link_targets var tgt visited) + if(${tgt} IN_LIST visited) + return() + endif() + list(APPEND visited ${tgt}) + + get_target_property(link_libs ${tgt} LINK_LIBRARIES) + if(NOT link_libs) + set(link_libs "") + endif() + get_target_property(i_link_libs ${tgt} INTERFACE_LINK_LIBRARIES) + if(i_link_libs) + list(APPEND link_libs ${i_link_libs}) + endif() + if(NOT link_libs) + return() + endif() + list(REMOVE_DUPLICATES link_libs) + + foreach(lib ${link_libs}) + if(${lib} IN_LIST llvm_libs) + list(APPEND rv ${lib}) + endif() + if(TARGET ${lib}) + get_llvm_link_targets(indirect ${lib} visited) + list(APPEND rv ${indirect}) + list(REMOVE_DUPLICATES rv) + endif() + endforeach() + + set(${var} ${rv} PARENT_SCOPE) + endfunction() + + #----------------------------------------------------------------------------- + # Check for extraneous libs + #----------------------------------------------------------------------------- + get_llvm_link_targets(llvm_link_targets omptarget "") + list(REMOVE_ITEM llvm_link_targets "LLVM") + if(llvm_link_targets) + list(JOIN llvm_link_targets " " pp_list) + message( + FATAL_ERROR + "'omptarget' should only link against 'LLVM' when 'LLVM_LINK_LLVM_DYLIB' " + "is on. Extraneous LLVM Libraries: ${pp_list}") + endif() +endif() diff --git a/offload/libomptarget/LegacyAPI.cpp b/offload/libomptarget/LegacyAPI.cpp index 033d7a3ef712a..a788f7c2087e8 100644 --- a/offload/libomptarget/LegacyAPI.cpp +++ b/offload/libomptarget/LegacyAPI.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "OpenMP/OMPT/Interface.h" +#include "OpenMP/OMPT/OmptCommonDefs.h" #include "omptarget.h" #include "private.h" @@ -180,6 +181,10 @@ EXTERN int __tgt_target_teams_nowait_mapper( EXTERN void __kmpc_push_target_tripcount_mapper(ident_t *Loc, int64_t DeviceId, uint64_t LoopTripcount) { TIMESCOPE_WITH_IDENT(Loc); + if (checkDevice(DeviceId, Loc)) { + DP("Not offloading to device %" PRId64 "\n", DeviceId); + return; + } DP("WARNING: __kmpc_push_target_tripcount has been deprecated and is a noop"); } diff --git a/offload/libomptarget/OpenMP/API.cpp b/offload/libomptarget/OpenMP/API.cpp index dd83a3ccd08e6..e8e2c408ab169 100644 --- a/offload/libomptarget/OpenMP/API.cpp +++ b/offload/libomptarget/OpenMP/API.cpp @@ -10,6 +10,7 @@ // //===----------------------------------------------------------------------===// +#include "OpenMP/OMPT/OmptCommonDefs.h" #include "PluginManager.h" #include "device.h" #include "omptarget.h" @@ -29,6 +30,16 @@ #include #include +EXTERN int ompx_get_team_procs(int DeviceNum) { + TIMESCOPE(); + auto DeviceOrErr = PM->getDevice(DeviceNum); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceNum, "%s", toString(DeviceOrErr.takeError()).c_str()); + int TeamProcs = DeviceOrErr->getTeamProcs(); + DP("Call to ompx_get_team_procs returning %d\n", TeamProcs); + return TeamProcs; +} + EXTERN void ompx_dump_mapping_tables() { ident_t Loc = {0, 0, 0, 0, ";libomptarget;libomptarget;0;0;;"}; auto ExclusiveDevicesAccessor = PM->getExclusiveDevicesAccessor(); @@ -58,12 +69,12 @@ EXTERN int omp_get_num_devices(void) { return NumDevices; } -EXTERN int omp_get_device_num(void) { +EXTERN int omp_get_DeviceNum(void) { TIMESCOPE(); OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); int HostDevice = omp_get_initial_device(); - DP("Call to omp_get_device_num returning %d\n", HostDevice); + DP("Call to omp_get_DeviceNum returning %d\n", HostDevice); return HostDevice; } @@ -98,6 +109,25 @@ EXTERN void *llvm_omp_target_alloc_shared(size_t Size, int DeviceNum) { return targetAllocExplicit(Size, DeviceNum, TARGET_ALLOC_SHARED, __func__); } +EXTERN void *llvm_omp_target_alloc_multi_devices(size_t size, int num_devices, + int DeviceNums[]) { + if (num_devices < 1) + return nullptr; + + DeviceTy &Device = *PM->getDevice(DeviceNums[0]); + if (!Device.RTL->is_system_supporting_managed_memory(Device.DeviceID)) + return nullptr; + + // disregard device ids for now and allocate shared memory that can be + // accessed by any device and host under xnack+ mode + void *ptr = + targetAllocExplicit(size, DeviceNums[0], TARGET_ALLOC_DEFAULT, __func__); + // TODO: not implemented yet + // if (Device.RTL->enable_access_to_all_agents) + // Device.RTL->enable_access_to_all_agents(DeviceNums[0], ptr); + return ptr; +} + EXTERN void omp_target_free(void *Ptr, int DeviceNum) { TIMESCOPE(); OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); @@ -585,7 +615,7 @@ EXTERN int omp_target_associate_ptr(const void *HostPtr, const void *DevicePtr, TIMESCOPE(); OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); DP("Call to omp_target_associate_ptr with host_ptr " DPxMOD ", " - "device_ptr " DPxMOD ", size %zu, device_offset %zu, device_num %d\n", + "device_ptr " DPxMOD ", size %zu, device_offset %zu, DeviceNum %d\n", DPxPTR(HostPtr), DPxPTR(DevicePtr), Size, DeviceOffset, DeviceNum); if (!HostPtr || !DevicePtr || Size <= 0) { @@ -619,7 +649,7 @@ EXTERN int omp_target_disassociate_ptr(const void *HostPtr, int DeviceNum) { TIMESCOPE(); OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); DP("Call to omp_target_disassociate_ptr with host_ptr " DPxMOD ", " - "device_num %d\n", + "DeviceNum %d\n", DPxPTR(HostPtr), DeviceNum); if (!HostPtr) { @@ -648,10 +678,45 @@ EXTERN int omp_target_disassociate_ptr(const void *HostPtr, int DeviceNum) { return Rc; } +EXTERN int omp_is_coarse_grain_mem_region(void *ptr, size_t size) { + if (!(PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY)) + return 0; + auto DeviceOrErr = PM->getDevice(omp_get_default_device()); + if (!DeviceOrErr) + FATAL_MESSAGE(omp_get_default_device(), "%s", + toString(DeviceOrErr.takeError()).c_str()); + + return DeviceOrErr->RTL->query_coarse_grain_mem_region( + omp_get_default_device(), ptr, size); +} + +// This user-callable function allows host overlays of HIP mem alloc functions +// to register memory as coarse grain in the openmp runtime. This will +// prevent duplicate HSA memory registration when OpenMP sees same memory +// in map clauses. +EXTERN void omp_register_coarse_grain_mem(void *ptr, size_t size, int setattr) { + if (!(PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY)) + return; + auto DeviceOrErr = PM->getDevice(omp_get_default_device()); + if (!DeviceOrErr) + FATAL_MESSAGE(omp_get_default_device(), "%s", + toString(DeviceOrErr.takeError()).c_str()); + + if (!(DeviceOrErr->RTL->is_gfx90a(omp_get_default_device()) && + DeviceOrErr->RTL->is_gfx90a_coarse_grain_usm_map_enabled( + omp_get_default_device()))) + return; + + bool set_attr = (setattr == 1) ? true : false; + DeviceOrErr->RTL->set_coarse_grain_mem(omp_get_default_device(), ptr, size, + set_attr); + return; +} + EXTERN void *omp_get_mapped_ptr(const void *Ptr, int DeviceNum) { TIMESCOPE(); OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); - DP("Call to omp_get_mapped_ptr with ptr " DPxMOD ", device_num %d.\n", + DP("Call to omp_get_mapped_ptr with ptr " DPxMOD ", DeviceNum %d.\n", DPxPTR(Ptr), DeviceNum); if (!Ptr) { diff --git a/offload/libomptarget/OpenMP/Mapping.cpp b/offload/libomptarget/OpenMP/Mapping.cpp index 9b3533895f2a6..75e64837f4886 100644 --- a/offload/libomptarget/OpenMP/Mapping.cpp +++ b/offload/libomptarget/OpenMP/Mapping.cpp @@ -77,7 +77,9 @@ int MappingInfoTy::associatePtr(void *HstPtrBegin, void *TgtPtrBegin, /*HstPtrEnd=*/(uintptr_t)HstPtrBegin + Size, /*TgtAllocBegin=*/(uintptr_t)TgtPtrBegin, /*TgtPtrBegin=*/(uintptr_t)TgtPtrBegin, - /*UseHoldRefCount=*/false, /*Name=*/nullptr, + /*UseHoldRefCount=*/false, + /*AllocKind=*/TARGET_ALLOC_DEFAULT, + /*Name=*/nullptr, /*IsRefCountINF=*/true)) .first->HDTT; DP("Creating new map entry: HstBase=" DPxMOD ", HstBegin=" DPxMOD @@ -199,10 +201,11 @@ LookupResult MappingInfoTy::lookupMapping(HDTTMapAccessorTy &HDTTMap, TargetPointerResultTy MappingInfoTy::getTargetPointer( HDTTMapAccessorTy &HDTTMap, void *HstPtrBegin, void *HstPtrBase, - int64_t TgtPadding, int64_t Size, map_var_info_t HstPtrName, bool HasFlagTo, - bool HasFlagAlways, bool IsImplicit, bool UpdateRefCount, - bool HasCloseModifier, bool HasPresentModifier, bool HasHoldModifier, - AsyncInfoTy &AsyncInfo, HostDataToTargetTy *OwnedTPR, bool ReleaseHDTTMap) { + int64_t TgtPadding, int64_t Size, int64_t TypeFlags, + map_var_info_t HstPtrName, bool HasFlagTo, bool HasFlagAlways, + bool IsImplicit, bool UpdateRefCount, bool HasCloseModifier, + bool HasPresentModifier, bool HasHoldModifier, AsyncInfoTy &AsyncInfo, + HostDataToTargetTy *OwnedTPR, bool ReleaseHDTTMap) { LookupResult LR = lookupMapping(HDTTMap, HstPtrBegin, Size, OwnedTPR); LR.TPR.Flags.IsPresent = true; @@ -254,28 +257,49 @@ TargetPointerResultTy MappingInfoTy::getTargetPointer( MESSAGE("device mapping required by 'present' map type modifier does not " "exist for host address " DPxMOD " (%" PRId64 " bytes)", DPxPTR(HstPtrBegin), Size); - } else if ((PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY && - !HasCloseModifier) || - (PM->getRequirements() & OMPX_REQ_AUTO_ZERO_COPY)) { - - // If unified shared memory is active, implicitly mapped variables that are - // not privatized use host address. Any explicitly mapped variables also use - // host address where correctness is not impeded. In all other cases maps - // are respected. - // In addition to the mapping rules above, the close map modifier forces the - // mapping of the variable to the device. + } else if (((PM->getRequirements() & OMPX_REQ_AUTO_ZERO_COPY) || + (PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY)) && + (!HasCloseModifier)) { + // If unified shared memory is active, implicitly mapped variables that + // are not privatized use host address. Any explicitly mapped variables + // also use host address where correctness is not impeded. In all other + // cases maps are respected. In addition to the mapping rules above, the + // close map modifier forces the mapping of the variable to the device. if (Size) { - INFO(OMP_INFOTYPE_MAPPING_CHANGED, Device.DeviceID, - "Return HstPtrBegin " DPxMOD " Size=%" PRId64 " for unified shared " - "memory\n", - DPxPTR((uintptr_t)HstPtrBegin), Size); - DP("Return HstPtrBegin " DPxMOD " Size=%" PRId64 " for unified shared " + // For MI200, when allocating under unified_shared_memory, amdgpu plugin + // can optimize memory access latency by registering allocated + // memory as coarse-grained. The usage of coarse-grained memory can be + // overriden by setting the env-var OMPX_DISABLE_USM_MAPS=1. + if (Device.RTL->is_gfx90a(Device.DeviceID) && HstPtrBegin && + Device.RTL->is_gfx90a_coarse_grain_usm_map_enabled(Device.DeviceID)) { + Device.RTL->set_coarse_grain_mem_region(Device.DeviceID, HstPtrBegin, + Size); + INFO(OMP_INFOTYPE_MAPPING_CHANGED, Device.DeviceID, + "Memory pages for HstPtrBegin " DPxMOD " Size=%" PRId64 + " switched to coarse grain\n", + DPxPTR((uintptr_t)HstPtrBegin), Size); + } + + // If we are here, it means that we are either in auto zero-copy or USM. + // Enable GPU page table prefaulting if selected by the user. This feature + // is only enabled for APUs. + if (PM->getRequirements() & OMPX_REQ_EAGER_ZERO_COPY_MAPS) { + Device.RTL->prepopulate_page_table(Device.DeviceID, HstPtrBegin, Size); + INFO(OMP_INFOTYPE_MAPPING_CHANGED, Device.DeviceID, + "Prefaulted " DPxMOD " Size=%" PRId64 " on GPU page table\n", + DPxPTR((uintptr_t)HstPtrBegin), Size); + } + } + INFO(OMP_INFOTYPE_MAPPING_CHANGED, Device.DeviceID, + "Return HstPtrBegin " DPxMOD " Size=%" PRId64 " for unified shared " "memory\n", DPxPTR((uintptr_t)HstPtrBegin), Size); - LR.TPR.Flags.IsPresent = false; - LR.TPR.Flags.IsHostPointer = true; - LR.TPR.TargetPointer = HstPtrBegin; - } + DP("Return HstPtrBegin " DPxMOD " Size=%" PRId64 " for unified shared " + "memory\n", + DPxPTR((uintptr_t)HstPtrBegin), Size); + LR.TPR.Flags.IsPresent = false; + LR.TPR.Flags.IsHostPointer = true; + LR.TPR.TargetPointer = HstPtrBegin; } else if (HasPresentModifier) { DP("Mapping required by 'present' map type modifier does not exist for " "HstPtrBegin=" DPxMOD ", Size=%" PRId64 "\n", @@ -286,17 +310,28 @@ TargetPointerResultTy MappingInfoTy::getTargetPointer( } else if (Size) { // If it is not contained and Size > 0, we should create a new entry for it. LR.TPR.Flags.IsNewEntry = true; + + int32_t AllocKind = TARGET_ALLOC_DEFAULT; + + if (TypeFlags == OMP_TGT_MAPTYPE_DESCRIPTOR && + Device.RTL->use_shared_mem_for_descriptor(Device.DeviceID, Size)) { + AllocKind = TARGET_ALLOC_SHARED; + INFO(OMP_INFOTYPE_MAPPING_CHANGED, Device.DeviceID, + "Using shared memory for descriptor allocation of size=%zu\n", Size); + } + uintptr_t TgtAllocBegin = - (uintptr_t)Device.allocData(TgtPadding + Size, HstPtrBegin); + (uintptr_t)Device.allocData(TgtPadding + Size, HstPtrBegin, AllocKind); uintptr_t TgtPtrBegin = TgtAllocBegin + TgtPadding; // Release the mapping table lock only after the entry is locked by // attaching it to TPR. - LR.TPR.setEntry(HDTTMap - ->emplace(new HostDataToTargetTy( - (uintptr_t)HstPtrBase, (uintptr_t)HstPtrBegin, - (uintptr_t)HstPtrBegin + Size, TgtAllocBegin, - TgtPtrBegin, HasHoldModifier, HstPtrName)) - .first->HDTT); + LR.TPR.setEntry( + HDTTMap + ->emplace(new HostDataToTargetTy( + (uintptr_t)HstPtrBase, (uintptr_t)HstPtrBegin, + (uintptr_t)HstPtrBegin + Size, TgtAllocBegin, TgtPtrBegin, + HasHoldModifier, AllocKind, HstPtrName)) + .first->HDTT); INFO(OMP_INFOTYPE_MAPPING_CHANGED, Device.DeviceID, "Creating new map entry with HstPtrBase=" DPxMOD ", HstPtrBegin=" DPxMOD ", TgtAllocBegin=" DPxMOD @@ -351,17 +386,25 @@ TargetPointerResultTy MappingInfoTy::getTargetPointer( DP("Moving %" PRId64 " bytes (hst:" DPxMOD ") -> (tgt:" DPxMOD ")\n", Size, DPxPTR(HstPtrBegin), DPxPTR(LR.TPR.TargetPointer)); - int Ret = Device.submitData(LR.TPR.TargetPointer, HstPtrBegin, Size, - AsyncInfo, LR.TPR.getEntry()); - if (Ret != OFFLOAD_SUCCESS) { - REPORT("Copying data to device failed.\n"); - // We will also return nullptr if the data movement fails because that - // pointer points to a corrupted memory region so it doesn't make any - // sense to continue to use it. - LR.TPR.TargetPointer = nullptr; - } else if (LR.TPR.getEntry()->addEventIfNecessary(Device, AsyncInfo) != - OFFLOAD_SUCCESS) - return TargetPointerResultTy{}; + if (LR.TPR.Flags.IsNewEntry || + LR.TPR.getEntry()->AllocKind != TARGET_ALLOC_SHARED) { + + DP("Moving %" PRId64 " bytes (hst:" DPxMOD ") -> (tgt:" DPxMOD ")\n", + Size, DPxPTR(HstPtrBegin), DPxPTR(LR.TPR.TargetPointer)); + + int Ret = Device.submitData(LR.TPR.TargetPointer, HstPtrBegin, Size, + AsyncInfo, LR.TPR.getEntry()); + if (Ret != OFFLOAD_SUCCESS) { + REPORT("Copying data to device failed.\n"); + // We will also return nullptr if the data movement fails because that + // pointer points to a corrupted memory region so it doesn't make any + // sense to continue to use it. + LR.TPR.TargetPointer = nullptr; + } else if (LR.TPR.getEntry()->addEventIfNecessary(Device, AsyncInfo) != + OFFLOAD_SUCCESS) + return TargetPointerResultTy{}; + } + } else { // If not a host pointer and no present modifier, we need to wait for the // event if it exists. @@ -393,8 +436,9 @@ TargetPointerResultTy MappingInfoTy::getTgtPtrBegin( LR.TPR.Flags.IsPresent = true; - if (LR.Flags.IsContained || - (!MustContain && (LR.Flags.ExtendsBefore || LR.Flags.ExtendsAfter))) { + if ((LR.Flags.IsContained || + (!MustContain && (LR.Flags.ExtendsBefore || LR.Flags.ExtendsAfter)))) { + LR.TPR.Flags.IsLast = LR.TPR.getEntry()->decShouldRemove(UseHoldRefCount, ForceDelete); @@ -439,7 +483,7 @@ TargetPointerResultTy MappingInfoTy::getTgtPtrBegin( LR.TPR.getEntry()->dynRefCountToStr().c_str(), DynRefCountAction, LR.TPR.getEntry()->holdRefCountToStr().c_str(), HoldRefCountAction); LR.TPR.TargetPointer = (void *)TP; - } else if (PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY || + } else if ((PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY) || PM->getRequirements() & OMPX_REQ_AUTO_ZERO_COPY) { // If the value isn't found in the mapping and unified shared memory // is on then it means we have stumbled upon a value which we need to diff --git a/offload/libomptarget/OpenMP/OMPT/Callback.cpp b/offload/libomptarget/OpenMP/OMPT/Callback.cpp index ab0942ed4fd3f..766606f82a02a 100644 --- a/offload/libomptarget/OpenMP/OMPT/Callback.cpp +++ b/offload/libomptarget/OpenMP/OMPT/Callback.cpp @@ -12,9 +12,13 @@ #ifdef OMPT_SUPPORT +#include +#include #include #include #include +#include +#include #include "Shared/Debug.h" @@ -23,7 +27,9 @@ #include "OpenMP/OMPT/Interface.h" #include "llvm/Support/DynamicLibrary.h" +#include "llvm/Support/ErrorHandling.h" +#pragma push_macro("DEBUG_PREFIX") #undef DEBUG_PREFIX #define DEBUG_PREFIX "OMPT" @@ -52,6 +58,7 @@ ompt_get_callback_t llvm::omp::target::ompt::lookupCallbackByCode = nullptr; ompt_function_lookup_t llvm::omp::target::ompt::lookupCallbackByName = nullptr; ompt_get_target_task_data_t ompt_get_target_task_data_fn = nullptr; ompt_get_task_data_t ompt_get_task_data_fn = nullptr; +ompt_set_frame_enter_t ompt_set_frame_enter_fn = nullptr; /// Unique correlation id static std::atomic IdCounter(1); @@ -409,6 +416,11 @@ void Interface::endTarget(int64_t DeviceId, void *Code) { endTargetRegion(); } +void Interface::announceTargetRegion(const char *RegionName) { + DP("in Interface::target_region_%s target_id=%lu\n", RegionName, + TargetData.value); +} + void Interface::beginTargetDataOperation() { DP("in ompt_target_region_begin (TargetRegionId = %lu)\n", TargetData.value); } @@ -472,6 +484,7 @@ int llvm::omp::target::ompt::initializeLibrary(ompt_function_lookup_t lookup, bindOmptFunctionName(ompt_get_callback, lookupCallbackByCode); bindOmptFunctionName(ompt_get_task_data, ompt_get_task_data_fn); bindOmptFunctionName(ompt_get_target_task_data, ompt_get_target_task_data_fn); + bindOmptFunctionName(ompt_set_frame_enter, ompt_set_frame_enter_fn); #undef bindOmptFunctionName // Store pointer of 'ompt_libomp_target_fn_lookup' for use by libomptarget @@ -482,6 +495,8 @@ int llvm::omp::target::ompt::initializeLibrary(ompt_function_lookup_t lookup, assert(ompt_get_task_data_fn && "ompt_get_task_data_fn should be non-null"); assert(ompt_get_target_task_data_fn && "ompt_get_target_task_data_fn should be non-null"); + assert(ompt_set_frame_enter_fn && + "ompt_set_frame_enter_fn should be non-null"); assert(LibraryFinalizer == nullptr && "LibraryFinalizer should not be initialized yet"); @@ -528,4 +543,5 @@ void llvm::omp::target::ompt::connectLibrary() { DP("Exiting connectLibrary\n"); } +#pragma pop_macro("DEBUG_PREFIX") #endif // OMPT_SUPPORT diff --git a/offload/libomptarget/OpenMP/OMPT/OmptTracing.cpp b/offload/libomptarget/OpenMP/OMPT/OmptTracing.cpp new file mode 100644 index 0000000000000..ddca8ceaec801 --- /dev/null +++ b/offload/libomptarget/OpenMP/OMPT/OmptTracing.cpp @@ -0,0 +1,877 @@ +//===-- OmptTracing.cpp - Target independent OpenMP target RTL --- C++ -*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Implementation of OMPT tracing interfaces for target independent layer +// +//===----------------------------------------------------------------------===// + +#ifdef OMPT_SUPPORT + +#include "OpenMP/OMPT/OmptTracing.h" +#include "OpenMP/OMPT/Callback.h" +#include "OpenMP/OMPT/Interface.h" +#include "OpenMP/OMPT/OmptTracingBuffer.h" +#include "PluginManager.h" +#include "Shared/Debug.h" +#include "omp-tools.h" + +#include "llvm/Support/DynamicLibrary.h" + +#include +#include +#include +#include +#include +#include +#include + +#pragma push_macro("DEBUG_PREFIX") +#undef DEBUG_PREFIX +#define DEBUG_PREFIX "OMPT" + +using namespace llvm::omp::target::ompt; + +std::mutex llvm::omp::target::ompt::DeviceAccessMutex; +std::mutex llvm::omp::target::ompt::TraceAccessMutex; +std::mutex llvm::omp::target::ompt::TraceControlMutex; +std::mutex llvm::omp::target::ompt::TraceHashThreadMutex; +std::mutex llvm::omp::target::ompt::BufferManagementFnMutex; + +std::unordered_map> + llvm::omp::target::ompt::BufferManagementFns; + +thread_local uint32_t llvm::omp::target::ompt::TraceRecordNumGrantedTeams = 0; +thread_local uint64_t llvm::omp::target::ompt::TraceRecordStartTime = 0; +thread_local uint64_t llvm::omp::target::ompt::TraceRecordStopTime = 0; +thread_local uint64_t llvm::omp::target::ompt::ThreadId = + std::numeric_limits::max(); + +std::map llvm::omp::target::ompt::TracedDevices; + +bool llvm::omp::target::ompt::TracingActive = false; + +void llvm::omp::target::ompt::resetTimestamp(uint64_t *T) { *T = 0; } + +ompt_callback_buffer_request_t +llvm::omp::target::ompt::getBufferRequestFn(int DeviceId) { + std::unique_lock Lock(BufferManagementFnMutex); + auto BufferMgrItr = BufferManagementFns.find(DeviceId); + if (BufferMgrItr == BufferManagementFns.end()) { + return nullptr; + } + return BufferMgrItr->second.first; +} + +ompt_callback_buffer_complete_t +llvm::omp::target::ompt::getBufferCompleteFn(int DeviceId) { + std::unique_lock Lock(BufferManagementFnMutex); + auto BufferMgrItr = BufferManagementFns.find(DeviceId); + if (BufferMgrItr == BufferManagementFns.end()) { + return nullptr; + } + return BufferMgrItr->second.second; +} + +void llvm::omp::target::ompt::setBufferManagementFns( + int DeviceId, ompt_callback_buffer_request_t ReqFn, + ompt_callback_buffer_complete_t CmpltFn) { + std::unique_lock Lock(BufferManagementFnMutex); + auto BufferMgrItr = BufferManagementFns.find(DeviceId); + if (BufferMgrItr != BufferManagementFns.end()) { + REPORT("Buffer request and complete functions already exist for device %d, " + "ignoring ...\n", + DeviceId); + return; + } + BufferManagementFns[DeviceId] = std::make_pair(ReqFn, CmpltFn); +} + +void llvm::omp::target::ompt::removeBufferManagementFns(int DeviceId) { + std::unique_lock Lock(BufferManagementFnMutex); + auto BufferMgrItr = BufferManagementFns.find(DeviceId); + if (BufferMgrItr == BufferManagementFns.end()) { + REPORT("Buffer request and complete functions don't exist for device %d, " + "ignoring ...\n", + DeviceId); + return; + } + BufferManagementFns.erase(BufferMgrItr); +} + +bool llvm::omp::target::ompt::isAllDeviceTracingStopped() { + std::unique_lock Lock(BufferManagementFnMutex); + return BufferManagementFns.empty(); +} + +void llvm::omp::target::ompt::ompt_callback_buffer_request( + int DeviceId, ompt_buffer_t **BufferPtr, size_t *Bytes) { + if (auto Fn = getBufferRequestFn(DeviceId)) + Fn(DeviceId, BufferPtr, Bytes); +} + +void llvm::omp::target::ompt::ompt_callback_buffer_complete( + int DeviceId, ompt_buffer_t *Buffer, size_t Bytes, + ompt_buffer_cursor_t BeginCursor, int BufferOwned) { + if (auto Fn = getBufferCompleteFn(DeviceId)) + Fn(DeviceId, Buffer, Bytes, BeginCursor, BufferOwned); +} + +inline void setDeviceTracing(uint64_t &TracingTypes) { + // Set bit 0 to indicate generally enabled device tracing. + TracingTypes |= 1UL; +} + +inline void resetDeviceTracing(uint64_t &TracingTypes) { + // Reset bit 0 to indicate generally disabled device tracing. + TracingTypes &= ~(1UL); +} + +inline bool checkDeviceTracingState(const uint64_t &TracingTypes) { + // Return state of bit 0 to indicate if device is actively traced. + return TracingTypes & 1UL; +} + +void llvm::omp::target::ompt::enableDeviceTracing(int DeviceId) { + std::unique_lock Lock(DeviceAccessMutex); + auto Device = TracedDevices.find(DeviceId); + if (Device == TracedDevices.end()) { + uint64_t TracingTypes{0}; + setDeviceTracing(TracingTypes); + TracedDevices.emplace(DeviceId, TracingTypes); + } else + setDeviceTracing(Device->second); + // In any case: at least one device is traced + TracingActive = true; +} + +void llvm::omp::target::ompt::disableDeviceTracing(int DeviceId) { + std::unique_lock Lock(DeviceAccessMutex); + auto Device = TracedDevices.find(DeviceId); + if (Device == TracedDevices.end()) { + uint64_t TracingTypes{0}; + resetDeviceTracing(TracingTypes); + TracedDevices.emplace(DeviceId, TracingTypes); + } else + resetDeviceTracing(Device->second); + + // Check for actively traced devices + for (auto &Dev : TracedDevices) + if (checkDeviceTracingState(Dev.second)) + return; + + // If no device is currently traced: set global tracing flag to false + TracingActive = false; +} + +bool llvm::omp::target::ompt::isTracingEnabled(int DeviceId, + unsigned int EventTy) { + return TracingActive && isTracedDevice(DeviceId) && + isTracingTypeGroupEnabled(DeviceId, EventTy); +} + +bool llvm::omp::target::ompt::isTracedDevice(int DeviceId) { + std::unique_lock Lock(DeviceAccessMutex); + auto Device = TracedDevices.find(DeviceId); + if (Device != TracedDevices.end()) + return checkDeviceTracingState(Device->second); + + return false; +} + +bool llvm::omp::target::ompt::isTracingTypeEnabled(int DeviceId, + unsigned int EventTy) { + std::unique_lock Lock(DeviceAccessMutex); + // Make sure we do not shift more than std::numeric_limits::digits + assert(EventTy < 64 && "Shift limit exceeded: EventTy must be less than 64"); + auto Device = TracedDevices.find(DeviceId); + if (Device != TracedDevices.end() && EventTy < 64) + return (Device->second & (1UL << EventTy)); + return false; +} + +bool llvm::omp::target::ompt::isTracingTypeGroupEnabled(int DeviceId, + unsigned int EventTy) { + std::unique_lock Lock(DeviceAccessMutex); + // Make sure we do not shift more than std::numeric_limits::digits + assert(EventTy < 64 && "Shift limit exceeded: EventTy must be less than 64"); + auto Device = TracedDevices.find(DeviceId); + if (Device != TracedDevices.end() && EventTy < 64) { + auto TracedEvents = Device->second; + switch (EventTy) { + case ompt_callbacks_t::ompt_callback_target: + case ompt_callbacks_t::ompt_callback_target_emi: + return ((TracedEvents & (1UL << ompt_callback_target))) || + ((TracedEvents & (1UL << ompt_callback_target_emi))); + case ompt_callbacks_t::ompt_callback_target_data_op: + case ompt_callbacks_t::ompt_callback_target_data_op_emi: + return ((TracedEvents & (1UL << ompt_callback_target_data_op))) || + ((TracedEvents & (1UL << ompt_callback_target_data_op_emi))); + case ompt_callbacks_t::ompt_callback_target_submit: + case ompt_callbacks_t::ompt_callback_target_submit_emi: + return ((TracedEvents & (1UL << ompt_callback_target_submit))) || + ((TracedEvents & (1UL << ompt_callback_target_submit_emi))); + // Special case: EventTy == 0 -> Check all EventTy + case 0: + return ((TracedEvents & (1UL << ompt_callback_target))) || + ((TracedEvents & (1UL << ompt_callback_target_emi))) || + ((TracedEvents & (1UL << ompt_callback_target_data_op))) || + ((TracedEvents & (1UL << ompt_callback_target_data_op_emi))) || + ((TracedEvents & (1UL << ompt_callback_target_submit))) || + ((TracedEvents & (1UL << ompt_callback_target_submit_emi))); + } + } + return false; +} + +void llvm::omp::target::ompt::setTracingTypeEnabled(uint64_t &TracedEventTy, + bool Enable, + unsigned int EventTy) { + // Make sure we do not shift more than std::numeric_limits::digits + assert(EventTy < 64 && "Shift limit exceeded: EventTy must be less than 64"); + if (EventTy < 64) { + if (Enable) + TracedEventTy |= (1UL << EventTy); + else + TracedEventTy &= ~(1UL << EventTy); + } +} + +ompt_set_result_t +llvm::omp::target::ompt::setTraceEventTy(int DeviceId, unsigned int Enable, + unsigned int EventTy) { + if (DeviceId < 0) { + REPORT("Failed to set trace event type for DeviceId=%d\n", DeviceId); + return ompt_set_never; + } + + DP("Executing setTraceEventTy: DeviceId=%d Enable=%d EventTy=%d\n", DeviceId, + Enable, EventTy); + + std::unique_lock Lock(DeviceAccessMutex); + if (TracedDevices.find(DeviceId) == TracedDevices.end()) + TracedDevices.emplace(DeviceId, 0UL); + + auto &TracedEventTy = TracedDevices[DeviceId]; + bool Enabled = Enable > 0; + if (EventTy == 0) { + // Set / reset all supported types + setTracingTypeEnabled(TracedEventTy, Enabled, + ompt_callbacks_t::ompt_callback_target); + setTracingTypeEnabled(TracedEventTy, Enabled, + ompt_callbacks_t::ompt_callback_target_data_op); + setTracingTypeEnabled(TracedEventTy, Enabled, + ompt_callbacks_t::ompt_callback_target_submit); + setTracingTypeEnabled(TracedEventTy, Enabled, + ompt_callbacks_t::ompt_callback_target_emi); + setTracingTypeEnabled(TracedEventTy, Enabled, + ompt_callbacks_t::ompt_callback_target_data_op_emi); + setTracingTypeEnabled(TracedEventTy, Enabled, + ompt_callbacks_t::ompt_callback_target_submit_emi); + + if (Enabled) { + // Event subset is enabled + return ompt_set_sometimes; + } else { + // All events are disabled + return ompt_set_always; + } + } + + switch (EventTy) { + case ompt_callbacks_t::ompt_callback_target: + case ompt_callbacks_t::ompt_callback_target_data_op: + case ompt_callbacks_t::ompt_callback_target_submit: + case ompt_callbacks_t::ompt_callback_target_emi: + case ompt_callbacks_t::ompt_callback_target_data_op_emi: + case ompt_callbacks_t::ompt_callback_target_submit_emi: { + setTracingTypeEnabled(TracedEventTy, Enabled, EventTy); + return ompt_set_always; + } + default: { + if (Enabled) { + // Unimplemented + return ompt_set_never; + } else { + // Always disabled anyways + return ompt_set_always; + } + } + } +} + +uint64_t llvm::omp::target::ompt::getThreadId() { + // Grab the value from thread local storage, if valid. + if (ThreadId != std::numeric_limits::max()) + return ThreadId; + // Otherwise set it, protecting the hash with a lock. + std::unique_lock Lock(TraceHashThreadMutex); + ThreadId = std::hash()(std::this_thread::get_id()); + return ThreadId; +} + +void Interface::setTraceRecordCommon(ompt_record_ompt_t *DataPtr, + ompt_callbacks_t CallbackType) { + DataPtr->type = CallbackType; + + if (CallbackType == ompt_callback_target) + DataPtr->time = 0; // Currently, no consumer, so no need to set it + else { + DataPtr->time = TraceRecordStartTime; + resetTimestamp(&TraceRecordStartTime); + } + + DataPtr->thread_id = getThreadId(); + DataPtr->target_id = TargetData.value; +} + +void Interface::setTraceRecordTargetDataOp(ompt_record_target_data_op_t *Record, + ompt_target_data_op_t DataOpType, + void *SrcAddr, int64_t SrcDeviceNum, + void *DstAddr, int64_t DstDeviceNum, + size_t Bytes, void *CodePtr) { + Record->host_op_id = HostOpId; + Record->optype = DataOpType; + Record->src_addr = SrcAddr; + Record->src_device_num = SrcDeviceNum; + Record->dest_addr = DstAddr; + Record->dest_device_num = DstDeviceNum; + Record->bytes = Bytes; + + Record->end_time = TraceRecordStopTime; + resetTimestamp(&TraceRecordStopTime); + + Record->codeptr_ra = CodePtr; +} + +void Interface::setTraceRecordTargetKernel(ompt_record_target_kernel_t *Record, + unsigned int NumTeams) { + Record->host_op_id = HostOpId; + Record->requested_num_teams = NumTeams; + Record->granted_num_teams = TraceRecordNumGrantedTeams; + + Record->end_time = TraceRecordStopTime; + resetTimestamp(&TraceRecordStopTime); +} + +void Interface::setTraceRecordTarget(ompt_record_target_t *Record, + int64_t DeviceId, ompt_target_t TargetKind, + ompt_scope_endpoint_t Endpoint, + void *CodePtr) { + Record->kind = TargetKind; + Record->endpoint = Endpoint; + Record->device_num = DeviceId; + assert(TaskData); + Record->task_id = TaskData->value; + Record->target_id = TargetData.value; + Record->codeptr_ra = CodePtr; +} + +void Interface::startTargetDataAllocTrace(int64_t DeviceId, void *HstPtrBegin, + void **TgtPtrBegin, size_t Size, + void *Code) {} + +ompt_record_ompt_t *Interface::stopTargetDataAllocTrace(int64_t DeviceId, + void *HstPtrBegin, + void **TgtPtrBegin, + size_t Size, + void *Code) { + if (!isTracingEnabled(DeviceId, ompt_callback_target_data_op)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = (ompt_record_ompt_t *)TRM->assignCursor( + ompt_callback_target_data_op, DeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target_data_op); + setTraceRecordTargetDataOp(&DataPtr->record.target_data_op, + ompt_target_data_alloc, HstPtrBegin, + /*SrcDeviceNum=*/omp_get_initial_device(), + *TgtPtrBegin, DeviceId, Size, Code); + + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("Generated trace record: %p (ompt_target_data_alloc)\n", DataPtr); + return DataPtr; +} + +void Interface::startTargetDataDeleteTrace(int64_t DeviceId, void *TgtPtrBegin, + void *Code) {} + +ompt_record_ompt_t *Interface::stopTargetDataDeleteTrace(int64_t DeviceId, + void *TgtPtrBegin, + void *Code) { + if (!isTracingEnabled(DeviceId, ompt_callback_target_data_op)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = (ompt_record_ompt_t *)TRM->assignCursor( + ompt_callback_target_data_op, DeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target_data_op); + setTraceRecordTargetDataOp(&DataPtr->record.target_data_op, + ompt_target_data_delete, TgtPtrBegin, DeviceId, + /*DstAddr=*/nullptr, + /*DstDeviceNum=*/-1, /*Bytes=*/0, Code); + + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("Generated trace record: %p (ompt_target_data_delete)\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t * +Interface::startTargetDataSubmitTrace(int64_t SrcDeviceId, void *SrcPtrBegin, + int64_t DstDeviceId, void *DstPtrBegin, + size_t Size, void *Code) { + if (!isTracingEnabled(DstDeviceId, ompt_callback_target_data_op)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = (ompt_record_ompt_t *)TRM->assignCursor( + ompt_callback_target_data_op, DstDeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target_data_op); + DataPtr->time = 0; // Set to sanity value and let "stop" function fix it + + // Set some of the data-op specific fields here + setTraceRecordTargetDataOp(&DataPtr->record.target_data_op, + ompt_target_data_transfer_to_device, SrcPtrBegin, + SrcDeviceId, DstPtrBegin, DstDeviceId, Size, Code); + + DP("OMPT-Async: Returning data trace record buf ptr %p\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t * +Interface::startTargetDataRetrieveTrace(int64_t SrcDeviceId, void *SrcPtrBegin, + int64_t DstDeviceId, void *DstPtrBegin, + size_t Size, void *Code) { + if (!isTracingEnabled(SrcDeviceId, ompt_callback_target_data_op)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = (ompt_record_ompt_t *)TRM->assignCursor( + ompt_callback_target_data_op, SrcDeviceId); + + if (!DataPtr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target_data_op); + DataPtr->time = 0; // Set to sanity value and let "stop" function fix it + + // Set some of the data-op specific fields here + setTraceRecordTargetDataOp(&DataPtr->record.target_data_op, + ompt_target_data_transfer_from_device, SrcPtrBegin, + SrcDeviceId, DstPtrBegin, DstDeviceId, Size, Code); + + DP("OMPT-Async: Returning data trace record buf ptr %p\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t *Interface::stopTargetDataMovementTraceAsync( + ompt_record_ompt_t *DataPtr, uint64_t NanosStart, uint64_t NanosEnd) { + // Finalize the data that comes from the plugin. + DataPtr->time = NanosStart; + auto Record = static_cast( + &DataPtr->record.target_data_op); + Record->end_time = NanosEnd; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("OMPT-Async: Completed target_data trace record %p\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t *Interface::startTargetSubmitTrace(int64_t DeviceId, + unsigned int NumTeams) { + if (!isTracingEnabled(DeviceId, ompt_callback_target_submit)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = (ompt_record_ompt_t *)TRM->assignCursor( + ompt_callback_target_submit, DeviceId); + + // Set all known entries and leave remaining to the stop function + setTraceRecordCommon(DataPtr, ompt_callback_target_submit); + DataPtr->time = 0; // Set to sanity value and let "stop" function fix it + // Kernel specific things + DataPtr->record.target_kernel.requested_num_teams = NumTeams; + DataPtr->record.target_kernel.host_op_id = getHostOpId(); + + // May be null if event is not traced + DP("OMPT-Async: Returning kernel trace record buf ptr %p\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t * +Interface::stopTargetSubmitTraceAsync(ompt_record_ompt_t *DataPtr, + unsigned int NumTeams, + uint64_t NanosStart, uint64_t NanosStop) { + // Common fields + DataPtr->time = NanosStart; + // Submit specific + DataPtr->record.target_kernel.end_time = NanosStop; + DataPtr->record.target_kernel.granted_num_teams = NumTeams; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + // Ready Record + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("OMPT-Async: Completed trace record buf ptr %p\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t *Interface::startTargetDataEnterTrace(int64_t DeviceId, + void *CodePtr) { + if (!isTracingEnabled(DeviceId, ompt_callback_target)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = + (ompt_record_ompt_t *)TRM->assignCursor(ompt_callback_target, DeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target); + setTraceRecordTarget(&DataPtr->record.target, DeviceId, + ompt_target_enter_data, ompt_scope_begin, CodePtr); + + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("Returning trace record buf ptr: %p (ompt_target_enter_data)\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t *Interface::stopTargetDataEnterTrace(int64_t DeviceId, + void *CodePtr) { + if (!isTracingEnabled(DeviceId, ompt_callback_target)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = + (ompt_record_ompt_t *)TRM->assignCursor(ompt_callback_target, DeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target); + setTraceRecordTarget(&DataPtr->record.target, DeviceId, + ompt_target_enter_data, ompt_scope_end, CodePtr); + + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("Generated trace record: %p (ompt_target_enter_data)\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t *Interface::startTargetDataExitTrace(int64_t DeviceId, + void *CodePtr) { + if (!isTracingEnabled(DeviceId, ompt_callback_target)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = + (ompt_record_ompt_t *)TRM->assignCursor(ompt_callback_target, DeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target); + setTraceRecordTarget(&DataPtr->record.target, DeviceId, ompt_target_exit_data, + ompt_scope_begin, CodePtr); + + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("Returning trace record buf ptr: %p (ompt_target_exit_data)\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t *Interface::stopTargetDataExitTrace(int64_t DeviceId, + void *CodePtr) { + if (!isTracingEnabled(DeviceId, ompt_callback_target)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = + (ompt_record_ompt_t *)TRM->assignCursor(ompt_callback_target, DeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target); + setTraceRecordTarget(&DataPtr->record.target, DeviceId, ompt_target_exit_data, + ompt_scope_end, CodePtr); + + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("Generated trace record: %p (ompt_target_exit_data)\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t *Interface::startTargetUpdateTrace(int64_t DeviceId, + void *CodePtr) { + if (!isTracingEnabled(DeviceId, ompt_callback_target)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = + (ompt_record_ompt_t *)TRM->assignCursor(ompt_callback_target, DeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target); + setTraceRecordTarget(&DataPtr->record.target, DeviceId, ompt_target_update, + ompt_scope_begin, CodePtr); + + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("Returning trace record buf ptr: %p (ompt_target_update)\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t *Interface::stopTargetUpdateTrace(int64_t DeviceId, + void *CodePtr) { + if (!isTracingEnabled(DeviceId, ompt_callback_target)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = + (ompt_record_ompt_t *)TRM->assignCursor(ompt_callback_target, DeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target); + setTraceRecordTarget(&DataPtr->record.target, DeviceId, ompt_target_update, + ompt_scope_end, CodePtr); + + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("Generated trace record: %p (ompt_target_update)\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t *Interface::startTargetTrace(int64_t DeviceId, + void *CodePtr) { + if (!isTracingEnabled(DeviceId, ompt_callback_target)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = + (ompt_record_ompt_t *)TRM->assignCursor(ompt_callback_target, DeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target); + setTraceRecordTarget(&DataPtr->record.target, DeviceId, ompt_target, + ompt_scope_begin, CodePtr); + + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + DP("Returning trace record buf ptr: %p (ompt_target)\n", DataPtr); + return DataPtr; +} + +ompt_record_ompt_t *Interface::stopTargetTrace(int64_t DeviceId, + void *CodePtr) { + if (!isTracingEnabled(DeviceId, ompt_callback_target)) + return nullptr; + + assert(PM && "Plugin manager not initialized"); + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + ompt_record_ompt_t *DataPtr = + (ompt_record_ompt_t *)TRM->assignCursor(ompt_callback_target, DeviceId); + + // This event will not be traced + if (DataPtr == nullptr) + return nullptr; + + setTraceRecordCommon(DataPtr, ompt_callback_target); + setTraceRecordTarget(&DataPtr->record.target, DeviceId, ompt_target, + ompt_scope_end, CodePtr); + + // The trace record has been created, mark it ready for delivery to the tool + TRM->setTRStatus(DataPtr, OmptTracingBufferMgr::TR_ready); + + DP("Generated trace record: %p (ompt_target)\n", DataPtr); + return DataPtr; +} + +extern "C" { +// Device-independent entry point for ompt_set_trace_ompt +ompt_set_result_t libomptarget_ompt_set_trace_ompt(int DeviceId, + unsigned int Enable, + unsigned int EventTy) { + std::unique_lock Lock(TraceAccessMutex); + return llvm::omp::target::ompt::setTraceEventTy(DeviceId, Enable, EventTy); +} + +// Device-independent entry point for ompt_start_trace +int libomptarget_ompt_start_trace(int DeviceId, + ompt_callback_buffer_request_t Request, + ompt_callback_buffer_complete_t Complete) { + if (!PM) { + REPORT("Failed to start trace for DeviceId=%d (invalid plugin manager)\n", + DeviceId); + // Indicate failure + return 0; + } + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + std::unique_lock Lock(TraceControlMutex); + if (Request && Complete) { + // Set buffer related functions + llvm::omp::target::ompt::setBufferManagementFns(DeviceId, Request, + Complete); + llvm::omp::target::ompt::enableDeviceTracing(DeviceId); + TRM->startHelperThreads(); + // Success + return 1; + } + // Failure + return 0; +} + +// Device-independent entry point for ompt_flush_trace +int libomptarget_ompt_flush_trace(int DeviceId) { + if (!PM) { + REPORT("Failed to flush trace for DeviceId=%d (invalid plugin manager)\n", + DeviceId); + // Indicate failure + return 0; + } + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + std::unique_lock Lock(TraceControlMutex); + return TRM->flushAllBuffers(DeviceId); +} + +// Device independent entry point for ompt_stop_trace +int libomptarget_ompt_stop_trace(int DeviceId) { + if (!PM) { + REPORT("Failed to stop trace for DeviceId=%d (invalid plugin manager)\n", + DeviceId); + // Indicate failure + return 0; + } + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + std::unique_lock Lock(TraceControlMutex); + + // Schedule flushing of trace records for this device + int Status = TRM->flushAllBuffers(DeviceId); + + // De-register this device so that no more traces are collected + // or delivered for this device until an ompt_start_trace is + // invoked for this device. + removeBufferManagementFns(DeviceId); + + // If no device is being traced, shut down the helper threads. A + // subsequent ompt_start_trace will start up the helper threads. + if (isAllDeviceTracingStopped()) { + // TODO shutdown should perhaps return a status + TRM->shutdownHelperThreads(); + llvm::omp::target::ompt::disableDeviceTracing(DeviceId); + } + return Status; +} + +// Device independent entry point for ompt_advance_buffer_cursor +// Note: The input parameter size is unused here. It refers to the +// bytes returned in the corresponding callback. +int libomptarget_ompt_advance_buffer_cursor(ompt_device_t *Device, + ompt_buffer_t *Buffer, size_t Size, + ompt_buffer_cursor_t CurrentPos, + ompt_buffer_cursor_t *NextPos) { + if (!PM) { + REPORT("Failed to advance buffer cursor for Device=%p (invalid plugin " + "manager)\n", + Device); + // Indicate failure + return false; + } + OmptTracingBufferMgr *TRM = PM->getTraceRecordManager(); + char *TraceRecord = (char *)CurrentPos; + // Don't assert if CurrentPos is null, just indicate end of buffer + if (TraceRecord == nullptr || TRM->isLastCursor(TraceRecord)) { + *NextPos = 0; + return false; + } + // TODO In debug mode, assert that the metadata points to the + // input parameter buffer + + size_t TRSize = TRM->getTRSize(); + *NextPos = (ompt_buffer_cursor_t)(TraceRecord + TRSize); + DP("Advanced buffer pointer by %lu bytes to %p\n", TRSize, + TraceRecord + TRSize); + return true; +} + +// This function is invoked before the kernel launch. So, when the trace record +// is populated after kernel completion, TraceRecordNumGrantedTeams is already +// updated. +void libomptarget_ompt_set_granted_teams(uint32_t NumTeams) { + TraceRecordNumGrantedTeams = NumTeams; +} + +// Assume a synchronous implementation and set thread local variables to track +// timestamps. The thread local variables can then be used to populate trace +// records. +void libomptarget_ompt_set_timestamp(uint64_t Start, uint64_t Stop) { + TraceRecordStartTime = Start; + TraceRecordStopTime = Stop; +} + +// Device-independent entry point to query for the trace format used. +// Currently, only OMPT format is supported. +ompt_record_t +libomptarget_ompt_get_record_type(ompt_buffer_t *Buffer, + ompt_buffer_cursor_t CurrentPos) { + // TODO: When different OMPT trace buffer formats supported, this needs to be + // fixed. + return ompt_record_t::ompt_record_ompt; +} +} // extern "C" + +#pragma pop_macro("DEBUG_PREFIX") + +#endif // OMPT_SUPPORT diff --git a/offload/libomptarget/OpenMP/OMPT/OmptTracingBuffer.cpp b/offload/libomptarget/OpenMP/OMPT/OmptTracingBuffer.cpp new file mode 100644 index 0000000000000..0cf17f79864fb --- /dev/null +++ b/offload/libomptarget/OpenMP/OMPT/OmptTracingBuffer.cpp @@ -0,0 +1,751 @@ +//=== OmptTracingBuffer.cpp - Target independent OpenMP target RTL -- C++ -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Implementation of OMPT device trace record generation and flushing. +// +//===----------------------------------------------------------------------===// + +#ifdef OMPT_SUPPORT + +#include "OpenMP/OMPT/OmptTracingBuffer.h" +#include "OpenMP/OMPT/OmptTracing.h" +#include "Shared/Debug.h" + +#include +#include +#include +#include + +// When set to true, helper threads terminate their work +static bool DoneTracing{false}; + +// Unique buffer id in creation order +static std::atomic BufId{0}; + +// Unique id in buffer flush order +static std::atomic FlushId{0}; + +thread_local OmptTracingBufferMgr::BufPtr + OmptTracingBufferMgr::ArrayOfBufPtr[MAX_NUM_DEVICES]; + +static uint64_t get_and_inc_buf_id() { return BufId++; } + +static uint64_t get_and_inc_flush_id() { return FlushId++; } +static uint64_t get_flush_id() { return FlushId; } + +/* + * Used by OpenMP threads for assigning space for a trace record. If + * there is no space in the last buffer allocated by this thread, the + * last buffer is marked full and scheduled for flushing. Otherwise, + * space is assigned for a trace record and the new cursor returned. + * Since the memory allocated by a thread is used by that thread alone + * for creating trace records, a lock need not be held. In the less + * common branch when memory is allocated, a lock needs to be acquired + * for updating shared metadata. The common path of allocating a trace + * record from an existing buffer proceeds without locking. + */ +void *OmptTracingBufferMgr::assignCursor(ompt_callbacks_t Type, + int64_t DeviceId) { + // The caller should handle nullptr by not tracing for this event. + if (DeviceId < 0 || DeviceId > MAX_NUM_DEVICES - 1) + return nullptr; + + size_t RecSize = getTRSize(); + + // If the buffer fills up, it will be scheduled for flushing with the + // following cursor. + void *ToBeFlushedCursor = nullptr; + BufPtr ToBeFlushedBuf = nullptr; + + // Thread local buffer pointer should be non-null once an allocation + // has been done by this thread. + BufPtr DeviceBuf = getDeviceSpecificBuffer(DeviceId); + if (DeviceBuf != nullptr) { + assert(DeviceBuf->DeviceId == DeviceId && "Unexpected device id in buffer"); + void *OldCursor = DeviceBuf->Cursor.load(std::memory_order_acquire); + // Try to assign a trace record from the last allocated buffer + if (RecSize <= DeviceBuf->RemainingBytes) { + assert((char *)DeviceBuf->Start + DeviceBuf->TotalBytes - + DeviceBuf->RemainingBytes == + (char *)OldCursor + RecSize); + DeviceBuf->RemainingBytes -= RecSize; + + // Note the trace record status must be initialized before setting + // the cursor, ensuring that a helper thread always sees an initialized + // trace record status. + void *NewCursor = (char *)OldCursor + RecSize; + initTraceRecordMetaData(NewCursor); + DeviceBuf->Cursor.store(NewCursor, std::memory_order_release); + + DP("Thread %lu: Assigned %lu bytes at %p in existing buffer %p for " + "device %ld\n", + llvm::omp::target::ompt::getThreadId(), RecSize, NewCursor, + DeviceBuf->Start, DeviceId); + return NewCursor; + } else { + ToBeFlushedCursor = OldCursor; + ToBeFlushedBuf = DeviceBuf; + + // Mark that no space is present for any more trace records. + // The following is atomic but there is no logical order between when + // it is set here and when it is checked by a helper thread. That works + // because the helper thread uses this info to decide whether a buffer + // can be scheduled for removal. In the worst case, the buffer will be + // removed late. + DeviceBuf->IsFull.store(true, std::memory_order_release); + } + } + void *NewBuffer = nullptr; + size_t TotalBytes = 0; + // TODO Move the buffer allocation to a helper thread + llvm::omp::target::ompt::ompt_callback_buffer_request(DeviceId, &NewBuffer, + &TotalBytes); + + // The caller should handle nullptr by not tracing for this event. + if (NewBuffer == nullptr || TotalBytes < RecSize) + return nullptr; + + uint64_t NewBufId = get_and_inc_buf_id(); + auto new_buf = std::make_shared( + NewBufId, DeviceId, /*Start=*/NewBuffer, TotalBytes, + /*RemainingBytes=*/TotalBytes - RecSize, + /*Cursor=*/NewBuffer, + /*IsFull=*/false); + + // Initialize trace record status before publishing it to helper threads. + initTraceRecordMetaData(new_buf->Cursor.load(std::memory_order_acquire)); + setDeviceSpecificBuffer(DeviceId, new_buf); + + // Make this trace record visible to helper threads by adding to shared + // metadata. + std::unique_lock lck(BufferMgrMutex); + assert(Id2BufferMap.find(NewBufId) == Id2BufferMap.end()); + Id2BufferMap[NewBufId] = new_buf; + lck.unlock(); + + // Schedule the full buffer for flushing till the corresponding cursor. + if (OMPX_FlushOnBufferFull && ToBeFlushedCursor) + triggerFlushOnBufferFull(ToBeFlushedCursor, ToBeFlushedBuf); + + DP("Thread %lu: Assigned %lu bytes at %p in new buffer with id %lu for " + "device %ld\n", + llvm::omp::target::ompt::getThreadId(), RecSize, NewBuffer, NewBufId, + DeviceId); + + return NewBuffer; +} + +/* + * Called by an OpenMP thread when a buffer fills up and should be + * flushed. This function assigns a new FlushId to the buffer, adds + * to the flush-related metadata and wakes up a helper thread to + * dispatch a buffer-completion callback. This function should be + * called without holding any lock. + * Note lock order: buf_lock -> flush_lock + */ +void OmptTracingBufferMgr::triggerFlushOnBufferFull(void *cursor, BufPtr Buf) { + std::unique_lock buf_lock(BufferMgrMutex); + + // Between calling this function and this check, a flush-all may have + // delivered this buffer to the tool and deleted it. So the buffer + // may not exist. + if (Id2BufferMap.find(Buf->Id) == Id2BufferMap.end()) + return; + + // Cannot assert that the state of the cursor is ready since a + // different thread may be in the process of populating it. If it + // remains in init state when the range of trace records is + // determined for dispatching the buffer-completion callback, it + // will not be included. + std::unique_lock flush_lock(FlushMutex); + uint64_t flush_id; + auto flush_itr = FlushBufPtr2IdMap.find(Buf); + if (flush_itr == FlushBufPtr2IdMap.end()) { + // This buffer has not been flushed yet + addNewFlushEntry(Buf, cursor); + } else { + // This buffer has been flushed before + flush_id = flush_itr->second; + auto flush_md_itr = Id2FlushMdMap.find(flush_id); + assert(flush_md_itr != Id2FlushMdMap.end()); + flush_md_itr->second.FlushCursor = cursor; // update the cursor + // Do not update the flush status since it may be under processing + // by another thread + DP("Updated id %lu cursor %p buf %p\n", flush_id, cursor, + flush_md_itr->second.FlushBuf->Start); + } + flush_lock.unlock(); + buf_lock.unlock(); + + // Wake up a helper thread to invoke the buffer-completion callback + FlushCv.notify_one(); +} + +// This is the driver routine for the completion thread +void OmptTracingBufferMgr::driveCompletion() { + while (true) { + bool should_signal_workers = false; + std::unique_lock flush_lock(FlushMutex); + if (DoneTracing) { + // An upper layer serializes flush_trace and stop_trace. In + // addition, before DoneTracing is set, a flush is performed as + // part of stop_trace. So assert that no flush is in progress. + assert(ThreadFlushTracker == 0); + break; + } + FlushCv.wait(flush_lock, [this] { + return DoneTracing || + (!Id2FlushMdMap.empty() && + llvm::omp::target::ompt::TracingActive) || + isThisThreadFlushWaitedUpon(); + }); + if (isThisThreadFlushWaitedUpon()) { + resetThisThreadFlush(); + if (ThreadFlushTracker == 0) + should_signal_workers = true; + } + flush_lock.unlock(); + + invokeCallbacks(); + + if (should_signal_workers) + ThreadFlushCv.notify_all(); + + // There is a scenario where a buffer was processed but not full + // or owned, so it was put back in waiting state. So this thread + // would not wait but keep on looping without having any actual + // work until new trace records are added and this thread + // signaled. Hence, this thread yields. + std::this_thread::yield(); + } + bool is_last_helper = false; + std::unique_lock flush_lock(FlushMutex); + assert(DoneTracing && "Helper thread exiting but not yet done"); + assert(isThisThreadShutdownWaitedUpon() && + "Helper thread exiting but not waited upon"); + resetThisThreadShutdown(); + if (ThreadShutdownTracker == 0) + is_last_helper = true; + flush_lock.unlock(); + if (is_last_helper) + ThreadShutdownCv.notify_all(); + + // Note that some trace records may have been written but not + // delivered to the tool. If flush/stop APIs are not called by the + // tool, those trace records may never be delivered to the tool and + // the corresponding buffers not reclaimed. TODO Explore whether + // this cleanup must be done. +} + +/* + * Called by a buffer-completion helper thread. This function examines + * the flushed buffers in flush order and dispatches + * callbacks. Lock holding is minimized by reserving a buffer, + * processing it, and then unreserving it if there are more trace + * records to flush later. If all trace records are flushed, a + * callback is dispatched informing the tool that the buffer can be + * deallocated. If the buffer can be deallocated, all metadata is + * destroyed. + * Note that this function must be called without holding any locks. + */ +void OmptTracingBufferMgr::invokeCallbacks() { + DP("Looking for callbacks to invoke\n"); + auto max_id = std::numeric_limits::max(); + auto curr_id = max_id; + auto end_id = get_flush_id(); + DP("End id is %lu\n", end_id); + while (true) { + // Set the status of the flushed buffer to in-processing so that + // another helper thread does not process it concurrently. An + // OpenMP worker thread may, however, populate a trace record in a + // reserved buffer concurrently. + FlushInfo flush_info = findAndReserveFlushedBuf(curr_id); + + // no entry found, nothing to process + if (curr_id == max_id && flush_info.FlushCursor == nullptr) + return; + + if (flush_info.FlushCursor != nullptr) { + // increment curr_id to get the candidate for the next iteration + curr_id = flush_info.FlushId + 1; + } else { + assert(curr_id != max_id && "Cannot increment max id"); + ++curr_id; + } + + DP("Next id will be %lu\n", curr_id); + + if (flush_info.FlushCursor == nullptr) { + // This buffer must have been processed already + if (curr_id < end_id) + continue; + else + return; // nothing else to process + } + + DP("Buf %p Cursor %p Id %lu will be flushed\n", flush_info.FlushBuf->Start, + flush_info.FlushCursor, flush_info.FlushId); + + // Examine the status of the trace records and dispatch + // buffer-completion callbacks as appropriate. + flushBuffer(flush_info); + + // TODO optimize to set buffer-owned in the same pass above. + // Currently, this is the only way a buffer is deallocated + if (isBufferFull(flush_info)) { + // All trace records have been delivered to the tool + if (isBufferOwned(flush_info)) { + // erase element from buffer and flush maps + destroyFlushedBuf(flush_info); + + // dispatch callback with a null range and have the tool + // deallocate the buffer + dispatchBufferOwnedCallback(flush_info); + } else { + unreserveFlushedBuf(flush_info); + } + } else { + unreserveFlushedBuf(flush_info); + } + if (curr_id >= end_id) + return; + } +} + +/* + * This function is called on a buffer that is already reserved by + * this thread. Buffer-completion callbacks are dispatched for every + * range of trace records that are ready. + * This routine must be called without holding locks + */ +void OmptTracingBufferMgr::flushBuffer(FlushInfo flush_info) { + assert(flush_info.FlushBuf && "Cannot flush an empty buffer"); + assert(flush_info.FlushCursor && "Cannot flush upto a null cursor"); + + void *curr_tr = flush_info.FlushBuf->Start; + void *last_tr = flush_info.FlushCursor; + // Compute a range [first_cursor,last_cursor] to flush + void *first_cursor = nullptr; + void *last_cursor = nullptr; + while (curr_tr <= last_tr) { + TRStatus tr_status = getTRStatus(curr_tr); + if (tr_status == TR_init || tr_status == TR_released) { + if (first_cursor == nullptr) { + // This TR won't be part of a range + assert(last_cursor == nullptr && + "Begin/last cursors mutually inconsistent"); + } else { + // End the current interval + dispatchCallback(flush_info.FlushBuf->DeviceId, + flush_info.FlushBuf->Start, first_cursor, last_cursor); + first_cursor = last_cursor = nullptr; + } + } else { + assert(tr_status == TR_ready && "Unknown trace record status"); + setTRStatus(curr_tr, TR_released); + if (first_cursor == nullptr) + first_cursor = curr_tr; + last_cursor = curr_tr; + } + curr_tr = getNextTR(curr_tr); + } + if (first_cursor != nullptr) { + assert(last_cursor != nullptr); + dispatchCallback(flush_info.FlushBuf->DeviceId, flush_info.FlushBuf->Start, + first_cursor, last_cursor); + } +} + +// Given a range of trace records, dispatch a buffer-completion callback +void OmptTracingBufferMgr::dispatchCallback(int64_t DeviceId, void *Buffer, + void *FirstCursor, + void *LastCursor) { + assert(FirstCursor != nullptr && LastCursor != nullptr && + "Callback with nullptr"); + addLastCursor(LastCursor); + + // This is best effort. + // There is a small window when the buffer-completion callback may + // be invoked even after tracing has been disabled. + // Note that we don't want to hold a lock when dispatching the callback. + if (llvm::omp::target::ompt::isTracedDevice(DeviceId)) { + DP("Dispatch callback w/ range (inclusive) to be flushed: %p -> %p\n", + FirstCursor, LastCursor); + llvm::omp::target::ompt::ompt_callback_buffer_complete( + DeviceId, Buffer, + /* bytes returned in this callback */ + (char *)getNextTR(LastCursor) - (char *)FirstCursor, + (ompt_buffer_cursor_t)FirstCursor, false /* buffer_owned */); + } + + removeLastCursor(LastCursor); +} + +// Dispatch a buffer-completion callback with buffer_owned set so that +// the tool can deallocate the buffer +void OmptTracingBufferMgr::dispatchBufferOwnedCallback( + const FlushInfo &flush_info) { + // This is best effort. + // There is a small window when the buffer-completion callback may + // be invoked even after tracing has been disabled. + // Note that we don't want to hold a lock when dispatching the callback. + if (llvm::omp::target::ompt::isTracedDevice(flush_info.FlushBuf->DeviceId)) { + DP("Dispatch callback with buffer %p owned\n", flush_info.FlushBuf->Start); + llvm::omp::target::ompt::ompt_callback_buffer_complete( + flush_info.FlushBuf->DeviceId, flush_info.FlushBuf->Start, 0, + (ompt_buffer_cursor_t)0, true /* buffer owned */); + } +} + +void OmptTracingBufferMgr::initTraceRecordMetaData(void *Rec) { + setTRStatus(Rec, TR_init); +} + +OmptTracingBufferMgr::BufPtr +OmptTracingBufferMgr::getDeviceSpecificBuffer(int64_t DeviceId) { + if (DeviceId < 0 || DeviceId > MAX_NUM_DEVICES - 1) { + REPORT("getDeviceSpecificBuffer: Device id %ld invalid or exceeds " + "supported max: %d\n", + DeviceId, MAX_NUM_DEVICES - 1); + return nullptr; + } + return ArrayOfBufPtr[DeviceId]; +} + +void OmptTracingBufferMgr::setDeviceSpecificBuffer(int64_t DeviceId, + BufPtr Buf) { + if (DeviceId < 0 || DeviceId > MAX_NUM_DEVICES - 1) { + REPORT("setDeviceSpecificBuffer: Device id %ld invalid or exceeds " + "supported max: %d\n", + DeviceId, MAX_NUM_DEVICES - 1); + return; + } + ArrayOfBufPtr[DeviceId] = Buf; +} + +void OmptTracingBufferMgr::setTRStatus(void *Rec, TRStatus Status) { + TraceRecord *TR = static_cast(Rec); + TR->TRState.store(Status, std::memory_order_release); +} + +OmptTracingBufferMgr::TRStatus OmptTracingBufferMgr::getTRStatus(void *Rec) { + return static_cast(Rec)->TRState.load( + std::memory_order_acquire); +} + +void *OmptTracingBufferMgr::getNextTR(void *TR) { + size_t RecSize = getTRSize(); + // warning: no overflow check done + return (char *)TR + RecSize; +} + +bool OmptTracingBufferMgr::isBufferFull(const FlushInfo &flush_info) { + std::unique_lock buf_lock(BufferMgrMutex); + return flush_info.FlushBuf->IsFull; +} + +void *OmptTracingBufferMgr::getBufferCursor(BufPtr buf) { + return buf->Cursor.load(std::memory_order_acquire); +} + +/* + * Traverse all the trace records of a buffer and return true if all + * of them have been released to the tool, otherwise return false + */ +bool OmptTracingBufferMgr::isBufferOwned(const FlushInfo &flush_info) { + assert(isBufferFull(flush_info) && "Compute buffer-owned when it is full"); + void *curr_tr = flush_info.FlushBuf->Start; + // Since the buffer is full, the cursor must be the last valid + // TR. Note that this may be more up-to-date than the cursor in the + // flush_info. Use the last valid TR to avoid dropping trace records + void *last_tr = getBufferCursor(flush_info.FlushBuf); + while (curr_tr <= last_tr) { + if (getTRStatus(curr_tr) != TR_released) + return false; + curr_tr = getNextTR(curr_tr); + } + return true; +} + +/* + * A buffer must be reserved by a thread before it can be processed + * and callbacks dispatched for that buffer. Reservation is done by + * setting the status to in-processing. + * + * If a buffer is found in the flush metadata for the given id and it + * is not in in-processing mode, reserve it by setting its mode to + * in-processing and return the corresponding flush metadata. If the + * given id is set to max, return the first waiting buffer in the + * list of buffers to be flushed. + */ +OmptTracingBufferMgr::FlushInfo +OmptTracingBufferMgr::findAndReserveFlushedBuf(uint64_t FlushId) { + std::unique_lock flush_lock(FlushMutex); + MapId2Md::iterator flush_itr; + if (FlushId == std::numeric_limits::max()) { + // Reserve the first waiting buffer and return it + if (Id2FlushMdMap.empty()) + return FlushInfo(); + for (flush_itr = Id2FlushMdMap.begin(); flush_itr != Id2FlushMdMap.end(); + ++flush_itr) { + // Reserve only if waiting + if (flush_itr->second.FlushStatus == Flush_waiting) + break; + } + if (flush_itr == Id2FlushMdMap.end()) + return FlushInfo(); + } else { + flush_itr = Id2FlushMdMap.find(FlushId); + if (flush_itr == Id2FlushMdMap.end() || + flush_itr->second.FlushStatus == Flush_processing) + return FlushInfo(); + } + assert(flush_itr->second.FlushStatus == Flush_waiting); + flush_itr->second.FlushStatus = Flush_processing; + // Update the metadata cursor since more trace records may have been + // generated. + flush_itr->second.FlushCursor = + flush_itr->second.FlushBuf->Cursor.load(std::memory_order_acquire); + + FlushInfo flush_info(flush_itr->first, flush_itr->second.FlushCursor, + flush_itr->second.FlushBuf); + DP("Reserved buffer: flush_id:%lu, cursor:%p, buf:%p\n", flush_itr->first, + flush_itr->second.FlushCursor, flush_itr->second.FlushBuf->Start); + return flush_info; +} + +/* + * Given a buffer, verify that it is in processing state and set its + * status to waiting, removing the reservation. The same thread that + * reserved it should be unreserving it but currently there is no such + * check. + */ +void OmptTracingBufferMgr::unreserveFlushedBuf(const FlushInfo &flush_info) { + std::unique_lock flush_lock(FlushMutex); + auto itr = Id2FlushMdMap.find(flush_info.FlushId); + assert(itr != Id2FlushMdMap.end() && + itr->second.FlushStatus == Flush_processing); + itr->second.FlushStatus = Flush_waiting; + DP("Unreserved buffer: flush_id:%lu, cursor:%p, buf:%p\n", flush_info.FlushId, + flush_info.FlushCursor, flush_info.FlushBuf->Start); +} + +/* + * This function must be called after all of the trace records in the + * buffer have been released to the tool. The buffer is removed from + * all metadata maps. + * Note lock order: buf_lock -> flush_lock + */ +void OmptTracingBufferMgr::destroyFlushedBuf(const FlushInfo &flush_info) { + DP("Destroying buffer: flush_id:%lu, cursor:%p, buf:%p\n", flush_info.FlushId, + flush_info.FlushCursor, flush_info.FlushBuf->Start); + + BufPtr buf = flush_info.FlushBuf; + + std::unique_lock buf_lock(BufferMgrMutex); + Id2BufferMap.erase(buf->Id); + + std::unique_lock flush_lock(FlushMutex); + auto flush_itr = Id2FlushMdMap.find(flush_info.FlushId); + assert(flush_itr != Id2FlushMdMap.end()); + assert(flush_itr->second.FlushBuf == buf); + Id2FlushMdMap.erase(flush_itr); + FlushBufPtr2IdMap.erase(buf); +} + +/* + * Generate a new flush id and add the buffer to the flush metadata + * maps. This function must be called while holding the flush lock. + */ +uint64_t OmptTracingBufferMgr::addNewFlushEntry(BufPtr Buf, void *Cursor) { + assert(FlushBufPtr2IdMap.find(Buf) == FlushBufPtr2IdMap.end()); + uint64_t FlushId = get_and_inc_flush_id(); + FlushBufPtr2IdMap.emplace(Buf, FlushId); + assert(Id2FlushMdMap.find(FlushId) == Id2FlushMdMap.end()); + Id2FlushMdMap.emplace(FlushId, FlushMd(Cursor, Buf, Flush_waiting)); + + DP("Added new flush id %lu cursor %p buf %p\n", FlushId, Cursor, Buf->Start); + + return FlushId; +} + +/* + * Called by ompt_flush_trace and ompt_stop_trace. Traverse the + * existing buffers in creation order and flush all the ready TRs + */ +int OmptTracingBufferMgr::flushAllBuffers(int DeviceId) { + DP("Flushing buffers for device %d :: START\n", DeviceId); + // Overloading MAX_NUM_DEVICES to mean all devices. + if (DeviceId < 0 || DeviceId > MAX_NUM_DEVICES) + return 0; // failed to flush + + if (!areHelperThreadsAvailable()) + return 0; // failed to flush + + // If flush is called from a helper thread, just bail out + if (amIHelperThread()) + return 0; // failed to flush + + // To avoid holding the mutex for too long, get the ids of the first + // and the last TRs under lock, and then go through that range, + // holding the mutex for an individual TR + std::unique_lock buf_lock(BufferMgrMutex); + if (Id2BufferMap.empty()) + return 1; // no trace records to flush + uint64_t curr_buf_id = Id2BufferMap.begin()->first; + uint64_t last_buf_id = Id2BufferMap.rbegin()->first; + buf_lock.unlock(); + + while (curr_buf_id <= last_buf_id) { + std::unique_lock buf_lock(BufferMgrMutex); + // Another thread may have deleted this buffer by now + auto buf_itr = Id2BufferMap.find(curr_buf_id); + if (buf_itr == Id2BufferMap.end()) { + ++curr_buf_id; + continue; + } + BufPtr curr_buf = buf_itr->second; + + // If the device-id does not match, skip it. A device-id of MAX_NUM_DEVICES + // indicates flushing for all devices. + if (DeviceId != MAX_NUM_DEVICES && curr_buf->DeviceId != DeviceId) { + ++curr_buf_id; + continue; + } + + // If this buffer is in the flush-map, skip it. It is either in + // process by another thread or will be processed + std::unique_lock flush_lock(FlushMutex); + auto flush_itr = FlushBufPtr2IdMap.find(curr_buf); + if (flush_itr != FlushBufPtr2IdMap.end()) { + ++curr_buf_id; + continue; + } + // This buffer has not been flushed yet + void *CurrBufCursor = getBufferCursor(curr_buf); + uint64_t flush_id = addNewFlushEntry(curr_buf, CurrBufCursor); + (void)flush_id; // Silence warning. + DP("flushAllBuffers: Added new id %lu cursor %p buf %p\n", flush_id, + CurrBufCursor, curr_buf->Start); + + flush_lock.unlock(); + buf_lock.unlock(); + + ++curr_buf_id; + } + + DP("Flushing buffers for device %d :: WAIT\n", DeviceId); + + // This is best effort. It is possible that some trace records are + // not flushed when the wait is done. + waitForFlushCompletion(); + + DP("Flushing buffers for device %d :: STOP\n", DeviceId); + + return 1; // success +} + +void OmptTracingBufferMgr::waitForFlushCompletion() { + { + std::unique_lock flush_lock(FlushMutex); + // Setting the flush bit for a given helper thread indicates that the worker + // thread is ready for the helper thread to do some work. + for (uint32_t i = 0; i < OMPT_NUM_HELPER_THREADS; ++i) + setThreadFlush(i); + } + + // Wake up all helper threads to invoke buffer-completion callbacks. + FlushCv.notify_all(); + + // Now wait for all helper threads to complete flushing. + { + std::unique_lock flush_lock(FlushMutex); + ThreadFlushCv.wait(flush_lock, [this] { return ThreadFlushTracker == 0; }); + } +} + +void OmptTracingBufferMgr::init() { + for (int i = 0; i < MAX_NUM_DEVICES; ++i) + ArrayOfBufPtr[i] = nullptr; + ThreadFlushTracker = 0; + ThreadShutdownTracker = 0; + DoneTracing = false; // TODO make it a class member +} + +void OmptTracingBufferMgr::startHelperThreads() { + // All helper threads are stopped while holding FlushMutex. So if + // any helper thread is present, just return. This takes care of + // repeated calls to start-trace. + std::unique_lock flush_lock(FlushMutex); + if (!HelperThreadIdMap.empty()) { + assert(!DoneTracing && "Helper threads exist but tracing is done"); + return; + } + init(); + createHelperThreads(); +} + +bool OmptTracingBufferMgr::areHelperThreadsAvailable() { + std::unique_lock flush_lock(FlushMutex); + if (DoneTracing // If another thread called stop, assume there are no threads + || HelperThreadIdMap.empty() // Threads were never started + ) { + // Don't assert on HelperThreadIdMap since shutdown by another + // thread may be in progress + return false; + } + return true; +} + +void OmptTracingBufferMgr::shutdownHelperThreads() { + if (!areHelperThreadsAvailable()) + return; + + std::unique_lock flush_lock(FlushMutex); + // If I am destroying the threads, then at least one thread must be present + assert(!CompletionThreads.empty()); + assert(!HelperThreadIdMap.empty()); + assert(ThreadShutdownTracker == 0); + + // Set the done flag which helper threads will look at + DoneTracing = true; + // Wait to make sure all helper threads exit + for (uint32_t i = 0; i < OMPT_NUM_HELPER_THREADS; ++i) + setThreadShutdown(i); + // Signal indicating that DoneTracing is set + FlushCv.notify_all(); + ThreadShutdownCv.wait(flush_lock, + [this] { return ThreadShutdownTracker == 0; }); + + // Now destroy all the helper threads + destroyHelperThreads(); +} + +void OmptTracingBufferMgr::flushAndShutdownHelperThreads() { + std::unique_lock Lock(llvm::omp::target::ompt::TraceControlMutex); + // Flush buffers for all devices. + if (OMPX_FlushOnShutdown) + flushAllBuffers(MAX_NUM_DEVICES); + shutdownHelperThreads(); +} + +void OmptTracingBufferMgr::createHelperThreads() { + for (uint32_t i = 0; i < OMPT_NUM_HELPER_THREADS; ++i) { + CompletionThreads.emplace_back( + std::thread(&OmptTracingBufferMgr::driveCompletion, this)); + HelperThreadIdMap[CompletionThreads.back().get_id()] = i; + } +} + +void OmptTracingBufferMgr::destroyHelperThreads() { + for (auto &thd : CompletionThreads) + thd.join(); + CompletionThreads.clear(); + HelperThreadIdMap.clear(); +} +#endif diff --git a/offload/libomptarget/PluginManager.cpp b/offload/libomptarget/PluginManager.cpp index c8d6b42114d0f..aece6ba535f97 100644 --- a/offload/libomptarget/PluginManager.cpp +++ b/offload/libomptarget/PluginManager.cpp @@ -11,6 +11,9 @@ //===----------------------------------------------------------------------===// #include "PluginManager.h" +#include "OpenMP/OMPT/Callback.h" +#include "OpenMP/OMPT/OmptCommonDefs.h" +#include "OpenMP/OMPT/OmptTracing.h" #include "OffloadPolicy.h" #include "Shared/Debug.h" #include "Shared/Profile.h" @@ -46,13 +49,33 @@ void PluginManager::init() { } while (false); #include "Shared/Targets.def" +// At this point, we don't know whether OMPT tracing will be turned ON. +// So we create the top-level tracing manager as long as OMPT is built in -- +// the construction itself is inexpensive. +#ifdef OMPT_SUPPORT + assert(TraceRecordManager == nullptr && + "Expected trace record manager to be null"); + TraceRecordManager = new OmptTracingBufferMgr(); +#endif + DP("RTLs loaded!\n"); } void PluginManager::deinit() { TIMESCOPE(); + if (OffloadPolicy::isOffloadDisabled()) { + DP("Offload is disabled. Skipping plugin deinitialization\n"); + return; + } DP("Unloading RTLs...\n"); +#ifdef OMPT_SUPPORT + assert(TraceRecordManager != nullptr && + "Trace record manager should have been non-null"); + delete TraceRecordManager; + TraceRecordManager = nullptr; +#endif + for (auto &Plugin : Plugins) { if (!Plugin->is_initialized()) continue; @@ -209,6 +232,7 @@ void PluginManager::registerLib(__tgt_bin_desc *Desc) { PM->addDeviceImage(*Desc, Desc->DeviceImages[i]); // Register the images with the RTLs that understand them, if any. + bool FoundCompatibleImage = false; llvm::DenseMap> UsedDevices; for (int32_t i = 0; i < Desc->NumDeviceImages; ++i) { // Obtain the image and information that was previously extracted. @@ -285,19 +309,39 @@ void PluginManager::registerLib(__tgt_bin_desc *Desc) { TT.TargetsTable[UserId] = nullptr; UsedDevices[&R].insert(DeviceId); - PM->UsedImages.insert(Img); + PM->TrlTblMtx.unlock(); FoundRTL = &R; + } - PM->TrlTblMtx.unlock(); + if (FoundRTL) { + PM->UsedImages.insert(Img); + break; } } - if (!FoundRTL) + if (!FoundRTL) { DP("No RTL found for image " DPxMOD "!\n", DPxPTR(Img->ImageStart)); + } else { + FoundCompatibleImage = true; + } } + + // Check if I can report any XNACK related image failures. The report + // should happen only when we have not found a compatible RTL with + // matching XNACK and we were expecting to have a match (i.e. the + // image was hoping to find an RTL for an AMD GPU with XNACK support). + if (!FoundCompatibleImage) { + for (DeviceImageTy &DI : PM->deviceImages()) { + __tgt_device_image *Img = &DI.getExecutableImage(); + for (auto &R : PM->plugins()) + R.check_invalid_image(Img); + } + } + PM->RTLsMtx.unlock(); - bool UseAutoZeroCopy = false; + bool IsAPU = Plugins.size() > 0; + bool UseAutoZeroCopy = false; auto ExclusiveDevicesAccessor = getExclusiveDevicesAccessor(); // APUs are homogeneous set of GPUs. Check the first device for // configuring Auto Zero-Copy. @@ -309,16 +353,54 @@ void PluginManager::registerLib(__tgt_bin_desc *Desc) { if (UseAutoZeroCopy) addRequirements(OMPX_REQ_AUTO_ZERO_COPY); + bool EagerMapsRequested = BoolEnvar("OMPX_EAGER_ZERO_COPY_MAPS", false).get(); + + // Eager Zero-Copy Maps makes a "copy" execution turn into + // an automatic zero-copy. It also applies to unified_shared_memory. + // It is only available on APUs. + if (IsAPU && EagerMapsRequested) { + addRequirements(OMPX_REQ_EAGER_ZERO_COPY_MAPS); + if (!(getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY)) + addRequirements(OMPX_REQ_AUTO_ZERO_COPY); + } + + // Sanity checks for zero-copy depend on specific devices: request it here + if ((ExclusiveDevicesAccessor->size() > 0) && + ((getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY) || + (getRequirements() & OMPX_REQ_AUTO_ZERO_COPY))) { + // APUs are assumed to be a homogeneous set of GPUs: ask + // the first device in the system to run a sanity check. + auto &Device = *(*ExclusiveDevicesAccessor)[0]; + // just skip checks if no devices are found in the system + Device.zeroCopySanityChecksAndDiag( + (getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY), + (getRequirements() & OMPX_REQ_AUTO_ZERO_COPY), + (getRequirements() & OMPX_REQ_EAGER_ZERO_COPY_MAPS)); + } + + // Add the flag for multi-device. + if (ExclusiveDevicesAccessor->size() > 0) { + auto &Device = *(*ExclusiveDevicesAccessor)[0]; + if (Device.getNumMultiDevices() > 0) + addRequirements(OMPX_REQ_MULTI_DEVICE_ENABLED); + } + DP("Done registering entries!\n"); } // Temporary forward declaration, old style CTor/DTor handling is going away. int target(ident_t *Loc, DeviceTy &Device, void *HostPtr, - KernelArgsTy &KernelArgs, AsyncInfoTy &AsyncInfo); + KernelArgsTy &KernelArgs, AsyncInfoTy &AsyncInfo, + bool InMultiDeviceMode, bool &IsMultiDeviceKernel); void PluginManager::unregisterLib(__tgt_bin_desc *Desc) { DP("Unloading target library!\n"); + // Flush in-process OMPT trace records and shut down helper threads + // before unloading the library. + OMPT_IF_TRACING_ENABLED( + PM->getTraceRecordManager()->flushAndShutdownHelperThreads();); + Desc = upgradeLegacyEntries(Desc); PM->RTLsMtx.lock(); @@ -520,8 +602,8 @@ static int loadImagesOntoDevice(DeviceTy &Device) { CurrHostEntry->Size /*HstPtrEnd*/, (uintptr_t)CurrDeviceEntryAddr /*TgtAllocBegin*/, (uintptr_t)CurrDeviceEntryAddr /*TgtPtrBegin*/, - false /*UseHoldRefCount*/, CurrHostEntry->SymbolName, - true /*IsRefCountINF*/)); + false /*UseHoldRefCount*/, TARGET_ALLOC_DEFAULT /*AllocKind*/, + CurrHostEntry->SymbolName, true /*IsRefCountINF*/)); // Notify about the new mapping. if (Device.notifyDataMapped(CurrHostEntry->Address, @@ -564,3 +646,21 @@ Expected PluginManager::getDevice(uint32_t DeviceNo) { DeviceNo); return *DevicePtr; } + +#ifdef OMPT_SUPPORT + +#include "OmptProfiler.h" + +std::unique_ptr +getProfilerToAttach() { + return std::make_unique(); +} + +#else + +std::unique_ptr +getProfilerToAttach() { + return std::make_unique(); +} + +#endif diff --git a/offload/libomptarget/device.cpp b/offload/libomptarget/device.cpp index ee36fbed935a5..6a5c6e7b6b7d9 100644 --- a/offload/libomptarget/device.cpp +++ b/offload/libomptarget/device.cpp @@ -15,6 +15,8 @@ #include "OpenMP/Mapping.h" #include "OpenMP/OMPT/Callback.h" #include "OpenMP/OMPT/Interface.h" +#include "OpenMP/OMPT/OmptCommonDefs.h" +#include "OpenMP/OMPT/OmptTracing.h" #include "PluginManager.h" #include "Shared/APITypes.h" #include "Shared/Debug.h" @@ -34,7 +36,8 @@ #include #ifdef OMPT_SUPPORT -using namespace llvm::omp::target::ompt; +using namespace llvm::omp::target; +using namespace ompt; #endif using namespace llvm::omp::target::plugin; @@ -68,7 +71,7 @@ int HostDataToTargetTy::addEventIfNecessary(DeviceTy &Device, DeviceTy::DeviceTy(GenericPluginTy *RTL, int32_t DeviceID, int32_t RTLDeviceID) : DeviceID(DeviceID), RTL(RTL), RTLDeviceID(RTLDeviceID), - MappingInfo(*this) {} + ForceSynchronousTargetRegions(false), MappingInfo(*this) {} DeviceTy::~DeviceTy() { if (DeviceID == -1 || !(getInfoLevel() & OMP_INFOTYPE_DUMP_TABLE)) @@ -78,12 +81,19 @@ DeviceTy::~DeviceTy() { dumpTargetPointerMappings(&Loc, *this); } +/// Used to set the asynchronous execution mode +inline void setAsyncInfoSynchronous(__tgt_async_info *AI, bool SetSynchronous) { + if (SetSynchronous) + AI->ExecAsync = false; +} + llvm::Error DeviceTy::init() { int32_t Ret = RTL->init_device(RTLDeviceID); if (Ret != OFFLOAD_SUCCESS) return error::createOffloadError(error::ErrorCode::BACKEND_FAILURE, "failed to initialize device %d\n", DeviceID); + setTeamProcs(RTL->number_of_team_procs(RTLDeviceID)); // Enables recording kernels if set. BoolEnvar OMPX_RecordKernel("LIBOMPTARGET_RECORD", false); @@ -193,10 +203,15 @@ DeviceTy::loadBinary(__tgt_device_image *Img) { void *DeviceTy::allocData(int64_t Size, void *HstPtr, int32_t Kind) { /// RAII to establish tool anchors before and after data allocation void *TargetPtr = nullptr; - OMPT_IF_BUILT(InterfaceRAII TargetDataAllocRAII( - RegionInterface.getCallbacks(), - DeviceID, HstPtr, &TargetPtr, Size, - /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) + OMPT_IF_BUILT( + InterfaceRAII TargetDataAllocRAII( + RegionInterface.getCallbacks(), DeviceID, + HstPtr, &TargetPtr, Size, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS); + InterfaceRAII TargetDataAllocTraceRAII( + RegionInterface.getTraceGenerators(), + RTLDeviceID, HstPtr, &TargetPtr, Size, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) TargetPtr = RTL->data_alloc(RTLDeviceID, Size, HstPtr, Kind); return TargetPtr; @@ -204,11 +219,15 @@ void *DeviceTy::allocData(int64_t Size, void *HstPtr, int32_t Kind) { int32_t DeviceTy::deleteData(void *TgtAllocBegin, int32_t Kind) { /// RAII to establish tool anchors before and after data deletion - OMPT_IF_BUILT(InterfaceRAII TargetDataDeleteRAII( - RegionInterface.getCallbacks(), - DeviceID, TgtAllocBegin, - /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) - + OMPT_IF_BUILT( + InterfaceRAII TargetDataDeleteRAII( + RegionInterface.getCallbacks(), DeviceID, + TgtAllocBegin, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS); + InterfaceRAII TargetDataDeleteTraceRAII( + RegionInterface.getTraceGenerators(), + DeviceID, TgtAllocBegin, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) return RTL->data_delete(RTLDeviceID, TgtAllocBegin, Kind); } @@ -225,8 +244,18 @@ int32_t DeviceTy::submitData(void *TgtPtrBegin, void *HstPtrBegin, int64_t Size, InterfaceRAII TargetDataSubmitRAII( RegionInterface.getCallbacks(), omp_get_initial_device(), HstPtrBegin, DeviceID, TgtPtrBegin, Size, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS); + // Only if 'TracedDeviceId' is actually traced, AsyncInfo->OmptEventInfo + // is set and a trace record generated. Otherwise: No OMPT device tracing. + TracerInterfaceRAII TargetDataSubmitTraceRAII( + RegionInterface + .getTraceGenerators(), + AsyncInfo, RTL->getProfiler(), /*TracedDeviceId=*/DeviceID, + /*EventType=*/ompt_callback_target_data_op, omp_get_initial_device(), + HstPtrBegin, DeviceID, TgtPtrBegin, Size, /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) + setAsyncInfoSynchronous(AsyncInfo, ForceSynchronousTargetRegions); return RTL->data_submit_async(RTLDeviceID, TgtPtrBegin, HstPtrBegin, Size, AsyncInfo); } @@ -245,8 +274,18 @@ int32_t DeviceTy::retrieveData(void *HstPtrBegin, void *TgtPtrBegin, InterfaceRAII TargetDataRetrieveRAII( RegionInterface.getCallbacks(), DeviceID, TgtPtrBegin, omp_get_initial_device(), HstPtrBegin, Size, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS); + // Only if 'TracedDeviceId' is actually traced, AsyncInfo->OmptEventInfo + // is set and a trace record generated. Otherwise: No OMPT device tracing. + TracerInterfaceRAII TargetDataSubmitTraceRAII( + RegionInterface + .getTraceGenerators(), + AsyncInfo, RTL->getProfiler(), /*TracedDeviceId=*/DeviceID, + /*EventType=*/ompt_callback_target_data_op, DeviceID, TgtPtrBegin, + omp_get_initial_device(), HstPtrBegin, Size, /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) + setAsyncInfoSynchronous(AsyncInfo, ForceSynchronousTargetRegions); return RTL->data_retrieve_async(RTLDeviceID, HstPtrBegin, TgtPtrBegin, Size, AsyncInfo); } @@ -264,11 +303,18 @@ int32_t DeviceTy::dataExchange(void *SrcPtr, DeviceTy &DstDev, void *DstPtr, InterfaceRAII TargetDataExchangeRAII( RegionInterface.getCallbacks(), RTLDeviceID, SrcPtr, DstDev.RTLDeviceID, DstPtr, Size, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS); + // Only if 'TracedDeviceId' is actually traced, AsyncInfo->OmptEventInfo + // is set and a trace record generated. Otherwise: No OMPT device tracing. + TracerInterfaceRAII TargetDataExchangeTraceRAII( + RegionInterface + .getTraceGenerators(), + AsyncInfo, RTL->getProfiler(), /*TracedDeviceId=*/RTLDeviceID, + /*EventType=*/ompt_callback_target_data_op, RTLDeviceID, SrcPtr, + DstDev.RTLDeviceID, DstPtr, Size, /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) - if (!AsyncInfo) { - return RTL->data_exchange(RTLDeviceID, SrcPtr, DstDev.RTLDeviceID, DstPtr, - Size); - } + + setAsyncInfoSynchronous(AsyncInfo, ForceSynchronousTargetRegions); return RTL->data_exchange_async(RTLDeviceID, SrcPtr, DstDev.RTLDeviceID, DstPtr, Size, AsyncInfo); } @@ -302,6 +348,8 @@ int32_t DeviceTy::notifyDataUnmapped(void *HstPtr) { int32_t DeviceTy::launchKernel(void *TgtEntryPtr, void **TgtVarsPtr, ptrdiff_t *TgtOffsets, KernelArgsTy &KernelArgs, AsyncInfoTy &AsyncInfo) { + + setAsyncInfoSynchronous(AsyncInfo, ForceSynchronousTargetRegions); return RTL->launch_kernel(RTLDeviceID, TgtEntryPtr, TgtVarsPtr, TgtOffsets, &KernelArgs, AsyncInfo); } @@ -365,9 +413,32 @@ void DeviceTy::dumpOffloadEntries() { bool DeviceTy::useAutoZeroCopy() { if (PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY) return false; + return RTL->use_auto_zero_copy(RTLDeviceID); } +bool DeviceTy::checkIfAPU() { return RTL->has_apu_device(RTLDeviceID); } + +bool DeviceTy::supportsUnifiedMemory() { + return RTL->supports_unified_memory(RTLDeviceID); +} + +void DeviceTy::zeroCopySanityChecksAndDiag(bool isUnifiedSharedMemory, + bool isAutoZeroCopy, + bool isEagerMaps) { + RTL->zero_copy_sanity_checks_and_diag(RTLDeviceID, isUnifiedSharedMemory, + isAutoZeroCopy, isEagerMaps); +} + +uint32_t DeviceTy::getNumMultiDevices() const { + return RTL->get_num_multi_devices(RTLDeviceID); +} + +// Check if kernel is a multi device kernel +bool DeviceTy::isMultiDeviceKernel(void *TgtEntryPtr) { + return RTL->kernel_is_multi_device(RTLDeviceID, TgtEntryPtr); +} + bool DeviceTy::isAccessiblePtr(const void *Ptr, size_t Size) { return RTL->is_accessible_ptr(RTLDeviceID, Ptr, Size); } diff --git a/offload/libomptarget/exports b/offload/libomptarget/exports index 910a5b6c827a7..6a9afd6534a1a 100644 --- a/offload/libomptarget/exports +++ b/offload/libomptarget/exports @@ -35,6 +35,7 @@ VERS1.0 { __tgt_push_mapper_component; __kmpc_push_target_tripcount; __kmpc_push_target_tripcount_mapper; + ompx_get_team_procs; ompx_dump_mapping_tables; ompx_interop_add_completion_callback; omp_get_mapped_ptr; @@ -53,9 +54,22 @@ VERS1.0 { omp_target_memset_async; omp_target_associate_ptr; omp_target_disassociate_ptr; + __kmpc_push_target_tripcount; + printf_allocate; + printf_execute; + global_allocate; + global_free; + f90print*; + __ockl_dm_alloc; + __ockl_dm_dealloc; + __ockl_devmem_request; llvm_omp_target_alloc_host; llvm_omp_target_alloc_shared; llvm_omp_target_alloc_device; + llvm_omp_target_alloc_multi_devices; + llvm_omp_target_lock_mem; + llvm_omp_target_unlock_mem; + llvm_omp_get_dynamic_shared; llvm_omp_target_free_host; llvm_omp_target_free_shared; llvm_omp_target_free_device; @@ -64,6 +78,16 @@ VERS1.0 { llvm_omp_target_unlock_mem; __tgt_set_info_flag; __tgt_print_device_info; + omp_is_coarse_grain_mem_region; + omp_register_coarse_grain_mem; + libomptarget_ompt_set_trace_ompt; + libomptarget_ompt_start_trace; + libomptarget_ompt_flush_trace; + libomptarget_ompt_stop_trace; + libomptarget_ompt_set_granted_teams; + libomptarget_ompt_set_timestamp; + libomptarget_ompt_advance_buffer_cursor; + libomptarget_ompt_get_record_type; omp_get_interop_ptr; omp_get_interop_str; omp_get_interop_int; @@ -79,6 +103,10 @@ VERS1.0 { __llvmPushCallConfiguration; __llvmPopCallConfiguration; llvmLaunchKernel; + EmissaryBuildVargs; + EmissaryHDF5; + EmissaryReserve; + EmissaryMPI; local: *; }; diff --git a/offload/libomptarget/interface.cpp b/offload/libomptarget/interface.cpp index fe18289765906..487d4b4568901 100644 --- a/offload/libomptarget/interface.cpp +++ b/offload/libomptarget/interface.cpp @@ -14,11 +14,13 @@ #include "OpenMP/OMPT/Interface.h" #include "OffloadPolicy.h" #include "OpenMP/OMPT/Callback.h" +#include "OpenMP/OMPT/OmptCommonDefs.h" #include "OpenMP/omp.h" #include "PluginManager.h" #include "omptarget.h" #include "private.h" +#include "Shared/APITypes.h" #include "Shared/EnvironmentVar.h" #include "Shared/Profile.h" @@ -32,6 +34,8 @@ #include #include +using llvm::SmallVector; + #ifdef OMPT_SUPPORT using namespace llvm::omp::target::ompt; #endif @@ -104,6 +108,7 @@ EXTERN void __tgt_init_all_rtls() { //////////////////////////////////////////////////////////////////////////////// /// unloads a target shared library EXTERN void __tgt_unregister_lib(__tgt_bin_desc *Desc) { + TIMESCOPE(); PM->unregisterLib(Desc); deinitRuntime(); @@ -120,8 +125,7 @@ targetData(ident_t *Loc, int64_t DeviceId, int32_t ArgNum, void **ArgsBase, static_assert(std::is_convertible_v, "TargetAsyncInfoTy must be convertible to AsyncInfoTy."); - TIMESCOPE_WITH_DETAILS_AND_IDENT("Runtime: Data Copy", - "NumArgs=" + std::to_string(ArgNum), Loc); + TIMESCOPE_WITH_RTM_AND_IDENT(RegionTypeMsg, Loc); DP("Entering data %s region for device %" PRId64 " with %d mappings\n", RegionName, DeviceId, ArgNum); @@ -151,19 +155,30 @@ targetData(ident_t *Loc, int64_t DeviceId, int32_t ArgNum, void **ArgsBase, AsyncInfoTy &AsyncInfo = TargetAsyncInfo; /// RAII to establish tool anchors before and after data begin / end / update - OMPT_IF_BUILT(assert((TargetDataFunction == targetDataBegin || - TargetDataFunction == targetDataEnd || - TargetDataFunction == targetDataUpdate) && - "Encountered unexpected TargetDataFunction during " - "execution of targetData"); - auto CallbackFunctions = - (TargetDataFunction == targetDataBegin) - ? RegionInterface.getCallbacks() - : (TargetDataFunction == targetDataEnd) - ? RegionInterface.getCallbacks() - : RegionInterface.getCallbacks(); - InterfaceRAII TargetDataRAII(CallbackFunctions, DeviceId, - OMPT_GET_RETURN_ADDRESS);) + OMPT_IF_BUILT( + assert((TargetDataFunction == targetDataBegin || + TargetDataFunction == targetDataEnd || + TargetDataFunction == targetDataUpdate) && + "Encountered unexpected TargetDataFunction during " + "execution of targetData"); + auto CallbackFunctions = + (TargetDataFunction == targetDataBegin) + ? RegionInterface.getCallbacks() + : (TargetDataFunction == targetDataEnd) + ? RegionInterface.getCallbacks() + : RegionInterface.getCallbacks(); + + auto TraceGenerators = + (TargetDataFunction == targetDataBegin) + ? RegionInterface.getTraceGenerators() + : (TargetDataFunction == targetDataEnd) + ? RegionInterface.getTraceGenerators() + : RegionInterface.getTraceGenerators(); + + InterfaceRAII TargetDataRAII(CallbackFunctions, DeviceId, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS); + InterfaceRAII TargetDataTraceRAII(TraceGenerators, DeviceId, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) int Rc = OFFLOAD_SUCCESS; @@ -197,6 +212,7 @@ EXTERN void __tgt_target_data_begin_mapper(ident_t *Loc, int64_t DeviceId, int64_t *ArgTypes, map_var_info_t *ArgNames, void **ArgMappers) { + TIMESCOPE_WITH_IDENT(Loc); OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); targetData(Loc, DeviceId, ArgNum, ArgsBase, Args, ArgSizes, ArgTypes, ArgNames, ArgMappers, targetDataBegin, @@ -225,6 +241,7 @@ EXTERN void __tgt_target_data_end_mapper(ident_t *Loc, int64_t DeviceId, int64_t *ArgTypes, map_var_info_t *ArgNames, void **ArgMappers) { + TIMESCOPE_WITH_IDENT(Loc); OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); targetData(Loc, DeviceId, ArgNum, ArgsBase, Args, ArgSizes, ArgTypes, ArgNames, ArgMappers, targetDataEnd, @@ -249,6 +266,7 @@ EXTERN void __tgt_target_data_update_mapper(ident_t *Loc, int64_t DeviceId, int64_t *ArgTypes, map_var_info_t *ArgNames, void **ArgMappers) { + TIMESCOPE_WITH_IDENT(Loc); OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); targetData( Loc, DeviceId, ArgNum, ArgsBase, Args, ArgSizes, ArgTypes, ArgNames, @@ -326,6 +344,20 @@ static inline int targetKernel(ident_t *Loc, int64_t DeviceId, int32_t NumTeams, assert(PM && "Runtime not initialized"); static_assert(std::is_convertible_v, "Target AsyncInfoTy must be convertible to AsyncInfoTy."); + + // Target multiple devices if the user requests more than 1 device. The + // variable below tracks the number of EXTRA devices that are going to be + // used other than the first device. + int32_t NumMultiDevices = 0; + char *SplitFactor = getenv("LIBOMPTARGET_NUM_MULTI_DEVICES"); + if (SplitFactor) { + NumMultiDevices = atoi(SplitFactor) - 1; + + // In multi-device mode the default device is always 0. + if (DeviceId == -1) + DeviceId = 0; + } + DP("Entering target region for device %" PRId64 " with entry point " DPxMOD "\n", DeviceId, DPxPTR(HostPtr)); @@ -355,7 +387,7 @@ static inline int targetKernel(ident_t *Loc, int64_t DeviceId, int32_t NumTeams, KernelArgs->ArgSizes, KernelArgs->ArgTypes, KernelArgs->ArgNames, "Entering OpenMP kernel"); #ifdef OMPTARGET_DEBUG - for (uint32_t I = 0; I < KernelArgs->NumArgs; ++I) { + for (int I = 0; I < KernelArgs->NumArgs; ++I) { DP("Entry %2d: Base=" DPxMOD ", Begin=" DPxMOD ", Size=%" PRId64 ", Type=0x%" PRIx64 ", Name=%s\n", I, DPxPTR(KernelArgs->ArgBasePtrs[I]), DPxPTR(KernelArgs->ArgPtrs[I]), @@ -372,21 +404,96 @@ static inline int targetKernel(ident_t *Loc, int64_t DeviceId, int32_t NumTeams, TargetAsyncInfoTy TargetAsyncInfo(*DeviceOrErr); AsyncInfoTy &AsyncInfo = TargetAsyncInfo; - /// RAII to establish tool anchors before and after target region OMPT_IF_BUILT(InterfaceRAII TargetRAII( RegionInterface.getCallbacks(), DeviceId, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS); + InterfaceRAII TargetTraceRAII( + RegionInterface.getTraceGenerators(), DeviceId, /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) int Rc = OFFLOAD_SUCCESS; - Rc = target(Loc, *DeviceOrErr, HostPtr, *KernelArgs, AsyncInfo); - { // required to show synchronization - TIMESCOPE_WITH_DETAILS_AND_IDENT("Runtime: synchronize", "", Loc); - if (Rc == OFFLOAD_SUCCESS) - Rc = AsyncInfo.synchronize(); + bool IsMultiDeviceKernel = false; + Rc = target(Loc, *DeviceOrErr, HostPtr, *KernelArgs, AsyncInfo, + /*InMultiDeviceMode*/ NumMultiDevices > 0, IsMultiDeviceKernel); + + // Check if this is a multi-device kernel. + SmallVector TargetAsyncInfos; + if (IsMultiDeviceKernel) { + // Check whether we have enough iterations for multiple devices, if we do + // not then we execute on one device. If the kernel does not have at least + // two arguments it means the loop bounds have not been passed in so we + // cannot execute on multiple devices. + if (NumMultiDevices > 0 && (KernelArgs->Tripcount < (NumMultiDevices + 1) || + KernelArgs->NumArgs < 2)) + NumMultiDevices = 0; + + // The first device used by the multi-device infrastructure: + int32_t FirstDeviceId = DeviceId + 1; + + // Launch kernel on one or across multiple devices. + for (int64_t DeviceIndex = FirstDeviceId; + DeviceIndex < FirstDeviceId + NumMultiDevices; DeviceIndex++) { + DP("Entering target region for device %" PRId64 + " with entry point " DPxMOD "\n", + DeviceIndex, DPxPTR(HostPtr)); + + if (checkDevice(DeviceIndex, Loc)) { + DP("Not offloading to device %" PRId64 "\n", DeviceIndex); + return OMP_TGT_FAIL; + } + + if (getInfoLevel() & OMP_INFOTYPE_KERNEL_ARGS) + printKernelArguments(Loc, DeviceIndex, KernelArgs->NumArgs, + KernelArgs->ArgSizes, KernelArgs->ArgTypes, + KernelArgs->ArgNames, "Entering OpenMP kernel"); +#ifdef OMPTARGET_DEBUG + for (int I = 0; I < KernelArgs->NumArgs; ++I) { + DP("Entry %2d: Base=" DPxMOD ", Begin=" DPxMOD ", Size=%" PRId64 + ", Type=0x%" PRIx64 ", Name=%s\n", + I, DPxPTR(KernelArgs->ArgBasePtrs[I]), + DPxPTR(KernelArgs->ArgPtrs[I]), KernelArgs->ArgSizes[I], + KernelArgs->ArgTypes[I], + (KernelArgs->ArgNames) + ? getNameFromMapping(KernelArgs->ArgNames[I]).c_str() + : "unknown"); + } +#endif + + auto DeviceOrErr = PM->getDevice(DeviceIndex); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceIndex, "%s", + toString(DeviceOrErr.takeError()).c_str()); + + TargetAsyncInfoTy *LocalTAI = new TargetAsyncInfoTy(*DeviceOrErr); + AsyncInfoTy &AsyncInfoMD = *LocalTAI; + TargetAsyncInfos.emplace_back(LocalTAI); - handleTargetOutcome(Rc == OFFLOAD_SUCCESS, Loc); - assert(Rc == OFFLOAD_SUCCESS && "__tgt_target_kernel unexpected failure!"); + // No need to check the global multi device value for this kernel. + if (target(Loc, *DeviceOrErr, HostPtr, *KernelArgs, AsyncInfoMD, false, + IsMultiDeviceKernel) != OFFLOAD_SUCCESS) + Rc = OFFLOAD_FAIL; + } } + + int PostSyncRc = Rc; + if (Rc == OFFLOAD_SUCCESS) { + PostSyncRc = AsyncInfo.synchronize(); + for (TargetAsyncInfoTy *LocalTAI : TargetAsyncInfos) { + AsyncInfoTy &AsyncInfo = *LocalTAI; + if (AsyncInfo.synchronize() != OFFLOAD_SUCCESS) + PostSyncRc = OFFLOAD_FAIL; + } + } + + // Deallocate the multi-device async infos if any were allocated. + for (TargetAsyncInfoTy *LocalTAI : TargetAsyncInfos) + delete LocalTAI; + + handleTargetOutcome(PostSyncRc == OFFLOAD_SUCCESS, Loc); + assert(PostSyncRc == OFFLOAD_SUCCESS && "offload failed"); + assert(PostSyncRc == OFFLOAD_SUCCESS && + "__tgt_target_kernel unexpected failure!"); + return OMP_TGT_SUCCESS; } @@ -473,6 +580,9 @@ EXTERN int __tgt_target_kernel_replay(ident_t *Loc, int64_t DeviceId, /// RAII to establish tool anchors before and after target region OMPT_IF_BUILT(InterfaceRAII TargetRAII( RegionInterface.getCallbacks(), DeviceId, + /*CodePtr=*/OMPT_GET_RETURN_ADDRESS); + InterfaceRAII TargetTraceRAII( + RegionInterface.getTraceGenerators(), DeviceId, /*CodePtr=*/OMPT_GET_RETURN_ADDRESS);) AsyncInfoTy AsyncInfo(*DeviceOrErr); @@ -489,6 +599,8 @@ EXTERN int __tgt_target_kernel_replay(ident_t *Loc, int64_t DeviceId, // Get the current number of components for a user-defined mapper. EXTERN int64_t __tgt_mapper_num_components(void *RtMapperHandle) { + TIMESCOPE(); + OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); auto *MapperComponentsPtr = (struct MapperComponentsTy *)RtMapperHandle; int64_t Size = MapperComponentsPtr->Components.size(); DP("__tgt_mapper_num_components(Handle=" DPxMOD ") returns %" PRId64 "\n", @@ -500,6 +612,8 @@ EXTERN int64_t __tgt_mapper_num_components(void *RtMapperHandle) { EXTERN void __tgt_push_mapper_component(void *RtMapperHandle, void *Base, void *Begin, int64_t Size, int64_t Type, void *Name) { + TIMESCOPE(); + OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); DP("__tgt_push_mapper_component(Handle=" DPxMOD ") adds an entry (Base=" DPxMOD ", Begin=" DPxMOD ", Size=%" PRId64 ", Type=0x%" PRIx64 ", Name=%s).\n", @@ -512,12 +626,14 @@ EXTERN void __tgt_push_mapper_component(void *RtMapperHandle, void *Base, EXTERN void __tgt_set_info_flag(uint32_t NewInfoLevel) { assert(PM && "Runtime not initialized"); + OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); std::atomic &InfoLevel = getInfoLevelInternal(); InfoLevel.store(NewInfoLevel); } EXTERN int __tgt_print_device_info(int64_t DeviceId) { assert(PM && "Runtime not initialized"); + OMPT_IF_BUILT(ReturnAddressSetterRAII RA(__builtin_return_address(0))); auto DeviceOrErr = PM->getDevice(DeviceId); if (!DeviceOrErr) FATAL_MESSAGE(DeviceId, "%s", toString(DeviceOrErr.takeError()).c_str()); diff --git a/offload/libomptarget/omptarget.cpp b/offload/libomptarget/omptarget.cpp index 69725e77bae00..1753917667fb4 100644 --- a/offload/libomptarget/omptarget.cpp +++ b/offload/libomptarget/omptarget.cpp @@ -18,11 +18,11 @@ #include "PluginManager.h" #include "Shared/Debug.h" #include "Shared/EnvironmentVar.h" -#include "Shared/Utils.h" #include "device.h" #include "private.h" #include "rtl.h" +#include "Shared/APITypes.h" #include "Shared/Profile.h" #include "OpenMP/Mapping.h" @@ -38,6 +38,7 @@ #include using llvm::SmallVector; + #ifdef OMPT_SUPPORT using namespace llvm::omp::target::ompt; #endif @@ -148,32 +149,10 @@ void handleTargetOutcome(bool Success, ident_t *Loc) { FAILURE_MESSAGE("Consult https://openmp.llvm.org/design/Runtimes.html " "for debugging options.\n"); - if (!PM->getNumActivePlugins()) { + if (!PM->getNumActivePlugins()) FAILURE_MESSAGE( "No images found compatible with the installed hardware. "); - llvm::SmallVector Archs; - for (auto &Image : PM->deviceImages()) { - const char *Start = reinterpret_cast( - Image.getExecutableImage().ImageStart); - uint64_t Length = - utils::getPtrDiff(Start, Image.getExecutableImage().ImageEnd); - llvm::MemoryBufferRef Buffer(llvm::StringRef(Start, Length), - /*Identifier=*/""); - - auto ObjectOrErr = llvm::object::ObjectFile::createObjectFile(Buffer); - if (auto Err = ObjectOrErr.takeError()) { - llvm::consumeError(std::move(Err)); - continue; - } - - if (auto CPU = (*ObjectOrErr)->tryGetCPUName()) - Archs.push_back(*CPU); - } - fprintf(stderr, "Found %zu image(s): (%s)\n", Archs.size(), - llvm::join(Archs, ",").c_str()); - } - SourceInfo Info(Loc); if (Info.isAvailible()) fprintf(stderr, "%s:%d:%d: ", Info.getFilename(), Info.getLine(), @@ -306,11 +285,11 @@ int targetDataMapper(ident_t *Loc, DeviceTy &Device, void *ArgBase, void *Arg, // Construct new arrays for args_base, args, arg_sizes and arg_types // using the information in MapperComponents and call the corresponding // targetData* function using these new arrays. - SmallVector MapperArgsBase(MapperComponents.Components.size()); - SmallVector MapperArgs(MapperComponents.Components.size()); - SmallVector MapperArgSizes(MapperComponents.Components.size()); - SmallVector MapperArgTypes(MapperComponents.Components.size()); - SmallVector MapperArgNames(MapperComponents.Components.size()); + std::vector MapperArgsBase(MapperComponents.Components.size()); + std::vector MapperArgs(MapperComponents.Components.size()); + std::vector MapperArgSizes(MapperComponents.Components.size()); + std::vector MapperArgTypes(MapperComponents.Components.size()); + std::vector MapperArgNames(MapperComponents.Components.size()); for (unsigned I = 0, E = MapperComponents.Components.size(); I < E; ++I) { auto &C = MapperComponents.Components[I]; @@ -618,10 +597,10 @@ int targetDataBegin(ident_t *Loc, DeviceTy &Device, int32_t ArgNum, // when HasPresentModifier. PointerTpr = Device.getMappingInfo().getTargetPointer( HDTTMap, HstPtrBase, HstPtrBase, /*TgtPadding=*/0, sizeof(void *), - /*HstPtrName=*/nullptr, - /*HasFlagTo=*/false, /*HasFlagAlways=*/false, IsImplicit, UpdateRef, - HasCloseModifier, HasPresentModifier, HasHoldModifier, AsyncInfo, - /*OwnedTPR=*/nullptr, /*ReleaseHDTTMap=*/false); + ArgTypes[I], /*HstPtrName=*/nullptr, /*HasFlagTo=*/false, + /*HasFlagAlways=*/false, IsImplicit, UpdateRef, HasCloseModifier, + HasPresentModifier, HasHoldModifier, AsyncInfo, /*OwnedTPR=*/nullptr, + /*ReleaseHDTTMap=*/false); PointerTgtPtrBegin = PointerTpr.TargetPointer; IsHostPtr = PointerTpr.Flags.IsHostPointer; if (!PointerTgtPtrBegin) { @@ -644,17 +623,18 @@ int targetDataBegin(ident_t *Loc, DeviceTy &Device, int32_t ArgNum, HstPtrBase = *reinterpret_cast(HstPtrBase); // No need to update pointee ref count for the first element of the // subelement that comes from mapper. - UpdateRef = - (!FromMapper || I != 0); // subsequently update ref count of pointee + // subsequently update ref count of pointee + UpdateRef = (!FromMapper || I != 0); } const bool HasFlagTo = ArgTypes[I] & OMP_TGT_MAPTYPE_TO; const bool HasFlagAlways = ArgTypes[I] & OMP_TGT_MAPTYPE_ALWAYS; // Note that HDTTMap will be released in getTargetPointer. auto TPR = Device.getMappingInfo().getTargetPointer( - HDTTMap, HstPtrBegin, HstPtrBase, TgtPadding, DataSize, HstPtrName, - HasFlagTo, HasFlagAlways, IsImplicit, UpdateRef, HasCloseModifier, - HasPresentModifier, HasHoldModifier, AsyncInfo, PointerTpr.getEntry()); + HDTTMap, HstPtrBegin, HstPtrBase, TgtPadding, DataSize, ArgTypes[I], + HstPtrName, HasFlagTo, HasFlagAlways, IsImplicit, UpdateRef, + HasCloseModifier, HasPresentModifier, HasHoldModifier, AsyncInfo, + PointerTpr.getEntry()); void *TgtPtrBegin = TPR.TargetPointer; IsHostPtr = TPR.Flags.IsHostPointer; // If data_size==0, then the argument could be a zero-length pointer to @@ -670,9 +650,10 @@ int targetDataBegin(ident_t *Loc, DeviceTy &Device, int32_t ArgNum, if (TPR.Flags.IsNewEntry && !IsHostPtr && TgtPtrBegin) AttachInfo->NewAllocations[HstPtrBegin] = DataSize; - DP("There are %" PRId64 " bytes allocated at target address " DPxMOD + DP("There are %" PRId64 " bytes allocated at %s address " DPxMOD " - is%s new\n", - DataSize, DPxPTR(TgtPtrBegin), (TPR.Flags.IsNewEntry ? "" : " not")); + DataSize, (IsHostPtr ? "host" : "target"), DPxPTR(TgtPtrBegin), + (TPR.Flags.IsNewEntry ? "" : " not")); if (ArgTypes[I] & OMP_TGT_MAPTYPE_RETURN_PARAM) { uintptr_t Delta = (uintptr_t)HstPtrBegin - (uintptr_t)HstPtrBase; @@ -681,7 +662,16 @@ int targetDataBegin(ident_t *Loc, DeviceTy &Device, int32_t ArgNum, ArgsBase[I] = TgtPtrBase; } - if (ArgTypes[I] & OMP_TGT_MAPTYPE_PTR_AND_OBJ && !IsHostPtr) { + // The || part of the if condition covers flang dope vectors that + // have different host and target addresses when USM is enabled. The + // pointer to the array is IsHostPtr but the dope vector is not. + // This happens with dope vectors in Fortran modules. + // The pointer has to be copied into the + // target dope vector. + // Perhaps OMP_TGT_MAPTYPE_DESCRIPTOR would help here, not sure. + if ((ArgTypes[I] & OMP_TGT_MAPTYPE_PTR_AND_OBJ) && + (!IsHostPtr || (PointerTpr.getEntry() != nullptr && + PointerHstPtrBegin != PointerTgtPtrBegin))) { int Ret = performPointerAttachment( Device, AsyncInfo, reinterpret_cast(PointerHstPtrBegin), HstPtrBase, HstPtrBegin, @@ -964,6 +954,11 @@ postProcessingTargetDataEnd(DeviceTy *Device, const bool HasFrom = ArgType & OMP_TGT_MAPTYPE_FROM; if (HasFrom) { Entry->foreachShadowPointerInfo([&](const ShadowPtrInfoTy &ShadowPtr) { + const bool isZeroCopy = PM->getRequirements() & OMPX_REQ_AUTO_ZERO_COPY; + const bool isUSMMode = + PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY; + if (*ShadowPtr.HstPtrAddr == nullptr || isZeroCopy || isUSMMode) + return OFFLOAD_SUCCESS; constexpr int64_t VoidPtrSize = sizeof(void *); if (ShadowPtr.PtrSize > VoidPtrSize) { DP("Restoring host descriptor " DPxMOD @@ -1236,6 +1231,12 @@ static int targetDataContiguous(ident_t *Loc, DeviceTy &Device, void *ArgsBase, AsyncInfo.addPostProcessingFunction([=]() -> int { int Ret = Entry->foreachShadowPointerInfo( [&](const ShadowPtrInfoTy &ShadowPtr) { + const bool isZeroCopy = + PM->getRequirements() & OMPX_REQ_AUTO_ZERO_COPY; + const bool isUSMMode = + PM->getRequirements() & OMP_REQ_UNIFIED_SHARED_MEMORY; + if (*ShadowPtr.HstPtrAddr == nullptr || isZeroCopy || isUSMMode) + return OFFLOAD_SUCCESS; constexpr int64_t VoidPtrSize = sizeof(void *); if (ShadowPtr.PtrSize > VoidPtrSize) { DP("Restoring host descriptor " DPxMOD @@ -1449,12 +1450,12 @@ class PrivateArgumentManagerTy { }; /// A vector of target pointers for all private arguments - SmallVector TgtPtrs; + std::vector TgtPtrs; /// A vector of information of all first-private arguments to be packed - SmallVector FirstPrivateArgInfo; + std::vector FirstPrivateArgInfo; /// Host buffer for all arguments to be packed - SmallVector FirstPrivateArgBuffer; + std::vector FirstPrivateArgBuffer; /// The total size of all arguments to be packed int64_t FirstPrivateArgSize = 0; @@ -1724,7 +1725,7 @@ class PrivateArgumentManagerTy { assert(FirstPrivateArgSize != 0 && "FirstPrivateArgSize is 0 but FirstPrivateArgInfo is empty"); FirstPrivateArgBuffer.resize(FirstPrivateArgSize, 0); - auto *Itr = FirstPrivateArgBuffer.begin(); + auto Itr = FirstPrivateArgBuffer.begin(); // Copy all host data to this buffer for (FirstPrivateArgInfoTy &Info : FirstPrivateArgInfo) { // First pad the pointer as we (have to) pad it on the device too. @@ -1828,7 +1829,7 @@ static int processDataBefore(ident_t *Loc, int64_t DeviceId, void *HostPtr, } // List of (first-)private arrays allocated for this target region - SmallVector TgtArgsPositions(ArgNum, -1); + std::vector TgtArgsPositions(ArgNum, -1); for (int32_t I = 0; I < ArgNum; ++I) { if (!(ArgTypes[I] & OMP_TGT_MAPTYPE_TARGET_PARAM)) { @@ -2020,7 +2021,8 @@ static int processDataAfter(ident_t *Loc, int64_t DeviceId, void *HostPtr, /// returns 0 if it was able to transfer the execution to a target and an /// integer different from zero otherwise. int target(ident_t *Loc, DeviceTy &Device, void *HostPtr, - KernelArgsTy &KernelArgs, AsyncInfoTy &AsyncInfo) { + KernelArgsTy &KernelArgs, AsyncInfoTy &AsyncInfo, + bool InMultiDeviceMode, bool &IsMultiDeviceKernel) { int32_t DeviceId = Device.DeviceID; TableMap *TM = getTableMap(HostPtr); // No map for this host pointer found! @@ -2098,12 +2100,30 @@ int target(ident_t *Loc, DeviceTy &Device, void *HostPtr, // No need to guard this with OMPT_IF_BUILT InterfaceRAII TargetSubmitRAII( RegionInterface.getCallbacks(), NumTeams); -#endif + // Calls "begin" for the OMPT trace record and let the plugin + // enqueue the stop operation for after the kernel is done. The stop + // operation completes the trace record entry with the information from + // within the plugin, eg., kernel timing info. + // Only if 'TracedDeviceId' is actually traced, AsyncInfo->OmptEventInfo is + // set and a trace record generated. Otherwise: No OMPT device tracing. + TracerInterfaceRAII TargetTraceRAII( + RegionInterface.getTraceGenerators(), + AsyncInfo, Device.RTL->getProfiler(), /*TracedDeviceId=*/DeviceId, + /*EventType=*/ompt_callback_target_submit, DeviceId, NumTeams); +#endif Ret = Device.launchKernel(TgtEntryPtr, TgtArgs.data(), TgtOffsets.data(), KernelArgs, AsyncInfo); + + // If we are in multidevice mode the check the value of the global variable + // for this kernel to see if the kernel is indeed a multi device kernel. + if (InMultiDeviceMode) + IsMultiDeviceKernel = Device.isMultiDeviceKernel(TgtEntryPtr); } + // Reset number of arguments just in case the kernel launch changed it. + KernelArgs.NumArgs = NumClangLaunchArgs; + if (Ret != OFFLOAD_SUCCESS) { REPORT("Executing target region abort target.\n"); return OFFLOAD_FAIL; diff --git a/offload/libomptarget/private.h b/offload/libomptarget/private.h index 90e5e1780e666..4e95a336be295 100644 --- a/offload/libomptarget/private.h +++ b/offload/libomptarget/private.h @@ -24,7 +24,8 @@ #include extern int target(ident_t *Loc, DeviceTy &Device, void *HostPtr, - KernelArgsTy &KernelArgs, AsyncInfoTy &AsyncInfo); + KernelArgsTy &KernelArgs, AsyncInfoTy &AsyncInfo, + bool InMultiDeviceMode, bool &IsMultiDeviceKernel); extern int target_activate_rr(DeviceTy &Device, uint64_t MemorySize, void *ReqAddr, bool isRecord, bool SaveOutput, @@ -37,6 +38,7 @@ extern int target_replay(ident_t *Loc, DeviceTy &Device, void *HostPtr, uint64_t LoopTripCount, AsyncInfoTy &AsyncInfo); extern void handleTargetOutcome(bool Success, ident_t *Loc); +extern bool checkDevice(int64_t &DeviceID, ident_t *Loc); //////////////////////////////////////////////////////////////////////////////// /// Print out the names and properties of the arguments to each kernel diff --git a/offload/plugins-nextgen/CMakeLists.txt b/offload/plugins-nextgen/CMakeLists.txt index a72befd9416b7..4a3a5ee0ddb10 100644 --- a/offload/plugins-nextgen/CMakeLists.txt +++ b/offload/plugins-nextgen/CMakeLists.txt @@ -5,6 +5,7 @@ add_subdirectory(common) function(add_target_library target_name lib_name) add_llvm_library(${target_name} STATIC LINK_COMPONENTS + ${LLVM_TARGETS_TO_BUILD} AggressiveInstCombine Analysis BinaryFormat @@ -38,8 +39,12 @@ function(add_target_library target_name lib_name) llvm_update_compile_flags(${target_name}) target_include_directories(${target_name} PUBLIC ${common_dir}/include ${common_bin_dir}/include) + if(OMPT_TARGET_DEFAULT AND LIBOMPTARGET_OMPT_SUPPORT) + target_include_directories(${target_name} PUBLIC ${common_dir}/OMPT) + endif() + target_link_libraries(${target_name} PRIVATE - PluginCommon ${OPENMP_PTHREAD_LIB}) + PluginCommon ${llvm_libs} ${OPENMP_PTHREAD_LIB}) target_compile_definitions(${target_name} PRIVATE TARGET_NAME=${lib_name}) target_compile_definitions(${target_name} PRIVATE diff --git a/offload/plugins-nextgen/amdgpu/CMakeLists.txt b/offload/plugins-nextgen/amdgpu/CMakeLists.txt index 47cd2feefc728..c434c0a4396d9 100644 --- a/offload/plugins-nextgen/amdgpu/CMakeLists.txt +++ b/offload/plugins-nextgen/amdgpu/CMakeLists.txt @@ -1,5 +1,33 @@ -# As of rocm-3.7, hsa is installed with cmake packages and kmt is found via hsa -find_package(hsa-runtime64 QUIET 1.2.0 HINTS ${CMAKE_INSTALL_PREFIX} PATHS /opt/rocm) +################################################################################ +set(LIBOMPTARGET_BUILD_AMDGPU_PLUGIN TRUE CACHE BOOL + "Whether to build AMDGPU plugin") +if (NOT LIBOMPTARGET_BUILD_AMDGPU_PLUGIN) + message(STATUS "Not building AMDGPU NextGen offloading plugin: LIBOMPTARGET_BUILD_AMDGPU_PLUGIN is false") + return() +endif() + +# If we are bootstrapping hsa via external project we need to use find_library +# as it will not be installed. +if(DEFINED LIBOMPTARGET_EXTERNAL_PROJECT_HSA_PATH) + if(OFFLOAD_EXTERNAL_PROJECT_UNIFIED_ROCR) + find_library(HSA_RUNTIME hsa-runtime64 + HINTS + ${CMAKE_BINARY_DIR}/../../runtimes/rocr-runtime-prefix/src/rocr-runtime-build/rocr/lib + ${CMAKE_INSTALL_PREFIX} + PATHS + /opt/rocm) + else() + find_library(HSA_RUNTIME hsa-runtime64 + HINTS + ${CMAKE_BINARY_DIR}/../../runtimes/rocr-runtime-prefix/src/rocr-runtime-build + ${CMAKE_INSTALL_PREFIX} + PATHS + ${LIBOMPTARGET_EXTERNAL_PROJECT_HSA_PATH}) + endif() +else() + # As of rocm-3.7, hsa is installed with cmake packages and kmt is found via hsa + find_package(hsa-runtime64 QUIET 1.2.0 HINTS ${CMAKE_INSTALL_PREFIX} PATHS /opt/rocm) +endif() # Create the library and add the default arguments. add_target_library(omptarget.rtl.amdgpu AMDGPU) @@ -7,14 +35,33 @@ add_target_library(omptarget.rtl.amdgpu AMDGPU) target_sources(omptarget.rtl.amdgpu PRIVATE src/rtl.cpp) target_include_directories(omptarget.rtl.amdgpu PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/utils) +if(DEFINED LIBOMPTARGET_EXTERNAL_PROJECT_HSA_PATH) + target_include_directories(omptarget.rtl.amdgpu PRIVATE + ${LIBOMPTARGET_EXTERNAL_PROJECT_HSA_PATH}/runtime/hsa-runtime/inc ) +endif() +target_include_directories(omptarget.rtl.amdgpu PRIVATE + ${CMAKE_INSTALL_PREFIX}/include) -if(hsa-runtime64_FOUND AND NOT "amdgpu" IN_LIST LIBOMPTARGET_DLOPEN_PLUGINS) +if (LLVM_LINK_LLVM_DYLIB) + set(llvm_libs LLVM) +else() + set(llvm_libs LLVMFrontendOffloading) +endif() + +option(LIBOMPTARGET_FORCE_DLOPEN_LIBHSA "Build with dlopened libhsa" OFF) +if(DEFINED HSA_RUNTIME AND NOT LIBOMPTARGET_FORCE_DLOPEN_LIBHSA) + message(STATUS "Building AMDGPU plugin linked against libhsa") + target_link_libraries(omptarget.rtl.amdgpu PRIVATE ${HSA_RUNTIME}) + get_filename_component(library_path ${HSA_RUNTIME} DIRECTORY) + target_include_directories(omptarget.rtl.amdgpu PRIVATE ${library_path}/../include) +elseif(hsa-runtime64_FOUND AND NOT LIBOMPTARGET_FORCE_DLOPEN_LIBHSA) message(STATUS "Building AMDGPU plugin linked against libhsa") - target_link_libraries(omptarget.rtl.amdgpu PRIVATE hsa-runtime64::hsa-runtime64) + target_link_libraries(omptarget.rtl.amdgpu PRIVATE hsa-runtime64::hsa-runtime64 ${llvm_libs}) else() message(STATUS "Building AMDGPU plugin for dlopened libhsa") target_include_directories(omptarget.rtl.amdgpu PRIVATE dynamic_hsa) target_sources(omptarget.rtl.amdgpu PRIVATE dynamic_hsa/hsa.cpp) + target_link_libraries(omptarget.rtl.amdgpu PRIVATE ${llvm_libs}) endif() # Configure testing for the AMDGPU plugin. We will build tests if we could a diff --git a/offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp b/offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp index bc92f4a46a5c0..b1b7037d2c654 100644 --- a/offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp +++ b/offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp @@ -75,7 +75,7 @@ DLWRAP(hsa_executable_load_agent_code_object, 5) DLWRAP_FINALIZE() #ifndef DYNAMIC_HSA_PATH -#define DYNAMIC_HSA_PATH "libhsa-runtime64.so" +#define DYNAMIC_HSA_PATH "libhsa-runtime64.so.1" #endif #ifndef TARGET_NAME diff --git a/offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h b/offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h index ad135f72fff12..f677931f93864 100644 --- a/offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h +++ b/offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h @@ -99,7 +99,9 @@ typedef enum { typedef enum { HSA_SYSTEM_INFO_VERSION_MAJOR = 0, HSA_SYSTEM_INFO_VERSION_MINOR = 1, -} hsa_system_info_t; + HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED = 0x201; +} +hsa_system_info_t; typedef enum { HSA_AGENT_FEATURE_KERNEL_DISPATCH = 1, diff --git a/offload/plugins-nextgen/amdgpu/src/rtl.cpp b/offload/plugins-nextgen/amdgpu/src/rtl.cpp index 0b03ef534d273..cb33851f7f067 100644 --- a/offload/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/offload/plugins-nextgen/amdgpu/src/rtl.cpp @@ -15,12 +15,16 @@ #include #include #include +#include #include #include #include +#include #include +#include #include #include +#include #include "ErrorReporting.h" #include "Shared/APITypes.h" @@ -31,11 +35,14 @@ #include "Utils/ELF.h" #include "GlobalHandler.h" -#include "OpenMP/OMPT/Callback.h" #include "PluginInterface.h" #include "UtilitiesRTL.h" #include "omptarget.h" +#include "print_tracing.h" + +#include "memtype.h" + #include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" @@ -75,8 +82,128 @@ #include "hsa/hsa_ext_amd.h" #endif +using namespace llvm::omp::target; +using namespace llvm::omp::xteam_red; using namespace error; +// AMDGPU-specific, so not using the common ones from the device independent +// includes. + +double setTicksToTime() { + uint64_t TicksFrequency = 1; + double TicksToTime = 1.0; + + hsa_status_t Status = + hsa_system_get_info(HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY, &TicksFrequency); + if (Status == HSA_STATUS_SUCCESS) + TicksToTime = (double)1e9 / (double)TicksFrequency; + else + DP("Error calling hsa_system_get_info for timestamp frequency\n"); + + return TicksToTime; +} + +/// HSA system clock frequency +double TicksToTime = 1.0; + +/// Compute system timestamp conversion factor, modeled after ROCclr +void setHSATicksToTimeConstant() { TicksToTime = setTicksToTime(); } + +/// Forward declare +namespace llvm { +namespace omp { +namespace target { +namespace plugin { + +struct AMDGPUSignalTy; +struct AMDGPUDeviceTy; + +/// Use to transport information to OMPT timing functions. +struct ProfilingInfoTy { + // Holds the profiler instance + GenericPluginTy *Plugin; + + // The HSA agent on which the operation is executed + hsa_agent_t Agent; + + // The signal to profile + AMDGPUSignalTy *Signal; + + // HSA system clock frequency + double TicksToTime; + + // Handle to profiler specific data + void *ProfilerSpecificData; +}; + +/// Get ProfilingInfoTy from the void * used in the action +/// functions. +static ProfilingInfoTy *getProfilingInfo(void *Data); + +/// Returns the pair of time for a kernel +static std::pair +getKernelStartAndEndTime(const ProfilingInfoTy *Args); + +/// Returns the pair of time for a data transfer +static std::pair +getCopyStartAndEndTime(const ProfilingInfoTy *Args); + +/// Obtain the timing info and call the RegionInterface callback for the +/// asynchronous trace records. +static Error timeDataTransferInNsAsync(void *Data) { + auto Args = getProfilingInfo(Data); + + auto [Start, End] = getCopyStartAndEndTime(Args); + + Args->Plugin->getProfiler()->handleDataTransfer(Start, End, + Args->ProfilerSpecificData); + + return Plugin::success(); +} + +static void * +getOrNullProfilerSpecificData(AsyncInfoWrapperTy &AsyncInfoWrapper) { + __tgt_async_info *AI = AsyncInfoWrapper; + return AI ? AI->ProfilerData : nullptr; +} + +} // namespace plugin +} // namespace target +} // namespace omp +} // namespace llvm + +/// Enable/disable async copy profiling. +void setOmptAsyncCopyProfile(bool Enable) { + hsa_status_t Status = hsa_amd_profiling_async_copy_enable(Enable); + if (Status != HSA_STATUS_SUCCESS) + DP("Error enabling async copy profiling\n"); +} + +/// Get the current HSA-based device timestamp. +uint64_t getSystemTimestampInNs() { + uint64_t TimeStamp = 0; + hsa_status_t Status = + hsa_system_get_info(HSA_SYSTEM_INFO_TIMESTAMP, &TimeStamp); + if (Status != HSA_STATUS_SUCCESS) + DP("Error calling hsa_system_get_info for timestamp\n"); + return TimeStamp * TicksToTime; +} + +/// @brief Helper to get the host time +/// @return CLOCK_REALTIME seconds as double +static double getTimeOfDay() { + double TimeVal = .0; + struct timeval tval; + int rc = gettimeofday(&tval, NULL); + if (rc) { + // XXX: Error case: What to do? + } else { + TimeVal = static_cast(tval.tv_sec) + + 1.0E-06 * static_cast(tval.tv_usec); + } + return TimeVal; +} + namespace llvm { namespace omp { namespace target { @@ -184,6 +311,7 @@ static Error asyncMemCopy(bool UseMultipleSdmaEngines, void *Dst, // dispatch to the same SDMA engine. This may result in sub-optimal // performance. However, I think the possibility to be fairly low. int LocalSdmaEngine = SdmaEngine.load(std::memory_order_acquire); + DP("Running Async Copy on SDMA Engine: %i\n", LocalSdmaEngine); // This call is only avail in ROCm >= 5.7 hsa_status_t S = hsa_amd_memory_async_copy_on_engine( Dst, DstAgent, Src, SrcAgent, Size, NumDepSignals, DepSignals, @@ -220,6 +348,7 @@ static Error getTargetTripleAndFeatures(hsa_agent_t Agent, }); return Err; } + } // namespace hsa_utils /// Utility class representing generic resource references to AMDGPU resources. @@ -354,6 +483,13 @@ struct AMDGPUMemoryPoolTy { return Plugin::check(Status, "error in hsa_amd_agents_allow_access: %s"); } + Error zeroInitializeMemory(void *Ptr, size_t Size) { + uint64_t Rounded = sizeof(uint32_t) * ((Size + 3) / sizeof(uint32_t)); + hsa_status_t Status = + hsa_amd_memory_fill(Ptr, 0, Rounded / sizeof(uint32_t)); + return Plugin::check(Status, "Error in hsa_amd_memory_fill: %s"); + } + /// Get attribute from the memory pool. template Error getAttr(hsa_amd_memory_pool_info_t Kind, Ty &Value) const { @@ -396,11 +532,22 @@ struct AMDGPUMemoryManagerTy : public DeviceAllocatorTy { /// Create an empty memory manager. AMDGPUMemoryManagerTy(AMDGPUPluginTy &Plugin) - : Plugin(Plugin), MemoryPool(nullptr), MemoryManager(nullptr) {} + : Plugin(Plugin), MemoryPool(nullptr), MemoryManager(nullptr), + OMPX_AMDMemoryMgrThreshold("OMPX_AMD_MEMORY_MANAGER_THRESHOLD_EXP_2", + 30) {} /// Initialize the memory manager from a memory pool. Error init(AMDGPUMemoryPoolTy &MemoryPool) { - const uint32_t Threshold = 1 << 30; + // Sanity check to ensure user input will not overflow the variable. + if (OMPX_AMDMemoryMgrThreshold > sizeof(size_t) * CHAR_BIT - 1) { + // if user input is too large, trim it down to the upper limit of size_t. + OMPX_AMDMemoryMgrThreshold = sizeof(size_t) * CHAR_BIT - 1; + DP("User input for AMDGPUMemoryManager threshhold is too larget and was " + "trimmed to: %u\n", + OMPX_AMDMemoryMgrThreshold.get()); + } + const size_t Threshold = 1UL << OMPX_AMDMemoryMgrThreshold; + DP("AMDGPUMemoryManager threshhold was set to: %zu B\n", Threshold); this->MemoryManager = new MemoryManagerTy(*this, Threshold); this->MemoryPool = &MemoryPool; return Plugin::success(); @@ -463,6 +610,12 @@ struct AMDGPUMemoryManagerTy : public DeviceAllocatorTy { /// Reference to the actual memory manager. MemoryManagerTy *MemoryManager; + + /// Set the threshold for the size of the allocated memory + /// that will be handled by AMDGPUMemoryMangerTy. The input + /// value should be the exponent in the expression (2^n). + /// e.g input 10 => 2 ^ 10 = 1KB + UInt32Envar OMPX_AMDMemoryMgrThreshold; }; /// Class implementing the AMDGPU device images' properties. @@ -502,9 +655,15 @@ struct AMDGPUDeviceImageTy : public DeviceImageTy { return It->second; } + /// Does device image contain Symbol + bool hasDeviceSymbol(GenericDeviceTy &Device, StringRef SymbolName) const; + private: /// The executable loaded on the agent. hsa_executable_t Executable; +#if SANITIZER_AMDGPU + hsa_code_object_reader_t CodeObjectReader; +#endif StringMap KernelInfoMap; uint16_t ELFABIVersion; }; @@ -513,7 +672,15 @@ struct AMDGPUDeviceImageTy : public DeviceImageTy { /// generic kernel class. struct AMDGPUKernelTy : public GenericKernelTy { /// Create an AMDGPU kernel with a name and an execution mode. - AMDGPUKernelTy(const char *Name) : GenericKernelTy(Name) {} + AMDGPUKernelTy(const char *Name, GenericGlobalHandlerTy &Handler) + : GenericKernelTy(Name), + OMPX_SPMDOccupancyBasedOpt("OMPX_SPMD_OCCUPANCY_BASED_OPT", false), + OMPX_GenericSPMDOccupancyBasedOpt( + "OMPX_GENERIC_SPMD_OCCUPANCY_BASED_OPT", false), + OMPX_BigJumpLoopOccupancyBasedOpt( + "OMPX_BIGJUMPLOOP_OCCUPANCY_BASED_OPT", false), + OMPX_XTeamReductionOccupancyBasedOpt( + "OMPX_XTEAMREDUCTION_OCCUPANCY_BASED_OPT", false) {} /// Initialize the AMDGPU kernel. Error initImpl(GenericDeviceTy &Device, DeviceImageTy &Image) override { @@ -556,8 +723,37 @@ struct AMDGPUKernelTy : public GenericKernelTy { // TODO: Read the kernel descriptor for the max threads per block. May be // read from the image. + // Get ConstWGSize for kernel from image + ConstWGSize = Device.getDefaultNumThreads(); + std::string WGSizeName(getName()); + WGSizeName += "_wg_size"; + GlobalTy HostConstWGSize(WGSizeName, sizeof(decltype(ConstWGSize)), + &ConstWGSize); + GenericGlobalHandlerTy &GHandler = Device.Plugin.getGlobalHandler(); + if (auto Err = + GHandler.readGlobalFromImage(Device, AMDImage, HostConstWGSize)) { + // In case it is not found, we simply stick with the defaults. + // So we consume the error and print a debug message. + DP("Could not load %s global from kernel image. Run with %u %u\n", + WGSizeName.c_str(), PreferredNumThreads, MaxNumThreads); + consumeError(std::move(Err)); + assert(PreferredNumThreads > 0 && "Prefer more than 0 threads"); + assert(MaxNumThreads > 0 && "MaxNumThreads more than 0 threads"); + } else { + // Set the number of preferred and max threads to the ConstWGSize to get + // the exact value for kernel launch. Exception: In generic-spmd mode, we + // set it to the default blocksize since ConstWGSize may include the + // master thread which is not required. + PreferredNumThreads = + getExecutionModeFlags() == OMP_TGT_EXEC_MODE_GENERIC_SPMD + ? Device.getDefaultNumThreads() + : ConstWGSize; + MaxNumThreads = ConstWGSize; + } + ImplicitArgsSize = - hsa_utils::getImplicitArgsSize(AMDImage.getELFABIVersion()); + hsa_utils::getImplicitArgsSize(AMDImage.getELFABIVersion()); // COV 5 patch + DP("ELFABIVersion: %d\n", AMDImage.getELFABIVersion()); // Get additional kernel info read from image @@ -566,6 +762,8 @@ struct AMDGPUKernelTy : public GenericKernelTy { INFO(OMP_INFOTYPE_PLUGIN_KERNEL, Device.getDeviceId(), "Could not read extra information for kernel %s.", getName()); + HasRPC = AMDImage.hasDeviceSymbol(Device, "__llvm_rpc_client"); + return Plugin::success(); } @@ -588,11 +786,19 @@ struct AMDGPUKernelTy : public GenericKernelTy { /// Print more elaborate kernel launch info for AMDGPU Error printLaunchInfoDetails(GenericDeviceTy &GenericDevice, KernelArgsTy &KernelArgs, uint32_t NumThreads[3], - uint32_t NumBlocks[3]) const override; + uint32_t NumBlocks[3], int64_t MultiDeviceLB, + int64_t MultiDeviceUB) const override; + /// Print the "old" AMD KernelTrace single-line format + void printAMDOneLineKernelTrace(GenericDeviceTy &GenericDevice, + KernelArgsTy &KernelArgs, + uint32_t NumThreads[3], uint32_t NumBlocks[3], + int64_t MultiDeviceLB, + int64_t MultiDeviceUB) const; /// Get group and private segment kernel size. uint32_t getGroupSize() const { return GroupSize; } uint32_t getPrivateSize() const { return PrivateSize; } + uint16_t getConstWGSize() const { return ConstWGSize; } /// Get the HSA kernel object representing the kernel function. uint64_t getKernelObject() const { return KernelObject; } @@ -603,6 +809,26 @@ struct AMDGPUKernelTy : public GenericKernelTy { /// Indicates whether or not we need to set up our own private segment size. bool usesDynamicStack() const { return DynamicStack; } + bool isValidBlockSize(uint32_t BlockSize) const override { + return BlockSize <= ConstWGSize; + } + + uint32_t getKernelLaunchId() const { return KernelLaunchId; } + + void setKernelLaunchId(uint32_t Id) const { KernelLaunchId = Id; } + + /// Envar to enable occupancy-based optimization for SPMD kernel. + BoolEnvar OMPX_SPMDOccupancyBasedOpt; + + /// Envar to enable occupancy-based optimization for generic SPMD kernel. + BoolEnvar OMPX_GenericSPMDOccupancyBasedOpt; + + /// Envar to enable occupancy-based optimization for big jump loop. + BoolEnvar OMPX_BigJumpLoopOccupancyBasedOpt; + + /// Envar to enable occupancy-based optimization for cross team reduction. + BoolEnvar OMPX_XTeamReductionOccupancyBasedOpt; + private: /// The kernel object to execute. uint64_t KernelObject; @@ -613,13 +839,494 @@ struct AMDGPUKernelTy : public GenericKernelTy { uint32_t PrivateSize; bool DynamicStack; + /// Device init sets this to true if image has symbol indicating that RPC + /// service threads are used in this image. Only used for trace display. + bool HasRPC; + /// The size of implicit kernel arguments. uint32_t ImplicitArgsSize; /// Additional Info for the AMD GPU Kernel std::optional KernelInfo; + /// CodeGen generate WGSize + uint16_t ConstWGSize; + + static thread_local uint32_t KernelLaunchId; + + /// Lower number of threads if tripcount is low. This should produce + /// a larger number of teams if allowed by other constraints. + std::pair adjustNumThreadsForLowTripCount( + GenericDeviceTy &GenericDevice, uint32_t BlockSize, + uint64_t LoopTripCount, uint32_t ThreadLimitClause[3]) const override { + uint32_t NumThreads = BlockSize; + + // If there is an override already, do nothing. Note the different + // default for Xteam Reductions. + if (!isXTeamReductionsMode() && + NumThreads != GenericDevice.getDefaultNumThreads() && + NumThreads != ConstWGSize) + return std::make_pair(false, NumThreads); + + if (isXTeamReductionsMode() && + NumThreads != llvm::omp::xteam_red::DefaultBlockSize && + NumThreads != ConstWGSize) + return std::make_pair(false, NumThreads); + + // If tripcount not set or not low, do nothing. + if ((LoopTripCount == 0) || + (LoopTripCount > GenericDevice.getOMPXLowTripCount())) + return std::make_pair(false, NumThreads); + + // Environment variable present, do nothing. + if (GenericDevice.getOMPTeamsThreadLimit() > 0) + return std::make_pair(false, NumThreads); + + // num_threads clause present, do nothing. + if ((ThreadLimitClause[0] > 0) && (ThreadLimitClause[0] != (uint32_t)-1)) + return std::make_pair(false, NumThreads); + + // If generic or generic-SPMD kernel, do nothing. + if (isGenericMode() || isGenericSPMDMode()) + return std::make_pair(false, NumThreads); + + // Reduce the blocksize as long as it is above the tunable limit. + while (NumThreads > GenericDevice.getOMPXSmallBlockSize()) + NumThreads >>= 1; + + if (NumThreads == 0) + return std::make_pair(false, BlockSize); + + if (isXTeamReductionsMode()) + return std::make_pair(true, + llvm::omp::getBlockSizeAsPowerOfTwo(NumThreads)); + + return std::make_pair(true, NumThreads); + } + + /// Optimize the number of teams based on the max occupancy value. + uint64_t OptimizeNumTeamsBaseOccupancy(GenericDeviceTy &GenericDevice, + uint32_t NumThreads) const { + unsigned NumWavesPerTeam = + divideCeil(NumThreads, GenericDevice.getWarpSize()); + unsigned TotalWavesPerCU = MaxOccupancy * llvm::omp::amdgpu_arch::SIMDPerCU; + // Per device + unsigned TotalWavesPerDevice = + TotalWavesPerCU * GenericDevice.getNumComputeUnits(); + unsigned NumTeams = divideCeil(TotalWavesPerDevice, NumWavesPerTeam); + + return static_cast(NumTeams); + } + + /// Get the number of threads and blocks for the kernel based on the + /// user-defined threads and block clauses. + uint32_t getNumThreads(GenericDeviceTy &GenericDevice, + uint32_t ThreadLimitClause[3]) const override { + assert(!isBareMode() && "bare kernel should not call this function"); + + assert(ThreadLimitClause[1] == 1 && ThreadLimitClause[2] == 1 && + "Multi dimensional launch not supported yet."); + + // Honor OMP_TEAMS_THREAD_LIMIT environment variable and + // num_threads/thread_limit clause for BigJumpLoop and NoLoop kernel types. + int32_t TeamsThreadLimitEnvVar = GenericDevice.getOMPTeamsThreadLimit(); + if (isBigJumpLoopMode() || isNoLoopMode()) { + if (TeamsThreadLimitEnvVar > 0) + return std::min(static_cast(ConstWGSize), + TeamsThreadLimitEnvVar); + if ((ThreadLimitClause[0] > 0) && (ThreadLimitClause[0] != (uint32_t)-1)) + return std::min(static_cast(ConstWGSize), + ThreadLimitClause[0]); + return ConstWGSize; + } + + if (isXTeamReductionsMode()) { + if (TeamsThreadLimitEnvVar > 0 && + TeamsThreadLimitEnvVar <= static_cast(ConstWGSize)) + return llvm::omp::getBlockSizeAsPowerOfTwo(TeamsThreadLimitEnvVar); + if (ThreadLimitClause[0] > 0 && ThreadLimitClause[0] != (uint32_t)-1 && + ThreadLimitClause[0] <= static_cast(ConstWGSize)) + return llvm::omp::getBlockSizeAsPowerOfTwo(ThreadLimitClause[0]); + assert(((ConstWGSize & (ConstWGSize - 1)) == 0) && + "XTeam Reduction blocksize must be a power of two"); + return ConstWGSize; + } + + if (ThreadLimitClause[0] > 0 && isGenericMode()) { + if (ThreadLimitClause[0] == (uint32_t)-1) + ThreadLimitClause[0] = PreferredNumThreads; + else + ThreadLimitClause[0] += GenericDevice.getWarpSize(); + } + + // Limit number of threads taking into consideration the user + // environment variable OMP_TEAMS_THREAD_LIMIT if provided. + uint32_t CurrentMaxNumThreads = MaxNumThreads; + if (TeamsThreadLimitEnvVar > 0) + CurrentMaxNumThreads = std::min( + static_cast(TeamsThreadLimitEnvVar), CurrentMaxNumThreads); + + return std::min(CurrentMaxNumThreads, (ThreadLimitClause[0] > 0) + ? ThreadLimitClause[0] + : PreferredNumThreads); + } + uint32_t getNumBlocks(GenericDeviceTy &GenericDevice, + uint32_t NumTeamsClause[3], uint64_t LoopTripCount, + uint32_t &NumThreads, + bool IsNumThreadsFromUser) const override { + assert(!isBareMode() && "bare kernel should not call this function"); + + assert(NumTeamsClause[1] == 1 && NumTeamsClause[2] == 1 && + "Multi dimensional launch not supported yet."); + + const auto getNumGroupsFromThreadsAndTripCount = + [](const uint64_t TripCount, const uint32_t NumThreads) { + return ((TripCount - 1) / NumThreads) + 1; + }; + uint64_t DeviceNumCUs = GenericDevice.getNumComputeUnits(); // FIXME + + if (isNoLoopMode()) { + return LoopTripCount > 0 ? getNumGroupsFromThreadsAndTripCount( + LoopTripCount, NumThreads) + : 1; + } + + uint64_t NumWavesInGroup = + (NumThreads - 1) / GenericDevice.getWarpSize() + 1; + + if (isBigJumpLoopMode()) { + int32_t NumTeamsEnvVar = GenericDevice.getOMPNumTeams(); + uint64_t NumGroups = 1; + // Cannot assert a non-zero tripcount. Instead, launch with 1 team if the + // tripcount is indeed zero. + if (LoopTripCount > 0) + NumGroups = + getNumGroupsFromThreadsAndTripCount(LoopTripCount, NumThreads); + + // Honor OMP_NUM_TEAMS environment variable for BigJumpLoop kernel type. + if (NumTeamsEnvVar > 0 && static_cast(NumTeamsEnvVar) <= + GenericDevice.getBlockLimit()) + NumGroups = std::min(static_cast(NumTeamsEnvVar), NumGroups); + // Honor num_teams clause but lower it if tripcount dictates. + else if (NumTeamsClause[0] > 0 && + NumTeamsClause[0] <= GenericDevice.getBlockLimit()) { + NumGroups = + std::min(static_cast(NumTeamsClause[0]), NumGroups); + } else { + // num_teams clause is not specified. Choose lower of tripcount-based + // NumGroups and a value determined as follows: + // - If the number of teams per CU is specified by the user with the + // envar LIBOMPTARGET_AMDGPU_BIG_JUMP_LOOP_TEAMS_PER_CU, compute + // NumGroups from that specified value. This envar is OFF by default. + // - Otherwise, use the max total teams specified with the envar + /// LIBOMPTARGET_AMDGPU_BIG_JUMP_LOOP_MAX_TOTAL_TEAMS. + // This envar is used by default with 1M as the default value. + if (GenericDevice.getOMPXBigJumpLoopTeamsPerCU() > 0) { + NumGroups = + std::min(NumGroups, GenericDevice.getOMPXBigJumpLoopTeamsPerCU() * + DeviceNumCUs); + } else { + NumGroups = std::min( + NumGroups, static_cast( + GenericDevice.getOMPXBigJumpLoopMaxTotalTeams())); + } + + // If the user specifies a number of teams for low trip count loops, + // honor it. + uint64_t LowTripCountBlocks = + GenericDevice.getOMPXNumBlocksForLowTripcount(LoopTripCount); + if (LowTripCountBlocks) { + NumGroups = LowTripCountBlocks; + } + } + // If envar OMPX_BIGJUMPLOOP_OCCUPANCY_BASED_OPT is set and no num_teams + // clause or OMP_NUM_TEAMS is specified, optimize the number of teams + // based on occupancy value. + if (OMPX_BigJumpLoopOccupancyBasedOpt && NumTeamsEnvVar == 0 && + NumTeamsClause[0] == 0) { + return std::min(NumGroups, OptimizeNumTeamsBaseOccupancy(GenericDevice, + NumThreads)); + } + return std::min(NumGroups, + static_cast(GenericDevice.getBlockLimit())); + } + + if (isXTeamReductionsMode()) { + // Here's the default number of teams. + uint64_t NumGroups = DeviceNumCUs; + // The number of teams must not exceed this upper limit. + uint64_t MaxNumGroups = NumGroups; + // Honor OMP_NUM_TEAMS environment variable for XteamReduction kernel + // type, if possible. + int32_t NumTeamsEnvVar = GenericDevice.getOMPNumTeams(); + // CU mulitiplier from envar. + uint32_t EnvarCUMultiplier = GenericDevice.getXTeamRedTeamsPerCU(); + + if (GenericDevice.isFastReductionEnabled()) { + // When fast reduction is enabled, the number of teams is capped by + // the MaxCUMultiplier constant. + MaxNumGroups = DeviceNumCUs * llvm::omp::xteam_red::MaxCUMultiplier; + } else { + // When fast reduction is not enabled, the number of teams is capped + // by the metadata that clang CodeGen created. The number of teams + // used here must not exceed the upper limit determined during + // CodeGen. This upper limit is not currently communicated from + // CodeGen to the plugin. So it is re-computed here. + + // ConstWGSize is the block size that CodeGen used. + uint32_t CUMultiplier = + llvm::omp::xteam_red::getXteamRedCUMultiplier(ConstWGSize); + MaxNumGroups = DeviceNumCUs * CUMultiplier; + } + + // If envar OMPX_XTEAMREDUCTION_OCCUPANCY_BASED_OPT is set and no + // OMP_NUM_TEAMS or num_teams clause is specified, optimize the num of + // teams based on occupancy value. + if (OMPX_XTeamReductionOccupancyBasedOpt && NumTeamsEnvVar == 0 && + NumTeamsClause[0] == 0) { + uint64_t newNumTeams = + OptimizeNumTeamsBaseOccupancy(GenericDevice, NumThreads); + return std::min(newNumTeams, MaxNumGroups); + } + + // Prefer num_teams clause over environment variable. There is a corner + // case where inspite of the presence of a num_teams clause, CodeGen + // may fail to extract it, instead using the alternative computation of + // the number of teams. But the runtime here will still see the value + // of the clause, so we need to check against the upper limit. + if (NumTeamsClause[0] > 0 && + NumTeamsClause[0] <= GenericDevice.getBlockLimit()) { + NumGroups = + std::min(static_cast(NumTeamsClause[0]), MaxNumGroups); + } else if (NumTeamsEnvVar > 0 && static_cast(NumTeamsEnvVar) <= + GenericDevice.getBlockLimit()) { + NumGroups = + std::min(static_cast(NumTeamsEnvVar), MaxNumGroups); + } else { + // Ensure we don't have a large number of teams running if the tripcount + // is low + uint64_t NumGroupsFromTripCount = 1; + if (LoopTripCount > 0) + NumGroupsFromTripCount = + getNumGroupsFromThreadsAndTripCount(LoopTripCount, NumThreads); + + // Compute desired number of groups in the absence of user input + // based on a factor controlled by an integer env-var. + // Note that the upper bound is MaxNumGroups. + uint32_t AdjustFactor = + GenericDevice.getOMPXAdjustNumTeamsForXteamRedSmallBlockSize(); + if (NumThreads > 0 && AdjustFactor > 0) { + uint64_t DesiredNumGroups = NumGroups; + if (AdjustFactor == 1) { + DesiredNumGroups = + DeviceNumCUs * + (llvm::omp::xteam_red::DesiredWavesPerCU / NumWavesInGroup); + } else { + DesiredNumGroups = DeviceNumCUs * AdjustFactor; + } + NumGroups = DesiredNumGroups; + } + + // Prefer OMPX_AdjustNumTeamsForXteamRedSmallBlockSize over + // OMPX_XTeamRedTeamsPerCU. + if (AdjustFactor == 0 && EnvarCUMultiplier > 0) + NumGroups = DeviceNumCUs * EnvarCUMultiplier; + + NumGroups = std::min(NumGroups, MaxNumGroups); + NumGroups = std::min(NumGroups, NumGroupsFromTripCount); + + // If the user specifies a number of teams for low trip count loops, + // and no num_teams clause was used, honor it. + uint64_t LowTripCountBlocks = + GenericDevice.getOMPXNumBlocksForLowTripcount(LoopTripCount); + if (LowTripCountBlocks) { + NumGroups = std::min(MaxNumGroups, LowTripCountBlocks); + } + } + DP("xteam-red:NumCUs=%lu xteam-red:NumGroups=%lu\n", DeviceNumCUs, + NumGroups); + return NumGroups; + } + + if (NumTeamsClause[0] > 0) { + // TODO: We need to honor any value and consequently allow more than the + // block limit. For this we might need to start multiple kernels or let + // the blocks start again until the requested number has been started. + return std::min(NumTeamsClause[0], GenericDevice.getBlockLimit()); + } + + // If envar OMPX_SPMD_OCCUPANCY_BASED_OPT is set and no OMP_NUM_TEAMS is + // specified, optimize the num of teams based on occupancy value. + int32_t NumTeamsEnvVar = GenericDevice.getOMPNumTeams(); + uint64_t TripCountNumBlocks = std::numeric_limits::max(); + if (LoopTripCount > 0) { + if (isSPMDMode()) { + // We have a combined construct, i.e. `target teams distribute + // parallel for [simd]`. We launch so many teams so that each thread + // will execute one iteration of the loop. round up to the nearest + // integer + TripCountNumBlocks = ((LoopTripCount - 1) / NumThreads) + 1; + } else { + assert((isGenericMode() || isGenericSPMDMode()) && + "Unexpected execution mode!"); + // If we reach this point, then we have a non-combined construct, i.e. + // `teams distribute` with a nested `parallel for` and each team is + // assigned one iteration of the `distribute` loop. E.g.: + // + // #pragma omp target teams distribute + // for(...loop_tripcount...) { + // #pragma omp parallel for + // for(...) {} + // } + // + // Threads within a team will execute the iterations of the `parallel` + // loop. + TripCountNumBlocks = LoopTripCount; + } + } + + if (isSPMDMode() && OMPX_SPMDOccupancyBasedOpt && NumTeamsEnvVar == 0 && + NumTeamsClause[0] == 0) { + return std::min(TripCountNumBlocks, + OptimizeNumTeamsBaseOccupancy(GenericDevice, NumThreads)); + } + + auto getAdjustedDefaultNumBlocks = + [this](GenericDeviceTy &GenericDevice, + uint64_t DeviceNumCUs) -> uint64_t { + if (!isGenericSPMDMode() || + GenericDevice.getOMPXGenericSpmdTeamsPerCU() == 0) + return static_cast(GenericDevice.getDefaultNumBlocks()); + return DeviceNumCUs * static_cast( + GenericDevice.getOMPXGenericSpmdTeamsPerCU()); + }; + + // If the loops are long running we rather reuse blocks than spawn too many. + // Additionally, under an env-var, adjust the number of teams based on the + // number of wave-slots in a CU that we aim to occupy. + uint64_t AdjustedNumBlocks = + getAdjustedDefaultNumBlocks(GenericDevice, DeviceNumCUs); + if (GenericDevice.getOMPXAdjustNumTeamsForSmallBlockSize()) { + uint64_t DefaultNumWavesInGroup = + (GenericDevice.getDefaultNumThreads() - 1) / + GenericDevice.getWarpSize() + + 1; + AdjustedNumBlocks = + (AdjustedNumBlocks * DefaultNumWavesInGroup) / NumWavesInGroup; + } + + // If the user specifies a number of teams for low trip count loops, honor + // it. + uint64_t LowTripCountBlocks = + GenericDevice.getOMPXNumBlocksForLowTripcount(LoopTripCount); + if (LowTripCountBlocks) { + return LowTripCountBlocks; + } + + uint64_t PreferredNumBlocks = TripCountNumBlocks; + // Occupancy-based setting overrides block reuse. + if (OMPX_GenericSPMDOccupancyBasedOpt && NumTeamsEnvVar == 0 && NumTeamsClause[0] == 0) { + PreferredNumBlocks = + std::min(PreferredNumBlocks, + OptimizeNumTeamsBaseOccupancy(GenericDevice, NumThreads)); + } else if (GenericDevice.getReuseBlocksForHighTripCount()) { + // If the loops are long running we rather reuse blocks than spawn too + // many. + PreferredNumBlocks = std::min(TripCountNumBlocks, AdjustedNumBlocks); + } + + // For most generic-SPMD kernels, the tripcount of the outer distribute-loop + // determines the number of teams launched. The tripcounts of the inner + // parallel loops should determine the number of threads launched. However, + // the inner loop tripcounts are unknown, so the runtime just launches 256 + // threads by default. But if the inner loop tripcount is lower than 256, + // many of the threads in every workgroup are idle and just waste resources. + // In order to reduce this wastage, we reduce the blocksize upto the + // wavefront size if the tripcount is large enough to proportionally + // increase the number of teams. The increase in the number of teams is + // required to preserve the occupancy in case the inner loop tripcounts are + // larger than the blocksize. This change is done only when the user has not + // specified the number of teams or threads. + if (isGenericSPMDMode() && !IsNumThreadsFromUser && + NumTeamsClause[0] == 0 && NumTeamsEnvVar == 0 && + GenericDevice.getOMPXGenericSpmdUseSmallBlockSize()) { + uint64_t TmpPreferredNumBlocks = PreferredNumBlocks << 1; + while (TmpPreferredNumBlocks <= LoopTripCount && + NumThreads > GenericDevice.getWarpSize()) { + NumThreads >>= 1; + PreferredNumBlocks = TmpPreferredNumBlocks; + TmpPreferredNumBlocks <<= 1; + } + } + return std::min(PreferredNumBlocks, + (uint64_t)GenericDevice.getBlockLimit()); + } + + /// Compute the occupancy with the constraint on the number of SGPRs + /// Follow the logic on the backend + /// Ref: + /// llvm-project/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp:getOccupancyWithNumSGPRs + unsigned getOccupancyWithNumSGPRs(unsigned SGPRCount) const { + + if (SGPRCount <= llvm::omp::amdgpu_arch::SGPRCountOccupancy10) { + return 10; + } else if (SGPRCount <= llvm::omp::amdgpu_arch::SGPRCountOccupancy9) { + return 9; + } else if (SGPRCount <= llvm::omp::amdgpu_arch::SGPRCountOccupancy8) { + return 8; + } + return 7; + } + + /// Compute the occupancy with the constraint on LDS + /// Follow the logic on the backend + /// Ref: + /// llvm-project/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp:getOccupancyWithLocalMemSize + unsigned getOccupancyWithLDS(GenericDeviceTy &GenericDevice, + uint32_t GroupSegmentSize, + unsigned MaxWavesPerEU, + uint32_t MaxFlatWorkgroupSize) const { + + unsigned MaxWorkgroupNum = + llvm::omp::amdgpu_arch::LocalMemorySize / GroupSegmentSize; + + // workgroup size + unsigned ThreadsPerWorkgroup = MaxFlatWorkgroupSize; + unsigned WavesPerWorkgroup = + divideCeil(ThreadsPerWorkgroup, GenericDevice.getWarpSize()); + + unsigned MaxWavesPerCU = MaxWavesPerEU * llvm::omp::amdgpu_arch::SIMDPerCU; + + // if a workgroup has just one wavefront, the max # of workgroup per CU is + // 40 if a workgroup has more than one wavefront, the max # of workgroup per + // CU is 16 https://github.com/ROCm/ROCm/issues/746#issuecomment-474656922 + if (WavesPerWorkgroup <= 1) { + MaxWorkgroupNum = std::min(MaxWorkgroupNum, MaxWavesPerCU); + } else { + MaxWorkgroupNum = + std::min(MaxWorkgroupNum, MaxWavesPerCU / WavesPerWorkgroup); + MaxWorkgroupNum = std::min(MaxWorkgroupNum, + llvm::omp::amdgpu_arch::MaxWorkgroupNumPerCU); + } + + // per SIMD + unsigned WaveNumByLDS = divideCeil(WavesPerWorkgroup * MaxWorkgroupNum, + llvm::omp::amdgpu_arch::SIMDPerCU); + WaveNumByLDS = std::min(WaveNumByLDS, MaxWavesPerEU); + + return WaveNumByLDS; + } + + /// Compute the max kernel occupancy for AMD GPU + unsigned computeMaxOccupancy(GenericDeviceTy &Device) const override; + + /// Compute the achieved kernel occupancy for AMD GPU. + unsigned computeAchievedOccupancy(GenericDeviceTy &Device, + uint32_t numThreads, + uint64_t numTeams) const override; }; +thread_local uint32_t AMDGPUKernelTy::KernelLaunchId = 0; + /// Class representing an HSA signal. Signals are used to define dependencies /// between asynchronous operations: kernel launches and memory transfers. struct AMDGPUSignalTy { @@ -703,18 +1410,24 @@ struct AMDGPUQueueTy { AMDGPUQueueTy() : Queue(nullptr), Mutex(), NumUsers(0) {} /// Lazily initialize a new queue belonging to a specific agent. - Error init(GenericDeviceTy &Device, hsa_agent_t Agent, int32_t QueueSize) { + Error init(GenericDeviceTy &Device, hsa_agent_t Agent, int32_t QueueSize, + int OMPX_EnableQueueProfiling) { if (Queue) return Plugin::success(); hsa_status_t Status = hsa_queue_create(Agent, QueueSize, HSA_QUEUE_TYPE_MULTI, callbackError, &Device, UINT32_MAX, UINT32_MAX, &Queue); - return Plugin::check(Status, "error in hsa_queue_create: %s"); + if (Device.Plugin.getProfiler()->isProfilingEnabled() || + OMPX_EnableQueueProfiling) + hsa_amd_profiling_set_profiler_enabled(Queue, /*Enable=*/1); + + return Plugin::check(Status, "Error in hsa_queue_create: %s"); } /// Deinitialize the queue and destroy its resources. Error deinit() { std::lock_guard Lock(Mutex); + // Don't bother turning OFF profiling, the queue is going away anyways. if (!Queue) return Plugin::success(); hsa_status_t Status = hsa_queue_destroy(Queue); @@ -776,7 +1489,10 @@ struct AMDGPUQueueTy { Packet->grid_size_y = NumBlocks[1] * NumThreads[1]; Packet->grid_size_z = NumBlocks[2] * NumThreads[2]; Packet->private_segment_size = - Kernel.usesDynamicStack() ? StackSize : Kernel.getPrivateSize(); + Kernel.usesDynamicStack() + ? std::max(static_cast(Kernel.getPrivateSize()), + StackSize) + : Kernel.getPrivateSize(); Packet->group_segment_size = GroupSize; Packet->kernel_object = Kernel.getKernelObject(); Packet->kernarg_address = KernelArgs; @@ -802,6 +1518,12 @@ struct AMDGPUQueueTy { return pushBarrierImpl(OutputSignal, InputSignal1, InputSignal2); } + /// Return the pointer to the underlying HSA queue + hsa_queue_t *getHsaQueue() { + assert(Queue && "HSA Queue initialized"); + return Queue; + } + private: /// Push a barrier packet that will wait up to two input signals. Assumes the /// the queue lock is acquired. @@ -948,6 +1670,42 @@ struct AMDGPUStreamTy { AMDGPUSignalManagerTy *SignalManager; }; + /// Utility struct holding arguments for OMPT-based kernel timing. + struct OmptKernelTimingArgsTy { + hsa_agent_t Agent; + AMDGPUSignalTy *Signal; + double TicksToTime; + }; + + /// Utility struct holding arguments for post kernel run processing. + struct PostKernelRunProcessingArgsTy { + hsa_agent_t Agent; + AMDGPUSignalTy *Signal; + double TicksToTime; + std::string KernelName; + uint32_t NumTeams; + uint32_t NumThreads; + KernelRunRecordTy *KernelRunRecords; + + PostKernelRunProcessingArgsTy() + : Agent{0}, Signal(nullptr), TicksToTime(setTicksToTime()), NumTeams(0), + NumThreads(0), KernelRunRecords(nullptr) {} + }; + + struct KernelDurationTracingArgsTy { + hsa_agent_t Agent; + AMDGPUSignalTy *Signal; + double TicksToTime; + int32_t DeviceId; + uint32_t LaunchId; + uint32_t NumTeams; + uint32_t NumThreads; + + KernelDurationTracingArgsTy() + : Agent{0}, Signal(nullptr), TicksToTime(setTicksToTime()), DeviceId(0), + LaunchId(0), NumTeams(0), NumThreads(0) {} + }; + using AMDGPUStreamCallbackTy = Error(void *Data); /// The stream is composed of N stream's slots. The struct below represents @@ -976,6 +1734,7 @@ struct AMDGPUStreamTy { ReleaseBufferArgsTy ReleaseBufferArgs; ReleaseSignalArgsTy ReleaseSignalArgs; void *CallbackArgs; + ProfilingInfoTy ProfilerArgs; }; llvm::SmallVector ActionArgs; @@ -1020,11 +1779,37 @@ struct AMDGPUStreamTy { return Plugin::success(); } + /// Schedule kernel timing measurement on the slot + Error schedProfilerKernelTiming(GenericDeviceTy *Device, hsa_agent_t Agent, + AMDGPUSignalTy *OutputSignal, + double TicksToTime, + void *ProfilerSpecificData) { + Callbacks.emplace_back(timeKernelInNsAsync); + ActionArgs.emplace_back().ProfilerArgs = + ProfilingInfoTy{&(Device->Plugin), Agent, OutputSignal, TicksToTime, + ProfilerSpecificData}; + return Plugin::success(); + } + + /// Schedule data transfer timing on the slot + Error schedProfilerDataTransferTiming(GenericDeviceTy *Device, + hsa_agent_t Agent, + AMDGPUSignalTy *OutputSignal, + double TicksToTime, + void *ProfilerSpecificData) { + Callbacks.emplace_back(timeDataTransferInNsAsync); + ActionArgs.emplace_back().ProfilerArgs = + ProfilingInfoTy{&(Device->Plugin), Agent, OutputSignal, TicksToTime, + ProfilerSpecificData}; + return Plugin::success(); + } + // Perform the action if needed. Error performAction() { if (Callbacks.empty()) return Plugin::success(); + // Perform the action. assert(Callbacks.size() == ActionArgs.size() && "Size mismatch"); for (auto [Callback, ActionArg] : llvm::zip(Callbacks, ActionArgs)) { // Perform the action. @@ -1037,6 +1822,12 @@ struct AMDGPUStreamTy { } else if (Callback == releaseSignalAction) { if (auto Err = releaseSignalAction(&ActionArg)) return Err; + } else if (Callback == timeKernelInNsAsync) { + if (auto Err = timeKernelInNsAsync(&ActionArg)) + return Err; + } else if (Callback == timeDataTransferInNsAsync) { + if (auto Err = timeDataTransferInNsAsync(&ActionArg)) + return Err; } else if (Callback) { if (auto Err = Callback(ActionArg.CallbackArgs)) return Err; @@ -1088,6 +1879,19 @@ struct AMDGPUStreamTy { /// Indicate to spread data transfers across all available SDMAs bool UseMultipleSdmaEngines; + /// Use synchronous copy back. + bool UseSyncCopyBack; + + /// When copying data from one host buffer to another, only do it + /// asynchronously if `MinHostToHostAsyncCopySize <= size`. + UInt32Envar OMPX_MinHostToHostAsyncCopySize; + + /// Arguments for the callback function. + PostKernelRunProcessingArgsTy PostKernelRunProcessingArgs; + + /// Arguments for callback function to collect kernel duration. + KernelDurationTracingArgsTy KernelDurationTracingArgs; + struct CallbackDataType { HostFnType UserFn; void *UserData; @@ -1205,14 +2009,14 @@ struct AMDGPUStreamTy { /// should be executed. Notice we use the post action mechanism to codify the /// asynchronous operation. static bool asyncActionCallback(hsa_signal_value_t Value, void *Args) { - StreamSlotTy *Slot = reinterpret_cast(Args); - assert(Slot && "Invalid slot"); - assert(Slot->Signal && "Invalid signal"); - // This thread is outside the stream mutex. Make sure the thread sees the // changes on the slot. std::atomic_thread_fence(std::memory_order_acquire); + StreamSlotTy *Slot = reinterpret_cast(Args); + assert(Slot && "Invalid slot"); + assert(Slot->Signal && "Invalid signal"); + // Perform the operation. if (auto Err = Slot->performAction()) FATAL_MESSAGE(1, "Error performing post action: %s", @@ -1279,6 +2083,78 @@ struct AMDGPUStreamTy { return Plugin::success(); } + template static uint64_t getKernelDuration(Ty *Args) { + assert(Args->Signal && + "Invalid AMDGPUSignal Pointer for obtaining kernel duration"); + hsa_amd_profiling_dispatch_time_t TimeRec; + hsa_amd_profiling_get_dispatch_time(Args->Agent, Args->Signal->get(), + &TimeRec); + + uint64_t StartTime = TimeRec.start * Args->TicksToTime; + uint64_t EndTime = TimeRec.end * Args->TicksToTime; + + return EndTime - StartTime; + } + + /// Callback funtion to process the data for each kernel run. + static Error postKernelRunProcessingAction(void *Data) { + assert(Data && "Invalid data pointer for post kernel run processing"); + PostKernelRunProcessingArgsTy *Args = + reinterpret_cast(Data); + + KernelRunRecordTy *KernelRecord = Args->KernelRunRecords; + assert(KernelRecord && "KernelRunRecord is null!"); + + uint64_t KernelDuration = + getKernelDuration(Args); + KernelRecord->addEntry(Args->KernelName, Args->NumTeams, Args->NumThreads, + KernelDuration); + + if (getInfoLevel() & OMP_INFOTYPE_AMD_KERNEL_TRACE) { + fprintf(stderr, + "[Autotuning run] Kernel %s with %u teams and %u threads " + "completed in %lu ns.\n", + Args->KernelName.c_str(), Args->NumTeams, Args->NumThreads, + KernelDuration); + } + return Plugin::success(); + } + + /// Callback function to generate traces for kernel runtime. + static Error KernelDurationTracingAction(void *Data) { + assert(Data && "Invalid data pointer for tracing kernel duration"); + KernelDurationTracingArgsTy *Args = + reinterpret_cast(Data); + + uint64_t KernelDuration = + getKernelDuration(Args); + + fprintf( + stderr, + "DeviceID: %2d LaunchID: %2d TeamsXthrds:(%4uX%4d) Duration(ns): %lu\n", + Args->DeviceId, Args->LaunchId, Args->NumTeams, Args->NumThreads, + KernelDuration); + + return Plugin::success(); + } + + /// Callback function used by GenericProfiler to capture kernel exec times. + static Error timeKernelInNsAsync(void *Data) { + assert(Data && "Invalid data pointer timeKernelInNsAsync"); + auto ProfilerInfo = getProfilingInfo(Data); + + assert(ProfilerInfo && "Invalid args pointer in timeKernelInNsAsync"); + assert(ProfilerInfo->ProfilerSpecificData && + "Invalid ProfilerSpecificData in timeKernelInNsAsync"); + + auto [StartTime, EndTime] = getKernelStartAndEndTime(ProfilerInfo); + + ProfilerInfo->Plugin->getProfiler()->handleKernelCompletion( + StartTime, EndTime, ProfilerInfo->ProfilerSpecificData); + + return Plugin::success(); + } + public: /// Create an empty stream associated with a specific device. AMDGPUStreamTy(AMDGPUDeviceTy &Device); @@ -1289,14 +2165,17 @@ struct AMDGPUStreamTy { /// Deinitialize the stream's signals. Error deinit() { return Plugin::success(); } + hsa_queue_t *getHsaQueue() { return Queue->getHsaQueue(); } + /// Push a asynchronous kernel to the stream. The kernel arguments must be /// placed in a special allocation for kernel args and must keep alive until /// the kernel finalizes. Once the kernel is finished, the stream will release /// the kernel args buffer to the specified memory manager. Error pushKernelLaunch(const AMDGPUKernelTy &Kernel, void *KernelArgs, uint32_t NumThreads[3], uint32_t NumBlocks[3], - uint32_t GroupSize, uint64_t StackSize, - AMDGPUMemoryManagerTy &MemoryManager) { + uint32_t GroupSize, uint32_t StackSize, + AMDGPUMemoryManagerTy &MemoryManager, + void *ProfilerSpecificData = nullptr) { if (Queue == nullptr) return Plugin::error(ErrorCode::INVALID_NULL_POINTER, "target queue was nullptr"); @@ -1317,6 +2196,58 @@ struct AMDGPUStreamTy { if (auto Err = Slots[Curr].schedReleaseBuffer(KernelArgs, MemoryManager)) return Err; + // TODO: Technically this conditional compilation is not needed anymore +#ifdef OMPT_SUPPORT + if (ProfilerSpecificData) { + + // ProfilerSpecificData holds function pointer to finish trace record once + // the kernel completed. + if (auto Err = Slots[Curr].schedProfilerKernelTiming( + &Device, Agent, OutputSignal, TicksToTime, ProfilerSpecificData)) + return Err; + } +#endif + + // If runtime autotuning is enabled, setup the callback functions to process + // the data after kernel completed. + if (Device.enableRuntimeAutotuning() && Kernel.isSPMDMode()) { + std::string KernelName(Kernel.getName()); + KernelRunRecordTy *KernelRecords = Device.getKernelRunRecords(); + assert(KernelRecords && "No KernelRecords!"); + + // If this kernel has reached the run limit, + // skip registering the callback function. + if (!KernelRecords->reachedRunLimitForKernel(KernelName)) { + PostKernelRunProcessingArgs.Agent = Agent; + PostKernelRunProcessingArgs.Signal = OutputSignal; + PostKernelRunProcessingArgs.KernelName = KernelName; + PostKernelRunProcessingArgs.NumTeams = NumBlocks[0]; + PostKernelRunProcessingArgs.NumThreads = NumThreads[0]; + PostKernelRunProcessingArgs.KernelRunRecords = KernelRecords; + + if (auto Err = Slots[Curr].schedCallback(postKernelRunProcessingAction, + &PostKernelRunProcessingArgs)) + return Err; + } + } + + // When LIBOMPTARGET_KERNEL_EXE_TIME is set, register the callback function + // to get the kernel duration. + if (Device.enableKernelDurationTracing()) { + KernelDurationTracingArgs.Agent = Agent; + KernelDurationTracingArgs.Signal = OutputSignal; + KernelDurationTracingArgs.DeviceId = Device.getDeviceId(); + KernelDurationTracingArgs.LaunchId = Kernel.getKernelLaunchId(); + KernelDurationTracingArgs.NumTeams = NumBlocks[0]; + KernelDurationTracingArgs.NumThreads = NumThreads[0]; + + if (auto Err = Slots[Curr].schedCallback(KernelDurationTracingAction, + &KernelDurationTracingArgs)) + return Err; + } + + // Push the kernel with the output signal and an input signal (optional) + DP("Using Queue: %p with HSA Queue: %p\n", Queue, Queue->getHsaQueue()); // If we are running an RPC server we want to wake up the server thread // whenever there is a kernel running and let it sleep otherwise. if (Device.getRPCServer()) @@ -1344,8 +2275,8 @@ struct AMDGPUStreamTy { } /// Push an asynchronous memory copy between pinned memory buffers. - Error pushPinnedMemoryCopyAsync(void *Dst, const void *Src, - uint64_t CopySize) { + Error pushPinnedMemoryCopyAsync(void *Dst, const void *Src, uint64_t CopySize, + void *ProfilerSpecificData = nullptr) { // Retrieve an available signal for the operation's output. AMDGPUSignalTy *OutputSignal = nullptr; if (auto Err = SignalManager.getResource(OutputSignal)) @@ -1358,6 +2289,16 @@ struct AMDGPUStreamTy { // Consume stream slot and compute dependencies. auto [Curr, InputSignal] = consume(OutputSignal); + // TODO: Technically this conditional compilation is not needed anymore +#ifdef OMPT_SUPPORT + if (ProfilerSpecificData) { + // Capture the time the data transfer required for the d2h transfer. + if (auto Err = Slots[Curr].schedProfilerDataTransferTiming( + &Device, Agent, OutputSignal, TicksToTime, ProfilerSpecificData)) + return Err; + } +#endif + // Issue the async memory copy. if (InputSignal && InputSignal->load()) { hsa_signal_t InputSignalRaw = InputSignal->get(); @@ -1379,7 +2320,8 @@ struct AMDGPUStreamTy { /// manager once the operation completes. Error pushMemoryCopyD2HAsync(void *Dst, const void *Src, void *Inter, uint64_t CopySize, - AMDGPUMemoryManagerTy &MemoryManager) { + AMDGPUMemoryManagerTy &MemoryManager, + void *ProfilerSpecificData = nullptr) { // Retrieve available signals for the operation's outputs. AMDGPUSignalTy *OutputSignals[2] = {}; if (auto Err = SignalManager.getResources(/*Num=*/2, OutputSignals)) @@ -1398,6 +2340,22 @@ struct AMDGPUStreamTy { if (auto Err = Slots[Curr].schedReleaseBuffer(Inter, MemoryManager)) return Err; + // Wait for kernel to finish before scheduling the asynchronous copy. + if (UseSyncCopyBack && InputSignal && InputSignal->load()) + if (auto Err = InputSignal->wait(StreamBusyWaitMicroseconds, &Device)) + return Err; + + // TODO: Technically this conditional compilation is not needed anymore +#ifdef OMPT_SUPPORT + if (ProfilerSpecificData) { + // Capture the time the data transfer required for the d2h transfer. + if (auto Err = Slots[Curr].schedProfilerDataTransferTiming( + &Device, Agent, OutputSignals[0], TicksToTime, + ProfilerSpecificData)) + return Err; + } +#endif + // Issue the first step: device to host transfer. Avoid defining the input // dependency if already satisfied. if (InputSignal && InputSignal->load()) { @@ -1413,6 +2371,14 @@ struct AMDGPUStreamTy { return Err; } + if (CopySize < OMPX_MinHostToHostAsyncCopySize) { + if (auto Err = + OutputSignals[0]->wait(StreamBusyWaitMicroseconds, &Device)) + return Err; + std::memcpy(Dst, Inter, CopySize); + return Error::success(); + } + // Consume another stream slot and compute dependencies. std::tie(Curr, InputSignal) = consume(OutputSignals[1]); assert(InputSignal && "Invalid input signal"); @@ -1442,6 +2408,7 @@ struct AMDGPUStreamTy { Error pushMemoryCopyH2DAsync(void *Dst, const void *Src, void *Inter, uint64_t CopySize, AMDGPUMemoryManagerTy &MemoryManager, + void *ProfilerSpecificData = nullptr, size_t NumTimes = 1) { // Retrieve available signals for the operation's outputs. AMDGPUSignalTy *OutputSignals[2] = {}; @@ -1502,6 +2469,17 @@ struct AMDGPUStreamTy { if (auto Err = Slots[Curr].schedReleaseBuffer(Inter, MemoryManager)) return Err; + // TODO: Technically, this conditional compilation is not needed anymore +#ifdef OMPT_SUPPORT + if (ProfilerSpecificData) { + // Capture the time the data transfer required for the d2h transfer. + if (auto Err = Slots[Curr].schedProfilerDataTransferTiming( + &Device, Agent, OutputSignals[0], TicksToTime, + ProfilerSpecificData)) + return Err; + } +#endif + // Issue the second step: host to device transfer. Avoid defining the input // dependency if already satisfied. if (InputSignal && InputSignal->load()) { @@ -1517,7 +2495,8 @@ struct AMDGPUStreamTy { // AMDGPUDeviceTy is incomplete here, passing the underlying agent instead Error pushMemoryCopyD2DAsync(void *Dst, hsa_agent_t DstAgent, const void *Src, - hsa_agent_t SrcAgent, uint64_t CopySize) { + hsa_agent_t SrcAgent, uint64_t CopySize, + void *ProfilerSpecificData = nullptr) { AMDGPUSignalTy *OutputSignal; if (auto Err = SignalManager.getResources(/*Num=*/1, &OutputSignal)) return Err; @@ -1529,6 +2508,16 @@ struct AMDGPUStreamTy { // Consume stream slot and compute dependencies. auto [Curr, InputSignal] = consume(OutputSignal); + // TODO: Technically, this conditional compilation is not needed anymore +#ifdef OMPT_SUPPORT + if (ProfilerSpecificData) { + // Capture the time the data transfer required for the d2h transfer. + if (auto Err = Slots[Curr].schedProfilerDataTransferTiming( + &Device, Agent, OutputSignal, TicksToTime, ProfilerSpecificData)) + return Err; + } +#endif + // The agents need to have access to the corresponding memory // This is presently only true if the pointers were originally // allocated by this runtime or the caller made the appropriate @@ -1790,14 +2779,24 @@ struct AMDGPUStreamManagerTy final AMDGPUStreamManagerTy(GenericDeviceTy &Device, hsa_agent_t HSAAgent) : GenericDeviceResourceManagerTy(Device), Device(Device), OMPX_QueueTracking("LIBOMPTARGET_AMDGPU_HSA_QUEUE_BUSY_TRACKING", true), - NextQueue(0), Agent(HSAAgent) {} + OMPX_EnableQueueProfiling("LIBOMPTARGET_AMDGPU_ENABLE_QUEUE_PROFILING", + false), + NextQueue(0), Agent(HSAAgent) { + // If OMPX_ENABLE_RUNTIME_AUTOTUNING or LIBOMPTARGET_KERNEL_EXE_TIME is + // enabled, set queue profiling to true. + if (Device.enableRuntimeAutotuning() || + Device.enableKernelDurationTracing()) { + OMPX_EnableQueueProfiling = true; + } + } Error init(uint32_t InitialSize, int NumHSAQueues, int HSAQueueSize) { Queues = std::vector(NumHSAQueues); QueueSize = HSAQueueSize; MaxNumQueues = NumHSAQueues; // Initialize one queue eagerly - if (auto Err = Queues.front().init(Device, Agent, QueueSize)) + if (auto Err = + Queues.front().init(Device, Agent, QueueSize, OMPX_EnableQueueProfiling)) return Err; return GenericDeviceResourceManagerTy::init(InitialSize); @@ -1830,6 +2829,17 @@ struct AMDGPUStreamManagerTy final }); } + /// Enable/disable profiling of the HSA queues. + void setHSAQueueProfiling(int Enable) { + // If queue profiling is enabled with an env-var, it means that + // profiling is already ON and should remain so all the time. + if (OMPX_EnableQueueProfiling) + return; + for (auto &Q : Queues) + if (Q.isInitialized()) + hsa_amd_profiling_set_profiler_enabled(Q.getHsaQueue(), Enable); + } + private: /// Search for and assign an preferably idle queue to the given Stream. If /// there is no queue without current users, choose the queue with the lowest @@ -1854,7 +2864,8 @@ struct AMDGPUStreamManagerTy final } // Make sure the queue is initialized, then add user & assign. - if (auto Err = Queues[Index].init(Device, Agent, QueueSize)) + if (auto Err = + Queues[Index].init(Device, Agent, QueueSize, OMPX_EnableQueueProfiling)) return Err; Queues[Index].addUser(); Stream->Queue = &Queues[Index]; @@ -1868,6 +2879,9 @@ struct AMDGPUStreamManagerTy final /// Envar for controlling the tracking of busy HSA queues. BoolEnvar OMPX_QueueTracking; + /// Envar for controlling whether to always profile HSA queues. + BoolEnvar OMPX_EnableQueueProfiling; + /// The next queue index to use for round robin selection. uint32_t NextQueue; @@ -1931,6 +2945,9 @@ struct AMDGenericDeviceTy { return Plugin::success(); } + AMDGPUMemoryPoolTy *getCoarseGrainedMemoryPool() { + return CoarseGrainedMemoryPools[0]; + } /// Retrieve and construct all memory pools from the device agent(s). virtual Error retrieveAllMemoryPools() = 0; @@ -2059,29 +3076,188 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { OMPX_NumQueues("LIBOMPTARGET_AMDGPU_NUM_HSA_QUEUES", 4), OMPX_QueueSize("LIBOMPTARGET_AMDGPU_HSA_QUEUE_SIZE", 512), OMPX_DefaultTeamsPerCU("LIBOMPTARGET_AMDGPU_TEAMS_PER_CU", 4), + OMPX_GenericSpmdTeamsPerCU( + "LIBOMPTARGET_AMDGPU_GENERIC_SPMD_TEAMS_PER_CU", 6), + OMPX_BigJumpLoopTeamsPerCU( + "LIBOMPTARGET_AMDGPU_BIG_JUMP_LOOP_TEAMS_PER_CU", 0), + OMPX_XTeamRedTeamsPerCU("LIBOMPTARGET_AMDGPU_XTEAM_RED_TEAMS_PER_CU", + 0), + OMPX_BigJumpLoopMaxTotalTeams( + "LIBOMPTARGET_AMDGPU_BIG_JUMP_LOOP_MAX_TOTAL_TEAMS", 1024 * 1024), + OMPX_LowTripCount("LIBOMPTARGET_AMDGPU_LOW_TRIPCOUNT", 9000), + OMPX_SmallBlockSize("LIBOMPTARGET_MIN_THREADS_FOR_LOW_TRIP_COUNT", 32), + OMPX_NumBlocksForLowTripcount("LIBOMPTARGET_BLOCKS_FOR_LOW_TRIP_COUNT", + 0), + OMPX_WavesPerCUForLowTripcount( + "LIBOMPTARGET_WAVES_PER_CU_FOR_LOW_TRIP_COUNT", 0), + OMPX_AdjustNumTeamsForSmallBlockSize("LIBOMPTARGET_AMDGPU_ADJUST_TEAMS", + 0), + OMPX_AdjustNumTeamsForXteamRedSmallBlockSize( + "LIBOMPTARGET_AMDGPU_ADJUST_XTEAM_RED_TEAMS", 1), + OMPX_GenericSpmdUseSmallBlockSize( + "LIBOMPTARGET_AMDGPU_GENERIC_SPMD_USE_SMALL_BLOCKSIZE", 1), OMPX_MaxAsyncCopyBytes("LIBOMPTARGET_AMDGPU_MAX_ASYNC_COPY_BYTES", - 1 * 1024 * 1024), // 1MB + 64 * 1024), OMPX_InitialNumSignals("LIBOMPTARGET_AMDGPU_NUM_INITIAL_HSA_SIGNALS", 64), + OMPX_ForceSyncRegions("OMPX_FORCE_SYNC_REGIONS", 0), OMPX_StreamBusyWait("LIBOMPTARGET_AMDGPU_STREAM_BUSYWAIT", 2000000), OMPX_UseMultipleSdmaEngines( - "LIBOMPTARGET_AMDGPU_USE_MULTIPLE_SDMA_ENGINES", false), - OMPX_ApuMaps("OMPX_APU_MAPS", false), AMDGPUStreamManager(*this, Agent), - AMDGPUEventManager(*this), AMDGPUSignalManager(*this), Agent(Agent), - HostDevice(HostDevice) {} + // setting default to true here appears to solve random sdma problem + "LIBOMPTARGET_AMDGPU_USE_MULTIPLE_SDMA_ENGINES", true), + OMPX_ApuMaps("OMPX_APU_MAPS", false), + OMPX_EnableGFX90ACoarseGrainUsmMaps( + "OMPX_ENABLE_GFX90A_COARSE_GRAIN_USM_MAPS", false), + OMPX_EnableGFX90ACoarseGrainSharedAlloc( + "OMPX_ENABLE_GFX90A_COARSE_GRAIN_SHARED_ALLOC", false), + OMPX_StrictSanityChecks("OMPX_STRICT_SANITY_CHECKS", false), + OMPX_SyncCopyBack("LIBOMPTARGET_SYNC_COPY_BACK", true), + OMPX_APUPrefaultMemcopy("LIBOMPTARGET_APU_PREFAULT_MEMCOPY", true), + OMPX_APUPrefaultMemcopySize("LIBOMPTARGET_APU_PREFAULT_MEMCOPY_SIZE", + 1 * 1024 * 1024), // 1MB + OMPX_DGPUMaps("OMPX_DGPU_MAPS", false), + OMPX_SharedDescriptorMaxSize("LIBOMPTARGET_SHARED_DESCRIPTOR_MAX_SIZE", + 0), + OMPX_EnableDevice2DeviceMemAccess( + "OMPX_ENABLE_DEVICE_TO_DEVICE_MEM_ACCESS", false), + AMDGPUStreamManager(*this, Agent), AMDGPUEventManager(*this), + AMDGPUSignalManager(*this), Agent(Agent), HostDevice(HostDevice) { + // Get config for envars. + const DeviceEnvarConfigTy &EnvarConfig = getEnvarConfig(); + // Check each envar if it was set by user. + if (!OMPX_UseMultipleSdmaEngines.isPresent()) { + OMPX_UseMultipleSdmaEngines = EnvarConfig.OMPX_UseMultipleSdmaEngines; + } + } ~AMDGPUDeviceTy() {} - /// Initialize the device, its resources and get its properties. - Error initImpl(GenericPluginTy &Plugin) override { - // First setup all the memory pools. - if (auto Err = initMemoryPools()) - return Err; - - char GPUName[64]; - if (auto Err = getDeviceAttr(HSA_AGENT_INFO_NAME, GPUName)) - return Err; - ComputeUnitKind = GPUName; + /// Return synchronous copy back status variable. + bool syncCopyBack() const { return OMPX_SyncCopyBack; } + + /// Returns the maximum of HSA queues to create + /// This reads a non-cached environment variable, don't call everywhere. + uint32_t getMaxNumHsaQueues() const { + // In case this environment variable is set: respect it and give it + // precendence + if (const char *GPUMaxHwQsEnv = getenv("GPU_MAX_HW_QUEUES")) { + uint32_t MaxGPUHwQueues = std::atoi(GPUMaxHwQsEnv); + if (MaxGPUHwQueues != OMPX_NumQueues) + DP("Different numbers of maximum HSA queues specified. Using %u\n", + MaxGPUHwQueues); + + return MaxGPUHwQueues; + } + // Otherwise use the regular environment variable + return OMPX_NumQueues; + } + + virtual uint32_t getOMPXGenericSpmdTeamsPerCU() const override { + return OMPX_GenericSpmdTeamsPerCU; + } + virtual uint32_t getOMPXBigJumpLoopTeamsPerCU() const override { + return OMPX_BigJumpLoopTeamsPerCU; + } + virtual uint32_t getXTeamRedTeamsPerCU() const override { + return OMPX_XTeamRedTeamsPerCU; + } + virtual uint32_t getOMPXBigJumpLoopMaxTotalTeams() const override { + return OMPX_BigJumpLoopMaxTotalTeams; + } + virtual uint32_t getOMPXLowTripCount() const override { + return OMPX_LowTripCount; + } + virtual uint32_t getOMPXSmallBlockSize() const override { + return OMPX_SmallBlockSize; + } + virtual uint32_t + getOMPXNumBlocksForLowTripcount(uint64_t LoopTripCount) const override { + uint32_t NumBlocks = 0; + + if (LoopTripCount > OMPX_LowTripCount) + return NumBlocks; + + // if NumBlocksForLowTripcount is set, it has the highest priority. + if (OMPX_NumBlocksForLowTripcount > 0) { + NumBlocks = OMPX_NumBlocksForLowTripcount; + DP("Small trip count loop: Using %u blocks\n", NumBlocks); + } + + // Next, check if the waves per CU is set. This will launch a number of + // blocks such that we only have at most OMPX_WavesPerCUForLowTripcount + // waves per CU. + if (OMPX_WavesPerCUForLowTripcount > 0) { + // Compute the number of waves per block. For sizes smaller than a full + // wave the size is 1. + uint32_t WavesPerBlock = (uint32_t)((OMPX_SmallBlockSize - 1) / 64) + 1; + DP("Small trip count loop: Using %u waves per block\n", WavesPerBlock); + + // We cannot return less than the number of CUs: + if (WavesPerBlock >= OMPX_WavesPerCUForLowTripcount) { + NumBlocks = NumComputeUnits; + DP("Small trip count loop: Using 1 block per CU\n"); + } else { + uint32_t BlocksPerCU = + (uint32_t)(OMPX_WavesPerCUForLowTripcount / WavesPerBlock); + DP("Small trip count loop: Using %u blocks per CU\n", BlocksPerCU); + NumBlocks = (uint32_t)(BlocksPerCU * NumComputeUnits); + } + } + + // Adjust the number of blocks to the trip count if number of blocks x + // threads is much larger than the loop trip count. + if (NumBlocks) { + if (LoopTripCount <= OMPX_SmallBlockSize) + NumBlocks = 1; + + uint32_t MaxBlocks = + (uint32_t)((LoopTripCount - 1) / OMPX_SmallBlockSize) + 1; + if (NumBlocks > MaxBlocks) { + NumBlocks = MaxBlocks; + DP("Small trip count loop: number of blocks capped to %u to fit loop " + "trip count\n", + NumBlocks); + } + } + return NumBlocks; + } + virtual uint32_t getOMPXAdjustNumTeamsForSmallBlockSize() const override { + return OMPX_AdjustNumTeamsForSmallBlockSize; + } + virtual uint32_t + getOMPXAdjustNumTeamsForXteamRedSmallBlockSize() const override { + return OMPX_AdjustNumTeamsForXteamRedSmallBlockSize; + } + virtual bool getOMPXGenericSpmdUseSmallBlockSize() const override { + return OMPX_GenericSpmdUseSmallBlockSize; + } + + uint64_t getDeviceTimeStamp() override { return getSystemTimestampInNs(); } + + /// Initialize the device, its resources and get its properties. + Error initImpl(GenericPluginTy &Plugin) override { + // First setup all the memory pools. + if (auto Err = initMemoryPools()) + return Err; + + setHSATicksToTimeConstant(); + + // At init we capture two time points for host and device. The two + // timepoints are spaced out to help smooth out their accuracy + // differences. + // libomp uses the CLOCK_REALTIME (via gettimeofday) to get + // the value for omp_get_wtime. So we use the same clock here to calculate + // the slope/offset and convert device time to omp_get_wtime via + // translate_time. + auto StartTime = getDHTime(); + + if (auto Err = preAllocateDeviceMemoryPool()) + return Err; + + char GPUName[64]; + if (auto Err = getDeviceAttr(HSA_AGENT_INFO_NAME, GPUName)) + return Err; + ComputeUnitKind = GPUName; // Get the wavefront size. uint32_t WavefrontSize = 0; @@ -2105,6 +3281,24 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Plugin::error(ErrorCode::UNSUPPORTED, "unexpected AMDGPU wavefront %d", WavefrontSize); + // To determine the correct scratch memory size per thread, we need to check + // the device architecure generation. Hence, we slice the major GFX version + // from the agent info (e.g. 'gfx90a' -> 9). + StringRef Arch(ComputeUnitKind); + unsigned GfxGen = 0u; + if (!llvm::to_integer(Arch.slice(sizeof("gfx") - 1, Arch.size() - 2), + GfxGen)) + return Plugin::error(ErrorCode::UNKNOWN, "Invalid GFX architecture string"); + + // TODO: Will try to eliminate this calculation, since its duplicated. + // See: 'getMaxWaveScratchSize' in 'llvm/lib/Target/AMDGPU/GCNSubtarget.h'. + // But we need to divide by WavefrontSize. + // For generations pre-gfx11: use 13-bit field in units of 256-dword, + // otherwise: 15-bit field in units of 64-dword. + MaxThreadScratchSize = (GfxGen < 11) + ? ((256 * 4) / WavefrontSize) * ((1 << 13) - 1) + : ((64 * 4) / WavefrontSize) * ((1 << 15) - 1); + // Get maximum number of workitems per workgroup. uint16_t WorkgroupMaxDim[3]; if (auto Err = @@ -2128,6 +3322,7 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { getDeviceAttr(HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT, ComputeUnits)) return Err; GridValues.GV_Default_Num_Teams = ComputeUnits * OMPX_DefaultTeamsPerCU; + NumComputeUnits = ComputeUnits; uint32_t WavesPerCU = 0; if (auto Err = @@ -2147,6 +3342,7 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { // Compute the number of queues and their size. OMPX_NumQueues = std::max(1U, std::min(OMPX_NumQueues.get(), MaxQueues)); OMPX_QueueSize = std::min(OMPX_QueueSize.get(), MaxQueueSize); + DP("Using a maximum of %u HSA queues\n", OMPX_NumQueues.get()); // Initialize stream pool. if (auto Err = AMDGPUStreamManager.init(OMPX_InitialNumStreams, @@ -2161,6 +3357,26 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { if (auto Err = AMDGPUSignalManager.init(OMPX_InitialNumSignals)) return Err; + // Take the second timepoints and compute the required metadata. + auto EndTime = getDHTime(); + deriveHostToDeviceClockOffset(StartTime, EndTime); + + uint32_t NumSdmaEngines = 0; + if (auto Err = + getDeviceAttr(HSA_AMD_AGENT_INFO_NUM_SDMA_ENG, NumSdmaEngines)) + return Err; + DP("The number of SDMA Engines: %i\n", NumSdmaEngines); + + uint32_t NumXGmiEngines = 0; + if (auto Err = + getDeviceAttr(HSA_AMD_AGENT_INFO_NUM_SDMA_XGMI_ENG, NumXGmiEngines)) + return Err; + DP("The number of XGMI Engines: %i\n", NumXGmiEngines); + + // Detect if we are in Multi-Device mode + if (OMPX_NumMultiDevices > 0) + IsMultiDeviceEnabled = true; + // Detect if XNACK is enabled SmallVector> Targets; if (auto Err = hsa_utils::getTargetTripleAndFeatures(Agent, Targets)) @@ -2172,6 +3388,22 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { if (auto Err = checkIfAPU()) return Err; + // detect if device is GFX90a. + if (auto Err = checkIfGFX90a()) + return Err; + + // detect if device is an MI300X. + if (auto Err = checkIfMI300x()) + return Err; + + // detect special cases for MI200 + specialBehaviorHandling(); + + // detect ROCm-specific environment variables + // for map and zero-copy control + // TODO: put them back in constructor + // readEnvVars(); + return Plugin::success(); } @@ -2202,6 +3434,8 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { // Invalidate agent reference. Agent = {0}; + delete CoarseGrainMemoryTable; + return Plugin::success(); } @@ -2292,6 +3526,8 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { /// See GenericDeviceTy::getComputeUnitKind(). std::string getComputeUnitKind() const override { return ComputeUnitKind; } + uint32_t getNumComputeUnits() const override { return NumComputeUnits; } + /// Returns the clock frequency for the given AMDGPU device. uint64_t getClockFrequency() const override { return ClockFrequency; } @@ -2303,7 +3539,7 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Plugin::error(ErrorCode::OUT_OF_RESOURCES, "failed to allocate memory for AMDGPU kernel"); - new (AMDGPUKernel) AMDGPUKernelTy(Name); + new (AMDGPUKernel) AMDGPUKernelTy(Name, Plugin.getGlobalHandler()); return *AMDGPUKernel; } @@ -2349,7 +3585,6 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { // Load the HSA executable. if (Error Err = AMDImage->loadExecutable(*this)) return std::move(Err); - return AMDImage; } @@ -2482,16 +3717,37 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { AMDGPUStreamTy *Stream = nullptr; void *PinnedPtr = nullptr; + // Obtain the OMPT-related callback data + auto ProfilerSpecificData = getOrNullProfilerSpecificData(AsyncInfoWrapper); + + // Prefault GPU page table in XNACK-Enabled case, on APUs, + // under the assumption that explicitly allocated memory + // will be fully accessed and that on-the-fly individual page faults + // perform worse than whole memory faulting. + if (OMPX_APUPrefaultMemcopy && Size >= OMPX_APUPrefaultMemcopySize && + IsAPU && IsXnackEnabled) + if (auto Err = prepopulatePageTableImpl(const_cast(HstPtr), Size)) + return Err; + // Use one-step asynchronous operation when host memory is already pinned. if (void *PinnedPtr = PinnedAllocs.getDeviceAccessiblePtrFromPinnedBuffer(HstPtr)) { if (auto Err = getStream(AsyncInfoWrapper, Stream)) return Err; - return Stream->pushPinnedMemoryCopyAsync(TgtPtr, PinnedPtr, Size); + return Stream->pushPinnedMemoryCopyAsync(TgtPtr, PinnedPtr, Size, + ProfilerSpecificData); } // For large transfers use synchronous behavior. - if (Size >= OMPX_MaxAsyncCopyBytes) { + // FIXME: Currently hsa async copy fails to see completion signal for + // non-x86 dataSubmit/Retrieve. Other non-x86 calls to asyncMemCopy + // work. So for now, skip async copy for non-x86 for dataSubmit + // and dataRetrive only. +#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) + if (OMPX_ForceSyncRegions || Size >= OMPX_MaxAsyncCopyBytes) { +#else + if (false) { +#endif if (AsyncInfoWrapper.hasQueue()) if (auto Err = synchronize(AsyncInfoWrapper)) return Err; @@ -2508,13 +3764,23 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Err; if (auto Err = hsa_utils::asyncMemCopy(useMultipleSdmaEngines(), TgtPtr, - Agent, PinnedPtr, Agent, Size, 0, - nullptr, Signal.get())) + Agent, PinnedPtr, Agent, Size, 0, + nullptr, Signal.get())) return Err; if (auto Err = Signal.wait(getStreamBusyWaitMicroseconds())) return Err; +#ifdef OMPT_SUPPORT + if (Plugin.getProfiler()->isProfilingEnabled()) { + ProfilingInfoTy OmptKernelTimingArgsAsync{ + &Plugin, Agent, &Signal, TicksToTime, ProfilerSpecificData}; + + if (auto Err = timeDataTransferInNsAsync(&OmptKernelTimingArgsAsync)) + return Err; + } +#endif + if (auto Err = Signal.deinit()) return Err; @@ -2532,7 +3798,8 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Err; return Stream->pushMemoryCopyH2DAsync(TgtPtr, HstPtr, PinnedPtr, Size, - PinnedMemoryManager); + PinnedMemoryManager, + ProfilerSpecificData); } /// Retrieve data from the device (device to host transfer). @@ -2541,17 +3808,38 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { AMDGPUStreamTy *Stream = nullptr; void *PinnedPtr = nullptr; + // Obtain the OMPT-related callback data + auto ProfilerSpecificData = getOrNullProfilerSpecificData(AsyncInfoWrapper); + + // Prefault GPU page table in XNACK-Enabled case, on APUs, + // under the assumption that explicitly allocated memory + // will be fully accessed and that on-the-fly individual page faults + // perform worse than whole memory faulting. + if (OMPX_APUPrefaultMemcopy && Size >= OMPX_APUPrefaultMemcopySize && + IsAPU && IsXnackEnabled) + if (auto Err = prepopulatePageTableImpl(const_cast(HstPtr), Size)) + return Err; + // Use one-step asynchronous operation when host memory is already pinned. if (void *PinnedPtr = PinnedAllocs.getDeviceAccessiblePtrFromPinnedBuffer(HstPtr)) { if (auto Err = getStream(AsyncInfoWrapper, Stream)) return Err; - - return Stream->pushPinnedMemoryCopyAsync(PinnedPtr, TgtPtr, Size); + return Stream->pushPinnedMemoryCopyAsync(PinnedPtr, TgtPtr, Size, + ProfilerSpecificData); } // For large transfers use synchronous behavior. - if (Size >= OMPX_MaxAsyncCopyBytes) { + // If OMPT is enabled or synchronous behavior is explicitly requested: + // FIXME: Currently hsa async copy fails to see completion signal for + // non-x86 dataSubmit/Retrieve. Other non-x86 calls to asyncMemCopy + // work. So for now, skip async copy for non-x86 for dataSubmit + // and dataRetrive only. +#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) + if (OMPX_ForceSyncRegions || Size >= OMPX_MaxAsyncCopyBytes) { +#else + if (false) { +#endif if (AsyncInfoWrapper.hasQueue()) if (auto Err = synchronize(AsyncInfoWrapper)) return Err; @@ -2575,6 +3863,16 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { if (auto Err = Signal.wait(getStreamBusyWaitMicroseconds())) return Err; +#ifdef OMPT_SUPPORT + if (Plugin.getProfiler()->isProfilingEnabled()) { + ProfilingInfoTy OmptKernelTimingArgsAsync{ + &Plugin, Agent, &Signal, TicksToTime, ProfilerSpecificData}; + + if (auto Err = timeDataTransferInNsAsync(&OmptKernelTimingArgsAsync)) + return Err; + } +#endif + if (auto Err = Signal.deinit()) return Err; @@ -2592,7 +3890,8 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Err; return Stream->pushMemoryCopyD2HAsync(HstPtr, TgtPtr, PinnedPtr, Size, - PinnedMemoryManager); + PinnedMemoryManager, + ProfilerSpecificData); } /// Exchange data between two devices within the plugin. @@ -2601,8 +3900,11 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { AsyncInfoWrapperTy &AsyncInfoWrapper) override { AMDGPUDeviceTy &DstDevice = static_cast(DstGenericDevice); + auto ProfilerSpecificData = getOrNullProfilerSpecificData(AsyncInfoWrapper); + // For large transfers use synchronous behavior. - if (Size >= OMPX_MaxAsyncCopyBytes) { + // If OMPT is enabled or synchronous behavior is explicitly requested: + if (OMPX_ForceSyncRegions || Size >= OMPX_MaxAsyncCopyBytes) { if (AsyncInfoWrapper.hasQueue()) if (auto Err = synchronize(AsyncInfoWrapper)) return Err; @@ -2619,6 +3921,16 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { if (auto Err = Signal.wait(getStreamBusyWaitMicroseconds())) return Err; +#ifdef OMPT_SUPPORT + if (Plugin.getProfiler()->isProfilingEnabled()) { + ProfilingInfoTy OmptKernelTimingArgsAsync{ + &Plugin, Agent, &Signal, TicksToTime, ProfilerSpecificData}; + + if (auto Err = timeDataTransferInNsAsync(&OmptKernelTimingArgsAsync)) + return Err; + } +#endif + return Signal.deinit(); } @@ -2629,7 +3941,8 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Plugin::success(); return Stream->pushMemoryCopyD2DAsync(DstPtr, DstDevice.getAgent(), SrcPtr, - getAgent(), (uint64_t)Size); + getAgent(), (uint64_t)Size, + ProfilerSpecificData); } /// Insert a data fence between previous data operations and the following @@ -2707,7 +4020,7 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Stream->pushMemoryCopyH2DAsync(TgtPtr, PatternPtr, PinnedPtr, PatternSize, PinnedMemoryManager, - Size / PatternSize); + nullptr, Size / PatternSize); } /// Initialize the async info @@ -2716,6 +4029,62 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Plugin::success(); } + Error setCoarseGrainMemoryImpl(void *ptr, int64_t size, + bool set_attr = true) override final { + // If the table has not yet been created, check if the gpu arch is + // MI200 and create it, but only if USM Map is enabled. + if (!IsEquippedWithGFX90A || !EnableGFX90ACoarseGrainUsmMaps) + return Plugin::error(ErrorCode::UNKNOWN, "Invalid request to set coarse grain mode"); + if (!CoarseGrainMemoryTable) + CoarseGrainMemoryTable = new AMDGPUMemTypeBitFieldTable( + AMDGPU_X86_64_SystemConfiguration::max_addressable_byte + + 1, // memory size + AMDGPU_X86_64_SystemConfiguration::page_size); + + if (CoarseGrainMemoryTable->contains((const uintptr_t)ptr, size)) + return Plugin::success(); + + // track coarse grain memory pages in local table for user queries. + CoarseGrainMemoryTable->insert((const uintptr_t)ptr, size); + + if (set_attr) { + // Ask ROCr to turn [ptr, ptr+size-1] pages to + // coarse grain. + hsa_amd_svm_attribute_pair_t tt; + tt.attribute = HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG; + tt.value = HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED; + hsa_status_t err = hsa_amd_svm_attributes_set(ptr, size, &tt, 1); + if (err != HSA_STATUS_SUCCESS) { + return Plugin::error(ErrorCode::UNKNOWN, "Failed to switch memotry to coarse grain mode."); + } + } + + return Plugin::success(); + } + + uint32_t queryCoarseGrainMemoryImpl(const void *ptr, + int64_t size) override final { + // If the table has not yet been created it means that + // no memory has yet been set to coarse grain. + if (!CoarseGrainMemoryTable) + return 0; + + return CoarseGrainMemoryTable->contains((const uintptr_t)ptr, size); + } + + Error prepopulatePageTableImpl(void *ptr, int64_t size) override final { + // Instruct runtimes that the [ptr, ptr+size-1] pages will be accessed by + // devices but should not be migrated (only perform page faults, if needed). + hsa_amd_svm_attribute_pair_t tt; + tt.attribute = HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE; + tt.value = Agent.handle; + hsa_status_t err = hsa_amd_svm_attributes_set(ptr, size, &tt, 1); + if (err != HSA_STATUS_SUCCESS) { + return Plugin::error(ErrorCode::UNKNOWN, "Failed to prepopulate GPU page table."); + } + return Plugin::success(); + } + interop_spec_t selectInteropPreference(int32_t InteropType, int32_t NumPrefers, interop_spec_t *Prefers) override { @@ -3059,7 +4428,54 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { /// XNACK can be enabled with a kernel boot parameter or with /// the HSA_XNACK environment variable. bool useAutoZeroCopyImpl() override { - return ((IsAPU || OMPX_ApuMaps) && IsXnackEnabled); + return !(OMPX_DGPUMaps && IsAPU) && + ((IsAPU || OMPX_ApuMaps) && IsXnackEnabled); + } + + /// Performs sanity checks on the selected zero-copy configuration and prints + /// diagnostic information. + Error zeroCopySanityChecksAndDiagImpl(bool isUnifiedSharedMemory, + bool isAutoZeroCopy, + bool isEagerMaps) override { + // Implementation sanity checks: either unified_shared_memory or auto + // zero-copy, not both + if (isUnifiedSharedMemory && isAutoZeroCopy) + return Plugin::error(ErrorCode::UNKNOWN, + "Internal runtime error: cannot be both " + "unified_shared_memory and auto zero-copy."); + + // The following IsXnackEnable variables comes from compiler flags so it + // might be true even when we run with HSA_XNACK=0. + if (IsXnackEnabled) + INFO(OMP_INFOTYPE_USER_DIAGNOSTIC, getDeviceId(), "XNACK is enabled.\n"); + else + INFO(OMP_INFOTYPE_USER_DIAGNOSTIC, getDeviceId(), "XNACK is disabled.\n"); + if (isUnifiedSharedMemory) + INFO(OMP_INFOTYPE_USER_DIAGNOSTIC, getDeviceId(), + "Application configured to run in zero-copy using " + "unified_shared_memory.\n"); + else if (isAutoZeroCopy) + INFO( + OMP_INFOTYPE_USER_DIAGNOSTIC, getDeviceId(), + "Application configured to run in zero-copy using auto zero-copy.\n"); + if (isEagerMaps) + INFO(OMP_INFOTYPE_USER_DIAGNOSTIC, getDeviceId(), + "Requested pre-faulting of GPU page tables.\n"); + + // Sanity checks: selecting unified_shared_memory with XNACK-Disabled + // triggers a warning that can be turned into a fatal error using an + // environment variable. + if (isUnifiedSharedMemory && !IsXnackEnabled) { + MESSAGE0( + "Running a program that requires XNACK on a system where XNACK is " + "disabled. This may cause problems when using an OS-allocated " + "pointer " + "inside a target region. " + "Re-run with HSA_XNACK=1 to remove this warning."); + if (OMPX_StrictSanityChecks) + llvm_unreachable("User-requested hard stop on sanity check errors."); + } + return Plugin::success(); } Expected isAccessiblePtrImpl(const void *Ptr, size_t Size) override { @@ -3092,7 +4508,17 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Plugin::success(); } Error setDeviceStackSize(uint64_t Value) override { - StackSize = Value; + if (Value > MaxThreadScratchSize) { + // Cap device scratch size. + MESSAGE("Scratch memory size will be set to %d. Reason: Requested size " + "%ld would exceed available resources.", + MaxThreadScratchSize, Value); + StackSize = MaxThreadScratchSize; + } else { + // Apply device scratch size, since it is within limits. + StackSize = Value; + } + return Plugin::success(); } Error getDeviceHeapSize(uint64_t &Value) override { @@ -3106,6 +4532,7 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { DeviceMemoryPoolSize = Value; return Plugin::success(); } + Error getDeviceMemorySize(uint64_t &Value) override { for (AMDGPUMemoryPoolTy *Pool : AllMemoryPools) { if (Pool->isGlobal()) { @@ -3149,8 +4576,56 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { }); } + /// Propagate the enable/disable profiling request to the StreamManager. + void setHSAQueueProfiling(int Enable) { + AMDGPUStreamManager.setHSAQueueProfiling(Enable); + } + + /// Get the address of pointer to the preallocated device memory pool. + void *getPreAllocatedDeviceMemoryPool() { + return PreAllocatedDeviceMemoryPool; + } + + /// Allocate and zero initialize a small memory pool from the coarse grained + /// device memory of each device. + Error preAllocateDeviceMemoryPool() { + + void *DevPtr; + for (AMDGPUMemoryPoolTy *MemoryPool : AllMemoryPools) { + if (!MemoryPool->isGlobal()) + continue; + + if (MemoryPool->isCoarseGrained()) { + DevPtr = nullptr; + size_t PreAllocSize = hsa_utils::PER_DEVICE_PREALLOC_SIZE; + + Error Err = MemoryPool->allocate(PreAllocSize, &DevPtr); + if (Err) + return Plugin::error(ErrorCode::UNKNOWN, "Device memory pool preallocation failed"); + + Err = MemoryPool->enableAccess(DevPtr, PreAllocSize, {getAgent()}); + if (Err) + return Plugin::error(ErrorCode::UNKNOWN, "Preallocated device memory pool inaccessible"); + + Err = MemoryPool->zeroInitializeMemory(DevPtr, PreAllocSize); + if (Err) + return Plugin::error(ErrorCode::UNKNOWN, + "Zero initialization of preallocated device memory pool failed"); + + PreAllocatedDeviceMemoryPool = DevPtr; + } + } + return Plugin::success(); + } + bool useMultipleSdmaEngines() const { return OMPX_UseMultipleSdmaEngines; } + bool useSharedMemForDescriptor(int64_t Size) override { + return Size <= OMPX_SharedDescriptorMaxSize; + } + + bool useStrictSanityChecks() const { return OMPX_StrictSanityChecks; } + private: using AMDGPUEventRef = AMDGPUResourceRef; using AMDGPUEventManagerTy = GenericDeviceResourceManagerTy; @@ -3168,7 +4643,7 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return Plugin::success(); // Allocate and construct the AMDGPU kernel. - AMDGPUKernelTy AMDGPUKernel(KernelName); + AMDGPUKernelTy AMDGPUKernel(KernelName, Plugin.getGlobalHandler()); if (auto Err = AMDGPUKernel.init(*this, Image)) return Err; @@ -3190,22 +4665,50 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { /// Detect if current architecture is an APU. Error checkIfAPU() { // TODO: replace with ROCr API once it becomes available. + // MI300A llvm::StringRef StrGfxName(ComputeUnitKind); bool MayBeAPU = llvm::StringSwitch(StrGfxName) .Case("gfx942", true) .Default(false); - if (!MayBeAPU) + if (!MayBeAPU) // not gfx90a or gfx942 return Plugin::success(); - // can be MI300A or MI300X + // Can be MI300A or MI300X uint32_t ChipID = 0; if (auto Err = getDeviceAttr(HSA_AMD_AGENT_INFO_CHIP_ID, ChipID)) return Err; - if (!(ChipID & 0x1)) { + if (!(ChipID & 0x1)) IsAPU = true; + + return Plugin::success(); + } + + Error checkIfGFX90a() { + llvm::StringRef StrGfxName(ComputeUnitKind); + IsEquippedWithGFX90A = llvm::StringSwitch(StrGfxName) + .Case("gfx90a", true) + .Default(false); + return Plugin::success(); + } + + Error checkIfMI300x() { + llvm::StringRef StrGfxName(ComputeUnitKind); + + bool isMI300 = llvm::StringSwitch(StrGfxName) + .Case("gfx942", true) + .Default(false); + if (!isMI300) return Plugin::success(); - } + + // Can be MI300A or MI300X + uint32_t ChipID = 0; + if (auto Err = getDeviceAttr(HSA_AMD_AGENT_INFO_CHIP_ID, ChipID)) + return Err; + + if (ChipID & 0x1) + IsEquippedWithMI300X = true; + return Plugin::success(); } @@ -3243,6 +4746,50 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { return 0; } + /// Determines if + /// - Coarse graining upon USM map on MI200 needs to be enabled. + void specialBehaviorHandling() { + EnableGFX90ACoarseGrainUsmMaps = OMPX_EnableGFX90ACoarseGrainUsmMaps; + EnableGFX90ACoarseGrainSharedAlloc = + OMPX_EnableGFX90ACoarseGrainSharedAlloc; + } + + bool IsGfx90aCoarseGrainUsmMapEnabledImpl() override final { + return EnableGFX90ACoarseGrainUsmMaps; + } + + bool hasAPUDeviceImpl() override final { return IsAPU; } + + // TODO: move the following function in private section. + bool hasMI300xDevice() { return IsEquippedWithMI300X; } + + /// Returns whether the device is a gfx90a. + bool hasGfx90aDeviceImpl() override final { return IsEquippedWithGFX90A; } + + /// Returns whether AMD GPU supports unified memory in + /// the current configuration. + bool supportsUnifiedMemoryImpl() override final { return IsXnackEnabled; } + + /// Get the normalized marketing name of the device. + /// It only targets Instinct MI series for now. + /// e.g AMD Instinct MI210 => MI210 + std::string getNormMarketingName() const { + char MarketingName[64]; + hsa_status_t Status = hsa_agent_get_info( + Agent, static_cast(HSA_AMD_AGENT_INFO_PRODUCT_NAME), + MarketingName); + + if (Status != HSA_STATUS_SUCCESS) + return "UNKNOWN"; + + // Normalize + const char *MIPos = strstr(MarketingName, "MI"); + if (MIPos) + return std::string(MIPos); + + return "UNKNOWN"; + } + /// Envar for controlling the number of HSA queues per device. High number of /// queues may degrade performance. UInt32Envar OMPX_NumQueues; @@ -3258,6 +4805,69 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { /// #default_teams = OMPX_DefaultTeamsPerCU * #CUs. UInt32Envar OMPX_DefaultTeamsPerCU; + /// Envar for controlling the number of teams relative to the number of + /// compute units (CUs) for generic-SPMD kernels. 0 indicates that this value + /// is not specified, so instead OMPX_DefaultTeamsPerCU should be used. If + /// non-zero, the number of teams = OMPX_GenericSpmdTeamsPerCU * #CUs. + UInt32Envar OMPX_GenericSpmdTeamsPerCU; + + /// Envar for controlling the number of teams relative to the number of + /// compute units (CUs) for Big-Jump-Loop kernels. 0 indicates that this value + /// is not specified. If non-zero, the number of teams = + /// OMPX_BigJumpLoopTeamsPerCU * #CUs. + UInt32Envar OMPX_BigJumpLoopTeamsPerCU; + + /// Envar for controlling the number of teams relative to the number of + /// compute units (CUs) for cross-team-reduction kernels. 0 indicates that + /// this value is not specified. If non-zero, the number of teams = + /// OMPX_XTeamRedTeamsPerCU * #CUs. + UInt32Envar OMPX_XTeamRedTeamsPerCU; + + /// Envar controlling the maximum number of teams per device for + /// Big-Jump-Loop kernels. + UInt32Envar OMPX_BigJumpLoopMaxTotalTeams; + + /// Envar specifying tripcount below which the blocksize should be adjusted. + UInt32Envar OMPX_LowTripCount; + + /// Envar specifying a value till which the blocksize can be adjusted if the + /// tripcount is low. + UInt32Envar OMPX_SmallBlockSize; + + /// Envar for the number of blocks when the loop trip count is under the small + /// trip count limit. + /// The default value of 0 means that the number of blocks will be inferred by + /// the existing getNumBlocks logic. + UInt32Envar OMPX_NumBlocksForLowTripcount; + + /// Envar to set the number of waves per CU for small trip count loops. The + /// number of blocks will be adjusted such that there are no more than the + /// specified number of blocks per CU than this variable specifies. For + /// example: + /// Given: + // a GPU with CUs = 100 + /// and OMPX_WavesPerCUForLowTripcount = 8 + /// and a waves per block number of 4 (256 threads) + /// The total number of blocks will be: 200 + UInt32Envar OMPX_WavesPerCUForLowTripcount; + + /// Envar to allow adjusting number of teams after small tripcount + /// optimization. The default 0 means no adjustment of number of teams is + /// done. + UInt32Envar OMPX_AdjustNumTeamsForSmallBlockSize; + + /// Envar to allow scaling up the number of teams for Xteam-Reduction, + /// whenever the blocksize has been reduced from the max. The value 0 + /// indicates that this functionality is disabled. The default value is 1, + /// indicating that if the number of waves is lower than the max, increase the + /// number of teams proportionally. A value greater than 1 indicates that the + /// value should be used as the scaling factor for the number of teams. + UInt32Envar OMPX_AdjustNumTeamsForXteamRedSmallBlockSize; + + /// Envar indicating whether, for generic-SPMD kernels, the blocksize should + /// be reduced and the corresponding number of teams adjusted. + BoolEnvar OMPX_GenericSpmdUseSmallBlockSize; + /// Envar specifying the maximum size in bytes where the memory copies are /// asynchronous operations. Up to this transfer size, the memory copies are /// asynchronous operations pushed to the corresponding stream. For larger @@ -3270,7 +4880,9 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { /// will be created. UInt32Envar OMPX_InitialNumSignals; - /// Environment variables to set the time to wait in active state before + /// Envar to force synchronous target regions. The default 0 uses an + /// asynchronous implementation. + UInt32Envar OMPX_ForceSyncRegions; /// switching to blocked state. The default 2000000 busywaits for 2 seconds /// before going into a blocking HSA wait state. The unit for these variables /// are microseconds. @@ -3283,6 +4895,52 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { /// automatic zero-copy behavior on non-APU GPUs. BoolEnvar OMPX_ApuMaps; + /// Value of OMPX_ENABLE_GFX90A_COARSE_GRAIN_USM_MAPS. + /// Use on MI200 systems to enable coarse graining + /// of mapped variables (and other variables partially + /// or fully on the same memory page) under unified + /// shared memory. + /// + /// It was enabled by default up to Rocm6.3 + /// and env var spelling for controlling it was + /// OMPX_DISABLE_USM_MAPS + BoolEnvar OMPX_EnableGFX90ACoarseGrainUsmMaps; + + /// Value of OMPX_ENABLE_GFX90A_COARSE_GRAIN_SHARED_ALLOC. + /// Use on MI200 systems to enable coarse grain + /// allocation of TARGET_ALLOC_SHARED memory. + /// Default is fine grain allocation. + BoolEnvar OMPX_EnableGFX90ACoarseGrainSharedAlloc; + + /// Makes warnings turn into fatal errors + BoolEnvar OMPX_StrictSanityChecks; + + /// Variable to hold synchronous copy back + BoolEnvar OMPX_SyncCopyBack; + + /// On APUs, this env var indicates whether memory copy + /// should be preceded by pre-faulting of host memory, + /// to prevent page faults during the copy. + BoolEnvar OMPX_APUPrefaultMemcopy; + + /// On APUs, when prefaulting host memory before a copy, + /// this env var controls the size after which prefaulting + /// is applied. + UInt32Envar OMPX_APUPrefaultMemcopySize; + + /// Value of OMPX_DGPU_MAPS. When enabled, it will always perform + /// copy on APUs regardless of the setting of HSA_XNACK. + BoolEnvar OMPX_DGPUMaps; + + /// Descriptors of size <= to this value will be allocated using shared + /// memory. Default value is 48. + UInt32Envar OMPX_SharedDescriptorMaxSize; + + // Determines whether we call HSA API, upon device memory allocation, + // for making the memory acceccible from other agents. + // Default is disabled + BoolEnvar OMPX_EnableDevice2DeviceMemAccess; + /// Stream manager for AMDGPU streams. AMDGPUStreamManagerTy AMDGPUStreamManager; @@ -3298,6 +4956,9 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { /// The GPU architecture. std::string ComputeUnitKind; + /// The number of CUs available in this device + uint32_t NumComputeUnits; + /// The frequency of the steady clock inside the device. uint64_t ClockFrequency; @@ -3307,19 +4968,118 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { /// Reference to the host device. AMDHostDeviceTy &HostDevice; + // Data structure used to keep track of coarse grain memory regions + // on MI200 in unified_shared_memory programs only. + AMDGPUMemTypeBitFieldTable *CoarseGrainMemoryTable = nullptr; + + /// Pointer to the preallocated device memory pool + void *PreAllocatedDeviceMemoryPool; + /// The current size of the global device memory pool (managed by us). - uint64_t DeviceMemoryPoolSize = 1L << 29L /*512MB=*/; + uint64_t DeviceMemoryPoolSize = 1L << 29L /* 512MB */; /// The current size of the stack that will be used in cases where it could /// not be statically determined. - uint64_t StackSize = 16 * 1024 /* 16 KB */; + /// Default: 1024, in conformity to hipLimitStackSize. + uint32_t StackSize = 1024 /* 1 KB */; + + // The maximum scratch memory size per thread. + // See COMPUTE_TMPRING_SIZE.WAVESIZE (divided by threads per wave). + uint32_t MaxThreadScratchSize; /// Is the plugin associated with an APU? bool IsAPU = false; - /// True is the system is configured with XNACK-Enabled. + // Is the device an MI300X? + bool IsEquippedWithMI300X = false; + + // Is the device an MI200? + bool IsEquippedWithGFX90A = false; + + /// True if the system is configured with XNACK-Enabled. /// False otherwise. bool IsXnackEnabled = false; + + // Set by OMPX_ENABLE_GFX90A_COARSE_GRAIN_USM_MAPS environment variable. + // If set, under unified shared memory on MI200, fine grained memory page + // is switched to coarse grain (and stay coarse grain) if a variable + // residing on the page goes through implicit/explicit OpenMP map. + bool EnableGFX90ACoarseGrainUsmMaps = false; + + // Set by OMPX_ENABLE_GFX90A_COARSE_GRAIN_SHARED_ALLOC environment variable. + // If set, TARGET_ALLOC_SHARED is allocated on coarse grain memory on MI200 + bool EnableGFX90ACoarseGrainSharedAlloc = false; + + /// True if in multi-device mode. + bool IsMultiDeviceEnabled = false; + + /// Struct holding time in ns at a point in time for both host and device + /// This is used to compute a device-to-host offset and skew. Required for + /// OMPT function translate_time. + struct DevHostTimePair { + uint64_t Device; + double Host; + }; + + /// Get a DHTimepoint + DevHostTimePair getDHTime() const { + return DevHostTimePair{getSystemTimestampInNs(), getTimeOfDay()}; + } + + /// Compute time differences for host and device between Start and End + /// Assume host (h) timing is related to device (d) timing as + /// h = m.d + o, where m is the slope and o is the offset. + /// Calculate slope and offset from the two host and device timepoints. + void deriveHostToDeviceClockOffset(DevHostTimePair Start, DevHostTimePair End) { + double HostDiff = End.Host - Start.Host; + uint64_t DeviceDiff = End.Device - Start.Device; + double Slope = DeviceDiff != 0 ? (HostDiff / DeviceDiff) : HostDiff; + double Offset = Start.Host - Slope * Start.Device; + DP("Translate time Slope: %f Offset: %f\n", Slope, Offset); + Plugin.getProfiler()->setTimeConversionFactors(Slope, Offset); + } + + /// Representing all the runtime envar configs for a device. + struct DeviceEnvarConfigTy { + bool + OMPX_UseMultipleSdmaEngines; // LIBOMPTARGET_AMDGPU_USE_MULTIPLE_SDMA_ENGINES + }; + + static inline const std::unordered_map + EnvarConfigs = {{"MI210", {.OMPX_UseMultipleSdmaEngines = true}}, + {"MI300A", {.OMPX_UseMultipleSdmaEngines = false}}, + {"MI300X", {.OMPX_UseMultipleSdmaEngines = true}}, + // Default config for unknown devices. + {"DEFAULT", {.OMPX_UseMultipleSdmaEngines = true}}}; + + const DeviceEnvarConfigTy &getEnvarConfig() const { + std::string DeviceMarketingName = getNormMarketingName(); + auto It = EnvarConfigs.find(DeviceMarketingName); + + if (DeviceMarketingName == "UNKNOWN" || It == EnvarConfigs.end()) { + // Return default config + DP("Default envar config is used.\n"); + auto DefaultIt = EnvarConfigs.find("DEFAULT"); + + assert(DefaultIt != EnvarConfigs.end() && + "Default envar config not found!\n"); + return DefaultIt->second; + } + + DP("Envar config for %s is used.\n", DeviceMarketingName.c_str()); + + return It->second; + } + +public: + /// Return if it is an MI300 series device. + bool checkIfMI300Device() { + // Include MI300, MI300X, MI308. + llvm::StringRef StrGfxName(ComputeUnitKind); + return llvm::StringSwitch(StrGfxName) + .Case("gfx942", true) + .Default(false); + } }; Error AMDGPUDeviceImageTy::loadExecutable(const AMDGPUDeviceTy &Device) { @@ -3371,7 +5131,6 @@ Error AMDGPUDeviceImageTy::loadExecutable(const AMDGPUDeviceTy &Device) { Expected AMDGPUDeviceImageTy::findDeviceSymbol(GenericDeviceTy &Device, StringRef SymbolName) const { - AMDGPUDeviceTy &AMDGPUDevice = static_cast(Device); hsa_agent_t Agent = AMDGPUDevice.getAgent(); @@ -3386,6 +5145,16 @@ AMDGPUDeviceImageTy::findDeviceSymbol(GenericDeviceTy &Device, return Symbol; } +bool AMDGPUDeviceImageTy::hasDeviceSymbol(GenericDeviceTy &Device, + StringRef SymbolName) const { + AMDGPUDeviceTy &AMDGPUDevice = static_cast(Device); + hsa_agent_t Agent = AMDGPUDevice.getAgent(); + hsa_executable_symbol_t Symbol; + hsa_status_t Status = hsa_executable_get_symbol_by_name( + Executable, SymbolName.data(), &Agent, &Symbol); + return (Status == HSA_STATUS_SUCCESS); +} + template Error AMDGPUResourceRef::create(GenericDeviceTy &Device) { if (Resource) @@ -3405,7 +5174,10 @@ AMDGPUStreamTy::AMDGPUStreamTy(AMDGPUDeviceTy &Device) // Initialize the std::deque with some empty positions. Slots(32), NextSlot(0), SyncCycle(0), StreamBusyWaitMicroseconds(Device.getStreamBusyWaitMicroseconds()), - UseMultipleSdmaEngines(Device.useMultipleSdmaEngines()) {} + UseMultipleSdmaEngines(Device.useMultipleSdmaEngines()), + UseSyncCopyBack(Device.syncCopyBack()), + OMPX_MinHostToHostAsyncCopySize( + "LIBOMPTARGET_AMDGPU_MIN_HOST_TO_HOST_ASYNC_COPY_SIZE", 2048) {} /// Class implementing the AMDGPU-specific functionalities of the global /// handler. @@ -3483,6 +5255,10 @@ struct AMDGPUPluginTy final : public GenericPluginTy { // HSA functions from now on, e.g., hsa_shut_down. Initialized = true; + // This should probably be ASO-only + UInt32Envar KernTrace("LIBOMPTARGET_KERNEL_TRACE", 0); + llvm::omp::target::plugin::PrintKernelTrace = KernTrace.get(); + // Register event handler to detect memory errors on the devices. Status = hsa_amd_register_system_event_handler(eventHandler, this); if (auto Err = Plugin::check( @@ -3575,12 +5351,29 @@ struct AMDGPUPluginTy final : public GenericPluginTy { /// Get the ELF code for recognizing the compatible image binary. uint16_t getMagicElfBits() const override { return ELF::EM_AMDGPU; } + bool IsSystemSupportingManagedMemory() override final { + bool HasManagedMemorySupport = false; + hsa_status_t Status = hsa_system_get_info(HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED, + &HasManagedMemorySupport); + + if (Status != HSA_STATUS_SUCCESS) + return false; + + return HasManagedMemorySupport; + } + + void checkInvalidImage(__tgt_device_image *TgtImage) override final { + hsa_utils::checkImageCompatibilityWithSystemXnackMode(TgtImage, + IsXnackEnabled()); + } + /// Check whether the image is compatible with an AMDGPU device. Expected isELFCompatible(uint32_t DeviceId, StringRef Image) const override { // Get the associated architecture and flags from the ELF. - auto ElfOrErr = ELF64LEObjectFile::create( - MemoryBufferRef(Image, /*Identifier=*/""), /*InitContent=*/false); + auto ElfOrErr = + ELF64LEObjectFile::create(MemoryBufferRef(Image, /*Identifier=*/""), + /*InitContent=*/false); if (!ElfOrErr) return ElfOrErr.takeError(); std::optional Processor = ElfOrErr->tryGetCPUName(); @@ -3695,6 +5488,20 @@ struct AMDGPUPluginTy final : public GenericPluginTy { return HSA_STATUS_ERROR; } + // TODO: This duplicates code that uses the target triple and features + // to determine if XNACK is enabled. Merge into a single implementation + // if possible (is this info available in ROCm 5.7? This might not apply + // to trunk). + bool IsXnackEnabled() const { + bool hasSystemXnackEnabled = false; + hsa_status_t HsaStatus = hsa_system_get_info( + HSA_AMD_SYSTEM_INFO_XNACK_ENABLED, &hasSystemXnackEnabled); + if (HsaStatus != HSA_STATUS_SUCCESS) + return false; + + return hasSystemXnackEnabled; + } + /// Indicate whether the HSA runtime was correctly initialized. Even if there /// is no available devices this boolean will be true. It indicates whether /// we can safely call HSA functions (e.g., hsa_shut_down). @@ -3742,7 +5549,6 @@ Error AMDGPUKernelTy::launchImpl(GenericDeviceTy &GenericDevice, std::memcpy(AllArgs, LaunchParams.Data, LaunchParams.Size); AMDGPUDeviceTy &AMDGPUDevice = static_cast(GenericDevice); - AMDGPUStreamTy *Stream = nullptr; if (auto Err = AMDGPUDevice.getStream(AsyncInfoWrapper, Stream)) return Err; @@ -3754,6 +5560,7 @@ Error AMDGPUKernelTy::launchImpl(GenericDeviceTy &GenericDevice, reinterpret_cast( utils::advancePtr(AllArgs, ImplArgsOffset)); + DP("Setting fields of ImplicitArgs for COV5\n"); // Set the COV5+ implicit arguments to the appropriate values if present. uint64_t ImplArgsSize = ArgsSize - ImplArgsOffset; std::memset(ImplArgs, 0, ImplArgsSize); @@ -3782,15 +5589,81 @@ Error AMDGPUKernelTy::launchImpl(GenericDeviceTy &GenericDevice, KernelArgs.DynCGroupMem); } + // Get required OMPT-related data + auto ProfilerSpecificData = getOrNullProfilerSpecificData(AsyncInfoWrapper); + // Push the kernel launch into the stream. return Stream->pushKernelLaunch(*this, AllArgs, NumThreads, NumBlocks, - GroupSize, StackSize, ArgsMemoryManager); + GroupSize, static_cast(StackSize), + ArgsMemoryManager, ProfilerSpecificData); +} + +void AMDGPUKernelTy::printAMDOneLineKernelTrace(GenericDeviceTy &GenericDevice, + KernelArgsTy &KernelArgs, + uint32_t NumThreads[3], + uint32_t NumBlocks[3], + int64_t MultiDeviceLB, + int64_t MultiDeviceUB) const { + auto GroupSegmentSize = (*KernelInfo).GroupSegmentList; + auto SGPRCount = (*KernelInfo).SGPRCount; + auto VGPRCount = (*KernelInfo).VGPRCount; + auto AGPRCount = (*KernelInfo).AGPRCount; + auto SGPRSpillCount = (*KernelInfo).SGPRSpillCount; + auto VGPRSpillCount = (*KernelInfo).VGPRSpillCount; + // auto MaxFlatWorkgroupSize = (*KernelInfo).MaxFlatWorkgroupSize; + + if (GenericDevice.enableKernelDurationTracing()) { + uint32_t LaunchId = GenericDevice.getAndIncrementLaunchId(); + setKernelLaunchId(LaunchId); + + // Print Launch Id after Device Id. + fprintf(stderr, + "DEVID: %2d LaunchId: %u SGN:%d ConstWGSize:%-4d args:%2d " + "teamsXthrds:(%4uX%4d) " + "reqd:(%4dX%4d) lds_usage:%uB sgpr_count:%u vgpr_count:%u " + "agpr_count:%u " + "sgpr_spill_count:%u vgpr_spill_count:%u tripcount:%lu rpc:%d " + "md:%d md_LB:%ld md_UB:%ld Max Occupancy: %u Achieved Occupancy: " + "%d%% n:%s\n", + GenericDevice.getDeviceId(), LaunchId, getExecutionModeFlags(), + ConstWGSize, KernelArgs.NumArgs, NumBlocks[0], NumThreads[0], 0, 0, + GroupSegmentSize, SGPRCount, VGPRCount, AGPRCount, SGPRSpillCount, + VGPRSpillCount, KernelArgs.Tripcount, HasRPC, isMultiDeviceKernel(), + MultiDeviceLB, MultiDeviceUB, MaxOccupancy, AchievedOccupancy, + getName()); + } else { + + // This line should print exactly as the one in the old plugin. + fprintf(stderr, + "DEVID: %2d SGN:%d ConstWGSize:%-4d args:%2d teamsXthrds:(%4uX%4d) " + "reqd:(%4dX%4d) lds_usage:%uB sgpr_count:%u vgpr_count:%u " + "agpr_count:%u " + "sgpr_spill_count:%u vgpr_spill_count:%u tripcount:%lu rpc:%d " + "md:%d md_LB:%ld md_UB:%ld Max Occupancy: %u Achieved Occupancy: " + "%d%% n:%s\n", + GenericDevice.getDeviceId(), getExecutionModeFlags(), ConstWGSize, + KernelArgs.NumArgs, NumBlocks[0], NumThreads[0], 0, 0, + GroupSegmentSize, SGPRCount, VGPRCount, AGPRCount, SGPRSpillCount, + VGPRSpillCount, KernelArgs.Tripcount, HasRPC, isMultiDeviceKernel(), + MultiDeviceLB, MultiDeviceUB, MaxOccupancy, AchievedOccupancy, + getName()); + } } Error AMDGPUKernelTy::printLaunchInfoDetails(GenericDeviceTy &GenericDevice, KernelArgsTy &KernelArgs, uint32_t NumThreads[3], - uint32_t NumBlocks[3]) const { + uint32_t NumBlocks[3], + int64_t MultiDeviceLB, + int64_t MultiDeviceUB) const { + // When LIBOMPTARGET_KERNEL_TRACE is set, print the single-line kernel trace + // info present in the old ASO plugin, and continue with the upstream 2-line + // info, should LIBOMPTARGET_INFO be a meaningful value, otherwise return. + if ((getInfoLevel() & OMP_INFOTYPE_AMD_KERNEL_TRACE) || + GenericDevice.enableKernelDurationTracing()) + printAMDOneLineKernelTrace(GenericDevice, KernelArgs, NumThreads, NumBlocks, + MultiDeviceLB, MultiDeviceUB); + // Only do all this when the output is requested if (!(getInfoLevel() & OMP_INFOTYPE_PLUGIN_KERNEL)) return Plugin::success(); @@ -3906,6 +5779,11 @@ Expected AMDGPUDeviceTy::allocate(size_t Size, void *, break; } + if (Kind == TARGET_ALLOC_SHARED && IsEquippedWithGFX90A && + EnableGFX90ACoarseGrainSharedAlloc) { + MemoryPool = CoarseGrainedMemoryPools[0]; + } + if (!MemoryPool) return Plugin::error(ErrorCode::UNSUPPORTED, "no memory pool for the specified allocation kind"); @@ -3915,7 +5793,18 @@ Expected AMDGPUDeviceTy::allocate(size_t Size, void *, if (auto Err = MemoryPool->allocate(Size, &Alloc)) return std::move(Err); - if (Alloc) { + if (MemoryPool == CoarseGrainedMemoryPools[0] && IsEquippedWithGFX90A && + EnableGFX90ACoarseGrainUsmMaps) { + // Need to register in the coarse grain usm map table + // if not already registered. + if (auto Err = setCoarseGrainMemoryImpl(Alloc, Size, /*set_attr=*/false)) { + REPORT("%s\n", toString(std::move(Err)).data()); + return nullptr; + } + } + + if (Alloc && (Kind == TARGET_ALLOC_HOST || Kind == TARGET_ALLOC_SHARED || + OMPX_EnableDevice2DeviceMemAccess)) { // Get a list of agents that can access this memory pool. Inherently // necessary for host or shared allocations Also enabled for device memory // to allow device to device memcpy @@ -3933,6 +5822,66 @@ Expected AMDGPUDeviceTy::allocate(size_t Size, void *, return Alloc; } +/// Casts and checks the Profiler related information to not be nullptr. +static ProfilingInfoTy *getProfilingInfo(void *Data) { + ProfilingInfoTy *Args = reinterpret_cast(Data); + + // The ProfilerSpecific part can be nullptr, do not check here. + assert(Args && "Invalid argument pointer"); + assert(Args->Plugin && "Invalid plugin"); + assert(Args->Signal && "Invalid signal"); + + return Args; +} + +static std::pair +getKernelStartAndEndTime(const ProfilingInfoTy *Args) { + assert(Args->Plugin && "Invalid GenericPlugin pointer in profiling"); + assert(Args->Signal && "Invalid AMDGPUSignal pointer in profiling"); + + hsa_amd_profiling_dispatch_time_t TimeRec{0, 0}; + hsa_status_t Status = hsa_amd_profiling_get_dispatch_time( + Args->Agent, Args->Signal->get(), &TimeRec); + if (auto Err = Plugin::check( + Status, + "WARNING Could not retrieve kernel dispatch timestamps: %s")) { + MESSAGE0(toString(std::move(Err)).data()); + + // XXX Is this important enough to keep it? + // auto *AMDGPUDevice = reinterpret_cast(Args->Device); + // if (AMDGPUDevice->useStrictSanityChecks()) + // llvm_unreachable("User-requested hard stop on sanity check errors."); + } + + uint64_t StartTime = TimeRec.start * Args->TicksToTime; + uint64_t EndTime = TimeRec.end * Args->TicksToTime; + + return {StartTime, EndTime}; +} + +static std::pair +getCopyStartAndEndTime(const ProfilingInfoTy *Args) { + assert(Args->Signal && "Invalid AMDGPUSignal Pointer in profiling"); + + hsa_amd_profiling_async_copy_time_t TimeRec{0, 0}; + hsa_status_t Status = + hsa_amd_profiling_get_async_copy_time(Args->Signal->get(), &TimeRec); + if (auto Err = Plugin::check( + Status, "WARNING Could not retrieve data-copy timestamps: %s")) { + MESSAGE0(toString(std::move(Err)).data()); + + // XXX Is this important enough to keep it? + // auto *AMDGPUDevice = reinterpret_cast(Args->Device); + // if (AMDGPUDevice->useStrictSanityChecks()) + // llvm_unreachable("User-requested hard stop on sanity check errors."); + } + + uint64_t StartTime = TimeRec.start * Args->TicksToTime; + uint64_t EndTime = TimeRec.end * Args->TicksToTime; + + return {StartTime, EndTime}; +} + void AMDGPUQueueTy::callbackError(hsa_status_t Status, hsa_queue_t *Source, void *Data) { auto &AMDGPUDevice = *reinterpret_cast(Data); @@ -3955,11 +5904,129 @@ void AMDGPUQueueTy::callbackError(hsa_status_t Status, hsa_queue_t *Source, FATAL_MESSAGE(1, "%s", toString(std::move(Err)).data()); } +/// Compute the max kernel occupancy for AMD GPU +unsigned AMDGPUKernelTy::computeMaxOccupancy(GenericDeviceTy &Device) const { + uint32_t GroupSegmentSize = (*KernelInfo).GroupSegmentList; + uint32_t SGPRCount = (*KernelInfo).SGPRCount; + uint32_t VGPRCount = (*KernelInfo).VGPRCount; + uint32_t MaxFlatWorkgroupSize = (*KernelInfo).MaxFlatWorkgroupSize; + + // Default number of waves per EU + unsigned MaxWavesPerEU = llvm::omp::amdgpu_arch::MaxWavesPerEU10; + + // Get GPU info + AMDGPUDeviceTy &AMDDevice = static_cast(Device); + bool IsEquippedWithGFX90A = Device.hasGfx90aDevice(); + bool IsEquippedWithMI300 = AMDDevice.checkIfMI300Device(); + + if (IsEquippedWithGFX90A || IsEquippedWithMI300) { + MaxWavesPerEU = llvm::omp::amdgpu_arch::MaxWavesPerEU8; + } + + unsigned Occupancy = INT_MAX; + + // Contraint on SGPR + if (SGPRCount) { + Occupancy = getOccupancyWithNumSGPRs(SGPRCount); + } + + Occupancy = std::min(Occupancy, MaxWavesPerEU); + + // Constraint on VGPR + // Follow the logic on the backend + // Ref: + // llvm-project/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp:getNumWavesPerEUWithNumVGPRs + if (VGPRCount) { + unsigned WaveNumByVGPR = + llvm::omp::amdgpu_arch::VGPRNumPerThread / VGPRCount; + Occupancy = std::min(Occupancy, WaveNumByVGPR); + } + + // Constraint on LDS + if (GroupSegmentSize) { + unsigned WaveNumByLDS = getOccupancyWithLDS( + Device, GroupSegmentSize, MaxWavesPerEU, MaxFlatWorkgroupSize); + Occupancy = std::min(Occupancy, WaveNumByLDS); + } else { + // If 0 LDS required by the kernel + Occupancy = std::min(Occupancy, MaxWavesPerEU); + } + + // Cache the value before return + MaxOccupancy = Occupancy; + + return Occupancy; +} + +/// Compute the achieved kernel occupancy for AMD GPU. +unsigned AMDGPUKernelTy::computeAchievedOccupancy(GenericDeviceTy &Device, + uint32_t numThreads, + uint64_t numTeams) const { + // Check if max occupancy is available + if (MaxOccupancy <= 0) { + return 0; + } + + // Default number of waves per EU. + unsigned MaxWavesPerEU = llvm::omp::amdgpu_arch::MaxWavesPerEU10; + + // Get GPU info. + AMDGPUDeviceTy &AMDDevice = static_cast(Device); + bool IsEquippedWithGFX90A = Device.hasGfx90aDevice(); + bool IsEquippedWithMI300 = AMDDevice.checkIfMI300Device(); + + if (IsEquippedWithGFX90A || IsEquippedWithMI300) { + MaxWavesPerEU = llvm::omp::amdgpu_arch::MaxWavesPerEU8; + } + + // Get the max number of waves per CU. + unsigned MaxNumWaves = MaxOccupancy * llvm::omp::amdgpu_arch::SIMDPerCU; + // Get the number of waves from the kernel launch parameters. + unsigned AchievedNumWaves = + divideCeil(numThreads, AMDDevice.getWarpSize()) * numTeams; + // Get the number of waves per CU. + AchievedNumWaves = divideCeil(AchievedNumWaves, Device.getNumComputeUnits()); + // Get the min waves. + AchievedNumWaves = std::min(MaxNumWaves, AchievedNumWaves); + // Total number of wave slots each CU supports. + unsigned TotalWaveSlotsPerCU = + MaxWavesPerEU * llvm::omp::amdgpu_arch::SIMDPerCU; + // Compute occupancy ratio representing in percentage. + unsigned Occupancy = (AchievedNumWaves * 100) / TotalWaveSlotsPerCU; + + // Cache the result. + AchievedOccupancy = Occupancy; + + return Occupancy; +} + +/// Enable profiling of HSA queues +void setHSAQueueProfiling(void *Device, int Enable) { + reinterpret_cast(Device)->setHSAQueueProfiling(Enable); +} + } // namespace plugin } // namespace target } // namespace omp } // namespace llvm +#ifdef OMPT_SUPPORT +namespace llvm::omp::target::plugin { + +/// Enable/disable kernel profiling for the given device. +void setOmptQueueProfile(void *Device, int Enable) { + setHSAQueueProfiling(Device, Enable); +} + +} // namespace llvm::omp::target::plugin + +/// Enable/disable kernel profiling for the given device. +void setGlobalOmptKernelProfile(void *Device, int Enable) { + llvm::omp::target::plugin::setHSAQueueProfiling(Device, Enable); +} + +#endif + extern "C" { llvm::omp::target::plugin::GenericPluginTy *createPlugin_amdgpu() { return new llvm::omp::target::plugin::AMDGPUPluginTy(); diff --git a/offload/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h b/offload/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h index 77c756e006029..bc0eee89e61ec 100644 --- a/offload/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h +++ b/offload/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h @@ -26,6 +26,14 @@ namespace target { namespace plugin { namespace hsa_utils { +/// A list of offsets required by the ABI of code object versions 4 and 5. +enum COV_OFFSETS : uint32_t { + // 128 KB + PER_DEVICE_PREALLOC_SIZE = 131072 +}; + +typedef unsigned XnackBuildMode; + // The implicit arguments of COV5 AMDGPU kernels. struct alignas(alignof(void *)) AMDGPUImplicitArgsTy { uint32_t BlockCountX; @@ -36,9 +44,15 @@ struct alignas(alignof(void *)) AMDGPUImplicitArgsTy { uint16_t GroupSizeZ; uint8_t Unused0[46]; // 46 byte offset. uint16_t GridDims; - uint8_t Unused1[54]; // 54 byte offset. + uint8_t Unused1[30]; // 30 byte offset. + uint64_t HeapV1Ptr; + uint8_t Unused2[16]; // 16 byte offset. uint32_t DynamicLdsSize; - uint8_t Unused2[132]; // 132 byte offset. + uint8_t Unused3[132]; // 132 byte offset. +}; +// Dummy struct for COV4 implicitargs. +struct AMDGPUImplicitArgsTyCOV4 { + uint8_t Unused[56]; }; /// Returns the size in bytes of the implicit arguments of AMDGPU kernels. @@ -47,6 +61,51 @@ inline uint32_t getImplicitArgsSize(uint16_t Version) { return sizeof(AMDGPUImplicitArgsTy); } +// Check target image for XNACK mode (XNACK+, XNACK-ANY, XNACK-) +[[nodiscard]] XnackBuildMode +extractXnackModeFromBinary(const __tgt_device_image *TgtImage) { + assert((TgtImage != nullptr) && "TgtImage is nullptr."); + StringRef Buffer(reinterpret_cast(TgtImage->ImageStart), + utils::getPtrDiff(TgtImage->ImageEnd, TgtImage->ImageStart)); + auto ElfOrErr = + ELF64LEObjectFile::create(MemoryBufferRef(Buffer, /*Identifier=*/""), + /*InitContent=*/false); + if (auto Err = ElfOrErr.takeError()) { + consumeError(std::move(Err)); + DP("An error occured while reading ELF to extract XNACK mode\n"); + return ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4; + } + u_int16_t EFlags = ElfOrErr->getPlatformFlags(); + + hsa_utils::XnackBuildMode XnackFlags = EFlags & ELF::EF_AMDGPU_FEATURE_XNACK_V4; + + if (XnackFlags == ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4) + DP("XNACK is not supported on this system!\n"); + + return XnackFlags; +} + +void checkImageCompatibilityWithSystemXnackMode(__tgt_device_image *TgtImage, + bool IsXnackEnabled) { + hsa_utils::XnackBuildMode ImageXnackMode = + hsa_utils::extractXnackModeFromBinary(TgtImage); + + if (ImageXnackMode == ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4) + return; + + if (IsXnackEnabled && + (ImageXnackMode == ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4)) { + FAILURE_MESSAGE( + "Image is not compatible with current XNACK mode! XNACK is enabled " + "on the system but image was compiled with xnack-.\n"); + } else if (!IsXnackEnabled && + (ImageXnackMode == ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4)) { + FAILURE_MESSAGE("Image is not compatible with current XNACK mode! " + "XNACK is disabled on the system. However, the image " + "requires xnack+.\n"); + } +} + /// Reads the AMDGPU specific metadata from the ELF file and propagates the /// KernelInfoMap inline Error readAMDGPUMetaDataFromImage( diff --git a/offload/plugins-nextgen/amdgpu/utils/memtype.h b/offload/plugins-nextgen/amdgpu/utils/memtype.h new file mode 100644 index 0000000000000..14d421a172f5d --- /dev/null +++ b/offload/plugins-nextgen/amdgpu/utils/memtype.h @@ -0,0 +1,113 @@ +#ifndef __MEMTYPE_H__ +#define __MEMTYPE_H__ + +#include +#include +#include + +// uncomment to disable assert() +// #define NDEBUG +#include + +// Virtual memory configuration on Linux x86_64 +// for AMDGPU based systems +namespace AMDGPU_X86_64_SystemConfiguration { +const uint64_t max_addressable_byte = 0x00007fffffffffff; +// 4KB +const uint64_t page_size = 4 * 1024; +} // namespace AMDGPU_X86_64_SystemConfiguration + +// Bit field table to track single memory page type +class AMDGPUMemTypeBitFieldTable { +private: + // set \arg idx bit to 1 + inline void set(uint64_t &tab_loc, const uint64_t idx) { + tab_loc |= 1UL << idx; + } + + // test if \arg idx bit is set to 1 + inline bool isSet(const uint64_t tab_loc, const uint64_t idx) const { + return ((1UL << idx) == (tab_loc & (1UL << idx))); + } + + // return table index for page pointed to by \arg ptr + inline uint64_t calc_page_index(uintptr_t ptr) const { + return ptr >> log2page_size; + } + +public: + AMDGPUMemTypeBitFieldTable(uint64_t mem_size, uint64_t page_size) { + assert(mem_size % page_size == 0); + num_pages = mem_size / page_size; + log2page_size = log2l(page_size); + + log2_pages_per_block = log2l(pages_per_block); + assert((num_pages % 2) == 0); + uint64_t tab_size = num_pages >> log2_pages_per_block; + tab = (uint64_t *)calloc(tab_size, sizeof(uint64_t)); + } + + ~AMDGPUMemTypeBitFieldTable() { + if (tab) + free(tab); + } + + // Set all pages touched by address in the range [base, base+size-1] + // \arg base : pointer to first byte of the memory area whose + // type should become of the tracked type + // \arg size : size in bytes of the memory area whose type + // should become of the tracked type + // \ret if any of the pages was already set + inline bool insert(const uintptr_t base, size_t size) { + uint64_t page_start = calc_page_index(base); + uint64_t page_end = calc_page_index(base + size - 1); + uint64_t blockId = page_start >> log2_pages_per_block; + uint64_t blockOffset = page_start & (pages_per_block - 1); + for (uint64_t i = page_start; i <= page_end; i++) { + blockId = i >> log2_pages_per_block; + blockOffset = i & (pages_per_block - 1); + set(tab[blockId], blockOffset); + } + return false; + } + + // Test if all pages in the range [base, base+size-1] + // are of the tracked memory type. + // \arg base : pointer to first byte of the memory area whose + // type should become of the tracked type + // \arg size : number of bytes of the memory area whose type + // should become of the tracked type + // \ret true if any of the pages was set; false otherwise + bool contains(const uintptr_t base, size_t size) const { + uint64_t page_start = calc_page_index(base); + uint64_t page_end = calc_page_index(base + size - 1); + for (uint64_t i = page_start; i <= page_end; i++) { + uint64_t blockId = i >> log2_pages_per_block; + uint64_t blockOffset = i & (pages_per_block - 1); + if (!isSet(tab[blockId], blockOffset)) + return false; + } + return true; + } + +private: + uint64_t num_pages; + + // leading zero's for page size + // used to calculate index in table + uint64_t log2page_size; + + // number of pages tracked in a single table entry + // (uint64_t: one bit per page) + const int pages_per_block = 64; + int log2_pages_per_block; + + // the actual table that given a page index + // contains whether the page belongs to the tracked + // memory type. For any bit: + // 0 = page is *not* of tracked type + // 1 = page is of tracked type + uint64_t *tab = nullptr; +}; + +#endif //__MEMTYPE_H__ diff --git a/offload/plugins-nextgen/common/CMakeLists.txt b/offload/plugins-nextgen/common/CMakeLists.txt index ea0910abf95d5..198e2add6b2d3 100644 --- a/offload/plugins-nextgen/common/CMakeLists.txt +++ b/offload/plugins-nextgen/common/CMakeLists.txt @@ -7,6 +7,14 @@ tablegen(OFFLOAD include/OffloadErrcodes.inc -gen-errcodes -I ${CMAKE_CURRENT_SO tablegen(OFFLOAD include/OffloadInfo.inc -gen-info -I ${CMAKE_CURRENT_SOURCE_DIR}/../../liboffload/API) add_public_tablegen_target(PluginErrcodes) +if(OFFLOAD_ENABLE_EMISSARY_APIS) + set(emissary_sources + src/Emissary.cpp + src/EmissaryFortrt.cpp + src/EmissaryPrint.cpp + ) +endif() + # NOTE: Don't try to build `PluginInterface` using `add_llvm_library` because we # don't want to export `PluginInterface` while `add_llvm_library` requires that. add_library(PluginCommon OBJECT @@ -16,6 +24,8 @@ add_library(PluginCommon OBJECT src/RPC.cpp src/OffloadError.cpp src/Utils/ELF.cpp + src/GenericProfiler.cpp + ${emissary_sources} ) add_dependencies(PluginCommon intrinsics_gen PluginErrcodes) @@ -34,6 +44,30 @@ endif() # Include the RPC server from the `libc` project. include(FindLibcCommonUtils) target_link_libraries(PluginCommon PRIVATE llvm-libc-common-utilities) +if(OFFLOAD_ENABLE_EMISSARY_APIS AND LIBOMPTARGET_BUILD_DEVICE_FORTRT) + target_link_libraries(PluginCommon PRIVATE flang_rt.runtime + -L${CMAKE_BINARY_DIR}/../../lib -L${CMAKE_INSTALL_PREFIX}/lib) +endif() + +if (OMPT_TARGET_DEFAULT AND LIBOMPTARGET_OMPT_SUPPORT) + add_library(PluginOmpt STATIC OMPT/OmptTracing.cpp OMPT/OmptProfiler.cpp) + target_include_directories(PluginOmpt PUBLIC + OMPT + ${CMAKE_CURRENT_SOURCE_DIR}/include + ${CMAKE_CURRENT_BINARY_DIR}/include + ${LIBOMPTARGET_LLVM_INCLUDE_DIRS} + ${LIBOMPTARGET_BINARY_INCLUDE_DIR} + ${LIBOMPTARGET_INCLUDE_DIR} + ) + target_compile_options(PluginOmpt PUBLIC ${offload_compile_flags} -fPIC ) + target_link_options(PluginOmpt PUBLIC ${offload_link_flags}) + target_compile_definitions(PluginOmpt PRIVATE + TARGET_NAME="Profiler" + DEBUG_PREFIX="OMPT" + ) + add_dependencies(PluginOmpt PluginErrcodes) + +endif() # Define the TARGET_NAME and DEBUG_PREFIX. target_compile_definitions(PluginCommon PRIVATE @@ -43,6 +77,11 @@ target_compile_definitions(PluginCommon PRIVATE target_compile_options(PluginCommon PUBLIC ${offload_compile_flags}) target_link_options(PluginCommon PUBLIC ${offload_link_flags}) +if (LLVM_LINK_LLVM_DYLIB) + target_link_libraries(PluginCommon PRIVATE LLVM) +else() + target_link_libraries(PluginCommon PRIVATE LLVMProfileData) +endif() target_include_directories(PluginCommon PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include diff --git a/offload/plugins-nextgen/common/OMPT/OmptDeviceTracing.h b/offload/plugins-nextgen/common/OMPT/OmptDeviceTracing.h new file mode 100644 index 0000000000000..5744a784825da --- /dev/null +++ b/offload/plugins-nextgen/common/OMPT/OmptDeviceTracing.h @@ -0,0 +1,133 @@ +//===- OmptDeviceTracing.h - Target independent OMPT callbacks --*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Interface used by target-independent runtimes to coordinate registration and +// invocation of OMPT tracing functionality. +// +//===----------------------------------------------------------------------===// + +#ifndef OPENMP_LIBOMPTARGET_PLUGINS_NEXTGEN_COMMON_OMPTDEVICETRACING_H +#define OPENMP_LIBOMPTARGET_PLUGINS_NEXTGEN_COMMON_OMPTDEVICETRACING_H + +#ifdef OMPT_SUPPORT + +#include "OpenMP/OMPT/OmptCommonDefs.h" + +#include "llvm/Support/DynamicLibrary.h" + +#include +#include + +#pragma push_macro("DEBUG_PREFIX") +#undef DEBUG_PREFIX +#define DEBUG_PREFIX "OMPT" + +extern void setOmptAsyncCopyProfile(bool Enable); +extern void setGlobalOmptKernelProfile(void *Device, int Enable); +extern uint64_t getSystemTimestampInNs(); + +namespace llvm { +namespace omp { +namespace target { +namespace ompt { + +// Declare OMPT device tracing function entry points +#define declareOmptTracingFn(Name) extern libomptarget_##Name##_t Name##_fn; +FOREACH_OMPT_DEVICE_TRACING_FN_IMPLEMENTAIONS(declareOmptTracingFn) +#undef declareOmptTracingFn + +// Declare OMPT device tracing function mutexes +#define declareOmptTracingFnMutex(Name) extern std::mutex Name##_mutex; +FOREACH_OMPT_DEVICE_TRACING_FN_IMPLEMENTAIONS(declareOmptTracingFnMutex) +#undef declareOmptTracingFnMutex + +extern std::mutex DeviceIdWritingMutex; + +/// Activate tracing on the given device +void enableDeviceTracing(int DeviceId); + +/// Deactivate tracing on the given device +void disableDeviceTracing(int DeviceId); + +/// Set 'start' and 'stop' in trace records +void setOmptTimestamp(uint64_t StartTime, uint64_t EndTime); + +/// Set the linear function correlation between host and device clocks +void setOmptHostToDeviceRate(double Slope, double Offset); + +/// Set / store the number of granted teams in trace records +void setOmptGrantedNumTeams(uint64_t NumTeams); + +/// Lookup the given device pointer and return its RTL device ID +int getDeviceId(ompt_device_t *Device); + +/// Map the given device pointer to the given DeviceId +void setDeviceId(ompt_device_t *Device, int32_t DeviceId); + +/// Rempve the given device pointer from the current mapping +void removeDeviceId(ompt_device_t *Device); + +/// Check whether the provided device is currently traced. +bool isTracedDevice(int32_t DeviceId); + +/// Provide name based lookup for the device tracing functions +extern ompt_interface_fn_t +lookupDeviceTracingFn(const char *InterfaceFunctionName); + +/// Host to device linear clock correlation +extern double HostToDeviceSlope; + +/// Host to device constant clock offset +extern double HostToDeviceOffset; + +/// Mapping of device pointers to their corresponding RTL device ID +extern std::map Devices; + +/// Mapping of RTL device IDs to their currently enabled tracing event types. +/// Note: Event type '0' (bit position) indicates if this device is traced. +extern std::map TracedDevices; + +/// OMPT global tracing status. Indicates if at least one device is traced. +extern bool TracingActive; + +/// Parent library pointer +extern std::shared_ptr ParentLibrary; + +/// Get the parent library by pointer. If it is not already set, it will set the +/// parent library pointer. +std::shared_ptr getParentLibrary(); + +/// Set the parent library by filename +void setParentLibrary(const char *Filename); + +/// Search for FuncName inside the parent library and assign to FuncPtr. +/// IMPORTANT: This function assumes that the *caller* holds the respective lock +/// for FuncPtr. +template +void ensureFuncPtrLoaded(const std::string &FuncName, FT *FuncPtr) { + if (*FuncPtr == nullptr) { + if ((ParentLibrary == nullptr && getParentLibrary() == nullptr) || + !ParentLibrary->isValid()) + return; + void *SymbolPtr = ParentLibrary->getAddressOfSymbol(FuncName.c_str()); + if (SymbolPtr == nullptr) + return; + *FuncPtr = reinterpret_cast(SymbolPtr); + } +} + +} // namespace ompt +} // namespace target +} // namespace omp +} // namespace llvm + +#pragma pop_macro("DEBUG_PREFIX") + +#endif // OMPT_SUPPORT + +#endif // OPENMP_LIBOMPTARGET_PLUGINS_NEXTGEN_COMMON_OMPTDEVICETRACING_H diff --git a/offload/plugins-nextgen/common/OMPT/OmptProfiler.cpp b/offload/plugins-nextgen/common/OMPT/OmptProfiler.cpp new file mode 100644 index 0000000000000..2f1431bbc8578 --- /dev/null +++ b/offload/plugins-nextgen/common/OMPT/OmptProfiler.cpp @@ -0,0 +1,155 @@ +//===- OmptProfiler.cpp - OMPT impl of GenericProfilerTy --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Implementation of OmptProfilerTy +// +//===----------------------------------------------------------------------===// + +#include "OmptProfiler.h" +#include "OpenMP/OMPT/Interface.h" +#include "PluginInterface.h" +#include "Shared/Debug.h" + +using namespace llvm::omp::target; + +void ompt::OmptProfilerTy::handleInit(plugin::GenericDeviceTy *Device, + plugin::GenericPluginTy *Plugin) { + auto DeviceId = Device->getDeviceId(); + auto DevicePtr = reinterpret_cast(Device); + ompt::setDeviceId(DevicePtr, Plugin->getUserId(DeviceId)); + + if (ompt::Initialized) { + bool ExpectedStatus = false; + if (OmptInitialized.compare_exchange_strong(ExpectedStatus, true)) + performOmptCallback(device_initialize, Plugin->getUserId(DeviceId), + /*type=*/Device->getComputeUnitKind().c_str(), + /*device=*/DevicePtr, + /*lookup=*/ompt::lookupDeviceTracingFn, + /*documentation=*/nullptr); + } +} + +void ompt::OmptProfilerTy::handleDeinit( + plugin::GenericDeviceTy *Device, target::plugin::GenericPluginTy *Plugin) { + auto DeviceId = Device->getDeviceId(); + + if (ompt::Initialized) { + bool ExpectedStatus = true; + if (OmptInitialized.compare_exchange_strong(ExpectedStatus, false)) + performOmptCallback(device_finalize, Plugin->getUserId(DeviceId)); + } + ompt::removeDeviceId(reinterpret_cast(Device)); +} + +void ompt::OmptProfilerTy::handleLoadBinary(plugin::GenericDeviceTy *Device, + plugin::GenericPluginTy *Plugin, + const StringRef InputTgtImage) { + + if (!ompt::Initialized) + return; + + auto DeviceId = Device->getDeviceId(); + size_t Bytes = InputTgtImage.size(); + performOmptCallback( + device_load, Plugin->getUserId(DeviceId), + /*FileName=*/nullptr, /*FileOffset=*/0, /*VmaInFile=*/nullptr, + /*ImgSize=*/Bytes, + /*HostAddr=*/const_cast(InputTgtImage.bytes_begin()), + /*DeviceAddr=*/nullptr, /* FIXME: ModuleId */ 0); +} + +void ompt::OmptProfilerTy::handleDataAlloc(uint64_t StartNanos, + uint64_t EndNanos, void *HostPtr, + uint64_t Size, void *Data) { + ompt::setOmptTimestamp(StartNanos, EndNanos); +} + +void ompt::OmptProfilerTy::handleDataDelete(uint64_t StartNanos, + uint64_t EndNanos, void *TgtPtr, + void *Data) { + ompt::setOmptTimestamp(StartNanos, EndNanos); +} + +void ompt::OmptProfilerTy::handlePreKernelLaunch( + plugin::GenericDeviceTy *Device, uint32_t NumBlocks[3], + __tgt_async_info *AI) { + if (!ompt::isTracedDevice(getDeviceId(Device))) + return; + + if (AI->ProfilerData == nullptr) + return; + + auto ProfilerSpecificData = + reinterpret_cast(AI->ProfilerData); + assert(ProfilerSpecificData && "Invalid ProfilerSpecificData"); + // Set number of granted teams for OMPT + setOmptGrantedNumTeams(NumBlocks[0]); + ProfilerSpecificData->NumTeams = NumBlocks[0]; +} + +void ompt::OmptProfilerTy::handleKernelCompletion(uint64_t StartNanos, + uint64_t EndNanos, + void *Data) { + + if (!isProfilingEnabled()) + return; + + /// Empty data means no tracing in OMPT + /// offload/include/OpenMP/OMPT/Interface.h line 492 + if (!Data) + return; + + DP("OMPT-Async: Time kernel for asynchronous execution: Start %lu " + "End %lu\n", + StartNanos, EndNanos); + + auto OmptEventInfo = reinterpret_cast(Data); + assert(OmptEventInfo && "Invalid OmptEventInfo"); + assert(OmptEventInfo->TraceRecord && "Invalid TraceRecord"); + + ompt::RegionInterface.stopTargetSubmitTraceAsync(OmptEventInfo->TraceRecord, + OmptEventInfo->NumTeams, + StartNanos, EndNanos); + + // Done processing, our responsibility to free the memory + freeProfilerDataEntry(OmptEventInfo); +} + +void ompt::OmptProfilerTy::handleDataTransfer(uint64_t StartNanos, + uint64_t EndNanos, void *Data) { + + if (!isProfilingEnabled()) + return; + + /// Empty data means no tracing in OMPT + /// offload/include/OpenMP/OMPT/Interface.h line 492 + if (!Data) + return; + + DP("OMPT-Async: Time data for asynchronous execution: Start %lu " + "End %lu\n", + StartNanos, EndNanos); + + auto OmptEventInfo = reinterpret_cast(Data); + assert(OmptEventInfo && "Invalid OmptEventInfo"); + assert(OmptEventInfo->TraceRecord && "Invalid TraceRecord"); + + ompt::RegionInterface.stopTargetDataMovementTraceAsync( + OmptEventInfo->TraceRecord, StartNanos, EndNanos); + + // Done processing, our responsibility to free the memory + freeProfilerDataEntry(OmptEventInfo); +} + +bool ompt::OmptProfilerTy::isProfilingEnabled() { return ompt::TracingActive; } + +void ompt::OmptProfilerTy::setTimeConversionFactorsImpl(double Slope, + double Offset) { + DP("Using Time Slope: %f and Offset: %f \n", Slope, Offset); + setOmptHostToDeviceRate(Slope, Offset); +} diff --git a/offload/plugins-nextgen/common/OMPT/OmptProfiler.h b/offload/plugins-nextgen/common/OMPT/OmptProfiler.h new file mode 100644 index 0000000000000..251689699ea94 --- /dev/null +++ b/offload/plugins-nextgen/common/OMPT/OmptProfiler.h @@ -0,0 +1,162 @@ +//===- OmptProfiler.h - OMPT specific impl of GenericProfilerTy -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// OMPT specific implementation of the GenericProfilerTy class. +// This class uses the already existing implementation of OMPT to invoke +// callbacks and perform tracing. +// +//===----------------------------------------------------------------------===// + +#ifndef OFFLOAD_PLUGINS_NEXTGEN_COMMON_OMPT_OMPTPROFILERTY_H +#define OFFLOAD_PLUGINS_NEXTGEN_COMMON_OMPT_OMPTPROFILERTY_H + +#include "GenericProfiler.h" + +#include "OmptDeviceTracing.h" +#include "OpenMP/OMPT/Callback.h" +#include "Shared/Debug.h" +#include "omp-tools.h" + +#include +#include + +#pragma push_macro("DEBUG_PREFIX") +#undef DEBUG_PREFIX +#define DEBUG_PREFIX "OMPT" + +extern uint64_t getSystemTimestampInNs(); + +namespace llvm { +namespace omp { +namespace target { +namespace plugin { +struct GenericDeviceTy; +struct GenericPluginTy; +class GenericProfilerTy; + +} // namespace plugin + +namespace ompt { + +// From Callback.h / Callback.cpp +extern bool Initialized; + +/** + * Implements an OMPT backend for the Profiler interface used in the plugins. + * + * Forwards / Implements the different generic hooks with OMPT semantics. + */ +class OmptProfilerTy : public plugin::GenericProfilerTy { +public: + /** Public members **/ + OmptProfilerTy() { + + OmptInitialized.store(false); + // Bind the callbacks to this device's member functions +#define bindOmptCallback(Name, Type, Code) \ + if (ompt::Initialized && ompt::lookupCallbackByCode) { \ + ompt::lookupCallbackByCode((ompt_callbacks_t)(Code), \ + ((ompt_callback_t *)&(Name##_fn))); \ + DP("class bound %s=%p\n", #Name, ((void *)(uint64_t)Name##_fn)); \ + } + + FOREACH_OMPT_DEVICE_EVENT(bindOmptCallback); +#undef bindOmptCallback + +#define bindOmptTracingFunction(FunctionName) \ + if (ompt::Initialized && ompt::lookupDeviceTracingFn) { \ + FunctionName##_fn = ompt::lookupDeviceTracingFn(#FunctionName); \ + DP("device tracing fn bound %s=%p\n", #FunctionName, \ + ((void *)(uint64_t)FunctionName##_fn)); \ + } + + FOREACH_OMPT_DEVICE_TRACING_FN_COMMON(bindOmptTracingFunction); +#undef bindOmptTracingFunction + } + + bool isProfilingEnabled() override; + + void handleInit(plugin::GenericDeviceTy *Device, + plugin::GenericPluginTy *Plugin) override; + + void handleDeinit(plugin::GenericDeviceTy *Device, + plugin::GenericPluginTy *Plugin) override; + + void handleLoadBinary(plugin::GenericDeviceTy *Device, + plugin::GenericPluginTy *Plugin, + const StringRef InputTgtImage) override; + + void handleDataAlloc(uint64_t StartNanos, uint64_t EndNanos, void *HostPtr, + uint64_t Size, void *Data) override; + void handleDataDelete(uint64_t StartNanos, uint64_t EndNanos, void *TgtPtr, + void *Data) override; + + void handlePreKernelLaunch(plugin::GenericDeviceTy *Device, + uint32_t NumBlocks[3], + __tgt_async_info *AI) override; + + void handleKernelCompletion(uint64_t StartNanos, uint64_t EndNanos, + void *Data) override; + + void handleDataTransfer(uint64_t StartNanos, uint64_t EndNanos, + void *Data) override; + + void setTimeConversionFactorsImpl(double Slope, double Offset) override; + + void *getProfilerSpecificData() override { + // TODO: This is ID is not used currently + uint64_t Id = OmptProfDataId.fetch_add(1); + { + std::scoped_lock Lock(ProfilerDataMutex); + ProfilerData[Id] = std::make_unique(); + return ProfilerData[Id].get(); + } + } + + void freeProfilerDataEntry(OmptEventInfoTy *DataPtr) { + std::scoped_lock Lock(ProfilerDataMutex); + + for (auto &Entry : ProfilerData) + if (Entry.second.get() == DataPtr) { + ProfilerData.erase(Entry.first); + break; + } + } + +private: + /// Holds a unique ID for each allocation of OmptEventInfoTy + std::atomic OmptProfDataId{0}; + + /// Holds memory used to store OMPT specific data and pass it down from + /// libomptarget into the plugins. + std::map> ProfilerData; + + /// Lock to guard STL ProfilerData map + std::mutex ProfilerDataMutex; + + /// OMPT callback functions +#define defineOmptCallback(Name, Type, Code) Name##_t Name##_fn = nullptr; + FOREACH_OMPT_DEVICE_EVENT(defineOmptCallback) +#undef defineOmptCallback + + /// OMPT device tracing functions +#define defineOmptTracingFunction(Name) ompt_interface_fn_t Name##_fn = nullptr; + FOREACH_OMPT_DEVICE_TRACING_FN_COMMON(defineOmptTracingFunction); +#undef defineOmptTracingFunction + + /// Internal representation for OMPT device (initialize & finalize) + std::atomic OmptInitialized; +}; +} // namespace ompt +} // namespace target +} // namespace omp +} // namespace llvm + +#pragma pop_macro("DEBUG_PREFIX") + +#endif diff --git a/offload/plugins-nextgen/common/OMPT/OmptTracing.cpp b/offload/plugins-nextgen/common/OMPT/OmptTracing.cpp new file mode 100644 index 0000000000000..daf4e5f71b85a --- /dev/null +++ b/offload/plugins-nextgen/common/OMPT/OmptTracing.cpp @@ -0,0 +1,314 @@ +//===-- OmptTracing.cpp - Target independent OpenMP target RTL --- C++ -*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Implementation of OMPT tracing interfaces for PluginInterface +// +//===----------------------------------------------------------------------===// + +#ifdef OMPT_SUPPORT + +#include "Shared/Debug.h" +#include "OmptDeviceTracing.h" +#include "omp-tools.h" + +#include "llvm/Support/DynamicLibrary.h" + +#include +#include +#include +#include +#include +#include + +#pragma push_macro("DEBUG_PREFIX") +#undef DEBUG_PREFIX +#define DEBUG_PREFIX "OMPT" + +// Define OMPT device tracing function entry points +#define defineOmptTracingFn(Name) \ + libomptarget_##Name##_t llvm::omp::target::ompt::Name##_fn = nullptr; +FOREACH_OMPT_DEVICE_TRACING_FN_IMPLEMENTAIONS(defineOmptTracingFn) +#undef defineOmptTracingFn + +// Define OMPT device tracing function mutexes +#define defineOmptTracingFnMutex(Name) \ + std::mutex llvm::omp::target::ompt::Name##_mutex; +FOREACH_OMPT_DEVICE_TRACING_FN_IMPLEMENTAIONS(defineOmptTracingFnMutex) +#undef defineOmptTracingFnMutex + +std::mutex llvm::omp::target::ompt::DeviceIdWritingMutex; + +using namespace llvm::omp::target::ompt; + +std::shared_ptr + llvm::omp::target::ompt::ParentLibrary(nullptr); + +double llvm::omp::target::ompt::HostToDeviceSlope = .0; +double llvm::omp::target::ompt::HostToDeviceOffset = .0; + +std::map llvm::omp::target::ompt::Devices; + +std::shared_ptr +llvm::omp::target::ompt::getParentLibrary() { + static bool ParentLibraryAssigned = false; + if (!ParentLibraryAssigned) { + setParentLibrary("libomptarget.so"); + ParentLibraryAssigned = true; + } + return ParentLibrary; +} + +void llvm::omp::target::ompt::setParentLibrary(const char *Filename) { + if (ParentLibrary) + return; + std::string ErrorMsg; + ParentLibrary = std::make_shared( + llvm::sys::DynamicLibrary::getPermanentLibrary(Filename, &ErrorMsg)); + if ((ParentLibrary == nullptr) || (!ParentLibrary->isValid())) + REPORT("Failed to set parent library: %s\n", ErrorMsg.c_str()); +} + +int llvm::omp::target::ompt::getDeviceId(ompt_device_t *Device) { + // Block other threads, which might trigger an erase (for the same device) + std::unique_lock Lock(DeviceIdWritingMutex); + auto DeviceIterator = Devices.find(Device); + if (Device == nullptr || DeviceIterator == Devices.end()) { + REPORT("Failed to get ID for Device=%p\n", Device); + return -1; + } + return DeviceIterator->second; +} + +void llvm::omp::target::ompt::setDeviceId(ompt_device_t *Device, + int32_t DeviceId) { + assert(Device && "Mapping device ID to nullptr is not allowed"); + if (Device == nullptr || DeviceId < 0) { + REPORT("Failed to set ID=%d for Device=%p\n", DeviceId, Device); + return; + } + std::unique_lock Lock(DeviceIdWritingMutex); + auto DeviceIterator = Devices.find(Device); + if (DeviceIterator != Devices.end()) { + auto CurrentDeviceId = DeviceIterator->second; + if (DeviceId == CurrentDeviceId) { + REPORT("Tried to duplicate OMPT Device=%p (ID=%d)\n", Device, DeviceId); + } else { + REPORT("Tried to overwrite OMPT Device=%p (ID=%d with new ID=%d)\n", + Device, CurrentDeviceId, DeviceId); + } + return; + } + Devices.emplace(Device, DeviceId); +} + +void llvm::omp::target::ompt::removeDeviceId(ompt_device_t *Device) { + int DeviceId = getDeviceId(Device); + if (DeviceId < 0) { + REPORT("Failed to remove Device=%p (ID=%d)\n", Device, DeviceId); + return; + } + std::unique_lock Lock(DeviceIdWritingMutex); + Devices.erase(Device); + TracedDevices.erase(DeviceId); +} + +OMPT_API_ROUTINE ompt_set_result_t ompt_set_trace_ompt(ompt_device_t *Device, + unsigned int Enable, + unsigned int EventTy) { + DP("Executing ompt_set_trace_ompt\n"); + + int DeviceId = getDeviceId(Device); + if (DeviceId < 0) { + REPORT("Failed to set trace events for Device=%p (Unknown device) " + "[Enable=%d, EventTy=%d]\n", + Device, Enable, EventTy); + return ompt_set_never; + } + + std::unique_lock Lock(ompt_set_trace_ompt_mutex); + ensureFuncPtrLoaded( + "libomptarget_ompt_set_trace_ompt", &ompt_set_trace_ompt_fn); + assert(ompt_set_trace_ompt_fn && "libomptarget_ompt_set_trace_ompt loaded"); + return ompt_set_trace_ompt_fn(DeviceId, Enable, EventTy); +} + +OMPT_API_ROUTINE int +ompt_start_trace(ompt_device_t *Device, ompt_callback_buffer_request_t Request, + ompt_callback_buffer_complete_t Complete) { + DP("Executing ompt_start_trace\n"); + + int DeviceId = getDeviceId(Device); + if (DeviceId < 0) { + REPORT("Failed to start trace for Device=%p (Unknown device)\n", Device); + // Indicate failure + return 0; + } + + { + // Protect the function pointer + std::unique_lock Lock(ompt_start_trace_mutex); + + if (Request && Complete) { + llvm::omp::target::ompt::enableDeviceTracing(DeviceId); + // Enable asynchronous memory copy profiling + setOmptAsyncCopyProfile(/*Enable=*/true); + // Enable queue dispatch profiling + if (DeviceId >= 0) + setGlobalOmptKernelProfile(Device, /*Enable=*/1); + else + REPORT("May not enable kernel profiling for invalid device id=%d\n", + DeviceId); + } + + // Call libomptarget specific function + ensureFuncPtrLoaded( + "libomptarget_ompt_start_trace", &ompt_start_trace_fn); + assert(ompt_start_trace_fn && "libomptarget_ompt_start_trace loaded"); + } + return ompt_start_trace_fn(DeviceId, Request, Complete); +} + +OMPT_API_ROUTINE int ompt_flush_trace(ompt_device_t *Device) { + DP("Executing ompt_flush_trace\n"); + + std::unique_lock Lock(ompt_flush_trace_mutex); + ensureFuncPtrLoaded( + "libomptarget_ompt_flush_trace", &ompt_flush_trace_fn); + assert(ompt_flush_trace_fn && "libomptarget_ompt_flush_trace loaded"); + return ompt_flush_trace_fn(getDeviceId(Device)); +} + +OMPT_API_ROUTINE int ompt_stop_trace(ompt_device_t *Device) { + DP("Executing ompt_stop_trace\n"); + + int DeviceId = getDeviceId(Device); + if (DeviceId < 0) { + REPORT("Failed to stop trace for Device=%p (Unknown device)\n", Device); + // Indicate failure + return 0; + } + + { + // Protect the function pointer + std::unique_lock Lock(ompt_stop_trace_mutex); + llvm::omp::target::ompt::disableDeviceTracing(DeviceId); + // Disable asynchronous memory copy profiling + setOmptAsyncCopyProfile(/*Enable=*/false); + // Disable queue dispatch profiling + if (DeviceId >= 0) + setGlobalOmptKernelProfile(Device, /*Enable=*/0); + else + REPORT("May not disable kernel profiling for invalid device id=%d\n", + DeviceId); + ensureFuncPtrLoaded( + "libomptarget_ompt_stop_trace", &ompt_stop_trace_fn); + assert(ompt_stop_trace_fn && "libomptarget_ompt_stop_trace loaded"); + } + return ompt_stop_trace_fn(DeviceId); +} + +OMPT_API_ROUTINE ompt_record_ompt_t * +ompt_get_record_ompt(ompt_buffer_t *Buffer, ompt_buffer_cursor_t CurrentPos) { + // TODO In debug mode, get the metadata associated with this buffer + // and assert that there are enough bytes for the current record + + // Currently, no synchronization required since a disjoint set of + // trace records is handed over to a thread. + + // Note that CurrentPos can be nullptr. In that case, we return + // nullptr. The tool has to handle that properly. + return (ompt_record_ompt_t *)CurrentPos; +} + +OMPT_API_ROUTINE int ompt_advance_buffer_cursor(ompt_device_t *Device, + ompt_buffer_t *Buffer, + size_t Size, + ompt_buffer_cursor_t CurrentPos, + ompt_buffer_cursor_t *NextPos) { + // Note: The input parameter size is unused here. It refers to the + // bytes returned in the corresponding callback. + // Advance can be called concurrently, so synchronize setting the + // function pointer. The actual libomptarget function does not need + // to be synchronized since it must be working on logically disjoint + // buffers. + std::unique_lock Lock(ompt_advance_buffer_cursor_mutex); + ensureFuncPtrLoaded( + "libomptarget_ompt_advance_buffer_cursor", + &ompt_advance_buffer_cursor_fn); + assert(ompt_advance_buffer_cursor_fn && + "libomptarget_ompt_advance_buffer_cursor loaded"); + return ompt_advance_buffer_cursor_fn(Device, Buffer, Size, CurrentPos, + NextPos); +} + +OMPT_API_ROUTINE ompt_record_t +ompt_get_record_type(ompt_buffer_t *Buffer, ompt_buffer_cursor_t CurrentPos) { + std::unique_lock Lock(ompt_get_record_type_mutex); + ensureFuncPtrLoaded( + "libomptarget_ompt_get_record_type", &ompt_get_record_type_fn); + assert(ompt_get_record_type_fn && "libomptarget_ompt_get_record_type loaded"); + return ompt_get_record_type_fn(Buffer, CurrentPos); +} + +OMPT_API_ROUTINE ompt_device_time_t +ompt_get_device_time(ompt_device_t *Device) { + DP("Executing ompt_get_device_time\n"); + return getSystemTimestampInNs(); +} + +OMPT_API_ROUTINE double ompt_translate_time(ompt_device_t *Device, + ompt_device_time_t DeviceTime) { + // Translate a device time to a meaningful timepoint in host time + // We do not need to account for clock-skew / drift. So simple linear + // translation using the host to device rate we obtained. + double TranslatedTime = DeviceTime * HostToDeviceSlope + HostToDeviceOffset; + DP("D2H translated time: %f\n", TranslatedTime); + + return TranslatedTime; +} + +void llvm::omp::target::ompt::setOmptTimestamp(uint64_t StartTime, + uint64_t EndTime) { + std::unique_lock Lock(ompt_set_timestamp_mutex); + ensureFuncPtrLoaded( + "libomptarget_ompt_set_timestamp", &ompt_set_timestamp_fn); + // No need to hold a lock + ompt_set_timestamp_fn(StartTime, EndTime); +} + +void llvm::omp::target::ompt::setOmptHostToDeviceRate(double Slope, + double Offset) { + HostToDeviceSlope = Slope; + HostToDeviceOffset = Offset; +} + +void llvm::omp::target::ompt::setOmptGrantedNumTeams(uint64_t NumTeams) { + std::unique_lock Lock(ompt_set_granted_teams_mutex); + ensureFuncPtrLoaded( + "libomptarget_ompt_set_granted_teams", &ompt_set_granted_teams_fn); + // No need to hold a lock + ompt_set_granted_teams_fn(NumTeams); +} + +ompt_interface_fn_t llvm::omp::target::ompt::lookupDeviceTracingFn( + const char *InterfaceFunctionName) { +#define compareAgainst(AvailableFunction) \ + if (strcmp(InterfaceFunctionName, #AvailableFunction) == 0) \ + return (ompt_interface_fn_t)AvailableFunction; + + FOREACH_OMPT_DEVICE_TRACING_FN(compareAgainst); +#undef compareAgainst + + DP("Warning: Could not find requested function '%s'\n", + InterfaceFunctionName); + return (ompt_interface_fn_t) nullptr; +} + +#pragma pop_macro("DEBUG_PREFIX") + +#endif // OMPT_SUPPORT diff --git a/offload/plugins-nextgen/common/include/Emissary.h b/offload/plugins-nextgen/common/include/Emissary.h new file mode 100644 index 0000000000000..4480ed9eb5506 --- /dev/null +++ b/offload/plugins-nextgen/common/include/Emissary.h @@ -0,0 +1,281 @@ +//===-- offload/plugins-nextgen/common/include/Emissary.h ------ C++ ------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Defines emissary helper functions. This include is only used for host +// compilation. +// +//===----------------------------------------------------------------------===// + +#ifndef OFFLOAD_EMISSARY_H +#define OFFLOAD_EMISSARY_H + +#include "../../../../openmp/device/include/EmissaryIds.h" + +extern "C" { + +/// Called by rpc after receiving emissary argument buffer +emis_return_t Emissary(char *data); + +/// Called by Emissary for all Fortrt emissary functions +emis_return_t EmissaryFortrt(char *data, emisArgBuf_t *ab); + +/// Called by Emissary for all misc print functions +emis_return_t EmissaryPrint(char *data, emisArgBuf_t *ab); + +/// Called by Emissary for all MPI emissary API functions +__attribute((weak)) emis_return_t EmissaryMPI(char *data, emisArgBuf_t *ab, + emis_argptr_t *arg[MAXVARGS]); + +/// Called by Emissary for all HDF5 Emissary API functions +__attribute((weak)) emis_return_t EmissaryHDF5(char *data, emisArgBuf_t *ab, + emis_argptr_t *arg[MAXVARGS]); + +/// Support externally supplied emissary API +__attribute((weak)) emis_return_t EmissaryReserve(char *data, emisArgBuf_t *ab, + emis_argptr_t *arg[MAXVARGS]); + +/// Called by Emissary to build the emisArgBuf_t structure from the emissary +/// data buffer sent to the CPU by rpc. This buffer is created by clang CodeGen +/// when variadic function _emissary_exec(...) is encountered when compiling +// /the device stub for each emissary function. +void emisExtractArgBuf(char *buf, emisArgBuf_t *ab); + +/// Get uint32 value extended to uint64_t value from a char ptr +uint64_t getuint32(char *val); +/// Get uint64_t value from a char ptr +uint64_t getuint64(char *val); +/// Get a function pointer from a char ptr +void *getfnptr(char *val); + +/// Builds the array of pointers passed to V_ functions +uint32_t EmissaryBuildVargs(int NumArgs, char *keyptr, char *dataptr, + char *strptr, unsigned long long *data_not_used, + emis_argptr_t *a[MAXVARGS]); + +} // end extern "C" + +/// Call the associated V_ function +template +extern T EmissaryCallFnptr(uint32_t NumArgs, void *fnptr, + emis_argptr_t *a[MAXVARGS]); + +// Error return codes (deprecated) +typedef enum service_rc { + _RC_SUCCESS = 0, + _RC_STATUS_UNKNOWN = 1, + _RC_STATUS_ERROR = 2, + _RC_STATUS_TERMINATE = 3, + _RC_DATA_USED_ERROR = 4, + _RC_ADDINT_ERROR = 5, + _RC_ADDFLOAT_ERROR = 6, + _RC_ADDSTRING_ERROR = 7, + _RC_UNSUPPORTED_ID_ERROR = 8, + _RC_INVALID_ID_ERROR = 9, + _RC_ERROR_INVALID_REQUEST = 10, + _RC_EXCEED_MAXVARGS_ERROR = 11, + _RC_INVALIDSERVICE_ERROR = 12, + _RC_ERROR_MEMFREE = 13, + _RC_ERROR_CONSUMER_ACTIVE = 14, + _RC_ERROR_CONSUMER_INACTIVE = 15, + _RC_ERROR_CONSUMER_LAUNCH_FAILED = 16, + _RC_ERROR_SERVICE_UNKNOWN = 17, + _RC_ERROR_INCORRECT_ALIGNMENT = 18, + _RC_ERROR_NULLPTR = 19, + _RC_ERROR_WRONGVERSION = 20, + _RC_ERROR_OLDHOSTVERSIONMOD = 21, + _RC_ERROR_HSAFAIL = 22, + _RC_ERROR_ZEROPACKETS = 23, + _RC_ERROR_ALIGNMENT = 24, +} service_rc; + +// We would like to get llvm typeID enum from Type.h. e.g. +// #include ".../llvm/include/llvm/IR/Type.h" +// But we cannot include LLVM headers in a runtime function. +// So we a have a manual copy of llvm TypeID enum from Type.h +// The codegen for _emissary_exec puts this ID in the key for +// each arg and the host runtime needs to decode this key. +enum TypeID { + // PrimitiveTypes + HalfTyID = 0, ///< 16-bit floating point type + BFloatTyID, ///< 16-bit floating point type (7-bit significand) + FloatTyID, ///< 32-bit floating point type + DoubleTyID, ///< 64-bit floating point type + X86_FP80TyID, ///< 80-bit floating point type (X87) + FP128TyID, ///< 128-bit floating point type (112-bit significand) + PPC_FP128TyID, ///< 128-bit floating point type (two 64-bits, PowerPC) + VoidTyID, ///< type with no size + LabelTyID, ///< Labels + MetadataTyID, ///< Metadata + X86_AMXTyID, ///< AMX vectors (8192 bits, X86 specific) + TokenTyID, ///< Tokens + + // Derived types... see DerivedTypes.h file. + IntegerTyID, ///< Arbitrary bit width integers + FunctionTyID, ///< Functions + PointerTyID, ///< Pointers + StructTyID, ///< Structures + ArrayTyID, ///< Arrays + FixedVectorTyID, ///< Fixed width SIMD vector type + ScalableVectorTyID, ///< Scalable SIMD vector type + TypedPointerTyID, ///< Typed pointer used by some GPU targets + TargetExtTyID, ///< Target extension type +}; + +template +extern T EmissaryCallFnptr(uint32_t NumArgs, void *fnptr, + emis_argptr_t *a[MAXVARGS]) { + T rv; + FT *vfnptr = (FT *)fnptr; + switch (NumArgs) { + case 1: + rv = (T)vfnptr(fnptr, a[0]); + break; + case 2: + rv = (T)vfnptr(fnptr, a[0], a[1]); + break; + case 3: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2]); + break; + case 4: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3]); + break; + case 5: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4]); + break; + case 6: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5]); + break; + case 7: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6]); + break; + case 8: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7]); + break; + case 9: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8]); + break; + case 10: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9]); + break; + case 11: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10]); + break; + case 12: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11]); + break; + case 13: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12]); + break; + case 14: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13]); + break; + case 15: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14]); + break; + case 16: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15]); + break; + case 17: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16]); + break; + case 18: + rv = + (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17]); + break; + case 19: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18]); + break; + case 20: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19]); + break; + case 21: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20]); + break; + case 22: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21]); + break; + case 23: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21], a[22]); + break; + case 24: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21], a[22], a[23]); + break; + case 25: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21], a[22], a[23], a[24]); + break; + case 26: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21], a[22], a[23], a[24], a[25]); + break; + case 27: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21], a[22], a[23], a[24], a[25], + a[26]); + break; + case 28: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21], a[22], a[23], a[24], a[25], + a[26], a[27]); + break; + case 29: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21], a[22], a[23], a[24], a[25], + a[26], a[27], a[28]); + break; + case 30: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21], a[22], a[23], a[24], a[25], + a[26], a[27], a[28], a[29]); + break; + case 31: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21], a[22], a[23], a[24], a[25], + a[26], a[27], a[28], a[29], a[30]); + break; + case 32: + rv = (T)vfnptr(fnptr, a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7], a[8], + a[9], a[10], a[11], a[12], a[13], a[14], a[15], a[16], a[17], + a[18], a[19], a[20], a[21], a[22], a[23], a[24], a[25], + a[26], a[27], a[28], a[29], a[30], a[31]); + break; + default: + rv = 0; + } + return rv; +} + +#endif // OFFLOAD_EMISSARY_H diff --git a/offload/plugins-nextgen/common/include/GenericProfiler.h b/offload/plugins-nextgen/common/include/GenericProfiler.h new file mode 100644 index 0000000000000..4df15c4f7b8be --- /dev/null +++ b/offload/plugins-nextgen/common/include/GenericProfiler.h @@ -0,0 +1,192 @@ +//===- GenericProfiler.h - GenericProfiler interface for use in Plugins ---===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// The GenericProfiler interface allows to implement profiler logic for various +// backends, such as OMPT or other tracing mechanisms. +// This enables the plugins to be agnostic of the actual high-level language +// that is implemented. +// +//===----------------------------------------------------------------------===// + +#ifndef OFFLOAD_PLUGINS_NEXTGEN_COMMON_INCLUDE_GENERICPROFILER_H +#define OFFLOAD_PLUGINS_NEXTGEN_COMMON_INCLUDE_GENERICPROFILER_H + +#include "Shared/APITypes.h" + +#include +#include +#include + +namespace llvm { +namespace omp { +namespace target { +namespace plugin { + +struct GenericDeviceTy; +struct GenericPluginTy; +class GenericProfilerTy; + +template +void callViaIndexSeq(FunT F, GenericProfilerTy *P, uint64_t StartNanos, + uint64_t EndNanos, std::tuple Args, + std::index_sequence) { + F(P, StartNanos, EndNanos, std::get(Args)...); +} + +template +void callViaUnpack(FunT F, GenericProfilerTy *P, uint64_t StartNanos, + uint64_t EndNanos, std::tuple Tup) { + callViaIndexSeq(F, P, StartNanos, EndNanos, Tup, + std::index_sequence_for{}); +} + +/*** + * Abstraction layer to implement different profiler backends. + * + * The plugins call into the GenericProfilerTy to handle the specific events + * with whatever specific backend was instantiated. For now, the supported + * backends are limited to an OMPT implementation. + */ +class GenericProfilerTy { +public: + GenericProfilerTy() = default; + virtual ~GenericProfilerTy() = default; + + /// Obtain a pointer to profiler-specific data, if any. + virtual void *getProfilerSpecificData() { return nullptr; } + + virtual bool isProfilingEnabled() { return false; } + + /// Set the factors which are used to interpolate the device clock compared to + /// the host clock. This follows a simple linear interpolation: Slope *